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100644 CodeVirtualizer/build/obj/xed-syntax-enum.c create mode 100644 CodeVirtualizer/build/obj/xed-syntax-enum.h create mode 100644 CodeVirtualizer/build/obj/xed3-operand-lu.c create mode 100644 CodeVirtualizer/build/obj/xed3-phash-lu-vv0.c create mode 100644 CodeVirtualizer/build/obj/xed3-phash-lu-vv1.c create mode 100644 CodeVirtualizer/build/obj/xed3-phash-lu-vv2.c create mode 100644 CodeVirtualizer/build/obj/xed3-phash-lu-vv3.c create mode 100644 CodeVirtualizer/build/obj/xed3_nt_cdicts.txt create mode 100644 CodeVirtualizer/x64/Debug/CodeVirtualizer.vcxproj.FileListAbsolute.txt diff --git a/CodeVirtualizer/Jit.cpp b/CodeVirtualizer/Jit.cpp index 0797690..1883222 100644 --- a/CodeVirtualizer/Jit.cpp +++ b/CodeVirtualizer/Jit.cpp @@ -212,6 +212,7 @@ PNATIVE_CODE_BLOCK JitEmitPostRipMov(PNATIVE_CODE_LINK Link, INT32 Delta) RipDelta += (FourByte - (Count - 1)) * DWORD_MOV_INST_LENGTH; RipDelta *= (-1); RipDelta += Delta; + ZeroValue = rand(); if (!JitEmitRipRelativeMovD(Block, RipDelta, (PUCHAR)&ZeroValue)) { NcDeleteBlock(Block); @@ -228,6 +229,7 @@ PNATIVE_CODE_BLOCK JitEmitPostRipMov(PNATIVE_CODE_LINK Link, INT32 Delta) RipDelta += WORD_MOV_INST_LENGTH; RipDelta *= (-1); RipDelta += Delta; + ZeroValue = rand(); if (!JitEmitRipRelativeMovW(Block, RipDelta, (PUCHAR)&ZeroValue)) { NcDeleteBlock(Block); @@ -244,6 +246,7 @@ PNATIVE_CODE_BLOCK JitEmitPostRipMov(PNATIVE_CODE_LINK Link, INT32 Delta) RipDelta += BYTE_MOV_INST_LENGTH; RipDelta *= (-1); RipDelta += Delta; + ZeroValue = rand(); if (!JitEmitRipRelativeMovB(Block, RipDelta, (PUCHAR)&ZeroValue)) { NcDeleteBlock(Block); diff --git a/CodeVirtualizer/NativeCode.cpp b/CodeVirtualizer/NativeCode.cpp index cddfa30..af44937 100644 --- a/CodeVirtualizer/NativeCode.cpp +++ b/CodeVirtualizer/NativeCode.cpp @@ -138,6 +138,7 @@ ULONG NcGenUnusedLabelId(PNATIVE_CODE_BLOCK Block) ULONG ReturnLabelId = rand(); while (StdFind(Block->LabelIds.begin(), Block->LabelIds.end(), ReturnLabelId) != Block->LabelIds.end()) ReturnLabelId = rand(); + Block->LabelIds.push_back(ReturnLabelId); return ReturnLabelId; } @@ -156,9 +157,7 @@ VOID NcFixLabelsForBlocks(PNATIVE_CODE_BLOCK Block1, PNATIVE_CODE_BLOCK Block2) { if ((T->Flags & CODE_FLAG_IS_LABEL) && StdFind(Block1->LabelIds.begin(), Block1->LabelIds.end(), T->Label) != Block1->LabelIds.end()) { - ULONG Lid = NcGenUnusedLabelId(Block1); - NcChangeLabelId(Block2, T->Label, Lid); - Block1->LabelIds.push_back(Lid); + NcChangeLabelId(Block2, T->Label, NcGenUnusedLabelId(Block1)); } } } diff --git a/CodeVirtualizer/build/obj/.mbuild.hash.xeddecgen b/CodeVirtualizer/build/obj/.mbuild.hash.xeddecgen new file mode 100644 index 0000000000000000000000000000000000000000..da34e77629f8ee4601e47ade56a848febce5aed1 GIT binary patch literal 9413 zcma)?*>0Q3c7=11+gxOxgA6A~BMCb-5APD7QMIeeW*||DMETeO0^|X7sk}^{E?@l= zfBsZkwoe}z?S{BnwTHFWTBZN_-T(c+-~7(G`kj>VN#(=iYXA_x+(9+D?vN z?)$DEo^F5s`11Ty@-8c7L~GTfG-pGzZnWm2ios|zRO->j^78zbUypQK?w3G17MqP2 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z>Q2<`Yex~oDYlMa9%Cc=d5VXZsq;#jtXU+gLQsIJ*rq&LWzRaW)nK#dc6#7_&DcR&QWqUH1oog15mSbOL9F$U*9g2u;1`L&_1+#8 zclU2P%s-^i;LCc3u>nvFtNmziqW+BNHJgCO7Jj)&tLH3g&T6;sYu9pFoPo>|tqaHa zQ&;jm5eA37ge@jv+_l~ya$BSN+&Mcj_My=tpf6**?}d`vP&cUfRQE%hldy%=_1zsTNTcI0q)hQXF_!Wmpum=v;RN zVNMI(4LG-&vL0sp*jmyg+R~(HEX0`XI^zm(40MKBGoeKbJ1uVy{ZF>jRPBsDN14fw z-`ec8zl(3i7AuTh$cfT+rn`-DOfUL<4H*QBX%P%D0Upb(bowi0=DNdj@*S4Vm0fPH zGgrJI27_D!lUXJjY-PbT3!no9H8!^bEyJM^(b-L#@Guts-5c7CuOhEx*o)iL~n!BVPwk$ z8JZGwAEN3!BLYPL7sY2`?OXrqp`+iwI1jt-CTG@pU=RWKDl@F8 z>rfQyr;?sjMEx9%=r)}Pom&fWLFwM!UkhpA*sU;FFaZPr;7~?L@Or}6%~XZNBzlmJ zwmqvmDR1B*sbhd+-IB!5U*GK(ds^SUovtQuvB`@JT0R`V_MIbXU_o zwdrne?NYnl{`ry7QWlfVv$GB2fR#)(Ra#gu6LL`*ToKDN5CRdos?pBb(!^-DXG|;> zNS5IH1@F!b+KA~Q2SYKg47)c4;{|A;a<$lHOE{B&4&ocSP)SM@_#+;t1yBms9^JP9 Re1dj@Ws6~uID7y8{|AptTQdLv literal 0 HcmV?d00001 diff --git a/CodeVirtualizer/build/obj/DEC-ERR.txt b/CodeVirtualizer/build/obj/DEC-ERR.txt new file mode 100644 index 0000000..f5c3492 --- /dev/null +++ b/CodeVirtualizer/build/obj/DEC-ERR.txt @@ -0,0 +1,2 @@ +[WARNING] isa_set referenced by chip model hierarchy, but not used by any instructions: 3DNOW_PREFETCH +[WARNING] isa_set referenced by chip model hierarchy, but not used by any instructions: PREFETCHW diff --git a/CodeVirtualizer/build/obj/DEC-OUT.txt b/CodeVirtualizer/build/obj/DEC-OUT.txt new file mode 100644 index 0000000..2045b33 --- /dev/null +++ b/CodeVirtualizer/build/obj/DEC-OUT.txt @@ -0,0 +1,13264 @@ +Opening output files +FE:EMIT_FILE obj/xed-operand-ctype-enum.txt +FE:EMIT_FILE obj/xed-operand-ctype-enum.c +FE:EMIT_FILE obj/xed-operand-ctype-enum.h +FE:EMIT_FILE obj/xed-operand-ctype-map.h +FE:EMIT_FILE obj/xed-operand-ctype-map.c +LER: Comparing YMM0 and ZMM0 for XMM0 + taking new wider version +LER: Comparing YMM1 and ZMM1 for XMM1 + taking new wider version +LER: Comparing YMM2 and ZMM2 for XMM2 + taking new wider version +LER: Comparing YMM3 and ZMM3 for XMM3 + taking new wider version +LER: Comparing YMM4 and ZMM4 for XMM4 + taking new wider version +LER: Comparing YMM5 and ZMM5 for XMM5 + taking new wider version +LER: Comparing YMM6 and ZMM6 for XMM6 + taking new wider version +LER: Comparing YMM7 and ZMM7 for XMM7 + taking new wider version +LER: Comparing YMM8 and ZMM8 for XMM8 + taking new wider version +LER: Comparing YMM9 and ZMM9 for XMM9 + taking new wider version +LER: Comparing YMM10 and ZMM10 for XMM10 + taking new wider version +LER: Comparing YMM11 and ZMM11 for XMM11 + taking new wider version +LER: Comparing YMM12 and ZMM12 for XMM12 + taking new wider version +LER: Comparing YMM13 and ZMM13 for XMM13 + taking new wider version +LER: Comparing YMM14 and ZMM14 for XMM14 + taking new wider version +LER: Comparing YMM15 and ZMM15 for XMM15 + taking new wider version +LER: Comparing YMM0 and ZMM0 for YMM0 + taking new wider version +LER: Comparing YMM1 and ZMM1 for YMM1 + taking new wider version +LER: Comparing YMM2 and ZMM2 for YMM2 + taking new wider version +LER: Comparing YMM3 and ZMM3 for YMM3 + taking new wider version +LER: Comparing YMM4 and ZMM4 for YMM4 + taking new wider version +LER: Comparing YMM5 and ZMM5 for YMM5 + taking new wider version +LER: Comparing YMM6 and ZMM6 for YMM6 + taking new wider version +LER: Comparing YMM7 and ZMM7 for YMM7 + taking new wider version +LER: Comparing YMM8 and ZMM8 for YMM8 + taking new wider version +LER: Comparing YMM9 and ZMM9 for YMM9 + taking new wider version +LER: Comparing YMM10 and ZMM10 for YMM10 + taking new wider version +LER: Comparing YMM11 and ZMM11 for YMM11 + taking new wider version +LER: Comparing YMM12 and ZMM12 for YMM12 + taking new wider version +LER: Comparing YMM13 and ZMM13 for YMM13 + taking new wider version +LER: Comparing YMM14 and ZMM14 for YMM14 + taking new wider version +LER: Comparing YMM15 and ZMM15 for YMM15 + taking new wider version +[RGROUPS] ['BNDCFG', 'BNDSTAT', 'BOUND', 'CR', 'DR', 'FLAGS', 'GPR16', 'GPR32', 'GPR64', 'GPR8', 'GPR8h', 'INVALID', 'IP', 'MASK', 'MMX', 'MSR', 'MXCSR', 'PSEUDO', 'PSEUDOX87', 'SR', 'TMP', 'TREG', 'UIF', 'X87', 'XCR', 'XMM', 'YMM', 'ZMM'] +FE:EMIT_FILE obj/xed-reg-enum.txt +FE:EMIT_FILE obj/xed-reg-enum.c +FE:EMIT_FILE obj/xed-reg-enum.h +FE:EMIT_FILE obj/xed-reg-class-enum.txt +FE:EMIT_FILE obj/xed-reg-class-enum.c +FE:EMIT_FILE obj/xed-reg-class-enum.h +FE:EMIT_FILE obj/xed-init-reg-class.c +FE:EMIT_FILE obj/xed-operand-width-enum.txt +FE:EMIT_FILE obj/xed-operand-width-enum.c +FE:EMIT_FILE obj/xed-operand-width-enum.h +FE:EMIT_FILE obj/xed-init-width.c +Adding scalable width: ASZ +Adding scalable width: SSZ +Adding scalable width: P +Adding scalable width: P2 +Adding scalable width: S +Adding scalable width: V +Adding scalable width: Y +Adding scalable width: Z +Adding scalable width: SPW8 +Adding scalable width: SPW +Adding scalable width: SPW5 +Adding scalable width: SPW3 +Adding scalable width: SPW2 +MAKING ELEMENT BASE TYPE ENUM +FE:EMIT_FILE obj/xed-operand-element-type-enum.c +FE:EMIT_FILE obj/xed-operand-element-type-enum.h +FE:EMIT_FILE obj/xed-operand-element-xtype-enum.txt +FE:EMIT_FILE obj/xed-operand-element-xtype-enum.c +FE:EMIT_FILE obj/xed-operand-element-xtype-enum.h +FE:EMIT_FILE obj/xed-init-operand-type-mappings.c +FE:EMIT_FILE obj/xed-init-pointer-names.h +FE:EMIT_FILE obj/xed-init-pointer-names.c +Reading state bits +Done reading state bits +Reading structured input +Reading Instructions (ISA) input +============================================= +Creating a generator 0 +============================================= +ALines (lines before reading input) = 75476 +read_input 0 +NONTERMINAL: ISA notype +Adding ISA to nonterminal dict +Nonterminal ISA():: +Nonterminal name ISA +read_flat_input 0 +Hit a nonterminal, returning at: REMOVE_SEGMENT():: +BLines (lines remaining after reading input) = 75474 +============================================= +Creating a generator 1 +============================================= +ALines (lines before reading input) = 75474 +read_input 1 +NONTERMINAL: REMOVE_SEGMENT notype +Adding REMOVE_SEGMENT to nonterminal dict +Nonterminal REMOVE_SEGMENT():: +Nonterminal name REMOVE_SEGMENT +read_flat_input 1 +Hit a nonterminal, returning at: PREFIXES():: +BLines (lines remaining after reading input) = 75470 +============================================= +Creating a generator 2 +============================================= +ALines (lines before reading input) = 75470 +read_input 4 +NONTERMINAL: PREFIXES notype +Adding PREFIXES to nonterminal dict +Nonterminal PREFIXES():: +Nonterminal name PREFIXES +read_flat_input 4 +Hit a nonterminal, returning at: BRANCH_HINT():: +BLines (lines remaining after reading input) = 75422 +============================================= +Creating a generator 3 +============================================= +ALines (lines before reading input) = 75422 +read_input 50 +NONTERMINAL: BRANCH_HINT notype +Adding BRANCH_HINT to nonterminal dict +Nonterminal BRANCH_HINT():: +Nonterminal name BRANCH_HINT +read_flat_input 50 +Hit a nonterminal, returning at: CET_NO_TRACK():: +BLines (lines remaining after reading input) = 75418 +============================================= +Creating a generator 4 +============================================= +ALines (lines before reading input) = 75418 +read_input 53 +NONTERMINAL: CET_NO_TRACK notype +Adding CET_NO_TRACK to nonterminal dict +Nonterminal CET_NO_TRACK():: +Nonterminal name CET_NO_TRACK +read_flat_input 53 +Hit a nonterminal, returning at: xed_reg_enum_t ArAX():: +BLines (lines remaining after reading input) = 75414 +============================================= +Creating a generator 5 +============================================= +ALines (lines before reading input) = 75414 +read_input 56 +NONTERMINAL: ArAX type= xed_reg_enum_t +Adding ArAX to nonterminal dict +Nonterminal xed_reg_enum_t ArAX():: +Nonterminal name ArAX +read_flat_input 56 +Hit a nonterminal, returning at: xed_reg_enum_t ArBX():: +BLines (lines remaining after reading input) = 75410 +============================================= +Creating a generator 6 +============================================= +ALines (lines before reading input) = 75410 +read_input 59 +NONTERMINAL: ArBX type= xed_reg_enum_t +Adding ArBX to nonterminal dict +Nonterminal xed_reg_enum_t ArBX():: +Nonterminal name ArBX +read_flat_input 59 +Hit a nonterminal, returning at: xed_reg_enum_t ArCX():: +BLines (lines remaining after reading input) = 75406 +============================================= +Creating a generator 7 +============================================= +ALines (lines before reading input) = 75406 +read_input 62 +NONTERMINAL: ArCX type= xed_reg_enum_t +Adding ArCX to nonterminal dict +Nonterminal xed_reg_enum_t ArCX():: +Nonterminal name ArCX +read_flat_input 62 +Hit a nonterminal, returning at: xed_reg_enum_t ArDX():: +BLines (lines remaining after reading input) = 75402 +============================================= +Creating a generator 8 +============================================= +ALines (lines before reading input) = 75402 +read_input 65 +NONTERMINAL: ArDX type= xed_reg_enum_t +Adding ArDX to nonterminal dict +Nonterminal xed_reg_enum_t ArDX():: +Nonterminal name ArDX +read_flat_input 65 +Hit a nonterminal, returning at: xed_reg_enum_t ArSI():: +BLines (lines remaining after reading input) = 75398 +============================================= +Creating a generator 9 +============================================= +ALines (lines before reading input) = 75398 +read_input 68 +NONTERMINAL: ArSI type= xed_reg_enum_t +Adding ArSI to nonterminal dict +Nonterminal xed_reg_enum_t ArSI():: +Nonterminal name ArSI +read_flat_input 68 +Hit a nonterminal, returning at: xed_reg_enum_t ArDI():: +BLines (lines remaining after reading input) = 75394 +============================================= +Creating a generator 10 +============================================= +ALines (lines before reading input) = 75394 +read_input 71 +NONTERMINAL: ArDI type= xed_reg_enum_t +Adding ArDI to nonterminal dict +Nonterminal xed_reg_enum_t ArDI():: +Nonterminal name ArDI +read_flat_input 71 +Hit a nonterminal, returning at: xed_reg_enum_t ArSP():: +BLines (lines remaining after reading input) = 75390 +============================================= +Creating a generator 11 +============================================= +ALines (lines before reading input) = 75390 +read_input 74 +NONTERMINAL: ArSP type= xed_reg_enum_t +Adding ArSP to nonterminal dict +Nonterminal xed_reg_enum_t ArSP():: +Nonterminal name ArSP +read_flat_input 74 +Hit a nonterminal, returning at: xed_reg_enum_t ArBP():: +BLines (lines remaining after reading input) = 75386 +============================================= +Creating a generator 12 +============================================= +ALines (lines before reading input) = 75386 +read_input 77 +NONTERMINAL: ArBP type= xed_reg_enum_t +Adding ArBP to nonterminal dict +Nonterminal xed_reg_enum_t ArBP():: +Nonterminal name ArBP +read_flat_input 77 +Hit a nonterminal, returning at: xed_reg_enum_t SrSP():: +BLines (lines remaining after reading input) = 75382 +============================================= +Creating a generator 13 +============================================= +ALines (lines before reading input) = 75382 +read_input 80 +NONTERMINAL: SrSP type= xed_reg_enum_t +Adding SrSP to nonterminal dict +Nonterminal xed_reg_enum_t SrSP():: +Nonterminal name SrSP +read_flat_input 80 +Hit a nonterminal, returning at: xed_reg_enum_t SrBP():: +BLines (lines remaining after reading input) = 75378 +============================================= +Creating a generator 14 +============================================= +ALines (lines before reading input) = 75378 +read_input 83 +NONTERMINAL: SrBP type= xed_reg_enum_t +Adding SrBP to nonterminal dict +Nonterminal xed_reg_enum_t SrBP():: +Nonterminal name SrBP +read_flat_input 83 +Hit a nonterminal, returning at: xed_reg_enum_t Ar8():: +BLines (lines remaining after reading input) = 75374 +============================================= +Creating a generator 15 +============================================= +ALines (lines before reading input) = 75374 +read_input 86 +NONTERMINAL: Ar8 type= xed_reg_enum_t +Adding Ar8 to nonterminal dict +Nonterminal xed_reg_enum_t Ar8():: +Nonterminal name Ar8 +read_flat_input 86 +Hit a nonterminal, returning at: xed_reg_enum_t Ar9():: +BLines (lines remaining after reading input) = 75370 +============================================= +Creating a generator 16 +============================================= +ALines (lines before reading input) = 75370 +read_input 89 +NONTERMINAL: Ar9 type= xed_reg_enum_t +Adding Ar9 to nonterminal dict +Nonterminal xed_reg_enum_t Ar9():: +Nonterminal name Ar9 +read_flat_input 89 +Hit a nonterminal, returning at: xed_reg_enum_t Ar10():: +BLines (lines remaining after reading input) = 75366 +============================================= +Creating a generator 17 +============================================= +ALines (lines before reading input) = 75366 +read_input 92 +NONTERMINAL: Ar10 type= xed_reg_enum_t +Adding Ar10 to nonterminal dict +Nonterminal xed_reg_enum_t Ar10():: +Nonterminal name Ar10 +read_flat_input 92 +Hit a nonterminal, returning at: xed_reg_enum_t Ar11():: +BLines (lines remaining after reading input) = 75362 +============================================= +Creating a generator 18 +============================================= +ALines (lines before reading input) = 75362 +read_input 95 +NONTERMINAL: Ar11 type= xed_reg_enum_t +Adding Ar11 to nonterminal dict +Nonterminal xed_reg_enum_t Ar11():: +Nonterminal name Ar11 +read_flat_input 95 +Hit a nonterminal, returning at: xed_reg_enum_t Ar12():: +BLines (lines remaining after reading input) = 75358 +============================================= +Creating a generator 19 +============================================= +ALines (lines before reading input) = 75358 +read_input 98 +NONTERMINAL: Ar12 type= xed_reg_enum_t +Adding Ar12 to nonterminal dict +Nonterminal xed_reg_enum_t Ar12():: +Nonterminal name Ar12 +read_flat_input 98 +Hit a nonterminal, returning at: xed_reg_enum_t Ar13():: +BLines (lines remaining after reading input) = 75354 +============================================= +Creating a generator 20 +============================================= +ALines (lines before reading input) = 75354 +read_input 101 +NONTERMINAL: Ar13 type= xed_reg_enum_t +Adding Ar13 to nonterminal dict +Nonterminal xed_reg_enum_t Ar13():: +Nonterminal name Ar13 +read_flat_input 101 +Hit a nonterminal, returning at: xed_reg_enum_t Ar14():: +BLines (lines remaining after reading input) = 75350 +============================================= +Creating a generator 21 +============================================= +ALines (lines before reading input) = 75350 +read_input 104 +NONTERMINAL: Ar14 type= xed_reg_enum_t +Adding Ar14 to nonterminal dict +Nonterminal xed_reg_enum_t Ar14():: +Nonterminal name Ar14 +read_flat_input 104 +Hit a nonterminal, returning at: xed_reg_enum_t Ar15():: +BLines (lines remaining after reading input) = 75346 +============================================= +Creating a generator 22 +============================================= +ALines (lines before reading input) = 75346 +read_input 107 +NONTERMINAL: Ar15 type= xed_reg_enum_t +Adding Ar15 to nonterminal dict +Nonterminal xed_reg_enum_t Ar15():: +Nonterminal name Ar15 +read_flat_input 107 +Hit a nonterminal, returning at: xed_reg_enum_t rIP():: +BLines (lines remaining after reading input) = 75342 +============================================= +Creating a generator 23 +============================================= +ALines (lines before reading input) = 75342 +read_input 110 +NONTERMINAL: rIP type= xed_reg_enum_t +Adding rIP to nonterminal dict +Nonterminal xed_reg_enum_t rIP():: +Nonterminal name rIP +read_flat_input 110 +Hit a nonterminal, returning at: xed_reg_enum_t rIPa():: +BLines (lines remaining after reading input) = 75338 +============================================= +Creating a generator 24 +============================================= +ALines (lines before reading input) = 75338 +read_input 113 +NONTERMINAL: rIPa type= xed_reg_enum_t +Adding rIPa to nonterminal dict +Nonterminal xed_reg_enum_t rIPa():: +Nonterminal name rIPa +read_flat_input 113 +Hit a nonterminal, returning at: xed_reg_enum_t OeAX():: +BLines (lines remaining after reading input) = 75335 +============================================= +Creating a generator 25 +============================================= +ALines (lines before reading input) = 75335 +read_input 115 +NONTERMINAL: OeAX type= xed_reg_enum_t +Adding OeAX to nonterminal dict +Nonterminal xed_reg_enum_t OeAX():: +Nonterminal name OeAX +read_flat_input 115 +Hit a nonterminal, returning at: xed_reg_enum_t OrAX():: +BLines (lines remaining after reading input) = 75331 +============================================= +Creating a generator 26 +============================================= +ALines (lines before reading input) = 75331 +read_input 118 +NONTERMINAL: OrAX type= xed_reg_enum_t +Adding OrAX to nonterminal dict +Nonterminal xed_reg_enum_t OrAX():: +Nonterminal name OrAX +read_flat_input 118 +Hit a nonterminal, returning at: xed_reg_enum_t OrDX():: +BLines (lines remaining after reading input) = 75327 +============================================= +Creating a generator 27 +============================================= +ALines (lines before reading input) = 75327 +read_input 121 +NONTERMINAL: OrDX type= xed_reg_enum_t +Adding OrDX to nonterminal dict +Nonterminal xed_reg_enum_t OrDX():: +Nonterminal name OrDX +read_flat_input 121 +Hit a nonterminal, returning at: xed_reg_enum_t OrCX():: +BLines (lines remaining after reading input) = 75323 +============================================= +Creating a generator 28 +============================================= +ALines (lines before reading input) = 75323 +read_input 124 +NONTERMINAL: OrCX type= xed_reg_enum_t +Adding OrCX to nonterminal dict +Nonterminal xed_reg_enum_t OrCX():: +Nonterminal name OrCX +read_flat_input 124 +Hit a nonterminal, returning at: xed_reg_enum_t OrBX():: +BLines (lines remaining after reading input) = 75319 +============================================= +Creating a generator 29 +============================================= +ALines (lines before reading input) = 75319 +read_input 127 +NONTERMINAL: OrBX type= xed_reg_enum_t +Adding OrBX to nonterminal dict +Nonterminal xed_reg_enum_t OrBX():: +Nonterminal name OrBX +read_flat_input 127 +Hit a nonterminal, returning at: xed_reg_enum_t OrSP():: +BLines (lines remaining after reading input) = 75315 +============================================= +Creating a generator 30 +============================================= +ALines (lines before reading input) = 75315 +read_input 130 +NONTERMINAL: OrSP type= xed_reg_enum_t +Adding OrSP to nonterminal dict +Nonterminal xed_reg_enum_t OrSP():: +Nonterminal name OrSP +read_flat_input 130 +Hit a nonterminal, returning at: xed_reg_enum_t OrBP():: +BLines (lines remaining after reading input) = 75311 +============================================= +Creating a generator 31 +============================================= +ALines (lines before reading input) = 75311 +read_input 133 +NONTERMINAL: OrBP type= xed_reg_enum_t +Adding OrBP to nonterminal dict +Nonterminal xed_reg_enum_t OrBP():: +Nonterminal name OrBP +read_flat_input 133 +Hit a nonterminal, returning at: xed_reg_enum_t rFLAGS():: +BLines (lines remaining after reading input) = 75307 +============================================= +Creating a generator 32 +============================================= +ALines (lines before reading input) = 75307 +read_input 136 +NONTERMINAL: rFLAGS type= xed_reg_enum_t +Adding rFLAGS to nonterminal dict +Nonterminal xed_reg_enum_t rFLAGS():: +Nonterminal name rFLAGS +read_flat_input 136 +Hit a nonterminal, returning at: xed_reg_enum_t MMX_R():: +BLines (lines remaining after reading input) = 75303 +============================================= +Creating a generator 33 +============================================= +ALines (lines before reading input) = 75303 +read_input 139 +NONTERMINAL: MMX_R type= xed_reg_enum_t +Adding MMX_R to nonterminal dict +Nonterminal xed_reg_enum_t MMX_R():: +Nonterminal name MMX_R +read_flat_input 139 +Hit a nonterminal, returning at: xed_reg_enum_t MMX_B():: +BLines (lines remaining after reading input) = 75294 +============================================= +Creating a generator 34 +============================================= +ALines (lines before reading input) = 75294 +read_input 147 +NONTERMINAL: MMX_B type= xed_reg_enum_t +Adding MMX_B to nonterminal dict +Nonterminal xed_reg_enum_t MMX_B():: +Nonterminal name MMX_B +read_flat_input 147 +Hit a nonterminal, returning at: xed_reg_enum_t GPRv_R():: +BLines (lines remaining after reading input) = 75285 +============================================= +Creating a generator 35 +============================================= +ALines (lines before reading input) = 75285 +read_input 155 +NONTERMINAL: GPRv_R type= xed_reg_enum_t +Adding GPRv_R to nonterminal dict +Nonterminal xed_reg_enum_t GPRv_R():: +Nonterminal name GPRv_R +read_flat_input 155 +Hit a nonterminal, returning at: xed_reg_enum_t GPRv_SB():: +BLines (lines remaining after reading input) = 75281 +============================================= +Creating a generator 36 +============================================= +ALines (lines before reading input) = 75281 +read_input 158 +NONTERMINAL: GPRv_SB type= xed_reg_enum_t +Adding GPRv_SB to nonterminal dict +Nonterminal xed_reg_enum_t GPRv_SB():: +Nonterminal name GPRv_SB +read_flat_input 158 +Hit a nonterminal, returning at: xed_reg_enum_t GPRz_R():: +BLines (lines remaining after reading input) = 75277 +============================================= +Creating a generator 37 +============================================= +ALines (lines before reading input) = 75277 +read_input 161 +NONTERMINAL: GPRz_R type= xed_reg_enum_t +Adding GPRz_R to nonterminal dict +Nonterminal xed_reg_enum_t GPRz_R():: +Nonterminal name GPRz_R +read_flat_input 161 +Hit a nonterminal, returning at: xed_reg_enum_t GPRv_B():: +BLines (lines remaining after reading input) = 75273 +============================================= +Creating a generator 38 +============================================= +ALines (lines before reading input) = 75273 +read_input 164 +NONTERMINAL: GPRv_B type= xed_reg_enum_t +Adding GPRv_B to nonterminal dict +Nonterminal xed_reg_enum_t GPRv_B():: +Nonterminal name GPRv_B +read_flat_input 164 +Hit a nonterminal, returning at: xed_reg_enum_t GPRz_B():: +BLines (lines remaining after reading input) = 75269 +============================================= +Creating a generator 39 +============================================= +ALines (lines before reading input) = 75269 +read_input 167 +NONTERMINAL: GPRz_B type= xed_reg_enum_t +Adding GPRz_B to nonterminal dict +Nonterminal xed_reg_enum_t GPRz_B():: +Nonterminal name GPRz_B +read_flat_input 167 +Hit a nonterminal, returning at: xed_reg_enum_t GPRy_B():: +BLines (lines remaining after reading input) = 75265 +============================================= +Creating a generator 40 +============================================= +ALines (lines before reading input) = 75265 +read_input 170 +NONTERMINAL: GPRy_B type= xed_reg_enum_t +Adding GPRy_B to nonterminal dict +Nonterminal xed_reg_enum_t GPRy_B():: +Nonterminal name GPRy_B +read_flat_input 170 +Hit a nonterminal, returning at: xed_reg_enum_t GPRy_R():: +BLines (lines remaining after reading input) = 75261 +============================================= +Creating a generator 41 +============================================= +ALines (lines before reading input) = 75261 +read_input 173 +NONTERMINAL: GPRy_R type= xed_reg_enum_t +Adding GPRy_R to nonterminal dict +Nonterminal xed_reg_enum_t GPRy_R():: +Nonterminal name GPRy_R +read_flat_input 173 +Hit a nonterminal, returning at: xed_reg_enum_t GPR64_R():: +BLines (lines remaining after reading input) = 75257 +============================================= +Creating a generator 42 +============================================= +ALines (lines before reading input) = 75257 +read_input 176 +NONTERMINAL: GPR64_R type= xed_reg_enum_t +Adding GPR64_R to nonterminal dict +Nonterminal xed_reg_enum_t GPR64_R():: +Nonterminal name GPR64_R +read_flat_input 176 +Hit a nonterminal, returning at: xed_reg_enum_t GPR64_B():: +BLines (lines remaining after reading input) = 75240 +============================================= +Creating a generator 43 +============================================= +ALines (lines before reading input) = 75240 +read_input 192 +NONTERMINAL: GPR64_B type= xed_reg_enum_t +Adding GPR64_B to nonterminal dict +Nonterminal xed_reg_enum_t GPR64_B():: +Nonterminal name GPR64_B +read_flat_input 192 +Hit a nonterminal, returning at: xed_reg_enum_t GPR64_SB():: +BLines (lines remaining after reading input) = 75223 +============================================= +Creating a generator 44 +============================================= +ALines (lines before reading input) = 75223 +read_input 208 +NONTERMINAL: GPR64_SB type= xed_reg_enum_t +Adding GPR64_SB to nonterminal dict +Nonterminal xed_reg_enum_t GPR64_SB():: +Nonterminal name GPR64_SB +read_flat_input 208 +Hit a nonterminal, returning at: xed_reg_enum_t GPR64_X():: +BLines (lines remaining after reading input) = 75206 +============================================= +Creating a generator 45 +============================================= +ALines (lines before reading input) = 75206 +read_input 224 +NONTERMINAL: GPR64_X type= xed_reg_enum_t +Adding GPR64_X to nonterminal dict +Nonterminal xed_reg_enum_t GPR64_X():: +Nonterminal name GPR64_X +read_flat_input 224 +Hit a nonterminal, returning at: xed_reg_enum_t GPR32_R():: +BLines (lines remaining after reading input) = 75189 +============================================= +Creating a generator 46 +============================================= +ALines (lines before reading input) = 75189 +read_input 240 +NONTERMINAL: GPR32_R type= xed_reg_enum_t +Adding GPR32_R to nonterminal dict +Nonterminal xed_reg_enum_t GPR32_R():: +Nonterminal name GPR32_R +read_flat_input 240 +Hit a nonterminal, returning at: xed_reg_enum_t GPR32_B():: +BLines (lines remaining after reading input) = 75172 +============================================= +Creating a generator 47 +============================================= +ALines (lines before reading input) = 75172 +read_input 256 +NONTERMINAL: GPR32_B type= xed_reg_enum_t +Adding GPR32_B to nonterminal dict +Nonterminal xed_reg_enum_t GPR32_B():: +Nonterminal name GPR32_B +read_flat_input 256 +Hit a nonterminal, returning at: xed_reg_enum_t GPR32_SB():: +BLines (lines remaining after reading input) = 75155 +============================================= +Creating a generator 48 +============================================= +ALines (lines before reading input) = 75155 +read_input 272 +NONTERMINAL: GPR32_SB type= xed_reg_enum_t +Adding GPR32_SB to nonterminal dict +Nonterminal xed_reg_enum_t GPR32_SB():: +Nonterminal name GPR32_SB +read_flat_input 272 +Hit a nonterminal, returning at: xed_reg_enum_t GPR32_X():: +BLines (lines remaining after reading input) = 75138 +============================================= +Creating a generator 49 +============================================= +ALines (lines before reading input) = 75138 +read_input 288 +NONTERMINAL: GPR32_X type= xed_reg_enum_t +Adding GPR32_X to nonterminal dict +Nonterminal xed_reg_enum_t GPR32_X():: +Nonterminal name GPR32_X +read_flat_input 288 +Hit a nonterminal, returning at: xed_reg_enum_t GPR16_R():: +BLines (lines remaining after reading input) = 75121 +============================================= +Creating a generator 50 +============================================= +ALines (lines before reading input) = 75121 +read_input 304 +NONTERMINAL: GPR16_R type= xed_reg_enum_t +Adding GPR16_R to nonterminal dict +Nonterminal xed_reg_enum_t GPR16_R():: +Nonterminal name GPR16_R +read_flat_input 304 +Hit a nonterminal, returning at: xed_reg_enum_t GPR16_B():: +BLines (lines remaining after reading input) = 75104 +============================================= +Creating a generator 51 +============================================= +ALines (lines before reading input) = 75104 +read_input 320 +NONTERMINAL: GPR16_B type= xed_reg_enum_t +Adding GPR16_B to nonterminal dict +Nonterminal xed_reg_enum_t GPR16_B():: +Nonterminal name GPR16_B +read_flat_input 320 +Hit a nonterminal, returning at: xed_reg_enum_t GPR16_SB():: +BLines (lines remaining after reading input) = 75087 +============================================= +Creating a generator 52 +============================================= +ALines (lines before reading input) = 75087 +read_input 336 +NONTERMINAL: GPR16_SB type= xed_reg_enum_t +Adding GPR16_SB to nonterminal dict +Nonterminal xed_reg_enum_t GPR16_SB():: +Nonterminal name GPR16_SB +read_flat_input 336 +Hit a nonterminal, returning at: xed_reg_enum_t CR_R():: +BLines (lines remaining after reading input) = 75070 +============================================= +Creating a generator 53 +============================================= +ALines (lines before reading input) = 75070 +read_input 352 +NONTERMINAL: CR_R type= xed_reg_enum_t +Adding CR_R to nonterminal dict +Nonterminal xed_reg_enum_t CR_R():: +Nonterminal name CR_R +read_flat_input 352 +Hit a nonterminal, returning at: xed_reg_enum_t CR_B():: +BLines (lines remaining after reading input) = 75053 +============================================= +Creating a generator 54 +============================================= +ALines (lines before reading input) = 75053 +read_input 368 +NONTERMINAL: CR_B type= xed_reg_enum_t +Adding CR_B to nonterminal dict +Nonterminal xed_reg_enum_t CR_B():: +Nonterminal name CR_B +read_flat_input 368 +Hit a nonterminal, returning at: xed_reg_enum_t DR_R():: +BLines (lines remaining after reading input) = 75036 +============================================= +Creating a generator 55 +============================================= +ALines (lines before reading input) = 75036 +read_input 384 +NONTERMINAL: DR_R type= xed_reg_enum_t +Adding DR_R to nonterminal dict +Nonterminal xed_reg_enum_t DR_R():: +Nonterminal name DR_R +read_flat_input 384 +Hit a nonterminal, returning at: xed_reg_enum_t X87():: +BLines (lines remaining after reading input) = 75019 +============================================= +Creating a generator 56 +============================================= +ALines (lines before reading input) = 75019 +read_input 400 +NONTERMINAL: X87 type= xed_reg_enum_t +Adding X87 to nonterminal dict +Nonterminal xed_reg_enum_t X87():: +Nonterminal name X87 +read_flat_input 400 +Hit a nonterminal, returning at: xed_reg_enum_t SEG():: +BLines (lines remaining after reading input) = 75010 +============================================= +Creating a generator 57 +============================================= +ALines (lines before reading input) = 75010 +read_input 408 +NONTERMINAL: SEG type= xed_reg_enum_t +Adding SEG to nonterminal dict +Nonterminal xed_reg_enum_t SEG():: +Nonterminal name SEG +read_flat_input 408 +Hit a nonterminal, returning at: xed_reg_enum_t SEG_MOV():: +BLines (lines remaining after reading input) = 75001 +============================================= +Creating a generator 58 +============================================= +ALines (lines before reading input) = 75001 +read_input 416 +NONTERMINAL: SEG_MOV type= xed_reg_enum_t +Adding SEG_MOV to nonterminal dict +Nonterminal xed_reg_enum_t SEG_MOV():: +Nonterminal name SEG_MOV +read_flat_input 416 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_DSEG():: +BLines (lines remaining after reading input) = 74992 +============================================= +Creating a generator 59 +============================================= +ALines (lines before reading input) = 74992 +read_input 424 +NONTERMINAL: FINAL_DSEG type= xed_reg_enum_t +Adding FINAL_DSEG to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_DSEG():: +Nonterminal name FINAL_DSEG +read_flat_input 424 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_DSEG_NOT64():: +BLines (lines remaining after reading input) = 74988 +============================================= +Creating a generator 60 +============================================= +ALines (lines before reading input) = 74988 +read_input 427 +NONTERMINAL: FINAL_DSEG_NOT64 type= xed_reg_enum_t +Adding FINAL_DSEG_NOT64 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_DSEG_NOT64():: +Nonterminal name FINAL_DSEG_NOT64 +read_flat_input 427 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_DSEG_MODE64():: +BLines (lines remaining after reading input) = 74980 +============================================= +Creating a generator 61 +============================================= +ALines (lines before reading input) = 74980 +read_input 434 +NONTERMINAL: FINAL_DSEG_MODE64 type= xed_reg_enum_t +Adding FINAL_DSEG_MODE64 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_DSEG_MODE64():: +Nonterminal name FINAL_DSEG_MODE64 +read_flat_input 434 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_DSEG1():: +BLines (lines remaining after reading input) = 74972 +============================================= +Creating a generator 62 +============================================= +ALines (lines before reading input) = 74972 +read_input 441 +NONTERMINAL: FINAL_DSEG1 type= xed_reg_enum_t +Adding FINAL_DSEG1 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_DSEG1():: +Nonterminal name FINAL_DSEG1 +read_flat_input 441 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_DSEG1_NOT64():: +BLines (lines remaining after reading input) = 74968 +============================================= +Creating a generator 63 +============================================= +ALines (lines before reading input) = 74968 +read_input 444 +NONTERMINAL: FINAL_DSEG1_NOT64 type= xed_reg_enum_t +Adding FINAL_DSEG1_NOT64 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_DSEG1_NOT64():: +Nonterminal name FINAL_DSEG1_NOT64 +read_flat_input 444 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_DSEG1_MODE64():: +BLines (lines remaining after reading input) = 74960 +============================================= +Creating a generator 64 +============================================= +ALines (lines before reading input) = 74960 +read_input 451 +NONTERMINAL: FINAL_DSEG1_MODE64 type= xed_reg_enum_t +Adding FINAL_DSEG1_MODE64 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_DSEG1_MODE64():: +Nonterminal name FINAL_DSEG1_MODE64 +read_flat_input 451 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_ESEG():: +BLines (lines remaining after reading input) = 74952 +============================================= +Creating a generator 65 +============================================= +ALines (lines before reading input) = 74952 +read_input 458 +NONTERMINAL: FINAL_ESEG type= xed_reg_enum_t +Adding FINAL_ESEG to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_ESEG():: +Nonterminal name FINAL_ESEG +read_flat_input 458 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_ESEG1():: +BLines (lines remaining after reading input) = 74948 +============================================= +Creating a generator 66 +============================================= +ALines (lines before reading input) = 74948 +read_input 461 +NONTERMINAL: FINAL_ESEG1 type= xed_reg_enum_t +Adding FINAL_ESEG1 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_ESEG1():: +Nonterminal name FINAL_ESEG1 +read_flat_input 461 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_SSEG1():: +BLines (lines remaining after reading input) = 74944 +============================================= +Creating a generator 67 +============================================= +ALines (lines before reading input) = 74944 +read_input 464 +NONTERMINAL: FINAL_SSEG1 type= xed_reg_enum_t +Adding FINAL_SSEG1 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_SSEG1():: +Nonterminal name FINAL_SSEG1 +read_flat_input 464 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_SSEG0():: +BLines (lines remaining after reading input) = 74940 +============================================= +Creating a generator 68 +============================================= +ALines (lines before reading input) = 74940 +read_input 467 +NONTERMINAL: FINAL_SSEG0 type= xed_reg_enum_t +Adding FINAL_SSEG0 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_SSEG0():: +Nonterminal name FINAL_SSEG0 +read_flat_input 467 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_SSEG():: +BLines (lines remaining after reading input) = 74936 +============================================= +Creating a generator 69 +============================================= +ALines (lines before reading input) = 74936 +read_input 470 +NONTERMINAL: FINAL_SSEG type= xed_reg_enum_t +Adding FINAL_SSEG to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_SSEG():: +Nonterminal name FINAL_SSEG +read_flat_input 470 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_SSEG_NOT64():: +BLines (lines remaining after reading input) = 74932 +============================================= +Creating a generator 70 +============================================= +ALines (lines before reading input) = 74932 +read_input 473 +NONTERMINAL: FINAL_SSEG_NOT64 type= xed_reg_enum_t +Adding FINAL_SSEG_NOT64 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_SSEG_NOT64():: +Nonterminal name FINAL_SSEG_NOT64 +read_flat_input 473 +Hit a nonterminal, returning at: xed_reg_enum_t FINAL_SSEG_MODE64():: +BLines (lines remaining after reading input) = 74924 +============================================= +Creating a generator 71 +============================================= +ALines (lines before reading input) = 74924 +read_input 480 +NONTERMINAL: FINAL_SSEG_MODE64 type= xed_reg_enum_t +Adding FINAL_SSEG_MODE64 to nonterminal dict +Nonterminal xed_reg_enum_t FINAL_SSEG_MODE64():: +Nonterminal name FINAL_SSEG_MODE64 +read_flat_input 480 +Hit a nonterminal, returning at: xed_reg_enum_t GPR8_R():: +BLines (lines remaining after reading input) = 74916 +============================================= +Creating a generator 72 +============================================= +ALines (lines before reading input) = 74916 +read_input 487 +NONTERMINAL: GPR8_R type= xed_reg_enum_t +Adding GPR8_R to nonterminal dict +Nonterminal xed_reg_enum_t GPR8_R():: +Nonterminal name GPR8_R +read_flat_input 487 +Hit a nonterminal, returning at: xed_reg_enum_t GPR8_B():: +BLines (lines remaining after reading input) = 74895 +============================================= +Creating a generator 73 +============================================= +ALines (lines before reading input) = 74895 +read_input 507 +NONTERMINAL: GPR8_B type= xed_reg_enum_t +Adding GPR8_B to nonterminal dict +Nonterminal xed_reg_enum_t GPR8_B():: +Nonterminal name GPR8_B +read_flat_input 507 +Hit a nonterminal, returning at: xed_reg_enum_t GPR8_SB():: +BLines (lines remaining after reading input) = 74874 +============================================= +Creating a generator 74 +============================================= +ALines (lines before reading input) = 74874 +read_input 527 +NONTERMINAL: GPR8_SB type= xed_reg_enum_t +Adding GPR8_SB to nonterminal dict +Nonterminal xed_reg_enum_t GPR8_SB():: +Nonterminal name GPR8_SB +read_flat_input 527 +Hit a nonterminal, returning at: OSZ_NONTERM():: +BLines (lines remaining after reading input) = 74853 +============================================= +Creating a generator 75 +============================================= +ALines (lines before reading input) = 74853 +read_input 547 +NONTERMINAL: OSZ_NONTERM notype +Adding OSZ_NONTERM to nonterminal dict +Nonterminal OSZ_NONTERM():: +Nonterminal name OSZ_NONTERM +read_flat_input 547 +Hit a nonterminal, returning at: DF64():: +BLines (lines remaining after reading input) = 74844 +============================================= +Creating a generator 76 +============================================= +ALines (lines before reading input) = 74844 +read_input 555 +NONTERMINAL: DF64 notype +Adding DF64 to nonterminal dict +Nonterminal DF64():: +Nonterminal name DF64 +read_flat_input 555 +Hit a nonterminal, returning at: REFINING66():: +BLines (lines remaining after reading input) = 74837 +============================================= +Creating a generator 77 +============================================= +ALines (lines before reading input) = 74837 +read_input 561 +NONTERMINAL: REFINING66 notype +Adding REFINING66 to nonterminal dict +Nonterminal REFINING66():: +Nonterminal name REFINING66 +read_flat_input 561 +Hit a nonterminal, returning at: IGNORE66():: +BLines (lines remaining after reading input) = 74832 +============================================= +Creating a generator 78 +============================================= +ALines (lines before reading input) = 74832 +read_input 565 +NONTERMINAL: IGNORE66 notype +Adding IGNORE66 to nonterminal dict +Nonterminal IGNORE66():: +Nonterminal name IGNORE66 +read_flat_input 565 +Hit a nonterminal, returning at: IMMUNE66():: +BLines (lines remaining after reading input) = 74827 +============================================= +Creating a generator 79 +============================================= +ALines (lines before reading input) = 74827 +read_input 569 +NONTERMINAL: IMMUNE66 notype +Adding IMMUNE66 to nonterminal dict +Nonterminal IMMUNE66():: +Nonterminal name IMMUNE66 +read_flat_input 569 +Hit a nonterminal, returning at: CR_WIDTH():: +BLines (lines remaining after reading input) = 74822 +============================================= +Creating a generator 80 +============================================= +ALines (lines before reading input) = 74822 +read_input 573 +NONTERMINAL: CR_WIDTH notype +Adding CR_WIDTH to nonterminal dict +Nonterminal CR_WIDTH():: +Nonterminal name CR_WIDTH +read_flat_input 573 +Hit a nonterminal, returning at: IMMUNE66_LOOP64():: +BLines (lines remaining after reading input) = 74818 +============================================= +Creating a generator 81 +============================================= +ALines (lines before reading input) = 74818 +read_input 576 +NONTERMINAL: IMMUNE66_LOOP64 notype +Adding IMMUNE66_LOOP64 to nonterminal dict +Nonterminal IMMUNE66_LOOP64():: +Nonterminal name IMMUNE66_LOOP64 +read_flat_input 576 +Hit a nonterminal, returning at: IMMUNE_REXW():: +BLines (lines remaining after reading input) = 74814 +============================================= +Creating a generator 82 +============================================= +ALines (lines before reading input) = 74814 +read_input 579 +NONTERMINAL: IMMUNE_REXW notype +Adding IMMUNE_REXW to nonterminal dict +Nonterminal IMMUNE_REXW():: +Nonterminal name IMMUNE_REXW +read_flat_input 579 +Hit a nonterminal, returning at: FORCE64():: +BLines (lines remaining after reading input) = 74808 +============================================= +Creating a generator 83 +============================================= +ALines (lines before reading input) = 74808 +read_input 584 +NONTERMINAL: FORCE64 notype +Adding FORCE64 to nonterminal dict +Nonterminal FORCE64():: +Nonterminal name FORCE64 +read_flat_input 584 +Hit a nonterminal, returning at: ASZ_NONTERM():: +BLines (lines remaining after reading input) = 74805 +============================================= +Creating a generator 84 +============================================= +ALines (lines before reading input) = 74805 +read_input 585 +NONTERMINAL: ASZ_NONTERM notype +Adding ASZ_NONTERM to nonterminal dict +Nonterminal ASZ_NONTERM():: +Nonterminal name ASZ_NONTERM +read_flat_input 585 +Hit a nonterminal, returning at: ONE():: +BLines (lines remaining after reading input) = 74798 +============================================= +Creating a generator 85 +============================================= +ALines (lines before reading input) = 74798 +read_input 591 +NONTERMINAL: ONE notype +Adding ONE to nonterminal dict +Nonterminal ONE():: +Nonterminal name ONE +read_flat_input 591 +Hit a nonterminal, returning at: UIMMv():: +BLines (lines remaining after reading input) = 74794 +============================================= +Creating a generator 86 +============================================= +ALines (lines before reading input) = 74794 +read_input 594 +NONTERMINAL: UIMMv notype +Adding UIMMv to nonterminal dict +Nonterminal UIMMv():: +Nonterminal name UIMMv +read_flat_input 594 +Hit a nonterminal, returning at: SIMMz():: +BLines (lines remaining after reading input) = 74790 +============================================= +Creating a generator 87 +============================================= +ALines (lines before reading input) = 74790 +read_input 597 +NONTERMINAL: SIMMz notype +Adding SIMMz to nonterminal dict +Nonterminal SIMMz():: +Nonterminal name SIMMz +read_flat_input 597 +Hit a nonterminal, returning at: SIMM8():: +BLines (lines remaining after reading input) = 74786 +============================================= +Creating a generator 88 +============================================= +ALines (lines before reading input) = 74786 +read_input 600 +NONTERMINAL: SIMM8 notype +Adding SIMM8 to nonterminal dict +Nonterminal SIMM8():: +Nonterminal name SIMM8 +read_flat_input 600 +Hit a nonterminal, returning at: UIMM8():: +BLines (lines remaining after reading input) = 74784 +============================================= +Creating a generator 89 +============================================= +ALines (lines before reading input) = 74784 +read_input 601 +NONTERMINAL: UIMM8 notype +Adding UIMM8 to nonterminal dict +Nonterminal UIMM8():: +Nonterminal name UIMM8 +read_flat_input 601 +Hit a nonterminal, returning at: UIMM8_1():: +BLines (lines remaining after reading input) = 74782 +============================================= +Creating a generator 90 +============================================= +ALines (lines before reading input) = 74782 +read_input 602 +NONTERMINAL: UIMM8_1 notype +Adding UIMM8_1 to nonterminal dict +Nonterminal UIMM8_1():: +Nonterminal name UIMM8_1 +read_flat_input 602 +Hit a nonterminal, returning at: UIMM16():: +BLines (lines remaining after reading input) = 74780 +============================================= +Creating a generator 91 +============================================= +ALines (lines before reading input) = 74780 +read_input 603 +NONTERMINAL: UIMM16 notype +Adding UIMM16 to nonterminal dict +Nonterminal UIMM16():: +Nonterminal name UIMM16 +read_flat_input 603 +Hit a nonterminal, returning at: UIMM32():: +BLines (lines remaining after reading input) = 74778 +============================================= +Creating a generator 92 +============================================= +ALines (lines before reading input) = 74778 +read_input 604 +NONTERMINAL: UIMM32 notype +Adding UIMM32 to nonterminal dict +Nonterminal UIMM32():: +Nonterminal name UIMM32 +read_flat_input 604 +Hit a nonterminal, returning at: BRDISP8():: +BLines (lines remaining after reading input) = 74776 +============================================= +Creating a generator 93 +============================================= +ALines (lines before reading input) = 74776 +read_input 605 +NONTERMINAL: BRDISP8 notype +Adding BRDISP8 to nonterminal dict +Nonterminal BRDISP8():: +Nonterminal name BRDISP8 +read_flat_input 605 +Hit a nonterminal, returning at: BRDISP32():: +BLines (lines remaining after reading input) = 74774 +============================================= +Creating a generator 94 +============================================= +ALines (lines before reading input) = 74774 +read_input 606 +NONTERMINAL: BRDISP32 notype +Adding BRDISP32 to nonterminal dict +Nonterminal BRDISP32():: +Nonterminal name BRDISP32 +read_flat_input 606 +Hit a nonterminal, returning at: BRDISPz():: +BLines (lines remaining after reading input) = 74772 +============================================= +Creating a generator 95 +============================================= +ALines (lines before reading input) = 74772 +read_input 607 +NONTERMINAL: BRDISPz notype +Adding BRDISPz to nonterminal dict +Nonterminal BRDISPz():: +Nonterminal name BRDISPz +read_flat_input 607 +Hit a nonterminal, returning at: MEMDISPv():: +BLines (lines remaining after reading input) = 74768 +============================================= +Creating a generator 96 +============================================= +ALines (lines before reading input) = 74768 +read_input 610 +NONTERMINAL: MEMDISPv notype +Adding MEMDISPv to nonterminal dict +Nonterminal MEMDISPv():: +Nonterminal name MEMDISPv +read_flat_input 610 +Hit a nonterminal, returning at: MEMDISP32():: +BLines (lines remaining after reading input) = 74764 +============================================= +Creating a generator 97 +============================================= +ALines (lines before reading input) = 74764 +read_input 613 +NONTERMINAL: MEMDISP32 notype +Adding MEMDISP32 to nonterminal dict +Nonterminal MEMDISP32():: +Nonterminal name MEMDISP32 +read_flat_input 613 +Hit a nonterminal, returning at: MEMDISP16():: +BLines (lines remaining after reading input) = 74762 +============================================= +Creating a generator 98 +============================================= +ALines (lines before reading input) = 74762 +read_input 614 +NONTERMINAL: MEMDISP16 notype +Adding MEMDISP16 to nonterminal dict +Nonterminal MEMDISP16():: +Nonterminal name MEMDISP16 +read_flat_input 614 +Hit a nonterminal, returning at: MEMDISP8():: +BLines (lines remaining after reading input) = 74760 +============================================= +Creating a generator 99 +============================================= +ALines (lines before reading input) = 74760 +read_input 615 +NONTERMINAL: MEMDISP8 notype +Adding MEMDISP8 to nonterminal dict +Nonterminal MEMDISP8():: +Nonterminal name MEMDISP8 +read_flat_input 615 +Hit a nonterminal, returning at: MEMDISP():: +BLines (lines remaining after reading input) = 74758 +============================================= +Creating a generator 100 +============================================= +ALines (lines before reading input) = 74758 +read_input 616 +NONTERMINAL: MEMDISP notype +Adding MEMDISP to nonterminal dict +Nonterminal MEMDISP():: +Nonterminal name MEMDISP +read_flat_input 616 +Hit a nonterminal, returning at: MODRM():: +BLines (lines remaining after reading input) = 74753 +============================================= +Creating a generator 101 +============================================= +ALines (lines before reading input) = 74753 +read_input 620 +NONTERMINAL: MODRM notype +Adding MODRM to nonterminal dict +Nonterminal MODRM():: +Nonterminal name MODRM +read_flat_input 620 +Hit a nonterminal, returning at: MODRM64alt32():: +BLines (lines remaining after reading input) = 74746 +============================================= +Creating a generator 102 +============================================= +ALines (lines before reading input) = 74746 +read_input 626 +NONTERMINAL: MODRM64alt32 notype +Adding MODRM64alt32 to nonterminal dict +Nonterminal MODRM64alt32():: +Nonterminal name MODRM64alt32 +read_flat_input 626 +Hit a nonterminal, returning at: MODRM32():: +BLines (lines remaining after reading input) = 74697 +============================================= +Creating a generator 103 +============================================= +ALines (lines before reading input) = 74697 +read_input 674 +NONTERMINAL: MODRM32 notype +Adding MODRM32 to nonterminal dict +Nonterminal MODRM32():: +Nonterminal name MODRM32 +read_flat_input 674 +Hit a nonterminal, returning at: MODRM16():: +BLines (lines remaining after reading input) = 74672 +============================================= +Creating a generator 104 +============================================= +ALines (lines before reading input) = 74672 +read_input 698 +NONTERMINAL: MODRM16 notype +Adding MODRM16 to nonterminal dict +Nonterminal MODRM16():: +Nonterminal name MODRM16 +read_flat_input 698 +Hit a nonterminal, returning at: SIB():: +BLines (lines remaining after reading input) = 74647 +============================================= +Creating a generator 105 +============================================= +ALines (lines before reading input) = 74647 +read_input 722 +NONTERMINAL: SIB notype +Adding SIB to nonterminal dict +Nonterminal SIB():: +Nonterminal name SIB +read_flat_input 722 +Hit a nonterminal, returning at: SIB_BASE0():: +BLines (lines remaining after reading input) = 74582 +============================================= +Creating a generator 106 +============================================= +ALines (lines before reading input) = 74582 +read_input 786 +NONTERMINAL: SIB_BASE0 notype +Adding SIB_BASE0 to nonterminal dict +Nonterminal SIB_BASE0():: +Nonterminal name SIB_BASE0 +read_flat_input 786 +Hit a nonterminal, returning at: OVERRIDE_SEG0():: +BLines (lines remaining after reading input) = 74561 +============================================= +Creating a generator 107 +============================================= +ALines (lines before reading input) = 74561 +read_input 806 +NONTERMINAL: OVERRIDE_SEG0 notype +Adding OVERRIDE_SEG0 to nonterminal dict +Nonterminal OVERRIDE_SEG0():: +Nonterminal name OVERRIDE_SEG0 +read_flat_input 806 +Hit a nonterminal, returning at: OVERRIDE_SEG1():: +BLines (lines remaining after reading input) = 74557 +============================================= +Creating a generator 108 +============================================= +ALines (lines before reading input) = 74557 +read_input 809 +NONTERMINAL: OVERRIDE_SEG1 notype +Adding OVERRIDE_SEG1 to nonterminal dict +Nonterminal OVERRIDE_SEG1():: +Nonterminal name OVERRIDE_SEG1 +read_flat_input 809 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_R():: +BLines (lines remaining after reading input) = 74553 +============================================= +Creating a generator 109 +============================================= +ALines (lines before reading input) = 74553 +read_input 812 +NONTERMINAL: XMM_R type= xed_reg_enum_t +Adding XMM_R to nonterminal dict +Nonterminal xed_reg_enum_t XMM_R():: +Nonterminal name XMM_R +read_flat_input 812 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_R_32():: +BLines (lines remaining after reading input) = 74549 +============================================= +Creating a generator 110 +============================================= +ALines (lines before reading input) = 74549 +read_input 815 +NONTERMINAL: XMM_R_32 type= xed_reg_enum_t +Adding XMM_R_32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_R_32():: +Nonterminal name XMM_R_32 +read_flat_input 815 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_R_64():: +BLines (lines remaining after reading input) = 74540 +============================================= +Creating a generator 111 +============================================= +ALines (lines before reading input) = 74540 +read_input 823 +NONTERMINAL: XMM_R_64 type= xed_reg_enum_t +Adding XMM_R_64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_R_64():: +Nonterminal name XMM_R_64 +read_flat_input 823 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_B():: +BLines (lines remaining after reading input) = 74523 +============================================= +Creating a generator 112 +============================================= +ALines (lines before reading input) = 74523 +read_input 839 +NONTERMINAL: XMM_B type= xed_reg_enum_t +Adding XMM_B to nonterminal dict +Nonterminal xed_reg_enum_t XMM_B():: +Nonterminal name XMM_B +read_flat_input 839 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_B_32():: +BLines (lines remaining after reading input) = 74519 +============================================= +Creating a generator 113 +============================================= +ALines (lines before reading input) = 74519 +read_input 842 +NONTERMINAL: XMM_B_32 type= xed_reg_enum_t +Adding XMM_B_32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_B_32():: +Nonterminal name XMM_B_32 +read_flat_input 842 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_B_64():: +BLines (lines remaining after reading input) = 74510 +============================================= +Creating a generator 114 +============================================= +ALines (lines before reading input) = 74510 +read_input 850 +NONTERMINAL: XMM_B_64 type= xed_reg_enum_t +Adding XMM_B_64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_B_64():: +Nonterminal name XMM_B_64 +read_flat_input 850 +Hit a nonterminal, returning at: AVX_SPLITTER():: +BLines (lines remaining after reading input) = 74493 +============================================= +Creating a generator 115 +============================================= +ALines (lines before reading input) = 74493 +read_input 866 +NONTERMINAL: AVX_SPLITTER notype +Adding AVX_SPLITTER to nonterminal dict +Nonterminal AVX_SPLITTER():: +Nonterminal name AVX_SPLITTER +read_flat_input 866 +Hit a nonterminal, returning at: EVEX_SPLITTER():: +BLines (lines remaining after reading input) = 74491 +============================================= +Creating a generator 116 +============================================= +ALines (lines before reading input) = 74491 +read_input 867 +NONTERMINAL: EVEX_SPLITTER notype +Adding EVEX_SPLITTER to nonterminal dict +Nonterminal EVEX_SPLITTER():: +Nonterminal name EVEX_SPLITTER +read_flat_input 867 +Hit a nonterminal, returning at: BND_R_CHECK():: +BLines (lines remaining after reading input) = 74489 +============================================= +Creating a generator 117 +============================================= +ALines (lines before reading input) = 74489 +read_input 868 +NONTERMINAL: BND_R_CHECK notype +Adding BND_R_CHECK to nonterminal dict +Nonterminal BND_R_CHECK():: +Nonterminal name BND_R_CHECK +read_flat_input 868 +Hit a nonterminal, returning at: BND_B_CHECK():: +BLines (lines remaining after reading input) = 74472 +============================================= +Creating a generator 118 +============================================= +ALines (lines before reading input) = 74472 +read_input 884 +NONTERMINAL: BND_B_CHECK notype +Adding BND_B_CHECK to nonterminal dict +Nonterminal BND_B_CHECK():: +Nonterminal name BND_B_CHECK +read_flat_input 884 +Hit a nonterminal, returning at: xed_reg_enum_t BND_R():: +BLines (lines remaining after reading input) = 74455 +============================================= +Creating a generator 119 +============================================= +ALines (lines before reading input) = 74455 +read_input 900 +NONTERMINAL: BND_R type= xed_reg_enum_t +Adding BND_R to nonterminal dict +Nonterminal xed_reg_enum_t BND_R():: +Nonterminal name BND_R +read_flat_input 900 +Hit a nonterminal, returning at: xed_reg_enum_t BND_B():: +BLines (lines remaining after reading input) = 74438 +============================================= +Creating a generator 120 +============================================= +ALines (lines before reading input) = 74438 +read_input 916 +NONTERMINAL: BND_B type= xed_reg_enum_t +Adding BND_B to nonterminal dict +Nonterminal xed_reg_enum_t BND_B():: +Nonterminal name BND_B +read_flat_input 916 +Hit a nonterminal, returning at: xed_reg_enum_t A_GPR_R():: +BLines (lines remaining after reading input) = 74421 +============================================= +Creating a generator 121 +============================================= +ALines (lines before reading input) = 74421 +read_input 932 +NONTERMINAL: A_GPR_R type= xed_reg_enum_t +Adding A_GPR_R to nonterminal dict +Nonterminal xed_reg_enum_t A_GPR_R():: +Nonterminal name A_GPR_R +read_flat_input 932 +Hit a nonterminal, returning at: xed_reg_enum_t A_GPR_B():: +BLines (lines remaining after reading input) = 74404 +============================================= +Creating a generator 122 +============================================= +ALines (lines before reading input) = 74404 +read_input 948 +NONTERMINAL: A_GPR_B type= xed_reg_enum_t +Adding A_GPR_B to nonterminal dict +Nonterminal xed_reg_enum_t A_GPR_B():: +Nonterminal name A_GPR_B +read_flat_input 948 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_SE():: +BLines (lines remaining after reading input) = 74387 +============================================= +Creating a generator 123 +============================================= +ALines (lines before reading input) = 74387 +read_input 964 +NONTERMINAL: XMM_SE type= xed_reg_enum_t +Adding XMM_SE to nonterminal dict +Nonterminal xed_reg_enum_t XMM_SE():: +Nonterminal name XMM_SE +read_flat_input 964 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_SE64():: +BLines (lines remaining after reading input) = 74383 +============================================= +Creating a generator 124 +============================================= +ALines (lines before reading input) = 74383 +read_input 967 +NONTERMINAL: XMM_SE64 type= xed_reg_enum_t +Adding XMM_SE64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_SE64():: +Nonterminal name XMM_SE64 +read_flat_input 967 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_SE32():: +BLines (lines remaining after reading input) = 74366 +============================================= +Creating a generator 125 +============================================= +ALines (lines before reading input) = 74366 +read_input 983 +NONTERMINAL: XMM_SE32 type= xed_reg_enum_t +Adding XMM_SE32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_SE32():: +Nonterminal name XMM_SE32 +read_flat_input 983 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_SE():: +BLines (lines remaining after reading input) = 74349 +============================================= +Creating a generator 126 +============================================= +ALines (lines before reading input) = 74349 +read_input 999 +NONTERMINAL: YMM_SE type= xed_reg_enum_t +Adding YMM_SE to nonterminal dict +Nonterminal xed_reg_enum_t YMM_SE():: +Nonterminal name YMM_SE +read_flat_input 999 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_SE64():: +BLines (lines remaining after reading input) = 74345 +============================================= +Creating a generator 127 +============================================= +ALines (lines before reading input) = 74345 +read_input 1002 +NONTERMINAL: YMM_SE64 type= xed_reg_enum_t +Adding YMM_SE64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_SE64():: +Nonterminal name YMM_SE64 +read_flat_input 1002 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_SE32():: +BLines (lines remaining after reading input) = 74328 +============================================= +Creating a generator 128 +============================================= +ALines (lines before reading input) = 74328 +read_input 1018 +NONTERMINAL: YMM_SE32 type= xed_reg_enum_t +Adding YMM_SE32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_SE32():: +Nonterminal name YMM_SE32 +read_flat_input 1018 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_N():: +BLines (lines remaining after reading input) = 74311 +============================================= +Creating a generator 129 +============================================= +ALines (lines before reading input) = 74311 +read_input 1034 +NONTERMINAL: XMM_N type= xed_reg_enum_t +Adding XMM_N to nonterminal dict +Nonterminal xed_reg_enum_t XMM_N():: +Nonterminal name XMM_N +read_flat_input 1034 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_N_32():: +BLines (lines remaining after reading input) = 74307 +============================================= +Creating a generator 130 +============================================= +ALines (lines before reading input) = 74307 +read_input 1037 +NONTERMINAL: XMM_N_32 type= xed_reg_enum_t +Adding XMM_N_32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_N_32():: +Nonterminal name XMM_N_32 +read_flat_input 1037 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_N_64():: +BLines (lines remaining after reading input) = 74298 +============================================= +Creating a generator 131 +============================================= +ALines (lines before reading input) = 74298 +read_input 1045 +NONTERMINAL: XMM_N_64 type= xed_reg_enum_t +Adding XMM_N_64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_N_64():: +Nonterminal name XMM_N_64 +read_flat_input 1045 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_N():: +BLines (lines remaining after reading input) = 74281 +============================================= +Creating a generator 132 +============================================= +ALines (lines before reading input) = 74281 +read_input 1061 +NONTERMINAL: YMM_N type= xed_reg_enum_t +Adding YMM_N to nonterminal dict +Nonterminal xed_reg_enum_t YMM_N():: +Nonterminal name YMM_N +read_flat_input 1061 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_N_32():: +BLines (lines remaining after reading input) = 74277 +============================================= +Creating a generator 133 +============================================= +ALines (lines before reading input) = 74277 +read_input 1064 +NONTERMINAL: YMM_N_32 type= xed_reg_enum_t +Adding YMM_N_32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_N_32():: +Nonterminal name YMM_N_32 +read_flat_input 1064 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_N_64():: +BLines (lines remaining after reading input) = 74268 +============================================= +Creating a generator 134 +============================================= +ALines (lines before reading input) = 74268 +read_input 1072 +NONTERMINAL: YMM_N_64 type= xed_reg_enum_t +Adding YMM_N_64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_N_64():: +Nonterminal name YMM_N_64 +read_flat_input 1072 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_R():: +BLines (lines remaining after reading input) = 74251 +============================================= +Creating a generator 135 +============================================= +ALines (lines before reading input) = 74251 +read_input 1088 +NONTERMINAL: YMM_R type= xed_reg_enum_t +Adding YMM_R to nonterminal dict +Nonterminal xed_reg_enum_t YMM_R():: +Nonterminal name YMM_R +read_flat_input 1088 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_R_32():: +BLines (lines remaining after reading input) = 74247 +============================================= +Creating a generator 136 +============================================= +ALines (lines before reading input) = 74247 +read_input 1091 +NONTERMINAL: YMM_R_32 type= xed_reg_enum_t +Adding YMM_R_32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_R_32():: +Nonterminal name YMM_R_32 +read_flat_input 1091 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_R_64():: +BLines (lines remaining after reading input) = 74238 +============================================= +Creating a generator 137 +============================================= +ALines (lines before reading input) = 74238 +read_input 1099 +NONTERMINAL: YMM_R_64 type= xed_reg_enum_t +Adding YMM_R_64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_R_64():: +Nonterminal name YMM_R_64 +read_flat_input 1099 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_B():: +BLines (lines remaining after reading input) = 74221 +============================================= +Creating a generator 138 +============================================= +ALines (lines before reading input) = 74221 +read_input 1115 +NONTERMINAL: YMM_B type= xed_reg_enum_t +Adding YMM_B to nonterminal dict +Nonterminal xed_reg_enum_t YMM_B():: +Nonterminal name YMM_B +read_flat_input 1115 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_B_32():: +BLines (lines remaining after reading input) = 74217 +============================================= +Creating a generator 139 +============================================= +ALines (lines before reading input) = 74217 +read_input 1118 +NONTERMINAL: YMM_B_32 type= xed_reg_enum_t +Adding YMM_B_32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_B_32():: +Nonterminal name YMM_B_32 +read_flat_input 1118 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_B_64():: +BLines (lines remaining after reading input) = 74208 +============================================= +Creating a generator 140 +============================================= +ALines (lines before reading input) = 74208 +read_input 1126 +NONTERMINAL: YMM_B_64 type= xed_reg_enum_t +Adding YMM_B_64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_B_64():: +Nonterminal name YMM_B_64 +read_flat_input 1126 +Hit a nonterminal, returning at: AVX_SPLITTER():: +BLines (lines remaining after reading input) = 74191 +============================================= +Creating a generator 141 +============================================= +ALines (lines before reading input) = 74191 +read_input 1142 +NONTERMINAL: AVX_SPLITTER notype +FOUND OLD PARSER FOR AVX_SPLITTER +Nonterminal AVX_SPLITTER():: +Nonterminal name AVX_SPLITTER +read_flat_input 1142 +Hit a nonterminal, returning at: SE_IMM8():: +BLines (lines remaining after reading input) = 74188 +============================================= +Creating a generator 141 +============================================= +ALines (lines before reading input) = 74188 +read_input 1144 +NONTERMINAL: SE_IMM8 notype +Adding SE_IMM8 to nonterminal dict +Nonterminal SE_IMM8():: +Nonterminal name SE_IMM8 +read_flat_input 1144 +Hit a nonterminal, returning at: VMODRM_YMM():: +BLines (lines remaining after reading input) = 74186 +============================================= +Creating a generator 142 +============================================= +ALines (lines before reading input) = 74186 +read_input 1145 +NONTERMINAL: VMODRM_YMM notype +Adding VMODRM_YMM to nonterminal dict +Nonterminal VMODRM_YMM():: +Nonterminal name VMODRM_YMM +read_flat_input 1145 +Hit a nonterminal, returning at: VMODRM_XMM():: +BLines (lines remaining after reading input) = 74182 +============================================= +Creating a generator 143 +============================================= +ALines (lines before reading input) = 74182 +read_input 1148 +NONTERMINAL: VMODRM_XMM notype +Adding VMODRM_XMM to nonterminal dict +Nonterminal VMODRM_XMM():: +Nonterminal name VMODRM_XMM +read_flat_input 1148 +Hit a nonterminal, returning at: VSIB_YMM():: +BLines (lines remaining after reading input) = 74178 +============================================= +Creating a generator 144 +============================================= +ALines (lines before reading input) = 74178 +read_input 1151 +NONTERMINAL: VSIB_YMM notype +Adding VSIB_YMM to nonterminal dict +Nonterminal VSIB_YMM():: +Nonterminal name VSIB_YMM +read_flat_input 1151 +Hit a nonterminal, returning at: VSIB_XMM():: +BLines (lines remaining after reading input) = 74173 +============================================= +Creating a generator 145 +============================================= +ALines (lines before reading input) = 74173 +read_input 1155 +NONTERMINAL: VSIB_XMM notype +Adding VSIB_XMM to nonterminal dict +Nonterminal VSIB_XMM():: +Nonterminal name VSIB_XMM +read_flat_input 1155 +Hit a nonterminal, returning at: xed_reg_enum_t VSIB_INDEX_YMM():: +BLines (lines remaining after reading input) = 74168 +============================================= +Creating a generator 146 +============================================= +ALines (lines before reading input) = 74168 +read_input 1159 +NONTERMINAL: VSIB_INDEX_YMM type= xed_reg_enum_t +Adding VSIB_INDEX_YMM to nonterminal dict +Nonterminal xed_reg_enum_t VSIB_INDEX_YMM():: +Nonterminal name VSIB_INDEX_YMM +read_flat_input 1159 +Hit a nonterminal, returning at: xed_reg_enum_t VSIB_INDEX_XMM():: +BLines (lines remaining after reading input) = 74151 +============================================= +Creating a generator 147 +============================================= +ALines (lines before reading input) = 74151 +read_input 1175 +NONTERMINAL: VSIB_INDEX_XMM type= xed_reg_enum_t +Adding VSIB_INDEX_XMM to nonterminal dict +Nonterminal xed_reg_enum_t VSIB_INDEX_XMM():: +Nonterminal name VSIB_INDEX_XMM +read_flat_input 1175 +Hit a nonterminal, returning at: VSIB_BASE():: +BLines (lines remaining after reading input) = 74134 +============================================= +Creating a generator 148 +============================================= +ALines (lines before reading input) = 74134 +read_input 1191 +NONTERMINAL: VSIB_BASE notype +Adding VSIB_BASE to nonterminal dict +Nonterminal VSIB_BASE():: +Nonterminal name VSIB_BASE +read_flat_input 1191 +Hit a nonterminal, returning at: xed_reg_enum_t VGPRy_R():: +BLines (lines remaining after reading input) = 74115 +============================================= +Creating a generator 149 +============================================= +ALines (lines before reading input) = 74115 +read_input 1209 +NONTERMINAL: VGPRy_R type= xed_reg_enum_t +Adding VGPRy_R to nonterminal dict +Nonterminal xed_reg_enum_t VGPRy_R():: +Nonterminal name VGPRy_R +read_flat_input 1209 +Hit a nonterminal, returning at: xed_reg_enum_t VGPRy_B():: +BLines (lines remaining after reading input) = 74111 +============================================= +Creating a generator 150 +============================================= +ALines (lines before reading input) = 74111 +read_input 1212 +NONTERMINAL: VGPRy_B type= xed_reg_enum_t +Adding VGPRy_B to nonterminal dict +Nonterminal xed_reg_enum_t VGPRy_B():: +Nonterminal name VGPRy_B +read_flat_input 1212 +Hit a nonterminal, returning at: xed_reg_enum_t VGPRy_N():: +BLines (lines remaining after reading input) = 74107 +============================================= +Creating a generator 151 +============================================= +ALines (lines before reading input) = 74107 +read_input 1215 +NONTERMINAL: VGPRy_N type= xed_reg_enum_t +Adding VGPRy_N to nonterminal dict +Nonterminal xed_reg_enum_t VGPRy_N():: +Nonterminal name VGPRy_N +read_flat_input 1215 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_N():: +BLines (lines remaining after reading input) = 74103 +============================================= +Creating a generator 152 +============================================= +ALines (lines before reading input) = 74103 +read_input 1218 +NONTERMINAL: VGPR32_N type= xed_reg_enum_t +Adding VGPR32_N to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_N():: +Nonterminal name VGPR32_N +read_flat_input 1218 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_B():: +BLines (lines remaining after reading input) = 74099 +============================================= +Creating a generator 153 +============================================= +ALines (lines before reading input) = 74099 +read_input 1221 +NONTERMINAL: VGPR32_B type= xed_reg_enum_t +Adding VGPR32_B to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_B():: +Nonterminal name VGPR32_B +read_flat_input 1221 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_R():: +BLines (lines remaining after reading input) = 74095 +============================================= +Creating a generator 154 +============================================= +ALines (lines before reading input) = 74095 +read_input 1224 +NONTERMINAL: VGPR32_R type= xed_reg_enum_t +Adding VGPR32_R to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_R():: +Nonterminal name VGPR32_R +read_flat_input 1224 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_N_32():: +BLines (lines remaining after reading input) = 74091 +============================================= +Creating a generator 155 +============================================= +ALines (lines before reading input) = 74091 +read_input 1227 +NONTERMINAL: VGPR32_N_32 type= xed_reg_enum_t +Adding VGPR32_N_32 to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_N_32():: +Nonterminal name VGPR32_N_32 +read_flat_input 1227 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_N_64():: +BLines (lines remaining after reading input) = 74082 +============================================= +Creating a generator 156 +============================================= +ALines (lines before reading input) = 74082 +read_input 1235 +NONTERMINAL: VGPR32_N_64 type= xed_reg_enum_t +Adding VGPR32_N_64 to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_N_64():: +Nonterminal name VGPR32_N_64 +read_flat_input 1235 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR64_N():: +BLines (lines remaining after reading input) = 74065 +============================================= +Creating a generator 157 +============================================= +ALines (lines before reading input) = 74065 +read_input 1251 +NONTERMINAL: VGPR64_N type= xed_reg_enum_t +Adding VGPR64_N to nonterminal dict +Nonterminal xed_reg_enum_t VGPR64_N():: +Nonterminal name VGPR64_N +read_flat_input 1251 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_R_32():: +BLines (lines remaining after reading input) = 74048 +============================================= +Creating a generator 158 +============================================= +ALines (lines before reading input) = 74048 +read_input 1267 +NONTERMINAL: VGPR32_R_32 type= xed_reg_enum_t +Adding VGPR32_R_32 to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_R_32():: +Nonterminal name VGPR32_R_32 +read_flat_input 1267 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_R_64():: +BLines (lines remaining after reading input) = 74039 +============================================= +Creating a generator 159 +============================================= +ALines (lines before reading input) = 74039 +read_input 1275 +NONTERMINAL: VGPR32_R_64 type= xed_reg_enum_t +Adding VGPR32_R_64 to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_R_64():: +Nonterminal name VGPR32_R_64 +read_flat_input 1275 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR64_R():: +BLines (lines remaining after reading input) = 74022 +============================================= +Creating a generator 160 +============================================= +ALines (lines before reading input) = 74022 +read_input 1291 +NONTERMINAL: VGPR64_R type= xed_reg_enum_t +Adding VGPR64_R to nonterminal dict +Nonterminal xed_reg_enum_t VGPR64_R():: +Nonterminal name VGPR64_R +read_flat_input 1291 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_B_32():: +BLines (lines remaining after reading input) = 74005 +============================================= +Creating a generator 161 +============================================= +ALines (lines before reading input) = 74005 +read_input 1307 +NONTERMINAL: VGPR32_B_32 type= xed_reg_enum_t +Adding VGPR32_B_32 to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_B_32():: +Nonterminal name VGPR32_B_32 +read_flat_input 1307 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR32_B_64():: +BLines (lines remaining after reading input) = 73996 +============================================= +Creating a generator 162 +============================================= +ALines (lines before reading input) = 73996 +read_input 1315 +NONTERMINAL: VGPR32_B_64 type= xed_reg_enum_t +Adding VGPR32_B_64 to nonterminal dict +Nonterminal xed_reg_enum_t VGPR32_B_64():: +Nonterminal name VGPR32_B_64 +read_flat_input 1315 +Hit a nonterminal, returning at: xed_reg_enum_t VGPR64_B():: +BLines (lines remaining after reading input) = 73979 +============================================= +Creating a generator 163 +============================================= +ALines (lines before reading input) = 73979 +read_input 1331 +NONTERMINAL: VGPR64_B type= xed_reg_enum_t +Adding VGPR64_B to nonterminal dict +Nonterminal xed_reg_enum_t VGPR64_B():: +Nonterminal name VGPR64_B +read_flat_input 1331 +Hit a nonterminal, returning at: NELEM_TUPLE1_4X():: +BLines (lines remaining after reading input) = 73962 +============================================= +Creating a generator 164 +============================================= +ALines (lines before reading input) = 73962 +read_input 1347 +NONTERMINAL: NELEM_TUPLE1_4X notype +Adding NELEM_TUPLE1_4X to nonterminal dict +Nonterminal NELEM_TUPLE1_4X():: +Nonterminal name NELEM_TUPLE1_4X +read_flat_input 1347 +Hit a nonterminal, returning at: EVEX_SPLITTER():: +BLines (lines remaining after reading input) = 73958 +============================================= +Creating a generator 165 +============================================= +ALines (lines before reading input) = 73958 +read_input 1350 +NONTERMINAL: EVEX_SPLITTER notype +FOUND OLD PARSER FOR EVEX_SPLITTER +Nonterminal EVEX_SPLITTER():: +Nonterminal name EVEX_SPLITTER +read_flat_input 1350 +Hit a nonterminal, returning at: AVX512_ROUND():: +BLines (lines remaining after reading input) = 73954 +============================================= +Creating a generator 165 +============================================= +ALines (lines before reading input) = 73954 +read_input 1353 +NONTERMINAL: AVX512_ROUND notype +Adding AVX512_ROUND to nonterminal dict +Nonterminal AVX512_ROUND():: +Nonterminal name AVX512_ROUND +read_flat_input 1353 +Hit a nonterminal, returning at: SAE():: +BLines (lines remaining after reading input) = 73949 +============================================= +Creating a generator 166 +============================================= +ALines (lines before reading input) = 73949 +read_input 1357 +NONTERMINAL: SAE notype +Adding SAE to nonterminal dict +Nonterminal SAE():: +Nonterminal name SAE +read_flat_input 1357 +Hit a nonterminal, returning at: ESIZE_128_BITS():: +BLines (lines remaining after reading input) = 73946 +============================================= +Creating a generator 167 +============================================= +ALines (lines before reading input) = 73946 +read_input 1359 +NONTERMINAL: ESIZE_128_BITS notype +Adding ESIZE_128_BITS to nonterminal dict +Nonterminal ESIZE_128_BITS():: +Nonterminal name ESIZE_128_BITS +read_flat_input 1359 +Hit a nonterminal, returning at: ESIZE_64_BITS():: +BLines (lines remaining after reading input) = 73944 +============================================= +Creating a generator 168 +============================================= +ALines (lines before reading input) = 73944 +read_input 1360 +NONTERMINAL: ESIZE_64_BITS notype +Adding ESIZE_64_BITS to nonterminal dict +Nonterminal ESIZE_64_BITS():: +Nonterminal name ESIZE_64_BITS +read_flat_input 1360 +Hit a nonterminal, returning at: ESIZE_32_BITS():: +BLines (lines remaining after reading input) = 73942 +============================================= +Creating a generator 169 +============================================= +ALines (lines before reading input) = 73942 +read_input 1361 +NONTERMINAL: ESIZE_32_BITS notype +Adding ESIZE_32_BITS to nonterminal dict +Nonterminal ESIZE_32_BITS():: +Nonterminal name ESIZE_32_BITS +read_flat_input 1361 +Hit a nonterminal, returning at: ESIZE_16_BITS():: +BLines (lines remaining after reading input) = 73940 +============================================= +Creating a generator 170 +============================================= +ALines (lines before reading input) = 73940 +read_input 1362 +NONTERMINAL: ESIZE_16_BITS notype +Adding ESIZE_16_BITS to nonterminal dict +Nonterminal ESIZE_16_BITS():: +Nonterminal name ESIZE_16_BITS +read_flat_input 1362 +Hit a nonterminal, returning at: ESIZE_8_BITS():: +BLines (lines remaining after reading input) = 73938 +============================================= +Creating a generator 171 +============================================= +ALines (lines before reading input) = 73938 +read_input 1363 +NONTERMINAL: ESIZE_8_BITS notype +Adding ESIZE_8_BITS to nonterminal dict +Nonterminal ESIZE_8_BITS():: +Nonterminal name ESIZE_8_BITS +read_flat_input 1363 +Hit a nonterminal, returning at: ESIZE_4_BITS():: +BLines (lines remaining after reading input) = 73936 +============================================= +Creating a generator 172 +============================================= +ALines (lines before reading input) = 73936 +read_input 1364 +NONTERMINAL: ESIZE_4_BITS notype +Adding ESIZE_4_BITS to nonterminal dict +Nonterminal ESIZE_4_BITS():: +Nonterminal name ESIZE_4_BITS +read_flat_input 1364 +Hit a nonterminal, returning at: ESIZE_2_BITS():: +BLines (lines remaining after reading input) = 73934 +============================================= +Creating a generator 173 +============================================= +ALines (lines before reading input) = 73934 +read_input 1365 +NONTERMINAL: ESIZE_2_BITS notype +Adding ESIZE_2_BITS to nonterminal dict +Nonterminal ESIZE_2_BITS():: +Nonterminal name ESIZE_2_BITS +read_flat_input 1365 +Hit a nonterminal, returning at: ESIZE_1_BITS():: +BLines (lines remaining after reading input) = 73932 +============================================= +Creating a generator 174 +============================================= +ALines (lines before reading input) = 73932 +read_input 1366 +NONTERMINAL: ESIZE_1_BITS notype +Adding ESIZE_1_BITS to nonterminal dict +Nonterminal ESIZE_1_BITS():: +Nonterminal name ESIZE_1_BITS +read_flat_input 1366 +Hit a nonterminal, returning at: NELEM_MOVDDUP():: +BLines (lines remaining after reading input) = 73930 +============================================= +Creating a generator 175 +============================================= +ALines (lines before reading input) = 73930 +read_input 1367 +NONTERMINAL: NELEM_MOVDDUP notype +Adding NELEM_MOVDDUP to nonterminal dict +Nonterminal NELEM_MOVDDUP():: +Nonterminal name NELEM_MOVDDUP +read_flat_input 1367 +Hit a nonterminal, returning at: NELEM_FULLMEM():: +BLines (lines remaining after reading input) = 73926 +============================================= +Creating a generator 176 +============================================= +ALines (lines before reading input) = 73926 +read_input 1370 +NONTERMINAL: NELEM_FULLMEM notype +Adding NELEM_FULLMEM to nonterminal dict +Nonterminal NELEM_FULLMEM():: +Nonterminal name NELEM_FULLMEM +read_flat_input 1370 +Hit a nonterminal, returning at: NELEM_HALFMEM():: +BLines (lines remaining after reading input) = 73895 +============================================= +Creating a generator 177 +============================================= +ALines (lines before reading input) = 73895 +read_input 1400 +NONTERMINAL: NELEM_HALFMEM notype +Adding NELEM_HALFMEM to nonterminal dict +Nonterminal NELEM_HALFMEM():: +Nonterminal name NELEM_HALFMEM +read_flat_input 1400 +Hit a nonterminal, returning at: NELEM_QUARTERMEM():: +BLines (lines remaining after reading input) = 73864 +============================================= +Creating a generator 178 +============================================= +ALines (lines before reading input) = 73864 +read_input 1430 +NONTERMINAL: NELEM_QUARTERMEM notype +Adding NELEM_QUARTERMEM to nonterminal dict +Nonterminal NELEM_QUARTERMEM():: +Nonterminal name NELEM_QUARTERMEM +read_flat_input 1430 +Hit a nonterminal, returning at: NELEM_EIGHTHMEM():: +BLines (lines remaining after reading input) = 73833 +============================================= +Creating a generator 179 +============================================= +ALines (lines before reading input) = 73833 +read_input 1460 +NONTERMINAL: NELEM_EIGHTHMEM notype +Adding NELEM_EIGHTHMEM to nonterminal dict +Nonterminal NELEM_EIGHTHMEM():: +Nonterminal name NELEM_EIGHTHMEM +read_flat_input 1460 +Hit a nonterminal, returning at: NELEM_GPR_READER_BYTE():: +BLines (lines remaining after reading input) = 73802 +============================================= +Creating a generator 180 +============================================= +ALines (lines before reading input) = 73802 +read_input 1490 +NONTERMINAL: NELEM_GPR_READER_BYTE notype +Adding NELEM_GPR_READER_BYTE to nonterminal dict +Nonterminal NELEM_GPR_READER_BYTE():: +Nonterminal name NELEM_GPR_READER_BYTE +read_flat_input 1490 +Hit a nonterminal, returning at: NELEM_GPR_READER_WORD():: +BLines (lines remaining after reading input) = 73798 +============================================= +Creating a generator 181 +============================================= +ALines (lines before reading input) = 73798 +read_input 1493 +NONTERMINAL: NELEM_GPR_READER_WORD notype +Adding NELEM_GPR_READER_WORD to nonterminal dict +Nonterminal NELEM_GPR_READER_WORD():: +Nonterminal name NELEM_GPR_READER_WORD +read_flat_input 1493 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_LDOP_D():: +BLines (lines remaining after reading input) = 73794 +============================================= +Creating a generator 182 +============================================= +ALines (lines before reading input) = 73794 +read_input 1496 +NONTERMINAL: NELEM_GPR_WRITER_LDOP_D notype +Adding NELEM_GPR_WRITER_LDOP_D to nonterminal dict +Nonterminal NELEM_GPR_WRITER_LDOP_D():: +Nonterminal name NELEM_GPR_WRITER_LDOP_D +read_flat_input 1496 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_LDOP_Q():: +BLines (lines remaining after reading input) = 73790 +============================================= +Creating a generator 183 +============================================= +ALines (lines before reading input) = 73790 +read_input 1499 +NONTERMINAL: NELEM_GPR_WRITER_LDOP_Q notype +Adding NELEM_GPR_WRITER_LDOP_Q to nonterminal dict +Nonterminal NELEM_GPR_WRITER_LDOP_Q():: +Nonterminal name NELEM_GPR_WRITER_LDOP_Q +read_flat_input 1499 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_STORE_BYTE():: +BLines (lines remaining after reading input) = 73786 +============================================= +Creating a generator 184 +============================================= +ALines (lines before reading input) = 73786 +read_input 1502 +NONTERMINAL: NELEM_GPR_WRITER_STORE_BYTE notype +Adding NELEM_GPR_WRITER_STORE_BYTE to nonterminal dict +Nonterminal NELEM_GPR_WRITER_STORE_BYTE():: +Nonterminal name NELEM_GPR_WRITER_STORE_BYTE +read_flat_input 1502 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_STORE_WORD():: +BLines (lines remaining after reading input) = 73782 +============================================= +Creating a generator 185 +============================================= +ALines (lines before reading input) = 73782 +read_input 1505 +NONTERMINAL: NELEM_GPR_WRITER_STORE_WORD notype +Adding NELEM_GPR_WRITER_STORE_WORD to nonterminal dict +Nonterminal NELEM_GPR_WRITER_STORE_WORD():: +Nonterminal name NELEM_GPR_WRITER_STORE_WORD +read_flat_input 1505 +Hit a nonterminal, returning at: NELEM_TUPLE1_BYTE():: +BLines (lines remaining after reading input) = 73778 +============================================= +Creating a generator 186 +============================================= +ALines (lines before reading input) = 73778 +read_input 1508 +NONTERMINAL: NELEM_TUPLE1_BYTE notype +Adding NELEM_TUPLE1_BYTE to nonterminal dict +Nonterminal NELEM_TUPLE1_BYTE():: +Nonterminal name NELEM_TUPLE1_BYTE +read_flat_input 1508 +Hit a nonterminal, returning at: NELEM_TUPLE1_WORD():: +BLines (lines remaining after reading input) = 73774 +============================================= +Creating a generator 187 +============================================= +ALines (lines before reading input) = 73774 +read_input 1511 +NONTERMINAL: NELEM_TUPLE1_WORD notype +Adding NELEM_TUPLE1_WORD to nonterminal dict +Nonterminal NELEM_TUPLE1_WORD():: +Nonterminal name NELEM_TUPLE1_WORD +read_flat_input 1511 +Hit a nonterminal, returning at: NELEM_SCALAR():: +BLines (lines remaining after reading input) = 73770 +============================================= +Creating a generator 188 +============================================= +ALines (lines before reading input) = 73770 +read_input 1514 +NONTERMINAL: NELEM_SCALAR notype +Adding NELEM_SCALAR to nonterminal dict +Nonterminal NELEM_SCALAR():: +Nonterminal name NELEM_SCALAR +read_flat_input 1514 +Hit a nonterminal, returning at: NELEM_TUPLE1_SUBDWORD():: +BLines (lines remaining after reading input) = 73766 +============================================= +Creating a generator 189 +============================================= +ALines (lines before reading input) = 73766 +read_input 1517 +NONTERMINAL: NELEM_TUPLE1_SUBDWORD notype +Adding NELEM_TUPLE1_SUBDWORD to nonterminal dict +Nonterminal NELEM_TUPLE1_SUBDWORD():: +Nonterminal name NELEM_TUPLE1_SUBDWORD +read_flat_input 1517 +Hit a nonterminal, returning at: NELEM_GPR_READER():: +BLines (lines remaining after reading input) = 73762 +============================================= +Creating a generator 190 +============================================= +ALines (lines before reading input) = 73762 +read_input 1520 +NONTERMINAL: NELEM_GPR_READER notype +Adding NELEM_GPR_READER to nonterminal dict +Nonterminal NELEM_GPR_READER():: +Nonterminal name NELEM_GPR_READER +read_flat_input 1520 +Hit a nonterminal, returning at: NELEM_GPR_READER_SUBDWORD():: +BLines (lines remaining after reading input) = 73758 +============================================= +Creating a generator 191 +============================================= +ALines (lines before reading input) = 73758 +read_input 1523 +NONTERMINAL: NELEM_GPR_READER_SUBDWORD notype +Adding NELEM_GPR_READER_SUBDWORD to nonterminal dict +Nonterminal NELEM_GPR_READER_SUBDWORD():: +Nonterminal name NELEM_GPR_READER_SUBDWORD +read_flat_input 1523 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_LDOP():: +BLines (lines remaining after reading input) = 73754 +============================================= +Creating a generator 192 +============================================= +ALines (lines before reading input) = 73754 +read_input 1526 +NONTERMINAL: NELEM_GPR_WRITER_LDOP notype +Adding NELEM_GPR_WRITER_LDOP to nonterminal dict +Nonterminal NELEM_GPR_WRITER_LDOP():: +Nonterminal name NELEM_GPR_WRITER_LDOP +read_flat_input 1526 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_STORE():: +BLines (lines remaining after reading input) = 73750 +============================================= +Creating a generator 193 +============================================= +ALines (lines before reading input) = 73750 +read_input 1529 +NONTERMINAL: NELEM_GPR_WRITER_STORE notype +Adding NELEM_GPR_WRITER_STORE to nonterminal dict +Nonterminal NELEM_GPR_WRITER_STORE():: +Nonterminal name NELEM_GPR_WRITER_STORE +read_flat_input 1529 +Hit a nonterminal, returning at: NELEM_GPR_WRITER_STORE_SUBDWORD():: +BLines (lines remaining after reading input) = 73746 +============================================= +Creating a generator 194 +============================================= +ALines (lines before reading input) = 73746 +read_input 1532 +NONTERMINAL: NELEM_GPR_WRITER_STORE_SUBDWORD notype +Adding NELEM_GPR_WRITER_STORE_SUBDWORD to nonterminal dict +Nonterminal NELEM_GPR_WRITER_STORE_SUBDWORD():: +Nonterminal name NELEM_GPR_WRITER_STORE_SUBDWORD +read_flat_input 1532 +Hit a nonterminal, returning at: NELEM_TUPLE1():: +BLines (lines remaining after reading input) = 73742 +============================================= +Creating a generator 195 +============================================= +ALines (lines before reading input) = 73742 +read_input 1535 +NONTERMINAL: NELEM_TUPLE1 notype +Adding NELEM_TUPLE1 to nonterminal dict +Nonterminal NELEM_TUPLE1():: +Nonterminal name NELEM_TUPLE1 +read_flat_input 1535 +Hit a nonterminal, returning at: NELEM_GSCAT():: +BLines (lines remaining after reading input) = 73738 +============================================= +Creating a generator 196 +============================================= +ALines (lines before reading input) = 73738 +read_input 1538 +NONTERMINAL: NELEM_GSCAT notype +Adding NELEM_GSCAT to nonterminal dict +Nonterminal NELEM_GSCAT():: +Nonterminal name NELEM_GSCAT +read_flat_input 1538 +Hit a nonterminal, returning at: NELEM_TUPLE2():: +BLines (lines remaining after reading input) = 73734 +============================================= +Creating a generator 197 +============================================= +ALines (lines before reading input) = 73734 +read_input 1541 +NONTERMINAL: NELEM_TUPLE2 notype +Adding NELEM_TUPLE2 to nonterminal dict +Nonterminal NELEM_TUPLE2():: +Nonterminal name NELEM_TUPLE2 +read_flat_input 1541 +Hit a nonterminal, returning at: NELEM_TUPLE4():: +BLines (lines remaining after reading input) = 73730 +============================================= +Creating a generator 198 +============================================= +ALines (lines before reading input) = 73730 +read_input 1544 +NONTERMINAL: NELEM_TUPLE4 notype +Adding NELEM_TUPLE4 to nonterminal dict +Nonterminal NELEM_TUPLE4():: +Nonterminal name NELEM_TUPLE4 +read_flat_input 1544 +Hit a nonterminal, returning at: NELEM_TUPLE8():: +BLines (lines remaining after reading input) = 73726 +============================================= +Creating a generator 199 +============================================= +ALines (lines before reading input) = 73726 +read_input 1547 +NONTERMINAL: NELEM_TUPLE8 notype +Adding NELEM_TUPLE8 to nonterminal dict +Nonterminal NELEM_TUPLE8():: +Nonterminal name NELEM_TUPLE8 +read_flat_input 1547 +Hit a nonterminal, returning at: NELEM_MEM128():: +BLines (lines remaining after reading input) = 73722 +============================================= +Creating a generator 200 +============================================= +ALines (lines before reading input) = 73722 +read_input 1550 +NONTERMINAL: NELEM_MEM128 notype +Adding NELEM_MEM128 to nonterminal dict +Nonterminal NELEM_MEM128():: +Nonterminal name NELEM_MEM128 +read_flat_input 1550 +Hit a nonterminal, returning at: NELEM_FULL():: +BLines (lines remaining after reading input) = 73719 +============================================= +Creating a generator 201 +============================================= +ALines (lines before reading input) = 73719 +read_input 1552 +NONTERMINAL: NELEM_FULL notype +Adding NELEM_FULL to nonterminal dict +Nonterminal NELEM_FULL():: +Nonterminal name NELEM_FULL +read_flat_input 1552 +Hit a nonterminal, returning at: NELEM_HALF():: +BLines (lines remaining after reading input) = 73700 +============================================= +Creating a generator 202 +============================================= +ALines (lines before reading input) = 73700 +read_input 1570 +NONTERMINAL: NELEM_HALF notype +Adding NELEM_HALF to nonterminal dict +Nonterminal NELEM_HALF():: +Nonterminal name NELEM_HALF +read_flat_input 1570 +Hit a nonterminal, returning at: FIX_ROUND_LEN512():: +BLines (lines remaining after reading input) = 73693 +============================================= +Creating a generator 203 +============================================= +ALines (lines before reading input) = 73693 +read_input 1576 +NONTERMINAL: FIX_ROUND_LEN512 notype +Adding FIX_ROUND_LEN512 to nonterminal dict +Nonterminal FIX_ROUND_LEN512():: +Nonterminal name FIX_ROUND_LEN512 +read_flat_input 1576 +Hit a nonterminal, returning at: FIX_ROUND_LEN128():: +BLines (lines remaining after reading input) = 73689 +============================================= +Creating a generator 204 +============================================= +ALines (lines before reading input) = 73689 +read_input 1579 +NONTERMINAL: FIX_ROUND_LEN128 notype +Adding FIX_ROUND_LEN128 to nonterminal dict +Nonterminal FIX_ROUND_LEN128():: +Nonterminal name FIX_ROUND_LEN128 +read_flat_input 1579 +Hit a nonterminal, returning at: UISA_VMODRM_ZMM():: +BLines (lines remaining after reading input) = 73685 +============================================= +Creating a generator 205 +============================================= +ALines (lines before reading input) = 73685 +read_input 1582 +NONTERMINAL: UISA_VMODRM_ZMM notype +Adding UISA_VMODRM_ZMM to nonterminal dict +Nonterminal UISA_VMODRM_ZMM():: +Nonterminal name UISA_VMODRM_ZMM +read_flat_input 1582 +Hit a nonterminal, returning at: UISA_VMODRM_YMM():: +BLines (lines remaining after reading input) = 73681 +============================================= +Creating a generator 206 +============================================= +ALines (lines before reading input) = 73681 +read_input 1585 +NONTERMINAL: UISA_VMODRM_YMM notype +Adding UISA_VMODRM_YMM to nonterminal dict +Nonterminal UISA_VMODRM_YMM():: +Nonterminal name UISA_VMODRM_YMM +read_flat_input 1585 +Hit a nonterminal, returning at: UISA_VMODRM_XMM():: +BLines (lines remaining after reading input) = 73677 +============================================= +Creating a generator 207 +============================================= +ALines (lines before reading input) = 73677 +read_input 1588 +NONTERMINAL: UISA_VMODRM_XMM notype +Adding UISA_VMODRM_XMM to nonterminal dict +Nonterminal UISA_VMODRM_XMM():: +Nonterminal name UISA_VMODRM_XMM +read_flat_input 1588 +Hit a nonterminal, returning at: UISA_VSIB_ZMM():: +BLines (lines remaining after reading input) = 73673 +============================================= +Creating a generator 208 +============================================= +ALines (lines before reading input) = 73673 +read_input 1591 +NONTERMINAL: UISA_VSIB_ZMM notype +Adding UISA_VSIB_ZMM to nonterminal dict +Nonterminal UISA_VSIB_ZMM():: +Nonterminal name UISA_VSIB_ZMM +read_flat_input 1591 +Hit a nonterminal, returning at: UISA_VSIB_YMM():: +BLines (lines remaining after reading input) = 73668 +============================================= +Creating a generator 209 +============================================= +ALines (lines before reading input) = 73668 +read_input 1595 +NONTERMINAL: UISA_VSIB_YMM notype +Adding UISA_VSIB_YMM to nonterminal dict +Nonterminal UISA_VSIB_YMM():: +Nonterminal name UISA_VSIB_YMM +read_flat_input 1595 +Hit a nonterminal, returning at: UISA_VSIB_XMM():: +BLines (lines remaining after reading input) = 73663 +============================================= +Creating a generator 210 +============================================= +ALines (lines before reading input) = 73663 +read_input 1599 +NONTERMINAL: UISA_VSIB_XMM notype +Adding UISA_VSIB_XMM to nonterminal dict +Nonterminal UISA_VSIB_XMM():: +Nonterminal name UISA_VSIB_XMM +read_flat_input 1599 +Hit a nonterminal, returning at: xed_reg_enum_t UISA_VSIB_INDEX_ZMM():: +BLines (lines remaining after reading input) = 73658 +============================================= +Creating a generator 211 +============================================= +ALines (lines before reading input) = 73658 +read_input 1603 +NONTERMINAL: UISA_VSIB_INDEX_ZMM type= xed_reg_enum_t +Adding UISA_VSIB_INDEX_ZMM to nonterminal dict +Nonterminal xed_reg_enum_t UISA_VSIB_INDEX_ZMM():: +Nonterminal name UISA_VSIB_INDEX_ZMM +read_flat_input 1603 +Hit a nonterminal, returning at: xed_reg_enum_t UISA_VSIB_INDEX_YMM():: +BLines (lines remaining after reading input) = 73625 +============================================= +Creating a generator 212 +============================================= +ALines (lines before reading input) = 73625 +read_input 1635 +NONTERMINAL: UISA_VSIB_INDEX_YMM type= xed_reg_enum_t +Adding UISA_VSIB_INDEX_YMM to nonterminal dict +Nonterminal xed_reg_enum_t UISA_VSIB_INDEX_YMM():: +Nonterminal name UISA_VSIB_INDEX_YMM +read_flat_input 1635 +Hit a nonterminal, returning at: xed_reg_enum_t UISA_VSIB_INDEX_XMM():: +BLines (lines remaining after reading input) = 73592 +============================================= +Creating a generator 213 +============================================= +ALines (lines before reading input) = 73592 +read_input 1667 +NONTERMINAL: UISA_VSIB_INDEX_XMM type= xed_reg_enum_t +Adding UISA_VSIB_INDEX_XMM to nonterminal dict +Nonterminal xed_reg_enum_t UISA_VSIB_INDEX_XMM():: +Nonterminal name UISA_VSIB_INDEX_XMM +read_flat_input 1667 +Hit a nonterminal, returning at: UISA_VSIB_BASE():: +BLines (lines remaining after reading input) = 73559 +============================================= +Creating a generator 214 +============================================= +ALines (lines before reading input) = 73559 +read_input 1699 +NONTERMINAL: UISA_VSIB_BASE notype +Adding UISA_VSIB_BASE to nonterminal dict +Nonterminal UISA_VSIB_BASE():: +Nonterminal name UISA_VSIB_BASE +read_flat_input 1699 +Hit a nonterminal, returning at: xed_reg_enum_t MASK1():: +BLines (lines remaining after reading input) = 73540 +============================================= +Creating a generator 215 +============================================= +ALines (lines before reading input) = 73540 +read_input 1717 +NONTERMINAL: MASK1 type= xed_reg_enum_t +Adding MASK1 to nonterminal dict +Nonterminal xed_reg_enum_t MASK1():: +Nonterminal name MASK1 +read_flat_input 1717 +Hit a nonterminal, returning at: xed_reg_enum_t MASKNOT0():: +BLines (lines remaining after reading input) = 73531 +============================================= +Creating a generator 216 +============================================= +ALines (lines before reading input) = 73531 +read_input 1725 +NONTERMINAL: MASKNOT0 type= xed_reg_enum_t +Adding MASKNOT0 to nonterminal dict +Nonterminal xed_reg_enum_t MASKNOT0():: +Nonterminal name MASKNOT0 +read_flat_input 1725 +Hit a nonterminal, returning at: xed_reg_enum_t MASK_R():: +BLines (lines remaining after reading input) = 73522 +============================================= +Creating a generator 217 +============================================= +ALines (lines before reading input) = 73522 +read_input 1733 +NONTERMINAL: MASK_R type= xed_reg_enum_t +Adding MASK_R to nonterminal dict +Nonterminal xed_reg_enum_t MASK_R():: +Nonterminal name MASK_R +read_flat_input 1733 +Hit a nonterminal, returning at: xed_reg_enum_t MASK_B():: +BLines (lines remaining after reading input) = 73513 +============================================= +Creating a generator 218 +============================================= +ALines (lines before reading input) = 73513 +read_input 1741 +NONTERMINAL: MASK_B type= xed_reg_enum_t +Adding MASK_B to nonterminal dict +Nonterminal xed_reg_enum_t MASK_B():: +Nonterminal name MASK_B +read_flat_input 1741 +Hit a nonterminal, returning at: xed_reg_enum_t MASK_N():: +BLines (lines remaining after reading input) = 73504 +============================================= +Creating a generator 219 +============================================= +ALines (lines before reading input) = 73504 +read_input 1749 +NONTERMINAL: MASK_N type= xed_reg_enum_t +Adding MASK_N to nonterminal dict +Nonterminal xed_reg_enum_t MASK_N():: +Nonterminal name MASK_N +read_flat_input 1749 +Hit a nonterminal, returning at: xed_reg_enum_t MASK_N64():: +BLines (lines remaining after reading input) = 73500 +============================================= +Creating a generator 220 +============================================= +ALines (lines before reading input) = 73500 +read_input 1752 +NONTERMINAL: MASK_N64 type= xed_reg_enum_t +Adding MASK_N64 to nonterminal dict +Nonterminal xed_reg_enum_t MASK_N64():: +Nonterminal name MASK_N64 +read_flat_input 1752 +Hit a nonterminal, returning at: xed_reg_enum_t MASK_N32():: +BLines (lines remaining after reading input) = 73491 +============================================= +Creating a generator 221 +============================================= +ALines (lines before reading input) = 73491 +read_input 1760 +NONTERMINAL: MASK_N32 type= xed_reg_enum_t +Adding MASK_N32 to nonterminal dict +Nonterminal xed_reg_enum_t MASK_N32():: +Nonterminal name MASK_N32 +read_flat_input 1760 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_R3():: +BLines (lines remaining after reading input) = 73482 +============================================= +Creating a generator 222 +============================================= +ALines (lines before reading input) = 73482 +read_input 1768 +NONTERMINAL: XMM_R3 type= xed_reg_enum_t +Adding XMM_R3 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_R3():: +Nonterminal name XMM_R3 +read_flat_input 1768 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_R3_32():: +BLines (lines remaining after reading input) = 73478 +============================================= +Creating a generator 223 +============================================= +ALines (lines before reading input) = 73478 +read_input 1771 +NONTERMINAL: XMM_R3_32 type= xed_reg_enum_t +Adding XMM_R3_32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_R3_32():: +Nonterminal name XMM_R3_32 +read_flat_input 1771 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_R3_64():: +BLines (lines remaining after reading input) = 73469 +============================================= +Creating a generator 224 +============================================= +ALines (lines before reading input) = 73469 +read_input 1779 +NONTERMINAL: XMM_R3_64 type= xed_reg_enum_t +Adding XMM_R3_64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_R3_64():: +Nonterminal name XMM_R3_64 +read_flat_input 1779 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_R3():: +BLines (lines remaining after reading input) = 73436 +============================================= +Creating a generator 225 +============================================= +ALines (lines before reading input) = 73436 +read_input 1811 +NONTERMINAL: YMM_R3 type= xed_reg_enum_t +Adding YMM_R3 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_R3():: +Nonterminal name YMM_R3 +read_flat_input 1811 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_R3_32():: +BLines (lines remaining after reading input) = 73432 +============================================= +Creating a generator 226 +============================================= +ALines (lines before reading input) = 73432 +read_input 1814 +NONTERMINAL: YMM_R3_32 type= xed_reg_enum_t +Adding YMM_R3_32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_R3_32():: +Nonterminal name YMM_R3_32 +read_flat_input 1814 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_R3_64():: +BLines (lines remaining after reading input) = 73423 +============================================= +Creating a generator 227 +============================================= +ALines (lines before reading input) = 73423 +read_input 1822 +NONTERMINAL: YMM_R3_64 type= xed_reg_enum_t +Adding YMM_R3_64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_R3_64():: +Nonterminal name YMM_R3_64 +read_flat_input 1822 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_R3():: +BLines (lines remaining after reading input) = 73390 +============================================= +Creating a generator 228 +============================================= +ALines (lines before reading input) = 73390 +read_input 1854 +NONTERMINAL: ZMM_R3 type= xed_reg_enum_t +Adding ZMM_R3 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_R3():: +Nonterminal name ZMM_R3 +read_flat_input 1854 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_R3_32():: +BLines (lines remaining after reading input) = 73386 +============================================= +Creating a generator 229 +============================================= +ALines (lines before reading input) = 73386 +read_input 1857 +NONTERMINAL: ZMM_R3_32 type= xed_reg_enum_t +Adding ZMM_R3_32 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_R3_32():: +Nonterminal name ZMM_R3_32 +read_flat_input 1857 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_R3_64():: +BLines (lines remaining after reading input) = 73377 +============================================= +Creating a generator 230 +============================================= +ALines (lines before reading input) = 73377 +read_input 1865 +NONTERMINAL: ZMM_R3_64 type= xed_reg_enum_t +Adding ZMM_R3_64 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_R3_64():: +Nonterminal name ZMM_R3_64 +read_flat_input 1865 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_B3():: +BLines (lines remaining after reading input) = 73344 +============================================= +Creating a generator 231 +============================================= +ALines (lines before reading input) = 73344 +read_input 1897 +NONTERMINAL: XMM_B3 type= xed_reg_enum_t +Adding XMM_B3 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_B3():: +Nonterminal name XMM_B3 +read_flat_input 1897 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_B3_32():: +BLines (lines remaining after reading input) = 73340 +============================================= +Creating a generator 232 +============================================= +ALines (lines before reading input) = 73340 +read_input 1900 +NONTERMINAL: XMM_B3_32 type= xed_reg_enum_t +Adding XMM_B3_32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_B3_32():: +Nonterminal name XMM_B3_32 +read_flat_input 1900 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_B3_64():: +BLines (lines remaining after reading input) = 73331 +============================================= +Creating a generator 233 +============================================= +ALines (lines before reading input) = 73331 +read_input 1908 +NONTERMINAL: XMM_B3_64 type= xed_reg_enum_t +Adding XMM_B3_64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_B3_64():: +Nonterminal name XMM_B3_64 +read_flat_input 1908 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_B3():: +BLines (lines remaining after reading input) = 73298 +============================================= +Creating a generator 234 +============================================= +ALines (lines before reading input) = 73298 +read_input 1940 +NONTERMINAL: YMM_B3 type= xed_reg_enum_t +Adding YMM_B3 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_B3():: +Nonterminal name YMM_B3 +read_flat_input 1940 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_B3_32():: +BLines (lines remaining after reading input) = 73294 +============================================= +Creating a generator 235 +============================================= +ALines (lines before reading input) = 73294 +read_input 1943 +NONTERMINAL: YMM_B3_32 type= xed_reg_enum_t +Adding YMM_B3_32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_B3_32():: +Nonterminal name YMM_B3_32 +read_flat_input 1943 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_B3_64():: +BLines (lines remaining after reading input) = 73285 +============================================= +Creating a generator 236 +============================================= +ALines (lines before reading input) = 73285 +read_input 1951 +NONTERMINAL: YMM_B3_64 type= xed_reg_enum_t +Adding YMM_B3_64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_B3_64():: +Nonterminal name YMM_B3_64 +read_flat_input 1951 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_B3():: +BLines (lines remaining after reading input) = 73252 +============================================= +Creating a generator 237 +============================================= +ALines (lines before reading input) = 73252 +read_input 1983 +NONTERMINAL: ZMM_B3 type= xed_reg_enum_t +Adding ZMM_B3 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_B3():: +Nonterminal name ZMM_B3 +read_flat_input 1983 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_B3_32():: +BLines (lines remaining after reading input) = 73248 +============================================= +Creating a generator 238 +============================================= +ALines (lines before reading input) = 73248 +read_input 1986 +NONTERMINAL: ZMM_B3_32 type= xed_reg_enum_t +Adding ZMM_B3_32 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_B3_32():: +Nonterminal name ZMM_B3_32 +read_flat_input 1986 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_B3_64():: +BLines (lines remaining after reading input) = 73239 +============================================= +Creating a generator 239 +============================================= +ALines (lines before reading input) = 73239 +read_input 1994 +NONTERMINAL: ZMM_B3_64 type= xed_reg_enum_t +Adding ZMM_B3_64 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_B3_64():: +Nonterminal name ZMM_B3_64 +read_flat_input 1994 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_N3():: +BLines (lines remaining after reading input) = 73206 +============================================= +Creating a generator 240 +============================================= +ALines (lines before reading input) = 73206 +read_input 2026 +NONTERMINAL: XMM_N3 type= xed_reg_enum_t +Adding XMM_N3 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_N3():: +Nonterminal name XMM_N3 +read_flat_input 2026 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_N3_32():: +BLines (lines remaining after reading input) = 73202 +============================================= +Creating a generator 241 +============================================= +ALines (lines before reading input) = 73202 +read_input 2029 +NONTERMINAL: XMM_N3_32 type= xed_reg_enum_t +Adding XMM_N3_32 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_N3_32():: +Nonterminal name XMM_N3_32 +read_flat_input 2029 +Hit a nonterminal, returning at: xed_reg_enum_t XMM_N3_64():: +BLines (lines remaining after reading input) = 73193 +============================================= +Creating a generator 242 +============================================= +ALines (lines before reading input) = 73193 +read_input 2037 +NONTERMINAL: XMM_N3_64 type= xed_reg_enum_t +Adding XMM_N3_64 to nonterminal dict +Nonterminal xed_reg_enum_t XMM_N3_64():: +Nonterminal name XMM_N3_64 +read_flat_input 2037 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_N3():: +BLines (lines remaining after reading input) = 73160 +============================================= +Creating a generator 243 +============================================= +ALines (lines before reading input) = 73160 +read_input 2069 +NONTERMINAL: YMM_N3 type= xed_reg_enum_t +Adding YMM_N3 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_N3():: +Nonterminal name YMM_N3 +read_flat_input 2069 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_N3_32():: +BLines (lines remaining after reading input) = 73156 +============================================= +Creating a generator 244 +============================================= +ALines (lines before reading input) = 73156 +read_input 2072 +NONTERMINAL: YMM_N3_32 type= xed_reg_enum_t +Adding YMM_N3_32 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_N3_32():: +Nonterminal name YMM_N3_32 +read_flat_input 2072 +Hit a nonterminal, returning at: xed_reg_enum_t YMM_N3_64():: +BLines (lines remaining after reading input) = 73147 +============================================= +Creating a generator 245 +============================================= +ALines (lines before reading input) = 73147 +read_input 2080 +NONTERMINAL: YMM_N3_64 type= xed_reg_enum_t +Adding YMM_N3_64 to nonterminal dict +Nonterminal xed_reg_enum_t YMM_N3_64():: +Nonterminal name YMM_N3_64 +read_flat_input 2080 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_N3():: +BLines (lines remaining after reading input) = 73114 +============================================= +Creating a generator 246 +============================================= +ALines (lines before reading input) = 73114 +read_input 2112 +NONTERMINAL: ZMM_N3 type= xed_reg_enum_t +Adding ZMM_N3 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_N3():: +Nonterminal name ZMM_N3 +read_flat_input 2112 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_N3_32():: +BLines (lines remaining after reading input) = 73110 +============================================= +Creating a generator 247 +============================================= +ALines (lines before reading input) = 73110 +read_input 2115 +NONTERMINAL: ZMM_N3_32 type= xed_reg_enum_t +Adding ZMM_N3_32 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_N3_32():: +Nonterminal name ZMM_N3_32 +read_flat_input 2115 +Hit a nonterminal, returning at: xed_reg_enum_t ZMM_N3_64():: +BLines (lines remaining after reading input) = 73101 +============================================= +Creating a generator 248 +============================================= +ALines (lines before reading input) = 73101 +read_input 2123 +NONTERMINAL: ZMM_N3_64 type= xed_reg_enum_t +Adding ZMM_N3_64 to nonterminal dict +Nonterminal xed_reg_enum_t ZMM_N3_64():: +Nonterminal name ZMM_N3_64 +read_flat_input 2123 +Hit a nonterminal, returning at: xed_reg_enum_t TMM_R():: +BLines (lines remaining after reading input) = 73068 +============================================= +Creating a generator 249 +============================================= +ALines (lines before reading input) = 73068 +read_input 2155 +NONTERMINAL: TMM_R type= xed_reg_enum_t +Adding TMM_R to nonterminal dict +Nonterminal xed_reg_enum_t TMM_R():: +Nonterminal name TMM_R +read_flat_input 2155 +Hit a nonterminal, returning at: xed_reg_enum_t TMM_B():: +BLines (lines remaining after reading input) = 73059 +============================================= +Creating a generator 250 +============================================= +ALines (lines before reading input) = 73059 +read_input 2163 +NONTERMINAL: TMM_B type= xed_reg_enum_t +Adding TMM_B to nonterminal dict +Nonterminal xed_reg_enum_t TMM_B():: +Nonterminal name TMM_B +read_flat_input 2163 +Hit a nonterminal, returning at: xed_reg_enum_t TMM_N():: +BLines (lines remaining after reading input) = 73050 +============================================= +Creating a generator 251 +============================================= +ALines (lines before reading input) = 73050 +read_input 2171 +NONTERMINAL: TMM_N type= xed_reg_enum_t +Adding TMM_N to nonterminal dict +Nonterminal xed_reg_enum_t TMM_N():: +Nonterminal name TMM_N +read_flat_input 2171 +Hit a nonterminal, returning at: NELEM_HALF():: +BLines (lines remaining after reading input) = 73041 +============================================= +Creating a generator 252 +============================================= +ALines (lines before reading input) = 73041 +read_input 2179 +NONTERMINAL: NELEM_HALF notype +FOUND OLD PARSER FOR NELEM_HALF +Nonterminal NELEM_HALF():: +Nonterminal name NELEM_HALF +read_flat_input 2179 +Hit a nonterminal, returning at: NELEM_QUARTER():: +BLines (lines remaining after reading input) = 73034 +============================================= +Creating a generator 252 +============================================= +ALines (lines before reading input) = 73034 +read_input 2185 +NONTERMINAL: NELEM_QUARTER notype +Adding NELEM_QUARTER to nonterminal dict +Nonterminal NELEM_QUARTER():: +Nonterminal name NELEM_QUARTER +read_flat_input 2185 +Hit a nonterminal, returning at: INSTRUCTIONS():: +BLines (lines remaining after reading input) = 73027 +============================================= +Creating a generator 253 +============================================= +ALines (lines before reading input) = 73027 +read_input 2191 +NONTERMINAL: INSTRUCTIONS notype +Adding INSTRUCTIONS to nonterminal dict +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 58747 lines remaining. +BLines (lines remaining after reading input) = 58747 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 58747 +read_input 4100 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 58553 lines remaining. +BLines (lines remaining after reading input) = 58553 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 58553 +read_input 4120 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 58111 lines remaining. +BLines (lines remaining after reading input) = 58111 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 58111 +read_input 4169 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 58086 lines remaining. +BLines (lines remaining after reading input) = 58086 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 58086 +read_input 4171 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 57948 lines remaining. +BLines (lines remaining after reading input) = 57948 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 57948 +read_input 4189 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 57900 lines remaining. +BLines (lines remaining after reading input) = 57900 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 57900 +read_input 4196 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 57888 lines remaining. +BLines (lines remaining after reading input) = 57888 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 57888 +read_input 4197 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 57847 lines remaining. +BLines (lines remaining after reading input) = 57847 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 57847 +read_input 4201 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: XOP_INSTRUCTIONS():: +parser returning with 57825 lines remaining. +BLines (lines remaining after reading input) = 57825 +============================================= +Creating a generator 254 +============================================= +ALines (lines before reading input) = 57825 +read_input 4204 +NONTERMINAL: XOP_INSTRUCTIONS notype +Adding XOP_INSTRUCTIONS to nonterminal dict +Nonterminal XOP_INSTRUCTIONS():: +Nonterminal name XOP_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 56852 lines remaining. +BLines (lines remaining after reading input) = 56852 +============================================= +Creating a generator 255 +============================================= +ALines (lines before reading input) = 56852 +read_input 4400 +NONTERMINAL: AVX_INSTRUCTIONS notype +Adding AVX_INSTRUCTIONS to nonterminal dict +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 56435 lines remaining. +BLines (lines remaining after reading input) = 56435 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 56435 +read_input 4528 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 56386 lines remaining. +BLines (lines remaining after reading input) = 56386 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 56386 +read_input 4544 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +REGISTERING UDELETE NOP0F1A +REGISTERING UDELETE NOP0F1B +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 56221 lines remaining. +BLines (lines remaining after reading input) = 56221 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 56221 +read_input 4577 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +REGISTERING UDELETE NOP0F1E +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 56134 lines remaining. +BLines (lines remaining after reading input) = 56134 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 56134 +read_input 4597 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55979 lines remaining. +BLines (lines remaining after reading input) = 55979 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55979 +read_input 4611 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55968 lines remaining. +BLines (lines remaining after reading input) = 55968 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55968 +read_input 4612 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55792 lines remaining. +BLines (lines remaining after reading input) = 55792 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55792 +read_input 4626 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55771 lines remaining. +BLines (lines remaining after reading input) = 55771 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55771 +read_input 4628 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55730 lines remaining. +BLines (lines remaining after reading input) = 55730 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55730 +read_input 4632 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55709 lines remaining. +BLines (lines remaining after reading input) = 55709 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55709 +read_input 4634 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55698 lines remaining. +BLines (lines remaining after reading input) = 55698 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55698 +read_input 4635 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55687 lines remaining. +BLines (lines remaining after reading input) = 55687 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55687 +read_input 4636 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55652 lines remaining. +BLines (lines remaining after reading input) = 55652 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55652 +read_input 4640 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55633 lines remaining. +BLines (lines remaining after reading input) = 55633 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55633 +read_input 4642 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55612 lines remaining. +BLines (lines remaining after reading input) = 55612 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55612 +read_input 4644 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55589 lines remaining. +BLines (lines remaining after reading input) = 55589 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55589 +read_input 4646 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55577 lines remaining. +BLines (lines remaining after reading input) = 55577 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55577 +read_input 4648 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55539 lines remaining. +BLines (lines remaining after reading input) = 55539 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55539 +read_input 4652 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55501 lines remaining. +BLines (lines remaining after reading input) = 55501 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55501 +read_input 4655 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +REGISTERING UDELETE NOP0F1C +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55436 lines remaining. +BLines (lines remaining after reading input) = 55436 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55436 +read_input 4667 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 55424 lines remaining. +BLines (lines remaining after reading input) = 55424 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55424 +read_input 4668 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 55412 lines remaining. +BLines (lines remaining after reading input) = 55412 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 55412 +read_input 4669 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 51974 lines remaining. +BLines (lines remaining after reading input) = 51974 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 51974 +read_input 5392 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 51943 lines remaining. +BLines (lines remaining after reading input) = 51943 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 51943 +read_input 5395 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 51876 lines remaining. +BLines (lines remaining after reading input) = 51876 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 51876 +read_input 5407 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 51864 lines remaining. +BLines (lines remaining after reading input) = 51864 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 51864 +read_input 5409 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 51829 lines remaining. +BLines (lines remaining after reading input) = 51829 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 51829 +read_input 5417 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 50964 lines remaining. +BLines (lines remaining after reading input) = 50964 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 50964 +read_input 5609 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 50843 lines remaining. +BLines (lines remaining after reading input) = 50843 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 50843 +read_input 5625 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 49363 lines remaining. +BLines (lines remaining after reading input) = 49363 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 49363 +read_input 5890 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 49287 lines remaining. +BLines (lines remaining after reading input) = 49287 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 49287 +read_input 5910 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 49276 lines remaining. +BLines (lines remaining after reading input) = 49276 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 49276 +read_input 5911 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 49035 lines remaining. +BLines (lines remaining after reading input) = 49035 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 49035 +read_input 5989 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 49005 lines remaining. +BLines (lines remaining after reading input) = 49005 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 49005 +read_input 5995 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48994 lines remaining. +BLines (lines remaining after reading input) = 48994 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48994 +read_input 5996 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48980 lines remaining. +BLines (lines remaining after reading input) = 48980 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48980 +read_input 5998 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48948 lines remaining. +BLines (lines remaining after reading input) = 48948 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48948 +read_input 6004 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48910 lines remaining. +BLines (lines remaining after reading input) = 48910 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48910 +read_input 6008 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48877 lines remaining. +BLines (lines remaining after reading input) = 48877 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48877 +read_input 6016 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48856 lines remaining. +BLines (lines remaining after reading input) = 48856 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48856 +read_input 6018 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 48845 lines remaining. +BLines (lines remaining after reading input) = 48845 +============================================= +Creating a generator 256 +============================================= +ALines (lines before reading input) = 48845 +read_input 6019 +NONTERMINAL: EVEX_INSTRUCTIONS notype +Adding EVEX_INSTRUCTIONS to nonterminal dict +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 48532 lines remaining. +BLines (lines remaining after reading input) = 48532 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 48532 +read_input 6043 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 48297 lines remaining. +BLines (lines remaining after reading input) = 48297 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 48297 +read_input 6061 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +REGISTERING UDELETE PREFETCH_RESERVED_0F0Dr2 +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 48295 lines remaining. +BLines (lines remaining after reading input) = 48295 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 48295 +read_input 6061 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 47696 lines remaining. +BLines (lines remaining after reading input) = 47696 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 47696 +read_input 6107 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 47683 lines remaining. +BLines (lines remaining after reading input) = 47683 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 47683 +read_input 6108 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 47630 lines remaining. +BLines (lines remaining after reading input) = 47630 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 47630 +read_input 6112 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 47603 lines remaining. +BLines (lines remaining after reading input) = 47603 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 47603 +read_input 6114 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 47550 lines remaining. +BLines (lines remaining after reading input) = 47550 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 47550 +read_input 6118 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 35951 lines remaining. +BLines (lines remaining after reading input) = 35951 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 35951 +read_input 7041 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 35754 lines remaining. +BLines (lines remaining after reading input) = 35754 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 35754 +read_input 7056 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 35625 lines remaining. +BLines (lines remaining after reading input) = 35625 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 35625 +read_input 7066 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 12253 lines remaining. +BLines (lines remaining after reading input) = 12253 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 12253 +read_input 8872 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 11561 lines remaining. +BLines (lines remaining after reading input) = 11561 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 11561 +read_input 8926 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 11404 lines remaining. +BLines (lines remaining after reading input) = 11404 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 11404 +read_input 8938 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 11091 lines remaining. +BLines (lines remaining after reading input) = 11091 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 11091 +read_input 8962 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 11067 lines remaining. +BLines (lines remaining after reading input) = 11067 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 11067 +read_input 8965 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 11051 lines remaining. +BLines (lines remaining after reading input) = 11051 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 11051 +read_input 8967 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 10816 lines remaining. +BLines (lines remaining after reading input) = 10816 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 10816 +read_input 8985 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 9567 lines remaining. +BLines (lines remaining after reading input) = 9567 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 9567 +read_input 9081 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 9491 lines remaining. +BLines (lines remaining after reading input) = 9491 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 9491 +read_input 9087 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 9256 lines remaining. +BLines (lines remaining after reading input) = 9256 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 9256 +read_input 9105 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 9111 lines remaining. +BLines (lines remaining after reading input) = 9111 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 9111 +read_input 9117 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 8735 lines remaining. +BLines (lines remaining after reading input) = 8735 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8735 +read_input 9147 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 8614 lines remaining. +BLines (lines remaining after reading input) = 8614 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8614 +read_input 9157 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 8509 lines remaining. +BLines (lines remaining after reading input) = 8509 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8509 +read_input 9165 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 8352 lines remaining. +BLines (lines remaining after reading input) = 8352 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8352 +read_input 9177 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 8219 lines remaining. +BLines (lines remaining after reading input) = 8219 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8219 +read_input 9188 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 8207 lines remaining. +BLines (lines remaining after reading input) = 8207 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8207 +read_input 9189 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 8014 lines remaining. +BLines (lines remaining after reading input) = 8014 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 8014 +read_input 9205 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: AVX_INSTRUCTIONS():: +parser returning with 7956 lines remaining. +BLines (lines remaining after reading input) = 7956 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 7956 +read_input 9210 +NONTERMINAL: AVX_INSTRUCTIONS notype +FOUND OLD PARSER FOR AVX_INSTRUCTIONS +Nonterminal AVX_INSTRUCTIONS():: +Nonterminal name AVX_INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 7799 lines remaining. +BLines (lines remaining after reading input) = 7799 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 7799 +read_input 9222 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 7774 lines remaining. +BLines (lines remaining after reading input) = 7774 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 7774 +read_input 9224 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 7751 lines remaining. +BLines (lines remaining after reading input) = 7751 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 7751 +read_input 9226 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: INSTRUCTIONS():: +parser returning with 7739 lines remaining. +BLines (lines remaining after reading input) = 7739 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 7739 +read_input 9227 +NONTERMINAL: INSTRUCTIONS notype +FOUND OLD PARSER FOR INSTRUCTIONS +Nonterminal INSTRUCTIONS():: +Nonterminal name INSTRUCTIONS +read_structured_input +Hit a nonterminal, returning at: EVEX_INSTRUCTIONS():: +parser returning with 7675 lines remaining. +BLines (lines remaining after reading input) = 7675 +============================================= +Creating a generator 257 +============================================= +ALines (lines before reading input) = 7675 +read_input 9232 +NONTERMINAL: EVEX_INSTRUCTIONS notype +FOUND OLD PARSER FOR EVEX_INSTRUCTIONS +Nonterminal EVEX_INSTRUCTIONS():: +Nonterminal name EVEX_INSTRUCTIONS +read_structured_input +parser returning with 0 lines remaining. +BLines (lines remaining after reading input) = 0 +DROPPING UNAME NOP0F1A +DROPPING UNAME NOP0F1A +DROPPING UNAME NOP0F1B +DROPPING UNAME NOP0F1B +DROPPING UNAME NOP0F1C +DROPPING UNAME NOP0F1C +DROPPING UNAME NOP0F1E +DROPPING UNAME NOP0F1E +DROPPING UNAME PREFETCH_RESERVED_0F0Dr2 +X9 need to splatter based on cases overlapping with scalar dispatch +Splattering because of conflicting 'other' conditions +X9 need to splatter based on cases overlapping with scalar dispatch +Splattering because of conflicting 'other' conditions +Length error: some instructions done and some are not done simultaneously +ilist len = 20 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:28 +bitpos:26 len-pattern:29 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:28 +bitpos:26 len-pattern:29 + + +NODE: + NOP inum=4581 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 0 n n n REP=3 + + NOP inum=4582 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 1 0 n n n REP=3 + + NOP inum=4583 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 1 1 n n n REP=3 + + NOP inum=4584 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 0 0 n n n REP=3 + + NOP inum=4585 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 0 1 n n n REP=3 + + NOP inum=4586 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 0 n n n REP=3 + + NOP inum=4587 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 0 REP=3 + + NOP inum=4588 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 1 REP=3 + + NOP inum=4589 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 0 REP=3 + + NOP inum=4590 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 1 REP=3 + + NOP inum=4591 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 0 REP=3 + + NOP inum=4592 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 1 REP=3 + + NOP inum=4593 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=0 + + NOP inum=4594 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=0 + + NOP inum=4595 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=28 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=0 CET=0 + + NOP inum=4596 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=29 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=1 MODE=2 CET=0 + + ENDBR32 inum=4598 iform_input=ENDBR32 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=1 + + ENDBR64 inum=4599 iform_input=ENDBR64 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=1 + + RDSSPD inum=4602 iform_input=RDSSPD_GPR32u32 isa_set=CET pattern len=28 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=0 CET=1 + + RDSSPQ inum=4603 iform_input=RDSSPQ_GPR64u64 isa_set=CET pattern len=29 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=1 MODE=2 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 21 +back_split_graph: based on 21 +BACKSPLIT fake bitpos: 21 real bitpos: 20 + + +BUILD ERROR: more than one leaf when ran out of bits: + NOP inum=4581 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 0 n n n REP=3 + + NOP inum=4582 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 1 0 n n n REP=3 + + NOP inum=4584 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 0 0 n n n REP=3 + + NOP inum=4586 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 0 n n n REP=3 + + + + +FALLBACK: we can parition on the 1s and 0s at bitpos 20 +NEED TO BACKSPLIT AT POSITION 20 +back_split_graph: based on 20 +BACKSPLIT fake bitpos: 20 real bitpos: 19 + + +BUILD ERROR: more than one leaf when ran out of bits: + NOP inum=4581 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 0 n n n REP=3 + + NOP inum=4584 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 0 0 n n n REP=3 + + + + +FALLBACK: we can parition on the 1s and 0s at bitpos 19 +NEED TO BACKSPLIT AT POSITION 19 +back_split_graph: based on 19 +BACKSPLIT fake bitpos: 19 real bitpos: 18 + + +BUILD ERROR: more than one leaf when ran out of bits: + NOP inum=4582 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 1 0 n n n REP=3 + + NOP inum=4586 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 0 n n n REP=3 + + + + +FALLBACK: we can parition on the 1s and 0s at bitpos 19 +NEED TO BACKSPLIT AT POSITION 19 +back_split_graph: based on 19 +BACKSPLIT fake bitpos: 19 real bitpos: 18 + +Length error: some instructions done and some are not done simultaneously +ilist len = 16 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:28 +bitpos:26 len-pattern:29 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:28 +bitpos:26 len-pattern:29 + + +NODE: + NOP inum=4583 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 1 1 n n n REP=3 + + NOP inum=4585 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 0 1 n n n REP=3 + + NOP inum=4587 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 0 REP=3 + + NOP inum=4588 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 1 REP=3 + + NOP inum=4589 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 0 REP=3 + + NOP inum=4590 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 1 REP=3 + + NOP inum=4591 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 0 REP=3 + + NOP inum=4592 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 1 REP=3 + + NOP inum=4593 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=0 + + NOP inum=4594 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=0 + + NOP inum=4595 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=28 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=0 CET=0 + + NOP inum=4596 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=29 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=1 MODE=2 CET=0 + + ENDBR32 inum=4598 iform_input=ENDBR32 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=1 + + ENDBR64 inum=4599 iform_input=ENDBR64 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=1 + + RDSSPD inum=4602 iform_input=RDSSPD_GPR32u32 isa_set=CET pattern len=28 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=0 CET=1 + + RDSSPQ inum=4603 iform_input=RDSSPQ_GPR64u64 isa_set=CET pattern len=29 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=1 MODE=2 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 20 +back_split_graph: based on 20 +BACKSPLIT fake bitpos: 20 real bitpos: 19 + +Length error: some instructions done and some are not done simultaneously +ilist len = 5 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:28 +bitpos:26 len-pattern:29 +bitpos:26 len-pattern:28 +bitpos:26 len-pattern:29 + + +NODE: + NOP inum=4585 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 0 1 n n n REP=3 + + NOP inum=4595 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=28 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=0 CET=0 + + NOP inum=4596 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=29 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=1 MODE=2 CET=0 + + RDSSPD inum=4602 iform_input=RDSSPD_GPR32u32 isa_set=CET pattern len=28 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=0 CET=1 + + RDSSPQ inum=4603 iform_input=RDSSPQ_GPR64u64 isa_set=CET pattern len=29 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 0 1 n n n REP=3 REXW=1 MODE=2 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 19 +back_split_graph: based on 19 +BACKSPLIT fake bitpos: 19 real bitpos: 18 + +Length error: some instructions done and some are not done simultaneously +ilist len = 11 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 + + +NODE: + NOP inum=4583 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 0 1 1 n n n REP=3 + + NOP inum=4587 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 0 REP=3 + + NOP inum=4588 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 1 REP=3 + + NOP inum=4589 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 0 REP=3 + + NOP inum=4590 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 1 REP=3 + + NOP inum=4591 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 0 REP=3 + + NOP inum=4592 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 1 REP=3 + + NOP inum=4593 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=0 + + NOP inum=4594 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=0 + + ENDBR32 inum=4598 iform_input=ENDBR32 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=1 + + ENDBR64 inum=4599 iform_input=ENDBR64 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 19 +back_split_graph: based on 19 +BACKSPLIT fake bitpos: 19 real bitpos: 18 + +Length error: some instructions done and some are not done simultaneously +ilist len = 10 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 + + +NODE: + NOP inum=4587 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 0 REP=3 + + NOP inum=4588 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 1 REP=3 + + NOP inum=4589 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 0 REP=3 + + NOP inum=4590 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 1 REP=3 + + NOP inum=4591 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 0 REP=3 + + NOP inum=4592 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 1 REP=3 + + NOP inum=4593 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=0 + + NOP inum=4594 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=0 + + ENDBR32 inum=4598 iform_input=ENDBR32 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=1 + + ENDBR64 inum=4599 iform_input=ENDBR64 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 24 +back_split_graph: based on 24 +BACKSPLIT fake bitpos: 24 real bitpos: 23 + +Length error: some instructions done and some are not done simultaneously +ilist len = 5 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 + + +NODE: + NOP inum=4587 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 0 REP=3 + + NOP inum=4589 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 0 REP=3 + + NOP inum=4591 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 0 REP=3 + + NOP inum=4593 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=0 + + ENDBR64 inum=4599 iform_input=ENDBR64 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 23 +back_split_graph: based on 23 +BACKSPLIT fake bitpos: 23 real bitpos: 22 + + +BUILD ERROR: more than one leaf when ran out of bits: + NOP inum=4587 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 0 REP=3 + + NOP inum=4589 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 0 REP=3 + + + + +FALLBACK: we can parition on the 1s and 0s at bitpos 22 +NEED TO BACKSPLIT AT POSITION 22 +back_split_graph: based on 22 +BACKSPLIT fake bitpos: 22 real bitpos: 21 + +Length error: some instructions done and some are not done simultaneously +ilist len = 3 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 + + +NODE: + NOP inum=4591 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 0 REP=3 + + NOP inum=4593 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=0 + + ENDBR64 inum=4599 iform_input=ENDBR64 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 0 REP=3 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 22 +back_split_graph: based on 22 +BACKSPLIT fake bitpos: 22 real bitpos: 21 + +Length error: some instructions done and some are not done simultaneously +ilist len = 5 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 + + +NODE: + NOP inum=4588 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 1 REP=3 + + NOP inum=4590 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 1 REP=3 + + NOP inum=4592 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 1 REP=3 + + NOP inum=4594 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=0 + + ENDBR32 inum=4598 iform_input=ENDBR32 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 23 +back_split_graph: based on 23 +BACKSPLIT fake bitpos: 23 real bitpos: 22 + + +BUILD ERROR: more than one leaf when ran out of bits: + NOP inum=4588 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 0 1 REP=3 + + NOP inum=4590 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 0 1 REP=3 + + + + +FALLBACK: we can parition on the 1s and 0s at bitpos 22 +NEED TO BACKSPLIT AT POSITION 22 +back_split_graph: based on 22 +BACKSPLIT fake bitpos: 22 real bitpos: 21 + +Length error: some instructions done and some are not done simultaneously +ilist len = 3 + + +ILIST: +bitpos:26 len-pattern:26 +bitpos:26 len-pattern:27 +bitpos:26 len-pattern:27 + + +NODE: + NOP inum=4592 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=26 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 1 1 1 REP=3 + + NOP inum=4594 iform_input=NOP_GPRv_GPRv_0F1E isa_set=PPRO pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=0 + + ENDBR32 inum=4598 iform_input=ENDBR32 isa_set=CET pattern len=27 + ipattern: 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 1 1 MOD=3 1 1 1 0 1 1 REP=3 CET=1 + +FALLBACK: we can parition on the 1s and 0s at bitpos 22 +back_split_graph: based on 22 +BACKSPLIT fake bitpos: 22 real bitpos: 21 + +FUNKY SPOT: bitpos 36 +Others: +MOVDIRI inum=4650 iform_input=MOVDIRI_MEMu32_GPR32u32 isa_set=MOVDIR pattern len=37 + ipattern: 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 0 0 1 m m MOD!=3 r r r n n n MODRM() REP=0 OSZ=0 REXW=0 + +MOVDIRI inum=4651 iform_input=MOVDIRI_MEMu64_GPR64u64 isa_set=MOVDIR pattern len=38 + ipattern: 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 1 1 0 0 1 m m MOD!=3 r r r n n n MODRM() REP=0 OSZ=0 MODE=2 REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING MOVDIRI inum 4650 -- already fine + REARRANGE needs to juggle: MOVDIRI inum 4651 + REARRANGE one pattern worked for MOVDIRI inum 4651 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 36 +FUNKY SPOT: bitpos 11 +Others: +LLWPCB inum=4394 isa_set=LWP pattern len=23 + ipattern: VEXVALID=3 0 0 0 1 0 0 1 0 VEX_PREFIX=0 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 MAP=9 1 1 MOD=3 0 0 0 n n n + +SLWPCB inum=4395 isa_set=LWP pattern len=23 + ipattern: VEXVALID=3 0 0 0 1 0 0 1 0 VEX_PREFIX=0 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 MAP=9 1 1 MOD=3 0 0 1 n n n + +LWPINS inum=4396 isa_set=LWP pattern len=23 + ipattern: VEXVALID=3 0 0 0 1 0 0 1 0 VEX_PREFIX=0 VL=0 MAP=10 m m MOD!=3 0 0 0 n n n MODRM() UIMM32() + +LWPINS inum=4397 isa_set=LWP pattern len=22 + ipattern: VEXVALID=3 0 0 0 1 0 0 1 0 VEX_PREFIX=0 VL=0 MAP=10 1 1 MOD=3 0 0 0 n n n UIMM32() + +LWPVAL inum=4398 isa_set=LWP pattern len=23 + ipattern: VEXVALID=3 0 0 0 1 0 0 1 0 VEX_PREFIX=0 VL=0 MAP=10 m m MOD!=3 0 0 1 n n n MODRM() UIMM32() + +LWPVAL inum=4399 isa_set=LWP pattern len=22 + ipattern: VEXVALID=3 0 0 0 1 0 0 1 0 VEX_PREFIX=0 VL=0 MAP=10 1 1 MOD=3 0 0 1 n n n UIMM32() + +Ones: +Zeros: +REARRANGE ATTEMPT using VEXDEST3 + SKIPPING LLWPCB inum 4394 -- already fine + SKIPPING SLWPCB inum 4395 -- already fine + REARRANGE needs to juggle: LWPINS inum 4396 + REARRANGE FAILED for VEXDEST3. Trying again... +REARRANGE ATTEMPT using VEXDEST210 + REARRANGE needs to juggle: LLWPCB inum 4394 + REARRANGE one pattern worked for LLWPCB inum 4394 + REARRANGE needs to juggle: SLWPCB inum 4395 + REARRANGE one pattern worked for SLWPCB inum 4395 + REARRANGE needs to juggle: LWPINS inum 4396 + REARRANGE FAILED for VEXDEST210. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: LLWPCB inum 4394 + REARRANGE one pattern worked for LLWPCB inum 4394 + REARRANGE needs to juggle: SLWPCB inum 4395 + REARRANGE one pattern worked for SLWPCB inum 4395 + SKIPPING LWPINS inum 4396 -- already fine + SKIPPING LWPINS inum 4397 -- already fine + SKIPPING LWPVAL inum 4398 -- already fine + SKIPPING LWPVAL inum 4399 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 10 +Others: +VPSHUFB inum=5747 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPSHUFB inum=5748 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n + +VPERMQ inum=5858 isa_set=AVX2 pattern len=26 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 0 VL=1 MAP=3 VEX_PREFIX=1 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VPERMQ inum=5859 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 0 VL=1 MAP=3 VEX_PREFIX=1 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPSHUFB inum 5747 -- already fine + SKIPPING VPSHUFB inum 5748 -- already fine + REARRANGE needs to juggle: VPERMQ inum 5858 + REARRANGE one pattern worked for VPERMQ inum 5858 + REARRANGE needs to juggle: VPERMQ inum 5859 + REARRANGE one pattern worked for VPERMQ inum 5859 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 10 +Others: +VPHADDW inum=5691 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPHADDW inum=5692 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n + +VPERMPD inum=5860 isa_set=AVX2 pattern len=26 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 1 VL=1 MAP=3 VEX_PREFIX=1 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VPERMPD inum=5861 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 0 0 0 0 0 0 1 VL=1 MAP=3 VEX_PREFIX=1 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPHADDW inum 5691 -- already fine + SKIPPING VPHADDW inum 5692 -- already fine + REARRANGE needs to juggle: VPERMPD inum 5860 + REARRANGE one pattern worked for VPERMPD inum 5860 + REARRANGE needs to juggle: VPERMPD inum 5861 + REARRANGE one pattern worked for VPERMPD inum 5861 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPSIGND inum=5089 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VL=0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPSIGND inum=5090 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VL=0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n + +VPSIGND inum=5753 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VL=1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPSIGND inum=5754 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VL=1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n + +VROUNDSS inum=5141 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VROUNDSS inum=5142 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSIGND inum 5089 -- already fine + SKIPPING VPSIGND inum 5090 -- already fine + SKIPPING VPSIGND inum 5753 -- already fine + SKIPPING VPSIGND inum 5754 -- already fine + REARRANGE needs to juggle: VROUNDSS inum 5141 + REARRANGE FAILED for VL. Trying again... +REARRANGE ATTEMPT using VEX_PREFIX + REARRANGE needs to juggle: VPSIGND inum 5089 + REARRANGE one pattern worked for VPSIGND inum 5089 + REARRANGE needs to juggle: VPSIGND inum 5090 + REARRANGE one pattern worked for VPSIGND inum 5090 + REARRANGE needs to juggle: VPSIGND inum 5753 + REARRANGE one pattern worked for VPSIGND inum 5753 + REARRANGE needs to juggle: VPSIGND inum 5754 + REARRANGE one pattern worked for VPSIGND inum 5754 + SKIPPING VROUNDSS inum 5141 -- already fine + SKIPPING VROUNDSS inum 5142 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPSIGND inum=5089 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 VL=0 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPSIGND inum=5090 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 VL=0 MAP=2 1 1 MOD=3 r r r n n n + +VPSIGND inum=5753 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 VL=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPSIGND inum=5754 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 VL=1 MAP=2 1 1 MOD=3 r r r n n n + +VROUNDSS inum=5141 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VROUNDSS inum=5142 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSIGND inum 5089 -- already fine + SKIPPING VPSIGND inum 5090 -- already fine + SKIPPING VPSIGND inum 5753 -- already fine + SKIPPING VPSIGND inum 5754 -- already fine + REARRANGE needs to juggle: VROUNDSS inum 5141 + REARRANGE FAILED for VL. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VPSIGND inum 5089 + REARRANGE one pattern worked for VPSIGND inum 5089 + REARRANGE needs to juggle: VPSIGND inum 5090 + REARRANGE one pattern worked for VPSIGND inum 5090 + REARRANGE needs to juggle: VPSIGND inum 5753 + REARRANGE one pattern worked for VPSIGND inum 5753 + REARRANGE needs to juggle: VPSIGND inum 5754 + REARRANGE one pattern worked for VPSIGND inum 5754 + SKIPPING VROUNDSS inum 5141 -- already fine + SKIPPING VROUNDSS inum 5142 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPMULHRSW inum=5069 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VL=0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPMULHRSW inum=5070 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VL=0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n + +VPMULHRSW inum=5733 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VL=1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPMULHRSW inum=5734 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VL=1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n + +VROUNDSD inum=5139 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VROUNDSD inum=5140 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPMULHRSW inum 5069 -- already fine + SKIPPING VPMULHRSW inum 5070 -- already fine + SKIPPING VPMULHRSW inum 5733 -- already fine + SKIPPING VPMULHRSW inum 5734 -- already fine + REARRANGE needs to juggle: VROUNDSD inum 5139 + REARRANGE FAILED for VL. Trying again... +REARRANGE ATTEMPT using VEX_PREFIX + REARRANGE needs to juggle: VPMULHRSW inum 5069 + REARRANGE one pattern worked for VPMULHRSW inum 5069 + REARRANGE needs to juggle: VPMULHRSW inum 5070 + REARRANGE one pattern worked for VPMULHRSW inum 5070 + REARRANGE needs to juggle: VPMULHRSW inum 5733 + REARRANGE one pattern worked for VPMULHRSW inum 5733 + REARRANGE needs to juggle: VPMULHRSW inum 5734 + REARRANGE one pattern worked for VPMULHRSW inum 5734 + SKIPPING VROUNDSD inum 5139 -- already fine + SKIPPING VROUNDSD inum 5140 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPMULHRSW inum=5069 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 VL=0 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPMULHRSW inum=5070 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 VL=0 MAP=2 1 1 MOD=3 r r r n n n + +VPMULHRSW inum=5733 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 VL=1 MAP=2 m m MOD!=3 r r r n n n MODRM() + +VPMULHRSW inum=5734 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 VL=1 MAP=2 1 1 MOD=3 r r r n n n + +VROUNDSD inum=5139 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VROUNDSD inum=5140 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 0 0 0 1 0 1 1 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPMULHRSW inum 5069 -- already fine + SKIPPING VPMULHRSW inum 5070 -- already fine + SKIPPING VPMULHRSW inum 5733 -- already fine + SKIPPING VPMULHRSW inum 5734 -- already fine + REARRANGE needs to juggle: VROUNDSD inum 5139 + REARRANGE FAILED for VL. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VPMULHRSW inum 5069 + REARRANGE one pattern worked for VPMULHRSW inum 5069 + REARRANGE needs to juggle: VPMULHRSW inum 5070 + REARRANGE one pattern worked for VPMULHRSW inum 5070 + REARRANGE needs to juggle: VPMULHRSW inum 5733 + REARRANGE one pattern worked for VPMULHRSW inum 5733 + REARRANGE needs to juggle: VPMULHRSW inum 5734 + REARRANGE one pattern worked for VPMULHRSW inum 5734 + SKIPPING VROUNDSD inum 5139 -- already fine + SKIPPING VROUNDSD inum 5140 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VBROADCASTSS inum=4859 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 0 REXW=0 VL=0 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VBROADCASTSS inum=4860 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 0 REXW=0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VBROADCASTSS inum=5886 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VBROADCASTSS inum=5887 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VINSERTF128 inum=4863 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 0 REXW=0 VL=1 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VINSERTF128 inum=4864 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 0 REXW=0 VL=1 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VBROADCASTSS inum 4859 -- already fine + SKIPPING VBROADCASTSS inum 4860 -- already fine + REARRANGE needs to juggle: VBROADCASTSS inum 5886 + REARRANGE one pattern worked for VBROADCASTSS inum 5886 + REARRANGE needs to juggle: VBROADCASTSS inum 5887 + REARRANGE one pattern worked for VBROADCASTSS inum 5887 + SKIPPING VINSERTF128 inum 4863 -- already fine + SKIPPING VINSERTF128 inum 4864 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VEXTRACTF128 inum=4813 isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 1 REXW=0 VL=1 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VEXTRACTF128 inum=4814 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 1 REXW=0 VL=1 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +VBROADCASTSD inum=4861 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 1 REXW=0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VBROADCASTSD inum=5888 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VEXTRACTF128 inum 4813 -- already fine + SKIPPING VEXTRACTF128 inum 4814 -- already fine + SKIPPING VBROADCASTSD inum 4861 -- already fine + REARRANGE needs to juggle: VBROADCASTSD inum 5888 + REARRANGE one pattern worked for VBROADCASTSD inum 5888 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPABSB inum=4981 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSB inum=4982 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPABSB inum=5625 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSB inum=5626 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPABSB inum 4981 -- already fine + SKIPPING VPABSB inum 4982 -- already fine + REARRANGE needs to juggle: VPABSB inum 5625 + REARRANGE one pattern worked for VPABSB inum 5625 + REARRANGE needs to juggle: VPABSB inum 5626 + REARRANGE one pattern worked for VPABSB inum 5626 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPABSB inum=4981 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSB inum=4982 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPABSB inum=5625 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSB inum=5626 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MAP + SKIPPING VPABSB inum 4981 -- already fine + SKIPPING VPABSB inum 4982 -- already fine + REARRANGE needs to juggle: VPABSB inum 5625 + REARRANGE one pattern worked for VPABSB inum 5625 + REARRANGE needs to juggle: VPABSB inum 5626 + REARRANGE one pattern worked for VPABSB inum 5626 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPABSW inum=4983 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSW inum=4984 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPABSW inum=5627 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSW inum=5628 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VCVTPS2PH inum=5413 isa_set=F16C pattern len=26 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() REXW=0 + +VCVTPS2PH inum=5414 isa_set=F16C pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() REXW=0 + +VCVTPS2PH inum=5415 isa_set=F16C pattern len=26 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() REXW=0 + +VCVTPS2PH inum=5416 isa_set=F16C pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() REXW=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPABSW inum 4983 -- already fine + SKIPPING VPABSW inum 4984 -- already fine + REARRANGE needs to juggle: VPABSW inum 5627 + REARRANGE one pattern worked for VPABSW inum 5627 + REARRANGE needs to juggle: VPABSW inum 5628 + REARRANGE one pattern worked for VPABSW inum 5628 + REARRANGE needs to juggle: VCVTPS2PH inum 5413 + REARRANGE one pattern worked for VCVTPS2PH inum 5413 + REARRANGE needs to juggle: VCVTPS2PH inum 5414 + REARRANGE one pattern worked for VCVTPS2PH inum 5414 + REARRANGE needs to juggle: VCVTPS2PH inum 5415 + REARRANGE one pattern worked for VCVTPS2PH inum 5415 + REARRANGE needs to juggle: VCVTPS2PH inum 5416 + REARRANGE one pattern worked for VCVTPS2PH inum 5416 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPABSW inum=4983 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSW inum=4984 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPABSW inum=5627 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSW inum=5628 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VCVTPS2PH inum=5413 isa_set=F16C pattern len=26 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() REXW=0 + +VCVTPS2PH inum=5414 isa_set=F16C pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() REXW=0 + +VCVTPS2PH inum=5415 isa_set=F16C pattern len=26 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() REXW=0 + +VCVTPS2PH inum=5416 isa_set=F16C pattern len=25 + ipattern: VEXVALID=1 0 0 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() REXW=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using MAP + SKIPPING VPABSW inum 4983 -- already fine + SKIPPING VPABSW inum 4984 -- already fine + REARRANGE needs to juggle: VPABSW inum 5627 + REARRANGE one pattern worked for VPABSW inum 5627 + REARRANGE needs to juggle: VPABSW inum 5628 + REARRANGE one pattern worked for VPABSW inum 5628 + REARRANGE needs to juggle: VCVTPS2PH inum 5413 + REARRANGE one pattern worked for VCVTPS2PH inum 5413 + REARRANGE needs to juggle: VCVTPS2PH inum 5414 + REARRANGE one pattern worked for VCVTPS2PH inum 5414 + REARRANGE needs to juggle: VCVTPS2PH inum 5415 + REARRANGE one pattern worked for VCVTPS2PH inum 5415 + REARRANGE needs to juggle: VCVTPS2PH inum 5416 + REARRANGE one pattern worked for VCVTPS2PH inum 5416 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPABSD inum=4985 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSD inum=4986 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPABSD inum=5629 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSD inum=5630 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPABSD inum 4985 -- already fine + SKIPPING VPABSD inum 4986 -- already fine + REARRANGE needs to juggle: VPABSD inum 5629 + REARRANGE one pattern worked for VPABSD inum 5629 + REARRANGE needs to juggle: VPABSD inum 5630 + REARRANGE one pattern worked for VPABSD inum 5630 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPABSD inum=4985 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSD inum=4986 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPABSD inum=5629 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPABSD inum=5630 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MAP + SKIPPING VPABSD inum 4985 -- already fine + SKIPPING VPABSD inum 4986 -- already fine + REARRANGE needs to juggle: VPABSD inum 5629 + REARRANGE one pattern worked for VPABSD inum 5629 + REARRANGE needs to juggle: VPABSD inum 5630 + REARRANGE one pattern worked for VPABSD inum 5630 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPMOVZXBW inum=5322 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPMOVZXBW inum=5323 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPMOVZXBW inum=5832 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPMOVZXBW inum=5833 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +KSHIFTRW inum=7052 iform_input=KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 isa_set=AVX512F_KOP pattern len=25 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 UIMM8() + +KSHIFTRB inum=8911 iform_input=KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 isa_set=AVX512DQ_KOP pattern len=25 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPMOVZXBW inum 5322 -- already fine + SKIPPING VPMOVZXBW inum 5323 -- already fine + SKIPPING VPMOVZXBW inum 5832 -- already fine + SKIPPING VPMOVZXBW inum 5833 -- already fine + REARRANGE needs to juggle: KSHIFTRW inum 7052 + REARRANGE one pattern worked for KSHIFTRW inum 7052 + REARRANGE needs to juggle: KSHIFTRB inum 8911 + REARRANGE one pattern worked for KSHIFTRB inum 8911 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPMOVZXBD inum=5324 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPMOVZXBD inum=5325 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPMOVZXBD inum=5834 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPMOVZXBD inum=5835 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +KSHIFTRD inum=8912 iform_input=KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 1 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 UIMM8() + +KSHIFTRQ inum=8913 iform_input=KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 0 0 1 1 0 0 0 1 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPMOVZXBD inum 5324 -- already fine + SKIPPING VPMOVZXBD inum 5325 -- already fine + SKIPPING VPMOVZXBD inum 5834 -- already fine + SKIPPING VPMOVZXBD inum 5835 -- already fine + REARRANGE needs to juggle: KSHIFTRD inum 8912 + REARRANGE one pattern worked for KSHIFTRD inum 8912 + REARRANGE needs to juggle: KSHIFTRQ inum 8913 + REARRANGE one pattern worked for KSHIFTRQ inum 8913 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VDPPD inum=4815 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VDPPD inum=4816 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +VPHMINPOSUW inum=4987 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPHMINPOSUW inum=4988 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VEX_PREFIX=1 MAP=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +KANDW inum=7042 iform_input=KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KANDB inum=8876 iform_input=KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KANDD inum=8877 iform_input=KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +KANDQ inum=8881 iform_input=KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 0 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VDPPD inum 4815 -- already fine + SKIPPING VDPPD inum 4816 -- already fine + REARRANGE needs to juggle: VPHMINPOSUW inum 4987 + REARRANGE one pattern worked for VPHMINPOSUW inum 4987 + REARRANGE needs to juggle: VPHMINPOSUW inum 4988 + REARRANGE one pattern worked for VPHMINPOSUW inum 4988 + REARRANGE needs to juggle: KANDW inum 7042 + REARRANGE one pattern worked for KANDW inum 7042 + REARRANGE needs to juggle: KANDB inum 8876 + REARRANGE one pattern worked for KANDB inum 8876 + REARRANGE needs to juggle: KANDD inum 8877 + REARRANGE one pattern worked for KANDD inum 8877 + REARRANGE needs to juggle: KANDQ inum 8881 + REARRANGE one pattern worked for KANDQ inum 8881 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VMPSADBW inum=5243 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VMPSADBW inum=5244 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +VMPSADBW inum=5791 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VL=1 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VMPSADBW inum=5792 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VL=1 VEX_PREFIX=1 MAP=3 1 1 MOD=3 r r r n n n UIMM8() + +KANDNW inum=7041 iform_input=KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KANDNB inum=8878 iform_input=KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KANDND inum=8879 iform_input=KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +KANDNQ inum=8880 iform_input=KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 0 1 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VMPSADBW inum 5243 -- already fine + SKIPPING VMPSADBW inum 5244 -- already fine + SKIPPING VMPSADBW inum 5791 -- already fine + SKIPPING VMPSADBW inum 5792 -- already fine + REARRANGE needs to juggle: KANDNW inum 7041 + REARRANGE one pattern worked for KANDNW inum 7041 + REARRANGE needs to juggle: KANDNB inum 8878 + REARRANGE one pattern worked for KANDNB inum 8878 + REARRANGE needs to juggle: KANDND inum 8879 + REARRANGE one pattern worked for KANDND inum 8879 + REARRANGE needs to juggle: KANDNQ inum 8880 + REARRANGE one pattern worked for KANDNQ inum 8880 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPSRLVD inum=5898 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VPSRLVD inum=5899 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=0 1 1 MOD=3 r r r n n n + +VPSRLVD inum=5900 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VPSRLVD inum=5901 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 1 1 MOD=3 r r r n n n + +VPSRLVQ inum=5902 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VPSRLVQ inum=5903 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=1 1 1 MOD=3 r r r n n n + +VPSRLVQ inum=5904 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VPSRLVQ inum=5905 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 1 1 MOD=3 r r r n n n + +KORW inum=7050 iform_input=KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KORB inum=8902 iform_input=KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KORD inum=8903 iform_input=KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +KORQ inum=8904 iform_input=KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSRLVD inum 5898 -- already fine + SKIPPING VPSRLVD inum 5899 -- already fine + SKIPPING VPSRLVD inum 5900 -- already fine + SKIPPING VPSRLVD inum 5901 -- already fine + SKIPPING VPSRLVQ inum 5902 -- already fine + SKIPPING VPSRLVQ inum 5903 -- already fine + SKIPPING VPSRLVQ inum 5904 -- already fine + SKIPPING VPSRLVQ inum 5905 -- already fine + REARRANGE needs to juggle: KORW inum 7050 + REARRANGE one pattern worked for KORW inum 7050 + REARRANGE needs to juggle: KORB inum 8902 + REARRANGE one pattern worked for KORB inum 8902 + REARRANGE needs to juggle: KORD inum 8903 + REARRANGE one pattern worked for KORD inum 8903 + REARRANGE needs to juggle: KORQ inum 8904 + REARRANGE one pattern worked for KORQ inum 8904 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPSRLVD inum=5900 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VPSRLVD inum=5901 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 1 1 MOD=3 r r r n n n + +VPSRLVQ inum=5904 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VPSRLVQ inum=5905 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 1 1 MOD=3 r r r n n n + +KORW inum=7050 iform_input=KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n REXW=0 + +KORB inum=8902 iform_input=KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n REXW=0 + +KORD inum=8903 iform_input=KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n REXW=1 + +KORQ inum=8904 iform_input=KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 0 1 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using MAP + SKIPPING VPSRLVD inum 5900 -- already fine + SKIPPING VPSRLVD inum 5901 -- already fine + SKIPPING VPSRLVQ inum 5904 -- already fine + SKIPPING VPSRLVQ inum 5905 -- already fine + REARRANGE needs to juggle: KORW inum 7050 + REARRANGE one pattern worked for KORW inum 7050 + REARRANGE needs to juggle: KORB inum 8902 + REARRANGE one pattern worked for KORB inum 8902 + REARRANGE needs to juggle: KORD inum 8903 + REARRANGE one pattern worked for KORD inum 8903 + REARRANGE needs to juggle: KORQ inum 8904 + REARRANGE one pattern worked for KORQ inum 8904 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPERM2I128 inum=5856 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=3 REXW=0 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VPERM2I128 inum=5857 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=3 REXW=0 1 1 MOD=3 r r r n n n UIMM8() + +VPSRAVD inum=5906 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 MAP=2 VEX_PREFIX=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 + +VPSRAVD inum=5907 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 MAP=2 VEX_PREFIX=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 + +VPSRAVD inum=5908 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 MAP=2 VEX_PREFIX=1 m m MOD!=3 r r r n n n MODRM() VL=1 REXW=0 + +VPSRAVD inum=5909 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 MAP=2 VEX_PREFIX=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KXNORW inum=7054 iform_input=KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KXNORB inum=8920 iform_input=KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KXNORD inum=8921 iform_input=KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +KXNORQ inum=8922 iform_input=KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPERM2I128 inum 5856 -- already fine + SKIPPING VPERM2I128 inum 5857 -- already fine + REARRANGE needs to juggle: VPSRAVD inum 5906 + REARRANGE one pattern worked for VPSRAVD inum 5906 + REARRANGE needs to juggle: VPSRAVD inum 5907 + REARRANGE one pattern worked for VPSRAVD inum 5907 + REARRANGE needs to juggle: VPSRAVD inum 5908 + REARRANGE one pattern worked for VPSRAVD inum 5908 + REARRANGE needs to juggle: VPSRAVD inum 5909 + REARRANGE one pattern worked for VPSRAVD inum 5909 + REARRANGE needs to juggle: KXNORW inum 7054 + REARRANGE one pattern worked for KXNORW inum 7054 + REARRANGE needs to juggle: KXNORB inum 8920 + REARRANGE one pattern worked for KXNORB inum 8920 + REARRANGE needs to juggle: KXNORD inum 8921 + REARRANGE one pattern worked for KXNORD inum 8921 + REARRANGE needs to juggle: KXNORQ inum 8922 + REARRANGE one pattern worked for KXNORQ inum 8922 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPERM2I128 inum=5856 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=3 REXW=0 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VPERM2I128 inum=5857 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=3 REXW=0 1 1 MOD=3 r r r n n n UIMM8() + +VPSRAVD inum=5908 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 MAP=2 VEX_PREFIX=1 m m MOD!=3 r r r n n n MODRM() REXW=0 + +VPSRAVD inum=5909 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 MAP=2 VEX_PREFIX=1 1 1 MOD=3 r r r n n n REXW=0 + +KXNORW inum=7054 iform_input=KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n REXW=0 + +KXNORB inum=8920 iform_input=KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n REXW=0 + +KXNORD inum=8921 iform_input=KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n REXW=1 + +KXNORQ inum=8922 iform_input=KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 0 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPERM2I128 inum 5856 -- already fine + SKIPPING VPERM2I128 inum 5857 -- already fine + REARRANGE needs to juggle: VPSRAVD inum 5908 + REARRANGE one pattern worked for VPSRAVD inum 5908 + REARRANGE needs to juggle: VPSRAVD inum 5909 + REARRANGE one pattern worked for VPSRAVD inum 5909 + SKIPPING KXNORW inum 7054 -- already fine + SKIPPING KXNORB inum 8920 -- already fine + SKIPPING KXNORD inum 8921 -- already fine + SKIPPING KXNORQ inum 8922 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPSLLVD inum=5890 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VPSLLVD inum=5891 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=0 1 1 MOD=3 r r r n n n + +VPSLLVD inum=5892 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VPSLLVD inum=5893 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 1 1 MOD=3 r r r n n n + +VPSLLVQ inum=5894 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLVQ inum=5895 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=0 MAP=2 VEX_PREFIX=1 REXW=1 1 1 MOD=3 r r r n n n + +VPSLLVQ inum=5896 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLVQ inum=5897 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 1 1 MOD=3 r r r n n n + +KXORW inum=7055 iform_input=KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KXORB inum=8923 iform_input=KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +KXORD inum=8924 iform_input=KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +KXORQ inum=8925 iform_input=KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=1 REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSLLVD inum 5890 -- already fine + SKIPPING VPSLLVD inum 5891 -- already fine + SKIPPING VPSLLVD inum 5892 -- already fine + SKIPPING VPSLLVD inum 5893 -- already fine + SKIPPING VPSLLVQ inum 5894 -- already fine + SKIPPING VPSLLVQ inum 5895 -- already fine + SKIPPING VPSLLVQ inum 5896 -- already fine + SKIPPING VPSLLVQ inum 5897 -- already fine + REARRANGE needs to juggle: KXORW inum 7055 + REARRANGE one pattern worked for KXORW inum 7055 + REARRANGE needs to juggle: KXORB inum 8923 + REARRANGE one pattern worked for KXORB inum 8923 + REARRANGE needs to juggle: KXORD inum 8924 + REARRANGE one pattern worked for KXORD inum 8924 + REARRANGE needs to juggle: KXORQ inum 8925 + REARRANGE one pattern worked for KXORQ inum 8925 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPSLLVD inum=5892 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VPSLLVD inum=5893 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=0 1 1 MOD=3 r r r n n n + +VPSLLVQ inum=5896 isa_set=AVX2 pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLVQ inum=5897 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 MAP=2 VEX_PREFIX=1 REXW=1 1 1 MOD=3 r r r n n n + +KXORW inum=7055 iform_input=KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n REXW=0 + +KXORB inum=8923 iform_input=KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n REXW=0 + +KXORD inum=8924 iform_input=KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n REXW=1 + +KXORQ inum=8925 iform_input=KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=22 + ipattern: VEXVALID=1 0 1 0 0 0 1 1 1 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n REXW=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using MAP + SKIPPING VPSLLVD inum 5892 -- already fine + SKIPPING VPSLLVD inum 5893 -- already fine + SKIPPING VPSLLVQ inum 5896 -- already fine + SKIPPING VPSLLVQ inum 5897 -- already fine + REARRANGE needs to juggle: KXORW inum 7055 + REARRANGE one pattern worked for KXORW inum 7055 + REARRANGE needs to juggle: KXORB inum 8923 + REARRANGE one pattern worked for KXORB inum 8923 + REARRANGE needs to juggle: KXORD inum 8924 + REARRANGE one pattern worked for KXORD inum 8924 + REARRANGE needs to juggle: KXORQ inum 8925 + REARRANGE one pattern worked for KXORQ inum 8925 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPERMIL2PD inum=4536 isa_set=XOP pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=3 REXW=0 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VPERMIL2PD inum=4537 isa_set=XOP pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=3 REXW=0 1 1 MOD=3 r r r n n n SE_IMM8() + +VPERMIL2PD inum=4538 isa_set=XOP pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=3 REXW=0 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VPERMIL2PD inum=4539 isa_set=XOP pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=3 REXW=0 1 1 MOD=3 r r r n n n SE_IMM8() + +VPERMIL2PD inum=4540 isa_set=XOP pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=3 REXW=1 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VPERMIL2PD inum=4541 isa_set=XOP pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=3 REXW=1 1 1 MOD=3 r r r n n n SE_IMM8() + +VPERMIL2PD inum=4542 isa_set=XOP pattern len=24 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=3 REXW=1 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VPERMIL2PD inum=4543 isa_set=XOP pattern len=23 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=3 REXW=1 1 1 MOD=3 r r r n n n SE_IMM8() + +LDTILECFG inum=9210 iform_input=LDTILECFG_MEM isa_set=AMX_TILE pattern len=26 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VEX_PREFIX=0 MAP=2 m m MOD!=3 0 0 0 n n n MODRM() VL=0 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +STTILECFG inum=9211 iform_input=STTILECFG_MEM isa_set=AMX_TILE pattern len=26 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 0 0 0 n n n MODRM() VL=0 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +TILERELEASE inum=9219 iform_input=TILERELEASE isa_set=AMX_TILE pattern len=25 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VEX_PREFIX=0 MAP=2 1 1 MOD=3 0 0 0 0 0 0 VL=0 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +TILEZERO inum=9221 iform_input=TILEZERO_TMMu32 isa_set=AMX_TILE pattern len=25 + ipattern: VEXVALID=1 0 1 0 0 1 0 0 1 VEX_PREFIX=2 MAP=2 1 1 MOD=3 r r r 0 0 0 VL=0 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPERMIL2PD inum 4536 -- already fine + SKIPPING VPERMIL2PD inum 4537 -- already fine + SKIPPING VPERMIL2PD inum 4538 -- already fine + SKIPPING VPERMIL2PD inum 4539 -- already fine + SKIPPING VPERMIL2PD inum 4540 -- already fine + SKIPPING VPERMIL2PD inum 4541 -- already fine + SKIPPING VPERMIL2PD inum 4542 -- already fine + SKIPPING VPERMIL2PD inum 4543 -- already fine + REARRANGE needs to juggle: LDTILECFG inum 9210 + REARRANGE one pattern worked for LDTILECFG inum 9210 + REARRANGE needs to juggle: STTILECFG inum 9211 + REARRANGE one pattern worked for STTILECFG inum 9211 + REARRANGE needs to juggle: TILERELEASE inum 9219 + REARRANGE one pattern worked for TILERELEASE inum 9219 + REARRANGE needs to juggle: TILEZERO inum 9221 + REARRANGE one pattern worked for TILEZERO inum 9221 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VMOVMSKPD inum=5305 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVMSKPD inum=5306 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVMSKPS inum=5307 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VL=0 VEX_PREFIX=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVMSKPS inum=5308 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VL=1 VEX_PREFIX=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPDPBUSD inum=9189 iform_input=VPDPBUSD_XMMi32_XMMu32_XMMu32 isa_set=AVX_VNNI pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 REXW=0 + +VPDPBUSD inum=9190 iform_input=VPDPBUSD_XMMi32_XMMu32_MEMu32 isa_set=AVX_VNNI pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 + +VPDPBUSD inum=9191 iform_input=VPDPBUSD_YMMi32_YMMu32_YMMu32 isa_set=AVX_VNNI pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +VPDPBUSD inum=9192 iform_input=VPDPBUSD_YMMi32_YMMu32_MEMu32 isa_set=AVX_VNNI pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 REXW=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VMOVMSKPD inum 5305 -- already fine + SKIPPING VMOVMSKPD inum 5306 -- already fine + SKIPPING VMOVMSKPS inum 5307 -- already fine + SKIPPING VMOVMSKPS inum 5308 -- already fine + REARRANGE needs to juggle: VPDPBUSD inum 9189 + REARRANGE one pattern worked for VPDPBUSD inum 9189 + REARRANGE needs to juggle: VPDPBUSD inum 9190 + REARRANGE one pattern worked for VPDPBUSD inum 9190 + REARRANGE needs to juggle: VPDPBUSD inum 9191 + REARRANGE one pattern worked for VPDPBUSD inum 9191 + REARRANGE needs to juggle: VPDPBUSD inum 9192 + REARRANGE one pattern worked for VPDPBUSD inum 9192 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VSQRTPD inum=5163 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VSQRTPD inum=5164 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VSQRTPD inum=5165 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VSQRTPD inum=5166 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VSQRTPS inum=5167 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=0 VEX_PREFIX=0 VEXDEST3=0b1 VEXDEST210=0b111 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSQRTPS inum=5168 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=0 VEX_PREFIX=0 VEXDEST3=0b1 VEXDEST210=0b111 MAP=1 1 1 MOD=3 r r r n n n + +VSQRTPS inum=5169 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=1 VEX_PREFIX=0 VEXDEST3=0b1 VEXDEST210=0b111 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSQRTPS inum=5170 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VL=1 VEX_PREFIX=0 VEXDEST3=0b1 VEXDEST210=0b111 MAP=1 1 1 MOD=3 r r r n n n + +VSQRTSD inum=5171 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSQRTSD inum=5172 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VSQRTSS inum=5173 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=3 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSQRTSS inum=5174 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=3 MAP=1 1 1 MOD=3 r r r n n n + +VPDPBUSDS inum=9193 iform_input=VPDPBUSDS_XMMi32_XMMu32_XMMu32 isa_set=AVX_VNNI pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 REXW=0 + +VPDPBUSDS inum=9194 iform_input=VPDPBUSDS_XMMi32_XMMu32_MEMu32 isa_set=AVX_VNNI pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 + +VPDPBUSDS inum=9195 iform_input=VPDPBUSDS_YMMi32_YMMu32_YMMu32 isa_set=AVX_VNNI pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +VPDPBUSDS inum=9196 iform_input=VPDPBUSDS_YMMi32_YMMu32_MEMu32 isa_set=AVX_VNNI pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 REXW=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VSQRTPD inum 5163 -- already fine + SKIPPING VSQRTPD inum 5164 -- already fine + SKIPPING VSQRTPD inum 5165 -- already fine + SKIPPING VSQRTPD inum 5166 -- already fine + SKIPPING VSQRTPS inum 5167 -- already fine + SKIPPING VSQRTPS inum 5168 -- already fine + SKIPPING VSQRTPS inum 5169 -- already fine + SKIPPING VSQRTPS inum 5170 -- already fine + REARRANGE needs to juggle: VSQRTSD inum 5171 + REARRANGE FAILED for VL. Trying again... +REARRANGE ATTEMPT using VEX_PREFIX + REARRANGE needs to juggle: VSQRTPD inum 5163 + REARRANGE one pattern worked for VSQRTPD inum 5163 + REARRANGE needs to juggle: VSQRTPD inum 5164 + REARRANGE one pattern worked for VSQRTPD inum 5164 + REARRANGE needs to juggle: VSQRTPD inum 5165 + REARRANGE one pattern worked for VSQRTPD inum 5165 + REARRANGE needs to juggle: VSQRTPD inum 5166 + REARRANGE one pattern worked for VSQRTPD inum 5166 + REARRANGE needs to juggle: VSQRTPS inum 5167 + REARRANGE one pattern worked for VSQRTPS inum 5167 + REARRANGE needs to juggle: VSQRTPS inum 5168 + REARRANGE one pattern worked for VSQRTPS inum 5168 + REARRANGE needs to juggle: VSQRTPS inum 5169 + REARRANGE one pattern worked for VSQRTPS inum 5169 + REARRANGE needs to juggle: VSQRTPS inum 5170 + REARRANGE one pattern worked for VSQRTPS inum 5170 + SKIPPING VSQRTSD inum 5171 -- already fine + SKIPPING VSQRTSD inum 5172 -- already fine + SKIPPING VSQRTSS inum 5173 -- already fine + SKIPPING VSQRTSS inum 5174 -- already fine + SKIPPING VPDPBUSDS inum 9193 -- already fine + SKIPPING VPDPBUSDS inum 9194 -- already fine + SKIPPING VPDPBUSDS inum 9195 -- already fine + SKIPPING VPDPBUSDS inum 9196 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VSQRTPD inum=5163 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VSQRTPD inum=5164 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VSQRTPD inum=5165 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VSQRTPD inum=5166 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPDPBUSDS inum=9193 iform_input=VPDPBUSDS_XMMi32_XMMu32_XMMu32 isa_set=AVX_VNNI pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 REXW=0 + +VPDPBUSDS inum=9194 iform_input=VPDPBUSDS_XMMi32_XMMu32_MEMu32 isa_set=AVX_VNNI pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 + +VPDPBUSDS inum=9195 iform_input=VPDPBUSDS_YMMi32_YMMu32_YMMu32 isa_set=AVX_VNNI pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 REXW=0 + +VPDPBUSDS inum=9196 iform_input=VPDPBUSDS_YMMi32_YMMu32_MEMu32 isa_set=AVX_VNNI pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 0 0 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 REXW=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VSQRTPD inum 5163 -- already fine + SKIPPING VSQRTPD inum 5164 -- already fine + SKIPPING VSQRTPD inum 5165 -- already fine + SKIPPING VSQRTPD inum 5166 -- already fine + REARRANGE needs to juggle: VPDPBUSDS inum 9193 + REARRANGE one pattern worked for VPDPBUSDS inum 9193 + REARRANGE needs to juggle: VPDPBUSDS inum 9194 + REARRANGE one pattern worked for VPDPBUSDS inum 9194 + REARRANGE needs to juggle: VPDPBUSDS inum 9195 + REARRANGE one pattern worked for VPDPBUSDS inum 9195 + REARRANGE needs to juggle: VPDPBUSDS inum 9196 + REARRANGE one pattern worked for VPDPBUSDS inum 9196 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VORPD inum=5207 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VORPD inum=5208 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VORPD inum=5209 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VORPD inum=5210 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VORPS inum=5211 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VEX_PREFIX=0 MAP=1 VL=0 m m MOD!=3 r r r n n n MODRM() + +VORPS inum=5212 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VEX_PREFIX=0 MAP=1 VL=0 1 1 MOD=3 r r r n n n + +VORPS inum=5213 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VEX_PREFIX=0 MAP=1 VL=1 m m MOD!=3 r r r n n n MODRM() + +VORPS inum=5214 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 0 1 1 0 VEX_PREFIX=0 MAP=1 VL=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VORPD inum 5207 -- already fine + SKIPPING VORPD inum 5208 -- already fine + SKIPPING VORPD inum 5209 -- already fine + SKIPPING VORPD inum 5210 -- already fine + REARRANGE needs to juggle: VORPS inum 5211 + REARRANGE one pattern worked for VORPS inum 5211 + REARRANGE needs to juggle: VORPS inum 5212 + REARRANGE one pattern worked for VORPS inum 5212 + REARRANGE needs to juggle: VORPS inum 5213 + REARRANGE one pattern worked for VORPS inum 5213 + REARRANGE needs to juggle: VORPS inum 5214 + REARRANGE one pattern worked for VORPS inum 5214 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VADDPD inum=4669 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VADDPD inum=4670 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VADDPD inum=4671 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VADDPD inum=4672 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +VADDPS inum=4673 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=0 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VADDPS inum=4674 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=0 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VADDPS inum=4675 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=0 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VADDPS inum=4676 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=0 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +VADDSD inum=4677 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VADDSD inum=4678 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VADDSS inum=4679 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=3 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VADDSS inum=4680 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VEX_PREFIX=3 MAP=1 1 1 MOD=3 r r r n n n + +VPBROADCASTD inum=5878 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTD inum=5879 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPBROADCASTD inum=5880 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTD inum=5881 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VADDPD inum 4669 -- already fine + SKIPPING VADDPD inum 4670 -- already fine + SKIPPING VADDPD inum 4671 -- already fine + SKIPPING VADDPD inum 4672 -- already fine + SKIPPING VADDPS inum 4673 -- already fine + SKIPPING VADDPS inum 4674 -- already fine + SKIPPING VADDPS inum 4675 -- already fine + SKIPPING VADDPS inum 4676 -- already fine + SKIPPING VADDSD inum 4677 -- already fine + SKIPPING VADDSD inum 4678 -- already fine + SKIPPING VADDSS inum 4679 -- already fine + SKIPPING VADDSS inum 4680 -- already fine + REARRANGE needs to juggle: VPBROADCASTD inum 5878 + REARRANGE one pattern worked for VPBROADCASTD inum 5878 + REARRANGE needs to juggle: VPBROADCASTD inum 5879 + REARRANGE one pattern worked for VPBROADCASTD inum 5879 + REARRANGE needs to juggle: VPBROADCASTD inum 5880 + REARRANGE one pattern worked for VPBROADCASTD inum 5880 + REARRANGE needs to juggle: VPBROADCASTD inum 5881 + REARRANGE one pattern worked for VPBROADCASTD inum 5881 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VMULPD inum=5195 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMULPD inum=5196 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VMULPD inum=5197 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMULPD inum=5198 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VMULPS inum=5199 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=0 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMULPS inum=5200 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n + +VMULPS inum=5201 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=1 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMULPS inum=5202 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n + +VMULSD inum=5203 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMULSD inum=5204 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VMULSS inum=5205 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VEX_PREFIX=3 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMULSS inum=5206 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VEX_PREFIX=3 MAP=1 1 1 MOD=3 r r r n n n + +VPBROADCASTQ inum=5882 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTQ inum=5883 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPBROADCASTQ inum=5884 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTQ inum=5885 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VMULPD inum 5195 -- already fine + SKIPPING VMULPD inum 5196 -- already fine + SKIPPING VMULPD inum 5197 -- already fine + SKIPPING VMULPD inum 5198 -- already fine + SKIPPING VMULPS inum 5199 -- already fine + SKIPPING VMULPS inum 5200 -- already fine + SKIPPING VMULPS inum 5201 -- already fine + SKIPPING VMULPS inum 5202 -- already fine + REARRANGE needs to juggle: VMULSD inum 5203 + REARRANGE FAILED for VL. Trying again... +REARRANGE ATTEMPT using VEX_PREFIX + REARRANGE needs to juggle: VMULPD inum 5195 + REARRANGE one pattern worked for VMULPD inum 5195 + REARRANGE needs to juggle: VMULPD inum 5196 + REARRANGE one pattern worked for VMULPD inum 5196 + REARRANGE needs to juggle: VMULPD inum 5197 + REARRANGE one pattern worked for VMULPD inum 5197 + REARRANGE needs to juggle: VMULPD inum 5198 + REARRANGE one pattern worked for VMULPD inum 5198 + REARRANGE needs to juggle: VMULPS inum 5199 + REARRANGE one pattern worked for VMULPS inum 5199 + REARRANGE needs to juggle: VMULPS inum 5200 + REARRANGE one pattern worked for VMULPS inum 5200 + REARRANGE needs to juggle: VMULPS inum 5201 + REARRANGE one pattern worked for VMULPS inum 5201 + REARRANGE needs to juggle: VMULPS inum 5202 + REARRANGE one pattern worked for VMULPS inum 5202 + SKIPPING VMULSD inum 5203 -- already fine + SKIPPING VMULSD inum 5204 -- already fine + SKIPPING VMULSS inum 5205 -- already fine + SKIPPING VMULSS inum 5206 -- already fine + REARRANGE needs to juggle: VPBROADCASTQ inum 5882 + REARRANGE one pattern worked for VPBROADCASTQ inum 5882 + REARRANGE needs to juggle: VPBROADCASTQ inum 5883 + REARRANGE one pattern worked for VPBROADCASTQ inum 5883 + REARRANGE needs to juggle: VPBROADCASTQ inum 5884 + REARRANGE one pattern worked for VPBROADCASTQ inum 5884 + REARRANGE needs to juggle: VPBROADCASTQ inum 5885 + REARRANGE one pattern worked for VPBROADCASTQ inum 5885 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VCVTPD2PS inum=4745 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VCVTPD2PS inum=4746 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VCVTPD2PS inum=4747 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VCVTPD2PS inum=4748 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VCVTPS2PD inum=4757 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=0 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VCVTPS2PD inum=4758 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=0 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VCVTPS2PD inum=4759 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=0 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VCVTPS2PD inum=4760 isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=0 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VCVTSD2SS inum=4785 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VCVTSD2SS inum=4786 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VCVTSS2SD inum=4799 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=3 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VCVTSS2SD inum=4800 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VEX_PREFIX=3 MAP=1 1 1 MOD=3 r r r n n n + +VBROADCASTI128 inum=5889 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 0 1 1 0 1 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VCVTPD2PS inum 4745 -- already fine + SKIPPING VCVTPD2PS inum 4746 -- already fine + SKIPPING VCVTPD2PS inum 4747 -- already fine + SKIPPING VCVTPD2PS inum 4748 -- already fine + SKIPPING VCVTPS2PD inum 4757 -- already fine + SKIPPING VCVTPS2PD inum 4758 -- already fine + SKIPPING VCVTPS2PD inum 4759 -- already fine + SKIPPING VCVTPS2PD inum 4760 -- already fine + SKIPPING VCVTSD2SS inum 4785 -- already fine + SKIPPING VCVTSD2SS inum 4786 -- already fine + SKIPPING VCVTSS2SD inum 4799 -- already fine + SKIPPING VCVTSS2SD inum 4800 -- already fine + REARRANGE needs to juggle: VBROADCASTI128 inum 5889 + REARRANGE one pattern worked for VBROADCASTI128 inum 5889 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VFMADDSUBPS inum=4400 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4401 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4402 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4403 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4404 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4405 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4406 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4407 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VSUBPD inum=5183 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=0 m m MOD!=3 r r r n n n MODRM() + +VSUBPD inum=5184 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=0 1 1 MOD=3 r r r n n n + +VSUBPD inum=5185 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=1 m m MOD!=3 r r r n n n MODRM() + +VSUBPD inum=5186 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=1 1 1 MOD=3 r r r n n n + +VSUBPS inum=5187 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VL=0 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSUBPS inum=5188 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VL=0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n + +VSUBPS inum=5189 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VL=1 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSUBPS inum=5190 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VL=1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n + +VSUBSD inum=5191 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSUBSD inum=5192 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VSUBSS inum=5193 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=3 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSUBSS inum=5194 isa_set=AVX pattern len=20 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=3 MAP=1 1 1 MOD=3 r r r n n n + +TDPBF16PS inum=9212 iform_input=TDPBF16PS_TMMf32_TMMu32_TMMu32 isa_set=AMX_BF16 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=3 MAP=2 1 1 MOD=3 r r r n n n VL=0 REXW=0 MODE=2 + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMADDSUBPS inum 4400 -- already fine + SKIPPING VFMADDSUBPS inum 4401 -- already fine + SKIPPING VFMADDSUBPS inum 4402 -- already fine + SKIPPING VFMADDSUBPS inum 4403 -- already fine + SKIPPING VFMADDSUBPS inum 4404 -- already fine + SKIPPING VFMADDSUBPS inum 4405 -- already fine + SKIPPING VFMADDSUBPS inum 4406 -- already fine + SKIPPING VFMADDSUBPS inum 4407 -- already fine + SKIPPING VSUBPD inum 5183 -- already fine + SKIPPING VSUBPD inum 5184 -- already fine + SKIPPING VSUBPD inum 5185 -- already fine + SKIPPING VSUBPD inum 5186 -- already fine + REARRANGE needs to juggle: VSUBPS inum 5187 + REARRANGE one pattern worked for VSUBPS inum 5187 + REARRANGE needs to juggle: VSUBPS inum 5188 + REARRANGE one pattern worked for VSUBPS inum 5188 + REARRANGE needs to juggle: VSUBPS inum 5189 + REARRANGE one pattern worked for VSUBPS inum 5189 + REARRANGE needs to juggle: VSUBPS inum 5190 + REARRANGE one pattern worked for VSUBPS inum 5190 + SKIPPING VSUBSD inum 5191 -- already fine + SKIPPING VSUBSD inum 5192 -- already fine + SKIPPING VSUBSS inum 5193 -- already fine + SKIPPING VSUBSS inum 5194 -- already fine + SKIPPING TDPBF16PS inum 9212 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMADDSUBPS inum=4400 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4401 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4402 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4403 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4404 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4405 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4406 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4407 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VSUBPD inum=5183 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=0 m m MOD!=3 r r r n n n MODRM() + +VSUBPD inum=5184 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=0 1 1 MOD=3 r r r n n n + +VSUBPD inum=5185 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=1 m m MOD!=3 r r r n n n MODRM() + +VSUBPD inum=5186 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=1 VL=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSUBPS inum 4400 -- already fine + SKIPPING VFMADDSUBPS inum 4401 -- already fine + SKIPPING VFMADDSUBPS inum 4402 -- already fine + SKIPPING VFMADDSUBPS inum 4403 -- already fine + SKIPPING VFMADDSUBPS inum 4404 -- already fine + SKIPPING VFMADDSUBPS inum 4405 -- already fine + SKIPPING VFMADDSUBPS inum 4406 -- already fine + SKIPPING VFMADDSUBPS inum 4407 -- already fine + REARRANGE needs to juggle: VSUBPD inum 5183 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMADDSUBPS inum 4400 + REARRANGE one pattern worked for VFMADDSUBPS inum 4400 + REARRANGE needs to juggle: VFMADDSUBPS inum 4401 + REARRANGE one pattern worked for VFMADDSUBPS inum 4401 + REARRANGE needs to juggle: VFMADDSUBPS inum 4402 + REARRANGE one pattern worked for VFMADDSUBPS inum 4402 + REARRANGE needs to juggle: VFMADDSUBPS inum 4403 + REARRANGE one pattern worked for VFMADDSUBPS inum 4403 + REARRANGE needs to juggle: VFMADDSUBPS inum 4404 + REARRANGE one pattern worked for VFMADDSUBPS inum 4404 + REARRANGE needs to juggle: VFMADDSUBPS inum 4405 + REARRANGE one pattern worked for VFMADDSUBPS inum 4405 + REARRANGE needs to juggle: VFMADDSUBPS inum 4406 + REARRANGE one pattern worked for VFMADDSUBPS inum 4406 + REARRANGE needs to juggle: VFMADDSUBPS inum 4407 + REARRANGE one pattern worked for VFMADDSUBPS inum 4407 + REARRANGE needs to juggle: VSUBPD inum 5183 + REARRANGE one pattern worked for VSUBPD inum 5183 + REARRANGE needs to juggle: VSUBPD inum 5184 + REARRANGE one pattern worked for VSUBPD inum 5184 + REARRANGE needs to juggle: VSUBPD inum 5185 + REARRANGE one pattern worked for VSUBPD inum 5185 + REARRANGE needs to juggle: VSUBPD inum 5186 + REARRANGE one pattern worked for VSUBPD inum 5186 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMADDSUBPS inum=4400 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4401 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4402 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4403 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VSUBPD inum=5183 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSUBPD inum=5184 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSUBPS inum 4400 -- already fine + SKIPPING VFMADDSUBPS inum 4401 -- already fine + SKIPPING VFMADDSUBPS inum 4402 -- already fine + SKIPPING VFMADDSUBPS inum 4403 -- already fine + REARRANGE needs to juggle: VSUBPD inum 5183 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDSUBPS inum 4400 + REARRANGE one pattern worked for VFMADDSUBPS inum 4400 + REARRANGE needs to juggle: VFMADDSUBPS inum 4401 + REARRANGE one pattern worked for VFMADDSUBPS inum 4401 + REARRANGE needs to juggle: VFMADDSUBPS inum 4402 + REARRANGE one pattern worked for VFMADDSUBPS inum 4402 + REARRANGE needs to juggle: VFMADDSUBPS inum 4403 + REARRANGE one pattern worked for VFMADDSUBPS inum 4403 + SKIPPING VSUBPD inum 5183 -- already fine + SKIPPING VSUBPD inum 5184 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMADDSUBPS inum=4404 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4405 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPS inum=4406 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPS inum=4407 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VSUBPD inum=5185 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VSUBPD inum=5186 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSUBPS inum 4404 -- already fine + SKIPPING VFMADDSUBPS inum 4405 -- already fine + SKIPPING VFMADDSUBPS inum 4406 -- already fine + SKIPPING VFMADDSUBPS inum 4407 -- already fine + REARRANGE needs to juggle: VSUBPD inum 5185 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDSUBPS inum 4404 + REARRANGE one pattern worked for VFMADDSUBPS inum 4404 + REARRANGE needs to juggle: VFMADDSUBPS inum 4405 + REARRANGE one pattern worked for VFMADDSUBPS inum 4405 + REARRANGE needs to juggle: VFMADDSUBPS inum 4406 + REARRANGE one pattern worked for VFMADDSUBPS inum 4406 + REARRANGE needs to juggle: VFMADDSUBPS inum 4407 + REARRANGE one pattern worked for VFMADDSUBPS inum 4407 + SKIPPING VSUBPD inum 5185 -- already fine + SKIPPING VSUBPD inum 5186 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 10 +Others: +VFMADDSUBPD inum=4408 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4409 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPD inum=4410 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4411 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPD inum=4412 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4413 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPD inum=4414 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4415 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMINPD inum=4901 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=1 VL=0 m m MOD!=3 r r r n n n MODRM() + +VMINPD inum=4902 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=1 VL=0 1 1 MOD=3 r r r n n n + +VMINPD inum=4903 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=1 VL=1 m m MOD!=3 r r r n n n MODRM() + +VMINPD inum=4904 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=1 VL=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSUBPD inum 4408 -- already fine + SKIPPING VFMADDSUBPD inum 4409 -- already fine + SKIPPING VFMADDSUBPD inum 4410 -- already fine + SKIPPING VFMADDSUBPD inum 4411 -- already fine + SKIPPING VFMADDSUBPD inum 4412 -- already fine + SKIPPING VFMADDSUBPD inum 4413 -- already fine + SKIPPING VFMADDSUBPD inum 4414 -- already fine + SKIPPING VFMADDSUBPD inum 4415 -- already fine + REARRANGE needs to juggle: VMINPD inum 4901 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMADDSUBPD inum 4408 + REARRANGE one pattern worked for VFMADDSUBPD inum 4408 + REARRANGE needs to juggle: VFMADDSUBPD inum 4409 + REARRANGE one pattern worked for VFMADDSUBPD inum 4409 + REARRANGE needs to juggle: VFMADDSUBPD inum 4410 + REARRANGE one pattern worked for VFMADDSUBPD inum 4410 + REARRANGE needs to juggle: VFMADDSUBPD inum 4411 + REARRANGE one pattern worked for VFMADDSUBPD inum 4411 + REARRANGE needs to juggle: VFMADDSUBPD inum 4412 + REARRANGE one pattern worked for VFMADDSUBPD inum 4412 + REARRANGE needs to juggle: VFMADDSUBPD inum 4413 + REARRANGE one pattern worked for VFMADDSUBPD inum 4413 + REARRANGE needs to juggle: VFMADDSUBPD inum 4414 + REARRANGE one pattern worked for VFMADDSUBPD inum 4414 + REARRANGE needs to juggle: VFMADDSUBPD inum 4415 + REARRANGE one pattern worked for VFMADDSUBPD inum 4415 + REARRANGE needs to juggle: VMINPD inum 4901 + REARRANGE one pattern worked for VMINPD inum 4901 + REARRANGE needs to juggle: VMINPD inum 4902 + REARRANGE one pattern worked for VMINPD inum 4902 + REARRANGE needs to juggle: VMINPD inum 4903 + REARRANGE one pattern worked for VMINPD inum 4903 + REARRANGE needs to juggle: VMINPD inum 4904 + REARRANGE one pattern worked for VMINPD inum 4904 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMADDSUBPD inum=4408 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4409 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPD inum=4410 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4411 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMINPD inum=4901 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMINPD inum=4902 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSUBPD inum 4408 -- already fine + SKIPPING VFMADDSUBPD inum 4409 -- already fine + SKIPPING VFMADDSUBPD inum 4410 -- already fine + SKIPPING VFMADDSUBPD inum 4411 -- already fine + REARRANGE needs to juggle: VMINPD inum 4901 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDSUBPD inum 4408 + REARRANGE one pattern worked for VFMADDSUBPD inum 4408 + REARRANGE needs to juggle: VFMADDSUBPD inum 4409 + REARRANGE one pattern worked for VFMADDSUBPD inum 4409 + REARRANGE needs to juggle: VFMADDSUBPD inum 4410 + REARRANGE one pattern worked for VFMADDSUBPD inum 4410 + REARRANGE needs to juggle: VFMADDSUBPD inum 4411 + REARRANGE one pattern worked for VFMADDSUBPD inum 4411 + SKIPPING VMINPD inum 4901 -- already fine + SKIPPING VMINPD inum 4902 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMADDSUBPD inum=4412 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4413 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSUBPD inum=4414 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSUBPD inum=4415 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMINPD inum=4903 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMINPD inum=4904 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSUBPD inum 4412 -- already fine + SKIPPING VFMADDSUBPD inum 4413 -- already fine + SKIPPING VFMADDSUBPD inum 4414 -- already fine + SKIPPING VFMADDSUBPD inum 4415 -- already fine + REARRANGE needs to juggle: VMINPD inum 4903 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDSUBPD inum 4412 + REARRANGE one pattern worked for VFMADDSUBPD inum 4412 + REARRANGE needs to juggle: VFMADDSUBPD inum 4413 + REARRANGE one pattern worked for VFMADDSUBPD inum 4413 + REARRANGE needs to juggle: VFMADDSUBPD inum 4414 + REARRANGE one pattern worked for VFMADDSUBPD inum 4414 + REARRANGE needs to juggle: VFMADDSUBPD inum 4415 + REARRANGE one pattern worked for VFMADDSUBPD inum 4415 + SKIPPING VMINPD inum 4903 -- already fine + SKIPPING VMINPD inum 4904 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 10 +Others: +VFMSUBADDPS inum=4416 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4417 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPS inum=4418 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4419 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPS inum=4420 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4421 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPS inum=4422 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4423 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VDIVPD inum=4801 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=1 VL=0 m m MOD!=3 r r r n n n MODRM() + +VDIVPD inum=4802 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=1 VL=0 1 1 MOD=3 r r r n n n + +VDIVPD inum=4803 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=1 VL=1 m m MOD!=3 r r r n n n MODRM() + +VDIVPD inum=4804 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=1 VL=1 1 1 MOD=3 r r r n n n + +TDPBUSD inum=9215 iform_input=TDPBUSD_TMMi32_TMMu32_TMMu32 isa_set=AMX_INT8 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 REXW=0 MODE=2 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBADDPS inum 4416 -- already fine + SKIPPING VFMSUBADDPS inum 4417 -- already fine + SKIPPING VFMSUBADDPS inum 4418 -- already fine + SKIPPING VFMSUBADDPS inum 4419 -- already fine + SKIPPING VFMSUBADDPS inum 4420 -- already fine + SKIPPING VFMSUBADDPS inum 4421 -- already fine + SKIPPING VFMSUBADDPS inum 4422 -- already fine + SKIPPING VFMSUBADDPS inum 4423 -- already fine + REARRANGE needs to juggle: VDIVPD inum 4801 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMSUBADDPS inum 4416 + REARRANGE one pattern worked for VFMSUBADDPS inum 4416 + REARRANGE needs to juggle: VFMSUBADDPS inum 4417 + REARRANGE one pattern worked for VFMSUBADDPS inum 4417 + REARRANGE needs to juggle: VFMSUBADDPS inum 4418 + REARRANGE one pattern worked for VFMSUBADDPS inum 4418 + REARRANGE needs to juggle: VFMSUBADDPS inum 4419 + REARRANGE one pattern worked for VFMSUBADDPS inum 4419 + REARRANGE needs to juggle: VFMSUBADDPS inum 4420 + REARRANGE one pattern worked for VFMSUBADDPS inum 4420 + REARRANGE needs to juggle: VFMSUBADDPS inum 4421 + REARRANGE one pattern worked for VFMSUBADDPS inum 4421 + REARRANGE needs to juggle: VFMSUBADDPS inum 4422 + REARRANGE one pattern worked for VFMSUBADDPS inum 4422 + REARRANGE needs to juggle: VFMSUBADDPS inum 4423 + REARRANGE one pattern worked for VFMSUBADDPS inum 4423 + REARRANGE needs to juggle: VDIVPD inum 4801 + REARRANGE one pattern worked for VDIVPD inum 4801 + REARRANGE needs to juggle: VDIVPD inum 4802 + REARRANGE one pattern worked for VDIVPD inum 4802 + REARRANGE needs to juggle: VDIVPD inum 4803 + REARRANGE one pattern worked for VDIVPD inum 4803 + REARRANGE needs to juggle: VDIVPD inum 4804 + REARRANGE one pattern worked for VDIVPD inum 4804 + REARRANGE needs to juggle: TDPBUSD inum 9215 + REARRANGE one pattern worked for TDPBUSD inum 9215 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBADDPS inum=4416 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4417 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPS inum=4418 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4419 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VDIVPD inum=4801 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VDIVPD inum=4802 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +TDPBUSD inum=9215 iform_input=TDPBUSD_TMMi32_TMMu32_TMMu32 isa_set=AMX_INT8 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=2 1 1 MOD=3 r r r n n n REXW=0 MODE=2 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBADDPS inum 4416 -- already fine + SKIPPING VFMSUBADDPS inum 4417 -- already fine + SKIPPING VFMSUBADDPS inum 4418 -- already fine + SKIPPING VFMSUBADDPS inum 4419 -- already fine + REARRANGE needs to juggle: VDIVPD inum 4801 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBADDPS inum 4416 + REARRANGE one pattern worked for VFMSUBADDPS inum 4416 + REARRANGE needs to juggle: VFMSUBADDPS inum 4417 + REARRANGE one pattern worked for VFMSUBADDPS inum 4417 + REARRANGE needs to juggle: VFMSUBADDPS inum 4418 + REARRANGE one pattern worked for VFMSUBADDPS inum 4418 + REARRANGE needs to juggle: VFMSUBADDPS inum 4419 + REARRANGE one pattern worked for VFMSUBADDPS inum 4419 + SKIPPING VDIVPD inum 4801 -- already fine + SKIPPING VDIVPD inum 4802 -- already fine + SKIPPING TDPBUSD inum 9215 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBADDPS inum=4420 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4421 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPS inum=4422 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPS inum=4423 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VDIVPD inum=4803 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VDIVPD inum=4804 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBADDPS inum 4420 -- already fine + SKIPPING VFMSUBADDPS inum 4421 -- already fine + SKIPPING VFMSUBADDPS inum 4422 -- already fine + SKIPPING VFMSUBADDPS inum 4423 -- already fine + REARRANGE needs to juggle: VDIVPD inum 4803 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBADDPS inum 4420 + REARRANGE one pattern worked for VFMSUBADDPS inum 4420 + REARRANGE needs to juggle: VFMSUBADDPS inum 4421 + REARRANGE one pattern worked for VFMSUBADDPS inum 4421 + REARRANGE needs to juggle: VFMSUBADDPS inum 4422 + REARRANGE one pattern worked for VFMSUBADDPS inum 4422 + REARRANGE needs to juggle: VFMSUBADDPS inum 4423 + REARRANGE one pattern worked for VFMSUBADDPS inum 4423 + SKIPPING VDIVPD inum 4803 -- already fine + SKIPPING VDIVPD inum 4804 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 10 +Others: +VFMSUBADDPD inum=4424 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4425 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPD inum=4426 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4427 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPD inum=4428 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4429 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPD inum=4430 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4431 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMAXPD inum=4889 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=1 VL=0 m m MOD!=3 r r r n n n MODRM() + +VMAXPD inum=4890 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=1 VL=0 1 1 MOD=3 r r r n n n + +VMAXPD inum=4891 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=1 VL=1 m m MOD!=3 r r r n n n MODRM() + +VMAXPD inum=4892 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=1 VL=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBADDPD inum 4424 -- already fine + SKIPPING VFMSUBADDPD inum 4425 -- already fine + SKIPPING VFMSUBADDPD inum 4426 -- already fine + SKIPPING VFMSUBADDPD inum 4427 -- already fine + SKIPPING VFMSUBADDPD inum 4428 -- already fine + SKIPPING VFMSUBADDPD inum 4429 -- already fine + SKIPPING VFMSUBADDPD inum 4430 -- already fine + SKIPPING VFMSUBADDPD inum 4431 -- already fine + REARRANGE needs to juggle: VMAXPD inum 4889 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMSUBADDPD inum 4424 + REARRANGE one pattern worked for VFMSUBADDPD inum 4424 + REARRANGE needs to juggle: VFMSUBADDPD inum 4425 + REARRANGE one pattern worked for VFMSUBADDPD inum 4425 + REARRANGE needs to juggle: VFMSUBADDPD inum 4426 + REARRANGE one pattern worked for VFMSUBADDPD inum 4426 + REARRANGE needs to juggle: VFMSUBADDPD inum 4427 + REARRANGE one pattern worked for VFMSUBADDPD inum 4427 + REARRANGE needs to juggle: VFMSUBADDPD inum 4428 + REARRANGE one pattern worked for VFMSUBADDPD inum 4428 + REARRANGE needs to juggle: VFMSUBADDPD inum 4429 + REARRANGE one pattern worked for VFMSUBADDPD inum 4429 + REARRANGE needs to juggle: VFMSUBADDPD inum 4430 + REARRANGE one pattern worked for VFMSUBADDPD inum 4430 + REARRANGE needs to juggle: VFMSUBADDPD inum 4431 + REARRANGE one pattern worked for VFMSUBADDPD inum 4431 + REARRANGE needs to juggle: VMAXPD inum 4889 + REARRANGE one pattern worked for VMAXPD inum 4889 + REARRANGE needs to juggle: VMAXPD inum 4890 + REARRANGE one pattern worked for VMAXPD inum 4890 + REARRANGE needs to juggle: VMAXPD inum 4891 + REARRANGE one pattern worked for VMAXPD inum 4891 + REARRANGE needs to juggle: VMAXPD inum 4892 + REARRANGE one pattern worked for VMAXPD inum 4892 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBADDPD inum=4424 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4425 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPD inum=4426 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4427 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMAXPD inum=4889 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMAXPD inum=4890 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBADDPD inum 4424 -- already fine + SKIPPING VFMSUBADDPD inum 4425 -- already fine + SKIPPING VFMSUBADDPD inum 4426 -- already fine + SKIPPING VFMSUBADDPD inum 4427 -- already fine + REARRANGE needs to juggle: VMAXPD inum 4889 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBADDPD inum 4424 + REARRANGE one pattern worked for VFMSUBADDPD inum 4424 + REARRANGE needs to juggle: VFMSUBADDPD inum 4425 + REARRANGE one pattern worked for VFMSUBADDPD inum 4425 + REARRANGE needs to juggle: VFMSUBADDPD inum 4426 + REARRANGE one pattern worked for VFMSUBADDPD inum 4426 + REARRANGE needs to juggle: VFMSUBADDPD inum 4427 + REARRANGE one pattern worked for VFMSUBADDPD inum 4427 + SKIPPING VMAXPD inum 4889 -- already fine + SKIPPING VMAXPD inum 4890 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBADDPD inum=4428 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4429 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBADDPD inum=4430 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBADDPD inum=4431 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMAXPD inum=4891 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VMAXPD inum=4892 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 0 1 1 1 1 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBADDPD inum 4428 -- already fine + SKIPPING VFMSUBADDPD inum 4429 -- already fine + SKIPPING VFMSUBADDPD inum 4430 -- already fine + SKIPPING VFMSUBADDPD inum 4431 -- already fine + REARRANGE needs to juggle: VMAXPD inum 4891 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBADDPD inum 4428 + REARRANGE one pattern worked for VFMSUBADDPD inum 4428 + REARRANGE needs to juggle: VFMSUBADDPD inum 4429 + REARRANGE one pattern worked for VFMSUBADDPD inum 4429 + REARRANGE needs to juggle: VFMSUBADDPD inum 4430 + REARRANGE one pattern worked for VFMSUBADDPD inum 4430 + REARRANGE needs to juggle: VFMSUBADDPD inum 4431 + REARRANGE one pattern worked for VFMSUBADDPD inum 4431 + SKIPPING VMAXPD inum 4891 -- already fine + SKIPPING VMAXPD inum 4892 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFMADDPS inum=4432 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4433 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4434 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4435 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4436 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4437 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4438 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4439 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHBW inum=5107 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHBW inum=5108 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHBW inum=5771 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHBW inum=5772 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMADDPS inum 4432 -- already fine + SKIPPING VFMADDPS inum 4433 -- already fine + SKIPPING VFMADDPS inum 4434 -- already fine + SKIPPING VFMADDPS inum 4435 -- already fine + SKIPPING VFMADDPS inum 4436 -- already fine + SKIPPING VFMADDPS inum 4437 -- already fine + SKIPPING VFMADDPS inum 4438 -- already fine + SKIPPING VFMADDPS inum 4439 -- already fine + REARRANGE needs to juggle: VPUNPCKHBW inum 5107 + REARRANGE one pattern worked for VPUNPCKHBW inum 5107 + REARRANGE needs to juggle: VPUNPCKHBW inum 5108 + REARRANGE one pattern worked for VPUNPCKHBW inum 5108 + REARRANGE needs to juggle: VPUNPCKHBW inum 5771 + REARRANGE one pattern worked for VPUNPCKHBW inum 5771 + REARRANGE needs to juggle: VPUNPCKHBW inum 5772 + REARRANGE one pattern worked for VPUNPCKHBW inum 5772 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMADDPS inum=4432 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4433 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4434 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4435 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4436 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4437 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4438 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4439 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHBW inum=5107 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHBW inum=5108 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHBW inum=5771 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHBW inum=5772 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDPS inum 4432 -- already fine + SKIPPING VFMADDPS inum 4433 -- already fine + SKIPPING VFMADDPS inum 4434 -- already fine + SKIPPING VFMADDPS inum 4435 -- already fine + SKIPPING VFMADDPS inum 4436 -- already fine + SKIPPING VFMADDPS inum 4437 -- already fine + SKIPPING VFMADDPS inum 4438 -- already fine + SKIPPING VFMADDPS inum 4439 -- already fine + REARRANGE needs to juggle: VPUNPCKHBW inum 5107 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMADDPS inum 4432 + REARRANGE one pattern worked for VFMADDPS inum 4432 + REARRANGE needs to juggle: VFMADDPS inum 4433 + REARRANGE one pattern worked for VFMADDPS inum 4433 + REARRANGE needs to juggle: VFMADDPS inum 4434 + REARRANGE one pattern worked for VFMADDPS inum 4434 + REARRANGE needs to juggle: VFMADDPS inum 4435 + REARRANGE one pattern worked for VFMADDPS inum 4435 + REARRANGE needs to juggle: VFMADDPS inum 4436 + REARRANGE one pattern worked for VFMADDPS inum 4436 + REARRANGE needs to juggle: VFMADDPS inum 4437 + REARRANGE one pattern worked for VFMADDPS inum 4437 + REARRANGE needs to juggle: VFMADDPS inum 4438 + REARRANGE one pattern worked for VFMADDPS inum 4438 + REARRANGE needs to juggle: VFMADDPS inum 4439 + REARRANGE one pattern worked for VFMADDPS inum 4439 + SKIPPING VPUNPCKHBW inum 5107 -- already fine + SKIPPING VPUNPCKHBW inum 5108 -- already fine + SKIPPING VPUNPCKHBW inum 5771 -- already fine + SKIPPING VPUNPCKHBW inum 5772 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMADDPS inum=4432 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4433 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4434 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4435 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHBW inum=5107 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHBW inum=5108 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDPS inum 4432 -- already fine + SKIPPING VFMADDPS inum 4433 -- already fine + SKIPPING VFMADDPS inum 4434 -- already fine + SKIPPING VFMADDPS inum 4435 -- already fine + REARRANGE needs to juggle: VPUNPCKHBW inum 5107 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDPS inum 4432 + REARRANGE one pattern worked for VFMADDPS inum 4432 + REARRANGE needs to juggle: VFMADDPS inum 4433 + REARRANGE one pattern worked for VFMADDPS inum 4433 + REARRANGE needs to juggle: VFMADDPS inum 4434 + REARRANGE one pattern worked for VFMADDPS inum 4434 + REARRANGE needs to juggle: VFMADDPS inum 4435 + REARRANGE one pattern worked for VFMADDPS inum 4435 + SKIPPING VPUNPCKHBW inum 5107 -- already fine + SKIPPING VPUNPCKHBW inum 5108 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMADDPS inum=4436 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4437 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPS inum=4438 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPS inum=4439 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHBW inum=5771 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHBW inum=5772 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDPS inum 4436 -- already fine + SKIPPING VFMADDPS inum 4437 -- already fine + SKIPPING VFMADDPS inum 4438 -- already fine + SKIPPING VFMADDPS inum 4439 -- already fine + REARRANGE needs to juggle: VPUNPCKHBW inum 5771 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDPS inum 4436 + REARRANGE one pattern worked for VFMADDPS inum 4436 + REARRANGE needs to juggle: VFMADDPS inum 4437 + REARRANGE one pattern worked for VFMADDPS inum 4437 + REARRANGE needs to juggle: VFMADDPS inum 4438 + REARRANGE one pattern worked for VFMADDPS inum 4438 + REARRANGE needs to juggle: VFMADDPS inum 4439 + REARRANGE one pattern worked for VFMADDPS inum 4439 + SKIPPING VPUNPCKHBW inum 5771 -- already fine + SKIPPING VPUNPCKHBW inum 5772 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFMADDPD inum=4440 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4441 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4442 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4443 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4444 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4445 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4446 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4447 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHWD inum=5109 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHWD inum=5110 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHWD inum=5773 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHWD inum=5774 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMADDPD inum 4440 -- already fine + SKIPPING VFMADDPD inum 4441 -- already fine + SKIPPING VFMADDPD inum 4442 -- already fine + SKIPPING VFMADDPD inum 4443 -- already fine + SKIPPING VFMADDPD inum 4444 -- already fine + SKIPPING VFMADDPD inum 4445 -- already fine + SKIPPING VFMADDPD inum 4446 -- already fine + SKIPPING VFMADDPD inum 4447 -- already fine + REARRANGE needs to juggle: VPUNPCKHWD inum 5109 + REARRANGE one pattern worked for VPUNPCKHWD inum 5109 + REARRANGE needs to juggle: VPUNPCKHWD inum 5110 + REARRANGE one pattern worked for VPUNPCKHWD inum 5110 + REARRANGE needs to juggle: VPUNPCKHWD inum 5773 + REARRANGE one pattern worked for VPUNPCKHWD inum 5773 + REARRANGE needs to juggle: VPUNPCKHWD inum 5774 + REARRANGE one pattern worked for VPUNPCKHWD inum 5774 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMADDPD inum=4440 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4441 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4442 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4443 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4444 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4445 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4446 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4447 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHWD inum=5109 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHWD inum=5110 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHWD inum=5773 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHWD inum=5774 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDPD inum 4440 -- already fine + SKIPPING VFMADDPD inum 4441 -- already fine + SKIPPING VFMADDPD inum 4442 -- already fine + SKIPPING VFMADDPD inum 4443 -- already fine + SKIPPING VFMADDPD inum 4444 -- already fine + SKIPPING VFMADDPD inum 4445 -- already fine + SKIPPING VFMADDPD inum 4446 -- already fine + SKIPPING VFMADDPD inum 4447 -- already fine + REARRANGE needs to juggle: VPUNPCKHWD inum 5109 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMADDPD inum 4440 + REARRANGE one pattern worked for VFMADDPD inum 4440 + REARRANGE needs to juggle: VFMADDPD inum 4441 + REARRANGE one pattern worked for VFMADDPD inum 4441 + REARRANGE needs to juggle: VFMADDPD inum 4442 + REARRANGE one pattern worked for VFMADDPD inum 4442 + REARRANGE needs to juggle: VFMADDPD inum 4443 + REARRANGE one pattern worked for VFMADDPD inum 4443 + REARRANGE needs to juggle: VFMADDPD inum 4444 + REARRANGE one pattern worked for VFMADDPD inum 4444 + REARRANGE needs to juggle: VFMADDPD inum 4445 + REARRANGE one pattern worked for VFMADDPD inum 4445 + REARRANGE needs to juggle: VFMADDPD inum 4446 + REARRANGE one pattern worked for VFMADDPD inum 4446 + REARRANGE needs to juggle: VFMADDPD inum 4447 + REARRANGE one pattern worked for VFMADDPD inum 4447 + SKIPPING VPUNPCKHWD inum 5109 -- already fine + SKIPPING VPUNPCKHWD inum 5110 -- already fine + SKIPPING VPUNPCKHWD inum 5773 -- already fine + SKIPPING VPUNPCKHWD inum 5774 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMADDPD inum=4440 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4441 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4442 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4443 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHWD inum=5109 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHWD inum=5110 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDPD inum 4440 -- already fine + SKIPPING VFMADDPD inum 4441 -- already fine + SKIPPING VFMADDPD inum 4442 -- already fine + SKIPPING VFMADDPD inum 4443 -- already fine + REARRANGE needs to juggle: VPUNPCKHWD inum 5109 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDPD inum 4440 + REARRANGE one pattern worked for VFMADDPD inum 4440 + REARRANGE needs to juggle: VFMADDPD inum 4441 + REARRANGE one pattern worked for VFMADDPD inum 4441 + REARRANGE needs to juggle: VFMADDPD inum 4442 + REARRANGE one pattern worked for VFMADDPD inum 4442 + REARRANGE needs to juggle: VFMADDPD inum 4443 + REARRANGE one pattern worked for VFMADDPD inum 4443 + SKIPPING VPUNPCKHWD inum 5109 -- already fine + SKIPPING VPUNPCKHWD inum 5110 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMADDPD inum=4444 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4445 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDPD inum=4446 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDPD inum=4447 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHWD inum=5773 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHWD inum=5774 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDPD inum 4444 -- already fine + SKIPPING VFMADDPD inum 4445 -- already fine + SKIPPING VFMADDPD inum 4446 -- already fine + SKIPPING VFMADDPD inum 4447 -- already fine + REARRANGE needs to juggle: VPUNPCKHWD inum 5773 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDPD inum 4444 + REARRANGE one pattern worked for VFMADDPD inum 4444 + REARRANGE needs to juggle: VFMADDPD inum 4445 + REARRANGE one pattern worked for VFMADDPD inum 4445 + REARRANGE needs to juggle: VFMADDPD inum 4446 + REARRANGE one pattern worked for VFMADDPD inum 4446 + REARRANGE needs to juggle: VFMADDPD inum 4447 + REARRANGE one pattern worked for VFMADDPD inum 4447 + SKIPPING VPUNPCKHWD inum 5773 -- already fine + SKIPPING VPUNPCKHWD inum 5774 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFMADDSS inum=4448 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSS inum=4449 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSS inum=4450 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSS inum=4451 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHDQ inum=5111 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHDQ inum=5112 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHDQ inum=5775 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHDQ inum=5776 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMADDSS inum 4448 -- already fine + SKIPPING VFMADDSS inum 4449 -- already fine + SKIPPING VFMADDSS inum 4450 -- already fine + SKIPPING VFMADDSS inum 4451 -- already fine + REARRANGE needs to juggle: VPUNPCKHDQ inum 5111 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5111 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5112 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5112 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5775 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5775 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5776 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5776 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMADDSS inum=4448 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSS inum=4449 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSS inum=4450 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSS inum=4451 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHDQ inum=5111 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHDQ inum=5112 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHDQ inum=5775 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHDQ inum=5776 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSS inum 4448 -- already fine + SKIPPING VFMADDSS inum 4449 -- already fine + SKIPPING VFMADDSS inum 4450 -- already fine + SKIPPING VFMADDSS inum 4451 -- already fine + REARRANGE needs to juggle: VPUNPCKHDQ inum 5111 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDSS inum 4448 + REARRANGE one pattern worked for VFMADDSS inum 4448 + REARRANGE needs to juggle: VFMADDSS inum 4449 + REARRANGE one pattern worked for VFMADDSS inum 4449 + REARRANGE needs to juggle: VFMADDSS inum 4450 + REARRANGE one pattern worked for VFMADDSS inum 4450 + REARRANGE needs to juggle: VFMADDSS inum 4451 + REARRANGE one pattern worked for VFMADDSS inum 4451 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5111 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5111 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5112 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5112 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5775 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5775 + REARRANGE needs to juggle: VPUNPCKHDQ inum 5776 + REARRANGE one pattern worked for VPUNPCKHDQ inum 5776 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFMADDSD inum=4452 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSD inum=4453 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSD inum=4454 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSD inum=4455 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPACKSSDW inum=4997 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPACKSSDW inum=4998 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPACKSSDW inum=5633 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPACKSSDW inum=5634 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMADDSD inum 4452 -- already fine + SKIPPING VFMADDSD inum 4453 -- already fine + SKIPPING VFMADDSD inum 4454 -- already fine + SKIPPING VFMADDSD inum 4455 -- already fine + REARRANGE needs to juggle: VPACKSSDW inum 4997 + REARRANGE one pattern worked for VPACKSSDW inum 4997 + REARRANGE needs to juggle: VPACKSSDW inum 4998 + REARRANGE one pattern worked for VPACKSSDW inum 4998 + REARRANGE needs to juggle: VPACKSSDW inum 5633 + REARRANGE one pattern worked for VPACKSSDW inum 5633 + REARRANGE needs to juggle: VPACKSSDW inum 5634 + REARRANGE one pattern worked for VPACKSSDW inum 5634 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMADDSD inum=4452 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSD inum=4453 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMADDSD inum=4454 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMADDSD inum=4455 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPACKSSDW inum=4997 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPACKSSDW inum=4998 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VPACKSSDW inum=5633 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPACKSSDW inum=5634 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 0 1 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMADDSD inum 4452 -- already fine + SKIPPING VFMADDSD inum 4453 -- already fine + SKIPPING VFMADDSD inum 4454 -- already fine + SKIPPING VFMADDSD inum 4455 -- already fine + REARRANGE needs to juggle: VPACKSSDW inum 4997 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMADDSD inum 4452 + REARRANGE one pattern worked for VFMADDSD inum 4452 + REARRANGE needs to juggle: VFMADDSD inum 4453 + REARRANGE one pattern worked for VFMADDSD inum 4453 + REARRANGE needs to juggle: VFMADDSD inum 4454 + REARRANGE one pattern worked for VFMADDSD inum 4454 + REARRANGE needs to juggle: VFMADDSD inum 4455 + REARRANGE one pattern worked for VFMADDSD inum 4455 + REARRANGE needs to juggle: VPACKSSDW inum 4997 + REARRANGE one pattern worked for VPACKSSDW inum 4997 + REARRANGE needs to juggle: VPACKSSDW inum 4998 + REARRANGE one pattern worked for VPACKSSDW inum 4998 + REARRANGE needs to juggle: VPACKSSDW inum 5633 + REARRANGE one pattern worked for VPACKSSDW inum 5633 + REARRANGE needs to juggle: VPACKSSDW inum 5634 + REARRANGE one pattern worked for VPACKSSDW inum 5634 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFMSUBPS inum=4456 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4457 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4458 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4459 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4460 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4461 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4462 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4463 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKLQDQ inum=5121 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKLQDQ inum=5122 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKLQDQ inum=5785 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKLQDQ inum=5786 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMSUBPS inum 4456 -- already fine + SKIPPING VFMSUBPS inum 4457 -- already fine + SKIPPING VFMSUBPS inum 4458 -- already fine + SKIPPING VFMSUBPS inum 4459 -- already fine + SKIPPING VFMSUBPS inum 4460 -- already fine + SKIPPING VFMSUBPS inum 4461 -- already fine + SKIPPING VFMSUBPS inum 4462 -- already fine + SKIPPING VFMSUBPS inum 4463 -- already fine + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5121 + REARRANGE one pattern worked for VPUNPCKLQDQ inum 5121 + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5122 + REARRANGE one pattern worked for VPUNPCKLQDQ inum 5122 + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5785 + REARRANGE one pattern worked for VPUNPCKLQDQ inum 5785 + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5786 + REARRANGE one pattern worked for VPUNPCKLQDQ inum 5786 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMSUBPS inum=4456 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4457 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4458 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4459 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4460 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4461 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4462 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4463 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKLQDQ inum=5121 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKLQDQ inum=5122 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKLQDQ inum=5785 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKLQDQ inum=5786 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBPS inum 4456 -- already fine + SKIPPING VFMSUBPS inum 4457 -- already fine + SKIPPING VFMSUBPS inum 4458 -- already fine + SKIPPING VFMSUBPS inum 4459 -- already fine + SKIPPING VFMSUBPS inum 4460 -- already fine + SKIPPING VFMSUBPS inum 4461 -- already fine + SKIPPING VFMSUBPS inum 4462 -- already fine + SKIPPING VFMSUBPS inum 4463 -- already fine + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5121 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMSUBPS inum 4456 + REARRANGE one pattern worked for VFMSUBPS inum 4456 + REARRANGE needs to juggle: VFMSUBPS inum 4457 + REARRANGE one pattern worked for VFMSUBPS inum 4457 + REARRANGE needs to juggle: VFMSUBPS inum 4458 + REARRANGE one pattern worked for VFMSUBPS inum 4458 + REARRANGE needs to juggle: VFMSUBPS inum 4459 + REARRANGE one pattern worked for VFMSUBPS inum 4459 + REARRANGE needs to juggle: VFMSUBPS inum 4460 + REARRANGE one pattern worked for VFMSUBPS inum 4460 + REARRANGE needs to juggle: VFMSUBPS inum 4461 + REARRANGE one pattern worked for VFMSUBPS inum 4461 + REARRANGE needs to juggle: VFMSUBPS inum 4462 + REARRANGE one pattern worked for VFMSUBPS inum 4462 + REARRANGE needs to juggle: VFMSUBPS inum 4463 + REARRANGE one pattern worked for VFMSUBPS inum 4463 + SKIPPING VPUNPCKLQDQ inum 5121 -- already fine + SKIPPING VPUNPCKLQDQ inum 5122 -- already fine + SKIPPING VPUNPCKLQDQ inum 5785 -- already fine + SKIPPING VPUNPCKLQDQ inum 5786 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBPS inum=4456 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4457 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4458 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4459 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKLQDQ inum=5121 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKLQDQ inum=5122 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBPS inum 4456 -- already fine + SKIPPING VFMSUBPS inum 4457 -- already fine + SKIPPING VFMSUBPS inum 4458 -- already fine + SKIPPING VFMSUBPS inum 4459 -- already fine + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5121 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBPS inum 4456 + REARRANGE one pattern worked for VFMSUBPS inum 4456 + REARRANGE needs to juggle: VFMSUBPS inum 4457 + REARRANGE one pattern worked for VFMSUBPS inum 4457 + REARRANGE needs to juggle: VFMSUBPS inum 4458 + REARRANGE one pattern worked for VFMSUBPS inum 4458 + REARRANGE needs to juggle: VFMSUBPS inum 4459 + REARRANGE one pattern worked for VFMSUBPS inum 4459 + SKIPPING VPUNPCKLQDQ inum 5121 -- already fine + SKIPPING VPUNPCKLQDQ inum 5122 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBPS inum=4460 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4461 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPS inum=4462 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPS inum=4463 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKLQDQ inum=5785 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKLQDQ inum=5786 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBPS inum 4460 -- already fine + SKIPPING VFMSUBPS inum 4461 -- already fine + SKIPPING VFMSUBPS inum 4462 -- already fine + SKIPPING VFMSUBPS inum 4463 -- already fine + REARRANGE needs to juggle: VPUNPCKLQDQ inum 5785 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBPS inum 4460 + REARRANGE one pattern worked for VFMSUBPS inum 4460 + REARRANGE needs to juggle: VFMSUBPS inum 4461 + REARRANGE one pattern worked for VFMSUBPS inum 4461 + REARRANGE needs to juggle: VFMSUBPS inum 4462 + REARRANGE one pattern worked for VFMSUBPS inum 4462 + REARRANGE needs to juggle: VFMSUBPS inum 4463 + REARRANGE one pattern worked for VFMSUBPS inum 4463 + SKIPPING VPUNPCKLQDQ inum 5785 -- already fine + SKIPPING VPUNPCKLQDQ inum 5786 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFMSUBPD inum=4464 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4465 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4466 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4467 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4468 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4469 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4470 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4471 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHQDQ inum=5113 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHQDQ inum=5114 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHQDQ inum=5777 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHQDQ inum=5778 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMSUBPD inum 4464 -- already fine + SKIPPING VFMSUBPD inum 4465 -- already fine + SKIPPING VFMSUBPD inum 4466 -- already fine + SKIPPING VFMSUBPD inum 4467 -- already fine + SKIPPING VFMSUBPD inum 4468 -- already fine + SKIPPING VFMSUBPD inum 4469 -- already fine + SKIPPING VFMSUBPD inum 4470 -- already fine + SKIPPING VFMSUBPD inum 4471 -- already fine + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5113 + REARRANGE one pattern worked for VPUNPCKHQDQ inum 5113 + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5114 + REARRANGE one pattern worked for VPUNPCKHQDQ inum 5114 + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5777 + REARRANGE one pattern worked for VPUNPCKHQDQ inum 5777 + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5778 + REARRANGE one pattern worked for VPUNPCKHQDQ inum 5778 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMSUBPD inum=4464 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4465 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4466 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4467 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4468 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4469 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4470 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4471 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHQDQ inum=5113 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHQDQ inum=5114 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VPUNPCKHQDQ inum=5777 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHQDQ inum=5778 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBPD inum 4464 -- already fine + SKIPPING VFMSUBPD inum 4465 -- already fine + SKIPPING VFMSUBPD inum 4466 -- already fine + SKIPPING VFMSUBPD inum 4467 -- already fine + SKIPPING VFMSUBPD inum 4468 -- already fine + SKIPPING VFMSUBPD inum 4469 -- already fine + SKIPPING VFMSUBPD inum 4470 -- already fine + SKIPPING VFMSUBPD inum 4471 -- already fine + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5113 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFMSUBPD inum 4464 + REARRANGE one pattern worked for VFMSUBPD inum 4464 + REARRANGE needs to juggle: VFMSUBPD inum 4465 + REARRANGE one pattern worked for VFMSUBPD inum 4465 + REARRANGE needs to juggle: VFMSUBPD inum 4466 + REARRANGE one pattern worked for VFMSUBPD inum 4466 + REARRANGE needs to juggle: VFMSUBPD inum 4467 + REARRANGE one pattern worked for VFMSUBPD inum 4467 + REARRANGE needs to juggle: VFMSUBPD inum 4468 + REARRANGE one pattern worked for VFMSUBPD inum 4468 + REARRANGE needs to juggle: VFMSUBPD inum 4469 + REARRANGE one pattern worked for VFMSUBPD inum 4469 + REARRANGE needs to juggle: VFMSUBPD inum 4470 + REARRANGE one pattern worked for VFMSUBPD inum 4470 + REARRANGE needs to juggle: VFMSUBPD inum 4471 + REARRANGE one pattern worked for VFMSUBPD inum 4471 + SKIPPING VPUNPCKHQDQ inum 5113 -- already fine + SKIPPING VPUNPCKHQDQ inum 5114 -- already fine + SKIPPING VPUNPCKHQDQ inum 5777 -- already fine + SKIPPING VPUNPCKHQDQ inum 5778 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBPD inum=4464 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4465 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4466 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4467 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHQDQ inum=5113 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHQDQ inum=5114 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBPD inum 4464 -- already fine + SKIPPING VFMSUBPD inum 4465 -- already fine + SKIPPING VFMSUBPD inum 4466 -- already fine + SKIPPING VFMSUBPD inum 4467 -- already fine + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5113 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBPD inum 4464 + REARRANGE one pattern worked for VFMSUBPD inum 4464 + REARRANGE needs to juggle: VFMSUBPD inum 4465 + REARRANGE one pattern worked for VFMSUBPD inum 4465 + REARRANGE needs to juggle: VFMSUBPD inum 4466 + REARRANGE one pattern worked for VFMSUBPD inum 4466 + REARRANGE needs to juggle: VFMSUBPD inum 4467 + REARRANGE one pattern worked for VFMSUBPD inum 4467 + SKIPPING VPUNPCKHQDQ inum 5113 -- already fine + SKIPPING VPUNPCKHQDQ inum 5114 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFMSUBPD inum=4468 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4469 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBPD inum=4470 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBPD inum=4471 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPUNPCKHQDQ inum=5777 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPUNPCKHQDQ inum=5778 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 0 1 1 0 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBPD inum 4468 -- already fine + SKIPPING VFMSUBPD inum 4469 -- already fine + SKIPPING VFMSUBPD inum 4470 -- already fine + SKIPPING VFMSUBPD inum 4471 -- already fine + REARRANGE needs to juggle: VPUNPCKHQDQ inum 5777 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBPD inum 4468 + REARRANGE one pattern worked for VFMSUBPD inum 4468 + REARRANGE needs to juggle: VFMSUBPD inum 4469 + REARRANGE one pattern worked for VFMSUBPD inum 4469 + REARRANGE needs to juggle: VFMSUBPD inum 4470 + REARRANGE one pattern worked for VFMSUBPD inum 4470 + REARRANGE needs to juggle: VFMSUBPD inum 4471 + REARRANGE one pattern worked for VFMSUBPD inum 4471 + SKIPPING VPUNPCKHQDQ inum 5777 -- already fine + SKIPPING VPUNPCKHQDQ inum 5778 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFMSUBSS inum=4472 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSS inum=4473 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBSS inum=4474 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSS inum=4475 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVD inum=4929 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4930 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVD inum=4933 isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4934 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVQ inum=4937 iform_input=VMOVQ_XMMdq_MEMq_6E isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVQ inum=4938 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMSUBSS inum 4472 -- already fine + SKIPPING VFMSUBSS inum 4473 -- already fine + SKIPPING VFMSUBSS inum 4474 -- already fine + SKIPPING VFMSUBSS inum 4475 -- already fine + REARRANGE needs to juggle: VMOVD inum 4929 + REARRANGE one pattern worked for VMOVD inum 4929 + REARRANGE needs to juggle: VMOVD inum 4930 + REARRANGE one pattern worked for VMOVD inum 4930 + REARRANGE needs to juggle: VMOVD inum 4933 + REARRANGE one pattern worked for VMOVD inum 4933 + REARRANGE needs to juggle: VMOVD inum 4934 + REARRANGE one pattern worked for VMOVD inum 4934 + REARRANGE needs to juggle: VMOVQ inum 4937 + REARRANGE one pattern worked for VMOVQ inum 4937 + REARRANGE needs to juggle: VMOVQ inum 4938 + REARRANGE one pattern worked for VMOVQ inum 4938 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMSUBSS inum=4472 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSS inum=4473 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBSS inum=4474 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSS inum=4475 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVD inum=4929 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4930 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVD inum=4933 isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4934 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVQ inum=4937 iform_input=VMOVQ_XMMdq_MEMq_6E isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVQ inum=4938 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBSS inum 4472 -- already fine + SKIPPING VFMSUBSS inum 4473 -- already fine + SKIPPING VFMSUBSS inum 4474 -- already fine + SKIPPING VFMSUBSS inum 4475 -- already fine + REARRANGE needs to juggle: VMOVD inum 4929 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBSS inum 4472 + REARRANGE one pattern worked for VFMSUBSS inum 4472 + REARRANGE needs to juggle: VFMSUBSS inum 4473 + REARRANGE one pattern worked for VFMSUBSS inum 4473 + REARRANGE needs to juggle: VFMSUBSS inum 4474 + REARRANGE one pattern worked for VFMSUBSS inum 4474 + REARRANGE needs to juggle: VFMSUBSS inum 4475 + REARRANGE one pattern worked for VFMSUBSS inum 4475 + REARRANGE needs to juggle: VMOVD inum 4929 + REARRANGE one pattern worked for VMOVD inum 4929 + REARRANGE needs to juggle: VMOVD inum 4930 + REARRANGE one pattern worked for VMOVD inum 4930 + REARRANGE needs to juggle: VMOVD inum 4933 + REARRANGE one pattern worked for VMOVD inum 4933 + REARRANGE needs to juggle: VMOVD inum 4934 + REARRANGE one pattern worked for VMOVD inum 4934 + REARRANGE needs to juggle: VMOVQ inum 4937 + REARRANGE one pattern worked for VMOVQ inum 4937 + REARRANGE needs to juggle: VMOVQ inum 4938 + REARRANGE one pattern worked for VMOVQ inum 4938 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFMSUBSD inum=4476 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSD inum=4477 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBSD inum=4478 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSD inum=4479 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVDQA inum=4949 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4950 iform_input=VMOVDQA_XMMdq_XMMdq_6F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQA inum=4953 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4954 iform_input=VMOVDQA_YMMqq_YMMqq_6F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQU inum=4957 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=0 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQU inum=4958 iform_input=VMOVDQU_XMMdq_XMMdq_6F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=0 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQU inum=4959 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=1 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQU inum=4960 iform_input=VMOVDQU_YMMqq_YMMqq_6F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VL=1 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFMSUBSD inum 4476 -- already fine + SKIPPING VFMSUBSD inum 4477 -- already fine + SKIPPING VFMSUBSD inum 4478 -- already fine + SKIPPING VFMSUBSD inum 4479 -- already fine + REARRANGE needs to juggle: VMOVDQA inum 4949 + REARRANGE one pattern worked for VMOVDQA inum 4949 + REARRANGE needs to juggle: VMOVDQA inum 4950 + REARRANGE one pattern worked for VMOVDQA inum 4950 + REARRANGE needs to juggle: VMOVDQA inum 4953 + REARRANGE one pattern worked for VMOVDQA inum 4953 + REARRANGE needs to juggle: VMOVDQA inum 4954 + REARRANGE one pattern worked for VMOVDQA inum 4954 + REARRANGE needs to juggle: VMOVDQU inum 4957 + REARRANGE one pattern worked for VMOVDQU inum 4957 + REARRANGE needs to juggle: VMOVDQU inum 4958 + REARRANGE one pattern worked for VMOVDQU inum 4958 + REARRANGE needs to juggle: VMOVDQU inum 4959 + REARRANGE one pattern worked for VMOVDQU inum 4959 + REARRANGE needs to juggle: VMOVDQU inum 4960 + REARRANGE one pattern worked for VMOVDQU inum 4960 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFMSUBSD inum=4476 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSD inum=4477 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFMSUBSD inum=4478 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFMSUBSD inum=4479 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVDQA inum=4949 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4950 iform_input=VMOVDQA_XMMdq_XMMdq_6F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQA inum=4953 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4954 iform_input=VMOVDQA_YMMqq_YMMqq_6F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 0 1 1 1 1 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFMSUBSD inum 4476 -- already fine + SKIPPING VFMSUBSD inum 4477 -- already fine + SKIPPING VFMSUBSD inum 4478 -- already fine + SKIPPING VFMSUBSD inum 4479 -- already fine + REARRANGE needs to juggle: VMOVDQA inum 4949 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFMSUBSD inum 4476 + REARRANGE one pattern worked for VFMSUBSD inum 4476 + REARRANGE needs to juggle: VFMSUBSD inum 4477 + REARRANGE one pattern worked for VFMSUBSD inum 4477 + REARRANGE needs to juggle: VFMSUBSD inum 4478 + REARRANGE one pattern worked for VFMSUBSD inum 4478 + REARRANGE needs to juggle: VFMSUBSD inum 4479 + REARRANGE one pattern worked for VFMSUBSD inum 4479 + REARRANGE needs to juggle: VMOVDQA inum 4949 + REARRANGE one pattern worked for VMOVDQA inum 4949 + REARRANGE needs to juggle: VMOVDQA inum 4950 + REARRANGE one pattern worked for VMOVDQA inum 4950 + REARRANGE needs to juggle: VMOVDQA inum 4953 + REARRANGE one pattern worked for VMOVDQA inum 4953 + REARRANGE needs to juggle: VMOVDQA inum 4954 + REARRANGE one pattern worked for VMOVDQA inum 4954 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFNMADDPS inum=4480 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4481 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPS inum=4482 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4483 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPS inum=4484 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4485 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPS inum=4486 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4487 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPBROADCASTB inum=5870 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTB inum=5871 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPBROADCASTB inum=5872 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTB inum=5873 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFNMADDPS inum 4480 -- already fine + SKIPPING VFNMADDPS inum 4481 -- already fine + SKIPPING VFNMADDPS inum 4482 -- already fine + SKIPPING VFNMADDPS inum 4483 -- already fine + SKIPPING VFNMADDPS inum 4484 -- already fine + SKIPPING VFNMADDPS inum 4485 -- already fine + SKIPPING VFNMADDPS inum 4486 -- already fine + SKIPPING VFNMADDPS inum 4487 -- already fine + REARRANGE needs to juggle: VPBROADCASTB inum 5870 + REARRANGE one pattern worked for VPBROADCASTB inum 5870 + REARRANGE needs to juggle: VPBROADCASTB inum 5871 + REARRANGE one pattern worked for VPBROADCASTB inum 5871 + REARRANGE needs to juggle: VPBROADCASTB inum 5872 + REARRANGE one pattern worked for VPBROADCASTB inum 5872 + REARRANGE needs to juggle: VPBROADCASTB inum 5873 + REARRANGE one pattern worked for VPBROADCASTB inum 5873 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFNMADDPS inum=4480 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4481 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPS inum=4482 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4483 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPS inum=4484 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4485 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPS inum=4486 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPS inum=4487 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPBROADCASTB inum=5870 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTB inum=5871 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 VL=0 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPBROADCASTB inum=5872 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTB inum=5873 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 0 VEX_PREFIX=1 VL=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMADDPS inum 4480 -- already fine + SKIPPING VFNMADDPS inum 4481 -- already fine + SKIPPING VFNMADDPS inum 4482 -- already fine + SKIPPING VFNMADDPS inum 4483 -- already fine + SKIPPING VFNMADDPS inum 4484 -- already fine + SKIPPING VFNMADDPS inum 4485 -- already fine + SKIPPING VFNMADDPS inum 4486 -- already fine + SKIPPING VFNMADDPS inum 4487 -- already fine + REARRANGE needs to juggle: VPBROADCASTB inum 5870 + REARRANGE one pattern worked for VPBROADCASTB inum 5870 + REARRANGE needs to juggle: VPBROADCASTB inum 5871 + REARRANGE one pattern worked for VPBROADCASTB inum 5871 + REARRANGE needs to juggle: VPBROADCASTB inum 5872 + REARRANGE one pattern worked for VPBROADCASTB inum 5872 + REARRANGE needs to juggle: VPBROADCASTB inum 5873 + REARRANGE one pattern worked for VPBROADCASTB inum 5873 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFNMADDPD inum=4488 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4489 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPD inum=4490 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4491 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPD inum=4492 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4493 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPD inum=4494 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4495 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPBROADCASTW inum=5874 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTW inum=5875 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPBROADCASTW inum=5876 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTW inum=5877 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFNMADDPD inum 4488 -- already fine + SKIPPING VFNMADDPD inum 4489 -- already fine + SKIPPING VFNMADDPD inum 4490 -- already fine + SKIPPING VFNMADDPD inum 4491 -- already fine + SKIPPING VFNMADDPD inum 4492 -- already fine + SKIPPING VFNMADDPD inum 4493 -- already fine + SKIPPING VFNMADDPD inum 4494 -- already fine + SKIPPING VFNMADDPD inum 4495 -- already fine + REARRANGE needs to juggle: VPBROADCASTW inum 5874 + REARRANGE one pattern worked for VPBROADCASTW inum 5874 + REARRANGE needs to juggle: VPBROADCASTW inum 5875 + REARRANGE one pattern worked for VPBROADCASTW inum 5875 + REARRANGE needs to juggle: VPBROADCASTW inum 5876 + REARRANGE one pattern worked for VPBROADCASTW inum 5876 + REARRANGE needs to juggle: VPBROADCASTW inum 5877 + REARRANGE one pattern worked for VPBROADCASTW inum 5877 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFNMADDPD inum=4488 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4489 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPD inum=4490 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4491 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPD inum=4492 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4493 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMADDPD inum=4494 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMADDPD inum=4495 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VPBROADCASTW inum=5874 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 VL=0 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTW inum=5875 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 VL=0 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VPBROADCASTW inum=5876 isa_set=AVX2 pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 VL=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VPBROADCASTW inum=5877 isa_set=AVX2 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 0 0 1 VEX_PREFIX=1 VL=1 MAP=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMADDPD inum 4488 -- already fine + SKIPPING VFNMADDPD inum 4489 -- already fine + SKIPPING VFNMADDPD inum 4490 -- already fine + SKIPPING VFNMADDPD inum 4491 -- already fine + SKIPPING VFNMADDPD inum 4492 -- already fine + SKIPPING VFNMADDPD inum 4493 -- already fine + SKIPPING VFNMADDPD inum 4494 -- already fine + SKIPPING VFNMADDPD inum 4495 -- already fine + REARRANGE needs to juggle: VPBROADCASTW inum 5874 + REARRANGE one pattern worked for VPBROADCASTW inum 5874 + REARRANGE needs to juggle: VPBROADCASTW inum 5875 + REARRANGE one pattern worked for VPBROADCASTW inum 5875 + REARRANGE needs to juggle: VPBROADCASTW inum 5876 + REARRANGE one pattern worked for VPBROADCASTW inum 5876 + REARRANGE needs to juggle: VPBROADCASTW inum 5877 + REARRANGE one pattern worked for VPBROADCASTW inum 5877 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFNMSUBPS inum=4504 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4505 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4506 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4507 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4508 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4509 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4510 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4511 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHADDPD inum=4825 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPD inum=4826 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VHADDPD inum=4827 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPD inum=4828 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VHADDPS inum=4829 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=0 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPS inum=4830 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VHADDPS inum=4831 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=1 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPS inum=4832 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VL=1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFNMSUBPS inum 4504 -- already fine + SKIPPING VFNMSUBPS inum 4505 -- already fine + SKIPPING VFNMSUBPS inum 4506 -- already fine + SKIPPING VFNMSUBPS inum 4507 -- already fine + SKIPPING VFNMSUBPS inum 4508 -- already fine + SKIPPING VFNMSUBPS inum 4509 -- already fine + SKIPPING VFNMSUBPS inum 4510 -- already fine + SKIPPING VFNMSUBPS inum 4511 -- already fine + REARRANGE needs to juggle: VHADDPD inum 4825 + REARRANGE one pattern worked for VHADDPD inum 4825 + REARRANGE needs to juggle: VHADDPD inum 4826 + REARRANGE one pattern worked for VHADDPD inum 4826 + REARRANGE needs to juggle: VHADDPD inum 4827 + REARRANGE one pattern worked for VHADDPD inum 4827 + REARRANGE needs to juggle: VHADDPD inum 4828 + REARRANGE one pattern worked for VHADDPD inum 4828 + REARRANGE needs to juggle: VHADDPS inum 4829 + REARRANGE one pattern worked for VHADDPS inum 4829 + REARRANGE needs to juggle: VHADDPS inum 4830 + REARRANGE one pattern worked for VHADDPS inum 4830 + REARRANGE needs to juggle: VHADDPS inum 4831 + REARRANGE one pattern worked for VHADDPS inum 4831 + REARRANGE needs to juggle: VHADDPS inum 4832 + REARRANGE one pattern worked for VHADDPS inum 4832 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFNMSUBPS inum=4504 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4505 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4506 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4507 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4508 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4509 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4510 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4511 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHADDPD inum=4825 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPD inum=4826 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VHADDPD inum=4827 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPD inum=4828 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBPS inum 4504 -- already fine + SKIPPING VFNMSUBPS inum 4505 -- already fine + SKIPPING VFNMSUBPS inum 4506 -- already fine + SKIPPING VFNMSUBPS inum 4507 -- already fine + SKIPPING VFNMSUBPS inum 4508 -- already fine + SKIPPING VFNMSUBPS inum 4509 -- already fine + SKIPPING VFNMSUBPS inum 4510 -- already fine + SKIPPING VFNMSUBPS inum 4511 -- already fine + REARRANGE needs to juggle: VHADDPD inum 4825 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFNMSUBPS inum 4504 + REARRANGE one pattern worked for VFNMSUBPS inum 4504 + REARRANGE needs to juggle: VFNMSUBPS inum 4505 + REARRANGE one pattern worked for VFNMSUBPS inum 4505 + REARRANGE needs to juggle: VFNMSUBPS inum 4506 + REARRANGE one pattern worked for VFNMSUBPS inum 4506 + REARRANGE needs to juggle: VFNMSUBPS inum 4507 + REARRANGE one pattern worked for VFNMSUBPS inum 4507 + REARRANGE needs to juggle: VFNMSUBPS inum 4508 + REARRANGE one pattern worked for VFNMSUBPS inum 4508 + REARRANGE needs to juggle: VFNMSUBPS inum 4509 + REARRANGE one pattern worked for VFNMSUBPS inum 4509 + REARRANGE needs to juggle: VFNMSUBPS inum 4510 + REARRANGE one pattern worked for VFNMSUBPS inum 4510 + REARRANGE needs to juggle: VFNMSUBPS inum 4511 + REARRANGE one pattern worked for VFNMSUBPS inum 4511 + SKIPPING VHADDPD inum 4825 -- already fine + SKIPPING VHADDPD inum 4826 -- already fine + SKIPPING VHADDPD inum 4827 -- already fine + SKIPPING VHADDPD inum 4828 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFNMSUBPS inum=4504 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4505 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4506 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4507 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHADDPD inum=4825 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPD inum=4826 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBPS inum 4504 -- already fine + SKIPPING VFNMSUBPS inum 4505 -- already fine + SKIPPING VFNMSUBPS inum 4506 -- already fine + SKIPPING VFNMSUBPS inum 4507 -- already fine + REARRANGE needs to juggle: VHADDPD inum 4825 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFNMSUBPS inum 4504 + REARRANGE one pattern worked for VFNMSUBPS inum 4504 + REARRANGE needs to juggle: VFNMSUBPS inum 4505 + REARRANGE one pattern worked for VFNMSUBPS inum 4505 + REARRANGE needs to juggle: VFNMSUBPS inum 4506 + REARRANGE one pattern worked for VFNMSUBPS inum 4506 + REARRANGE needs to juggle: VFNMSUBPS inum 4507 + REARRANGE one pattern worked for VFNMSUBPS inum 4507 + SKIPPING VHADDPD inum 4825 -- already fine + SKIPPING VHADDPD inum 4826 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFNMSUBPS inum=4508 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4509 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPS inum=4510 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPS inum=4511 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHADDPD inum=4827 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHADDPD inum=4828 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 0 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBPS inum 4508 -- already fine + SKIPPING VFNMSUBPS inum 4509 -- already fine + SKIPPING VFNMSUBPS inum 4510 -- already fine + SKIPPING VFNMSUBPS inum 4511 -- already fine + REARRANGE needs to juggle: VHADDPD inum 4827 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFNMSUBPS inum 4508 + REARRANGE one pattern worked for VFNMSUBPS inum 4508 + REARRANGE needs to juggle: VFNMSUBPS inum 4509 + REARRANGE one pattern worked for VFNMSUBPS inum 4509 + REARRANGE needs to juggle: VFNMSUBPS inum 4510 + REARRANGE one pattern worked for VFNMSUBPS inum 4510 + REARRANGE needs to juggle: VFNMSUBPS inum 4511 + REARRANGE one pattern worked for VFNMSUBPS inum 4511 + SKIPPING VHADDPD inum 4827 -- already fine + SKIPPING VHADDPD inum 4828 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFNMSUBPD inum=4512 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4513 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4514 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4515 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4516 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4517 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4518 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4519 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHSUBPD inum=4833 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPD inum=4834 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VHSUBPD inum=4835 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPD inum=4836 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VHSUBPS inum=4837 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=0 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPS inum=4838 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +VHSUBPS inum=4839 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=1 VEX_PREFIX=2 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPS inum=4840 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VL=1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFNMSUBPD inum 4512 -- already fine + SKIPPING VFNMSUBPD inum 4513 -- already fine + SKIPPING VFNMSUBPD inum 4514 -- already fine + SKIPPING VFNMSUBPD inum 4515 -- already fine + SKIPPING VFNMSUBPD inum 4516 -- already fine + SKIPPING VFNMSUBPD inum 4517 -- already fine + SKIPPING VFNMSUBPD inum 4518 -- already fine + SKIPPING VFNMSUBPD inum 4519 -- already fine + REARRANGE needs to juggle: VHSUBPD inum 4833 + REARRANGE one pattern worked for VHSUBPD inum 4833 + REARRANGE needs to juggle: VHSUBPD inum 4834 + REARRANGE one pattern worked for VHSUBPD inum 4834 + REARRANGE needs to juggle: VHSUBPD inum 4835 + REARRANGE one pattern worked for VHSUBPD inum 4835 + REARRANGE needs to juggle: VHSUBPD inum 4836 + REARRANGE one pattern worked for VHSUBPD inum 4836 + REARRANGE needs to juggle: VHSUBPS inum 4837 + REARRANGE one pattern worked for VHSUBPS inum 4837 + REARRANGE needs to juggle: VHSUBPS inum 4838 + REARRANGE one pattern worked for VHSUBPS inum 4838 + REARRANGE needs to juggle: VHSUBPS inum 4839 + REARRANGE one pattern worked for VHSUBPS inum 4839 + REARRANGE needs to juggle: VHSUBPS inum 4840 + REARRANGE one pattern worked for VHSUBPS inum 4840 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFNMSUBPD inum=4512 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4513 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4514 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4515 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4516 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4517 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=0 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4518 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4519 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 REXW=1 VL=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHSUBPD inum=4833 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPD inum=4834 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +VHSUBPD inum=4835 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPD inum=4836 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBPD inum 4512 -- already fine + SKIPPING VFNMSUBPD inum 4513 -- already fine + SKIPPING VFNMSUBPD inum 4514 -- already fine + SKIPPING VFNMSUBPD inum 4515 -- already fine + SKIPPING VFNMSUBPD inum 4516 -- already fine + SKIPPING VFNMSUBPD inum 4517 -- already fine + SKIPPING VFNMSUBPD inum 4518 -- already fine + SKIPPING VFNMSUBPD inum 4519 -- already fine + REARRANGE needs to juggle: VHSUBPD inum 4833 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using VL + REARRANGE needs to juggle: VFNMSUBPD inum 4512 + REARRANGE one pattern worked for VFNMSUBPD inum 4512 + REARRANGE needs to juggle: VFNMSUBPD inum 4513 + REARRANGE one pattern worked for VFNMSUBPD inum 4513 + REARRANGE needs to juggle: VFNMSUBPD inum 4514 + REARRANGE one pattern worked for VFNMSUBPD inum 4514 + REARRANGE needs to juggle: VFNMSUBPD inum 4515 + REARRANGE one pattern worked for VFNMSUBPD inum 4515 + REARRANGE needs to juggle: VFNMSUBPD inum 4516 + REARRANGE one pattern worked for VFNMSUBPD inum 4516 + REARRANGE needs to juggle: VFNMSUBPD inum 4517 + REARRANGE one pattern worked for VFNMSUBPD inum 4517 + REARRANGE needs to juggle: VFNMSUBPD inum 4518 + REARRANGE one pattern worked for VFNMSUBPD inum 4518 + REARRANGE needs to juggle: VFNMSUBPD inum 4519 + REARRANGE one pattern worked for VFNMSUBPD inum 4519 + SKIPPING VHSUBPD inum 4833 -- already fine + SKIPPING VHSUBPD inum 4834 -- already fine + SKIPPING VHSUBPD inum 4835 -- already fine + SKIPPING VHSUBPD inum 4836 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 11 +Others: +VFNMSUBPD inum=4512 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4513 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4514 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4515 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHSUBPD inum=4833 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPD inum=4834 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=0 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBPD inum 4512 -- already fine + SKIPPING VFNMSUBPD inum 4513 -- already fine + SKIPPING VFNMSUBPD inum 4514 -- already fine + SKIPPING VFNMSUBPD inum 4515 -- already fine + REARRANGE needs to juggle: VHSUBPD inum 4833 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFNMSUBPD inum 4512 + REARRANGE one pattern worked for VFNMSUBPD inum 4512 + REARRANGE needs to juggle: VFNMSUBPD inum 4513 + REARRANGE one pattern worked for VFNMSUBPD inum 4513 + REARRANGE needs to juggle: VFNMSUBPD inum 4514 + REARRANGE one pattern worked for VFNMSUBPD inum 4514 + REARRANGE needs to juggle: VFNMSUBPD inum 4515 + REARRANGE one pattern worked for VFNMSUBPD inum 4515 + SKIPPING VHSUBPD inum 4833 -- already fine + SKIPPING VHSUBPD inum 4834 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +VFNMSUBPD inum=4516 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4517 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBPD inum=4518 isa_set=FMA4 pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBPD inum=4519 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VHSUBPD inum=4835 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VHSUBPD inum=4836 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 0 1 1 1 1 1 0 1 VEX_PREFIX=1 VL=1 MAP=1 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBPD inum 4516 -- already fine + SKIPPING VFNMSUBPD inum 4517 -- already fine + SKIPPING VFNMSUBPD inum 4518 -- already fine + SKIPPING VFNMSUBPD inum 4519 -- already fine + REARRANGE needs to juggle: VHSUBPD inum 4835 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFNMSUBPD inum 4516 + REARRANGE one pattern worked for VFNMSUBPD inum 4516 + REARRANGE needs to juggle: VFNMSUBPD inum 4517 + REARRANGE one pattern worked for VFNMSUBPD inum 4517 + REARRANGE needs to juggle: VFNMSUBPD inum 4518 + REARRANGE one pattern worked for VFNMSUBPD inum 4518 + REARRANGE needs to juggle: VFNMSUBPD inum 4519 + REARRANGE one pattern worked for VFNMSUBPD inum 4519 + SKIPPING VHSUBPD inum 4835 -- already fine + SKIPPING VHSUBPD inum 4836 -- already fine +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 9 +Others: +VFNMSUBSS inum=4520 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSS inum=4521 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBSS inum=4522 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSS inum=4523 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVD inum=4931 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4932 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVD inum=4935 isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4936 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVQ inum=4939 iform_input=VMOVQ_MEMq_XMMq_7E isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVQ inum=4940 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVQ inum=4941 iform_input=VMOVQ_XMMdq_MEMq_7E isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVQ inum=4942 iform_input=VMOVQ_XMMdq_XMMq_7E isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VL=0 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFNMSUBSS inum 4520 -- already fine + SKIPPING VFNMSUBSS inum 4521 -- already fine + SKIPPING VFNMSUBSS inum 4522 -- already fine + SKIPPING VFNMSUBSS inum 4523 -- already fine + REARRANGE needs to juggle: VMOVD inum 4931 + REARRANGE one pattern worked for VMOVD inum 4931 + REARRANGE needs to juggle: VMOVD inum 4932 + REARRANGE one pattern worked for VMOVD inum 4932 + REARRANGE needs to juggle: VMOVD inum 4935 + REARRANGE one pattern worked for VMOVD inum 4935 + REARRANGE needs to juggle: VMOVD inum 4936 + REARRANGE one pattern worked for VMOVD inum 4936 + REARRANGE needs to juggle: VMOVQ inum 4939 + REARRANGE one pattern worked for VMOVQ inum 4939 + REARRANGE needs to juggle: VMOVQ inum 4940 + REARRANGE one pattern worked for VMOVQ inum 4940 + REARRANGE needs to juggle: VMOVQ inum 4941 + REARRANGE one pattern worked for VMOVQ inum 4941 + REARRANGE needs to juggle: VMOVQ inum 4942 + REARRANGE one pattern worked for VMOVQ inum 4942 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFNMSUBSS inum=4520 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSS inum=4521 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBSS inum=4522 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSS inum=4523 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVD inum=4931 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4932 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVD inum=4935 isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVD inum=4936 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVQ inum=4939 iform_input=VMOVQ_MEMq_XMMq_7E isa_set=AVX pattern len=26 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVQ inum=4940 isa_set=AVX pattern len=25 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 0 VEX_PREFIX=1 VL=0 MAP=1 MODE=2 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBSS inum 4520 -- already fine + SKIPPING VFNMSUBSS inum 4521 -- already fine + SKIPPING VFNMSUBSS inum 4522 -- already fine + SKIPPING VFNMSUBSS inum 4523 -- already fine + REARRANGE needs to juggle: VMOVD inum 4931 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFNMSUBSS inum 4520 + REARRANGE one pattern worked for VFNMSUBSS inum 4520 + REARRANGE needs to juggle: VFNMSUBSS inum 4521 + REARRANGE one pattern worked for VFNMSUBSS inum 4521 + REARRANGE needs to juggle: VFNMSUBSS inum 4522 + REARRANGE one pattern worked for VFNMSUBSS inum 4522 + REARRANGE needs to juggle: VFNMSUBSS inum 4523 + REARRANGE one pattern worked for VFNMSUBSS inum 4523 + REARRANGE needs to juggle: VMOVD inum 4931 + REARRANGE one pattern worked for VMOVD inum 4931 + REARRANGE needs to juggle: VMOVD inum 4932 + REARRANGE one pattern worked for VMOVD inum 4932 + REARRANGE needs to juggle: VMOVD inum 4935 + REARRANGE one pattern worked for VMOVD inum 4935 + REARRANGE needs to juggle: VMOVD inum 4936 + REARRANGE one pattern worked for VMOVD inum 4936 + REARRANGE needs to juggle: VMOVQ inum 4939 + REARRANGE one pattern worked for VMOVQ inum 4939 + REARRANGE needs to juggle: VMOVQ inum 4940 + REARRANGE one pattern worked for VMOVQ inum 4940 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VFNMSUBSD inum=4524 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSD inum=4525 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBSD inum=4526 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSD inum=4527 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVDQA inum=4951 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4952 iform_input=VMOVDQA_XMMdq_XMMdq_7F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQA inum=4955 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4956 iform_input=VMOVDQA_YMMqq_YMMqq_7F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQU inum=4961 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=0 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQU inum=4962 iform_input=VMOVDQU_XMMdq_XMMdq_7F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=0 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQU inum=4963 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=1 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQU inum=4964 iform_input=VMOVDQU_YMMqq_YMMqq_7F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VL=1 VEX_PREFIX=3 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VFNMSUBSD inum 4524 -- already fine + SKIPPING VFNMSUBSD inum 4525 -- already fine + SKIPPING VFNMSUBSD inum 4526 -- already fine + SKIPPING VFNMSUBSD inum 4527 -- already fine + REARRANGE needs to juggle: VMOVDQA inum 4951 + REARRANGE one pattern worked for VMOVDQA inum 4951 + REARRANGE needs to juggle: VMOVDQA inum 4952 + REARRANGE one pattern worked for VMOVDQA inum 4952 + REARRANGE needs to juggle: VMOVDQA inum 4955 + REARRANGE one pattern worked for VMOVDQA inum 4955 + REARRANGE needs to juggle: VMOVDQA inum 4956 + REARRANGE one pattern worked for VMOVDQA inum 4956 + REARRANGE needs to juggle: VMOVDQU inum 4961 + REARRANGE one pattern worked for VMOVDQU inum 4961 + REARRANGE needs to juggle: VMOVDQU inum 4962 + REARRANGE one pattern worked for VMOVDQU inum 4962 + REARRANGE needs to juggle: VMOVDQU inum 4963 + REARRANGE one pattern worked for VMOVDQU inum 4963 + REARRANGE needs to juggle: VMOVDQU inum 4964 + REARRANGE one pattern worked for VMOVDQU inum 4964 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VFNMSUBSD inum=4524 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSD inum=4525 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=0 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VFNMSUBSD inum=4526 isa_set=FMA4 pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 m m MOD!=3 r r r n n n MODRM() SE_IMM8() + +VFNMSUBSD inum=4527 isa_set=FMA4 pattern len=22 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 REXW=1 MAP=3 1 1 MOD=3 r r r n n n SE_IMM8() + +VMOVDQA inum=4951 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4952 iform_input=VMOVDQA_XMMdq_XMMdq_7F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 VL=0 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +VMOVDQA inum=4955 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VMOVDQA inum=4956 iform_input=VMOVDQA_YMMqq_YMMqq_7F isa_set=AVX pattern len=23 + ipattern: VEXVALID=1 0 1 1 1 1 1 1 1 VEX_PREFIX=1 VL=1 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VFNMSUBSD inum 4524 -- already fine + SKIPPING VFNMSUBSD inum 4525 -- already fine + SKIPPING VFNMSUBSD inum 4526 -- already fine + SKIPPING VFNMSUBSD inum 4527 -- already fine + REARRANGE needs to juggle: VMOVDQA inum 4951 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MAP + REARRANGE needs to juggle: VFNMSUBSD inum 4524 + REARRANGE one pattern worked for VFNMSUBSD inum 4524 + REARRANGE needs to juggle: VFNMSUBSD inum 4525 + REARRANGE one pattern worked for VFNMSUBSD inum 4525 + REARRANGE needs to juggle: VFNMSUBSD inum 4526 + REARRANGE one pattern worked for VFNMSUBSD inum 4526 + REARRANGE needs to juggle: VFNMSUBSD inum 4527 + REARRANGE one pattern worked for VFNMSUBSD inum 4527 + REARRANGE needs to juggle: VMOVDQA inum 4951 + REARRANGE one pattern worked for VMOVDQA inum 4951 + REARRANGE needs to juggle: VMOVDQA inum 4952 + REARRANGE one pattern worked for VMOVDQA inum 4952 + REARRANGE needs to juggle: VMOVDQA inum 4955 + REARRANGE one pattern worked for VMOVDQA inum 4955 + REARRANGE needs to juggle: VMOVDQA inum 4956 + REARRANGE one pattern worked for VMOVDQA inum 4956 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 9 +Others: +VPGATHERDQ inum=5617 iform_input=VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +VPGATHERDQ inum=5618 iform_input=VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +VPGATHERDD inum=5619 iform_input=VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_YMM() EASZ!=1 + +VPGATHERDD inum=5620 iform_input=VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +KMOVW inum=7043 iform_input=KMOVW_MASKmskw_MASKu16_AVX512 isa_set=AVX512F_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVW inum=7044 iform_input=KMOVW_MASKmskw_MEMu16_AVX512 isa_set=AVX512F_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVB inum=8882 iform_input=KMOVB_MASKmskw_MASKu8_AVX512 isa_set=AVX512DQ_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVB inum=8883 iform_input=KMOVB_MASKmskw_MEMu8_AVX512 isa_set=AVX512DQ_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8887 iform_input=KMOVD_MASKmskw_MASKu32_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8888 iform_input=KMOVD_MASKmskw_MEMu32_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8894 iform_input=KMOVQ_MASKmskw_MASKu64_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8895 iform_input=KMOVQ_MASKmskw_MEMu64_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 0 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPGATHERDQ inum 5617 -- already fine + SKIPPING VPGATHERDQ inum 5618 -- already fine + SKIPPING VPGATHERDD inum 5619 -- already fine + SKIPPING VPGATHERDD inum 5620 -- already fine + REARRANGE needs to juggle: KMOVW inum 7043 + REARRANGE one pattern worked for KMOVW inum 7043 + REARRANGE needs to juggle: KMOVW inum 7044 + REARRANGE one pattern worked for KMOVW inum 7044 + REARRANGE needs to juggle: KMOVB inum 8882 + REARRANGE one pattern worked for KMOVB inum 8882 + REARRANGE needs to juggle: KMOVB inum 8883 + REARRANGE one pattern worked for KMOVB inum 8883 + REARRANGE needs to juggle: KMOVD inum 8887 + REARRANGE one pattern worked for KMOVD inum 8887 + REARRANGE needs to juggle: KMOVD inum 8888 + REARRANGE one pattern worked for KMOVD inum 8888 + REARRANGE needs to juggle: KMOVQ inum 8894 + REARRANGE one pattern worked for KMOVQ inum 8894 + REARRANGE needs to juggle: KMOVQ inum 8895 + REARRANGE one pattern worked for KMOVQ inum 8895 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPGATHERQQ inum=5621 iform_input=VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_YMM() EASZ!=1 + +VPGATHERQQ inum=5622 iform_input=VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +VPGATHERQD inum=5623 iform_input=VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_YMM() EASZ!=1 + +VPGATHERQD inum=5624 iform_input=VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +KMOVW inum=7045 iform_input=KMOVW_MEMu16_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVB inum=8884 iform_input=KMOVB_MEMu8_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8889 iform_input=KMOVD_MEMu32_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8896 iform_input=KMOVQ_MEMu64_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 0 1 VEX_PREFIX=0 MAP=1 m m MOD!=3 r r r n n n MODRM() VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPGATHERQQ inum 5621 -- already fine + SKIPPING VPGATHERQQ inum 5622 -- already fine + SKIPPING VPGATHERQD inum 5623 -- already fine + SKIPPING VPGATHERQD inum 5624 -- already fine + REARRANGE needs to juggle: KMOVW inum 7045 + REARRANGE one pattern worked for KMOVW inum 7045 + REARRANGE needs to juggle: KMOVB inum 8884 + REARRANGE one pattern worked for KMOVB inum 8884 + REARRANGE needs to juggle: KMOVD inum 8889 + REARRANGE one pattern worked for KMOVD inum 8889 + REARRANGE needs to juggle: KMOVQ inum 8896 + REARRANGE one pattern worked for KMOVQ inum 8896 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VGATHERDPD inum=5609 iform_input=VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +VGATHERDPD inum=5610 iform_input=VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +VGATHERDPS inum=5611 iform_input=VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_YMM() EASZ!=1 + +VGATHERDPS inum=5612 iform_input=VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +KMOVW inum=7046 iform_input=KMOVW_MASKmskw_GPR32u32_AVX512 isa_set=AVX512F_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVB inum=8885 iform_input=KMOVB_MASKmskw_GPR32u32_AVX512 isa_set=AVX512DQ_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8890 iform_input=KMOVD_MASKmskw_GPR32u32_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8891 iform_input=KMOVD_MASKmskw_GPR32u32_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8897 iform_input=KMOVQ_MASKmskw_GPR64u64_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VGATHERDPD inum 5609 -- already fine + SKIPPING VGATHERDPD inum 5610 -- already fine + SKIPPING VGATHERDPS inum 5611 -- already fine + SKIPPING VGATHERDPS inum 5612 -- already fine + REARRANGE needs to juggle: KMOVW inum 7046 + REARRANGE one pattern worked for KMOVW inum 7046 + REARRANGE needs to juggle: KMOVB inum 8885 + REARRANGE one pattern worked for KMOVB inum 8885 + REARRANGE needs to juggle: KMOVD inum 8890 + REARRANGE one pattern worked for KMOVD inum 8890 + REARRANGE needs to juggle: KMOVD inum 8891 + REARRANGE one pattern worked for KMOVD inum 8891 + REARRANGE needs to juggle: KMOVQ inum 8897 + REARRANGE one pattern worked for KMOVQ inum 8897 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 21 +Others: +KMOVD inum=8890 iform_input=KMOVD_MASKmskw_GPR32u32_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8891 iform_input=KMOVD_MASKmskw_GPR32u32_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8897 iform_input=KMOVQ_MASKmskw_GPR64u64_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 0 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING KMOVD inum 8890 -- already fine + REARRANGE needs to juggle: KMOVD inum 8891 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: KMOVD inum 8890 + REARRANGE one pattern worked for KMOVD inum 8890 + SKIPPING KMOVD inum 8891 -- already fine + REARRANGE needs to juggle: KMOVQ inum 8897 + REARRANGE one pattern worked for KMOVQ inum 8897 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 21 +FUNKY SPOT: bitpos 9 +Others: +VGATHERQPD inum=5613 iform_input=VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_YMM() EASZ!=1 + +VGATHERQPD inum=5614 iform_input=VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +VGATHERQPS inum=5615 iform_input=VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_YMM() EASZ!=1 + +VGATHERQPS inum=5616 iform_input=VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 isa_set=AVX2GATHER pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n RM=4 VMODRM_XMM() EASZ!=1 + +KMOVW inum=7047 iform_input=KMOVW_GPR32u32_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVB inum=8886 iform_input=KMOVB_GPR32u32_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8892 iform_input=KMOVD_GPR32u32_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8893 iform_input=KMOVD_GPR32u32_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8898 iform_input=KMOVQ_GPR64u64_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VGATHERQPD inum 5613 -- already fine + SKIPPING VGATHERQPD inum 5614 -- already fine + SKIPPING VGATHERQPS inum 5615 -- already fine + SKIPPING VGATHERQPS inum 5616 -- already fine + REARRANGE needs to juggle: KMOVW inum 7047 + REARRANGE one pattern worked for KMOVW inum 7047 + REARRANGE needs to juggle: KMOVB inum 8886 + REARRANGE one pattern worked for KMOVB inum 8886 + REARRANGE needs to juggle: KMOVD inum 8892 + REARRANGE one pattern worked for KMOVD inum 8892 + REARRANGE needs to juggle: KMOVD inum 8893 + REARRANGE one pattern worked for KMOVD inum 8893 + REARRANGE needs to juggle: KMOVQ inum 8898 + REARRANGE one pattern worked for KMOVQ inum 8898 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 21 +Others: +KMOVD inum=8892 iform_input=KMOVD_GPR32u32_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVD inum=8893 iform_input=KMOVD_GPR32u32_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 + +KMOVQ inum=8898 iform_input=KMOVQ_GPR64u64_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=25 + ipattern: VEXVALID=1 1 0 0 1 0 0 1 1 VL=0 VEX_PREFIX=2 MAP=1 1 1 MOD=3 r r r n n n REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING KMOVD inum 8892 -- already fine + REARRANGE needs to juggle: KMOVD inum 8893 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: KMOVD inum 8892 + REARRANGE one pattern worked for KMOVD inum 8892 + SKIPPING KMOVD inum 8893 -- already fine + REARRANGE needs to juggle: KMOVQ inum 8898 + REARRANGE one pattern worked for KMOVQ inum 8898 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 21 +FUNKY SPOT: bitpos 9 +Others: +VFMADD132PD inum=5417 isa_set=FMA pattern len=23 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VFMADD132PD inum=5418 isa_set=FMA pattern len=22 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=1 1 1 MOD=3 r r r n n n + +VFMADD132PD inum=5419 isa_set=FMA pattern len=23 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=1 m m MOD!=3 r r r n n n MODRM() + +VFMADD132PD inum=5420 isa_set=FMA pattern len=22 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=1 1 1 MOD=3 r r r n n n + +VFMADD132PS inum=5421 isa_set=FMA pattern len=23 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VFMADD132PS inum=5422 isa_set=FMA pattern len=22 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=0 VEX_PREFIX=1 MAP=2 REXW=0 1 1 MOD=3 r r r n n n + +VFMADD132PS inum=5423 isa_set=FMA pattern len=23 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 m m MOD!=3 r r r n n n MODRM() + +VFMADD132PS inum=5424 isa_set=FMA pattern len=22 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VL=1 VEX_PREFIX=1 MAP=2 REXW=0 1 1 MOD=3 r r r n n n + +KORTESTW inum=7049 iform_input=KORTESTW_MASKmskw_MASKmskw_AVX512 isa_set=AVX512F_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KORTESTB inum=8905 iform_input=KORTESTB_MASKmskw_MASKmskw_AVX512 isa_set=AVX512DQ_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 + +KORTESTD inum=8906 iform_input=KORTESTD_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +KORTESTQ inum=8907 iform_input=KORTESTQ_MASKmskw_MASKmskw_AVX512 isa_set=AVX512BW_KOP pattern len=24 + ipattern: VEXVALID=1 1 0 0 1 1 0 0 0 VEX_PREFIX=0 MAP=1 1 1 MOD=3 r r r n n n VL=0 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VFMADD132PD inum 5417 -- already fine + SKIPPING VFMADD132PD inum 5418 -- already fine + SKIPPING VFMADD132PD inum 5419 -- already fine + SKIPPING VFMADD132PD inum 5420 -- already fine + SKIPPING VFMADD132PS inum 5421 -- already fine + SKIPPING VFMADD132PS inum 5422 -- already fine + SKIPPING VFMADD132PS inum 5423 -- already fine + SKIPPING VFMADD132PS inum 5424 -- already fine + REARRANGE needs to juggle: KORTESTW inum 7049 + REARRANGE one pattern worked for KORTESTW inum 7049 + REARRANGE needs to juggle: KORTESTB inum 8905 + REARRANGE one pattern worked for KORTESTB inum 8905 + REARRANGE needs to juggle: KORTESTD inum 8906 + REARRANGE one pattern worked for KORTESTD inum 8906 + REARRANGE needs to juggle: KORTESTQ inum 8907 + REARRANGE one pattern worked for KORTESTQ inum 8907 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPADDUSB inum=5031 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPADDUSB inum=5032 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPADDUSB inum=5667 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPADDUSB inum=5668 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VAESENC inum=5397 isa_set=AVXAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 + +VAESENC inum=5398 isa_set=AVXAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 + +VAESENC inum=9151 iform_input=VAESENC_YMMu128_YMMu128_YMMu128 isa_set=VAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 + +VAESENC inum=9152 iform_input=VAESENC_YMMu128_YMMu128_MEMu128 isa_set=VAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPADDUSB inum 5031 -- already fine + SKIPPING VPADDUSB inum 5032 -- already fine + SKIPPING VPADDUSB inum 5667 -- already fine + SKIPPING VPADDUSB inum 5668 -- already fine + REARRANGE needs to juggle: VAESENC inum 5397 + REARRANGE one pattern worked for VAESENC inum 5397 + REARRANGE needs to juggle: VAESENC inum 5398 + REARRANGE one pattern worked for VAESENC inum 5398 + REARRANGE needs to juggle: VAESENC inum 9151 + REARRANGE one pattern worked for VAESENC inum 9151 + REARRANGE needs to juggle: VAESENC inum 9152 + REARRANGE one pattern worked for VAESENC inum 9152 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPADDUSW inum=5033 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPADDUSW inum=5034 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPADDUSW inum=5669 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPADDUSW inum=5670 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VAESENCLAST inum=5399 isa_set=AVXAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 + +VAESENCLAST inum=5400 isa_set=AVXAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 + +VAESENCLAST inum=9153 iform_input=VAESENCLAST_YMMu128_YMMu128_YMMu128 isa_set=VAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 + +VAESENCLAST inum=9154 iform_input=VAESENCLAST_YMMu128_YMMu128_MEMu128 isa_set=VAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 0 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPADDUSW inum 5033 -- already fine + SKIPPING VPADDUSW inum 5034 -- already fine + SKIPPING VPADDUSW inum 5669 -- already fine + SKIPPING VPADDUSW inum 5670 -- already fine + REARRANGE needs to juggle: VAESENCLAST inum 5399 + REARRANGE one pattern worked for VAESENCLAST inum 5399 + REARRANGE needs to juggle: VAESENCLAST inum 5400 + REARRANGE one pattern worked for VAESENCLAST inum 5400 + REARRANGE needs to juggle: VAESENCLAST inum 9153 + REARRANGE one pattern worked for VAESENCLAST inum 9153 + REARRANGE needs to juggle: VAESENCLAST inum 9154 + REARRANGE one pattern worked for VAESENCLAST inum 9154 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPMAXUB inum=5221 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPMAXUB inum=5222 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPMAXUB inum=5713 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPMAXUB inum=5714 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VAESDEC inum=5401 isa_set=AVXAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 + +VAESDEC inum=5402 isa_set=AVXAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 + +VAESDEC inum=9147 iform_input=VAESDEC_YMMu128_YMMu128_YMMu128 isa_set=VAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 + +VAESDEC inum=9148 iform_input=VAESDEC_YMMu128_YMMu128_MEMu128 isa_set=VAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 0 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPMAXUB inum 5221 -- already fine + SKIPPING VPMAXUB inum 5222 -- already fine + SKIPPING VPMAXUB inum 5713 -- already fine + SKIPPING VPMAXUB inum 5714 -- already fine + REARRANGE needs to juggle: VAESDEC inum 5401 + REARRANGE one pattern worked for VAESDEC inum 5401 + REARRANGE needs to juggle: VAESDEC inum 5402 + REARRANGE one pattern worked for VAESDEC inum 5402 + REARRANGE needs to juggle: VAESDEC inum 9147 + REARRANGE one pattern worked for VAESDEC inum 9147 + REARRANGE needs to juggle: VAESDEC inum 9148 + REARRANGE one pattern worked for VAESDEC inum 9148 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VPANDN inum=4977 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPANDN inum=4978 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPANDN inum=5797 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPANDN inum=5798 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VAESKEYGENASSIST inum=5395 isa_set=AVXAES pattern len=24 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +VAESKEYGENASSIST inum=5396 isa_set=AVXAES pattern len=25 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VL=0 VEX_PREFIX=1 MAP=3 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +VAESDECLAST inum=5403 isa_set=AVXAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=0 + +VAESDECLAST inum=5404 isa_set=AVXAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=0 + +VAESDECLAST inum=9149 iform_input=VAESDECLAST_YMMu128_YMMu128_YMMu128 isa_set=VAES pattern len=21 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=2 1 1 MOD=3 r r r n n n VL=1 + +VAESDECLAST inum=9150 iform_input=VAESDECLAST_YMMu128_YMMu128_MEMu128 isa_set=VAES pattern len=22 + ipattern: VEXVALID=1 1 1 0 1 1 1 1 1 VEX_PREFIX=1 MAP=2 m m MOD!=3 r r r n n n MODRM() VL=1 + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPANDN inum 4977 -- already fine + SKIPPING VPANDN inum 4978 -- already fine + SKIPPING VPANDN inum 5797 -- already fine + SKIPPING VPANDN inum 5798 -- already fine + SKIPPING VAESKEYGENASSIST inum 5395 -- already fine + SKIPPING VAESKEYGENASSIST inum 5396 -- already fine + REARRANGE needs to juggle: VAESDECLAST inum 5403 + REARRANGE one pattern worked for VAESDECLAST inum 5403 + REARRANGE needs to juggle: VAESDECLAST inum 5404 + REARRANGE one pattern worked for VAESDECLAST inum 5404 + REARRANGE needs to juggle: VAESDECLAST inum 9149 + REARRANGE one pattern worked for VAESDECLAST inum 9149 + REARRANGE needs to juggle: VAESDECLAST inum 9150 + REARRANGE one pattern worked for VAESDECLAST inum 9150 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 9 +Others: +VLDDQU inum=4867 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +VLDDQU inum=4868 isa_set=AVX pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=1 VEX_PREFIX=2 MAP=1 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() + +RORX inum=5983 isa_set=BMI2 pattern len=25 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VEX_PREFIX=2 MAP=3 MODE!=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +RORX inum=5984 isa_set=BMI2 pattern len=26 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VEX_PREFIX=2 MAP=3 REXW=0 MODE=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +RORX inum=5985 isa_set=BMI2 pattern len=26 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VEX_PREFIX=2 MAP=3 MODE!=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +RORX inum=5986 isa_set=BMI2 pattern len=27 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VEX_PREFIX=2 MAP=3 REXW=0 MODE=2 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +RORX inum=5987 isa_set=BMI2 pattern len=26 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VEX_PREFIX=2 MAP=3 REXW=1 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 MODE=2 1 1 MOD=3 r r r n n n UIMM8() + +RORX inum=5988 isa_set=BMI2 pattern len=27 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VEX_PREFIX=2 MAP=3 REXW=1 VL=0 VEXDEST3=0b1 VEXDEST210=0b111 MODE=2 m m MOD!=3 r r r n n n MODRM() UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VLDDQU inum 4867 -- already fine + SKIPPING VLDDQU inum 4868 -- already fine + REARRANGE needs to juggle: RORX inum 5983 + REARRANGE one pattern worked for RORX inum 5983 + REARRANGE needs to juggle: RORX inum 5984 + REARRANGE one pattern worked for RORX inum 5984 + REARRANGE needs to juggle: RORX inum 5985 + REARRANGE one pattern worked for RORX inum 5985 + REARRANGE needs to juggle: RORX inum 5986 + REARRANGE one pattern worked for RORX inum 5986 + REARRANGE needs to juggle: RORX inum 5987 + REARRANGE one pattern worked for RORX inum 5987 + REARRANGE needs to juggle: RORX inum 5988 + REARRANGE one pattern worked for RORX inum 5988 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 12 +Others: +RORX inum=5983 isa_set=BMI2 pattern len=25 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=3 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +RORX inum=5984 isa_set=BMI2 pattern len=26 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=3 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 1 1 MOD=3 r r r n n n UIMM8() + +RORX inum=5985 isa_set=BMI2 pattern len=26 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=3 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +RORX inum=5986 isa_set=BMI2 pattern len=27 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=3 REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 m m MOD!=3 r r r n n n MODRM() UIMM8() + +RORX inum=5987 isa_set=BMI2 pattern len=26 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=3 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 MODE=2 1 1 MOD=3 r r r n n n UIMM8() + +RORX inum=5988 isa_set=BMI2 pattern len=27 + ipattern: VEXVALID=1 1 1 1 1 0 0 0 0 VL=0 VEX_PREFIX=2 MAP=3 REXW=1 VEXDEST3=0b1 VEXDEST210=0b111 MODE=2 m m MOD!=3 r r r n n n MODRM() UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING RORX inum 5983 -- already fine + REARRANGE needs to juggle: RORX inum 5984 + REARRANGE one pattern worked for RORX inum 5984 + SKIPPING RORX inum 5985 -- already fine + REARRANGE needs to juggle: RORX inum 5986 + REARRANGE one pattern worked for RORX inum 5986 + REARRANGE needs to juggle: RORX inum 5987 + REARRANGE one pattern worked for RORX inum 5987 + REARRANGE needs to juggle: RORX inum 5988 + REARRANGE one pattern worked for RORX inum 5988 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 9 +Others: +VPSLLD inum=5005 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLD inum=5006 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPSLLD inum=5641 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLD inum=5642 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +ANDN inum=5923 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5924 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5925 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +ANDN inum=5926 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +ANDN inum=5927 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5928 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSLLD inum 5005 -- already fine + SKIPPING VPSLLD inum 5006 -- already fine + SKIPPING VPSLLD inum 5641 -- already fine + SKIPPING VPSLLD inum 5642 -- already fine + REARRANGE needs to juggle: ANDN inum 5923 + REARRANGE one pattern worked for ANDN inum 5923 + REARRANGE needs to juggle: ANDN inum 5924 + REARRANGE one pattern worked for ANDN inum 5924 + REARRANGE needs to juggle: ANDN inum 5925 + REARRANGE one pattern worked for ANDN inum 5925 + REARRANGE needs to juggle: ANDN inum 5926 + REARRANGE one pattern worked for ANDN inum 5926 + REARRANGE needs to juggle: ANDN inum 5927 + REARRANGE one pattern worked for ANDN inum 5927 + REARRANGE needs to juggle: ANDN inum 5928 + REARRANGE one pattern worked for ANDN inum 5928 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPSLLD inum=5005 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLD inum=5006 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +ANDN inum=5923 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5924 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5925 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 1 1 MOD=3 r r r n n n + +ANDN inum=5926 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +ANDN inum=5927 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5928 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPSLLD inum 5005 -- already fine + SKIPPING VPSLLD inum 5006 -- already fine + REARRANGE needs to juggle: ANDN inum 5923 + REARRANGE one pattern worked for ANDN inum 5923 + REARRANGE needs to juggle: ANDN inum 5924 + REARRANGE one pattern worked for ANDN inum 5924 + REARRANGE needs to juggle: ANDN inum 5925 + REARRANGE one pattern worked for ANDN inum 5925 + REARRANGE needs to juggle: ANDN inum 5926 + REARRANGE one pattern worked for ANDN inum 5926 + REARRANGE needs to juggle: ANDN inum 5927 + REARRANGE one pattern worked for ANDN inum 5927 + REARRANGE needs to juggle: ANDN inum 5928 + REARRANGE one pattern worked for ANDN inum 5928 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 12 +Others: +ANDN inum=5923 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5924 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5925 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 1 1 MOD=3 r r r n n n + +ANDN inum=5926 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +ANDN inum=5927 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +ANDN inum=5928 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 0 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING ANDN inum 5923 -- already fine + REARRANGE needs to juggle: ANDN inum 5924 + REARRANGE one pattern worked for ANDN inum 5924 + SKIPPING ANDN inum 5925 -- already fine + REARRANGE needs to juggle: ANDN inum 5926 + REARRANGE one pattern worked for ANDN inum 5926 + REARRANGE needs to juggle: ANDN inum 5927 + REARRANGE one pattern worked for ANDN inum 5927 + REARRANGE needs to juggle: ANDN inum 5928 + REARRANGE one pattern worked for ANDN inum 5928 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 9 +Others: +VPSLLQ inum=5007 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLQ inum=5008 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPSLLQ inum=5643 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLQ inum=5644 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +BLSR inum=5929 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5930 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5931 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 1 1 MOD=3 0 0 1 n n n + +BLSR inum=5932 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 1 1 MOD=3 0 0 1 n n n + +BLSR inum=5933 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5934 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 1 1 MOD=3 0 0 1 n n n + +BLSMSK inum=5935 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5936 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5937 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 1 1 MOD=3 0 1 0 n n n + +BLSMSK inum=5938 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 1 1 MOD=3 0 1 0 n n n + +BLSMSK inum=5939 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5940 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 1 1 MOD=3 0 1 0 n n n + +BLSI inum=5941 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5942 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5943 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 1 1 MOD=3 0 1 1 n n n + +BLSI inum=5944 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 1 1 MOD=3 0 1 1 n n n + +BLSI inum=5945 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5946 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 1 1 MOD=3 0 1 1 n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSLLQ inum 5007 -- already fine + SKIPPING VPSLLQ inum 5008 -- already fine + SKIPPING VPSLLQ inum 5643 -- already fine + SKIPPING VPSLLQ inum 5644 -- already fine + REARRANGE needs to juggle: BLSR inum 5929 + REARRANGE one pattern worked for BLSR inum 5929 + REARRANGE needs to juggle: BLSR inum 5930 + REARRANGE one pattern worked for BLSR inum 5930 + REARRANGE needs to juggle: BLSR inum 5931 + REARRANGE one pattern worked for BLSR inum 5931 + REARRANGE needs to juggle: BLSR inum 5932 + REARRANGE one pattern worked for BLSR inum 5932 + REARRANGE needs to juggle: BLSR inum 5933 + REARRANGE one pattern worked for BLSR inum 5933 + REARRANGE needs to juggle: BLSR inum 5934 + REARRANGE one pattern worked for BLSR inum 5934 + REARRANGE needs to juggle: BLSMSK inum 5935 + REARRANGE one pattern worked for BLSMSK inum 5935 + REARRANGE needs to juggle: BLSMSK inum 5936 + REARRANGE one pattern worked for BLSMSK inum 5936 + REARRANGE needs to juggle: BLSMSK inum 5937 + REARRANGE one pattern worked for BLSMSK inum 5937 + REARRANGE needs to juggle: BLSMSK inum 5938 + REARRANGE one pattern worked for BLSMSK inum 5938 + REARRANGE needs to juggle: BLSMSK inum 5939 + REARRANGE one pattern worked for BLSMSK inum 5939 + REARRANGE needs to juggle: BLSMSK inum 5940 + REARRANGE one pattern worked for BLSMSK inum 5940 + REARRANGE needs to juggle: BLSI inum 5941 + REARRANGE one pattern worked for BLSI inum 5941 + REARRANGE needs to juggle: BLSI inum 5942 + REARRANGE one pattern worked for BLSI inum 5942 + REARRANGE needs to juggle: BLSI inum 5943 + REARRANGE one pattern worked for BLSI inum 5943 + REARRANGE needs to juggle: BLSI inum 5944 + REARRANGE one pattern worked for BLSI inum 5944 + REARRANGE needs to juggle: BLSI inum 5945 + REARRANGE one pattern worked for BLSI inum 5945 + REARRANGE needs to juggle: BLSI inum 5946 + REARRANGE one pattern worked for BLSI inum 5946 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPSLLQ inum=5007 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSLLQ inum=5008 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +BLSR inum=5929 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5930 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5931 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 1 1 MOD=3 0 0 1 n n n + +BLSR inum=5932 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 1 1 MOD=3 0 0 1 n n n + +BLSR inum=5933 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5934 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 1 1 MOD=3 0 0 1 n n n + +BLSMSK inum=5935 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5936 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5937 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 1 1 MOD=3 0 1 0 n n n + +BLSMSK inum=5938 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 1 1 MOD=3 0 1 0 n n n + +BLSMSK inum=5939 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5940 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 1 1 MOD=3 0 1 0 n n n + +BLSI inum=5941 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5942 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5943 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 1 1 MOD=3 0 1 1 n n n + +BLSI inum=5944 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 1 1 MOD=3 0 1 1 n n n + +BLSI inum=5945 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5946 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 1 1 MOD=3 0 1 1 n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPSLLQ inum 5007 -- already fine + SKIPPING VPSLLQ inum 5008 -- already fine + REARRANGE needs to juggle: BLSR inum 5929 + REARRANGE one pattern worked for BLSR inum 5929 + REARRANGE needs to juggle: BLSR inum 5930 + REARRANGE one pattern worked for BLSR inum 5930 + REARRANGE needs to juggle: BLSR inum 5931 + REARRANGE one pattern worked for BLSR inum 5931 + REARRANGE needs to juggle: BLSR inum 5932 + REARRANGE one pattern worked for BLSR inum 5932 + REARRANGE needs to juggle: BLSR inum 5933 + REARRANGE one pattern worked for BLSR inum 5933 + REARRANGE needs to juggle: BLSR inum 5934 + REARRANGE one pattern worked for BLSR inum 5934 + REARRANGE needs to juggle: BLSMSK inum 5935 + REARRANGE one pattern worked for BLSMSK inum 5935 + REARRANGE needs to juggle: BLSMSK inum 5936 + REARRANGE one pattern worked for BLSMSK inum 5936 + REARRANGE needs to juggle: BLSMSK inum 5937 + REARRANGE one pattern worked for BLSMSK inum 5937 + REARRANGE needs to juggle: BLSMSK inum 5938 + REARRANGE one pattern worked for BLSMSK inum 5938 + REARRANGE needs to juggle: BLSMSK inum 5939 + REARRANGE one pattern worked for BLSMSK inum 5939 + REARRANGE needs to juggle: BLSMSK inum 5940 + REARRANGE one pattern worked for BLSMSK inum 5940 + REARRANGE needs to juggle: BLSI inum 5941 + REARRANGE one pattern worked for BLSI inum 5941 + REARRANGE needs to juggle: BLSI inum 5942 + REARRANGE one pattern worked for BLSI inum 5942 + REARRANGE needs to juggle: BLSI inum 5943 + REARRANGE one pattern worked for BLSI inum 5943 + REARRANGE needs to juggle: BLSI inum 5944 + REARRANGE one pattern worked for BLSI inum 5944 + REARRANGE needs to juggle: BLSI inum 5945 + REARRANGE one pattern worked for BLSI inum 5945 + REARRANGE needs to juggle: BLSI inum 5946 + REARRANGE one pattern worked for BLSI inum 5946 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 12 +Others: +BLSR inum=5929 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5930 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5931 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 1 1 MOD=3 0 0 1 n n n + +BLSR inum=5932 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 1 1 MOD=3 0 0 1 n n n + +BLSR inum=5933 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 m m MOD!=3 0 0 1 n n n MODRM() + +BLSR inum=5934 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 1 1 MOD=3 0 0 1 n n n + +BLSMSK inum=5935 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5936 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5937 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 1 1 MOD=3 0 1 0 n n n + +BLSMSK inum=5938 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 1 1 MOD=3 0 1 0 n n n + +BLSMSK inum=5939 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 m m MOD!=3 0 1 0 n n n MODRM() + +BLSMSK inum=5940 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 1 1 MOD=3 0 1 0 n n n + +BLSI inum=5941 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5942 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5943 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 1 1 MOD=3 0 1 1 n n n + +BLSI inum=5944 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 1 1 MOD=3 0 1 1 n n n + +BLSI inum=5945 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 m m MOD!=3 0 1 1 n n n MODRM() + +BLSI inum=5946 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 0 1 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 1 1 MOD=3 0 1 1 n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING BLSR inum 5929 -- already fine + REARRANGE needs to juggle: BLSR inum 5930 + REARRANGE one pattern worked for BLSR inum 5930 + SKIPPING BLSR inum 5931 -- already fine + REARRANGE needs to juggle: BLSR inum 5932 + REARRANGE one pattern worked for BLSR inum 5932 + REARRANGE needs to juggle: BLSR inum 5933 + REARRANGE one pattern worked for BLSR inum 5933 + REARRANGE needs to juggle: BLSR inum 5934 + REARRANGE one pattern worked for BLSR inum 5934 + SKIPPING BLSMSK inum 5935 -- already fine + REARRANGE needs to juggle: BLSMSK inum 5936 + REARRANGE one pattern worked for BLSMSK inum 5936 + SKIPPING BLSMSK inum 5937 -- already fine + REARRANGE needs to juggle: BLSMSK inum 5938 + REARRANGE one pattern worked for BLSMSK inum 5938 + REARRANGE needs to juggle: BLSMSK inum 5939 + REARRANGE one pattern worked for BLSMSK inum 5939 + REARRANGE needs to juggle: BLSMSK inum 5940 + REARRANGE one pattern worked for BLSMSK inum 5940 + SKIPPING BLSI inum 5941 -- already fine + REARRANGE needs to juggle: BLSI inum 5942 + REARRANGE one pattern worked for BLSI inum 5942 + SKIPPING BLSI inum 5943 -- already fine + REARRANGE needs to juggle: BLSI inum 5944 + REARRANGE one pattern worked for BLSI inum 5944 + REARRANGE needs to juggle: BLSI inum 5945 + REARRANGE one pattern worked for BLSI inum 5945 + REARRANGE needs to juggle: BLSI inum 5946 + REARRANGE one pattern worked for BLSI inum 5946 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 9 +Others: +VPMADDWD inum=5239 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPMADDWD inum=5240 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPMADDWD inum=5703 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPMADDWD inum=5704 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +PDEP inum=5911 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=2 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5912 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=2 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5913 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=2 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +PDEP inum=5914 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=2 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +PDEP inum=5915 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=2 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5916 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=2 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +PEXT inum=5917 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=3 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5918 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=3 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5919 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=3 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +PEXT inum=5920 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=3 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +PEXT inum=5921 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=3 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5922 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=3 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +BZHI inum=5947 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5948 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5949 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +BZHI inum=5950 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +BZHI inum=5951 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5952 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPMADDWD inum 5239 -- already fine + SKIPPING VPMADDWD inum 5240 -- already fine + SKIPPING VPMADDWD inum 5703 -- already fine + SKIPPING VPMADDWD inum 5704 -- already fine + REARRANGE needs to juggle: PDEP inum 5911 + REARRANGE one pattern worked for PDEP inum 5911 + REARRANGE needs to juggle: PDEP inum 5912 + REARRANGE one pattern worked for PDEP inum 5912 + REARRANGE needs to juggle: PDEP inum 5913 + REARRANGE one pattern worked for PDEP inum 5913 + REARRANGE needs to juggle: PDEP inum 5914 + REARRANGE one pattern worked for PDEP inum 5914 + REARRANGE needs to juggle: PDEP inum 5915 + REARRANGE one pattern worked for PDEP inum 5915 + REARRANGE needs to juggle: PDEP inum 5916 + REARRANGE one pattern worked for PDEP inum 5916 + REARRANGE needs to juggle: PEXT inum 5917 + REARRANGE one pattern worked for PEXT inum 5917 + REARRANGE needs to juggle: PEXT inum 5918 + REARRANGE one pattern worked for PEXT inum 5918 + REARRANGE needs to juggle: PEXT inum 5919 + REARRANGE one pattern worked for PEXT inum 5919 + REARRANGE needs to juggle: PEXT inum 5920 + REARRANGE one pattern worked for PEXT inum 5920 + REARRANGE needs to juggle: PEXT inum 5921 + REARRANGE one pattern worked for PEXT inum 5921 + REARRANGE needs to juggle: PEXT inum 5922 + REARRANGE one pattern worked for PEXT inum 5922 + REARRANGE needs to juggle: BZHI inum 5947 + REARRANGE one pattern worked for BZHI inum 5947 + REARRANGE needs to juggle: BZHI inum 5948 + REARRANGE one pattern worked for BZHI inum 5948 + REARRANGE needs to juggle: BZHI inum 5949 + REARRANGE one pattern worked for BZHI inum 5949 + REARRANGE needs to juggle: BZHI inum 5950 + REARRANGE one pattern worked for BZHI inum 5950 + REARRANGE needs to juggle: BZHI inum 5951 + REARRANGE one pattern worked for BZHI inum 5951 + REARRANGE needs to juggle: BZHI inum 5952 + REARRANGE one pattern worked for BZHI inum 5952 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 10 +Others: +VPMADDWD inum=5239 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPMADDWD inum=5240 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +PDEP inum=5911 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=2 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5912 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=2 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5913 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=2 MODE!=2 1 1 MOD=3 r r r n n n + +PDEP inum=5914 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=2 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +PDEP inum=5915 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=2 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5916 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=2 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +PEXT inum=5917 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=3 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5918 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=3 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5919 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=3 MODE!=2 1 1 MOD=3 r r r n n n + +PEXT inum=5920 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=3 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +PEXT inum=5921 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=3 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5922 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=3 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +BZHI inum=5947 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5948 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5949 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=0 MODE!=2 1 1 MOD=3 r r r n n n + +BZHI inum=5950 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +BZHI inum=5951 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5952 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 MAP=2 VEX_PREFIX=0 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using VEX_PREFIX + SKIPPING VPMADDWD inum 5239 -- already fine + SKIPPING VPMADDWD inum 5240 -- already fine + REARRANGE needs to juggle: PDEP inum 5911 + REARRANGE one pattern worked for PDEP inum 5911 + REARRANGE needs to juggle: PDEP inum 5912 + REARRANGE one pattern worked for PDEP inum 5912 + REARRANGE needs to juggle: PDEP inum 5913 + REARRANGE one pattern worked for PDEP inum 5913 + REARRANGE needs to juggle: PDEP inum 5914 + REARRANGE one pattern worked for PDEP inum 5914 + REARRANGE needs to juggle: PDEP inum 5915 + REARRANGE one pattern worked for PDEP inum 5915 + REARRANGE needs to juggle: PDEP inum 5916 + REARRANGE one pattern worked for PDEP inum 5916 + REARRANGE needs to juggle: PEXT inum 5917 + REARRANGE one pattern worked for PEXT inum 5917 + REARRANGE needs to juggle: PEXT inum 5918 + REARRANGE one pattern worked for PEXT inum 5918 + REARRANGE needs to juggle: PEXT inum 5919 + REARRANGE one pattern worked for PEXT inum 5919 + REARRANGE needs to juggle: PEXT inum 5920 + REARRANGE one pattern worked for PEXT inum 5920 + REARRANGE needs to juggle: PEXT inum 5921 + REARRANGE one pattern worked for PEXT inum 5921 + REARRANGE needs to juggle: PEXT inum 5922 + REARRANGE one pattern worked for PEXT inum 5922 + REARRANGE needs to juggle: BZHI inum 5947 + REARRANGE one pattern worked for BZHI inum 5947 + REARRANGE needs to juggle: BZHI inum 5948 + REARRANGE one pattern worked for BZHI inum 5948 + REARRANGE needs to juggle: BZHI inum 5949 + REARRANGE one pattern worked for BZHI inum 5949 + REARRANGE needs to juggle: BZHI inum 5950 + REARRANGE one pattern worked for BZHI inum 5950 + REARRANGE needs to juggle: BZHI inum 5951 + REARRANGE one pattern worked for BZHI inum 5951 + REARRANGE needs to juggle: BZHI inum 5952 + REARRANGE one pattern worked for BZHI inum 5952 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 10 +FUNKY SPOT: bitpos 12 +Others: +PDEP inum=5911 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=2 MAP=2 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5912 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=2 MAP=2 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5913 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=2 MAP=2 MODE!=2 1 1 MOD=3 r r r n n n + +PDEP inum=5914 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=2 MAP=2 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +PDEP inum=5915 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=2 MAP=2 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PDEP inum=5916 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=2 MAP=2 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING PDEP inum 5911 -- already fine + REARRANGE needs to juggle: PDEP inum 5912 + REARRANGE one pattern worked for PDEP inum 5912 + SKIPPING PDEP inum 5913 -- already fine + REARRANGE needs to juggle: PDEP inum 5914 + REARRANGE one pattern worked for PDEP inum 5914 + REARRANGE needs to juggle: PDEP inum 5915 + REARRANGE one pattern worked for PDEP inum 5915 + REARRANGE needs to juggle: PDEP inum 5916 + REARRANGE one pattern worked for PDEP inum 5916 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 12 +Others: +PEXT inum=5917 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=3 MAP=2 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5918 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=3 MAP=2 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5919 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=3 MAP=2 MODE!=2 1 1 MOD=3 r r r n n n + +PEXT inum=5920 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=3 MAP=2 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +PEXT inum=5921 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=3 MAP=2 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +PEXT inum=5922 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=3 MAP=2 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING PEXT inum 5917 -- already fine + REARRANGE needs to juggle: PEXT inum 5918 + REARRANGE one pattern worked for PEXT inum 5918 + SKIPPING PEXT inum 5919 -- already fine + REARRANGE needs to juggle: PEXT inum 5920 + REARRANGE one pattern worked for PEXT inum 5920 + REARRANGE needs to juggle: PEXT inum 5921 + REARRANGE one pattern worked for PEXT inum 5921 + REARRANGE needs to juggle: PEXT inum 5922 + REARRANGE one pattern worked for PEXT inum 5922 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 12 +Others: +BZHI inum=5947 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5948 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5949 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=0 MAP=2 MODE!=2 1 1 MOD=3 r r r n n n + +BZHI inum=5950 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +BZHI inum=5951 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +BZHI inum=5952 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 0 1 VL=0 VEX_PREFIX=0 MAP=2 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING BZHI inum 5947 -- already fine + REARRANGE needs to juggle: BZHI inum 5948 + REARRANGE one pattern worked for BZHI inum 5948 + SKIPPING BZHI inum 5949 -- already fine + REARRANGE needs to juggle: BZHI inum 5950 + REARRANGE one pattern worked for BZHI inum 5950 + REARRANGE needs to juggle: BZHI inum 5951 + REARRANGE one pattern worked for BZHI inum 5951 + REARRANGE needs to juggle: BZHI inum 5952 + REARRANGE one pattern worked for BZHI inum 5952 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 9 +Others: +VPSADBW inum=5081 isa_set=AVX pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSADBW inum=5082 isa_set=AVX pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +VPSADBW inum=5745 isa_set=AVX2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n MODRM() + +VPSADBW inum=5746 isa_set=AVX2 pattern len=21 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=1 VEX_PREFIX=1 MAP=1 1 1 MOD=3 r r r n n n + +MULX inum=5977 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VEX_PREFIX=2 MAP=2 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +MULX inum=5978 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VEX_PREFIX=2 MAP=2 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +MULX inum=5979 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VEX_PREFIX=2 MAP=2 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +MULX inum=5980 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VEX_PREFIX=2 MAP=2 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +MULX inum=5981 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VEX_PREFIX=2 MAP=2 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +MULX inum=5982 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VEX_PREFIX=2 MAP=2 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +Ones: +Zeros: +REARRANGE ATTEMPT using VL + SKIPPING VPSADBW inum 5081 -- already fine + SKIPPING VPSADBW inum 5082 -- already fine + SKIPPING VPSADBW inum 5745 -- already fine + SKIPPING VPSADBW inum 5746 -- already fine + REARRANGE needs to juggle: MULX inum 5977 + REARRANGE one pattern worked for MULX inum 5977 + REARRANGE needs to juggle: MULX inum 5978 + REARRANGE one pattern worked for MULX inum 5978 + REARRANGE needs to juggle: MULX inum 5979 + REARRANGE one pattern worked for MULX inum 5979 + REARRANGE needs to juggle: MULX inum 5980 + REARRANGE one pattern worked for MULX inum 5980 + REARRANGE needs to juggle: MULX inum 5981 + REARRANGE one pattern worked for MULX inum 5981 + REARRANGE needs to juggle: MULX inum 5982 + REARRANGE one pattern worked for MULX inum 5982 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 9 +FUNKY SPOT: bitpos 12 +Others: +MULX inum=5977 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=2 MAP=2 MODE!=2 1 1 MOD=3 r r r n n n + +MULX inum=5978 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=2 MAP=2 REXW=0 MODE=2 1 1 MOD=3 r r r n n n + +MULX inum=5979 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=2 MAP=2 MODE!=2 m m MOD!=3 r r r n n n MODRM() + +MULX inum=5980 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=2 MAP=2 REXW=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +MULX inum=5981 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=2 MAP=2 REXW=1 MODE=2 1 1 MOD=3 r r r n n n + +MULX inum=5982 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 0 VL=0 VEX_PREFIX=2 MAP=2 REXW=1 MODE=2 m m MOD!=3 r r r n n n MODRM() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING MULX inum 5977 -- already fine + REARRANGE needs to juggle: MULX inum 5978 + REARRANGE one pattern worked for MULX inum 5978 + SKIPPING MULX inum 5979 -- already fine + REARRANGE needs to juggle: MULX inum 5980 + REARRANGE one pattern worked for MULX inum 5980 + REARRANGE needs to juggle: MULX inum 5981 + REARRANGE one pattern worked for MULX inum 5981 + REARRANGE needs to juggle: MULX inum 5982 + REARRANGE one pattern worked for MULX inum 5982 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 12 +FUNKY SPOT: bitpos 11 +Others: +BEXTR inum=5953 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +BEXTR inum=5954 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +BEXTR inum=5955 isa_set=BMI1 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=0 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +BEXTR inum=5956 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=0 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +BEXTR inum=5957 isa_set=BMI1 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +BEXTR inum=5958 isa_set=BMI1 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=0 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING BEXTR inum 5953 -- already fine + REARRANGE needs to juggle: BEXTR inum 5954 + REARRANGE one pattern worked for BEXTR inum 5954 + SKIPPING BEXTR inum 5955 -- already fine + REARRANGE needs to juggle: BEXTR inum 5956 + REARRANGE one pattern worked for BEXTR inum 5956 + REARRANGE needs to juggle: BEXTR inum 5957 + REARRANGE one pattern worked for BEXTR inum 5957 + REARRANGE needs to juggle: BEXTR inum 5958 + REARRANGE one pattern worked for BEXTR inum 5958 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +SHLX inum=5959 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=1 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +SHLX inum=5960 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=1 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +SHLX inum=5961 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=1 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +SHLX inum=5962 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=1 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +SHLX inum=5963 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=1 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +SHLX inum=5964 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=1 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING SHLX inum 5959 -- already fine + REARRANGE needs to juggle: SHLX inum 5960 + REARRANGE one pattern worked for SHLX inum 5960 + SKIPPING SHLX inum 5961 -- already fine + REARRANGE needs to juggle: SHLX inum 5962 + REARRANGE one pattern worked for SHLX inum 5962 + REARRANGE needs to juggle: SHLX inum 5963 + REARRANGE one pattern worked for SHLX inum 5963 + REARRANGE needs to juggle: SHLX inum 5964 + REARRANGE one pattern worked for SHLX inum 5964 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +SARX inum=5965 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=3 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +SARX inum=5966 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=3 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +SARX inum=5967 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=3 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +SARX inum=5968 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=3 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +SARX inum=5969 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=3 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +SARX inum=5970 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=3 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING SARX inum 5965 -- already fine + REARRANGE needs to juggle: SARX inum 5966 + REARRANGE one pattern worked for SARX inum 5966 + SKIPPING SARX inum 5967 -- already fine + REARRANGE needs to juggle: SARX inum 5968 + REARRANGE one pattern worked for SARX inum 5968 + REARRANGE needs to juggle: SARX inum 5969 + REARRANGE one pattern worked for SARX inum 5969 + REARRANGE needs to juggle: SARX inum 5970 + REARRANGE one pattern worked for SARX inum 5970 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 11 +Others: +SHRX inum=5971 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=2 MODE!=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +SHRX inum=5972 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=2 REXW=0 MODE=2 VL=0 m m MOD!=3 r r r n n n MODRM() + +SHRX inum=5973 isa_set=BMI2 pattern len=22 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=2 MODE!=2 VL=0 1 1 MOD=3 r r r n n n + +SHRX inum=5974 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=2 REXW=0 MODE=2 VL=0 1 1 MOD=3 r r r n n n + +SHRX inum=5975 isa_set=BMI2 pattern len=24 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=2 REXW=1 VL=0 MODE=2 m m MOD!=3 r r r n n n MODRM() + +SHRX inum=5976 isa_set=BMI2 pattern len=23 + ipattern: VEXVALID=1 1 1 1 1 0 1 1 1 MAP=2 VEX_PREFIX=2 REXW=1 VL=0 MODE=2 1 1 MOD=3 r r r n n n + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING SHRX inum 5971 -- already fine + REARRANGE needs to juggle: SHRX inum 5972 + REARRANGE one pattern worked for SHRX inum 5972 + SKIPPING SHRX inum 5973 -- already fine + REARRANGE needs to juggle: SHRX inum 5974 + REARRANGE one pattern worked for SHRX inum 5974 + REARRANGE needs to juggle: SHRX inum 5975 + REARRANGE one pattern worked for SHRX inum 5975 + REARRANGE needs to juggle: SHRX inum 5976 + REARRANGE one pattern worked for SHRX inum 5976 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 11 +FUNKY SPOT: bitpos 22 +Others: +VPEXTRD inum=8054 iform_input=VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=29 + ipattern: VEXVALID=2 0 0 0 1 0 1 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 UIMM8() + +VPEXTRD inum=8055 iform_input=VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=30 + ipattern: VEXVALID=2 0 0 0 1 0 1 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 UIMM8() + +VPEXTRQ inum=8058 iform_input=VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=30 + ipattern: VEXVALID=2 0 0 0 1 0 1 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 BCRC=0 r r r n n n VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VPEXTRD inum 8054 -- already fine + SKIPPING VPEXTRD inum 8055 -- already fine + REARRANGE needs to juggle: VPEXTRQ inum 8058 + REARRANGE one pattern worked for VPEXTRQ inum 8058 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VPEXTRD inum=8056 iform_input=VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=32 + ipattern: VEXVALID=2 0 0 0 1 0 1 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() + +VPEXTRD inum=8057 iform_input=VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=33 + ipattern: VEXVALID=2 0 0 0 1 0 1 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() + +VPEXTRQ inum=8059 iform_input=VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=33 + ipattern: VEXVALID=2 0 0 0 1 0 1 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VPEXTRD inum 8056 -- already fine + SKIPPING VPEXTRD inum 8057 -- already fine + REARRANGE needs to juggle: VPEXTRQ inum 8059 + REARRANGE one pattern worked for VPEXTRQ inum 8059 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VPINSRD inum=8074 iform_input=VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=26 + ipattern: VEXVALID=2 0 0 1 0 0 0 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE!=2 ZEROING=0 MASK=0 UIMM8() + +VPINSRD inum=8075 iform_input=VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=27 + ipattern: VEXVALID=2 0 0 1 0 0 0 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE=2 REXW=0 ZEROING=0 MASK=0 UIMM8() + +VPINSRQ inum=8078 iform_input=VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=27 + ipattern: VEXVALID=2 0 0 1 0 0 0 1 0 VEX_PREFIX=1 MAP=3 1 1 MOD=3 BCRC=0 r r r n n n VL=0 REXW=1 MODE=2 ZEROING=0 MASK=0 UIMM8() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VPINSRD inum 8074 -- already fine + SKIPPING VPINSRD inum 8075 -- already fine + REARRANGE needs to juggle: VPINSRQ inum 8078 + REARRANGE one pattern worked for VPINSRQ inum 8078 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VPINSRD inum=8076 iform_input=VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=29 + ipattern: VEXVALID=2 0 0 1 0 0 0 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE!=2 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() + +VPINSRD inum=8077 iform_input=VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 0 0 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE=2 REXW=0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() + +VPINSRQ inum=8079 iform_input=VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 isa_set=AVX512DQ_128N pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 0 0 1 0 VEX_PREFIX=1 MAP=3 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 REXW=1 MODE=2 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VPINSRD inum 8076 -- already fine + SKIPPING VPINSRD inum 8077 -- already fine + REARRANGE needs to juggle: VPINSRQ inum 8079 + REARRANGE one pattern worked for VPINSRQ inum 8079 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VCVTSI2SH inum=9366 iform_input=VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=26 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=0 MODE=2 ZEROING=0 MASK=0 + +VCVTSI2SH inum=9369 iform_input=VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=25 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() MODE!=2 ZEROING=0 MASK=0 + +VCVTSI2SH inum=9372 iform_input=VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=26 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=1 MODE=2 ZEROING=0 MASK=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSI2SH inum 9366 -- already fine + REARRANGE needs to juggle: VCVTSI2SH inum 9369 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSI2SH inum 9366 + REARRANGE one pattern worked for VCVTSI2SH inum 9366 + SKIPPING VCVTSI2SH inum 9369 -- already fine + REARRANGE needs to juggle: VCVTSI2SH inum 9372 + REARRANGE one pattern worked for VCVTSI2SH inum 9372 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VCVTSI2SH inum=9367 iform_input=VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=27 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=0 MODE=2 ZEROING=0 MASK=0 + +VCVTSI2SH inum=9370 iform_input=VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=26 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() MODE!=2 ZEROING=0 MASK=0 + +VCVTSI2SH inum=9373 iform_input=VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=27 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=1 MODE=2 ZEROING=0 MASK=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSI2SH inum 9367 -- already fine + REARRANGE needs to juggle: VCVTSI2SH inum 9370 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSI2SH inum 9367 + REARRANGE one pattern worked for VCVTSI2SH inum 9367 + SKIPPING VCVTSI2SH inum 9370 -- already fine + REARRANGE needs to juggle: VCVTSI2SH inum 9373 + REARRANGE one pattern worked for VCVTSI2SH inum 9373 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 23 +Others: +VCVTSI2SH inum=9368 iform_input=VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=0 MODE=2 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() + +VCVTSI2SH inum=9371 iform_input=VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=28 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() MODE!=2 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() + +VCVTSI2SH inum=9374 iform_input=VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 0 1 0 1 0 1 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=1 MODE=2 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSI2SH inum 9368 -- already fine + REARRANGE needs to juggle: VCVTSI2SH inum 9371 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSI2SH inum 9368 + REARRANGE one pattern worked for VCVTSI2SH inum 9368 + SKIPPING VCVTSI2SH inum 9371 -- already fine + REARRANGE needs to juggle: VCVTSI2SH inum 9374 + REARRANGE one pattern worked for VCVTSI2SH inum 9374 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VCVTTSH2SI inum=9420 iform_input=VCVTTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2SI inum=9423 iform_input=VCVTTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2SI inum=9426 iform_input=VCVTTSH2SI_GPR64i64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTTSH2SI inum 9420 -- already fine + REARRANGE needs to juggle: VCVTTSH2SI inum 9423 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTTSH2SI inum 9420 + REARRANGE one pattern worked for VCVTTSH2SI inum 9420 + SKIPPING VCVTTSH2SI inum 9423 -- already fine + REARRANGE needs to juggle: VCVTTSH2SI inum 9426 + REARRANGE one pattern worked for VCVTTSH2SI inum 9426 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VCVTTSH2SI inum=9421 iform_input=VCVTTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() SAE() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2SI inum=9424 iform_input=VCVTTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() SAE() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2SI inum=9427 iform_input=VCVTTSH2SI_GPR64i64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() SAE() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTTSH2SI inum 9421 -- already fine + REARRANGE needs to juggle: VCVTTSH2SI inum 9424 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTTSH2SI inum 9421 + REARRANGE one pattern worked for VCVTTSH2SI inum 9421 + SKIPPING VCVTTSH2SI inum 9424 -- already fine + REARRANGE needs to juggle: VCVTTSH2SI inum 9427 + REARRANGE one pattern worked for VCVTTSH2SI inum 9427 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 23 +Others: +VCVTTSH2SI inum=9422 iform_input=VCVTTSH2SI_GPR32i32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTTSH2SI inum=9425 iform_input=VCVTTSH2SI_GPR32i32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=32 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTTSH2SI inum=9428 iform_input=VCVTTSH2SI_GPR64i64_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTTSH2SI inum 9422 -- already fine + REARRANGE needs to juggle: VCVTTSH2SI inum 9425 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTTSH2SI inum 9422 + REARRANGE one pattern worked for VCVTTSH2SI inum 9422 + SKIPPING VCVTTSH2SI inum 9425 -- already fine + REARRANGE needs to juggle: VCVTTSH2SI inum 9428 + REARRANGE one pattern worked for VCVTTSH2SI inum 9428 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VCVTSH2SI inum=9345 iform_input=VCVTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2SI inum=9348 iform_input=VCVTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2SI inum=9351 iform_input=VCVTSH2SI_GPR64i64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSH2SI inum 9345 -- already fine + REARRANGE needs to juggle: VCVTSH2SI inum 9348 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSH2SI inum 9345 + REARRANGE one pattern worked for VCVTSH2SI inum 9345 + SKIPPING VCVTSH2SI inum 9348 -- already fine + REARRANGE needs to juggle: VCVTSH2SI inum 9351 + REARRANGE one pattern worked for VCVTSH2SI inum 9351 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VCVTSH2SI inum=9346 iform_input=VCVTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2SI inum=9349 iform_input=VCVTSH2SI_GPR32i32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2SI inum=9352 iform_input=VCVTSH2SI_GPR64i64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSH2SI inum 9346 -- already fine + REARRANGE needs to juggle: VCVTSH2SI inum 9349 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSH2SI inum 9346 + REARRANGE one pattern worked for VCVTSH2SI inum 9346 + SKIPPING VCVTSH2SI inum 9349 -- already fine + REARRANGE needs to juggle: VCVTSH2SI inum 9352 + REARRANGE one pattern worked for VCVTSH2SI inum 9352 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 23 +Others: +VCVTSH2SI inum=9347 iform_input=VCVTSH2SI_GPR32i32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTSH2SI inum=9350 iform_input=VCVTSH2SI_GPR32i32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=32 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTSH2SI inum=9353 iform_input=VCVTSH2SI_GPR64i64_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 0 1 0 1 1 0 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSH2SI inum 9347 -- already fine + REARRANGE needs to juggle: VCVTSH2SI inum 9350 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSH2SI inum 9347 + REARRANGE one pattern worked for VCVTSH2SI inum 9347 + SKIPPING VCVTSH2SI inum 9350 -- already fine + REARRANGE needs to juggle: VCVTSH2SI inum 9353 + REARRANGE one pattern worked for VCVTSH2SI inum 9353 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VMOVD inum=6614 iform_input=VMOVD_XMMu32_GPR32u32_AVX512 isa_set=AVX512F_128N pattern len=28 + ipattern: VEXVALID=2 0 1 1 0 1 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 + +VMOVD inum=6615 iform_input=VMOVD_XMMu32_GPR32u32_AVX512 isa_set=AVX512F_128N pattern len=29 + ipattern: VEXVALID=2 0 1 1 0 1 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 + +VMOVQ inum=6654 iform_input=VMOVQ_XMMu64_GPR64u64_AVX512 isa_set=AVX512F_128N pattern len=29 + ipattern: VEXVALID=2 0 1 1 0 1 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 BCRC=0 r r r n n n VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VMOVD inum 6614 -- already fine + SKIPPING VMOVD inum 6615 -- already fine + REARRANGE needs to juggle: VMOVQ inum 6654 + REARRANGE one pattern worked for VMOVQ inum 6654 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VMOVD inum=6616 iform_input=VMOVD_XMMu32_MEMu32_AVX512 isa_set=AVX512F_128N pattern len=31 + ipattern: VEXVALID=2 0 1 1 0 1 1 1 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() + +VMOVD inum=6617 iform_input=VMOVD_XMMu32_MEMu32_AVX512 isa_set=AVX512F_128N pattern len=32 + ipattern: VEXVALID=2 0 1 1 0 1 1 1 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() + +VMOVQ inum=6655 iform_input=VMOVQ_XMMu64_MEMu64_AVX512 isa_set=AVX512F_128N pattern len=32 + ipattern: VEXVALID=2 0 1 1 0 1 1 1 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VMOVD inum 6616 -- already fine + SKIPPING VMOVD inum 6617 -- already fine + REARRANGE needs to juggle: VMOVQ inum 6655 + REARRANGE one pattern worked for VMOVQ inum 6655 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VCVTTSH2USI inum=9429 iform_input=VCVTTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2USI inum=9432 iform_input=VCVTTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2USI inum=9435 iform_input=VCVTTSH2USI_GPR64u64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTTSH2USI inum 9429 -- already fine + REARRANGE needs to juggle: VCVTTSH2USI inum 9432 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTTSH2USI inum 9429 + REARRANGE one pattern worked for VCVTTSH2USI inum 9429 + SKIPPING VCVTTSH2USI inum 9432 -- already fine + REARRANGE needs to juggle: VCVTTSH2USI inum 9435 + REARRANGE one pattern worked for VCVTTSH2USI inum 9435 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VCVTTSH2USI inum=9430 iform_input=VCVTTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() SAE() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2USI inum=9433 iform_input=VCVTTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() SAE() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTTSH2USI inum=9436 iform_input=VCVTTSH2USI_GPR64u64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() SAE() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTTSH2USI inum 9430 -- already fine + REARRANGE needs to juggle: VCVTTSH2USI inum 9433 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTTSH2USI inum 9430 + REARRANGE one pattern worked for VCVTTSH2USI inum 9430 + SKIPPING VCVTTSH2USI inum 9433 -- already fine + REARRANGE needs to juggle: VCVTTSH2USI inum 9436 + REARRANGE one pattern worked for VCVTTSH2USI inum 9436 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 23 +Others: +VCVTTSH2USI inum=9431 iform_input=VCVTTSH2USI_GPR32u32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTTSH2USI inum=9434 iform_input=VCVTTSH2USI_GPR32u32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=32 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTTSH2USI inum=9437 iform_input=VCVTTSH2USI_GPR64u64_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 0 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTTSH2USI inum 9431 -- already fine + REARRANGE needs to juggle: VCVTTSH2USI inum 9434 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTTSH2USI inum 9431 + REARRANGE one pattern worked for VCVTTSH2USI inum 9431 + SKIPPING VCVTTSH2USI inum 9434 -- already fine + REARRANGE needs to juggle: VCVTTSH2USI inum 9437 + REARRANGE one pattern worked for VCVTTSH2USI inum 9437 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VCVTSH2USI inum=9357 iform_input=VCVTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2USI inum=9360 iform_input=VCVTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2USI inum=9363 iform_input=VCVTSH2USI_GPR64u64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSH2USI inum 9357 -- already fine + REARRANGE needs to juggle: VCVTSH2USI inum 9360 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSH2USI inum 9357 + REARRANGE one pattern worked for VCVTSH2USI inum 9357 + SKIPPING VCVTSH2USI inum 9360 -- already fine + REARRANGE needs to juggle: VCVTSH2USI inum 9363 + REARRANGE one pattern worked for VCVTSH2USI inum 9363 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VCVTSH2USI inum=9358 iform_input=VCVTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2USI inum=9361 iform_input=VCVTSH2USI_GPR32u32_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=30 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +VCVTSH2USI inum=9364 iform_input=VCVTSH2USI_GPR64u64_XMMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=31 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSH2USI inum 9358 -- already fine + REARRANGE needs to juggle: VCVTSH2USI inum 9361 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSH2USI inum 9358 + REARRANGE one pattern worked for VCVTSH2USI inum 9358 + SKIPPING VCVTSH2USI inum 9361 -- already fine + REARRANGE needs to juggle: VCVTSH2USI inum 9364 + REARRANGE one pattern worked for VCVTSH2USI inum 9364 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 23 +Others: +VCVTSH2USI inum=9359 iform_input=VCVTSH2USI_GPR32u32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=0 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTSH2USI inum=9362 iform_input=VCVTSH2USI_GPR32u32_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=32 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +VCVTSH2USI inum=9365 iform_input=VCVTSH2USI_GPR64u64_MEMf16_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=33 + ipattern: VEXVALID=2 0 1 1 1 1 0 0 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() REXRR=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTSH2USI inum 9359 -- already fine + REARRANGE needs to juggle: VCVTSH2USI inum 9362 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTSH2USI inum 9359 + REARRANGE one pattern worked for VCVTSH2USI inum 9359 + SKIPPING VCVTSH2USI inum 9362 -- already fine + REARRANGE needs to juggle: VCVTSH2USI inum 9365 + REARRANGE one pattern worked for VCVTSH2USI inum 9365 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VCVTUSI2SH inum=9452 iform_input=VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=26 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=0 MODE=2 ZEROING=0 MASK=0 + +VCVTUSI2SH inum=9455 iform_input=VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=25 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() MODE!=2 ZEROING=0 MASK=0 + +VCVTUSI2SH inum=9458 iform_input=VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=26 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=0 r r r n n n FIX_ROUND_LEN128() REXW=1 MODE=2 ZEROING=0 MASK=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTUSI2SH inum 9452 -- already fine + REARRANGE needs to juggle: VCVTUSI2SH inum 9455 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTUSI2SH inum 9452 + REARRANGE one pattern worked for VCVTUSI2SH inum 9452 + SKIPPING VCVTUSI2SH inum 9455 -- already fine + REARRANGE needs to juggle: VCVTUSI2SH inum 9458 + REARRANGE one pattern worked for VCVTUSI2SH inum 9458 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VCVTUSI2SH inum=9453 iform_input=VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=27 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=0 MODE=2 ZEROING=0 MASK=0 + +VCVTUSI2SH inum=9456 iform_input=VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=26 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() MODE!=2 ZEROING=0 MASK=0 + +VCVTUSI2SH inum=9459 iform_input=VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=27 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 1 1 MOD=3 BCRC=1 r r r n n n FIX_ROUND_LEN128() AVX512_ROUND() REXW=1 MODE=2 ZEROING=0 MASK=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTUSI2SH inum 9453 -- already fine + REARRANGE needs to juggle: VCVTUSI2SH inum 9456 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTUSI2SH inum 9453 + REARRANGE one pattern worked for VCVTUSI2SH inum 9453 + SKIPPING VCVTUSI2SH inum 9456 -- already fine + REARRANGE needs to juggle: VCVTUSI2SH inum 9459 + REARRANGE one pattern worked for VCVTUSI2SH inum 9459 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 23 +Others: +VCVTUSI2SH inum=9454 iform_input=VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=0 MODE=2 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() + +VCVTUSI2SH inum=9457 iform_input=VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=28 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() MODE!=2 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() + +VCVTUSI2SH inum=9460 iform_input=VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 isa_set=AVX512_FP16_SCALAR pattern len=29 + ipattern: VEXVALID=2 0 1 1 1 1 0 1 1 VEX_PREFIX=3 MAP=5 m m MOD!=3 r r r n n n BCRC=0 MODRM() FIX_ROUND_LEN128() REXW=1 MODE=2 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() + +Ones: +Zeros: +REARRANGE ATTEMPT using REXW + SKIPPING VCVTUSI2SH inum 9454 -- already fine + REARRANGE needs to juggle: VCVTUSI2SH inum 9457 + REARRANGE FAILED for REXW. Trying again... +REARRANGE ATTEMPT using MODE + REARRANGE needs to juggle: VCVTUSI2SH inum 9454 + REARRANGE one pattern worked for VCVTUSI2SH inum 9454 + SKIPPING VCVTUSI2SH inum 9457 -- already fine + REARRANGE needs to juggle: VCVTUSI2SH inum 9460 + REARRANGE one pattern worked for VCVTUSI2SH inum 9460 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +FUNKY SPOT: bitpos 22 +Others: +VPBROADCASTD inum=7845 iform_input=VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 isa_set=AVX512F_128 pattern len=26 + ipattern: VEXVALID=2 0 1 1 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +VPBROADCASTD inum=7846 iform_input=VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 isa_set=AVX512F_128 pattern len=27 + ipattern: VEXVALID=2 0 1 1 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +VPBROADCASTQ inum=7857 iform_input=VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 isa_set=AVX512F_128 pattern len=27 + ipattern: VEXVALID=2 0 1 1 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 BCRC=0 r r r n n n VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VPBROADCASTD inum 7845 -- already fine + SKIPPING VPBROADCASTD inum 7846 -- already fine + REARRANGE needs to juggle: VPBROADCASTQ inum 7857 + REARRANGE one pattern worked for VPBROADCASTQ inum 7857 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 22 +Others: +VPBROADCASTD inum=7849 iform_input=VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 isa_set=AVX512F_256 pattern len=26 + ipattern: VEXVALID=2 0 1 1 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 BCRC=0 r r r n n n VL=1 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +VPBROADCASTD inum=7850 iform_input=VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 isa_set=AVX512F_256 pattern len=27 + ipattern: VEXVALID=2 0 1 1 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 BCRC=0 r r r n n n VL=1 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +VPBROADCASTQ inum=7860 iform_input=VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 isa_set=AVX512F_256 pattern len=27 + ipattern: VEXVALID=2 0 1 1 1 1 1 0 0 VEX_PREFIX=1 MAP=2 1 1 MOD=3 BCRC=0 r r r n n n VL=1 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VPBROADCASTD inum 7849 -- already fine + SKIPPING VPBROADCASTD inum 7850 -- already fine + REARRANGE needs to juggle: VPBROADCASTQ inum 7860 + REARRANGE one pattern worked for VPBROADCASTQ inum 7860 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 22 +Others: +VMOVD inum=6618 iform_input=VMOVD_GPR32u32_XMMu32_AVX512 isa_set=AVX512F_128N pattern len=28 + ipattern: VEXVALID=2 0 1 1 1 1 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 + +VMOVD inum=6619 iform_input=VMOVD_GPR32u32_XMMu32_AVX512 isa_set=AVX512F_128N pattern len=29 + ipattern: VEXVALID=2 0 1 1 1 1 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 BCRC=0 r r r n n n VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 + +VMOVQ inum=6656 iform_input=VMOVQ_GPR64u64_XMMu64_AVX512 isa_set=AVX512F_128N pattern len=29 + ipattern: VEXVALID=2 0 1 1 1 1 1 1 0 VEX_PREFIX=1 MAP=1 1 1 MOD=3 BCRC=0 r r r n n n VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VMOVD inum 6618 -- already fine + SKIPPING VMOVD inum 6619 -- already fine + REARRANGE needs to juggle: VMOVQ inum 6656 + REARRANGE one pattern worked for VMOVQ inum 6656 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 22 +FUNKY SPOT: bitpos 23 +Others: +VMOVD inum=6620 iform_input=VMOVD_MEMu32_XMMu32_AVX512 isa_set=AVX512F_128N pattern len=31 + ipattern: VEXVALID=2 0 1 1 1 1 1 1 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE!=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() + +VMOVD inum=6621 iform_input=VMOVD_MEMu32_XMMu32_AVX512 isa_set=AVX512F_128N pattern len=32 + ipattern: VEXVALID=2 0 1 1 1 1 1 1 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 MODE=2 REXW=0 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() + +VMOVQ inum=6657 iform_input=VMOVQ_MEMu64_XMMu64_AVX512 isa_set=AVX512F_128N pattern len=32 + ipattern: VEXVALID=2 0 1 1 1 1 1 1 0 VEX_PREFIX=1 MAP=1 m m MOD!=3 r r r n n n BCRC=0 MODRM() VL=0 REXW=1 MODE=2 VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() + +Ones: +Zeros: +REARRANGE ATTEMPT using MODE + SKIPPING VMOVD inum 6620 -- already fine + SKIPPING VMOVD inum 6621 -- already fine + REARRANGE needs to juggle: VMOVQ inum 6657 + REARRANGE one pattern worked for VMOVQ inum 6657 +REARRANGE: FIXED OD CONFLICT! +REARRANGED ODs TO BYPASS PROBLEM at bitpos 23 +[NUMBER OF CONVERT PATTERNS] 5 +FE:EMIT_FILE obj/xed-operand-convert-init.c +emit_iclass_enum_info +FE:EMIT_FILE obj/xed-iclass-enum.txt +FE:EMIT_FILE obj/xed-iclass-enum.c +FE:EMIT_FILE obj/xed-iclass-enum.h +NOREP KEYS: [0, 112, 113, 115, 117, 291, 292, 295, 400, 401, 402, 403, 456, 457, 461, 463, 498, 499, 500, 761, 762, 763, 764, 819, 820, 821, 822, 1741] +REP KEYS: [696, 697, 698, 699, 700, 701, 702, 703, 704, 705, 706, 707, 708, 709, 710, 711, 712, 713, 714, 715, 716, 717, 718, 719, 720, 721, 722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733, 734, 735, 736, 737, 738] +key - 696 +h(x) = linear(x - 696) +FOUND PERFECT HASH FUNCTION FOR repinst +((11*key % 79) % 56) +x = Sigma(Ti << bit_shift) +FKS(x) = (11x mod 79) mod 56 +FOUND PERFECT HASH FUNCTION FOR norepinst +FE:EMIT_FILE obj/xed-rep-map.c +FE:EMIT_FILE obj/xed-iform-enum.txt +FE:EMIT_FILE obj/xed-iform-enum.c +FE:EMIT_FILE obj/xed-iform-enum.h +FE:EMIT_FILE obj/xed-iformfl-enum.txt +FE:EMIT_FILE obj/xed-iformfl-enum.c +FE:EMIT_FILE obj/xed-iformfl-enum.h +FE:EMIT_FILE obj/xed-iform-max.c +FE:EMIT_FILE obj/xed-iclass-string.c +[DUPLICATE IFORM] FLDENV_MEMmem14 +[DUPLICATE IFORM] FLDENV_MEMmem14 +[DUPLICATE IFORM] FLDENV_MEMmem28 +[DUPLICATE IFORM] FLDENV_MEMmem28 +[DUPLICATE IFORM] FLDENV_MEMmem28 +[DUPLICATE IFORM] FNSTENV_MEMmem14 +[DUPLICATE IFORM] FNSTENV_MEMmem14 +[DUPLICATE IFORM] FNSTENV_MEMmem28 +[DUPLICATE IFORM] FNSTENV_MEMmem28 +[DUPLICATE IFORM] FNSTENV_MEMmem28 +[DUPLICATE IFORM] FRSTOR_MEMmem94 +[DUPLICATE IFORM] FRSTOR_MEMmem94 +[DUPLICATE IFORM] FRSTOR_MEMmem108 +[DUPLICATE IFORM] FRSTOR_MEMmem108 +[DUPLICATE IFORM] FRSTOR_MEMmem108 +[DUPLICATE IFORM] FNSAVE_MEMmem94 +[DUPLICATE IFORM] FNSAVE_MEMmem94 +[DUPLICATE IFORM] FNSAVE_MEMmem108 +[DUPLICATE IFORM] FNSAVE_MEMmem108 +[DUPLICATE IFORM] FNSAVE_MEMmem108 +[DUPLICATE IFORM] JMP_RELBRb +[DUPLICATE IFORM] CMPXCHG8B_LOCK_MEMq +[DUPLICATE IFORM] CMPXCHG8B_MEMq +[DUPLICATE IFORM] NOP_90 +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1B +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1A +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1B +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_GPRv_GPRv_0F1E +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] NOP_MEMv_GPRv_0F1C +[DUPLICATE IFORM] MONITOR +[DUPLICATE IFORM] MONITOR +[DUPLICATE IFORM] MONITOR +[DUPLICATE IFORM] PUSHA +[DUPLICATE IFORM] PUSHAD +[DUPLICATE IFORM] POPA +[DUPLICATE IFORM] POPAD +[DUPLICATE IFORM] BOUND_GPRv_MEMa16 +[DUPLICATE IFORM] BOUND_GPRv_MEMa32 +[DUPLICATE IFORM] REP_INSB +[DUPLICATE IFORM] REP_INSW +[DUPLICATE IFORM] REP_INSW +[DUPLICATE IFORM] REP_INSW +[DUPLICATE IFORM] REP_INSW +[DUPLICATE IFORM] REP_INSW +[DUPLICATE IFORM] INSW +[DUPLICATE IFORM] INSW +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] REP_INSD +[DUPLICATE IFORM] INSD +[DUPLICATE IFORM] INSD +[DUPLICATE IFORM] INSD +[DUPLICATE IFORM] REP_OUTSB +[DUPLICATE IFORM] REP_OUTSW +[DUPLICATE IFORM] REP_OUTSW +[DUPLICATE IFORM] REP_OUTSW +[DUPLICATE IFORM] REP_OUTSW +[DUPLICATE IFORM] REP_OUTSW +[DUPLICATE IFORM] OUTSW +[DUPLICATE IFORM] OUTSW +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] REP_OUTSD +[DUPLICATE IFORM] OUTSD +[DUPLICATE IFORM] OUTSD +[DUPLICATE IFORM] OUTSD +[DUPLICATE IFORM] JO_RELBRb +[DUPLICATE IFORM] JNO_RELBRb +[DUPLICATE IFORM] JB_RELBRb +[DUPLICATE IFORM] JNB_RELBRb +[DUPLICATE IFORM] JZ_RELBRb +[DUPLICATE IFORM] JNZ_RELBRb +[DUPLICATE IFORM] JBE_RELBRb +[DUPLICATE IFORM] JNBE_RELBRb +[DUPLICATE IFORM] JS_RELBRb +[DUPLICATE IFORM] JNS_RELBRb +[DUPLICATE IFORM] JP_RELBRb +[DUPLICATE IFORM] JNP_RELBRb +[DUPLICATE IFORM] JL_RELBRb +[DUPLICATE IFORM] JNL_RELBRb +[DUPLICATE IFORM] JLE_RELBRb +[DUPLICATE IFORM] JNLE_RELBRb +[DUPLICATE IFORM] XCHG_MEMb_GPR8 +[DUPLICATE IFORM] XCHG_MEMv_GPRv +[DUPLICATE IFORM] XCHG_GPRv_OrAX +[DUPLICATE IFORM] CBW +[DUPLICATE IFORM] CBW +[DUPLICATE IFORM] CWDE +[DUPLICATE IFORM] CWDE +[DUPLICATE IFORM] CWD +[DUPLICATE IFORM] CWD +[DUPLICATE IFORM] CDQ +[DUPLICATE IFORM] CDQ +[DUPLICATE IFORM] PUSHF +[DUPLICATE IFORM] PUSHF +[DUPLICATE IFORM] PUSHFD +[DUPLICATE IFORM] PUSHFQ +[DUPLICATE IFORM] POPF +[DUPLICATE IFORM] POPF +[DUPLICATE IFORM] POPFD +[DUPLICATE IFORM] POPFQ +[DUPLICATE IFORM] REP_MOVSB +[DUPLICATE IFORM] REP_MOVSW +[DUPLICATE IFORM] REP_MOVSW +[DUPLICATE IFORM] REP_MOVSW +[DUPLICATE IFORM] REP_MOVSW +[DUPLICATE IFORM] REP_MOVSW +[DUPLICATE IFORM] MOVSW +[DUPLICATE IFORM] MOVSW +[DUPLICATE IFORM] REP_MOVSD +[DUPLICATE IFORM] REP_MOVSD +[DUPLICATE IFORM] REP_MOVSD +[DUPLICATE IFORM] REP_MOVSD +[DUPLICATE IFORM] REP_MOVSD +[DUPLICATE IFORM] MOVSD +[DUPLICATE IFORM] MOVSD +[DUPLICATE IFORM] REP_MOVSQ +[DUPLICATE IFORM] REPE_CMPSW +[DUPLICATE IFORM] REPE_CMPSW +[DUPLICATE IFORM] REPNE_CMPSW +[DUPLICATE IFORM] REPNE_CMPSW +[DUPLICATE IFORM] CMPSW +[DUPLICATE IFORM] CMPSW +[DUPLICATE IFORM] REPE_CMPSD +[DUPLICATE IFORM] REPE_CMPSD +[DUPLICATE IFORM] REPNE_CMPSD +[DUPLICATE IFORM] REPNE_CMPSD +[DUPLICATE IFORM] CMPSD +[DUPLICATE IFORM] CMPSD +[DUPLICATE IFORM] REP_STOSB +[DUPLICATE IFORM] REP_STOSW +[DUPLICATE IFORM] REP_STOSW +[DUPLICATE IFORM] REP_STOSW +[DUPLICATE IFORM] REP_STOSW +[DUPLICATE IFORM] REP_STOSW +[DUPLICATE IFORM] STOSW +[DUPLICATE IFORM] STOSW +[DUPLICATE IFORM] REP_STOSD +[DUPLICATE IFORM] REP_STOSD +[DUPLICATE IFORM] REP_STOSD +[DUPLICATE IFORM] REP_STOSD +[DUPLICATE IFORM] REP_STOSD +[DUPLICATE IFORM] STOSD +[DUPLICATE IFORM] STOSD +[DUPLICATE IFORM] REP_STOSQ +[DUPLICATE IFORM] REP_LODSB +[DUPLICATE IFORM] REP_LODSW +[DUPLICATE IFORM] REP_LODSW +[DUPLICATE IFORM] REP_LODSW +[DUPLICATE IFORM] REP_LODSW +[DUPLICATE IFORM] REP_LODSW +[DUPLICATE IFORM] LODSW +[DUPLICATE IFORM] LODSW +[DUPLICATE IFORM] REP_LODSD +[DUPLICATE IFORM] REP_LODSD +[DUPLICATE IFORM] REP_LODSD +[DUPLICATE IFORM] REP_LODSD +[DUPLICATE IFORM] REP_LODSD +[DUPLICATE IFORM] LODSD +[DUPLICATE IFORM] LODSD +[DUPLICATE IFORM] REP_LODSQ +[DUPLICATE IFORM] REPE_SCASW +[DUPLICATE IFORM] REPE_SCASW +[DUPLICATE IFORM] REPNE_SCASW +[DUPLICATE IFORM] REPNE_SCASW +[DUPLICATE IFORM] SCASW +[DUPLICATE IFORM] SCASW +[DUPLICATE IFORM] REPE_SCASD +[DUPLICATE IFORM] REPE_SCASD +[DUPLICATE IFORM] REPNE_SCASD +[DUPLICATE IFORM] REPNE_SCASD +[DUPLICATE IFORM] SCASD +[DUPLICATE IFORM] SCASD +[DUPLICATE IFORM] IRET +[DUPLICATE IFORM] IRET +[DUPLICATE IFORM] IRETD +[DUPLICATE IFORM] IRETD +[DUPLICATE IFORM] LOOPNE_RELBRb +[DUPLICATE IFORM] LOOPNE_RELBRb +[DUPLICATE IFORM] LOOPNE_RELBRb +[DUPLICATE IFORM] LOOPE_RELBRb +[DUPLICATE IFORM] LOOPE_RELBRb +[DUPLICATE IFORM] LOOPE_RELBRb +[DUPLICATE IFORM] JECXZ_RELBRb +[DUPLICATE IFORM] SYSENTER +[DUPLICATE IFORM] SYSEXIT +[DUPLICATE IFORM] MOVNTI_MEMd_GPR32 +[DUPLICATE IFORM] MOVD_XMMdq_MEMd +[DUPLICATE IFORM] MOVD_XMMdq_GPR32 +[DUPLICATE IFORM] MOVD_MEMd_XMMd +[DUPLICATE IFORM] MOVD_GPR32_XMMd +[DUPLICATE IFORM] MOVD_MMXq_MEMd +[DUPLICATE IFORM] MOVD_MMXq_GPR32 +[DUPLICATE IFORM] MOVD_MEMd_MMXd +[DUPLICATE IFORM] MOVD_GPR32_MMXd +[DUPLICATE IFORM] PCMPESTRI_XMMdq_MEMdq_IMMb +[DUPLICATE IFORM] PCMPESTRI_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] PCMPISTRI_XMMdq_MEMdq_IMMb +[DUPLICATE IFORM] PCMPISTRI_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] PCMPESTRM_XMMdq_MEMdq_IMMb +[DUPLICATE IFORM] PCMPESTRM_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] REP_MONTMUL +[DUPLICATE IFORM] MONITORX +[DUPLICATE IFORM] MONITORX +[DUPLICATE IFORM] MONITORX +[DUPLICATE IFORM] BNDMOV_BND_MEMq +[DUPLICATE IFORM] BNDMOV_BND_BND +[DUPLICATE IFORM] BNDMOV_MEMq_BND +[DUPLICATE IFORM] BNDLDX_BND_MEMbnd64 +[DUPLICATE IFORM] BNDLDX_BND_MEMbnd64 +[DUPLICATE IFORM] BNDSTX_MEMbnd64_BND +[DUPLICATE IFORM] BNDSTX_MEMbnd64_BND +[DUPLICATE IFORM] MOVDIR64B_GPRa_MEM +[DUPLICATE IFORM] BSF_GPRv_MEMv +[DUPLICATE IFORM] BSF_GPRv_GPRv +[DUPLICATE IFORM] BSR_GPRv_MEMv +[DUPLICATE IFORM] BSR_GPRv_GPRv +[DUPLICATE IFORM] WBINVD +[DUPLICATE IFORM] TDCALL +[DUPLICATE IFORM] VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VPPERM_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPROTB_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPROTW_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPROTD_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPROTQ_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHLB_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHLW_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHLD_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHLQ_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHAB_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHAW_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHAD_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VPSHAQ_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMADDSS_XMMdq_XMMd_XMMd_XMMd +[DUPLICATE IFORM] VFMADDSD_XMMdq_XMMq_XMMq_XMMq +[DUPLICATE IFORM] VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFMSUBSS_XMMdq_XMMd_XMMd_XMMd +[DUPLICATE IFORM] VFMSUBSD_XMMdq_XMMq_XMMq_XMMq +[DUPLICATE IFORM] VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFNMADDSS_XMMdq_XMMd_XMMd_XMMd +[DUPLICATE IFORM] VFNMADDSD_XMMdq_XMMq_XMMq_XMMq +[DUPLICATE IFORM] VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq +[DUPLICATE IFORM] VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq +[DUPLICATE IFORM] VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd +[DUPLICATE IFORM] VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq +[DUPLICATE IFORM] VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb +[DUPLICATE IFORM] VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb +[DUPLICATE IFORM] VCVTSD2SI_GPR32d_MEMq +[DUPLICATE IFORM] VCVTSD2SI_GPR32d_XMMq +[DUPLICATE IFORM] VCVTTSD2SI_GPR32d_MEMq +[DUPLICATE IFORM] VCVTTSD2SI_GPR32d_XMMq +[DUPLICATE IFORM] VCVTSS2SI_GPR32d_MEMd +[DUPLICATE IFORM] VCVTSS2SI_GPR32d_XMMd +[DUPLICATE IFORM] VCVTTSS2SI_GPR32d_MEMd +[DUPLICATE IFORM] VCVTTSS2SI_GPR32d_XMMd +[DUPLICATE IFORM] VCVTSI2SD_XMMdq_XMMdq_MEMd +[DUPLICATE IFORM] VCVTSI2SD_XMMdq_XMMdq_GPR32d +[DUPLICATE IFORM] VCVTSI2SS_XMMdq_XMMdq_MEMd +[DUPLICATE IFORM] VCVTSI2SS_XMMdq_XMMdq_GPR32d +[DUPLICATE IFORM] VMOVD_XMMdq_MEMd +[DUPLICATE IFORM] VMOVD_XMMdq_GPR32d +[DUPLICATE IFORM] VMOVD_MEMd_XMMd +[DUPLICATE IFORM] VMOVD_GPR32d_XMMd +[DUPLICATE IFORM] VPEXTRD_MEMd_XMMdq_IMMb +[DUPLICATE IFORM] VPEXTRD_GPR32d_XMMdq_IMMb +[DUPLICATE IFORM] VPINSRD_XMMdq_XMMdq_MEMd_IMMb +[DUPLICATE IFORM] VPINSRD_XMMdq_XMMdq_GPR32d_IMMb +[DUPLICATE IFORM] VPCMPESTRI_XMMdq_MEMdq_IMMb +[DUPLICATE IFORM] VPCMPESTRI_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] VPCMPISTRI_XMMdq_MEMdq_IMMb +[DUPLICATE IFORM] VPCMPISTRI_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] VPCMPESTRM_XMMdq_MEMdq_IMMb +[DUPLICATE IFORM] VPCMPESTRM_XMMdq_XMMdq_IMMb +[DUPLICATE IFORM] PDEP_VGPR32d_VGPR32d_MEMd +[DUPLICATE IFORM] PDEP_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] PEXT_VGPR32d_VGPR32d_MEMd +[DUPLICATE IFORM] PEXT_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] ANDN_VGPR32d_VGPR32d_MEMd +[DUPLICATE IFORM] ANDN_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] BLSR_VGPR32d_MEMd +[DUPLICATE IFORM] BLSR_VGPR32d_VGPR32d +[DUPLICATE IFORM] BLSMSK_VGPR32d_MEMd +[DUPLICATE IFORM] BLSMSK_VGPR32d_VGPR32d +[DUPLICATE IFORM] BLSI_VGPR32d_MEMd +[DUPLICATE IFORM] BLSI_VGPR32d_VGPR32d +[DUPLICATE IFORM] BZHI_VGPR32d_MEMd_VGPR32d +[DUPLICATE IFORM] BZHI_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] BEXTR_VGPR32d_MEMd_VGPR32d +[DUPLICATE IFORM] BEXTR_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] SHLX_VGPR32d_MEMd_VGPR32d +[DUPLICATE IFORM] SHLX_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] SARX_VGPR32d_MEMd_VGPR32d +[DUPLICATE IFORM] SARX_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] SHRX_VGPR32d_MEMd_VGPR32d +[DUPLICATE IFORM] SHRX_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] MULX_VGPR32d_VGPR32d_VGPR32d +[DUPLICATE IFORM] MULX_VGPR32d_VGPR32d_MEMd +[DUPLICATE IFORM] RORX_VGPR32d_VGPR32d_IMMb +[DUPLICATE IFORM] RORX_VGPR32d_MEMd_IMMb +[DUPLICATE IFORM] KMOVD_MASKmskw_GPR32u32_AVX512 +[DUPLICATE IFORM] KMOVD_GPR32u32_MASKmskw_AVX512 +[DUPLICATE IFORM] VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +[DUPLICATE IFORM] VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +[DUPLICATE IFORM] VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +[DUPLICATE IFORM] VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +[DUPLICATE IFORM] VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +[DUPLICATE IFORM] VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +[DUPLICATE IFORM] VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +[DUPLICATE IFORM] VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +[DUPLICATE IFORM] VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +[DUPLICATE IFORM] VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +[DUPLICATE IFORM] VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VCOMISD_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VCOMISS_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +[DUPLICATE IFORM] VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +[DUPLICATE IFORM] VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +[DUPLICATE IFORM] VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +[DUPLICATE IFORM] VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +[DUPLICATE IFORM] VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +[DUPLICATE IFORM] VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VCVTSD2SI_GPR32i32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2SI_GPR32i32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2SI_GPR32i32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2SI_GPR32i32_MEMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2SI_GPR64i64_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2USI_GPR32u32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2USI_GPR32u32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2USI_GPR32u32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2USI_GPR32u32_MEMf64_AVX512 +[DUPLICATE IFORM] VCVTSD2USI_GPR64u64_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +[DUPLICATE IFORM] VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +[DUPLICATE IFORM] VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +[DUPLICATE IFORM] VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +[DUPLICATE IFORM] VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2SI_GPR32i32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2SI_GPR32i32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2SI_GPR32i32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2SI_GPR32i32_MEMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2SI_GPR64i64_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2USI_GPR32u32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2USI_GPR32u32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2USI_GPR32u32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2USI_GPR32u32_MEMf32_AVX512 +[DUPLICATE IFORM] VCVTSS2USI_GPR64u64_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +[DUPLICATE IFORM] VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +[DUPLICATE IFORM] VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +[DUPLICATE IFORM] VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +[DUPLICATE IFORM] VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +[DUPLICATE IFORM] VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +[DUPLICATE IFORM] VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +[DUPLICATE IFORM] VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +[DUPLICATE IFORM] VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +[DUPLICATE IFORM] VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +[DUPLICATE IFORM] VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VMOVD_XMMu32_GPR32u32_AVX512 +[DUPLICATE IFORM] VMOVD_XMMu32_MEMu32_AVX512 +[DUPLICATE IFORM] VMOVD_GPR32u32_XMMu32_AVX512 +[DUPLICATE IFORM] VMOVD_MEMu32_XMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +[DUPLICATE IFORM] VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +[DUPLICATE IFORM] VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +[DUPLICATE IFORM] VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +[DUPLICATE IFORM] VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +[DUPLICATE IFORM] VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +[DUPLICATE IFORM] VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +[DUPLICATE IFORM] VMOVQ_XMMu64_MEMu64_AVX512 +[DUPLICATE IFORM] VMOVQ_XMMu64_XMMu64_AVX512 +[DUPLICATE IFORM] VMOVQ_MEMu64_XMMu64_AVX512 +[DUPLICATE IFORM] VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +[DUPLICATE IFORM] VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +[DUPLICATE IFORM] VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +[DUPLICATE IFORM] VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +[DUPLICATE IFORM] VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +[DUPLICATE IFORM] VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +[DUPLICATE IFORM] VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +[DUPLICATE IFORM] VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +[DUPLICATE IFORM] VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VUCOMISD_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VUCOMISS_XMMf32_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +[DUPLICATE IFORM] VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +[DUPLICATE IFORM] VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +[DUPLICATE IFORM] VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +[DUPLICATE IFORM] VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +[DUPLICATE IFORM] VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +[DUPLICATE IFORM] VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +[DUPLICATE IFORM] VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +[DUPLICATE IFORM] VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +[DUPLICATE IFORM] VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +[DUPLICATE IFORM] VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +[DUPLICATE IFORM] VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +[DUPLICATE IFORM] VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 +[DUPLICATE IFORM] VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +[DUPLICATE IFORM] VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +[DUPLICATE IFORM] VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +[DUPLICATE IFORM] VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +[DUPLICATE IFORM] VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VCOMISH_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 +[DUPLICATE IFORM] VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 +[DUPLICATE IFORM] VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +[DUPLICATE IFORM] VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +[DUPLICATE IFORM] VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 +[DUPLICATE IFORM] VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +[DUPLICATE IFORM] VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 +[DUPLICATE IFORM] VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2SI_GPR32i32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2SI_GPR32i32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2SI_GPR32i32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2SI_GPR32i32_MEMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2SI_GPR64i64_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2USI_GPR32u32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2USI_GPR32u32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2USI_GPR32u32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2USI_GPR32u32_MEMf16_AVX512 +[DUPLICATE IFORM] VCVTSH2USI_GPR64u64_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +[DUPLICATE IFORM] VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 +[DUPLICATE IFORM] VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 +[DUPLICATE IFORM] VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 +[DUPLICATE IFORM] VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +[DUPLICATE IFORM] VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +[DUPLICATE IFORM] VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +[DUPLICATE IFORM] VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2SI_GPR32i32_MEMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2SI_GPR64i64_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2USI_GPR32u32_MEMf16_AVX512 +[DUPLICATE IFORM] VCVTTSH2USI_GPR64u64_XMMf16_AVX512 +[DUPLICATE IFORM] VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 +[DUPLICATE IFORM] VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +[DUPLICATE IFORM] VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 +[DUPLICATE IFORM] VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 +[DUPLICATE IFORM] VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 +[DUPLICATE IFORM] VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 +[DUPLICATE IFORM] VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +[DUPLICATE IFORM] VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +[DUPLICATE IFORM] VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +[DUPLICATE IFORM] VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +[DUPLICATE IFORM] VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +[DUPLICATE IFORM] VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +[DUPLICATE IFORM] VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +[DUPLICATE IFORM] VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +[DUPLICATE IFORM] VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +[DUPLICATE IFORM] VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +[DUPLICATE IFORM] VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +[DUPLICATE IFORM] VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +[DUPLICATE IFORM] VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +[DUPLICATE IFORM] VUCOMISH_XMMf16_XMMf16_AVX512 +FE:EMIT_FILE obj/idata.txt +FE:EMIT_FILE obj/xed-iform-map-init.c +FE:EMIT_FILE obj/xed-exception-enum.txt +FE:EMIT_FILE obj/xed-exception-enum.c +FE:EMIT_FILE obj/xed-exception-enum.h +[Unique Operand Sequences] 2828 +[Number of required operand sequence pointers] 8974 +[Number of reused operand sequence pointers] 6976 +[Number of required operands] 1502 +[MAX OPERAND COUNT 11] +[INVALID WIDTH CODE] REP imm_const [0x2] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REP imm_const [0x3] r SUPPRESSED INVALID +[INVALID WIDTH CODE] LOCK imm_const [0x1] r SUPPRESSED INVALID +[INVALID WIDTH CODE] HINT imm_const [0x1] r SUPPRESSED INVALID +[INVALID WIDTH CODE] HINT imm_const [0x2] r SUPPRESSED INVALID +[INVALID WIDTH CODE] HINT imm_const [0x3] r SUPPRESSED INVALID +[INVALID WIDTH CODE] HINT imm_const [0x4] r SUPPRESSED INVALID +[INVALID WIDTH CODE] HINT imm_const [0x5] r SUPPRESSED INVALID +[INVALID WIDTH CODE] EOSZ imm_const [0x1] r SUPPRESSED INVALID +[INVALID WIDTH CODE] EOSZ imm_const [0x2] r SUPPRESSED INVALID +[INVALID WIDTH CODE] EOSZ imm_const [0x3] r SUPPRESSED INVALID +[INVALID WIDTH CODE] EASZ imm_const [0x1] r SUPPRESSED INVALID +[INVALID WIDTH CODE] EASZ imm_const [0x2] r SUPPRESSED INVALID +[INVALID WIDTH CODE] EASZ imm_const [0x3] r SUPPRESSED INVALID +[INVALID WIDTH CODE] IMM0SIGNED imm_const [0x1] r EXPLICIT INVALID +[INVALID WIDTH CODE] DISP_WIDTH imm_const [0x10] r SUPPRESSED INVALID +[INVALID WIDTH CODE] DISP_WIDTH imm_const [0x20] r SUPPRESSED INVALID +[INVALID WIDTH CODE] DISP_WIDTH imm_const [0x40] r SUPPRESSED INVALID +[INVALID WIDTH CODE] DISP_WIDTH imm_const [0x8] r SUPPRESSED INVALID +[INVALID WIDTH CODE] DISP_WIDTH imm_const [0x0] r SUPPRESSED INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar8 INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar9 INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT ArDX INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar10 INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar11 INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT rIPa INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar14 INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar15 INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar13 INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_ESI] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_EDI] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_EBP] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_BX] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_BP] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_SI] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_DI] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 reg [XED_REG_INVALID] r EXPLICIT INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT ArSP INVALID +[INVALID WIDTH CODE] BASE0 nt_lookup_fn r EXPLICIT Ar12 INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn w EXPLICIT SEG_MOV INVALID +[INVALID WIDTH CODE] REG2 reg [XED_REG_CX] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG4 reg [XED_REG_BX] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG5 reg [XED_REG_SP] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG6 reg [XED_REG_BP] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG7 reg [XED_REG_SI] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG8 reg [XED_REG_DI] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG5 reg [XED_REG_ESP] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG6 reg [XED_REG_EBP] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG7 reg [XED_REG_ESI] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG8 reg [XED_REG_EDI] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG2 reg [XED_REG_CX] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG4 reg [XED_REG_BX] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG5 reg [XED_REG_BP] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG6 reg [XED_REG_SI] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG7 reg [XED_REG_DI] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG5 reg [XED_REG_EBP] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG6 reg [XED_REG_ESI] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG7 reg [XED_REG_EDI] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG0 reg [XED_REG_CX] r SUPPRESSED INVALID +[INVALID WIDTH CODE] REG1 reg [XED_REG_IP] rw SUPPRESSED INVALID +[INVALID WIDTH CODE] REG1 reg [XED_REG_ESP] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG1 reg [XED_REG_RSP] w SUPPRESSED INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn r SUPPRESSED OrCX INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID +[INVALID WIDTH CODE] REG2 nt_lookup_fn r SUPPRESSED OrBX INVALID +[INVALID WIDTH CODE] REG1 nt_lookup_fn rcw SUPPRESSED OrCX INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn w EXPLICIT BND_R INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn r EXPLICIT BND_R INVALID +[INVALID WIDTH CODE] REG1 nt_lookup_fn r EXPLICIT BND_B INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn w EXPLICIT BND_B INVALID +[INVALID WIDTH CODE] REG1 nt_lookup_fn r EXPLICIT BND_R INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn r EXPLICIT A_GPR_R INVALID +[INVALID WIDTH CODE] BASE1 nt_lookup_fn r SUPPRESSED A_GPR_R INVALID +[INVALID WIDTH CODE] REG0 nt_lookup_fn r EXPLICIT A_GPR_B INVALID +FE:EMIT_FILE obj/xed-init-operand-data.c +FE:EMIT_FILE obj/xed-init-operand-sequences.c +FE:EMIT_FILE obj/xed-init-inst-table-data.c +FE:EMIT_FILE obj/xed-init-inst-table-0.c +FE:EMIT_FILE obj/xed-init-inst-table.c +emit_enum_info +OPERAND-NAMES SEG_OVD HINT ENCODE_FORCE LOCK NEED_MEMDISP DISP DISP_WIDTH BRDISP_WIDTH DF32 DF64 NOREX NEEDREX REX REXW REXR REXX REXB REP OSZ PREFIX66 ASZ EOSZ EASZ MOD REG SRM RM REALMODE CHIP MODE SMODE MODEP5 MODEP55C P4 LZCNT TZCNT MODE_FIRST_PREFIX MODE_SHORT_UD0 IMM0 IMM1 IMM0SIGNED UIMM0 UIMM1 IMM_WIDTH USING_DEFAULT_SEGMENT0 USING_DEFAULT_SEGMENT1 DEFAULT_SEG SEG0 BASE0 INDEX SCALE NEED_SIB SIBSCALE SIBBASE SIBINDEX SEG1 BASE1 MEM0 MEM1 MEM_WIDTH AGEN RELBR PTR REG0 REG1 REG2 REG3 REG4 REG5 REG6 REG7 REG8 REG9 OUTREG ENCODER_PREFERRED ERROR ICLASS NELEM ELEMENT_SIZE MAP OUT_OF_BYTES FIRST_F2F3 LAST_F2F3 ILD_F2 ILD_F3 MAX_BYTES ILD_SEG NSEG_PREFIXES NREXES NPREFIXES NOMINAL_OPCODE POS_NOMINAL_OPCODE HAS_MODRM HAS_SIB POS_MODRM POS_SIB POS_DISP POS_IMM POS_IMM1 IMM1_BYTES MODRM_BYTE ESRC VEXVALID DUMMY AMD3DNOW MPXMODE CET CLDEMOTE VEXDEST3 VEXDEST210 VL VEX_PREFIX VEX_C4 BCAST MUST_USE_EVEX ZEROING LLRC BCRC REXRR VEXDEST4 MASK ROUNDC SAE NO_SCALE_DISP8 UBIT WBNOINVD +FE:EMIT_FILE obj/xed-attributes-list.c +FE:EMIT_FILE obj/xed-nonterminal-enum.txt +FE:EMIT_FILE obj/xed-nonterminal-enum.c +FE:EMIT_FILE obj/xed-nonterminal-enum.h +FE:EMIT_FILE obj/xed-operand-enum.txt +FE:EMIT_FILE obj/xed-operand-enum.c +FE:EMIT_FILE obj/xed-operand-enum.h +FE:EMIT_FILE obj/xed-operand-type-enum.txt +FE:EMIT_FILE obj/xed-operand-type-enum.c +FE:EMIT_FILE obj/xed-operand-type-enum.h +FE:EMIT_FILE obj/xed-attribute-enum.txt +FE:EMIT_FILE obj/xed-attribute-enum.c +FE:EMIT_FILE obj/xed-attribute-enum.h +FE:EMIT_FILE obj/xed-category-enum.txt +FE:EMIT_FILE obj/xed-category-enum.c +FE:EMIT_FILE obj/xed-category-enum.h +FE:EMIT_FILE obj/xed-extension-enum.txt +FE:EMIT_FILE obj/xed-extension-enum.c +FE:EMIT_FILE obj/xed-extension-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-addr-width-enum.txt +FE:EMIT_FILE obj/xed-address-width-enum.c +FE:EMIT_FILE obj/xed-address-width-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-error-enum.txt +FE:EMIT_FILE obj/xed-error-enum.c +FE:EMIT_FILE obj/xed-error-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-flag-action-enum.txt +FE:EMIT_FILE obj/xed-flag-action-enum.c +FE:EMIT_FILE obj/xed-flag-action-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-flag-enum.txt +FE:EMIT_FILE obj/xed-flag-enum.c +FE:EMIT_FILE obj/xed-flag-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-machine-modes-enum.txt +FE:EMIT_FILE obj/xed-machine-mode-enum.c +FE:EMIT_FILE obj/xed-machine-mode-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-operand-action-enum.txt +FE:EMIT_FILE obj/xed-operand-action-enum.c +FE:EMIT_FILE obj/xed-operand-action-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-operand-visibility-enum.txt +FE:EMIT_FILE obj/xed-operand-visibility-enum.c +FE:EMIT_FILE obj/xed-operand-visibility-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-reg-role.enum.txt +FE:EMIT_FILE obj/xed-reg-role-enum.c +FE:EMIT_FILE obj/xed-reg-role-enum.h +PREFAB-ENUM: C:/$Fanta/IntelXED/xed\datafiles\xed-syntax-enum.txt +FE:EMIT_FILE obj/xed-syntax-enum.c +FE:EMIT_FILE obj/xed-syntax-enum.h +FE:EMIT_FILE obj/xed-attributes-init.c +FE:EMIT_FILE obj/xed-gen-table-defs.h +FE:EMIT_FILE obj/cdata.txt +FE:EMIT_FILE obj/xed-chip-enum.txt +FE:EMIT_FILE obj/xed-chip-enum.c +FE:EMIT_FILE obj/xed-chip-enum.h +[FROM CHIP MODEL] ['INVALID', '3DNOW', '3DNOW_PREFETCH', 'ADOX_ADCX', 'AES', 'AMD', 'AMD_INVLPGB', 'AMX_BF16', 'AMX_INT8', 'AMX_TILE', 'AVX', 'AVX2', 'AVX2GATHER', 'AVX512BW_128', 'AVX512BW_128N', 'AVX512BW_256', 'AVX512BW_512', 'AVX512BW_KOP', 'AVX512CD_128', 'AVX512CD_256', 'AVX512CD_512', 'AVX512DQ_128', 'AVX512DQ_128N', 'AVX512DQ_256', 'AVX512DQ_512', 'AVX512DQ_KOP', 'AVX512DQ_SCALAR', 'AVX512ER_512', 'AVX512ER_SCALAR', 'AVX512F_128', 'AVX512F_128N', 'AVX512F_256', 'AVX512F_512', 'AVX512F_KOP', 'AVX512F_SCALAR', 'AVX512PF_512', 'AVX512_4FMAPS_512', 'AVX512_4FMAPS_SCALAR', 'AVX512_4VNNIW_512', 'AVX512_BF16_128', 'AVX512_BF16_256', 'AVX512_BF16_512', 'AVX512_BITALG_128', 'AVX512_BITALG_256', 'AVX512_BITALG_512', 'AVX512_FP16_128', 'AVX512_FP16_128N', 'AVX512_FP16_256', 'AVX512_FP16_512', 'AVX512_FP16_SCALAR', 'AVX512_GFNI_128', 'AVX512_GFNI_256', 'AVX512_GFNI_512', 'AVX512_IFMA_128', 'AVX512_IFMA_256', 'AVX512_IFMA_512', 'AVX512_VAES_128', 'AVX512_VAES_256', 'AVX512_VAES_512', 'AVX512_VBMI2_128', 'AVX512_VBMI2_256', 'AVX512_VBMI2_512', 'AVX512_VBMI_128', 'AVX512_VBMI_256', 'AVX512_VBMI_512', 'AVX512_VNNI_128', 'AVX512_VNNI_256', 'AVX512_VNNI_512', 'AVX512_VP2INTERSECT_128', 'AVX512_VP2INTERSECT_256', 'AVX512_VP2INTERSECT_512', 'AVX512_VPCLMULQDQ_128', 'AVX512_VPCLMULQDQ_256', 'AVX512_VPCLMULQDQ_512', 'AVX512_VPOPCNTDQ_128', 'AVX512_VPOPCNTDQ_256', 'AVX512_VPOPCNTDQ_512', 'AVXAES', 'AVX_GFNI', 'AVX_VNNI', 'BMI1', 'BMI2', 'CET', 'CLDEMOTE', 'CLFLUSHOPT', 'CLFSH', 'CLWB', 'CLZERO', 'CMOV', 'CMPXCHG16B', 'ENQCMD', 'F16C', 'FAT_NOP', 'FCMOV', 'FMA', 'FMA4', 'FXSAVE', 'FXSAVE64', 'GFNI', 'HRESET', 'I186', 'I286PROTECTED', 'I286REAL', 'I386', 'I486', 'I486REAL', 'I86', 'INVPCID', 'KEYLOCKER', 'KEYLOCKER_WIDE', 'LAHF', 'LONGMODE', 'LWP', 'LZCNT', 'MCOMMIT', 'MONITOR', 'MONITORX', 'MOVBE', 'MOVDIR', 'MPX', 'PAUSE', 'PCLMULQDQ', 'PCONFIG', 'PENTIUMMMX', 'PENTIUMREAL', 'PKU', 'POPCNT', 'PPRO', 'PPRO_UD0_LONG', 'PPRO_UD0_SHORT', 'PREFETCHW', 'PREFETCHWT1', 'PREFETCH_NOP', 'PTWRITE', 'RDPID', 'RDPMC', 'RDPRU', 'RDRAND', 'RDSEED', 'RDTSCP', 'RDWRFSGS', 'RTM', 'SERIALIZE', 'SGX', 'SGX_ENCLV', 'SHA', 'SMAP', 'SMX', 'SNP', 'SSE', 'SSE2', 'SSE2MMX', 'SSE3', 'SSE3X87', 'SSE4', 'SSE42', 'SSE4A', 'SSEMXCSR', 'SSE_PREFETCH', 'SSSE3', 'SSSE3MMX', 'SVM', 'TBM', 'TDX', 'TSX_LDTRK', 'UINTR', 'VAES', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_MONTMUL', 'VIA_PADLOCK_RNG', 'VIA_PADLOCK_SHA', 'VMFUNC', 'VPCLMULQDQ', 'VTX', 'WAITPKG', 'WBNOINVD', 'X87', 'XOP', 'XSAVE', 'XSAVEC', 'XSAVEOPT', 'XSAVES'] +[FROM INSTRUCTIONS ] {'VIA_PADLOCK_SHA', 'SSE4A', 'AVX_VNNI', 'XOP', 'PREFETCHWT1', 'AVX512_VPCLMULQDQ_256', 'SSE42', 'AVX512_VNNI_256', 'PAUSE', 'AVX512PF_512', 'AVX512CD_256', 'WBNOINVD', 'RDTSCP', 'AVX512_VPOPCNTDQ_128', 'AVX_GFNI', 'MOVBE', 'AVX512BW_128N', 'VMFUNC', 'SSE_PREFETCH', 'AVX512_VBMI2_256', 'MONITORX', 'SSSE3MMX', 'AVX512DQ_KOP', 'AVX512_VNNI_128', 'I86', 'AVX512BW_512', 'UINTR', 'TSX_LDTRK', 'TBM', 'AVX512_FP16_512', 'VIA_PADLOCK_RNG', 'LWP', 'AVX512_GFNI_512', 'AVX512BW_KOP', 'PENTIUMMMX', 'KEYLOCKER', 'XSAVEOPT', 'CLDEMOTE', 'BMI2', 'AVX512_VAES_256', 'AVX512_VNNI_512', 'AVX512_VP2INTERSECT_256', 'MOVDIR', 'AVX512_IFMA_256', 'AVX512_GFNI_128', 'INVPCID', 'FMA', 'MONITOR', 'AVX2GATHER', 'AVX512_4FMAPS_SCALAR', 'AES', 'AVX512_VPCLMULQDQ_512', 'RDPRU', 'VPCLMULQDQ', 'CLZERO', 'AVX512F_512', 'AVX512BW_128', 'SNP', 'AVX512_BF16_128', '3DNOW', 'PPRO', 'AVX512CD_128', 'MPX', 'AVX512BW_256', 'AVX512_4FMAPS_512', 'LZCNT', 'AMD', 'CLFSH', 'VAES', 'XSAVEC', 'GFNI', 'AVX512_FP16_256', 'RDPID', 'PCONFIG', 'AMD_INVLPGB', 'AVX512_GFNI_256', 'AVX512DQ_128', 'AVX512_VBMI2_128', 'SMX', 'RDRAND', 'RDWRFSGS', 'AVX512DQ_512', 'PREFETCH_NOP', 'AVX512_VAES_128', 'KEYLOCKER_WIDE', 'AVX512_BITALG_128', 'I486REAL', 'AVX512F_128N', 'AVX512_VPOPCNTDQ_256', 'I386', 'WAITPKG', 'AVX512_VBMI_512', 'AVX', 'AVX512ER_512', 'SGX', 'LONGMODE', 'AVX512_VPCLMULQDQ_128', 'AVX512_VAES_512', 'SSEMXCSR', 'AMX_BF16', 'AVX512_VBMI2_512', 'AVX512DQ_SCALAR', 'AVX512_VBMI_128', 'RDPMC', 'SSSE3', 'PPRO_UD0_SHORT', 'HRESET', 'FXSAVE64', 'SSE3', 'AVX512_4VNNIW_512', 'ENQCMD', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_MONTMUL', 'SSE2MMX', 'FMA4', 'AVX512_IFMA_512', 'PCLMULQDQ', 'AVX512F_128', 'RTM', 'AVXAES', 'AVX512CD_512', 'AVX512_BITALG_256', 'F16C', 'ADOX_ADCX', 'AVX512_VBMI_256', 'SERIALIZE', 'AVX512_IFMA_128', 'SSE2', 'VTX', 'AMX_INT8', 'SSE4', 'PKU', 'CMPXCHG16B', 'CLWB', 'SHA', 'PPRO_UD0_LONG', 'FAT_NOP', 'FXSAVE', 'I486', 'BMI1', 'AVX2', 'LAHF', 'AVX512_FP16_128N', 'XSAVE', 'I286REAL', 'CET', 'AVX512ER_SCALAR', 'SGX_ENCLV', 'SMAP', 'AMX_TILE', 'CLFLUSHOPT', 'XSAVES', 'AVX512F_SCALAR', 'AVX512_VP2INTERSECT_512', 'AVX512_BF16_256', 'SSE', 'POPCNT', 'SSE3X87', 'AVX512F_256', 'RDSEED', 'AVX512DQ_128N', 'AVX512F_KOP', 'AVX512_BF16_512', 'AVX512_VPOPCNTDQ_512', 'MCOMMIT', 'PENTIUMREAL', 'SVM', 'I186', 'TDX', 'X87', 'I286PROTECTED', 'AVX512_VP2INTERSECT_128', 'AVX512_BITALG_512', 'AVX512_FP16_SCALAR', 'CMOV', 'AVX512_FP16_128', 'PTWRITE', 'FCMOV', 'AVX512DQ_256'} +FE:EMIT_FILE obj/xed-isa-set-enum.txt +FE:EMIT_FILE obj/xed-isa-set-enum.c +FE:EMIT_FILE obj/xed-isa-set-enum.h +FE:EMIT_FILE obj/xed-chip-features-table.c +FE:EMIT_FILE obj\include-private/xed-chip-features-table.h +Created files: obj/cdata.txt obj/xed-chip-enum.h obj/xed-chip-enum.c obj/xed-isa-set-enum.h obj/xed-isa-set-enum.c obj\include-private/xed-chip-features-table.h obj/xed-chip-features-table.c +FE:EMIT_FILE obj/xed-operand-convert-enum.txt +FE:EMIT_FILE obj/xed-operand-convert-enum.c +FE:EMIT_FILE obj/xed-operand-convert-enum.h +FE:EMIT_FILE obj/xed-convert-table-init.c +FE:EMIT_FILE obj/xed-convert-table-init.h +FE:EMIT_FILE obj/xed-operand-storage.h +FE:EMIT_FILE obj/xed-classifiers.c +[ILD_MODRM] alias search for map legacy_map1 opcode 0x4 +[ILD_MODRM] alias search for map legacy_map1 opcode 0xa +[ILD_MODRM] alias search for map legacy_map1 opcode 0xc +[ILD_MODRM] alias search for map legacy_map1 opcode 0xf +[ILD_MODRM] alias search for map legacy_map1 opcode 0x24 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x25 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x26 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x27 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x36 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x38 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x39 +[ILD_MODRM] alias search for map legacy_map1 opcode 0x3a +[ILD_MODRM] alias search for map legacy_map1 opcode 0x3b +[ILD_MODRM] alias search for map legacy_map1 opcode 0x3c +[ILD_MODRM] alias search for map legacy_map1 opcode 0x3d +[ILD_MODRM] alias search for map legacy_map1 opcode 0x3e +[ILD_MODRM] alias search for map legacy_map1 opcode 0x3f +[ILD_MODRM] alias search for map legacy_map1 opcode 0x7a +[ILD_MODRM] alias search for map legacy_map1 opcode 0x7b +[ILD_MODRM] alias search for map vex_map1 opcode 0x0 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x2 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x4 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x4 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x5 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x6 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x7 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0xa = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0xc = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xd +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xe +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xf +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0xf = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x18 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x19 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1a +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1b +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1c +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1d +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1e +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x1f +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x20 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_IGNORE_MOD +[ILD_MODRM] alias search for map vex_map1 opcode 0x21 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_IGNORE_MOD +[ILD_MODRM] alias search for map vex_map1 opcode 0x22 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_IGNORE_MOD +[ILD_MODRM] alias search for map vex_map1 opcode 0x23 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_IGNORE_MOD +[ILD_MODRM] alias search for map vex_map1 opcode 0x24 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x24 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x25 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x25 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x26 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x26 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x27 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x27 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x30 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x31 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x32 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x33 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x34 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x35 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x36 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x36 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x37 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x38 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x38 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x39 +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x39 = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3a +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x3a = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3b +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x3b = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3c +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x3c = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3d +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x3d = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3e +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x3e = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x3f +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x3f = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x40 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x43 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x48 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x49 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x4c +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x4d +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x4e +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x4f +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x78 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x79 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x7a +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x7a = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x7b +[ild_modrm] providing ild gap data for map legacy_map1 opcode 0x7b = XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x80 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x81 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x82 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x83 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x84 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x85 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x86 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x87 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x88 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x89 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8a +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8b +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8c +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8d +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8e +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x8f +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0x94 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x95 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x96 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x97 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9a +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9b +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9c +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9d +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9e +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0x9f +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa0 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa1 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa2 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa3 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa4 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa5 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa6 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_IGNORE_MOD +[ILD_MODRM] alias search for map vex_map1 opcode 0xa7 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_IGNORE_MOD +[ILD_MODRM] alias search for map vex_map1 opcode 0xa8 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xa9 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xaa +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xab +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xac +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xad +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xaf +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb0 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb1 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb2 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb3 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb4 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb5 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb6 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb7 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb8 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xb9 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xba +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xbb +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xbc +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xbd +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xbe +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xbf +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc0 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc1 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc3 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc7 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_TRUE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc8 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xc9 +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xca +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xcb +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xcc +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xcd +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xce +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xcf +[ILD_MODRM] --> supplied XED_ILD_HASMODRM_FALSE +[ILD_MODRM] alias search for map vex_map1 opcode 0xff +[ILD_MODRM] alias search for map legacy_map0 opcode 0xf +[ILD_MODRM] alias search for map legacy_map0 opcode 0x26 +[ILD_MODRM] alias search for map legacy_map0 opcode 0x2e +[ILD_MODRM] alias search for map legacy_map0 opcode 0x36 +[ILD_MODRM] alias search for map legacy_map0 opcode 0x3e +[ILD_MODRM] alias search for map legacy_map0 opcode 0x64 +[ILD_MODRM] alias search for map legacy_map0 opcode 0x65 +[ILD_MODRM] alias search for map legacy_map0 opcode 0x66 +[ILD_MODRM] alias search for map legacy_map0 opcode 0x67 +[ILD_MODRM] alias search for map legacy_map0 opcode 0xf0 +[ILD_MODRM] alias search for map legacy_map0 opcode 0xf2 +[ILD_MODRM] alias search for map legacy_map0 opcode 0xf3 +FE:EMIT_FILE obj/include-private/xed-ild-modrm.h +[ILD_MODRM] aliases supplied 110 +FE:EMIT_FILE obj/ild_eosz_debug.txt +FE:EMIT_FILE obj/ild_eosz_debug_header.txt +FE:EMIT_FILE obj/xed-ild-eosz.c +FE:EMIT_FILE obj/include-private/xed-ild-eosz.h +FE:EMIT_FILE obj/include-private/xed-ild-eosz-getters.h +FE:EMIT_FILE obj/ild_easz_debug.txt +FE:EMIT_FILE obj/ild_easz_debug_header.txt +FE:EMIT_FILE obj/xed-ild-easz.c +FE:EMIT_FILE obj/include-private/xed-ild-easz.h +FE:EMIT_FILE obj/include-private/xed-ild-easz-getters.h +FE:EMIT_FILE obj/xed-operand-accessors.h +FE:EMIT_FILE obj/xed-operand-accessors.c +FE:EMIT_FILE obj/xed-ild-imm-l3.c +FE:EMIT_FILE obj/include-private/xed-ild-imm-l3.h +FE:EMIT_FILE obj/include-private/xed-ild-imm-l2.h +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0xf6 map legacy_map0 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0xf7 map legacy_map0 +FE:EMIT_FILE obj/include-private/xed-ild-imm-l1.h +FE:EMIT_FILE obj/include-private/xed-ild-imm-bytes.h +FE:EMIT_FILE obj/xed-ild-disp-l3.c +FE:EMIT_FILE obj/include-private/xed-ild-disp-l3.h +FE:EMIT_FILE obj/include-private/xed-ild-disp-l2.h +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x80 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x81 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x82 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x83 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x84 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x85 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x86 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x87 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x88 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x89 map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x8a map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x8b map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x8c map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x8d map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x8e map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0x8f map legacy_map1 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0xc7 map legacy_map0 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0xe8 map legacy_map0 +[ILD_PARSER WARNING] generating by reg fun_dict for opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg0 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg1 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg2 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg3 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg4 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg5 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg6 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] BYREG resolving: No infos for reg7 opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] Failed to generate by reg fun_dict for opcode 0xe9 map legacy_map0 +[ILD_PARSER WARNING] generating by mode fun_dict for opcode 0xe9 map legacy_map0 +FE:EMIT_FILE obj/include-private/xed-ild-disp-l1.h +FE:EMIT_FILE obj/include-private/xed-ild-disp-bytes.h +[ALL ZEROS] VV=0 MAP=amd_xop8 +[ALL ZEROS] VV=0 MAP=amd_xop9 +[ALL ZEROS] VV=0 MAP=amd_xopA +[ALL ZEROS] VV=0 MAP=vex_map2 +[ALL ZEROS] VV=0 MAP=vex_map3 +[ALL ZEROS] VV=0 MAP=evex_map2 +[ALL ZEROS] VV=0 MAP=evex_map3 +[ALL ZEROS] VV=0 MAP=evex_map5 +[ALL ZEROS] VV=0 MAP=evex_map6 +[ALL ZEROS] VV=0 MAP=vex_map1 +[ALL ZEROS] VV=0 MAP=evex_map1 +FE:EMIT_FILE obj/include-private/xed3-phash-vv0.h +FE:EMIT_FILE obj/xed3-phash-lu-vv0.c +FE:EMIT_FILE obj/include-private/xed3-phash-lu-vv0.h +[ALL ZEROS] VV=1 MAP=legacy_map2 +[ALL ZEROS] VV=1 MAP=legacy_map3 +[ALL ZEROS] VV=1 MAP=amd_3dnow +[ALL ZEROS] VV=1 MAP=amd_xop8 +[ALL ZEROS] VV=1 MAP=amd_xop9 +[ALL ZEROS] VV=1 MAP=amd_xopA +[ALL ZEROS] VV=1 MAP=evex_map2 +[ALL ZEROS] VV=1 MAP=evex_map3 +[ALL ZEROS] VV=1 MAP=legacy_map1 +[ALL ZEROS] VV=1 MAP=evex_map5 +[ALL ZEROS] VV=1 MAP=evex_map6 +[ALL ZEROS] VV=1 MAP=evex_map1 +[ALL ZEROS] VV=1 MAP=legacy_map0 +FE:EMIT_FILE obj/include-private/xed3-phash-vv1.h +FE:EMIT_FILE obj/xed3-phash-lu-vv1.c +FE:EMIT_FILE obj/include-private/xed3-phash-lu-vv1.h +[ALL ZEROS] VV=2 MAP=legacy_map2 +[ALL ZEROS] VV=2 MAP=legacy_map3 +[ALL ZEROS] VV=2 MAP=amd_3dnow +[ALL ZEROS] VV=2 MAP=amd_xop8 +[ALL ZEROS] VV=2 MAP=amd_xop9 +[ALL ZEROS] VV=2 MAP=amd_xopA +[ALL ZEROS] VV=2 MAP=vex_map2 +[ALL ZEROS] VV=2 MAP=vex_map3 +[ALL ZEROS] VV=2 MAP=legacy_map1 +[ALL ZEROS] VV=2 MAP=vex_map1 +[ALL ZEROS] VV=2 MAP=legacy_map0 +FE:EMIT_FILE obj/include-private/xed3-phash-vv2.h +FE:EMIT_FILE obj/xed3-phash-lu-vv2.c +FE:EMIT_FILE obj/include-private/xed3-phash-lu-vv2.h +[ALL ZEROS] VV=3 MAP=legacy_map2 +[ALL ZEROS] VV=3 MAP=legacy_map3 +[ALL ZEROS] VV=3 MAP=amd_3dnow +[ALL ZEROS] VV=3 MAP=vex_map2 +[ALL ZEROS] VV=3 MAP=vex_map3 +[ALL ZEROS] VV=3 MAP=evex_map2 +[ALL ZEROS] VV=3 MAP=evex_map3 +[ALL ZEROS] VV=3 MAP=legacy_map1 +[ALL ZEROS] VV=3 MAP=evex_map5 +[ALL ZEROS] VV=3 MAP=evex_map6 +[ALL ZEROS] VV=3 MAP=vex_map1 +[ALL ZEROS] VV=3 MAP=evex_map1 +[ALL ZEROS] VV=3 MAP=legacy_map0 +FE:EMIT_FILE obj/include-private/xed3-phash-vv3.h +FE:EMIT_FILE obj/xed3-phash-lu-vv3.c +FE:EMIT_FILE obj/include-private/xed3-phash-lu-vv3.h +FE:EMIT_FILE obj/include-private/xed3-operand-lu.h +FE:EMIT_FILE obj/xed3-operand-lu.c +FE:EMIT_FILE obj/include-private/xed3-phash.h +FE:EMIT_FILE obj/include-private/xed3-nt-capture.h +FE:EMIT_FILE obj/include-private/xed3-chain-capture.h +FE:EMIT_FILE obj/include-private/xed3-chain-capture-lu.h +FE:EMIT_FILE obj/include-private/xed3-op-chain-capture.h +FE:EMIT_FILE obj/include-private/xed3-op-chain-capture-lu.h +FE:EMIT_FILE obj/include-private/xed3-dynamic-part1-capture.h +FE:EMIT_FILE obj/xed-ild-enum.c +FE:EMIT_FILE obj/xed-ild-enum.h +FE:EMIT_FILE obj/xed-mapu-enum.c +FE:EMIT_FILE obj/xed-mapu-enum.h +FE:EMIT_FILE obj\include-private/xed-map-feature-tables.h +FE:EMIT_FILE obj/xed-cpuid-bit-enum.txt +FE:EMIT_FILE obj/xed-cpuid-bit-enum.c +FE:EMIT_FILE obj/xed-cpuid-bit-enum.h +ISASET: INVALID +ISASET: 3DNOW +ISASET: 3DNOW_PREFETCH +ISASET: ADOX_ADCX +ISASET: AES +ISASET: AMD +ISASET: AMD_INVLPGB +ISASET: AMX_BF16 +ISASET: AMX_INT8 +ISASET: AMX_TILE +ISASET: AVX +ISASET: AVX2 +ISASET: AVX2GATHER +ISASET: AVX512BW_128 +ISASET: AVX512BW_128N +ISASET: AVX512BW_256 +ISASET: AVX512BW_512 +ISASET: AVX512BW_KOP +ISASET: AVX512CD_128 +ISASET: AVX512CD_256 +ISASET: AVX512CD_512 +ISASET: AVX512DQ_128 +ISASET: AVX512DQ_128N +ISASET: AVX512DQ_256 +ISASET: AVX512DQ_512 +ISASET: AVX512DQ_KOP +ISASET: AVX512DQ_SCALAR +ISASET: AVX512ER_512 +ISASET: AVX512ER_SCALAR +ISASET: AVX512F_128 +ISASET: AVX512F_128N +ISASET: AVX512F_256 +ISASET: AVX512F_512 +ISASET: AVX512F_KOP +ISASET: AVX512F_SCALAR +ISASET: AVX512PF_512 +ISASET: AVX512_4FMAPS_512 +ISASET: AVX512_4FMAPS_SCALAR +ISASET: AVX512_4VNNIW_512 +ISASET: AVX512_BF16_128 +ISASET: AVX512_BF16_256 +ISASET: AVX512_BF16_512 +ISASET: AVX512_BITALG_128 +ISASET: AVX512_BITALG_256 +ISASET: AVX512_BITALG_512 +ISASET: AVX512_FP16_128 +ISASET: AVX512_FP16_128N +ISASET: AVX512_FP16_256 +ISASET: AVX512_FP16_512 +ISASET: AVX512_FP16_SCALAR +ISASET: AVX512_GFNI_128 +ISASET: AVX512_GFNI_256 +ISASET: AVX512_GFNI_512 +ISASET: AVX512_IFMA_128 +ISASET: AVX512_IFMA_256 +ISASET: AVX512_IFMA_512 +ISASET: AVX512_VAES_128 +ISASET: AVX512_VAES_256 +ISASET: AVX512_VAES_512 +ISASET: AVX512_VBMI2_128 +ISASET: AVX512_VBMI2_256 +ISASET: AVX512_VBMI2_512 +ISASET: AVX512_VBMI_128 +ISASET: AVX512_VBMI_256 +ISASET: AVX512_VBMI_512 +ISASET: AVX512_VNNI_128 +ISASET: AVX512_VNNI_256 +ISASET: AVX512_VNNI_512 +ISASET: AVX512_VP2INTERSECT_128 +ISASET: AVX512_VP2INTERSECT_256 +ISASET: AVX512_VP2INTERSECT_512 +ISASET: AVX512_VPCLMULQDQ_128 +ISASET: AVX512_VPCLMULQDQ_256 +ISASET: AVX512_VPCLMULQDQ_512 +ISASET: AVX512_VPOPCNTDQ_128 +ISASET: AVX512_VPOPCNTDQ_256 +ISASET: AVX512_VPOPCNTDQ_512 +ISASET: AVXAES +ISASET: AVX_GFNI +ISASET: AVX_VNNI +ISASET: BMI1 +ISASET: BMI2 +ISASET: CET +ISASET: CLDEMOTE +ISASET: CLFLUSHOPT +ISASET: CLFSH +ISASET: CLWB +ISASET: CLZERO +ISASET: CMOV +ISASET: CMPXCHG16B +ISASET: ENQCMD +ISASET: F16C +ISASET: FAT_NOP +ISASET: FCMOV +ISASET: FMA +ISASET: FMA4 +ISASET: FXSAVE +ISASET: FXSAVE64 +ISASET: GFNI +ISASET: HRESET +ISASET: I186 +ISASET: I286PROTECTED +ISASET: I286REAL +ISASET: I386 +ISASET: I486 +ISASET: I486REAL +ISASET: I86 +ISASET: INVPCID +ISASET: KEYLOCKER +ISASET: KEYLOCKER_WIDE +ISASET: LAHF +ISASET: LONGMODE +ISASET: LWP +ISASET: LZCNT +ISASET: MCOMMIT +ISASET: MONITOR +ISASET: MONITORX +ISASET: MOVBE +ISASET: MOVDIR +ISASET: MPX +ISASET: PAUSE +ISASET: PCLMULQDQ +ISASET: PCONFIG +ISASET: PENTIUMMMX +ISASET: PENTIUMREAL +ISASET: PKU +ISASET: POPCNT +ISASET: PPRO +ISASET: PPRO_UD0_LONG +ISASET: PPRO_UD0_SHORT +ISASET: PREFETCHW +ISASET: PREFETCHWT1 +ISASET: PREFETCH_NOP +ISASET: PTWRITE +ISASET: RDPID +ISASET: RDPMC +ISASET: RDPRU +ISASET: RDRAND +ISASET: RDSEED +ISASET: RDTSCP +ISASET: RDWRFSGS +ISASET: RTM +ISASET: SERIALIZE +ISASET: SGX +ISASET: SGX_ENCLV +ISASET: SHA +ISASET: SMAP +ISASET: SMX +ISASET: SNP +ISASET: SSE +ISASET: SSE2 +ISASET: SSE2MMX +ISASET: SSE3 +ISASET: SSE3X87 +ISASET: SSE4 +ISASET: SSE42 +ISASET: SSE4A +ISASET: SSEMXCSR +ISASET: SSE_PREFETCH +ISASET: SSSE3 +ISASET: SSSE3MMX +ISASET: SVM +ISASET: TBM +ISASET: TDX +ISASET: TSX_LDTRK +ISASET: UINTR +ISASET: VAES +ISASET: VIA_PADLOCK_AES +ISASET: VIA_PADLOCK_MONTMUL +ISASET: VIA_PADLOCK_RNG +ISASET: VIA_PADLOCK_SHA +ISASET: VMFUNC +ISASET: VPCLMULQDQ +ISASET: VTX +ISASET: WAITPKG +ISASET: WBNOINVD +ISASET: X87 +ISASET: XOP +ISASET: XSAVE +ISASET: XSAVEC +ISASET: XSAVEOPT +ISASET: XSAVES +FE:EMIT_FILE obj/xed-cpuid-tables.c +FE: Closing an already-closed file: obj/xed-init-inst-table.c +FE:EMIT_FILE obj/xed-flags-simple.c +FE:EMIT_FILE obj/xed-flags-complex.c +FE:EMIT_FILE obj/xed-flags-actions.c +FE: Closing an already-closed file: obj/xed-operand-convert-init.c +FE: Closing an already-closed file: obj/xed-iclass-string.c +FE: Closing an already-closed file: obj/xed-iform-map-init.c +FE: Closing an already-closed file: obj/xed-init-inst-table-0.c +FE: Closing an already-closed file: obj/xed-attributes-init.c diff --git a/CodeVirtualizer/build/obj/DECGEN-OUTPUT-FILES.txt b/CodeVirtualizer/build/obj/DECGEN-OUTPUT-FILES.txt new file mode 100644 index 0000000..7e9e242 --- /dev/null +++ b/CodeVirtualizer/build/obj/DECGEN-OUTPUT-FILES.txt @@ -0,0 +1,128 @@ +obj/xed-operand-ctype-enum.h +obj/xed-operand-ctype-map.h +obj/xed-reg-enum.h +obj/xed-reg-class-enum.h +obj/xed-operand-width-enum.h +obj/xed-operand-element-type-enum.h +obj/xed-operand-element-xtype-enum.h +obj/xed-init-pointer-names.h +obj/xed-iclass-enum.h +obj/xed-iform-enum.h +obj/xed-iformfl-enum.h +obj/xed-exception-enum.h +obj/xed-nonterminal-enum.h +obj/xed-operand-enum.h +obj/xed-operand-type-enum.h +obj/xed-attribute-enum.h +obj/xed-category-enum.h +obj/xed-extension-enum.h +obj/xed-address-width-enum.h +obj/xed-error-enum.h +obj/xed-flag-action-enum.h +obj/xed-flag-enum.h +obj/xed-machine-mode-enum.h +obj/xed-operand-action-enum.h +obj/xed-operand-visibility-enum.h +obj/xed-reg-role-enum.h +obj/xed-syntax-enum.h +obj/xed-gen-table-defs.h +obj/xed-chip-enum.h +obj/xed-isa-set-enum.h +obj\include-private/xed-chip-features-table.h +obj/include-private/xed-ild-modrm.h +obj/include-private/xed-ild-eosz.h +obj/include-private/xed-ild-eosz-getters.h +obj/include-private/xed-ild-easz.h +obj/include-private/xed-ild-easz-getters.h +obj/include-private/xed-ild-imm-l3.h +obj/include-private/xed-ild-imm-l2.h +obj/include-private/xed-ild-imm-l1.h +obj/include-private/xed-ild-imm-bytes.h +obj/include-private/xed-ild-disp-l3.h +obj/include-private/xed-ild-disp-l2.h +obj/include-private/xed-ild-disp-l1.h +obj/include-private/xed-ild-disp-bytes.h +obj/include-private/xed3-phash-vv0.h +obj/include-private/xed3-phash-lu-vv0.h +obj/include-private/xed3-phash-vv1.h +obj/include-private/xed3-phash-lu-vv1.h +obj/include-private/xed3-phash-vv2.h +obj/include-private/xed3-phash-lu-vv2.h +obj/include-private/xed3-phash-vv3.h +obj/include-private/xed3-phash-lu-vv3.h +obj/include-private/xed3-operand-lu.h +obj/include-private/xed3-phash.h +obj/include-private/xed3-nt-capture.h +obj/include-private/xed3-chain-capture.h +obj/include-private/xed3-op-chain-capture.h +obj/include-private/xed3-dynamic-part1-capture.h +obj/xed-ild-enum.h +obj/xed-mapu-enum.h +obj\include-private/xed-map-feature-tables.h +obj/xed-cpuid-bit-enum.h +obj/xed-operand-ctype-enum.c +obj/xed-operand-ctype-map.c +obj/xed-reg-enum.c +obj/xed-reg-class-enum.c +obj/xed-init-reg-class.c +obj/xed-operand-width-enum.c +obj/xed-init-width.c +obj/xed-operand-element-type-enum.c +obj/xed-operand-element-xtype-enum.c +obj/xed-init-operand-type-mappings.c +obj/xed-init-pointer-names.c +obj/xed-iclass-enum.c +obj/xed-rep-map.c +obj/xed-iform-enum.c +obj/xed-iformfl-enum.c +obj/xed-iform-max.c +obj/xed-exception-enum.c +obj/xed-init-inst-table-data.c +obj/xed-init-operand-data.c +obj/xed-init-operand-sequences.c +obj/xed-attributes-list.c +obj/xed-nonterminal-enum.c +obj/xed-operand-enum.c +obj/xed-operand-type-enum.c +obj/xed-attribute-enum.c +obj/xed-category-enum.c +obj/xed-extension-enum.c +obj/xed-address-width-enum.c +obj/xed-error-enum.c +obj/xed-flag-action-enum.c +obj/xed-flag-enum.c +obj/xed-machine-mode-enum.c +obj/xed-operand-action-enum.c +obj/xed-operand-visibility-enum.c +obj/xed-reg-role-enum.c +obj/xed-syntax-enum.c +obj/xed-init-inst-table.c +obj/xed-flags-simple.c +obj/xed-flags-complex.c +obj/xed-flags-actions.c +obj/xed-operand-convert-init.c +obj/xed-iclass-string.c +obj/xed-iform-map-init.c +obj/xed-init-inst-table-0.c +obj/cdata.txt +obj/xed-chip-enum.c +obj/xed-isa-set-enum.c +obj/xed-chip-features-table.c +obj/xed-classifiers.c +obj/ild_eosz_debug.txt +obj/ild_eosz_debug_header.txt +obj/xed-ild-eosz.c +obj/ild_easz_debug.txt +obj/ild_easz_debug_header.txt +obj/xed-ild-easz.c +obj/xed-ild-imm-l3.c +obj/xed-ild-disp-l3.c +obj/xed3-phash-lu-vv0.c +obj/xed3-phash-lu-vv1.c +obj/xed3-phash-lu-vv2.c +obj/xed3-phash-lu-vv3.c +obj/xed3-operand-lu.c +obj/xed-ild-enum.c +obj/xed-mapu-enum.c +obj/xed-cpuid-bit-enum.c +obj/xed-cpuid-tables.c diff --git a/CodeVirtualizer/build/obj/ENC-ERR.txt b/CodeVirtualizer/build/obj/ENC-ERR.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/ENC-OUT.txt b/CodeVirtualizer/build/obj/ENC-OUT.txt new file mode 100644 index 0000000..49ce5cb --- /dev/null +++ b/CodeVirtualizer/build/obj/ENC-OUT.txt @@ -0,0 +1,83 @@ +LER: Comparing YMM0 and ZMM0 for XMM0 + taking new wider version +LER: Comparing YMM1 and ZMM1 for XMM1 + taking new wider version +LER: Comparing YMM2 and ZMM2 for XMM2 + taking new wider version +LER: Comparing YMM3 and ZMM3 for XMM3 + taking new wider version +LER: Comparing YMM4 and ZMM4 for XMM4 + taking new wider version +LER: Comparing YMM5 and ZMM5 for XMM5 + taking new wider version +LER: Comparing YMM6 and ZMM6 for XMM6 + taking new wider version +LER: Comparing YMM7 and ZMM7 for XMM7 + taking new wider version +LER: Comparing YMM8 and ZMM8 for XMM8 + taking new wider version +LER: Comparing YMM9 and ZMM9 for XMM9 + taking new wider version +LER: Comparing YMM10 and ZMM10 for XMM10 + taking new wider version +LER: Comparing YMM11 and ZMM11 for XMM11 + taking new wider version +LER: Comparing YMM12 and ZMM12 for XMM12 + taking new wider version +LER: Comparing YMM13 and ZMM13 for XMM13 + taking new wider version +LER: Comparing YMM14 and ZMM14 for XMM14 + taking new wider version +LER: Comparing YMM15 and ZMM15 for XMM15 + taking new wider version +LER: Comparing YMM0 and ZMM0 for YMM0 + taking new wider version +LER: Comparing YMM1 and ZMM1 for YMM1 + taking new wider version +LER: Comparing YMM2 and ZMM2 for YMM2 + taking new wider version +LER: Comparing YMM3 and ZMM3 for YMM3 + taking new wider version +LER: Comparing YMM4 and ZMM4 for YMM4 + taking new wider version +LER: Comparing YMM5 and ZMM5 for YMM5 + taking new wider version +LER: Comparing YMM6 and ZMM6 for YMM6 + taking new wider version +LER: Comparing YMM7 and ZMM7 for YMM7 + taking new wider version +LER: Comparing YMM8 and ZMM8 for YMM8 + taking new wider version +LER: Comparing YMM9 and ZMM9 for YMM9 + taking new wider version +LER: Comparing YMM10 and ZMM10 for YMM10 + taking new wider version +LER: Comparing YMM11 and ZMM11 for YMM11 + taking new wider version +LER: Comparing YMM12 and ZMM12 for YMM12 + taking new wider version +LER: Comparing YMM13 and ZMM13 for YMM13 + taking new wider version +LER: Comparing YMM14 and ZMM14 for YMM14 + taking new wider version +LER: Comparing YMM15 and ZMM15 for YMM15 + taking new wider version +[RGROUPS] ['BNDCFG', 'BNDSTAT', 'BOUND', 'CR', 'DR', 'FLAGS', 'GPR16', 'GPR32', 'GPR64', 'GPR8', 'GPR8h', 'INVALID', 'IP', 'MASK', 'MMX', 'MSR', 'MXCSR', 'PSEUDO', 'PSEUDOX87', 'SR', 'TMP', 'TREG', 'UIF', 'X87', 'XCR', 'XMM', 'YMM', 'ZMM'] +FE:EMIT_FILE obj/xed-enc-operand-lu.c +FE:EMIT_FILE obj\include-private/xed-enc-operand-lu.h +FE:EMIT_FILE obj/xed-encoder-order-init.c +FE:EMIT_FILE obj/xed-enc-groups.c +FE:EMIT_FILE obj\include-private/xed-enc-groups.h +FE:EMIT_FILE obj/xed-enc-patterns.c +FE:EMIT_FILE obj\include-private/xed-enc-patterns.h +FE:EMIT_FILE obj/xed-encoder-pattern-lu.c +FE:EMIT_FILE obj/xed-encoder-iforms-init.c +FE:EMIT_FILE obj/xed-encoder-init.c +FE:EMIT_FILE obj/xed-encoder-0.c +FE:EMIT_FILE obj/xed-encoder-1.c +FE:EMIT_FILE obj/xed-encoder-2.c +FE:EMIT_FILE obj/xed-encoder-3.c +FE:EMIT_FILE obj/xed-encoder-4.c +FE:EMIT_FILE obj\include-private/xed-encoder.h +FE:EMIT_FILE obj/xed-encoder-iforms.h +FE:EMIT_FILE obj/xed-encoder-gen-defs.h diff --git a/CodeVirtualizer/build/obj/ENCGEN-OUTPUT-FILES.txt b/CodeVirtualizer/build/obj/ENCGEN-OUTPUT-FILES.txt new file mode 100644 index 0000000..948d79e --- /dev/null +++ b/CodeVirtualizer/build/obj/ENCGEN-OUTPUT-FILES.txt @@ -0,0 +1,18 @@ +obj\include-private/xed-enc-operand-lu.h +obj/xed-enc-operand-lu.c +obj/xed-encoder-order-init.c +obj\include-private/xed-enc-groups.h +obj/xed-enc-groups.c +obj\include-private/xed-enc-patterns.h +obj/xed-enc-patterns.c +obj/xed-encoder-pattern-lu.c +obj/xed-encoder-iforms-init.c +obj/xed-encoder-init.c +obj\include-private/xed-encoder.h +obj/xed-encoder-0.c +obj/xed-encoder-1.c +obj/xed-encoder-2.c +obj/xed-encoder-3.c +obj/xed-encoder-4.c +obj/xed-encoder-iforms.h +obj/xed-encoder-gen-defs.h diff --git a/CodeVirtualizer/build/obj/all_constraints_vv0.txt b/CodeVirtualizer/build/obj/all_constraints_vv0.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/all_constraints_vv1.txt b/CodeVirtualizer/build/obj/all_constraints_vv1.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/all_constraints_vv2.txt b/CodeVirtualizer/build/obj/all_constraints_vv2.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/all_constraints_vv3.txt b/CodeVirtualizer/build/obj/all_constraints_vv3.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/cdata.txt b/CodeVirtualizer/build/obj/cdata.txt new file mode 100644 index 0000000..7803d73 --- /dev/null +++ b/CodeVirtualizer/build/obj/cdata.txt @@ -0,0 +1,849 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +I86 : + I86 LAHF +I86FP : + I86 LAHF X87 +I186 : + I186 I86 LAHF +I186FP : + I186 I86 LAHF X87 +I286REAL : + I186 I286REAL I86 LAHF + X87 +I286 : + I186 I286PROTECTED I286REAL I86 + LAHF X87 +I2186FP : + I186 I286PROTECTED I286REAL I86 + LAHF X87 +I386REAL : + I186 I286REAL I86 LAHF + X87 +I386 : + I186 I286PROTECTED I286REAL I386 + I86 LAHF X87 +I386FP : + I186 I286PROTECTED I286REAL I386 + I86 LAHF X87 +I486REAL : + I186 I286REAL I486REAL I86 + LAHF X87 +I486 : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + X87 +PENTIUMREAL : + I186 I286REAL I486REAL I86 + LAHF PENTIUMREAL X87 +PENTIUM : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMREAL X87 +QUARK : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMREAL X87 +PENTIUMMMXREAL : + I186 I286REAL I486REAL I86 + LAHF PENTIUMREAL RDPMC X87 +PENTIUMMMX : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMMMX PENTIUMREAL RDPMC X87 +ALLREAL : + I186 I286REAL I486REAL I86 + LAHF PENTIUMREAL RDPMC X87 +PENTIUMPRO : + CMOV FAT_NOP FCMOV I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF PENTIUMREAL + PPRO PPRO_UD0_SHORT PREFETCH_NOP RDPMC + X87 +PENTIUM2 : + CMOV FAT_NOP FCMOV FXSAVE + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMMMX PENTIUMREAL PPRO PREFETCH_NOP + RDPMC X87 +PENTIUM3 : + CMOV FAT_NOP FCMOV FXSAVE + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMMMX PENTIUMREAL PPRO PREFETCH_NOP + RDPMC SSE SSEMXCSR SSE_PREFETCH + X87 +PENTIUM4 : + CLFSH CMOV FAT_NOP FCMOV + FXSAVE I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF PAUSE PENTIUMMMX PENTIUMREAL + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + SSE SSE2 SSE2MMX SSEMXCSR + SSE_PREFETCH X87 +P4PRESCOTT : + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + MONITOR PAUSE PENTIUMMMX PENTIUMREAL + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSEMXCSR SSE_PREFETCH X87 +P4PRESCOTT_NOLAHF : + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LONGMODE MONITOR + PAUSE PENTIUMMMX PENTIUMREAL PPRO + PPRO_UD0_LONG PREFETCH_NOP RDPMC SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSEMXCSR SSE_PREFETCH X87 +P4PRESCOTT_VTX : + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + MONITOR PAUSE PENTIUMMMX PENTIUMREAL + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSEMXCSR SSE_PREFETCH VTX + X87 +MEROM : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL PPRO PPRO_UD0_LONG PREFETCH_NOP + RDPMC SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +PENRYN : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL PPRO PPRO_UD0_LONG PREFETCH_NOP + RDPMC SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VTX X87 +PENRYN_E : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL PPRO PPRO_UD0_LONG PREFETCH_NOP + RDPMC SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VTX X87 XSAVE +NEHALEM : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL POPCNT PPRO PPRO_UD0_LONG + PREFETCH_NOP RDPMC RDTSCP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +WESTMERE : + 3DNOW_PREFETCH AES CLFSH CMOV + CMPXCHG16B FAT_NOP FCMOV FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE MONITOR PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + RDTSCP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX VTX X87 +BONNELL : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR MOVBE PAUSE + PENTIUMMMX PENTIUMREAL PPRO PPRO_UD0_SHORT + PREFETCH_NOP RDPMC SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +SALTWELL : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR MOVBE PAUSE + PENTIUMMMX PENTIUMREAL PPRO PPRO_UD0_SHORT + PREFETCH_NOP RDPMC SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +SILVERMONT : + 3DNOW_PREFETCH AES CLFSH CMOV + CMPXCHG16B FAT_NOP FCMOV FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE MONITOR MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_SHORT PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDTSCP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX X87 +VIA : + VIA_PADLOCK_AES VIA_PADLOCK_MONTMUL VIA_PADLOCK_RNG VIA_PADLOCK_SHA +AMD_K10 : + 3DNOW 3DNOW_PREFETCH AES AMD + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + LZCNT MONITOR PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDTSCP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSE4A SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX SVM VTX + X87 +AMD_BULLDOZER : + 3DNOW_PREFETCH AES AMD AVX + AVXAES CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA4 + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LWP + LZCNT MONITOR PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDTSCP RDWRFSGS SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSE4A SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX SVM + VTX X87 XOP XSAVE + XSAVEOPT +AMD_PILEDRIVER : + 3DNOW_PREFETCH AES AMD AVX + AVXAES CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FMA4 FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + LWP LZCNT MONITOR PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPMC RDTSCP RDWRFSGS SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSE4A + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + SVM TBM VTX X87 + XOP XSAVE XSAVEOPT +AMD_ZEN : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AVX AVX2 AVX2GATHER AVXAES + BMI2 CLFLUSHOPT CLFSH CLZERO + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE LZCNT MONITOR MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSE4A SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX SVM TBM VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +AMD_ZENPLUS : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AVX AVX2 AVX2GATHER AVXAES + BMI2 CLFLUSHOPT CLFSH CLZERO + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE LZCNT MONITOR MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSE4A SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX SVM TBM VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +AMD_ZEN2 : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AVX AVX2 AVX2GATHER AVXAES + BMI2 CLFLUSHOPT CLFSH CLWB + CLZERO CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FMA FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE LZCNT MCOMMIT + MONITOR MONITORX MOVBE PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPID RDPMC RDPRU RDRAND + RDSEED RDTSCP RDWRFSGS SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSE4A SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX SVM TBM + VTX WBNOINVD X87 XSAVE + XSAVEC XSAVEOPT XSAVES +AMD_FUTURE : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AMD_INVLPGB AVX AVX2 AVX2GATHER + AVXAES BMI2 CLFLUSHOPT CLFSH + CLWB CLZERO CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LZCNT + MCOMMIT MONITOR MONITORX MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPID RDPMC RDPRU + RDRAND RDSEED RDTSCP RDWRFSGS + SHA SMAP SMX SNP + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSE4A + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + SVM TBM VTX WBNOINVD + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +GOLDMONT : + 3DNOW_PREFETCH AES CLFLUSHOPT CLFSH + CMOV CMPXCHG16B FAT_NOP FCMOV + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE MONITOR + MOVBE MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_SHORT PREFETCHW PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SHA SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +GOLDMONT_PLUS : + 3DNOW_PREFETCH AES CLFLUSHOPT CLFSH + CMOV CMPXCHG16B FAT_NOP FCMOV + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE MONITOR + MOVBE MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_SHORT PREFETCHW PREFETCH_NOP PTWRITE + RDPID RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SGX SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX VMFUNC VTX X87 + XSAVE XSAVEC XSAVEOPT XSAVES +TREMONT : + 3DNOW_PREFETCH AES CLFLUSHOPT CLFSH + CLWB CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 GFNI + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR MOVBE MPX + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_SHORT PREFETCHW + PREFETCH_NOP PTWRITE RDPID RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SHA SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +SNOW_RIDGE : + 3DNOW_PREFETCH AES CLDEMOTE CLFLUSHOPT + CLFSH CLWB CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + GFNI I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE MONITOR MOVBE + MOVDIR MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_SHORT PREFETCHW PREFETCH_NOP PTWRITE + RDPID RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX WAITPKG X87 + XSAVE XSAVEC XSAVEOPT XSAVES +SANDYBRIDGE : + 3DNOW_PREFETCH AES AVX AVXAES + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + MONITOR PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL POPCNT PPRO PPRO_UD0_LONG + PREFETCH_NOP RDPMC RDTSCP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 XSAVE XSAVEOPT +IVYBRIDGE : + 3DNOW_PREFETCH AES AVX AVXAES + CLFSH CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCH_NOP RDPMC RDRAND + RDTSCP RDWRFSGS SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VTX X87 + XSAVE XSAVEOPT +HASWELL : + 3DNOW_PREFETCH AES AVX AVX2 + AVX2GATHER AVXAES BMI1 BMI2 + CLFSH CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FMA FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCH_NOP RDPMC RDRAND + RDTSCP RDWRFSGS RTM SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEOPT +BROADWELL : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES BMI1 + BMI2 CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 INVPCID LAHF LONGMODE + LZCNT MONITOR MOVBE PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPMC RDRAND RDSEED RDTSCP + RDWRFSGS RTM SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEOPT +SKYLAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES BMI1 + BMI2 CLFLUSHOPT CLFSH CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MPX PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL POPCNT PPRO PPRO_UD0_LONG + PREFETCHW PREFETCH_NOP RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SGX SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +COMET_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES BMI1 + BMI2 CLFLUSHOPT CLFSH CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MPX PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL PKU POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + RTM SGX SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEC + XSAVEOPT XSAVES +SKYLAKE_SERVER : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVXAES BMI1 + BMI2 CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 INVPCID + LAHF LONGMODE LZCNT MONITOR + MOVBE MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPMC RDRAND RDSEED RDTSCP + RDWRFSGS RTM SGX SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX X87 XSAVE + XSAVEC XSAVEOPT XSAVES +CASCADE_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_VNNI_128 AVX512_VNNI_256 + AVX512_VNNI_512 AVXAES BMI1 BMI2 + CLFLUSHOPT CLFSH CLWB CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MPX PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL PKU POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + RTM SGX SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEC + XSAVEOPT XSAVES +COOPER_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BF16_128 AVX512_BF16_256 + AVX512_BF16_512 AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 + AVXAES BMI1 BMI2 CLFLUSHOPT + CLFSH CLWB CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 INVPCID LAHF LONGMODE + LZCNT MONITOR MOVBE MPX + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + PKU POPCNT PPRO PPRO_UD0_LONG + PREFETCHW PREFETCH_NOP RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SGX SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +KNL : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512CD_512 AVX512ER_512 + AVX512ER_SCALAR AVX512F_128N AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512PF_512 AVXAES BMI1 + BMI2 CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHWT1 PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VTX X87 XSAVE XSAVEOPT +KNM : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512CD_512 AVX512ER_512 + AVX512ER_SCALAR AVX512F_128N AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512PF_512 AVX512_4FMAPS_512 AVX512_4FMAPS_SCALAR + AVX512_4VNNIW_512 AVX512_VPOPCNTDQ_512 AVXAES BMI1 + BMI2 CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHWT1 PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX X87 XSAVE + XSAVEOPT +CANNONLAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_IFMA_128 AVX512_IFMA_256 + AVX512_IFMA_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVXAES BMI1 BMI2 CLFLUSHOPT + CLFSH CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FMA FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID LAHF LONGMODE LZCNT + MONITOR MOVBE MPX PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL PKU + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS RTM SGX + SHA SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +ICE_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BITALG_128 AVX512_BITALG_256 + AVX512_BITALG_512 AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 + AVX512_IFMA_128 AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 + AVX512_VAES_256 AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 + AVX512_VBMI2_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VPCLMULQDQ_128 + AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 + AVX512_VPOPCNTDQ_512 AVXAES AVX_GFNI BMI1 + BMI2 CLFLUSHOPT CLFSH CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 GFNI + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 INVPCID + LAHF LONGMODE LZCNT MONITOR + MOVBE PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL PKU POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPID + RDPMC RDRAND RDSEED RDTSCP + RDWRFSGS RTM SGX SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX VAES VMFUNC VPCLMULQDQ + VTX X87 XSAVE XSAVEC + XSAVEOPT XSAVES +ICE_LAKE_SERVER : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BITALG_128 AVX512_BITALG_256 + AVX512_BITALG_512 AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 + AVX512_IFMA_128 AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 + AVX512_VAES_256 AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 + AVX512_VBMI2_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VPCLMULQDQ_128 + AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 + AVX512_VPOPCNTDQ_512 AVXAES AVX_GFNI BMI1 + BMI2 CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + GFNI I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PCONFIG PENTIUMMMX PENTIUMREAL PKU + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPID RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SGX SGX_ENCLV SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VAES VMFUNC VPCLMULQDQ VTX + WBNOINVD X87 XSAVE XSAVEC + XSAVEOPT XSAVES +TIGER_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BITALG_128 AVX512_BITALG_256 + AVX512_BITALG_512 AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 + AVX512_IFMA_128 AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 + AVX512_VAES_256 AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 + AVX512_VBMI2_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VP2INTERSECT_128 + AVX512_VP2INTERSECT_256 AVX512_VP2INTERSECT_512 AVX512_VPCLMULQDQ_128 AVX512_VPCLMULQDQ_256 + AVX512_VPCLMULQDQ_512 AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 AVX512_VPOPCNTDQ_512 + AVXAES AVX_GFNI BMI1 BMI2 + CET CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + GFNI I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID KEYLOCKER KEYLOCKER_WIDE LAHF + LONGMODE LZCNT MONITOR MOVBE + MOVDIR PAUSE PCLMULQDQ PCONFIG + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPID RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS RTM SGX + SGX_ENCLV SHA SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VAES + VMFUNC VPCLMULQDQ VTX WBNOINVD + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +ALDER_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES AVX_GFNI + AVX_VNNI BMI1 BMI2 CET + CLDEMOTE CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + GFNI HRESET I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 INVPCID KEYLOCKER KEYLOCKER_WIDE + LAHF LONGMODE LZCNT MONITOR + MOVBE MOVDIR PAUSE PCLMULQDQ + PCONFIG PENTIUMMMX PENTIUMREAL PKU + POPCNT PPRO PPRO_UD0_SHORT PREFETCHW + PREFETCH_NOP PTWRITE RDPID RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SERIALIZE SHA SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VAES + VMFUNC VPCLMULQDQ VTX WAITPKG + WBNOINVD X87 XSAVE XSAVEC + XSAVEOPT XSAVES +SAPPHIRE_RAPIDS : + 3DNOW_PREFETCH ADOX_ADCX AES AMX_BF16 + AMX_INT8 AMX_TILE AVX AVX2 + AVX2GATHER AVX512BW_128 AVX512BW_128N AVX512BW_256 + AVX512BW_512 AVX512BW_KOP AVX512CD_128 AVX512CD_256 + AVX512CD_512 AVX512DQ_128 AVX512DQ_128N AVX512DQ_256 + AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR AVX512F_128 + AVX512F_128N AVX512F_256 AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512_BF16_128 AVX512_BF16_256 AVX512_BF16_512 + AVX512_BITALG_128 AVX512_BITALG_256 AVX512_BITALG_512 AVX512_FP16_128 + AVX512_FP16_128N AVX512_FP16_256 AVX512_FP16_512 AVX512_FP16_SCALAR + AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 AVX512_IFMA_128 + AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 AVX512_VAES_256 + AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 AVX512_VBMI2_512 + AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 AVX512_VNNI_128 + AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VP2INTERSECT_128 AVX512_VP2INTERSECT_256 + AVX512_VP2INTERSECT_512 AVX512_VPCLMULQDQ_128 AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 + AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 AVX512_VPOPCNTDQ_512 AVXAES + AVX_GFNI AVX_VNNI BMI1 BMI2 + CET CLDEMOTE CLFLUSHOPT CLFSH + CLWB CMOV CMPXCHG16B ENQCMD + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 GFNI I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MOVDIR PAUSE PCLMULQDQ PCONFIG + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + PTWRITE RDPID RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SERIALIZE SGX SGX_ENCLV SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX TDX TSX_LDTRK UINTR + VAES VMFUNC VPCLMULQDQ VTX + WAITPKG WBNOINVD X87 XSAVE + XSAVEC XSAVEOPT XSAVES +FUTURE : + 3DNOW_PREFETCH ADOX_ADCX AES AMX_BF16 + AMX_INT8 AMX_TILE AVX AVX2 + AVX2GATHER AVX512BW_128 AVX512BW_128N AVX512BW_256 + AVX512BW_512 AVX512BW_KOP AVX512CD_128 AVX512CD_256 + AVX512CD_512 AVX512DQ_128 AVX512DQ_128N AVX512DQ_256 + AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR AVX512F_128 + AVX512F_128N AVX512F_256 AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512_BF16_128 AVX512_BF16_256 AVX512_BF16_512 + AVX512_BITALG_128 AVX512_BITALG_256 AVX512_BITALG_512 AVX512_FP16_128 + AVX512_FP16_128N AVX512_FP16_256 AVX512_FP16_512 AVX512_FP16_SCALAR + AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 AVX512_IFMA_128 + AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 AVX512_VAES_256 + AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 AVX512_VBMI2_512 + AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 AVX512_VNNI_128 + AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VP2INTERSECT_128 AVX512_VP2INTERSECT_256 + AVX512_VP2INTERSECT_512 AVX512_VPCLMULQDQ_128 AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 + AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 AVX512_VPOPCNTDQ_512 AVXAES + AVX_GFNI AVX_VNNI BMI1 BMI2 + CET CLDEMOTE CLFLUSHOPT CLFSH + CLWB CMOV CMPXCHG16B ENQCMD + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 GFNI I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MOVDIR PAUSE PCLMULQDQ PCONFIG + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + PTWRITE RDPID RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SERIALIZE SGX SGX_ENCLV SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX TDX TSX_LDTRK UINTR + VAES VMFUNC VPCLMULQDQ VTX + WAITPKG WBNOINVD X87 XSAVE + XSAVEC XSAVEOPT XSAVES diff --git a/CodeVirtualizer/build/obj/dgen/all-chip-models.txt b/CodeVirtualizer/build/obj/dgen/all-chip-models.txt new file mode 100644 index 0000000..f778a0b --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-chip-models.txt @@ -0,0 +1,817 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# This file is for defining sets of extensions implemented by various chips +# +# The first column is a chip name. It will become the source for the enum xed_chip_t XED_CHIP_* +# The rest of the columns are ISA extensions that that CHIP implements +# ALL_OF(x) is a macro that refers to the set defined previously for some chip x. +# NOT(y) is a macro that removes a specific ISA extension (processed last) + +I86: I86 LAHF +I86FP: I86 LAHF X87 + +I186: ALL_OF(I86) I186 + # BOUND, ENTER, INS/INSB/INSW, LEAVE, OUTS/OUTSB/OUTSW, POPA, PUSHA +I186FP: ALL_OF(I186) X87 + +I286REAL: ALL_OF(I186) I286REAL X87 +I286: ALL_OF(I286REAL) I286PROTECTED + # ARPL, CLTS, LAR, LGDT, LIDT, LLDT, LMSW, + # LOADALL(undoc), LSL, LTR, SGDT, SIDT,SLDT, SMSW, STR,VERR,VERW +I2186FP: ALL_OF(I286) X87 + +# 386 did not add any instr to real mode +I386REAL: ALL_OF(I286REAL) +I386: ALL_OF(I386REAL) ALL_OF(I286) I386 + # BSF, BSR, BT, BTC, BTR,BTS, CDQ, CMPSD,CWDE, INSD, IRET*, JECXZ, + # LFS, LGS,LSS, LOADALL(undoc), LODSD, LOOP, MOVSD + # MOVSX, OUTSD, POPAD POPFD, PUSHAD PUSHD PUSHFD, SCASD + # SETcc* SHLD, SHRD, STOSD +I386FP: ALL_OF(I386) X87 + +I486REAL: ALL_OF(I386REAL) I486REAL # BSWAP, CMPXCHG, CPUID, INVD, INVLPG, RSM,WBINVD,XADD +I486: ALL_OF(I486REAL) ALL_OF(I386) I486 X87 # RSM + +PENTIUMREAL: ALL_OF(I486REAL) PENTIUMREAL # CMPXCHG8B, RDMSR, RDTSC, WRMSR +PENTIUM: ALL_OF(PENTIUMREAL) ALL_OF(I486) +# Quark is PENTIUM ISA, but not Pentium implementation. +QUARK: ALL_OF(PENTIUM) + +PENTIUMMMXREAL: ALL_OF(PENTIUMREAL) RDPMC # P55C++ RDPMC +PENTIUMMMX: ALL_OF(PENTIUMMMXREAL) ALL_OF(PENTIUM) PENTIUMMMX # P55C++ + +ALLREAL: ALL_OF(PENTIUMMMXREAL) + +# P6, PentiumPro, PPRO: +# The SSE_PREFETCH were on P6 as fat NOPs, but XED only recognizes them on >=PENTIUM3 +PENTIUMPRO: ALL_OF(PENTIUM) PPRO PPRO_UD0_SHORT CMOV FCMOV RDPMC FAT_NOP PREFETCH_NOP # NO MMX (Orig P6) + # FCMOV*, CMOV*, RDPMC, SYSCALL, SYSENTER, SYSEXIT,SYSRET, UD2, F[U]COMI[P] + # note conflict with PENTIUM2 addition of SYSENTER/SYSEXIT + + +PENTIUM2: ALL_OF(PENTIUM) PENTIUMMMX PPRO CMOV FCMOV FAT_NOP RDPMC PREFETCH_NOP FXSAVE + # FXSAVE/FXRSTOR, SYSENTER,SYSEXIT P6 + +# we keep SSEMXCSR separate from SSE to accommodate chip-check for KNC +# which only implements LDMXCSR/STMXCSR from SSE. +# The SSE_PREFETCH came in as NOPs on P6/PPRO. innaccuracy... +PENTIUM3: ALL_OF(PENTIUM2) SSE SSEMXCSR SSE_PREFETCH # SSE(incl. ldmxcsr/stmxcsr) (KNI) + +# SSE2MMX is a several purely mmx instructions that came with SSE2 (PADDQ, PSUBQ, PMULUDQ). +# They are really part of SSE2. +PENTIUM4: ALL_OF(PENTIUM3) NOT(PPRO_UD0_SHORT) PPRO_UD0_LONG SSE2 SSE2MMX CLFSH PAUSE + +# MONITOR is (MONITOR and MWAIT) instructions +# SSE3X87 is two x87 instructions that came with SSE3. +P4PRESCOTT: ALL_OF(PENTIUM4) SSE3 SSE3X87 MONITOR LONGMODE CMPXCHG16B FXSAVE64 + +# Made a chip for the P4's that omit LAHF in 64b mode +P4PRESCOTT_NOLAHF: ALL_OF(P4PRESCOTT) NOT(LAHF) + +P4PRESCOTT_VTX: ALL_OF(P4PRESCOTT) VTX + +# SSSE3MMX is a a bunch of purely mmx instructions that came with SSSE3. +# They are really part of SSSE3. The 3DNOW_PREFETCH instr were nops. +# previously listed as CORE2 +MEROM: ALL_OF(P4PRESCOTT) VTX SSSE3 SSSE3MMX SMX 3DNOW_PREFETCH + +PENRYN: ALL_OF(MEROM) SSE4 +PENRYN_E: ALL_OF(PENRYN) XSAVE +NEHALEM: ALL_OF(PENRYN) SSE42 POPCNT RDTSCP +WESTMERE: ALL_OF(NEHALEM) AES PCLMULQDQ + +# ATOM +BONNELL: ALL_OF(MEROM) MOVBE NOT(SMX) NOT(PPRO_UD0_LONG) PPRO_UD0_SHORT +SALTWELL: ALL_OF(BONNELL) + +# PREFETCHW semantics added to PREFETCHW opcode but not subject +# to chip-check because of prior implementation as NOP. +SILVERMONT: ALL_OF(WESTMERE) MOVBE RDRAND PREFETCHW VMFUNC NOT(PPRO_UD0_LONG) PPRO_UD0_SHORT + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/xed-via-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# VIA CENTAUR CHIPS??? +#VIA: ALL_OF(P4PRESCOTT) VIA_PADLOCK_RNG VIA_PADLOCK_AES VIA_PADLOCK_SHA +VIA: VIA_PADLOCK_RNG VIA_PADLOCK_AES VIA_PADLOCK_SHA VIA_PADLOCK_MONTMUL + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +# This is based mostly on my read of the wikpedia page: +# https://en.wikipedia.org/wiki/Template:AMD_x86_CPU_features + +# FIXME: need a proper baseline for AMD_K10 as a starting point. I +# used WESTMERE to avoid TSX/RTM. + +# FIXME: not sure when LZCNT entered the picture + +# FIXME: guessing about F16C and RDWRFSGS + +AMD_K10: ALL_OF(WESTMERE) PREFETCHW 3DNOW 3DNOW_PREFETCH SSE4A AMD SVM PREFETCH_NOP LZCNT + + +AMD_BULLDOZER: ALL_OF(AMD_K10) \ + NOT(3DNOW) \ + FMA4 LWP XOP \ + AVX AVXAES XSAVE XSAVEOPT F16C RDWRFSGS + +AMD_PILEDRIVER: ALL_OF(AMD_BULLDOZER) TBM FMA + +AMD_ZEN: ALL_OF(AMD_PILEDRIVER) \ + NOT(FMA4) \ + NOT(LWP) \ + NOT(XOP) \ + AVX2 AVX2GATHER \ + BMI2 MOVBE ADOX_ADCX SHA \ + RDRAND RDSEED \ + SMAP XSAVEC XSAVES CLFLUSHOPT CLZERO + +AMD_ZENPLUS: ALL_OF(AMD_ZEN) + +# Guessing about MONITORX +AMD_ZEN2: ALL_OF(AMD_ZENPLUS) \ + WBNOINVD CLWB RDPID RDPRU MCOMMIT \ + MONITORX + +# Guessing +AMD_FUTURE: ALL_OF(AMD_ZEN2) \ + SNP \ + AMD_INVLPGB + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/glm/glm-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +GOLDMONT: ALL_OF(SILVERMONT) MPX SHA RDSEED RDWRFSGS \ + XSAVE XSAVEOPT XSAVEC XSAVES SMAP \ + CLFLUSHOPT + +GOLDMONT_PLUS: ALL_OF(GOLDMONT) PTWRITE RDPID SGX +# and UMIP but not instr for that + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tremont/tremont-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +TREMONT: ALL_OF(GOLDMONT_PLUS) CLWB GFNI NOT(SGX) + +SNOW_RIDGE: ALL_OF(TREMONT) WAITPKG MOVDIR CLDEMOTE NOT(SGX) + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SANDYBRIDGE: ALL_OF(WESTMERE) AVX AVXAES XSAVE XSAVEOPT + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/ivb-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +IVYBRIDGE: ALL_OF(SANDYBRIDGE) RDRAND F16C RDWRFSGS + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/hsw-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +HASWELL: ALL_OF(IVYBRIDGE) FMA BMI1 BMI2 LZCNT AVX2 AVX2GATHER INVPCID MOVBE VMFUNC RTM + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/bdw/bdw-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# PREFETCHW semantics added to PREFETCHW opcode but not subject +# to chip-check because of prior implementation as NOP +BROADWELL: ALL_OF(HASWELL) ADOX_ADCX RDSEED SMAP PREFETCHW + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/skl/skl-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SKYLAKE: ALL_OF(BROADWELL) MPX XSAVEC XSAVES SGX CLFLUSHOPT + +COMET_LAKE: ALL_OF(SKYLAKE) PKU + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/skx/skx-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +SKYLAKE_SERVER: ALL_OF(SKYLAKE) PKU \ + CLWB \ + AVX512F_512 \ + AVX512F_128 \ + AVX512F_128N \ + AVX512F_256 \ + AVX512F_KOP \ + AVX512F_SCALAR \ + AVX512BW_128 \ + AVX512BW_128N \ + AVX512BW_256 \ + AVX512BW_512 \ + AVX512BW_KOP \ + AVX512CD_128 \ + AVX512CD_256 \ + AVX512CD_512 \ + AVX512DQ_128 \ + AVX512DQ_128N \ + AVX512DQ_256 \ + AVX512DQ_512 \ + AVX512DQ_KOP \ + AVX512DQ_SCALAR + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/clx/clx-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# Cascade Lake (CLX) based on Coffee Lake CPU. +# Coffee Lake has same ISA as SKX. + +CASCADE_LAKE: ALL_OF(SKYLAKE_SERVER) \ + AVX512_VNNI_128 \ + AVX512_VNNI_256 \ + AVX512_VNNI_512 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cpx/cooper-lake-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + + +COOPER_LAKE: ALL_OF(CASCADE_LAKE) \ + AVX512_BF16_128 \ + AVX512_BF16_256 \ + AVX512_BF16_512 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# No HSW INVPCID, RTM, VMFUNC +# No BDW SMAP +KNL: ALL_OF(IVYBRIDGE) \ + AVX512F_SCALAR \ + AVX512F_KOP \ + AVX512F_512 \ + AVX512F_128N \ + AVX512CD_512 \ + AVX512ER_512 \ + AVX512ER_SCALAR \ + AVX512PF_512 \ + PREFETCHWT1 \ + ADOX_ADCX RDSEED FMA BMI1 BMI2 LZCNT AVX2 AVX2GATHER MOVBE + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knm/knm-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# VMFUNC was partially implmented on KNL but VMX was disabled. +KNM: ALL_OF(KNL) VMFUNC \ + AVX512_4VNNIW_512 \ + AVX512_4FMAPS_512 \ + AVX512_4FMAPS_SCALAR \ + AVX512_VPOPCNTDQ_512 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cnl/cnl-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +# CANNONLAKE does not have CLWB +CANNONLAKE: ALL_OF(SKYLAKE_SERVER) SHA \ + NOT(CLWB) \ + AVX512_IFMA_128 \ + AVX512_IFMA_256 \ + AVX512_IFMA_512 \ + AVX512_VBMI_128 \ + AVX512_VBMI_256 \ + AVX512_VBMI_512 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/icl/icl-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# NOT(HLE) but no HLE instr support. +ICE_LAKE: \ + ALL_OF(SKYLAKE_SERVER) \ + NOT(CLWB) \ + NOT(MPX) \ + RDPID \ + SHA \ + AVX512_IFMA_128 \ + AVX512_IFMA_256 \ + AVX512_IFMA_512 \ + AVX512_VBMI_128 \ + AVX512_VBMI_256 \ + AVX512_VBMI_512 \ + AVX512_VBMI2_128 \ + AVX512_VBMI2_256 \ + AVX512_VBMI2_512 \ + AVX512_BITALG_512 \ + AVX512_BITALG_256 \ + AVX512_BITALG_128 \ + AVX512_VPOPCNTDQ_128 \ + AVX512_VPOPCNTDQ_256 \ + AVX512_VPOPCNTDQ_512 \ + AVX512_GFNI_128 \ + AVX512_GFNI_256 \ + AVX512_GFNI_512 \ + AVX_GFNI \ + GFNI \ + AVX512_VAES_128 \ + AVX512_VAES_256 \ + AVX512_VAES_512 \ + VAES \ + AVX512_VPCLMULQDQ_128 \ + AVX512_VPCLMULQDQ_256 \ + AVX512_VPCLMULQDQ_512 \ + VPCLMULQDQ \ + AVX512_VNNI_128 \ + AVX512_VNNI_256 \ + AVX512_VNNI_512 + + +ICE_LAKE_SERVER: \ + ALL_OF(ICE_LAKE) \ + CLWB \ + SGX_ENCLV \ + PCONFIG \ + WBNOINVD + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tgl/tgl-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +TIGER_LAKE: \ + ALL_OF(ICE_LAKE_SERVER) \ + KEYLOCKER \ + KEYLOCKER_WIDE \ + CET \ + MOVDIR \ + AVX512_VP2INTERSECT_128 \ + AVX512_VP2INTERSECT_256 \ + AVX512_VP2INTERSECT_512 + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/adl/adl-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +# MKTME has no new instr +ALDER_LAKE: \ + ALL_OF(SNOW_RIDGE) \ + NOT(SGX_ENCLV) \ + NOT(MPX) \ + KEYLOCKER \ + KEYLOCKER_WIDE \ + CET \ + PCONFIG \ + INVPCID \ + SERIALIZE \ + AVX \ + AVX_VNNI \ + VPCLMULQDQ \ + VAES \ + F16C \ + AVXAES \ + PKU \ + FMA \ + BMI1 \ + BMI2 \ + AVX2 \ + AVX_GFNI \ + AVX2GATHER \ + ADOX_ADCX \ + LZCNT \ + WBNOINVD \ + HRESET + + + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/spr/spr-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +SAPPHIRE_RAPIDS: \ + ALL_OF(TIGER_LAKE) \ + NOT(KEYLOCKER) \ + NOT(KEYLOCKER_WIDE) \ + UINTR \ + PTWRITE \ + CLDEMOTE \ + ENQCMD \ + SERIALIZE \ + TSX_LDTRK \ + WAITPKG \ + AVX512_BF16_128 \ + AVX512_BF16_256 \ + AVX512_BF16_512 \ + AVX_VNNI \ + AMX_TILE \ + AMX_INT8 \ + AMX_BF16 \ + TDX \ + AVX512_BF16_128 \ + AVX512_BF16_256 \ + AVX512_BF16_512 \ + AVX512_FP16_128N \ + AVX512_FP16_128 \ + AVX512_FP16_256 \ + AVX512_FP16_512 \ + AVX512_FP16_SCALAR + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/future/future-chips.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# This is intentionally *completely* inaccurate but Intel is not +# saying which chips will have these instructions publicly at this +# time and I had to put the new instructions on some chip so I made +# somethign up. + +FUTURE: \ + ALL_OF(SAPPHIRE_RAPIDS) \ + TDX diff --git a/CodeVirtualizer/build/obj/dgen/all-conversion-table.txt b/CodeVirtualizer/build/obj/dgen/all-conversion-table.txt new file mode 100644 index 0000000..08a3410 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-conversion-table.txt @@ -0,0 +1,90 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-convert.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# empty file + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-strings.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ZEROSTR(XED_OPERAND_ZEROING):: +0 -> '' +1 -> '{z}' + +SAESTR(XED_OPERAND_SAE):: +0 -> '' +1 -> '{sae}' + +# AVX512 only has rounding with implied SAE +ROUNDC(XED_OPERAND_ROUNDC):: +0 -> '' +1 -> '{rne-sae}' +2 -> '{rd-sae}' +3 -> '{ru-sae}' +4 -> '{rz-sae}' + + +BCASTSTR(XED_OPERAND_BCAST):: +0 -> '' +1 -> '{1to16}' +2 -> '{4to16}' +3 -> '{1to8}' +4 -> '{4to8}' +5 -> '{1to8}' +6 -> '{4to8}' +7 -> '{2to16}' +8 -> '{2to8}' +9 -> '{8to16}' +10 -> '{1to4}' +11 -> '{1to2}' +12 -> '{2to4}' +13 -> '{1to4}' +14 -> '{1to8}' +15 -> '{1to16}' +16 -> '{1to32}' +17 -> '{1to16}' +18 -> '{1to32}' +19 -> '{1to64}' +20 -> '{2to4}' +21 -> '{2to8}' +22 -> '{1to2}' +23 -> '{1to2}' +24 -> '{1to4}' +25 -> '{1to8}' +26 -> '{1to2}' +27 -> '{1to4}' diff --git a/CodeVirtualizer/build/obj/dgen/all-cpuid.txt b/CodeVirtualizer/build/obj/dgen/all-cpuid.txt new file mode 100644 index 0000000..905b870 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-cpuid.txt @@ -0,0 +1,1428 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_XSAVE: xsave.1.0.ecx.26 osxsave.1.0.ecx.27 +XED_ISA_SET_AES: aes.1.0.ecx.25 + +XED_ISA_SET_CLFSH: clflush.1.0.edx.19 + +XED_ISA_SET_CMPXCHG16B: cmpxchg16b.1.0.ecx.13 + +XED_ISA_SET_FXSAVE: fxsave.1.0.edx.24 +XED_ISA_SET_FXSAVE64: fxsave.1.0.edx.24 intel64.80000001.0.edx.29 +XED_ISA_SET_I186: n/a +XED_ISA_SET_I286PROTECTED: n/a +XED_ISA_SET_I286REAL: n/a +XED_ISA_SET_I386: n/a +XED_ISA_SET_I486: n/a +XED_ISA_SET_I486REAL: n/a +XED_ISA_SET_I86: n/a + +XED_ISA_SET_LAHF: lahf.80000001.0.ecx.0 +XED_ISA_SET_LONGMODE: intel64.80000001.0.edx.29 + +XED_ISA_SET_MOVBE: movebe.1.0.ecx.22 +XED_ISA_SET_PAUSE: n/a +XED_ISA_SET_PCLMULQDQ: pclmulqdq.1.0.ecx.1 +XED_ISA_SET_PENTIUMMMX: n/a +XED_ISA_SET_PENTIUMREAL: n/a + +XED_ISA_SET_POPCNT: popcnt.1.0.ecx.23 +XED_ISA_SET_PPRO: n/a +XED_ISA_SET_PREFETCHW: prefetchw.80000001.0.ecx.8 + +XED_ISA_SET_PREFETCH_NOP: n/a +XED_ISA_SET_RDPMC: n/a +XED_ISA_SET_RDTSCP: rdtscp.80000001.0.edx.27 + +XED_ISA_SET_SMX: smx.1.0.ecx.6 +XED_ISA_SET_SSE: sse.1.0.edx.25 +XED_ISA_SET_SSE2: sse2.1.0.edx.26 +XED_ISA_SET_SSE2MMX: sse2.1.0.edx.26 +XED_ISA_SET_SSE3: sse3.1.0.ecx.0 +XED_ISA_SET_SSE3X87: sse3.1.0.ecx.0 +XED_ISA_SET_MONITOR: monitor.1.0.ecx.3 +XED_ISA_SET_SSE4: sse4.1.0.ecx.19 +XED_ISA_SET_SSE42: sse42.1.0.ecx.20 + +XED_ISA_SET_SSEMXCSR: sse.1.0.edx.25 +XED_ISA_SET_SSSE3: ssse3.1.0.ecx.9 +XED_ISA_SET_SSSE3MMX: ssse3.1.0.ecx.9 + + +XED_ISA_SET_VTX: vmx.1.0.ecx.5 +XED_ISA_SET_X87: n/a + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/cpuid-via-padlock.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_VIA_PADLOCK_RNG: via_padlock_rng.c0000001.0.edx.2 via_padlock_rng_en.c0000001.0.edx.3 +XED_ISA_SET_VIA_PADLOCK_AES: via_padlock_aes.c0000001.0.edx.6 via_padlock_aes_en.c0000001.0.edx.7 +XED_ISA_SET_VIA_PADLOCK_SHA: via_padlock_sha.c0000001.0.edx.10 via_padlock_sha_en.c0000001.0.edx.11 +XED_ISA_SET_VIA_PADLOCK_MONTMUL: via_padlock_pmm.c0000001.0.edx.12 via_padlock_pmm_en.c0000001.0.edx.13 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/cpuid-amd.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_AMD: n/a +XED_ISA_SET_3DNOW: n/a +XED_ISA_SET_SSE4A: sse4a.80000001.0.ecx.6 +XED_ISA_SET_SVM: n/a +XED_ISA_SET_MONITORX: monitorx.80000001.0.ecx.29 +XED_ISA_SET_RDPRU: rdpru.80000008.0.ebx.4 +XED_ISA_SET_MCOMMIT: mcommit.80000008.0.ebx.8 +XED_ISA_SET_SNP: snp.8000001f.0.eax.4 +XED_ISA_SET_AMD_INVLPGB: n/a ### amd_invlpgb.80000001.0.edx.XXX # 2020-04-29 not published yet + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XOP: n/a + XED_ISA_SET_TBM: n/a + XED_ISA_SET_FMA4: n/a + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_MPX: mpx.7.0.ebx.14 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_CET: cet.7.0.ecx.7 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdrand/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_RDRAND: rdrand.1.0.ecx.30 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sha/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_SHA: sha.7.0.ebx.29 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaveopt/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XSAVEOPT: xsaveopt.d.1.eax.0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaves/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XSAVES: xsaves.d.1.eax.3 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsavec/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_XSAVEC: xsavec.d.1.eax.1 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/clflushopt/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_CLFLUSHOPT: clflushopt.7.0.ebx.23 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdseed/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + 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except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_SMAP: smap.7.0.ebx.20 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_SGX: sgx.7.0.ebx.2 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdpid/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_RDPID: rdp.7.0.ecx.22 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pt/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_PTWRITE: intelpt.7.0.ebx.25 ptwrite.14.0.ebx.4 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_MOVDIR: movdiri.7.0.ecx.27 movdir64b.7.0.ecx.28 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_WAITPKG: waitpkg.7.0.ecx.5 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_CLDEMOTE: cldemote.7.0.ecx.25 + + +###FILE: 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in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_F16C: f16c.1.0.ecx.29 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# 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implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_CLWB: clwb.7.0.ebx.24 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vnni/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_VNNI_128: avx512_vnni.7.0.ecx.11 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_VNNI_256: avx512_vnni.7.0.ecx.11 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+#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512ER_512: avx512er.7.0.ebx.27 + XED_ISA_SET_AVX512ER_SCALAR: avx512er.7.0.ebx.27 + XED_ISA_SET_AVX512PF_512: avx512pf.7.0.ebx.26 + XED_ISA_SET_PREFETCHWT1: prefetchwt1.7.0.ecx.0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_4FMAPS_512: avx512_4fmaps.7.0.edx.3 +XED_ISA_SET_AVX512_4FMAPS_SCALAR: avx512_4fmaps.7.0.edx.3 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_4VNNIW_512: avx512_4vnniw.7.0.edx.2 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-512/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_VPOPCNTDQ_512: avx512_vpopcntdq.7.0.ecx.14 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512F_128: avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512F_128N: avx512f.7.0.ebx.16 + XED_ISA_SET_AVX512F_256: avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512F_512: avx512f.7.0.ebx.16 + XED_ISA_SET_AVX512F_KOP: avx512f.7.0.ebx.16 + XED_ISA_SET_AVX512F_SCALAR: avx512f.7.0.ebx.16 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512cd/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512CD_128: avx512cd.7.0.ebx.28 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512CD_256: avx512cd.7.0.ebx.28 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512CD_512: avx512cd.7.0.ebx.28 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512BW_128: avx512bw.7.0.ebx.30 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512BW_128N: avx512bw.7.0.ebx.30 + XED_ISA_SET_AVX512BW_256: avx512bw.7.0.ebx.30 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512BW_512: avx512bw.7.0.ebx.30 + XED_ISA_SET_AVX512BW_KOP: avx512bw.7.0.ebx.30 + + XED_ISA_SET_AVX512DQ_128: avx512dq.7.0.ebx.17 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512DQ_128N: avx512dq.7.0.ebx.17 + XED_ISA_SET_AVX512DQ_256: avx512dq.7.0.ebx.17 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512DQ_512: avx512dq.7.0.ebx.17 + XED_ISA_SET_AVX512DQ_KOP: avx512dq.7.0.ebx.17 + XED_ISA_SET_AVX512DQ_SCALAR: avx512dq.7.0.ebx.17 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512ifma/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512_IFMA_128: avx512ifma.7.0.ebx.21 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_IFMA_256: avx512ifma.7.0.ebx.21 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_IFMA_512: avx512ifma.7.0.ebx.21 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512vbmi/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX512_VBMI_128: avx512vbmi.7.0.ecx.1 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_VBMI_256: avx512vbmi.7.0.ecx.1 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_VBMI_512: avx512vbmi.7.0.ecx.1 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/wbnoinvd/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_WBNOINVD: wbnoinvd.80000008.0.ebx.9 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pconfig/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_PCONFIG : pconfig.7.0.edx.18 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/bitalg/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_BITALG_128: avx512_bitalg.7.0.ecx.12 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_BITALG_256: avx512_bitalg.7.0.ecx.12 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_BITALG_512: avx512_bitalg.7.0.ecx.12 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vbmi2/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_VBMI2_128: avx512_vbmi2.7.0.ecx.6 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_VBMI2_256: avx512_vbmi2.7.0.ecx.6 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_VBMI2_512: avx512_vbmi2.7.0.ecx.6 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/cpuid-sse.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_GFNI: gfni.7.0.ecx.8 + +# could include aes.1.0.ecx.25 and avx.1.0.ecx.28. implied + XED_ISA_SET_VAES: vaes.7.0.ecx.9 # avx.1.0.ecx.28 + +# could include pclmulqdq.1.0.ecx.1 and avx.1.0.ecx.28. implied + XED_ISA_SET_VPCLMULQDQ: vpclmulqdq.7.0.ecx.10 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AVX_GFNI: gfni.7.0.ecx.8 avx.1.0.ecx.28 + XED_ISA_SET_AVX512_GFNI_128: gfni.7.0.ecx.8 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_GFNI_256: gfni.7.0.ecx.8 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_GFNI_512: gfni.7.0.ecx.8 avx512f.7.0.ebx.16 + + XED_ISA_SET_AVX512_VAES_128: vaes.7.0.ecx.9 aes.1.0.ecx.25 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_VAES_256: vaes.7.0.ecx.9 aes.1.0.ecx.25 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_VAES_512: vaes.7.0.ecx.9 aes.1.0.ecx.25 avx512f.7.0.ebx.16 + + XED_ISA_SET_AVX512_VPCLMULQDQ_128: vpclmulqdq.7.0.ecx.10 pclmulqdq.1.0.ecx.1 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_VPCLMULQDQ_256: vpclmulqdq.7.0.ecx.10 pclmulqdq.1.0.ecx.1 avx512f.7.0.ebx.16 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_VPCLMULQDQ_512: vpclmulqdq.7.0.ecx.10 pclmulqdq.1.0.ecx.1 avx512f.7.0.ebx.16 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-vl/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_VPOPCNTDQ_128: avx512_vpopcntdq.7.0.ecx.14 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_VPOPCNTDQ_256: avx512_vpopcntdq.7.0.ecx.14 avx512vl.7.0.ebx.31 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vp2intersect/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_AVX512_VP2INTERSECT_128: avx512_vp2intersect.7.0.edx.8 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_VP2INTERSECT_256: avx512_vp2intersect.7.0.edx.8 avx512vl.7.0.ebx.31 +XED_ISA_SET_AVX512_VP2INTERSECT_512: avx512_vp2intersect.7.0.edx.8 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/keylocker/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_KEYLOCKER: klsupported.7.0.ecx.23 klenabled.19.0.ebx.0 + XED_ISA_SET_KEYLOCKER_WIDE: klsupported.7.0.ecx.23 klwide.19.0.ebx.2 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hreset/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_HRESET: hreset.7.1.eax.22 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_AVX_VNNI: avx_vnni.7.1.eax.4 + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/uintr/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_UINTR : uintr.7.0.edx.5 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_AMX_TILE: amx_tiles.7.0.edx.24 + XED_ISA_SET_AMX_INT8: amx_tiles.7.0.edx.24 amx_int8.7.0.edx.25 + XED_ISA_SET_AMX_BF16: amx_tiles.7.0.edx.24 amx_bf16.7.0.edx.22 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/enqcmd/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XED_ISA_SET_ENQCMD: enqcmd.7.0.ecx.29 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tsx-ldtrk/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_TSX_LDTRK: tsx_ldtrk.7.0.edx.16 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/serialize/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XED_ISA_SET_SERIALIZE : serialize.7.0.edx.14 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tdx/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + XED_ISA_SET_TDX: n/a + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/cpuid.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + XED_ISA_SET_AVX512_FP16_128N: avx512_fp16.7.0.edx.23 + XED_ISA_SET_AVX512_FP16_128: avx512_fp16.7.0.edx.23 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_FP16_256: avx512_fp16.7.0.edx.23 avx512vl.7.0.ebx.31 + XED_ISA_SET_AVX512_FP16_512: avx512_fp16.7.0.edx.23 + XED_ISA_SET_AVX512_FP16_SCALAR: avx512_fp16.7.0.edx.23 + diff --git a/CodeVirtualizer/build/obj/dgen/all-dec-instructions.txt b/CodeVirtualizer/build/obj/dgen/all-dec-instructions.txt new file mode 100644 index 0000000..a710ee8 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-dec-instructions.txt @@ -0,0 +1,86770 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} + +{ +ICLASS : FCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP + +COMMENT : UNDOC DC D0..D7 is an undocumented alaias (see sandpile.org) +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FCOM_ST0_X87_DCD0 +} + + +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} + +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +COMMENT : UNDOC ALIASES +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FCOMP_ST0_X87_DCD1 + +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FCOMP_ST0_X87_DED0 +} + + +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem80real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP + +COMMENT : UNDOC ALIASES +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FSTP_X87_ST0_DFD0 + +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FSTP_X87_ST0_DFD1 +} + +{ +ICLASS : FSTPNCE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +COMMENT : UNDOC ALIASES - empty top of stack behavior differs from FSTP. +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} + + + +{ +ICLASS : FLDENV +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +# EOSZ=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +# EOSZ!=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDCW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mem16 REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNSTENV +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +# EOSZ=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +# EOSZ!=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNSTCW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87CONTROL:r:SUPP REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87PUSH:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXCH +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXCH +ATTRIBUTES: NOTSX +CPL : 3 +COMMENT : UNDOC ALIAS +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FXCH_ST0_X87_DFC1 + +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FXCH_ST0_X87_DDC1 +} + + + +{ +ICLASS : FNOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP X87_CONTROL NOTSX +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000] +OPERANDS : +} +{ +ICLASS : FCHS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FABS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FTST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXAM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDL2T +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDL2E +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDPI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDLG2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDLN2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDZ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : F2XM1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FYL2X +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPTAN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPATAN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXTRACT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPREM1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDECSTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110] +OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FINCSTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111] +OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FPREM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FYL2XP1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSQRT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSINCOS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FRNDINT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSCALE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSIN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVBE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVU +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOMPP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:rw:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNBE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNU +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNCLEX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010] +OPERANDS : REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNINIT +CPL : 3 +ATTRIBUTES : x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011] +OPERANDS : REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSETPM287_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100] +OPERANDS : +COMMENT : UNDOC +} +{ +ICLASS : FENI8087_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : +COMMENT : UNDOC +} +{ +ICLASS : FDISI8087_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001] +COMMENT : UNDOC +OPERANDS : +} + + +{ +ICLASS : FUCOMI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +ISA_SET : SSE3X87 +ATTRIBUTES : NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FRSTOR +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : x87_mmx_state_w X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +# EOSZ=1 +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +# EOSZ!=1 +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +} +{ +ICLASS : FNSAVE +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : x87_mmx_state_r x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP + +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FNSTSW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FFREE +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FIADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADDP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. faddp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FMULP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fmulp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FCOMPP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FSUBRP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fsubrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. + +} +{ +ICLASS : FSUBP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fsubp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FDIVRP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fdivrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. + +} +{ +ICLASS : FDIVP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fdivp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +ISA_SET : SSE3X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FBLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80dec REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FBSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem80dec REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FFREEP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP +COMMENT : UNDOC +} +{ +ICLASS : FNSTSW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : REG0=XED_REG_AX:w:IMPL REG1=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FUCOMIP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMIP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_LOCK_MEMb_IMMb_80r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_MEMb_IMMb_80r0 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : ADD_GPR8_IMMb_80r0 +} + + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_LOCK_MEMb_IMMb_80r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_MEMb_IMMb_80r1 +} + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : OR_GPR8_IMMb_80r1 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_LOCK_MEMb_IMMb_80r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_MEMb_IMMb_80r2 +} + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADC_GPR8_IMMb_80r2 +} + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_LOCK_MEMb_IMMb_80r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_MEMb_IMMb_80r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SBB_GPR8_IMMb_80r3 +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_LOCK_MEMb_IMMb_80r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_MEMb_IMMb_80r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : AND_GPR8_IMMb_80r4 +} + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_LOCK_MEMb_IMMb_80r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_MEMb_IMMb_80r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SUB_GPR8_IMMb_80r5 +} + + + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_LOCK_MEMb_IMMb_80r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_MEMb_IMMb_80r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : XOR_GPR8_IMMb_80r6 +} + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : CMP_MEMb_IMMb_80r7 + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : CMP_GPR8_IMMb_80r7 +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +} + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_LOCK_MEMb_IMMb_82r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_MEMb_IMMb_82r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADD_GPR8_IMMb_82r0 +} + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_LOCK_MEMb_IMMb_82r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_MEMb_IMMb_82r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : OR_GPR8_IMMb_82r1 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_LOCK_MEMb_IMMb_82r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_MEMb_IMMb_82r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADC_GPR8_IMMb_82r2 +} + + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_LOCK_MEMb_IMMb_82r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_MEMb_IMMb_82r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SBB_GPR8_IMMb_82r3 +} + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_LOCK_MEMb_IMMb_82r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_MEMb_IMMb_82r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : AND_GPR8_IMMb_82r4 +} + + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_LOCK_MEMb_IMMb_82r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_MEMb_IMMb_82r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SUB_GPR8_IMMb_82r5 +} + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_LOCK_MEMb_IMMb_82r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_MEMb_IMMb_82r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : XOR_GPR8_IMMb_82r6 +} + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : CMP_MEMb_IMMb_82r7 + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : CMP_GPR8_IMMb_82r7 +} + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:v IMM0:r:b:i8 + +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():r IMM0:r:b:i8 +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM() +OPERANDS : MEM0:w:v REG0=XED_REG_STACKPOP:r:spw:SUPP + +PATTERN : 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64() +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_STACKPOP:r:spw:SUPP +IFORM : POP_GPRv_8F +} + + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +# 2009-02-09: THIS WAS MISSING ENTIRELY UNTIL NOW +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : ROR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : ROR_GPR8_ONE +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : ROR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : ROR_GPRv_ONE +} + + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL + +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} + + + + + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : ROL_MEMb_ONE +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : ROL_GPR8_ONE +} + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : ROL_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : ROL_GPRv_ONE +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-mod ] # REMOVED cf-tst 2009-02-08 +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL + +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} + +################# + + + + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : SHL_MEMb_IMMb_C0r4 + +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : SHL_GPR8_IMMb_C0r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : SHL_MEMb_IMMb_C0r6 + +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : SHL_GPR8_IMMb_C0r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +IFORM : SHL_MEMv_IMMb_C1r4 + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +IFORM : SHL_GPRv_IMMb_C1r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +IFORM : SHL_MEMv_IMMb_C1r6 + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +IFORM : SHL_GPRv_IMMb_C1r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : RCL_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : RCL_GPR8_ONE +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : RCR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : RCR_GPR8_ONE +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHL_MEMb_ONE_D0r4 + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPR8_ONE_D0r4 + +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHL_MEMb_ONE_D0r6 + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPR8_ONE_D0r6 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHR_GPR8_ONE +} + +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SAR_MEMb_ONE +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SAR_GPR8_ONE +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : RCL_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : RCL_GPRv_ONE +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : RCR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : RCR_GPRv_ONE +} + +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHR_GPRv_ONE +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHL_MEMv_ONE_D1r6 + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPRv_ONE_D1r6 + +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHL_MEMv_ONE_D1r4 + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPRv_ONE_D1r4 +} + + +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SAR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SAR_GPRv_ONE +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMb_CL_D2r4 + +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPR8_CL_D2r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMb_CL_D2r6 + +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPR8_CL_D2r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMv_CL_D3r4 +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPRv_CL_D3r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMv_CL_D3r6 +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPRv_CL_D3r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : TEST_MEMb_IMMb_F6r0 + +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : TEST_MEMb_IMMb_F6r1 + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : TEST_GPR8_IMMb_F6r0 + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : TEST_GPR8_IMMb_F6r1 +} + +{ +ICLASS : NOT_LOCK +DISASM : not +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : NEG_LOCK +DISASM : neg +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP +} +{ +ICLASS : DIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP +} +{ +ICLASS : IDIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +IFORM : TEST_MEMv_IMMz_F7r0 + +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +IFORM : TEST_MEMv_IMMz_F7r1 + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +IFORM : TEST_GPRv_IMMz_F7r0 + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +IFORM : TEST_GPRv_IMMz_F7r1 +} +{ +ICLASS : NOT_LOCK +DISASM : not +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +} +{ +ICLASS : NEG_LOCK +DISASM : neg +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP +} +{ +ICLASS : DIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP +} +{ +ICLASS : IDIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP +} +{ +ICLASS : INC_LOCK +DISASM : inc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : DEC_LOCK +DISASM : dec +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : INC_LOCK +DISASM : inc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +IFORM : INC_GPRv_FFr0 +} +{ +ICLASS : DEC_LOCK +DISASM : dec +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +IFORM : DEC_GPRv_FFr1 +} + +{ +ICLASS : CALL_NEAR +DISASM_INTEL: call +DISASM_ATTSV: call +CPL : 3 +CATEGORY : CALL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK() +OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK() +OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP +} +{ +ICLASS : CALL_NEAR +DISASM_INTEL: call +DISASM_ATTSV: call +CPL : 3 +CATEGORY : CALL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0xE8 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP +PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64() +OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK() +OPERANDS : MEM0:r:v REG0=rIP():w:SUPP +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK() +OPERANDS : REG0=GPRv_B():r REG1=rIP():w:SUPP +} +{ +ICLASS : JMP_FAR +DISASM_INTEL: jmp far +DISASM_ATTSV: ljmp +CPL : 3 +ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:p2 REG0=rIP():w:SUPP +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM() +OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP + +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64() +OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP +IFORM : PUSH_GPRv_FFr6 +} +{ +ICLASS : SLDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_LDTR:r:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_LDTR:r:SUPP +} +{ +ICLASS : STR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_TR:r:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_TR:r:SUPP +} +{ +ICLASS : LLDT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_LDTR:w:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_LDTR:w:SUPP +} +{ +ICLASS : LTR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_TR:w:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_TR:w:SUPP +} +{ +ICLASS : VERR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:w +COMMENT : reads a selector +} +{ +ICLASS : VERR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR16_B():r +COMMENT : reads a selector +} +{ +ICLASS : VERW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:w +COMMENT : reads a selector +} +{ +ICLASS : VERW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR16_B():r +COMMENT : reads a selector +} +{ +ICLASS : LGDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored + +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() +OPERANDS : MEM0:r:s REG0=XED_REG_GDTR:w:SUPP +} +{ +ICLASS : SMSW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored + +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_CR0:r:SUPP +} +{ +ICLASS : SMSW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP +} +{ +ICLASS : LMSW +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_CR0:w:SUPP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_CR0:w:SUPP +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:r:v IMM0:r:b +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():r IMM0:r:b +} +{ +ICLASS : BTS_LOCK +DISASM : bts +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : BTR_LOCK +DISASM : btr +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : BTC_LOCK +DISASM : btc +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} + +# NOTE: VMXON and VMCLEAR almost conflict when there is a redundant 66 +# on VMXON. It should be (and is) a VMXON. VMCLEAR is required to +# "not have" f2/f3; osz_refining_prefix handles this. + +{ +ICLASS : VMCLEAR +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : VMPTRLD +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : VMPTRST +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:q +} + + +{ +ICLASS : VMXON +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: PROTECTED_MODE NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : CMPXCHG8B_LOCK +DISASM : cmpxchg8b +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +} +{ +ICLASS : CMPXCHG8B +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +} +{ +ICLASS : CMPXCHG16B_LOCK +DISASM : cmpxchg16b +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : LONGMODE +ISA_SET : CMPXCHG16B +ATTRIBUTES: REQUIRES_ALIGNMENT LOCKED +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP +} +{ +ICLASS : CMPXCHG16B +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : LONGMODE +ISA_SET : CMPXCHG16B +ATTRIBUTES: REQUIRES_ALIGNMENT LOCKABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP + +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():w IMM0:r:b +IFORM : MOV_GPR8_IMMb_C6r0 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP HLE_REL_ABLE +PATTERN : 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b IMM0:r:b +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():w IMM0:r:z +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : HLE_REL_ABLE +PATTERN : 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:w:v IMM0:r:z +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:i16 IMM0:r:b +} +{ +ICLASS : PSLLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b +} +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:i16 IMM0:r:b +} +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:i32 IMM0:r:b +} +{ +ICLASS : PSLLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b +} +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b +} +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:i32 IMM0:r:b +} +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b +} +{ +ICLASS : PSLLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b +} +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b +} +{ +ICLASS : PSRLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b +} +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b +} +{ +ICLASS : PSLLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b +} +{ +ICLASS : FXSAVE +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM() +OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP +} +{ +ICLASS : FXRSTOR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM() +OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP +} +{ +ICLASS : FXSAVE64 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE64 +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM() +OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP +} +{ +ICLASS : FXRSTOR64 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE64 +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM() +OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP +} + + + + + +{ +ICLASS : LDMXCSR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : SSEMXCSR +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP +} +{ +ICLASS : STMXCSR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : SSEMXCSR +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR_RD +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP +} +{ +ICLASS : PREFETCHNTA +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH NONTEMPORAL +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT0 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT1 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT2 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r0 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r1 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r2 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r3 + + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r4 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r4 + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r5 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r5 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r6 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r7 +} + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18r6 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r6 +} + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18r7 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r7 +} + + +{ +ICLASS : NOP +UNAME : NOP0F19 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F19 + +PATTERN : 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F19 +} +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F1A +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1A + +PATTERN : 0x0F 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A +} +{ +ICLASS : NOP +UNAME : NOP0F1B +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B +} +{ +ICLASS : NOP +UNAME : NOP0F1C +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C + +PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1C +} +{ +ICLASS : NOP +UNAME : NOP0F1D +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1D + +PATTERN : 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1D +} +{ +ICLASS : NOP +UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + +{ +ICLASS : NOP +UNAME : NOP0F1F +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1F +PATTERN : 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1F +} +{ +ICLASS : VMCALL +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix +OPERANDS : +} +{ +ICLASS : VMLAUNCH +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix +OPERANDS : +} +{ +ICLASS : VMRESUME +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix +OPERANDS : +} +{ +ICLASS : VMXOFF +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-mod pf-mod ] + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix +OPERANDS : +} +{ +ICLASS : SGDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:w:s64 REG0=XED_REG_GDTR:r:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:s REG0=XED_REG_GDTR:r:SUPP +} +{ +ICLASS : LIDT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: RING0 NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() +OPERANDS : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP +} +{ +ICLASS : MONITOR +CPL : 0 +CATEGORY : MISC +EXTENSION : MONITOR +ISA_SET : MONITOR +ATTRIBUTES: RING0 NOTSX + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16 +OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP +} +{ +ICLASS : MWAIT +CPL : 0 +CATEGORY : MISC +EXTENSION : MONITOR +ISA_SET : MONITOR +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP +} +{ +ICLASS : SIDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP +} +{ +ICLASS : SIDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP +} +{ +ICLASS : INVLPG +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION BYTEOP RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:b +} +{ +ICLASS : SWAPGS +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : LONGMODE +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64 +OPERANDS : +} +{ +ICLASS : RDTSCP +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : RDTSCP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_TSC:r:SUPP REG4=XED_REG_TSCAUX:r:SUPP +} +{ +ICLASS : SFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : CLFLUSH +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : CLFSH +ISA_SET : CLFSH +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : LFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE2 +ISA_SET : SSE2 +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : MFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE2 +ISA_SET : SSE2 +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : MOVHLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : MOVLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 +} +{ +ICLASS : MOVLHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : MOVHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : ADD_GPR8_GPR8_00 +} + + + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : ADD_GPRv_GPRv_01 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : ADD_GPR8_GPR8_02 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : ADD_GPRv_GPRv_03 +} + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x04 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x05 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x06 not64 +OPERANDS : REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x07 not64 +OPERANDS : REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : OR_GPR8_GPR8_08 +} + + + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : OR_GPRv_GPRv_09 +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : OR_GPR8_GPR8_0A +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : OR_GPRv_GPRv_0B +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x0C UIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x0D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0E not64 +OPERANDS : REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : ADC_GPR8_GPR8_10 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : ADC_GPRv_GPRv_11 +} + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : ADC_GPR8_GPR8_12 +} + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : ADC_GPRv_GPRv_13 +} + + + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x14 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x15 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x16 not64 +OPERANDS : REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x17 not64 +COMMENT : Inhibits all interrupts until after next instr +OPERANDS : REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : SBB_GPR8_GPR8_18 +} + + + + + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : SBB_GPRv_GPRv_19 +} + + +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : SBB_GPR8_GPR8_1A + +PATTERN : 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : SBB_GPRv_GPRv_1B + +PATTERN : 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1C SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x1E not64 +OPERANDS : REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x1F not64 +OPERANDS : REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : AND_GPR8_GPR8_20 +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : AND_GPRv_GPRv_21 +} + + + +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : AND_GPR8_GPR8_22 + +PATTERN : 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : AND_GPRv_GPRv_23 + +PATTERN : 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x24 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x25 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : DAA +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x27 not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP +} + + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : SUB_GPR8_GPR8_28 +} + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : SUB_GPRv_GPRv_29 +} + + + +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : SUB_GPR8_GPR8_2A +PATTERN : 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : SUB_GPRv_GPRv_2B + +PATTERN : 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2C SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : DAS +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x2F not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP +} + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : XOR_GPR8_GPR8_30 +} + + + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : XOR_GPRv_GPRv_31 +} + + + +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : XOR_GPR8_GPR8_32 + +PATTERN : 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : XOR_GPRv_GPRv_33 + +PATTERN : 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x34 UIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x35 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : AAA +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] +PATTERN : 0x37 not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=GPR8_R():r + +PATTERN : 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r +IFORM : CMP_GPR8_GPR8_38 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +PATTERN : 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : CMP_GPRv_GPRv_39 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():r MEM0:r:b +PATTERN : 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():r REG1=GPR8_B():r +IFORM : CMP_GPR8_GPR8_3A +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:v +PATTERN : 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():r REG1=GPRv_B():r +IFORM : CMP_GPRv_GPRv_3B +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3C SIMM8() +OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3D SIMMz() +OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z +} +{ +ICLASS : AAS +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] +PATTERN : 0x3F not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0b0100_0 SRM[rrr] not64 +OPERANDS : REG0=GPRv_SB():rw +IFORM : INC_GPRv_40 +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0b0100_1 SRM[rrr] not64 +OPERANDS : REG0=GPRv_SB():rw +IFORM : DEC_GPRv_48 +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b0101_0 SRM[rrr] DF64() +OPERANDS : REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:w:spw:SUPP +IFORM : PUSH_GPRv_50 +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b0101_1 SRM[rrr] DF64() +OPERANDS : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP +IFORM : POP_GPRv_58 +} +{ +ICLASS : PUSHA +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +# EOSZ=1 not64 +PATTERN : 0x60 mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP +PATTERN : 0x60 mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP +} +{ +ICLASS : PUSHAD +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I386 + # EOSZ=2 not64 +PATTERN : 0x60 mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP +PATTERN : 0x60 mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP +} +{ +ICLASS : POPA +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I186 +# EOSZ=1 not64 +PATTERN : 0x61 mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP +PATTERN : 0x61 mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP + +COMMENT : eSP value on the stack is ignored! 2008-08-14 +} +{ +ICLASS : POPAD +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I386 + # EOSZ=2 not64 +PATTERN : 0x61 mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP +PATTERN : 0x61 mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP + +COMMENT : eSP value on the stack is ignored! 2008-08-14 +} +{ +ICLASS : BOUND +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ATTRIBUTES: EXCEPTION_BR +ISA_SET : I186 +# EOSZ=1 +PATTERN : 0x62 mode16 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a16 +PATTERN : 0x62 mode32 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a16 +# EOSZ=2 +PATTERN : 0x62 mode16 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a32 +PATTERN : 0x62 mode32 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a32 +} +{ +ICLASS : ARPL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:rw:w REG0=GPR16_R():r +} +{ +ICLASS : ARPL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=GPR16_B():rw REG1=GPR16_R():r +} +{ +ICLASS : MOVSXD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : LONGMODE +COMMENT : Prescott reads 32b for the 16b version. My testing indicates Merom, Nehalem and later reference 16b \ + for the 16b version. I did not find an accessible Penryn. Oct 2017 (rev64) SDM documents modern behavior. \ + 2019 AMD docs say "mem32" and I am told AMD does reference 32b always. +PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:z +} +{ +ICLASS : MOVSXD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : LONGMODE +PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 +OPERANDS : REG0=GPRv_R():w REG1=GPRz_B():r +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x68 DF64() SIMMz() +OPERANDS : IMM0:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I186 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz() +OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:z + +PATTERN : 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x6A DF64() SIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I186 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8() +OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8 + +PATTERN : 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8 +} + + +{ +ICLASS : REP_INSB +DISASM : insb +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6C repe +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6C repne +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : INSB +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6C norep +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_INSW +DISASM : insw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D mode16 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode16 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : INSW +DISASM : insw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D mode16 no66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode32 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode64 norexw_prefix 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_INSD +DISASM : insd +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6D mode16 66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode64 rexw_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode16 66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode64 rexw_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : INSD +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D mode16 66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode32 no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode64 norexw_prefix no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP + +PATTERN : 0x6D mode64 rexw_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_OUTSB +DISASM : outsb +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6E repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6E repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : OUTSB +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6E norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : REP_OUTSW +DISASM : outsw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6F mode16 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + + +PATTERN : 0x6F mode16 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : OUTSW +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6F mode16 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode32 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : REP_OUTSD +DISASM : outsd +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6F mode16 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F mode64 rexw_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F mode16 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F mode64 rexw_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : OUTSD +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6F mode16 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode32 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP + +PATTERN : 0x6F mode64 rexw_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=GPR8_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw +} + + +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw +} + + +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 + +PATTERN : 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w REG1=GPR8_R():r +IFORM : MOV_GPR8_GPR8_88 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b REG0=GPR8_R():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : HLE_REL_ABLE +PATTERN : 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:v REG0=GPRv_R():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=GPRv_R():r +IFORM : MOV_GPRv_GPRv_89 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():w MEM0:r:b + +PATTERN : 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():w REG1=GPR8_B():r +IFORM : MOV_GPR8_GPR8_8A +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +IFORM : MOV_GPRv_GPRv_8B +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=SEG():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=SEG():r +} +{ +ICLASS : LEA +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT() +OPERANDS : REG0=GPRv_R():w AGEN:r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS +PATTERN : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=SEG_MOV():w MEM0:r:w +IFORM : MOV_SEG_MEMw +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS +PATTERN : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=SEG_MOV():w REG1=GPR16_B():r +IFORM : MOV_SEG_GPR16 +} + + + +{ +ICLASS : NOP +UNAME : NOP90 +CPL : 3 +CATEGORY : NOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : I86 +PATTERN : 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix +OPERANDS : +IFORM : NOP_90 +} +{ +ICLASS : PAUSE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : PAUSE +ISA_SET : PAUSE +PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1 +OPERANDS : +COMMENT : 2008-06-11 Ignores REX completely. Introduced on PENTIUM4 +} +{ +ICLASS : NOP +CPL : 3 +CATEGORY : NOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : I86 +PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0 +OPERANDS : +IFORM : NOP_90 +COMMENT : This is the encoding of PAUSE on pre-P4 systems + +} + +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 + +PATTERN : 0b1001_0 SRM[rrr] SRM!=0 +OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL + +# This is strange. REG0 is r8w, r8d or r8 depending on the EOSZ. mode64 +PATTERN : 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix +OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL +} +{ +ICLASS : CBW +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x98 mode16 no66_prefix +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +PATTERN : 0x98 mode32 66_prefix +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +PATTERN : 0x98 mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +} +{ +ICLASS : CDQE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : LONGMODE +PATTERN : 0x98 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RAX:w:SUPP REG1=XED_REG_EAX:r:SUPP +} +{ +ICLASS : CWDE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x98 mode16 66_prefix +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x98 mode32 no66_prefix +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x98 mode64 norexw_prefix no66_prefix +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +} +{ +ICLASS : CWD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x99 mode16 no66_prefix +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x99 mode32 66_prefix +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x99 mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +} +{ +ICLASS : CQO +CPL : 3 +CATEGORY : CONVERT +EXTENSION : LONGMODE +PATTERN : 0x99 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RDX:w:SUPP REG1=XED_REG_RAX:r:SUPP +} +{ +ICLASS : CDQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x99 mode16 66_prefix +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +PATTERN : 0x99 mode32 no66_prefix +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +PATTERN : 0x99 mode64 norexw_prefix no66_prefix +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +} + +{ +ICLASS : CALL_FAR +DISASM_INTEL : call far +DISASM_ATTSV : lcall +CPL : 3 +CATEGORY : CALL +ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH +EXTENSION : BASE +ISA_SET : I86 + +COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP +} + + +{ +ICLASS : CALL_FAR +DISASM_INTEL : call far +DISASM_ATTSV : lcall +CPL : 3 +CATEGORY : CALL +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 + +COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) + +PATTERN : 0x9A not64 BRDISPz() UIMM16() +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP +} + + +{ +ICLASS : FWAIT +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +PATTERN : 0x9B +OPERANDS : +} +{ +ICLASS : PUSHF +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] + # DF64() EOSZ=1 +PATTERN : 0x9C mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +PATTERN : 0x9C mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +PATTERN : 0x9C mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +} +{ +ICLASS : PUSHFD +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +# DF64() EOSZ=2 not64 +PATTERN : 0x9C mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP +PATTERN : 0x9C mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP +} +{ +ICLASS : PUSHFQ +CPL : 3 +CATEGORY : PUSH +EXTENSION : LONGMODE +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +# DF64() EOSZ=3 mode64 +PATTERN : 0x9C mode64 norexw_prefix no66_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP +PATTERN : 0x9C mode64 rexw_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP +} +{ +ICLASS : POPF +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +# DF64() EOSZ=1 +PATTERN : 0x9D mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +PATTERN : 0x9D mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +PATTERN : 0x9D mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +} +{ +ICLASS : POPFD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +# DF64() EOSZ=2 not64 +PATTERN : 0x9D mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP +PATTERN : 0x9D mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP +} +{ +ICLASS : POPFQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : LONGMODE +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] + # DF64() EOSZ=3 mode64 +PATTERN : 0x9D mode64 norexw_prefix no66_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP +PATTERN : 0x9D mode64 rexw_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP +} +{ +ICLASS : SAHF +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : LAHF +FLAGS : MUST [ sf-ah zf-ah af-ah pf-ah cf-ah ] +PATTERN : 0x9E +OPERANDS : REG0=XED_REG_AH:r:SUPP +} +{ +ICLASS : LAHF +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : LAHF +FLAGS : MUST [ sf-tst zf-tst af-tst pf-tst cf-tst ] +PATTERN : 0x9F +OPERANDS : REG0=XED_REG_AH:w:SUPP +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +PATTERN : 0xA0 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:w:IMPL MEM0:r:b SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xA1 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : REG0=OrAX():w:IMPL MEM0:r:v SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +PATTERN : 0xA2 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : MEM0:w:b REG0=XED_REG_AL:r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xA3 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : MEM0:w:v REG0=OrAX():r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} + + +{ +ICLASS : REP_MOVSB +DISASM : movsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 fixed_base1 BYTEOP +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA4 repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA4 repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA4 norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_MOVSW +DISASM : movsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 no66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 mode16 no66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : MOVSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 no66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode32 66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_MOVSD +DISASM : movsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 no66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 mode16 66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 no66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode32 no66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REP_MOVSQ +DISASM : movsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode64 rexw_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 mode64 rexw_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : MOVSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode64 rexw_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:q BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSB +DISASM : cmpsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA6 repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSB +DISASM : cmpsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA6 repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : CMPSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA6 norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSW +DISASM : cmpsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSW +DISASM : cmpsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : CMPSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA7 mode16 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode32 66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + + +{ +ICLASS : REPE_CMPSD +DISASM : cmpsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSD +DISASM : cmpsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + + +{ +ICLASS : CMPSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA7 mode16 66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode32 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSQ +DISASM : cmpsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode64 rexw_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSQ +DISASM : cmpsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode64 rexw_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : CMPSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xA7 mode64 rexw_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:q BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xA8 SIMM8() +OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xA9 SIMMz() +OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z +} + +{ +ICLASS : REP_STOSB +DISASM : stosb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAA repe +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAA repne +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAA norep +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP +} + + + +{ +ICLASS : REP_STOSW +DISASM : stosw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xAB mode16 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAB mode16 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode16 no66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +PATTERN : 0xAB mode32 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +PATTERN : 0xAB mode64 norexw_prefix 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +} + + + + +{ +ICLASS : REP_STOSD +DISASM : stosd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode16 66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAB mode16 66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode16 66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +PATTERN : 0xAB mode32 no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +PATTERN : 0xAB mode64 norexw_prefix no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +} + + + + +{ +ICLASS : REP_STOSQ +DISASM : stosq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode64 rexw_prefix repe +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 rexw_prefix repne +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode64 rexw_prefix norep +OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP +} + + + + +{ +ICLASS : REP_LODSB +DISASM : lodsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAC repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAC repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAC norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:w:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + + +{ +ICLASS : REP_LODSW +DISASM : lodsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAD mode16 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode32 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + + +{ +ICLASS : REP_LODSD +DISASM : lodsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAD mode16 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode32 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + +{ +ICLASS : REP_LODSQ +DISASM : lodsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode64 rexw_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 rexw_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode64 rexw_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:w:SUPP MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + +{ +ICLASS : REPE_SCASB +DISASM : scasb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAE repe +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASB +DISASM : scasb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAE repne +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : SCASB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAE norep +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:r:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASW +DISASM : scasw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xAF mode16 no66_prefix repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 66_prefix repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix 66_prefix repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASW +DISASM : scasw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xAF mode16 no66_prefix repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 66_prefix repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix 66_prefix repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF mode16 no66_prefix norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode32 66_prefix norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode64 norexw_prefix 66_prefix norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASD +DISASM : scasd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode16 66_prefix repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 no66_prefix repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix no66_prefix repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASD +DISASM : scasd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode16 66_prefix repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 no66_prefix repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix no66_prefix repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF mode16 66_prefix norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode32 no66_prefix norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode64 norexw_prefix no66_prefix norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASQ +DISASM : scasq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode64 rexw_prefix repe +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASQ +DISASM : scasq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode64 rexw_prefix repne +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF mode64 rexw_prefix norep +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:r:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b1011_0 SRM[rrr] UIMM8() +OPERANDS : REG0=GPR8_SB():w IMM0:r:b +# i had to come up with a partial nibble name +IFORM : MOV_GPR8_IMMb_B0 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b1011_1 SRM[rrr] UIMMv() +OPERANDS : REG0=GPRv_SB():w IMM0:r:v +} +{ +ICLASS : RET_NEAR +DISASM : ret +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xC2 DF64() UIMM16() IMMUNE66_LOOP64() +OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : RET_NEAR +DISASM : ret +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xC3 DF64() IMMUNE66_LOOP64() +OPERANDS : REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : LES +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_ES:w:SUPP +} +{ +ICLASS : LDS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_DS:w:SUPP +} +{ +ICLASS : ENTER +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +PATTERN : 0xC8 DF64() UIMM16() UIMM8_1() +OPERANDS : IMM0:r:w IMM1:r:b REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=OrBP():rw:SUPP +} +{ +ICLASS : LEAVE +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 +PATTERN : 0xC9 DF64() +# Ignoring STACKPOP semantics for LEAVE because it accesses memory at rBP because of +# the initial copy of rBP to rSP as part of the LEAVE's execution. +OPERANDS : MEM0:r:SUPP:v BASE0=ArBP():r:SUPP SEG0=FINAL_SSEG0():r:SUPP REG0=OrBP():rw:SUPP REG1=OrSP():rw:SUPP +} +{ +ICLASS : RET_FAR +DISASM_INTEL: ret far +DISASM_ATTSV: lcall +CPL : 3 +CATEGORY : RET +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +COMMENT : same privilege level does 2 pops (spw2). inter-privilege level does 4 (not represented) +PATTERN : 0xCA UIMM16() +OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : RET_FAR +DISASM_INTEL: ret far +DISASM_ATTSV: lcall +CPL : 3 +CATEGORY : RET +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xCB +OPERANDS : REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : INT3 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] +PATTERN : 0xCC +OPERANDS : REG0=rIP():w:SUPP +} +{ +ICLASS : INT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] +PATTERN : 0xCD UIMM8() +OPERANDS : IMM0:r:b REG0=rIP():w:SUPP +} +{ +ICLASS : INTO +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ] +PATTERN : 0xCE not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP +} +{ +ICLASS : IRET +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : IRETD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode64 norexw_prefix no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : IRETQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : LONGMODE +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF mode64 rexw_prefix +# FIXME: This is only an approximate width for the stack pops +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=XED_REG_RIP:w:SUPP +} +{ +ICLASS : AAM +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] +PATTERN : 0xD4 not64 UIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP +} +{ +ICLASS : AAD +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] +PATTERN : 0xD5 not64 UIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : SALC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-tst ] +PATTERN : 0xD6 not64 +OPERANDS : REG0=XED_REG_AL:w:SUPP +COMMENT : was undocumented, but added to SDM v3 under "undefined opcodes" in 2017 +} +{ +ICLASS : XLAT +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xD7 OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:b BASE0=ArBX():r:SUPP INDEX=XED_REG_AL:r:SUPP REG0=XED_REG_AL:w:SUPP SEG0=FINAL_DSEG():r:SUPP SCALE=1:r:SUPP +} + + +{ +ICLASS : LOOPNE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +PATTERN : 0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP + +COMMENT : REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC +PATTERN : 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} +{ +ICLASS : LOOPE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +PATTERN : 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP + +COMMENT : REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC +PATTERN : 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} + + + +{ +ICLASS : LOOP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xE2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} + +{ +ICLASS : JCXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0xE3 eamode16 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=XED_REG_IP:rw:SUPP +} +{ +ICLASS : JECXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0xE3 eamode32 not64 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EIP:rw:SUPP +PATTERN : 0xE3 eamode32 mode64 BRDISP8() FORCE64() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : JRCXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : LONGMODE +PATTERN : 0xE3 eamode64 BRDISP8() FORCE64() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=XED_REG_RIP:rw:SUPP +} + +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE4 UIMM8() +OPERANDS : REG0=XED_REG_AL:w:IMPL IMM0:r:b +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE5 UIMM8() IMMUNE_REXW() +OPERANDS : REG0=OeAX():w:IMPL IMM0:r:b +} + +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE6 UIMM8() +OPERANDS : IMM0:r:b REG0=XED_REG_AL:r:IMPL +} + +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE7 UIMM8() IMMUNE_REXW() +OPERANDS : IMM0:r:b REG0=OeAX():r:IMPL +} + +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xE9 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +PATTERN : 0xE9 mode64 FORCE64() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : JMP_FAR +DISASM_INTEL: jmp far +DISASM_ATTSV: ljmp +CPL : 3 +CATEGORY : UNCOND_BR +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xEA not64 BRDISPz() UIMM16() +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP +} +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xEB not64 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +PATTERN : 0xEB mode64 FORCE64() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEC +OPERANDS : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xED IMMUNE_REXW() +OPERANDS : REG0=OeAX():w:IMPL REG1=XED_REG_DX:r:IMPL +} +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEE +OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL +} +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEF IMMUNE_REXW() +OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=OeAX():r:IMPL +} +{ +ICLASS : INT1 +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xF1 +OPERANDS : REG0=rIP():w:SUPP +} +{ +ICLASS : HLT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ATTRIBUTES : RING0 NOTSX +ISA_SET : I86 +PATTERN : 0xF4 +OPERANDS : +} +{ +ICLASS : CMC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-tst cf-mod ] +PATTERN : 0xF5 +OPERANDS : +} +{ +ICLASS : CLC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-0 ] +PATTERN : 0xF8 +OPERANDS : +} +{ +ICLASS : STC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-1 ] +PATTERN : 0xF9 +OPERANDS : +} +{ +ICLASS : CLI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod iopl-tst if-mod ] +PATTERN : 0xFA +OPERANDS : +} +{ +ICLASS : STI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +COMMENT : Inhibits all interrupts until after next instr +FLAGS : MUST [ vif-mod iopl-tst if-mod ] +PATTERN : 0xFB +OPERANDS : +} +{ +ICLASS : CLD +ATTRIBUTES: NOTSX_COND +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ df-0 ] +PATTERN : 0xFC +OPERANDS : +} +{ +ICLASS : STD +ATTRIBUTES: NOTSX_COND +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ df-1 ] +PATTERN : 0xFD +OPERANDS : +} +{ +ICLASS : LAR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +COMMENT : LAR only sometimes writes its destination register. +PATTERN : 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:w +PATTERN : 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : LSL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:w + +PATTERN : 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRz_B():r +} +{ +ICLASS : SYSCALL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x05 mode64 FORCE64() +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:w:SUPP REG2=XED_REG_R11:w:SUPP +COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD +} +{ +ICLASS : CLTS +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x06 +OPERANDS : +} + +{ +ICLASS : SYSRET +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0x07 mode64 norexw_prefix +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ECX:r:SUPP +COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD +} +{ +ICLASS : SYSRET64 +DISASM : sysret +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x07 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:r:SUPP REG2=XED_REG_R11:r:SUPP +} + +{ +ICLASS : MOVUPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps + +PATTERN : 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +IFORM : MOVUPS_XMMps_XMMps_0F10 + +PATTERN : 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps + +PATTERN : 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps +IFORM : MOVUPS_XMMps_XMMps_0F11 +} +{ +ICLASS : MOVLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 +} +{ +ICLASS : UNPCKLPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq +PATTERN : 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:q +} +{ +ICLASS : UNPCKHPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq +PATTERN : 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:dq +} +{ +ICLASS : MOVHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 +} +{ +ICLASS : MOVSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:ss + +PATTERN : 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +IFORM : MOVSS_XMMss_XMMss_0F10 + +PATTERN : 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:ss REG0=XMM_R():r:ss + +PATTERN : 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:ss REG1=XMM_R():r:ss +IFORM : MOVSS_XMMss_XMMss_0F11 +} +{ +ICLASS : MOVSLDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVSHDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVUPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd + +PATTERN : 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +IFORM : MOVUPD_XMMpd_XMMpd_0F10 + +PATTERN : 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd + +PATTERN : 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd +IFORM : MOVUPD_XMMpd_XMMpd_0F11 +} +{ +ICLASS : MOVLPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:q +PATTERN : 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:sd +} +{ +ICLASS : UNPCKLPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq +PATTERN : 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q +} +{ +ICLASS : UNPCKHPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq +PATTERN : 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q +} +{ +ICLASS : MOVHPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:q +PATTERN : 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:sd +} +{ +ICLASS : MOVSD_XMM +DISASM : movsd +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:sd + +PATTERN : 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +IFORM : MOVSD_XMM_XMMsd_XMMsd_0F10 + +PATTERN : 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:sd REG0=XMM_R():r:sd + +PATTERN : 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:sd REG1=XMM_R():r:sd +IFORM : MOVSD_XMM_XMMsd_XMMsd_0F11 +} +{ +ICLASS : MOVDDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +PATTERN : 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +} + +{ +ICLASS : MOV_CR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 NOTSX +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=CR_R():w REG1=GPR32_B():r + +PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=CR_R():w REG1=GPR64_B():r +} + +{ +ICLASS : MOV_CR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=GPR32_B():w REG1=CR_R():r + +PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=GPR64_B():w REG1=CR_R():r +} + +{ +ICLASS : MOV_DR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 NOTSX +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=DR_R():w REG1=GPR32_B():r + +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=DR_R():w REG1=GPR64_B():r +} + +{ +ICLASS : MOV_DR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=GPR32_B():w REG1=DR_R():r + +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=GPR64_B():w REG1=DR_R():r +} + + +{ +ICLASS : WRMSR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x30 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:w:SUPP +} +{ +ICLASS : RDTSC +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +PATTERN : 0x0F 0x31 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_TSC:r:SUPP +} +{ +ICLASS : RDMSR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x32 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP +} +{ +ICLASS : RDPMC +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : RDPMC +PATTERN : 0x0F 0x33 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP +} +{ +ICLASS : SYSENTER +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: PROTECTED_MODE NOTSX +FLAGS : MUST [ vm-0 rf-0 if-0 ] +PATTERN : 0x0F 0x34 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP +PATTERN : 0x0F 0x34 mode64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP +COMMENT : AMD does not document support for this in 64b mode +} +{ +ICLASS : SYSEXIT +CPL : 0 +CATEGORY : SYSRET +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x35 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP +PATTERN : 0x0F 0x35 mode64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RDX:r:SUPP +COMMENT : AMD does not document support for this in 64b mode +} +{ +ICLASS : CMOVO +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNO +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVB +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNB +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVZ +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNZ +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVBE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNBE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : MOVMSKPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:ps +} +{ +ICLASS : SQRTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : RSQRTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : RCPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ANDPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : ANDNPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : ORPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : XORPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : SQRTSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : RSQRTSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : RCPSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MOVMSKPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:pd +} +{ +ICLASS : SQRTPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd +PATTERN : 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ANDPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : ANDNPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : ORPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : XORPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : SQRTSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:sd +PATTERN : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +} +{ +ICLASS : PUNPCKLBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u8 MEM0:r:d:u8 + +PATTERN : 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u8 REG1=MMX_B():r:d:u8 +} +{ +ICLASS : PUNPCKLWD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:d:u16 +PATTERN : 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:d:u16 +} +{ +ICLASS : PUNPCKLDQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:d:u32 +PATTERN : 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:d:u32 +} +{ +ICLASS : PACKSSWB +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PACKSSWB +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPGTB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +} +{ +ICLASS : PCMPGTB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PCMPGTW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PCMPGTW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPGTD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +} +{ +ICLASS : PCMPGTD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : PACKUSWB +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PACKUSWB +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PUNPCKLBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKLWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PACKSSWB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPGTB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PCMPGTW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPGTD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PACKUSWB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PSHUFW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():w:q:u16 MEM0:r:q:u16 IMM0:r:b +PATTERN : 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():w:q:u16 REG1=MMX_B():r:q:u16 IMM0:r:b +} +{ +ICLASS : PCMPEQB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +PATTERN : 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PCMPEQW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPEQD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +PATTERN : 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : EMMS +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : x87_mmx_state_w NOTSX +PATTERN : 0x0F 0x77 no_refining_prefix +OPERANDS : +} +{ +ICLASS : PSHUFD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b +PATTERN : 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b +} +{ +ICLASS : PCMPEQB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PCMPEQW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPEQD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PSHUFLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b +PATTERN : 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b +} +{ +ICLASS : PSHUFHW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b +PATTERN : 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b +} +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} + + +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP + +} +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP + +} +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + + +{ +ICLASS : SETO +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNO +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETB +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNB +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETZ +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNZ +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETBE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNBE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0F 0xA0 DF64() +OPERANDS : REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xA1 DF64() +OPERANDS : REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : CPUID +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I486REAL +PATTERN : 0x0F 0xA2 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_EBX:w:SUPP REG2=XED_REG_ECX:crw:SUPP REG3=XED_REG_EDX:w:SUPP +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +PATTERN : 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +} + +{ +ICLASS : CMPXCHG_LOCK +DISASM : cmpxchg +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP LOCKABLE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rcw REG1=GPR8_R():r REG2=XED_REG_AL:rcw:SUPP +} + + + +{ +ICLASS : CMPXCHG_LOCK +DISASM : cmpxchg +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=OrAX():rcw:SUPP +} + + + +{ +ICLASS : LSS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_SS:w:SUPP +} +{ +ICLASS : BTR_LOCK +DISASM : btr +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + +{ +ICLASS : LFS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_FS:w:SUPP +} +{ +ICLASS : LGS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_GS:w:SUPP +} +{ +ICLASS : MOVZX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:b +PATTERN : 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r +PATTERN : 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:w +PATTERN : 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r +} +{ +ICLASS : XADD_LOCK +DISASM : xadd +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw +} + + + +{ +ICLASS : XADD_LOCK +DISASM : xadd +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw +} + + +{ +ICLASS : CMPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +{ +ICLASS : MOVNTI +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : IGNORES_OSFXSR NOTSX NONTEMPORAL +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:d REG0=GPR32_R():r +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=GPR32_R():r +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=GPR64_R():r +} +{ +ICLASS : PINSRW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : NOTSX +PATTERN : 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b +PATTERN : 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b +} +{ +ICLASS : PEXTRW +EXCEPTIONS: mmx-nomem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:u16 IMM0:r:b +} +{ +ICLASS : SHUFPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +{ +ICLASS : CMPSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss IMM0:r:b +PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss IMM0:r:b +} +{ +ICLASS : CMPPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b +} +{ +ICLASS : PINSRW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b +PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b +} +{ +ICLASS : PEXTRW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : SHUFPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b +} +{ +ICLASS : CMPSD_XMM +DISASM : cmpsd +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd IMM0:r:b +PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd IMM0:r:b +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q +} +{ +ICLASS : PADDQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +ISA_SET : SSE2MMX +PATTERN : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64 +PATTERN : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64 +} +{ +ICLASS : PMULLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PMOVMSKB +EXCEPTIONS: mmx-nomem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : SSE +COMMENT : KNI on PentiumIII. MMX instructions intro'd w/SSE +PATTERN : 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:i8 +} +{ +ICLASS : ADDSUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + +{ +ICLASS : PADDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMULLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMOVMSKB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : MOVQ2DQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : MMX_EXCEPT NOTSX +PATTERN : 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=MMX_B():r:q:u64 +} +{ +ICLASS : ADDSUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVDQ2Q +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : MMX_EXCEPT NOTSX +PATTERN : 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=MMX_R():w:q:u64 REG1=XMM_B():r:q:u64 +} +{ +ICLASS : PAVGB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAVGB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q +} +{ +ICLASS : PAVGW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PAVGW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PMULHUW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q:u16 +} +{ +ICLASS : PMULHUW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q:u16 +} +{ +ICLASS : PMULHW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PMULHW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : MOVNTQ +EXCEPTIONS: mmx-nofp2 +ATTRIBUTES: NOTSX NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +} +{ +ICLASS : PAVGB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 +PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 +} + + +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:u64 +} +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:u64 +} + + + + +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:u64 +} +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:u64 +} + + + + +{ +ICLASS : PAVGW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 +PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 +} +{ +ICLASS : PMULHUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 +PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 +} +{ +ICLASS : PMULHW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : CVTTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : MOVNTDQ +ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq +} +{ +ICLASS : CVTDQ2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +COMMENT : ignores MXCSR. 32b int fits in f64 + +PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 +PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:i32 +} +{ +ICLASS : CVTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : PSLLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q +PATTERN : 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q +} +{ +ICLASS : PSLLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q +PATTERN : 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q +} +{ +ICLASS : PSLLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q +PATTERN : 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q +} +{ +ICLASS : PMULUDQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +ISA_SET : SSE2MMX +PATTERN : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32 +PATTERN : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q:u32 +} +{ +ICLASS : PMADDWD +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PSADBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : MASKMOVQ +EXCEPTIONS: mmx-nofp2 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL +PATTERN : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0() +OPERANDS : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq +} +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq +} + + + +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + + +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u64 MEM0:r:dq:u64 +} +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u64 REG1=XMM_B():r:dq:u64 +} + + + +{ +ICLASS : PMULUDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMADDWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PSADBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : MASKMOVDQU +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL +PATTERN : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} +{ +ICLASS : LDDQU +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : +PATTERN : 0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix +OPERANDS : REG0=XMM_R():w:pd MEM0:r:dq +} +{ +ICLASS : INVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x08 +OPERANDS : +} +{ +ICLASS : WBINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 +OPERANDS : +} +{ +ICLASS : UD0 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO_UD0_SHORT +ATTRIBUTES: NOTSX +COMMENT : Older processors (before NHM) did not take a MODRM byte sequence. Atom too. +PATTERN : 0x0F 0xFF MODE_SHORT_UD0=1 +OPERANDS : +} +{ +ICLASS : UD0 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO_UD0_LONG +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():r MEM0:r:d +PATTERN : 0x0F 0xFF MODE_SHORT_UD0=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : UD1 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():r MEM0:r:d +PATTERN : 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : UD2 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x0B +OPERANDS : +} +{ +ICLASS : MOVAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps + +PATTERN : 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +IFORM : MOVAPS_XMMps_XMMps_0F28 + +PATTERN : 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps + +PATTERN : 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps +IFORM : MOVAPS_XMMps_XMMps_0F29 +} + +{ +ICLASS : CVTPI2PS +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:q:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:q:f32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVNTPS +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:ps +} +{ +ICLASS : CVTTPS2PI +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 +PATTERN : 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : CVTPS2PI +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 +PATTERN : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : UCOMISS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss +PATTERN : 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss +} +{ +ICLASS : COMISS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss +PATTERN : 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss +} +{ +ICLASS : CVTSI2SS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:d:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=GPR32_B():r:d:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=GPR64_B():r:q:i32 +} +{ +ICLASS : CVTTSS2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : CVTSS2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : MOVAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd + +PATTERN : 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +IFORM : MOVAPD_XMMpd_XMMpd_0F28 + +PATTERN : 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd + +PATTERN : 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd +IFORM : MOVAPD_XMMpd_XMMpd_0F29 +} +{ +ICLASS : CVTPI2PD +EXCEPTIONS: mmx-nofp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES: MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVNTPD +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:pd +} +{ +ICLASS : CVTTPD2PI +EXCEPTIONS: mmx-fp-16align +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : CVTPD2PI +EXCEPTIONS: mmx-fp-16align +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : UCOMISD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd +PATTERN : 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd +} +{ +ICLASS : COMISD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd +PATTERN : 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd +} +{ +ICLASS : CVTSI2SD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:d:i32 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=GPR32_B():r:d:i32 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:q:i64 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=GPR64_B():r:q:i64 +} +{ +ICLASS : CVTTSD2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : CVTSD2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : CMOVS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : ADDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MULPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : CVTPS2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +ATTRIBUTES: MXCSR +PATTERN : 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:f32 +PATTERN : 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : CVTDQ2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : SUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MINPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : DIVPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MAXPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ADDSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MULSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : CVTSS2SD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : CVTTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 +PATTERN : 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 +} +{ +ICLASS : SUBSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MINSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : DIVSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MAXSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : ADDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MULPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : CVTPD2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : CVTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 +PATTERN : 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 +} +{ +ICLASS : SUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MINPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : DIVPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MAXPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MXCSR +PATTERN : 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ADDSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MULSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : CVTSD2SS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : SUBSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MINSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : DIVSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MAXSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : PUNPCKHBW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PUNPCKHWD +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PUNPCKHDQ +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PACKSSDW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +} +{ +ICLASS : PACKSSDW +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r + + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d +} +{ +ICLASS : MOVD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : NOTSX +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:d + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:d + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r + + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:d REG0=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d +} + + +{ +ICLASS : MOVQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : MOVQ_XMMdq_MEMq_0F6E + +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : MOVQ_MEMq_XMMq_0F7E + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +OPERANDS : REG0=GPR64_B():w REG1=XMM_R():r:q + +PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : MOVQ_MEMq_XMMq_0FD6 + +PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q +IFORM : MOVQ_XMMdq_XMMq_0FD6 + +PATTERN : 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : MOVQ_XMMdq_MEMq_0F7E + +PATTERN : 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +IFORM : MOVQ_XMMdq_XMMq_0F7E +} + + +{ +ICLASS : MOVQ +EXCEPTIONS: mmx-nofp2 # FIXME guessing here... +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +IFORM : MOVQ_MMXq_MEMq_0F6E + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +OPERANDS : REG0=MMX_R():w:q REG1=GPR64_B():r + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +IFORM : MOVQ_MEMq_MMXq_0F7E + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +OPERANDS : REG0=GPR64_B():w REG1=MMX_R():r:q + +PATTERN : 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +IFORM : MOVQ_MMXq_MEMq_0F6F + +PATTERN : 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +IFORM : MOVQ_MMXq_MMXq_0F6F + +PATTERN : 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +IFORM : MOVQ_MEMq_MMXq_0F7F + +PATTERN : 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_B():w:q REG1=MMX_R():r:q +IFORM : MOVQ_MMXq_MMXq_0F7F +} + +{ +ICLASS : PUNPCKHBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PACKSSDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PUNPCKLQDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHQDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : MOVDQU +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : MOVDQU_XMMdq_XMMdq_0F6F + +PATTERN : 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : MOVDQU_XMMdq_XMMdq_0F7F +} +{ +ICLASS : VMREAD +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +OPERANDS : MEM0:w:q REG0=GPR64_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +OPERANDS : REG0=GPR64_B():w REG1=GPR64_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +OPERANDS : MEM0:w:d REG0=GPR32_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +OPERANDS : REG0=GPR32_B():w REG1=GPR32_R():r +} +{ +ICLASS : VMWRITE +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:q + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +OPERANDS : REG0=GPR64_R():r REG1=GPR64_B():r + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:d + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : HADDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : HSUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MOVDQA +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : MOVDQA_XMMdq_XMMdq_0F7F + +PATTERN : 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : MOVDQA_XMMdq_XMMdq_0F6F +} +{ +ICLASS : HADDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : HSUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : SETS +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNS +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETP +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNP +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETL +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNL +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETLE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNLE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0F 0xA8 DF64() +OPERANDS : REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xA9 DF64() +OPERANDS : REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : RSM +CPL : 3 +CATEGORY : SYSRET +EXTENSION : BASE +ISA_SET : I486 +ATTRIBUTES: NOTSX +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xAA +OPERANDS : REG0=rIP():w:SUPP +} + +{ +ICLASS : BTS_LOCK +DISASM : bts +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + + + +{ +ICLASS : SHRD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b + +PATTERN : 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b +} +{ +ICLASS : SHRD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL + +PATTERN : 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL +} + +{ +ICLASS : SHLD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b + +PATTERN : 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b +} + +{ +ICLASS : SHLD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL + +PATTERN : 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL +} + +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v + +PATTERN : 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +} + +{ +ICLASS : BTC_LOCK +DISASM : btc +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + + +{ +ICLASS : BSF +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +COMMENT : replaced in the HSW builds +PATTERN : 0x0F 0xBC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +COMMENT : replaced in the HSW builds +PATTERN : 0x0F 0xBD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:b +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:w +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r +} +{ +ICLASS : BSWAP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I486REAL +PATTERN : 0x0F 0b1100_1 SRM[rrr] +OPERANDS : REG0=GPRv_SB():rw +} +{ +ICLASS : PSUBUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSUBUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSUBUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMINUB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMINUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PAND +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAND +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PADDUSB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PADDUSW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMAXUB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMAXUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PANDN +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PANDN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBUSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS : SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBUSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS : SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDUSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDUSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMINSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : POR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMAXSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PXOR +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : POR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +ISA_SET : SSE2MMX +PATTERN : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PADDD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMADDUBSW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PMADDUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT +PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PMULHRSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMULHRSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSHUFB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSHUFB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGNB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGNB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGNW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGNW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGND +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +EXCEPTIONS: mmx-mem +PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGND +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PALIGNR +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b +PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b +} +{ +ICLASS : PALIGNR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : PABSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PABSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PABSD +EXCEPTIONS: mmx-mem +CPL : 3 +ATTRIBUTES : simd_scalar NOTSX +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar NOTSX +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar REQUIRES_ALIGNMENT +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} + +#################################################################################### +{ +ICLASS : POPCNT +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : POPCNT +ATTRIBUTES: IGNORES_OSFXSR +# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix +# to get to the 16b form 32b and 64b modes. +FLAGS : MUST [ cf-0 zf-mod of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} +#################################################################################### +{ +ICLASS : PCMPGTQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +#################################################################################### +{ +ICLASS : CRC32 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +ATTRIBUTES : IGNORES_OSFXSR +# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix +# to get to the 16b form 32b and 64b modes. + +COMMENT: The dest min size is 32b, even for EOSZ 16b. + +# The byte-readers + +PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRy_R():rw:y MEM0:r:b +PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRy_R():rw:y REG1=GPR8_B():r:b + + +# The scalable readers + +PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRy_R():rw:y MEM0:r:v +PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRy_R():rw:y REG1=GPRv_B():r:v + +} + + + +{ +ICLASS : BLENDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b +} +{ +ICLASS : BLENDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b +} +#######################################################################33 +{ +ICLASS : BLENDVPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 REG1=XED_REG_XMM0:r:SUPP:dq:u64 + +PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 REG2=XED_REG_XMM0:r:SUPP:dq:u64 +} + +{ +ICLASS : BLENDVPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 REG1=XED_REG_XMM0:r:SUPP:dq:u32 + +PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 REG2=XED_REG_XMM0:r:SUPP:dq:u32 +} +#################################################################################### +{ +ICLASS : PCMPEQQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq + +PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +#################################################################################### +{ +ICLASS : DPPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2D +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b +} +{ +ICLASS : DPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2D +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b +} +#################################################################################### +{ +ICLASS : MOVNTDQA +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +#################################################################################### +{ +ICLASS : EXTRACTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:ps IMM0:r:b + +PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +#################################################################################### +{ +ICLASS : INSERTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:d IMM0:r:b + +PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +############################################################################ +{ +ICLASS : MPSADBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT +PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b +} +############################################################################ +{ +ICLASS : PACKUSDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 + +PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +############################################################################ +{ +ICLASS : PBLENDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PBLENDVB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq REG1=XED_REG_XMM0:r:dq:SUPP + +PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq REG2=XED_REG_XMM0:r:dq:SUPP +} +############################################################################ +{ +ICLASS : PEXTRB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b REG0=XMM_R():r:dq IMM0:r:b +# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? +PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PEXTRW_SSE4 +DISASM_INTEL: pextrw +DISASM_ATTSV: pextrw +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +# this one aliases with the SSE2 version so we made a new name + +PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:w REG0=XMM_R():r:dq IMM0:r:b +IFORM : PEXTRW_SSE4_MEMw_XMMdq_IMMb + +# this one aliases with the SSE2 version so we made a new name +PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq IMM0:r:b +IFORM : PEXTRW_SSE4_GPR32_XMMdq_IMMb +} + +############################################################################ +{ +ICLASS : PEXTRQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:q REG0=XMM_R():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PEXTRD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq IMM0:r:b +# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:b IMM0:r:b + +PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:d IMM0:r:b + +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:q IMM0:r:b + +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR64_B():r:q IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:q MEM0:r:q IMM0:r:b +PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:d MEM0:r:d IMM0:r:b +PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:d REG1=XMM_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PTEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +FLAGS : MUST [ cf-mod zf-mod of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq +} +############################################################################ +{ +ICLASS : PHMINPOSUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} + + +{ +ICLASS : PMAXSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXSD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + +{ +ICLASS : PMINSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINSD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + +{ +ICLASS : PMULLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMULDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + + +{ +ICLASS : PMOVSXBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 +PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 +} +{ +ICLASS : PMOVSXBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 +PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 +} +{ +ICLASS : PMOVSXBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 +PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 +} + +{ +ICLASS : PMOVSXWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 +PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 +} +{ +ICLASS : PMOVSXWQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 +PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 +} +{ +ICLASS : PMOVSXDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 +PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 +} + +{ +ICLASS : PMOVZXBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 +PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 +} +{ +ICLASS : PMOVZXBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 +PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 +} +{ +ICLASS : PMOVZXBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 +PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 +} + +{ +ICLASS : PMOVZXWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 +PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 +} +{ +ICLASS : PMOVZXWQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 +PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 +} +{ +ICLASS : PMOVZXDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 +PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 +} + + + + + + + +{ +ICLASS : PCMPESTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +# 64b eosz=2 +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP +} +{ +ICLASS : PCMPESTRI64 +DISASM : pcmpestri +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +# EOSZ=3 +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP +} +{ +ICLASS : PCMPISTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP +} +{ +ICLASS : PCMPISTRI64 +DISASM : pcmpistri +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP +} + +{ +ICLASS : PCMPESTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} +{ +ICLASS : PCMPESTRM64 +DISASM : pcmpestrm +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : PCMPISTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP +} +#################################################################################### +{ +ICLASS : XGETBV +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix +OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_EAX:w:SUPP REG3=XED_REG_XCR0:r:SUPP +} + +{ +ICLASS : XSETBV +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVE +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix +OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_XCR0:w:SUPP +} + + +{ +ICLASS : XSAVE +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} +{ +ICLASS : XRSTOR +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length load and conditional reg write +ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVE64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + +{ +ICLASS : XRSTOR64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length load and conditional reg write +ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + + +#################################################################################### + +{ +ICLASS : MOVBE +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MOVBE +COMMENT : Intro on Atom Silverthorne. Intercepted by Haswell. +# +# must allow 66 prefix. So "not_refning" gives us REFINING=0 which suffices to exclude F2/F3 prefixes. +# +PATTERN : 0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v +PATTERN : 0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:v REG0=GPRv_R():r +} + + +{ +ICLASS : GETSEC +CPL : 3 +CATEGORY : SYSTEM +ATTRIBUTES: PROTECTED_MODE NOTSX +EXTENSION : SMX +PATTERN : 0x0F 0x37 no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP REG1=XED_REG_EBX:r:SUPP +} + + +#################################################################################### +{ +ICLASS : AESKEYGENASSIST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b +} +{ +ICLASS : AESENC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESENCLAST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESDEC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESDECLAST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESIMC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +#################################################################################### +{ +ICLASS : PCLMULQDQ +CPL : 3 +CATEGORY : PCLMULQDQ +EXTENSION : PCLMULQDQ +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b +} + + +####################################################################### +{ +ICLASS : INVEPT +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES : RING0 NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : SDM rev 27 +} +{ +ICLASS : INVVPID +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES : RING0 NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : SDM rev 27 +} + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-amd-prefetch.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : NOP +UNAME : NOP0F0D_reg +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : PREFETCH_NOP +COMMENT : AMD 3DNOW prefetches that do not touch memory. This is the reg/reg form. + +PATTERN : 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F0D +} + +# The rest are all mem forms (MODRM.MOD!=3) + +{ +ICLASS : PREFETCH_EXCLUSIVE +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHW +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +COMMENT : was PREFETCH_MODIFIED, prefetch on >=broadwell and >=silvermont +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCHW_0F0Dr1 +} +{ +ICLASS : PREFETCH_RESERVED +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr2 +UNAME : PREFETCH_RESERVED_0F0Dr2 +} +{ +ICLASS : PREFETCHW +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +COMMENT : was PREFETCH_MODIFIED +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCHW_0F0Dr3 +} +{ +ICLASS : PREFETCH_RESERVED +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr4 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr5 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr6 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr7 +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/via-padlock-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : XSTORE +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_RNG +ISA_SET : VIA_PADLOCK_RNG +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] not_refining +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():r:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + +{ +ICLASS : REP_XSTORE +DISASM : xstore +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_RNG +ISA_SET : VIA_PADLOCK_RNG +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + +{ +ICLASS : REP_XCRYPTECB +DISASM : xcryptecb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + +{ +ICLASS : REP_XCRYPTCBC +DISASM : xcryptcbc +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REP_XCRYPTCTR +DISASM : xcryptctr +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} +{ +ICLASS : REP_XCRYPTCFB +DISASM : xcryptcfb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} +{ +ICLASS : REP_XCRYPTOFB +DISASM : xcryptofb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_XSHA1 +DISASM : xsha1 +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_SHA +ISA_SET : VIA_PADLOCK_SHA +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + +{ +ICLASS : REP_XSHA256 +DISASM : xsha256 +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_SHA +ISA_SET : VIA_PADLOCK_SHA +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + +{ +ICLASS : REP_MONTMUL +DISASM : montmul +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_MONTMUL +ISA_SET : VIA_PADLOCK_MONTMUL +ATTRIBUTES : REP FIXED_BASE0 +COMMENT : EAX output value undefined, so list as write. + +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP \ + REG1=XED_REG_ECX:rw:SUPP \ + REG2=XED_REG_EDX:w:SUPP \ + MEM0:rw:SUPP:pmmsz16 \ + BASE0=ArSI():r:SUPP \ + SEG0=FINAL_ESEG():r:SUPP + +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP \ + REG1=XED_REG_ECX:rw:SUPP \ + REG2=XED_REG_EDX:w:SUPP \ + MEM0:rw:SUPP:pmmsz32 \ + BASE0=ArSI():r:SUPP \ + SEG0=FINAL_ESEG():r:SUPP +} + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-3dnow.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : FEMMS +CPL : 3 +CATEGORY : MMX +EXTENSION : 3DNOW +ATTRIBUTES : x87_mmx_state_w AMDONLY +PATTERN : 0x0F 0x0E +OPERANDS : +} +{ +ICLASS : PI2FW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PI2FW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PI2FD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PI2FD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PF2IW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PF2IW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PF2ID +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PF2ID +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFPNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFPNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPGE +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPGE +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMIN +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMIN +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCP +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCP +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRSQRT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRSQRT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSUB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSUB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFADD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFADD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPGT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPGT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMAX +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMAX +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCPIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCPIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRSQIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRSQIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSUBR +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSUBR +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPEQ +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPEQ +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMUL +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMUL +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCPIT2 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCPIT2 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMULHRW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMULHRW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSWAPD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSWAPD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PAVGUSB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAVGUSB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-base.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# file: xed-amd-base.txt + +INSTRUCTIONS():: +# SYSCALL and SYSRET are supported in 32b mode only on AMD chips + +{ +ICLASS : SYSCALL_AMD +DISASM : syscall +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : BASE +ISA_SET : AMD +ATTRIBUTES : AMDONLY +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x05 not64 IGNORE66() +OPERANDS : REG0=rIP():w:SUPP +} + + +{ +ICLASS : SYSRET_AMD +DISASM : sysret +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 AMDONLY +EXTENSION : BASE +ISA_SET : AMD + +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x07 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-svm.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : VMRUN +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000] +OPERANDS : REG0=ArAX():r:IMPL +} +{ +ICLASS : VMMCALL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001] +OPERANDS : +} +{ +ICLASS : VMLOAD +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010] +OPERANDS : REG0=ArAX():r:IMPL +} +{ +ICLASS : VMSAVE +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011] +OPERANDS : +} +{ +ICLASS : STGI +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100] +OPERANDS : +} +{ +ICLASS : CLGI +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101] +OPERANDS : +} +{ +ICLASS : SKINIT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110] +OPERANDS : REG0=XED_REG_EAX:r:IMPL +} +{ +ICLASS : INVLPGA +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] +OPERANDS : REG0=ArAX():r:IMPL REG1=XED_REG_ECX:r:IMPL +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-sse4a.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# EXTRQ xmm:w:q, imm8, imm8 66 0F 78 /0 ib ib +# EXTRQ xmm:w:q, xmm:r:w 66 0F 79 /r + +{ +ICLASS : EXTRQ +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : SSE4a +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY +PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1() +OPERANDS : REG0=XMM_B():w:q IMM0:r:b IMM1:r:b +PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq +} + +# INSERTQ xmm:w:q xmm:r:q, imm8, imm8 f2 0f 78 /r ib ib +# INSERTQ xmm:w:q xmm:r:dq, f2 0f 79 /r + +{ +ICLASS : INSERTQ +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : SSE4a +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY +PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1() +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b +PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq +} + + +# MOVNTSD mem64:w:q, xmm:r:q f2 0f 2b /r +# MOVNTSS mem32:w:d, xmm:r:d f3 0f 2b /r + +{ +ICLASS : MOVNTSD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE4a +ATTRIBUTES: NONTEMPORAL AMDONLY +PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +} +{ +ICLASS : MOVNTSS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE4a +ATTRIBUTES: NONTEMPORAL AMDONLY +PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +} + +######################################################################################################### +# These next one is not part of SSE4a or SSE5. + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r + +{ +ICLASS : LZCNT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : AMD +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} + + +{ +ICLASS : BSR +VERSION : 1 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-clzero.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : CLZERO +CPL : 3 +CATEGORY : CLZERO +EXTENSION : CLZERO +ATTRIBUTES : AMDONLY + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +OPERANDS : REG0=ArAX():r:SUPP +COMMENT : AMD "Zen" ~2016 (expected) CPU +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-monitorx.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : MONITORX +CPL : 3 +CATEGORY : MISC +EXTENSION : MONITORX +ISA_SET : MONITORX +ATTRIBUTES: AMDONLY + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16 +OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP +} +{ +ICLASS : MWAITX +CPL : 3 +CATEGORY : MISC +EXTENSION : MONITORX +ISA_SET : MONITORX +ATTRIBUTES: AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-mcommit.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : MCOMMIT +CPL : 3 +CATEGORY : MISC +EXTENSION : MCOMMIT +ISA_SET : MCOMMIT +ATTRIBUTES: AMDONLY +FLAGS : MUST [ cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix +OPERANDS : + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-rdpru.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS: RDPRU +CPL: 3 +CATEGORY: RDPRU +EXTENSION: RDPRU +ISA_SET: RDPRU +ATTRIBUTES: AMDONLY +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +OPERANDS: REG0=XED_REG_EDX:w:SUPP:d REG1=XED_REG_EAX:w:SUPP:d REG2=XED_REG_ECX:r:SUPP:d +IFORM: RDPRU +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-snp.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : PSMASH +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64 +OPERANDS : REG0=XED_REG_RAX:rw:IMPL +} + + +{ +ICLASS : PVALIDATE +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix +OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_ECX:r:IMPL REG2=XED_REG_EDX:r:IMPL +} + + +{ +ICLASS : RMPADJUST +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64 +OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL REG2=XED_REG_RDX:r:IMPL +} + +{ +ICLASS : RMPUPDATE +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64 +OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-invlpgb.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : INVLPGB +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : AMD_INVLPGB +ATTRIBUTES: AMDONLY +COMMENT : Is this 64b mode only? +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32 +OPERANDS : REG0=XED_REG_EAX:r:IMPL \ + REG1=XED_REG_EDX:r:IMPL \ + REG2=XED_REG_ECX:r:IMPL +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64 +OPERANDS : REG0=XED_REG_RAX:r:IMPL \ + REG1=XED_REG_EDX:r:IMPL \ + REG2=XED_REG_ECX:r:IMPL +} +{ +ICLASS : TLBSYNC +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : AMD_INVLPGB +ATTRIBUTES: AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix +OPERANDS : +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XOP_INSTRUCTIONS():: +{ +ICLASS: VPMACSSWW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 +} + +{ +ICLASS: VPMACSSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSSDQL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPMACSWW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 +} + +{ +ICLASS: VPMACSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSDQL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPCMOV +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1 +} + +{ +ICLASS: VPPERM +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 MEM0:r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 REG3=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPMADCSSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMADCSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPROTB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 + +PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8 + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8 + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8 + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u8 +} + +{ +ICLASS: VPMACSSDD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSSDQH +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPMACSDD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSDQH +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPCOMB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:u8 + +PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:u8 + +PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:u8 + +PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:u8 + +PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 + +PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8 + +PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8 + +PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8 + +PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u8 +} + +{ +ICLASS: VFRCZPS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFRCZPD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFRCZSS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 + +PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:d:f32 +} + +{ +ICLASS: VFRCZSD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS: VPROTB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPROTW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPROTD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS: VPROTQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS: VPSHLB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPSHLW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPSHLD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS: VPSHLQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS: VPHADDBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDBD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDBQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 + +PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHADDWQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16 + +PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHADDUBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUBD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUBQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16 + +PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPHADDUWQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16 + +PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPHSUBBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8 + +PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHSUBWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 + +PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHSUBDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 + +PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPSHAB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8 + +PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 REG2=XMM_N():r:dq:i8 + +PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPSHAW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16 + +PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i16 REG2=XMM_N():r:dq:i16 + +PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPSHAD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32 + +PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XMM_N():r:dq:i32 + +PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPSHAQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64 + +PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i64 REG2=XMM_N():r:dq:i64 + +PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS: VPHADDDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 + +PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPHADDUDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32 + +PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32 +} + +{ +ICLASS: BEXTR_XOP +DISASM: bextr +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ] + +PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:d +PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_R():w:y MEM0:r:y IMM0:r:d + +PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +OPERANDS: REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:d +PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_R():w:y REG1=VGPRy_B():r:y IMM0:r:d +} + +{ +ICLASS: BLCFILL +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLSFILL +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCS +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: TZMSK +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCIC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLSIC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: T1MSKC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCMSK +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCI +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: LLWPCB +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS: REG0=VGPRy_B():w:y +} + +{ +ICLASS: SLWPCB +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_B():w:y +} + +{ +ICLASS: LWPINS +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod ] + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d +} + +{ +ICLASS: LWPVAL +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-fma4-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: +{ +ICLASS: VFMADDSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMADDSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMSUBADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMSUBADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMADDSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFMADDSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFMSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMSUBSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFMSUBSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFNMADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFNMADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFNMADDSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFNMADDSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFNMSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFNMSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFNMSUBSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFNMSUBSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-vpermil2-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VPERMIL2PS +CPL : 3 +CATEGORY : XOP +EXTENSION : XOP +ISA_SET : XOP +ATTRIBUTES : AMDONLY + +# 128b W0 +PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 IMM0:r:b + +# 256b W0 +PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 IMM0:r:b + +# 128b W1 +PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 IMM0:r:b + +# 256b W1 +PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 IMM0:r:b + +} + + + +{ +ICLASS : VPERMIL2PD +CPL : 3 +CATEGORY : XOP +EXTENSION : XOP +ISA_SET : XOP +ATTRIBUTES : AMDONLY + +# 128b W0 +PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b + +# 256b W0 +PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b + +# 128b W1 +PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b + +# 256b W1 +PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + + +UDELETE: NOP0F1A +UDELETE: NOP0F1B + + + +{ +ICLASS: BNDMK +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: NO_RIP_REL +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():w AGEN:r +} + + + + +{ +ICLASS: BNDCL +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCU +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCN +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r + +} + +{ +ICLASS: BNDMOV +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: load form + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_R():w REG1=BND_B():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 + + + +} + +{ +ICLASS: BNDMOV +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: store form + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_B():w REG1=BND_R():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r +} + + +{ +ICLASS: BNDLDX +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:bnd32 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +} + +{ +ICLASS: BNDSTX +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: MEM0:w:bnd32 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +} + +{ +ICLASS : NOP +CPL : 3 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. + +PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B +} + + +{ +ICLASS : NOP +CPL : 3 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : For MPXMODE=0 operation + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEMv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEM_0F1B +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-nop-remove.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +UDELETE: NOP0F1E + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : reg form MODRM.MOD=3 & MODRM.REG=0b001 f3 prefix is RDSSP{D,Q} + +# mem forms + +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E + + +# reg forms + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + + + + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b001 is for CET for all values of RM. +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b111 with RM=2 or RM=3 is for CET +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +} + + +# REPLACE CERTAIN NOPS WITH MODAL OPTIONS basd on CET=0/1 +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLRSSBSY (CLRSSBSY-N/A-1) +{ +ICLASS: CLRSSBSY +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM() +OPERANDS: MEM0:rw:q:u64 +IFORM: CLRSSBSY_MEMu64 +} + + +# EMITTING ENDBR32 (ENDBR32-N/A-1) +{ +ICLASS: ENDBR32 +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR32 +} + + +# EMITTING ENDBR64 (ENDBR64-N/A-1) +{ +ICLASS: ENDBR64 +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR64 +} + + +# EMITTING INCSSPD (INCSSPD-N/A-1) +{ +ICLASS: INCSSPD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0 +OPERANDS: REG0=GPR32_B():r:d:u8 REG1=XED_REG_SSP:rw:SUPP:u64 +IFORM: INCSSPD_GPR32u8 +} + + +# EMITTING INCSSPQ (INCSSPQ-N/A-1) +{ +ICLASS: INCSSPQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64 +OPERANDS: REG0=GPR64_B():r:q:u8 REG1=XED_REG_SSP:rw:SUPP:u64 +IFORM: INCSSPQ_GPR64u8 +} + + +# EMITTING RDSSPD (RDSSPD-N/A-1) +{ +ICLASS: RDSSPD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_SSP:r:SUPP:u64 +IFORM: RDSSPD_GPR32u32 +} + + +# EMITTING RDSSPQ (RDSSPQ-N/A-1) +{ +ICLASS: RDSSPQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_SSP:r:SUPP:u64 +IFORM: RDSSPQ_GPR64u64 +} + + +# EMITTING RSTORSSP (RSTORSSP-N/A-1) +{ +ICLASS: RSTORSSP +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:rw:q:u64 REG0=XED_REG_SSP:w:SUPP:u64 +IFORM: RSTORSSP_MEMu64 +} + + +# EMITTING SAVEPREVSSP (SAVEPREVSSP-N/A-1) +{ +ICLASS: SAVEPREVSSP +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix +OPERANDS: REG0=XED_REG_SSP:r:SUPP:u64 +IFORM: SAVEPREVSSP +} + + +# EMITTING SETSSBSY (SETSSBSY-N/A-1) +{ +ICLASS: SETSSBSY +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix +OPERANDS: +IFORM: SETSSBSY +} + + +# EMITTING WRSSD (WRSSD-N/A-1) +{ +ICLASS: WRSSD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRSSD_MEMu32_GPR32u32 +} + + +# EMITTING WRSSQ (WRSSQ-N/A-1) +{ +ICLASS: WRSSQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRSSQ_MEMu64_GPR64u64 +} + + +# EMITTING WRUSSD (WRUSSD-N/A-1) +{ +ICLASS: WRUSSD +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRUSSD_MEMu32_GPR32u32 +} + + +# EMITTING WRUSSQ (WRUSSQ-N/A-1) +{ +ICLASS: WRUSSQ +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRUSSQ_MEMu64_GPR64u64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdrand/rdrand-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : RDRAND +CPL : 3 +CATEGORY : RDRAND +EXTENSION : RDRAND +ISA_SET : RDRAND +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sha/sha-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SHA1MSG1 (SHA1MSG1-N/A-1) +{ +ICLASS: SHA1MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1MSG1_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1MSG1_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1MSG2 (SHA1MSG2-N/A-1) +{ +ICLASS: SHA1MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1MSG2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1MSG2_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1NEXTE (SHA1NEXTE-N/A-1) +{ +ICLASS: SHA1NEXTE +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1NEXTE_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1NEXTE +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1NEXTE_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1RNDS4 (SHA1RNDS4-N/A-1) +{ +ICLASS: SHA1RNDS4 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b +IFORM: SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA +} + +{ +ICLASS: SHA1RNDS4 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 IMM0:r:b +IFORM: SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA +} + + +# EMITTING SHA256MSG1 (SHA256MSG1-N/A-1) +{ +ICLASS: SHA256MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA256MSG1_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA256MSG1_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA256MSG2 (SHA256MSG2-N/A-1) +{ +ICLASS: SHA256MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA256MSG2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA256MSG2_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA256RNDS2 (SHA256RNDS2-N/A-1) +{ +ICLASS: SHA256RNDS2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: SHA256RNDS2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256RNDS2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 REG1=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaveopt/xsaveopt-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVEOPT +CPL : 3 +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +COMMENT : Variable length Store and conditional reg read. reads/modifies header. +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVEOPT64 +CPL : 3 +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +COMMENT : Variable length Store and conditional reg read. reads/modifies header. +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaves/xsaves-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVES +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVES64 +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + + +{ +ICLASS : XRSTORS +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditional reg write. +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XRSTORS64 +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditional reg write +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsavec/xsavec-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVEC +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVEC +COMMENT : Variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +{ +ICLASS : XSAVEC64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVEC +COMMENT : Variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/clflushopt/clflushopt.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS: CLFLUSHOPT +CPL: 3 +CATEGORY: CLFLUSHOPT +EXTENSION: CLFLUSHOPT +ISA_SET: CLFLUSHOPT +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdseed/rdseed-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : RDSEED +CPL : 3 +CATEGORY : RDSEED +EXTENSION : RDSEED +ISA_SET : RDSEED +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/fsgsbase/fsgsbase-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + + +{ +ICLASS : RDFSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y + +} +{ +ICLASS : RDGSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y + +} + + + +{ +ICLASS : WRFSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y + +} +{ +ICLASS : WRGSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/smap/smap-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS : CLAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-0 ] +# 0F 01 CA = 1100_1010 = 11_001_010 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix +OPERANDS : +} + +{ +ICLASS : STAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-1 ] +# 0F 01 CB = 1100_1011 = 11_001_011 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix +OPERANDS : +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx/sgx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +# Both read EAX +# Both may read or write or r/w RBX, RCX, RDX +# ENCLU 0f 01 D7 +# D7 = 1101 0111 + +# ENCLS 0f 01 CF +# CF = 1100_1111 + + + +{ +ICLASS: ENCLU +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP +} + +{ + +ICLASS: ENCLS +CPL: 0 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdpid/rdpid-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING RDPID (RDPID-N/A-1-32) +{ +ICLASS: RDPID +CPL: 3 +CATEGORY: RDPID +EXTENSION: RDPID +ISA_SET: RDPID +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 +IFORM: RDPID_GPR32u32 +} + + +# EMITTING RDPID (RDPID-N/A-1-64) +{ +ICLASS: RDPID +CPL: 3 +CATEGORY: RDPID +EXTENSION: RDPID +ISA_SET: RDPID +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 +IFORM: RDPID_GPR64u64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pt/intelpt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: +{ +ICLASS : PTWRITE +CPL : 3 +CATEGORY : PTWRITE +EXTENSION : PTWRITE +ISA_SET : PTWRITE +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():r +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:y + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/movdir-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING MOVDIR64B (MOVDIR64B-N/A-1) +{ +ICLASS: MOVDIR64B +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64 +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP SEG1=XED_REG_ES:r:SUPP +IFORM: MOVDIR64B_GPRa_MEM + +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64 +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP +IFORM: MOVDIR64B_GPRa_MEM +} + + +# EMITTING MOVDIRI (MOVDIRI-N/A-1-32) +{ +ICLASS: MOVDIRI +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: MOVDIRI_MEMu32_GPR32u32 +} + + +# EMITTING MOVDIRI (MOVDIRI-N/A-1-64) +{ +ICLASS: MOVDIRI +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: MOVDIRI_MEMu64_GPR64u64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/waitpkg-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING TPAUSE (TPAUSE-N/A-1-32) +{ +ICLASS: TPAUSE +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix +OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: TPAUSE_GPR32u32 +} + + + +# EMITTING UMONITOR (UMONITOR-N/A-1) +{ +ICLASS: UMONITOR +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS: REG0=A_GPR_B():r +IFORM: UMONITOR_GPRa +} + + +# EMITTING UMWAIT (UMWAIT-N/A-1-32) +{ +ICLASS: UMWAIT +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix +OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: UMWAIT_GPR32 +} + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-nop-mod.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +UDELETE: NOP0F1C + +{ +ICLASS : NOP +#UNAME : NOP0F1C +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : memory form with MODRM.REG=0b000 and no refining prefix is CLDEMOTE +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C + + +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +} + +# re-defined by another contemporaneous ISA extension +{ +ICLASS : NOP +UNAME : NOP0F1C_REG +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +# reg form +PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1C +} + +{ +ICLASS : NOP +UNAME : NOP0F1C_MEM +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0 +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLDEMOTE (CLDEMOTE-N/A-1) +{ +ICLASS: CLDEMOTE +CPL: 3 +CATEGORY: CLDEMOTE +EXTENSION: CLDEMOTE +ISA_SET: CLDEMOTE +REAL_OPCODE: Y +PATTERN: 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=1 +OPERANDS: MEM0:r:b:u8 +IFORM: CLDEMOTE_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx-enclv/sgx-enclv-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING ENCLV (ENCLV-N/A-1) +{ +ICLASS: ENCLV +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX_ENCLV +ISA_SET: SGX_ENCLV +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64 +IFORM: ENCLV +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# The neat thing is we can just end a nonterminal by starting a new one. + +AVX_INSTRUCTIONS():: +{ +ICLASS : VADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VADDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VADDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VADDSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VADDSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VANDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +{ +ICLASS : VANDNPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDNPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + + +{ +ICLASS : VBLENDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VBLENDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + + + + +{ +ICLASS : VCMPPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + +{ +ICLASS : VCMPSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + + +{ +ICLASS : VCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 +} + + +{ +ICLASS : VCVTDQ2PD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +COMMENT : ignores MXCSR. 32b int fits in f64 +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 + +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VCVTDQ2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 + +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 +} + +{ +ICLASS : VCVTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 + +PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 + +PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VCVTTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 + +PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 + +PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VCVTPD2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f64 + +PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:qq:f64 + +PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS : VCVTPS2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VCVTTPS2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VCVTPS2PD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f32 + +PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f32 + +PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f32 + +PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f32 +} + + + + +{ +ICLASS : VCVTSD2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + +PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCVTTSD2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + + +PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 +} + + + + +{ +ICLASS : VCVTSS2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + +PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 +} + +{ +ICLASS : VCVTTSS2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + +PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 +} + + + + +{ +ICLASS : VCVTSD2SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f64 + +PATTERN : VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:q:f64 + +} + + +{ +ICLASS : VCVTSI2SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:i64 + +PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR64_B():r:q:i64 +} + + +{ +ICLASS : VCVTSI2SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 + +PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR64_B():r:q:i64 +} + + +{ +ICLASS : VCVTSS2SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:f32 + +PATTERN : VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VDIVPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VDIVPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VDIVSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VDIVSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VEXTRACTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:f64 REG0=YMM_R():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=YMM_R():r:dq:f64 IMM0:r:b +} + + + +{ +ICLASS : VDPPD +EXCEPTIONS: avx-type-2D +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b +} + +{ +ICLASS : VDPPS +EXCEPTIONS: avx-type-2D +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + +{ +ICLASS : VEXTRACTPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b +} + + +{ +ICLASS : VZEROALL +EXCEPTIONS: avx-type-8 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : xmm_state_w + +PATTERN : VV1 0x77 VNP V0F VL256 NOVSR +OPERANDS: + +} + +# FIXME: how to denote partial upper clobber! +{ +ICLASS : VZEROUPPER +EXCEPTIONS: avx-type-8 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : xmm_state_w NOTSX # FIXME: should be ymm_state_w? + +PATTERN : VV1 0x77 VNP V0F VL128 NOVSR +OPERANDS: +} + + +{ +ICLASS : VHADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VHADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VHSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VHSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VPERMILPD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +# 2008-02-01 moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPD +PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64 + +PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64 + +PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64 + +######################################## +# IMMEDIATE FORM +######################################## + +# 2008-02-01 moved norexw_prefix to after V0F3A to avoid a graph build conflict with VPHSUBW +PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VPERMILPS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +# moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPS +PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:u32 + +PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:u32 + +PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:u32 + +PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:u32 + +######################################## +# IMMEDIATE FORM +######################################## + +# 2008-02-01: moved norexw_prefix after V0F3A due to graph-build collision with VPMADDUBSW +PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b +} + + +{ +ICLASS : VPERM2F128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# 2008-02-01 moved norexw_prefix to after V0F3A to avoid conflict with VPHSUBD +PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VBROADCASTSS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +PATTERN : VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +} +{ +ICLASS : VBROADCASTSD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +} + +{ +ICLASS : VBROADCASTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +COMMENT : There is no F128 type. I just set these to f64 for lack of anything better. +PATTERN : VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +} + + +{ +ICLASS : VINSERTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 + +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 +} + +{ +ICLASS : VINSERTPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b +} + + + + + +{ +ICLASS : VLDDQU +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq +} + + + + + + +{ +ICLASS : VMASKMOVPS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop NONTEMPORAL +# load forms +PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32 + +PATTERN : VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq MEM0:r:qq:f32 + +# store forms +PATTERN : VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_N():r:dq REG1=XMM_R():r:dq:f32 + +PATTERN : VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_N():r:qq REG1=YMM_R():r:qq:f32 +} + +{ +ICLASS : VMASKMOVPD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop +# load forms +PATTERN : VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:f64 + +PATTERN : VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:f64 + +# store forms +PATTERN : VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:f64 + +PATTERN : VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:f64 +} + +{ +ICLASS : VPTEST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq + +PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq + +PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq MEM0:r:qq + +PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq REG1=YMM_B():r:qq +} + +{ +ICLASS : VTESTPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq:f32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VTESTPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq:f64 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VMAXPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMAXPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VMAXSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VMAXSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VMINPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMINPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VMINSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VMINSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VMOVAPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# 128b load + +PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 +IFORM : VMOVAPD_XMMdq_XMMdq_28 + +# 128b store + +PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 +IFORM : VMOVAPD_XMMdq_XMMdq_29 + +# 256b load + +PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +IFORM : VMOVAPD_YMMqq_YMMqq_28 + +# 256b store + +PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 +IFORM : VMOVAPD_YMMqq_YMMqq_29 +} + + + +{ +ICLASS : VMOVAPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# 128b load + +PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 +IFORM : VMOVAPS_XMMdq_XMMdq_28 +# 128b store + +PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 +IFORM : VMOVAPS_XMMdq_XMMdq_29 + +# 256b load + +PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +IFORM : VMOVAPS_YMMqq_YMMqq_28 + +# 256b store + +PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 +IFORM : VMOVAPS_YMMqq_YMMqq_29 +} + + + +{ +ICLASS : VMOVD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# 32b load +PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d + +PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d + +# 32b store +PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d + +PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d + + + +# 32b load +PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d + +PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d + +# 32b store +PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d + +PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d + + +} + +{ +ICLASS : VMOVQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# 64b load +PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : VMOVQ_XMMdq_MEMq_6E + +PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r:q + +# 64b store +PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : VMOVQ_MEMq_XMMq_7E + +PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:q + + +# 2nd page of MOVQ forms +PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : VMOVQ_XMMdq_MEMq_7E + +PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +IFORM : VMOVQ_XMMdq_XMMq_7E + +PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : VMOVQ_MEMq_XMMq_D6 + +PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q +IFORM : VMOVQ_XMMdq_XMMq_D6 + +} + + + + +{ +ICLASS : VMOVDDUP +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64 + + +PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} + + + +{ +ICLASS : VMOVDQA +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# LOAD XMM + +PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : VMOVDQA_XMMdq_XMMdq_6F + +# STORE XMM + +PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : VMOVDQA_XMMdq_XMMdq_7F + +# LOAD YMM + +PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq + +PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq +IFORM : VMOVDQA_YMMqq_YMMqq_6F + + +# STORE YMM + +PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq + +PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq +IFORM : VMOVDQA_YMMqq_YMMqq_7F +} + + +{ +ICLASS : VMOVDQU +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# LOAD XMM + +PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : VMOVDQU_XMMdq_XMMdq_6F + +# LOAD YMM + +PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq + +PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq +IFORM : VMOVDQU_YMMqq_YMMqq_6F + +# STORE XMM + +PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : VMOVDQU_XMMdq_XMMdq_7F + +# STORE YMM + +PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq + +PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq +IFORM : VMOVDQU_YMMqq_YMMqq_7F +} + +################################################# +## skipping to the end +################################################# + +################################################# +## MACROS +################################################# +{ +ICLASS : VMOVSHDUP +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VMOVSLDUP +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VPOR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPAND +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPANDN +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPXOR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} + + +{ +ICLASS : VPABSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8 + +PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : VPABSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:i16 + +PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : VPABSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:i32 + +PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPHMINPOSUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 +} + + + + + + + + + + +{ +ICLASS : VPSHUFD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : VPSHUFHW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : VPSHUFLW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} + + + + + + + + + + + + + +{ +ICLASS : VPACKSSWB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPACKSSDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPACKUSWB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPACKUSDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSLLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSLLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSLLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPSRLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPSRAW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:u64 + +PATTERN : VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRAD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:u64 + +PATTERN : VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPADDB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPADDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPADDD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPADDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPADDSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPADDSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPADDUSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPADDUSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPAVGB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPAVGW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPCMPEQB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPCMPEQW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPCMPEQD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPCMPEQQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPCMPGTB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPCMPGTW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPCMPGTD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPCMPGTQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPHADDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHADDD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPHADDSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHSUBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHSUBD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPHSUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPMULHUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMULHRSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULHW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULLW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULLD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMULUDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPMULDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSADBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPSHUFB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS : VPSIGNB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSIGNW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPSIGND +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSUBSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPSUBUSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPSUBUSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPSUBB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSUBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPSUBD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPSUBQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPUNPCKHBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPUNPCKHWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPUNPCKHDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPUNPCKLBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPUNPCKLWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPUNPCKLDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPUNPCKLQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + + + +{ +ICLASS : VPSRLDQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLDQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD +} + + + + + + + + + + + + + + + + + + + + +{ +ICLASS : VMOVLHPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 REG2=XMM_B():r:q:f32 +} +{ +ICLASS : VMOVHLPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +} + + + + + + + +{ +ICLASS : VPALIGNR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b + +PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b +} + + + + + + + + + + + + +############################################################ +{ +ICLASS : VROUNDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} +{ +ICLASS : VROUNDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b +} +{ +ICLASS : VROUNDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} +{ +ICLASS : VROUNDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + +{ +ICLASS : VSHUFPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} +{ +ICLASS : VSHUFPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + +{ +ICLASS : VRCPPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VRCPSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: simd_scalar +PATTERN : VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VRSQRTPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VRSQRTSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: simd_scalar +PATTERN : VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VSQRTPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} +{ +ICLASS : VSQRTPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VSQRTSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR simd_scalar +PATTERN : VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VSQRTSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VUNPCKHPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VUNPCKHPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VSUBSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR SIMD_SCALAR +PATTERN : VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VSUBSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VMULPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VMULPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VMULSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR simd_scalar +PATTERN : VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VMULSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VORPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} +{ +ICLASS : VORPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 + +PATTERN : VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMAXSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPMAXSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMAXSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMAXUB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPMAXUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMAXUD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS : VPMINSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPMINSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMINSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMINUB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPMINUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMINUD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + + +{ +ICLASS : VPMADDWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMADDUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:i8 + +PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:i8 +} + + +{ +ICLASS : VMPSADBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b +} + + +############################################################ +{ +ICLASS : VPSLLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD +} + +{ +ICLASS : VPSRAW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:i16 REG1=XMM_B():r:dq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD +} + + +{ +ICLASS : VUCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] + +PATTERN : VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VUCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] + +PATTERN : VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:d:f32 +} + +############################################### + + +{ +ICLASS : VUNPCKLPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VUNPCKLPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + + +{ +ICLASS : VXORPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + +{ +ICLASS : VXORPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +############################################################################ + +{ +ICLASS : VMOVSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : simd_scalar + +# NOTE: REG1 is ignored!!! +PATTERN : VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +IFORM : VMOVSS_XMMdq_XMMdq_XMMd_10 + +PATTERN : VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:d:f32 + +PATTERN : VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32 +IFORM : VMOVSS_XMMdq_XMMdq_XMMd_11 +} +############################################################################ +{ +ICLASS : VMOVSD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : simd_scalar + +# NOTE: REG1 is ignored!!! +PATTERN : VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +IFORM : VMOVSD_XMMdq_XMMdq_XMMq_10 + +PATTERN : VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 + +PATTERN : VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64 +IFORM : VMOVSD_XMMdq_XMMdq_XMMq_11 +} +############################################################################ +{ +ICLASS : VMOVUPD +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 +IFORM : VMOVUPD_XMMdq_XMMdq_10 + +PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 +IFORM : VMOVUPD_XMMdq_XMMdq_11 + +# 256b versions + +PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +IFORM : VMOVUPD_YMMqq_YMMqq_10 + +PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 +IFORM : VMOVUPD_YMMqq_YMMqq_11 +} + +############################################################################ +{ +ICLASS : VMOVUPS +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 +IFORM : VMOVUPS_XMMdq_XMMdq_10 + +PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 +IFORM : VMOVUPS_XMMdq_XMMdq_11 + +# 256b versions + +PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +IFORM : VMOVUPS_YMMqq_YMMqq_10 + +PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 +IFORM : VMOVUPS_YMMqq_YMMqq_11 +} + + +############################################################################ +{ +ICLASS : VMOVLPD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +COMMENT: 3op version uses high part of XMM_N +PATTERN : VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 +} + +{ +ICLASS : VMOVLPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +COMMENT: 3op version uses high part of XMM_N +PATTERN : VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f32 + +PATTERN : VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 +} + +{ +ICLASS : VMOVHPD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 +PATTERN : VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:dq:f64 +} + +{ +ICLASS : VMOVHPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 +PATTERN : VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 MEM0:r:q:f32 + +PATTERN : VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:dq:f32 +} +############################################################################ + +{ +ICLASS : VMOVMSKPD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f64 + +# 256b versions + +PATTERN : VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMOVMSKPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f32 + +# 256b versions + +PATTERN : VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f32 +} + +############################################################################ +{ +ICLASS : VPMOVMSKB +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=XMM_B():r:dq:i8 +} + +############################################################################ + +############################################################################ +# SX versions +############################################################################ + +{ +ICLASS : VPMOVSXBW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 +} + +############################################################################ +{ +ICLASS : VPMOVSXBD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 +PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 +PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 +PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 +} + + + + + +############################################################################ +# ZX versions +############################################################################ + +{ +ICLASS : VPMOVZXBW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 +} + +############################################################################ +{ +ICLASS : VPMOVZXBD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 +PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 +PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 +PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 +} + + + +############################################################################ +############################################################################ +{ +ICLASS : VPEXTRB +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG +PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b REG0=XMM_R():r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u8 IMM0:r:b +} +############################################################################ +{ +ICLASS : VPEXTRW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG + +PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:w REG0=XMM_R():r:dq:u16 IMM0:r:b + +PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u16 IMM0:r:b +IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_15 + +# special C5 reg-only versions from SSE2: + +PATTERN : VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:u16 IMM0:r:b +IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_C5 +} +############################################################################ +{ +ICLASS : VPEXTRQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b +} +############################################################################ +{ +ICLASS : VPEXTRD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled. + +# 64b mode +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b + +# not64b mode +PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b + +} +############################################################################ + + + + + + +{ +ICLASS : VPINSRB +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG +PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +} + +{ +ICLASS : VPINSRW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : WIG +PATTERN : VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b + +PATTERN : VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +} + +{ +ICLASS : VPINSRD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled +# 64b mode +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b + +# 32b mode +PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +} +{ +ICLASS : VPINSRQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +} + +############################################################################ + + + + + +{ +ICLASS : VPCMPESTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP +} +{ +ICLASS : VPCMPESTRI64 +DISASM : vpcmpestri +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP +} +{ +ICLASS : VPCMPISTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP +} +{ +ICLASS : VPCMPISTRI64 +DISASM : vpcmpistri +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP +} + +{ +ICLASS : VPCMPESTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : VPCMPESTRM64 +DISASM : vpcmpestrm +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : VPCMPISTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP +} +#################################################################################### + + + +#################################################################################### +{ +ICLASS : VMASKMOVDQU +EXCEPTIONS: avx-type-4 +CPL : 3 + +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop fixed_base0 NOTSX NONTEMPORAL +PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} + +#################################################################################### +{ +ICLASS : VLDMXCSR +EXCEPTIONS: avx-type-5L +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP +} +{ +ICLASS : VSTMXCSR +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR_RD +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP +} +####################################################################################### + +{ +ICLASS : VPBLENDVB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 REG2=XMM_SE():r:dq:i8 + +PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 REG3=XMM_SE():r:dq:i8 +} + +{ +ICLASS : VBLENDVPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:u64 + +} + +{ +ICLASS : VBLENDVPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32 + + +} + +####################################################################################### + + + +{ +ICLASS : VMOVNTDQA +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL + +PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} + + + + + +{ +ICLASS : VMOVNTDQ +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32 + +} +{ +ICLASS : VMOVNTPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +} +{ +ICLASS : VMOVNTPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-movnt-store.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VMOVNTDQ +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32 + +} +{ +ICLASS : VMOVNTPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +} +{ +ICLASS : VMOVNTPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-aes-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + +{ +ICLASS : VAESKEYGENASSIST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b +} +{ +ICLASS : VAESENC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESENCLAST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESDEC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESDECLAST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESIMC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pclmul-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: +{ +ICLASS : VPCLMULQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b +PATTERN : VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/fp16-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: +{ +ICLASS : VCVTPH2PS +COMMENT : UPCONVERT -- NO IMMEDIATE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : F16C +ATTRIBUTES : MXCSR +EXCEPTIONS: avx-type-11 +# 128b form + +PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:q:f16 + +PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16 + + +# 256b form + +PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16 + +PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16 +} + + +{ +ICLASS : VCVTPS2PH +COMMENT : DOWNCONVERT -- HAS IMMEDIATE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : F16C +ATTRIBUTES : MXCSR +EXCEPTIONS: avx-type-11 +# 128b imm8 form + +PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +OPERANDS : MEM0:w:q:f16 REG0=XMM_R():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +OPERANDS : REG0=XMM_B():w:q:f16 REG1=XMM_R():r:dq:f32 IMM0:r:b + +# 256b imm8 form + +PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +OPERANDS : MEM0:w:dq:f16 REG0=YMM_R():r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/avx-fma-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + +# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. +# Encoder must enforce equality between two parameters. Never had to do this before. +# Extra check? +# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) +############################################################################################# +# Operand orders: +# A = B * C + D +#Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 +#Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 +#Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 + +# dst is in MODRM.REG +# regsrc is in VEX.vvvv +# memop is in MODRM.RM +############################################################################################ + + + + + + + + + + + + +########################################################## + + + + + + + + + + + + +################################################################## + + + + + + + + + + + + + +################################################################## +{ +ICLASS : VFMADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADD132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFMADD132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFMADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADD213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMADD213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFMADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFMADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFMADD231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMADD231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + + +################################################### +{ +ICLASS : VFMADDSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADDSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADDSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} + +{ +ICLASS : VFMADDSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADDSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADDSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +################################################### + +{ +ICLASS : VFMSUBADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUBADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUBADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} + +{ +ICLASS : VFMSUBADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUBADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUBADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} + + +################################################### + +{ +ICLASS : VFMSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUB132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFMSUB132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFMSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMSUB213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFMSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFMSUB231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + +{ +ICLASS : VFNMADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMADD132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFNMADD132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFNMADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMADD213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMADD213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFNMADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFNMADD231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMADD231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + +{ +ICLASS : VFNMSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMSUB132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFNMSUB132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFNMSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFNMSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFNMSUB231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/gather-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +# DEST in MODRM.REG +# BASE in SIB.base +# INDEX in SIB.index +# MASK in VEX.VVVV -- NOTE mask is a signed integer!!! + +# VL = 128 VL = 256 +# dest/mask index memsz dest/mask index memsz +# qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b +# dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b +# dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b +# qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b + + + +{ +ICLASS : VGATHERDPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERDPS +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32 +IFORM: VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERQPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERQPS +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:d:f32 REG1=XMM_N():rw:q:i32 +IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} + +{ +ICLASS : VPGATHERDQ +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERDD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:d:u32 REG1=YMM_N():rw:qq:i32 +IFORM: VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERQQ +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERQD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:d:u32 REG1=XMM_N():rw:q:i32 +IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-int256-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VPABSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 +} +{ +ICLASS : VPABSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 + +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 +} +{ +ICLASS : VPABSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 + +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 +} + + + + + + + + + +{ +ICLASS : VPACKSSWB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPACKSSDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPACKUSWB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPACKUSDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPSLLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 +} + +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 +} + +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 + +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 + +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 +} + + +{ +ICLASS : VPADDB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPADDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPADDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPADDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + +{ +ICLASS : VPADDSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPADDSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPADDUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPADDUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + +{ +ICLASS : VPAVGB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPAVGW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + + +{ +ICLASS : VPCMPEQB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPCMPEQW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPCMPEQD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPCMPEQQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + +{ +ICLASS : VPCMPGTB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPCMPGTW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPCMPGTD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPCMPGTQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + + +{ +ICLASS : VPHADDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHADDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHADDSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPMADDWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMADDUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 +} + +{ +ICLASS : VPMAXSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPMAXSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMAXSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMAXUB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPMAXUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMAXUD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMINSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPMINSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMINSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMINUB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPMINUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMINUD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMULHUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMULHRSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPMULHW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMULLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMULLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMULUDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPMULDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSHUFB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} + +{ +ICLASS : VPSIGNB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSIGNW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSIGND +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + + +{ +ICLASS : VPSUBSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPSUBUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSUBUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + +{ +ICLASS : VPSUBB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPSUBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + +{ +ICLASS : VPUNPCKHBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKHWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKHDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + +{ +ICLASS : VPUNPCKLBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKLWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKLQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + +{ +ICLASS : VPALIGNR +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b + +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b +} +{ +ICLASS : VMPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b + +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} + + + +{ +ICLASS : VPOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} + + + +{ +ICLASS : VPBLENDVB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 + +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 +} + + + + +{ +ICLASS : VPMOVMSKB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 +} + + + +{ +ICLASS : VPSHUFD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b + +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b +} +{ +ICLASS : VPSHUFHW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} +{ +ICLASS : VPSHUFLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} + + + +{ +ICLASS : VPSRLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +} + +############################################## + +{ +ICLASS : VPSLLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} + +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 + +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} + + + +############################################################################ +# SX versions +############################################################################ + +{ +ICLASS : VPMOVSXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 +} + +############################################################################ +{ +ICLASS : VPMOVSXBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 +} + + + + + +############################################################################ +# ZX versions +############################################################################ + +{ +ICLASS : VPMOVZXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 +} + +############################################################################ +{ +ICLASS : VPMOVZXBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 +} + + +################################## +# newer stuff 2009-08-14 + + +{ +ICLASS : VINSERTI128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b + +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b +} + + + + + +{ +ICLASS : VEXTRACTI128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b + +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b +} + + +########################################################################### + +### # VPMASKMOVD masked load and store +### # VPMASKMOVQ masked load and store + + + + +{ +ICLASS : VPMASKMOVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + + +PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + + +PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +} + +{ +ICLASS : VPMASKMOVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 + + +PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 + + +PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 +} +########################################################################### + + +### # VPERM2I128 256b only + +{ +ICLASS : VPERM2I128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... + +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b + +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b +} + + +{ +ICLASS : VPERMQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b + +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b +} + +{ +ICLASS : VPERMPD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} + + + + + + + + +{ +ICLASS : VPERMD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + + +PATTERN : VV1 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x36 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPERMPS +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +########################################################################### + + +### # VPBLENDD imm 128/256 + + + +{ +ICLASS : VPBLENDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b + +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b + + +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b + +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b +} + + + +########################################################################### + +{ +ICLASS : VPBROADCASTB +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 + +} + + + + +{ +ICLASS : VPBROADCASTW +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 + +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 + +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 + +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 +} + + + + +### # VPBROADCASTD gpr/mem + + +{ +ICLASS : VPBROADCASTD +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 + + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 +} + + + +### # VPBROADCASTQ gpr/mem + +{ +ICLASS : VPBROADCASTQ +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 + +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 + +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 + +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 +} + + + + + + +{ +ICLASS : VBROADCASTSS +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : xmm,xmm and ymm,xmm +PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 +} + + +{ +ICLASS : VBROADCASTSD +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : ymm,xmm only +PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 +} + + + +{ +ICLASS : VBROADCASTI128 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? +PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-vshift-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + + + +{ +ICLASS : VPSLLVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} +{ +ICLASS : VPSLLVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + +{ +ICLASS : VPSRLVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} +{ +ICLASS : VPSRLVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + +{ +ICLASS : VPSRAVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/movnt-load-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VMOVNTDQA +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX2 +EXCEPTIONS: avx-type-1 +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL + +PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq +} + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/hsw-bmi-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + +{ +ICLASS : PDEP +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +#32b +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + +{ +ICLASS : PEXT +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + + +#32b +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + + +{ +ICLASS : ANDN +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] + +# 32b +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + +{ +ICLASS : BLSR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] + +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q + +} + +{ +ICLASS : BLSMSK +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] + +#32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +#64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} + +{ +ICLASS : BLSI +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] + +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} + +{ +ICLASS : BZHI +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] + +# 32b +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + +{ +ICLASS : BEXTR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] + +# 32b +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + + + +{ +ICLASS : SHLX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} +{ +ICLASS : SARX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} +{ +ICLASS : SHRX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + + + +{ +ICLASS : MULX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# reg:w vvvv:w rm:r rdx:r +# 32b +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP + +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP + +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP + +# 64b +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP +} + +{ +ICLASS : RORX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change + +# 32b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b + +# 64b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/tzcnt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : TZCNT +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +} + +{ +ICLASS : BSF +VERSION : 1 +COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] + +PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/vmfunc-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : VMFUNC +CPL : 3 +CATEGORY : VTX +EXTENSION : VMFUNC +ISA_SET : VMFUNC +ATTRIBUTES : +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:r:SUPP +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/invpcid-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + + +{ +ICLASS : INVPCID +CPL : 0 +CATEGORY : MISC +EXTENSION : INVPCID +ISA_SET : INVPCID +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/lzcnt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r + +{ +ICLASS : LZCNT +# This replace the AMD version in LZCNT builds +VERSION : 2 +CPL : 3 +CATEGORY : LZCNT +EXTENSION : LZCNT +COMMENT : These next one WAS introduced first by AMD circa SSE4a. +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} + + +{ +ICLASS : BSR +VERSION : 2 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/rtm-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XBEGIN +CPL : 3 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Not always a branch. If aborts, then branches & eax is written + +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP +} + +{ +ICLASS : XEND +CPL : 3 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Transaction end. may branch +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix +OPERANDS : +} + +{ +ICLASS : XABORT +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : RTM +COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b +} + + +{ +ICLASS : XTEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : RTM +COMMENT : test if in RTM transaction mode +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix +OPERANDS : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/bdw/adox-adcx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : ADCX +CPL : 3 +CATEGORY : ADOX_ADCX +EXTENSION : ADOX_ADCX +ISA_SET : ADOX_ADCX + +FLAGS : MUST [ cf-tst cf-mod ] + +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d + +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +} + + + +{ +ICLASS : ADOX +CPL : 3 +CATEGORY : ADOX_ADCX +EXTENSION : ADOX_ADCX +ISA_SET : ADOX_ADCX + +FLAGS : MUST [ of-tst of-mod ] + +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d + +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pku/pku-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +{ +ICLASS: RDPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix +OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP +} + + +{ +ICLASS: WRPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/clwb/clwb.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS: CLWB +CPL: 3 +CATEGORY: CLWB +EXTENSION: CLWB +ISA_SET: CLWB +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vnni/vnni-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPDPBUSD (VPDPBUSD-128-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSD (VPDPBUSD-256-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSD (VPDPBUSD-512-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 +IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-128-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-256-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-512-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 +IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-128-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-256-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-512-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 +IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-128-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-256-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-512-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 +IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-128-1) +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 +} + + +# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-256-1) +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 +} + + +# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-512-1) +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-128-1) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-256-1) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-512-1) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VDPBF16PS (VDPBF16PS-128-1) +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VDPBF16PS (VDPBF16PS-256-1) +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VDPBF16PS (VDPBF16PS-512-1) +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-fixup.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +UDELETE : PREFETCH_RESERVED_0F0Dr2 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VEXP2PD (VEXP2PD-512-1) +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VEXP2PS (VEXP2PS-512-1) +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) +{ +ICLASS: VGATHERPF0DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) +{ +ICLASS: VGATHERPF0DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) +{ +ICLASS: VGATHERPF0QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) +{ +ICLASS: VGATHERPF0QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) +{ +ICLASS: VGATHERPF1DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) +{ +ICLASS: VGATHERPF1DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) +{ +ICLASS: VGATHERPF1QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) +{ +ICLASS: VGATHERPF1QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VRCP28PD (VRCP28PD-512-1) +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRCP28PS (VRCP28PS-512-1) +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRCP28SD (VRCP28SD-128-1) +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRCP28SS (VRCP28SS-128-1) +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28PD (VRSQRT28PD-512-1) +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28PS (VRSQRT28PS-512-1) +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28SD (VRSQRT28SD-128-1) +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28SS (VRSQRT28SS-128-1) +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) +{ +ICLASS: VSCATTERPF0DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) +{ +ICLASS: VSCATTERPF0DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) +{ +ICLASS: VSCATTERPF0QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) +{ +ICLASS: VSCATTERPF0QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) +{ +ICLASS: VSCATTERPF1DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) +{ +ICLASS: VSCATTERPF1DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) +{ +ICLASS: VSCATTERPF1QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) +{ +ICLASS: VSCATTERPF1QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +INSTRUCTIONS():: +# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) +{ +ICLASS: PREFETCHWT1 +CPL: 3 +CATEGORY: PREFETCHWT1 +EXTENSION: PREFETCHWT1 +ISA_SET: PREFETCHWT1 +REAL_OPCODE: Y +ATTRIBUTES: PREFETCH +PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: MEM0:r:b:u8 +IFORM: PREFETCHWT1_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING V4FMADDPS (V4FMADDPS-512-1) +{ +ICLASS: V4FMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FMADDSS (V4FMADDSS-128-1) +{ +ICLASS: V4FMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDPS (V4FNMADDPS-512-1) +{ +ICLASS: V4FNMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDSS (V4FNMADDSS-128-1) +{ +ICLASS: V4FNMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VP4DPWSSD (VP4DPWSSD-512-1) +{ +ICLASS: VP4DPWSSD +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + +# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) +{ +ICLASS: VP4DPWSSDS +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-512-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-512-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-foundation-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-512-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-512-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDSD (VADDSD-128-1) +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDSS (VADDSS-128-1) +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-512-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-512-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-512-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-512-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) +{ +ICLASS: VBROADCASTF64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) +{ +ICLASS: VBROADCASTI64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-512-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-512-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPSD (VCMPSD-128-1) +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPSS (VCMPSS-128-1) +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMISD (VCOMISD-128-1) +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCOMISS (VCOMISS-128-1) +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +COMMENT: ignores rc/sae. need to adjust VL to 512 +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-512-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-512-1) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-512-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-1) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-1) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-2) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SS (VCVTSD2SS-128-1) +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-1) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-2) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-1) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-2) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 +} + + +# EMITTING VCVTSI2SS (VCVTSI2SS-128-1) +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SS (VCVTSI2SS-128-2) +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 +} +# EMITTING VCVTSS2SD (VCVTSS2SD-128-1) +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2SI (VCVTSS2SI-128-1) +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2SI (VCVTSS2SI-128-2) +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2USI (VCVTSS2USI-128-1) +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2USI (VCVTSS2USI-128-2) +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +COMMENT: ignores rc/sae. need to adjust VL to 512 +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 +} + + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-512-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-512-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VDIVSD (VDIVSD-128-1) +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVSS (VDIVSS-128-1) +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-512-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-512-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-512-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-512-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) +{ +ICLASS: VEXTRACTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) +{ +ICLASS: VEXTRACTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) +{ +ICLASS: VEXTRACTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) +{ +ICLASS: VEXTRACTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTPS (VEXTRACTPS-128-1) +{ +ICLASS: VEXTRACTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VEXTRACTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-512-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-512-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD132SD (VFMADD132SD-128-1) +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132SS (VFMADD132SS-128-1) +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-512-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-512-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213SD (VFMADD213SD-128-1) +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213SS (VFMADD213SS-128-1) +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-512-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-512-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231SD (VFMADD231SD-128-1) +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231SS (VFMADD231SS-128-1) +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-512-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-512-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132SD (VFMSUB132SD-128-1) +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132SS (VFMSUB132SS-128-1) +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-512-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-512-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213SD (VFMSUB213SD-128-1) +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213SS (VFMSUB213SS-128-1) +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-512-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-512-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231SD (VFMSUB231SD-128-1) +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231SS (VFMSUB231SS-128-1) +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-512-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-512-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132SD (VFNMADD132SD-128-1) +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132SS (VFNMADD132SS-128-1) +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-512-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-512-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213SD (VFNMADD213SD-128-1) +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213SS (VFNMADD213SS-128-1) +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-512-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-512-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231SD (VFNMADD231SD-128-1) +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231SS (VFNMADD231SS-128-1) +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-512-1) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-512-1) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-512-1) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-512-1) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-512-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-512-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETEXPSD (VGETEXPSD-128-1) +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VGETEXPSS (VGETEXPSS-128-1) +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-512-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-512-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGETMANTSD (VGETMANTSD-128-1) +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTSS (VGETMANTSS-128-1) +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) +{ +ICLASS: VINSERTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) +{ +ICLASS: VINSERTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VINSERTPS (VINSERTPS-128-1) +{ +ICLASS: VINSERTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1 +PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-512-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-512-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMAXSD (VMAXSD-128-1) +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXSS (VMAXSS-128-1) +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPD (VMINPD-512-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPS (VMINPS-512-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINSD (VMINSD-128-1) +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINSS (VMINSS-128-1) +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVD (VMOVD-128-1) +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +} + +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVD (VMOVD-128-2) +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +} + +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-512-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVHLPS (VMOVHLPS-128-1) +{ +ICLASS: VMOVHLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 +IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVHPD (VMOVHPD-128-1) +{ +ICLASS: VMOVHPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 +IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMOVHPD (VMOVHPD-128-2) +{ +ICLASS: VMOVHPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVHPS (VMOVHPS-128-1) +{ +ICLASS: VMOVHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 +IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVHPS (VMOVHPS-128-2) +{ +ICLASS: VMOVHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVLHPS (VMOVLHPS-128-1) +{ +ICLASS: VMOVLHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 +IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVLPD (VMOVLPD-128-1) +{ +ICLASS: VMOVLPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMOVLPD (VMOVLPD-128-2) +{ +ICLASS: VMOVLPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 +IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVLPS (VMOVLPS-128-1) +{ +ICLASS: VMOVLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 +IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVLPS (VMOVLPS-128-2) +{ +ICLASS: VMOVLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 +IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-512-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 +IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-512-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 +IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-512-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 +IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-512-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 +IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-1) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 +IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-2) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-3) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-4) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-1) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-2) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-3) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-4) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-512-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-512-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-1) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-2) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-3) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-4) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMULPD (VMULPD-512-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPS (VMULPS-512-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMULSD (VMULSD-128-1) +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULSS (VMULSS-128-1) +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPABSD (VPABSD-512-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-512-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 +IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPADDD (VPADDD-512-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-512-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDD (VPANDD-512-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-512-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-512-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-512-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-512-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-512-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-512-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-512-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-512-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-512-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-512-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-512-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-512-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-512-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPERMD (VPERMD-512-1) +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-512-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-512-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-512-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-512-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-512-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-512-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-512-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-512-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-512-1) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-512-2) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMPS (VPERMPS-512-1) +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-512-1) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-512-2) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-512-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-512-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-512-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-512-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-512-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-512-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-512-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-512-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-512-1) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-512-1) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-512-1) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-512-1) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VPMAXSD (VPMAXSD-512-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-512-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-512-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-512-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-512-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-512-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-512-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-512-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-512-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-512-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-512-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-512-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-512-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-512-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-512-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-512-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-512-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-512-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-512-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-512-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-512-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-512-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-512-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-512-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-512-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-512-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-512-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-512-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-512-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-512-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-512-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-512-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-512-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-512-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-512-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-512-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-512-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-512-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-512-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-512-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-512-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-512-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORQ (VPORQ-512-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLD (VPROLD-512-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-512-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-512-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-512-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORD (VPRORD-512-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-512-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-512-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-512-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-512-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-512-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +} + + +# EMITTING VPSHUFD (VPSHUFD-512-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-512-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-512-2) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-512-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-512-2) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-512-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-512-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-2) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-512-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-512-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-512-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-512-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-512-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-512-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-512-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-512-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-512-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-512-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-512-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-512-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-512-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-512-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-512-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-512-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-512-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPXORD (VPXORD-512-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-512-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-512-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-512-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRCP14SD (VRCP14SD-128-1) +{ +ICLASS: VRCP14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VRCP14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VRCP14SS (VRCP14SS-128-1) +{ +ICLASS: VRCP14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VRCP14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESD (VRNDSCALESD-128-1) +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESS (VRNDSCALESS-128-1) +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-512-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-512-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRSQRT14SD (VRSQRT14SD-128-1) +{ +ICLASS: VRSQRT14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14SS (VRSQRT14SS-128-1) +{ +ICLASS: VRSQRT14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-512-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-512-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFSD (VSCALEFSD-128-1) +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFSS (VSCALEFSS-128-1) +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-512-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-512-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-512-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-512-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 +} + + +# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-512-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-512-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-512-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-512-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSQRTSD (VSQRTSD-128-1) +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSQRTSS (VSQRTSS-128-1) +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-512-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-512-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBSD (VSUBSD-128-1) +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBSS (VSUBSS-128-1) +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUCOMISD (VUCOMISD-128-1) +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUCOMISS (VUCOMISS-128-1) +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-512-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-512-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-512-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-512-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +AVX_INSTRUCTIONS():: +# EMITTING KANDNW (KANDNW-256-1) +{ +ICLASS: KANDNW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDW (KANDW-256-1) +{ +ICLASS: KANDW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-1) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 +IFORM: KMOVW_MASKmskw_MASKu16_AVX512 +} + +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 +IFORM: KMOVW_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-2) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw +IFORM: KMOVW_MEMu16_MASKmskw_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-3) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-4) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KNOTW (KNOTW-128-1) +{ +ICLASS: KNOTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTW (KORTESTW-128-1) +{ +ICLASS: KORTESTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORW (KORW-256-1) +{ +ICLASS: KORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KSHIFTLW (KSHIFTLW-128-1) +{ +ICLASS: KSHIFTLW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRW (KSHIFTRW-128-1) +{ +ICLASS: KSHIFTRW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KUNPCKBW (KUNPCKBW-256-1) +{ +ICLASS: KUNPCKBW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORW (KXNORW-256-1) +{ +ICLASS: KXNORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORW (KXORW-256-1) +{ +ICLASS: KXORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512cd/vconflict-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 +IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-512-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +} + + +# EMITTING VPLZCNTD (VPLZCNTD-512-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-512-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-128-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPD (VADDPD-256-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-128-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDPS (VADDPS-256-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-128-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGND (VALIGND-256-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-128-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-256-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-128-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-256-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-512-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-128-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-256-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-512-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDPD (VANDPD-128-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDPD (VANDPD-256-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDPD (VANDPD-512-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDPS (VANDPS-128-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDPS (VANDPS-256-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDPS (VANDPS-512-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-128-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-256-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-128-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-256-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) +{ +ICLASS: VBROADCASTF32X8 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) +{ +ICLASS: VBROADCASTF64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) +{ +ICLASS: VBROADCASTF64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) +{ +ICLASS: VBROADCASTI32X8 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) +{ +ICLASS: VBROADCASTI64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) +{ +ICLASS: VBROADCASTI64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-128-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-256-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-128-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-256-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-128-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-256-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-128-2) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-256-2) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-128-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-256-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-3) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-3) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND() +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-128-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-256-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-512-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-128-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-256-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-128-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-256-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-128-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-128-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-256-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-256-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-128-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-128-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-256-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-256-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) +{ +ICLASS: VEXTRACTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) +{ +ICLASS: VEXTRACTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) +{ +ICLASS: VEXTRACTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) +{ +ICLASS: VEXTRACTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-128-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-256-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-128-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-256-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-128-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-256-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-128-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-256-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-128-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-256-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-128-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-256-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-128-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-256-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-128-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-256-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-128-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-256-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-128-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-256-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-128-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-256-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-128-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-256-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-128-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-256-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-128-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-256-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-128-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-256-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-128-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-256-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-128-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-256-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-128-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-256-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-128-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-256-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-512-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-128-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-256-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-512-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 +} + + +# EMITTING VFPCLASSSD (VFPCLASSSD-128-1) +{ +ICLASS: VFPCLASSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFPCLASSSS (VFPCLASSSS-128-1) +{ +ICLASS: VFPCLASSSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-128-2) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-256-2) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-128-2) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-256-2) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-128-2) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-256-2) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-128-2) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-256-2) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-128-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-256-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-128-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-256-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-128-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-256-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-128-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-256-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) +{ +ICLASS: VINSERTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) +{ +ICLASS: VINSERTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-128-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-256-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-128-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-256-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPD (VMINPD-128-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPD (VMINPD-256-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPS (VMINPS-128-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPS (VMINPS-256-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-128-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-256-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-128-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-256-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 +IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-128-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 +IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-256-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 +IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-128-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-256-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 +IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-128-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-256-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 +IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-128-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-256-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-128-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-256-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMULPD (VMULPD-128-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPD (VMULPD-256-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPS (VMULPS-128-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMULPS (VMULPS-256-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VORPD (VORPD-128-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VORPD (VORPD-256-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VORPD (VORPD-512-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VORPS (VORPS-128-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VORPS (VORPS-256-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VORPS (VORPS-512-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPABSB (VPABSB-128-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSB (VPABSB-256-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSB (VPABSB-512-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 +IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 +IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSD (VPABSD-128-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSD (VPABSD-256-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-128-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 +IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-256-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 +IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPABSW (VPABSW-128-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPABSW (VPABSW-256-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPABSW (VPABSW-512-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 +IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-128-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-256-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-512-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-128-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-256-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-512-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-128-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-256-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-512-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-128-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-256-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-512-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDB (VPADDB-128-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDB (VPADDB-256-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDB (VPADDB-512-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDD (VPADDD-128-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDD (VPADDD-256-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-128-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-256-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-128-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-256-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-512-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-128-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-256-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-512-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-128-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-256-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-512-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-128-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-256-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-512-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-128-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-256-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-512-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-128-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-256-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-512-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPANDD (VPANDD-128-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDD (VPANDD-256-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-128-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-256-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-128-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-256-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-128-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-256-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-128-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-256-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-512-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-128-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-256-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-512-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-128-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-256-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-512-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-128-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-256-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-128-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-256-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-128-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-256-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-512-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-128-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-128-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-512-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-512-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 +IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 +} + + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 +IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 +IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-256-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-256-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-128-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-256-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-512-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-128-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-256-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-128-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-256-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-512-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-128-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-256-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-128-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-256-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-128-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-256-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-512-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-128-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-256-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-512-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-128-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-256-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-128-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-256-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-128-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-256-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-512-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-128-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-256-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-128-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-256-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-512-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-128-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-256-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-128-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-256-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-128-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-256-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-512-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-128-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-256-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-512-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-128-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-256-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPERMD (VPERMD-256-1) +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-128-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-256-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-128-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-256-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-128-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-256-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-128-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-256-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-128-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-256-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-512-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-128-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-128-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-256-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-256-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-128-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-128-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-256-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-256-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-256-1) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-256-2) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMPS (VPERMPS-256-1) +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-256-1) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-256-2) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-128-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-256-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-128-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-256-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-128-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-256-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-128-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-256-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-128-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-256-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-512-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-128-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-256-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-512-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-256-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-256-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPEXTRB (VPEXTRB-128-1) +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE +PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() +OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 +} + + +# EMITTING VPEXTRD (VPEXTRD-128-1) +{ +ICLASS: VPEXTRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +} + + +# EMITTING VPEXTRQ (VPEXTRQ-128-1) +{ +ICLASS: VPEXTRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 +} + + +# EMITTING VPEXTRW (VPEXTRW-128-1) +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD +PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() +OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 +} + + +# EMITTING VPEXTRW (VPEXTRW-128-2) +{ +ICLASS: VPEXTRW_C5 +DISASM: vpextrw +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64 +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-128-2) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-256-2) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-128-2) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-256-2) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-128-2) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-256-2) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-128-2) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-256-2) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VPINSRB (VPINSRB-128-1) +{ +ICLASS: VPINSRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 +} + +{ +ICLASS: VPINSRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER_BYTE +PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPINSRD (VPINSRD-128-1) +{ +ICLASS: VPINSRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +} + +{ +ICLASS: VPINSRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPINSRQ (VPINSRQ-128-1) +{ +ICLASS: VPINSRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 +} + +{ +ICLASS: VPINSRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPINSRW (VPINSRW-128-1) +{ +ICLASS: VPINSRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 +} + +{ +ICLASS: VPINSRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER_WORD +PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPLZCNTD (VPLZCNTD-128-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPLZCNTD (VPLZCNTD-256-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-128-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-256-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-128-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-256-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-512-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-128-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-256-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-512-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-128-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-256-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-512-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSD (VPMAXSD-128-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSD (VPMAXSD-256-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-128-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-256-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-128-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-256-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-512-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-128-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-256-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-512-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-128-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-256-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-128-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-256-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-128-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-256-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-512-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-128-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-256-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-512-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-128-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-256-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-128-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-256-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-128-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-256-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-512-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-128-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-256-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-512-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-128-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-256-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-128-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-256-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-128-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-256-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-512-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-128-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 +IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-256-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 +IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-512-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 +IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-128-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 +IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-256-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 +IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-512-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 +IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-128-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-128-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-128-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-128-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-256-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-256-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-128-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-256-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-512-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-128-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-256-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-512-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-128-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-256-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-512-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-128-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-256-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-512-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-128-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 +IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-256-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 +IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-512-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 +IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-128-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-128-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-256-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-256-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-128-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-128-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-256-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-256-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-128-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-128-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-128-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-128-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-256-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-256-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-128-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-128-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-256-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-256-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-128-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-128-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-256-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-256-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-128-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-128-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-256-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-256-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-128-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-128-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-256-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-256-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-128-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-128-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-256-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-256-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-512-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-512-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-128-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-256-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-128-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-256-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-512-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-128-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-256-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-128-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 +IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-256-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 +IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-512-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 +IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-256-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-256-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-512-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-512-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-128-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-256-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-128-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-256-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-512-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-128-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-256-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-128-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-256-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-128-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-256-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-512-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-128-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-256-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-512-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-128-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-256-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-512-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-128-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-256-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-128-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-256-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-512-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-128-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-256-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-512-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-128-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-256-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-128-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-256-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORQ (VPORQ-128-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPORQ (VPORQ-256-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLD (VPROLD-128-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLD (VPROLD-256-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-128-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-256-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-128-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-256-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-128-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-256-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORD (VPRORD-128-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORD (VPRORD-256-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-128-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-256-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-128-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-256-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-128-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-256-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-128-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-256-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-512-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 +IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-128-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-256-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-128-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-256-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +} + + +# EMITTING VPSHUFB (VPSHUFB-128-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFB (VPSHUFB-256-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFB (VPSHUFB-512-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFD (VPSHUFD-128-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHUFD (VPSHUFD-256-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-128-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-256-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-512-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-128-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-256-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-512-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-128-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-128-3) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-256-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-256-3) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-128-2) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-256-2) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-512-1) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-128-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-128-3) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-256-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-256-3) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-128-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-256-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-128-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-256-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-128-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-256-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-512-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-128-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-128-3) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-256-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-256-3) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-512-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-512-2) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-128-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-128-3) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-256-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-256-3) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-128-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-128-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-256-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-256-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-128-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-256-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-128-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-256-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-128-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-256-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-512-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-128-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-128-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-256-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-256-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-512-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-512-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-128-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-128-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-256-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-256-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-128-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-256-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-512-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-128-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-128-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-256-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-256-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-128-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-256-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-128-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-256-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-128-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-256-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-512-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-128-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-128-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-256-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-256-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-512-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-512-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-128-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-256-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-512-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-128-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-256-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-128-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-256-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-128-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-256-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-512-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-128-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-256-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-512-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-128-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-256-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-512-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-128-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-256-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-512-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-128-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-256-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-512-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-128-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-256-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-128-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-256-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-512-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-128-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-256-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-128-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-256-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-128-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-256-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-512-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-128-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-256-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-512-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-128-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-256-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-128-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-256-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-128-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-256-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-512-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPXORD (VPXORD-128-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORD (VPXORD-256-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-128-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-256-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-128-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-256-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-512-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-128-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-256-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-512-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGESD (VRANGESD-128-1) +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGESS (VRANGESS-128-1) +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-128-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-256-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-128-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-256-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-128-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-256-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-512-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-128-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-256-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-512-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCESD (VREDUCESD-128-1) +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCESS (VREDUCESS-128-1) +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-128-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-256-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-128-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-256-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-128-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-256-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-128-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-256-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-128-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-256-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-128-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-256-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-128-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-256-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-128-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-256-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 +} + + +# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-128-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-256-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-128-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-256-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-128-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-256-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-128-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-256-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-128-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-256-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-128-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-256-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-128-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-256-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-128-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-256-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-128-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-256-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-128-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-256-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VXORPD (VXORPD-128-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VXORPD (VXORPD-256-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VXORPD (VXORPD-512-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VXORPS (VXORPS-128-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VXORPS (VXORPS-256-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VXORPS (VXORPS-512-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +AVX_INSTRUCTIONS():: +# EMITTING KADDB (KADDB-256-1) +{ +ICLASS: KADDB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDD (KADDD-256-1) +{ +ICLASS: KADDD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDQ (KADDQ-256-1) +{ +ICLASS: KADDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDW (KADDW-256-1) +{ +ICLASS: KADDW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDB (KANDB-256-1) +{ +ICLASS: KANDB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDD (KANDD-256-1) +{ +ICLASS: KANDD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDNB (KANDNB-256-1) +{ +ICLASS: KANDNB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDND (KANDND-256-1) +{ +ICLASS: KANDND +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDNQ (KANDNQ-256-1) +{ +ICLASS: KANDNQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDQ (KANDQ-256-1) +{ +ICLASS: KANDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-1) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 +IFORM: KMOVB_MASKmskw_MASKu8_AVX512 +} + +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 +IFORM: KMOVB_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-2) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw +IFORM: KMOVB_MEMu8_MASKmskw_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-3) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-4) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-1) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 +IFORM: KMOVD_MASKmskw_MASKu32_AVX512 +} + +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 +IFORM: KMOVD_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-2) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw +IFORM: KMOVD_MEMu32_MASKmskw_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-3) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 + +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-4) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 + +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-1) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 +IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 +} + +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 +IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-2) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw +IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-3) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 +IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-4) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw +IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 +} + + +# EMITTING KNOTB (KNOTB-128-1) +{ +ICLASS: KNOTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KNOTD (KNOTD-128-1) +{ +ICLASS: KNOTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KNOTQ (KNOTQ-128-1) +{ +ICLASS: KNOTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORB (KORB-256-1) +{ +ICLASS: KORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORD (KORD-256-1) +{ +ICLASS: KORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORQ (KORQ-256-1) +{ +ICLASS: KORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTB (KORTESTB-128-1) +{ +ICLASS: KORTESTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTD (KORTESTD-128-1) +{ +ICLASS: KORTESTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTQ (KORTESTQ-128-1) +{ +ICLASS: KORTESTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KSHIFTLB (KSHIFTLB-128-1) +{ +ICLASS: KSHIFTLB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTLD (KSHIFTLD-128-1) +{ +ICLASS: KSHIFTLD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTLQ (KSHIFTLQ-128-1) +{ +ICLASS: KSHIFTLQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRB (KSHIFTRB-128-1) +{ +ICLASS: KSHIFTRB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRD (KSHIFTRD-128-1) +{ +ICLASS: KSHIFTRD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRQ (KSHIFTRQ-128-1) +{ +ICLASS: KSHIFTRQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KTESTB (KTESTB-128-1) +{ +ICLASS: KTESTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTD (KTESTD-128-1) +{ +ICLASS: KTESTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTQ (KTESTQ-128-1) +{ +ICLASS: KTESTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTW (KTESTW-128-1) +{ +ICLASS: KTESTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KUNPCKDQ (KUNPCKDQ-256-1) +{ +ICLASS: KUNPCKDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KUNPCKWD (KUNPCKWD-256-1) +{ +ICLASS: KUNPCKWD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORB (KXNORB-256-1) +{ +ICLASS: KXNORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORD (KXNORD-256-1) +{ +ICLASS: KXNORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORQ (KXNORQ-256-1) +{ +ICLASS: KXNORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORB (KXORB-256-1) +{ +ICLASS: KXORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORD (KXORD-256-1) +{ +ICLASS: KXORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORQ (KXORQ-256-1) +{ +ICLASS: KXORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512ifma/ifma-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512vbmi/vbmi-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPERMB (VPERMB-128-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMB (VPERMB-256-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMB (VPERMB-512-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-128-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-256-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-512-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-128-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-256-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-512-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/wbnoinvd/wbnoinvd-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : WBINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 WBNOINVD=0 +OPERANDS : +PATTERN : 0x0F 0x09 WBNOINVD=1 REP!=3 +OPERANDS : +VERSION : 2 +} + +{ +ICLASS : WBNOINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : WBNOINVD +ISA_SET : WBNOINVD +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 WBNOINVD=1 f3_refining_prefix +OPERANDS : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pconfig/pconfig-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING PCONFIG (PCONFIG-N/A-1) +{ +ICLASS: PCONFIG +CPL: 0 +CATEGORY: PCONFIG +EXTENSION: PCONFIG +ISA_SET: PCONFIG +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64 +OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_EBX:crw:SUPP:d:u32 REG2=XED_REG_ECX:crw:SUPP:d:u32 REG3=XED_REG_EDX:crw:SUPP:d:u32 +IFORM: PCONFIG + +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64 +OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64 +IFORM: PCONFIG64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/bitalg/bitalg-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTB (VPOPCNTB-128-1) +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPOPCNTB (VPOPCNTB-256-1) +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 +} + +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPOPCNTB (VPOPCNTB-512-1) +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPOPCNTW (VPOPCNTW-128-1) +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPOPCNTW (VPOPCNTW-256-1) +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPOPCNTW (VPOPCNTW-512-1) +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1) +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 +} + +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 +} + + +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1) +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 +} + +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 +} + + +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1) +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 +} + +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vbmi2/vbmi2-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-128-1) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-128-2) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-256-1) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-256-2) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-512-1) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-512-2) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-128-1) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-128-2) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-256-1) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-256-2) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-512-1) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-512-2) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPSHLDD (VPSHLDD-128-1) +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHLDD (VPSHLDD-256-1) +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHLDD (VPSHLDD-512-1) +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHLDQ (VPSHLDQ-128-1) +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHLDQ (VPSHLDQ-256-1) +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHLDQ (VPSHLDQ-512-1) +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHLDVD (VPSHLDVD-128-1) +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHLDVD (VPSHLDVD-256-1) +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHLDVD (VPSHLDVD-512-1) +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHLDVQ (VPSHLDVQ-128-1) +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHLDVQ (VPSHLDVQ-256-1) +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHLDVQ (VPSHLDVQ-512-1) +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHLDVW (VPSHLDVW-128-1) +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHLDVW (VPSHLDVW-256-1) +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHLDVW (VPSHLDVW-512-1) +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHLDW (VPSHLDW-128-1) +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHLDW (VPSHLDW-256-1) +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHLDW (VPSHLDW-512-1) +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDD (VPSHRDD-128-1) +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHRDD (VPSHRDD-256-1) +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHRDD (VPSHRDD-512-1) +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHRDQ (VPSHRDQ-128-1) +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHRDQ (VPSHRDQ-256-1) +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHRDQ (VPSHRDQ-512-1) +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHRDVD (VPSHRDVD-128-1) +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHRDVD (VPSHRDVD-256-1) +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHRDVD (VPSHRDVD-512-1) +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHRDVQ (VPSHRDVQ-128-1) +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHRDVQ (VPSHRDVQ-256-1) +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHRDVQ (VPSHRDVQ-512-1) +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHRDVW (VPSHRDVW-128-1) +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHRDVW (VPSHRDVW-256-1) +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHRDVW (VPSHRDVW-512-1) +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-128-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-256-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-512-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-sse-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING GF2P8AFFINEINVQB (GF2P8AFFINEINVQB-N/A-1) +{ +ICLASS: GF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: GF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 +} + + +# EMITTING GF2P8AFFINEQB (GF2P8AFFINEQB-N/A-1) +{ +ICLASS: GF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: GF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 +} + + +# EMITTING GF2P8MULB (GF2P8MULB-N/A-1) +{ +ICLASS: GF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 +IFORM: GF2P8MULB_XMMu8_XMMu8 +} + +{ +ICLASS: GF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 +IFORM: GF2P8MULB_XMMu8_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-evex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-128-1) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-256-1) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-512-1) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-2) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-2) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-2) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-2) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-128-2) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_XMMu8_XMMu8 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_XMMu8_MEMu8 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-256-2) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_YMMu8_YMMu8 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_YMMu8_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/vaes-evex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VAESDEC (VAESDEC-128-1) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDEC (VAESDEC-256-1) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDEC (VAESDEC-512-1) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-128-1) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-256-1) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-512-1) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENC (VAESENC-128-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESENC_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESENC_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENC (VAESENC-256-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENC (VAESENC-512-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-128-1) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-256-1) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-512-1) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b +IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/vaes-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VAESDEC (VAESDEC-256-2) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-256-2) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESENC (VAESENC-256-2) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-256-2) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-2) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: VPCLMULQDQ +ISA_SET: VPCLMULQDQ +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: VPCLMULQDQ +ISA_SET: VPCLMULQDQ +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-vl/vpopcntdq-vl-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-128-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTD (VPOPCNTD-256-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-128-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-256-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vp2intersect/vp2intersect-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VP2INTERSECTD (VP2INTERSECTD-128-1) +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32 +IFORM: VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VP2INTERSECTD (VP2INTERSECTD-256-1) +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32 +IFORM: VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VP2INTERSECTD (VP2INTERSECTD-512-1) +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32 +IFORM: VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-128-1) +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 +IFORM: VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-256-1) +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 +IFORM: VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-512-1) +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 +IFORM: VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/keylocker/keylocker-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING AESDEC128KL (AESDEC128KL-N/A-1) +{ +ICLASS: AESDEC128KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:m384:u8 +IFORM: AESDEC128KL_XMMu8_MEMu8 +} + + +# EMITTING AESDEC256KL (AESDEC256KL-N/A-1) +{ +ICLASS: AESDEC256KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDF f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:zd:u8 +IFORM: AESDEC256KL_XMMu8_MEMu8 +} + + +# EMITTING AESDECWIDE128KL (AESDECWIDE128KL-N/A-1) +{ +ICLASS: AESDECWIDE128KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:m384:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESDECWIDE128KL_MEMu8 +} + + +# EMITTING AESDECWIDE256KL (AESDECWIDE256KL-N/A-1) +{ +ICLASS: AESDECWIDE256KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:zd:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESDECWIDE256KL_MEMu8 +} + + +# EMITTING AESENC128KL (AESENC128KL-N/A-1) +{ +ICLASS: AESENC128KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDC f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:m384:u8 +IFORM: AESENC128KL_XMMu8_MEMu8 +} + + +# EMITTING AESENC256KL (AESENC256KL-N/A-1) +{ +ICLASS: AESENC256KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDE f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:zd:u8 +IFORM: AESENC256KL_XMMu8_MEMu8 +} + + +# EMITTING AESENCWIDE128KL (AESENCWIDE128KL-N/A-1) +{ +ICLASS: AESENCWIDE128KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:m384:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESENCWIDE128KL_MEMu8 +} + + +# EMITTING AESENCWIDE256KL (AESENCWIDE256KL-N/A-1) +{ +ICLASS: AESENCWIDE256KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:zd:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESENCWIDE256KL_MEMu8 +} + + +# EMITTING ENCODEKEY128 (ENCODEKEY128-N/A-1) +{ +ICLASS: ENCODEKEY128 +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-0 of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xFA MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS: REG0=GPR32_R():w:d:u8 REG1=GPR32_B():r:d:u8 REG2=XED_REG_XMM0:rw:SUPP:dq:u8 REG3=XED_REG_XMM1:w:SUPP:dq:u8 REG4=XED_REG_XMM2:w:SUPP:dq:u8 REG5=XED_REG_XMM4:w:SUPP:dq:u8 REG6=XED_REG_XMM5:w:SUPP:dq:u8 REG7=XED_REG_XMM6:w:SUPP:dq:u8 +IFORM: ENCODEKEY128_GPR32u8_GPR32u8 +} + + +# EMITTING ENCODEKEY256 (ENCODEKEY256-N/A-1) +{ +ICLASS: ENCODEKEY256 +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-0 of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xFB MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS: REG0=GPR32_R():w:d:u8 REG1=GPR32_B():r:d:u8 REG2=XED_REG_XMM0:rw:SUPP:dq:u8 REG3=XED_REG_XMM1:rw:SUPP:dq:u8 REG4=XED_REG_XMM2:w:SUPP:dq:u8 REG5=XED_REG_XMM3:w:SUPP:dq:u8 REG6=XED_REG_XMM4:w:SUPP:dq:u8 REG7=XED_REG_XMM5:w:SUPP:dq:u8 REG8=XED_REG_XMM6:w:SUPP:dq:u8 +IFORM: ENCODEKEY256_GPR32u8_GPR32u8 +} + + +# EMITTING LOADIWKEY (LOADIWKEY-N/A-1) +{ +ICLASS: LOADIWKEY +CPL: 0 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDC f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XED_REG_EAX:r:SUPP:d:u32 REG3=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: LOADIWKEY_XMMu8_XMMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hreset/hreset-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING HRESET (HRESET-N/A-1) +{ +ICLASS: HRESET +CPL: 0 +CATEGORY: HRESET +EXTENSION: HRESET +ISA_SET: HRESET +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xF0 MOD[0b11] MOD=3 REG[0b000] RM[0b000] f3_refining_prefix UIMM8() +OPERANDS: IMM0:r:b REG0=XED_REG_EAX:r:SUPP:d:u32 +IFORM: HRESET_IMM8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/avx-vnni-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VPDPBUSD (VPDPBUSD-128-2) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPBUSD_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPBUSD_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPBUSD (VPDPBUSD-256-2) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPBUSD_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPBUSD_YMMi32_YMMu32_MEMu32 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-128-2) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-256-2) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_YMMu32_MEMu32 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-128-2) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPWSSD_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPWSSD_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-256-2) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPWSSD_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPWSSD_YMMi32_YMMu32_MEMu32 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-128-2) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-256-2) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_YMMu32_MEMu32 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/uintr/uintr-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLUI (CLUI-N/A-1) +{ +ICLASS: CLUI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_UIF:w:SUPP:i1 +IFORM: CLUI +} + + +# EMITTING SENDUIPI (SENDUIPI-N/A-1) +{ +ICLASS: SENDUIPI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=GPR32_B():r:d:u32 +IFORM: SENDUIPI_GPR32u32 +} + + +# EMITTING STUI (STUI-N/A-1) +{ +ICLASS: STUI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_UIF:w:SUPP:i1 +IFORM: STUI +} + + +# EMITTING TESTUI (TESTUI-N/A-1) +{ +ICLASS: TESTUI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_UIF:r:SUPP:i1 +IFORM: TESTUI +} + + +# EMITTING UIRET (UIRET-N/A-1) +{ +ICLASS: UIRET +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64 +OPERANDS: REG0=rIP():w:SUPP REG1=XED_REG_STACKPOP:r:SUPP:spw +IFORM: UIRET +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-spr-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING LDTILECFG (LDTILECFG-128-1) +{ +ICLASS: LDTILECFG +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E1 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: MEM0:r:zd +IFORM: LDTILECFG_MEM +} + + +# EMITTING STTILECFG (STTILECFG-128-1) +{ +ICLASS: STTILECFG +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E2 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: MEM0:w:zd +IFORM: STTILECFG_MEM +} + + +# EMITTING TDPBF16PS (TDPBF16PS-128-1) +{ +ICLASS: TDPBF16PS +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_BF16 +ISA_SET: AMX_BF16 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBF16PS_TMMf32_TMMu32_TMMu32 +} + + +# EMITTING TDPBSSD (TDPBSSD-128-1) +{ +ICLASS: TDPBSSD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBSSD_TMMi32_TMMu32_TMMu32 +} + + +# EMITTING TDPBSUD (TDPBSUD-128-1) +{ +ICLASS: TDPBSUD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBSUD_TMMi32_TMMu32_TMMu32 +} + + +# EMITTING TDPBUSD (TDPBUSD-128-1) +{ +ICLASS: TDPBUSD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBUSD_TMMi32_TMMu32_TMMu32 +} + + +# EMITTING TDPBUUD (TDPBUUD-128-1) +{ +ICLASS: TDPBUUD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:u32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBUUD_TMMu32_TMMu32_TMMu32 +} + + +# EMITTING TILELOADD (TILELOADD-128-1) +{ +ICLASS: TILELOADD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E3 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED +PATTERN: VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32 +IFORM: TILELOADD_TMMu32_MEMu32 +} + + +# EMITTING TILELOADDT1 (TILELOADDT1-128-1) +{ +ICLASS: TILELOADDT1 +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E3 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED +PATTERN: VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32 +IFORM: TILELOADDT1_TMMu32_MEMu32 +} + + +# EMITTING TILERELEASE (TILERELEASE-128-1) +{ +ICLASS: TILERELEASE +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E6 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 VNP V0F38 MOD[0b11] MOD=3 REG[0b000] RM[0b000] VL128 W0 mode64 NOVSR +OPERANDS: +IFORM: TILERELEASE +} + + +# EMITTING TILESTORED (TILESTORED-128-1) +{ +ICLASS: TILESTORED +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E3 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED +PATTERN: VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: MEM0:w:ptr:u32 REG0=TMM_R():r:tv:u32 +IFORM: TILESTORED_MEMu32_TMMu32 +} + + +# EMITTING TILEZERO (TILEZERO-128-1) +{ +ICLASS: TILEZERO +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E5 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR +OPERANDS: REG0=TMM_R():w:tv:u32 +IFORM: TILEZERO_TMMu32 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/enqcmd/enqcmd-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING ENQCMD (ENQCMD-N/A-1) +{ +ICLASS: ENQCMD +CPL: 3 +CATEGORY: ENQCMD +EXTENSION: ENQCMD +ISA_SET: ENQCMD +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 +IFORM: ENQCMD_GPRa_MEMu32 +} + + +# EMITTING ENQCMDS (ENQCMDS-N/A-1) +{ +ICLASS: ENQCMDS +CPL: 3 +CATEGORY: ENQCMD +EXTENSION: ENQCMD +ISA_SET: ENQCMD +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 +IFORM: ENQCMDS_GPRa_MEMu32 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tsx-ldtrk/tsx-ldtrk-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +# EMITTING XRESLDTRK (XRESLDTRK-N/A-1) +{ +ICLASS: XRESLDTRK +CPL: 3 +CATEGORY: TSX_LDTRK +EXTENSION: TSX_LDTRK +ISA_SET: TSX_LDTRK +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix +OPERANDS: +IFORM: XRESLDTRK +} + + +# EMITTING XSUSLDTRK (XSUSLDTRK-N/A-1) +{ +ICLASS: XSUSLDTRK +CPL: 3 +CATEGORY: TSX_LDTRK +EXTENSION: TSX_LDTRK +ISA_SET: TSX_LDTRK +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix +OPERANDS: +IFORM: XSUSLDTRK +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/serialize/serialize-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SERIALIZE (SERIALIZE-N/A-1) +{ +ICLASS: SERIALIZE +CPL: 3 +CATEGORY: SERIALIZE +EXTENSION: SERIALIZE +ISA_SET: SERIALIZE +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix +OPERANDS: +IFORM: SERIALIZE +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tdx/tdx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SEAMCALL (SEAMCALL-N/A-1) +{ +ICLASS: SEAMCALL +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RAX:rw:SUPP:q:u64 +IFORM: SEAMCALL +} + + +# EMITTING SEAMOPS (SEAMOPS-N/A-1) +{ +ICLASS: SEAMOPS +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RAX:rw:SUPP:q:u64 +IFORM: SEAMOPS +} + + +# EMITTING SEAMRET (SEAMRET-N/A-1) +{ +ICLASS: SEAMRET +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64 +OPERANDS: +IFORM: SEAMRET +} + + +# EMITTING TDCALL (TDCALL-N/A-1) +{ +ICLASS: TDCALL +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RCX:r:SUPP:q:u64 +IFORM: TDCALL +} + + +# EMITTING TDCALL (TDCALL-N/A-2) +{ +ICLASS: TDCALL +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64 +OPERANDS: REG0=XED_REG_ECX:r:SUPP:d:u32 +IFORM: TDCALL +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-fp16-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPH (VADDPH-128-1) +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VADDPH (VADDPH-256-1) +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VADDPH (VADDPH-512-1) +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VADDSH (VADDSH-128-1) +{ +ICLASS: VADDSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VADDSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VADDSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VCMPPH (VCMPPH-128-1) +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCMPPH (VCMPPH-256-1) +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCMPPH (VCMPPH-512-1) +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCMPSH (VCMPSH-128-1) +{ +ICLASS: VCMPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCOMISH (VCOMISH-128-1) +{ +ICLASS: VCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16 +IFORM: VCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: DISP8_SCALAR MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VCOMISH_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VCVTDQ2PH (VCVTDQ2PH-128-1) +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 +} + + +# EMITTING VCVTDQ2PH (VCVTDQ2PH-256-1) +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 +} + + +# EMITTING VCVTDQ2PH (VCVTDQ2PH-512-1) +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2PH (VCVTPD2PH-128-1) +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2PH (VCVTPD2PH-256-1) +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2PH (VCVTPD2PH-512-1) +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPH2DQ (VCVTPH2DQ-128-1) +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2DQ (VCVTPH2DQ-256-1) +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2DQ (VCVTPH2DQ-512-1) +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PD (VCVTPH2PD-128-1) +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PD (VCVTPH2PD-256-1) +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PD (VCVTPH2PD-512-1) +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PSX (VCVTPH2PSX-128-1) +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PSX (VCVTPH2PSX-256-1) +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PSX (VCVTPH2PSX-512-1) +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2QQ (VCVTPH2QQ-128-1) +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2QQ (VCVTPH2QQ-256-1) +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2QQ (VCVTPH2QQ-512-1) +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-128-1) +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-256-1) +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-512-1) +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-128-1) +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-256-1) +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-512-1) +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UW (VCVTPH2UW-128-1) +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UW (VCVTPH2UW-256-1) +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UW (VCVTPH2UW-512-1) +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2W (VCVTPH2W-128-1) +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2W (VCVTPH2W-256-1) +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2W (VCVTPH2W-512-1) +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2PHX (VCVTPS2PHX-128-1) +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VCVTPS2PHX (VCVTPS2PHX-256-1) +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VCVTPS2PHX (VCVTPS2PHX-512-1) +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VCVTQQ2PH (VCVTQQ2PH-128-1) +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTQQ2PH (VCVTQQ2PH-256-1) +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTQQ2PH (VCVTQQ2PH-512-1) +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTSD2SH (VCVTSD2SH-128-1) +{ +ICLASS: VCVTSD2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCVTSH2SD (VCVTSH2SD-128-1) +{ +ICLASS: VCVTSH2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:wrd:f16 +IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-mode64) +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-not64) +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SI (VCVTSH2SI-128-2) +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16 +IFORM: VCVTSH2SI_GPR64i64_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SS (VCVTSH2SS-128-1) +{ +ICLASS: VCVTSH2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:wrd:f16 +IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-mode64) +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-not64) +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2USI (VCVTSH2USI-128-2) +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16 +IFORM: VCVTSH2USI_GPR64u64_MEMf16_AVX512 +} + + +# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-mode64) +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-not64) +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SH (VCVTSI2SH-128-2) +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:i64 +IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 +} + + +# EMITTING VCVTSS2SH (VCVTSS2SH-128-1) +{ +ICLASS: VCVTSS2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:d:f32 +IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 +} + + +# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-128-1) +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-256-1) +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-512-1) +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-128-1) +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-256-1) +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-512-1) +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-128-1) +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-256-1) +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-512-1) +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-128-1) +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-256-1) +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-512-1) +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UW (VCVTTPH2UW-128-1) +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UW (VCVTTPH2UW-256-1) +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UW (VCVTTPH2UW-512-1) +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2W (VCVTTPH2W-128-1) +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2W (VCVTTPH2W-256-1) +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2W (VCVTTPH2W-512-1) +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-mode64) +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-not64) +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-2) +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16 +IFORM: VCVTTSH2SI_GPR64i64_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-mode64) +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-not64) +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-2) +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16 +IFORM: VCVTTSH2USI_GPR64u64_MEMf16_AVX512 +} + + +# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-128-1) +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-256-1) +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-512-1) +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-128-1) +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-256-1) +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-512-1) +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-mode64) +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-not64) +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-2) +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:u64 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 +} + + +# EMITTING VCVTUW2PH (VCVTUW2PH-128-1) +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR +IFORM: VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VCVTUW2PH (VCVTUW2PH-256-1) +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR +IFORM: VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VCVTUW2PH (VCVTUW2PH-512-1) +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR +IFORM: VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VCVTW2PH (VCVTW2PH-128-1) +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR +IFORM: VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VCVTW2PH (VCVTW2PH-256-1) +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR +IFORM: VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VCVTW2PH (VCVTW2PH-512-1) +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR +IFORM: VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VDIVPH (VDIVPH-128-1) +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VDIVPH (VDIVPH-256-1) +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VDIVPH (VDIVPH-512-1) +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VDIVSH (VDIVSH-128-1) +{ +ICLASS: VDIVSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VDIVSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VDIVSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFCMADDCPH (VFCMADDCPH-128-1) +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMADDCPH (VFCMADDCPH-256-1) +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMADDCPH (VFCMADDCPH-512-1) +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMADDCSH (VFCMADDCSH-128-1) +{ +ICLASS: VFCMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCPH (VFCMULCPH-128-1) +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCPH (VFCMULCPH-256-1) +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCPH (VFCMULCPH-512-1) +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCSH (VFCMULCSH-128-1) +{ +ICLASS: VFCMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADD132PH (VFMADD132PH-128-1) +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD132PH (VFMADD132PH-256-1) +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD132PH (VFMADD132PH-512-1) +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD132SH (VFMADD132SH-128-1) +{ +ICLASS: VFMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213PH (VFMADD213PH-128-1) +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213PH (VFMADD213PH-256-1) +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213PH (VFMADD213PH-512-1) +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213SH (VFMADD213SH-128-1) +{ +ICLASS: VFMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231PH (VFMADD231PH-128-1) +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231PH (VFMADD231PH-256-1) +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231PH (VFMADD231PH-512-1) +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231SH (VFMADD231SH-128-1) +{ +ICLASS: VFMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDCPH (VFMADDCPH-128-1) +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDCPH (VFMADDCPH-256-1) +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDCPH (VFMADDCPH-512-1) +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDCSH (VFMADDCSH-128-1) +{ +ICLASS: VFMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-128-1) +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-256-1) +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-512-1) +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-128-1) +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-256-1) +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-512-1) +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-128-1) +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-256-1) +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-512-1) +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132PH (VFMSUB132PH-128-1) +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132PH (VFMSUB132PH-256-1) +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132PH (VFMSUB132PH-512-1) +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132SH (VFMSUB132SH-128-1) +{ +ICLASS: VFMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213PH (VFMSUB213PH-128-1) +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213PH (VFMSUB213PH-256-1) +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213PH (VFMSUB213PH-512-1) +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213SH (VFMSUB213SH-128-1) +{ +ICLASS: VFMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231PH (VFMSUB231PH-128-1) +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231PH (VFMSUB231PH-256-1) +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231PH (VFMSUB231PH-512-1) +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231SH (VFMSUB231SH-128-1) +{ +ICLASS: VFMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-128-1) +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-256-1) +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-512-1) +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-128-1) +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-256-1) +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-512-1) +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-128-1) +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-256-1) +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-512-1) +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMULCPH (VFMULCPH-128-1) +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMULCPH (VFMULCPH-256-1) +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMULCPH (VFMULCPH-512-1) +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMULCSH (VFMULCSH-128-1) +{ +ICLASS: VFMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFNMADD132PH (VFNMADD132PH-128-1) +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD132PH (VFNMADD132PH-256-1) +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD132PH (VFNMADD132PH-512-1) +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD132SH (VFNMADD132SH-128-1) +{ +ICLASS: VFNMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213PH (VFNMADD213PH-128-1) +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213PH (VFNMADD213PH-256-1) +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213PH (VFNMADD213PH-512-1) +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213SH (VFNMADD213SH-128-1) +{ +ICLASS: VFNMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231PH (VFNMADD231PH-128-1) +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231PH (VFNMADD231PH-256-1) +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231PH (VFNMADD231PH-512-1) +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231SH (VFNMADD231SH-128-1) +{ +ICLASS: VFNMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132PH (VFNMSUB132PH-128-1) +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132PH (VFNMSUB132PH-256-1) +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132PH (VFNMSUB132PH-512-1) +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132SH (VFNMSUB132SH-128-1) +{ +ICLASS: VFNMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213PH (VFNMSUB213PH-128-1) +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213PH (VFNMSUB213PH-256-1) +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213PH (VFNMSUB213PH-512-1) +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213SH (VFNMSUB213SH-128-1) +{ +ICLASS: VFNMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231PH (VFNMSUB231PH-128-1) +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231PH (VFNMSUB231PH-256-1) +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231PH (VFNMSUB231PH-512-1) +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231SH (VFNMSUB231SH-128-1) +{ +ICLASS: VFNMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFPCLASSPH (VFPCLASSPH-128-1) +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 +} + + +# EMITTING VFPCLASSPH (VFPCLASSPH-256-1) +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 +} + + +# EMITTING VFPCLASSPH (VFPCLASSPH-512-1) +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 +} + + +# EMITTING VFPCLASSSH (VFPCLASSSH-128-1) +{ +ICLASS: VFPCLASSSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x67 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x67 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:wrd:f16 IMM0:r:b +IFORM: VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETEXPPH (VGETEXPPH-128-1) +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VGETEXPPH (VGETEXPPH-256-1) +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VGETEXPPH (VGETEXPPH-512-1) +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VGETEXPSH (VGETEXPSH-128-1) +{ +ICLASS: VGETEXPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VGETEXPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VGETEXPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VGETMANTPH (VGETMANTPH-128-1) +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETMANTPH (VGETMANTPH-256-1) +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETMANTPH (VGETMANTPH-512-1) +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETMANTSH (VGETMANTSH-128-1) +{ +ICLASS: VGETMANTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VMAXPH (VMAXPH-128-1) +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMAXPH (VMAXPH-256-1) +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VMAXPH (VMAXPH-512-1) +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VMAXSH (VMAXSH-128-1) +{ +ICLASS: VMAXSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMAXSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMAXSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINPH (VMINPH-128-1) +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINPH (VMINPH-256-1) +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINPH (VMINPH-512-1) +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINSH (VMINSH-128-1) +{ +ICLASS: VMINSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMINSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMINSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-1) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x10 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:f16 +IFORM: VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-5) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x11 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:wrd:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f16 +IFORM: VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-6) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-7) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_R3():r:dq:f16 +IFORM: VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + + +# EMITTING VMOVW (VMOVW-128-1) +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=GPR32_B():r:d:f16 +IFORM: VMOVW_XMMf16_GPR32f16_AVX512 +} + +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 MEM0:r:wrd:f16 +IFORM: VMOVW_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMOVW (VMOVW-128-2) +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:f16 REG1=XMM_R3():r:dq:f16 +IFORM: VMOVW_GPR32f16_XMMf16_AVX512 +} + +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:wrd:f16 REG0=XMM_R3():r:dq:f16 +IFORM: VMOVW_MEMf16_XMMf16_AVX512 +} + + +# EMITTING VMULPH (VMULPH-128-1) +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMULPH (VMULPH-256-1) +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VMULPH (VMULPH-512-1) +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VMULSH (VMULSH-128-1) +{ +ICLASS: VMULSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMULSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMULSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VRCPPH (VRCPPH-128-1) +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRCPPH (VRCPPH-256-1) +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRCPPH (VRCPPH-512-1) +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRCPSH (VRCPSH-128-1) +{ +ICLASS: VRCPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x4D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VRCPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x4D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VREDUCEPH (VREDUCEPH-128-1) +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VREDUCEPH (VREDUCEPH-256-1) +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VREDUCEPH (VREDUCEPH-512-1) +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VREDUCESH (VREDUCESH-128-1) +{ +ICLASS: VREDUCESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPH (VRNDSCALEPH-128-1) +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPH (VRNDSCALEPH-256-1) +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPH (VRNDSCALEPH-512-1) +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESH (VRNDSCALESH-128-1) +{ +ICLASS: VRNDSCALESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRSQRTPH (VRSQRTPH-128-1) +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRSQRTPH (VRSQRTPH-256-1) +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRSQRTPH (VRSQRTPH-512-1) +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRSQRTSH (VRSQRTSH-128-1) +{ +ICLASS: VRSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x4F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VRSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x4F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFPH (VSCALEFPH-128-1) +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFPH (VSCALEFPH-256-1) +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFPH (VSCALEFPH-512-1) +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFSH (VSCALEFSH-128-1) +{ +ICLASS: VSCALEFSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSCALEFSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSCALEFSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSQRTPH (VSQRTPH-128-1) +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VSQRTPH (VSQRTPH-256-1) +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VSQRTPH (VSQRTPH-512-1) +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VSQRTSH (VSQRTSH-128-1) +{ +ICLASS: VSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBPH (VSUBPH-128-1) +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBPH (VSUBPH-256-1) +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBPH (VSUBPH-512-1) +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBSH (VSUBSH-128-1) +{ +ICLASS: VSUBSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSUBSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSUBSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VUCOMISH (VUCOMISH-128-1) +{ +ICLASS: VUCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16 +IFORM: VUCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VUCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VUCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VUCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: DISP8_SCALAR MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VUCOMISH_XMMf16_MEMf16_AVX512 +} + + diff --git a/CodeVirtualizer/build/obj/dgen/all-dec-patterns.txt b/CodeVirtualizer/build/obj/dgen/all-dec-patterns.txt new file mode 100644 index 0000000..d7c6bb3 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-dec-patterns.txt @@ -0,0 +1,3857 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-prefixes.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +################################################################# +## file: xed-prefixes.txt +################################################################# + +# SYNTAX: +# conditions and input bytes | output-mode-state and captures... + + +# FIXME: make ICLASS a possible field? +# Remove the segment override if any supplied, from an LEA +REMOVE_SEGMENT():: +mode16 | SEG0=XED_REG_INVALID +mode32 | SEG0=XED_REG_INVALID +mode64 | SEG0=XED_REG_INVALID +# FIXME 2007-07-10 full "otherwise" RHS's are not supported yet in decoder. +#otherwise | SEG0=XED_REG_INVALID + + + +PREFIXES():: + +# The presence of the REX itself and the REXW are state bits because +# they control decoding downstream. + +# +# 64b mode prefixes +# + +# rex prefixes +mode64 0b0100 wrxb | XED_RESET REX=1 REXW=w REXR=r REXX=x REXB=b + +# Note that because of the REX rules, if we see a legacy prefix after +# a rex prefix, we have to ignore the rex prefix and all its captures! +# (reset_rex). The new state bits override existing captures and state +# bits. That explains all the rex stuff. + +# other prefixes + +# NOTE: double denotation of f2/f3/osz.(eg f2_prefix and +# f2_refining_prefix). That 2nd allows for table lookups indexing to +# the 2B table. + +mode64 0xf2 MODE_FIRST_PREFIX=0 | XED_RESET reset_rex f2_prefix refining_f2 +mode64 0xf3 MODE_FIRST_PREFIX=0 | XED_RESET reset_rex f3_prefix refining_f3 +mode64 0xf2 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET reset_rex f2_prefix refining_f2 +mode64 0xf3 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET reset_rex f3_prefix refining_f3 +mode64 0xf2 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET reset_rex +mode64 0xf3 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET reset_rex + + +# 2009-08-17: The 66_prefix (OSZ=1) gets zero'ed by some instructions +# that use 66 as a refining prefix. To ensure we have a 66 prefix +# indicator, we also set PREFIX66=1. +mode64 0x66 | XED_RESET 66_prefix PREFIX66=1 reset_rex + +mode64 0x67 | XED_RESET 67_prefix reset_rex +mode64 0xf0 | XED_RESET lock_prefix reset_rex + +# CS and DS prefixes could be branch hints. cs_prefix and ds_prefix +# translate to the correct values for the BRANCH_HINT nonterminal. +mode64 0x2e | XED_RESET HINT=1 reset_rex +mode64 0x3e | XED_RESET HINT=2 reset_rex + +mode64 0x26 | XED_RESET reset_rex +mode64 0x64 | XED_RESET fs_prefix reset_rex +mode64 0x65 | XED_RESET gs_prefix reset_rex +mode64 0x36 | XED_RESET reset_rex + +# +# 32b mode prefixes +# + +mode32 0xf2 MODE_FIRST_PREFIX=0 | XED_RESET f2_prefix refining_f2 +mode32 0xf3 MODE_FIRST_PREFIX=0 | XED_RESET f3_prefix refining_f3 +mode32 0xf2 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f2_prefix refining_f2 +mode32 0xf3 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f3_prefix refining_f3 +mode32 0xf2 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET +mode32 0xf3 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET + +mode32 0x66 | XED_RESET 66_prefix PREFIX66=1 +mode32 0x67 | XED_RESET 67_prefix +mode32 0xf0 | XED_RESET lock_prefix +# CS and DS prefixes could be branch hints. cs_prefix and ds_prefix +# translate to the correct values for the BRANCH_HINT nonterminal. +mode32 0x2e | XED_RESET cs_prefix HINT=1 +mode32 0x3e | XED_RESET ds_prefix HINT=2 + +mode32 0x26 | XED_RESET es_prefix +mode32 0x64 | XED_RESET fs_prefix +mode32 0x65 | XED_RESET gs_prefix +mode32 0x36 | XED_RESET ss_prefix + +# +# 16b mode prefixes +# + + +mode16 0xf2 MODE_FIRST_PREFIX=0 | XED_RESET f2_prefix refining_f2 +mode16 0xf3 MODE_FIRST_PREFIX=0 | XED_RESET f3_prefix refining_f3 +mode16 0xf2 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f2_prefix refining_f2 +mode16 0xf3 MODE_FIRST_PREFIX=1 REP=0 | XED_RESET f3_prefix refining_f3 +mode16 0xf2 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET +mode16 0xf3 MODE_FIRST_PREFIX=1 REP!=0 | XED_RESET + +mode16 0x66 | XED_RESET 66_prefix PREFIX66=1 +mode16 0x67 | XED_RESET 67_prefix +mode16 0xf0 | XED_RESET lock_prefix +# CS and DS prefixes could be branch hints. cs_prefix and ds_prefix +# translate to the correct values for the BRANCH_HINT nonterminal. +mode16 0x2e | XED_RESET cs_prefix HINT=1 +mode16 0x3e | XED_RESET ds_prefix HINT=2 + +mode16 0x26 | XED_RESET es_prefix +mode16 0x64 | XED_RESET fs_prefix +mode16 0x65 | XED_RESET gs_prefix +mode16 0x36 | XED_RESET ss_prefix + +# This is the epsilon action indicating that it is okay to +# accept nothing at this point in the traversal. +otherwise | + +BRANCH_HINT():: +HINT=0 | +HINT=1 | HINT=3 +HINT=2 | HINT=4 + +CET_NO_TRACK():: +HINT=0 | +HINT=1 | +HINT=2 | HINT=5 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-reg-tables.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +######################################################################## +## file: xed-reg-tables.txt +######################################################################## + +# Need to handle flags, rIP, seg-selectors, pseudo regs +# Also does not specify register width + +# What about something like this: +# op1=GPRv_R():rw +# we need to know what to bind the result to ultimately. +# Just specifying a register is confusing to me. Don't know where to store it. +# Have a "store-here" location for this kind of thing? + +####################################################################### +# Expand the generic registers using the effective address size EASZ +####################################################################### +xed_reg_enum_t ArAX():: +EASZ=1 | OUTREG=XED_REG_AX +EASZ=2 | OUTREG=XED_REG_EAX +EASZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t ArBX():: +EASZ=1 | OUTREG=XED_REG_BX +EASZ=2 | OUTREG=XED_REG_EBX +EASZ=3 | OUTREG=XED_REG_RBX +xed_reg_enum_t ArCX():: +EASZ=1 | OUTREG=XED_REG_CX +EASZ=2 | OUTREG=XED_REG_ECX +EASZ=3 | OUTREG=XED_REG_RCX +xed_reg_enum_t ArDX():: +EASZ=1 | OUTREG=XED_REG_DX +EASZ=2 | OUTREG=XED_REG_EDX +EASZ=3 | OUTREG=XED_REG_RDX + +xed_reg_enum_t ArSI():: +EASZ=1 | OUTREG=XED_REG_SI +EASZ=2 | OUTREG=XED_REG_ESI +EASZ=3 | OUTREG=XED_REG_RSI +xed_reg_enum_t ArDI():: +EASZ=1 | OUTREG=XED_REG_DI +EASZ=2 | OUTREG=XED_REG_EDI +EASZ=3 | OUTREG=XED_REG_RDI +xed_reg_enum_t ArSP():: +EASZ=1 | OUTREG=XED_REG_SP +EASZ=2 | OUTREG=XED_REG_ESP +EASZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t ArBP():: +EASZ=1 | OUTREG=XED_REG_BP +EASZ=2 | OUTREG=XED_REG_EBP +EASZ=3 | OUTREG=XED_REG_RBP + +xed_reg_enum_t SrSP():: +smode16 | OUTREG=XED_REG_SP +smode32 | OUTREG=XED_REG_ESP +smode64 | OUTREG=XED_REG_RSP +xed_reg_enum_t SrBP():: +smode16 | OUTREG=XED_REG_BP +smode32 | OUTREG=XED_REG_EBP +smode64 | OUTREG=XED_REG_RBP + +xed_reg_enum_t Ar8():: +EASZ=1 | OUTREG=XED_REG_R8W +EASZ=2 | OUTREG=XED_REG_R8D +EASZ=3 | OUTREG=XED_REG_R8 +xed_reg_enum_t Ar9():: +EASZ=1 | OUTREG=XED_REG_R9W +EASZ=2 | OUTREG=XED_REG_R9D +EASZ=3 | OUTREG=XED_REG_R9 +xed_reg_enum_t Ar10():: +EASZ=1 | OUTREG=XED_REG_R10W +EASZ=2 | OUTREG=XED_REG_R10D +EASZ=3 | OUTREG=XED_REG_R10 +xed_reg_enum_t Ar11():: +EASZ=1 | OUTREG=XED_REG_R11W +EASZ=2 | OUTREG=XED_REG_R11D +EASZ=3 | OUTREG=XED_REG_R11 +xed_reg_enum_t Ar12():: +EASZ=1 | OUTREG=XED_REG_R12W +EASZ=2 | OUTREG=XED_REG_R12D +EASZ=3 | OUTREG=XED_REG_R12 +xed_reg_enum_t Ar13():: +EASZ=1 | OUTREG=XED_REG_R13W +EASZ=2 | OUTREG=XED_REG_R13D +EASZ=3 | OUTREG=XED_REG_R13 +xed_reg_enum_t Ar14():: +EASZ=1 | OUTREG=XED_REG_R14W +EASZ=2 | OUTREG=XED_REG_R14D +EASZ=3 | OUTREG=XED_REG_R14 +xed_reg_enum_t Ar15():: +EASZ=1 | OUTREG=XED_REG_R15W +EASZ=2 | OUTREG=XED_REG_R15D +EASZ=3 | OUTREG=XED_REG_R15 + +xed_reg_enum_t rIP():: +mode16 | OUTREG=XED_REG_EIP +mode32 | OUTREG=XED_REG_EIP +mode64 | OUTREG=XED_REG_RIP + +xed_reg_enum_t rIPa():: +EASZ=2 | OUTREG=XED_REG_EIP +EASZ=3 | OUTREG=XED_REG_RIP + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 32b +####################################################################### + + +xed_reg_enum_t OeAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_EAX + + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 64b +####################################################################### + +xed_reg_enum_t OrAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t OrDX():: +EOSZ=1 | OUTREG=XED_REG_DX +EOSZ=2 | OUTREG=XED_REG_EDX +EOSZ=3 | OUTREG=XED_REG_RDX + +# only used for VIA PADLOCK ISA: +xed_reg_enum_t OrCX():: +EOSZ=1 | OUTREG=XED_REG_CX +EOSZ=2 | OUTREG=XED_REG_ECX +EOSZ=3 | OUTREG=XED_REG_RCX +# only used for VIA PADLOCK ISA: +xed_reg_enum_t OrBX():: +EOSZ=1 | OUTREG=XED_REG_BX +EOSZ=2 | OUTREG=XED_REG_EBX +EOSZ=3 | OUTREG=XED_REG_RBX + +xed_reg_enum_t OrSP():: +EOSZ=1 | OUTREG=XED_REG_SP +EOSZ=2 | OUTREG=XED_REG_ESP +EOSZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t OrBP():: +EOSZ=1 | OUTREG=XED_REG_BP +EOSZ=2 | OUTREG=XED_REG_EBP +EOSZ=3 | OUTREG=XED_REG_RBP + + +##################################################### + +xed_reg_enum_t rFLAGS():: +mode16 | OUTREG=XED_REG_FLAGS +mode32 | OUTREG=XED_REG_EFLAGS +mode64 | OUTREG=XED_REG_RFLAGS + +##################################################### + + +xed_reg_enum_t MMX_R():: +REG=0x0 | OUTREG=XED_REG_MMX0 +REG=0x1 | OUTREG=XED_REG_MMX1 +REG=0x2 | OUTREG=XED_REG_MMX2 +REG=0x3 | OUTREG=XED_REG_MMX3 +REG=0x4 | OUTREG=XED_REG_MMX4 +REG=0x5 | OUTREG=XED_REG_MMX5 +REG=0x6 | OUTREG=XED_REG_MMX6 +REG=0x7 | OUTREG=XED_REG_MMX7 + +xed_reg_enum_t MMX_B():: +RM=0x0 | OUTREG=XED_REG_MMX0 +RM=0x1 | OUTREG=XED_REG_MMX1 +RM=0x2 | OUTREG=XED_REG_MMX2 +RM=0x3 | OUTREG=XED_REG_MMX3 +RM=0x4 | OUTREG=XED_REG_MMX4 +RM=0x5 | OUTREG=XED_REG_MMX5 +RM=0x6 | OUTREG=XED_REG_MMX6 +RM=0x7 | OUTREG=XED_REG_MMX7 + +################################# + +# Things that scale with effective operand size + + + +# When used as the MODRM.REG register +xed_reg_enum_t GPRv_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +xed_reg_enum_t GPRv_SB():: +EOSZ=3 | OUTREG=GPR64_SB() +EOSZ=2 | OUTREG=GPR32_SB() +EOSZ=1 | OUTREG=GPR16_SB() + +xed_reg_enum_t GPRz_R():: +EOSZ=3 | OUTREG=GPR32_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +# When used as the MOD=11/RM register +xed_reg_enum_t GPRv_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRz_B():: +EOSZ=3 | OUTREG=GPR32_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRy_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR32_B() + +xed_reg_enum_t GPRy_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR32_R() + +##################################### + +xed_reg_enum_t GPR64_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_RAX +REXR=0 REG=0x1 | OUTREG=XED_REG_RCX +REXR=0 REG=0x2 | OUTREG=XED_REG_RDX +REXR=0 REG=0x3 | OUTREG=XED_REG_RBX +REXR=0 REG=0x4 | OUTREG=XED_REG_RSP +REXR=0 REG=0x5 | OUTREG=XED_REG_RBP +REXR=0 REG=0x6 | OUTREG=XED_REG_RSI +REXR=0 REG=0x7 | OUTREG=XED_REG_RDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8 +REXR=1 REG=0x1 | OUTREG=XED_REG_R9 +REXR=1 REG=0x2 | OUTREG=XED_REG_R10 +REXR=1 REG=0x3 | OUTREG=XED_REG_R11 +REXR=1 REG=0x4 | OUTREG=XED_REG_R12 +REXR=1 REG=0x5 | OUTREG=XED_REG_R13 +REXR=1 REG=0x6 | OUTREG=XED_REG_R14 +REXR=1 REG=0x7 | OUTREG=XED_REG_R15 + + +xed_reg_enum_t GPR64_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_RAX +REXB=0 RM=0x1 | OUTREG=XED_REG_RCX +REXB=0 RM=0x2 | OUTREG=XED_REG_RDX +REXB=0 RM=0x3 | OUTREG=XED_REG_RBX +REXB=0 RM=0x4 | OUTREG=XED_REG_RSP +REXB=0 RM=0x5 | OUTREG=XED_REG_RBP +REXB=0 RM=0x6 | OUTREG=XED_REG_RSI +REXB=0 RM=0x7 | OUTREG=XED_REG_RDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8 +REXB=1 RM=0x1 | OUTREG=XED_REG_R9 +REXB=1 RM=0x2 | OUTREG=XED_REG_R10 +REXB=1 RM=0x3 | OUTREG=XED_REG_R11 +REXB=1 RM=0x4 | OUTREG=XED_REG_R12 +REXB=1 RM=0x5 | OUTREG=XED_REG_R13 +REXB=1 RM=0x6 | OUTREG=XED_REG_R14 +REXB=1 RM=0x7 | OUTREG=XED_REG_R15 + +xed_reg_enum_t GPR64_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_RAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_RCX +REXB=0 SRM=0x2 | OUTREG=XED_REG_RDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_RBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_RSP +REXB=0 SRM=0x5 | OUTREG=XED_REG_RBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_RSI +REXB=0 SRM=0x7 | OUTREG=XED_REG_RDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8 +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9 +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10 +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11 +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12 +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13 +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14 +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15 + + + +xed_reg_enum_t GPR64_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_RAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_RCX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_RDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_RBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_RBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_RSI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_RDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8 +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9 +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10 +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11 +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12 +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13 +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14 +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15 + + +################################# + + +xed_reg_enum_t GPR32_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_EAX +REXR=0 REG=0x1 | OUTREG=XED_REG_ECX +REXR=0 REG=0x2 | OUTREG=XED_REG_EDX +REXR=0 REG=0x3 | OUTREG=XED_REG_EBX +REXR=0 REG=0x4 | OUTREG=XED_REG_ESP +REXR=0 REG=0x5 | OUTREG=XED_REG_EBP +REXR=0 REG=0x6 | OUTREG=XED_REG_ESI +REXR=0 REG=0x7 | OUTREG=XED_REG_EDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8D +REXR=1 REG=0x1 | OUTREG=XED_REG_R9D +REXR=1 REG=0x2 | OUTREG=XED_REG_R10D +REXR=1 REG=0x3 | OUTREG=XED_REG_R11D +REXR=1 REG=0x4 | OUTREG=XED_REG_R12D +REXR=1 REG=0x5 | OUTREG=XED_REG_R13D +REXR=1 REG=0x6 | OUTREG=XED_REG_R14D +REXR=1 REG=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_EAX +REXB=0 RM=0x1 | OUTREG=XED_REG_ECX +REXB=0 RM=0x2 | OUTREG=XED_REG_EDX +REXB=0 RM=0x3 | OUTREG=XED_REG_EBX +REXB=0 RM=0x4 | OUTREG=XED_REG_ESP +REXB=0 RM=0x5 | OUTREG=XED_REG_EBP +REXB=0 RM=0x6 | OUTREG=XED_REG_ESI +REXB=0 RM=0x7 | OUTREG=XED_REG_EDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8D +REXB=1 RM=0x1 | OUTREG=XED_REG_R9D +REXB=1 RM=0x2 | OUTREG=XED_REG_R10D +REXB=1 RM=0x3 | OUTREG=XED_REG_R11D +REXB=1 RM=0x4 | OUTREG=XED_REG_R12D +REXB=1 RM=0x5 | OUTREG=XED_REG_R13D +REXB=1 RM=0x6 | OUTREG=XED_REG_R14D +REXB=1 RM=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_EAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_ECX +REXB=0 SRM=0x2 | OUTREG=XED_REG_EDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_EBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_ESP +REXB=0 SRM=0x5 | OUTREG=XED_REG_EBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_ESI +REXB=0 SRM=0x7 | OUTREG=XED_REG_EDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8D +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9D +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10D +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11D +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12D +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13D +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14D +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15D + + + + + +xed_reg_enum_t GPR32_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_EAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_ECX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_EDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_EBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_EBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_ESI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_EDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8D +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9D +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10D +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11D +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12D +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13D +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14D +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15D + + +############################# + + +xed_reg_enum_t GPR16_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_AX +REXR=0 REG=0x1 | OUTREG=XED_REG_CX +REXR=0 REG=0x2 | OUTREG=XED_REG_DX +REXR=0 REG=0x3 | OUTREG=XED_REG_BX +REXR=0 REG=0x4 | OUTREG=XED_REG_SP +REXR=0 REG=0x5 | OUTREG=XED_REG_BP +REXR=0 REG=0x6 | OUTREG=XED_REG_SI +REXR=0 REG=0x7 | OUTREG=XED_REG_DI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8W +REXR=1 REG=0x1 | OUTREG=XED_REG_R9W +REXR=1 REG=0x2 | OUTREG=XED_REG_R10W +REXR=1 REG=0x3 | OUTREG=XED_REG_R11W +REXR=1 REG=0x4 | OUTREG=XED_REG_R12W +REXR=1 REG=0x5 | OUTREG=XED_REG_R13W +REXR=1 REG=0x6 | OUTREG=XED_REG_R14W +REXR=1 REG=0x7 | OUTREG=XED_REG_R15W + + + +xed_reg_enum_t GPR16_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_AX +REXB=0 RM=0x1 | OUTREG=XED_REG_CX +REXB=0 RM=0x2 | OUTREG=XED_REG_DX +REXB=0 RM=0x3 | OUTREG=XED_REG_BX +REXB=0 RM=0x4 | OUTREG=XED_REG_SP +REXB=0 RM=0x5 | OUTREG=XED_REG_BP +REXB=0 RM=0x6 | OUTREG=XED_REG_SI +REXB=0 RM=0x7 | OUTREG=XED_REG_DI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8W +REXB=1 RM=0x1 | OUTREG=XED_REG_R9W +REXB=1 RM=0x2 | OUTREG=XED_REG_R10W +REXB=1 RM=0x3 | OUTREG=XED_REG_R11W +REXB=1 RM=0x4 | OUTREG=XED_REG_R12W +REXB=1 RM=0x5 | OUTREG=XED_REG_R13W +REXB=1 RM=0x6 | OUTREG=XED_REG_R14W +REXB=1 RM=0x7 | OUTREG=XED_REG_R15W + +xed_reg_enum_t GPR16_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_AX +REXB=0 SRM=0x1 | OUTREG=XED_REG_CX +REXB=0 SRM=0x2 | OUTREG=XED_REG_DX +REXB=0 SRM=0x3 | OUTREG=XED_REG_BX +REXB=0 SRM=0x4 | OUTREG=XED_REG_SP +REXB=0 SRM=0x5 | OUTREG=XED_REG_BP +REXB=0 SRM=0x6 | OUTREG=XED_REG_SI +REXB=0 SRM=0x7 | OUTREG=XED_REG_DI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8W +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9W +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10W +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11W +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12W +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13W +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14W +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15W + + + +############################# + +# GPR8_R and GPR8_B are handled in separate files -- grep for them. + +###########################a + +xed_reg_enum_t CR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_CR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x2 | OUTREG=XED_REG_CR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_CR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_CR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_CR8 +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +# FIXME: not used +xed_reg_enum_t CR_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_CR0 +REXB=0 RM=0x1 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x2 | OUTREG=XED_REG_CR2 +REXB=0 RM=0x3 | OUTREG=XED_REG_CR3 +REXB=0 RM=0x4 | OUTREG=XED_REG_CR4 +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_CR8 +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR + +######################## + +xed_reg_enum_t DR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_DR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_DR1 +REXR=0 REG=0x2 | OUTREG=XED_REG_DR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_DR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_DR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_DR5 +REXR=0 REG=0x6 | OUTREG=XED_REG_DR6 +REXR=0 REG=0x7 | OUTREG=XED_REG_DR7 +REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR enc +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +####################### + + +xed_reg_enum_t X87():: +RM=0x0 | OUTREG=XED_REG_ST0 +RM=0x1 | OUTREG=XED_REG_ST1 +RM=0x2 | OUTREG=XED_REG_ST2 +RM=0x3 | OUTREG=XED_REG_ST3 +RM=0x4 | OUTREG=XED_REG_ST4 +RM=0x5 | OUTREG=XED_REG_ST5 +RM=0x6 | OUTREG=XED_REG_ST6 +RM=0x7 | OUTREG=XED_REG_ST7 + +################### + +xed_reg_enum_t SEG():: +REG=0x0 | OUTREG=XED_REG_ES +REG=0x1 | OUTREG=XED_REG_CS +REG=0x2 | OUTREG=XED_REG_SS +REG=0x3 | OUTREG=XED_REG_DS +REG=0x4 | OUTREG=XED_REG_FS +REG=0x5 | OUTREG=XED_REG_GS +REG=0x6 | OUTREG=XED_REG_ERROR enc +REG=0x7 | OUTREG=XED_REG_ERROR + +# MOV to SEG cannot load CS +xed_reg_enum_t SEG_MOV():: +REG=0x0 | OUTREG=XED_REG_ES +REG=0x1 | OUTREG=XED_REG_ERROR +REG=0x2 | OUTREG=XED_REG_SS +REG=0x3 | OUTREG=XED_REG_DS +REG=0x4 | OUTREG=XED_REG_FS +REG=0x5 | OUTREG=XED_REG_GS +REG=0x6 | OUTREG=XED_REG_ERROR enc +REG=0x7 | OUTREG=XED_REG_ERROR + + +################################################### + +# We have two versions of FINAL_DSEG called FINAL_DSEG and +# FINAL_DSEG1. This is required because in the nonterminal function, I +# don't know if which memop (MEM0 or MEM1) the segment selector is +# being applied to. I set USING_DEFAULT_SEGMENT0 for MEM0 and +# USING_DEFAULT_SEGMENT1 for MEM1. + + +# These set USING_DEFAULT_SEGMENT0 + +xed_reg_enum_t FINAL_DSEG():: +mode16 | OUTREG=FINAL_DSEG_NOT64() +mode32 | OUTREG=FINAL_DSEG_NOT64() +mode64 | OUTREG=FINAL_DSEG_MODE64() + +xed_reg_enum_t FINAL_DSEG_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 enc # default data seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 # explicit ds seg +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=0 + +xed_reg_enum_t FINAL_DSEG_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + + +# These set USING_DEFAULT_SEGMENT1 + +xed_reg_enum_t FINAL_DSEG1():: +mode16 | OUTREG=FINAL_DSEG1_NOT64() +mode32 | OUTREG=FINAL_DSEG1_NOT64() +mode64 | OUTREG=FINAL_DSEG1_MODE64() + +xed_reg_enum_t FINAL_DSEG1_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 enc # default data seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 # explicit ds seg +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=0 + +xed_reg_enum_t FINAL_DSEG1_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + + + + + +################################################### + +# FINAL_ESEG is only called for STRING OPS and only specifies MEM0's SEG0. + +xed_reg_enum_t FINAL_ESEG():: +mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1 +mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + +xed_reg_enum_t FINAL_ESEG1():: +mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1 +mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + +# For synthesized stack operands (see generator.py) +xed_reg_enum_t FINAL_SSEG1():: +mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1 +mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + +# For stack operands that cannot be overridden +xed_reg_enum_t FINAL_SSEG0():: +mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 +mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + +# This is only called for MODRM BYTEs and they only set MEM0's SEG0. + +xed_reg_enum_t FINAL_SSEG():: +mode16 | OUTREG=FINAL_SSEG_NOT64() +mode32 | OUTREG=FINAL_SSEG_NOT64() +mode64 | OUTREG=FINAL_SSEG_MODE64() + +xed_reg_enum_t FINAL_SSEG_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 enc # default stack seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 # explicit ss seg + +xed_reg_enum_t FINAL_SSEG_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-gpr8-dec-reg-table.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +######################################################################## +## file: xed-reg-tables.txt +######################################################################## + +xed_reg_enum_t GPR8_R():: + +REXR=0 REG=0x0 | OUTREG=XED_REG_AL +REXR=0 REG=0x1 | OUTREG=XED_REG_CL +REXR=0 REG=0x2 | OUTREG=XED_REG_DL +REXR=0 REG=0x3 | OUTREG=XED_REG_BL + +REXR=0 REG=0x4 REX=0 | OUTREG=XED_REG_AH +REXR=0 REG=0x5 REX=0 | OUTREG=XED_REG_CH +REXR=0 REG=0x6 REX=0 | OUTREG=XED_REG_DH +REXR=0 REG=0x7 REX=0 | OUTREG=XED_REG_BH + +REXR=0 REG=0x4 REX=1 | OUTREG=XED_REG_SPL +REXR=0 REG=0x5 REX=1 | OUTREG=XED_REG_BPL +REXR=0 REG=0x6 REX=1 | OUTREG=XED_REG_SIL +REXR=0 REG=0x7 REX=1 | OUTREG=XED_REG_DIL + +REXR=1 REG=0x0 | OUTREG=XED_REG_R8B +REXR=1 REG=0x1 | OUTREG=XED_REG_R9B +REXR=1 REG=0x2 | OUTREG=XED_REG_R10B +REXR=1 REG=0x3 | OUTREG=XED_REG_R11B +REXR=1 REG=0x4 | OUTREG=XED_REG_R12B +REXR=1 REG=0x5 | OUTREG=XED_REG_R13B +REXR=1 REG=0x6 | OUTREG=XED_REG_R14B +REXR=1 REG=0x7 | OUTREG=XED_REG_R15B + +xed_reg_enum_t GPR8_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_AL +REXB=0 RM=0x1 | OUTREG=XED_REG_CL +REXB=0 RM=0x2 | OUTREG=XED_REG_DL +REXB=0 RM=0x3 | OUTREG=XED_REG_BL + +REXB=0 RM=0x4 REX=0 | OUTREG=XED_REG_AH +REXB=0 RM=0x5 REX=0 | OUTREG=XED_REG_CH +REXB=0 RM=0x6 REX=0 | OUTREG=XED_REG_DH +REXB=0 RM=0x7 REX=0 | OUTREG=XED_REG_BH + +REXB=0 RM=0x4 REX=1 | OUTREG=XED_REG_SPL +REXB=0 RM=0x5 REX=1 | OUTREG=XED_REG_BPL +REXB=0 RM=0x6 REX=1 | OUTREG=XED_REG_SIL +REXB=0 RM=0x7 REX=1 | OUTREG=XED_REG_DIL + +REXB=1 RM=0x0 | OUTREG=XED_REG_R8B +REXB=1 RM=0x1 | OUTREG=XED_REG_R9B +REXB=1 RM=0x2 | OUTREG=XED_REG_R10B +REXB=1 RM=0x3 | OUTREG=XED_REG_R11B +REXB=1 RM=0x4 | OUTREG=XED_REG_R12B +REXB=1 RM=0x5 | OUTREG=XED_REG_R13B +REXB=1 RM=0x6 | OUTREG=XED_REG_R14B +REXB=1 RM=0x7 | OUTREG=XED_REG_R15B + + +xed_reg_enum_t GPR8_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_AL +REXB=0 SRM=0x1 | OUTREG=XED_REG_CL +REXB=0 SRM=0x2 | OUTREG=XED_REG_DL +REXB=0 SRM=0x3 | OUTREG=XED_REG_BL + +REXB=0 SRM=0x4 REX=0 | OUTREG=XED_REG_AH +REXB=0 SRM=0x5 REX=0 | OUTREG=XED_REG_CH +REXB=0 SRM=0x6 REX=0 | OUTREG=XED_REG_DH +REXB=0 SRM=0x7 REX=0 | OUTREG=XED_REG_BH + +REXB=0 SRM=0x4 REX=1 | OUTREG=XED_REG_SPL +REXB=0 SRM=0x5 REX=1 | OUTREG=XED_REG_BPL +REXB=0 SRM=0x6 REX=1 | OUTREG=XED_REG_SIL +REXB=0 SRM=0x7 REX=1 | OUTREG=XED_REG_DIL + +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8B +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9B +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10B +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11B +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12B +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13B +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14B +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15B + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-eOSZ.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-eOSZ.txt +########################################################################### + +OSZ_NONTERM():: + +mode16 no66_prefix | EOSZ=1 +mode16 66_prefix | EOSZ=2 + +mode32 66_prefix | EOSZ=1 +mode32 no66_prefix | EOSZ=2 + +# NOTE this can get overridden later if a DF64 NT shows up. +mode64 66_prefix REXW=0 | EOSZ=1 +mode64 no66_prefix REXW=0 | EOSZ=2 +mode64 66_prefix REXW=1 | EOSZ=3 +mode64 no66_prefix REXW=1 | EOSZ=3 + + +# Things that default to 64b mode invoke this nonterminal once they +# are identified to denote that fact. Placement of this nonterminal is +# critical for those operations and the ones the might collide with +# during decoding. See PUSHF/PUSHFD/PUSHFQ. +# +# Denote the DF64=1 (df64). +DF64():: +mode16 | +mode32 | +mode64 66_prefix REXW=0 | EOSZ=1 df64 +mode64 no66_prefix REXW=0 | EOSZ=3 df64 +mode64 66_prefix REXW=1 | EOSZ=3 df64 +mode64 no66_prefix REXW=1 | EOSZ=3 df64 + +# if we have a refining OSZ 0x66 prefix, then we must undo the effects +# of the OSZ_NONTERM(). DF64 is not used with anything that has refining 66 prefixes. +# We turn off the osze prefix because it is really behaving like a refining prefix for these instructions. +REFINING66():: +mode16 | EOSZ=1 no66_prefix +mode32 | EOSZ=2 no66_prefix +mode64 REXW=0 | EOSZ=2 no66_prefix +mode64 REXW=1 | EOSZ=3 no66_prefix + +IGNORE66():: +mode16 | EOSZ=1 no66_prefix +mode32 | EOSZ=2 no66_prefix +mode64 REXW=0 | EOSZ=2 no66_prefix +mode64 REXW=1 | EOSZ=3 no66_prefix + + +# IMMUNE66() is used to make 16b mode behave like 32b mode. +# Used for: +# cmpxchg8b / cmpxchg16b, +# NHM sttni instr: pcmpestri, pcmpistrm, pcmpestrm, pcmpistri, +# BDW adox, adcx. +# +IMMUNE66():: +mode16 | EOSZ=2 no66_prefix +mode32 | EOSZ=2 no66_prefix +mode64 REXW=0 | EOSZ=2 no66_prefix +mode64 REXW=1 | EOSZ=3 no66_prefix + +# Used for for CRs and DRs. +CR_WIDTH():: +mode16 | EOSZ=2 DF32=1 no66_prefix +mode32 | EOSZ=2 DF32=1 no66_prefix +mode64 | EOSZ=3 DF64=1 no66_prefix + + +IMMUNE66_LOOP64():: +mode16 | +mode32 | +mode64 | EOSZ=3 no66_prefix + +IMMUNE_REXW():: +mode16 | +mode32 | +mode64 no66_prefix | EOSZ=2 +mode64 66_prefix REXW=1 | EOSZ=2 +mode64 66_prefix REXW=0 | EOSZ=1 + +# FORCE64() can only be used with mode64 stuff (else encode does not +# work). see IMMUNE66_LOOP64() for something that works in all modes. +FORCE64():: +mode64 | EOSZ=3 no66_prefix +otherwise | + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-eASZ.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-eASZ.txt +########################################################################### +# Call this after all legacy prefixes and before every instruction! + + +ASZ_NONTERM():: + +mode16 no67_prefix | eamode16 +mode16 67_prefix | eamode32 + +mode32 no67_prefix | eamode32 +mode32 67_prefix | eamode16 + +mode64 no67_prefix | eamode64 +mode64 67_prefix | eamode32 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-immediates.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-immediates.txt +########################################################################### +# Immediates and displacements +# FIXME: when there are multiple immediates, need separate storage +# FIXME: record the width of the immediate + +# FIXME: for encode we'll sometimes have to choose between SIMMv and +# SIMMz to pick a MOV, for 16 and 32b widths. +########################################################################################## +## 2-BYTE STORAGE UNITS +########################################################################################## + +ONE():: +mode16 | IMM_WIDTH=8 UIMM0=1 +mode32 | IMM_WIDTH=8 UIMM0=1 +mode64 | IMM_WIDTH=8 UIMM0=1 + + +UIMMv():: +EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 +EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 +EOSZ=3 UIMM0[i/64] | IMM_WIDTH=64 + +SIMMz():: +EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 IMM0SIGNED=1 +EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1 +EOSZ=3 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1 + +SIMM8():: + UIMM0[i/8] | IMM_WIDTH=8 IMM0SIGNED=1 + +UIMM8():: + UIMM0[i/8] | IMM_WIDTH=8 + +# For ENTER. separate storage. +UIMM8_1():: + UIMM1[i/8] | true + +UIMM16():: + UIMM0[i/16] | IMM_WIDTH=16 + +UIMM32():: + UIMM0[i/32] | IMM_WIDTH=32 + +BRDISP8():: + DISP[d/8] |BRDISP_WIDTH=8 + +BRDISP32():: + DISP[d/32] | BRDISP_WIDTH=32 + +BRDISPz():: +EOSZ=1 DISP[d/16] | BRDISP_WIDTH=16 +EOSZ=2 DISP[d/32] | BRDISP_WIDTH=32 +EOSZ=3 DISP[d/32] | BRDISP_WIDTH=32 + + +MEMDISPv():: +EASZ=1 DISP[a/16] | DISP_WIDTH=16 +EASZ=2 DISP[a/32] | DISP_WIDTH=32 +EASZ=3 DISP[a/64] | DISP_WIDTH=64 + + +MEMDISP32():: +DISP[a/32] | DISP_WIDTH=32 + +MEMDISP16():: +DISP[a/16] | DISP_WIDTH=16 + +MEMDISP8():: +DISP[a/8] | DISP_WIDTH=8 + + +MEMDISP():: +NEED_MEMDISP=0 | DISP_WIDTH=0 +NEED_MEMDISP=8 DISP[a/8] | DISP_WIDTH=8 +NEED_MEMDISP=16 DISP[a/16] | DISP_WIDTH=16 +NEED_MEMDISP=32 DISP[a/32] | DISP_WIDTH=32 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-addressing-modes-new.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-addressing-modes-new.txt +########################################################################### + +# inputs: +# REX = REX or NOREX +# REXB = REXB0 or REXB1 +# REXX = REXX0 or REXX1 +# MODE = MODE32 or MODE64 + +# outputs: +# SEG0, BASE0, INDEX, SCALE, DISP and +# a register id to be evaluated at a higher level + +# The 32b and 64b share SIB/SIB_BASE0 productions. The registers there +# have to be converted to the right width. Similarly, the rAX'es etc +# in the MODRM64alt32 need to be scaled by ASZ. So rAX is either RAX +# or EAX and r15 is either R15 or R15D depending on ASZ. + +# Sooo. for the BASE0/SIB_BASE0,INDEX, we need a lookup like: +# base_or_index_reg_lookup(rex,rexb/x,RM,mode,asz) +# The ASZ operand will do different things. In 32b mode it is not used +# because the ASZ would take use to 16 mode addressing. In 64b mode, +# it tells use to use 64 or 32b registers. + + + + +############################################################################ +MODRM():: +# +# NOTE: the RIP handling in 64b mode with effective addressing of 32b +# is different than the 32b addressing in 32b mode when MODRM.MOD=00_ +# and MODRM.RM=101, where it is just #a base, not RIP relative. +# +mode64 eamode64 MODRM64alt32() MEMDISP() | +mode64 eamode32 MODRM64alt32() MEMDISP() | +mode32 eamode32 MODRM32() MEMDISP() | +mode32 eamode16 MODRM16() MEMDISP() | +mode16 eamode32 MODRM32() MEMDISP() | +mode16 eamode16 MODRM16() MEMDISP() | + + +############################################################################ + +MODRM64alt32():: + REXB=0 MOD=0b00 RM=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b100 SIB() | + REXB=1 MOD=0b00 RM=0b100 SIB() | + +# Ignores rexb -- must duplicate to avoid don't-care problems + REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() enc + REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b00 RM=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b00 RM=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG() + +############################################ + + REXB=0 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=Ar8() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 + REXB=1 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 + + REXB=0 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=ArBP() SEG0=FINAL_SSEG() + REXB=1 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=Ar13() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=Ar15() SEG0=FINAL_DSEG() + + +############################################ + + REXB=0 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=Ar8() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 + REXB=1 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 + + REXB=0 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=ArBP() SEG0=FINAL_SSEG() + REXB=1 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=Ar13() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=Ar15() SEG0=FINAL_DSEG() + +############################################ + + +MODRM32():: + MOD=0b00 RM=0b000 | BASE0=XED_REG_EAX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b001 | BASE0=XED_REG_ECX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b010 | BASE0=XED_REG_EDX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b011 | BASE0=XED_REG_EBX SEG0=FINAL_DSEG() + MOD=0b00 RM=0b100 SIB() | + MOD=0b00 RM=0b101 | NEED_MEMDISP=32 SEG0=FINAL_DSEG() + MOD=0b00 RM=0b110 | BASE0=XED_REG_ESI SEG0=FINAL_DSEG() + MOD=0b00 RM=0b111 | BASE0=XED_REG_EDI SEG0=FINAL_DSEG() +#################################### + MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_EAX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_ECX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_EDX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_EBX SEG0=FINAL_DSEG() + MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8 + MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_EBP SEG0=FINAL_SSEG() + MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_ESI SEG0=FINAL_DSEG() + MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_EDI SEG0=FINAL_DSEG() +#################################### + MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=XED_REG_EAX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=XED_REG_ECX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=XED_REG_EDX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=XED_REG_EBX SEG0=FINAL_DSEG() + MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32 + MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_EBP SEG0=FINAL_SSEG() + MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=XED_REG_ESI SEG0=FINAL_DSEG() + MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=XED_REG_EDI SEG0=FINAL_DSEG() +############################################ + + + +################################################### +# 16 bit addressing MODRM bytes +MODRM16():: + MOD=0b00 RM=0b000 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b00 RM=0b001 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b00 RM=0b010 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b00 RM=0b011 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b00 RM=0b100 | BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b00 RM=0b101 | BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + MOD=0b00 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b00 RM=0b111 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + +############################################# + + MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b01 RM=0b100 | NEED_MEMDISP=8 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID + MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + +############################################# + MOD=0b10 RM=0b000 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b10 RM=0b001 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b10 RM=0b010 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1 + MOD=0b10 RM=0b011 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1 + + MOD=0b10 RM=0b100 | NEED_MEMDISP=16 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + MOD=0b10 RM=0b101 | NEED_MEMDISP=16 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID + + MOD=0b10 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID + MOD=0b10 RM=0b111 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID +############################################ + +SIB():: + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 enc + REXX=1 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=1 + + REXX=0 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=1 + REXX=1 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=1 + + + + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=2 + + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=2 + + REXX=0 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=2 + REXX=1 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=2 + + + + + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=4 + + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=4 + + REXX=0 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=4 + REXX=1 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=4 + + + + + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=8 + + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=8 + + REXX=0 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=8 + REXX=1 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=8 + + +################################################### + +SIB_BASE0():: + + REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG() + REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG() + REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG() + +# FIXME the d/8 for MOD=01_ and d/32 for MOD=10_ case are redundantly +# specified in the manuals. I removed them from here, but the d/32 for +# MOD=00_ is required as it is unique. + +# I redunantly specify DISP_WIDTH=8 or DISPWITH=32 for the MOD=01_ and +# MOD=10_ cases so that the encoder will pick the right one even though we +# accept the displacment at a higher level. + + REXB=0 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() enc + REXB=0 SIBBASE=0b101 MOD=0b01 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=8 + REXB=0 SIBBASE=0b101 MOD=0b10 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=32 + + REXB=1 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b101 MOD=0b01 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=8 + REXB=1 SIBBASE=0b101 MOD=0b10 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=32 + + REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG() + + REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG() + REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG() + +#FIXME: 2008-10-01 make these in to nops! +OVERRIDE_SEG0():: +mode16 | +mode32 | +mode64 | + +OVERRIDE_SEG1():: +mode16 | +mode32 | +mode64 | + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-reg-tables-xmm.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_R():: +mode16 | OUTREG=XMM_R_32() +mode32 | OUTREG=XMM_R_32() +mode64 | OUTREG=XMM_R_64() + +xed_reg_enum_t XMM_R_32():: +REG=0x0 | OUTREG=XED_REG_XMM0 +REG=0x1 | OUTREG=XED_REG_XMM1 +REG=0x2 | OUTREG=XED_REG_XMM2 +REG=0x3 | OUTREG=XED_REG_XMM3 +REG=0x4 | OUTREG=XED_REG_XMM4 +REG=0x5 | OUTREG=XED_REG_XMM5 +REG=0x6 | OUTREG=XED_REG_XMM6 +REG=0x7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_R_64():: +REXR=0 REG=0x0 | OUTREG=XED_REG_XMM0 +REXR=0 REG=0x1 | OUTREG=XED_REG_XMM1 +REXR=0 REG=0x2 | OUTREG=XED_REG_XMM2 +REXR=0 REG=0x3 | OUTREG=XED_REG_XMM3 +REXR=0 REG=0x4 | OUTREG=XED_REG_XMM4 +REXR=0 REG=0x5 | OUTREG=XED_REG_XMM5 +REXR=0 REG=0x6 | OUTREG=XED_REG_XMM6 +REXR=0 REG=0x7 | OUTREG=XED_REG_XMM7 +REXR=1 REG=0x0 | OUTREG=XED_REG_XMM8 +REXR=1 REG=0x1 | OUTREG=XED_REG_XMM9 +REXR=1 REG=0x2 | OUTREG=XED_REG_XMM10 +REXR=1 REG=0x3 | OUTREG=XED_REG_XMM11 +REXR=1 REG=0x4 | OUTREG=XED_REG_XMM12 +REXR=1 REG=0x5 | OUTREG=XED_REG_XMM13 +REXR=1 REG=0x6 | OUTREG=XED_REG_XMM14 +REXR=1 REG=0x7 | OUTREG=XED_REG_XMM15 + + +xed_reg_enum_t XMM_B():: +mode16 | OUTREG=XMM_B_32() +mode32 | OUTREG=XMM_B_32() +mode64 | OUTREG=XMM_B_64() + +xed_reg_enum_t XMM_B_32():: +RM=0x0 | OUTREG=XED_REG_XMM0 +RM=0x1 | OUTREG=XED_REG_XMM1 +RM=0x2 | OUTREG=XED_REG_XMM2 +RM=0x3 | OUTREG=XED_REG_XMM3 +RM=0x4 | OUTREG=XED_REG_XMM4 +RM=0x5 | OUTREG=XED_REG_XMM5 +RM=0x6 | OUTREG=XED_REG_XMM6 +RM=0x7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_B_64():: +REXB=0 RM=0x0 | OUTREG=XED_REG_XMM0 +REXB=0 RM=0x1 | OUTREG=XED_REG_XMM1 +REXB=0 RM=0x2 | OUTREG=XED_REG_XMM2 +REXB=0 RM=0x3 | OUTREG=XED_REG_XMM3 +REXB=0 RM=0x4 | OUTREG=XED_REG_XMM4 +REXB=0 RM=0x5 | OUTREG=XED_REG_XMM5 +REXB=0 RM=0x6 | OUTREG=XED_REG_XMM6 +REXB=0 RM=0x7 | OUTREG=XED_REG_XMM7 +REXB=1 RM=0x0 | OUTREG=XED_REG_XMM8 +REXB=1 RM=0x1 | OUTREG=XED_REG_XMM9 +REXB=1 RM=0x2 | OUTREG=XED_REG_XMM10 +REXB=1 RM=0x3 | OUTREG=XED_REG_XMM11 +REXB=1 RM=0x4 | OUTREG=XED_REG_XMM12 +REXB=1 RM=0x5 | OUTREG=XED_REG_XMM13 +REXB=1 RM=0x6 | OUTREG=XED_REG_XMM14 +REXB=1 RM=0x7 | OUTREG=XED_REG_XMM15 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-dec.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_SPLITTER():: +VEXVALID=3 XOP_INSTRUCTIONS() | + +EVEX_SPLITTER():: +VEXVALID=3 XOP_INSTRUCTIONS() | + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-reg-check.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BND_R_CHECK():: +REXR=0 REG=0x0 | +REXR=0 REG=0x1 | +REXR=0 REG=0x2 | +REXR=0 REG=0x3 | +REXR=0 REG=0x4 | error +REXR=0 REG=0x5 | error +REXR=0 REG=0x6 | error +REXR=0 REG=0x7 | error +REXR=1 REG=0x0 | error +REXR=1 REG=0x1 | error +REXR=1 REG=0x2 | error +REXR=1 REG=0x3 | error +REXR=1 REG=0x4 | error +REXR=1 REG=0x5 | error +REXR=1 REG=0x6 | error +REXR=1 REG=0x7 | error + +BND_B_CHECK():: +REXB=0 RM=0x0 | +REXB=0 RM=0x1 | +REXB=0 RM=0x2 | +REXB=0 RM=0x3 | +REXB=0 RM=0x4 | error +REXB=0 RM=0x5 | error +REXB=0 RM=0x6 | error +REXB=0 RM=0x7 | error +REXB=1 RM=0x0 | error +REXB=1 RM=0x1 | error +REXB=1 RM=0x2 | error +REXB=1 RM=0x3 | error +REXB=1 RM=0x4 | error +REXB=1 RM=0x5 | error +REXB=1 RM=0x6 | error +REXB=1 RM=0x7 | error + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-reg-tables.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t BND_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_BND0 +REXR=0 REG=0x1 | OUTREG=XED_REG_BND1 +REXR=0 REG=0x2 | OUTREG=XED_REG_BND2 +REXR=0 REG=0x3 | OUTREG=XED_REG_BND3 +REXR=0 REG=0x4 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +xed_reg_enum_t BND_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_BND0 +REXB=0 RM=0x1 | OUTREG=XED_REG_BND1 +REXB=0 RM=0x2 | OUTREG=XED_REG_BND2 +REXB=0 RM=0x3 | OUTREG=XED_REG_BND3 +REXB=0 RM=0x4 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/asize-reg-table.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t A_GPR_R():: +REXR=0 REG=0x0 | OUTREG=ArAX() +REXR=0 REG=0x1 | OUTREG=ArCX() +REXR=0 REG=0x2 | OUTREG=ArDX() +REXR=0 REG=0x3 | OUTREG=ArBX() +REXR=0 REG=0x4 | OUTREG=ArSP() +REXR=0 REG=0x5 | OUTREG=ArBP() +REXR=0 REG=0x6 | OUTREG=ArSI() +REXR=0 REG=0x7 | OUTREG=ArDI() +REXR=1 REG=0x0 | OUTREG=Ar8() +REXR=1 REG=0x1 | OUTREG=Ar9() +REXR=1 REG=0x2 | OUTREG=Ar10() +REXR=1 REG=0x3 | OUTREG=Ar11() +REXR=1 REG=0x4 | OUTREG=Ar12() +REXR=1 REG=0x5 | OUTREG=Ar13() +REXR=1 REG=0x6 | OUTREG=Ar14() +REXR=1 REG=0x7 | OUTREG=Ar15() + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/asize-rm-table.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t A_GPR_B():: +REXB=0 RM=0x0 | OUTREG=ArAX() +REXB=0 RM=0x1 | OUTREG=ArCX() +REXB=0 RM=0x2 | OUTREG=ArDX() +REXB=0 RM=0x3 | OUTREG=ArBX() +REXB=0 RM=0x4 | OUTREG=ArSP() +REXB=0 RM=0x5 | OUTREG=ArBP() +REXB=0 RM=0x6 | OUTREG=ArSI() +REXB=0 RM=0x7 | OUTREG=ArDI() +REXB=1 RM=0x0 | OUTREG=Ar8() +REXB=1 RM=0x1 | OUTREG=Ar9() +REXB=1 RM=0x2 | OUTREG=Ar10() +REXB=1 RM=0x3 | OUTREG=Ar11() +REXB=1 RM=0x4 | OUTREG=Ar12() +REXB=1 RM=0x5 | OUTREG=Ar13() +REXB=1 RM=0x6 | OUTREG=Ar14() +REXB=1 RM=0x7 | OUTREG=Ar15() + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-reg-table.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t XMM_SE():: +mode16 | OUTREG=XMM_SE32() +mode32 | OUTREG=XMM_SE32() +mode64 | OUTREG=XMM_SE64() + +xed_reg_enum_t XMM_SE64():: +ESRC=0x0 | OUTREG=XED_REG_XMM0 +ESRC=0x1 | OUTREG=XED_REG_XMM1 +ESRC=0x2 | OUTREG=XED_REG_XMM2 +ESRC=0x3 | OUTREG=XED_REG_XMM3 +ESRC=0x4 | OUTREG=XED_REG_XMM4 +ESRC=0x5 | OUTREG=XED_REG_XMM5 +ESRC=0x6 | OUTREG=XED_REG_XMM6 +ESRC=0x7 | OUTREG=XED_REG_XMM7 +ESRC=0x8 | OUTREG=XED_REG_XMM8 +ESRC=0x9 | OUTREG=XED_REG_XMM9 +ESRC=0xA | OUTREG=XED_REG_XMM10 +ESRC=0xB | OUTREG=XED_REG_XMM11 +ESRC=0xC | OUTREG=XED_REG_XMM12 +ESRC=0xD | OUTREG=XED_REG_XMM13 +ESRC=0xE | OUTREG=XED_REG_XMM14 +ESRC=0xF | OUTREG=XED_REG_XMM15 + +xed_reg_enum_t XMM_SE32():: +ESRC=0 | OUTREG=XED_REG_XMM0 enc +ESRC=1 | OUTREG=XED_REG_XMM1 enc +ESRC=2 | OUTREG=XED_REG_XMM2 enc +ESRC=3 | OUTREG=XED_REG_XMM3 enc +ESRC=4 | OUTREG=XED_REG_XMM4 enc +ESRC=5 | OUTREG=XED_REG_XMM5 enc +ESRC=6 | OUTREG=XED_REG_XMM6 enc +ESRC=7 | OUTREG=XED_REG_XMM7 enc +# ignoring the high bit in non64b modes. Really just 0...7 +ESRC=0x8 | OUTREG=XED_REG_XMM0 +ESRC=0x9 | OUTREG=XED_REG_XMM1 +ESRC=0xA | OUTREG=XED_REG_XMM2 +ESRC=0xB | OUTREG=XED_REG_XMM3 +ESRC=0xC | OUTREG=XED_REG_XMM4 +ESRC=0xD | OUTREG=XED_REG_XMM5 +ESRC=0xE | OUTREG=XED_REG_XMM6 +ESRC=0xF | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t YMM_SE():: +mode16 | OUTREG=YMM_SE32() +mode32 | OUTREG=YMM_SE32() +mode64 | OUTREG=YMM_SE64() + +xed_reg_enum_t YMM_SE64():: +ESRC=0x0 | OUTREG=XED_REG_YMM0 +ESRC=0x1 | OUTREG=XED_REG_YMM1 +ESRC=0x2 | OUTREG=XED_REG_YMM2 +ESRC=0x3 | OUTREG=XED_REG_YMM3 +ESRC=0x4 | OUTREG=XED_REG_YMM4 +ESRC=0x5 | OUTREG=XED_REG_YMM5 +ESRC=0x6 | OUTREG=XED_REG_YMM6 +ESRC=0x7 | OUTREG=XED_REG_YMM7 +ESRC=0x8 | OUTREG=XED_REG_YMM8 +ESRC=0x9 | OUTREG=XED_REG_YMM9 +ESRC=0xA | OUTREG=XED_REG_YMM10 +ESRC=0xB | OUTREG=XED_REG_YMM11 +ESRC=0xC | OUTREG=XED_REG_YMM12 +ESRC=0xD | OUTREG=XED_REG_YMM13 +ESRC=0xE | OUTREG=XED_REG_YMM14 +ESRC=0xF | OUTREG=XED_REG_YMM15 + +xed_reg_enum_t YMM_SE32():: +ESRC=0 | OUTREG=XED_REG_YMM0 enc +ESRC=1 | OUTREG=XED_REG_YMM1 enc +ESRC=2 | OUTREG=XED_REG_YMM2 enc +ESRC=3 | OUTREG=XED_REG_YMM3 enc +ESRC=4 | OUTREG=XED_REG_YMM4 enc +ESRC=5 | OUTREG=XED_REG_YMM5 enc +ESRC=6 | OUTREG=XED_REG_YMM6 enc +ESRC=7 | OUTREG=XED_REG_YMM7 enc +# ignoring the high bit in non64b modes. Really just 0...7 +ESRC=0x8 | OUTREG=XED_REG_YMM0 +ESRC=0x9 | OUTREG=XED_REG_YMM1 +ESRC=0xA | OUTREG=XED_REG_YMM2 +ESRC=0xB | OUTREG=XED_REG_YMM3 +ESRC=0xC | OUTREG=XED_REG_YMM4 +ESRC=0xD | OUTREG=XED_REG_YMM5 +ESRC=0xE | OUTREG=XED_REG_YMM6 +ESRC=0xF | OUTREG=XED_REG_YMM7 + + +xed_reg_enum_t XMM_N():: +mode16 | OUTREG=XMM_N_32(): +mode32 | OUTREG=XMM_N_32(): +mode64 | OUTREG=XMM_N_64(): + +xed_reg_enum_t XMM_N_32():: +VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_N_64():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7 +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15 + +xed_reg_enum_t YMM_N():: +mode16 | OUTREG=YMM_N_32(): +mode32 | OUTREG=YMM_N_32(): +mode64 | OUTREG=YMM_N_64(): + +xed_reg_enum_t YMM_N_32():: +VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST210=0 | OUTREG=XED_REG_YMM7 +xed_reg_enum_t YMM_N_64():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7 +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15 + +xed_reg_enum_t YMM_R():: +mode16 | OUTREG=YMM_R_32(): +mode32 | OUTREG=YMM_R_32(): +mode64 | OUTREG=YMM_R_64(): + + +xed_reg_enum_t YMM_R_32():: +REG=0 | OUTREG=XED_REG_YMM0 +REG=1 | OUTREG=XED_REG_YMM1 +REG=2 | OUTREG=XED_REG_YMM2 +REG=3 | OUTREG=XED_REG_YMM3 +REG=4 | OUTREG=XED_REG_YMM4 +REG=5 | OUTREG=XED_REG_YMM5 +REG=6 | OUTREG=XED_REG_YMM6 +REG=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_R_64():: +REXR=0 REG=0 | OUTREG=XED_REG_YMM0 +REXR=0 REG=1 | OUTREG=XED_REG_YMM1 +REXR=0 REG=2 | OUTREG=XED_REG_YMM2 +REXR=0 REG=3 | OUTREG=XED_REG_YMM3 +REXR=0 REG=4 | OUTREG=XED_REG_YMM4 +REXR=0 REG=5 | OUTREG=XED_REG_YMM5 +REXR=0 REG=6 | OUTREG=XED_REG_YMM6 +REXR=0 REG=7 | OUTREG=XED_REG_YMM7 +REXR=1 REG=0 | OUTREG=XED_REG_YMM8 +REXR=1 REG=1 | OUTREG=XED_REG_YMM9 +REXR=1 REG=2 | OUTREG=XED_REG_YMM10 +REXR=1 REG=3 | OUTREG=XED_REG_YMM11 +REXR=1 REG=4 | OUTREG=XED_REG_YMM12 +REXR=1 REG=5 | OUTREG=XED_REG_YMM13 +REXR=1 REG=6 | OUTREG=XED_REG_YMM14 +REXR=1 REG=7 | OUTREG=XED_REG_YMM15 + + +xed_reg_enum_t YMM_B():: +mode16 | OUTREG=YMM_B_32(): +mode32 | OUTREG=YMM_B_32(): +mode64 | OUTREG=YMM_B_64(): + + +xed_reg_enum_t YMM_B_32():: +RM=0 | OUTREG=XED_REG_YMM0 +RM=1 | OUTREG=XED_REG_YMM1 +RM=2 | OUTREG=XED_REG_YMM2 +RM=3 | OUTREG=XED_REG_YMM3 +RM=4 | OUTREG=XED_REG_YMM4 +RM=5 | OUTREG=XED_REG_YMM5 +RM=6 | OUTREG=XED_REG_YMM6 +RM=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_B_64():: +REXB=0 RM=0 | OUTREG=XED_REG_YMM0 +REXB=0 RM=1 | OUTREG=XED_REG_YMM1 +REXB=0 RM=2 | OUTREG=XED_REG_YMM2 +REXB=0 RM=3 | OUTREG=XED_REG_YMM3 +REXB=0 RM=4 | OUTREG=XED_REG_YMM4 +REXB=0 RM=5 | OUTREG=XED_REG_YMM5 +REXB=0 RM=6 | OUTREG=XED_REG_YMM6 +REXB=0 RM=7 | OUTREG=XED_REG_YMM7 +REXB=1 RM=0 | OUTREG=XED_REG_YMM8 +REXB=1 RM=1 | OUTREG=XED_REG_YMM9 +REXB=1 RM=2 | OUTREG=XED_REG_YMM10 +REXB=1 RM=3 | OUTREG=XED_REG_YMM11 +REXB=1 RM=4 | OUTREG=XED_REG_YMM12 +REXB=1 RM=5 | OUTREG=XED_REG_YMM13 +REXB=1 RM=6 | OUTREG=XED_REG_YMM14 +REXB=1 RM=7 | OUTREG=XED_REG_YMM15 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa-supp.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_SPLITTER():: +VEXVALID=0 INSTRUCTIONS() | +VEXVALID=1 AVX_INSTRUCTIONS() | + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-vex.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# FOR VEX'ed instructions, I need to turn off the normal REX prefix +# encoder. Ideally, I could use fields names other than REX{WRXB}, +# but the register lookup functions need those names. I can get away +# with using different names for the f2/f3/66 refining legacy prefixes +# since they are only referenced by the AVX instructions. + + + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-imm.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SE_IMM8():: +UIMM0[ssss_uuuu] | IMM_WIDTH=8 ESRC=ssss + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/vsib-addressing-dec.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# SPARSE OPERATIONS REQUIRE A SPECIAL MODRM BYTE and a mandatory VSIB BYTE + +VMODRM_YMM():: + MOD=0b00 VSIB_YMM() | + MOD=0b01 VSIB_YMM() MEMDISP8() | + MOD=0b10 VSIB_YMM() MEMDISP32() | + + +VMODRM_XMM():: + MOD=0b00 VSIB_XMM() | + MOD=0b01 VSIB_XMM() MEMDISP8() | + MOD=0b10 VSIB_XMM() MEMDISP32() | + +VSIB_YMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=8 + +VSIB_XMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=8 + +xed_reg_enum_t VSIB_INDEX_YMM():: +REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM0 +REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM1 +REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM2 +REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM3 +REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM4 +REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM5 +REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM6 +REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM7 +REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM8 +REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM9 +REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM10 +REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM11 +REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM12 +REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM13 +REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM14 +REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM15 + + +xed_reg_enum_t VSIB_INDEX_XMM():: +REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM0 +REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM1 +REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM2 +REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM3 +REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM4 +REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM5 +REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM6 +REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM7 +REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM8 +REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM9 +REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM10 +REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM11 +REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM12 +REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM13 +REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM14 +REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM15 + + +VSIB_BASE():: +REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG() + + + + + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/hsw-reg-table.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# VGPRy_N, VGPRy_B, and VGPRy_R are used by AMD XOP. +# Only but the lower level stuff is used by HSW NI. + +xed_reg_enum_t VGPRy_R():: +EOSZ=1 | OUTREG=VGPR32_R() +EOSZ=2 | OUTREG=VGPR32_R() +EOSZ=3 | OUTREG=VGPR64_R() + +xed_reg_enum_t VGPRy_B():: +EOSZ=1 | OUTREG=VGPR32_B() +EOSZ=2 | OUTREG=VGPR32_B() +EOSZ=3 | OUTREG=VGPR64_B() + +xed_reg_enum_t VGPRy_N():: +EOSZ=1 | OUTREG=VGPR32_N() +EOSZ=2 | OUTREG=VGPR32_N() +EOSZ=3 | OUTREG=VGPR64_N() + +xed_reg_enum_t VGPR32_N():: +mode16 | OUTREG=VGPR32_N_32() +mode32 | OUTREG=VGPR32_N_32() +mode64 | OUTREG=VGPR32_N_64() + +xed_reg_enum_t VGPR32_B():: +mode16 | OUTREG=VGPR32_B_32() +mode32 | OUTREG=VGPR32_B_32() +mode64 | OUTREG=VGPR32_B_64() + +xed_reg_enum_t VGPR32_R():: +mode16 | OUTREG=VGPR32_R_32() +mode32 | OUTREG=VGPR32_R_32() +mode64 | OUTREG=VGPR32_R_64() + + + + + + +xed_reg_enum_t VGPR32_N_32():: # IGNORES UPPER BIT (VEXDEST3) IN 32b mode +VEXDEST210=7 | OUTREG=XED_REG_EAX +VEXDEST210=6 | OUTREG=XED_REG_ECX +VEXDEST210=5 | OUTREG=XED_REG_EDX +VEXDEST210=4 | OUTREG=XED_REG_EBX +VEXDEST210=3 | OUTREG=XED_REG_ESP +VEXDEST210=2 | OUTREG=XED_REG_EBP +VEXDEST210=1 | OUTREG=XED_REG_ESI +VEXDEST210=0 | OUTREG=XED_REG_EDI + +xed_reg_enum_t VGPR32_N_64():: # IGNORES UPPER BIT (VEXDEST3) IN 32b mode +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_EAX +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ECX +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_EDX +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_EBX +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ESP +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_EBP +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ESI +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_EDI +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8D +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9D +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10D +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11D +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12D +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13D +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14D +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15D + + +xed_reg_enum_t VGPR64_N():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_RAX +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_RCX +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_RDX +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_RBX +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_RSP +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_RBP +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_RSI +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_RDI +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15 + + +########### + +xed_reg_enum_t VGPR32_R_32():: # IGNORES (REXR) IN 32b mode +REG=0 | OUTREG=XED_REG_EAX +REG=1 | OUTREG=XED_REG_ECX +REG=2 | OUTREG=XED_REG_EDX +REG=3 | OUTREG=XED_REG_EBX +REG=4 | OUTREG=XED_REG_ESP +REG=5 | OUTREG=XED_REG_EBP +REG=6 | OUTREG=XED_REG_ESI +REG=7 | OUTREG=XED_REG_EDI + + +xed_reg_enum_t VGPR32_R_64():: +REXR=0 REG=0 | OUTREG=XED_REG_EAX +REXR=0 REG=1 | OUTREG=XED_REG_ECX +REXR=0 REG=2 | OUTREG=XED_REG_EDX +REXR=0 REG=3 | OUTREG=XED_REG_EBX +REXR=0 REG=4 | OUTREG=XED_REG_ESP +REXR=0 REG=5 | OUTREG=XED_REG_EBP +REXR=0 REG=6 | OUTREG=XED_REG_ESI +REXR=0 REG=7 | OUTREG=XED_REG_EDI +REXR=1 REG=0 | OUTREG=XED_REG_R8D +REXR=1 REG=1 | OUTREG=XED_REG_R9D +REXR=1 REG=2 | OUTREG=XED_REG_R10D +REXR=1 REG=3 | OUTREG=XED_REG_R11D +REXR=1 REG=4 | OUTREG=XED_REG_R12D +REXR=1 REG=5 | OUTREG=XED_REG_R13D +REXR=1 REG=6 | OUTREG=XED_REG_R14D +REXR=1 REG=7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t VGPR64_R():: +REXR=0 REG=0 | OUTREG=XED_REG_RAX +REXR=0 REG=1 | OUTREG=XED_REG_RCX +REXR=0 REG=2 | OUTREG=XED_REG_RDX +REXR=0 REG=3 | OUTREG=XED_REG_RBX +REXR=0 REG=4 | OUTREG=XED_REG_RSP +REXR=0 REG=5 | OUTREG=XED_REG_RBP +REXR=0 REG=6 | OUTREG=XED_REG_RSI +REXR=0 REG=7 | OUTREG=XED_REG_RDI +REXR=1 REG=0 | OUTREG=XED_REG_R8 +REXR=1 REG=1 | OUTREG=XED_REG_R9 +REXR=1 REG=2 | OUTREG=XED_REG_R10 +REXR=1 REG=3 | OUTREG=XED_REG_R11 +REXR=1 REG=4 | OUTREG=XED_REG_R12 +REXR=1 REG=5 | OUTREG=XED_REG_R13 +REXR=1 REG=6 | OUTREG=XED_REG_R14 +REXR=1 REG=7 | OUTREG=XED_REG_R15 + + +################### + +xed_reg_enum_t VGPR32_B_32():: # IGNORES (REXB) IN 32b mode +RM=0 | OUTREG=XED_REG_EAX +RM=1 | OUTREG=XED_REG_ECX +RM=2 | OUTREG=XED_REG_EDX +RM=3 | OUTREG=XED_REG_EBX +RM=4 | OUTREG=XED_REG_ESP +RM=5 | OUTREG=XED_REG_EBP +RM=6 | OUTREG=XED_REG_ESI +RM=7 | OUTREG=XED_REG_EDI + + +xed_reg_enum_t VGPR32_B_64():: +REXB=0 RM=0 | OUTREG=XED_REG_EAX +REXB=0 RM=1 | OUTREG=XED_REG_ECX +REXB=0 RM=2 | OUTREG=XED_REG_EDX +REXB=0 RM=3 | OUTREG=XED_REG_EBX +REXB=0 RM=4 | OUTREG=XED_REG_ESP +REXB=0 RM=5 | OUTREG=XED_REG_EBP +REXB=0 RM=6 | OUTREG=XED_REG_ESI +REXB=0 RM=7 | OUTREG=XED_REG_EDI +REXB=1 RM=0 | OUTREG=XED_REG_R8D +REXB=1 RM=1 | OUTREG=XED_REG_R9D +REXB=1 RM=2 | OUTREG=XED_REG_R10D +REXB=1 RM=3 | OUTREG=XED_REG_R11D +REXB=1 RM=4 | OUTREG=XED_REG_R12D +REXB=1 RM=5 | OUTREG=XED_REG_R13D +REXB=1 RM=6 | OUTREG=XED_REG_R14D +REXB=1 RM=7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t VGPR64_B():: +REXB=0 RM=0 | OUTREG=XED_REG_RAX +REXB=0 RM=1 | OUTREG=XED_REG_RCX +REXB=0 RM=2 | OUTREG=XED_REG_RDX +REXB=0 RM=3 | OUTREG=XED_REG_RBX +REXB=0 RM=4 | OUTREG=XED_REG_RSP +REXB=0 RM=5 | OUTREG=XED_REG_RBP +REXB=0 RM=6 | OUTREG=XED_REG_RSI +REXB=0 RM=7 | OUTREG=XED_REG_RDI +REXB=1 RM=0 | OUTREG=XED_REG_R8 +REXB=1 RM=1 | OUTREG=XED_REG_R9 +REXB=1 RM=2 | OUTREG=XED_REG_R10 +REXB=1 RM=3 | OUTREG=XED_REG_R11 +REXB=1 RM=4 | OUTREG=XED_REG_R12 +REXB=1 RM=5 | OUTREG=XED_REG_R13 +REXB=1 RM=6 | OUTREG=XED_REG_R14 +REXB=1 RM=7 | OUTREG=XED_REG_R15 + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knm/knm-disp8.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +NELEM_TUPLE1_4X():: +VL128 | NELEM=4 +VL256 | NELEM=4 +VL512 | NELEM=4 + + + +###FILE: C:\$Fanta\IntelXED\xed\datafiles\knc\uisa-splitter.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +EVEX_SPLITTER():: +VEXVALID=0 INSTRUCTIONS() | +VEXVALID=1 AVX_INSTRUCTIONS() | +VEXVALID=2 EVEX_INSTRUCTIONS() | + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-evex-dec.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX512_ROUND():: +LLRC=0b00 | ROUNDC=1 SAE=1 +LLRC=0b01 | ROUNDC=2 SAE=1 +LLRC=0b10 | ROUNDC=3 SAE=1 +LLRC=0b11 | ROUNDC=4 SAE=1 + +SAE():: +BCRC=1 | SAE=1 +BCRC=0 | error + +# NEWKEY: VEXPFX_OP == 0x62 +# NEWKEY: MBITS --> REXR, REXX (complemented MBITS) +# NEWKEY: BRR -> REXB, REXRR (complemented BRR bits) +# NEWKEY: EVMAP -> V0F, V0F38, V0F3A or error +# NEWKEY: REXW +# NEWKEY: VEXDEST3 +# NEWKEY: VEXDEST210 +# NEWKEY: UBIT +# NEWKEY: VEXPP_OP -> VNP/V66/VF3/VF2 recoding +# NEWKEY: confirm no refining prefix or rex prefix +# NEWKEY: set VEXVALID=2 +# NEWKEY: ZEROING[z] +# NEWKEY: LLRCDECODE()-> LLRC -> VL128,256,512 or error +# NEWKEY: BCRC[b] +# NEWKEY: VEXDEST4P[p] +# NEWKEY: VEXDEST4_INVERT() <<<< invert VEXDEST4 +# NEWKEY: MASK[aaa] + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-disp8.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#The "MEM" suffix on tuples means NO BROADCAST ALLOWED + +# SET THE ELEMENT SIZE DURING DECODE -- using spreadsheet InputSize field +# FIXME: fix and use 'otherwise' instead of REX=0! +ESIZE_128_BITS():: +REX=0 | ELEMENT_SIZE=128 +ESIZE_64_BITS():: +REX=0 | ELEMENT_SIZE=64 +ESIZE_32_BITS():: +REX=0 | ELEMENT_SIZE=32 +ESIZE_16_BITS():: +REX=0 | ELEMENT_SIZE=16 +ESIZE_8_BITS():: +REX=0 | ELEMENT_SIZE=8 +ESIZE_4_BITS():: +REX=0 | ELEMENT_SIZE=4 +ESIZE_2_BITS():: +REX=0 | ELEMENT_SIZE=2 +ESIZE_1_BITS():: +REX=0 | ELEMENT_SIZE=1 + +# eightmem is a 8B reference +# quartermem is a 16B reference +# halfmem is a 32B reference +# fullmem is a 64B reference + +# legacy movddup references 64b when doing a 128b VL +# but acts like fullmem for 256/512. +NELEM_MOVDDUP():: +ELEMENT_SIZE=64 VL128 | NELEM=1 +ELEMENT_SIZE=64 VL256 | NELEM=4 +ELEMENT_SIZE=64 VL512 | NELEM=8 + +# element size is in bits... +NELEM_FULLMEM():: # updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=512 +ELEMENT_SIZE=2 VL512 | NELEM=256 +ELEMENT_SIZE=4 VL512 | NELEM=128 +ELEMENT_SIZE=8 VL512 | NELEM=64 +ELEMENT_SIZE=16 VL512 | NELEM=32 +ELEMENT_SIZE=32 VL512 | NELEM=16 +ELEMENT_SIZE=64 VL512 | NELEM=8 +ELEMENT_SIZE=128 VL512 | NELEM=4 +ELEMENT_SIZE=256 VL512 | NELEM=2 +ELEMENT_SIZE=512 VL512 | NELEM=1 + +ELEMENT_SIZE=1 VL256 | NELEM=256 +ELEMENT_SIZE=2 VL256 | NELEM=128 +ELEMENT_SIZE=4 VL256 | NELEM=64 +ELEMENT_SIZE=8 VL256 | NELEM=32 +ELEMENT_SIZE=16 VL256 | NELEM=16 +ELEMENT_SIZE=32 VL256 | NELEM=8 +ELEMENT_SIZE=64 VL256 | NELEM=4 +ELEMENT_SIZE=128 VL256 | NELEM=2 +ELEMENT_SIZE=256 VL256 | NELEM=1 +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=128 +ELEMENT_SIZE=2 VL128 | NELEM=64 +ELEMENT_SIZE=4 VL128 | NELEM=32 +ELEMENT_SIZE=8 VL128 | NELEM=16 +ELEMENT_SIZE=16 VL128 | NELEM=8 +ELEMENT_SIZE=32 VL128 | NELEM=4 +ELEMENT_SIZE=64 VL128 | NELEM=2 +ELEMENT_SIZE=128 VL128 | NELEM=1 +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + +NELEM_HALFMEM():: # 32B/256b reference updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=256 +ELEMENT_SIZE=2 VL512 | NELEM=128 +ELEMENT_SIZE=4 VL512 | NELEM=64 +ELEMENT_SIZE=8 VL512 | NELEM=32 +ELEMENT_SIZE=16 VL512 | NELEM=16 +ELEMENT_SIZE=32 VL512 | NELEM=8 +ELEMENT_SIZE=64 VL512 | NELEM=4 +ELEMENT_SIZE=128 VL512 | NELEM=2 +ELEMENT_SIZE=256 VL512 | NELEM=1 +ELEMENT_SIZE=512 VL512 | error + +ELEMENT_SIZE=1 VL256 | NELEM=128 +ELEMENT_SIZE=2 VL256 | NELEM=64 +ELEMENT_SIZE=4 VL256 | NELEM=32 +ELEMENT_SIZE=8 VL256 | NELEM=16 +ELEMENT_SIZE=16 VL256 | NELEM=8 +ELEMENT_SIZE=32 VL256 | NELEM=4 +ELEMENT_SIZE=64 VL256 | NELEM=2 +ELEMENT_SIZE=128 VL256 | NELEM=1 +ELEMENT_SIZE=256 VL256 | error +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=64 +ELEMENT_SIZE=2 VL128 | NELEM=32 +ELEMENT_SIZE=4 VL128 | NELEM=16 +ELEMENT_SIZE=8 VL128 | NELEM=8 +ELEMENT_SIZE=16 VL128 | NELEM=4 +ELEMENT_SIZE=32 VL128 | NELEM=2 +ELEMENT_SIZE=64 VL128 | NELEM=1 +ELEMENT_SIZE=128 VL128 | error +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + + +NELEM_QUARTERMEM():: # 16B/128b reference updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=128 +ELEMENT_SIZE=2 VL512 | NELEM=64 +ELEMENT_SIZE=4 VL512 | NELEM=32 +ELEMENT_SIZE=8 VL512 | NELEM=16 +ELEMENT_SIZE=16 VL512 | NELEM=8 +ELEMENT_SIZE=32 VL512 | NELEM=4 +ELEMENT_SIZE=64 VL512 | NELEM=2 +ELEMENT_SIZE=128 VL512 | NELEM=1 +ELEMENT_SIZE=256 VL512 | error +ELEMENT_SIZE=512 VL512 | error + +ELEMENT_SIZE=1 VL256 | NELEM=64 +ELEMENT_SIZE=2 VL256 | NELEM=32 +ELEMENT_SIZE=4 VL256 | NELEM=16 +ELEMENT_SIZE=8 VL256 | NELEM=8 +ELEMENT_SIZE=16 VL256 | NELEM=4 +ELEMENT_SIZE=32 VL256 | NELEM=2 +ELEMENT_SIZE=64 VL256 | NELEM=1 +ELEMENT_SIZE=128 VL256 | error +ELEMENT_SIZE=256 VL256 | error +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=32 +ELEMENT_SIZE=2 VL128 | NELEM=16 +ELEMENT_SIZE=4 VL128 | NELEM=8 +ELEMENT_SIZE=8 VL128 | NELEM=4 +ELEMENT_SIZE=16 VL128 | NELEM=2 +ELEMENT_SIZE=32 VL128 | NELEM=1 +ELEMENT_SIZE=64 VL128 | error +ELEMENT_SIZE=128 VL128 | error +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + + +NELEM_EIGHTHMEM():: # 8B/64b reference updated 2011-02-18 +ELEMENT_SIZE=1 VL512 | NELEM=64 +ELEMENT_SIZE=2 VL512 | NELEM=32 +ELEMENT_SIZE=4 VL512 | NELEM=16 +ELEMENT_SIZE=8 VL512 | NELEM=8 +ELEMENT_SIZE=16 VL512 | NELEM=4 +ELEMENT_SIZE=32 VL512 | NELEM=2 +ELEMENT_SIZE=64 VL512 | NELEM=1 +ELEMENT_SIZE=128 VL512 | error +ELEMENT_SIZE=256 VL512 | error +ELEMENT_SIZE=512 VL512 | error + +ELEMENT_SIZE=1 VL256 | NELEM=32 +ELEMENT_SIZE=2 VL256 | NELEM=16 +ELEMENT_SIZE=4 VL256 | NELEM=8 +ELEMENT_SIZE=8 VL256 | NELEM=4 +ELEMENT_SIZE=16 VL256 | NELEM=2 +ELEMENT_SIZE=32 VL256 | NELEM=1 +ELEMENT_SIZE=64 VL256 | error +ELEMENT_SIZE=128 VL256 | error +ELEMENT_SIZE=256 VL256 | error +ELEMENT_SIZE=512 VL256 | error + +ELEMENT_SIZE=1 VL128 | NELEM=16 +ELEMENT_SIZE=2 VL128 | NELEM=8 +ELEMENT_SIZE=4 VL128 | NELEM=4 +ELEMENT_SIZE=8 VL128 | NELEM=2 +ELEMENT_SIZE=16 VL128 | NELEM=1 +ELEMENT_SIZE=32 VL128 | error +ELEMENT_SIZE=64 VL128 | error +ELEMENT_SIZE=128 VL128 | error +ELEMENT_SIZE=256 VL128 | error +ELEMENT_SIZE=512 VL128 | error + +NELEM_GPR_READER_BYTE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_READER_WORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_LDOP_D():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_LDOP_Q():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE_BYTE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE_WORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_TUPLE1_BYTE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_TUPLE1_WORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 + +NELEM_SCALAR():: # same as tuple1 updated 2011-02-18 +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_TUPLE1_SUBDWORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_READER():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_READER_SUBDWORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_LDOP():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GPR_WRITER_STORE_SUBDWORD():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 + + +# TUPLE1,2,4,8, FULL and HALF + +NELEM_TUPLE1():: #updated 2011-02-18 +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 +NELEM_GSCAT():: +VL128 | NELEM=1 +VL256 | NELEM=1 +VL512 | NELEM=1 + + +NELEM_TUPLE2():: #updated 2011-02-18 +VL128 | NELEM=2 +VL256 | NELEM=2 +VL512 | NELEM=2 + +NELEM_TUPLE4():: #updated 2011-02-18 +VL128 | NELEM=4 +VL256 | NELEM=4 +VL512 | NELEM=4 + +NELEM_TUPLE8():: # updated 2011-02-18 +VL128 | NELEM=8 +VL256 | NELEM=8 +VL512 | NELEM=8 + +NELEM_MEM128():: # element_size=64 always!! SPECIAL updated 2011-02-18 +BCRC=0b0 | ELEMENT_SIZE=64 NELEM=2 +BCRC=0b1 | error + + +NELEM_FULL():: +BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=32 +BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO32_16 +BCRC=0b0 ELEMENT_SIZE=32 VL512 | NELEM=16 +BCRC=0b1 ELEMENT_SIZE=32 VL512 | NELEM=1 EMX_BROADCAST_1TO16_32 +BCRC=0b0 ELEMENT_SIZE=64 VL512 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=64 VL512 | NELEM=1 EMX_BROADCAST_1TO8_64 + +BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=16 +BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO16_16 +BCRC=0b0 ELEMENT_SIZE=32 VL256 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=32 VL256 | NELEM=1 EMX_BROADCAST_1TO8_32 +BCRC=0b0 ELEMENT_SIZE=64 VL256 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=64 VL256 | NELEM=1 EMX_BROADCAST_1TO4_64 + +BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO8_16 +BCRC=0b0 ELEMENT_SIZE=32 VL128 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=32 VL128 | NELEM=1 EMX_BROADCAST_1TO4_32 +BCRC=0b0 ELEMENT_SIZE=64 VL128 | NELEM=2 +BCRC=0b1 ELEMENT_SIZE=64 VL128 | NELEM=1 EMX_BROADCAST_1TO2_64 + + +# 512b=64B=16DW=8QW -> Half = 256b=32B=8DWORDS=4QWORDS +# 256b=32B=8DW=4QW -> Half = 128b=16B=4DW=2QW +# 128b=16B=4DW=2QW -> Half = 64b=8B=2DW=1QW +NELEM_HALF():: # updated 2011-02-18 +BCRC=0b0 ELEMENT_SIZE=32 VL512 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=32 VL512 | NELEM=1 EMX_BROADCAST_1TO8_32 + +BCRC=0b0 ELEMENT_SIZE=32 VL256 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=32 VL256 | NELEM=1 EMX_BROADCAST_1TO4_32 + +BCRC=0b0 ELEMENT_SIZE=32 VL128 | NELEM=2 +BCRC=0b1 ELEMENT_SIZE=32 VL128 | NELEM=1 EMX_BROADCAST_1TO2_32 + + +# For reg/reg ops with rounding control, we have to avoid having the +# RC bits mes up the length. So we fix them here. +FIX_ROUND_LEN512():: +mode16 | VL512 +mode32 | VL512 +mode64 | VL512 +FIX_ROUND_LEN128():: +mode16 | VL128 +mode32 | VL128 +mode64 | VL128 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-addressing-dec.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +UISA_VMODRM_ZMM():: + MOD=0b00 UISA_VSIB_ZMM() | + MOD=0b01 UISA_VSIB_ZMM() MEMDISP8() | + MOD=0b10 UISA_VSIB_ZMM() MEMDISP32() | + +UISA_VMODRM_YMM():: + MOD=0b00 UISA_VSIB_YMM() | + MOD=0b01 UISA_VSIB_YMM() MEMDISP8() | + MOD=0b10 UISA_VSIB_YMM() MEMDISP32() | + +UISA_VMODRM_XMM():: + MOD=0b00 UISA_VSIB_XMM() | + MOD=0b01 UISA_VSIB_XMM() MEMDISP8() | + MOD=0b10 UISA_VSIB_XMM() MEMDISP32() | + + +UISA_VSIB_ZMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=8 +UISA_VSIB_YMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=8 +UISA_VSIB_XMM():: +SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=1 +SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=2 +SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=4 +SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=8 + + +xed_reg_enum_t UISA_VSIB_INDEX_ZMM():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM31 + + + +xed_reg_enum_t UISA_VSIB_INDEX_YMM():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM31 + + +xed_reg_enum_t UISA_VSIB_INDEX_XMM():: +VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM0 +VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM1 +VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM2 +VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM3 +VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM4 +VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM5 +VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM6 +VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM7 +VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM8 +VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM9 +VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM10 +VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM11 +VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM12 +VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM13 +VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM14 +VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM15 +VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM16 +VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM17 +VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM18 +VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM19 +VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM20 +VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM21 +VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM22 +VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM23 +VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM24 +VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM25 +VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM26 +VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM27 +VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM28 +VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM29 +VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM30 +VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM31 + + +UISA_VSIB_BASE():: +REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG() + +# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8 and DISP32 +REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG() + +REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG() +REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG() + +# FIXME: BASE ISA IS CONSIDERABLY MORE COMPLICATED FOR DISP8 and DISP32 +REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() +REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG() + +REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG() +REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG() + + + + + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-table-mask.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# FIXME: the rest of this file is common w/KNC. Split it out to avoid +# duplication + +xed_reg_enum_t MASK1():: +MASK=0x0 | OUTREG=XED_REG_K0 +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +xed_reg_enum_t MASKNOT0():: +MASK=0x0 | OUTREG=XED_REG_ERROR +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +# used for compares in EVEX +xed_reg_enum_t MASK_R():: +REXRR=0 REXR=0 REG=0x0 | OUTREG=XED_REG_K0 +REXRR=0 REXR=0 REG=0x1 | OUTREG=XED_REG_K1 +REXRR=0 REXR=0 REG=0x2 | OUTREG=XED_REG_K2 +REXRR=0 REXR=0 REG=0x3 | OUTREG=XED_REG_K3 +REXRR=0 REXR=0 REG=0x4 | OUTREG=XED_REG_K4 +REXRR=0 REXR=0 REG=0x5 | OUTREG=XED_REG_K5 +REXRR=0 REXR=0 REG=0x6 | OUTREG=XED_REG_K6 +REXRR=0 REXR=0 REG=0x7 | OUTREG=XED_REG_K7 + +# MASK_B is used by VEX and EVEX encodings. SDM (rev 062) states in +# EVEX, EVEX.B (REXB) is ignored. SDM does not (yet) say what happens +# on VEX.B but assuming it is similar. + +xed_reg_enum_t MASK_B():: +RM=0x0 | OUTREG=XED_REG_K0 +RM=0x1 | OUTREG=XED_REG_K1 +RM=0x2 | OUTREG=XED_REG_K2 +RM=0x3 | OUTREG=XED_REG_K3 +RM=0x4 | OUTREG=XED_REG_K4 +RM=0x5 | OUTREG=XED_REG_K5 +RM=0x6 | OUTREG=XED_REG_K6 +RM=0x7 | OUTREG=XED_REG_K7 + +# only used in VEX space for K-mask ops +# stored inverted +xed_reg_enum_t MASK_N():: +mode64 | OUTREG=MASK_N64() +mode32 | OUTREG=MASK_N32() +mode16 | OUTREG=MASK_N32() + +xed_reg_enum_t MASK_N64():: +VEXDEST3=1 VEXDEST210=0x0 | OUTREG=XED_REG_K7 +VEXDEST3=1 VEXDEST210=0x1 | OUTREG=XED_REG_K6 +VEXDEST3=1 VEXDEST210=0x2 | OUTREG=XED_REG_K5 +VEXDEST3=1 VEXDEST210=0x3 | OUTREG=XED_REG_K4 +VEXDEST3=1 VEXDEST210=0x4 | OUTREG=XED_REG_K3 +VEXDEST3=1 VEXDEST210=0x5 | OUTREG=XED_REG_K2 +VEXDEST3=1 VEXDEST210=0x6 | OUTREG=XED_REG_K1 +VEXDEST3=1 VEXDEST210=0x7 | OUTREG=XED_REG_K0 + +xed_reg_enum_t MASK_N32():: +VEXDEST210=0x0 | OUTREG=XED_REG_K7 +VEXDEST210=0x1 | OUTREG=XED_REG_K6 +VEXDEST210=0x2 | OUTREG=XED_REG_K5 +VEXDEST210=0x3 | OUTREG=XED_REG_K4 +VEXDEST210=0x4 | OUTREG=XED_REG_K3 +VEXDEST210=0x5 | OUTREG=XED_REG_K2 +VEXDEST210=0x6 | OUTREG=XED_REG_K1 +VEXDEST210=0x7 | OUTREG=XED_REG_K0 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-r3.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_R3():: +mode16 | OUTREG=XMM_R3_32() +mode32 | OUTREG=XMM_R3_32() +mode64 | OUTREG=XMM_R3_64() + +xed_reg_enum_t XMM_R3_32():: +REG=0 | OUTREG=XED_REG_XMM0 +REG=1 | OUTREG=XED_REG_XMM1 +REG=2 | OUTREG=XED_REG_XMM2 +REG=3 | OUTREG=XED_REG_XMM3 +REG=4 | OUTREG=XED_REG_XMM4 +REG=5 | OUTREG=XED_REG_XMM5 +REG=6 | OUTREG=XED_REG_XMM6 +REG=7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7 + +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31 + + +xed_reg_enum_t YMM_R3():: +mode16 | OUTREG=YMM_R3_32() +mode32 | OUTREG=YMM_R3_32() +mode64 | OUTREG=YMM_R3_64() + +xed_reg_enum_t YMM_R3_32():: +REG=0 | OUTREG=XED_REG_YMM0 +REG=1 | OUTREG=XED_REG_YMM1 +REG=2 | OUTREG=XED_REG_YMM2 +REG=3 | OUTREG=XED_REG_YMM3 +REG=4 | OUTREG=XED_REG_YMM4 +REG=5 | OUTREG=XED_REG_YMM5 +REG=6 | OUTREG=XED_REG_YMM6 +REG=7 | OUTREG=XED_REG_YMM7 +xed_reg_enum_t YMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31 + + + +xed_reg_enum_t ZMM_R3():: +mode16 | OUTREG=ZMM_R3_32() +mode32 | OUTREG=ZMM_R3_32() +mode64 | OUTREG=ZMM_R3_64() + +xed_reg_enum_t ZMM_R3_32():: +REG=0 | OUTREG=XED_REG_ZMM0 +REG=1 | OUTREG=XED_REG_ZMM1 +REG=2 | OUTREG=XED_REG_ZMM2 +REG=3 | OUTREG=XED_REG_ZMM3 +REG=4 | OUTREG=XED_REG_ZMM4 +REG=5 | OUTREG=XED_REG_ZMM5 +REG=6 | OUTREG=XED_REG_ZMM6 +REG=7 | OUTREG=XED_REG_ZMM7 + +xed_reg_enum_t ZMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-b3.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_B3():: +mode16 | OUTREG=XMM_B3_32() +mode32 | OUTREG=XMM_B3_32() +mode64 | OUTREG=XMM_B3_64() + +xed_reg_enum_t XMM_B3_32():: +RM=0 | OUTREG=XED_REG_XMM0 +RM=1 | OUTREG=XED_REG_XMM1 +RM=2 | OUTREG=XED_REG_XMM2 +RM=3 | OUTREG=XED_REG_XMM3 +RM=4 | OUTREG=XED_REG_XMM4 +RM=5 | OUTREG=XED_REG_XMM5 +RM=6 | OUTREG=XED_REG_XMM6 +RM=7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_XMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_XMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_XMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_XMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_XMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_XMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_XMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_XMM7 + +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_XMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_XMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_XMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_XMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_XMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_XMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_XMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_XMM15 + +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_XMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_XMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_XMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_XMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_XMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_XMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_XMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_XMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_XMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_XMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_XMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_XMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_XMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_XMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_XMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_XMM31 + + + +xed_reg_enum_t YMM_B3():: +mode16 | OUTREG=YMM_B3_32() +mode32 | OUTREG=YMM_B3_32() +mode64 | OUTREG=YMM_B3_64() + +xed_reg_enum_t YMM_B3_32():: +RM=0 | OUTREG=XED_REG_YMM0 +RM=1 | OUTREG=XED_REG_YMM1 +RM=2 | OUTREG=XED_REG_YMM2 +RM=3 | OUTREG=XED_REG_YMM3 +RM=4 | OUTREG=XED_REG_YMM4 +RM=5 | OUTREG=XED_REG_YMM5 +RM=6 | OUTREG=XED_REG_YMM6 +RM=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_YMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_YMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_YMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_YMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_YMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_YMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_YMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_YMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_YMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_YMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_YMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_YMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_YMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_YMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_YMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_YMM15 + +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_YMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_YMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_YMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_YMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_YMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_YMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_YMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_YMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_YMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_YMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_YMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_YMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_YMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_YMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_YMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_YMM31 + + + +xed_reg_enum_t ZMM_B3():: +mode16 | OUTREG=ZMM_B3_32() +mode32 | OUTREG=ZMM_B3_32() +mode64 | OUTREG=ZMM_B3_64() + +xed_reg_enum_t ZMM_B3_32():: +RM=0 | OUTREG=XED_REG_ZMM0 +RM=1 | OUTREG=XED_REG_ZMM1 +RM=2 | OUTREG=XED_REG_ZMM2 +RM=3 | OUTREG=XED_REG_ZMM3 +RM=4 | OUTREG=XED_REG_ZMM4 +RM=5 | OUTREG=XED_REG_ZMM5 +RM=6 | OUTREG=XED_REG_ZMM6 +RM=7 | OUTREG=XED_REG_ZMM7 + +xed_reg_enum_t ZMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15 +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-n3.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_N3():: +mode16 | OUTREG=XMM_N3_32() +mode32 | OUTREG=XMM_N3_32() +mode64 | OUTREG=XMM_N3_64() + +xed_reg_enum_t XMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31 + + +xed_reg_enum_t YMM_N3():: +mode16 | OUTREG=YMM_N3_32() +mode32 | OUTREG=YMM_N3_32() +mode64 | OUTREG=YMM_N3_64() + +xed_reg_enum_t YMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST210=0 | OUTREG=XED_REG_YMM7 + + +xed_reg_enum_t YMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31 + + +xed_reg_enum_t ZMM_N3():: +mode16 | OUTREG=ZMM_N3_32() +mode32 | OUTREG=ZMM_N3_32() +mode64 | OUTREG=ZMM_N3_64() + + +xed_reg_enum_t ZMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST210=0 | OUTREG=XED_REG_ZMM7 + + +xed_reg_enum_t ZMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-reg-tables.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t TMM_R():: +REXR=0 REG=0 | OUTREG=XED_REG_TMM0 +REXR=0 REG=1 | OUTREG=XED_REG_TMM1 +REXR=0 REG=2 | OUTREG=XED_REG_TMM2 +REXR=0 REG=3 | OUTREG=XED_REG_TMM3 +REXR=0 REG=4 | OUTREG=XED_REG_TMM4 +REXR=0 REG=5 | OUTREG=XED_REG_TMM5 +REXR=0 REG=6 | OUTREG=XED_REG_TMM6 +REXR=0 REG=7 | OUTREG=XED_REG_TMM7 + +xed_reg_enum_t TMM_B():: +REXB=0 RM=0 | OUTREG=XED_REG_TMM0 +REXB=0 RM=1 | OUTREG=XED_REG_TMM1 +REXB=0 RM=2 | OUTREG=XED_REG_TMM2 +REXB=0 RM=3 | OUTREG=XED_REG_TMM3 +REXB=0 RM=4 | OUTREG=XED_REG_TMM4 +REXB=0 RM=5 | OUTREG=XED_REG_TMM5 +REXB=0 RM=6 | OUTREG=XED_REG_TMM6 +REXB=0 RM=7 | OUTREG=XED_REG_TMM7 + + +xed_reg_enum_t TMM_N():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_TMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_TMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_TMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_TMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_TMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_TMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_TMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_TMM7 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-evex-disp8-fp16.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +NELEM_HALF():: +BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=16 +BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO16_16 + +BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO8_16 + +BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO4_16 + + +NELEM_QUARTER():: +BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=8 +BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO8_16 + +BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=4 +BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO4_16 + +BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=2 +BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO2_16 + + diff --git a/CodeVirtualizer/build/obj/dgen/all-dec-spine.txt b/CodeVirtualizer/build/obj/dgen/all-dec-spine.txt new file mode 100644 index 0000000..da21be1 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-dec-spine.txt @@ -0,0 +1,25 @@ + + +###FILE: C:\$Fanta\IntelXED\xed\datafiles\knc\uisa-spine.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ISA():: +PREFIXES() OSZ_NONTERM() ASZ_NONTERM() EVEX_SPLITTER() | + + diff --git a/CodeVirtualizer/build/obj/dgen/all-element-type-base.txt b/CodeVirtualizer/build/obj/dgen/all-element-type-base.txt new file mode 100644 index 0000000..0b07415 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-element-type-base.txt @@ -0,0 +1,84 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-operand-element-type-enum-base.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +hfn xed-operand-element-type-enum.h +cfn xed-operand-element-type-enum.c +prefix XED_OPERAND_ELEMENT_TYPE_ +typename xed_operand_element_type_enum_t +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +UINT ///< Unsigned integer +INT ///< Signed integer +SINGLE ///< 32b FP single precision +DOUBLE ///< 64b FP double precision +LONGDOUBLE ///< 80b FP x87 +LONGBCD ///< 80b decimal BCD +STRUCT ///< a structure of various fields +VARIABLE ///< depends on other fields in the instruction + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/fp16-element-type-enum.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +FLOAT16 ///< 16b floating point + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-element-type-enum.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BFLOAT16 ///< bfloat16 floating point + diff --git a/CodeVirtualizer/build/obj/dgen/all-element-types.txt b/CodeVirtualizer/build/obj/dgen/all-element-types.txt new file mode 100644 index 0000000..5355812 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-element-types.txt @@ -0,0 +1,116 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-operand-types.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +#XTYPE TYPE BITS-PER-ELEM +# +var VARIABLE 0 # instruction must set NELEM and ELEMENT_SIZE +struct STRUCT 0 # many elements of different widths +int INT 0 # one element, all the bits, width varies +uint UINT 0 # one element, all the bits, width varies +# +i1 INT 1 +i8 INT 8 +i16 INT 16 +i32 INT 32 +i64 INT 64 +u8 UINT 8 +u16 UINT 16 +u32 UINT 32 +u64 UINT 64 +u128 UINT 128 +u256 UINT 256 +f32 SINGLE 32 +f64 DOUBLE 64 +f80 LONGDOUBLE 80 +b80 LONGBCD 80 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/fp16-operand-types.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#XTYPE TYPE BITS-PER-ELEM +f16 FLOAT16 16 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-element-types.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +bf16 BFLOAT16 16 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/operand-types.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#XTYPE TYPE BITS-PER-ELEM +2f16 FLOAT16 32 + diff --git a/CodeVirtualizer/build/obj/dgen/all-enc-dec-patterns.txt b/CodeVirtualizer/build/obj/dgen/all-enc-dec-patterns.txt new file mode 100644 index 0000000..29fcc89 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-enc-dec-patterns.txt @@ -0,0 +1,2158 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-reg-tables.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +######################################################################## +## file: xed-reg-tables.txt +######################################################################## + +# Need to handle flags, rIP, seg-selectors, pseudo regs +# Also does not specify register width + +# What about something like this: +# op1=GPRv_R():rw +# we need to know what to bind the result to ultimately. +# Just specifying a register is confusing to me. Don't know where to store it. +# Have a "store-here" location for this kind of thing? + +####################################################################### +# Expand the generic registers using the effective address size EASZ +####################################################################### +xed_reg_enum_t ArAX():: +EASZ=1 | OUTREG=XED_REG_AX +EASZ=2 | OUTREG=XED_REG_EAX +EASZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t ArBX():: +EASZ=1 | OUTREG=XED_REG_BX +EASZ=2 | OUTREG=XED_REG_EBX +EASZ=3 | OUTREG=XED_REG_RBX +xed_reg_enum_t ArCX():: +EASZ=1 | OUTREG=XED_REG_CX +EASZ=2 | OUTREG=XED_REG_ECX +EASZ=3 | OUTREG=XED_REG_RCX +xed_reg_enum_t ArDX():: +EASZ=1 | OUTREG=XED_REG_DX +EASZ=2 | OUTREG=XED_REG_EDX +EASZ=3 | OUTREG=XED_REG_RDX + +xed_reg_enum_t ArSI():: +EASZ=1 | OUTREG=XED_REG_SI +EASZ=2 | OUTREG=XED_REG_ESI +EASZ=3 | OUTREG=XED_REG_RSI +xed_reg_enum_t ArDI():: +EASZ=1 | OUTREG=XED_REG_DI +EASZ=2 | OUTREG=XED_REG_EDI +EASZ=3 | OUTREG=XED_REG_RDI +xed_reg_enum_t ArSP():: +EASZ=1 | OUTREG=XED_REG_SP +EASZ=2 | OUTREG=XED_REG_ESP +EASZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t ArBP():: +EASZ=1 | OUTREG=XED_REG_BP +EASZ=2 | OUTREG=XED_REG_EBP +EASZ=3 | OUTREG=XED_REG_RBP + +xed_reg_enum_t SrSP():: +smode16 | OUTREG=XED_REG_SP +smode32 | OUTREG=XED_REG_ESP +smode64 | OUTREG=XED_REG_RSP +xed_reg_enum_t SrBP():: +smode16 | OUTREG=XED_REG_BP +smode32 | OUTREG=XED_REG_EBP +smode64 | OUTREG=XED_REG_RBP + +xed_reg_enum_t Ar8():: +EASZ=1 | OUTREG=XED_REG_R8W +EASZ=2 | OUTREG=XED_REG_R8D +EASZ=3 | OUTREG=XED_REG_R8 +xed_reg_enum_t Ar9():: +EASZ=1 | OUTREG=XED_REG_R9W +EASZ=2 | OUTREG=XED_REG_R9D +EASZ=3 | OUTREG=XED_REG_R9 +xed_reg_enum_t Ar10():: +EASZ=1 | OUTREG=XED_REG_R10W +EASZ=2 | OUTREG=XED_REG_R10D +EASZ=3 | OUTREG=XED_REG_R10 +xed_reg_enum_t Ar11():: +EASZ=1 | OUTREG=XED_REG_R11W +EASZ=2 | OUTREG=XED_REG_R11D +EASZ=3 | OUTREG=XED_REG_R11 +xed_reg_enum_t Ar12():: +EASZ=1 | OUTREG=XED_REG_R12W +EASZ=2 | OUTREG=XED_REG_R12D +EASZ=3 | OUTREG=XED_REG_R12 +xed_reg_enum_t Ar13():: +EASZ=1 | OUTREG=XED_REG_R13W +EASZ=2 | OUTREG=XED_REG_R13D +EASZ=3 | OUTREG=XED_REG_R13 +xed_reg_enum_t Ar14():: +EASZ=1 | OUTREG=XED_REG_R14W +EASZ=2 | OUTREG=XED_REG_R14D +EASZ=3 | OUTREG=XED_REG_R14 +xed_reg_enum_t Ar15():: +EASZ=1 | OUTREG=XED_REG_R15W +EASZ=2 | OUTREG=XED_REG_R15D +EASZ=3 | OUTREG=XED_REG_R15 + +xed_reg_enum_t rIP():: +mode16 | OUTREG=XED_REG_EIP +mode32 | OUTREG=XED_REG_EIP +mode64 | OUTREG=XED_REG_RIP + +xed_reg_enum_t rIPa():: +EASZ=2 | OUTREG=XED_REG_EIP +EASZ=3 | OUTREG=XED_REG_RIP + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 32b +####################################################################### + + +xed_reg_enum_t OeAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_EAX + + +####################################################################### +# Expand the generic registers using the effective address size EOSZ - limit 64b +####################################################################### + +xed_reg_enum_t OrAX():: +EOSZ=1 | OUTREG=XED_REG_AX +EOSZ=2 | OUTREG=XED_REG_EAX +EOSZ=3 | OUTREG=XED_REG_RAX +xed_reg_enum_t OrDX():: +EOSZ=1 | OUTREG=XED_REG_DX +EOSZ=2 | OUTREG=XED_REG_EDX +EOSZ=3 | OUTREG=XED_REG_RDX + +# only used for VIA PADLOCK ISA: +xed_reg_enum_t OrCX():: +EOSZ=1 | OUTREG=XED_REG_CX +EOSZ=2 | OUTREG=XED_REG_ECX +EOSZ=3 | OUTREG=XED_REG_RCX +# only used for VIA PADLOCK ISA: +xed_reg_enum_t OrBX():: +EOSZ=1 | OUTREG=XED_REG_BX +EOSZ=2 | OUTREG=XED_REG_EBX +EOSZ=3 | OUTREG=XED_REG_RBX + +xed_reg_enum_t OrSP():: +EOSZ=1 | OUTREG=XED_REG_SP +EOSZ=2 | OUTREG=XED_REG_ESP +EOSZ=3 | OUTREG=XED_REG_RSP +xed_reg_enum_t OrBP():: +EOSZ=1 | OUTREG=XED_REG_BP +EOSZ=2 | OUTREG=XED_REG_EBP +EOSZ=3 | OUTREG=XED_REG_RBP + + +##################################################### + +xed_reg_enum_t rFLAGS():: +mode16 | OUTREG=XED_REG_FLAGS +mode32 | OUTREG=XED_REG_EFLAGS +mode64 | OUTREG=XED_REG_RFLAGS + +##################################################### + + +xed_reg_enum_t MMX_R():: +REG=0x0 | OUTREG=XED_REG_MMX0 +REG=0x1 | OUTREG=XED_REG_MMX1 +REG=0x2 | OUTREG=XED_REG_MMX2 +REG=0x3 | OUTREG=XED_REG_MMX3 +REG=0x4 | OUTREG=XED_REG_MMX4 +REG=0x5 | OUTREG=XED_REG_MMX5 +REG=0x6 | OUTREG=XED_REG_MMX6 +REG=0x7 | OUTREG=XED_REG_MMX7 + +xed_reg_enum_t MMX_B():: +RM=0x0 | OUTREG=XED_REG_MMX0 +RM=0x1 | OUTREG=XED_REG_MMX1 +RM=0x2 | OUTREG=XED_REG_MMX2 +RM=0x3 | OUTREG=XED_REG_MMX3 +RM=0x4 | OUTREG=XED_REG_MMX4 +RM=0x5 | OUTREG=XED_REG_MMX5 +RM=0x6 | OUTREG=XED_REG_MMX6 +RM=0x7 | OUTREG=XED_REG_MMX7 + +################################# + +# Things that scale with effective operand size + + + +# When used as the MODRM.REG register +xed_reg_enum_t GPRv_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +xed_reg_enum_t GPRv_SB():: +EOSZ=3 | OUTREG=GPR64_SB() +EOSZ=2 | OUTREG=GPR32_SB() +EOSZ=1 | OUTREG=GPR16_SB() + +xed_reg_enum_t GPRz_R():: +EOSZ=3 | OUTREG=GPR32_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR16_R() + +# When used as the MOD=11/RM register +xed_reg_enum_t GPRv_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRz_B():: +EOSZ=3 | OUTREG=GPR32_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR16_B() + +xed_reg_enum_t GPRy_B():: +EOSZ=3 | OUTREG=GPR64_B() +EOSZ=2 | OUTREG=GPR32_B() +EOSZ=1 | OUTREG=GPR32_B() + +xed_reg_enum_t GPRy_R():: +EOSZ=3 | OUTREG=GPR64_R() +EOSZ=2 | OUTREG=GPR32_R() +EOSZ=1 | OUTREG=GPR32_R() + +##################################### + +xed_reg_enum_t GPR64_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_RAX +REXR=0 REG=0x1 | OUTREG=XED_REG_RCX +REXR=0 REG=0x2 | OUTREG=XED_REG_RDX +REXR=0 REG=0x3 | OUTREG=XED_REG_RBX +REXR=0 REG=0x4 | OUTREG=XED_REG_RSP +REXR=0 REG=0x5 | OUTREG=XED_REG_RBP +REXR=0 REG=0x6 | OUTREG=XED_REG_RSI +REXR=0 REG=0x7 | OUTREG=XED_REG_RDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8 +REXR=1 REG=0x1 | OUTREG=XED_REG_R9 +REXR=1 REG=0x2 | OUTREG=XED_REG_R10 +REXR=1 REG=0x3 | OUTREG=XED_REG_R11 +REXR=1 REG=0x4 | OUTREG=XED_REG_R12 +REXR=1 REG=0x5 | OUTREG=XED_REG_R13 +REXR=1 REG=0x6 | OUTREG=XED_REG_R14 +REXR=1 REG=0x7 | OUTREG=XED_REG_R15 + + +xed_reg_enum_t GPR64_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_RAX +REXB=0 RM=0x1 | OUTREG=XED_REG_RCX +REXB=0 RM=0x2 | OUTREG=XED_REG_RDX +REXB=0 RM=0x3 | OUTREG=XED_REG_RBX +REXB=0 RM=0x4 | OUTREG=XED_REG_RSP +REXB=0 RM=0x5 | OUTREG=XED_REG_RBP +REXB=0 RM=0x6 | OUTREG=XED_REG_RSI +REXB=0 RM=0x7 | OUTREG=XED_REG_RDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8 +REXB=1 RM=0x1 | OUTREG=XED_REG_R9 +REXB=1 RM=0x2 | OUTREG=XED_REG_R10 +REXB=1 RM=0x3 | OUTREG=XED_REG_R11 +REXB=1 RM=0x4 | OUTREG=XED_REG_R12 +REXB=1 RM=0x5 | OUTREG=XED_REG_R13 +REXB=1 RM=0x6 | OUTREG=XED_REG_R14 +REXB=1 RM=0x7 | OUTREG=XED_REG_R15 + +xed_reg_enum_t GPR64_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_RAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_RCX +REXB=0 SRM=0x2 | OUTREG=XED_REG_RDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_RBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_RSP +REXB=0 SRM=0x5 | OUTREG=XED_REG_RBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_RSI +REXB=0 SRM=0x7 | OUTREG=XED_REG_RDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8 +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9 +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10 +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11 +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12 +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13 +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14 +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15 + + + +xed_reg_enum_t GPR64_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_RAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_RCX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_RDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_RBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_RBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_RSI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_RDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8 +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9 +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10 +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11 +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12 +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13 +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14 +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15 + + +################################# + + +xed_reg_enum_t GPR32_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_EAX +REXR=0 REG=0x1 | OUTREG=XED_REG_ECX +REXR=0 REG=0x2 | OUTREG=XED_REG_EDX +REXR=0 REG=0x3 | OUTREG=XED_REG_EBX +REXR=0 REG=0x4 | OUTREG=XED_REG_ESP +REXR=0 REG=0x5 | OUTREG=XED_REG_EBP +REXR=0 REG=0x6 | OUTREG=XED_REG_ESI +REXR=0 REG=0x7 | OUTREG=XED_REG_EDI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8D +REXR=1 REG=0x1 | OUTREG=XED_REG_R9D +REXR=1 REG=0x2 | OUTREG=XED_REG_R10D +REXR=1 REG=0x3 | OUTREG=XED_REG_R11D +REXR=1 REG=0x4 | OUTREG=XED_REG_R12D +REXR=1 REG=0x5 | OUTREG=XED_REG_R13D +REXR=1 REG=0x6 | OUTREG=XED_REG_R14D +REXR=1 REG=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_EAX +REXB=0 RM=0x1 | OUTREG=XED_REG_ECX +REXB=0 RM=0x2 | OUTREG=XED_REG_EDX +REXB=0 RM=0x3 | OUTREG=XED_REG_EBX +REXB=0 RM=0x4 | OUTREG=XED_REG_ESP +REXB=0 RM=0x5 | OUTREG=XED_REG_EBP +REXB=0 RM=0x6 | OUTREG=XED_REG_ESI +REXB=0 RM=0x7 | OUTREG=XED_REG_EDI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8D +REXB=1 RM=0x1 | OUTREG=XED_REG_R9D +REXB=1 RM=0x2 | OUTREG=XED_REG_R10D +REXB=1 RM=0x3 | OUTREG=XED_REG_R11D +REXB=1 RM=0x4 | OUTREG=XED_REG_R12D +REXB=1 RM=0x5 | OUTREG=XED_REG_R13D +REXB=1 RM=0x6 | OUTREG=XED_REG_R14D +REXB=1 RM=0x7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t GPR32_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_EAX +REXB=0 SRM=0x1 | OUTREG=XED_REG_ECX +REXB=0 SRM=0x2 | OUTREG=XED_REG_EDX +REXB=0 SRM=0x3 | OUTREG=XED_REG_EBX +REXB=0 SRM=0x4 | OUTREG=XED_REG_ESP +REXB=0 SRM=0x5 | OUTREG=XED_REG_EBP +REXB=0 SRM=0x6 | OUTREG=XED_REG_ESI +REXB=0 SRM=0x7 | OUTREG=XED_REG_EDI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8D +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9D +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10D +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11D +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12D +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13D +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14D +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15D + + + + + +xed_reg_enum_t GPR32_X():: +REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_EAX +REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_ECX +REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_EDX +REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_EBX +REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID +REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_EBP +REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_ESI +REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_EDI +REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8D +REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9D +REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10D +REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11D +REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12D +REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13D +REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14D +REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15D + + +############################# + + +xed_reg_enum_t GPR16_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_AX +REXR=0 REG=0x1 | OUTREG=XED_REG_CX +REXR=0 REG=0x2 | OUTREG=XED_REG_DX +REXR=0 REG=0x3 | OUTREG=XED_REG_BX +REXR=0 REG=0x4 | OUTREG=XED_REG_SP +REXR=0 REG=0x5 | OUTREG=XED_REG_BP +REXR=0 REG=0x6 | OUTREG=XED_REG_SI +REXR=0 REG=0x7 | OUTREG=XED_REG_DI +REXR=1 REG=0x0 | OUTREG=XED_REG_R8W +REXR=1 REG=0x1 | OUTREG=XED_REG_R9W +REXR=1 REG=0x2 | OUTREG=XED_REG_R10W +REXR=1 REG=0x3 | OUTREG=XED_REG_R11W +REXR=1 REG=0x4 | OUTREG=XED_REG_R12W +REXR=1 REG=0x5 | OUTREG=XED_REG_R13W +REXR=1 REG=0x6 | OUTREG=XED_REG_R14W +REXR=1 REG=0x7 | OUTREG=XED_REG_R15W + + + +xed_reg_enum_t GPR16_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_AX +REXB=0 RM=0x1 | OUTREG=XED_REG_CX +REXB=0 RM=0x2 | OUTREG=XED_REG_DX +REXB=0 RM=0x3 | OUTREG=XED_REG_BX +REXB=0 RM=0x4 | OUTREG=XED_REG_SP +REXB=0 RM=0x5 | OUTREG=XED_REG_BP +REXB=0 RM=0x6 | OUTREG=XED_REG_SI +REXB=0 RM=0x7 | OUTREG=XED_REG_DI +REXB=1 RM=0x0 | OUTREG=XED_REG_R8W +REXB=1 RM=0x1 | OUTREG=XED_REG_R9W +REXB=1 RM=0x2 | OUTREG=XED_REG_R10W +REXB=1 RM=0x3 | OUTREG=XED_REG_R11W +REXB=1 RM=0x4 | OUTREG=XED_REG_R12W +REXB=1 RM=0x5 | OUTREG=XED_REG_R13W +REXB=1 RM=0x6 | OUTREG=XED_REG_R14W +REXB=1 RM=0x7 | OUTREG=XED_REG_R15W + +xed_reg_enum_t GPR16_SB():: +REXB=0 SRM=0x0 | OUTREG=XED_REG_AX +REXB=0 SRM=0x1 | OUTREG=XED_REG_CX +REXB=0 SRM=0x2 | OUTREG=XED_REG_DX +REXB=0 SRM=0x3 | OUTREG=XED_REG_BX +REXB=0 SRM=0x4 | OUTREG=XED_REG_SP +REXB=0 SRM=0x5 | OUTREG=XED_REG_BP +REXB=0 SRM=0x6 | OUTREG=XED_REG_SI +REXB=0 SRM=0x7 | OUTREG=XED_REG_DI +REXB=1 SRM=0x0 | OUTREG=XED_REG_R8W +REXB=1 SRM=0x1 | OUTREG=XED_REG_R9W +REXB=1 SRM=0x2 | OUTREG=XED_REG_R10W +REXB=1 SRM=0x3 | OUTREG=XED_REG_R11W +REXB=1 SRM=0x4 | OUTREG=XED_REG_R12W +REXB=1 SRM=0x5 | OUTREG=XED_REG_R13W +REXB=1 SRM=0x6 | OUTREG=XED_REG_R14W +REXB=1 SRM=0x7 | OUTREG=XED_REG_R15W + + + +############################# + +# GPR8_R and GPR8_B are handled in separate files -- grep for them. + +###########################a + +xed_reg_enum_t CR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_CR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x2 | OUTREG=XED_REG_CR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_CR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_CR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_CR8 +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +# FIXME: not used +xed_reg_enum_t CR_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_CR0 +REXB=0 RM=0x1 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x2 | OUTREG=XED_REG_CR2 +REXB=0 RM=0x3 | OUTREG=XED_REG_CR3 +REXB=0 RM=0x4 | OUTREG=XED_REG_CR4 +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_CR8 +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR + +######################## + +xed_reg_enum_t DR_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_DR0 +REXR=0 REG=0x1 | OUTREG=XED_REG_DR1 +REXR=0 REG=0x2 | OUTREG=XED_REG_DR2 +REXR=0 REG=0x3 | OUTREG=XED_REG_DR3 +REXR=0 REG=0x4 | OUTREG=XED_REG_DR4 +REXR=0 REG=0x5 | OUTREG=XED_REG_DR5 +REXR=0 REG=0x6 | OUTREG=XED_REG_DR6 +REXR=0 REG=0x7 | OUTREG=XED_REG_DR7 +REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR enc +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +####################### + + +xed_reg_enum_t X87():: +RM=0x0 | OUTREG=XED_REG_ST0 +RM=0x1 | OUTREG=XED_REG_ST1 +RM=0x2 | OUTREG=XED_REG_ST2 +RM=0x3 | OUTREG=XED_REG_ST3 +RM=0x4 | OUTREG=XED_REG_ST4 +RM=0x5 | OUTREG=XED_REG_ST5 +RM=0x6 | OUTREG=XED_REG_ST6 +RM=0x7 | OUTREG=XED_REG_ST7 + +################### + +xed_reg_enum_t SEG():: +REG=0x0 | OUTREG=XED_REG_ES +REG=0x1 | OUTREG=XED_REG_CS +REG=0x2 | OUTREG=XED_REG_SS +REG=0x3 | OUTREG=XED_REG_DS +REG=0x4 | OUTREG=XED_REG_FS +REG=0x5 | OUTREG=XED_REG_GS +REG=0x6 | OUTREG=XED_REG_ERROR enc +REG=0x7 | OUTREG=XED_REG_ERROR + +# MOV to SEG cannot load CS +xed_reg_enum_t SEG_MOV():: +REG=0x0 | OUTREG=XED_REG_ES +REG=0x1 | OUTREG=XED_REG_ERROR +REG=0x2 | OUTREG=XED_REG_SS +REG=0x3 | OUTREG=XED_REG_DS +REG=0x4 | OUTREG=XED_REG_FS +REG=0x5 | OUTREG=XED_REG_GS +REG=0x6 | OUTREG=XED_REG_ERROR enc +REG=0x7 | OUTREG=XED_REG_ERROR + + +################################################### + +# We have two versions of FINAL_DSEG called FINAL_DSEG and +# FINAL_DSEG1. This is required because in the nonterminal function, I +# don't know if which memop (MEM0 or MEM1) the segment selector is +# being applied to. I set USING_DEFAULT_SEGMENT0 for MEM0 and +# USING_DEFAULT_SEGMENT1 for MEM1. + + +# These set USING_DEFAULT_SEGMENT0 + +xed_reg_enum_t FINAL_DSEG():: +mode16 | OUTREG=FINAL_DSEG_NOT64() +mode32 | OUTREG=FINAL_DSEG_NOT64() +mode64 | OUTREG=FINAL_DSEG_MODE64() + +xed_reg_enum_t FINAL_DSEG_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 enc # default data seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 # explicit ds seg +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=0 + +xed_reg_enum_t FINAL_DSEG_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + + +# These set USING_DEFAULT_SEGMENT1 + +xed_reg_enum_t FINAL_DSEG1():: +mode16 | OUTREG=FINAL_DSEG1_NOT64() +mode32 | OUTREG=FINAL_DSEG1_NOT64() +mode64 | OUTREG=FINAL_DSEG1_MODE64() + +xed_reg_enum_t FINAL_DSEG1_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 enc # default data seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 # explicit ds seg +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=0 + +xed_reg_enum_t FINAL_DSEG1_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + + + + + +################################################### + +# FINAL_ESEG is only called for STRING OPS and only specifies MEM0's SEG0. + +xed_reg_enum_t FINAL_ESEG():: +mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1 +mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + +xed_reg_enum_t FINAL_ESEG1():: +mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1 +mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + +# For synthesized stack operands (see generator.py) +xed_reg_enum_t FINAL_SSEG1():: +mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1 +mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 + +# For stack operands that cannot be overridden +xed_reg_enum_t FINAL_SSEG0():: +mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 +mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 +mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + +# This is only called for MODRM BYTEs and they only set MEM0's SEG0. + +xed_reg_enum_t FINAL_SSEG():: +mode16 | OUTREG=FINAL_SSEG_NOT64() +mode32 | OUTREG=FINAL_SSEG_NOT64() +mode64 | OUTREG=FINAL_SSEG_MODE64() + +xed_reg_enum_t FINAL_SSEG_NOT64():: +SEG_OVD=0 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 enc # default stack seg +SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 # explicit ss seg + +xed_reg_enum_t FINAL_SSEG_MODE64():: +SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc +SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 +SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0 +SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-eASZ.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-eASZ.txt +########################################################################### +# Call this after all legacy prefixes and before every instruction! + + +ASZ_NONTERM():: + +mode16 no67_prefix | eamode16 +mode16 67_prefix | eamode32 + +mode32 no67_prefix | eamode32 +mode32 67_prefix | eamode16 + +mode64 no67_prefix | eamode64 +mode64 67_prefix | eamode32 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-immediates.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-immediates.txt +########################################################################### +# Immediates and displacements +# FIXME: when there are multiple immediates, need separate storage +# FIXME: record the width of the immediate + +# FIXME: for encode we'll sometimes have to choose between SIMMv and +# SIMMz to pick a MOV, for 16 and 32b widths. +########################################################################################## +## 2-BYTE STORAGE UNITS +########################################################################################## + +ONE():: +mode16 | IMM_WIDTH=8 UIMM0=1 +mode32 | IMM_WIDTH=8 UIMM0=1 +mode64 | IMM_WIDTH=8 UIMM0=1 + + +UIMMv():: +EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 +EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 +EOSZ=3 UIMM0[i/64] | IMM_WIDTH=64 + +SIMMz():: +EOSZ=1 UIMM0[i/16] | IMM_WIDTH=16 IMM0SIGNED=1 +EOSZ=2 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1 +EOSZ=3 UIMM0[i/32] | IMM_WIDTH=32 IMM0SIGNED=1 + +SIMM8():: + UIMM0[i/8] | IMM_WIDTH=8 IMM0SIGNED=1 + +UIMM8():: + UIMM0[i/8] | IMM_WIDTH=8 + +# For ENTER. separate storage. +UIMM8_1():: + UIMM1[i/8] | true + +UIMM16():: + UIMM0[i/16] | IMM_WIDTH=16 + +UIMM32():: + UIMM0[i/32] | IMM_WIDTH=32 + +BRDISP8():: + DISP[d/8] |BRDISP_WIDTH=8 + +BRDISP32():: + DISP[d/32] | BRDISP_WIDTH=32 + +BRDISPz():: +EOSZ=1 DISP[d/16] | BRDISP_WIDTH=16 +EOSZ=2 DISP[d/32] | BRDISP_WIDTH=32 +EOSZ=3 DISP[d/32] | BRDISP_WIDTH=32 + + +MEMDISPv():: +EASZ=1 DISP[a/16] | DISP_WIDTH=16 +EASZ=2 DISP[a/32] | DISP_WIDTH=32 +EASZ=3 DISP[a/64] | DISP_WIDTH=64 + + +MEMDISP32():: +DISP[a/32] | DISP_WIDTH=32 + +MEMDISP16():: +DISP[a/16] | DISP_WIDTH=16 + +MEMDISP8():: +DISP[a/8] | DISP_WIDTH=8 + + +MEMDISP():: +NEED_MEMDISP=0 | DISP_WIDTH=0 +NEED_MEMDISP=8 DISP[a/8] | DISP_WIDTH=8 +NEED_MEMDISP=16 DISP[a/16] | DISP_WIDTH=16 +NEED_MEMDISP=32 DISP[a/32] | DISP_WIDTH=32 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-reg-tables-xmm.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_R():: +mode16 | OUTREG=XMM_R_32() +mode32 | OUTREG=XMM_R_32() +mode64 | OUTREG=XMM_R_64() + +xed_reg_enum_t XMM_R_32():: +REG=0x0 | OUTREG=XED_REG_XMM0 +REG=0x1 | OUTREG=XED_REG_XMM1 +REG=0x2 | OUTREG=XED_REG_XMM2 +REG=0x3 | OUTREG=XED_REG_XMM3 +REG=0x4 | OUTREG=XED_REG_XMM4 +REG=0x5 | OUTREG=XED_REG_XMM5 +REG=0x6 | OUTREG=XED_REG_XMM6 +REG=0x7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_R_64():: +REXR=0 REG=0x0 | OUTREG=XED_REG_XMM0 +REXR=0 REG=0x1 | OUTREG=XED_REG_XMM1 +REXR=0 REG=0x2 | OUTREG=XED_REG_XMM2 +REXR=0 REG=0x3 | OUTREG=XED_REG_XMM3 +REXR=0 REG=0x4 | OUTREG=XED_REG_XMM4 +REXR=0 REG=0x5 | OUTREG=XED_REG_XMM5 +REXR=0 REG=0x6 | OUTREG=XED_REG_XMM6 +REXR=0 REG=0x7 | OUTREG=XED_REG_XMM7 +REXR=1 REG=0x0 | OUTREG=XED_REG_XMM8 +REXR=1 REG=0x1 | OUTREG=XED_REG_XMM9 +REXR=1 REG=0x2 | OUTREG=XED_REG_XMM10 +REXR=1 REG=0x3 | OUTREG=XED_REG_XMM11 +REXR=1 REG=0x4 | OUTREG=XED_REG_XMM12 +REXR=1 REG=0x5 | OUTREG=XED_REG_XMM13 +REXR=1 REG=0x6 | OUTREG=XED_REG_XMM14 +REXR=1 REG=0x7 | OUTREG=XED_REG_XMM15 + + +xed_reg_enum_t XMM_B():: +mode16 | OUTREG=XMM_B_32() +mode32 | OUTREG=XMM_B_32() +mode64 | OUTREG=XMM_B_64() + +xed_reg_enum_t XMM_B_32():: +RM=0x0 | OUTREG=XED_REG_XMM0 +RM=0x1 | OUTREG=XED_REG_XMM1 +RM=0x2 | OUTREG=XED_REG_XMM2 +RM=0x3 | OUTREG=XED_REG_XMM3 +RM=0x4 | OUTREG=XED_REG_XMM4 +RM=0x5 | OUTREG=XED_REG_XMM5 +RM=0x6 | OUTREG=XED_REG_XMM6 +RM=0x7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_B_64():: +REXB=0 RM=0x0 | OUTREG=XED_REG_XMM0 +REXB=0 RM=0x1 | OUTREG=XED_REG_XMM1 +REXB=0 RM=0x2 | OUTREG=XED_REG_XMM2 +REXB=0 RM=0x3 | OUTREG=XED_REG_XMM3 +REXB=0 RM=0x4 | OUTREG=XED_REG_XMM4 +REXB=0 RM=0x5 | OUTREG=XED_REG_XMM5 +REXB=0 RM=0x6 | OUTREG=XED_REG_XMM6 +REXB=0 RM=0x7 | OUTREG=XED_REG_XMM7 +REXB=1 RM=0x0 | OUTREG=XED_REG_XMM8 +REXB=1 RM=0x1 | OUTREG=XED_REG_XMM9 +REXB=1 RM=0x2 | OUTREG=XED_REG_XMM10 +REXB=1 RM=0x3 | OUTREG=XED_REG_XMM11 +REXB=1 RM=0x4 | OUTREG=XED_REG_XMM12 +REXB=1 RM=0x5 | OUTREG=XED_REG_XMM13 +REXB=1 RM=0x6 | OUTREG=XED_REG_XMM14 +REXB=1 RM=0x7 | OUTREG=XED_REG_XMM15 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-reg-tables.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t BND_R():: +REXR=0 REG=0x0 | OUTREG=XED_REG_BND0 +REXR=0 REG=0x1 | OUTREG=XED_REG_BND1 +REXR=0 REG=0x2 | OUTREG=XED_REG_BND2 +REXR=0 REG=0x3 | OUTREG=XED_REG_BND3 +REXR=0 REG=0x4 | OUTREG=XED_REG_ERROR enc +REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR +REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR + +xed_reg_enum_t BND_B():: +REXB=0 RM=0x0 | OUTREG=XED_REG_BND0 +REXB=0 RM=0x1 | OUTREG=XED_REG_BND1 +REXB=0 RM=0x2 | OUTREG=XED_REG_BND2 +REXB=0 RM=0x3 | OUTREG=XED_REG_BND3 +REXB=0 RM=0x4 | OUTREG=XED_REG_ERROR enc +REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x0 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR +REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/asize-reg-table.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t A_GPR_R():: +REXR=0 REG=0x0 | OUTREG=ArAX() +REXR=0 REG=0x1 | OUTREG=ArCX() +REXR=0 REG=0x2 | OUTREG=ArDX() +REXR=0 REG=0x3 | OUTREG=ArBX() +REXR=0 REG=0x4 | OUTREG=ArSP() +REXR=0 REG=0x5 | OUTREG=ArBP() +REXR=0 REG=0x6 | OUTREG=ArSI() +REXR=0 REG=0x7 | OUTREG=ArDI() +REXR=1 REG=0x0 | OUTREG=Ar8() +REXR=1 REG=0x1 | OUTREG=Ar9() +REXR=1 REG=0x2 | OUTREG=Ar10() +REXR=1 REG=0x3 | OUTREG=Ar11() +REXR=1 REG=0x4 | OUTREG=Ar12() +REXR=1 REG=0x5 | OUTREG=Ar13() +REXR=1 REG=0x6 | OUTREG=Ar14() +REXR=1 REG=0x7 | OUTREG=Ar15() + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/asize-rm-table.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t A_GPR_B():: +REXB=0 RM=0x0 | OUTREG=ArAX() +REXB=0 RM=0x1 | OUTREG=ArCX() +REXB=0 RM=0x2 | OUTREG=ArDX() +REXB=0 RM=0x3 | OUTREG=ArBX() +REXB=0 RM=0x4 | OUTREG=ArSP() +REXB=0 RM=0x5 | OUTREG=ArBP() +REXB=0 RM=0x6 | OUTREG=ArSI() +REXB=0 RM=0x7 | OUTREG=ArDI() +REXB=1 RM=0x0 | OUTREG=Ar8() +REXB=1 RM=0x1 | OUTREG=Ar9() +REXB=1 RM=0x2 | OUTREG=Ar10() +REXB=1 RM=0x3 | OUTREG=Ar11() +REXB=1 RM=0x4 | OUTREG=Ar12() +REXB=1 RM=0x5 | OUTREG=Ar13() +REXB=1 RM=0x6 | OUTREG=Ar14() +REXB=1 RM=0x7 | OUTREG=Ar15() + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-reg-table.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t XMM_SE():: +mode16 | OUTREG=XMM_SE32() +mode32 | OUTREG=XMM_SE32() +mode64 | OUTREG=XMM_SE64() + +xed_reg_enum_t XMM_SE64():: +ESRC=0x0 | OUTREG=XED_REG_XMM0 +ESRC=0x1 | OUTREG=XED_REG_XMM1 +ESRC=0x2 | OUTREG=XED_REG_XMM2 +ESRC=0x3 | OUTREG=XED_REG_XMM3 +ESRC=0x4 | OUTREG=XED_REG_XMM4 +ESRC=0x5 | OUTREG=XED_REG_XMM5 +ESRC=0x6 | OUTREG=XED_REG_XMM6 +ESRC=0x7 | OUTREG=XED_REG_XMM7 +ESRC=0x8 | OUTREG=XED_REG_XMM8 +ESRC=0x9 | OUTREG=XED_REG_XMM9 +ESRC=0xA | OUTREG=XED_REG_XMM10 +ESRC=0xB | OUTREG=XED_REG_XMM11 +ESRC=0xC | OUTREG=XED_REG_XMM12 +ESRC=0xD | OUTREG=XED_REG_XMM13 +ESRC=0xE | OUTREG=XED_REG_XMM14 +ESRC=0xF | OUTREG=XED_REG_XMM15 + +xed_reg_enum_t XMM_SE32():: +ESRC=0 | OUTREG=XED_REG_XMM0 enc +ESRC=1 | OUTREG=XED_REG_XMM1 enc +ESRC=2 | OUTREG=XED_REG_XMM2 enc +ESRC=3 | OUTREG=XED_REG_XMM3 enc +ESRC=4 | OUTREG=XED_REG_XMM4 enc +ESRC=5 | OUTREG=XED_REG_XMM5 enc +ESRC=6 | OUTREG=XED_REG_XMM6 enc +ESRC=7 | OUTREG=XED_REG_XMM7 enc +# ignoring the high bit in non64b modes. Really just 0...7 +ESRC=0x8 | OUTREG=XED_REG_XMM0 +ESRC=0x9 | OUTREG=XED_REG_XMM1 +ESRC=0xA | OUTREG=XED_REG_XMM2 +ESRC=0xB | OUTREG=XED_REG_XMM3 +ESRC=0xC | OUTREG=XED_REG_XMM4 +ESRC=0xD | OUTREG=XED_REG_XMM5 +ESRC=0xE | OUTREG=XED_REG_XMM6 +ESRC=0xF | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t YMM_SE():: +mode16 | OUTREG=YMM_SE32() +mode32 | OUTREG=YMM_SE32() +mode64 | OUTREG=YMM_SE64() + +xed_reg_enum_t YMM_SE64():: +ESRC=0x0 | OUTREG=XED_REG_YMM0 +ESRC=0x1 | OUTREG=XED_REG_YMM1 +ESRC=0x2 | OUTREG=XED_REG_YMM2 +ESRC=0x3 | OUTREG=XED_REG_YMM3 +ESRC=0x4 | OUTREG=XED_REG_YMM4 +ESRC=0x5 | OUTREG=XED_REG_YMM5 +ESRC=0x6 | OUTREG=XED_REG_YMM6 +ESRC=0x7 | OUTREG=XED_REG_YMM7 +ESRC=0x8 | OUTREG=XED_REG_YMM8 +ESRC=0x9 | OUTREG=XED_REG_YMM9 +ESRC=0xA | OUTREG=XED_REG_YMM10 +ESRC=0xB | OUTREG=XED_REG_YMM11 +ESRC=0xC | OUTREG=XED_REG_YMM12 +ESRC=0xD | OUTREG=XED_REG_YMM13 +ESRC=0xE | OUTREG=XED_REG_YMM14 +ESRC=0xF | OUTREG=XED_REG_YMM15 + +xed_reg_enum_t YMM_SE32():: +ESRC=0 | OUTREG=XED_REG_YMM0 enc +ESRC=1 | OUTREG=XED_REG_YMM1 enc +ESRC=2 | OUTREG=XED_REG_YMM2 enc +ESRC=3 | OUTREG=XED_REG_YMM3 enc +ESRC=4 | OUTREG=XED_REG_YMM4 enc +ESRC=5 | OUTREG=XED_REG_YMM5 enc +ESRC=6 | OUTREG=XED_REG_YMM6 enc +ESRC=7 | OUTREG=XED_REG_YMM7 enc +# ignoring the high bit in non64b modes. Really just 0...7 +ESRC=0x8 | OUTREG=XED_REG_YMM0 +ESRC=0x9 | OUTREG=XED_REG_YMM1 +ESRC=0xA | OUTREG=XED_REG_YMM2 +ESRC=0xB | OUTREG=XED_REG_YMM3 +ESRC=0xC | OUTREG=XED_REG_YMM4 +ESRC=0xD | OUTREG=XED_REG_YMM5 +ESRC=0xE | OUTREG=XED_REG_YMM6 +ESRC=0xF | OUTREG=XED_REG_YMM7 + + +xed_reg_enum_t XMM_N():: +mode16 | OUTREG=XMM_N_32(): +mode32 | OUTREG=XMM_N_32(): +mode64 | OUTREG=XMM_N_64(): + +xed_reg_enum_t XMM_N_32():: +VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_N_64():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7 +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15 + +xed_reg_enum_t YMM_N():: +mode16 | OUTREG=YMM_N_32(): +mode32 | OUTREG=YMM_N_32(): +mode64 | OUTREG=YMM_N_64(): + +xed_reg_enum_t YMM_N_32():: +VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST210=0 | OUTREG=XED_REG_YMM7 +xed_reg_enum_t YMM_N_64():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7 +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15 + +xed_reg_enum_t YMM_R():: +mode16 | OUTREG=YMM_R_32(): +mode32 | OUTREG=YMM_R_32(): +mode64 | OUTREG=YMM_R_64(): + + +xed_reg_enum_t YMM_R_32():: +REG=0 | OUTREG=XED_REG_YMM0 +REG=1 | OUTREG=XED_REG_YMM1 +REG=2 | OUTREG=XED_REG_YMM2 +REG=3 | OUTREG=XED_REG_YMM3 +REG=4 | OUTREG=XED_REG_YMM4 +REG=5 | OUTREG=XED_REG_YMM5 +REG=6 | OUTREG=XED_REG_YMM6 +REG=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_R_64():: +REXR=0 REG=0 | OUTREG=XED_REG_YMM0 +REXR=0 REG=1 | OUTREG=XED_REG_YMM1 +REXR=0 REG=2 | OUTREG=XED_REG_YMM2 +REXR=0 REG=3 | OUTREG=XED_REG_YMM3 +REXR=0 REG=4 | OUTREG=XED_REG_YMM4 +REXR=0 REG=5 | OUTREG=XED_REG_YMM5 +REXR=0 REG=6 | OUTREG=XED_REG_YMM6 +REXR=0 REG=7 | OUTREG=XED_REG_YMM7 +REXR=1 REG=0 | OUTREG=XED_REG_YMM8 +REXR=1 REG=1 | OUTREG=XED_REG_YMM9 +REXR=1 REG=2 | OUTREG=XED_REG_YMM10 +REXR=1 REG=3 | OUTREG=XED_REG_YMM11 +REXR=1 REG=4 | OUTREG=XED_REG_YMM12 +REXR=1 REG=5 | OUTREG=XED_REG_YMM13 +REXR=1 REG=6 | OUTREG=XED_REG_YMM14 +REXR=1 REG=7 | OUTREG=XED_REG_YMM15 + + +xed_reg_enum_t YMM_B():: +mode16 | OUTREG=YMM_B_32(): +mode32 | OUTREG=YMM_B_32(): +mode64 | OUTREG=YMM_B_64(): + + +xed_reg_enum_t YMM_B_32():: +RM=0 | OUTREG=XED_REG_YMM0 +RM=1 | OUTREG=XED_REG_YMM1 +RM=2 | OUTREG=XED_REG_YMM2 +RM=3 | OUTREG=XED_REG_YMM3 +RM=4 | OUTREG=XED_REG_YMM4 +RM=5 | OUTREG=XED_REG_YMM5 +RM=6 | OUTREG=XED_REG_YMM6 +RM=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_B_64():: +REXB=0 RM=0 | OUTREG=XED_REG_YMM0 +REXB=0 RM=1 | OUTREG=XED_REG_YMM1 +REXB=0 RM=2 | OUTREG=XED_REG_YMM2 +REXB=0 RM=3 | OUTREG=XED_REG_YMM3 +REXB=0 RM=4 | OUTREG=XED_REG_YMM4 +REXB=0 RM=5 | OUTREG=XED_REG_YMM5 +REXB=0 RM=6 | OUTREG=XED_REG_YMM6 +REXB=0 RM=7 | OUTREG=XED_REG_YMM7 +REXB=1 RM=0 | OUTREG=XED_REG_YMM8 +REXB=1 RM=1 | OUTREG=XED_REG_YMM9 +REXB=1 RM=2 | OUTREG=XED_REG_YMM10 +REXB=1 RM=3 | OUTREG=XED_REG_YMM11 +REXB=1 RM=4 | OUTREG=XED_REG_YMM12 +REXB=1 RM=5 | OUTREG=XED_REG_YMM13 +REXB=1 RM=6 | OUTREG=XED_REG_YMM14 +REXB=1 RM=7 | OUTREG=XED_REG_YMM15 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/hsw-reg-table.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# VGPRy_N, VGPRy_B, and VGPRy_R are used by AMD XOP. +# Only but the lower level stuff is used by HSW NI. + +xed_reg_enum_t VGPRy_R():: +EOSZ=1 | OUTREG=VGPR32_R() +EOSZ=2 | OUTREG=VGPR32_R() +EOSZ=3 | OUTREG=VGPR64_R() + +xed_reg_enum_t VGPRy_B():: +EOSZ=1 | OUTREG=VGPR32_B() +EOSZ=2 | OUTREG=VGPR32_B() +EOSZ=3 | OUTREG=VGPR64_B() + +xed_reg_enum_t VGPRy_N():: +EOSZ=1 | OUTREG=VGPR32_N() +EOSZ=2 | OUTREG=VGPR32_N() +EOSZ=3 | OUTREG=VGPR64_N() + +xed_reg_enum_t VGPR32_N():: +mode16 | OUTREG=VGPR32_N_32() +mode32 | OUTREG=VGPR32_N_32() +mode64 | OUTREG=VGPR32_N_64() + +xed_reg_enum_t VGPR32_B():: +mode16 | OUTREG=VGPR32_B_32() +mode32 | OUTREG=VGPR32_B_32() +mode64 | OUTREG=VGPR32_B_64() + +xed_reg_enum_t VGPR32_R():: +mode16 | OUTREG=VGPR32_R_32() +mode32 | OUTREG=VGPR32_R_32() +mode64 | OUTREG=VGPR32_R_64() + + + + + + +xed_reg_enum_t VGPR32_N_32():: # IGNORES UPPER BIT (VEXDEST3) IN 32b mode +VEXDEST210=7 | OUTREG=XED_REG_EAX +VEXDEST210=6 | OUTREG=XED_REG_ECX +VEXDEST210=5 | OUTREG=XED_REG_EDX +VEXDEST210=4 | OUTREG=XED_REG_EBX +VEXDEST210=3 | OUTREG=XED_REG_ESP +VEXDEST210=2 | OUTREG=XED_REG_EBP +VEXDEST210=1 | OUTREG=XED_REG_ESI +VEXDEST210=0 | OUTREG=XED_REG_EDI + +xed_reg_enum_t VGPR32_N_64():: # IGNORES UPPER BIT (VEXDEST3) IN 32b mode +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_EAX +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ECX +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_EDX +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_EBX +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ESP +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_EBP +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ESI +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_EDI +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8D +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9D +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10D +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11D +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12D +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13D +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14D +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15D + + +xed_reg_enum_t VGPR64_N():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_RAX +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_RCX +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_RDX +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_RBX +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_RSP +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_RBP +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_RSI +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_RDI +VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8 +VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9 +VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10 +VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11 +VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12 +VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13 +VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14 +VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15 + + +########### + +xed_reg_enum_t VGPR32_R_32():: # IGNORES (REXR) IN 32b mode +REG=0 | OUTREG=XED_REG_EAX +REG=1 | OUTREG=XED_REG_ECX +REG=2 | OUTREG=XED_REG_EDX +REG=3 | OUTREG=XED_REG_EBX +REG=4 | OUTREG=XED_REG_ESP +REG=5 | OUTREG=XED_REG_EBP +REG=6 | OUTREG=XED_REG_ESI +REG=7 | OUTREG=XED_REG_EDI + + +xed_reg_enum_t VGPR32_R_64():: +REXR=0 REG=0 | OUTREG=XED_REG_EAX +REXR=0 REG=1 | OUTREG=XED_REG_ECX +REXR=0 REG=2 | OUTREG=XED_REG_EDX +REXR=0 REG=3 | OUTREG=XED_REG_EBX +REXR=0 REG=4 | OUTREG=XED_REG_ESP +REXR=0 REG=5 | OUTREG=XED_REG_EBP +REXR=0 REG=6 | OUTREG=XED_REG_ESI +REXR=0 REG=7 | OUTREG=XED_REG_EDI +REXR=1 REG=0 | OUTREG=XED_REG_R8D +REXR=1 REG=1 | OUTREG=XED_REG_R9D +REXR=1 REG=2 | OUTREG=XED_REG_R10D +REXR=1 REG=3 | OUTREG=XED_REG_R11D +REXR=1 REG=4 | OUTREG=XED_REG_R12D +REXR=1 REG=5 | OUTREG=XED_REG_R13D +REXR=1 REG=6 | OUTREG=XED_REG_R14D +REXR=1 REG=7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t VGPR64_R():: +REXR=0 REG=0 | OUTREG=XED_REG_RAX +REXR=0 REG=1 | OUTREG=XED_REG_RCX +REXR=0 REG=2 | OUTREG=XED_REG_RDX +REXR=0 REG=3 | OUTREG=XED_REG_RBX +REXR=0 REG=4 | OUTREG=XED_REG_RSP +REXR=0 REG=5 | OUTREG=XED_REG_RBP +REXR=0 REG=6 | OUTREG=XED_REG_RSI +REXR=0 REG=7 | OUTREG=XED_REG_RDI +REXR=1 REG=0 | OUTREG=XED_REG_R8 +REXR=1 REG=1 | OUTREG=XED_REG_R9 +REXR=1 REG=2 | OUTREG=XED_REG_R10 +REXR=1 REG=3 | OUTREG=XED_REG_R11 +REXR=1 REG=4 | OUTREG=XED_REG_R12 +REXR=1 REG=5 | OUTREG=XED_REG_R13 +REXR=1 REG=6 | OUTREG=XED_REG_R14 +REXR=1 REG=7 | OUTREG=XED_REG_R15 + + +################### + +xed_reg_enum_t VGPR32_B_32():: # IGNORES (REXB) IN 32b mode +RM=0 | OUTREG=XED_REG_EAX +RM=1 | OUTREG=XED_REG_ECX +RM=2 | OUTREG=XED_REG_EDX +RM=3 | OUTREG=XED_REG_EBX +RM=4 | OUTREG=XED_REG_ESP +RM=5 | OUTREG=XED_REG_EBP +RM=6 | OUTREG=XED_REG_ESI +RM=7 | OUTREG=XED_REG_EDI + + +xed_reg_enum_t VGPR32_B_64():: +REXB=0 RM=0 | OUTREG=XED_REG_EAX +REXB=0 RM=1 | OUTREG=XED_REG_ECX +REXB=0 RM=2 | OUTREG=XED_REG_EDX +REXB=0 RM=3 | OUTREG=XED_REG_EBX +REXB=0 RM=4 | OUTREG=XED_REG_ESP +REXB=0 RM=5 | OUTREG=XED_REG_EBP +REXB=0 RM=6 | OUTREG=XED_REG_ESI +REXB=0 RM=7 | OUTREG=XED_REG_EDI +REXB=1 RM=0 | OUTREG=XED_REG_R8D +REXB=1 RM=1 | OUTREG=XED_REG_R9D +REXB=1 RM=2 | OUTREG=XED_REG_R10D +REXB=1 RM=3 | OUTREG=XED_REG_R11D +REXB=1 RM=4 | OUTREG=XED_REG_R12D +REXB=1 RM=5 | OUTREG=XED_REG_R13D +REXB=1 RM=6 | OUTREG=XED_REG_R14D +REXB=1 RM=7 | OUTREG=XED_REG_R15D + +xed_reg_enum_t VGPR64_B():: +REXB=0 RM=0 | OUTREG=XED_REG_RAX +REXB=0 RM=1 | OUTREG=XED_REG_RCX +REXB=0 RM=2 | OUTREG=XED_REG_RDX +REXB=0 RM=3 | OUTREG=XED_REG_RBX +REXB=0 RM=4 | OUTREG=XED_REG_RSP +REXB=0 RM=5 | OUTREG=XED_REG_RBP +REXB=0 RM=6 | OUTREG=XED_REG_RSI +REXB=0 RM=7 | OUTREG=XED_REG_RDI +REXB=1 RM=0 | OUTREG=XED_REG_R8 +REXB=1 RM=1 | OUTREG=XED_REG_R9 +REXB=1 RM=2 | OUTREG=XED_REG_R10 +REXB=1 RM=3 | OUTREG=XED_REG_R11 +REXB=1 RM=4 | OUTREG=XED_REG_R12 +REXB=1 RM=5 | OUTREG=XED_REG_R13 +REXB=1 RM=6 | OUTREG=XED_REG_R14 +REXB=1 RM=7 | OUTREG=XED_REG_R15 + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-table-mask.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# FIXME: the rest of this file is common w/KNC. Split it out to avoid +# duplication + +xed_reg_enum_t MASK1():: +MASK=0x0 | OUTREG=XED_REG_K0 +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +xed_reg_enum_t MASKNOT0():: +MASK=0x0 | OUTREG=XED_REG_ERROR +MASK=0x1 | OUTREG=XED_REG_K1 +MASK=0x2 | OUTREG=XED_REG_K2 +MASK=0x3 | OUTREG=XED_REG_K3 +MASK=0x4 | OUTREG=XED_REG_K4 +MASK=0x5 | OUTREG=XED_REG_K5 +MASK=0x6 | OUTREG=XED_REG_K6 +MASK=0x7 | OUTREG=XED_REG_K7 + +# used for compares in EVEX +xed_reg_enum_t MASK_R():: +REXRR=0 REXR=0 REG=0x0 | OUTREG=XED_REG_K0 +REXRR=0 REXR=0 REG=0x1 | OUTREG=XED_REG_K1 +REXRR=0 REXR=0 REG=0x2 | OUTREG=XED_REG_K2 +REXRR=0 REXR=0 REG=0x3 | OUTREG=XED_REG_K3 +REXRR=0 REXR=0 REG=0x4 | OUTREG=XED_REG_K4 +REXRR=0 REXR=0 REG=0x5 | OUTREG=XED_REG_K5 +REXRR=0 REXR=0 REG=0x6 | OUTREG=XED_REG_K6 +REXRR=0 REXR=0 REG=0x7 | OUTREG=XED_REG_K7 + +# MASK_B is used by VEX and EVEX encodings. SDM (rev 062) states in +# EVEX, EVEX.B (REXB) is ignored. SDM does not (yet) say what happens +# on VEX.B but assuming it is similar. + +xed_reg_enum_t MASK_B():: +RM=0x0 | OUTREG=XED_REG_K0 +RM=0x1 | OUTREG=XED_REG_K1 +RM=0x2 | OUTREG=XED_REG_K2 +RM=0x3 | OUTREG=XED_REG_K3 +RM=0x4 | OUTREG=XED_REG_K4 +RM=0x5 | OUTREG=XED_REG_K5 +RM=0x6 | OUTREG=XED_REG_K6 +RM=0x7 | OUTREG=XED_REG_K7 + +# only used in VEX space for K-mask ops +# stored inverted +xed_reg_enum_t MASK_N():: +mode64 | OUTREG=MASK_N64() +mode32 | OUTREG=MASK_N32() +mode16 | OUTREG=MASK_N32() + +xed_reg_enum_t MASK_N64():: +VEXDEST3=1 VEXDEST210=0x0 | OUTREG=XED_REG_K7 +VEXDEST3=1 VEXDEST210=0x1 | OUTREG=XED_REG_K6 +VEXDEST3=1 VEXDEST210=0x2 | OUTREG=XED_REG_K5 +VEXDEST3=1 VEXDEST210=0x3 | OUTREG=XED_REG_K4 +VEXDEST3=1 VEXDEST210=0x4 | OUTREG=XED_REG_K3 +VEXDEST3=1 VEXDEST210=0x5 | OUTREG=XED_REG_K2 +VEXDEST3=1 VEXDEST210=0x6 | OUTREG=XED_REG_K1 +VEXDEST3=1 VEXDEST210=0x7 | OUTREG=XED_REG_K0 + +xed_reg_enum_t MASK_N32():: +VEXDEST210=0x0 | OUTREG=XED_REG_K7 +VEXDEST210=0x1 | OUTREG=XED_REG_K6 +VEXDEST210=0x2 | OUTREG=XED_REG_K5 +VEXDEST210=0x3 | OUTREG=XED_REG_K4 +VEXDEST210=0x4 | OUTREG=XED_REG_K3 +VEXDEST210=0x5 | OUTREG=XED_REG_K2 +VEXDEST210=0x6 | OUTREG=XED_REG_K1 +VEXDEST210=0x7 | OUTREG=XED_REG_K0 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-r3.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_R3():: +mode16 | OUTREG=XMM_R3_32() +mode32 | OUTREG=XMM_R3_32() +mode64 | OUTREG=XMM_R3_64() + +xed_reg_enum_t XMM_R3_32():: +REG=0 | OUTREG=XED_REG_XMM0 +REG=1 | OUTREG=XED_REG_XMM1 +REG=2 | OUTREG=XED_REG_XMM2 +REG=3 | OUTREG=XED_REG_XMM3 +REG=4 | OUTREG=XED_REG_XMM4 +REG=5 | OUTREG=XED_REG_XMM5 +REG=6 | OUTREG=XED_REG_XMM6 +REG=7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7 + +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31 + + +xed_reg_enum_t YMM_R3():: +mode16 | OUTREG=YMM_R3_32() +mode32 | OUTREG=YMM_R3_32() +mode64 | OUTREG=YMM_R3_64() + +xed_reg_enum_t YMM_R3_32():: +REG=0 | OUTREG=XED_REG_YMM0 +REG=1 | OUTREG=XED_REG_YMM1 +REG=2 | OUTREG=XED_REG_YMM2 +REG=3 | OUTREG=XED_REG_YMM3 +REG=4 | OUTREG=XED_REG_YMM4 +REG=5 | OUTREG=XED_REG_YMM5 +REG=6 | OUTREG=XED_REG_YMM6 +REG=7 | OUTREG=XED_REG_YMM7 +xed_reg_enum_t YMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31 + + + +xed_reg_enum_t ZMM_R3():: +mode16 | OUTREG=ZMM_R3_32() +mode32 | OUTREG=ZMM_R3_32() +mode64 | OUTREG=ZMM_R3_64() + +xed_reg_enum_t ZMM_R3_32():: +REG=0 | OUTREG=XED_REG_ZMM0 +REG=1 | OUTREG=XED_REG_ZMM1 +REG=2 | OUTREG=XED_REG_ZMM2 +REG=3 | OUTREG=XED_REG_ZMM3 +REG=4 | OUTREG=XED_REG_ZMM4 +REG=5 | OUTREG=XED_REG_ZMM5 +REG=6 | OUTREG=XED_REG_ZMM6 +REG=7 | OUTREG=XED_REG_ZMM7 + +xed_reg_enum_t ZMM_R3_64():: +REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0 +REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1 +REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2 +REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3 +REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4 +REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5 +REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6 +REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7 +REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8 +REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9 +REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10 +REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11 +REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12 +REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13 +REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14 +REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15 + +REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16 +REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17 +REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18 +REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19 +REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20 +REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21 +REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22 +REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23 +REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24 +REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25 +REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26 +REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27 +REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28 +REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29 +REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30 +REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-b3.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_B3():: +mode16 | OUTREG=XMM_B3_32() +mode32 | OUTREG=XMM_B3_32() +mode64 | OUTREG=XMM_B3_64() + +xed_reg_enum_t XMM_B3_32():: +RM=0 | OUTREG=XED_REG_XMM0 +RM=1 | OUTREG=XED_REG_XMM1 +RM=2 | OUTREG=XED_REG_XMM2 +RM=3 | OUTREG=XED_REG_XMM3 +RM=4 | OUTREG=XED_REG_XMM4 +RM=5 | OUTREG=XED_REG_XMM5 +RM=6 | OUTREG=XED_REG_XMM6 +RM=7 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_XMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_XMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_XMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_XMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_XMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_XMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_XMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_XMM7 + +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_XMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_XMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_XMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_XMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_XMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_XMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_XMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_XMM15 + +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_XMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_XMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_XMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_XMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_XMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_XMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_XMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_XMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_XMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_XMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_XMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_XMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_XMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_XMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_XMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_XMM31 + + + +xed_reg_enum_t YMM_B3():: +mode16 | OUTREG=YMM_B3_32() +mode32 | OUTREG=YMM_B3_32() +mode64 | OUTREG=YMM_B3_64() + +xed_reg_enum_t YMM_B3_32():: +RM=0 | OUTREG=XED_REG_YMM0 +RM=1 | OUTREG=XED_REG_YMM1 +RM=2 | OUTREG=XED_REG_YMM2 +RM=3 | OUTREG=XED_REG_YMM3 +RM=4 | OUTREG=XED_REG_YMM4 +RM=5 | OUTREG=XED_REG_YMM5 +RM=6 | OUTREG=XED_REG_YMM6 +RM=7 | OUTREG=XED_REG_YMM7 + +xed_reg_enum_t YMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_YMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_YMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_YMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_YMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_YMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_YMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_YMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_YMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_YMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_YMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_YMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_YMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_YMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_YMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_YMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_YMM15 + +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_YMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_YMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_YMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_YMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_YMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_YMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_YMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_YMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_YMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_YMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_YMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_YMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_YMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_YMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_YMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_YMM31 + + + +xed_reg_enum_t ZMM_B3():: +mode16 | OUTREG=ZMM_B3_32() +mode32 | OUTREG=ZMM_B3_32() +mode64 | OUTREG=ZMM_B3_64() + +xed_reg_enum_t ZMM_B3_32():: +RM=0 | OUTREG=XED_REG_ZMM0 +RM=1 | OUTREG=XED_REG_ZMM1 +RM=2 | OUTREG=XED_REG_ZMM2 +RM=3 | OUTREG=XED_REG_ZMM3 +RM=4 | OUTREG=XED_REG_ZMM4 +RM=5 | OUTREG=XED_REG_ZMM5 +RM=6 | OUTREG=XED_REG_ZMM6 +RM=7 | OUTREG=XED_REG_ZMM7 + +xed_reg_enum_t ZMM_B3_64():: +REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0 +REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1 +REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2 +REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3 +REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4 +REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5 +REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6 +REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7 +REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8 +REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9 +REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10 +REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11 +REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12 +REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13 +REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14 +REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15 +REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16 +REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17 +REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18 +REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19 +REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20 +REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21 +REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22 +REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23 +REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24 +REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25 +REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26 +REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27 +REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28 +REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29 +REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30 +REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-n3.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t XMM_N3():: +mode16 | OUTREG=XMM_N3_32() +mode32 | OUTREG=XMM_N3_32() +mode64 | OUTREG=XMM_N3_64() + +xed_reg_enum_t XMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +xed_reg_enum_t XMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7 + +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31 + + +xed_reg_enum_t YMM_N3():: +mode16 | OUTREG=YMM_N3_32() +mode32 | OUTREG=YMM_N3_32() +mode64 | OUTREG=YMM_N3_64() + +xed_reg_enum_t YMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST210=0 | OUTREG=XED_REG_YMM7 + + +xed_reg_enum_t YMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31 + + +xed_reg_enum_t ZMM_N3():: +mode16 | OUTREG=ZMM_N3_32() +mode32 | OUTREG=ZMM_N3_32() +mode64 | OUTREG=ZMM_N3_64() + + +xed_reg_enum_t ZMM_N3_32():: +VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST210=0 | OUTREG=XED_REG_ZMM7 + + +xed_reg_enum_t ZMM_N3_64():: +VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6 +VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14 +VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15 + +VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22 +VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30 +VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-reg-tables.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +xed_reg_enum_t TMM_R():: +REXR=0 REG=0 | OUTREG=XED_REG_TMM0 +REXR=0 REG=1 | OUTREG=XED_REG_TMM1 +REXR=0 REG=2 | OUTREG=XED_REG_TMM2 +REXR=0 REG=3 | OUTREG=XED_REG_TMM3 +REXR=0 REG=4 | OUTREG=XED_REG_TMM4 +REXR=0 REG=5 | OUTREG=XED_REG_TMM5 +REXR=0 REG=6 | OUTREG=XED_REG_TMM6 +REXR=0 REG=7 | OUTREG=XED_REG_TMM7 + +xed_reg_enum_t TMM_B():: +REXB=0 RM=0 | OUTREG=XED_REG_TMM0 +REXB=0 RM=1 | OUTREG=XED_REG_TMM1 +REXB=0 RM=2 | OUTREG=XED_REG_TMM2 +REXB=0 RM=3 | OUTREG=XED_REG_TMM3 +REXB=0 RM=4 | OUTREG=XED_REG_TMM4 +REXB=0 RM=5 | OUTREG=XED_REG_TMM5 +REXB=0 RM=6 | OUTREG=XED_REG_TMM6 +REXB=0 RM=7 | OUTREG=XED_REG_TMM7 + + +xed_reg_enum_t TMM_N():: +VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_TMM0 +VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_TMM1 +VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_TMM2 +VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_TMM3 +VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_TMM4 +VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_TMM5 +VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_TMM6 +VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_TMM7 diff --git a/CodeVirtualizer/build/obj/dgen/all-enc-instructions.txt b/CodeVirtualizer/build/obj/dgen/all-enc-instructions.txt new file mode 100644 index 0000000..f1940cf --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-enc-instructions.txt @@ -0,0 +1,86875 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} + +{ +ICLASS : FCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP + +COMMENT : UNDOC DC D0..D7 is an undocumented alaias (see sandpile.org) +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FCOM_ST0_X87_DCD0 +} + + +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} + +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +COMMENT : UNDOC ALIASES +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FCOMP_ST0_X87_DCD1 + +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FCOMP_ST0_X87_DED0 +} + + +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem80real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP + +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP + +COMMENT : UNDOC ALIASES +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FSTP_X87_ST0_DFD0 + +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +IFORM : FSTP_X87_ST0_DFD1 +} + +{ +ICLASS : FSTPNCE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +COMMENT : UNDOC ALIASES - empty top of stack behavior differs from FSTP. +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} + + + +{ +ICLASS : FLDENV +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +# EOSZ=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:r:mem14 REG0=XED_REG_X87STATUS:w:SUPP +# EOSZ!=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:mem28 REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDCW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mem16 REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNSTENV +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +# EOSZ=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:w:mem14 REG0=XED_REG_X87STATUS:w:SUPP +# EOSZ!=1 +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:w:mem28 REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNSTCW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87CONTROL:r:SUPP REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87PUSH:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXCH +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXCH +ATTRIBUTES: NOTSX +CPL : 3 +COMMENT : UNDOC ALIAS +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FXCH_ST0_X87_DFC1 + +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():rw:f80 REG2=XED_REG_X87STATUS:w:SUPP +IFORM : FXCH_ST0_X87_DDC1 +} + + + +{ +ICLASS : FNOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP X87_CONTROL NOTSX +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000] +OPERANDS : +} +{ +ICLASS : FCHS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FABS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FTST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXAM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDL2T +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDL2E +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDPI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDLG2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDLN2 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLDZ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110] +OPERANDS : REG0=XED_REG_ST0:w:SUPP:f80 REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : F2XM1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FYL2X +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPTAN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPATAN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FXTRACT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FPREM1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDECSTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110] +OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FINCSTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111] +OPERANDS : REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FPREM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FYL2XP1 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:rw:SUPP:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSQRT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSINCOS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:w:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FRNDINT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSCALE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSIN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOS +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-mod fc3-u ] +PATTERN : 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111] +OPERANDS : REG0=XED_REG_ST0:rw:SUPP:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVBE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVU +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOMPP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:rw:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem32int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem32int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNBE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ cf-tst zf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCMOVNU +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FCMOV +EXTENSION : X87 +ISA_SET : FCMOV +FLAGS : MUST [ pf-tst fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:cw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNCLEX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010] +OPERANDS : REG0=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FNINIT +CPL : 3 +ATTRIBUTES : x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011] +OPERANDS : REG0=XED_REG_X87CONTROL:w:SUPP REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSETPM287_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100] +OPERANDS : +COMMENT : UNDOC +} +{ +ICLASS : FENI8087_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : +COMMENT : UNDOC +} +{ +ICLASS : FDISI8087_NOP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: NOP NOTSX +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001] +COMMENT : UNDOC +OPERANDS : +} + + +{ +ICLASS : FUCOMI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FSUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64real REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +ISA_SET : SSE3X87 +ATTRIBUTES : NOTSX +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64real REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FRSTOR +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : x87_mmx_state_w X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +# EOSZ=1 +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:r:mem94 REG0=XED_REG_X87CONTROL:w:SUPP +# EOSZ!=1 +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:mem108 REG0=XED_REG_X87CONTROL:w:SUPP +} +{ +ICLASS : FNSAVE +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : x87_mmx_state_r x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +OPERANDS : MEM0:w:mem94 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP + +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +OPERANDS : MEM0:w:mem108 \ + REG0=XED_REG_X87CONTROL:rw:SUPP \ + REG1=XED_REG_X87TAG:rw:SUPP \ + REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FNSTSW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16 REG0=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FFREE +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP +} +{ +ICLASS : FST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=X87():w:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FUCOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FIADD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIMUL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOM +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FICOMP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISUBR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIV +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIDIVR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FADDP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. faddp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FMULP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fmulp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FCOMPP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-mod fc1-mod fc2-mod fc3-mod ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001] +OPERANDS : REG0=XED_REG_ST0:r:SUPP:f80 REG1=XED_REG_ST1:r:SUPP:f80 REG2=XED_REG_X87POP2:r:SUPP REG3=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FSUBRP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fsubrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. + +} +{ +ICLASS : FSUBP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fsubp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FDIVRP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fdivrp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. + +} +{ +ICLASS : FDIVP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=X87():rw:f80 REG1=XED_REG_ST0:r:IMPL:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +COMMENT : 2011-02-10: the pop essentially occurs later. fdivp st2 reads st2,st0 and writes st1. but xed says st2 is written. No other way to do it. +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem16int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : SSE3 +ISA_SET : SSE3X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FIST +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem16int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FBLD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:mem80dec REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FILD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : REG0=XED_REG_ST0:w:IMPL:f80 MEM0:r:m64int REG1=XED_REG_X87PUSH:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FBSTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:w:mem80dec REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FISTP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +FLAGS : MUST [ fc0-u fc1-mod fc2-u fc3-u ] +PATTERN : 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:w:m64int REG0=XED_REG_ST0:r:IMPL:f80 REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FFREEP +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES: X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP +COMMENT : UNDOC +} +{ +ICLASS : FNSTSW +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_NOWAIT X87_CONTROL NOTSX +FLAGS : MUST [ fc0-u fc1-u fc2-u fc3-u ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000] +OPERANDS : REG0=XED_REG_AX:w:IMPL REG1=XED_REG_X87STATUS:rw:SUPP +} +{ +ICLASS : FUCOMIP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : FCOMIP +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ISA_SET : PPRO +FLAGS : MUST [ zf-mod pf-mod cf-mod af-0 sf-0 of-0 fc1-mod ] +PATTERN : 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87POP:r:SUPP REG3=XED_REG_X87STATUS:w:SUPP +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_LOCK_MEMb_IMMb_80r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_MEMb_IMMb_80r0 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : ADD_GPR8_IMMb_80r0 +} + + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_LOCK_MEMb_IMMb_80r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_MEMb_IMMb_80r1 +} + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : OR_GPR8_IMMb_80r1 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_LOCK_MEMb_IMMb_80r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_MEMb_IMMb_80r2 +} + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADC_GPR8_IMMb_80r2 +} + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_LOCK_MEMb_IMMb_80r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_MEMb_IMMb_80r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SBB_GPR8_IMMb_80r3 +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_LOCK_MEMb_IMMb_80r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_MEMb_IMMb_80r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : AND_GPR8_IMMb_80r4 +} + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_LOCK_MEMb_IMMb_80r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_MEMb_IMMb_80r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SUB_GPR8_IMMb_80r5 +} + + + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_LOCK_MEMb_IMMb_80r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_MEMb_IMMb_80r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : XOR_GPR8_IMMb_80r6 +} + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : CMP_MEMb_IMMb_80r7 + +PATTERN : 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : CMP_GPR8_IMMb_80r7 +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:z +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():rw IMM0:r:z +} + + + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +PATTERN : 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +} + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_LOCK_MEMb_IMMb_82r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADD_MEMb_IMMb_82r0 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADD_GPR8_IMMb_82r0 +} + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_LOCK_MEMb_IMMb_82r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : OR_MEMb_IMMb_82r1 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : OR_GPR8_IMMb_82r1 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_LOCK_MEMb_IMMb_82r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : ADC_MEMb_IMMb_82r2 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : ADC_GPR8_IMMb_82r2 +} + + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_LOCK_MEMb_IMMb_82r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SBB_MEMb_IMMb_82r3 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SBB_GPR8_IMMb_82r3 +} + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_LOCK_MEMb_IMMb_82r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : AND_MEMb_IMMb_82r4 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : AND_GPR8_IMMb_82r4 +} + + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_LOCK_MEMb_IMMb_82r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b:i8 +IFORM : SUB_MEMb_IMMb_82r5 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:i8 +IFORM : SUB_GPR8_IMMb_82r5 +} + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_LOCK_MEMb_IMMb_82r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : XOR_MEMb_IMMb_82r6 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : XOR_GPR8_IMMb_82r6 +} + +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : CMP_MEMb_IMMb_82r7 + +PATTERN : 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : CMP_GPR8_IMMb_82r7 +} + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b:i8 +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:i8 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:v IMM0:r:b:i8 + +PATTERN : 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_B():r IMM0:r:b:i8 +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM() +OPERANDS : MEM0:w:v REG0=XED_REG_STACKPOP:r:spw:SUPP + +PATTERN : 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64() +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_STACKPOP:r:spw:SUPP +IFORM : POP_GPRv_8F +} + + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-mod ], IMMx MUST [ of-u cf-mod ] +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +# 2009-02-09: THIS WAS MISSING ENTIRELY UNTIL NOW +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : ROR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : ROR_GPR8_ONE +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : ROR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : ROR_GPRv_ONE +} + + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} + +{ +ICLASS : ROR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL + +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} + + + + + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : ROL_MEMb_ONE +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : ROL_GPR8_ONE +} + +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : ROL_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : ROL_GPRv_ONE +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-mod ] # REMOVED cf-tst 2009-02-08 +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : ROL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL + +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} + +################# + + + + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : SHL_MEMb_IMMb_C0r4 + +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : SHL_GPR8_IMMb_C0r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +IFORM : SHL_MEMb_IMMb_C0r6 + +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +IFORM : SHL_GPR8_IMMb_C0r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : BYTEOP +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:b IMM0:r:b +PATTERN : 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b +} + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod cf-tst cf-mod ], IMMx MUST [ of-u cf-tst cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +IFORM : SHL_MEMv_IMMb_C1r4 + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +IFORM : SHL_GPRv_IMMb_C1r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +IFORM : SHL_MEMv_IMMb_C1r6 + +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +IFORM : SHL_GPRv_IMMb_C1r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I186 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rw:v IMM0:r:b +PATTERN : 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : RCL_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : RCL_GPR8_ONE +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : RCR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : RCR_GPR8_ONE +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHL_MEMb_ONE_D0r4 + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPR8_ONE_D0r4 + +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHL_MEMb_ONE_D0r6 + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPR8_ONE_D0r6 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SHR_MEMb_ONE + +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SHR_GPR8_ONE +} + +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:b IMM0:r:b:IMPL +IFORM : SAR_MEMb_ONE +PATTERN : 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +OPERANDS : REG0=GPR8_B():rw IMM0:r:b:IMPL +IFORM : SAR_GPR8_ONE +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : RCL_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : RCL_GPRv_ONE +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod cf-tst cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : RCR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : RCR_GPRv_ONE +} + +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHR_GPRv_ONE +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHL_MEMv_ONE_D1r6 + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPRv_ONE_D1r6 + +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SHL_MEMv_ONE_D1r4 + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SHL_GPRv_ONE_D1r4 +} + + +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : IMPLICIT_ONE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +OPERANDS : MEM0:rw:v IMM0:r:b:IMPL +IFORM : SAR_MEMv_ONE + +PATTERN : 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b:IMPL +IFORM : SAR_GPRv_ONE +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMb_CL_D2r4 + +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPR8_CL_D2r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMb_CL_D2r6 + +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPR8_CL_D2r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:rw:b REG0=XED_REG_CL:r:IMPL +PATTERN : 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=XED_REG_CL:r:IMPL +} + +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCL +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : RCR +CPL : 3 +CATEGORY : ROTATE +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u cf-tst cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMv_CL_D3r4 +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPRv_CL_D3r4 +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +IFORM : SHL_MEMv_CL_D3r6 +} +{ +ICLASS : SHL +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +IFORM : SHL_GPRv_CL_D3r6 +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:rw:v REG0=XED_REG_CL:r:IMPL +} +{ +ICLASS : SAR +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=XED_REG_CL:r:IMPL +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : TEST_MEMb_IMMb_F6r0 + +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() +OPERANDS : MEM0:r:b IMM0:r:b:i8 +IFORM : TEST_MEMb_IMMb_F6r1 + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : TEST_GPR8_IMMb_F6r0 + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +OPERANDS : REG0=GPR8_B():r IMM0:r:b:i8 +IFORM : TEST_GPR8_IMMb_F6r1 +} + +{ +ICLASS : NOT_LOCK +DISASM : not +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : NEG_LOCK +DISASM : neg +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AL:r:SUPP REG1=XED_REG_AX:w:SUPP + +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AL:r:SUPP REG2=XED_REG_AX:w:SUPP +} +{ +ICLASS : DIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP +} +{ +ICLASS : IDIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=XED_REG_AX:rw:SUPP +PATTERN : 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=XED_REG_AX:rw:SUPP +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +IFORM : TEST_MEMv_IMMz_F7r0 + +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:r:v IMM0:r:z +IFORM : TEST_MEMv_IMMz_F7r1 + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +IFORM : TEST_GPRv_IMMz_F7r0 + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():r IMM0:r:z +IFORM : TEST_GPRv_IMMz_F7r1 +} +{ +ICLASS : NOT_LOCK +DISASM : not +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NOT +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +} +{ +ICLASS : NEG_LOCK +DISASM : neg +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : NEG +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP +} +{ +ICLASS : MUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():w:SUPP + +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():w:SUPP +} +{ +ICLASS : DIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP +} +{ +ICLASS : IDIV +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-u pf-u cf-u ] +PATTERN : 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=OrAX():rw:SUPP REG1=OrDX():rw:SUPP +PATTERN : 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=OrAX():rw:SUPP REG2=OrDX():rw:SUPP +} +{ +ICLASS : INC_LOCK +DISASM : inc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : DEC_LOCK +DISASM : dec +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPR8_B():rw +} +{ +ICLASS : INC_LOCK +DISASM : inc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +IFORM : INC_GPRv_FFr0 +} +{ +ICLASS : DEC_LOCK +DISASM : dec +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():rw +IFORM : DEC_GPRv_FFr1 +} + +{ +ICLASS : CALL_NEAR +DISASM_INTEL: call +DISASM_ATTSV: call +CPL : 3 +CATEGORY : CALL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK() +OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK() +OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP REG2=rIP():rw:SUPP +} +{ +ICLASS : CALL_NEAR +DISASM_INTEL: call +DISASM_ATTSV: call +CPL : 3 +CATEGORY : CALL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0xE8 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_EIP:rw:SUPP +PATTERN : 0xE8 mode64 BRDISP32() DF64() FORCE64() +OPERANDS : RELBR:r:d REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE INDIRECT_BRANCH +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK() +OPERANDS : MEM0:r:v REG0=rIP():w:SUPP +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK() +OPERANDS : REG0=GPRv_B():r REG1=rIP():w:SUPP +} +{ +ICLASS : JMP_FAR +DISASM_INTEL: jmp far +DISASM_ATTSV: ljmp +CPL : 3 +ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:p2 REG0=rIP():w:SUPP +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM() +OPERANDS : MEM0:r:v REG0=XED_REG_STACKPUSH:w:spw:SUPP + +PATTERN : 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64() +OPERANDS : REG0=GPRv_B():r REG1=XED_REG_STACKPUSH:w:spw:SUPP +IFORM : PUSH_GPRv_FFr6 +} +{ +ICLASS : SLDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_LDTR:r:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_LDTR:r:SUPP +} +{ +ICLASS : STR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_TR:r:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_TR:r:SUPP +} +{ +ICLASS : LLDT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_LDTR:w:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_LDTR:w:SUPP +} +{ +ICLASS : LTR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_TR:w:SUPP + +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_TR:w:SUPP +} +{ +ICLASS : VERR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:w +COMMENT : reads a selector +} +{ +ICLASS : VERR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPR16_B():r +COMMENT : reads a selector +} +{ +ICLASS : VERW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:w +COMMENT : reads a selector +} +{ +ICLASS : VERW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPR16_B():r +COMMENT : reads a selector +} +{ +ICLASS : LGDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored + +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:r:s64 REG0=XED_REG_GDTR:w:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() +OPERANDS : MEM0:r:s REG0=XED_REG_GDTR:w:SUPP +} +{ +ICLASS : SMSW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored + +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=XED_REG_CR0:r:SUPP +} +{ +ICLASS : SMSW +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=XED_REG_CR0:r:SUPP +} +{ +ICLASS : LMSW +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:w REG0=XED_REG_CR0:w:SUPP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPR16_B():r REG1=XED_REG_CR0:w:SUPP +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:r:v IMM0:r:b +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():r IMM0:r:b +} +{ +ICLASS : BTS_LOCK +DISASM : bts +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : BTR_LOCK +DISASM : btr +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} +{ +ICLASS : BTC_LOCK +DISASM : btc +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix +OPERANDS : MEM0:rw:v IMM0:r:b +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rw IMM0:r:b +} + +# NOTE: VMXON and VMCLEAR almost conflict when there is a redundant 66 +# on VMXON. It should be (and is) a VMXON. VMCLEAR is required to +# "not have" f2/f3; osz_refining_prefix handles this. + +{ +ICLASS : VMCLEAR +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : VMPTRLD +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : VMPTRST +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:q +} + + +{ +ICLASS : VMXON +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: PROTECTED_MODE NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM() +OPERANDS : MEM0:r:q +} +{ +ICLASS : CMPXCHG8B_LOCK +DISASM : cmpxchg8b +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +} +{ +ICLASS : CMPXCHG8B +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:q REG0=XED_REG_EDX:rcw:SUPP REG1=XED_REG_EAX:rcw:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EBX:r:SUPP +} +{ +ICLASS : CMPXCHG16B_LOCK +DISASM : cmpxchg16b +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : LONGMODE +ISA_SET : CMPXCHG16B +ATTRIBUTES: REQUIRES_ALIGNMENT LOCKED +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix +OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP +} +{ +ICLASS : CMPXCHG16B +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : LONGMODE +ISA_SET : CMPXCHG16B +ATTRIBUTES: REQUIRES_ALIGNMENT LOCKABLE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix +OPERANDS : MEM0:rcw:dq REG0=XED_REG_RDX:rcw:SUPP REG1=XED_REG_RAX:rcw:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RBX:r:SUPP +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP + +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +OPERANDS : REG0=GPR8_B():w IMM0:r:b +IFORM : MOV_GPR8_IMMb_C6r0 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP HLE_REL_ABLE +PATTERN : 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b IMM0:r:b +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_B():w IMM0:r:z +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : HLE_REL_ABLE +PATTERN : 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +OPERANDS : MEM0:w:v IMM0:r:z +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:i16 IMM0:r:b +} +{ +ICLASS : PSLLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u16 IMM0:r:b +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b +} +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:i16 IMM0:r:b +} +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u16 IMM0:r:b +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:i32 IMM0:r:b +} +{ +ICLASS : PSLLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u32 IMM0:r:b +} +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b +} +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:i32 IMM0:r:b +} +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u32 IMM0:r:b +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b +} +{ +ICLASS : PSLLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_B():rw:q:u64 IMM0:r:b +} +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b +} +{ +ICLASS : PSRLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b +} +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u64 IMM0:r:b +} +{ +ICLASS : PSLLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_B():rw:dq:u128 IMM0:r:b +} +{ +ICLASS : FXSAVE +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM() +OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP +} +{ +ICLASS : FXRSTOR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM() +OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP +} +{ +ICLASS : FXSAVE64 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE64 +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM() +OPERANDS : MEM0:w:mfpxenv REG0=XED_REG_X87CONTROL:r:SUPP +} +{ +ICLASS : FXRSTOR64 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : FXSAVE64 +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w X87_NOWAIT X87_CONTROL NOTSX +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM() +OPERANDS : MEM0:r:mfpxenv REG0=XED_REG_X87CONTROL:w:SUPP +} + + + + + +{ +ICLASS : LDMXCSR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : SSEMXCSR +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP +} +{ +ICLASS : STMXCSR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +ISA_SET : SSEMXCSR +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : MXCSR_RD +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP +} +{ +ICLASS : PREFETCHNTA +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH NONTEMPORAL +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT0 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT1 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHT2 +CPL : 3 +CATEGORY : PREFETCH +ATTRIBUTES: PREFETCH +EXTENSION : SSE +ISA_SET : SSE_PREFETCH +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r0 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r1 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r2 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r3 + + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r4 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r4 + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r5 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r5 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r6 + +PATTERN : 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS : REG0=GPRv_B():r +IFORM : NOP_GPRv_0F18r7 +} + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18r6 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r6 +} + +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F18r7 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP + +PATTERN : 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v +IFORM : NOP_MEMv_0F18r7 +} + + +{ +ICLASS : NOP +UNAME : NOP0F19 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F19 + +PATTERN : 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F19 +} +{ +ICLASS : NOP +CPL : 3 +UNAME : NOP0F1A +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1A + +PATTERN : 0x0F 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A +} +{ +ICLASS : NOP +UNAME : NOP0F1B +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B +} +{ +ICLASS : NOP +UNAME : NOP0F1C +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C + +PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1C +} +{ +ICLASS : NOP +UNAME : NOP0F1D +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1D + +PATTERN : 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1D +} +{ +ICLASS : NOP +UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + +{ +ICLASS : NOP +UNAME : NOP0F1F +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1F +PATTERN : 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1F +} +{ +ICLASS : VMCALL +CPL : 3 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix +OPERANDS : +} +{ +ICLASS : VMLAUNCH +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix +OPERANDS : +} +{ +ICLASS : VMRESUME +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +COMMENT : on some execution paths loads all flags from VMCS. Always writes CF/PF/AF/ZF/SF/OF. +FLAGS : MAY [ id-mod vip-mod vif-mod ac-mod vm-tst rf-mod nt-mod iopl-tst iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix +OPERANDS : +} +{ +ICLASS : VMXOFF +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES: NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-mod pf-mod ] + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix +OPERANDS : +} +{ +ICLASS : SGDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:w:s64 REG0=XED_REG_GDTR:r:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:s REG0=XED_REG_GDTR:r:SUPP +} +{ +ICLASS : LIDT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: RING0 NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:r:s64 REG0=XED_REG_IDTR:w:SUPP +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() +OPERANDS : MEM0:r:s REG0=XED_REG_IDTR:w:SUPP +} +{ +ICLASS : MONITOR +CPL : 0 +CATEGORY : MISC +EXTENSION : MONITOR +ISA_SET : MONITOR +ATTRIBUTES: RING0 NOTSX + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16 +OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP +} +{ +ICLASS : MWAIT +CPL : 0 +CATEGORY : MISC +EXTENSION : MONITOR +ISA_SET : MONITOR +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP +} +{ +ICLASS : SIDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES: NOTSX +COMMENT : 66 is OSZ; F2/F3 ignored +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:s REG0=XED_REG_IDTR:r:SUPP +} +{ +ICLASS : SIDT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +COMMENT : 66 is OSZ; F2/F3 ignored +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM() +OPERANDS : MEM0:w:s64 REG0=XED_REG_IDTR:r:SUPP +} +{ +ICLASS : INVLPG +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION BYTEOP RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:b +} +{ +ICLASS : SWAPGS +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : LONGMODE +ATTRIBUTES: RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64 +OPERANDS : +} +{ +ICLASS : RDTSCP +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : RDTSCP +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_TSC:r:SUPP REG4=XED_REG_TSCAUX:r:SUPP +} +{ +ICLASS : SFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : CLFLUSH +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : CLFSH +ISA_SET : CLFSH +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : LFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE2 +ISA_SET : SSE2 +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : MFENCE +CPL : 3 +CATEGORY : MISC +EXTENSION : SSE2 +ISA_SET : SSE2 +ATTRIBUTES: IGNORES_OSFXSR +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix +OPERANDS : +} +{ +ICLASS : MOVHLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : MOVLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 +} +{ +ICLASS : MOVLHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q:f32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : MOVHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:q:f32 MEM0:r:q:f32 +} +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : ADD_GPR8_GPR8_00 +} + + + +{ +ICLASS : ADD_LOCK +DISASM : add +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : ADD_GPRv_GPRv_01 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : ADD_GPR8_GPR8_02 +} + + + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : ADD_GPRv_GPRv_03 +} + +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x04 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : ADD +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x05 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x06 not64 +OPERANDS : REG0=XED_REG_ES:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x07 not64 +OPERANDS : REG0=XED_REG_ES:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : OR_GPR8_GPR8_08 +} + + + + +{ +ICLASS : OR_LOCK +DISASM : or +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : OR_GPRv_GPRv_09 +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : OR_GPR8_GPR8_0A +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : OR_GPRv_GPRv_0B +} + + + +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x0C UIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b +} +{ +ICLASS : OR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x0D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0E not64 +OPERANDS : REG0=XED_REG_CS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : ADC_GPR8_GPR8_10 +} + + + +{ +ICLASS : ADC_LOCK +DISASM : adc +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : ADC_GPRv_GPRv_11 +} + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : ADC_GPR8_GPR8_12 +} + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] + +PATTERN : 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : ADC_GPRv_GPRv_13 +} + + + + + +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x14 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : ADC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x15 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x16 not64 +OPERANDS : REG0=XED_REG_SS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x17 not64 +COMMENT : Inhibits all interrupts until after next instr +OPERANDS : REG0=XED_REG_SS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : SBB_GPR8_GPR8_18 +} + + + + + + +{ +ICLASS : SBB_LOCK +DISASM : sbb +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] + +PATTERN : 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : SBB_GPRv_GPRv_19 +} + + +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : SBB_GPR8_GPR8_1A + +PATTERN : 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : SBB_GPRv_GPRv_1B + +PATTERN : 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1C SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : SBB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-tst cf-mod ] +PATTERN : 0x1D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x1E not64 +OPERANDS : REG0=XED_REG_DS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x1F not64 +OPERANDS : REG0=XED_REG_DS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : AND_GPR8_GPR8_20 +} + + + +{ +ICLASS : AND_LOCK +DISASM : and +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : AND_GPRv_GPRv_21 +} + + + +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : AND_GPR8_GPR8_22 + +PATTERN : 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : AND_GPRv_GPRv_23 + +PATTERN : 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x24 SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : AND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x25 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : DAA +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x27 not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP +} + + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : SUB_GPR8_GPR8_28 +} + + +{ +ICLASS : SUB_LOCK +DISASM : sub +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : SUB_GPRv_GPRv_29 +} + + + +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : SUB_GPR8_GPR8_2A +PATTERN : 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : SUB_GPRv_GPRv_2B + +PATTERN : 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2C SIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b:i8 +} +{ +ICLASS : SUB +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x2D SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : DAS +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-tst af-mod pf-mod cf-tst cf-mod ] +PATTERN : 0x2F not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP +} + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():r +IFORM : XOR_GPR8_GPR8_30 +} + + + + + +{ +ICLASS : XOR_LOCK +DISASM : xor +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] + +PATTERN : 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +IFORM : XOR_GPRv_GPRv_31 +} + + + +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():rw REG1=GPR8_B():r +IFORM : XOR_GPR8_GPR8_32 + +PATTERN : 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():rw MEM0:r:b +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +IFORM : XOR_GPRv_GPRv_33 + +PATTERN : 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x34 UIMM8() +OPERANDS : REG0=XED_REG_AL:rw:IMPL IMM0:r:b +} +{ +ICLASS : XOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x35 SIMMz() +OPERANDS : REG0=OrAX():rw:IMPL IMM0:r:z +} +{ +ICLASS : AAA +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] +PATTERN : 0x37 not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=GPR8_R():r + +PATTERN : 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r +IFORM : CMP_GPR8_GPR8_38 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +PATTERN : 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : CMP_GPRv_GPRv_39 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():r MEM0:r:b +PATTERN : 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():r REG1=GPR8_B():r +IFORM : CMP_GPR8_GPR8_3A +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:v +PATTERN : 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():r REG1=GPRv_B():r +IFORM : CMP_GPRv_GPRv_3B +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3C SIMM8() +OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 +} +{ +ICLASS : CMP +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x3D SIMMz() +OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z +} +{ +ICLASS : AAS +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-u zf-u af-tst af-mod pf-u cf-mod ] +PATTERN : 0x3F not64 +OPERANDS : REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : INC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0b0100_0 SRM[rrr] not64 +OPERANDS : REG0=GPRv_SB():rw +IFORM : INC_GPRv_40 +} +{ +ICLASS : DEC +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0b0100_1 SRM[rrr] not64 +OPERANDS : REG0=GPRv_SB():rw +IFORM : DEC_GPRv_48 +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b0101_0 SRM[rrr] DF64() +OPERANDS : REG0=GPRv_SB():r REG1=XED_REG_STACKPUSH:w:spw:SUPP +IFORM : PUSH_GPRv_50 +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b0101_1 SRM[rrr] DF64() +OPERANDS : REG0=GPRv_SB():w REG1=XED_REG_STACKPOP:r:spw:SUPP +IFORM : POP_GPRv_58 +} +{ +ICLASS : PUSHA +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +# EOSZ=1 not64 +PATTERN : 0x60 mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP +PATTERN : 0x60 mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_AX:r:SUPP REG2=XED_REG_CX:r:SUPP REG3=XED_REG_DX:r:SUPP REG4=XED_REG_BX:r:SUPP REG5=XED_REG_SP:r:SUPP REG6=XED_REG_BP:r:SUPP REG7=XED_REG_SI:r:SUPP REG8=XED_REG_DI:r:SUPP +} +{ +ICLASS : PUSHAD +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I386 + # EOSZ=2 not64 +PATTERN : 0x60 mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP +PATTERN : 0x60 mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:spw8:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_EBX:r:SUPP REG5=XED_REG_ESP:r:SUPP REG6=XED_REG_EBP:r:SUPP REG7=XED_REG_ESI:r:SUPP REG8=XED_REG_EDI:r:SUPP +} +{ +ICLASS : POPA +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I186 +# EOSZ=1 not64 +PATTERN : 0x61 mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP +PATTERN : 0x61 mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_AX:w:SUPP REG2=XED_REG_CX:w:SUPP REG3=XED_REG_DX:w:SUPP REG4=XED_REG_BX:w:SUPP REG5=XED_REG_BP:w:SUPP REG6=XED_REG_SI:w:SUPP REG7=XED_REG_DI:w:SUPP + +COMMENT : eSP value on the stack is ignored! 2008-08-14 +} +{ +ICLASS : POPAD +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I386 + # EOSZ=2 not64 +PATTERN : 0x61 mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP +PATTERN : 0x61 mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw8:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:w:SUPP REG3=XED_REG_EDX:w:SUPP REG4=XED_REG_EBX:w:SUPP REG5=XED_REG_EBP:w:SUPP REG6=XED_REG_ESI:w:SUPP REG7=XED_REG_EDI:w:SUPP + +COMMENT : eSP value on the stack is ignored! 2008-08-14 +} +{ +ICLASS : BOUND +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ATTRIBUTES: EXCEPTION_BR +ISA_SET : I186 +# EOSZ=1 +PATTERN : 0x62 mode16 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a16 +PATTERN : 0x62 mode32 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a16 +# EOSZ=2 +PATTERN : 0x62 mode16 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a32 +PATTERN : 0x62 mode32 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():r MEM0:r:a32 +} +{ +ICLASS : ARPL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:rw:w REG0=GPR16_R():r +} +{ +ICLASS : ARPL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES: PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=GPR16_B():rw REG1=GPR16_R():r +} +{ +ICLASS : MOVSXD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : LONGMODE +COMMENT : Prescott reads 32b for the 16b version. My testing indicates Merom, Nehalem and later reference 16b \ + for the 16b version. I did not find an accessible Penryn. Oct 2017 (rev64) SDM documents modern behavior. \ + 2019 AMD docs say "mem32" and I am told AMD does reference 32b always. +PATTERN : 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:z +} +{ +ICLASS : MOVSXD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : LONGMODE +PATTERN : 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 +OPERANDS : REG0=GPRv_R():w REG1=GPRz_B():r +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x68 DF64() SIMMz() +OPERANDS : IMM0:r:z REG0=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I186 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz() +OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:z + +PATTERN : 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz() +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:z +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I186 +PATTERN : 0x6A DF64() SIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I186 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8() +OPERANDS : REG0=GPRv_R():w MEM0:r:v IMM0:r:b:i8 + +PATTERN : 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8() +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r IMM0:r:b:i8 +} + + +{ +ICLASS : REP_INSB +DISASM : insb +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6C repe +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6C repne +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : INSB +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6C norep +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_INSW +DISASM : insw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D mode16 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode16 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : INSW +DISASM : insw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D mode16 no66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode32 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode64 norexw_prefix 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_INSD +DISASM : insd +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6D mode16 66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode64 rexw_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode16 66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode32 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6D mode64 norexw_prefix no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6D mode64 rexw_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : INSD +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6D mode16 66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode32 no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +PATTERN : 0x6D mode64 norexw_prefix no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP + +PATTERN : 0x6D mode64 rexw_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_DX:r:SUPP +} + + +{ +ICLASS : REP_OUTSB +DISASM : outsb +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6E repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6E repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : OUTSB +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6E norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : REP_OUTSW +DISASM : outsw +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6F mode16 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + + +PATTERN : 0x6F mode16 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : OUTSW +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] +PATTERN : 0x6F mode16 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode32 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : REP_OUTSD +DISASM : outsd +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6F mode16 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F mode64 rexw_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F mode16 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode32 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0x6F mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0x6F mode64 rexw_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : OUTSD +CPL : 3 +CATEGORY : IOSTRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 NOTSX +FLAGS : READONLY [ iopl-tst df-tst ] + +PATTERN : 0x6F mode16 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode32 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0x6F mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP + +PATTERN : 0x6F mode64 rexw_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_DX:r:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x70 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x71 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x72 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x73 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x74 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x75 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x76 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x77 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x78 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x79 not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7A not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7B not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7C not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7D not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7E not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +PATTERN : 0x7F not64 BRANCH_HINT() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:b REG0=GPR8_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():r REG1=GPR8_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +PATTERN : 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw +} + + +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +PATTERN : 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw +} + + +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 + +PATTERN : 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w REG1=GPR8_R():r +IFORM : MOV_GPR8_GPR8_88 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b REG0=GPR8_R():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : HLE_REL_ABLE +PATTERN : 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:v REG0=GPRv_R():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=GPRv_R():r +IFORM : MOV_GPRv_GPRv_89 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR8_R():w MEM0:r:b + +PATTERN : 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_R():w REG1=GPR8_B():r +IFORM : MOV_GPR8_GPR8_8A +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +IFORM : MOV_GPRv_GPRv_8B +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:w REG0=SEG():r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():w REG1=SEG():r +} +{ +ICLASS : LEA +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT() +OPERANDS : REG0=GPRv_R():w AGEN:r +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS +PATTERN : 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=SEG_MOV():w MEM0:r:w +IFORM : MOV_SEG_MEMw +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +COMMENT : MOV to SS Inhibits all interrupts until after next instr. Cannot write to CS +PATTERN : 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=SEG_MOV():w REG1=GPR16_B():r +IFORM : MOV_SEG_GPR16 +} + + + +{ +ICLASS : NOP +UNAME : NOP90 +CPL : 3 +CATEGORY : NOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : I86 +PATTERN : 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix +OPERANDS : +IFORM : NOP_90 +} +{ +ICLASS : PAUSE +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : PAUSE +ISA_SET : PAUSE +PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1 +OPERANDS : +COMMENT : 2008-06-11 Ignores REX completely. Introduced on PENTIUM4 +} +{ +ICLASS : NOP +CPL : 3 +CATEGORY : NOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : I86 +PATTERN : 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0 +OPERANDS : +IFORM : NOP_90 +COMMENT : This is the encoding of PAUSE on pre-P4 systems + +} + +{ +ICLASS : XCHG +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 + +PATTERN : 0b1001_0 SRM[rrr] SRM!=0 +OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL + +# This is strange. REG0 is r8w, r8d or r8 depending on the EOSZ. mode64 +PATTERN : 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix +OPERANDS : REG0=GPRv_SB():rw REG1=OrAX():rw:IMPL +} +{ +ICLASS : CBW +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x98 mode16 no66_prefix +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +PATTERN : 0x98 mode32 66_prefix +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +PATTERN : 0x98 mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_AX:w:SUPP REG1=XED_REG_AL:r:SUPP +} +{ +ICLASS : CDQE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : LONGMODE +PATTERN : 0x98 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RAX:w:SUPP REG1=XED_REG_EAX:r:SUPP +} +{ +ICLASS : CWDE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x98 mode16 66_prefix +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x98 mode32 no66_prefix +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x98 mode64 norexw_prefix no66_prefix +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_AX:r:SUPP +} +{ +ICLASS : CWD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x99 mode16 no66_prefix +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x99 mode32 66_prefix +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +PATTERN : 0x99 mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_DX:w:SUPP REG1=XED_REG_AX:r:SUPP +} +{ +ICLASS : CQO +CPL : 3 +CATEGORY : CONVERT +EXTENSION : LONGMODE +PATTERN : 0x99 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RDX:w:SUPP REG1=XED_REG_RAX:r:SUPP +} +{ +ICLASS : CDQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x99 mode16 66_prefix +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +PATTERN : 0x99 mode32 no66_prefix +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +PATTERN : 0x99 mode64 norexw_prefix no66_prefix +OPERANDS : REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:r:SUPP +} + +{ +ICLASS : CALL_FAR +DISASM_INTEL : call far +DISASM_ATTSV : lcall +CPL : 3 +CATEGORY : CALL +ATTRIBUTES : FAR_XFER NOTSX INDIRECT_BRANCH +EXTENSION : BASE +ISA_SET : I86 + +COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) + +PATTERN : 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:p2 REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=rIP():w:SUPP +} + + +{ +ICLASS : CALL_FAR +DISASM_INTEL : call far +DISASM_ATTSV : lcall +CPL : 3 +CATEGORY : CALL +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 + +COMMENT : same privilege level does 2 pushes (spw2). inter-privilege level does 4 (not represented) + +PATTERN : 0x9A not64 BRDISPz() UIMM16() +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_STACKPUSH:w:spw2:SUPP REG1=XED_REG_EIP:w:SUPP +} + + +{ +ICLASS : FWAIT +CPL : 3 +CATEGORY : X87_ALU +EXTENSION : X87 +ATTRIBUTES : X87_CONTROL NOTSX +PATTERN : 0x9B +OPERANDS : +} +{ +ICLASS : PUSHF +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] + # DF64() EOSZ=1 +PATTERN : 0x9C mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +PATTERN : 0x9C mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +PATTERN : 0x9C mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:w:SUPP +} +{ +ICLASS : PUSHFD +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +# DF64() EOSZ=2 not64 +PATTERN : 0x9C mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP +PATTERN : 0x9C mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPUSH:w:d:SUPP +} +{ +ICLASS : PUSHFQ +CPL : 3 +CATEGORY : PUSH +EXTENSION : LONGMODE +FLAGS : MUST [ id-tst vip-tst vif-tst ac-tst vm-tst rf-tst nt-tst iopl-tst iopl-tst of-tst df-tst if-tst tf-tst sf-tst zf-tst af-tst pf-tst cf-tst ] +# DF64() EOSZ=3 mode64 +PATTERN : 0x9C mode64 norexw_prefix no66_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP +PATTERN : 0x9C mode64 rexw_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPUSH:w:q:SUPP +} +{ +ICLASS : POPF +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +# DF64() EOSZ=1 +PATTERN : 0x9D mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +PATTERN : 0x9D mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +PATTERN : 0x9D mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:w:SUPP +} +{ +ICLASS : POPFD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +# DF64() EOSZ=2 not64 +PATTERN : 0x9D mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP +PATTERN : 0x9D mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:d:SUPP +} +{ +ICLASS : POPFQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : POP +EXTENSION : LONGMODE +FLAGS : MUST [ id-pop vip-tst vif-mod ac-pop vm-tst rf-0 nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] + # DF64() EOSZ=3 mode64 +PATTERN : 0x9D mode64 norexw_prefix no66_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP +PATTERN : 0x9D mode64 rexw_prefix DF64() +OPERANDS : REG0=XED_REG_STACKPOP:r:q:SUPP +} +{ +ICLASS : SAHF +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : LAHF +FLAGS : MUST [ sf-ah zf-ah af-ah pf-ah cf-ah ] +PATTERN : 0x9E +OPERANDS : REG0=XED_REG_AH:r:SUPP +} +{ +ICLASS : LAHF +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : LAHF +FLAGS : MUST [ sf-tst zf-tst af-tst pf-tst cf-tst ] +PATTERN : 0x9F +OPERANDS : REG0=XED_REG_AH:w:SUPP +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +PATTERN : 0xA0 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:w:IMPL MEM0:r:b SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xA1 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : REG0=OrAX():w:IMPL MEM0:r:v SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +PATTERN : 0xA2 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : MEM0:w:b REG0=XED_REG_AL:r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xA3 MEMDISPv() OVERRIDE_SEG0() +OPERANDS : MEM0:w:v REG0=OrAX():r:IMPL SEG0=FINAL_DSEG():r:SUPP BASE0=XED_REG_INVALID:r:ECOND INDEX=XED_REG_INVALID:r:ECOND +} + + +{ +ICLASS : REP_MOVSB +DISASM : movsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 fixed_base1 BYTEOP +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA4 repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA4 repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA4 norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_MOVSW +DISASM : movsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 no66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 mode16 no66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : MOVSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 no66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode32 66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:w BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_MOVSD +DISASM : movsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 no66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 mode16 66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode32 no66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA5 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : MOVSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode16 66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode32 no66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +PATTERN : 0xA5 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:d BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REP_MOVSQ +DISASM : movsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode64 rexw_prefix repe OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP + +PATTERN : 0xA5 mode64 rexw_prefix repne OVERRIDE_SEG1() +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : MOVSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xA5 mode64 rexw_prefix norep OVERRIDE_SEG1() +OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:q BASE1=ArSI():rw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSB +DISASM : cmpsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA6 repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSB +DISASM : cmpsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA6 repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : CMPSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 BYTEOP +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA6 norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSW +DISASM : cmpsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSW +DISASM : cmpsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:w BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + +{ +ICLASS : CMPSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA7 mode16 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode32 66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:w BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + + +{ +ICLASS : REPE_CMPSD +DISASM : cmpsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSD +DISASM : cmpsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode16 66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode32 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +PATTERN : 0xA7 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:d BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} + + +{ +ICLASS : CMPSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0xA7 mode16 66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode32 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +PATTERN : 0xA7 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:d BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : REPE_CMPSQ +DISASM : cmpsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode64 rexw_prefix repe OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_CMPSQ +DISASM : cmpsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 fixed_base1 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xA7 mode64 rexw_prefix repne OVERRIDE_SEG0() +OPERANDS : MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:cr:SUPP:q BASE1=ArDI():rcw:SUPP SEG1=FINAL_ESEG1():r:SUPP REG0=ArCX():rcw:SUPP +} +{ +ICLASS : CMPSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 fixed_base1 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xA7 mode64 rexw_prefix norep OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP MEM1:r:SUPP:q BASE1=ArDI():rw:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xA8 SIMM8() +OPERANDS : REG0=XED_REG_AL:r:IMPL IMM0:r:b:i8 +} +{ +ICLASS : TEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-mod cf-0 ] +PATTERN : 0xA9 SIMMz() +OPERANDS : REG0=OrAX():r:IMPL IMM0:r:z +} + +{ +ICLASS : REP_STOSB +DISASM : stosb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAA repe +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAA repne +OPERANDS : MEM0:cw:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAA norep +OPERANDS : MEM0:w:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AL:r:SUPP +} + + + +{ +ICLASS : REP_STOSW +DISASM : stosw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] + +PATTERN : 0xAB mode16 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix 66_prefix repe +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAB mode16 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix 66_prefix repne +OPERANDS : MEM0:cw:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode16 no66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +PATTERN : 0xAB mode32 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +PATTERN : 0xAB mode64 norexw_prefix 66_prefix norep +OPERANDS : MEM0:w:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_AX:r:SUPP +} + + + + +{ +ICLASS : REP_STOSD +DISASM : stosd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode16 66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix no66_prefix repe +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAB mode16 66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode32 no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 norexw_prefix no66_prefix repne +OPERANDS : MEM0:cw:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode16 66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +PATTERN : 0xAB mode32 no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +PATTERN : 0xAB mode64 norexw_prefix no66_prefix norep +OPERANDS : MEM0:w:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_EAX:r:SUPP +} + + + + +{ +ICLASS : REP_STOSQ +DISASM : stosq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode64 rexw_prefix repe +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAB mode64 rexw_prefix repne +OPERANDS : MEM0:cw:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : STOSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAB mode64 rexw_prefix norep +OPERANDS : MEM0:w:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP REG0=XED_REG_RAX:r:SUPP +} + + + + +{ +ICLASS : REP_LODSB +DISASM : lodsb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAC repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAC repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:cw:SUPP MEM0:cr:SUPP:b BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAC norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AL:w:SUPP MEM0:r:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + + +{ +ICLASS : REP_LODSW +DISASM : lodsw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAD mode16 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:cw:SUPP MEM0:cr:SUPP:w BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode32 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_AX:w:SUPP MEM0:r:SUPP:w BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + + +{ +ICLASS : REP_LODSD +DISASM : lodsd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP + +PATTERN : 0xAD mode16 66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode32 no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:cw:SUPP MEM0:cr:SUPP:d BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode16 66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode32 no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +PATTERN : 0xAD mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_EAX:w:SUPP MEM0:r:SUPP:d BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + +{ +ICLASS : REP_LODSQ +DISASM : lodsq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES :REP fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode64 rexw_prefix repe OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAD mode64 rexw_prefix repne OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:cw:SUPP MEM0:cr:SUPP:q BASE0=ArSI():rcw:SUPP SEG0=FINAL_DSEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : LODSQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : READONLY [ df-tst ] +PATTERN : 0xAD mode64 rexw_prefix norep OVERRIDE_SEG0() +OPERANDS : REG0=XED_REG_RAX:w:SUPP MEM0:r:SUPP:q BASE0=ArSI():rw:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + + +{ +ICLASS : REPE_SCASB +DISASM : scasb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAE repe +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASB +DISASM : scasb +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 BYTEOP +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAE repne +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:cr:SUPP:b BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} + +{ +ICLASS : SCASB +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 BYTEOP +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAE norep +OPERANDS : REG0=XED_REG_AL:r:SUPP MEM0:r:SUPP:b BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASW +DISASM : scasw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xAF mode16 no66_prefix repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 66_prefix repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix 66_prefix repe +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASW +DISASM : scasw +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] + +PATTERN : 0xAF mode16 no66_prefix repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 66_prefix repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix 66_prefix repne +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:cr:SUPP:w BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASW +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF mode16 no66_prefix norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode32 66_prefix norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode64 norexw_prefix 66_prefix norep +OPERANDS : REG0=XED_REG_AX:r:SUPP MEM0:r:SUPP:w BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASD +DISASM : scasd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode16 66_prefix repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 no66_prefix repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix no66_prefix repe +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASD +DISASM : scasd +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode16 66_prefix repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode32 no66_prefix repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +PATTERN : 0xAF mode64 norexw_prefix no66_prefix repne +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:cr:SUPP:d BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASD +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF mode16 66_prefix norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode32 no66_prefix norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +PATTERN : 0xAF mode64 norexw_prefix no66_prefix norep +OPERANDS : REG0=XED_REG_EAX:r:SUPP MEM0:r:SUPP:d BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : REPE_SCASQ +DISASM : scasq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode64 rexw_prefix repe +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : REPNE_SCASQ +DISASM : scasq +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : REP fixed_base0 +FLAGS : MAY [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod zf-tst ] +PATTERN : 0xAF mode64 rexw_prefix repne +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:cr:SUPP:q BASE0=ArDI():rcw:SUPP SEG0=FINAL_ESEG():r:SUPP REG1=ArCX():rcw:SUPP +} +{ +ICLASS : SCASQ +CPL : 3 +CATEGORY : STRINGOP +EXTENSION : LONGMODE +ATTRIBUTES : fixed_base0 +FLAGS : MUST [ of-mod df-tst sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0xAF mode64 rexw_prefix norep +OPERANDS : REG0=XED_REG_RAX:r:SUPP MEM0:r:SUPP:q BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + + + +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b1011_0 SRM[rrr] UIMM8() +OPERANDS : REG0=GPR8_SB():w IMM0:r:b +# i had to come up with a partial nibble name +IFORM : MOV_GPR8_IMMb_B0 +} +{ +ICLASS : MOV +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0b1011_1 SRM[rrr] UIMMv() +OPERANDS : REG0=GPRv_SB():w IMM0:r:v +} +{ +ICLASS : RET_NEAR +DISASM : ret +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xC2 DF64() UIMM16() IMMUNE66_LOOP64() +OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : RET_NEAR +DISASM : ret +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xC3 DF64() IMMUNE66_LOOP64() +OPERANDS : REG0=XED_REG_STACKPOP:r:spw:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : LES +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_ES:w:SUPP +} +{ +ICLASS : LDS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=GPRz_R():w MEM0:r:p REG1=XED_REG_DS:w:SUPP +} +{ +ICLASS : ENTER +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION +PATTERN : 0xC8 DF64() UIMM16() UIMM8_1() +OPERANDS : IMM0:r:w IMM1:r:b REG0=XED_REG_STACKPUSH:w:spw:SUPP REG1=OrBP():rw:SUPP +} +{ +ICLASS : LEAVE +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I186 +ATTRIBUTES : fixed_base0 +PATTERN : 0xC9 DF64() +# Ignoring STACKPOP semantics for LEAVE because it accesses memory at rBP because of +# the initial copy of rBP to rSP as part of the LEAVE's execution. +OPERANDS : MEM0:r:SUPP:v BASE0=ArBP():r:SUPP SEG0=FINAL_SSEG0():r:SUPP REG0=OrBP():rw:SUPP REG1=OrSP():rw:SUPP +} +{ +ICLASS : RET_FAR +DISASM_INTEL: ret far +DISASM_ATTSV: lcall +CPL : 3 +CATEGORY : RET +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +COMMENT : same privilege level does 2 pops (spw2). inter-privilege level does 4 (not represented) +PATTERN : 0xCA UIMM16() +OPERANDS : IMM0:r:w REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : RET_FAR +DISASM_INTEL: ret far +DISASM_ATTSV: lcall +CPL : 3 +CATEGORY : RET +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xCB +OPERANDS : REG0=XED_REG_STACKPOP:r:spw2:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : INT3 +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] +PATTERN : 0xCC +OPERANDS : REG0=rIP():w:SUPP +} +{ +ICLASS : INT +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst if-mod tf-0 ] +PATTERN : 0xCD UIMM8() +OPERANDS : IMM0:r:b REG0=rIP():w:SUPP +} +{ +ICLASS : INTO +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ ac-mod vm-tst vm-mod rf-0 nt-mod iopl-tst of-tst if-mod tf-mod ] +PATTERN : 0xCE not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP +} +{ +ICLASS : IRET +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF mode16 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode32 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode64 norexw_prefix 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : IRETD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF mode16 66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode32 no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +PATTERN : 0xCF mode64 norexw_prefix no66_prefix +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=rIP():w:SUPP +} +{ +ICLASS : IRETQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : RET +EXTENSION : LONGMODE +FLAGS : MUST [ id-pop vip-pop vif-pop ac-pop vm-tst vm-pop rf-pop nt-tst nt-pop iopl-tst iopl-pop of-pop df-pop if-pop tf-pop sf-pop zf-pop af-pop pf-pop cf-pop ] +PATTERN : 0xCF mode64 rexw_prefix +# FIXME: This is only an approximate width for the stack pops +OPERANDS : REG0=XED_REG_STACKPOP:r:spw5:SUPP REG1=XED_REG_RIP:w:SUPP +} +{ +ICLASS : AAM +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] +PATTERN : 0xD4 not64 UIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:w:SUPP +} +{ +ICLASS : AAD +CPL : 3 +CATEGORY : DECIMAL +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-u sf-mod zf-mod af-u pf-mod cf-u ] +PATTERN : 0xD5 not64 UIMM8() +OPERANDS : IMM0:r:b:i8 REG0=XED_REG_AL:rw:SUPP REG1=XED_REG_AH:rw:SUPP +} +{ +ICLASS : SALC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-tst ] +PATTERN : 0xD6 not64 +OPERANDS : REG0=XED_REG_AL:w:SUPP +COMMENT : was undocumented, but added to SDM v3 under "undefined opcodes" in 2017 +} +{ +ICLASS : XLAT +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : fixed_base0 +PATTERN : 0xD7 OVERRIDE_SEG0() +OPERANDS : MEM0:r:SUPP:b BASE0=ArBX():r:SUPP INDEX=XED_REG_AL:r:SUPP REG0=XED_REG_AL:w:SUPP SEG0=FINAL_DSEG():r:SUPP SCALE=1:r:SUPP +} + + +{ +ICLASS : LOOPNE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +PATTERN : 0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP + +COMMENT : REPNE WITH A E1 (LOOPE) makes a LOOPNE on P5-class machines UNDOC +PATTERN : 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} +{ +ICLASS : LOOPE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +PATTERN : 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +PATTERN : 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP + +COMMENT : REPE WITH A E0 (LOOPNE) makes a LOOPE on P5-class machines UNDOC +PATTERN : 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} + + + +{ +ICLASS : LOOP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xE2 DF64() BRDISP8() IMMUNE66_LOOP64() +OPERANDS : RELBR:r:b:i8 REG0=ArCX():rw:SUPP REG1=rIP():rw:SUPP +} + +{ +ICLASS : JCXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0xE3 eamode16 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_CX:r:SUPP REG1=XED_REG_IP:rw:SUPP +} +{ +ICLASS : JECXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0xE3 eamode32 not64 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EIP:rw:SUPP +PATTERN : 0xE3 eamode32 mode64 BRDISP8() FORCE64() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : JRCXZ +COMMENT : Same opcode as JCXZ/JECXZ/JRCXZ -- asz modulated +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : LONGMODE +PATTERN : 0xE3 eamode64 BRDISP8() FORCE64() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RCX:r:SUPP REG1=XED_REG_RIP:rw:SUPP +} + +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE4 UIMM8() +OPERANDS : REG0=XED_REG_AL:w:IMPL IMM0:r:b +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE5 UIMM8() IMMUNE_REXW() +OPERANDS : REG0=OeAX():w:IMPL IMM0:r:b +} + +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE6 UIMM8() +OPERANDS : IMM0:r:b REG0=XED_REG_AL:r:IMPL +} + +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xE7 UIMM8() IMMUNE_REXW() +OPERANDS : IMM0:r:b REG0=OeAX():r:IMPL +} + +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: MPX_PREFIX_ABLE +PATTERN : 0xE9 not64 BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +PATTERN : 0xE9 mode64 FORCE64() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : JMP_FAR +DISASM_INTEL: jmp far +DISASM_ATTSV: ljmp +CPL : 3 +CATEGORY : UNCOND_BR +ATTRIBUTES : FAR_XFER NOTSX +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xEA not64 BRDISPz() UIMM16() +OPERANDS : PTR:r:p IMM0:r:w REG0=XED_REG_EIP:w:SUPP +} +{ +ICLASS : JMP +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xEB not64 BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_EIP:rw:SUPP +PATTERN : 0xEB mode64 FORCE64() BRDISP8() +OPERANDS : RELBR:r:b:i8 REG0=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEC +OPERANDS : REG0=XED_REG_AL:w:IMPL REG1=XED_REG_DX:r:IMPL +} +{ +ICLASS : IN +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xED IMMUNE_REXW() +OPERANDS : REG0=OeAX():w:IMPL REG1=XED_REG_DX:r:IMPL +} +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEE +OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=XED_REG_AL:r:IMPL +} +{ +ICLASS : OUT +CPL : 3 +CATEGORY : IO +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ iopl-tst ] +PATTERN : 0xEF IMMUNE_REXW() +OPERANDS : REG0=XED_REG_DX:r:IMPL REG1=OeAX():r:IMPL +} +{ +ICLASS : INT1 +CPL : 3 +CATEGORY : INTERRUPT +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0xF1 +OPERANDS : REG0=rIP():w:SUPP +} +{ +ICLASS : HLT +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ATTRIBUTES : RING0 NOTSX +ISA_SET : I86 +PATTERN : 0xF4 +OPERANDS : +} +{ +ICLASS : CMC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-tst cf-mod ] +PATTERN : 0xF5 +OPERANDS : +} +{ +ICLASS : CLC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-0 ] +PATTERN : 0xF8 +OPERANDS : +} +{ +ICLASS : STC +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ cf-1 ] +PATTERN : 0xF9 +OPERANDS : +} +{ +ICLASS : CLI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ vif-mod iopl-tst if-mod ] +PATTERN : 0xFA +OPERANDS : +} +{ +ICLASS : STI +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +COMMENT : Inhibits all interrupts until after next instr +FLAGS : MUST [ vif-mod iopl-tst if-mod ] +PATTERN : 0xFB +OPERANDS : +} +{ +ICLASS : CLD +ATTRIBUTES: NOTSX_COND +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ df-0 ] +PATTERN : 0xFC +OPERANDS : +} +{ +ICLASS : STD +ATTRIBUTES: NOTSX_COND +CPL : 3 +CATEGORY : FLAGOP +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ df-1 ] +PATTERN : 0xFD +OPERANDS : +} +{ +ICLASS : LAR +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +COMMENT : LAR only sometimes writes its destination register. +PATTERN : 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:w +PATTERN : 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : LSL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286PROTECTED +ATTRIBUTES : PROTECTED_MODE +FLAGS : MUST [ zf-mod ] +PATTERN : 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:w + +PATTERN : 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRz_B():r +} +{ +ICLASS : SYSCALL +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x05 mode64 FORCE64() +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:w:SUPP REG2=XED_REG_R11:w:SUPP +COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD +} +{ +ICLASS : CLTS +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I286REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x06 +OPERANDS : +} + +{ +ICLASS : SYSRET +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0x07 mode64 norexw_prefix +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ECX:r:SUPP +COMMENT : 32B VERSION IS ONLY SUPPORTED ON AMD +} +{ +ICLASS : SYSRET64 +DISASM : sysret +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +EXTENSION : LONGMODE +ISA_SET : LONGMODE +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x07 mode64 rexw_prefix +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RCX:r:SUPP REG2=XED_REG_R11:r:SUPP +} + +{ +ICLASS : MOVUPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps + +PATTERN : 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +IFORM : MOVUPS_XMMps_XMMps_0F10 + +PATTERN : 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps + +PATTERN : 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps +IFORM : MOVUPS_XMMps_XMMps_0F11 +} +{ +ICLASS : MOVLPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 +} +{ +ICLASS : UNPCKLPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq +PATTERN : 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:q +} +{ +ICLASS : UNPCKHPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:dq +PATTERN : 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:dq +} +{ +ICLASS : MOVHPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:ps:f32 +} +{ +ICLASS : MOVSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:ss + +PATTERN : 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +IFORM : MOVSS_XMMss_XMMss_0F10 + +PATTERN : 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:ss REG0=XMM_R():r:ss + +PATTERN : 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:ss REG1=XMM_R():r:ss +IFORM : MOVSS_XMMss_XMMss_0F11 +} +{ +ICLASS : MOVSLDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVSHDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVUPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd + +PATTERN : 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +IFORM : MOVUPD_XMMpd_XMMpd_0F10 + +PATTERN : 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd + +PATTERN : 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd +IFORM : MOVUPD_XMMpd_XMMpd_0F11 +} +{ +ICLASS : MOVLPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:q +PATTERN : 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:sd +} +{ +ICLASS : UNPCKLPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq +PATTERN : 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q +} +{ +ICLASS : UNPCKHPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:dq +PATTERN : 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:q +} +{ +ICLASS : MOVHPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:q +PATTERN : 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:sd +} +{ +ICLASS : MOVSD_XMM +DISASM : movsd +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:sd + +PATTERN : 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +IFORM : MOVSD_XMM_XMMsd_XMMsd_0F10 + +PATTERN : 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:sd REG0=XMM_R():r:sd + +PATTERN : 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:sd REG1=XMM_R():r:sd +IFORM : MOVSD_XMM_XMMsd_XMMsd_0F11 +} +{ +ICLASS : MOVDDUP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +PATTERN : 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +} + +{ +ICLASS : MOV_CR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 NOTSX +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=CR_R():w REG1=GPR32_B():r + +PATTERN : 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=CR_R():w REG1=GPR64_B():r +} + +{ +ICLASS : MOV_CR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=GPR32_B():w REG1=CR_R():r + +PATTERN : 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=GPR64_B():w REG1=CR_R():r +} + +{ +ICLASS : MOV_DR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 NOTSX +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=DR_R():w REG1=GPR32_B():r + +PATTERN : 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=DR_R():w REG1=GPR64_B():r +} + +{ +ICLASS : MOV_DR +DISASM : mov +CPL : 0 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES : RING0 +COMMENT : MODRM.MOD=00/01/10 aliased to MODRM.MOD=11 +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +OPERANDS : REG0=GPR32_B():w REG1=DR_R():r + +PATTERN : 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +OPERANDS : REG0=GPR64_B():w REG1=DR_R():r +} + + +{ +ICLASS : WRMSR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x30 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:w:SUPP +} +{ +ICLASS : RDTSC +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +PATTERN : 0x0F 0x31 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_TSC:r:SUPP +} +{ +ICLASS : RDMSR +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : PENTIUMREAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x32 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP +} +{ +ICLASS : RDPMC +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : RDPMC +PATTERN : 0x0F 0x33 +OPERANDS : REG0=XED_REG_EAX:w:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_MSRS:r:SUPP +} +{ +ICLASS : SYSENTER +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: PROTECTED_MODE NOTSX +FLAGS : MUST [ vm-0 rf-0 if-0 ] +PATTERN : 0x0F 0x34 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP +PATTERN : 0x0F 0x34 mode64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP +COMMENT : AMD does not document support for this in 64b mode +} +{ +ICLASS : SYSEXIT +CPL : 0 +CATEGORY : SYSRET +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: PROTECTED_MODE RING0 NOTSX +PATTERN : 0x0F 0x35 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP REG1=XED_REG_ESP:w:SUPP REG2=XED_REG_ECX:r:SUPP REG3=XED_REG_EDX:r:SUPP +PATTERN : 0x0F 0x35 mode64 +OPERANDS : REG0=XED_REG_RIP:w:SUPP REG1=XED_REG_RSP:w:SUPP REG2=XED_REG_RCX:r:SUPP REG3=XED_REG_RDX:r:SUPP +COMMENT : AMD does not document support for this in 64b mode +} +{ +ICLASS : CMOVO +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNO +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVB +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNB +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVZ +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNZ +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVBE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNBE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +PATTERN : 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : MOVMSKPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:ps +} +{ +ICLASS : SQRTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : RSQRTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : RCPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps +PATTERN : 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ANDPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : ANDNPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : ORPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : XORPS +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:xud MEM0:r:xud +PATTERN : 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:xud REG1=XMM_B():r:xud +} +{ +ICLASS : SQRTSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : RSQRTSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : RCPSS +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:ss MEM0:r:ss +PATTERN : 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MOVMSKPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:pd +} +{ +ICLASS : SQRTPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd +PATTERN : 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ANDPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : ANDNPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : ORPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : XORPD +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:xuq MEM0:r:xuq +PATTERN : 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:xuq REG1=XMM_B():r:xuq +} +{ +ICLASS : SQRTSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:sd MEM0:r:sd +PATTERN : 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:sd REG1=XMM_B():r:sd +} +{ +ICLASS : PUNPCKLBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u8 MEM0:r:d:u8 + +PATTERN : 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u8 REG1=MMX_B():r:d:u8 +} +{ +ICLASS : PUNPCKLWD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:d:u16 +PATTERN : 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:d:u16 +} +{ +ICLASS : PUNPCKLDQ +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:d:u32 +PATTERN : 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:d:u32 +} +{ +ICLASS : PACKSSWB +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PACKSSWB +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPGTB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +} +{ +ICLASS : PCMPGTB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PCMPGTW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PCMPGTW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPGTD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +} +{ +ICLASS : PCMPGTD +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : PACKUSWB +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PACKUSWB +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PUNPCKLBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKLWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKLDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PACKSSWB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPGTB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PCMPGTW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPGTD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PACKUSWB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PSHUFW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():w:q:u16 MEM0:r:q:u16 IMM0:r:b +PATTERN : 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():w:q:u16 REG1=MMX_B():r:q:u16 IMM0:r:b +} +{ +ICLASS : PCMPEQB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +PATTERN : 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PCMPEQW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PCMPEQD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +PATTERN : 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : EMMS +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : x87_mmx_state_w NOTSX +PATTERN : 0x0F 0x77 no_refining_prefix +OPERANDS : +} +{ +ICLASS : PSHUFD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b +PATTERN : 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b +} +{ +ICLASS : PCMPEQB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PCMPEQW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PCMPEQD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PSHUFLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b +PATTERN : 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b +} +{ +ICLASS : PSHUFHW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b +PATTERN : 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b +} +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} +{ +ICLASS : JO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x80 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} + + +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x81 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNO +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x82 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x83 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP + +} +{ +ICLASS : JNB +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x84 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x85 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP + +} +{ +ICLASS : JNZ +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x86 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x87 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNBE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ cf-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + + +{ +ICLASS : SETO +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNO +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ of-tst ] +PATTERN : 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETB +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNB +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst ] +PATTERN : 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETZ +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNZ +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ zf-tst ] +PATTERN : 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETBE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNBE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ cf-tst zf-tst ] +PATTERN : 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0F 0xA0 DF64() +OPERANDS : REG0=XED_REG_FS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xA1 DF64() +OPERANDS : REG0=XED_REG_FS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : CPUID +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : I486REAL +PATTERN : 0x0F 0xA2 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_EBX:w:SUPP REG2=XED_REG_ECX:crw:SUPP REG3=XED_REG_EDX:w:SUPP +} +{ +ICLASS : BT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +PATTERN : 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +} + +{ +ICLASS : CMPXCHG_LOCK +DISASM : cmpxchg +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP LOCKABLE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rcw:b REG0=GPR8_R():r REG1=XED_REG_AL:rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +ATTRIBUTES : BYTEOP +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rcw REG1=GPR8_R():r REG2=XED_REG_AL:rcw:SUPP +} + + + +{ +ICLASS : CMPXCHG_LOCK +DISASM : cmpxchg +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=OrAX():rcw:SUPP +} +{ +ICLASS : CMPXCHG +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=OrAX():rcw:SUPP +} + + + +{ +ICLASS : LSS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_SS:w:SUPP +} +{ +ICLASS : BTR_LOCK +DISASM : btr +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + +{ +ICLASS : LFS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_FS:w:SUPP +} +{ +ICLASS : LGS +CPL : 3 +CATEGORY : SEGOP +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:p2 REG1=XED_REG_GS:w:SUPP +} +{ +ICLASS : MOVZX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:b +PATTERN : 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r +PATTERN : 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:w +PATTERN : 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r +} +{ +ICLASS : XADD_LOCK +DISASM : xadd +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:b REG0=GPR8_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : BYTEOP +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():rw REG1=GPR8_R():rw +} + + + +{ +ICLASS : XADD_LOCK +DISASM : xadd +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():rw +} +{ +ICLASS : XADD +CPL : 3 +CATEGORY : SEMAPHORE +EXTENSION : BASE +ISA_SET : I486REAL +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] + +PATTERN : 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():rw +} + + +{ +ICLASS : CMPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +{ +ICLASS : MOVNTI +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : IGNORES_OSFXSR NOTSX NONTEMPORAL +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:d REG0=GPR32_R():r +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=GPR32_R():r +PATTERN : 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=GPR64_R():r +} +{ +ICLASS : PINSRW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : NOTSX +PATTERN : 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:w:u16 IMM0:r:b +PATTERN : 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=GPR32_B():r IMM0:r:b +} +{ +ICLASS : PEXTRW +EXCEPTIONS: mmx-nomem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:u16 IMM0:r:b +} +{ +ICLASS : SHUFPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +{ +ICLASS : CMPSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss IMM0:r:b +PATTERN : 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss IMM0:r:b +} +{ +ICLASS : CMPPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b +} +{ +ICLASS : PINSRW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:w IMM0:r:b +PATTERN : 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r IMM0:r:b +} +{ +ICLASS : PEXTRW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +PATTERN : 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : SHUFPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd IMM0:r:b +} +{ +ICLASS : CMPSD_XMM +DISASM : cmpsd +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd IMM0:r:b +PATTERN : 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd IMM0:r:b +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q +} +{ +ICLASS : PSRLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q +} +{ +ICLASS : PSRLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q +} +{ +ICLASS : PSRLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q +} +{ +ICLASS : PADDQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +ISA_SET : SSE2MMX +PATTERN : 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q:u64 +PATTERN : 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q:u64 +} +{ +ICLASS : PMULLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PMOVMSKB +EXCEPTIONS: mmx-nomem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : SSE +COMMENT : KNI on PentiumIII. MMX instructions intro'd w/SSE +PATTERN : 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w REG1=MMX_B():r:q:i8 +} +{ +ICLASS : ADDSUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSRLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + +{ +ICLASS : PADDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMULLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMOVMSKB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +PATTERN : 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=GPR32_R():w REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : MOVQ2DQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : MMX_EXCEPT NOTSX +PATTERN : 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=MMX_B():r:q:u64 +} +{ +ICLASS : ADDSUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MOVDQ2Q +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +ATTRIBUTES : MMX_EXCEPT NOTSX +PATTERN : 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=MMX_R():w:q:u64 REG1=XMM_B():r:q:u64 +} +{ +ICLASS : PAVGB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAVGB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q +} +{ +ICLASS : PSRAW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q +} +{ +ICLASS : PSRAD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q +} +{ +ICLASS : PAVGW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PAVGW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PMULHUW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q:u16 +} +{ +ICLASS : PMULHUW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q:u16 +} +{ +ICLASS : PMULHW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +} +{ +ICLASS : PMULHW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : MOVNTQ +EXCEPTIONS: mmx-nofp2 +ATTRIBUTES: NOTSX NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +} +{ +ICLASS : PAVGB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 +PATTERN : 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 +} + + +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:u64 +} +{ +ICLASS : PSRAW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:u64 +} + + + + +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:u64 +} +{ +ICLASS : PSRAD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:u64 +} + + + + +{ +ICLASS : PAVGW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 +PATTERN : 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 +} +{ +ICLASS : PMULHUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq:u16 +PATTERN : 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq:u16 +} +{ +ICLASS : PMULHW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : CVTTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : MOVNTDQ +ATTRIBUTES: REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq +} +{ +ICLASS : CVTDQ2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +COMMENT : ignores MXCSR. 32b int fits in f64 + +PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 +PATTERN : 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:i32 +} +{ +ICLASS : CVTPD2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : PSLLW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u16 MEM0:r:q +PATTERN : 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u16 REG1=MMX_B():r:q +} +{ +ICLASS : PSLLD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q +PATTERN : 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q +} +{ +ICLASS : PSLLQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u64 MEM0:r:q +PATTERN : 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u64 REG1=MMX_B():r:q +} +{ +ICLASS : PMULUDQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +ISA_SET : SSE2MMX +PATTERN : 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:u32 MEM0:r:q:u32 +PATTERN : 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:u32 REG1=MMX_B():r:q:u32 +} +{ +ICLASS : PMADDWD +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i16 MEM0:r:q:i16 +PATTERN : 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i16 REG1=MMX_B():r:q:i16 +} +{ +ICLASS : PSADBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : MASKMOVQ +EXCEPTIONS: mmx-nofp2 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL +PATTERN : 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0() +OPERANDS : REG0=MMX_R():r:q:u8 REG1=MMX_B():r:q:i8 MEM0:w:q:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} + + +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u16 MEM0:r:dq +} +{ +ICLASS : PSLLW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u16 REG1=XMM_B():r:dq +} + + + +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : PSLLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + + +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:u64 MEM0:r:dq:u64 +} +{ +ICLASS : PSLLQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_7 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:u64 REG1=XMM_B():r:dq:u64 +} + + + +{ +ICLASS : PMULUDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMADDWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PSADBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : MASKMOVDQU +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : fixed_base0 maskop NOTSX NONTEMPORAL +PATTERN : 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq MEM0:w:dq:SUPP BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} +{ +ICLASS : LDDQU +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : +PATTERN : 0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix +OPERANDS : REG0=XMM_R():w:pd MEM0:r:dq +} +{ +ICLASS : INVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x08 +OPERANDS : +} +{ +ICLASS : WBINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 +OPERANDS : +} +{ +ICLASS : UD0 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO_UD0_SHORT +ATTRIBUTES: NOTSX +COMMENT : Older processors (before NHM) did not take a MODRM byte sequence. Atom too. +PATTERN : 0x0F 0xFF MODE_SHORT_UD0=1 +OPERANDS : +} +{ +ICLASS : UD0 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO_UD0_LONG +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():r MEM0:r:d +PATTERN : 0x0F 0xFF MODE_SHORT_UD0=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : UD1 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():r MEM0:r:d +PATTERN : 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : UD2 +CPL : 3 +CATEGORY : MISC +EXTENSION : BASE +ISA_SET : PPRO +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0x0B +OPERANDS : +} +{ +ICLASS : MOVAPS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps + +PATTERN : 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps +IFORM : MOVAPS_XMMps_XMMps_0F28 + +PATTERN : 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:ps REG0=XMM_R():r:ps + +PATTERN : 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:ps REG1=XMM_R():r:ps +IFORM : MOVAPS_XMMps_XMMps_0F29 +} + +{ +ICLASS : CVTPI2PS +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:q:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:q:f32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVNTPS +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:ps +} +{ +ICLASS : CVTTPS2PI +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 +PATTERN : 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : CVTPS2PI +EXCEPTIONS: mmx-fp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE +ATTRIBUTES : MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:q:f32 +PATTERN : 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : UCOMISS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss +PATTERN : 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss +} +{ +ICLASS : COMISS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:ss MEM0:r:ss +PATTERN : 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:ss REG1=XMM_B():r:ss +} +{ +ICLASS : CVTSI2SS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:d:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=GPR32_B():r:d:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=GPR64_B():r:q:i32 +} +{ +ICLASS : CVTTSS2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : CVTSS2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : MOVAPD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd + +PATTERN : 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd +IFORM : MOVAPD_XMMpd_XMMpd_0F28 + +PATTERN : 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:pd REG0=XMM_R():r:pd + +PATTERN : 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:pd REG1=XMM_R():r:pd +IFORM : MOVAPD_XMMpd_XMMpd_0F29 +} +{ +ICLASS : CVTPI2PD +EXCEPTIONS: mmx-nofp +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES: MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:i32 +PATTERN : 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVNTPD +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT NONTEMPORAL +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +PATTERN : 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:pd +} +{ +ICLASS : CVTTPD2PI +EXCEPTIONS: mmx-fp-16align +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : CVTPD2PI +EXCEPTIONS: mmx-fp-16align +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MMX_EXCEPT NOTSX +PATTERN : 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=MMX_R():w:q:i32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=MMX_R():w:q:i32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : UCOMISD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd +PATTERN : 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd +} +{ +ICLASS : COMISD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-mod cf-mod ] +PATTERN : 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():r:sd MEM0:r:sd +PATTERN : 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():r:sd REG1=XMM_B():r:sd +} +{ +ICLASS : CVTSI2SD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:d:i32 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=GPR32_B():r:d:i32 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:q:i64 +PATTERN : 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=GPR64_B():r:q:i64 +} +{ +ICLASS : CVTTSD2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : CVTSD2SI +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:sd:f64 +PATTERN : 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : CMOVS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNS +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNP +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNL +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : CMOVNLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v +} +{ +ICLASS : CMOVNLE +CPL : 3 +CATEGORY : CMOV +EXTENSION : BASE +ISA_SET : CMOV +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : ADDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MULPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : CVTPS2PD +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +ATTRIBUTES: MXCSR +PATTERN : 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:pd:f64 MEM0:r:q:f32 +PATTERN : 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:pd:f64 REG1=XMM_B():r:q:f32 +} +{ +ICLASS : CVTDQ2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : SUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MINPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : DIVPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : MAXPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : ADDSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MULSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : CVTSS2SD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd:f64 MEM0:r:ss:f32 +PATTERN : 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd:f64 REG1=XMM_B():r:ss:f32 +} +{ +ICLASS : CVTTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 +PATTERN : 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 +} +{ +ICLASS : SUBSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MINSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : DIVSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : MAXSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss MEM0:r:ss +PATTERN : 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss REG1=XMM_B():r:ss +} +{ +ICLASS : ADDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MULPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : CVTPD2PS +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:ps:f32 MEM0:r:pd:f64 +PATTERN : 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:ps:f32 REG1=XMM_B():r:pd:f64 +} +{ +ICLASS : CVTPS2DQ +CPL : 3 +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:ps:f32 +PATTERN : 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:ps:f32 +} +{ +ICLASS : SUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MINPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : DIVPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MAXPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR MXCSR +PATTERN : 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : ADDSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MULSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : CVTSD2SS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : CONVERT +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ss:f32 MEM0:r:sd:f64 +PATTERN : 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ss:f32 REG1=XMM_B():r:sd:f64 +} +{ +ICLASS : SUBSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MINSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : DIVSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : MAXSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:sd MEM0:r:sd +PATTERN : 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:sd REG1=XMM_B():r:sd +} +{ +ICLASS : PUNPCKHBW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PUNPCKHWD +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PUNPCKHDQ +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : SKIPLOW32 NOTSX +PATTERN : 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:d +} +{ +ICLASS : PACKSSDW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i32 MEM0:r:q:i32 +} +{ +ICLASS : PACKSSDW +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : HALF_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i32 REG1=MMX_B():r:q:i32 +} +{ +ICLASS : MOVD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r + + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:d +} +{ +ICLASS : MOVD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX +ATTRIBUTES : NOTSX +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:d + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:d + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=MMX_R():w:q REG1=GPR32_B():r + + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +OPERANDS : MEM0:w:d REG0=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +OPERANDS : MEM0:w:d REG0=MMX_R():r:d + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +OPERANDS : REG0=GPR32_B():w REG1=MMX_R():r:d +} + + +{ +ICLASS : MOVQ +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : MOVQ_XMMdq_MEMq_0F6E + +PATTERN : 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : MOVQ_MEMq_XMMq_0F7E + +PATTERN : 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +OPERANDS : REG0=GPR64_B():w REG1=XMM_R():r:q + +PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : MOVQ_MEMq_XMMq_0FD6 + +PATTERN : 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q +IFORM : MOVQ_XMMdq_XMMq_0FD6 + +PATTERN : 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : MOVQ_XMMdq_MEMq_0F7E + +PATTERN : 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +IFORM : MOVQ_XMMdq_XMMq_0F7E +} + + +{ +ICLASS : MOVQ +EXCEPTIONS: mmx-nofp2 # FIXME guessing here... +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MMX +ISA_SET : PENTIUMMMX + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +IFORM : MOVQ_MMXq_MEMq_0F6E + +PATTERN : 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +OPERANDS : REG0=MMX_R():w:q REG1=GPR64_B():r + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +IFORM : MOVQ_MEMq_MMXq_0F7E + +PATTERN : 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +OPERANDS : REG0=GPR64_B():w REG1=MMX_R():r:q + +PATTERN : 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +IFORM : MOVQ_MMXq_MEMq_0F6F + +PATTERN : 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +IFORM : MOVQ_MMXq_MMXq_0F6F + +PATTERN : 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=MMX_R():r:q +IFORM : MOVQ_MEMq_MMXq_0F7F + +PATTERN : 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_B():w:q REG1=MMX_R():r:q +IFORM : MOVQ_MMXq_MMXq_0F7F +} + +{ +ICLASS : PUNPCKHBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PACKSSDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +PATTERN : 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +{ +ICLASS : PUNPCKLQDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +COMMENT : mem form only uses q portion of the dq load. See SDM. +PATTERN : 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : PUNPCKHQDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : SKIPLOW64 REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:q +} +{ +ICLASS : MOVDQU +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4M +ATTRIBUTES : +PATTERN : 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : MOVDQU_XMMdq_XMMdq_0F6F + +PATTERN : 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : MOVDQU_XMMdq_XMMdq_0F7F +} +{ +ICLASS : VMREAD +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +OPERANDS : MEM0:w:q REG0=GPR64_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +OPERANDS : REG0=GPR64_B():w REG1=GPR64_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +OPERANDS : MEM0:w:d REG0=GPR32_R():r + +PATTERN : 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +OPERANDS : REG0=GPR32_B():w REG1=GPR32_R():r +} +{ +ICLASS : VMWRITE +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:q + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +OPERANDS : REG0=GPR64_R():r REG1=GPR64_B():r + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:d + +PATTERN : 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +OPERANDS : REG0=GPR32_R():r REG1=GPR32_B():r +} +{ +ICLASS : HADDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : HSUBPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:pd MEM0:r:pd +PATTERN : 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:pd REG1=XMM_B():r:pd +} +{ +ICLASS : MOVDQA +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : MOVDQA_XMMdq_XMMdq_0F7F + +PATTERN : 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : MOVDQA_XMMdq_XMMdq_0F6F +} +{ +ICLASS : HADDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : HSUBPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE3 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:ps +PATTERN : 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x88 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x89 not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNS +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8A not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8B not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNP +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ pf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8C not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8D not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNL +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8E not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + + +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES : SCALABLE MPX_PREFIX_ABLE +PATTERN : 0x0F 0x8F not64 BRANCH_HINT() BRDISPz() +OPERANDS : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP +} +{ +ICLASS : JNLE +CPL : 3 +CATEGORY : COND_BR +EXTENSION : BASE +ISA_SET : I86 +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +ATTRIBUTES: MPX_PREFIX_ABLE + +PATTERN : 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32() +OPERANDS : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP +} + + +{ +ICLASS : SETS +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNS +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst ] +PATTERN : 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETP +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNP +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ pf-tst ] +PATTERN : 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETL +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNL +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst ] +PATTERN : 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETLE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : SETNLE +CPL : 3 +CATEGORY : SETCC +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : BYTEOP +FLAGS : READONLY [ sf-tst of-tst zf-tst ] +PATTERN : 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:b +PATTERN : 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR8_B():w +} +{ +ICLASS : PUSH +CPL : 3 +CATEGORY : PUSH +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x0F 0xA8 DF64() +OPERANDS : REG0=XED_REG_GS:r:IMPL REG1=XED_REG_STACKPUSH:w:spw:SUPP +} +{ +ICLASS : POP +CPL : 3 +CATEGORY : POP +EXTENSION : BASE +ISA_SET : I86 +ATTRIBUTES: NOTSX +PATTERN : 0x0F 0xA9 DF64() +OPERANDS : REG0=XED_REG_GS:w:IMPL REG1=XED_REG_STACKPOP:r:spw:SUPP +} +{ +ICLASS : RSM +CPL : 3 +CATEGORY : SYSRET +EXTENSION : BASE +ISA_SET : I486 +ATTRIBUTES: NOTSX +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-mod rf-mod nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0xAA +OPERANDS : REG0=rIP():w:SUPP +} + +{ +ICLASS : BTS_LOCK +DISASM : bts +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTS +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + + + +{ +ICLASS : SHRD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b + +PATTERN : 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b +} +{ +ICLASS : SHRD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL + +PATTERN : 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL +} + +{ +ICLASS : SHLD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : IMM1 MUST [ of-mod sf-mod zf-mod af-u pf-mod cf-mod ], IMMx MUST [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r IMM0:r:b + +PATTERN : 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r IMM0:r:b +} + +{ +ICLASS : SHLD +CPL : 3 +CATEGORY : SHIFT +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MAY [ of-u sf-mod zf-mod af-u pf-mod cf-mod ] +PATTERN : 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:rcw:v REG0=GPRv_R():r REG1=XED_REG_CL:r:IMPL + +PATTERN : 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rcw REG1=GPRv_R():r REG2=XED_REG_CL:r:IMPL +} + +{ +ICLASS : IMUL +CPL : 3 +CATEGORY : BINARY +EXTENSION : BASE +ISA_SET : I86 +FLAGS : MUST [ of-mod sf-u zf-u af-u pf-u cf-mod ] +PATTERN : 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():rw MEM0:r:v + +PATTERN : 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():rw REG1=GPRv_B():r +} + +{ +ICLASS : BTC_LOCK +DISASM : btc +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKED HLE_ACQ_ABLE HLE_REL_ABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +ATTRIBUTES : LOCKABLE +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +OPERANDS : MEM0:rw:v REG0=GPRv_R():r +} +{ +ICLASS : BTC +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u af-u pf-u cf-mod ] + +PATTERN : 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():rw REG1=GPRv_R():r +} + + +{ +ICLASS : BSF +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +COMMENT : replaced in the HSW builds +PATTERN : 0x0F 0xBC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +COMMENT : replaced in the HSW builds +PATTERN : 0x0F 0xBD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:b +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR8_B():r +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:w +} +{ +ICLASS : MOVSX +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I386 +PATTERN : 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPR16_B():r +} +{ +ICLASS : BSWAP +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : BASE +ISA_SET : I486REAL +PATTERN : 0x0F 0b1100_1 SRM[rrr] +OPERANDS : REG0=GPRv_SB():rw +} +{ +ICLASS : PSUBUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSUBUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSUBUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMINUB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMINUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PAND +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAND +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDUSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PADDUSB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDUSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PADDUSW +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMAXUB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMAXUB +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PANDN +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PANDN +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBUSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS : SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBUSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS : SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDUSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDUSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMINSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : POR +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMAXSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PXOR +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : POR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBQ +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSE2 +ISA_SET : SSE2MMX +PATTERN : 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PADDD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : MMX +ISA_SET : PENTIUMMMX +PATTERN : 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSUBB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSUBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PADDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i16 MEM0:r:dq:i16 +PATTERN : 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : PADDD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE2 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHADDSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHADDSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBD +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PHSUBSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PHSUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMADDUBSW +EXCEPTIONS: mmx-mem +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +ATTRIBUTES : DOUBLE_WIDE_OUTPUT NOTSX +PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q:i8 MEM0:r:q:i8 +PATTERN : 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q:i8 REG1=MMX_B():r:q:i8 +} +{ +ICLASS : PMADDUBSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT +PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i8 MEM0:r:dq:i8 +PATTERN : 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq:i8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : PMULHRSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMULHRSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSHUFB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSHUFB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGNB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGNB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGNW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGNW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PSIGND +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +EXCEPTIONS: mmx-mem +PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +PATTERN : 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSIGND +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PALIGNR +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q IMM0:r:b +PATTERN : 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q IMM0:r:b +} +{ +ICLASS : PALIGNR +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : PABSB +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +PATTERN : 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PABSW +EXCEPTIONS: mmx-mem +ATTRIBUTES: NOTSX +CPL : 3 +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +PATTERN : 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PABSD +EXCEPTIONS: mmx-mem +CPL : 3 +ATTRIBUTES : simd_scalar NOTSX +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=MMX_R():w:q MEM0:r:q +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar NOTSX +CATEGORY : MMX +EXTENSION : SSSE3 +ISA_SET : SSSE3MMX +PATTERN : 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=MMX_R():w:q REG1=MMX_B():r:q +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar REQUIRES_ALIGNMENT +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +{ +ICLASS : PABSD +CPL : 3 +ATTRIBUTES : simd_scalar +CATEGORY : SSE +EXTENSION : SSSE3 +EXCEPTIONS: SSE_TYPE_4 +PATTERN : 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} + +#################################################################################### +{ +ICLASS : POPCNT +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : POPCNT +ATTRIBUTES: IGNORES_OSFXSR +# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix +# to get to the 16b form 32b and 64b modes. +FLAGS : MUST [ cf-0 zf-mod of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} +#################################################################################### +{ +ICLASS : PCMPGTQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +#################################################################################### +{ +ICLASS : CRC32 +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +ATTRIBUTES : IGNORES_OSFXSR +# 2009-02-20: not using IGNORE66 on this because we need the 66 prefix +# to get to the 16b form 32b and 64b modes. + +COMMENT: The dest min size is 32b, even for EOSZ 16b. + +# The byte-readers + +PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRy_R():rw:y MEM0:r:b +PATTERN : 0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRy_R():rw:y REG1=GPR8_B():r:b + + +# The scalable readers + +PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRy_R():rw:y MEM0:r:v +PATTERN : 0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRy_R():rw:y REG1=GPRv_B():r:v + +} + + + +{ +ICLASS : BLENDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b +} +{ +ICLASS : BLENDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b +} +#######################################################################33 +{ +ICLASS : BLENDVPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 REG1=XED_REG_XMM0:r:SUPP:dq:u64 + +PATTERN : 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 REG2=XED_REG_XMM0:r:SUPP:dq:u64 +} + +{ +ICLASS : BLENDVPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 REG1=XED_REG_XMM0:r:SUPP:dq:u32 + +PATTERN : 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 REG2=XED_REG_XMM0:r:SUPP:dq:u32 +} +#################################################################################### +{ +ICLASS : PCMPEQQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq + +PATTERN : 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +#################################################################################### +{ +ICLASS : DPPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2D +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b +} +{ +ICLASS : DPPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2D +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b +} +#################################################################################### +{ +ICLASS : MOVNTDQA +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_1 +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +#################################################################################### +{ +ICLASS : EXTRACTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:ps IMM0:r:b + +PATTERN : 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +#################################################################################### +{ +ICLASS : INSERTPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:ps MEM0:r:d IMM0:r:b + +PATTERN : 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:ps REG1=XMM_B():r:ps IMM0:r:b +} +############################################################################ +{ +ICLASS : MPSADBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT DOUBLE_WIDE_OUTPUT +PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b +} +############################################################################ +{ +ICLASS : PACKUSDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT HALF_WIDE_OUTPUT +PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 + +PATTERN : 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +} +############################################################################ +{ +ICLASS : PBLENDW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b + +PATTERN : 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PBLENDVB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq REG1=XED_REG_XMM0:r:dq:SUPP + +PATTERN : 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq REG2=XED_REG_XMM0:r:dq:SUPP +} +############################################################################ +{ +ICLASS : PEXTRB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b REG0=XMM_R():r:dq IMM0:r:b +# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? +PATTERN : 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PEXTRW_SSE4 +DISASM_INTEL: pextrw +DISASM_ATTSV: pextrw +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +# this one aliases with the SSE2 version so we made a new name + +PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:w REG0=XMM_R():r:dq IMM0:r:b +IFORM : PEXTRW_SSE4_MEMw_XMMdq_IMMb + +# this one aliases with the SSE2 version so we made a new name +PATTERN : 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq IMM0:r:b +IFORM : PEXTRW_SSE4_GPR32_XMMdq_IMMb +} + +############################################################################ +{ +ICLASS : PEXTRQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:q REG0=XMM_R():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PEXTRD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq IMM0:r:b +# FIXME: 2007-06-11 Might want to make a new 64/32 reg accessor. what happens in 64b??? +PATTERN : 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:b IMM0:r:b + +PATTERN : 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:d IMM0:r:b + +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR32_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PINSRQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:q IMM0:r:b + +PATTERN : 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=GPR64_B():r:q IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDPD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:pd MEM0:r:pd IMM0:r:b +PATTERN : 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:pd REG1=XMM_B():r:pd IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDPS +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_2 +ATTRIBUTES : REQUIRES_ALIGNMENT MXCSR +PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:ps MEM0:r:ps IMM0:r:b +PATTERN : 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:ps REG1=XMM_B():r:ps IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDSD +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:q MEM0:r:q IMM0:r:b +PATTERN : 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b +} +############################################################################ +{ +ICLASS : ROUNDSS +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_3 +PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:d MEM0:r:d IMM0:r:b +PATTERN : 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:d REG1=XMM_B():r:d IMM0:r:b +} +############################################################################ +{ +ICLASS : PTEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +FLAGS : MUST [ cf-mod zf-mod of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq +} +############################################################################ +{ +ICLASS : PHMINPOSUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +} + + +{ +ICLASS : PMAXSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXSD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMAXUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + +{ +ICLASS : PMINSB +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINSD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMINUW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + +{ +ICLASS : PMULLD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} +{ +ICLASS : PMULDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +PATTERN : 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +} + + + + + +{ +ICLASS : PMOVSXBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 +PATTERN : 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 +} +{ +ICLASS : PMOVSXBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 +PATTERN : 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 +} +{ +ICLASS : PMOVSXBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 +PATTERN : 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 +} + +{ +ICLASS : PMOVSXWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 +PATTERN : 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 +} +{ +ICLASS : PMOVSXWQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 +PATTERN : 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 +} +{ +ICLASS : PMOVSXDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 +PATTERN : 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 +} + +{ +ICLASS : PMOVZXBW +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 +PATTERN : 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 +} +{ +ICLASS : PMOVZXBD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 +PATTERN : 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 +} +{ +ICLASS : PMOVZXBQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 +PATTERN : 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 +} + +{ +ICLASS : PMOVZXWD +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 +PATTERN : 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 +} +{ +ICLASS : PMOVZXWQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 +PATTERN : 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 +} +{ +ICLASS : PMOVZXDQ +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +EXCEPTIONS: SSE_TYPE_5 +ATTRIBUTES : +PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 +PATTERN : 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 +} + + + + + + + +{ +ICLASS : PCMPESTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +# 64b eosz=2 +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP +} +{ +ICLASS : PCMPESTRI64 +DISASM : pcmpestri +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +# EOSZ=3 +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP + +PATTERN : 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP +} +{ +ICLASS : PCMPISTRI +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP +} +{ +ICLASS : PCMPISTRI64 +DISASM : pcmpistri +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP + +PATTERN : 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP +} + +{ +ICLASS : PCMPESTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} +{ +ICLASS : PCMPESTRM64 +DISASM : pcmpestrm +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : PCMPISTRM +CPL : 3 +CATEGORY : SSE +EXTENSION : SSE4 +ISA_SET : SSE42 +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES: +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP + +PATTERN : 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP +} +#################################################################################### +{ +ICLASS : XGETBV +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix +OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:w:SUPP REG2=XED_REG_EAX:w:SUPP REG3=XED_REG_XCR0:r:SUPP +} + +{ +ICLASS : XSETBV +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVE +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix +OPERANDS : REG0=XED_REG_ECX:r:SUPP REG1=XED_REG_EDX:r:SUPP REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_XCR0:w:SUPP +} + + +{ +ICLASS : XSAVE +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} +{ +ICLASS : XRSTOR +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length load and conditional reg write +ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVE64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : Variable length store and conditional reg read. Reads/writes XSTATE_BV from header. +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + +{ +ICLASS : XRSTOR64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVE +COMMENT : variable length load and conditional reg write +ATTRIBUTES : xmm_state_cw REQUIRES_ALIGNMENT x87_mmx_state_cw NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XRSTOR +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + + +#################################################################################### + +{ +ICLASS : MOVBE +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : MOVBE +COMMENT : Intro on Atom Silverthorne. Intercepted by Haswell. +# +# must allow 66 prefix. So "not_refning" gives us REFINING=0 which suffices to exclude F2/F3 prefixes. +# +PATTERN : 0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v +PATTERN : 0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:v REG0=GPRv_R():r +} + + +{ +ICLASS : GETSEC +CPL : 3 +CATEGORY : SYSTEM +ATTRIBUTES: PROTECTED_MODE NOTSX +EXTENSION : SMX +PATTERN : 0x0F 0x37 no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP REG1=XED_REG_EBX:r:SUPP +} + + +#################################################################################### +{ +ICLASS : AESKEYGENASSIST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b +} +{ +ICLASS : AESENC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESENCLAST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESDEC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESDECLAST +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq +} +{ +ICLASS : AESIMC +CPL : 3 +CATEGORY : AES +EXTENSION : AES +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +PATTERN : 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} +#################################################################################### +{ +ICLASS : PCLMULQDQ +CPL : 3 +CATEGORY : PCLMULQDQ +EXTENSION : PCLMULQDQ +EXCEPTIONS: SSE_TYPE_4 +ATTRIBUTES : REQUIRES_ALIGNMENT +PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +OPERANDS : REG0=XMM_R():rw:dq MEM0:r:dq IMM0:r:b +} + + +####################################################################### +{ +ICLASS : INVEPT +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES : RING0 NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : SDM rev 27 +} +{ +ICLASS : INVVPID +CPL : 0 +CATEGORY : VTX +EXTENSION : VTX +ATTRIBUTES : RING0 NOTSX +FLAGS : MUST [ cf-mod zf-mod sf-0 of-0 af-0 pf-0 ] +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : SDM rev 27 +} + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-amd-prefetch.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : NOP +UNAME : NOP0F0D_reg +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : PREFETCH_NOP +COMMENT : AMD 3DNOW prefetches that do not touch memory. This is the reg/reg form. + +PATTERN : 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F0D +} + +# The rest are all mem forms (MODRM.MOD!=3) + +{ +ICLASS : PREFETCH_EXCLUSIVE +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +} +{ +ICLASS : PREFETCHW +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +COMMENT : was PREFETCH_MODIFIED, prefetch on >=broadwell and >=silvermont +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCHW_0F0Dr1 +} +{ +ICLASS : PREFETCH_RESERVED +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr2 +UNAME : PREFETCH_RESERVED_0F0Dr2 +} +{ +ICLASS : PREFETCHW +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +COMMENT : was PREFETCH_MODIFIED +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCHW_0F0Dr3 +} +{ +ICLASS : PREFETCH_RESERVED +CPL : 3 +ATTRIBUTES: PREFETCH +CATEGORY : PREFETCH +EXTENSION : 3DNOW_PREFETCH +ISA_SET : PREFETCH_NOP +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr4 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr5 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr6 + +PATTERN : 0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:mprefetch +IFORM : PREFETCH_RESERVED_0F0Dr7 +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-nops.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#################################################################### +# SPECIFIC WIDE NOPS RECOMMENDED BY THE PROGRAMMERS REFERENCE MANUAL +#################################################################### +#{ +#ICLASS : NOP1 +#CPL : 3 +#CATEGORY : WIDENOP +#EXTENSION : BASE +#ISA_SET : I86 +#PATTERN : 90 +#OPERANDS : +#} +{ +ICLASS : NOP2 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : I86 +PATTERN : 0x90 66_prefix +OPERANDS : +} +{ +ICLASS : NOP3 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x00 +OPERANDS : +} +{ +ICLASS : NOP4 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x40 0x00 +OPERANDS : +} +{ +ICLASS : NOP5 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x44 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP6 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x44 0x00 0x00 66_prefix +OPERANDS : +} +{ +ICLASS : NOP7 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP8 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 +OPERANDS : +} +{ +ICLASS : NOP9 +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ISA_SET : FAT_NOP +PATTERN : 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 66_prefix +OPERANDS : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/via-padlock-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : XSTORE +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_RNG +ISA_SET : VIA_PADLOCK_RNG +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] not_refining +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():r:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + +{ +ICLASS : REP_XSTORE +DISASM : xstore +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_RNG +ISA_SET : VIA_PADLOCK_RNG +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():rw:SUPP REG2=OrAX():w:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP +} + + +{ +ICLASS : REP_XCRYPTECB +DISASM : xcryptecb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + +{ +ICLASS : REP_XCRYPTCBC +DISASM : xcryptcbc +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + +{ +ICLASS : REP_XCRYPTCTR +DISASM : xcryptctr +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} +{ +ICLASS : REP_XCRYPTCFB +DISASM : xcryptcfb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} +{ +ICLASS : REP_XCRYPTOFB +DISASM : xcryptofb +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_AES +ISA_SET : VIA_PADLOCK_AES +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000] f3_refining_prefix +COMMENT : rAX contains a pointer to memory using ES segment. +OPERANDS : MEM0:w:SUPP:b REG0=OrCX():rw:SUPP REG1=OrDX():r:SUPP REG2=OrBX():r:SUPP REG3=ArAX():r:SUPP BASE0=ArDI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:cr:SUPP:b BASE1=ArSI():rcw:SUPP SEG1=FINAL_DSEG1():r:SUPP +} + + + +{ +ICLASS : REP_XSHA1 +DISASM : xsha1 +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_SHA +ISA_SET : VIA_PADLOCK_SHA +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + +{ +ICLASS : REP_XSHA256 +DISASM : xsha256 +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_SHA +ISA_SET : VIA_PADLOCK_SHA +ATTRIBUTES : REP FIXED_BASE0 BYTEOP +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +OPERANDS : REG0=ArAX():rcw:SUPP REG1=OrCX():rcw:SUPP MEM0:w:SUPP:b BASE0=ArSI():rw:SUPP SEG0=FINAL_ESEG():r:SUPP MEM1:r:SUPP:b BASE1=ArDI():r:SUPP SEG1=FINAL_ESEG1():r:SUPP +} + + + +{ +ICLASS : REP_MONTMUL +DISASM : montmul +CPL : 3 +CATEGORY : VIA_PADLOCK +EXTENSION : VIA_PADLOCK_MONTMUL +ISA_SET : VIA_PADLOCK_MONTMUL +ATTRIBUTES : REP FIXED_BASE0 +COMMENT : EAX output value undefined, so list as write. + +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP \ + REG1=XED_REG_ECX:rw:SUPP \ + REG2=XED_REG_EDX:w:SUPP \ + MEM0:rw:SUPP:pmmsz16 \ + BASE0=ArSI():r:SUPP \ + SEG0=FINAL_ESEG():r:SUPP + +PATTERN : 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32 +OPERANDS : REG0=XED_REG_EAX:rw:SUPP \ + REG1=XED_REG_ECX:rw:SUPP \ + REG2=XED_REG_EDX:w:SUPP \ + MEM0:rw:SUPP:pmmsz32 \ + BASE0=ArSI():r:SUPP \ + SEG0=FINAL_ESEG():r:SUPP +} + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-3dnow.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : FEMMS +CPL : 3 +CATEGORY : MMX +EXTENSION : 3DNOW +ATTRIBUTES : x87_mmx_state_w AMDONLY +PATTERN : 0x0F 0x0E +OPERANDS : +} +{ +ICLASS : PI2FW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PI2FW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PI2FD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PI2FD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PF2IW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PF2IW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PF2ID +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PF2ID +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFPNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFPNACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPGE +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPGE +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMIN +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMIN +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCP +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCP +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRSQRT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRSQRT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSUB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSUB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFADD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFADD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPGT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPGT +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMAX +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMAX +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCPIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCPIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRSQIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRSQIT1 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFSUBR +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFSUBR +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFACC +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFCMPEQ +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFCMPEQ +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFMUL +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFMUL +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PFRCPIT2 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PFRCPIT2 +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PMULHRW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7 +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PMULHRW +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7 +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PSWAPD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PSWAPD +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} +{ +ICLASS : PAVGUSB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF +OPERANDS : REG0=MMX_R():rw:q MEM0:r:q +} +{ +ICLASS : PAVGUSB +CPL : 3 +CATEGORY : 3DNOW +EXTENSION : 3DNOW +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF +OPERANDS : REG0=MMX_R():rw:q REG1=MMX_B():r:q +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-base.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# file: xed-amd-base.txt + +INSTRUCTIONS():: +# SYSCALL and SYSRET are supported in 32b mode only on AMD chips + +{ +ICLASS : SYSCALL_AMD +DISASM : syscall +CPL : 3 +CATEGORY : SYSCALL +EXTENSION : BASE +ISA_SET : AMD +ATTRIBUTES : AMDONLY +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod vm-0 rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x05 not64 IGNORE66() +OPERANDS : REG0=rIP():w:SUPP +} + + +{ +ICLASS : SYSRET_AMD +DISASM : sysret +CPL : 0 +CATEGORY : SYSRET +ATTRIBUTES: PROTECTED_MODE RING0 AMDONLY +EXTENSION : BASE +ISA_SET : AMD + +FLAGS : MUST [ id-mod vip-mod vif-mod ac-mod rf-0 nt-mod iopl-mod of-mod df-mod if-mod tf-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x07 not64 +OPERANDS : REG0=XED_REG_EIP:w:SUPP +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-svm.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : VMRUN +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000] +OPERANDS : REG0=ArAX():r:IMPL +} +{ +ICLASS : VMMCALL +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES : AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001] +OPERANDS : +} +{ +ICLASS : VMLOAD +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010] +OPERANDS : REG0=ArAX():r:IMPL +} +{ +ICLASS : VMSAVE +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011] +OPERANDS : +} +{ +ICLASS : STGI +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100] +OPERANDS : +} +{ +ICLASS : CLGI +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101] +OPERANDS : +} +{ +ICLASS : SKINIT +CPL : 3 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110] +OPERANDS : REG0=XED_REG_EAX:r:IMPL +} +{ +ICLASS : INVLPGA +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SVM +ATTRIBUTES: PROTECTED_MODE AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] +OPERANDS : REG0=ArAX():r:IMPL REG1=XED_REG_ECX:r:IMPL +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-sse4a.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# EXTRQ xmm:w:q, imm8, imm8 66 0F 78 /0 ib ib +# EXTRQ xmm:w:q, xmm:r:w 66 0F 79 /r + +{ +ICLASS : EXTRQ +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : SSE4a +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY +PATTERN : 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1() +OPERANDS : REG0=XMM_B():w:q IMM0:r:b IMM1:r:b +PATTERN : 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq +} + +# INSERTQ xmm:w:q xmm:r:q, imm8, imm8 f2 0f 78 /r ib ib +# INSERTQ xmm:w:q xmm:r:dq, f2 0f 79 /r + +{ +ICLASS : INSERTQ +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : SSE4a +ATTRIBUTES : ATT_OPERAND_ORDER_EXCEPTION AMDONLY +PATTERN : 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1() +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:q IMM0:r:b IMM1:r:b +PATTERN : 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:q REG1=XMM_B():r:dq +} + + +# MOVNTSD mem64:w:q, xmm:r:q f2 0f 2b /r +# MOVNTSS mem32:w:d, xmm:r:d f3 0f 2b /r + +{ +ICLASS : MOVNTSD +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE4a +ATTRIBUTES: NONTEMPORAL AMDONLY +PATTERN : 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +} +{ +ICLASS : MOVNTSS +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : SSE4a +ATTRIBUTES: NONTEMPORAL AMDONLY +PATTERN : 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d +} + +######################################################################################################### +# These next one is not part of SSE4a or SSE5. + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r + +{ +ICLASS : LZCNT +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : AMD +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} + + +{ +ICLASS : BSR +VERSION : 1 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-clzero.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: +{ +ICLASS : CLZERO +CPL : 3 +CATEGORY : CLZERO +EXTENSION : CLZERO +ATTRIBUTES : AMDONLY + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +OPERANDS : REG0=ArAX():r:SUPP +COMMENT : AMD "Zen" ~2016 (expected) CPU +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-monitorx.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : MONITORX +CPL : 3 +CATEGORY : MISC +EXTENSION : MONITORX +ISA_SET : MONITORX +ATTRIBUTES: AMDONLY + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16 +OPERANDS : REG0=XED_REG_AX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64 +OPERANDS : REG0=XED_REG_RAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP + +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32 +OPERANDS : REG0=XED_REG_EAX:r:SUPP REG1=XED_REG_ECX:r:SUPP REG2=XED_REG_EDX:r:SUPP +} +{ +ICLASS : MWAITX +CPL : 3 +CATEGORY : MISC +EXTENSION : MONITORX +ISA_SET : MONITORX +ATTRIBUTES: AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:rw:SUPP REG1=XED_REG_ECX:r:SUPP +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-mcommit.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +{ +ICLASS : MCOMMIT +CPL : 3 +CATEGORY : MISC +EXTENSION : MCOMMIT +ISA_SET : MCOMMIT +ATTRIBUTES: AMDONLY +FLAGS : MUST [ cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix +OPERANDS : + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-rdpru.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS: RDPRU +CPL: 3 +CATEGORY: RDPRU +EXTENSION: RDPRU +ISA_SET: RDPRU +ATTRIBUTES: AMDONLY +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +OPERANDS: REG0=XED_REG_EDX:w:SUPP:d REG1=XED_REG_EAX:w:SUPP:d REG2=XED_REG_ECX:r:SUPP:d +IFORM: RDPRU +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-snp.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : PSMASH +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64 +OPERANDS : REG0=XED_REG_RAX:rw:IMPL +} + + +{ +ICLASS : PVALIDATE +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix +OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_ECX:r:IMPL REG2=XED_REG_EDX:r:IMPL +} + + +{ +ICLASS : RMPADJUST +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64 +OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL REG2=XED_REG_RDX:r:IMPL +} + +{ +ICLASS : RMPUPDATE +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : SNP +ATTRIBUTES: AMDONLY +FLAGS : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64 +OPERANDS : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-invlpgb.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : INVLPGB +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : AMD_INVLPGB +ATTRIBUTES: AMDONLY +COMMENT : Is this 64b mode only? +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32 +OPERANDS : REG0=XED_REG_EAX:r:IMPL \ + REG1=XED_REG_EDX:r:IMPL \ + REG2=XED_REG_ECX:r:IMPL +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64 +OPERANDS : REG0=XED_REG_RAX:r:IMPL \ + REG1=XED_REG_EDX:r:IMPL \ + REG2=XED_REG_ECX:r:IMPL +} +{ +ICLASS : TLBSYNC +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : AMD_INVLPGB +ATTRIBUTES: AMDONLY +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix +OPERANDS : +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XOP_INSTRUCTIONS():: +{ +ICLASS: VPMACSSWW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 +} + +{ +ICLASS: VPMACSSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSSDQL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPMACSWW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 +} + +{ +ICLASS: VPMACSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSDQL +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPCMOV +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 MEM0:r:dq:i1 REG2=XMM_SE():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_B():r:dq:i1 REG3=XMM_SE():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 MEM0:r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i1 REG1=XMM_N():r:dq:i1 REG2=XMM_SE():r:dq:i1 REG3=XMM_B():r:dq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 MEM0:r:qq:i1 REG2=YMM_SE():r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_B():r:qq:i1 REG3=YMM_SE():r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 MEM0:r:qq:i1 + +PATTERN: XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:i1 REG1=YMM_N():r:qq:i1 REG2=YMM_SE():r:qq:i1 REG3=YMM_B():r:qq:i1 +} + +{ +ICLASS: VPPERM +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 MEM0:r:dq:i16 + +PATTERN: XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_SE():r:dq:i16 REG3=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPMADCSSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMADCSWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPROTB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 + +PATTERN: XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8 + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8 + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b:u8 +} + +{ +ICLASS: VPROTQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8 + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b:u8 +} + +{ +ICLASS: VPMACSSDD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSSDQH +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPMACSDD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i32 + +PATTERN: XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i32 +} + +{ +ICLASS: VPMACSDQH +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 REG2=XMM_SE():r:dq:i64 + +PATTERN: XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 REG3=XMM_SE():r:dq:i64 +} + +{ +ICLASS: VPCOMB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b:u8 + +PATTERN: XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b:u8 + +PATTERN: XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 IMM0:r:b:u8 + +PATTERN: XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 IMM0:r:b:u8 + +PATTERN: XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b:u8 + +PATTERN: XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b:u8 + +PATTERN: XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b:u8 + +PATTERN: XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b:u8 +} + +{ +ICLASS: VPCOMUQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b:u8 + +PATTERN: XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b:u8 +} + +{ +ICLASS: VFRCZPS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN: XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFRCZPD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN: XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFRCZSS +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 + +PATTERN: XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:d:f32 +} + +{ +ICLASS: VFRCZSD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN: XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS: VPROTB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN: XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPROTW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN: XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPROTD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN: XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS: VPROTQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN: XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS: VPSHLB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 MEM0:r:dq:u8 REG1=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XMM_N():r:dq:u8 + +PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN: XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPSHLW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 REG1=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 REG2=XMM_N():r:dq:u16 + +PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN: XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPSHLD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u32 REG1=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u32 REG2=XMM_N():r:dq:u32 + +PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN: XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS: VPSHLQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u64 REG1=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u64 REG2=XMM_N():r:dq:u64 + +PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN: XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS: VPHADDBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDBD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDBQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i8 + +PATTERN: XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHADDWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 + +PATTERN: XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHADDWQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i16 + +PATTERN: XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHADDUBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u16 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUBD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUBQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u8 + +PATTERN: XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u8 +} + +{ +ICLASS: VPHADDUWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u32 MEM0:r:dq:u16 + +PATTERN: XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPHADDUWQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u16 + +PATTERN: XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u16 +} + +{ +ICLASS: VPHSUBBW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i8 + +PATTERN: XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPHSUBWD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i16 + +PATTERN: XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPHSUBDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 + +PATTERN: XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPSHAB +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 MEM0:r:dq:i8 REG1=XMM_N():r:dq:i8 + +PATTERN: XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_B():r:dq:i8 REG2=XMM_N():r:dq:i8 + +PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN: XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} + +{ +ICLASS: VPSHAW +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 MEM0:r:dq:i16 REG1=XMM_N():r:dq:i16 + +PATTERN: XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:dq:i16 REG2=XMM_N():r:dq:i16 + +PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN: XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS: VPSHAD +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 MEM0:r:dq:i32 REG1=XMM_N():r:dq:i32 + +PATTERN: XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XMM_N():r:dq:i32 + +PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN: XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPSHAQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i64 REG1=XMM_N():r:dq:i64 + +PATTERN: XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i64 REG2=XMM_N():r:dq:i64 + +PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN: XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS: VPHADDDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:i64 MEM0:r:dq:i32 + +PATTERN: XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS: VPHADDUDQ +CPL: 3 +CATEGORY: XOP +ISA_SET: XOP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():w:dq:u64 MEM0:r:dq:u32 + +PATTERN: XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:dq:u32 +} + +{ +ICLASS: BEXTR_XOP +DISASM: bextr +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ] + +PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:d +PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_R():w:y MEM0:r:y IMM0:r:d + +PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +OPERANDS: REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:d +PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_R():w:y REG1=VGPRy_B():r:y IMM0:r:d +} + +{ +ICLASS: BLCFILL +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLSFILL +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCS +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: TZMSK +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCIC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLSIC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: T1MSKC +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCMSK +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: BLCI +CPL: 3 +CATEGORY: TBM +ISA_SET: TBM +EXTENSION: TBM +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod pf-u af-u zf-mod sf-mod of-0 ] + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPR32_N():w:d MEM0:r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y + +PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d +PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y +} + +{ +ICLASS: LLWPCB +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +OPERANDS: REG0=VGPRy_B():w:y +} + +{ +ICLASS: SLWPCB +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS: REG0=VGPRy_B():w:y +} + +{ +ICLASS: LWPINS +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +FLAGS: MUST [ cf-mod ] + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d +} + +{ +ICLASS: LWPVAL +CPL: 3 +CATEGORY: XOP +ISA_SET: LWP +EXTENSION: XOP +ATTRIBUTES: AMDONLY + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() +OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d + +PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() +OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-fma4-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: +{ +ICLASS: VFMADDSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMADDSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMSUBADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMSUBADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMADDSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFMADDSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFMSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFMSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFMSUBSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFMSUBSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFNMADDPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFNMADDPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFNMADDSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFNMADDSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + +{ +ICLASS: VFNMSUBPS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 + +PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 + +PATTERN: VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 + +PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 + +PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 + +PATTERN: VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 +} + +{ +ICLASS: VFNMSUBPD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: MXCSR AMDONLY + +PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 + +PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 + +PATTERN: VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 + +PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 + +PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 + +PATTERN: VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 +} + +{ +ICLASS: VFNMSUBSS +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 REG2=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 REG3=XMM_SE():r:d:f32 + +PATTERN: VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 MEM0:r:d:f32 + +PATTERN: VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_SE():r:d:f32 REG3=XMM_B():r:d:f32 +} + +{ +ICLASS: VFNMSUBSD +CPL: 3 +CATEGORY: FMA4 +ISA_SET: FMA4 +EXTENSION: FMA4 +ATTRIBUTES: SIMD_SCALAR MXCSR AMDONLY + +PATTERN: VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 REG2=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 REG3=XMM_SE():r:q:f64 + +PATTERN: VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 MEM0:r:q:f64 + +PATTERN: VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS: REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_SE():r:q:f64 REG3=XMM_B():r:q:f64 +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-vpermil2-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VPERMIL2PS +CPL : 3 +CATEGORY : XOP +EXTENSION : XOP +ISA_SET : XOP +ATTRIBUTES : AMDONLY + +# 128b W0 +PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:f32 IMM0:r:b + +# 256b W0 +PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:f32 IMM0:r:b + +# 128b W1 +PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_SE():r:dq:f32 REG3=XMM_B():r:dq:f32 IMM0:r:b + +# 256b W1 +PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_SE():r:qq:f32 REG3=YMM_B():r:qq:f32 IMM0:r:b + +} + + + +{ +ICLASS : VPERMIL2PD +CPL : 3 +CATEGORY : XOP +EXTENSION : XOP +ISA_SET : XOP +ATTRIBUTES : AMDONLY + +# 128b W0 +PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:f64 IMM0:r:b + +# 256b W0 +PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:f64 IMM0:r:b + +# 128b W1 +PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_SE():r:dq:f64 REG3=XMM_B():r:dq:f64 IMM0:r:b + +# 256b W1 +PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_SE():r:qq:f64 REG3=YMM_B():r:qq:f64 IMM0:r:b + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + + +UDELETE: NOP0F1A +UDELETE: NOP0F1B + + + +{ +ICLASS: BNDMK +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: NO_RIP_REL +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():w AGEN:r +} + + + + +{ +ICLASS: BNDCL +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCU +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r +} + +{ +ICLASS: BNDCN +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR +COMMENT: 67 prefixes will be misinterpreted on MPX NI. XED cannot ignore them. +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=BND_R():r AGEN:r + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +OPERANDS: REG0=BND_R():r REG1=GPR64_B():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +OPERANDS: REG0=BND_R():r REG1=GPR32_B():r + +} + +{ +ICLASS: BNDMOV +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: load form + +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_R():w REG1=BND_B():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:q:u32 + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: REG0=BND_R():w MEM0:r:dq:u64 + + + +} + +{ +ICLASS: BNDMOV +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: +COMMENT: store form + +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +OPERANDS: REG0=BND_B():w REG1=BND_R():r + +# 16b refs 64b memop (2x32b) but only if EASZ=32b! +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 32b refs 64b memop (2x32b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +OPERANDS: MEM0:w:q:u32 REG0=BND_R():r + +# 64b refs 128b memop (2x64b) +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +OPERANDS: MEM0:w:dq:u64 REG0=BND_R():r +} + + +{ +ICLASS: BNDLDX +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: REG0=BND_R():w MEM0:r:bnd32 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +PATTERN: 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: REG0=BND_R():w MEM0:r:bnd64 +} + +{ +ICLASS: BNDSTX +CPL: 3 +EXTENSION: MPX +CATEGORY: MPX +ISA_SET: MPX +ATTRIBUTES: EXCEPTION_BR SPECIAL_AGEN_REQUIRED INDEX_REG_IS_POINTER NO_RIP_REL +COMMENT: RIP (mode64, easz64, MOD=0, RM=5) mode disallowed in 64b And 16/32b is easize32 only +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +OPERANDS: MEM0:w:bnd32 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 # RM!=5 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +PATTERN: 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +OPERANDS: MEM0:w:bnd64 REG0=BND_R():r +} + +{ +ICLASS : NOP +CPL : 3 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : MPXMODE=1: some of the reg/reg forms of these NOPs are still NOPs. + +PATTERN : 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B +} + + +{ +ICLASS : NOP +CPL : 3 +CATEGORY : WIDENOP +ATTRIBUTES: NOP +EXTENSION : BASE +ISA_SET : PPRO +COMMENT : For MPXMODE=0 operation + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1B + +PATTERN : 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEMv_0F1A + +PATTERN : 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_B():r MEM0:r:v +IFORM : NOP_GPRv_MEM_0F1B +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-nop-remove.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +UDELETE: NOP0F1E + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : reg form MODRM.MOD=3 & MODRM.REG=0b001 f3 prefix is RDSSP{D,Q} + +# mem forms + +PATTERN : 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1E + + +# reg forms + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + + + + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b001 is for CET for all values of RM. +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +# ... +# F3 with MODRM.REG=0b111 with RM=2 or RM=3 is for CET +# ... + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + + +} + + +# REPLACE CERTAIN NOPS WITH MODAL OPTIONS basd on CET=0/1 +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + + +{ +ICLASS : NOP +#UNAME : NOP0F1E +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E + +PATTERN : 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0 +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1E +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLRSSBSY (CLRSSBSY-N/A-1) +{ +ICLASS: CLRSSBSY +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM() +OPERANDS: MEM0:rw:q:u64 +IFORM: CLRSSBSY_MEMu64 +} + + +# EMITTING ENDBR32 (ENDBR32-N/A-1) +{ +ICLASS: ENDBR32 +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR32 +} + + +# EMITTING ENDBR64 (ENDBR64-N/A-1) +{ +ICLASS: ENDBR64 +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1 +OPERANDS: +IFORM: ENDBR64 +} + + +# EMITTING INCSSPD (INCSSPD-N/A-1) +{ +ICLASS: INCSSPD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0 +OPERANDS: REG0=GPR32_B():r:d:u8 REG1=XED_REG_SSP:rw:SUPP:u64 +IFORM: INCSSPD_GPR32u8 +} + + +# EMITTING INCSSPQ (INCSSPQ-N/A-1) +{ +ICLASS: INCSSPQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64 +OPERANDS: REG0=GPR64_B():r:q:u8 REG1=XED_REG_SSP:rw:SUPP:u64 +IFORM: INCSSPQ_GPR64u8 +} + + +# EMITTING RDSSPD (RDSSPD-N/A-1) +{ +ICLASS: RDSSPD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_SSP:r:SUPP:u64 +IFORM: RDSSPD_GPR32u32 +} + + +# EMITTING RDSSPQ (RDSSPQ-N/A-1) +{ +ICLASS: RDSSPQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_SSP:r:SUPP:u64 +IFORM: RDSSPQ_GPR64u64 +} + + +# EMITTING RSTORSSP (RSTORSSP-N/A-1) +{ +ICLASS: RSTORSSP +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:rw:q:u64 REG0=XED_REG_SSP:w:SUPP:u64 +IFORM: RSTORSSP_MEMu64 +} + + +# EMITTING SAVEPREVSSP (SAVEPREVSSP-N/A-1) +{ +ICLASS: SAVEPREVSSP +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix +OPERANDS: REG0=XED_REG_SSP:r:SUPP:u64 +IFORM: SAVEPREVSSP +} + + +# EMITTING SETSSBSY (SETSSBSY-N/A-1) +{ +ICLASS: SETSSBSY +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix +OPERANDS: +IFORM: SETSSBSY +} + + +# EMITTING WRSSD (WRSSD-N/A-1) +{ +ICLASS: WRSSD +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRSSD_MEMu32_GPR32u32 +} + + +# EMITTING WRSSQ (WRSSQ-N/A-1) +{ +ICLASS: WRSSQ +CPL: 3 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRSSQ_MEMu64_GPR64u64 +} + + +# EMITTING WRUSSD (WRUSSD-N/A-1) +{ +ICLASS: WRUSSD +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: WRUSSD_MEMu32_GPR32u32 +} + + +# EMITTING WRUSSQ (WRUSSQ-N/A-1) +{ +ICLASS: WRUSSQ +CPL: 0 +CATEGORY: CET +EXTENSION: CET +ISA_SET: CET +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64 +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: WRUSSQ_MEMu64_GPR64u64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdrand/rdrand-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : RDRAND +CPL : 3 +CATEGORY : RDRAND +EXTENSION : RDRAND +ISA_SET : RDRAND +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sha/sha-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SHA1MSG1 (SHA1MSG1-N/A-1) +{ +ICLASS: SHA1MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1MSG1_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1MSG1_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1MSG2 (SHA1MSG2-N/A-1) +{ +ICLASS: SHA1MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1MSG2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1MSG2_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1NEXTE (SHA1NEXTE-N/A-1) +{ +ICLASS: SHA1NEXTE +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA1NEXTE_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA1NEXTE +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA1NEXTE_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA1RNDS4 (SHA1RNDS4-N/A-1) +{ +ICLASS: SHA1RNDS4 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b +IFORM: SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA +} + +{ +ICLASS: SHA1RNDS4 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 IMM0:r:b +IFORM: SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA +} + + +# EMITTING SHA256MSG1 (SHA256MSG1-N/A-1) +{ +ICLASS: SHA256MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA256MSG1_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256MSG1 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA256MSG1_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA256MSG2 (SHA256MSG2-N/A-1) +{ +ICLASS: SHA256MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 +IFORM: SHA256MSG2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256MSG2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 +IFORM: SHA256MSG2_XMMi32_MEMi32_SHA +} + + +# EMITTING SHA256RNDS2 (SHA256RNDS2-N/A-1) +{ +ICLASS: SHA256RNDS2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_B():r:dq:i32 REG2=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: SHA256RNDS2_XMMi32_XMMi32_SHA +} + +{ +ICLASS: SHA256RNDS2 +CPL: 3 +CATEGORY: SHA +EXTENSION: SHA +ISA_SET: SHA +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:i32 MEM0:r:dq:i32 REG1=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: SHA256RNDS2_XMMi32_MEMi32_SHA +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaveopt/xsaveopt-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVEOPT +CPL : 3 +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +COMMENT : Variable length Store and conditional reg read. reads/modifies header. +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVEOPT64 +CPL : 3 +CATEGORY : XSAVEOPT +EXTENSION : XSAVEOPT +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX +COMMENT : Variable length Store and conditional reg read. reads/modifies header. +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() +#FIXME 2007-06-25 need a meaningful width code for XSAVE/XSAVEOPT/XRSTOR +OPERANDS : MEM0:rw:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsaves/xsaves-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVES +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XSAVES64 +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + + +{ +ICLASS : XRSTORS +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditional reg write. +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + +{ +ICLASS : XRSTORS64 +CPL : 0 +CATEGORY : XSAVE +EXTENSION : XSAVES +COMMENT : variable length load and conditional reg write +ATTRIBUTES : xmm_state_w REQUIRES_ALIGNMENT x87_mmx_state_w NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:r:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xsavec/xsavec-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XSAVEC +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVEC +COMMENT : Variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + +{ +ICLASS : XSAVEC64 +CPL : 3 +CATEGORY : XSAVE +EXTENSION : XSAVEC +COMMENT : Variable length store and conditional reg read. does not read header +ATTRIBUTES : xmm_state_r REQUIRES_ALIGNMENT x87_mmx_state_r NOTSX SPECIAL_AGEN_REQUIRED +PATTERN : 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix +OPERANDS : MEM0:w:mxsave REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_XCR0:r:SUPP +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/clflushopt/clflushopt.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS: CLFLUSHOPT +CPL: 3 +CATEGORY: CLFLUSHOPT +EXTENSION: CLFLUSHOPT +ISA_SET: CLFLUSHOPT +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdseed/rdseed-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : RDSEED +CPL : 3 +CATEGORY : RDSEED +EXTENSION : RDSEED +ISA_SET : RDSEED +FLAGS : MUST [ cf-mod zf-0 of-0 af-0 pf-0 sf-0 ] +PATTERN : 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining +OPERANDS : REG0=GPRv_B():w +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/fsgsbase/fsgsbase-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + + +{ +ICLASS : RDFSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_FSBASE:r:SUPP:y + +} +{ +ICLASS : RDGSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():w REG1=XED_REG_GSBASE:r:SUPP:y + +} + + + +{ +ICLASS : WRFSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_FSBASE:w:SUPP:y + +} +{ +ICLASS : WRGSBASE +CPL : 3 +CATEGORY : RDWRFSGS +EXTENSION : RDWRFSGS +ATTRIBUTES: NOTSX + +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix +OPERANDS : REG0=GPRy_B():r REG1=XED_REG_GSBASE:w:SUPP:y + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/smap/smap-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS : CLAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-0 ] +# 0F 01 CA = 1100_1010 = 11_001_010 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix +OPERANDS : +} + +{ +ICLASS : STAC +CPL : 0 +CATEGORY : SMAP +EXTENSION : SMAP +FLAGS : MUST [ ac-1 ] +# 0F 01 CB = 1100_1011 = 11_001_011 +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix +OPERANDS : +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx/sgx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +# Both read EAX +# Both may read or write or r/w RBX, RCX, RDX +# ENCLU 0f 01 D7 +# D7 = 1101 0111 + +# ENCLS 0f 01 CF +# CF = 1100_1111 + + + +{ +ICLASS: ENCLU +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP +} + +{ + +ICLASS: ENCLS +CPL: 0 +CATEGORY: SGX +EXTENSION: SGX +ISA_SET: SGX +COMMENT: May set flags +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP \ + REG1=XED_REG_RBX:crw:SUPP \ + REG2=XED_REG_RCX:crw:SUPP \ + REG3=XED_REG_RDX:crw:SUPP + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/rdpid/rdpid-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING RDPID (RDPID-N/A-1-32) +{ +ICLASS: RDPID +CPL: 3 +CATEGORY: RDPID +EXTENSION: RDPID +ISA_SET: RDPID +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 +IFORM: RDPID_GPR32u32 +} + + +# EMITTING RDPID (RDPID-N/A-1-64) +{ +ICLASS: RDPID +CPL: 3 +CATEGORY: RDPID +EXTENSION: RDPID +ISA_SET: RDPID +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XED_REG_TSCAUX:r:SUPP:d:u32 +IFORM: RDPID_GPR64u64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pt/intelpt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: +{ +ICLASS : PTWRITE +CPL : 3 +CATEGORY : PTWRITE +EXTENSION : PTWRITE +ISA_SET : PTWRITE +PATTERN : 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix +OPERANDS : REG0=GPRy_B():r +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() +OPERANDS : MEM0:r:y + +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/movdir/movdir-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING MOVDIR64B (MOVDIR64B-N/A-1) +{ +ICLASS: MOVDIR64B +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64 +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP SEG1=XED_REG_ES:r:SUPP +IFORM: MOVDIR64B_GPRa_MEM + +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64 +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 MEM1:w:zd:SUPP BASE1=A_GPR_R():r:SUPP +IFORM: MOVDIR64B_GPRa_MEM +} + + +# EMITTING MOVDIRI (MOVDIRI-N/A-1-32) +{ +ICLASS: MOVDIRI +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix +OPERANDS: MEM0:w:d:u32 REG0=GPR32_R():r:d:u32 +IFORM: MOVDIRI_MEMu32_GPR32u32 +} + + +# EMITTING MOVDIRI (MOVDIRI-N/A-1-64) +{ +ICLASS: MOVDIRI +CPL: 3 +CATEGORY: MOVDIR +EXTENSION: MOVDIR +ISA_SET: MOVDIR +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix +OPERANDS: MEM0:w:q:u64 REG0=GPR64_R():r:q:u64 +IFORM: MOVDIRI_MEMu64_GPR64u64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/waitpkg/waitpkg-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING TPAUSE (TPAUSE-N/A-1-32) +{ +ICLASS: TPAUSE +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix +OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: TPAUSE_GPR32u32 +} + + + +# EMITTING UMONITOR (UMONITOR-N/A-1) +{ +ICLASS: UMONITOR +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +OPERANDS: REG0=A_GPR_B():r +IFORM: UMONITOR_GPRa +} + + +# EMITTING UMWAIT (UMWAIT-N/A-1-32) +{ +ICLASS: UMWAIT +CPL: 3 +CATEGORY: WAITPKG +EXTENSION: WAITPKG +ISA_SET: WAITPKG +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-0 pf-0 af-0 sf-0 of-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix +OPERANDS: REG0=GPR32_B():r:d:u32 REG1=XED_REG_EDX:r:SUPP:d:u32 REG2=XED_REG_EAX:r:SUPP:d:u32 +IFORM: UMWAIT_GPR32 +} + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-nop-mod.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +UDELETE: NOP0F1C + +{ +ICLASS : NOP +#UNAME : NOP0F1C +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO +COMMENT : memory form with MODRM.REG=0b000 and no refining prefix is CLDEMOTE +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C + + +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +} + +# re-defined by another contemporaneous ISA extension +{ +ICLASS : NOP +UNAME : NOP0F1C_REG +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +# reg form +PATTERN : 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_B():r REG1=GPRv_R():r +IFORM : NOP_GPRv_GPRv_0F1C +} + +{ +ICLASS : NOP +UNAME : NOP0F1C_MEM +CPL : 3 +CATEGORY : WIDENOP +EXTENSION : BASE +ATTRIBUTES: NOP +ISA_SET : PPRO + +PATTERN : 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0 +OPERANDS : MEM0:r:v REG0=GPRv_R():r +IFORM : NOP_MEMv_GPRv_0F1C +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLDEMOTE (CLDEMOTE-N/A-1) +{ +ICLASS: CLDEMOTE +CPL: 3 +CATEGORY: CLDEMOTE +EXTENSION: CLDEMOTE +ISA_SET: CLDEMOTE +REAL_OPCODE: Y +PATTERN: 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=1 +OPERANDS: MEM0:r:b:u8 +IFORM: CLDEMOTE_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/sgx-enclv/sgx-enclv-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING ENCLV (ENCLV-N/A-1) +{ +ICLASS: ENCLV +CPL: 3 +CATEGORY: SGX +EXTENSION: SGX_ENCLV +ISA_SET: SGX_ENCLV +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix +OPERANDS: REG0=XED_REG_EAX:r:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64 +IFORM: ENCLV +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# The neat thing is we can just end a nonterminal by starting a new one. + +AVX_INSTRUCTIONS():: +{ +ICLASS : VADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VADDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VADDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +ATTRIBUTES : simd_scalar MXCSR +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VADDSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VADDSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VANDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +{ +ICLASS : VANDNPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + + +{ +ICLASS : VANDNPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + + +{ +ICLASS : VBLENDPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VBLENDPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + + + + +{ +ICLASS : VCMPPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + + +{ +ICLASS : VCMPSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +PATTERN : VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} + + + +{ +ICLASS : VCMPSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + + +{ +ICLASS : VCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:q:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:d:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:d:f32 REG1=XMM_B():r:d:f32 +} + + +{ +ICLASS : VCVTDQ2PD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +COMMENT : ignores MXCSR. 32b int fits in f64 +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:i32 + +PATTERN : VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:i32 + +PATTERN : VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VCVTDQ2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:i32 + +PATTERN : VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:i32 + +PATTERN : VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:i32 +} + +{ +ICLASS : VCVTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 + +PATTERN : VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 + +PATTERN : VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VCVTTPD2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f64 + +PATTERN : VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:qq:f64 + +PATTERN : VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VCVTPD2PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f64 + +PATTERN : VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:qq:f64 + +PATTERN : VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS : VCVTPS2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VCVTTPS2DQ +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VCVTPS2PD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f32 + +PATTERN : VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f32 + +PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f32 + +PATTERN : VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f32 +} + + + + +{ +ICLASS : VCVTSD2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + +PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 + +PATTERN : VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VCVTTSD2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + + +PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:q:f64 + + + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 + +PATTERN : VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:q:f64 +} + + + + +{ +ICLASS : VCVTSS2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + +PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 + +PATTERN : VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 +} + +{ +ICLASS : VCVTTSS2SI +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR +COMMENT : SNB/IVB/HSW require VEX.L=128. Later processors are LIG + +PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:i32 REG1=XMM_B():r:d:f32 + + + + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 + +PATTERN : VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_R():w:q:i64 REG1=XMM_B():r:d:f32 +} + + + + +{ +ICLASS : VCVTSD2SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f64 + +PATTERN : VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:q:f64 + +} + + +{ +ICLASS : VCVTSI2SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:i64 + +PATTERN : VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=GPR64_B():r:q:i64 +} + + +{ +ICLASS : VCVTSI2SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:i32 + +PATTERN : VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR32_B():r:d:i32 + + + +PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:i64 + +PATTERN : VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=GPR64_B():r:q:i64 +} + + +{ +ICLASS : VCVTSS2SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : CONVERT +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:d:f32 + +PATTERN : VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VDIVPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VDIVPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VDIVSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VDIVSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VEXTRACTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:f64 REG0=YMM_R():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=YMM_R():r:dq:f64 IMM0:r:b +} + + + +{ +ICLASS : VDPPD +EXCEPTIONS: avx-type-2D +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b +} + +{ +ICLASS : VDPPS +EXCEPTIONS: avx-type-2D +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + + +{ +ICLASS : VEXTRACTPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w REG1=XMM_R():r:dq:f32 IMM0:r:b +} + + +{ +ICLASS : VZEROALL +EXCEPTIONS: avx-type-8 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : xmm_state_w + +PATTERN : VV1 0x77 VNP V0F VL256 NOVSR +OPERANDS: + +} + +# FIXME: how to denote partial upper clobber! +{ +ICLASS : VZEROUPPER +EXCEPTIONS: avx-type-8 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : xmm_state_w NOTSX # FIXME: should be ymm_state_w? + +PATTERN : VV1 0x77 VNP V0F VL128 NOVSR +OPERANDS: +} + + +{ +ICLASS : VHADDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VHADDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +{ +ICLASS : VHSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VHSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VPERMILPD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +# 2008-02-01 moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPD +PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:u64 + +PATTERN : VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:u64 + +PATTERN : VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:u64 + +######################################## +# IMMEDIATE FORM +######################################## + +# 2008-02-01 moved norexw_prefix to after V0F3A to avoid a graph build conflict with VPHSUBW +PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} + + +{ +ICLASS : VPERMILPS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +# moved norexw_prefix to after V0F38 to avoid graph build conflict with VBLENDPS +PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:u32 + +PATTERN : VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:u32 + +PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:u32 + +PATTERN : VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:u32 + +######################################## +# IMMEDIATE FORM +######################################## + +# 2008-02-01: moved norexw_prefix after V0F3A due to graph-build collision with VPMADDUBSW +PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b +} + + +{ +ICLASS : VPERM2F128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# 2008-02-01 moved norexw_prefix to after V0F3A to avoid conflict with VPHSUBD +PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} + + + +{ +ICLASS : VBROADCASTSS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +PATTERN : VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +} +{ +ICLASS : VBROADCASTSD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +PATTERN : VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +} + +{ +ICLASS : VBROADCASTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX +COMMENT : There is no F128 type. I just set these to f64 for lack of anything better. +PATTERN : VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +} + + +{ +ICLASS : VINSERTF128 +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 + +PATTERN : VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b EMX_BROADCAST_2TO4_64 +} + +{ +ICLASS : VINSERTPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b +} + + + + + +{ +ICLASS : VLDDQU +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq +} + + + + + + +{ +ICLASS : VMASKMOVPS +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop NONTEMPORAL +# load forms +PATTERN : VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq MEM0:r:dq:f32 + +PATTERN : VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq MEM0:r:qq:f32 + +# store forms +PATTERN : VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_N():r:dq REG1=XMM_R():r:dq:f32 + +PATTERN : VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_N():r:qq REG1=YMM_R():r:qq:f32 +} + +{ +ICLASS : VMASKMOVPD +EXCEPTIONS: avx-type-6 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop +# load forms +PATTERN : VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:f64 + +PATTERN : VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:f64 + +# store forms +PATTERN : VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:f64 + +PATTERN : VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:f64 +} + +{ +ICLASS : VPTEST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq + +PATTERN : VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq + +PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq MEM0:r:qq + +PATTERN : VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq REG1=YMM_B():r:qq +} + +{ +ICLASS : VTESTPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq:f32 REG1=YMM_B():r:qq:f32 +} + +{ +ICLASS : VTESTPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +FLAGS : MUST [ zf-mod cf-mod ] +PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():r:qq:f64 REG1=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VMAXPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMAXPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VMAXSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VMAXSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VMINPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMINPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VMINSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} + +{ +ICLASS : VMINSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +PATTERN : VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VMOVAPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# 128b load + +PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 +IFORM : VMOVAPD_XMMdq_XMMdq_28 + +# 128b store + +PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +PATTERN : VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 +IFORM : VMOVAPD_XMMdq_XMMdq_29 + +# 256b load + +PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +IFORM : VMOVAPD_YMMqq_YMMqq_28 + +# 256b store + +PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +PATTERN : VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 +IFORM : VMOVAPD_YMMqq_YMMqq_29 +} + + + +{ +ICLASS : VMOVAPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# 128b load + +PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 +IFORM : VMOVAPS_XMMdq_XMMdq_28 +# 128b store + +PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +PATTERN : VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 +IFORM : VMOVAPS_XMMdq_XMMdq_29 + +# 256b load + +PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +IFORM : VMOVAPS_YMMqq_YMMqq_28 + +# 256b store + +PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +PATTERN : VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 +IFORM : VMOVAPS_YMMqq_YMMqq_29 +} + + + +{ +ICLASS : VMOVD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# 32b load +PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d + +PATTERN : VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d + +# 32b store +PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d + +PATTERN : VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d + + + +# 32b load +PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:d + +PATTERN : VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR32_B():r:d + +# 32b store +PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XMM_R():r:d + +PATTERN : VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:d + + +} + +{ +ICLASS : VMOVQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# 64b load +PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : VMOVQ_XMMdq_MEMq_6E + +PATTERN : VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=GPR64_B():r:q + +# 64b store +PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : VMOVQ_MEMq_XMMq_7E + +PATTERN : VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:q + + +# 2nd page of MOVQ forms +PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:q +IFORM : VMOVQ_XMMdq_MEMq_7E + +PATTERN : VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:q +IFORM : VMOVQ_XMMdq_XMMq_7E + +PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q REG0=XMM_R():r:q +IFORM : VMOVQ_MEMq_XMMq_D6 + +PATTERN : VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:q +IFORM : VMOVQ_XMMdq_XMMq_D6 + +} + + + + +{ +ICLASS : VMOVDDUP +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:q:f64 + + +PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} + + + +{ +ICLASS : VMOVDQA +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT + +# LOAD XMM + +PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : VMOVDQA_XMMdq_XMMdq_6F + +# STORE XMM + +PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : VMOVDQA_XMMdq_XMMdq_7F + +# LOAD YMM + +PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq + +PATTERN : VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq +IFORM : VMOVDQA_YMMqq_YMMqq_6F + + +# STORE YMM + +PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq + +PATTERN : VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq +IFORM : VMOVDQA_YMMqq_YMMqq_7F +} + + +{ +ICLASS : VMOVDQU +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +# LOAD XMM + +PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq + +PATTERN : VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +IFORM : VMOVDQU_XMMdq_XMMdq_6F + +# LOAD YMM + +PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq + +PATTERN : VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_B():r:qq +IFORM : VMOVDQU_YMMqq_YMMqq_6F + +# STORE XMM + +PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq REG0=XMM_R():r:dq + +PATTERN : VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq REG1=XMM_R():r:dq +IFORM : VMOVDQU_XMMdq_XMMdq_7F + +# STORE YMM + +PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq REG0=YMM_R():r:qq + +PATTERN : VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq REG1=YMM_R():r:qq +IFORM : VMOVDQU_YMMqq_YMMqq_7F +} + +################################################# +## skipping to the end +################################################# + +################################################# +## MACROS +################################################# +{ +ICLASS : VMOVSHDUP +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VMOVSLDUP +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VPOR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPAND +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPANDN +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} +{ +ICLASS : VPXOR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX +PATTERN : VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 MEM0:r:dq:u128 + +PATTERN : VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u128 REG2=XMM_B():r:dq:u128 +} + + +{ +ICLASS : VPABSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:dq:i8 + +PATTERN : VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:dq:i8 +} +{ +ICLASS : VPABSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:i16 + +PATTERN : VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:i16 +} +{ +ICLASS : VPABSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:dq:i32 + +PATTERN : VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPHMINPOSUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:dq:u16 +} + + + + + + + + + + +{ +ICLASS : VPSHUFD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : VPSHUFHW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} +{ +ICLASS : VPSHUFLW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b + +PATTERN : VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +} + + + + + + + + + + + + + +{ +ICLASS : VPACKSSWB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPACKSSDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPACKUSWB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPACKUSDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSLLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSLLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSLLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPSRLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPSRAW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:u64 + +PATTERN : VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:u64 +} +{ +ICLASS : VPSRAD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:u64 + +PATTERN : VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPADDB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPADDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPADDD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPADDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPADDSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPADDSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPADDUSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPADDUSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPAVGB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPAVGW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPCMPEQB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPCMPEQW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPCMPEQD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPCMPEQQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPCMPGTB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPCMPGTW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPCMPGTD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPCMPGTQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPHADDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHADDD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPHADDSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHSUBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPHSUBD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPHSUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPMULHUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMULHRSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULHW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULLW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMULLD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMULUDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPMULDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSADBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPSHUFB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} + +{ +ICLASS : VPSIGNB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSIGNW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPSIGND +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPSUBSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} + +{ +ICLASS : VPSUBUSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPSUBUSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} + +{ +ICLASS : VPSUBB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPSUBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPSUBD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} +{ +ICLASS : VPSUBQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 MEM0:r:dq:i64 + +PATTERN : VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_N():r:dq:i64 REG2=XMM_B():r:dq:i64 +} + +{ +ICLASS : VPUNPCKHBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPUNPCKHWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPUNPCKHDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + +{ +ICLASS : VPUNPCKLBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPUNPCKLWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPUNPCKLDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} +{ +ICLASS : VPUNPCKLQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 +} + + + +{ +ICLASS : VPSRLDQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLDQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u128 REG1=XMM_B():r:dq:u128 IMM0:r:b # NDD +} + + + + + + + + + + + + + + + + + + + + +{ +ICLASS : VMOVLHPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 REG2=XMM_B():r:q:f32 +} +{ +ICLASS : VMOVHLPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 +} + + + + + + + +{ +ICLASS : VPALIGNR +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b + +PATTERN : VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 IMM0:r:b +} + + + + + + + + + + + + +############################################################ +{ +ICLASS : VROUNDPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} +{ +ICLASS : VROUNDPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 IMM0:r:b +} +{ +ICLASS : VROUNDSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 IMM0:r:b + +PATTERN : VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 IMM0:r:b +} +{ +ICLASS : VROUNDSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 IMM0:r:b + +PATTERN : VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 IMM0:r:b +} + +{ +ICLASS : VSHUFPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 IMM0:r:b +} +{ +ICLASS : VSHUFPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 IMM0:r:b + +PATTERN : VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 IMM0:r:b +} + +{ +ICLASS : VRCPPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VRCPSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: simd_scalar +PATTERN : VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VRSQRTPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VRSQRTSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: simd_scalar +PATTERN : VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VSQRTPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 + +PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +} +{ +ICLASS : VSQRTPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 + +PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +} +{ +ICLASS : VSQRTSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR simd_scalar +PATTERN : VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VSQRTSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + + +{ +ICLASS : VUNPCKHPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VUNPCKHPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + +{ +ICLASS : VSUBPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VSUBPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VSUBSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR SIMD_SCALAR +PATTERN : VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VSUBSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VMULPD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VMULPS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VMULSD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : MXCSR simd_scalar +PATTERN : VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VMULSS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR simd_scalar +PATTERN : VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VORPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} +{ +ICLASS : VORPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 + +PATTERN : VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMAXSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPMAXSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMAXSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMAXUB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPMAXUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMAXUD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + +{ +ICLASS : VPMINSB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 + +PATTERN : VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 +} +{ +ICLASS : VPMINSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMINSD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 MEM0:r:dq:i32 + +PATTERN : VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i32 REG2=XMM_B():r:dq:i32 +} + +{ +ICLASS : VPMINUB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 + +PATTERN : VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +} +{ +ICLASS : VPMINUW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:dq:u16 + +PATTERN : VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=XMM_B():r:dq:u16 +} +{ +ICLASS : VPMINUD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + +PATTERN : VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +} + + +{ +ICLASS : VPMADDWD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 MEM0:r:dq:i16 + +PATTERN : VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_N():r:dq:i16 REG2=XMM_B():r:dq:i16 +} +{ +ICLASS : VPMADDUBSW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:i8 + +PATTERN : VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:i8 +} + + +{ +ICLASS : VMPSADBW +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 IMM0:r:b +} + + +############################################################ +{ +ICLASS : VPSLLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD +} + +{ +ICLASS : VPSRAW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:i16 REG1=XMM_B():r:dq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:i32 REG1=XMM_B():r:dq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u16 REG1=XMM_B():r:dq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u32 REG1=XMM_B():r:dq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_N():w:dq:u64 REG1=XMM_B():r:dq:u64 IMM0:r:b # NDD +} + + +{ +ICLASS : VUCOMISD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] + +PATTERN : VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f64 REG1=XMM_B():r:q:f64 +} + +{ +ICLASS : VUCOMISS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : simd_scalar MXCSR + +FLAGS : MUST [ zf-mod pf-mod cf-mod of-0 af-0 sf-0 ] + +PATTERN : VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():r:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:f32 REG1=XMM_B():r:d:f32 +} + +############################################### + + +{ +ICLASS : VUNPCKLPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + +PATTERN : VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} + + +{ +ICLASS : VUNPCKLPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +PATTERN : VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + + + +{ +ICLASS : VXORPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 + +PATTERN : VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + +{ +ICLASS : VXORPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : LOGICAL_FP +EXTENSION : AVX +PATTERN : VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq +} + + +############################################################################ + +{ +ICLASS : VMOVSS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : simd_scalar + +# NOTE: REG1 is ignored!!! +PATTERN : VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:d:f32 + +PATTERN : VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:d:f32 +IFORM : VMOVSS_XMMdq_XMMdq_XMMd_10 + +PATTERN : VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:d:f32 REG0=XMM_R():r:d:f32 + +PATTERN : VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_R():r:d:f32 +IFORM : VMOVSS_XMMdq_XMMdq_XMMd_11 +} +############################################################################ +{ +ICLASS : VMOVSD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : simd_scalar + +# NOTE: REG1 is ignored!!! +PATTERN : VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:q:f64 +IFORM : VMOVSD_XMMdq_XMMdq_XMMq_10 + +PATTERN : VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 + +PATTERN : VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_R():r:q:f64 +IFORM : VMOVSD_XMMdq_XMMdq_XMMq_11 +} +############################################################################ +{ +ICLASS : VMOVUPD +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 MEM0:r:dq:f64 + +PATTERN : VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_B():r:dq:f64 +IFORM : VMOVUPD_XMMdq_XMMdq_10 + +PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +PATTERN : VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f64 REG1=XMM_R():r:dq:f64 +IFORM : VMOVUPD_XMMdq_XMMdq_11 + +# 256b versions + +PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 + +PATTERN : VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 +IFORM : VMOVUPD_YMMqq_YMMqq_10 + +PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +PATTERN : VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f64 REG1=YMM_R():r:qq:f64 +IFORM : VMOVUPD_YMMqq_YMMqq_11 +} + +############################################################################ +{ +ICLASS : VMOVUPS +EXCEPTIONS: avx-type-4M +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:dq:f32 + +PATTERN : VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 +IFORM : VMOVUPS_XMMdq_XMMdq_10 + +PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +PATTERN : VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_B():w:dq:f32 REG1=XMM_R():r:dq:f32 +IFORM : VMOVUPS_XMMdq_XMMdq_11 + +# 256b versions + +PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_B():r:qq:f32 +IFORM : VMOVUPS_YMMqq_YMMqq_10 + +PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +PATTERN : VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_B():w:qq:f32 REG1=YMM_R():r:qq:f32 +IFORM : VMOVUPS_YMMqq_YMMqq_11 +} + + +############################################################################ +{ +ICLASS : VMOVLPD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +COMMENT: 3op version uses high part of XMM_N +PATTERN : VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:q:f64 +} + +{ +ICLASS : VMOVLPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +COMMENT: 3op version uses high part of XMM_N +PATTERN : VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:q:f32 + +PATTERN : VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:q:f32 +} + +{ +ICLASS : VMOVHPD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 +PATTERN : VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 + +PATTERN : VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f64 REG0=XMM_R():r:dq:f64 +} + +{ +ICLASS : VMOVHPS +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX + +COMMENT: 3op form use low bits of REG1, 2op form uses high bits of REG0 +PATTERN : VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:q:f32 MEM0:r:q:f32 + +PATTERN : VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:q:f32 REG0=XMM_R():r:dq:f32 +} +############################################################################ + +{ +ICLASS : VMOVMSKPD +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f64 + +# 256b versions + +PATTERN : VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f64 +} + +{ +ICLASS : VMOVMSKPS +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +PATTERN : VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:f32 + +# 256b versions + +PATTERN : VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d REG1=YMM_B():r:qq:f32 +} + +############################################################################ +{ +ICLASS : VPMOVMSKB +EXCEPTIONS: avx-type-7 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=XMM_B():r:dq:i8 +} + +############################################################################ + +############################################################################ +# SX versions +############################################################################ + +{ +ICLASS : VPMOVSXBW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i16 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i16 MEM0:r:q:i8 +} + +############################################################################ +{ +ICLASS : VPMOVSXBD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:w:i8 +PATTERN : VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:w:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i32 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i32 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:d:i16 +PATTERN : VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:d:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:i64 REG1=XMM_B():r:q:i32 +PATTERN : VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:i64 MEM0:r:q:i32 +} + + + + + +############################################################################ +# ZX versions +############################################################################ + +{ +ICLASS : VPMOVZXBW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:q:u8 +} + +############################################################################ +{ +ICLASS : VPMOVZXBD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:w:u8 +PATTERN : VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:w:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:d:u16 +PATTERN : VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:d:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u32 +PATTERN : VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u32 +} + + + +############################################################################ +############################################################################ +{ +ICLASS : VPEXTRB +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG +PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:b REG0=XMM_R():r:dq:u8 IMM0:r:b + +PATTERN : VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u8 IMM0:r:b +} +############################################################################ +{ +ICLASS : VPEXTRW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG + +PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:w REG0=XMM_R():r:dq:u16 IMM0:r:b + +PATTERN : VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u16 IMM0:r:b +IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_15 + +# special C5 reg-only versions from SSE2: + +PATTERN : VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_R():w:d REG1=XMM_B():r:dq:u16 IMM0:r:b +IFORM : VPEXTRW_GPR32d_XMMdq_IMMb_C5 +} +############################################################################ +{ +ICLASS : VPEXTRQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:q REG0=XMM_R():r:dq:u64 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR64_B():w:q REG1=XMM_R():r:dq:u64 IMM0:r:b +} +############################################################################ +{ +ICLASS : VPEXTRD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled. + +# 64b mode +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b + +# not64b mode +PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:d REG0=XMM_R():r:dq:u32 IMM0:r:b +PATTERN : VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=GPR32_B():w:d REG1=XMM_R():r:dq:u32 IMM0:r:b + +} +############################################################################ + + + + + + +{ +ICLASS : VPINSRB +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT: WIG +PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +PATTERN : VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +} + +{ +ICLASS : VPINSRW +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : WIG +PATTERN : VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 MEM0:r:w:u16 IMM0:r:b + +PATTERN : VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_N():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +} + +{ +ICLASS : VPINSRD +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +COMMENT : SNB had an errata where it would #UD of VEX.W=1 outside of 64b mode. Not modeled +# 64b mode +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b + +# 32b mode +PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +} +{ +ICLASS : VPINSRQ +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +PATTERN : VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +} + +############################################################################ + + + + + +{ +ICLASS : VPCMPESTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_ECX:w:SUPP +} +{ +ICLASS : VPCMPESTRI64 +DISASM : vpcmpestri +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_RCX:w:SUPP +PATTERN : VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_RCX:w:SUPP +} +{ +ICLASS : VPCMPISTRI +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_ECX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_ECX:w:SUPP +} +{ +ICLASS : VPCMPISTRI64 +DISASM : vpcmpistri +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RCX:w:SUPP +PATTERN : VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RCX:w:SUPP +} + +{ +ICLASS : VPCMPESTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +# outside of 64b mode, vex.w is ignored for this instr +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP + +# in 64b mode, vex.w changes the behavior for GPRs +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_EDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_EAX:r:SUPP REG3=XED_REG_EDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : VPCMPESTRM64 +DISASM : vpcmpestrm +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] + +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_RAX:r:SUPP REG2=XED_REG_RDX:r:SUPP REG3=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_RAX:r:SUPP REG3=XED_REG_RDX:r:SUPP REG4=XED_REG_XMM0:w:dq:SUPP +} + +{ +ICLASS : VPCMPISTRM +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : STTNI +EXTENSION : AVX +FLAGS : MUST [ cf-mod zf-mod sf-mod of-mod af-0 pf-0 ] +PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():r:dq MEM0:r:dq IMM0:r:b REG1=XED_REG_XMM0:w:dq:SUPP +PATTERN : VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():r:dq REG1=XMM_B():r:dq IMM0:r:b REG2=XED_REG_XMM0:w:dq:SUPP +} +#################################################################################### + + + +#################################################################################### +{ +ICLASS : VMASKMOVDQU +EXCEPTIONS: avx-type-4 +CPL : 3 + +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES : maskop fixed_base0 NOTSX NONTEMPORAL +PATTERN : VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 MEM0:w:SUPP:dq:u8 BASE0=ArDI():r:SUPP SEG0=FINAL_DSEG():r:SUPP +} + +#################################################################################### +{ +ICLASS : VLDMXCSR +EXCEPTIONS: avx-type-5L +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : MEM0:r:d REG0=XED_REG_MXCSR:w:SUPP +} +{ +ICLASS : VSTMXCSR +EXCEPTIONS: avx-type-5 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +ATTRIBUTES: MXCSR_RD +PATTERN : VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : MEM0:w:d REG0=XED_REG_MXCSR:r:SUPP +} +####################################################################################### + +{ +ICLASS : VPBLENDVB +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 MEM0:r:dq:i8 REG2=XMM_SE():r:dq:i8 + +PATTERN : VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:i8 REG1=XMM_N():r:dq:i8 REG2=XMM_B():r:dq:i8 REG3=XMM_SE():r:dq:i8 +} + +{ +ICLASS : VBLENDVPD +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 REG2=XMM_SE():r:dq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 REG3=XMM_SE():r:dq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 REG2=YMM_SE():r:qq:u64 + +PATTERN : VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 REG3=YMM_SE():r:qq:u64 + +} + +{ +ICLASS : VBLENDVPS +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX + +# W0 (modrm.rm memory op 2nd to last) +PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 REG2=XMM_SE():r:dq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 REG3=XMM_SE():r:dq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 REG2=YMM_SE():r:qq:u32 + +PATTERN : VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 REG3=YMM_SE():r:qq:u32 + + +} + +####################################################################################### + + + +{ +ICLASS : VMOVNTDQA +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL + +PATTERN : VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} + + + + + +{ +ICLASS : VMOVNTDQ +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:i32 REG0=XMM_R():r:dq:i32 + +} +{ +ICLASS : VMOVNTPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f64 REG0=XMM_R():r:dq:f64 + +} +{ +ICLASS : VMOVNTPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:f32 REG0=XMM_R():r:dq:f32 + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-movnt-store.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VMOVNTDQ +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:i32 REG0=YMM_R():r:qq:i32 + +} +{ +ICLASS : VMOVNTPD +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f64 REG0=YMM_R():r:qq:f64 + +} +{ +ICLASS : VMOVNTPS +EXCEPTIONS: avx-type-1 +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL +PATTERN : VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:f32 REG0=YMM_R():r:qq:f32 + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-aes-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + +{ +ICLASS : VAESKEYGENASSIST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq IMM0:r:b +PATTERN : VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq IMM0:r:b +} +{ +ICLASS : VAESENC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESENCLAST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESDEC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESDECLAST +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq +PATTERN : VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq +} +{ +ICLASS : VAESIMC +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AES +EXTENSION : AVXAES +PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_B():r:dq +PATTERN : VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq MEM0:r:dq +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pclmul-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: +{ +ICLASS : VPCLMULQDQ +EXCEPTIONS: avx-type-4 +CPL : 3 +CATEGORY : AVX +EXTENSION : AVX +PATTERN : VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 REG2=XMM_B():r:dq:u64 IMM0:r:b +PATTERN : VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u128 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/ivbavx/fp16-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: +{ +ICLASS : VCVTPH2PS +COMMENT : UPCONVERT -- NO IMMEDIATE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : F16C +ATTRIBUTES : MXCSR +EXCEPTIONS: avx-type-11 +# 128b form + +PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +OPERANDS : REG0=XMM_R():w:dq:f32 MEM0:r:q:f16 + +PATTERN : VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:q:f16 + + +# 256b form + +PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +OPERANDS : REG0=YMM_R():w:qq:f32 MEM0:r:dq:f16 + +PATTERN : VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f16 +} + + +{ +ICLASS : VCVTPS2PH +COMMENT : DOWNCONVERT -- HAS IMMEDIATE +CPL : 3 +CATEGORY : CONVERT +EXTENSION : F16C +ATTRIBUTES : MXCSR +EXCEPTIONS: avx-type-11 +# 128b imm8 form + +PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +OPERANDS : MEM0:w:q:f16 REG0=XMM_R():r:dq:f32 IMM0:r:b + +PATTERN : VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +OPERANDS : REG0=XMM_B():w:q:f16 REG1=XMM_R():r:dq:f32 IMM0:r:b + +# 256b imm8 form + +PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +OPERANDS : MEM0:w:dq:f16 REG0=YMM_R():r:qq:f32 IMM0:r:b + +PATTERN : VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +OPERANDS : REG0=XMM_B():w:dq:f16 REG1=YMM_R():r:qq:f32 IMM0:r:b + +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/avx-fma-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + +# Issues: encoder is at a loss for vmaddps xmm0,xmm0,xmm0,xmm0. +# Encoder must enforce equality between two parameters. Never had to do this before. +# Extra check? +# Decoder must rip off suffixes _DDMR, _DDRM, _DRMD in disassembly (eventually) +############################################################################################# +# Operand orders: +# A = B * C + D +#Type 1) reg0 reg0 mem/reg1 reg2 DDMR 312 or 132 +#Type 2) reg0 reg0 reg1 mem/reg2 DDRM 123 or 213 +#Type 3) reg0 reg1 mem/reg2 reg0 DRMD 321 or 231 + +# dst is in MODRM.REG +# regsrc is in VEX.vvvv +# memop is in MODRM.RM +############################################################################################ + + + + + + + + + + + + +########################################################## + + + + + + + + + + + + +################################################################## + + + + + + + + + + + + + +################################################################## +{ +ICLASS : VFMADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADD132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFMADD132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFMADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADD213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMADD213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFMADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFMADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFMADD231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMADD231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + + +################################################### +{ +ICLASS : VFMADDSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADDSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMADDSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} + +{ +ICLASS : VFMADDSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADDSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMADDSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +################################################### + +{ +ICLASS : VFMSUBADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUBADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUBADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} + +{ +ICLASS : VFMSUBADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUBADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUBADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} + + +################################################### + +{ +ICLASS : VFMSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUB132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFMSUB132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFMSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFMSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMSUB213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFMSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFMSUB231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + +{ +ICLASS : VFNMADD132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMADD132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMADD132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFNMADD132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFNMADD213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMADD213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMADD213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMADD213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMADD231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFNMADD231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFNMADD231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMADD231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + +{ +ICLASS : VFNMSUB132PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMSUB132PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMSUB132SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 +} +{ +ICLASS : VFNMSUB132SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +{ +ICLASS : VFNMSUB213PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 +} +{ +ICLASS : VFNMSUB213PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + + +# R/M 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} +{ +ICLASS : VFNMSUB213SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB213SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 +} + +{ +ICLASS : VFNMSUB231PD +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 MEM0:r:dq:f64 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:dq:f64 REG2=XMM_B():r:dq:f64 + + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 MEM0:r:qq:f64 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f64 REG1=YMM_N():r:qq:f64 REG2=YMM_B():r:qq:f64 + +} +{ +ICLASS : VFNMSUB231PS +EXCEPTIONS: avx-type-2 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR +# R/M 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 MEM0:r:dq:f32 +# R/R 128 +PATTERN : VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:dq:f32 REG2=XMM_B():r:dq:f32 + +# R/M 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 +# R/R 256 +PATTERN : VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():rw:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 + +} +{ +ICLASS : VFNMSUB231SD +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 MEM0:r:q:f64 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f64 REG1=XMM_N():r:q:f64 REG2=XMM_B():r:q:f64 + +} +{ +ICLASS : VFNMSUB231SS +EXCEPTIONS: avx-type-3 +CPL : 3 +CATEGORY : VFMA +EXTENSION : FMA +ATTRIBUTES: MXCSR simd_scalar +# R/M 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 MEM0:r:d:f32 +# R/R 128 +PATTERN : VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():rw:dq:f32 REG1=XMM_N():r:d:f32 REG2=XMM_B():r:d:f32 + +} + +################################################### + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/gather-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +# DEST in MODRM.REG +# BASE in SIB.base +# INDEX in SIB.index +# MASK in VEX.VVVV -- NOTE mask is a signed integer!!! + +# VL = 128 VL = 256 +# dest/mask index memsz dest/mask index memsz +# qps/qd xmm xmm 2*32=64b xmm* ymm* 4*32=128b +# dps/dd xmm xmm 4*32=128b ymm ymm 8*32=256b +# dpd/dq xmm xmm 2*64=128b ymm* xmm* 4*64=256b +# qpd/qq xmm xmm 2*64=128b ymm ymm 4*64=256b + + + +{ +ICLASS : VGATHERDPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERDPS +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f32 MEM0:r:d:f32 REG1=YMM_N():rw:qq:i32 +IFORM: VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERQPD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:f64 MEM0:r:q:f64 REG1=YMM_N():rw:qq:i64 +IFORM: VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f64 MEM0:r:q:f64 REG1=XMM_N():rw:dq:i64 +IFORM: VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VGATHERQPS +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:f32 MEM0:r:d:f32 REG1=XMM_N():rw:dq:i32 +IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:f32 MEM0:r:d:f32 REG1=XMM_N():rw:q:i32 +IFORM: VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} + +{ +ICLASS : VPGATHERDQ +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERDD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather DWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u32 MEM0:r:d:u32 REG1=YMM_N():rw:qq:i32 +IFORM: VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERQQ +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_q SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=YMM_R():crw:qq:u64 MEM0:r:q:u64 REG1=YMM_N():rw:qq:i64 +IFORM: VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u64 MEM0:r:q:u64 REG1=XMM_N():rw:dq:i64 +IFORM: VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} +{ +ICLASS : VPGATHERQD +CPL : 3 +CATEGORY : AVX2GATHER +EXTENSION : AVX2GATHER +ATTRIBUTES : gather QWORD_INDICES ELEMENT_SIZE_d SPECIAL_AGEN_REQUIRED +EXCEPTIONS: avx-type-12 + +# VL = 256 - when data/mask differ from index size see asterisks in above chart. +PATTERN : VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +OPERANDS : REG0=XMM_R():crw:dq:u32 MEM0:r:d:u32 REG1=XMM_N():rw:dq:i32 +IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 + +# VL = 128 - index, mask and dest are all XMMs +PATTERN : VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +OPERANDS : REG0=XMM_R():crw:q:u32 MEM0:r:d:u32 REG1=XMM_N():rw:q:i32 +IFORM: VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 + +COMMENT: mask reg is zeroized on normal termination. mask_sz=data_sz +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-int256-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VPABSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_B():r:qq:i8 +} +{ +ICLASS : VPABSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:i16 + +PATTERN : VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:i16 +} +{ +ICLASS : VPABSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:i32 + +PATTERN : VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:i32 +} + + + + + + + + + +{ +ICLASS : VPACKSSWB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPACKSSDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPACKUSWB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPACKUSDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPSLLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 +} + +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:dq:u64 + +PATTERN : VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:dq:u64 + +PATTERN : VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:dq:u64 + +PATTERN : VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=XMM_B():r:q:u64 +} + +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:dq:u64 + +PATTERN : VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=XMM_B():r:q:u64 +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:dq:u64 + +PATTERN : VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=XMM_B():r:q:u64 +} + + +{ +ICLASS : VPADDB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPADDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPADDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPADDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + +{ +ICLASS : VPADDSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPADDSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPADDUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPADDUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + +{ +ICLASS : VPAVGB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPAVGW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + + +{ +ICLASS : VPCMPEQB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPCMPEQW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPCMPEQD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPCMPEQQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + +{ +ICLASS : VPCMPGTB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPCMPGTW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPCMPGTD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPCMPGTQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + + +{ +ICLASS : VPHADDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHADDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHADDSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPHSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPHSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPMADDWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMADDUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:i8 + +PATTERN : VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:i8 +} + +{ +ICLASS : VPMAXSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPMAXSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMAXSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMAXUB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPMAXUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMAXUD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMINSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPMINSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMINSD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMINUB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPMINUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMINUD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} + +{ +ICLASS : VPMULHUW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPMULHRSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPMULHW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMULLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPMULLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPMULUDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPMULDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + +{ +ICLASS : VPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSHUFB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} + +{ +ICLASS : VPSIGNB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSIGNW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSIGND +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} + + +{ +ICLASS : VPSUBSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} + +{ +ICLASS : VPSUBUSB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPSUBUSW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} + +{ +ICLASS : VPSUBB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 MEM0:r:qq:i8 + +PATTERN : VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i8 REG1=YMM_N():r:qq:i8 REG2=YMM_B():r:qq:i8 +} +{ +ICLASS : VPSUBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 MEM0:r:qq:i16 + +PATTERN : VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=YMM_N():r:qq:i16 REG2=YMM_B():r:qq:i16 +} +{ +ICLASS : VPSUBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 MEM0:r:qq:i32 + +PATTERN : VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=YMM_N():r:qq:i32 REG2=YMM_B():r:qq:i32 +} +{ +ICLASS : VPSUBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 MEM0:r:qq:i64 + +PATTERN : VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=YMM_N():r:qq:i64 REG2=YMM_B():r:qq:i64 +} + +{ +ICLASS : VPUNPCKHBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKHWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKHDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKHQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + +{ +ICLASS : VPUNPCKLBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 + +PATTERN : VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +} +{ +ICLASS : VPUNPCKLWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 + +PATTERN : VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 +} +{ +ICLASS : VPUNPCKLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPUNPCKLQDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 + +PATTERN : VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 +} + + +{ +ICLASS : VPALIGNR +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b + +PATTERN : VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} +{ +ICLASS : VPBLENDW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u16 REG2=YMM_B():r:qq:u16 IMM0:r:b +} +{ +ICLASS : VMPSADBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b + +PATTERN : VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 IMM0:r:b +} + + + +{ +ICLASS : VPOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPAND +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPANDN +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} +{ +ICLASS : VPXOR +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 MEM0:r:qq:u256 + +PATTERN : VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u256 REG1=YMM_N():r:qq:u256 REG2=YMM_B():r:qq:u256 +} + + + +{ +ICLASS : VPBLENDVB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 REG2=YMM_SE():r:qq:u8 + +PATTERN : VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 REG3=YMM_SE():r:qq:u8 +} + + + + +{ +ICLASS : VPMOVMSKB +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPR32_R():w:d:u32 REG1=YMM_B():r:qq:i8 +} + + + +{ +ICLASS : VPSHUFD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:qq:u32 IMM0:r:b + +PATTERN : VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b +} +{ +ICLASS : VPSHUFHW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} +{ +ICLASS : VPSHUFLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:qq:u16 IMM0:r:b + +PATTERN : VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b +} + + + +{ +ICLASS : VPSRLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u128 REG1=YMM_B():r:qq:u128 IMM0:r:b # NDD +} + +############################################## + +{ +ICLASS : VPSLLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSLLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b #NDD +} +{ +ICLASS : VPSLLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} + +{ +ICLASS : VPSRAW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i16 REG1=YMM_B():r:qq:i16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRAD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:i32 REG1=YMM_B():r:qq:i32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u16 REG1=YMM_B():r:qq:u16 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 + +PATTERN : VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u32 REG1=YMM_B():r:qq:u32 IMM0:r:b # NDD +} +{ +ICLASS : VPSRLQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-7 +PATTERN : VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_N():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b # NDD +} + + + +############################################################################ +# SX versions +############################################################################ + +{ +ICLASS : VPMOVSXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i16 REG1=XMM_B():r:dq:i8 +PATTERN : VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i16 MEM0:r:dq:i8 +} + +############################################################################ +{ +ICLASS : VPMOVSXBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:q:i8 +PATTERN : VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:q:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:d:i8 +PATTERN : VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:d:i8 +} +############################################################################ +{ +ICLASS : VPMOVSXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i32 REG1=XMM_B():r:dq:i16 +PATTERN : VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i32 MEM0:r:dq:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:q:i16 +PATTERN : VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:q:i16 +} +############################################################################ +{ +ICLASS : VPMOVSXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:i64 REG1=XMM_B():r:dq:i32 +PATTERN : VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:i64 MEM0:r:dq:i32 +} + + + + + +############################################################################ +# ZX versions +############################################################################ + +{ +ICLASS : VPMOVZXBW +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:dq:u8 +PATTERN : VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:dq:u8 +} + +############################################################################ +{ +ICLASS : VPMOVZXBD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:q:u8 +PATTERN : VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:q:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXBQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:d:u8 +PATTERN : VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:d:u8 +} +############################################################################ +{ +ICLASS : VPMOVZXWD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:dq:u16 +PATTERN : VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:dq:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXWQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u16 +PATTERN : VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u16 +} +############################################################################ +{ +ICLASS : VPMOVZXDQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-5 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:dq:u32 +PATTERN : VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:dq:u32 +} + + +################################## +# newer stuff 2009-08-14 + + +{ +ICLASS : VINSERTI128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:dq:u128 IMM0:r:b + +PATTERN : VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=XMM_B():r:dq:u128 IMM0:r:b +} + + + + + +{ +ICLASS : VEXTRACTI128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : MEM0:w:dq:u128 REG0=YMM_R():r:qq:u128 IMM0:r:b + +PATTERN : VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_B():w:dq:u128 REG1=YMM_R():r:qq:u128 IMM0:r:b +} + + +########################################################################### + +### # VPMASKMOVD masked load and store +### # VPMASKMOVQ masked load and store + + + + +{ +ICLASS : VPMASKMOVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 + + +PATTERN : VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_N():r:dq:u64 MEM0:r:dq:u64 + + +PATTERN : VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 +} + +{ +ICLASS : VPMASKMOVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u32 REG0=XMM_N():r:dq:u32 REG1=XMM_R():r:dq:u32 + + +PATTERN : VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u32 REG0=YMM_N():r:qq:u32 REG1=YMM_R():r:qq:u32 +} +{ +ICLASS : VPMASKMOVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +ATTRIBUTES: maskop +EXCEPTIONS: avx-type-6 +PATTERN : VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:dq:u64 REG0=XMM_N():r:dq:u64 REG1=XMM_R():r:dq:u64 + + +PATTERN : VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : MEM0:w:qq:u64 REG0=YMM_N():r:qq:u64 REG1=YMM_R():r:qq:u64 +} +########################################################################### + + +### # VPERM2I128 256b only + +{ +ICLASS : VPERM2I128 +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 # Note: vperm2f128 is type 4... + +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 IMM0:r:b + +PATTERN : VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 IMM0:r:b +} + + +{ +ICLASS : VPERMQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:qq:u64 IMM0:r:b + +PATTERN : VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=YMM_B():r:qq:u64 IMM0:r:b +} + +{ +ICLASS : VPERMPD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 MEM0:r:qq:f64 IMM0:r:b + +PATTERN : VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=YMM_B():r:qq:f64 IMM0:r:b +} + + + + + + + + +{ +ICLASS : VPERMD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + + +PATTERN : VV1 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 + +PATTERN : VV1 0x36 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +} +{ +ICLASS : VPERMPS +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 MEM0:r:qq:f32 + +PATTERN : VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=YMM_N():r:qq:f32 REG2=YMM_B():r:qq:f32 +} + + +########################################################################### + + +### # VPBLENDD imm 128/256 + + + +{ +ICLASS : VPBLENDD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 + +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 IMM0:r:b + +PATTERN : VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 IMM0:r:b + + +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 IMM0:r:b + +PATTERN : VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 IMM0:r:b +} + + + +########################################################################### + +{ +ICLASS : VPBROADCASTB +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO16_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u8 MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 + +PATTERN : VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u8 REG1=XMM_B():r:b:u8 EMX_BROADCAST_1TO32_8 + +} + + + + +{ +ICLASS : VPBROADCASTW +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO8_16 + +PATTERN : VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO8_16 + +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u16 MEM0:r:w:u16 EMX_BROADCAST_1TO16_16 + +PATTERN : VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u16 REG1=XMM_B():r:w:u16 EMX_BROADCAST_1TO16_16 +} + + + + +### # VPBROADCASTD gpr/mem + + +{ +ICLASS : VPBROADCASTD +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO4_32 + + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u32 MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 + +PATTERN : VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u32 REG1=XMM_B():r:d:u32 EMX_BROADCAST_1TO8_32 +} + + + +### # VPBROADCASTQ gpr/mem + +{ +ICLASS : VPBROADCASTQ +COMMENT : gpr 128/256 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 + +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 + +PATTERN : VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO2_64 + +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u64 MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 + +PATTERN : VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:u64 REG1=XMM_B():r:q:u64 EMX_BROADCAST_1TO4_64 +} + + + + + + +{ +ICLASS : VBROADCASTSS +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : xmm,xmm and ymm,xmm +PATTERN : VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO4_32 + +PATTERN : VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f32 REG1=XMM_B():r:dq:f32 EMX_BROADCAST_1TO8_32 +} + + +{ +ICLASS : VBROADCASTSD +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : ymm,xmm only +PATTERN : VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq:f64 REG1=XMM_B():r:dq:f64 EMX_BROADCAST_1TO4_64 +} + + + +{ +ICLASS : VBROADCASTI128 +CPL : 3 +CATEGORY : BROADCAST +EXTENSION : AVX2 +EXCEPTIONS: avx-type-6 +COMMENT : memonly 256 -- FIXME: make types u64 like in AVX1? +PATTERN : VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq:u128 MEM0:r:dq:u128 EMX_BROADCAST_2TO4_64 +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-vshift-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + + + +{ +ICLASS : VPSLLVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} +{ +ICLASS : VPSLLVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + +{ +ICLASS : VPSRLVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} +{ +ICLASS : VPSRLVQ +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + +{ +ICLASS : VPSRAVD +CPL : 3 +CATEGORY : AVX2 +EXTENSION : AVX2 +EXCEPTIONS: avx-type-4 +PATTERN : VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq MEM0:r:dq + +PATTERN : VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS : REG0=XMM_R():w:dq REG1=XMM_N():r:dq REG2=XMM_B():r:dq + +PATTERN : VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq MEM0:r:qq + +PATTERN : VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS : REG0=YMM_R():w:qq REG1=YMM_N():r:qq REG2=YMM_B():r:qq + +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/movnt-load-isa.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +AVX_INSTRUCTIONS():: + + +{ +ICLASS : VMOVNTDQA +CPL : 3 +CATEGORY : DATAXFER +EXTENSION : AVX2 +EXCEPTIONS: avx-type-1 +ATTRIBUTES : REQUIRES_ALIGNMENT NOTSX NONTEMPORAL + +PATTERN : VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=YMM_R():w:qq MEM0:r:qq +} + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/hsw-bmi-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +AVX_INSTRUCTIONS():: + +{ +ICLASS : PDEP +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +#32b +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + +{ +ICLASS : PEXT +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + + +#32b +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + + +{ +ICLASS : ANDN +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] + +# 32b +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d MEM0:r:d + +PATTERN : VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +PATTERN : VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():r:d REG2=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q MEM0:r:q + +PATTERN : VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():r:q REG2=VGPR64_B():r:q +} + +{ +ICLASS : BLSR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] + +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q + +} + +{ +ICLASS : BLSMSK +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-0 af-u pf-u cf-mod ] + +#32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +#64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} + +{ +ICLASS : BLSI +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-0 ] + +# 32b +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_N():w:d MEM0:r:d + +PATTERN : VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +PATTERN : VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d + +# 64b +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_N():w:q MEM0:r:q + +PATTERN : VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +OPERANDS : REG0=VGPR64_N():w:q REG1=VGPR64_B():r:q +} + +{ +ICLASS : BZHI +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 +FLAGS : MUST [ of-0 sf-mod zf-mod af-u pf-u cf-mod ] + +# 32b +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + +{ +ICLASS : BEXTR +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] + +# 32b +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + + + +{ +ICLASS : SHLX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} +{ +ICLASS : SARX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} +{ +ICLASS : SHRX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# 32b +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d REG1=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +PATTERN : VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d REG2=VGPR32_N():r:d + +# 64b +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q REG1=VGPR64_N():r:q + +PATTERN : VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q REG2=VGPR64_N():r:q +} + + + +{ +ICLASS : MULX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# reg:w vvvv:w rm:r rdx:r +# 32b +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP + +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d REG2=VGPR32_B():r:d REG3=XED_REG_EDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP + +PATTERN : VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_N():w:d MEM0:r:d REG2=XED_REG_EDX:r:SUPP + +# 64b +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q REG2=VGPR64_B():r:q REG3=XED_REG_RDX:r:SUPP +PATTERN : VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_N():w:q MEM0:r:q REG2=XED_REG_RDX:r:SUPP +} + +{ +ICLASS : RORX +CPL : 3 +CATEGORY : BMI2 +EXTENSION : BMI2 + +# reg(w) rm(r) / vvvv must be 1111. / 2010-01-08 CART change + +# 32b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b + +PATTERN : VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:b + +# 64b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +OPERANDS : REG0=VGPR64_R():w:q REG1=VGPR64_B():r:q IMM0:r:b +PATTERN : VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +OPERANDS : REG0=VGPR64_R():w:q MEM0:r:q IMM0:r:b +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswbmi/tzcnt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : TZCNT +CPL : 3 +CATEGORY : BMI1 +EXTENSION : BMI1 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-mod ] +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w MEM0:r:v + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w REG1=GPRv_B():r +} + +{ +ICLASS : BSF +VERSION : 1 +COMMENT : AMD reused 0FBC for TZCNT and made BSF not have a refining prefix. This version replaces the normal version of BSF +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] + +PATTERN : 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/vmfunc-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : VMFUNC +CPL : 3 +CATEGORY : VTX +EXTENSION : VMFUNC +ISA_SET : VMFUNC +ATTRIBUTES : +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix +OPERANDS : REG0=XED_REG_EAX:r:SUPP +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/invpcid-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + + +{ +ICLASS : INVPCID +CPL : 0 +CATEGORY : MISC +EXTENSION : INVPCID +ISA_SET : INVPCID +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR64_R():r MEM0:r:dq +PATTERN : 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +OPERANDS : REG0=GPR32_R():r MEM0:r:dq +COMMENT : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/lzcnt-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +# LZCNT reg16, reg/mem16 F30FBD /r +# LZCNT reg32, reg/mem32 F30FBD /r +# LZCNT reg64, reg/mem64 F30FBD /r + +{ +ICLASS : LZCNT +# This replace the AMD version in LZCNT builds +VERSION : 2 +CPL : 3 +CATEGORY : LZCNT +EXTENSION : LZCNT +COMMENT : These next one WAS introduced first by AMD circa SSE4a. +FLAGS : MUST [ cf-mod zf-mod of-u af-u pf-u sf-u ] +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():w:v MEM0:r:v +PATTERN : 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():w:v REG1=GPRv_B():r:v +} + + +{ +ICLASS : BSR +VERSION : 2 +COMMENT : AMD reused 0FBD for LZCNT and made BSR not have a refining prefix. This version replaces the normal version of BSR +CPL : 3 +CATEGORY : BITBYTE +EXTENSION : BASE +ISA_SET : I386 +FLAGS : MUST [ of-u sf-u zf-mod af-u pf-u cf-u ] +PATTERN : 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS : REG0=GPRv_R():cw MEM0:r:v + +PATTERN : 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS : REG0=GPRv_R():cw REG1=GPRv_B():r +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hsw/rtm-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : XBEGIN +CPL : 3 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Not always a branch. If aborts, then branches & eax is written + +PATTERN : 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() +OPERANDS : RELBR:r:z REG0=rIP():rw:SUPP REG1=XED_REG_EAX:cw:SUPP +} + +{ +ICLASS : XEND +CPL : 3 +CATEGORY : COND_BR +EXTENSION : RTM +COMMENT : Transaction end. may branch +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix +OPERANDS : +} + +{ +ICLASS : XABORT +CPL : 3 +CATEGORY : UNCOND_BR +EXTENSION : RTM +COMMENT : Transaction abort. Branches. NOP outside of transaction; Thus eax is rcw. +PATTERN : 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() +OPERANDS : REG0=XED_REG_EAX:rcw:SUPP IMM0:r:b +} + + +{ +ICLASS : XTEST +CPL : 3 +CATEGORY : LOGICAL +EXTENSION : RTM +COMMENT : test if in RTM transaction mode +FLAGS : MUST [ of-0 sf-0 zf-mod af-0 pf-0 cf-0 ] +PATTERN : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix +OPERANDS : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/bdw/adox-adcx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +INSTRUCTIONS():: + +{ +ICLASS : ADCX +CPL : 3 +CATEGORY : ADOX_ADCX +EXTENSION : ADOX_ADCX +ISA_SET : ADOX_ADCX + +FLAGS : MUST [ cf-tst cf-mod ] + +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d + +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +} + + + +{ +ICLASS : ADOX +CPL : 3 +CATEGORY : ADOX_ADCX +EXTENSION : ADOX_ADCX +ISA_SET : ADOX_ADCX + +FLAGS : MUST [ of-tst of-mod ] + +# reg:rw rm:r +# 32b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d REG1=GPR32_B():r:d +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() +OPERANDS : REG0=GPR32_R():rw:d MEM0:r:d + +# 64b +PATTERN : 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q REG1=GPR64_B():r:q +PATTERN : 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() mode64 +OPERANDS : REG0=GPR64_R():rw:q MEM0:r:q +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pku/pku-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +INSTRUCTIONS():: + +{ +ICLASS: RDPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix +OPERANDS: REG0=XED_REG_EDX:w:SUPP REG1=XED_REG_EAX:w:SUPP REG2=XED_REG_ECX:r:SUPP +} + + +{ +ICLASS: WRPKRU +CPL: 3 +CATEGORY: PKU +EXTENSION: PKU +ISA_SET: PKU +ATTRIBUTES: +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix +OPERANDS: REG0=XED_REG_EDX:r:SUPP REG1=XED_REG_EAX:r:SUPP REG2=XED_REG_ECX:r:SUPP +} + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/clwb/clwb.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: + +{ +ICLASS: CLWB +CPL: 3 +CATEGORY: CLWB +EXTENSION: CLWB +ISA_SET: CLWB +ATTRIBUTES: PREFETCH # check TSX-friendlyness +PATTERN : 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +OPERANDS : MEM0:r:mprefetch +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vnni/vnni-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPDPBUSD (VPDPBUSD-128-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSD (VPDPBUSD-256-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSD (VPDPBUSD-512-1) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 +IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-128-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-256-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-512-1) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu32 +IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-128-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-256-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-512-1) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 +IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-128-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-256-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-512-1) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zu32 +IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VNNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-128-1) +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 +} + + +# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-256-1) +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 +} + + +# EMITTING VCVTNE2PS2BF16 (VCVTNE2PS2BF16-512-1) +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTNE2PS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zbf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-128-1) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-256-1) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VCVTNEPS2BF16 (VCVTNEPS2BF16-512-1) +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTNEPS2BF16 +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:bf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VDPBF16PS (VDPBF16PS-128-1) +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VDPBF16PS (VDPBF16PS-256-1) +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VDPBF16PS (VDPBF16PS-512-1) +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VDPBF16PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BF16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-fixup.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +UDELETE : PREFETCH_RESERVED_0F0Dr2 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knl/knl-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VEXP2PD (VEXP2PD-512-1) +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VEXP2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VEXP2PS (VEXP2PS-512-1) +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VEXP2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VGATHERPF0DPD (VGATHERPF0DPD-512-1) +{ +ICLASS: VGATHERPF0DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0DPS (VGATHERPF0DPS-512-1) +{ +ICLASS: VGATHERPF0DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPD (VGATHERPF0QPD-512-1) +{ +ICLASS: VGATHERPF0QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF0QPS (VGATHERPF0QPS-512-1) +{ +ICLASS: VGATHERPF0QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPD (VGATHERPF1DPD-512-1) +{ +ICLASS: VGATHERPF1DPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1DPS (VGATHERPF1DPS-512-1) +{ +ICLASS: VGATHERPF1DPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPD (VGATHERPF1QPD-512-1) +{ +ICLASS: VGATHERPF1QPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VGATHERPF1QPS (VGATHERPF1QPS-512-1) +{ +ICLASS: VGATHERPF1QPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES GATHER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VRCP28PD (VRCP28PD-512-1) +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRCP28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRCP28PS (VRCP28PS-512-1) +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRCP28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRCP28SD (VRCP28SD-128-1) +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRCP28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRCP28SS (VRCP28SS-128-1) +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRCP28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28PD (VRSQRT28PD-512-1) +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28PS (VRSQRT28PS-512-1) +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MASKOP_EVEX +PATTERN: EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER +} + + +# EMITTING VRSQRT28SD (VRSQRT28SD-128-1) +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER +} + +{ +ICLASS: VRSQRT28SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER +} + + +# EMITTING VRSQRT28SS (VRSQRT28SS-128-1) +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MASKOP_EVEX +PATTERN: EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER +} + +{ +ICLASS: VRSQRT28SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512ER_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_SCALAR +PATTERN: EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER +} + + +# EMITTING VSCATTERPF0DPD (VSCATTERPF0DPD-512-1) +{ +ICLASS: VSCATTERPF0DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0DPS (VSCATTERPF0DPS-512-1) +{ +ICLASS: VSCATTERPF0DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPD (VSCATTERPF0QPD-512-1) +{ +ICLASS: VSCATTERPF0QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF0QPS (VSCATTERPF0QPS-512-1) +{ +ICLASS: VSCATTERPF0QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPD (VSCATTERPF1DPD-512-1) +{ +ICLASS: VSCATTERPF1DPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1DPS (VSCATTERPF1DPS-512-1) +{ +ICLASS: VSCATTERPF1DPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED DWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPD (VSCATTERPF1QPD-512-1) +{ +ICLASS: VSCATTERPF1QPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:q:f64 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 +} + + +# EMITTING VSCATTERPF1QPS (VSCATTERPF1QPS-512-1) +{ +ICLASS: VSCATTERPF1QPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512PF_512 +EXCEPTIONS: AVX512-E12NP +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION SPECIAL_AGEN_REQUIRED QWORD_INDICES SCATTER PREFETCH MASKOP_EVEX DISP8_GSCAT +PATTERN: EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:r:d:f32 REG0=MASKNOT0():rw:mskw +IFORM: VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 +} + + +INSTRUCTIONS():: +# EMITTING PREFETCHWT1 (PREFETCHWT1-N/A-1) +{ +ICLASS: PREFETCHWT1 +CPL: 3 +CATEGORY: PREFETCHWT1 +EXTENSION: PREFETCHWT1 +ISA_SET: PREFETCHWT1 +REAL_OPCODE: Y +ATTRIBUTES: PREFETCH +PATTERN: 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +OPERANDS: MEM0:r:b:u8 +IFORM: PREFETCHWT1_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING V4FMADDPS (V4FMADDPS-512-1) +{ +ICLASS: V4FMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FMADDSS (V4FMADDSS-128-1) +{ +ICLASS: V4FMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDPS (V4FNMADDPS-512-1) +{ +ICLASS: V4FNMADDPS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MXCSR MASKOP_EVEX +PATTERN: EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING V4FNMADDSS (V4FNMADDSS-128-1) +{ +ICLASS: V4FNMADDSS +CPL: 3 +CATEGORY: AVX512_4FMAPS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4FMAPS_SCALAR +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1_4X MXCSR MULTISOURCE4 MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32:MULTISOURCE4 MEM0:r:dq:f32 +IFORM: V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VP4DPWSSD (VP4DPWSSD-512-1) +{ +ICLASS: VP4DPWSSD +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + +# EMITTING VP4DPWSSDS (VP4DPWSSDS-512-1) +{ +ICLASS: VP4DPWSSDS +CPL: 3 +CATEGORY: AVX512_4VNNIW +EXTENSION: AVX512EVEX +ISA_SET: AVX512_4VNNIW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MULTISOURCE4 DISP8_TUPLE1_4X MASKOP_EVEX +PATTERN: EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +OPERANDS: REG0=ZMM_R3():rw:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16:MULTISOURCE4 MEM0:r:dq:u32 +IFORM: VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-512/vpopcntdq-512-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-512-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-512-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-foundation-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-512-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-512-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDSD (VADDSD-128-1) +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDSS (VADDSS-128-1) +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-512-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-512-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-512-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-512-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-512-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X4 (VBROADCASTF64X4-512-1) +{ +ICLASS: VBROADCASTF64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-512-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO16_32 +IFORM: VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X4 (VBROADCASTI64X4-512-1) +{ +ICLASS: VBROADCASTI64X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 EMX_BROADCAST_4TO8_64 +IFORM: VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-512-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO8_64 +IFORM: VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-512-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO16_32 +IFORM: VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-512-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-512-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPSD (VCMPSD-128-1) +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPSS (VCMPSS-128-1) +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMISD (VCOMISD-128-1) +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCOMISS (VCOMISS-128-1) +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-512-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-512-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-512-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +COMMENT: ignores rc/sae. need to adjust VL to 512 +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-512-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-512-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-512-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-512-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-512-1) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f16 +IFORM: VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-512-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-512-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-1) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-512-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:f16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-512-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-1) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SI (VCVTSD2SI-128-2) +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2SS (VCVTSD2SS-128-1) +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-1) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTSD2USI (VCVTSD2USI-128-2) +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f64 +IFORM: VCVTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-1) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +COMMENT: Ignores rounding controls: 32b-INT-to-FP64 does not need rounding +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:i32 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SD (VCVTSI2SD-128-2) +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:i64 +IFORM: VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 +} + + +# EMITTING VCVTSI2SS (VCVTSI2SS-128-1) +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:i32 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SS (VCVTSI2SS-128-2) +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:i64 +IFORM: VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 +} +# EMITTING VCVTSS2SD (VCVTSS2SD-128-1) +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2SI (VCVTSS2SI-128-1) +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR32i32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2SI (VCVTSS2SI-128-2) +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTSS2SI_GPR64i64_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2USI (VCVTSS2USI-128-1) +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR32u32_MEMf32_AVX512 +} + + +# EMITTING VCVTSS2USI (VCVTSS2USI-128-2) +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f32 +IFORM: VCVTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTSS2USI_GPR64u64_MEMf32_AVX512 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-512-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-512-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-512-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-512-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-1) +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR32i32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR32i32_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2SI (VCVTTSD2SI-128-2) +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2SI_GPR64i64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:q:f64 +IFORM: VCVTTSD2SI_GPR64i64_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-1) +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR32u32_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR32u32_MEMf64_AVX512 +} + + +# EMITTING VCVTTSD2USI (VCVTTSD2USI-128-2) +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VCVTTSD2USI_GPR64u64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTSD2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_WRITER_LDOP_Q +PATTERN: EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:q:f64 +IFORM: VCVTTSD2USI_GPR64u64_MEMf64_AVX512 +} + + +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-1) +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR32i32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR32i32_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2SI (VCVTTSS2SI-128-2) +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2SI_GPR64i64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:d:f32 +IFORM: VCVTTSS2SI_GPR64i64_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-1) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR32u32_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR32u32_MEMf32_AVX512 +} + + +# EMITTING VCVTTSS2USI (VCVTTSS2USI-128-2) +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VCVTTSS2USI_GPR64u64_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTSS2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:d:f32 +IFORM: VCVTTSS2USI_GPR64u64_MEMf32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-512-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +COMMENT: ignores rc/sae. need to adjust VL to 512 +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-512-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-1) +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10NF +REAL_OPCODE: Y +ATTRIBUTES: SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:d:u32 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SD (VCVTUSI2SD-128-2) +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=XMM_N3():r:dq:f64 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:u64 +IFORM: VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 +} + + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-1) +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:u32 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SS (VCVTUSI2SS-128-2) +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=XMM_N3():r:dq:f32 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_GPR_READER +PATTERN: EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:u64 +IFORM: VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-512-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-512-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VDIVSD (VDIVSD-128-1) +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVSS (VDIVSS-128-1) +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-512-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-512-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-512-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-512-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-1) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-512-2) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-1) +{ +ICLASS: VEXTRACTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X4 (VEXTRACTF64X4-512-2) +{ +ICLASS: VEXTRACTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-1) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-512-2) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-1) +{ +ICLASS: VEXTRACTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X4 (VEXTRACTI64X4-512-2) +{ +ICLASS: VEXTRACTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTPS (VEXTRACTPS-128-1) +{ +ICLASS: VEXTRACTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:f32 REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VEXTRACTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:f32 REG0=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-512-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-512-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMSD (VFIXUPIMMSD-128-1) +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMSS (VFIXUPIMMSS-128-1) +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-512-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-512-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD132SD (VFMADD132SD-128-1) +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132SS (VFMADD132SS-128-1) +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-512-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-512-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213SD (VFMADD213SD-128-1) +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213SS (VFMADD213SS-128-1) +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-512-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-512-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231SD (VFMADD231SD-128-1) +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231SS (VFMADD231SS-128-1) +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-512-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-512-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-512-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-512-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-512-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-512-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-512-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-512-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132SD (VFMSUB132SD-128-1) +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132SS (VFMSUB132SS-128-1) +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-512-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-512-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213SD (VFMSUB213SD-128-1) +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213SS (VFMSUB213SS-128-1) +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-512-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-512-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231SD (VFMSUB231SD-128-1) +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231SS (VFMSUB231SS-128-1) +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-512-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-512-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-512-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-512-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-512-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-512-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-512-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-512-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132SD (VFNMADD132SD-128-1) +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132SS (VFNMADD132SS-128-1) +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-512-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-512-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213SD (VFNMADD213SD-128-1) +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213SS (VFNMADD213SS-128-1) +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-512-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-512-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231SD (VFNMADD231SD-128-1) +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231SS (VFNMADD231SS-128-1) +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-512-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-512-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132SD (VFNMSUB132SD-128-1) +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132SS (VFNMSUB132SS-128-1) +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-512-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-512-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213SD (VFNMSUB213SD-128-1) +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213SS (VFNMSUB213SS-128-1) +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-512-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():rw:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-512-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231SD (VFNMSUB231SD-128-1) +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231SD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231SS (VFNMSUB231SS-128-1) +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231SS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-512-1) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-512-1) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-512-1) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-512-1) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-512-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-512-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETEXPSD (VGETEXPSD-128-1) +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VGETEXPSS (VGETEXPSS-128-1) +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-512-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-512-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGETMANTSD (VGETMANTSD-128-1) +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTSS (VGETMANTSS-128-1) +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-512-1) +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X4 (VINSERTF64X4-512-1) +{ +ICLASS: VINSERTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:qq:f64 IMM0:r:b +IFORM: VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X4 (VINSERTI32X4-512-1) +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X4 (VINSERTI64X4-512-1) +{ +ICLASS: VINSERTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VINSERTPS (VINSERTPS-128-1) +{ +ICLASS: VINSERTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE1 +PATTERN: EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-512-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-512-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMAXSD (VMAXSD-128-1) +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXSS (VMAXSS-128-1) +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPD (VMINPD-512-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPS (VMINPS-512-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINSD (VMINSD-128-1) +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINSS (VMINSS-128-1) +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-512-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-512-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVD (VMOVD-128-1) +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=GPR32_B():r:d:u32 +IFORM: VMOVD_XMMu32_GPR32u32_AVX512 +} + +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:d:u32 +IFORM: VMOVD_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVD (VMOVD-128-2) +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 +IFORM: VMOVD_GPR32u32_XMMu32_AVX512 +} + +{ +ICLASS: VMOVD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVD_MEMu32_XMMu32_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-512-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-512-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-512-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-512-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-512-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VMOVHLPS (VMOVHLPS-128-1) +{ +ICLASS: VMOVHLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 REG2=XMM_B3():r:dq:f32 +IFORM: VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVHPD (VMOVHPD-128-1) +{ +ICLASS: VMOVHPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:q:f64 MEM0:r:q:f64 +IFORM: VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMOVHPD (VMOVHPD-128-2) +{ +ICLASS: VMOVHPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVHPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVHPS (VMOVHPS-128-1) +{ +ICLASS: VMOVHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 MEM0:r:q:f32 +IFORM: VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVHPS (VMOVHPS-128-2) +{ +ICLASS: VMOVHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVHPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVLHPS (VMOVLHPS-128-1) +{ +ICLASS: VMOVLHPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E7NM128 +REAL_OPCODE: Y +PATTERN: EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:q:f32 REG2=XMM_B3():r:q:f32 +IFORM: VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVLPD (VMOVLPD-128-1) +{ +ICLASS: VMOVLPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMOVLPD (VMOVLPD-128-2) +{ +ICLASS: VMOVLPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=XMM_R3():r:q:f64 +IFORM: VMOVLPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVLPS (VMOVLPS-128-1) +{ +ICLASS: VMOVLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=XMM_N3():r:dq:f32 MEM0:r:q:f32 +IFORM: VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVLPS (VMOVLPS-128-2) +{ +ICLASS: VMOVLPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_TUPLE2 +PATTERN: EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:q:f32 REG0=XMM_R3():r:q:f32 +IFORM: VMOVLPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-512-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u32 REG0=ZMM_R3():r:zu32 +IFORM: VMOVNTDQ_MEMu32_ZMMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-512-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu32 MEM0:r:zd:u32 +IFORM: VMOVNTDQA_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-512-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=ZMM_R3():r:zf64 +IFORM: VMOVNTPD_MEMf64_ZMMf64_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-512-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=ZMM_R3():r:zf32 +IFORM: VMOVNTPS_MEMf32_ZMMf32_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-1) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=GPR64_B():r:q:u64 +IFORM: VMOVQ_XMMu64_GPR64u64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-2) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_GPR64u64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-3) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_B3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:u64 MEM0:r:q:u64 +IFORM: VMOVQ_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VMOVQ (VMOVQ-128-4) +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=XMM_R3():r:dq:u64 +IFORM: VMOVQ_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VMOVQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR +PATTERN: EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 +IFORM: VMOVQ_MEMu64_XMMu64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-1) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-2) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:q:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-3) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVSD (VMOVSD-128-4) +{ +ICLASS: VMOVSD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_R3():r:dq:f64 +IFORM: VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-512-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-512-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-1) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-2) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:d:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-3) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVSS (VMOVSS-128-4) +{ +ICLASS: VMOVSS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_R3():r:dq:f32 +IFORM: VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 +IFORM: VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-512-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 +IFORM: VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:f32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 +IFORM: VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-512-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 +IFORM: VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 +} + + +# EMITTING VMULPD (VMULPD-512-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPS (VMULPS-512-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VMULSD (VMULSD-128-1) +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULSS (VMULSS-128-1) +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPABSD (VPABSD-512-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-512-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi64 +IFORM: VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPADDD (VPADDD-512-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-512-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDD (VPANDD-512-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-512-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-512-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-512-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-512-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-512-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-512-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO16_32 +IFORM: VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-512-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO8_64 +IFORM: VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-512-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-512-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-512-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-512-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-512-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-512-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-512-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-512-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-512-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-512-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPERMD (VPERMD-512-1) +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-512-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-512-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-512-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-512-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-512-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-512-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-512-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-512-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-512-1) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-512-2) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMPS (VPERMPS-512-1) +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-512-1) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-512-2) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-512-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-512-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-512-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-512-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-512-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-512-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-512-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-512-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-512-1) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-512-1) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-512-1) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-512-1) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VPMAXSD (VPMAXSD-512-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-512-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-512-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-512-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-512-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-512-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-512-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-512-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-512-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-512-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-512-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-512-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-512-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-512-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-512-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-512-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-512-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-512-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-512-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-512-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-512-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-512-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-512-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-512-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-512-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-512-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-512-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-512-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-512-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-512-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-512-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-512-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-512-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-512-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-512-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-512-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-512-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-512-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-512-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-512-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-512-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-512-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-512-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-512-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i32 +IFORM: VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-512-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-512-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-512-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 REG3=ZMM_B3():r:zi64 +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-512-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-512-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-512-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORQ (VPORQ-512-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLD (VPROLD-512-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-512-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-512-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-512-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORD (VPRORD-512-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-512-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-512-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-512-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-512-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-512-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-512-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-512-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zu64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 +} + + +# EMITTING VPSHUFD (VPSHUFD-512-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-512-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-512-2) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-512-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-512-2) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-512-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-512-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-512-2) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-512-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-512-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-512-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-512-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-512-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:dq:u32 +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-512-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-512-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-512-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_N3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-512-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-512-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-512-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-512-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-512-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-512-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-512-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-512-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-512-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-512-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-512-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-512-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-512-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-512-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPXORD (VPXORD-512-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-512-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-512-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-512-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRCP14SD (VRCP14SD-128-1) +{ +ICLASS: VRCP14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VRCP14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VRCP14SS (VRCP14SS-128-1) +{ +ICLASS: VRCP14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VRCP14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-512-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-512-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESD (VRNDSCALESD-128-1) +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESS (VRNDSCALESS-128-1) +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-512-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-512-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRSQRT14SD (VRSQRT14SD-128-1) +{ +ICLASS: VRSQRT14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14SD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14SS (VRSQRT14SS-128-1) +{ +ICLASS: VRSQRT14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14SS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-512-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-512-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFSD (VSCALEFSD-128-1) +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFSS (VSCALEFSS-128-1) +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-512-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-512-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-512-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=ZMM_R3():r:zf64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-512-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 +} + + +# EMITTING VSHUFF32X4 (VSHUFF32X4-512-1) +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFF64X2 (VSHUFF64X2-512-1) +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFI32X4 (VSHUFI32X4-512-1) +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VSHUFI64X2 (VSHUFI64X2-512-1) +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-512-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-512-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-512-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-512-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSQRTSD (VSQRTSD-128-1) +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSQRTSS (VSQRTSS-128-1) +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-512-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-512-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBSD (VSUBSD-128-1) +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBSS (VSUBSS-128-1) +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 +IFORM: VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUCOMISD (VUCOMISD-128-1) +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f64:TXT=SAESTR REG1=XMM_B3():r:dq:f64 +IFORM: VUCOMISD_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUCOMISD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f64 MEM0:r:q:f64 +IFORM: VUCOMISD_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUCOMISS (VUCOMISS-128-1) +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f32:TXT=SAESTR REG1=XMM_B3():r:dq:f32 +IFORM: VUCOMISS_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUCOMISS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-mod of-0 af-0 sf-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +OPERANDS: REG0=XMM_R3():r:dq:f32 MEM0:r:d:f32 +IFORM: VUCOMISS_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-512-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-512-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-512-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-512-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 +} + + +AVX_INSTRUCTIONS():: +# EMITTING KANDNW (KANDNW-256-1) +{ +ICLASS: KANDNW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDW (KANDW-256-1) +{ +ICLASS: KANDW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-1) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u16 +IFORM: KMOVW_MASKmskw_MASKu16_AVX512 +} + +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:wrd:u16 +IFORM: KMOVW_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-2) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: MEM0:w:wrd:u16 REG0=MASK_R():r:mskw +IFORM: KMOVW_MEMu16_MASKmskw_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-3) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVW_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVW (KMOVW-128-4) +{ +ICLASS: KMOVW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVW_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KNOTW (KNOTW-128-1) +{ +ICLASS: KNOTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTW (KORTESTW-128-1) +{ +ICLASS: KORTESTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORW (KORW-256-1) +{ +ICLASS: KORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KSHIFTLW (KSHIFTLW-128-1) +{ +ICLASS: KSHIFTLW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRW (KSHIFTRW-128-1) +{ +ICLASS: KSHIFTRW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KUNPCKBW (KUNPCKBW-256-1) +{ +ICLASS: KUNPCKBW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORW (KXNORW-256-1) +{ +ICLASS: KXNORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORW (KXORW-256-1) +{ +ICLASS: KXORW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512F_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512cd/vconflict-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-512-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO8_8 +IFORM: VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-512-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-512-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-512-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +} + + +# EMITTING VPLZCNTD (VPLZCNTD-512-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-512-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPD (VADDPD-128-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPD (VADDPD-256-1) +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VADDPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VADDPS (VADDPS-128-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VADDPS (VADDPS-256-1) +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VADDPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VALIGND (VALIGND-128-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGND (VALIGND-256-1) +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VALIGND +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-128-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VALIGNQ (VALIGNQ-256-1) +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VALIGNQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-128-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-256-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDNPD (VANDNPD-512-1) +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VANDNPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-128-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-256-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDNPS (VANDNPS-512-1) +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VANDNPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDPD (VANDPD-128-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDPD (VANDPD-256-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDPD (VANDPD-512-1) +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VANDPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VANDPS (VANDPS-128-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDPS (VANDPS-256-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VANDPS (VANDPS-512-1) +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VANDPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-128-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPD (VBLENDMPD-256-1) +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VBLENDMPD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-128-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VBLENDMPS (VBLENDMPS-256-1) +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VBLENDMPS +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-256-1) +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X2 (VBROADCASTF32X2-512-1) +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VBROADCASTF32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X4 (VBROADCASTF32X4-256-1) +{ +ICLASS: VBROADCASTF32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF32X8 (VBROADCASTF32X8-512-1) +{ +ICLASS: VBROADCASTF32X8 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-256-1) +{ +ICLASS: VBROADCASTF64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTF64X2 (VBROADCASTF64X2-512-1) +{ +ICLASS: VBROADCASTF64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-128-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO4_32 +IFORM: VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-256-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO8_32 +IFORM: VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X2 (VBROADCASTI32X2-512-1) +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VBROADCASTI32X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u32 EMX_BROADCAST_2TO16_32 +IFORM: VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X4 (VBROADCASTI32X4-256-1) +{ +ICLASS: VBROADCASTI32X4 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 EMX_BROADCAST_4TO8_32 +IFORM: VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI32X8 (VBROADCASTI32X8-512-1) +{ +ICLASS: VBROADCASTI32X8 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 EMX_BROADCAST_8TO16_32 +IFORM: VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-256-1) +{ +ICLASS: VBROADCASTI64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO4_64 +IFORM: VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTI64X2 (VBROADCASTI64X2-512-1) +{ +ICLASS: VBROADCASTI64X2 +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 EMX_BROADCAST_2TO8_64 +IFORM: VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-1) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VBROADCASTSD (VBROADCASTSD-256-2) +{ +ICLASS: VBROADCASTSD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 EMX_BROADCAST_1TO4_64 +IFORM: VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-128-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO4_32 +IFORM: VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-1) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VBROADCASTSS (VBROADCASTSS-256-2) +{ +ICLASS: VBROADCASTSS +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 EMX_BROADCAST_1TO8_32 +IFORM: VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-128-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPD (VCMPPD-256-1) +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VCMPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-128-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCMPPS (VCMPPS-256-1) +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VCMPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-128-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-1) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPD (VCOMPRESSPD-256-2) +{ +ICLASS: VCOMPRESSPD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-128-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-1) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VCOMPRESSPS (VCOMPRESSPS-256-2) +{ +ICLASS: VCOMPRESSPS +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-128-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PD (VCVTDQ2PD-256-1) +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-128-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTDQ2PS (VCVTDQ2PS-256-1) +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-128-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2DQ (VCVTPD2DQ-256-1) +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-128-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2PS (VCVTPD2PS-256-1) +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-128-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-256-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2QQ (VCVTPD2QQ-512-1) +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-128-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2UDQ (VCVTPD2UDQ-256-1) +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-128-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-256-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPD2UQQ (VCVTPD2UQQ-512-1) +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-128-2) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f16 +IFORM: VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PS (VCVTPH2PS-256-2) +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f16 +IFORM: VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-128-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2DQ (VCVTPS2DQ-256-1) +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-128-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PD (VCVTPS2PD-256-1) +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-128-3) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-2) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2PH (VCVTPS2PH-256-3) +{ +ICLASS: VCVTPS2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E11 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR DISP8_HALFMEM +PATTERN: EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:f16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-128-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-256-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2QQ (VCVTPS2QQ-512-1) +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-128-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UDQ (VCVTPS2UDQ-256-1) +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-128-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-256-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTPS2UQQ (VCVTPS2UQQ-512-1) +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-128-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-256-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PD (VCVTQQ2PD-512-1) +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND() +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-128-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-256-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTQQ2PS (VCVTQQ2PS-512-1) +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-128-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTTPD2DQ (VCVTTPD2DQ-256-1) +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTTPD2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-128-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-256-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2QQ (VCVTTPD2QQ-512-1) +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-128-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTTPD2UDQ (VCVTTPD2UDQ-256-1) +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 +} + +{ +ICLASS: VCVTTPD2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-128-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-256-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPD2UQQ (VCVTTPD2UQQ-512-1) +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTTPD2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-128-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2DQ (VCVTTPS2DQ-256-1) +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-128-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-256-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2QQ (VCVTTPS2QQ-512-1) +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-128-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UDQ (VCVTTPS2UDQ-256-1) +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-128-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-256-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTTPS2UQQ (VCVTTPS2UQQ-512-1) +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTTPS2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-128-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PD (VCVTUDQ2PD-256-1) +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALF BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-128-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUDQ2PS (VCVTUDQ2PS-256-1) +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-128-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-256-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PD (VCVTUQQ2PD-512-1) +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-128-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-256-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTUQQ2PS (VCVTUQQ2PS-512-1) +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 +} + +{ +ICLASS: VCVTUQQ2PS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-128-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-256-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDBPSADBW (VDBPSADBW-512-1) +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VDBPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-128-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPD (VDIVPD-256-1) +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VDIVPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-128-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VDIVPS (VDIVPS-256-1) +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VDIVPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-128-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-128-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-256-1) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VEXPANDPD (VEXPANDPD-256-2) +{ +ICLASS: VEXPANDPD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-128-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-128-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-256-1) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VEXPANDPS (VEXPANDPS-256-2) +{ +ICLASS: VEXPANDPS +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-1) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X4 (VEXTRACTF32X4-256-2) +{ +ICLASS: VEXTRACTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 IMM0:r:b +IFORM: VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-1) +{ +ICLASS: VEXTRACTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF32X8 (VEXTRACTF32X8-512-2) +{ +ICLASS: VEXTRACTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf32 IMM0:r:b +IFORM: VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-1) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-256-2) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-1) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTF64X2 (VEXTRACTF64X2-512-2) +{ +ICLASS: VEXTRACTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zf64 IMM0:r:b +IFORM: VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-1) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X4 (VEXTRACTI32X4-256-2) +{ +ICLASS: VEXTRACTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 IMM0:r:b +IFORM: VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-1) +{ +ICLASS: VEXTRACTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI32X8 (VEXTRACTI32X8-512-2) +{ +ICLASS: VEXTRACTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu32 IMM0:r:b +IFORM: VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-1) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-256-2) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-1) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VEXTRACTI64X2 (VEXTRACTI64X2-512-2) +{ +ICLASS: VEXTRACTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu64 IMM0:r:b +IFORM: VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-128-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPD (VFIXUPIMMPD-256-1) +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-128-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFIXUPIMMPS (VFIXUPIMMPS-256-1) +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFIXUPIMMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-128-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PD (VFMADD132PD-256-1) +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-128-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD132PS (VFMADD132PS-256-1) +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-128-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PD (VFMADD213PD-256-1) +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-128-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD213PS (VFMADD213PS-256-1) +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-128-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PD (VFMADD231PD-256-1) +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-128-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADD231PS (VFMADD231PS-256-1) +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-128-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PD (VFMADDSUB132PD-256-1) +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-128-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB132PS (VFMADDSUB132PS-256-1) +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-128-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PD (VFMADDSUB213PD-256-1) +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-128-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB213PS (VFMADDSUB213PS-256-1) +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-128-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PD (VFMADDSUB231PD-256-1) +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMADDSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-128-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMADDSUB231PS (VFMADDSUB231PS-256-1) +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMADDSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-128-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PD (VFMSUB132PD-256-1) +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-128-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB132PS (VFMSUB132PS-256-1) +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-128-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PD (VFMSUB213PD-256-1) +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-128-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB213PS (VFMSUB213PS-256-1) +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-128-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PD (VFMSUB231PD-256-1) +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-128-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUB231PS (VFMSUB231PS-256-1) +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-128-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PD (VFMSUBADD132PD-256-1) +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-128-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD132PS (VFMSUBADD132PS-256-1) +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-128-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PD (VFMSUBADD213PD-256-1) +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-128-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD213PS (VFMSUBADD213PS-256-1) +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-128-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PD (VFMSUBADD231PD-256-1) +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFMSUBADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-128-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFMSUBADD231PS (VFMSUBADD231PS-256-1) +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFMSUBADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-128-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PD (VFNMADD132PD-256-1) +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-128-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD132PS (VFNMADD132PS-256-1) +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-128-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PD (VFNMADD213PD-256-1) +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-128-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD213PS (VFNMADD213PS-256-1) +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-128-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PD (VFNMADD231PD-256-1) +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMADD231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-128-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMADD231PS (VFNMADD231PS-256-1) +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMADD231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-128-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PD (VFNMSUB132PD-256-1) +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB132PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-128-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB132PS (VFNMSUB132PS-256-1) +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB132PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-128-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PD (VFNMSUB213PD-256-1) +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB213PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-128-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB213PS (VFNMSUB213PS-256-1) +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB213PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-128-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PD (VFNMSUB231PD-256-1) +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VFNMSUB231PD +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-128-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VFNMSUB231PS (VFNMSUB231PS-256-1) +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VFNMSUB231PS +CPL: 3 +CATEGORY: VFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-128-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-256-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 +} + + +# EMITTING VFPCLASSPD (VFPCLASSPD-512-1) +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-128-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-256-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 +} + + +# EMITTING VFPCLASSPS (VFPCLASSPS-512-1) +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 +} + + +# EMITTING VFPCLASSSD (VFPCLASSSD-128-1) +{ +ICLASS: VFPCLASSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:q:f64 IMM0:r:b +IFORM: VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VFPCLASSSS (VFPCLASSSS-128-1) +{ +ICLASS: VFPCLASSSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:d:f32 IMM0:r:b +IFORM: VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-128-2) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VGATHERDPD (VGATHERDPD-256-2) +{ +ICLASS: VGATHERDPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-128-2) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VGATHERDPS (VGATHERDPS-256-2) +{ +ICLASS: VGATHERDPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-128-2) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VGATHERQPD (VGATHERQPD-256-2) +{ +ICLASS: VGATHERQPD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASKNOT0():rw:mskw MEM0:r:q:f64 +IFORM: VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-128-2) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VGATHERQPS (VGATHERQPS-256-2) +{ +ICLASS: VGATHERQPS +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASKNOT0():rw:mskw MEM0:r:d:f32 +IFORM: VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-128-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPD (VGETEXPPD-256-1) +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VGETEXPPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-128-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETEXPPS (VGETEXPPS-256-1) +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VGETEXPPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-128-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPD (VGETMANTPD-256-1) +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-128-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VGETMANTPS (VGETMANTPS-256-1) +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X4 (VINSERTF32X4-256-1) +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:dq:f32 IMM0:r:b +IFORM: VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF32X8 (VINSERTF32X8-512-1) +{ +ICLASS: VINSERTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:qq:f32 IMM0:r:b +IFORM: VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X2 (VINSERTF64X2-256-1) +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTF64X2 (VINSERTF64X2-512-1) +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:dq:f64 IMM0:r:b +IFORM: VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X4 (VINSERTI32X4-256-1) +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE4 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 IMM0:r:b +IFORM: VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI32X8 (VINSERTI32X8-512-1) +{ +ICLASS: VINSERTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI32X8 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE8 +PATTERN: EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:qq:u32 IMM0:r:b +IFORM: VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X2 (VINSERTI64X2-256-1) +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VINSERTI64X2 (VINSERTI64X2-512-1) +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VINSERTI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_TUPLE2 +PATTERN: EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-128-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPD (VMAXPD-256-1) +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMAXPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-128-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMAXPS (VMAXPS-256-1) +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMAXPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPD (VMINPD-128-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPD (VMINPD-256-1) +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMINPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMINPS (VMINPS-128-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMINPS (VMINPS-256-1) +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMINPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-128-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-1) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-2) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVAPD (VMOVAPD-256-3) +{ +ICLASS: VMOVAPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-128-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-1) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-2) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVAPS (VMOVAPS-256-3) +{ +ICLASS: VMOVAPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-128-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:f64 +IFORM: VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDDUP (VMOVDDUP-256-1) +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVDDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MOVDDUP +PATTERN: EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-128-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-1) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-2) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQA32 (VMOVDQA32-256-3) +{ +ICLASS: VMOVDQA32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-128-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-1) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-2) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQA64 (VMOVDQA64-256-3) +{ +ICLASS: VMOVDQA64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX REQUIRES_ALIGNMENT DISP8_FULLMEM +PATTERN: EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-128-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-256-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-1) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-2) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VMOVDQU16 (VMOVDQU16-512-3) +{ +ICLASS: VMOVDQU16 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-128-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-1) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-2) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQU32 (VMOVDQU32-256-3) +{ +ICLASS: VMOVDQU32 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-128-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-1) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-2) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU64 (VMOVDQU64-256-3) +{ +ICLASS: VMOVDQU64 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-128-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-256-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-1) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-2) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VMOVDQU8 (VMOVDQU8-512-3) +{ +ICLASS: VMOVDQU8 +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-128-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:u32 REG0=XMM_R3():r:dq:u32 +IFORM: VMOVNTDQ_MEMu32_XMMu32_AVX512 +} + + +# EMITTING VMOVNTDQ (VMOVNTDQ-256-1) +{ +ICLASS: VMOVNTDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:u32 REG0=YMM_R3():r:qq:u32 +IFORM: VMOVNTDQ_MEMu32_YMMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-128-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u32 MEM0:r:dq:u32 +IFORM: VMOVNTDQA_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTDQA (VMOVNTDQA-256-1) +{ +ICLASS: VMOVNTDQA +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u32 MEM0:r:qq:u32 +IFORM: VMOVNTDQA_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-128-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=XMM_R3():r:dq:f64 +IFORM: VMOVNTPD_MEMf64_XMMf64_AVX512 +} + + +# EMITTING VMOVNTPD (VMOVNTPD-256-1) +{ +ICLASS: VMOVNTPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=YMM_R3():r:qq:f64 +IFORM: VMOVNTPD_MEMf64_YMMf64_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-128-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=XMM_R3():r:dq:f32 +IFORM: VMOVNTPS_MEMf32_XMMf32_AVX512 +} + + +# EMITTING VMOVNTPS (VMOVNTPS-256-1) +{ +ICLASS: VMOVNTPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E1NF +REAL_OPCODE: Y +ATTRIBUTES: NOTSX REQUIRES_ALIGNMENT DISP8_FULLMEM NONTEMPORAL +PATTERN: EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=YMM_R3():r:qq:f32 +IFORM: VMOVNTPS_MEMf32_YMMf32_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-128-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSHDUP (VMOVSHDUP-256-1) +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVSHDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-128-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVSLDUP (VMOVSLDUP-256-1) +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVSLDUP +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-128-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-1) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-2) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVUPD (VMOVUPD-256-3) +{ +ICLASS: VMOVUPD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-128-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:dq:f32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-1) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-2) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMOVUPS (VMOVUPS-256-3) +{ +ICLASS: VMOVUPS +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +OPERANDS: MEM0:w:qq:f32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 +} + + +# EMITTING VMULPD (VMULPD-128-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPD (VMULPD-256-1) +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VMULPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VMULPS (VMULPS-128-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VMULPS (VMULPS-256-1) +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VMULPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VORPD (VORPD-128-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VORPD (VORPD-256-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VORPD (VORPD-512-1) +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VORPS (VORPS-128-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VORPS (VORPS-256-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VORPS (VORPS-512-1) +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPABSB (VPABSB-128-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSB (VPABSB-256-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSB (VPABSB-512-1) +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi8 +IFORM: VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 +} + +{ +ICLASS: VPABSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i8 +IFORM: VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPABSD (VPABSD-128-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSD (VPABSD-256-1) +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VPABSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-128-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i64 +IFORM: VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPABSQ (VPABSQ-256-1) +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i64 +IFORM: VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 +} + +{ +ICLASS: VPABSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 +} + + +# EMITTING VPABSW (VPABSW-128-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPABSW (VPABSW-256-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i16 +IFORM: VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPABSW (VPABSW-512-1) +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VPABSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:i16 +IFORM: VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-128-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-256-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSDW (VPACKSSDW-512-1) +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 REG3=ZMM_B3():r:zi32 +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 +} + +{ +ICLASS: VPACKSSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-128-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-256-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKSSWB (VPACKSSWB-512-1) +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPACKSSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-128-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-256-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSDW (VPACKUSDW-512-1) +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPACKUSDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-128-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-256-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPACKUSWB (VPACKUSWB-512-1) +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPACKUSWB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDB (VPADDB-128-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDB (VPADDB-256-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDB (VPADDB-512-1) +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPADDB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDD (VPADDD-128-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDD (VPADDD-256-1) +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPADDD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-128-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPADDQ (VPADDQ-256-1) +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPADDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-128-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-256-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSB (VPADDSB-512-1) +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPADDSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-128-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-256-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDSW (VPADDSW-512-1) +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPADDSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-128-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-256-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSB (VPADDUSB-512-1) +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPADDUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-128-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-256-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDUSW (VPADDUSW-512-1) +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPADDUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-128-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-256-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPADDW (VPADDW-512-1) +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPADDW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-128-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-256-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPALIGNR (VPALIGNR-512-1) +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPALIGNR +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPANDD (VPANDD-128-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDD (VPANDD-256-1) +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPANDD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-128-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDND (VPANDND-256-1) +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPANDND +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-128-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDNQ (VPANDNQ-256-1) +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPANDNQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-128-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPANDQ (VPANDQ-256-1) +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPANDQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-128-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-256-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGB (VPAVGB-512-1) +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPAVGB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-128-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-256-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPAVGW (VPAVGW-512-1) +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPAVGW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-128-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-256-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMB (VPBLENDMB-512-1) +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPBLENDMB +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-128-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMD (VPBLENDMD-256-1) +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPBLENDMD +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-128-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMQ (VPBLENDMQ-256-1) +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPBLENDMQ +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED MASK_AS_CONTROL +PATTERN: EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-128-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-256-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBLENDMW (VPBLENDMW-512-1) +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPBLENDMW +CPL: 3 +CATEGORY: BLEND +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM MASK_AS_CONTROL +PATTERN: EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-128-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-128-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO16_8 +IFORM: VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-256-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO32_8 +IFORM: VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-512-1) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_BYTE +PATTERN: EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:b:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPBROADCASTB (VPBROADCASTB-512-2) +{ +ICLASS: VPBROADCASTB +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u8 EMX_BROADCAST_1TO64_8 +IFORM: VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-128-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO4_32 +IFORM: VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-1) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-2) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPBROADCASTD (VPBROADCASTD-256-3) +{ +ICLASS: VPBROADCASTD +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u32 EMX_BROADCAST_1TO8_32 +IFORM: VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-128-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO2_8 +IFORM: VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 +} + + +# EMITTING VPBROADCASTMB2Q (VPBROADCASTMB2Q-256-1) +{ +ICLASS: VPBROADCASTMB2Q +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw:u64 EMX_BROADCAST_1TO4_8 +IFORM: VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-128-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO4_16 +IFORM: VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 +} + + +# EMITTING VPBROADCASTMW2D (VPBROADCASTMW2D-256-1) +{ +ICLASS: VPBROADCASTMW2D +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +PATTERN: EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw:u32 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-128-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO2_64 +IFORM: VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-1) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1 +PATTERN: EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-2) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPBROADCASTQ (VPBROADCASTQ-256-3) +{ +ICLASS: VPBROADCASTQ +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR64_B():r:q:u64 EMX_BROADCAST_1TO4_64 +IFORM: VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-128-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO8_16 +IFORM: VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-256-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-256-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO16_16 +IFORM: VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-1) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_TUPLE1_WORD +PATTERN: EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPBROADCASTW (VPBROADCASTW-512-2) +{ +ICLASS: VPBROADCASTW +CPL: 3 +CATEGORY: BROADCAST +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=GPR32_B():r:d:u16 EMX_BROADCAST_1TO32_16 +IFORM: VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-128-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-256-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPB (VPCMPB-512-1) +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 IMM0:r:b +IFORM: VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-128-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPD (VPCMPD-256-1) +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-128-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-256-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQB (VPCMPEQB-512-1) +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPCMPEQB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-128-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQD (VPCMPEQD-256-1) +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPCMPEQD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-128-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPEQQ (VPCMPEQQ-256-1) +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPCMPEQQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-128-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-256-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPEQW (VPCMPEQW-512-1) +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPCMPEQW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-128-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-256-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTB (VPCMPGTB-512-1) +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPCMPGTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-128-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTD (VPCMPGTD-256-1) +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPCMPGTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-128-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPGTQ (VPCMPGTQ-256-1) +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPCMPGTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-128-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-256-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPGTW (VPCMPGTW-512-1) +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPCMPGTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-128-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPQ (VPCMPQ-256-1) +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-128-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-256-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUB (VPCMPUB-512-1) +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-128-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUD (VPCMPUD-256-1) +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-128-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCMPUQ (VPCMPUQ-256-1) +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-128-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-256-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPUW (VPCMPUW-512-1) +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-128-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-256-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCMPW (VPCMPW-512-1) +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 +} + +{ +ICLASS: VPCMPW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 IMM0:r:b +IFORM: VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-128-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-1) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSD (VPCOMPRESSD-256-2) +{ +ICLASS: VPCOMPRESSD +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u64 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-128-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-1) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u64 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPCOMPRESSQ (VPCOMPRESSQ-256-2) +{ +ICLASS: VPCOMPRESSQ +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-128-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPCONFLICTD (VPCONFLICTD-256-1) +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPCONFLICTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-128-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPCONFLICTQ (VPCONFLICTQ-256-1) +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPCONFLICTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPERMD (VPERMD-256-1) +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-128-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2D (VPERMI2D-256-1) +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMI2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-128-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PD (VPERMI2PD-256-1) +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMI2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-128-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2PS (VPERMI2PS-256-1) +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMI2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-128-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMI2Q (VPERMI2Q-256-1) +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMI2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-128-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-256-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMI2W (VPERMI2W-512-1) +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMI2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-128-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-128-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-256-1) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMILPD (VPERMILPD-256-2) +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMILPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-128-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-128-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-256-1) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VPERMILPS (VPERMILPS-256-2) +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMILPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-256-1) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VPERMPD (VPERMPD-256-2) +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMPS (VPERMPS-256-1) +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-256-1) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPERMQ (VPERMQ-256-2) +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-128-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2D (VPERMT2D-256-1) +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPERMT2D +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-128-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PD (VPERMT2PD-256-1) +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VPERMT2PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-128-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2PS (VPERMT2PS-256-1) +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VPERMT2PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-128-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2Q (VPERMT2Q-256-1) +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPERMT2Q +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-128-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-256-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMT2W (VPERMT2W-512-1) +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMT2W +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-128-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-256-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPERMW (VPERMW-512-1) +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPERMW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-128-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-256-1) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPEXPANDD (VPEXPANDD-256-2) +{ +ICLASS: VPEXPANDD +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-128-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-1) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPEXPANDQ (VPEXPANDQ-256-2) +{ +ICLASS: VPEXPANDQ +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPEXTRB (VPEXTRB-128-1) +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u8 REG1=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE_BYTE +PATTERN: EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() +OPERANDS: MEM0:w:b:u8 REG0=XMM_R3():r:dq:u8 IMM0:r:b +IFORM: VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 +} + + +# EMITTING VPEXTRD (VPEXTRD-128-1) +{ +ICLASS: VPEXTRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u32 REG1=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:d:u32 REG0=XMM_R3():r:dq:u32 IMM0:r:b +IFORM: VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 +} + + +# EMITTING VPEXTRQ (VPEXTRQ-128-1) +{ +ICLASS: VPEXTRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR64_B():w:q:u64 REG1=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:q:u64 REG0=XMM_R3():r:dq:u64 IMM0:r:b +IFORM: VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 +} + + +# EMITTING VPEXTRW (VPEXTRW-128-1) +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=GPR32_B():w:d:u16 REG1=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPEXTRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE_WORD +PATTERN: EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() +OPERANDS: MEM0:w:wrd:u16 REG0=XMM_R3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 +} + + +# EMITTING VPEXTRW (VPEXTRW-128-2) +{ +ICLASS: VPEXTRW_C5 +DISASM: vpextrw +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64 +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 + +PATTERN: EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u16 REG1=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-128-2) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VPGATHERDD (VPGATHERDD-256-2) +{ +ICLASS: VPGATHERDD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-128-2) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERDQ (VPGATHERDQ-256-2) +{ +ICLASS: VPGATHERDQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES GATHER DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-128-2) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VPGATHERQD (VPGATHERQD-256-2) +{ +ICLASS: VPGATHERQD +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASKNOT0():rw:mskw MEM0:r:d:u32 +IFORM: VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-128-2) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VPGATHERQQ (VPGATHERQQ-256-2) +{ +ICLASS: VPGATHERQQ +CPL: 3 +CATEGORY: GATHER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: GATHER QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED +PATTERN: EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASKNOT0():rw:mskw MEM0:r:q:u64 +IFORM: VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VPINSRB (VPINSRB-128-1) +{ +ICLASS: VPINSRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 REG2=GPR32_B():r:d:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 +} + +{ +ICLASS: VPINSRB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER_BYTE +PATTERN: EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=XMM_N3():r:dq:u8 MEM0:r:b:u8 IMM0:r:b +IFORM: VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPINSRD (VPINSRD-128-1) +{ +ICLASS: VPINSRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 REG2=GPR32_B():r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 +} + +{ +ICLASS: VPINSRD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=XMM_N3():r:dq:u32 MEM0:r:d:u32 IMM0:r:b +IFORM: VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPINSRQ (VPINSRQ-128-1) +{ +ICLASS: VPINSRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 REG2=GPR64_B():r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 +} + +{ +ICLASS: VPINSRQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=XMM_N3():r:dq:u64 MEM0:r:q:u64 IMM0:r:b +IFORM: VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPINSRW (VPINSRW-128-1) +{ +ICLASS: VPINSRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 REG2=GPR32_B():r:d:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 +} + +{ +ICLASS: VPINSRW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER_WORD +PATTERN: EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u16 MEM0:r:wrd:u16 IMM0:r:b +IFORM: VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPLZCNTD (VPLZCNTD-128-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPLZCNTD (VPLZCNTD-256-1) +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPLZCNTD +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-128-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPLZCNTQ (VPLZCNTQ-256-1) +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPLZCNTQ +CPL: 3 +CATEGORY: CONFLICT +EXTENSION: AVX512EVEX +ISA_SET: AVX512CD_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-128-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-256-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDUBSW (VPMADDUBSW-512-1) +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMADDUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-128-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-256-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMADDWD (VPMADDWD-512-1) +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMADDWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-128-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-256-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSB (VPMAXSB-512-1) +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPMAXSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMAXSD (VPMAXSD-128-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSD (VPMAXSD-256-1) +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMAXSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-128-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXSQ (VPMAXSQ-256-1) +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMAXSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-128-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-256-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXSW (VPMAXSW-512-1) +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMAXSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-128-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-256-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUB (VPMAXUB-512-1) +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPMAXUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-128-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUD (VPMAXUD-256-1) +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMAXUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-128-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUQ (VPMAXUQ-256-1) +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMAXUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-128-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-256-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMAXUW (VPMAXUW-512-1) +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMAXUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-128-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-256-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSB (VPMINSB-512-1) +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPMINSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-128-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 REG3=XMM_B3():r:dq:i32 +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSD (VPMINSD-256-1) +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 REG3=YMM_B3():r:qq:i32 +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMINSD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i32 MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-128-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSQ (VPMINSQ-256-1) +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 +} + +{ +ICLASS: VPMINSQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-128-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-256-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINSW (VPMINSW-512-1) +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMINSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-128-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-256-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUB (VPMINUB-512-1) +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPMINUB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-128-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUD (VPMINUD-256-1) +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMINUD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-128-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINUQ (VPMINUQ-256-1) +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMINUQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-128-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-256-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMINUW (VPMINUW-512-1) +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMINUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-128-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u8 +IFORM: VPMOVB2M_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-256-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u8 +IFORM: VPMOVB2M_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPMOVB2M (VPMOVB2M-512-1) +{ +ICLASS: VPMOVB2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu8 +IFORM: VPMOVB2M_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-128-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u32 +IFORM: VPMOVD2M_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-256-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u32 +IFORM: VPMOVD2M_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVD2M (VPMOVD2M-512-1) +{ +ICLASS: VPMOVD2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu32 +IFORM: VPMOVD2M_MASKmskw_ZMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-128-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-128-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-1) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDB (VPMOVDB-256-2) +{ +ICLASS: VPMOVDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-128-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-128-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-256-1) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVDW (VPMOVDW-256-2) +{ +ICLASS: VPMOVDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-128-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_XMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-256-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_YMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2B (VPMOVM2B-512-1) +{ +ICLASS: VPMOVM2B +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK_B():r:mskw +IFORM: VPMOVM2B_ZMMu8_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-128-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_XMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-256-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_YMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2D (VPMOVM2D-512-1) +{ +ICLASS: VPMOVM2D +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK_B():r:mskw +IFORM: VPMOVM2D_ZMMu32_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-128-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_XMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-256-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_YMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2Q (VPMOVM2Q-512-1) +{ +ICLASS: VPMOVM2Q +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK_B():r:mskw +IFORM: VPMOVM2Q_ZMMu64_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-128-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_XMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-256-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_YMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVM2W (VPMOVM2W-512-1) +{ +ICLASS: VPMOVM2W +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK_B():r:mskw +IFORM: VPMOVM2W_ZMMu16_MASKmskw_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-128-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u64 +IFORM: VPMOVQ2M_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-256-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u64 +IFORM: VPMOVQ2M_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQ2M (VPMOVQ2M-512-1) +{ +ICLASS: VPMOVQ2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu64 +IFORM: VPMOVQ2M_MASKmskw_ZMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-128-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-128-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-256-1) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQB (VPMOVQB-256-2) +{ +ICLASS: VPMOVQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-128-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-128-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-256-1) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQD (VPMOVQD-256-2) +{ +ICLASS: VPMOVQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-128-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-128-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-1) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVQW (VPMOVQW-256-2) +{ +ICLASS: VPMOVQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-128-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-128-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-256-1) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDB (VPMOVSDB-256-2) +{ +ICLASS: VPMOVSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-128-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-128-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-256-1) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSDW (VPMOVSDW-256-2) +{ +ICLASS: VPMOVSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i32 +IFORM: VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-128-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-128-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-256-1) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQB (VPMOVSQB-256-2) +{ +ICLASS: VPMOVSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-128-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-128-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-256-1) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQD (VPMOVSQD-256-2) +{ +ICLASS: VPMOVSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-128-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-128-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:i16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-256-1) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSQW (VPMOVSQW-256-2) +{ +ICLASS: VPMOVSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:i16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i64 +IFORM: VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-128-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-128-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:i8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-256-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-256-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:i8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:i16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-512-1) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 +} + + +# EMITTING VPMOVSWB (VPMOVSWB-512-2) +{ +ICLASS: VPMOVSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:i8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zi16 +IFORM: VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-128-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBD (VPMOVSXBD-256-1) +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-128-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBQ (VPMOVSXBQ-256-1) +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-128-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-256-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXBW (VPMOVSXBW-512-1) +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPMOVSXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-128-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXDQ (VPMOVSXDQ-256-1) +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVSXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-128-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWD (VPMOVSXWD-256-1) +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-128-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVSXWQ (VPMOVSXWQ-256-1) +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVSXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-128-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-1) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDB (VPMOVUSDB-256-2) +{ +ICLASS: VPMOVUSDB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-128-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-1) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSDW (VPMOVUSDW-256-2) +{ +ICLASS: VPMOVUSDW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-128-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:wrd:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-1) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQB (VPMOVUSQB-256-2) +{ +ICLASS: VPMOVUSQB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: MEM0:w:d:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-128-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u32 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-1) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQD (VPMOVUSQD-256-2) +{ +ICLASS: VPMOVUSQD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u32 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-128-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:d:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-1) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSQW (VPMOVUSQW-256-2) +{ +ICLASS: VPMOVUSQW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: MEM0:w:q:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-128-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-256-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-1) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVUSWB (VPMOVUSWB-512-2) +{ +ICLASS: VPMOVUSWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-128-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=XMM_B3():r:dq:u16 +IFORM: VPMOVW2M_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-256-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=YMM_B3():r:qq:u16 +IFORM: VPMOVW2M_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVW2M (VPMOVW2M-512-1) +{ +ICLASS: VPMOVW2M +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E7NM +REAL_OPCODE: Y +PATTERN: EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=ZMM_B3():r:zu16 +IFORM: VPMOVW2M_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-128-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:q:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-256-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-256-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-512-1) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVWB (VPMOVWB-512-2) +{ +ICLASS: VPMOVWB +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E6 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-128-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBD (VPMOVZXBD-256-1) +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-128-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:i8 +IFORM: VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBQ (VPMOVZXBQ-256-1) +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_EIGHTHMEM +PATTERN: EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i8 +IFORM: VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-128-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i8 +IFORM: VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-256-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i8 +IFORM: VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXBW (VPMOVZXBW-512-1) +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 +} + +{ +ICLASS: VPMOVZXBW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:i8 +IFORM: VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-128-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i32 +IFORM: VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXDQ (VPMOVZXDQ-256-1) +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VPMOVZXDQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i32 +IFORM: VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-128-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWD (VPMOVZXWD-256-1) +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWD +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_HALFMEM +PATTERN: EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:i16 +IFORM: VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-128-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:d:i16 +IFORM: VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMOVZXWQ (VPMOVZXWQ-256-1) +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VPMOVZXWQ +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_QUARTERMEM +PATTERN: EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:q:i16 +IFORM: VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-128-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 REG3=XMM_B3():r:dq:i64 +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULDQ (VPMULDQ-256-1) +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 REG3=YMM_B3():r:qq:i64 +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 +} + +{ +ICLASS: VPMULDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i64 MEM0:r:vv:i64:TXT=BCASTSTR +IFORM: VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-128-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-256-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHRSW (VPMULHRSW-512-1) +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPMULHRSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-128-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-256-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHUW (VPMULHUW-512-1) +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULHUW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-128-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-256-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULHW (VPMULHW-512-1) +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-128-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULLD (VPMULLD-256-1) +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMULLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-128-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-256-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLQ (VPMULLQ-512-1) +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMULLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-128-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-256-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULLW (VPMULLW-512-1) +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPMULLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-128-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPMULUDQ (VPMULUDQ-256-1) +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPMULUDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +COMMENT: Strange instruction that uses 32b of each 64b input element +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION DOUBLE_WIDE_MEMOP DISP8_FULL BROADCAST_ENABLED MASKOP_EVEX +PATTERN: EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-128-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORD (VPORD-256-1) +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPORQ (VPORQ-128-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPORQ (VPORQ-256-1) +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLD (VPROLD-128-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLD (VPROLD-256-1) +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPROLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-128-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLQ (VPROLQ-256-1) +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPROLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-128-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVD (VPROLVD-256-1) +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPROLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-128-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPROLVQ (VPROLVQ-256-1) +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPROLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORD (VPRORD-128-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORD (VPRORD-256-1) +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPRORD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-128-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORQ (VPRORQ-256-1) +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPRORQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-128-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVD (VPRORVD-256-1) +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPRORVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-128-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPRORVQ (VPRORVQ-256-1) +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPRORVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-128-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 REG2=XMM_B3():r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-256-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 REG2=YMM_B3():r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSADBW (VPSADBW-512-1) +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 REG2=ZMM_B3():r:zu8 +IFORM: VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSADBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-128-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +} + + +# EMITTING VPSCATTERDD (VPSCATTERDD-256-1) +{ +ICLASS: VPSCATTERDD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u32 +IFORM: VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-128-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +} + + +# EMITTING VPSCATTERDQ (VPSCATTERDQ-256-1) +{ +ICLASS: VPSCATTERDQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-128-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 +} + + +# EMITTING VPSCATTERQD (VPSCATTERQD-256-1) +{ +ICLASS: VPSCATTERQD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:u32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u32 +IFORM: VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-128-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 +} + + +# EMITTING VPSCATTERQQ (VPSCATTERQQ-256-1) +{ +ICLASS: VPSCATTERQQ +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:u64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:u64 +IFORM: VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 +} + + +# EMITTING VPSHUFB (VPSHUFB-128-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFB (VPSHUFB-256-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFB (VPSHUFB-512-1) +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSHUFB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSHUFD (VPSHUFD-128-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHUFD (VPSHUFD-256-1) +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-128-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-256-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFHW (VPSHUFHW-512-1) +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFHW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-128-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-256-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHUFLW (VPSHUFLW-512-1) +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHUFLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-128-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-128-3) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-256-1) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLD (VPSLLD-256-3) +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSLLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-128-2) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-256-2) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLDQ (VPSLLDQ-512-1) +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSLLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-128-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-128-3) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-256-1) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLQ (VPSLLQ-256-3) +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSLLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-128-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVD (VPSLLVD-256-1) +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSLLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-128-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLVQ (VPSLLVQ-256-1) +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSLLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-128-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-256-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLVW (VPSLLVW-512-1) +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSLLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-128-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-128-3) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-256-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-256-3) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-512-1) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSLLW (VPSLLW-512-2) +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSLLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-128-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-128-3) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-256-1) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAD (VPSRAD-256-3) +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRAD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-128-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-128-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-256-1) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAQ (VPSRAQ-256-2) +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRAQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-128-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVD (VPSRAVD-256-1) +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSRAVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-128-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAVQ (VPSRAVQ-256-1) +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSRAVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-128-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-256-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAVW (VPSRAVW-512-1) +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSRAVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-128-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-128-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-256-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-256-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-512-1) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRAW (VPSRAW-512-2) +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRAW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-128-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-128-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-256-1) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:dq:u32 +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLD (VPSRLD-256-2) +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSRLD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-128-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u8 REG1=XMM_B3():r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u8 MEM0:r:dq:u8 IMM0:r:b +IFORM: VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-256-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u8 REG1=YMM_B3():r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u8 MEM0:r:qq:u8 IMM0:r:b +IFORM: VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLDQ (VPSRLDQ-512-1) +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu8 REG1=ZMM_B3():r:zu8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 +} + +{ +ICLASS: VPSRLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu8 MEM0:r:zd:u8 IMM0:r:b +IFORM: VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-128-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-128-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_N3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-256-1) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:dq:u64 +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLQ (VPSRLQ-256-2) +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSRLQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_N3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-128-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVD (VPSRLVD-256-1) +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSRLVD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-128-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLVQ (VPSRLVQ-256-1) +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSRLVQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-128-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-256-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLVW (VPSRLVW-512-1) +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSRLVW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-128-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-128-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_N3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-256-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:dq:u16 +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-256-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_N3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-512-1) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_MEM128 +PATTERN: EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:dq:u16 +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSRLW (VPSRLW-512-2) +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSRLW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_N3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-128-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-256-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBB (VPSUBB-512-1) +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-128-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBD (VPSUBD-256-1) +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSUBD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-128-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBQ (VPSUBQ-256-1) +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSUBQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-128-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 REG3=XMM_B3():r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i8 MEM0:r:dq:i8 +IFORM: VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-256-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 REG3=YMM_B3():r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i8 MEM0:r:qq:i8 +IFORM: VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSB (VPSUBSB-512-1) +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 REG3=ZMM_B3():r:zi8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 +} + +{ +ICLASS: VPSUBSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi8 MEM0:r:zd:i8 +IFORM: VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-128-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 REG3=XMM_B3():r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:i16 MEM0:r:dq:i16 +IFORM: VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-256-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 REG3=YMM_B3():r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:i16 MEM0:r:qq:i16 +IFORM: VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBSW (VPSUBSW-512-1) +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 REG3=ZMM_B3():r:zi16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 +} + +{ +ICLASS: VPSUBSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zi16 MEM0:r:zd:i16 +IFORM: VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-128-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-256-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSB (VPSUBUSB-512-1) +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPSUBUSB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-128-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-256-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBUSW (VPSUBUSW-512-1) +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSUBUSW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-128-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-256-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSUBW (VPSUBW-512-1) +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSUBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-128-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGD (VPTERNLOGD-256-1) +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-128-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTERNLOGQ (VPTERNLOGQ-256-1) +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPTERNLOGQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-128-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-256-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMB (VPTESTMB-512-1) +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPTESTMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-128-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMD (VPTESTMD-256-1) +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPTESTMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-128-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTMQ (VPTESTMQ-256-1) +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPTESTMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-128-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-256-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTMW (VPTESTMW-512-1) +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPTESTMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-128-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-256-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMB (VPTESTNMB-512-1) +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPTESTNMB +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-128-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMD (VPTESTNMD-256-1) +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPTESTNMD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-128-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMQ (VPTESTNMQ-256-1) +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPTESTNMQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-128-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-256-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPTESTNMW (VPTESTNMW-512-1) +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPTESTNMW +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-128-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-256-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHBW (VPUNPCKHBW-512-1) +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKHBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-128-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHDQ (VPUNPCKHDQ-256-1) +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKHDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-128-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHQDQ (VPUNPCKHQDQ-256-1) +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKHQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-128-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-256-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKHWD (VPUNPCKHWD-512-1) +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKHWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-128-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-256-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLBW (VPUNPCKLBW-512-1) +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPUNPCKLBW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-128-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLDQ (VPUNPCKLDQ-256-1) +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPUNPCKLDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-128-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLQDQ (VPUNPCKLQDQ-256-1) +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPUNPCKLQDQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-128-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-256-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPUNPCKLWD (VPUNPCKLWD-512-1) +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPUNPCKLWD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512BW_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPXORD (VPXORD-128-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORD (VPXORD-256-1) +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPXORD +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-128-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPXORQ (VPXORQ-256-1) +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPXORQ +CPL: 3 +CATEGORY: LOGICAL +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-128-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-256-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPD (VRANGEPD-512-1) +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 REG3=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-128-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-256-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGEPS (VRANGEPS-512-1) +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 REG3=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRANGESD (VRANGESD-128-1) +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRANGESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRANGESS (VRANGESS-128-1) +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRANGESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-128-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PD (VRCP14PD-256-1) +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VRCP14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-128-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRCP14PS (VRCP14PS-256-1) +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VRCP14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-128-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-256-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPD (VREDUCEPD-512-1) +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-128-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-256-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCEPS (VREDUCEPS-512-1) +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VREDUCESD (VREDUCESD-128-1) +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 IMM0:r:b +IFORM: VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VREDUCESS (VREDUCESS-128-1) +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX MXCSR SIMD_SCALAR DISP8_SCALAR +PATTERN: EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:d:f32 IMM0:r:b +IFORM: VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-128-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPD (VRNDSCALEPD-256-1) +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-128-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPS (VRNDSCALEPS-256-1) +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-128-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PD (VRSQRT14PD-256-1) +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VRSQRT14PD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-128-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VRSQRT14PS (VRSQRT14PS-256-1) +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VRSQRT14PS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-128-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPD (VSCALEFPD-256-1) +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VSCALEFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-128-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCALEFPS (VSCALEFPS-256-1) +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VSCALEFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-128-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +} + + +# EMITTING VSCATTERDPD (VSCATTERDPD-256-1) +{ +ICLASS: VSCATTERDPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-128-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +} + + +# EMITTING VSCATTERDPS (VSCATTERDPS-256-1) +{ +ICLASS: VSCATTERDPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: DWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f32 +IFORM: VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-128-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 +} + + +# EMITTING VSCATTERQPD (VSCATTERQPD-256-1) +{ +ICLASS: VSCATTERQPD +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:q:f64 REG0=MASKNOT0():rw:mskw REG1=YMM_R3():r:qq:f64 +IFORM: VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-128-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 +} + + +# EMITTING VSCATTERQPS (VSCATTERQPS-256-1) +{ +ICLASS: VSCATTERQPS +CPL: 3 +CATEGORY: SCATTER +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E12 +REAL_OPCODE: Y +ATTRIBUTES: QWORD_INDICES DISP8_GSCAT MEMORY_FAULT_SUPPRESSION MASKOP_EVEX SPECIAL_AGEN_REQUIRED SCATTER +PATTERN: EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:d:f32 REG0=MASKNOT0():rw:mskw REG1=XMM_R3():r:dq:f32 +IFORM: VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 +} + + +# EMITTING VSHUFF32X4 (VSHUFF32X4-256-1) +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFF64X2 (VSHUFF64X2-256-1) +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFF64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFI32X4 (VSHUFI32X4-256-1) +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI32X4 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VSHUFI64X2 (VSHUFI64X2-256-1) +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFI64X2 +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-128-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPD (VSHUFPD-256-1) +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-128-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSHUFPS (VSHUFPS-256-1) +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 +} + +{ +ICLASS: VSHUFPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR IMM0:r:b +IFORM: VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-128-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPD (VSQRTPD-256-1) +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VSQRTPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-128-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSQRTPS (VSQRTPS-256-1) +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VSQRTPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-128-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPD (VSUBPD-256-1) +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VSUBPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-128-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VSUBPS (VSUBPS-256-1) +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VSUBPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL MXCSR BROADCAST_ENABLED +PATTERN: EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-128-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPD (VUNPCKHPD-256-1) +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VUNPCKHPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-128-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKHPS (VUNPCKHPS-256-1) +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VUNPCKHPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-128-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPD (VUNPCKLPD-256-1) +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 REG3=YMM_B3():r:qq:f64 +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 +} + +{ +ICLASS: VUNPCKLPD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f64 MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-128-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f32 +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 +} + + +# EMITTING VUNPCKLPS (VUNPCKLPS-256-1) +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 REG3=YMM_B3():r:qq:f32 +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 +} + +{ +ICLASS: VUNPCKLPS +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512F_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f32 MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 +} + + +# EMITTING VXORPD (VXORPD-128-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VXORPD (VXORPD-256-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VXORPD (VXORPD-512-1) +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VXORPD +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VXORPS (VXORPS-128-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VXORPS (VXORPS-256-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VXORPS (VXORPS-512-1) +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VXORPS +CPL: 3 +CATEGORY: LOGICAL_FP +EXTENSION: AVX512EVEX +ISA_SET: AVX512DQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +AVX_INSTRUCTIONS():: +# EMITTING KADDB (KADDB-256-1) +{ +ICLASS: KADDB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDD (KADDD-256-1) +{ +ICLASS: KADDD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDQ (KADDQ-256-1) +{ +ICLASS: KADDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KADDW (KADDW-256-1) +{ +ICLASS: KADDW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDB (KANDB-256-1) +{ +ICLASS: KANDB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDD (KANDD-256-1) +{ +ICLASS: KANDD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDNB (KANDNB-256-1) +{ +ICLASS: KANDNB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDND (KANDND-256-1) +{ +ICLASS: KANDND +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDNQ (KANDNQ-256-1) +{ +ICLASS: KANDNQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KANDQ (KANDQ-256-1) +{ +ICLASS: KANDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-1) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u8 +IFORM: KMOVB_MASKmskw_MASKu8_AVX512 +} + +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:b:u8 +IFORM: KMOVB_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-2) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +OPERANDS: MEM0:w:b:u8 REG0=MASK_R():r:mskw +IFORM: KMOVB_MEMu8_MASKmskw_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-3) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVB_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVB (KMOVB-128-4) +{ +ICLASS: KMOVB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVB_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-1) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u32 +IFORM: KMOVD_MASKmskw_MASKu32_AVX512 +} + +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:d:u32 +IFORM: KMOVD_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-2) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: MEM0:w:d:u32 REG0=MASK_R():r:mskw +IFORM: KMOVD_MEMu32_MASKmskw_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-3) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 + +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR32_B():r:d:u32 +IFORM: KMOVD_MASKmskw_GPR32u32_AVX512 +} + + +# EMITTING KMOVD (KMOVD-128-4) +{ +ICLASS: KMOVD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +COMMENT: KMOVQ aliases to KMOVD in 32b mode due to W bit being ignored. +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 + +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=MASK_B():r:mskw +IFORM: KMOVD_GPR32u32_MASKmskw_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-1) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw:u64 +IFORM: KMOVQ_MASKmskw_MASKu64_AVX512 +} + +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw MEM0:r:q:u64 +IFORM: KMOVQ_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-2) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K21 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +OPERANDS: MEM0:w:q:u64 REG0=MASK_R():r:mskw +IFORM: KMOVQ_MEMu64_MASKmskw_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-3) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=GPR64_B():r:q:u64 +IFORM: KMOVQ_MASKmskw_GPR64u64_AVX512 +} + + +# EMITTING KMOVQ (KMOVQ-128-4) +{ +ICLASS: KMOVQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=MASK_B():r:mskw +IFORM: KMOVQ_GPR64u64_MASKmskw_AVX512 +} + + +# EMITTING KNOTB (KNOTB-128-1) +{ +ICLASS: KNOTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KNOTD (KNOTD-128-1) +{ +ICLASS: KNOTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KNOTQ (KNOTQ-128-1) +{ +ICLASS: KNOTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw +IFORM: KNOTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORB (KORB-256-1) +{ +ICLASS: KORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORD (KORD-256-1) +{ +ICLASS: KORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORQ (KORQ-256-1) +{ +ICLASS: KORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTB (KORTESTB-128-1) +{ +ICLASS: KORTESTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTD (KORTESTD-128-1) +{ +ICLASS: KORTESTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KORTESTQ (KORTESTQ-128-1) +{ +ICLASS: KORTESTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KORTESTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KSHIFTLB (KSHIFTLB-128-1) +{ +ICLASS: KSHIFTLB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTLD (KSHIFTLD-128-1) +{ +ICLASS: KSHIFTLD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTLQ (KSHIFTLQ-128-1) +{ +ICLASS: KSHIFTLQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRB (KSHIFTRB-128-1) +{ +ICLASS: KSHIFTRB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRD (KSHIFTRD-128-1) +{ +ICLASS: KSHIFTRD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KSHIFTRQ (KSHIFTRQ-128-1) +{ +ICLASS: KSHIFTRQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_B():r:mskw IMM0:r:b +IFORM: KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 +} + + +# EMITTING KTESTB (KTESTB-128-1) +{ +ICLASS: KTESTB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTB_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTD (KTESTD-128-1) +{ +ICLASS: KTESTD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTD_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTQ (KTESTQ-128-1) +{ +ICLASS: KTESTQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTQ_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KTESTW (KTESTW-128-1) +{ +ICLASS: KTESTW +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod zf-mod pf-0 of-0 af-0 sf-0 ] +ATTRIBUTES: KMASK +PATTERN: VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +OPERANDS: REG0=MASK_R():r:mskw REG1=MASK_B():r:mskw +IFORM: KTESTW_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KUNPCKDQ (KUNPCKDQ-256-1) +{ +ICLASS: KUNPCKDQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KUNPCKWD (KUNPCKWD-256-1) +{ +ICLASS: KUNPCKWD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORB (KXNORB-256-1) +{ +ICLASS: KXNORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORD (KXNORD-256-1) +{ +ICLASS: KXNORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXNORQ (KXNORQ-256-1) +{ +ICLASS: KXNORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORB (KXORB-256-1) +{ +ICLASS: KXORB +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512DQ_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORD (KXORD-256-1) +{ +ICLASS: KXORD +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + +# EMITTING KXORQ (KXORQ-256-1) +{ +ICLASS: KXORQ +CPL: 3 +CATEGORY: KMASK +EXTENSION: AVX512VEX +ISA_SET: AVX512BW_KOP +EXCEPTIONS: AVX512-K20 +REAL_OPCODE: Y +ATTRIBUTES: KMASK +PATTERN: VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK_N():r:mskw REG2=MASK_B():r:mskw +IFORM: KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512ifma/ifma-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPMADD52HUQ (VPMADD52HUQ-128-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-256-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52HUQ (VPMADD52HUQ-512-1) +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMADD52HUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-128-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-256-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPMADD52LUQ (VPMADD52LUQ-512-1) +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPMADD52LUQ +CPL: 3 +CATEGORY: IFMA +EXTENSION: AVX512EVEX +ISA_SET: AVX512_IFMA_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512vbmi/vbmi-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPERMB (VPERMB-128-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMB (VPERMB-256-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMB (VPERMB-512-1) +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-128-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-256-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMI2B (VPERMI2B-512-1) +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMI2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-128-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-256-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VPERMT2B (VPERMT2B-512-1) +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VPERMT2B +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-128-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_128 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-256-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_256 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 +} + + +# EMITTING VPMULTISHIFTQB (VPMULTISHIFTQB-512-1) +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 +} + +{ +ICLASS: VPMULTISHIFTQB +CPL: 3 +CATEGORY: AVX512_VBMI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI_512 +EXCEPTIONS: AVX512-E4NF +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/wbnoinvd/wbnoinvd-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +{ +ICLASS : WBINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : BASE +ISA_SET : I486REAL +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 WBNOINVD=0 +OPERANDS : +PATTERN : 0x0F 0x09 WBNOINVD=1 REP!=3 +OPERANDS : +VERSION : 2 +} + +{ +ICLASS : WBNOINVD +CPL : 0 +CATEGORY : SYSTEM +EXTENSION : WBNOINVD +ISA_SET : WBNOINVD +ATTRIBUTES : RING0 NOTSX +PATTERN : 0x0F 0x09 WBNOINVD=1 f3_refining_prefix +OPERANDS : +} + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/pconfig/pconfig-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING PCONFIG (PCONFIG-N/A-1) +{ +ICLASS: PCONFIG +CPL: 0 +CATEGORY: PCONFIG +EXTENSION: PCONFIG +ISA_SET: PCONFIG +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64 +OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_EBX:crw:SUPP:d:u32 REG2=XED_REG_ECX:crw:SUPP:d:u32 REG3=XED_REG_EDX:crw:SUPP:d:u32 +IFORM: PCONFIG + +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64 +OPERANDS: REG0=XED_REG_EAX:rw:SUPP:d:u32 REG1=XED_REG_RBX:crw:SUPP:q:u64 REG2=XED_REG_RCX:crw:SUPP:q:u64 REG3=XED_REG_RDX:crw:SUPP:q:u64 +IFORM: PCONFIG64 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/bitalg/bitalg-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTB (VPOPCNTB-128-1) +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 +} + +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPOPCNTB (VPOPCNTB-256-1) +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 +} + +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPOPCNTB (VPOPCNTB-512-1) +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + +{ +ICLASS: VPOPCNTB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPOPCNTW (VPOPCNTW-128-1) +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPOPCNTW (VPOPCNTW-256-1) +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPOPCNTW (VPOPCNTW-512-1) +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VPOPCNTW +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-128-1) +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 +} + +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:u64 MEM0:r:dq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 +} + + +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-256-1) +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 +} + +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:u64 MEM0:r:qq:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 +} + + +# EMITTING VPSHUFBITQMB (VPSHUFBITQMB-512-1) +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 +} + +{ +ICLASS: VPSHUFBITQMB +CPL: 3 +CATEGORY: AVX512_BITALG +EXTENSION: AVX512EVEX +ISA_SET: AVX512_BITALG_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zu64 MEM0:r:zd:u8 +IFORM: VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vbmi2/vbmi2-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-1) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u8 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-128-2) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u8 +IFORM: VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-1) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u8 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-256-2) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u8 +IFORM: VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-1) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u8 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu8 +IFORM: VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSB (VPCOMPRESSB-512-2) +{ +ICLASS: VPCOMPRESSB +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu8 +IFORM: VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-1) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:dq:u16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:u16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-128-2) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_B3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_R3():r:dq:u16 +IFORM: VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-1) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:qq:u16 REG0=MASK1():r:mskw REG1=YMM_R3():r:qq:u16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-256-2) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_B3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_R3():r:qq:u16 +IFORM: VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-1) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: MEM0:w:zd:u16 REG0=MASK1():r:mskw REG1=ZMM_R3():r:zu16 +IFORM: VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPCOMPRESSW (VPCOMPRESSW-512-2) +{ +ICLASS: VPCOMPRESSW +CPL: 3 +CATEGORY: COMPRESS +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_B3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_R3():r:zu16 +IFORM: VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-128-1) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u8 +IFORM: VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-128-2) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u8 +IFORM: VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-256-1) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u8 +IFORM: VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-256-2) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u8 +IFORM: VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-512-1) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u8 +IFORM: VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 +} + + +# EMITTING VPEXPANDB (VPEXPANDB-512-2) +{ +ICLASS: VPEXPANDB +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu8 +IFORM: VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-128-1) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:dq:u16 +IFORM: VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-128-2) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-256-1) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:qq:u16 +IFORM: VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-256-2) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-512-1) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_GSCAT MASK_VARIABLE_MEMOP +PATTERN: EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:zd:u16 +IFORM: VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VPEXPANDW (VPEXPANDW-512-2) +{ +ICLASS: VPEXPANDW +CPL: 3 +CATEGORY: EXPAND +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 +} + + +# EMITTING VPSHLDD (VPSHLDD-128-1) +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHLDD (VPSHLDD-256-1) +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHLDD (VPSHLDD-512-1) +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHLDQ (VPSHLDQ-128-1) +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHLDQ (VPSHLDQ-256-1) +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHLDQ (VPSHLDQ-512-1) +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHLDVD (VPSHLDVD-128-1) +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHLDVD (VPSHLDVD-256-1) +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHLDVD (VPSHLDVD-512-1) +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSHLDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHLDVQ (VPSHLDVQ-128-1) +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHLDVQ (VPSHLDVQ-256-1) +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHLDVQ (VPSHLDVQ-512-1) +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSHLDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHLDVW (VPSHLDVW-128-1) +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHLDVW (VPSHLDVW-256-1) +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHLDVW (VPSHLDVW-512-1) +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSHLDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHLDW (VPSHLDW-128-1) +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHLDW (VPSHLDW-256-1) +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHLDW (VPSHLDW-512-1) +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHLDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDD (VPSHRDD-128-1) +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 IMM0:r:b +IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHRDD (VPSHRDD-256-1) +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 IMM0:r:b +IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHRDD (VPSHRDD-512-1) +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 IMM0:r:b +IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 +} + + +# EMITTING VPSHRDQ (VPSHRDQ-128-1) +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHRDQ (VPSHRDQ-256-1) +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHRDQ (VPSHRDQ-512-1) +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPSHRDVD (VPSHRDVD-128-1) +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 REG3=XMM_B3():r:dq:u32 +IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHRDVD (VPSHRDVD-256-1) +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 REG3=YMM_B3():r:qq:u32 +IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHRDVD (VPSHRDVD-512-1) +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 REG3=ZMM_B3():r:zu32 +IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VPSHRDVD +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VPSHRDVQ (VPSHRDVQ-128-1) +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 REG3=XMM_B3():r:dq:u64 +IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHRDVQ (VPSHRDVQ-256-1) +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 REG3=YMM_B3():r:qq:u64 +IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHRDVQ (VPSHRDVQ-512-1) +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 REG3=ZMM_B3():r:zu64 +IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VPSHRDVQ +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + +# EMITTING VPSHRDVW (VPSHRDVW-128-1) +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 +IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 +} + +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():rw:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 +IFORM: VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHRDVW (VPSHRDVW-256-1) +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 +IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 +} + +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():rw:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 +IFORM: VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHRDVW (VPSHRDVW-512-1) +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 +IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 +} + +{ +ICLASS: VPSHRDVW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():rw:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 +IFORM: VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-128-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 REG3=XMM_B3():r:dq:u16 IMM0:r:b +IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u16 MEM0:r:dq:u16 IMM0:r:b +IFORM: VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-256-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 REG3=YMM_B3():r:qq:u16 IMM0:r:b +IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u16 MEM0:r:qq:u16 IMM0:r:b +IFORM: VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 +} + + +# EMITTING VPSHRDW (VPSHRDW-512-1) +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 REG3=ZMM_B3():r:zu16 IMM0:r:b +IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 +} + +{ +ICLASS: VPSHRDW +CPL: 3 +CATEGORY: VBMI2 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VBMI2_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu16 MEM0:r:zd:u16 IMM0:r:b +IFORM: VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-sse-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING GF2P8AFFINEINVQB (GF2P8AFFINEINVQB-N/A-1) +{ +ICLASS: GF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: GF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 +} + + +# EMITTING GF2P8AFFINEQB (GF2P8AFFINEQB-N/A-1) +{ +ICLASS: GF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: GF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 +} + + +# EMITTING GF2P8MULB (GF2P8MULB-N/A-1) +{ +ICLASS: GF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +PATTERN: 0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:u8 REG1=XMM_B():r:dq:u8 +IFORM: GF2P8MULB_XMMu8_XMMu8 +} + +{ +ICLASS: GF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: GFNI +EXCEPTIONS: SSE_TYPE_4 +REAL_OPCODE: Y +ATTRIBUTES: REQUIRES_ALIGNMENT +PATTERN: 0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:dq:u8 +IFORM: GF2P8MULB_XMMu8_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-evex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-1) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-1) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-512-1) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-1) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-1) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-512-1) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:vv:u64:TXT=BCASTSTR IMM0:r:b +IFORM: VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-128-1) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 REG3=XMM_B3():r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:u8 MEM0:r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-256-1) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 REG3=YMM_B3():r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:u8 MEM0:r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-512-1) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 REG3=ZMM_B3():r:zu8 +IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: AVX512EVEX +ISA_SET: AVX512_GFNI_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULLMEM +PATTERN: EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu8 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zu8 MEM0:r:zd:u8 +IFORM: VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/gfni-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-128-2) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8AFFINEINVQB (VGF2P8AFFINEINVQB-256-2) +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEINVQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-128-2) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8AFFINEQB (VGF2P8AFFINEQB-256-2) +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 +} + +{ +ICLASS: VGF2P8AFFINEQB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u64 IMM0:r:b +IFORM: VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-128-2) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 REG2=XMM_B():r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_XMMu8_XMMu8 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():w:dq:u8 REG1=XMM_N():r:dq:u8 MEM0:r:dq:u8 +IFORM: VGF2P8MULB_XMMu8_XMMu8_MEMu8 +} + + +# EMITTING VGF2P8MULB (VGF2P8MULB-256-2) +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 REG2=YMM_B():r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_YMMu8_YMMu8 +} + +{ +ICLASS: VGF2P8MULB +CPL: 3 +CATEGORY: GFNI +EXTENSION: GFNI +ISA_SET: AVX_GFNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():w:qq:u8 REG1=YMM_N():r:qq:u8 MEM0:r:qq:u8 +IFORM: VGF2P8MULB_YMMu8_YMMu8_MEMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/vaes-evex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VAESDEC (VAESDEC-128-1) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDEC (VAESDEC-256-1) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDEC (VAESDEC-512-1) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-128-1) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-256-1) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-512-1) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENC (VAESENC-128-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESENC_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESENC_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENC (VAESENC-256-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENC (VAESENC-512-1) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-128-1) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 REG2=XMM_B3():r:dq:u128 +IFORM: VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u128 MEM0:r:dq:u128 +IFORM: VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-256-1) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 REG2=YMM_B3():r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-512-1) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 REG2=ZMM_B3():r:zu128 +IFORM: VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VAES_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu128 MEM0:r:zd:u128 +IFORM: VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-128-1) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=XMM_R3():w:dq:u128 REG1=XMM_N3():r:dq:u64 MEM0:r:dq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-1) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=YMM_R3():w:qq:u128 REG1=YMM_N3():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-512-1) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +PATTERN: EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 IMM0:r:b +IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPCLMULQDQ_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULLMEM +PATTERN: EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +OPERANDS: REG0=ZMM_R3():w:zu128 REG1=ZMM_N3():r:zu64 MEM0:r:zd:u64 IMM0:r:b +IFORM: VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/gfni-vaes-vpcl/vaes-vex-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VAESDEC (VAESDEC-256-2) +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESDEC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDEC_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESDECLAST (VAESDECLAST-256-2) +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESDECLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESDECLAST_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESENC (VAESENC-256-2) +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESENC +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENC_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VAESENCLAST (VAESENCLAST-256-2) +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 REG2=YMM_B():r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_YMMu128 +} + +{ +ICLASS: VAESENCLAST +CPL: 3 +CATEGORY: VAES +EXTENSION: VAES +ISA_SET: VAES +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u128 MEM0:r:qq:u128 +IFORM: VAESENCLAST_YMMu128_YMMu128_MEMu128 +} + + +# EMITTING VPCLMULQDQ (VPCLMULQDQ-256-2) +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: VPCLMULQDQ +ISA_SET: VPCLMULQDQ +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 REG2=YMM_B():r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 +} + +{ +ICLASS: VPCLMULQDQ +CPL: 3 +CATEGORY: VPCLMULQDQ +EXTENSION: VPCLMULQDQ +ISA_SET: VPCLMULQDQ +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8() +OPERANDS: REG0=YMM_R():w:qq:u128 REG1=YMM_N():r:qq:u64 MEM0:r:qq:u64 IMM0:r:b +IFORM: VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vpopcntdq-vl/vpopcntdq-vl-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VPOPCNTD (VPOPCNTD-128-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTD (VPOPCNTD-256-1) +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VPOPCNTD +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-128-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 +} + + +# EMITTING VPOPCNTQ (VPOPCNTQ-256-1) +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VPOPCNTQ +CPL: 3 +CATEGORY: AVX512 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VPOPCNTDQ_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MEMORY_FAULT_SUPPRESSION MASKOP_EVEX DISP8_FULL BROADCAST_ENABLED +PATTERN: EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/vp2intersect/vp2intersect-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VP2INTERSECTD (VP2INTERSECTD-128-1) +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 REG2=XMM_B3():r:dq:u32 +IFORM: VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 +} + +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 +} + + +# EMITTING VP2INTERSECTD (VP2INTERSECTD-256-1) +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 REG2=YMM_B3():r:qq:u32 +IFORM: VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 +} + +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 +} + + +# EMITTING VP2INTERSECTD (VP2INTERSECTD-512-1) +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 REG2=ZMM_B3():r:zu32 +IFORM: VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 +} + +{ +ICLASS: VP2INTERSECTD +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu32 MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 +} + + +# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-128-1) +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 REG2=XMM_B3():r:dq:u64 +IFORM: VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 +} + +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=XMM_N3():r:dq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 +} + + +# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-256-1) +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 REG2=YMM_B3():r:qq:u64 +IFORM: VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 +} + +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=YMM_N3():r:qq:u64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 +} + + +# EMITTING VP2INTERSECTQ (VP2INTERSECTQ-512-1) +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MULTIDEST2 +PATTERN: EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 MASK=0 +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 REG2=ZMM_B3():r:zu64 +IFORM: VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 +} + +{ +ICLASS: VP2INTERSECTQ +CPL: 3 +CATEGORY: AVX512_VP2INTERSECT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_VP2INTERSECT_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_FULL MULTIDEST2 BROADCAST_ENABLED +PATTERN: EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw:MULTIDEST2 REG1=ZMM_N3():r:zu64 MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/keylocker/keylocker-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING AESDEC128KL (AESDEC128KL-N/A-1) +{ +ICLASS: AESDEC128KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:m384:u8 +IFORM: AESDEC128KL_XMMu8_MEMu8 +} + + +# EMITTING AESDEC256KL (AESDEC256KL-N/A-1) +{ +ICLASS: AESDEC256KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDF f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:zd:u8 +IFORM: AESDEC256KL_XMMu8_MEMu8 +} + + +# EMITTING AESDECWIDE128KL (AESDECWIDE128KL-N/A-1) +{ +ICLASS: AESDECWIDE128KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:m384:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESDECWIDE128KL_MEMu8 +} + + +# EMITTING AESDECWIDE256KL (AESDECWIDE256KL-N/A-1) +{ +ICLASS: AESDECWIDE256KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:zd:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESDECWIDE256KL_MEMu8 +} + + +# EMITTING AESENC128KL (AESENC128KL-N/A-1) +{ +ICLASS: AESENC128KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDC f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:m384:u8 +IFORM: AESENC128KL_XMMu8_MEMu8 +} + + +# EMITTING AESENC256KL (AESENC256KL-N/A-1) +{ +ICLASS: AESENC256KL +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDE f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +OPERANDS: REG0=XMM_R():rw:dq:u8 MEM0:r:zd:u8 +IFORM: AESENC256KL_XMMu8_MEMu8 +} + + +# EMITTING AESENCWIDE128KL (AESENCWIDE128KL-N/A-1) +{ +ICLASS: AESENCWIDE128KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:m384:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESENCWIDE128KL_MEMu8 +} + + +# EMITTING AESENCWIDE256KL (AESENCWIDE256KL-N/A-1) +{ +ICLASS: AESENCWIDE256KL +CPL: 3 +CATEGORY: KEYLOCKER_WIDE +EXTENSION: KEYLOCKER_WIDE +ISA_SET: KEYLOCKER_WIDE +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: MEM0:r:zd:u8 REG0=XED_REG_XMM0:rw:SUPP:dq:u8 REG1=XED_REG_XMM1:rw:SUPP:dq:u8 REG2=XED_REG_XMM2:rw:SUPP:dq:u8 REG3=XED_REG_XMM3:rw:SUPP:dq:u8 REG4=XED_REG_XMM4:rw:SUPP:dq:u8 REG5=XED_REG_XMM5:rw:SUPP:dq:u8 REG6=XED_REG_XMM6:rw:SUPP:dq:u8 REG7=XED_REG_XMM7:rw:SUPP:dq:u8 +IFORM: AESENCWIDE256KL_MEMu8 +} + + +# EMITTING ENCODEKEY128 (ENCODEKEY128-N/A-1) +{ +ICLASS: ENCODEKEY128 +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-0 of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xFA MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS: REG0=GPR32_R():w:d:u8 REG1=GPR32_B():r:d:u8 REG2=XED_REG_XMM0:rw:SUPP:dq:u8 REG3=XED_REG_XMM1:w:SUPP:dq:u8 REG4=XED_REG_XMM2:w:SUPP:dq:u8 REG5=XED_REG_XMM4:w:SUPP:dq:u8 REG6=XED_REG_XMM5:w:SUPP:dq:u8 REG7=XED_REG_XMM6:w:SUPP:dq:u8 +IFORM: ENCODEKEY128_GPR32u8_GPR32u8 +} + + +# EMITTING ENCODEKEY256 (ENCODEKEY256-N/A-1) +{ +ICLASS: ENCODEKEY256 +CPL: 3 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-0 of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xFB MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +OPERANDS: REG0=GPR32_R():w:d:u8 REG1=GPR32_B():r:d:u8 REG2=XED_REG_XMM0:rw:SUPP:dq:u8 REG3=XED_REG_XMM1:rw:SUPP:dq:u8 REG4=XED_REG_XMM2:w:SUPP:dq:u8 REG5=XED_REG_XMM3:w:SUPP:dq:u8 REG6=XED_REG_XMM4:w:SUPP:dq:u8 REG7=XED_REG_XMM5:w:SUPP:dq:u8 REG8=XED_REG_XMM6:w:SUPP:dq:u8 +IFORM: ENCODEKEY256_GPR32u8_GPR32u8 +} + + +# EMITTING LOADIWKEY (LOADIWKEY-N/A-1) +{ +ICLASS: LOADIWKEY +CPL: 0 +CATEGORY: KEYLOCKER +EXTENSION: KEYLOCKER +ISA_SET: KEYLOCKER +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod of-0 sf-0 af-0 pf-0 cf-0 ] +PATTERN: 0x0F 0x38 0xDC f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +OPERANDS: REG0=XMM_R():r:dq:u8 REG1=XMM_B():r:dq:u8 REG2=XED_REG_EAX:r:SUPP:d:u32 REG3=XED_REG_XMM0:r:SUPP:dq:u8 +IFORM: LOADIWKEY_XMMu8_XMMu8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hreset/hreset-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING HRESET (HRESET-N/A-1) +{ +ICLASS: HRESET +CPL: 0 +CATEGORY: HRESET +EXTENSION: HRESET +ISA_SET: HRESET +REAL_OPCODE: Y +PATTERN: 0x0F 0x3A 0xF0 MOD[0b11] MOD=3 REG[0b000] RM[0b000] f3_refining_prefix UIMM8() +OPERANDS: IMM0:r:b REG0=XED_REG_EAX:r:SUPP:d:u32 +IFORM: HRESET_IMM8 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/avx-vnni-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING VPDPBUSD (VPDPBUSD-128-2) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPBUSD_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPBUSD_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPBUSD (VPDPBUSD-256-2) +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPBUSD_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPBUSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPBUSD_YMMi32_YMMu32_MEMu32 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-128-2) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPBUSDS_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPBUSDS (VPDPBUSDS-256-2) +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPBUSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPBUSDS_YMMi32_YMMu32_MEMu32 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-128-2) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPWSSD_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPWSSD_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPWSSD (VPDPWSSD-256-2) +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPWSSD_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPWSSD +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPWSSD_YMMi32_YMMu32_MEMu32 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-128-2) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 REG2=XMM_B():r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_XMMu32_XMMu32 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +OPERANDS: REG0=XMM_R():rw:dq:i32 REG1=XMM_N():r:dq:u32 MEM0:r:dq:u32 +IFORM: VPDPWSSDS_XMMi32_XMMu32_MEMu32 +} + + +# EMITTING VPDPWSSDS (VPDPWSSDS-256-2) +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 REG2=YMM_B():r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_YMMu32_YMMu32 +} + +{ +ICLASS: VPDPWSSDS +CPL: 3 +CATEGORY: VEX +EXTENSION: AVX_VNNI +ISA_SET: AVX_VNNI +EXCEPTIONS: avx-type-4 +REAL_OPCODE: Y +PATTERN: VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +OPERANDS: REG0=YMM_R():rw:qq:i32 REG1=YMM_N():r:qq:u32 MEM0:r:qq:u32 +IFORM: VPDPWSSDS_YMMi32_YMMu32_MEMu32 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/uintr/uintr-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING CLUI (CLUI-N/A-1) +{ +ICLASS: CLUI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_UIF:w:SUPP:i1 +IFORM: CLUI +} + + +# EMITTING SENDUIPI (SENDUIPI-N/A-1) +{ +ICLASS: SENDUIPI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +PATTERN: 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64 +OPERANDS: REG0=GPR32_B():r:d:u32 +IFORM: SENDUIPI_GPR32u32 +} + + +# EMITTING STUI (STUI-N/A-1) +{ +ICLASS: STUI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_UIF:w:SUPP:i1 +IFORM: STUI +} + + +# EMITTING TESTUI (TESTUI-N/A-1) +{ +ICLASS: TESTUI +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +FLAGS: MUST [ cf-mod ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64 +OPERANDS: REG0=XED_REG_UIF:r:SUPP:i1 +IFORM: TESTUI +} + + +# EMITTING UIRET (UIRET-N/A-1) +{ +ICLASS: UIRET +CPL: 3 +CATEGORY: UINTR +EXTENSION: UINTR +ISA_SET: UINTR +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-mod of-mod sf-mod af-mod ] +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64 +OPERANDS: REG0=rIP():w:SUPP REG1=XED_REG_STACKPOP:r:SUPP:spw +IFORM: UIRET +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-spr-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +AVX_INSTRUCTIONS():: +# EMITTING LDTILECFG (LDTILECFG-128-1) +{ +ICLASS: LDTILECFG +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E1 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: MEM0:r:zd +IFORM: LDTILECFG_MEM +} + + +# EMITTING STTILECFG (STTILECFG-128-1) +{ +ICLASS: STTILECFG +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E2 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: MEM0:w:zd +IFORM: STTILECFG_MEM +} + + +# EMITTING TDPBF16PS (TDPBF16PS-128-1) +{ +ICLASS: TDPBF16PS +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_BF16 +ISA_SET: AMX_BF16 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBF16PS_TMMf32_TMMu32_TMMu32 +} + + +# EMITTING TDPBSSD (TDPBSSD-128-1) +{ +ICLASS: TDPBSSD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBSSD_TMMi32_TMMu32_TMMu32 +} + + +# EMITTING TDPBSUD (TDPBSUD-128-1) +{ +ICLASS: TDPBSUD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBSUD_TMMi32_TMMu32_TMMu32 +} + + +# EMITTING TDPBUSD (TDPBUSD-128-1) +{ +ICLASS: TDPBUSD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:i32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBUSD_TMMi32_TMMu32_TMMu32 +} + + +# EMITTING TDPBUUD (TDPBUUD-128-1) +{ +ICLASS: TDPBUUD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_INT8 +ISA_SET: AMX_INT8 +EXCEPTIONS: AMX-E4 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x5E VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +OPERANDS: REG0=TMM_R():rw:tv:u32 REG1=TMM_B():r:tv:u32 REG2=TMM_N():r:tv:u32 +IFORM: TDPBUUD_TMMu32_TMMu32_TMMu32 +} + + +# EMITTING TILELOADD (TILELOADD-128-1) +{ +ICLASS: TILELOADD +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E3 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED +PATTERN: VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32 +IFORM: TILELOADD_TMMu32_MEMu32 +} + + +# EMITTING TILELOADDT1 (TILELOADDT1-128-1) +{ +ICLASS: TILELOADDT1 +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E3 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED +PATTERN: VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32 +IFORM: TILELOADDT1_TMMu32_MEMu32 +} + + +# EMITTING TILERELEASE (TILERELEASE-128-1) +{ +ICLASS: TILERELEASE +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E6 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 VNP V0F38 MOD[0b11] MOD=3 REG[0b000] RM[0b000] VL128 W0 mode64 NOVSR +OPERANDS: +IFORM: TILERELEASE +} + + +# EMITTING TILESTORED (TILESTORED-128-1) +{ +ICLASS: TILESTORED +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E3 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX SPECIAL_AGEN_REQUIRED +PATTERN: VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +OPERANDS: MEM0:w:ptr:u32 REG0=TMM_R():r:tv:u32 +IFORM: TILESTORED_MEMu32_TMMu32 +} + + +# EMITTING TILEZERO (TILEZERO-128-1) +{ +ICLASS: TILEZERO +CPL: 3 +CATEGORY: AMX_TILE +EXTENSION: AMX_TILE +ISA_SET: AMX_TILE +EXCEPTIONS: AMX-E5 +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR +OPERANDS: REG0=TMM_R():w:tv:u32 +IFORM: TILEZERO_TMMu32 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/enqcmd/enqcmd-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING ENQCMD (ENQCMD-N/A-1) +{ +ICLASS: ENQCMD +CPL: 3 +CATEGORY: ENQCMD +EXTENSION: ENQCMD +ISA_SET: ENQCMD +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 +IFORM: ENQCMD_GPRa_MEMu32 +} + + +# EMITTING ENQCMDS (ENQCMDS-N/A-1) +{ +ICLASS: ENQCMDS +CPL: 3 +CATEGORY: ENQCMD +EXTENSION: ENQCMD +ISA_SET: ENQCMD +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-0 pf-0 of-0 sf-0 af-0 ] +PATTERN: 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +OPERANDS: REG0=A_GPR_R():r MEM0:r:zd:u32 +IFORM: ENQCMDS_GPRa_MEMu32 +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tsx-ldtrk/tsx-ldtrk-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +INSTRUCTIONS():: +# EMITTING XRESLDTRK (XRESLDTRK-N/A-1) +{ +ICLASS: XRESLDTRK +CPL: 3 +CATEGORY: TSX_LDTRK +EXTENSION: TSX_LDTRK +ISA_SET: TSX_LDTRK +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix +OPERANDS: +IFORM: XRESLDTRK +} + + +# EMITTING XSUSLDTRK (XSUSLDTRK-N/A-1) +{ +ICLASS: XSUSLDTRK +CPL: 3 +CATEGORY: TSX_LDTRK +EXTENSION: TSX_LDTRK +ISA_SET: TSX_LDTRK +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix +OPERANDS: +IFORM: XSUSLDTRK +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/serialize/serialize-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SERIALIZE (SERIALIZE-N/A-1) +{ +ICLASS: SERIALIZE +CPL: 3 +CATEGORY: SERIALIZE +EXTENSION: SERIALIZE +ISA_SET: SERIALIZE +REAL_OPCODE: Y +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix +OPERANDS: +IFORM: SERIALIZE +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/tdx/tdx-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +INSTRUCTIONS():: +# EMITTING SEAMCALL (SEAMCALL-N/A-1) +{ +ICLASS: SEAMCALL +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RAX:rw:SUPP:q:u64 +IFORM: SEAMCALL +} + + +# EMITTING SEAMOPS (SEAMOPS-N/A-1) +{ +ICLASS: SEAMOPS +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RAX:rw:SUPP:q:u64 +IFORM: SEAMOPS +} + + +# EMITTING SEAMRET (SEAMRET-N/A-1) +{ +ICLASS: SEAMRET +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod cf-mod pf-0 of-0 sf-0 af-0 ] +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64 +OPERANDS: +IFORM: SEAMRET +} + + +# EMITTING TDCALL (TDCALL-N/A-1) +{ +ICLASS: TDCALL +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64 +OPERANDS: REG0=XED_REG_RCX:r:SUPP:q:u64 +IFORM: TDCALL +} + + +# EMITTING TDCALL (TDCALL-N/A-2) +{ +ICLASS: TDCALL +CPL: 0 +CATEGORY: LEGACY +EXTENSION: TDX +ISA_SET: TDX +REAL_OPCODE: Y +ATTRIBUTES: NOTSX +PATTERN: 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64 +OPERANDS: REG0=XED_REG_ECX:r:SUPP:d:u32 +IFORM: TDCALL +} + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-fp16-isa.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# +# +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# ***** GENERATED FILE -- DO NOT EDIT! ***** +# +# +# +EVEX_INSTRUCTIONS():: +# EMITTING VADDPH (VADDPH-128-1) +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VADDPH (VADDPH-256-1) +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VADDPH (VADDPH-512-1) +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VADDPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VADDSH (VADDSH-128-1) +{ +ICLASS: VADDSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VADDSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VADDSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VCMPPH (VCMPPH-128-1) +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCMPPH (VCMPPH-256-1) +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCMPPH (VCMPPH-512-1) +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCMPSH (VCMPSH-128-1) +{ +ICLASS: VCMPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw:TXT=SAESTR REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VCMPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VCOMISH (VCOMISH-128-1) +{ +ICLASS: VCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16 +IFORM: VCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: DISP8_SCALAR MXCSR SIMD_SCALAR +PATTERN: EVV 0x2F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VCOMISH_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VCVTDQ2PH (VCVTDQ2PH-128-1) +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i32 +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 +} + + +# EMITTING VCVTDQ2PH (VCVTDQ2PH-256-1) +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32 +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 +} + + +# EMITTING VCVTDQ2PH (VCVTDQ2PH-512-1) +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi32 +IFORM: VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 +} + +{ +ICLASS: VCVTDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i32:TXT=BCASTSTR +IFORM: VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 +} + + +# EMITTING VCVTPD2PH (VCVTPD2PH-128-1) +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 +} + + +# EMITTING VCVTPD2PH (VCVTPD2PH-256-1) +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 +} + + +# EMITTING VCVTPD2PH (VCVTPD2PH-512-1) +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64 +IFORM: VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 +} + +{ +ICLASS: VCVTPD2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR +IFORM: VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 +} + + +# EMITTING VCVTPH2DQ (VCVTPH2DQ-128-1) +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2DQ (VCVTPH2DQ-256-1) +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2DQ (VCVTPH2DQ-512-1) +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PD (VCVTPH2PD-128-1) +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PD (VCVTPH2PD-256-1) +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PD (VCVTPH2PD-512-1) +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PSX (VCVTPH2PSX-128-1) +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PSX (VCVTPH2PSX-256-1) +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2PSX (VCVTPH2PSX-512-1) +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2PSX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_FTZ +PATTERN: EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2QQ (VCVTPH2QQ-128-1) +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2QQ (VCVTPH2QQ-256-1) +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2QQ (VCVTPH2QQ-512-1) +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-128-1) +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-256-1) +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UDQ (VCVTPH2UDQ-512-1) +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-128-1) +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-256-1) +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UQQ (VCVTPH2UQQ-512-1) +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UW (VCVTPH2UW-128-1) +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UW (VCVTPH2UW-256-1) +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2UW (VCVTPH2UW-512-1) +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2W (VCVTPH2W-128-1) +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2W (VCVTPH2W-256-1) +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPH2W (VCVTPH2W-512-1) +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTPS2PHX (VCVTPS2PHX-128-1) +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f32 +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 +} + + +# EMITTING VCVTPS2PHX (VCVTPS2PHX-256-1) +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f32 +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 +} + + +# EMITTING VCVTPS2PHX (VCVTPS2PHX-512-1) +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32 +IFORM: VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 +} + +{ +ICLASS: VCVTPS2PHX +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR USES_DAZ +PATTERN: EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR +IFORM: VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 +} + + +# EMITTING VCVTQQ2PH (VCVTQQ2PH-128-1) +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTQQ2PH (VCVTQQ2PH-256-1) +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTQQ2PH (VCVTQQ2PH-512-1) +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTSD2SH (VCVTSD2SH-128-1) +{ +ICLASS: VCVTSD2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f64 +IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 +} + +{ +ICLASS: VCVTSD2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:q:f64 +IFORM: VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 +} + + +# EMITTING VCVTSH2SD (VCVTSH2SD-128-1) +{ +ICLASS: VCVTSH2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SD +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f64 MEM0:r:wrd:f16 +IFORM: VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-mode64) +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SI (VCVTSH2SI-128-1-not64) +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SI (VCVTSH2SI-128-2) +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16 +IFORM: VCVTSH2SI_GPR64i64_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2SS (VCVTSH2SS-128-1) +{ +ICLASS: VCVTSH2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 REG3=XMM_B3():r:dq:f16 +IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2SS +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_FTZ +PATTERN: EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f32 MEM0:r:wrd:f16 +IFORM: VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-mode64) +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2USI (VCVTSH2USI-128-1-not64) +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTSH2USI (VCVTSH2USI-128-2) +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=ROUNDC REG1=XMM_B3():r:dq:f16 +IFORM: VCVTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16 +IFORM: VCVTSH2USI_GPR64u64_MEMf16_AVX512 +} + + +# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-mode64) +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SH (VCVTSI2SH-128-1-not64) +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:i32 +IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 +} + + +# EMITTING VCVTSI2SH (VCVTSI2SH-128-2) +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:i64 +IFORM: VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 +} + +{ +ICLASS: VCVTSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:i64 +IFORM: VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 +} + + +# EMITTING VCVTSS2SH (VCVTSS2SH-128-1) +{ +ICLASS: VCVTSS2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f32 +IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 +} + +{ +ICLASS: VCVTSS2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR USES_DAZ +PATTERN: EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:d:f32 +IFORM: VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 +} + + +# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-128-1) +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-256-1) +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:i32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2DQ (VCVTTPH2DQ-512-1) +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2DQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zi32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-128-1) +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-256-1) +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:i64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2QQ (VCVTTPH2QQ-512-1) +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2QQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zi64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-128-1) +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=XMM_R3():w:dq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-256-1) +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=YMM_R3():w:qq:u32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UDQ (VCVTTPH2UDQ-512-1) +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UDQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_HALF MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +OPERANDS: REG0=ZMM_R3():w:zu32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-128-1) +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=XMM_R3():w:dq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-256-1) +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=YMM_R3():w:qq:u64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UQQ (VCVTTPH2UQQ-512-1) +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UQQ +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_QUARTER MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +OPERANDS: REG0=ZMM_R3():w:zu64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UW (VCVTTPH2UW-128-1) +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UW (VCVTTPH2UW-256-1) +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:u16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2UW (VCVTTPH2UW-512-1) +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zu16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2UW +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zu16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2W (VCVTTPH2W-128-1) +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2W (VCVTTPH2W-256-1) +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:i16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTPH2W (VCVTTPH2W-512-1) +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zi16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VCVTTPH2W +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zi16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-mode64) +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-1-not64) +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR32i32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:i32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2SI_GPR32i32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2SI (VCVTTSH2SI-128-2) +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2SI_GPR64i64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2SI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:i64 MEM0:r:wrd:f16 +IFORM: VCVTTSH2SI_GPR64i64_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-mode64) +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-1-not64) +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR32u32_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR32_R():w:d:u32 MEM0:r:wrd:f16 +IFORM: VCVTTSH2USI_GPR32u32_MEMf16_AVX512 +} + + +# EMITTING VCVTTSH2USI (VCVTTSH2USI-128-2) +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VCVTTSH2USI_GPR64u64_XMMf16_AVX512 +} + +{ +ICLASS: VCVTTSH2USI +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_LDOP_D MXCSR SIMD_SCALAR +PATTERN: EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +OPERANDS: REG0=GPR64_R():w:q:u64 MEM0:r:wrd:f16 +IFORM: VCVTTSH2USI_GPR64u64_MEMf16_AVX512 +} + + +# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-128-1) +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u32 +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 +} + + +# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-256-1) +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32 +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 +} + + +# EMITTING VCVTUDQ2PH (VCVTUDQ2PH-512-1) +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu32 +IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 +} + +{ +ICLASS: VCVTUDQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u32:TXT=BCASTSTR +IFORM: VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 +} + + +# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-128-1) +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 +} + + +# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-256-1) +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 +} + + +# EMITTING VCVTUQQ2PH (VCVTUQQ2PH-512-1) +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64 +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 +} + +{ +ICLASS: VCVTUQQ2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u64:TXT=BCASTSTR +IFORM: VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 +} + + +# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-mode64) +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-1-not64) +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR32_B():r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:d:u32 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 +} + + +# EMITTING VCVTUSI2SH (VCVTUSI2SH-128-2) +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=XMM_N3():r:dq:f16 REG2=GPR64_B():r:q:u64 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 +} + +{ +ICLASS: VCVTUSI2SH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER MXCSR SIMD_SCALAR +PATTERN: EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=XMM_N3():r:dq:f16 MEM0:r:q:u64 +IFORM: VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 +} + + +# EMITTING VCVTUW2PH (VCVTUW2PH-128-1) +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:u16 +IFORM: VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR +IFORM: VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VCVTUW2PH (VCVTUW2PH-256-1) +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u16 +IFORM: VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR +IFORM: VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VCVTUW2PH (VCVTUW2PH-512-1) +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu16 +IFORM: VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 +} + +{ +ICLASS: VCVTUW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:u16:TXT=BCASTSTR +IFORM: VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 +} + + +# EMITTING VCVTW2PH (VCVTW2PH-128-1) +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:i16 +IFORM: VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR +IFORM: VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VCVTW2PH (VCVTW2PH-256-1) +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i16 +IFORM: VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR +IFORM: VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VCVTW2PH (VCVTW2PH-512-1) +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zi16 +IFORM: VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 +} + +{ +ICLASS: VCVTW2PH +CPL: 3 +CATEGORY: CONVERT +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:i16:TXT=BCASTSTR +IFORM: VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 +} + + +# EMITTING VDIVPH (VDIVPH-128-1) +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VDIVPH (VDIVPH-256-1) +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VDIVPH (VDIVPH-512-1) +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VDIVPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VDIVSH (VDIVSH-128-1) +{ +ICLASS: VDIVSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VDIVSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VDIVSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFCMADDCPH (VFCMADDCPH-128-1) +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMADDCPH (VFCMADDCPH-256-1) +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMADDCPH (VFCMADDCPH-512-1) +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMADDCSH (VFCMADDCSH-128-1) +{ +ICLASS: VFCMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCPH (VFCMULCPH-128-1) +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCPH (VFCMULCPH-256-1) +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCPH (VFCMULCPH-512-1) +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFCMULCSH (VFCMULCSH-128-1) +{ +ICLASS: VFCMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFCMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADD132PH (VFMADD132PH-128-1) +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD132PH (VFMADD132PH-256-1) +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD132PH (VFMADD132PH-512-1) +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD132SH (VFMADD132SH-128-1) +{ +ICLASS: VFMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x99 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213PH (VFMADD213PH-128-1) +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213PH (VFMADD213PH-256-1) +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213PH (VFMADD213PH-512-1) +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD213SH (VFMADD213SH-128-1) +{ +ICLASS: VFMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xA9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231PH (VFMADD231PH-128-1) +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231PH (VFMADD231PH-256-1) +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231PH (VFMADD231PH-512-1) +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADD231SH (VFMADD231SH-128-1) +{ +ICLASS: VFMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xB9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDCPH (VFMADDCPH-128-1) +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDCPH (VFMADDCPH-256-1) +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDCPH (VFMADDCPH-512-1) +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDCSH (VFMADDCSH-128-1) +{ +ICLASS: VFMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMADDCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0x57 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-128-1) +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-256-1) +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB132PH (VFMADDSUB132PH-512-1) +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-128-1) +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-256-1) +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB213PH (VFMADDSUB213PH-512-1) +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-128-1) +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-256-1) +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMADDSUB231PH (VFMADDSUB231PH-512-1) +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMADDSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132PH (VFMSUB132PH-128-1) +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132PH (VFMSUB132PH-256-1) +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132PH (VFMSUB132PH-512-1) +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB132SH (VFMSUB132SH-128-1) +{ +ICLASS: VFMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x9B V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213PH (VFMSUB213PH-128-1) +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213PH (VFMSUB213PH-256-1) +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213PH (VFMSUB213PH-512-1) +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB213SH (VFMSUB213SH-128-1) +{ +ICLASS: VFMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xAB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231PH (VFMSUB231PH-128-1) +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231PH (VFMSUB231PH-256-1) +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231PH (VFMSUB231PH-512-1) +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUB231SH (VFMSUB231SH-128-1) +{ +ICLASS: VFMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xBB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-128-1) +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-256-1) +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD132PH (VFMSUBADD132PH-512-1) +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-128-1) +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-256-1) +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD213PH (VFMSUBADD213PH-512-1) +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-128-1) +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-256-1) +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMSUBADD231PH (VFMSUBADD231PH-512-1) +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFMSUBADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFMULCPH (VFMULCPH-128-1) +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMULCPH (VFMULCPH-256-1) +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 REG3=YMM_B3():r:qq:2f16 +IFORM: VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMULCPH (VFMULCPH-512-1) +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:z2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 REG3=ZMM_B3():r:z2f16 +IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 +} + +{ +ICLASS: VFMULCPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH +PATTERN: EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:z2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:z2f16 MEM0:r:vv:2f16:TXT=BCASTSTR +IFORM: VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFMULCSH (VFMULCSH-128-1) +{ +ICLASS: VFMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:2f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 REG3=XMM_B3():r:dq:2f16 +IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 +} + +{ +ICLASS: VFMULCSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR NO_SRC_DEST_MATCH SIMD_SCALAR +PATTERN: EVV 0xD7 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:2f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:2f16 MEM0:r:d:2f16 +IFORM: VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 +} + + +# EMITTING VFNMADD132PH (VFNMADD132PH-128-1) +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD132PH (VFNMADD132PH-256-1) +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD132PH (VFNMADD132PH-512-1) +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD132SH (VFNMADD132SH-128-1) +{ +ICLASS: VFNMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x9D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213PH (VFNMADD213PH-128-1) +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213PH (VFNMADD213PH-256-1) +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213PH (VFNMADD213PH-512-1) +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD213SH (VFNMADD213SH-128-1) +{ +ICLASS: VFNMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xAD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231PH (VFNMADD231PH-128-1) +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231PH (VFNMADD231PH-256-1) +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231PH (VFNMADD231PH-512-1) +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMADD231SH (VFNMADD231SH-128-1) +{ +ICLASS: VFNMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMADD231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xBD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132PH (VFNMSUB132PH-128-1) +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132PH (VFNMSUB132PH-256-1) +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132PH (VFNMSUB132PH-512-1) +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB132SH (VFNMSUB132SH-128-1) +{ +ICLASS: VFNMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB132SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x9F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213PH (VFNMSUB213PH-128-1) +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213PH (VFNMSUB213PH-256-1) +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213PH (VFNMSUB213PH-512-1) +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB213SH (VFNMSUB213SH-128-1) +{ +ICLASS: VFNMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB213SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xAF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231PH (VFNMSUB231PH-128-1) +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231PH (VFNMSUB231PH-256-1) +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():rw:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231PH (VFNMSUB231PH-512-1) +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():rw:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231PH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():rw:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VFNMSUB231SH (VFNMSUB231SH-128-1) +{ +ICLASS: VFNMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():rw:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VFNMSUB231SH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0xBF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():rw:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VFPCLASSPH (VFPCLASSPH-128-1) +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 +} + + +# EMITTING VFPCLASSPH (VFPCLASSPH-256-1) +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 +} + + +# EMITTING VFPCLASSPH (VFPCLASSPH-512-1) +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 +} + + +# EMITTING VFPCLASSSH (VFPCLASSSH-128-1) +{ +ICLASS: VFPCLASSSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x67 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VFPCLASSSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x67 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=MASK_R():w:mskw REG1=MASK1():r:mskw MEM0:r:wrd:f16 IMM0:r:b +IFORM: VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETEXPPH (VGETEXPPH-128-1) +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VGETEXPPH (VGETEXPPH-256-1) +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VGETEXPPH (VGETEXPPH-512-1) +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VGETEXPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VGETEXPSH (VGETEXPSH-128-1) +{ +ICLASS: VGETEXPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VGETEXPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VGETEXPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x43 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VGETMANTPH (VGETMANTPH-128-1) +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETMANTPH (VGETMANTPH-256-1) +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETMANTPH (VGETMANTPH-512-1) +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VGETMANTSH (VGETMANTSH-128-1) +{ +ICLASS: VGETMANTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VGETMANTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x27 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VMAXPH (VMAXPH-128-1) +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMAXPH (VMAXPH-256-1) +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VMAXPH (VMAXPH-512-1) +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMAXPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VMAXSH (VMAXSH-128-1) +{ +ICLASS: VMAXSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMAXSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMAXSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINPH (VMINPH-128-1) +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINPH (VMINPH-256-1) +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINPH (VMINPH-512-1) +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMINPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VMINSH (VMINSH-128-1) +{ +ICLASS: VMINSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMINSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMINSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-1) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x10 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:wrd:f16 +IFORM: VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-5) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x11 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: MEM0:w:wrd:f16 REG0=MASK1():r:mskw REG1=XMM_R3():r:dq:f16 +IFORM: VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-6) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + + +# EMITTING VMOVSH (VMOVSH-128-7) +{ +ICLASS: VMOVSH +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E5 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_B3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_R3():r:dq:f16 +IFORM: VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + + +# EMITTING VMOVW (VMOVW-128-1) +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x6E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=GPR32_B():r:d:f16 +IFORM: VMOVW_XMMf16_GPR32f16_AVX512 +} + +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_READER +PATTERN: EVV 0x6E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_READER() +OPERANDS: REG0=XMM_R3():w:dq:f16 MEM0:r:wrd:f16 +IFORM: VMOVW_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMOVW (VMOVW-128-2) +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +PATTERN: EVV 0x7E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=GPR32_B():w:d:f16 REG1=XMM_R3():r:dq:f16 +IFORM: VMOVW_GPR32f16_XMMf16_AVX512 +} + +{ +ICLASS: VMOVW +CPL: 3 +CATEGORY: DATAXFER +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128N +EXCEPTIONS: AVX512-E9NF +REAL_OPCODE: Y +ATTRIBUTES: DISP8_GPR_WRITER_STORE +PATTERN: EVV 0x7E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_STORE() +OPERANDS: MEM0:w:wrd:f16 REG0=XMM_R3():r:dq:f16 +IFORM: VMOVW_MEMf16_XMMf16_AVX512 +} + + +# EMITTING VMULPH (VMULPH-128-1) +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VMULPH (VMULPH-256-1) +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VMULPH (VMULPH-512-1) +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VMULPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VMULSH (VMULSH-128-1) +{ +ICLASS: VMULSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMULSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VMULSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VRCPPH (VRCPPH-128-1) +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRCPPH (VRCPPH-256-1) +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRCPPH (VRCPPH-512-1) +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VRCPPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRCPSH (VRCPSH-128-1) +{ +ICLASS: VRCPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x4D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VRCPSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x4D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VREDUCEPH (VREDUCEPH-128-1) +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VREDUCEPH (VREDUCEPH-256-1) +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VREDUCEPH (VREDUCEPH-512-1) +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VREDUCESH (VREDUCESH-128-1) +{ +ICLASS: VREDUCESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VREDUCESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x57 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPH (VRNDSCALEPH-128-1) +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPH (VRNDSCALEPH-256-1) +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 IMM0:r:b +IFORM: VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALEPH (VRNDSCALEPH-512-1) +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 IMM0:r:b +IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALEPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR IMM0:r:b +IFORM: VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRNDSCALESH (VRNDSCALESH-128-1) +{ +ICLASS: VRNDSCALESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 IMM0:r:b +IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 +} + +{ +ICLASS: VRNDSCALESH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x0A VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 IMM0:r:b +IFORM: VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 +} + + +# EMITTING VRSQRTPH (VRSQRTPH-128-1) +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRSQRTPH (VRSQRTPH-256-1) +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRSQRTPH (VRSQRTPH-512-1) +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX +PATTERN: EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VRSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E4 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION +PATTERN: EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VRSQRTSH (VRSQRTSH-128-1) +{ +ICLASS: VRSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX SIMD_SCALAR +PATTERN: EVV 0x4F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VRSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E10 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION SIMD_SCALAR +PATTERN: EVV 0x4F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFPH (VSCALEFPH-128-1) +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFPH (VSCALEFPH-256-1) +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFPH (VSCALEFPH-512-1) +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSCALEFPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VSCALEFSH (VSCALEFSH-128-1) +{ +ICLASS: VSCALEFSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSCALEFSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSCALEFSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x2D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSQRTPH (VSQRTPH-128-1) +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_B3():r:dq:f16 +IFORM: VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VSQRTPH (VSQRTPH-256-1) +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:f16 +IFORM: VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VSQRTPH (VSQRTPH-512-1) +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf16 +IFORM: VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 +} + +{ +ICLASS: VSQRTPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 +} + + +# EMITTING VSQRTSH (VSQRTSH-128-1) +{ +ICLASS: VSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSQRTSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBPH (VSUBPH-128-1) +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_128 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBPH (VSUBPH-256-1) +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 REG3=YMM_B3():r:qq:f16 +IFORM: VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_256 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=YMM_R3():w:qq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_N3():r:qq:f16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBPH (VSUBPH-512-1) +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +OPERANDS: REG0=ZMM_R3():w:zf16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 REG3=ZMM_B3():r:zf16 +IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 +} + +{ +ICLASS: VSUBPH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_512 +EXCEPTIONS: AVX512-E2 +REAL_OPCODE: Y +ATTRIBUTES: BROADCAST_ENABLED DISP8_FULL MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR +PATTERN: EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +OPERANDS: REG0=ZMM_R3():w:zf16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_N3():r:zf16 MEM0:r:vv:f16:TXT=BCASTSTR +IFORM: VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 +} + + +# EMITTING VSUBSH (VSUBSH-128-1) +{ +ICLASS: VSUBSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSUBSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: MASKOP_EVEX MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +OPERANDS: REG0=XMM_R3():w:dq:f16:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 REG3=XMM_B3():r:dq:f16 +IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VSUBSH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3 +REAL_OPCODE: Y +ATTRIBUTES: DISP8_SCALAR MASKOP_EVEX MEMORY_FAULT_SUPPRESSION MXCSR SIMD_SCALAR +PATTERN: EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():w:dq:f16 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=XMM_N3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 +} + + +# EMITTING VUCOMISH (VUCOMISH-128-1) +{ +ICLASS: VUCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16 REG1=XMM_B3():r:dq:f16 +IFORM: VUCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VUCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +OPERANDS: REG0=XMM_R3():r:dq:f16:TXT=SAESTR REG1=XMM_B3():r:dq:f16 +IFORM: VUCOMISH_XMMf16_XMMf16_AVX512 +} + +{ +ICLASS: VUCOMISH +CPL: 3 +CATEGORY: FP16 +EXTENSION: AVX512EVEX +ISA_SET: AVX512_FP16_SCALAR +EXCEPTIONS: AVX512-E3NF +REAL_OPCODE: Y +FLAGS: MUST [ zf-mod pf-mod cf-mod of-0 sf-0 af-0 ] +ATTRIBUTES: DISP8_SCALAR MXCSR SIMD_SCALAR +PATTERN: EVV 0x2E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR() +OPERANDS: REG0=XMM_R3():r:dq:f16 MEM0:r:wrd:f16 +IFORM: VUCOMISH_XMMf16_MEMf16_AVX512 +} + + diff --git a/CodeVirtualizer/build/obj/dgen/all-enc-patterns.txt b/CodeVirtualizer/build/obj/dgen/all-enc-patterns.txt new file mode 100644 index 0000000..1bc826c --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-enc-patterns.txt @@ -0,0 +1,1925 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-gpr8-enc-reg-table.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +############################################################################ +#This is an experiment with an encoder table. It does not set fields +#that are initialized to zero (REXR, REXB). It sets NOREX, NEEDREX to +#indicated encoding constraints. +############################################################################ + + + +xed_reg_enum_t GPR8_R():: + +OUTREG=XED_REG_AL -> REG=0x0 +OUTREG=XED_REG_CL -> REG=0x1 +OUTREG=XED_REG_DL -> REG=0x2 +OUTREG=XED_REG_BL -> REG=0x3 + +OUTREG=XED_REG_AH -> REG=0x4 NOREX=1 +OUTREG=XED_REG_CH -> REG=0x5 NOREX=1 +OUTREG=XED_REG_DH -> REG=0x6 NOREX=1 +OUTREG=XED_REG_BH -> REG=0x7 NOREX=1 + +OUTREG=XED_REG_SPL -> REG=0x4 NEEDREX=1 +OUTREG=XED_REG_BPL -> REG=0x5 NEEDREX=1 +OUTREG=XED_REG_SIL -> REG=0x6 NEEDREX=1 +OUTREG=XED_REG_DIL -> REG=0x7 NEEDREX=1 + +OUTREG=XED_REG_R8B -> REXR=1 REG=0x0 +OUTREG=XED_REG_R9B -> REXR=1 REG=0x1 +OUTREG=XED_REG_R10B -> REXR=1 REG=0x2 +OUTREG=XED_REG_R11B -> REXR=1 REG=0x3 +OUTREG=XED_REG_R12B -> REXR=1 REG=0x4 +OUTREG=XED_REG_R13B -> REXR=1 REG=0x5 +OUTREG=XED_REG_R14B -> REXR=1 REG=0x6 +OUTREG=XED_REG_R15B -> REXR=1 REG=0x7 + + +xed_reg_enum_t GPR8_B():: +OUTREG=XED_REG_AL -> RM=0x0 +OUTREG=XED_REG_CL -> RM=0x1 +OUTREG=XED_REG_DL -> RM=0x2 +OUTREG=XED_REG_BL -> RM=0x3 + +OUTREG=XED_REG_AH -> RM=0x4 NOREX=1 +OUTREG=XED_REG_CH -> RM=0x5 NOREX=1 +OUTREG=XED_REG_DH -> RM=0x6 NOREX=1 +OUTREG=XED_REG_BH -> RM=0x7 NOREX=1 + +OUTREG=XED_REG_SPL -> RM=0x4 NEEDREX=1 +OUTREG=XED_REG_BPL -> RM=0x5 NEEDREX=1 +OUTREG=XED_REG_SIL -> RM=0x6 NEEDREX=1 +OUTREG=XED_REG_DIL -> RM=0x7 NEEDREX=1 + +OUTREG=XED_REG_R8B -> REXB=1 RM=0x0 +OUTREG=XED_REG_R9B -> REXB=1 RM=0x1 +OUTREG=XED_REG_R10B -> REXB=1 RM=0x2 +OUTREG=XED_REG_R11B -> REXB=1 RM=0x3 +OUTREG=XED_REG_R12B -> REXB=1 RM=0x4 +OUTREG=XED_REG_R13B -> REXB=1 RM=0x5 +OUTREG=XED_REG_R14B -> REXB=1 RM=0x6 +OUTREG=XED_REG_R15B -> REXB=1 RM=0x7 + + +xed_reg_enum_t GPR8_SB():: +OUTREG=XED_REG_AL -> SRM=0x0 +OUTREG=XED_REG_CL -> SRM=0x1 +OUTREG=XED_REG_DL -> SRM=0x2 +OUTREG=XED_REG_BL -> SRM=0x3 + +OUTREG=XED_REG_AH -> SRM=0x4 NOREX=1 +OUTREG=XED_REG_CH -> SRM=0x5 NOREX=1 +OUTREG=XED_REG_DH -> SRM=0x6 NOREX=1 +OUTREG=XED_REG_BH -> SRM=0x7 NOREX=1 + +OUTREG=XED_REG_SPL -> SRM=0x4 NEEDREX=1 +OUTREG=XED_REG_BPL -> SRM=0x5 NEEDREX=1 +OUTREG=XED_REG_SIL -> SRM=0x6 NEEDREX=1 +OUTREG=XED_REG_DIL -> SRM=0x7 NEEDREX=1 + +OUTREG=XED_REG_R8B -> REXB=1 SRM=0x0 +OUTREG=XED_REG_R9B -> REXB=1 SRM=0x1 +OUTREG=XED_REG_R10B -> REXB=1 SRM=0x2 +OUTREG=XED_REG_R11B -> REXB=1 SRM=0x3 +OUTREG=XED_REG_R12B -> REXB=1 SRM=0x4 +OUTREG=XED_REG_R13B -> REXB=1 SRM=0x5 +OUTREG=XED_REG_R14B -> REXB=1 SRM=0x6 +OUTREG=XED_REG_R15B -> REXB=1 SRM=0x7 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-modrm-encode.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# Decoder ring +# @ = null = invalid register +# * = any valid register or value for this field +# nothing = encode nothing in this case +# error = cannot encode + +SEQUENCE MODRM_BIND + SIB_REQUIRED_ENCODE_BIND() + SIBSCALE_ENCODE_BIND() + SIBINDEX_ENCODE_BIND() + SIBBASE_ENCODE_BIND() + MODRM_RM_ENCODE_BIND() + MODRM_MOD_ENCODE_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + SIB_NT_BIND() # FIXME 2007-06-30 + DISP_NT_BIND() + +SEQUENCE MODRM_EMIT + #MODRM_NT_EMIT() # FIXME: 2007-06-30 the instruction will emit this as part of the INSTRUCTIONS NT + SIB_NT_EMIT() + DISP_NT_EMIT() + +SEGMENT_DEFAULT_ENCODE():: +BASE0=rIPa() -> nothing # no segment for RIP/EIP +BASE0=ArSP() -> default_ss # default to SS +BASE0=ArBP() -> default_ss # default to SS +BASE0=@ -> default_ds # default to DS -- baseless +# +BASE0=ArAX() -> default_ds # everything else defaults to DS +BASE0=ArCX() -> default_ds +BASE0=ArDX() -> default_ds +BASE0=ArBX() -> default_ds +BASE0=ArSI() -> default_ds +BASE0=ArDI() -> default_ds +BASE0=Ar8() -> default_ds +BASE0=Ar9() -> default_ds +BASE0=Ar10() -> default_ds +BASE0=Ar11() -> default_ds +BASE0=Ar12() -> default_ds +BASE0=Ar13() -> default_ds +BASE0=Ar14() -> default_ds +BASE0=Ar15() -> default_ds + +SEGMENT_ENCODE():: +default_ss SEG0=@ -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # assume this is what the user wanted +default_ss SEG0=XED_REG_CS -> cs_prefix +default_ss SEG0=XED_REG_DS -> ds_prefix +default_ss SEG0=XED_REG_SS -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # matches default +default_ss SEG0=XED_REG_ES -> es_prefix +default_ss SEG0=XED_REG_FS -> fs_prefix +default_ss SEG0=XED_REG_GS -> gs_prefix +# +default_ds SEG0=@ -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # assume this is what the user wanted +default_ds SEG0=XED_REG_CS -> cs_prefix +default_ds SEG0=XED_REG_DS -> no_seg_prefix # was "nothing" 2007-0x08-0x14 # matches default +default_ds SEG0=XED_REG_SS -> ss_prefix +default_ds SEG0=XED_REG_ES -> es_prefix +default_ds SEG0=XED_REG_FS -> fs_prefix +default_ds SEG0=XED_REG_GS -> gs_prefix +otherwise -> no_seg_prefix # was "nothing" 2007-0x08-0x14 + + +SIB_REQUIRED_ENCODE():: +eamode32 INDEX=GPR32e() -> NEED_SIB=1 +eamode64 INDEX=GPR64e() -> NEED_SIB=1 +# base-less memop in 64b mode requires a SIB + +eamode64 BASE0=@ DISP_WIDTH=32 -> NEED_SIB=1 +eamode32 mode64 BASE0=@ DISP_WIDTH=32 -> NEED_SIB=1 +eamode32 mode16 -> nothing +eamode32 mode32 -> nothing + +# Denote the need of a SIB byte if base is rSP or r12 +eanot16 BASE0=ArSP() -> NEED_SIB=1 +eanot16 BASE0=Ar12() -> NEED_SIB=1 + +# When the displacement is omitted, we supply one for these r13 and rBP. +#eanot16 BASE0=ArBP() DISP_WIDTH=0 -> NEED_SIB=1 +#eanot16 BASE0=Ar13() DISP_WIDTH=0 -> NEED_SIB=1 + +otherwise -> nothing # FIXME: could set NEED_SIB=0 + +SIBBASE_ENCODE():: +NEED_SIB=0 -> nothing +NEED_SIB=1 -> SIBBASE_ENCODE_SIB1() + +SIBBASE_ENCODE_SIB1():: +BASE0=ArAX() -> SIBBASE=0 REXB=0 +BASE0=Ar8() -> SIBBASE=0 REXB=1 +BASE0=ArCX() -> SIBBASE=1 REXB=0 +BASE0=Ar9() -> SIBBASE=1 REXB=1 +BASE0=ArDX() -> SIBBASE=2 REXB=0 +BASE0=Ar10() -> SIBBASE=2 REXB=1 +BASE0=ArBX() -> SIBBASE=3 REXB=0 +BASE0=Ar11() -> SIBBASE=3 REXB=1 +BASE0=ArSP() -> SIBBASE=4 REXB=0 +BASE0=Ar12() -> SIBBASE=4 REXB=1 + +# The mod values are really gotten by the MOD rule, only requiring one +# addition. +## BAD MODIFIES DISP! NEED_SIB=1 BASE0=@ DISP_WIDTH=8 -> SIBBASE=5 REXB=0 DISP_WIDTH=32 # MOD=0 +BASE0=@ -> DISP_WIDTH_32() SIBBASE=5 REXB=0 # MOD=0 +# The MOD rule handles the DISP arg modification for rBP and r13 +BASE0=ArBP() -> DISP_WIDTH_0_8_32() SIBBASE=5 REXB=0 # MOD=1 # ARG MODIFICATION LATER IN MOD RULE + +# NEED_SIB=1 BASE0=@ DISP_WIDTH=32 -> SIBBASE=5 REXB=0 # MOD=0 redundant with the above +# The MOD rule handles the DISP arg modification for rBP and r13 +BASE0=Ar13() -> DISP_WIDTH_0_8_32() SIBBASE=5 REXB=1 # MOD=1 # ARG MODIFICATION LATER IN MOD RULE + +BASE0=ArSI() -> SIBBASE=6 REXB=0 +BASE0=Ar14() -> SIBBASE=6 REXB=1 +BASE0=ArDI() -> SIBBASE=7 REXB=0 +BASE0=Ar15() -> SIBBASE=7 REXB=1 +otherwise -> error # BASE0 was some other register + +SIBINDEX_ENCODE():: +NEED_SIB=0 -> nothing +NEED_SIB=1 -> SIBINDEX_ENCODE_SIB1() + +SIBINDEX_ENCODE_SIB1():: +INDEX=ArAX() -> SIBINDEX=0 REXX=0 +INDEX=Ar8() -> SIBINDEX=0 REXX=1 +INDEX=ArCX() -> SIBINDEX=1 REXX=0 +INDEX=Ar9() -> SIBINDEX=1 REXX=1 +INDEX=ArDX() -> SIBINDEX=2 REXX=0 +INDEX=Ar10() -> SIBINDEX=2 REXX=1 +INDEX=ArBX() -> SIBINDEX=3 REXX=0 +INDEX=Ar11() -> SIBINDEX=3 REXX=1 +INDEX=@ -> SIBINDEX=4 REXX=0 # the "no index" option +INDEX=Ar12() -> SIBINDEX=4 REXX=1 +INDEX=ArBP() -> SIBINDEX=5 REXX=0 +INDEX=Ar13() -> SIBINDEX=5 REXX=1 +INDEX=ArSI() -> SIBINDEX=6 REXX=0 +INDEX=Ar14() -> SIBINDEX=6 REXX=1 +INDEX=ArDI() -> SIBINDEX=7 REXX=0 +INDEX=Ar15() -> SIBINDEX=7 REXX=1 +otherwise -> error # INDEX was some other register + + +SIBSCALE_ENCODE():: +NEED_SIB=0 -> nothing +NEED_SIB=1 SCALE=0 -> SIBSCALE=0 # this allows for default unset scales +NEED_SIB=1 SCALE=1 -> SIBSCALE=0 +NEED_SIB=1 SCALE=2 -> SIBSCALE=1 +NEED_SIB=1 SCALE=4 -> SIBSCALE=2 +NEED_SIB=1 SCALE=8 -> SIBSCALE=3 +otherwise -> error # SCALE was some other value + +############################################################################## +MODRM_MOD_ENCODE():: +eamode16 DISP_WIDTH=0 -> MODRM_MOD_EA16_DISP0() +eamode16 DISP_WIDTH=8 -> MODRM_MOD_EA16_DISP8() +eamode16 DISP_WIDTH=16 -> MODRM_MOD_EA16_DISP16() +eamode16 DISP_WIDTH=32 -> ERROR() +eamode16 DISP_WIDTH=64 -> ERROR() + +eamode32 DISP_WIDTH=0 -> MODRM_MOD_EA32_DISP0() +eamode32 DISP_WIDTH=8 -> MODRM_MOD_EA32_DISP8() +eamode32 DISP_WIDTH=16 -> ERROR() +eamode32 DISP_WIDTH=32 -> MODRM_MOD_EA32_DISP32() +eamode32 DISP_WIDTH=64 -> ERROR() + +eamode64 DISP_WIDTH=0 -> MODRM_MOD_EA64_DISP0() +eamode64 DISP_WIDTH=8 -> MODRM_MOD_EA64_DISP8() +eamode64 DISP_WIDTH=16 -> ERROR() +eamode64 DISP_WIDTH=32 -> MODRM_MOD_EA64_DISP32() +eamode64 DISP_WIDTH=64 -> ERROR() +############################################################################## +#### EAMODE16 +############################################################################## +MODRM_MOD_EA16_DISP0():: +BASE0=XED_REG_BX INDEX=@ -> MOD=0 +BASE0=XED_REG_SI INDEX=@ -> MOD=0 +BASE0=XED_REG_DI INDEX=@ -> MOD=0 +BASE0=XED_REG_BP INDEX=@ -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_BP INDEX=XED_REG_SI -> MOD=0 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> MOD=0 +BASE0=XED_REG_BX INDEX=XED_REG_SI -> MOD=0 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> MOD=0 + +MODRM_MOD_EA16_DISP8():: +BASE0=XED_REG_BX INDEX=@ -> MOD=1 +BASE0=XED_REG_SI INDEX=@ -> MOD=1 +BASE0=XED_REG_DI INDEX=@ -> MOD=1 +BASE0=XED_REG_BP INDEX=@ -> MOD=1 +BASE0=XED_REG_BP INDEX=XED_REG_SI -> MOD=1 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> MOD=1 +BASE0=XED_REG_BX INDEX=XED_REG_SI -> MOD=1 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> MOD=1 + +MODRM_MOD_EA16_DISP16():: +BASE0=@ INDEX=@ -> MOD=0 +BASE0=XED_REG_BX INDEX=@ -> MOD=2 +BASE0=XED_REG_SI INDEX=@ -> MOD=2 +BASE0=XED_REG_DI INDEX=@ -> MOD=2 +BASE0=XED_REG_BP INDEX=@ -> MOD=2 +BASE0=XED_REG_BP INDEX=XED_REG_SI -> MOD=2 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> MOD=2 +BASE0=XED_REG_BX INDEX=XED_REG_SI -> MOD=2 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> MOD=2 + + +############################################################################## +#### EAMODE32 +############################################################################## +MODRM_MOD_EA32_DISP0():: +# Add a fake 1B displacement to rBP and r13 if they do not have one already. +BASE0=XED_REG_EBP mode32 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_EBP mode64 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_R13D mode64 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION + +# All these 32b and 64b base regs can handle no displacement +BASE0=XED_REG_EAX mode32 -> MOD=0 +BASE0=XED_REG_EBX mode32 -> MOD=0 +BASE0=XED_REG_ECX mode32 -> MOD=0 +BASE0=XED_REG_EDX mode32 -> MOD=0 +BASE0=XED_REG_ESI mode32 -> MOD=0 +BASE0=XED_REG_EDI mode32 -> MOD=0 +BASE0=XED_REG_ESP mode32 -> MOD=0 # our choice to use MOD=0 (w/sib) + +BASE0=XED_REG_EAX mode64 -> MOD=0 +BASE0=XED_REG_EBX mode64 -> MOD=0 +BASE0=XED_REG_ECX mode64 -> MOD=0 +BASE0=XED_REG_EDX mode64 -> MOD=0 +BASE0=XED_REG_ESI mode64 -> MOD=0 +BASE0=XED_REG_EDI mode64 -> MOD=0 +BASE0=XED_REG_ESP mode64 -> MOD=0 # our choice to use MOD=0 (w/sib) + +BASE0=XED_REG_R8D mode64 -> MOD=0 +BASE0=XED_REG_R9D mode64 -> MOD=0 +BASE0=XED_REG_R10D mode64 -> MOD=0 +BASE0=XED_REG_R11D mode64 -> MOD=0 +BASE0=XED_REG_R12D mode64 -> MOD=0 # our choice to use MOD=0 (w/sib) +BASE0=XED_REG_R14D mode64 -> MOD=0 +BASE0=XED_REG_R15D mode64 -> MOD=0 + +MODRM_MOD_EA32_DISP8():: +otherwise -> MOD=1 # might use SIB + +MODRM_MOD_EA32_DISP32():: +BASE0=@ -> MOD=0 #no base (handles NEED_SIB=1 case) +BASE0=GPR32e() -> MOD=2 #some base, not RIP, might use SIB +BASE0=rIPa() mode64 -> MOD=0 + +############################################################################## +#### EAMODE64 +############################################################################## + +MODRM_MOD_EA64_DISP0():: +BASE0=XED_REG_EIP -> MOD=0 DISP_WIDTH=32 DISP=0 # base eip +BASE0=XED_REG_RIP -> MOD=0 DISP_WIDTH=32 DISP=0 # base rip + +BASE0=XED_REG_RBP -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_R13 -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +BASE0=XED_REG_RAX -> MOD=0 +BASE0=XED_REG_RBX -> MOD=0 +BASE0=XED_REG_RCX -> MOD=0 +BASE0=XED_REG_RDX -> MOD=0 +BASE0=XED_REG_RSI -> MOD=0 +BASE0=XED_REG_RDI -> MOD=0 +BASE0=XED_REG_RSP -> MOD=0 +BASE0=XED_REG_R8 -> MOD=0 +BASE0=XED_REG_R9 -> MOD=0 +BASE0=XED_REG_R10 -> MOD=0 +BASE0=XED_REG_R11 -> MOD=0 +BASE0=XED_REG_R12 -> MOD=0 +BASE0=XED_REG_R14 -> MOD=0 +BASE0=XED_REG_R15 -> MOD=0 + +MODRM_MOD_EA64_DISP8():: +BASE0=GPR64e() -> MOD=1 + +MODRM_MOD_EA64_DISP32():: +BASE0=@ -> MOD=0 #no base, NEED_SIB=1 required (provided elsewhere) +BASE0=XED_REG_EIP -> MOD=0 #base eip +BASE0=XED_REG_RIP -> MOD=0 #base rip +BASE0=XED_REG_RAX -> MOD=2 +BASE0=XED_REG_RBX -> MOD=2 +BASE0=XED_REG_RCX -> MOD=2 +BASE0=XED_REG_RDX -> MOD=2 +BASE0=XED_REG_RSI -> MOD=2 +BASE0=XED_REG_RDI -> MOD=2 +BASE0=XED_REG_RSP -> MOD=2 # NEED_SIB=1 required (and is provided elsewhere) +BASE0=XED_REG_RBP -> MOD=2 +BASE0=XED_REG_R8 -> MOD=2 +BASE0=XED_REG_R9 -> MOD=2 +BASE0=XED_REG_R10 -> MOD=2 +BASE0=XED_REG_R11 -> MOD=2 +BASE0=XED_REG_R12 -> MOD=2 # NEED_SIB=1 required (and is provided elsewhere) +BASE0=XED_REG_R13 -> MOD=2 +BASE0=XED_REG_R14 -> MOD=2 +BASE0=XED_REG_R15 -> MOD=2 +######################################################################################################## + + +#If we didn't already encode the base in the SIB! +MODRM_RM_ENCODE():: + +eamode16 NEED_SIB=0 -> MODRM_RM_ENCODE_EA16_SIB0() +eamode32 NEED_SIB=0 -> MODRM_RM_ENCODE_EA32_SIB0() +eamode64 NEED_SIB=0 -> MODRM_RM_ENCODE_EA64_SIB0() +eanot16 NEED_SIB=1 -> MODRM_RM_ENCODE_EANOT16_SIB1() + +############################################# + +MODRM_RM_ENCODE_EA16_SIB0():: +BASE0=XED_REG_BX INDEX=XED_REG_SI -> RM=0 +BASE0=XED_REG_BX INDEX=XED_REG_DI -> RM=1 +BASE0=XED_REG_BP INDEX=XED_REG_SI -> RM=2 +BASE0=XED_REG_BP INDEX=XED_REG_DI -> RM=3 +BASE0=XED_REG_SI INDEX=@ -> RM=4 +BASE0=XED_REG_DI INDEX=@ -> RM=5 +BASE0=@ INDEX=@ -> DISP_WIDTH_16() RM=6 + + +# for BP without an index, we add an imm8=0 when encoding the MOD +BASE0=XED_REG_BP INDEX=@ -> DISP_WIDTH_0_8_16() RM=6 +BASE0=XED_REG_BX INDEX=@ -> RM=7 + +MODRM_RM_ENCODE_EA64_SIB0():: +BASE0=XED_REG_RAX -> RM=0 REXB=0 +BASE0=XED_REG_R8 -> RM=0 REXB=1 +BASE0=XED_REG_RCX -> RM=1 REXB=0 +BASE0=XED_REG_R9 -> RM=1 REXB=1 +BASE0=XED_REG_RDX -> RM=2 REXB=0 +BASE0=XED_REG_R10 -> RM=2 REXB=1 +BASE0=XED_REG_RBX -> RM=3 REXB=0 +BASE0=XED_REG_R11 -> RM=3 REXB=1 + + +BASE0=XED_REG_RSI -> RM=6 REXB=0 +BASE0=XED_REG_R14 -> RM=6 REXB=1 +BASE0=XED_REG_RDI -> RM=7 REXB=0 +BASE0=XED_REG_R15 -> RM=7 REXB=1 + +# case RM=5 is tricky. The mode,base and disp width play a role +BASE0=@ -> DISP_WIDTH_32() RM=5 # not setting REXB FIXME? + +# for rBP without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_RBP -> DISP_WIDTH_0_8_32() RM=5 REXB=0 + + +# When we do the MOD encoding, we fix the displacement at 4B. +BASE0=XED_REG_RIP -> RM=5 # not setting REXB FIXME? +BASE0=XED_REG_EIP -> RM=5 # not setting REXB FIXME? + +# for r13 without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_R13 -> DISP_WIDTH_0_8_32() RM=5 REXB=1 + +MODRM_RM_ENCODE_EA32_SIB0():: +BASE0=XED_REG_EAX -> RM=0 REXB=0 +BASE0=XED_REG_R8D -> RM=0 REXB=1 +BASE0=XED_REG_ECX -> RM=1 REXB=0 +BASE0=XED_REG_R9D -> RM=1 REXB=1 +BASE0=XED_REG_EDX -> RM=2 REXB=0 +BASE0=XED_REG_R10D -> RM=2 REXB=1 +BASE0=XED_REG_EBX -> RM=3 REXB=0 +BASE0=XED_REG_R11D -> RM=3 REXB=1 + + +BASE0=XED_REG_ESI -> RM=6 REXB=0 +BASE0=XED_REG_R14D -> RM=6 REXB=1 +BASE0=XED_REG_EDI -> RM=7 REXB=0 +BASE0=XED_REG_R15D -> RM=7 REXB=1 + +# case RM=5 is tricky. The mode,base and disp width play a role +BASE0=@ -> DISP_WIDTH_32() RM=5 # not setting REXB FIXME? + +# for rBP without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_EBP -> DISP_WIDTH_0_8_32() RM=5 REXB=0 + +# for r13 without a disp, we add a 1B disp so MOD will be 1 +BASE0=XED_REG_R13D -> DISP_WIDTH_0_8_32() RM=5 REXB=1 + +BASE0=XED_REG_RIP mode64 -> RM=5 +BASE0=XED_REG_EIP mode64 -> RM=5 + +MODRM_RM_ENCODE_EANOT16_SIB1():: +otherwise -> RM=4 # SIB will specify the REXB etc. + +############################################# + + + +# These are good, seemingly: + +# FIXME: these are semi-redundant with field bindings that I need for decode. +# I was thinking about using something like: +# MODRM[mm,rrr,nnn] & SIB[ss,iii,bbb] +# coupled with: +# MODRM = (MOD,2), (REG,3), (RM,3) +# SIB = (SIBSCALE,2), (SIBINDEX,3), (SIBBASE,3) + +#FIXME: don't require =*??? +#FIXME: handle "nothing" option + +## SIB_EMIT():: +## NEED_SIB=1 SIBBASE[bbb]=* SIBSCALE[ss]=* SIBINDEX[iii]=* -> ss_iii_bbb +## NEED_SIB=0 -> nothing +## +## MODRM_EMIT():: +## MODRM=1 MOD[xx]=* REG[rrr]=* RM[mmm]=* -> xx_rrr_mmm +## MODRM=0 -> nothing + +# ... OR ... + +SIB_NT():: +NEED_SIB=1 SIBBASE[bbb] SIBSCALE[ss] SIBINDEX[iii] -> ss_iii_bbb +NEED_SIB=0 -> nothing + + + +# 2 bytes storage +DISP_NT():: +#DISP_WIDTH=0 -> nothing +DISP_WIDTH=8 DISP[d/8] -> d/8 +DISP_WIDTH=16 DISP[d/16] -> d/16 +DISP_WIDTH=32 DISP[d/32] -> d/32 +DISP_WIDTH=64 DISP[d/64] -> d/64 +otherwise -> nothing + +ERROR():: +otherwise -> ERROR=XED_ERROR_GENERAL_ERROR + +DISP_WIDTH_0():: +DISP_WIDTH=0 -> nothing + +DISP_WIDTH_8():: +DISP_WIDTH=8 -> nothing + +DISP_WIDTH_16():: +DISP_WIDTH=16 -> nothing + +DISP_WIDTH_32():: +DISP_WIDTH=32 -> nothing + +DISP_WIDTH_0_8_16():: +DISP_WIDTH=0 -> nothing +DISP_WIDTH=8 -> nothing +DISP_WIDTH=16 -> nothing + + +DISP_WIDTH_0_8_32():: +DISP_WIDTH=0 -> nothing +DISP_WIDTH=8 -> nothing +DISP_WIDTH=32 -> nothing + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-prefixes-encode.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# any of the things in {} can trigger the action for these +# the letters in square brackets are bound to the bits after the arrow. +# The [] brackets are like an OR-triggering function. + +# For encoding, we spell out the order of the legacy prefixes and rex +# prefixes. On decode, the sequential semantics were used to zero out +# the effects of rex prefixes but that doesn't work for encode. So we +# have to make a different table for encoding. + + +SEQUENCE ISA_ENCODE + ISA_BINDINGS + ISA_EMIT + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + REX_PREFIX_ENC_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + REX_PREFIX_ENC_EMIT() + INSTRUCTIONS_EMIT() # THIS TAKES CARE OF MODRM/SIB/DISP/IMM + + +FIXUP_EOSZ_ENC():: +mode16 EOSZ=0 -> EOSZ=1 +mode32 EOSZ=0 -> EOSZ=2 +mode64 EOSZ=0 -> EOSZ=2 +otherwise -> nothing + +FIXUP_EASZ_ENC():: +mode16 EASZ=0 -> EASZ=1 +mode32 EASZ=0 -> EASZ=2 +mode64 EASZ=0 -> EASZ=3 +otherwise -> nothing + +FIXUP_SMODE_ENC():: +mode64 SMODE=0 -> SMODE=2 +mode64 SMODE=1 -> error +otherwise -> nothing + +# FIXME: make ICLASS a possible field? +# Remove the segment override if any supplied, from an LEA +REMOVE_SEGMENT():: +AGEN=0 -> nothing +AGEN=1 -> REMOVE_SEGMENT_AGEN1() + +REMOVE_SEGMENT_AGEN1():: +SEG0=@ -> nothing +SEG0=SEGe() -> error + + +# need to emit a segment override if the segment is not the default segment for the operation. +# These are only meant for use with the things that do not use MODRM (like xlat, A0-A3 MOVs, and the string ops). +# (MODRM encoding handles this stuff much better). +OVERRIDE_SEG0():: +SEG0=@ -> SEG_OVD=0 +SEG0=XED_REG_DS -> SEG_OVD=0 +SEG0=XED_REG_CS -> SEG_OVD=1 +SEG0=XED_REG_ES -> SEG_OVD=3 +SEG0=XED_REG_FS -> SEG_OVD=4 +SEG0=XED_REG_GS -> SEG_OVD=5 +SEG0=XED_REG_SS -> SEG_OVD=6 + +OVERRIDE_SEG1():: +SEG1=@ -> SEG_OVD=0 +SEG1=XED_REG_DS -> SEG_OVD=0 +SEG1=XED_REG_CS -> SEG_OVD=1 +SEG1=XED_REG_ES -> SEG_OVD=3 +SEG1=XED_REG_FS -> SEG_OVD=4 +SEG1=XED_REG_GS -> SEG_OVD=5 +SEG1=XED_REG_SS -> SEG_OVD=6 + + + +REX_PREFIX_ENC():: +mode64 NOREX=0 NEEDREX=1 REXW[w] REXB[b] REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REX=1 REXW[w] REXB[b] REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w]=1 REXB[b] REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w] REXB[b]=1 REXX[x] REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w] REXB[b] REXX[x]=1 REXR[r] -> 0b0100 wrxb +mode64 NOREX=0 REXW[w] REXB[b] REXX[x] REXR[r]=1 -> 0b0100 wrxb +mode64 NOREX=1 NEEDREX=1 -> error +mode64 NOREX=1 REX=1 -> error +mode64 NOREX=1 REXW=1 -> error +mode64 NOREX=1 REXB=1 -> error +mode64 NOREX=1 REXX=1 -> error +mode64 NOREX=1 REXR=1 -> error +mode64 NEEDREX=0 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + +# If any REX bit shows up in 32 or 16b mode, we have an error. ensure everything is zero +mode32 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing +mode16 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + +# or die...1 +otherwise -> error + +# This checks that we didn't try to use a byte register that requires +# we do not have a rex with something else that requires we have a REX +# prefix. + +# FIXME: need to allow repeated prefixes + +# FIXME: optionally allow for prefix order to be specified (from decode) + +PREFIX_ENC():: +# create an "OR" of REFINING=2 and REP=2 +REP=2 -> 0xf2 no_return +REP=3 -> 0xf3 no_return +# +66_prefix -> 0x66 no_return +67_prefix -> 0x67 no_return +lock_prefix -> 0xf0 no_return +fs_prefix -> 0x64 no_return +gs_prefix -> 0x65 no_return +#################################################### +mode64 HINT=3 -> 0x2e no_return +mode64 HINT=4 -> 0x3e no_return +mode64 HINT=5 -> 0x3e no_return # CET NO-TRACK +##################################################### +not64 cs_prefix -> 0x2e no_return +not64 HINT=3 -> 0x2e no_return +not64 ds_prefix -> 0x3e no_return +not64 HINT=4 -> 0x3e no_return +not64 HINT=5 -> 0x3e no_return # CET NO-TRACK +not64 es_prefix -> 0x26 no_return +not64 ss_prefix -> 0x36 no_return +otherwise -> nothing + + +########################################################################## +# +# +# This is the encode version. It just sets DF64 for later use by the +# OSZ_NONTERM_ENC() nonterminal. +# +DF64():: +mode16 -> nothing +mode32 -> nothing +mode64 -> DF64=1 ### EOSZ=3 -- removed EOSZ=3 because it broke encoding pop 16b dx in 64b mode. + +# +# If an instruction pattern sets W to zero or 1, we make sure it also +# sets SKIP_OSZ=1 so that we do not do any overwrite of that value for +# the EOSZ computation. +# +OSZ_NONTERM_ENC():: +VEXVALID=0 mode16 EOSZ=1 -> nothing +VEXVALID=0 mode16 EOSZ=2 DF32=1 -> nothing + +# We don't use SKIP_OSZ=1 with the MOV_CR instructions but this is +# here for completeness. +#VEXVALID=0 mode16 EOSZ=2 DF32=0 SKIP_OSZ=1 -> nothing +#VEXVALID=0 mode16 EOSZ=2 DF32=0 SKIP_OSZ=0 -> 66_prefix +VEXVALID=0 mode16 EOSZ=2 DF32=0 -> 66_prefix + +#VEXVALID=0 mode32 EOSZ=1 SKIP_OSZ=1 -> nothing +#VEXVALID=0 mode32 EOSZ=1 SKIP_OSZ=0 -> 66_prefix +VEXVALID=0 mode32 EOSZ=1 -> 66_prefix + +VEXVALID=0 mode32 EOSZ=2 -> nothing + +#VEXVALID=0 mode64 EOSZ=1 SKIP_OSZ=1 -> nothing +#VEXVALID=0 mode64 EOSZ=1 SKIP_OSZ=0 -> 66_prefix +VEXVALID=0 mode64 EOSZ=1 -> 66_prefix + +VEXVALID=0 mode64 EOSZ=2 DF64=1 -> error +VEXVALID=0 mode64 EOSZ=2 DF64=0 -> nothing +VEXVALID=0 mode64 EOSZ=3 DF64=1 -> nothing + +#VEXVALID=0 mode64 EOSZ=3 DF64=0 SKIP_OSZ=1 -> nothing +#VEXVALID=0 mode64 EOSZ=3 DF64=0 SKIP_OSZ=0 -> REXW=1 +VEXVALID=0 mode64 EOSZ=3 DF64=0 -> REXW=1 +otherwise -> nothing + +# The REFINING66() decode version is required for when we have a 66 +# prefix that should not change the EOSZ. The REFINING66() decode +# nonterminal restores that EOSZ. +# +# This one, the REFINING66() encode version is required for +# compatibility, but it doesn't do anything. The EOSZ is an input to +# the endoder. +# +# Turn off the REP prefix in case we are switching forms. +REFINING66():: +otherwise -> nothing # norep works too +IGNORE66():: +otherwise -> nothing + +# Same for IMMUNE66() used for sttni/cmpxchg8B/cmpxchg16b. We do not want to emit a 66 prefix in 32b mode +IMMUNE66():: +mode16 -> EOSZ=2 DF32=1 +otherwise -> nothing + + +IMMUNE66_LOOP64():: +otherwise -> nothing + +IMMUNE_REXW():: +otherwise -> nothing + +CR_WIDTH():: +mode16 -> DF32=1 EOSZ=2 +mode32 -> nothing +mode64 -> DF64=1 EOSZ=3 + +FORCE64():: +otherwise -> DF64=1 EOSZ=3 + + +# the prefix encoder does all the required work. +BRANCH_HINT():: +otherwise -> nothing +# the prefix encoder does all the required work. +CET_NO_TRACK():: +otherwise -> nothing + +# end of xed-prefixes-encode.txt +########################################################################## + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-regs-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +xed_reg_enum_t SEGe():: +OUTREG=XED_REG_DS -> nothing +OUTREG=XED_REG_CS -> nothing +OUTREG=XED_REG_ES -> nothing +OUTREG=XED_REG_FS -> nothing +OUTREG=XED_REG_GS -> nothing +OUTREG=XED_REG_SS -> nothing + +xed_reg_enum_t GPR16e():: +OUTREG=XED_REG_AX -> nothing +OUTREG=XED_REG_BX -> nothing +OUTREG=XED_REG_CX -> nothing +OUTREG=XED_REG_DX -> nothing +OUTREG=XED_REG_SP -> nothing +OUTREG=XED_REG_BP -> nothing +OUTREG=XED_REG_SI -> nothing +OUTREG=XED_REG_DI -> nothing + + +xed_reg_enum_t GPR32e():: +mode32 OUTREG=GPR32e_m32() -> nothing +mode64 OUTREG=GPR32e_m64() -> nothing + + +xed_reg_enum_t GPR32e_m32():: +OUTREG=XED_REG_EAX -> nothing +OUTREG=XED_REG_EBX -> nothing +OUTREG=XED_REG_ECX -> nothing +OUTREG=XED_REG_EDX -> nothing +OUTREG=XED_REG_ESP -> nothing +OUTREG=XED_REG_EBP -> nothing +OUTREG=XED_REG_ESI -> nothing +OUTREG=XED_REG_EDI -> nothing + +xed_reg_enum_t GPR32e_m64():: +OUTREG=XED_REG_EAX -> nothing +OUTREG=XED_REG_EBX -> nothing +OUTREG=XED_REG_ECX -> nothing +OUTREG=XED_REG_EDX -> nothing +OUTREG=XED_REG_ESP -> nothing +OUTREG=XED_REG_EBP -> nothing +OUTREG=XED_REG_ESI -> nothing +OUTREG=XED_REG_EDI -> nothing +OUTREG=XED_REG_R8D -> nothing +OUTREG=XED_REG_R9D -> nothing +OUTREG=XED_REG_R10D -> nothing +OUTREG=XED_REG_R11D -> nothing +OUTREG=XED_REG_R12D -> nothing +OUTREG=XED_REG_R13D -> nothing +OUTREG=XED_REG_R14D -> nothing +OUTREG=XED_REG_R15D -> nothing + +xed_reg_enum_t GPR64e():: +OUTREG=XED_REG_RAX -> nothing +OUTREG=XED_REG_RBX -> nothing +OUTREG=XED_REG_RCX -> nothing +OUTREG=XED_REG_RDX -> nothing +OUTREG=XED_REG_RSP -> nothing +OUTREG=XED_REG_RBP -> nothing +OUTREG=XED_REG_RSI -> nothing +OUTREG=XED_REG_RDI -> nothing +OUTREG=XED_REG_R8 -> nothing +OUTREG=XED_REG_R9 -> nothing +OUTREG=XED_REG_R10 -> nothing +OUTREG=XED_REG_R11 -> nothing +OUTREG=XED_REG_R12 -> nothing +OUTREG=XED_REG_R13 -> nothing +OUTREG=XED_REG_R14 -> nothing +OUTREG=XED_REG_R15 -> nothing + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +######## XOP ################################# +SEQUENCE XOP_ENC_BIND + XOP_TYPE_ENC_BIND + VEX_REXR_ENC_BIND + XOP_REXXB_ENC_BIND + XOP_MAP_ENC_BIND + VEX_REG_ENC_BIND + VEX_ESCVL_ENC_BIND + +SEQUENCE XOP_ENC_EMIT + XOP_TYPE_ENC_EMIT + VEX_REXR_ENC_EMIT + XOP_REXXB_ENC_EMIT + XOP_MAP_ENC_EMIT + VEX_REG_ENC_EMIT + VEX_ESCVL_ENC_EMIT + +############################################## + +VEXED_REX():: +VEXVALID=3 -> XOP_ENC() + +XOP_TYPE_ENC():: +XMAP8 -> 0x8F +XMAP9 -> 0x8F +XMAPA -> 0x8F +otherwise -> error + +XOP_MAP_ENC():: +XMAP8 REXW[w] -> 0b0_1000 w +XMAP9 REXW[w] -> 0b0_1001 w +XMAPA REXW[w] -> 0b0_1010 w +otherwise -> error + +XOP_REXXB_ENC():: +mode64 REXX=0 REXB=0 -> 0b11 +mode64 REXX=1 REXB=0 -> 0b01 +mode64 REXX=0 REXB=1 -> 0b10 +mode64 REXX=1 REXB=1 -> 0b00 +not64 REXX=0 REXB=0 -> 0b11 +not64 REXX=1 REXB=0 -> error +not64 REXX=0 REXB=1 -> error +not64 REXX=1 REXB=1 -> error +otherwise -> nothing + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-reg-check-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BND_R_CHECK():: +REXR=0 REG=0x0 -> nothing +REXR=0 REG=0x1 -> nothing +REXR=0 REG=0x2 -> nothing +REXR=0 REG=0x3 -> nothing +REXR=0 REG=0x4 -> error +REXR=0 REG=0x5 -> error +REXR=0 REG=0x6 -> error +REXR=0 REG=0x7 -> error +REXR=1 REG=0x0 -> error +REXR=1 REG=0x1 -> error +REXR=1 REG=0x2 -> error +REXR=1 REG=0x3 -> error +REXR=1 REG=0x4 -> error +REXR=1 REG=0x5 -> error +REXR=1 REG=0x6 -> error +REXR=1 REG=0x7 -> error + +BND_B_CHECK():: +REXB=0 RM=0x0 -> nothing +REXB=0 RM=0x1 -> nothing +REXB=0 RM=0x2 -> nothing +REXB=0 RM=0x3 -> nothing +REXB=0 RM=0x4 -> error +REXB=0 RM=0x5 -> error +REXB=0 RM=0x6 -> error +REXB=0 RM=0x7 -> error +REXB=1 RM=0x0 -> error +REXB=1 RM=0x1 -> error +REXB=1 RM=0x2 -> error +REXB=1 RM=0x3 -> error +REXB=1 RM=0x4 -> error +REXB=1 RM=0x5 -> error +REXB=1 RM=0x6 -> error +REXB=1 RM=0x7 -> error + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-vex-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() # not calling tree splitter! AVX instructions must set VEXVALID=1 + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + VEXED_REX_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + VEXED_REX_EMIT() + INSTRUCTIONS_EMIT() + +VEXED_REX():: +VEXVALID=0 -> REX_PREFIX_ENC() +VEXVALID=1 -> NEWVEX_ENC() + + +################################################# +SEQUENCE NEWVEX_ENC_BIND + VEX_TYPE_ENC_BIND + VEX_REXR_ENC_BIND + VEX_REXXB_ENC_BIND + VEX_MAP_ENC_BIND + VEX_REG_ENC_BIND + VEX_ESCVL_ENC_BIND + +SEQUENCE NEWVEX_ENC_EMIT + VEX_TYPE_ENC_EMIT + VEX_REXR_ENC_EMIT + VEX_REXXB_ENC_EMIT + VEX_MAP_ENC_EMIT + VEX_REG_ENC_EMIT + VEX_ESCVL_ENC_EMIT + +############################################## +VEX_TYPE_ENC():: +REXX=1 -> 0xC4 VEX_C4=1 +REXB=1 -> 0xC4 VEX_C4=1 +MAP=0 -> 0xC4 VEX_C4=1 +MAP=2 -> 0xC4 VEX_C4=1 +MAP=3 -> 0xC4 VEX_C4=1 +REXW=1 -> 0xC4 VEX_C4=1 +otherwise -> 0xC5 VEX_C4=0 + +VEX_REXR_ENC():: +mode64 REXR=1 -> 0b0 +mode64 REXR=0 -> 0b1 +not64 REXR=1 -> error +not64 REXR=0 -> 0b1 + +VEX_REXXB_ENC():: +mode64 VEX_C4=1 REXX=0 REXB=0 -> 0b11 +mode64 VEX_C4=1 REXX=1 REXB=0 -> 0b01 +mode64 VEX_C4=1 REXX=0 REXB=1 -> 0b10 +mode64 VEX_C4=1 REXX=1 REXB=1 -> 0b00 +not64 VEX_C4=1 REXX=0 REXB=0 -> 0b11 +not64 VEX_C4=1 REXX=1 REXB=0 -> error +not64 VEX_C4=1 REXX=0 REXB=1 -> error +not64 VEX_C4=1 REXX=1 REXB=1 -> error +otherwise -> nothing + +# also emits W + +VEX_MAP_ENC():: +VEX_C4=1 MAP=0 REXW[w] -> 0b0_0000 w +VEX_C4=1 MAP=1 REXW[w] -> 0b0_0001 w +VEX_C4=1 MAP=2 REXW[w] -> 0b0_0010 w +VEX_C4=1 MAP=3 REXW[w] -> 0b0_0011 w +otherwise -> nothing + +# for VEX C5, VEXDEST3 MUST be 1 in 32b mode +VEX_REG_ENC():: +mode64 VEXDEST3[u] VEXDEST210[ddd] -> u_ddd +not64 VEXDEST3[u] VEXDEST210[ddd] -> 1_ddd + + +# FOR VEX'ed instructions, I need to turn off the normal REX prefix +# encoder. Ideally, I could use fields names other than REX{WRXB}, +# but the register lookup functions need those names. I can get away +# with using different names for the f2/f3/66 refining legacy prefixes +# since they are only referenced by the AVX instructions. + +VEX_ESCVL_ENC():: +VL128 VNP -> 0b000 +VL128 V66 -> 0b001 +VL128 VF3 -> 0b010 +VL128 VF2 -> 0b011 +VL256 VNP -> 0b100 +VL256 V66 -> 0b101 +VL256 VF3 -> 0b110 +VL256 VF2 -> 0b111 + +############################################################################## + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-imm-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SE_IMM8():: +true ESRC[ssss] UIMM0[dddd] -> ssss_dddd + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/vsib-addressing-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SEQUENCE VMODRM_XMM_BIND + VMODRM_MOD_ENCODE_BIND() + VSIB_ENC_BASE_BIND() + VSIB_ENC_INDEX_XMM_BIND() + VSIB_ENC_SCALE_BIND() + VSIB_ENC_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + DISP_NT_BIND() + +SEQUENCE VMODRM_YMM_BIND + VMODRM_MOD_ENCODE_BIND() + VSIB_ENC_BASE_BIND() + VSIB_ENC_INDEX_YMM_BIND() + VSIB_ENC_SCALE_BIND() + VSIB_ENC_BIND() + SEGMENT_DEFAULT_ENCODE_BIND() + SEGMENT_ENCODE_BIND() + DISP_NT_BIND() + +# MODRM.MOD is emitted as part of the instruction +SEQUENCE VMODRM_XMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + +SEQUENCE VMODRM_YMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + +###################################### +VMODRM_MOD_ENCODE():: + +# (1) no base with rBP/r13 +# Add a fake 1B displacement to rBP and r13 if they do not have one already +eamode32 DISP_WIDTH=0 BASE0=ArBP() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +eamode32 DISP_WIDTH=0 BASE0=Ar13() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION + +eamode64 DISP_WIDTH=0 BASE0=ArBP() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION +eamode64 DISP_WIDTH=0 BASE0=Ar13() -> MOD=1 DISP_WIDTH=8 DISP=0 # ARG MODIFICATION + +# (2) no disp with most base regs +# All these 32b and 64b can handle no displacement +eamode32 DISP_WIDTH=0 BASE0=ArAX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArBX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArCX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArDX() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArSI() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArDI() -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=ArSP() -> MOD=0 + +eamode32 DISP_WIDTH=0 BASE0=Ar8() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar9() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar10() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar11() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar12() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar14() mode64 -> MOD=0 +eamode32 DISP_WIDTH=0 BASE0=Ar15() mode64 -> MOD=0 + +# rBP and r13 are handled above +eamode64 DISP_WIDTH=0 BASE0=ArAX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArBX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArCX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArDX() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArSI() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArDI() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=ArSP() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar8() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar9() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar10() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar11() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar12() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar14() -> MOD=0 +eamode64 DISP_WIDTH=0 BASE0=Ar15() -> MOD=0 + +# (3) 8b displacement +eamode32 DISP_WIDTH=8 -> MOD=1 +eamode64 DISP_WIDTH=8 BASE0=GPR64e() -> MOD=1 + + +# (4) 32b displacement with no base or some base +eamode32 DISP_WIDTH=32 BASE0=@ -> MOD=0 #no base +eamode32 DISP_WIDTH=32 BASE0=GPR32e() -> MOD=2 #some base, not RIP +eamode64 DISP_WIDTH=32 BASE0=@ -> MOD=0 #no base + +eamode64 DISP_WIDTH=32 BASE0=ArAX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArBX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArCX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArDX() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArSI() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArDI() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArSP() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=ArBP() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar8() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar9() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar10() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar11() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar12() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar13() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar14() -> MOD=2 +eamode64 DISP_WIDTH=32 BASE0=Ar15() -> MOD=2 + +otherwise -> error + +VSIB_ENC_BASE():: + BASE0=ArAX() -> REXB=0 SIBBASE=0 + BASE0=ArCX() -> REXB=0 SIBBASE=1 + BASE0=ArDX() -> REXB=0 SIBBASE=2 + BASE0=ArBX() -> REXB=0 SIBBASE=3 + BASE0=ArSP() -> REXB=0 SIBBASE=4 + + BASE0=@ -> DISP_WIDTH_32() REXB=0 SIBBASE=5 + + # RBP/EBP or r13/r13d must have a displacement + BASE0=ArBP() -> DISP_WIDTH_8_32() REXB=0 SIBBASE=5 + + BASE0=Ar13() -> DISP_WIDTH_8_32() REXB=1 SIBBASE=5 + + + BASE0=ArSI() -> REXB=0 SIBBASE=6 + BASE0=ArDI() -> REXB=0 SIBBASE=7 + BASE0=Ar8() -> REXB=1 SIBBASE=0 + BASE0=Ar9() -> REXB=1 SIBBASE=1 + BASE0=Ar10() -> REXB=1 SIBBASE=2 + BASE0=Ar11() -> REXB=1 SIBBASE=3 + BASE0=Ar12() -> REXB=1 SIBBASE=4 + + BASE0=Ar14() -> REXB=1 SIBBASE=6 + BASE0=Ar15() -> REXB=1 SIBBASE=7 + otherwise -> error + + + + +VSIB_ENC_SCALE():: + SCALE=0 -> SIBSCALE=0 + SCALE=1 -> SIBSCALE=0 + SCALE=2 -> SIBSCALE=1 + SCALE=4 -> SIBSCALE=2 + SCALE=8 -> SIBSCALE=3 + otherwise -> error + +VSIB_ENC():: + true SIBBASE[bbb] SIBINDEX[iii] SIBSCALE[ss] -> ss_iii_bbb + + +VSIB_ENC_INDEX_XMM():: +INDEX=XED_REG_XMM0 -> REXX=0 SIBINDEX=0 +INDEX=XED_REG_XMM1 -> REXX=0 SIBINDEX=1 +INDEX=XED_REG_XMM2 -> REXX=0 SIBINDEX=2 +INDEX=XED_REG_XMM3 -> REXX=0 SIBINDEX=3 +INDEX=XED_REG_XMM4 -> REXX=0 SIBINDEX=4 +INDEX=XED_REG_XMM5 -> REXX=0 SIBINDEX=5 +INDEX=XED_REG_XMM6 -> REXX=0 SIBINDEX=6 +INDEX=XED_REG_XMM7 -> REXX=0 SIBINDEX=7 +INDEX=XED_REG_XMM8 -> REXX=1 SIBINDEX=0 +INDEX=XED_REG_XMM9 -> REXX=1 SIBINDEX=1 +INDEX=XED_REG_XMM10 -> REXX=1 SIBINDEX=2 +INDEX=XED_REG_XMM11 -> REXX=1 SIBINDEX=3 +INDEX=XED_REG_XMM12 -> REXX=1 SIBINDEX=4 +INDEX=XED_REG_XMM13 -> REXX=1 SIBINDEX=5 +INDEX=XED_REG_XMM14 -> REXX=1 SIBINDEX=6 +INDEX=XED_REG_XMM15 -> REXX=1 SIBINDEX=7 + + +VSIB_ENC_INDEX_YMM():: +INDEX=XED_REG_YMM0 -> REXX=0 SIBINDEX=0 +INDEX=XED_REG_YMM1 -> REXX=0 SIBINDEX=1 +INDEX=XED_REG_YMM2 -> REXX=0 SIBINDEX=2 +INDEX=XED_REG_YMM3 -> REXX=0 SIBINDEX=3 +INDEX=XED_REG_YMM4 -> REXX=0 SIBINDEX=4 +INDEX=XED_REG_YMM5 -> REXX=0 SIBINDEX=5 +INDEX=XED_REG_YMM6 -> REXX=0 SIBINDEX=6 +INDEX=XED_REG_YMM7 -> REXX=0 SIBINDEX=7 +INDEX=XED_REG_YMM8 -> REXX=1 SIBINDEX=0 +INDEX=XED_REG_YMM9 -> REXX=1 SIBINDEX=1 +INDEX=XED_REG_YMM10 -> REXX=1 SIBINDEX=2 +INDEX=XED_REG_YMM11 -> REXX=1 SIBINDEX=3 +INDEX=XED_REG_YMM12 -> REXX=1 SIBINDEX=4 +INDEX=XED_REG_YMM13 -> REXX=1 SIBINDEX=5 +INDEX=XED_REG_YMM14 -> REXX=1 SIBINDEX=6 +INDEX=XED_REG_YMM15 -> REXX=1 SIBINDEX=7 + + +DISP_WIDTH_8_32():: +DISP_WIDTH=8 -> nothing +DISP_WIDTH=32 -> nothing + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knm/knm-disp8-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +NELEM_TUPLE1_4X():: +otherwise -> nothing + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-evex-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# These bind the operand deciders that control the encoding +SEQUENCE ISA_BINDINGS + FIXUP_EOSZ_ENC_BIND() + FIXUP_EASZ_ENC_BIND() + ASZ_NONTERM_BIND() + INSTRUCTIONS_BIND() # not calling tree splitter! AVX instructions must set VEXVALID=1 + OSZ_NONTERM_ENC_BIND() # OSZ must be after the instructions so that DF64 is bound (and before any prefixes obviously) + PREFIX_ENC_BIND() + VEXED_REX_BIND() + +# These emit the bits and bytes that make up the encoding +SEQUENCE ISA_EMIT + PREFIX_ENC_EMIT() + VEXED_REX_EMIT() + INSTRUCTIONS_EMIT() + +VEXED_REX():: +VEXVALID=2 -> EVEX_ENC() + + +################################################# +SEQUENCE EVEX_ENC_BIND + # R,X,B R map(mmm) (byte 1) + # W, vvvv, U, pp (byte 2) + # z, LL/RC, b V', aaa ( byte 3) + EVEX_62_REXR_ENC_BIND + EVEX_REXX_ENC_BIND + EVEX_REXB_ENC_BIND + EVEX_REXRR_ENC_BIND + EVEX_MAP_ENC_BIND + EVEX_REXW_VVVV_ENC_BIND + EVEX_UPP_ENC_BIND + EVEX_LL_ENC_BIND + AVX512_EVEX_BYTE3_ENC_BIND + + +SEQUENCE EVEX_ENC_EMIT + EVEX_62_REXR_ENC_EMIT + EVEX_REXX_ENC_EMIT + EVEX_REXB_ENC_EMIT + EVEX_REXRR_ENC_EMIT + EVEX_MAP_ENC_EMIT + EVEX_REXW_VVVV_ENC_EMIT + EVEX_UPP_ENC_EMIT + EVEX_LL_ENC_EMIT + AVX512_EVEX_BYTE3_ENC_EMIT + + +EVEX_62_REXR_ENC():: +mode64 REXR=1 -> 0x62 0b0 +mode64 REXR=0 -> 0x62 0b1 +mode32 REXR=1 -> error +mode32 REXR=0 -> 0x62 0b1 + +EVEX_REXX_ENC():: +mode64 REXX=1 -> 0b0 +mode64 REXX=0 -> 0b1 +mode32 REXX=1 -> error +mode32 REXX=0 -> 0b1 + +EVEX_REXB_ENC():: +mode64 REXB=1 -> 0b0 +mode64 REXB=0 -> 0b1 +mode32 REXB=1 -> error +mode32 REXB=0 -> 0b1 + +EVEX_REXRR_ENC():: +mode64 REXRR=1 -> 0b0 +mode64 REXRR=0 -> 0b1 +mode32 REXRR=1 -> error +mode32 REXRR=0 -> 0b1 + +EVEX_MAP_ENC():: +MAP=0 -> 0b0000 +MAP=1 -> 0b0001 +MAP=2 -> 0b0010 +MAP=3 -> 0b0011 + +EVEX_REXW_VVVV_ENC():: +true REXW[w] VEXDEST3[u] VEXDEST210[ddd] -> w u_ddd + +# emit the EVEX.U=1 with the EVEX.pp field +EVEX_UPP_ENC():: +VNP -> 0b100 +V66 -> 0b101 +VF3 -> 0b110 +VF2 -> 0b111 + +EVEX_LL_ENC():: +ROUNDC=0 SAE=0 VL128 -> LLRC=0 +ROUNDC=0 SAE=0 VL256 -> LLRC=1 +ROUNDC=0 SAE=0 VL512 -> LLRC=2 + +# scalars (XED has scalars as VL128) +ROUNDC=0 SAE=1 VL128 -> LLRC=0 BCRC=1 # sae only, no rounding +ROUNDC=1 SAE=1 VL128 -> LLRC=0 BCRC=1 # rounding only supported with sae +ROUNDC=2 SAE=1 VL128 -> LLRC=1 BCRC=1 # rounding only supported with sae +ROUNDC=3 SAE=1 VL128 -> LLRC=2 BCRC=1 # rounding only supported with sae +ROUNDC=4 SAE=1 VL128 -> LLRC=3 BCRC=1 # rounding only supported with sae + +# everything else (must be VL512) +ROUNDC=0 SAE=1 VL512 -> LLRC=0 BCRC=1 # sae only, no rounding +ROUNDC=1 SAE=1 VL512 -> LLRC=0 BCRC=1 # rounding only supported with sae +ROUNDC=2 SAE=1 VL512 -> LLRC=1 BCRC=1 # rounding only supported with sae +ROUNDC=3 SAE=1 VL512 -> LLRC=2 BCRC=1 # rounding only supported with sae +ROUNDC=4 SAE=1 VL512 -> LLRC=3 BCRC=1 # rounding only supported with sae + + +AVX512_EVEX_BYTE3_ENC():: +ZEROING[z] LLRC[nn] BCRC[b] VEXDEST4=0 MASK[aaa] -> z_nn_b 0b1 aaa +ZEROING[z] LLRC[nn] BCRC[b] VEXDEST4=1 MASK[aaa] -> z_nn_b 0b0 aaa + + + +################################################# +SEQUENCE NEWVEX3_ENC_BIND + VEX_TYPE_ENC_BIND + VEX_REXR_ENC_BIND + VEX_REXXB_ENC_BIND + VEX_MAP_ENC_BIND + VEX_REG_ENC_BIND + VEX_ESCVL_ENC_BIND + +SEQUENCE NEWVEX3_ENC_EMIT + VEX_TYPE_ENC_EMIT + VEX_REXR_ENC_EMIT + VEX_REXXB_ENC_EMIT + VEX_MAP_ENC_EMIT + VEX_REG_ENC_EMIT + VEX_ESCVL_ENC_EMIT + + + +############################################################################## + +AVX512_ROUND():: +ROUNDC=1 -> LLRC=0 BCRC=1 +ROUNDC=2 -> LLRC=1 BCRC=1 +ROUNDC=3 -> LLRC=2 BCRC=1 +ROUNDC=4 -> LLRC=3 BCRC=1 + +SAE():: +SAE=1 -> BCRC=1 +SAE=0 -> BCRC=0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-disp8-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ESIZE_128_BITS():: +otherwise -> nothing +ESIZE_64_BITS():: +otherwise -> nothing +ESIZE_32_BITS():: +otherwise -> nothing +ESIZE_16_BITS():: +otherwise -> nothing +ESIZE_8_BITS():: +otherwise -> nothing +ESIZE_4_BITS():: +otherwise -> nothing +ESIZE_2_BITS():: +otherwise -> nothing +ESIZE_1_BITS():: +otherwise -> nothing + +NELEM_MOVDDUP():: +otherwise -> nothing +NELEM_FULLMEM():: +otherwise -> nothing + +NELEM_HALFMEM():: +otherwise -> nothing + +NELEM_QUARTERMEM():: +otherwise -> nothing + +NELEM_EIGHTHMEM():: +otherwise -> nothing + +NELEM_GPR_READER_BYTE():: +otherwise -> nothing +NELEM_GPR_READER_WORD():: +otherwise -> nothing +NELEM_GPR_WRITER_LDOP_D():: +otherwise -> nothing +NELEM_GPR_WRITER_LDOP_Q():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE_BYTE():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE_WORD():: +otherwise -> nothing +NELEM_TUPLE1_BYTE():: +otherwise -> nothing +NELEM_TUPLE1_WORD():: +otherwise -> nothing + +NELEM_SCALAR():: +otherwise -> nothing +NELEM_TUPLE1_SUBDWORD():: +otherwise -> nothing +NELEM_GPR_READER():: +otherwise -> nothing +NELEM_GPR_READER_SUBDWORD():: +otherwise -> nothing +NELEM_GPR_WRITER_LDOP():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE():: +otherwise -> nothing +NELEM_GPR_WRITER_STORE_SUBDWORD():: +otherwise -> nothing + +NELEM_MEM128():: +BCAST!=0 -> error +otherwise -> BCRC=0 + +# TUPLE1,2,4,8, FULL and HALF + +NELEM_TUPLE1():: +otherwise -> nothing + +NELEM_GSCAT():: +otherwise -> nothing + +NELEM_TUPLE2():: +otherwise -> nothing + +NELEM_TUPLE4():: +otherwise -> nothing + +NELEM_TUPLE8():: +otherwise -> nothing + +# these have broadcasting + +NELEM_FULL():: +BCAST!=0 -> BCRC=1 +otherwise -> BCRC=0 + +NELEM_HALF():: +BCAST!=0 -> BCRC=1 +otherwise -> BCRC=0 + +FIX_ROUND_LEN512():: +otherwise -> nothing +FIX_ROUND_LEN128():: +otherwise -> nothing + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-addressing-enc.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +SEQUENCE UISA_VMODRM_ZMM_BIND + VMODRM_MOD_ENCODE_BIND() # FROM HSW + VSIB_ENC_BASE_BIND() # FROM HSW + UISA_ENC_INDEX_ZMM_BIND() + VSIB_ENC_SCALE_BIND() # FROM HSW + VSIB_ENC_BIND() # FROM HSW + SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA + SEGMENT_ENCODE_BIND() # FROM BASE ISA + DISP_NT_BIND() # FROM BASE ISA +SEQUENCE UISA_VMODRM_YMM_BIND + VMODRM_MOD_ENCODE_BIND() # FROM HSW + VSIB_ENC_BASE_BIND() # FROM HSW + UISA_ENC_INDEX_YMM_BIND() + VSIB_ENC_SCALE_BIND() # FROM HSW + VSIB_ENC_BIND() # FROM HSW + SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA + SEGMENT_ENCODE_BIND() # FROM BASE ISA + DISP_NT_BIND() # FROM BASE ISA +SEQUENCE UISA_VMODRM_XMM_BIND + VMODRM_MOD_ENCODE_BIND() # FROM HSW + VSIB_ENC_BASE_BIND() # FROM HSW + UISA_ENC_INDEX_XMM_BIND() + VSIB_ENC_SCALE_BIND() # FROM HSW + VSIB_ENC_BIND() # FROM HSW + SEGMENT_DEFAULT_ENCODE_BIND() # FROM BASE ISA + SEGMENT_ENCODE_BIND() # FROM BASE ISA + DISP_NT_BIND() # FROM BASE ISA + +# For now, ignoring the difference in x/y/zmm for the index register. Could +# split these. +SEQUENCE UISA_VMODRM_ZMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() +SEQUENCE UISA_VMODRM_YMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() +SEQUENCE UISA_VMODRM_XMM_EMIT + VSIB_ENC_EMIT() + DISP_NT_EMIT() + +###################################### + + + +UISA_ENC_INDEX_ZMM():: +INDEX=XED_REG_ZMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 +INDEX=XED_REG_ZMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 +INDEX=XED_REG_ZMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 +INDEX=XED_REG_ZMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 +INDEX=XED_REG_ZMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 +INDEX=XED_REG_ZMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 +INDEX=XED_REG_ZMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 +INDEX=XED_REG_ZMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 +INDEX=XED_REG_ZMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 +INDEX=XED_REG_ZMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 +INDEX=XED_REG_ZMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 +INDEX=XED_REG_ZMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 +INDEX=XED_REG_ZMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 +INDEX=XED_REG_ZMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 +INDEX=XED_REG_ZMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 +INDEX=XED_REG_ZMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 +INDEX=XED_REG_ZMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 +INDEX=XED_REG_ZMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 +INDEX=XED_REG_ZMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 +INDEX=XED_REG_ZMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 +INDEX=XED_REG_ZMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 +INDEX=XED_REG_ZMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 +INDEX=XED_REG_ZMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 +INDEX=XED_REG_ZMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 +INDEX=XED_REG_ZMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 +INDEX=XED_REG_ZMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 +INDEX=XED_REG_ZMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 +INDEX=XED_REG_ZMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 +INDEX=XED_REG_ZMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 +INDEX=XED_REG_ZMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 +INDEX=XED_REG_ZMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 +INDEX=XED_REG_ZMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 +UISA_ENC_INDEX_YMM():: +INDEX=XED_REG_YMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 +INDEX=XED_REG_YMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 +INDEX=XED_REG_YMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 +INDEX=XED_REG_YMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 +INDEX=XED_REG_YMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 +INDEX=XED_REG_YMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 +INDEX=XED_REG_YMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 +INDEX=XED_REG_YMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 +INDEX=XED_REG_YMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 +INDEX=XED_REG_YMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 +INDEX=XED_REG_YMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 +INDEX=XED_REG_YMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 +INDEX=XED_REG_YMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 +INDEX=XED_REG_YMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 +INDEX=XED_REG_YMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 +INDEX=XED_REG_YMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 +INDEX=XED_REG_YMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 +INDEX=XED_REG_YMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 +INDEX=XED_REG_YMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 +INDEX=XED_REG_YMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 +INDEX=XED_REG_YMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 +INDEX=XED_REG_YMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 +INDEX=XED_REG_YMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 +INDEX=XED_REG_YMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 +INDEX=XED_REG_YMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 +INDEX=XED_REG_YMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 +INDEX=XED_REG_YMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 +INDEX=XED_REG_YMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 +INDEX=XED_REG_YMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 +INDEX=XED_REG_YMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 +INDEX=XED_REG_YMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 +INDEX=XED_REG_YMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 +UISA_ENC_INDEX_XMM():: +INDEX=XED_REG_XMM0 -> VEXDEST4=0 REXX=0 SIBINDEX=0 +INDEX=XED_REG_XMM1 -> VEXDEST4=0 REXX=0 SIBINDEX=1 +INDEX=XED_REG_XMM2 -> VEXDEST4=0 REXX=0 SIBINDEX=2 +INDEX=XED_REG_XMM3 -> VEXDEST4=0 REXX=0 SIBINDEX=3 +INDEX=XED_REG_XMM4 -> VEXDEST4=0 REXX=0 SIBINDEX=4 +INDEX=XED_REG_XMM5 -> VEXDEST4=0 REXX=0 SIBINDEX=5 +INDEX=XED_REG_XMM6 -> VEXDEST4=0 REXX=0 SIBINDEX=6 +INDEX=XED_REG_XMM7 -> VEXDEST4=0 REXX=0 SIBINDEX=7 +INDEX=XED_REG_XMM8 -> VEXDEST4=0 REXX=1 SIBINDEX=0 +INDEX=XED_REG_XMM9 -> VEXDEST4=0 REXX=1 SIBINDEX=1 +INDEX=XED_REG_XMM10 -> VEXDEST4=0 REXX=1 SIBINDEX=2 +INDEX=XED_REG_XMM11 -> VEXDEST4=0 REXX=1 SIBINDEX=3 +INDEX=XED_REG_XMM12 -> VEXDEST4=0 REXX=1 SIBINDEX=4 +INDEX=XED_REG_XMM13 -> VEXDEST4=0 REXX=1 SIBINDEX=5 +INDEX=XED_REG_XMM14 -> VEXDEST4=0 REXX=1 SIBINDEX=6 +INDEX=XED_REG_XMM15 -> VEXDEST4=0 REXX=1 SIBINDEX=7 +INDEX=XED_REG_XMM16 -> VEXDEST4=1 REXX=0 SIBINDEX=0 +INDEX=XED_REG_XMM17 -> VEXDEST4=1 REXX=0 SIBINDEX=1 +INDEX=XED_REG_XMM18 -> VEXDEST4=1 REXX=0 SIBINDEX=2 +INDEX=XED_REG_XMM19 -> VEXDEST4=1 REXX=0 SIBINDEX=3 +INDEX=XED_REG_XMM20 -> VEXDEST4=1 REXX=0 SIBINDEX=4 +INDEX=XED_REG_XMM21 -> VEXDEST4=1 REXX=0 SIBINDEX=5 +INDEX=XED_REG_XMM22 -> VEXDEST4=1 REXX=0 SIBINDEX=6 +INDEX=XED_REG_XMM23 -> VEXDEST4=1 REXX=0 SIBINDEX=7 +INDEX=XED_REG_XMM24 -> VEXDEST4=1 REXX=1 SIBINDEX=0 +INDEX=XED_REG_XMM25 -> VEXDEST4=1 REXX=1 SIBINDEX=1 +INDEX=XED_REG_XMM26 -> VEXDEST4=1 REXX=1 SIBINDEX=2 +INDEX=XED_REG_XMM27 -> VEXDEST4=1 REXX=1 SIBINDEX=3 +INDEX=XED_REG_XMM28 -> VEXDEST4=1 REXX=1 SIBINDEX=4 +INDEX=XED_REG_XMM29 -> VEXDEST4=1 REXX=1 SIBINDEX=5 +INDEX=XED_REG_XMM30 -> VEXDEST4=1 REXX=1 SIBINDEX=6 +INDEX=XED_REG_XMM31 -> VEXDEST4=1 REXX=1 SIBINDEX=7 + + + + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-evex-enc-map5-and-6.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# augment EVEX_MAP_ENC() in avx512f + +EVEX_MAP_ENC():: +MAP=4 -> error +MAP=5 -> 0b0101 +MAP=6 -> 0b0110 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-evex-disp8-enc-fp16.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +NELEM_QUARTER():: +otherwise -> nothing diff --git a/CodeVirtualizer/build/obj/dgen/all-extra-widths.txt b/CodeVirtualizer/build/obj/dgen/all-extra-widths.txt new file mode 100644 index 0000000..2cc402f --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-extra-widths.txt @@ -0,0 +1,119 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/oc2-extras.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +# ssz, asz are new oc2 widths +# pseudo is a new oc2 width +# +# col0: reg or nt +# col1: regname or nt name +# col2: oc2 width +# +# +imm_const AGEN pseudo +reg AH b +reg AL b +reg AX w +reg CL b +reg CR0 y +reg CS w +reg DS w +reg DX w +reg EAX d +reg EBX d +reg ECX d +reg EDX d +reg EIP d +reg ES w +reg FS w +reg GDTR pseudo +reg GS w +reg IDTR pseudo +reg LDTR pseudo +reg MSRS pseudo +reg MXCSR d +reg RAX q +reg RBX q +reg RCX q +reg RDX q +reg R11 q +reg RIP q +reg XCR0 q +reg SS w +reg TR pseudo +reg TSC pseudo +reg TSCAUX pseudo +reg X87CONTROL pseudo +reg X87POP pseudo +reg X87POP2 pseudo +reg X87PUSH pseudo +reg X87STATUS pseudo +reg X87TAG pseudo +reg X87TOP pseudo +# +nt ArBP asz +nt ArAX asz +nt ArBX asz +nt ArCX asz +nt ArDI asz +nt ArSI asz +nt CR_R y +nt DR_R y +nt GPR16_B w +nt GPR16_R w +nt GPR32_B d +nt GPR32_R d +nt GPR64_B q +nt GPR64_R q +nt GPR8_B b +nt GPR8_R b +nt GPRv_B v +nt GPRv_R v +nt GPRy_B y +nt GPRy_R y +nt GPRz_B z +nt GPRz_R z +nt GPRv_SB v +nt GPRv_SR v +nt GPR64_SB q +nt GPR64_SR q +nt GPR32_SB d +nt GPR32_SR d +nt GPR16_SB w +nt GPR16_SR w +nt GPR8_SB b +nt GPR8_SR b +nt OeAX v +nt OeBP v +nt OeBX v +nt OeCX v +nt OeDI v +nt OeDX v +nt OeSI v +nt OeSP v +nt OrAX v +nt OrBP v +nt OrDX v +nt OrSP v +nt SEG w +nt SrSP ssz +nt rFLAGS y +nt rIP y diff --git a/CodeVirtualizer/build/obj/dgen/all-fields.txt b/CodeVirtualizer/build/obj/dgen/all-fields.txt new file mode 100644 index 0000000..673f01e --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-fields.txt @@ -0,0 +1,442 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# @file xed-fields.txt + + +# visibilities are one of [EXPLICIT|IMPLICIT|SUPPRESSED] + +# Major properties of the fields are determined by the columns with +# the content {EI,EO} or {DI,DO,DS}. EI is encoder inputs and EO is +# for encoder outputs. DI is decoder inputs, DO is decoder +# outputs. And DS means "decoder skip" and is used for fields that +# show up in instruction pattern constraints but should be completely +# ignored by the decoder. + + +# INTERNAL means that the field is excluded from the instructions' +# operands array template. + + + +# ==== ====== ==== ========= ========== +# scalar default +# name array type bit-width visibility +# ==== ====== ==== ========= ========== +SEG_OVD SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO # FIXME: DO_EO? always an output + +# HINT: 0=no hint, +# 1=CS PREFIX OBSERVED (NOT TAKEN) +# 2=DS PREFIX OBSERVED (TAKEN) +# 3=NOT TAKEN HINT VALIDATED for a BRANCH +# 4=TAKEN HINT VALIDATED for a BRANCH +HINT SCALAR xed_bits_t 3 SUPPRESSED NOPRINT PUBLIC DO EI +# do not do encoder chip checking for the encode request +ENCODE_FORCE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + +LOCK SCALAR xed_bits_t 1 SUPPRESSED PRINT PUBLIC DO EO + +NEED_MEMDISP SCALAR xed_bits_t 6 SUPPRESSED NOPRINT INTERNAL DO EO + +DISP SCALAR xed_int64_t 64 SUPPRESSED NOPRINT INTERNAL DO EI # MEMORY DISPLACEMENT + +DISP_WIDTH SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT PUBLIC DO EI # in bytes FIXME: could use log2 + +BRDISP_WIDTH SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT INTERNAL DO EI # in bytes FIXME: could use log2 + +# DF32 is for MOV_CR & CR_WIDTH() NTs +DF32 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +DF64 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# NOREX is an unfortunate thing. It is only required to prevent +# encoding illegal instructions that have REX prefixes and use the +# AH/BH/CH/DH registers. It was not used for decoding + +NOREX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +NEEDREX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +REX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXW SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +REXB SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# refining must be used to interpret the REP output of decode +REP SCALAR xed_bits_t 2 SUPPRESSED PRINT PUBLIC DO EO # 0=no-rep, 2=F2, 3=F3 +OSZ SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +PREFIX66 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +ASZ SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# effective operand size and address size +EOSZ SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DO EI +EASZ SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DO EI + + + +#MODRM fields +MOD SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO +REG SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +# SRM is for partial-byte opcodes that capture a RM-like field. +SRM SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +RM SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +# Machine mode, addressing mode , stack addressing mode + +REALMODE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI +CHIP SCALAR xed_chip_enum_t 16 SUPPRESSED NOPRINT PUBLIC DI EI +MODE SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DI EI +SMODE SCALAR xed_bits_t 2 SUPPRESSED NOPRINT PUBLIC DI EI +MODEP5 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI +# P55C introduced MMX - FIXME: unfinished support for MODEP55C +MODEP55C SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI + +# for PAUSE vs F3 NOP +P4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO + +# for LZCNT/F3+BSR and TZCNT/F3+BSF +LZCNT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO +TZCNT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO + +MODE_FIRST_PREFIX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI +MODE_SHORT_UD0 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI + +IMM0 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI # Indicator +IMM1 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI # Indicator ENTER instruction +IMM0SIGNED SCALAR xed_bits_t 1 EXPLICIT NOPRINT PUBLIC DO EO # Decode information only + +UIMM0 SCALAR xed_uint64_t 64 SUPPRESSED NOPRINT INTERNAL DO EI +UIMM1 SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT INTERNAL DO EI # for ENTER's 2nd immediate, always 8b +IMM_WIDTH SCALAR xed_uint8_t 8 SUPPRESSED NOPRINT INTERNAL DO EI # in bits + + +# These two are decode outputs that tell us when there was an overridden segment +# selector that was not the default segment selector. + +USING_DEFAULT_SEGMENT0 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +USING_DEFAULT_SEGMENT1 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + + + +# MODRM/SIB field processing +DEFAULT_SEG SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO # ENCODER INTERNAL +SEG0 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT INTERNAL DO EI + +# BASE0 & BASE1 must be PUBLIC because the string ops conditionally update them so users need the rw code + +BASE0 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +INDEX SCALAR xed_reg_enum_t 16 EXPLICIT PRINT INTERNAL DO EI +SCALE SCALAR xed_bits_t 4 EXPLICIT PRINT INTERNAL DO EI #1/2/4/8 + +# NEED_SIB is variable used by encoder to control emitting fa sib byte. not used by decoder +NEED_SIB SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +# raw values of the SIB fields: +SIBSCALE SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO +SIBBASE SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +SIBINDEX SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +# For the string ops: +SEG1 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT INTERNAL DO EI +BASE1 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI + +# Things that tell us to look at other fields +MEM0 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI +MEM1 SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI +# MEM_WIDTH is not really a decoder-output; it is purely an encoder input. (see also ICLASS) +MEM_WIDTH SCALAR xed_uint16_t 16 SUPPRESSED NOPRINT PUBLIC DO EI # in bytes + +AGEN SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI + +# RELBR is used as a decode operand, but it is not required for encode +RELBR SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI +# for CALL_FAR & JMP_FAR. Note UIM0 is also set by these +PTR SCALAR xed_bits_t 1 EXPLICIT PRINT PUBLIC DO EI + +# NOTE: The arrays are experimental +# +#REGN ARRAY xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +# +REG0 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG1 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG2 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG3 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG4 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG5 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG6 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG7 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG8 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI +REG9 SCALAR xed_reg_enum_t 16 EXPLICIT PRINT PUBLIC DO EI + +OUTREG SCALAR xed_reg_enum_t 16 SUPPRESSED NOPRINT INTERNAL DO EI # output for lookup-functions +ENCODER_PREFERRED SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI # encoder preference when underdetermined. +ERROR SCALAR xed_error_enum_t 8 SUPPRESSED NOPRINT INTERNAL DO EO # an error occurred + +# ICLASS is not really a decoder-output; it is purely an encoder input. (see also MEM_WIDTH) +ICLASS SCALAR xed_iclass_enum_t 16 SUPPRESSED NOPRINT PUBLIC DO EI # the instruction class + +NELEM SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +ELEMENT_SIZE SCALAR xed_bits_t 9 SUPPRESSED NOPRINT INTERNAL DO EO + +#ILD-spesific operands +MAP SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +OUT_OF_BYTES SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +FIRST_F2F3 SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI +LAST_F2F3 SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI +ILD_F2 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +ILD_F3 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +MAX_BYTES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +ILD_SEG SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NSEG_PREFIXES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NREXES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NPREFIXES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +NOMINAL_OPCODE SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_NOMINAL_OPCODE SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +# HAS_MODRM: 0=no, 1=yes, 2=yes, but ignore MOD, 3=undefined +HAS_MODRM SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI +HAS_SIB SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI +POS_MODRM SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_SIB SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_DISP SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_IMM SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +POS_IMM1 SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +IMM1_BYTES SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +MODRM_BYTE SCALAR xed_bits_t 8 SUPPRESSED NOPRINT INTERNAL DO EI +ESRC SCALAR xed_bits_t 4 SUPPRESSED NOPRINT INTERNAL DO EO +VEXVALID SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +DUMMY SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd3dnow-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# @file xed-fields.txt + + +# visibilities are one of [EXPLICIT|IMPLICIT|SUPPRESSED] + +# Major properties of the fields are determined by the columns with +# the content {EI,EO} or {DI,DO,DS}. EI is encoder inputs and EO is +# for encoder outputs. DI is decoder inputs, DO is decoder +# outputs. And DS means "decoder skip" and is used for fields that +# show up in instruction pattern constraints but should be completely +# ignored by the decoder. + + +# INTERNAL means that the field is excluded from the instructions' +# operands array template. + + + +# ==== ====== ==== ========= ========== +# scalar default +# name array type bit-width visibility +# ==== ====== ==== ========= ========== +AMD3DNOW SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +MPXMODE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EI + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +CET SCALAR xed_bits_t 1 SUPPRESSED NOPRINT PUBLIC DI EO + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cldemote/cldemote-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# scalar +# name array type bit-width +# ==== ====== ==== ========= +CLDEMOTE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# ==== ==== ========= ========== ============== +# default +# name type bit-width visibility behavior +# ==== ==== ========= ========== ============== +VEXDEST3 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +VEXDEST210 SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO +VL SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EI + +VEX_PREFIX SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO # VEX.PP +VEX_C4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO # ENCONLY +BCAST SCALAR xed_bits_t 5 SUPPRESSED NOPRINT INTERNAL DO EO + +MUST_USE_EVEX SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +ZEROING SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +LLRC SCALAR xed_bits_t 2 SUPPRESSED NOPRINT INTERNAL DO EO +BCRC SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +REXRR SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO +VEXDEST4 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +MASK SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EO + +ROUNDC SCALAR xed_bits_t 3 SUPPRESSED NOPRINT INTERNAL DO EI +SAE SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EI + +# this is required for KNC's disp8 C-code override file +# (for their unaligned memop support). +NO_SCALE_DISP8 SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + +UBIT SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/wbnoinvd/wbnoinvd-fields.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# scalar +# name array type bit-width +# ==== ====== ==== ========= +WBNOINVD SCALAR xed_bits_t 1 SUPPRESSED NOPRINT INTERNAL DO EO diff --git a/CodeVirtualizer/build/obj/dgen/all-map-descriptions.txt b/CodeVirtualizer/build/obj/dgen/all-map-descriptions.txt new file mode 100644 index 0000000..52c2108 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-map-descriptions.txt @@ -0,0 +1,154 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-base-maps.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# name space esc mapopc mapno modrm disp imm opcpos 2pattern +legacy-map0 legacy N/A N/A 0 var var var 0 '' +legacy-map1 legacy 0x0F N/A 1 var var var 1 '0x0F' +legacy-map2 legacy 0x0F 0x38 2 yes no 0 2 '0x0F 0x38' +legacy-map3 legacy 0x0F 0x3A 3 yes no 1 2 '0x0F 0x3A' + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amd-3dnow-maps.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# name space esc mapopc mapno modrm disp imm opcpos pattern +amd-3dnow legacy 0x0F 0x0F AMD3DNOW yes no 1 -1 '0x0F 0x0F' + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-maps.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# name space esc mapopc mapno modrm disp imm opcpos pattern +amd-xop8 xop N/A N/A 8 yes no 1 1 'XMAP8' +amd-xop9 xop N/A N/A 9 yes no 0 1 'XMAP9' +amd-xopA xop N/A N/A 0xA yes no 4 1 'XMAPA' + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/vex-maps.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# name space esc mapopc mapno modrm disp imm opcpos pattern +vex-map1 vex N/A N/A 1 var no var 1 'V0F' +vex-map2 vex N/A N/A 2 yes no 0 1 'V0F38' +vex-map3 vex N/A N/A 3 yes no 1 1 'V0F3A' + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/evex-maps.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# name space esc mapopc mapno modrm disp imm opcpos pattern +evex-map1 evex N/A N/A 1 yes no var 1 'V0F' +evex-map2 evex N/A N/A 2 yes no 0 1 'V0F38' +evex-map3 evex N/A N/A 3 yes no 1 1 'V0F3A' + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/evex-map5-6/evex-map5-6.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# name space esc mapopc mapno modrm disp imm opcpos pattern +evex-map5 evex N/A N/A 5 yes no 0 1 'MAP5' +evex-map6 evex N/A N/A 6 yes no 0 1 'MAP6' + diff --git a/CodeVirtualizer/build/obj/dgen/all-pointer-names.txt b/CodeVirtualizer/build/obj/dgen/all-pointer-names.txt new file mode 100644 index 0000000..79dbc6d --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-pointer-names.txt @@ -0,0 +1,71 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-pointer-width.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +1 byte b +2 word w +4 dword l +8 qword q +16 xmmword x + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pointer-width.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +32 ymmword y + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-pointer-width.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +64 zmmword z + diff --git a/CodeVirtualizer/build/obj/dgen/all-registers.txt b/CodeVirtualizer/build/obj/dgen/all-registers.txt new file mode 100644 index 0000000..2df41f0 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-registers.txt @@ -0,0 +1,637 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +############################################################################ +# file: xed-regs.txt +############################################################################ + +# h is for the "h" byte regs + +#name class width max-enclosing-reg-64b/32b-mode regid [h] +INVALID INVALID 0 +ERROR INVALID 0 # used to denote errors in lookup functions + +RAX gpr 64 RAX 0 +EAX gpr 32 RAX/EAX 0 +AX gpr 16 RAX/EAX 0 +AH gpr 8 RAX/EAX 4 h +AL gpr 8 RAX/EAX 0 + +RCX gpr 64 RCX 1 +ECX gpr 32 RCX/ECX 1 +CX gpr 16 RCX/ECX 1 +CH gpr 8 RCX/ECX 5 h +CL gpr 8 RCX/ECX 1 + +RDX gpr 64 RDX 2 +EDX gpr 32 RDX/EDX 2 +DX gpr 16 RDX/EDX 2 +DH gpr 8 RDX/EDX 6 h +DL gpr 8 RDX/EDX 2 + +RBX gpr 64 RBX 3 +EBX gpr 32 RBX/EBX 3 +BX gpr 16 RBX/EBX 3 +BH gpr 8 RBX/EBX 7 h +BL gpr 8 RBX/EBX 3 + +RSP gpr 64 RSP 4 +ESP gpr 32 RSP/ESP 4 +SP gpr 16 RSP/ESP 4 +SPL gpr 8 RSP/ESP 4 + +RBP gpr 64 RBP 5 +EBP gpr 32 RBP/EBP 5 +BP gpr 16 RBP/EBP 5 +BPL gpr 8 RBP/EBP 5 + +RSI gpr 64 RSI 6 +ESI gpr 32 RSI/ESI 6 +SI gpr 16 RSI/ESI 6 +SIL gpr 8 RSI/ESI 6 + +RDI gpr 64 RDI 7 +EDI gpr 32 RDI/EDI 7 +DI gpr 16 RDI/EDI 7 +DIL gpr 8 RDI/EDI 7 + + +R8 gpr 64 R8 8 +R8D gpr 32 R8/R8D 8 +R8W gpr 16 R8/R8D 8 +R8B gpr 8 R8/R8D 8 + +R9 gpr 64 R9 9 +R9D gpr 32 R9/R9D 9 +R9W gpr 16 R9/R9D 9 +R9B gpr 8 R9/R9D 9 + +R10 gpr 64 R10 10 +R10D gpr 32 R10/R10D 10 +R10W gpr 16 R10/R10D 10 +R10B gpr 8 R10/R10D 10 + +R11 gpr 64 R11 11 +R11D gpr 32 R11/R11D 11 +R11W gpr 16 R11/R11D 11 +R11B gpr 8 R11/R11D 11 + +R12 gpr 64 R12 12 +R12D gpr 32 R12/R12D 12 +R12W gpr 16 R12/R12D 12 +R12B gpr 8 R12/R12D 12 + +R13 gpr 64 R13 13 +R13D gpr 32 R13/R13D 13 +R13W gpr 16 R13/R13D 13 +R13B gpr 8 R13/R13D 13 + +R14 gpr 64 R14 14 +R14D gpr 32 R14/R14D 14 +R14W gpr 16 R14/R14D 14 +R14B gpr 8 R14/R14D 14 + +R15 gpr 64 R15 15 +R15D gpr 32 R15/R15D 15 +R15W gpr 16 R15/R15D 15 +R15B gpr 8 R15/R15D 15 + + +RIP ip 64 RIP +EIP ip 32 RIP/EIP +IP ip 16 RIP/EIP + +FLAGS flags 16 RFLAGS/EFLAGS +EFLAGS flags 32 RFLAGS/EFLAGS +RFLAGS flags 64 RFLAGS + +# natural order for the seg regs. See SEG() nonterminal +ES sr 16 ES +CS sr 16 CS +SS sr 16 SS +DS sr 16 DS +FS sr 16 FS +GS sr 16 GS + + +MMX0 mmx 64 MMX0 0 - mm0 +MMX1 mmx 64 MMX1 1 - mm1 +MMX2 mmx 64 MMX2 2 - mm2 +MMX3 mmx 64 MMX3 3 - mm3 + +MMX4 mmx 64 MMX4 4 - mm4 +MMX5 mmx 64 MMX5 5 - mm5 +MMX6 mmx 64 MMX6 6 - mm6 +MMX7 mmx 64 MMX7 7 - mm7 + + +ST0 x87 80 ST0 0 - st(0) +ST1 x87 80 ST1 1 - st(1) +ST2 x87 80 ST2 2 - st(2) +ST3 x87 80 ST3 3 - st(3) +ST4 x87 80 ST4 4 - st(4) +ST5 x87 80 ST5 5 - st(5) +ST6 x87 80 ST6 6 - st(6) +ST7 x87 80 ST7 7 - st(7) + +CR0 cr 32/64 CR0 0 +CR1 cr 32/64 CR1 1 +CR2 cr 32/64 CR2 2 +CR3 cr 32/64 CR3 3 +CR4 cr 32/64 CR4 4 +CR5 cr 32/64 CR5 5 +CR6 cr 32/64 CR6 6 +CR7 cr 32/64 CR7 7 +CR8 cr 32/64 CR8 8 +CR9 cr 32/64 CR9 9 +CR10 cr 32/64 CR10 10 +CR11 cr 32/64 CR11 11 +CR12 cr 32/64 CR12 12 +CR13 cr 32/64 CR13 13 +CR14 cr 32/64 CR14 14 +CR15 cr 32/64 CR15 15 + +DR0 dr 32/64 DR0 0 +DR1 dr 32/64 DR1 1 +DR2 dr 32/64 DR2 2 +DR3 dr 32/64 DR3 3 +DR4 dr 32/64 DR4 4 +DR5 dr 32/64 DR5 5 +DR6 dr 32/64 DR6 6 +DR7 dr 32/64 DR7 7 + +STACKPUSH pseudo NA +STACKPOP pseudo NA +GDTR pseudo 80 +LDTR pseudo 80 +IDTR pseudo 80 +TR pseudo 80 +TSC pseudo 32 +# TSC_AUX was added in 3.10 version of AMD's manual +TSCAUX pseudo 32 +MSRS pseudo NA + +X87CONTROL pseudox87 16 +X87STATUS pseudox87 16 # includes TOP field for x87 stack +X87TAG pseudox87 16 +X87PUSH pseudox87 NA +X87POP pseudox87 NA +X87POP2 pseudox87 NA + +X87OPCODE pseudox87 11 # These 5 are not used by XED +X87LASTCS pseudox87 16 +X87LASTIP pseudox87 32/64 # 16b mode is wrong +X87LASTDS pseudox87 16 +X87LASTDP pseudox87 32/64 # 16b mode is wrong + +XCR0 xcr 64 # previously known as XFEM + +MXCSR mxcsr 32 + +# Some dummy registers for someone to play with if they ever want to +TMP0 tmp NA TMP0 0 +TMP1 tmp NA TMP1 1 +TMP2 tmp NA TMP2 2 +TMP3 tmp NA TMP3 3 +TMP4 tmp NA TMP4 4 +TMP5 tmp NA TMP5 5 +TMP6 tmp NA TMP6 6 +TMP7 tmp NA TMP7 7 +TMP8 tmp NA TMP8 8 +TMP9 tmp NA TMP9 9 +TMP10 tmp NA TMP10 10 +TMP11 tmp NA TMP11 11 +TMP12 tmp NA TMP12 12 +TMP13 tmp NA TMP13 13 +TMP14 tmp NA TMP14 14 +TMP15 tmp NA TMP15 15 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/knc-kregs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +K0 mask 16 K0 0 +K1 mask 16 K1 1 +K2 mask 16 K2 2 +K3 mask 16 K3 3 +K4 mask 16 K4 4 +K5 mask 16 K5 5 +K6 mask 16 K6 6 +K7 mask 16 K7 7 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/mpx/mpx-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +BND0 bound 128 BND0 0 +BND1 bound 128 BND1 1 +BND2 bound 128 BND2 2 +BND3 bound 128 BND3 3 +BNDCFGU bndcfg 64 BNDCFGU 0 +BNDSTATUS bndstat 64 BNDSTATUS 0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/cet/cet-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +SSP MSR 32/64 +IA32_U_CET MSR NA + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/fsgsbase/fsgsbase-regs.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +FSBASE pseudo NA +GSBASE pseudo NA + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XMM0 xmm 128 YMM0 0 +XMM1 xmm 128 YMM1 1 +XMM2 xmm 128 YMM2 2 +XMM3 xmm 128 YMM3 3 + +XMM4 xmm 128 YMM4 4 +XMM5 xmm 128 YMM5 5 +XMM6 xmm 128 YMM6 6 +XMM7 xmm 128 YMM7 7 + +XMM8 xmm 128 YMM8 8 +XMM9 xmm 128 YMM9 9 +XMM10 xmm 128 YMM10 10 +XMM11 xmm 128 YMM11 11 + +XMM12 xmm 128 YMM12 12 +XMM13 xmm 128 YMM13 13 +XMM14 xmm 128 YMM14 14 +XMM15 xmm 128 YMM15 15 + +YMM0 ymm 256 YMM0 0 +YMM1 ymm 256 YMM1 1 +YMM2 ymm 256 YMM2 2 +YMM3 ymm 256 YMM3 3 +YMM4 ymm 256 YMM4 4 +YMM5 ymm 256 YMM5 5 +YMM6 ymm 256 YMM6 6 +YMM7 ymm 256 YMM7 7 +YMM8 ymm 256 YMM8 8 +YMM9 ymm 256 YMM9 9 +YMM10 ymm 256 YMM10 10 +YMM11 ymm 256 YMM11 11 +YMM12 ymm 256 YMM12 12 +YMM13 ymm 256 YMM13 13 +YMM14 ymm 256 YMM14 14 +YMM15 ymm 256 YMM15 15 + + + + + + + +###FILE: C:\$Fanta\IntelXED\xed\datafiles\knc\lrb2-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +ZMM0 zmm 512 ZMM0 0 +ZMM1 zmm 512 ZMM1 1 +ZMM2 zmm 512 ZMM2 2 +ZMM3 zmm 512 ZMM3 3 +ZMM4 zmm 512 ZMM4 4 +ZMM5 zmm 512 ZMM5 5 +ZMM6 zmm 512 ZMM6 6 +ZMM7 zmm 512 ZMM7 7 +ZMM8 zmm 512 ZMM8 8 +ZMM9 zmm 512 ZMM9 9 +ZMM10 zmm 512 ZMM10 10 +ZMM11 zmm 512 ZMM11 11 +ZMM12 zmm 512 ZMM12 12 +ZMM13 zmm 512 ZMM13 13 +ZMM14 zmm 512 ZMM14 14 +ZMM15 zmm 512 ZMM15 15 +ZMM16 zmm 512 ZMM16 16 +ZMM17 zmm 512 ZMM17 17 +ZMM18 zmm 512 ZMM18 18 +ZMM19 zmm 512 ZMM19 19 +ZMM20 zmm 512 ZMM20 20 +ZMM21 zmm 512 ZMM21 21 +ZMM22 zmm 512 ZMM22 22 +ZMM23 zmm 512 ZMM23 23 +ZMM24 zmm 512 ZMM24 24 +ZMM25 zmm 512 ZMM25 25 +ZMM26 zmm 512 ZMM26 26 +ZMM27 zmm 512 ZMM27 27 +ZMM28 zmm 512 ZMM28 28 +ZMM29 zmm 512 ZMM29 29 +ZMM30 zmm 512 ZMM30 30 +ZMM31 zmm 512 ZMM31 31 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +XMM0 xmm 128 ZMM0 0 +XMM1 xmm 128 ZMM1 1 +XMM2 xmm 128 ZMM2 2 +XMM3 xmm 128 ZMM3 3 +XMM4 xmm 128 ZMM4 4 +XMM5 xmm 128 ZMM5 5 +XMM6 xmm 128 ZMM6 6 +XMM7 xmm 128 ZMM7 7 + +XMM8 xmm 128 ZMM8 8 +XMM9 xmm 128 ZMM9 9 +XMM10 xmm 128 ZMM10 10 +XMM11 xmm 128 ZMM11 11 +XMM12 xmm 128 ZMM12 12 +XMM13 xmm 128 ZMM13 13 +XMM14 xmm 128 ZMM14 14 +XMM15 xmm 128 ZMM15 15 + +XMM16 xmm 128 ZMM16 16 +XMM17 xmm 128 ZMM17 17 +XMM18 xmm 128 ZMM18 18 +XMM19 xmm 128 ZMM19 19 +XMM20 xmm 128 ZMM20 20 +XMM21 xmm 128 ZMM21 21 +XMM22 xmm 128 ZMM22 22 +XMM23 xmm 128 ZMM23 23 +XMM24 xmm 128 ZMM24 24 +XMM25 xmm 128 ZMM25 25 +XMM26 xmm 128 ZMM26 26 +XMM27 xmm 128 ZMM27 27 +XMM28 xmm 128 ZMM28 28 +XMM29 xmm 128 ZMM29 29 +XMM30 xmm 128 ZMM30 30 +XMM31 xmm 128 ZMM31 31 + +YMM0 ymm 256 ZMM0 0 +YMM1 ymm 256 ZMM1 1 +YMM2 ymm 256 ZMM2 2 +YMM3 ymm 256 ZMM3 3 +YMM4 ymm 256 ZMM4 4 +YMM5 ymm 256 ZMM5 5 +YMM6 ymm 256 ZMM6 6 +YMM7 ymm 256 ZMM7 7 +YMM8 ymm 256 ZMM8 8 +YMM9 ymm 256 ZMM9 9 +YMM10 ymm 256 ZMM10 10 +YMM11 ymm 256 ZMM11 11 +YMM12 ymm 256 ZMM12 12 +YMM13 ymm 256 ZMM13 13 +YMM14 ymm 256 ZMM14 14 +YMM15 ymm 256 ZMM15 15 + +YMM16 ymm 256 ZMM16 16 +YMM17 ymm 256 ZMM17 17 +YMM18 ymm 256 ZMM18 18 +YMM19 ymm 256 ZMM19 19 +YMM20 ymm 256 ZMM20 20 +YMM21 ymm 256 ZMM21 21 +YMM22 ymm 256 ZMM22 22 +YMM23 ymm 256 ZMM23 23 +YMM24 ymm 256 ZMM24 24 +YMM25 ymm 256 ZMM25 25 +YMM26 ymm 256 ZMM26 26 +YMM27 ymm 256 ZMM27 27 +YMM28 ymm 256 ZMM28 28 +YMM29 ymm 256 ZMM29 29 +YMM30 ymm 256 ZMM30 30 +YMM31 ymm 256 ZMM31 31 + + + + + + + + + + + + + + + + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-kregs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +K0 mask 64 K0 0 +K1 mask 64 K1 1 +K2 mask 64 K2 2 +K3 mask 64 K3 3 +K4 mask 64 K4 4 +K5 mask 64 K5 5 +K6 mask 64 K6 6 +K7 mask 64 K7 7 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/uintr/uintr-regs.xed.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +UIF UIF 1 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-regs.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +# 1KB = 8192 bits + +TMM0 treg 8192 TMM0 0 +TMM1 treg 8192 TMM1 1 +TMM2 treg 8192 TMM2 2 +TMM3 treg 8192 TMM3 3 +TMM4 treg 8192 TMM4 4 +TMM5 treg 8192 TMM5 5 +TMM6 treg 8192 TMM6 6 +TMM7 treg 8192 TMM7 7 + + +TILECONFIG pseudo 512 diff --git a/CodeVirtualizer/build/obj/dgen/all-state.txt b/CodeVirtualizer/build/obj/dgen/all-state.txt new file mode 100644 index 0000000..2cbb631 --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-state.txt @@ -0,0 +1,370 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +########################################################################### +## file: xed-state-bits.txt +########################################################################### + +# These are just shorthand for some conditions or captures. +# Simple macro replacement +#all_modes ALL_MODES=1 +not64 MODE!=2 +mode64 MODE=2 +mode32 MODE=1 +mode16 MODE=0 + +# effective addressing mode +eanot16 EASZ!=1 +eamode16 EASZ=1 +eamode32 EASZ=2 +eamode64 EASZ=3 + +# stack addressing mode +smode16 SMODE=0 +smode32 SMODE=1 +smode64 SMODE=2 + +eosz8 EOSZ=0 +eosz16 EOSZ=1 +not_eosz16 EOSZ!=1 +eosz32 EOSZ=2 +eosz64 EOSZ=3 +eosznot64 EOSZ!=3 + + +# for OD expansion in graph partitioning FIXME +mod0 MOD=0 +mod1 MOD=1 +mod2 MOD=2 +mod3 MOD=3 + +rex_reqd REX=1 +no_rex REX=0 +reset_rex REX=0 REXW=0 REXB=0 REXR=0 REXX=0 + +rexb_prefix REXB=1 +rexx_prefix REXX=1 +rexr_prefix REXR=1 + +# 2013-09-25 FIXME: we were inconsistent. some things use W0/W1, some +# use the more verbose form. We should converge on W0/W1. + +rexw_prefix REXW=1 +norexw_prefix REXW=0 +W1 REXW=1 +W0 REXW=0 + +norexb_prefix REXB=0 +norexx_prefix REXX=0 +norexr_prefix REXR=0 +############################################################3333 +f2_prefix REP=2 # REPNZ, REPNE +f3_prefix REP=3 # REPZ, REPE +repne REP=2 +repe REP=3 +norep REP=0 +66_prefix OSZ=1 +nof3_prefix REP!=3 +no66_prefix OSZ=0 +not_refining REP=0 +refining_f2 REP=2 +refining_f3 REP=3 +not_refining_f3 REP!=3 # for pause vs xchg +no_refining_prefix REP=0 OSZ=0 # critical:REP must be first for decoding partitioning +osz_refining_prefix REP=0 OSZ=1 +f2_refining_prefix REP=2 +f3_refining_prefix REP=3 + +no67_prefix ASZ=0 +67_prefix ASZ=1 + +lock_prefix LOCK=1 +nolock_prefix LOCK=0 + +default_ds DEFAULT_SEG=0 +default_ss DEFAULT_SEG=1 +default_es DEFAULT_SEG=2 # for string ops +no_seg_prefix SEG_OVD=0 +some_seg_prefix SEG_OVD!=0 +cs_prefix SEG_OVD=1 +ds_prefix SEG_OVD=2 +es_prefix SEG_OVD=3 +fs_prefix SEG_OVD=4 +gs_prefix SEG_OVD=5 +ss_prefix SEG_OVD=6 + +# default (or not) to 64b width in 64b mode +nrmw DF64=0 +df64 DF64=1 + +# default choice for encoder when there are multiple choices for a +# nonterminal. The ISA is not uniquely determined for encoding so we +# must express preferences for certain forms! +enc ENCODER_PREFERRED=1 + +# for the legacy prefix encoder, tell it to keep trying rules and not +# return after successfully finding one that applies +no_return NO_RETURN=1 + +# indicate an encoding or decoding error occurred +error ERROR=XED_ERROR_GENERAL_ERROR + +# dummy constraint which always satisfies +true DUMMY=0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/xop-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +XMAP8 MAP=8 +XMAP9 MAP=9 +XMAPA MAP=10 + +XOPV VEXVALID=3 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +VL128 VL=0 +VL256 VL=1 + +VV1 VEXVALID=1 +VV0 VEXVALID=0 + +VMAP0 MAP=0 +V0F MAP=1 +V0F38 MAP=2 +V0F3A MAP=3 + +VNP VEX_PREFIX=0 +V66 VEX_PREFIX=1 +VF2 VEX_PREFIX=2 +VF3 VEX_PREFIX=3 + +# No VEX-SPECIFIED-REGISTER +NOVSR VEXDEST3=0b1 VEXDEST210=0b111 + +EMX_BROADCAST_1TO4_32 BCAST=10 # 128 +EMX_BROADCAST_1TO4_64 BCAST=13 # 256 +EMX_BROADCAST_1TO8_32 BCAST=3 # 256 +EMX_BROADCAST_2TO4_64 BCAST=20 # 256 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/hswavx/hsw-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + + +EMX_BROADCAST_1TO2_64 BCAST=11 # 128 +EMX_BROADCAST_1TO8_16 BCAST=14 # 128 +EMX_BROADCAST_1TO16_16 BCAST=15 # 256 +EMX_BROADCAST_1TO16_8 BCAST=17 # 128 +EMX_BROADCAST_1TO32_8 BCAST=18 # 256 + + + + +###FILE: C:\$Fanta\IntelXED\xed\datafiles\knc\uisa-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +VL512 VL=2 +VLBAD VL=3 # unused VL setting to cause things not to decode. + +# KNC EVEX is KVV +# +KVV VEXVALID=4 + +# No VEX-SPECIFIED-REGISTER +NOEVSR VEXDEST3=0b1 VEXDEST210=0b111 VEXDEST4=0b0 + +# No VEX-SPECIFIED-REGISTER for GATHERS/SCATTERS -- index reg 5th bit is VEXTDEST4 +NO_SPARSE_EVSR VEXDEST3=0b1 VEXDEST210=0b111 + +# These conflict w/another chip ... so if you ever build a combo +# model you'll have to remove these somehow. +# +EMX_BROADCAST_1TO16_32 BCAST=1 # 512 +EMX_BROADCAST_4TO16_32 BCAST=2 # 512 +EMX_BROADCAST_1TO8_64 BCAST=5 # 512 +EMX_BROADCAST_4TO8_64 BCAST=6 # 512 + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +EVV VEXVALID=2 + +EMX_BROADCAST_1TO16_32 BCAST=1 # 512 +EMX_BROADCAST_4TO16_32 BCAST=2 # 512 +EMX_BROADCAST_1TO8_64 BCAST=5 # 512 +EMX_BROADCAST_4TO8_64 BCAST=6 # 512 +EMX_BROADCAST_2TO16_32 BCAST=7 # 512 +EMX_BROADCAST_2TO8_64 BCAST=8 # 512 +EMX_BROADCAST_8TO16_32 BCAST=9 # 512 +EMX_BROADCAST_1TO32_16 BCAST=16 # 512 +EMX_BROADCAST_1TO64_8 BCAST=19 # 512 +# these do not show up on earlier processors +EMX_BROADCAST_4TO8_32 BCAST=4 # 256 +EMX_BROADCAST_2TO4_32 BCAST=12 # 128 +EMX_BROADCAST_2TO8_32 BCAST=21 # 256 +EMX_BROADCAST_1TO2_32 BCAST=22 # 128 + +# REXRR is EVEX.RR stored inverted. EVEX.RR=0 (or REXRR=1) implies +# #UD in 64b mode and gpr encoded in modrm.reg. +EVEXRR_ONE REXRR=0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +EMX_BROADCAST_1TO2_8 BCAST=23 +EMX_BROADCAST_1TO4_8 BCAST=24 +EMX_BROADCAST_1TO8_8 BCAST=25 + +EMX_BROADCAST_1TO2_16 BCAST=26 +EMX_BROADCAST_1TO4_16 BCAST=27 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/state-bits.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +MAP5 MAP=5 +MAP6 MAP=6 + diff --git a/CodeVirtualizer/build/obj/dgen/all-widths.txt b/CodeVirtualizer/build/obj/dgen/all-widths.txt new file mode 100644 index 0000000..1e29d3d --- /dev/null +++ b/CodeVirtualizer/build/obj/dgen/all-widths.txt @@ -0,0 +1,356 @@ + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/xed-operand-width.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# @file xed-operand-width.txt + +# the default xtype can be overridden in each operand using a ":" followed by an explicit xtype +## +## the width defaults to bytes. But it can be bits if it has a "bits" suffix +## +# +# default +#oc2-code XTYPE width16 width32 width64 (if only one width is shown, it is for all widths) +# +INVALID INVALID 0 +# +# 3 strange things: +# +asz int 2 4 8 # varies with the effective address width +ssz int 2 4 8 # varies with the stack address width +pseudo struct 0 # these are for unusual registers +pseudox87 struct 0 # these are for unusual registers +# +# +# +#1 i1 1 # FIXME: this is not used... +a16 i16 4 # bound +a32 i32 8 # bound +b u8 1 +d i32 4 +# +i8 i8 1 +u8 u8 1 +i16 i16 2 +u16 u16 2 +i32 i32 4 +u32 u32 4 +i64 i64 8 +u64 u64 8 +f16 f16 2 # IVB converts +f32 f32 4 +f64 f64 8 +# +dq i32 16 +# +xub u8 16 +xuw u16 16 +xud u32 16 +xuq u64 16 +x128 u128 16 +# +xb i8 16 +xw i16 16 +xd i32 16 +xq i64 16 + +# relocated from AVX512 for use with other instructions +zb i8 512bits +zw i16 512bits +zd i32 512bits +zq i64 512bits + + +mb i8 8 +mw i16 8 +md i32 8 +mq i64 8 +# +m64int i64 8 +m64real f64 8 +mem108 struct 108 +mem14 struct 14 +mem16 struct 2 +mem16int i16 2 +mem28 struct 28 +mem32int i32 4 +mem32real f32 4 +mem80dec b80 10 +mem80real f80 10 +f80 f80 10 # for X87 registers: +mem94 struct 94 +mfpxenv struct 512 +mxsave struct 576 +mprefetch i64 64 # made up width for prefetches +p struct 4 6 6 +p2 struct 4 6 10 +pd f64 16 +ps f32 16 +pi i32 8 +q i64 8 +s struct 6 6 10 +s64 struct 10 +sd f64 8 +si i32 4 +ss f32 4 +v int 2 4 8 +y int 4 4 8 +w i16 2 +z int 2 4 4 +spw8 int 16 32 0 # varies (64b invalid) STACK POINTER WIDTH +spw int 2 4 8 # varies STACK POINTER WIDTH +spw5 int 10 20 40 # varies (IRET approx) STACK POINTER WIDTH +spw3 int 6 12 24 # varies (IRET approx) STACK POINTER WIDTH +spw2 int 4 8 16 # varies (FAR call/ret approx) STACK POINTER WIDTH +i1 int 1bits +i2 int 2bits +i3 int 3bits +i4 int 4bits +i5 int 5bits +i6 int 6bits +i7 int 7bits +i8 int 8bits +var var 0 # relies on NELEM * ELEMENT_SIZE to get the number of bits. +bnd32 u32 12 # MPX 32b BNDLDX/BNDSTX memop 3x4B +bnd64 u64 24 # MPX 32b BNDLDX/BNDSTX memop 3x8B + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/via/xed-via-operand-widths.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +#oc2-code XTYPE widths... +pmmsz16 struct 14 +pmmsz32 struct 24 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx/avx-operand-width.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# +qq i32 32 +yub u8 32 +yuw u16 32 +yud u32 32 +yuq u64 32 +y128 u128 32 + +yb i8 32 +yw i16 32 +yd i32 32 +yq i64 32 + +yps f32 32 +ypd f64 32 + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-opnd-widths.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# + +zbf16 bf16 512bits + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-operand-widths.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2019 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# +vv var 0 # relies on nelem * elem_size +zv var 0 # relies on nelem * elem_size + +wrd u16 16bits +mskw i1 64bits # FIXME: bad name + +zmskw i1 512bits + +zf32 f32 512bits +zf64 f64 512bits + +zub u8 512bits +zuw u16 512bits +zud u32 512bits +zuq u64 512bits + +# alternative names... +zi8 i8 512bits +zi16 i16 512bits +zi32 i32 512bits +zi64 i64 512bits + +zu8 u8 512bits +zu16 u16 512bits +zu32 u32 512bits +zu64 u64 512bits +zu128 u128 512bits + + + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/keylocker/widths.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL + +m384 struct 48 # bytes +m512 struct 64 # bytes + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-operand-widths.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2020 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# +#code XTYPE width16 width32 width64 (if only one width is presented, it is for all widths) +# + +ptr u8 0 +tmemrow u8 0 +tmemcol u8 0 + +# tiles are variable width based on palette so hard to really specify an overall width. +tv u8 0 + + +###FILE: C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/widths.txt + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +# + +zf16 f16 512bits +z2f16 2f16 512bits diff --git a/CodeVirtualizer/build/obj/dummy-prep b/CodeVirtualizer/build/obj/dummy-prep new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/idata.txt b/CodeVirtualizer/build/obj/idata.txt new file mode 100644 index 0000000..50ec311 --- /dev/null +++ b/CodeVirtualizer/build/obj/idata.txt @@ -0,0 +1,6883 @@ +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +#iclass extension category iform isa_set attributes +AAA BASE DECIMAL AAA I86 INVALID +AAD BASE DECIMAL AAD_IMMb I86 INVALID +AAM BASE DECIMAL AAM_IMMb I86 INVALID +AAS BASE DECIMAL AAS I86 INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR32d_GPR32d ADOX_ADCX INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR32d_MEMd ADOX_ADCX INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR64q_GPR64q ADOX_ADCX INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR64q_MEMq ADOX_ADCX INVALID +ADC BASE BINARY ADC_AL_IMMb I86 BYTEOP +ADC BASE BINARY ADC_GPR8_GPR8_10 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_GPR8_12 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_IMMb_80r2 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_IMMb_82r2 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_MEMb I86 BYTEOP +ADC BASE BINARY ADC_GPRv_GPRv_11 I86 SCALABLE +ADC BASE BINARY ADC_GPRv_GPRv_13 I86 SCALABLE +ADC BASE BINARY ADC_GPRv_IMMb I86 SCALABLE +ADC BASE BINARY ADC_GPRv_IMMz I86 SCALABLE +ADC BASE BINARY ADC_GPRv_MEMv I86 SCALABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMb_IMMb_80r2 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMb_IMMb_82r2 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADC BASE BINARY ADC_MEMb_GPR8 I86 BYTEOP:LOCKABLE +ADC BASE BINARY ADC_MEMb_IMMb_80r2 I86 BYTEOP:LOCKABLE +ADC BASE BINARY ADC_MEMb_IMMb_82r2 I86 BYTEOP:LOCKABLE +ADC BASE BINARY ADC_MEMv_GPRv I86 LOCKABLE:SCALABLE +ADC BASE BINARY ADC_MEMv_IMMb I86 LOCKABLE:SCALABLE +ADC BASE BINARY ADC_MEMv_IMMz I86 LOCKABLE:SCALABLE +ADC BASE BINARY ADC_OrAX_IMMz I86 SCALABLE +ADDPD SSE2 SSE ADDPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +ADDPD SSE2 SSE ADDPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +ADDPS SSE SSE ADDPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +ADDPS SSE SSE ADDPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +ADDSD SSE2 SSE ADDSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +ADDSD SSE2 SSE ADDSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +ADDSS SSE SSE ADDSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +ADDSS SSE SSE ADDSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +ADDSUBPD SSE3 SSE ADDSUBPD_XMMpd_MEMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +ADDSUBPD SSE3 SSE ADDSUBPD_XMMpd_XMMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +ADDSUBPS SSE3 SSE ADDSUBPS_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT:MXCSR +ADDSUBPS SSE3 SSE ADDSUBPS_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT:MXCSR +ADD BASE BINARY ADD_AL_IMMb I86 BYTEOP +ADD BASE BINARY ADD_GPR8_GPR8_00 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_GPR8_02 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_IMMb_80r0 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_IMMb_82r0 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_MEMb I86 BYTEOP +ADD BASE BINARY ADD_GPRv_GPRv_01 I86 SCALABLE +ADD BASE BINARY ADD_GPRv_GPRv_03 I86 SCALABLE +ADD BASE BINARY ADD_GPRv_IMMb I86 SCALABLE +ADD BASE BINARY ADD_GPRv_IMMz I86 SCALABLE +ADD BASE BINARY ADD_GPRv_MEMv I86 SCALABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMb_IMMb_80r0 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMb_IMMb_82r0 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADD BASE BINARY ADD_MEMb_GPR8 I86 BYTEOP:LOCKABLE +ADD BASE BINARY ADD_MEMb_IMMb_80r0 I86 BYTEOP:LOCKABLE +ADD BASE BINARY ADD_MEMb_IMMb_82r0 I86 BYTEOP:LOCKABLE +ADD BASE BINARY ADD_MEMv_GPRv I86 LOCKABLE:SCALABLE +ADD BASE BINARY ADD_MEMv_IMMb I86 LOCKABLE:SCALABLE +ADD BASE BINARY ADD_MEMv_IMMz I86 LOCKABLE:SCALABLE +ADD BASE BINARY ADD_OrAX_IMMz I86 SCALABLE +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR32d_GPR32d ADOX_ADCX INVALID +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR32d_MEMd ADOX_ADCX INVALID +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR64q_GPR64q ADOX_ADCX INVALID +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR64q_MEMq ADOX_ADCX INVALID +AESDEC128KL KEYLOCKER KEYLOCKER AESDEC128KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESDEC256KL KEYLOCKER KEYLOCKER AESDEC256KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESDECLAST AES AES AESDECLAST_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESDECLAST AES AES AESDECLAST_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESDECWIDE128KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESDECWIDE128KL_MEMu8 KEYLOCKER_WIDE INVALID +AESDECWIDE256KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESDECWIDE256KL_MEMu8 KEYLOCKER_WIDE INVALID +AESDEC AES AES AESDEC_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESDEC AES AES AESDEC_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESENC128KL KEYLOCKER KEYLOCKER AESENC128KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESENC256KL KEYLOCKER KEYLOCKER AESENC256KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESENCLAST AES AES AESENCLAST_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESENCLAST AES AES AESENCLAST_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESENCWIDE128KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESENCWIDE128KL_MEMu8 KEYLOCKER_WIDE INVALID +AESENCWIDE256KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESENCWIDE256KL_MEMu8 KEYLOCKER_WIDE INVALID +AESENC AES AES AESENC_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESENC AES AES AESENC_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESIMC AES AES AESIMC_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESIMC AES AES AESIMC_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESKEYGENASSIST AES AES AESKEYGENASSIST_XMMdq_MEMdq_IMMb AES REQUIRES_ALIGNMENT +AESKEYGENASSIST AES AES AESKEYGENASSIST_XMMdq_XMMdq_IMMb AES REQUIRES_ALIGNMENT +ANDNPD SSE2 LOGICAL_FP ANDNPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +ANDNPD SSE2 LOGICAL_FP ANDNPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +ANDNPS SSE LOGICAL_FP ANDNPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +ANDNPS SSE LOGICAL_FP ANDNPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +ANDN BMI1 BMI1 ANDN_VGPR32d_VGPR32d_MEMd BMI1 INVALID +ANDN BMI1 BMI1 ANDN_VGPR32d_VGPR32d_VGPR32d BMI1 INVALID +ANDN BMI1 BMI1 ANDN_VGPR64q_VGPR64q_MEMq BMI1 INVALID +ANDN BMI1 BMI1 ANDN_VGPR64q_VGPR64q_VGPR64q BMI1 INVALID +ANDPD SSE2 LOGICAL_FP ANDPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +ANDPD SSE2 LOGICAL_FP ANDPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +ANDPS SSE LOGICAL_FP ANDPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +ANDPS SSE LOGICAL_FP ANDPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +AND BASE LOGICAL AND_AL_IMMb I86 BYTEOP +AND BASE LOGICAL AND_GPR8_GPR8_20 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_GPR8_22 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_IMMb_80r4 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_IMMb_82r4 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_MEMb I86 BYTEOP +AND BASE LOGICAL AND_GPRv_GPRv_21 I86 SCALABLE +AND BASE LOGICAL AND_GPRv_GPRv_23 I86 SCALABLE +AND BASE LOGICAL AND_GPRv_IMMb I86 SCALABLE +AND BASE LOGICAL AND_GPRv_IMMz I86 SCALABLE +AND BASE LOGICAL AND_GPRv_MEMv I86 SCALABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMb_IMMb_80r4 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMb_IMMb_82r4 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +AND BASE LOGICAL AND_MEMb_GPR8 I86 BYTEOP:LOCKABLE +AND BASE LOGICAL AND_MEMb_IMMb_80r4 I86 BYTEOP:LOCKABLE +AND BASE LOGICAL AND_MEMb_IMMb_82r4 I86 BYTEOP:LOCKABLE +AND BASE LOGICAL AND_MEMv_GPRv I86 LOCKABLE:SCALABLE +AND BASE LOGICAL AND_MEMv_IMMb I86 LOCKABLE:SCALABLE +AND BASE LOGICAL AND_MEMv_IMMz I86 LOCKABLE:SCALABLE +AND BASE LOGICAL AND_OrAX_IMMz I86 SCALABLE +ARPL BASE SYSTEM ARPL_GPR16_GPR16 I286PROTECTED PROTECTED_MODE +ARPL BASE SYSTEM ARPL_MEMw_GPR16 I286PROTECTED PROTECTED_MODE +BEXTR BMI1 BMI1 BEXTR_VGPR32d_MEMd_VGPR32d BMI1 INVALID +BEXTR BMI1 BMI1 BEXTR_VGPR32d_VGPR32d_VGPR32d BMI1 INVALID +BEXTR BMI1 BMI1 BEXTR_VGPR64q_MEMq_VGPR64q BMI1 INVALID +BEXTR BMI1 BMI1 BEXTR_VGPR64q_VGPR64q_VGPR64q BMI1 INVALID +BEXTR_XOP TBM TBM BEXTR_XOP_VGPR32d_MEMd_IMMd TBM AMDONLY +BEXTR_XOP TBM TBM BEXTR_XOP_VGPR32d_VGPR32d_IMMd TBM AMDONLY +BEXTR_XOP TBM TBM BEXTR_XOP_VGPRyy_MEMy_IMMd TBM AMDONLY:SCALABLE +BEXTR_XOP TBM TBM BEXTR_XOP_VGPRyy_VGPRyy_IMMd TBM AMDONLY:SCALABLE +BLCFILL TBM TBM BLCFILL_VGPR32d_MEMd TBM AMDONLY +BLCFILL TBM TBM BLCFILL_VGPR32d_VGPR32d TBM AMDONLY +BLCFILL TBM TBM BLCFILL_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCFILL TBM TBM BLCFILL_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCIC TBM TBM BLCIC_VGPR32d_MEMd TBM AMDONLY +BLCIC TBM TBM BLCIC_VGPR32d_VGPR32d TBM AMDONLY +BLCIC TBM TBM BLCIC_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCIC TBM TBM BLCIC_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCI TBM TBM BLCI_VGPR32d_MEMd TBM AMDONLY +BLCI TBM TBM BLCI_VGPR32d_VGPR32d TBM AMDONLY +BLCI TBM TBM BLCI_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCI TBM TBM BLCI_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCMSK TBM TBM BLCMSK_VGPR32d_MEMd TBM AMDONLY +BLCMSK TBM TBM BLCMSK_VGPR32d_VGPR32d TBM AMDONLY +BLCMSK TBM TBM BLCMSK_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCMSK TBM TBM BLCMSK_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCS TBM TBM BLCS_VGPR32d_MEMd TBM AMDONLY +BLCS TBM TBM BLCS_VGPR32d_VGPR32d TBM AMDONLY +BLCS TBM TBM BLCS_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCS TBM TBM BLCS_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLENDPD SSE4 SSE BLENDPD_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDPD SSE4 SSE BLENDPD_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDPS SSE4 SSE BLENDPS_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDPS SSE4 SSE BLENDPS_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDVPD SSE4 SSE BLENDVPD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +BLENDVPD SSE4 SSE BLENDVPD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +BLENDVPS SSE4 SSE BLENDVPS_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +BLENDVPS SSE4 SSE BLENDVPS_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +BLSFILL TBM TBM BLSFILL_VGPR32d_MEMd TBM AMDONLY +BLSFILL TBM TBM BLSFILL_VGPR32d_VGPR32d TBM AMDONLY +BLSFILL TBM TBM BLSFILL_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLSFILL TBM TBM BLSFILL_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLSIC TBM TBM BLSIC_VGPR32d_MEMd TBM AMDONLY +BLSIC TBM TBM BLSIC_VGPR32d_VGPR32d TBM AMDONLY +BLSIC TBM TBM BLSIC_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLSIC TBM TBM BLSIC_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLSI BMI1 BMI1 BLSI_VGPR32d_MEMd BMI1 INVALID +BLSI BMI1 BMI1 BLSI_VGPR32d_VGPR32d BMI1 INVALID +BLSI BMI1 BMI1 BLSI_VGPR64q_MEMq BMI1 INVALID +BLSI BMI1 BMI1 BLSI_VGPR64q_VGPR64q BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR32d_MEMd BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR32d_VGPR32d BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR64q_MEMq BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR64q_VGPR64q BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR32d_MEMd BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR32d_VGPR32d BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR64q_MEMq BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR64q_VGPR64q BMI1 INVALID +BNDCL MPX MPX BNDCL_BND_AGEN MPX EXCEPTION_BR +BNDCL MPX MPX BNDCL_BND_GPR32 MPX EXCEPTION_BR +BNDCL MPX MPX BNDCL_BND_GPR64 MPX EXCEPTION_BR +BNDCN MPX MPX BNDCN_BND_AGEN MPX EXCEPTION_BR +BNDCN MPX MPX BNDCN_BND_GPR32 MPX EXCEPTION_BR +BNDCN MPX MPX BNDCN_BND_GPR64 MPX EXCEPTION_BR +BNDCU MPX MPX BNDCU_BND_AGEN MPX EXCEPTION_BR +BNDCU MPX MPX BNDCU_BND_GPR32 MPX EXCEPTION_BR +BNDCU MPX MPX BNDCU_BND_GPR64 MPX EXCEPTION_BR +BNDLDX MPX MPX BNDLDX_BND_MEMbnd32 MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BNDLDX MPX MPX BNDLDX_BND_MEMbnd64 MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BNDMK MPX MPX BNDMK_BND_AGEN MPX NO_RIP_REL +BNDMOV MPX MPX BNDMOV_BND_BND MPX INVALID +BNDMOV MPX MPX BNDMOV_BND_MEMdq MPX INVALID +BNDMOV MPX MPX BNDMOV_BND_MEMq MPX INVALID +BNDMOV MPX MPX BNDMOV_MEMdq_BND MPX INVALID +BNDMOV MPX MPX BNDMOV_MEMq_BND MPX INVALID +BNDSTX MPX MPX BNDSTX_MEMbnd32_BND MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BNDSTX MPX MPX BNDSTX_MEMbnd64_BND MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BOUND BASE INTERRUPT BOUND_GPRv_MEMa16 I186 EXCEPTION_BR:SCALABLE +BOUND BASE INTERRUPT BOUND_GPRv_MEMa32 I186 EXCEPTION_BR:SCALABLE +BSF BASE BITBYTE BSF_GPRv_GPRv I386 SCALABLE +BSF BASE BITBYTE BSF_GPRv_MEMv I386 SCALABLE +BSR BASE BITBYTE BSR_GPRv_GPRv I386 SCALABLE +BSR BASE BITBYTE BSR_GPRv_MEMv I386 SCALABLE +BSWAP BASE DATAXFER BSWAP_GPRv I486REAL SCALABLE +BTC BASE BITBYTE BTC_GPRv_GPRv I386 SCALABLE +BTC BASE BITBYTE BTC_GPRv_IMMb I386 SCALABLE +BTC_LOCK BASE BITBYTE BTC_LOCK_MEMv_GPRv I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTC_LOCK BASE BITBYTE BTC_LOCK_MEMv_IMMb I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTC BASE BITBYTE BTC_MEMv_GPRv I386 LOCKABLE:SCALABLE +BTC BASE BITBYTE BTC_MEMv_IMMb I386 LOCKABLE:SCALABLE +BTR BASE BITBYTE BTR_GPRv_GPRv I386 SCALABLE +BTR BASE BITBYTE BTR_GPRv_IMMb I386 SCALABLE +BTR_LOCK BASE BITBYTE BTR_LOCK_MEMv_GPRv I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTR_LOCK BASE BITBYTE BTR_LOCK_MEMv_IMMb I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTR BASE BITBYTE BTR_MEMv_GPRv I386 LOCKABLE:SCALABLE +BTR BASE BITBYTE BTR_MEMv_IMMb I386 LOCKABLE:SCALABLE +BTS BASE BITBYTE BTS_GPRv_GPRv I386 SCALABLE +BTS BASE BITBYTE BTS_GPRv_IMMb I386 SCALABLE +BTS_LOCK BASE BITBYTE BTS_LOCK_MEMv_GPRv I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTS_LOCK BASE BITBYTE BTS_LOCK_MEMv_IMMb I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTS BASE BITBYTE BTS_MEMv_GPRv I386 LOCKABLE:SCALABLE +BTS BASE BITBYTE BTS_MEMv_IMMb I386 LOCKABLE:SCALABLE +BT BASE BITBYTE BT_GPRv_GPRv I386 SCALABLE +BT BASE BITBYTE BT_GPRv_IMMb I386 SCALABLE +BT BASE BITBYTE BT_MEMv_GPRv I386 SCALABLE +BT BASE BITBYTE BT_MEMv_IMMb I386 SCALABLE +BZHI BMI2 BMI2 BZHI_VGPR32d_MEMd_VGPR32d BMI2 INVALID +BZHI BMI2 BMI2 BZHI_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +BZHI BMI2 BMI2 BZHI_VGPR64q_MEMq_VGPR64q BMI2 INVALID +BZHI BMI2 BMI2 BZHI_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +CALL_FAR BASE CALL CALL_FAR_MEMp2 I86 FAR_XFER:NOTSX:INDIRECT_BRANCH:FIXED_BASE1:STACKPUSH1:SCALABLE +CALL_FAR BASE CALL CALL_FAR_PTRp_IMMw I86 FAR_XFER:NOTSX:FIXED_BASE0:STACKPUSH0:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_GPRv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:FIXED_BASE0:STACKPUSH0:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_MEMv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:FIXED_BASE1:STACKPUSH1:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_RELBRd I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPUSH0:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_RELBRz I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPUSH0:SCALABLE +CBW BASE CONVERT CBW I86 INVALID +CDQ BASE CONVERT CDQ I386 INVALID +CDQE LONGMODE CONVERT CDQE LONGMODE INVALID +CLAC SMAP SMAP CLAC SMAP INVALID +CLC BASE FLAGOP CLC I86 INVALID +CLD BASE FLAGOP CLD I86 NOTSX_COND +CLDEMOTE CLDEMOTE CLDEMOTE CLDEMOTE_MEMu8 CLDEMOTE INVALID +CLFLUSHOPT CLFLUSHOPT CLFLUSHOPT CLFLUSHOPT_MEMmprefetch CLFLUSHOPT PREFETCH +CLFLUSH CLFSH MISC CLFLUSH_MEMmprefetch CLFSH NOTSX +CLGI SVM SYSTEM CLGI SVM PROTECTED_MODE:AMDONLY +CLI BASE FLAGOP CLI I86 NOTSX +CLRSSBSY CET CET CLRSSBSY_MEMu64 CET INVALID +CLTS BASE SYSTEM CLTS I286REAL RING0:NOTSX +CLUI UINTR UINTR CLUI UINTR INVALID +CLWB CLWB CLWB CLWB_MEMmprefetch CLWB PREFETCH +CLZERO CLZERO CLZERO CLZERO CLZERO AMDONLY +CMC BASE FLAGOP CMC I86 INVALID +CMOVBE BASE CMOV CMOVBE_GPRv_GPRv CMOV SCALABLE +CMOVBE BASE CMOV CMOVBE_GPRv_MEMv CMOV SCALABLE +CMOVB BASE CMOV CMOVB_GPRv_GPRv CMOV SCALABLE +CMOVB BASE CMOV CMOVB_GPRv_MEMv CMOV SCALABLE +CMOVLE BASE CMOV CMOVLE_GPRv_GPRv CMOV SCALABLE +CMOVLE BASE CMOV CMOVLE_GPRv_MEMv CMOV SCALABLE +CMOVL BASE CMOV CMOVL_GPRv_GPRv CMOV SCALABLE +CMOVL BASE CMOV CMOVL_GPRv_MEMv CMOV SCALABLE +CMOVNBE BASE CMOV CMOVNBE_GPRv_GPRv CMOV SCALABLE +CMOVNBE BASE CMOV CMOVNBE_GPRv_MEMv CMOV SCALABLE +CMOVNB BASE CMOV CMOVNB_GPRv_GPRv CMOV SCALABLE +CMOVNB BASE CMOV CMOVNB_GPRv_MEMv CMOV SCALABLE +CMOVNLE BASE CMOV CMOVNLE_GPRv_GPRv CMOV SCALABLE +CMOVNLE BASE CMOV CMOVNLE_GPRv_MEMv CMOV SCALABLE +CMOVNL BASE CMOV CMOVNL_GPRv_GPRv CMOV SCALABLE +CMOVNL BASE CMOV CMOVNL_GPRv_MEMv CMOV SCALABLE +CMOVNO BASE CMOV CMOVNO_GPRv_GPRv CMOV SCALABLE +CMOVNO BASE CMOV CMOVNO_GPRv_MEMv CMOV SCALABLE +CMOVNP BASE CMOV CMOVNP_GPRv_GPRv CMOV SCALABLE +CMOVNP BASE CMOV CMOVNP_GPRv_MEMv CMOV SCALABLE +CMOVNS BASE CMOV CMOVNS_GPRv_GPRv CMOV SCALABLE +CMOVNS BASE CMOV CMOVNS_GPRv_MEMv CMOV SCALABLE +CMOVNZ BASE CMOV CMOVNZ_GPRv_GPRv CMOV SCALABLE +CMOVNZ BASE CMOV CMOVNZ_GPRv_MEMv CMOV SCALABLE +CMOVO BASE CMOV CMOVO_GPRv_GPRv CMOV SCALABLE +CMOVO BASE CMOV CMOVO_GPRv_MEMv CMOV SCALABLE +CMOVP BASE CMOV CMOVP_GPRv_GPRv CMOV SCALABLE +CMOVP BASE CMOV CMOVP_GPRv_MEMv CMOV SCALABLE +CMOVS BASE CMOV CMOVS_GPRv_GPRv CMOV SCALABLE +CMOVS BASE CMOV CMOVS_GPRv_MEMv CMOV SCALABLE +CMOVZ BASE CMOV CMOVZ_GPRv_GPRv CMOV SCALABLE +CMOVZ BASE CMOV CMOVZ_GPRv_MEMv CMOV SCALABLE +CMPPD SSE2 SSE CMPPD_XMMpd_MEMpd_IMMb SSE2 REQUIRES_ALIGNMENT:MXCSR +CMPPD SSE2 SSE CMPPD_XMMpd_XMMpd_IMMb SSE2 REQUIRES_ALIGNMENT:MXCSR +CMPPS SSE SSE CMPPS_XMMps_MEMps_IMMb SSE REQUIRES_ALIGNMENT:MXCSR +CMPPS SSE SSE CMPPS_XMMps_XMMps_IMMb SSE REQUIRES_ALIGNMENT:MXCSR +CMPSB BASE STRINGOP CMPSB I86 FIXED_BASE0:FIXED_BASE1:BYTEOP +CMPSD BASE STRINGOP CMPSD I386 FIXED_BASE0:FIXED_BASE1 +CMPSD_XMM SSE2 SSE CMPSD_XMM_XMMsd_MEMsd_IMMb SSE2 SIMD_SCALAR:MXCSR +CMPSD_XMM SSE2 SSE CMPSD_XMM_XMMsd_XMMsd_IMMb SSE2 SIMD_SCALAR:MXCSR +CMPSQ LONGMODE STRINGOP CMPSQ LONGMODE FIXED_BASE0:FIXED_BASE1 +CMPSS SSE SSE CMPSS_XMMss_MEMss_IMMb SSE SIMD_SCALAR:MXCSR +CMPSS SSE SSE CMPSS_XMMss_XMMss_IMMb SSE SIMD_SCALAR:MXCSR +CMPSW BASE STRINGOP CMPSW I86 FIXED_BASE0:FIXED_BASE1 +CMPXCHG16B_LOCK LONGMODE SEMAPHORE CMPXCHG16B_LOCK_MEMdq CMPXCHG16B REQUIRES_ALIGNMENT:LOCKED +CMPXCHG16B LONGMODE SEMAPHORE CMPXCHG16B_MEMdq CMPXCHG16B REQUIRES_ALIGNMENT:LOCKABLE +CMPXCHG8B_LOCK BASE SEMAPHORE CMPXCHG8B_LOCK_MEMq PENTIUMREAL LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +CMPXCHG8B BASE SEMAPHORE CMPXCHG8B_MEMq PENTIUMREAL LOCKABLE +CMPXCHG BASE SEMAPHORE CMPXCHG_GPR8_GPR8 I486REAL BYTEOP +CMPXCHG BASE SEMAPHORE CMPXCHG_GPRv_GPRv I486REAL SCALABLE +CMPXCHG_LOCK BASE SEMAPHORE CMPXCHG_LOCK_MEMb_GPR8 I486REAL BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +CMPXCHG_LOCK BASE SEMAPHORE CMPXCHG_LOCK_MEMv_GPRv I486REAL LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +CMPXCHG BASE SEMAPHORE CMPXCHG_MEMb_GPR8 I486REAL BYTEOP:LOCKABLE +CMPXCHG BASE SEMAPHORE CMPXCHG_MEMv_GPRv I486REAL LOCKABLE:SCALABLE +CMP BASE BINARY CMP_AL_IMMb I86 BYTEOP +CMP BASE BINARY CMP_GPR8_GPR8_38 I86 BYTEOP +CMP BASE BINARY CMP_GPR8_GPR8_3A I86 BYTEOP +CMP BASE BINARY CMP_GPR8_IMMb_80r7 I86 BYTEOP +CMP BASE BINARY CMP_GPR8_IMMb_82r7 I86 BYTEOP +CMP BASE BINARY CMP_GPR8_MEMb I86 BYTEOP +CMP BASE BINARY CMP_GPRv_GPRv_39 I86 SCALABLE +CMP BASE BINARY CMP_GPRv_GPRv_3B I86 SCALABLE +CMP BASE BINARY CMP_GPRv_IMMb I86 SCALABLE +CMP BASE BINARY CMP_GPRv_IMMz I86 SCALABLE +CMP BASE BINARY CMP_GPRv_MEMv I86 SCALABLE +CMP BASE BINARY CMP_MEMb_GPR8 I86 BYTEOP +CMP BASE BINARY CMP_MEMb_IMMb_80r7 I86 BYTEOP +CMP BASE BINARY CMP_MEMb_IMMb_82r7 I86 BYTEOP +CMP BASE BINARY CMP_MEMv_GPRv I86 SCALABLE +CMP BASE BINARY CMP_MEMv_IMMb I86 SCALABLE +CMP BASE BINARY CMP_MEMv_IMMz I86 SCALABLE +CMP BASE BINARY CMP_OrAX_IMMz I86 SCALABLE +COMISD SSE2 SSE COMISD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +COMISD SSE2 SSE COMISD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +COMISS SSE SSE COMISS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +COMISS SSE SSE COMISS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +CPUID BASE MISC CPUID I486REAL NOTSX +CQO LONGMODE CONVERT CQO LONGMODE INVALID +CRC32 SSE4 SSE CRC32_GPRyy_GPR8b SSE42 IGNORES_OSFXSR:SCALABLE +CRC32 SSE4 SSE CRC32_GPRyy_GPRv SSE42 IGNORES_OSFXSR:SCALABLE +CRC32 SSE4 SSE CRC32_GPRyy_MEMb SSE42 IGNORES_OSFXSR:SCALABLE +CRC32 SSE4 SSE CRC32_GPRyy_MEMv SSE42 IGNORES_OSFXSR:SCALABLE +CVTDQ2PD SSE2 CONVERT CVTDQ2PD_XMMpd_MEMq SSE2 INVALID +CVTDQ2PD SSE2 CONVERT CVTDQ2PD_XMMpd_XMMq SSE2 INVALID +CVTDQ2PS SSE2 CONVERT CVTDQ2PS_XMMps_MEMdq SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTDQ2PS SSE2 CONVERT CVTDQ2PS_XMMps_XMMdq SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2DQ SSE2 CONVERT CVTPD2DQ_XMMdq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2DQ SSE2 CONVERT CVTPD2DQ_XMMdq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2PI SSE2 CONVERT CVTPD2PI_MMXq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTPD2PI SSE2 CONVERT CVTPD2PI_MMXq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTPD2PS SSE2 CONVERT CVTPD2PS_XMMps_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2PS SSE2 CONVERT CVTPD2PS_XMMps_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPI2PD SSE2 CONVERT CVTPI2PD_XMMpd_MEMq SSE2 MXCSR:MMX_EXCEPT:NOTSX +CVTPI2PD SSE2 CONVERT CVTPI2PD_XMMpd_MMXq SSE2 MXCSR:MMX_EXCEPT:NOTSX +CVTPI2PS SSE CONVERT CVTPI2PS_XMMq_MEMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTPI2PS SSE CONVERT CVTPI2PS_XMMq_MMXq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTPS2DQ SSE2 CONVERT CVTPS2DQ_XMMdq_MEMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPS2DQ SSE2 CONVERT CVTPS2DQ_XMMdq_XMMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPS2PD SSE2 CONVERT CVTPS2PD_XMMpd_MEMq SSE2 MXCSR +CVTPS2PD SSE2 CONVERT CVTPS2PD_XMMpd_XMMq SSE2 MXCSR +CVTPS2PI SSE CONVERT CVTPS2PI_MMXq_MEMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTPS2PI SSE CONVERT CVTPS2PI_MMXq_XMMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR32d_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR32d_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR64q_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR64q_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SS SSE2 CONVERT CVTSD2SS_XMMss_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SS SSE2 CONVERT CVTSD2SS_XMMss_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_GPR32d SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_GPR64q SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_MEMd SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_MEMq SSE2 SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_GPR32d SSE SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_GPR64q SSE SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_MEMd SSE SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_MEMq SSE SIMD_SCALAR:MXCSR +CVTSS2SD SSE2 CONVERT CVTSS2SD_XMMsd_MEMss SSE2 SIMD_SCALAR:MXCSR +CVTSS2SD SSE2 CONVERT CVTSS2SD_XMMsd_XMMss SSE2 SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR32d_MEMss SSE SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR32d_XMMss SSE SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR64q_MEMss SSE SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR64q_XMMss SSE SIMD_SCALAR:MXCSR +CVTTPD2DQ SSE2 CONVERT CVTTPD2DQ_XMMdq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPD2DQ SSE2 CONVERT CVTTPD2DQ_XMMdq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPD2PI SSE2 CONVERT CVTTPD2PI_MMXq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTTPD2PI SSE2 CONVERT CVTTPD2PI_MMXq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTTPS2DQ SSE2 CONVERT CVTTPS2DQ_XMMdq_MEMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPS2DQ SSE2 CONVERT CVTTPS2DQ_XMMdq_XMMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPS2PI SSE CONVERT CVTTPS2PI_MMXq_MEMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTTPS2PI SSE CONVERT CVTTPS2PI_MMXq_XMMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR32d_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR32d_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR64q_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR64q_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR32d_MEMss SSE SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR32d_XMMss SSE SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR64q_MEMss SSE SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR64q_XMMss SSE SIMD_SCALAR:MXCSR +CWD BASE CONVERT CWD I86 INVALID +CWDE BASE CONVERT CWDE I386 INVALID +DAA BASE DECIMAL DAA I86 INVALID +DAS BASE DECIMAL DAS I86 INVALID +DEC BASE BINARY DEC_GPR8 I86 BYTEOP +DEC BASE BINARY DEC_GPRv_48 I86 SCALABLE +DEC BASE BINARY DEC_GPRv_FFr1 I86 SCALABLE +DEC_LOCK BASE BINARY DEC_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +DEC_LOCK BASE BINARY DEC_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +DEC BASE BINARY DEC_MEMb I86 BYTEOP:LOCKABLE +DEC BASE BINARY DEC_MEMv I86 LOCKABLE:SCALABLE +DIVPD SSE2 SSE DIVPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +DIVPD SSE2 SSE DIVPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +DIVPS SSE SSE DIVPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +DIVPS SSE SSE DIVPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +DIVSD SSE2 SSE DIVSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +DIVSD SSE2 SSE DIVSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +DIVSS SSE SSE DIVSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +DIVSS SSE SSE DIVSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +DIV BASE BINARY DIV_GPR8 I86 BYTEOP +DIV BASE BINARY DIV_GPRv I86 SCALABLE +DIV BASE BINARY DIV_MEMb I86 BYTEOP +DIV BASE BINARY DIV_MEMv I86 SCALABLE +DPPD SSE4 SSE DPPD_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +DPPD SSE4 SSE DPPD_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +DPPS SSE4 SSE DPPS_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +DPPS SSE4 SSE DPPS_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +EMMS MMX MMX EMMS PENTIUMMMX X87_MMX_STATE_W:NOTSX +ENCLS SGX SGX ENCLS SGX INVALID +ENCLU SGX SGX ENCLU SGX INVALID +ENCLV SGX_ENCLV SGX ENCLV SGX_ENCLV INVALID +ENCODEKEY128 KEYLOCKER KEYLOCKER ENCODEKEY128_GPR32u8_GPR32u8 KEYLOCKER INVALID +ENCODEKEY256 KEYLOCKER KEYLOCKER ENCODEKEY256_GPR32u8_GPR32u8 KEYLOCKER INVALID +ENDBR32 CET CET ENDBR32 CET INVALID +ENDBR64 CET CET ENDBR64 CET INVALID +ENQCMDS ENQCMD ENQCMD ENQCMDS_GPRa_MEMu32 ENQCMD INVALID +ENQCMD ENQCMD ENQCMD ENQCMD_GPRa_MEMu32 ENQCMD INVALID +ENTER BASE MISC ENTER_IMMw_IMMb I186 ATT_OPERAND_ORDER_EXCEPTION:FIXED_BASE0:STACKPUSH0:SCALABLE +EXTRACTPS SSE4 SSE EXTRACTPS_GPR32d_XMMdq_IMMb SSE4 INVALID +EXTRACTPS SSE4 SSE EXTRACTPS_MEMd_XMMps_IMMb SSE4 INVALID +EXTRQ SSE4a BITBYTE EXTRQ_XMMq_IMMb_IMMb SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +EXTRQ SSE4a BITBYTE EXTRQ_XMMq_XMMdq SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +F2XM1 X87 X87_ALU F2XM1 X87 NOTSX +FABS X87 X87_ALU FABS X87 NOTSX +FADDP X87 X87_ALU FADDP_X87_ST0 X87 NOTSX +FADD X87 X87_ALU FADD_ST0_MEMm64real X87 NOTSX +FADD X87 X87_ALU FADD_ST0_MEMmem32real X87 NOTSX +FADD X87 X87_ALU FADD_ST0_X87 X87 NOTSX +FADD X87 X87_ALU FADD_X87_ST0 X87 NOTSX +FBLD X87 X87_ALU FBLD_ST0_MEMmem80dec X87 NOTSX +FBSTP X87 X87_ALU FBSTP_MEMmem80dec_ST0 X87 NOTSX +FCHS X87 X87_ALU FCHS X87 NOTSX +FCMOVBE X87 FCMOV FCMOVBE_ST0_X87 FCMOV NOTSX +FCMOVB X87 FCMOV FCMOVB_ST0_X87 FCMOV NOTSX +FCMOVE X87 FCMOV FCMOVE_ST0_X87 FCMOV NOTSX +FCMOVNBE X87 FCMOV FCMOVNBE_ST0_X87 FCMOV NOTSX +FCMOVNB X87 FCMOV FCMOVNB_ST0_X87 FCMOV NOTSX +FCMOVNE X87 FCMOV FCMOVNE_ST0_X87 FCMOV NOTSX +FCMOVNU X87 FCMOV FCMOVNU_ST0_X87 FCMOV NOTSX +FCMOVU X87 FCMOV FCMOVU_ST0_X87 FCMOV NOTSX +FCOMIP X87 X87_ALU FCOMIP_ST0_X87 PPRO NOTSX +FCOMI X87 X87_ALU FCOMI_ST0_X87 PPRO NOTSX +FCOMPP X87 X87_ALU FCOMPP X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_MEMm64real X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_MEMmem32real X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_X87 X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_X87_DCD1 X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_X87_DED0 X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_MEMm64real X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_MEMmem32real X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_X87 X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_X87_DCD0 X87 NOTSX +FCOS X87 X87_ALU FCOS X87 NOTSX +FDECSTP X87 X87_ALU FDECSTP X87 X87_CONTROL:NOTSX +FDISI8087_NOP X87 X87_ALU FDISI8087_NOP X87 NOP:NOTSX +FDIVP X87 X87_ALU FDIVP_X87_ST0 X87 NOTSX +FDIVRP X87 X87_ALU FDIVRP_X87_ST0 X87 NOTSX +FDIVR X87 X87_ALU FDIVR_ST0_MEMm64real X87 NOTSX +FDIVR X87 X87_ALU FDIVR_ST0_MEMmem32real X87 NOTSX +FDIVR X87 X87_ALU FDIVR_ST0_X87 X87 NOTSX +FDIVR X87 X87_ALU FDIVR_X87_ST0 X87 NOTSX +FDIV X87 X87_ALU FDIV_ST0_MEMm64real X87 NOTSX +FDIV X87 X87_ALU FDIV_ST0_MEMmem32real X87 NOTSX +FDIV X87 X87_ALU FDIV_ST0_X87 X87 NOTSX +FDIV X87 X87_ALU FDIV_X87_ST0 X87 NOTSX +FEMMS 3DNOW MMX FEMMS 3DNOW X87_MMX_STATE_W:AMDONLY +FENI8087_NOP X87 X87_ALU FENI8087_NOP X87 NOP:NOTSX +FFREEP X87 X87_ALU FFREEP_X87 X87 X87_CONTROL:NOTSX +FFREE X87 X87_ALU FFREE_X87 X87 X87_CONTROL:NOTSX +FIADD X87 X87_ALU FIADD_ST0_MEMmem16int X87 NOTSX +FIADD X87 X87_ALU FIADD_ST0_MEMmem32int X87 NOTSX +FICOMP X87 X87_ALU FICOMP_ST0_MEMmem16int X87 NOTSX +FICOMP X87 X87_ALU FICOMP_ST0_MEMmem32int X87 NOTSX +FICOM X87 X87_ALU FICOM_ST0_MEMmem16int X87 NOTSX +FICOM X87 X87_ALU FICOM_ST0_MEMmem32int X87 NOTSX +FIDIVR X87 X87_ALU FIDIVR_ST0_MEMmem16int X87 NOTSX +FIDIVR X87 X87_ALU FIDIVR_ST0_MEMmem32int X87 NOTSX +FIDIV X87 X87_ALU FIDIV_ST0_MEMmem16int X87 NOTSX +FIDIV X87 X87_ALU FIDIV_ST0_MEMmem32int X87 NOTSX +FILD X87 X87_ALU FILD_ST0_MEMm64int X87 NOTSX +FILD X87 X87_ALU FILD_ST0_MEMmem16int X87 NOTSX +FILD X87 X87_ALU FILD_ST0_MEMmem32int X87 NOTSX +FIMUL X87 X87_ALU FIMUL_ST0_MEMmem16int X87 NOTSX +FIMUL X87 X87_ALU FIMUL_ST0_MEMmem32int X87 NOTSX +FINCSTP X87 X87_ALU FINCSTP X87 X87_CONTROL:NOTSX +FISTP X87 X87_ALU FISTP_MEMm64int_ST0 X87 NOTSX +FISTP X87 X87_ALU FISTP_MEMmem16int_ST0 X87 NOTSX +FISTP X87 X87_ALU FISTP_MEMmem32int_ST0 X87 NOTSX +FISTTP SSE3 X87_ALU FISTTP_MEMm64int_ST0 SSE3X87 NOTSX +FISTTP SSE3 X87_ALU FISTTP_MEMmem16int_ST0 SSE3X87 NOTSX +FISTTP SSE3 X87_ALU FISTTP_MEMmem32int_ST0 SSE3 NOTSX +FIST X87 X87_ALU FIST_MEMmem16int_ST0 X87 NOTSX +FIST X87 X87_ALU FIST_MEMmem32int_ST0 X87 NOTSX +FISUBR X87 X87_ALU FISUBR_ST0_MEMmem16int X87 NOTSX +FISUBR X87 X87_ALU FISUBR_ST0_MEMmem32int X87 NOTSX +FISUB X87 X87_ALU FISUB_ST0_MEMmem16int X87 NOTSX +FISUB X87 X87_ALU FISUB_ST0_MEMmem32int X87 NOTSX +FLD1 X87 X87_ALU FLD1 X87 NOTSX +FLDCW X87 X87_ALU FLDCW_MEMmem16 X87 X87_CONTROL:NOTSX +FLDENV X87 X87_ALU FLDENV_MEMmem14 X87 X87_CONTROL:NOTSX +FLDENV X87 X87_ALU FLDENV_MEMmem28 X87 X87_CONTROL:NOTSX +FLDL2E X87 X87_ALU FLDL2E X87 NOTSX +FLDL2T X87 X87_ALU FLDL2T X87 NOTSX +FLDLG2 X87 X87_ALU FLDLG2 X87 NOTSX +FLDLN2 X87 X87_ALU FLDLN2 X87 NOTSX +FLDPI X87 X87_ALU FLDPI X87 NOTSX +FLDZ X87 X87_ALU FLDZ X87 NOTSX +FLD X87 X87_ALU FLD_ST0_MEMm64real X87 NOTSX +FLD X87 X87_ALU FLD_ST0_MEMmem32real X87 NOTSX +FLD X87 X87_ALU FLD_ST0_MEMmem80real X87 NOTSX +FLD X87 X87_ALU FLD_ST0_X87 X87 NOTSX +FMULP X87 X87_ALU FMULP_X87_ST0 X87 NOTSX +FMUL X87 X87_ALU FMUL_ST0_MEMm64real X87 NOTSX +FMUL X87 X87_ALU FMUL_ST0_MEMmem32real X87 NOTSX +FMUL X87 X87_ALU FMUL_ST0_X87 X87 NOTSX +FMUL X87 X87_ALU FMUL_X87_ST0 X87 NOTSX +FNCLEX X87 X87_ALU FNCLEX X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNINIT X87 X87_ALU FNINIT X87 X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FNOP X87 X87_ALU FNOP X87 NOP:X87_CONTROL:NOTSX +FNSAVE X87 X87_ALU FNSAVE_MEMmem108 X87 X87_MMX_STATE_R:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FNSAVE X87 X87_ALU FNSAVE_MEMmem94 X87 X87_MMX_STATE_R:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FNSTCW X87 X87_ALU FNSTCW_MEMmem16 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTENV X87 X87_ALU FNSTENV_MEMmem14 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTENV X87 X87_ALU FNSTENV_MEMmem28 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTSW X87 X87_ALU FNSTSW_AX X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTSW X87 X87_ALU FNSTSW_MEMmem16 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FPATAN X87 X87_ALU FPATAN X87 NOTSX +FPREM X87 X87_ALU FPREM X87 NOTSX +FPREM1 X87 X87_ALU FPREM1 X87 NOTSX +FPTAN X87 X87_ALU FPTAN X87 NOTSX +FRNDINT X87 X87_ALU FRNDINT X87 NOTSX +FRSTOR X87 X87_ALU FRSTOR_MEMmem108 X87 X87_MMX_STATE_W:X87_CONTROL:NOTSX +FRSTOR X87 X87_ALU FRSTOR_MEMmem94 X87 X87_MMX_STATE_W:X87_CONTROL:NOTSX +FSCALE X87 X87_ALU FSCALE X87 NOTSX +FSETPM287_NOP X87 X87_ALU FSETPM287_NOP X87 NOP:NOTSX +FSIN X87 X87_ALU FSIN X87 NOTSX +FSINCOS X87 X87_ALU FSINCOS X87 NOTSX +FSQRT X87 X87_ALU FSQRT X87 NOTSX +FSTPNCE X87 X87_ALU FSTPNCE_X87_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_MEMm64real_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_MEMmem32real_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_MEMmem80real_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_X87_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_X87_ST0_DFD0 X87 NOTSX +FSTP X87 X87_ALU FSTP_X87_ST0_DFD1 X87 NOTSX +FST X87 X87_ALU FST_MEMm64real_ST0 X87 NOTSX +FST X87 X87_ALU FST_MEMmem32real_ST0 X87 NOTSX +FST X87 X87_ALU FST_X87_ST0 X87 NOTSX +FSUBP X87 X87_ALU FSUBP_X87_ST0 X87 NOTSX +FSUBRP X87 X87_ALU FSUBRP_X87_ST0 X87 NOTSX +FSUBR X87 X87_ALU FSUBR_ST0_MEMm64real X87 NOTSX +FSUBR X87 X87_ALU FSUBR_ST0_MEMmem32real X87 NOTSX +FSUBR X87 X87_ALU FSUBR_ST0_X87 X87 NOTSX +FSUBR X87 X87_ALU FSUBR_X87_ST0 X87 NOTSX +FSUB X87 X87_ALU FSUB_ST0_MEMm64real X87 NOTSX +FSUB X87 X87_ALU FSUB_ST0_MEMmem32real X87 NOTSX +FSUB X87 X87_ALU FSUB_ST0_X87 X87 NOTSX +FSUB X87 X87_ALU FSUB_X87_ST0 X87 NOTSX +FTST X87 X87_ALU FTST X87 NOTSX +FUCOMIP X87 X87_ALU FUCOMIP_ST0_X87 PPRO NOTSX +FUCOMI X87 X87_ALU FUCOMI_ST0_X87 PPRO NOTSX +FUCOMPP X87 X87_ALU FUCOMPP X87 NOTSX +FUCOMP X87 X87_ALU FUCOMP_ST0_X87 X87 NOTSX +FUCOM X87 X87_ALU FUCOM_ST0_X87 X87 NOTSX +FWAIT X87 X87_ALU FWAIT X87 X87_CONTROL:NOTSX +FXAM X87 X87_ALU FXAM X87 NOTSX +FXCH X87 X87_ALU FXCH_ST0_X87 X87 NOTSX +FXCH X87 X87_ALU FXCH_ST0_X87_DDC1 X87 NOTSX +FXCH X87 X87_ALU FXCH_ST0_X87_DFC1 X87 NOTSX +FXRSTOR64 SSE SSE FXRSTOR64_MEMmfpxenv FXSAVE64 XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FXRSTOR SSE SSE FXRSTOR_MEMmfpxenv FXSAVE XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FXSAVE64 SSE SSE FXSAVE64_MEMmfpxenv FXSAVE64 XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:X87_NOWAIT:X87_CONTROL:NOTSX +FXSAVE SSE SSE FXSAVE_MEMmfpxenv FXSAVE XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:X87_NOWAIT:X87_CONTROL:NOTSX +FXTRACT X87 X87_ALU FXTRACT X87 NOTSX +FYL2X X87 X87_ALU FYL2X X87 NOTSX +FYL2XP1 X87 X87_ALU FYL2XP1 X87 NOTSX +GETSEC SMX SYSTEM GETSEC SMX PROTECTED_MODE:NOTSX +GF2P8AFFINEINVQB GFNI GFNI GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 GFNI REQUIRES_ALIGNMENT +GF2P8AFFINEINVQB GFNI GFNI GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 GFNI INVALID +GF2P8AFFINEQB GFNI GFNI GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 GFNI REQUIRES_ALIGNMENT +GF2P8AFFINEQB GFNI GFNI GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 GFNI INVALID +GF2P8MULB GFNI GFNI GF2P8MULB_XMMu8_MEMu8 GFNI REQUIRES_ALIGNMENT +GF2P8MULB GFNI GFNI GF2P8MULB_XMMu8_XMMu8 GFNI INVALID +HADDPD SSE3 SSE HADDPD_XMMpd_MEMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HADDPD SSE3 SSE HADDPD_XMMpd_XMMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HADDPS SSE3 SSE HADDPS_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT:MXCSR +HADDPS SSE3 SSE HADDPS_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT:MXCSR +HLT BASE SYSTEM HLT I86 RING0:NOTSX +HRESET HRESET HRESET HRESET_IMM8 HRESET INVALID +HSUBPD SSE3 SSE HSUBPD_XMMpd_MEMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HSUBPD SSE3 SSE HSUBPD_XMMpd_XMMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HSUBPS SSE3 SSE HSUBPS_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT:MXCSR +HSUBPS SSE3 SSE HSUBPS_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT:MXCSR +IDIV BASE BINARY IDIV_GPR8 I86 BYTEOP +IDIV BASE BINARY IDIV_GPRv I86 SCALABLE +IDIV BASE BINARY IDIV_MEMb I86 BYTEOP +IDIV BASE BINARY IDIV_MEMv I86 SCALABLE +IMUL BASE BINARY IMUL_GPR8 I86 BYTEOP +IMUL BASE BINARY IMUL_GPRv I86 SCALABLE +IMUL BASE BINARY IMUL_GPRv_GPRv I86 SCALABLE +IMUL BASE BINARY IMUL_GPRv_GPRv_IMMb I186 SCALABLE +IMUL BASE BINARY IMUL_GPRv_GPRv_IMMz I186 SCALABLE +IMUL BASE BINARY IMUL_GPRv_MEMv I86 SCALABLE +IMUL BASE BINARY IMUL_GPRv_MEMv_IMMb I186 SCALABLE +IMUL BASE BINARY IMUL_GPRv_MEMv_IMMz I186 SCALABLE +IMUL BASE BINARY IMUL_MEMb I86 BYTEOP +IMUL BASE BINARY IMUL_MEMv I86 SCALABLE +INCSSPD CET CET INCSSPD_GPR32u8 CET INVALID +INCSSPQ CET CET INCSSPQ_GPR64u8 CET INVALID +INC BASE BINARY INC_GPR8 I86 BYTEOP +INC BASE BINARY INC_GPRv_40 I86 SCALABLE +INC BASE BINARY INC_GPRv_FFr0 I86 SCALABLE +INC_LOCK BASE BINARY INC_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +INC_LOCK BASE BINARY INC_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +INC BASE BINARY INC_MEMb I86 BYTEOP:LOCKABLE +INC BASE BINARY INC_MEMv I86 LOCKABLE:SCALABLE +INSB BASE IOSTRINGOP INSB I186 FIXED_BASE0:NOTSX:BYTEOP +INSD BASE IOSTRINGOP INSD I386 FIXED_BASE0:NOTSX +INSERTPS SSE4 SSE INSERTPS_XMMps_MEMd_IMMb SSE4 INVALID +INSERTPS SSE4 SSE INSERTPS_XMMps_XMMps_IMMb SSE4 INVALID +INSERTQ SSE4a BITBYTE INSERTQ_XMMq_XMMdq SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +INSERTQ SSE4a BITBYTE INSERTQ_XMMq_XMMq_IMMb_IMMb SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +INSW BASE IOSTRINGOP INSW I186 FIXED_BASE0:NOTSX +INT1 BASE INTERRUPT INT1 I86 INVALID +INT3 BASE INTERRUPT INT3 I86 NOTSX +INTO BASE INTERRUPT INTO I86 NOTSX +INT BASE INTERRUPT INT_IMMb I86 NOTSX +INVD BASE SYSTEM INVD I486REAL RING0:NOTSX +INVEPT VTX VTX INVEPT_GPR32_MEMdq VTX RING0:NOTSX +INVEPT VTX VTX INVEPT_GPR64_MEMdq VTX RING0:NOTSX +INVLPGA SVM SYSTEM INVLPGA_ArAX_ECX SVM PROTECTED_MODE:AMDONLY +INVLPGB AMD_INVLPGB SYSTEM INVLPGB_EAX_EDX_ECX AMD_INVLPGB AMDONLY +INVLPGB AMD_INVLPGB SYSTEM INVLPGB_RAX_EDX_ECX AMD_INVLPGB AMDONLY +INVLPG BASE SYSTEM INVLPG_MEMb I486REAL ATT_OPERAND_ORDER_EXCEPTION:BYTEOP:RING0:NOTSX +INVPCID INVPCID MISC INVPCID_GPR32_MEMdq INVPCID RING0:NOTSX +INVPCID INVPCID MISC INVPCID_GPR64_MEMdq INVPCID RING0:NOTSX +INVVPID VTX VTX INVVPID_GPR32_MEMdq VTX RING0:NOTSX +INVVPID VTX VTX INVVPID_GPR64_MEMdq VTX RING0:NOTSX +IN BASE IO IN_AL_DX I86 BYTEOP +IN BASE IO IN_AL_IMMb I86 BYTEOP:NOTSX +IN BASE IO IN_OeAX_DX I86 SCALABLE +IN BASE IO IN_OeAX_IMMb I86 NOTSX:SCALABLE +IRET BASE RET IRET I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +IRETD BASE RET IRETD I386 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +IRETQ LONGMODE RET IRETQ LONGMODE NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +JBE BASE COND_BR JBE_RELBRb I86 MPX_PREFIX_ABLE +JBE BASE COND_BR JBE_RELBRd I86 MPX_PREFIX_ABLE +JBE BASE COND_BR JBE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JB BASE COND_BR JB_RELBRb I86 MPX_PREFIX_ABLE +JB BASE COND_BR JB_RELBRd I86 MPX_PREFIX_ABLE +JB BASE COND_BR JB_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JCXZ BASE COND_BR JCXZ_RELBRb I386 INVALID +JECXZ BASE COND_BR JECXZ_RELBRb I386 INVALID +JLE BASE COND_BR JLE_RELBRb I86 MPX_PREFIX_ABLE +JLE BASE COND_BR JLE_RELBRd I86 MPX_PREFIX_ABLE +JLE BASE COND_BR JLE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JL BASE COND_BR JL_RELBRb I86 MPX_PREFIX_ABLE +JL BASE COND_BR JL_RELBRd I86 MPX_PREFIX_ABLE +JL BASE COND_BR JL_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JMP_FAR BASE UNCOND_BR JMP_FAR_MEMp2 I86 FAR_XFER:NOTSX:INDIRECT_BRANCH:SCALABLE +JMP_FAR BASE UNCOND_BR JMP_FAR_PTRp_IMMw I86 FAR_XFER:NOTSX:SCALABLE +JMP BASE UNCOND_BR JMP_GPRv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:SCALABLE +JMP BASE UNCOND_BR JMP_MEMv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:SCALABLE +JMP BASE UNCOND_BR JMP_RELBRb I86 INVALID +JMP BASE UNCOND_BR JMP_RELBRd I86 MPX_PREFIX_ABLE +JMP BASE UNCOND_BR JMP_RELBRz I86 MPX_PREFIX_ABLE:SCALABLE +JNBE BASE COND_BR JNBE_RELBRb I86 MPX_PREFIX_ABLE +JNBE BASE COND_BR JNBE_RELBRd I86 MPX_PREFIX_ABLE +JNBE BASE COND_BR JNBE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNB BASE COND_BR JNB_RELBRb I86 MPX_PREFIX_ABLE +JNB BASE COND_BR JNB_RELBRd I86 MPX_PREFIX_ABLE +JNB BASE COND_BR JNB_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNLE BASE COND_BR JNLE_RELBRb I86 MPX_PREFIX_ABLE +JNLE BASE COND_BR JNLE_RELBRd I86 MPX_PREFIX_ABLE +JNLE BASE COND_BR JNLE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNL BASE COND_BR JNL_RELBRb I86 MPX_PREFIX_ABLE +JNL BASE COND_BR JNL_RELBRd I86 MPX_PREFIX_ABLE +JNL BASE COND_BR JNL_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNO BASE COND_BR JNO_RELBRb I86 MPX_PREFIX_ABLE +JNO BASE COND_BR JNO_RELBRd I86 MPX_PREFIX_ABLE +JNO BASE COND_BR JNO_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNP BASE COND_BR JNP_RELBRb I86 MPX_PREFIX_ABLE +JNP BASE COND_BR JNP_RELBRd I86 MPX_PREFIX_ABLE +JNP BASE COND_BR JNP_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNS BASE COND_BR JNS_RELBRb I86 MPX_PREFIX_ABLE +JNS BASE COND_BR JNS_RELBRd I86 MPX_PREFIX_ABLE +JNS BASE COND_BR JNS_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNZ BASE COND_BR JNZ_RELBRb I86 MPX_PREFIX_ABLE +JNZ BASE COND_BR JNZ_RELBRd I86 MPX_PREFIX_ABLE +JNZ BASE COND_BR JNZ_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JO BASE COND_BR JO_RELBRb I86 MPX_PREFIX_ABLE +JO BASE COND_BR JO_RELBRd I86 MPX_PREFIX_ABLE +JO BASE COND_BR JO_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JP BASE COND_BR JP_RELBRb I86 MPX_PREFIX_ABLE +JP BASE COND_BR JP_RELBRd I86 MPX_PREFIX_ABLE +JP BASE COND_BR JP_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JRCXZ BASE COND_BR JRCXZ_RELBRb LONGMODE INVALID +JS BASE COND_BR JS_RELBRb I86 MPX_PREFIX_ABLE +JS BASE COND_BR JS_RELBRd I86 MPX_PREFIX_ABLE +JS BASE COND_BR JS_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JZ BASE COND_BR JZ_RELBRb I86 MPX_PREFIX_ABLE +JZ BASE COND_BR JZ_RELBRd I86 MPX_PREFIX_ABLE +JZ BASE COND_BR JZ_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +KADDB AVX512VEX KMASK KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KADDD AVX512VEX KMASK KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KADDQ AVX512VEX KMASK KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KADDW AVX512VEX KMASK KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KANDB AVX512VEX KMASK KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KANDD AVX512VEX KMASK KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDNB AVX512VEX KMASK KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KANDND AVX512VEX KMASK KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDNQ AVX512VEX KMASK KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDNW AVX512VEX KMASK KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KANDQ AVX512VEX KMASK KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDW AVX512VEX KMASK KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_GPR32u32_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MASKmskw_GPR32u32_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MASKmskw_MASKu8_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MASKmskw_MEMu8_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MEMu8_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_GPR32u32_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MASKmskw_GPR32u32_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MASKmskw_MASKu32_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MASKmskw_MEMu32_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MEMu32_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_GPR64u64_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MASKmskw_GPR64u64_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MASKmskw_MASKu64_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MASKmskw_MEMu64_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MEMu64_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_GPR32u32_MASKmskw_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MASKmskw_GPR32u32_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MASKmskw_MASKu16_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MASKmskw_MEMu16_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MEMu16_MASKmskw_AVX512 AVX512F_KOP KMASK +KNOTB AVX512VEX KMASK KNOTB_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KNOTD AVX512VEX KMASK KNOTD_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KNOTQ AVX512VEX KMASK KNOTQ_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KNOTW AVX512VEX KMASK KNOTW_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KORB AVX512VEX KMASK KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KORD AVX512VEX KMASK KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORQ AVX512VEX KMASK KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORTESTB AVX512VEX KMASK KORTESTB_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KORTESTD AVX512VEX KMASK KORTESTD_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORTESTQ AVX512VEX KMASK KORTESTQ_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORTESTW AVX512VEX KMASK KORTESTW_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KORW AVX512VEX KMASK KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KSHIFTLB AVX512VEX KMASK KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 AVX512DQ_KOP KMASK +KSHIFTLD AVX512VEX KMASK KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTLQ AVX512VEX KMASK KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTLW AVX512VEX KMASK KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 AVX512F_KOP KMASK +KSHIFTRB AVX512VEX KMASK KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 AVX512DQ_KOP KMASK +KSHIFTRD AVX512VEX KMASK KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTRQ AVX512VEX KMASK KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTRW AVX512VEX KMASK KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 AVX512F_KOP KMASK +KTESTB AVX512VEX KMASK KTESTB_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KTESTD AVX512VEX KMASK KTESTD_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KTESTQ AVX512VEX KMASK KTESTQ_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KTESTW AVX512VEX KMASK KTESTW_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KUNPCKBW AVX512VEX KMASK KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KUNPCKDQ AVX512VEX KMASK KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KUNPCKWD AVX512VEX KMASK KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXNORB AVX512VEX KMASK KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KXNORD AVX512VEX KMASK KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXNORQ AVX512VEX KMASK KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXNORW AVX512VEX KMASK KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KXORB AVX512VEX KMASK KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KXORD AVX512VEX KMASK KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXORQ AVX512VEX KMASK KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXORW AVX512VEX KMASK KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +LAHF BASE FLAGOP LAHF LAHF INVALID +LAR BASE SYSTEM LAR_GPRv_GPRv I286PROTECTED PROTECTED_MODE:SCALABLE +LAR BASE SYSTEM LAR_GPRv_MEMw I286PROTECTED PROTECTED_MODE:SCALABLE +LDDQU SSE3 SSE LDDQU_XMMpd_MEMdq SSE3 INVALID +LDMXCSR SSE SSE LDMXCSR_MEMd SSEMXCSR MXCSR +LDS BASE SEGOP LDS_GPRz_MEMp I86 NOTSX:SCALABLE +LDTILECFG AMX_TILE AMX_TILE LDTILECFG_MEM AMX_TILE NOTSX +LEAVE BASE MISC LEAVE I186 FIXED_BASE0:SCALABLE +LEA BASE MISC LEA_GPRv_AGEN I86 SCALABLE +LES BASE SEGOP LES_GPRz_MEMp I86 NOTSX:SCALABLE +LFENCE SSE2 MISC LFENCE SSE2 IGNORES_OSFXSR +LFS BASE SEGOP LFS_GPRv_MEMp2 I386 NOTSX:SCALABLE +LGDT BASE SYSTEM LGDT_MEMs I286REAL NOTSX:SCALABLE +LGDT BASE SYSTEM LGDT_MEMs64 I286REAL NOTSX +LGS BASE SEGOP LGS_GPRv_MEMp2 I386 NOTSX:SCALABLE +LIDT BASE SYSTEM LIDT_MEMs I286REAL RING0:NOTSX:SCALABLE +LIDT BASE SYSTEM LIDT_MEMs64 I286REAL RING0:NOTSX +LLDT BASE SYSTEM LLDT_GPR16 I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LLDT BASE SYSTEM LLDT_MEMw I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LLWPCB XOP XOP LLWPCB_VGPRyy LWP AMDONLY:SCALABLE +LMSW BASE SYSTEM LMSW_GPR16 I286REAL RING0:NOTSX +LMSW BASE SYSTEM LMSW_MEMw I286REAL RING0:NOTSX +LOADIWKEY KEYLOCKER KEYLOCKER LOADIWKEY_XMMu8_XMMu8 KEYLOCKER INVALID +LODSB BASE STRINGOP LODSB I86 FIXED_BASE0:BYTEOP +LODSD BASE STRINGOP LODSD I386 FIXED_BASE0 +LODSQ LONGMODE STRINGOP LODSQ LONGMODE FIXED_BASE0 +LODSW BASE STRINGOP LODSW I86 FIXED_BASE0 +LOOPE BASE COND_BR LOOPE_RELBRb I86 INVALID +LOOPNE BASE COND_BR LOOPNE_RELBRb I86 INVALID +LOOP BASE COND_BR LOOP_RELBRb I86 INVALID +LSL BASE SYSTEM LSL_GPRv_GPRz I286PROTECTED PROTECTED_MODE:SCALABLE +LSL BASE SYSTEM LSL_GPRv_MEMw I286PROTECTED PROTECTED_MODE:SCALABLE +LSS BASE SEGOP LSS_GPRv_MEMp2 I386 NOTSX:SCALABLE +LTR BASE SYSTEM LTR_GPR16 I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LTR BASE SYSTEM LTR_MEMw I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LWPINS XOP XOP LWPINS_VGPRyy_MEMd_IMMd LWP AMDONLY:SCALABLE +LWPINS XOP XOP LWPINS_VGPRyy_VGPR32y_IMMd LWP AMDONLY:SCALABLE +LWPVAL XOP XOP LWPVAL_VGPRyy_MEMd_IMMd LWP AMDONLY:SCALABLE +LWPVAL XOP XOP LWPVAL_VGPRyy_VGPR32y_IMMd LWP AMDONLY:SCALABLE +LZCNT LZCNT LZCNT LZCNT_GPRv_GPRv LZCNT SCALABLE +LZCNT LZCNT LZCNT LZCNT_GPRv_MEMv LZCNT SCALABLE +MASKMOVDQU SSE2 DATAXFER MASKMOVDQU_XMMdq_XMMdq SSE2 FIXED_BASE0:MASKOP:NOTSX:NONTEMPORAL +MASKMOVQ MMX DATAXFER MASKMOVQ_MMXq_MMXq PENTIUMMMX FIXED_BASE0:MASKOP:NOTSX:NONTEMPORAL +MAXPD SSE2 SSE MAXPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MXCSR +MAXPD SSE2 SSE MAXPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MXCSR +MAXPS SSE SSE MAXPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +MAXPS SSE SSE MAXPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +MAXSD SSE2 SSE MAXSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +MAXSD SSE2 SSE MAXSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +MAXSS SSE SSE MAXSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +MAXSS SSE SSE MAXSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +MCOMMIT MCOMMIT MISC MCOMMIT MCOMMIT AMDONLY +MFENCE SSE2 MISC MFENCE SSE2 IGNORES_OSFXSR +MINPD SSE2 SSE MINPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MINPD SSE2 SSE MINPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MINPS SSE SSE MINPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +MINPS SSE SSE MINPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +MINSD SSE2 SSE MINSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +MINSD SSE2 SSE MINSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +MINSS SSE SSE MINSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +MINSS SSE SSE MINSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +MONITOR MONITOR MISC MONITOR MONITOR RING0:NOTSX +MONITORX MONITORX MISC MONITORX MONITORX AMDONLY +MOVAPD SSE2 DATAXFER MOVAPD_MEMpd_XMMpd SSE2 REQUIRES_ALIGNMENT +MOVAPD SSE2 DATAXFER MOVAPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT +MOVAPD SSE2 DATAXFER MOVAPD_XMMpd_XMMpd_0F28 SSE2 REQUIRES_ALIGNMENT +MOVAPD SSE2 DATAXFER MOVAPD_XMMpd_XMMpd_0F29 SSE2 REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_MEMps_XMMps SSE REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_XMMps_XMMps_0F28 SSE REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_XMMps_XMMps_0F29 SSE REQUIRES_ALIGNMENT +MOVBE MOVBE DATAXFER MOVBE_GPRv_MEMv MOVBE SCALABLE +MOVBE MOVBE DATAXFER MOVBE_MEMv_GPRv MOVBE SCALABLE +MOVDDUP SSE3 DATAXFER MOVDDUP_XMMdq_MEMq SSE3 INVALID +MOVDDUP SSE3 DATAXFER MOVDDUP_XMMdq_XMMq SSE3 INVALID +MOVDIR64B MOVDIR MOVDIR MOVDIR64B_GPRa_MEM MOVDIR REQUIRES_ALIGNMENT +MOVDIRI MOVDIR MOVDIR MOVDIRI_MEMu32_GPR32u32 MOVDIR INVALID +MOVDIRI MOVDIR MOVDIR MOVDIRI_MEMu64_GPR64u64 MOVDIR INVALID +MOVDQ2Q SSE2 DATAXFER MOVDQ2Q_MMXq_XMMq SSE2 MMX_EXCEPT:NOTSX +MOVDQA SSE2 DATAXFER MOVDQA_MEMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +MOVDQA SSE2 DATAXFER MOVDQA_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +MOVDQA SSE2 DATAXFER MOVDQA_XMMdq_XMMdq_0F6F SSE2 REQUIRES_ALIGNMENT +MOVDQA SSE2 DATAXFER MOVDQA_XMMdq_XMMdq_0F7F SSE2 REQUIRES_ALIGNMENT +MOVDQU SSE2 DATAXFER MOVDQU_MEMdq_XMMdq SSE2 INVALID +MOVDQU SSE2 DATAXFER MOVDQU_XMMdq_MEMdq SSE2 INVALID +MOVDQU SSE2 DATAXFER MOVDQU_XMMdq_XMMdq_0F6F SSE2 INVALID +MOVDQU SSE2 DATAXFER MOVDQU_XMMdq_XMMdq_0F7F SSE2 INVALID +MOVD MMX DATAXFER MOVD_GPR32_MMXd PENTIUMMMX NOTSX +MOVD SSE2 DATAXFER MOVD_GPR32_XMMd SSE2 INVALID +MOVD MMX DATAXFER MOVD_MEMd_MMXd PENTIUMMMX NOTSX +MOVD SSE2 DATAXFER MOVD_MEMd_XMMd SSE2 INVALID +MOVD MMX DATAXFER MOVD_MMXq_GPR32 PENTIUMMMX NOTSX +MOVD MMX DATAXFER MOVD_MMXq_MEMd PENTIUMMMX NOTSX +MOVD SSE2 DATAXFER MOVD_XMMdq_GPR32 SSE2 INVALID +MOVD SSE2 DATAXFER MOVD_XMMdq_MEMd SSE2 INVALID +MOVHLPS SSE DATAXFER MOVHLPS_XMMq_XMMq SSE INVALID +MOVHPD SSE2 DATAXFER MOVHPD_MEMq_XMMsd SSE2 INVALID +MOVHPD SSE2 DATAXFER MOVHPD_XMMsd_MEMq SSE2 INVALID +MOVHPS SSE DATAXFER MOVHPS_MEMq_XMMps SSE INVALID +MOVHPS SSE DATAXFER MOVHPS_XMMq_MEMq SSE INVALID +MOVLHPS SSE DATAXFER MOVLHPS_XMMq_XMMq SSE INVALID +MOVLPD SSE2 DATAXFER MOVLPD_MEMq_XMMsd SSE2 INVALID +MOVLPD SSE2 DATAXFER MOVLPD_XMMsd_MEMq SSE2 INVALID +MOVLPS SSE DATAXFER MOVLPS_MEMq_XMMq SSE INVALID +MOVLPS SSE DATAXFER MOVLPS_XMMq_MEMq SSE INVALID +MOVMSKPD SSE2 DATAXFER MOVMSKPD_GPR32_XMMpd SSE2 INVALID +MOVMSKPS SSE DATAXFER MOVMSKPS_GPR32_XMMps SSE INVALID +MOVNTDQA SSE4 SSE MOVNTDQA_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +MOVNTDQ SSE2 DATAXFER MOVNTDQ_MEMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +MOVNTI SSE2 DATAXFER MOVNTI_MEMd_GPR32 SSE2 IGNORES_OSFXSR:NOTSX:NONTEMPORAL +MOVNTI SSE2 DATAXFER MOVNTI_MEMq_GPR64 SSE2 IGNORES_OSFXSR:NOTSX:NONTEMPORAL +MOVNTPD SSE2 DATAXFER MOVNTPD_MEMdq_XMMpd SSE2 NOTSX:REQUIRES_ALIGNMENT:NONTEMPORAL +MOVNTPS SSE DATAXFER MOVNTPS_MEMdq_XMMps SSE NOTSX:REQUIRES_ALIGNMENT:NONTEMPORAL +MOVNTQ MMX DATAXFER MOVNTQ_MEMq_MMXq PENTIUMMMX NOTSX:NONTEMPORAL +MOVNTSD SSE4a DATAXFER MOVNTSD_MEMq_XMMq SSE4a NONTEMPORAL:AMDONLY +MOVNTSS SSE4a DATAXFER MOVNTSS_MEMd_XMMd SSE4a NONTEMPORAL:AMDONLY +MOVQ2DQ SSE2 DATAXFER MOVQ2DQ_XMMdq_MMXq SSE2 MMX_EXCEPT:NOTSX +MOVQ MMX DATAXFER MOVQ_GPR64_MMXq PENTIUMMMX NOTSX +MOVQ SSE2 DATAXFER MOVQ_GPR64_XMMq SSE2 INVALID +MOVQ MMX DATAXFER MOVQ_MEMq_MMXq_0F7E PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MEMq_MMXq_0F7F PENTIUMMMX NOTSX +MOVQ SSE2 DATAXFER MOVQ_MEMq_XMMq_0F7E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_MEMq_XMMq_0FD6 SSE2 INVALID +MOVQ MMX DATAXFER MOVQ_MMXq_GPR64 PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MEMq_0F6E PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MEMq_0F6F PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MMXq_0F6F PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MMXq_0F7F PENTIUMMMX NOTSX +MOVQ SSE2 DATAXFER MOVQ_XMMdq_GPR64 SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_MEMq_0F6E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_MEMq_0F7E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_XMMq_0F7E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_XMMq_0FD6 SSE2 INVALID +MOVSB BASE STRINGOP MOVSB I86 FIXED_BASE0:FIXED_BASE1:BYTEOP +MOVSD BASE STRINGOP MOVSD I386 FIXED_BASE0:FIXED_BASE1 +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_MEMsd_XMMsd SSE2 SIMD_SCALAR +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_XMMdq_MEMsd SSE2 SIMD_SCALAR +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_XMMsd_XMMsd_0F10 SSE2 SIMD_SCALAR +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_XMMsd_XMMsd_0F11 SSE2 SIMD_SCALAR +MOVSHDUP SSE3 DATAXFER MOVSHDUP_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT +MOVSHDUP SSE3 DATAXFER MOVSHDUP_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT +MOVSLDUP SSE3 DATAXFER MOVSLDUP_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT +MOVSLDUP SSE3 DATAXFER MOVSLDUP_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT +MOVSQ LONGMODE STRINGOP MOVSQ LONGMODE FIXED_BASE0:FIXED_BASE1 +MOVSS SSE DATAXFER MOVSS_MEMss_XMMss SSE SIMD_SCALAR +MOVSS SSE DATAXFER MOVSS_XMMdq_MEMss SSE SIMD_SCALAR +MOVSS SSE DATAXFER MOVSS_XMMss_XMMss_0F10 SSE SIMD_SCALAR +MOVSS SSE DATAXFER MOVSS_XMMss_XMMss_0F11 SSE SIMD_SCALAR +MOVSW BASE STRINGOP MOVSW I86 FIXED_BASE0:FIXED_BASE1 +MOVSXD LONGMODE DATAXFER MOVSXD_GPRv_GPRz LONGMODE SCALABLE +MOVSXD LONGMODE DATAXFER MOVSXD_GPRv_MEMz LONGMODE SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_GPR16 I386 SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_GPR8 I386 SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_MEMb I386 SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_MEMw I386 SCALABLE +MOVUPD SSE2 DATAXFER MOVUPD_MEMpd_XMMpd SSE2 INVALID +MOVUPD SSE2 DATAXFER MOVUPD_XMMpd_MEMpd SSE2 INVALID +MOVUPD SSE2 DATAXFER MOVUPD_XMMpd_XMMpd_0F10 SSE2 INVALID +MOVUPD SSE2 DATAXFER MOVUPD_XMMpd_XMMpd_0F11 SSE2 INVALID +MOVUPS SSE DATAXFER MOVUPS_MEMps_XMMps SSE INVALID +MOVUPS SSE DATAXFER MOVUPS_XMMps_MEMps SSE INVALID +MOVUPS SSE DATAXFER MOVUPS_XMMps_XMMps_0F10 SSE INVALID +MOVUPS SSE DATAXFER MOVUPS_XMMps_XMMps_0F11 SSE INVALID +MOVZX BASE DATAXFER MOVZX_GPRv_GPR16 I386 SCALABLE +MOVZX BASE DATAXFER MOVZX_GPRv_GPR8 I386 SCALABLE +MOVZX BASE DATAXFER MOVZX_GPRv_MEMb I386 SCALABLE +MOVZX BASE DATAXFER MOVZX_GPRv_MEMw I386 SCALABLE +MOV BASE DATAXFER MOV_AL_MEMb I86 FIXED_BASE0:BYTEOP +MOV_CR BASE DATAXFER MOV_CR_CR_GPR32 I86 RING0:NOTSX +MOV_CR BASE DATAXFER MOV_CR_CR_GPR64 I86 RING0:NOTSX +MOV_CR BASE DATAXFER MOV_CR_GPR32_CR I86 RING0 +MOV_CR BASE DATAXFER MOV_CR_GPR64_CR I86 RING0 +MOV_DR BASE DATAXFER MOV_DR_DR_GPR32 I86 RING0:NOTSX +MOV_DR BASE DATAXFER MOV_DR_DR_GPR64 I86 RING0:NOTSX +MOV_DR BASE DATAXFER MOV_DR_GPR32_DR I86 RING0 +MOV_DR BASE DATAXFER MOV_DR_GPR64_DR I86 RING0 +MOV BASE DATAXFER MOV_GPR8_GPR8_88 I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_GPR8_8A I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_IMMb_B0 I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_IMMb_C6r0 I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_MEMb I86 BYTEOP +MOV BASE DATAXFER MOV_GPRv_GPRv_89 I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_GPRv_8B I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_IMMv I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_IMMz I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_MEMv I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_SEG I86 SCALABLE +MOV BASE DATAXFER MOV_MEMb_AL I86 FIXED_BASE0:BYTEOP +MOV BASE DATAXFER MOV_MEMb_GPR8 I86 BYTEOP:HLE_REL_ABLE +MOV BASE DATAXFER MOV_MEMb_IMMb I86 BYTEOP:HLE_REL_ABLE +MOV BASE DATAXFER MOV_MEMv_GPRv I86 HLE_REL_ABLE:SCALABLE +MOV BASE DATAXFER MOV_MEMv_IMMz I86 HLE_REL_ABLE:SCALABLE +MOV BASE DATAXFER MOV_MEMv_OrAX I86 FIXED_BASE0:SCALABLE +MOV BASE DATAXFER MOV_MEMw_SEG I86 INVALID +MOV BASE DATAXFER MOV_OrAX_MEMv I86 FIXED_BASE0:SCALABLE +MOV BASE DATAXFER MOV_SEG_GPR16 I86 NOTSX +MOV BASE DATAXFER MOV_SEG_MEMw I86 NOTSX +MPSADBW SSE4 SSE MPSADBW_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +MPSADBW SSE4 SSE MPSADBW_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +MULPD SSE2 SSE MULPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MULPD SSE2 SSE MULPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MULPS SSE SSE MULPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +MULPS SSE SSE MULPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +MULSD SSE2 SSE MULSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +MULSD SSE2 SSE MULSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +MULSS SSE SSE MULSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +MULSS SSE SSE MULSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +MULX BMI2 BMI2 MULX_VGPR32d_VGPR32d_MEMd BMI2 INVALID +MULX BMI2 BMI2 MULX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +MULX BMI2 BMI2 MULX_VGPR64q_VGPR64q_MEMq BMI2 INVALID +MULX BMI2 BMI2 MULX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +MUL BASE BINARY MUL_GPR8 I86 BYTEOP +MUL BASE BINARY MUL_GPRv I86 SCALABLE +MUL BASE BINARY MUL_MEMb I86 BYTEOP +MUL BASE BINARY MUL_MEMv I86 SCALABLE +MWAIT MONITOR MISC MWAIT MONITOR RING0:NOTSX +MWAITX MONITORX MISC MWAITX MONITORX AMDONLY +NEG BASE BINARY NEG_GPR8 I86 BYTEOP +NEG BASE BINARY NEG_GPRv I86 SCALABLE +NEG_LOCK BASE BINARY NEG_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +NEG_LOCK BASE BINARY NEG_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +NEG BASE BINARY NEG_MEMb I86 BYTEOP:LOCKABLE +NEG BASE BINARY NEG_MEMv I86 LOCKABLE:SCALABLE +NOP BASE NOP NOP_90 I86 NOP +NOP BASE WIDENOP NOP_GPRv_0F18r0 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r1 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r2 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r3 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r4 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r5 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r6 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r7 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F0D PREFETCH_NOP SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F19 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1A PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1B PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1C PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1D FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1E PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1F FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_MEM_0F1B PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_MEMv_0F1A PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r4 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r5 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r6 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r7 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F19 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1C PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1D FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1E PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1F FAT_NOP NOP:SCALABLE +NOT BASE LOGICAL NOT_GPR8 I86 BYTEOP +NOT BASE LOGICAL NOT_GPRv I86 SCALABLE +NOT_LOCK BASE LOGICAL NOT_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +NOT_LOCK BASE LOGICAL NOT_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +NOT BASE LOGICAL NOT_MEMb I86 BYTEOP:LOCKABLE +NOT BASE LOGICAL NOT_MEMv I86 LOCKABLE:SCALABLE +ORPD SSE2 LOGICAL_FP ORPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +ORPD SSE2 LOGICAL_FP ORPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +ORPS SSE LOGICAL_FP ORPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +ORPS SSE LOGICAL_FP ORPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +OR BASE LOGICAL OR_AL_IMMb I86 BYTEOP +OR BASE LOGICAL OR_GPR8_GPR8_08 I86 BYTEOP +OR BASE LOGICAL OR_GPR8_GPR8_0A I86 BYTEOP +OR BASE LOGICAL OR_GPR8_IMMb_80r1 I86 BYTEOP +OR BASE LOGICAL OR_GPR8_IMMb_82r1 I86 BYTEOP +OR BASE LOGICAL OR_GPR8_MEMb I86 BYTEOP +OR BASE LOGICAL OR_GPRv_GPRv_09 I86 SCALABLE +OR BASE LOGICAL OR_GPRv_GPRv_0B I86 SCALABLE +OR BASE LOGICAL OR_GPRv_IMMb I86 SCALABLE +OR BASE LOGICAL OR_GPRv_IMMz I86 SCALABLE +OR BASE LOGICAL OR_GPRv_MEMv I86 SCALABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMb_IMMb_80r1 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMb_IMMb_82r1 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +OR BASE LOGICAL OR_MEMb_GPR8 I86 BYTEOP:LOCKABLE +OR BASE LOGICAL OR_MEMb_IMMb_80r1 I86 BYTEOP:LOCKABLE +OR BASE LOGICAL OR_MEMb_IMMb_82r1 I86 BYTEOP:LOCKABLE +OR BASE LOGICAL OR_MEMv_GPRv I86 LOCKABLE:SCALABLE +OR BASE LOGICAL OR_MEMv_IMMb I86 LOCKABLE:SCALABLE +OR BASE LOGICAL OR_MEMv_IMMz I86 LOCKABLE:SCALABLE +OR BASE LOGICAL OR_OrAX_IMMz I86 SCALABLE +OUTSB BASE IOSTRINGOP OUTSB I186 FIXED_BASE0:NOTSX:BYTEOP +OUTSD BASE IOSTRINGOP OUTSD I386 FIXED_BASE0:NOTSX +OUTSW BASE IOSTRINGOP OUTSW I186 FIXED_BASE0:NOTSX +OUT BASE IO OUT_DX_AL I86 BYTEOP +OUT BASE IO OUT_DX_OeAX I86 SCALABLE +OUT BASE IO OUT_IMMb_AL I86 NOTSX:BYTEOP +OUT BASE IO OUT_IMMb_OeAX I86 NOTSX:SCALABLE +PABSB SSSE3 MMX PABSB_MMXq_MEMq SSSE3MMX NOTSX +PABSB SSSE3 MMX PABSB_MMXq_MMXq SSSE3MMX NOTSX +PABSB SSSE3 SSE PABSB_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PABSB SSSE3 SSE PABSB_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PABSD SSSE3 MMX PABSD_MMXq_MEMq SSSE3MMX SIMD_SCALAR:NOTSX +PABSD SSSE3 MMX PABSD_MMXq_MMXq SSSE3MMX SIMD_SCALAR:NOTSX +PABSD SSSE3 SSE PABSD_XMMdq_MEMdq SSSE3 SIMD_SCALAR:REQUIRES_ALIGNMENT +PABSD SSSE3 SSE PABSD_XMMdq_XMMdq SSSE3 SIMD_SCALAR +PABSW SSSE3 MMX PABSW_MMXq_MEMq SSSE3MMX NOTSX +PABSW SSSE3 MMX PABSW_MMXq_MMXq SSSE3MMX NOTSX +PABSW SSSE3 SSE PABSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PABSW SSSE3 SSE PABSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PACKSSDW MMX MMX PACKSSDW_MMXq_MEMq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSDW MMX MMX PACKSSDW_MMXq_MMXq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSDW SSE2 SSE PACKSSDW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKSSDW SSE2 SSE PACKSSDW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKSSWB MMX MMX PACKSSWB_MMXq_MEMq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSWB MMX MMX PACKSSWB_MMXq_MMXq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSWB SSE2 SSE PACKSSWB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKSSWB SSE2 SSE PACKSSWB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSDW SSE4 SSE PACKUSDW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSDW SSE4 SSE PACKUSDW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSWB MMX MMX PACKUSWB_MMXq_MEMq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKUSWB MMX MMX PACKUSWB_MMXq_MMXq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKUSWB SSE2 SSE PACKUSWB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSWB SSE2 SSE PACKUSWB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PADDB MMX MMX PADDB_MMXq_MEMq PENTIUMMMX NOTSX +PADDB MMX MMX PADDB_MMXq_MMXq PENTIUMMMX NOTSX +PADDB SSE2 SSE PADDB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDB SSE2 SSE PADDB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDD MMX MMX PADDD_MMXq_MEMq PENTIUMMMX NOTSX +PADDD MMX MMX PADDD_MMXq_MMXq PENTIUMMMX NOTSX +PADDD SSE2 SSE PADDD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDD SSE2 SSE PADDD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDQ SSE2 MMX PADDQ_MMXq_MEMq SSE2MMX NOTSX +PADDQ SSE2 MMX PADDQ_MMXq_MMXq SSE2MMX NOTSX +PADDQ SSE2 SSE PADDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDQ SSE2 SSE PADDQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDSB MMX MMX PADDSB_MMXq_MEMq PENTIUMMMX NOTSX +PADDSB MMX MMX PADDSB_MMXq_MMXq PENTIUMMMX NOTSX +PADDSB SSE2 SSE PADDSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDSB SSE2 SSE PADDSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDSW MMX MMX PADDSW_MMXq_MEMq PENTIUMMMX NOTSX +PADDSW MMX MMX PADDSW_MMXq_MMXq PENTIUMMMX NOTSX +PADDSW SSE2 SSE PADDSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDSW SSE2 SSE PADDSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDUSB MMX MMX PADDUSB_MMXq_MEMq PENTIUMMMX NOTSX +PADDUSB MMX MMX PADDUSB_MMXq_MMXq PENTIUMMMX NOTSX +PADDUSB SSE2 SSE PADDUSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDUSB SSE2 SSE PADDUSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDUSW MMX MMX PADDUSW_MMXq_MEMq PENTIUMMMX NOTSX +PADDUSW MMX MMX PADDUSW_MMXq_MMXq PENTIUMMMX NOTSX +PADDUSW SSE2 SSE PADDUSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDUSW SSE2 SSE PADDUSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDW MMX MMX PADDW_MMXq_MEMq PENTIUMMMX NOTSX +PADDW MMX MMX PADDW_MMXq_MMXq PENTIUMMMX NOTSX +PADDW SSE2 SSE PADDW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDW SSE2 SSE PADDW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PALIGNR SSSE3 MMX PALIGNR_MMXq_MEMq_IMMb SSSE3MMX NOTSX +PALIGNR SSSE3 MMX PALIGNR_MMXq_MMXq_IMMb SSSE3MMX NOTSX +PALIGNR SSSE3 SSE PALIGNR_XMMdq_MEMdq_IMMb SSSE3 REQUIRES_ALIGNMENT +PALIGNR SSSE3 SSE PALIGNR_XMMdq_XMMdq_IMMb SSSE3 REQUIRES_ALIGNMENT +PANDN MMX LOGICAL PANDN_MMXq_MEMq PENTIUMMMX NOTSX +PANDN MMX LOGICAL PANDN_MMXq_MMXq PENTIUMMMX NOTSX +PANDN SSE2 LOGICAL PANDN_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PANDN SSE2 LOGICAL PANDN_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PAND MMX LOGICAL PAND_MMXq_MEMq PENTIUMMMX NOTSX +PAND MMX LOGICAL PAND_MMXq_MMXq PENTIUMMMX NOTSX +PAND SSE2 LOGICAL PAND_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PAND SSE2 LOGICAL PAND_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PAUSE PAUSE MISC PAUSE PAUSE NOTSX +PAVGB MMX MMX PAVGB_MMXq_MEMq PENTIUMMMX NOTSX +PAVGB MMX MMX PAVGB_MMXq_MMXq PENTIUMMMX NOTSX +PAVGB SSE2 SSE PAVGB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PAVGB SSE2 SSE PAVGB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PAVGUSB 3DNOW 3DNOW PAVGUSB_MMXq_MEMq 3DNOW AMDONLY +PAVGUSB 3DNOW 3DNOW PAVGUSB_MMXq_MMXq 3DNOW AMDONLY +PAVGW MMX MMX PAVGW_MMXq_MEMq PENTIUMMMX NOTSX +PAVGW MMX MMX PAVGW_MMXq_MMXq PENTIUMMMX NOTSX +PAVGW SSE2 SSE PAVGW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PAVGW SSE2 SSE PAVGW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PBLENDVB SSE4 SSE PBLENDVB_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PBLENDVB SSE4 SSE PBLENDVB_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PBLENDW SSE4 SSE PBLENDW_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT +PBLENDW SSE4 SSE PBLENDW_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT +PCLMULQDQ PCLMULQDQ PCLMULQDQ PCLMULQDQ_XMMdq_MEMdq_IMMb PCLMULQDQ REQUIRES_ALIGNMENT +PCLMULQDQ PCLMULQDQ PCLMULQDQ PCLMULQDQ_XMMdq_XMMdq_IMMb PCLMULQDQ REQUIRES_ALIGNMENT +PCMPEQB MMX MMX PCMPEQB_MMXq_MEMq PENTIUMMMX NOTSX +PCMPEQB MMX MMX PCMPEQB_MMXq_MMXq PENTIUMMMX NOTSX +PCMPEQB SSE2 SSE PCMPEQB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQB SSE2 SSE PCMPEQB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQD MMX MMX PCMPEQD_MMXq_MEMq PENTIUMMMX NOTSX +PCMPEQD MMX MMX PCMPEQD_MMXq_MMXq PENTIUMMMX NOTSX +PCMPEQD SSE2 SSE PCMPEQD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQD SSE2 SSE PCMPEQD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQQ SSE4 SSE PCMPEQQ_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PCMPEQQ SSE4 SSE PCMPEQQ_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PCMPEQW MMX MMX PCMPEQW_MMXq_MEMq PENTIUMMMX NOTSX +PCMPEQW MMX MMX PCMPEQW_MMXq_MMXq PENTIUMMMX NOTSX +PCMPEQW SSE2 SSE PCMPEQW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQW SSE2 SSE PCMPEQW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPESTRI64 SSE4 SSE PCMPESTRI64_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRI64 SSE4 SSE PCMPESTRI64_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPESTRI SSE4 SSE PCMPESTRI_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRI SSE4 SSE PCMPESTRI_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPESTRM64 SSE4 SSE PCMPESTRM64_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRM64 SSE4 SSE PCMPESTRM64_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPESTRM SSE4 SSE PCMPESTRM_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRM SSE4 SSE PCMPESTRM_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPGTB MMX MMX PCMPGTB_MMXq_MEMq PENTIUMMMX NOTSX +PCMPGTB MMX MMX PCMPGTB_MMXq_MMXq PENTIUMMMX NOTSX +PCMPGTB SSE2 SSE PCMPGTB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTB SSE2 SSE PCMPGTB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTD MMX MMX PCMPGTD_MMXq_MEMq PENTIUMMMX NOTSX +PCMPGTD MMX MMX PCMPGTD_MMXq_MMXq PENTIUMMMX NOTSX +PCMPGTD SSE2 SSE PCMPGTD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTD SSE2 SSE PCMPGTD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTQ SSE4 SSE PCMPGTQ_XMMdq_MEMdq SSE42 REQUIRES_ALIGNMENT +PCMPGTQ SSE4 SSE PCMPGTQ_XMMdq_XMMdq SSE42 REQUIRES_ALIGNMENT +PCMPGTW MMX MMX PCMPGTW_MMXq_MEMq PENTIUMMMX NOTSX +PCMPGTW MMX MMX PCMPGTW_MMXq_MMXq PENTIUMMMX NOTSX +PCMPGTW SSE2 SSE PCMPGTW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTW SSE2 SSE PCMPGTW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPISTRI64 SSE4 SSE PCMPISTRI64_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPISTRI64 SSE4 SSE PCMPISTRI64_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPISTRI SSE4 SSE PCMPISTRI_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPISTRI SSE4 SSE PCMPISTRI_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPISTRM SSE4 SSE PCMPISTRM_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPISTRM SSE4 SSE PCMPISTRM_XMMdq_XMMdq_IMMb SSE42 INVALID +PCONFIG PCONFIG PCONFIG PCONFIG PCONFIG INVALID +PCONFIG PCONFIG PCONFIG PCONFIG64 PCONFIG INVALID +PDEP BMI2 BMI2 PDEP_VGPR32d_VGPR32d_MEMd BMI2 INVALID +PDEP BMI2 BMI2 PDEP_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +PDEP BMI2 BMI2 PDEP_VGPR64q_VGPR64q_MEMq BMI2 INVALID +PDEP BMI2 BMI2 PDEP_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +PEXTRB SSE4 SSE PEXTRB_GPR32d_XMMdq_IMMb SSE4 INVALID +PEXTRB SSE4 SSE PEXTRB_MEMb_XMMdq_IMMb SSE4 INVALID +PEXTRD SSE4 SSE PEXTRD_GPR32d_XMMdq_IMMb SSE4 INVALID +PEXTRD SSE4 SSE PEXTRD_MEMd_XMMdq_IMMb SSE4 INVALID +PEXTRQ SSE4 SSE PEXTRQ_GPR64q_XMMdq_IMMb SSE4 INVALID +PEXTRQ SSE4 SSE PEXTRQ_MEMq_XMMdq_IMMb SSE4 INVALID +PEXTRW MMX MMX PEXTRW_GPR32_MMXq_IMMb PENTIUMMMX NOTSX +PEXTRW SSE2 SSE PEXTRW_GPR32_XMMdq_IMMb SSE2 INVALID +PEXTRW_SSE4 SSE4 SSE PEXTRW_SSE4_GPR32_XMMdq_IMMb SSE4 INVALID +PEXTRW_SSE4 SSE4 SSE PEXTRW_SSE4_MEMw_XMMdq_IMMb SSE4 INVALID +PEXT BMI2 BMI2 PEXT_VGPR32d_VGPR32d_MEMd BMI2 INVALID +PEXT BMI2 BMI2 PEXT_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +PEXT BMI2 BMI2 PEXT_VGPR64q_VGPR64q_MEMq BMI2 INVALID +PEXT BMI2 BMI2 PEXT_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +PF2ID 3DNOW 3DNOW PF2ID_MMXq_MEMq 3DNOW AMDONLY +PF2ID 3DNOW 3DNOW PF2ID_MMXq_MMXq 3DNOW AMDONLY +PF2IW 3DNOW 3DNOW PF2IW_MMXq_MEMq 3DNOW AMDONLY +PF2IW 3DNOW 3DNOW PF2IW_MMXq_MMXq 3DNOW AMDONLY +PFACC 3DNOW 3DNOW PFACC_MMXq_MEMq 3DNOW AMDONLY +PFACC 3DNOW 3DNOW PFACC_MMXq_MMXq 3DNOW AMDONLY +PFADD 3DNOW 3DNOW PFADD_MMXq_MEMq 3DNOW AMDONLY +PFADD 3DNOW 3DNOW PFADD_MMXq_MMXq 3DNOW AMDONLY +PFCMPEQ 3DNOW 3DNOW PFCMPEQ_MMXq_MEMq 3DNOW AMDONLY +PFCMPEQ 3DNOW 3DNOW PFCMPEQ_MMXq_MMXq 3DNOW AMDONLY +PFCMPGE 3DNOW 3DNOW PFCMPGE_MMXq_MEMq 3DNOW AMDONLY +PFCMPGE 3DNOW 3DNOW PFCMPGE_MMXq_MMXq 3DNOW AMDONLY +PFCMPGT 3DNOW 3DNOW PFCMPGT_MMXq_MEMq 3DNOW AMDONLY +PFCMPGT 3DNOW 3DNOW PFCMPGT_MMXq_MMXq 3DNOW AMDONLY +PFMAX 3DNOW 3DNOW PFMAX_MMXq_MEMq 3DNOW AMDONLY +PFMAX 3DNOW 3DNOW PFMAX_MMXq_MMXq 3DNOW AMDONLY +PFMIN 3DNOW 3DNOW PFMIN_MMXq_MEMq 3DNOW AMDONLY +PFMIN 3DNOW 3DNOW PFMIN_MMXq_MMXq 3DNOW AMDONLY +PFMUL 3DNOW 3DNOW PFMUL_MMXq_MEMq 3DNOW AMDONLY +PFMUL 3DNOW 3DNOW PFMUL_MMXq_MMXq 3DNOW AMDONLY +PFNACC 3DNOW 3DNOW PFNACC_MMXq_MEMq 3DNOW AMDONLY +PFNACC 3DNOW 3DNOW PFNACC_MMXq_MMXq 3DNOW AMDONLY +PFPNACC 3DNOW 3DNOW PFPNACC_MMXq_MEMq 3DNOW AMDONLY +PFPNACC 3DNOW 3DNOW PFPNACC_MMXq_MMXq 3DNOW AMDONLY +PFRCPIT1 3DNOW 3DNOW PFRCPIT1_MMXq_MEMq 3DNOW AMDONLY +PFRCPIT1 3DNOW 3DNOW PFRCPIT1_MMXq_MMXq 3DNOW AMDONLY +PFRCPIT2 3DNOW 3DNOW PFRCPIT2_MMXq_MEMq 3DNOW AMDONLY +PFRCPIT2 3DNOW 3DNOW PFRCPIT2_MMXq_MMXq 3DNOW AMDONLY +PFRCP 3DNOW 3DNOW PFRCP_MMXq_MEMq 3DNOW AMDONLY +PFRCP 3DNOW 3DNOW PFRCP_MMXq_MMXq 3DNOW AMDONLY +PFRSQIT1 3DNOW 3DNOW PFRSQIT1_MMXq_MEMq 3DNOW AMDONLY +PFRSQIT1 3DNOW 3DNOW PFRSQIT1_MMXq_MMXq 3DNOW AMDONLY +PFRSQRT 3DNOW 3DNOW PFRSQRT_MMXq_MEMq 3DNOW AMDONLY +PFRSQRT 3DNOW 3DNOW PFRSQRT_MMXq_MMXq 3DNOW AMDONLY +PFSUBR 3DNOW 3DNOW PFSUBR_MMXq_MEMq 3DNOW AMDONLY +PFSUBR 3DNOW 3DNOW PFSUBR_MMXq_MMXq 3DNOW AMDONLY +PFSUB 3DNOW 3DNOW PFSUB_MMXq_MEMq 3DNOW AMDONLY +PFSUB 3DNOW 3DNOW PFSUB_MMXq_MMXq 3DNOW AMDONLY +PHADDD SSSE3 MMX PHADDD_MMXq_MEMq SSSE3MMX NOTSX +PHADDD SSSE3 MMX PHADDD_MMXq_MMXq SSSE3MMX NOTSX +PHADDD SSSE3 SSE PHADDD_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHADDD SSSE3 SSE PHADDD_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHADDSW SSSE3 MMX PHADDSW_MMXq_MEMq SSSE3MMX NOTSX +PHADDSW SSSE3 MMX PHADDSW_MMXq_MMXq SSSE3MMX NOTSX +PHADDSW SSSE3 SSE PHADDSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHADDSW SSSE3 SSE PHADDSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHADDW SSSE3 MMX PHADDW_MMXq_MEMq SSSE3MMX NOTSX +PHADDW SSSE3 MMX PHADDW_MMXq_MMXq SSSE3MMX NOTSX +PHADDW SSSE3 SSE PHADDW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHADDW SSSE3 SSE PHADDW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHMINPOSUW SSE4 SSE PHMINPOSUW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PHMINPOSUW SSE4 SSE PHMINPOSUW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PHSUBD SSSE3 MMX PHSUBD_MMXq_MEMq SSSE3MMX NOTSX +PHSUBD SSSE3 MMX PHSUBD_MMXq_MMXq SSSE3MMX NOTSX +PHSUBD SSSE3 SSE PHSUBD_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBD SSSE3 SSE PHSUBD_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBSW SSSE3 MMX PHSUBSW_MMXq_MEMq SSSE3MMX NOTSX +PHSUBSW SSSE3 MMX PHSUBSW_MMXq_MMXq SSSE3MMX NOTSX +PHSUBSW SSSE3 SSE PHSUBSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBSW SSSE3 SSE PHSUBSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBW SSSE3 MMX PHSUBW_MMXq_MEMq SSSE3MMX NOTSX +PHSUBW SSSE3 MMX PHSUBW_MMXq_MMXq SSSE3MMX NOTSX +PHSUBW SSSE3 SSE PHSUBW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBW SSSE3 SSE PHSUBW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PI2FD 3DNOW 3DNOW PI2FD_MMXq_MEMq 3DNOW AMDONLY +PI2FD 3DNOW 3DNOW PI2FD_MMXq_MMXq 3DNOW AMDONLY +PI2FW 3DNOW 3DNOW PI2FW_MMXq_MEMq 3DNOW AMDONLY +PI2FW 3DNOW 3DNOW PI2FW_MMXq_MMXq 3DNOW AMDONLY +PINSRB SSE4 SSE PINSRB_XMMdq_GPR32d_IMMb SSE4 INVALID +PINSRB SSE4 SSE PINSRB_XMMdq_MEMb_IMMb SSE4 INVALID +PINSRD SSE4 SSE PINSRD_XMMdq_GPR32d_IMMb SSE4 INVALID +PINSRD SSE4 SSE PINSRD_XMMdq_MEMd_IMMb SSE4 INVALID +PINSRQ SSE4 SSE PINSRQ_XMMdq_GPR64q_IMMb SSE4 INVALID +PINSRQ SSE4 SSE PINSRQ_XMMdq_MEMq_IMMb SSE4 INVALID +PINSRW MMX MMX PINSRW_MMXq_GPR32_IMMb PENTIUMMMX NOTSX +PINSRW MMX MMX PINSRW_MMXq_MEMw_IMMb PENTIUMMMX NOTSX +PINSRW SSE2 SSE PINSRW_XMMdq_GPR32_IMMb SSE2 INVALID +PINSRW SSE2 SSE PINSRW_XMMdq_MEMw_IMMb SSE2 INVALID +PMADDUBSW SSSE3 MMX PMADDUBSW_MMXq_MEMq SSSE3MMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDUBSW SSSE3 MMX PMADDUBSW_MMXq_MMXq SSSE3MMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDUBSW SSSE3 SSE PMADDUBSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +PMADDUBSW SSSE3 SSE PMADDUBSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +PMADDWD MMX MMX PMADDWD_MMXq_MEMq PENTIUMMMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDWD MMX MMX PMADDWD_MMXq_MMXq PENTIUMMMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDWD SSE2 SSE PMADDWD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMADDWD SSE2 SSE PMADDWD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMAXSB SSE4 SSE PMAXSB_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXSB SSE4 SSE PMAXSB_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMAXSD SSE4 SSE PMAXSD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXSD SSE4 SSE PMAXSD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMAXSW MMX MMX PMAXSW_MMXq_MEMq PENTIUMMMX NOTSX +PMAXSW MMX MMX PMAXSW_MMXq_MMXq PENTIUMMMX NOTSX +PMAXSW SSE2 SSE PMAXSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMAXSW SSE2 SSE PMAXSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMAXUB MMX MMX PMAXUB_MMXq_MEMq PENTIUMMMX NOTSX +PMAXUB MMX MMX PMAXUB_MMXq_MMXq PENTIUMMMX NOTSX +PMAXUB SSE2 SSE PMAXUB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMAXUB SSE2 SSE PMAXUB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMAXUD SSE4 SSE PMAXUD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXUD SSE4 SSE PMAXUD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMAXUW SSE4 SSE PMAXUW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXUW SSE4 SSE PMAXUW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINSB SSE4 SSE PMINSB_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINSB SSE4 SSE PMINSB_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINSD SSE4 SSE PMINSD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINSD SSE4 SSE PMINSD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINSW MMX MMX PMINSW_MMXq_MEMq PENTIUMMMX NOTSX +PMINSW MMX MMX PMINSW_MMXq_MMXq PENTIUMMMX NOTSX +PMINSW SSE2 SSE PMINSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMINSW SSE2 SSE PMINSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMINUB MMX MMX PMINUB_MMXq_MEMq PENTIUMMMX NOTSX +PMINUB MMX MMX PMINUB_MMXq_MMXq PENTIUMMMX NOTSX +PMINUB SSE2 SSE PMINUB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMINUB SSE2 SSE PMINUB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMINUD SSE4 SSE PMINUD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINUD SSE4 SSE PMINUD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINUW SSE4 SSE PMINUW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINUW SSE4 SSE PMINUW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMOVMSKB MMX MMX PMOVMSKB_GPR32_MMXq SSE NOTSX +PMOVMSKB SSE2 SSE PMOVMSKB_GPR32_XMMdq SSE2 INVALID +PMOVSXBD SSE4 SSE PMOVSXBD_XMMdq_MEMd SSE4 INVALID +PMOVSXBD SSE4 SSE PMOVSXBD_XMMdq_XMMd SSE4 INVALID +PMOVSXBQ SSE4 SSE PMOVSXBQ_XMMdq_MEMw SSE4 INVALID +PMOVSXBQ SSE4 SSE PMOVSXBQ_XMMdq_XMMw SSE4 INVALID +PMOVSXBW SSE4 SSE PMOVSXBW_XMMdq_MEMq SSE4 INVALID +PMOVSXBW SSE4 SSE PMOVSXBW_XMMdq_XMMq SSE4 INVALID +PMOVSXDQ SSE4 SSE PMOVSXDQ_XMMdq_MEMq SSE4 INVALID +PMOVSXDQ SSE4 SSE PMOVSXDQ_XMMdq_XMMq SSE4 INVALID +PMOVSXWD SSE4 SSE PMOVSXWD_XMMdq_MEMq SSE4 INVALID +PMOVSXWD SSE4 SSE PMOVSXWD_XMMdq_XMMq SSE4 INVALID +PMOVSXWQ SSE4 SSE PMOVSXWQ_XMMdq_MEMd SSE4 INVALID +PMOVSXWQ SSE4 SSE PMOVSXWQ_XMMdq_XMMd SSE4 INVALID +PMOVZXBD SSE4 SSE PMOVZXBD_XMMdq_MEMd SSE4 INVALID +PMOVZXBD SSE4 SSE PMOVZXBD_XMMdq_XMMd SSE4 INVALID +PMOVZXBQ SSE4 SSE PMOVZXBQ_XMMdq_MEMw SSE4 INVALID +PMOVZXBQ SSE4 SSE PMOVZXBQ_XMMdq_XMMw SSE4 INVALID +PMOVZXBW SSE4 SSE PMOVZXBW_XMMdq_MEMq SSE4 INVALID +PMOVZXBW SSE4 SSE PMOVZXBW_XMMdq_XMMq SSE4 INVALID +PMOVZXDQ SSE4 SSE PMOVZXDQ_XMMdq_MEMq SSE4 INVALID +PMOVZXDQ SSE4 SSE PMOVZXDQ_XMMdq_XMMq SSE4 INVALID +PMOVZXWD SSE4 SSE PMOVZXWD_XMMdq_MEMq SSE4 INVALID +PMOVZXWD SSE4 SSE PMOVZXWD_XMMdq_XMMq SSE4 INVALID +PMOVZXWQ SSE4 SSE PMOVZXWQ_XMMdq_MEMd SSE4 INVALID +PMOVZXWQ SSE4 SSE PMOVZXWQ_XMMdq_XMMd SSE4 INVALID +PMULDQ SSE4 SSE PMULDQ_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMULDQ SSE4 SSE PMULDQ_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMULHRSW SSSE3 MMX PMULHRSW_MMXq_MEMq SSSE3MMX NOTSX +PMULHRSW SSSE3 MMX PMULHRSW_MMXq_MMXq SSSE3MMX NOTSX +PMULHRSW SSSE3 SSE PMULHRSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PMULHRSW SSSE3 SSE PMULHRSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PMULHRW 3DNOW 3DNOW PMULHRW_MMXq_MEMq 3DNOW AMDONLY +PMULHRW 3DNOW 3DNOW PMULHRW_MMXq_MMXq 3DNOW AMDONLY +PMULHUW MMX MMX PMULHUW_MMXq_MEMq PENTIUMMMX NOTSX +PMULHUW MMX MMX PMULHUW_MMXq_MMXq PENTIUMMMX NOTSX +PMULHUW SSE2 SSE PMULHUW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULHUW SSE2 SSE PMULHUW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMULHW MMX MMX PMULHW_MMXq_MEMq PENTIUMMMX NOTSX +PMULHW MMX MMX PMULHW_MMXq_MMXq PENTIUMMMX NOTSX +PMULHW SSE2 SSE PMULHW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULHW SSE2 SSE PMULHW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMULLD SSE4 SSE PMULLD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMULLD SSE4 SSE PMULLD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMULLW MMX MMX PMULLW_MMXq_MEMq PENTIUMMMX NOTSX +PMULLW MMX MMX PMULLW_MMXq_MMXq PENTIUMMMX NOTSX +PMULLW SSE2 SSE PMULLW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULLW SSE2 SSE PMULLW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMULUDQ SSE2 MMX PMULUDQ_MMXq_MEMq SSE2MMX NOTSX +PMULUDQ SSE2 MMX PMULUDQ_MMXq_MMXq SSE2MMX NOTSX +PMULUDQ SSE2 SSE PMULUDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULUDQ SSE2 SSE PMULUDQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +POPA BASE POP POPA I186 FIXED_BASE0:STACKPOP0:SCALABLE +POPAD BASE POP POPAD I386 FIXED_BASE0:STACKPOP0:SCALABLE +POPCNT SSE4 SSE POPCNT_GPRv_GPRv POPCNT IGNORES_OSFXSR:SCALABLE +POPCNT SSE4 SSE POPCNT_GPRv_MEMv POPCNT IGNORES_OSFXSR:SCALABLE +POPF BASE POP POPF I86 NOTSX:FIXED_BASE0:STACKPOP0 +POPFD BASE POP POPFD I386 NOTSX:FIXED_BASE0:STACKPOP0 +POPFQ LONGMODE POP POPFQ LONGMODE NOTSX:FIXED_BASE0:STACKPOP0 +POP BASE POP POP_DS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_ES I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_FS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_GPRv_58 I86 FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_GPRv_8F I86 FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_GS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_MEMv I86 FIXED_BASE1:STACKPOP1:SCALABLE +POP BASE POP POP_SS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POR MMX LOGICAL POR_MMXq_MEMq PENTIUMMMX NOTSX +POR MMX LOGICAL POR_MMXq_MMXq PENTIUMMMX NOTSX +POR SSE2 LOGICAL POR_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +POR SSE2 LOGICAL POR_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PREFETCHNTA SSE PREFETCH PREFETCHNTA_MEMmprefetch SSE_PREFETCH PREFETCH:NONTEMPORAL +PREFETCHT0 SSE PREFETCH PREFETCHT0_MEMmprefetch SSE_PREFETCH PREFETCH +PREFETCHT1 SSE PREFETCH PREFETCHT1_MEMmprefetch SSE_PREFETCH PREFETCH +PREFETCHT2 SSE PREFETCH PREFETCHT2_MEMmprefetch SSE_PREFETCH PREFETCH +PREFETCHWT1 PREFETCHWT1 PREFETCHWT1 PREFETCHWT1_MEMu8 PREFETCHWT1 PREFETCH +PREFETCHW 3DNOW_PREFETCH PREFETCH PREFETCHW_0F0Dr1 PREFETCH_NOP PREFETCH +PREFETCHW 3DNOW_PREFETCH PREFETCH PREFETCHW_0F0Dr3 PREFETCH_NOP PREFETCH +PREFETCH_EXCLUSIVE 3DNOW_PREFETCH PREFETCH PREFETCH_EXCLUSIVE_MEMmprefetch PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr4 PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr5 PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr6 PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr7 PREFETCH_NOP PREFETCH +PSADBW MMX MMX PSADBW_MMXq_MEMq PENTIUMMMX NOTSX +PSADBW MMX MMX PSADBW_MMXq_MMXq PENTIUMMMX NOTSX +PSADBW SSE2 SSE PSADBW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSADBW SSE2 SSE PSADBW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSHUFB SSSE3 MMX PSHUFB_MMXq_MEMq SSSE3MMX NOTSX +PSHUFB SSSE3 MMX PSHUFB_MMXq_MMXq SSSE3MMX NOTSX +PSHUFB SSSE3 SSE PSHUFB_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSHUFB SSSE3 SSE PSHUFB_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSHUFD SSE2 SSE PSHUFD_XMMdq_MEMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFD SSE2 SSE PSHUFD_XMMdq_XMMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFHW SSE2 SSE PSHUFHW_XMMdq_MEMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFHW SSE2 SSE PSHUFHW_XMMdq_XMMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFLW SSE2 SSE PSHUFLW_XMMdq_MEMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFLW SSE2 SSE PSHUFLW_XMMdq_XMMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFW MMX MMX PSHUFW_MMXq_MEMq_IMMb PENTIUMMMX NOTSX +PSHUFW MMX MMX PSHUFW_MMXq_MMXq_IMMb PENTIUMMMX NOTSX +PSIGNB SSSE3 MMX PSIGNB_MMXq_MEMq SSSE3MMX NOTSX +PSIGNB SSSE3 MMX PSIGNB_MMXq_MMXq SSSE3MMX NOTSX +PSIGNB SSSE3 SSE PSIGNB_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSIGNB SSSE3 SSE PSIGNB_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSIGND SSSE3 MMX PSIGND_MMXq_MEMq SSSE3MMX NOTSX +PSIGND SSSE3 MMX PSIGND_MMXq_MMXq SSSE3MMX NOTSX +PSIGND SSSE3 SSE PSIGND_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSIGND SSSE3 SSE PSIGND_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSIGNW SSSE3 MMX PSIGNW_MMXq_MEMq SSSE3MMX NOTSX +PSIGNW SSSE3 MMX PSIGNW_MMXq_MMXq SSSE3MMX NOTSX +PSIGNW SSSE3 SSE PSIGNW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSIGNW SSSE3 SSE PSIGNW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSLLDQ SSE2 SSE PSLLDQ_XMMdq_IMMb SSE2 INVALID +PSLLD MMX MMX PSLLD_MMXq_IMMb PENTIUMMMX NOTSX +PSLLD MMX MMX PSLLD_MMXq_MEMq PENTIUMMMX NOTSX +PSLLD MMX MMX PSLLD_MMXq_MMXq PENTIUMMMX NOTSX +PSLLD SSE2 SSE PSLLD_XMMdq_IMMb SSE2 INVALID +PSLLD SSE2 SSE PSLLD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSLLD SSE2 SSE PSLLD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSLLQ MMX MMX PSLLQ_MMXq_IMMb PENTIUMMMX NOTSX +PSLLQ MMX MMX PSLLQ_MMXq_MEMq PENTIUMMMX NOTSX +PSLLQ MMX MMX PSLLQ_MMXq_MMXq PENTIUMMMX NOTSX +PSLLQ SSE2 SSE PSLLQ_XMMdq_IMMb SSE2 INVALID +PSLLQ SSE2 SSE PSLLQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSLLQ SSE2 SSE PSLLQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSLLW MMX MMX PSLLW_MMXq_IMMb PENTIUMMMX NOTSX +PSLLW MMX MMX PSLLW_MMXq_MEMq PENTIUMMMX NOTSX +PSLLW MMX MMX PSLLW_MMXq_MMXq PENTIUMMMX NOTSX +PSLLW SSE2 SSE PSLLW_XMMdq_IMMb SSE2 INVALID +PSLLW SSE2 SSE PSLLW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSLLW SSE2 SSE PSLLW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSMASH SNP SYSTEM PSMASH_RAX SNP AMDONLY +PSRAD MMX MMX PSRAD_MMXq_IMMb PENTIUMMMX NOTSX +PSRAD MMX MMX PSRAD_MMXq_MEMq PENTIUMMMX NOTSX +PSRAD MMX MMX PSRAD_MMXq_MMXq PENTIUMMMX NOTSX +PSRAD SSE2 SSE PSRAD_XMMdq_IMMb SSE2 INVALID +PSRAD SSE2 SSE PSRAD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRAD SSE2 SSE PSRAD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRAW MMX MMX PSRAW_MMXq_IMMb PENTIUMMMX NOTSX +PSRAW MMX MMX PSRAW_MMXq_MEMq PENTIUMMMX NOTSX +PSRAW MMX MMX PSRAW_MMXq_MMXq PENTIUMMMX NOTSX +PSRAW SSE2 SSE PSRAW_XMMdq_IMMb SSE2 INVALID +PSRAW SSE2 SSE PSRAW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRAW SSE2 SSE PSRAW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRLDQ SSE2 SSE PSRLDQ_XMMdq_IMMb SSE2 INVALID +PSRLD MMX MMX PSRLD_MMXq_IMMb PENTIUMMMX NOTSX +PSRLD MMX MMX PSRLD_MMXq_MEMq PENTIUMMMX NOTSX +PSRLD MMX MMX PSRLD_MMXq_MMXq PENTIUMMMX NOTSX +PSRLD SSE2 SSE PSRLD_XMMdq_IMMb SSE2 INVALID +PSRLD SSE2 SSE PSRLD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRLD SSE2 SSE PSRLD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRLQ MMX MMX PSRLQ_MMXq_IMMb PENTIUMMMX NOTSX +PSRLQ MMX MMX PSRLQ_MMXq_MEMq PENTIUMMMX NOTSX +PSRLQ MMX MMX PSRLQ_MMXq_MMXq PENTIUMMMX NOTSX +PSRLQ SSE2 SSE PSRLQ_XMMdq_IMMb SSE2 INVALID +PSRLQ SSE2 SSE PSRLQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRLQ SSE2 SSE PSRLQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRLW MMX MMX PSRLW_MMXq_IMMb PENTIUMMMX NOTSX +PSRLW MMX MMX PSRLW_MMXq_MEMq PENTIUMMMX NOTSX +PSRLW MMX MMX PSRLW_MMXq_MMXq PENTIUMMMX NOTSX +PSRLW SSE2 SSE PSRLW_XMMdq_IMMb SSE2 INVALID +PSRLW SSE2 SSE PSRLW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRLW SSE2 SSE PSRLW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBB MMX MMX PSUBB_MMXq_MEMq PENTIUMMMX NOTSX +PSUBB MMX MMX PSUBB_MMXq_MMXq PENTIUMMMX NOTSX +PSUBB SSE2 SSE PSUBB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBB SSE2 SSE PSUBB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBD MMX MMX PSUBD_MMXq_MEMq PENTIUMMMX NOTSX +PSUBD MMX MMX PSUBD_MMXq_MMXq PENTIUMMMX NOTSX +PSUBD SSE2 SSE PSUBD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBD SSE2 SSE PSUBD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBQ SSE2 MMX PSUBQ_MMXq_MEMq SSE2MMX NOTSX +PSUBQ SSE2 MMX PSUBQ_MMXq_MMXq SSE2MMX NOTSX +PSUBQ SSE2 SSE PSUBQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBQ SSE2 SSE PSUBQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBSB MMX MMX PSUBSB_MMXq_MEMq PENTIUMMMX NOTSX +PSUBSB MMX MMX PSUBSB_MMXq_MMXq PENTIUMMMX NOTSX +PSUBSB SSE2 SSE PSUBSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBSB SSE2 SSE PSUBSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBSW MMX MMX PSUBSW_MMXq_MEMq PENTIUMMMX NOTSX +PSUBSW MMX MMX PSUBSW_MMXq_MMXq PENTIUMMMX NOTSX +PSUBSW SSE2 SSE PSUBSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBSW SSE2 SSE PSUBSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSB MMX MMX PSUBUSB_MMXq_MEMq PENTIUMMMX NOTSX +PSUBUSB MMX MMX PSUBUSB_MMXq_MMXq PENTIUMMMX NOTSX +PSUBUSB SSE2 SSE PSUBUSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSB SSE2 SSE PSUBUSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSW MMX MMX PSUBUSW_MMXq_MEMq PENTIUMMMX NOTSX +PSUBUSW MMX MMX PSUBUSW_MMXq_MMXq PENTIUMMMX NOTSX +PSUBUSW SSE2 SSE PSUBUSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSW SSE2 SSE PSUBUSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBW MMX MMX PSUBW_MMXq_MEMq PENTIUMMMX NOTSX +PSUBW MMX MMX PSUBW_MMXq_MMXq PENTIUMMMX NOTSX +PSUBW SSE2 SSE PSUBW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBW SSE2 SSE PSUBW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSWAPD 3DNOW 3DNOW PSWAPD_MMXq_MEMq 3DNOW AMDONLY +PSWAPD 3DNOW 3DNOW PSWAPD_MMXq_MMXq 3DNOW AMDONLY +PTEST SSE4 LOGICAL PTEST_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PTEST SSE4 LOGICAL PTEST_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PTWRITE PTWRITE PTWRITE PTWRITE_GPRy PTWRITE SCALABLE +PTWRITE PTWRITE PTWRITE PTWRITE_MEMy PTWRITE SCALABLE +PUNPCKHBW MMX MMX PUNPCKHBW_MMXq_MEMq PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHBW MMX MMX PUNPCKHBW_MMXq_MMXd PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHBW SSE2 SSE PUNPCKHBW_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHBW SSE2 SSE PUNPCKHBW_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHDQ MMX MMX PUNPCKHDQ_MMXq_MEMq PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHDQ MMX MMX PUNPCKHDQ_MMXq_MMXd PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHDQ SSE2 SSE PUNPCKHDQ_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHDQ SSE2 SSE PUNPCKHDQ_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHQDQ SSE2 SSE PUNPCKHQDQ_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHQDQ SSE2 SSE PUNPCKHQDQ_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHWD MMX MMX PUNPCKHWD_MMXq_MEMq PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHWD MMX MMX PUNPCKHWD_MMXq_MMXd PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHWD SSE2 SSE PUNPCKHWD_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHWD SSE2 SSE PUNPCKHWD_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKLBW MMX MMX PUNPCKLBW_MMXq_MEMd PENTIUMMMX NOTSX +PUNPCKLBW MMX MMX PUNPCKLBW_MMXq_MMXd PENTIUMMMX NOTSX +PUNPCKLBW SSE2 SSE PUNPCKLBW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLBW SSE2 SSE PUNPCKLBW_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUNPCKLDQ MMX MMX PUNPCKLDQ_MMXq_MEMd PENTIUMMMX NOTSX +PUNPCKLDQ MMX MMX PUNPCKLDQ_MMXq_MMXd PENTIUMMMX NOTSX +PUNPCKLDQ SSE2 SSE PUNPCKLDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLDQ SSE2 SSE PUNPCKLDQ_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUNPCKLQDQ SSE2 SSE PUNPCKLQDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLQDQ SSE2 SSE PUNPCKLQDQ_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUNPCKLWD MMX MMX PUNPCKLWD_MMXq_MEMd PENTIUMMMX NOTSX +PUNPCKLWD MMX MMX PUNPCKLWD_MMXq_MMXd PENTIUMMMX NOTSX +PUNPCKLWD SSE2 SSE PUNPCKLWD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLWD SSE2 SSE PUNPCKLWD_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUSHA BASE PUSH PUSHA I186 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSHAD BASE PUSH PUSHAD I386 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSHF BASE PUSH PUSHF I86 FIXED_BASE0:STACKPUSH0 +PUSHFD BASE PUSH PUSHFD I386 FIXED_BASE0:STACKPUSH0 +PUSHFQ LONGMODE PUSH PUSHFQ LONGMODE FIXED_BASE0:STACKPUSH0 +PUSH BASE PUSH PUSH_CS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_DS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_ES I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_FS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_GPRv_50 I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_GPRv_FFr6 I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_GS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_IMMb I186 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_IMMz I186 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_MEMv I86 FIXED_BASE1:STACKPUSH1:SCALABLE +PUSH BASE PUSH PUSH_SS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PVALIDATE SNP SYSTEM PVALIDATE_RAX_ECX_EDX SNP AMDONLY +PXOR MMX LOGICAL PXOR_MMXq_MEMq PENTIUMMMX NOTSX +PXOR MMX LOGICAL PXOR_MMXq_MMXq PENTIUMMMX NOTSX +PXOR SSE2 LOGICAL PXOR_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PXOR SSE2 LOGICAL PXOR_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +RCL BASE ROTATE RCL_GPR8_CL I86 BYTEOP +RCL BASE ROTATE RCL_GPR8_IMMb I186 BYTEOP +RCL BASE ROTATE RCL_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +RCL BASE ROTATE RCL_GPRv_CL I86 SCALABLE +RCL BASE ROTATE RCL_GPRv_IMMb I186 SCALABLE +RCL BASE ROTATE RCL_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +RCL BASE ROTATE RCL_MEMb_CL I86 BYTEOP +RCL BASE ROTATE RCL_MEMb_IMMb I186 BYTEOP +RCL BASE ROTATE RCL_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +RCL BASE ROTATE RCL_MEMv_CL I86 SCALABLE +RCL BASE ROTATE RCL_MEMv_IMMb I186 SCALABLE +RCL BASE ROTATE RCL_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +RCPPS SSE SSE RCPPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT +RCPPS SSE SSE RCPPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT +RCPSS SSE SSE RCPSS_XMMss_MEMss SSE SIMD_SCALAR +RCPSS SSE SSE RCPSS_XMMss_XMMss SSE SIMD_SCALAR +RCR BASE ROTATE RCR_GPR8_CL I86 BYTEOP +RCR BASE ROTATE RCR_GPR8_IMMb I186 BYTEOP +RCR BASE ROTATE RCR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +RCR BASE ROTATE RCR_GPRv_CL I86 SCALABLE +RCR BASE ROTATE RCR_GPRv_IMMb I186 SCALABLE +RCR BASE ROTATE RCR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +RCR BASE ROTATE RCR_MEMb_CL I86 BYTEOP +RCR BASE ROTATE RCR_MEMb_IMMb I186 BYTEOP +RCR BASE ROTATE RCR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +RCR BASE ROTATE RCR_MEMv_CL I86 SCALABLE +RCR BASE ROTATE RCR_MEMv_IMMb I186 SCALABLE +RCR BASE ROTATE RCR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +RDFSBASE RDWRFSGS RDWRFSGS RDFSBASE_GPRy RDWRFSGS SCALABLE +RDGSBASE RDWRFSGS RDWRFSGS RDGSBASE_GPRy RDWRFSGS SCALABLE +RDMSR BASE SYSTEM RDMSR PENTIUMREAL RING0:NOTSX +RDPID RDPID RDPID RDPID_GPR32u32 RDPID INVALID +RDPID RDPID RDPID RDPID_GPR64u64 RDPID INVALID +RDPKRU PKU PKU RDPKRU PKU INVALID +RDPMC BASE SYSTEM RDPMC RDPMC INVALID +RDPRU RDPRU RDPRU RDPRU RDPRU AMDONLY +RDRAND RDRAND RDRAND RDRAND_GPRv RDRAND SCALABLE +RDSEED RDSEED RDSEED RDSEED_GPRv RDSEED SCALABLE +RDSSPD CET CET RDSSPD_GPR32u32 CET INVALID +RDSSPQ CET CET RDSSPQ_GPR64u64 CET INVALID +RDTSC BASE SYSTEM RDTSC PENTIUMREAL INVALID +RDTSCP RDTSCP SYSTEM RDTSCP RDTSCP INVALID +REPE_CMPSB BASE STRINGOP REPE_CMPSB I86 REP:FIXED_BASE0:FIXED_BASE1:BYTEOP +REPE_CMPSD BASE STRINGOP REPE_CMPSD I386 REP:FIXED_BASE0:FIXED_BASE1 +REPE_CMPSQ LONGMODE STRINGOP REPE_CMPSQ LONGMODE REP:FIXED_BASE0:FIXED_BASE1 +REPE_CMPSW BASE STRINGOP REPE_CMPSW I86 REP:FIXED_BASE0:FIXED_BASE1 +REPE_SCASB BASE STRINGOP REPE_SCASB I86 REP:FIXED_BASE0:BYTEOP +REPE_SCASD BASE STRINGOP REPE_SCASD I386 REP:FIXED_BASE0 +REPE_SCASQ LONGMODE STRINGOP REPE_SCASQ LONGMODE REP:FIXED_BASE0 +REPE_SCASW BASE STRINGOP REPE_SCASW I86 REP:FIXED_BASE0 +REPNE_CMPSB BASE STRINGOP REPNE_CMPSB I86 REP:FIXED_BASE0:FIXED_BASE1:BYTEOP +REPNE_CMPSD BASE STRINGOP REPNE_CMPSD I386 REP:FIXED_BASE0:FIXED_BASE1 +REPNE_CMPSQ LONGMODE STRINGOP REPNE_CMPSQ LONGMODE REP:FIXED_BASE0:FIXED_BASE1 +REPNE_CMPSW BASE STRINGOP REPNE_CMPSW I86 REP:FIXED_BASE0:FIXED_BASE1 +REPNE_SCASB BASE STRINGOP REPNE_SCASB I86 REP:FIXED_BASE0:BYTEOP +REPNE_SCASD BASE STRINGOP REPNE_SCASD I386 REP:FIXED_BASE0 +REPNE_SCASQ LONGMODE STRINGOP REPNE_SCASQ LONGMODE REP:FIXED_BASE0 +REPNE_SCASW BASE STRINGOP REPNE_SCASW I86 REP:FIXED_BASE0 +REP_INSB BASE IOSTRINGOP REP_INSB I186 REP:FIXED_BASE0:NOTSX:BYTEOP +REP_INSD BASE IOSTRINGOP REP_INSD I386 REP:FIXED_BASE0:NOTSX +REP_INSW BASE IOSTRINGOP REP_INSW I186 REP:FIXED_BASE0:NOTSX +REP_LODSB BASE STRINGOP REP_LODSB I86 REP:FIXED_BASE0:BYTEOP +REP_LODSD BASE STRINGOP REP_LODSD I386 REP:FIXED_BASE0 +REP_LODSQ LONGMODE STRINGOP REP_LODSQ LONGMODE REP:FIXED_BASE0 +REP_LODSW BASE STRINGOP REP_LODSW I86 REP:FIXED_BASE0 +REP_MONTMUL VIA_PADLOCK_MONTMUL VIA_PADLOCK REP_MONTMUL VIA_PADLOCK_MONTMUL REP:FIXED_BASE0 +REP_MOVSB BASE STRINGOP REP_MOVSB I86 REP:FIXED_BASE0:FIXED_BASE1:BYTEOP +REP_MOVSD BASE STRINGOP REP_MOVSD I386 REP:FIXED_BASE0:FIXED_BASE1 +REP_MOVSQ LONGMODE STRINGOP REP_MOVSQ LONGMODE REP:FIXED_BASE0:FIXED_BASE1 +REP_MOVSW BASE STRINGOP REP_MOVSW I86 REP:FIXED_BASE0:FIXED_BASE1 +REP_OUTSB BASE IOSTRINGOP REP_OUTSB I186 REP:FIXED_BASE0:NOTSX:BYTEOP +REP_OUTSD BASE IOSTRINGOP REP_OUTSD I386 REP:FIXED_BASE0:NOTSX +REP_OUTSW BASE IOSTRINGOP REP_OUTSW I186 REP:FIXED_BASE0:NOTSX +REP_STOSB BASE STRINGOP REP_STOSB I86 REP:FIXED_BASE0:BYTEOP +REP_STOSD BASE STRINGOP REP_STOSD I386 REP:FIXED_BASE0 +REP_STOSQ LONGMODE STRINGOP REP_STOSQ LONGMODE REP:FIXED_BASE0 +REP_STOSW BASE STRINGOP REP_STOSW I86 REP:FIXED_BASE0 +REP_XCRYPTCBC VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTCBC VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTCFB VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTCFB VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTCTR VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTCTR VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTECB VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTECB VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTOFB VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTOFB VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XSHA1 VIA_PADLOCK_SHA VIA_PADLOCK REP_XSHA1 VIA_PADLOCK_SHA REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XSHA256 VIA_PADLOCK_SHA VIA_PADLOCK REP_XSHA256 VIA_PADLOCK_SHA REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XSTORE VIA_PADLOCK_RNG VIA_PADLOCK REP_XSTORE VIA_PADLOCK_RNG REP:FIXED_BASE0:BYTEOP:SCALABLE +RET_FAR BASE RET RET_FAR I86 FAR_XFER:NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +RET_FAR BASE RET RET_FAR_IMMw I86 FAR_XFER:NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +RET_NEAR BASE RET RET_NEAR I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPOP0:SCALABLE +RET_NEAR BASE RET RET_NEAR_IMMw I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPOP0:SCALABLE +RMPADJUST SNP SYSTEM RMPADJUST_RAX_RCX_RDX SNP AMDONLY +RMPUPDATE SNP SYSTEM RMPUPDATE_RAX_RCX SNP AMDONLY +ROL BASE ROTATE ROL_GPR8_CL I86 BYTEOP +ROL BASE ROTATE ROL_GPR8_IMMb I186 BYTEOP +ROL BASE ROTATE ROL_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +ROL BASE ROTATE ROL_GPRv_CL I86 SCALABLE +ROL BASE ROTATE ROL_GPRv_IMMb I186 SCALABLE +ROL BASE ROTATE ROL_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +ROL BASE ROTATE ROL_MEMb_CL I86 BYTEOP +ROL BASE ROTATE ROL_MEMb_IMMb I186 BYTEOP +ROL BASE ROTATE ROL_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +ROL BASE ROTATE ROL_MEMv_CL I86 SCALABLE +ROL BASE ROTATE ROL_MEMv_IMMb I186 SCALABLE +ROL BASE ROTATE ROL_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +RORX BMI2 BMI2 RORX_VGPR32d_MEMd_IMMb BMI2 INVALID +RORX BMI2 BMI2 RORX_VGPR32d_VGPR32d_IMMb BMI2 INVALID +RORX BMI2 BMI2 RORX_VGPR64q_MEMq_IMMb BMI2 INVALID +RORX BMI2 BMI2 RORX_VGPR64q_VGPR64q_IMMb BMI2 INVALID +ROR BASE ROTATE ROR_GPR8_CL I86 BYTEOP +ROR BASE ROTATE ROR_GPR8_IMMb I186 BYTEOP +ROR BASE ROTATE ROR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +ROR BASE ROTATE ROR_GPRv_CL I86 SCALABLE +ROR BASE ROTATE ROR_GPRv_IMMb I186 SCALABLE +ROR BASE ROTATE ROR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +ROR BASE ROTATE ROR_MEMb_CL I86 BYTEOP +ROR BASE ROTATE ROR_MEMb_IMMb I186 BYTEOP +ROR BASE ROTATE ROR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +ROR BASE ROTATE ROR_MEMv_CL I86 SCALABLE +ROR BASE ROTATE ROR_MEMv_IMMb I186 SCALABLE +ROR BASE ROTATE ROR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +ROUNDPD SSE4 SSE ROUNDPD_XMMpd_MEMpd_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDPD SSE4 SSE ROUNDPD_XMMpd_XMMpd_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDPS SSE4 SSE ROUNDPS_XMMps_MEMps_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDPS SSE4 SSE ROUNDPS_XMMps_XMMps_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDSD SSE4 SSE ROUNDSD_XMMq_MEMq_IMMb SSE4 SIMD_SCALAR:MXCSR +ROUNDSD SSE4 SSE ROUNDSD_XMMq_XMMq_IMMb SSE4 SIMD_SCALAR:MXCSR +ROUNDSS SSE4 SSE ROUNDSS_XMMd_MEMd_IMMb SSE4 SIMD_SCALAR:MXCSR +ROUNDSS SSE4 SSE ROUNDSS_XMMd_XMMd_IMMb SSE4 SIMD_SCALAR:MXCSR +RSM BASE SYSRET RSM I486 NOTSX +RSQRTPS SSE SSE RSQRTPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT +RSQRTPS SSE SSE RSQRTPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT +RSQRTSS SSE SSE RSQRTSS_XMMss_MEMss SSE SIMD_SCALAR +RSQRTSS SSE SSE RSQRTSS_XMMss_XMMss SSE SIMD_SCALAR +RSTORSSP CET CET RSTORSSP_MEMu64 CET INVALID +SAHF BASE FLAGOP SAHF LAHF INVALID +SALC BASE FLAGOP SALC I86 INVALID +SARX BMI2 BMI2 SARX_VGPR32d_MEMd_VGPR32d BMI2 INVALID +SARX BMI2 BMI2 SARX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +SARX BMI2 BMI2 SARX_VGPR64q_MEMq_VGPR64q BMI2 INVALID +SARX BMI2 BMI2 SARX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +SAR BASE SHIFT SAR_GPR8_CL I86 BYTEOP +SAR BASE SHIFT SAR_GPR8_IMMb I186 BYTEOP +SAR BASE SHIFT SAR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +SAR BASE SHIFT SAR_GPRv_CL I86 SCALABLE +SAR BASE SHIFT SAR_GPRv_IMMb I186 SCALABLE +SAR BASE SHIFT SAR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +SAR BASE SHIFT SAR_MEMb_CL I86 BYTEOP +SAR BASE SHIFT SAR_MEMb_IMMb I186 BYTEOP +SAR BASE SHIFT SAR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +SAR BASE SHIFT SAR_MEMv_CL I86 SCALABLE +SAR BASE SHIFT SAR_MEMv_IMMb I186 SCALABLE +SAR BASE SHIFT SAR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +SAVEPREVSSP CET CET SAVEPREVSSP CET INVALID +SBB BASE BINARY SBB_AL_IMMb I86 BYTEOP +SBB BASE BINARY SBB_GPR8_GPR8_18 I86 BYTEOP +SBB BASE BINARY SBB_GPR8_GPR8_1A I86 BYTEOP +SBB BASE BINARY SBB_GPR8_IMMb_80r3 I86 BYTEOP +SBB BASE BINARY SBB_GPR8_IMMb_82r3 I86 BYTEOP +SBB BASE BINARY SBB_GPR8_MEMb I86 BYTEOP +SBB BASE BINARY SBB_GPRv_GPRv_19 I86 SCALABLE +SBB BASE BINARY SBB_GPRv_GPRv_1B I86 SCALABLE +SBB BASE BINARY SBB_GPRv_IMMb I86 SCALABLE +SBB BASE BINARY SBB_GPRv_IMMz I86 SCALABLE +SBB BASE BINARY SBB_GPRv_MEMv I86 SCALABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMb_IMMb_80r3 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMb_IMMb_82r3 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SBB BASE BINARY SBB_MEMb_GPR8 I86 BYTEOP:LOCKABLE +SBB BASE BINARY SBB_MEMb_IMMb_80r3 I86 BYTEOP:LOCKABLE +SBB BASE BINARY SBB_MEMb_IMMb_82r3 I86 BYTEOP:LOCKABLE +SBB BASE BINARY SBB_MEMv_GPRv I86 LOCKABLE:SCALABLE +SBB BASE BINARY SBB_MEMv_IMMb I86 LOCKABLE:SCALABLE +SBB BASE BINARY SBB_MEMv_IMMz I86 LOCKABLE:SCALABLE +SBB BASE BINARY SBB_OrAX_IMMz I86 SCALABLE +SCASB BASE STRINGOP SCASB I86 FIXED_BASE0:BYTEOP +SCASD BASE STRINGOP SCASD I386 FIXED_BASE0 +SCASQ LONGMODE STRINGOP SCASQ LONGMODE FIXED_BASE0 +SCASW BASE STRINGOP SCASW I86 FIXED_BASE0 +SEAMCALL TDX LEGACY SEAMCALL TDX NOTSX +SEAMOPS TDX LEGACY SEAMOPS TDX NOTSX +SEAMRET TDX LEGACY SEAMRET TDX NOTSX +SENDUIPI UINTR UINTR SENDUIPI_GPR32u32 UINTR INVALID +SERIALIZE SERIALIZE SERIALIZE SERIALIZE SERIALIZE INVALID +SETBE BASE SETCC SETBE_GPR8 I386 BYTEOP +SETBE BASE SETCC SETBE_MEMb I386 BYTEOP +SETB BASE SETCC SETB_GPR8 I386 BYTEOP +SETB BASE SETCC SETB_MEMb I386 BYTEOP +SETLE BASE SETCC SETLE_GPR8 I386 BYTEOP +SETLE BASE SETCC SETLE_MEMb I386 BYTEOP +SETL BASE SETCC SETL_GPR8 I386 BYTEOP +SETL BASE SETCC SETL_MEMb I386 BYTEOP +SETNBE BASE SETCC SETNBE_GPR8 I386 BYTEOP +SETNBE BASE SETCC SETNBE_MEMb I386 BYTEOP +SETNB BASE SETCC SETNB_GPR8 I386 BYTEOP +SETNB BASE SETCC SETNB_MEMb I386 BYTEOP +SETNLE BASE SETCC SETNLE_GPR8 I386 BYTEOP +SETNLE BASE SETCC SETNLE_MEMb I386 BYTEOP +SETNL BASE SETCC SETNL_GPR8 I386 BYTEOP +SETNL BASE SETCC SETNL_MEMb I386 BYTEOP +SETNO BASE SETCC SETNO_GPR8 I386 BYTEOP +SETNO BASE SETCC SETNO_MEMb I386 BYTEOP +SETNP BASE SETCC SETNP_GPR8 I386 BYTEOP +SETNP BASE SETCC SETNP_MEMb I386 BYTEOP +SETNS BASE SETCC SETNS_GPR8 I386 BYTEOP +SETNS BASE SETCC SETNS_MEMb I386 BYTEOP +SETNZ BASE SETCC SETNZ_GPR8 I386 BYTEOP +SETNZ BASE SETCC SETNZ_MEMb I386 BYTEOP +SETO BASE SETCC SETO_GPR8 I386 BYTEOP +SETO BASE SETCC SETO_MEMb I386 BYTEOP +SETP BASE SETCC SETP_GPR8 I386 BYTEOP +SETP BASE SETCC SETP_MEMb I386 BYTEOP +SETSSBSY CET CET SETSSBSY CET INVALID +SETS BASE SETCC SETS_GPR8 I386 BYTEOP +SETS BASE SETCC SETS_MEMb I386 BYTEOP +SETZ BASE SETCC SETZ_GPR8 I386 BYTEOP +SETZ BASE SETCC SETZ_MEMb I386 BYTEOP +SFENCE SSE MISC SFENCE SSE IGNORES_OSFXSR +SGDT BASE SYSTEM SGDT_MEMs I286REAL NOTSX:SCALABLE +SGDT BASE SYSTEM SGDT_MEMs64 I286REAL NOTSX +SHA1MSG1 SHA SHA SHA1MSG1_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA1MSG1 SHA SHA SHA1MSG1_XMMi32_XMMi32_SHA SHA INVALID +SHA1MSG2 SHA SHA SHA1MSG2_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA1MSG2 SHA SHA SHA1MSG2_XMMi32_XMMi32_SHA SHA INVALID +SHA1NEXTE SHA SHA SHA1NEXTE_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA1NEXTE SHA SHA SHA1NEXTE_XMMi32_XMMi32_SHA SHA INVALID +SHA1RNDS4 SHA SHA SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA SHA REQUIRES_ALIGNMENT +SHA1RNDS4 SHA SHA SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA SHA INVALID +SHA256MSG1 SHA SHA SHA256MSG1_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA256MSG1 SHA SHA SHA256MSG1_XMMi32_XMMi32_SHA SHA INVALID +SHA256MSG2 SHA SHA SHA256MSG2_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA256MSG2 SHA SHA SHA256MSG2_XMMi32_XMMi32_SHA SHA INVALID +SHA256RNDS2 SHA SHA SHA256RNDS2_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA256RNDS2 SHA SHA SHA256RNDS2_XMMi32_XMMi32_SHA SHA INVALID +SHLD BASE SHIFT SHLD_GPRv_GPRv_CL I386 SCALABLE +SHLD BASE SHIFT SHLD_GPRv_GPRv_IMMb I386 SCALABLE +SHLD BASE SHIFT SHLD_MEMv_GPRv_CL I386 SCALABLE +SHLD BASE SHIFT SHLD_MEMv_GPRv_IMMb I386 SCALABLE +SHLX BMI2 BMI2 SHLX_VGPR32d_MEMd_VGPR32d BMI2 INVALID +SHLX BMI2 BMI2 SHLX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +SHLX BMI2 BMI2 SHLX_VGPR64q_MEMq_VGPR64q BMI2 INVALID +SHLX BMI2 BMI2 SHLX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +SHL BASE SHIFT SHL_GPR8_CL_D2r4 I86 BYTEOP +SHL BASE SHIFT SHL_GPR8_CL_D2r6 I86 BYTEOP +SHL BASE SHIFT SHL_GPR8_IMMb_C0r4 I186 BYTEOP +SHL BASE SHIFT SHL_GPR8_IMMb_C0r6 I186 BYTEOP +SHL BASE SHIFT SHL_GPR8_ONE_D0r4 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_GPR8_ONE_D0r6 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_GPRv_CL_D3r4 I86 SCALABLE +SHL BASE SHIFT SHL_GPRv_CL_D3r6 I86 SCALABLE +SHL BASE SHIFT SHL_GPRv_IMMb_C1r4 I186 SCALABLE +SHL BASE SHIFT SHL_GPRv_IMMb_C1r6 I186 SCALABLE +SHL BASE SHIFT SHL_GPRv_ONE_D1r4 I86 IMPLICIT_ONE:SCALABLE +SHL BASE SHIFT SHL_GPRv_ONE_D1r6 I86 IMPLICIT_ONE:SCALABLE +SHL BASE SHIFT SHL_MEMb_CL_D2r4 I86 BYTEOP +SHL BASE SHIFT SHL_MEMb_CL_D2r6 I86 BYTEOP +SHL BASE SHIFT SHL_MEMb_IMMb_C0r4 I186 BYTEOP +SHL BASE SHIFT SHL_MEMb_IMMb_C0r6 I186 BYTEOP +SHL BASE SHIFT SHL_MEMb_ONE_D0r4 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_MEMb_ONE_D0r6 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_MEMv_CL_D3r4 I86 SCALABLE +SHL BASE SHIFT SHL_MEMv_CL_D3r6 I86 SCALABLE +SHL BASE SHIFT SHL_MEMv_IMMb_C1r4 I186 SCALABLE +SHL BASE SHIFT SHL_MEMv_IMMb_C1r6 I186 SCALABLE +SHL BASE SHIFT SHL_MEMv_ONE_D1r4 I86 IMPLICIT_ONE:SCALABLE +SHL BASE SHIFT SHL_MEMv_ONE_D1r6 I86 IMPLICIT_ONE:SCALABLE +SHRD BASE SHIFT SHRD_GPRv_GPRv_CL I386 SCALABLE +SHRD BASE SHIFT SHRD_GPRv_GPRv_IMMb I386 SCALABLE +SHRD BASE SHIFT SHRD_MEMv_GPRv_CL I386 SCALABLE +SHRD BASE SHIFT SHRD_MEMv_GPRv_IMMb I386 SCALABLE +SHRX BMI2 BMI2 SHRX_VGPR32d_MEMd_VGPR32d BMI2 INVALID +SHRX BMI2 BMI2 SHRX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +SHRX BMI2 BMI2 SHRX_VGPR64q_MEMq_VGPR64q BMI2 INVALID +SHRX BMI2 BMI2 SHRX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +SHR BASE SHIFT SHR_GPR8_CL I86 BYTEOP +SHR BASE SHIFT SHR_GPR8_IMMb I186 BYTEOP +SHR BASE SHIFT SHR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +SHR BASE SHIFT SHR_GPRv_CL I86 SCALABLE +SHR BASE SHIFT SHR_GPRv_IMMb I186 SCALABLE +SHR BASE SHIFT SHR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +SHR BASE SHIFT SHR_MEMb_CL I86 BYTEOP +SHR BASE SHIFT SHR_MEMb_IMMb I186 BYTEOP +SHR BASE SHIFT SHR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +SHR BASE SHIFT SHR_MEMv_CL I86 SCALABLE +SHR BASE SHIFT SHR_MEMv_IMMb I186 SCALABLE +SHR BASE SHIFT SHR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +SHUFPD SSE2 SSE SHUFPD_XMMpd_MEMpd_IMMb SSE2 REQUIRES_ALIGNMENT +SHUFPD SSE2 SSE SHUFPD_XMMpd_XMMpd_IMMb SSE2 REQUIRES_ALIGNMENT +SHUFPS SSE SSE SHUFPS_XMMps_MEMps_IMMb SSE REQUIRES_ALIGNMENT +SHUFPS SSE SSE SHUFPS_XMMps_XMMps_IMMb SSE REQUIRES_ALIGNMENT +SIDT BASE SYSTEM SIDT_MEMs I286REAL NOTSX:SCALABLE +SIDT BASE SYSTEM SIDT_MEMs64 I286REAL INVALID +SKINIT SVM SYSTEM SKINIT_EAX SVM PROTECTED_MODE:AMDONLY +SLDT BASE SYSTEM SLDT_GPRv I286PROTECTED PROTECTED_MODE:NOTSX:SCALABLE +SLDT BASE SYSTEM SLDT_MEMw I286PROTECTED PROTECTED_MODE:NOTSX +SLWPCB XOP XOP SLWPCB_VGPRyy LWP AMDONLY:SCALABLE +SMSW BASE SYSTEM SMSW_GPRv I286REAL SCALABLE +SMSW BASE SYSTEM SMSW_MEMw I286REAL INVALID +SQRTPD SSE2 SSE SQRTPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SQRTPD SSE2 SSE SQRTPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SQRTPS SSE SSE SQRTPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +SQRTPS SSE SSE SQRTPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +SQRTSD SSE2 SSE SQRTSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +SQRTSD SSE2 SSE SQRTSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +SQRTSS SSE SSE SQRTSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +SQRTSS SSE SSE SQRTSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +STAC SMAP SMAP STAC SMAP INVALID +STC BASE FLAGOP STC I86 INVALID +STD BASE FLAGOP STD I86 NOTSX_COND +STGI SVM SYSTEM STGI SVM PROTECTED_MODE:AMDONLY +STI BASE FLAGOP STI I86 NOTSX +STMXCSR SSE SSE STMXCSR_MEMd SSEMXCSR MXCSR_RD +STOSB BASE STRINGOP STOSB I86 FIXED_BASE0:BYTEOP +STOSD BASE STRINGOP STOSD I386 FIXED_BASE0 +STOSQ LONGMODE STRINGOP STOSQ LONGMODE FIXED_BASE0 +STOSW BASE STRINGOP STOSW I86 FIXED_BASE0 +STR BASE SYSTEM STR_GPRv I286PROTECTED PROTECTED_MODE:NOTSX:SCALABLE +STR BASE SYSTEM STR_MEMw I286PROTECTED PROTECTED_MODE:NOTSX +STTILECFG AMX_TILE AMX_TILE STTILECFG_MEM AMX_TILE NOTSX +STUI UINTR UINTR STUI UINTR INVALID +SUBPD SSE2 SSE SUBPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SUBPD SSE2 SSE SUBPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SUBPS SSE SSE SUBPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +SUBPS SSE SSE SUBPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +SUBSD SSE2 SSE SUBSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +SUBSD SSE2 SSE SUBSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +SUBSS SSE SSE SUBSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +SUBSS SSE SSE SUBSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +SUB BASE BINARY SUB_AL_IMMb I86 BYTEOP +SUB BASE BINARY SUB_GPR8_GPR8_28 I86 BYTEOP +SUB BASE BINARY SUB_GPR8_GPR8_2A I86 BYTEOP +SUB BASE BINARY SUB_GPR8_IMMb_80r5 I86 BYTEOP +SUB BASE BINARY SUB_GPR8_IMMb_82r5 I86 BYTEOP +SUB BASE BINARY SUB_GPR8_MEMb I86 BYTEOP +SUB BASE BINARY SUB_GPRv_GPRv_29 I86 SCALABLE +SUB BASE BINARY SUB_GPRv_GPRv_2B I86 SCALABLE +SUB BASE BINARY SUB_GPRv_IMMb I86 SCALABLE +SUB BASE BINARY SUB_GPRv_IMMz I86 SCALABLE +SUB BASE BINARY SUB_GPRv_MEMv I86 SCALABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMb_IMMb_80r5 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMb_IMMb_82r5 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SUB BASE BINARY SUB_MEMb_GPR8 I86 BYTEOP:LOCKABLE +SUB BASE BINARY SUB_MEMb_IMMb_80r5 I86 BYTEOP:LOCKABLE +SUB BASE BINARY SUB_MEMb_IMMb_82r5 I86 BYTEOP:LOCKABLE +SUB BASE BINARY SUB_MEMv_GPRv I86 LOCKABLE:SCALABLE +SUB BASE BINARY SUB_MEMv_IMMb I86 LOCKABLE:SCALABLE +SUB BASE BINARY SUB_MEMv_IMMz I86 LOCKABLE:SCALABLE +SUB BASE BINARY SUB_OrAX_IMMz I86 SCALABLE +SWAPGS LONGMODE SYSTEM SWAPGS LONGMODE RING0:NOTSX +SYSCALL LONGMODE SYSCALL SYSCALL LONGMODE NOTSX +SYSCALL_AMD BASE SYSCALL SYSCALL_AMD AMD AMDONLY +SYSENTER BASE SYSCALL SYSENTER PPRO PROTECTED_MODE:NOTSX +SYSEXIT BASE SYSRET SYSEXIT PPRO PROTECTED_MODE:RING0:NOTSX +SYSRET LONGMODE SYSRET SYSRET LONGMODE PROTECTED_MODE:RING0:NOTSX +SYSRET64 LONGMODE SYSRET SYSRET64 LONGMODE PROTECTED_MODE:RING0:NOTSX +SYSRET_AMD BASE SYSRET SYSRET_AMD AMD PROTECTED_MODE:RING0:AMDONLY +T1MSKC TBM TBM T1MSKC_VGPR32d_MEMd TBM AMDONLY +T1MSKC TBM TBM T1MSKC_VGPR32d_VGPR32d TBM AMDONLY +T1MSKC TBM TBM T1MSKC_VGPRyy_MEMy TBM AMDONLY:SCALABLE +T1MSKC TBM TBM T1MSKC_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +TDCALL TDX LEGACY TDCALL TDX NOTSX +TDPBF16PS AMX_BF16 AMX_TILE TDPBF16PS_TMMf32_TMMu32_TMMu32 AMX_BF16 NOTSX +TDPBSSD AMX_INT8 AMX_TILE TDPBSSD_TMMi32_TMMu32_TMMu32 AMX_INT8 NOTSX +TDPBSUD AMX_INT8 AMX_TILE TDPBSUD_TMMi32_TMMu32_TMMu32 AMX_INT8 NOTSX +TDPBUSD AMX_INT8 AMX_TILE TDPBUSD_TMMi32_TMMu32_TMMu32 AMX_INT8 NOTSX +TDPBUUD AMX_INT8 AMX_TILE TDPBUUD_TMMu32_TMMu32_TMMu32 AMX_INT8 NOTSX +TESTUI UINTR UINTR TESTUI UINTR INVALID +TEST BASE LOGICAL TEST_AL_IMMb I86 BYTEOP +TEST BASE LOGICAL TEST_GPR8_GPR8 I86 BYTEOP +TEST BASE LOGICAL TEST_GPR8_IMMb_F6r0 I86 BYTEOP +TEST BASE LOGICAL TEST_GPR8_IMMb_F6r1 I86 BYTEOP +TEST BASE LOGICAL TEST_GPRv_GPRv I86 SCALABLE +TEST BASE LOGICAL TEST_GPRv_IMMz_F7r0 I86 SCALABLE +TEST BASE LOGICAL TEST_GPRv_IMMz_F7r1 I86 SCALABLE +TEST BASE LOGICAL TEST_MEMb_GPR8 I86 BYTEOP +TEST BASE LOGICAL TEST_MEMb_IMMb_F6r0 I86 BYTEOP +TEST BASE LOGICAL TEST_MEMb_IMMb_F6r1 I86 BYTEOP +TEST BASE LOGICAL TEST_MEMv_GPRv I86 SCALABLE +TEST BASE LOGICAL TEST_MEMv_IMMz_F7r0 I86 SCALABLE +TEST BASE LOGICAL TEST_MEMv_IMMz_F7r1 I86 SCALABLE +TEST BASE LOGICAL TEST_OrAX_IMMz I86 SCALABLE +TILELOADDT1 AMX_TILE AMX_TILE TILELOADDT1_TMMu32_MEMu32 AMX_TILE NOTSX:SPECIAL_AGEN_REQUIRED +TILELOADD AMX_TILE AMX_TILE TILELOADD_TMMu32_MEMu32 AMX_TILE NOTSX:SPECIAL_AGEN_REQUIRED +TILERELEASE AMX_TILE AMX_TILE TILERELEASE AMX_TILE NOTSX +TILESTORED AMX_TILE AMX_TILE TILESTORED_MEMu32_TMMu32 AMX_TILE NOTSX:SPECIAL_AGEN_REQUIRED +TILEZERO AMX_TILE AMX_TILE TILEZERO_TMMu32 AMX_TILE NOTSX +TLBSYNC AMD_INVLPGB SYSTEM TLBSYNC AMD_INVLPGB AMDONLY +TPAUSE WAITPKG WAITPKG TPAUSE_GPR32u32 WAITPKG INVALID +TZCNT BMI1 BMI1 TZCNT_GPRv_GPRv BMI1 SCALABLE +TZCNT BMI1 BMI1 TZCNT_GPRv_MEMv BMI1 SCALABLE +TZMSK TBM TBM TZMSK_VGPR32d_MEMd TBM AMDONLY +TZMSK TBM TBM TZMSK_VGPR32d_VGPR32d TBM AMDONLY +TZMSK TBM TBM TZMSK_VGPRyy_MEMy TBM AMDONLY:SCALABLE +TZMSK TBM TBM TZMSK_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +UCOMISD SSE2 SSE UCOMISD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +UCOMISD SSE2 SSE UCOMISD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +UCOMISS SSE SSE UCOMISS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +UCOMISS SSE SSE UCOMISS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +UD0 BASE MISC UD0 PPRO_UD0_SHORT NOTSX +UD0 BASE MISC UD0_GPR32_GPR32 PPRO_UD0_LONG NOTSX +UD0 BASE MISC UD0_GPR32_MEMd PPRO_UD0_LONG NOTSX +UD1 BASE MISC UD1_GPR32_GPR32 PPRO NOTSX +UD1 BASE MISC UD1_GPR32_MEMd PPRO NOTSX +UD2 BASE MISC UD2 PPRO NOTSX +UIRET UINTR UINTR UIRET UINTR FIXED_BASE0:STACKPOP0:SCALABLE +UMONITOR WAITPKG WAITPKG UMONITOR_GPRa WAITPKG NOTSX +UMWAIT WAITPKG WAITPKG UMWAIT_GPR32 WAITPKG NOTSX +UNPCKHPD SSE2 SSE UNPCKHPD_XMMpd_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKHPD SSE2 SSE UNPCKHPD_XMMpd_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKHPS SSE SSE UNPCKHPS_XMMps_MEMdq SSE SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKHPS SSE SSE UNPCKHPS_XMMps_XMMdq SSE SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKLPD SSE2 SSE UNPCKLPD_XMMpd_MEMdq SSE2 REQUIRES_ALIGNMENT +UNPCKLPD SSE2 SSE UNPCKLPD_XMMpd_XMMq SSE2 REQUIRES_ALIGNMENT +UNPCKLPS SSE SSE UNPCKLPS_XMMps_MEMdq SSE REQUIRES_ALIGNMENT +UNPCKLPS SSE SSE UNPCKLPS_XMMps_XMMq SSE REQUIRES_ALIGNMENT +V4FMADDPS AVX512EVEX AVX512_4FMAPS V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512_4FMAPS_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MXCSR:MASKOP_EVEX +V4FMADDSS AVX512EVEX AVX512_4FMAPS V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512_4FMAPS_SCALAR DISP8_TUPLE1_4X:MXCSR:MULTISOURCE4:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR +V4FNMADDPS AVX512EVEX AVX512_4FMAPS V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512_4FMAPS_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MXCSR:MASKOP_EVEX +V4FNMADDSS AVX512EVEX AVX512_4FMAPS V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512_4FMAPS_SCALAR DISP8_TUPLE1_4X:MXCSR:MULTISOURCE4:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR +VADDPD AVX AVX VADDPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDPD AVX AVX VADDPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDPD AVX512EVEX AVX512 VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPD AVX512EVEX AVX512 VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VADDPD AVX512EVEX AVX512 VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPD AVX512EVEX AVX512 VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VADDPD AVX AVX VADDPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDPD AVX AVX VADDPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VADDPD AVX512EVEX AVX512 VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPD AVX512EVEX AVX512 VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VADDPS AVX AVX VADDPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDPS AVX AVX VADDPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDPS AVX512EVEX AVX512 VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPS AVX512EVEX AVX512 VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VADDPS AVX512EVEX AVX512 VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPS AVX512EVEX AVX512 VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VADDPS AVX AVX VADDPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDPS AVX AVX VADDPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VADDPS AVX512EVEX AVX512 VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPS AVX512EVEX AVX512 VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VADDSD AVX AVX VADDSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VADDSD AVX AVX VADDSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VADDSD AVX512EVEX AVX512 VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VADDSD AVX512EVEX AVX512 VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VADDSH AVX512EVEX FP16 VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VADDSH AVX512EVEX FP16 VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VADDSS AVX AVX VADDSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VADDSS AVX AVX VADDSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VADDSS AVX512EVEX AVX512 VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VADDSS AVX512EVEX AVX512 VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VADDSUBPD AVX AVX VADDSUBPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDSUBPD AVX AVX VADDSUBPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDSUBPD AVX AVX VADDSUBPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDSUBPD AVX AVX VADDSUBPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VAESDECLAST AVXAES AES VAESDECLAST_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESDECLAST AVXAES AES VAESDECLAST_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESDECLAST AVX512EVEX VAES VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESDECLAST VAES VAES VAESDECLAST_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESDECLAST VAES VAES VAESDECLAST_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESDECLAST AVX512EVEX VAES VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESDEC AVXAES AES VAESDEC_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESDEC AVXAES AES VAESDEC_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESDEC AVX512EVEX VAES VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESDEC AVX512EVEX VAES VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESDEC VAES VAES VAESDEC_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESDEC AVX512EVEX VAES VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESDEC VAES VAES VAESDEC_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESDEC AVX512EVEX VAES VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESDEC AVX512EVEX VAES VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESDEC AVX512EVEX VAES VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESENCLAST AVXAES AES VAESENCLAST_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESENCLAST AVXAES AES VAESENCLAST_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESENCLAST AVX512EVEX VAES VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESENCLAST VAES VAES VAESENCLAST_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESENCLAST VAES VAES VAESENCLAST_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESENCLAST AVX512EVEX VAES VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESENC AVXAES AES VAESENC_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESENC AVXAES AES VAESENC_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESENC AVX512EVEX VAES VAESENC_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESENC AVX512EVEX VAES VAESENC_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESENC VAES VAES VAESENC_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESENC AVX512EVEX VAES VAESENC_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESENC VAES VAES VAESENC_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESENC AVX512EVEX VAES VAESENC_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESENC AVX512EVEX VAES VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESENC AVX512EVEX VAES VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESIMC AVXAES AES VAESIMC_XMMdq_MEMdq AVXAES INVALID +VAESIMC AVXAES AES VAESIMC_XMMdq_XMMdq AVXAES INVALID +VAESKEYGENASSIST AVXAES AES VAESKEYGENASSIST_XMMdq_MEMdq_IMMb AVXAES INVALID +VAESKEYGENASSIST AVXAES AES VAESKEYGENASSIST_XMMdq_XMMdq_IMMb AVXAES INVALID +VALIGND AVX512EVEX AVX512 VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGND AVX512EVEX AVX512 VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VALIGND AVX512EVEX AVX512 VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGND AVX512EVEX AVX512 VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VALIGND AVX512EVEX AVX512 VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGND AVX512EVEX AVX512 VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VALIGNQ AVX512EVEX AVX512 VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGNQ AVX512EVEX AVX512 VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VALIGNQ AVX512EVEX AVX512 VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGNQ AVX512EVEX AVX512 VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VALIGNQ AVX512EVEX AVX512 VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGNQ AVX512EVEX AVX512 VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VANDNPD AVX LOGICAL_FP VANDNPD_XMMdq_XMMdq_MEMdq AVX INVALID +VANDNPD AVX LOGICAL_FP VANDNPD_XMMdq_XMMdq_XMMdq AVX INVALID +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDNPD AVX LOGICAL_FP VANDNPD_YMMqq_YMMqq_MEMqq AVX INVALID +VANDNPD AVX LOGICAL_FP VANDNPD_YMMqq_YMMqq_YMMqq AVX INVALID +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VANDNPS AVX LOGICAL_FP VANDNPS_XMMdq_XMMdq_MEMdq AVX INVALID +VANDNPS AVX LOGICAL_FP VANDNPS_XMMdq_XMMdq_XMMdq AVX INVALID +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDNPS AVX LOGICAL_FP VANDNPS_YMMqq_YMMqq_MEMqq AVX INVALID +VANDNPS AVX LOGICAL_FP VANDNPS_YMMqq_YMMqq_YMMqq AVX INVALID +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VANDPD AVX LOGICAL_FP VANDPD_XMMdq_XMMdq_MEMdq AVX INVALID +VANDPD AVX LOGICAL_FP VANDPD_XMMdq_XMMdq_XMMdq AVX INVALID +VANDPD AVX512EVEX LOGICAL_FP VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPD AVX512EVEX LOGICAL_FP VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDPD AVX LOGICAL_FP VANDPD_YMMqq_YMMqq_MEMqq AVX INVALID +VANDPD AVX LOGICAL_FP VANDPD_YMMqq_YMMqq_YMMqq AVX INVALID +VANDPD AVX512EVEX LOGICAL_FP VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPD AVX512EVEX LOGICAL_FP VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDPD AVX512EVEX LOGICAL_FP VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPD AVX512EVEX LOGICAL_FP VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VANDPS AVX LOGICAL_FP VANDPS_XMMdq_XMMdq_MEMdq AVX INVALID +VANDPS AVX LOGICAL_FP VANDPS_XMMdq_XMMdq_XMMdq AVX INVALID +VANDPS AVX512EVEX LOGICAL_FP VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPS AVX512EVEX LOGICAL_FP VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDPS AVX LOGICAL_FP VANDPS_YMMqq_YMMqq_MEMqq AVX INVALID +VANDPS AVX LOGICAL_FP VANDPS_YMMqq_YMMqq_YMMqq AVX INVALID +VANDPS AVX512EVEX LOGICAL_FP VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPS AVX512EVEX LOGICAL_FP VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDPS AVX512EVEX LOGICAL_FP VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPS AVX512EVEX LOGICAL_FP VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDPD AVX AVX VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VBLENDPD AVX AVX VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VBLENDPD AVX AVX VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VBLENDPD AVX AVX VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq AVX INVALID +VBROADCASTF128 AVX BROADCAST VBROADCASTF128_YMMqq_MEMdq AVX INVALID +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX +VBROADCASTF32X4 AVX512EVEX BROADCAST VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTF32X4 AVX512EVEX BROADCAST VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTF32X8 AVX512EVEX BROADCAST VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE8 +VBROADCASTF64X2 AVX512EVEX BROADCAST VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF64X2 AVX512EVEX BROADCAST VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF64X4 AVX512EVEX BROADCAST VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTI128 AVX2 BROADCAST VBROADCASTI128_YMMqq_MEMdq AVX2 INVALID +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VBROADCASTI32X4 AVX512EVEX BROADCAST VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTI32X4 AVX512EVEX BROADCAST VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTI32X8 AVX512EVEX BROADCAST VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE8 +VBROADCASTI64X2 AVX512EVEX BROADCAST VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI64X2 AVX512EVEX BROADCAST VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI64X4 AVX512EVEX BROADCAST VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VBROADCASTSD AVX BROADCAST VBROADCASTSD_YMMqq_MEMq AVX INVALID +VBROADCASTSD AVX2 BROADCAST VBROADCASTSD_YMMqq_XMMdq AVX2 INVALID +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VBROADCASTSS AVX BROADCAST VBROADCASTSS_XMMdq_MEMd AVX INVALID +VBROADCASTSS AVX2 BROADCAST VBROADCASTSS_XMMdq_XMMdq AVX2 INVALID +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VBROADCASTSS AVX BROADCAST VBROADCASTSS_YMMqq_MEMd AVX INVALID +VBROADCASTSS AVX2 BROADCAST VBROADCASTSS_YMMqq_XMMdq AVX2 INVALID +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCMPPD AVX AVX VCMPPD_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VCMPPD AVX AVX VCMPPD_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VCMPPD AVX AVX VCMPPD_YMMqq_YMMqq_MEMqq_IMMb AVX MXCSR +VCMPPD AVX AVX VCMPPD_YMMqq_YMMqq_YMMqq_IMMb AVX MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCMPPS AVX AVX VCMPPS_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VCMPPS AVX AVX VCMPPS_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VCMPPS AVX AVX VCMPPS_YMMqq_YMMqq_MEMqq_IMMb AVX MXCSR +VCMPPS AVX AVX VCMPPS_YMMqq_YMMqq_YMMqq_IMMb AVX MXCSR +VCMPSD AVX512EVEX AVX512 VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCMPSD AVX512EVEX AVX512 VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCMPSD AVX AVX VCMPSD_XMMdq_XMMdq_MEMq_IMMb AVX SIMD_SCALAR:MXCSR +VCMPSD AVX AVX VCMPSD_XMMdq_XMMdq_XMMq_IMMb AVX SIMD_SCALAR:MXCSR +VCMPSH AVX512EVEX FP16 VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VCMPSH AVX512EVEX FP16 VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCMPSS AVX512EVEX AVX512 VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCMPSS AVX512EVEX AVX512 VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCMPSS AVX AVX VCMPSS_XMMdq_XMMdq_MEMd_IMMb AVX SIMD_SCALAR:MXCSR +VCMPSS AVX AVX VCMPSS_XMMdq_XMMdq_XMMd_IMMb AVX SIMD_SCALAR:MXCSR +VCOMISD AVX512EVEX AVX512 VCOMISD_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCOMISD AVX512EVEX AVX512 VCOMISD_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCOMISD AVX AVX VCOMISD_XMMq_MEMq AVX SIMD_SCALAR:MXCSR +VCOMISD AVX AVX VCOMISD_XMMq_XMMq AVX SIMD_SCALAR:MXCSR +VCOMISH AVX512EVEX FP16 VCOMISH_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MXCSR:SIMD_SCALAR +VCOMISH AVX512EVEX FP16 VCOMISH_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCOMISS AVX AVX VCOMISS_XMMd_MEMd AVX SIMD_SCALAR:MXCSR +VCOMISS AVX AVX VCOMISS_XMMd_XMMd AVX SIMD_SCALAR:MXCSR +VCOMISS AVX512EVEX AVX512 VCOMISS_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCOMISS AVX512EVEX AVX512 VCOMISS_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_XMMdq_MEMq AVX INVALID +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_XMMdq_XMMq AVX INVALID +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_YMMqq_MEMdq AVX INVALID +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_YMMqq_XMMdq AVX INVALID +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_XMMdq_MEMdq AVX MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_XMMdq_XMMdq AVX MXCSR +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_YMMqq_MEMqq AVX MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_YMMqq_YMMqq AVX MXCSR +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 AVX512_BF16_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 AVX512_BF16_128 MASKOP_EVEX +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 AVX512_BF16_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 AVX512_BF16_256 MASKOP_EVEX +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 AVX512_BF16_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512_BF16_512 MASKOP_EVEX +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 AVX512_BF16_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 AVX512_BF16_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 AVX512_BF16_128 MASKOP_EVEX +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 AVX512_BF16_256 MASKOP_EVEX +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 AVX512_BF16_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 AVX512_BF16_512 MASKOP_EVEX +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_MEMdq AVX MXCSR +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_MEMqq AVX MXCSR +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_XMMdq AVX MXCSR +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_YMMqq AVX MXCSR +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_MEMdq AVX MXCSR +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_MEMqq AVX MXCSR +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_XMMdq AVX MXCSR +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_YMMqq AVX MXCSR +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PS F16C CONVERT VCVTPH2PS_XMMdq_MEMq F16C MXCSR +VCVTPH2PS F16C CONVERT VCVTPH2PS_XMMdq_XMMq F16C MXCSR +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPH2PS F16C CONVERT VCVTPH2PS_YMMqq_MEMdq F16C MXCSR +VCVTPH2PS F16C CONVERT VCVTPH2PS_YMMqq_XMMdq F16C MXCSR +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_XMMdq_MEMdq AVX MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_XMMdq_XMMdq AVX MXCSR +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_YMMqq_MEMqq AVX MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_YMMqq_YMMqq AVX MXCSR +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_XMMdq_MEMq AVX MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_XMMdq_XMMq AVX MXCSR +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_YMMqq_MEMdq AVX MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_YMMqq_XMMdq AVX MXCSR +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPS2PH F16C CONVERT VCVTPS2PH_MEMdq_YMMqq_IMMb F16C MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPS2PH F16C CONVERT VCVTPS2PH_MEMq_XMMdq_IMMb F16C MXCSR +VCVTPS2PH F16C CONVERT VCVTPS2PH_XMMdq_YMMqq_IMMb F16C MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2PH F16C CONVERT VCVTPS2PH_XMMq_XMMdq_IMMb F16C MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTSD2SH AVX512EVEX CONVERT VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSD2SH AVX512EVEX CONVERT VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR32d_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR32d_XMMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR32i32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR32i32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR64i64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR64i64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR64q_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR64q_XMMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SS AVX CONVERT VCVTSD2SS_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SS AVX CONVERT VCVTSD2SS_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SS AVX512EVEX CONVERT VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCVTSD2SS AVX512EVEX CONVERT VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR32u32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR32u32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR64u64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR64u64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2SD AVX512EVEX CONVERT VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2SD AVX512EVEX CONVERT VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR32i32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR32i32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR64i64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR64i64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2SS AVX512EVEX CONVERT VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2SS AVX512EVEX CONVERT VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR32u32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR32u32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR64u64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR64u64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_GPR32d AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_GPR64q AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 AVX512F_SCALAR SIMD_SCALAR +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 AVX512F_SCALAR SIMD_SCALAR:DISP8_GPR_READER +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_GPR32d AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_GPR64q AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTSS2SD AVX CONVERT VCVTSS2SD_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SD AVX CONVERT VCVTSS2SD_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SD AVX512EVEX CONVERT VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCVTSS2SD AVX512EVEX CONVERT VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCVTSS2SH AVX512EVEX CONVERT VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSS2SH AVX512EVEX CONVERT VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR32d_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR32d_XMMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR32i32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR32i32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR64i64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR64i64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR64q_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR64q_XMMd AVX SIMD_SCALAR:MXCSR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR32u32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR32u32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR64u64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR64u64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_MEMdq AVX MXCSR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_MEMqq AVX MXCSR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_XMMdq AVX MXCSR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_YMMqq AVX MXCSR +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_XMMdq_MEMdq AVX MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_XMMdq_XMMdq AVX MXCSR +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_YMMqq_MEMqq AVX MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_YMMqq_YMMqq AVX MXCSR +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR32d_MEMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR32d_XMMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR32i32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR32i32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR64i64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR64i64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR64q_MEMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR64q_XMMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR32u32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR32u32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR64u64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR64u64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR32i32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR32i32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR64i64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR64i64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR32u32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR32u32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR64u64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR64u64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR32d_MEMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR32d_XMMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR32i32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR32i32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR64i64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR64i64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR64q_MEMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR64q_XMMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR32u32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR32u32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR64u64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR64u64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 AVX512F_SCALAR SIMD_SCALAR +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 AVX512F_SCALAR SIMD_SCALAR:DISP8_GPR_READER +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VDIVPD AVX AVX VDIVPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VDIVPD AVX AVX VDIVPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VDIVPD AVX512EVEX AVX512 VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPD AVX512EVEX AVX512 VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VDIVPD AVX512EVEX AVX512 VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPD AVX512EVEX AVX512 VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VDIVPD AVX AVX VDIVPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VDIVPD AVX AVX VDIVPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VDIVPD AVX512EVEX AVX512 VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPD AVX512EVEX AVX512 VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VDIVPS AVX AVX VDIVPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VDIVPS AVX AVX VDIVPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VDIVPS AVX512EVEX AVX512 VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPS AVX512EVEX AVX512 VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VDIVPS AVX512EVEX AVX512 VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPS AVX512EVEX AVX512 VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VDIVPS AVX AVX VDIVPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VDIVPS AVX AVX VDIVPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VDIVPS AVX512EVEX AVX512 VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPS AVX512EVEX AVX512 VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VDIVSD AVX AVX VDIVSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VDIVSD AVX AVX VDIVSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VDIVSD AVX512EVEX AVX512 VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VDIVSD AVX512EVEX AVX512 VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VDIVSH AVX512EVEX FP16 VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VDIVSH AVX512EVEX FP16 VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VDIVSS AVX AVX VDIVSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VDIVSS AVX AVX VDIVSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VDIVSS AVX512EVEX AVX512 VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VDIVSS AVX512EVEX AVX512 VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_BF16_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_BF16_128 MASKOP_EVEX +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_BF16_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_BF16_256 MASKOP_EVEX +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_BF16_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_BF16_512 MASKOP_EVEX +VDPPD AVX AVX VDPPD_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VDPPD AVX AVX VDPPD_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_YMMqq_YMMqq_MEMqq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_YMMqq_YMMqq_YMMqq_IMMb AVX MXCSR +VERR BASE SYSTEM VERR_GPR16 I286PROTECTED PROTECTED_MODE +VERR BASE SYSTEM VERR_MEMw I286PROTECTED PROTECTED_MODE +VERW BASE SYSTEM VERW_GPR16 I286PROTECTED PROTECTED_MODE +VERW BASE SYSTEM VERW_MEMw I286PROTECTED PROTECTED_MODE +VEXP2PD AVX512EVEX AVX512 VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VEXP2PD AVX512EVEX AVX512 VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VEXP2PS AVX512EVEX AVX512 VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VEXP2PS AVX512EVEX AVX512 VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTF128 AVX AVX VEXTRACTF128_MEMdq_YMMdq_IMMb AVX INVALID +VEXTRACTF128 AVX AVX VEXTRACTF128_XMMdq_YMMdq_IMMb AVX INVALID +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTF32X8 AVX512EVEX AVX512 VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VEXTRACTF32X8 AVX512EVEX AVX512 VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTF64X4 AVX512EVEX AVX512 VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTF64X4 AVX512EVEX AVX512 VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTI128 AVX2 AVX2 VEXTRACTI128_MEMdq_YMMqq_IMMb AVX2 INVALID +VEXTRACTI128 AVX2 AVX2 VEXTRACTI128_XMMdq_YMMqq_IMMb AVX2 INVALID +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTI32X8 AVX512EVEX AVX512 VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VEXTRACTI32X8 AVX512EVEX AVX512 VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTI64X4 AVX512EVEX AVX512 VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTI64X4 AVX512EVEX AVX512 VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTPS AVX AVX VEXTRACTPS_GPR32_XMMdq_IMMb AVX INVALID +VEXTRACTPS AVX512EVEX AVX512 VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 AVX512F_128N INVALID +VEXTRACTPS AVX AVX VEXTRACTPS_MEMd_XMMdq_IMMb AVX INVALID +VEXTRACTPS AVX512EVEX AVX512 VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 AVX512F_128N DISP8_GPR_WRITER_STORE +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCSH AVX512EVEX FP16 VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFCMADDCSH AVX512EVEX FP16 VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMULCSH AVX512EVEX FP16 VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFCMULCSH AVX512EVEX FP16 VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFIXUPIMMSD AVX512EVEX AVX512 VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFIXUPIMMSD AVX512EVEX AVX512 VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFIXUPIMMSS AVX512EVEX AVX512 VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFIXUPIMMSS AVX512EVEX AVX512 VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD132PD FMA VFMA VFMADD132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD132PD FMA VFMA VFMADD132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD132PD FMA VFMA VFMADD132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD132PD FMA VFMA VFMADD132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD132SD FMA VFMA VFMADD132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMADD132SD FMA VFMA VFMADD132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMADD132SD AVX512EVEX VFMA VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD132SD AVX512EVEX VFMA VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD132SH AVX512EVEX FP16 VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMADD132SH AVX512EVEX FP16 VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD132SS FMA VFMA VFMADD132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMADD132SS FMA VFMA VFMADD132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMADD132SS AVX512EVEX VFMA VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD132SS AVX512EVEX VFMA VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD213PD FMA VFMA VFMADD213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD213PD FMA VFMA VFMADD213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD213PD FMA VFMA VFMADD213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD213PD FMA VFMA VFMADD213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD213SD FMA VFMA VFMADD213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMADD213SD FMA VFMA VFMADD213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMADD213SD AVX512EVEX VFMA VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD213SD AVX512EVEX VFMA VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD213SH AVX512EVEX FP16 VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMADD213SH AVX512EVEX FP16 VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD213SS FMA VFMA VFMADD213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMADD213SS FMA VFMA VFMADD213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMADD213SS AVX512EVEX VFMA VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD213SS AVX512EVEX VFMA VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD231PD FMA VFMA VFMADD231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD231PD FMA VFMA VFMADD231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD231PD FMA VFMA VFMADD231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD231PD FMA VFMA VFMADD231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD231SD FMA VFMA VFMADD231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMADD231SD FMA VFMA VFMADD231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMADD231SD AVX512EVEX VFMA VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD231SD AVX512EVEX VFMA VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD231SH AVX512EVEX FP16 VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMADD231SH AVX512EVEX FP16 VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD231SS FMA VFMA VFMADD231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMADD231SS FMA VFMA VFMADD231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMADD231SS AVX512EVEX VFMA VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD231SS AVX512EVEX VFMA VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMADDCSH AVX512EVEX FP16 VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFMADDCSH AVX512EVEX FP16 VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFMADDPD FMA4 FMA4 VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSD FMA4 FMA4 VFMADDSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSD FMA4 FMA4 VFMADDSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSD FMA4 FMA4 VFMADDSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSS FMA4 FMA4 VFMADDSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSS FMA4 FMA4 VFMADDSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSS FMA4 FMA4 VFMADDSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUB132PD FMA VFMA VFMSUB132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB132PD FMA VFMA VFMSUB132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB132PD FMA VFMA VFMSUB132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB132PD FMA VFMA VFMSUB132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB132SD FMA VFMA VFMSUB132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMSUB132SD FMA VFMA VFMSUB132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMSUB132SD AVX512EVEX VFMA VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB132SD AVX512EVEX VFMA VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB132SH AVX512EVEX FP16 VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMSUB132SH AVX512EVEX FP16 VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB132SS FMA VFMA VFMSUB132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMSUB132SS FMA VFMA VFMSUB132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMSUB132SS AVX512EVEX VFMA VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB132SS AVX512EVEX VFMA VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB213PD FMA VFMA VFMSUB213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB213PD FMA VFMA VFMSUB213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB213PD FMA VFMA VFMSUB213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB213PD FMA VFMA VFMSUB213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB213SD FMA VFMA VFMSUB213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMSUB213SD FMA VFMA VFMSUB213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMSUB213SD AVX512EVEX VFMA VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB213SD AVX512EVEX VFMA VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB213SH AVX512EVEX FP16 VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMSUB213SH AVX512EVEX FP16 VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB213SS FMA VFMA VFMSUB213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMSUB213SS FMA VFMA VFMSUB213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMSUB213SS AVX512EVEX VFMA VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB213SS AVX512EVEX VFMA VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB231PD FMA VFMA VFMSUB231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB231PD FMA VFMA VFMSUB231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB231PD FMA VFMA VFMSUB231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB231PD FMA VFMA VFMSUB231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB231SD FMA VFMA VFMSUB231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMSUB231SD FMA VFMA VFMSUB231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMSUB231SD AVX512EVEX VFMA VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB231SD AVX512EVEX VFMA VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB231SH AVX512EVEX FP16 VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMSUB231SH AVX512EVEX FP16 VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB231SS FMA VFMA VFMSUB231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMSUB231SS FMA VFMA VFMSUB231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMSUB231SS AVX512EVEX VFMA VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB231SS AVX512EVEX VFMA VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBSD FMA4 FMA4 VFMSUBSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSD FMA4 FMA4 VFMSUBSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSD FMA4 FMA4 VFMSUBSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSS FMA4 FMA4 VFMSUBSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSS FMA4 FMA4 VFMSUBSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSS FMA4 FMA4 VFMSUBSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMULCPH AVX512EVEX FP16 VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMULCSH AVX512EVEX FP16 VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFMULCSH AVX512EVEX FP16 VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFNMADD132PD FMA VFMA VFNMADD132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD132PD FMA VFMA VFNMADD132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD132PD FMA VFMA VFNMADD132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD132PD FMA VFMA VFNMADD132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD132SD FMA VFMA VFNMADD132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMADD132SD FMA VFMA VFNMADD132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMADD132SD AVX512EVEX VFMA VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD132SD AVX512EVEX VFMA VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD132SH AVX512EVEX FP16 VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMADD132SH AVX512EVEX FP16 VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD132SS FMA VFMA VFNMADD132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMADD132SS FMA VFMA VFNMADD132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMADD132SS AVX512EVEX VFMA VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD132SS AVX512EVEX VFMA VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD213PD FMA VFMA VFNMADD213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD213PD FMA VFMA VFNMADD213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD213PD FMA VFMA VFNMADD213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD213PD FMA VFMA VFNMADD213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD213SD FMA VFMA VFNMADD213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMADD213SD FMA VFMA VFNMADD213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMADD213SD AVX512EVEX VFMA VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD213SD AVX512EVEX VFMA VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD213SH AVX512EVEX FP16 VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMADD213SH AVX512EVEX FP16 VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD213SS FMA VFMA VFNMADD213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMADD213SS FMA VFMA VFNMADD213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMADD213SS AVX512EVEX VFMA VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD213SS AVX512EVEX VFMA VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD231PD FMA VFMA VFNMADD231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD231PD FMA VFMA VFNMADD231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD231PD FMA VFMA VFNMADD231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD231PD FMA VFMA VFNMADD231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD231SD FMA VFMA VFNMADD231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMADD231SD FMA VFMA VFNMADD231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMADD231SD AVX512EVEX VFMA VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD231SD AVX512EVEX VFMA VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD231SH AVX512EVEX FP16 VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMADD231SH AVX512EVEX FP16 VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD231SS FMA VFMA VFNMADD231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMADD231SS FMA VFMA VFNMADD231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMADD231SS AVX512EVEX VFMA VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD231SS AVX512EVEX VFMA VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADDPD FMA4 FMA4 VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDSD FMA4 FMA4 VFNMADDSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSD FMA4 FMA4 VFNMADDSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSD FMA4 FMA4 VFNMADDSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSS FMA4 FMA4 VFNMADDSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSS FMA4 FMA4 VFNMADDSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSS FMA4 FMA4 VFNMADDSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUB132PD FMA VFMA VFNMSUB132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB132PD FMA VFMA VFNMSUB132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB132PD FMA VFMA VFNMSUB132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB132PD FMA VFMA VFNMSUB132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB132SD FMA VFMA VFNMSUB132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMSUB132SD FMA VFMA VFNMSUB132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMSUB132SD AVX512EVEX VFMA VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB132SD AVX512EVEX VFMA VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB132SH AVX512EVEX FP16 VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMSUB132SH AVX512EVEX FP16 VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB132SS FMA VFMA VFNMSUB132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMSUB132SS FMA VFMA VFNMSUB132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMSUB132SS AVX512EVEX VFMA VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB132SS AVX512EVEX VFMA VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB213SD FMA VFMA VFNMSUB213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMSUB213SD FMA VFMA VFNMSUB213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMSUB213SD AVX512EVEX VFMA VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB213SD AVX512EVEX VFMA VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB213SH AVX512EVEX FP16 VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMSUB213SH AVX512EVEX FP16 VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB213SS FMA VFMA VFNMSUB213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMSUB213SS FMA VFMA VFNMSUB213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMSUB213SS AVX512EVEX VFMA VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB213SS AVX512EVEX VFMA VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB231SD FMA VFMA VFNMSUB231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMSUB231SD FMA VFMA VFNMSUB231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMSUB231SD AVX512EVEX VFMA VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB231SD AVX512EVEX VFMA VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB231SH AVX512EVEX FP16 VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMSUB231SH AVX512EVEX FP16 VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB231SS FMA VFMA VFNMSUB231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMSUB231SS FMA VFMA VFNMSUB231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMSUB231SS AVX512EVEX VFMA VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB231SS AVX512EVEX VFMA VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBSD FMA4 FMA4 VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSD FMA4 FMA4 VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSD FMA4 FMA4 VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSS FMA4 FMA4 VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSS FMA4 FMA4 VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSS FMA4 FMA4 VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VFPCLASSSD AVX512EVEX AVX512 VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFPCLASSSD AVX512EVEX AVX512 VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFPCLASSSH AVX512EVEX FP16 VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VFPCLASSSH AVX512EVEX FP16 VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VFPCLASSSS AVX512EVEX AVX512 VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFPCLASSSS AVX512EVEX AVX512 VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFRCZPD XOP XOP VFRCZPD_XMMdq_MEMdq XOP MXCSR:AMDONLY +VFRCZPD XOP XOP VFRCZPD_XMMdq_XMMdq XOP MXCSR:AMDONLY +VFRCZPD XOP XOP VFRCZPD_YMMqq_MEMqq XOP MXCSR:AMDONLY +VFRCZPD XOP XOP VFRCZPD_YMMqq_YMMqq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_XMMdq_MEMdq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_XMMdq_XMMdq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_YMMqq_MEMqq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_YMMqq_YMMqq XOP MXCSR:AMDONLY +VFRCZSD XOP XOP VFRCZSD_XMMdq_MEMq XOP SIMD_SCALAR:MXCSR:AMDONLY +VFRCZSD XOP XOP VFRCZSD_XMMdq_XMMq XOP SIMD_SCALAR:MXCSR:AMDONLY +VFRCZSS XOP XOP VFRCZSS_XMMdq_MEMd XOP SIMD_SCALAR:MXCSR:AMDONLY +VFRCZSS XOP XOP VFRCZSS_XMMdq_XMMd XOP SIMD_SCALAR:MXCSR:AMDONLY +VGATHERDPD AVX512EVEX GATHER VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX2GATHER AVX2GATHER VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX512EVEX GATHER VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX2GATHER AVX2GATHER VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX512EVEX GATHER VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX512EVEX GATHER VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX2GATHER AVX2GATHER VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX512EVEX GATHER VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX2GATHER AVX2GATHER VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX512EVEX GATHER VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERPF0DPD AVX512EVEX GATHER VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF0DPS AVX512EVEX GATHER VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF0QPD AVX512EVEX GATHER VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF0QPS AVX512EVEX GATHER VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1DPD AVX512EVEX GATHER VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1DPS AVX512EVEX GATHER VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1QPD AVX512EVEX GATHER VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1QPS AVX512EVEX GATHER VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERQPD AVX512EVEX GATHER VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX2GATHER AVX2GATHER VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX512EVEX GATHER VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX2GATHER AVX2GATHER VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX512EVEX GATHER VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX512EVEX GATHER VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX512EVEX GATHER VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX2GATHER AVX2GATHER VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX2GATHER AVX2GATHER VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX512EVEX GATHER VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETEXPSD AVX512EVEX AVX512 VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETEXPSD AVX512EVEX AVX512 VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETEXPSH AVX512EVEX FP16 VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VGETEXPSH AVX512EVEX FP16 VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETEXPSS AVX512EVEX AVX512 VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETEXPSS AVX512EVEX AVX512 VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETMANTSD AVX512EVEX AVX512 VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETMANTSD AVX512EVEX AVX512 VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETMANTSH AVX512EVEX FP16 VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VGETMANTSH AVX512EVEX FP16 VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETMANTSS AVX512EVEX AVX512 VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETMANTSS AVX512EVEX AVX512 VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_GFNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_GFNI_128 MASKOP_EVEX +VGF2P8MULB GFNI GFNI VGF2P8MULB_XMMu8_XMMu8_MEMu8 AVX_GFNI INVALID +VGF2P8MULB GFNI GFNI VGF2P8MULB_XMMu8_XMMu8_XMMu8 AVX_GFNI INVALID +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_GFNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_GFNI_256 MASKOP_EVEX +VGF2P8MULB GFNI GFNI VGF2P8MULB_YMMu8_YMMu8_MEMu8 AVX_GFNI INVALID +VGF2P8MULB GFNI GFNI VGF2P8MULB_YMMu8_YMMu8_YMMu8 AVX_GFNI INVALID +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_GFNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_GFNI_512 MASKOP_EVEX +VHADDPD AVX AVX VHADDPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VHADDPD AVX AVX VHADDPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VHADDPD AVX AVX VHADDPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VHADDPD AVX AVX VHADDPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VHADDPS AVX AVX VHADDPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VHADDPS AVX AVX VHADDPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VHADDPS AVX AVX VHADDPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VHADDPS AVX AVX VHADDPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VINSERTF128 AVX AVX VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb AVX INVALID +VINSERTF128 AVX AVX VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb AVX INVALID +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTF32X8 AVX512EVEX AVX512 VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VINSERTF32X8 AVX512EVEX AVX512 VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTF64X4 AVX512EVEX AVX512 VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTF64X4 AVX512EVEX AVX512 VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTI128 AVX2 AVX2 VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb AVX2 INVALID +VINSERTI128 AVX2 AVX2 VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb AVX2 INVALID +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTI32X8 AVX512EVEX AVX512 VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VINSERTI32X8 AVX512EVEX AVX512 VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTI64X4 AVX512EVEX AVX512 VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTI64X4 AVX512EVEX AVX512 VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTPS AVX AVX VINSERTPS_XMMdq_XMMdq_MEMd_IMMb AVX INVALID +VINSERTPS AVX AVX VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VINSERTPS AVX512EVEX AVX512 VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128N DISP8_TUPLE1 +VINSERTPS AVX512EVEX AVX512 VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128N INVALID +VLDDQU AVX AVX VLDDQU_XMMdq_MEMdq AVX INVALID +VLDDQU AVX AVX VLDDQU_YMMqq_MEMqq AVX INVALID +VLDMXCSR AVX AVX VLDMXCSR_MEMd AVX MXCSR +VMASKMOVDQU AVX AVX VMASKMOVDQU_XMMdq_XMMdq AVX MASKOP:FIXED_BASE0:NOTSX:NONTEMPORAL +VMASKMOVPD AVX AVX VMASKMOVPD_MEMdq_XMMdq_XMMdq AVX MASKOP +VMASKMOVPD AVX AVX VMASKMOVPD_MEMqq_YMMqq_YMMqq AVX MASKOP +VMASKMOVPD AVX AVX VMASKMOVPD_XMMdq_XMMdq_MEMdq AVX MASKOP +VMASKMOVPD AVX AVX VMASKMOVPD_YMMqq_YMMqq_MEMqq AVX MASKOP +VMASKMOVPS AVX AVX VMASKMOVPS_MEMdq_XMMdq_XMMdq AVX MASKOP:NONTEMPORAL +VMASKMOVPS AVX AVX VMASKMOVPS_MEMqq_YMMqq_YMMqq AVX MASKOP:NONTEMPORAL +VMASKMOVPS AVX AVX VMASKMOVPS_XMMdq_XMMdq_MEMdq AVX MASKOP:NONTEMPORAL +VMASKMOVPS AVX AVX VMASKMOVPS_YMMqq_YMMqq_MEMqq AVX MASKOP:NONTEMPORAL +VMAXPD AVX AVX VMAXPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VMAXPD AVX AVX VMAXPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VMAXPD AVX512EVEX AVX512 VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPD AVX512EVEX AVX512 VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMAXPD AVX512EVEX AVX512 VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPD AVX512EVEX AVX512 VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMAXPD AVX AVX VMAXPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VMAXPD AVX AVX VMAXPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VMAXPD AVX512EVEX AVX512 VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPD AVX512EVEX AVX512 VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VMAXPS AVX AVX VMAXPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VMAXPS AVX AVX VMAXPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VMAXPS AVX512EVEX AVX512 VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPS AVX512EVEX AVX512 VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMAXPS AVX512EVEX AVX512 VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPS AVX512EVEX AVX512 VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMAXPS AVX AVX VMAXPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VMAXPS AVX AVX VMAXPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VMAXPS AVX512EVEX AVX512 VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPS AVX512EVEX AVX512 VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMAXSD AVX AVX VMAXSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VMAXSD AVX AVX VMAXSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VMAXSD AVX512EVEX AVX512 VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMAXSD AVX512EVEX AVX512 VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMAXSH AVX512EVEX FP16 VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VMAXSH AVX512EVEX FP16 VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMAXSS AVX AVX VMAXSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VMAXSS AVX AVX VMAXSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VMAXSS AVX512EVEX AVX512 VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMAXSS AVX512EVEX AVX512 VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMCALL VTX VTX VMCALL VTX NOTSX +VMCLEAR VTX VTX VMCLEAR_MEMq VTX NOTSX +VMFUNC VMFUNC VTX VMFUNC VMFUNC INVALID +VMINPD AVX AVX VMINPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VMINPD AVX AVX VMINPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VMINPD AVX512EVEX AVX512 VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPD AVX512EVEX AVX512 VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMINPD AVX512EVEX AVX512 VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPD AVX512EVEX AVX512 VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMINPD AVX AVX VMINPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VMINPD AVX AVX VMINPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VMINPD AVX512EVEX AVX512 VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPD AVX512EVEX AVX512 VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VMINPS AVX AVX VMINPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VMINPS AVX AVX VMINPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VMINPS AVX512EVEX AVX512 VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPS AVX512EVEX AVX512 VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMINPS AVX512EVEX AVX512 VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPS AVX512EVEX AVX512 VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMINPS AVX AVX VMINPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VMINPS AVX AVX VMINPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VMINPS AVX512EVEX AVX512 VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPS AVX512EVEX AVX512 VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMINSD AVX AVX VMINSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VMINSD AVX AVX VMINSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VMINSD AVX512EVEX AVX512 VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMINSD AVX512EVEX AVX512 VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMINSH AVX512EVEX FP16 VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VMINSH AVX512EVEX FP16 VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMINSS AVX AVX VMINSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VMINSS AVX AVX VMINSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VMINSS AVX512EVEX AVX512 VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMINSS AVX512EVEX AVX512 VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMLAUNCH VTX VTX VMLAUNCH VTX NOTSX +VMLOAD SVM SYSTEM VMLOAD_ArAX SVM PROTECTED_MODE:AMDONLY +VMMCALL SVM SYSTEM VMMCALL SVM AMDONLY +VMOVAPD AVX DATAXFER VMOVAPD_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX DATAXFER VMOVAPD_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_XMMdq_XMMdq_28 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_XMMdq_XMMdq_29 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVAPD AVX DATAXFER VMOVAPD_YMMqq_MEMqq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_YMMqq_YMMqq_28 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_YMMqq_YMMqq_29 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVAPS AVX DATAXFER VMOVAPS_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX DATAXFER VMOVAPS_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_XMMdq_XMMdq_28 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_XMMdq_XMMdq_29 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVAPS AVX DATAXFER VMOVAPS_YMMqq_MEMqq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_YMMqq_YMMqq_28 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_YMMqq_YMMqq_29 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDDUP AVX DATAXFER VMOVDDUP_XMMdq_MEMq AVX INVALID +VMOVDDUP AVX DATAXFER VMOVDDUP_XMMdq_XMMq AVX INVALID +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MOVDDUP +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MOVDDUP +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDDUP AVX DATAXFER VMOVDDUP_YMMqq_MEMqq AVX INVALID +VMOVDDUP AVX DATAXFER VMOVDDUP_YMMqq_YMMqq AVX INVALID +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MOVDDUP +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQA AVX DATAXFER VMOVDQA_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_XMMdq_XMMdq_6F AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_XMMdq_XMMdq_7F AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_YMMqq_MEMqq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_YMMqq_YMMqq_6F AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_YMMqq_YMMqq_7F AVX REQUIRES_ALIGNMENT +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VMOVDQU AVX DATAXFER VMOVDQU_MEMdq_XMMdq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_MEMqq_YMMqq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_XMMdq_MEMdq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_XMMdq_XMMdq_6F AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_XMMdq_XMMdq_7F AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_YMMqq_MEMqq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_YMMqq_YMMqq_6F AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_YMMqq_YMMqq_7F AVX INVALID +VMOVD AVX DATAXFER VMOVD_GPR32d_XMMd AVX INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_GPR32u32_XMMu32_AVX512 AVX512F_128N INVALID +VMOVD AVX DATAXFER VMOVD_MEMd_XMMd AVX INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_MEMu32_XMMu32_AVX512 AVX512F_128N DISP8_GPR_WRITER_STORE +VMOVD AVX DATAXFER VMOVD_XMMdq_GPR32d AVX INVALID +VMOVD AVX DATAXFER VMOVD_XMMdq_MEMd AVX INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_XMMu32_GPR32u32_AVX512 AVX512F_128N INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_XMMu32_MEMu32_AVX512 AVX512F_128N DISP8_GPR_READER +VMOVHLPS AVX DATAXFER VMOVHLPS_XMMdq_XMMdq_XMMdq AVX INVALID +VMOVHLPS AVX512EVEX DATAXFER VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 AVX512F_128N INVALID +VMOVHPD AVX512EVEX DATAXFER VMOVHPD_MEMf64_XMMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVHPD AVX DATAXFER VMOVHPD_MEMq_XMMdq AVX INVALID +VMOVHPD AVX DATAXFER VMOVHPD_XMMdq_XMMq_MEMq AVX INVALID +VMOVHPD AVX512EVEX DATAXFER VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVHPS AVX512EVEX DATAXFER VMOVHPS_MEMf32_XMMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVHPS AVX DATAXFER VMOVHPS_MEMq_XMMdq AVX INVALID +VMOVHPS AVX DATAXFER VMOVHPS_XMMdq_XMMq_MEMq AVX INVALID +VMOVHPS AVX512EVEX DATAXFER VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVLHPS AVX DATAXFER VMOVLHPS_XMMdq_XMMq_XMMq AVX INVALID +VMOVLHPS AVX512EVEX DATAXFER VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 AVX512F_128N INVALID +VMOVLPD AVX512EVEX DATAXFER VMOVLPD_MEMf64_XMMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVLPD AVX DATAXFER VMOVLPD_MEMq_XMMq AVX INVALID +VMOVLPD AVX DATAXFER VMOVLPD_XMMdq_XMMdq_MEMq AVX INVALID +VMOVLPD AVX512EVEX DATAXFER VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVLPS AVX512EVEX DATAXFER VMOVLPS_MEMf32_XMMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVLPS AVX DATAXFER VMOVLPS_MEMq_XMMq AVX INVALID +VMOVLPS AVX DATAXFER VMOVLPS_XMMdq_XMMdq_MEMq AVX INVALID +VMOVLPS AVX512EVEX DATAXFER VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVMSKPD AVX DATAXFER VMOVMSKPD_GPR32d_XMMdq AVX INVALID +VMOVMSKPD AVX DATAXFER VMOVMSKPD_GPR32d_YMMqq AVX INVALID +VMOVMSKPS AVX DATAXFER VMOVMSKPS_GPR32d_XMMdq AVX INVALID +VMOVMSKPS AVX DATAXFER VMOVMSKPS_GPR32d_YMMqq AVX INVALID +VMOVNTDQA AVX DATAXFER VMOVNTDQA_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQA AVX512EVEX DATAXFER VMOVNTDQA_XMMu32_MEMu32_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQA AVX2 DATAXFER VMOVNTDQA_YMMqq_MEMqq AVX2 REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQA AVX512EVEX DATAXFER VMOVNTDQA_YMMu32_MEMu32_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQA AVX512EVEX DATAXFER VMOVNTDQA_ZMMu32_MEMu32_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQ AVX DATAXFER VMOVNTDQ_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQ AVX DATAXFER VMOVNTDQ_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQ AVX512EVEX DATAXFER VMOVNTDQ_MEMu32_XMMu32_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQ AVX512EVEX DATAXFER VMOVNTDQ_MEMu32_YMMu32_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQ AVX512EVEX DATAXFER VMOVNTDQ_MEMu32_ZMMu32_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX DATAXFER VMOVNTPD_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTPD AVX512EVEX DATAXFER VMOVNTPD_MEMf64_XMMf64_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX512EVEX DATAXFER VMOVNTPD_MEMf64_YMMf64_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX512EVEX DATAXFER VMOVNTPD_MEMf64_ZMMf64_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX DATAXFER VMOVNTPD_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTPS AVX DATAXFER VMOVNTPS_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTPS AVX512EVEX DATAXFER VMOVNTPS_MEMf32_XMMf32_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPS AVX512EVEX DATAXFER VMOVNTPS_MEMf32_YMMf32_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPS AVX512EVEX DATAXFER VMOVNTPS_MEMf32_ZMMf32_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPS AVX DATAXFER VMOVNTPS_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVQ AVX DATAXFER VMOVQ_GPR64q_XMMq AVX INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_GPR64u64_XMMu64_AVX512 AVX512F_128N INVALID +VMOVQ AVX DATAXFER VMOVQ_MEMq_XMMq_7E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_MEMq_XMMq_D6 AVX INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_MEMu64_XMMu64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVQ AVX DATAXFER VMOVQ_XMMdq_GPR64q AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_MEMq_6E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_MEMq_7E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_XMMq_7E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_XMMq_D6 AVX INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_XMMu64_GPR64u64_AVX512 AVX512F_128N INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_XMMu64_MEMu64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVQ AVX512EVEX DATAXFER VMOVQ_XMMu64_XMMu64_AVX512 AVX512F_128N INVALID +VMOVSD AVX512EVEX DATAXFER VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSD AVX DATAXFER VMOVSD_MEMq_XMMq AVX SIMD_SCALAR +VMOVSD AVX DATAXFER VMOVSD_XMMdq_MEMq AVX SIMD_SCALAR +VMOVSD AVX DATAXFER VMOVSD_XMMdq_XMMdq_XMMq_10 AVX SIMD_SCALAR +VMOVSD AVX DATAXFER VMOVSD_XMMdq_XMMdq_XMMq_11 AVX SIMD_SCALAR +VMOVSD AVX512EVEX DATAXFER VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSD AVX512EVEX DATAXFER VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:SIMD_SCALAR +VMOVSHDUP AVX DATAXFER VMOVSHDUP_XMMdq_MEMdq AVX INVALID +VMOVSHDUP AVX DATAXFER VMOVSHDUP_XMMdq_XMMdq AVX INVALID +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULLMEM +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULLMEM +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVSHDUP AVX DATAXFER VMOVSHDUP_YMMqq_MEMqq AVX INVALID +VMOVSHDUP AVX DATAXFER VMOVSHDUP_YMMqq_YMMqq AVX INVALID +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULLMEM +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVSH AVX512EVEX DATAXFER VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VMOVSH AVX512EVEX DATAXFER VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VMOVSH AVX512EVEX DATAXFER VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VMOVSLDUP AVX DATAXFER VMOVSLDUP_XMMdq_MEMdq AVX INVALID +VMOVSLDUP AVX DATAXFER VMOVSLDUP_XMMdq_XMMdq AVX INVALID +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULLMEM +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULLMEM +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVSLDUP AVX DATAXFER VMOVSLDUP_YMMqq_MEMqq AVX INVALID +VMOVSLDUP AVX DATAXFER VMOVSLDUP_YMMqq_YMMqq AVX INVALID +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULLMEM +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVSS AVX DATAXFER VMOVSS_MEMd_XMMd AVX SIMD_SCALAR +VMOVSS AVX512EVEX DATAXFER VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSS AVX DATAXFER VMOVSS_XMMdq_MEMd AVX SIMD_SCALAR +VMOVSS AVX DATAXFER VMOVSS_XMMdq_XMMdq_XMMd_10 AVX SIMD_SCALAR +VMOVSS AVX DATAXFER VMOVSS_XMMdq_XMMdq_XMMd_11 AVX SIMD_SCALAR +VMOVSS AVX512EVEX DATAXFER VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSS AVX512EVEX DATAXFER VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:SIMD_SCALAR +VMOVUPD AVX DATAXFER VMOVUPD_MEMdq_XMMdq AVX INVALID +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX DATAXFER VMOVUPD_MEMqq_YMMqq AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_XMMdq_MEMdq AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_XMMdq_XMMdq_10 AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_XMMdq_XMMdq_11 AVX INVALID +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVUPD AVX DATAXFER VMOVUPD_YMMqq_MEMqq AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_YMMqq_YMMqq_10 AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_YMMqq_YMMqq_11 AVX INVALID +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVUPS AVX DATAXFER VMOVUPS_MEMdq_XMMdq AVX INVALID +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX DATAXFER VMOVUPS_MEMqq_YMMqq AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_XMMdq_MEMdq AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_XMMdq_XMMdq_10 AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_XMMdq_XMMdq_11 AVX INVALID +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVUPS AVX DATAXFER VMOVUPS_YMMqq_MEMqq AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_YMMqq_YMMqq_10 AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_YMMqq_YMMqq_11 AVX INVALID +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVW AVX512EVEX DATAXFER VMOVW_GPR32f16_XMMf16_AVX512 AVX512_FP16_128N INVALID +VMOVW AVX512EVEX DATAXFER VMOVW_MEMf16_XMMf16_AVX512 AVX512_FP16_128N DISP8_GPR_WRITER_STORE +VMOVW AVX512EVEX DATAXFER VMOVW_XMMf16_GPR32f16_AVX512 AVX512_FP16_128N INVALID +VMOVW AVX512EVEX DATAXFER VMOVW_XMMf16_MEMf16_AVX512 AVX512_FP16_128N DISP8_GPR_READER +VMPSADBW AVX AVX VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VMPSADBW AVX AVX VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VMPSADBW AVX2 AVX2 VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VMPSADBW AVX2 AVX2 VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VMPTRLD VTX VTX VMPTRLD_MEMq VTX NOTSX +VMPTRST VTX VTX VMPTRST_MEMq VTX NOTSX +VMREAD VTX VTX VMREAD_GPR32_GPR32 VTX INVALID +VMREAD VTX VTX VMREAD_GPR64_GPR64 VTX INVALID +VMREAD VTX VTX VMREAD_MEMd_GPR32 VTX INVALID +VMREAD VTX VTX VMREAD_MEMq_GPR64 VTX INVALID +VMRESUME VTX VTX VMRESUME VTX NOTSX +VMRUN SVM SYSTEM VMRUN_ArAX SVM PROTECTED_MODE:AMDONLY +VMSAVE SVM SYSTEM VMSAVE SVM PROTECTED_MODE:AMDONLY +VMULPD AVX AVX VMULPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VMULPD AVX AVX VMULPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VMULPD AVX512EVEX AVX512 VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPD AVX512EVEX AVX512 VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMULPD AVX512EVEX AVX512 VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPD AVX512EVEX AVX512 VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMULPD AVX AVX VMULPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VMULPD AVX AVX VMULPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VMULPD AVX512EVEX AVX512 VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPD AVX512EVEX AVX512 VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VMULPS AVX AVX VMULPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VMULPS AVX AVX VMULPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VMULPS AVX512EVEX AVX512 VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPS AVX512EVEX AVX512 VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMULPS AVX512EVEX AVX512 VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPS AVX512EVEX AVX512 VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMULPS AVX AVX VMULPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VMULPS AVX AVX VMULPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VMULPS AVX512EVEX AVX512 VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPS AVX512EVEX AVX512 VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMULSD AVX AVX VMULSD_XMMdq_XMMdq_MEMq AVX MXCSR:SIMD_SCALAR +VMULSD AVX AVX VMULSD_XMMdq_XMMdq_XMMq AVX MXCSR:SIMD_SCALAR +VMULSD AVX512EVEX AVX512 VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMULSD AVX512EVEX AVX512 VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMULSH AVX512EVEX FP16 VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VMULSH AVX512EVEX FP16 VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMULSS AVX AVX VMULSS_XMMdq_XMMdq_MEMd AVX MXCSR:SIMD_SCALAR +VMULSS AVX AVX VMULSS_XMMdq_XMMdq_XMMd AVX MXCSR:SIMD_SCALAR +VMULSS AVX512EVEX AVX512 VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMULSS AVX512EVEX AVX512 VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMWRITE VTX VTX VMWRITE_GPR32_GPR32 VTX INVALID +VMWRITE VTX VTX VMWRITE_GPR32_MEMd VTX INVALID +VMWRITE VTX VTX VMWRITE_GPR64_GPR64 VTX INVALID +VMWRITE VTX VTX VMWRITE_GPR64_MEMq VTX INVALID +VMXOFF VTX VTX VMXOFF VTX NOTSX +VMXON VTX VTX VMXON_MEMq VTX PROTECTED_MODE:NOTSX +VORPD AVX LOGICAL_FP VORPD_XMMdq_XMMdq_MEMdq AVX INVALID +VORPD AVX LOGICAL_FP VORPD_XMMdq_XMMdq_XMMdq AVX INVALID +VORPD AVX512EVEX LOGICAL_FP VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPD AVX512EVEX LOGICAL_FP VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VORPD AVX LOGICAL_FP VORPD_YMMqq_YMMqq_MEMqq AVX INVALID +VORPD AVX LOGICAL_FP VORPD_YMMqq_YMMqq_YMMqq AVX INVALID +VORPD AVX512EVEX LOGICAL_FP VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPD AVX512EVEX LOGICAL_FP VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VORPD AVX512EVEX LOGICAL_FP VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPD AVX512EVEX LOGICAL_FP VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VORPS AVX LOGICAL_FP VORPS_XMMdq_XMMdq_MEMdq AVX INVALID +VORPS AVX LOGICAL_FP VORPS_XMMdq_XMMdq_XMMdq AVX INVALID +VORPS AVX512EVEX LOGICAL_FP VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPS AVX512EVEX LOGICAL_FP VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VORPS AVX LOGICAL_FP VORPS_YMMqq_YMMqq_MEMqq AVX INVALID +VORPS AVX LOGICAL_FP VORPS_YMMqq_YMMqq_YMMqq AVX INVALID +VORPS AVX512EVEX LOGICAL_FP VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPS AVX512EVEX LOGICAL_FP VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VORPS AVX512EVEX LOGICAL_FP VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPS AVX512EVEX LOGICAL_FP VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_VP2INTERSECT_128 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_VP2INTERSECT_128 MULTIDEST2 +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_VP2INTERSECT_256 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_VP2INTERSECT_256 MULTIDEST2 +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_VP2INTERSECT_512 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_VP2INTERSECT_512 MULTIDEST2 +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_VP2INTERSECT_128 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_VP2INTERSECT_128 MULTIDEST2 +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_VP2INTERSECT_256 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_VP2INTERSECT_256 MULTIDEST2 +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_VP2INTERSECT_512 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_VP2INTERSECT_512 MULTIDEST2 +VP4DPWSSDS AVX512EVEX AVX512_4VNNIW VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_4VNNIW_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MASKOP_EVEX +VP4DPWSSD AVX512EVEX AVX512_4VNNIW VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_4VNNIW_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MASKOP_EVEX +VPABSB AVX AVX VPABSB_XMMdq_MEMdq AVX INVALID +VPABSB AVX AVX VPABSB_XMMdq_XMMdq AVX INVALID +VPABSB AVX512EVEX AVX512 VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSB AVX512EVEX AVX512 VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPABSB AVX512EVEX AVX512 VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSB AVX512EVEX AVX512 VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPABSB AVX2 AVX2 VPABSB_YMMqq_MEMqq AVX2 INVALID +VPABSB AVX2 AVX2 VPABSB_YMMqq_YMMqq AVX2 INVALID +VPABSB AVX512EVEX AVX512 VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSB AVX512EVEX AVX512 VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPABSD AVX AVX VPABSD_XMMdq_MEMdq AVX INVALID +VPABSD AVX AVX VPABSD_XMMdq_XMMdq AVX INVALID +VPABSD AVX512EVEX AVX512 VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSD AVX512EVEX AVX512 VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPABSD AVX512EVEX AVX512 VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSD AVX512EVEX AVX512 VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPABSD AVX2 AVX2 VPABSD_YMMqq_MEMqq AVX2 INVALID +VPABSD AVX2 AVX2 VPABSD_YMMqq_YMMqq AVX2 INVALID +VPABSD AVX512EVEX AVX512 VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSD AVX512EVEX AVX512 VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPABSQ AVX512EVEX AVX512 VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSQ AVX512EVEX AVX512 VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPABSQ AVX512EVEX AVX512 VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSQ AVX512EVEX AVX512 VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPABSQ AVX512EVEX AVX512 VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSQ AVX512EVEX AVX512 VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPABSW AVX AVX VPABSW_XMMdq_MEMdq AVX INVALID +VPABSW AVX AVX VPABSW_XMMdq_XMMdq AVX INVALID +VPABSW AVX512EVEX AVX512 VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSW AVX512EVEX AVX512 VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPABSW AVX512EVEX AVX512 VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSW AVX512EVEX AVX512 VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPABSW AVX2 AVX2 VPABSW_YMMqq_MEMqq AVX2 INVALID +VPABSW AVX2 AVX2 VPABSW_YMMqq_YMMqq AVX2 INVALID +VPABSW AVX512EVEX AVX512 VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSW AVX512EVEX AVX512 VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKSSDW AVX AVX VPACKSSDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKSSDW AVX AVX VPACKSSDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKSSDW AVX2 AVX2 VPACKSSDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKSSDW AVX2 AVX2 VPACKSSDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKSSWB AVX AVX VPACKSSWB_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKSSWB AVX AVX VPACKSSWB_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKSSWB AVX2 AVX2 VPACKSSWB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKSSWB AVX2 AVX2 VPACKSSWB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKUSDW AVX AVX VPACKUSDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKUSDW AVX AVX VPACKUSDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKUSDW AVX2 AVX2 VPACKUSDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKUSDW AVX2 AVX2 VPACKUSDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKUSWB AVX AVX VPACKUSWB_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKUSWB AVX AVX VPACKUSWB_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKUSWB AVX2 AVX2 VPACKUSWB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKUSWB AVX2 AVX2 VPACKUSWB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDB AVX AVX VPADDB_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDB AVX AVX VPADDB_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDB AVX512EVEX AVX512 VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDB AVX512EVEX AVX512 VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDB AVX2 AVX2 VPADDB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDB AVX2 AVX2 VPADDB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDB AVX512EVEX AVX512 VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDB AVX512EVEX AVX512 VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDB AVX512EVEX AVX512 VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDB AVX512EVEX AVX512 VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDD AVX AVX VPADDD_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDD AVX AVX VPADDD_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDD AVX512EVEX AVX512 VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDD AVX512EVEX AVX512 VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPADDD AVX2 AVX2 VPADDD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDD AVX2 AVX2 VPADDD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDD AVX512EVEX AVX512 VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDD AVX512EVEX AVX512 VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPADDD AVX512EVEX AVX512 VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDD AVX512EVEX AVX512 VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPADDQ AVX AVX VPADDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDQ AVX AVX VPADDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDQ AVX512EVEX AVX512 VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDQ AVX512EVEX AVX512 VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPADDQ AVX2 AVX2 VPADDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDQ AVX2 AVX2 VPADDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDQ AVX512EVEX AVX512 VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDQ AVX512EVEX AVX512 VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPADDQ AVX512EVEX AVX512 VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDQ AVX512EVEX AVX512 VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPADDSB AVX AVX VPADDSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDSB AVX AVX VPADDSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDSB AVX512EVEX AVX512 VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSB AVX512EVEX AVX512 VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDSB AVX512EVEX AVX512 VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSB AVX512EVEX AVX512 VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDSB AVX2 AVX2 VPADDSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDSB AVX2 AVX2 VPADDSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDSB AVX512EVEX AVX512 VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSB AVX512EVEX AVX512 VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDSW AVX AVX VPADDSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDSW AVX AVX VPADDSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDSW AVX512EVEX AVX512 VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSW AVX512EVEX AVX512 VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDSW AVX512EVEX AVX512 VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSW AVX512EVEX AVX512 VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDSW AVX2 AVX2 VPADDSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDSW AVX2 AVX2 VPADDSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDSW AVX512EVEX AVX512 VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSW AVX512EVEX AVX512 VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDUSB AVX AVX VPADDUSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDUSB AVX AVX VPADDUSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDUSB AVX512EVEX AVX512 VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSB AVX512EVEX AVX512 VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDUSB AVX2 AVX2 VPADDUSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDUSB AVX2 AVX2 VPADDUSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDUSB AVX512EVEX AVX512 VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSB AVX512EVEX AVX512 VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDUSB AVX512EVEX AVX512 VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSB AVX512EVEX AVX512 VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDUSW AVX AVX VPADDUSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDUSW AVX AVX VPADDUSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDUSW AVX512EVEX AVX512 VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSW AVX512EVEX AVX512 VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDUSW AVX2 AVX2 VPADDUSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDUSW AVX2 AVX2 VPADDUSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDUSW AVX512EVEX AVX512 VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSW AVX512EVEX AVX512 VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDUSW AVX512EVEX AVX512 VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSW AVX512EVEX AVX512 VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDW AVX AVX VPADDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDW AVX AVX VPADDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDW AVX512EVEX AVX512 VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDW AVX512EVEX AVX512 VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDW AVX2 AVX2 VPADDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDW AVX2 AVX2 VPADDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDW AVX512EVEX AVX512 VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDW AVX512EVEX AVX512 VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDW AVX512EVEX AVX512 VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDW AVX512EVEX AVX512 VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPALIGNR AVX AVX VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VPALIGNR AVX AVX VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VPALIGNR AVX512EVEX AVX512 VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPALIGNR AVX512EVEX AVX512 VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPALIGNR AVX2 AVX2 VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPALIGNR AVX2 AVX2 VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPALIGNR AVX512EVEX AVX512 VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPALIGNR AVX512EVEX AVX512 VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPALIGNR AVX512EVEX AVX512 VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPALIGNR AVX512EVEX AVX512 VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPANDD AVX512EVEX LOGICAL VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDD AVX512EVEX LOGICAL VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPANDD AVX512EVEX LOGICAL VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDD AVX512EVEX LOGICAL VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPANDD AVX512EVEX LOGICAL VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDD AVX512EVEX LOGICAL VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPANDND AVX512EVEX LOGICAL VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDND AVX512EVEX LOGICAL VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPANDND AVX512EVEX LOGICAL VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDND AVX512EVEX LOGICAL VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPANDND AVX512EVEX LOGICAL VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDND AVX512EVEX LOGICAL VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPANDN AVX LOGICAL VPANDN_XMMdq_XMMdq_MEMdq AVX INVALID +VPANDN AVX LOGICAL VPANDN_XMMdq_XMMdq_XMMdq AVX INVALID +VPANDN AVX2 LOGICAL VPANDN_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPANDN AVX2 LOGICAL VPANDN_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPANDQ AVX512EVEX LOGICAL VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDQ AVX512EVEX LOGICAL VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPANDQ AVX512EVEX LOGICAL VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDQ AVX512EVEX LOGICAL VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPANDQ AVX512EVEX LOGICAL VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDQ AVX512EVEX LOGICAL VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPAND AVX LOGICAL VPAND_XMMdq_XMMdq_MEMdq AVX INVALID +VPAND AVX LOGICAL VPAND_XMMdq_XMMdq_XMMdq AVX INVALID +VPAND AVX2 LOGICAL VPAND_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPAND AVX2 LOGICAL VPAND_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPAVGB AVX AVX VPAVGB_XMMdq_XMMdq_MEMdq AVX INVALID +VPAVGB AVX AVX VPAVGB_XMMdq_XMMdq_XMMdq AVX INVALID +VPAVGB AVX512EVEX AVX512 VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGB AVX512EVEX AVX512 VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPAVGB AVX2 AVX2 VPAVGB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPAVGB AVX2 AVX2 VPAVGB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPAVGB AVX512EVEX AVX512 VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGB AVX512EVEX AVX512 VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPAVGB AVX512EVEX AVX512 VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGB AVX512EVEX AVX512 VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPAVGW AVX AVX VPAVGW_XMMdq_XMMdq_MEMdq AVX INVALID +VPAVGW AVX AVX VPAVGW_XMMdq_XMMdq_XMMdq AVX INVALID +VPAVGW AVX512EVEX AVX512 VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGW AVX512EVEX AVX512 VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPAVGW AVX2 AVX2 VPAVGW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPAVGW AVX2 AVX2 VPAVGW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPAVGW AVX512EVEX AVX512 VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGW AVX512EVEX AVX512 VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPAVGW AVX512EVEX AVX512 VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGW AVX512EVEX AVX512 VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPBLENDD AVX2 AVX2 VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb AVX2 INVALID +VPBLENDD AVX2 AVX2 VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb AVX2 INVALID +VPBLENDD AVX2 AVX2 VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPBLENDD AVX2 AVX2 VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDVB AVX AVX VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq AVX INVALID +VPBLENDVB AVX AVX VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq AVX INVALID +VPBLENDVB AVX2 AVX2 VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq AVX2 INVALID +VPBLENDVB AVX2 AVX2 VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPBLENDW AVX AVX VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VPBLENDW AVX AVX VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VPBLENDW AVX2 AVX2 VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPBLENDW AVX2 AVX2 VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_XMMdq_MEMb AVX2 INVALID +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_XMMdq_XMMb AVX2 INVALID +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_BYTE +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_YMMqq_MEMb AVX2 INVALID +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_YMMqq_XMMb AVX2 INVALID +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_BYTE +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 AVX512BW_512 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_BYTE +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_XMMdq_MEMd AVX2 INVALID +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_XMMdq_XMMd AVX2 INVALID +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_YMMqq_MEMd AVX2 INVALID +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_YMMqq_XMMd AVX2 INVALID +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTMB2Q AVX512EVEX BROADCAST VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 AVX512CD_128 INVALID +VPBROADCASTMB2Q AVX512EVEX BROADCAST VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 AVX512CD_256 INVALID +VPBROADCASTMB2Q AVX512EVEX BROADCAST VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD AVX512CD_512 INVALID +VPBROADCASTMW2D AVX512EVEX BROADCAST VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 AVX512CD_128 INVALID +VPBROADCASTMW2D AVX512EVEX BROADCAST VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 AVX512CD_256 INVALID +VPBROADCASTMW2D AVX512EVEX BROADCAST VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD AVX512CD_512 INVALID +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_XMMdq_MEMq AVX2 INVALID +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_XMMdq_XMMq AVX2 INVALID +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_YMMqq_MEMq AVX2 INVALID +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_YMMqq_XMMq AVX2 INVALID +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_XMMdq_MEMw AVX2 INVALID +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_XMMdq_XMMw AVX2 INVALID +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_WORD +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_YMMqq_MEMw AVX2 INVALID +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_YMMqq_XMMw AVX2 INVALID +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_WORD +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 AVX512BW_512 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_WORD +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPCLMULQDQ AVX AVX VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VPCLMULQDQ AVX AVX VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_128 DISP8_FULLMEM +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_128 INVALID +VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 VPCLMULQDQ INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_256 DISP8_FULLMEM +VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 VPCLMULQDQ INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_256 INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_512 DISP8_FULLMEM +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_512 INVALID +VPCMOV XOP XOP VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq XOP AMDONLY +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPEQB AVX AVX VPCMPEQB_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQB AVX AVX VPCMPEQB_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQB AVX2 AVX2 VPCMPEQB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQB AVX2 AVX2 VPCMPEQB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPEQD AVX AVX VPCMPEQD_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQD AVX AVX VPCMPEQD_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQD AVX2 AVX2 VPCMPEQD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQD AVX2 AVX2 VPCMPEQD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPEQQ AVX AVX VPCMPEQQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQQ AVX AVX VPCMPEQQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQQ AVX2 AVX2 VPCMPEQQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQQ AVX2 AVX2 VPCMPEQQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPEQW AVX AVX VPCMPEQW_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQW AVX AVX VPCMPEQW_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQW AVX2 AVX2 VPCMPEQW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQW AVX2 AVX2 VPCMPEQW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPESTRI64 AVX STTNI VPCMPESTRI64_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRI64 AVX STTNI VPCMPESTRI64_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPESTRI AVX STTNI VPCMPESTRI_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRI AVX STTNI VPCMPESTRI_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPESTRM64 AVX STTNI VPCMPESTRM64_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRM64 AVX STTNI VPCMPESTRM64_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPESTRM AVX STTNI VPCMPESTRM_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRM AVX STTNI VPCMPESTRM_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPGTB AVX AVX VPCMPGTB_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTB AVX AVX VPCMPGTB_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTB AVX2 AVX2 VPCMPGTB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTB AVX2 AVX2 VPCMPGTB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPGTD AVX AVX VPCMPGTD_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTD AVX AVX VPCMPGTD_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTD AVX2 AVX2 VPCMPGTD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTD AVX2 AVX2 VPCMPGTD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPGTQ AVX AVX VPCMPGTQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTQ AVX AVX VPCMPGTQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTQ AVX2 AVX2 VPCMPGTQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTQ AVX2 AVX2 VPCMPGTQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPGTW AVX AVX VPCMPGTW_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTW AVX AVX VPCMPGTW_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTW AVX2 AVX2 VPCMPGTW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTW AVX2 AVX2 VPCMPGTW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPISTRI64 AVX STTNI VPCMPISTRI64_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPISTRI64 AVX STTNI VPCMPISTRI64_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPISTRI AVX STTNI VPCMPISTRI_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPISTRI AVX STTNI VPCMPISTRI_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPISTRM AVX STTNI VPCMPISTRM_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPISTRM AVX STTNI VPCMPISTRM_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCOMB XOP XOP VPCOMB_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMB XOP XOP VPCOMB_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMD XOP XOP VPCOMD_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMD XOP XOP VPCOMD_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPCOMQ XOP XOP VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMQ XOP XOP VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUB XOP XOP VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUB XOP XOP VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUD XOP XOP VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUD XOP XOP VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUQ XOP XOP VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUQ XOP XOP VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUW XOP XOP VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUW XOP XOP VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMW XOP XOP VPCOMW_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMW XOP XOP VPCOMW_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512CD_128 MASKOP_EVEX +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512CD_256 MASKOP_EVEX +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD AVX512CD_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD AVX512CD_512 MASKOP_EVEX +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512CD_128 MASKOP_EVEX +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512CD_256 MASKOP_EVEX +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD AVX512CD_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD AVX512CD_512 MASKOP_EVEX +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPBUSD AVX_VNNI VEX VPDPBUSD_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSD AVX_VNNI VEX VPDPBUSD_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPBUSD AVX_VNNI VEX VPDPBUSD_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSD AVX_VNNI VEX VPDPBUSD_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPWSSD AVX_VNNI VEX VPDPWSSD_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSD AVX_VNNI VEX VPDPWSSD_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPWSSD AVX_VNNI VEX VPDPWSSD_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSD AVX_VNNI VEX VPDPWSSD_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPERM2F128 AVX AVX VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VPERM2F128 AVX AVX VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VPERM2I128 AVX2 AVX2 VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPERM2I128 AVX2 AVX2 VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPERMB AVX512EVEX AVX512_VBMI VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMB AVX512EVEX AVX512_VBMI VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPERMB AVX512EVEX AVX512_VBMI VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMB AVX512EVEX AVX512_VBMI VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPERMB AVX512EVEX AVX512_VBMI VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMB AVX512EVEX AVX512_VBMI VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPERMD AVX2 AVX2 VPERMD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPERMD AVX2 AVX2 VPERMD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPERMD AVX512EVEX AVX512 VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMD AVX512EVEX AVX512 VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMD AVX512EVEX AVX512 VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMD AVX512EVEX AVX512 VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPERMI2D AVX512EVEX AVX512 VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2D AVX512EVEX AVX512 VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2D AVX512EVEX AVX512 VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2D AVX512EVEX AVX512 VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2D AVX512EVEX AVX512 VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2D AVX512EVEX AVX512 VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2W AVX512EVEX AVX512 VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2W AVX512EVEX AVX512 VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPERMI2W AVX512EVEX AVX512 VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2W AVX512EVEX AVX512 VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPERMI2W AVX512EVEX AVX512 VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2W AVX512EVEX AVX512 VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPERMIL2PD XOP XOP VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb XOP AMDONLY +VPERMILPD AVX AVX VPERMILPD_XMMdq_MEMdq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_XMMdq_XMMdq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_XMMdq_XMMdq_MEMdq AVX INVALID +VPERMILPD AVX AVX VPERMILPD_XMMdq_XMMdq_XMMdq AVX INVALID +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPD AVX AVX VPERMILPD_YMMqq_MEMqq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_YMMqq_YMMqq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_YMMqq_YMMqq_MEMqq AVX INVALID +VPERMILPD AVX AVX VPERMILPD_YMMqq_YMMqq_YMMqq AVX INVALID +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMILPS AVX AVX VPERMILPS_XMMdq_MEMdq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_XMMdq_XMMdq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_XMMdq_XMMdq_MEMdq AVX INVALID +VPERMILPS AVX AVX VPERMILPS_XMMdq_XMMdq_XMMdq AVX INVALID +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPS AVX AVX VPERMILPS_YMMqq_MEMqq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_YMMqq_YMMqq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_YMMqq_YMMqq_MEMqq AVX INVALID +VPERMILPS AVX AVX VPERMILPS_YMMqq_YMMqq_YMMqq AVX INVALID +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMPD AVX2 AVX2 VPERMPD_YMMqq_MEMqq_IMMb AVX2 INVALID +VPERMPD AVX2 AVX2 VPERMPD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMPS AVX512EVEX AVX512 VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPS AVX512EVEX AVX512 VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMPS AVX2 AVX2 VPERMPS_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPERMPS AVX2 AVX2 VPERMPS_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPERMPS AVX512EVEX AVX512 VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPS AVX512EVEX AVX512 VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMQ AVX2 AVX2 VPERMQ_YMMqq_MEMqq_IMMb AVX2 INVALID +VPERMQ AVX2 AVX2 VPERMQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPERMT2D AVX512EVEX AVX512 VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2D AVX512EVEX AVX512 VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2D AVX512EVEX AVX512 VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2D AVX512EVEX AVX512 VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2D AVX512EVEX AVX512 VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2D AVX512EVEX AVX512 VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2W AVX512EVEX AVX512 VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2W AVX512EVEX AVX512 VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPERMT2W AVX512EVEX AVX512 VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2W AVX512EVEX AVX512 VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPERMT2W AVX512EVEX AVX512 VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2W AVX512EVEX AVX512 VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPERMW AVX512EVEX AVX512 VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMW AVX512EVEX AVX512 VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPERMW AVX512EVEX AVX512 VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMW AVX512EVEX AVX512 VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPERMW AVX512EVEX AVX512 VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMW AVX512EVEX AVX512 VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPEXTRB AVX AVX VPEXTRB_GPR32d_XMMdq_IMMb AVX INVALID +VPEXTRB AVX512EVEX AVX512 VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 AVX512BW_128N INVALID +VPEXTRB AVX AVX VPEXTRB_MEMb_XMMdq_IMMb AVX INVALID +VPEXTRB AVX512EVEX AVX512 VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 AVX512BW_128N DISP8_GPR_WRITER_STORE_BYTE +VPEXTRD AVX AVX VPEXTRD_GPR32d_XMMdq_IMMb AVX INVALID +VPEXTRD AVX512EVEX AVX512 VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 AVX512DQ_128N INVALID +VPEXTRD AVX AVX VPEXTRD_MEMd_XMMdq_IMMb AVX INVALID +VPEXTRD AVX512EVEX AVX512 VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_WRITER_STORE +VPEXTRQ AVX AVX VPEXTRQ_GPR64q_XMMdq_IMMb AVX INVALID +VPEXTRQ AVX512EVEX AVX512 VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 AVX512DQ_128N INVALID +VPEXTRQ AVX AVX VPEXTRQ_MEMq_XMMdq_IMMb AVX INVALID +VPEXTRQ AVX512EVEX AVX512 VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_WRITER_STORE +VPEXTRW AVX AVX VPEXTRW_GPR32d_XMMdq_IMMb_15 AVX INVALID +VPEXTRW AVX AVX VPEXTRW_GPR32d_XMMdq_IMMb_C5 AVX INVALID +VPEXTRW AVX512EVEX AVX512 VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 AVX512BW_128N INVALID +VPEXTRW_C5 AVX512EVEX AVX512 VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 AVX512BW_128N INVALID +VPEXTRW AVX512EVEX AVX512 VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 AVX512BW_128N DISP8_GPR_WRITER_STORE_WORD +VPEXTRW AVX AVX VPEXTRW_MEMw_XMMdq_IMMb AVX INVALID +VPGATHERDD AVX512EVEX GATHER VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX2GATHER AVX2GATHER VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX512EVEX GATHER VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX2GATHER AVX2GATHER VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX512EVEX GATHER VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX512EVEX GATHER VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX2GATHER AVX2GATHER VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX512EVEX GATHER VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX2GATHER AVX2GATHER VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX512EVEX GATHER VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX512EVEX GATHER VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX512EVEX GATHER VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX2GATHER AVX2GATHER VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX2GATHER AVX2GATHER VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX512EVEX GATHER VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX512EVEX GATHER VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX2GATHER AVX2GATHER VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX512EVEX GATHER VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX2GATHER AVX2GATHER VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX512EVEX GATHER VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPHADDBD XOP XOP VPHADDBD_XMMdq_MEMdq XOP AMDONLY +VPHADDBD XOP XOP VPHADDBD_XMMdq_XMMdq XOP AMDONLY +VPHADDBQ XOP XOP VPHADDBQ_XMMdq_MEMdq XOP AMDONLY +VPHADDBQ XOP XOP VPHADDBQ_XMMdq_XMMdq XOP AMDONLY +VPHADDBW XOP XOP VPHADDBW_XMMdq_MEMdq XOP AMDONLY +VPHADDBW XOP XOP VPHADDBW_XMMdq_XMMdq XOP AMDONLY +VPHADDDQ XOP XOP VPHADDDQ_XMMdq_MEMdq XOP AMDONLY +VPHADDDQ XOP XOP VPHADDDQ_XMMdq_XMMdq XOP AMDONLY +VPHADDD AVX AVX VPHADDD_XMMdq_XMMdq_MEMdq AVX INVALID +VPHADDD AVX AVX VPHADDD_XMMdq_XMMdq_XMMdq AVX INVALID +VPHADDD AVX2 AVX2 VPHADDD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHADDD AVX2 AVX2 VPHADDD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHADDSW AVX AVX VPHADDSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHADDSW AVX AVX VPHADDSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHADDSW AVX2 AVX2 VPHADDSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHADDSW AVX2 AVX2 VPHADDSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHADDUBD XOP XOP VPHADDUBD_XMMdq_MEMdq XOP AMDONLY +VPHADDUBD XOP XOP VPHADDUBD_XMMdq_XMMdq XOP AMDONLY +VPHADDUBQ XOP XOP VPHADDUBQ_XMMdq_MEMdq XOP AMDONLY +VPHADDUBQ XOP XOP VPHADDUBQ_XMMdq_XMMdq XOP AMDONLY +VPHADDUBW XOP XOP VPHADDUBW_XMMdq_MEMdq XOP AMDONLY +VPHADDUBW XOP XOP VPHADDUBW_XMMdq_XMMdq XOP AMDONLY +VPHADDUDQ XOP XOP VPHADDUDQ_XMMdq_MEMdq XOP AMDONLY +VPHADDUDQ XOP XOP VPHADDUDQ_XMMdq_XMMdq XOP AMDONLY +VPHADDUWD XOP XOP VPHADDUWD_XMMdq_MEMdq XOP AMDONLY +VPHADDUWD XOP XOP VPHADDUWD_XMMdq_XMMdq XOP AMDONLY +VPHADDUWQ XOP XOP VPHADDUWQ_XMMdq_MEMdq XOP AMDONLY +VPHADDUWQ XOP XOP VPHADDUWQ_XMMdq_XMMdq XOP AMDONLY +VPHADDWD XOP XOP VPHADDWD_XMMdq_MEMdq XOP AMDONLY +VPHADDWD XOP XOP VPHADDWD_XMMdq_XMMdq XOP AMDONLY +VPHADDWQ XOP XOP VPHADDWQ_XMMdq_MEMdq XOP AMDONLY +VPHADDWQ XOP XOP VPHADDWQ_XMMdq_XMMdq XOP AMDONLY +VPHADDW AVX AVX VPHADDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHADDW AVX AVX VPHADDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHADDW AVX2 AVX2 VPHADDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHADDW AVX2 AVX2 VPHADDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHMINPOSUW AVX AVX VPHMINPOSUW_XMMdq_MEMdq AVX INVALID +VPHMINPOSUW AVX AVX VPHMINPOSUW_XMMdq_XMMdq AVX INVALID +VPHSUBBW XOP XOP VPHSUBBW_XMMdq_MEMdq XOP AMDONLY +VPHSUBBW XOP XOP VPHSUBBW_XMMdq_XMMdq XOP AMDONLY +VPHSUBDQ XOP XOP VPHSUBDQ_XMMdq_MEMdq XOP AMDONLY +VPHSUBDQ XOP XOP VPHSUBDQ_XMMdq_XMMdq XOP AMDONLY +VPHSUBD AVX AVX VPHSUBD_XMMdq_XMMdq_MEMdq AVX INVALID +VPHSUBD AVX AVX VPHSUBD_XMMdq_XMMdq_XMMdq AVX INVALID +VPHSUBD AVX2 AVX2 VPHSUBD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHSUBD AVX2 AVX2 VPHSUBD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHSUBSW AVX AVX VPHSUBSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHSUBSW AVX AVX VPHSUBSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHSUBSW AVX2 AVX2 VPHSUBSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHSUBSW AVX2 AVX2 VPHSUBSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHSUBWD XOP XOP VPHSUBWD_XMMdq_MEMdq XOP AMDONLY +VPHSUBWD XOP XOP VPHSUBWD_XMMdq_XMMdq XOP AMDONLY +VPHSUBW AVX AVX VPHSUBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHSUBW AVX AVX VPHSUBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHSUBW AVX2 AVX2 VPHSUBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHSUBW AVX2 AVX2 VPHSUBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPINSRB AVX AVX VPINSRB_XMMdq_XMMdq_GPR32d_IMMb AVX INVALID +VPINSRB AVX AVX VPINSRB_XMMdq_XMMdq_MEMb_IMMb AVX INVALID +VPINSRB AVX512EVEX AVX512 VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 AVX512BW_128N INVALID +VPINSRB AVX512EVEX AVX512 VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128N DISP8_GPR_READER_BYTE +VPINSRD AVX AVX VPINSRD_XMMdq_XMMdq_GPR32d_IMMb AVX INVALID +VPINSRD AVX AVX VPINSRD_XMMdq_XMMdq_MEMd_IMMb AVX INVALID +VPINSRD AVX512EVEX AVX512 VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 AVX512DQ_128N INVALID +VPINSRD AVX512EVEX AVX512 VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_READER +VPINSRQ AVX AVX VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb AVX INVALID +VPINSRQ AVX AVX VPINSRQ_XMMdq_XMMdq_MEMq_IMMb AVX INVALID +VPINSRQ AVX512EVEX AVX512 VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 AVX512DQ_128N INVALID +VPINSRQ AVX512EVEX AVX512 VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_READER +VPINSRW AVX AVX VPINSRW_XMMdq_XMMdq_GPR32d_IMMb AVX INVALID +VPINSRW AVX AVX VPINSRW_XMMdq_XMMdq_MEMw_IMMb AVX INVALID +VPINSRW AVX512EVEX AVX512 VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 AVX512BW_128N INVALID +VPINSRW AVX512EVEX AVX512 VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 AVX512BW_128N DISP8_GPR_READER_WORD +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512CD_128 MASKOP_EVEX +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512CD_256 MASKOP_EVEX +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD AVX512CD_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD AVX512CD_512 MASKOP_EVEX +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512CD_128 MASKOP_EVEX +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512CD_256 MASKOP_EVEX +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD AVX512CD_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD AVX512CD_512 MASKOP_EVEX +VPMACSDD XOP XOP VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSDD XOP XOP VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSDQH XOP XOP VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSDQH XOP XOP VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSDQL XOP XOP VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSDQL XOP XOP VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSDD XOP XOP VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSDD XOP XOP VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSDQH XOP XOP VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSDQH XOP XOP VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSDQL XOP XOP VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSDQL XOP XOP VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSWD XOP XOP VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSWD XOP XOP VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSWW XOP XOP VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSWW XOP XOP VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSWD XOP XOP VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSWD XOP XOP VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSWW XOP XOP VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSWW XOP XOP VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMADCSSWD XOP XOP VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMADCSSWD XOP XOP VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMADCSWD XOP XOP VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMADCSWD XOP XOP VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_IFMA_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_IFMA_128 MASKOP_EVEX +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_IFMA_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_IFMA_256 MASKOP_EVEX +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_IFMA_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_IFMA_512 MASKOP_EVEX +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_IFMA_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_IFMA_128 MASKOP_EVEX +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_IFMA_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_IFMA_256 MASKOP_EVEX +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_IFMA_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_IFMA_512 MASKOP_EVEX +VPMADDUBSW AVX AVX VPMADDUBSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMADDUBSW AVX AVX VPMADDUBSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMADDUBSW AVX2 AVX2 VPMADDUBSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMADDUBSW AVX2 AVX2 VPMADDUBSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMADDWD AVX AVX VPMADDWD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMADDWD AVX AVX VPMADDWD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMADDWD AVX512EVEX AVX512 VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPMADDWD AVX512EVEX AVX512 VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMADDWD AVX512EVEX AVX512 VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPMADDWD AVX512EVEX AVX512 VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMADDWD AVX2 AVX2 VPMADDWD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMADDWD AVX2 AVX2 VPMADDWD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMADDWD AVX512EVEX AVX512 VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPMADDWD AVX512EVEX AVX512 VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_MEMdq_XMMdq_XMMdq AVX2 MASKOP +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_MEMqq_YMMqq_YMMqq AVX2 MASKOP +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_XMMdq_XMMdq_MEMdq AVX2 MASKOP +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_YMMqq_YMMqq_MEMqq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_MEMdq_XMMdq_XMMdq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_MEMqq_YMMqq_YMMqq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_XMMdq_XMMdq_MEMdq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_YMMqq_YMMqq_MEMqq AVX2 MASKOP +VPMAXSB AVX AVX VPMAXSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXSB AVX AVX VPMAXSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXSB AVX512EVEX AVX512 VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSB AVX512EVEX AVX512 VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXSB AVX512EVEX AVX512 VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSB AVX512EVEX AVX512 VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXSB AVX2 AVX2 VPMAXSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXSB AVX2 AVX2 VPMAXSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXSB AVX512EVEX AVX512 VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSB AVX512EVEX AVX512 VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMAXSD AVX AVX VPMAXSD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXSD AVX AVX VPMAXSD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXSD AVX512EVEX AVX512 VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSD AVX512EVEX AVX512 VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXSD AVX512EVEX AVX512 VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSD AVX512EVEX AVX512 VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXSD AVX2 AVX2 VPMAXSD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXSD AVX2 AVX2 VPMAXSD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXSD AVX512EVEX AVX512 VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSD AVX512EVEX AVX512 VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXSW AVX AVX VPMAXSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXSW AVX AVX VPMAXSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXSW AVX512EVEX AVX512 VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSW AVX512EVEX AVX512 VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXSW AVX512EVEX AVX512 VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSW AVX512EVEX AVX512 VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXSW AVX2 AVX2 VPMAXSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXSW AVX2 AVX2 VPMAXSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXSW AVX512EVEX AVX512 VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSW AVX512EVEX AVX512 VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMAXUB AVX AVX VPMAXUB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXUB AVX AVX VPMAXUB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXUB AVX512EVEX AVX512 VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUB AVX512EVEX AVX512 VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXUB AVX2 AVX2 VPMAXUB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXUB AVX2 AVX2 VPMAXUB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXUB AVX512EVEX AVX512 VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUB AVX512EVEX AVX512 VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXUB AVX512EVEX AVX512 VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUB AVX512EVEX AVX512 VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMAXUD AVX AVX VPMAXUD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXUD AVX AVX VPMAXUD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXUD AVX512EVEX AVX512 VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUD AVX512EVEX AVX512 VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXUD AVX2 AVX2 VPMAXUD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXUD AVX2 AVX2 VPMAXUD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXUD AVX512EVEX AVX512 VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUD AVX512EVEX AVX512 VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXUD AVX512EVEX AVX512 VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUD AVX512EVEX AVX512 VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXUW AVX AVX VPMAXUW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXUW AVX AVX VPMAXUW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXUW AVX512EVEX AVX512 VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUW AVX512EVEX AVX512 VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXUW AVX2 AVX2 VPMAXUW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXUW AVX2 AVX2 VPMAXUW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXUW AVX512EVEX AVX512 VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUW AVX512EVEX AVX512 VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXUW AVX512EVEX AVX512 VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUW AVX512EVEX AVX512 VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINSB AVX AVX VPMINSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINSB AVX AVX VPMINSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINSB AVX512EVEX AVX512 VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSB AVX512EVEX AVX512 VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINSB AVX512EVEX AVX512 VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSB AVX512EVEX AVX512 VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINSB AVX2 AVX2 VPMINSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINSB AVX2 AVX2 VPMINSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINSB AVX512EVEX AVX512 VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSB AVX512EVEX AVX512 VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINSD AVX AVX VPMINSD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINSD AVX AVX VPMINSD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINSD AVX512EVEX AVX512 VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSD AVX512EVEX AVX512 VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMINSD AVX512EVEX AVX512 VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSD AVX512EVEX AVX512 VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMINSD AVX2 AVX2 VPMINSD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINSD AVX2 AVX2 VPMINSD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINSD AVX512EVEX AVX512 VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSD AVX512EVEX AVX512 VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMINSQ AVX512EVEX AVX512 VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSQ AVX512EVEX AVX512 VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMINSQ AVX512EVEX AVX512 VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSQ AVX512EVEX AVX512 VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMINSQ AVX512EVEX AVX512 VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSQ AVX512EVEX AVX512 VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMINSW AVX AVX VPMINSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINSW AVX AVX VPMINSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINSW AVX512EVEX AVX512 VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSW AVX512EVEX AVX512 VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINSW AVX512EVEX AVX512 VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSW AVX512EVEX AVX512 VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINSW AVX2 AVX2 VPMINSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINSW AVX2 AVX2 VPMINSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINSW AVX512EVEX AVX512 VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSW AVX512EVEX AVX512 VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINUB AVX AVX VPMINUB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINUB AVX AVX VPMINUB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINUB AVX512EVEX AVX512 VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUB AVX512EVEX AVX512 VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINUB AVX2 AVX2 VPMINUB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINUB AVX2 AVX2 VPMINUB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINUB AVX512EVEX AVX512 VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUB AVX512EVEX AVX512 VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINUB AVX512EVEX AVX512 VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUB AVX512EVEX AVX512 VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINUD AVX AVX VPMINUD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINUD AVX AVX VPMINUD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINUD AVX512EVEX AVX512 VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUD AVX512EVEX AVX512 VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMINUD AVX2 AVX2 VPMINUD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINUD AVX2 AVX2 VPMINUD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINUD AVX512EVEX AVX512 VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUD AVX512EVEX AVX512 VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMINUD AVX512EVEX AVX512 VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUD AVX512EVEX AVX512 VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMINUQ AVX512EVEX AVX512 VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUQ AVX512EVEX AVX512 VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMINUQ AVX512EVEX AVX512 VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUQ AVX512EVEX AVX512 VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMINUQ AVX512EVEX AVX512 VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUQ AVX512EVEX AVX512 VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMINUW AVX AVX VPMINUW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINUW AVX AVX VPMINUW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINUW AVX512EVEX AVX512 VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUW AVX512EVEX AVX512 VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINUW AVX2 AVX2 VPMINUW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINUW AVX2 AVX2 VPMINUW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINUW AVX512EVEX AVX512 VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUW AVX512EVEX AVX512 VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINUW AVX512EVEX AVX512 VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUW AVX512EVEX AVX512 VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVB2M AVX512EVEX DATAXFER VPMOVB2M_MASKmskw_XMMu8_AVX512 AVX512BW_128 INVALID +VPMOVB2M AVX512EVEX DATAXFER VPMOVB2M_MASKmskw_YMMu8_AVX512 AVX512BW_256 INVALID +VPMOVB2M AVX512EVEX DATAXFER VPMOVB2M_MASKmskw_ZMMu8_AVX512 AVX512BW_512 INVALID +VPMOVD2M AVX512EVEX DATAXFER VPMOVD2M_MASKmskw_XMMu32_AVX512 AVX512DQ_128 INVALID +VPMOVD2M AVX512EVEX DATAXFER VPMOVD2M_MASKmskw_YMMu32_AVX512 AVX512DQ_256 INVALID +VPMOVD2M AVX512EVEX DATAXFER VPMOVD2M_MASKmskw_ZMMu32_AVX512 AVX512DQ_512 INVALID +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVM2B AVX512EVEX DATAXFER VPMOVM2B_XMMu8_MASKmskw_AVX512 AVX512BW_128 INVALID +VPMOVM2B AVX512EVEX DATAXFER VPMOVM2B_YMMu8_MASKmskw_AVX512 AVX512BW_256 INVALID +VPMOVM2B AVX512EVEX DATAXFER VPMOVM2B_ZMMu8_MASKmskw_AVX512 AVX512BW_512 INVALID +VPMOVM2D AVX512EVEX DATAXFER VPMOVM2D_XMMu32_MASKmskw_AVX512 AVX512DQ_128 INVALID +VPMOVM2D AVX512EVEX DATAXFER VPMOVM2D_YMMu32_MASKmskw_AVX512 AVX512DQ_256 INVALID +VPMOVM2D AVX512EVEX DATAXFER VPMOVM2D_ZMMu32_MASKmskw_AVX512 AVX512DQ_512 INVALID +VPMOVM2Q AVX512EVEX DATAXFER VPMOVM2Q_XMMu64_MASKmskw_AVX512 AVX512DQ_128 INVALID +VPMOVM2Q AVX512EVEX DATAXFER VPMOVM2Q_YMMu64_MASKmskw_AVX512 AVX512DQ_256 INVALID +VPMOVM2Q AVX512EVEX DATAXFER VPMOVM2Q_ZMMu64_MASKmskw_AVX512 AVX512DQ_512 INVALID +VPMOVM2W AVX512EVEX DATAXFER VPMOVM2W_XMMu16_MASKmskw_AVX512 AVX512BW_128 INVALID +VPMOVM2W AVX512EVEX DATAXFER VPMOVM2W_YMMu16_MASKmskw_AVX512 AVX512BW_256 INVALID +VPMOVM2W AVX512EVEX DATAXFER VPMOVM2W_ZMMu16_MASKmskw_AVX512 AVX512BW_512 INVALID +VPMOVMSKB AVX AVX VPMOVMSKB_GPR32d_XMMdq AVX INVALID +VPMOVMSKB AVX2 AVX2 VPMOVMSKB_GPR32d_YMMqq AVX2 INVALID +VPMOVQ2M AVX512EVEX DATAXFER VPMOVQ2M_MASKmskw_XMMu64_AVX512 AVX512DQ_128 INVALID +VPMOVQ2M AVX512EVEX DATAXFER VPMOVQ2M_MASKmskw_YMMu64_AVX512 AVX512DQ_256 INVALID +VPMOVQ2M AVX512EVEX DATAXFER VPMOVQ2M_MASKmskw_ZMMu64_AVX512 AVX512DQ_512 INVALID +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVSXBD AVX AVX VPMOVSXBD_XMMdq_MEMd AVX INVALID +VPMOVSXBD AVX AVX VPMOVSXBD_XMMdq_XMMd AVX INVALID +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXBD AVX2 AVX2 VPMOVSXBD_YMMqq_MEMq AVX2 INVALID +VPMOVSXBD AVX2 AVX2 VPMOVSXBD_YMMqq_XMMq AVX2 INVALID +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXBQ AVX AVX VPMOVSXBQ_XMMdq_MEMw AVX INVALID +VPMOVSXBQ AVX AVX VPMOVSXBQ_XMMdq_XMMw AVX INVALID +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXBQ AVX2 AVX2 VPMOVSXBQ_YMMqq_MEMd AVX2 INVALID +VPMOVSXBQ AVX2 AVX2 VPMOVSXBQ_YMMqq_XMMd AVX2 INVALID +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXBW AVX AVX VPMOVSXBW_XMMdq_MEMq AVX INVALID +VPMOVSXBW AVX AVX VPMOVSXBW_XMMdq_XMMq AVX INVALID +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVSXBW AVX2 AVX2 VPMOVSXBW_YMMqq_MEMdq AVX2 INVALID +VPMOVSXBW AVX2 AVX2 VPMOVSXBW_YMMqq_XMMdq AVX2 INVALID +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVSXDQ AVX AVX VPMOVSXDQ_XMMdq_MEMq AVX INVALID +VPMOVSXDQ AVX AVX VPMOVSXDQ_XMMdq_XMMq AVX INVALID +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXDQ AVX2 AVX2 VPMOVSXDQ_YMMqq_MEMdq AVX2 INVALID +VPMOVSXDQ AVX2 AVX2 VPMOVSXDQ_YMMqq_XMMdq AVX2 INVALID +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXWD AVX AVX VPMOVSXWD_XMMdq_MEMq AVX INVALID +VPMOVSXWD AVX AVX VPMOVSXWD_XMMdq_XMMq AVX INVALID +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXWD AVX2 AVX2 VPMOVSXWD_YMMqq_MEMdq AVX2 INVALID +VPMOVSXWD AVX2 AVX2 VPMOVSXWD_YMMqq_XMMdq AVX2 INVALID +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXWQ AVX AVX VPMOVSXWQ_XMMdq_MEMd AVX INVALID +VPMOVSXWQ AVX AVX VPMOVSXWQ_XMMdq_XMMd AVX INVALID +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXWQ AVX2 AVX2 VPMOVSXWQ_YMMqq_MEMq AVX2 INVALID +VPMOVSXWQ AVX2 AVX2 VPMOVSXWQ_YMMqq_XMMq AVX2 INVALID +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVW2M AVX512EVEX DATAXFER VPMOVW2M_MASKmskw_XMMu16_AVX512 AVX512BW_128 INVALID +VPMOVW2M AVX512EVEX DATAXFER VPMOVW2M_MASKmskw_YMMu16_AVX512 AVX512BW_256 INVALID +VPMOVW2M AVX512EVEX DATAXFER VPMOVW2M_MASKmskw_ZMMu16_AVX512 AVX512BW_512 INVALID +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVZXBD AVX AVX VPMOVZXBD_XMMdq_MEMd AVX INVALID +VPMOVZXBD AVX AVX VPMOVZXBD_XMMdq_XMMd AVX INVALID +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXBD AVX2 AVX2 VPMOVZXBD_YMMqq_MEMq AVX2 INVALID +VPMOVZXBD AVX2 AVX2 VPMOVZXBD_YMMqq_XMMq AVX2 INVALID +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXBQ AVX AVX VPMOVZXBQ_XMMdq_MEMw AVX INVALID +VPMOVZXBQ AVX AVX VPMOVZXBQ_XMMdq_XMMw AVX INVALID +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXBQ AVX2 AVX2 VPMOVZXBQ_YMMqq_MEMd AVX2 INVALID +VPMOVZXBQ AVX2 AVX2 VPMOVZXBQ_YMMqq_XMMd AVX2 INVALID +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXBW AVX AVX VPMOVZXBW_XMMdq_MEMq AVX INVALID +VPMOVZXBW AVX AVX VPMOVZXBW_XMMdq_XMMq AVX INVALID +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVZXBW AVX2 AVX2 VPMOVZXBW_YMMqq_MEMdq AVX2 INVALID +VPMOVZXBW AVX2 AVX2 VPMOVZXBW_YMMqq_XMMdq AVX2 INVALID +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVZXDQ AVX AVX VPMOVZXDQ_XMMdq_MEMq AVX INVALID +VPMOVZXDQ AVX AVX VPMOVZXDQ_XMMdq_XMMq AVX INVALID +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXDQ AVX2 AVX2 VPMOVZXDQ_YMMqq_MEMdq AVX2 INVALID +VPMOVZXDQ AVX2 AVX2 VPMOVZXDQ_YMMqq_XMMdq AVX2 INVALID +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXWD AVX AVX VPMOVZXWD_XMMdq_MEMq AVX INVALID +VPMOVZXWD AVX AVX VPMOVZXWD_XMMdq_XMMq AVX INVALID +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXWD AVX2 AVX2 VPMOVZXWD_YMMqq_MEMdq AVX2 INVALID +VPMOVZXWD AVX2 AVX2 VPMOVZXWD_YMMqq_XMMdq AVX2 INVALID +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXWQ AVX AVX VPMOVZXWQ_XMMdq_MEMd AVX INVALID +VPMOVZXWQ AVX AVX VPMOVZXWQ_XMMdq_XMMd AVX INVALID +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXWQ AVX2 AVX2 VPMOVZXWQ_YMMqq_MEMq AVX2 INVALID +VPMOVZXWQ AVX2 AVX2 VPMOVZXWQ_YMMqq_XMMq AVX2 INVALID +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMULDQ AVX AVX VPMULDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULDQ AVX AVX VPMULDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULDQ AVX512EVEX AVX512 VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMULDQ AVX2 AVX2 VPMULDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULDQ AVX2 AVX2 VPMULDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULDQ AVX512EVEX AVX512 VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMULHRSW AVX AVX VPMULHRSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULHRSW AVX AVX VPMULHRSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULHRSW AVX2 AVX2 VPMULHRSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULHRSW AVX2 AVX2 VPMULHRSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULHUW AVX AVX VPMULHUW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULHUW AVX AVX VPMULHUW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULHUW AVX512EVEX AVX512 VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHUW AVX512EVEX AVX512 VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULHUW AVX2 AVX2 VPMULHUW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULHUW AVX2 AVX2 VPMULHUW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULHUW AVX512EVEX AVX512 VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHUW AVX512EVEX AVX512 VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULHUW AVX512EVEX AVX512 VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHUW AVX512EVEX AVX512 VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULHW AVX AVX VPMULHW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULHW AVX AVX VPMULHW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULHW AVX512EVEX AVX512 VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHW AVX512EVEX AVX512 VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULHW AVX2 AVX2 VPMULHW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULHW AVX2 AVX2 VPMULHW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULHW AVX512EVEX AVX512 VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHW AVX512EVEX AVX512 VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULHW AVX512EVEX AVX512 VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHW AVX512EVEX AVX512 VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULLD AVX AVX VPMULLD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULLD AVX AVX VPMULLD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULLD AVX512EVEX AVX512 VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLD AVX512EVEX AVX512 VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMULLD AVX2 AVX2 VPMULLD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULLD AVX2 AVX2 VPMULLD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULLD AVX512EVEX AVX512 VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLD AVX512EVEX AVX512 VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMULLD AVX512EVEX AVX512 VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLD AVX512EVEX AVX512 VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMULLQ AVX512EVEX AVX512 VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLQ AVX512EVEX AVX512 VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VPMULLQ AVX512EVEX AVX512 VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLQ AVX512EVEX AVX512 VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VPMULLQ AVX512EVEX AVX512 VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLQ AVX512EVEX AVX512 VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VPMULLW AVX AVX VPMULLW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULLW AVX AVX VPMULLW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULLW AVX512EVEX AVX512 VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULLW AVX512EVEX AVX512 VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULLW AVX2 AVX2 VPMULLW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULLW AVX2 AVX2 VPMULLW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULLW AVX512EVEX AVX512 VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULLW AVX512EVEX AVX512 VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULLW AVX512EVEX AVX512 VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULLW AVX512EVEX AVX512 VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPMULUDQ AVX AVX VPMULUDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULUDQ AVX AVX VPMULUDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMULUDQ AVX2 AVX2 VPMULUDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULUDQ AVX2 AVX2 VPMULUDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 AVX512_BITALG_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512_BITALG_128 MASKOP_EVEX +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 AVX512_BITALG_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 AVX512_BITALG_256 MASKOP_EVEX +VPOPCNTB AVX512EVEX AVX512_BITALG VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512_BITALG_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTB AVX512EVEX AVX512_BITALG VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512_BITALG_512 MASKOP_EVEX +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512_VPOPCNTDQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512_VPOPCNTDQ_128 MASKOP_EVEX +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512_VPOPCNTDQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512_VPOPCNTDQ_256 MASKOP_EVEX +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512_VPOPCNTDQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512_VPOPCNTDQ_512 MASKOP_EVEX +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512_VPOPCNTDQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512_VPOPCNTDQ_128 MASKOP_EVEX +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512_VPOPCNTDQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512_VPOPCNTDQ_256 MASKOP_EVEX +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512_VPOPCNTDQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512_VPOPCNTDQ_512 MASKOP_EVEX +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 AVX512_BITALG_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512_BITALG_128 MASKOP_EVEX +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 AVX512_BITALG_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 AVX512_BITALG_256 MASKOP_EVEX +VPOPCNTW AVX512EVEX AVX512_BITALG VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512_BITALG_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTW AVX512EVEX AVX512_BITALG VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512_BITALG_512 MASKOP_EVEX +VPORD AVX512EVEX LOGICAL VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORD AVX512EVEX LOGICAL VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPORD AVX512EVEX LOGICAL VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORD AVX512EVEX LOGICAL VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPORD AVX512EVEX LOGICAL VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORD AVX512EVEX LOGICAL VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPORQ AVX512EVEX LOGICAL VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORQ AVX512EVEX LOGICAL VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPORQ AVX512EVEX LOGICAL VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORQ AVX512EVEX LOGICAL VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPORQ AVX512EVEX LOGICAL VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORQ AVX512EVEX LOGICAL VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPOR AVX LOGICAL VPOR_XMMdq_XMMdq_MEMdq AVX INVALID +VPOR AVX LOGICAL VPOR_XMMdq_XMMdq_XMMdq AVX INVALID +VPOR AVX2 LOGICAL VPOR_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPOR AVX2 LOGICAL VPOR_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPPERM XOP XOP VPPERM_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPPERM XOP XOP VPPERM_XMMdq_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPPERM XOP XOP VPPERM_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROLD AVX512EVEX AVX512 VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLD AVX512EVEX AVX512 VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPROLD AVX512EVEX AVX512 VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLD AVX512EVEX AVX512 VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPROLD AVX512EVEX AVX512 VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLD AVX512EVEX AVX512 VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPROLQ AVX512EVEX AVX512 VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLQ AVX512EVEX AVX512 VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPROLQ AVX512EVEX AVX512 VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLQ AVX512EVEX AVX512 VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPROLQ AVX512EVEX AVX512 VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLQ AVX512EVEX AVX512 VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPROLVD AVX512EVEX AVX512 VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVD AVX512EVEX AVX512 VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPROLVD AVX512EVEX AVX512 VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVD AVX512EVEX AVX512 VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPROLVD AVX512EVEX AVX512 VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVD AVX512EVEX AVX512 VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPROLVQ AVX512EVEX AVX512 VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVQ AVX512EVEX AVX512 VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPROLVQ AVX512EVEX AVX512 VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVQ AVX512EVEX AVX512 VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPROLVQ AVX512EVEX AVX512 VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVQ AVX512EVEX AVX512 VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPRORD AVX512EVEX AVX512 VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORD AVX512EVEX AVX512 VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPRORD AVX512EVEX AVX512 VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORD AVX512EVEX AVX512 VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPRORD AVX512EVEX AVX512 VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORD AVX512EVEX AVX512 VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPRORQ AVX512EVEX AVX512 VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORQ AVX512EVEX AVX512 VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPRORQ AVX512EVEX AVX512 VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORQ AVX512EVEX AVX512 VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPRORQ AVX512EVEX AVX512 VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORQ AVX512EVEX AVX512 VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPRORVD AVX512EVEX AVX512 VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVD AVX512EVEX AVX512 VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPRORVD AVX512EVEX AVX512 VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVD AVX512EVEX AVX512 VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPRORVD AVX512EVEX AVX512 VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVD AVX512EVEX AVX512 VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPRORVQ AVX512EVEX AVX512 VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVQ AVX512EVEX AVX512 VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPRORVQ AVX512EVEX AVX512 VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVQ AVX512EVEX AVX512 VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPRORVQ AVX512EVEX AVX512 VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVQ AVX512EVEX AVX512 VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPROTB XOP XOP VPROTB_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSADBW AVX AVX VPSADBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSADBW AVX AVX VPSADBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSADBW AVX512EVEX AVX512 VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 AVX512BW_128 DISP8_FULLMEM +VPSADBW AVX512EVEX AVX512 VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 AVX512BW_128 INVALID +VPSADBW AVX2 AVX2 VPSADBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSADBW AVX2 AVX2 VPSADBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSADBW AVX512EVEX AVX512 VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 AVX512BW_256 DISP8_FULLMEM +VPSADBW AVX512EVEX AVX512 VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 AVX512BW_256 INVALID +VPSADBW AVX512EVEX AVX512 VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 AVX512BW_512 DISP8_FULLMEM +VPSADBW AVX512EVEX AVX512 VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 AVX512BW_512 INVALID +VPSCATTERDD AVX512EVEX SCATTER VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDD AVX512EVEX SCATTER VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDD AVX512EVEX SCATTER VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDQ AVX512EVEX SCATTER VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDQ AVX512EVEX SCATTER VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDQ AVX512EVEX SCATTER VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQD AVX512EVEX SCATTER VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQD AVX512EVEX SCATTER VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQD AVX512EVEX SCATTER VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQQ AVX512EVEX SCATTER VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQQ AVX512EVEX SCATTER VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQQ AVX512EVEX SCATTER VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSHAB XOP XOP VPSHAB_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAB XOP XOP VPSHAB_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAB XOP XOP VPSHAB_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHAD XOP XOP VPSHAD_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAD XOP XOP VPSHAD_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAD XOP XOP VPSHAD_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHAQ XOP XOP VPSHAQ_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAQ XOP XOP VPSHAQ_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAQ XOP XOP VPSHAQ_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHAW XOP XOP VPSHAW_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAW XOP XOP VPSHAW_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAW XOP XOP VPSHAW_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLB XOP XOP VPSHLB_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLB XOP XOP VPSHLB_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLB XOP XOP VPSHLB_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLD XOP XOP VPSHLD_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLD XOP XOP VPSHLD_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLD XOP XOP VPSHLD_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLQ XOP XOP VPSHLQ_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLQ XOP XOP VPSHLQ_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLQ XOP XOP VPSHLQ_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLW XOP XOP VPSHLW_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLW XOP XOP VPSHLW_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLW XOP XOP VPSHLW_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 AVX512_BITALG_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 AVX512_BITALG_128 MASKOP_EVEX +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 AVX512_BITALG_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 AVX512_BITALG_256 MASKOP_EVEX +VPSHUFBITQMB AVX512EVEX AVX512_BITALG VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 AVX512_BITALG_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHUFBITQMB AVX512EVEX AVX512_BITALG VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 AVX512_BITALG_512 MASKOP_EVEX +VPSHUFB AVX AVX VPSHUFB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSHUFB AVX AVX VPSHUFB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSHUFB AVX512EVEX AVX512 VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFB AVX512EVEX AVX512 VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSHUFB AVX2 AVX2 VPSHUFB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSHUFB AVX2 AVX2 VPSHUFB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSHUFB AVX512EVEX AVX512 VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFB AVX512EVEX AVX512 VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSHUFB AVX512EVEX AVX512 VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFB AVX512EVEX AVX512 VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSHUFD AVX AVX VPSHUFD_XMMdq_MEMdq_IMMb AVX INVALID +VPSHUFD AVX AVX VPSHUFD_XMMdq_XMMdq_IMMb AVX INVALID +VPSHUFD AVX512EVEX AVX512 VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHUFD AVX512EVEX AVX512 VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSHUFD AVX2 AVX2 VPSHUFD_YMMqq_MEMqq_IMMb AVX2 INVALID +VPSHUFD AVX2 AVX2 VPSHUFD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSHUFD AVX512EVEX AVX512 VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHUFD AVX512EVEX AVX512 VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSHUFD AVX512EVEX AVX512 VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHUFD AVX512EVEX AVX512 VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSHUFHW AVX AVX VPSHUFHW_XMMdq_MEMdq_IMMb AVX INVALID +VPSHUFHW AVX AVX VPSHUFHW_XMMdq_XMMdq_IMMb AVX INVALID +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSHUFHW AVX2 AVX2 VPSHUFHW_YMMqq_MEMqq_IMMb AVX2 INVALID +VPSHUFHW AVX2 AVX2 VPSHUFHW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSHUFLW AVX AVX VPSHUFLW_XMMdq_MEMdq_IMMb AVX INVALID +VPSHUFLW AVX AVX VPSHUFLW_XMMdq_XMMdq_IMMb AVX INVALID +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSHUFLW AVX2 AVX2 VPSHUFLW_YMMqq_MEMqq_IMMb AVX2 INVALID +VPSHUFLW AVX2 AVX2 VPSHUFLW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSIGNB AVX AVX VPSIGNB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSIGNB AVX AVX VPSIGNB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSIGNB AVX2 AVX2 VPSIGNB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSIGNB AVX2 AVX2 VPSIGNB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSIGND AVX AVX VPSIGND_XMMdq_XMMdq_MEMdq AVX INVALID +VPSIGND AVX AVX VPSIGND_XMMdq_XMMdq_XMMdq AVX INVALID +VPSIGND AVX2 AVX2 VPSIGND_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSIGND AVX2 AVX2 VPSIGND_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSIGNW AVX AVX VPSIGNW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSIGNW AVX AVX VPSIGNW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSIGNW AVX2 AVX2 VPSIGNW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSIGNW AVX2 AVX2 VPSIGNW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSLLDQ AVX AVX VPSLLDQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 DISP8_FULLMEM +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 INVALID +VPSLLDQ AVX2 AVX2 VPSLLDQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 DISP8_FULLMEM +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 INVALID +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 DISP8_FULLMEM +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 INVALID +VPSLLD AVX AVX VPSLLD_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLD AVX AVX VPSLLD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSLLD AVX AVX VPSLLD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLD AVX2 AVX2 VPSLLD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLD AVX2 AVX2 VPSLLD_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSLLD AVX2 AVX2 VPSLLD_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLQ AVX AVX VPSLLQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLQ AVX AVX VPSLLQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPSLLQ AVX AVX VPSLLQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLQ AVX2 AVX2 VPSLLQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLQ AVX2 AVX2 VPSLLQ_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSLLQ AVX2 AVX2 VPSLLQ_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLVD AVX2 AVX2 VPSLLVD_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSLLVD AVX2 AVX2 VPSLLVD_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSLLVD AVX512EVEX AVX512 VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVD AVX512EVEX AVX512 VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLVD AVX2 AVX2 VPSLLVD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSLLVD AVX2 AVX2 VPSLLVD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSLLVD AVX512EVEX AVX512 VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVD AVX512EVEX AVX512 VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLVD AVX512EVEX AVX512 VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVD AVX512EVEX AVX512 VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLVQ AVX2 AVX2 VPSLLVQ_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSLLVQ AVX2 AVX2 VPSLLVQ_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLVQ AVX2 AVX2 VPSLLVQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSLLVQ AVX2 AVX2 VPSLLVQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLVW AVX512EVEX AVX512 VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLVW AVX512EVEX AVX512 VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSLLVW AVX512EVEX AVX512 VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLVW AVX512EVEX AVX512 VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSLLVW AVX512EVEX AVX512 VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLVW AVX512EVEX AVX512 VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSLLW AVX AVX VPSLLW_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLW AVX AVX VPSLLW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSLLW AVX AVX VPSLLW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_MEM128 +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSLLW AVX2 AVX2 VPSLLW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLW AVX2 AVX2 VPSLLW_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSLLW AVX2 AVX2 VPSLLW_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_MEM128 +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_MEM128 +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRAD AVX AVX VPSRAD_XMMdq_XMMdq_IMMb AVX INVALID +VPSRAD AVX AVX VPSRAD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRAD AVX AVX VPSRAD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAD AVX2 AVX2 VPSRAD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRAD AVX2 AVX2 VPSRAD_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRAD AVX2 AVX2 VPSRAD_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAVD AVX2 AVX2 VPSRAVD_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSRAVD AVX2 AVX2 VPSRAVD_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSRAVD AVX512EVEX AVX512 VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVD AVX512EVEX AVX512 VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAVD AVX2 AVX2 VPSRAVD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSRAVD AVX2 AVX2 VPSRAVD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSRAVD AVX512EVEX AVX512 VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVD AVX512EVEX AVX512 VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAVD AVX512EVEX AVX512 VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVD AVX512EVEX AVX512 VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAVW AVX512EVEX AVX512 VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAVW AVX512EVEX AVX512 VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRAVW AVX512EVEX AVX512 VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAVW AVX512EVEX AVX512 VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRAVW AVX512EVEX AVX512 VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAVW AVX512EVEX AVX512 VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRAW AVX AVX VPSRAW_XMMdq_XMMdq_IMMb AVX INVALID +VPSRAW AVX AVX VPSRAW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRAW AVX AVX VPSRAW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_MEM128 +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRAW AVX2 AVX2 VPSRAW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRAW AVX2 AVX2 VPSRAW_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRAW AVX2 AVX2 VPSRAW_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_MEM128 +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_MEM128 +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRLDQ AVX AVX VPSRLDQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 DISP8_FULLMEM +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 INVALID +VPSRLDQ AVX2 AVX2 VPSRLDQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 DISP8_FULLMEM +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 INVALID +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 DISP8_FULLMEM +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 INVALID +VPSRLD AVX AVX VPSRLD_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLD AVX AVX VPSRLD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRLD AVX AVX VPSRLD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLD AVX2 AVX2 VPSRLD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLD AVX2 AVX2 VPSRLD_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRLD AVX2 AVX2 VPSRLD_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLQ AVX AVX VPSRLQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLQ AVX AVX VPSRLQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRLQ AVX AVX VPSRLQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLQ AVX2 AVX2 VPSRLQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLQ AVX2 AVX2 VPSRLQ_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRLQ AVX2 AVX2 VPSRLQ_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLVD AVX2 AVX2 VPSRLVD_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSRLVD AVX2 AVX2 VPSRLVD_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSRLVD AVX512EVEX AVX512 VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVD AVX512EVEX AVX512 VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLVD AVX2 AVX2 VPSRLVD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSRLVD AVX2 AVX2 VPSRLVD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSRLVD AVX512EVEX AVX512 VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVD AVX512EVEX AVX512 VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLVD AVX512EVEX AVX512 VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVD AVX512EVEX AVX512 VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLVQ AVX2 AVX2 VPSRLVQ_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSRLVQ AVX2 AVX2 VPSRLVQ_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLVQ AVX2 AVX2 VPSRLVQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSRLVQ AVX2 AVX2 VPSRLVQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLVW AVX512EVEX AVX512 VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLVW AVX512EVEX AVX512 VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRLVW AVX512EVEX AVX512 VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLVW AVX512EVEX AVX512 VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRLVW AVX512EVEX AVX512 VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLVW AVX512EVEX AVX512 VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRLW AVX AVX VPSRLW_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLW AVX AVX VPSRLW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRLW AVX AVX VPSRLW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_MEM128 +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRLW AVX2 AVX2 VPSRLW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLW AVX2 AVX2 VPSRLW_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRLW AVX2 AVX2 VPSRLW_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_MEM128 +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_MEM128 +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBB AVX AVX VPSUBB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBB AVX AVX VPSUBB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBB AVX512EVEX AVX512 VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBB AVX512EVEX AVX512 VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBB AVX2 AVX2 VPSUBB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBB AVX2 AVX2 VPSUBB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBB AVX512EVEX AVX512 VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBB AVX512EVEX AVX512 VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBB AVX512EVEX AVX512 VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBB AVX512EVEX AVX512 VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBD AVX AVX VPSUBD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBD AVX AVX VPSUBD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBD AVX512EVEX AVX512 VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBD AVX512EVEX AVX512 VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSUBD AVX2 AVX2 VPSUBD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBD AVX2 AVX2 VPSUBD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBD AVX512EVEX AVX512 VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBD AVX512EVEX AVX512 VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSUBD AVX512EVEX AVX512 VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBD AVX512EVEX AVX512 VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSUBQ AVX AVX VPSUBQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBQ AVX AVX VPSUBQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBQ AVX512EVEX AVX512 VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBQ AVX512EVEX AVX512 VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSUBQ AVX2 AVX2 VPSUBQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBQ AVX2 AVX2 VPSUBQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBQ AVX512EVEX AVX512 VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBQ AVX512EVEX AVX512 VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSUBQ AVX512EVEX AVX512 VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBQ AVX512EVEX AVX512 VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSUBSB AVX AVX VPSUBSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBSB AVX AVX VPSUBSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBSB AVX512EVEX AVX512 VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSB AVX512EVEX AVX512 VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBSB AVX512EVEX AVX512 VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSB AVX512EVEX AVX512 VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBSB AVX2 AVX2 VPSUBSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBSB AVX2 AVX2 VPSUBSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBSB AVX512EVEX AVX512 VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSB AVX512EVEX AVX512 VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBSW AVX AVX VPSUBSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBSW AVX AVX VPSUBSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBSW AVX512EVEX AVX512 VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSW AVX512EVEX AVX512 VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBSW AVX512EVEX AVX512 VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSW AVX512EVEX AVX512 VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBSW AVX2 AVX2 VPSUBSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBSW AVX2 AVX2 VPSUBSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBSW AVX512EVEX AVX512 VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSW AVX512EVEX AVX512 VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBUSB AVX AVX VPSUBUSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBUSB AVX AVX VPSUBUSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBUSB AVX2 AVX2 VPSUBUSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBUSB AVX2 AVX2 VPSUBUSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBUSW AVX AVX VPSUBUSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBUSW AVX AVX VPSUBUSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBUSW AVX2 AVX2 VPSUBUSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBUSW AVX2 AVX2 VPSUBUSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBW AVX AVX VPSUBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBW AVX AVX VPSUBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBW AVX512EVEX AVX512 VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBW AVX512EVEX AVX512 VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBW AVX2 AVX2 VPSUBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBW AVX2 AVX2 VPSUBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBW AVX512EVEX AVX512 VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBW AVX512EVEX AVX512 VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBW AVX512EVEX AVX512 VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBW AVX512EVEX AVX512 VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPTEST AVX LOGICAL VPTEST_XMMdq_MEMdq AVX INVALID +VPTEST AVX LOGICAL VPTEST_XMMdq_XMMdq AVX INVALID +VPTEST AVX LOGICAL VPTEST_YMMqq_MEMqq AVX INVALID +VPTEST AVX LOGICAL VPTEST_YMMqq_YMMqq AVX INVALID +VPUNPCKHBW AVX AVX VPUNPCKHBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHBW AVX AVX VPUNPCKHBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKHBW AVX2 AVX2 VPUNPCKHBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHBW AVX2 AVX2 VPUNPCKHBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPUNPCKHDQ AVX AVX VPUNPCKHDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHDQ AVX AVX VPUNPCKHDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKHDQ AVX2 AVX2 VPUNPCKHDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHDQ AVX2 AVX2 VPUNPCKHDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKHQDQ AVX AVX VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHQDQ AVX AVX VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKHQDQ AVX2 AVX2 VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHQDQ AVX2 AVX2 VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKHWD AVX AVX VPUNPCKHWD_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHWD AVX AVX VPUNPCKHWD_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKHWD AVX2 AVX2 VPUNPCKHWD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHWD AVX2 AVX2 VPUNPCKHWD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPUNPCKLBW AVX AVX VPUNPCKLBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLBW AVX AVX VPUNPCKLBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKLBW AVX2 AVX2 VPUNPCKLBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLBW AVX2 AVX2 VPUNPCKLBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPUNPCKLDQ AVX AVX VPUNPCKLDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLDQ AVX AVX VPUNPCKLDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKLDQ AVX2 AVX2 VPUNPCKLDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLDQ AVX2 AVX2 VPUNPCKLDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKLQDQ AVX AVX VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLQDQ AVX AVX VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKLQDQ AVX2 AVX2 VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLQDQ AVX2 AVX2 VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKLWD AVX AVX VPUNPCKLWD_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLWD AVX AVX VPUNPCKLWD_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKLWD AVX2 AVX2 VPUNPCKLWD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLWD AVX2 AVX2 VPUNPCKLWD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPXORD AVX512EVEX LOGICAL VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORD AVX512EVEX LOGICAL VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPXORD AVX512EVEX LOGICAL VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORD AVX512EVEX LOGICAL VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPXORD AVX512EVEX LOGICAL VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORD AVX512EVEX LOGICAL VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPXORQ AVX512EVEX LOGICAL VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORQ AVX512EVEX LOGICAL VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPXORQ AVX512EVEX LOGICAL VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORQ AVX512EVEX LOGICAL VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPXORQ AVX512EVEX LOGICAL VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORQ AVX512EVEX LOGICAL VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPXOR AVX LOGICAL VPXOR_XMMdq_XMMdq_MEMdq AVX INVALID +VPXOR AVX LOGICAL VPXOR_XMMdq_XMMdq_XMMdq AVX INVALID +VPXOR AVX2 LOGICAL VPXOR_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPXOR AVX2 LOGICAL VPXOR_YMMqq_YMMqq_YMMqq AVX2 INVALID +VRANGEPD AVX512EVEX AVX512 VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPD AVX512EVEX AVX512 VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VRANGEPD AVX512EVEX AVX512 VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPD AVX512EVEX AVX512 VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VRANGEPD AVX512EVEX AVX512 VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPD AVX512EVEX AVX512 VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VRANGEPS AVX512EVEX AVX512 VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPS AVX512EVEX AVX512 VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VRANGEPS AVX512EVEX AVX512 VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPS AVX512EVEX AVX512 VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VRANGEPS AVX512EVEX AVX512 VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPS AVX512EVEX AVX512 VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VRANGESD AVX512EVEX AVX512 VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRANGESD AVX512EVEX AVX512 VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRANGESS AVX512EVEX AVX512 VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRANGESS AVX512EVEX AVX512 VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRCP14PD AVX512EVEX AVX512 VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PD AVX512EVEX AVX512 VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRCP14PD AVX512EVEX AVX512 VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PD AVX512EVEX AVX512 VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRCP14PD AVX512EVEX AVX512 VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PD AVX512EVEX AVX512 VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRCP14PS AVX512EVEX AVX512 VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PS AVX512EVEX AVX512 VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRCP14PS AVX512EVEX AVX512 VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PS AVX512EVEX AVX512 VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRCP14PS AVX512EVEX AVX512 VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PS AVX512EVEX AVX512 VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRCP14SD AVX512EVEX AVX512 VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRCP14SD AVX512EVEX AVX512 VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRCP14SS AVX512EVEX AVX512 VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRCP14SS AVX512EVEX AVX512 VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRCP28PD AVX512EVEX AVX512 VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRCP28PD AVX512EVEX AVX512 VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRCP28PS AVX512EVEX AVX512 VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRCP28PS AVX512EVEX AVX512 VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRCP28SD AVX512EVEX AVX512 VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRCP28SD AVX512EVEX AVX512 VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRCP28SS AVX512EVEX AVX512 VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRCP28SS AVX512EVEX AVX512 VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRCPPH AVX512EVEX FP16 VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRCPPH AVX512EVEX FP16 VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX +VRCPPH AVX512EVEX FP16 VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRCPPH AVX512EVEX FP16 VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX +VRCPPH AVX512EVEX FP16 VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRCPPH AVX512EVEX FP16 VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX +VRCPPS AVX AVX VRCPPS_XMMdq_MEMdq AVX INVALID +VRCPPS AVX AVX VRCPPS_XMMdq_XMMdq AVX INVALID +VRCPPS AVX AVX VRCPPS_YMMqq_MEMqq AVX INVALID +VRCPPS AVX AVX VRCPPS_YMMqq_YMMqq AVX INVALID +VRCPSH AVX512EVEX FP16 VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VRCPSH AVX512EVEX FP16 VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VRCPSS AVX AVX VRCPSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR +VRCPSS AVX AVX VRCPSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VREDUCESD AVX512EVEX AVX512 VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VREDUCESD AVX512EVEX AVX512 VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VREDUCESH AVX512EVEX FP16 VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VREDUCESH AVX512EVEX FP16 VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VREDUCESS AVX512EVEX AVX512 VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VREDUCESS AVX512EVEX AVX512 VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRNDSCALESD AVX512EVEX AVX512 VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRNDSCALESD AVX512EVEX AVX512 VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRNDSCALESH AVX512EVEX FP16 VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VRNDSCALESH AVX512EVEX FP16 VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRNDSCALESS AVX512EVEX AVX512 VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRNDSCALESS AVX512EVEX AVX512 VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VROUNDPD AVX AVX VROUNDPD_XMMdq_MEMdq_IMMb AVX MXCSR +VROUNDPD AVX AVX VROUNDPD_XMMdq_XMMdq_IMMb AVX MXCSR +VROUNDPD AVX AVX VROUNDPD_YMMqq_MEMqq_IMMb AVX MXCSR +VROUNDPD AVX AVX VROUNDPD_YMMqq_YMMqq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_XMMdq_MEMdq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_XMMdq_XMMdq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_YMMqq_MEMqq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_YMMqq_YMMqq_IMMb AVX MXCSR +VROUNDSD AVX AVX VROUNDSD_XMMdq_XMMdq_MEMq_IMMb AVX MXCSR:SIMD_SCALAR +VROUNDSD AVX AVX VROUNDSD_XMMdq_XMMdq_XMMq_IMMb AVX MXCSR:SIMD_SCALAR +VROUNDSS AVX AVX VROUNDSS_XMMdq_XMMdq_MEMd_IMMb AVX MXCSR:SIMD_SCALAR +VROUNDSS AVX AVX VROUNDSS_XMMdq_XMMdq_XMMd_IMMb AVX MXCSR:SIMD_SCALAR +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRSQRT14SD AVX512EVEX AVX512 VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRSQRT14SD AVX512EVEX AVX512 VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRSQRT14SS AVX512EVEX AVX512 VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRSQRT14SS AVX512EVEX AVX512 VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRSQRT28PD AVX512EVEX AVX512 VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRSQRT28PD AVX512EVEX AVX512 VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRSQRT28PS AVX512EVEX AVX512 VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRSQRT28PS AVX512EVEX AVX512 VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRSQRT28SD AVX512EVEX AVX512 VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRSQRT28SD AVX512EVEX AVX512 VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRSQRT28SS AVX512EVEX AVX512 VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRSQRT28SS AVX512EVEX AVX512 VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX +VRSQRTPS AVX AVX VRSQRTPS_XMMdq_MEMdq AVX INVALID +VRSQRTPS AVX AVX VRSQRTPS_XMMdq_XMMdq AVX INVALID +VRSQRTPS AVX AVX VRSQRTPS_YMMqq_MEMqq AVX INVALID +VRSQRTPS AVX AVX VRSQRTPS_YMMqq_YMMqq AVX INVALID +VRSQRTSH AVX512EVEX FP16 VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VRSQRTSH AVX512EVEX FP16 VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VRSQRTSS AVX AVX VRSQRTSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR +VRSQRTSS AVX AVX VRSQRTSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSCALEFSD AVX512EVEX AVX512 VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSCALEFSD AVX512EVEX AVX512 VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSCALEFSH AVX512EVEX FP16 VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VSCALEFSH AVX512EVEX FP16 VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSCALEFSS AVX512EVEX AVX512 VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSCALEFSS AVX512EVEX AVX512 VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSCATTERDPD AVX512EVEX SCATTER VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPD AVX512EVEX SCATTER VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPD AVX512EVEX SCATTER VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPS AVX512EVEX SCATTER VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPS AVX512EVEX SCATTER VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPS AVX512EVEX SCATTER VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERPF0DPD AVX512EVEX SCATTER VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF0DPS AVX512EVEX SCATTER VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF0QPD AVX512EVEX SCATTER VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF0QPS AVX512EVEX SCATTER VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1DPD AVX512EVEX SCATTER VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1DPS AVX512EVEX SCATTER VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1QPD AVX512EVEX SCATTER VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1QPS AVX512EVEX SCATTER VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERQPD AVX512EVEX SCATTER VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPD AVX512EVEX SCATTER VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPD AVX512EVEX SCATTER VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPS AVX512EVEX SCATTER VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPS AVX512EVEX SCATTER VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPS AVX512EVEX SCATTER VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFPD AVX AVX VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VSHUFPD AVX AVX VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VSHUFPD AVX512EVEX AVX512 VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPD AVX512EVEX AVX512 VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VSHUFPD AVX512EVEX AVX512 VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPD AVX512EVEX AVX512 VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFPD AVX AVX VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VSHUFPD AVX AVX VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VSHUFPD AVX512EVEX AVX512 VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPD AVX512EVEX AVX512 VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFPS AVX AVX VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VSHUFPS AVX AVX VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VSHUFPS AVX512EVEX AVX512 VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPS AVX512EVEX AVX512 VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VSHUFPS AVX512EVEX AVX512 VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPS AVX512EVEX AVX512 VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFPS AVX AVX VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VSHUFPS AVX AVX VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VSHUFPS AVX512EVEX AVX512 VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPS AVX512EVEX AVX512 VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSQRTPD AVX AVX VSQRTPD_XMMdq_MEMdq AVX MXCSR +VSQRTPD AVX AVX VSQRTPD_XMMdq_XMMdq AVX MXCSR +VSQRTPD AVX512EVEX AVX512 VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPD AVX512EVEX AVX512 VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSQRTPD AVX512EVEX AVX512 VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPD AVX512EVEX AVX512 VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSQRTPD AVX AVX VSQRTPD_YMMqq_MEMqq AVX MXCSR +VSQRTPD AVX AVX VSQRTPD_YMMqq_YMMqq AVX MXCSR +VSQRTPD AVX512EVEX AVX512 VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPD AVX512EVEX AVX512 VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VSQRTPS AVX AVX VSQRTPS_XMMdq_MEMdq AVX MXCSR +VSQRTPS AVX AVX VSQRTPS_XMMdq_XMMdq AVX MXCSR +VSQRTPS AVX512EVEX AVX512 VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPS AVX512EVEX AVX512 VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSQRTPS AVX512EVEX AVX512 VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPS AVX512EVEX AVX512 VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSQRTPS AVX AVX VSQRTPS_YMMqq_MEMqq AVX MXCSR +VSQRTPS AVX AVX VSQRTPS_YMMqq_YMMqq AVX MXCSR +VSQRTPS AVX512EVEX AVX512 VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPS AVX512EVEX AVX512 VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSQRTSD AVX AVX VSQRTSD_XMMdq_XMMdq_MEMq AVX MXCSR:SIMD_SCALAR +VSQRTSD AVX AVX VSQRTSD_XMMdq_XMMdq_XMMq AVX MXCSR:SIMD_SCALAR +VSQRTSD AVX512EVEX AVX512 VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSQRTSD AVX512EVEX AVX512 VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSQRTSH AVX512EVEX FP16 VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VSQRTSH AVX512EVEX FP16 VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSQRTSS AVX AVX VSQRTSS_XMMdq_XMMdq_MEMd AVX MXCSR:SIMD_SCALAR +VSQRTSS AVX AVX VSQRTSS_XMMdq_XMMdq_XMMd AVX MXCSR:SIMD_SCALAR +VSQRTSS AVX512EVEX AVX512 VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSQRTSS AVX512EVEX AVX512 VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSTMXCSR AVX AVX VSTMXCSR_MEMd AVX MXCSR_RD +VSUBPD AVX AVX VSUBPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VSUBPD AVX AVX VSUBPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VSUBPD AVX512EVEX AVX512 VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPD AVX512EVEX AVX512 VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSUBPD AVX512EVEX AVX512 VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPD AVX512EVEX AVX512 VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSUBPD AVX AVX VSUBPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VSUBPD AVX AVX VSUBPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VSUBPD AVX512EVEX AVX512 VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPD AVX512EVEX AVX512 VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VSUBPS AVX AVX VSUBPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VSUBPS AVX AVX VSUBPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VSUBPS AVX512EVEX AVX512 VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPS AVX512EVEX AVX512 VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSUBPS AVX512EVEX AVX512 VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPS AVX512EVEX AVX512 VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSUBPS AVX AVX VSUBPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VSUBPS AVX AVX VSUBPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VSUBPS AVX512EVEX AVX512 VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPS AVX512EVEX AVX512 VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSUBSD AVX AVX VSUBSD_XMMdq_XMMdq_MEMq AVX MXCSR:SIMD_SCALAR +VSUBSD AVX AVX VSUBSD_XMMdq_XMMdq_XMMq AVX MXCSR:SIMD_SCALAR +VSUBSD AVX512EVEX AVX512 VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSUBSD AVX512EVEX AVX512 VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSUBSH AVX512EVEX FP16 VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VSUBSH AVX512EVEX FP16 VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSUBSS AVX AVX VSUBSS_XMMdq_XMMdq_MEMd AVX MXCSR:SIMD_SCALAR +VSUBSS AVX AVX VSUBSS_XMMdq_XMMdq_XMMd AVX MXCSR:SIMD_SCALAR +VSUBSS AVX512EVEX AVX512 VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSUBSS AVX512EVEX AVX512 VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VTESTPD AVX LOGICAL_FP VTESTPD_XMMdq_MEMdq AVX INVALID +VTESTPD AVX LOGICAL_FP VTESTPD_XMMdq_XMMdq AVX INVALID +VTESTPD AVX LOGICAL_FP VTESTPD_YMMqq_MEMqq AVX INVALID +VTESTPD AVX LOGICAL_FP VTESTPD_YMMqq_YMMqq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_XMMdq_MEMdq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_XMMdq_XMMdq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_YMMqq_MEMqq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_YMMqq_YMMqq AVX INVALID +VUCOMISD AVX AVX VUCOMISD_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VUCOMISD AVX AVX VUCOMISD_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VUCOMISD AVX512EVEX AVX512 VUCOMISD_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VUCOMISD AVX512EVEX AVX512 VUCOMISD_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VUCOMISH AVX512EVEX FP16 VUCOMISH_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MXCSR:SIMD_SCALAR +VUCOMISH AVX512EVEX FP16 VUCOMISH_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VUCOMISS AVX AVX VUCOMISS_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VUCOMISS AVX AVX VUCOMISS_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VUCOMISS AVX512EVEX AVX512 VUCOMISS_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VUCOMISS AVX512EVEX AVX512 VUCOMISS_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VUNPCKHPD AVX AVX VUNPCKHPD_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKHPD AVX AVX VUNPCKHPD_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKHPD AVX AVX VUNPCKHPD_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKHPD AVX AVX VUNPCKHPD_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VUNPCKHPS AVX AVX VUNPCKHPS_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKHPS AVX AVX VUNPCKHPS_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKHPS AVX AVX VUNPCKHPS_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKHPS AVX AVX VUNPCKHPS_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VUNPCKLPD AVX AVX VUNPCKLPD_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKLPD AVX AVX VUNPCKLPD_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKLPD AVX AVX VUNPCKLPD_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKLPD AVX AVX VUNPCKLPD_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VUNPCKLPS AVX AVX VUNPCKLPS_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKLPS AVX AVX VUNPCKLPS_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKLPS AVX AVX VUNPCKLPS_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKLPS AVX AVX VUNPCKLPS_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VXORPD AVX LOGICAL_FP VXORPD_XMMdq_XMMdq_MEMdq AVX INVALID +VXORPD AVX LOGICAL_FP VXORPD_XMMdq_XMMdq_XMMdq AVX INVALID +VXORPD AVX512EVEX LOGICAL_FP VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPD AVX512EVEX LOGICAL_FP VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VXORPD AVX LOGICAL_FP VXORPD_YMMqq_YMMqq_MEMqq AVX INVALID +VXORPD AVX LOGICAL_FP VXORPD_YMMqq_YMMqq_YMMqq AVX INVALID +VXORPD AVX512EVEX LOGICAL_FP VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPD AVX512EVEX LOGICAL_FP VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VXORPD AVX512EVEX LOGICAL_FP VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPD AVX512EVEX LOGICAL_FP VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VXORPS AVX LOGICAL_FP VXORPS_XMMdq_XMMdq_MEMdq AVX INVALID +VXORPS AVX LOGICAL_FP VXORPS_XMMdq_XMMdq_XMMdq AVX INVALID +VXORPS AVX512EVEX LOGICAL_FP VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPS AVX512EVEX LOGICAL_FP VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VXORPS AVX LOGICAL_FP VXORPS_YMMqq_YMMqq_MEMqq AVX INVALID +VXORPS AVX LOGICAL_FP VXORPS_YMMqq_YMMqq_YMMqq AVX INVALID +VXORPS AVX512EVEX LOGICAL_FP VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPS AVX512EVEX LOGICAL_FP VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VXORPS AVX512EVEX LOGICAL_FP VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPS AVX512EVEX LOGICAL_FP VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VZEROALL AVX AVX VZEROALL AVX XMM_STATE_W +VZEROUPPER AVX AVX VZEROUPPER AVX XMM_STATE_W:NOTSX +WBINVD BASE SYSTEM WBINVD I486REAL RING0:NOTSX +WBNOINVD WBNOINVD SYSTEM WBNOINVD WBNOINVD RING0:NOTSX +WRFSBASE RDWRFSGS RDWRFSGS WRFSBASE_GPRy RDWRFSGS NOTSX:SCALABLE +WRGSBASE RDWRFSGS RDWRFSGS WRGSBASE_GPRy RDWRFSGS NOTSX:SCALABLE +WRMSR BASE SYSTEM WRMSR PENTIUMREAL RING0:NOTSX +WRPKRU PKU PKU WRPKRU PKU INVALID +WRSSD CET CET WRSSD_MEMu32_GPR32u32 CET INVALID +WRSSQ CET CET WRSSQ_MEMu64_GPR64u64 CET INVALID +WRUSSD CET CET WRUSSD_MEMu32_GPR32u32 CET INVALID +WRUSSQ CET CET WRUSSQ_MEMu64_GPR64u64 CET INVALID +XABORT RTM UNCOND_BR XABORT_IMMb RTM INVALID +XADD BASE SEMAPHORE XADD_GPR8_GPR8 I486REAL BYTEOP +XADD BASE SEMAPHORE XADD_GPRv_GPRv I486REAL SCALABLE +XADD_LOCK BASE SEMAPHORE XADD_LOCK_MEMb_GPR8 I486REAL BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XADD_LOCK BASE SEMAPHORE XADD_LOCK_MEMv_GPRv I486REAL LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XADD BASE SEMAPHORE XADD_MEMb_GPR8 I486REAL BYTEOP:LOCKABLE +XADD BASE SEMAPHORE XADD_MEMv_GPRv I486REAL LOCKABLE:SCALABLE +XBEGIN RTM COND_BR XBEGIN_RELBRz RTM SCALABLE +XCHG BASE DATAXFER XCHG_GPR8_GPR8 I86 BYTEOP +XCHG BASE DATAXFER XCHG_GPRv_GPRv I86 SCALABLE +XCHG BASE DATAXFER XCHG_GPRv_OrAX I86 SCALABLE +XCHG BASE DATAXFER XCHG_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XCHG BASE DATAXFER XCHG_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XEND RTM COND_BR XEND RTM INVALID +XGETBV XSAVE XSAVE XGETBV XSAVE INVALID +XLAT BASE MISC XLAT I86 FIXED_BASE0 +XORPD SSE2 LOGICAL_FP XORPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +XORPD SSE2 LOGICAL_FP XORPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +XORPS SSE LOGICAL_FP XORPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +XORPS SSE LOGICAL_FP XORPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +XOR BASE LOGICAL XOR_AL_IMMb I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_GPR8_30 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_GPR8_32 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_IMMb_80r6 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_IMMb_82r6 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_MEMb I86 BYTEOP +XOR BASE LOGICAL XOR_GPRv_GPRv_31 I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_GPRv_33 I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_IMMb I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_IMMz I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_MEMv I86 SCALABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMb_IMMb_80r6 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMb_IMMb_82r6 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XOR BASE LOGICAL XOR_MEMb_GPR8 I86 BYTEOP:LOCKABLE +XOR BASE LOGICAL XOR_MEMb_IMMb_80r6 I86 BYTEOP:LOCKABLE +XOR BASE LOGICAL XOR_MEMb_IMMb_82r6 I86 BYTEOP:LOCKABLE +XOR BASE LOGICAL XOR_MEMv_GPRv I86 LOCKABLE:SCALABLE +XOR BASE LOGICAL XOR_MEMv_IMMb I86 LOCKABLE:SCALABLE +XOR BASE LOGICAL XOR_MEMv_IMMz I86 LOCKABLE:SCALABLE +XOR BASE LOGICAL XOR_OrAX_IMMz I86 SCALABLE +XRESLDTRK TSX_LDTRK TSX_LDTRK XRESLDTRK TSX_LDTRK INVALID +XRSTOR64 XSAVE XSAVE XRSTOR64_MEMmxsave XSAVE XMM_STATE_CW:REQUIRES_ALIGNMENT:X87_MMX_STATE_CW:NOTSX:SPECIAL_AGEN_REQUIRED +XRSTORS64 XSAVES XSAVE XRSTORS64_MEMmxsave XSAVES XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:NOTSX:SPECIAL_AGEN_REQUIRED +XRSTORS XSAVES XSAVE XRSTORS_MEMmxsave XSAVES XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:NOTSX:SPECIAL_AGEN_REQUIRED +XRSTOR XSAVE XSAVE XRSTOR_MEMmxsave XSAVE XMM_STATE_CW:REQUIRES_ALIGNMENT:X87_MMX_STATE_CW:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVE64 XSAVE XSAVE XSAVE64_MEMmxsave XSAVE XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVEC64 XSAVEC XSAVE XSAVEC64_MEMmxsave XSAVEC XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVEC XSAVEC XSAVE XSAVEC_MEMmxsave XSAVEC XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVEOPT64 XSAVEOPT XSAVEOPT XSAVEOPT64_MEMmxsave XSAVEOPT XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX +XSAVEOPT XSAVEOPT XSAVEOPT XSAVEOPT_MEMmxsave XSAVEOPT XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX +XSAVES64 XSAVES XSAVE XSAVES64_MEMmxsave XSAVES XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVES XSAVES XSAVE XSAVES_MEMmxsave XSAVES XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVE XSAVE XSAVE XSAVE_MEMmxsave XSAVE XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSETBV XSAVE XSAVE XSETBV XSAVE RING0:NOTSX +XSTORE VIA_PADLOCK_RNG VIA_PADLOCK XSTORE VIA_PADLOCK_RNG SCALABLE +XSUSLDTRK TSX_LDTRK TSX_LDTRK XSUSLDTRK TSX_LDTRK INVALID +XTEST RTM LOGICAL XTEST RTM INVALID diff --git a/CodeVirtualizer/build/obj/ild_debug.txt b/CodeVirtualizer/build/obj/ild_debug.txt new file mode 100644 index 0000000..9be2e6f --- /dev/null +++ b/CodeVirtualizer/build/obj/ild_debug.txt @@ -0,0 +1,229 @@ +state_space: + {'MODE': [0, 1, 2], 'EASZ': [1, 2, 3], 'SMODE': [0, 1, 2], 'EOSZ': [0, 1, 2, 3], 'MOD': [0, 1, 2, 3], 'REX': [0, 1], 'REXW': [0, 1], 'REXB': [0, 1], 'REXR': [0, 1], 'REXX': [0, 1], 'REP': [0, 2, 3], 'OSZ': [0, 1], 'ASZ': [0, 1], 'LOCK': [0, 1], 'DEFAULT_SEG': [0, 1, 2], 'SEG_OVD': [0, 1, 2, 3, 4, 5, 6], 'DF64': [0, 1], 'ENCODER_PREFERRED': [1], 'NO_RETURN': [1], 'DUMMY': [0], 'MAP': [0, 1, 2, 3, 5, 6, 8, 9, 10], 'VEXVALID': [0, 1, 2, 3, 4], 'VL': [0, 1, 2, 3], 'VEX_PREFIX': [0, 1, 2, 3], 'VEXDEST3': [1], 'VEXDEST210': [7], 'BCAST': [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27], 'VEXDEST4': [0], 'REXRR': [0]}EOSZ NTS: +IMMUNE66_LOOP64 +IMMUNE66 +DF64 +IGNORE66 +IMMUNE_REXW +CR_WIDTH +FORCE64 +OSZ_NONTERM +REFINING66 + +EASZ NTS: +ASZ_NONTERM + +IMMNTS: +UIMM16 +UIMM32 +UIMMv +SE_IMM8 +SIMMz +UIMM8 +SIMM8 + +DISP NTS: +MEMDISPv +MEMDISP16 +MEMDISP32 +MEMDISP +MEMDISP8 +SIB_BASE0 + +BRDISP NTS: +BRDISP32 +BRDISPz +BRDISP8 + +NESTED NTS: +GPRz_B +VSIB_YMM +VGPRy_N +SIB +MODRM32 +AVX_SPLITTER +XMM_B3 +UISA_VSIB_ZMM +XMM_N +YMM_R3 +VGPR32_N +ZMM_R3 +UISA_VMODRM_YMM +FINAL_SSEG +GPRy_B +ISA +YMM_R +VGPRy_R +GPRz_R +XMM_R3 +XMM_R +MASK_N +MODRM16 +A_GPR_R +VGPRy_B +VSIB_XMM +A_GPR_B +XMM_SE +YMM_N +VGPR32_B +GPRv_R +VMODRM_YMM +UISA_VMODRM_XMM +YMM_B3 +YMM_B +VGPR32_R +FINAL_DSEG +FINAL_DSEG1 +MODRM +XMM_B +EVEX_SPLITTER +UISA_VSIB_BASE +VSIB_BASE +ZMM_N3 +UISA_VSIB_XMM +YMM_N3 +GPRv_B +XMM_N3 +UISA_VMODRM_ZMM +GPRy_R +VMODRM_XMM +UISA_VSIB_YMM +MODRM64alt32 +YMM_SE +GPRv_SB +ZMM_B3 +SIB_BASE0 +ALL_STATE_SPACE: +MODE: {0: True, 1: True, 2: True} +MODE_FIRST_PREFIX: {0: True, 1: True} +REP: {0: True, 3: True, 2: True} +HINT: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True} +EASZ: {1: True, 2: True, 3: True} +SMODE: {0: True, 1: True, 2: True} +EOSZ: {1: True, 2: True, 3: True} +REG: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True} +RM: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True} +REXR: {0: True, 1: True} +REXB: {0: True, 1: True} +SRM: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True} +REXX: {0: True, 1: True} +SIBINDEX: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True} +SEG_OVD: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True} +REX: {0: True, 1: True} +OSZ: {0: True, 1: True} +REXW: {0: True, 1: True} +ASZ: {0: True, 1: True} +NEED_MEMDISP: {0: True, 8: True, 16: True, 32: True} +MOD: {0: True, 1: True, 2: True, 3: True} +SIBSCALE: {0: True, 1: True, 2: True, 3: True} +SIBBASE: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True} +VEXVALID: {3: True, 0: True, 1: True, 2: True} +ESRC: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True, 8: True, 9: True, 10: True, 11: True, 12: True, 13: True, 14: True, 15: True} +VEXDEST210: {7: True, 6: True, 5: True, 4: True, 3: True, 2: True, 1: True, 0: True} +VEXDEST3: {1: True, 0: True} +VL: {0: True, 1: True, 2: True, 3: True} +LLRC: {0: True, 1: True, 2: True, 3: True} +BCRC: {1: True, 0: True} +ELEMENT_SIZE: {64: True, 1: True, 2: True, 4: True, 8: True, 16: True, 32: True, 128: True, 256: True, 512: True} +VEXDEST4: {0: True, 1: True} +MASK: {0: True, 1: True, 2: True, 3: True, 4: True, 5: True, 6: True, 7: True} +REXRR: {0: True, 1: True} +LOCK: {1: True, 0: True} +P4: {0: True, 1: True} +MPXMODE: {1: True, 0: True} +CET: {0: True, 1: True} +CLDEMOTE: {0: True, 1: True} +MODEP5: {1: True, 0: True} +MODE_SHORT_UD0: {1: True, 0: True} +TZCNT: {1: True, 0: True} +LZCNT: {1: True, 0: True} +WBNOINVD: {0: True, 1: True} +VEX_PREFIX: {0: True, 1: True, 2: True, 3: True} +MAP: {8: True, 9: True, 10: True, 3: True, 1: True, 2: True, 5: True, 6: True} +ZEROING: {0: True, 1: True} +ALL_OPS_WIDTHS: +MODE: 2 +MODE_FIRST_PREFIX: 1 +REP: 2 +HINT: 3 +EASZ: 2 +SMODE: 2 +EOSZ: 2 +REG: 3 +RM: 3 +REXR: 1 +REXB: 1 +SRM: 3 +REXX: 1 +SIBINDEX: 3 +SEG_OVD: 3 +REX: 1 +OSZ: 1 +REXW: 1 +ASZ: 1 +NEED_MEMDISP: 6 +MOD: 2 +SIBSCALE: 2 +SIBBASE: 3 +VEXVALID: 3 +ESRC: 4 +VEXDEST210: 3 +VEXDEST3: 1 +VL: 2 +LLRC: 2 +BCRC: 1 +ELEMENT_SIZE: 9 +VEXDEST4: 1 +MASK: 3 +REXRR: 1 +LOCK: 1 +P4: 1 +MPXMODE: 1 +CET: 1 +CLDEMOTE: 1 +MODEP5: 1 +MODE_SHORT_UD0: 1 +TZCNT: 1 +LZCNT: 1 +WBNOINVD: 1 +VEX_PREFIX: 2 +MAP: 4 +ZEROING: 1 +MOD3: 1 +VEXDEST210_7: 1 +RM4: 1 +MASK_NOT0: 1 +MASK_ZERO: 1 +UIMM0: 8 +incomplete opcode for iclass POP, pttrn 0b0101_1 SRM[rrr] DF64() +Expanding opcode for POP +incomplete opcode for iclass INC, pttrn 0b0100_0 SRM[rrr] not64 +Expanding opcode for INC +incomplete opcode for iclass DEC, pttrn 0b0100_1 SRM[rrr] not64 +Expanding opcode for DEC +incomplete opcode for iclass PUSH, pttrn 0b0101_0 SRM[rrr] DF64() +Expanding opcode for PUSH +incomplete opcode for iclass MOV, pttrn 0b1011_0 SRM[rrr] UIMM8() +Expanding opcode for MOV +incomplete opcode for iclass MOV, pttrn 0b1011_1 SRM[rrr] UIMMv() +Expanding opcode for MOV +incomplete opcode for iclass NOP, pttrn 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix +incomplete opcode for iclass NOP, pttrn 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0 +incomplete opcode for iclass XCHG, pttrn 0b1001_0 SRM[rrr] SRM!=0 +Expanding opcode for XCHG +incomplete opcode for iclass XCHG, pttrn 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix +Expanding opcode for XCHG +incomplete opcode for iclass PAUSE, pttrn 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1 +incomplete opcode for iclass BSWAP, pttrn 0x0F 0b1100_1 SRM[rrr] +Expanding opcode for BSWAP +EOSZ SEQS: [['OSZ_NONTERM', 'REFINING66'], ['OSZ_NONTERM', 'DF64', 'FORCE64'], ['OSZ_NONTERM', 'IGNORE66'], ['OSZ_NONTERM', 'REFINING66', 'CR_WIDTH'], ['OSZ_NONTERM', 'DF64', 'IMMUNE66_LOOP64'], ['OSZ_NONTERM', 'CR_WIDTH'], ['OSZ_NONTERM'], ['OSZ_NONTERM', 'IMMUNE_REXW'], ['OSZ_NONTERM', 'IMMUNE66'], ['OSZ_NONTERM', 'DF64'], ['OSZ_NONTERM', 'FORCE64']] +EASZ SEQS: [['ASZ_NONTERM']] +IMM SEQS: [['SIMMz'], ['SIMM8'], ['UIMM16', 'UIMM8_1'], ['UIMMv'], ['SE_IMM8'], ['UIMM32'], [], ['UIMM16'], ['UIMM8', 'UIMM8_1'], ['UIMM8']] +DISP SEQS: [['MEMDISPv'], ['BRDISP32'], ['BRDISPz'], [], ['BRDISP8']] +DISP NTs: ['MEMDISPv'] +BRDISP NTs: ['BRDISP32', 'BRDISPz', 'BRDISP8'] +vv0 cnames: {'MOD3', 'MODE_SHORT_UD0', 'OSZ', 'SRM', 'CET', 'REP', 'MOD', 'P4', 'MODEP5', 'WBNOINVD', 'EASZ', 'RM', 'MPXMODE', 'CLDEMOTE', 'MODE', 'LOCK', 'LZCNT', 'REG', 'REXB', 'TZCNT', 'REXW'} +vv1 cnames: {'EASZ', 'RM', 'MODE', 'MOD3', 'VL', 'VEXDEST3', 'REG', 'VEX_PREFIX', 'VEXDEST210_7', 'REXW', 'RM4'} +vv2 cnames: {'REXRR', 'ZEROING', 'MOD3', 'VL', 'VEXDEST210_7', 'VEXDEST4', 'EASZ', 'BCRC', 'MODE', 'MASK_ZERO', 'VEXDEST3', 'REG', 'VEX_PREFIX', 'REXW', 'RM4'} +vv3 cnames: {'MODE', 'MOD3', 'VL', 'VEXDEST3', 'REG', 'VEX_PREFIX', 'VEXDEST210_7', 'REXW'} +all cnames: {'REXRR', 'ZEROING', 'VL', 'MODE_SHORT_UD0', 'SRM', 'CET', 'VEXDEST210_7', 'VEXDEST4', 'WBNOINVD', 'RM', 'BCRC', 'MASK_ZERO', 'LOCK', 'LZCNT', 'REG', 'REXB', 'MODEP5', 'RM4', 'MOD3', 'OSZ', 'REP', 'MOD', 'P4', 'EASZ', 'MPXMODE', 'CLDEMOTE', 'MODE', 'VEXDEST3', 'VEX_PREFIX', 'TZCNT', 'REXW'} diff --git a/CodeVirtualizer/build/obj/ild_easz_debug.txt b/CodeVirtualizer/build/obj/ild_easz_debug.txt new file mode 100644 index 0000000..a0f063c --- /dev/null +++ b/CodeVirtualizer/build/obj/ild_easz_debug.txt @@ -0,0 +1,36 @@ +/// @file ild_easz_debug.txt + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +/*Array declaration*/ +xed_bits_t xed_lookup_ASZ_NONTERM_EASZ[3][2]; + +/*Array initialization*/ +void xed_lookup_function_init_ASZ_NONTERM_EASZ(void) +{ +xed_lookup_ASZ_NONTERM_EASZ[0][0]=0x1; +xed_lookup_ASZ_NONTERM_EASZ[0][1]=0x2; +xed_lookup_ASZ_NONTERM_EASZ[1][0]=0x2; +xed_lookup_ASZ_NONTERM_EASZ[1][1]=0x1; +xed_lookup_ASZ_NONTERM_EASZ[2][0]=0x3; +xed_lookup_ASZ_NONTERM_EASZ[2][1]=0x2; +} diff --git a/CodeVirtualizer/build/obj/ild_easz_debug_header.txt b/CodeVirtualizer/build/obj/ild_easz_debug_header.txt new file mode 100644 index 0000000..ffd5ba2 --- /dev/null +++ b/CodeVirtualizer/build/obj/ild_easz_debug_header.txt @@ -0,0 +1,37 @@ +/// @file ild_easz_debug_header.txt + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_lookup_function_init_ASZ_NONTERM_EASZ(void); + +/*Array declaration*/ +extern xed_bits_t xed_lookup_ASZ_NONTERM_EASZ[3][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_ASZ_NONTERM_EASZ(xed_bits_t arg_MODE, xed_bits_t arg_ASZ) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_ASZ>=0 && arg_ASZ<2); +_v=xed_lookup_ASZ_NONTERM_EASZ[arg_MODE][arg_ASZ]; +return _v; +} diff --git a/CodeVirtualizer/build/obj/ild_eosz_debug.txt b/CodeVirtualizer/build/obj/ild_eosz_debug.txt new file mode 100644 index 0000000..8569a84 --- /dev/null +++ b/CodeVirtualizer/build/obj/ild_eosz_debug.txt @@ -0,0 +1,113 @@ +/// @file ild_eosz_debug.txt + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +/*Array declaration*/ +xed_bits_t xed_lookup_IMMUNE66_EOSZ[3][2]; + +/*Array initialization*/ +void xed_lookup_function_init_IMMUNE66_EOSZ(void) +{ +xed_lookup_IMMUNE66_EOSZ[0][0]=0x2; +xed_lookup_IMMUNE66_EOSZ[0][1]=0x2; +xed_lookup_IMMUNE66_EOSZ[1][0]=0x2; +xed_lookup_IMMUNE66_EOSZ[1][1]=0x2; +xed_lookup_IMMUNE66_EOSZ[2][0]=0x2; +xed_lookup_IMMUNE66_EOSZ[2][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_DF64_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_DF64_EOSZ(void) +{ +xed_lookup_DF64_EOSZ[2][1][0]=0x1; +xed_lookup_DF64_EOSZ[2][0][0]=0x3; +xed_lookup_DF64_EOSZ[2][1][1]=0x3; +xed_lookup_DF64_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_IGNORE66_EOSZ[3][2]; + +/*Array initialization*/ +void xed_lookup_function_init_IGNORE66_EOSZ(void) +{ +xed_lookup_IGNORE66_EOSZ[0][0]=0x1; +xed_lookup_IGNORE66_EOSZ[0][1]=0x1; +xed_lookup_IGNORE66_EOSZ[1][0]=0x2; +xed_lookup_IGNORE66_EOSZ[1][1]=0x2; +xed_lookup_IGNORE66_EOSZ[2][0]=0x2; +xed_lookup_IGNORE66_EOSZ[2][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_IMMUNE_REXW_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_IMMUNE_REXW_EOSZ(void) +{ +xed_lookup_IMMUNE_REXW_EOSZ[2][0][1]=0x2; +xed_lookup_IMMUNE_REXW_EOSZ[2][0][0]=0x2; +xed_lookup_IMMUNE_REXW_EOSZ[2][1][1]=0x2; +xed_lookup_IMMUNE_REXW_EOSZ[2][1][0]=0x1; +} +/*Array declaration*/ +xed_bits_t xed_lookup_CR_WIDTH_EOSZ[3]; + +/*Array initialization*/ +void xed_lookup_function_init_CR_WIDTH_EOSZ(void) +{ +xed_lookup_CR_WIDTH_EOSZ[0]=0x2; +xed_lookup_CR_WIDTH_EOSZ[1]=0x2; +xed_lookup_CR_WIDTH_EOSZ[2]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[2][1][0]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[2][0][0]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_REFINING66_EOSZ[3][2]; + +/*Array initialization*/ +void xed_lookup_function_init_REFINING66_EOSZ(void) +{ +xed_lookup_REFINING66_EOSZ[0][0]=0x1; +xed_lookup_REFINING66_EOSZ[0][1]=0x1; +xed_lookup_REFINING66_EOSZ[1][0]=0x2; +xed_lookup_REFINING66_EOSZ[1][1]=0x2; +xed_lookup_REFINING66_EOSZ[2][0]=0x2; +xed_lookup_REFINING66_EOSZ[2][1]=0x3; +} diff --git a/CodeVirtualizer/build/obj/ild_eosz_debug_header.txt b/CodeVirtualizer/build/obj/ild_eosz_debug_header.txt new file mode 100644 index 0000000..6ddd683 --- /dev/null +++ b/CodeVirtualizer/build/obj/ild_eosz_debug_header.txt @@ -0,0 +1,135 @@ +/// @file ild_eosz_debug_header.txt + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_lookup_function_init_IMMUNE66_EOSZ(void); + +void xed_lookup_function_init_DF64_EOSZ(void); + +void xed_lookup_function_init_IGNORE66_EOSZ(void); + +void xed_lookup_function_init_IMMUNE_REXW_EOSZ(void); + +void xed_lookup_function_init_CR_WIDTH_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_EOSZ(void); + +void xed_lookup_function_init_REFINING66_EOSZ(void); + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_IMMUNE66_LOOP64_EOSZ(void) +{ +/*Constant function*/ +return 0x3; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_IMMUNE66_EOSZ[3][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_IMMUNE66_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_IMMUNE66_EOSZ[arg_MODE][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_DF64_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_DF64_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_DF64_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_IGNORE66_EOSZ[3][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_IGNORE66_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_IGNORE66_EOSZ[arg_MODE][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_IMMUNE_REXW_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_IMMUNE_REXW_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_IMMUNE_REXW_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_CR_WIDTH_EOSZ[3]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_CR_WIDTH_EOSZ(xed_bits_t arg_MODE) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +_v=xed_lookup_CR_WIDTH_EOSZ[arg_MODE]; +return _v; +} +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_FORCE64_EOSZ(void) +{ +/*Constant function*/ +return 0x3; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_REFINING66_EOSZ[3][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_REFINING66_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_REFINING66_EOSZ[arg_MODE][arg_REXW]; +return _v; +} diff --git a/CodeVirtualizer/build/obj/include-private/xed-chip-features-table.h b/CodeVirtualizer/build/obj/include-private/xed-chip-features-table.h new file mode 100644 index 0000000..56e3f9b --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-chip-features-table.h @@ -0,0 +1,31 @@ +/// @file xed-chip-features-table.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CHIP_FEATURES_TABLE_H) +# define XED_CHIP_FEATURES_TABLE_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-isa-set-enum.h" +#include "xed-chip-enum.h" +extern xed_uint64_t xed_chip_features[XED_CHIP_LAST][5]; +extern xed_bool_t xed_chip_supports_avx512[XED_CHIP_LAST]; +void xed_init_chip_model_info(void); +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-enc-groups.h b/CodeVirtualizer/build/obj/include-private/xed-enc-groups.h new file mode 100644 index 0000000..ca62981 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-enc-groups.h @@ -0,0 +1,561 @@ +/// @file xed-enc-groups.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENC_GROUPS_H) +# define XED_ENC_GROUPS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +xed_bool_t xed_encode_group_0(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_1(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_2(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_3(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_4(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_5(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_6(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_7(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_8(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_9(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_10(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_11(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_12(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_13(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_14(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_15(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_16(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_17(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_18(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_19(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_20(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_21(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_22(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_23(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_24(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_25(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_26(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_27(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_28(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_29(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_30(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_31(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_32(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_33(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_34(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_35(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_36(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_37(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_38(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_39(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_40(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_41(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_42(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_43(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_44(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_45(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_46(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_47(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_48(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_49(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_50(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_51(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_52(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_53(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_54(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_55(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_56(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_57(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_58(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_59(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_60(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_61(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_62(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_63(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_64(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_65(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_66(xed_encoder_request_t* xes); +xed_bool_t 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xed_encode_group_275(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_276(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_277(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_278(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_279(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_280(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_281(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_282(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_283(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_284(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_285(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_286(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_287(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_288(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_289(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_290(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_291(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_292(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_293(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_294(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_295(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_296(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_297(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_298(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_299(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_300(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_301(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_302(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_303(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_304(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_305(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_306(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_307(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_308(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_309(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_310(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_311(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_312(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_313(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_314(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_315(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_316(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_317(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_318(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_319(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_320(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_321(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_322(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_323(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_324(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_325(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_326(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_327(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_328(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_329(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_330(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_331(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_332(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_333(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_334(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_335(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_336(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_337(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_338(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_339(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_340(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_341(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_342(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_343(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_344(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_345(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_346(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_347(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_348(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_349(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_350(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_351(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_352(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_353(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_354(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_355(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_356(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_357(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_358(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_359(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_360(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_361(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_362(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_363(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_364(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_365(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_366(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_367(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_368(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_369(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_370(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_371(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_372(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_373(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_374(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_375(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_376(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_377(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_378(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_379(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_380(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_381(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_382(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_383(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_384(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_385(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_386(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_387(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_388(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_389(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_390(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_391(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_392(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_393(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_394(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_395(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_396(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_397(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_398(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_399(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_400(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_401(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_402(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_403(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_404(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_405(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_406(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_407(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_408(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_409(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_410(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_411(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_412(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_413(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_414(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_415(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_416(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_417(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_418(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_419(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_420(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_421(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_422(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_423(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_424(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_425(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_426(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_427(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_428(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_429(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_430(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_431(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_432(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_433(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_434(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_435(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_436(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_437(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_438(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_439(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_440(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_441(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_442(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_443(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_444(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_445(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_446(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_447(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_448(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_449(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_450(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_451(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_452(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_453(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_454(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_455(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_456(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_457(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_458(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_459(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_460(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_461(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_462(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_463(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_464(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_465(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_466(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_467(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_468(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_469(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_470(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_471(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_472(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_473(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_474(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_475(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_476(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_477(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_478(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_479(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_480(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_481(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_482(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_483(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_484(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_485(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_486(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_487(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_488(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_489(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_490(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_491(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_492(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_493(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_494(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_495(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_496(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_497(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_498(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_499(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_500(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_501(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_502(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_503(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_504(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_505(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_506(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_507(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_508(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_509(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_510(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_511(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_512(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_513(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_514(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_515(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_516(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_517(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_518(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_519(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_520(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_521(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_522(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_523(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_524(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_525(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_526(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_527(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_528(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_529(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_530(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_531(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_532(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_533(xed_encoder_request_t* xes); +xed_bool_t xed_encode_group_534(xed_encoder_request_t* xes); +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-enc-operand-lu.h b/CodeVirtualizer/build/obj/include-private/xed-enc-operand-lu.h new file mode 100644 index 0000000..b2ea17b --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-enc-operand-lu.h @@ -0,0 +1,78 @@ +/// @file xed-enc-operand-lu.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENC_OPERAND_LU_H) +# define XED_ENC_OPERAND_LU_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_EASZ(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_DEFAULT_SEG_SEG0(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_NEED_SIB(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_INDEX(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_NEED_SIB_SCALE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_DISP_WIDTH_EASZ(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_INDEX(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_MODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_EASZ_MODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_NEED_SIB(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_DISP_WIDTH(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ_MODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_MODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_SMODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_AGEN(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_SEG0(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_SEG1(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_DF32_DF64_EOSZ_MODE_VEXVALID(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_VEXVALID(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MAP(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXB_REXX(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_REG_REXR(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_REXB_RM(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXR(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXB_REXX_VEX_C4(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MAP_VEX_C4(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_VEX_PREFIX_VL(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_DUMMY(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_SCALE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_INDEX(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXX(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXB(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXRR(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_VEX_PREFIX(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_ROUNDC_SAE_VL(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_VEXDEST4(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_ROUNDC(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_SAE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BCAST(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_IMM_WIDTH_MODE_UIMM0_1(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ_IMM_WIDTH(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_IMM_WIDTH(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BRDISP_WIDTH(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_BRDISP_WIDTH_EOSZ(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_OUTREG(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_OUTREG(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_OUTREG(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_OUTREG_SMODE(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ_OUTREG(xed_encoder_request_t* xes); +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ(xed_encoder_request_t* xes); +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-enc-patterns.h b/CodeVirtualizer/build/obj/include-private/xed-enc-patterns.h new file mode 100644 index 0000000..f6c583c --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-enc-patterns.h @@ -0,0 +1,346 @@ +/// @file xed-enc-patterns.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENC_PATTERNS_H) +# define XED_ENC_PATTERNS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_encode_instruction_fb_pattern_0(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_1(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_2(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_3(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_4(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_5(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_6(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_7(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_8(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_9(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_10(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_11(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_12(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_13(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_14(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_15(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_16(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_17(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_18(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_19(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_20(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_21(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_22(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_23(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_24(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_25(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_26(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_27(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_28(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_29(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_30(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_31(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_32(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_33(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_34(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_35(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_36(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_37(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_38(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_39(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_40(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_41(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_42(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_43(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_44(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_45(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_46(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_47(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_48(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_49(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_50(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_51(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_52(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_53(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_54(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_55(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_56(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_57(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_58(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_59(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_60(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_61(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_62(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_63(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_64(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_65(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_66(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_67(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_68(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_69(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_70(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_71(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_72(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_73(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_74(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_75(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_76(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_77(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_78(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_79(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_80(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_81(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_82(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_83(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_84(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_85(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_86(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_87(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_88(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_89(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_90(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_91(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_92(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_93(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_94(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_95(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_96(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_97(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_98(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_99(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_100(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_101(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_102(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_103(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_104(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_105(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_106(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_107(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_108(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_109(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_110(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_111(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_112(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_113(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_114(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_115(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_116(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_117(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_118(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_119(xed_encoder_request_t* xes); +void xed_encode_instruction_fb_pattern_120(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_0(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_1(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_2(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_3(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_4(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_5(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_6(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_7(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_8(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_9(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_10(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_11(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_12(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_13(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_14(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_15(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_16(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_17(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_18(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_19(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_20(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_21(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_22(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_23(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_24(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_25(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_26(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_27(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_28(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_29(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_30(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_31(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_32(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_33(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_34(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_35(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_36(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_37(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_38(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_39(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_40(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_41(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_42(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_43(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_44(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_45(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_46(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_47(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_48(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_49(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_50(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_51(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_52(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_53(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_54(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_55(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_56(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_57(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_58(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_59(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_60(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_61(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_62(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_63(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_64(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_65(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_66(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_67(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_68(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_69(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_70(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_71(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_72(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_73(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_74(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_75(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_76(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_77(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_78(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_79(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_80(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_81(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_82(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_83(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_84(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_85(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_86(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_87(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_88(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_89(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_90(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_91(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_92(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_93(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_94(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_95(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_96(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_97(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_98(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_99(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_100(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_101(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_102(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_103(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_104(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_105(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_106(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_107(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_108(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_109(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_110(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_111(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_112(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_113(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_114(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_115(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_116(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_117(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_118(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_119(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_120(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_121(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_122(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_123(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_124(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_125(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_126(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_127(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_128(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_129(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_130(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_131(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_132(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_133(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_134(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_135(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_136(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_137(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_138(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_139(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_140(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_141(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_142(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_143(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_144(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_145(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_146(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_147(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_148(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_149(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_150(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_151(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_152(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_153(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_154(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_155(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_156(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_157(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_158(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_159(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_160(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_161(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_162(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_163(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_164(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_165(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_166(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_167(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_168(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_169(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_170(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_171(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_172(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_173(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_174(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_175(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_176(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_177(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_178(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_179(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_180(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_181(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_182(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_183(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_184(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_185(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_186(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_187(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_188(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_189(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_190(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_191(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_192(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_193(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_194(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_195(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_196(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_197(xed_encoder_request_t* xes); +void xed_encode_instruction_emit_pattern_198(xed_encoder_request_t* xes); +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-encoder.h b/CodeVirtualizer/build/obj/include-private/xed-encoder.h new file mode 100644 index 0000000..8aed428 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-encoder.h @@ -0,0 +1,491 @@ +/// @file xed-encoder.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENCODER_H) +# define XED_ENCODER_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +xed_bool_t xed_encode_nonterminal_MODRM_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_MODRM_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_ISA_ENCODE(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_ISA_BINDINGS(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_ISA_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_XOP_ENC_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_XOP_ENC_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_NEWVEX_ENC_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_NEWVEX_ENC_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_VMODRM_XMM_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_VMODRM_YMM_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_VMODRM_XMM_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_VMODRM_YMM_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_EVEX_ENC_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_EVEX_ENC_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_NEWVEX3_ENC_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_NEWVEX3_ENC_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_ZMM_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_YMM_EMIT(xed_encoder_request_t* xes); +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_XMM_EMIT(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIBBASE_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIBBASE_ENCODE_SIB1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIBINDEX_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIBINDEX_ENCODE_SIB1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIBSCALE_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP16_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA16_SIB0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA64_SIB0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA32_SIB0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIB_NT_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_NT_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ERROR_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_16_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_0_8_16_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_FIXUP_EOSZ_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_FIXUP_EASZ_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_FIXUP_SMODE_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_REMOVE_SEGMENT_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_REMOVE_SEGMENT_AGEN1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DF64_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_OSZ_NONTERM_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_REFINING66_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_IGNORE66_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_IMMUNE66_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_IMMUNE_REXW_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_CR_WIDTH_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_FORCE64_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_BRANCH_HINT_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_CET_NO_TRACK_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VEXED_REX_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_XOP_TYPE_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_XOP_MAP_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_XOP_REXXB_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_BND_R_CHECK_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_BND_B_CHECK_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VEX_REXR_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VEX_REXXB_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VEX_MAP_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VEX_REG_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VEX_ESCVL_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SE_IMM8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_INDEX_XMM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_INDEX_YMM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_8_32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_4X_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_62_REXR_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_REXX_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_REXB_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_REXRR_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_MAP_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_REXW_VVVV_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_UPP_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_EVEX_LL_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_AVX512_EVEX_BYTE3_ENC_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_AVX512_ROUND_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SAE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_128_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_64_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_32_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_16_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_8_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_4_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_2_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ESIZE_1_BITS_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_MOVDDUP_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_FULLMEM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_HALFMEM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_BYTE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_WORD_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BYTE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_WORD_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_BYTE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_WORD_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_SCALAR_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_SUBDWORD_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_SUBDWORD_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_SUBDWORD_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_MEM128_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_GSCAT_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE2_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE4_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_FULL_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_HALF_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UISA_ENC_INDEX_ZMM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UISA_ENC_INDEX_YMM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UISA_ENC_INDEX_XMM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_NELEM_QUARTER_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ASZ_NONTERM_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_ONE_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UIMMv_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIMMz_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_SIMM8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UIMM8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UIMM8_1_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UIMM16_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_UIMM32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_BRDISP8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_BRDISP32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_BRDISPz_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MEMDISPv_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MEMDISP32_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MEMDISP16_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MEMDISP8_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_nonterminal_MEMDISP_BIND(xed_encoder_request_t* xes); +xed_uint32_t xed_encode_ntluf_GPR8_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR8_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR8_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_SEGe(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR16e(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32e(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32e_m32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32e_m64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR64e(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArAX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArBX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArCX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArDX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArSI(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArDI(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArSP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ArBP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_SrSP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_SrBP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar8(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar9(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar10(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar11(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar12(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar13(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar14(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_Ar15(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_rIP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_rIPa(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OeAX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OrAX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OrDX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OrCX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OrBX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OrSP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_OrBP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_rFLAGS(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MMX_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MMX_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRv_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRv_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRz_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRv_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRz_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRy_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPRy_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR64_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR64_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR64_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR64_X(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR32_X(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR16_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR16_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_GPR16_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_CR_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_CR_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_DR_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_X87(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_SEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_SEG_MOV(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_DSEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_DSEG_NOT64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_DSEG_MODE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_DSEG1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_DSEG1_NOT64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_DSEG1_MODE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_ESEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_ESEG1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_SSEG1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_SSEG0(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_SSEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_SSEG_NOT64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_FINAL_SSEG_MODE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_R_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_R_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_B_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_B_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_BND_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_BND_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_A_GPR_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_A_GPR_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_SE(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_SE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_SE32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_SE(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_SE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_SE32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_N_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_N_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_N_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_N_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_R_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_R_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_B_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_B_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPRy_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPRy_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPRy_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_N_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_N_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR64_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_R_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_R_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR64_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_B_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR32_B_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_VGPR64_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASK1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASKNOT0(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASK_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASK_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASK_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASK_N64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_MASK_N32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_R3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_R3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_R3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_R3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_R3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_R3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_R3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_R3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_R3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_B3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_B3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_B3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_B3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_B3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_B3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_B3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_B3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_B3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_N3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_N3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_XMM_N3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_N3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_N3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_YMM_N3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_N3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_N3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_ZMM_N3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_TMM_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_TMM_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint32_t xed_encode_ntluf_TMM_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg); +xed_uint_t xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SEGMENT_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIB_REQUIRED_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIB_REQUIRED_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIBBASE_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIBBASE_ENCODE_SIB1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIBINDEX_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIBINDEX_ENCODE_SIB1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIBSCALE_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP16_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA16_SIB0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA64_SIB0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA32_SIB0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIB_NT_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_NT_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ERROR_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_16_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_0_8_16_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_FIXUP_EOSZ_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_FIXUP_EASZ_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_FIXUP_SMODE_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_REMOVE_SEGMENT_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_REMOVE_SEGMENT_AGEN1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_OVERRIDE_SEG0_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_OVERRIDE_SEG1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_REX_PREFIX_ENC_BIND(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_REX_PREFIX_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_PREFIX_ENC_BIND(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_PREFIX_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DF64_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_OSZ_NONTERM_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_REFINING66_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_IGNORE66_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_IMMUNE66_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_IMMUNE_REXW_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_CR_WIDTH_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_FORCE64_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_BRANCH_HINT_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_CET_NO_TRACK_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEXED_REX_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_XOP_TYPE_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_XOP_MAP_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_XOP_REXXB_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_BND_R_CHECK_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_BND_B_CHECK_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_TYPE_ENC_BIND(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_TYPE_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_REXR_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_REXXB_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_MAP_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_REG_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VEX_ESCVL_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SE_IMM8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VMODRM_MOD_ENCODE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VSIB_ENC_BASE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VSIB_ENC_SCALE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VSIB_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VSIB_ENC_INDEX_XMM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_VSIB_ENC_INDEX_YMM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_4X_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_62_REXR_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_REXX_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_REXB_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_REXRR_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_MAP_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_REXW_VVVV_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_UPP_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_EVEX_LL_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_AVX512_EVEX_BYTE3_ENC_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_AVX512_ROUND_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SAE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_128_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_4_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_2_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ESIZE_1_BITS_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_MOVDDUP_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_HALFMEM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_QUARTERMEM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_EIGHTHMEM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_BYTE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_WORD_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BYTE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_WORD_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_BYTE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_WORD_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_SCALAR_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_SUBDWORD_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_SUBDWORD_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_SUBDWORD_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_MEM128_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_GSCAT_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE2_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE4_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_FULL_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_HALF_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_FIX_ROUND_LEN512_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UISA_ENC_INDEX_ZMM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UISA_ENC_INDEX_YMM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UISA_ENC_INDEX_XMM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_NELEM_QUARTER_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ASZ_NONTERM_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_ONE_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UIMMv_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIMMz_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_SIMM8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UIMM8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UIMM8_1_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UIMM16_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_UIMM32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_BRDISP8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_BRDISP32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_BRDISPz_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MEMDISPv_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MEMDISP32_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MEMDISP16_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MEMDISP8_EMIT(xed_encoder_request_t* xes); +xed_uint_t xed_encode_nonterminal_MEMDISP_EMIT(xed_encoder_request_t* xes); +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-disp-bytes.h b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-bytes.h new file mode 100644 index 0000000..1b5e7f0 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-bytes.h @@ -0,0 +1,545 @@ +/// @file include-private/xed-ild-disp-bytes.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_DISP_BYTES_H) +# define INCLUDE_PRIVATE_XED_ILD_DISP_BYTES_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-disp-l1.h" +#include "xed-ild-private.h" +#include "xed-operand-accessors.h" +const xed_ild_l1_func_t disp_width_map_legacy_map0[256] = { +/*opcode 0x0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x10*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x11*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x12*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x13*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x14*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x15*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x16*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x17*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x18*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x19*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x20*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x21*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x22*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x23*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x24*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x25*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x26*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x27*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x28*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x29*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x30*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x31*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x32*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x33*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x34*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x35*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x36*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x37*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x38*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x39*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x40*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x41*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x42*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x43*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x44*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x45*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x46*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x47*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x48*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x49*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x50*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x51*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x52*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x53*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x54*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x55*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x56*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x57*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x58*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x59*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x60*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x61*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x62*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x63*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x64*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x65*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x66*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x67*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x68*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x69*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x70*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x71*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x72*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x73*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x74*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x75*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x76*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x77*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x78*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x79*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x7a*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x7b*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x7c*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x7d*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x7e*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x7f*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0x80*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x81*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x82*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x83*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x84*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x85*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x86*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x87*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x88*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x89*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x90*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x91*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x92*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x93*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x94*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x95*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x96*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x97*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x98*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x99*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9a*/ xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x9b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa0*/ xed_lookup_function_MEMDISPv_DISP_WIDTH_ASZ_NONTERM_EASZ_l2, +/*opcode 0xa1*/ xed_lookup_function_MEMDISPv_DISP_WIDTH_ASZ_NONTERM_EASZ_l2, +/*opcode 0xa2*/ xed_lookup_function_MEMDISPv_DISP_WIDTH_ASZ_NONTERM_EASZ_l2, +/*opcode 0xa3*/ xed_lookup_function_MEMDISPv_DISP_WIDTH_ASZ_NONTERM_EASZ_l2, +/*opcode 0xa4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xaa*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xab*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xac*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xad*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xae*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xaf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xba*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbe*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc7*/ xed_lookup_function_RESOLVE_BYREG_DISP_maplegacy_map0_op0xc7_l1, +/*opcode 0xc8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xca*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xce*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xda*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xde*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe0*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0xe1*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0xe2*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0xe3*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0xe4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe8*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0xe9*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0xea*/ xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xeb*/ xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2, +/*opcode 0xec*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xed*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xee*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xef*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfa*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfe*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xff*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +}; +const xed_ild_l1_func_t disp_width_map_legacy_map1[256] = { +/*opcode 0x0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x10*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x11*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x12*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x13*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x14*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x15*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x16*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x17*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x18*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x19*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x1f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x20*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x21*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x22*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x23*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x24*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x25*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x26*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x27*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x28*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x29*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x2f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x30*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x31*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x32*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x33*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x34*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x35*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x36*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x37*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x38*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x39*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x3f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x40*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x41*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x42*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x43*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x44*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x45*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x46*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x47*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x48*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x49*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x4f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x50*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x51*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x52*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x53*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x54*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x55*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x56*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x57*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x58*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x59*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x5f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x60*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x61*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x62*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x63*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x64*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x65*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x66*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x67*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x68*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x69*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x6f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x70*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x71*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x72*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x73*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x74*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x75*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x76*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x77*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x78*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x79*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x7f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x80*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x81*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x82*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x83*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x84*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x85*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x86*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x87*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x88*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x89*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x8a*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x8b*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x8c*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x8d*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x8e*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x8f*/ xed_lookup_function_DISP_BUCKET_0_l1, +/*opcode 0x90*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x91*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x92*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x93*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x94*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x95*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x96*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x97*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x98*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x99*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9a*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9b*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9c*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9d*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9e*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0x9f*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xa9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xaa*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xab*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xac*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xad*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xae*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xaf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xb9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xba*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbe*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xbf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xc9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xca*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xce*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xcf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xd9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xda*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xde*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xdf*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xe9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xea*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xeb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xec*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xed*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xee*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xef*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf0*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf1*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf2*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf3*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf4*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf5*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf6*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf7*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf8*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xf9*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfa*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfb*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfc*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfd*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xfe*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +/*opcode 0xff*/ xed_lookup_function_EMPTY_DISP_CONST_l2, +}; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l1.h b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l1.h new file mode 100644 index 0000000..dbd812e --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l1.h @@ -0,0 +1,59 @@ +/// @file include-private/xed-ild-disp-l1.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_DISP_L1_H) +# define INCLUDE_PRIVATE_XED_ILD_DISP_L1_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-disp-l2.h" +static XED_INLINE void xed_lookup_function_DISP_BUCKET_0_l1(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_DISP_maplegacy_map0_op0xc7_l1(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_DISP_BUCKET_0_l1(xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +if(_mode <= 1) { +xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_EOSZ_l2(x); +return; +} +else if(2 == _mode) { +xed_lookup_function_BRDISP32_BRDISP_WIDTH_CONST_l2(x); +return; +} +} +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_DISP_maplegacy_map0_op0xc7_l1(xed_decoded_inst_t* x) +{ +xed_uint8_t _reg; +_reg = xed3_operand_get_reg(x); +switch(_reg) { +case 0: +xed_lookup_function_EMPTY_DISP_CONST_l2(x); +break; +case 7: +xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_EOSZ_l2(x); +break; +/*We should only get here for #UDs and those have no defined architectural length*/ +default: ; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l2.h b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l2.h new file mode 100644 index 0000000..10884c0 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l2.h @@ -0,0 +1,248 @@ +/// @file include-private/xed-ild-disp-l2.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_DISP_L2_H) +# define INCLUDE_PRIVATE_XED_ILD_DISP_L2_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-eosz.h" +#include "xed-ild-easz.h" +#include "xed-ild-disp-l3.h" +#include "xed-ild-private.h" +#include "xed-operand-accessors.h" +static XED_INLINE void xed_lookup_function_MEMDISPv_DISP_WIDTH_ASZ_NONTERM_EASZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISP32_BRDISP_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_DF64_FORCE64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_FORCE64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_IGNORE66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_IMMUNE66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_IMMUNE_REXW_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_REFINING66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_EMPTY_DISP_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_MEMDISPv_DISP_WIDTH_ASZ_NONTERM_EASZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _easz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _asz; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_asz = (xed_bits_t)xed3_operand_get_asz(x); +_easz = xed_lookup_function_ASZ_NONTERM_EASZ(_mode, _asz); +_disp_width = (xed_bits_t)xed_lookup_function_MEMDISPv_DISP_WIDTH_l3(_easz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISP32_BRDISP_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _disp_width; +_disp_width = (xed_bits_t)xed_lookup_function_BRDISP32_BRDISP_WIDTH_l3(); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISP8_BRDISP_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _disp_width; +_disp_width = (xed_bits_t)xed_lookup_function_BRDISP8_BRDISP_WIDTH_l3(); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_DF64_FORCE64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_FORCE64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_IGNORE66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_IMMUNE66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_IMMUNE_REXW_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_REFINING66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_BRDISPz_BRDISP_WIDTH_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _disp_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +_disp_width = (xed_bits_t)xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(_eosz); +xed3_operand_set_disp_width(x, _disp_width); +} +static XED_INLINE void xed_lookup_function_EMPTY_DISP_CONST_l2(xed_decoded_inst_t* x) +{ +/*This function does nothing for map-opcodes whose +disp_bytes value is set earlier in xed-ild.c +(regular displacement resolution by modrm/sib)*/ + +/*pacify the compiler*/ +(void)x; +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l3.h b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l3.h new file mode 100644 index 0000000..4a7f2c9 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-disp-l3.h @@ -0,0 +1,66 @@ +/// @file include-private/xed-ild-disp-l3.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_DISP_L3_H) +# define INCLUDE_PRIVATE_XED_ILD_DISP_L3_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_lookup_function_init_BRDISPz_BRDISP_WIDTH(void); + +void xed_lookup_function_init_MEMDISPv_DISP_WIDTH(void); + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_BRDISP32_BRDISP_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x20; +} +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_BRDISP8_BRDISP_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x8; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_BRDISPz_BRDISP_WIDTH[4]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_BRDISPz_BRDISP_WIDTH_l3(xed_bits_t arg_EOSZ) +{ +xed_bits_t _v; +xed_assert(arg_EOSZ>=1 && arg_EOSZ<4); +_v=xed_lookup_BRDISPz_BRDISP_WIDTH[arg_EOSZ]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_MEMDISPv_DISP_WIDTH[4]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_MEMDISPv_DISP_WIDTH_l3(xed_bits_t arg_EASZ) +{ +xed_bits_t _v; +xed_assert(arg_EASZ>=1 && arg_EASZ<4); +_v=xed_lookup_MEMDISPv_DISP_WIDTH[arg_EASZ]; +return _v; +} +void xed_ild_disp_l3_init(void); + +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-easz-getters.h b/CodeVirtualizer/build/obj/include-private/xed-ild-easz-getters.h new file mode 100644 index 0000000..2b81db7 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-easz-getters.h @@ -0,0 +1,39 @@ +/// @file include-private/xed-ild-easz-getters.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_EASZ_GETTERS_H) +# define INCLUDE_PRIVATE_XED_ILD_EASZ_GETTERS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-private.h" +#include "xed-ild-easz.h" +#include "xed-operand-accessors.h" +static XED_INLINE xed_bits_t xed_lookup_function_ASZ_NONTERM_EASZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_ASZ_NONTERM_EASZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _asz; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_asz = (xed_bits_t)xed3_operand_get_asz(x); +return xed_lookup_function_ASZ_NONTERM_EASZ(_mode, _asz); +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-easz.h b/CodeVirtualizer/build/obj/include-private/xed-ild-easz.h new file mode 100644 index 0000000..6e0fa28 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-easz.h @@ -0,0 +1,42 @@ +/// @file include-private/xed-ild-easz.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_EASZ_H) +# define INCLUDE_PRIVATE_XED_ILD_EASZ_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_lookup_function_init_ASZ_NONTERM_EASZ(void); + +/*Array declaration*/ +extern xed_bits_t xed_lookup_ASZ_NONTERM_EASZ[3][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_ASZ_NONTERM_EASZ(xed_bits_t arg_MODE, xed_bits_t arg_ASZ) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_ASZ>=0 && arg_ASZ<2); +_v=xed_lookup_ASZ_NONTERM_EASZ[arg_MODE][arg_ASZ]; +return _v; +} +void xed_ild_easz_init(void); + +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-eosz-getters.h b/CodeVirtualizer/build/obj/include-private/xed-ild-eosz-getters.h new file mode 100644 index 0000000..4a70c48 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-eosz-getters.h @@ -0,0 +1,161 @@ +/// @file include-private/xed-ild-eosz-getters.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_EOSZ_GETTERS_H) +# define INCLUDE_PRIVATE_XED_ILD_EOSZ_GETTERS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-private.h" +#include "xed-ild-eosz.h" +#include "xed-operand-accessors.h" +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ_getter(const xed_decoded_inst_t* x); + +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_DF64_EOSZ(_mode, _osz, _rexw); +} +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ_getter(const xed_decoded_inst_t* x) +{ +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +return xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ(_mode, _osz, _rexw); +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-eosz.h b/CodeVirtualizer/build/obj/include-private/xed-ild-eosz.h new file mode 100644 index 0000000..51588db --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-eosz.h @@ -0,0 +1,193 @@ +/// @file include-private/xed-ild-eosz.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_EOSZ_H) +# define INCLUDE_PRIVATE_XED_ILD_EOSZ_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_lookup_function_init_OSZ_NONTERM_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_CR_WIDTH_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_DF64_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_DF64_FORCE64_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_FORCE64_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_IGNORE66_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_IMMUNE66_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_IMMUNE_REXW_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_REFINING66_EOSZ(void); + +void xed_lookup_function_init_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(void); + +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_DF64_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_DF64_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[3][2][2]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(xed_bits_t arg_MODE, xed_bits_t arg_OSZ, xed_bits_t arg_REXW) +{ +xed_bits_t _v; +xed_assert(arg_MODE>=0 && arg_MODE<3); +xed_assert(arg_OSZ>=0 && arg_OSZ<2); +xed_assert(arg_REXW>=0 && arg_REXW<2); +_v=xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[arg_MODE][arg_OSZ][arg_REXW]; +return _v; +} +void xed_ild_eosz_init(void); + +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-imm-bytes.h b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-bytes.h new file mode 100644 index 0000000..ac1937d --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-bytes.h @@ -0,0 +1,1073 @@ +/// @file include-private/xed-ild-imm-bytes.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_IMM_BYTES_H) +# define INCLUDE_PRIVATE_XED_ILD_IMM_BYTES_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-imm-l1.h" +#include "xed-ild-private.h" +#include "xed-operand-accessors.h" +const xed_ild_l1_func_t imm_width_map_evex_map1[256] = { +/*opcode 0x0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x10*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x11*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x12*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x13*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x14*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x15*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x16*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x17*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x18*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x19*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x20*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x21*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x22*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x23*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x24*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x25*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x26*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x27*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x28*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x29*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x30*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x31*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x32*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x33*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x34*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x35*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x36*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x37*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x38*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x39*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x40*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x41*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x42*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x43*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x44*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x45*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x46*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x47*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x48*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x49*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x50*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x51*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x52*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x53*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x54*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x55*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x56*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x57*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x58*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x59*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x60*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x61*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x62*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x63*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x64*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x65*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x66*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x67*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x68*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x69*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x70*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x71*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x72*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x73*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x74*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x75*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x76*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x77*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x78*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x79*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x80*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x81*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x82*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x83*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x84*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x85*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x86*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x87*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x88*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x89*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x90*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x91*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x92*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x93*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x94*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x95*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x96*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x97*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x98*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x99*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xab*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xac*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xad*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xae*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xba*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc2*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc5*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc6*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xca*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xce*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xda*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xde*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xea*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xeb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xec*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xed*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xee*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xef*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xff*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +}; +const xed_ild_l1_func_t imm_width_map_legacy_map0[256] = { +/*opcode 0x0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x5*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xd*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x10*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x11*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x12*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x13*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x14*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x15*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x16*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x17*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x18*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x19*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1c*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x1d*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x1e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x20*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x21*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x22*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x23*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x24*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x25*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x26*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x27*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x28*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x29*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2c*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x2d*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x2e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x30*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x31*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x32*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x33*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x34*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x35*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x36*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x37*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x38*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x39*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3c*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x3d*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x3e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x40*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x41*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x42*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x43*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x44*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x45*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x46*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x47*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x48*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x49*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x50*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x51*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x52*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x53*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x54*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x55*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x56*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x57*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x58*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x59*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x60*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x61*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x62*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x63*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x64*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x65*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x66*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x67*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x68*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2, +/*opcode 0x69*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x6a*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x6b*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x6c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x70*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x71*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x72*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x73*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x74*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x75*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x76*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x77*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x78*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x79*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x80*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x81*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0x82*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x83*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x84*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x85*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x86*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x87*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x88*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x89*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x90*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x91*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x92*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x93*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x94*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x95*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x96*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x97*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x98*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x99*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9a*/ xed_lookup_function_UIMM16_IMM_WIDTH_CONST_l2, +/*opcode 0x9b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa8*/ xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xa9*/ xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xaa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xab*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xac*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xad*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xae*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb0*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb1*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb2*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb3*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb5*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb6*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb7*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xb8*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xb9*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xba*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xbb*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xbc*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xbd*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xbe*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xbf*/ xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2, +/*opcode 0xc0*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc1*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc2*/ xed_lookup_function_UIMM16_IMM_WIDTH_CONST_l2, +/*opcode 0xc3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc6*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc7*/ xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xc7_l1, +/*opcode 0xc8*/ xed_ild_hasimm_map0x0_op0xc8_l1, +/*opcode 0xc9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xca*/ xed_lookup_function_UIMM16_IMM_WIDTH_CONST_l2, +/*opcode 0xcb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcd*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xce*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xd5*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xd6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xda*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xde*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xe5*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xe6*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xe7*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xe8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xea*/ xed_lookup_function_UIMM16_IMM_WIDTH_CONST_l2, +/*opcode 0xeb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xec*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xed*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xee*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xef*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf6*/ xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xf6_l1, +/*opcode 0xf7*/ xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xf7_l1, +/*opcode 0xf8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xff*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +}; +const xed_ild_l1_func_t imm_width_map_legacy_map1[256] = { +/*opcode 0x0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x10*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x11*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x12*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x13*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x14*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x15*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x16*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x17*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x18*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x19*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x20*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x21*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x22*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x23*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x24*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x25*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x26*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x27*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x28*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x29*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x30*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x31*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x32*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x33*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x34*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x35*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x36*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x37*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x38*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x39*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x40*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x41*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x42*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x43*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x44*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x45*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x46*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x47*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x48*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x49*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x50*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x51*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x52*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x53*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x54*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x55*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x56*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x57*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x58*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x59*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x60*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x61*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x62*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x63*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x64*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x65*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x66*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x67*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x68*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x69*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x70*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x71*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x72*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x73*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x74*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x75*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x76*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x77*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x78*/ xed_ild_hasimm_map0x0F_op0x78_l1, +/*opcode 0x79*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x80*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x81*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x82*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x83*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x84*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x85*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x86*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x87*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x88*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x89*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x90*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x91*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x92*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x93*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x94*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x95*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x96*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x97*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x98*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x99*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xa5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xab*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xac*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xad*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xae*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xba*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xbb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc2*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc5*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc6*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xca*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xce*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xda*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xde*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xea*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xeb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xec*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xed*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xee*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xef*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xff*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +}; +const xed_ild_l1_func_t imm_width_map_vex_map1[256] = { +/*opcode 0x0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x10*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x11*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x12*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x13*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x14*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x15*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x16*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x17*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x18*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x19*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x1f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x20*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x21*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x22*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x23*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x24*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x25*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x26*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x27*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x28*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x29*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x2f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x30*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x31*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x32*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x33*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x34*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x35*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x36*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x37*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x38*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x39*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x3f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x40*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x41*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x42*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x43*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x44*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x45*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x46*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x47*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x48*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x49*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x4f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x50*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x51*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x52*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x53*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x54*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x55*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x56*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x57*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x58*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x59*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x5f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x60*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x61*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x62*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x63*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x64*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x65*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x66*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x67*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x68*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x69*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x6f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x70*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x71*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x72*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x73*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0x74*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x75*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x76*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x77*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x78*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x79*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x7f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x80*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x81*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x82*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x83*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x84*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x85*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x86*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x87*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x88*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x89*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x8f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x90*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x91*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x92*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x93*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x94*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x95*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x96*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x97*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x98*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x99*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9a*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9b*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9c*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9d*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9e*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0x9f*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xa9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xab*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xac*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xad*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xae*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xaf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xb9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xba*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xbf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc2*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc4*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc5*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc6*/ xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2, +/*opcode 0xc7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xc9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xca*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xce*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xcf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xd9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xda*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xde*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xdf*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xe9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xea*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xeb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xec*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xed*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xee*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xef*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf0*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf1*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf2*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf3*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf4*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf5*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf6*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf7*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf8*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xf9*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfa*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfb*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfc*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfd*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xfe*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +/*opcode 0xff*/ xed_lookup_function_0_IMM_WIDTH_CONST_l2, +}; +#if !defined(XED_MAP_ROW_LIMIT) +# define XED_MAP_ROW_LIMIT 11 +#endif +#if !defined(XED_VEXVALID_LIMIT) +# define XED_VEXVALID_LIMIT 4 +#endif +const xed_ild_l1_func_t* xed_ild_imm_width_table[XED_VEXVALID_LIMIT][XED_MAP_ROW_LIMIT] = { +{ imm_width_map_legacy_map0, imm_width_map_legacy_map1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, imm_width_map_vex_map1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, imm_width_map_evex_map1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l1.h b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l1.h new file mode 100644 index 0000000..795aeb8 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l1.h @@ -0,0 +1,74 @@ +/// @file include-private/xed-ild-imm-l1.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_IMM_L1_H) +# define INCLUDE_PRIVATE_XED_ILD_IMM_L1_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-imm-l2.h" +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xc7_l1(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xf6_l1(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xf7_l1(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xc7_l1(xed_decoded_inst_t* x) +{ +xed_uint8_t _reg; +_reg = xed3_operand_get_reg(x); +switch(_reg) { +case 0: +xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2(x); +break; +case 7: +xed_lookup_function_0_IMM_WIDTH_CONST_l2(x); +break; +/*We should only get here for #UDs and those have no defined architectural length*/ +default: ; +} +} +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xf6_l1(xed_decoded_inst_t* x) +{ +xed_uint8_t _reg; +_reg = xed3_operand_get_reg(x); +if(_reg <= 1) { +xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2(x); +return; +} +else if((2 <= _reg) && (_reg <= 7)) { +xed_lookup_function_0_IMM_WIDTH_CONST_l2(x); +return; +} +} +static XED_INLINE void xed_lookup_function_RESOLVE_BYREG_IMM_WIDTH_maplegacy_map0_op0xf7_l1(xed_decoded_inst_t* x) +{ +xed_uint8_t _reg; +_reg = xed3_operand_get_reg(x); +if(_reg <= 1) { +xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2(x); +return; +} +else if((2 <= _reg) && (_reg <= 7)) { +xed_lookup_function_0_IMM_WIDTH_CONST_l2(x); +return; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l2.h b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l2.h new file mode 100644 index 0000000..29097b5 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l2.h @@ -0,0 +1,428 @@ +/// @file include-private/xed-ild-imm-l2.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_IMM_L2_H) +# define INCLUDE_PRIVATE_XED_ILD_IMM_L2_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-eosz.h" +#include "xed-ild-imm-l3.h" +#include "xed-ild.h" +#include "xed-operand-accessors.h" +static XED_INLINE void xed_lookup_function_SE_IMM8_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_FORCE64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_FORCE64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_IGNORE66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_IMMUNE66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_IMMUNE_REXW_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_REFINING66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMM16_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMM32_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_DF64_FORCE64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_FORCE64_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_IGNORE66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_IMMUNE66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_IMMUNE_REXW_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_REFINING66_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_0_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x); + +static XED_INLINE void xed_lookup_function_SE_IMM8_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _imm_width; +_imm_width = (xed_bits_t)xed_lookup_function_SE_IMM8_IMM_WIDTH_l3(); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMM8_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _imm_width; +_imm_width = (xed_bits_t)xed_lookup_function_SIMM8_IMM_WIDTH_l3(); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_FORCE64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_FORCE64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_IGNORE66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_IMMUNE66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_IMMUNE_REXW_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_REFINING66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_SIMMz_IMM_WIDTH_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_SIMMz_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMM16_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _imm_width; +_imm_width = (xed_bits_t)xed_lookup_function_UIMM16_IMM_WIDTH_l3(); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMM32_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _imm_width; +_imm_width = (xed_bits_t)xed_lookup_function_UIMM32_IMM_WIDTH_l3(); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMM8_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _imm_width; +_imm_width = (xed_bits_t)xed_lookup_function_UIMM8_IMM_WIDTH_l3(); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_DF64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_DF64_FORCE64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_FORCE64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_FORCE64_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_FORCE64_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_IGNORE66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IGNORE66_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_IMMUNE66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IMMUNE66_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_IMMUNE_REXW_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_IMMUNE_REXW_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_REFINING66_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_REFINING66_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_UIMMv_IMM_WIDTH_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ_l2(xed_decoded_inst_t* x) +{ +xed_bits_t _eosz; +xed_bits_t _imm_width; +xed_bits_t _mode; +xed_bits_t _osz; +xed_bits_t _rexw; +_mode = (xed_bits_t)xed3_operand_get_mode(x); +_osz = (xed_bits_t)xed3_operand_get_osz(x); +_rexw = (xed_bits_t)xed3_operand_get_rexw(x); +_eosz = xed_lookup_function_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(_mode, _osz, _rexw); +_imm_width = (xed_bits_t)xed_lookup_function_UIMMv_IMM_WIDTH_l3(_eosz); +xed3_operand_set_imm_width(x, _imm_width); +} +static XED_INLINE void xed_lookup_function_0_IMM_WIDTH_CONST_l2(xed_decoded_inst_t* x) +{ +xed3_operand_set_imm_width(x, 0); +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l3.h b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l3.h new file mode 100644 index 0000000..c172069 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-imm-l3.h @@ -0,0 +1,84 @@ +/// @file include-private/xed-ild-imm-l3.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_IMM_L3_H) +# define INCLUDE_PRIVATE_XED_ILD_IMM_L3_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_lookup_function_init_SIMMz_IMM_WIDTH(void); + +void xed_lookup_function_init_UIMMv_IMM_WIDTH(void); + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_SE_IMM8_IMM_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x8; +} +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_SIMM8_IMM_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x8; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_SIMMz_IMM_WIDTH[4]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_SIMMz_IMM_WIDTH_l3(xed_bits_t arg_EOSZ) +{ +xed_bits_t _v; +xed_assert(arg_EOSZ>=1 && arg_EOSZ<4); +_v=xed_lookup_SIMMz_IMM_WIDTH[arg_EOSZ]; +return _v; +} +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_UIMM16_IMM_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x10; +} +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_UIMM32_IMM_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x20; +} +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_UIMM8_IMM_WIDTH_l3(void) +{ +/*Constant function*/ +return 0x8; +} +/*Array declaration*/ +extern xed_bits_t xed_lookup_UIMMv_IMM_WIDTH[4]; + +/*Lookup function*/ +static XED_INLINE xed_bits_t xed_lookup_function_UIMMv_IMM_WIDTH_l3(xed_bits_t arg_EOSZ) +{ +xed_bits_t _v; +xed_assert(arg_EOSZ>=1 && arg_EOSZ<4); +_v=xed_lookup_UIMMv_IMM_WIDTH[arg_EOSZ]; +return _v; +} +void xed_ild_imm_l3_init(void); + +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-ild-modrm.h b/CodeVirtualizer/build/obj/include-private/xed-ild-modrm.h new file mode 100644 index 0000000..8746586 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-ild-modrm.h @@ -0,0 +1,824 @@ +/// @file include-private/xed-ild-modrm.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED_ILD_MODRM_H) +# define INCLUDE_PRIVATE_XED_ILD_MODRM_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#define XED_ILD_HASMODRM_FALSE 0 + +#define XED_ILD_HASMODRM_IGNORE_MOD 2 + +#define XED_ILD_HASMODRM_TRUE 1 + +#define XED_ILD_HASMODRM_UD0 4 + +#define XED_ILD_HASMODRM_UNDEF 3 + + + +const xed_uint8_t has_modrm_map_legacy_map0[256] = { +/*opcode 0x0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x10*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x11*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x12*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x13*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x14*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x15*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x16*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x17*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x18*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x19*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x1d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x1e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x1f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x20*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x21*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x22*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x23*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x24*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x25*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x26*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x27*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x28*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x29*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x2d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x2e*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x2f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x30*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x31*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x32*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x33*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x34*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x35*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x36*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x37*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x38*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x39*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x3a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x3b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x3c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3e*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x40*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x41*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x42*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x43*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x44*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x45*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x46*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x47*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x48*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x49*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x4a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x4b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x4c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x4d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x4e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x4f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x50*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x51*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x52*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x53*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x54*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x55*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x56*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x57*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x58*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x59*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x60*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x61*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x62*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x63*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x64*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x65*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x66*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x67*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x68*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x69*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x70*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x71*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x72*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x73*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x74*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x75*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x76*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x77*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x78*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x79*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x80*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x81*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x82*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x83*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x84*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x85*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x86*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x87*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x88*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x89*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x8a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x8b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x8c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x8d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x8e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x8f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x90*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x91*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x92*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x93*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x94*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x95*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x96*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x97*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x98*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x99*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa0*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa1*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa2*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa3*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xaa*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xab*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xac*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xad*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xae*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xaf*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb0*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb1*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb2*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb3*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xba*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xbb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xbc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xbd*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xbe*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xbf*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc2*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc3*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xca*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcd*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xce*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcf*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xda*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xde*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe0*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe1*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe2*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe3*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xe9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xea*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xeb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xec*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xed*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xee*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xef*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf0*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0xf1*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf2*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0xf3*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0xf4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xfa*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xfb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xfc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xfd*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xfe*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xff*/ XED_ILD_HASMODRM_TRUE, +}; +const xed_uint8_t has_modrm_map_legacy_map1[256] = { +/*opcode 0x0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0xb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0xd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x10*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x11*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x12*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x13*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x14*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x15*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x16*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x17*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x18*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x19*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x20*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x21*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x22*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x23*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x24*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x25*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x26*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x27*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x28*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x29*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x30*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x31*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x32*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x33*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x34*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x35*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x36*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x37*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x38*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x39*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3a*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3b*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3c*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3d*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3e*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x3f*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x40*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x41*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x42*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x43*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x44*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x45*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x46*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x47*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x48*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x49*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x50*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x51*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x52*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x53*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x54*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x55*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x56*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x57*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x58*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x59*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x60*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x61*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x62*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x63*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x64*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x65*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x66*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x67*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x68*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x69*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x70*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x71*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x72*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x73*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x74*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x75*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x76*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x77*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x78*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x79*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7a*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x7b*/ XED_ILD_HASMODRM_UNDEF, +/*opcode 0x7c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x80*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x81*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x82*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x83*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x84*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x85*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x86*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x87*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x88*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x89*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x90*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x91*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x92*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x93*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x94*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x95*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x96*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x97*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x98*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x99*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa0*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa1*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa2*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa6*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0xa7*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0xa8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xaa*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xab*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xac*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xad*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xae*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xaf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xba*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbe*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xca*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcd*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xce*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcf*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xda*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xde*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xea*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xeb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xec*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xed*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xee*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xef*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfa*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfe*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xff*/ XED_ILD_HASMODRM_UD0, +}; +const xed_uint8_t has_modrm_map_vex_map1[256] = { +/*opcode 0x0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x5*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x6*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xf*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x10*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x11*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x12*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x13*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x14*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x15*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x16*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x17*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x18*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x19*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x1f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x20*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x21*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x22*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x23*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0x24*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x25*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x26*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x27*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x28*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x29*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x2f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x30*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x31*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x32*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x33*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x34*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x35*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x36*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x37*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x38*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x39*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x3f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x40*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x41*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x42*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x43*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x44*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x45*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x46*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x47*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x48*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x49*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x4f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x50*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x51*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x52*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x53*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x54*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x55*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x56*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x57*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x58*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x59*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x5f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x60*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x61*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x62*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x63*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x64*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x65*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x66*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x67*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x68*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x69*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x6f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x70*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x71*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x72*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x73*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x74*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x75*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x76*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x77*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x78*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x79*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x7c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x7f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x80*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x81*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x82*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x83*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x84*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x85*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x86*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x87*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x88*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x89*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8a*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8b*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8c*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8d*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8e*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x8f*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0x90*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x91*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x92*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x93*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x94*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x95*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x96*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x97*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x98*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x99*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9a*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9b*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9c*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9d*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9e*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0x9f*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa0*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa1*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa2*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xa6*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0xa7*/ XED_ILD_HASMODRM_IGNORE_MOD, +/*opcode 0xa8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xa9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xaa*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xab*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xac*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xad*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xae*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xaf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xb9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xba*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbe*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xbf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xc8*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xc9*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xca*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcb*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcc*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcd*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xce*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xcf*/ XED_ILD_HASMODRM_FALSE, +/*opcode 0xd0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xd9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xda*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xde*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xdf*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xe9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xea*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xeb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xec*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xed*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xee*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xef*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf0*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf1*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf2*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf3*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf4*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf5*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf6*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf7*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf8*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xf9*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfa*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfb*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfc*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfd*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xfe*/ XED_ILD_HASMODRM_TRUE, +/*opcode 0xff*/ XED_ILD_HASMODRM_UD0, +}; +#if !defined(XED_MAP_ROW_LIMIT) +# define XED_MAP_ROW_LIMIT 11 +#endif +#if !defined(XED_VEXVALID_LIMIT) +# define XED_VEXVALID_LIMIT 4 +#endif +const xed_uint8_t* xed_ild_has_modrm_table[XED_VEXVALID_LIMIT][XED_MAP_ROW_LIMIT] = { +{ has_modrm_map_legacy_map0, has_modrm_map_legacy_map1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, has_modrm_map_vex_map1, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, +}; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed-map-feature-tables.h b/CodeVirtualizer/build/obj/include-private/xed-map-feature-tables.h new file mode 100644 index 0000000..f114dcf --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed-map-feature-tables.h @@ -0,0 +1,204 @@ +/// @file xed-map-feature-tables.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_MAP_FEATURE_TABLES_H) +# define XED_MAP_FEATURE_TABLES_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-map-info.h" +static XED_INLINE xed_bool_t xed_ild_has_modrm_legacy(xed_uint_t m) +{ + /* [2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x15aULL; + return (xed_bool_t)((data_const >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_disp_legacy(xed_uint_t m) +{ + /* [2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0xaULL; + return (xed_bool_t)((data_const >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_imm_legacy(xed_uint_t m) +{ + /* [7, 7, 0, 1, 1, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x11077ULL; + return (xed_bool_t)((data_const >> (4*m)) & 15); +} +static XED_INLINE xed_bool_t xed_ild_has_modrm_vex(xed_uint_t m) +{ + /* [0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x58ULL; + return (xed_bool_t)((data_const >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_disp_vex(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] */ + return 0; + (void)m; +} +static XED_INLINE xed_bool_t xed_ild_has_imm_vex(xed_uint_t m) +{ + /* [0, 7, 0, 1, 0, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x1070ULL; + return (xed_bool_t)((data_const >> (4*m)) & 15); +} +static XED_INLINE xed_bool_t xed_ild_has_modrm_evex(xed_uint_t m) +{ + /* [0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x1454ULL; + return (xed_bool_t)((data_const >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_disp_evex(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] */ + return 0; + (void)m; +} +static XED_INLINE xed_bool_t xed_ild_has_imm_evex(xed_uint_t m) +{ + /* [0, 7, 0, 1, 0, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x1070ULL; + return (xed_bool_t)((data_const >> (4*m)) & 15); +} +static XED_INLINE xed_bool_t xed_ild_has_modrm_xop(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1] */ + const xed_uint64_t data_const = 0x150000ULL; + return (xed_bool_t)((data_const >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_disp_xop(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] */ + return 0; + (void)m; +} +static XED_INLINE xed_bool_t xed_ild_has_imm_xop(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 4] */ + const xed_uint64_t data_const = 0x40100000000ULL; + return (xed_bool_t)((data_const >> (4*m)) & 15); +} +static XED_INLINE xed_bool_t xed_ild_has_modrm_knc(xed_uint_t m) +{ + /* [0] */ + return 0; + (void)m; +} +static XED_INLINE xed_bool_t xed_ild_has_disp_knc(xed_uint_t m) +{ + /* [0] */ + return 0; + (void)m; +} +static XED_INLINE xed_bool_t xed_ild_has_imm_knc(xed_uint_t m) +{ + /* [0] */ + return 0; + (void)m; +} +static XED_INLINE xed_bool_t xed_ild_has_modrm(xed_uint_t vv, xed_uint_t m) +{ + const xed_uint64_t data_const[5] = { + /* [2, 2, 1, 1, 1, 0, 0, 0, 0, 0, 0] legacy */ + 0x15aULL, + /* [0, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0] vex */ + 0x58ULL, + /* [0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0] evex */ + 0x1454ULL, + /* [0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1] xop */ + 0x150000ULL, + /* [0] knc */ + 0x0ULL, + }; + xed_assert(vv < 5); + return (xed_bool_t)((data_const[vv] >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_disp(xed_uint_t vv, xed_uint_t m) +{ + const xed_uint64_t data_const[5] = { + /* [2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0] legacy */ + 0xaULL, + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] vex */ + 0x0ULL, + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] evex */ + 0x0ULL, + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] xop */ + 0x0ULL, + /* [0] knc */ + 0x0ULL, + }; + xed_assert(vv < 5); + return (xed_bool_t)((data_const[vv] >> (2*m)) & 3); +} +static XED_INLINE xed_bool_t xed_ild_has_imm(xed_uint_t vv, xed_uint_t m) +{ + const xed_uint64_t data_const[5] = { + /* [7, 7, 0, 1, 1, 0, 0, 0, 0, 0, 0] legacy */ + 0x11077ULL, + /* [0, 7, 0, 1, 0, 0, 0, 0, 0, 0, 0] vex */ + 0x1070ULL, + /* [0, 7, 0, 1, 0, 0, 0, 0, 0, 0, 0] evex */ + 0x1070ULL, + /* [0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 4] xop */ + 0x40100000000ULL, + /* [0] knc */ + 0x0ULL, + }; + xed_assert(vv < 5); + return (xed_bool_t)((data_const[vv] >> (4*m)) & 15); +} +static XED_INLINE xed_bool_t xed_ild_map_valid_legacy(xed_uint_t m) +{ + /* [1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x1fULL; + return (xed_bool_t)((data_const >> m) & 1); +} +static XED_INLINE xed_bool_t xed_ild_map_valid_vex(xed_uint_t m) +{ + /* [0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0xeULL; + return (xed_bool_t)((data_const >> m) & 1); +} +static XED_INLINE xed_bool_t xed_ild_map_valid_evex(xed_uint_t m) +{ + /* [0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x6eULL; + return (xed_bool_t)((data_const >> m) & 1); +} +static XED_INLINE xed_bool_t xed_ild_map_valid_xop(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1] */ + const xed_uint64_t data_const = 0x700ULL; + return (xed_bool_t)((data_const >> m) & 1); +} +static XED_INLINE xed_bool_t xed_ild_map_valid_knc(xed_uint_t m) +{ + /* [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0] */ + const xed_uint64_t data_const = 0x0ULL; + return (xed_bool_t)((data_const >> m) & 1); +} +const xed_map_info_t xed_legacy_maps[] = { +{ 0x0F, 1, 0x38, 2, 2 }, +{ 0x0F, 1, 0x3A, 3, 2 }, +{ 0x0F, 1, 0x0F, 4, -1 }, +{ 0x0F, 0, 0, 1, 1 }, +}; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-chain-capture-lu.h b/CodeVirtualizer/build/obj/include-private/xed3-chain-capture-lu.h new file mode 100644 index 0000000..6295b51 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-chain-capture-lu.h @@ -0,0 +1,22870 @@ +/// @file xed3-chain-capture-lu.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED3_CHAIN_CAPTURE_LU_H) +# define XED3_CHAIN_CAPTURE_LU_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-chain-capture.h" +typedef xed_error_enum_t(*xed3_chain_function_t)(xed_decoded_inst_t*); +static xed3_chain_function_t xed3_chain_fptr_lu[7614] = { +/*NO PATTERN*/ (xed3_chain_function_t)0, +/* +0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=1*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=2*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=3*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=4*/ xed3_capture_nt_nop, +/* +0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=5*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=6*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=7*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=8*/ xed3_capture_nt_nop, +/* +0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=9*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=10*/ xed3_capture_nt_nop, +/* +0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=11*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=12*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=13*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=14*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=15*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=16*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=17*/ xed3_capture_nt_nop, +/* +0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=18*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=19*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=20*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=21*/ xed3_capture_nt_nop, +/* +0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=22*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=23*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=24*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=25*/ xed3_capture_nt_nop, +/* +0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=26*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=27*/ xed3_capture_nt_nop, +/* +0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=28*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=29*/ xed3_capture_nt_nop, +/* +0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=30*/ xed3_capture_chain_MODRM, +/* +0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=31*/ xed3_capture_chain_MODRM, +/* +0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=32*/ xed3_capture_nt_nop, +/* +0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=33*/ xed3_capture_nt_nop, +/* +0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=34*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=35*/ xed3_capture_nt_nop, +/* +0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=36*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=37*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=38*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=39*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=40*/ xed3_capture_nt_nop, +/* +0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=41*/ xed3_capture_chain_MODRM, +/* +0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=42*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=43*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=44*/ xed3_capture_nt_nop, +/* +0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=45*/ xed3_capture_nt_nop, +/* +0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=46*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=47*/ xed3_capture_nt_nop, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM() +inum=48*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM() +inum=49*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +inum=50*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM() +inum=51*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM() +inum=52*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM() +inum=53*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +inum=54*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=55*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM() +inum=56*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM() +inum=57*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +inum=58*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM() +inum=59*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM() +inum=60*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM() +inum=61*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +inum=62*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=63*/ xed3_capture_chain_MODRM, +/* +0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=64*/ xed3_capture_nt_nop, +/* +0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=65*/ xed3_capture_nt_nop, +/* +0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=66*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000] +inum=67*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000] +inum=68*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001] +inum=69*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100] +inum=70*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101] +inum=71*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000] +inum=72*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001] +inum=73*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010] +inum=74*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011] +inum=75*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100] +inum=76*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101] +inum=77*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110] +inum=78*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000] +inum=79*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001] +inum=80*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010] +inum=81*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011] +inum=82*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100] +inum=83*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101] +inum=84*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110] +inum=85*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111] +inum=86*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000] +inum=87*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +inum=88*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010] +inum=89*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011] +inum=90*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +inum=91*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +inum=92*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110] +inum=93*/ xed3_capture_nt_nop, +/* +0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111] +inum=94*/ xed3_capture_nt_nop, +/* +0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=95*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=96*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=97*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=98*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=99*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=100*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=101*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=102*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=103*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=104*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=105*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=106*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=107*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=108*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=109*/ xed3_capture_chain_MODRM, +/* +0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=110*/ xed3_capture_chain_MODRM, +/* +0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=111*/ xed3_capture_nt_nop, +/* +0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=112*/ xed3_capture_nt_nop, +/* +0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=113*/ xed3_capture_nt_nop, +/* +0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=114*/ xed3_capture_nt_nop, +/* +0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001] +inum=115*/ xed3_capture_nt_nop, +/* +0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=116*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=117*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=118*/ xed3_capture_chain_MODRM, +/* +0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=119*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=120*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=121*/ xed3_capture_chain_MODRM, +/* +0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=122*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=123*/ xed3_capture_chain_MODRM, +/* +0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=124*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=125*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=126*/ xed3_capture_chain_MODRM, +/* +0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=127*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=128*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=129*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=130*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010] +inum=131*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011] +inum=132*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100] +inum=133*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000] +inum=134*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001] +inum=135*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=136*/ xed3_capture_nt_nop, +/* +0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=137*/ xed3_capture_nt_nop, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM() +inum=138*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM() +inum=139*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +inum=140*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM() +inum=141*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM() +inum=142*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM() +inum=143*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +inum=144*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM() +inum=145*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM() +inum=146*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM() +inum=147*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM() +inum=148*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM() +inum=149*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM() +inum=150*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM() +inum=151*/ xed3_capture_chain_MODRM, +/* +0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=152*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000] +inum=153*/ xed3_capture_nt_nop, +/* +0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=154*/ xed3_capture_nt_nop, +/* +0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=155*/ xed3_capture_nt_nop, +/* +0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=156*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=157*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=158*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001] +inum=159*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=160*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=161*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=162*/ xed3_capture_nt_nop, +/* +0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=163*/ xed3_capture_nt_nop, +/* +0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=164*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=165*/ xed3_capture_chain_MODRM, +/* +0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=166*/ xed3_capture_nt_nop, +/* +0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=167*/ xed3_capture_nt_nop, +/* +0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=168*/ xed3_capture_nt_nop, +/* +0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +inum=169*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix +inum=170*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix +inum=171*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix +inum=172*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=173*/ xed3_capture_chain_MODRM, +/* +0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=174*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=175*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +inum=176*/ xed3_capture_chain_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=177*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +inum=178*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +inum=179*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8() +inum=180*/ xed3_capture_chain_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=181*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +inum=182*/ xed3_capture_chain_SIMM8, +/* +0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=183*/ xed3_capture_chain_MODRM, +/* +0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=184*/ xed3_capture_nt_nop, +/* +0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=185*/ xed3_capture_chain_MODRM, +/* +0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=186*/ xed3_capture_nt_nop, +/* +0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=187*/ xed3_capture_chain_MODRM, +/* +0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=188*/ xed3_capture_nt_nop, +/* +0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=189*/ xed3_capture_chain_MODRM, +/* +0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=190*/ xed3_capture_nt_nop, +/* +0x04 SIMM8() +inum=191*/ xed3_capture_chain_SIMM8, +/* +0x05 SIMMz() +inum=192*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +inum=193*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix +inum=194*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix +inum=195*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix +inum=196*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=197*/ xed3_capture_chain_MODRM, +/* +0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=198*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=199*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +inum=200*/ xed3_capture_chain_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=201*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +inum=202*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +inum=203*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8() +inum=204*/ xed3_capture_chain_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=205*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +inum=206*/ xed3_capture_chain_SIMM8, +/* +0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=207*/ xed3_capture_chain_MODRM, +/* +0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=208*/ xed3_capture_nt_nop, +/* +0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=209*/ xed3_capture_chain_MODRM, +/* +0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=210*/ xed3_capture_nt_nop, +/* +0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=211*/ xed3_capture_chain_MODRM, +/* +0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=212*/ xed3_capture_nt_nop, +/* +0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=213*/ xed3_capture_chain_MODRM, +/* +0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=214*/ xed3_capture_nt_nop, +/* +0x0C UIMM8() +inum=215*/ xed3_capture_chain_UIMM8, +/* +0x0D SIMMz() +inum=216*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +inum=217*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix +inum=218*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix +inum=219*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix +inum=220*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=221*/ xed3_capture_chain_MODRM, +/* +0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=222*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=223*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +inum=224*/ xed3_capture_chain_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=225*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz() +inum=226*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +inum=227*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8() +inum=228*/ xed3_capture_chain_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=229*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8() +inum=230*/ xed3_capture_chain_SIMM8, +/* +0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=231*/ xed3_capture_chain_MODRM, +/* +0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=232*/ xed3_capture_nt_nop, +/* +0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=233*/ xed3_capture_chain_MODRM, +/* +0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=234*/ xed3_capture_nt_nop, +/* +0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=235*/ xed3_capture_chain_MODRM, +/* +0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=236*/ xed3_capture_nt_nop, +/* +0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=237*/ xed3_capture_chain_MODRM, +/* +0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=238*/ xed3_capture_nt_nop, +/* +0x14 SIMM8() +inum=239*/ xed3_capture_chain_SIMM8, +/* +0x15 SIMMz() +inum=240*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +inum=241*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix +inum=242*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix +inum=243*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix +inum=244*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=245*/ xed3_capture_chain_MODRM, +/* +0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=246*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=247*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +inum=248*/ xed3_capture_chain_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=249*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz() +inum=250*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +inum=251*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8() +inum=252*/ xed3_capture_chain_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=253*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8() +inum=254*/ xed3_capture_chain_SIMM8, +/* +0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=255*/ xed3_capture_chain_MODRM, +/* +0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=256*/ xed3_capture_nt_nop, +/* +0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=257*/ xed3_capture_chain_MODRM, +/* +0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=258*/ xed3_capture_nt_nop, +/* +0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=259*/ xed3_capture_nt_nop, +/* +0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=260*/ xed3_capture_chain_MODRM, +/* +0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=261*/ xed3_capture_nt_nop, +/* +0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=262*/ xed3_capture_chain_MODRM, +/* +0x1C SIMM8() +inum=263*/ xed3_capture_chain_SIMM8, +/* +0x1D SIMMz() +inum=264*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix +inum=265*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix +inum=266*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix +inum=267*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix +inum=268*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=269*/ xed3_capture_chain_MODRM, +/* +0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=270*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix +inum=271*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=272*/ xed3_capture_chain_UIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=273*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz() +inum=274*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +inum=275*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8() +inum=276*/ xed3_capture_chain_UIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=277*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8() +inum=278*/ xed3_capture_chain_SIMM8, +/* +0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=279*/ xed3_capture_chain_MODRM, +/* +0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=280*/ xed3_capture_nt_nop, +/* +0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=281*/ xed3_capture_chain_MODRM, +/* +0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=282*/ xed3_capture_nt_nop, +/* +0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=283*/ xed3_capture_nt_nop, +/* +0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=284*/ xed3_capture_chain_MODRM, +/* +0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=285*/ xed3_capture_nt_nop, +/* +0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=286*/ xed3_capture_chain_MODRM, +/* +0x24 SIMM8() +inum=287*/ xed3_capture_chain_SIMM8, +/* +0x25 SIMMz() +inum=288*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +inum=289*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix +inum=290*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix +inum=291*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix +inum=292*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=293*/ xed3_capture_chain_MODRM, +/* +0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=294*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=295*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +inum=296*/ xed3_capture_chain_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=297*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz() +inum=298*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix +inum=299*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8() +inum=300*/ xed3_capture_chain_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=301*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8() +inum=302*/ xed3_capture_chain_SIMM8, +/* +0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=303*/ xed3_capture_chain_MODRM, +/* +0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=304*/ xed3_capture_nt_nop, +/* +0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=305*/ xed3_capture_chain_MODRM, +/* +0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=306*/ xed3_capture_nt_nop, +/* +0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=307*/ xed3_capture_nt_nop, +/* +0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=308*/ xed3_capture_chain_MODRM, +/* +0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=309*/ xed3_capture_nt_nop, +/* +0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=310*/ xed3_capture_chain_MODRM, +/* +0x2C SIMM8() +inum=311*/ xed3_capture_chain_SIMM8, +/* +0x2D SIMMz() +inum=312*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +inum=313*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix +inum=314*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix +inum=315*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix +inum=316*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=317*/ xed3_capture_chain_MODRM, +/* +0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=318*/ xed3_capture_chain_MODRM, +/* +0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +inum=319*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=320*/ xed3_capture_chain_UIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix +inum=321*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz() +inum=322*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix +inum=323*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8() +inum=324*/ xed3_capture_chain_UIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix +inum=325*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8() +inum=326*/ xed3_capture_chain_SIMM8, +/* +0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=327*/ xed3_capture_chain_MODRM, +/* +0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=328*/ xed3_capture_nt_nop, +/* +0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=329*/ xed3_capture_chain_MODRM, +/* +0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=330*/ xed3_capture_nt_nop, +/* +0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=331*/ xed3_capture_nt_nop, +/* +0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=332*/ xed3_capture_chain_MODRM, +/* +0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=333*/ xed3_capture_nt_nop, +/* +0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=334*/ xed3_capture_chain_MODRM, +/* +0x34 UIMM8() +inum=335*/ xed3_capture_chain_UIMM8, +/* +0x35 SIMMz() +inum=336*/ xed3_capture_chain_SIMMz, +/* +0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +inum=337*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +inum=338*/ xed3_capture_chain_SIMM8, +/* +0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz() +inum=339*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz() +inum=340*/ xed3_capture_chain_SIMMz, +/* +0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8() +inum=341*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8() +inum=342*/ xed3_capture_chain_SIMM8, +/* +0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8() +inum=343*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8() +inum=344*/ xed3_capture_chain_SIMM8, +/* +0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=345*/ xed3_capture_chain_MODRM, +/* +0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=346*/ xed3_capture_nt_nop, +/* +0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=347*/ xed3_capture_chain_MODRM, +/* +0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=348*/ xed3_capture_nt_nop, +/* +0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=349*/ xed3_capture_chain_MODRM, +/* +0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=350*/ xed3_capture_nt_nop, +/* +0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=351*/ xed3_capture_chain_MODRM, +/* +0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=352*/ xed3_capture_nt_nop, +/* +0x3C SIMM8() +inum=353*/ xed3_capture_chain_SIMM8, +/* +0x3D SIMMz() +inum=354*/ xed3_capture_chain_SIMMz, +/* +0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM() +inum=355*/ xed3_capture_chain_DF64_MODRM, +/* +0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64() +inum=356*/ xed3_capture_chain_DF64, +/* +0x07 not64 +inum=357*/ xed3_capture_nt_nop, +/* +0x17 not64 +inum=358*/ xed3_capture_nt_nop, +/* +0x1F not64 +inum=359*/ xed3_capture_nt_nop, +/* +0b0101_1 SRM[rrr] DF64() +inum=360*/ xed3_capture_chain_DF64, +/* +0x0F 0xA1 DF64() +inum=361*/ xed3_capture_chain_DF64, +/* +0x0F 0xA9 DF64() +inum=362*/ xed3_capture_chain_DF64, +/* +0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +inum=363*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +inum=364*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +inum=365*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +inum=366*/ xed3_capture_chain_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +inum=367*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +inum=368*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE() +inum=369*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE() +inum=370*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=371*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=372*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=373*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=374*/ xed3_capture_nt_nop, +/* +0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +inum=375*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +inum=376*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8() +inum=377*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8() +inum=378*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +inum=379*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +inum=380*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE() +inum=381*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE() +inum=382*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=383*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=384*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=385*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=386*/ xed3_capture_nt_nop, +/* +0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +inum=387*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=388*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8() +inum=389*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=390*/ xed3_capture_chain_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +inum=391*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +inum=392*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE() +inum=393*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE() +inum=394*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=395*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=396*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=397*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=398*/ xed3_capture_nt_nop, +/* +0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +inum=399*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +inum=400*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8() +inum=401*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +inum=402*/ xed3_capture_chain_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +inum=403*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +inum=404*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE() +inum=405*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE() +inum=406*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=407*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=408*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=409*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=410*/ xed3_capture_nt_nop, +/* +0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +inum=411*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=412*/ xed3_capture_chain_UIMM8, +/* +0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +inum=413*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=414*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +inum=415*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=416*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() +inum=417*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=418*/ xed3_capture_chain_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +inum=419*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +inum=420*/ xed3_capture_chain_ONE, +/* +0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +inum=421*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +inum=422*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE() +inum=423*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE() +inum=424*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE() +inum=425*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE() +inum=426*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=427*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=428*/ xed3_capture_nt_nop, +/* +0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=429*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=430*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=431*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=432*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=433*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=434*/ xed3_capture_nt_nop, +/* +0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +inum=435*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +inum=436*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() +inum=437*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +inum=438*/ xed3_capture_chain_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +inum=439*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +inum=440*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE() +inum=441*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE() +inum=442*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=443*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=444*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=445*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=446*/ xed3_capture_nt_nop, +/* +0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +inum=447*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +inum=448*/ xed3_capture_chain_UIMM8, +/* +0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() +inum=449*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +inum=450*/ xed3_capture_chain_UIMM8, +/* +0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +inum=451*/ xed3_capture_chain_MODRM_ONE, +/* +0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +inum=452*/ xed3_capture_chain_ONE, +/* +0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE() +inum=453*/ xed3_capture_chain_MODRM_ONE, +/* +0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE() +inum=454*/ xed3_capture_chain_ONE, +/* +0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=455*/ xed3_capture_chain_MODRM, +/* +0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=456*/ xed3_capture_nt_nop, +/* +0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=457*/ xed3_capture_chain_MODRM, +/* +0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=458*/ xed3_capture_nt_nop, +/* +0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() +inum=459*/ xed3_capture_chain_MODRM_SIMM8, +/* +0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() +inum=460*/ xed3_capture_chain_MODRM_SIMM8, +/* +0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8() +inum=461*/ xed3_capture_chain_SIMM8, +/* +0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8() +inum=462*/ xed3_capture_chain_SIMM8, +/* +0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +inum=463*/ xed3_capture_chain_MODRM_SIMMz, +/* +0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() +inum=464*/ xed3_capture_chain_MODRM_SIMMz, +/* +0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +inum=465*/ xed3_capture_chain_SIMMz, +/* +0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz() +inum=466*/ xed3_capture_chain_SIMMz, +/* +0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=467*/ xed3_capture_chain_MODRM, +/* +0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=468*/ xed3_capture_nt_nop, +/* +0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=469*/ xed3_capture_chain_MODRM, +/* +0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=470*/ xed3_capture_nt_nop, +/* +0xA8 SIMM8() +inum=471*/ xed3_capture_chain_SIMM8, +/* +0xA9 SIMMz() +inum=472*/ xed3_capture_chain_SIMMz, +/* +0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +inum=473*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix +inum=474*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +inum=475*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=476*/ xed3_capture_nt_nop, +/* +0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix +inum=477*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=478*/ xed3_capture_nt_nop, +/* +0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +inum=479*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix +inum=480*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +inum=481*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=482*/ xed3_capture_nt_nop, +/* +0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix +inum=483*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=484*/ xed3_capture_nt_nop, +/* +0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=485*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=486*/ xed3_capture_nt_nop, +/* +0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=487*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=488*/ xed3_capture_nt_nop, +/* +0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=489*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=490*/ xed3_capture_nt_nop, +/* +0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=491*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=492*/ xed3_capture_nt_nop, +/* +0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz() +inum=493*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz() +inum=494*/ xed3_capture_chain_SIMMz, +/* +0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8() +inum=495*/ xed3_capture_chain_MODRM_SIMM8, +/* +0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8() +inum=496*/ xed3_capture_chain_SIMM8, +/* +0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=497*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=498*/ xed3_capture_nt_nop, +/* +0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=499*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=500*/ xed3_capture_nt_nop, +/* +0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=501*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=502*/ xed3_capture_nt_nop, +/* +0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=503*/ xed3_capture_chain_MODRM, +/* +0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=504*/ xed3_capture_nt_nop, +/* +0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=505*/ xed3_capture_chain_MODRM, +/* +0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=506*/ xed3_capture_nt_nop, +/* +0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +inum=507*/ xed3_capture_chain_MODRM, +/* +0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix +inum=508*/ xed3_capture_chain_MODRM, +/* +0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +inum=509*/ xed3_capture_chain_MODRM, +/* +0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=510*/ xed3_capture_nt_nop, +/* +0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix +inum=511*/ xed3_capture_chain_MODRM, +/* +0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=512*/ xed3_capture_nt_nop, +/* +0b0100_0 SRM[rrr] not64 +inum=513*/ xed3_capture_nt_nop, +/* +0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +inum=514*/ xed3_capture_chain_MODRM, +/* +0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix +inum=515*/ xed3_capture_chain_MODRM, +/* +0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +inum=516*/ xed3_capture_chain_MODRM, +/* +0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=517*/ xed3_capture_nt_nop, +/* +0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix +inum=518*/ xed3_capture_chain_MODRM, +/* +0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=519*/ xed3_capture_nt_nop, +/* +0b0100_1 SRM[rrr] not64 +inum=520*/ xed3_capture_nt_nop, +/* +0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK() +inum=521*/ xed3_capture_chain_DF64_IMMUNE66_LOOP64_MODRM_CET_NO_TRACK, +/* +0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK() +inum=522*/ xed3_capture_chain_DF64_IMMUNE66_LOOP64_CET_NO_TRACK, +/* +0xE8 not64 BRDISPz() +inum=523*/ xed3_capture_chain_BRDISPz, +/* +0xE8 mode64 BRDISP32() DF64() FORCE64() +inum=524*/ xed3_capture_chain_BRDISP32_DF64_FORCE64, +/* +0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK() +inum=525*/ xed3_capture_chain_DF64_IMMUNE66_LOOP64_MODRM_CET_NO_TRACK, +/* +0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK() +inum=526*/ xed3_capture_chain_DF64_IMMUNE66_LOOP64_CET_NO_TRACK, +/* +0xE9 not64 BRDISPz() +inum=527*/ xed3_capture_chain_BRDISPz, +/* +0xE9 mode64 FORCE64() BRDISP32() +inum=528*/ xed3_capture_chain_FORCE64_BRDISP32, +/* +0xEB not64 BRDISP8() +inum=529*/ xed3_capture_chain_BRDISP8, +/* +0xEB mode64 FORCE64() BRDISP8() +inum=530*/ xed3_capture_chain_FORCE64_BRDISP8, +/* +0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=531*/ xed3_capture_chain_MODRM, +/* +0xEA not64 BRDISPz() UIMM16() +inum=532*/ xed3_capture_chain_BRDISPz_UIMM16, +/* +0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM() +inum=533*/ xed3_capture_chain_DF64_MODRM, +/* +0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64() +inum=534*/ xed3_capture_chain_DF64, +/* +0x06 not64 +inum=535*/ xed3_capture_nt_nop, +/* +0x0E not64 +inum=536*/ xed3_capture_nt_nop, +/* +0x16 not64 +inum=537*/ xed3_capture_nt_nop, +/* +0x1E not64 +inum=538*/ xed3_capture_nt_nop, +/* +0b0101_0 SRM[rrr] DF64() +inum=539*/ xed3_capture_chain_DF64, +/* +0x68 DF64() SIMMz() +inum=540*/ xed3_capture_chain_DF64_SIMMz, +/* +0x6A DF64() SIMM8() +inum=541*/ xed3_capture_chain_DF64_SIMM8, +/* +0x0F 0xA0 DF64() +inum=542*/ xed3_capture_chain_DF64, +/* +0x0F 0xA8 DF64() +inum=543*/ xed3_capture_chain_DF64, +/* +0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=544*/ xed3_capture_chain_MODRM, +/* +0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=545*/ xed3_capture_nt_nop, +/* +0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=546*/ xed3_capture_chain_MODRM, +/* +0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=547*/ xed3_capture_nt_nop, +/* +0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=548*/ xed3_capture_chain_MODRM, +/* +0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=549*/ xed3_capture_nt_nop, +/* +0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=550*/ xed3_capture_chain_MODRM, +/* +0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=551*/ xed3_capture_nt_nop, +/* +0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=552*/ xed3_capture_chain_MODRM, +/* +0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=553*/ xed3_capture_nt_nop, +/* +0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=554*/ xed3_capture_chain_MODRM, +/* +0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=555*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM() +inum=556*/ xed3_capture_chain_FORCE64_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() +inum=557*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=558*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=559*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=560*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=561*/ xed3_capture_nt_nop, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() +inum=562*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=563*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=564*/ xed3_capture_chain_MODRM, +/* +0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=565*/ xed3_capture_nt_nop, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix +inum=566*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=567*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix +inum=568*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8() +inum=569*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=570*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=571*/ xed3_capture_nt_nop, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix +inum=572*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=573*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix +inum=574*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=575*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=576*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=577*/ xed3_capture_nt_nop, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix +inum=578*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=579*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix +inum=580*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +inum=581*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=582*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=583*/ xed3_capture_nt_nop, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +inum=584*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM() +inum=585*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +inum=586*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM() +inum=587*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix +inum=588*/ xed3_capture_chain_IMMUNE66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix +inum=589*/ xed3_capture_chain_IMMUNE66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix +inum=590*/ xed3_capture_chain_IMMUNE66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix +inum=591*/ xed3_capture_chain_IMMUNE66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix +inum=592*/ xed3_capture_chain_IMMUNE66_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix +inum=593*/ xed3_capture_chain_IMMUNE66_MODRM, +/* +0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() +inum=594*/ xed3_capture_chain_UIMM8, +/* +0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8() +inum=595*/ xed3_capture_chain_MODRM_UIMM8, +/* +0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz() +inum=596*/ xed3_capture_chain_SIMMz, +/* +0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() +inum=597*/ xed3_capture_chain_MODRM_SIMMz, +/* +0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=598*/ xed3_capture_nt_nop, +/* +0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=599*/ xed3_capture_chain_MODRM, +/* +0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=600*/ xed3_capture_chain_MODRM, +/* +0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=601*/ xed3_capture_nt_nop, +/* +0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=602*/ xed3_capture_chain_MODRM, +/* +0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=603*/ xed3_capture_nt_nop, +/* +0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=604*/ xed3_capture_chain_MODRM, +/* +0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=605*/ xed3_capture_nt_nop, +/* +0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=606*/ xed3_capture_chain_MODRM, +/* +0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=607*/ xed3_capture_nt_nop, +/* +0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=608*/ xed3_capture_chain_MODRM, +/* +0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=609*/ xed3_capture_nt_nop, +/* +0xA0 MEMDISPv() OVERRIDE_SEG0() +inum=610*/ xed3_capture_chain_MEMDISPv_OVERRIDE_SEG0, +/* +0xA1 MEMDISPv() OVERRIDE_SEG0() +inum=611*/ xed3_capture_chain_MEMDISPv_OVERRIDE_SEG0, +/* +0xA2 MEMDISPv() OVERRIDE_SEG0() +inum=612*/ xed3_capture_chain_MEMDISPv_OVERRIDE_SEG0, +/* +0xA3 MEMDISPv() OVERRIDE_SEG0() +inum=613*/ xed3_capture_chain_MEMDISPv_OVERRIDE_SEG0, +/* +0b1011_0 SRM[rrr] UIMM8() +inum=614*/ xed3_capture_chain_UIMM8, +/* +0b1011_1 SRM[rrr] UIMMv() +inum=615*/ xed3_capture_chain_UIMMv, +/* +0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=616*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +inum=617*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=618*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=619*/ xed3_capture_nt_nop, +/* +0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=620*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=621*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=622*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +inum=623*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=624*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=625*/ xed3_capture_nt_nop, +/* +0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=626*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=627*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=628*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +inum=629*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=630*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=631*/ xed3_capture_nt_nop, +/* +0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=632*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=633*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=634*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +inum=635*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=636*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=637*/ xed3_capture_nt_nop, +/* +0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=638*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=639*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=640*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8() +inum=641*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=642*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=643*/ xed3_capture_nt_nop, +/* +0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=644*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=645*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=646*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +inum=647*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=648*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=649*/ xed3_capture_nt_nop, +/* +0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=650*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=651*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=652*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8() +inum=653*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=654*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=655*/ xed3_capture_nt_nop, +/* +0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=656*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=657*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=658*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8() +inum=659*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=660*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=661*/ xed3_capture_nt_nop, +/* +0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=662*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=663*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8() +inum=664*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8() +inum=665*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM() +inum=666*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM() +inum=667*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM() +inum=668*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM() +inum=669*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM() +inum=670*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM() +inum=671*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=672*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=673*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=674*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=675*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=676*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=677*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=678*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=679*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=680*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=681*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=682*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=683*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=684*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=685*/ xed3_capture_nt_nop, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=686*/ xed3_capture_chain_MODRM, +/* +0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=687*/ xed3_capture_chain_MODRM, +/* +0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=688*/ xed3_capture_chain_MODRM, +/* +0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=689*/ xed3_capture_nt_nop, +/* +0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=690*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=691*/ xed3_capture_nt_nop, +/* +0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=692*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=693*/ xed3_capture_nt_nop, +/* +0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix +inum=694*/ xed3_capture_nt_nop, +/* +0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0 +inum=695*/ xed3_capture_nt_nop, +/* +0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=696*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=697*/ xed3_capture_nt_nop, +/* +0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=698*/ xed3_capture_nt_nop, +/* +0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +inum=699*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=700*/ xed3_capture_nt_nop, +/* +0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=701*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=702*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=703*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=704*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=705*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix +inum=706*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +inum=707*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix +inum=708*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix +inum=709*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix +inum=710*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix +inum=711*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix +inum=712*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +inum=713*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix +inum=714*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix +inum=715*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix +inum=716*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix +inum=717*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix +inum=718*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix +inum=719*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0 +inum=720*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0 +inum=721*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0 +inum=722*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0 +inum=723*/ xed3_capture_nt_nop, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix +inum=724*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +inum=725*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix +inum=726*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=727*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=728*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=729*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=730*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=731*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=732*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=733*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=734*/ xed3_capture_nt_nop, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0 +inum=735*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix +inum=736*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix +inum=737*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix +inum=738*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix +inum=739*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM() +inum=740*/ xed3_capture_chain_FORCE64_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() +inum=741*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM() +inum=742*/ xed3_capture_chain_FORCE64_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() +inum=743*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32 +inum=744*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16 +inum=745*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64 +inum=746*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32 +inum=747*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix +inum=748*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() +inum=749*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM() +inum=750*/ xed3_capture_chain_FORCE64_MODRM, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=751*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64 +inum=752*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001] +inum=753*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix +inum=754*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM() +inum=755*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix +inum=756*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix +inum=757*/ xed3_capture_nt_nop, +/* +0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=758*/ xed3_capture_nt_nop, +/* +0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=759*/ xed3_capture_chain_MODRM, +/* +0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=760*/ xed3_capture_chain_MODRM, +/* +0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=761*/ xed3_capture_nt_nop, +/* +0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=762*/ xed3_capture_chain_MODRM, +/* +0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=763*/ xed3_capture_chain_MODRM, +/* +0x27 not64 +inum=764*/ xed3_capture_nt_nop, +/* +0x2F not64 +inum=765*/ xed3_capture_nt_nop, +/* +0x37 not64 +inum=766*/ xed3_capture_nt_nop, +/* +0x3F not64 +inum=767*/ xed3_capture_nt_nop, +/* +0x60 mode16 no66_prefix +inum=768*/ xed3_capture_nt_nop, +/* +0x60 mode32 66_prefix +inum=769*/ xed3_capture_nt_nop, +/* +0x60 mode16 66_prefix +inum=770*/ xed3_capture_nt_nop, +/* +0x60 mode32 no66_prefix +inum=771*/ xed3_capture_nt_nop, +/* +0x61 mode16 no66_prefix +inum=772*/ xed3_capture_nt_nop, +/* +0x61 mode32 66_prefix +inum=773*/ xed3_capture_nt_nop, +/* +0x61 mode16 66_prefix +inum=774*/ xed3_capture_nt_nop, +/* +0x61 mode32 no66_prefix +inum=775*/ xed3_capture_nt_nop, +/* +0x62 mode16 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=776*/ xed3_capture_chain_MODRM, +/* +0x62 mode32 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=777*/ xed3_capture_chain_MODRM, +/* +0x62 mode16 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=778*/ xed3_capture_chain_MODRM, +/* +0x62 mode32 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=779*/ xed3_capture_chain_MODRM, +/* +0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +inum=780*/ xed3_capture_chain_MODRM, +/* +0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +inum=781*/ xed3_capture_nt_nop, +/* +0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() +inum=782*/ xed3_capture_chain_MODRM, +/* +0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 +inum=783*/ xed3_capture_nt_nop, +/* +0x6C repe +inum=784*/ xed3_capture_nt_nop, +/* +0x6C repne +inum=785*/ xed3_capture_nt_nop, +/* +0x6C norep +inum=786*/ xed3_capture_nt_nop, +/* +0x6D mode16 no66_prefix repe +inum=787*/ xed3_capture_nt_nop, +/* +0x6D mode32 66_prefix repe +inum=788*/ xed3_capture_nt_nop, +/* +0x6D mode64 norexw_prefix 66_prefix repe +inum=789*/ xed3_capture_nt_nop, +/* +0x6D mode16 no66_prefix repne +inum=790*/ xed3_capture_nt_nop, +/* +0x6D mode32 66_prefix repne +inum=791*/ xed3_capture_nt_nop, +/* +0x6D mode64 norexw_prefix 66_prefix repne +inum=792*/ xed3_capture_nt_nop, +/* +0x6D mode16 no66_prefix norep +inum=793*/ xed3_capture_nt_nop, +/* +0x6D mode32 66_prefix norep +inum=794*/ xed3_capture_nt_nop, +/* +0x6D mode64 norexw_prefix 66_prefix norep +inum=795*/ xed3_capture_nt_nop, +/* +0x6D mode16 66_prefix repe +inum=796*/ xed3_capture_nt_nop, +/* +0x6D mode32 no66_prefix repe +inum=797*/ xed3_capture_nt_nop, +/* +0x6D mode64 norexw_prefix no66_prefix repe +inum=798*/ xed3_capture_nt_nop, +/* +0x6D mode64 rexw_prefix repe +inum=799*/ xed3_capture_nt_nop, +/* +0x6D mode16 66_prefix repne +inum=800*/ xed3_capture_nt_nop, +/* +0x6D mode32 no66_prefix repne +inum=801*/ xed3_capture_nt_nop, +/* +0x6D mode64 norexw_prefix no66_prefix repne +inum=802*/ xed3_capture_nt_nop, +/* +0x6D mode64 rexw_prefix repne +inum=803*/ xed3_capture_nt_nop, +/* +0x6D mode16 66_prefix norep +inum=804*/ xed3_capture_nt_nop, +/* +0x6D mode32 no66_prefix norep +inum=805*/ xed3_capture_nt_nop, +/* +0x6D mode64 norexw_prefix no66_prefix norep +inum=806*/ xed3_capture_nt_nop, +/* +0x6D mode64 rexw_prefix norep +inum=807*/ xed3_capture_nt_nop, +/* +0x6E repe OVERRIDE_SEG0() +inum=808*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6E repne OVERRIDE_SEG0() +inum=809*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6E norep OVERRIDE_SEG0() +inum=810*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode16 no66_prefix repe OVERRIDE_SEG0() +inum=811*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode32 66_prefix repe OVERRIDE_SEG0() +inum=812*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +inum=813*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode16 no66_prefix repne OVERRIDE_SEG0() +inum=814*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode32 66_prefix repne OVERRIDE_SEG0() +inum=815*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +inum=816*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode16 no66_prefix norep OVERRIDE_SEG0() +inum=817*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode32 66_prefix norep OVERRIDE_SEG0() +inum=818*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +inum=819*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode16 66_prefix repe OVERRIDE_SEG0() +inum=820*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode32 no66_prefix repe OVERRIDE_SEG0() +inum=821*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +inum=822*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 rexw_prefix repe OVERRIDE_SEG0() +inum=823*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode16 66_prefix repne OVERRIDE_SEG0() +inum=824*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode32 no66_prefix repne OVERRIDE_SEG0() +inum=825*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +inum=826*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 rexw_prefix repne OVERRIDE_SEG0() +inum=827*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode16 66_prefix norep OVERRIDE_SEG0() +inum=828*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode32 no66_prefix norep OVERRIDE_SEG0() +inum=829*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +inum=830*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x6F mode64 rexw_prefix norep OVERRIDE_SEG0() +inum=831*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=832*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x70 not64 BRANCH_HINT() BRDISP8() +inum=833*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=834*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x0F 0x80 not64 BRANCH_HINT() BRDISPz() +inum=835*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=836*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x71 not64 BRANCH_HINT() BRDISP8() +inum=837*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x81 not64 BRANCH_HINT() BRDISPz() +inum=838*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=839*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=840*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x72 not64 BRANCH_HINT() BRDISP8() +inum=841*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x82 not64 BRANCH_HINT() BRDISPz() +inum=842*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=843*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=844*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x73 not64 BRANCH_HINT() BRDISP8() +inum=845*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x83 not64 BRANCH_HINT() BRDISPz() +inum=846*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=847*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=848*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x74 not64 BRANCH_HINT() BRDISP8() +inum=849*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x84 not64 BRANCH_HINT() BRDISPz() +inum=850*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=851*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=852*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x75 not64 BRANCH_HINT() BRDISP8() +inum=853*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x85 not64 BRANCH_HINT() BRDISPz() +inum=854*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=855*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=856*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x76 not64 BRANCH_HINT() BRDISP8() +inum=857*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x86 not64 BRANCH_HINT() BRDISPz() +inum=858*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=859*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=860*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x77 not64 BRANCH_HINT() BRDISP8() +inum=861*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x87 not64 BRANCH_HINT() BRDISPz() +inum=862*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=863*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=864*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x78 not64 BRANCH_HINT() BRDISP8() +inum=865*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x88 not64 BRANCH_HINT() BRDISPz() +inum=866*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=867*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=868*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x79 not64 BRANCH_HINT() BRDISP8() +inum=869*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x89 not64 BRANCH_HINT() BRDISPz() +inum=870*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=871*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=872*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x7A not64 BRANCH_HINT() BRDISP8() +inum=873*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x8A not64 BRANCH_HINT() BRDISPz() +inum=874*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=875*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=876*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x7B not64 BRANCH_HINT() BRDISP8() +inum=877*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x8B not64 BRANCH_HINT() BRDISPz() +inum=878*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=879*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=880*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x7C not64 BRANCH_HINT() BRDISP8() +inum=881*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x8C not64 BRANCH_HINT() BRDISPz() +inum=882*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=883*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=884*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x7D not64 BRANCH_HINT() BRDISP8() +inum=885*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x8D not64 BRANCH_HINT() BRDISPz() +inum=886*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=887*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=888*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x7E not64 BRANCH_HINT() BRDISP8() +inum=889*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x8E not64 BRANCH_HINT() BRDISPz() +inum=890*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=891*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8() +inum=892*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8, +/* +0x7F not64 BRANCH_HINT() BRDISP8() +inum=893*/ xed3_capture_chain_BRANCH_HINT_BRDISP8, +/* +0x0F 0x8F not64 BRANCH_HINT() BRDISPz() +inum=894*/ xed3_capture_chain_BRANCH_HINT_BRDISPz, +/* +0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32() +inum=895*/ xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32, +/* +0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=896*/ xed3_capture_chain_MODRM, +/* +0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=897*/ xed3_capture_chain_MODRM, +/* +0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=898*/ xed3_capture_nt_nop, +/* +0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=899*/ xed3_capture_chain_MODRM, +/* +0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=900*/ xed3_capture_chain_MODRM, +/* +0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=901*/ xed3_capture_nt_nop, +/* +0b1001_0 SRM[rrr] SRM!=0 +inum=902*/ xed3_capture_nt_nop, +/* +0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix +inum=903*/ xed3_capture_nt_nop, +/* +0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT() +inum=904*/ xed3_capture_chain_MODRM_REMOVE_SEGMENT, +/* +0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1 +inum=905*/ xed3_capture_nt_nop, +/* +0x98 mode16 no66_prefix +inum=906*/ xed3_capture_nt_nop, +/* +0x98 mode32 66_prefix +inum=907*/ xed3_capture_nt_nop, +/* +0x98 mode64 norexw_prefix 66_prefix +inum=908*/ xed3_capture_nt_nop, +/* +0x98 mode64 rexw_prefix +inum=909*/ xed3_capture_nt_nop, +/* +0x98 mode16 66_prefix +inum=910*/ xed3_capture_nt_nop, +/* +0x98 mode32 no66_prefix +inum=911*/ xed3_capture_nt_nop, +/* +0x98 mode64 norexw_prefix no66_prefix +inum=912*/ xed3_capture_nt_nop, +/* +0x99 mode16 no66_prefix +inum=913*/ xed3_capture_nt_nop, +/* +0x99 mode32 66_prefix +inum=914*/ xed3_capture_nt_nop, +/* +0x99 mode64 norexw_prefix 66_prefix +inum=915*/ xed3_capture_nt_nop, +/* +0x99 mode64 rexw_prefix +inum=916*/ xed3_capture_nt_nop, +/* +0x99 mode16 66_prefix +inum=917*/ xed3_capture_nt_nop, +/* +0x99 mode32 no66_prefix +inum=918*/ xed3_capture_nt_nop, +/* +0x99 mode64 norexw_prefix no66_prefix +inum=919*/ xed3_capture_nt_nop, +/* +0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=920*/ xed3_capture_chain_MODRM, +/* +0x9A not64 BRDISPz() UIMM16() +inum=921*/ xed3_capture_chain_BRDISPz_UIMM16, +/* +0x9B +inum=922*/ xed3_capture_nt_nop, +/* +0x9C mode16 no66_prefix +inum=923*/ xed3_capture_nt_nop, +/* +0x9C mode32 66_prefix +inum=924*/ xed3_capture_nt_nop, +/* +0x9C mode64 norexw_prefix 66_prefix +inum=925*/ xed3_capture_nt_nop, +/* +0x9C mode32 no66_prefix +inum=926*/ xed3_capture_nt_nop, +/* +0x9C mode16 66_prefix +inum=927*/ xed3_capture_nt_nop, +/* +0x9C mode64 norexw_prefix no66_prefix DF64() +inum=928*/ xed3_capture_chain_DF64, +/* +0x9C mode64 rexw_prefix DF64() +inum=929*/ xed3_capture_chain_DF64, +/* +0x9D mode16 no66_prefix +inum=930*/ xed3_capture_nt_nop, +/* +0x9D mode32 66_prefix +inum=931*/ xed3_capture_nt_nop, +/* +0x9D mode64 norexw_prefix 66_prefix +inum=932*/ xed3_capture_nt_nop, +/* +0x9D mode16 66_prefix +inum=933*/ xed3_capture_nt_nop, +/* +0x9D mode32 no66_prefix +inum=934*/ xed3_capture_nt_nop, +/* +0x9D mode64 norexw_prefix no66_prefix DF64() +inum=935*/ xed3_capture_chain_DF64, +/* +0x9D mode64 rexw_prefix DF64() +inum=936*/ xed3_capture_chain_DF64, +/* +0x9E +inum=937*/ xed3_capture_nt_nop, +/* +0x9F +inum=938*/ xed3_capture_nt_nop, +/* +0xA4 repe OVERRIDE_SEG1() +inum=939*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA4 repne OVERRIDE_SEG1() +inum=940*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA4 norep OVERRIDE_SEG1() +inum=941*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode16 no66_prefix repe OVERRIDE_SEG1() +inum=942*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode32 66_prefix repe OVERRIDE_SEG1() +inum=943*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG1() +inum=944*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode16 no66_prefix repne OVERRIDE_SEG1() +inum=945*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode32 66_prefix repne OVERRIDE_SEG1() +inum=946*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG1() +inum=947*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode16 no66_prefix norep OVERRIDE_SEG1() +inum=948*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode32 66_prefix norep OVERRIDE_SEG1() +inum=949*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG1() +inum=950*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode16 66_prefix repe OVERRIDE_SEG1() +inum=951*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode32 no66_prefix repe OVERRIDE_SEG1() +inum=952*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG1() +inum=953*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode16 66_prefix repne OVERRIDE_SEG1() +inum=954*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode32 no66_prefix repne OVERRIDE_SEG1() +inum=955*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG1() +inum=956*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode16 66_prefix norep OVERRIDE_SEG1() +inum=957*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode32 no66_prefix norep OVERRIDE_SEG1() +inum=958*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG1() +inum=959*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 rexw_prefix repe OVERRIDE_SEG1() +inum=960*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 rexw_prefix repne OVERRIDE_SEG1() +inum=961*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA5 mode64 rexw_prefix norep OVERRIDE_SEG1() +inum=962*/ xed3_capture_chain_OVERRIDE_SEG1, +/* +0xA6 repe OVERRIDE_SEG0() +inum=963*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA6 repne OVERRIDE_SEG0() +inum=964*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA6 norep OVERRIDE_SEG0() +inum=965*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode16 no66_prefix repe OVERRIDE_SEG0() +inum=966*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode32 66_prefix repe OVERRIDE_SEG0() +inum=967*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +inum=968*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode16 no66_prefix repne OVERRIDE_SEG0() +inum=969*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode32 66_prefix repne OVERRIDE_SEG0() +inum=970*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +inum=971*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode16 no66_prefix norep OVERRIDE_SEG0() +inum=972*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode32 66_prefix norep OVERRIDE_SEG0() +inum=973*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +inum=974*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode16 66_prefix repe OVERRIDE_SEG0() +inum=975*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode32 no66_prefix repe OVERRIDE_SEG0() +inum=976*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +inum=977*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode16 66_prefix repne OVERRIDE_SEG0() +inum=978*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode32 no66_prefix repne OVERRIDE_SEG0() +inum=979*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +inum=980*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode16 66_prefix norep OVERRIDE_SEG0() +inum=981*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode32 no66_prefix norep OVERRIDE_SEG0() +inum=982*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +inum=983*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 rexw_prefix repe OVERRIDE_SEG0() +inum=984*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 rexw_prefix repne OVERRIDE_SEG0() +inum=985*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xA7 mode64 rexw_prefix norep OVERRIDE_SEG0() +inum=986*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAA repe +inum=987*/ xed3_capture_nt_nop, +/* +0xAA repne +inum=988*/ xed3_capture_nt_nop, +/* +0xAA norep +inum=989*/ xed3_capture_nt_nop, +/* +0xAB mode16 no66_prefix repe +inum=990*/ xed3_capture_nt_nop, +/* +0xAB mode32 66_prefix repe +inum=991*/ xed3_capture_nt_nop, +/* +0xAB mode64 norexw_prefix 66_prefix repe +inum=992*/ xed3_capture_nt_nop, +/* +0xAB mode16 no66_prefix repne +inum=993*/ xed3_capture_nt_nop, +/* +0xAB mode32 66_prefix repne +inum=994*/ xed3_capture_nt_nop, +/* +0xAB mode64 norexw_prefix 66_prefix repne +inum=995*/ xed3_capture_nt_nop, +/* +0xAB mode16 no66_prefix norep +inum=996*/ xed3_capture_nt_nop, +/* +0xAB mode32 66_prefix norep +inum=997*/ xed3_capture_nt_nop, +/* +0xAB mode64 norexw_prefix 66_prefix norep +inum=998*/ xed3_capture_nt_nop, +/* +0xAB mode16 66_prefix repe +inum=999*/ xed3_capture_nt_nop, +/* +0xAB mode32 no66_prefix repe +inum=1000*/ xed3_capture_nt_nop, +/* +0xAB mode64 norexw_prefix no66_prefix repe +inum=1001*/ xed3_capture_nt_nop, +/* +0xAB mode16 66_prefix repne +inum=1002*/ xed3_capture_nt_nop, +/* +0xAB mode32 no66_prefix repne +inum=1003*/ xed3_capture_nt_nop, +/* +0xAB mode64 norexw_prefix no66_prefix repne +inum=1004*/ xed3_capture_nt_nop, +/* +0xAB mode16 66_prefix norep +inum=1005*/ xed3_capture_nt_nop, +/* +0xAB mode32 no66_prefix norep +inum=1006*/ xed3_capture_nt_nop, +/* +0xAB mode64 norexw_prefix no66_prefix norep +inum=1007*/ xed3_capture_nt_nop, +/* +0xAB mode64 rexw_prefix repe +inum=1008*/ xed3_capture_nt_nop, +/* +0xAB mode64 rexw_prefix repne +inum=1009*/ xed3_capture_nt_nop, +/* +0xAB mode64 rexw_prefix norep +inum=1010*/ xed3_capture_nt_nop, +/* +0xAC repe OVERRIDE_SEG0() +inum=1011*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAC repne OVERRIDE_SEG0() +inum=1012*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAC norep OVERRIDE_SEG0() +inum=1013*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode16 no66_prefix repe OVERRIDE_SEG0() +inum=1014*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode32 66_prefix repe OVERRIDE_SEG0() +inum=1015*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0() +inum=1016*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode16 no66_prefix repne OVERRIDE_SEG0() +inum=1017*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode32 66_prefix repne OVERRIDE_SEG0() +inum=1018*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0() +inum=1019*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode16 no66_prefix norep OVERRIDE_SEG0() +inum=1020*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode32 66_prefix norep OVERRIDE_SEG0() +inum=1021*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0() +inum=1022*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode16 66_prefix repe OVERRIDE_SEG0() +inum=1023*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode32 no66_prefix repe OVERRIDE_SEG0() +inum=1024*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0() +inum=1025*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode16 66_prefix repne OVERRIDE_SEG0() +inum=1026*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode32 no66_prefix repne OVERRIDE_SEG0() +inum=1027*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0() +inum=1028*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode16 66_prefix norep OVERRIDE_SEG0() +inum=1029*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode32 no66_prefix norep OVERRIDE_SEG0() +inum=1030*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0() +inum=1031*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 rexw_prefix repe OVERRIDE_SEG0() +inum=1032*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 rexw_prefix repne OVERRIDE_SEG0() +inum=1033*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAD mode64 rexw_prefix norep OVERRIDE_SEG0() +inum=1034*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xAE repe +inum=1035*/ xed3_capture_nt_nop, +/* +0xAE repne +inum=1036*/ xed3_capture_nt_nop, +/* +0xAE norep +inum=1037*/ xed3_capture_nt_nop, +/* +0xAF mode16 no66_prefix repe +inum=1038*/ xed3_capture_nt_nop, +/* +0xAF mode32 66_prefix repe +inum=1039*/ xed3_capture_nt_nop, +/* +0xAF mode64 norexw_prefix 66_prefix repe +inum=1040*/ xed3_capture_nt_nop, +/* +0xAF mode16 no66_prefix repne +inum=1041*/ xed3_capture_nt_nop, +/* +0xAF mode32 66_prefix repne +inum=1042*/ xed3_capture_nt_nop, +/* +0xAF mode64 norexw_prefix 66_prefix repne +inum=1043*/ xed3_capture_nt_nop, +/* +0xAF mode16 no66_prefix norep +inum=1044*/ xed3_capture_nt_nop, +/* +0xAF mode32 66_prefix norep +inum=1045*/ xed3_capture_nt_nop, +/* +0xAF mode64 norexw_prefix 66_prefix norep +inum=1046*/ xed3_capture_nt_nop, +/* +0xAF mode16 66_prefix repe +inum=1047*/ xed3_capture_nt_nop, +/* +0xAF mode32 no66_prefix repe +inum=1048*/ xed3_capture_nt_nop, +/* +0xAF mode64 norexw_prefix no66_prefix repe +inum=1049*/ xed3_capture_nt_nop, +/* +0xAF mode16 66_prefix repne +inum=1050*/ xed3_capture_nt_nop, +/* +0xAF mode32 no66_prefix repne +inum=1051*/ xed3_capture_nt_nop, +/* +0xAF mode64 norexw_prefix no66_prefix repne +inum=1052*/ xed3_capture_nt_nop, +/* +0xAF mode16 66_prefix norep +inum=1053*/ xed3_capture_nt_nop, +/* +0xAF mode32 no66_prefix norep +inum=1054*/ xed3_capture_nt_nop, +/* +0xAF mode64 norexw_prefix no66_prefix norep +inum=1055*/ xed3_capture_nt_nop, +/* +0xAF mode64 rexw_prefix repe +inum=1056*/ xed3_capture_nt_nop, +/* +0xAF mode64 rexw_prefix repne +inum=1057*/ xed3_capture_nt_nop, +/* +0xAF mode64 rexw_prefix norep +inum=1058*/ xed3_capture_nt_nop, +/* +0xC2 DF64() UIMM16() IMMUNE66_LOOP64() +inum=1059*/ xed3_capture_chain_DF64_UIMM16_IMMUNE66_LOOP64, +/* +0xC3 DF64() IMMUNE66_LOOP64() +inum=1060*/ xed3_capture_chain_DF64_IMMUNE66_LOOP64, +/* +0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +inum=1061*/ xed3_capture_chain_MODRM, +/* +0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +inum=1062*/ xed3_capture_chain_MODRM, +/* +0xC8 DF64() UIMM16() UIMM8_1() +inum=1063*/ xed3_capture_chain_DF64_UIMM16_UIMM8_1, +/* +0xC9 DF64() +inum=1064*/ xed3_capture_chain_DF64, +/* +0xCA UIMM16() +inum=1065*/ xed3_capture_chain_UIMM16, +/* +0xCB +inum=1066*/ xed3_capture_nt_nop, +/* +0xCC +inum=1067*/ xed3_capture_nt_nop, +/* +0xCD UIMM8() +inum=1068*/ xed3_capture_chain_UIMM8, +/* +0xCE not64 +inum=1069*/ xed3_capture_nt_nop, +/* +0xCF mode16 no66_prefix +inum=1070*/ xed3_capture_nt_nop, +/* +0xCF mode32 66_prefix +inum=1071*/ xed3_capture_nt_nop, +/* +0xCF mode64 norexw_prefix 66_prefix +inum=1072*/ xed3_capture_nt_nop, +/* +0xCF mode16 66_prefix +inum=1073*/ xed3_capture_nt_nop, +/* +0xCF mode32 no66_prefix +inum=1074*/ xed3_capture_nt_nop, +/* +0xCF mode64 norexw_prefix no66_prefix +inum=1075*/ xed3_capture_nt_nop, +/* +0xCF mode64 rexw_prefix +inum=1076*/ xed3_capture_nt_nop, +/* +0xD4 not64 UIMM8() +inum=1077*/ xed3_capture_chain_UIMM8, +/* +0xD5 not64 UIMM8() +inum=1078*/ xed3_capture_chain_UIMM8, +/* +0xD6 not64 +inum=1079*/ xed3_capture_nt_nop, +/* +0xD7 OVERRIDE_SEG0() +inum=1080*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1081*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1082*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1083*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1084*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1085*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1086*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1087*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1088*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE2 DF64() BRDISP8() IMMUNE66_LOOP64() +inum=1089*/ xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64, +/* +0xE3 eamode16 BRDISP8() +inum=1090*/ xed3_capture_chain_BRDISP8, +/* +0xE3 eamode32 not64 BRDISP8() +inum=1091*/ xed3_capture_chain_BRDISP8, +/* +0xE3 eamode32 mode64 BRDISP8() FORCE64() +inum=1092*/ xed3_capture_chain_BRDISP8_FORCE64, +/* +0xE3 eamode64 BRDISP8() FORCE64() +inum=1093*/ xed3_capture_chain_BRDISP8_FORCE64, +/* +0xE4 UIMM8() +inum=1094*/ xed3_capture_chain_UIMM8, +/* +0xE5 UIMM8() IMMUNE_REXW() +inum=1095*/ xed3_capture_chain_UIMM8_IMMUNE_REXW, +/* +0xEC +inum=1096*/ xed3_capture_nt_nop, +/* +0xED IMMUNE_REXW() +inum=1097*/ xed3_capture_chain_IMMUNE_REXW, +/* +0xE6 UIMM8() +inum=1098*/ xed3_capture_chain_UIMM8, +/* +0xE7 UIMM8() IMMUNE_REXW() +inum=1099*/ xed3_capture_chain_UIMM8_IMMUNE_REXW, +/* +0xEE +inum=1100*/ xed3_capture_nt_nop, +/* +0xEF IMMUNE_REXW() +inum=1101*/ xed3_capture_chain_IMMUNE_REXW, +/* +0xF1 +inum=1102*/ xed3_capture_nt_nop, +/* +0xF4 +inum=1103*/ xed3_capture_nt_nop, +/* +0xF5 +inum=1104*/ xed3_capture_nt_nop, +/* +0xF8 +inum=1105*/ xed3_capture_nt_nop, +/* +0xF9 +inum=1106*/ xed3_capture_nt_nop, +/* +0xFA +inum=1107*/ xed3_capture_nt_nop, +/* +0xFB +inum=1108*/ xed3_capture_nt_nop, +/* +0xFC +inum=1109*/ xed3_capture_nt_nop, +/* +0xFD +inum=1110*/ xed3_capture_nt_nop, +/* +0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1111*/ xed3_capture_chain_MODRM, +/* +0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1112*/ xed3_capture_nt_nop, +/* +0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1113*/ xed3_capture_chain_MODRM, +/* +0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1114*/ xed3_capture_nt_nop, +/* +0x0F 0x05 mode64 FORCE64() +inum=1115*/ xed3_capture_chain_FORCE64, +/* +0x0F 0x06 +inum=1116*/ xed3_capture_nt_nop, +/* +0x0F 0x07 mode64 norexw_prefix +inum=1117*/ xed3_capture_nt_nop, +/* +0x0F 0x07 mode64 rexw_prefix +inum=1118*/ xed3_capture_nt_nop, +/* +0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1119*/ xed3_capture_chain_MODRM, +/* +0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1120*/ xed3_capture_nt_nop, +/* +0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1121*/ xed3_capture_chain_MODRM, +/* +0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1122*/ xed3_capture_nt_nop, +/* +0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1123*/ xed3_capture_chain_MODRM, +/* +0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1124*/ xed3_capture_nt_nop, +/* +0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1125*/ xed3_capture_chain_MODRM, +/* +0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1126*/ xed3_capture_nt_nop, +/* +0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1127*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1128*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1129*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1130*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1131*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1132*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1133*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1134*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1135*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1136*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1137*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1138*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1139*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1140*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1141*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1142*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1143*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1144*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1145*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1146*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1147*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1148*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1149*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1150*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1151*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1152*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +inum=1153*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +inum=1154*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +inum=1155*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +inum=1156*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +inum=1157*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +inum=1158*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64 +inum=1159*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64 +inum=1160*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x30 +inum=1161*/ xed3_capture_nt_nop, +/* +0x0F 0x31 +inum=1162*/ xed3_capture_nt_nop, +/* +0x0F 0x32 +inum=1163*/ xed3_capture_nt_nop, +/* +0x0F 0x33 +inum=1164*/ xed3_capture_nt_nop, +/* +0x0F 0x34 not64 +inum=1165*/ xed3_capture_nt_nop, +/* +0x0F 0x34 mode64 +inum=1166*/ xed3_capture_nt_nop, +/* +0x0F 0x35 not64 +inum=1167*/ xed3_capture_nt_nop, +/* +0x0F 0x35 mode64 +inum=1168*/ xed3_capture_nt_nop, +/* +0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1169*/ xed3_capture_chain_MODRM, +/* +0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1170*/ xed3_capture_nt_nop, +/* +0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1171*/ xed3_capture_chain_MODRM, +/* +0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1172*/ xed3_capture_nt_nop, +/* +0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1173*/ xed3_capture_chain_MODRM, +/* +0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1174*/ xed3_capture_nt_nop, +/* +0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1175*/ xed3_capture_chain_MODRM, +/* +0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1176*/ xed3_capture_nt_nop, +/* +0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1177*/ xed3_capture_chain_MODRM, +/* +0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1178*/ xed3_capture_nt_nop, +/* +0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1179*/ xed3_capture_chain_MODRM, +/* +0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1180*/ xed3_capture_nt_nop, +/* +0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1181*/ xed3_capture_chain_MODRM, +/* +0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1182*/ xed3_capture_nt_nop, +/* +0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1183*/ xed3_capture_chain_MODRM, +/* +0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1184*/ xed3_capture_nt_nop, +/* +0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1185*/ xed3_capture_nt_nop, +/* +0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1186*/ xed3_capture_chain_MODRM, +/* +0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1187*/ xed3_capture_nt_nop, +/* +0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1188*/ xed3_capture_chain_MODRM, +/* +0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1189*/ xed3_capture_nt_nop, +/* +0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1190*/ xed3_capture_chain_MODRM, +/* +0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1191*/ xed3_capture_nt_nop, +/* +0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1192*/ xed3_capture_chain_MODRM, +/* +0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1193*/ xed3_capture_nt_nop, +/* +0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1194*/ xed3_capture_chain_MODRM, +/* +0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1195*/ xed3_capture_nt_nop, +/* +0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1196*/ xed3_capture_chain_MODRM, +/* +0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1197*/ xed3_capture_nt_nop, +/* +0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1198*/ xed3_capture_chain_MODRM, +/* +0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1199*/ xed3_capture_nt_nop, +/* +0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1200*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1201*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1202*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1203*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1204*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1205*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1206*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1207*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1208*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1209*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1210*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1211*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1212*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1213*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1214*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1215*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1216*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1217*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1218*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1219*/ xed3_capture_chain_MODRM, +/* +0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1220*/ xed3_capture_nt_nop, +/* +0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1221*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1222*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1223*/ xed3_capture_chain_MODRM, +/* +0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1224*/ xed3_capture_nt_nop, +/* +0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1225*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1226*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1227*/ xed3_capture_chain_MODRM, +/* +0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1228*/ xed3_capture_nt_nop, +/* +0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1229*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1230*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1231*/ xed3_capture_chain_MODRM, +/* +0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1232*/ xed3_capture_nt_nop, +/* +0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1233*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1234*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1235*/ xed3_capture_chain_MODRM, +/* +0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1236*/ xed3_capture_nt_nop, +/* +0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1237*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1238*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1239*/ xed3_capture_chain_MODRM, +/* +0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1240*/ xed3_capture_nt_nop, +/* +0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1241*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1242*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1243*/ xed3_capture_chain_MODRM, +/* +0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1244*/ xed3_capture_nt_nop, +/* +0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1245*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1246*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1247*/ xed3_capture_chain_MODRM, +/* +0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1248*/ xed3_capture_nt_nop, +/* +0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1249*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1250*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1251*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1252*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1253*/ xed3_capture_chain_MODRM, +/* +0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1254*/ xed3_capture_nt_nop, +/* +0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1255*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1256*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1257*/ xed3_capture_chain_MODRM, +/* +0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1258*/ xed3_capture_nt_nop, +/* +0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1259*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1260*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1261*/ xed3_capture_chain_MODRM, +/* +0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1262*/ xed3_capture_nt_nop, +/* +0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1263*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1264*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x77 no_refining_prefix +inum=1265*/ xed3_capture_nt_nop, +/* +0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1266*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1267*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +inum=1268*/ xed3_capture_chain_IGNORE66_MODRM_UIMM8, +/* +0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +inum=1269*/ xed3_capture_chain_IGNORE66_UIMM8, +/* +0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +inum=1270*/ xed3_capture_chain_IGNORE66_MODRM_UIMM8, +/* +0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +inum=1271*/ xed3_capture_chain_IGNORE66_UIMM8, +/* +0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1272*/ xed3_capture_chain_MODRM, +/* +0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1273*/ xed3_capture_nt_nop, +/* +0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1274*/ xed3_capture_chain_MODRM, +/* +0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1275*/ xed3_capture_nt_nop, +/* +0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1276*/ xed3_capture_chain_MODRM, +/* +0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1277*/ xed3_capture_nt_nop, +/* +0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1278*/ xed3_capture_chain_MODRM, +/* +0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1279*/ xed3_capture_nt_nop, +/* +0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1280*/ xed3_capture_chain_MODRM, +/* +0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1281*/ xed3_capture_nt_nop, +/* +0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1282*/ xed3_capture_chain_MODRM, +/* +0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1283*/ xed3_capture_nt_nop, +/* +0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1284*/ xed3_capture_chain_MODRM, +/* +0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1285*/ xed3_capture_nt_nop, +/* +0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1286*/ xed3_capture_chain_MODRM, +/* +0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1287*/ xed3_capture_nt_nop, +/* +0x0F 0xA2 +inum=1288*/ xed3_capture_nt_nop, +/* +0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=1289*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=1290*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=1291*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1292*/ xed3_capture_nt_nop, +/* +0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=1293*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1294*/ xed3_capture_nt_nop, +/* +0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1295*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1296*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1297*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1298*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1299*/ xed3_capture_nt_nop, +/* +0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1300*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1301*/ xed3_capture_nt_nop, +/* +0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=1302*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix +inum=1303*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=1304*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1305*/ xed3_capture_nt_nop, +/* +0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix +inum=1306*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1307*/ xed3_capture_nt_nop, +/* +0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1308*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1309*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +inum=1310*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +inum=1311*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +inum=1312*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1313*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1314*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1315*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1316*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1317*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1318*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1319*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1320*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +inum=1321*/ xed3_capture_chain_IGNORE66_MODRM_UIMM8, +/* +0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +inum=1322*/ xed3_capture_chain_IGNORE66_UIMM8, +/* +0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1323*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1324*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1325*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1326*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8() +inum=1327*/ xed3_capture_chain_IGNORE66_MODRM_UIMM8, +/* +0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8() +inum=1328*/ xed3_capture_chain_IGNORE66_UIMM8, +/* +0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1329*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1330*/ xed3_capture_nt_nop, +/* +0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1331*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1332*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1333*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1334*/ xed3_capture_nt_nop, +/* +0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1335*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1336*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1337*/ xed3_capture_nt_nop, +/* +0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1338*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1339*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1340*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1341*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1342*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1343*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1344*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1345*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1346*/ xed3_capture_nt_nop, +/* +0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1347*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1348*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1349*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1350*/ xed3_capture_nt_nop, +/* +0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1351*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1352*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1353*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1354*/ xed3_capture_nt_nop, +/* +0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1355*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1356*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1357*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1358*/ xed3_capture_nt_nop, +/* +0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1359*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1360*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1361*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1362*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1363*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1364*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1365*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1366*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1367*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1368*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1369*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1370*/ xed3_capture_nt_nop, +/* +0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1371*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1372*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1373*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1374*/ xed3_capture_nt_nop, +/* +0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1375*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1376*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1377*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1378*/ xed3_capture_nt_nop, +/* +0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1379*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1380*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0() +inum=1381*/ xed3_capture_chain_OVERRIDE_SEG0, +/* +0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0() +inum=1382*/ xed3_capture_chain_REFINING66_OVERRIDE_SEG0, +/* +0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix +inum=1383*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x08 +inum=1384*/ xed3_capture_nt_nop, +/* +0x0F 0xFF MODE_SHORT_UD0=1 +inum=1385*/ xed3_capture_nt_nop, +/* +0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1386*/ xed3_capture_chain_MODRM, +/* +0x0F 0xFF MODE_SHORT_UD0=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1387*/ xed3_capture_nt_nop, +/* +0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1388*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1389*/ xed3_capture_nt_nop, +/* +0x0F 0x0B +inum=1390*/ xed3_capture_nt_nop, +/* +0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1391*/ xed3_capture_chain_MODRM, +/* +0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1392*/ xed3_capture_nt_nop, +/* +0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1393*/ xed3_capture_chain_MODRM, +/* +0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1394*/ xed3_capture_nt_nop, +/* +0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1395*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1396*/ xed3_capture_nt_nop, +/* +0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1397*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1398*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1399*/ xed3_capture_nt_nop, +/* +0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1400*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1401*/ xed3_capture_nt_nop, +/* +0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1402*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1403*/ xed3_capture_nt_nop, +/* +0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1404*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1405*/ xed3_capture_nt_nop, +/* +0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +inum=1406*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +inum=1407*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +inum=1408*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +inum=1409*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +inum=1410*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +inum=1411*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +inum=1412*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +inum=1413*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +inum=1414*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +inum=1415*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +inum=1416*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +inum=1417*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1418*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1419*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1420*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1421*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1422*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1423*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1424*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1425*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1426*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1427*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1428*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1429*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1430*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1431*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1432*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +inum=1433*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +inum=1434*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +inum=1435*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +inum=1436*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +inum=1437*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +inum=1438*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +inum=1439*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +inum=1440*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM() +inum=1441*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix +inum=1442*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM() +inum=1443*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix +inum=1444*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1445*/ xed3_capture_chain_MODRM, +/* +0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1446*/ xed3_capture_nt_nop, +/* +0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1447*/ xed3_capture_chain_MODRM, +/* +0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1448*/ xed3_capture_nt_nop, +/* +0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1449*/ xed3_capture_chain_MODRM, +/* +0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1450*/ xed3_capture_nt_nop, +/* +0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1451*/ xed3_capture_chain_MODRM, +/* +0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1452*/ xed3_capture_nt_nop, +/* +0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1453*/ xed3_capture_chain_MODRM, +/* +0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1454*/ xed3_capture_nt_nop, +/* +0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1455*/ xed3_capture_chain_MODRM, +/* +0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1456*/ xed3_capture_nt_nop, +/* +0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1457*/ xed3_capture_chain_MODRM, +/* +0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1458*/ xed3_capture_nt_nop, +/* +0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1459*/ xed3_capture_chain_MODRM, +/* +0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1460*/ xed3_capture_nt_nop, +/* +0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1461*/ xed3_capture_chain_MODRM, +/* +0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1462*/ xed3_capture_nt_nop, +/* +0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1463*/ xed3_capture_chain_MODRM, +/* +0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1464*/ xed3_capture_nt_nop, +/* +0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1465*/ xed3_capture_chain_MODRM, +/* +0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1466*/ xed3_capture_nt_nop, +/* +0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1467*/ xed3_capture_chain_MODRM, +/* +0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1468*/ xed3_capture_nt_nop, +/* +0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1469*/ xed3_capture_chain_MODRM, +/* +0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1470*/ xed3_capture_nt_nop, +/* +0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1471*/ xed3_capture_chain_MODRM, +/* +0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1472*/ xed3_capture_nt_nop, +/* +0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1473*/ xed3_capture_chain_MODRM, +/* +0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1474*/ xed3_capture_nt_nop, +/* +0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1475*/ xed3_capture_chain_MODRM, +/* +0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1476*/ xed3_capture_nt_nop, +/* +0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1477*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1478*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1479*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1480*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1481*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1482*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1483*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1484*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1485*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1486*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1487*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1488*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1489*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1490*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1491*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1492*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1493*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1494*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1495*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1496*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1497*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1498*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1499*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1500*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1501*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1502*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1503*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1504*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1505*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1506*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1507*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1508*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1509*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1510*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1511*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1512*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1513*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1514*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1515*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1516*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1517*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1518*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1519*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1520*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1521*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1522*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1523*/ xed3_capture_chain_MODRM, +/* +0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1524*/ xed3_capture_nt_nop, +/* +0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1525*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1526*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1527*/ xed3_capture_chain_MODRM, +/* +0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1528*/ xed3_capture_nt_nop, +/* +0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1529*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1530*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1531*/ xed3_capture_chain_MODRM, +/* +0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1532*/ xed3_capture_nt_nop, +/* +0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1533*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1534*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1535*/ xed3_capture_chain_MODRM, +/* +0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1536*/ xed3_capture_nt_nop, +/* +0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1537*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1538*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +inum=1539*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +inum=1540*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +inum=1541*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +inum=1542*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM() +inum=1543*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix +inum=1544*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() +inum=1545*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64 +inum=1546*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +inum=1547*/ xed3_capture_chain_MODRM, +/* +0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +inum=1548*/ xed3_capture_nt_nop, +/* +0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +inum=1549*/ xed3_capture_chain_MODRM, +/* +0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +inum=1550*/ xed3_capture_nt_nop, +/* +0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM() +inum=1551*/ xed3_capture_chain_MODRM, +/* +0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix +inum=1552*/ xed3_capture_nt_nop, +/* +0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() +inum=1553*/ xed3_capture_chain_MODRM, +/* +0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 +inum=1554*/ xed3_capture_nt_nop, +/* +0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +inum=1555*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +inum=1556*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM() +inum=1557*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix +inum=1558*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1559*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1560*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1561*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1562*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +inum=1563*/ xed3_capture_chain_MODRM, +/* +0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +inum=1564*/ xed3_capture_nt_nop, +/* +0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM() +inum=1565*/ xed3_capture_chain_MODRM, +/* +0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix +inum=1566*/ xed3_capture_nt_nop, +/* +0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1567*/ xed3_capture_chain_MODRM, +/* +0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1568*/ xed3_capture_nt_nop, +/* +0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1569*/ xed3_capture_chain_MODRM, +/* +0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1570*/ xed3_capture_nt_nop, +/* +0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1571*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1572*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1573*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1574*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1575*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1576*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1577*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1578*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +inum=1579*/ xed3_capture_chain_MODRM_CR_WIDTH, +/* +0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +inum=1580*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +inum=1581*/ xed3_capture_chain_MODRM_CR_WIDTH, +/* +0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +inum=1582*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH() +inum=1583*/ xed3_capture_chain_MODRM_CR_WIDTH, +/* +0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH() +inum=1584*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH() +inum=1585*/ xed3_capture_chain_MODRM_CR_WIDTH, +/* +0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH() +inum=1586*/ xed3_capture_chain_CR_WIDTH, +/* +0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1587*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1588*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1589*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1590*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1591*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1592*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1593*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1594*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1595*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1596*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() +inum=1597*/ xed3_capture_chain_IGNORE66_MODRM, +/* +0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() +inum=1598*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1599*/ xed3_capture_chain_MODRM, +/* +0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1600*/ xed3_capture_nt_nop, +/* +0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1601*/ xed3_capture_chain_MODRM, +/* +0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1602*/ xed3_capture_nt_nop, +/* +0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1603*/ xed3_capture_chain_MODRM, +/* +0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1604*/ xed3_capture_nt_nop, +/* +0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1605*/ xed3_capture_chain_MODRM, +/* +0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1606*/ xed3_capture_nt_nop, +/* +0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1607*/ xed3_capture_chain_MODRM, +/* +0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1608*/ xed3_capture_nt_nop, +/* +0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1609*/ xed3_capture_chain_MODRM, +/* +0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1610*/ xed3_capture_nt_nop, +/* +0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1611*/ xed3_capture_chain_MODRM, +/* +0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1612*/ xed3_capture_nt_nop, +/* +0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1613*/ xed3_capture_chain_MODRM, +/* +0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1614*/ xed3_capture_nt_nop, +/* +0x0F 0xAA +inum=1615*/ xed3_capture_nt_nop, +/* +0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1616*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1617*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1618*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1619*/ xed3_capture_nt_nop, +/* +0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1620*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1621*/ xed3_capture_chain_UIMM8, +/* +0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1622*/ xed3_capture_chain_MODRM, +/* +0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1623*/ xed3_capture_nt_nop, +/* +0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1624*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1625*/ xed3_capture_nt_nop, +/* +0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1626*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1627*/ xed3_capture_nt_nop, +/* +0x0F 0b1100_1 SRM[rrr] +inum=1628*/ xed3_capture_nt_nop, +/* +0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1629*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1630*/ xed3_capture_nt_nop, +/* +0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1631*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1632*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1633*/ xed3_capture_chain_MODRM, +/* +0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1634*/ xed3_capture_nt_nop, +/* +0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1635*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1636*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1637*/ xed3_capture_chain_MODRM, +/* +0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1638*/ xed3_capture_nt_nop, +/* +0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1639*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1640*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1641*/ xed3_capture_chain_MODRM, +/* +0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1642*/ xed3_capture_nt_nop, +/* +0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1643*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1644*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1645*/ xed3_capture_chain_MODRM, +/* +0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1646*/ xed3_capture_nt_nop, +/* +0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1647*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1648*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1649*/ xed3_capture_chain_MODRM, +/* +0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1650*/ xed3_capture_nt_nop, +/* +0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1651*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1652*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1653*/ xed3_capture_chain_MODRM, +/* +0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1654*/ xed3_capture_nt_nop, +/* +0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1655*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1656*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1657*/ xed3_capture_chain_MODRM, +/* +0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1658*/ xed3_capture_nt_nop, +/* +0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1659*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1660*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1661*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1662*/ xed3_capture_nt_nop, +/* +0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1663*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1664*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1665*/ xed3_capture_chain_MODRM, +/* +0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1666*/ xed3_capture_nt_nop, +/* +0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1667*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1668*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1669*/ xed3_capture_chain_MODRM, +/* +0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1670*/ xed3_capture_nt_nop, +/* +0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1671*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1672*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1673*/ xed3_capture_chain_MODRM, +/* +0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1674*/ xed3_capture_nt_nop, +/* +0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1675*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1676*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1677*/ xed3_capture_chain_MODRM, +/* +0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1678*/ xed3_capture_nt_nop, +/* +0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1679*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1680*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1681*/ xed3_capture_chain_MODRM, +/* +0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1682*/ xed3_capture_nt_nop, +/* +0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1683*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1684*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1685*/ xed3_capture_chain_MODRM, +/* +0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1686*/ xed3_capture_nt_nop, +/* +0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1687*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1688*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1689*/ xed3_capture_chain_MODRM, +/* +0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1690*/ xed3_capture_nt_nop, +/* +0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1691*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1692*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1693*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1694*/ xed3_capture_nt_nop, +/* +0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1695*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1696*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1697*/ xed3_capture_chain_MODRM, +/* +0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1698*/ xed3_capture_nt_nop, +/* +0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1699*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1700*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1701*/ xed3_capture_chain_MODRM, +/* +0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1702*/ xed3_capture_nt_nop, +/* +0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1703*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1704*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1705*/ xed3_capture_chain_MODRM, +/* +0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1706*/ xed3_capture_nt_nop, +/* +0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1707*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1708*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1709*/ xed3_capture_chain_MODRM, +/* +0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1710*/ xed3_capture_nt_nop, +/* +0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1711*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1712*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1713*/ xed3_capture_chain_MODRM, +/* +0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1714*/ xed3_capture_nt_nop, +/* +0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1715*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1716*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1717*/ xed3_capture_chain_MODRM, +/* +0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1718*/ xed3_capture_nt_nop, +/* +0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1719*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1720*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1721*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1722*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1723*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1724*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1725*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1726*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1727*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1728*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1729*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1730*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1731*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1732*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1733*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1734*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1735*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1736*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1737*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1738*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1739*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1740*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1741*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1742*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1743*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1744*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1745*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1746*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1747*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1748*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1749*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1750*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1751*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1752*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1753*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1754*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1755*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1756*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1757*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1758*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1759*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1760*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1761*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1762*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1763*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1764*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1765*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1766*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1767*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1768*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1769*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1770*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1771*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1772*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1773*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1774*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1775*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1776*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1777*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1778*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1779*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1780*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1781*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1782*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1783*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1784*/ xed3_capture_chain_REFINING66, +/* +0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1785*/ xed3_capture_chain_MODRM, +/* +0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1786*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1787*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1788*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1789*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1790*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1791*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1792*/ xed3_capture_nt_nop, +/* +0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1793*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1794*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1795*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1796*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1797*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1798*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1799*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1800*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1801*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1802*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1803*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1804*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1805*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1806*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1807*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1808*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1809*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1810*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1811*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1812*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1813*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1814*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1815*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1816*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1817*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1818*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1819*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1820*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1821*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1822*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1823*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1824*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1825*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1826*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1827*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1828*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1829*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1830*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1831*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1832*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1833*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1834*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1835*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1836*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1837*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1838*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1839*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1840*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1841*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1842*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1843*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1844*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1845*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1846*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1847*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1848*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1849*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1850*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1851*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1852*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1853*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1854*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1855*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1856*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1857*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1858*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1859*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1860*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1861*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1862*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1863*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1864*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1865*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1866*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1867*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1868*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1869*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1870*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1871*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1872*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1873*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1874*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1875*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1876*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1877*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1878*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1879*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1880*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1881*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1882*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1883*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1884*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1885*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1886*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1887*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1888*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=1889*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1890*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1891*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1892*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1893*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1894*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1895*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1896*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1897*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1898*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1899*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1900*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1901*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1902*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1903*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1904*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1905*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1906*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1907*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=1908*/ xed3_capture_chain_IMMUNE66_MODRM_UIMM8, +/* +0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=1909*/ xed3_capture_chain_IMMUNE66_UIMM8, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix +inum=1910*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix +inum=1911*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM() +inum=1912*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM() +inum=1913*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM() +inum=1914*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM() +inum=1915*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1916*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=1917*/ xed3_capture_chain_MODRM, +/* +0x0F 0x37 no_refining_prefix +inum=1918*/ xed3_capture_nt_nop, +/* +0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1919*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1920*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1921*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1922*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1923*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1924*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1925*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1926*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1927*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1928*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() +inum=1929*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() +inum=1930*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8() +inum=1931*/ xed3_capture_chain_REFINING66_UIMM8, +/* +0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8() +inum=1932*/ xed3_capture_chain_REFINING66_MODRM_UIMM8, +/* +0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +inum=1933*/ xed3_capture_chain_REFINING66_MODRM_CR_WIDTH, +/* +0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +inum=1934*/ xed3_capture_chain_REFINING66_MODRM_CR_WIDTH, +/* +0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +inum=1935*/ xed3_capture_chain_REFINING66_MODRM_CR_WIDTH, +/* +0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +inum=1936*/ xed3_capture_chain_REFINING66_MODRM_CR_WIDTH, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() +inum=1937*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=1938*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=1939*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=1940*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=1941*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=1942*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=1943*/ xed3_capture_chain_MODRM, +/* +0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] not_refining +inum=1944*/ xed3_capture_nt_nop, +/* +0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix +inum=1945*/ xed3_capture_nt_nop, +/* +0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +inum=1946*/ xed3_capture_nt_nop, +/* +0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +inum=1947*/ xed3_capture_nt_nop, +/* +0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix +inum=1948*/ xed3_capture_nt_nop, +/* +0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix +inum=1949*/ xed3_capture_nt_nop, +/* +0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000] f3_refining_prefix +inum=1950*/ xed3_capture_nt_nop, +/* +0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix +inum=1951*/ xed3_capture_nt_nop, +/* +0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix +inum=1952*/ xed3_capture_nt_nop, +/* +0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16 +inum=1953*/ xed3_capture_nt_nop, +/* +0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32 +inum=1954*/ xed3_capture_nt_nop, +/* +0x0F 0x0E +inum=1955*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C +inum=1956*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C +inum=1957*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D +inum=1958*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D +inum=1959*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C +inum=1960*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C +inum=1961*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D +inum=1962*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D +inum=1963*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A +inum=1964*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A +inum=1965*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E +inum=1966*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E +inum=1967*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90 +inum=1968*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90 +inum=1969*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94 +inum=1970*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94 +inum=1971*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96 +inum=1972*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96 +inum=1973*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97 +inum=1974*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97 +inum=1975*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A +inum=1976*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A +inum=1977*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E +inum=1978*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E +inum=1979*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0 +inum=1980*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0 +inum=1981*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4 +inum=1982*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4 +inum=1983*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6 +inum=1984*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6 +inum=1985*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7 +inum=1986*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7 +inum=1987*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA +inum=1988*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA +inum=1989*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE +inum=1990*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE +inum=1991*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0 +inum=1992*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0 +inum=1993*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4 +inum=1994*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4 +inum=1995*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6 +inum=1996*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6 +inum=1997*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7 +inum=1998*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7 +inum=1999*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB +inum=2000*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB +inum=2001*/ xed3_capture_nt_nop, +/* +0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF +inum=2002*/ xed3_capture_chain_MODRM, +/* +0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF +inum=2003*/ xed3_capture_nt_nop, +/* +0x0F 0x05 not64 IGNORE66() +inum=2004*/ xed3_capture_chain_IGNORE66, +/* +0x0F 0x07 not64 +inum=2005*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000] +inum=2006*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001] +inum=2007*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010] +inum=2008*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011] +inum=2009*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100] +inum=2010*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101] +inum=2011*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110] +inum=2012*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] +inum=2013*/ xed3_capture_nt_nop, +/* +0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1() +inum=2014*/ xed3_capture_chain_REFINING66_UIMM8_UIMM8_1, +/* +0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2015*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1() +inum=2016*/ xed3_capture_chain_UIMM8_UIMM8_1, +/* +0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2017*/ xed3_capture_nt_nop, +/* +0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2018*/ xed3_capture_chain_MODRM, +/* +0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2019*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100] +inum=2020*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32 +inum=2021*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16 +inum=2022*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64 +inum=2023*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32 +inum=2024*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix +inum=2025*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix +inum=2026*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101] +inum=2027*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64 +inum=2028*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix +inum=2029*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64 +inum=2030*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64 +inum=2031*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32 +inum=2032*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64 +inum=2033*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix +inum=2034*/ xed3_capture_nt_nop, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +inum=2035*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +inum=2036*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64 +inum=2037*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64 +inum=2038*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +inum=2039*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +inum=2040*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +inum=2041*/ xed3_capture_nt_nop, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +inum=2042*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64 +inum=2043*/ xed3_capture_nt_nop, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64 +inum=2044*/ xed3_capture_nt_nop, +/* +0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +inum=2045*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +inum=2046*/ xed3_capture_chain_MODRM_REFINING66, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +inum=2047*/ xed3_capture_chain_MODRM_REFINING66, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +inum=2048*/ xed3_capture_chain_MODRM_REFINING66, +/* +0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66() +inum=2049*/ xed3_capture_chain_REFINING66, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32 +inum=2050*/ xed3_capture_chain_MODRM_REFINING66, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32 +inum=2051*/ xed3_capture_chain_MODRM_REFINING66, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64 +inum=2052*/ xed3_capture_chain_MODRM_REFINING66, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +inum=2053*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +inum=2054*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +inum=2055*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +inum=2056*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32 +inum=2057*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +inum=2058*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +inum=2059*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 +inum=2060*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM() +inum=2061*/ xed3_capture_chain_MODRM, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1 +inum=2062*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1 +inum=2063*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0 +inum=2064*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64 +inum=2065*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1 +inum=2066*/ xed3_capture_nt_nop, +/* +0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1 +inum=2067*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix +inum=2068*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix +inum=2069*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix +inum=2070*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0 +inum=2071*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64 +inum=2072*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 +inum=2073*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64 +inum=2074*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining +inum=2075*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=2076*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +inum=2077*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=2078*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +inum=2079*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=2080*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +inum=2081*/ xed3_capture_chain_MODRM, +/* +0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8() +inum=2082*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8() +inum=2083*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=2084*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +inum=2085*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=2086*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +inum=2087*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix +inum=2088*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix +inum=2089*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM() +inum=2090*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM() +inum=2091*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix +inum=2092*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix +inum=2093*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix +inum=2094*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix +inum=2095*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix +inum=2096*/ xed3_capture_chain_MODRM, +/* +0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix +inum=2097*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM() +inum=2098*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining +inum=2099*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix +inum=2100*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix +inum=2101*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix +inum=2102*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix +inum=2103*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix +inum=2104*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix +inum=2105*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix +inum=2106*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix +inum=2107*/ xed3_capture_nt_nop, +/* +0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64 +inum=2108*/ xed3_capture_nt_nop, +/* +0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64 +inum=2109*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix +inum=2110*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM() +inum=2111*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64 +inum=2112*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64 +inum=2113*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix +inum=2114*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix +inum=2115*/ xed3_capture_chain_MODRM, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix +inum=2116*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix +inum=2117*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix +inum=2118*/ xed3_capture_nt_nop, +/* +0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=1 +inum=2119*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix +inum=2120*/ xed3_capture_nt_nop, +/* +0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2121*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2122*/ xed3_capture_nt_nop, +/* +0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2123*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2124*/ xed3_capture_nt_nop, +/* +0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2125*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2126*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix +inum=2127*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH() +inum=2128*/ xed3_capture_chain_REFINING66_MODRM_CR_WIDTH, +/* +0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH() +inum=2129*/ xed3_capture_chain_REFINING66_MODRM_CR_WIDTH, +/* +0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2130*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2131*/ xed3_capture_nt_nop, +/* +0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2132*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2133*/ xed3_capture_nt_nop, +/* +0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2134*/ xed3_capture_chain_MODRM, +/* +0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2135*/ xed3_capture_nt_nop, +/* +0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz() +inum=2136*/ xed3_capture_chain_BRDISPz, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix +inum=2137*/ xed3_capture_nt_nop, +/* +0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8() +inum=2138*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix +inum=2139*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66() +inum=2140*/ xed3_capture_chain_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66() +inum=2141*/ xed3_capture_chain_MODRM_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() mode64 +inum=2142*/ xed3_capture_chain_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() mode64 +inum=2143*/ xed3_capture_chain_MODRM_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66() +inum=2144*/ xed3_capture_chain_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66() +inum=2145*/ xed3_capture_chain_MODRM_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() mode64 +inum=2146*/ xed3_capture_chain_IMMUNE66, +/* +0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() mode64 +inum=2147*/ xed3_capture_chain_MODRM_IMMUNE66, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix +inum=2148*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix +inum=2149*/ xed3_capture_nt_nop, +/* +0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM() +inum=2150*/ xed3_capture_chain_REFINING66_MODRM, +/* +0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=2151*/ xed3_capture_chain_MODRM, +/* +0x0F 0x09 WBNOINVD=0 +inum=2152*/ xed3_capture_nt_nop, +/* +0x0F 0x09 WBNOINVD=1 REP!=3 +inum=2153*/ xed3_capture_nt_nop, +/* +0x0F 0x09 WBNOINVD=1 f3_refining_prefix +inum=2154*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64 +inum=2155*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64 +inum=2156*/ xed3_capture_nt_nop, +/* +0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +inum=2157*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +inum=2158*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8() +inum=2159*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8() +inum=2160*/ xed3_capture_chain_MODRM_UIMM8, +/* +0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix +inum=2161*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix +inum=2162*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xDD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2163*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xDF f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2164*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() f3_refining_prefix +inum=2165*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() f3_refining_prefix +inum=2166*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xDC f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2167*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xDE f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2168*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix +inum=2169*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() f3_refining_prefix +inum=2170*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xFA MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +inum=2171*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xFB MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix +inum=2172*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xDC f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2173*/ xed3_capture_nt_nop, +/* +0x0F 0x3A 0xF0 MOD[0b11] MOD=3 REG[0b000] RM[0b000] f3_refining_prefix UIMM8() +inum=2174*/ xed3_capture_chain_UIMM8, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64 +inum=2175*/ xed3_capture_nt_nop, +/* +0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64 +inum=2176*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64 +inum=2177*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64 +inum=2178*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64 +inum=2179*/ xed3_capture_nt_nop, +/* +0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix +inum=2180*/ xed3_capture_chain_MODRM, +/* +0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix +inum=2181*/ xed3_capture_chain_MODRM, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix +inum=2182*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix +inum=2183*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix +inum=2184*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64 +inum=2185*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64 +inum=2186*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64 +inum=2187*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64 +inum=2188*/ xed3_capture_nt_nop, +/* +0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64 +inum=2189*/ xed3_capture_nt_nop, +/* +XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2190*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2191*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2192*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2193*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2194*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2195*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2196*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2197*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2198*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2199*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2200*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2201*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2202*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2203*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2204*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2205*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2206*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2207*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2208*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2209*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2210*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2211*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2212*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2213*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2214*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2215*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2216*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2217*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2218*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2219*/ xed3_capture_chain_UIMM8, +/* +XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2220*/ xed3_capture_chain_MODRM, +/* +XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2221*/ xed3_capture_nt_nop, +/* +XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2222*/ xed3_capture_chain_MODRM, +/* +XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2223*/ xed3_capture_nt_nop, +/* +XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2224*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2225*/ xed3_capture_chain_UIMM8, +/* +XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2226*/ xed3_capture_chain_MODRM, +/* +XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2227*/ xed3_capture_nt_nop, +/* +XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2228*/ xed3_capture_chain_MODRM, +/* +XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2229*/ xed3_capture_nt_nop, +/* +XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2230*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2231*/ xed3_capture_chain_UIMM8, +/* +XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2232*/ xed3_capture_chain_MODRM, +/* +XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2233*/ xed3_capture_nt_nop, +/* +XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2234*/ xed3_capture_chain_MODRM, +/* +XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2235*/ xed3_capture_nt_nop, +/* +XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2236*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2237*/ xed3_capture_chain_UIMM8, +/* +XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2238*/ xed3_capture_chain_MODRM, +/* +XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2239*/ xed3_capture_nt_nop, +/* +XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2240*/ xed3_capture_chain_MODRM, +/* +XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2241*/ xed3_capture_nt_nop, +/* +XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2242*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2243*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2244*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2245*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2246*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2247*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2248*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2249*/ xed3_capture_chain_SE_IMM8, +/* +XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2250*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2251*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2252*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2253*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2254*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2255*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2256*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2257*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2258*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2259*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2260*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2261*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2262*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2263*/ xed3_capture_chain_UIMM8, +/* +XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2264*/ xed3_capture_chain_MODRM_UIMM8, +/* +XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2265*/ xed3_capture_chain_UIMM8, +/* +XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2266*/ xed3_capture_chain_MODRM, +/* +XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2267*/ xed3_capture_nt_nop, +/* +XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2268*/ xed3_capture_chain_MODRM, +/* +XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2269*/ xed3_capture_nt_nop, +/* +XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2270*/ xed3_capture_chain_MODRM, +/* +XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2271*/ xed3_capture_nt_nop, +/* +XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2272*/ xed3_capture_chain_MODRM, +/* +XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2273*/ xed3_capture_nt_nop, +/* +XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2274*/ xed3_capture_chain_MODRM, +/* +XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2275*/ xed3_capture_nt_nop, +/* +XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2276*/ xed3_capture_chain_MODRM, +/* +XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2277*/ xed3_capture_nt_nop, +/* +XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2278*/ xed3_capture_chain_MODRM, +/* +XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2279*/ xed3_capture_nt_nop, +/* +XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2280*/ xed3_capture_chain_MODRM, +/* +XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2281*/ xed3_capture_nt_nop, +/* +XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2282*/ xed3_capture_chain_MODRM, +/* +XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2283*/ xed3_capture_nt_nop, +/* +XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2284*/ xed3_capture_chain_MODRM, +/* +XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2285*/ xed3_capture_nt_nop, +/* +XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2286*/ xed3_capture_chain_MODRM, +/* +XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2287*/ xed3_capture_nt_nop, +/* +XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2288*/ xed3_capture_chain_MODRM, +/* +XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2289*/ xed3_capture_nt_nop, +/* +XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2290*/ xed3_capture_chain_MODRM, +/* +XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2291*/ xed3_capture_nt_nop, +/* +XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2292*/ xed3_capture_chain_MODRM, +/* +XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2293*/ xed3_capture_nt_nop, +/* +XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2294*/ xed3_capture_chain_MODRM, +/* +XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2295*/ xed3_capture_nt_nop, +/* +XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2296*/ xed3_capture_chain_MODRM, +/* +XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2297*/ xed3_capture_nt_nop, +/* +XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2298*/ xed3_capture_chain_MODRM, +/* +XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2299*/ xed3_capture_nt_nop, +/* +XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2300*/ xed3_capture_chain_MODRM, +/* +XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2301*/ xed3_capture_nt_nop, +/* +XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2302*/ xed3_capture_chain_MODRM, +/* +XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2303*/ xed3_capture_nt_nop, +/* +XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2304*/ xed3_capture_chain_MODRM, +/* +XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2305*/ xed3_capture_nt_nop, +/* +XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2306*/ xed3_capture_chain_MODRM, +/* +XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2307*/ xed3_capture_nt_nop, +/* +XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2308*/ xed3_capture_chain_MODRM, +/* +XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2309*/ xed3_capture_nt_nop, +/* +XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2310*/ xed3_capture_chain_MODRM, +/* +XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2311*/ xed3_capture_nt_nop, +/* +XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2312*/ xed3_capture_chain_MODRM, +/* +XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2313*/ xed3_capture_nt_nop, +/* +XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2314*/ xed3_capture_chain_MODRM, +/* +XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2315*/ xed3_capture_nt_nop, +/* +XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2316*/ xed3_capture_chain_MODRM, +/* +XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2317*/ xed3_capture_nt_nop, +/* +XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2318*/ xed3_capture_chain_MODRM, +/* +XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2319*/ xed3_capture_nt_nop, +/* +XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2320*/ xed3_capture_chain_MODRM, +/* +XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2321*/ xed3_capture_nt_nop, +/* +XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2322*/ xed3_capture_chain_MODRM, +/* +XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2323*/ xed3_capture_nt_nop, +/* +XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2324*/ xed3_capture_chain_MODRM, +/* +XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2325*/ xed3_capture_nt_nop, +/* +XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2326*/ xed3_capture_chain_MODRM, +/* +XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2327*/ xed3_capture_nt_nop, +/* +XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2328*/ xed3_capture_chain_MODRM, +/* +XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2329*/ xed3_capture_nt_nop, +/* +XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2330*/ xed3_capture_chain_MODRM, +/* +XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2331*/ xed3_capture_nt_nop, +/* +XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2332*/ xed3_capture_chain_MODRM, +/* +XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2333*/ xed3_capture_nt_nop, +/* +XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2334*/ xed3_capture_chain_MODRM, +/* +XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2335*/ xed3_capture_nt_nop, +/* +XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2336*/ xed3_capture_chain_MODRM, +/* +XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2337*/ xed3_capture_nt_nop, +/* +XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2338*/ xed3_capture_chain_MODRM, +/* +XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2339*/ xed3_capture_nt_nop, +/* +XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +inum=2340*/ xed3_capture_chain_MODRM_UIMM32, +/* +XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32() +inum=2341*/ xed3_capture_chain_MODRM_UIMM32, +/* +XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +inum=2342*/ xed3_capture_chain_UIMM32, +/* +XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32() +inum=2343*/ xed3_capture_chain_UIMM32, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=2344*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=2345*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=2346*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=2347*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=2348*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=2349*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=2350*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=2351*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=2352*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=2353*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=2354*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=2355*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=2356*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() +inum=2357*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=2358*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn] +inum=2359*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=2360*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() +inum=2361*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=2362*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn] +inum=2363*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=2364*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=2365*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=2366*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=2367*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=2368*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() +inum=2369*/ xed3_capture_chain_MODRM, +/* +XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=2370*/ xed3_capture_nt_nop, +/* +XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn] +inum=2371*/ xed3_capture_nt_nop, +/* +XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=2372*/ xed3_capture_chain_MODRM, +/* +XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=2373*/ xed3_capture_chain_MODRM, +/* +XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=2374*/ xed3_capture_nt_nop, +/* +XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=2375*/ xed3_capture_nt_nop, +/* +XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=2376*/ xed3_capture_chain_MODRM, +/* +XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() +inum=2377*/ xed3_capture_chain_MODRM, +/* +XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=2378*/ xed3_capture_nt_nop, +/* +XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn] +inum=2379*/ xed3_capture_nt_nop, +/* +XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn] +inum=2380*/ xed3_capture_nt_nop, +/* +XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=2381*/ xed3_capture_nt_nop, +/* +XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32() +inum=2382*/ xed3_capture_chain_MODRM_UIMM32, +/* +XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32() +inum=2383*/ xed3_capture_chain_UIMM32, +/* +XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32() +inum=2384*/ xed3_capture_chain_MODRM_UIMM32, +/* +XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32() +inum=2385*/ xed3_capture_chain_UIMM32, +/* +VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2386*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2387*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2388*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2389*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2390*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2391*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2392*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2393*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2394*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2395*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2396*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2397*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2398*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2399*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2400*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2401*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2402*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2403*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2404*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2405*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2406*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2407*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2408*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2409*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2410*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2411*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2412*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2413*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2414*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2415*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2416*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2417*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2418*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2419*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2420*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2421*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2422*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2423*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2424*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2425*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2426*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2427*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2428*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2429*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2430*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2431*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2432*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2433*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2434*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2435*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2436*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2437*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2438*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2439*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2440*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2441*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2442*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2443*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2444*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2445*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2446*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2447*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2448*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2449*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2450*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2451*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2452*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2453*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2454*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2455*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2456*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2457*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2458*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2459*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2460*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2461*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2462*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2463*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2464*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2465*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2466*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2467*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2468*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2469*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2470*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2471*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2472*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2473*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2474*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2475*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2476*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2477*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2478*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2479*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2480*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2481*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2482*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2483*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2484*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2485*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2486*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2487*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2488*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2489*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2490*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2491*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2492*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2493*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2494*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2495*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2496*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2497*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2498*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2499*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2500*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2501*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2502*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2503*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2504*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2505*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2506*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2507*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2508*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2509*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2510*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2511*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2512*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2513*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2514*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2515*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2516*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2517*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2518*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2519*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2520*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2521*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2522*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2523*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2524*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2525*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2526*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2527*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=2528*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=2529*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2530*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2531*/ xed3_capture_nt_nop, +/* +VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2532*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2533*/ xed3_capture_nt_nop, +/* +VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2534*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2535*/ xed3_capture_nt_nop, +/* +VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2536*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2537*/ xed3_capture_nt_nop, +/* +VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2538*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2539*/ xed3_capture_nt_nop, +/* +VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2540*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2541*/ xed3_capture_nt_nop, +/* +VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2542*/ xed3_capture_chain_MODRM, +/* +VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2543*/ xed3_capture_nt_nop, +/* +VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2544*/ xed3_capture_chain_MODRM, +/* +VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2545*/ xed3_capture_nt_nop, +/* +VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2546*/ xed3_capture_chain_MODRM, +/* +VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2547*/ xed3_capture_nt_nop, +/* +VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2548*/ xed3_capture_chain_MODRM, +/* +VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2549*/ xed3_capture_nt_nop, +/* +VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2550*/ xed3_capture_chain_MODRM, +/* +VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2551*/ xed3_capture_nt_nop, +/* +VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2552*/ xed3_capture_chain_MODRM, +/* +VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2553*/ xed3_capture_nt_nop, +/* +VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2554*/ xed3_capture_chain_MODRM, +/* +VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2555*/ xed3_capture_nt_nop, +/* +VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2556*/ xed3_capture_chain_MODRM, +/* +VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2557*/ xed3_capture_nt_nop, +/* +VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2558*/ xed3_capture_chain_MODRM, +/* +VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2559*/ xed3_capture_nt_nop, +/* +VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2560*/ xed3_capture_chain_MODRM, +/* +VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2561*/ xed3_capture_nt_nop, +/* +VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2562*/ xed3_capture_chain_MODRM, +/* +VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2563*/ xed3_capture_nt_nop, +/* +VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2564*/ xed3_capture_chain_MODRM, +/* +VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2565*/ xed3_capture_nt_nop, +/* +VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2566*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2567*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2568*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2569*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2570*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2571*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2572*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2573*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2574*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2575*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2576*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2577*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2578*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2579*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2580*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2581*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2582*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2583*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2584*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2585*/ xed3_capture_chain_UIMM8, +/* +VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2586*/ xed3_capture_chain_MODRM, +/* +VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2587*/ xed3_capture_nt_nop, +/* +VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2588*/ xed3_capture_chain_MODRM, +/* +VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2589*/ xed3_capture_nt_nop, +/* +VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2590*/ xed3_capture_chain_MODRM, +/* +VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2591*/ xed3_capture_nt_nop, +/* +VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2592*/ xed3_capture_chain_MODRM, +/* +VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2593*/ xed3_capture_nt_nop, +/* +VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2594*/ xed3_capture_chain_MODRM, +/* +VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2595*/ xed3_capture_nt_nop, +/* +VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2596*/ xed3_capture_chain_MODRM, +/* +VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2597*/ xed3_capture_nt_nop, +/* +VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2598*/ xed3_capture_chain_MODRM, +/* +VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2599*/ xed3_capture_nt_nop, +/* +VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2600*/ xed3_capture_chain_MODRM, +/* +VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2601*/ xed3_capture_nt_nop, +/* +VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2602*/ xed3_capture_chain_MODRM, +/* +VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2603*/ xed3_capture_nt_nop, +/* +VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2604*/ xed3_capture_chain_MODRM, +/* +VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2605*/ xed3_capture_nt_nop, +/* +VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2606*/ xed3_capture_chain_MODRM, +/* +VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2607*/ xed3_capture_nt_nop, +/* +VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2608*/ xed3_capture_chain_MODRM, +/* +VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2609*/ xed3_capture_nt_nop, +/* +VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2610*/ xed3_capture_chain_MODRM, +/* +VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2611*/ xed3_capture_nt_nop, +/* +VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2612*/ xed3_capture_chain_MODRM, +/* +VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2613*/ xed3_capture_nt_nop, +/* +VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2614*/ xed3_capture_chain_MODRM, +/* +VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2615*/ xed3_capture_nt_nop, +/* +VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2616*/ xed3_capture_chain_MODRM, +/* +VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2617*/ xed3_capture_nt_nop, +/* +VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2618*/ xed3_capture_chain_MODRM, +/* +VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2619*/ xed3_capture_nt_nop, +/* +VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2620*/ xed3_capture_chain_MODRM, +/* +VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2621*/ xed3_capture_nt_nop, +/* +VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2622*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2623*/ xed3_capture_nt_nop, +/* +VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2624*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2625*/ xed3_capture_nt_nop, +/* +VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2626*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2627*/ xed3_capture_nt_nop, +/* +VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2628*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2629*/ xed3_capture_nt_nop, +/* +VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2630*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2631*/ xed3_capture_nt_nop, +/* +VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2632*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2633*/ xed3_capture_nt_nop, +/* +VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2634*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2635*/ xed3_capture_nt_nop, +/* +VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2636*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2637*/ xed3_capture_nt_nop, +/* +VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2638*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2639*/ xed3_capture_nt_nop, +/* +VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2640*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2641*/ xed3_capture_nt_nop, +/* +VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2642*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2643*/ xed3_capture_nt_nop, +/* +VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2644*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2645*/ xed3_capture_nt_nop, +/* +VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2646*/ xed3_capture_chain_MODRM, +/* +VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2647*/ xed3_capture_nt_nop, +/* +VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2648*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2649*/ xed3_capture_nt_nop, +/* +VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2650*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2651*/ xed3_capture_nt_nop, +/* +VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2652*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2653*/ xed3_capture_nt_nop, +/* +VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2654*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2655*/ xed3_capture_nt_nop, +/* +VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2656*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2657*/ xed3_capture_nt_nop, +/* +VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2658*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2659*/ xed3_capture_nt_nop, +/* +VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2660*/ xed3_capture_chain_MODRM, +/* +VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2661*/ xed3_capture_nt_nop, +/* +VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2662*/ xed3_capture_chain_MODRM, +/* +VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2663*/ xed3_capture_nt_nop, +/* +VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2664*/ xed3_capture_chain_MODRM, +/* +VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2665*/ xed3_capture_nt_nop, +/* +VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2666*/ xed3_capture_chain_MODRM, +/* +VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2667*/ xed3_capture_nt_nop, +/* +VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2668*/ xed3_capture_chain_MODRM, +/* +VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2669*/ xed3_capture_nt_nop, +/* +VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2670*/ xed3_capture_chain_MODRM, +/* +VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2671*/ xed3_capture_nt_nop, +/* +VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2672*/ xed3_capture_chain_MODRM, +/* +VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2673*/ xed3_capture_nt_nop, +/* +VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2674*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2675*/ xed3_capture_chain_UIMM8, +/* +VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2676*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2677*/ xed3_capture_chain_UIMM8, +/* +VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2678*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2679*/ xed3_capture_chain_UIMM8, +/* +VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2680*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2681*/ xed3_capture_chain_UIMM8, +/* +VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2682*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2683*/ xed3_capture_chain_UIMM8, +/* +VV1 0x77 VNP V0F VL256 NOVSR +inum=2684*/ xed3_capture_nt_nop, +/* +VV1 0x77 VNP V0F VL128 NOVSR +inum=2685*/ xed3_capture_nt_nop, +/* +VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2686*/ xed3_capture_chain_MODRM, +/* +VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2687*/ xed3_capture_nt_nop, +/* +VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2688*/ xed3_capture_chain_MODRM, +/* +VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2689*/ xed3_capture_nt_nop, +/* +VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2690*/ xed3_capture_chain_MODRM, +/* +VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2691*/ xed3_capture_nt_nop, +/* +VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2692*/ xed3_capture_chain_MODRM, +/* +VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2693*/ xed3_capture_nt_nop, +/* +VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2694*/ xed3_capture_chain_MODRM, +/* +VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2695*/ xed3_capture_nt_nop, +/* +VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2696*/ xed3_capture_chain_MODRM, +/* +VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2697*/ xed3_capture_nt_nop, +/* +VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2698*/ xed3_capture_chain_MODRM, +/* +VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2699*/ xed3_capture_nt_nop, +/* +VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2700*/ xed3_capture_chain_MODRM, +/* +VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2701*/ xed3_capture_nt_nop, +/* +VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2702*/ xed3_capture_chain_MODRM, +/* +VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2703*/ xed3_capture_nt_nop, +/* +VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2704*/ xed3_capture_chain_MODRM, +/* +VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2705*/ xed3_capture_nt_nop, +/* +VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2706*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2707*/ xed3_capture_chain_UIMM8, +/* +VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2708*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2709*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2710*/ xed3_capture_chain_MODRM, +/* +VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2711*/ xed3_capture_nt_nop, +/* +VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2712*/ xed3_capture_chain_MODRM, +/* +VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2713*/ xed3_capture_nt_nop, +/* +VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2714*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2715*/ xed3_capture_chain_UIMM8, +/* +VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2716*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2717*/ xed3_capture_chain_UIMM8, +/* +VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2718*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2719*/ xed3_capture_chain_UIMM8, +/* +VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2720*/ xed3_capture_chain_MODRM, +/* +VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2721*/ xed3_capture_chain_MODRM, +/* +VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2722*/ xed3_capture_nt_nop, +/* +VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2723*/ xed3_capture_nt_nop, +/* +VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2724*/ xed3_capture_chain_MODRM, +/* +VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2725*/ xed3_capture_nt_nop, +/* +VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2726*/ xed3_capture_chain_MODRM, +/* +VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2727*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2728*/ xed3_capture_chain_UIMM8, +/* +VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2729*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2730*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2731*/ xed3_capture_chain_MODRM, +/* +VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2732*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2733*/ xed3_capture_chain_MODRM, +/* +VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2734*/ xed3_capture_chain_MODRM, +/* +VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2735*/ xed3_capture_chain_MODRM, +/* +VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2736*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2737*/ xed3_capture_chain_MODRM, +/* +VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2738*/ xed3_capture_chain_MODRM, +/* +VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2739*/ xed3_capture_chain_MODRM, +/* +VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2740*/ xed3_capture_chain_MODRM, +/* +VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2741*/ xed3_capture_chain_MODRM, +/* +VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2742*/ xed3_capture_nt_nop, +/* +VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2743*/ xed3_capture_chain_MODRM, +/* +VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2744*/ xed3_capture_nt_nop, +/* +VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2745*/ xed3_capture_chain_MODRM, +/* +VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2746*/ xed3_capture_nt_nop, +/* +VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2747*/ xed3_capture_chain_MODRM, +/* +VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2748*/ xed3_capture_nt_nop, +/* +VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2749*/ xed3_capture_chain_MODRM, +/* +VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2750*/ xed3_capture_nt_nop, +/* +VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2751*/ xed3_capture_chain_MODRM, +/* +VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2752*/ xed3_capture_nt_nop, +/* +VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2753*/ xed3_capture_chain_MODRM, +/* +VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2754*/ xed3_capture_nt_nop, +/* +VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2755*/ xed3_capture_chain_MODRM, +/* +VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2756*/ xed3_capture_nt_nop, +/* +VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2757*/ xed3_capture_chain_MODRM, +/* +VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2758*/ xed3_capture_nt_nop, +/* +VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2759*/ xed3_capture_chain_MODRM, +/* +VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2760*/ xed3_capture_nt_nop, +/* +VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2761*/ xed3_capture_chain_MODRM, +/* +VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2762*/ xed3_capture_nt_nop, +/* +VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2763*/ xed3_capture_chain_MODRM, +/* +VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2764*/ xed3_capture_nt_nop, +/* +VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2765*/ xed3_capture_chain_MODRM, +/* +VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2766*/ xed3_capture_nt_nop, +/* +VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2767*/ xed3_capture_chain_MODRM, +/* +VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2768*/ xed3_capture_nt_nop, +/* +VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2769*/ xed3_capture_chain_MODRM, +/* +VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2770*/ xed3_capture_nt_nop, +/* +VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2771*/ xed3_capture_chain_MODRM, +/* +VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2772*/ xed3_capture_nt_nop, +/* +VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2773*/ xed3_capture_chain_MODRM, +/* +VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2774*/ xed3_capture_nt_nop, +/* +VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2775*/ xed3_capture_chain_MODRM, +/* +VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2776*/ xed3_capture_nt_nop, +/* +VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2777*/ xed3_capture_chain_MODRM, +/* +VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2778*/ xed3_capture_nt_nop, +/* +VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2779*/ xed3_capture_chain_MODRM, +/* +VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2780*/ xed3_capture_nt_nop, +/* +VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2781*/ xed3_capture_chain_MODRM, +/* +VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2782*/ xed3_capture_nt_nop, +/* +VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2783*/ xed3_capture_chain_MODRM, +/* +VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2784*/ xed3_capture_nt_nop, +/* +VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2785*/ xed3_capture_chain_MODRM, +/* +VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2786*/ xed3_capture_nt_nop, +/* +VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2787*/ xed3_capture_chain_MODRM, +/* +VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2788*/ xed3_capture_nt_nop, +/* +VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2789*/ xed3_capture_chain_MODRM, +/* +VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2790*/ xed3_capture_nt_nop, +/* +VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2791*/ xed3_capture_chain_MODRM, +/* +VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2792*/ xed3_capture_nt_nop, +/* +VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2793*/ xed3_capture_chain_MODRM, +/* +VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2794*/ xed3_capture_nt_nop, +/* +VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2795*/ xed3_capture_chain_MODRM, +/* +VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2796*/ xed3_capture_nt_nop, +/* +VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2797*/ xed3_capture_chain_MODRM, +/* +VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2798*/ xed3_capture_nt_nop, +/* +VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2799*/ xed3_capture_chain_MODRM, +/* +VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2800*/ xed3_capture_nt_nop, +/* +VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2801*/ xed3_capture_chain_MODRM, +/* +VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2802*/ xed3_capture_nt_nop, +/* +VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2803*/ xed3_capture_chain_MODRM, +/* +VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2804*/ xed3_capture_nt_nop, +/* +VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2805*/ xed3_capture_chain_MODRM, +/* +VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2806*/ xed3_capture_nt_nop, +/* +VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2807*/ xed3_capture_chain_MODRM, +/* +VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2808*/ xed3_capture_nt_nop, +/* +VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2809*/ xed3_capture_chain_MODRM, +/* +VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2810*/ xed3_capture_nt_nop, +/* +VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2811*/ xed3_capture_chain_MODRM, +/* +VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2812*/ xed3_capture_nt_nop, +/* +VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2813*/ xed3_capture_chain_MODRM, +/* +VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2814*/ xed3_capture_nt_nop, +/* +VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2815*/ xed3_capture_chain_MODRM, +/* +VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2816*/ xed3_capture_nt_nop, +/* +VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2817*/ xed3_capture_chain_MODRM, +/* +VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2818*/ xed3_capture_nt_nop, +/* +VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2819*/ xed3_capture_chain_MODRM, +/* +VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2820*/ xed3_capture_nt_nop, +/* +VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2821*/ xed3_capture_chain_MODRM, +/* +VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2822*/ xed3_capture_nt_nop, +/* +VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2823*/ xed3_capture_chain_MODRM, +/* +VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2824*/ xed3_capture_nt_nop, +/* +VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2825*/ xed3_capture_chain_MODRM, +/* +VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2826*/ xed3_capture_nt_nop, +/* +VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2827*/ xed3_capture_chain_MODRM, +/* +VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2828*/ xed3_capture_nt_nop, +/* +VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2829*/ xed3_capture_chain_MODRM, +/* +VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2830*/ xed3_capture_nt_nop, +/* +VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2831*/ xed3_capture_chain_MODRM, +/* +VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2832*/ xed3_capture_nt_nop, +/* +VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2833*/ xed3_capture_chain_MODRM, +/* +VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2834*/ xed3_capture_nt_nop, +/* +VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2835*/ xed3_capture_chain_MODRM, +/* +VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2836*/ xed3_capture_nt_nop, +/* +VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2837*/ xed3_capture_chain_MODRM, +/* +VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2838*/ xed3_capture_nt_nop, +/* +VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2839*/ xed3_capture_chain_MODRM, +/* +VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2840*/ xed3_capture_nt_nop, +/* +VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2841*/ xed3_capture_chain_MODRM, +/* +VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2842*/ xed3_capture_nt_nop, +/* +VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2843*/ xed3_capture_chain_MODRM, +/* +VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2844*/ xed3_capture_nt_nop, +/* +VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2845*/ xed3_capture_chain_MODRM, +/* +VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2846*/ xed3_capture_nt_nop, +/* +VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2847*/ xed3_capture_chain_MODRM, +/* +VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2848*/ xed3_capture_nt_nop, +/* +VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2849*/ xed3_capture_chain_MODRM, +/* +VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2850*/ xed3_capture_nt_nop, +/* +VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2851*/ xed3_capture_chain_MODRM, +/* +VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2852*/ xed3_capture_nt_nop, +/* +VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2853*/ xed3_capture_chain_MODRM, +/* +VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2854*/ xed3_capture_nt_nop, +/* +VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2855*/ xed3_capture_chain_MODRM, +/* +VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2856*/ xed3_capture_nt_nop, +/* +VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2857*/ xed3_capture_chain_MODRM, +/* +VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2858*/ xed3_capture_nt_nop, +/* +VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2859*/ xed3_capture_chain_MODRM, +/* +VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2860*/ xed3_capture_nt_nop, +/* +VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2861*/ xed3_capture_chain_MODRM, +/* +VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2862*/ xed3_capture_nt_nop, +/* +VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2863*/ xed3_capture_chain_MODRM, +/* +VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2864*/ xed3_capture_nt_nop, +/* +VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2865*/ xed3_capture_chain_MODRM, +/* +VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2866*/ xed3_capture_nt_nop, +/* +VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2867*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2868*/ xed3_capture_chain_UIMM8, +/* +VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2869*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2870*/ xed3_capture_chain_UIMM8, +/* +VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2871*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2872*/ xed3_capture_chain_UIMM8, +/* +VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2873*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2874*/ xed3_capture_chain_UIMM8, +/* +VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2875*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2876*/ xed3_capture_chain_UIMM8, +/* +VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=2877*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=2878*/ xed3_capture_chain_UIMM8, +/* +VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2879*/ xed3_capture_chain_MODRM, +/* +VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2880*/ xed3_capture_nt_nop, +/* +VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2881*/ xed3_capture_chain_MODRM, +/* +VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2882*/ xed3_capture_nt_nop, +/* +VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2883*/ xed3_capture_chain_MODRM, +/* +VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2884*/ xed3_capture_nt_nop, +/* +VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2885*/ xed3_capture_chain_MODRM, +/* +VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2886*/ xed3_capture_nt_nop, +/* +VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2887*/ xed3_capture_chain_MODRM, +/* +VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2888*/ xed3_capture_nt_nop, +/* +VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2889*/ xed3_capture_chain_MODRM, +/* +VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2890*/ xed3_capture_nt_nop, +/* +VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2891*/ xed3_capture_chain_MODRM, +/* +VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2892*/ xed3_capture_nt_nop, +/* +VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2893*/ xed3_capture_chain_MODRM, +/* +VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2894*/ xed3_capture_nt_nop, +/* +VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2895*/ xed3_capture_chain_MODRM, +/* +VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2896*/ xed3_capture_nt_nop, +/* +VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=2897*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2898*/ xed3_capture_chain_MODRM, +/* +VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2899*/ xed3_capture_nt_nop, +/* +VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=2900*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2901*/ xed3_capture_chain_MODRM, +/* +VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2902*/ xed3_capture_nt_nop, +/* +VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=2903*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2904*/ xed3_capture_chain_MODRM, +/* +VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2905*/ xed3_capture_nt_nop, +/* +VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=2906*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2907*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2908*/ xed3_capture_nt_nop, +/* +VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=2909*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2910*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2911*/ xed3_capture_nt_nop, +/* +VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8() +inum=2912*/ xed3_capture_chain_UIMM8, +/* +VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2913*/ xed3_capture_chain_MODRM, +/* +VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2914*/ xed3_capture_nt_nop, +/* +VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=2915*/ xed3_capture_chain_UIMM8, +/* +VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2916*/ xed3_capture_chain_MODRM, +/* +VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2917*/ xed3_capture_nt_nop, +/* +VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=2918*/ xed3_capture_chain_UIMM8, +/* +VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2919*/ xed3_capture_chain_MODRM, +/* +VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2920*/ xed3_capture_nt_nop, +/* +VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=2921*/ xed3_capture_chain_UIMM8, +/* +VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2922*/ xed3_capture_chain_MODRM, +/* +VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2923*/ xed3_capture_nt_nop, +/* +VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=2924*/ xed3_capture_chain_UIMM8, +/* +VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2925*/ xed3_capture_chain_MODRM, +/* +VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2926*/ xed3_capture_nt_nop, +/* +VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=2927*/ xed3_capture_chain_UIMM8, +/* +VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2928*/ xed3_capture_chain_MODRM, +/* +VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2929*/ xed3_capture_nt_nop, +/* +VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8() +inum=2930*/ xed3_capture_chain_UIMM8, +/* +VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2931*/ xed3_capture_chain_MODRM, +/* +VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2932*/ xed3_capture_nt_nop, +/* +VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=2933*/ xed3_capture_chain_UIMM8, +/* +VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2934*/ xed3_capture_chain_MODRM, +/* +VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2935*/ xed3_capture_nt_nop, +/* +VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=2936*/ xed3_capture_chain_UIMM8, +/* +VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2937*/ xed3_capture_chain_MODRM, +/* +VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2938*/ xed3_capture_nt_nop, +/* +VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=2939*/ xed3_capture_chain_UIMM8, +/* +VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2940*/ xed3_capture_chain_MODRM, +/* +VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2941*/ xed3_capture_nt_nop, +/* +VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8() +inum=2942*/ xed3_capture_chain_UIMM8, +/* +VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2943*/ xed3_capture_chain_MODRM, +/* +VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2944*/ xed3_capture_nt_nop, +/* +VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2945*/ xed3_capture_chain_MODRM, +/* +VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2946*/ xed3_capture_nt_nop, +/* +VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2947*/ xed3_capture_chain_MODRM, +/* +VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2948*/ xed3_capture_nt_nop, +/* +VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2949*/ xed3_capture_chain_MODRM, +/* +VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2950*/ xed3_capture_nt_nop, +/* +VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2951*/ xed3_capture_chain_MODRM, +/* +VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2952*/ xed3_capture_nt_nop, +/* +VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2953*/ xed3_capture_chain_MODRM, +/* +VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2954*/ xed3_capture_nt_nop, +/* +VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2955*/ xed3_capture_chain_MODRM, +/* +VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2956*/ xed3_capture_nt_nop, +/* +VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2957*/ xed3_capture_chain_MODRM, +/* +VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2958*/ xed3_capture_nt_nop, +/* +VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2959*/ xed3_capture_chain_MODRM, +/* +VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2960*/ xed3_capture_nt_nop, +/* +VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2961*/ xed3_capture_chain_MODRM, +/* +VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2962*/ xed3_capture_nt_nop, +/* +VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2963*/ xed3_capture_chain_MODRM, +/* +VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2964*/ xed3_capture_nt_nop, +/* +VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2965*/ xed3_capture_chain_MODRM, +/* +VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2966*/ xed3_capture_nt_nop, +/* +VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2967*/ xed3_capture_chain_MODRM, +/* +VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2968*/ xed3_capture_nt_nop, +/* +VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2969*/ xed3_capture_chain_MODRM, +/* +VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2970*/ xed3_capture_nt_nop, +/* +VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2971*/ xed3_capture_chain_MODRM, +/* +VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2972*/ xed3_capture_nt_nop, +/* +VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2973*/ xed3_capture_chain_MODRM, +/* +VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2974*/ xed3_capture_nt_nop, +/* +VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2975*/ xed3_capture_chain_MODRM, +/* +VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2976*/ xed3_capture_nt_nop, +/* +VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2977*/ xed3_capture_chain_MODRM, +/* +VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2978*/ xed3_capture_nt_nop, +/* +VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2979*/ xed3_capture_chain_MODRM, +/* +VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2980*/ xed3_capture_nt_nop, +/* +VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2981*/ xed3_capture_chain_MODRM, +/* +VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2982*/ xed3_capture_nt_nop, +/* +VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2983*/ xed3_capture_chain_MODRM, +/* +VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2984*/ xed3_capture_nt_nop, +/* +VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2985*/ xed3_capture_chain_MODRM, +/* +VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2986*/ xed3_capture_nt_nop, +/* +VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2987*/ xed3_capture_chain_MODRM, +/* +VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2988*/ xed3_capture_nt_nop, +/* +VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2989*/ xed3_capture_chain_MODRM, +/* +VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2990*/ xed3_capture_nt_nop, +/* +VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2991*/ xed3_capture_chain_MODRM, +/* +VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2992*/ xed3_capture_nt_nop, +/* +VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2993*/ xed3_capture_chain_MODRM, +/* +VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2994*/ xed3_capture_nt_nop, +/* +VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2995*/ xed3_capture_chain_MODRM, +/* +VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2996*/ xed3_capture_nt_nop, +/* +VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2997*/ xed3_capture_chain_MODRM, +/* +VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=2998*/ xed3_capture_nt_nop, +/* +VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=2999*/ xed3_capture_chain_MODRM, +/* +VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3000*/ xed3_capture_nt_nop, +/* +VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3001*/ xed3_capture_chain_MODRM, +/* +VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3002*/ xed3_capture_nt_nop, +/* +VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3003*/ xed3_capture_chain_MODRM, +/* +VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3004*/ xed3_capture_nt_nop, +/* +VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3005*/ xed3_capture_chain_MODRM, +/* +VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3006*/ xed3_capture_nt_nop, +/* +VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3007*/ xed3_capture_chain_MODRM, +/* +VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3008*/ xed3_capture_nt_nop, +/* +VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3009*/ xed3_capture_chain_MODRM, +/* +VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3010*/ xed3_capture_nt_nop, +/* +VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3011*/ xed3_capture_chain_MODRM, +/* +VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3012*/ xed3_capture_nt_nop, +/* +VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3013*/ xed3_capture_chain_MODRM, +/* +VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3014*/ xed3_capture_nt_nop, +/* +VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3015*/ xed3_capture_chain_MODRM, +/* +VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3016*/ xed3_capture_nt_nop, +/* +VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3017*/ xed3_capture_chain_MODRM, +/* +VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3018*/ xed3_capture_nt_nop, +/* +VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3019*/ xed3_capture_chain_MODRM, +/* +VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3020*/ xed3_capture_nt_nop, +/* +VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3021*/ xed3_capture_chain_MODRM, +/* +VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3022*/ xed3_capture_nt_nop, +/* +VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3023*/ xed3_capture_chain_MODRM, +/* +VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3024*/ xed3_capture_nt_nop, +/* +VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3025*/ xed3_capture_chain_MODRM, +/* +VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3026*/ xed3_capture_nt_nop, +/* +VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3027*/ xed3_capture_chain_MODRM, +/* +VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3028*/ xed3_capture_nt_nop, +/* +VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3029*/ xed3_capture_chain_MODRM, +/* +VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3030*/ xed3_capture_nt_nop, +/* +VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3031*/ xed3_capture_chain_MODRM, +/* +VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3032*/ xed3_capture_nt_nop, +/* +VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3033*/ xed3_capture_chain_MODRM, +/* +VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3034*/ xed3_capture_nt_nop, +/* +VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3035*/ xed3_capture_chain_MODRM, +/* +VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3036*/ xed3_capture_nt_nop, +/* +VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3037*/ xed3_capture_chain_MODRM, +/* +VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3038*/ xed3_capture_nt_nop, +/* +VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3039*/ xed3_capture_chain_MODRM, +/* +VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3040*/ xed3_capture_nt_nop, +/* +VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3041*/ xed3_capture_chain_MODRM, +/* +VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3042*/ xed3_capture_nt_nop, +/* +VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3043*/ xed3_capture_chain_MODRM, +/* +VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3044*/ xed3_capture_nt_nop, +/* +VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3045*/ xed3_capture_chain_MODRM, +/* +VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3046*/ xed3_capture_nt_nop, +/* +VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3047*/ xed3_capture_chain_MODRM, +/* +VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3048*/ xed3_capture_nt_nop, +/* +VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3049*/ xed3_capture_chain_MODRM, +/* +VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3050*/ xed3_capture_nt_nop, +/* +VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3051*/ xed3_capture_chain_MODRM, +/* +VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3052*/ xed3_capture_nt_nop, +/* +VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3053*/ xed3_capture_chain_MODRM, +/* +VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3054*/ xed3_capture_nt_nop, +/* +VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3055*/ xed3_capture_chain_MODRM, +/* +VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3056*/ xed3_capture_nt_nop, +/* +VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3057*/ xed3_capture_chain_MODRM, +/* +VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3058*/ xed3_capture_nt_nop, +/* +VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3059*/ xed3_capture_chain_MODRM, +/* +VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3060*/ xed3_capture_nt_nop, +/* +VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3061*/ xed3_capture_chain_MODRM, +/* +VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3062*/ xed3_capture_nt_nop, +/* +VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3063*/ xed3_capture_chain_MODRM, +/* +VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3064*/ xed3_capture_nt_nop, +/* +VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3065*/ xed3_capture_chain_MODRM, +/* +VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3066*/ xed3_capture_nt_nop, +/* +VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3067*/ xed3_capture_chain_MODRM, +/* +VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3068*/ xed3_capture_nt_nop, +/* +VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3069*/ xed3_capture_chain_MODRM, +/* +VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3070*/ xed3_capture_nt_nop, +/* +VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3071*/ xed3_capture_chain_MODRM, +/* +VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3072*/ xed3_capture_nt_nop, +/* +VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3073*/ xed3_capture_chain_MODRM, +/* +VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3074*/ xed3_capture_nt_nop, +/* +VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3075*/ xed3_capture_chain_MODRM, +/* +VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3076*/ xed3_capture_nt_nop, +/* +VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3077*/ xed3_capture_chain_MODRM, +/* +VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3078*/ xed3_capture_nt_nop, +/* +VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3079*/ xed3_capture_chain_MODRM, +/* +VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3080*/ xed3_capture_nt_nop, +/* +VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3081*/ xed3_capture_chain_MODRM, +/* +VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3082*/ xed3_capture_nt_nop, +/* +VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3083*/ xed3_capture_chain_MODRM, +/* +VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3084*/ xed3_capture_nt_nop, +/* +VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3085*/ xed3_capture_chain_MODRM, +/* +VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3086*/ xed3_capture_nt_nop, +/* +VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3087*/ xed3_capture_chain_MODRM, +/* +VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3088*/ xed3_capture_nt_nop, +/* +VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3089*/ xed3_capture_chain_MODRM, +/* +VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3090*/ xed3_capture_nt_nop, +/* +VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3091*/ xed3_capture_chain_MODRM, +/* +VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3092*/ xed3_capture_nt_nop, +/* +VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3093*/ xed3_capture_chain_MODRM, +/* +VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3094*/ xed3_capture_nt_nop, +/* +VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3095*/ xed3_capture_chain_MODRM, +/* +VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3096*/ xed3_capture_nt_nop, +/* +VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3097*/ xed3_capture_chain_MODRM, +/* +VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3098*/ xed3_capture_nt_nop, +/* +VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3099*/ xed3_capture_chain_MODRM, +/* +VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3100*/ xed3_capture_nt_nop, +/* +VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3101*/ xed3_capture_chain_MODRM, +/* +VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3102*/ xed3_capture_nt_nop, +/* +VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3103*/ xed3_capture_chain_MODRM, +/* +VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3104*/ xed3_capture_nt_nop, +/* +VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3105*/ xed3_capture_chain_MODRM, +/* +VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3106*/ xed3_capture_nt_nop, +/* +VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3107*/ xed3_capture_chain_MODRM, +/* +VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3108*/ xed3_capture_nt_nop, +/* +VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3109*/ xed3_capture_chain_MODRM, +/* +VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3110*/ xed3_capture_nt_nop, +/* +VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3111*/ xed3_capture_chain_MODRM, +/* +VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3112*/ xed3_capture_nt_nop, +/* +VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3113*/ xed3_capture_chain_MODRM, +/* +VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3114*/ xed3_capture_nt_nop, +/* +VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3115*/ xed3_capture_chain_MODRM, +/* +VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3116*/ xed3_capture_nt_nop, +/* +VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3117*/ xed3_capture_chain_MODRM, +/* +VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3118*/ xed3_capture_nt_nop, +/* +VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3119*/ xed3_capture_chain_MODRM, +/* +VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3120*/ xed3_capture_nt_nop, +/* +VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3121*/ xed3_capture_chain_MODRM, +/* +VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3122*/ xed3_capture_nt_nop, +/* +VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3123*/ xed3_capture_chain_MODRM, +/* +VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3124*/ xed3_capture_nt_nop, +/* +VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3125*/ xed3_capture_chain_MODRM, +/* +VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3126*/ xed3_capture_nt_nop, +/* +VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3127*/ xed3_capture_chain_MODRM, +/* +VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3128*/ xed3_capture_nt_nop, +/* +VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3129*/ xed3_capture_chain_MODRM, +/* +VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3130*/ xed3_capture_nt_nop, +/* +VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3131*/ xed3_capture_chain_MODRM, +/* +VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3132*/ xed3_capture_nt_nop, +/* +VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3133*/ xed3_capture_chain_MODRM, +/* +VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3134*/ xed3_capture_nt_nop, +/* +VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3135*/ xed3_capture_chain_MODRM, +/* +VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3136*/ xed3_capture_nt_nop, +/* +VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3137*/ xed3_capture_chain_MODRM, +/* +VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3138*/ xed3_capture_nt_nop, +/* +VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3139*/ xed3_capture_chain_MODRM, +/* +VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3140*/ xed3_capture_nt_nop, +/* +VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3141*/ xed3_capture_chain_MODRM, +/* +VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3142*/ xed3_capture_nt_nop, +/* +VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3143*/ xed3_capture_chain_MODRM, +/* +VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3144*/ xed3_capture_nt_nop, +/* +VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3145*/ xed3_capture_chain_MODRM, +/* +VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3146*/ xed3_capture_nt_nop, +/* +VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3147*/ xed3_capture_chain_MODRM, +/* +VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3148*/ xed3_capture_nt_nop, +/* +VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3149*/ xed3_capture_chain_MODRM, +/* +VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3150*/ xed3_capture_nt_nop, +/* +VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +inum=3151*/ xed3_capture_chain_UIMM8, +/* +VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8() +inum=3152*/ xed3_capture_chain_UIMM8, +/* +VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +inum=3153*/ xed3_capture_chain_UIMM8, +/* +VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8() +inum=3154*/ xed3_capture_chain_UIMM8, +/* +VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3155*/ xed3_capture_nt_nop, +/* +VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3156*/ xed3_capture_nt_nop, +/* +VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3157*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3158*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3159*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3160*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3161*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3162*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3163*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3164*/ xed3_capture_chain_UIMM8, +/* +VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3165*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3166*/ xed3_capture_chain_UIMM8, +/* +VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3167*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3168*/ xed3_capture_chain_UIMM8, +/* +VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3169*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3170*/ xed3_capture_chain_UIMM8, +/* +VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3171*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3172*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3173*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3174*/ xed3_capture_chain_UIMM8, +/* +VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3175*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3176*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3177*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3178*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3179*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3180*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3181*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3182*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3183*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3184*/ xed3_capture_chain_UIMM8, +/* +VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3185*/ xed3_capture_chain_MODRM, +/* +VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3186*/ xed3_capture_nt_nop, +/* +VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3187*/ xed3_capture_chain_MODRM, +/* +VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3188*/ xed3_capture_nt_nop, +/* +VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3189*/ xed3_capture_chain_MODRM, +/* +VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3190*/ xed3_capture_nt_nop, +/* +VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3191*/ xed3_capture_chain_MODRM, +/* +VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3192*/ xed3_capture_nt_nop, +/* +VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3193*/ xed3_capture_chain_MODRM, +/* +VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3194*/ xed3_capture_nt_nop, +/* +VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3195*/ xed3_capture_chain_MODRM, +/* +VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3196*/ xed3_capture_nt_nop, +/* +VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3197*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3198*/ xed3_capture_nt_nop, +/* +VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3199*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3200*/ xed3_capture_nt_nop, +/* +VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3201*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3202*/ xed3_capture_nt_nop, +/* +VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3203*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3204*/ xed3_capture_nt_nop, +/* +VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3205*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3206*/ xed3_capture_nt_nop, +/* +VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3207*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3208*/ xed3_capture_nt_nop, +/* +VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3209*/ xed3_capture_chain_MODRM, +/* +VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3210*/ xed3_capture_nt_nop, +/* +VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3211*/ xed3_capture_chain_MODRM, +/* +VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3212*/ xed3_capture_nt_nop, +/* +VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3213*/ xed3_capture_chain_MODRM, +/* +VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3214*/ xed3_capture_nt_nop, +/* +VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3215*/ xed3_capture_chain_MODRM, +/* +VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3216*/ xed3_capture_nt_nop, +/* +VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3217*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3218*/ xed3_capture_nt_nop, +/* +VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3219*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3220*/ xed3_capture_nt_nop, +/* +VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3221*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3222*/ xed3_capture_nt_nop, +/* +VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3223*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3224*/ xed3_capture_nt_nop, +/* +VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3225*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3226*/ xed3_capture_nt_nop, +/* +VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3227*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3228*/ xed3_capture_nt_nop, +/* +VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3229*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3230*/ xed3_capture_nt_nop, +/* +VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3231*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3232*/ xed3_capture_nt_nop, +/* +VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3233*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3234*/ xed3_capture_nt_nop, +/* +VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3235*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3236*/ xed3_capture_nt_nop, +/* +VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3237*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3238*/ xed3_capture_nt_nop, +/* +VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3239*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3240*/ xed3_capture_nt_nop, +/* +VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3241*/ xed3_capture_chain_MODRM, +/* +VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3242*/ xed3_capture_nt_nop, +/* +VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3243*/ xed3_capture_chain_MODRM, +/* +VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3244*/ xed3_capture_nt_nop, +/* +VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3245*/ xed3_capture_chain_MODRM, +/* +VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3246*/ xed3_capture_nt_nop, +/* +VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3247*/ xed3_capture_chain_MODRM, +/* +VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3248*/ xed3_capture_nt_nop, +/* +VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3249*/ xed3_capture_chain_MODRM, +/* +VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3250*/ xed3_capture_nt_nop, +/* +VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3251*/ xed3_capture_chain_MODRM, +/* +VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3252*/ xed3_capture_nt_nop, +/* +VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3253*/ xed3_capture_chain_MODRM, +/* +VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3254*/ xed3_capture_nt_nop, +/* +VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3255*/ xed3_capture_chain_MODRM, +/* +VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3256*/ xed3_capture_nt_nop, +/* +VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3257*/ xed3_capture_chain_MODRM, +/* +VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3258*/ xed3_capture_nt_nop, +/* +VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3259*/ xed3_capture_chain_MODRM, +/* +VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3260*/ xed3_capture_nt_nop, +/* +VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3261*/ xed3_capture_chain_MODRM, +/* +VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3262*/ xed3_capture_nt_nop, +/* +VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3263*/ xed3_capture_chain_MODRM, +/* +VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3264*/ xed3_capture_nt_nop, +/* +VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3265*/ xed3_capture_chain_MODRM, +/* +VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3266*/ xed3_capture_nt_nop, +/* +VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3267*/ xed3_capture_chain_MODRM, +/* +VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3268*/ xed3_capture_nt_nop, +/* +VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3269*/ xed3_capture_chain_MODRM, +/* +VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3270*/ xed3_capture_nt_nop, +/* +VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3271*/ xed3_capture_chain_MODRM, +/* +VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3272*/ xed3_capture_nt_nop, +/* +VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3273*/ xed3_capture_chain_MODRM, +/* +VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3274*/ xed3_capture_nt_nop, +/* +VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3275*/ xed3_capture_chain_MODRM, +/* +VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3276*/ xed3_capture_nt_nop, +/* +VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3277*/ xed3_capture_chain_MODRM, +/* +VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3278*/ xed3_capture_nt_nop, +/* +VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3279*/ xed3_capture_chain_MODRM, +/* +VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3280*/ xed3_capture_nt_nop, +/* +VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3281*/ xed3_capture_chain_MODRM, +/* +VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3282*/ xed3_capture_nt_nop, +/* +VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3283*/ xed3_capture_chain_MODRM, +/* +VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3284*/ xed3_capture_nt_nop, +/* +VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3285*/ xed3_capture_chain_MODRM, +/* +VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3286*/ xed3_capture_nt_nop, +/* +VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3287*/ xed3_capture_chain_MODRM, +/* +VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3288*/ xed3_capture_nt_nop, +/* +VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3289*/ xed3_capture_chain_MODRM, +/* +VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3290*/ xed3_capture_nt_nop, +/* +VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3291*/ xed3_capture_chain_MODRM, +/* +VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3292*/ xed3_capture_nt_nop, +/* +VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3293*/ xed3_capture_chain_MODRM, +/* +VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3294*/ xed3_capture_nt_nop, +/* +VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3295*/ xed3_capture_chain_MODRM, +/* +VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3296*/ xed3_capture_nt_nop, +/* +VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3297*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3298*/ xed3_capture_nt_nop, +/* +VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3299*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3300*/ xed3_capture_nt_nop, +/* +VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3301*/ xed3_capture_chain_MODRM, +/* +VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3302*/ xed3_capture_nt_nop, +/* +VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3303*/ xed3_capture_chain_MODRM, +/* +VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3304*/ xed3_capture_nt_nop, +/* +VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3305*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3306*/ xed3_capture_chain_UIMM8, +/* +VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3307*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3308*/ xed3_capture_chain_UIMM8, +/* +VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3309*/ xed3_capture_chain_MODRM, +/* +VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3310*/ xed3_capture_nt_nop, +/* +VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3311*/ xed3_capture_chain_MODRM, +/* +VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3312*/ xed3_capture_nt_nop, +/* +VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3313*/ xed3_capture_chain_MODRM, +/* +VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3314*/ xed3_capture_nt_nop, +/* +VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3315*/ xed3_capture_chain_MODRM, +/* +VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3316*/ xed3_capture_nt_nop, +/* +VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3317*/ xed3_capture_chain_MODRM, +/* +VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3318*/ xed3_capture_nt_nop, +/* +VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3319*/ xed3_capture_chain_MODRM, +/* +VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3320*/ xed3_capture_nt_nop, +/* +VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3321*/ xed3_capture_chain_MODRM, +/* +VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3322*/ xed3_capture_nt_nop, +/* +VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3323*/ xed3_capture_chain_MODRM, +/* +VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3324*/ xed3_capture_nt_nop, +/* +VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3325*/ xed3_capture_chain_MODRM, +/* +VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3326*/ xed3_capture_nt_nop, +/* +VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3327*/ xed3_capture_chain_MODRM, +/* +VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3328*/ xed3_capture_nt_nop, +/* +VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +inum=3329*/ xed3_capture_chain_MODRM, +/* +VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3330*/ xed3_capture_nt_nop, +/* +VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +inum=3331*/ xed3_capture_chain_MODRM, +/* +VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3332*/ xed3_capture_nt_nop, +/* +VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +inum=3333*/ xed3_capture_chain_MODRM, +/* +VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3334*/ xed3_capture_nt_nop, +/* +VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM() +inum=3335*/ xed3_capture_chain_MODRM, +/* +VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3336*/ xed3_capture_nt_nop, +/* +VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3337*/ xed3_capture_chain_MODRM, +/* +VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3338*/ xed3_capture_nt_nop, +/* +VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3339*/ xed3_capture_chain_MODRM, +/* +VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3340*/ xed3_capture_nt_nop, +/* +VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3341*/ xed3_capture_chain_MODRM, +/* +VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3342*/ xed3_capture_nt_nop, +/* +VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3343*/ xed3_capture_chain_MODRM, +/* +VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3344*/ xed3_capture_nt_nop, +/* +VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3345*/ xed3_capture_chain_MODRM, +/* +VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3346*/ xed3_capture_nt_nop, +/* +VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3347*/ xed3_capture_chain_MODRM, +/* +VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3348*/ xed3_capture_nt_nop, +/* +VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3349*/ xed3_capture_chain_MODRM, +/* +VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3350*/ xed3_capture_nt_nop, +/* +VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3351*/ xed3_capture_chain_MODRM, +/* +VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3352*/ xed3_capture_nt_nop, +/* +VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3353*/ xed3_capture_chain_MODRM, +/* +VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3354*/ xed3_capture_chain_MODRM, +/* +VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3355*/ xed3_capture_chain_MODRM, +/* +VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3356*/ xed3_capture_chain_MODRM, +/* +VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3357*/ xed3_capture_chain_MODRM, +/* +VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3358*/ xed3_capture_chain_MODRM, +/* +VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3359*/ xed3_capture_chain_MODRM, +/* +VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3360*/ xed3_capture_chain_MODRM, +/* +VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3361*/ xed3_capture_nt_nop, +/* +VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3362*/ xed3_capture_nt_nop, +/* +VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3363*/ xed3_capture_nt_nop, +/* +VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3364*/ xed3_capture_nt_nop, +/* +VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3365*/ xed3_capture_nt_nop, +/* +VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3366*/ xed3_capture_nt_nop, +/* +VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3367*/ xed3_capture_nt_nop, +/* +VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3368*/ xed3_capture_chain_MODRM, +/* +VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3369*/ xed3_capture_nt_nop, +/* +VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3370*/ xed3_capture_chain_MODRM, +/* +VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3371*/ xed3_capture_nt_nop, +/* +VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3372*/ xed3_capture_chain_MODRM, +/* +VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3373*/ xed3_capture_nt_nop, +/* +VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3374*/ xed3_capture_chain_MODRM, +/* +VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3375*/ xed3_capture_nt_nop, +/* +VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3376*/ xed3_capture_chain_MODRM, +/* +VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3377*/ xed3_capture_nt_nop, +/* +VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3378*/ xed3_capture_chain_MODRM, +/* +VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3379*/ xed3_capture_nt_nop, +/* +VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3380*/ xed3_capture_chain_MODRM, +/* +VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3381*/ xed3_capture_nt_nop, +/* +VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3382*/ xed3_capture_chain_MODRM, +/* +VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3383*/ xed3_capture_nt_nop, +/* +VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3384*/ xed3_capture_chain_MODRM, +/* +VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3385*/ xed3_capture_nt_nop, +/* +VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3386*/ xed3_capture_chain_MODRM, +/* +VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3387*/ xed3_capture_nt_nop, +/* +VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3388*/ xed3_capture_chain_MODRM, +/* +VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3389*/ xed3_capture_nt_nop, +/* +VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3390*/ xed3_capture_chain_MODRM, +/* +VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3391*/ xed3_capture_nt_nop, +/* +VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3392*/ xed3_capture_chain_MODRM, +/* +VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3393*/ xed3_capture_nt_nop, +/* +VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3394*/ xed3_capture_chain_MODRM, +/* +VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3395*/ xed3_capture_nt_nop, +/* +VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3396*/ xed3_capture_chain_MODRM, +/* +VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3397*/ xed3_capture_nt_nop, +/* +VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3398*/ xed3_capture_chain_MODRM, +/* +VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3399*/ xed3_capture_nt_nop, +/* +VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3400*/ xed3_capture_chain_MODRM, +/* +VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3401*/ xed3_capture_nt_nop, +/* +VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3402*/ xed3_capture_chain_MODRM, +/* +VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3403*/ xed3_capture_nt_nop, +/* +VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3404*/ xed3_capture_chain_MODRM, +/* +VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3405*/ xed3_capture_nt_nop, +/* +VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3406*/ xed3_capture_chain_MODRM, +/* +VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3407*/ xed3_capture_nt_nop, +/* +VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3408*/ xed3_capture_chain_MODRM, +/* +VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3409*/ xed3_capture_nt_nop, +/* +VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3410*/ xed3_capture_chain_MODRM, +/* +VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3411*/ xed3_capture_nt_nop, +/* +VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3412*/ xed3_capture_chain_MODRM, +/* +VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3413*/ xed3_capture_nt_nop, +/* +VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3414*/ xed3_capture_chain_MODRM, +/* +VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3415*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3416*/ xed3_capture_chain_UIMM8, +/* +VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3417*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3418*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3419*/ xed3_capture_chain_UIMM8, +/* +VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3420*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3421*/ xed3_capture_chain_UIMM8, +/* +VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3422*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3423*/ xed3_capture_chain_UIMM8, +/* +VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3424*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3425*/ xed3_capture_chain_UIMM8, +/* +VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3426*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3427*/ xed3_capture_chain_UIMM8, +/* +VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3428*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3429*/ xed3_capture_chain_UIMM8, +/* +VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3430*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3431*/ xed3_capture_chain_UIMM8, +/* +VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3432*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3433*/ xed3_capture_chain_UIMM8, +/* +VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3434*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3435*/ xed3_capture_chain_UIMM8, +/* +VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3436*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3437*/ xed3_capture_chain_UIMM8, +/* +VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3438*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3439*/ xed3_capture_chain_UIMM8, +/* +VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3440*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3441*/ xed3_capture_chain_UIMM8, +/* +VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3442*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3443*/ xed3_capture_chain_UIMM8, +/* +VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3444*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3445*/ xed3_capture_chain_UIMM8, +/* +VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3446*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3447*/ xed3_capture_chain_UIMM8, +/* +VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3448*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3449*/ xed3_capture_chain_UIMM8, +/* +VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3450*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3451*/ xed3_capture_chain_UIMM8, +/* +VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3452*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3453*/ xed3_capture_chain_UIMM8, +/* +VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3454*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3455*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3456*/ xed3_capture_nt_nop, +/* +VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=3457*/ xed3_capture_chain_MODRM, +/* +VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=3458*/ xed3_capture_chain_MODRM, +/* +VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=3459*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=3460*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=3461*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=3462*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=3463*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=3464*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=3465*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=3466*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=3467*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=3468*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8() +inum=3469*/ xed3_capture_chain_MODRM_SE_IMM8, +/* +VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8() +inum=3470*/ xed3_capture_chain_SE_IMM8, +/* +VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3471*/ xed3_capture_chain_MODRM, +/* +VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3472*/ xed3_capture_chain_MODRM, +/* +VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3473*/ xed3_capture_chain_MODRM, +/* +VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3474*/ xed3_capture_chain_MODRM, +/* +VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3475*/ xed3_capture_chain_MODRM, +/* +VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3476*/ xed3_capture_chain_MODRM, +/* +VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3477*/ xed3_capture_chain_MODRM, +/* +VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3478*/ xed3_capture_chain_MODRM, +/* +VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3479*/ xed3_capture_chain_UIMM8, +/* +VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3480*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +inum=3481*/ xed3_capture_nt_nop, +/* +VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +inum=3482*/ xed3_capture_chain_MODRM, +/* +VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +inum=3483*/ xed3_capture_nt_nop, +/* +VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +inum=3484*/ xed3_capture_chain_MODRM, +/* +VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +inum=3485*/ xed3_capture_nt_nop, +/* +VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +inum=3486*/ xed3_capture_chain_MODRM, +/* +VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +inum=3487*/ xed3_capture_nt_nop, +/* +VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +inum=3488*/ xed3_capture_chain_MODRM, +/* +VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +inum=3489*/ xed3_capture_nt_nop, +/* +VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +inum=3490*/ xed3_capture_chain_MODRM, +/* +VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +inum=3491*/ xed3_capture_nt_nop, +/* +VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +inum=3492*/ xed3_capture_chain_MODRM, +/* +VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 +inum=3493*/ xed3_capture_nt_nop, +/* +VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 +inum=3494*/ xed3_capture_chain_MODRM, +/* +VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 +inum=3495*/ xed3_capture_nt_nop, +/* +VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 +inum=3496*/ xed3_capture_chain_MODRM, +/* +VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3497*/ xed3_capture_nt_nop, +/* +VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3498*/ xed3_capture_chain_MODRM, +/* +VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8() +inum=3499*/ xed3_capture_chain_UIMM8, +/* +VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8() +inum=3500*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8() +inum=3501*/ xed3_capture_chain_UIMM8, +/* +VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8() +inum=3502*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +inum=3503*/ xed3_capture_chain_MODRM, +/* +VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +inum=3504*/ xed3_capture_nt_nop, +/* +VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0 +inum=3505*/ xed3_capture_chain_MODRM, +/* +VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 +inum=3506*/ xed3_capture_nt_nop, +/* +VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +inum=3507*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +inum=3508*/ xed3_capture_chain_UIMM8, +/* +VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0 +inum=3509*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0 +inum=3510*/ xed3_capture_chain_UIMM8, +/* +VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3511*/ xed3_capture_chain_MODRM, +/* +VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3512*/ xed3_capture_nt_nop, +/* +VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3513*/ xed3_capture_chain_MODRM, +/* +VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3514*/ xed3_capture_nt_nop, +/* +VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3515*/ xed3_capture_chain_MODRM, +/* +VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3516*/ xed3_capture_nt_nop, +/* +VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3517*/ xed3_capture_chain_MODRM, +/* +VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3518*/ xed3_capture_nt_nop, +/* +VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3519*/ xed3_capture_chain_MODRM, +/* +VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3520*/ xed3_capture_nt_nop, +/* +VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3521*/ xed3_capture_chain_MODRM, +/* +VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3522*/ xed3_capture_nt_nop, +/* +VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3523*/ xed3_capture_chain_MODRM, +/* +VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3524*/ xed3_capture_nt_nop, +/* +VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3525*/ xed3_capture_chain_MODRM, +/* +VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3526*/ xed3_capture_nt_nop, +/* +VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3527*/ xed3_capture_chain_MODRM, +/* +VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3528*/ xed3_capture_nt_nop, +/* +VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3529*/ xed3_capture_chain_MODRM, +/* +VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3530*/ xed3_capture_nt_nop, +/* +VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3531*/ xed3_capture_chain_MODRM, +/* +VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3532*/ xed3_capture_nt_nop, +/* +VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3533*/ xed3_capture_chain_MODRM, +/* +VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3534*/ xed3_capture_nt_nop, +/* +VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3535*/ xed3_capture_chain_MODRM, +/* +VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3536*/ xed3_capture_nt_nop, +/* +VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3537*/ xed3_capture_chain_MODRM, +/* +VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3538*/ xed3_capture_nt_nop, +/* +VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3539*/ xed3_capture_chain_MODRM, +/* +VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3540*/ xed3_capture_nt_nop, +/* +VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3541*/ xed3_capture_chain_MODRM, +/* +VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3542*/ xed3_capture_nt_nop, +/* +VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3543*/ xed3_capture_chain_MODRM, +/* +VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3544*/ xed3_capture_nt_nop, +/* +VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3545*/ xed3_capture_chain_MODRM, +/* +VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3546*/ xed3_capture_nt_nop, +/* +VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3547*/ xed3_capture_chain_MODRM, +/* +VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3548*/ xed3_capture_nt_nop, +/* +VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3549*/ xed3_capture_chain_MODRM, +/* +VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3550*/ xed3_capture_nt_nop, +/* +VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3551*/ xed3_capture_chain_MODRM, +/* +VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3552*/ xed3_capture_nt_nop, +/* +VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3553*/ xed3_capture_chain_MODRM, +/* +VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3554*/ xed3_capture_nt_nop, +/* +VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3555*/ xed3_capture_chain_MODRM, +/* +VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3556*/ xed3_capture_nt_nop, +/* +VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3557*/ xed3_capture_chain_MODRM, +/* +VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3558*/ xed3_capture_nt_nop, +/* +VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3559*/ xed3_capture_chain_MODRM, +/* +VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3560*/ xed3_capture_nt_nop, +/* +VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3561*/ xed3_capture_chain_MODRM, +/* +VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3562*/ xed3_capture_nt_nop, +/* +VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3563*/ xed3_capture_chain_MODRM, +/* +VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3564*/ xed3_capture_nt_nop, +/* +VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3565*/ xed3_capture_chain_MODRM, +/* +VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3566*/ xed3_capture_nt_nop, +/* +VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3567*/ xed3_capture_chain_MODRM, +/* +VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3568*/ xed3_capture_nt_nop, +/* +VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3569*/ xed3_capture_chain_MODRM, +/* +VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3570*/ xed3_capture_nt_nop, +/* +VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3571*/ xed3_capture_chain_MODRM, +/* +VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3572*/ xed3_capture_nt_nop, +/* +VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3573*/ xed3_capture_chain_MODRM, +/* +VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3574*/ xed3_capture_nt_nop, +/* +VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3575*/ xed3_capture_chain_MODRM, +/* +VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3576*/ xed3_capture_nt_nop, +/* +VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3577*/ xed3_capture_chain_MODRM, +/* +VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3578*/ xed3_capture_nt_nop, +/* +VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3579*/ xed3_capture_chain_MODRM, +/* +VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3580*/ xed3_capture_nt_nop, +/* +VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3581*/ xed3_capture_chain_MODRM, +/* +VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3582*/ xed3_capture_nt_nop, +/* +VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3583*/ xed3_capture_chain_MODRM, +/* +VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3584*/ xed3_capture_nt_nop, +/* +VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3585*/ xed3_capture_chain_MODRM, +/* +VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3586*/ xed3_capture_nt_nop, +/* +VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3587*/ xed3_capture_chain_MODRM, +/* +VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3588*/ xed3_capture_nt_nop, +/* +VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3589*/ xed3_capture_chain_MODRM, +/* +VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3590*/ xed3_capture_nt_nop, +/* +VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3591*/ xed3_capture_chain_MODRM, +/* +VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3592*/ xed3_capture_nt_nop, +/* +VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3593*/ xed3_capture_chain_MODRM, +/* +VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3594*/ xed3_capture_nt_nop, +/* +VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3595*/ xed3_capture_chain_MODRM, +/* +VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3596*/ xed3_capture_nt_nop, +/* +VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3597*/ xed3_capture_chain_MODRM, +/* +VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3598*/ xed3_capture_nt_nop, +/* +VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3599*/ xed3_capture_chain_MODRM, +/* +VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3600*/ xed3_capture_nt_nop, +/* +VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3601*/ xed3_capture_chain_MODRM, +/* +VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3602*/ xed3_capture_nt_nop, +/* +VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3603*/ xed3_capture_chain_MODRM, +/* +VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3604*/ xed3_capture_nt_nop, +/* +VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3605*/ xed3_capture_chain_MODRM, +/* +VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3606*/ xed3_capture_nt_nop, +/* +VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3607*/ xed3_capture_chain_MODRM, +/* +VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3608*/ xed3_capture_nt_nop, +/* +VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3609*/ xed3_capture_chain_MODRM, +/* +VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3610*/ xed3_capture_nt_nop, +/* +VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3611*/ xed3_capture_chain_MODRM, +/* +VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3612*/ xed3_capture_nt_nop, +/* +VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3613*/ xed3_capture_chain_MODRM, +/* +VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3614*/ xed3_capture_nt_nop, +/* +VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3615*/ xed3_capture_chain_MODRM, +/* +VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3616*/ xed3_capture_nt_nop, +/* +VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3617*/ xed3_capture_chain_MODRM, +/* +VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3618*/ xed3_capture_nt_nop, +/* +VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3619*/ xed3_capture_chain_MODRM, +/* +VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3620*/ xed3_capture_nt_nop, +/* +VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3621*/ xed3_capture_chain_MODRM, +/* +VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3622*/ xed3_capture_nt_nop, +/* +VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3623*/ xed3_capture_chain_MODRM, +/* +VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3624*/ xed3_capture_nt_nop, +/* +VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3625*/ xed3_capture_chain_MODRM, +/* +VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3626*/ xed3_capture_nt_nop, +/* +VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3627*/ xed3_capture_chain_MODRM, +/* +VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3628*/ xed3_capture_nt_nop, +/* +VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3629*/ xed3_capture_chain_MODRM, +/* +VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3630*/ xed3_capture_nt_nop, +/* +VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3631*/ xed3_capture_chain_MODRM, +/* +VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3632*/ xed3_capture_nt_nop, +/* +VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3633*/ xed3_capture_chain_MODRM, +/* +VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3634*/ xed3_capture_nt_nop, +/* +VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3635*/ xed3_capture_chain_MODRM, +/* +VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3636*/ xed3_capture_nt_nop, +/* +VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3637*/ xed3_capture_chain_MODRM, +/* +VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3638*/ xed3_capture_nt_nop, +/* +VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3639*/ xed3_capture_chain_MODRM, +/* +VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3640*/ xed3_capture_nt_nop, +/* +VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3641*/ xed3_capture_chain_MODRM, +/* +VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3642*/ xed3_capture_nt_nop, +/* +VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3643*/ xed3_capture_chain_MODRM, +/* +VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3644*/ xed3_capture_nt_nop, +/* +VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3645*/ xed3_capture_chain_MODRM, +/* +VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3646*/ xed3_capture_nt_nop, +/* +VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3647*/ xed3_capture_chain_MODRM, +/* +VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3648*/ xed3_capture_nt_nop, +/* +VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3649*/ xed3_capture_chain_MODRM, +/* +VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3650*/ xed3_capture_nt_nop, +/* +VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3651*/ xed3_capture_chain_MODRM, +/* +VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3652*/ xed3_capture_nt_nop, +/* +VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3653*/ xed3_capture_chain_MODRM, +/* +VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3654*/ xed3_capture_nt_nop, +/* +VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3655*/ xed3_capture_chain_MODRM, +/* +VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3656*/ xed3_capture_nt_nop, +/* +VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3657*/ xed3_capture_chain_MODRM, +/* +VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3658*/ xed3_capture_nt_nop, +/* +VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3659*/ xed3_capture_chain_MODRM, +/* +VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3660*/ xed3_capture_nt_nop, +/* +VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3661*/ xed3_capture_chain_MODRM, +/* +VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3662*/ xed3_capture_nt_nop, +/* +VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3663*/ xed3_capture_chain_MODRM, +/* +VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3664*/ xed3_capture_nt_nop, +/* +VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3665*/ xed3_capture_chain_MODRM, +/* +VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3666*/ xed3_capture_nt_nop, +/* +VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3667*/ xed3_capture_chain_MODRM, +/* +VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3668*/ xed3_capture_nt_nop, +/* +VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3669*/ xed3_capture_chain_MODRM, +/* +VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3670*/ xed3_capture_nt_nop, +/* +VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3671*/ xed3_capture_chain_MODRM, +/* +VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3672*/ xed3_capture_nt_nop, +/* +VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3673*/ xed3_capture_chain_MODRM, +/* +VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3674*/ xed3_capture_nt_nop, +/* +VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3675*/ xed3_capture_chain_MODRM, +/* +VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3676*/ xed3_capture_nt_nop, +/* +VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3677*/ xed3_capture_chain_MODRM, +/* +VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3678*/ xed3_capture_nt_nop, +/* +VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3679*/ xed3_capture_chain_MODRM, +/* +VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3680*/ xed3_capture_nt_nop, +/* +VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3681*/ xed3_capture_chain_MODRM, +/* +VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3682*/ xed3_capture_nt_nop, +/* +VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3683*/ xed3_capture_chain_MODRM, +/* +VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3684*/ xed3_capture_nt_nop, +/* +VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3685*/ xed3_capture_chain_MODRM, +/* +VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3686*/ xed3_capture_nt_nop, +/* +VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3687*/ xed3_capture_chain_MODRM, +/* +VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3688*/ xed3_capture_nt_nop, +/* +VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3689*/ xed3_capture_chain_MODRM, +/* +VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3690*/ xed3_capture_nt_nop, +/* +VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3691*/ xed3_capture_chain_MODRM, +/* +VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3692*/ xed3_capture_nt_nop, +/* +VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3693*/ xed3_capture_chain_MODRM, +/* +VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3694*/ xed3_capture_nt_nop, +/* +VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3695*/ xed3_capture_chain_MODRM, +/* +VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3696*/ xed3_capture_nt_nop, +/* +VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3697*/ xed3_capture_chain_MODRM, +/* +VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3698*/ xed3_capture_nt_nop, +/* +VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3699*/ xed3_capture_chain_MODRM, +/* +VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3700*/ xed3_capture_nt_nop, +/* +VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3701*/ xed3_capture_chain_MODRM, +/* +VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3702*/ xed3_capture_nt_nop, +/* +VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3703*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3704*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +inum=3705*/ xed3_capture_chain_VMODRM_YMM, +/* +VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3706*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +inum=3707*/ xed3_capture_chain_VMODRM_YMM, +/* +VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3708*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +inum=3709*/ xed3_capture_chain_VMODRM_YMM, +/* +VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3710*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3711*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3712*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +inum=3713*/ xed3_capture_chain_VMODRM_YMM, +/* +VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3714*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +inum=3715*/ xed3_capture_chain_VMODRM_YMM, +/* +VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3716*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16 +inum=3717*/ xed3_capture_chain_VMODRM_YMM, +/* +VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16 +inum=3718*/ xed3_capture_chain_VMODRM_XMM, +/* +VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3719*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3720*/ xed3_capture_chain_UIMM8, +/* +VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3721*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3722*/ xed3_capture_chain_UIMM8, +/* +VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3723*/ xed3_capture_chain_MODRM, +/* +VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3724*/ xed3_capture_chain_MODRM, +/* +VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3725*/ xed3_capture_chain_MODRM, +/* +VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3726*/ xed3_capture_chain_MODRM, +/* +VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3727*/ xed3_capture_chain_MODRM, +/* +VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3728*/ xed3_capture_chain_MODRM, +/* +VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3729*/ xed3_capture_chain_MODRM, +/* +VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3730*/ xed3_capture_chain_MODRM, +/* +VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3731*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3732*/ xed3_capture_chain_UIMM8, +/* +VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3733*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3734*/ xed3_capture_chain_UIMM8, +/* +VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3735*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3736*/ xed3_capture_chain_UIMM8, +/* +VV1 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3737*/ xed3_capture_chain_MODRM, +/* +VV1 0x36 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3738*/ xed3_capture_nt_nop, +/* +VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3739*/ xed3_capture_chain_MODRM, +/* +VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3740*/ xed3_capture_nt_nop, +/* +VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3741*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3742*/ xed3_capture_chain_UIMM8, +/* +VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3743*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3744*/ xed3_capture_chain_UIMM8, +/* +VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3745*/ xed3_capture_chain_MODRM, +/* +VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3746*/ xed3_capture_nt_nop, +/* +VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3747*/ xed3_capture_chain_MODRM, +/* +VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3748*/ xed3_capture_nt_nop, +/* +VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3749*/ xed3_capture_chain_MODRM, +/* +VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3750*/ xed3_capture_nt_nop, +/* +VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3751*/ xed3_capture_chain_MODRM, +/* +VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3752*/ xed3_capture_nt_nop, +/* +VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3753*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3754*/ xed3_capture_nt_nop, +/* +VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3755*/ xed3_capture_chain_MODRM, +/* +VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3756*/ xed3_capture_nt_nop, +/* +VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3757*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3758*/ xed3_capture_nt_nop, +/* +VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3759*/ xed3_capture_chain_MODRM, +/* +VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3760*/ xed3_capture_nt_nop, +/* +VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3761*/ xed3_capture_chain_MODRM, +/* +VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3762*/ xed3_capture_chain_MODRM, +/* +VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3763*/ xed3_capture_nt_nop, +/* +VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3764*/ xed3_capture_chain_MODRM, +/* +VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3765*/ xed3_capture_nt_nop, +/* +VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3766*/ xed3_capture_chain_MODRM, +/* +VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3767*/ xed3_capture_nt_nop, +/* +VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3768*/ xed3_capture_chain_MODRM, +/* +VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3769*/ xed3_capture_nt_nop, +/* +VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3770*/ xed3_capture_chain_MODRM, +/* +VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3771*/ xed3_capture_nt_nop, +/* +VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3772*/ xed3_capture_chain_MODRM, +/* +VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3773*/ xed3_capture_nt_nop, +/* +VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3774*/ xed3_capture_chain_MODRM, +/* +VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3775*/ xed3_capture_nt_nop, +/* +VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3776*/ xed3_capture_chain_MODRM, +/* +VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3777*/ xed3_capture_nt_nop, +/* +VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +inum=3778*/ xed3_capture_chain_MODRM, +/* +VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +inum=3779*/ xed3_capture_nt_nop, +/* +VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3780*/ xed3_capture_chain_MODRM, +/* +VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3781*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3782*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3783*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3784*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3785*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3786*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3787*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3788*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3789*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3790*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3791*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3792*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3793*/ xed3_capture_nt_nop, +/* +VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3794*/ xed3_capture_chain_MODRM, +/* +VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3795*/ xed3_capture_chain_MODRM, +/* +VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3796*/ xed3_capture_nt_nop, +/* +VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3797*/ xed3_capture_nt_nop, +/* +VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3798*/ xed3_capture_chain_MODRM, +/* +VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3799*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=3800*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=3801*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=3802*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=3803*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() +inum=3804*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn] +inum=3805*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=3806*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=3807*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=3808*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=3809*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() +inum=3810*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn] +inum=3811*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=3812*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=3813*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=3814*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=3815*/ xed3_capture_nt_nop, +/* +VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() +inum=3816*/ xed3_capture_chain_MODRM, +/* +VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn] +inum=3817*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3818*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3819*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3820*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3821*/ xed3_capture_nt_nop, +/* +VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3822*/ xed3_capture_chain_MODRM, +/* +VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3823*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3824*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3825*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3826*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3827*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3828*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3829*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3830*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3831*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3832*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3833*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3834*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3835*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3836*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3837*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3838*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3839*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3840*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3841*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3842*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3843*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3844*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3845*/ xed3_capture_nt_nop, +/* +VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3846*/ xed3_capture_chain_MODRM, +/* +VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3847*/ xed3_capture_nt_nop, +/* +VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3848*/ xed3_capture_nt_nop, +/* +VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3849*/ xed3_capture_nt_nop, +/* +VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3850*/ xed3_capture_chain_MODRM, +/* +VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3851*/ xed3_capture_chain_MODRM, +/* +VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] +inum=3852*/ xed3_capture_nt_nop, +/* +VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() +inum=3853*/ xed3_capture_chain_MODRM, +/* +VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3854*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3855*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3856*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3857*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() +inum=3858*/ xed3_capture_chain_UIMM8, +/* +VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() +inum=3859*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3860*/ xed3_capture_nt_nop, +/* +VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3861*/ xed3_capture_nt_nop, +/* +VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3862*/ xed3_capture_nt_nop, +/* +VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +inum=3863*/ xed3_capture_chain_MODRM, +/* +VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +inum=3864*/ xed3_capture_chain_MODRM, +/* +VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3865*/ xed3_capture_nt_nop, +/* +VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3866*/ xed3_capture_nt_nop, +/* +VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3867*/ xed3_capture_nt_nop, +/* +VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3868*/ xed3_capture_nt_nop, +/* +VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3869*/ xed3_capture_nt_nop, +/* +VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +inum=3870*/ xed3_capture_chain_UIMM8, +/* +VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +inum=3871*/ xed3_capture_chain_UIMM8, +/* +VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3872*/ xed3_capture_nt_nop, +/* +VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3873*/ xed3_capture_nt_nop, +/* +VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3874*/ xed3_capture_nt_nop, +/* +VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3875*/ xed3_capture_nt_nop, +/* +VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3876*/ xed3_capture_nt_nop, +/* +VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3877*/ xed3_capture_nt_nop, +/* +VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3878*/ xed3_capture_nt_nop, +/* +VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3879*/ xed3_capture_nt_nop, +/* +VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3880*/ xed3_capture_nt_nop, +/* +VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3881*/ xed3_capture_nt_nop, +/* +VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3882*/ xed3_capture_nt_nop, +/* +VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3883*/ xed3_capture_nt_nop, +/* +VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3884*/ xed3_capture_nt_nop, +/* +VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3885*/ xed3_capture_nt_nop, +/* +VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +inum=3886*/ xed3_capture_chain_MODRM, +/* +VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR +inum=3887*/ xed3_capture_chain_MODRM, +/* +VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3888*/ xed3_capture_nt_nop, +/* +VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3889*/ xed3_capture_nt_nop, +/* +VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3890*/ xed3_capture_nt_nop, +/* +VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +inum=3891*/ xed3_capture_chain_MODRM, +/* +VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +inum=3892*/ xed3_capture_chain_MODRM, +/* +VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR +inum=3893*/ xed3_capture_nt_nop, +/* +VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR +inum=3894*/ xed3_capture_nt_nop, +/* +VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR +inum=3895*/ xed3_capture_nt_nop, +/* +VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR +inum=3896*/ xed3_capture_nt_nop, +/* +VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3897*/ xed3_capture_nt_nop, +/* +VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +inum=3898*/ xed3_capture_chain_MODRM, +/* +VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR +inum=3899*/ xed3_capture_chain_MODRM, +/* +VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR +inum=3900*/ xed3_capture_nt_nop, +/* +VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR +inum=3901*/ xed3_capture_nt_nop, +/* +VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3902*/ xed3_capture_nt_nop, +/* +VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3903*/ xed3_capture_nt_nop, +/* +VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3904*/ xed3_capture_nt_nop, +/* +VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3905*/ xed3_capture_nt_nop, +/* +VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3906*/ xed3_capture_nt_nop, +/* +VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3907*/ xed3_capture_nt_nop, +/* +VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3908*/ xed3_capture_nt_nop, +/* +VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3909*/ xed3_capture_nt_nop, +/* +VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3910*/ xed3_capture_nt_nop, +/* +VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +inum=3911*/ xed3_capture_chain_UIMM8, +/* +VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +inum=3912*/ xed3_capture_chain_UIMM8, +/* +VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +inum=3913*/ xed3_capture_chain_UIMM8, +/* +VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +inum=3914*/ xed3_capture_chain_UIMM8, +/* +VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8() +inum=3915*/ xed3_capture_chain_UIMM8, +/* +VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8() +inum=3916*/ xed3_capture_chain_UIMM8, +/* +VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3917*/ xed3_capture_nt_nop, +/* +VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3918*/ xed3_capture_nt_nop, +/* +VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR +inum=3919*/ xed3_capture_nt_nop, +/* +VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR +inum=3920*/ xed3_capture_nt_nop, +/* +VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3921*/ xed3_capture_nt_nop, +/* +VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3922*/ xed3_capture_nt_nop, +/* +VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3923*/ xed3_capture_nt_nop, +/* +VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3924*/ xed3_capture_nt_nop, +/* +VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3925*/ xed3_capture_nt_nop, +/* +VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3926*/ xed3_capture_nt_nop, +/* +VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3927*/ xed3_capture_nt_nop, +/* +VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 +inum=3928*/ xed3_capture_nt_nop, +/* +VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=3929*/ xed3_capture_chain_UIMM8, +/* +VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +inum=3930*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=3931*/ xed3_capture_chain_UIMM8, +/* +VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +inum=3932*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=3933*/ xed3_capture_chain_UIMM8, +/* +VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() +inum=3934*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=3935*/ xed3_capture_chain_UIMM8, +/* +VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() +inum=3936*/ xed3_capture_chain_MODRM_UIMM8, +/* +VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +inum=3937*/ xed3_capture_nt_nop, +/* +VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +inum=3938*/ xed3_capture_chain_MODRM, +/* +VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3939*/ xed3_capture_nt_nop, +/* +VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3940*/ xed3_capture_chain_MODRM, +/* +VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +inum=3941*/ xed3_capture_nt_nop, +/* +VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +inum=3942*/ xed3_capture_chain_MODRM, +/* +VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3943*/ xed3_capture_nt_nop, +/* +VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3944*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +inum=3945*/ xed3_capture_nt_nop, +/* +VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +inum=3946*/ xed3_capture_chain_MODRM, +/* +VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3947*/ xed3_capture_nt_nop, +/* +VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3948*/ xed3_capture_chain_MODRM, +/* +VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +inum=3949*/ xed3_capture_nt_nop, +/* +VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +inum=3950*/ xed3_capture_chain_MODRM, +/* +VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3951*/ xed3_capture_nt_nop, +/* +VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3952*/ xed3_capture_chain_MODRM, +/* +VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 +inum=3953*/ xed3_capture_nt_nop, +/* +VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 +inum=3954*/ xed3_capture_chain_MODRM, +/* +VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0 +inum=3955*/ xed3_capture_nt_nop, +/* +VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 +inum=3956*/ xed3_capture_chain_MODRM, +/* +VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR +inum=3957*/ xed3_capture_chain_MODRM, +/* +VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR +inum=3958*/ xed3_capture_chain_MODRM, +/* +VV1 0x5C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +inum=3959*/ xed3_capture_nt_nop, +/* +VV1 0x5E VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +inum=3960*/ xed3_capture_nt_nop, +/* +VV1 0x5E VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +inum=3961*/ xed3_capture_nt_nop, +/* +VV1 0x5E V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +inum=3962*/ xed3_capture_nt_nop, +/* +VV1 0x5E VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 +inum=3963*/ xed3_capture_nt_nop, +/* +VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +inum=3964*/ xed3_capture_chain_MODRM, +/* +VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +inum=3965*/ xed3_capture_chain_MODRM, +/* +VV1 0x49 VNP V0F38 MOD[0b11] MOD=3 REG[0b000] RM[0b000] VL128 W0 mode64 NOVSR +inum=3966*/ xed3_capture_nt_nop, +/* +VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR +inum=3967*/ xed3_capture_chain_MODRM, +/* +VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR +inum=3968*/ xed3_capture_nt_nop, +/* +EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=3969*/ xed3_capture_nt_nop, +/* +EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3970*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=3971*/ xed3_capture_nt_nop, +/* +EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3972*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=3973*/ xed3_capture_nt_nop, +/* +EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3974*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=3975*/ xed3_capture_nt_nop, +/* +EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3976*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=3977*/ xed3_capture_nt_nop, +/* +EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3978*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=3979*/ xed3_capture_nt_nop, +/* +EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3980*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=3981*/ xed3_capture_nt_nop, +/* +EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3982*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=3983*/ xed3_capture_nt_nop, +/* +EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3984*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=3985*/ xed3_capture_nt_nop, +/* +EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3986*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=3987*/ xed3_capture_nt_nop, +/* +EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3988*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=3989*/ xed3_capture_nt_nop, +/* +EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3990*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=3991*/ xed3_capture_nt_nop, +/* +EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3992*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=3993*/ xed3_capture_nt_nop, +/* +EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3994*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=3995*/ xed3_capture_nt_nop, +/* +EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3996*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=3997*/ xed3_capture_nt_nop, +/* +EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=3998*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=3999*/ xed3_capture_nt_nop, +/* +EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4000*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4001*/ xed3_capture_nt_nop, +/* +EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4002*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4003*/ xed3_capture_nt_nop, +/* +EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4004*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4005*/ xed3_capture_nt_nop, +/* +EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4006*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4007*/ xed3_capture_nt_nop, +/* +EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4008*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4009*/ xed3_capture_nt_nop, +/* +EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4010*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4011*/ xed3_capture_nt_nop, +/* +EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=4012*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4013*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4014*/ xed3_capture_nt_nop, +/* +EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4015*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4016*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4017*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4018*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4019*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4020*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4021*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4022*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4023*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4024*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4025*/ xed3_capture_nt_nop, +/* +EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=4026*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4027*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4028*/ xed3_capture_nt_nop, +/* +EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4029*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4030*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4031*/ xed3_capture_nt_nop, +/* +EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +inum=4032*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4033*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4034*/ xed3_capture_nt_nop, +/* +EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=4035*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4036*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4037*/ xed3_capture_nt_nop, +/* +EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=4038*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4039*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4040*/ xed3_capture_nt_nop, +/* +EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4041*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4042*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4043*/ xed3_capture_nt_nop, +/* +EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +inum=4044*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4045*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4046*/ xed3_capture_nt_nop, +/* +EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=4047*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4048*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4049*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4050*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4051*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4052*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4053*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4054*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4055*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4056*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +inum=4057*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X, +/* +EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +inum=4058*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X, +/* +EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +inum=4059*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X, +/* +EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +inum=4060*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X, +/* +EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +inum=4061*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X, +/* +EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X() +inum=4062*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X, +/* +EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4063*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4064*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4065*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4066*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4067*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4068*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4069*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4070*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4071*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4072*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4073*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4074*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4075*/ xed3_capture_nt_nop, +/* +EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4076*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4077*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4078*/ xed3_capture_nt_nop, +/* +EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4079*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4080*/ xed3_capture_nt_nop, +/* +EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4081*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4082*/ xed3_capture_nt_nop, +/* +EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4083*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4084*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4085*/ xed3_capture_nt_nop, +/* +EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4086*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4087*/ xed3_capture_nt_nop, +/* +EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4088*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4089*/ xed3_capture_nt_nop, +/* +EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4090*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4091*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4092*/ xed3_capture_nt_nop, +/* +EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4093*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4094*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=4095*/ xed3_capture_chain_UIMM8, +/* +EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4096*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=4097*/ xed3_capture_chain_UIMM8, +/* +EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4098*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=4099*/ xed3_capture_chain_UIMM8, +/* +EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4100*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=4101*/ xed3_capture_chain_UIMM8, +/* +EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4102*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=4103*/ xed3_capture_chain_UIMM8, +/* +EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4104*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=4105*/ xed3_capture_chain_UIMM8, +/* +EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4106*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4107*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4108*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4109*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4110*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4111*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4112*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4113*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4114*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4115*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4116*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4117*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4118*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +inum=4119*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +inum=4120*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +inum=4121*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE4, +/* +EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +inum=4122*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4() +inum=4123*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4() +inum=4124*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE4, +/* +EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +inum=4125*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1, +/* +EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4126*/ xed3_capture_nt_nop, +/* +EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +inum=4127*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1, +/* +EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4128*/ xed3_capture_nt_nop, +/* +EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +inum=4129*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4130*/ xed3_capture_nt_nop, +/* +EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +inum=4131*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4132*/ xed3_capture_nt_nop, +/* +EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +inum=4133*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4134*/ xed3_capture_nt_nop, +/* +EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +inum=4135*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8() +inum=4136*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4137*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +inum=4138*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4139*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +inum=4140*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4141*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +inum=4142*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +inum=4143*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4144*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +inum=4145*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4146*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +inum=4147*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4148*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8() +inum=4149*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8() +inum=4150*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=4151*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8() +inum=4152*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +inum=4153*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=4154*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4155*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +inum=4156*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +inum=4157*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR_FIX_ROUND_LEN128, +/* +EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4158*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +inum=4159*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +inum=4160*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR_FIX_ROUND_LEN128, +/* +EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4161*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4162*/ xed3_capture_nt_nop, +/* +EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4163*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4164*/ xed3_capture_nt_nop, +/* +EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4165*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4166*/ xed3_capture_nt_nop, +/* +EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4167*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4168*/ xed3_capture_nt_nop, +/* +EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4169*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4170*/ xed3_capture_nt_nop, +/* +EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4171*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4172*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4173*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() +inum=4174*/ xed3_capture_chain_FIX_ROUND_LEN512, +/* +EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4175*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4176*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4177*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4178*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4179*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4180*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=4181*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4182*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4183*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4184*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4185*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4186*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4187*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=4188*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4189*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4190*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4191*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4192*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4193*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4194*/ xed3_capture_nt_nop, +/* +EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=4195*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4196*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4197*/ xed3_capture_nt_nop, +/* +EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4198*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4199*/ xed3_capture_nt_nop, +/* +EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4200*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4201*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=4202*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4203*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4204*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4205*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4206*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4207*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4208*/ xed3_capture_nt_nop, +/* +EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4209*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=4210*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4211*/ xed3_capture_nt_nop, +/* +EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=4212*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4213*/ xed3_capture_nt_nop, +/* +EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=4214*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4215*/ xed3_capture_nt_nop, +/* +EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=4216*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4217*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4218*/ xed3_capture_nt_nop, +/* +EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4219*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4220*/ xed3_capture_nt_nop, +/* +EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4221*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4222*/ xed3_capture_nt_nop, +/* +EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4223*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4224*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4225*/ xed3_capture_nt_nop, +/* +EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4226*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4227*/ xed3_capture_nt_nop, +/* +EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4228*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=4229*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=4230*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +inum=4231*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=4232*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +inum=4233*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=4234*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM() +inum=4235*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4236*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=4237*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4238*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4239*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4240*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4241*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4242*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4243*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4244*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +inum=4245*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4246*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +inum=4247*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4248*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4249*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4250*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4251*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4252*/ xed3_capture_nt_nop, +/* +EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4253*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4254*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4255*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4256*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +inum=4257*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4258*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +inum=4259*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4260*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4261*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4262*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4263*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4264*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4265*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4266*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4267*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128() +inum=4268*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +inum=4269*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4270*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4271*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4272*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +inum=4273*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +inum=4274*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4275*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4276*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4277*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +inum=4278*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4279*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4280*/ xed3_capture_nt_nop, +/* +EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=4281*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4282*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4283*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4284*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +inum=4285*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4286*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +inum=4287*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4288*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4289*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4290*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4291*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4292*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4293*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 +inum=4294*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4295*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +inum=4296*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4297*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4298*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4299*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4300*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4301*/ xed3_capture_nt_nop, +/* +EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=4302*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4303*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4304*/ xed3_capture_nt_nop, +/* +EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4305*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4306*/ xed3_capture_nt_nop, +/* +EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4307*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4308*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=4309*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4310*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4311*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4312*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4313*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4314*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4315*/ xed3_capture_nt_nop, +/* +EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4316*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4317*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4318*/ xed3_capture_nt_nop, +/* +EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4319*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4320*/ xed3_capture_nt_nop, +/* +EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4321*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4322*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4323*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4324*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4325*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4326*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4327*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4328*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4329*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4330*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +inum=4331*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4332*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +inum=4333*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4334*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4335*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4336*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4337*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4338*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4339*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +inum=4340*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4341*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128() +inum=4342*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4343*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4344*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4345*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4346*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4347*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4348*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +inum=4349*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4350*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +inum=4351*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4352*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4353*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4354*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4355*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4356*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4357*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 +inum=4358*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4359*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128() +inum=4360*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4361*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128() +inum=4362*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=4363*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128() +inum=4364*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4365*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512() +inum=4366*/ xed3_capture_chain_FIX_ROUND_LEN512, +/* +EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4367*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4368*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4369*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4370*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=4371*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4372*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=4373*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4374*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4375*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4376*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4377*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4378*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4379*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4380*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4381*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4382*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128() +inum=4383*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND() +inum=4384*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4385*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4386*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4387*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +inum=4388*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0 +inum=4389*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4390*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4391*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=4392*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0 +inum=4393*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128() +inum=4394*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128, +/* +EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4395*/ xed3_capture_nt_nop, +/* +EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4396*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4397*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4398*/ xed3_capture_nt_nop, +/* +EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4399*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4400*/ xed3_capture_nt_nop, +/* +EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4401*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4402*/ xed3_capture_nt_nop, +/* +EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4403*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4404*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4405*/ xed3_capture_nt_nop, +/* +EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4406*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4407*/ xed3_capture_nt_nop, +/* +EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4408*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4409*/ xed3_capture_nt_nop, +/* +EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4410*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4411*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4412*/ xed3_capture_nt_nop, +/* +EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4413*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4414*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +inum=4415*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4416*/ xed3_capture_nt_nop, +/* +EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +inum=4417*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4418*/ xed3_capture_nt_nop, +/* +EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +inum=4419*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4420*/ xed3_capture_nt_nop, +/* +EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +inum=4421*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4422*/ xed3_capture_nt_nop, +/* +EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +inum=4423*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4424*/ xed3_capture_nt_nop, +/* +EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +inum=4425*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4426*/ xed3_capture_nt_nop, +/* +EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=4427*/ xed3_capture_chain_UIMM8, +/* +EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4428*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=4429*/ xed3_capture_chain_UIMM8, +/* +EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4430*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=4431*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +inum=4432*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE4, +/* +EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=4433*/ xed3_capture_chain_UIMM8, +/* +EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4434*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=4435*/ xed3_capture_chain_UIMM8, +/* +EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4436*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=4437*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +inum=4438*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE4, +/* +EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +inum=4439*/ xed3_capture_chain_UIMM8, +/* +EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +inum=4440*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=4441*/ xed3_capture_chain_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +inum=4442*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4443*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=4444*/ xed3_capture_chain_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4445*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=4446*/ xed3_capture_chain_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4447*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=4448*/ xed3_capture_chain_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +inum=4449*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4450*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=4451*/ xed3_capture_chain_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4452*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=4453*/ xed3_capture_chain_UIMM8, +/* +EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4454*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +inum=4455*/ xed3_capture_chain_UIMM8, +/* +EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +inum=4456*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=4457*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +inum=4458*/ xed3_capture_chain_UIMM8, +/* +EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=4459*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=4460*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4461*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4462*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4463*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4464*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4465*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4466*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4467*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4468*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4469*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4470*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4471*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4472*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4473*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4474*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4475*/ xed3_capture_nt_nop, +/* +EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4476*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4477*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4478*/ xed3_capture_nt_nop, +/* +EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4479*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4480*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4481*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4482*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4483*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4484*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4485*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4486*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4487*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4488*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4489*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4490*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4491*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4492*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4493*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4494*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4495*/ xed3_capture_nt_nop, +/* +EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4496*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4497*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4498*/ xed3_capture_nt_nop, +/* +EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4499*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4500*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4501*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4502*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4503*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4504*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4505*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4506*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4507*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4508*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4509*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4510*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4511*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4512*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4513*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4514*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4515*/ xed3_capture_nt_nop, +/* +EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4516*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4517*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4518*/ xed3_capture_nt_nop, +/* +EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4519*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4520*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4521*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4522*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4523*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4524*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4525*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4526*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4527*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4528*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4529*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4530*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4531*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4532*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4533*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4534*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4535*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4536*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4537*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4538*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4539*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4540*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4541*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4542*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4543*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4544*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4545*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4546*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4547*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4548*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4549*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4550*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4551*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4552*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4553*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4554*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4555*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4556*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4557*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4558*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4559*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4560*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4561*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4562*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4563*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4564*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4565*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4566*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4567*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4568*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4569*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4570*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4571*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4572*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4573*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4574*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4575*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4576*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4577*/ xed3_capture_nt_nop, +/* +EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4578*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4579*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4580*/ xed3_capture_nt_nop, +/* +EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4581*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4582*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4583*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4584*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4585*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4586*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4587*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4588*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4589*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4590*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4591*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4592*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4593*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4594*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4595*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4596*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4597*/ xed3_capture_nt_nop, +/* +EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4598*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4599*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4600*/ xed3_capture_nt_nop, +/* +EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4601*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4602*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4603*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4604*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4605*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4606*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4607*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4608*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4609*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4610*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4611*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4612*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4613*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4614*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4615*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4616*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4617*/ xed3_capture_nt_nop, +/* +EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4618*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4619*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4620*/ xed3_capture_nt_nop, +/* +EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4621*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4622*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4623*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4624*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4625*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4626*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4627*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4628*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4629*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4630*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4631*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4632*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4633*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4634*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4635*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4636*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4637*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4638*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4639*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4640*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4641*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4642*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4643*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4644*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4645*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4646*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4647*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4648*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4649*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4650*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4651*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4652*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4653*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4654*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4655*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4656*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4657*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4658*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4659*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4660*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4661*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4662*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4663*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4664*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4665*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4666*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4667*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4668*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4669*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4670*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4671*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4672*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4673*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4674*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4675*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4676*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4677*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4678*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4679*/ xed3_capture_nt_nop, +/* +EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4680*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4681*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4682*/ xed3_capture_nt_nop, +/* +EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4683*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4684*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4685*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4686*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4687*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4688*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4689*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4690*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4691*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4692*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4693*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4694*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4695*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4696*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4697*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4698*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4699*/ xed3_capture_nt_nop, +/* +EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4700*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4701*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4702*/ xed3_capture_nt_nop, +/* +EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4703*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4704*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4705*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4706*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4707*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4708*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4709*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4710*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4711*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4712*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4713*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4714*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4715*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4716*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4717*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4718*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4719*/ xed3_capture_nt_nop, +/* +EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4720*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4721*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4722*/ xed3_capture_nt_nop, +/* +EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4723*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4724*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4725*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4726*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4727*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4728*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4729*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4730*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4731*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4732*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4733*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4734*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4735*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4736*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4737*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4738*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4739*/ xed3_capture_nt_nop, +/* +EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4740*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4741*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4742*/ xed3_capture_nt_nop, +/* +EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4743*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4744*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4745*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4746*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4747*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4748*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4749*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4750*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4751*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4752*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4753*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4754*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4755*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4756*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4757*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4758*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4759*/ xed3_capture_nt_nop, +/* +EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4760*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4761*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4762*/ xed3_capture_nt_nop, +/* +EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4763*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4764*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4765*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=4766*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4767*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4768*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4769*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4770*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4771*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4772*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=4773*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4774*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4775*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4776*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4777*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4778*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4779*/ xed3_capture_nt_nop, +/* +EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=4780*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4781*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4782*/ xed3_capture_nt_nop, +/* +EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=4783*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4784*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4785*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4786*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4787*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4788*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4789*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4790*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4791*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4792*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=4793*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4794*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4795*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=4796*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4797*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=4798*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4799*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4800*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4801*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4802*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=4803*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4804*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=4805*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4806*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4807*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4808*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4809*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=4810*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4811*/ xed3_capture_nt_nop, +/* +EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +inum=4812*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4813*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4814*/ xed3_capture_nt_nop, +/* +EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=4815*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4816*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=4817*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +inum=4818*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4819*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +inum=4820*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4821*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=4822*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=4823*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=4824*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=4825*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4826*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=4827*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4828*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=4829*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=4830*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +inum=4831*/ xed3_capture_chain_UIMM8, +/* +EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +inum=4832*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=4833*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +inum=4834*/ xed3_capture_chain_UIMM8, +/* +EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=4835*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=4836*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=4837*/ xed3_capture_chain_UIMM8, +/* +EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4838*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=4839*/ xed3_capture_chain_UIMM8, +/* +EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4840*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=4841*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +inum=4842*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE4, +/* +EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=4843*/ xed3_capture_chain_UIMM8, +/* +EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4844*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=4845*/ xed3_capture_chain_UIMM8, +/* +EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4() +inum=4846*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4, +/* +EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=4847*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4() +inum=4848*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE4, +/* +EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8() +inum=4849*/ xed3_capture_chain_UIMM8, +/* +EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1() +inum=4850*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4851*/ xed3_capture_nt_nop, +/* +EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +inum=4852*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4853*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4854*/ xed3_capture_nt_nop, +/* +EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4855*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4856*/ xed3_capture_nt_nop, +/* +EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4857*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4858*/ xed3_capture_nt_nop, +/* +EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +inum=4859*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4860*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4861*/ xed3_capture_nt_nop, +/* +EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4862*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4863*/ xed3_capture_nt_nop, +/* +EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4864*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4865*/ xed3_capture_nt_nop, +/* +EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +inum=4866*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4867*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4868*/ xed3_capture_nt_nop, +/* +EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=4869*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4870*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=4871*/ xed3_capture_nt_nop, +/* +EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 +inum=4872*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4873*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=4874*/ xed3_capture_nt_nop, +/* +EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4875*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=4876*/ xed3_capture_nt_nop, +/* +EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=4877*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=4878*/ xed3_capture_nt_nop, +/* +EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +inum=4879*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4880*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=4881*/ xed3_capture_nt_nop, +/* +EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4882*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=4883*/ xed3_capture_nt_nop, +/* +EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=4884*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=4885*/ xed3_capture_nt_nop, +/* +EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 +inum=4886*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=4887*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=4888*/ xed3_capture_nt_nop, +/* +EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=4889*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=4890*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4891*/ xed3_capture_nt_nop, +/* +EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4892*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4893*/ xed3_capture_nt_nop, +/* +EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4894*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4895*/ xed3_capture_nt_nop, +/* +EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4896*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4897*/ xed3_capture_nt_nop, +/* +EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4898*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4899*/ xed3_capture_nt_nop, +/* +EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4900*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4901*/ xed3_capture_nt_nop, +/* +EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4902*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4903*/ xed3_capture_nt_nop, +/* +EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4904*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4905*/ xed3_capture_nt_nop, +/* +EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4906*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4907*/ xed3_capture_nt_nop, +/* +EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4908*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4909*/ xed3_capture_nt_nop, +/* +EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4910*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4911*/ xed3_capture_nt_nop, +/* +EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4912*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4913*/ xed3_capture_nt_nop, +/* +EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4914*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +inum=4915*/ xed3_capture_nt_nop, +/* +EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +inum=4916*/ xed3_capture_nt_nop, +/* +EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +inum=4917*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +inum=4918*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 +inum=4919*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 +inum=4920*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +inum=4921*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +inum=4922*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4923*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +inum=4924*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MOVDDUP, +/* +EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4925*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +inum=4926*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MOVDDUP, +/* +EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4927*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP() +inum=4928*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MOVDDUP, +/* +EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4929*/ xed3_capture_nt_nop, +/* +EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4930*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4931*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4932*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4933*/ xed3_capture_nt_nop, +/* +EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4934*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4935*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4936*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4937*/ xed3_capture_nt_nop, +/* +EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4938*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4939*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4940*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4941*/ xed3_capture_nt_nop, +/* +EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4942*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4943*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4944*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4945*/ xed3_capture_nt_nop, +/* +EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4946*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4947*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4948*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4949*/ xed3_capture_nt_nop, +/* +EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4950*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4951*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4952*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4953*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4954*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=4955*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4956*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4957*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4958*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=4959*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4960*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4961*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=4962*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=4963*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4964*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4965*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4966*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=4967*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4968*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4969*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4970*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=4971*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4972*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4973*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=4974*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=4975*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4976*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +inum=4977*/ xed3_capture_nt_nop, +/* +EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=4978*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=4979*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +inum=4980*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +inum=4981*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +inum=4982*/ xed3_capture_nt_nop, +/* +EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=4983*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=4984*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +inum=4985*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2() +inum=4986*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4987*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4988*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4989*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4990*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4991*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4992*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4993*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4994*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=4995*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4996*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4997*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=4998*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +inum=4999*/ xed3_capture_nt_nop, +/* +EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +inum=5000*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER, +/* +EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 +inum=5001*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +inum=5002*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=5003*/ xed3_capture_nt_nop, +/* +EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=5004*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=5005*/ xed3_capture_nt_nop, +/* +EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=5006*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR() +inum=5007*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR() +inum=5008*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5009*/ xed3_capture_nt_nop, +/* +EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5010*/ xed3_capture_nt_nop, +/* +EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5011*/ xed3_capture_nt_nop, +/* +EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5012*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5013*/ xed3_capture_nt_nop, +/* +EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5014*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5015*/ xed3_capture_nt_nop, +/* +EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5016*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5017*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5018*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5019*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5020*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5021*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5022*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR() +inum=5023*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5024*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5025*/ xed3_capture_nt_nop, +/* +EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5026*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5027*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=5028*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5029*/ xed3_capture_nt_nop, +/* +EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=5030*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5031*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=5032*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5033*/ xed3_capture_nt_nop, +/* +EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=5034*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5035*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM() +inum=5036*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5037*/ xed3_capture_nt_nop, +/* +EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM() +inum=5038*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5039*/ xed3_capture_nt_nop, +/* +EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5040*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5041*/ xed3_capture_nt_nop, +/* +EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=5042*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5043*/ xed3_capture_nt_nop, +/* +EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5044*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5045*/ xed3_capture_nt_nop, +/* +EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=5046*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5047*/ xed3_capture_nt_nop, +/* +EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM() +inum=5048*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5049*/ xed3_capture_nt_nop, +/* +EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM() +inum=5050*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM, +/* +EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5051*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=5052*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5053*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5054*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5055*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5056*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5057*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5058*/ xed3_capture_nt_nop, +/* +EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=5059*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5060*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5061*/ xed3_capture_nt_nop, +/* +EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5062*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5063*/ xed3_capture_nt_nop, +/* +EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5064*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5065*/ xed3_capture_nt_nop, +/* +EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=5066*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=5067*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5068*/ xed3_capture_nt_nop, +/* +EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=5069*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5070*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5071*/ xed3_capture_nt_nop, +/* +EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5072*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5073*/ xed3_capture_nt_nop, +/* +EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5074*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5075*/ xed3_capture_nt_nop, +/* +EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5076*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5077*/ xed3_capture_nt_nop, +/* +EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5078*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5079*/ xed3_capture_nt_nop, +/* +EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5080*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5081*/ xed3_capture_nt_nop, +/* +EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5082*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5083*/ xed3_capture_nt_nop, +/* +EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5084*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5085*/ xed3_capture_nt_nop, +/* +EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5086*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5087*/ xed3_capture_nt_nop, +/* +EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5088*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5089*/ xed3_capture_nt_nop, +/* +EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5090*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5091*/ xed3_capture_nt_nop, +/* +EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5092*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5093*/ xed3_capture_nt_nop, +/* +EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5094*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5095*/ xed3_capture_nt_nop, +/* +EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5096*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5097*/ xed3_capture_nt_nop, +/* +EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5098*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5099*/ xed3_capture_nt_nop, +/* +EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5100*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5101*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5102*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5103*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5104*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5105*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5106*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5107*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5108*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5109*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5110*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5111*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5112*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5113*/ xed3_capture_nt_nop, +/* +EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5114*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5115*/ xed3_capture_nt_nop, +/* +EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5116*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5117*/ xed3_capture_nt_nop, +/* +EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5118*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5119*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5120*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5121*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5122*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5123*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5124*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5125*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5126*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5127*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5128*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5129*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5130*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +inum=5131*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5132*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR +inum=5133*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR +inum=5134*/ xed3_capture_nt_nop, +/* +EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +inum=5135*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5136*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR +inum=5137*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR +inum=5138*/ xed3_capture_nt_nop, +/* +EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1() +inum=5139*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1, +/* +EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5140*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR +inum=5141*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR +inum=5142*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +inum=5143*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1, +/* +EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5144*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR +inum=5145*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +inum=5146*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1, +/* +EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5147*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR +inum=5148*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1() +inum=5149*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1, +/* +EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5150*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR +inum=5151*/ xed3_capture_nt_nop, +/* +EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +inum=5152*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5153*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +inum=5154*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5155*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +inum=5156*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5157*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=5158*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5159*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=5160*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5161*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=5162*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5163*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +inum=5164*/ xed3_capture_nt_nop, +/* +EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5165*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +inum=5166*/ xed3_capture_nt_nop, +/* +EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5167*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +inum=5168*/ xed3_capture_nt_nop, +/* +EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5169*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=5170*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5171*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=5172*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5173*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=5174*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5175*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +inum=5176*/ xed3_capture_nt_nop, +/* +EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5177*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +inum=5178*/ xed3_capture_nt_nop, +/* +EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5179*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +inum=5180*/ xed3_capture_nt_nop, +/* +EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5181*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +inum=5182*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5183*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +inum=5184*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5185*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +inum=5186*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5187*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +inum=5188*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5189*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +inum=5190*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5191*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +inum=5192*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5193*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +inum=5194*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5195*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +inum=5196*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5197*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +inum=5198*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5199*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5200*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5201*/ xed3_capture_nt_nop, +/* +EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5202*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5203*/ xed3_capture_nt_nop, +/* +EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5204*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5205*/ xed3_capture_nt_nop, +/* +EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5206*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5207*/ xed3_capture_nt_nop, +/* +EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5208*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5209*/ xed3_capture_nt_nop, +/* +EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5210*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5211*/ xed3_capture_nt_nop, +/* +EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5212*/ xed3_capture_nt_nop, +/* +EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5213*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5214*/ xed3_capture_nt_nop, +/* +EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5215*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5216*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5217*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5218*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5219*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5220*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5221*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5222*/ xed3_capture_nt_nop, +/* +EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5223*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5224*/ xed3_capture_nt_nop, +/* +EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5225*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5226*/ xed3_capture_nt_nop, +/* +EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5227*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5228*/ xed3_capture_nt_nop, +/* +EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5229*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5230*/ xed3_capture_nt_nop, +/* +EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5231*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5232*/ xed3_capture_nt_nop, +/* +EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5233*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5234*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5235*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5236*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5237*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5238*/ xed3_capture_nt_nop, +/* +EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5239*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=5240*/ xed3_capture_chain_UIMM8, +/* +EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5241*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5242*/ xed3_capture_nt_nop, +/* +EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5243*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +inum=5244*/ xed3_capture_chain_UIMM8, +/* +EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5245*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5246*/ xed3_capture_nt_nop, +/* +EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5247*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=5248*/ xed3_capture_chain_UIMM8, +/* +EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5249*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5250*/ xed3_capture_nt_nop, +/* +EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5251*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=5252*/ xed3_capture_chain_UIMM8, +/* +EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5253*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5254*/ xed3_capture_nt_nop, +/* +EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5255*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=5256*/ xed3_capture_chain_UIMM8, +/* +EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5257*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5258*/ xed3_capture_nt_nop, +/* +EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5259*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=5260*/ xed3_capture_chain_UIMM8, +/* +EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5261*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5262*/ xed3_capture_nt_nop, +/* +EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5263*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=5264*/ xed3_capture_chain_UIMM8, +/* +EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5265*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5266*/ xed3_capture_nt_nop, +/* +EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5267*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=5268*/ xed3_capture_chain_UIMM8, +/* +EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5269*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5270*/ xed3_capture_nt_nop, +/* +EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5271*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5272*/ xed3_capture_nt_nop, +/* +EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5273*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5274*/ xed3_capture_nt_nop, +/* +EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5275*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=5276*/ xed3_capture_chain_UIMM8, +/* +EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5277*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5278*/ xed3_capture_nt_nop, +/* +EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5279*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=5280*/ xed3_capture_chain_UIMM8, +/* +EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5281*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5282*/ xed3_capture_nt_nop, +/* +EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5283*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5284*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5285*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5286*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5287*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5288*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5289*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5290*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5291*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5292*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5293*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5294*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5295*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5296*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5297*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5298*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5299*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5300*/ xed3_capture_nt_nop, +/* +EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5301*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5302*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5303*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5304*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5305*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5306*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5307*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +inum=5308*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5309*/ xed3_capture_nt_nop, +/* +EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +inum=5310*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5311*/ xed3_capture_nt_nop, +/* +EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT() +inum=5312*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5313*/ xed3_capture_nt_nop, +/* +EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +inum=5314*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5315*/ xed3_capture_nt_nop, +/* +EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +inum=5316*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5317*/ xed3_capture_nt_nop, +/* +EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT() +inum=5318*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5319*/ xed3_capture_nt_nop, +/* +EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5320*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5321*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5322*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5323*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5324*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5325*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5326*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5327*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5328*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5329*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5330*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5331*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5332*/ xed3_capture_nt_nop, +/* +EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5333*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5334*/ xed3_capture_nt_nop, +/* +EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5335*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5336*/ xed3_capture_nt_nop, +/* +EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5337*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5338*/ xed3_capture_nt_nop, +/* +EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5339*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5340*/ xed3_capture_nt_nop, +/* +EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5341*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5342*/ xed3_capture_nt_nop, +/* +EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5343*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5344*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5345*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5346*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5347*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5348*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5349*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5350*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5351*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5352*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5353*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5354*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5355*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5356*/ xed3_capture_nt_nop, +/* +EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5357*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5358*/ xed3_capture_nt_nop, +/* +EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5359*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5360*/ xed3_capture_nt_nop, +/* +EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5361*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5362*/ xed3_capture_nt_nop, +/* +EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5363*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5364*/ xed3_capture_nt_nop, +/* +EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5365*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5366*/ xed3_capture_nt_nop, +/* +EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5367*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5368*/ xed3_capture_nt_nop, +/* +EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5369*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5370*/ xed3_capture_nt_nop, +/* +EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5371*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5372*/ xed3_capture_nt_nop, +/* +EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5373*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5374*/ xed3_capture_nt_nop, +/* +EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5375*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5376*/ xed3_capture_nt_nop, +/* +EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5377*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5378*/ xed3_capture_nt_nop, +/* +EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5379*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5380*/ xed3_capture_nt_nop, +/* +EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5381*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5382*/ xed3_capture_nt_nop, +/* +EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5383*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5384*/ xed3_capture_nt_nop, +/* +EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5385*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5386*/ xed3_capture_nt_nop, +/* +EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5387*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5388*/ xed3_capture_nt_nop, +/* +EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5389*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5390*/ xed3_capture_nt_nop, +/* +EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5391*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5392*/ xed3_capture_nt_nop, +/* +EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5393*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5394*/ xed3_capture_nt_nop, +/* +EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5395*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5396*/ xed3_capture_nt_nop, +/* +EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5397*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5398*/ xed3_capture_nt_nop, +/* +EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5399*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5400*/ xed3_capture_nt_nop, +/* +EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5401*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5402*/ xed3_capture_nt_nop, +/* +EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5403*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5404*/ xed3_capture_nt_nop, +/* +EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5405*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5406*/ xed3_capture_nt_nop, +/* +EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5407*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5408*/ xed3_capture_nt_nop, +/* +EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5409*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5410*/ xed3_capture_nt_nop, +/* +EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5411*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5412*/ xed3_capture_nt_nop, +/* +EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5413*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5414*/ xed3_capture_nt_nop, +/* +EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5415*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5416*/ xed3_capture_nt_nop, +/* +EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5417*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5418*/ xed3_capture_nt_nop, +/* +EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5419*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5420*/ xed3_capture_nt_nop, +/* +EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5421*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5422*/ xed3_capture_nt_nop, +/* +EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5423*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5424*/ xed3_capture_nt_nop, +/* +EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5425*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5426*/ xed3_capture_nt_nop, +/* +EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5427*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5428*/ xed3_capture_nt_nop, +/* +EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5429*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5430*/ xed3_capture_nt_nop, +/* +EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5431*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5432*/ xed3_capture_nt_nop, +/* +EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5433*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5434*/ xed3_capture_nt_nop, +/* +EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5435*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5436*/ xed3_capture_nt_nop, +/* +EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5437*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5438*/ xed3_capture_nt_nop, +/* +EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5439*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5440*/ xed3_capture_nt_nop, +/* +EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5441*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5442*/ xed3_capture_nt_nop, +/* +EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5443*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5444*/ xed3_capture_nt_nop, +/* +EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5445*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5446*/ xed3_capture_nt_nop, +/* +EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5447*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5448*/ xed3_capture_nt_nop, +/* +EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5449*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5450*/ xed3_capture_nt_nop, +/* +EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5451*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5452*/ xed3_capture_nt_nop, +/* +EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +inum=5453*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5454*/ xed3_capture_nt_nop, +/* +EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +inum=5455*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5456*/ xed3_capture_nt_nop, +/* +EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +inum=5457*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5458*/ xed3_capture_nt_nop, +/* +EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=5459*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5460*/ xed3_capture_nt_nop, +/* +EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=5461*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5462*/ xed3_capture_nt_nop, +/* +EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=5463*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5464*/ xed3_capture_nt_nop, +/* +EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5465*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5466*/ xed3_capture_nt_nop, +/* +EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5467*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5468*/ xed3_capture_nt_nop, +/* +EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5469*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5470*/ xed3_capture_nt_nop, +/* +EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5471*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5472*/ xed3_capture_nt_nop, +/* +EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5473*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5474*/ xed3_capture_nt_nop, +/* +EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5475*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5476*/ xed3_capture_nt_nop, +/* +EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5477*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5478*/ xed3_capture_nt_nop, +/* +EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5479*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5480*/ xed3_capture_nt_nop, +/* +EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM() +inum=5481*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5482*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5483*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5484*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5485*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5486*/ xed3_capture_nt_nop, +/* +EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5487*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5488*/ xed3_capture_nt_nop, +/* +EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5489*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5490*/ xed3_capture_nt_nop, +/* +EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5491*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5492*/ xed3_capture_nt_nop, +/* +EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM() +inum=5493*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5494*/ xed3_capture_nt_nop, +/* +EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5495*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5496*/ xed3_capture_nt_nop, +/* +EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5497*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5498*/ xed3_capture_nt_nop, +/* +EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5499*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5500*/ xed3_capture_nt_nop, +/* +EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5501*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5502*/ xed3_capture_nt_nop, +/* +EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5503*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5504*/ xed3_capture_nt_nop, +/* +EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM() +inum=5505*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM, +/* +EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5506*/ xed3_capture_nt_nop, +/* +EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5507*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5508*/ xed3_capture_nt_nop, +/* +EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5509*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5510*/ xed3_capture_nt_nop, +/* +EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM() +inum=5511*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM, +/* +EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5512*/ xed3_capture_nt_nop, +/* +EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +inum=5513*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5514*/ xed3_capture_nt_nop, +/* +EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +inum=5515*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5516*/ xed3_capture_nt_nop, +/* +EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM() +inum=5517*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM, +/* +EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5518*/ xed3_capture_nt_nop, +/* +EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=5519*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5520*/ xed3_capture_nt_nop, +/* +EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=5521*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5522*/ xed3_capture_nt_nop, +/* +EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM() +inum=5523*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM, +/* +EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=5524*/ xed3_capture_nt_nop, +/* +EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5525*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=5526*/ xed3_capture_nt_nop, +/* +EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5527*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=5528*/ xed3_capture_nt_nop, +/* +EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM() +inum=5529*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM, +/* +EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5530*/ xed3_capture_nt_nop, +/* +EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5531*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5532*/ xed3_capture_nt_nop, +/* +EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5533*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5534*/ xed3_capture_nt_nop, +/* +EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5535*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5536*/ xed3_capture_nt_nop, +/* +EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5537*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5538*/ xed3_capture_nt_nop, +/* +EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5539*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5540*/ xed3_capture_nt_nop, +/* +EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5541*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5542*/ xed3_capture_nt_nop, +/* +EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5543*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5544*/ xed3_capture_nt_nop, +/* +EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5545*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5546*/ xed3_capture_nt_nop, +/* +EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5547*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5548*/ xed3_capture_nt_nop, +/* +EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5549*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5550*/ xed3_capture_nt_nop, +/* +EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5551*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5552*/ xed3_capture_nt_nop, +/* +EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5553*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5554*/ xed3_capture_nt_nop, +/* +EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5555*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5556*/ xed3_capture_nt_nop, +/* +EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5557*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5558*/ xed3_capture_nt_nop, +/* +EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5559*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8() +inum=5560*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5561*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8() +inum=5562*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5563*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8() +inum=5564*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5565*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8() +inum=5566*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5567*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8() +inum=5568*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5569*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8() +inum=5570*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5571*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5572*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5573*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5574*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5575*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5576*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5577*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5578*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5579*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5580*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5581*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5582*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5583*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8() +inum=5584*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5585*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8() +inum=5586*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5587*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8() +inum=5588*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5589*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8() +inum=5590*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5591*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8() +inum=5592*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5593*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8() +inum=5594*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5595*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5596*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5597*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5598*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5599*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5600*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5601*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5602*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5603*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5604*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5605*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5606*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5607*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5608*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5609*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5610*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5611*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5612*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5613*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5614*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5615*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5616*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5617*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5618*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5619*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=5620*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5621*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=5622*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5623*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=5624*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5625*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5626*/ xed3_capture_nt_nop, +/* +EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5627*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8() +inum=5628*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5629*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5630*/ xed3_capture_nt_nop, +/* +EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5631*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8() +inum=5632*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5633*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5634*/ xed3_capture_nt_nop, +/* +EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5635*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8() +inum=5636*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5637*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5638*/ xed3_capture_nt_nop, +/* +EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5639*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8() +inum=5640*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5641*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5642*/ xed3_capture_nt_nop, +/* +EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5643*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8() +inum=5644*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5645*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5646*/ xed3_capture_nt_nop, +/* +EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5647*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8() +inum=5648*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5649*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5650*/ xed3_capture_nt_nop, +/* +EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5651*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5652*/ xed3_capture_nt_nop, +/* +EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5653*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5654*/ xed3_capture_nt_nop, +/* +EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5655*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5656*/ xed3_capture_nt_nop, +/* +EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5657*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5658*/ xed3_capture_nt_nop, +/* +EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5659*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5660*/ xed3_capture_nt_nop, +/* +EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5661*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5662*/ xed3_capture_nt_nop, +/* +EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5663*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8() +inum=5664*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5665*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5666*/ xed3_capture_nt_nop, +/* +EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5667*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8() +inum=5668*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5669*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5670*/ xed3_capture_nt_nop, +/* +EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5671*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8() +inum=5672*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5673*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5674*/ xed3_capture_nt_nop, +/* +EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5675*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8() +inum=5676*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5677*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5678*/ xed3_capture_nt_nop, +/* +EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5679*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8() +inum=5680*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5681*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5682*/ xed3_capture_nt_nop, +/* +EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5683*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8() +inum=5684*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5685*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5686*/ xed3_capture_nt_nop, +/* +EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5687*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5688*/ xed3_capture_nt_nop, +/* +EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5689*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5690*/ xed3_capture_nt_nop, +/* +EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5691*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5692*/ xed3_capture_nt_nop, +/* +EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5693*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5694*/ xed3_capture_nt_nop, +/* +EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5695*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5696*/ xed3_capture_nt_nop, +/* +EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5697*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5698*/ xed3_capture_nt_nop, +/* +EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5699*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8() +inum=5700*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5701*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5702*/ xed3_capture_nt_nop, +/* +EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5703*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8() +inum=5704*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5705*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5706*/ xed3_capture_nt_nop, +/* +EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128() +inum=5707*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128, +/* +EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8() +inum=5708*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5709*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5710*/ xed3_capture_nt_nop, +/* +EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5711*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8() +inum=5712*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5713*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5714*/ xed3_capture_nt_nop, +/* +EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5715*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8() +inum=5716*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5717*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5718*/ xed3_capture_nt_nop, +/* +EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128() +inum=5719*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8() +inum=5720*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5721*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5722*/ xed3_capture_nt_nop, +/* +EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5723*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5724*/ xed3_capture_nt_nop, +/* +EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5725*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5726*/ xed3_capture_nt_nop, +/* +EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5727*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5728*/ xed3_capture_nt_nop, +/* +EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5729*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5730*/ xed3_capture_nt_nop, +/* +EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5731*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5732*/ xed3_capture_nt_nop, +/* +EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5733*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5734*/ xed3_capture_nt_nop, +/* +EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5735*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5736*/ xed3_capture_nt_nop, +/* +EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5737*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5738*/ xed3_capture_nt_nop, +/* +EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5739*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5740*/ xed3_capture_nt_nop, +/* +EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5741*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5742*/ xed3_capture_nt_nop, +/* +EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5743*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5744*/ xed3_capture_nt_nop, +/* +EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5745*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=5746*/ xed3_capture_chain_UIMM8, +/* +EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5747*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=5748*/ xed3_capture_chain_UIMM8, +/* +EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5749*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=5750*/ xed3_capture_chain_UIMM8, +/* +EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5751*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=5752*/ xed3_capture_chain_UIMM8, +/* +EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5753*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=5754*/ xed3_capture_chain_UIMM8, +/* +EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5755*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=5756*/ xed3_capture_chain_UIMM8, +/* +EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5757*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=5758*/ xed3_capture_nt_nop, +/* +EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5759*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=5760*/ xed3_capture_nt_nop, +/* +EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5761*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=5762*/ xed3_capture_nt_nop, +/* +EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5763*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +inum=5764*/ xed3_capture_nt_nop, +/* +EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5765*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +inum=5766*/ xed3_capture_nt_nop, +/* +EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5767*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +inum=5768*/ xed3_capture_nt_nop, +/* +EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5769*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=5770*/ xed3_capture_nt_nop, +/* +EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5771*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=5772*/ xed3_capture_nt_nop, +/* +EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5773*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=5774*/ xed3_capture_nt_nop, +/* +EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL() +inum=5775*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +inum=5776*/ xed3_capture_nt_nop, +/* +EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5777*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +inum=5778*/ xed3_capture_nt_nop, +/* +EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5779*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +inum=5780*/ xed3_capture_nt_nop, +/* +EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL() +inum=5781*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5782*/ xed3_capture_nt_nop, +/* +EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5783*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5784*/ xed3_capture_nt_nop, +/* +EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5785*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5786*/ xed3_capture_nt_nop, +/* +EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5787*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5788*/ xed3_capture_nt_nop, +/* +EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5789*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5790*/ xed3_capture_nt_nop, +/* +EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5791*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5792*/ xed3_capture_nt_nop, +/* +EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5793*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5794*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5795*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5796*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5797*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5798*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5799*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5800*/ xed3_capture_nt_nop, +/* +EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5801*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5802*/ xed3_capture_nt_nop, +/* +EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5803*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5804*/ xed3_capture_nt_nop, +/* +EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5805*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5806*/ xed3_capture_nt_nop, +/* +EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5807*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5808*/ xed3_capture_nt_nop, +/* +EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5809*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5810*/ xed3_capture_nt_nop, +/* +EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5811*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5812*/ xed3_capture_nt_nop, +/* +EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5813*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5814*/ xed3_capture_nt_nop, +/* +EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5815*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5816*/ xed3_capture_nt_nop, +/* +EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5817*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5818*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5819*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5820*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5821*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5822*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5823*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5824*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5825*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5826*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5827*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5828*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5829*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5830*/ xed3_capture_nt_nop, +/* +EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=5831*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5832*/ xed3_capture_nt_nop, +/* +EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5833*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=5834*/ xed3_capture_chain_UIMM8, +/* +EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +inum=5835*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5836*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +inum=5837*/ xed3_capture_chain_UIMM8, +/* +EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5838*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=5839*/ xed3_capture_chain_UIMM8, +/* +EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5840*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=5841*/ xed3_capture_chain_UIMM8, +/* +EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=5842*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5843*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=5844*/ xed3_capture_chain_UIMM8, +/* +EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5845*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=5846*/ xed3_capture_chain_UIMM8, +/* +EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5847*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +inum=5848*/ xed3_capture_chain_UIMM8, +/* +EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +inum=5849*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=5850*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +inum=5851*/ xed3_capture_chain_UIMM8, +/* +EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=5852*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=5853*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5854*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5855*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5856*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5857*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5858*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5859*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5860*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5861*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5862*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5863*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5864*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5865*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5866*/ xed3_capture_nt_nop, +/* +EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=5867*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5868*/ xed3_capture_nt_nop, +/* +EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5869*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5870*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=5871*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5872*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5873*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5874*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5875*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5876*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5877*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=5878*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5879*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5880*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5881*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5882*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5883*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5884*/ xed3_capture_nt_nop, +/* +EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=5885*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=5886*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5887*/ xed3_capture_nt_nop, +/* +EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=5888*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5889*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5890*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5891*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5892*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5893*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5894*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5895*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5896*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5897*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT() +inum=5898*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT, +/* +EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5899*/ xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5900*/ xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT() +inum=5901*/ xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT, +/* +EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=5902*/ xed3_capture_chain_UIMM8, +/* +EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5903*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=5904*/ xed3_capture_chain_UIMM8, +/* +EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5905*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=5906*/ xed3_capture_chain_UIMM8, +/* +EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5907*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=5908*/ xed3_capture_chain_UIMM8, +/* +EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5909*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=5910*/ xed3_capture_chain_UIMM8, +/* +EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5911*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=5912*/ xed3_capture_chain_UIMM8, +/* +EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5913*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=5914*/ xed3_capture_chain_UIMM8, +/* +EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5915*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=5916*/ xed3_capture_chain_UIMM8, +/* +EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5917*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=5918*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5919*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=5920*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5921*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=5922*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=5923*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=5924*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5925*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=5926*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5927*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=5928*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=5929*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=5930*/ xed3_capture_nt_nop, +/* +EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=5931*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5932*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=5933*/ xed3_capture_nt_nop, +/* +EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5934*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=5935*/ xed3_capture_nt_nop, +/* +EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=5936*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=5937*/ xed3_capture_nt_nop, +/* +EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=5938*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5939*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=5940*/ xed3_capture_nt_nop, +/* +EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5941*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=5942*/ xed3_capture_nt_nop, +/* +EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=5943*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5944*/ xed3_capture_nt_nop, +/* +EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=5945*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=5946*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5947*/ xed3_capture_nt_nop, +/* +EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=5948*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5949*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5950*/ xed3_capture_nt_nop, +/* +EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 +inum=5951*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5952*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5953*/ xed3_capture_nt_nop, +/* +EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5954*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5955*/ xed3_capture_nt_nop, +/* +EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5956*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5957*/ xed3_capture_nt_nop, +/* +EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=5958*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5959*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5960*/ xed3_capture_nt_nop, +/* +EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5961*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5962*/ xed3_capture_nt_nop, +/* +EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5963*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 +inum=5964*/ xed3_capture_nt_nop, +/* +EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=5965*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=5966*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 +inum=5967*/ xed3_capture_nt_nop, +/* +EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=5968*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=5969*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=5970*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0 +inum=5971*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +inum=5972*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR_FIX_ROUND_LEN128, +/* +EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128() +inum=5973*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +inum=5974*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128() +inum=5975*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR_FIX_ROUND_LEN128, +/* +EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5976*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5977*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5978*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5979*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5980*/ xed3_capture_nt_nop, +/* +EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5981*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5982*/ xed3_capture_nt_nop, +/* +EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5983*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5984*/ xed3_capture_nt_nop, +/* +EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5985*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5986*/ xed3_capture_nt_nop, +/* +EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5987*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=5988*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5989*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=5990*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5991*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=5992*/ xed3_capture_nt_nop, +/* +EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=5993*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=5994*/ xed3_capture_nt_nop, +/* +EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5995*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=5996*/ xed3_capture_nt_nop, +/* +EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5997*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=5998*/ xed3_capture_nt_nop, +/* +EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=5999*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +inum=6000*/ xed3_capture_nt_nop, +/* +EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=6001*/ xed3_capture_nt_nop, +/* +EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +inum=6002*/ xed3_capture_nt_nop, +/* +EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +inum=6003*/ xed3_capture_nt_nop, +/* +EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +inum=6004*/ xed3_capture_nt_nop, +/* +EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +inum=6005*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6006*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=6007*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6008*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=6009*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6010*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=6011*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6012*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6013*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6014*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6015*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6016*/ xed3_capture_nt_nop, +/* +EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6017*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6018*/ xed3_capture_nt_nop, +/* +EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=6019*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6020*/ xed3_capture_nt_nop, +/* +EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=6021*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6022*/ xed3_capture_nt_nop, +/* +EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=6023*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6024*/ xed3_capture_nt_nop, +/* +EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6025*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6026*/ xed3_capture_nt_nop, +/* +EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6027*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6028*/ xed3_capture_nt_nop, +/* +EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6029*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6030*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6031*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6032*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6033*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6034*/ xed3_capture_nt_nop, +/* +EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6035*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6036*/ xed3_capture_nt_nop, +/* +EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6037*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6038*/ xed3_capture_nt_nop, +/* +EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6039*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6040*/ xed3_capture_nt_nop, +/* +EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6041*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6042*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6043*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6044*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6045*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6046*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6047*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6048*/ xed3_capture_nt_nop, +/* +EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6049*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6050*/ xed3_capture_nt_nop, +/* +EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6051*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6052*/ xed3_capture_nt_nop, +/* +EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6053*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6054*/ xed3_capture_nt_nop, +/* +EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +inum=6055*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6056*/ xed3_capture_nt_nop, +/* +EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +inum=6057*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +inum=6058*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE8, +/* +EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +inum=6059*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +inum=6060*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6061*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +inum=6062*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6063*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +inum=6064*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6065*/ xed3_capture_nt_nop, +/* +EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2() +inum=6066*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2, +/* +EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8() +inum=6067*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE8, +/* +EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +inum=6068*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2() +inum=6069*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6070*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6071*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6072*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6073*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6074*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=6075*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6076*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6077*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6078*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6079*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6080*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6081*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=6082*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6083*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6084*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6085*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6086*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6087*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6088*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=6089*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6090*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6091*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6092*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6093*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6094*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6095*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=6096*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6097*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6098*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6099*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6100*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6101*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6102*/ xed3_capture_nt_nop, +/* +EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND() +inum=6103*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6104*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6105*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6106*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6107*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6108*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6109*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=6110*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6111*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6112*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6113*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6114*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6115*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6116*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=6117*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6118*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6119*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6120*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6121*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6122*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6123*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR +inum=6124*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6125*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6126*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6127*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6128*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6129*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6130*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=6131*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6132*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6133*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6134*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6135*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6136*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6137*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=6138*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF() +inum=6139*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6140*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6141*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6142*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6143*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6144*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND() +inum=6145*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6146*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6147*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6148*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6149*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6150*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6151*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=6152*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=6153*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=6154*/ xed3_capture_chain_UIMM8, +/* +EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6155*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=6156*/ xed3_capture_chain_UIMM8, +/* +EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6157*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=6158*/ xed3_capture_chain_UIMM8, +/* +EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6159*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=6160*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +inum=6161*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE8, +/* +EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=6162*/ xed3_capture_chain_UIMM8, +/* +EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6163*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=6164*/ xed3_capture_chain_UIMM8, +/* +EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6165*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=6166*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +inum=6167*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE8, +/* +EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=6168*/ xed3_capture_chain_UIMM8, +/* +EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6169*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=6170*/ xed3_capture_chain_UIMM8, +/* +EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6171*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8() +inum=6172*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6173*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8() +inum=6174*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6175*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8() +inum=6176*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6177*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +inum=6178*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6179*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +inum=6180*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6181*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +inum=6182*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6183*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8() +inum=6184*/ xed3_capture_chain_UIMM8, +/* +EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=6185*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8() +inum=6186*/ xed3_capture_chain_UIMM8, +/* +EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=6187*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=6188*/ xed3_capture_chain_UIMM8, +/* +EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +inum=6189*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE8, +/* +EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6190*/ xed3_capture_chain_UIMM8, +/* +EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6191*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6192*/ xed3_capture_chain_UIMM8, +/* +EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6193*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=6194*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8() +inum=6195*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE8, +/* +EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6196*/ xed3_capture_chain_UIMM8, +/* +EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6197*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6198*/ xed3_capture_chain_UIMM8, +/* +EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2() +inum=6199*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2, +/* +EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6200*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6201*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6202*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6203*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6204*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6205*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6206*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6207*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6208*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6209*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6210*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6211*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6212*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6213*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6214*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6215*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6216*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6217*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6218*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6219*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6220*/ xed3_capture_nt_nop, +/* +EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6221*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6222*/ xed3_capture_nt_nop, +/* +EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6223*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6224*/ xed3_capture_nt_nop, +/* +EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6225*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6226*/ xed3_capture_nt_nop, +/* +EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6227*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6228*/ xed3_capture_nt_nop, +/* +EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6229*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6230*/ xed3_capture_nt_nop, +/* +EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6231*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6232*/ xed3_capture_nt_nop, +/* +EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6233*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6234*/ xed3_capture_nt_nop, +/* +EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6235*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=6236*/ xed3_capture_nt_nop, +/* +EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6237*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=6238*/ xed3_capture_nt_nop, +/* +EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6239*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=6240*/ xed3_capture_nt_nop, +/* +EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6241*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=6242*/ xed3_capture_nt_nop, +/* +EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6243*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=6244*/ xed3_capture_nt_nop, +/* +EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6245*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=6246*/ xed3_capture_nt_nop, +/* +EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6247*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6248*/ xed3_capture_nt_nop, +/* +EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6249*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6250*/ xed3_capture_nt_nop, +/* +EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6251*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6252*/ xed3_capture_nt_nop, +/* +EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6253*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6254*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6255*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6256*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6257*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6258*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6259*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6260*/ xed3_capture_nt_nop, +/* +EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6261*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6262*/ xed3_capture_nt_nop, +/* +EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6263*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6264*/ xed3_capture_nt_nop, +/* +EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6265*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6266*/ xed3_capture_nt_nop, +/* +EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6267*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6268*/ xed3_capture_nt_nop, +/* +EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6269*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6270*/ xed3_capture_nt_nop, +/* +EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6271*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6272*/ xed3_capture_nt_nop, +/* +EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6273*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6274*/ xed3_capture_nt_nop, +/* +EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6275*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6276*/ xed3_capture_nt_nop, +/* +EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6277*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6278*/ xed3_capture_nt_nop, +/* +EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6279*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6280*/ xed3_capture_nt_nop, +/* +EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6281*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6282*/ xed3_capture_nt_nop, +/* +EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6283*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6284*/ xed3_capture_nt_nop, +/* +EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6285*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6286*/ xed3_capture_nt_nop, +/* +EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6287*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6288*/ xed3_capture_nt_nop, +/* +EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6289*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6290*/ xed3_capture_nt_nop, +/* +EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6291*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6292*/ xed3_capture_nt_nop, +/* +EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6293*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6294*/ xed3_capture_nt_nop, +/* +EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6295*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6296*/ xed3_capture_nt_nop, +/* +EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6297*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6298*/ xed3_capture_nt_nop, +/* +EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6299*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6300*/ xed3_capture_nt_nop, +/* +EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6301*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6302*/ xed3_capture_nt_nop, +/* +EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6303*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6304*/ xed3_capture_nt_nop, +/* +EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6305*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6306*/ xed3_capture_nt_nop, +/* +EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6307*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8() +inum=6308*/ xed3_capture_chain_UIMM8, +/* +EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +inum=6309*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8() +inum=6310*/ xed3_capture_chain_UIMM8, +/* +EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +inum=6311*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8() +inum=6312*/ xed3_capture_chain_UIMM8, +/* +EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +inum=6313*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6314*/ xed3_capture_nt_nop, +/* +EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6315*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6316*/ xed3_capture_nt_nop, +/* +EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6317*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6318*/ xed3_capture_nt_nop, +/* +EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6319*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6320*/ xed3_capture_nt_nop, +/* +EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6321*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6322*/ xed3_capture_nt_nop, +/* +EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6323*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6324*/ xed3_capture_nt_nop, +/* +EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6325*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6326*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6327*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6328*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6329*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6330*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6331*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6332*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6333*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6334*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6335*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6336*/ xed3_capture_nt_nop, +/* +EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6337*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6338*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +inum=6339*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_TUPLE1_BYTE, +/* +EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6340*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6341*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +inum=6342*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_TUPLE1_BYTE, +/* +EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6343*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6344*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE() +inum=6345*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_TUPLE1_BYTE, +/* +EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6346*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6347*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +inum=6348*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_TUPLE1_WORD, +/* +EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6349*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6350*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +inum=6351*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_TUPLE1_WORD, +/* +EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6352*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6353*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD() +inum=6354*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_TUPLE1_WORD, +/* +EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6355*/ xed3_capture_nt_nop, +/* +EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +inum=6356*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6357*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +inum=6358*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6359*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +inum=6360*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6361*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +inum=6362*/ xed3_capture_nt_nop, +/* +EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6363*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +inum=6364*/ xed3_capture_nt_nop, +/* +EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6365*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +inum=6366*/ xed3_capture_nt_nop, +/* +EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6367*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +inum=6368*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6369*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +inum=6370*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6371*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +inum=6372*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6373*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +inum=6374*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6375*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +inum=6376*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6377*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +inum=6378*/ xed3_capture_nt_nop, +/* +EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6379*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 +inum=6380*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6381*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 +inum=6382*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6383*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 +inum=6384*/ xed3_capture_nt_nop, +/* +EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6385*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +inum=6386*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6387*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +inum=6388*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6389*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +inum=6390*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6391*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +inum=6392*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6393*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +inum=6394*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6395*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +inum=6396*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6397*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8() +inum=6398*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6399*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8() +inum=6400*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6401*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8() +inum=6402*/ xed3_capture_chain_UIMM8, +/* +EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6403*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6404*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6405*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6406*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6407*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6408*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6409*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6410*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6411*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6412*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6413*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6414*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6415*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6416*/ xed3_capture_nt_nop, +/* +EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6417*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6418*/ xed3_capture_nt_nop, +/* +EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6419*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6420*/ xed3_capture_nt_nop, +/* +EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6421*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +inum=6422*/ xed3_capture_chain_UIMM8, +/* +EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE() +inum=6423*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_GPR_WRITER_STORE_BYTE, +/* +EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() +inum=6424*/ xed3_capture_chain_UIMM8, +/* +EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() +inum=6425*/ xed3_capture_chain_UIMM8, +/* +EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +inum=6426*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE() +inum=6427*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() +inum=6428*/ xed3_capture_chain_UIMM8, +/* +EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE() +inum=6429*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() +inum=6430*/ xed3_capture_chain_UIMM8, +/* +EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD() +inum=6431*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_GPR_WRITER_STORE_WORD, +/* +EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64 +inum=6432*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE +inum=6433*/ xed3_capture_chain_UIMM8, +/* +EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +inum=6434*/ xed3_capture_chain_UIMM8, +/* +EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE() +inum=6435*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_GPR_READER_BYTE, +/* +EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8() +inum=6436*/ xed3_capture_chain_UIMM8, +/* +EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() +inum=6437*/ xed3_capture_chain_UIMM8, +/* +EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +inum=6438*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER() +inum=6439*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() +inum=6440*/ xed3_capture_chain_UIMM8, +/* +EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER() +inum=6441*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_GPR_READER, +/* +EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +inum=6442*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD() +inum=6443*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_GPR_READER_WORD, +/* +EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6444*/ xed3_capture_nt_nop, +/* +EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6445*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6446*/ xed3_capture_nt_nop, +/* +EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6447*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6448*/ xed3_capture_nt_nop, +/* +EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6449*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6450*/ xed3_capture_nt_nop, +/* +EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6451*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6452*/ xed3_capture_nt_nop, +/* +EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6453*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6454*/ xed3_capture_nt_nop, +/* +EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6455*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6456*/ xed3_capture_nt_nop, +/* +EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6457*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6458*/ xed3_capture_nt_nop, +/* +EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6459*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6460*/ xed3_capture_nt_nop, +/* +EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6461*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6462*/ xed3_capture_nt_nop, +/* +EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6463*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6464*/ xed3_capture_nt_nop, +/* +EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6465*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6466*/ xed3_capture_nt_nop, +/* +EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6467*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6468*/ xed3_capture_nt_nop, +/* +EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6469*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6470*/ xed3_capture_nt_nop, +/* +EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6471*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6472*/ xed3_capture_nt_nop, +/* +EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6473*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6474*/ xed3_capture_nt_nop, +/* +EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6475*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6476*/ xed3_capture_nt_nop, +/* +EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6477*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6478*/ xed3_capture_nt_nop, +/* +EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6479*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6480*/ xed3_capture_nt_nop, +/* +EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6481*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6482*/ xed3_capture_nt_nop, +/* +EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6483*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6484*/ xed3_capture_nt_nop, +/* +EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6485*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6486*/ xed3_capture_nt_nop, +/* +EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6487*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6488*/ xed3_capture_nt_nop, +/* +EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6489*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6490*/ xed3_capture_nt_nop, +/* +EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6491*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6492*/ xed3_capture_nt_nop, +/* +EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6493*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6494*/ xed3_capture_nt_nop, +/* +EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6495*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6496*/ xed3_capture_nt_nop, +/* +EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6497*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6498*/ xed3_capture_nt_nop, +/* +EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6499*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6500*/ xed3_capture_nt_nop, +/* +EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6501*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6502*/ xed3_capture_nt_nop, +/* +EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6503*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +inum=6504*/ xed3_capture_nt_nop, +/* +EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +inum=6505*/ xed3_capture_nt_nop, +/* +EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +inum=6506*/ xed3_capture_nt_nop, +/* +EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +inum=6507*/ xed3_capture_nt_nop, +/* +EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +inum=6508*/ xed3_capture_nt_nop, +/* +EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +inum=6509*/ xed3_capture_nt_nop, +/* +EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +inum=6510*/ xed3_capture_nt_nop, +/* +EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +inum=6511*/ xed3_capture_nt_nop, +/* +EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +inum=6512*/ xed3_capture_nt_nop, +/* +EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0 +inum=6513*/ xed3_capture_nt_nop, +/* +EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0 +inum=6514*/ xed3_capture_nt_nop, +/* +EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0 +inum=6515*/ xed3_capture_nt_nop, +/* +EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=6516*/ xed3_capture_nt_nop, +/* +EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +inum=6517*/ xed3_capture_nt_nop, +/* +EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +inum=6518*/ xed3_capture_nt_nop, +/* +EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=6519*/ xed3_capture_nt_nop, +/* +EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +inum=6520*/ xed3_capture_nt_nop, +/* +EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +inum=6521*/ xed3_capture_nt_nop, +/* +EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=6522*/ xed3_capture_nt_nop, +/* +EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +inum=6523*/ xed3_capture_nt_nop, +/* +EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +inum=6524*/ xed3_capture_nt_nop, +/* +EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6525*/ xed3_capture_nt_nop, +/* +EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6526*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6527*/ xed3_capture_nt_nop, +/* +EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6528*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6529*/ xed3_capture_nt_nop, +/* +EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6530*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=6531*/ xed3_capture_nt_nop, +/* +EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +inum=6532*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=6533*/ xed3_capture_nt_nop, +/* +EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +inum=6534*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=6535*/ xed3_capture_nt_nop, +/* +EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +inum=6536*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6537*/ xed3_capture_nt_nop, +/* +EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6538*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6539*/ xed3_capture_nt_nop, +/* +EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6540*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6541*/ xed3_capture_nt_nop, +/* +EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6542*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0 +inum=6543*/ xed3_capture_nt_nop, +/* +EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0 +inum=6544*/ xed3_capture_nt_nop, +/* +EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0 +inum=6545*/ xed3_capture_nt_nop, +/* +EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6546*/ xed3_capture_nt_nop, +/* +EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6547*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6548*/ xed3_capture_nt_nop, +/* +EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6549*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6550*/ xed3_capture_nt_nop, +/* +EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM() +inum=6551*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR +inum=6552*/ xed3_capture_nt_nop, +/* +EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +inum=6553*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR +inum=6554*/ xed3_capture_nt_nop, +/* +EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +inum=6555*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR +inum=6556*/ xed3_capture_nt_nop, +/* +EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM() +inum=6557*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM, +/* +EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6558*/ xed3_capture_nt_nop, +/* +EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6559*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6560*/ xed3_capture_nt_nop, +/* +EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6561*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6562*/ xed3_capture_nt_nop, +/* +EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6563*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6564*/ xed3_capture_nt_nop, +/* +EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6565*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6566*/ xed3_capture_nt_nop, +/* +EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6567*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6568*/ xed3_capture_nt_nop, +/* +EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6569*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6570*/ xed3_capture_nt_nop, +/* +EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6571*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6572*/ xed3_capture_nt_nop, +/* +EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6573*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6574*/ xed3_capture_nt_nop, +/* +EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6575*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6576*/ xed3_capture_nt_nop, +/* +EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6577*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6578*/ xed3_capture_nt_nop, +/* +EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6579*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6580*/ xed3_capture_nt_nop, +/* +EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6581*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6582*/ xed3_capture_nt_nop, +/* +EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6583*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6584*/ xed3_capture_nt_nop, +/* +EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6585*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6586*/ xed3_capture_nt_nop, +/* +EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6587*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +inum=6588*/ xed3_capture_nt_nop, +/* +EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6589*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +inum=6590*/ xed3_capture_nt_nop, +/* +EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6591*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +inum=6592*/ xed3_capture_nt_nop, +/* +EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6593*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6594*/ xed3_capture_nt_nop, +/* +EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6595*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6596*/ xed3_capture_nt_nop, +/* +EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6597*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6598*/ xed3_capture_nt_nop, +/* +EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6599*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +inum=6600*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6601*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +inum=6602*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6603*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +inum=6604*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6605*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8() +inum=6606*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6607*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8() +inum=6608*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6609*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8() +inum=6610*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6611*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +inum=6612*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6613*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +inum=6614*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6615*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +inum=6616*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6617*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6618*/ xed3_capture_nt_nop, +/* +EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6619*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6620*/ xed3_capture_nt_nop, +/* +EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6621*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6622*/ xed3_capture_nt_nop, +/* +EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6623*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6624*/ xed3_capture_nt_nop, +/* +EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +inum=6625*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8() +inum=6626*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6627*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6628*/ xed3_capture_nt_nop, +/* +EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +inum=6629*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8() +inum=6630*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6631*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6632*/ xed3_capture_nt_nop, +/* +EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +inum=6633*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8() +inum=6634*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6635*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6636*/ xed3_capture_nt_nop, +/* +EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6637*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6638*/ xed3_capture_nt_nop, +/* +EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6639*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6640*/ xed3_capture_nt_nop, +/* +EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6641*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6642*/ xed3_capture_nt_nop, +/* +EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +inum=6643*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8() +inum=6644*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6645*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6646*/ xed3_capture_nt_nop, +/* +EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +inum=6647*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8() +inum=6648*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6649*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6650*/ xed3_capture_nt_nop, +/* +EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +inum=6651*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8() +inum=6652*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6653*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +inum=6654*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6655*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +inum=6656*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6657*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +inum=6658*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM() +inum=6659*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6660*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6661*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6662*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6663*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6664*/ xed3_capture_nt_nop, +/* +EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6665*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6666*/ xed3_capture_nt_nop, +/* +EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128() +inum=6667*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8() +inum=6668*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6669*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6670*/ xed3_capture_nt_nop, +/* +EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128() +inum=6671*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8() +inum=6672*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6673*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6674*/ xed3_capture_nt_nop, +/* +EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128() +inum=6675*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128, +/* +EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8() +inum=6676*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6677*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6678*/ xed3_capture_nt_nop, +/* +EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6679*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6680*/ xed3_capture_nt_nop, +/* +EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6681*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6682*/ xed3_capture_nt_nop, +/* +EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6683*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6684*/ xed3_capture_nt_nop, +/* +EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6685*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6686*/ xed3_capture_nt_nop, +/* +EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6687*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6688*/ xed3_capture_nt_nop, +/* +EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6689*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6690*/ xed3_capture_nt_nop, +/* +EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6691*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6692*/ xed3_capture_nt_nop, +/* +EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6693*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6694*/ xed3_capture_nt_nop, +/* +EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6695*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6696*/ xed3_capture_nt_nop, +/* +EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6697*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6698*/ xed3_capture_nt_nop, +/* +EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6699*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6700*/ xed3_capture_nt_nop, +/* +EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6701*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6702*/ xed3_capture_nt_nop, +/* +EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6703*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6704*/ xed3_capture_nt_nop, +/* +EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6705*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6706*/ xed3_capture_nt_nop, +/* +EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6707*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6708*/ xed3_capture_nt_nop, +/* +EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6709*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6710*/ xed3_capture_nt_nop, +/* +EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6711*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6712*/ xed3_capture_nt_nop, +/* +EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6713*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=6714*/ xed3_capture_nt_nop, +/* +EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6715*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=6716*/ xed3_capture_nt_nop, +/* +EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6717*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=6718*/ xed3_capture_nt_nop, +/* +EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6719*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +inum=6720*/ xed3_capture_nt_nop, +/* +EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6721*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +inum=6722*/ xed3_capture_nt_nop, +/* +EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6723*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +inum=6724*/ xed3_capture_nt_nop, +/* +EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6725*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=6726*/ xed3_capture_nt_nop, +/* +EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6727*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=6728*/ xed3_capture_nt_nop, +/* +EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6729*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=6730*/ xed3_capture_nt_nop, +/* +EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6731*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 +inum=6732*/ xed3_capture_nt_nop, +/* +EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6733*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 +inum=6734*/ xed3_capture_nt_nop, +/* +EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6735*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 +inum=6736*/ xed3_capture_nt_nop, +/* +EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6737*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6738*/ xed3_capture_nt_nop, +/* +EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6739*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6740*/ xed3_capture_nt_nop, +/* +EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6741*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6742*/ xed3_capture_nt_nop, +/* +EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6743*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6744*/ xed3_capture_nt_nop, +/* +EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6745*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6746*/ xed3_capture_nt_nop, +/* +EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6747*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6748*/ xed3_capture_nt_nop, +/* +EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6749*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6750*/ xed3_capture_nt_nop, +/* +EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6751*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6752*/ xed3_capture_nt_nop, +/* +EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6753*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6754*/ xed3_capture_nt_nop, +/* +EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6755*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 +inum=6756*/ xed3_capture_nt_nop, +/* +EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6757*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 +inum=6758*/ xed3_capture_nt_nop, +/* +EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6759*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 +inum=6760*/ xed3_capture_nt_nop, +/* +EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6761*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6762*/ xed3_capture_chain_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6763*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6764*/ xed3_capture_chain_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6765*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6766*/ xed3_capture_chain_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8() +inum=6767*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6768*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=6769*/ xed3_capture_chain_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6770*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=6771*/ xed3_capture_chain_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6772*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=6773*/ xed3_capture_chain_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8() +inum=6774*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6775*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +inum=6776*/ xed3_capture_chain_UIMM8, +/* +EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +inum=6777*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=6778*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +inum=6779*/ xed3_capture_chain_UIMM8, +/* +EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=6780*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=6781*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8() +inum=6782*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6783*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8() +inum=6784*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6785*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8() +inum=6786*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8() +inum=6787*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6788*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=6789*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6790*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=6791*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6792*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=6793*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=6794*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6795*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8() +inum=6796*/ xed3_capture_chain_UIMM8, +/* +EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8() +inum=6797*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR() +inum=6798*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8() +inum=6799*/ xed3_capture_chain_UIMM8, +/* +EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=6800*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR() +inum=6801*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6802*/ xed3_capture_nt_nop, +/* +EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6803*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6804*/ xed3_capture_nt_nop, +/* +EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6805*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6806*/ xed3_capture_nt_nop, +/* +EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6807*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6808*/ xed3_capture_nt_nop, +/* +EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6809*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6810*/ xed3_capture_nt_nop, +/* +EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6811*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6812*/ xed3_capture_nt_nop, +/* +EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6813*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6814*/ xed3_capture_nt_nop, +/* +EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6815*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6816*/ xed3_capture_nt_nop, +/* +EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6817*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6818*/ xed3_capture_nt_nop, +/* +EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6819*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6820*/ xed3_capture_nt_nop, +/* +EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6821*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6822*/ xed3_capture_nt_nop, +/* +EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6823*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6824*/ xed3_capture_nt_nop, +/* +EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6825*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6826*/ xed3_capture_nt_nop, +/* +EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6827*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6828*/ xed3_capture_nt_nop, +/* +EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6829*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6830*/ xed3_capture_nt_nop, +/* +EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6831*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6832*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6833*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6834*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6835*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6836*/ xed3_capture_nt_nop, +/* +EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6837*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6838*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6839*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6840*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6841*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6842*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6843*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6844*/ xed3_capture_nt_nop, +/* +EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6845*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6846*/ xed3_capture_nt_nop, +/* +EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6847*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6848*/ xed3_capture_nt_nop, +/* +EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6849*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6850*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6851*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6852*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6853*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6854*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM() +inum=6855*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6856*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6857*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6858*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6859*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6860*/ xed3_capture_nt_nop, +/* +EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM() +inum=6861*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 +inum=6862*/ xed3_capture_nt_nop, +/* +EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6863*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 +inum=6864*/ xed3_capture_nt_nop, +/* +EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6865*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 +inum=6866*/ xed3_capture_nt_nop, +/* +EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6867*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +inum=6868*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT, +/* +EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6869*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +inum=6870*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT, +/* +EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6871*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT() +inum=6872*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT, +/* +EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6873*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +inum=6874*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT, +/* +EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6875*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +inum=6876*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT, +/* +EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6877*/ xed3_capture_nt_nop, +/* +EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT() +inum=6878*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT, +/* +EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6879*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +inum=6880*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT, +/* +EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=6881*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +inum=6882*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT, +/* +EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=6883*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT() +inum=6884*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT, +/* +EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=6885*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +inum=6886*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT, +/* +EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=6887*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +inum=6888*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT, +/* +EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=6889*/ xed3_capture_nt_nop, +/* +EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT() +inum=6890*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT, +/* +EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=6891*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=6892*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6893*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=6894*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6895*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=6896*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6897*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6898*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6899*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6900*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6901*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6902*/ xed3_capture_chain_UIMM8, +/* +EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6903*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6904*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6905*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6906*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6907*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6908*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6909*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6910*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6911*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6912*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6913*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6914*/ xed3_capture_nt_nop, +/* +EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6915*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6916*/ xed3_capture_nt_nop, +/* +EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6917*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6918*/ xed3_capture_nt_nop, +/* +EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6919*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6920*/ xed3_capture_nt_nop, +/* +EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6921*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6922*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6923*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6924*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6925*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6926*/ xed3_capture_chain_UIMM8, +/* +EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6927*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8() +inum=6928*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6929*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8() +inum=6930*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6931*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8() +inum=6932*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL() +inum=6933*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6934*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6935*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6936*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6937*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6938*/ xed3_capture_chain_UIMM8, +/* +EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6939*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6940*/ xed3_capture_nt_nop, +/* +EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6941*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6942*/ xed3_capture_nt_nop, +/* +EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6943*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6944*/ xed3_capture_nt_nop, +/* +EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=6945*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6946*/ xed3_capture_nt_nop, +/* +EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6947*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6948*/ xed3_capture_nt_nop, +/* +EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6949*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6950*/ xed3_capture_nt_nop, +/* +EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL() +inum=6951*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 +inum=6952*/ xed3_capture_nt_nop, +/* +EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6953*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 +inum=6954*/ xed3_capture_nt_nop, +/* +EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6955*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 +inum=6956*/ xed3_capture_nt_nop, +/* +EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM() +inum=6957*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6958*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6959*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6960*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6961*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6962*/ xed3_capture_chain_UIMM8, +/* +EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM() +inum=6963*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM, +/* +EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6964*/ xed3_capture_chain_UIMM8, +/* +EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6965*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6966*/ xed3_capture_chain_UIMM8, +/* +EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6967*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6968*/ xed3_capture_chain_UIMM8, +/* +EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6969*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8() +inum=6970*/ xed3_capture_chain_UIMM8, +/* +EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6971*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8() +inum=6972*/ xed3_capture_chain_UIMM8, +/* +EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6973*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8() +inum=6974*/ xed3_capture_chain_UIMM8, +/* +EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL() +inum=6975*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=6976*/ xed3_capture_nt_nop, +/* +EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6977*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=6978*/ xed3_capture_nt_nop, +/* +EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6979*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=6980*/ xed3_capture_nt_nop, +/* +EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM() +inum=6981*/ xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM, +/* +EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +inum=6982*/ xed3_capture_nt_nop, +/* +EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6983*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +inum=6984*/ xed3_capture_nt_nop, +/* +EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6985*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +inum=6986*/ xed3_capture_nt_nop, +/* +EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6987*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +inum=6988*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6989*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +inum=6990*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6991*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +inum=6992*/ xed3_capture_nt_nop, +/* +EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6993*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +inum=6994*/ xed3_capture_nt_nop, +/* +EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6995*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +inum=6996*/ xed3_capture_nt_nop, +/* +EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6997*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +inum=6998*/ xed3_capture_nt_nop, +/* +EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=6999*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 +inum=7000*/ xed3_capture_nt_nop, +/* +EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=7001*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 +inum=7002*/ xed3_capture_nt_nop, +/* +EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=7003*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 +inum=7004*/ xed3_capture_nt_nop, +/* +EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM() +inum=7005*/ xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM, +/* +EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8() +inum=7006*/ xed3_capture_chain_UIMM8, +/* +EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +inum=7007*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8() +inum=7008*/ xed3_capture_chain_UIMM8, +/* +EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +inum=7009*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8() +inum=7010*/ xed3_capture_chain_UIMM8, +/* +EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM() +inum=7011*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM, +/* +EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 +inum=7012*/ xed3_capture_nt_nop, +/* +EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +inum=7013*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 MASK=0 +inum=7014*/ xed3_capture_nt_nop, +/* +EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +inum=7015*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 MASK=0 +inum=7016*/ xed3_capture_nt_nop, +/* +EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL() +inum=7017*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 MASK=0 +inum=7018*/ xed3_capture_nt_nop, +/* +EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +inum=7019*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 MASK=0 +inum=7020*/ xed3_capture_nt_nop, +/* +EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +inum=7021*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 MASK=0 +inum=7022*/ xed3_capture_nt_nop, +/* +EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL() +inum=7023*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7024*/ xed3_capture_nt_nop, +/* +EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7025*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7026*/ xed3_capture_nt_nop, +/* +EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7027*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7028*/ xed3_capture_nt_nop, +/* +EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7029*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7030*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7031*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7032*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7033*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8() +inum=7034*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7035*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8() +inum=7036*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7037*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8() +inum=7038*/ xed3_capture_chain_UIMM8, +/* +EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8() +inum=7039*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7040*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() +inum=7041*/ xed3_capture_chain_FIX_ROUND_LEN128_UIMM8, +/* +EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8() +inum=7042*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +inum=7043*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 +inum=7044*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +inum=7045*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7046*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7047*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7048*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7049*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7050*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7051*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7052*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7053*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=7054*/ xed3_capture_nt_nop, +/* +EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7055*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=7056*/ xed3_capture_nt_nop, +/* +EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7057*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=7058*/ xed3_capture_nt_nop, +/* +EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=7059*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7060*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7061*/ xed3_capture_nt_nop, +/* +EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7062*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7063*/ xed3_capture_nt_nop, +/* +EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7064*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7065*/ xed3_capture_nt_nop, +/* +EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7066*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7067*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7068*/ xed3_capture_nt_nop, +/* +EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7069*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7070*/ xed3_capture_nt_nop, +/* +EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7071*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7072*/ xed3_capture_nt_nop, +/* +EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7073*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7074*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7075*/ xed3_capture_nt_nop, +/* +EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7076*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7077*/ xed3_capture_nt_nop, +/* +EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7078*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7079*/ xed3_capture_nt_nop, +/* +EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7080*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7081*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7082*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7083*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7084*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7085*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7086*/ xed3_capture_nt_nop, +/* +EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7087*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7088*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7089*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7090*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7091*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7092*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7093*/ xed3_capture_nt_nop, +/* +EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7094*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7095*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7096*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7097*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7098*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7099*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7100*/ xed3_capture_nt_nop, +/* +EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7101*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7102*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7103*/ xed3_capture_nt_nop, +/* +EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7104*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7105*/ xed3_capture_nt_nop, +/* +EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7106*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7107*/ xed3_capture_nt_nop, +/* +EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7108*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7109*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7110*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7111*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7112*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7113*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7114*/ xed3_capture_nt_nop, +/* +EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7115*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7116*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7117*/ xed3_capture_nt_nop, +/* +EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7118*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7119*/ xed3_capture_nt_nop, +/* +EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7120*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7121*/ xed3_capture_nt_nop, +/* +EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7122*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7123*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=7124*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7125*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=7126*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7127*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=7128*/ xed3_capture_nt_nop, +/* +EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=7129*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7130*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 +inum=7131*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 +inum=7132*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR() +inum=7133*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_SCALAR, +/* +EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7134*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=7135*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7136*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7137*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7138*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7139*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7140*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7141*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7142*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7143*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7144*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7145*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7146*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=7147*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7148*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7149*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7150*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7151*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7152*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7153*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7154*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7155*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7156*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7157*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 +inum=7158*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0 +inum=7159*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +inum=7160*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 +inum=7161*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +inum=7162*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +inum=7163*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 +inum=7164*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +inum=7165*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +inum=7166*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_GPR_READER, +/* +EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7167*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7168*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=7169*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7170*/ xed3_capture_nt_nop, +/* +EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7171*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7172*/ xed3_capture_nt_nop, +/* +EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7173*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7174*/ xed3_capture_nt_nop, +/* +EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7175*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7176*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7177*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7178*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7179*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7180*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7181*/ xed3_capture_nt_nop, +/* +EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7182*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7183*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7184*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7185*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7186*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7187*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7188*/ xed3_capture_nt_nop, +/* +EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7189*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF() +inum=7190*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF, +/* +EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7191*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7192*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7193*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7194*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7195*/ xed3_capture_nt_nop, +/* +EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7196*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER() +inum=7197*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER, +/* +EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7198*/ xed3_capture_nt_nop, +/* +EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7199*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7200*/ xed3_capture_nt_nop, +/* +EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7201*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7202*/ xed3_capture_nt_nop, +/* +EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7203*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7204*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7205*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7206*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7207*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7208*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7209*/ xed3_capture_nt_nop, +/* +EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7210*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7211*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7212*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7213*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7214*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7215*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7216*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7217*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7218*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7219*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7220*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7221*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7222*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7223*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7224*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7225*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7226*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7227*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE +inum=7228*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE +inum=7229*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7230*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7231*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7232*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7233*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7234*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7235*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL() +inum=7236*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR +inum=7237*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7238*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR +inum=7239*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7240*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR +inum=7241*/ xed3_capture_nt_nop, +/* +EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR +inum=7242*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL() +inum=7243*/ xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL, +/* +EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 +inum=7244*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0 +inum=7245*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +inum=7246*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 +inum=7247*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0 +inum=7248*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() +inum=7249*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_GPR_READER, +/* +EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 +inum=7250*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0 +inum=7251*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() +inum=7252*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_GPR_READER, +/* +EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7253*/ xed3_capture_nt_nop, +/* +EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7254*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7255*/ xed3_capture_nt_nop, +/* +EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7256*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7257*/ xed3_capture_nt_nop, +/* +EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7258*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7259*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7260*/ xed3_capture_nt_nop, +/* +EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7261*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7262*/ xed3_capture_nt_nop, +/* +EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7263*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7264*/ xed3_capture_nt_nop, +/* +EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7265*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7266*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7267*/ xed3_capture_nt_nop, +/* +EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7268*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7269*/ xed3_capture_nt_nop, +/* +EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7270*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7271*/ xed3_capture_nt_nop, +/* +EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7272*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7273*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7274*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7275*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7276*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7277*/ xed3_capture_nt_nop, +/* +EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7278*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7279*/ xed3_capture_nt_nop, +/* +EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7280*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7281*/ xed3_capture_nt_nop, +/* +EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7282*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7283*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7284*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7285*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x57 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=7286*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7287*/ xed3_capture_nt_nop, +/* +EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7288*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7289*/ xed3_capture_nt_nop, +/* +EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7290*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7291*/ xed3_capture_nt_nop, +/* +EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7292*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7293*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7294*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7295*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xD7 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=7296*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7297*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7298*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7299*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7300*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7301*/ xed3_capture_nt_nop, +/* +EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7302*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7303*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7304*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7305*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x99 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7306*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7307*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7308*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7309*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7310*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7311*/ xed3_capture_nt_nop, +/* +EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7312*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7313*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7314*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7315*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xA9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7316*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7317*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7318*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7319*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7320*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7321*/ xed3_capture_nt_nop, +/* +EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7322*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7323*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7324*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7325*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xB9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7326*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7327*/ xed3_capture_nt_nop, +/* +EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7328*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7329*/ xed3_capture_nt_nop, +/* +EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7330*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7331*/ xed3_capture_nt_nop, +/* +EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7332*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7333*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7334*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7335*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x57 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=7336*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7337*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7338*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7339*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7340*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7341*/ xed3_capture_nt_nop, +/* +EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7342*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7343*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7344*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7345*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7346*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7347*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7348*/ xed3_capture_nt_nop, +/* +EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7349*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7350*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7351*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7352*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7353*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7354*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7355*/ xed3_capture_nt_nop, +/* +EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7356*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7357*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7358*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7359*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7360*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7361*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7362*/ xed3_capture_nt_nop, +/* +EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7363*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7364*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7365*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7366*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9B V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7367*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7368*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7369*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7370*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7371*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7372*/ xed3_capture_nt_nop, +/* +EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7373*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7374*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7375*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7376*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7377*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7378*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7379*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7380*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7381*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7382*/ xed3_capture_nt_nop, +/* +EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7383*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7384*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7385*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7386*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7387*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7388*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7389*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7390*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7391*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7392*/ xed3_capture_nt_nop, +/* +EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7393*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7394*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7395*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7396*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7397*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7398*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7399*/ xed3_capture_nt_nop, +/* +EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7400*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7401*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7402*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7403*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7404*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7405*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7406*/ xed3_capture_nt_nop, +/* +EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7407*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7408*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7409*/ xed3_capture_nt_nop, +/* +EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7410*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7411*/ xed3_capture_nt_nop, +/* +EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7412*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7413*/ xed3_capture_nt_nop, +/* +EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7414*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL() +inum=7415*/ xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL, +/* +EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7416*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7417*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xD7 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR() +inum=7418*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR, +/* +EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7419*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7420*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7421*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7422*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7423*/ xed3_capture_nt_nop, +/* +EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7424*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7425*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7426*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7427*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7428*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7429*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7430*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7431*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7432*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7433*/ xed3_capture_nt_nop, +/* +EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7434*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7435*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7436*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7437*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7438*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7439*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7440*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7441*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7442*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7443*/ xed3_capture_nt_nop, +/* +EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7444*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7445*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7446*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7447*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7448*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7449*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7450*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7451*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7452*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7453*/ xed3_capture_nt_nop, +/* +EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7454*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7455*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7456*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7457*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x9F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7458*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7459*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7460*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7461*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7462*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7463*/ xed3_capture_nt_nop, +/* +EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7464*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7465*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7466*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7467*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xAF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7468*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7469*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7470*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7471*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7472*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7473*/ xed3_capture_nt_nop, +/* +EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7474*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7475*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7476*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7477*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0xBF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7478*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8() +inum=7479*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7480*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8() +inum=7481*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7482*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8() +inum=7483*/ xed3_capture_chain_UIMM8, +/* +EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7484*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x67 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() +inum=7485*/ xed3_capture_chain_FIX_ROUND_LEN128_UIMM8, +/* +EVV 0x67 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +inum=7486*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7487*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7488*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7489*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7490*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7491*/ xed3_capture_nt_nop, +/* +EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR +inum=7492*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7493*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7494*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=7495*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x43 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7496*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=7497*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7498*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=7499*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7500*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=7501*/ xed3_capture_chain_UIMM8, +/* +EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=7502*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7503*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +inum=7504*/ xed3_capture_chain_FIX_ROUND_LEN128_UIMM8, +/* +EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=7505*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x27 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +inum=7506*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7507*/ xed3_capture_nt_nop, +/* +EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7508*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7509*/ xed3_capture_nt_nop, +/* +EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7510*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7511*/ xed3_capture_nt_nop, +/* +EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +inum=7512*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7513*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7514*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=7515*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7516*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7517*/ xed3_capture_nt_nop, +/* +EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7518*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7519*/ xed3_capture_nt_nop, +/* +EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7520*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7521*/ xed3_capture_nt_nop, +/* +EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 +inum=7522*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE, +/* +EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7523*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7524*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 +inum=7525*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7526*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x10 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ESIZE_16_BITS() NELEM_SCALAR() +inum=7527*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x11 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7528*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7529*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7530*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x6E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 +inum=7531*/ xed3_capture_nt_nop, +/* +EVV 0x6E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_READER() +inum=7532*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GPR_READER, +/* +EVV 0x7E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 +inum=7533*/ xed3_capture_nt_nop, +/* +EVV 0x7E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_STORE() +inum=7534*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GPR_WRITER_STORE, +/* +EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7535*/ xed3_capture_nt_nop, +/* +EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7536*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7537*/ xed3_capture_nt_nop, +/* +EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7538*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7539*/ xed3_capture_nt_nop, +/* +EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7540*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7541*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7542*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7543*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7544*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7545*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7546*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7547*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7548*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7549*/ xed3_capture_nt_nop, +/* +EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7550*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x4D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7551*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x4D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7552*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=7553*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7554*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=7555*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7556*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=7557*/ xed3_capture_chain_UIMM8, +/* +EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=7558*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7559*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +inum=7560*/ xed3_capture_chain_FIX_ROUND_LEN128_UIMM8, +/* +EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=7561*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x57 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +inum=7562*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8() +inum=7563*/ xed3_capture_chain_UIMM8, +/* +EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7564*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8() +inum=7565*/ xed3_capture_chain_UIMM8, +/* +EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7566*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8() +inum=7567*/ xed3_capture_chain_UIMM8, +/* +EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8() +inum=7568*/ xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8, +/* +EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL() +inum=7569*/ xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8() +inum=7570*/ xed3_capture_chain_FIX_ROUND_LEN128_UIMM8, +/* +EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8() +inum=7571*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8, +/* +EVV 0x0A VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR() +inum=7572*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7573*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7574*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7575*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7576*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7577*/ xed3_capture_nt_nop, +/* +EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7578*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x4F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7579*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x4F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7580*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7581*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7582*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7583*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7584*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7585*/ xed3_capture_nt_nop, +/* +EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7586*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7587*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7588*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7589*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x2D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7590*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR +inum=7591*/ xed3_capture_nt_nop, +/* +EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7592*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR +inum=7593*/ xed3_capture_nt_nop, +/* +EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7594*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR +inum=7595*/ xed3_capture_nt_nop, +/* +EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR +inum=7596*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL() +inum=7597*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7598*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7599*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7600*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 +inum=7601*/ xed3_capture_nt_nop, +/* +EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7602*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 +inum=7603*/ xed3_capture_nt_nop, +/* +EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7604*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 +inum=7605*/ xed3_capture_nt_nop, +/* +EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 +inum=7606*/ xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND, +/* +EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL() +inum=7607*/ xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL, +/* +EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 +inum=7608*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 +inum=7609*/ xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND, +/* +EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7610*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +/* +EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 +inum=7611*/ xed3_capture_chain_FIX_ROUND_LEN128, +/* +EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0 +inum=7612*/ xed3_capture_chain_FIX_ROUND_LEN128_SAE, +/* +EVV 0x2E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR() +inum=7613*/ xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR, +}; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-chain-capture.h b/CodeVirtualizer/build/obj/include-private/xed3-chain-capture.h new file mode 100644 index 0000000..7ec8362 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-chain-capture.h @@ -0,0 +1,2708 @@ +/// @file include-private/xed3-chain-capture.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_CHAIN_CAPTURE_H) +# define INCLUDE_PRIVATE_XED3_CHAIN_CAPTURE_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-nt-capture.h" +static XED_INLINE xed_error_enum_t xed3_capture_nt_nop(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_SIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_SIMMz(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_SIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_SIMMz(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ONE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ONE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_IMMUNE66_LOOP64_MODRM_CET_NO_TRACK(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_IMMUNE66_LOOP64_CET_NO_TRACK(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISPz(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISP32_DF64_FORCE64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRDISP32(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISP8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRDISP8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISPz_UIMM16(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_SIMMz(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_SIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MEMDISPv_OVERRIDE_SEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMMv(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_OVERRIDE_SEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRANCH_HINT_BRDISP8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRANCH_HINT_BRDISPz(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_REMOVE_SEGMENT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_OVERRIDE_SEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_UIMM16_IMMUNE66_LOOP64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_IMMUNE66_LOOP64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_UIMM16_UIMM8_1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM16(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISP8_FORCE64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM8_IMMUNE_REXW(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE_REXW(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_CR_WIDTH(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_MODRM_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66_MODRM_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_OVERRIDE_SEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_CR_WIDTH(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66_MODRM_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_MODRM_CR_WIDTH(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_UIMM8_UIMM8_1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM8_UIMM8_1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_REFINING66(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_IMMUNE66(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_SE_IMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_SE_IMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM32(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM32(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_VMODRM_XMM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_VMODRM_YMM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512_SAE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_SAE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MOVDDUP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE2(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_TUPLE1_BYTE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_TUPLE1_WORD(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_GPR_WRITER_STORE_BYTE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_GPR_WRITER_STORE_WORD(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_GPR_READER_BYTE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_GPR_READER_WORD(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_nt_nop(xed_decoded_inst_t* d) +{ +(void)d; +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_SIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_SIMMz(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SIMMz(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_SIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_SIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_SIMMz(xed_decoded_inst_t* d) +{ +xed3_capture_nt_SIMMz(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_MODRM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ONE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ONE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ONE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ONE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_IMMUNE66_LOOP64_MODRM_CET_NO_TRACK(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE66_LOOP64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_CET_NO_TRACK(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_IMMUNE66_LOOP64_CET_NO_TRACK(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE66_LOOP64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_CET_NO_TRACK(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISPz(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRDISPz(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISP32_DF64_FORCE64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRDISP32(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRDISP32(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISP32(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISP8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRDISP8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRDISP8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISP8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISPz_UIMM16(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRDISPz(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM16(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_SIMMz(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SIMMz(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_SIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_MODRM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_MODRM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66_MODRM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IGNORE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66_MODRM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IMMUNE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MEMDISPv_OVERRIDE_SEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MEMDISPv(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OVERRIDE_SEG0(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMMv(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UIMMv(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_OVERRIDE_SEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OVERRIDE_SEG0(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRANCH_HINT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISP8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRANCH_HINT_BRDISP8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRANCH_HINT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISP8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64_BRANCH_HINT_BRDISP32(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRANCH_HINT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISP32(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRANCH_HINT_BRDISPz(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRANCH_HINT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISPz(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_REMOVE_SEGMENT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_REMOVE_SEGMENT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_OVERRIDE_SEG1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OVERRIDE_SEG1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_UIMM16_IMMUNE66_LOOP64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM16(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE66_LOOP64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_IMMUNE66_LOOP64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE66_LOOP64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_UIMM16_UIMM8_1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM16(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8_1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM16(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UIMM16(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_DF64_BRDISP8_IMMUNE66_LOOP64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DF64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BRDISP8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE66_LOOP64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_BRDISP8_FORCE64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BRDISP8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM8_IMMUNE_REXW(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE_REXW(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE_REXW(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IMMUNE_REXW(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FORCE64(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FORCE64(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IGNORE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_CR_WIDTH(xed_decoded_inst_t* d) +{ +xed3_capture_nt_CR_WIDTH(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_MODRM_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66_MODRM_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IGNORE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IGNORE66_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IGNORE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_OVERRIDE_SEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OVERRIDE_SEG0(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_CR_WIDTH(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_CR_WIDTH(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66_MODRM_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IMMUNE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IMMUNE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_MODRM_CR_WIDTH(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_CR_WIDTH(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_REFINING66_UIMM8_UIMM8_1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8_1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM8_UIMM8_1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8_1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_REFINING66(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_REFINING66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_IMMUNE66(xed_decoded_inst_t* d) +{ +xed3_capture_nt_IMMUNE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_IMMUNE66(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_IMMUNE66(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_SE_IMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SE_IMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_SE_IMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_SE_IMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM32(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM32(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UIMM32(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UIMM32(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_VMODRM_XMM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VMODRM_XMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_VMODRM_YMM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VMODRM_YMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULL(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512_SAE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN512(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SAE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULL(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UISA_VMODRM_YMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UISA_VMODRM_ZMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_ZMM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UISA_VMODRM_ZMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_SAE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SAE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1_4X(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE1_4X(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512_AVX512_ROUND(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN512(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_AVX512_ROUND(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_AVX512_ROUND(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_AVX512_ROUND(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULL(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULL(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE4(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE4(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512_SAE_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN512(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SAE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_SAE_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SAE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_SCALAR_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_SCALAR_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN512(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN512(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALF(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_HALF(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_HALFMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_HALFMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_LDOP_Q_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_LDOP_Q(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_LDOP_D_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_LDOP_D(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE4(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE4(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE4(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_64_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UISA_VMODRM_XMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_XMM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UISA_VMODRM_XMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_UISA_VMODRM_YMM_ESIZE_32_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_UISA_VMODRM_YMM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE1(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MOVDDUP(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_MOVDDUP(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE2(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE2(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_QUARTERMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_QUARTERMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_EIGHTHMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_EIGHTHMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_HALFMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTERMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_QUARTERMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_MEM128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_MEM128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_MEM128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_MEM128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_32_BITS_NELEM_TUPLE8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_64_BITS_NELEM_TUPLE2(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE2(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_TUPLE8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_TUPLE2(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE2(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_TUPLE1_BYTE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE1_BYTE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_TUPLE1_WORD(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_TUPLE1_WORD(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_GPR_WRITER_STORE_BYTE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE_BYTE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_GPR_WRITER_STORE_WORD(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE_WORD(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_8_BITS_NELEM_GPR_READER_BYTE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER_BYTE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_32_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_64_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_GPR_READER_WORD(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER_WORD(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_HALFMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_HALFMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_MEM128(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_MEM128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_8_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_8_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GSCAT(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_128_BITS_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_128_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULLMEM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULL(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_UIMM8_ESIZE_16_BITS_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_FULL(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_FIX_ROUND_LEN128_UIMM8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_UIMM8_ESIZE_16_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_UIMM8(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_HALF(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_HALF(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_QUARTER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_QUARTER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_16_BITS_NELEM_GPR_WRITER_LDOP_D(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_LDOP_D(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_64_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_64_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_FIX_ROUND_LEN128_ESIZE_32_BITS_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FIX_ROUND_LEN128(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_32_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_SCALAR(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_READER(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_MODRM_ESIZE_16_BITS_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MODRM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ESIZE_16_BITS(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_NELEM_GPR_WRITER_STORE(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-dynamic-part1-capture.h b/CodeVirtualizer/build/obj/include-private/xed3-dynamic-part1-capture.h new file mode 100644 index 0000000..e7f107e --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-dynamic-part1-capture.h @@ -0,0 +1,41 @@ +/// @file include-private/xed3-dynamic-part1-capture.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_DYNAMIC_PART1_CAPTURE_H) +# define INCLUDE_PRIVATE_XED3_DYNAMIC_PART1_CAPTURE_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-nt-capture.h" +static XED_INLINE xed_error_enum_t xed3_dynamic_decode_part1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_dynamic_decode_part1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OSZ_NONTERM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ASZ_NONTERM(d); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-nt-capture.h b/CodeVirtualizer/build/obj/include-private/xed3-nt-capture.h new file mode 100644 index 0000000..1b1c798 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-nt-capture.h @@ -0,0 +1,14925 @@ +/// @file include-private/xed3-nt-capture.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_NT_CAPTURE_H) +# define INCLUDE_PRIVATE_XED3_NT_CAPTURE_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-operand-accessors.h" +#include "xed-ild.h" +static XED_INLINE void xed3_capture_nt_REMOVE_SEGMENT(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BRANCH_HINT(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_CET_NO_TRACK(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArAX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArBX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArCX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArDX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArSI(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArDI(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArSP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ArBP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SrSP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SrBP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar9(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar10(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar11(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar12(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar13(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar14(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_Ar15(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_rIP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_rIPa(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OeAX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OrAX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OrDX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OrCX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OrBX(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OrSP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OrBP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MMX_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MMX_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRv_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRv_SB(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRz_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRv_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRz_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRy_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPRy_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR64_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR64_SB(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR64_X(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR32_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR32_SB(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR32_X(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR16_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR16_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR16_SB(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_CR_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_CR_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_DR_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_X87(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SEG(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SEG_MOV(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_DSEG_NOT64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_DSEG_MODE64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_DSEG1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_DSEG1_NOT64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_DSEG1_MODE64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_ESEG(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_ESEG1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_SSEG1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_SSEG(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_SSEG_NOT64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FINAL_SSEG_MODE64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR8_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR8_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_GPR8_SB(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OSZ_NONTERM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_DF64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_REFINING66(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_IGNORE66(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_IMMUNE66(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_CR_WIDTH(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_IMMUNE66_LOOP64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_IMMUNE_REXW(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FORCE64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ASZ_NONTERM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ONE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UIMMv(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SIMMz(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SIMM8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UIMM8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UIMM8_1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UIMM16(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UIMM32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BRDISP8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BRDISP32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BRDISPz(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MEMDISPv(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MEMDISP32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MEMDISP16(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MEMDISP8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MEMDISP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MODRM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MODRM64alt32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MODRM32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MODRM16(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SIB(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SIB_BASE0(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OVERRIDE_SEG0(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_OVERRIDE_SEG1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_R_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_R_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_B_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_B_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BND_R_CHECK(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BND_B_CHECK(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BND_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_BND_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_A_GPR_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_A_GPR_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_SE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_SE64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_SE32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_SE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_SE64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_SE32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_N_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_N_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_N_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_N_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_R_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_R_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_B_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_B_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SE_IMM8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VMODRM_YMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VMODRM_XMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VSIB_YMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VSIB_XMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VSIB_INDEX_YMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VSIB_INDEX_XMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VSIB_BASE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPRy_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPRy_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPRy_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_N_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_N_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR64_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_R_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_R_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR64_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_B_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR32_B_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_VGPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_4X(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_AVX512_ROUND(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_SAE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_128_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_64_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_32_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_16_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_8_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_4_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_2_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ESIZE_1_BITS(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_MOVDDUP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_FULLMEM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_HALFMEM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_QUARTERMEM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_EIGHTHMEM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER_BYTE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER_WORD(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_LDOP_D(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_LDOP_Q(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE_BYTE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE_WORD(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_BYTE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_WORD(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_SCALAR(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_SUBDWORD(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER_SUBDWORD(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_LDOP(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE_SUBDWORD(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_GSCAT(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE2(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE4(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE8(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_MEM128(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_FULL(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_HALF(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FIX_ROUND_LEN512(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_FIX_ROUND_LEN128(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VMODRM_ZMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VMODRM_YMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VMODRM_XMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_ZMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_YMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_XMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_INDEX_ZMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_INDEX_YMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_INDEX_XMM(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_UISA_VSIB_BASE(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASK1(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASKNOT0(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASK_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASK_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASK_N64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_MASK_N32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_R3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_R3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_R3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_R3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_R3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_R3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_B3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_B3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_B3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_B3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_B3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_B3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_N3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_N3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_XMM_N3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_N3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_N3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_YMM_N3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_N3(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_N3_32(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_ZMM_N3_64(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_TMM_R(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_TMM_B(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_TMM_N(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_NELEM_QUARTER(xed_decoded_inst_t* d); + +static XED_INLINE void xed3_capture_nt_REMOVE_SEGMENT(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | SEG0=XED_REG_INVALID*/ + xed3_operand_set_seg0(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | SEG0=XED_REG_INVALID*/ + xed3_operand_set_seg0(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | SEG0=XED_REG_INVALID*/ + xed3_operand_set_seg0(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_BRANCH_HINT(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_hint(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> HINT=0 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> HINT=1 | HINT=3*/ + xed3_operand_set_hint(d, 0x3); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> HINT=2 | HINT=4*/ + xed3_operand_set_hint(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_CET_NO_TRACK(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_hint(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> HINT=0 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> HINT=1 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> HINT=2 | HINT=5*/ + xed3_operand_set_hint(d, 0x5); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArAX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_AX*/ + xed3_operand_set_outreg(d, XED_REG_AX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArBX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_BX*/ + xed3_operand_set_outreg(d, XED_REG_BX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArCX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_CX*/ + xed3_operand_set_outreg(d, XED_REG_CX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArDX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_DX*/ + xed3_operand_set_outreg(d, XED_REG_DX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArSI(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_SI*/ + xed3_operand_set_outreg(d, XED_REG_SI); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArDI(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_DI*/ + xed3_operand_set_outreg(d, XED_REG_DI); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArSP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_SP*/ + xed3_operand_set_outreg(d, XED_REG_SP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ArBP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_BP*/ + xed3_operand_set_outreg(d, XED_REG_BP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SrSP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_smode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> smode16 | OUTREG=XED_REG_SP*/ + xed3_operand_set_outreg(d, XED_REG_SP); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> smode32 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> smode64 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SrBP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_smode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> smode16 | OUTREG=XED_REG_BP*/ + xed3_operand_set_outreg(d, XED_REG_BP); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> smode32 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> smode64 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar8(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R8W*/ + xed3_operand_set_outreg(d, XED_REG_R8W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar9(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R9W*/ + xed3_operand_set_outreg(d, XED_REG_R9W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar10(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R10W*/ + xed3_operand_set_outreg(d, XED_REG_R10W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar11(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R11W*/ + xed3_operand_set_outreg(d, XED_REG_R11W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar12(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R12W*/ + xed3_operand_set_outreg(d, XED_REG_R12W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar13(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R13W*/ + xed3_operand_set_outreg(d, XED_REG_R13W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar14(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R14W*/ + xed3_operand_set_outreg(d, XED_REG_R14W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_Ar15(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 | OUTREG=XED_REG_R15W*/ + xed3_operand_set_outreg(d, XED_REG_R15W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_rIP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XED_REG_EIP*/ + xed3_operand_set_outreg(d, XED_REG_EIP); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XED_REG_EIP*/ + xed3_operand_set_outreg(d, XED_REG_EIP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XED_REG_RIP*/ + xed3_operand_set_outreg(d, XED_REG_RIP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_rIPa(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 2: /*(2,) -> EASZ=2 | OUTREG=XED_REG_EIP*/ + xed3_operand_set_outreg(d, XED_REG_EIP); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 | OUTREG=XED_REG_RIP*/ + xed3_operand_set_outreg(d, XED_REG_RIP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OeAX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_AX*/ + xed3_operand_set_outreg(d, XED_REG_AX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OrAX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_AX*/ + xed3_operand_set_outreg(d, XED_REG_AX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OrDX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_DX*/ + xed3_operand_set_outreg(d, XED_REG_DX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OrCX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_CX*/ + xed3_operand_set_outreg(d, XED_REG_CX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OrBX(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_BX*/ + xed3_operand_set_outreg(d, XED_REG_BX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OrSP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_SP*/ + xed3_operand_set_outreg(d, XED_REG_SP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OrBP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=XED_REG_BP*/ + xed3_operand_set_outreg(d, XED_REG_BP); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_rFLAGS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XED_REG_FLAGS*/ + xed3_operand_set_outreg(d, XED_REG_FLAGS); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XED_REG_EFLAGS*/ + xed3_operand_set_outreg(d, XED_REG_EFLAGS); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XED_REG_RFLAGS*/ + xed3_operand_set_outreg(d, XED_REG_RFLAGS); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MMX_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0x0 | OUTREG=XED_REG_MMX0*/ + xed3_operand_set_outreg(d, XED_REG_MMX0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=0x1 | OUTREG=XED_REG_MMX1*/ + xed3_operand_set_outreg(d, XED_REG_MMX1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=0x2 | OUTREG=XED_REG_MMX2*/ + xed3_operand_set_outreg(d, XED_REG_MMX2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=0x3 | OUTREG=XED_REG_MMX3*/ + xed3_operand_set_outreg(d, XED_REG_MMX3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=0x4 | OUTREG=XED_REG_MMX4*/ + xed3_operand_set_outreg(d, XED_REG_MMX4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=0x5 | OUTREG=XED_REG_MMX5*/ + xed3_operand_set_outreg(d, XED_REG_MMX5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=0x6 | OUTREG=XED_REG_MMX6*/ + xed3_operand_set_outreg(d, XED_REG_MMX6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=0x7 | OUTREG=XED_REG_MMX7*/ + xed3_operand_set_outreg(d, XED_REG_MMX7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MMX_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0x0 | OUTREG=XED_REG_MMX0*/ + xed3_operand_set_outreg(d, XED_REG_MMX0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=0x1 | OUTREG=XED_REG_MMX1*/ + xed3_operand_set_outreg(d, XED_REG_MMX1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=0x2 | OUTREG=XED_REG_MMX2*/ + xed3_operand_set_outreg(d, XED_REG_MMX2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=0x3 | OUTREG=XED_REG_MMX3*/ + xed3_operand_set_outreg(d, XED_REG_MMX3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=0x4 | OUTREG=XED_REG_MMX4*/ + xed3_operand_set_outreg(d, XED_REG_MMX4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=0x5 | OUTREG=XED_REG_MMX5*/ + xed3_operand_set_outreg(d, XED_REG_MMX5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=0x6 | OUTREG=XED_REG_MMX6*/ + xed3_operand_set_outreg(d, XED_REG_MMX6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=0x7 | OUTREG=XED_REG_MMX7*/ + xed3_operand_set_outreg(d, XED_REG_MMX7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRv_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR16_R()*/ + xed3_capture_nt_GPR16_R(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_R()*/ + xed3_capture_nt_GPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR64_R()*/ + xed3_capture_nt_GPR64_R(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRv_SB(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR16_SB()*/ + xed3_capture_nt_GPR16_SB(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_SB()*/ + xed3_capture_nt_GPR32_SB(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR64_SB()*/ + xed3_capture_nt_GPR64_SB(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRz_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR16_R()*/ + xed3_capture_nt_GPR16_R(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_R()*/ + xed3_capture_nt_GPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR32_R()*/ + xed3_capture_nt_GPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRv_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR16_B()*/ + xed3_capture_nt_GPR16_B(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_B()*/ + xed3_capture_nt_GPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR64_B()*/ + xed3_capture_nt_GPR64_B(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRz_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR16_B()*/ + xed3_capture_nt_GPR16_B(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_B()*/ + xed3_capture_nt_GPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR32_B()*/ + xed3_capture_nt_GPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRy_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR32_B()*/ + xed3_capture_nt_GPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_B()*/ + xed3_capture_nt_GPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR64_B()*/ + xed3_capture_nt_GPR64_B(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPRy_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=GPR32_R()*/ + xed3_capture_nt_GPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=GPR32_R()*/ + xed3_capture_nt_GPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=GPR64_R()*/ + xed3_capture_nt_GPR64_R(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR64_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR64_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR64_SB(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_srm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 SRM=0x0 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 SRM=0x0 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 SRM=0x1 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 SRM=0x1 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 SRM=0x2 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 SRM=0x2 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 SRM=0x3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 SRM=0x3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 SRM=0x4 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 SRM=0x4 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 SRM=0x5 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 SRM=0x5 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 SRM=0x6 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 SRM=0x6 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 SRM=0x7 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 SRM=0x7 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR64_X(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR32_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR32_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR32_SB(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_srm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 SRM=0x0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 SRM=0x0 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 SRM=0x1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 SRM=0x1 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 SRM=0x2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 SRM=0x2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 SRM=0x3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 SRM=0x3 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 SRM=0x4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 SRM=0x4 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 SRM=0x5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 SRM=0x5 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 SRM=0x6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 SRM=0x6 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 SRM=0x7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 SRM=0x7 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR32_X(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXX=0 SIBINDEX=0x0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXX=1 SIBINDEX=0x0 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXX=0 SIBINDEX=0x1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXX=1 SIBINDEX=0x1 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXX=0 SIBINDEX=0x2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXX=1 SIBINDEX=0x2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXX=0 SIBINDEX=0x3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXX=1 SIBINDEX=0x3 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXX=0 SIBINDEX=0x4 | OUTREG=XED_REG_INVALID*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXX=1 SIBINDEX=0x4 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXX=0 SIBINDEX=0x5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXX=1 SIBINDEX=0x5 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXX=0 SIBINDEX=0x6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXX=1 SIBINDEX=0x6 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXX=0 SIBINDEX=0x7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXX=1 SIBINDEX=0x7 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR16_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_AX*/ + xed3_operand_set_outreg(d, XED_REG_AX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_CX*/ + xed3_operand_set_outreg(d, XED_REG_CX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_DX*/ + xed3_operand_set_outreg(d, XED_REG_DX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_BX*/ + xed3_operand_set_outreg(d, XED_REG_BX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_SP*/ + xed3_operand_set_outreg(d, XED_REG_SP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_BP*/ + xed3_operand_set_outreg(d, XED_REG_BP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_SI*/ + xed3_operand_set_outreg(d, XED_REG_SI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_DI*/ + xed3_operand_set_outreg(d, XED_REG_DI); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_R8W*/ + xed3_operand_set_outreg(d, XED_REG_R8W); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_R9W*/ + xed3_operand_set_outreg(d, XED_REG_R9W); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_R10W*/ + xed3_operand_set_outreg(d, XED_REG_R10W); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_R11W*/ + xed3_operand_set_outreg(d, XED_REG_R11W); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_R12W*/ + xed3_operand_set_outreg(d, XED_REG_R12W); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_R13W*/ + xed3_operand_set_outreg(d, XED_REG_R13W); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_R14W*/ + xed3_operand_set_outreg(d, XED_REG_R14W); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_R15W*/ + xed3_operand_set_outreg(d, XED_REG_R15W); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR16_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_AX*/ + xed3_operand_set_outreg(d, XED_REG_AX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_R8W*/ + xed3_operand_set_outreg(d, XED_REG_R8W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_CX*/ + xed3_operand_set_outreg(d, XED_REG_CX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_R9W*/ + xed3_operand_set_outreg(d, XED_REG_R9W); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_DX*/ + xed3_operand_set_outreg(d, XED_REG_DX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_R10W*/ + xed3_operand_set_outreg(d, XED_REG_R10W); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_BX*/ + xed3_operand_set_outreg(d, XED_REG_BX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_R11W*/ + xed3_operand_set_outreg(d, XED_REG_R11W); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=XED_REG_SP*/ + xed3_operand_set_outreg(d, XED_REG_SP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_R12W*/ + xed3_operand_set_outreg(d, XED_REG_R12W); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=XED_REG_BP*/ + xed3_operand_set_outreg(d, XED_REG_BP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_R13W*/ + xed3_operand_set_outreg(d, XED_REG_R13W); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=XED_REG_SI*/ + xed3_operand_set_outreg(d, XED_REG_SI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_R14W*/ + xed3_operand_set_outreg(d, XED_REG_R14W); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=XED_REG_DI*/ + xed3_operand_set_outreg(d, XED_REG_DI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_R15W*/ + xed3_operand_set_outreg(d, XED_REG_R15W); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR16_SB(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_srm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 SRM=0x0 | OUTREG=XED_REG_AX*/ + xed3_operand_set_outreg(d, XED_REG_AX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 SRM=0x0 | OUTREG=XED_REG_R8W*/ + xed3_operand_set_outreg(d, XED_REG_R8W); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 SRM=0x1 | OUTREG=XED_REG_CX*/ + xed3_operand_set_outreg(d, XED_REG_CX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 SRM=0x1 | OUTREG=XED_REG_R9W*/ + xed3_operand_set_outreg(d, XED_REG_R9W); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 SRM=0x2 | OUTREG=XED_REG_DX*/ + xed3_operand_set_outreg(d, XED_REG_DX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 SRM=0x2 | OUTREG=XED_REG_R10W*/ + xed3_operand_set_outreg(d, XED_REG_R10W); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 SRM=0x3 | OUTREG=XED_REG_BX*/ + xed3_operand_set_outreg(d, XED_REG_BX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 SRM=0x3 | OUTREG=XED_REG_R11W*/ + xed3_operand_set_outreg(d, XED_REG_R11W); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 SRM=0x4 | OUTREG=XED_REG_SP*/ + xed3_operand_set_outreg(d, XED_REG_SP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 SRM=0x4 | OUTREG=XED_REG_R12W*/ + xed3_operand_set_outreg(d, XED_REG_R12W); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 SRM=0x5 | OUTREG=XED_REG_BP*/ + xed3_operand_set_outreg(d, XED_REG_BP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 SRM=0x5 | OUTREG=XED_REG_R13W*/ + xed3_operand_set_outreg(d, XED_REG_R13W); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 SRM=0x6 | OUTREG=XED_REG_SI*/ + xed3_operand_set_outreg(d, XED_REG_SI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 SRM=0x6 | OUTREG=XED_REG_R14W*/ + xed3_operand_set_outreg(d, XED_REG_R14W); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 SRM=0x7 | OUTREG=XED_REG_DI*/ + xed3_operand_set_outreg(d, XED_REG_DI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 SRM=0x7 | OUTREG=XED_REG_R15W*/ + xed3_operand_set_outreg(d, XED_REG_R15W); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_CR_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_CR0*/ + xed3_operand_set_outreg(d, XED_REG_CR0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_CR2*/ + xed3_operand_set_outreg(d, XED_REG_CR2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_CR3*/ + xed3_operand_set_outreg(d, XED_REG_CR3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_CR4*/ + xed3_operand_set_outreg(d, XED_REG_CR4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_CR8*/ + xed3_operand_set_outreg(d, XED_REG_CR8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_CR_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_CR0*/ + xed3_operand_set_outreg(d, XED_REG_CR0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_CR8*/ + xed3_operand_set_outreg(d, XED_REG_CR8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_CR2*/ + xed3_operand_set_outreg(d, XED_REG_CR2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_CR3*/ + xed3_operand_set_outreg(d, XED_REG_CR3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=XED_REG_CR4*/ + xed3_operand_set_outreg(d, XED_REG_CR4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_DR_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_DR0*/ + xed3_operand_set_outreg(d, XED_REG_DR0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_DR1*/ + xed3_operand_set_outreg(d, XED_REG_DR1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_DR2*/ + xed3_operand_set_outreg(d, XED_REG_DR2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_DR3*/ + xed3_operand_set_outreg(d, XED_REG_DR3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_DR4*/ + xed3_operand_set_outreg(d, XED_REG_DR4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_DR5*/ + xed3_operand_set_outreg(d, XED_REG_DR5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_DR6*/ + xed3_operand_set_outreg(d, XED_REG_DR6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_DR7*/ + xed3_operand_set_outreg(d, XED_REG_DR7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_X87(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0x0 | OUTREG=XED_REG_ST0*/ + xed3_operand_set_outreg(d, XED_REG_ST0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=0x1 | OUTREG=XED_REG_ST1*/ + xed3_operand_set_outreg(d, XED_REG_ST1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=0x2 | OUTREG=XED_REG_ST2*/ + xed3_operand_set_outreg(d, XED_REG_ST2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=0x3 | OUTREG=XED_REG_ST3*/ + xed3_operand_set_outreg(d, XED_REG_ST3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=0x4 | OUTREG=XED_REG_ST4*/ + xed3_operand_set_outreg(d, XED_REG_ST4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=0x5 | OUTREG=XED_REG_ST5*/ + xed3_operand_set_outreg(d, XED_REG_ST5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=0x6 | OUTREG=XED_REG_ST6*/ + xed3_operand_set_outreg(d, XED_REG_ST6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=0x7 | OUTREG=XED_REG_ST7*/ + xed3_operand_set_outreg(d, XED_REG_ST7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SEG(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0x0 | OUTREG=XED_REG_ES*/ + xed3_operand_set_outreg(d, XED_REG_ES); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=0x1 | OUTREG=XED_REG_CS*/ + xed3_operand_set_outreg(d, XED_REG_CS); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=0x2 | OUTREG=XED_REG_SS*/ + xed3_operand_set_outreg(d, XED_REG_SS); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=0x3 | OUTREG=XED_REG_DS*/ + xed3_operand_set_outreg(d, XED_REG_DS); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=0x4 | OUTREG=XED_REG_FS*/ + xed3_operand_set_outreg(d, XED_REG_FS); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=0x5 | OUTREG=XED_REG_GS*/ + xed3_operand_set_outreg(d, XED_REG_GS); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=0x6 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SEG_MOV(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0x0 | OUTREG=XED_REG_ES*/ + xed3_operand_set_outreg(d, XED_REG_ES); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=0x1 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=0x2 | OUTREG=XED_REG_SS*/ + xed3_operand_set_outreg(d, XED_REG_SS); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=0x3 | OUTREG=XED_REG_DS*/ + xed3_operand_set_outreg(d, XED_REG_DS); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=0x4 | OUTREG=XED_REG_FS*/ + xed3_operand_set_outreg(d, XED_REG_FS); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=0x5 | OUTREG=XED_REG_GS*/ + xed3_operand_set_outreg(d, XED_REG_GS); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=0x6 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=FINAL_DSEG_NOT64()*/ + xed3_capture_nt_FINAL_DSEG_NOT64(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=FINAL_DSEG_NOT64()*/ + xed3_capture_nt_FINAL_DSEG_NOT64(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=FINAL_DSEG_MODE64()*/ + xed3_capture_nt_FINAL_DSEG_MODE64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_DSEG_NOT64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_seg_ovd(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1 enc*/ + xed3_operand_set_outreg(d, XED_REG_DS); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_CS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_DS); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_FS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_GS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_DSEG_MODE64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_seg_ovd(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_FS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_GS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_DSEG1(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=FINAL_DSEG1_NOT64()*/ + xed3_capture_nt_FINAL_DSEG1_NOT64(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=FINAL_DSEG1_NOT64()*/ + xed3_capture_nt_FINAL_DSEG1_NOT64(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=FINAL_DSEG1_MODE64()*/ + xed3_capture_nt_FINAL_DSEG1_MODE64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_DSEG1_NOT64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_seg_ovd(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SEG_OVD=0 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1 enc*/ + xed3_operand_set_outreg(d, XED_REG_DS); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_CS); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_DS); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_FS); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_GS); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_DSEG1_MODE64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_seg_ovd(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1 enc*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_FS); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT1=0*/ + xed3_operand_set_outreg(d, XED_REG_GS); + xed3_operand_set_using_default_segment1(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_ESEG(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_ESEG1(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_SSEG1(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT1=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment1(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_SSEG(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=FINAL_SSEG_NOT64()*/ + xed3_capture_nt_FINAL_SSEG_NOT64(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=FINAL_SSEG_NOT64()*/ + xed3_capture_nt_FINAL_SSEG_NOT64(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=FINAL_SSEG_MODE64()*/ + xed3_capture_nt_FINAL_SSEG_MODE64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_SSEG_NOT64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_seg_ovd(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SEG_OVD=0 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1 enc*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SEG_OVD=1 | OUTREG=XED_REG_CS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_CS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SEG_OVD=2 | OUTREG=XED_REG_DS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_DS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SEG_OVD=3 | OUTREG=XED_REG_ES USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_ES); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_FS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_GS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> SEG_OVD=6 | OUTREG=XED_REG_SS USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_SS); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FINAL_SSEG_MODE64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_seg_ovd(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SEG_OVD=0 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1 enc*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SEG_OVD=1 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SEG_OVD=2 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SEG_OVD=3 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> SEG_OVD=4 | OUTREG=XED_REG_FS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_FS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> SEG_OVD=5 | OUTREG=XED_REG_GS USING_DEFAULT_SEGMENT0=0*/ + xed3_operand_set_outreg(d, XED_REG_GS); + xed3_operand_set_using_default_segment0(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> SEG_OVD=6 | OUTREG=XED_REG_INVALID USING_DEFAULT_SEGMENT0=1*/ + xed3_operand_set_outreg(d, XED_REG_INVALID); + xed3_operand_set_using_default_segment0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR8_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rex(d)) << ((3)); +key += (xed3_operand_get_rexr(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_AL*/ +case 8: /*(0, 1, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_AL*/ + xed3_operand_set_outreg(d, XED_REG_AL); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_CL*/ +case 9: /*(1, 1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_CL*/ + xed3_operand_set_outreg(d, XED_REG_CL); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_DL*/ +case 10: /*(2, 1, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_DL*/ + xed3_operand_set_outreg(d, XED_REG_DL); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_BL*/ +case 11: /*(3, 1, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_BL*/ + xed3_operand_set_outreg(d, XED_REG_BL); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> REXR=0 REG=0x4 REX=0 | OUTREG=XED_REG_AH*/ + xed3_operand_set_outreg(d, XED_REG_AH); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> REXR=0 REG=0x5 REX=0 | OUTREG=XED_REG_CH*/ + xed3_operand_set_outreg(d, XED_REG_CH); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> REXR=0 REG=0x6 REX=0 | OUTREG=XED_REG_DH*/ + xed3_operand_set_outreg(d, XED_REG_DH); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> REXR=0 REG=0x7 REX=0 | OUTREG=XED_REG_BH*/ + xed3_operand_set_outreg(d, XED_REG_BH); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> REXR=0 REG=0x4 REX=1 | OUTREG=XED_REG_SPL*/ + xed3_operand_set_outreg(d, XED_REG_SPL); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> REXR=0 REG=0x5 REX=1 | OUTREG=XED_REG_BPL*/ + xed3_operand_set_outreg(d, XED_REG_BPL); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> REXR=0 REG=0x6 REX=1 | OUTREG=XED_REG_SIL*/ + xed3_operand_set_outreg(d, XED_REG_SIL); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> REXR=0 REG=0x7 REX=1 | OUTREG=XED_REG_DIL*/ + xed3_operand_set_outreg(d, XED_REG_DIL); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_R8B*/ +case 24: /*(0, 1, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_R8B*/ + xed3_operand_set_outreg(d, XED_REG_R8B); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_R9B*/ +case 25: /*(1, 1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_R9B*/ + xed3_operand_set_outreg(d, XED_REG_R9B); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_R10B*/ +case 26: /*(2, 1, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_R10B*/ + xed3_operand_set_outreg(d, XED_REG_R10B); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_R11B*/ +case 27: /*(3, 1, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_R11B*/ + xed3_operand_set_outreg(d, XED_REG_R11B); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_R12B*/ +case 28: /*(4, 1, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_R12B*/ + xed3_operand_set_outreg(d, XED_REG_R12B); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_R13B*/ +case 29: /*(5, 1, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_R13B*/ + xed3_operand_set_outreg(d, XED_REG_R13B); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_R14B*/ +case 30: /*(6, 1, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_R14B*/ + xed3_operand_set_outreg(d, XED_REG_R14B); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_R15B*/ +case 31: /*(7, 1, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_R15B*/ + xed3_operand_set_outreg(d, XED_REG_R15B); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR8_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((1)); +key += (xed3_operand_get_rm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_AL*/ +case 1: /*(1, 0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_AL*/ + xed3_operand_set_outreg(d, XED_REG_AL); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_R8B*/ +case 3: /*(1, 1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_R8B*/ + xed3_operand_set_outreg(d, XED_REG_R8B); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_CL*/ +case 5: /*(1, 0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_CL*/ + xed3_operand_set_outreg(d, XED_REG_CL); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_R9B*/ +case 7: /*(1, 1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_R9B*/ + xed3_operand_set_outreg(d, XED_REG_R9B); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_DL*/ +case 9: /*(1, 0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_DL*/ + xed3_operand_set_outreg(d, XED_REG_DL); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_R10B*/ +case 11: /*(1, 1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_R10B*/ + xed3_operand_set_outreg(d, XED_REG_R10B); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_BL*/ +case 13: /*(1, 0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_BL*/ + xed3_operand_set_outreg(d, XED_REG_BL); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_R11B*/ +case 15: /*(1, 1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_R11B*/ + xed3_operand_set_outreg(d, XED_REG_R11B); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 4) -> REXB=0 RM=0x4 REX=0 | OUTREG=XED_REG_AH*/ + xed3_operand_set_outreg(d, XED_REG_AH); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 4) -> REXB=0 RM=0x4 REX=1 | OUTREG=XED_REG_SPL*/ + xed3_operand_set_outreg(d, XED_REG_SPL); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_R12B*/ +case 19: /*(1, 1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_R12B*/ + xed3_operand_set_outreg(d, XED_REG_R12B); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 0, 5) -> REXB=0 RM=0x5 REX=0 | OUTREG=XED_REG_CH*/ + xed3_operand_set_outreg(d, XED_REG_CH); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 0, 5) -> REXB=0 RM=0x5 REX=1 | OUTREG=XED_REG_BPL*/ + xed3_operand_set_outreg(d, XED_REG_BPL); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_R13B*/ +case 23: /*(1, 1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_R13B*/ + xed3_operand_set_outreg(d, XED_REG_R13B); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 6) -> REXB=0 RM=0x6 REX=0 | OUTREG=XED_REG_DH*/ + xed3_operand_set_outreg(d, XED_REG_DH); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 0, 6) -> REXB=0 RM=0x6 REX=1 | OUTREG=XED_REG_SIL*/ + xed3_operand_set_outreg(d, XED_REG_SIL); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_R14B*/ +case 27: /*(1, 1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_R14B*/ + xed3_operand_set_outreg(d, XED_REG_R14B); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 0, 7) -> REXB=0 RM=0x7 REX=0 | OUTREG=XED_REG_BH*/ + xed3_operand_set_outreg(d, XED_REG_BH); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 0, 7) -> REXB=0 RM=0x7 REX=1 | OUTREG=XED_REG_DIL*/ + xed3_operand_set_outreg(d, XED_REG_DIL); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_R15B*/ +case 31: /*(1, 1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_R15B*/ + xed3_operand_set_outreg(d, XED_REG_R15B); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_GPR8_SB(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((1)); +key += (xed3_operand_get_srm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXB=0 SRM=0x0 | OUTREG=XED_REG_AL*/ +case 1: /*(1, 0, 0) -> REXB=0 SRM=0x0 | OUTREG=XED_REG_AL*/ + xed3_operand_set_outreg(d, XED_REG_AL); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> REXB=1 SRM=0x0 | OUTREG=XED_REG_R8B*/ +case 3: /*(1, 1, 0) -> REXB=1 SRM=0x0 | OUTREG=XED_REG_R8B*/ + xed3_operand_set_outreg(d, XED_REG_R8B); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 0, 1) -> REXB=0 SRM=0x1 | OUTREG=XED_REG_CL*/ +case 5: /*(1, 0, 1) -> REXB=0 SRM=0x1 | OUTREG=XED_REG_CL*/ + xed3_operand_set_outreg(d, XED_REG_CL); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 1, 1) -> REXB=1 SRM=0x1 | OUTREG=XED_REG_R9B*/ +case 7: /*(1, 1, 1) -> REXB=1 SRM=0x1 | OUTREG=XED_REG_R9B*/ + xed3_operand_set_outreg(d, XED_REG_R9B); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 2) -> REXB=0 SRM=0x2 | OUTREG=XED_REG_DL*/ +case 9: /*(1, 0, 2) -> REXB=0 SRM=0x2 | OUTREG=XED_REG_DL*/ + xed3_operand_set_outreg(d, XED_REG_DL); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 1, 2) -> REXB=1 SRM=0x2 | OUTREG=XED_REG_R10B*/ +case 11: /*(1, 1, 2) -> REXB=1 SRM=0x2 | OUTREG=XED_REG_R10B*/ + xed3_operand_set_outreg(d, XED_REG_R10B); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 0, 3) -> REXB=0 SRM=0x3 | OUTREG=XED_REG_BL*/ +case 13: /*(1, 0, 3) -> REXB=0 SRM=0x3 | OUTREG=XED_REG_BL*/ + xed3_operand_set_outreg(d, XED_REG_BL); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 1, 3) -> REXB=1 SRM=0x3 | OUTREG=XED_REG_R11B*/ +case 15: /*(1, 1, 3) -> REXB=1 SRM=0x3 | OUTREG=XED_REG_R11B*/ + xed3_operand_set_outreg(d, XED_REG_R11B); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 4) -> REXB=0 SRM=0x4 REX=0 | OUTREG=XED_REG_AH*/ + xed3_operand_set_outreg(d, XED_REG_AH); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 4) -> REXB=0 SRM=0x4 REX=1 | OUTREG=XED_REG_SPL*/ + xed3_operand_set_outreg(d, XED_REG_SPL); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 4) -> REXB=1 SRM=0x4 | OUTREG=XED_REG_R12B*/ +case 19: /*(1, 1, 4) -> REXB=1 SRM=0x4 | OUTREG=XED_REG_R12B*/ + xed3_operand_set_outreg(d, XED_REG_R12B); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 0, 5) -> REXB=0 SRM=0x5 REX=0 | OUTREG=XED_REG_CH*/ + xed3_operand_set_outreg(d, XED_REG_CH); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 0, 5) -> REXB=0 SRM=0x5 REX=1 | OUTREG=XED_REG_BPL*/ + xed3_operand_set_outreg(d, XED_REG_BPL); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 1, 5) -> REXB=1 SRM=0x5 | OUTREG=XED_REG_R13B*/ +case 23: /*(1, 1, 5) -> REXB=1 SRM=0x5 | OUTREG=XED_REG_R13B*/ + xed3_operand_set_outreg(d, XED_REG_R13B); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 6) -> REXB=0 SRM=0x6 REX=0 | OUTREG=XED_REG_DH*/ + xed3_operand_set_outreg(d, XED_REG_DH); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 0, 6) -> REXB=0 SRM=0x6 REX=1 | OUTREG=XED_REG_SIL*/ + xed3_operand_set_outreg(d, XED_REG_SIL); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 1, 6) -> REXB=1 SRM=0x6 | OUTREG=XED_REG_R14B*/ +case 27: /*(1, 1, 6) -> REXB=1 SRM=0x6 | OUTREG=XED_REG_R14B*/ + xed3_operand_set_outreg(d, XED_REG_R14B); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 0, 7) -> REXB=0 SRM=0x7 REX=0 | OUTREG=XED_REG_BH*/ + xed3_operand_set_outreg(d, XED_REG_BH); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 0, 7) -> REXB=0 SRM=0x7 REX=1 | OUTREG=XED_REG_DIL*/ + xed3_operand_set_outreg(d, XED_REG_DIL); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 1, 7) -> REXB=1 SRM=0x7 | OUTREG=XED_REG_R15B*/ +case 31: /*(1, 1, 7) -> REXB=1 SRM=0x7 | OUTREG=XED_REG_R15B*/ + xed3_operand_set_outreg(d, XED_REG_R15B); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OSZ_NONTERM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> mode16 no66_prefix | EOSZ=1*/ +case 8: /*(0, 0, 1) -> mode16 no66_prefix | EOSZ=1*/ + xed3_operand_set_eosz(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> mode32 no66_prefix | EOSZ=2*/ +case 9: /*(1, 0, 1) -> mode32 no66_prefix | EOSZ=2*/ + xed3_operand_set_eosz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> mode64 no66_prefix REXW=0 | EOSZ=2*/ + xed3_operand_set_eosz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1, 0) -> mode16 66_prefix | EOSZ=2*/ +case 12: /*(0, 1, 1) -> mode16 66_prefix | EOSZ=2*/ + xed3_operand_set_eosz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 1, 0) -> mode32 66_prefix | EOSZ=1*/ +case 13: /*(1, 1, 1) -> mode32 66_prefix | EOSZ=1*/ + xed3_operand_set_eosz(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1, 0) -> mode64 66_prefix REXW=0 | EOSZ=1*/ + xed3_operand_set_eosz(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 0, 1) -> mode64 no66_prefix REXW=1 | EOSZ=3*/ + xed3_operand_set_eosz(d, 0x3); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(2, 1, 1) -> mode64 66_prefix REXW=1 | EOSZ=3*/ + xed3_operand_set_eosz(d, 0x3); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_DF64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> mode16 |*/ +case 8: /*(0, 0, 1) -> mode16 |*/ +case 4: /*(0, 1, 0) -> mode16 |*/ +case 12: /*(0, 1, 1) -> mode16 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> mode32 |*/ +case 9: /*(1, 0, 1) -> mode32 |*/ +case 5: /*(1, 1, 0) -> mode32 |*/ +case 13: /*(1, 1, 1) -> mode32 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> mode64 no66_prefix REXW=0 | EOSZ=3 df64*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_df64(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1, 0) -> mode64 66_prefix REXW=0 | EOSZ=1 df64*/ + xed3_operand_set_eosz(d, 0x1); + xed3_operand_set_df64(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 0, 1) -> mode64 no66_prefix REXW=1 | EOSZ=3 df64*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_df64(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(2, 1, 1) -> mode64 66_prefix REXW=1 | EOSZ=3 df64*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_df64(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_REFINING66(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> mode16 | EOSZ=1 no66_prefix*/ +case 4: /*(0, 1) -> mode16 | EOSZ=1 no66_prefix*/ + xed3_operand_set_eosz(d, 0x1); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> mode32 | EOSZ=2 no66_prefix*/ +case 5: /*(1, 1) -> mode32 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> mode64 REXW=0 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1) -> mode64 REXW=1 | EOSZ=3 no66_prefix*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_IGNORE66(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> mode16 | EOSZ=1 no66_prefix*/ +case 4: /*(0, 1) -> mode16 | EOSZ=1 no66_prefix*/ + xed3_operand_set_eosz(d, 0x1); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> mode32 | EOSZ=2 no66_prefix*/ +case 5: /*(1, 1) -> mode32 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> mode64 REXW=0 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1) -> mode64 REXW=1 | EOSZ=3 no66_prefix*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_IMMUNE66(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> mode16 | EOSZ=2 no66_prefix*/ +case 4: /*(0, 1) -> mode16 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> mode32 | EOSZ=2 no66_prefix*/ +case 5: /*(1, 1) -> mode32 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> mode64 REXW=0 | EOSZ=2 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1) -> mode64 REXW=1 | EOSZ=3 no66_prefix*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_CR_WIDTH(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | EOSZ=2 DF32=1 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_df32(d, 0x1); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | EOSZ=2 DF32=1 no66_prefix*/ + xed3_operand_set_eosz(d, 0x2); + xed3_operand_set_df32(d, 0x1); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | EOSZ=3 DF64=1 no66_prefix*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_df64(d, 0x1); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_IMMUNE66_LOOP64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | EOSZ=3 no66_prefix*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_IMMUNE_REXW(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> mode16 |*/ +case 8: /*(0, 0, 1) -> mode16 |*/ +case 4: /*(0, 1, 0) -> mode16 |*/ +case 12: /*(0, 1, 1) -> mode16 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> mode32 |*/ +case 9: /*(1, 0, 1) -> mode32 |*/ +case 5: /*(1, 1, 0) -> mode32 |*/ +case 13: /*(1, 1, 1) -> mode32 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> mode64 no66_prefix | EOSZ=2*/ +case 10: /*(2, 0, 1) -> mode64 no66_prefix | EOSZ=2*/ + xed3_operand_set_eosz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1, 0) -> mode64 66_prefix REXW=0 | EOSZ=1*/ + xed3_operand_set_eosz(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(2, 1, 1) -> mode64 66_prefix REXW=1 | EOSZ=2*/ + xed3_operand_set_eosz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FORCE64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 2: /*(2,) -> mode64 | EOSZ=3 no66_prefix*/ + xed3_operand_set_eosz(d, 0x3); + xed3_operand_set_osz(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: +/* otherwise_ok */ + break; +} +} +static XED_INLINE void xed3_capture_nt_ASZ_NONTERM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_asz(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> mode16 no67_prefix | eamode16*/ + xed3_operand_set_easz(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> mode16 67_prefix | eamode32*/ + xed3_operand_set_easz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> mode32 no67_prefix | eamode32*/ + xed3_operand_set_easz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> mode32 67_prefix | eamode16*/ + xed3_operand_set_easz(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> mode64 no67_prefix | eamode64*/ + xed3_operand_set_easz(d, 0x3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> mode64 67_prefix | eamode32*/ + xed3_operand_set_easz(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ONE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | IMM_WIDTH=8 UIMM0=1*/ + xed3_operand_set_imm_width(d, 0x8); + xed3_operand_set_uimm0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | IMM_WIDTH=8 UIMM0=1*/ + xed3_operand_set_imm_width(d, 0x8); + xed3_operand_set_uimm0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | IMM_WIDTH=8 UIMM0=1*/ + xed3_operand_set_imm_width(d, 0x8); + xed3_operand_set_uimm0(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UIMMv(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 UIMM0[iiiiiiiiiiiiiiii] | IMM_WIDTH=16*/ + xed3_operand_set_imm_width(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii] | IMM_WIDTH=32*/ + xed3_operand_set_imm_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii] | IMM_WIDTH=64*/ + xed3_operand_set_imm_width(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SIMMz(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 UIMM0[iiiiiiiiiiiiiiii] | IMM_WIDTH=16 IMM0SIGNED=1*/ + xed3_operand_set_imm_width(d, 0x10); + xed3_operand_set_imm0signed(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii] | IMM_WIDTH=32 IMM0SIGNED=1*/ + xed3_operand_set_imm_width(d, 0x20); + xed3_operand_set_imm0signed(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii] | IMM_WIDTH=32 IMM0SIGNED=1*/ + xed3_operand_set_imm_width(d, 0x20); + xed3_operand_set_imm0signed(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SIMM8(xed_decoded_inst_t* d) +{ + xed3_operand_set_imm_width(d, 0x8); + xed3_operand_set_imm0signed(d, 0x1); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_UIMM8(xed_decoded_inst_t* d) +{ + xed3_operand_set_imm_width(d, 0x8); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_UIMM8_1(xed_decoded_inst_t* d) +{ + xed3_operand_set_dummy(d, 0x0); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_UIMM16(xed_decoded_inst_t* d) +{ + xed3_operand_set_imm_width(d, 0x10); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_UIMM32(xed_decoded_inst_t* d) +{ + xed3_operand_set_imm_width(d, 0x20); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_BRDISP8(xed_decoded_inst_t* d) +{ + xed3_operand_set_brdisp_width(d, 0x8); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_BRDISP32(xed_decoded_inst_t* d) +{ + xed3_operand_set_brdisp_width(d, 0x20); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_BRDISPz(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 DISP[dddddddddddddddd] | BRDISP_WIDTH=16*/ + xed3_operand_set_brdisp_width(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 DISP[dddddddddddddddddddddddddddddddd] | BRDISP_WIDTH=32*/ + xed3_operand_set_brdisp_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 DISP[dddddddddddddddddddddddddddddddd] | BRDISP_WIDTH=32*/ + xed3_operand_set_brdisp_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MEMDISPv(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EASZ=1 DISP[aaaaaaaaaaaaaaaa] | DISP_WIDTH=16*/ + xed3_operand_set_disp_width(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EASZ=2 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa] | DISP_WIDTH=32*/ + xed3_operand_set_disp_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EASZ=3 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa] | DISP_WIDTH=64*/ + xed3_operand_set_disp_width(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MEMDISP32(xed_decoded_inst_t* d) +{ + xed3_operand_set_disp_width(d, 0x20); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_MEMDISP16(xed_decoded_inst_t* d) +{ + xed3_operand_set_disp_width(d, 0x10); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_MEMDISP8(xed_decoded_inst_t* d) +{ + xed3_operand_set_disp_width(d, 0x8); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_MEMDISP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_need_memdisp(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> NEED_MEMDISP=0 | DISP_WIDTH=0*/ + xed3_operand_set_disp_width(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8,) -> NEED_MEMDISP=8 DISP[aaaaaaaa] | DISP_WIDTH=8*/ + xed3_operand_set_disp_width(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(16,) -> NEED_MEMDISP=16 DISP[aaaaaaaaaaaaaaaa] | DISP_WIDTH=16*/ + xed3_operand_set_disp_width(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(32,) -> NEED_MEMDISP=32 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa] | DISP_WIDTH=32*/ + xed3_operand_set_disp_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MODRM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_easz(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 1: /*(1, 0) -> mode16 eamode16 MODRM16() MEMDISP() |*/ + xed3_capture_nt_MODRM16(d); + xed3_capture_nt_MEMDISP(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> mode16 eamode32 MODRM32() MEMDISP() |*/ + xed3_capture_nt_MODRM32(d); + xed3_capture_nt_MEMDISP(d); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 1) -> mode32 eamode16 MODRM16() MEMDISP() |*/ + xed3_capture_nt_MODRM16(d); + xed3_capture_nt_MEMDISP(d); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1) -> mode32 eamode32 MODRM32() MEMDISP() |*/ + xed3_capture_nt_MODRM32(d); + xed3_capture_nt_MEMDISP(d); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 2) -> mode64 eamode32 MODRM64alt32() MEMDISP() |*/ + xed3_capture_nt_MODRM64alt32(d); + xed3_capture_nt_MEMDISP(d); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 2) -> mode64 eamode64 MODRM64alt32() MEMDISP() |*/ + xed3_capture_nt_MODRM64alt32(d); + xed3_capture_nt_MEMDISP(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MODRM64alt32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((2)); +key += (xed3_operand_get_rm(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXB=0 MOD=0b00 RM=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArAX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXB=0 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=ArAX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArAX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> REXB=0 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=ArAX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArAX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1, 0) -> REXB=1 MOD=0b00 RM=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar8(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 1, 0) -> REXB=1 MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=Ar8() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar8(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1, 0) -> REXB=1 MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=Ar8() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar8(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 1) -> REXB=0 MOD=0b00 RM=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArCX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 0, 1) -> REXB=0 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=ArCX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArCX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 0, 1) -> REXB=0 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=ArCX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArCX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 1, 1) -> REXB=1 MOD=0b00 RM=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar9(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 1, 1) -> REXB=1 MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=Ar9() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar9(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(2, 1, 1) -> REXB=1 MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=Ar9() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar9(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 2) -> REXB=0 MOD=0b00 RM=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 2) -> REXB=0 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=ArDX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArDX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 2) -> REXB=0 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=ArDX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArDX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 1, 2) -> REXB=1 MOD=0b00 RM=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar10(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 1, 2) -> REXB=1 MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=Ar10() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar10(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(2, 1, 2) -> REXB=1 MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=Ar10() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar10(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 3) -> REXB=0 MOD=0b00 RM=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArBX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 0, 3) -> REXB=0 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=ArBX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArBX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 0, 3) -> REXB=0 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=ArBX() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArBX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 1, 3) -> REXB=1 MOD=0b00 RM=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar11(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 1, 3) -> REXB=1 MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=Ar11() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar11(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(2, 1, 3) -> REXB=1 MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=Ar11() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar11(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(0, 0, 4) -> REXB=0 MOD=0b00 RM=0b100 SIB() |*/ + xed3_capture_nt_SIB(d); +/*pacify the compiler */ +(void)d; + break; +case 33: /*(1, 0, 4) -> REXB=0 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8*/ + xed3_capture_nt_SIB(d); + xed3_operand_set_need_memdisp(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 34: /*(2, 0, 4) -> REXB=0 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32*/ + xed3_capture_nt_SIB(d); + xed3_operand_set_need_memdisp(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 36: /*(0, 1, 4) -> REXB=1 MOD=0b00 RM=0b100 SIB() |*/ + xed3_capture_nt_SIB(d); +/*pacify the compiler */ +(void)d; + break; +case 37: /*(1, 1, 4) -> REXB=1 MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8*/ + xed3_capture_nt_SIB(d); + xed3_operand_set_need_memdisp(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 38: /*(2, 1, 4) -> REXB=1 MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32*/ + xed3_capture_nt_SIB(d); + xed3_operand_set_need_memdisp(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 40: /*(0, 0, 5) -> REXB=0 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG() enc*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_rIPa(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 41: /*(1, 0, 5) -> REXB=0 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=ArBP() SEG0=FINAL_SSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArBP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 42: /*(2, 0, 5) -> REXB=0 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=ArBP() SEG0=FINAL_SSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArBP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 44: /*(0, 1, 5) -> REXB=1 MOD=0b00 RM=0b101 | NEED_MEMDISP=32 BASE0=rIPa() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_rIPa(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 45: /*(1, 1, 5) -> REXB=1 MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=Ar13() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar13(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 46: /*(2, 1, 5) -> REXB=1 MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=Ar13() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar13(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 48: /*(0, 0, 6) -> REXB=0 MOD=0b00 RM=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArSI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 49: /*(1, 0, 6) -> REXB=0 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=ArSI() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArSI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 50: /*(2, 0, 6) -> REXB=0 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=ArSI() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArSI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 52: /*(0, 1, 6) -> REXB=1 MOD=0b00 RM=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar14(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 53: /*(1, 1, 6) -> REXB=1 MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=Ar14() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar14(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 54: /*(2, 1, 6) -> REXB=1 MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=Ar14() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar14(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 56: /*(0, 0, 7) -> REXB=0 MOD=0b00 RM=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 57: /*(1, 0, 7) -> REXB=0 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=ArDI() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_ArDI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 58: /*(2, 0, 7) -> REXB=0 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=ArDI() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_ArDI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 60: /*(0, 1, 7) -> REXB=1 MOD=0b00 RM=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar15(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 61: /*(1, 1, 7) -> REXB=1 MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=Ar15() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_capture_nt_Ar15(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 62: /*(2, 1, 7) -> REXB=1 MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=Ar15() SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_Ar15(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MODRM32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> MOD=0b00 RM=0b000 | BASE0=XED_REG_EAX SEG0=FINAL_DSEG()*/ + xed3_operand_set_base0(d, XED_REG_EAX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_EAX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_EAX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> MOD=0b10 RM=0b000 | NEED_MEMDISP=32 BASE0=XED_REG_EAX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_EAX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1) -> MOD=0b00 RM=0b001 | BASE0=XED_REG_ECX SEG0=FINAL_DSEG()*/ + xed3_operand_set_base0(d, XED_REG_ECX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 1) -> MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_ECX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_ECX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1) -> MOD=0b10 RM=0b001 | NEED_MEMDISP=32 BASE0=XED_REG_ECX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_ECX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 2) -> MOD=0b00 RM=0b010 | BASE0=XED_REG_EDX SEG0=FINAL_DSEG()*/ + xed3_operand_set_base0(d, XED_REG_EDX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 2) -> MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_EDX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_EDX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 2) -> MOD=0b10 RM=0b010 | NEED_MEMDISP=32 BASE0=XED_REG_EDX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_EDX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 3) -> MOD=0b00 RM=0b011 | BASE0=XED_REG_EBX SEG0=FINAL_DSEG()*/ + xed3_operand_set_base0(d, XED_REG_EBX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 3) -> MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_EBX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_EBX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(2, 3) -> MOD=0b10 RM=0b011 | NEED_MEMDISP=32 BASE0=XED_REG_EBX SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_EBX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 4) -> MOD=0b00 RM=0b100 SIB() |*/ + xed3_capture_nt_SIB(d); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 4) -> MOD=0b01 RM=0b100 SIB() | NEED_MEMDISP=8*/ + xed3_capture_nt_SIB(d); + xed3_operand_set_need_memdisp(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 4) -> MOD=0b10 RM=0b100 SIB() | NEED_MEMDISP=32*/ + xed3_capture_nt_SIB(d); + xed3_operand_set_need_memdisp(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 5) -> MOD=0b00 RM=0b101 | NEED_MEMDISP=32 SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 5) -> MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_EBP SEG0=FINAL_SSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_EBP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(2, 5) -> MOD=0b10 RM=0b101 | NEED_MEMDISP=32 BASE0=XED_REG_EBP SEG0=FINAL_SSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_EBP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 6) -> MOD=0b00 RM=0b110 | BASE0=XED_REG_ESI SEG0=FINAL_DSEG()*/ + xed3_operand_set_base0(d, XED_REG_ESI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 6) -> MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_ESI SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_ESI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 6) -> MOD=0b10 RM=0b110 | NEED_MEMDISP=32 BASE0=XED_REG_ESI SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_ESI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 7) -> MOD=0b00 RM=0b111 | BASE0=XED_REG_EDI SEG0=FINAL_DSEG()*/ + xed3_operand_set_base0(d, XED_REG_EDI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 7) -> MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_EDI SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_EDI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(2, 7) -> MOD=0b10 RM=0b111 | NEED_MEMDISP=32 BASE0=XED_REG_EDI SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_EDI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MODRM16(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> MOD=0b00 RM=0b000 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1*/ + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_SI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> MOD=0b01 RM=0b000 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_SI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> MOD=0b10 RM=0b000 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_SI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_SI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1) -> MOD=0b00 RM=0b001 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1*/ + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_DI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 1) -> MOD=0b01 RM=0b001 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_DI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(2, 1) -> MOD=0b10 RM=0b001 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_DI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_DI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 2) -> MOD=0b00 RM=0b010 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1*/ + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_SI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 2) -> MOD=0b01 RM=0b010 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_SI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 2) -> MOD=0b10 RM=0b010 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_SI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_SI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 3) -> MOD=0b00 RM=0b011 | BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1*/ + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_DI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 3) -> MOD=0b01 RM=0b011 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_DI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(2, 3) -> MOD=0b10 RM=0b011 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_DI SCALE=1*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_DI); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 4) -> MOD=0b00 RM=0b100 | BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_base0(d, XED_REG_SI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 4) -> MOD=0b01 RM=0b100 | NEED_MEMDISP=8 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_SI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 4) -> MOD=0b10 RM=0b100 | NEED_MEMDISP=16 BASE0=XED_REG_SI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_SI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 5) -> MOD=0b00 RM=0b101 | BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_base0(d, XED_REG_DI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 5) -> MOD=0b01 RM=0b101 | NEED_MEMDISP=8 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_DI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(2, 5) -> MOD=0b10 RM=0b101 | NEED_MEMDISP=16 BASE0=XED_REG_DI SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_DI); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 6) -> MOD=0b00 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 6) -> MOD=0b01 RM=0b110 | NEED_MEMDISP=8 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 6) -> MOD=0b10 RM=0b110 | NEED_MEMDISP=16 BASE0=XED_REG_BP SEG0=FINAL_SSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_BP); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 7) -> MOD=0b00 RM=0b111 | BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 7) -> MOD=0b01 RM=0b111 | NEED_MEMDISP=8 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x8); + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(2, 7) -> MOD=0b10 RM=0b111 | NEED_MEMDISP=16 BASE0=XED_REG_BX SEG0=FINAL_DSEG() INDEX=XED_REG_INVALID*/ + xed3_operand_set_need_memdisp(d, 0x10); + xed3_operand_set_base0(d, XED_REG_BX); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_index(d, XED_REG_INVALID); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SIB(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +key += (xed3_operand_get_sibscale(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArAX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar8(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArCX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar9(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar10(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar11(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1 enc*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_operand_set_index(d, XED_REG_INVALID); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar12(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBP(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar13(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArSI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar14(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7, 0) -> REXX=0 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7, 0) -> REXX=1 SIBSCALE[0b00] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar15(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArAX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar8(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArCX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar9(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 2, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 2, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar10(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 3, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 3, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar11(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 4, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_operand_set_index(d, XED_REG_INVALID); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 4, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar12(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 5, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBP(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 5, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar13(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 6, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArSI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 6, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar14(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 7, 1) -> REXX=0 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 7, 1) -> REXX=1 SIBSCALE[0b01] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=2*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar15(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(0, 0, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArAX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 33: /*(1, 0, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar8(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 34: /*(0, 1, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArCX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 35: /*(1, 1, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar9(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 36: /*(0, 2, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 37: /*(1, 2, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar10(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 38: /*(0, 3, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 39: /*(1, 3, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar11(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 40: /*(0, 4, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_operand_set_index(d, XED_REG_INVALID); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 41: /*(1, 4, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar12(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 42: /*(0, 5, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBP(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 43: /*(1, 5, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar13(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 44: /*(0, 6, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArSI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 45: /*(1, 6, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar14(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 46: /*(0, 7, 2) -> REXX=0 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 47: /*(1, 7, 2) -> REXX=1 SIBSCALE[0b10] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=4*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar15(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 48: /*(0, 0, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=ArAX() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArAX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 49: /*(1, 0, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b000] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar8() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar8(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 50: /*(0, 1, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=ArCX() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArCX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 51: /*(1, 1, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b001] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar9() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar9(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 52: /*(0, 2, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDX() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 53: /*(1, 2, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b010] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar10() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar10(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 54: /*(0, 3, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBX() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBX(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 55: /*(1, 3, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b011] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar11() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar11(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 56: /*(0, 4, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=XED_REG_INVALID SCALE=1*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_operand_set_index(d, XED_REG_INVALID); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 57: /*(1, 4, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b100] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar12() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar12(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 58: /*(0, 5, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=ArBP() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArBP(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 59: /*(1, 5, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b101] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar13() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar13(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 60: /*(0, 6, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=ArSI() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArSI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 61: /*(1, 6, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b110] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar14() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar14(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 62: /*(0, 7, 3) -> REXX=0 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=ArDI() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_ArDI(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 63: /*(1, 7, 3) -> REXX=1 SIBSCALE[0b11] SIBINDEX[0b111] SIBBASE[bbb] SIB_BASE0() | INDEX=Ar15() SCALE=8*/ + xed3_capture_nt_SIB_BASE0(d); + xed3_capture_nt_Ar15(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SIB_BASE0(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((2)); +key += (xed3_operand_get_sibbase(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 1: /*(1, 0, 0) -> REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 2: /*(2, 0, 0) -> REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 3: /*(3, 0, 0) -> REXB=0 SIBBASE=0b000 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArAX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1, 0) -> REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 5: /*(1, 1, 0) -> REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 6: /*(2, 1, 0) -> REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 7: /*(3, 1, 0) -> REXB=1 SIBBASE=0b000 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar8(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 1) -> REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 9: /*(1, 0, 1) -> REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 10: /*(2, 0, 1) -> REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 11: /*(3, 0, 1) -> REXB=0 SIBBASE=0b001 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArCX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 1, 1) -> REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 13: /*(1, 1, 1) -> REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 14: /*(2, 1, 1) -> REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 15: /*(3, 1, 1) -> REXB=1 SIBBASE=0b001 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar9(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 2) -> REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 17: /*(1, 0, 2) -> REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 18: /*(2, 0, 2) -> REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 19: /*(3, 0, 2) -> REXB=0 SIBBASE=0b010 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 1, 2) -> REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 21: /*(1, 1, 2) -> REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 22: /*(2, 1, 2) -> REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 23: /*(3, 1, 2) -> REXB=1 SIBBASE=0b010 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar10(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 3) -> REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 25: /*(1, 0, 3) -> REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 26: /*(2, 0, 3) -> REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 27: /*(3, 0, 3) -> REXB=0 SIBBASE=0b011 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArBX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 1, 3) -> REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 29: /*(1, 1, 3) -> REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 30: /*(2, 1, 3) -> REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 31: /*(3, 1, 3) -> REXB=1 SIBBASE=0b011 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar11(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(0, 0, 4) -> REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 33: /*(1, 0, 4) -> REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 34: /*(2, 0, 4) -> REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 35: /*(3, 0, 4) -> REXB=0 SIBBASE=0b100 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ + xed3_capture_nt_ArSP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 36: /*(0, 1, 4) -> REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 37: /*(1, 1, 4) -> REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 38: /*(2, 1, 4) -> REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 39: /*(3, 1, 4) -> REXB=1 SIBBASE=0b100 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar12(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 40: /*(0, 0, 5) -> REXB=0 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG() enc*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 41: /*(1, 0, 5) -> REXB=0 SIBBASE=0b101 MOD=0b01 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=8*/ + xed3_capture_nt_ArBP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_disp_width(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 42: /*(2, 0, 5) -> REXB=0 SIBBASE=0b101 MOD=0b10 | BASE0=ArBP() SEG0=FINAL_SSEG() DISP_WIDTH=32*/ + xed3_capture_nt_ArBP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_disp_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 44: /*(0, 1, 5) -> REXB=1 SIBBASE=0b101 MOD=0b00 | NEED_MEMDISP=32 BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()*/ + xed3_operand_set_need_memdisp(d, 0x20); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 45: /*(1, 1, 5) -> REXB=1 SIBBASE=0b101 MOD=0b01 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=8*/ + xed3_capture_nt_Ar13(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_disp_width(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 46: /*(2, 1, 5) -> REXB=1 SIBBASE=0b101 MOD=0b10 | BASE0=Ar13() SEG0=FINAL_DSEG() DISP_WIDTH=32*/ + xed3_capture_nt_Ar13(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); + xed3_operand_set_disp_width(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 48: /*(0, 0, 6) -> REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 49: /*(1, 0, 6) -> REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 50: /*(2, 0, 6) -> REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 51: /*(3, 0, 6) -> REXB=0 SIBBASE=0b110 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArSI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 52: /*(0, 1, 6) -> REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 53: /*(1, 1, 6) -> REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 54: /*(2, 1, 6) -> REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 55: /*(3, 1, 6) -> REXB=1 SIBBASE=0b110 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar14(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 56: /*(0, 0, 7) -> REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 57: /*(1, 0, 7) -> REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 58: /*(2, 0, 7) -> REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 59: /*(3, 0, 7) -> REXB=0 SIBBASE=0b111 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 60: /*(0, 1, 7) -> REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 61: /*(1, 1, 7) -> REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 62: /*(2, 1, 7) -> REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 63: /*(3, 1, 7) -> REXB=1 SIBBASE=0b111 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar15(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OVERRIDE_SEG0(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 |*/ +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_OVERRIDE_SEG1(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 |*/ +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_R_32()*/ + xed3_capture_nt_XMM_R_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_R_32()*/ + xed3_capture_nt_XMM_R_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_R_64()*/ + xed3_capture_nt_XMM_R_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_R_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0x0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=0x1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=0x2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=0x3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=0x4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=0x5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=0x6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=0x7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_R_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_B_32()*/ + xed3_capture_nt_XMM_B_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_B_32()*/ + xed3_capture_nt_XMM_B_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_B_64()*/ + xed3_capture_nt_XMM_B_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_B_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0x0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=0x1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=0x2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=0x3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=0x4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=0x5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=0x6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=0x7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_B_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_BND_R_CHECK(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 |*/ +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 |*/ +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 |*/ +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_BND_B_CHECK(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 |*/ +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 |*/ +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 |*/ +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 |*/ +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_BND_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=XED_REG_BND0*/ + xed3_operand_set_outreg(d, XED_REG_BND0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=XED_REG_BND1*/ + xed3_operand_set_outreg(d, XED_REG_BND1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=XED_REG_BND2*/ + xed3_operand_set_outreg(d, XED_REG_BND2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=XED_REG_BND3*/ + xed3_operand_set_outreg(d, XED_REG_BND3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_BND_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=XED_REG_BND0*/ + xed3_operand_set_outreg(d, XED_REG_BND0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=XED_REG_BND1*/ + xed3_operand_set_outreg(d, XED_REG_BND1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=XED_REG_BND2*/ + xed3_operand_set_outreg(d, XED_REG_BND2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=XED_REG_BND3*/ + xed3_operand_set_outreg(d, XED_REG_BND3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=XED_REG_ERROR enc*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_A_GPR_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0x0 | OUTREG=ArAX()*/ + xed3_capture_nt_ArAX(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=0x1 | OUTREG=ArCX()*/ + xed3_capture_nt_ArCX(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=0x2 | OUTREG=ArDX()*/ + xed3_capture_nt_ArDX(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=0x3 | OUTREG=ArBX()*/ + xed3_capture_nt_ArBX(d); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=0x4 | OUTREG=ArSP()*/ + xed3_capture_nt_ArSP(d); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=0x5 | OUTREG=ArBP()*/ + xed3_capture_nt_ArBP(d); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=0x6 | OUTREG=ArSI()*/ + xed3_capture_nt_ArSI(d); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=0x7 | OUTREG=ArDI()*/ + xed3_capture_nt_ArDI(d); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0x0 | OUTREG=Ar8()*/ + xed3_capture_nt_Ar8(d); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=0x1 | OUTREG=Ar9()*/ + xed3_capture_nt_Ar9(d); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=0x2 | OUTREG=Ar10()*/ + xed3_capture_nt_Ar10(d); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=0x3 | OUTREG=Ar11()*/ + xed3_capture_nt_Ar11(d); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=0x4 | OUTREG=Ar12()*/ + xed3_capture_nt_Ar12(d); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=0x5 | OUTREG=Ar13()*/ + xed3_capture_nt_Ar13(d); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=0x6 | OUTREG=Ar14()*/ + xed3_capture_nt_Ar14(d); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=0x7 | OUTREG=Ar15()*/ + xed3_capture_nt_Ar15(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_A_GPR_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0x0 | OUTREG=ArAX()*/ + xed3_capture_nt_ArAX(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0x0 | OUTREG=Ar8()*/ + xed3_capture_nt_Ar8(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=0x1 | OUTREG=ArCX()*/ + xed3_capture_nt_ArCX(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=0x1 | OUTREG=Ar9()*/ + xed3_capture_nt_Ar9(d); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=0x2 | OUTREG=ArDX()*/ + xed3_capture_nt_ArDX(d); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=0x2 | OUTREG=Ar10()*/ + xed3_capture_nt_Ar10(d); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=0x3 | OUTREG=ArBX()*/ + xed3_capture_nt_ArBX(d); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=0x3 | OUTREG=Ar11()*/ + xed3_capture_nt_Ar11(d); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=0x4 | OUTREG=ArSP()*/ + xed3_capture_nt_ArSP(d); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=0x4 | OUTREG=Ar12()*/ + xed3_capture_nt_Ar12(d); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=0x5 | OUTREG=ArBP()*/ + xed3_capture_nt_ArBP(d); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=0x5 | OUTREG=Ar13()*/ + xed3_capture_nt_Ar13(d); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=0x6 | OUTREG=ArSI()*/ + xed3_capture_nt_ArSI(d); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=0x6 | OUTREG=Ar14()*/ + xed3_capture_nt_Ar14(d); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=0x7 | OUTREG=ArDI()*/ + xed3_capture_nt_ArDI(d); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=0x7 | OUTREG=Ar15()*/ + xed3_capture_nt_Ar15(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_SE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_SE32()*/ + xed3_capture_nt_XMM_SE32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_SE32()*/ + xed3_capture_nt_XMM_SE32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_SE64()*/ + xed3_capture_nt_XMM_SE64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_SE64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_esrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> ESRC=0x0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> ESRC=0x1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> ESRC=0x2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> ESRC=0x3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> ESRC=0x4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> ESRC=0x5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> ESRC=0x6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> ESRC=0x7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8,) -> ESRC=0x8 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(9,) -> ESRC=0x9 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(10,) -> ESRC=0xA | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(11,) -> ESRC=0xB | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(12,) -> ESRC=0xC | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(13,) -> ESRC=0xD | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(14,) -> ESRC=0xE | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(15,) -> ESRC=0xF | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_SE32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_esrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> ESRC=0 | OUTREG=XED_REG_XMM0 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> ESRC=1 | OUTREG=XED_REG_XMM1 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> ESRC=2 | OUTREG=XED_REG_XMM2 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> ESRC=3 | OUTREG=XED_REG_XMM3 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> ESRC=4 | OUTREG=XED_REG_XMM4 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> ESRC=5 | OUTREG=XED_REG_XMM5 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> ESRC=6 | OUTREG=XED_REG_XMM6 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> ESRC=7 | OUTREG=XED_REG_XMM7 enc*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8,) -> ESRC=0x8 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(9,) -> ESRC=0x9 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(10,) -> ESRC=0xA | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(11,) -> ESRC=0xB | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(12,) -> ESRC=0xC | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(13,) -> ESRC=0xD | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(14,) -> ESRC=0xE | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(15,) -> ESRC=0xF | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_SE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_SE32()*/ + xed3_capture_nt_YMM_SE32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_SE32()*/ + xed3_capture_nt_YMM_SE32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_SE64()*/ + xed3_capture_nt_YMM_SE64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_SE64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_esrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> ESRC=0x0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> ESRC=0x1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> ESRC=0x2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> ESRC=0x3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> ESRC=0x4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> ESRC=0x5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> ESRC=0x6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> ESRC=0x7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8,) -> ESRC=0x8 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(9,) -> ESRC=0x9 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(10,) -> ESRC=0xA | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(11,) -> ESRC=0xB | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(12,) -> ESRC=0xC | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(13,) -> ESRC=0xD | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(14,) -> ESRC=0xE | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(15,) -> ESRC=0xF | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_SE32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_esrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> ESRC=0 | OUTREG=XED_REG_YMM0 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> ESRC=1 | OUTREG=XED_REG_YMM1 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> ESRC=2 | OUTREG=XED_REG_YMM2 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> ESRC=3 | OUTREG=XED_REG_YMM3 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> ESRC=4 | OUTREG=XED_REG_YMM4 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> ESRC=5 | OUTREG=XED_REG_YMM5 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> ESRC=6 | OUTREG=XED_REG_YMM6 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> ESRC=7 | OUTREG=XED_REG_YMM7 enc*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8,) -> ESRC=0x8 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(9,) -> ESRC=0x9 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(10,) -> ESRC=0xA | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(11,) -> ESRC=0xB | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(12,) -> ESRC=0xC | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(13,) -> ESRC=0xD | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(14,) -> ESRC=0xE | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(15,) -> ESRC=0xF | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_N_32():*/ + xed3_capture_nt_XMM_N_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_N_32():*/ + xed3_capture_nt_XMM_N_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_N_64():*/ + xed3_capture_nt_XMM_N_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_N_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=1 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=2 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=3 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=4 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=5 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=6 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=7 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_N_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_N_32():*/ + xed3_capture_nt_YMM_N_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_N_32():*/ + xed3_capture_nt_YMM_N_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_N_64():*/ + xed3_capture_nt_YMM_N_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_N_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=1 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=2 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=3 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=4 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=5 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=6 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=7 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_N_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_R_32():*/ + xed3_capture_nt_YMM_R_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_R_32():*/ + xed3_capture_nt_YMM_R_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_R_64():*/ + xed3_capture_nt_YMM_R_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_R_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_R_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=1 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=2 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=3 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=4 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=5 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=6 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=7 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_B_32():*/ + xed3_capture_nt_YMM_B_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_B_32():*/ + xed3_capture_nt_YMM_B_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_B_64():*/ + xed3_capture_nt_YMM_B_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_B_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_B_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=1 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=2 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=3 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=4 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=5 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=6 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=7 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SE_IMM8(xed_decoded_inst_t* d) +{ + xed3_operand_set_imm_width(d, 0x8); +/*pacify the compiler */ +(void)d; +} +static XED_INLINE void xed3_capture_nt_VMODRM_YMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MOD=0b00 VSIB_YMM() |*/ + xed3_capture_nt_VSIB_YMM(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MOD=0b01 VSIB_YMM() MEMDISP8() |*/ + xed3_capture_nt_VSIB_YMM(d); + xed3_capture_nt_MEMDISP8(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MOD=0b10 VSIB_YMM() MEMDISP32() |*/ + xed3_capture_nt_VSIB_YMM(d); + xed3_capture_nt_MEMDISP32(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VMODRM_XMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MOD=0b00 VSIB_XMM() |*/ + xed3_capture_nt_VSIB_XMM(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MOD=0b01 VSIB_XMM() MEMDISP8() |*/ + xed3_capture_nt_VSIB_XMM(d); + xed3_capture_nt_MEMDISP8(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MOD=0b10 VSIB_XMM() MEMDISP32() |*/ + xed3_capture_nt_VSIB_XMM(d); + xed3_capture_nt_MEMDISP32(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VSIB_YMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_sibscale(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=1*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=2*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=4*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_YMM() SCALE=8*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VSIB_XMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_sibscale(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=1*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=2*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=4*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] VSIB_BASE() | INDEX=VSIB_INDEX_XMM() SCALE=8*/ + xed3_capture_nt_VSIB_BASE(d); + xed3_capture_nt_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VSIB_INDEX_YMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VSIB_INDEX_XMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VSIB_BASE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((2)); +key += (xed3_operand_get_sibbase(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 1: /*(1, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 2: /*(2, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 3: /*(3, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArAX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 5: /*(1, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 6: /*(2, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 7: /*(3, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar8(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 9: /*(1, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 10: /*(2, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 11: /*(3, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArCX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 13: /*(1, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 14: /*(2, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 15: /*(3, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar9(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 17: /*(1, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 18: /*(2, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 19: /*(3, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 21: /*(1, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 22: /*(2, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 23: /*(3, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar10(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 25: /*(1, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 26: /*(2, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 27: /*(3, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArBX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 29: /*(1, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 30: /*(2, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 31: /*(3, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar11(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(0, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 33: /*(1, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 34: /*(2, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 35: /*(3, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ + xed3_capture_nt_ArSP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 36: /*(0, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 37: /*(1, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 38: /*(2, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 39: /*(3, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar12(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 40: /*(0, 0, 5) -> REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()*/ + xed3_capture_nt_MEMDISP32(d); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 41: /*(1, 0, 5) -> REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()*/ +case 42: /*(2, 0, 5) -> REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()*/ +case 43: /*(3, 0, 5) -> REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()*/ + xed3_capture_nt_ArBP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 44: /*(0, 1, 5) -> REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()*/ + xed3_capture_nt_MEMDISP32(d); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 45: /*(1, 1, 5) -> REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()*/ +case 46: /*(2, 1, 5) -> REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()*/ +case 47: /*(3, 1, 5) -> REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar13(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 48: /*(0, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 49: /*(1, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 50: /*(2, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 51: /*(3, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArSI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 52: /*(0, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 53: /*(1, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 54: /*(2, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 55: /*(3, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar14(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 56: /*(0, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 57: /*(1, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 58: /*(2, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 59: /*(3, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 60: /*(0, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 61: /*(1, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 62: /*(2, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 63: /*(3, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar15(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPRy_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=VGPR32_R()*/ + xed3_capture_nt_VGPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=VGPR32_R()*/ + xed3_capture_nt_VGPR32_R(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=VGPR64_R()*/ + xed3_capture_nt_VGPR64_R(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPRy_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=VGPR32_B()*/ + xed3_capture_nt_VGPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=VGPR32_B()*/ + xed3_capture_nt_VGPR32_B(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=VGPR64_B()*/ + xed3_capture_nt_VGPR64_B(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPRy_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_eosz(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 1: /*(1,) -> EOSZ=1 | OUTREG=VGPR32_N()*/ + xed3_capture_nt_VGPR32_N(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> EOSZ=2 | OUTREG=VGPR32_N()*/ + xed3_capture_nt_VGPR32_N(d); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> EOSZ=3 | OUTREG=VGPR64_N()*/ + xed3_capture_nt_VGPR64_N(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=VGPR32_N_32()*/ + xed3_capture_nt_VGPR32_N_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=VGPR32_N_32()*/ + xed3_capture_nt_VGPR32_N_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=VGPR32_N_64()*/ + xed3_capture_nt_VGPR32_N_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=VGPR32_B_32()*/ + xed3_capture_nt_VGPR32_B_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=VGPR32_B_32()*/ + xed3_capture_nt_VGPR32_B_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=VGPR32_B_64()*/ + xed3_capture_nt_VGPR32_B_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=VGPR32_R_32()*/ + xed3_capture_nt_VGPR32_R_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=VGPR32_R_32()*/ + xed3_capture_nt_VGPR32_R_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=VGPR32_R_64()*/ + xed3_capture_nt_VGPR32_R_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_N_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=1 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=2 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=3 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=4 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=5 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=6 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=7 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_N_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR64_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_R_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_R_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=1 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=3 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=4 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=5 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=6 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=7 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR64_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=1 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=2 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=4 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=5 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=6 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=7 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1) -> REXR=1 REG=0 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> REXR=1 REG=1 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> REXR=1 REG=2 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> REXR=1 REG=3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> REXR=1 REG=4 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> REXR=1 REG=5 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> REXR=1 REG=6 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> REXR=1 REG=7 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_B_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR32_B_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0 | OUTREG=XED_REG_EAX*/ + xed3_operand_set_outreg(d, XED_REG_EAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0 | OUTREG=XED_REG_R8D*/ + xed3_operand_set_outreg(d, XED_REG_R8D); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=1 | OUTREG=XED_REG_ECX*/ + xed3_operand_set_outreg(d, XED_REG_ECX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=1 | OUTREG=XED_REG_R9D*/ + xed3_operand_set_outreg(d, XED_REG_R9D); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=2 | OUTREG=XED_REG_EDX*/ + xed3_operand_set_outreg(d, XED_REG_EDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=2 | OUTREG=XED_REG_R10D*/ + xed3_operand_set_outreg(d, XED_REG_R10D); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=3 | OUTREG=XED_REG_EBX*/ + xed3_operand_set_outreg(d, XED_REG_EBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=3 | OUTREG=XED_REG_R11D*/ + xed3_operand_set_outreg(d, XED_REG_R11D); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=4 | OUTREG=XED_REG_ESP*/ + xed3_operand_set_outreg(d, XED_REG_ESP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=4 | OUTREG=XED_REG_R12D*/ + xed3_operand_set_outreg(d, XED_REG_R12D); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=5 | OUTREG=XED_REG_EBP*/ + xed3_operand_set_outreg(d, XED_REG_EBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=5 | OUTREG=XED_REG_R13D*/ + xed3_operand_set_outreg(d, XED_REG_R13D); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=6 | OUTREG=XED_REG_ESI*/ + xed3_operand_set_outreg(d, XED_REG_ESI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=6 | OUTREG=XED_REG_R14D*/ + xed3_operand_set_outreg(d, XED_REG_R14D); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=7 | OUTREG=XED_REG_EDI*/ + xed3_operand_set_outreg(d, XED_REG_EDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=7 | OUTREG=XED_REG_R15D*/ + xed3_operand_set_outreg(d, XED_REG_R15D); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_VGPR64_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0 | OUTREG=XED_REG_RAX*/ + xed3_operand_set_outreg(d, XED_REG_RAX); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXB=1 RM=0 | OUTREG=XED_REG_R8*/ + xed3_operand_set_outreg(d, XED_REG_R8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=1 | OUTREG=XED_REG_RCX*/ + xed3_operand_set_outreg(d, XED_REG_RCX); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1) -> REXB=1 RM=1 | OUTREG=XED_REG_R9*/ + xed3_operand_set_outreg(d, XED_REG_R9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=2 | OUTREG=XED_REG_RDX*/ + xed3_operand_set_outreg(d, XED_REG_RDX); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2) -> REXB=1 RM=2 | OUTREG=XED_REG_R10*/ + xed3_operand_set_outreg(d, XED_REG_R10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=3 | OUTREG=XED_REG_RBX*/ + xed3_operand_set_outreg(d, XED_REG_RBX); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3) -> REXB=1 RM=3 | OUTREG=XED_REG_R11*/ + xed3_operand_set_outreg(d, XED_REG_R11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=4 | OUTREG=XED_REG_RSP*/ + xed3_operand_set_outreg(d, XED_REG_RSP); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4) -> REXB=1 RM=4 | OUTREG=XED_REG_R12*/ + xed3_operand_set_outreg(d, XED_REG_R12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=5 | OUTREG=XED_REG_RBP*/ + xed3_operand_set_outreg(d, XED_REG_RBP); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5) -> REXB=1 RM=5 | OUTREG=XED_REG_R13*/ + xed3_operand_set_outreg(d, XED_REG_R13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=6 | OUTREG=XED_REG_RSI*/ + xed3_operand_set_outreg(d, XED_REG_RSI); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6) -> REXB=1 RM=6 | OUTREG=XED_REG_R14*/ + xed3_operand_set_outreg(d, XED_REG_R14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=7 | OUTREG=XED_REG_RDI*/ + xed3_operand_set_outreg(d, XED_REG_RDI); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7) -> REXB=1 RM=7 | OUTREG=XED_REG_R15*/ + xed3_operand_set_outreg(d, XED_REG_R15); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_4X(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_AVX512_ROUND(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_llrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> LLRC=0b00 | ROUNDC=1 SAE=1*/ + xed3_operand_set_roundc(d, 0x1); + xed3_operand_set_sae(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> LLRC=0b01 | ROUNDC=2 SAE=1*/ + xed3_operand_set_roundc(d, 0x2); + xed3_operand_set_sae(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> LLRC=0b10 | ROUNDC=3 SAE=1*/ + xed3_operand_set_roundc(d, 0x3); + xed3_operand_set_sae(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> LLRC=0b11 | ROUNDC=4 SAE=1*/ + xed3_operand_set_roundc(d, 0x4); + xed3_operand_set_sae(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_SAE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> BCRC=0 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1: /*(1,) -> BCRC=1 | SAE=1*/ + xed3_operand_set_sae(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_128_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=128*/ + xed3_operand_set_element_size(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_64_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=64*/ + xed3_operand_set_element_size(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_32_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=32*/ + xed3_operand_set_element_size(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_16_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=16*/ + xed3_operand_set_element_size(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_8_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=8*/ + xed3_operand_set_element_size(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_4_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=4*/ + xed3_operand_set_element_size(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_2_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=2*/ + xed3_operand_set_element_size(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ESIZE_1_BITS(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rex(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REX=0 | ELEMENT_SIZE=1*/ + xed3_operand_set_element_size(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_MOVDDUP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_element_size(d)) << ((0)); +key += (xed3_operand_get_vl(d)) << ((9)); +/* now switch code..*/ +switch(key) { +case 64: /*(64, 0) -> ELEMENT_SIZE=64 VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 576: /*(64, 1) -> ELEMENT_SIZE=64 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(64, 2) -> ELEMENT_SIZE=64 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_FULLMEM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_element_size(d)) << ((0)); +key += (xed3_operand_get_vl(d)) << ((9)); +/* now switch code..*/ +switch(key) { +case 1: /*(1, 0) -> ELEMENT_SIZE=1 VL128 | NELEM=128*/ + xed3_operand_set_nelem(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> ELEMENT_SIZE=2 VL128 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> ELEMENT_SIZE=4 VL128 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8, 0) -> ELEMENT_SIZE=8 VL128 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(16, 0) -> ELEMENT_SIZE=16 VL128 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(32, 0) -> ELEMENT_SIZE=32 VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 64: /*(64, 0) -> ELEMENT_SIZE=64 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 128: /*(128, 0) -> ELEMENT_SIZE=128 VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 256: /*(256, 0) -> ELEMENT_SIZE=256 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 512: /*(512, 0) -> ELEMENT_SIZE=512 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 513: /*(1, 1) -> ELEMENT_SIZE=1 VL256 | NELEM=256*/ + xed3_operand_set_nelem(d, 0x100); +/*pacify the compiler */ +(void)d; + break; +case 514: /*(2, 1) -> ELEMENT_SIZE=2 VL256 | NELEM=128*/ + xed3_operand_set_nelem(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +case 516: /*(4, 1) -> ELEMENT_SIZE=4 VL256 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 520: /*(8, 1) -> ELEMENT_SIZE=8 VL256 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 528: /*(16, 1) -> ELEMENT_SIZE=16 VL256 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 544: /*(32, 1) -> ELEMENT_SIZE=32 VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 576: /*(64, 1) -> ELEMENT_SIZE=64 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 640: /*(128, 1) -> ELEMENT_SIZE=128 VL256 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 768: /*(256, 1) -> ELEMENT_SIZE=256 VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1024: /*(512, 1) -> ELEMENT_SIZE=512 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1025: /*(1, 2) -> ELEMENT_SIZE=1 VL512 | NELEM=512*/ + xed3_operand_set_nelem(d, 0x200); +/*pacify the compiler */ +(void)d; + break; +case 1026: /*(2, 2) -> ELEMENT_SIZE=2 VL512 | NELEM=256*/ + xed3_operand_set_nelem(d, 0x100); +/*pacify the compiler */ +(void)d; + break; +case 1028: /*(4, 2) -> ELEMENT_SIZE=4 VL512 | NELEM=128*/ + xed3_operand_set_nelem(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +case 1032: /*(8, 2) -> ELEMENT_SIZE=8 VL512 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 1040: /*(16, 2) -> ELEMENT_SIZE=16 VL512 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(32, 2) -> ELEMENT_SIZE=32 VL512 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(64, 2) -> ELEMENT_SIZE=64 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1152: /*(128, 2) -> ELEMENT_SIZE=128 VL512 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1280: /*(256, 2) -> ELEMENT_SIZE=256 VL512 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1536: /*(512, 2) -> ELEMENT_SIZE=512 VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_HALFMEM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_element_size(d)) << ((0)); +key += (xed3_operand_get_vl(d)) << ((9)); +/* now switch code..*/ +switch(key) { +case 1: /*(1, 0) -> ELEMENT_SIZE=1 VL128 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> ELEMENT_SIZE=2 VL128 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> ELEMENT_SIZE=4 VL128 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8, 0) -> ELEMENT_SIZE=8 VL128 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(16, 0) -> ELEMENT_SIZE=16 VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(32, 0) -> ELEMENT_SIZE=32 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 64: /*(64, 0) -> ELEMENT_SIZE=64 VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 128: /*(128, 0) -> ELEMENT_SIZE=128 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 256: /*(256, 0) -> ELEMENT_SIZE=256 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 512: /*(512, 0) -> ELEMENT_SIZE=512 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 513: /*(1, 1) -> ELEMENT_SIZE=1 VL256 | NELEM=128*/ + xed3_operand_set_nelem(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +case 514: /*(2, 1) -> ELEMENT_SIZE=2 VL256 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 516: /*(4, 1) -> ELEMENT_SIZE=4 VL256 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 520: /*(8, 1) -> ELEMENT_SIZE=8 VL256 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 528: /*(16, 1) -> ELEMENT_SIZE=16 VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 544: /*(32, 1) -> ELEMENT_SIZE=32 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 576: /*(64, 1) -> ELEMENT_SIZE=64 VL256 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 640: /*(128, 1) -> ELEMENT_SIZE=128 VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 768: /*(256, 1) -> ELEMENT_SIZE=256 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1024: /*(512, 1) -> ELEMENT_SIZE=512 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1025: /*(1, 2) -> ELEMENT_SIZE=1 VL512 | NELEM=256*/ + xed3_operand_set_nelem(d, 0x100); +/*pacify the compiler */ +(void)d; + break; +case 1026: /*(2, 2) -> ELEMENT_SIZE=2 VL512 | NELEM=128*/ + xed3_operand_set_nelem(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +case 1028: /*(4, 2) -> ELEMENT_SIZE=4 VL512 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 1032: /*(8, 2) -> ELEMENT_SIZE=8 VL512 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 1040: /*(16, 2) -> ELEMENT_SIZE=16 VL512 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(32, 2) -> ELEMENT_SIZE=32 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(64, 2) -> ELEMENT_SIZE=64 VL512 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1152: /*(128, 2) -> ELEMENT_SIZE=128 VL512 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1280: /*(256, 2) -> ELEMENT_SIZE=256 VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1536: /*(512, 2) -> ELEMENT_SIZE=512 VL512 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_QUARTERMEM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_element_size(d)) << ((0)); +key += (xed3_operand_get_vl(d)) << ((9)); +/* now switch code..*/ +switch(key) { +case 1: /*(1, 0) -> ELEMENT_SIZE=1 VL128 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> ELEMENT_SIZE=2 VL128 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> ELEMENT_SIZE=4 VL128 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8, 0) -> ELEMENT_SIZE=8 VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(16, 0) -> ELEMENT_SIZE=16 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(32, 0) -> ELEMENT_SIZE=32 VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 64: /*(64, 0) -> ELEMENT_SIZE=64 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 128: /*(128, 0) -> ELEMENT_SIZE=128 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 256: /*(256, 0) -> ELEMENT_SIZE=256 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 512: /*(512, 0) -> ELEMENT_SIZE=512 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 513: /*(1, 1) -> ELEMENT_SIZE=1 VL256 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 514: /*(2, 1) -> ELEMENT_SIZE=2 VL256 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 516: /*(4, 1) -> ELEMENT_SIZE=4 VL256 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 520: /*(8, 1) -> ELEMENT_SIZE=8 VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 528: /*(16, 1) -> ELEMENT_SIZE=16 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 544: /*(32, 1) -> ELEMENT_SIZE=32 VL256 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 576: /*(64, 1) -> ELEMENT_SIZE=64 VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 640: /*(128, 1) -> ELEMENT_SIZE=128 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 768: /*(256, 1) -> ELEMENT_SIZE=256 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1024: /*(512, 1) -> ELEMENT_SIZE=512 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1025: /*(1, 2) -> ELEMENT_SIZE=1 VL512 | NELEM=128*/ + xed3_operand_set_nelem(d, 0x80); +/*pacify the compiler */ +(void)d; + break; +case 1026: /*(2, 2) -> ELEMENT_SIZE=2 VL512 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 1028: /*(4, 2) -> ELEMENT_SIZE=4 VL512 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 1032: /*(8, 2) -> ELEMENT_SIZE=8 VL512 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 1040: /*(16, 2) -> ELEMENT_SIZE=16 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(32, 2) -> ELEMENT_SIZE=32 VL512 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(64, 2) -> ELEMENT_SIZE=64 VL512 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1152: /*(128, 2) -> ELEMENT_SIZE=128 VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1280: /*(256, 2) -> ELEMENT_SIZE=256 VL512 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1536: /*(512, 2) -> ELEMENT_SIZE=512 VL512 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_EIGHTHMEM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_element_size(d)) << ((0)); +key += (xed3_operand_get_vl(d)) << ((9)); +/* now switch code..*/ +switch(key) { +case 1: /*(1, 0) -> ELEMENT_SIZE=1 VL128 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> ELEMENT_SIZE=2 VL128 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> ELEMENT_SIZE=4 VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(8, 0) -> ELEMENT_SIZE=8 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(16, 0) -> ELEMENT_SIZE=16 VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(32, 0) -> ELEMENT_SIZE=32 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 64: /*(64, 0) -> ELEMENT_SIZE=64 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 128: /*(128, 0) -> ELEMENT_SIZE=128 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 256: /*(256, 0) -> ELEMENT_SIZE=256 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 512: /*(512, 0) -> ELEMENT_SIZE=512 VL128 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 513: /*(1, 1) -> ELEMENT_SIZE=1 VL256 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 514: /*(2, 1) -> ELEMENT_SIZE=2 VL256 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 516: /*(4, 1) -> ELEMENT_SIZE=4 VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 520: /*(8, 1) -> ELEMENT_SIZE=8 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 528: /*(16, 1) -> ELEMENT_SIZE=16 VL256 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 544: /*(32, 1) -> ELEMENT_SIZE=32 VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 576: /*(64, 1) -> ELEMENT_SIZE=64 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 640: /*(128, 1) -> ELEMENT_SIZE=128 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 768: /*(256, 1) -> ELEMENT_SIZE=256 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1024: /*(512, 1) -> ELEMENT_SIZE=512 VL256 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1025: /*(1, 2) -> ELEMENT_SIZE=1 VL512 | NELEM=64*/ + xed3_operand_set_nelem(d, 0x40); +/*pacify the compiler */ +(void)d; + break; +case 1026: /*(2, 2) -> ELEMENT_SIZE=2 VL512 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 1028: /*(4, 2) -> ELEMENT_SIZE=4 VL512 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 1032: /*(8, 2) -> ELEMENT_SIZE=8 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1040: /*(16, 2) -> ELEMENT_SIZE=16 VL512 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(32, 2) -> ELEMENT_SIZE=32 VL512 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(64, 2) -> ELEMENT_SIZE=64 VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1152: /*(128, 2) -> ELEMENT_SIZE=128 VL512 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1280: /*(256, 2) -> ELEMENT_SIZE=256 VL512 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +case 1536: /*(512, 2) -> ELEMENT_SIZE=512 VL512 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER_BYTE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER_WORD(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_LDOP_D(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_LDOP_Q(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE_BYTE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE_WORD(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_BYTE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_WORD(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_SCALAR(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1_SUBDWORD(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_READER_SUBDWORD(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_LDOP(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GPR_WRITER_STORE_SUBDWORD(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE1(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_GSCAT(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=1*/ + xed3_operand_set_nelem(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE2(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE4(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_TUPLE8(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vl(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VL128 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_MEM128(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> BCRC=0b0 | ELEMENT_SIZE=64 NELEM=2*/ + xed3_operand_set_element_size(d, 0x40); + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> BCRC=0b1 | error*/ + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_FULL(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_element_size(d)) << ((1)); +key += (xed3_operand_get_vl(d)) << ((10)); +/* now switch code..*/ +switch(key) { +case 32: /*(0, 16, 0) -> BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 33: /*(1, 16, 0) -> BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO8_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xe); +/*pacify the compiler */ +(void)d; + break; +case 64: /*(0, 32, 0) -> BCRC=0b0 ELEMENT_SIZE=32 VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 65: /*(1, 32, 0) -> BCRC=0b1 ELEMENT_SIZE=32 VL128 | NELEM=1 EMX_BROADCAST_1TO4_32*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xa); +/*pacify the compiler */ +(void)d; + break; +case 128: /*(0, 64, 0) -> BCRC=0b0 ELEMENT_SIZE=64 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 129: /*(1, 64, 0) -> BCRC=0b1 ELEMENT_SIZE=64 VL128 | NELEM=1 EMX_BROADCAST_1TO2_64*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xb); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(0, 16, 1) -> BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 1057: /*(1, 16, 1) -> BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO16_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xf); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(0, 32, 1) -> BCRC=0b0 ELEMENT_SIZE=32 VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1089: /*(1, 32, 1) -> BCRC=0b1 ELEMENT_SIZE=32 VL256 | NELEM=1 EMX_BROADCAST_1TO8_32*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x3); +/*pacify the compiler */ +(void)d; + break; +case 1152: /*(0, 64, 1) -> BCRC=0b0 ELEMENT_SIZE=64 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1153: /*(1, 64, 1) -> BCRC=0b1 ELEMENT_SIZE=64 VL256 | NELEM=1 EMX_BROADCAST_1TO4_64*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xd); +/*pacify the compiler */ +(void)d; + break; +case 2080: /*(0, 16, 2) -> BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=32*/ + xed3_operand_set_nelem(d, 0x20); +/*pacify the compiler */ +(void)d; + break; +case 2081: /*(1, 16, 2) -> BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO32_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2112: /*(0, 32, 2) -> BCRC=0b0 ELEMENT_SIZE=32 VL512 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2113: /*(1, 32, 2) -> BCRC=0b1 ELEMENT_SIZE=32 VL512 | NELEM=1 EMX_BROADCAST_1TO16_32*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 2176: /*(0, 64, 2) -> BCRC=0b0 ELEMENT_SIZE=64 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 2177: /*(1, 64, 2) -> BCRC=0b1 ELEMENT_SIZE=64 VL512 | NELEM=1 EMX_BROADCAST_1TO8_64*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x5); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_HALF(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_element_size(d)) << ((1)); +key += (xed3_operand_get_vl(d)) << ((10)); +/* now switch code..*/ +switch(key) { +case 32: /*(0, 16, 0) -> BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 33: /*(1, 16, 0) -> BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO4_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x1b); +/*pacify the compiler */ +(void)d; + break; +case 64: /*(0, 32, 0) -> BCRC=0b0 ELEMENT_SIZE=32 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 65: /*(1, 32, 0) -> BCRC=0b1 ELEMENT_SIZE=32 VL128 | NELEM=1 EMX_BROADCAST_1TO2_32*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x16); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(0, 16, 1) -> BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 1057: /*(1, 16, 1) -> BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO8_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xe); +/*pacify the compiler */ +(void)d; + break; +case 1088: /*(0, 32, 1) -> BCRC=0b0 ELEMENT_SIZE=32 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1089: /*(1, 32, 1) -> BCRC=0b1 ELEMENT_SIZE=32 VL256 | NELEM=1 EMX_BROADCAST_1TO4_32*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xa); +/*pacify the compiler */ +(void)d; + break; +case 2080: /*(0, 16, 2) -> BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=16*/ + xed3_operand_set_nelem(d, 0x10); +/*pacify the compiler */ +(void)d; + break; +case 2081: /*(1, 16, 2) -> BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO16_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xf); +/*pacify the compiler */ +(void)d; + break; +case 2112: /*(0, 32, 2) -> BCRC=0b0 ELEMENT_SIZE=32 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 2113: /*(1, 32, 2) -> BCRC=0b1 ELEMENT_SIZE=32 VL512 | NELEM=1 EMX_BROADCAST_1TO8_32*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x3); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FIX_ROUND_LEN512(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | VL512*/ + xed3_operand_set_vl(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | VL512*/ + xed3_operand_set_vl(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | VL512*/ + xed3_operand_set_vl(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_FIX_ROUND_LEN128(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | VL128*/ + xed3_operand_set_vl(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | VL128*/ + xed3_operand_set_vl(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | VL128*/ + xed3_operand_set_vl(d, 0x0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VMODRM_ZMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MOD=0b00 UISA_VSIB_ZMM() |*/ + xed3_capture_nt_UISA_VSIB_ZMM(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MOD=0b01 UISA_VSIB_ZMM() MEMDISP8() |*/ + xed3_capture_nt_UISA_VSIB_ZMM(d); + xed3_capture_nt_MEMDISP8(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MOD=0b10 UISA_VSIB_ZMM() MEMDISP32() |*/ + xed3_capture_nt_UISA_VSIB_ZMM(d); + xed3_capture_nt_MEMDISP32(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VMODRM_YMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MOD=0b00 UISA_VSIB_YMM() |*/ + xed3_capture_nt_UISA_VSIB_YMM(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MOD=0b01 UISA_VSIB_YMM() MEMDISP8() |*/ + xed3_capture_nt_UISA_VSIB_YMM(d); + xed3_capture_nt_MEMDISP8(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MOD=0b10 UISA_VSIB_YMM() MEMDISP32() |*/ + xed3_capture_nt_UISA_VSIB_YMM(d); + xed3_capture_nt_MEMDISP32(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VMODRM_XMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MOD=0b00 UISA_VSIB_XMM() |*/ + xed3_capture_nt_UISA_VSIB_XMM(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MOD=0b01 UISA_VSIB_XMM() MEMDISP8() |*/ + xed3_capture_nt_UISA_VSIB_XMM(d); + xed3_capture_nt_MEMDISP8(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MOD=0b10 UISA_VSIB_XMM() MEMDISP32() |*/ + xed3_capture_nt_UISA_VSIB_XMM(d); + xed3_capture_nt_MEMDISP32(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_ZMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_sibscale(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=1*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_ZMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=2*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_ZMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=4*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_ZMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_ZMM() SCALE=8*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_ZMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_YMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_sibscale(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=1*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=2*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=4*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_YMM() SCALE=8*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_YMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_XMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_sibscale(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> SIBSCALE[0b00] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=1*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x1); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> SIBSCALE[0b01] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=2*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> SIBSCALE[0b10] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=4*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> SIBSCALE[0b11] SIBINDEX[iii] SIBBASE[bbb] UISA_VSIB_BASE() | INDEX=UISA_VSIB_INDEX_XMM() SCALE=8*/ + xed3_capture_nt_UISA_VSIB_BASE(d); + xed3_capture_nt_UISA_VSIB_INDEX_XMM(d); + xed3_operand_set_index(d, xed3_operand_get_outreg(d)); + xed3_operand_set_scale(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_INDEX_ZMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM8*/ + xed3_operand_set_outreg(d, XED_REG_ZMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM9*/ + xed3_operand_set_outreg(d, XED_REG_ZMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM10*/ + xed3_operand_set_outreg(d, XED_REG_ZMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM11*/ + xed3_operand_set_outreg(d, XED_REG_ZMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM12*/ + xed3_operand_set_outreg(d, XED_REG_ZMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM13*/ + xed3_operand_set_outreg(d, XED_REG_ZMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM14*/ + xed3_operand_set_outreg(d, XED_REG_ZMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM15*/ + xed3_operand_set_outreg(d, XED_REG_ZMM15); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_ZMM16*/ + xed3_operand_set_outreg(d, XED_REG_ZMM16); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_ZMM24*/ + xed3_operand_set_outreg(d, XED_REG_ZMM24); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_ZMM17*/ + xed3_operand_set_outreg(d, XED_REG_ZMM17); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_ZMM25*/ + xed3_operand_set_outreg(d, XED_REG_ZMM25); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 2, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_ZMM18*/ + xed3_operand_set_outreg(d, XED_REG_ZMM18); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 2, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_ZMM26*/ + xed3_operand_set_outreg(d, XED_REG_ZMM26); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 3, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_ZMM19*/ + xed3_operand_set_outreg(d, XED_REG_ZMM19); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 3, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_ZMM27*/ + xed3_operand_set_outreg(d, XED_REG_ZMM27); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 4, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_ZMM20*/ + xed3_operand_set_outreg(d, XED_REG_ZMM20); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 4, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_ZMM28*/ + xed3_operand_set_outreg(d, XED_REG_ZMM28); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 5, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_ZMM21*/ + xed3_operand_set_outreg(d, XED_REG_ZMM21); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 5, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_ZMM29*/ + xed3_operand_set_outreg(d, XED_REG_ZMM29); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 6, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_ZMM22*/ + xed3_operand_set_outreg(d, XED_REG_ZMM22); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 6, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_ZMM30*/ + xed3_operand_set_outreg(d, XED_REG_ZMM30); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 7, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_ZMM23*/ + xed3_operand_set_outreg(d, XED_REG_ZMM23); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 7, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_ZMM31*/ + xed3_operand_set_outreg(d, XED_REG_ZMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_INDEX_YMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_YMM16*/ + xed3_operand_set_outreg(d, XED_REG_YMM16); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_YMM24*/ + xed3_operand_set_outreg(d, XED_REG_YMM24); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_YMM17*/ + xed3_operand_set_outreg(d, XED_REG_YMM17); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_YMM25*/ + xed3_operand_set_outreg(d, XED_REG_YMM25); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 2, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_YMM18*/ + xed3_operand_set_outreg(d, XED_REG_YMM18); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 2, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_YMM26*/ + xed3_operand_set_outreg(d, XED_REG_YMM26); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 3, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_YMM19*/ + xed3_operand_set_outreg(d, XED_REG_YMM19); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 3, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_YMM27*/ + xed3_operand_set_outreg(d, XED_REG_YMM27); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 4, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_YMM20*/ + xed3_operand_set_outreg(d, XED_REG_YMM20); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 4, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_YMM28*/ + xed3_operand_set_outreg(d, XED_REG_YMM28); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 5, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_YMM21*/ + xed3_operand_set_outreg(d, XED_REG_YMM21); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 5, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_YMM29*/ + xed3_operand_set_outreg(d, XED_REG_YMM29); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 6, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_YMM22*/ + xed3_operand_set_outreg(d, XED_REG_YMM22); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 6, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_YMM30*/ + xed3_operand_set_outreg(d, XED_REG_YMM30); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 7, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_YMM23*/ + xed3_operand_set_outreg(d, XED_REG_YMM23); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 7, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_YMM31*/ + xed3_operand_set_outreg(d, XED_REG_YMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_INDEX_XMM(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexx(d)) << ((0)); +key += (xed3_operand_get_sibindex(d)) << ((1)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 2, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 3, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 4, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 5, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 6, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7, 0) -> VEXDEST4=0 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 7, 0) -> VEXDEST4=0 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=0 | OUTREG=XED_REG_XMM16*/ + xed3_operand_set_outreg(d, XED_REG_XMM16); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=0 | OUTREG=XED_REG_XMM24*/ + xed3_operand_set_outreg(d, XED_REG_XMM24); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=1 | OUTREG=XED_REG_XMM17*/ + xed3_operand_set_outreg(d, XED_REG_XMM17); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=1 | OUTREG=XED_REG_XMM25*/ + xed3_operand_set_outreg(d, XED_REG_XMM25); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 2, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=2 | OUTREG=XED_REG_XMM18*/ + xed3_operand_set_outreg(d, XED_REG_XMM18); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 2, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=2 | OUTREG=XED_REG_XMM26*/ + xed3_operand_set_outreg(d, XED_REG_XMM26); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 3, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=3 | OUTREG=XED_REG_XMM19*/ + xed3_operand_set_outreg(d, XED_REG_XMM19); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 3, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=3 | OUTREG=XED_REG_XMM27*/ + xed3_operand_set_outreg(d, XED_REG_XMM27); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 4, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=4 | OUTREG=XED_REG_XMM20*/ + xed3_operand_set_outreg(d, XED_REG_XMM20); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 4, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=4 | OUTREG=XED_REG_XMM28*/ + xed3_operand_set_outreg(d, XED_REG_XMM28); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 5, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=5 | OUTREG=XED_REG_XMM21*/ + xed3_operand_set_outreg(d, XED_REG_XMM21); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 5, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=5 | OUTREG=XED_REG_XMM29*/ + xed3_operand_set_outreg(d, XED_REG_XMM29); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 6, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=6 | OUTREG=XED_REG_XMM22*/ + xed3_operand_set_outreg(d, XED_REG_XMM22); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 6, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=6 | OUTREG=XED_REG_XMM30*/ + xed3_operand_set_outreg(d, XED_REG_XMM30); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 7, 1) -> VEXDEST4=1 REXX=0 SIBINDEX=7 | OUTREG=XED_REG_XMM23*/ + xed3_operand_set_outreg(d, XED_REG_XMM23); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 7, 1) -> VEXDEST4=1 REXX=1 SIBINDEX=7 | OUTREG=XED_REG_XMM31*/ + xed3_operand_set_outreg(d, XED_REG_XMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_UISA_VSIB_BASE(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((2)); +key += (xed3_operand_get_sibbase(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 1: /*(1, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 2: /*(2, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ +case 3: /*(3, 0, 0) -> REXB=0 SIBBASE=0 | BASE0=ArAX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArAX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 5: /*(1, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 6: /*(2, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ +case 7: /*(3, 1, 0) -> REXB=1 SIBBASE=0 | BASE0=Ar8() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar8(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 9: /*(1, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 10: /*(2, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ +case 11: /*(3, 0, 1) -> REXB=0 SIBBASE=1 | BASE0=ArCX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArCX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 13: /*(1, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 14: /*(2, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ +case 15: /*(3, 1, 1) -> REXB=1 SIBBASE=1 | BASE0=Ar9() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar9(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 17: /*(1, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 18: /*(2, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ +case 19: /*(3, 0, 2) -> REXB=0 SIBBASE=2 | BASE0=ArDX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 21: /*(1, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 22: /*(2, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ +case 23: /*(3, 1, 2) -> REXB=1 SIBBASE=2 | BASE0=Ar10() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar10(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 25: /*(1, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 26: /*(2, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ +case 27: /*(3, 0, 3) -> REXB=0 SIBBASE=3 | BASE0=ArBX() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArBX(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 29: /*(1, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 30: /*(2, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ +case 31: /*(3, 1, 3) -> REXB=1 SIBBASE=3 | BASE0=Ar11() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar11(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 32: /*(0, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 33: /*(1, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 34: /*(2, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ +case 35: /*(3, 0, 4) -> REXB=0 SIBBASE=4 | BASE0=ArSP() SEG0=FINAL_SSEG()*/ + xed3_capture_nt_ArSP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 36: /*(0, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 37: /*(1, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 38: /*(2, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ +case 39: /*(3, 1, 4) -> REXB=1 SIBBASE=4 | BASE0=Ar12() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar12(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 40: /*(0, 0, 5) -> REXB=0 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()*/ + xed3_capture_nt_MEMDISP32(d); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 41: /*(1, 0, 5) -> REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()*/ +case 42: /*(2, 0, 5) -> REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()*/ +case 43: /*(3, 0, 5) -> REXB=0 SIBBASE=5 MOD!=0 | BASE0=ArBP() SEG0=FINAL_SSEG()*/ + xed3_capture_nt_ArBP(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_SSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 44: /*(0, 1, 5) -> REXB=1 SIBBASE=5 MOD=0 MEMDISP32() | BASE0=XED_REG_INVALID SEG0=FINAL_DSEG()*/ + xed3_capture_nt_MEMDISP32(d); + xed3_operand_set_base0(d, XED_REG_INVALID); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 45: /*(1, 1, 5) -> REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()*/ +case 46: /*(2, 1, 5) -> REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()*/ +case 47: /*(3, 1, 5) -> REXB=1 SIBBASE=5 MOD!=0 | BASE0=Ar13() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar13(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 48: /*(0, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 49: /*(1, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 50: /*(2, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ +case 51: /*(3, 0, 6) -> REXB=0 SIBBASE=6 | BASE0=ArSI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArSI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 52: /*(0, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 53: /*(1, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 54: /*(2, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ +case 55: /*(3, 1, 6) -> REXB=1 SIBBASE=6 | BASE0=Ar14() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar14(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 56: /*(0, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 57: /*(1, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 58: /*(2, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ +case 59: /*(3, 0, 7) -> REXB=0 SIBBASE=7 | BASE0=ArDI() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_ArDI(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +case 60: /*(0, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 61: /*(1, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 62: /*(2, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ +case 63: /*(3, 1, 7) -> REXB=1 SIBBASE=7 | BASE0=Ar15() SEG0=FINAL_DSEG()*/ + xed3_capture_nt_Ar15(d); + xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); + xed3_capture_nt_FINAL_DSEG(d); + xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASK1(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mask(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MASK=0x0 | OUTREG=XED_REG_K0*/ + xed3_operand_set_outreg(d, XED_REG_K0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MASK=0x1 | OUTREG=XED_REG_K1*/ + xed3_operand_set_outreg(d, XED_REG_K1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MASK=0x2 | OUTREG=XED_REG_K2*/ + xed3_operand_set_outreg(d, XED_REG_K2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> MASK=0x3 | OUTREG=XED_REG_K3*/ + xed3_operand_set_outreg(d, XED_REG_K3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> MASK=0x4 | OUTREG=XED_REG_K4*/ + xed3_operand_set_outreg(d, XED_REG_K4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> MASK=0x5 | OUTREG=XED_REG_K5*/ + xed3_operand_set_outreg(d, XED_REG_K5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> MASK=0x6 | OUTREG=XED_REG_K6*/ + xed3_operand_set_outreg(d, XED_REG_K6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> MASK=0x7 | OUTREG=XED_REG_K7*/ + xed3_operand_set_outreg(d, XED_REG_K7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASKNOT0(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mask(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> MASK=0x0 | OUTREG=XED_REG_ERROR*/ + xed3_operand_set_outreg(d, XED_REG_ERROR); + xed3_operand_set_error(d, XED_ERROR_BAD_REGISTER); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> MASK=0x1 | OUTREG=XED_REG_K1*/ + xed3_operand_set_outreg(d, XED_REG_K1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> MASK=0x2 | OUTREG=XED_REG_K2*/ + xed3_operand_set_outreg(d, XED_REG_K2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> MASK=0x3 | OUTREG=XED_REG_K3*/ + xed3_operand_set_outreg(d, XED_REG_K3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> MASK=0x4 | OUTREG=XED_REG_K4*/ + xed3_operand_set_outreg(d, XED_REG_K4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> MASK=0x5 | OUTREG=XED_REG_K5*/ + xed3_operand_set_outreg(d, XED_REG_K5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> MASK=0x6 | OUTREG=XED_REG_K6*/ + xed3_operand_set_outreg(d, XED_REG_K6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> MASK=0x7 | OUTREG=XED_REG_K7*/ + xed3_operand_set_outreg(d, XED_REG_K7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASK_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXRR=0 REXR=0 REG=0x0 | OUTREG=XED_REG_K0*/ + xed3_operand_set_outreg(d, XED_REG_K0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXRR=0 REXR=0 REG=0x1 | OUTREG=XED_REG_K1*/ + xed3_operand_set_outreg(d, XED_REG_K1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> REXRR=0 REXR=0 REG=0x2 | OUTREG=XED_REG_K2*/ + xed3_operand_set_outreg(d, XED_REG_K2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> REXRR=0 REXR=0 REG=0x3 | OUTREG=XED_REG_K3*/ + xed3_operand_set_outreg(d, XED_REG_K3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> REXRR=0 REXR=0 REG=0x4 | OUTREG=XED_REG_K4*/ + xed3_operand_set_outreg(d, XED_REG_K4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> REXRR=0 REXR=0 REG=0x5 | OUTREG=XED_REG_K5*/ + xed3_operand_set_outreg(d, XED_REG_K5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> REXRR=0 REXR=0 REG=0x6 | OUTREG=XED_REG_K6*/ + xed3_operand_set_outreg(d, XED_REG_K6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> REXRR=0 REXR=0 REG=0x7 | OUTREG=XED_REG_K7*/ + xed3_operand_set_outreg(d, XED_REG_K7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASK_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0x0 | OUTREG=XED_REG_K0*/ + xed3_operand_set_outreg(d, XED_REG_K0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=0x1 | OUTREG=XED_REG_K1*/ + xed3_operand_set_outreg(d, XED_REG_K1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=0x2 | OUTREG=XED_REG_K2*/ + xed3_operand_set_outreg(d, XED_REG_K2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=0x3 | OUTREG=XED_REG_K3*/ + xed3_operand_set_outreg(d, XED_REG_K3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=0x4 | OUTREG=XED_REG_K4*/ + xed3_operand_set_outreg(d, XED_REG_K4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=0x5 | OUTREG=XED_REG_K5*/ + xed3_operand_set_outreg(d, XED_REG_K5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=0x6 | OUTREG=XED_REG_K6*/ + xed3_operand_set_outreg(d, XED_REG_K6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=0x7 | OUTREG=XED_REG_K7*/ + xed3_operand_set_outreg(d, XED_REG_K7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASK_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=MASK_N32()*/ + xed3_capture_nt_MASK_N32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=MASK_N32()*/ + xed3_capture_nt_MASK_N32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=MASK_N64()*/ + xed3_capture_nt_MASK_N64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASK_N64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 8: /*(0, 1) -> VEXDEST3=1 VEXDEST210=0x0 | OUTREG=XED_REG_K7*/ + xed3_operand_set_outreg(d, XED_REG_K7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> VEXDEST3=1 VEXDEST210=0x1 | OUTREG=XED_REG_K6*/ + xed3_operand_set_outreg(d, XED_REG_K6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> VEXDEST3=1 VEXDEST210=0x2 | OUTREG=XED_REG_K5*/ + xed3_operand_set_outreg(d, XED_REG_K5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> VEXDEST3=1 VEXDEST210=0x3 | OUTREG=XED_REG_K4*/ + xed3_operand_set_outreg(d, XED_REG_K4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> VEXDEST3=1 VEXDEST210=0x4 | OUTREG=XED_REG_K3*/ + xed3_operand_set_outreg(d, XED_REG_K3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> VEXDEST3=1 VEXDEST210=0x5 | OUTREG=XED_REG_K2*/ + xed3_operand_set_outreg(d, XED_REG_K2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> VEXDEST3=1 VEXDEST210=0x6 | OUTREG=XED_REG_K1*/ + xed3_operand_set_outreg(d, XED_REG_K1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> VEXDEST3=1 VEXDEST210=0x7 | OUTREG=XED_REG_K0*/ + xed3_operand_set_outreg(d, XED_REG_K0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_MASK_N32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0x0 | OUTREG=XED_REG_K7*/ + xed3_operand_set_outreg(d, XED_REG_K7); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=0x1 | OUTREG=XED_REG_K6*/ + xed3_operand_set_outreg(d, XED_REG_K6); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=0x2 | OUTREG=XED_REG_K5*/ + xed3_operand_set_outreg(d, XED_REG_K5); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=0x3 | OUTREG=XED_REG_K4*/ + xed3_operand_set_outreg(d, XED_REG_K4); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=0x4 | OUTREG=XED_REG_K3*/ + xed3_operand_set_outreg(d, XED_REG_K3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=0x5 | OUTREG=XED_REG_K2*/ + xed3_operand_set_outreg(d, XED_REG_K2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=0x6 | OUTREG=XED_REG_K1*/ + xed3_operand_set_outreg(d, XED_REG_K1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=0x7 | OUTREG=XED_REG_K0*/ + xed3_operand_set_outreg(d, XED_REG_K0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_R3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_R3_32()*/ + xed3_capture_nt_XMM_R3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_R3_32()*/ + xed3_capture_nt_XMM_R3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_R3_64()*/ + xed3_capture_nt_XMM_R3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_R3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_R3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1, 0) -> REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1, 0) -> REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1, 0) -> REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1, 0) -> REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_XMM16*/ + xed3_operand_set_outreg(d, XED_REG_XMM16); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_XMM17*/ + xed3_operand_set_outreg(d, XED_REG_XMM17); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_XMM18*/ + xed3_operand_set_outreg(d, XED_REG_XMM18); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_XMM19*/ + xed3_operand_set_outreg(d, XED_REG_XMM19); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_XMM20*/ + xed3_operand_set_outreg(d, XED_REG_XMM20); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_XMM21*/ + xed3_operand_set_outreg(d, XED_REG_XMM21); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_XMM22*/ + xed3_operand_set_outreg(d, XED_REG_XMM22); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_XMM23*/ + xed3_operand_set_outreg(d, XED_REG_XMM23); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 1, 1) -> REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_XMM24*/ + xed3_operand_set_outreg(d, XED_REG_XMM24); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 1, 1) -> REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_XMM25*/ + xed3_operand_set_outreg(d, XED_REG_XMM25); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 1, 1) -> REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_XMM26*/ + xed3_operand_set_outreg(d, XED_REG_XMM26); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(3, 1, 1) -> REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_XMM27*/ + xed3_operand_set_outreg(d, XED_REG_XMM27); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(4, 1, 1) -> REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_XMM28*/ + xed3_operand_set_outreg(d, XED_REG_XMM28); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(5, 1, 1) -> REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_XMM29*/ + xed3_operand_set_outreg(d, XED_REG_XMM29); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(6, 1, 1) -> REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_XMM30*/ + xed3_operand_set_outreg(d, XED_REG_XMM30); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(7, 1, 1) -> REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_XMM31*/ + xed3_operand_set_outreg(d, XED_REG_XMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_R3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_R3_32()*/ + xed3_capture_nt_YMM_R3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_R3_32()*/ + xed3_capture_nt_YMM_R3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_R3_64()*/ + xed3_capture_nt_YMM_R3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_R3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_R3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1, 0) -> REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1, 0) -> REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1, 0) -> REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1, 0) -> REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_YMM16*/ + xed3_operand_set_outreg(d, XED_REG_YMM16); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_YMM17*/ + xed3_operand_set_outreg(d, XED_REG_YMM17); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_YMM18*/ + xed3_operand_set_outreg(d, XED_REG_YMM18); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_YMM19*/ + xed3_operand_set_outreg(d, XED_REG_YMM19); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_YMM20*/ + xed3_operand_set_outreg(d, XED_REG_YMM20); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_YMM21*/ + xed3_operand_set_outreg(d, XED_REG_YMM21); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_YMM22*/ + xed3_operand_set_outreg(d, XED_REG_YMM22); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_YMM23*/ + xed3_operand_set_outreg(d, XED_REG_YMM23); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 1, 1) -> REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_YMM24*/ + xed3_operand_set_outreg(d, XED_REG_YMM24); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 1, 1) -> REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_YMM25*/ + xed3_operand_set_outreg(d, XED_REG_YMM25); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 1, 1) -> REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_YMM26*/ + xed3_operand_set_outreg(d, XED_REG_YMM26); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(3, 1, 1) -> REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_YMM27*/ + xed3_operand_set_outreg(d, XED_REG_YMM27); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(4, 1, 1) -> REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_YMM28*/ + xed3_operand_set_outreg(d, XED_REG_YMM28); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(5, 1, 1) -> REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_YMM29*/ + xed3_operand_set_outreg(d, XED_REG_YMM29); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(6, 1, 1) -> REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_YMM30*/ + xed3_operand_set_outreg(d, XED_REG_YMM30); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(7, 1, 1) -> REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_YMM31*/ + xed3_operand_set_outreg(d, XED_REG_YMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_R3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=ZMM_R3_32()*/ + xed3_capture_nt_ZMM_R3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=ZMM_R3_32()*/ + xed3_capture_nt_ZMM_R3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=ZMM_R3_64()*/ + xed3_capture_nt_ZMM_R3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_R3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> REG=0 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> REG=1 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> REG=2 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> REG=3 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> REG=4 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> REG=5 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> REG=6 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> REG=7 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_R3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXRR=0 REXR=0 REG=0 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXRR=0 REXR=0 REG=1 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> REXRR=0 REXR=0 REG=2 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> REXRR=0 REXR=0 REG=3 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> REXRR=0 REXR=0 REG=4 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> REXRR=0 REXR=0 REG=5 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> REXRR=0 REXR=0 REG=6 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> REXRR=0 REXR=0 REG=7 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1, 0) -> REXRR=0 REXR=1 REG=0 | OUTREG=XED_REG_ZMM8*/ + xed3_operand_set_outreg(d, XED_REG_ZMM8); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1, 0) -> REXRR=0 REXR=1 REG=1 | OUTREG=XED_REG_ZMM9*/ + xed3_operand_set_outreg(d, XED_REG_ZMM9); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1, 0) -> REXRR=0 REXR=1 REG=2 | OUTREG=XED_REG_ZMM10*/ + xed3_operand_set_outreg(d, XED_REG_ZMM10); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1, 0) -> REXRR=0 REXR=1 REG=3 | OUTREG=XED_REG_ZMM11*/ + xed3_operand_set_outreg(d, XED_REG_ZMM11); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> REXRR=0 REXR=1 REG=4 | OUTREG=XED_REG_ZMM12*/ + xed3_operand_set_outreg(d, XED_REG_ZMM12); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> REXRR=0 REXR=1 REG=5 | OUTREG=XED_REG_ZMM13*/ + xed3_operand_set_outreg(d, XED_REG_ZMM13); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> REXRR=0 REXR=1 REG=6 | OUTREG=XED_REG_ZMM14*/ + xed3_operand_set_outreg(d, XED_REG_ZMM14); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> REXRR=0 REXR=1 REG=7 | OUTREG=XED_REG_ZMM15*/ + xed3_operand_set_outreg(d, XED_REG_ZMM15); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> REXRR=1 REXR=0 REG=0 | OUTREG=XED_REG_ZMM16*/ + xed3_operand_set_outreg(d, XED_REG_ZMM16); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> REXRR=1 REXR=0 REG=1 | OUTREG=XED_REG_ZMM17*/ + xed3_operand_set_outreg(d, XED_REG_ZMM17); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> REXRR=1 REXR=0 REG=2 | OUTREG=XED_REG_ZMM18*/ + xed3_operand_set_outreg(d, XED_REG_ZMM18); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> REXRR=1 REXR=0 REG=3 | OUTREG=XED_REG_ZMM19*/ + xed3_operand_set_outreg(d, XED_REG_ZMM19); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> REXRR=1 REXR=0 REG=4 | OUTREG=XED_REG_ZMM20*/ + xed3_operand_set_outreg(d, XED_REG_ZMM20); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> REXRR=1 REXR=0 REG=5 | OUTREG=XED_REG_ZMM21*/ + xed3_operand_set_outreg(d, XED_REG_ZMM21); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> REXRR=1 REXR=0 REG=6 | OUTREG=XED_REG_ZMM22*/ + xed3_operand_set_outreg(d, XED_REG_ZMM22); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> REXRR=1 REXR=0 REG=7 | OUTREG=XED_REG_ZMM23*/ + xed3_operand_set_outreg(d, XED_REG_ZMM23); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 1, 1) -> REXRR=1 REXR=1 REG=0 | OUTREG=XED_REG_ZMM24*/ + xed3_operand_set_outreg(d, XED_REG_ZMM24); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 1, 1) -> REXRR=1 REXR=1 REG=1 | OUTREG=XED_REG_ZMM25*/ + xed3_operand_set_outreg(d, XED_REG_ZMM25); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 1, 1) -> REXRR=1 REXR=1 REG=2 | OUTREG=XED_REG_ZMM26*/ + xed3_operand_set_outreg(d, XED_REG_ZMM26); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(3, 1, 1) -> REXRR=1 REXR=1 REG=3 | OUTREG=XED_REG_ZMM27*/ + xed3_operand_set_outreg(d, XED_REG_ZMM27); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(4, 1, 1) -> REXRR=1 REXR=1 REG=4 | OUTREG=XED_REG_ZMM28*/ + xed3_operand_set_outreg(d, XED_REG_ZMM28); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(5, 1, 1) -> REXRR=1 REXR=1 REG=5 | OUTREG=XED_REG_ZMM29*/ + xed3_operand_set_outreg(d, XED_REG_ZMM29); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(6, 1, 1) -> REXRR=1 REXR=1 REG=6 | OUTREG=XED_REG_ZMM30*/ + xed3_operand_set_outreg(d, XED_REG_ZMM30); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(7, 1, 1) -> REXRR=1 REXR=1 REG=7 | OUTREG=XED_REG_ZMM31*/ + xed3_operand_set_outreg(d, XED_REG_ZMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_B3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_B3_32()*/ + xed3_capture_nt_XMM_B3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_B3_32()*/ + xed3_capture_nt_XMM_B3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_B3_64()*/ + xed3_capture_nt_XMM_B3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_B3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_B3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rexx(d)) << ((1)); +key += (xed3_operand_get_rm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_XMM16*/ + xed3_operand_set_outreg(d, XED_REG_XMM16); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_XMM24*/ + xed3_operand_set_outreg(d, XED_REG_XMM24); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 0, 1) -> REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 0, 1) -> REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 1, 1) -> REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_XMM17*/ + xed3_operand_set_outreg(d, XED_REG_XMM17); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 1, 1) -> REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_XMM25*/ + xed3_operand_set_outreg(d, XED_REG_XMM25); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 2) -> REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 0, 2) -> REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 1, 2) -> REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_XMM18*/ + xed3_operand_set_outreg(d, XED_REG_XMM18); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 1, 2) -> REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_XMM26*/ + xed3_operand_set_outreg(d, XED_REG_XMM26); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 0, 3) -> REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 0, 3) -> REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 1, 3) -> REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_XMM19*/ + xed3_operand_set_outreg(d, XED_REG_XMM19); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 1, 3) -> REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_XMM27*/ + xed3_operand_set_outreg(d, XED_REG_XMM27); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 4) -> REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 4) -> REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 4) -> REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_XMM20*/ + xed3_operand_set_outreg(d, XED_REG_XMM20); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 4) -> REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_XMM28*/ + xed3_operand_set_outreg(d, XED_REG_XMM28); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 0, 5) -> REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 0, 5) -> REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 1, 5) -> REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_XMM21*/ + xed3_operand_set_outreg(d, XED_REG_XMM21); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 1, 5) -> REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_XMM29*/ + xed3_operand_set_outreg(d, XED_REG_XMM29); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 6) -> REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 0, 6) -> REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 1, 6) -> REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_XMM22*/ + xed3_operand_set_outreg(d, XED_REG_XMM22); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 1, 6) -> REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_XMM30*/ + xed3_operand_set_outreg(d, XED_REG_XMM30); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 0, 7) -> REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 0, 7) -> REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 1, 7) -> REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_XMM23*/ + xed3_operand_set_outreg(d, XED_REG_XMM23); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 1, 7) -> REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_XMM31*/ + xed3_operand_set_outreg(d, XED_REG_XMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_B3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_B3_32()*/ + xed3_capture_nt_YMM_B3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_B3_32()*/ + xed3_capture_nt_YMM_B3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_B3_64()*/ + xed3_capture_nt_YMM_B3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_B3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_B3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rexx(d)) << ((1)); +key += (xed3_operand_get_rm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_YMM16*/ + xed3_operand_set_outreg(d, XED_REG_YMM16); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_YMM24*/ + xed3_operand_set_outreg(d, XED_REG_YMM24); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 0, 1) -> REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 0, 1) -> REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 1, 1) -> REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_YMM17*/ + xed3_operand_set_outreg(d, XED_REG_YMM17); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 1, 1) -> REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_YMM25*/ + xed3_operand_set_outreg(d, XED_REG_YMM25); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 2) -> REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 0, 2) -> REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 1, 2) -> REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_YMM18*/ + xed3_operand_set_outreg(d, XED_REG_YMM18); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 1, 2) -> REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_YMM26*/ + xed3_operand_set_outreg(d, XED_REG_YMM26); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 0, 3) -> REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 0, 3) -> REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 1, 3) -> REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_YMM19*/ + xed3_operand_set_outreg(d, XED_REG_YMM19); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 1, 3) -> REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_YMM27*/ + xed3_operand_set_outreg(d, XED_REG_YMM27); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 4) -> REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 4) -> REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 4) -> REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_YMM20*/ + xed3_operand_set_outreg(d, XED_REG_YMM20); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 4) -> REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_YMM28*/ + xed3_operand_set_outreg(d, XED_REG_YMM28); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 0, 5) -> REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 0, 5) -> REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 1, 5) -> REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_YMM21*/ + xed3_operand_set_outreg(d, XED_REG_YMM21); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 1, 5) -> REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_YMM29*/ + xed3_operand_set_outreg(d, XED_REG_YMM29); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 6) -> REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 0, 6) -> REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 1, 6) -> REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_YMM22*/ + xed3_operand_set_outreg(d, XED_REG_YMM22); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 1, 6) -> REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_YMM30*/ + xed3_operand_set_outreg(d, XED_REG_YMM30); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 0, 7) -> REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 0, 7) -> REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 1, 7) -> REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_YMM23*/ + xed3_operand_set_outreg(d, XED_REG_YMM23); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 1, 7) -> REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_YMM31*/ + xed3_operand_set_outreg(d, XED_REG_YMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_B3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=ZMM_B3_32()*/ + xed3_capture_nt_ZMM_B3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=ZMM_B3_32()*/ + xed3_capture_nt_ZMM_B3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=ZMM_B3_64()*/ + xed3_capture_nt_ZMM_B3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_B3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rm(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> RM=0 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> RM=1 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> RM=2 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> RM=3 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> RM=4 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> RM=5 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> RM=6 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> RM=7 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_B3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rexx(d)) << ((1)); +key += (xed3_operand_get_rm(d)) << ((2)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> REXX=0 REXB=0 RM=0 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> REXX=0 REXB=1 RM=0 | OUTREG=XED_REG_ZMM8*/ + xed3_operand_set_outreg(d, XED_REG_ZMM8); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1, 0) -> REXX=1 REXB=0 RM=0 | OUTREG=XED_REG_ZMM16*/ + xed3_operand_set_outreg(d, XED_REG_ZMM16); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(1, 1, 0) -> REXX=1 REXB=1 RM=0 | OUTREG=XED_REG_ZMM24*/ + xed3_operand_set_outreg(d, XED_REG_ZMM24); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 0, 1) -> REXX=0 REXB=0 RM=1 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(1, 0, 1) -> REXX=0 REXB=1 RM=1 | OUTREG=XED_REG_ZMM9*/ + xed3_operand_set_outreg(d, XED_REG_ZMM9); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 1, 1) -> REXX=1 REXB=0 RM=1 | OUTREG=XED_REG_ZMM17*/ + xed3_operand_set_outreg(d, XED_REG_ZMM17); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(1, 1, 1) -> REXX=1 REXB=1 RM=1 | OUTREG=XED_REG_ZMM25*/ + xed3_operand_set_outreg(d, XED_REG_ZMM25); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 0, 2) -> REXX=0 REXB=0 RM=2 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 0, 2) -> REXX=0 REXB=1 RM=2 | OUTREG=XED_REG_ZMM10*/ + xed3_operand_set_outreg(d, XED_REG_ZMM10); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 1, 2) -> REXX=1 REXB=0 RM=2 | OUTREG=XED_REG_ZMM18*/ + xed3_operand_set_outreg(d, XED_REG_ZMM18); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(1, 1, 2) -> REXX=1 REXB=1 RM=2 | OUTREG=XED_REG_ZMM26*/ + xed3_operand_set_outreg(d, XED_REG_ZMM26); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 0, 3) -> REXX=0 REXB=0 RM=3 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(1, 0, 3) -> REXX=0 REXB=1 RM=3 | OUTREG=XED_REG_ZMM11*/ + xed3_operand_set_outreg(d, XED_REG_ZMM11); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 1, 3) -> REXX=1 REXB=0 RM=3 | OUTREG=XED_REG_ZMM19*/ + xed3_operand_set_outreg(d, XED_REG_ZMM19); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(1, 1, 3) -> REXX=1 REXB=1 RM=3 | OUTREG=XED_REG_ZMM27*/ + xed3_operand_set_outreg(d, XED_REG_ZMM27); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 4) -> REXX=0 REXB=0 RM=4 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 4) -> REXX=0 REXB=1 RM=4 | OUTREG=XED_REG_ZMM12*/ + xed3_operand_set_outreg(d, XED_REG_ZMM12); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(0, 1, 4) -> REXX=1 REXB=0 RM=4 | OUTREG=XED_REG_ZMM20*/ + xed3_operand_set_outreg(d, XED_REG_ZMM20); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(1, 1, 4) -> REXX=1 REXB=1 RM=4 | OUTREG=XED_REG_ZMM28*/ + xed3_operand_set_outreg(d, XED_REG_ZMM28); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(0, 0, 5) -> REXX=0 REXB=0 RM=5 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(1, 0, 5) -> REXX=0 REXB=1 RM=5 | OUTREG=XED_REG_ZMM13*/ + xed3_operand_set_outreg(d, XED_REG_ZMM13); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(0, 1, 5) -> REXX=1 REXB=0 RM=5 | OUTREG=XED_REG_ZMM21*/ + xed3_operand_set_outreg(d, XED_REG_ZMM21); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(1, 1, 5) -> REXX=1 REXB=1 RM=5 | OUTREG=XED_REG_ZMM29*/ + xed3_operand_set_outreg(d, XED_REG_ZMM29); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 0, 6) -> REXX=0 REXB=0 RM=6 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 0, 6) -> REXX=0 REXB=1 RM=6 | OUTREG=XED_REG_ZMM14*/ + xed3_operand_set_outreg(d, XED_REG_ZMM14); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(0, 1, 6) -> REXX=1 REXB=0 RM=6 | OUTREG=XED_REG_ZMM22*/ + xed3_operand_set_outreg(d, XED_REG_ZMM22); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(1, 1, 6) -> REXX=1 REXB=1 RM=6 | OUTREG=XED_REG_ZMM30*/ + xed3_operand_set_outreg(d, XED_REG_ZMM30); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(0, 0, 7) -> REXX=0 REXB=0 RM=7 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(1, 0, 7) -> REXX=0 REXB=1 RM=7 | OUTREG=XED_REG_ZMM15*/ + xed3_operand_set_outreg(d, XED_REG_ZMM15); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(0, 1, 7) -> REXX=1 REXB=0 RM=7 | OUTREG=XED_REG_ZMM23*/ + xed3_operand_set_outreg(d, XED_REG_ZMM23); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(1, 1, 7) -> REXX=1 REXB=1 RM=7 | OUTREG=XED_REG_ZMM31*/ + xed3_operand_set_outreg(d, XED_REG_ZMM31); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_N3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=XMM_N3_32()*/ + xed3_capture_nt_XMM_N3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=XMM_N3_32()*/ + xed3_capture_nt_XMM_N3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=XMM_N3_64()*/ + xed3_capture_nt_XMM_N3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_N3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=1 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=2 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=3 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=4 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=5 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=6 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=7 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_XMM_N3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM15*/ + xed3_operand_set_outreg(d, XED_REG_XMM15); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM14*/ + xed3_operand_set_outreg(d, XED_REG_XMM14); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM13*/ + xed3_operand_set_outreg(d, XED_REG_XMM13); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM12*/ + xed3_operand_set_outreg(d, XED_REG_XMM12); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM11*/ + xed3_operand_set_outreg(d, XED_REG_XMM11); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM10*/ + xed3_operand_set_outreg(d, XED_REG_XMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM9*/ + xed3_operand_set_outreg(d, XED_REG_XMM9); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM8*/ + xed3_operand_set_outreg(d, XED_REG_XMM8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM7*/ + xed3_operand_set_outreg(d, XED_REG_XMM7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM6*/ + xed3_operand_set_outreg(d, XED_REG_XMM6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM5*/ + xed3_operand_set_outreg(d, XED_REG_XMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM4*/ + xed3_operand_set_outreg(d, XED_REG_XMM4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM3*/ + xed3_operand_set_outreg(d, XED_REG_XMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM2*/ + xed3_operand_set_outreg(d, XED_REG_XMM2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM1*/ + xed3_operand_set_outreg(d, XED_REG_XMM1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM0*/ + xed3_operand_set_outreg(d, XED_REG_XMM0); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_XMM31*/ + xed3_operand_set_outreg(d, XED_REG_XMM31); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_XMM30*/ + xed3_operand_set_outreg(d, XED_REG_XMM30); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_XMM29*/ + xed3_operand_set_outreg(d, XED_REG_XMM29); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_XMM28*/ + xed3_operand_set_outreg(d, XED_REG_XMM28); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_XMM27*/ + xed3_operand_set_outreg(d, XED_REG_XMM27); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_XMM26*/ + xed3_operand_set_outreg(d, XED_REG_XMM26); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_XMM25*/ + xed3_operand_set_outreg(d, XED_REG_XMM25); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_XMM24*/ + xed3_operand_set_outreg(d, XED_REG_XMM24); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_XMM23*/ + xed3_operand_set_outreg(d, XED_REG_XMM23); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_XMM22*/ + xed3_operand_set_outreg(d, XED_REG_XMM22); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_XMM21*/ + xed3_operand_set_outreg(d, XED_REG_XMM21); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(3, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_XMM20*/ + xed3_operand_set_outreg(d, XED_REG_XMM20); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(4, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_XMM19*/ + xed3_operand_set_outreg(d, XED_REG_XMM19); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(5, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_XMM18*/ + xed3_operand_set_outreg(d, XED_REG_XMM18); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(6, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_XMM17*/ + xed3_operand_set_outreg(d, XED_REG_XMM17); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(7, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_XMM16*/ + xed3_operand_set_outreg(d, XED_REG_XMM16); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_N3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=YMM_N3_32()*/ + xed3_capture_nt_YMM_N3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=YMM_N3_32()*/ + xed3_capture_nt_YMM_N3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=YMM_N3_64()*/ + xed3_capture_nt_YMM_N3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_N3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=1 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=2 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=3 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=4 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=5 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=6 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=7 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_YMM_N3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM15*/ + xed3_operand_set_outreg(d, XED_REG_YMM15); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM14*/ + xed3_operand_set_outreg(d, XED_REG_YMM14); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM13*/ + xed3_operand_set_outreg(d, XED_REG_YMM13); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM12*/ + xed3_operand_set_outreg(d, XED_REG_YMM12); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM11*/ + xed3_operand_set_outreg(d, XED_REG_YMM11); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM10*/ + xed3_operand_set_outreg(d, XED_REG_YMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM9*/ + xed3_operand_set_outreg(d, XED_REG_YMM9); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM8*/ + xed3_operand_set_outreg(d, XED_REG_YMM8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM7*/ + xed3_operand_set_outreg(d, XED_REG_YMM7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM6*/ + xed3_operand_set_outreg(d, XED_REG_YMM6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM5*/ + xed3_operand_set_outreg(d, XED_REG_YMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM4*/ + xed3_operand_set_outreg(d, XED_REG_YMM4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM3*/ + xed3_operand_set_outreg(d, XED_REG_YMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM2*/ + xed3_operand_set_outreg(d, XED_REG_YMM2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM1*/ + xed3_operand_set_outreg(d, XED_REG_YMM1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM0*/ + xed3_operand_set_outreg(d, XED_REG_YMM0); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_YMM31*/ + xed3_operand_set_outreg(d, XED_REG_YMM31); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_YMM30*/ + xed3_operand_set_outreg(d, XED_REG_YMM30); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_YMM29*/ + xed3_operand_set_outreg(d, XED_REG_YMM29); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_YMM28*/ + xed3_operand_set_outreg(d, XED_REG_YMM28); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_YMM27*/ + xed3_operand_set_outreg(d, XED_REG_YMM27); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_YMM26*/ + xed3_operand_set_outreg(d, XED_REG_YMM26); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_YMM25*/ + xed3_operand_set_outreg(d, XED_REG_YMM25); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_YMM24*/ + xed3_operand_set_outreg(d, XED_REG_YMM24); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_YMM23*/ + xed3_operand_set_outreg(d, XED_REG_YMM23); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_YMM22*/ + xed3_operand_set_outreg(d, XED_REG_YMM22); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_YMM21*/ + xed3_operand_set_outreg(d, XED_REG_YMM21); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(3, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_YMM20*/ + xed3_operand_set_outreg(d, XED_REG_YMM20); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(4, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_YMM19*/ + xed3_operand_set_outreg(d, XED_REG_YMM19); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(5, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_YMM18*/ + xed3_operand_set_outreg(d, XED_REG_YMM18); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(6, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_YMM17*/ + xed3_operand_set_outreg(d, XED_REG_YMM17); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(7, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_YMM16*/ + xed3_operand_set_outreg(d, XED_REG_YMM16); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_N3(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> mode16 | OUTREG=ZMM_N3_32()*/ + xed3_capture_nt_ZMM_N3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> mode32 | OUTREG=ZMM_N3_32()*/ + xed3_capture_nt_ZMM_N3_32(d); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> mode64 | OUTREG=ZMM_N3_64()*/ + xed3_capture_nt_ZMM_N3_64(d); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_N3_32(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +/* now switch code..*/ +switch(key) { +case 0: /*(0,) -> VEXDEST210=0 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1,) -> VEXDEST210=1 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2,) -> VEXDEST210=2 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3,) -> VEXDEST210=3 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4,) -> VEXDEST210=4 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5,) -> VEXDEST210=5 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6,) -> VEXDEST210=6 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7,) -> VEXDEST210=7 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_ZMM_N3_64(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM15*/ + xed3_operand_set_outreg(d, XED_REG_ZMM15); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM14*/ + xed3_operand_set_outreg(d, XED_REG_ZMM14); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM13*/ + xed3_operand_set_outreg(d, XED_REG_ZMM13); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM12*/ + xed3_operand_set_outreg(d, XED_REG_ZMM12); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM11*/ + xed3_operand_set_outreg(d, XED_REG_ZMM11); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM10*/ + xed3_operand_set_outreg(d, XED_REG_ZMM10); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM9*/ + xed3_operand_set_outreg(d, XED_REG_ZMM9); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0, 0) -> VEXDEST4=0 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM8*/ + xed3_operand_set_outreg(d, XED_REG_ZMM8); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM7*/ + xed3_operand_set_outreg(d, XED_REG_ZMM7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM6*/ + xed3_operand_set_outreg(d, XED_REG_ZMM6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM5*/ + xed3_operand_set_outreg(d, XED_REG_ZMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM4*/ + xed3_operand_set_outreg(d, XED_REG_ZMM4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM3*/ + xed3_operand_set_outreg(d, XED_REG_ZMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM2*/ + xed3_operand_set_outreg(d, XED_REG_ZMM2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM1*/ + xed3_operand_set_outreg(d, XED_REG_ZMM1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1, 0) -> VEXDEST4=0 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM0*/ + xed3_operand_set_outreg(d, XED_REG_ZMM0); +/*pacify the compiler */ +(void)d; + break; +case 16: /*(0, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_ZMM31*/ + xed3_operand_set_outreg(d, XED_REG_ZMM31); +/*pacify the compiler */ +(void)d; + break; +case 17: /*(1, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_ZMM30*/ + xed3_operand_set_outreg(d, XED_REG_ZMM30); +/*pacify the compiler */ +(void)d; + break; +case 18: /*(2, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_ZMM29*/ + xed3_operand_set_outreg(d, XED_REG_ZMM29); +/*pacify the compiler */ +(void)d; + break; +case 19: /*(3, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_ZMM28*/ + xed3_operand_set_outreg(d, XED_REG_ZMM28); +/*pacify the compiler */ +(void)d; + break; +case 20: /*(4, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_ZMM27*/ + xed3_operand_set_outreg(d, XED_REG_ZMM27); +/*pacify the compiler */ +(void)d; + break; +case 21: /*(5, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_ZMM26*/ + xed3_operand_set_outreg(d, XED_REG_ZMM26); +/*pacify the compiler */ +(void)d; + break; +case 22: /*(6, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_ZMM25*/ + xed3_operand_set_outreg(d, XED_REG_ZMM25); +/*pacify the compiler */ +(void)d; + break; +case 23: /*(7, 0, 1) -> VEXDEST4=1 VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_ZMM24*/ + xed3_operand_set_outreg(d, XED_REG_ZMM24); +/*pacify the compiler */ +(void)d; + break; +case 24: /*(0, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_ZMM23*/ + xed3_operand_set_outreg(d, XED_REG_ZMM23); +/*pacify the compiler */ +(void)d; + break; +case 25: /*(1, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_ZMM22*/ + xed3_operand_set_outreg(d, XED_REG_ZMM22); +/*pacify the compiler */ +(void)d; + break; +case 26: /*(2, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_ZMM21*/ + xed3_operand_set_outreg(d, XED_REG_ZMM21); +/*pacify the compiler */ +(void)d; + break; +case 27: /*(3, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_ZMM20*/ + xed3_operand_set_outreg(d, XED_REG_ZMM20); +/*pacify the compiler */ +(void)d; + break; +case 28: /*(4, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_ZMM19*/ + xed3_operand_set_outreg(d, XED_REG_ZMM19); +/*pacify the compiler */ +(void)d; + break; +case 29: /*(5, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_ZMM18*/ + xed3_operand_set_outreg(d, XED_REG_ZMM18); +/*pacify the compiler */ +(void)d; + break; +case 30: /*(6, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_ZMM17*/ + xed3_operand_set_outreg(d, XED_REG_ZMM17); +/*pacify the compiler */ +(void)d; + break; +case 31: /*(7, 1, 1) -> VEXDEST4=1 VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_ZMM16*/ + xed3_operand_set_outreg(d, XED_REG_ZMM16); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_TMM_R(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_reg(d)) << ((0)); +key += (xed3_operand_get_rexr(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXR=0 REG=0 | OUTREG=XED_REG_TMM0*/ + xed3_operand_set_outreg(d, XED_REG_TMM0); +/*pacify the compiler */ +(void)d; + break; +case 1: /*(1, 0) -> REXR=0 REG=1 | OUTREG=XED_REG_TMM1*/ + xed3_operand_set_outreg(d, XED_REG_TMM1); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(2, 0) -> REXR=0 REG=2 | OUTREG=XED_REG_TMM2*/ + xed3_operand_set_outreg(d, XED_REG_TMM2); +/*pacify the compiler */ +(void)d; + break; +case 3: /*(3, 0) -> REXR=0 REG=3 | OUTREG=XED_REG_TMM3*/ + xed3_operand_set_outreg(d, XED_REG_TMM3); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(4, 0) -> REXR=0 REG=4 | OUTREG=XED_REG_TMM4*/ + xed3_operand_set_outreg(d, XED_REG_TMM4); +/*pacify the compiler */ +(void)d; + break; +case 5: /*(5, 0) -> REXR=0 REG=5 | OUTREG=XED_REG_TMM5*/ + xed3_operand_set_outreg(d, XED_REG_TMM5); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(6, 0) -> REXR=0 REG=6 | OUTREG=XED_REG_TMM6*/ + xed3_operand_set_outreg(d, XED_REG_TMM6); +/*pacify the compiler */ +(void)d; + break; +case 7: /*(7, 0) -> REXR=0 REG=7 | OUTREG=XED_REG_TMM7*/ + xed3_operand_set_outreg(d, XED_REG_TMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_TMM_B(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_rexb(d)) << ((0)); +key += (xed3_operand_get_rm(d)) << ((1)); +/* now switch code..*/ +switch(key) { +case 0: /*(0, 0) -> REXB=0 RM=0 | OUTREG=XED_REG_TMM0*/ + xed3_operand_set_outreg(d, XED_REG_TMM0); +/*pacify the compiler */ +(void)d; + break; +case 2: /*(0, 1) -> REXB=0 RM=1 | OUTREG=XED_REG_TMM1*/ + xed3_operand_set_outreg(d, XED_REG_TMM1); +/*pacify the compiler */ +(void)d; + break; +case 4: /*(0, 2) -> REXB=0 RM=2 | OUTREG=XED_REG_TMM2*/ + xed3_operand_set_outreg(d, XED_REG_TMM2); +/*pacify the compiler */ +(void)d; + break; +case 6: /*(0, 3) -> REXB=0 RM=3 | OUTREG=XED_REG_TMM3*/ + xed3_operand_set_outreg(d, XED_REG_TMM3); +/*pacify the compiler */ +(void)d; + break; +case 8: /*(0, 4) -> REXB=0 RM=4 | OUTREG=XED_REG_TMM4*/ + xed3_operand_set_outreg(d, XED_REG_TMM4); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(0, 5) -> REXB=0 RM=5 | OUTREG=XED_REG_TMM5*/ + xed3_operand_set_outreg(d, XED_REG_TMM5); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(0, 6) -> REXB=0 RM=6 | OUTREG=XED_REG_TMM6*/ + xed3_operand_set_outreg(d, XED_REG_TMM6); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(0, 7) -> REXB=0 RM=7 | OUTREG=XED_REG_TMM7*/ + xed3_operand_set_outreg(d, XED_REG_TMM7); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_TMM_N(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_vexdest210(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +/* now switch code..*/ +switch(key) { +case 8: /*(0, 1) -> VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_TMM7*/ + xed3_operand_set_outreg(d, XED_REG_TMM7); +/*pacify the compiler */ +(void)d; + break; +case 9: /*(1, 1) -> VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_TMM6*/ + xed3_operand_set_outreg(d, XED_REG_TMM6); +/*pacify the compiler */ +(void)d; + break; +case 10: /*(2, 1) -> VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_TMM5*/ + xed3_operand_set_outreg(d, XED_REG_TMM5); +/*pacify the compiler */ +(void)d; + break; +case 11: /*(3, 1) -> VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_TMM4*/ + xed3_operand_set_outreg(d, XED_REG_TMM4); +/*pacify the compiler */ +(void)d; + break; +case 12: /*(4, 1) -> VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_TMM3*/ + xed3_operand_set_outreg(d, XED_REG_TMM3); +/*pacify the compiler */ +(void)d; + break; +case 13: /*(5, 1) -> VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_TMM2*/ + xed3_operand_set_outreg(d, XED_REG_TMM2); +/*pacify the compiler */ +(void)d; + break; +case 14: /*(6, 1) -> VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_TMM1*/ + xed3_operand_set_outreg(d, XED_REG_TMM1); +/*pacify the compiler */ +(void)d; + break; +case 15: /*(7, 1) -> VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_TMM0*/ + xed3_operand_set_outreg(d, XED_REG_TMM0); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +static XED_INLINE void xed3_capture_nt_NELEM_QUARTER(xed_decoded_inst_t* d) +{ +xed_uint32_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_element_size(d)) << ((1)); +key += (xed3_operand_get_vl(d)) << ((10)); +/* now switch code..*/ +switch(key) { +case 32: /*(0, 16, 0) -> BCRC=0b0 ELEMENT_SIZE=16 VL128 | NELEM=2*/ + xed3_operand_set_nelem(d, 0x2); +/*pacify the compiler */ +(void)d; + break; +case 33: /*(1, 16, 0) -> BCRC=0b1 ELEMENT_SIZE=16 VL128 | NELEM=1 EMX_BROADCAST_1TO2_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x1a); +/*pacify the compiler */ +(void)d; + break; +case 1056: /*(0, 16, 1) -> BCRC=0b0 ELEMENT_SIZE=16 VL256 | NELEM=4*/ + xed3_operand_set_nelem(d, 0x4); +/*pacify the compiler */ +(void)d; + break; +case 1057: /*(1, 16, 1) -> BCRC=0b1 ELEMENT_SIZE=16 VL256 | NELEM=1 EMX_BROADCAST_1TO4_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0x1b); +/*pacify the compiler */ +(void)d; + break; +case 2080: /*(0, 16, 2) -> BCRC=0b0 ELEMENT_SIZE=16 VL512 | NELEM=8*/ + xed3_operand_set_nelem(d, 0x8); +/*pacify the compiler */ +(void)d; + break; +case 2081: /*(1, 16, 2) -> BCRC=0b1 ELEMENT_SIZE=16 VL512 | NELEM=1 EMX_BROADCAST_1TO8_16*/ + xed3_operand_set_nelem(d, 0x1); + xed3_operand_set_bcast(d, 0xe); +/*pacify the compiler */ +(void)d; + break; +default: + xed3_operand_set_error(d, XED_ERROR_GENERAL_ERROR); + break; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-op-chain-capture-lu.h b/CodeVirtualizer/build/obj/include-private/xed3-op-chain-capture-lu.h new file mode 100644 index 0000000..d3c1b3f --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-op-chain-capture-lu.h @@ -0,0 +1,46869 @@ +/// @file xed3-op-chain-capture-lu.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED3_OP_CHAIN_CAPTURE_LU_H) +# define XED3_OP_CHAIN_CAPTURE_LU_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-op-chain-capture.h" +typedef xed_error_enum_t(*xed3_op_chain_function_t)(xed_decoded_inst_t*); +static xed3_op_chain_function_t xed3_op_chain_fptr_lu[7614] = { +/*NO PATTERN*/ (xed3_op_chain_function_t)0, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=1*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=2*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=3*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=4*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=5*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=6*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=7*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=8*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=9*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=10*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=11*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=12*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=13*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=14*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=15*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=16*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=17*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=18*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=19*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=20*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=21*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=22*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=23*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=24*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=25*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=26*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=27*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=28*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=29*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=30*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=31*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=32*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=33*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32real f32 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=34*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=35*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87PUSH_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem80real f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=36*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64real f64 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=37*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem32real f32 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=38*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT m64real f64 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=39*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn w EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=40*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem32real f32 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=41*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem80real f80 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=42*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT m64real f64 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=43*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn w EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=44*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn w EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=45*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn w EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=46*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn w EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=47*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem14 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=48*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem14 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=49*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem14 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=50*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=51*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=52*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=53*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=54*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] r EXPLICIT mem16 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=55*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem14 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=56*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem14 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=57*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem14 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=58*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=59*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=60*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=61*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem28 struct + REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=62*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem16 struct + REG0 reg [XED_REG_X87CONTROL] r SUPPRESSED INVALID + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=63*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=64*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=65*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + REG1 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=66*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=67*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=68*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=69*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=70*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=71*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=72*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=73*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=74*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=75*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=76*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=77*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=78*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=79*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] rw SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=80*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] w SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=81*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] rw SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=82*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] w SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=83*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] r SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=84*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=85*/ xed3_capture_chain_ntluf_REG0_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=86*/ xed3_capture_chain_ntluf_REG0_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] r SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=87*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] rw SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=88*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=89*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] w SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=90*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=91*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] r SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=92*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=93*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw SUPPRESSED f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=94*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=95*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=96*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=97*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=98*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=99*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=100*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=101*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=102*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=103*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=104*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=105*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=106*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=107*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=108*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=109*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] rw IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=110*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=111*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=112*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=113*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=114*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] r SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] r SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87POP2] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=115*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP2_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem32int i32 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=116*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem16int i16 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=117*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT m64int i64 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=118*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem32int i32 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=119*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT m64int i64 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=120*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem16int i16 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=121*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem32int i32 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=122*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem16int i16 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=123*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem32int i32 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=124*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem16int i16 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=125*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT m64int i64 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=126*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=127*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=128*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=129*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] cw IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=130*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=131*/ xed3_capture_chain_ntluf_REG0_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] w SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=132*/ xed3_capture_chain_ntluf_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG2_XED_REG_X87STATUS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=133*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=134*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=135*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=136*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=137*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT mem94 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=138*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mem94 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=139*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mem94 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=140*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=141*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=142*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=143*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=144*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] w EXPLICIT mem94 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=145*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem94 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=146*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem94 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=147*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=148*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=149*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=150*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem108 struct + REG0 reg [XED_REG_X87CONTROL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_X87TAG] rw SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=151*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem16 struct + REG0 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=152*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_AX] w IMPLICIT INVALID + REG1 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=153*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_X87TAG] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=154*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_X87TAG, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=155*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=156*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=157*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=158*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] r SUPPRESSED f80 f80 + REG1 reg [XED_REG_ST1] r SUPPRESSED f80 f80 + REG2 reg [XED_REG_X87POP2] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=159*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP2_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=160*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=161*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=162*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn rw EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=163*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS, +/* REG0 reg [XED_REG_ST0] w IMPLICIT f80 f80 + MEM0 imm_const [1] r EXPLICIT mem80dec b80 + REG1 reg [XED_REG_X87PUSH] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=164*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS, +/* MEM0 imm_const [1] w EXPLICIT mem80dec b80 + REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG2 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=165*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS, +/* REG0 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG1 reg [XED_REG_X87TAG] w SUPPRESSED INVALID + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=166*/ xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_X87TAG_REG2_XED_REG_X87POP, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=167*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS_REG4_rFLAGS, +/* REG0 reg [XED_REG_ST0] r IMPLICIT f80 f80 + REG1 nt_lookup_fn r EXPLICIT X87 f80 f80 + REG2 reg [XED_REG_X87POP] r SUPPRESSED INVALID + REG3 reg [XED_REG_X87STATUS] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=168*/ xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS_REG4_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=169*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=170*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=171*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=172*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=173*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=174*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=175*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=176*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=177*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=178*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=179*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=180*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=181*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=182*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=183*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=184*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=185*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=186*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=187*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=188*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=189*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=190*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=191*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=192*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=193*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=194*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=195*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=196*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=197*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=198*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=199*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=200*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=201*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=202*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=203*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=204*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=205*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=206*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=207*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=208*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=209*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=210*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=211*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=212*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=213*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=214*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=215*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=216*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=217*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=218*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=219*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=220*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=221*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=222*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=223*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=224*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=225*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=226*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=227*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=228*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=229*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=230*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=231*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=232*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=233*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=234*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=235*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=236*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=237*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=238*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=239*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=240*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=241*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=242*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=243*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=244*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=245*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=246*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=247*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=248*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=249*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=250*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=251*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=252*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=253*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=254*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=255*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=256*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=257*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=258*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=259*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=260*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=261*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=262*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=263*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=264*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=265*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=266*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=267*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=268*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=269*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=270*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=271*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=272*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=273*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=274*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=275*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=276*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=277*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=278*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=279*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=280*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=281*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=282*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=283*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=284*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=285*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=286*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=287*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=288*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=289*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=290*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=291*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=292*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=293*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=294*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=295*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=296*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=297*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=298*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=299*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=300*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=301*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=302*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=303*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=304*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=305*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=306*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=307*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=308*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=309*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=310*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=311*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=312*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=313*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=314*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=315*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=316*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=317*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=318*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=319*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=320*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=321*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=322*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=323*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=324*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=325*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=326*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=327*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=328*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=329*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=330*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=331*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=332*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=333*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=334*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] rw IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=335*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=336*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=337*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=338*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=339*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=340*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=341*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=342*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=343*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=344*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=345*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=346*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=347*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=348*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=349*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=350*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=351*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=352*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] r IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=353*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=354*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT v int + REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM1 imm_const [1] r SUPPRESSED spw int + BASE1 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_SSEG1 INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=355*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPOP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=356*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_ES] w IMPLICIT INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=357*/ xed3_capture_chain_ntluf_REG0_XED_REG_ES_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_SS] w IMPLICIT INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=358*/ xed3_capture_chain_ntluf_REG0_XED_REG_SS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_DS] w IMPLICIT INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=359*/ xed3_capture_chain_ntluf_REG0_XED_REG_DS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_SB INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=360*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_FS] w IMPLICIT INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=361*/ xed3_capture_chain_ntluf_REG0_XED_REG_FS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_GS] w IMPLICIT INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=362*/ xed3_capture_chain_ntluf_REG0_XED_REG_GS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=363*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=364*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=365*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=366*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=367*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=368*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=369*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=370*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=371*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=372*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=373*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=374*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=375*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=376*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=377*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=378*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=379*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=380*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=381*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=382*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=383*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=384*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=385*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=386*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=387*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=388*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=389*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=390*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=391*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=392*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=393*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=394*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=395*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=396*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=397*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=398*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=399*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=400*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=401*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=402*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=403*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=404*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=405*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=406*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=407*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=408*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=409*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=410*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=411*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=412*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=413*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=414*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=415*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=416*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=417*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=418*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=419*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=420*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=421*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=422*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=423*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=424*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=425*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=426*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=427*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=428*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=429*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=430*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=431*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=432*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=433*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=434*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=435*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=436*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=437*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=438*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=439*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=440*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=441*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=442*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=443*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=444*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=445*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=446*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=447*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=448*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=449*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=450*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=451*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=452*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=453*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r IMPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=454*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=455*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=456*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=457*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=458*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=459*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=460*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=461*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=462*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=463*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=464*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=465*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=466*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=467*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=468*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=469*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=470*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] r IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=471*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r IMPLICIT OrAX INVALID + IMM0 imm_const [1] r EXPLICIT z int + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=472*/ xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=473*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=474*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=475*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=476*/ xed3_capture_chain_ntluf_REG0_GPR8_B, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=477*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=478*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=479*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=480*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=481*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=482*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=483*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=484*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + REG1 reg [XED_REG_AX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=485*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_AL] r SUPPRESSED INVALID + REG2 reg [XED_REG_AX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=486*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AL_REG2_XED_REG_AX_REG3_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG1 nt_lookup_fn w SUPPRESSED OrDX INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=487*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_REG1_OrDX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG2 nt_lookup_fn w SUPPRESSED OrDX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=488*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_OrAX_REG2_OrDX_REG3_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + REG1 reg [XED_REG_AX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=489*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_AL] r SUPPRESSED INVALID + REG2 reg [XED_REG_AX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=490*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AL_REG2_XED_REG_AX_REG3_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG1 nt_lookup_fn w SUPPRESSED OrDX INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=491*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_REG1_OrDX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG2 nt_lookup_fn w SUPPRESSED OrDX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=492*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_OrAX_REG2_OrDX_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=493*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=494*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_IMM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=495*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=496*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_IMM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=497*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=498*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_AX] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=499*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AX_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_AX] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=500*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AX_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrDX INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=501*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_REG1_OrDX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG2 nt_lookup_fn rw SUPPRESSED OrDX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=502*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_OrAX_REG2_OrDX_REG3_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_AX] rw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=503*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AX_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR8_B INVALID + REG1 reg [XED_REG_AX] rw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=504*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AX_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrDX INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=505*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_REG1_OrDX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrAX INVALID + REG2 nt_lookup_fn rw SUPPRESSED OrDX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=506*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_OrAX_REG2_OrDX_REG3_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=507*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=508*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=509*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=510*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=511*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=512*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_SB INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=513*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=514*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=515*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=516*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=517*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=518*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=519*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_SB INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=520*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + MEM1 imm_const [1] w SUPPRESSED spw int + BASE1 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_SSEG1 INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=521*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_REG1_rIP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + REG2 nt_lookup_fn rw SUPPRESSED rIP INVALID + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=522*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPUSH_REG2_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + REG1 reg [XED_REG_EIP] rw SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=523*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + REG1 reg [XED_REG_RIP] rw SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=524*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_RIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=525*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rIP, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=526*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rIP, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID inum=527*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID inum=528*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID inum=529*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID inum=530*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP, +/* MEM0 imm_const [1] r EXPLICIT p2 struct + REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=531*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rIP, +/* PTR imm_const [1] r EXPLICIT p struct + IMM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_EIP] w SUPPRESSED INVALID inum=532*/ xed3_capture_chain_ntluf_PTR_const1_IMM0_const1_REG0_XED_REG_EIP, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM1 imm_const [1] w SUPPRESSED spw int + BASE1 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_SSEG1 INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=533*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=534*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_ES] r IMPLICIT INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=535*/ xed3_capture_chain_ntluf_REG0_XED_REG_ES_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_CS] r IMPLICIT INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=536*/ xed3_capture_chain_ntluf_REG0_XED_REG_CS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_SS] r IMPLICIT INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=537*/ xed3_capture_chain_ntluf_REG0_XED_REG_SS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_DS] r IMPLICIT INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=538*/ xed3_capture_chain_ntluf_REG0_XED_REG_DS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_SB INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=539*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* IMM0 imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=540*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* IMM0 imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=541*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_FS] r IMPLICIT INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=542*/ xed3_capture_chain_ntluf_REG0_XED_REG_FS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_GS] r IMPLICIT INVALID + REG1 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=543*/ xed3_capture_chain_ntluf_REG0_XED_REG_GS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* MEM0 imm_const [1] w EXPLICIT w i16 + REG0 reg [XED_REG_LDTR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=544*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_LDTR, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_LDTR] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=545*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_LDTR, +/* MEM0 imm_const [1] w EXPLICIT w i16 + REG0 reg [XED_REG_TR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=546*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_TR, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_TR] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=547*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_TR, +/* MEM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_LDTR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=548*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_LDTR, +/* REG0 nt_lookup_fn r EXPLICIT GPR16_B INVALID + REG1 reg [XED_REG_LDTR] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=549*/ xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_LDTR, +/* MEM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_TR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=550*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_TR, +/* REG0 nt_lookup_fn r EXPLICIT GPR16_B INVALID + REG1 reg [XED_REG_TR] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=551*/ xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_TR, +/* MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=552*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR16_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=553*/ xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=554*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR16_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=555*/ xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT s64 struct + REG0 reg [XED_REG_GDTR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=556*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_GDTR, +/* MEM0 imm_const [1] r EXPLICIT s struct + REG0 reg [XED_REG_GDTR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=557*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_GDTR, +/* MEM0 imm_const [1] w EXPLICIT w i16 + REG0 reg [XED_REG_CR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=558*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CR0, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + REG1 reg [XED_REG_CR0] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=559*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CR0, +/* MEM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_CR0] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=560*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CR0, +/* REG0 nt_lookup_fn r EXPLICIT GPR16_B INVALID + REG1 reg [XED_REG_CR0] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=561*/ xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_CR0, +/* MEM0 imm_const [1] r EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=562*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=563*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=564*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=565*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=566*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=567*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=568*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=569*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=570*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=571*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=572*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=573*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=574*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=575*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=576*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=577*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=578*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=579*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=580*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=581*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=582*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=583*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=584*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=585*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=586*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=587*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT q i64 + REG0 reg [XED_REG_EDX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] rcw SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EBX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=588*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EBX_REG4_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT q i64 + REG0 reg [XED_REG_EDX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] rcw SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EBX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=589*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EBX_REG4_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT q i64 + REG0 reg [XED_REG_EDX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] rcw SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EBX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=590*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EBX_REG4_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT q i64 + REG0 reg [XED_REG_EDX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] rcw SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EBX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=591*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EBX_REG4_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT dq i32 + REG0 reg [XED_REG_RDX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_RAX] rcw SUPPRESSED INVALID + REG2 reg [XED_REG_RCX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RBX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=592*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_RDX_REG1_XED_REG_RAX_REG2_XED_REG_RCX_REG3_XED_REG_RBX_REG4_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT dq i32 + REG0 reg [XED_REG_RDX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_RAX] rcw SUPPRESSED INVALID + REG2 reg [XED_REG_RCX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RBX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=593*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_RDX_REG1_XED_REG_RAX_REG2_XED_REG_RCX_REG3_XED_REG_RBX_REG4_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=594*/ xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=595*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + IMM0 imm_const [1] r EXPLICIT z int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=596*/ xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT v int + IMM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=597*/ xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=598*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R, +/* MEM0 imm_const [1] w EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=599*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R, +/* MEM0 imm_const [1] w EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=600*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=601*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=602*/ xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=603*/ xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=604*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=605*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B, +/* MEM0 imm_const [1] w EXPLICIT w i16 + REG0 nt_lookup_fn r EXPLICIT SEG INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=606*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_SEG, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT SEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=607*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_SEG, +/* REG0 nt_lookup_fn w EXPLICIT SEG_MOV INVALID + MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=608*/ xed3_capture_chain_ntluf_REG0_SEG_MOV_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT SEG_MOV INVALID + REG1 nt_lookup_fn r EXPLICIT GPR16_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=609*/ xed3_capture_chain_ntluf_REG0_SEG_MOV_REG1_GPR16_B, +/* REG0 reg [XED_REG_AL] w IMPLICIT INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID inum=610*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_SEG0_FINAL_DSEG, +/* REG0 nt_lookup_fn w IMPLICIT OrAX INVALID + MEM0 imm_const [1] r EXPLICIT v int + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID inum=611*/ xed3_capture_chain_ntluf_REG0_OrAX_MEM0_const1_SEG0_FINAL_DSEG, +/* MEM0 imm_const [1] w EXPLICIT b u8 + REG0 reg [XED_REG_AL] r IMPLICIT INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID inum=612*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_SEG0_FINAL_DSEG, +/* MEM0 imm_const [1] w EXPLICIT v int + REG0 nt_lookup_fn r IMPLICIT OrAX INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID inum=613*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_SEG0_FINAL_DSEG, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_SB INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=614*/ xed3_capture_chain_ntluf_REG0_GPR8_SB_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_SB INVALID + IMM0 imm_const [1] r EXPLICIT v int + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=615*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=616*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=617*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=618*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=619*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=620*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=621*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=622*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=623*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=624*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=625*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=626*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=627*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=628*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=629*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=630*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=631*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=632*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=633*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=634*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=635*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=636*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=637*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=638*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=639*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=640*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=641*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=642*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=643*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=644*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=645*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=646*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=647*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=648*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=649*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=650*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=651*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=652*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=653*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=654*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=655*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=656*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=657*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_B q u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=658*/ xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=659*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=660*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=661*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=662*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=663*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=664*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_B dq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=665*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT mfpxenv struct + REG0 reg [XED_REG_X87CONTROL] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=666*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mfpxenv struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=667*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] w EXPLICIT mfpxenv struct + REG0 reg [XED_REG_X87CONTROL] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=668*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT mfpxenv struct + REG0 reg [XED_REG_X87CONTROL] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=669*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL, +/* MEM0 imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_MXCSR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=670*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_MXCSR, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 reg [XED_REG_MXCSR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=671*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_MXCSR, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=672*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=673*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=674*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=675*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=676*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=677*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=678*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=679*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=680*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=681*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=682*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=683*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=684*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=685*/ xed3_capture_chain_ntluf_REG0_GPRv_B, +/* MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=686*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=687*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=688*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=689*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=690*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=691*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=692*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=693*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* SRM imm 000 (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=694*/ xed3_capture_nt_nop_ntluf, +/* SRM imm 000 (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=695*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=696*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=697*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=698*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=699*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=700*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=701*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=702*/ xed3_capture_chain_ntluf_REG0_GPRv_B_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=703*/ xed3_capture_chain_ntluf_REG0_GPRv_B_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=704*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=705*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=706*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=707*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=708*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=709*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=710*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=711*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=712*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=713*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=714*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=715*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=716*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=717*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=718*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=719*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=720*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=721*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=722*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=723*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=724*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=725*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=726*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=727*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=728*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=729*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=730*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=731*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=732*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=733*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=734*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* MEM0 imm_const [1] r EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=735*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=736*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=737*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=738*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=739*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT s64 struct + REG0 reg [XED_REG_GDTR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=740*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_GDTR, +/* MEM0 imm_const [1] w EXPLICIT s struct + REG0 reg [XED_REG_GDTR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=741*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_GDTR, +/* MEM0 imm_const [1] r EXPLICIT s64 struct + REG0 reg [XED_REG_IDTR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=742*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_IDTR, +/* MEM0 imm_const [1] r EXPLICIT s struct + REG0 reg [XED_REG_IDTR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=743*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_IDTR, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=744*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=745*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=746*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=747*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=748*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX, +/* MEM0 imm_const [1] w EXPLICIT s struct + REG0 reg [XED_REG_IDTR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=749*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_IDTR, +/* MEM0 imm_const [1] w EXPLICIT s64 struct + REG0 reg [XED_REG_IDTR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=750*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_IDTR, +/* MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=751*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=752*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + REG3 reg [XED_REG_TSC] r SUPPRESSED INVALID + REG4 reg [XED_REG_TSCAUX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=753*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_TSC_REG4_XED_REG_TSCAUX, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=754*/ xed3_capture_nt_nop_ntluf, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=755*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=756*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=757*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=758*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q f32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=759*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=760*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=761*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q f32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=762*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=763*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 reg [XED_REG_AL] rw SUPPRESSED INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=764*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] rw SUPPRESSED INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=765*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_AH] rw SUPPRESSED INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=766*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_AH] rw SUPPRESSED INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=767*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw8 int + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID + REG2 reg [XED_REG_CX] r SUPPRESSED INVALID + REG3 reg [XED_REG_DX] r SUPPRESSED INVALID + REG4 reg [XED_REG_BX] r SUPPRESSED INVALID + REG5 reg [XED_REG_SP] r SUPPRESSED INVALID + REG6 reg [XED_REG_BP] r SUPPRESSED INVALID + REG7 reg [XED_REG_SI] r SUPPRESSED INVALID + REG8 reg [XED_REG_DI] r SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=768*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_SP_REG6_XED_REG_BP_REG7_XED_REG_SI_REG8_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw8 int + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID + REG2 reg [XED_REG_CX] r SUPPRESSED INVALID + REG3 reg [XED_REG_DX] r SUPPRESSED INVALID + REG4 reg [XED_REG_BX] r SUPPRESSED INVALID + REG5 reg [XED_REG_SP] r SUPPRESSED INVALID + REG6 reg [XED_REG_BP] r SUPPRESSED INVALID + REG7 reg [XED_REG_SI] r SUPPRESSED INVALID + REG8 reg [XED_REG_DI] r SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=769*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_SP_REG6_XED_REG_BP_REG7_XED_REG_SI_REG8_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw8 int + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_EBX] r SUPPRESSED INVALID + REG5 reg [XED_REG_ESP] r SUPPRESSED INVALID + REG6 reg [XED_REG_EBP] r SUPPRESSED INVALID + REG7 reg [XED_REG_ESI] r SUPPRESSED INVALID + REG8 reg [XED_REG_EDI] r SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=770*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_ESP_REG6_XED_REG_EBP_REG7_XED_REG_ESI_REG8_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw8 int + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_EBX] r SUPPRESSED INVALID + REG5 reg [XED_REG_ESP] r SUPPRESSED INVALID + REG6 reg [XED_REG_EBP] r SUPPRESSED INVALID + REG7 reg [XED_REG_ESI] r SUPPRESSED INVALID + REG8 reg [XED_REG_EDI] r SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=771*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_ESP_REG6_XED_REG_EBP_REG7_XED_REG_ESI_REG8_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw8 int + REG1 reg [XED_REG_AX] w SUPPRESSED INVALID + REG2 reg [XED_REG_CX] w SUPPRESSED INVALID + REG3 reg [XED_REG_DX] w SUPPRESSED INVALID + REG4 reg [XED_REG_BX] w SUPPRESSED INVALID + REG5 reg [XED_REG_BP] w SUPPRESSED INVALID + REG6 reg [XED_REG_SI] w SUPPRESSED INVALID + REG7 reg [XED_REG_DI] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=772*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_BP_REG6_XED_REG_SI_REG7_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw8 int + REG1 reg [XED_REG_AX] w SUPPRESSED INVALID + REG2 reg [XED_REG_CX] w SUPPRESSED INVALID + REG3 reg [XED_REG_DX] w SUPPRESSED INVALID + REG4 reg [XED_REG_BX] w SUPPRESSED INVALID + REG5 reg [XED_REG_BP] w SUPPRESSED INVALID + REG6 reg [XED_REG_SI] w SUPPRESSED INVALID + REG7 reg [XED_REG_DI] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=773*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_BP_REG6_XED_REG_SI_REG7_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw8 int + REG1 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG4 reg [XED_REG_EBX] w SUPPRESSED INVALID + REG5 reg [XED_REG_EBP] w SUPPRESSED INVALID + REG6 reg [XED_REG_ESI] w SUPPRESSED INVALID + REG7 reg [XED_REG_EDI] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=774*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_EBP_REG6_XED_REG_ESI_REG7_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw8 int + REG1 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG4 reg [XED_REG_EBX] w SUPPRESSED INVALID + REG5 reg [XED_REG_EBP] w SUPPRESSED INVALID + REG6 reg [XED_REG_ESI] w SUPPRESSED INVALID + REG7 reg [XED_REG_EDI] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED spw8 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=775*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_EBP_REG6_XED_REG_ESI_REG7_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT a16 i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 10, 11 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 13, 14, 15 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 16, 17, 18 inum=776*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT a16 i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 10, 11 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 13, 14, 15 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 16, 17, 18 inum=777*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT a32 i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 10, 11 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 13, 14, 15 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 16, 17, 18 inum=778*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT a32 i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 10, 11 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 13, 14, 15 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 16, 17, 18 inum=779*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* MEM0 imm_const [1] rw EXPLICIT w i16 + REG0 nt_lookup_fn r EXPLICIT GPR16_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=780*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR16_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR16_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR16_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=781*/ xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_GPR16_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT z int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=782*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRz_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=783*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRz_B, +/* MEM0 imm_const [1] cw SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=784*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=785*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=786*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=787*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=788*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=789*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=790*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=791*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=792*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=793*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=794*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=795*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=796*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=797*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=798*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=799*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=800*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=801*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=802*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=803*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=804*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=805*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=806*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=807*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=808*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=809*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=810*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=811*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=812*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=813*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=814*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=815*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=816*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=817*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=818*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=819*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=820*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=821*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=822*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=823*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=824*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=825*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=826*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=827*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=828*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=829*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=830*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=831*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=832*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=833*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=834*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=835*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=836*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=837*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=838*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=839*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=840*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=841*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=842*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=843*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=844*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=845*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=846*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=847*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=848*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=849*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=850*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=851*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=852*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=853*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=854*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=855*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=856*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=857*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=858*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=859*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=860*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=861*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=862*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=863*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=864*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=865*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=866*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=867*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=868*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=869*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=870*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=871*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=872*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=873*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=874*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=875*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=876*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=877*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=878*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=879*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=880*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=881*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=882*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=883*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=884*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=885*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=886*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=887*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=888*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=889*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=890*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=891*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=892*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=893*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 reg [XED_REG_EIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=894*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_RIP] rw SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=895*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=896*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=897*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=898*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=899*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=900*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=901*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_SB INVALID + REG1 nt_lookup_fn rw IMPLICIT OrAX INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=902*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_OrAX, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_SB INVALID + REG1 nt_lookup_fn rw IMPLICIT OrAX INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=903*/ xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_OrAX, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + AGEN imm_const [1] r EXPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=904*/ xed3_capture_chain_ntluf_REG0_GPRv_R_AGEN_const1, +/* SRM imm 000 (L) r SUPPRESSED i3 bitpos: 5, 6, 7 inum=905*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_AX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AL] r SUPPRESSED INVALID inum=906*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_AL, +/* REG0 reg [XED_REG_AX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AL] r SUPPRESSED INVALID inum=907*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_AL, +/* REG0 reg [XED_REG_AX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AL] r SUPPRESSED INVALID inum=908*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_AL, +/* REG0 reg [XED_REG_RAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID inum=909*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_EAX, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID inum=910*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_AX, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID inum=911*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_AX, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID inum=912*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_AX, +/* REG0 reg [XED_REG_DX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID inum=913*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AX, +/* REG0 reg [XED_REG_DX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID inum=914*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AX, +/* REG0 reg [XED_REG_DX] w SUPPRESSED INVALID + REG1 reg [XED_REG_AX] r SUPPRESSED INVALID inum=915*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AX, +/* REG0 reg [XED_REG_RDX] w SUPPRESSED INVALID + REG1 reg [XED_REG_RAX] r SUPPRESSED INVALID inum=916*/ xed3_capture_chain_ntluf_REG0_XED_REG_RDX_REG1_XED_REG_RAX, +/* REG0 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID inum=917*/ xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX, +/* REG0 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID inum=918*/ xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX, +/* REG0 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID inum=919*/ xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX, +/* MEM0 imm_const [1] r EXPLICIT p2 struct + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw2 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM1 imm_const [1] w SUPPRESSED spw2 int + BASE1 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_SSEG1 INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=920*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_REG1_rIP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1, +/* PTR imm_const [1] r EXPLICIT p struct + IMM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw2 int + REG1 reg [XED_REG_EIP] w SUPPRESSED INVALID + MEM0 imm_const [1] w SUPPRESSED spw2 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=921*/ xed3_capture_chain_ntluf_PTR_const1_IMM0_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* inum=922*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED w i16 + MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=923*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED w i16 + MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=924*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED w i16 + MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=925*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED d i32 + MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=926*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED d i32 + MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=927*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED q i64 + MEM0 imm_const [1] w SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=928*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED q i64 + MEM0 imm_const [1] w SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=929*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED w i16 + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=930*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED w i16 + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=931*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED w i16 + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=932*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED d i32 + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=933*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED d i32 + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=934*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED q i64 + MEM0 imm_const [1] r SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=935*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED q i64 + MEM0 imm_const [1] r SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=936*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS, +/* REG0 reg [XED_REG_AH] r SUPPRESSED INVALID + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=937*/ xed3_capture_chain_ntluf_REG0_XED_REG_AH_REG1_rFLAGS, +/* REG0 reg [XED_REG_AH] w SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=938*/ xed3_capture_chain_ntluf_REG0_XED_REG_AH_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=939*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=940*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED b u8 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=941*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=942*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=943*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=944*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=945*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=946*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=947*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED w i16 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=948*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED w i16 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=949*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED w i16 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=950*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=951*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=952*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=953*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=954*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=955*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=956*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED d i32 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=957*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED d i32 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=958*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED d i32 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=959*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED q i64 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=960*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED q i64 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=961*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED q i64 + BASE1 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=962*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=963*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=964*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED b u8 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=965*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=966*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=967*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=968*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=969*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=970*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED w i16 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=971*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED w i16 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=972*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED w i16 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=973*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED w i16 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=974*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=975*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=976*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=977*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=978*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=979*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED d i32 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=980*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED d i32 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=981*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED d i32 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=982*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED d i32 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=983*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED q i64 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=984*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] cr SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] cr SUPPRESSED q i64 + BASE1 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=985*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MEM1 imm_const [1] r SUPPRESSED q i64 + BASE1 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=986*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=987*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=988*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=989*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=990*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=991*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=992*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=993*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=994*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=995*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=996*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=997*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=998*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=999*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1000*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1001*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1002*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1003*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1004*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1005*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1006*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1007*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1008*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] cw SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1009*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_ArCX_REG2_rFLAGS, +/* MEM0 imm_const [1] w SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1010*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1011*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1012*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1013*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1014*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1015*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1016*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1017*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1018*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1019*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1020*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1021*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1022*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1023*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1024*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1025*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1026*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1027*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1028*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1029*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1030*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1031*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_RAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1032*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_RAX] cw SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1033*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_RAX] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1034*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1035*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED b u8 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1036*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1037*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1038*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1039*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1040*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1041*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1042*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED w i16 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1043*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1044*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1045*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED w i16 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1046*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1047*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1048*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1049*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1050*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1051*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED d i32 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1052*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1053*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1054*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED d i32 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1055*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1056*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + MEM0 imm_const [1] cr SUPPRESSED q i64 + BASE0 nt_lookup_fn rcw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rcw SUPPRESSED ArCX INVALID + REG2 nt_lookup_fn rcw SUPPRESSED rFLAGS INVALID inum=1057*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED q i64 + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1058*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=1059*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=1060*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 nt_lookup_fn w EXPLICIT GPRz_R INVALID + MEM0 imm_const [1] r EXPLICIT p struct + REG1 reg [XED_REG_ES] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=1061*/ xed3_capture_chain_ntluf_REG0_GPRz_R_MEM0_const1_REG1_XED_REG_ES, +/* REG0 nt_lookup_fn w EXPLICIT GPRz_R INVALID + MEM0 imm_const [1] r EXPLICIT p struct + REG1 reg [XED_REG_DS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=1062*/ xed3_capture_chain_ntluf_REG0_GPRz_R_MEM0_const1_REG1_XED_REG_DS, +/* IMM0 imm_const [1] r EXPLICIT w i16 + IMM1 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_STACKPUSH] w SUPPRESSED spw int + REG1 nt_lookup_fn rw SUPPRESSED OrBP INVALID + MEM0 imm_const [1] w SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=1063*/ xed3_capture_chain_ntluf_IMM0_const1_IMM1_const1_REG0_XED_REG_STACKPUSH_REG1_OrBP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* MEM0 imm_const [1] r SUPPRESSED v int + BASE0 nt_lookup_fn r SUPPRESSED ArBP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG0 nt_lookup_fn rw SUPPRESSED OrBP INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrSP INVALID inum=1064*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArBP_SEG0_FINAL_SSEG0_REG0_OrBP_REG1_OrSP, +/* IMM0 imm_const [1] r EXPLICIT w i16 + REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw2 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw2 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=1065*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw2 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw2 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID inum=1066*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0, +/* REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1067*/ xed3_capture_chain_ntluf_REG0_rIP_REG1_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT b u8 + REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1068*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_rIP_REG1_rFLAGS, +/* REG0 reg [XED_REG_EIP] w SUPPRESSED INVALID + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1069*/ xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1070*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1071*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1072*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1073*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1074*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 nt_lookup_fn w SUPPRESSED rIP INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1075*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 reg [XED_REG_STACKPOP] r SUPPRESSED spw5 int + REG1 reg [XED_REG_RIP] w SUPPRESSED INVALID + MEM0 imm_const [1] r SUPPRESSED spw5 int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1076*/ xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_RIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_AL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_AH] w SUPPRESSED INVALID + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1077*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_AL] rw SUPPRESSED INVALID + REG1 reg [XED_REG_AH] rw SUPPRESSED INVALID + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1078*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS, +/* REG0 reg [XED_REG_AL] w SUPPRESSED INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1079*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_rFLAGS, +/* MEM0 imm_const [1] r SUPPRESSED b u8 + BASE0 nt_lookup_fn r SUPPRESSED ArBX INVALID + INDEX reg [XED_REG_AL] r SUPPRESSED INVALID + REG0 reg [XED_REG_AL] w SUPPRESSED INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + SCALE imm_const [0x1] r SUPPRESSED INVALID inum=1080*/ xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArBX_INDEX_XED_REG_AL_REG0_XED_REG_AL_SEG0_FINAL_DSEG_SCALE_const0x1, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1081*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1082*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1083*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1084*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1085*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1086*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1087*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1088*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 nt_lookup_fn rw SUPPRESSED ArCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED rIP INVALID inum=1089*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_CX] r SUPPRESSED INVALID + REG1 reg [XED_REG_IP] rw SUPPRESSED INVALID inum=1090*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_CX_REG1_XED_REG_IP, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EIP] rw SUPPRESSED INVALID inum=1091*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_ECX_REG1_XED_REG_EIP, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG1 reg [XED_REG_RIP] rw SUPPRESSED INVALID inum=1092*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_ECX_REG1_XED_REG_RIP, +/* RELBR imm_const [1] r EXPLICIT b i8 + REG0 reg [XED_REG_RCX] r SUPPRESSED INVALID + REG1 reg [XED_REG_RIP] rw SUPPRESSED INVALID inum=1093*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RCX_REG1_XED_REG_RIP, +/* REG0 reg [XED_REG_AL] w IMPLICIT INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1094*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w IMPLICIT OeAX INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1095*/ xed3_capture_chain_ntluf_REG0_OeAX_IMM0_const1_REG1_rFLAGS, +/* REG0 reg [XED_REG_AL] w IMPLICIT INVALID + REG1 reg [XED_REG_DX] r IMPLICIT INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1096*/ xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_DX_REG2_rFLAGS, +/* REG0 nt_lookup_fn w IMPLICIT OeAX INVALID + REG1 reg [XED_REG_DX] r IMPLICIT INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1097*/ xed3_capture_chain_ntluf_REG0_OeAX_REG1_XED_REG_DX_REG2_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_AL] r IMPLICIT INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1098*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT b u8 + REG0 nt_lookup_fn r IMPLICIT OeAX INVALID + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1099*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_OeAX_REG1_rFLAGS, +/* REG0 reg [XED_REG_DX] r IMPLICIT INVALID + REG1 reg [XED_REG_AL] r IMPLICIT INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1100*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AL_REG2_rFLAGS, +/* REG0 reg [XED_REG_DX] r IMPLICIT INVALID + REG1 nt_lookup_fn r IMPLICIT OeAX INVALID + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1101*/ xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_OeAX_REG2_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rIP INVALID inum=1102*/ xed3_capture_chain_ntluf_REG0_rIP, +/* inum=1103*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1104*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1105*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1106*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1107*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=1108*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1109*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1110*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1111*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1112*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1113*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRz_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1114*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRz_B_REG2_rFLAGS, +/* REG0 reg [XED_REG_RIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_RCX] w SUPPRESSED INVALID + REG2 reg [XED_REG_R11] w SUPPRESSED INVALID + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1115*/ xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RCX_REG2_XED_REG_R11_REG3_rFLAGS, +/* inum=1116*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_EIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1117*/ xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ECX_REG2_rFLAGS, +/* REG0 reg [XED_REG_RIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_RCX] r SUPPRESSED INVALID + REG2 reg [XED_REG_R11] r SUPPRESSED INVALID + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1118*/ xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RCX_REG2_XED_REG_R11_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1119*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1120*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT ps f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1121*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_R ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1122*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1123*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1124*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1125*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1126*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1127*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1128*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT ss f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1129*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_R ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1130*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1131*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1132*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1133*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1134*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1135*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1136*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT pd f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1137*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_R pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1138*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1139*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1140*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1141*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1142*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1143*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1144*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1145*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1146*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1147*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1148*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT sd f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1149*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_R sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1150*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1151*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1152*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT CR_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1153*/ xed3_capture_chain_ntluf_REG0_CR_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT CR_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1154*/ xed3_capture_chain_ntluf_REG0_CR_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT CR_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1155*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_CR_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B INVALID + REG1 nt_lookup_fn r EXPLICIT CR_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1156*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_CR_R, +/* REG0 nt_lookup_fn w EXPLICIT DR_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1157*/ xed3_capture_chain_ntluf_REG0_DR_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT DR_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1158*/ xed3_capture_chain_ntluf_REG0_DR_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT DR_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1159*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_DR_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B INVALID + REG1 nt_lookup_fn r EXPLICIT DR_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1160*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_DR_R, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_MSRS] w SUPPRESSED INVALID inum=1161*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_MSRS, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG2 reg [XED_REG_TSC] r SUPPRESSED INVALID inum=1162*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_TSC, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_MSRS] r SUPPRESSED INVALID inum=1163*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_MSRS, +/* REG0 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_MSRS] r SUPPRESSED INVALID inum=1164*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_MSRS, +/* REG0 reg [XED_REG_EIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_ESP] w SUPPRESSED INVALID + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1165*/ xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ESP_REG2_rFLAGS, +/* REG0 reg [XED_REG_RIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_RSP] w SUPPRESSED INVALID + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1166*/ xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RSP_REG2_rFLAGS, +/* REG0 reg [XED_REG_EIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_ESP] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID inum=1167*/ xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ESP_REG2_XED_REG_ECX_REG3_XED_REG_EDX, +/* REG0 reg [XED_REG_RIP] w SUPPRESSED INVALID + REG1 reg [XED_REG_RSP] w SUPPRESSED INVALID + REG2 reg [XED_REG_RCX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] r SUPPRESSED INVALID inum=1168*/ xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RSP_REG2_XED_REG_RCX_REG3_XED_REG_RDX, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1169*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1170*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1171*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1172*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1173*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1174*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1175*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1176*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1177*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1178*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1179*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1180*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1181*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1182*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1183*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1184*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1185*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1186*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1187*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1188*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1189*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1190*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1191*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + MEM0 imm_const [1] r EXPLICIT xud u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1192*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B xud u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1193*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + MEM0 imm_const [1] r EXPLICIT xud u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1194*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B xud u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1195*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + MEM0 imm_const [1] r EXPLICIT xud u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1196*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B xud u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1197*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + MEM0 imm_const [1] r EXPLICIT xud u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1198*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xud u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B xud u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1199*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1200*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1201*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1202*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1203*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1204*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1205*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1206*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1207*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1208*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + MEM0 imm_const [1] r EXPLICIT xuq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1209*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B xuq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1210*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + MEM0 imm_const [1] r EXPLICIT xuq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1211*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B xuq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1212*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + MEM0 imm_const [1] r EXPLICIT xuq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1213*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B xuq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1214*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + MEM0 imm_const [1] r EXPLICIT xuq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1215*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R xuq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B xuq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1216*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1217*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1218*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u8 + MEM0 imm_const [1] r EXPLICIT d u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1219*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u8 + REG1 nt_lookup_fn r EXPLICIT MMX_B d u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1220*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1221*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1222*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + MEM0 imm_const [1] r EXPLICIT d u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1223*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + REG1 nt_lookup_fn r EXPLICIT MMX_B d u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1224*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1225*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1226*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1227*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + REG1 nt_lookup_fn r EXPLICIT MMX_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1228*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1229*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1230*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1231*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1232*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1233*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1234*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1235*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1236*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1237*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1238*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1239*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1240*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1241*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1242*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1243*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1244*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1245*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1246*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1247*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1248*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1249*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1250*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q u16 + MEM0 imm_const [1] r EXPLICIT q u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1251*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q u16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1252*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1253*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1254*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1255*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1256*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1257*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1258*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1259*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1260*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1261*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1262*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1263*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1264*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* inum=1265*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1266*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1267*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1268*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1269*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1270*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1271*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1272*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1273*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1274*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1275*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1276*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1277*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1278*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1279*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1280*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1281*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1282*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1283*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1284*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1285*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1286*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1287*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* REG0 reg [XED_REG_EAX] rw SUPPRESSED INVALID + REG1 reg [XED_REG_EBX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] crw SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] w SUPPRESSED INVALID inum=1288*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX_REG2_XED_REG_ECX_REG3_XED_REG_EDX, +/* MEM0 imm_const [1] rcw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + REG1 reg [XED_REG_AL] rcw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1289*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_XED_REG_AL_REG2_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn rcw SUPPRESSED OrAX INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1290*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_OrAX_REG2_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT GPR8_R INVALID + REG1 reg [XED_REG_AL] rcw SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1291*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_XED_REG_AL_REG2_rFLAGS, +/* REG0 nt_lookup_fn rcw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_R INVALID + REG2 reg [XED_REG_AL] rcw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1292*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_XED_REG_AL_REG3_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn rcw SUPPRESSED OrAX INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1293*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_OrAX_REG2_rFLAGS, +/* REG0 nt_lookup_fn rcw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG2 nt_lookup_fn rcw SUPPRESSED OrAX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1294*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_OrAX_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT p2 struct + REG1 reg [XED_REG_SS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1295*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_SS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT p2 struct + REG1 reg [XED_REG_FS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1296*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_FS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT p2 struct + REG1 reg [XED_REG_GS] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1297*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_GS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1298*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1299*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR8_B, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1300*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR16_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1301*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR16_B, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1302*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1303*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT b u8 + REG0 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1304*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR8_B INVALID + REG1 nt_lookup_fn rw EXPLICIT GPR8_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1305*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS, +/* MEM0 imm_const [1] rw EXPLICIT v int + REG0 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1306*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn rw EXPLICIT GPRv_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1307*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1308*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1309*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1310*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1311*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1312*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + MEM0 imm_const [1] r EXPLICIT w u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1313*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1314*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT w i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1315*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1316*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT MMX_B q u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1317*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1318*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1319*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1320*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1321*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1322*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1323*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1324*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1325*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1326*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1327*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1328*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u64 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1329*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1330*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1331*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1332*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1333*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1334*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1335*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1336*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT MMX_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1337*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MMX_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1338*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1339*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1340*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1341*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1342*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1343*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1344*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1345*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1346*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1347*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1348*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1349*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1350*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1351*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1352*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + MEM0 imm_const [1] r EXPLICIT q u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1353*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1354*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1355*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1356*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1357*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1358*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1359*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1360*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT MMX_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1361*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1362*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1363*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1364*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1365*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1366*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1367*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1368*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + MEM0 imm_const [1] r EXPLICIT q u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1369*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q u32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1370*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1371*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1372*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1373*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i16 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1374*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1375*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1376*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1377*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1378*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1379*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1380*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn r EXPLICIT MMX_R q u8 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i8 + MEM0 imm_const [1] w SUPPRESSED q i64 + BASE0 nt_lookup_fn r SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1381*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MEM0 imm_const [1] w SUPPRESSED dq i32 + BASE0 nt_lookup_fn r SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1382*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1383*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* inum=1384*/ xed3_capture_nt_nop_ntluf, +/* inum=1385*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1386*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1387*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1388*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1389*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B, +/* inum=1390*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1391*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1392*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT ps f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1393*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_R ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1394*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R q f32 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1395*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R q f32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1396*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_MMX_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1397*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1398*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1399*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1400*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1401*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1402*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1403*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1404*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1405*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1406*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1407*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1408*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1409*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1410*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1411*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1412*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1413*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1414*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1415*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1416*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1417*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1418*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1419*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT pd f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1420*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_R pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1421*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1422*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1423*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_MMX_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 19, 20 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 25, 26, 27 inum=1424*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1425*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1426*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1427*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1428*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1429*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1430*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1431*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1432*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1433*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1434*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1435*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1436*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1437*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1438*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1439*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1440*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1441*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1442*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1443*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1444*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1445*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1446*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1447*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1448*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1449*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1450*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1451*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1452*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1453*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1454*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1455*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1456*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1457*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1458*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1459*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1460*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1461*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1462*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1463*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1464*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1465*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1466*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1467*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1468*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1469*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1470*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1471*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1472*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1473*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1474*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1475*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1476*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1477*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1478*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1479*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1480*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1481*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1482*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1483*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1484*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1485*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1486*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1487*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1488*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1489*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1490*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT ss f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1491*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ss f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1492*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1493*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1494*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1495*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1496*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1497*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1498*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1499*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1500*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1501*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1502*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1503*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1504*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1505*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1506*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1507*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1508*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1509*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1510*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1511*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1512*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1513*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ss f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1514*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1515*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1516*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1517*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1518*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1519*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1520*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + MEM0 imm_const [1] r EXPLICIT sd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1521*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R sd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B sd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1522*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1523*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1524*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1525*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1526*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1527*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1528*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1529*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1530*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1531*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1532*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1533*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1534*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1535*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i32 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1536*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1537*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1538*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1539*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1540*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1541*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1542*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1543*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1544*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1545*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1546*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1547*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1548*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1549*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1550*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT MMX_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1551*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT MMX_R d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1552*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_MMX_R, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT MMX_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1553*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT MMX_R d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1554*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1555*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1556*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1557*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1558*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1559*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1560*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1561*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1562*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1563*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1564*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR64_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT MMX_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1565*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B INVALID + REG1 nt_lookup_fn r EXPLICIT MMX_R q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1566*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1567*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1568*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT MMX_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1569*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R, +/* REG0 nt_lookup_fn w EXPLICIT MMX_B q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_R q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1570*/ xed3_capture_chain_ntluf_REG0_MMX_B_REG1_MMX_R, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1571*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1572*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1573*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1574*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1575*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1576*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1577*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1578*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1579*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1580*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_GPR64_R_REG2_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1581*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1582*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_GPR32_R_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1583*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1584*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_GPR64_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1585*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1586*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1587*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1588*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1589*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1590*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1591*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1592*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1593*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1594*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1595*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1596*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1597*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=1598*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1599*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1600*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1601*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1602*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1603*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1604*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1605*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1606*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1607*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1608*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1609*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1610*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1611*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1612*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1613*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn r SUPPRESSED rFLAGS INVALID inum=1614*/ xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1615*/ xed3_capture_chain_ntluf_REG0_rIP_REG1_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1616*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rcw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1617*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_IMM0_const1_REG2_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=1618*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_XED_REG_CL_REG2_rFLAGS, +/* REG0 nt_lookup_fn rcw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG2 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=1619*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_XED_REG_CL_REG3_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1620*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rcw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1621*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_IMM0_const1_REG2_rFLAGS, +/* MEM0 imm_const [1] rcw EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG1 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=1622*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_XED_REG_CL_REG2_rFLAGS, +/* REG0 nt_lookup_fn rcw EXPLICIT GPRv_B INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_R INVALID + REG2 reg [XED_REG_CL] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn cw SUPPRESSED rFLAGS INVALID inum=1623*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_XED_REG_CL_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1624*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR8_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1625*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR8_B, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT w i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1626*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR16_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1627*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR16_B, +/* REG0 nt_lookup_fn rw EXPLICIT GPRv_SB INVALID + SRM imm rrr (L) r SUPPRESSED i3 bitpos: 13, 14, 15 inum=1628*/ xed3_capture_chain_ntluf_REG0_GPRv_SB, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1629*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1630*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1631*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1632*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1633*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1634*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1635*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1636*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1637*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1638*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1639*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1640*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1641*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1642*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1643*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1644*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1645*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1646*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1647*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1648*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1649*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1650*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1651*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1652*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1653*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1654*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1655*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1656*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1657*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1658*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1659*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1660*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1661*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1662*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1663*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1664*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1665*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1666*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1667*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1668*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1669*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1670*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1671*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1672*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1673*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1674*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1675*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1676*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1677*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1678*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1679*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1680*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1681*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1682*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1683*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1684*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1685*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1686*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1687*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1688*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1689*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1690*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1691*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1692*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1693*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1694*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1695*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1696*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1697*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1698*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1699*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1700*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1701*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1702*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1703*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1704*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1705*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1706*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1707*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1708*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1709*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1710*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1711*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1712*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1713*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1714*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1715*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1716*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1717*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1718*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1719*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 inum=1720*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1721*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1722*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1723*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1724*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1725*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1726*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1727*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1728*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1729*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1730*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1731*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1732*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1733*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1734*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1735*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1736*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1737*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1738*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1739*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1740*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1741*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1742*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1743*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1744*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1745*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i8 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1746*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1747*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1748*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1749*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1750*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1751*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1752*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1753*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1754*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1755*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1756*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1757*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1758*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1759*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1760*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1761*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1762*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1763*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1764*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1765*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1766*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1767*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1768*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1769*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1770*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1771*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1772*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1773*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1774*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1775*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1776*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1777*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1778*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1779*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1780*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1781*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1782*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1783*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1784*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R v int + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1785*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R v int + REG1 nt_lookup_fn r EXPLICIT GPRv_B v int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1786*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1787*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1788*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT GPRy_R y int + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 inum=1789*/ xed3_capture_chain_ntluf_REG0_GPRy_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT GPRy_R y int + REG1 nt_lookup_fn r EXPLICIT GPR8_B b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 inum=1790*/ xed3_capture_chain_ntluf_REG0_GPRy_R_REG1_GPR8_B, +/* REG0 nt_lookup_fn rw EXPLICIT GPRy_R y int + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 inum=1791*/ xed3_capture_chain_ntluf_REG0_GPRy_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT GPRy_R y int + REG1 nt_lookup_fn r EXPLICIT GPRv_B v int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 inum=1792*/ xed3_capture_chain_ntluf_REG0_GPRy_R_REG1_GPRv_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1793*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1794*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1795*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1796*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG1 reg [XED_REG_XMM0] r SUPPRESSED dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1797*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XED_REG_XMM0, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG2 reg [XED_REG_XMM0] r SUPPRESSED dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1798*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_XMM0, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG1 reg [XED_REG_XMM0] r SUPPRESSED dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1799*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XED_REG_XMM0, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG2 reg [XED_REG_XMM0] r SUPPRESSED dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1800*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_XMM0, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1801*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1802*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1803*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1804*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1805*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1806*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1807*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1808*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1809*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1810*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1811*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1812*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1813*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1814*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1815*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1816*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1817*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG1 reg [XED_REG_XMM0] r SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1818*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XED_REG_XMM0, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG2 reg [XED_REG_XMM0] r SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1819*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_XMM0, +/* MEM0 imm_const [1] w EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1820*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1821*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT w i16 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1822*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1823*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 inum=1824*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 inum=1825*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 inum=1826*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 inum=1827*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1828*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1829*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 inum=1830*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 inum=1831*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 inum=1832*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 inum=1833*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + MEM0 imm_const [1] r EXPLICIT pd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1834*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R pd f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B pd f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1835*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + MEM0 imm_const [1] r EXPLICIT ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1836*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R ps f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B ps f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1837*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1838*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1839*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1840*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1841*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1842*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1843*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1844*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1845*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1846*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1847*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1848*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1849*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1850*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1851*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1852*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1853*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1854*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1855*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1856*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1857*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1858*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1859*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1860*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1861*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1862*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1863*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1864*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1865*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1866*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1867*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1868*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1869*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT w i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1870*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B w i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1871*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1872*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1873*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT d i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1874*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1875*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1876*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1877*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT q u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1878*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1879*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT d u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1880*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1881*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT w u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1882*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B w u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1883*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT q u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1884*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1885*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT d u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1886*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1887*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT q u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1888*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 inum=1889*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1890*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_ECX_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1891*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_ECX_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1892*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_ECX_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1893*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_ECX_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1894*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_RCX_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1895*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_RCX_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1896*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_ECX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1897*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_ECX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1898*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_ECX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1899*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_ECX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1900*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RCX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1901*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RCX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1902*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 28, 29 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 34, 35, 36 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1903*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_XMM0_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1904*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1905*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_XMM0_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1906*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 29, 30 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 35, 36, 37 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1907*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_XMM0_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1908*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_XMM0_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 27, 28 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 33, 34, 35 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1909*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_XMM0_REG3_rFLAGS, +/* REG0 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG2 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG3 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1910*/ xed3_capture_chain_ntluf_REG0_XED_REG_ECX_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_XED_REG_XCR0, +/* REG0 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XCR0] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1911*/ xed3_capture_chain_ntluf_REG0_XED_REG_ECX_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_XED_REG_XCR0, +/* MEM0 imm_const [1] rw EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1912*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] r EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1913*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] rw EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1914*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] r EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1915*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 inum=1916*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT v int + REG0 nt_lookup_fn r EXPLICIT GPRv_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 inum=1917*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R, +/* REG0 reg [XED_REG_EAX] rcw SUPPRESSED INVALID + REG1 reg [XED_REG_EBX] r SUPPRESSED INVALID inum=1918*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1919*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1920*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1921*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1922*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1923*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1924*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1925*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1926*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1927*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1928*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1929*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1930*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1931*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=1932*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1933*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1934*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1935*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=1936*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1937*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1938*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1939*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1940*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1941*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1942*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1943*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn r SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn w SUPPRESSED OrAX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1944*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrAX_BASE0_ArDI_SEG0_FINAL_ESEG, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn rw SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn w SUPPRESSED OrAX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1945*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrAX_BASE0_ArDI_SEG0_FINAL_ESEG, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn r SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn r SUPPRESSED OrBX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1946*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn r SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn r SUPPRESSED OrBX INVALID + REG3 nt_lookup_fn r SUPPRESSED ArAX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1947*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_REG3_ArAX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn r SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn r SUPPRESSED OrBX INVALID + REG3 nt_lookup_fn r SUPPRESSED ArAX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1948*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_REG3_ArAX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn r SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn r SUPPRESSED OrBX INVALID + REG3 nt_lookup_fn r SUPPRESSED ArAX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1949*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_REG3_ArAX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1, +/* MEM0 imm_const [1] w SUPPRESSED b u8 + REG0 nt_lookup_fn rw SUPPRESSED OrCX INVALID + REG1 nt_lookup_fn r SUPPRESSED OrDX INVALID + REG2 nt_lookup_fn r SUPPRESSED OrBX INVALID + REG3 nt_lookup_fn r SUPPRESSED ArAX INVALID + BASE0 nt_lookup_fn rw SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] cr SUPPRESSED b u8 + BASE1 nt_lookup_fn rcw SUPPRESSED ArSI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_DSEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1950*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_REG3_ArAX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1, +/* REG0 nt_lookup_fn rcw SUPPRESSED ArAX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED OrCX INVALID + MEM0 imm_const [1] w SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED b u8 + BASE1 nt_lookup_fn r SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1951*/ xed3_capture_chain_ntluf_REG0_ArAX_REG1_OrCX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1, +/* REG0 nt_lookup_fn rcw SUPPRESSED ArAX INVALID + REG1 nt_lookup_fn rcw SUPPRESSED OrCX INVALID + MEM0 imm_const [1] w SUPPRESSED b u8 + BASE0 nt_lookup_fn rw SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MEM1 imm_const [1] r SUPPRESSED b u8 + BASE1 nt_lookup_fn r SUPPRESSED ArDI INVALID + SEG1 nt_lookup_fn r SUPPRESSED FINAL_ESEG1 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1952*/ xed3_capture_chain_ntluf_REG0_ArAX_REG1_OrCX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1, +/* REG0 reg [XED_REG_EAX] rw SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] rw SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] w SUPPRESSED INVALID + MEM0 imm_const [1] rw SUPPRESSED pmmsz16 struct + BASE0 nt_lookup_fn r SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1953*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG, +/* REG0 reg [XED_REG_EAX] rw SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] rw SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] w SUPPRESSED INVALID + MEM0 imm_const [1] rw SUPPRESSED pmmsz32 struct + BASE0 nt_lookup_fn r SUPPRESSED ArSI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_ESEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=1954*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG, +/* inum=1955*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1956*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1957*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1958*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1959*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1960*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1961*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1962*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1963*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1964*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1965*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1966*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1967*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1968*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1969*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1970*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1971*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1972*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1973*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1974*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1975*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1976*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1977*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1978*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1979*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1980*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1981*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1982*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1983*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1984*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1985*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1986*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1987*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1988*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1989*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1990*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1991*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1992*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1993*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1994*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1995*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1996*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1997*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1998*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=1999*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2000*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2001*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2002*/ xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT MMX_R q i64 + REG1 nt_lookup_fn r EXPLICIT MMX_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2003*/ xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B, +/* REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2004*/ xed3_capture_chain_ntluf_REG0_rIP_REG1_rFLAGS, +/* REG0 reg [XED_REG_EIP] w SUPPRESSED INVALID + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2005*/ xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_rFLAGS, +/* REG0 nt_lookup_fn r IMPLICIT ArAX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2006*/ xed3_capture_chain_ntluf_REG0_ArAX, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2007*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn r IMPLICIT ArAX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2008*/ xed3_capture_chain_ntluf_REG0_ArAX, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2009*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2010*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2011*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_EAX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2012*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX, +/* REG0 nt_lookup_fn r IMPLICIT ArAX INVALID + REG1 reg [XED_REG_ECX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2013*/ xed3_capture_chain_ntluf_REG0_ArAX_REG1_XED_REG_ECX, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + IMM1 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 19, 20 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 25, 26, 27 inum=2014*/ xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1_IMM1_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 19, 20 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 25, 26, 27 inum=2015*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + IMM1 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2016*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_IMM1_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2017*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2018*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2019*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn r SUPPRESSED ArAX INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2020*/ xed3_capture_chain_ntluf_REG0_ArAX, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2021*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_AX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2022*/ xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2023*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2024*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX, +/* REG0 reg [XED_REG_EAX] rw SUPPRESSED INVALID + REG1 reg [XED_REG_ECX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2025*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2026*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 reg [XED_REG_EDX] w SUPPRESSED d i32 + REG1 reg [XED_REG_EAX] w SUPPRESSED d i32 + REG2 reg [XED_REG_ECX] r SUPPRESSED d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2027*/ xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX, +/* REG0 reg [XED_REG_RAX] rw IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2028*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_rFLAGS, +/* REG0 reg [XED_REG_RAX] rw IMPLICIT INVALID + REG1 reg [XED_REG_ECX] r IMPLICIT INVALID + REG2 reg [XED_REG_EDX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2029*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_REG3_rFLAGS, +/* REG0 reg [XED_REG_RAX] rw IMPLICIT INVALID + REG1 reg [XED_REG_RCX] r IMPLICIT INVALID + REG2 reg [XED_REG_RDX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2030*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_RCX_REG2_XED_REG_RDX_REG3_rFLAGS, +/* REG0 reg [XED_REG_RAX] rw IMPLICIT INVALID + REG1 reg [XED_REG_RCX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2031*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_RCX_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r IMPLICIT INVALID + REG1 reg [XED_REG_EDX] r IMPLICIT INVALID + REG2 reg [XED_REG_ECX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2032*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX, +/* REG0 reg [XED_REG_RAX] r IMPLICIT INVALID + REG1 reg [XED_REG_EDX] r IMPLICIT INVALID + REG2 reg [XED_REG_ECX] r IMPLICIT INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2033*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2034*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + AGEN imm_const [1] r EXPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2035*/ xed3_capture_chain_ntluf_REG0_BND_R_AGEN_const1, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + AGEN imm_const [1] r EXPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2036*/ xed3_capture_chain_ntluf_REG0_BND_R_AGEN_const1, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2037*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2038*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + AGEN imm_const [1] r EXPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2039*/ xed3_capture_chain_ntluf_REG0_BND_R_AGEN_const1, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2040*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2041*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + AGEN imm_const [1] r EXPLICIT INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2042*/ xed3_capture_chain_ntluf_REG0_BND_R_AGEN_const1, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR64_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2043*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPR32_B INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2044*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + REG1 nt_lookup_fn r EXPLICIT BND_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2045*/ xed3_capture_chain_ntluf_REG0_BND_R_REG1_BND_B, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT q u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2046*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT q u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2047*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2048*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT BND_B INVALID + REG1 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2049*/ xed3_capture_chain_ntluf_REG0_BND_B_REG1_BND_R, +/* MEM0 imm_const [1] w EXPLICIT q u32 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2050*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* MEM0 imm_const [1] w EXPLICIT q u32 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2051*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2052*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT bnd32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2053*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT bnd64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2054*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT bnd64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2055*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT BND_R INVALID + MEM0 imm_const [1] r EXPLICIT bnd64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2056*/ xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT bnd32 u32 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2057*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* MEM0 imm_const [1] w EXPLICIT bnd64 u64 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2058*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* MEM0 imm_const [1] w EXPLICIT bnd64 u64 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2059*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* MEM0 imm_const [1] w EXPLICIT bnd64 u64 + REG0 nt_lookup_fn r EXPLICIT BND_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 inum=2060*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R, +/* MEM0 imm_const [1] rw EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2061*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2062*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2063*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_B d u8 + REG1 reg [XED_REG_SSP] rw SUPPRESSED u64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2064*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_SSP, +/* REG0 nt_lookup_fn r EXPLICIT GPR64_B q u8 + REG1 reg [XED_REG_SSP] rw SUPPRESSED u64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2065*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_SSP, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u32 + REG1 reg [XED_REG_SSP] r SUPPRESSED u64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2066*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_SSP, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q u64 + REG1 reg [XED_REG_SSP] r SUPPRESSED u64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2067*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_SSP, +/* MEM0 imm_const [1] rw EXPLICIT q u64 + REG0 reg [XED_REG_SSP] w SUPPRESSED u64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2068*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_SSP, +/* REG0 reg [XED_REG_SSP] r SUPPRESSED u64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2069*/ xed3_capture_chain_ntluf_REG0_XED_REG_SSP, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2070*/ xed3_capture_nt_nop_ntluf, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT GPR32_R d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2071*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT GPR64_R q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2072*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT GPR32_R d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2073*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT GPR64_R q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2074*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2075*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2076*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2077*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2078*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2079*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2080*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2081*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2082*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2083*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2084*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2085*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2086*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2087*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG2 reg [XED_REG_XMM0] r SUPPRESSED dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2088*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_XMM0, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG1 reg [XED_REG_XMM0] r SUPPRESSED dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2089*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XED_REG_XMM0, +/* MEM0 imm_const [1] rw EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2090*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] rw EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2091*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] w EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2092*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] w EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2093*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] r EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2094*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] r EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2095*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] w EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2096*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] w EXPLICIT mxsave struct + REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_XCR0] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2097*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2098*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2099*/ xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRy_B INVALID + REG1 reg [XED_REG_FSBASE] r SUPPRESSED y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2100*/ xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_FSBASE, +/* REG0 nt_lookup_fn w EXPLICIT GPRy_B INVALID + REG1 reg [XED_REG_GSBASE] r SUPPRESSED y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2101*/ xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_GSBASE, +/* REG0 nt_lookup_fn r EXPLICIT GPRy_B INVALID + REG1 reg [XED_REG_FSBASE] w SUPPRESSED y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2102*/ xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_FSBASE, +/* REG0 nt_lookup_fn r EXPLICIT GPRy_B INVALID + REG1 reg [XED_REG_GSBASE] w SUPPRESSED y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2103*/ xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_GSBASE, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 010 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2104*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 011 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2105*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_RBX] crw SUPPRESSED INVALID + REG2 reg [XED_REG_RCX] crw SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] crw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2106*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG1 reg [XED_REG_RBX] crw SUPPRESSED INVALID + REG2 reg [XED_REG_RCX] crw SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] crw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2107*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u32 + REG1 reg [XED_REG_TSCAUX] r SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2108*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_TSCAUX, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q u64 + REG1 reg [XED_REG_TSCAUX] r SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2109*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_TSCAUX, +/* REG0 nt_lookup_fn r EXPLICIT GPRy_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2110*/ xed3_capture_chain_ntluf_REG0_GPRy_B, +/* MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2111*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT A_GPR_R INVALID + MEM0 imm_const [1] r EXPLICIT zd u32 + MEM1 imm_const [1] w SUPPRESSED zd i32 + BASE1 nt_lookup_fn r SUPPRESSED A_GPR_R INVALID + SEG1 reg [XED_REG_ES] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2112*/ xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_MEM1_const1_BASE1_A_GPR_R_SEG1_XED_REG_ES, +/* REG0 nt_lookup_fn r EXPLICIT A_GPR_R INVALID + MEM0 imm_const [1] r EXPLICIT zd u32 + MEM1 imm_const [1] w SUPPRESSED zd i32 + BASE1 nt_lookup_fn r SUPPRESSED A_GPR_R INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2113*/ xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_MEM1_const1_BASE1_A_GPR_R, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT GPR32_R d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2114*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT GPR64_R q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2115*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_B d u32 + REG1 reg [XED_REG_EDX] r SUPPRESSED d u32 + REG2 reg [XED_REG_EAX] r SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2116*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT A_GPR_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2117*/ xed3_capture_chain_ntluf_REG0_A_GPR_B, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_B d u32 + REG1 reg [XED_REG_EDX] r SUPPRESSED d u32 + REG2 reg [XED_REG_EAX] r SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2118*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2119*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED d u32 + REG1 reg [XED_REG_RBX] crw SUPPRESSED q u64 + REG2 reg [XED_REG_RCX] crw SUPPRESSED q u64 + REG3 reg [XED_REG_RDX] crw SUPPRESSED q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2120*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2121*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2122*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2123*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2124*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2125*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2126*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 reg [XED_REG_EAX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2127*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX, +/* REG0 nt_lookup_fn r EXPLICIT GPR64_R INVALID + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=2128*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_R INVALID + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 26, 27 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 29, 30, 31 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 32, 33, 34 inum=2129*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R v int + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2130*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPRv_R v int + REG1 nt_lookup_fn r EXPLICIT GPRv_B v int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2131*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2132*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 17, 18 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 23, 24, 25 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2133*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + MEM0 imm_const [1] r EXPLICIT v int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2134*/ xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn cw EXPLICIT GPRv_R INVALID + REG1 nt_lookup_fn r EXPLICIT GPRv_B INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 18, 19 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 24, 25, 26 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2135*/ xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS, +/* RELBR imm_const [1] r EXPLICIT z int + REG0 nt_lookup_fn rw SUPPRESSED rIP INVALID + REG1 reg [XED_REG_EAX] cw SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=2136*/ xed3_capture_chain_ntluf_RELBR_const1_REG0_rIP_REG1_XED_REG_EAX, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2137*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_EAX] rcw SUPPRESSED INVALID + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 8, 9 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 11, 12, 13 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 inum=2138*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_IMM0_const1, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2139*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2140*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2141*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2142*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_GPR64_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2143*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2144*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2145*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG2 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2146*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_GPR64_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG1 nt_lookup_fn rw SUPPRESSED rFLAGS INVALID inum=2147*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS, +/* REG0 reg [XED_REG_EDX] w SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] w SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2148*/ xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX, +/* REG0 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_ECX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2149*/ xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX, +/* MEM0 imm_const [1] r EXPLICIT mprefetch i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2150*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2151*/ xed3_capture_chain_ntluf_MEM0_const1, +/* inum=2152*/ xed3_capture_nt_nop_ntluf, +/* inum=2153*/ xed3_capture_nt_nop_ntluf, +/* inum=2154*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_EAX] rw SUPPRESSED d u32 + REG1 reg [XED_REG_EBX] crw SUPPRESSED d u32 + REG2 reg [XED_REG_ECX] crw SUPPRESSED d u32 + REG3 reg [XED_REG_EDX] crw SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2155*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_rFLAGS, +/* REG0 reg [XED_REG_EAX] rw SUPPRESSED d u32 + REG1 reg [XED_REG_RBX] crw SUPPRESSED q u64 + REG2 reg [XED_REG_RCX] crw SUPPRESSED q u64 + REG3 reg [XED_REG_RDX] crw SUPPRESSED q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2156*/ xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX_REG4_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2157*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2158*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2159*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2160*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2161*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2162*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT m384 u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2163*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2164*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT m384 u8 + REG0 reg [XED_REG_XMM0] rw SUPPRESSED dq u8 + REG1 reg [XED_REG_XMM1] rw SUPPRESSED dq u8 + REG2 reg [XED_REG_XMM2] rw SUPPRESSED dq u8 + REG3 reg [XED_REG_XMM3] rw SUPPRESSED dq u8 + REG4 reg [XED_REG_XMM4] rw SUPPRESSED dq u8 + REG5 reg [XED_REG_XMM5] rw SUPPRESSED dq u8 + REG6 reg [XED_REG_XMM6] rw SUPPRESSED dq u8 + REG7 reg [XED_REG_XMM7] rw SUPPRESSED dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG8 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2165*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_XMM0_REG1_XED_REG_XMM1_REG2_XED_REG_XMM2_REG3_XED_REG_XMM3_REG4_XED_REG_XMM4_REG5_XED_REG_XMM5_REG6_XED_REG_XMM6_REG7_XED_REG_XMM7_REG8_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT zd u8 + REG0 reg [XED_REG_XMM0] rw SUPPRESSED dq u8 + REG1 reg [XED_REG_XMM1] rw SUPPRESSED dq u8 + REG2 reg [XED_REG_XMM2] rw SUPPRESSED dq u8 + REG3 reg [XED_REG_XMM3] rw SUPPRESSED dq u8 + REG4 reg [XED_REG_XMM4] rw SUPPRESSED dq u8 + REG5 reg [XED_REG_XMM5] rw SUPPRESSED dq u8 + REG6 reg [XED_REG_XMM6] rw SUPPRESSED dq u8 + REG7 reg [XED_REG_XMM7] rw SUPPRESSED dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG8 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2166*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_XMM0_REG1_XED_REG_XMM1_REG2_XED_REG_XMM2_REG3_XED_REG_XMM3_REG4_XED_REG_XMM4_REG5_XED_REG_XMM5_REG6_XED_REG_XMM6_REG7_XED_REG_XMM7_REG8_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT m384 u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2167*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2168*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT m384 u8 + REG0 reg [XED_REG_XMM0] rw SUPPRESSED dq u8 + REG1 reg [XED_REG_XMM1] rw SUPPRESSED dq u8 + REG2 reg [XED_REG_XMM2] rw SUPPRESSED dq u8 + REG3 reg [XED_REG_XMM3] rw SUPPRESSED dq u8 + REG4 reg [XED_REG_XMM4] rw SUPPRESSED dq u8 + REG5 reg [XED_REG_XMM5] rw SUPPRESSED dq u8 + REG6 reg [XED_REG_XMM6] rw SUPPRESSED dq u8 + REG7 reg [XED_REG_XMM7] rw SUPPRESSED dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG8 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2169*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_XMM0_REG1_XED_REG_XMM1_REG2_XED_REG_XMM2_REG3_XED_REG_XMM3_REG4_XED_REG_XMM4_REG5_XED_REG_XMM5_REG6_XED_REG_XMM6_REG7_XED_REG_XMM7_REG8_rFLAGS, +/* MEM0 imm_const [1] r EXPLICIT zd u8 + REG0 reg [XED_REG_XMM0] rw SUPPRESSED dq u8 + REG1 reg [XED_REG_XMM1] rw SUPPRESSED dq u8 + REG2 reg [XED_REG_XMM2] rw SUPPRESSED dq u8 + REG3 reg [XED_REG_XMM3] rw SUPPRESSED dq u8 + REG4 reg [XED_REG_XMM4] rw SUPPRESSED dq u8 + REG5 reg [XED_REG_XMM5] rw SUPPRESSED dq u8 + REG6 reg [XED_REG_XMM6] rw SUPPRESSED dq u8 + REG7 reg [XED_REG_XMM7] rw SUPPRESSED dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG8 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2170*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_XMM0_REG1_XED_REG_XMM1_REG2_XED_REG_XMM2_REG3_XED_REG_XMM3_REG4_XED_REG_XMM4_REG5_XED_REG_XMM5_REG6_XED_REG_XMM6_REG7_XED_REG_XMM7_REG8_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u8 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u8 + REG2 reg [XED_REG_XMM0] rw SUPPRESSED dq u8 + REG3 reg [XED_REG_XMM1] w SUPPRESSED dq u8 + REG4 reg [XED_REG_XMM2] w SUPPRESSED dq u8 + REG5 reg [XED_REG_XMM4] w SUPPRESSED dq u8 + REG6 reg [XED_REG_XMM5] w SUPPRESSED dq u8 + REG7 reg [XED_REG_XMM6] w SUPPRESSED dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG8 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2171*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_XED_REG_XMM0_REG3_XED_REG_XMM1_REG4_XED_REG_XMM2_REG5_XED_REG_XMM4_REG6_XED_REG_XMM5_REG7_XED_REG_XMM6_REG8_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u8 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u8 + REG2 reg [XED_REG_XMM0] rw SUPPRESSED dq u8 + REG3 reg [XED_REG_XMM1] rw SUPPRESSED dq u8 + REG4 reg [XED_REG_XMM2] w SUPPRESSED dq u8 + REG5 reg [XED_REG_XMM3] w SUPPRESSED dq u8 + REG6 reg [XED_REG_XMM4] w SUPPRESSED dq u8 + REG7 reg [XED_REG_XMM5] w SUPPRESSED dq u8 + REG8 reg [XED_REG_XMM6] w SUPPRESSED dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG9 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2172*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_XED_REG_XMM0_REG3_XED_REG_XMM1_REG4_XED_REG_XMM2_REG5_XED_REG_XMM3_REG6_XED_REG_XMM4_REG7_XED_REG_XMM5_REG8_XED_REG_XMM6_REG9_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED d u32 + REG3 reg [XED_REG_XMM0] r SUPPRESSED dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 25, 26 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 28, 29, 30 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 31, 32, 33 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2173*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_EAX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* IMM0 imm_const [1] r EXPLICIT b u8 + REG0 reg [XED_REG_EAX] r SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 30, 31, 32 inum=2174*/ xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_EAX, +/* REG0 reg [XED_REG_UIF] w SUPPRESSED i1 int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2175*/ xed3_capture_chain_ntluf_REG0_XED_REG_UIF, +/* REG0 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2176*/ xed3_capture_chain_ntluf_REG0_GPR32_B, +/* REG0 reg [XED_REG_UIF] w SUPPRESSED i1 int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2177*/ xed3_capture_chain_ntluf_REG0_XED_REG_UIF, +/* REG0 reg [XED_REG_UIF] r SUPPRESSED i1 int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2178*/ xed3_capture_chain_ntluf_REG0_XED_REG_UIF_REG1_rFLAGS, +/* REG0 nt_lookup_fn w SUPPRESSED rIP INVALID + REG1 reg [XED_REG_STACKPOP] r SUPPRESSED spw int + MEM0 imm_const [1] r SUPPRESSED spw int + BASE0 nt_lookup_fn rw SUPPRESSED SrSP INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_SSEG0 INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2179*/ xed3_capture_chain_ntluf_REG0_rIP_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT A_GPR_R INVALID + MEM0 imm_const [1] r EXPLICIT zd u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2180*/ xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT A_GPR_R INVALID + MEM0 imm_const [1] r EXPLICIT zd u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 24, 25 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 27, 28, 29 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 30, 31, 32 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2181*/ xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_REG1_rFLAGS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 001 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2182*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2183*/ xed3_capture_nt_nop_ntluf, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2184*/ xed3_capture_nt_nop_ntluf, +/* REG0 reg [XED_REG_RAX] rw SUPPRESSED q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 111 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2185*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_rFLAGS, +/* REG0 reg [XED_REG_RAX] rw SUPPRESSED q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 110 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2186*/ xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_rFLAGS, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 101 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG0 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2187*/ xed3_capture_chain_ntluf_REG0_rFLAGS, +/* REG0 reg [XED_REG_RCX] r SUPPRESSED q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2188*/ xed3_capture_chain_ntluf_REG0_XED_REG_RCX, +/* REG0 reg [XED_REG_ECX] r SUPPRESSED d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2189*/ xed3_capture_chain_ntluf_REG0_XED_REG_ECX, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2190*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2191*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2192*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2193*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2194*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2195*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2196*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2197*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2198*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2199*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2200*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2201*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i1 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i1 + MEM0 imm_const [1] r EXPLICIT dq i1 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2202*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i1 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i1 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2203*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i1 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i1 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i1 + MEM0 imm_const [1] r EXPLICIT dq i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2204*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i1 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i1 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i1 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2205*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i1 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i1 + MEM0 imm_const [1] r EXPLICIT qq i1 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2206*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i1 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i1 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i1 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2207*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i1 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i1 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq i1 + MEM0 imm_const [1] r EXPLICIT qq i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2208*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i1 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i1 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq i1 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2209*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2210*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2211*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2212*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2213*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2214*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2215*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2216*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2217*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2218*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2219*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2220*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2221*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2222*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2223*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2224*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2225*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2226*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2227*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2228*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2229*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2230*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2231*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2232*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2233*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2234*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2235*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2236*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2237*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2238*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2239*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2240*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2241*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2242*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2243*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2244*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2245*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2246*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2247*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2248*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2249*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2250*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2251*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2252*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2253*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2254*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2255*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MEM0 imm_const [1] r EXPLICIT dq i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2256*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2257*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2258*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2259*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2260*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2261*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2262*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2263*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2264*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2265*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2266*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2267*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2268*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2269*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2270*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2271*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2272*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2273*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2274*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2275*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2276*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2277*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2278*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2279*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2280*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2281*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2282*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2283*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2284*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2285*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2286*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2287*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2288*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2289*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2290*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2291*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2292*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2293*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2294*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2295*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2296*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2297*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2298*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2299*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2300*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2301*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2302*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2303*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2304*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2305*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2306*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2307*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2308*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2309*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2310*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2311*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2312*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2313*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2314*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2315*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2316*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2317*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2318*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2319*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2320*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2321*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2322*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2323*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2324*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2325*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2326*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2327*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2328*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2329*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2330*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2331*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2332*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i64 + REG2 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2333*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MEM0 imm_const [1] r EXPLICIT dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2334*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2335*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2336*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2337*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2338*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2339*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2340*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_R y int + MEM0 imm_const [1] r EXPLICIT y int + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2341*/ xed3_capture_chain_ntluf_REG0_VGPRy_R_MEM0_const1_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2342*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_R y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2343*/ xed3_capture_chain_ntluf_REG0_VGPRy_R_REG1_VGPRy_B_IMM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2344*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2345*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2346*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2347*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2348*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2349*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2350*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2351*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2352*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2353*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2354*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2355*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2356*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2357*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2358*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2359*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2360*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2361*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2362*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2363*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2364*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2365*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2366*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2367*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2368*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2369*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2370*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2371*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2372*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2373*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2374*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2375*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2376*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT y int + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2377*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2378*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2379*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2380*/ xed3_capture_chain_ntluf_REG0_VGPRy_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_B y int + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2381*/ xed3_capture_chain_ntluf_REG0_VGPRy_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2382*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_IMM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPR32_B y int + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2383*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPR32_B_IMM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2384*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPRy_N y int + REG1 nt_lookup_fn r EXPLICIT VGPR32_B y int + IMM0 imm_const [1] r EXPLICIT d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2385*/ xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2386*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2387*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2388*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2389*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2390*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2391*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2392*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2393*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2394*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2395*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2396*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2397*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2398*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2399*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2400*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2401*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2402*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2403*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2404*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2405*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2406*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2407*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2408*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2409*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2410*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2411*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2412*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2413*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2414*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2415*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2416*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2417*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2418*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2419*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2420*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2421*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2422*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2423*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2424*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2425*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2426*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2427*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2428*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2429*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2430*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2431*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2432*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2433*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2434*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2435*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2436*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2437*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2438*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2439*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2440*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2441*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2442*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2443*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2444*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2445*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2446*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2447*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2448*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2449*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2450*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2451*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2452*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2453*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2454*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2455*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2456*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2457*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2458*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2459*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2460*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2461*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2462*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2463*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2464*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2465*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2466*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2467*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2468*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2469*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2470*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2471*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2472*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2473*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2474*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2475*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2476*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2477*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2478*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2479*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2480*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2481*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2482*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2483*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2484*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2485*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2486*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2487*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2488*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2489*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2490*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2491*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2492*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2493*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2494*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2495*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2496*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2497*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2498*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2499*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2500*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2501*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2502*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2503*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2504*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2505*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2506*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2507*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2508*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE d f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2509*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2510*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2511*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2512*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE q f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2513*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2514*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2515*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2516*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2517*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2518*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2519*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2520*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2521*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2522*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2523*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2524*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2525*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2526*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2527*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2528*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2529*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2530*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2531*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2532*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2533*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2534*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2535*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2536*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2537*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2538*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2539*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2540*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2541*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2542*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2543*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2544*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2545*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2546*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2547*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2548*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2549*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2550*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2551*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2552*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2553*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2554*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2555*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2556*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2557*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2558*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2559*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2560*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2561*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2562*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2563*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2564*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2565*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2566*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2567*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2568*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2569*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2570*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2571*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2572*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2573*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2574*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2575*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2576*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2577*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2578*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2579*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2580*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2581*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2582*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2583*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2584*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2585*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2586*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R q f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2587*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2588*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R d f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2589*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2590*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2591*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2592*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2593*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2594*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2595*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2596*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2597*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2598*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2599*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2600*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2601*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2602*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2603*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2604*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2605*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2606*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2607*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2608*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2609*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2610*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2611*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2612*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2613*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2614*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2615*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2616*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2617*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2618*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2619*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2620*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2621*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2622*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2623*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2624*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2625*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2626*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2627*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2628*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2629*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2630*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2631*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2632*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2633*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2634*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2635*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2636*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2637*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2638*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2639*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2640*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2641*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2642*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2643*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2644*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2645*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2646*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2647*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2648*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2649*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2650*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2651*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2652*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2653*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2654*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2655*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2656*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2657*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2658*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2659*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2660*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2661*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2662*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2663*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2664*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2665*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2666*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2667*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2668*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2669*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2670*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2671*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2672*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2673*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT YMM_R dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2674*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_R dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2675*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_YMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2676*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2677*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2678*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2679*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2680*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2681*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2682*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B INVALID + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2683*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* inum=2684*/ xed3_capture_nt_nop_ntluf, +/* inum=2685*/ xed3_capture_nt_nop_ntluf, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2686*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2687*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2688*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2689*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2690*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2691*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2692*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2693*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2694*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2695*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2696*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2697*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2698*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2699*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2700*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2701*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2702*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2703*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2704*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2705*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2706*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2707*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2708*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2709*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2710*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2711*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2712*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2713*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2714*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2715*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2716*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2717*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2718*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2719*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2720*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2721*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2722*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2723*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2724*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2725*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + BCAST imm_const [0x14] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2726*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x14, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x14] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2727*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1_BCAST_const0x14, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x14] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2728*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B_IMM0_const1_BCAST_const0x14, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2729*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2730*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2731*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2732*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2733*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2734*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2735*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_N_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2736*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_N_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2737*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2738*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2739*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_N_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=2740*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_N_REG1_YMM_R, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2741*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2742*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2743*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2744*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2745*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2746*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2747*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2748*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2749*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2750*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2751*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=2752*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2753*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2754*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2755*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2756*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2757*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2758*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2759*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2760*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2761*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2762*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2763*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2764*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2765*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2766*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2767*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2768*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2769*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2770*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2771*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2772*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2773*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2774*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2775*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=2776*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2777*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2778*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2779*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2780*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2781*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2782*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2783*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2784*/ xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2785*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2786*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2787*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2788*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2789*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2790*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2791*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2792*/ xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2793*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2794*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2795*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=2796*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2797*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2798*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2799*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2800*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2801*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2802*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2803*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=2804*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2805*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2806*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2807*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2808*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2809*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2810*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2811*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2812*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2813*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2814*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2815*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2816*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2817*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2818*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* MEM0 imm_const [1] w EXPLICIT qq i32 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2819*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2820*/ xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2821*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2822*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2823*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2824*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2825*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2826*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq i32 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2827*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2828*/ xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2829*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2830*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2831*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2832*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2833*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2834*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2835*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2836*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2837*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2838*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + MEM0 imm_const [1] r EXPLICIT qq u256 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2839*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u256 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2840*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2841*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2842*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + MEM0 imm_const [1] r EXPLICIT qq u256 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2843*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u256 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2844*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2845*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2846*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + MEM0 imm_const [1] r EXPLICIT qq u256 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2847*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u256 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2848*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2849*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2850*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + MEM0 imm_const [1] r EXPLICIT qq u256 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2851*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u256 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u256 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u256 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2852*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2853*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2854*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2855*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2856*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2857*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2858*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2859*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2860*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2861*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2862*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2863*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2864*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2865*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2866*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2867*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2868*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2869*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2870*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2871*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2872*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2873*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2874*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2875*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2876*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2877*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=2878*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2879*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2880*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2881*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2882*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2883*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2884*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2885*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2886*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2887*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2888*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2889*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2890*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2891*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2892*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2893*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2894*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2895*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2896*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2897*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2898*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2899*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2900*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2901*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2902*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2903*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2904*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2905*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2906*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2907*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2908*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2909*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2910*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2911*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2912*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2913*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2914*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2915*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2916*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2917*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2918*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2919*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2920*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2921*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2922*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2923*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2924*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2925*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2926*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2927*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2928*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2929*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2930*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2931*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2932*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2933*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2934*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2935*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2936*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2937*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2938*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2939*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2940*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2941*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2942*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2943*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2944*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2945*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2946*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2947*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2948*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2949*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2950*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2951*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2952*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2953*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2954*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MEM0 imm_const [1] r EXPLICIT dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2955*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2956*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i64 + MEM0 imm_const [1] r EXPLICIT qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2957*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2958*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2959*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2960*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2961*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2962*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2963*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2964*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2965*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2966*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2967*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2968*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2969*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2970*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2971*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2972*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2973*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2974*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2975*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2976*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2977*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2978*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2979*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2980*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2981*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2982*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2983*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2984*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2985*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2986*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2987*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2988*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2989*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2990*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2991*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2992*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2993*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2994*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2995*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2996*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2997*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2998*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=2999*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3000*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3001*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3002*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3003*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3004*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3005*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3006*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3007*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3008*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3009*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3010*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MEM0 imm_const [1] r EXPLICIT dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3011*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3012*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i64 + MEM0 imm_const [1] r EXPLICIT qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3013*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3014*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3015*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3016*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3017*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3018*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3019*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3020*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3021*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3022*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3023*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3024*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3025*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3026*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3027*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3028*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3029*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3030*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3031*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3032*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3033*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3034*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3035*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3036*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3037*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3038*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3039*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3040*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3041*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3042*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3043*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3044*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3045*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3046*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3047*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3048*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3049*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3050*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3051*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3052*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3053*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3054*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3055*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3056*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3057*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3058*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3059*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3060*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3061*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3062*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3063*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3064*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3065*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3066*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3067*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3068*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3069*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3070*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3071*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3072*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3073*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3074*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3075*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3076*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3077*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3078*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3079*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3080*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3081*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3082*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3083*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3084*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3085*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3086*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3087*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3088*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3089*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3090*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3091*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3092*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3093*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3094*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3095*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3096*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3097*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3098*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3099*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3100*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3101*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3102*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3103*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3104*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3105*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3106*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3107*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3108*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3109*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3110*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3111*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3112*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3113*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3114*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + MEM0 imm_const [1] r EXPLICIT dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3115*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3116*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i64 + MEM0 imm_const [1] r EXPLICIT qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3117*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3118*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3119*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3120*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3121*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3122*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3123*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3124*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3125*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3126*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3127*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3128*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3129*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3130*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3131*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3132*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3133*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3134*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3135*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3136*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3137*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3138*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3139*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3140*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3141*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3142*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3143*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3144*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3145*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3146*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3147*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3148*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3149*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3150*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3151*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3152*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3153*/ xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3154*/ xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3155*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3156*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3157*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3158*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3159*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3160*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3161*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3162*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3163*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3164*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3165*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3166*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3167*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3168*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3169*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3170*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3171*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3172*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3173*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3174*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3175*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3176*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3177*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3178*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3179*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3180*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3181*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3182*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3183*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3184*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3185*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3186*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3187*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3188*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3189*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3190*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3191*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3192*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3193*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3194*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3195*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3196*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3197*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3198*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3199*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3200*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3201*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3202*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3203*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3204*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3205*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3206*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3207*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3208*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3209*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3210*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3211*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3212*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3213*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3214*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3215*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3216*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3217*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3218*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3219*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3220*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3221*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3222*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3223*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3224*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3225*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3226*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3227*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3228*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3229*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3230*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3231*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3232*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3233*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3234*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3235*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3236*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3237*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3238*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3239*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3240*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3241*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3242*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3243*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3244*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3245*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3246*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3247*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3248*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3249*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3250*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3251*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3252*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3253*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3254*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3255*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3256*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3257*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3258*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3259*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3260*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3261*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3262*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3263*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3264*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3265*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3266*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3267*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3268*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3269*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3270*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3271*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3272*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3273*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3274*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3275*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3276*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3277*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3278*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3279*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3280*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3281*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3282*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3283*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3284*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3285*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3286*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3287*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3288*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3289*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3290*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3291*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3292*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3293*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3294*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3295*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3296*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3297*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i16 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3298*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3299*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i16 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3300*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3301*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3302*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3303*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3304*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3305*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3306*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3307*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3308*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3309*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3310*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3311*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3312*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3313*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3314*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3315*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3316*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3317*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3318*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3319*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3320*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3321*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3322*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3323*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3324*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3325*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3326*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3327*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3328*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3329*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3330*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3331*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_R d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3332*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_N_REG2_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3333*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3334*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3335*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_R q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3336*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_N_REG2_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3337*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3338*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3339*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3340*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3341*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3342*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3343*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3344*/ xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3345*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3346*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3347*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3348*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3349*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3350*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3351*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3352*/ xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3353*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3354*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3355*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3356*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3357*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3358*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3359*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3360*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3361*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3362*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3363*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3364*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3365*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3366*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3367*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i16 + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3368*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3369*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i16 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3370*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3371*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3372*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3373*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3374*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B w i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3375*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT w i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3376*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3377*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3378*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3379*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3380*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3381*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3382*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3383*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT d i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3384*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3385*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3386*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3387*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i64 + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3388*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3389*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i64 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3390*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3391*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT q u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3392*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3393*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3394*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3395*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT d u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3396*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3397*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + MEM0 imm_const [1] r EXPLICIT q u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3398*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B w u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3399*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT w u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3400*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3401*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT d u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3402*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3403*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT q u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3404*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3405*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3406*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3407*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT d u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3408*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3409*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT q u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3410*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3411*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT q u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3412*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3413*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3414*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3415*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3416*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT w i16 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3417*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3418*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3419*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q i64 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3420*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3421*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3422*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3423*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3424*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3425*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3426*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3427*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + MEM0 imm_const [1] r EXPLICIT w u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3428*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3429*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3430*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3431*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3432*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3433*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3434*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3435*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3436*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_ECX_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3437*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_ECX_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3438*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_ECX_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3439*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_ECX_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3440*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_RCX_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3441*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_RCX_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3442*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_ECX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3443*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_ECX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3444*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_ECX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_ECX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3445*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_ECX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3446*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RCX_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_RCX] w SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3447*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RCX_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3448*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3449*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_XMM0_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3450*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_EAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3451*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_XMM0_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG2 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG3 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG4 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3452*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_XMM0_REG4_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_RAX] r SUPPRESSED INVALID + REG3 reg [XED_REG_RDX] r SUPPRESSED INVALID + REG4 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 + REG5 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3453*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_XMM0_REG5_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG1 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3454*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_XMM0_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + REG2 reg [XED_REG_XMM0] w SUPPRESSED dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3455*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_XMM0_REG3_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MEM0 imm_const [1] w SUPPRESSED dq u8 + BASE0 nt_lookup_fn r SUPPRESSED ArDI INVALID + SEG0 nt_lookup_fn r SUPPRESSED FINAL_DSEG INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3456*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG, +/* MEM0 imm_const [1] r EXPLICIT d i32 + REG0 reg [XED_REG_MXCSR] w SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3457*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_MXCSR, +/* MEM0 imm_const [1] w EXPLICIT d i32 + REG0 reg [XED_REG_MXCSR] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3458*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_MXCSR, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3459*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i8 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3460*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3461*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3462*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3463*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3464*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3465*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3466*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_SE dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3467*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_SE dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3468*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_SE qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3469*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_SE qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3470*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3471*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3472*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3473*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq i32 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3474*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3475*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3476*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3477*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3478*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3479*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3480*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3481*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3482*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3483*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3484*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3485*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3486*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3487*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3488*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3489*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3490*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3491*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3492*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3493*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3494*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3495*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3496*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3497*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3498*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3499*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3500*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3501*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3502*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT q f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3503*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B q f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3504*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT dq f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3505*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3506*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B, +/* MEM0 imm_const [1] w EXPLICIT q f16 + REG0 nt_lookup_fn r EXPLICIT XMM_R dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3507*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B q f16 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3508*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f16 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3509*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq f16 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3510*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_YMM_R_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3511*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3512*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3513*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3514*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3515*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3516*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3517*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3518*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3519*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3520*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3521*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3522*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3523*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3524*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3525*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3526*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3527*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3528*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3529*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3530*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3531*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3532*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3533*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3534*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3535*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3536*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3537*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3538*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3539*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3540*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3541*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3542*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3543*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3544*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3545*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3546*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3547*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3548*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3549*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3550*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3551*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3552*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3553*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3554*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3555*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3556*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3557*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3558*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3559*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3560*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3561*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3562*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3563*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3564*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3565*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3566*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3567*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3568*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3569*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3570*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3571*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3572*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3573*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3574*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3575*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3576*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3577*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3578*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3579*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3580*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3581*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3582*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3583*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3584*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3585*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3586*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3587*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3588*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3589*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3590*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3591*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3592*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3593*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3594*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3595*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3596*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3597*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3598*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3599*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3600*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3601*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3602*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3603*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3604*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3605*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3606*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3607*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3608*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3609*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3610*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3611*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3612*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3613*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3614*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3615*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3616*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3617*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3618*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3619*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3620*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3621*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3622*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3623*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3624*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3625*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3626*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3627*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3628*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3629*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3630*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3631*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3632*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3633*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3634*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3635*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3636*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3637*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3638*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3639*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3640*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3641*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3642*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3643*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3644*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3645*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3646*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3647*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3648*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3649*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3650*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3651*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3652*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3653*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3654*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3655*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3656*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3657*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3658*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3659*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3660*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3661*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3662*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3663*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3664*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3665*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3666*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3667*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3668*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3669*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3670*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3671*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3672*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3673*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3674*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3675*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3676*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3677*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3678*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3679*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3680*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3681*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3682*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3683*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3684*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3685*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3686*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3687*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3688*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3689*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3690*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3691*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3692*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3693*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f64 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3694*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3695*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3696*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3697*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3698*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3699*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N q f64 + REG2 nt_lookup_fn r EXPLICIT XMM_B q f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3700*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3701*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N d f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B d f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3702*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn crw EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG1 nt_lookup_fn rw EXPLICIT YMM_N qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3703*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3704*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT YMM_R qq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG1 nt_lookup_fn rw EXPLICIT YMM_N qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3705*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3706*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG1 nt_lookup_fn rw EXPLICIT YMM_N qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3707*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3708*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3709*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R q f32 + MEM0 imm_const [1] r EXPLICIT d f32 + REG1 nt_lookup_fn rw EXPLICIT XMM_N q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3710*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + REG1 nt_lookup_fn rw EXPLICIT YMM_N qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3711*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3712*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT YMM_R qq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + REG1 nt_lookup_fn rw EXPLICIT YMM_N qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3713*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3714*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + REG1 nt_lookup_fn rw EXPLICIT YMM_N qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3715*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3716*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + REG1 nt_lookup_fn rw EXPLICIT XMM_N dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3717*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn crw EXPLICIT XMM_R q u32 + MEM0 imm_const [1] r EXPLICIT d u32 + REG1 nt_lookup_fn rw EXPLICIT XMM_N q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3718*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3719*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3720*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u128 + REG0 nt_lookup_fn r EXPLICIT YMM_R qq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3721*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B dq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3722*/ xed3_capture_chain_ntluf_REG0_XMM_B_REG1_YMM_R_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3723*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3724*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3725*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_N_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3726*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_N_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3727*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3728*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT XMM_N dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_R dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3729*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_N_REG1_XMM_R, +/* MEM0 imm_const [1] w EXPLICIT qq u64 + REG0 nt_lookup_fn r EXPLICIT YMM_N qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_R qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3730*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_N_REG1_YMM_R, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3731*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u128 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3732*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3733*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3734*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3735*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f64 + REG1 nt_lookup_fn r EXPLICIT YMM_B qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3736*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3737*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3738*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3739*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq f32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq f32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3740*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3741*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3742*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3743*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3744*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + MEM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x11] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3745*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0x11, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B b u8 + BCAST imm_const [0x11] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3746*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0x11, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + MEM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x12] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3747*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x12, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B b u8 + BCAST imm_const [0x12] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3748*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x12, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + MEM0 imm_const [1] r EXPLICIT w u16 + BCAST imm_const [0xe] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3749*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xe, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B w u16 + BCAST imm_const [0xe] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3750*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xe, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + MEM0 imm_const [1] r EXPLICIT w u16 + BCAST imm_const [0xf] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3751*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xf, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B w u16 + BCAST imm_const [0xf] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3752*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xf, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3753*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3754*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3755*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B d u32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3756*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + BCAST imm_const [0xb] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3757*/ xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xb, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u64 + BCAST imm_const [0xb] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3758*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xb, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3759*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B q u64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3760*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + BCAST imm_const [0x14] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3761*/ xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x14, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3762*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3763*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3764*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3765*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3766*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3767*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3768*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3769*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3770*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3771*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3772*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3773*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3774*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3775*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3776*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3777*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3778*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq i32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3779*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3780*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq i32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3781*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3782*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3783*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3784*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3785*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3786*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3787*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3788*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3789*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3790*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3791*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3792*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3793*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3794*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3795*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3796*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3797*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3798*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3799*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3800*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3801*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3802*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3803*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3804*/ xed3_capture_chain_ntluf_REG0_VGPR64_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3805*/ xed3_capture_chain_ntluf_REG0_VGPR64_N_REG1_VGPR64_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3806*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3807*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3808*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3809*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3810*/ xed3_capture_chain_ntluf_REG0_VGPR64_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3811*/ xed3_capture_chain_ntluf_REG0_VGPR64_N_REG1_VGPR64_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3812*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3813*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3814*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3815*/ xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3816*/ xed3_capture_chain_ntluf_REG0_VGPR64_N_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3817*/ xed3_capture_chain_ntluf_REG0_VGPR64_N_REG1_VGPR64_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3818*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3819*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3820*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3821*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3822*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3823*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3824*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3825*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3826*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3827*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3828*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 + REG3 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3829*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N_REG3_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3830*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3831*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3832*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3833*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3834*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3835*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3836*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3837*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3838*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3839*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3840*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3841*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3842*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3843*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3844*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_N d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3845*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3846*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_N q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3847*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3848*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_XED_REG_EDX, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + REG2 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + REG3 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3849*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_XED_REG_EDX, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 13, 14 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 16, 17, 18 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 19, 20, 21 inum=3850*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_XED_REG_EDX, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn w EXPLICIT VGPR32_N d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + REG2 reg [XED_REG_EDX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3851*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_XED_REG_EDX, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + REG2 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + REG3 reg [XED_REG_RDX] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3852*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B_REG3_XED_REG_RDX, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn w EXPLICIT VGPR64_N q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + REG2 reg [XED_REG_RDX] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 14, 15 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 20, 21, 22 inum=3853*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1_REG2_XED_REG_RDX, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3854*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT VGPR32_B d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3855*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 15, 16 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 21, 22, 23 inum=3856*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3857*/ xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT VGPR64_B q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3858*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT VGPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 16, 17 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 19, 20, 21 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 22, 23, 24 inum=3859*/ xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3860*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3861*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3862*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + MEM0 imm_const [1] r EXPLICIT wrd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3863*/ xed3_capture_chain_ntluf_REG0_MASK_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT wrd u16 + REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3864*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK_R, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3865*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3866*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3867*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3868*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3869*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3870*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3871*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3872*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3873*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3874*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3875*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3876*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3877*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3878*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3879*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3880*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3881*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3882*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3883*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3884*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3885*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + MEM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3886*/ xed3_capture_chain_ntluf_REG0_MASK_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3887*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK_R, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3888*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3889*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3890*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3891*/ xed3_capture_chain_ntluf_REG0_MASK_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3892*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK_R, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3893*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3894*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3895*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3896*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3897*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3898*/ xed3_capture_chain_ntluf_REG0_MASK_R_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3899*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK_R, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3900*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3901*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3902*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3903*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3904*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3905*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3906*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3907*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3908*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3909*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3910*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3911*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3912*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3913*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3914*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3915*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3916*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3917*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3918*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3919*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=3920*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3921*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3922*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3923*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3924*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3925*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3926*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3927*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK_N mskw i1 + REG2 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3928*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3929*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3930*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3931*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3932*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3933*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3934*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3935*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3936*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3937*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3938*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3939*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3940*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3941*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3942*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3943*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3944*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3945*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3946*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3947*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3948*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3949*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3950*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3951*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3952*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3953*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R dq i32 + REG1 nt_lookup_fn r EXPLICIT XMM_N dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3954*/ xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3955*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R qq i32 + REG1 nt_lookup_fn r EXPLICIT YMM_N qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3956*/ xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT zd i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3957*/ xed3_capture_chain_ntluf_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT zd i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3958*/ xed3_capture_chain_ntluf_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT TMM_R tv f32 + REG1 nt_lookup_fn r EXPLICIT TMM_B tv u32 + REG2 nt_lookup_fn r EXPLICIT TMM_N tv u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3959*/ xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N, +/* REG0 nt_lookup_fn rw EXPLICIT TMM_R tv i32 + REG1 nt_lookup_fn r EXPLICIT TMM_B tv u32 + REG2 nt_lookup_fn r EXPLICIT TMM_N tv u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3960*/ xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N, +/* REG0 nt_lookup_fn rw EXPLICIT TMM_R tv i32 + REG1 nt_lookup_fn r EXPLICIT TMM_B tv u32 + REG2 nt_lookup_fn r EXPLICIT TMM_N tv u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3961*/ xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N, +/* REG0 nt_lookup_fn rw EXPLICIT TMM_R tv i32 + REG1 nt_lookup_fn r EXPLICIT TMM_B tv u32 + REG2 nt_lookup_fn r EXPLICIT TMM_N tv u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3962*/ xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N, +/* REG0 nt_lookup_fn rw EXPLICIT TMM_R tv u32 + REG1 nt_lookup_fn r EXPLICIT TMM_B tv u32 + REG2 nt_lookup_fn r EXPLICIT TMM_N tv u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3963*/ xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N, +/* REG0 nt_lookup_fn w EXPLICIT TMM_R tv u32 + MEM0 imm_const [1] r EXPLICIT ptr u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3964*/ xed3_capture_chain_ntluf_REG0_TMM_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT TMM_R tv u32 + MEM0 imm_const [1] r EXPLICIT ptr u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3965*/ xed3_capture_chain_ntluf_REG0_TMM_R_MEM0_const1, +/* MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3966*/ xed3_capture_nt_nop_ntluf, +/* MEM0 imm_const [1] w EXPLICIT ptr u32 + REG0 nt_lookup_fn r EXPLICIT TMM_R tv u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3967*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_TMM_R, +/* REG0 nt_lookup_fn w EXPLICIT TMM_R tv u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 12, 13 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm 000 (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3968*/ xed3_capture_chain_ntluf_REG0_TMM_R, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3969*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3970*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3971*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3972*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3973*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3974*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3975*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3976*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3977*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3978*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3979*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3980*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3981*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3982*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3983*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3984*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3985*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3986*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3987*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3988*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3989*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3990*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3991*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3992*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3993*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3994*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3995*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3996*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zbf16 bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3997*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zbf16 bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=3998*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=3999*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4000*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4001*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4002*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4003*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq bf16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4004*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4005*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4006*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4007*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4008*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4009*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4010*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4011*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4012*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4013*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4014*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4015*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4016*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4017*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4018*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4019*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4020*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4021*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4022*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4023*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4024*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4025*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4026*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4027*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4028*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4029*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4030*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4031*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4032*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4033*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4034*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4035*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4036*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4037*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4038*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4039*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4040*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4041*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4042*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4043*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4044*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4045*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4046*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4047*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4048*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4049*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4050*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4051*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 101 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4052*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4053*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4054*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4055*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* MEM0 imm_const [1] r EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4056*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 MULTIREG4 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4057*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 MULTIREG4 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4058*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 MULTIREG4 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4059*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 MULTIREG4 + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4060*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 MULTIREG4 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4061*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 MULTIREG4 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4062*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4063*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4064*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4065*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4066*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4067*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4068*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4069*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4070*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4071*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4072*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4073*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4074*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4075*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4076*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4077*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4078*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4079*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4080*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4081*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4082*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4083*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4084*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4085*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4086*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4087*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4088*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4089*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4090*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4091*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4092*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4093*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4094*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4095*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4096*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4097*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4098*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4099*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4100*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4101*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4102*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4103*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4104*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4105*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4106*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4107*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4108*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4109*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4110*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4111*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4112*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4113*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4114*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4115*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4116*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4117*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4118*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + BCAST imm_const [0x2] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4119*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x2, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + BCAST imm_const [0x4] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4120*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x4, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f64 + BCAST imm_const [0x6] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4121*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x6, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u32 + BCAST imm_const [0x2] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4122*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x2, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u32 + BCAST imm_const [0x4] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4123*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x4, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u64 + BCAST imm_const [0x6] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4124*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x6, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f64 + BCAST imm_const [0x5] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4125*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x5, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + BCAST imm_const [0x5] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4126*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x5, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4127*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4128*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d f32 + BCAST imm_const [0x1] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4129*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + BCAST imm_const [0x1] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4130*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d f32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4131*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4132*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d f32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4133*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4134*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4135*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4136*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4137*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4138*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4139*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4140*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4141*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4142*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4143*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4144*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4145*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4146*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4147*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4148*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4149*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4150*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4151*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4152*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4153*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4154*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=4155*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=4156*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=4157*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=4158*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=4159*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=4160*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS, +/* MEM0 imm_const [1] w EXPLICIT zd f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4161*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4162*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4163*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4164*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4165*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4166*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4167*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4168*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4169*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4170*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4171*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4172*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4173*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4174*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4175*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4176*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4177*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4178*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4179*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4180*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4181*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4182*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4183*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4184*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4185*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4186*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4187*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4188*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4189*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4190*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4191*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4192*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4193*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4194*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4195*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4196*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4197*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4198*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4199*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4200*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4201*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4202*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4203*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4204*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4205*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4206*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4207*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4208*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4209*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4210*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4211*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4212*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4213*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4214*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4215*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4216*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4217*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4218*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4219*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4220*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4221*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4222*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4223*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4224*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4225*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4226*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4227*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4228*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4229*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4230*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT qq f16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4231*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4232*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4233*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4234*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4235*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4236*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4237*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4238*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4239*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4240*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4241*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4242*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4243*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4244*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4245*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4246*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4247*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4248*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4249*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4250*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4251*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4252*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4253*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4254*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4255*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4256*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4257*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4258*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4259*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4260*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4261*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4262*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4263*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4264*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4265*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4266*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4267*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4268*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4269*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4270*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4271*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4272*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4273*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4274*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4275*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4276*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4277*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4278*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4279*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4280*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4281*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4282*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4283*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4284*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4285*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4286*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4287*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4288*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4289*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4290*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4291*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4292*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4293*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4294*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4295*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4296*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4297*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4298*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4299*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4300*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4301*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4302*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4303*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4304*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4305*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4306*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4307*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4308*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4309*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4310*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4311*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4312*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4313*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4314*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4315*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4316*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4317*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4318*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4319*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4320*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4321*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4322*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4323*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4324*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4325*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4326*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4327*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4328*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4329*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4330*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4331*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4332*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4333*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4334*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4335*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4336*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4337*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4338*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4339*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4340*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4341*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4342*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4343*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4344*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4345*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4346*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4347*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4348*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4349*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4350*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4351*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4352*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4353*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4354*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4355*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4356*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4357*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4358*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4359*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4360*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4361*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4362*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4363*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4364*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4365*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4366*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4367*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4368*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4369*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4370*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4371*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4372*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4373*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4374*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4375*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4376*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4377*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4378*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4379*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4380*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4381*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4382*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4383*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4384*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4385*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4386*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4387*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4388*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4389*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4390*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4391*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4392*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4393*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4394*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4395*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4396*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4397*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4398*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4399*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4400*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4401*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4402*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4403*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4404*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4405*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4406*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4407*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4408*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4409*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4410*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4411*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4412*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4413*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4414*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4415*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4416*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4417*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4418*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4419*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4420*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4421*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4422*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4423*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4424*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4425*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4426*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4427*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4428*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4429*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4430*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4431*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4432*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4433*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4434*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4435*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4436*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4437*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT qq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4438*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d f32 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4439*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4440*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4441*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4442*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4443*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4444*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4445*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4446*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4447*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4448*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4449*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4450*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4451*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4452*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4453*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4454*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4455*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4456*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4457*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4458*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4459*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4460*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4461*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4462*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4463*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4464*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4465*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4466*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4467*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4468*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4469*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4470*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4471*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4472*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4473*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4474*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4475*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4476*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4477*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4478*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4479*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4480*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4481*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4482*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4483*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4484*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4485*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4486*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4487*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4488*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4489*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4490*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4491*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4492*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4493*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4494*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4495*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4496*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4497*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4498*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4499*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4500*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4501*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4502*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4503*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4504*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4505*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4506*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4507*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4508*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4509*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4510*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4511*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4512*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4513*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4514*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4515*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4516*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4517*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4518*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4519*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4520*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4521*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4522*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4523*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4524*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4525*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4526*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4527*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4528*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4529*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4530*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4531*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4532*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4533*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4534*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4535*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4536*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4537*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4538*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4539*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4540*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4541*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4542*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4543*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4544*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4545*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4546*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4547*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4548*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4549*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4550*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4551*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4552*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4553*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4554*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4555*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4556*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4557*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4558*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4559*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4560*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4561*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4562*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4563*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4564*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4565*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4566*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4567*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4568*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4569*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4570*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4571*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4572*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4573*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4574*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4575*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4576*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4577*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4578*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4579*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4580*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4581*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4582*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4583*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4584*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4585*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4586*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4587*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4588*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4589*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4590*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4591*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4592*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4593*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4594*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4595*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4596*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4597*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4598*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4599*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4600*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4601*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4602*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4603*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4604*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4605*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4606*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4607*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4608*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4609*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4610*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4611*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4612*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4613*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4614*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4615*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4616*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4617*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4618*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4619*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4620*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4621*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4622*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4623*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4624*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4625*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4626*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4627*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4628*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4629*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4630*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4631*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4632*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4633*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4634*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4635*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4636*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4637*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4638*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4639*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4640*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4641*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4642*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4643*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4644*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4645*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4646*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4647*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4648*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4649*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4650*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4651*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4652*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4653*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4654*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4655*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4656*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4657*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4658*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4659*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4660*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4661*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4662*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4663*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4664*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4665*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4666*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4667*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4668*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4669*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4670*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4671*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4672*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4673*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4674*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4675*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4676*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4677*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4678*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4679*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4680*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4681*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4682*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4683*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4684*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4685*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4686*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4687*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4688*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4689*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4690*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4691*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4692*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4693*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4694*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4695*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4696*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4697*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4698*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4699*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4700*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4701*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4702*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4703*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4704*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4705*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4706*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4707*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4708*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4709*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4710*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4711*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4712*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4713*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4714*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4715*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4716*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4717*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4718*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4719*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4720*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4721*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4722*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4723*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4724*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4725*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4726*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4727*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4728*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4729*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4730*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4731*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4732*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4733*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4734*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4735*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4736*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4737*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4738*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4739*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4740*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4741*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4742*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4743*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4744*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4745*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4746*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4747*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4748*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4749*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4750*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4751*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4752*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4753*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4754*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4755*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4756*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4757*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4758*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4759*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4760*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4761*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4762*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4763*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4764*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4765*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4766*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4767*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4768*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4769*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4770*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4771*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4772*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4773*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4774*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4775*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4776*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4777*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4778*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4779*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4780*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4781*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4782*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4783*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4784*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4785*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4786*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4787*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4788*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4789*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4790*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4791*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4792*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4793*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4794*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4795*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4796*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4797*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4798*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4799*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4800*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4801*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4802*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4803*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4804*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4805*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4806*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4807*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4808*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4809*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4810*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4811*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4812*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4813*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4814*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4815*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4816*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4817*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4818*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4819*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4820*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4821*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4822*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4823*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4824*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4825*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4826*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4827*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4828*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4829*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4830*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4831*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4832*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4833*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4834*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4835*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4836*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4837*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4838*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4839*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4840*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4841*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4842*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4843*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4844*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4845*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4846*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4847*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4848*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4849*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4850*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4851*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4852*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4853*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4854*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4855*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4856*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4857*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4858*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4859*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4860*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4861*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4862*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4863*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4864*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4865*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4866*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4867*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4868*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4869*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4870*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4871*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4872*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4873*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4874*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4875*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4876*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4877*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4878*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4879*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4880*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4881*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4882*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4883*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4884*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4885*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4886*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4887*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4888*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4889*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4890*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4891*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4892*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4893*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4894*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4895*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4896*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4897*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4898*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4899*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4900*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4901*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4902*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4903*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4904*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4905*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4906*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4907*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4908*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4909*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4910*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4911*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4912*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4913*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4914*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4915*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4916*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4917*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4918*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4919*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4920*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4921*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4922*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4923*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4924*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4925*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4926*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4927*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4928*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4929*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4930*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4931*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4932*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4933*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4934*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4935*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4936*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4937*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4938*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4939*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4940*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4941*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4942*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4943*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4944*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4945*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4946*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4947*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4948*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4949*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4950*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4951*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4952*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4953*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4954*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4955*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4956*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4957*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4958*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4959*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4960*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4961*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4962*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4963*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4964*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4965*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4966*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4967*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4968*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4969*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4970*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4971*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4972*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4973*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4974*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4975*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4976*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4977*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 q f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4978*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4979*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 q f32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4980*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4981*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 q f32 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 q f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4982*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4983*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4984*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4985*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 q f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4986*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u32 + REG0 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4987*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4988*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4989*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT zd u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4990*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4991*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4992*/ xed3_capture_chain_ntluf_REG0_YMM_R3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT zd f64 + REG0 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4993*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4994*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4995*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd f32 + REG0 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4996*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4997*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=4998*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=4999*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5000*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5001*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5002*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5003*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5004*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5005*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5006*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5007*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5008*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5009*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5010*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5011*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5012*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5013*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5014*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5015*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5016*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5017*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5018*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5019*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5020*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5021*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5022*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5023*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5024*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5025*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5026*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5027*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5028*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5029*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5030*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5031*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5032*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5033*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5034*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5035*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5036*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5037*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5038*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5039*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5040*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5041*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5042*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5043*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5044*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5045*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5046*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5047*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5048*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5049*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5050*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5051*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5052*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5053*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5054*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5055*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5056*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5057*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5058*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5059*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5060*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5061*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5062*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5063*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5064*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5065*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5066*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5067*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5068*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5069*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5070*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5071*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5072*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5073*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5074*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5075*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5076*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5077*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5078*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5079*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5080*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5081*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5082*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5083*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5084*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5085*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5086*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5087*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5088*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5089*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5090*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5091*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5092*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5093*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5094*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5095*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5096*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5097*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5098*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5099*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5100*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5101*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5102*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5103*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5104*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5105*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5106*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5107*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5108*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5109*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5110*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5111*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5112*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5113*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5114*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5115*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5116*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5117*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5118*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5119*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5120*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5121*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5122*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5123*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5124*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5125*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5126*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5127*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5128*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5129*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5130*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d u32 + BCAST imm_const [0x1] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5131*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + BCAST imm_const [0x1] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5132*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + BCAST imm_const [0x1] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5133*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + BCAST imm_const [0x1] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5134*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d u32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5135*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5136*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5137*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + BCAST imm_const [0xa] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5138*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xa, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d u32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5139*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5140*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5141*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + BCAST imm_const [0x3] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5142*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q u64 + BCAST imm_const [0x5] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5143*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x5, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + BCAST imm_const [0x5] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5144*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x5, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + BCAST imm_const [0x5] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5145*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0x5, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q u64 + BCAST imm_const [0xb] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5146*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xb, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + BCAST imm_const [0xb] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5147*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xb, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + BCAST imm_const [0xb] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5148*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0xb, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q u64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5149*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5150*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + BCAST imm_const [0xd] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5151*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0xd, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5152*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5153*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5154*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5155*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5156*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5157*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5158*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5159*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5160*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5161*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5162*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5163*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5164*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5165*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5166*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5167*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5168*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5169*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5170*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5171*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5172*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5173*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5174*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5175*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5176*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5177*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5178*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5179*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5180*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5181*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi64 i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5182*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5183*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5184*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5185*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5186*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5187*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5188*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5189*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5190*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5191*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5192*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5193*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5194*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5195*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5196*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5197*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5198*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5199*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT zd u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5200*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5201*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5202*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5203*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5204*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5205*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5206*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5207*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5208*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5209*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5210*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5211*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5212*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5213*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5214*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5215*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5216*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5217*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5218*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5219*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5220*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5221*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5222*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5223*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5224*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5225*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5226*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5227*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5228*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5229*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5230*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5231*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5232*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5233*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5234*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5235*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5236*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5237*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5238*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5239*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5240*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5241*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5242*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5243*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5244*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5245*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5246*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5247*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5248*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5249*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5250*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5251*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5252*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5253*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5254*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5255*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5256*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5257*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5258*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5259*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5260*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5261*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5262*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5263*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5264*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5265*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5266*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5267*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5268*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5269*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5270*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5271*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5272*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5273*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5274*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5275*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5276*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5277*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5278*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5279*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5280*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5281*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5282*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5283*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5284*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5285*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5286*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5287*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5288*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5289*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5290*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5291*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5292*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5293*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5294*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5295*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5296*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5297*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5298*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5299*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5300*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5301*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5302*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5303*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5304*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5305*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5306*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5307*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5308*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5309*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5310*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5311*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5312*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5313*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5314*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5315*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5316*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5317*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5318*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5319*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5320*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5321*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5322*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5323*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5324*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5325*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5326*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5327*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5328*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5329*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5330*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5331*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5332*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5333*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5334*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5335*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5336*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5337*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5338*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5339*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5340*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5341*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5342*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5343*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5344*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5345*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5346*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5347*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5348*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5349*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5350*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5351*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5352*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5353*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5354*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5355*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5356*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5357*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5358*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5359*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5360*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5361*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5362*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5363*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5364*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5365*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5366*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5367*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5368*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5369*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5370*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5371*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5372*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5373*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5374*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5375*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5376*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5377*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5378*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5379*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5380*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5381*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5382*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5383*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5384*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5385*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5386*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5387*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5388*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5389*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5390*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5391*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5392*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5393*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5394*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT wrd u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5395*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5396*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5397*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5398*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5399*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5400*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5401*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5402*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5403*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5404*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5405*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5406*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5407*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5408*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5409*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5410*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zi32 i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5411*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5412*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5413*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5414*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5415*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5416*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq i16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zi32 i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5417*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5418*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q i16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5419*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5420*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq i16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5421*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5422*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zi64 i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5423*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5424*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT wrd i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5425*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5426*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5427*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5428*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq i32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zi64 i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5429*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5430*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q i32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5431*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5432*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq i32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5433*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5434*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq i16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zi64 i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5435*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5436*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d i16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5437*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5438*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q i16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5439*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5440*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5441*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5442*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5443*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5444*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5445*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5446*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5447*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5448*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT wrd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5449*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5450*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5451*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5452*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5453*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5454*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5455*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5456*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5457*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5458*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5459*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5460*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5461*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5462*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5463*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5464*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5465*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5466*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5467*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5468*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5469*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5470*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5471*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5472*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5473*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5474*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5475*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5476*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5477*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5478*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5479*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5480*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5481*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5482*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5483*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5484*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT wrd u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5485*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5486*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5487*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5488*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5489*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5490*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5491*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5492*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5493*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5494*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5495*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5496*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5497*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5498*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5499*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5500*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5501*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5502*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5503*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5504*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5505*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5506*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5507*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5508*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT wrd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5509*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5510*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5511*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5512*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5513*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5514*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5515*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5516*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5517*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5518*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5519*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5520*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5521*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5522*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5523*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5524*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5525*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5526*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT d i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5527*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5528*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5529*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi64 i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5530*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi64 i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5531*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5532*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5533*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5534*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i64 + MEM0 imm_const [1] r EXPLICIT vv i64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5535*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5536*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5537*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5538*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5539*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5540*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5541*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5542*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5543*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5544*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5545*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5546*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5547*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5548*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5549*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5550*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5551*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5552*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5553*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5554*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5555*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5556*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5557*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5558*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5559*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5560*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5561*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5562*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5563*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5564*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5565*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5566*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5567*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5568*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5569*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5570*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 001 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5571*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5572*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5573*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5574*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5575*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5576*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5577*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5578*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5579*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5580*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5581*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5582*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5583*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5584*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5585*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5586*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5587*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5588*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5589*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5590*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5591*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5592*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5593*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5594*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 000 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5595*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5596*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5597*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5598*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5599*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5600*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5601*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5602*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5603*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5604*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5605*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5606*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5607*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5608*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5609*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5610*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5611*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5612*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5613*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5614*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5615*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5616*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5617*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5618*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5619*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5620*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5621*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5622*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5623*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5624*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5625*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5626*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5627*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5628*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5629*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5630*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5631*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5632*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5633*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5634*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5635*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5636*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5637*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5638*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5639*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5640*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5641*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5642*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5643*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5644*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5645*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5646*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5647*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5648*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5649*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5650*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5651*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5652*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5653*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5654*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5655*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5656*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5657*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5658*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5659*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5660*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5661*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5662*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5663*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5664*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5665*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5666*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5667*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5668*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5669*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5670*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5671*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5672*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5673*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5674*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5675*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5676*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5677*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5678*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5679*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5680*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5681*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5682*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5683*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5684*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5685*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5686*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5687*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5688*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5689*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5690*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5691*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5692*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5693*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5694*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5695*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5696*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5697*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5698*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5699*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5700*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5701*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5702*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5703*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5704*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5705*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5706*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT dq u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5707*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5708*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5709*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5710*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5711*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5712*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5713*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5714*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5715*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5716*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5717*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5718*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5719*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5720*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5721*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5722*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5723*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5724*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5725*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5726*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5727*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5728*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5729*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5730*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5731*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5732*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5733*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5734*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5735*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5736*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5737*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5738*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5739*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5740*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5741*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5742*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5743*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5744*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5745*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5746*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5747*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5748*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5749*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5750*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5751*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5752*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5753*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5754*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5755*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5756*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5757*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5758*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5759*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5760*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5761*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5762*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5763*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5764*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5765*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5766*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5767*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5768*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5769*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5770*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5771*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5772*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5773*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5774*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5775*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5776*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5777*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5778*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5779*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5780*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5781*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5782*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5783*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5784*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5785*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5786*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5787*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5788*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5789*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5790*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5791*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5792*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5793*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5794*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5795*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5796*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5797*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5798*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5799*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5800*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5801*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5802*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5803*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5804*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5805*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5806*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5807*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5808*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5809*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5810*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5811*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5812*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5813*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5814*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5815*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5816*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5817*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5818*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5819*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5820*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5821*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5822*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5823*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5824*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5825*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5826*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5827*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5828*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5829*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5830*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5831*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5832*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5833*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5834*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5835*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5836*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5837*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5838*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5839*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5840*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5841*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5842*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5843*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5844*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5845*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5846*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5847*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5848*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5849*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5850*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5851*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5852*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5853*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5854*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5855*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5856*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5857*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5858*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5859*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5860*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5861*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5862*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5863*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5864*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5865*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5866*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5867*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5868*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5869*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5870*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5871*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5872*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5873*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5874*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5875*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5876*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5877*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5878*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5879*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5880*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5881*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5882*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5883*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5884*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5885*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5886*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5887*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5888*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5889*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5890*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5891*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5892*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5893*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5894*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5895*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5896*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5897*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q f64 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5898*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5899*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5900*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT d f32 + REG0 nt_lookup_fn rw EXPLICIT MASKNOT0 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm 100 (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5901*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5902*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5903*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5904*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5905*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5906*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5907*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5908*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5909*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5910*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5911*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5912*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5913*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5914*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5915*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5916*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5917*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5918*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5919*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5920*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5921*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5922*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5923*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5924*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5925*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5926*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5927*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5928*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5929*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5930*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5931*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5932*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5933*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5934*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5935*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5936*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5937*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5938*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5939*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5940*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5941*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5942*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5943*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5944*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5945*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5946*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5947*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5948*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5949*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5950*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5951*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5952*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5953*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5954*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5955*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5956*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5957*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5958*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5959*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5960*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5961*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5962*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5963*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5964*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5965*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5966*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5967*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5968*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5969*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=5970*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=5971*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=5972*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=5973*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=5974*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=5975*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5976*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5977*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5978*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5979*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5980*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5981*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5982*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5983*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5984*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5985*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5986*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5987*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5988*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5989*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5990*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5991*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5992*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5993*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5994*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5995*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5996*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5997*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=5998*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=5999*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u64 + BCAST imm_const [0x19] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6000*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B_BCAST_const0x19, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u64 + BCAST imm_const [0x17] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6001*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B_BCAST_const0x17, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u64 + BCAST imm_const [0x18] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6002*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B_BCAST_const0x18, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u32 + BCAST imm_const [0xf] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6003*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B_BCAST_const0xf, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u32 + BCAST imm_const [0x1b] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6004*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B_BCAST_const0x1b, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw u32 + BCAST imm_const [0xe] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6005*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B_BCAST_const0xe, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6006*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6007*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6008*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6009*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6010*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6011*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6012*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6013*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6014*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6015*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6016*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6017*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6018*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6019*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6020*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6021*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6022*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6023*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6024*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6025*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6026*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6027*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6028*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6029*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6030*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6031*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6032*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6033*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6034*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6035*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6036*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6037*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6038*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6039*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6040*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6041*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6042*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6043*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6044*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6045*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6046*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6047*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6048*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6049*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6050*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6051*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6052*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6053*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + BCAST imm_const [0x15] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6054*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x15, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f32 + BCAST imm_const [0x15] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6055*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x15, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + BCAST imm_const [0x7] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6056*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x7, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q f32 + BCAST imm_const [0x7] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6057*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x7, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq f32 + BCAST imm_const [0x9] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6058*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x9, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f64 + BCAST imm_const [0x14] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6059*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x14, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq f64 + BCAST imm_const [0x8] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6060*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x8, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + BCAST imm_const [0xc] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6061*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xc, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q u32 + BCAST imm_const [0xc] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6062*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xc, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + BCAST imm_const [0x15] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6063*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x15, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q u32 + BCAST imm_const [0x15] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6064*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x15, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + BCAST imm_const [0x7] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6065*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x7, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q u32 + BCAST imm_const [0x7] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6066*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x7, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u32 + BCAST imm_const [0x9] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6067*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x9, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u64 + BCAST imm_const [0x14] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6068*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x14, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u64 + BCAST imm_const [0x8] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6069*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x8, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6070*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6071*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6072*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6073*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6074*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6075*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6076*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6077*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6078*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6079*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6080*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6081*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6082*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6083*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6084*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6085*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6086*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6087*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6088*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6089*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6090*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6091*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6092*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6093*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6094*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6095*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6096*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6097*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6098*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6099*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6100*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6101*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6102*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6103*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6104*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6105*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6106*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6107*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6108*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6109*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6110*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6111*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6112*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6113*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6114*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6115*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6116*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6117*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6118*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6119*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6120*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6121*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6122*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6123*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6124*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6125*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6126*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6127*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6128*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6129*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6130*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6131*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6132*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6133*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6134*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6135*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6136*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6137*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6138*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6139*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6140*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6141*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6142*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6143*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6144*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6145*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6146*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6147*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6148*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6149*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6150*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6151*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6152*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6153*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6154*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6155*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6156*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6157*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6158*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6159*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6160*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT qq f32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6161*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6162*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6163*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6164*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq f64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6165*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6166*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT qq u32 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6167*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6168*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6169*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6170*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u64 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6171*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6172*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6173*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6174*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6175*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6176*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6177*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6178*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6179*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6180*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6181*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6182*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6183*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6184*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6185*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6186*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6187*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6188*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6189*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6190*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6191*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6192*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6193*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6194*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6195*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6196*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6197*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6198*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6199*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6200*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6201*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6202*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6203*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6204*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6205*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6206*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6207*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6208*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6209*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6210*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6211*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6212*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6213*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6214*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6215*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6216*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6217*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6218*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6219*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6220*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6221*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6222*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu8 u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6223*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6224*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6225*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6226*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6227*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6228*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6229*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6230*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6231*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6232*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6233*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6234*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6235*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6236*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6237*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6238*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6239*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi8 i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6240*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6241*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6242*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6243*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6244*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6245*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6246*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6247*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6248*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6249*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6250*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6251*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6252*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi32 i32 + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6253*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6254*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6255*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6256*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6257*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6258*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6259*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6260*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6261*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6262*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6263*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6264*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6265*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6266*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6267*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6268*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6269*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6270*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6271*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6272*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6273*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6274*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6275*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6276*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6277*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6278*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6279*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6280*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6281*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi8 i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6282*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + MEM0 imm_const [1] r EXPLICIT zd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6283*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6284*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6285*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6286*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6287*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6288*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6289*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6290*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6291*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6292*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6293*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6294*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6295*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6296*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6297*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6298*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6299*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6300*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6301*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6302*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6303*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6304*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6305*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6306*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6307*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6308*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6309*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6310*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6311*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6312*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6313*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6314*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6315*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6316*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6317*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6318*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6319*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6320*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6321*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6322*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6323*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6324*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6325*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6326*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6327*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6328*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6329*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6330*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6331*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6332*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6333*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6334*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6335*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6336*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6337*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + BCAST imm_const [0x11] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6338*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x11, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x11] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6339*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x11, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u8 + BCAST imm_const [0x11] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6340*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x11, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + BCAST imm_const [0x12] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6341*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x12, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x12] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6342*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x12, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u8 + BCAST imm_const [0x12] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6343*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x12, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + BCAST imm_const [0x13] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6344*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x13, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT b u8 + BCAST imm_const [0x13] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6345*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x13, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u8 + BCAST imm_const [0x13] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6346*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x13, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + BCAST imm_const [0xe] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6347*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xe, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT wrd u16 + BCAST imm_const [0xe] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6348*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xe, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u16 + BCAST imm_const [0xe] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6349*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xe, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + BCAST imm_const [0xf] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6350*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xf, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT wrd u16 + BCAST imm_const [0xf] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6351*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xf, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u16 + BCAST imm_const [0xf] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6352*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xf, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + BCAST imm_const [0x10] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6353*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x10, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT wrd u16 + BCAST imm_const [0x10] r SUPPRESSED INVALID + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6354*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x10, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u16 + BCAST imm_const [0x10] r SUPPRESSED INVALID + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6355*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x10, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6356*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6357*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6358*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6359*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi8 i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6360*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + MEM0 imm_const [1] r EXPLICIT zd i8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6361*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6362*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6363*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6364*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6365*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6366*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6367*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6368*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6369*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6370*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6371*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6372*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6373*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6374*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6375*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6376*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6377*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6378*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6379*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6380*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6381*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6382*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6383*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6384*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6385*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6386*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6387*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6388*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6389*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6390*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6391*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6392*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6393*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6394*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6395*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6396*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6397*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6398*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6399*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6400*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6401*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6402*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6403*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6404*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6405*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6406*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6407*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6408*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6409*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6410*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6411*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6412*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6413*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6414*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6415*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6416*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6417*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6418*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6419*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6420*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6421*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u8 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6422*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT b u8 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6423*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6424*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6425*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6426*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT d u32 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6427*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_B q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6428*/ xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT q u64 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6429*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d u16 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6430*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1, +/* MEM0 imm_const [1] w EXPLICIT wrd u16 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6431*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6432*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u16 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6433*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6434*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT b u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6435*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6436*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6437*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6438*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT d u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6439*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6440*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT q u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6441*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6442*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT wrd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6443*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6444*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6445*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6446*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6447*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6448*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6449*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6450*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6451*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6452*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6453*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6454*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6455*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6456*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6457*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6458*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6459*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi8 i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6460*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + MEM0 imm_const [1] r EXPLICIT zd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6461*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6462*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6463*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6464*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6465*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6466*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6467*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6468*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6469*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6470*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6471*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6472*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6473*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6474*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6475*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6476*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6477*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6478*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6479*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6480*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6481*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6482*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6483*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi8 i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6484*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + MEM0 imm_const [1] r EXPLICIT zd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6485*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6486*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6487*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6488*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6489*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6490*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6491*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6492*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6493*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6494*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6495*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6496*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6497*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6498*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6499*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6500*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6501*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6502*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6503*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6504*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6505*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6506*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6507*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6508*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6509*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6510*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6511*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6512*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6513*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6514*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6515*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6516*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6517*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6518*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6519*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6520*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK_B mskw i1 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6521*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6522*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6523*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6524*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6525*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6526*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6527*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6528*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6529*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq i8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zi16 i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6530*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6531*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6532*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6533*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6534*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6535*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6536*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6537*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6538*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6539*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6540*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6541*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6542*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6543*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6544*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6545*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6546*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT q u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6547*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6548*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6549*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6550*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6551*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6552*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT q i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6553*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6554*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6555*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6556*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6557*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6558*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6559*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6560*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6561*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6562*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6563*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6564*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6565*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6566*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6567*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6568*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6569*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6570*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6571*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6572*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6573*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6574*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6575*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6576*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6577*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6578*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6579*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6580*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6581*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6582*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6583*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6584*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6585*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6586*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6587*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6588*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6589*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6590*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6591*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6592*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6593*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6594*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6595*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6596*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6597*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6598*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6599*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6600*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6601*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6602*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6603*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6604*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6605*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6606*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6607*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6608*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6609*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6610*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6611*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6612*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6613*/ xed3_capture_chain_ntluf_REG0_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6614*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6615*/ xed3_capture_chain_ntluf_REG0_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6616*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 111 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6617*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6618*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6619*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6620*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6621*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6622*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6623*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6624*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6625*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6626*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6627*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6628*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6629*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6630*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6631*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6632*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6633*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6634*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 110 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6635*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6636*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6637*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6638*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6639*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6640*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6641*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6642*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6643*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6644*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6645*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6646*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6647*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6648*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6649*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6650*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6651*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6652*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 100 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6653*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u8 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6654*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6655*/ xed3_capture_chain_ntluf_REG0_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u8 + REG1 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6656*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6657*/ xed3_capture_chain_ntluf_REG0_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6658*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 011 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6659*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6660*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6661*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6662*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6663*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6664*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6665*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6666*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6667*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6668*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_N3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6669*/ xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6670*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6671*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6672*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_N3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6673*/ xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6674*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6675*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6676*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_N3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm 010 (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6677*/ xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6678*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6679*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6680*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6681*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6682*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6683*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6684*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i8 + MEM0 imm_const [1] r EXPLICIT dq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6685*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6686*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i8 + MEM0 imm_const [1] r EXPLICIT qq i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6687*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi8 i8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6688*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi8 i8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi8 i8 + MEM0 imm_const [1] r EXPLICIT zd i8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6689*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6690*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq i16 + MEM0 imm_const [1] r EXPLICIT dq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6691*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6692*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq i16 + MEM0 imm_const [1] r EXPLICIT qq i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6693*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6694*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zi16 i16 + MEM0 imm_const [1] r EXPLICIT zd i16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6695*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6696*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6697*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6698*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6699*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6700*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6701*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6702*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6703*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6704*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6705*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6706*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6707*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6708*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6709*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6710*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6711*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6712*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6713*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6714*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6715*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6716*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6717*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6718*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6719*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6720*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6721*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6722*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6723*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6724*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6725*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6726*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6727*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6728*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6729*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6730*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6731*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6732*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6733*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6734*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6735*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6736*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6737*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6738*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6739*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6740*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6741*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6742*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6743*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6744*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6745*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6746*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6747*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6748*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6749*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6750*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6751*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6752*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6753*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6754*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6755*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6756*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6757*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6758*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6759*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6760*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6761*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6762*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6763*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6764*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6765*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6766*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6767*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf64 f64 + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6768*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6769*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6770*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6771*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6772*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6773*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6774*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf32 f32 + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6775*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6776*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6777*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6778*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6779*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6780*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6781*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6782*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6783*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6784*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6785*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6786*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6787*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6788*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6789*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6790*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6791*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6792*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6793*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6794*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6795*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6796*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6797*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6798*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6799*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6800*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT d f32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6801*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6802*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6803*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6804*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6805*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6806*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6807*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6808*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6809*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6810*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6811*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6812*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6813*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6814*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6815*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6816*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6817*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6818*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6819*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6820*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6821*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6822*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6823*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6824*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6825*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6826*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6827*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6828*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6829*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6830*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6831*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6832*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6833*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6834*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6835*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6836*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6837*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6838*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6839*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6840*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6841*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6842*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6843*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6844*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6845*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6846*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6847*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6848*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6849*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6850*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6851*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6852*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6853*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6854*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6855*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6856*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6857*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6858*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6859*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6860*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6861*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6862*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6863*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6864*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6865*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6866*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6867*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT dq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6868*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6869*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6870*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6871*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u8 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu8 u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6872*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6873*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* MEM0 imm_const [1] w EXPLICIT dq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6874*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_R3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6875*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT qq u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6876*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_B3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_R3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6877*/ xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3, +/* MEM0 imm_const [1] w EXPLICIT zd u16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6878*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_B3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_R3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6879*/ xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6880*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6881*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6882*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6883*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6884*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6885*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6886*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6887*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6888*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6889*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6890*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6891*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6892*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6893*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6894*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6895*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6896*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6897*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6898*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6899*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6900*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6901*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6902*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6903*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6904*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6905*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6906*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6907*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6908*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6909*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6910*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6911*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6912*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6913*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6914*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6915*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6916*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6917*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6918*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6919*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6920*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6921*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6922*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6923*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6924*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6925*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6926*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6927*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6928*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6929*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6930*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6931*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6932*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6933*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6934*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6935*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6936*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6937*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6938*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6939*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6940*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6941*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6942*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6943*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6944*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6945*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6946*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6947*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6948*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6949*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6950*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6951*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6952*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6953*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6954*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6955*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6956*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6957*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6958*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u16 + MEM0 imm_const [1] r EXPLICIT dq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6959*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6960*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u16 + MEM0 imm_const [1] r EXPLICIT qq u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6961*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6962*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu16 u16 + MEM0 imm_const [1] r EXPLICIT zd u16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6963*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6964*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6965*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6966*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6967*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6968*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6969*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6970*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6971*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6972*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6973*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6974*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6975*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6976*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq u8 + MEM0 imm_const [1] r EXPLICIT dq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6977*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6978*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq u8 + MEM0 imm_const [1] r EXPLICIT qq u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6979*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zu8 u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6980*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu8 u8 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zu8 u8 + MEM0 imm_const [1] r EXPLICIT zd u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6981*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6982*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6983*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6984*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6985*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu128 u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6986*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + MEM0 imm_const [1] r EXPLICIT zd u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6987*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6988*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6989*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6990*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6991*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu128 u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6992*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + MEM0 imm_const [1] r EXPLICIT zd u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6993*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6994*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6995*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6996*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6997*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu128 u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=6998*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + MEM0 imm_const [1] r EXPLICIT zd u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=6999*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7000*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u128 + MEM0 imm_const [1] r EXPLICIT dq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7001*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7002*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u128 + MEM0 imm_const [1] r EXPLICIT qq u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7003*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu128 u128 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7004*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu128 u128 + MEM0 imm_const [1] r EXPLICIT zd u128 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7005*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7006*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u128 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT dq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7007*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7008*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u128 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT qq u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7009*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7010*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu128 u128 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT zd u64 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7011*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7012*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7013*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7014*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7015*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7016*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu32 u32 + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7017*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7018*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7019*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7020*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT YMM_N3 qq u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7021*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7022*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 MULTIREG2 + REG1 nt_lookup_fn r EXPLICIT ZMM_N3 zu64 u64 + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7023*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7024*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7025*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7026*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7027*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7028*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7029*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7030*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7031*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7032*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7033*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7034*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7035*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7036*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7037*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7038*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7039*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7040*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7041*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7042*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7043*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=7044*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=7045*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=7046*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7047*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7048*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7049*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7050*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7051*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi32 i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7052*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7053*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7054*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7055*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7056*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7057*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7058*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf64 f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7059*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7060*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7061*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7062*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7063*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7064*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7065*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7066*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7067*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7068*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7069*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7070*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7071*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7072*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7073*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf64 f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7074*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7075*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7076*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7077*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7078*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7079*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7080*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf32 f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7081*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7082*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7083*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7084*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7085*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7086*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7087*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7088*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7089*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7090*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7091*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7092*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7093*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7094*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7095*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7096*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7097*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7098*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7099*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7100*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7101*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7102*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7103*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7104*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7105*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7106*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7107*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7108*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7109*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7110*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7111*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7112*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7113*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7114*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7115*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7116*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7117*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7118*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7119*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7120*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7121*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf32 f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7122*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7123*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7124*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7125*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7126*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7127*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7128*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7129*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7130*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7131*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7132*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT q f64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7133*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7134*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7135*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f64 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7136*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7137*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7138*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7139*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7140*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7141*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7142*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7143*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7144*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7145*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7146*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7147*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7148*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7149*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7150*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7151*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7152*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7153*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7154*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7155*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7156*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7157*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7158*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7159*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7160*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7161*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d i32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7162*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT d i32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7163*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7164*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q i64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7165*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT q i64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7166*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7167*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7168*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT d f32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7169*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7170*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7171*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7172*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7173*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7174*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7175*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi32 i32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7176*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7177*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7178*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7179*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7180*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7181*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7182*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi64 i64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7183*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7184*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7185*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7186*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7187*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7188*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7189*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu32 u32 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7190*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7191*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7192*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7193*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7194*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7195*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7196*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu64 u64 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7197*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7198*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7199*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7200*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7201*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7202*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7203*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zu16 u16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7204*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7205*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7206*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7207*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7208*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7209*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7210*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zi16 i16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7211*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7212*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7213*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7214*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7215*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7216*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d i32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7217*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7218*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7219*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q i64 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7220*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7221*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7222*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7223*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7224*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7225*/ xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_R d u32 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7226*/ xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7227*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7228*/ xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT GPR64_R q u64 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7229*/ xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7230*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7231*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7232*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7233*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7234*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu32 u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7235*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u32 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7236*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7237*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7238*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7239*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7240*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7241*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu64 u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7242*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u64 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7243*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7244*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7245*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7246*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7247*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR32_B d u32 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7248*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT d u32 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7249*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7250*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG2 nt_lookup_fn r EXPLICIT GPR64_B q u64 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7251*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT q u64 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7252*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7253*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7254*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7255*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7256*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7257*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zu16 u16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7258*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv u16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7259*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7260*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7261*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7262*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7263*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7264*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zi16 i16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7265*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv i16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7266*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7267*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7268*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7269*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7270*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7271*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7272*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7273*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7274*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7275*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7276*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7277*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7278*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7279*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7280*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7281*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 z2f16 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7282*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7283*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7284*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7285*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT d 2f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7286*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7287*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7288*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7289*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7290*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7291*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 z2f16 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7292*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7293*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7294*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7295*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT d 2f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7296*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7297*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7298*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7299*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7300*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7301*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7302*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7303*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7304*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7305*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7306*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7307*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7308*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7309*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7310*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7311*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7312*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7313*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7314*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7315*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7316*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7317*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7318*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7319*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7320*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7321*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7322*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7323*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7324*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7325*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7326*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7327*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7328*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7329*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7330*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7331*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 z2f16 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7332*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7333*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7334*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7335*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT d 2f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7336*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7337*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7338*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7339*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7340*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7341*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7342*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7343*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7344*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7345*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7346*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7347*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7348*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7349*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7350*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7351*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7352*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7353*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7354*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7355*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7356*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7357*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7358*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7359*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7360*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7361*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7362*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7363*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7364*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7365*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7366*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7367*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7368*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7369*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7370*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7371*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7372*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7373*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7374*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7375*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7376*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7377*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7378*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7379*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7380*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7381*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7382*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7383*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7384*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7385*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7386*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7387*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7388*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7389*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7390*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7391*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7392*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7393*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7394*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7395*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7396*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7397*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7398*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7399*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7400*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7401*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7402*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7403*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7404*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7405*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7406*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7407*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7408*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7409*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7410*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7411*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7412*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7413*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 z2f16 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 z2f16 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7414*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 z2f16 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 z2f16 2f16 + MEM0 imm_const [1] r EXPLICIT vv 2f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7415*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7416*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq 2f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7417*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq 2f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq 2f16 + MEM0 imm_const [1] r EXPLICIT d 2f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7418*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7419*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7420*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7421*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7422*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7423*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7424*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7425*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7426*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7427*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7428*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7429*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7430*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7431*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7432*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7433*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7434*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7435*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7436*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7437*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7438*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7439*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7440*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7441*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7442*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7443*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7444*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7445*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7446*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7447*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7448*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7449*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7450*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7451*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7452*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7453*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7454*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7455*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7456*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7457*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7458*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7459*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7460*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7461*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7462*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7463*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7464*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7465*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7466*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7467*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7468*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7469*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7470*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7471*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7472*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7473*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7474*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7475*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7476*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7477*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn rw EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7478*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7479*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7480*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7481*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7482*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7483*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7484*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7485*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT MASK_R mskw i1 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + MEM0 imm_const [1] r EXPLICIT wrd f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7486*/ xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7487*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7488*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7489*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7490*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7491*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7492*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7493*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7494*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7495*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7496*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7497*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7498*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7499*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7500*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7501*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7502*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7503*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7504*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7505*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7506*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7507*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7508*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7509*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7510*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7511*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7512*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7513*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7514*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7515*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7516*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7517*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7518*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7519*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7520*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7521*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7522*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7523*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7524*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7525*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7526*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7527*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* MEM0 imm_const [1] w EXPLICIT wrd f16 + REG0 nt_lookup_fn r EXPLICIT MASK1 mskw i1 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7528*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7529*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_B3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7530*/ xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT GPR32_B d f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7531*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR32_B, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7532*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT GPR32_B d f16 + REG1 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7533*/ xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3, +/* MEM0 imm_const [1] w EXPLICIT wrd f16 + REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7534*/ xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7535*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7536*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7537*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7538*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7539*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7540*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7541*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7542*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7543*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7544*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7545*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7546*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7547*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7548*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7549*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7550*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7551*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7552*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7553*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7554*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7555*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7556*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7557*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7558*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7559*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7560*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7561*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7562*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7563*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7564*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7565*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7566*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7567*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7568*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7569*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7570*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7571*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + IMM0 imm_const [1] r EXPLICIT b u8 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7572*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7573*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7574*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7575*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7576*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7577*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7578*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7579*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7580*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7581*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7582*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7583*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7584*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7585*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7586*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7587*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7588*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7589*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7590*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7591*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7592*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7593*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7594*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7595*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7596*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7597*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7598*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7599*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7600*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7601*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7602*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + REG3 nt_lookup_fn r EXPLICIT YMM_B3 qq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7603*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT YMM_R3 qq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT YMM_N3 qq f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7604*/ xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7605*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + REG3 nt_lookup_fn r EXPLICIT ZMM_B3 zf16 f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7606*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT ZMM_R3 zf16 f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT ZMM_N3 zf16 f16 + MEM0 imm_const [1] r EXPLICIT vv f16 TXT=BCASTSTR + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7607*/ xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7608*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 TXT=ROUNDC + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + REG3 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 inum=7609*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3, +/* REG0 nt_lookup_fn w EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT MASK1 mskw i1 TXT=ZEROSTR + REG2 nt_lookup_fn r EXPLICIT XMM_N3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 inum=7610*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=7611*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 TXT=SAESTR + REG1 nt_lookup_fn r EXPLICIT XMM_B3 dq f16 + MOD imm 11 (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 15, 16, 17 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 18, 19, 20 + REG2 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=7612*/ xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS, +/* REG0 nt_lookup_fn r EXPLICIT XMM_R3 dq f16 + MEM0 imm_const [1] r EXPLICIT wrd f16 + MOD imm mm (L) r SUPPRESSED i2 bitpos: 11, 12 + REG imm rrr (L) r SUPPRESSED i3 bitpos: 14, 15, 16 + RM imm nnn (L) r SUPPRESSED i3 bitpos: 17, 18, 19 + REG1 nt_lookup_fn w SUPPRESSED rFLAGS INVALID inum=7613*/ xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS, +}; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-op-chain-capture.h b/CodeVirtualizer/build/obj/include-private/xed3-op-chain-capture.h new file mode 100644 index 0000000..54be57b --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-op-chain-capture.h @@ -0,0 +1,13592 @@ +/// @file include-private/xed3-op-chain-capture.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_OP_CHAIN_CAPTURE_H) +# define INCLUDE_PRIVATE_XED3_OP_CHAIN_CAPTURE_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-nt-capture.h" +static XED_INLINE xed_error_enum_t xed3_capture_nt_nop_ntluf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87PUSH_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP2_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_X87TAG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_X87TAG_REG2_XED_REG_X87POP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPOP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ES_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_SS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_FS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_GS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AL_REG2_XED_REG_AX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_REG1_OrDX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_OrAX_REG2_OrDX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_REG1_rIP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPUSH_REG2_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_RIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_rIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_PTR_const1_IMM0_const1_REG0_XED_REG_EIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ES_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_CS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_SS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_FS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_GS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_LDTR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_LDTR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_TR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_TR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_LDTR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_TR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_GDTR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CR0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CR0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_CR0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EBX_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_RDX_REG1_XED_REG_RAX_REG2_XED_REG_RCX_REG3_XED_REG_RBX_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_SEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_SEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_SEG_MOV_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_SEG_MOV_REG1_GPR16_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_SEG0_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OrAX_MEM0_const1_SEG0_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_SEG0_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_SEG0_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_SB_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_MXCSR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_IDTR(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_ECX_REG2_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_TSC_REG4_XED_REG_TSCAUX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_SP_REG6_XED_REG_BP_REG7_XED_REG_SI_REG8_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_ESP_REG6_XED_REG_EBP_REG7_XED_REG_ESI_REG8_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_BP_REG6_XED_REG_SI_REG7_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_EBP_REG6_XED_REG_ESI_REG7_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR16_R_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_GPR16_R_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRz_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_OrAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_AGEN_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_AL(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_EAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_AX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RDX_REG1_XED_REG_RAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_PTR_const1_IMM0_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AH_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRz_R_MEM0_const1_REG1_XED_REG_ES(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRz_R_MEM0_const1_REG1_XED_REG_DS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_IMM1_const1_REG0_XED_REG_STACKPUSH_REG1_OrBP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArBP_SEG0_FINAL_SSEG0_REG0_OrBP_REG1_OrSP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rIP_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_rIP_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_RIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArBX_INDEX_XED_REG_AL_REG0_XED_REG_AL_SEG0_FINAL_DSEG_SCALE_const0x1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_CX_REG1_XED_REG_IP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_ECX_REG1_XED_REG_EIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_ECX_REG1_XED_REG_RIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RCX_REG1_XED_REG_RIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OeAX_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_DX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OeAX_REG1_XED_REG_DX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_OeAX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AL_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_OeAX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rIP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRz_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RCX_REG2_XED_REG_R11_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ECX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_CR_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_CR_R_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_CR_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_CR_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_DR_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_DR_R_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_DR_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_DR_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_MSRS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_TSC(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ESP_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RSP_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ESP_REG2_XED_REG_ECX_REG3_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RSP_REG2_XED_REG_RCX_REG3_XED_REG_RDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX_REG2_XED_REG_ECX_REG3_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_XED_REG_AL_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_OrAX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_XED_REG_AL_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_OrAX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_SS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_FS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_GS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR8_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR16_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MMX_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MMX_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_MMX_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_MMX_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_MMX_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_B_REG1_MMX_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_GPR64_R_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_GPR32_R_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_GPR64_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_XED_REG_CL_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_XED_REG_CL_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_R_REG1_GPR8_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_R_REG1_GPRv_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XED_REG_XMM0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_XMM0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_ECX_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_ECX_REG5_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_RCX_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_RCX_REG5_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_ECX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_ECX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RCX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_XMM0_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_XMM0_REG5_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_XMM0_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_XMM0_REG5_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_XMM0_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_XMM0_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ECX_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_XED_REG_XCR0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrAX_BASE0_ArDI_SEG0_FINAL_ESEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_REG3_ArAX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ArAX_REG1_OrCX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ArAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ArAX_REG1_XED_REG_ECX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1_IMM1_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_IMM1_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_RCX_REG2_XED_REG_RDX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_RCX_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_AGEN_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_REG1_BND_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_B_REG1_BND_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_SSP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_SSP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_SSP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_SSP(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_FSBASE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_GSBASE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_TSCAUX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_TSCAUX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_MEM1_const1_BASE1_A_GPR_R_SEG1_XED_REG_ES(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_MEM1_const1_BASE1_A_GPR_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_rIP_REG1_XED_REG_EAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_XMM0_REG1_XED_REG_XMM1_REG2_XED_REG_XMM2_REG3_XED_REG_XMM3_REG4_XED_REG_XMM4_REG5_XED_REG_XMM5_REG6_XED_REG_XMM6_REG7_XED_REG_XMM7_REG8_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_XED_REG_XMM0_REG3_XED_REG_XMM1_REG4_XED_REG_XMM2_REG5_XED_REG_XMM4_REG6_XED_REG_XMM5_REG7_XED_REG_XMM6_REG8_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_XED_REG_XMM0_REG3_XED_REG_XMM1_REG4_XED_REG_XMM2_REG5_XED_REG_XMM3_REG6_XED_REG_XMM4_REG7_XED_REG_XMM5_REG8_XED_REG_XMM6_REG9_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_EAX_REG3_XED_REG_XMM0_REG4_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_EAX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_UIF(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_UIF_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rIP_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RCX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ECX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_R_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_R_REG1_VGPRy_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPR32_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPR32_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_YMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_YMM_R_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xa(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xa(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xd(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xd(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x14(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1_BCAST_const0x14(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B_IMM0_const1_BCAST_const0x14(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_N_REG1_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_N_REG1_YMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_N_REG2_XMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_YMM_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0x11(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0x11(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x12(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x12(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xe(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xe(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xb(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xb(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_N_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_N_REG1_VGPR64_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N_REG3_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_XED_REG_EDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B_REG3_XED_REG_RDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1_REG2_XED_REG_RDX(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_TMM_R_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_TMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_TMM_R(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x2(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x4(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x6(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x5(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x5(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xd(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xd(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xa(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xa(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR32_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR64_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xa(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0x5(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xb(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xb(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0xb(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0xd(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B_BCAST_const0x19(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B_BCAST_const0x17(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B_BCAST_const0x18(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B_BCAST_const0xf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B_BCAST_const0x1b(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B_BCAST_const0xe(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x15(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x15(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x7(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x7(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x9(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x14(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x8(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xc(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xc(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x11(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x11(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x11(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x12(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x12(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x12(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x13(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x13(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x13(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xe(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xe(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xe(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xf(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x10(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x10(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x10(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_XMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_REG2_XMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_REG2_YMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_REG2_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3(xed_decoded_inst_t* d); + +static XED_INLINE xed_error_enum_t xed3_capture_nt_nop_ntluf(xed_decoded_inst_t* d) +{ +(void)d; +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_capture_nt_X87(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_X87(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_ST0); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_X87POP); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_capture_nt_X87(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_X87POP); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_MEM0_const1_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_X87PUSH); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87PUSH_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_capture_nt_X87(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_X87PUSH); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_ST0_REG1_XED_REG_X87POP_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_X87POP); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_ST0_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_X87(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_ST0); +xed3_operand_set_reg2(d, XED_REG_X87POP); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_X87CONTROL); +xed3_operand_set_reg1(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_X87PUSH_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_X87PUSH); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_ST1); +xed3_operand_set_reg2(d, XED_REG_X87POP); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_ST1); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87STATUS_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_capture_nt_X87(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_XED_REG_ST1_REG2_XED_REG_X87POP2_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_operand_set_reg1(d, XED_REG_ST1); +xed3_operand_set_reg2(d, XED_REG_X87POP2); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG2_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_X87CONTROL); +xed3_operand_set_reg1(d, XED_REG_X87TAG); +xed3_operand_set_reg2(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_X87CONTROL); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_X87CONTROL_REG1_XED_REG_X87TAG_REG3_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_X87CONTROL); +xed3_operand_set_reg1(d, XED_REG_X87TAG); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_X87STATUS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_reg1(d, XED_REG_X87STATUS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_X87TAG(xed_decoded_inst_t* d) +{ +xed3_capture_nt_X87(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_X87TAG); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_X87_REG1_XED_REG_X87TAG_REG2_XED_REG_X87POP(xed_decoded_inst_t* d) +{ +xed3_capture_nt_X87(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_X87TAG); +xed3_operand_set_reg2(d, XED_REG_X87POP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ST0_REG1_X87_REG2_XED_REG_X87POP_REG3_XED_REG_X87STATUS_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ST0); +xed3_capture_nt_X87(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_X87POP); +xed3_operand_set_reg3(d, XED_REG_X87STATUS); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1_REG0_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OrAX_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OrAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPOP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ES_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ES); +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_SS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_SS); +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DS); +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_FS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_FS); +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_GS_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_GS); +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CL_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_CL); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_CL_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_CL); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CL_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_CL); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_reg1(d, XED_REG_AX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AL_REG2_XED_REG_AX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_AL); +xed3_operand_set_reg2(d, XED_REG_AX); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_REG1_OrDX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_OrAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrDX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_OrAX_REG2_OrDX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrAX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrDX(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_XED_REG_AX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_AX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_REG1_rIP_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPUSH_REG2_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_capture_nt_rIP(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_reg1(d, XED_REG_EIP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_RIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_reg1(d, XED_REG_RIP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_rIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rIP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_rIP(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_EIP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_RIP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_PTR_const1_IMM0_const1_REG0_XED_REG_EIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_ptr(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_EIP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_STACKPUSH_MEM1_const1_BASE1_SrSP_SEG1_FINAL_SSEG1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ES_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ES); +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_CS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_CS); +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_SS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_SS); +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DS); +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_FS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_FS); +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_GS_REG1_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_GS); +xed3_operand_set_reg1(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_LDTR(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_LDTR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_LDTR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_LDTR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_TR(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_TR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_TR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_TR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_LDTR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR16_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_LDTR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_TR(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR16_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_TR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR16_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_GDTR(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_GDTR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_CR0(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_CR0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_XED_REG_CR0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_CR0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_XED_REG_CR0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR16_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_CR0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EBX_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_EDX); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_EBX); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_RDX_REG1_XED_REG_RAX_REG2_XED_REG_RCX_REG3_XED_REG_RBX_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_RDX); +xed3_operand_set_reg1(d, XED_REG_RAX); +xed3_operand_set_reg2(d, XED_REG_RCX); +xed3_operand_set_reg3(d, XED_REG_RBX); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_R_REG1_GPR8_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRv_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_SEG(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SEG(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_SEG(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_SEG(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_SEG_MOV_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_SEG_MOV(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_SEG_MOV_REG1_GPR16_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_SEG_MOV(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR16_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_SEG0_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OrAX_MEM0_const1_SEG0_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OrAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_AL_SEG0_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrAX_SEG0_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_OrAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_SB_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_MXCSR(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_MXCSR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_rFLAGS(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_IDTR(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_IDTR); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_operand_set_reg2(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_ECX_REG2_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_operand_set_reg2(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_operand_set_reg2(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_ECX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_TSC_REG4_XED_REG_TSCAUX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_TSC); +xed3_operand_set_reg4(d, XED_REG_TSCAUX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_reg1(d, XED_REG_AH); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_SP_REG6_XED_REG_BP_REG7_XED_REG_SI_REG8_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_reg1(d, XED_REG_AX); +xed3_operand_set_reg2(d, XED_REG_CX); +xed3_operand_set_reg3(d, XED_REG_DX); +xed3_operand_set_reg4(d, XED_REG_BX); +xed3_operand_set_reg5(d, XED_REG_SP); +xed3_operand_set_reg6(d, XED_REG_BP); +xed3_operand_set_reg7(d, XED_REG_SI); +xed3_operand_set_reg8(d, XED_REG_DI); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_ESP_REG6_XED_REG_EBP_REG7_XED_REG_ESI_REG8_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_EDX); +xed3_operand_set_reg4(d, XED_REG_EBX); +xed3_operand_set_reg5(d, XED_REG_ESP); +xed3_operand_set_reg6(d, XED_REG_EBP); +xed3_operand_set_reg7(d, XED_REG_ESI); +xed3_operand_set_reg8(d, XED_REG_EDI); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_AX_REG2_XED_REG_CX_REG3_XED_REG_DX_REG4_XED_REG_BX_REG5_XED_REG_BP_REG6_XED_REG_SI_REG7_XED_REG_DI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_operand_set_reg1(d, XED_REG_AX); +xed3_operand_set_reg2(d, XED_REG_CX); +xed3_operand_set_reg3(d, XED_REG_DX); +xed3_operand_set_reg4(d, XED_REG_BX); +xed3_operand_set_reg5(d, XED_REG_BP); +xed3_operand_set_reg6(d, XED_REG_SI); +xed3_operand_set_reg7(d, XED_REG_DI); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_EAX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_XED_REG_EBX_REG5_XED_REG_EBP_REG6_XED_REG_ESI_REG7_XED_REG_EDI_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_EDX); +xed3_operand_set_reg4(d, XED_REG_EBX); +xed3_operand_set_reg5(d, XED_REG_EBP); +xed3_operand_set_reg6(d, XED_REG_ESI); +xed3_operand_set_reg7(d, XED_REG_EDI); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR16_R_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR16_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR16_B_REG1_GPR16_R_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR16_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR16_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRz_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRz_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_DX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RIP_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_RIP); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_EIP_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_EIP); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB_REG1_OrAX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrAX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_AGEN_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_agen(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_REG1_XED_REG_AL(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_reg1(d, XED_REG_AL); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_EAX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_reg1(d, XED_REG_EAX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_AX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_AX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_operand_set_reg1(d, XED_REG_AX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RDX_REG1_XED_REG_RAX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RDX); +xed3_operand_set_reg1(d, XED_REG_RAX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EDX); +xed3_operand_set_reg1(d, XED_REG_EAX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_PTR_const1_IMM0_const1_REG0_XED_REG_STACKPUSH_REG1_XED_REG_EIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_ptr(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_reg1(d, XED_REG_EIP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPUSH_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AH_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AH); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_ArCX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1_REG0_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_ArCX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1_REG0_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AL_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_AX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_EAX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG0_XED_REG_RAX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_DSEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_ArCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_MEM0_const1_BASE0_ArDI_SEG0_FINAL_ESEG_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRz_R_MEM0_const1_REG1_XED_REG_ES(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRz_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_ES); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRz_R_MEM0_const1_REG1_XED_REG_DS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRz_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_DS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_IMM1_const1_REG0_XED_REG_STACKPUSH_REG1_OrBP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_operand_set_imm1(d, 1); +xed3_operand_set_reg0(d, XED_REG_STACKPUSH); +xed3_capture_nt_OrBP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArBP_SEG0_FINAL_SSEG0_REG0_OrBP_REG1_OrSP(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArBP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrBP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrSP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rIP_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_rIP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_rIP_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rIP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EIP); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_rIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_STACKPOP_REG1_XED_REG_RIP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_STACKPOP); +xed3_operand_set_reg1(d, XED_REG_RIP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_XED_REG_AH_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_reg1(d, XED_REG_AH); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_BASE0_ArBX_INDEX_XED_REG_AL_REG0_XED_REG_AL_SEG0_FINAL_DSEG_SCALE_const0x1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArBX(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_index(d, XED_REG_AL); +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_scale(d, 0x1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_capture_nt_ArCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_ArCX_REG1_rIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_capture_nt_ArCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rIP(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_CX_REG1_XED_REG_IP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_CX); +xed3_operand_set_reg1(d, XED_REG_IP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_ECX_REG1_XED_REG_EIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_ECX); +xed3_operand_set_reg1(d, XED_REG_EIP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_ECX_REG1_XED_REG_RIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_ECX); +xed3_operand_set_reg1(d, XED_REG_RIP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_XED_REG_RCX_REG1_XED_REG_RIP(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_operand_set_reg0(d, XED_REG_RCX); +xed3_operand_set_reg1(d, XED_REG_RIP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OeAX_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OeAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_AL_REG1_XED_REG_DX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_operand_set_reg1(d, XED_REG_DX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_OeAX_REG1_XED_REG_DX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_OeAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_DX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_AL_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_AL); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_OeAX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_OeAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_XED_REG_AL_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_operand_set_reg1(d, XED_REG_AL); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_DX_REG1_OeAX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_DX); +xed3_capture_nt_OeAX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rIP(xed_decoded_inst_t* d) +{ +xed3_capture_nt_rIP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPRz_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRz_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RCX_REG2_XED_REG_R11_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RIP); +xed3_operand_set_reg1(d, XED_REG_RCX); +xed3_operand_set_reg2(d, XED_REG_R11); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ECX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EIP); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_CR_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_CR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_CR_R_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_CR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_CR_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_CR_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_CR_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_CR_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_DR_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_DR_R_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_DR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_DR_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_DR_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_DR_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_DR_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX_REG3_XED_REG_MSRS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_MSRS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_TSC(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_TSC); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ESP_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EIP); +xed3_operand_set_reg1(d, XED_REG_ESP); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RSP_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RIP); +xed3_operand_set_reg1(d, XED_REG_RSP); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EIP_REG1_XED_REG_ESP_REG2_XED_REG_ECX_REG3_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EIP); +xed3_operand_set_reg1(d, XED_REG_ESP); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RIP_REG1_XED_REG_RSP_REG2_XED_REG_RCX_REG3_XED_REG_RDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RIP); +xed3_operand_set_reg1(d, XED_REG_RSP); +xed3_operand_set_reg2(d, XED_REG_RCX); +xed3_operand_set_reg3(d, XED_REG_RDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX_REG2_XED_REG_ECX_REG3_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EBX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR8_R_REG1_XED_REG_AL_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR8_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_AL); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_OrAX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrAX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR8_B_REG1_GPR8_R_REG2_XED_REG_AL_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR8_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_AL); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_OrAX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrAX(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_SS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_SS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_FS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_FS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_MEM0_const1_REG1_XED_REG_GS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_GS); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR8_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_R_REG1_GPR16_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR16_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MMX_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MMX_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_MMX_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MMX_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_MMX_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_MEM0_const1_BASE0_ArDI_SEG0_FINAL_DSEG(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_MMX_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_R_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_MMX_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MMX_B_REG1_MMX_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MMX_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MMX_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR64_R_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_GPR64_R_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPR32_R_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_GPR32_R_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_GPR64_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_GPRv_R_REG1_XED_REG_CL_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_GPRv_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_CL); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_B_REG1_GPRv_R_REG2_XED_REG_CL_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_CL); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRv_SB(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRv_SB(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRy_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_R_REG1_GPR8_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRy_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR8_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_R_REG1_GPRv_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRy_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPRv_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XED_REG_XMM0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg1(d, XED_REG_XMM0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_XMM0(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_XMM0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_GPR64_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_ECX_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_EDX); +xed3_operand_set_reg3(d, XED_REG_ECX); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_ECX_REG5_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_EAX); +xed3_operand_set_reg3(d, XED_REG_EDX); +xed3_operand_set_reg4(d, XED_REG_ECX); +xed3_capture_nt_rFLAGS(d); +/*opname REG5 */ +xed3_operand_set_reg5(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_RCX_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_RAX); +xed3_operand_set_reg2(d, XED_REG_RDX); +xed3_operand_set_reg3(d, XED_REG_RCX); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_RCX_REG5_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_RAX); +xed3_operand_set_reg3(d, XED_REG_RDX); +xed3_operand_set_reg4(d, XED_REG_RCX); +xed3_capture_nt_rFLAGS(d); +/*opname REG5 */ +xed3_operand_set_reg5(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_ECX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_ECX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_RCX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RCX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_RCX); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_EAX_REG2_XED_REG_EDX_REG3_XED_REG_XMM0_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_EDX); +xed3_operand_set_reg3(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_EAX_REG3_XED_REG_EDX_REG4_XED_REG_XMM0_REG5_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_EAX); +xed3_operand_set_reg3(d, XED_REG_EDX); +xed3_operand_set_reg4(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG5 */ +xed3_operand_set_reg5(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_RAX_REG2_XED_REG_RDX_REG3_XED_REG_XMM0_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_RAX); +xed3_operand_set_reg2(d, XED_REG_RDX); +xed3_operand_set_reg3(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_RAX_REG3_XED_REG_RDX_REG4_XED_REG_XMM0_REG5_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_RAX); +xed3_operand_set_reg3(d, XED_REG_RDX); +xed3_operand_set_reg4(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG5 */ +xed3_operand_set_reg5(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_IMM0_const1_REG1_XED_REG_XMM0_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg1(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_REG2_XED_REG_XMM0_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg2(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ECX_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_XED_REG_XCR0(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ECX); +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_EAX); +xed3_operand_set_reg3(d, XED_REG_XCR0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_XCR0(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_EDX); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_XCR0); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EBX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrAX_BASE0_ArDI_SEG0_FINAL_ESEG(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_OrCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrDX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrAX(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_OrCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrDX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrBX(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_OrCX_REG1_OrDX_REG2_OrBX_REG3_ArAX_BASE0_ArDI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArSI_SEG1_FINAL_DSEG1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_OrCX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrDX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrBX(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArAX(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ArDI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_DSEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ArAX_REG1_OrCX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG_MEM1_const1_BASE1_ArDI_SEG1_FINAL_ESEG1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ArAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_OrCX(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_ArDI(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG1(d); +/*opname SEG1 */ +xed3_operand_set_seg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_MEM0_const1_BASE0_ArSI_SEG0_FINAL_ESEG(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_operand_set_reg2(d, XED_REG_EDX); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ArSI(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_ESEG(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ArAX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ArAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ArAX_REG1_XED_REG_ECX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ArAX(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_ECX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_IMM0_const1_IMM1_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_imm1(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_IMM0_const1_IMM1_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_imm1(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EDX_REG1_XED_REG_EAX_REG2_XED_REG_ECX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EDX); +xed3_operand_set_reg1(d, XED_REG_EAX); +xed3_operand_set_reg2(d, XED_REG_ECX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_ECX_REG2_XED_REG_EDX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_reg1(d, XED_REG_ECX); +xed3_operand_set_reg2(d, XED_REG_EDX); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_RCX_REG2_XED_REG_RDX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_reg1(d, XED_REG_RCX); +xed3_operand_set_reg2(d, XED_REG_RDX); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_RCX_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_reg1(d, XED_REG_RCX); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_ECX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RAX_REG1_XED_REG_EDX_REG2_XED_REG_ECX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RAX); +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_ECX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_AGEN_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BND_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_agen(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BND_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BND_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_REG1_BND_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BND_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BND_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BND_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_BND_B_REG1_BND_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_BND_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_BND_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_BND_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_BND_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_SSP(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_SSP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_SSP(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_SSP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_SSP(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_SSP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_SSP(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_SSP); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_FSBASE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRy_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_FSBASE); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_B_REG1_XED_REG_GSBASE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRy_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_GSBASE); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_RBX); +xed3_operand_set_reg2(d, XED_REG_RCX); +xed3_operand_set_reg3(d, XED_REG_RDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_TSCAUX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_TSCAUX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XED_REG_TSCAUX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_TSCAUX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPRy_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPRy_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_MEM1_const1_BASE1_A_GPR_R_SEG1_XED_REG_ES(xed_decoded_inst_t* d) +{ +xed3_capture_nt_A_GPR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_A_GPR_R(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_seg1(d, XED_REG_ES); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_MEM1_const1_BASE1_A_GPR_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_A_GPR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_mem1(d, 1); +xed3_capture_nt_A_GPR_R(d); +/*opname BASE1 */ +xed3_operand_set_base1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XED_REG_EDX_REG2_XED_REG_EAX_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_EDX); +xed3_operand_set_reg2(d, XED_REG_EAX); +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_A_GPR_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_RELBR_const1_REG0_rIP_REG1_XED_REG_EAX(xed_decoded_inst_t* d) +{ +xed3_operand_set_relbr(d, 1); +xed3_capture_nt_rIP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_EAX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_EBX_REG2_XED_REG_ECX_REG3_XED_REG_EDX_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_EBX); +xed3_operand_set_reg2(d, XED_REG_ECX); +xed3_operand_set_reg3(d, XED_REG_EDX); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_EAX_REG1_XED_REG_RBX_REG2_XED_REG_RCX_REG3_XED_REG_RDX_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_EAX); +xed3_operand_set_reg1(d, XED_REG_RBX); +xed3_operand_set_reg2(d, XED_REG_RCX); +xed3_operand_set_reg3(d, XED_REG_RDX); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XED_REG_XMM0_REG1_XED_REG_XMM1_REG2_XED_REG_XMM2_REG3_XED_REG_XMM3_REG4_XED_REG_XMM4_REG5_XED_REG_XMM5_REG6_XED_REG_XMM6_REG7_XED_REG_XMM7_REG8_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg0(d, XED_REG_XMM0); +xed3_operand_set_reg1(d, XED_REG_XMM1); +xed3_operand_set_reg2(d, XED_REG_XMM2); +xed3_operand_set_reg3(d, XED_REG_XMM3); +xed3_operand_set_reg4(d, XED_REG_XMM4); +xed3_operand_set_reg5(d, XED_REG_XMM5); +xed3_operand_set_reg6(d, XED_REG_XMM6); +xed3_operand_set_reg7(d, XED_REG_XMM7); +xed3_capture_nt_rFLAGS(d); +/*opname REG8 */ +xed3_operand_set_reg8(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_XED_REG_XMM0_REG3_XED_REG_XMM1_REG4_XED_REG_XMM2_REG5_XED_REG_XMM4_REG6_XED_REG_XMM5_REG7_XED_REG_XMM6_REG8_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_XMM0); +xed3_operand_set_reg3(d, XED_REG_XMM1); +xed3_operand_set_reg4(d, XED_REG_XMM2); +xed3_operand_set_reg5(d, XED_REG_XMM4); +xed3_operand_set_reg6(d, XED_REG_XMM5); +xed3_operand_set_reg7(d, XED_REG_XMM6); +xed3_capture_nt_rFLAGS(d); +/*opname REG8 */ +xed3_operand_set_reg8(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_GPR32_B_REG2_XED_REG_XMM0_REG3_XED_REG_XMM1_REG4_XED_REG_XMM2_REG5_XED_REG_XMM3_REG6_XED_REG_XMM4_REG7_XED_REG_XMM5_REG8_XED_REG_XMM6_REG9_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_XMM0); +xed3_operand_set_reg3(d, XED_REG_XMM1); +xed3_operand_set_reg4(d, XED_REG_XMM2); +xed3_operand_set_reg5(d, XED_REG_XMM3); +xed3_operand_set_reg6(d, XED_REG_XMM4); +xed3_operand_set_reg7(d, XED_REG_XMM5); +xed3_operand_set_reg8(d, XED_REG_XMM6); +xed3_capture_nt_rFLAGS(d); +/*opname REG9 */ +xed3_operand_set_reg9(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XED_REG_EAX_REG3_XED_REG_XMM0_REG4_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg2(d, XED_REG_EAX); +xed3_operand_set_reg3(d, XED_REG_XMM0); +xed3_capture_nt_rFLAGS(d); +/*opname REG4 */ +xed3_operand_set_reg4(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_IMM0_const1_REG0_XED_REG_EAX(xed_decoded_inst_t* d) +{ +xed3_operand_set_imm0(d, 1); +xed3_operand_set_reg0(d, XED_REG_EAX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_UIF(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_UIF); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_UIF_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_UIF); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_rIP_REG1_XED_REG_STACKPOP_MEM0_const1_BASE0_SrSP_SEG0_FINAL_SSEG0_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_rIP(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg1(d, XED_REG_STACKPOP); +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_SrSP(d); +/*opname BASE0 */ +xed3_operand_set_base0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_FINAL_SSEG0(d); +/*opname SEG0 */ +xed3_operand_set_seg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_A_GPR_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_A_GPR_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_RCX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_RCX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XED_REG_ECX(xed_decoded_inst_t* d) +{ +xed3_operand_set_reg0(d, XED_REG_ECX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_SE(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_SE(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_REG1_XMM_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_REG2_XMM_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_R_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_R_REG1_VGPRy_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPRy_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_N_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_N_REG1_VGPR32_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPRy_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPRy_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_IMM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPR32_B_IMM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPRy_N_REG1_VGPR32_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPRy_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_MEM0_const1_REG2_XMM_SE_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_B_REG3_XMM_SE_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_SE(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_REG2_YMM_SE_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_REG3_YMM_SE_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_SE(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_XMM_SE_REG3_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_SE_REG3_YMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_SE(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_YMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_YMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_YMM_R_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xa(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xa); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x3); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xa(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xa); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x3); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xd(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xd); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xd(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xd); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x14(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x14); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_MEM0_const1_IMM0_const1_BCAST_const0x14(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +xed3_operand_set_bcast(d, 0x14); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B_IMM0_const1_BCAST_const0x14(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +xed3_operand_set_bcast(d, 0x14); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_N_REG1_XMM_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_N_REG1_YMM_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B_REG1_YMM_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N_REG1_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N_REG1_YMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_N_REG2_XMM_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_YMM_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR32_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_N_REG2_GPR64_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B_REG1_XMM_R_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_REG1_YMM_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_YMM_N_REG2_XMM_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0x11(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x11); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0x11(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x11); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0x12(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x12); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0x12(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x12); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xe(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xe); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xe(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xe); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_MEM0_const1_BCAST_const0xf(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xf); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R_REG1_XMM_B_BCAST_const0xf(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xf); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_MEM0_const1_BCAST_const0xb(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xb); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R_REG1_XMM_B_BCAST_const0xb(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xb); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_N_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_N_REG1_VGPR64_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_N(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N_REG3_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_REG1_VGPR32_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_REG2_VGPR32_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_REG1_VGPR64_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_REG2_VGPR64_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_REG2_VGPR32_B_REG3_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg3(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_N_MEM0_const1_REG2_XED_REG_EDX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg2(d, XED_REG_EDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_REG2_VGPR64_B_REG3_XED_REG_RDX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_reg3(d, XED_REG_RDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_N_MEM0_const1_REG2_XED_REG_RDX(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_reg2(d, XED_REG_RDX); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_REG1_VGPR32_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR32_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_REG1_VGPR64_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_VGPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_VGPR64_R_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_VGPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_N_REG2_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_N(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_TMM_R_REG1_TMM_B_REG2_TMM_N(xed_decoded_inst_t* d) +{ +xed3_capture_nt_TMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_TMM_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_TMM_N(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_TMM_R_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_TMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_TMM_R(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_TMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_TMM_R(xed_decoded_inst_t* d) +{ +xed3_capture_nt_TMM_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASKNOT0(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x2(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x2); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x4(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x4); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x6(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x6); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x5(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x5); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x5(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x5); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xd(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xd); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xd(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xd); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xa(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xa); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xa(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xa); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x3); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x3); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3_REG2_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_rFLAGS(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1_REG1_rFLAGS(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_rFLAGS(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK1(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_B3_REG1_MASK1_REG2_ZMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK1(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK1(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_YMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_ZMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK1(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_XMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK1(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASK1_REG1_YMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASK1(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_R_REG1_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASKNOT0_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASKNOT0(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASKNOT0_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASKNOT0(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASKNOT0_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASKNOT0(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR32_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_B_REG1_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_ZMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_YMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_GPR64_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_XMM_N3_REG3_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xa(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xa); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x3); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0x5(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x5); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xb(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xb); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xb(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xb); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0xb(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xb); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR64_B_BCAST_const0xd(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xd); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_REG3_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_REG3_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_ZMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_B3_REG1_MASK1_REG2_YMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_B3_REG1_MASK1_REG2_ZMM_R3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_B3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_ZMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASKNOT0(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_XMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASKNOT0(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_MEM0_const1_REG0_MASKNOT0_REG1_YMM_R3(xed_decoded_inst_t* d) +{ +xed3_operand_set_mem0(d, 1); +xed3_capture_nt_MASKNOT0(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_ZMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_YMM_N3_REG3_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG3 */ +xed3_operand_set_reg3(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B_BCAST_const0x19(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x19); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B_BCAST_const0x17(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x17); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B_BCAST_const0x18(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x18); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B_BCAST_const0xf(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xf); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B_BCAST_const0x1b(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x1b); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B_BCAST_const0xe(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xe); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x15(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x15); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x15(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x15); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x7(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x7); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x7(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x7); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x9(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x9); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x14(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x14); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x8(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x8); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xc(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xc); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xc(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xc); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_MASK1_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x11(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x11); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x11(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x11); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x11(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x11); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x12(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x12); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x12(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x12); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x12(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x12); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x13(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x13); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x13(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x13); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x13(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x13); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xe(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xe); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xe(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xe); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xe(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xe); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0xf(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xf); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0xf(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0xf); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0xf(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0xf); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_XMM_B3_BCAST_const0x10(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x10); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_MEM0_const1_BCAST_const0x10(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_bcast(d, 0x10); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK1_REG2_GPR32_B_BCAST_const0x10(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_bcast(d, 0x10); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR64_B_REG1_XMM_R3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR64_B(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_R3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_GPR32_R_REG1_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_GPR32_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR32_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR32_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_XMM_N3_REG2_GPR64_B_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_GPR64_B(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_MASK_B(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK_B(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_REG1_XMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_REG1_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_REG1_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_N3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_REG2_YMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_YMM_R3_REG1_YMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_YMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_REG2_ZMM_B3_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_ZMM_R3_REG1_ZMM_N3_MEM0_const1_IMM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_ZMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +xed3_operand_set_imm0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_REG2_XMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_XMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_XMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_REG2_YMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_YMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_YMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_REG2_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_MASK_R_REG1_ZMM_N3_MEM0_const1(xed_decoded_inst_t* d) +{ +xed3_capture_nt_MASK_R(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_N3(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_operand_set_mem0(d, 1); +return XED_ERROR_NONE; +} +static XED_INLINE xed_error_enum_t xed3_capture_chain_ntluf_REG0_XMM_R3_REG1_MASK1_REG2_ZMM_B3(xed_decoded_inst_t* d) +{ +xed3_capture_nt_XMM_R3(d); +/*opname REG0 */ +xed3_operand_set_reg0(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_MASK1(d); +/*opname REG1 */ +xed3_operand_set_reg1(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +xed3_capture_nt_ZMM_B3(d); +/*opname REG2 */ +xed3_operand_set_reg2(d, xed3_operand_get_outreg(d)); +if (xed3_operand_get_error(d)) { +return xed3_operand_get_error(d); +} +return XED_ERROR_NONE; +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-operand-lu.h b/CodeVirtualizer/build/obj/include-private/xed3-operand-lu.h new file mode 100644 index 0000000..f3510c6 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-operand-lu.h @@ -0,0 +1,208 @@ +/// @file include-private/xed3-operand-lu.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_OPERAND_LU_H) +# define INCLUDE_PRIVATE_XED3_OPERAND_LU_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild-eosz-getters.h" +#include "xed-ild-easz-getters.h" +#include "xed-internal-header.h" +#include "xed-ild-private.h" +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_OSZ_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_REP_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_REP_WBNOINVD(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_CLDEMOTE_MOD3_OSZ_REG_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_OSZ_REP_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_OSZ_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_OSZ_REG_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD_REG_REP_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD_REG_REP_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3_REG(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REP_TZCNT(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_LZCNT_MOD3_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD_MODE_SHORT_UD0(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_OSZ(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_OSZ_REP_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3_MODE_REG(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_P4_REP_REXB_SRM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_REP_REXB_SRM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_OSZ_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REXW(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MODEP5_REP(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MODE(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REG_REXW_RM_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REXW_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REG_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REG_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REG_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REG_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REG_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REG_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d); + +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv0.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv0.h new file mode 100644 index 0000000..fb6a8a4 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv0.h @@ -0,0 +1,31 @@ +/// @file include-private/xed3-phash-lu-vv0.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_LU_VV0_H) +# define INCLUDE_PRIVATE_XED3_PHASH_LU_VV0_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +extern const xed3_find_func_t xed3_phash_vv0_map_amd_3dnow[256]; +extern const xed3_find_func_t xed3_phash_vv0_map_legacy_map0[256]; +extern const xed3_find_func_t xed3_phash_vv0_map_legacy_map1[256]; +extern const xed3_find_func_t xed3_phash_vv0_map_legacy_map2[256]; +extern const xed3_find_func_t xed3_phash_vv0_map_legacy_map3[256]; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv1.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv1.h new file mode 100644 index 0000000..d411e67 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv1.h @@ -0,0 +1,29 @@ +/// @file include-private/xed3-phash-lu-vv1.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_LU_VV1_H) +# define INCLUDE_PRIVATE_XED3_PHASH_LU_VV1_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +extern const xed3_find_func_t xed3_phash_vv1_map_vex_map1[256]; +extern const xed3_find_func_t xed3_phash_vv1_map_vex_map2[256]; +extern const xed3_find_func_t xed3_phash_vv1_map_vex_map3[256]; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv2.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv2.h new file mode 100644 index 0000000..e38abd5 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv2.h @@ -0,0 +1,31 @@ +/// @file include-private/xed3-phash-lu-vv2.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_LU_VV2_H) +# define INCLUDE_PRIVATE_XED3_PHASH_LU_VV2_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +extern const xed3_find_func_t xed3_phash_vv2_map_evex_map1[256]; +extern const xed3_find_func_t xed3_phash_vv2_map_evex_map2[256]; +extern const xed3_find_func_t xed3_phash_vv2_map_evex_map3[256]; +extern const xed3_find_func_t xed3_phash_vv2_map_evex_map5[256]; +extern const xed3_find_func_t xed3_phash_vv2_map_evex_map6[256]; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv3.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv3.h new file mode 100644 index 0000000..69e1ccb --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-lu-vv3.h @@ -0,0 +1,29 @@ +/// @file include-private/xed3-phash-lu-vv3.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_LU_VV3_H) +# define INCLUDE_PRIVATE_XED3_PHASH_LU_VV3_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +extern const xed3_find_func_t xed3_phash_vv3_map_amd_xop8[256]; +extern const xed3_find_func_t xed3_phash_vv3_map_amd_xop9[256]; +extern const xed3_find_func_t xed3_phash_vv3_map_amd_xopA[256]; +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-vv0.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv0.h new file mode 100644 index 0000000..1eec4f1 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv0.h @@ -0,0 +1,274085 @@ +/// @file include-private/xed3-phash-vv0.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_VV0_H) +# define INCLUDE_PRIVATE_XED3_PHASH_VV0_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-operand-lu.h" +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x10_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x14_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x15_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x17_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x20_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x21_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x22_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x23_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x24_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x25_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x28_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x29_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x2a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x2b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x30_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x31_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x32_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x33_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x34_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x35_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x37_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x38_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x39_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x40_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x41_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x80_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x81_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x82_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xc8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xc9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xca_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xd8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xde_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xfa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xfb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x14_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x15_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x16_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x17_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x20_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x21_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x22_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x40_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x41_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x42_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x44_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x60_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x61_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x62_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x63_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xcc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xce_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xcf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xdf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xf0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x1c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x1d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x8a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x8e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x90_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x94_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x96_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x97_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x9a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x9e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xaa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xae_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xbb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xbf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x10_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x11_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x12_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x13_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x14_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x15_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x16_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x17_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x18_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x19_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2881_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2028_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7001_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4861_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2821_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_996_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5670_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5040_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6933_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x20_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x21_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x22_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x23_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x28_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x29_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x30_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x31_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x32_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x33_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x34_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x35_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x37_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x40_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x41_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x42_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x43_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x44_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x45_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x46_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x47_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x48_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x49_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x50_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x51_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x52_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x53_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x54_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x55_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x56_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x57_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x58_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x59_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x60_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x61_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x62_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x63_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x64_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x65_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x66_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x67_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x68_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x69_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x70_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x71_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x72_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x73_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x74_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x75_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x76_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x77_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x78_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x79_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x80_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x81_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x82_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x83_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x84_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x85_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x86_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x87_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x88_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x89_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x90_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x91_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x92_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x93_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x94_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x95_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x96_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x97_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x98_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x99_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xaa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xab_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xac_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xad_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xaf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xba_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xca_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xce_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xda_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xde_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xea_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xeb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xec_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xed_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xee_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xef_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xff_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x10_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x11_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x12_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x13_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x14_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x15_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x16_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x17_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x18_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x19_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x20_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x21_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x22_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x23_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x24_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x25_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x27_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x28_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x29_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x30_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x31_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x32_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x33_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x34_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x35_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x37_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x38_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x39_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x40_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x41_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x42_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x43_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x44_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x45_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x46_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x47_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x48_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x49_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x50_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x51_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x52_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x53_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x54_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x55_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x56_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x57_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x58_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x59_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x60_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x61_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x62_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x63_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x68_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x69_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x70_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x71_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x72_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x73_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x74_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x75_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x76_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x77_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x78_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x79_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x80_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x81_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x82_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x83_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x84_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x85_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x86_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x87_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x88_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x89_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x90_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x91_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x92_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x93_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x94_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x95_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x96_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x97_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x98_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x99_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9a_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9b_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9c_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9d_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9e_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9f_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xaa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xab_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xac_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xad_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xae_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xaf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xba_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xca_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xce_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1076_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_928_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_887_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1096_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_916_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1037_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1062_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1094_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_907_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_779_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1060_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1067_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_736_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_772_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_987_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_872_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_706_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_774_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1055_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_799_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1048_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_865_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_998_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1023_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_745_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_989_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_797_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_840_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_765_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xda_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xde_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdf_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe0_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe2_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe3_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xea_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xeb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xec_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xed_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xee_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xef_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf1_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf4_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf5_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf6_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf7_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf8_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf9_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfa_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfb_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfc_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfd_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfe_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xff_vv0(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x00 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1753}, +/*h(1)=1 0x0F 0x38 0x00 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1754}, +/*h(2)=2 0x0F 0x38 0x00 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1755}, +/*h(3)=3 0x0F 0x38 0x00 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x01 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1721}, +/*h(1)=1 0x0F 0x38 0x01 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1722}, +/*h(2)=2 0x0F 0x38 0x01 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1723}, +/*h(3)=3 0x0F 0x38 0x01 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1724} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x02 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1725}, +/*h(1)=1 0x0F 0x38 0x02 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1726}, +/*h(2)=2 0x0F 0x38 0x02 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1727}, +/*h(3)=3 0x0F 0x38 0x02 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1728} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x03 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1729}, +/*h(1)=1 0x0F 0x38 0x03 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1730}, +/*h(2)=2 0x0F 0x38 0x03 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1731}, +/*h(3)=3 0x0F 0x38 0x03 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1732} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x04 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1745}, +/*h(1)=1 0x0F 0x38 0x04 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1746}, +/*h(2)=2 0x0F 0x38 0x04 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1747}, +/*h(3)=3 0x0F 0x38 0x04 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x05 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1733}, +/*h(1)=1 0x0F 0x38 0x05 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1734}, +/*h(2)=2 0x0F 0x38 0x05 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1735}, +/*h(3)=3 0x0F 0x38 0x05 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x06 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1737}, +/*h(1)=1 0x0F 0x38 0x06 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1738}, +/*h(2)=2 0x0F 0x38 0x06 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1739}, +/*h(3)=3 0x0F 0x38 0x06 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x07 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1741}, +/*h(1)=1 0x0F 0x38 0x07 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1742}, +/*h(2)=2 0x0F 0x38 0x07 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1743}, +/*h(3)=3 0x0F 0x38 0x07 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1744} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x08 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1757}, +/*h(1)=1 0x0F 0x38 0x08 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1758}, +/*h(2)=2 0x0F 0x38 0x08 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1759}, +/*h(3)=3 0x0F 0x38 0x08 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1760} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x09 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1761}, +/*h(1)=1 0x0F 0x38 0x09 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1762}, +/*h(2)=2 0x0F 0x38 0x09 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1763}, +/*h(3)=3 0x0F 0x38 0x09 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1764} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x0A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1765}, +/*h(1)=1 0x0F 0x38 0x0A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1766}, +/*h(2)=2 0x0F 0x38 0x0A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1767}, +/*h(3)=3 0x0F 0x38 0x0A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1768} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x0B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1749}, +/*h(1)=1 0x0F 0x38 0x0B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1750}, +/*h(2)=2 0x0F 0x38 0x0B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1751}, +/*h(3)=3 0x0F 0x38 0x0B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x10_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1818}, +/*h(3)=1 0x0F 0x38 0x10 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1819} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x14_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1799}, +/*h(3)=1 0x0F 0x38 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1800} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x15_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1797}, +/*h(3)=1 0x0F 0x38 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1798} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x17_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1842}, +/*h(3)=1 0x0F 0x38 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1843} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x1C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1773}, +/*h(1)=1 0x0F 0x38 0x1C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1774}, +/*h(2)=2 0x0F 0x38 0x1C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1775}, +/*h(3)=3 0x0F 0x38 0x1C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1776} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x1D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1777}, +/*h(1)=1 0x0F 0x38 0x1D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1778}, +/*h(2)=2 0x0F 0x38 0x1D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1779}, +/*h(3)=3 0x0F 0x38 0x1D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1780} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x1e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0x1E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1781}, +/*h(1)=1 0x0F 0x38 0x1E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1782}, +/*h(2)=2 0x0F 0x38 0x1E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1783}, +/*h(3)=3 0x0F 0x38 0x1E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1784} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x20_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1866}, +/*h(3)=1 0x0F 0x38 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1867} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x21_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1868}, +/*h(3)=1 0x0F 0x38 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1869} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x22_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1870}, +/*h(3)=1 0x0F 0x38 0x22 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1871} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x23_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1872}, +/*h(3)=1 0x0F 0x38 0x23 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1873} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x24_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1874}, +/*h(3)=1 0x0F 0x38 0x24 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1875} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x25_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1876}, +/*h(3)=1 0x0F 0x38 0x25 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1877} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x28_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1864}, +/*h(3)=1 0x0F 0x38 0x28 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1865} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x29_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1801}, +/*h(3)=1 0x0F 0x38 0x29 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1802} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x2a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2)=0 0x0F 0x38 0x2A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1807} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x2b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1814}, +/*h(3)=1 0x0F 0x38 0x2B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1815} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x30_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1878}, +/*h(3)=1 0x0F 0x38 0x30 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1879} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x31_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1880}, +/*h(3)=1 0x0F 0x38 0x31 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1881} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x32_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1882}, +/*h(3)=1 0x0F 0x38 0x32 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1883} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x33_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1884}, +/*h(3)=1 0x0F 0x38 0x33 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1885} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x34_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1886}, +/*h(3)=1 0x0F 0x38 0x34 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1887} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x35_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1888}, +/*h(3)=1 0x0F 0x38 0x35 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1889} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x37_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x37 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1787}, +/*h(3)=1 0x0F 0x38 0x37 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1788} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x38_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1854}, +/*h(3)=1 0x0F 0x38 0x38 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1855} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x39_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1856}, +/*h(3)=1 0x0F 0x38 0x39 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1857} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1860}, +/*h(3)=1 0x0F 0x38 0x3A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1861} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1858}, +/*h(3)=1 0x0F 0x38 0x3B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1859} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1846}, +/*h(3)=1 0x0F 0x38 0x3C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1847} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1848}, +/*h(3)=1 0x0F 0x38 0x3D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1849} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1852}, +/*h(3)=1 0x0F 0x38 0x3E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1853} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x3f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1850}, +/*h(3)=1 0x0F 0x38 0x3F osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1851} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x40_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1862}, +/*h(3)=1 0x0F 0x38 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1863} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x41_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1844}, +/*h(3)=1 0x0F 0x38 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1845} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x80_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10)=0 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()*/ {10, 1934}, +/*h(12)=1 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH()*/ {12, 1933}, +/*h(8)=2 0x0F 0x38 0x80 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()*/ {8, 1934} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x81_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10)=0 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()*/ {10, 1936}, +/*h(12)=1 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH()*/ {12, 1935}, +/*h(8)=2 0x0F 0x38 0x81 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()*/ {8, 1936} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0x82_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10)=0 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()*/ {10, 2129}, +/*h(12)=1 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 MODRM() CR_WIDTH()*/ {12, 2128}, +/*h(8)=2 0x0F 0x38 0x82 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM() CR_WIDTH()*/ {8, 2129} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xc8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x38 0xC8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix*/ {2081}, +/*h(1)=1 0x0F 0x38 0xC8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xc9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x38 0xC9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix*/ {2077}, +/*h(1)=1 0x0F 0x38 0xC9 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xca_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x38 0xCA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix*/ {2079}, +/*h(1)=1 0x0F 0x38 0xCA MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x38 0xCB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix*/ {2089}, +/*h(1)=1 0x0F 0x38 0xCB MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x38 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix*/ {2085}, +/*h(1)=1 0x0F 0x38 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x38 0xCD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix*/ {2087}, +/*h(1)=1 0x0F 0x38 0xCD MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xcf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix*/ {2162}, +/*h(3)=1 0x0F 0x38 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2161} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xd8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(52)=0 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() f3_refining_prefix*/ {52, 2170}, +/*h(54)=1 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() f3_refining_prefix*/ {54, 2166}, +/*h(48)=2 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix*/ {48, 2169}, +/*h(50)=3 0x0F 0x38 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() f3_refining_prefix*/ {50, 2165} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_REP(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x38 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1930}, +/*h(3)=1 0x0F 0x38 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1929} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(13)=0 0x0F 0x38 0xDC f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2173}, +/*h(2)=1 0x0F 0x38 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1922}, +/*h(15)=2 0x0F 0x38 0xDC f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2173}, +/*h(12)=3 0x0F 0x38 0xDC f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2167}, +/*empty slot1 */ {0,0}, +/*h(14)=5 0x0F 0x38 0xDC f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2167}, +/*h(3)=6 0x0F 0x38 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1921}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2)=0 0x0F 0x38 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1924}, +/*h(12)=1 0x0F 0x38 0xDD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2163}, +/*h(14)=2 0x0F 0x38 0xDD f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2163}, +/*h(3)=3 0x0F 0x38 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1923} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xde_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2)=0 0x0F 0x38 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1926}, +/*h(12)=1 0x0F 0x38 0xDE f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2168}, +/*h(14)=2 0x0F 0x38 0xDE f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2168}, +/*h(3)=3 0x0F 0x38 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1925} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xdf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2)=0 0x0F 0x38 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1928}, +/*h(12)=1 0x0F 0x38 0xDF f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2164}, +/*h(14)=2 0x0F 0x38 0xDF f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2164}, +/*h(3)=3 0x0F 0x38 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1927} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x38 0xF0 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1916}, +/*h(4)=1 0x0F 0x38 0xF0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 1789}, +/*h(5)=2 0x0F 0x38 0xF0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 1790} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x38 0xF1 not_refining MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1917}, +/*h(4)=1 0x0F 0x38 0xF1 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 1791}, +/*h(5)=2 0x0F 0x38 0xF1 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 1792} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(10)=0 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0*/ {10, 2073}, +/*h(76)=1 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 mode64*/ {76, 2074}, +/*h(12)=2 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0*/ {12, 2073}, +/*h(8)=3 0x0F 0x38 0xF5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0*/ {8, 2073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((6*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[56] = { +/*h(0)=0 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0*/ {0, 2071}, +/*h(4)=1 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0*/ {4, 2071}, +/*h(8)=2 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66()*/ {8, 2141}, +/*h(12)=3 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66()*/ {12, 2141}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=6 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66()*/ {11, 2140}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(48)=12 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()*/ {48, 2145}, +/*h(52)=13 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()*/ {52, 2145}, +/*h(56)=14 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()*/ {56, 2145}, +/*h(60)=15 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()*/ {60, 2145}, +/*h(51)=16 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()*/ {51, 2144}, +/*h(68)=17 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W1 mode64*/ {68, 2072}, +/*h(59)=18 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()*/ {59, 2144}, +/*h(76)=19 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W1 IMMUNE66() mode64*/ {76, 2143}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=22 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66()*/ {9, 2140}, +/*h(13)=23 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W0 IMMUNE66()*/ {13, 2140}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=29 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() mode64*/ {116, 2147}, +/*empty slot1 */ {0,0}, +/*h(124)=31 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W1 IMMUNE66() mode64*/ {124, 2147}, +/*h(49)=32 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()*/ {49, 2144}, +/*h(53)=33 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()*/ {53, 2144}, +/*h(57)=34 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()*/ {57, 2144}, +/*h(61)=35 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W0 IMMUNE66()*/ {61, 2144}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=39 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix W1 IMMUNE66() mode64*/ {77, 2142}, +/*h(2)=40 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix W0*/ {2, 2071}, +/*empty slot1 */ {0,0}, +/*h(10)=42 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix W0 IMMUNE66()*/ {10, 2141}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(117)=49 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() mode64*/ {117, 2146}, +/*empty slot1 */ {0,0}, +/*h(125)=51 0x0F 0x38 0xF6 MOD[0b11] MOD=3 REG[rrr] RM[nnn] refining_f3 W1 IMMUNE66() mode64*/ {125, 2146}, +/*h(50)=52 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()*/ {50, 2145}, +/*empty slot1 */ {0,0}, +/*h(58)=54 0x0F 0x38 0xF6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() refining_f3 W0 IMMUNE66()*/ {58, 2145}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((20*key % 79) % 56); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*h(34)=0 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {34, 2180}, +/*h(60)=1 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {60, 2181}, +/*h(52)=2 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {52, 2181}, +/*h(10)=3 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64*/ {10, 2112}, +/*h(44)=4 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {44, 2180}, +/*h(36)=5 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {36, 2180}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=8 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix mode64*/ {12, 2113}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=12 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {56, 2181}, +/*h(48)=13 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {48, 2181}, +/*empty slot1 */ {0,0}, +/*h(40)=15 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {40, 2180}, +/*h(32)=16 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {32, 2180}, +/*h(58)=17 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {58, 2181}, +/*h(50)=18 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {50, 2181}, +/*h(8)=19 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix not64*/ {8, 2112}, +/*h(42)=20 0x0F 0x38 0xF8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {42, 2180} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xf9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix*/ {0, 2114}, +/*h(4)=1 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix*/ {4, 2114}, +/*h(68)=2 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64 rexw_prefix*/ {68, 2115}, +/*h(2)=3 0x0F 0x38 0xF9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix norexw_prefix*/ {2, 2114} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((4*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xfa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7)=0 0x0F 0x38 0xFA MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {2171} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP(d); +hidx = key - 7; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map2_opcode0xfb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7)=0 0x0F 0x38 0xFB MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {2172} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP(d); +hidx = key - 7; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1836}, +/*h(3)=1 0x0F 0x3A 0x08 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1837} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1834}, +/*h(3)=1 0x0F 0x3A 0x09 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1835} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1840}, +/*h(3)=1 0x0F 0x3A 0x0A osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1841} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1838}, +/*h(3)=1 0x0F 0x3A 0x0B osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1839} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1795}, +/*h(3)=1 0x0F 0x3A 0x0C osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1796} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1793}, +/*h(3)=1 0x0F 0x3A 0x0D osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1794} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xe_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1816}, +/*h(3)=1 0x0F 0x3A 0x0E osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1817} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x3A 0x0F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1769}, +/*h(1)=1 0x0F 0x3A 0x0F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1770}, +/*h(2)=2 0x0F 0x3A 0x0F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {1771}, +/*h(3)=3 0x0F 0x3A 0x0F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {1772} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x14_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1820}, +/*h(3)=1 0x0F 0x3A 0x14 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1821} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x15_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1822}, +/*h(3)=1 0x0F 0x3A 0x15 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1823} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x16_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(77)=0 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {77, 1825}, +/*h(76)=1 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {76, 1824}, +/*h(13)=2 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {13, 1827}, +/*h(12)=3 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {12, 1826}, +/*h(11)=4 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 1827}, +/*h(10)=5 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 1826}, +/*h(9)=6 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 1827}, +/*h(8)=7 0x0F 0x3A 0x16 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 1826} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((30*key % 31) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x17_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1808}, +/*h(3)=1 0x0F 0x3A 0x17 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1809} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x20_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1828}, +/*h(3)=1 0x0F 0x3A 0x20 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1829} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x21_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1810}, +/*h(3)=1 0x0F 0x3A 0x21 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1811} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x22_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(77)=0 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {77, 1833}, +/*h(76)=1 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() rexw_prefix mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {76, 1832}, +/*h(13)=2 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {13, 1831}, +/*h(12)=3 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {12, 1830}, +/*h(11)=4 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 1831}, +/*h(10)=5 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 1830}, +/*h(9)=6 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 1831}, +/*h(8)=7 0x0F 0x3A 0x22 osz_refining_prefix REFINING66() norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 1830} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((30*key % 31) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x40_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1805}, +/*h(3)=1 0x0F 0x3A 0x40 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1806} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x41_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1803}, +/*h(3)=1 0x0F 0x3A 0x41 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1804} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x42_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1812}, +/*h(3)=1 0x0F 0x3A 0x42 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1813} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x44_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x44 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {1932}, +/*h(3)=1 0x0F 0x3A 0x44 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {1931} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x60_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*h(13)=0 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {13, 1905}, +/*empty slot1 */ {0,0}, +/*h(73)=2 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {73, 1903}, +/*h(10)=3 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 1902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=7 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {75, 1903}, +/*h(12)=8 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {12, 1904}, +/*empty slot1 */ {0,0}, +/*h(72)=10 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {72, 1902}, +/*h(9)=11 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 1903}, +/*h(77)=12 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {77, 1907}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=15 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {74, 1902}, +/*h(11)=16 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 1903}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=19 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 1902}, +/*h(76)=20 0x0F 0x3A 0x60 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {76, 1906} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x61_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*h(13)=0 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {13, 1893}, +/*empty slot1 */ {0,0}, +/*h(73)=2 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {73, 1891}, +/*h(10)=3 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 1890}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=7 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {75, 1891}, +/*h(12)=8 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {12, 1892}, +/*empty slot1 */ {0,0}, +/*h(72)=10 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {72, 1890}, +/*h(9)=11 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 1891}, +/*h(77)=12 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {77, 1895}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=15 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {74, 1890}, +/*h(11)=16 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 1891}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=19 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 1890}, +/*h(76)=20 0x0F 0x3A 0x61 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {76, 1894} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x62_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1908}, +/*h(3)=1 0x0F 0x3A 0x62 osz_refining_prefix IMMUNE66() MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1909} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0x63_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*h(13)=0 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {13, 1899}, +/*empty slot1 */ {0,0}, +/*h(73)=2 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {73, 1897}, +/*h(10)=3 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 1896}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=7 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {75, 1897}, +/*h(12)=8 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {12, 1898}, +/*empty slot1 */ {0,0}, +/*h(72)=10 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {72, 1896}, +/*h(9)=11 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 1897}, +/*h(77)=12 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {77, 1901}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=15 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {74, 1896}, +/*h(11)=16 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 1897}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=19 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 1896}, +/*h(76)=20 0x0F 0x3A 0x63 osz_refining_prefix IMMUNE66() mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {76, 1900} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xcc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x3A 0xCC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix UIMM8()*/ {2083}, +/*h(1)=1 0x0F 0x3A 0xCC MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix UIMM8()*/ {2082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xce_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0xCE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8()*/ {2160}, +/*h(3)=1 0x0F 0x3A 0xCE MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8()*/ {2159} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xcf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0xCF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix UIMM8()*/ {2158}, +/*h(3)=1 0x0F 0x3A 0xCF MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix UIMM8()*/ {2157} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xdf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x3A 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {1920}, +/*h(3)=1 0x0F 0x3A 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {1919} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map3_opcode0xf0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(49)=0 0x0F 0x3A 0xF0 MOD[0b11] MOD=3 REG[0b000] RM[0b000] f3_refining_prefix UIMM8()*/ {2174} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_REP_RM(d); +hidx = key - 49; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0C*/ {1956}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0C*/ {1957} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x0D*/ {1958}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x0D*/ {1959} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x1c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1C*/ {1960}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1C*/ {1961} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x1d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x1D*/ {1962}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x1D*/ {1963} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x8a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8A*/ {1964}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8A*/ {1965} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x8e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x8E*/ {1966}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x8E*/ {1967} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x90_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x90*/ {1968}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x90*/ {1969} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x94_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x94*/ {1970}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x94*/ {1971} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x96_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x96*/ {1972}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x96*/ {1973} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x97_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x97*/ {1974}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x97*/ {1975} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x9a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9A*/ {1976}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9A*/ {1977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0x9e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0x9E*/ {1978}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0x9E*/ {1979} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA0*/ {1980}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA0*/ {1981} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA4*/ {1982}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA4*/ {1983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA6*/ {1984}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA6*/ {1985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xa7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xA7*/ {1986}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xA7*/ {1987} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xaa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAA*/ {1988}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAA*/ {1989} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xae_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xAE*/ {1990}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xAE*/ {1991} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB0*/ {1992}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB0*/ {1993} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB4*/ {1994}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB4*/ {1995} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB6*/ {1996}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB6*/ {1997} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xb7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xB7*/ {1998}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xB7*/ {1999} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xbb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBB*/ {2000}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBB*/ {2001} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_3dnow_opcode0xbf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() 0xBF*/ {2002}, +/*h(1)=1 0x0F 0x0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] 0xBF*/ {2003} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x00 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {544}, +/*h(1)=1 0x0F 0x00 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {545}, +/*h(2)=2 0x0F 0x00 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {546}, +/*h(3)=3 0x0F 0x00 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {547}, +/*h(4)=4 0x0F 0x00 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {548}, +/*h(5)=5 0x0F 0x00 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {549}, +/*h(6)=6 0x0F 0x00 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {550}, +/*h(7)=7 0x0F 0x00 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {551}, +/*h(8)=8 0x0F 0x00 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {552}, +/*h(9)=9 0x0F 0x00 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {553}, +/*h(10)=10 0x0F 0x00 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {554}, +/*h(11)=11 0x0F 0x00 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {555} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 11) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3086_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4326, 2008}, +/*h(145)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {145, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1749_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6374)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6374, 2009}, +/*h(2193)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {2193, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8422, 2010}, +/*h(4241)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {4241, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4094_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10470, 2011}, +/*h(6289)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {6289, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2757_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12518, 2012}, +/*h(8337)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {8337, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1420_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14566, 2013}, +/*h(10385)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {10385, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12433)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3765_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {14481, 556}, +/*h(3535)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3535, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1080_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14163, 2068}, +/*h(3217)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3217, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5265, 556}, +/*h(16211)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16211, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2511)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2511, 753}, +/*h(13457)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {13457, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5862)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5862, 2008}, +/*h(1681)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1681, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7910)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7910, 2009}, +/*h(3729)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3729, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1919_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9958)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9958, 2010}, +/*h(5777)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5777, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_582_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12006)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {12006, 2011}, +/*h(7825)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {7825, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4263_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9873)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {9873, 556}, +/*h(12457)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {12457, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2926_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14505, 557}, +/*h(11921)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11921, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13969)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16017)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1967_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1638_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12550, 559}, +/*h(8369)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {8369, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14598)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14598, 559}, +/*h(10417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {10417, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2646_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3567)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3567, 753}, +/*h(14513)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {14513, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1299_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12147, 2068}, +/*h(5382)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5382, 559}, +/*h(1201)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1201, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4981_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3249)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3249, 556}, +/*h(14195)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14195, 2068}, +/*h(7430)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7430, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3643_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7881)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7881, 743}, +/*h(5297)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5297, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9929)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9929, 743}, +/*h(7345)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {7345, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_969_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {9393, 556}, +/*h(11977)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {11977, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4651_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14025)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14025, 743}, +/*h(11441)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11441, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {13489, 556}, +/*h(16073)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {16073, 743}, +/*h(2543)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2543, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3474_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5894)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5894, 559}, +/*h(1713)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1713, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7942)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7942, 559}, +/*h(3761)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3761, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_800_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9990)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9990, 559}, +/*h(5809)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5809, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4482_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12038)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12038, 559}, +/*h(7857)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {7857, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14086)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14086, 559}, +/*h(9905)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {9905, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1808_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16134)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16134, 559}, +/*h(11953)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11953, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {471, 752}, +/*h(14001)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {14001, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2519)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2519, 753}, +/*h(16049)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {16049, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {146, 556}, +/*h(4327)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4327, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4851_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {2194, 556}, +/*h(6375)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6375, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3514_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {4242, 556}, +/*h(8423)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8423, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {6290, 556}, +/*h(10471)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10471, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_840_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {8338, 556}, +/*h(12519)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12519, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {10386, 556}, +/*h(14567)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14567, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {4266, 557}, +/*h(1682)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1682, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {6314, 557}, +/*h(3730)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3730, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5778, 556}, +/*h(8362)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {8362, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3683_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {10410, 557}, +/*h(7826)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {7826, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2346_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {12458, 557}, +/*h(9874)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {9874, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1009_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11922, 556}, +/*h(14506)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14506, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {178, 556}, +/*h(4359)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {4359, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3732_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {2226, 556}, +/*h(6407)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {6407, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {4274, 556}, +/*h(8455)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8455, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1058_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {6322, 556}, +/*h(10503)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10503, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4740_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {8370, 556}, +/*h(12551)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12551, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {10418, 556}, +/*h(14599)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14599, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4400_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3786)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3786, 743}, +/*h(1202)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1202, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3063_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5834)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5834, 743}, +/*h(3250)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3250, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1726_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5298, 556}, +/*h(7882)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7882, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_389_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9930)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9930, 743}, +/*h(7346)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {7346, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4071_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2734_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1557_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1714, 556}, +/*h(5895)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5895, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3762, 556}, +/*h(7943)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7943, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3902_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5810, 556}, +/*h(9991)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9991, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2565_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {7858, 556}, +/*h(12039)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12039, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1228_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {9906, 556}, +/*h(14087)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14087, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4910_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11954, 556}, +/*h(16135)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16135, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2195)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6291)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3602_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64*/ {12117, 2178}, +/*h(1171)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1171, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3219)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {3219, 556}, +/*h(14165)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64*/ {14165, 2175} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_928_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {5267, 556}, +/*h(16213)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64*/ {16213, 2177} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7315)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9363)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1936_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {465, 751}, +/*h(11411)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11411, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_599_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2513)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2513, 751}, +/*h(13459)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {13459, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {15507, 556}, +/*h(4561)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4561, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1683)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1683, 556}, +/*h(4267)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {4267, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16019)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2227)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1521, 751}, +/*h(12467)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {12467, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3831_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3569)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3569, 751}, +/*h(14515)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {14515, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1203)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {1203, 556}, +/*h(14733)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14733, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3251)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7347)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9395)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_817_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {497, 751}, +/*h(11443)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {11443, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4499_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {13491, 556}, +/*h(2545)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2545, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3162_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4593, 751}, +/*h(15539)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {15539, 556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1715)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7859)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14003)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16051)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] mode64 FORCE64() MODRM()*/ {556} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_971_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12417)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2977_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5334)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5334, 2008}, +/*h(1153)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1153, 557}, +/*h(12099)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12099, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1640_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14147, 2068}, +/*h(3201)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3201, 557}, +/*h(7382)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7382, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9430)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9430, 2010}, +/*h(5249)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5249, 557}, +/*h(16195)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16195, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3985_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11478)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11478, 2011}, +/*h(7297)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7297, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2648_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13526)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13526, 2012}, +/*h(9345)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9345, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15574, 2013}, +/*h(11393)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11393, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1959)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1959, 561}, +/*h(15489)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {15489, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5846)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5846, 2008}, +/*h(1665)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1665, 557}, +/*h(8430)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8430, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3815_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10478)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10478, 2011}, +/*h(3713)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3713, 557}, +/*h(7894)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7894, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2478_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5761)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5761, 557}, +/*h(9942)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9942, 2010}, +/*h(12526)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12526, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14574, 2013}, +/*h(11990)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11990, 2011}, +/*h(7809)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7809, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4823_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14038)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14038, 2012}, +/*h(9857)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9857, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3486_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16086)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16086, 2013}, +/*h(11905)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11905, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13953)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16001)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8353)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1858_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(12131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12131, 2068}, +/*h(1185)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1185, 557}, +/*h(7950)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7950, 559}, +/*h(5366)=3 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5366, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3233, 557}, +/*h(14179)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14179, 2068}, +/*h(9998)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9998, 559}, +/*h(7414)=3 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7414, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(12046)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12046, 559}, +/*h(9462)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9462, 2010}, +/*h(5281)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5281, 557}, +/*h(16227)=3 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16227, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2866_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7329, 557}, +/*h(11510)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11510, 2011}, +/*h(14094)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14094, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1529_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16142)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16142, 559}, +/*h(13558)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13558, 2012}, +/*h(9377)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9377, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15606)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15606, 2013}, +/*h(11425)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11425, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4033_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8462)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8462, 559}, +/*h(1697)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1697, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2696_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10510)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10510, 559}, +/*h(3745)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3745, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1359_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12558, 559}, +/*h(5793)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5793, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14606)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14606, 559}, +/*h(7841)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7841, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9889)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11937)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13985)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16033)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2185)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10377)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4044_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3527)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3527, 753}, +/*h(14473)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14473, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2697_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7926)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7926, 2009}, +/*h(1161)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1161, 557}, +/*h(12107)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12107, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14155)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14155, 2068}, +/*h(9974)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9974, 2010}, +/*h(3209)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3209, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5257, 557}, +/*h(16203)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16203, 2068}, +/*h(12022)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {12022, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14070, 2012}, +/*h(7305)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7305, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2368_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16118, 2013}, +/*h(9353)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9353, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {13449, 557}, +/*h(2503)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2503, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4872_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8438, 2010}, +/*h(1673)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1673, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10486, 2011}, +/*h(3721)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3721, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12534, 2012}, +/*h(5769)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5769, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_861_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14582)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14582, 2013}, +/*h(7817)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7817, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9865)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11913)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13961)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16009)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2217)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1578_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(7958)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7958, 559}, +/*h(14723)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14723, 560}, +/*h(1193)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1193, 557}, +/*h(12139)=3 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12139, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((7*key % 23) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3241, 557}, +/*h(14187)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14187, 2068}, +/*h(10006)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10006, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3923_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12054)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12054, 559}, +/*h(16235)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16235, 2068}, +/*h(5289)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5289, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2586_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14102)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14102, 559}, +/*h(7337)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7337, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16150)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16150, 559}, +/*h(9385)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9385, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11433)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3594_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2535)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2535, 753}, +/*h(13481)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {13481, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3753_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8470, 559}, +/*h(4289)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {4289, 743}, +/*h(1705)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1705, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2416_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10518, 559}, +/*h(3753)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3753, 557}, +/*h(6337)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {6337, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1079_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12566, 559}, +/*h(8385)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {8385, 743}, +/*h(5801)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5801, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4761_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7849)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7849, 557}, +/*h(14614)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14614, 559}, +/*h(10433)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {10433, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3424_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9897)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9897, 557}, +/*h(12481)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12481, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2087_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14529, 743}, +/*h(11945)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11945, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13993)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16041)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1728_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1060_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1154)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1154, 557}, +/*h(5335)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5335, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4742_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3202, 557}, +/*h(7383)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7383, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5250, 557}, +/*h(9431)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9431, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2068_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7298, 557}, +/*h(11479)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11479, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_731_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9346, 557}, +/*h(13527)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13527, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11394, 557}, +/*h(15575)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15575, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3235_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1666, 557}, +/*h(5847)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5847, 2008}, +/*h(8431)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8431, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1898_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10479)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10479, 2011}, +/*h(7895)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7895, 2009}, +/*h(3714)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3714, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12527)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12527, 2012}, +/*h(9943)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9943, 2010}, +/*h(5762)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5762, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4243_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7810, 557}, +/*h(11991)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11991, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2906_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9858, 557}, +/*h(14039)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14039, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11906, 557}, +/*h(16087)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16087, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {4258, 557}, +/*h(77)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16*/ {77, 745} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {6306, 557}, +/*h(2125)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {2125, 748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {8354, 557}, +/*h(4173)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {4173, 2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3962_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {10402, 557}, +/*h(6221)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {6221, 2105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4960_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1186, 557}, +/*h(5367)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5367, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3623_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3234, 557}, +/*h(7415)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7415, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5282, 557}, +/*h(9463)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9463, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_949_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7330, 557}, +/*h(11511)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11511, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4631_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9378, 557}, +/*h(13559)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13559, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11426, 557}, +/*h(15607)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15607, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2116_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1698, 557}, +/*h(8463)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8463, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_779_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3746, 557}, +/*h(10511)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10511, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5794, 557}, +/*h(12559)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12559, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7842, 557}, +/*h(14607)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14607, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_780_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1162, 557}, +/*h(7927)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7927, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4462_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3210, 557}, +/*h(9975)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9975, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5258, 557}, +/*h(12023)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {12023, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1788_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7306, 557}, +/*h(14071)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14071, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9354, 557}, +/*h(16119)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16119, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2955_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1674)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1674, 557}, +/*h(8439)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8439, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1618_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3722)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3722, 557}, +/*h(10487)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10487, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5770)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5770, 557}, +/*h(12535)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12535, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7818)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7818, 557}, +/*h(14583)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14583, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9866)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11914)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4971_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13962)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16010)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4680_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1194, 557}, +/*h(7959)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7959, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3242, 557}, +/*h(10007)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10007, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2006_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5290, 557}, +/*h(12055)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12055, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7338, 557}, +/*h(14103)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14103, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4351_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {9386, 557}, +/*h(16151)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16151, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8471, 559}, +/*h(4290)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {4290, 743}, +/*h(1706)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1706, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_499_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3754)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3754, 557}, +/*h(10519)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10519, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5802)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {5802, 557}, +/*h(12567)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12567, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7850)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {7850, 557}, +/*h(14615)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14615, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9898)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11946)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13994)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16042)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4227)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1473, 751}, +/*h(12419)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {12419, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3521, 751}, +/*h(14467)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14467, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1155)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3203)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5251)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9347)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {449, 751}, +/*h(11395)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11395, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13443)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {13443, 557}, +/*h(2497)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2497, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4840_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4545)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4545, 751}, +/*h(15491)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {15491, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1667, 557}, +/*h(12613)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {12613, 2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14661)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {14661, 2149}, +/*h(3715)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3715, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9859)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3334_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {425, 560}, +/*h(13955)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {13955, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1997_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2473, 560}, +/*h(16003)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {16003, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2211)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1037_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(78)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32*/ {78, 744}, +/*h(4259)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {4259, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2126)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {2126, 748}, +/*h(6307)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {6307, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3382_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4174)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {4174, 2104}, +/*h(8355)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {8355, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2045_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6222)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {6222, 2105}, +/*h(10403)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {10403, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1505, 751}, +/*h(12451)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {12451, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14499, 557}, +/*h(3553)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3553, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1187)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3235)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11427)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3722_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1993)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1993, 751}, +/*h(15523)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {15523, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3747)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5795)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11939)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13987)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(139)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2187)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4235)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1547_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1481, 751}, +/*h(12427)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {12427, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14475, 557}, +/*h(3529)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3529, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3211)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7307)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11403, 557}, +/*h(457)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {457, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_879_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2505, 751}, +/*h(13451)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {13451, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1969)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1969, 560}, +/*h(4553)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4553, 751}, +/*h(15499)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {15499, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1038_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12621)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {12621, 2148}, +/*h(1675)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {1675, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4720_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3723)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {3723, 557}, +/*h(14669)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {14669, 2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5771)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7819)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9867)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11915)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13963)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16011)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(171)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2219)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2134)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {2134, 748}, +/*h(6315)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {6315, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4182)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {4182, 2104}, +/*h(8363)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {8363, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1765_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6230)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {6230, 2105}, +/*h(10411)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {10411, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_428_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {12459, 557}, +/*h(1513)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1513, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3561)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3561, 751}, +/*h(14507)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {14507, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1195)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5291)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {489, 751}, +/*h(11435)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {11435, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4779_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2537, 751}, +/*h(13483)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {13483, 557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3442_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {15531, 557}, +/*h(4585)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4585, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1707)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3755)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5803)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7851)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9899)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11947)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13995)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16043)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM()*/ {557} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4353)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3860_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12630)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {12630, 2148}, +/*h(8449)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8449, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2523_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14678)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {14678, 2149}, +/*h(10497)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10497, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12545)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1281, 558}, +/*h(12227)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12227, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3329, 558}, +/*h(14275)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14275, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5377)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1854_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13569)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4199_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {490, 751}, +/*h(15617)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {15617, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_677_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1793, 558}, +/*h(12739)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12739, 751}, +/*h(5974)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {5974, 2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4359_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14787)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14787, 751}, +/*h(3841)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3841, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64*/ {10070, 2179}, +/*h(5889)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5889, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64*/ {12118, 2178}, +/*h(7937)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7937, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14166)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64*/ {14166, 2175}, +/*h(9985)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {9985, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4030_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16214)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64*/ {16214, 2177}, +/*h(12033)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12033, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2337)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4385)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6433)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14625)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2402_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1313, 558}, +/*h(12259)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12259, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1065_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14307)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14307, 751}, +/*h(3361)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3361, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4747_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5409, 558}, +/*h(16355)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16355, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7457)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11553)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3081_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2119)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {2119, 748}, +/*h(15649)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {15649, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4577_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8590)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8590, 561}, +/*h(1825)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1825, 558}, +/*h(12771)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12771, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3873)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3873, 558}, +/*h(14819)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14819, 751}, +/*h(10638)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10638, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((15*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1903_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10102)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64*/ {10102, 2179}, +/*h(5921)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5921, 558}, +/*h(12686)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12686, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_566_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14734)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14734, 561}, +/*h(12150)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64*/ {12150, 2178}, +/*h(7969)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7969, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 23) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4248_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14198)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64*/ {14198, 2175}, +/*h(10017)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10017, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2911_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16246)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64*/ {16246, 2177}, +/*h(12065)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12065, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14113)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3909_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {265, 558}, +/*h(13795)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {13795, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {2313, 558}, +/*h(15843)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {15843, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8457)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12553)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1289, 558}, +/*h(12235)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12235, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1904_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14283, 751}, +/*h(3337)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3337, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_567_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5385)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5385, 558}, +/*h(16331)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16331, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7433)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2912_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15625)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12747)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12747, 751}, +/*h(1801)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1801, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4079_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3849)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3849, 558}, +/*h(14795)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14795, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5897)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7945)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9993)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12041)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14089)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1809)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1809, 558}, +/*h(4393)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {4393, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8086)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8086, 561}, +/*h(1321)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1321, 558}, +/*h(12267)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12267, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3369, 558}, +/*h(14315)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14315, 751}, +/*h(10134)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10134, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12182)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12182, 561}, +/*h(5417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5417, 558}, +/*h(16363)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16363, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14230)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14230, 561}, +/*h(7465)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7465, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1793_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16278)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16278, 561}, +/*h(9513)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {9513, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11561)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13609)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15657)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1833)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1833, 558}, +/*h(15363)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15363, 741}, +/*h(8598)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8598, 561}, +/*h(12779)=3 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12779, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 23) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2960_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14827, 751}, +/*h(10646)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10646, 561}, +/*h(3881)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3881, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1623_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12694)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12694, 561}, +/*h(5929)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5929, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14742)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14742, 561}, +/*h(7977)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7977, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10025)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12073)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14121)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6417)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10513)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12561)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14609)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12243, 751}, +/*h(1297)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1297, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1624_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3345, 558}, +/*h(14291)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14291, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5393, 558}, +/*h(16339)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16339, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3857)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5905)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7953)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10001)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12049)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2511_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4486, 561}, +/*h(305)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {305, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6534, 561}, +/*h(2353)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {2353, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4856_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8582)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8582, 561}, +/*h(4401)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {4401, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3519_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10630)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10630, 561}, +/*h(6449)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {6449, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12678)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12678, 561}, +/*h(8497)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8497, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_845_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14726)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14726, 561}, +/*h(10545)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10545, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14641)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3377)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16371, 751}, +/*h(5425)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5425, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11569)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13617)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15665)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4018_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6022)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6022, 561}, +/*h(1841)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1841, 558}, +/*h(12787)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12787, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((15*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2681_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14835)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14835, 751}, +/*h(8070)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8070, 561}, +/*h(3889)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3889, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10118, 561}, +/*h(5937)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5937, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12166)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12166, 561}, +/*h(7985)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7985, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14214)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14214, 561}, +/*h(10033)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10033, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1943_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8450, 558}, +/*h(12631)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {12631, 2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_606_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10498, 558}, +/*h(14679)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {14679, 2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2282_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {15618, 558}, +/*h(491)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {491, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3779_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1794, 558}, +/*h(5975)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {5975, 2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5890, 558}, +/*h(10071)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64*/ {10071, 2179} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4787_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7938, 558}, +/*h(12119)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64*/ {12119, 2178} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3450_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {9986, 558}, +/*h(7402)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7402, 743}, +/*h(14167)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64*/ {14167, 2175} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9450, 743}, +/*h(12034)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12034, 558}, +/*h(16215)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64*/ {16215, 2177} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14082, 558}, +/*h(11498)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {11498, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4458_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16130, 558}, +/*h(13546)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {13546, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {4386, 558}, +/*h(205)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {205, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {6434, 558}, +/*h(2253)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2253, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_824_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8482, 558}, +/*h(4301)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4301, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10530, 558}, +/*h(6349)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6349, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12578, 558}, +/*h(8397)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8397, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2660_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6007)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {6007, 2069}, +/*h(1826)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1826, 558}, +/*h(8591)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8591, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1323_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3874, 558}, +/*h(10639)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10639, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5005_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5922, 558}, +/*h(10103)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64*/ {10103, 2179}, +/*h(12687)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12687, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3668_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7970, 558}, +/*h(12151)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64*/ {12151, 2178} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10018, 558}, +/*h(14199)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64*/ {14199, 2175} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_994_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12066, 558}, +/*h(16247)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64*/ {16247, 2177} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_995_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1802)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3850)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5898)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7946)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9994)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12042)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14090)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_873_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3218_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {4394, 558}, +/*h(213)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {213, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1881_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {6442, 558}, +/*h(2261)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2261, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8490, 558}, +/*h(4309)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4309, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4226_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10538, 558}, +/*h(6357)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6357, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2889_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12586, 558}, +/*h(8405)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8405, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14634, 558}, +/*h(10453)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10453, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1322, 558}, +/*h(8087)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8087, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3887_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3370, 558}, +/*h(10135)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10135, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2550_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5418, 558}, +/*h(12183)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12183, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7466, 558}, +/*h(14231)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14231, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4895_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {9514, 558}, +/*h(16279)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16279, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13610)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15658)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1834)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1834, 558}, +/*h(8599)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8599, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1043_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3882)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3882, 558}, +/*h(10647)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10647, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5930)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5930, 558}, +/*h(1749)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1749, 2006}, +/*h(12695)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12695, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3388_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14743)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14743, 561}, +/*h(7978)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7978, 558}, +/*h(3797)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3797, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2051_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10026)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10026, 558}, +/*h(5845)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5845, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_714_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12074)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12074, 558}, +/*h(7893)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7893, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14122, 558}, +/*h(9941)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9941, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3059_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16170, 558}, +/*h(11989)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11989, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {274, 558}, +/*h(15401)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15401, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4058_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3728_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14610)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {306, 558}, +/*h(15433)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15433, 749}, +/*h(4487)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4487, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {2354, 558}, +/*h(6535)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6535, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2939_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {4402, 558}, +/*h(8583)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8583, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1602_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {6450, 558}, +/*h(10631)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10631, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8498, 558}, +/*h(12679)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12679, 561}, +/*h(1733)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1733, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3947_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3781)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3781, 2007}, +/*h(14727)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14727, 561}, +/*h(10546)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10546, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12594, 558}, +/*h(5829)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5829, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1273_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14642, 558}, +/*h(7877)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7877, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_933_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4037_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2307)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3708_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1601, 749}, +/*h(12547)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12547, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1034_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14595)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14595, 558}, +/*h(1065)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1065, 741}, +/*h(3649)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3649, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4705_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7427)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11523)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1795)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3843, 558}, +/*h(14789)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14789, 2034}, +/*h(1259)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1259, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5891, 558}, +/*h(3307)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3307, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2870_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5355, 743}, +/*h(7939)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7939, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9987)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {9987, 558}, +/*h(7403)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7403, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12035, 558}, +/*h(9451)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9451, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3877_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3137, 749}, +/*h(14083)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14083, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16131, 558}, +/*h(5185)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5185, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(291)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12579)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12579, 558}, +/*h(1633)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1633, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3681, 749}, +/*h(14627)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14627, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12261)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12261, 2027}, +/*h(1315)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1315, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3363)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_913_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5411)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5326, 2008}, +/*h(9507)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {9507, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1920_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7374)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7374, 2009}, +/*h(11555)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {11555, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9422, 2010}, +/*h(13603)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {13603, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11470, 2011}, +/*h(15651)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {15651, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10019)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4096_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1121)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1121, 749}, +/*h(12067)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12067, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14115)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2315)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4363)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6411)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2091_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12555)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12555, 558}, +/*h(1609)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1609, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_754_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3657)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3657, 749}, +/*h(14603)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14603, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4426_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12237)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12237, 2027}, +/*h(1291)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1291, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4097_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(49)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {49, 740}, +/*h(13579)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {13579, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15627)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {15627, 558}, +/*h(2097)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {2097, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1803)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3851)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3851, 558}, +/*h(14797)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14797, 2034} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5899)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7947)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9995)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1097, 749}, +/*h(12043)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12043, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3598_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14091)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14091, 558}, +/*h(3145)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3145, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5193, 749}, +/*h(16139)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16139, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2347)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(214)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {214, 2006}, +/*h(4395)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {4395, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4983_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2262, 2007}, +/*h(6443)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {6443, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3646_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4310)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4310, 2008}, +/*h(8491)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8491, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2309_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6358)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6358, 2009}, +/*h(10539)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10539, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_972_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12587, 558}, +/*h(8406)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8406, 2010}, +/*h(1641)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1641, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3689)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3689, 749}, +/*h(14635)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14635, 558}, +/*h(10454)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10454, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3307_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1323, 558}, +/*h(12269)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12269, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7467)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11563)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13611)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {13611, 558}, +/*h(81)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {81, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3986_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15659)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {15659, 558}, +/*h(2129)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {2129, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1835)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3883)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2808_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1750)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1750, 2006}, +/*h(5931)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5931, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3798)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3798, 2007}, +/*h(7979)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {7979, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10027)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12075)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12075, 558}, +/*h(1129)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1129, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3177, 749}, +/*h(14123)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14123, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1142_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5225, 749}, +/*h(16171)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16171, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {2323, 558}, +/*h(15853)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {15853, 2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8467)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1811_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1617)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1617, 750}, +/*h(12563)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12563, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3665)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3665, 750}, +/*h(14611)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14611, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1299, 558}, +/*h(12245)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12245, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2809_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3347)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3347, 558}, +/*h(14293)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64*/ {14293, 2030} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1472_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16341)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64*/ {16341, 2028}, +/*h(5395)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5395, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7443)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3817_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4984_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14805)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14805, 2034}, +/*h(3859)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3859, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10003)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4655_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12051)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12051, 558}, +/*h(1105)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1105, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3153)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3153, 750}, +/*h(14099)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14099, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1981_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5201)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {5201, 750}, +/*h(16147)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16147, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3696_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15434, 749}, +/*h(307)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {307, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1022_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1734)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1734, 2006}, +/*h(8499)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8499, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2030_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3782)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3782, 2007}, +/*h(10547)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {10547, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5830)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5830, 2008}, +/*h(12595)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12595, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4375_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7878)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7878, 2009}, +/*h(14643)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14643, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3027_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1331, 558}, +/*h(12277)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12277, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1690_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14325)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64*/ {14325, 2030}, +/*h(3379)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {3379, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5427)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {5427, 558}, +/*h(16373)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64*/ {16373, 2028} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4035_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9523)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5939)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7987)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4873_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3536_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1137, 750}, +/*h(12083)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {12083, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2199_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3185)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3185, 750}, +/*h(14131)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14131, 558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16179, 558}, +/*h(5233)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {5233, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(261)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 261; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2309)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2309; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4357)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6405)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1211_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8453)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8453, 559}, +/*h(5869)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5869, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7917)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7917, 2009}, +/*h(10501)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10501, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3556_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12549)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12549, 559}, +/*h(9965)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9965, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2219_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14597)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14597, 559}, +/*h(1067)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1067, 741}, +/*h(12013)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {12013, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_871_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8050, 2068}, +/*h(12231)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12231, 2027}, +/*h(1285)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1285, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10098, 2068}, +/*h(3333)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3333, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12146, 2068}, +/*h(5381)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5381, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1879_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14194, 2068}, +/*h(7429)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7429, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16242, 2068}, +/*h(9477)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9477, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11525)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13573)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13573; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15621)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1797)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3845)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5893)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7941)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9989)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1091)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1091, 749}, +/*h(12037)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12037, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14085)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14085, 559}, +/*h(3139)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3139, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5187)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5187, 749}, +/*h(16133)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16133, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(293)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2341)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4389)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6437)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8485)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10533)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10533; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1635, 749}, +/*h(12581)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12581, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3683)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3683, 749}, +/*h(14629)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14629, 559}, +/*h(1099)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1099, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((7*key % 23) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4771_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8082, 560}, +/*h(1317)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1317, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10130, 560}, +/*h(3365)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3365, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12178, 560}, +/*h(5413)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5413, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_760_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14226, 560}, +/*h(7461)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7461, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4442_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16274, 560}, +/*h(9509)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9509, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11557)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11557; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13605)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15653)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1829)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1293)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1293, 559}, +/*h(3877)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3877, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4273_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5925)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5925, 559}, +/*h(3341)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3341, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2936_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7973)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7973, 559}, +/*h(5389)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5389, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1599_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7437)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7437, 559}, +/*h(10021)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10021, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12069)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12069, 559}, +/*h(9485)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9485, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14117, 559}, +/*h(11533)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11533, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2607_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13581)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {13581, 559}, +/*h(16165)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16165, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(269)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 269; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2317)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2317; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4365)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6413)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8461)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10509)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1611)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1611, 749}, +/*h(12557)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12557, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1939_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3659)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3659, 749}, +/*h(14605)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14605, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {502, 752}, +/*h(15629)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15629, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2767_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5986, 2068}, +/*h(1805)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1805, 559}, +/*h(12751)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64*/ {12751, 2033} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14799)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14799, 2034}, +/*h(8034)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8034, 2068}, +/*h(3853)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3853, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10082, 2068}, +/*h(5901)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5901, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3775_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12130, 2068}, +/*h(7949)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7949, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14178, 2068}, +/*h(9997)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9997, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16226, 2068}, +/*h(12045)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12045, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4783_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14093)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14093, 559}, +/*h(11509)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11509, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3446_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13557)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13557, 2012}, +/*h(16141)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16141, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(301)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 301; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2349)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4397)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6445)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8493)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10541)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2157_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1643)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1643, 749}, +/*h(12589)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12589, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_820_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14637)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14637, 559}, +/*h(3691)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3691, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12271)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12271, 2027}, +/*h(1325)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1325, 559}, +/*h(5506)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5506, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7554, 560}, +/*h(3373)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3373, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1818_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {9602, 560}, +/*h(5421)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5421, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {11650, 560}, +/*h(7469)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7469, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {13698, 560}, +/*h(9517)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9517, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2826_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {15746, 560}, +/*h(11565)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11565, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(83)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {83, 750}, +/*h(13613)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {13613, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {2131, 750}, +/*h(15661)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15661, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1648_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6018, 560}, +/*h(1837)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1837, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8066, 560}, +/*h(3885)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3885, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3993_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10114, 560}, +/*h(5933)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5933, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12162, 560}, +/*h(7981)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7981, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1319_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14210, 560}, +/*h(10029)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10029, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5001_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1131, 749}, +/*h(16258)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16258, 560}, +/*h(12077)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12077, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3664_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3179, 749}, +/*h(14125)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14125, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16173)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16173, 559}, +/*h(5227)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5227, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(277)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 277; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4662_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15855)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {15855, 2029}, +/*h(2325)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {2325, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4373)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6421)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8469)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10517)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2996_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1619, 750}, +/*h(12565)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12565, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1659_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14613)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14613, 559}, +/*h(3667)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3667, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1301)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1301, 559}, +/*h(12247)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12247, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3994_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14295)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64*/ {14295, 2030}, +/*h(3349)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3349, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2657_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5397)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5397, 559}, +/*h(16343)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64*/ {16343, 2028} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7445)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9493)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11541)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13589)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15637)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1813)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1813, 559}, +/*h(12759)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64*/ {12759, 2033}, +/*h(8578)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8578, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10626, 560}, +/*h(14807)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14807, 2034}, +/*h(3861)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3861, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4832_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12674)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12674, 560}, +/*h(5909)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5909, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14722)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14722, 560}, +/*h(7957)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7957, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14186, 2068}, +/*h(10005)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10005, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_821_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1107)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1107, 750}, +/*h(16234)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16234, 2068}, +/*h(12053)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12053, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4503_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3155)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3155, 750}, +/*h(14101)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14101, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16149)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16149, 559}, +/*h(5203)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {5203, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(309)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 309; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2357)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4405)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6453)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8501)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8501; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10549)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1877_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12597)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12597, 559}, +/*h(1651)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1651, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3699, 750}, +/*h(14645)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14645, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12279)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12279, 2027}, +/*h(8098)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8098, 560}, +/*h(1333)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1333, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2875_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3381)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3381, 559}, +/*h(14327)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64*/ {14327, 2030}, +/*h(7562)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7562, 560}, +/*h(10146)=3 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10146, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1538_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(12194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12194, 560}, +/*h(16375)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64*/ {16375, 2028}, +/*h(5429)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5429, 559}, +/*h(9610)=3 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {9610, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14242, 560}, +/*h(11658)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {11658, 560}, +/*h(7477)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7477, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3883_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13706)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {13706, 560}, +/*h(9525)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9525, 559}, +/*h(16290)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16290, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2546_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15754)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {15754, 560}, +/*h(11573)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11573, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13621)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15669)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1368_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8610)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8610, 560}, +/*h(1845)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1845, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10658)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10658, 560}, +/*h(3893)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3893, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12706)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12706, 560}, +/*h(5941)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5941, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2376_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14754)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14754, 560}, +/*h(7989)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7989, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10037)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4721_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1139)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {1139, 750}, +/*h(12085)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12085, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3384_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14133)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14133, 559}, +/*h(3187)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {3187, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2047_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5235)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {5235, 750}, +/*h(16181)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16181, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2310)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1968_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4358)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {4358, 559}, +/*h(1774)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1774, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_631_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3822)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3822, 2007}, +/*h(6406)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {6406, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4313_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8454)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8454, 559}, +/*h(5870)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5870, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2976_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10502, 559}, +/*h(7918)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7918, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3973_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1286)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1286, 559}, +/*h(8051)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8051, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2636_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3334)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3334, 559}, +/*h(10099)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10099, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3644_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9478)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9478, 559}, +/*h(16243)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16243, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11526)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15622)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1798)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3846)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(294)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_849_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12582)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14630)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14630; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1318)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1318, 559}, +/*h(8083)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8083, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3366)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3366, 559}, +/*h(10131)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10131, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1233, 742}, +/*h(12179)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12179, 560}, +/*h(5414)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5414, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7462)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7462, 559}, +/*h(3281)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3281, 742}, +/*h(14227)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14227, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2525_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16275, 560}, +/*h(5329)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5329, 742}, +/*h(9510)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9510, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11558, 559}, +/*h(7377)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {7377, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4870_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13606)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {13606, 559}, +/*h(9425)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {9425, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15654)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15654, 559}, +/*h(11473)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {11473, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1830)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3878)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3878, 559}, +/*h(1294)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1294, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3342, 559}, +/*h(5926)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5926, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1018_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7974)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7974, 559}, +/*h(3793)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3793, 742}, +/*h(14739)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14739, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4700_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10022)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10022, 559}, +/*h(5841)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5841, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3363_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12070, 559}, +/*h(7889)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {7889, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2026_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14118, 559}, +/*h(9937)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {9937, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16166)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16166, 559}, +/*h(11985)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {11985, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(270)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2318)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4366)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6414)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13582)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4372_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15630)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15630, 559}, +/*h(503)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {503, 752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_850_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1806)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1806, 559}, +/*h(5987)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5987, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4532_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3854)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3854, 559}, +/*h(1270)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1270, 2006}, +/*h(8035)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8035, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3318)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3318, 2007}, +/*h(5902)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5902, 559}, +/*h(10083)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10083, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(302)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2350)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8494)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8494, 559}, +/*h(1729)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1729, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1577_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10542, 559}, +/*h(3777)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3777, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12590)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12590, 559}, +/*h(5825)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5825, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3922_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14638)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14638, 559}, +/*h(7873)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7873, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2575_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1326, 559}, +/*h(5507)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5507, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1238_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3374)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3374, 559}, +/*h(7555)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7555, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4920_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5422, 559}, +/*h(9603)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {9603, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3583_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7470, 559}, +/*h(11651)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {11651, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9518, 559}, +/*h(13699)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {13699, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_909_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11566, 559}, +/*h(15747)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {15747, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13614)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15662)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1838)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1838, 559}, +/*h(6019)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6019, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3886)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3886, 559}, +/*h(8067)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8067, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2076_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5934)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5934, 559}, +/*h(10115)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10115, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_739_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7982)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7982, 559}, +/*h(1217)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1217, 743}, +/*h(12163)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12163, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4421_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14211)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14211, 560}, +/*h(10030)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10030, 559}, +/*h(3265)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3265, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3084_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5313, 743}, +/*h(16259)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16259, 560}, +/*h(12078)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12078, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1747_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14126)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14126, 559}, +/*h(7361)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7361, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16174)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16174, 559}, +/*h(9409)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9409, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(278)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4374)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {4374, 559}, +/*h(193)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {193, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {6422, 559}, +/*h(2241)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {2241, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1302)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2077_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3350)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9494)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1748_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_411_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13590)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15638)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_570_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8579)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8579, 560}, +/*h(5995)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5995, 2068}, +/*h(1814)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1814, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8043)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8043, 2068}, +/*h(3862)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3862, 559}, +/*h(10627)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10627, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2915_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5910)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5910, 559}, +/*h(12675)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12675, 560}, +/*h(10091)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10091, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(310)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2358)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2358; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4406)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {4406, 559}, +/*h(225)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {225, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6454)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {6454, 559}, +/*h(2273)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {2273, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2634_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8502, 559}, +/*h(4321)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {4321, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10550, 559}, +/*h(6369)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {6369, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4979_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12598)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12598, 559}, +/*h(8417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {8417, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3642_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14646)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14646, 559}, +/*h(10465)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {10465, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2295_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8099)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8099, 560}, +/*h(5515)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5515, 560}, +/*h(1334)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1334, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_958_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10147, 560}, +/*h(7563)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7563, 560}, +/*h(3382)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3382, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4640_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9611)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {9611, 560}, +/*h(5430)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5430, 559}, +/*h(12195)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12195, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3303_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7478)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7478, 559}, +/*h(14243)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14243, 560}, +/*h(11659)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {11659, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9526)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9526, 559}, +/*h(13707)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {13707, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11574, 559}, +/*h(15755)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {15755, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13622)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15670)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4470_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1846)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1846, 559}, +/*h(8611)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8611, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3894)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3894, 559}, +/*h(10659)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10659, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12707)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12707, 560}, +/*h(5942)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5942, 559}, +/*h(1761)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1761, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1225, 743}, +/*h(3809)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3809, 743}, +/*h(14755)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14755, 560}, +/*h(7990)=3 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7990, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10038)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10038, 559}, +/*h(5857)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5857, 743}, +/*h(3273)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3273, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2804_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12086)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12086, 559}, +/*h(5321)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5321, 743}, +/*h(7905)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7905, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14134)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14134, 559}, +/*h(7369)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7369, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16182)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16182, 559}, +/*h(9417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9417, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(263)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15841)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {15841, 751}, +/*h(2311)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {2311, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2056_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1287)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1287, 559}, +/*h(12233)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12233, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3335)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3335, 559}, +/*h(14281)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14281, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4401_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16329, 751}, +/*h(5383)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5383, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7431)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9479)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9479; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11527)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13575)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15623)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15623; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4231_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1799)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1799, 559}, +/*h(12745)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12745, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2894_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14793, 751}, +/*h(3847)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3847, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(295)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2343)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4391)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6439)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8487)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4959_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10535)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10535, 559}, +/*h(7951)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7951, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3622_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9999)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9999, 559}, +/*h(12583)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12583, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14631)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14631, 559}, +/*h(12047)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12047, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_937_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1319)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1319, 559}, +/*h(12265)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12265, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4619_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14313, 751}, +/*h(3367)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3367, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3282_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5415)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5415, 559}, +/*h(1234)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1234, 742}, +/*h(16361)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16361, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1945_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3282, 742}, +/*h(7463)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7463, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5330, 742}, +/*h(9511)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9511, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {7378, 742}, +/*h(11559)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {11559, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {9426, 742}, +/*h(13607)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {13607, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1616_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {11474, 742}, +/*h(15655)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15655, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15361, 741}, +/*h(1831)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1831, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3879)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1746, 742}, +/*h(5927)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5927, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3794, 742}, +/*h(7975)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7975, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2783_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5842, 742}, +/*h(10023)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10023, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1446_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {7890, 742}, +/*h(12071)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12071, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {9938, 742}, +/*h(14119)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14119, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3791_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {11986, 742}, +/*h(16167)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16167, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(271)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2319)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4367)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6415)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1295)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1295, 559}, +/*h(14825)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14825, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14289, 751}, +/*h(3343)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3343, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5391)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5391, 559}, +/*h(16337)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16337, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7439)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9487)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11535)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13583)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13583; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15631)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15631; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12753)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12753, 751}, +/*h(1807)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1807, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2615_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1271)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1271, 2006}, +/*h(14801)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14801, 751}, +/*h(3855)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3855, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5903)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {5903, 559}, +/*h(3319)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3319, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14095)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16143)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(303)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2351)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6447)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_997_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1730, 743}, +/*h(8495)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8495, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4679_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3778, 743}, +/*h(10543)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10543, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3342_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5826)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5826, 743}, +/*h(12591)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12591, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2005_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7874, 743}, +/*h(14639)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14639, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_658_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12273, 751}, +/*h(1327)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1327, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3375)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3375, 559}, +/*h(5959)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {5959, 2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5423)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9519)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11567)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13615)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15663)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2833_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1839)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {1839, 559}, +/*h(12785)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12785, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1496_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3887)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {3887, 559}, +/*h(14833)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14833, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5935)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1218, 743}, +/*h(7983)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7983, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2504_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3266, 743}, +/*h(10031)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10031, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1167_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5314, 743}, +/*h(12079)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12079, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7362, 743}, +/*h(14127)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14127, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3512_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9410, 743}, +/*h(16175)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16175, 559}, +/*h(13591)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {13591, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(279)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2327)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {194, 743}, +/*h(4375)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {4375, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {2242, 743}, +/*h(6423)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {6423, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1303)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3351)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7447)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9495)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11543)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {11458, 743}, +/*h(15639)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15639, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1815)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3863)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5911)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1046_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(311)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {311, 559}, +/*h(13841)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {13841, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4728_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2359)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {2359, 559}, +/*h(15889)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {15889, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {226, 743}, +/*h(4407)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {4407, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2054_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {2274, 743}, +/*h(6455)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {6455, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {4322, 743}, +/*h(8503)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {8503, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4399_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {6370, 743}, +/*h(10551)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10551, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3062_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {8418, 743}, +/*h(12599)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12599, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {10466, 743}, +/*h(14647)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14647, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1335)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1335; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3383)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3383; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5431)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7479)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7479; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9527)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11575)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13623)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13623; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1057_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15671)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1847)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3895)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5943)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1226, 743}, +/*h(7991)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {7991, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2224_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3274, 743}, +/*h(10039)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {10039, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_887_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5322, 743}, +/*h(12087)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {12087, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7370, 743}, +/*h(14135)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {14135, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9418, 743}, +/*h(16183)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {16183, 559} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4733_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode32*/ {4566, 2024}, +/*h(385)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {385, 560}, +/*h(11331)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11331, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13379, 749}, +/*h(6614)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {6614, 2025}, +/*h(2433)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2433, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2059_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4481, 560}, +/*h(15427)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15427, 749}, +/*h(8662)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8662, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_722_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10710)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10710, 2027}, +/*h(6529)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6529, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4404_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12758)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32*/ {12758, 2032}, +/*h(8577)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8577, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3067_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14806)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14806, 2034}, +/*h(10625)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10625, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12673)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14721)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2727_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10222)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10222, 2020}, +/*h(3457)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3457, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12270)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12270, 2027}, +/*h(5505)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5505, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7553)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11649)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1221_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6102)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6102, 2026}, +/*h(1921)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1921, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3969)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3566_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10198)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10198, 2020}, +/*h(6017)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6017, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12246)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12246, 2027}, +/*h(8065)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8065, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_892_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14294)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64*/ {14294, 2030}, +/*h(10113)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10113, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1899_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1130, 749}, +/*h(16257)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16257, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(417)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {417, 560}, +/*h(11363)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11363, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2277_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2465, 560}, +/*h(13411)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13411, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_940_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15459, 749}, +/*h(4513)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4513, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6561)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8609)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10657)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12705)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14753)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2946_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12387, 749}, +/*h(1441)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1441, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1609_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3489, 560}, +/*h(14435)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14435, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9718)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9718, 2020}, +/*h(5537)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5537, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3953_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4961_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13729)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15777)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6134)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6134, 2026}, +/*h(1953)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1953, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4001)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10230)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10230, 2020}, +/*h(6049)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6049, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12278)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12278, 2027}, +/*h(8097)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8097, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4792_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64*/ {14326, 2030}, +/*h(10145)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10145, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16374)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64*/ {16374, 2028}, +/*h(12193)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12193, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4453_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {393, 560}, +/*h(11339)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11339, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3116_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2441, 560}, +/*h(13387)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13387, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1779_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15435, 749}, +/*h(4489)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4489, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1450_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12681, 560}, +/*h(1735)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1735, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3783)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3783, 2007}, +/*h(14729)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14729, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12363)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12363, 749}, +/*h(1417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1417, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2448_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3465, 560}, +/*h(14411)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14411, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5513)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7561)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9609)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11657)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13705)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15753)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_941_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8694)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8694, 2020}, +/*h(1929)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1929, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4623_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10742)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10742, 2027}, +/*h(3977)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3977, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6025)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8073)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10121)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1223)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1223, 2006}, +/*h(12169)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12169, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2957_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14217)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14217, 560}, +/*h(3271)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3271, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1620_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5319)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5319, 2008}, +/*h(16265)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16265, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6569)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8617)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10665)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1767)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1767, 2006}, +/*h(12713)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12713, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3815)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3815, 2007}, +/*h(14761)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14761, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2666_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1449, 560}, +/*h(12395)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12395, 749}, +/*h(8214)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {8214, 739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1329_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3497, 560}, +/*h(14443)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14443, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5545)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9641)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11689)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4682_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13737)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {13737, 560}, +/*h(207)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {207, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3345_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15785)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {15785, 560}, +/*h(2255)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2255, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1961)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4009)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6057)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8105)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10153)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12201)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12201, 560}, +/*h(1255)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1255, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1838_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3303)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3303, 2007}, +/*h(14249)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14249, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5351)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5351, 2008}, +/*h(16297)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16297, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {401, 560}, +/*h(13931)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13931, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2449, 560}, +/*h(15979)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15979, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6545)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10641)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1743)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1743, 2006}, +/*h(12689)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12689, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4852_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3791)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3791, 2007}, +/*h(14737)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14737, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1425, 560}, +/*h(12371)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {12371, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3473, 560}, +/*h(14419)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {14419, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_831_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9702)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9702, 2020}, +/*h(5521)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5521, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4513_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11750)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11750, 2027}, +/*h(7569)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7569, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9617)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1839_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15846)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {15846, 2029}, +/*h(11665)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {11665, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13713)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15761)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1937)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1937, 560}, +/*h(15467)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15467, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3985)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6033)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4014_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12177, 560}, +/*h(1231)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1231, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2677_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3279)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3279, 2007}, +/*h(14225)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14225, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1340_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5327)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5327, 2008}, +/*h(16273)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16273, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3055_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {11379, 750}, +/*h(433)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {433, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1718_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2481, 560}, +/*h(13427)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {13427, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_381_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4529, 560}, +/*h(15475)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {15475, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8625)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10673)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12721)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3734_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1239)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1239, 2006}, +/*h(14769)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14769, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1457)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1457, 560}, +/*h(12403)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {12403, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1049_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {14451, 750}, +/*h(3505)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3505, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5553)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2057_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9649)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4017)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6065)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8113)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2895_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1263)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1263, 2006}, +/*h(12209)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12209, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1558_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3311)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3311, 2007}, +/*h(14257)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14257, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16305, 560}, +/*h(5359)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5359, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {386, 560}, +/*h(4567)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix mode64 eamode64*/ {4567, 2023} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {2434, 560}, +/*h(6615)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {6615, 2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4482, 560}, +/*h(8663)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8663, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3824_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6530, 560}, +/*h(10711)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10711, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_810_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3458, 560}, +/*h(10223)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10223, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1922, 560}, +/*h(8687)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8687, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2985_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3970, 560}, +/*h(10735)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10735, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4042_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4514, 560}, +/*h(8695)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8695, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6562, 560}, +/*h(10743)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10743, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1028_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1442, 560}, +/*h(8207)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {8207, 739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3490, 560}, +/*h(10255)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64*/ {10255, 2155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5538, 560}, +/*h(1357)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1357, 2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2036_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7586, 560}, +/*h(3405)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3405, 2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3204_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1954, 560}, +/*h(6135)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6135, 2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_530_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6050, 560}, +/*h(10231)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10231, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1930)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3978)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6026)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8074)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4522, 560}, +/*h(341)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {341, 2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11690)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15786)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1962)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4010)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6058)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10154)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12690)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3933_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5522, 560}, +/*h(9703)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9703, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7570, 560}, +/*h(11751)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11751, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4941_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {11666, 560}, +/*h(15847)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {15847, 2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {434, 560}, +/*h(15561)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {15561, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10674)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12722)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1816_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14770)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1907_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6531, 560}, +/*h(3947)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3947, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1411)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3459, 560}, +/*h(14405)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14405, 2107} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2467)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6563)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1443)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1358)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1358, 2183}, +/*h(5539)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {5539, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3406)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3406, 2182}, +/*h(7587)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {7587, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11683)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4969_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1419, 560}, +/*h(4003)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4003, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3632_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6051)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {6051, 560}, +/*h(3467)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3467, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1965_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5345, 743}, +/*h(16291)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16291, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(395)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2443)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2635_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1737)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1737, 743}, +/*h(12683)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12683, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1298_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3785)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3785, 743}, +/*h(14731)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14731, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1931)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3979)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6027)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8075)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8075; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10123)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12171)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14219)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(427)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1845_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {342, 2184}, +/*h(4523)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {4523, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1516_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1769)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1769, 743}, +/*h(12715)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12715, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14763, 560}, +/*h(3817)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3817, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7595)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9643)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11691)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_848_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {209, 742}, +/*h(13739)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {13739, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4530_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {2257, 742}, +/*h(15787)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {15787, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1963)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4011)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6059)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8107)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10155)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1257, 743}, +/*h(12203)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12203, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3023_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3305, 743}, +/*h(14251)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14251, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16299, 560}, +/*h(5353)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5353, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8595)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10643)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2355_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1745, 742}, +/*h(12691)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12691, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1427)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14421)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14421, 2107}, +/*h(3475)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3475, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5523)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13715)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1939)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3987)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6579)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8627)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10675)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12723)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12723, 560}, +/*h(1777)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1777, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4918_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3825)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3825, 742}, +/*h(14771)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14771, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3571_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12405)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64*/ {12405, 2186}, +/*h(1459)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1459, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2234_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {3507, 560}, +/*h(14453)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64*/ {14453, 2185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5555)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7603)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9651)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13747)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15795)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4019)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6067)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6067; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1735_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1350)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1350, 2183}, +/*h(8115)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {8115, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3398, 2182}, +/*h(10163)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {10163, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4080_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1265, 742}, +/*h(12211)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12211, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2743_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {14259, 560}, +/*h(3313)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3313, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5361, 742}, +/*h(16307)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {16307, 560} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(389)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2437)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4485)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3091_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6533)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6533; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8581)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8581; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10629)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10629; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4099_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1731, 743}, +/*h(12677)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12677, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3779, 743}, +/*h(14725)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14725, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8178, 751}, +/*h(1413)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1413, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14407)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14407, 2107}, +/*h(10226)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10226, 751}, +/*h(3461)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3461, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3760_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12274, 751}, +/*h(5509)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5509, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14322, 751}, +/*h(7557)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7557, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1086_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16370, 751}, +/*h(9605)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {9605, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11653)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13701)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15749)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3590_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8690)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8690, 751}, +/*h(1925)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1925, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2253_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10738, 751}, +/*h(3973)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3973, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_916_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12786)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12786, 751}, +/*h(6021)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6021, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4598_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14834)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14834, 751}, +/*h(8069)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8069, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1924_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12165)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12165, 561}, +/*h(1219)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1219, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3267, 743}, +/*h(14213)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14213, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4269_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5315)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5315, 743}, +/*h(16261)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16261, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(421)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2469)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4517)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6565)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6565; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8613)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8613, 561}, +/*h(6029)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6029, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10661)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10661, 561}, +/*h(8077)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8077, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2981_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10125)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10125, 561}, +/*h(12709)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12709, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1644_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12173)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12173, 561}, +/*h(14757)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14757, 561}, +/*h(1227)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1227, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {8210, 740}, +/*h(1445)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1445, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3978_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {10258, 740}, +/*h(3493)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3493, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2641_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {12306, 740}, +/*h(5541)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5541, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1304_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {14354, 740}, +/*h(7589)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7589, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9637)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11685)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13733)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15781)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1957)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4005)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4816_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6053)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8101)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10149)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_805_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1251)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1251, 743}, +/*h(12197)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12197, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3299, 743}, +/*h(14245)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14245, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16293)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16293, 561}, +/*h(5347)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5347, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1804_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4578, 751}, +/*h(397)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {397, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6626, 751}, +/*h(2445)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2445, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8674)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8674, 751}, +/*h(4493)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4493, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2812_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10722)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10722, 751}, +/*h(6541)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6541, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12770)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12770, 751}, +/*h(8589)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8589, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14818)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14818, 751}, +/*h(10637)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10637, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12685)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1421)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4817_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14415)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14415, 2107}, +/*h(3469)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3469, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5517)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7565)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7565; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9613)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9613; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11661)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13709)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15757)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6114, 751}, +/*h(1933)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1933, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8162, 751}, +/*h(3981)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3981, 561}, +/*h(1397)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1397, 2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3275, 743}, +/*h(14221)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14221, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3989_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16269)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16269, 561}, +/*h(5323)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5323, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_685_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(429)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2477)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2477; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4525)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6573)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6573; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8621)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10669)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2701_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12717)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12717, 561}, +/*h(1771)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1771, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3819)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3819, 743}, +/*h(14765)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14765, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4037)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {4037, 753}, +/*h(1453)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1453, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3698_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3501)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3501, 561}, +/*h(6085)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6085, 2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5549)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1024_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10181)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10181, 2020}, +/*h(7597)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7597, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4706_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9645)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {9645, 561}, +/*h(12229)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12229, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11693)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2032_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13741)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15789)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {6146, 741}, +/*h(1965)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1965, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_855_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8194, 741}, +/*h(4013)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4013, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4537_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10242, 741}, +/*h(6061)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6061, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12290, 741}, +/*h(8109)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8109, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1863_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14338, 741}, +/*h(10157)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10157, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12205)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12205; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14253)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2871_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16301)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16301, 561}, +/*h(13717)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {13717, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1524_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7170, 741}, +/*h(405)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {405, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9218, 741}, +/*h(2453)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2453, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3869_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11266, 741}, +/*h(4501)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4501, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2532_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13314, 741}, +/*h(6549)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6549, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15362, 741}, +/*h(8597)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8597, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10645)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12693)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12693, 561}, +/*h(1747)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1747, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3795)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3795, 742}, +/*h(14741)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14741, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_856_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5610)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {5610, 751}, +/*h(1429)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1429, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4538_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7658)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {7658, 751}, +/*h(3477)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3477, 561}, +/*h(14423)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14423, 2107} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3201_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9706)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {9706, 751}, +/*h(5525)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5525, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1864_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11754)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {11754, 751}, +/*h(7573)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7573, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13802)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {13802, 751}, +/*h(9621)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {9621, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15850)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {15850, 751}, +/*h(11669)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {11669, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15765)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3031_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6122, 751}, +/*h(1941)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1941, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8170, 751}, +/*h(3989)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3989, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10218, 751}, +/*h(6037)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6037, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4039_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12266, 751}, +/*h(8085)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8085, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2702_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14314, 751}, +/*h(10133)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10133, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1365_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16362, 751}, +/*h(12181)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12181, 561}, +/*h(1235)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1235, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14229)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14229, 561}, +/*h(3283)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3283, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5331, 742}, +/*h(16277)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16277, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7202, 741}, +/*h(437)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {437, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4087_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9250, 741}, +/*h(2485)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2485, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11298, 741}, +/*h(4533)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4533, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13346, 741}, +/*h(6581)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6581, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15394, 741}, +/*h(8629)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8629, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3758_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10677)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2421_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1779, 742}, +/*h(12725)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12725, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1084_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3827, 742}, +/*h(14773)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14773, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4756_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5642, 741}, +/*h(1461)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1461, 561}, +/*h(12407)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64*/ {12407, 2186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3419_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14455)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64*/ {14455, 2185}, +/*h(3509)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3509, 561}, +/*h(7690)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7690, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2082_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9738, 741}, +/*h(5557)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5557, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_745_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11786)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11786, 741}, +/*h(7605)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7605, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4427_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13834)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13834, 741}, +/*h(9653)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {9653, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3090_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15882)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15882, 741}, +/*h(11701)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {11701, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13749)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15797)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1912_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1973)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4021)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6069)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10165)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12213)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12213, 561}, +/*h(1267)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {1267, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3928_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3315)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {3315, 742}, +/*h(14261)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14261, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2591_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5363)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {5363, 742}, +/*h(16309)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16309, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1414)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1414, 561}, +/*h(8179)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8179, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3180_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3462)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3462, 561}, +/*h(10227)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10227, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1843_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5510)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5510, 561}, +/*h(12275)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12275, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7558, 561}, +/*h(14323)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14323, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9606)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11654)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13702)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15750)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1926)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1926, 561}, +/*h(8691)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8691, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3974)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3974, 561}, +/*h(10739)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10739, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4518, 561}, +/*h(1934)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1934, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6566, 561}, +/*h(3982)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3982, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3738_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6030)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6030, 561}, +/*h(8614)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8614, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2401_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10662)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10662, 561}, +/*h(8078)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8078, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1064_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12710)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12710, 561}, +/*h(10126)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10126, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14758)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1446, 561}, +/*h(8211)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {8211, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3494)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3494, 561}, +/*h(10259)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {10259, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_724_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5542, 561}, +/*h(12307)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {12307, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7590)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7590, 561}, +/*h(14355)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {14355, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9638)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11686)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13734)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4077_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15782)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1958)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4006)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2899_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6054)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6054, 561}, +/*h(1873)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1873, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8102)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8102, 561}, +/*h(3921)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3921, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10150)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10150, 561}, +/*h(5969)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5969, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3907_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12198)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12198, 561}, +/*h(8017)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8017, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2570_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14246)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14246, 561}, +/*h(10065)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10065, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1233_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16294)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16294, 561}, +/*h(12113)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12113, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4906_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {398, 561}, +/*h(4579)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4579, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2446, 561}, +/*h(6627)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6627, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4494)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4494, 561}, +/*h(8675)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8675, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_895_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6542, 561}, +/*h(10723)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10723, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7566; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9614)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11662)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13710)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15758)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12174)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14222)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16270)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(430)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2478)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4526)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3458_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8622)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8622, 561}, +/*h(1857)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1857, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10670)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10670, 561}, +/*h(3905)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3905, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_784_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12718)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12718, 561}, +/*h(5953)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5953, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14766)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14766, 561}, +/*h(8001)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8001, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4038)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {4038, 753}, +/*h(1454)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1454, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1781_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6086)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6086, 2026}, +/*h(3502)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3502, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7598)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9646)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11694)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13742)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15790)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1966)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1966, 561}, +/*h(6147)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {6147, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3957_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4014)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4014, 561}, +/*h(8195)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8195, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2620_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6062)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6062, 561}, +/*h(3478)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3478, 561}, +/*h(10243)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10243, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8110)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8110, 561}, +/*h(5526)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5526, 561}, +/*h(12291)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12291, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4965_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7574, 561}, +/*h(10158)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10158, 561}, +/*h(14339)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14339, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3628_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12206)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12206, 561}, +/*h(9622)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {9622, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2291_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11670)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {11670, 561}, +/*h(14254)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14254, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16302)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16302, 561}, +/*h(13718)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {13718, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4626_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(406)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {406, 561}, +/*h(7171)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7171, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3289_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2454)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2454, 561}, +/*h(9219)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9219, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4502, 561}, +/*h(11267)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11267, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_615_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10731, 751}, +/*h(6550)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6550, 561}, +/*h(13315)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13315, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3958_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1430)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1430, 561}, +/*h(5611)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {5611, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15766)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1114_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1942)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1942, 561}, +/*h(6123)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6123, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3990)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3990, 561}, +/*h(8171)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8171, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6038)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6038, 561}, +/*h(10219)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10219, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3507_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {438, 561}, +/*h(7203)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7203, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2486, 561}, +/*h(9251)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9251, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_833_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4534, 561}, +/*h(11299)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11299, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4515_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6582)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6582, 561}, +/*h(13347)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13347, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15395)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15395, 741}, +/*h(8630)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8630, 561}, +/*h(1865)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1865, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10678)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10678, 561}, +/*h(3913)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3913, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_504_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12726)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12726, 561}, +/*h(5961)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5961, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4186_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14774)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14774, 561}, +/*h(8009)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8009, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2839_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1462)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1462, 561}, +/*h(5643)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5643, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1502_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3510)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3510, 561}, +/*h(7691)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7691, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5558, 561}, +/*h(9739)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9739, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3847_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7606)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {7606, 561}, +/*h(11787)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11787, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9654)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {9654, 561}, +/*h(13835)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13835, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11702)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {11702, 561}, +/*h(15883)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15883, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13750)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15798)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5014_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1974)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1974, 561}, +/*h(6155)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {6155, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3677_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4022)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4022, 561}, +/*h(8203)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8203, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2340_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6070, 561}, +/*h(10251)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10251, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8118, 561}, +/*h(12299)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12299, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10166)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10166, 561}, +/*h(14347)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14347, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12214)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12214; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16310)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(391)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {391, 561}, +/*h(13921)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13921, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1931_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2439)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2439, 561}, +/*h(15969)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15969, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2600_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1415)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1415, 561}, +/*h(12361)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12361, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1263_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14409, 749}, +/*h(3463)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3463, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5511)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5511; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7559)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9607)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11655)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13703)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15751)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1927)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3975)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6023)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8071)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10119)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10119; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1221)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1221, 2006}, +/*h(12167)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12167, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1772_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3269)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3269, 2007}, +/*h(14215)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14215, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16263)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16263, 561}, +/*h(5317)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5317, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(423)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {423, 561}, +/*h(11369)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11369, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_813_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2471, 561}, +/*h(13417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13417, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4519)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6567)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8615)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10663)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4165_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12711)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12711, 561}, +/*h(1765)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1765, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2828_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3813)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3813, 2007}, +/*h(14759)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14759, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1481_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12393, 749}, +/*h(1447)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1447, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3495)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3495, 561}, +/*h(14441)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14441, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5543)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7591)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9639)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11687)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13735)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15783)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4007)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_982_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1874, 2068}, +/*h(6055)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6055, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4664_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3922, 2068}, +/*h(8103)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8103, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5970, 2068}, +/*h(10151)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10151, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1990_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1253)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1253, 2006}, +/*h(12199)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12199, 561}, +/*h(8018)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8018, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_653_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10066, 2068}, +/*h(14247)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14247, 561}, +/*h(3301)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3301, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4335_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5349)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5349, 2008}, +/*h(16295)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16295, 561}, +/*h(12114)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12114, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2989_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {399, 561}, +/*h(11345)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {11345, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1652_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2447)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2447, 561}, +/*h(13393)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {13393, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {15441, 750}, +/*h(1911)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1911, 2070}, +/*h(4495)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4495, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 23) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3997_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6543)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3667_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3789)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3789, 2007}, +/*h(14735)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14735, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2320_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {12369, 750}, +/*h(1423)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1423, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_983_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3471, 561}, +/*h(14417)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {14417, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5519)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7567)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9615)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11663)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13711)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15759)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1935)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1935, 561}, +/*h(15465)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15465, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3983)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3983; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6031)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8079)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8079; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10127)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10127; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2829_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1229)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1229, 2006}, +/*h(12175)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12175, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14223)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14223, 561}, +/*h(3277)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3277, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5325)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5325, 2008}, +/*h(16271)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16271, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1870_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(431)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {431, 561}, +/*h(11377)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {11377, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {13425, 750}, +/*h(2479)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {2479, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4527)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4527, 561}, +/*h(15473)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {15473, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6575)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1541_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1858, 2068}, +/*h(8623)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8623, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3906, 2068}, +/*h(10671)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10671, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12719)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12719, 561}, +/*h(1773)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1773, 2006}, +/*h(5954)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5954, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(14767)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14767, 561}, +/*h(3821)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3821, 2007}, +/*h(1237)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1237, 2006}, +/*h(8002)=3 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8002, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((8*key % 23) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1455)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1455; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4883_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3503)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3503, 561}, +/*h(14449)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {14449, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5551)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7599)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9647)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11695)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13743)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15791)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1967)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2040_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1431)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {1431, 561}, +/*h(4015)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {4015, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_703_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6063)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {6063, 561}, +/*h(3479)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {3479, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4385_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8111)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8111, 561}, +/*h(5527)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {5527, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3047_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12743)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64*/ {12743, 2033}, +/*h(10159)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10159, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1261)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1261, 2006}, +/*h(12207)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12207, 561}, +/*h(14791)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14791, 2034} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((7*key % 23) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3309)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3309, 2007}, +/*h(14255)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14255, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4055_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5357)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5357, 2008}, +/*h(16303)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16303, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(407)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 407; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2455)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2455; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4503)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4503; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6551)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3048_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7575)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9623)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9623; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11671)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13719)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15767)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1943)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3991)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6039)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(439)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2487)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4535)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6583)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6583; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1866)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1866, 2068}, +/*h(8631)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {8631, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4943_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3914)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3914, 2068}, +/*h(10679)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {10679, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3606_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12727)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12727, 561}, +/*h(5962)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5962, 2068}, +/*h(1781)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1781, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2269_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8010)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8010, 2068}, +/*h(3829)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3829, 2007}, +/*h(14775)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14775, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1463)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3511)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3511; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5559)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7607)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9655)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11703)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13751)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15799)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3097_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1975)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4023)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6071)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8119)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8119; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10167)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10167; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1431_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1269)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1269, 2006}, +/*h(12215)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {12215, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3317)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3317, 2007}, +/*h(14263)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {14263, 561} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16311)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {16311, 561}, +/*h(5365)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5365, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2053)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2061)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {2061, 736}, +/*h(15591)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15591, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3575_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {6250, 749}, +/*h(2069)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {2069, 736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2054)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2062)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2062; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1658_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {2070, 736}, +/*h(6251)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {6251, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2055)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2063)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4759_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2071)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b001] no_refining_prefix*/ {2071, 736}, +/*h(15601)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {15601, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4101)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4109)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4109; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2238_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8298, 749}, +/*h(4117)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {4117, 737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4102)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4110)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4110; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_321_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {4118, 737}, +/*h(8299)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8299, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4103)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4111)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4111; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4119)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b010] no_refining_prefix*/ {737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4119; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6149)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6157)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6157; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_901_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10346, 749}, +/*h(6165)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {6165, 738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6150)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6158)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6158; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6166)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {6166, 738}, +/*h(10347)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10347, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6151)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6159)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6159; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2085_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1986, 751}, +/*h(6167)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b011] no_refining_prefix*/ {6167, 738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8197)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8205)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8205; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4583_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12394, 749}, +/*h(8213)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {8213, 739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8198)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8206)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8199)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_748_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4034, 751}, +/*h(8215)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b100] no_refining_prefix*/ {8215, 739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 17; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2065)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4113)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4558_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1359)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1359, 2183}, +/*h(12305)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {12305, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3221_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3407)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3407, 2182}, +/*h(14353)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {14353, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1041)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1041, 740}, +/*h(11987)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {11987, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5673)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5673, 741}, +/*h(3089)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3089, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4218_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7721)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7721, 741}, +/*h(5137)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {5137, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2881_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7185)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {7185, 740}, +/*h(9769)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9769, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1544_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11817)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11817, 741}, +/*h(9233)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {9233, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {11281, 740}, +/*h(13865)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13865, 741}, +/*h(335)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {335, 2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3889_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {13329, 740}, +/*h(15913)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15913, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15377)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4049_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1553)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1553, 740}, +/*h(12499)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {12499, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2712_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {14547, 742}, +/*h(3601)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3601, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5649)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1391)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1391, 2183}, +/*h(12337)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {12337, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14385)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {14385, 740}, +/*h(3439)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3439, 2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1073)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1073, 740}, +/*h(12019)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {12019, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14067)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {14067, 742}, +/*h(3121)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3121, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {5169, 740}, +/*h(16115)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {16115, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7217)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1879)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1879, 2070}, +/*h(15409)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {15409, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2930_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {12531, 742}, +/*h(1585)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1585, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3633, 740}, +/*h(14579)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {14579, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7729)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9777)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11825)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13873)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15921)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(18)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 18; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2970_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {4114, 740}, +/*h(8295)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64*/ {8295, 2189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4975_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3626, 741}, +/*h(1042)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1042, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3638_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3090)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3090, 740}, +/*h(5674)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5674, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7722)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7722, 741}, +/*h(5138)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {5138, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(50)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 50; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2859_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {10290, 740}, +/*h(3525)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3525, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3857_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1074)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1074, 740}, +/*h(16201)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16201, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3528_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {9266, 740}, +/*h(2501)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2501, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {11314, 740}, +/*h(4549)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16*/ {4549, 2022} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {13362, 740}, +/*h(6597)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {6597, 2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1013_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11826)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(19)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 19; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2067)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2067; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4115)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3058_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1043)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1043, 740}, +/*h(14573)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14573, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3091)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_384_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5139)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {5139, 740}, +/*h(16085)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16085, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7187)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9235)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12501)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12501, 2012}, +/*h(1555)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1555, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3897_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3603)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3603, 740}, +/*h(14549)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14549, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5651)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9747)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3567_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14379, 741}, +/*h(11795)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {11795, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_893_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(51)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 51; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2099)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4953_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6195)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_942_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3526)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3526, 753}, +/*h(10291)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {10291, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1940_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12021)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {12021, 2011}, +/*h(1075)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1075, 740}, +/*h(16202)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16202, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3123)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3123, 740}, +/*h(14069)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14069, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4284_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7755)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7755, 749}, +/*h(5171)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {5171, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2947_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9803)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9803, 749}, +/*h(7219)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {7219, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {9267, 740}, +/*h(11851)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11851, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13899)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13899, 749}, +/*h(11315)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {11315, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3955_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15947)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15947, 749}, +/*h(13363)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {13363, 740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15411)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {1587, 740}, +/*h(12533)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12533, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2778_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {3635, 740}, +/*h(14581)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14581, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5683)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] mode64 FORCE64() MODRM()*/ {740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2049)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2772_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14337)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1025)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1025, 741}, +/*h(11971)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {11971, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1096_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14019)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14019, 743}, +/*h(3073)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3073, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4778_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5121)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5121, 741}, +/*h(16067)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {16067, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9217)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4608_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8302)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64*/ {8302, 2189}, +/*h(12483)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12483, 743}, +/*h(1537)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1537, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3585, 741}, +/*h(14531)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14531, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9729)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11777)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13825)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15873)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(33)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 33; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8310)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64*/ {8310, 2188}, +/*h(4129)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {4129, 741}, +/*h(1545)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1545, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2991_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3593, 741}, +/*h(10358)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64*/ {10358, 2187}, +/*h(6177)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {6177, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8225, 741}, +/*h(5641)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5641, 741}, +/*h(12406)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b110] osz_refining_prefix mode64*/ {12406, 2186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10273, 741}, +/*h(7689)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7689, 741}, +/*h(14454)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] osz_refining_prefix mode64*/ {14454, 2185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3999_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12321, 741}, +/*h(9737)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9737, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12003)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12003, 743}, +/*h(1057)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1057, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4996_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3105)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3105, 741}, +/*h(14051)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14051, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3659_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5153)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5153, 741}, +/*h(16099)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {16099, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7201)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9249)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8334)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {8334, 2127}, +/*h(1569)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1569, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10382)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {10382, 2137}, +/*h(3617)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3617, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_815_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12430)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12430, 2139}, +/*h(5665)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5665, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4497_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14478)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14478, 2106}, +/*h(7713)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7713, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9761)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11809)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13857)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15905)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2057)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4105)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6153)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8201)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1156_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7665)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {7665, 751}, +/*h(10249)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10249, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4838_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12297, 741}, +/*h(9713)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {9713, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14345, 741}, +/*h(11761)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {11761, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1033)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1033, 741}, +/*h(14563)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14563, 743}, +/*h(11979)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {11979, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3081, 741}, +/*h(14027)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14027, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5129, 741}, +/*h(16075)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {16075, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(327)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {327, 2184}, +/*h(11273)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11273, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11785)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13833)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15881)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(41)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 41; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2089)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4048_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6185)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1383)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1383, 2183}, +/*h(12329)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12329, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2382_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3431)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3431, 2182}, +/*h(14377)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14377, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5697, 749}, +/*h(3113)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3113, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3379_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7745, 749}, +/*h(5161)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5161, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2042_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_705_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13353)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1577, 741}, +/*h(12523)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12523, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1873_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14571, 743}, +/*h(3625)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3625, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1026)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3074)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2691_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1538, 741}, +/*h(8303)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64*/ {8303, 2189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13826)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(34)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 34; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3748_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8226, 741}, +/*h(4045)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {4045, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3418_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10274, 741}, +/*h(6093)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6093, 2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_744_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14370, 741}, +/*h(10189)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10189, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1058)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5154)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1570, 741}, +/*h(8335)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {8335, 2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3618, 741}, +/*h(10383)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {10383, 2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3917_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5666, 741}, +/*h(12431)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12431, 2139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2580_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7714, 741}, +/*h(3533)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3533, 753}, +/*h(14479)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14479, 2106} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3588_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13858, 741}, +/*h(9677)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9677, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2251_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15906, 741}, +/*h(11725)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11725, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2058)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {4106, 741}, +/*h(1522)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1522, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1913_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3570, 751}, +/*h(6154)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {6154, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8202, 741}, +/*h(5618)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {5618, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4258_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10250, 741}, +/*h(7666)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {7666, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2921_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {9714, 751}, +/*h(12298)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {12298, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1584_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14346, 741}, +/*h(11762)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {11762, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1546, 741}, +/*h(8311)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64*/ {8311, 2188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1074_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3594, 741}, +/*h(10359)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64*/ {10359, 2187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(42)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 42; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2090)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12354, 749}, +/*h(9770)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9770, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4645_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14402, 749}, +/*h(11818)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11818, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13866)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13866, 741}, +/*h(9685)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9685, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15914)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15914, 741}, +/*h(11733)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11733, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2051)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4099)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3618_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11973)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11973, 2011}, +/*h(1027)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1027, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3075)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3075, 741}, +/*h(14021)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14021, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5123)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5123, 741}, +/*h(16069)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16069, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_774_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1539, 741}, +/*h(12485)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12485, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3587, 741}, +/*h(14533)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14533, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7683)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(35)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 35; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2083)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2838_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4046)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {4046, 753}, +/*h(8227)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {8227, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6094)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6094, 2026}, +/*h(10275)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {10275, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3846_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10190)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10190, 2020}, +/*h(14371)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {14371, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2499_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1059)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1059, 741}, +/*h(12005)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {12005, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1162_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3107)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3107, 741}, +/*h(14053)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14053, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16101)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16101, 2013}, +/*h(5155)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5155, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4674_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1571, 741}, +/*h(12517)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12517, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3337_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14565)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14565, 2013}, +/*h(3619)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3619, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_663_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3534, 753}, +/*h(7715)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7715, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1671_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9678)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9678, 2020}, +/*h(13859)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13859, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11726)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11726, 2027}, +/*h(15907)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15907, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2059)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1333_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4107)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {4107, 741}, +/*h(1523)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1523, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1035, 741}, +/*h(11981)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11981, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2001_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3083)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3083, 741}, +/*h(14029)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14029, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_664_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16077)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16077, 2013}, +/*h(5131)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5131, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9227)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_494_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1547, 741}, +/*h(12493)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12493, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14541)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14541, 2013}, +/*h(3595)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3595, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(43)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 43; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2091)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4139)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6187)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8235)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4904_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_882_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14061)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14061, 2012}, +/*h(3115)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3115, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4564_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5163, 741}, +/*h(16109)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16109, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7211)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11307)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4394_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {4163, 749}, +/*h(1579)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {1579, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3057_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3627)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {3627, 741}, +/*h(6211)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {6211, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1720_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8259, 749}, +/*h(1494)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {1494, 752}, +/*h(5675)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {5675, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3542, 753}, +/*h(7723)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {7723, 741}, +/*h(10307)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10307, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4065_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9771)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {9771, 741}, +/*h(12355)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {12355, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2728_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14403, 749}, +/*h(11819)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {11819, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9686)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9686, 2020}, +/*h(13867)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {13867, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11734)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11734, 2027}, +/*h(15915)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM()*/ {15915, 741} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6353)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14545)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_859_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2039)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {2039, 752}, +/*h(15569)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {15569, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14033)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4748_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {241, 742}, +/*h(13771)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {13771, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((6*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {2289, 742}, +/*h(15819)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {15819, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4337)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6385)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8433)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9457)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1077_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(23)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {23, 2120}, +/*h(13553)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {13553, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5873)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7921)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9969)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12017)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14065)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16113)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3961_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3826)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(211)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4307)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8403)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2372_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9963)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9963, 743}, +/*h(7379)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {7379, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12011)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12011, 743}, +/*h(9427)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {9427, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {11475, 742}, +/*h(14059)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14059, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16107)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {16107, 743}, +/*h(13523)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {13523, 742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9939)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16083)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2291)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {2291, 742}, +/*h(15821)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {15821, 2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7411)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13555)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15603)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] mode64 FORCE64() MODRM()*/ {742} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11457)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13505)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15553)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9921)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11969)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14017)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16065)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12513)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14561)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1249)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9953)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12001)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14049)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(201)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2249)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8393)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10441)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11465)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13513)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5833)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6377)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10473)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12521)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14569)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9449)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11497)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13545)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {13545, 743}, +/*h(15)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {15, 2120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {466, 751}, +/*h(15593)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {15593, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5865)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7913)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9961)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12009)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14057)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16105)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12482, 743}, +/*h(8301)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64*/ {8301, 2189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11970)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3013_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4070_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {14562, 743}, +/*h(11978)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {11978, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5858, 743}, +/*h(12623)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {12623, 2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7906, 743}, +/*h(14671)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {14671, 2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2893_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14026)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16074)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {15594, 743}, +/*h(467)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {467, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1770)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3818)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5866)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7914)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9962)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2952_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12010)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14058)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(195)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4291)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6339)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8387)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10435)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7363)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9411)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2603_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2025)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2025, 751}, +/*h(15555)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {15555, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3819_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {4323, 743}, +/*h(1739)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {1739, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2482_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {6371, 743}, +/*h(3787)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {3787, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5835)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {5835, 743}, +/*h(8419)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {8419, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10467)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {10467, 743}, +/*h(7883)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {7883, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {12515, 743}, +/*h(9931)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {9931, 743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7395)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9443)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5859)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(203)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2251)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4299)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6347)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8395)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10443)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4997_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11467)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15563)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6379)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8427)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15595)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5867)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7915)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM()*/ {743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(70)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode32*/ {744} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 70; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(69)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix not64 eamode16*/ {745} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 69; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(87)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode64*/ {746} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 87; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(86)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b000] no_refining_prefix mode64 eamode32*/ {747} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 86; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2133)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2127)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2127; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2135)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b001] no_refining_prefix*/ {748} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(65)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 65; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2113)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {8342, 2127}, +/*h(4161)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {4161, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1872_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {10390, 2137}, +/*h(6209)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {6209, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12438, 2139}, +/*h(8257)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8257, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14486, 2106}, +/*h(10305)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10305, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12353)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1089)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13377)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15425)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11841)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13889)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15937)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(97)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 97; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10337)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12385)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14433)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9934)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9934, 2010}, +/*h(3169)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3169, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1421_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11982)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11982, 2011}, +/*h(5217)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5217, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14030)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14030, 2012}, +/*h(7265)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7265, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3766_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16078)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16078, 2013}, +/*h(9313)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9313, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11361)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13409)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15457)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5729)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7777)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9825)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11873)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(73)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 73; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2121)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6217)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8265)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10313)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9289)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11337)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13385)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5705)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7753)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9801)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11849)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13897)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15945)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(105)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2153)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4201)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6249)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10345)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12502, 2012}, +/*h(5737)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5737, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1980_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14550, 2013}, +/*h(7785)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7785, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9833)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11881)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13929)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15977)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(66)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 66; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1292_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {4162, 749}, +/*h(8343)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {8343, 2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {6210, 749}, +/*h(10391)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {10391, 2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1493)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {1493, 752}, +/*h(12439)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12439, 2139}, +/*h(8258)=2 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8258, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((15*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10306, 749}, +/*h(3541)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3541, 753}, +/*h(14487)=2 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14487, 2106} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1090)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2968_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9282, 749}, +/*h(2517)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2517, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13378, 749}, +/*h(6613)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {6613, 2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3976_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15426, 749}, +/*h(8661)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8661, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7746, 749}, +/*h(3565)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3565, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2469_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13890, 749}, +/*h(9709)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9709, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15938, 749}, +/*h(11757)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11757, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(98)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 98; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8290, 749}, +/*h(1525)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {1525, 752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10338, 749}, +/*h(3573)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3573, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14434)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1122, 749}, +/*h(7887)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7887, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3170, 749}, +/*h(9935)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9935, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4523_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5218, 749}, +/*h(11983)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {11983, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3186_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7266, 749}, +/*h(14031)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {14031, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9314, 749}, +/*h(16079)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16079, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7778, 749}, +/*h(5194)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5194, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4025_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7242)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7242, 749}, +/*h(9826)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9826, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11874)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11874, 749}, +/*h(9290)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9290, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1351_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13922)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13922, 749}, +/*h(11338)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {11338, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13386)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13386, 749}, +/*h(15970)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15970, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(74)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 74; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2122)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4170)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6218)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8266)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10314)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12362)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14410)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3018_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1098, 749}, +/*h(16225)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16225, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1610)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3658)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5706)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7754)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9802)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11850)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13898)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15946)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2154)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {4202, 749}, +/*h(21)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {21, 2120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {14442, 749}, +/*h(10261)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64*/ {10261, 2156} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1570_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15466)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4074_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {1642, 749}, +/*h(8407)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8407, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2737_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3690)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3690, 749}, +/*h(10455)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10455, 2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1400_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5738, 749}, +/*h(12503)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12503, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7786)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7786, 749}, +/*h(14551)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14551, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9834)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11882)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1071_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13930)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15978)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(67)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 67; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2115)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2388_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {470, 752}, +/*h(7235)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7235, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1051_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2518, 753}, +/*h(9283)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9283, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1603)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3651)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4563_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3566, 753}, +/*h(7747)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7747, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9795)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9710)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9710, 2020}, +/*h(13891)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {13891, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4234_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11758)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {11758, 2027}, +/*h(15939)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {15939, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(99)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 99; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4195)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6243)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1526)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {1526, 752}, +/*h(8291)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {8291, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3574)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3574, 753}, +/*h(10339)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {10339, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1123)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3943_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3171)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5219)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9315)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4782_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {3147, 749}, +/*h(5731)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5731, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3445_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7779, 749}, +/*h(5195)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {5195, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {9827, 749}, +/*h(7243)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {7243, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(75)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 75; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2123)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4171)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6219)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8267)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10315)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9291)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5707)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(107)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2155)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2995_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(22)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {22, 2120}, +/*h(4203)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {4203, 749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11371)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13419)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5739)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7787)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9835)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11883)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM()*/ {749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7249)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9297)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5713)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7761)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9809)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11857)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3827_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13905)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15953)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4294)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4294, 2008}, +/*h(113)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {113, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2868_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6342, 2009}, +/*h(2161)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {2161, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {8390, 2010}, +/*h(4209)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {4209, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {10438, 2011}, +/*h(6257)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {6257, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3876_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12486)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {12486, 2012}, +/*h(8305)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {8305, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2539_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {14534, 2013}, +/*h(10353)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {10353, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12401)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7281)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9329)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1649)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3037_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9841)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4045_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11889)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2708_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13937)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15985)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(82)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 82; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3077_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12370)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14418)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3154)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5202)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7250)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2409_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9298)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {9298, 750}, +/*h(2533)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2533, 753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11346)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13394)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15442)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {15442, 750}, +/*h(8677)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8677, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4913_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(114)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {114, 750}, +/*h(4295)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4295, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_951_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {2162, 750}, +/*h(6343)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6343, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12402)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {9330, 750}, +/*h(13511)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13511, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4972_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11378)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {11378, 750}, +/*h(15559)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15559, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13426)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15986)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4179)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6227)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8275)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4842_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {3558, 753}, +/*h(10323)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {10323, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7251)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2534)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2534, 753}, +/*h(9299)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {9299, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11347)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13395)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8678)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8678, 2020}, +/*h(15443)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {15443, 750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5715)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11859)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(115)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2163)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4211)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6259)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8307)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10355)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7283)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9331)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5747)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7795)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9843)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3893_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13939)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15987)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 FORCE64() MODRM()*/ {750} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6593)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8641)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10689)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12737)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14785)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5569)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7617)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9665)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11713)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3843_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(231)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {231, 2006}, +/*h(13761)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {13761, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15809)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {15809, 751}, +/*h(2279)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2279, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1985)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4033)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64*/ {10262, 2156}, +/*h(6081)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6081, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12225)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14273)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(481)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2529)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6625)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8673)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10721)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12769)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2055_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14817)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14414)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14414, 2107}, +/*h(7649)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {7649, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11745)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13793)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2017)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4065)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6113)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12257)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14305)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16353)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6601)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1886_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8649)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10697)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5577)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7625)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9673)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11721)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13769)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15817)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4041)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1048_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6089)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10185)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10729)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12777)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2773_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5609)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1436_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14422, 2107}, +/*h(7657)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {7657, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9705)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11753)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13801)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15849)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4073)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6121)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8169)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10217)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6609)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8657)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10705)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1489)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3537)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5585)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7633)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9681)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11729)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13777)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15825)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2001)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4049)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6641)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8689)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10737)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5617)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13809)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_827_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15857)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2324_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6214)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {6214, 2105}, +/*h(2033)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2033, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1995_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14406)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {14406, 2107}, +/*h(10225)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10225, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14321)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16369)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(450)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8642, 751}, +/*h(1877)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1877, 2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10690)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2594_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12738)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12738, 751}, +/*h(5973)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {5973, 2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14786)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1474)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3522)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5570)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7618)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9666)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11714)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13762)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6082, 751}, +/*h(10263)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix mode64*/ {10263, 2156} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8130, 751}, +/*h(1365)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1365, 2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1756_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10178)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10178, 751}, +/*h(3413)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3413, 2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12226)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14274)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16322)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15842)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2018)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4066)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10210, 751}, +/*h(3445)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3445, 2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12258)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14306)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16354)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(458)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2506)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4554)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6602)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8650)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10698)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12746)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14794)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1482)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3530)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5578)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7626)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9674)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11722)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13770)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15818)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1994)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4042)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6090)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6090, 751}, +/*h(1909)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1909, 2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1476_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10186)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10186, 751}, +/*h(6005)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {6005, 2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12234)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3821_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14282)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14282, 751}, +/*h(10101)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64*/ {10101, 2179} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2484_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16330)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {16330, 751}, +/*h(12149)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b101] f3_refining_prefix mode64*/ {12149, 2178} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4050, 751}, +/*h(6634)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6634, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3870_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8682, 751}, +/*h(6098)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6098, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10730, 751}, +/*h(8146)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8146, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10194, 751}, +/*h(12778)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12778, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4878_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14826)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14826, 751}, +/*h(12242)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12242, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2026)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4074)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2514)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4562)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6610)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4709_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8658)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8658, 751}, +/*h(1893)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1893, 2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10706)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12754)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12754, 751}, +/*h(5989)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {5989, 2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14802)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1490)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3032_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3538)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5586)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7634)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9682)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11730)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13778)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15826)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14290)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16338)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(498)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2546)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4594)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6642)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13810)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15858)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2034)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2034, 751}, +/*h(6215)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {6215, 2105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4082)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6130)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(451)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6595)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3351_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1878)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1878, 2070}, +/*h(8643)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8643, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10691)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3012_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1475)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1475, 751}, +/*h(12421)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12421, 2139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14469)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14469, 2106}, +/*h(3523)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3523, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11715)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1987)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6083)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1366)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1366, 2183}, +/*h(8131)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8131, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4858_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3414)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3414, 2182}, +/*h(10179)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10179, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16323)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1893_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3555)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5603)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7651)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11747)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2019)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4067)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4067; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6115)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {1398, 2183}, +/*h(8163)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8163, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3739_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {3446, 2182}, +/*h(10211)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10211, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(459)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2507)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4555)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6603)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3071_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8651)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1734_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10699)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2732_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12429)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12429, 2139}, +/*h(1483)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1483, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3531)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3531, 751}, +/*h(14477)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14477, 2106} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5579)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7627)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9675)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11723)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1995)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3570_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4043)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2233_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1910)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1910, 2070}, +/*h(6091)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6091, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8139)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4578_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6006)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {6006, 2069}, +/*h(10187)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {10187, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4587, 751}, +/*h(2003)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2003, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6635, 751}, +/*h(4051)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {4051, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6099)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {6099, 751}, +/*h(8683)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8683, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3563)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7659)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9707)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11755)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13803)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15851)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3788_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15557)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15557, 2013}, +/*h(2027)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2027, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4075)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4075; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2515)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4563)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6611)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2792_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1894)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {1894, 2070}, +/*h(8659)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {8659, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10707)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5990)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {5990, 2069}, +/*h(12755)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {12755, 751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14803)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2452_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1491)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1491, 751}, +/*h(12437)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {12437, 2139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3539)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {3539, 751}, +/*h(14485)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {14485, 2106} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5587)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7635)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9683)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11731)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13779)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15827)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8147)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10195)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(499)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2547)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4595)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6643)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3571)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5619)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7667)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9715)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11763)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13811)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15859)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2035)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4083)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6131)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {751} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(469)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2005)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(501)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 501; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2037)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {2037, 752}, +/*h(15567)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {15567, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2006)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2038)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1495)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2007)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1527)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b000] mode64*/ {752} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3557)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3557; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4069)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2509)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2541)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {2541, 753}, +/*h(16071)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {16071, 2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4077)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4077; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4053)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2549)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4085)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4085; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2510)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4078)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4078; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4054)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4952_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4086)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4086; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4039)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3559)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4071)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_921_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4047)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4047; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4079)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4079; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3543)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4055)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3035_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2551)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3575)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4087)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {753} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4087; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_996_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(133)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_716_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(141)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 141; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(149)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(134)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(150)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(135)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(143)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(151)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b000] no_refining_prefix*/ {1910} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2181)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2181; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2189)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2197)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2182)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2190)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2198)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2183)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2191)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2199)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b001] no_refining_prefix*/ {1911} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(197)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(229)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1741)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(237)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 237; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(245)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(198)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1222)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(230)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1254)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1254, 2006}, +/*h(8019)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8019, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1766)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(206)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_912_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1230)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1742)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(238)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1238)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1238, 2006}, +/*h(8003)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8003, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(246)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1782)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1782, 2006}, +/*h(5963)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5963, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4962_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(199)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(239)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1775)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(215)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 215; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_890_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4335)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {4335, 2008}, +/*h(1751)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {1751, 2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(247)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1783)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b000]*/ {2006} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2245)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2277)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2277; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1042_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2285)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2285; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10050)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10050, 2068}, +/*h(3285)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3285, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2293)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2246)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3270)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2278)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3302)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3302, 2007}, +/*h(10067)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10067, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3814)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2254)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3278)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3790)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2286)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3310)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3286)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3286, 2007}, +/*h(10051)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10051, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2294)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3830)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3830, 2007}, +/*h(8011)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8011, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2247)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2287)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2287; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3823)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2263)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3287)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3287; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6383)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {6383, 2009}, +/*h(3799)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {3799, 2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2295)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 2295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3831)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {2007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4293)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4325)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5861)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5837)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4333)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4333; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4894_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12098)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12098, 2068}, +/*h(5333)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5333, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4341)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_932_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10058)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10058, 2068}, +/*h(5877)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5877, 2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5318)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2418_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5350)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5350, 2008}, +/*h(12115)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12115, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4302)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5838)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4334)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4334; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5358)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5358; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4034_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5878)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {5878, 2008}, +/*h(10059)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {10059, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5831)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5863)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4303)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5839)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5871)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4311)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4311; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4343)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5879)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b010]*/ {2008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4785_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6341)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7365)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6373)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2998_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14162)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14162, 2068}, +/*h(7397)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7397, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7909)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7373)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7885)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6381)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7405)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3557_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14146)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14146, 2068}, +/*h(7381)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7381, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6389)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7413)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12106)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {12106, 2068}, +/*h(7925)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {7925, 2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7366)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6350)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7886)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6382)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6382; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7406)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7406; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7367)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7879)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7911)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6351)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7375)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7375; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7407)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7407; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7919)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6359)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6359; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6391)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b011]*/ {2009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8389)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9413)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9925)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9925; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8421)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1661_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16210)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16210, 2068}, +/*h(9445)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9445, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3836_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9957)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9421)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9933)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8429)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9453)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16194)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {16194, 2068}, +/*h(9429)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9429, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8437)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9461)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3277_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14154)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {14154, 2068}, +/*h(9973)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {9973, 2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9414)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9926)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8398)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9454)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9966)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8391)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9415)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9927)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9447)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9959)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3685_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9423)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9455)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9455; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9967)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b100]*/ {2010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10437)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11461)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10469)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11493)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10445)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11469)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_713_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10477)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10477; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11501)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11501; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11477)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11477; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10485)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11462)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11974)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11494)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4933_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10446)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11502)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12014)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12014; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10439)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11463)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11975)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11495)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12007)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10447)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11503)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11503; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12015)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b101]*/ {2011} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12015; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13509)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13541)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13517)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12525)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13549)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13525)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14037)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13510)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14022)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14054)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12494)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13518)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14062)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14062; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12487)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14023)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {13, 2120}, +/*h(13543)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {13543, 2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((3*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14055)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12495)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13519)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13551)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14063)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b110]*/ {2012} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15589)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15565)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15565; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15597)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15573)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15573; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15605)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16070)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15590)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16102)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14542)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15566)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15566; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15598)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16110)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16110; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14535)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16103)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14543)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14575)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15599)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16111)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111]*/ {2013} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16111; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8645)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9669)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9701)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10213)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10213; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8653)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8685)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10221)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10221; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10197)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8693)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9717)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10229)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8646)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9670)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10182)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10182, 2020}, +/*h(6001)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {6001, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10214)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10214; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8654)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8654, 2020}, +/*h(1889)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1889, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8686)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8647)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9671)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6002)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {6002, 2068}, +/*h(10183)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {10183, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8679)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10215)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10215; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1890)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1890, 2068}, +/*h(8655)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {8655, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4772_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12263)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12263, 2027}, +/*h(9679)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {9679, 2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10191)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9711)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9687)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10199)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9719)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {2020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 9719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4550)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32*/ {2021} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5013_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4558)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode32*/ {2021} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4557)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] no_refining_prefix not64 eamode16*/ {2022} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4557; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6605)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6598)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6606)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6599)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6607)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b011] no_refining_prefix*/ {2025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6117)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6125)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6101)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6133)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6118)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6126)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6126; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4882_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1906)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {1906, 2068}, +/*h(6087)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {6087, 2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6119)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6119; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6095)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6127)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6127; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6103)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix*/ {2026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10693)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11717)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10725)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11749)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10701)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10733)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10709)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10741)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11765)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10694)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11718)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2788_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12230)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {12230, 2027}, +/*h(8049)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8049, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10726)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12262)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1002_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10702)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10702, 2027}, +/*h(3937)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3937, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12238)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10734)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3954_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11766)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10695)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11719)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10727)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3938)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {3938, 2068}, +/*h(10703)=1 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {10703, 2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11727)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12239)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11759)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11735)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2037_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11767)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {2027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 11767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16342)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64*/ {2028} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15813)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15845)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15829)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15861)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15814)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15822)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15854)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15830)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15862)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15815)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15823)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15831)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15863)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix*/ {2029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 15863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13781)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64*/ {2031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13813)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64*/ {2031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13782)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64*/ {2031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13814)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64*/ {2031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13783)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64*/ {2031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13815)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64*/ {2031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 13815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12742)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32*/ {2032} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4684_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12750)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32*/ {12750, 2032}, +/*h(5985)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {5985, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14790)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {2034} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3347_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14798)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix*/ {14798, 2034}, +/*h(8033)=1 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {8033, 2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10049)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10081)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12129)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14177)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2849_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10057)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12105)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14153)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1897)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3945)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5993)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8041)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10089)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12137)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14185)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16233)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14161)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16209)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1905)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3953)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10097)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12145)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14193)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16241)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1898)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3946)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5994)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8042)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10090)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12138)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3954)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1859)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1891)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3939)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1867)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3915)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1899)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1875)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3923)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5971)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1907)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3955)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6003)=0 0x0F 0x01 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() f3_refining_prefix*/ {2068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5957)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5965)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5997)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5958)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5966)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5998)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5991)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5967)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5999)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b010] f3_refining_prefix*/ {2069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1861)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1869)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1901)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1862)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1870)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1902)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1863)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1895)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1871)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1903)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f3_refining_prefix*/ {2070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4165)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4181)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4181; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4166)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4167)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4167; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4175)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4175; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4183)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b010] no_refining_prefix*/ {2104} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 4183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6213)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {2105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6213; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6229)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {2105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6223)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {2105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6223; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6231)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b011] no_refining_prefix*/ {2105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6231; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14470)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {2106} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14471)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b111] no_refining_prefix*/ {2106} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14413)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b111] no_refining_prefix*/ {2107} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {2120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 5; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {2120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 6; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {2120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b000] no_refining_prefix*/ {2120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 7; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8325)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8333)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8333; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8341)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8327)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b100] no_refining_prefix*/ {2127} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10373)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10381)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10389)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10374)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10375)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b101] no_refining_prefix*/ {2137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10375; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12422)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {2139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12423)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b010] RM[0b110] no_refining_prefix*/ {2139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12629)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12629; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12614)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12622)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12615)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] no_refining_prefix*/ {2148} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 12615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14677)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14662)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14670)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14663)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] no_refining_prefix*/ {2149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10245)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64*/ {2155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10253)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64*/ {2155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10246)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64*/ {2155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10254)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64*/ {2155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10247)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b000] RM[0b101] no_refining_prefix not64*/ {2155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14197)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b110] f3_refining_prefix mode64*/ {2175} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 14197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16245)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b111] f3_refining_prefix mode64*/ {2177} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 16245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10069)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b100] f3_refining_prefix mode64*/ {2179} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3397)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3429)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3437)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3430)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3438)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3415)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3447)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b001] f2_refining_prefix*/ {2182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 3447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1349)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1381)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1389)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1382)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1382; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1390)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1351)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1367)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1399)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] f2_refining_prefix*/ {2183} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 1399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(325)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(333)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 333; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(326)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(334)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 334; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(343)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b101] RM[0b000] no_refining_prefix*/ {2184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10357)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b101] osz_refining_prefix mode64*/ {2187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 10357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8309)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix mode64*/ {2188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8309; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8293)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64*/ {2189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8294)=0 0x0F 0x01 MOD[0b11] MOD=3 REG[0b001] RM[0b100] osz_refining_prefix not64*/ {2189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = key - 8294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[5019] = { +/*h(4181)=0 */ {4181, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_0_l1}, +/*h(8362)=1 */ {8362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1_l1}, +/*h(9959)=2 */ {9959, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2_l1}, +/*h(7375)=3 */ {7375, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12166)=7 */ {12166, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_7_l1}, +/*h(13763)=8 */ {13763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_8_l1}, +/*h(233)=9 */ {233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_9_l1}, +/*h(8595)=10 */ {8595, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_10_l1}, +/*h(1830)=11 */ {1830, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_11_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13386)=14 */ {13386, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4037)=16 */ {4037, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_16_l1}, +/*h(5634)=17 */ {5634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_17_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(466)=19 */ {466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_19_l1}, +/*h(2063)=20 */ {2063, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14606)=22 */ {14606, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_22_l1}, +/*h(16203)=23 */ {16203, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_23_l1}, +/*h(13619)=24 */ {13619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_24_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8451)=26 */ {8451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_26_l1}, +/*h(5867)=27 */ {5867, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_27_l1}, +/*h(3283)=28 */ {3283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_28_l1}, +/*h(15826)=29 */ {15826, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10658)=31 */ {10658, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_31_l1}, +/*h(8074)=32 */ {8074, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_32_l1}, +/*h(9671)=33 */ {9671, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_33_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4503)=35 */ {4503, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_35_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10281)=37 */ {10281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_37_l1}, +/*h(7697)=38 */ {7697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_38_l1}, +/*h(2529)=39 */ {2529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_39_l1}, +/*h(13475)=40 */ {13475, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_40_l1}, +/*h(8307)=41 */ {8307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_41_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3139)=43 */ {3139, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_43_l1}, +/*h(11501)=44 */ {11501, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_44_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10514)=46 */ {10514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_46_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5346)=48 */ {5346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_48_l1}, +/*h(9527)=49 */ {9527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_49_l1}, +/*h(4359)=50 */ {4359, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_50_l1}, +/*h(1775)=51 */ {1775, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_51_l1}, +/*h(12721)=52 */ {12721, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_52_l1}, +/*h(7553)=53 */ {7553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_53_l1}, +/*h(11734)=54 */ {11734, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_54_l1}, +/*h(13331)=55 */ {13331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_55_l1}, +/*h(3982)=56 */ {3982, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_56_l1}, +/*h(1398)=57 */ {1398, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_57_l1}, +/*h(5579)=58 */ {5579, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_58_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15538)=60 */ {15538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10370)=62 */ {10370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_62_l1}, +/*h(14551)=63 */ {14551, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_63_l1}, +/*h(5202)=64 */ {5202, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(34)=66 */ {34, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_66_l1}, +/*h(12577)=67 */ {12577, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_67_l1}, +/*h(9993)=68 */ {9993, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_68_l1}, +/*h(7409)=69 */ {7409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_69_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2241)=71 */ {2241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8019)=73 */ {8019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_73_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(267)=75 */ {267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_75_l1}, +/*h(15394)=76 */ {15394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_76_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14407)=78 */ {14407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_78_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2474)=80 */ {2474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_80_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4071)=82 */ {4071, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_82_l1}, +/*h(12433)=83 */ {12433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_83_l1}, +/*h(14030)=84 */ {14030, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_84_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2097)=86 */ {2097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7875)=88 */ {7875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_88_l1}, +/*h(5291)=89 */ {5291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_89_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8485)=92 */ {8485, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_92_l1}, +/*h(10082)=93 */ {10082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_93_l1}, +/*h(3317)=94 */ {3317, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_94_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12289)=98 */ {12289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_98_l1}, +/*h(9705)=99 */ {9705, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_99_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6134)=102 */ {6134, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_102_l1}, +/*h(10315)=103 */ {10315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_103_l1}, +/*h(7731)=104 */ {7731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_104_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13509)=106 */ {13509, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_106_l1}, +/*h(8341)=107 */ {8341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_107_l1}, +/*h(12522)=108 */ {12522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_108_l1}, +/*h(9938)=109 */ {9938, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_109_l1}, +/*h(11535)=110 */ {11535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_110_l1}, +/*h(2186)=111 */ {2186, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3783)=113 */ {3783, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_113_l1}, +/*h(12145)=114 */ {12145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_114_l1}, +/*h(13742)=115 */ {13742, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_115_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1809)=117 */ {1809, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_117_l1}, +/*h(5990)=118 */ {5990, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_118_l1}, +/*h(3406)=119 */ {3406, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8197)=123 */ {8197, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_123_l1}, +/*h(9794)=124 */ {9794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_124_l1}, +/*h(7210)=125 */ {7210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6223)=128 */ {6223, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_128_l1}, +/*h(12001)=129 */ {12001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_129_l1}, +/*h(9417)=130 */ {9417, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8430)=133 */ {8430, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_133_l1}, +/*h(10027)=134 */ {10027, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_134_l1}, +/*h(7443)=135 */ {7443, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2275)=137 */ {2275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_137_l1}, +/*h(14818)=138 */ {14818, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_138_l1}, +/*h(12234)=139 */ {12234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_139_l1}, +/*h(9650)=140 */ {9650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_140_l1}, +/*h(301)=141 */ {301, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_141_l1}, +/*h(8663)=142 */ {8663, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_142_l1}, +/*h(1898)=143 */ {1898, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_143_l1}, +/*h(14441)=144 */ {14441, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_144_l1}, +/*h(11857)=145 */ {11857, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4105)=148 */ {4105, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_148_l1}, +/*h(1521)=149 */ {1521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_149_l1}, +/*h(7299)=150 */ {7299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2131)=152 */ {2131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7909)=154 */ {7909, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_154_l1}, +/*h(5325)=155 */ {5325, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_155_l1}, +/*h(9506)=156 */ {9506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_156_l1}, +/*h(4338)=157 */ {4338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_157_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5935)=159 */ {5935, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_159_l1}, +/*h(3351)=160 */ {3351, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_160_l1}, +/*h(11713)=161 */ {11713, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_161_l1}, +/*h(6545)=162 */ {6545, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_162_l1}, +/*h(10726)=163 */ {10726, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_163_l1}, +/*h(12323)=164 */ {12323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_164_l1}, +/*h(9739)=165 */ {9739, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_165_l1}, +/*h(390)=166 */ {390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1987)=168 */ {1987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_168_l1}, +/*h(14530)=169 */ {14530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_169_l1}, +/*h(11946)=170 */ {11946, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_170_l1}, +/*h(9362)=171 */ {9362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_171_l1}, +/*h(13)=172 */ {13, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_172_l1}, +/*h(4194)=173 */ {4194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_173_l1}, +/*h(1610)=174 */ {1610, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_174_l1}, +/*h(14153)=175 */ {14153, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_175_l1}, +/*h(11569)=176 */ {11569, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_176_l1}, +/*h(15750)=177 */ {15750, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_177_l1}, +/*h(6401)=178 */ {6401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_178_l1}, +/*h(3817)=179 */ {3817, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_179_l1}, +/*h(1233)=180 */ {1233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(246)=182 */ {246, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_182_l1}, +/*h(1843)=183 */ {1843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14386)=185 */ {14386, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9218)=187 */ {9218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_187_l1}, +/*h(4050)=188 */ {4050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15606)=192 */ {15606, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_192_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10438)=194 */ {10438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_194_l1}, +/*h(1089)=195 */ {1089, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_195_l1}, +/*h(9451)=196 */ {9451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1699)=199 */ {1699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11658)=201 */ {11658, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_201_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2309)=203 */ {2309, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_203_l1}, +/*h(3906)=204 */ {3906, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_204_l1}, +/*h(8087)=205 */ {8087, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(335)=207 */ {335, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_207_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6113)=209 */ {6113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_209_l1}, +/*h(3529)=210 */ {3529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_210_l1}, +/*h(11891)=211 */ {11891, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_211_l1}, +/*h(2542)=212 */ {2542, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_212_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4139)=214 */ {4139, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_214_l1}, +/*h(12501)=215 */ {12501, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_215_l1}, +/*h(14098)=216 */ {14098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_216_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6346)=219 */ {6346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_219_l1}, +/*h(7943)=220 */ {7943, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_220_l1}, +/*h(5359)=221 */ {5359, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5969)=225 */ {5969, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_225_l1}, +/*h(7566)=226 */ {7566, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_226_l1}, +/*h(11747)=227 */ {11747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_227_l1}, +/*h(6579)=228 */ {6579, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_228_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1411)=230 */ {1411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13954)=232 */ {13954, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_232_l1}, +/*h(11370)=233 */ {11370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10383)=235 */ {10383, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_235_l1}, +/*h(1034)=236 */ {1034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_236_l1}, +/*h(16161)=237 */ {16161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_237_l1}, +/*h(13577)=238 */ {13577, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5825)=240 */ {5825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_240_l1}, +/*h(14187)=241 */ {14187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_241_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2254)=243 */ {2254, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_243_l1}, +/*h(6435)=244 */ {6435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_244_l1}, +/*h(14797)=245 */ {14797, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_245_l1}, +/*h(1267)=246 */ {1267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_246_l1}, +/*h(13810)=247 */ {13810, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1877)=249 */ {1877, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_249_l1}, +/*h(6058)=250 */ {6058, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_250_l1}, +/*h(3474)=251 */ {3474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_251_l1}, +/*h(16017)=252 */ {16017, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_252_l1}, +/*h(2487)=253 */ {2487, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8265)=255 */ {8265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_255_l1}, +/*h(5681)=256 */ {5681, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_256_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11459)=258 */ {11459, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6291)=260 */ {6291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_260_l1}, +/*h(1123)=261 */ {1123, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_261_l1}, +/*h(9485)=262 */ {9485, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_262_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1733)=265 */ {1733, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_265_l1}, +/*h(3330)=266 */ {3330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_266_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15873)=268 */ {15873, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_268_l1}, +/*h(2343)=269 */ {2343, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_269_l1}, +/*h(10705)=270 */ {10705, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9718)=272 */ {9718, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_272_l1}, +/*h(13899)=273 */ {13899, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_273_l1}, +/*h(4550)=274 */ {4550, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_274_l1}, +/*h(6147)=275 */ {6147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_275_l1}, +/*h(3563)=276 */ {3563, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16106)=278 */ {16106, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_278_l1}, +/*h(13522)=279 */ {13522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_279_l1}, +/*h(4173)=280 */ {4173, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_280_l1}, +/*h(12535)=281 */ {12535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_281_l1}, +/*h(3186)=282 */ {3186, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_282_l1}, +/*h(7367)=283 */ {7367, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_283_l1}, +/*h(2199)=284 */ {2199, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_284_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14742)=286 */ {14742, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_286_l1}, +/*h(16339)=287 */ {16339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_287_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(225)=289 */ {225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_289_l1}, +/*h(8587)=290 */ {8587, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_290_l1}, +/*h(6003)=291 */ {6003, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_291_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6613)=294 */ {6613, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8210)=296 */ {8210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_296_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(458)=298 */ {458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_298_l1}, +/*h(15585)=299 */ {15585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_299_l1}, +/*h(2055)=300 */ {2055, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_300_l1}, +/*h(14598)=301 */ {14598, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_301_l1}, +/*h(12014)=302 */ {12014, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_302_l1}, +/*h(16195)=303 */ {16195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_303_l1}, +/*h(81)=304 */ {81, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_304_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5859)=306 */ {5859, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_306_l1}, +/*h(3275)=307 */ {3275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_307_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15818)=309 */ {15818, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8066)=311 */ {8066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_311_l1}, +/*h(12247)=312 */ {12247, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1911)=315 */ {1911, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14454)=317 */ {14454, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_317_l1}, +/*h(16051)=318 */ {16051, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8299)=321 */ {8299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_321_l1}, +/*h(5715)=322 */ {5715, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_322_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11493)=324 */ {11493, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_324_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10506)=326 */ {10506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_326_l1}, +/*h(7922)=327 */ {7922, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_327_l1}, +/*h(9519)=328 */ {9519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_328_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(170)=330 */ {170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_330_l1}, +/*h(1767)=331 */ {1767, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_331_l1}, +/*h(10129)=332 */ {10129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11726)=334 */ {11726, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_334_l1}, +/*h(13323)=335 */ {13323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_335_l1}, +/*h(10739)=336 */ {10739, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_336_l1}, +/*h(1390)=337 */ {1390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_337_l1}, +/*h(5571)=338 */ {5571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_338_l1}, +/*h(403)=339 */ {403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_339_l1}, +/*h(15530)=340 */ {15530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14543)=342 */ {14543, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_342_l1}, +/*h(5194)=343 */ {5194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14166)=348 */ {14166, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_348_l1}, +/*h(7401)=349 */ {7401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_349_l1}, +/*h(15763)=350 */ {15763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_350_l1}, +/*h(6414)=351 */ {6414, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_351_l1}, +/*h(8011)=352 */ {8011, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_352_l1}, +/*h(16373)=353 */ {16373, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_353_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(259)=355 */ {259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_355_l1}, +/*h(8621)=356 */ {8621, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_356_l1}, +/*h(10218)=357 */ {10218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_357_l1}, +/*h(7634)=358 */ {7634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2466)=360 */ {2466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_360_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12425)=362 */ {12425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_362_l1}, +/*h(9841)=363 */ {9841, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_363_l1}, +/*h(14022)=364 */ {14022, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_364_l1}, +/*h(15619)=365 */ {15619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_365_l1}, +/*h(2089)=366 */ {2089, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_366_l1}, +/*h(10451)=367 */ {10451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_367_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5283)=369 */ {5283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_369_l1}, +/*h(115)=370 */ {115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5893)=372 */ {5893, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_372_l1}, +/*h(3309)=373 */ {3309, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_373_l1}, +/*h(11671)=374 */ {11671, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2322)=376 */ {2322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1335)=378 */ {1335, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_378_l1}, +/*h(9697)=379 */ {9697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_379_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15475)=381 */ {15475, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_381_l1}, +/*h(6126)=382 */ {6126, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_382_l1}, +/*h(3542)=383 */ {3542, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_383_l1}, +/*h(16085)=384 */ {16085, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8333)=387 */ {8333, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_387_l1}, +/*h(12514)=388 */ {12514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_388_l1}, +/*h(9930)=389 */ {9930, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_389_l1}, +/*h(11527)=390 */ {11527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_390_l1}, +/*h(2178)=391 */ {2178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_391_l1}, +/*h(6359)=392 */ {6359, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_392_l1}, +/*h(14721)=393 */ {14721, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_393_l1}, +/*h(12137)=394 */ {12137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_394_l1}, +/*h(13734)=395 */ {13734, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_395_l1}, +/*h(4385)=396 */ {4385, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_396_l1}, +/*h(12747)=397 */ {12747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_397_l1}, +/*h(3398)=398 */ {3398, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12370)=403 */ {12370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7202)=405 */ {7202, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6215)=407 */ {6215, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_407_l1}, +/*h(14577)=408 */ {14577, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_408_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9409)=410 */ {9409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_410_l1}, +/*h(13590)=411 */ {13590, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_411_l1}, +/*h(8422)=412 */ {8422, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_412_l1}, +/*h(5838)=413 */ {5838, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_413_l1}, +/*h(10019)=414 */ {10019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_414_l1}, +/*h(7435)=415 */ {7435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_415_l1}, +/*h(15797)=416 */ {15797, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_416_l1}, +/*h(10629)=417 */ {10629, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12226)=419 */ {12226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_419_l1}, +/*h(9642)=420 */ {9642, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_420_l1}, +/*h(293)=421 */ {293, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_421_l1}, +/*h(1890)=422 */ {1890, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_422_l1}, +/*h(6071)=423 */ {6071, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_423_l1}, +/*h(14433)=424 */ {14433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_424_l1}, +/*h(11849)=425 */ {11849, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_425_l1}, +/*h(9265)=426 */ {9265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_426_l1}, +/*h(4097)=427 */ {4097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_427_l1}, +/*h(1513)=428 */ {1513, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_428_l1}, +/*h(9875)=429 */ {9875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_429_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15653)=431 */ {15653, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_431_l1}, +/*h(2123)=432 */ {2123, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_432_l1}, +/*h(10485)=433 */ {10485, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_433_l1}, +/*h(12082)=434 */ {12082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_434_l1}, +/*h(5317)=435 */ {5317, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_435_l1}, +/*h(149)=436 */ {149, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_436_l1}, +/*h(4330)=437 */ {4330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_437_l1}, +/*h(1746)=438 */ {1746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_438_l1}, +/*h(14289)=439 */ {14289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6537)=442 */ {6537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_442_l1}, +/*h(3953)=443 */ {3953, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_443_l1}, +/*h(5550)=444 */ {5550, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_444_l1}, +/*h(9731)=445 */ {9731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4563)=447 */ {4563, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11938)=450 */ {11938, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_450_l1}, +/*h(16119)=451 */ {16119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_451_l1}, +/*h(5)=452 */ {5, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_452_l1}, +/*h(1602)=453 */ {1602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_453_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14145)=455 */ {14145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_455_l1}, +/*h(11561)=456 */ {11561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1225)=459 */ {1225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_459_l1}, +/*h(12171)=460 */ {12171, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_460_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(238)=462 */ {238, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_462_l1}, +/*h(1835)=463 */ {1835, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_463_l1}, +/*h(10197)=464 */ {10197, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_464_l1}, +/*h(14378)=465 */ {14378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_465_l1}, +/*h(11794)=466 */ {11794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_466_l1}, +/*h(6626)=467 */ {6626, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_467_l1}, +/*h(4042)=468 */ {4042, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_468_l1}, +/*h(1458)=469 */ {1458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_469_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(471)=471 */ {471, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_471_l1}, +/*h(15598)=472 */ {15598, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_472_l1}, +/*h(6249)=473 */ {6249, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_473_l1}, +/*h(3665)=474 */ {3665, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9443)=476 */ {9443, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4275)=478 */ {4275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11650)=481 */ {11650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_481_l1}, +/*h(15831)=482 */ {15831, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_482_l1}, +/*h(10663)=483 */ {10663, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_483_l1}, +/*h(8079)=484 */ {8079, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_484_l1}, +/*h(1314)=485 */ {1314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_485_l1}, +/*h(13857)=486 */ {13857, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_486_l1}, +/*h(327)=487 */ {327, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_487_l1}, +/*h(8689)=488 */ {8689, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_488_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3521)=490 */ {3521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_490_l1}, +/*h(11883)=491 */ {11883, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_491_l1}, +/*h(2534)=492 */ {2534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_492_l1}, +/*h(4131)=493 */ {4131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_493_l1}, +/*h(12493)=494 */ {12493, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_494_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14090)=496 */ {14090, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_496_l1}, +/*h(11506)=497 */ {11506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_497_l1}, +/*h(6338)=498 */ {6338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_498_l1}, +/*h(10519)=499 */ {10519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_499_l1}, +/*h(1170)=500 */ {1170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_500_l1}, +/*h(5351)=501 */ {5351, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_501_l1}, +/*h(13713)=502 */ {13713, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5961)=504 */ {5961, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_504_l1}, +/*h(3377)=505 */ {3377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_505_l1}, +/*h(14323)=506 */ {14323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_506_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6571)=508 */ {6571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_508_l1}, +/*h(3987)=509 */ {3987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_509_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11362)=512 */ {11362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_512_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6194)=514 */ {6194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_514_l1}, +/*h(10375)=515 */ {10375, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_515_l1}, +/*h(1026)=516 */ {1026, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_516_l1}, +/*h(13569)=517 */ {13569, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8401)=519 */ {8401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_519_l1}, +/*h(12582)=520 */ {12582, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_520_l1}, +/*h(14179)=521 */ {14179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_521_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2246)=523 */ {2246, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_523_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14789)=525 */ {14789, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_525_l1}, +/*h(12205)=526 */ {12205, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_526_l1}, +/*h(13802)=527 */ {13802, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_527_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1869)=529 */ {1869, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_529_l1}, +/*h(10231)=530 */ {10231, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_530_l1}, +/*h(3466)=531 */ {3466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_531_l1}, +/*h(16009)=532 */ {16009, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_532_l1}, +/*h(13425)=533 */ {13425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_533_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12438)=535 */ {12438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_535_l1}, +/*h(5673)=536 */ {5673, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_536_l1}, +/*h(14035)=537 */ {14035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_537_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6283)=539 */ {6283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_539_l1}, +/*h(3699)=540 */ {3699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16242)=542 */ {16242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4309)=544 */ {4309, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_544_l1}, +/*h(5906)=545 */ {5906, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_545_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10697)=549 */ {10697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_549_l1}, +/*h(8113)=550 */ {8113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_550_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9710)=552 */ {9710, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_552_l1}, +/*h(11307)=553 */ {11307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_553_l1}, +/*h(1958)=554 */ {1958, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_554_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3555)=556 */ {3555, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_556_l1}, +/*h(16098)=557 */ {16098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_557_l1}, +/*h(13514)=558 */ {13514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_558_l1}, +/*h(4165)=559 */ {4165, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_559_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12527)=561 */ {12527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_561_l1}, +/*h(3178)=562 */ {3178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_562_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2191)=564 */ {2191, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_564_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12150)=566 */ {12150, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_566_l1}, +/*h(16331)=567 */ {16331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_567_l1}, +/*h(13747)=568 */ {13747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_568_l1}, +/*h(4398)=569 */ {4398, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_569_l1}, +/*h(5995)=570 */ {5995, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_570_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15954)=573 */ {15954, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_573_l1}, +/*h(6605)=574 */ {6605, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_574_l1}, +/*h(4021)=575 */ {4021, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_575_l1}, +/*h(5618)=576 */ {5618, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(450)=578 */ {450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10409)=581 */ {10409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_581_l1}, +/*h(12006)=582 */ {12006, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_582_l1}, +/*h(9422)=583 */ {9422, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_583_l1}, +/*h(73)=584 */ {73, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_584_l1}, +/*h(8435)=585 */ {8435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_585_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3267)=587 */ {3267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_587_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15810)=589 */ {15810, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_589_l1}, +/*h(10642)=590 */ {10642, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_590_l1}, +/*h(1293)=591 */ {1293, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_591_l1}, +/*h(12239)=592 */ {12239, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_592_l1}, +/*h(9655)=593 */ {9655, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_593_l1}, +/*h(15433)=594 */ {15433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_594_l1}, +/*h(1903)=595 */ {1903, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_595_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7681)=597 */ {7681, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_597_l1}, +/*h(16043)=598 */ {16043, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_598_l1}, +/*h(2513)=599 */ {2513, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_599_l1}, +/*h(4110)=600 */ {4110, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_600_l1}, +/*h(1526)=601 */ {1526, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_601_l1}, +/*h(5707)=602 */ {5707, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_602_l1}, +/*h(14069)=603 */ {14069, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_603_l1}, +/*h(15666)=604 */ {15666, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_604_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14679)=606 */ {14679, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_606_l1}, +/*h(7914)=607 */ {7914, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_607_l1}, +/*h(5330)=608 */ {5330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_608_l1}, +/*h(162)=609 */ {162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_609_l1}, +/*h(4343)=610 */ {4343, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_610_l1}, +/*h(12705)=611 */ {12705, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_611_l1}, +/*h(10121)=612 */ {10121, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_612_l1}, +/*h(11718)=613 */ {11718, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_613_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10731)=615 */ {10731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_615_l1}, +/*h(8147)=616 */ {8147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_616_l1}, +/*h(1382)=617 */ {1382, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_617_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(395)=619 */ {395, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_619_l1}, +/*h(15522)=620 */ {15522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_620_l1}, +/*h(10354)=621 */ {10354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_621_l1}, +/*h(14535)=622 */ {14535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_622_l1}, +/*h(5186)=623 */ {5186, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_623_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(18)=625 */ {18, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12561)=627 */ {12561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_627_l1}, +/*h(7393)=628 */ {7393, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_628_l1}, +/*h(15755)=629 */ {15755, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_629_l1}, +/*h(2225)=630 */ {2225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_630_l1}, +/*h(3822)=631 */ {3822, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_631_l1}, +/*h(8003)=632 */ {8003, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_632_l1}, +/*h(5419)=633 */ {5419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_633_l1}, +/*h(13781)=634 */ {13781, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_634_l1}, +/*h(15378)=635 */ {15378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_635_l1}, +/*h(6029)=636 */ {6029, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_636_l1}, +/*h(3445)=637 */ {3445, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_637_l1}, +/*h(7626)=638 */ {7626, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_638_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4055)=641 */ {4055, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_641_l1}, +/*h(12417)=642 */ {12417, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_642_l1}, +/*h(9833)=643 */ {9833, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_643_l1}, +/*h(7249)=644 */ {7249, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_644_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2081)=646 */ {2081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_646_l1}, +/*h(10443)=647 */ {10443, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_647_l1}, +/*h(7859)=648 */ {7859, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_648_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(107)=650 */ {107, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_650_l1}, +/*h(8469)=651 */ {8469, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_651_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10066)=653 */ {10066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_653_l1}, +/*h(11663)=654 */ {11663, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_654_l1}, +/*h(2314)=655 */ {2314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12273)=658 */ {12273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_658_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4521)=660 */ {4521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_660_l1}, +/*h(15467)=661 */ {15467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_661_l1}, +/*h(6118)=662 */ {6118, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_662_l1}, +/*h(3534)=663 */ {3534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_663_l1}, +/*h(16077)=664 */ {16077, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_664_l1}, +/*h(2547)=665 */ {2547, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_665_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8325)=667 */ {8325, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_667_l1}, +/*h(9922)=668 */ {9922, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_668_l1}, +/*h(14103)=669 */ {14103, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6351)=671 */ {6351, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_671_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12129)=673 */ {12129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_673_l1}, +/*h(16310)=674 */ {16310, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_674_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5974)=677 */ {5974, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_677_l1}, +/*h(10155)=678 */ {10155, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_678_l1}, +/*h(7571)=679 */ {7571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_679_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12362)=683 */ {12362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_683_l1}, +/*h(9778)=684 */ {9778, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_684_l1}, +/*h(429)=685 */ {429, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_685_l1}, +/*h(2026)=686 */ {2026, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14569)=688 */ {14569, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_688_l1}, +/*h(11985)=689 */ {11985, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_689_l1}, +/*h(13582)=690 */ {13582, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_690_l1}, +/*h(4233)=691 */ {4233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_691_l1}, +/*h(1649)=692 */ {1649, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_692_l1}, +/*h(5830)=693 */ {5830, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_693_l1}, +/*h(7427)=694 */ {7427, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_694_l1}, +/*h(15789)=695 */ {15789, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_695_l1}, +/*h(2259)=696 */ {2259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_696_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14802)=698 */ {14802, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_698_l1}, +/*h(9634)=699 */ {9634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_699_l1}, +/*h(13815)=700 */ {13815, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_700_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8647)=702 */ {8647, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_702_l1}, +/*h(3479)=703 */ {3479, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_703_l1}, +/*h(11841)=704 */ {11841, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_704_l1}, +/*h(9257)=705 */ {9257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_705_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1505)=708 */ {1505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_708_l1}, +/*h(9867)=709 */ {9867, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_709_l1}, +/*h(7283)=710 */ {7283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_710_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2115)=712 */ {2115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_712_l1}, +/*h(10477)=713 */ {10477, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_713_l1}, +/*h(7893)=714 */ {7893, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_714_l1}, +/*h(9490)=715 */ {9490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_715_l1}, +/*h(141)=716 */ {141, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_716_l1}, +/*h(4322)=717 */ {4322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_717_l1}, +/*h(1738)=718 */ {1738, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_718_l1}, +/*h(14281)=719 */ {14281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_719_l1}, +/*h(11697)=720 */ {11697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_720_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10710)=722 */ {10710, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_722_l1}, +/*h(3945)=723 */ {3945, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_723_l1}, +/*h(12307)=724 */ {12307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_724_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4555)=726 */ {4555, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_726_l1}, +/*h(1971)=727 */ {1971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14514)=729 */ {14514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_729_l1}, +/*h(16111)=730 */ {16111, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_730_l1}, +/*h(13527)=731 */ {13527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_731_l1}, +/*h(4178)=732 */ {4178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_732_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11553)=736 */ {11553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_736_l1}, +/*h(6385)=737 */ {6385, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_737_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1217)=739 */ {1217, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_739_l1}, +/*h(5398)=740 */ {5398, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_740_l1}, +/*h(230)=741 */ {230, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_741_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1827)=743 */ {1827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_743_l1}, +/*h(10189)=744 */ {10189, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_744_l1}, +/*h(11786)=745 */ {11786, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_745_l1}, +/*h(2437)=746 */ {2437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_746_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4034)=748 */ {4034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_748_l1}, +/*h(1450)=749 */ {1450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_749_l1}, +/*h(13993)=750 */ {13993, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_750_l1}, +/*h(11409)=751 */ {11409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_751_l1}, +/*h(15590)=752 */ {15590, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_752_l1}, +/*h(6241)=753 */ {6241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_753_l1}, +/*h(3657)=754 */ {3657, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_754_l1}, +/*h(12019)=755 */ {12019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_755_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(86)=757 */ {86, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_757_l1}, +/*h(4267)=758 */ {4267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_758_l1}, +/*h(12629)=759 */ {12629, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_759_l1}, +/*h(14226)=760 */ {14226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_760_l1}, +/*h(15823)=761 */ {15823, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_761_l1}, +/*h(2293)=762 */ {2293, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_762_l1}, +/*h(3890)=763 */ {3890, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_763_l1}, +/*h(8071)=764 */ {8071, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11265)=767 */ {11265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_767_l1}, +/*h(8681)=768 */ {8681, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_768_l1}, +/*h(6097)=769 */ {6097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_769_l1}, +/*h(11875)=770 */ {11875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_770_l1}, +/*h(9291)=771 */ {9291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12485)=774 */ {12485, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_774_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11498)=776 */ {11498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_776_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10511)=779 */ {10511, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_779_l1}, +/*h(7927)=780 */ {7927, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_780_l1}, +/*h(16289)=781 */ {16289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_781_l1}, +/*h(13705)=782 */ {13705, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_782_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5953)=784 */ {5953, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_784_l1}, +/*h(14315)=785 */ {14315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_785_l1}, +/*h(11731)=786 */ {11731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_786_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6563)=788 */ {6563, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_788_l1}, +/*h(3979)=789 */ {3979, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_789_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13938)=791 */ {13938, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_791_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2005)=793 */ {2005, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_793_l1}, +/*h(6186)=794 */ {6186, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_794_l1}, +/*h(3602)=795 */ {3602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_795_l1}, +/*h(16145)=796 */ {16145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_796_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8393)=799 */ {8393, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_799_l1}, +/*h(9990)=800 */ {9990, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_800_l1}, +/*h(7406)=801 */ {7406, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_801_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6419)=803 */ {6419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1251)=805 */ {1251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_805_l1}, +/*h(9613)=806 */ {9613, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_806_l1}, +/*h(13794)=807 */ {13794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_807_l1}, +/*h(8626)=808 */ {8626, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_808_l1}, +/*h(1861)=809 */ {1861, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_809_l1}, +/*h(10223)=810 */ {10223, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_810_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16001)=812 */ {16001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_812_l1}, +/*h(13417)=813 */ {13417, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_813_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12430)=815 */ {12430, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_815_l1}, +/*h(14027)=816 */ {14027, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_816_l1}, +/*h(497)=817 */ {497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_817_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6275)=819 */ {6275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_819_l1}, +/*h(3691)=820 */ {3691, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_820_l1}, +/*h(16234)=821 */ {16234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_821_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4301)=824 */ {4301, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_824_l1}, +/*h(5898)=825 */ {5898, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_825_l1}, +/*h(3314)=826 */ {3314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_826_l1}, +/*h(15857)=827 */ {15857, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_827_l1}, +/*h(2327)=828 */ {2327, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_828_l1}, +/*h(10689)=829 */ {10689, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_829_l1}, +/*h(8105)=830 */ {8105, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_830_l1}, +/*h(9702)=831 */ {9702, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_831_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11299)=833 */ {11299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_833_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6131)=835 */ {6131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_835_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13506)=838 */ {13506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_838_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12519)=840 */ {12519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_840_l1}, +/*h(9935)=841 */ {9935, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_841_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2183)=844 */ {2183, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_844_l1}, +/*h(14726)=845 */ {14726, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_845_l1}, +/*h(5377)=846 */ {5377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_846_l1}, +/*h(16323)=847 */ {16323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_847_l1}, +/*h(209)=848 */ {209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_848_l1}, +/*h(4390)=849 */ {4390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_849_l1}, +/*h(5987)=850 */ {5987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_850_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11765)=852 */ {11765, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_852_l1}, +/*h(15946)=853 */ {15946, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_853_l1}, +/*h(6597)=854 */ {6597, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_854_l1}, +/*h(8194)=855 */ {8194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_855_l1}, +/*h(5610)=856 */ {5610, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_856_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2039)=859 */ {2039, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_859_l1}, +/*h(10401)=860 */ {10401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_860_l1}, +/*h(14582)=861 */ {14582, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_861_l1}, +/*h(5233)=862 */ {5233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_862_l1}, +/*h(9414)=863 */ {9414, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_863_l1}, +/*h(65)=864 */ {65, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_864_l1}, +/*h(8427)=865 */ {8427, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_865_l1}, +/*h(5843)=866 */ {5843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_866_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6453)=869 */ {6453, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_869_l1}, +/*h(10634)=870 */ {10634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_870_l1}, +/*h(8050)=871 */ {8050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_871_l1}, +/*h(9647)=872 */ {9647, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_872_l1}, +/*h(298)=873 */ {298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_873_l1}, +/*h(15425)=874 */ {15425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_874_l1}, +/*h(1895)=875 */ {1895, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_875_l1}, +/*h(10257)=876 */ {10257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_876_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16035)=878 */ {16035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_878_l1}, +/*h(2505)=879 */ {2505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_879_l1}, +/*h(4102)=880 */ {4102, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_880_l1}, +/*h(5699)=881 */ {5699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_881_l1}, +/*h(14061)=882 */ {14061, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_882_l1}, +/*h(11477)=883 */ {11477, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_883_l1}, +/*h(15658)=884 */ {15658, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_884_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14671)=886 */ {14671, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_886_l1}, +/*h(5322)=887 */ {5322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_887_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4335)=890 */ {4335, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_890_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14294)=892 */ {14294, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_892_l1}, +/*h(15891)=893 */ {15891, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_893_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10723)=895 */ {10723, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_895_l1}, +/*h(8139)=896 */ {8139, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_896_l1}, +/*h(5555)=897 */ {5555, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_897_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(387)=899 */ {387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_899_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10346)=901 */ {10346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_901_l1}, +/*h(7762)=902 */ {7762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_902_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10)=905 */ {10, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_905_l1}, +/*h(12553)=906 */ {12553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_906_l1}, +/*h(9969)=907 */ {9969, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_907_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15747)=909 */ {15747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_909_l1}, +/*h(2217)=910 */ {2217, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_910_l1}, +/*h(3814)=911 */ {3814, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_911_l1}, +/*h(1230)=912 */ {1230, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_912_l1}, +/*h(5411)=913 */ {5411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_913_l1}, +/*h(243)=914 */ {243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_914_l1}, +/*h(15370)=915 */ {15370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_915_l1}, +/*h(12786)=916 */ {12786, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_916_l1}, +/*h(3437)=917 */ {3437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_917_l1}, +/*h(7618)=918 */ {7618, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_918_l1}, +/*h(2450)=919 */ {2450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_919_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4047)=921 */ {4047, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_921_l1}, +/*h(1463)=922 */ {1463, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_922_l1}, +/*h(9825)=923 */ {9825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_923_l1}, +/*h(7241)=924 */ {7241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_924_l1}, +/*h(15603)=925 */ {15603, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_925_l1}, +/*h(10435)=926 */ {10435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_926_l1}, +/*h(7851)=927 */ {7851, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_927_l1}, +/*h(16213)=928 */ {16213, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_928_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(99)=930 */ {99, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_930_l1}, +/*h(8461)=931 */ {8461, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_931_l1}, +/*h(10058)=932 */ {10058, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_932_l1}, +/*h(7474)=933 */ {7474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_933_l1}, +/*h(11655)=934 */ {11655, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_934_l1}, +/*h(2306)=935 */ {2306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_935_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12265)=937 */ {12265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_937_l1}, +/*h(9681)=938 */ {9681, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_938_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15459)=940 */ {15459, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_940_l1}, +/*h(8694)=941 */ {8694, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_941_l1}, +/*h(3526)=942 */ {3526, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_942_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16069)=944 */ {16069, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_944_l1}, +/*h(2539)=945 */ {2539, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_945_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12498)=947 */ {12498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_947_l1}, +/*h(14095)=948 */ {14095, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_948_l1}, +/*h(11511)=949 */ {11511, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_949_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6343)=951 */ {6343, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_951_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13718)=954 */ {13718, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_954_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4369)=956 */ {4369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_956_l1}, +/*h(5966)=957 */ {5966, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_957_l1}, +/*h(7563)=958 */ {7563, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_958_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12354)=963 */ {12354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_963_l1}, +/*h(7186)=964 */ {7186, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_964_l1}, +/*h(421)=965 */ {421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_965_l1}, +/*h(2018)=966 */ {2018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14561)=968 */ {14561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_968_l1}, +/*h(11977)=969 */ {11977, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_969_l1}, +/*h(13574)=970 */ {13574, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_970_l1}, +/*h(4225)=971 */ {4225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_971_l1}, +/*h(8406)=972 */ {8406, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_972_l1}, +/*h(10003)=973 */ {10003, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_973_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15781)=975 */ {15781, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_975_l1}, +/*h(2251)=976 */ {2251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_976_l1}, +/*h(14794)=977 */ {14794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_977_l1}, +/*h(12210)=978 */ {12210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_978_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(277)=980 */ {277, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_980_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1874)=982 */ {1874, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_982_l1}, +/*h(14417)=983 */ {14417, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_983_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9249)=985 */ {9249, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_985_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4081)=987 */ {4081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_987_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9859)=989 */ {9859, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_989_l1}, +/*h(7275)=990 */ {7275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_990_l1}, +/*h(15637)=991 */ {15637, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_991_l1}, +/*h(10469)=992 */ {10469, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_992_l1}, +/*h(7885)=993 */ {7885, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_993_l1}, +/*h(16247)=994 */ {16247, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_994_l1}, +/*h(9482)=995 */ {9482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_995_l1}, +/*h(133)=996 */ {133, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_996_l1}, +/*h(1730)=997 */ {1730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_997_l1}, +/*h(5911)=998 */ {5911, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_998_l1}, +/*h(14273)=999 */ {14273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_999_l1}, +/*h(11689)=1000 */ {11689, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1000_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3937)=1002 */ {3937, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1002_l1}, +/*h(12299)=1003 */ {12299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1003_l1}, +/*h(9715)=1004 */ {9715, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1004_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4547)=1006 */ {4547, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1006_l1}, +/*h(1963)=1007 */ {1963, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1007_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14506)=1009 */ {14506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1009_l1}, +/*h(16103)=1010 */ {16103, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1010_l1}, +/*h(13519)=1011 */ {13519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1011_l1}, +/*h(4170)=1012 */ {4170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1012_l1}, +/*h(1586)=1013 */ {1586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1013_l1}, +/*h(14129)=1014 */ {14129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1014_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6377)=1017 */ {6377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1017_l1}, +/*h(3793)=1018 */ {3793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1018_l1}, +/*h(5390)=1019 */ {5390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1019_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4403)=1022 */ {4403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1022_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10181)=1024 */ {10181, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1024_l1}, +/*h(11778)=1025 */ {11778, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6610)=1027 */ {6610, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1027_l1}, +/*h(8207)=1028 */ {8207, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1028_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13985)=1030 */ {13985, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1030_l1}, +/*h(11401)=1031 */ {11401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1031_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3649)=1034 */ {3649, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1034_l1}, +/*h(12011)=1035 */ {12011, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1035_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(78)=1037 */ {78, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1037_l1}, +/*h(12621)=1038 */ {12621, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1038_l1}, +/*h(10037)=1039 */ {10037, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1039_l1}, +/*h(14218)=1040 */ {14218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1040_l1}, +/*h(15815)=1041 */ {15815, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1041_l1}, +/*h(2285)=1042 */ {2285, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1042_l1}, +/*h(10647)=1043 */ {10647, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1043_l1}, +/*h(1298)=1044 */ {1298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1044_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13841)=1046 */ {13841, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1046_l1}, +/*h(8673)=1047 */ {8673, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1047_l1}, +/*h(6089)=1048 */ {6089, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1048_l1}, +/*h(14451)=1049 */ {14451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1049_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2518)=1051 */ {2518, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1051_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4115)=1053 */ {4115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1053_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11490)=1056 */ {11490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1056_l1}, +/*h(15671)=1057 */ {15671, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1057_l1}, +/*h(10503)=1058 */ {10503, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1058_l1}, +/*h(7919)=1059 */ {7919, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1059_l1}, +/*h(5335)=1060 */ {5335, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1060_l1}, +/*h(13697)=1061 */ {13697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10126)=1064 */ {10126, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1064_l1}, +/*h(14307)=1065 */ {14307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1065_l1}, +/*h(11723)=1066 */ {11723, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1066_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3971)=1068 */ {3971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1068_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13930)=1071 */ {13930, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1071_l1}, +/*h(11346)=1072 */ {11346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1072_l1}, +/*h(6178)=1073 */ {6178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1073_l1}, +/*h(10359)=1074 */ {10359, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1074_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16137)=1076 */ {16137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1076_l1}, +/*h(23)=1077 */ {23, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1077_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8385)=1079 */ {8385, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1079_l1}, +/*h(14163)=1080 */ {14163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1080_l1}, +/*h(7398)=1081 */ {7398, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1081_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6411)=1083 */ {6411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1083_l1}, +/*h(3827)=1084 */ {3827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1084_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16370)=1086 */ {16370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1086_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8618)=1088 */ {8618, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1088_l1}, +/*h(6034)=1089 */ {6034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1089_l1}, +/*h(10215)=1090 */ {10215, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1090_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13409)=1092 */ {13409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1092_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8241)=1094 */ {8241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1094_l1}, +/*h(12422)=1095 */ {12422, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1095_l1}, +/*h(14019)=1096 */ {14019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1096_l1}, +/*h(489)=1097 */ {489, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1097_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1099)=1100 */ {1099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1100_l1}, +/*h(16226)=1101 */ {16226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1101_l1}, +/*h(9461)=1102 */ {9461, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1102_l1}, +/*h(4293)=1103 */ {4293, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10071)=1105 */ {10071, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1105_l1}, +/*h(3306)=1106 */ {3306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1106_l1}, +/*h(15849)=1107 */ {15849, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1107_l1}, +/*h(2319)=1108 */ {2319, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12278)=1110 */ {12278, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1110_l1}, +/*h(5513)=1111 */ {5513, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1111_l1}, +/*h(13875)=1112 */ {13875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1112_l1}, +/*h(4526)=1113 */ {4526, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1113_l1}, +/*h(6123)=1114 */ {6123, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1114_l1}, +/*h(14485)=1115 */ {14485, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1115_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16082)=1117 */ {16082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8330)=1119 */ {8330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1119_l1}, +/*h(5746)=1120 */ {5746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1120_l1}, +/*h(9927)=1121 */ {9927, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10537)=1124 */ {10537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1124_l1}, +/*h(7953)=1125 */ {7953, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13731)=1127 */ {13731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1127_l1}, +/*h(201)=1128 */ {201, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1128_l1}, +/*h(1798)=1129 */ {1798, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1129_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11757)=1132 */ {11757, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1132_l1}, +/*h(13354)=1133 */ {13354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1133_l1}, +/*h(4005)=1134 */ {4005, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1134_l1}, +/*h(1421)=1135 */ {1421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1135_l1}, +/*h(5602)=1136 */ {5602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1136_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15561)=1138 */ {15561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14574)=1141 */ {14574, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1141_l1}, +/*h(5225)=1142 */ {5225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1142_l1}, +/*h(13587)=1143 */ {13587, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1143_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5835)=1145 */ {5835, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1145_l1}, +/*h(3251)=1146 */ {3251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1146_l1}, +/*h(14197)=1147 */ {14197, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1147_l1}, +/*h(15794)=1148 */ {15794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1148_l1}, +/*h(6445)=1149 */ {6445, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1149_l1}, +/*h(14807)=1150 */ {14807, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1150_l1}, +/*h(8042)=1151 */ {8042, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1151_l1}, +/*h(9639)=1152 */ {9639, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1152_l1}, +/*h(290)=1153 */ {290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7665)=1156 */ {7665, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2497)=1158 */ {2497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8275)=1160 */ {8275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14053)=1162 */ {14053, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1162_l1}, +/*h(11469)=1163 */ {11469, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1163_l1}, +/*h(15650)=1164 */ {15650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1164_l1}, +/*h(10482)=1165 */ {10482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1165_l1}, +/*h(14663)=1166 */ {14663, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1166_l1}, +/*h(5314)=1167 */ {5314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1167_l1}, +/*h(9495)=1168 */ {9495, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1168_l1}, +/*h(4327)=1169 */ {4327, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1169_l1}, +/*h(1743)=1170 */ {1743, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15883)=1173 */ {15883, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1173_l1}, +/*h(6534)=1174 */ {6534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1174_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1366)=1176 */ {1366, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1176_l1}, +/*h(5547)=1177 */ {5547, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1177_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15506)=1179 */ {15506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1179_l1}, +/*h(6157)=1180 */ {6157, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1180_l1}, +/*h(3573)=1181 */ {3573, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1181_l1}, +/*h(7754)=1182 */ {7754, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1182_l1}, +/*h(5170)=1183 */ {5170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1183_l1}, +/*h(2)=1184 */ {2, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1184_l1}, +/*h(4183)=1185 */ {4183, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1185_l1}, +/*h(12545)=1186 */ {12545, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1186_l1}, +/*h(9961)=1187 */ {9961, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1187_l1}, +/*h(7377)=1188 */ {7377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1188_l1}, +/*h(2209)=1189 */ {2209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1189_l1}, +/*h(6390)=1190 */ {6390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1190_l1}, +/*h(7987)=1191 */ {7987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1191_l1}, +/*h(1222)=1192 */ {1222, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1192_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(235)=1194 */ {235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1194_l1}, +/*h(15362)=1195 */ {15362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1195_l1}, +/*h(10194)=1196 */ {10194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1196_l1}, +/*h(3429)=1197 */ {3429, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2442)=1199 */ {2442, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1199_l1}, +/*h(4039)=1200 */ {4039, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1200_l1}, +/*h(1455)=1201 */ {1455, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1201_l1}, +/*h(12401)=1202 */ {12401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1202_l1}, +/*h(7233)=1203 */ {7233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1203_l1}, +/*h(15595)=1204 */ {15595, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1204_l1}, +/*h(2065)=1205 */ {2065, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7843)=1207 */ {7843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1207_l1}, +/*h(5259)=1208 */ {5259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1208_l1}, +/*h(13621)=1209 */ {13621, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5869)=1211 */ {5869, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1211_l1}, +/*h(10050)=1212 */ {10050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1212_l1}, +/*h(14231)=1213 */ {14231, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3895)=1216 */ {3895, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1216_l1}, +/*h(12257)=1217 */ {12257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1217_l1}, +/*h(9673)=1218 */ {9673, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8686)=1220 */ {8686, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1220_l1}, +/*h(6102)=1221 */ {6102, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1221_l1}, +/*h(10283)=1222 */ {10283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1222_l1}, +/*h(7699)=1223 */ {7699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1223_l1}, +/*h(2531)=1224 */ {2531, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8309)=1226 */ {8309, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1226_l1}, +/*h(12490)=1227 */ {12490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1227_l1}, +/*h(14087)=1228 */ {14087, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1228_l1}, +/*h(11503)=1229 */ {11503, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1229_l1}, +/*h(2154)=1230 */ {2154, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12113)=1233 */ {12113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1233_l1}, +/*h(13710)=1234 */ {13710, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1234_l1}, +/*h(4361)=1235 */ {4361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1235_l1}, +/*h(1777)=1236 */ {1777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1236_l1}, +/*h(5958)=1237 */ {5958, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1237_l1}, +/*h(7555)=1238 */ {7555, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9762)=1243 */ {9762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1243_l1}, +/*h(7178)=1244 */ {7178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1244_l1}, +/*h(4594)=1245 */ {4594, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1245_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11969)=1248 */ {11969, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1248_l1}, +/*h(16150)=1249 */ {16150, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8398)=1251 */ {8398, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1251_l1}, +/*h(1633)=1252 */ {1633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1252_l1}, +/*h(9995)=1253 */ {9995, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1253_l1}, +/*h(7411)=1254 */ {7411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1254_l1}, +/*h(2243)=1255 */ {2243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1255_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14786)=1257 */ {14786, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1257_l1}, +/*h(12202)=1258 */ {12202, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1258_l1}, +/*h(9618)=1259 */ {9618, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1259_l1}, +/*h(269)=1260 */ {269, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1260_l1}, +/*h(1866)=1261 */ {1866, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14409)=1263 */ {14409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1263_l1}, +/*h(11825)=1264 */ {11825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4073)=1266 */ {4073, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1266_l1}, +/*h(1489)=1267 */ {1489, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1267_l1}, +/*h(12435)=1268 */ {12435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1268_l1}, +/*h(7267)=1269 */ {7267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1269_l1}, +/*h(502)=1270 */ {502, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1270_l1}, +/*h(2099)=1271 */ {2099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7877)=1273 */ {7877, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1273_l1}, +/*h(9474)=1274 */ {9474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1274_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4306)=1276 */ {4306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1276_l1}, +/*h(8487)=1277 */ {8487, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1277_l1}, +/*h(3319)=1278 */ {3319, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1278_l1}, +/*h(11681)=1279 */ {11681, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1279_l1}, +/*h(15862)=1280 */ {15862, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1280_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10694)=1282 */ {10694, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1282_l1}, +/*h(12291)=1283 */ {12291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1283_l1}, +/*h(9707)=1284 */ {9707, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1284_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1955)=1287 */ {1955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1287_l1}, +/*h(14498)=1288 */ {14498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1288_l1}, +/*h(11914)=1289 */ {11914, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1289_l1}, +/*h(13511)=1290 */ {13511, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8343)=1292 */ {8343, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1292_l1}, +/*h(1578)=1293 */ {1578, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1293_l1}, +/*h(14121)=1294 */ {14121, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1294_l1}, +/*h(11537)=1295 */ {11537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6369)=1297 */ {6369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1297_l1}, +/*h(3785)=1298 */ {3785, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1298_l1}, +/*h(12147)=1299 */ {12147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1299_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(214)=1301 */ {214, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1301_l1}, +/*h(1811)=1302 */ {1811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14354)=1304 */ {14354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1304_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6602)=1306 */ {6602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1306_l1}, +/*h(4018)=1307 */ {4018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1307_l1}, +/*h(8199)=1308 */ {8199, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1308_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15574)=1311 */ {15574, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1311_l1}, +/*h(6225)=1312 */ {6225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12003)=1314 */ {12003, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1314_l1}, +/*h(9419)=1315 */ {9419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1315_l1}, +/*h(70)=1316 */ {70, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1316_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12613)=1318 */ {12613, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1318_l1}, +/*h(14210)=1319 */ {14210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1319_l1}, +/*h(7445)=1320 */ {7445, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1320_l1}, +/*h(2277)=1321 */ {2277, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1321_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10639)=1323 */ {10639, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1323_l1}, +/*h(1290)=1324 */ {1290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1324_l1}, +/*h(13833)=1325 */ {13833, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1325_l1}, +/*h(303)=1326 */ {303, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10262)=1328 */ {10262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1328_l1}, +/*h(14443)=1329 */ {14443, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1329_l1}, +/*h(11859)=1330 */ {11859, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1330_l1}, +/*h(2510)=1331 */ {2510, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1331_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1523)=1333 */ {1523, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14066)=1335 */ {14066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1335_l1}, +/*h(15663)=1336 */ {15663, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1336_l1}, +/*h(2133)=1337 */ {2133, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1337_l1}, +/*h(6314)=1338 */ {6314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1338_l1}, +/*h(7911)=1339 */ {7911, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1339_l1}, +/*h(5327)=1340 */ {5327, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10118)=1344 */ {10118, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1344_l1}, +/*h(11715)=1345 */ {11715, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6547)=1347 */ {6547, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11338)=1351 */ {11338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1351_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3586)=1354 */ {3586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16129)=1356 */ {16129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1356_l1}, +/*h(15)=1357 */ {15, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1357_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12558)=1359 */ {12558, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1359_l1}, +/*h(14155)=1360 */ {14155, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1360_l1}, +/*h(11571)=1361 */ {11571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6403)=1363 */ {6403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1363_l1}, +/*h(3819)=1364 */ {3819, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1364_l1}, +/*h(16362)=1365 */ {16362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1365_l1}, +/*h(13778)=1366 */ {13778, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8610)=1368 */ {8610, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1368_l1}, +/*h(6026)=1369 */ {6026, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1369_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15985)=1371 */ {15985, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1371_l1}, +/*h(2455)=1372 */ {2455, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8233)=1374 */ {8233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1374_l1}, +/*h(5649)=1375 */ {5649, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1375_l1}, +/*h(481)=1376 */ {481, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1376_l1}, +/*h(11427)=1377 */ {11427, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1377_l1}, +/*h(6259)=1378 */ {6259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1091)=1380 */ {1091, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1380_l1}, +/*h(9453)=1381 */ {9453, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1381_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8466)=1383 */ {8466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3298)=1385 */ {3298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1385_l1}, +/*h(7479)=1386 */ {7479, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1386_l1}, +/*h(15841)=1387 */ {15841, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10673)=1389 */ {10673, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1389_l1}, +/*h(12270)=1390 */ {12270, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1390_l1}, +/*h(9686)=1391 */ {9686, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1391_l1}, +/*h(11283)=1392 */ {11283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1392_l1}, +/*h(1934)=1393 */ {1934, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1393_l1}, +/*h(6115)=1394 */ {6115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1394_l1}, +/*h(14477)=1395 */ {14477, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1395_l1}, +/*h(16074)=1396 */ {16074, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1396_l1}, +/*h(13490)=1397 */ {13490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8322)=1399 */ {8322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1399_l1}, +/*h(12503)=1400 */ {12503, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1400_l1}, +/*h(3154)=1401 */ {3154, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1401_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10529)=1404 */ {10529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1404_l1}, +/*h(7945)=1405 */ {7945, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1405_l1}, +/*h(5361)=1406 */ {5361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(193)=1408 */ {193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1408_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5971)=1410 */ {5971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11749)=1412 */ {11749, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1412_l1}, +/*h(13346)=1413 */ {13346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1413_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8178)=1415 */ {8178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(426)=1417 */ {426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1417_l1}, +/*h(15553)=1418 */ {15553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1418_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14566)=1420 */ {14566, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1420_l1}, +/*h(11982)=1421 */ {11982, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1421_l1}, +/*h(16163)=1422 */ {16163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1422_l1}, +/*h(49)=1423 */ {49, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1423_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5827)=1425 */ {5827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1425_l1}, +/*h(3243)=1426 */ {3243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1426_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15786)=1428 */ {15786, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1428_l1}, +/*h(6437)=1429 */ {6437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1429_l1}, +/*h(8034)=1430 */ {8034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1430_l1}, +/*h(1269)=1431 */ {1269, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1431_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1879)=1434 */ {1879, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1434_l1}, +/*h(10241)=1435 */ {10241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1435_l1}, +/*h(14422)=1436 */ {14422, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1436_l1}, +/*h(16019)=1437 */ {16019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4086)=1439 */ {4086, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1439_l1}, +/*h(8267)=1440 */ {8267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1440_l1}, +/*h(5683)=1441 */ {5683, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1441_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11461)=1443 */ {11461, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1443_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10474)=1445 */ {10474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1445_l1}, +/*h(7890)=1446 */ {7890, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1446_l1}, +/*h(9487)=1447 */ {9487, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1447_l1}, +/*h(138)=1448 */ {138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1735)=1450 */ {1735, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1450_l1}, +/*h(10097)=1451 */ {10097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1451_l1}, +/*h(11694)=1452 */ {11694, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1452_l1}, +/*h(15875)=1453 */ {15875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1453_l1}, +/*h(2345)=1454 */ {2345, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1454_l1}, +/*h(10707)=1455 */ {10707, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1455_l1}, +/*h(1358)=1456 */ {1358, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15498)=1459 */ {15498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1459_l1}, +/*h(6149)=1460 */ {6149, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1460_l1}, +/*h(3565)=1461 */ {3565, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1461_l1}, +/*h(5162)=1462 */ {5162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4175)=1465 */ {4175, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1465_l1}, +/*h(9953)=1466 */ {9953, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1466_l1}, +/*h(7369)=1467 */ {7369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1467_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6382)=1470 */ {6382, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1470_l1}, +/*h(3798)=1471 */ {3798, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1471_l1}, +/*h(16341)=1472 */ {16341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1472_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(227)=1474 */ {227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1474_l1}, +/*h(12770)=1475 */ {12770, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1475_l1}, +/*h(6005)=1476 */ {6005, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1476_l1}, +/*h(7602)=1477 */ {7602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6615)=1479 */ {6615, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1479_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12393)=1481 */ {12393, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1481_l1}, +/*h(9809)=1482 */ {9809, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1482_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15587)=1484 */ {15587, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1484_l1}, +/*h(2057)=1485 */ {2057, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1485_l1}, +/*h(10419)=1486 */ {10419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1486_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5251)=1488 */ {5251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1488_l1}, +/*h(83)=1489 */ {83, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1489_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5861)=1491 */ {5861, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1491_l1}, +/*h(3277)=1492 */ {3277, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1492_l1}, +/*h(7458)=1493 */ {7458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1493_l1}, +/*h(2290)=1494 */ {2290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1494_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14833)=1496 */ {14833, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1496_l1}, +/*h(1303)=1497 */ {1303, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1497_l1}, +/*h(9665)=1498 */ {9665, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1498_l1}, +/*h(4497)=1499 */ {4497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1499_l1}, +/*h(8678)=1500 */ {8678, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1500_l1}, +/*h(6094)=1501 */ {6094, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1501_l1}, +/*h(7691)=1502 */ {7691, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8301)=1506 */ {8301, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1506_l1}, +/*h(9898)=1507 */ {9898, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1507_l1}, +/*h(7314)=1508 */ {7314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1508_l1}, +/*h(11495)=1509 */ {11495, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1509_l1}, +/*h(2146)=1510 */ {2146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12105)=1512 */ {12105, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1512_l1}, +/*h(9521)=1513 */ {9521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1513_l1}, +/*h(13702)=1514 */ {13702, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1514_l1}, +/*h(4353)=1515 */ {4353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1515_l1}, +/*h(1769)=1516 */ {1769, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1516_l1}, +/*h(10131)=1517 */ {10131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10741)=1521 */ {10741, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1521_l1}, +/*h(12338)=1522 */ {12338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7170)=1524 */ {7170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1524_l1}, +/*h(4586)=1525 */ {4586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1525_l1}, +/*h(2002)=1526 */ {2002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1526_l1}, +/*h(14545)=1527 */ {14545, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1527_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13558)=1529 */ {13558, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1529_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8390)=1531 */ {8390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1531_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7403)=1533 */ {7403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1533_l1}, +/*h(15765)=1534 */ {15765, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1534_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16375)=1538 */ {16375, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(261)=1540 */ {261, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1540_l1}, +/*h(1858)=1541 */ {1858, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1541_l1}, +/*h(6039)=1542 */ {6039, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1542_l1}, +/*h(14401)=1543 */ {14401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1543_l1}, +/*h(11817)=1544 */ {11817, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1544_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4065)=1546 */ {4065, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1546_l1}, +/*h(1481)=1547 */ {1481, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1547_l1}, +/*h(9843)=1548 */ {9843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15621)=1550 */ {15621, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1550_l1}, +/*h(2091)=1551 */ {2091, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1551_l1}, +/*h(10453)=1552 */ {10453, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1552_l1}, +/*h(12050)=1553 */ {12050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1553_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4298)=1556 */ {4298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1556_l1}, +/*h(5895)=1557 */ {5895, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1557_l1}, +/*h(3311)=1558 */ {3311, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15854)=1560 */ {15854, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1560_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3921)=1562 */ {3921, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1562_l1}, +/*h(5518)=1563 */ {5518, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1563_l1}, +/*h(9699)=1564 */ {9699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1564_l1}, +/*h(4531)=1565 */ {4531, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16087)=1569 */ {16087, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1569_l1}, +/*h(9322)=1570 */ {9322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1570_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8335)=1572 */ {8335, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1572_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14113)=1574 */ {14113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1574_l1}, +/*h(11529)=1575 */ {11529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1575_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3777)=1577 */ {3777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1577_l1}, +/*h(12139)=1578 */ {12139, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(206)=1580 */ {206, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1580_l1}, +/*h(4387)=1581 */ {4387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1581_l1}, +/*h(1803)=1582 */ {1803, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1582_l1}, +/*h(10165)=1583 */ {10165, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1583_l1}, +/*h(11762)=1584 */ {11762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1584_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6594)=1586 */ {6594, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1586_l1}, +/*h(4010)=1587 */ {4010, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1587_l1}, +/*h(1426)=1588 */ {1426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1588_l1}, +/*h(13969)=1589 */ {13969, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1589_l1}, +/*h(439)=1590 */ {439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1590_l1}, +/*h(15566)=1591 */ {15566, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1591_l1}, +/*h(6217)=1592 */ {6217, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1592_l1}, +/*h(14579)=1593 */ {14579, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1593_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9411)=1595 */ {9411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1595_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4243)=1597 */ {4243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7437)=1599 */ {7437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1599_l1}, +/*h(15799)=1600 */ {15799, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1600_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10631)=1602 */ {10631, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1602_l1}, +/*h(1282)=1603 */ {1282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1603_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13825)=1605 */ {13825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1605_l1}, +/*h(295)=1606 */ {295, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1606_l1}, +/*h(8657)=1607 */ {8657, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1607_l1}, +/*h(10254)=1608 */ {10254, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1608_l1}, +/*h(14435)=1609 */ {14435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1609_l1}, +/*h(11851)=1610 */ {11851, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1610_l1}, +/*h(2502)=1611 */ {2502, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1611_l1}, +/*h(4099)=1612 */ {4099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1612_l1}, +/*h(1515)=1613 */ {1515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1613_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14058)=1615 */ {14058, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1615_l1}, +/*h(11474)=1616 */ {11474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1616_l1}, +/*h(2125)=1617 */ {2125, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1617_l1}, +/*h(10487)=1618 */ {10487, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1618_l1}, +/*h(1138)=1619 */ {1138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1619_l1}, +/*h(5319)=1620 */ {5319, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1620_l1}, +/*h(151)=1621 */ {151, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1621_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12694)=1623 */ {12694, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1623_l1}, +/*h(14291)=1624 */ {14291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2358)=1626 */ {2358, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1626_l1}, +/*h(6539)=1627 */ {6539, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1627_l1}, +/*h(3955)=1628 */ {3955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1628_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11330)=1631 */ {11330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1631_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6162)=1633 */ {6162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1633_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13537)=1636 */ {13537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1636_l1}, +/*h(7)=1637 */ {7, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1637_l1}, +/*h(12550)=1638 */ {12550, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1638_l1}, +/*h(9966)=1639 */ {9966, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1639_l1}, +/*h(14147)=1640 */ {14147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1640_l1}, +/*h(11563)=1641 */ {11563, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1641_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3811)=1643 */ {3811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1643_l1}, +/*h(1227)=1644 */ {1227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1644_l1}, +/*h(16354)=1645 */ {16354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1645_l1}, +/*h(13770)=1646 */ {13770, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1646_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6018)=1648 */ {6018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1648_l1}, +/*h(10199)=1649 */ {10199, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1649_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15977)=1651 */ {15977, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1651_l1}, +/*h(13393)=1652 */ {13393, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12406)=1654 */ {12406, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1654_l1}, +/*h(14003)=1655 */ {14003, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6251)=1658 */ {6251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1658_l1}, +/*h(3667)=1659 */ {3667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1659_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16210)=1661 */ {16210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8458)=1663 */ {8458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1663_l1}, +/*h(5874)=1664 */ {5874, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1664_l1}, +/*h(7471)=1665 */ {7471, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1665_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10665)=1668 */ {10665, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1668_l1}, +/*h(8081)=1669 */ {8081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1669_l1}, +/*h(12262)=1670 */ {12262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1670_l1}, +/*h(9678)=1671 */ {9678, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1671_l1}, +/*h(11275)=1672 */ {11275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1672_l1}, +/*h(8691)=1673 */ {8691, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1673_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14469)=1675 */ {14469, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1675_l1}, +/*h(16066)=1676 */ {16066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1676_l1}, +/*h(13482)=1677 */ {13482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1677_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12495)=1679 */ {12495, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1679_l1}, +/*h(5730)=1680 */ {5730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1680_l1}, +/*h(3146)=1681 */ {3146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1681_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12118)=1685 */ {12118, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1685_l1}, +/*h(5353)=1686 */ {5353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1686_l1}, +/*h(13715)=1687 */ {13715, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1687_l1}, +/*h(4366)=1688 */ {4366, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1688_l1}, +/*h(5963)=1689 */ {5963, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1689_l1}, +/*h(14325)=1690 */ {14325, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1690_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15922)=1692 */ {15922, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1692_l1}, +/*h(6573)=1693 */ {6573, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1693_l1}, +/*h(8170)=1694 */ {8170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1694_l1}, +/*h(5586)=1695 */ {5586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1695_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(418)=1697 */ {418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1697_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10377)=1699 */ {10377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1699_l1}, +/*h(7793)=1700 */ {7793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1700_l1}, +/*h(11974)=1701 */ {11974, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1701_l1}, +/*h(13571)=1702 */ {13571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1702_l1}, +/*h(41)=1703 */ {41, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1703_l1}, +/*h(8403)=1704 */ {8403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1704_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3235)=1706 */ {3235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1706_l1}, +/*h(15778)=1707 */ {15778, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1707_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3845)=1709 */ {3845, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1709_l1}, +/*h(14791)=1710 */ {14791, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1710_l1}, +/*h(9623)=1711 */ {9623, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1711_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15401)=1713 */ {15401, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1713_l1}, +/*h(1871)=1714 */ {1871, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1714_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14414)=1716 */ {14414, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1716_l1}, +/*h(16011)=1717 */ {16011, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1717_l1}, +/*h(13427)=1718 */ {13427, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1718_l1}, +/*h(4078)=1719 */ {4078, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1719_l1}, +/*h(1494)=1720 */ {1494, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1720_l1}, +/*h(3091)=1721 */ {3091, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1721_l1}, +/*h(14037)=1722 */ {14037, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1722_l1}, +/*h(15634)=1723 */ {15634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1723_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10466)=1725 */ {10466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1725_l1}, +/*h(7882)=1726 */ {7882, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1726_l1}, +/*h(9479)=1727 */ {9479, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1727_l1}, +/*h(130)=1728 */ {130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1728_l1}, +/*h(4311)=1729 */ {4311, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1729_l1}, +/*h(12673)=1730 */ {12673, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1730_l1}, +/*h(10089)=1731 */ {10089, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1731_l1}, +/*h(11686)=1732 */ {11686, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1732_l1}, +/*h(2337)=1733 */ {2337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1733_l1}, +/*h(10699)=1734 */ {10699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1734_l1}, +/*h(1350)=1735 */ {1350, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15490)=1739 */ {15490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1739_l1}, +/*h(10322)=1740 */ {10322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1740_l1}, +/*h(3557)=1741 */ {3557, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1741_l1}, +/*h(5154)=1742 */ {5154, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1742_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4167)=1744 */ {4167, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1744_l1}, +/*h(12529)=1745 */ {12529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1745_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7361)=1747 */ {7361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1747_l1}, +/*h(11542)=1748 */ {11542, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1748_l1}, +/*h(6374)=1749 */ {6374, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1749_l1}, +/*h(3790)=1750 */ {3790, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1750_l1}, +/*h(7971)=1751 */ {7971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1751_l1}, +/*h(5387)=1752 */ {5387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1752_l1}, +/*h(13749)=1753 */ {13749, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1753_l1}, +/*h(8581)=1754 */ {8581, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1754_l1}, +/*h(5997)=1755 */ {5997, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1755_l1}, +/*h(3413)=1756 */ {3413, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1756_l1}, +/*h(7594)=1757 */ {7594, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1757_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6607)=1759 */ {6607, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1759_l1}, +/*h(4023)=1760 */ {4023, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1760_l1}, +/*h(12385)=1761 */ {12385, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1761_l1}, +/*h(9801)=1762 */ {9801, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1762_l1}, +/*h(7217)=1763 */ {7217, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1763_l1}, +/*h(2049)=1764 */ {2049, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1764_l1}, +/*h(6230)=1765 */ {6230, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1765_l1}, +/*h(7827)=1766 */ {7827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1766_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13605)=1768 */ {13605, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1768_l1}, +/*h(75)=1769 */ {75, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1769_l1}, +/*h(8437)=1770 */ {8437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1770_l1}, +/*h(10034)=1771 */ {10034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1771_l1}, +/*h(3269)=1772 */ {3269, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1772_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2282)=1774 */ {2282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1774_l1}, +/*h(3879)=1775 */ {3879, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1775_l1}, +/*h(14825)=1776 */ {14825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1776_l1}, +/*h(12241)=1777 */ {12241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1777_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15435)=1779 */ {15435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1779_l1}, +/*h(1905)=1780 */ {1905, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1780_l1}, +/*h(6086)=1781 */ {6086, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1781_l1}, +/*h(7683)=1782 */ {7683, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1782_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2515)=1784 */ {2515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1784_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8293)=1786 */ {8293, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1786_l1}, +/*h(9890)=1787 */ {9890, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1787_l1}, +/*h(14071)=1788 */ {14071, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12097)=1792 */ {12097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1792_l1}, +/*h(16278)=1793 */ {16278, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1793_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1761)=1796 */ {1761, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1796_l1}, +/*h(10123)=1797 */ {10123, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1797_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10733)=1800 */ {10733, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1800_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12330)=1802 */ {12330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1802_l1}, +/*h(9746)=1803 */ {9746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1803_l1}, +/*h(4578)=1804 */ {4578, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1804_l1}, +/*h(1994)=1805 */ {1994, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1805_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14537)=1807 */ {14537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1807_l1}, +/*h(16134)=1808 */ {16134, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1808_l1}, +/*h(13550)=1809 */ {13550, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1809_l1}, +/*h(4201)=1810 */ {4201, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1810_l1}, +/*h(1617)=1811 */ {1617, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1811_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7395)=1813 */ {7395, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1813_l1}, +/*h(15757)=1814 */ {15757, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1814_l1}, +/*h(2227)=1815 */ {2227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1815_l1}, +/*h(14770)=1816 */ {14770, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1816_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9602)=1818 */ {9602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1818_l1}, +/*h(13783)=1819 */ {13783, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1819_l1}, +/*h(8615)=1820 */ {8615, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1820_l1}, +/*h(6031)=1821 */ {6031, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1821_l1}, +/*h(3447)=1822 */ {3447, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1822_l1}, +/*h(11809)=1823 */ {11809, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1823_l1}, +/*h(9225)=1824 */ {9225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1824_l1}, +/*h(6641)=1825 */ {6641, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1473)=1827 */ {1473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1827_l1}, +/*h(9835)=1828 */ {9835, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1828_l1}, +/*h(7251)=1829 */ {7251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1829_l1}, +/*h(2083)=1830 */ {2083, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1830_l1}, +/*h(10445)=1831 */ {10445, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1831_l1}, +/*h(14626)=1832 */ {14626, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1832_l1}, +/*h(12042)=1833 */ {12042, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1833_l1}, +/*h(9458)=1834 */ {9458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1834_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4290)=1836 */ {4290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1836_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3303)=1838 */ {3303, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1838_l1}, +/*h(15846)=1839 */ {15846, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3913)=1841 */ {3913, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1841_l1}, +/*h(1329)=1842 */ {1329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1842_l1}, +/*h(12275)=1843 */ {12275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1843_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(342)=1845 */ {342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1845_l1}, +/*h(1939)=1846 */ {1939, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1846_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14482)=1848 */ {14482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1848_l1}, +/*h(16079)=1849 */ {16079, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1849_l1}, +/*h(2549)=1850 */ {2549, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1850_l1}, +/*h(4146)=1851 */ {4146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1851_l1}, +/*h(8327)=1852 */ {8327, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1852_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11521)=1854 */ {11521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6353)=1856 */ {6353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1856_l1}, +/*h(10534)=1857 */ {10534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1857_l1}, +/*h(12131)=1858 */ {12131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1858_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(198)=1860 */ {198, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1860_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1795)=1862 */ {1795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1862_l1}, +/*h(14338)=1863 */ {14338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1863_l1}, +/*h(11754)=1864 */ {11754, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1864_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4002)=1867 */ {4002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1867_l1}, +/*h(1418)=1868 */ {1418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1868_l1}, +/*h(13961)=1869 */ {13961, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1869_l1}, +/*h(11377)=1870 */ {11377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1870_l1}, +/*h(15558)=1871 */ {15558, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1871_l1}, +/*h(10390)=1872 */ {10390, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1872_l1}, +/*h(14571)=1873 */ {14571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1873_l1}, +/*h(11987)=1874 */ {11987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1874_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4235)=1876 */ {4235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1876_l1}, +/*h(1651)=1877 */ {1651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1877_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14194)=1879 */ {14194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1879_l1}, +/*h(15791)=1880 */ {15791, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1880_l1}, +/*h(2261)=1881 */ {2261, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1881_l1}, +/*h(3858)=1882 */ {3858, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1882_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8649)=1886 */ {8649, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1886_l1}, +/*h(6065)=1887 */ {6065, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1887_l1}, +/*h(10246)=1888 */ {10246, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1888_l1}, +/*h(11843)=1889 */ {11843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1889_l1}, +/*h(9259)=1890 */ {9259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1890_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1507)=1893 */ {1507, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1893_l1}, +/*h(14050)=1894 */ {14050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1894_l1}, +/*h(11466)=1895 */ {11466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1895_l1}, +/*h(2117)=1896 */ {2117, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1896_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10479)=1898 */ {10479, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1898_l1}, +/*h(1130)=1899 */ {1130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1899_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(143)=1901 */ {143, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1901_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10102)=1903 */ {10102, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1903_l1}, +/*h(14283)=1904 */ {14283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1904_l1}, +/*h(11699)=1905 */ {11699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1905_l1}, +/*h(2350)=1906 */ {2350, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1906_l1}, +/*h(3947)=1907 */ {3947, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1907_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13906)=1910 */ {13906, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1910_l1}, +/*h(4557)=1911 */ {4557, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1911_l1}, +/*h(1973)=1912 */ {1973, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1912_l1}, +/*h(3570)=1913 */ {3570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1913_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16113)=1915 */ {16113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8361)=1918 */ {8361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1918_l1}, +/*h(9958)=1919 */ {9958, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1919_l1}, +/*h(7374)=1920 */ {7374, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6387)=1922 */ {6387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1922_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1219)=1924 */ {1219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1924_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13762)=1926 */ {13762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1926_l1}, +/*h(8594)=1927 */ {8594, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1927_l1}, +/*h(1829)=1928 */ {1829, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1928_l1}, +/*h(10191)=1929 */ {10191, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1929_l1}, +/*h(7607)=1930 */ {7607, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1930_l1}, +/*h(15969)=1931 */ {15969, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1931_l1}, +/*h(13385)=1932 */ {13385, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5633)=1934 */ {5633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1934_l1}, +/*h(13995)=1935 */ {13995, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1935_l1}, +/*h(465)=1936 */ {465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1936_l1}, +/*h(2062)=1937 */ {2062, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1937_l1}, +/*h(6243)=1938 */ {6243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1938_l1}, +/*h(3659)=1939 */ {3659, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1939_l1}, +/*h(16202)=1940 */ {16202, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1940_l1}, +/*h(13618)=1941 */ {13618, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1941_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12631)=1943 */ {12631, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1943_l1}, +/*h(5866)=1944 */ {5866, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1944_l1}, +/*h(3282)=1945 */ {3282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1945_l1}, +/*h(15825)=1946 */ {15825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1946_l1}, +/*h(2295)=1947 */ {2295, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1947_l1}, +/*h(10657)=1948 */ {10657, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1948_l1}, +/*h(8073)=1949 */ {8073, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1949_l1}, +/*h(9670)=1950 */ {9670, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1950_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11267)=1952 */ {11267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1952_l1}, +/*h(6099)=1953 */ {6099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1953_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13474)=1957 */ {13474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1957_l1}, +/*h(8306)=1958 */ {8306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1958_l1}, +/*h(12487)=1959 */ {12487, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1959_l1}, +/*h(3138)=1960 */ {3138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1960_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10513)=1964 */ {10513, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1964_l1}, +/*h(5345)=1965 */ {5345, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1965_l1}, +/*h(13707)=1966 */ {13707, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1966_l1}, +/*h(177)=1967 */ {177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1967_l1}, +/*h(1774)=1968 */ {1774, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1968_l1}, +/*h(5955)=1969 */ {5955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1969_l1}, +/*h(3371)=1970 */ {3371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1970_l1}, +/*h(11733)=1971 */ {11733, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1971_l1}, +/*h(13330)=1972 */ {13330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1972_l1}, +/*h(6565)=1973 */ {6565, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1973_l1}, +/*h(1397)=1974 */ {1397, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1974_l1}, +/*h(5578)=1975 */ {5578, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1975_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15537)=1977 */ {15537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1977_l1}, +/*h(2007)=1978 */ {2007, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1978_l1}, +/*h(10369)=1979 */ {10369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1979_l1}, +/*h(14550)=1980 */ {14550, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1980_l1}, +/*h(5201)=1981 */ {5201, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1981_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(33)=1983 */ {33, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1983_l1}, +/*h(8395)=1984 */ {8395, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1984_l1}, +/*h(5811)=1985 */ {5811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1985_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6421)=1988 */ {6421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1988_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8018)=1990 */ {8018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1990_l1}, +/*h(9615)=1991 */ {9615, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1991_l1}, +/*h(266)=1992 */ {266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1992_l1}, +/*h(15393)=1993 */ {15393, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1993_l1}, +/*h(1863)=1994 */ {1863, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1994_l1}, +/*h(14406)=1995 */ {14406, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1995_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2473)=1997 */ {2473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1997_l1}, +/*h(13419)=1998 */ {13419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1998_l1}, +/*h(4070)=1999 */ {4070, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_1999_l1}, +/*h(5667)=2000 */ {5667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2000_l1}, +/*h(14029)=2001 */ {14029, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2001_l1}, +/*h(499)=2002 */ {499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2002_l1}, +/*h(15626)=2003 */ {15626, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2003_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7874)=2005 */ {7874, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2005_l1}, +/*h(12055)=2006 */ {12055, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2006_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4303)=2008 */ {4303, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2008_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10081)=2010 */ {10081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2010_l1}, +/*h(14262)=2011 */ {14262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2011_l1}, +/*h(15859)=2012 */ {15859, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2012_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10691)=2014 */ {10691, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2014_l1}, +/*h(8107)=2015 */ {8107, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2015_l1}, +/*h(5523)=2016 */ {5523, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2016_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6133)=2019 */ {6133, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2019_l1}, +/*h(10314)=2020 */ {10314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2020_l1}, +/*h(7730)=2021 */ {7730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12521)=2025 */ {12521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2025_l1}, +/*h(9937)=2026 */ {9937, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2026_l1}, +/*h(11534)=2027 */ {11534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2185)=2029 */ {2185, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2029_l1}, +/*h(3782)=2030 */ {3782, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2030_l1}, +/*h(5379)=2031 */ {5379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2031_l1}, +/*h(13741)=2032 */ {13741, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2032_l1}, +/*h(211)=2033 */ {211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2033_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5989)=2035 */ {5989, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2035_l1}, +/*h(3405)=2036 */ {3405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2036_l1}, +/*h(11767)=2037 */ {11767, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2037_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6599)=2039 */ {6599, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2039_l1}, +/*h(1431)=2040 */ {1431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2040_l1}, +/*h(9793)=2041 */ {9793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2041_l1}, +/*h(7209)=2042 */ {7209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2042_l1}, +/*h(15571)=2043 */ {15571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2043_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6222)=2045 */ {6222, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2045_l1}, +/*h(7819)=2046 */ {7819, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2046_l1}, +/*h(5235)=2047 */ {5235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(67)=2049 */ {67, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2049_l1}, +/*h(8429)=2050 */ {8429, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2050_l1}, +/*h(5845)=2051 */ {5845, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2051_l1}, +/*h(7442)=2052 */ {7442, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2052_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2274)=2054 */ {2274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2054_l1}, +/*h(14817)=2055 */ {14817, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2055_l1}, +/*h(12233)=2056 */ {12233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2056_l1}, +/*h(9649)=2057 */ {9649, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2057_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8662)=2059 */ {8662, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2059_l1}, +/*h(1897)=2060 */ {1897, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2060_l1}, +/*h(10259)=2061 */ {10259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2507)=2063 */ {2507, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2063_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12466)=2066 */ {12466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2066_l1}, +/*h(14063)=2067 */ {14063, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2067_l1}, +/*h(11479)=2068 */ {11479, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2068_l1}, +/*h(2130)=2069 */ {2130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2069_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16270)=2072 */ {16270, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2072_l1}, +/*h(9505)=2073 */ {9505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2073_l1}, +/*h(4337)=2074 */ {4337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2074_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10115)=2076 */ {10115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2076_l1}, +/*h(3350)=2077 */ {3350, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2077_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10725)=2080 */ {10725, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2080_l1}, +/*h(12322)=2081 */ {12322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2081_l1}, +/*h(9738)=2082 */ {9738, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2082_l1}, +/*h(389)=2083 */ {389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2083_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1986)=2085 */ {1986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2085_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14529)=2087 */ {14529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2087_l1}, +/*h(9361)=2088 */ {9361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2088_l1}, +/*h(13542)=2089 */ {13542, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2089_l1}, +/*h(4193)=2090 */ {4193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2090_l1}, +/*h(1609)=2091 */ {1609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2091_l1}, +/*h(9971)=2092 */ {9971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2092_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15749)=2094 */ {15749, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2094_l1}, +/*h(2219)=2095 */ {2219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2095_l1}, +/*h(14762)=2096 */ {14762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2096_l1}, +/*h(12178)=2097 */ {12178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2097_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(245)=2099 */ {245, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2099_l1}, +/*h(1842)=2100 */ {1842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2100_l1}, +/*h(6023)=2101 */ {6023, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2101_l1}, +/*h(3439)=2102 */ {3439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9217)=2104 */ {9217, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2104_l1}, +/*h(6633)=2105 */ {6633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2105_l1}, +/*h(4049)=2106 */ {4049, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7243)=2108 */ {7243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2108_l1}, +/*h(15605)=2109 */ {15605, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2109_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10437)=2111 */ {10437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16215)=2113 */ {16215, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8463)=2116 */ {8463, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2116_l1}, +/*h(5879)=2117 */ {5879, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2117_l1}, +/*h(14241)=2118 */ {14241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2118_l1}, +/*h(11657)=2119 */ {11657, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3905)=2121 */ {3905, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2121_l1}, +/*h(12267)=2122 */ {12267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2122_l1}, +/*h(9683)=2123 */ {9683, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2123_l1}, +/*h(334)=2124 */ {334, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2124_l1}, +/*h(4515)=2125 */ {4515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2125_l1}, +/*h(1931)=2126 */ {1931, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2126_l1}, +/*h(14474)=2127 */ {14474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2127_l1}, +/*h(11890)=2128 */ {11890, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2128_l1}, +/*h(16071)=2129 */ {16071, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2129_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4138)=2131 */ {4138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2131_l1}, +/*h(1554)=2132 */ {1554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2132_l1}, +/*h(14097)=2133 */ {14097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6345)=2136 */ {6345, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2136_l1}, +/*h(7942)=2137 */ {7942, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2137_l1}, +/*h(5358)=2138 */ {5358, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4371)=2140 */ {4371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10149)=2142 */ {10149, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2142_l1}, +/*h(7565)=2143 */ {7565, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2143_l1}, +/*h(11746)=2144 */ {11746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2144_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6578)=2146 */ {6578, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2146_l1}, +/*h(1410)=2147 */ {1410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13953)=2149 */ {13953, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2149_l1}, +/*h(11369)=2150 */ {11369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10382)=2152 */ {10382, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2152_l1}, +/*h(11979)=2153 */ {11979, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2153_l1}, +/*h(9395)=2154 */ {9395, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4227)=2156 */ {4227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2156_l1}, +/*h(1643)=2157 */ {1643, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2157_l1}, +/*h(14186)=2158 */ {14186, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15783)=2160 */ {15783, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2160_l1}, +/*h(2253)=2161 */ {2253, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2161_l1}, +/*h(3850)=2162 */ {3850, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2162_l1}, +/*h(1266)=2163 */ {1266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2163_l1}, +/*h(13809)=2164 */ {13809, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2164_l1}, +/*h(279)=2165 */ {279, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2165_l1}, +/*h(8641)=2166 */ {8641, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2166_l1}, +/*h(6057)=2167 */ {6057, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2167_l1}, +/*h(14419)=2168 */ {14419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9251)=2170 */ {9251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4083)=2172 */ {4083, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11458)=2175 */ {11458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10471)=2177 */ {10471, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2177_l1}, +/*h(7887)=2178 */ {7887, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(135)=2181 */ {135, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2181_l1}, +/*h(12678)=2182 */ {12678, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2182_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14275)=2184 */ {14275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2184_l1}, +/*h(11691)=2185 */ {11691, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2185_l1}, +/*h(2342)=2186 */ {2342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2186_l1}, +/*h(3939)=2187 */ {3939, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2187_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9717)=2189 */ {9717, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2189_l1}, +/*h(13898)=2190 */ {13898, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2190_l1}, +/*h(4549)=2191 */ {4549, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2191_l1}, +/*h(6146)=2192 */ {6146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2192_l1}, +/*h(3562)=2193 */ {3562, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16105)=2195 */ {16105, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2195_l1}, +/*h(13521)=2196 */ {13521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2196_l1}, +/*h(8353)=2197 */ {8353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2197_l1}, +/*h(12534)=2198 */ {12534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2198_l1}, +/*h(3185)=2199 */ {3185, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2199_l1}, +/*h(7366)=2200 */ {7366, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2200_l1}, +/*h(2198)=2201 */ {2198, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2201_l1}, +/*h(6379)=2202 */ {6379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2202_l1}, +/*h(3795)=2203 */ {3795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2203_l1}, +/*h(16338)=2204 */ {16338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2204_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4405)=2206 */ {4405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2206_l1}, +/*h(8586)=2207 */ {8586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2207_l1}, +/*h(6002)=2208 */ {6002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2208_l1}, +/*h(7599)=2209 */ {7599, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13377)=2211 */ {13377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2211_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8209)=2213 */ {8209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13987)=2215 */ {13987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2215_l1}, +/*h(457)=2216 */ {457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2216_l1}, +/*h(2054)=2217 */ {2054, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2217_l1}, +/*h(3651)=2218 */ {3651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2218_l1}, +/*h(12013)=2219 */ {12013, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2219_l1}, +/*h(16194)=2220 */ {16194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2220_l1}, +/*h(13610)=2221 */ {13610, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12623)=2223 */ {12623, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2223_l1}, +/*h(3274)=2224 */ {3274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15817)=2226 */ {15817, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2226_l1}, +/*h(2287)=2227 */ {2287, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12246)=2229 */ {12246, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2229_l1}, +/*h(13843)=2230 */ {13843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8675)=2232 */ {8675, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2232_l1}, +/*h(1910)=2233 */ {1910, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2233_l1}, +/*h(14453)=2234 */ {14453, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2234_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16050)=2236 */ {16050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2236_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8298)=2238 */ {8298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2238_l1}, +/*h(5714)=2239 */ {5714, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2239_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10505)=2243 */ {10505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2243_l1}, +/*h(7921)=2244 */ {7921, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13699)=2246 */ {13699, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2246_l1}, +/*h(169)=2247 */ {169, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2247_l1}, +/*h(1766)=2248 */ {1766, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2248_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3363)=2250 */ {3363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2250_l1}, +/*h(11725)=2251 */ {11725, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2251_l1}, +/*h(13322)=2252 */ {13322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2252_l1}, +/*h(10738)=2253 */ {10738, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2253_l1}, +/*h(1389)=2254 */ {1389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2254_l1}, +/*h(5570)=2255 */ {5570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2255_l1}, +/*h(402)=2256 */ {402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2256_l1}, +/*h(15529)=2257 */ {15529, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14542)=2259 */ {14542, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2259_l1}, +/*h(7777)=2260 */ {7777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2260_l1}, +/*h(5193)=2261 */ {5193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2261_l1}, +/*h(13555)=2262 */ {13555, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2262_l1}, +/*h(8387)=2263 */ {8387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2263_l1}, +/*h(5803)=2264 */ {5803, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2264_l1}, +/*h(14165)=2265 */ {14165, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2265_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15762)=2267 */ {15762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2267_l1}, +/*h(6413)=2268 */ {6413, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2268_l1}, +/*h(8010)=2269 */ {8010, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2269_l1}, +/*h(5426)=2270 */ {5426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2270_l1}, +/*h(9607)=2271 */ {9607, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2271_l1}, +/*h(258)=2272 */ {258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2272_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10217)=2274 */ {10217, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2274_l1}, +/*h(7633)=2275 */ {7633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2275_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13411)=2277 */ {13411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2277_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8243)=2279 */ {8243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14021)=2281 */ {14021, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2281_l1}, +/*h(491)=2282 */ {491, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2282_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10450)=2284 */ {10450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2284_l1}, +/*h(12047)=2285 */ {12047, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2285_l1}, +/*h(9463)=2286 */ {9463, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4295)=2288 */ {4295, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11670)=2291 */ {11670, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2291_l1}, +/*h(15851)=2292 */ {15851, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2292_l1}, +/*h(2321)=2293 */ {2321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5515)=2295 */ {5515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15474)=2298 */ {15474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2298_l1}, +/*h(6125)=2299 */ {6125, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2299_l1}, +/*h(14487)=2300 */ {14487, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2300_l1}, +/*h(7722)=2301 */ {7722, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2301_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12513)=2305 */ {12513, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2305_l1}, +/*h(9929)=2306 */ {9929, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2306_l1}, +/*h(11526)=2307 */ {11526, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2307_l1}, +/*h(2177)=2308 */ {2177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2308_l1}, +/*h(6358)=2309 */ {6358, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2309_l1}, +/*h(7955)=2310 */ {7955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13733)=2312 */ {13733, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2312_l1}, +/*h(203)=2313 */ {203, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2313_l1}, +/*h(12746)=2314 */ {12746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2314_l1}, +/*h(10162)=2315 */ {10162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2315_l1}, +/*h(3397)=2316 */ {3397, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2316_l1}, +/*h(11759)=2317 */ {11759, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4007)=2319 */ {4007, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2319_l1}, +/*h(12369)=2320 */ {12369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7201)=2322 */ {7201, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2322_l1}, +/*h(15563)=2323 */ {15563, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2323_l1}, +/*h(6214)=2324 */ {6214, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2324_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7811)=2326 */ {7811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2326_l1}, +/*h(5227)=2327 */ {5227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2327_l1}, +/*h(13589)=2328 */ {13589, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2328_l1}, +/*h(8421)=2329 */ {8421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2329_l1}, +/*h(5837)=2330 */ {5837, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2330_l1}, +/*h(14199)=2331 */ {14199, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2331_l1}, +/*h(7434)=2332 */ {7434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6447)=2334 */ {6447, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2334_l1}, +/*h(3863)=2335 */ {3863, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2335_l1}, +/*h(12225)=2336 */ {12225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2336_l1}, +/*h(9641)=2337 */ {9641, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2337_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1889)=2339 */ {1889, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2339_l1}, +/*h(10251)=2340 */ {10251, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2340_l1}, +/*h(7667)=2341 */ {7667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2341_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2499)=2343 */ {2499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12458)=2346 */ {12458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2346_l1}, +/*h(14055)=2347 */ {14055, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2347_l1}, +/*h(11471)=2348 */ {11471, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2348_l1}, +/*h(2122)=2349 */ {2122, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12081)=2351 */ {12081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2351_l1}, +/*h(16262)=2352 */ {16262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2352_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4329)=2354 */ {4329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2354_l1}, +/*h(1745)=2355 */ {1745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2355_l1}, +/*h(3342)=2356 */ {3342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2355)=2359 */ {2355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5549)=2361 */ {5549, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2361_l1}, +/*h(9730)=2362 */ {9730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2362_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4562)=2364 */ {4562, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2364_l1}, +/*h(6159)=2365 */ {6159, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2365_l1}, +/*h(3575)=2366 */ {3575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2366_l1}, +/*h(11937)=2367 */ {11937, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2367_l1}, +/*h(16118)=2368 */ {16118, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2368_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1601)=2371 */ {1601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2371_l1}, +/*h(9963)=2372 */ {9963, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2211)=2374 */ {2211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14754)=2376 */ {14754, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2376_l1}, +/*h(12170)=2377 */ {12170, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(237)=2379 */ {237, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2379_l1}, +/*h(8599)=2380 */ {8599, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3431)=2382 */ {3431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2382_l1}, +/*h(11793)=2383 */ {11793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2383_l1}, +/*h(6625)=2384 */ {6625, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2384_l1}, +/*h(4041)=2385 */ {4041, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2385_l1}, +/*h(12403)=2386 */ {12403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2386_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(470)=2388 */ {470, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2388_l1}, +/*h(15597)=2389 */ {15597, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2389_l1}, +/*h(2067)=2390 */ {2067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2390_l1}, +/*h(14610)=2391 */ {14610, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2391_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9442)=2393 */ {9442, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2393_l1}, +/*h(13623)=2394 */ {13623, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2394_l1}, +/*h(8455)=2395 */ {8455, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2395_l1}, +/*h(5871)=2396 */ {5871, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2396_l1}, +/*h(3287)=2397 */ {3287, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2397_l1}, +/*h(11649)=2398 */ {11649, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2398_l1}, +/*h(15830)=2399 */ {15830, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8078)=2401 */ {8078, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2401_l1}, +/*h(12259)=2402 */ {12259, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2402_l1}, +/*h(9675)=2403 */ {9675, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2403_l1}, +/*h(326)=2404 */ {326, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2404_l1}, +/*h(1923)=2405 */ {1923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14466)=2407 */ {14466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2407_l1}, +/*h(11882)=2408 */ {11882, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2408_l1}, +/*h(2533)=2409 */ {2533, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2409_l1}, +/*h(4130)=2410 */ {4130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2410_l1}, +/*h(8311)=2411 */ {8311, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2411_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14089)=2413 */ {14089, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2413_l1}, +/*h(11505)=2414 */ {11505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2414_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6337)=2416 */ {6337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2416_l1}, +/*h(1169)=2417 */ {1169, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2417_l1}, +/*h(12115)=2418 */ {12115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2418_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4363)=2420 */ {4363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2420_l1}, +/*h(1779)=2421 */ {1779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2421_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14322)=2423 */ {14322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2423_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6570)=2425 */ {6570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2425_l1}, +/*h(3986)=2426 */ {3986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2426_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11361)=2429 */ {11361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2429_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6193)=2431 */ {6193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2431_l1}, +/*h(10374)=2432 */ {10374, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2432_l1}, +/*h(11971)=2433 */ {11971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2433_l1}, +/*h(9387)=2434 */ {9387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2434_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1635)=2437 */ {1635, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2437_l1}, +/*h(14178)=2438 */ {14178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2438_l1}, +/*h(7413)=2439 */ {7413, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2439_l1}, +/*h(2245)=2440 */ {2245, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2440_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3842)=2442 */ {3842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2442_l1}, +/*h(1258)=2443 */ {1258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2443_l1}, +/*h(13801)=2444 */ {13801, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2444_l1}, +/*h(271)=2445 */ {271, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10230)=2447 */ {10230, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2447_l1}, +/*h(14411)=2448 */ {14411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2448_l1}, +/*h(11827)=2449 */ {11827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2449_l1}, +/*h(2478)=2450 */ {2478, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2450_l1}, +/*h(4075)=2451 */ {4075, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2451_l1}, +/*h(12437)=2452 */ {12437, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2452_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14034)=2454 */ {14034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2454_l1}, +/*h(15631)=2455 */ {15631, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2455_l1}, +/*h(6282)=2456 */ {6282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2456_l1}, +/*h(3698)=2457 */ {3698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2457_l1}, +/*h(7879)=2458 */ {7879, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2458_l1}, +/*h(16241)=2459 */ {16241, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8489)=2461 */ {8489, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2461_l1}, +/*h(5905)=2462 */ {5905, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11683)=2464 */ {11683, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2464_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9709)=2469 */ {9709, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2469_l1}, +/*h(11306)=2470 */ {11306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2470_l1}, +/*h(1957)=2471 */ {1957, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3554)=2473 */ {3554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2473_l1}, +/*h(16097)=2474 */ {16097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2474_l1}, +/*h(13513)=2475 */ {13513, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2475_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12526)=2478 */ {12526, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2478_l1}, +/*h(3177)=2479 */ {3177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2479_l1}, +/*h(11539)=2480 */ {11539, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2480_l1}, +/*h(2190)=2481 */ {2190, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2481_l1}, +/*h(3787)=2482 */ {3787, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2482_l1}, +/*h(14733)=2483 */ {14733, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2483_l1}, +/*h(12149)=2484 */ {12149, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2484_l1}, +/*h(13746)=2485 */ {13746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2485_l1}, +/*h(4397)=2486 */ {4397, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2486_l1}, +/*h(12759)=2487 */ {12759, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2487_l1}, +/*h(5994)=2488 */ {5994, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2488_l1}, +/*h(7591)=2489 */ {7591, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2489_l1}, +/*h(15953)=2490 */ {15953, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8201)=2493 */ {8201, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2493_l1}, +/*h(5617)=2494 */ {5617, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2494_l1}, +/*h(449)=2495 */ {449, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2495_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6227)=2497 */ {6227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2497_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12005)=2499 */ {12005, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2499_l1}, +/*h(9421)=2500 */ {9421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2500_l1}, +/*h(13602)=2501 */ {13602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2501_l1}, +/*h(8434)=2502 */ {8434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2502_l1}, +/*h(12615)=2503 */ {12615, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2503_l1}, +/*h(3266)=2504 */ {3266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2504_l1}, +/*h(7447)=2505 */ {7447, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2505_l1}, +/*h(2279)=2506 */ {2279, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2506_l1}, +/*h(10641)=2507 */ {10641, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2507_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12238)=2509 */ {12238, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2509_l1}, +/*h(13835)=2510 */ {13835, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2510_l1}, +/*h(4486)=2511 */ {4486, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2511_l1}, +/*h(1902)=2512 */ {1902, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2512_l1}, +/*h(6083)=2513 */ {6083, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2513_l1}, +/*h(3499)=2514 */ {3499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2514_l1}, +/*h(16042)=2515 */ {16042, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2515_l1}, +/*h(13458)=2516 */ {13458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2516_l1}, +/*h(4109)=2517 */ {4109, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2517_l1}, +/*h(1525)=2518 */ {1525, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2518_l1}, +/*h(5706)=2519 */ {5706, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2519_l1}, +/*h(3122)=2520 */ {3122, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2520_l1}, +/*h(15665)=2521 */ {15665, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2521_l1}, +/*h(2135)=2522 */ {2135, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2522_l1}, +/*h(14678)=2523 */ {14678, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2523_l1}, +/*h(7913)=2524 */ {7913, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2524_l1}, +/*h(5329)=2525 */ {5329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2525_l1}, +/*h(161)=2526 */ {161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2526_l1}, +/*h(4342)=2527 */ {4342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2527_l1}, +/*h(5939)=2528 */ {5939, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11717)=2530 */ {11717, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2530_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13314)=2532 */ {13314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2532_l1}, +/*h(8146)=2533 */ {8146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2533_l1}, +/*h(1381)=2534 */ {1381, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2534_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(394)=2536 */ {394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2536_l1}, +/*h(15521)=2537 */ {15521, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2537_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14534)=2539 */ {14534, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2539_l1}, +/*h(5185)=2540 */ {5185, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2540_l1}, +/*h(13547)=2541 */ {13547, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2541_l1}, +/*h(17)=2542 */ {17, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5795)=2544 */ {5795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2544_l1}, +/*h(3211)=2545 */ {3211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2545_l1}, +/*h(15754)=2546 */ {15754, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6405)=2548 */ {6405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2548_l1}, +/*h(8002)=2549 */ {8002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2549_l1}, +/*h(12183)=2550 */ {12183, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2550_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15377)=2552 */ {15377, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2552_l1}, +/*h(1847)=2553 */ {1847, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2553_l1}, +/*h(10209)=2554 */ {10209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2554_l1}, +/*h(7625)=2555 */ {7625, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2555_l1}, +/*h(15987)=2556 */ {15987, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2556_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4054)=2558 */ {4054, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2558_l1}, +/*h(8235)=2559 */ {8235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2559_l1}, +/*h(5651)=2560 */ {5651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2560_l1}, +/*h(483)=2561 */ {483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2561_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10442)=2564 */ {10442, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2564_l1}, +/*h(12039)=2565 */ {12039, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2565_l1}, +/*h(9455)=2566 */ {9455, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2566_l1}, +/*h(106)=2567 */ {106, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2567_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10065)=2570 */ {10065, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2570_l1}, +/*h(11662)=2571 */ {11662, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2571_l1}, +/*h(15843)=2572 */ {15843, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2572_l1}, +/*h(10675)=2573 */ {10675, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2573_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5507)=2575 */ {5507, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2575_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15466)=2578 */ {15466, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2578_l1}, +/*h(6117)=2579 */ {6117, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2579_l1}, +/*h(14479)=2580 */ {14479, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2580_l1}, +/*h(5130)=2581 */ {5130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2581_l1}, +/*h(2546)=2582 */ {2546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2582_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9921)=2585 */ {9921, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2585_l1}, +/*h(14102)=2586 */ {14102, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2586_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6350)=2588 */ {6350, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2588_l1}, +/*h(10531)=2589 */ {10531, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2589_l1}, +/*h(7947)=2590 */ {7947, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2590_l1}, +/*h(5363)=2591 */ {5363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2591_l1}, +/*h(195)=2592 */ {195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2592_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5973)=2594 */ {5973, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2594_l1}, +/*h(10154)=2595 */ {10154, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2595_l1}, +/*h(11751)=2596 */ {11751, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2596_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6583)=2598 */ {6583, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12361)=2600 */ {12361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2600_l1}, +/*h(9777)=2601 */ {9777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2601_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2025)=2603 */ {2025, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2603_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10387)=2605 */ {10387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2605_l1}, +/*h(5219)=2606 */ {5219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2606_l1}, +/*h(13581)=2607 */ {13581, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2607_l1}, +/*h(51)=2608 */ {51, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2608_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5829)=2610 */ {5829, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2610_l1}, +/*h(7426)=2611 */ {7426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2611_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2258)=2613 */ {2258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2613_l1}, +/*h(6439)=2614 */ {6439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2614_l1}, +/*h(1271)=2615 */ {1271, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2615_l1}, +/*h(9633)=2616 */ {9633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2616_l1}, +/*h(13814)=2617 */ {13814, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2617_l1}, +/*h(15411)=2618 */ {15411, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2618_l1}, +/*h(8646)=2619 */ {8646, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2619_l1}, +/*h(10243)=2620 */ {10243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2620_l1}, +/*h(7659)=2621 */ {7659, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2621_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12450)=2625 */ {12450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2625_l1}, +/*h(9866)=2626 */ {9866, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2626_l1}, +/*h(7282)=2627 */ {7282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2627_l1}, +/*h(11463)=2628 */ {11463, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2628_l1}, +/*h(2114)=2629 */ {2114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2629_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12073)=2631 */ {12073, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2631_l1}, +/*h(9489)=2632 */ {9489, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2632_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4321)=2634 */ {4321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2634_l1}, +/*h(1737)=2635 */ {1737, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2635_l1}, +/*h(10099)=2636 */ {10099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2636_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2347)=2638 */ {2347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2638_l1}, +/*h(10709)=2639 */ {10709, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2639_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12306)=2641 */ {12306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2641_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4554)=2643 */ {4554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2643_l1}, +/*h(1970)=2644 */ {1970, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2644_l1}, +/*h(6151)=2645 */ {6151, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2645_l1}, +/*h(3567)=2646 */ {3567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2646_l1}, +/*h(16110)=2647 */ {16110, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2647_l1}, +/*h(13526)=2648 */ {13526, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2648_l1}, +/*h(4177)=2649 */ {4177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2649_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9955)=2651 */ {9955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2651_l1}, +/*h(7371)=2652 */ {7371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12162)=2656 */ {12162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2656_l1}, +/*h(16343)=2657 */ {16343, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2657_l1}, +/*h(229)=2658 */ {229, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2658_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6007)=2660 */ {6007, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2660_l1}, +/*h(14369)=2661 */ {14369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2661_l1}, +/*h(11785)=2662 */ {11785, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2662_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4033)=2665 */ {4033, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2665_l1}, +/*h(12395)=2666 */ {12395, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2666_l1}, +/*h(9811)=2667 */ {9811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2667_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15589)=2669 */ {15589, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2669_l1}, +/*h(2059)=2670 */ {2059, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2670_l1}, +/*h(14602)=2671 */ {14602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2671_l1}, +/*h(12018)=2672 */ {12018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2672_l1}, +/*h(13615)=2673 */ {13615, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2673_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4266)=2675 */ {4266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2675_l1}, +/*h(5863)=2676 */ {5863, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2676_l1}, +/*h(3279)=2677 */ {3279, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2677_l1}, +/*h(15822)=2678 */ {15822, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2678_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14835)=2681 */ {14835, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2681_l1}, +/*h(9667)=2682 */ {9667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2682_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4499)=2684 */ {4499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9290)=2688 */ {9290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2688_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8303)=2691 */ {8303, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2691_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14081)=2693 */ {14081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2693_l1}, +/*h(11497)=2694 */ {11497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2694_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10510)=2696 */ {10510, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2696_l1}, +/*h(12107)=2697 */ {12107, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2697_l1}, +/*h(9523)=2698 */ {9523, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2698_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4355)=2700 */ {4355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2700_l1}, +/*h(1771)=2701 */ {1771, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2701_l1}, +/*h(14314)=2702 */ {14314, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2702_l1}, +/*h(11730)=2703 */ {11730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2703_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10743)=2705 */ {10743, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2705_l1}, +/*h(3978)=2706 */ {3978, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2706_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13937)=2708 */ {13937, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2708_l1}, +/*h(407)=2709 */ {407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2709_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6185)=2711 */ {6185, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2711_l1}, +/*h(14547)=2712 */ {14547, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2712_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9379)=2714 */ {9379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2714_l1}, +/*h(4211)=2715 */ {4211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9989)=2717 */ {9989, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2717_l1}, +/*h(7405)=2718 */ {7405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2718_l1}, +/*h(15767)=2719 */ {15767, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2719_l1}, +/*h(6418)=2720 */ {6418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2720_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1250)=2722 */ {1250, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2722_l1}, +/*h(5431)=2723 */ {5431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2723_l1}, +/*h(13793)=2724 */ {13793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2724_l1}, +/*h(263)=2725 */ {263, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2725_l1}, +/*h(8625)=2726 */ {8625, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2726_l1}, +/*h(10222)=2727 */ {10222, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2727_l1}, +/*h(14403)=2728 */ {14403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2728_l1}, +/*h(9235)=2729 */ {9235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2729_l1}, +/*h(2470)=2730 */ {2470, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2730_l1}, +/*h(4067)=2731 */ {4067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2731_l1}, +/*h(12429)=2732 */ {12429, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2732_l1}, +/*h(14026)=2733 */ {14026, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2733_l1}, +/*h(11442)=2734 */ {11442, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2734_l1}, +/*h(15623)=2735 */ {15623, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2735_l1}, +/*h(6274)=2736 */ {6274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2736_l1}, +/*h(10455)=2737 */ {10455, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2737_l1}, +/*h(1106)=2738 */ {1106, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2738_l1}, +/*h(16233)=2739 */ {16233, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2739_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8481)=2741 */ {8481, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2741_l1}, +/*h(5897)=2742 */ {5897, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2742_l1}, +/*h(3313)=2743 */ {3313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2743_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2326)=2745 */ {2326, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2745_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3923)=2747 */ {3923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9701)=2749 */ {9701, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2749_l1}, +/*h(11298)=2750 */ {11298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6130)=2752 */ {6130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2752_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13505)=2755 */ {13505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2755_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12518)=2757 */ {12518, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2757_l1}, +/*h(9934)=2758 */ {9934, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2758_l1}, +/*h(14115)=2759 */ {14115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2759_l1}, +/*h(11531)=2760 */ {11531, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2760_l1}, +/*h(2182)=2761 */ {2182, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2761_l1}, +/*h(3779)=2762 */ {3779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2762_l1}, +/*h(1195)=2763 */ {1195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2763_l1}, +/*h(16322)=2764 */ {16322, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2764_l1}, +/*h(13738)=2765 */ {13738, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2765_l1}, +/*h(4389)=2766 */ {4389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2766_l1}, +/*h(5986)=2767 */ {5986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2767_l1}, +/*h(10167)=2768 */ {10167, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2768_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15945)=2770 */ {15945, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2770_l1}, +/*h(13361)=2771 */ {13361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2771_l1}, +/*h(8193)=2772 */ {8193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2772_l1}, +/*h(5609)=2773 */ {5609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2773_l1}, +/*h(13971)=2774 */ {13971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2774_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2038)=2776 */ {2038, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2776_l1}, +/*h(6219)=2777 */ {6219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2777_l1}, +/*h(14581)=2778 */ {14581, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2778_l1}, +/*h(16178)=2779 */ {16178, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2779_l1}, +/*h(9413)=2780 */ {9413, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2780_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8426)=2782 */ {8426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2782_l1}, +/*h(5842)=2783 */ {5842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2783_l1}, +/*h(7439)=2784 */ {7439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2784_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10633)=2787 */ {10633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2787_l1}, +/*h(8049)=2788 */ {8049, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2788_l1}, +/*h(9646)=2789 */ {9646, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2789_l1}, +/*h(13827)=2790 */ {13827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2790_l1}, +/*h(297)=2791 */ {297, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2791_l1}, +/*h(1894)=2792 */ {1894, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2792_l1}, +/*h(3491)=2793 */ {3491, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2793_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16034)=2795 */ {16034, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2795_l1}, +/*h(13450)=2796 */ {13450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2796_l1}, +/*h(4101)=2797 */ {4101, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2797_l1}, +/*h(5698)=2798 */ {5698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2798_l1}, +/*h(3114)=2799 */ {3114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2799_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15657)=2801 */ {15657, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2801_l1}, +/*h(2127)=2802 */ {2127, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2802_l1}, +/*h(14670)=2803 */ {14670, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2803_l1}, +/*h(5321)=2804 */ {5321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2804_l1}, +/*h(16267)=2805 */ {16267, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2805_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4334)=2807 */ {4334, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2807_l1}, +/*h(1750)=2808 */ {1750, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2808_l1}, +/*h(14293)=2809 */ {14293, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2809_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15890)=2811 */ {15890, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2811_l1}, +/*h(10722)=2812 */ {10722, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2812_l1}, +/*h(8138)=2813 */ {8138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2813_l1}, +/*h(5554)=2814 */ {5554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2814_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4567)=2816 */ {4567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2816_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10345)=2818 */ {10345, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2818_l1}, +/*h(7761)=2819 */ {7761, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2819_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13539)=2821 */ {13539, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2821_l1}, +/*h(9)=2822 */ {9, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2822_l1}, +/*h(8371)=2823 */ {8371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2823_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3203)=2825 */ {3203, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2825_l1}, +/*h(15746)=2826 */ {15746, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2826_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3813)=2828 */ {3813, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2828_l1}, +/*h(1229)=2829 */ {1229, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2829_l1}, +/*h(5410)=2830 */ {5410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2830_l1}, +/*h(242)=2831 */ {242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2831_l1}, +/*h(15369)=2832 */ {15369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2832_l1}, +/*h(12785)=2833 */ {12785, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2833_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7617)=2835 */ {7617, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2835_l1}, +/*h(15979)=2836 */ {15979, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2836_l1}, +/*h(13395)=2837 */ {13395, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2837_l1}, +/*h(4046)=2838 */ {4046, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2838_l1}, +/*h(5643)=2839 */ {5643, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15602)=2842 */ {15602, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2842_l1}, +/*h(10434)=2843 */ {10434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2843_l1}, +/*h(14615)=2844 */ {14615, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2844_l1}, +/*h(5266)=2845 */ {5266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2845_l1}, +/*h(9447)=2846 */ {9447, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2846_l1}, +/*h(98)=2847 */ {98, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2847_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10057)=2849 */ {10057, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2849_l1}, +/*h(7473)=2850 */ {7473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2850_l1}, +/*h(11654)=2851 */ {11654, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2851_l1}, +/*h(2305)=2852 */ {2305, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2852_l1}, +/*h(10667)=2853 */ {10667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2853_l1}, +/*h(8083)=2854 */ {8083, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15458)=2857 */ {15458, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2857_l1}, +/*h(8693)=2858 */ {8693, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2858_l1}, +/*h(3525)=2859 */ {3525, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2859_l1}, +/*h(14471)=2860 */ {14471, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2860_l1}, +/*h(5122)=2861 */ {5122, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2861_l1}, +/*h(2538)=2862 */ {2538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2862_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12497)=2864 */ {12497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2864_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11510)=2866 */ {11510, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2866_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6342)=2868 */ {6342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2868_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5355)=2870 */ {5355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2870_l1}, +/*h(13717)=2871 */ {13717, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2871_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5965)=2874 */ {5965, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2874_l1}, +/*h(14327)=2875 */ {14327, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2875_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6575)=2878 */ {6575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2878_l1}, +/*h(3991)=2879 */ {3991, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2879_l1}, +/*h(12353)=2880 */ {12353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2880_l1}, +/*h(9769)=2881 */ {9769, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2881_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2017)=2883 */ {2017, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2883_l1}, +/*h(10379)=2884 */ {10379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2884_l1}, +/*h(7795)=2885 */ {7795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2885_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13573)=2887 */ {13573, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2887_l1}, +/*h(43)=2888 */ {43, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2888_l1}, +/*h(8405)=2889 */ {8405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2889_l1}, +/*h(10002)=2890 */ {10002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2890_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2250)=2893 */ {2250, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2893_l1}, +/*h(14793)=2894 */ {14793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2894_l1}, +/*h(1263)=2895 */ {1263, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2895_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15403)=2898 */ {15403, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2898_l1}, +/*h(1873)=2899 */ {1873, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2899_l1}, +/*h(3470)=2900 */ {3470, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2900_l1}, +/*h(7651)=2901 */ {7651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2901_l1}, +/*h(2483)=2902 */ {2483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2902_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14039)=2906 */ {14039, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2906_l1}, +/*h(7274)=2907 */ {7274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2907_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16246)=2911 */ {16246, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2911_l1}, +/*h(9481)=2912 */ {9481, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2912_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1729)=2914 */ {1729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2914_l1}, +/*h(10091)=2915 */ {10091, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2339)=2918 */ {2339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2918_l1}, +/*h(10701)=2919 */ {10701, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2919_l1}, +/*h(8117)=2920 */ {8117, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2920_l1}, +/*h(9714)=2921 */ {9714, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2921_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4546)=2923 */ {4546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2923_l1}, +/*h(1962)=2924 */ {1962, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2924_l1}, +/*h(3559)=2925 */ {3559, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2925_l1}, +/*h(14505)=2926 */ {14505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2926_l1}, +/*h(16102)=2927 */ {16102, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2927_l1}, +/*h(13518)=2928 */ {13518, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2928_l1}, +/*h(4169)=2929 */ {4169, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2929_l1}, +/*h(12531)=2930 */ {12531, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2930_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7363)=2932 */ {7363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2195)=2934 */ {2195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2934_l1}, +/*h(14738)=2935 */ {14738, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2935_l1}, +/*h(5389)=2936 */ {5389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2936_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13751)=2938 */ {13751, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2938_l1}, +/*h(8583)=2939 */ {8583, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2939_l1}, +/*h(5999)=2940 */ {5999, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2940_l1}, +/*h(3415)=2941 */ {3415, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2941_l1}, +/*h(11777)=2942 */ {11777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2942_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6609)=2944 */ {6609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2944_l1}, +/*h(8206)=2945 */ {8206, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2945_l1}, +/*h(12387)=2946 */ {12387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2946_l1}, +/*h(9803)=2947 */ {9803, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2947_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2051)=2949 */ {2051, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2949_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14594)=2951 */ {14594, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2951_l1}, +/*h(12010)=2952 */ {12010, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2952_l1}, +/*h(9426)=2953 */ {9426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2953_l1}, +/*h(77)=2954 */ {77, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2954_l1}, +/*h(8439)=2955 */ {8439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2955_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3271)=2957 */ {3271, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2957_l1}, +/*h(15814)=2958 */ {15814, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2958_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14827)=2960 */ {14827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2960_l1}, +/*h(12243)=2961 */ {12243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2961_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(310)=2963 */ {310, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2963_l1}, +/*h(4491)=2964 */ {4491, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2964_l1}, +/*h(1907)=2965 */ {1907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2965_l1}, +/*h(14450)=2966 */ {14450, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2517)=2968 */ {2517, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2968_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8295)=2970 */ {8295, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2970_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11489)=2973 */ {11489, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2973_l1}, +/*h(15670)=2974 */ {15670, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2974_l1}, +/*h(6321)=2975 */ {6321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2975_l1}, +/*h(7918)=2976 */ {7918, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2976_l1}, +/*h(12099)=2977 */ {12099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2977_l1}, +/*h(9515)=2978 */ {9515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2978_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1763)=2980 */ {1763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2980_l1}, +/*h(10125)=2981 */ {10125, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2981_l1}, +/*h(14306)=2982 */ {14306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2982_l1}, +/*h(11722)=2983 */ {11722, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2983_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10735)=2985 */ {10735, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2985_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13929)=2988 */ {13929, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2988_l1}, +/*h(11345)=2989 */ {11345, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2989_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10358)=2991 */ {10358, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2991_l1}, +/*h(14539)=2992 */ {14539, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2992_l1}, +/*h(11955)=2993 */ {11955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2993_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22)=2995 */ {22, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2995_l1}, +/*h(1619)=2996 */ {1619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2996_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14162)=2998 */ {14162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2998_l1}, +/*h(15759)=2999 */ {15759, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_2999_l1}, +/*h(6410)=3000 */ {6410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3000_l1}, +/*h(3826)=3001 */ {3826, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3001_l1}, +/*h(5423)=3002 */ {5423, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3002_l1}, +/*h(16369)=3003 */ {16369, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3003_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8617)=3005 */ {8617, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3005_l1}, +/*h(6033)=3006 */ {6033, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3006_l1}, +/*h(10214)=3007 */ {10214, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3007_l1}, +/*h(11811)=3008 */ {11811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3008_l1}, +/*h(9227)=3009 */ {9227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3009_l1}, +/*h(6643)=3010 */ {6643, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3010_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12421)=3012 */ {12421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3012_l1}, +/*h(14018)=3013 */ {14018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3013_l1}, +/*h(11434)=3014 */ {11434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3014_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10447)=3016 */ {10447, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3016_l1}, +/*h(3682)=3017 */ {3682, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3017_l1}, +/*h(16225)=3018 */ {16225, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3018_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10070)=3022 */ {10070, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3022_l1}, +/*h(3305)=3023 */ {3305, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3023_l1}, +/*h(11667)=3024 */ {11667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3024_l1}, +/*h(2318)=3025 */ {2318, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3025_l1}, +/*h(3915)=3026 */ {3915, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3026_l1}, +/*h(12277)=3027 */ {12277, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13874)=3029 */ {13874, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3029_l1}, +/*h(4525)=3030 */ {4525, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3030_l1}, +/*h(6122)=3031 */ {6122, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3031_l1}, +/*h(3538)=3032 */ {3538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3032_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16081)=3034 */ {16081, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3034_l1}, +/*h(2551)=3035 */ {2551, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3035_l1}, +/*h(8329)=3036 */ {8329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3036_l1}, +/*h(5745)=3037 */ {5745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3037_l1}, +/*h(9926)=3038 */ {9926, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3038_l1}, +/*h(11523)=3039 */ {11523, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3039_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6355)=3041 */ {6355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3041_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1187)=3043 */ {1187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3043_l1}, +/*h(13730)=3044 */ {13730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3044_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1797)=3046 */ {1797, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3046_l1}, +/*h(12743)=3047 */ {12743, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3047_l1}, +/*h(7575)=3048 */ {7575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3048_l1}, +/*h(15937)=3049 */ {15937, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3049_l1}, +/*h(13353)=3050 */ {13353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3050_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5601)=3053 */ {5601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3053_l1}, +/*h(13963)=3054 */ {13963, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3054_l1}, +/*h(11379)=3055 */ {11379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3055_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6211)=3057 */ {6211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3057_l1}, +/*h(14573)=3058 */ {14573, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3058_l1}, +/*h(11989)=3059 */ {11989, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3059_l1}, +/*h(13586)=3060 */ {13586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3060_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8418)=3062 */ {8418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3062_l1}, +/*h(5834)=3063 */ {5834, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3063_l1}, +/*h(7431)=3064 */ {7431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3064_l1}, +/*h(15793)=3065 */ {15793, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3065_l1}, +/*h(2263)=3066 */ {2263, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3066_l1}, +/*h(14806)=3067 */ {14806, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3067_l1}, +/*h(8041)=3068 */ {8041, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3068_l1}, +/*h(9638)=3069 */ {9638, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3069_l1}, +/*h(289)=3070 */ {289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3070_l1}, +/*h(8651)=3071 */ {8651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3071_l1}, +/*h(6067)=3072 */ {6067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3072_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13442)=3076 */ {13442, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3076_l1}, +/*h(8274)=3077 */ {8274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3077_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3106)=3079 */ {3106, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3079_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2119)=3081 */ {2119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3081_l1}, +/*h(10481)=3082 */ {10481, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3082_l1}, +/*h(14662)=3083 */ {14662, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3083_l1}, +/*h(5313)=3084 */ {5313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3084_l1}, +/*h(9494)=3085 */ {9494, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3085_l1}, +/*h(4326)=3086 */ {4326, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3086_l1}, +/*h(1742)=3087 */ {1742, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3087_l1}, +/*h(5923)=3088 */ {5923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3088_l1}, +/*h(3339)=3089 */ {3339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3089_l1}, +/*h(15882)=3090 */ {15882, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3090_l1}, +/*h(6533)=3091 */ {6533, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3091_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1365)=3093 */ {1365, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3093_l1}, +/*h(5546)=3094 */ {5546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3094_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15505)=3096 */ {15505, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3096_l1}, +/*h(1975)=3097 */ {1975, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3097_l1}, +/*h(10337)=3098 */ {10337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3098_l1}, +/*h(7753)=3099 */ {7753, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3099_l1}, +/*h(16115)=3100 */ {16115, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3100_l1}, +/*h(1)=3101 */ {1, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3101_l1}, +/*h(4182)=3102 */ {4182, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3102_l1}, +/*h(5779)=3103 */ {5779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11557)=3105 */ {11557, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6389)=3107 */ {6389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3107_l1}, +/*h(7986)=3108 */ {7986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3108_l1}, +/*h(1221)=3109 */ {1221, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3109_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=3111 */ {234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3111_l1}, +/*h(15361)=3112 */ {15361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3112_l1}, +/*h(12777)=3113 */ {12777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3113_l1}, +/*h(10193)=3114 */ {10193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3114_l1}, +/*h(15971)=3115 */ {15971, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3115_l1}, +/*h(13387)=3116 */ {13387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4038)=3118 */ {4038, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3118_l1}, +/*h(5635)=3119 */ {5635, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(467)=3121 */ {467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14607)=3124 */ {14607, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3124_l1}, +/*h(12023)=3125 */ {12023, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10049)=3129 */ {10049, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3129_l1}, +/*h(14230)=3130 */ {14230, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3130_l1}, +/*h(15827)=3131 */ {15827, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3131_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10659)=3133 */ {10659, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3133_l1}, +/*h(8075)=3134 */ {8075, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8685)=3137 */ {8685, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3137_l1}, +/*h(6101)=3138 */ {6101, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3138_l1}, +/*h(10282)=3139 */ {10282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3139_l1}, +/*h(7698)=3140 */ {7698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3140_l1}, +/*h(2530)=3141 */ {2530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12489)=3144 */ {12489, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3144_l1}, +/*h(14086)=3145 */ {14086, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3145_l1}, +/*h(11502)=3146 */ {11502, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3146_l1}, +/*h(2153)=3147 */ {2153, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3147_l1}, +/*h(10515)=3148 */ {10515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5347)=3150 */ {5347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3150_l1}, +/*h(13709)=3151 */ {13709, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3151_l1}, +/*h(179)=3152 */ {179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3152_l1}, +/*h(12722)=3153 */ {12722, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3153_l1}, +/*h(5957)=3154 */ {5957, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3154_l1}, +/*h(7554)=3155 */ {7554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3155_l1}, +/*h(11735)=3156 */ {11735, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3156_l1}, +/*h(6567)=3157 */ {6567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3157_l1}, +/*h(3983)=3158 */ {3983, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3158_l1}, +/*h(1399)=3159 */ {1399, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3159_l1}, +/*h(9761)=3160 */ {9761, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3160_l1}, +/*h(7177)=3161 */ {7177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3161_l1}, +/*h(4593)=3162 */ {4593, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3162_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10371)=3164 */ {10371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3164_l1}, +/*h(7787)=3165 */ {7787, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3165_l1}, +/*h(5203)=3166 */ {5203, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3166_l1}, +/*h(35)=3167 */ {35, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8397)=3169 */ {8397, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3169_l1}, +/*h(9994)=3170 */ {9994, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3170_l1}, +/*h(7410)=3171 */ {7410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3171_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2242)=3173 */ {2242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3173_l1}, +/*h(14785)=3174 */ {14785, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3174_l1}, +/*h(1255)=3175 */ {1255, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3175_l1}, +/*h(9617)=3176 */ {9617, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1865)=3178 */ {1865, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10227)=3180 */ {10227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2475)=3182 */ {2475, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3182_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12434)=3185 */ {12434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3185_l1}, +/*h(14031)=3186 */ {14031, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3186_l1}, +/*h(501)=3187 */ {501, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3187_l1}, +/*h(2098)=3188 */ {2098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14641)=3190 */ {14641, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3190_l1}, +/*h(9473)=3191 */ {9473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4305)=3193 */ {4305, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3193_l1}, +/*h(8486)=3194 */ {8486, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3194_l1}, +/*h(10083)=3195 */ {10083, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15861)=3197 */ {15861, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10693)=3199 */ {10693, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3199_l1}, +/*h(12290)=3200 */ {12290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3200_l1}, +/*h(9706)=3201 */ {9706, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3201_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6135)=3204 */ {6135, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3204_l1}, +/*h(14497)=3205 */ {14497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3205_l1}, +/*h(11913)=3206 */ {11913, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3206_l1}, +/*h(9329)=3207 */ {9329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3207_l1}, +/*h(13510)=3208 */ {13510, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3208_l1}, +/*h(8342)=3209 */ {8342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3209_l1}, +/*h(12523)=3210 */ {12523, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3210_l1}, +/*h(9939)=3211 */ {9939, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3211_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2187)=3213 */ {2187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3213_l1}, +/*h(10549)=3214 */ {10549, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3214_l1}, +/*h(14730)=3215 */ {14730, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3215_l1}, +/*h(12146)=3216 */ {12146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3216_l1}, +/*h(13743)=3217 */ {13743, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3217_l1}, +/*h(213)=3218 */ {213, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3218_l1}, +/*h(1810)=3219 */ {1810, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3219_l1}, +/*h(5991)=3220 */ {5991, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3220_l1}, +/*h(3407)=3221 */ {3407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6601)=3223 */ {6601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3223_l1}, +/*h(4017)=3224 */ {4017, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3224_l1}, +/*h(8198)=3225 */ {8198, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3225_l1}, +/*h(9795)=3226 */ {9795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3226_l1}, +/*h(7211)=3227 */ {7211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3227_l1}, +/*h(15573)=3228 */ {15573, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3228_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12002)=3231 */ {12002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3231_l1}, +/*h(9418)=3232 */ {9418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3232_l1}, +/*h(69)=3233 */ {69, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8431)=3235 */ {8431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3235_l1}, +/*h(14209)=3236 */ {14209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3236_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14819)=3240 */ {14819, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3240_l1}, +/*h(12235)=3241 */ {12235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3241_l1}, +/*h(9651)=3242 */ {9651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3242_l1}, +/*h(302)=3243 */ {302, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3243_l1}, +/*h(4483)=3244 */ {4483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3244_l1}, +/*h(1899)=3245 */ {1899, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3245_l1}, +/*h(10261)=3246 */ {10261, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3246_l1}, +/*h(11858)=3247 */ {11858, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3247_l1}, +/*h(2509)=3248 */ {2509, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3248_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1522)=3250 */ {1522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14065)=3252 */ {14065, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3252_l1}, +/*h(15662)=3253 */ {15662, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6313)=3255 */ {6313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3255_l1}, +/*h(7910)=3256 */ {7910, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3256_l1}, +/*h(5326)=3257 */ {5326, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4339)=3259 */ {4339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10117)=3261 */ {10117, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11714)=3263 */ {11714, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3263_l1}, +/*h(6546)=3264 */ {6546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3264_l1}, +/*h(10727)=3265 */ {10727, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3265_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5559)=3267 */ {5559, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3267_l1}, +/*h(13921)=3268 */ {13921, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3268_l1}, +/*h(11337)=3269 */ {11337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14531)=3271 */ {14531, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3271_l1}, +/*h(11947)=3272 */ {11947, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3272_l1}, +/*h(9363)=3273 */ {9363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3273_l1}, +/*h(14)=3274 */ {14, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3274_l1}, +/*h(4195)=3275 */ {4195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3275_l1}, +/*h(1611)=3276 */ {1611, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3276_l1}, +/*h(14154)=3277 */ {14154, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3277_l1}, +/*h(11570)=3278 */ {11570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3278_l1}, +/*h(15751)=3279 */ {15751, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3279_l1}, +/*h(6402)=3280 */ {6402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3280_l1}, +/*h(3818)=3281 */ {3818, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3281_l1}, +/*h(16361)=3282 */ {16361, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3282_l1}, +/*h(13777)=3283 */ {13777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3283_l1}, +/*h(247)=3284 */ {247, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3284_l1}, +/*h(8609)=3285 */ {8609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3285_l1}, +/*h(6025)=3286 */ {6025, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3286_l1}, +/*h(14387)=3287 */ {14387, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3287_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9219)=3289 */ {9219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3289_l1}, +/*h(4051)=3290 */ {4051, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15607)=3294 */ {15607, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3294_l1}, +/*h(6258)=3295 */ {6258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3295_l1}, +/*h(10439)=3296 */ {10439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3296_l1}, +/*h(1090)=3297 */ {1090, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3297_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8465)=3301 */ {8465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3301_l1}, +/*h(3297)=3302 */ {3297, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3302_l1}, +/*h(11659)=3303 */ {11659, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2310)=3305 */ {2310, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3305_l1}, +/*h(3907)=3306 */ {3907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3306_l1}, +/*h(12269)=3307 */ {12269, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3307_l1}, +/*h(9685)=3308 */ {9685, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3308_l1}, +/*h(11282)=3309 */ {11282, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3309_l1}, +/*h(4517)=3310 */ {4517, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3310_l1}, +/*h(6114)=3311 */ {6114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3311_l1}, +/*h(3530)=3312 */ {3530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2543)=3314 */ {2543, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3314_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8321)=3316 */ {8321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3316_l1}, +/*h(12502)=3317 */ {12502, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3317_l1}, +/*h(3153)=3318 */ {3153, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6347)=3321 */ {6347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3321_l1}, +/*h(3763)=3322 */ {3763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3322_l1}, +/*h(16306)=3323 */ {16306, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3323_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4373)=3325 */ {4373, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5970)=3327 */ {5970, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3327_l1}, +/*h(7567)=3328 */ {7567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3328_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13345)=3330 */ {13345, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8177)=3332 */ {8177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(425)=3334 */ {425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3334_l1}, +/*h(11371)=3335 */ {11371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14565)=3337 */ {14565, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3337_l1}, +/*h(11981)=3338 */ {11981, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3338_l1}, +/*h(16162)=3339 */ {16162, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3339_l1}, +/*h(13578)=3340 */ {13578, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5826)=3342 */ {5826, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3342_l1}, +/*h(10007)=3343 */ {10007, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2255)=3345 */ {2255, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8033)=3347 */ {8033, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3347_l1}, +/*h(12214)=3348 */ {12214, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3348_l1}, +/*h(13811)=3349 */ {13811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1878)=3351 */ {1878, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3351_l1}, +/*h(6059)=3352 */ {6059, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3352_l1}, +/*h(14421)=3353 */ {14421, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3353_l1}, +/*h(16018)=3354 */ {16018, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4085)=3356 */ {4085, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3356_l1}, +/*h(8266)=3357 */ {8266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3357_l1}, +/*h(5682)=3358 */ {5682, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10473)=3362 */ {10473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3362_l1}, +/*h(7889)=3363 */ {7889, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3363_l1}, +/*h(9486)=3364 */ {9486, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(137)=3366 */ {137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3366_l1}, +/*h(1734)=3367 */ {1734, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3367_l1}, +/*h(3331)=3368 */ {3331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3368_l1}, +/*h(11693)=3369 */ {11693, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3369_l1}, +/*h(15874)=3370 */ {15874, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10706)=3372 */ {10706, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3372_l1}, +/*h(1357)=3373 */ {1357, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3373_l1}, +/*h(9719)=3374 */ {9719, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15497)=3376 */ {15497, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3376_l1}, +/*h(1967)=3377 */ {1967, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7745)=3379 */ {7745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3379_l1}, +/*h(16107)=3380 */ {16107, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4174)=3382 */ {4174, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3382_l1}, +/*h(5771)=3383 */ {5771, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3383_l1}, +/*h(3187)=3384 */ {3187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6381)=3387 */ {6381, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3387_l1}, +/*h(3797)=3388 */ {3797, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3388_l1}, +/*h(5394)=3389 */ {5394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3389_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(226)=3391 */ {226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3391_l1}, +/*h(12769)=3392 */ {12769, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3392_l1}, +/*h(10185)=3393 */ {10185, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3393_l1}, +/*h(7601)=3394 */ {7601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6614)=3396 */ {6614, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3396_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8211)=3398 */ {8211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(459)=3400 */ {459, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3400_l1}, +/*h(15586)=3401 */ {15586, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3401_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14599)=3403 */ {14599, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3403_l1}, +/*h(12015)=3404 */ {12015, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3404_l1}, +/*h(9431)=3405 */ {9431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3405_l1}, +/*h(82)=3406 */ {82, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14222)=3409 */ {14222, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3409_l1}, +/*h(7457)=3410 */ {7457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3410_l1}, +/*h(15819)=3411 */ {15819, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3411_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8067)=3413 */ {8067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3413_l1}, +/*h(1302)=3414 */ {1302, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3414_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8677)=3417 */ {8677, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3417_l1}, +/*h(6093)=3418 */ {6093, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3418_l1}, +/*h(14455)=3419 */ {14455, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4119)=3422 */ {4119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3422_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12481)=3424 */ {12481, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3424_l1}, +/*h(7313)=3425 */ {7313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3425_l1}, +/*h(11494)=3426 */ {11494, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3426_l1}, +/*h(2145)=3427 */ {2145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3427_l1}, +/*h(10507)=3428 */ {10507, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3428_l1}, +/*h(7923)=3429 */ {7923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3429_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13701)=3431 */ {13701, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3431_l1}, +/*h(171)=3432 */ {171, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3432_l1}, +/*h(12714)=3433 */ {12714, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3433_l1}, +/*h(10130)=3434 */ {10130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3434_l1}, +/*h(11727)=3435 */ {11727, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3975)=3438 */ {3975, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3438_l1}, +/*h(1391)=3439 */ {1391, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7169)=3441 */ {7169, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3441_l1}, +/*h(4585)=3442 */ {4585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3442_l1}, +/*h(2001)=3443 */ {2001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3443_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5195)=3445 */ {5195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3445_l1}, +/*h(13557)=3446 */ {13557, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3446_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8389)=3448 */ {8389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14167)=3450 */ {14167, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3450_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6415)=3453 */ {6415, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3453_l1}, +/*h(3831)=3454 */ {3831, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3454_l1}, +/*h(16374)=3455 */ {16374, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3455_l1}, +/*h(9609)=3456 */ {9609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1857)=3458 */ {1857, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3458_l1}, +/*h(10219)=3459 */ {10219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3459_l1}, +/*h(7635)=3460 */ {7635, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3460_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2467)=3462 */ {2467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12426)=3464 */ {12426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3464_l1}, +/*h(9842)=3465 */ {9842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3465_l1}, +/*h(14023)=3466 */ {14023, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3466_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2090)=3468 */ {2090, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3468_l1}, +/*h(14633)=3469 */ {14633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3469_l1}, +/*h(12049)=3470 */ {12049, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3470_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4297)=3473 */ {4297, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3473_l1}, +/*h(5894)=3474 */ {5894, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3474_l1}, +/*h(3310)=3475 */ {3310, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3475_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15853)=3477 */ {15853, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8101)=3479 */ {8101, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3479_l1}, +/*h(5517)=3480 */ {5517, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3480_l1}, +/*h(9698)=3481 */ {9698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4530)=3483 */ {4530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3483_l1}, +/*h(6127)=3484 */ {6127, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3484_l1}, +/*h(3543)=3485 */ {3543, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3485_l1}, +/*h(16086)=3486 */ {16086, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3486_l1}, +/*h(9321)=3487 */ {9321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3487_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8334)=3489 */ {8334, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3489_l1}, +/*h(9931)=3490 */ {9931, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3490_l1}, +/*h(7347)=3491 */ {7347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3491_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2179)=3493 */ {2179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3493_l1}, +/*h(10541)=3494 */ {10541, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3494_l1}, +/*h(14722)=3495 */ {14722, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3495_l1}, +/*h(12138)=3496 */ {12138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3496_l1}, +/*h(13735)=3497 */ {13735, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3497_l1}, +/*h(205)=3498 */ {205, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3498_l1}, +/*h(1802)=3499 */ {1802, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3499_l1}, +/*h(3399)=3500 */ {3399, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3500_l1}, +/*h(11761)=3501 */ {11761, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3501_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6593)=3503 */ {6593, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3503_l1}, +/*h(4009)=3504 */ {4009, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3504_l1}, +/*h(12371)=3505 */ {12371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7203)=3507 */ {7203, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3507_l1}, +/*h(15565)=3508 */ {15565, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3508_l1}, +/*h(2035)=3509 */ {2035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3509_l1}, +/*h(14578)=3510 */ {14578, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9410)=3512 */ {9410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3512_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8423)=3514 */ {8423, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3514_l1}, +/*h(5839)=3515 */ {5839, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15798)=3518 */ {15798, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3518_l1}, +/*h(10630)=3519 */ {10630, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12227)=3521 */ {12227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3521_l1}, +/*h(9643)=3522 */ {9643, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3522_l1}, +/*h(294)=3523 */ {294, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3523_l1}, +/*h(1891)=3524 */ {1891, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3524_l1}, +/*h(10253)=3525 */ {10253, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3525_l1}, +/*h(14434)=3526 */ {14434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3526_l1}, +/*h(11850)=3527 */ {11850, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3527_l1}, +/*h(2501)=3528 */ {2501, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3528_l1}, +/*h(4098)=3529 */ {4098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3529_l1}, +/*h(1514)=3530 */ {1514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3530_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14057)=3532 */ {14057, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3532_l1}, +/*h(11473)=3533 */ {11473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3533_l1}, +/*h(6305)=3534 */ {6305, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3534_l1}, +/*h(10486)=3535 */ {10486, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3535_l1}, +/*h(1137)=3536 */ {1137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3536_l1}, +/*h(5318)=3537 */ {5318, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3537_l1}, +/*h(150)=3538 */ {150, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3538_l1}, +/*h(4331)=3539 */ {4331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3539_l1}, +/*h(1747)=3540 */ {1747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3540_l1}, +/*h(14290)=3541 */ {14290, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3541_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2357)=3543 */ {2357, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3543_l1}, +/*h(6538)=3544 */ {6538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3544_l1}, +/*h(3954)=3545 */ {3954, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3545_l1}, +/*h(5551)=3546 */ {5551, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11329)=3548 */ {11329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6161)=3550 */ {6161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3550_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11939)=3552 */ {11939, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3552_l1}, +/*h(9355)=3553 */ {9355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3553_l1}, +/*h(6)=3554 */ {6, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3554_l1}, +/*h(1603)=3555 */ {1603, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3555_l1}, +/*h(9965)=3556 */ {9965, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3556_l1}, +/*h(14146)=3557 */ {14146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3557_l1}, +/*h(11562)=3558 */ {11562, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3810)=3560 */ {3810, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3560_l1}, +/*h(1226)=3561 */ {1226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3561_l1}, +/*h(16353)=3562 */ {16353, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3562_l1}, +/*h(13769)=3563 */ {13769, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3563_l1}, +/*h(239)=3564 */ {239, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3564_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10198)=3566 */ {10198, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3566_l1}, +/*h(14379)=3567 */ {14379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3567_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6627)=3569 */ {6627, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3569_l1}, +/*h(4043)=3570 */ {4043, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3570_l1}, +/*h(12405)=3571 */ {12405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3571_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14002)=3573 */ {14002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3573_l1}, +/*h(15599)=3574 */ {15599, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3574_l1}, +/*h(6250)=3575 */ {6250, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3575_l1}, +/*h(3666)=3576 */ {3666, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16209)=3578 */ {16209, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8457)=3580 */ {8457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3580_l1}, +/*h(5873)=3581 */ {5873, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11651)=3583 */ {11651, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3583_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12261)=3587 */ {12261, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3587_l1}, +/*h(9677)=3588 */ {9677, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3588_l1}, +/*h(11274)=3589 */ {11274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3589_l1}, +/*h(8690)=3590 */ {8690, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3590_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3522)=3592 */ {3522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3592_l1}, +/*h(16065)=3593 */ {16065, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3593_l1}, +/*h(2535)=3594 */ {2535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12494)=3596 */ {12494, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3596_l1}, +/*h(5729)=3597 */ {5729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3597_l1}, +/*h(3145)=3598 */ {3145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3598_l1}, +/*h(11507)=3599 */ {11507, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3599_l1}, +/*h(6339)=3600 */ {6339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3600_l1}, +/*h(3755)=3601 */ {3755, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3601_l1}, +/*h(12117)=3602 */ {12117, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3602_l1}, +/*h(16298)=3603 */ {16298, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3603_l1}, +/*h(13714)=3604 */ {13714, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3604_l1}, +/*h(4365)=3605 */ {4365, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3605_l1}, +/*h(5962)=3606 */ {5962, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3606_l1}, +/*h(3378)=3607 */ {3378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3607_l1}, +/*h(7559)=3608 */ {7559, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3608_l1}, +/*h(15921)=3609 */ {15921, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3609_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8169)=3611 */ {8169, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3611_l1}, +/*h(5585)=3612 */ {5585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3612_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11363)=3614 */ {11363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3614_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6195)=3616 */ {6195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3616_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11973)=3618 */ {11973, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3618_l1}, +/*h(13570)=3619 */ {13570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3619_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8402)=3621 */ {8402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3621_l1}, +/*h(9999)=3622 */ {9999, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3622_l1}, +/*h(7415)=3623 */ {7415, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3623_l1}, +/*h(15777)=3624 */ {15777, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3624_l1}, +/*h(2247)=3625 */ {2247, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14790)=3627 */ {14790, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3627_l1}, +/*h(9622)=3628 */ {9622, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3628_l1}, +/*h(13803)=3629 */ {13803, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3629_l1}, +/*h(273)=3630 */ {273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3630_l1}, +/*h(1870)=3631 */ {1870, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3631_l1}, +/*h(3467)=3632 */ {3467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3632_l1}, +/*h(14413)=3633 */ {14413, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3633_l1}, +/*h(16010)=3634 */ {16010, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3634_l1}, +/*h(13426)=3635 */ {13426, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3635_l1}, +/*h(4077)=3636 */ {4077, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3636_l1}, +/*h(12439)=3637 */ {12439, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3637_l1}, +/*h(5674)=3638 */ {5674, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3638_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15633)=3640 */ {15633, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10465)=3642 */ {10465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3642_l1}, +/*h(7881)=3643 */ {7881, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3643_l1}, +/*h(16243)=3644 */ {16243, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3644_l1}, +/*h(129)=3645 */ {129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3645_l1}, +/*h(4310)=3646 */ {4310, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3646_l1}, +/*h(5907)=3647 */ {5907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3647_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11685)=3649 */ {11685, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3649_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10698)=3651 */ {10698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3651_l1}, +/*h(8114)=3652 */ {8114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3652_l1}, +/*h(1349)=3653 */ {1349, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3653_l1}, +/*h(9711)=3654 */ {9711, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3654_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1959)=3656 */ {1959, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3656_l1}, +/*h(10321)=3657 */ {10321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16099)=3659 */ {16099, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3659_l1}, +/*h(13515)=3660 */ {13515, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3660_l1}, +/*h(4166)=3661 */ {4166, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5763)=3663 */ {5763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3663_l1}, +/*h(3179)=3664 */ {3179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3664_l1}, +/*h(11541)=3665 */ {11541, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3665_l1}, +/*h(6373)=3666 */ {6373, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3666_l1}, +/*h(3789)=3667 */ {3789, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3667_l1}, +/*h(12151)=3668 */ {12151, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3668_l1}, +/*h(5386)=3669 */ {5386, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4399)=3671 */ {4399, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3671_l1}, +/*h(1815)=3672 */ {1815, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3672_l1}, +/*h(10177)=3673 */ {10177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3673_l1}, +/*h(7593)=3674 */ {7593, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3674_l1}, +/*h(15955)=3675 */ {15955, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3675_l1}, +/*h(6606)=3676 */ {6606, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3676_l1}, +/*h(8203)=3677 */ {8203, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3677_l1}, +/*h(5619)=3678 */ {5619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3678_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(451)=3680 */ {451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3680_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6229)=3682 */ {6229, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3682_l1}, +/*h(10410)=3683 */ {10410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3683_l1}, +/*h(12007)=3684 */ {12007, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3684_l1}, +/*h(9423)=3685 */ {9423, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3685_l1}, +/*h(74)=3686 */ {74, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14214)=3689 */ {14214, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3689_l1}, +/*h(15811)=3690 */ {15811, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3690_l1}, +/*h(2281)=3691 */ {2281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3691_l1}, +/*h(10643)=3692 */ {10643, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3692_l1}, +/*h(1294)=3693 */ {1294, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15434)=3696 */ {15434, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3696_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6085)=3698 */ {6085, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3698_l1}, +/*h(7682)=3699 */ {7682, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3699_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2514)=3701 */ {2514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3701_l1}, +/*h(4111)=3702 */ {4111, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3702_l1}, +/*h(1527)=3703 */ {1527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3703_l1}, +/*h(9889)=3704 */ {9889, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3704_l1}, +/*h(14070)=3705 */ {14070, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3705_l1}, +/*h(15667)=3706 */ {15667, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3706_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10499)=3708 */ {10499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3708_l1}, +/*h(7915)=3709 */ {7915, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3709_l1}, +/*h(5331)=3710 */ {5331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3710_l1}, +/*h(163)=3711 */ {163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3711_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12706)=3713 */ {12706, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3713_l1}, +/*h(10122)=3714 */ {10122, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3714_l1}, +/*h(11719)=3715 */ {11719, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6551)=3717 */ {6551, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3717_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1383)=3719 */ {1383, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3719_l1}, +/*h(9745)=3720 */ {9745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3720_l1}, +/*h(4577)=3721 */ {4577, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3721_l1}, +/*h(1993)=3722 */ {1993, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3722_l1}, +/*h(10355)=3723 */ {10355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3723_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5187)=3725 */ {5187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3725_l1}, +/*h(13549)=3726 */ {13549, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3726_l1}, +/*h(19)=3727 */ {19, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3727_l1}, +/*h(12562)=3728 */ {12562, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3728_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7394)=3730 */ {7394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3730_l1}, +/*h(11575)=3731 */ {11575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3731_l1}, +/*h(6407)=3732 */ {6407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3732_l1}, +/*h(3823)=3733 */ {3823, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3733_l1}, +/*h(1239)=3734 */ {1239, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3734_l1}, +/*h(9601)=3735 */ {9601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3735_l1}, +/*h(13782)=3736 */ {13782, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3736_l1}, +/*h(15379)=3737 */ {15379, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3737_l1}, +/*h(6030)=3738 */ {6030, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3738_l1}, +/*h(3446)=3739 */ {3446, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3739_l1}, +/*h(7627)=3740 */ {7627, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3740_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12418)=3744 */ {12418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3744_l1}, +/*h(9834)=3745 */ {9834, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3745_l1}, +/*h(7250)=3746 */ {7250, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3746_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2082)=3748 */ {2082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3748_l1}, +/*h(14625)=3749 */ {14625, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3749_l1}, +/*h(12041)=3750 */ {12041, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3750_l1}, +/*h(9457)=3751 */ {9457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3751_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4289)=3753 */ {4289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3753_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10067)=3755 */ {10067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3755_l1}, +/*h(15845)=3756 */ {15845, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3756_l1}, +/*h(2315)=3757 */ {2315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3757_l1}, +/*h(10677)=3758 */ {10677, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3758_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12274)=3760 */ {12274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3760_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(341)=3762 */ {341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3762_l1}, +/*h(1938)=3763 */ {1938, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3763_l1}, +/*h(6119)=3764 */ {6119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3764_l1}, +/*h(3535)=3765 */ {3535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3765_l1}, +/*h(16078)=3766 */ {16078, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3766_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4145)=3768 */ {4145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3768_l1}, +/*h(8326)=3769 */ {8326, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3769_l1}, +/*h(9923)=3770 */ {9923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3770_l1}, +/*h(7339)=3771 */ {7339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10533)=3774 */ {10533, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3774_l1}, +/*h(12130)=3775 */ {12130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3775_l1}, +/*h(5365)=3776 */ {5365, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3776_l1}, +/*h(197)=3777 */ {197, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3777_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5975)=3779 */ {5975, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3779_l1}, +/*h(14337)=3780 */ {14337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3780_l1}, +/*h(11753)=3781 */ {11753, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3781_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4001)=3784 */ {4001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3784_l1}, +/*h(12363)=3785 */ {12363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3785_l1}, +/*h(9779)=3786 */ {9779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3786_l1}, +/*h(430)=3787 */ {430, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3787_l1}, +/*h(15557)=3788 */ {15557, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3788_l1}, +/*h(10389)=3789 */ {10389, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3789_l1}, +/*h(14570)=3790 */ {14570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3790_l1}, +/*h(11986)=3791 */ {11986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3791_l1}, +/*h(13583)=3792 */ {13583, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3792_l1}, +/*h(4234)=3793 */ {4234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3793_l1}, +/*h(1650)=3794 */ {1650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3794_l1}, +/*h(5831)=3795 */ {5831, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3795_l1}, +/*h(14193)=3796 */ {14193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3796_l1}, +/*h(15790)=3797 */ {15790, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3797_l1}, +/*h(6441)=3798 */ {6441, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3798_l1}, +/*h(3857)=3799 */ {3857, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3799_l1}, +/*h(14803)=3800 */ {14803, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3800_l1}, +/*h(9635)=3801 */ {9635, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3801_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10245)=3805 */ {10245, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3805_l1}, +/*h(11842)=3806 */ {11842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3806_l1}, +/*h(9258)=3807 */ {9258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3807_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1506)=3810 */ {1506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3810_l1}, +/*h(14049)=3811 */ {14049, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3811_l1}, +/*h(11465)=3812 */ {11465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3812_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10478)=3815 */ {10478, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3815_l1}, +/*h(1129)=3816 */ {1129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3816_l1}, +/*h(9491)=3817 */ {9491, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3817_l1}, +/*h(142)=3818 */ {142, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3818_l1}, +/*h(1739)=3819 */ {1739, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3819_l1}, +/*h(12685)=3820 */ {12685, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3820_l1}, +/*h(10101)=3821 */ {10101, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3821_l1}, +/*h(11698)=3822 */ {11698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3822_l1}, +/*h(2349)=3823 */ {2349, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3823_l1}, +/*h(10711)=3824 */ {10711, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3824_l1}, +/*h(3946)=3825 */ {3946, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3825_l1}, +/*h(5543)=3826 */ {5543, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3826_l1}, +/*h(13905)=3827 */ {13905, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3827_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6153)=3830 */ {6153, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3830_l1}, +/*h(3569)=3831 */ {3569, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3831_l1}, +/*h(9347)=3832 */ {9347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3832_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4179)=3834 */ {4179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3834_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9957)=3836 */ {9957, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3836_l1}, +/*h(7373)=3837 */ {7373, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3837_l1}, +/*h(11554)=3838 */ {11554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3838_l1}, +/*h(6386)=3839 */ {6386, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1218)=3841 */ {1218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3841_l1}, +/*h(5399)=3842 */ {5399, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3842_l1}, +/*h(231)=3843 */ {231, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3843_l1}, +/*h(8593)=3844 */ {8593, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3844_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10190)=3846 */ {10190, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3846_l1}, +/*h(11787)=3847 */ {11787, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3847_l1}, +/*h(2438)=3848 */ {2438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3848_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4035)=3850 */ {4035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3850_l1}, +/*h(1451)=3851 */ {1451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3851_l1}, +/*h(13994)=3852 */ {13994, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3852_l1}, +/*h(11410)=3853 */ {11410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3853_l1}, +/*h(15591)=3854 */ {15591, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3854_l1}, +/*h(6242)=3855 */ {6242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3855_l1}, +/*h(3658)=3856 */ {3658, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3856_l1}, +/*h(16201)=3857 */ {16201, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3857_l1}, +/*h(13617)=3858 */ {13617, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3858_l1}, +/*h(87)=3859 */ {87, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3859_l1}, +/*h(12630)=3860 */ {12630, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3860_l1}, +/*h(5865)=3861 */ {5865, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3861_l1}, +/*h(3281)=3862 */ {3281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3862_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2294)=3864 */ {2294, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3864_l1}, +/*h(3891)=3865 */ {3891, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3865_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9669)=3867 */ {9669, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3867_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11266)=3869 */ {11266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3869_l1}, +/*h(6098)=3870 */ {6098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3870_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13473)=3874 */ {13473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3874_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12486)=3876 */ {12486, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3876_l1}, +/*h(3137)=3877 */ {3137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3877_l1}, +/*h(11499)=3878 */ {11499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3878_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3747)=3881 */ {3747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3881_l1}, +/*h(1163)=3882 */ {1163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3882_l1}, +/*h(13706)=3883 */ {13706, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3883_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4357)=3885 */ {4357, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3885_l1}, +/*h(5954)=3886 */ {5954, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3886_l1}, +/*h(10135)=3887 */ {10135, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3887_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15913)=3889 */ {15913, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3889_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8161)=3891 */ {8161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3891_l1}, +/*h(5577)=3892 */ {5577, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3892_l1}, +/*h(13939)=3893 */ {13939, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3893_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2006)=3895 */ {2006, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3895_l1}, +/*h(6187)=3896 */ {6187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3896_l1}, +/*h(14549)=3897 */ {14549, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3897_l1}, +/*h(16146)=3898 */ {16146, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3898_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8394)=3901 */ {8394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3901_l1}, +/*h(9991)=3902 */ {9991, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3902_l1}, +/*h(7407)=3903 */ {7407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8017)=3907 */ {8017, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3907_l1}, +/*h(9614)=3908 */ {9614, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3908_l1}, +/*h(13795)=3909 */ {13795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3909_l1}, +/*h(8627)=3910 */ {8627, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3910_l1}, +/*h(1862)=3911 */ {1862, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3911_l1}, +/*h(14405)=3912 */ {14405, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3912_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16002)=3914 */ {16002, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3914_l1}, +/*h(13418)=3915 */ {13418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3915_l1}, +/*h(4069)=3916 */ {4069, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3916_l1}, +/*h(12431)=3917 */ {12431, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3917_l1}, +/*h(3082)=3918 */ {3082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3918_l1}, +/*h(498)=3919 */ {498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3919_l1}, +/*h(15625)=3920 */ {15625, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7873)=3922 */ {7873, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3922_l1}, +/*h(16235)=3923 */ {16235, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3923_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4302)=3925 */ {4302, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3925_l1}, +/*h(8483)=3926 */ {8483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3926_l1}, +/*h(5899)=3927 */ {5899, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3927_l1}, +/*h(3315)=3928 */ {3315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3928_l1}, +/*h(15858)=3929 */ {15858, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3929_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10690)=3931 */ {10690, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3931_l1}, +/*h(8106)=3932 */ {8106, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3932_l1}, +/*h(9703)=3933 */ {9703, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3933_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4535)=3935 */ {4535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3935_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10313)=3937 */ {10313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3937_l1}, +/*h(7729)=3938 */ {7729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3938_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13507)=3940 */ {13507, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3940_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8339)=3942 */ {8339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3942_l1}, +/*h(3171)=3943 */ {3171, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3943_l1}, +/*h(11533)=3944 */ {11533, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3944_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3781)=3947 */ {3781, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3947_l1}, +/*h(5378)=3948 */ {5378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3948_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(210)=3950 */ {210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3950_l1}, +/*h(4391)=3951 */ {4391, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3951_l1}, +/*h(12753)=3952 */ {12753, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3952_l1}, +/*h(7585)=3953 */ {7585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3953_l1}, +/*h(11766)=3954 */ {11766, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3954_l1}, +/*h(15947)=3955 */ {15947, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3955_l1}, +/*h(6598)=3956 */ {6598, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3956_l1}, +/*h(8195)=3957 */ {8195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3957_l1}, +/*h(5611)=3958 */ {5611, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3958_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15570)=3961 */ {15570, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3961_l1}, +/*h(6221)=3962 */ {6221, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3962_l1}, +/*h(14583)=3963 */ {14583, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3963_l1}, +/*h(5234)=3964 */ {5234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3964_l1}, +/*h(9415)=3965 */ {9415, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3965_l1}, +/*h(66)=3966 */ {66, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10025)=3968 */ {10025, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3968_l1}, +/*h(7441)=3969 */ {7441, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3969_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2273)=3971 */ {2273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3971_l1}, +/*h(10635)=3972 */ {10635, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3972_l1}, +/*h(8051)=3973 */ {8051, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3973_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(299)=3975 */ {299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3975_l1}, +/*h(8661)=3976 */ {8661, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3976_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10258)=3978 */ {10258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3978_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2506)=3980 */ {2506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3980_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4103)=3982 */ {4103, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3982_l1}, +/*h(12465)=3983 */ {12465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3983_l1}, +/*h(14062)=3984 */ {14062, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3984_l1}, +/*h(11478)=3985 */ {11478, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3985_l1}, +/*h(2129)=3986 */ {2129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7907)=3988 */ {7907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3988_l1}, +/*h(5323)=3989 */ {5323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3989_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10114)=3993 */ {10114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3993_l1}, +/*h(14295)=3994 */ {14295, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3994_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6543)=3997 */ {6543, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3997_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9737)=3999 */ {9737, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_3999_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1985)=4002 */ {1985, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4002_l1}, +/*h(10347)=4003 */ {10347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4003_l1}, +/*h(7763)=4004 */ {7763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4004_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13541)=4006 */ {13541, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4006_l1}, +/*h(11)=4007 */ {11, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4007_l1}, +/*h(12554)=4008 */ {12554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4008_l1}, +/*h(9970)=4009 */ {9970, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4009_l1}, +/*h(11567)=4010 */ {11567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4010_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2218)=4012 */ {2218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4012_l1}, +/*h(3815)=4013 */ {3815, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4013_l1}, +/*h(1231)=4014 */ {1231, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4014_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15371)=4017 */ {15371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4017_l1}, +/*h(12787)=4018 */ {12787, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4018_l1}, +/*h(3438)=4019 */ {3438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4019_l1}, +/*h(7619)=4020 */ {7619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4020_l1}, +/*h(2451)=4021 */ {2451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7242)=4025 */ {7242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16214)=4030 */ {16214, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4030_l1}, +/*h(9449)=4031 */ {9449, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4031_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8462)=4033 */ {8462, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4033_l1}, +/*h(10059)=4034 */ {10059, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4034_l1}, +/*h(7475)=4035 */ {7475, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4035_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2307)=4037 */ {2307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4037_l1}, +/*h(10669)=4038 */ {10669, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4038_l1}, +/*h(12266)=4039 */ {12266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4039_l1}, +/*h(9682)=4040 */ {9682, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4040_l1}, +/*h(333)=4041 */ {333, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4041_l1}, +/*h(8695)=4042 */ {8695, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4042_l1}, +/*h(1930)=4043 */ {1930, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4043_l1}, +/*h(3527)=4044 */ {3527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4044_l1}, +/*h(11889)=4045 */ {11889, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4045_l1}, +/*h(16070)=4046 */ {16070, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4046_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4137)=4048 */ {4137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4048_l1}, +/*h(12499)=4049 */ {12499, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4049_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7331)=4051 */ {7331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4051_l1}, +/*h(2163)=4052 */ {2163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4052_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7941)=4054 */ {7941, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4054_l1}, +/*h(5357)=4055 */ {5357, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4055_l1}, +/*h(13719)=4056 */ {13719, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4056_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4370)=4058 */ {4370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4058_l1}, +/*h(5967)=4059 */ {5967, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4059_l1}, +/*h(3383)=4060 */ {3383, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4060_l1}, +/*h(11745)=4061 */ {11745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6577)=4063 */ {6577, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4063_l1}, +/*h(1409)=4064 */ {1409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4064_l1}, +/*h(12355)=4065 */ {12355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4065_l1}, +/*h(7187)=4066 */ {7187, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4066_l1}, +/*h(422)=4067 */ {422, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4067_l1}, +/*h(2019)=4068 */ {2019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4068_l1}, +/*h(10381)=4069 */ {10381, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4069_l1}, +/*h(11978)=4070 */ {11978, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4070_l1}, +/*h(9394)=4071 */ {9394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4071_l1}, +/*h(13575)=4072 */ {13575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4072_l1}, +/*h(4226)=4073 */ {4226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4073_l1}, +/*h(8407)=4074 */ {8407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4074_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14185)=4076 */ {14185, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4076_l1}, +/*h(15782)=4077 */ {15782, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4077_l1}, +/*h(6433)=4078 */ {6433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4078_l1}, +/*h(14795)=4079 */ {14795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4079_l1}, +/*h(1265)=4080 */ {1265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4080_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(278)=4082 */ {278, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4082_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1875)=4084 */ {1875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4084_l1}, +/*h(14418)=4085 */ {14418, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4085_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9250)=4087 */ {9250, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4087_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4082)=4089 */ {4082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4089_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11457)=4092 */ {11457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4092_l1}, +/*h(15638)=4093 */ {15638, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4093_l1}, +/*h(10470)=4094 */ {10470, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4094_l1}, +/*h(7886)=4095 */ {7886, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4095_l1}, +/*h(1121)=4096 */ {1121, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4096_l1}, +/*h(9483)=4097 */ {9483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4097_l1}, +/*h(134)=4098 */ {134, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4098_l1}, +/*h(1731)=4099 */ {1731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4099_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14274)=4101 */ {14274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4101_l1}, +/*h(11690)=4102 */ {11690, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4102_l1}, +/*h(2341)=4103 */ {2341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4103_l1}, +/*h(3938)=4104 */ {3938, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4104_l1}, +/*h(8119)=4105 */ {8119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13897)=4107 */ {13897, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4107_l1}, +/*h(11313)=4108 */ {11313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4108_l1}, +/*h(6145)=4109 */ {6145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4109_l1}, +/*h(3561)=4110 */ {3561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4110_l1}, +/*h(11923)=4111 */ {11923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4171)=4114 */ {4171, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4114_l1}, +/*h(12533)=4115 */ {12533, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4115_l1}, +/*h(14130)=4116 */ {14130, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4116_l1}, +/*h(7365)=4117 */ {7365, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4117_l1}, +/*h(2197)=4118 */ {2197, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4118_l1}, +/*h(6378)=4119 */ {6378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4119_l1}, +/*h(3794)=4120 */ {3794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4120_l1}, +/*h(16337)=4121 */ {16337, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8585)=4124 */ {8585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4124_l1}, +/*h(6001)=4125 */ {6001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4125_l1}, +/*h(7598)=4126 */ {7598, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4126_l1}, +/*h(11779)=4127 */ {11779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6611)=4129 */ {6611, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4129_l1}, +/*h(1443)=4130 */ {1443, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13986)=4132 */ {13986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4132_l1}, +/*h(11402)=4133 */ {11402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4133_l1}, +/*h(2053)=4134 */ {2053, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4134_l1}, +/*h(3650)=4135 */ {3650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4135_l1}, +/*h(1066)=4136 */ {1066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4136_l1}, +/*h(16193)=4137 */ {16193, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4137_l1}, +/*h(13609)=4138 */ {13609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12622)=4140 */ {12622, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4140_l1}, +/*h(3273)=4141 */ {3273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4141_l1}, +/*h(14219)=4142 */ {14219, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2286)=4144 */ {2286, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4144_l1}, +/*h(3883)=4145 */ {3883, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4145_l1}, +/*h(12245)=4146 */ {12245, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13842)=4148 */ {13842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4148_l1}, +/*h(8674)=4149 */ {8674, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4149_l1}, +/*h(1909)=4150 */ {1909, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4150_l1}, +/*h(3506)=4151 */ {3506, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2519)=4153 */ {2519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8297)=4155 */ {8297, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4155_l1}, +/*h(5713)=4156 */ {5713, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11491)=4158 */ {11491, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6323)=4160 */ {6323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1155)=4162 */ {1155, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4162_l1}, +/*h(13698)=4163 */ {13698, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1765)=4165 */ {1765, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4165_l1}, +/*h(10127)=4166 */ {10127, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4166_l1}, +/*h(3362)=4167 */ {3362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4167_l1}, +/*h(15905)=4168 */ {15905, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4168_l1}, +/*h(13321)=4169 */ {13321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4169_l1}, +/*h(10737)=4170 */ {10737, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5569)=4172 */ {5569, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4172_l1}, +/*h(13931)=4173 */ {13931, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4173_l1}, +/*h(11347)=4174 */ {11347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4174_l1}, +/*h(6179)=4175 */ {6179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4175_l1}, +/*h(14541)=4176 */ {14541, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16138)=4178 */ {16138, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4178_l1}, +/*h(13554)=4179 */ {13554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4179_l1}, +/*h(8386)=4180 */ {8386, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4180_l1}, +/*h(12567)=4181 */ {12567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4181_l1}, +/*h(3218)=4182 */ {3218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4182_l1}, +/*h(7399)=4183 */ {7399, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4183_l1}, +/*h(15761)=4184 */ {15761, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8009)=4186 */ {8009, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4186_l1}, +/*h(16371)=4187 */ {16371, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4187_l1}, +/*h(9606)=4188 */ {9606, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4188_l1}, +/*h(257)=4189 */ {257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4189_l1}, +/*h(8619)=4190 */ {8619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4190_l1}, +/*h(6035)=4191 */ {6035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13410)=4194 */ {13410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8242)=4196 */ {8242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4196_l1}, +/*h(12423)=4197 */ {12423, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4197_l1}, +/*h(3074)=4198 */ {3074, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4198_l1}, +/*h(490)=4199 */ {490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10449)=4201 */ {10449, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4201_l1}, +/*h(14630)=4202 */ {14630, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4202_l1}, +/*h(16227)=4203 */ {16227, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4294)=4205 */ {4294, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3307)=4207 */ {3307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4207_l1}, +/*h(14253)=4208 */ {14253, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4208_l1}, +/*h(15850)=4209 */ {15850, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12279)=4212 */ {12279, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4212_l1}, +/*h(5514)=4213 */ {5514, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15473)=4215 */ {15473, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4215_l1}, +/*h(1943)=4216 */ {1943, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4216_l1}, +/*h(14486)=4217 */ {14486, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4217_l1}, +/*h(7721)=4218 */ {7721, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4218_l1}, +/*h(16083)=4219 */ {16083, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4219_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8331)=4221 */ {8331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4221_l1}, +/*h(5747)=4222 */ {5747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4222_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11525)=4224 */ {11525, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6357)=4226 */ {6357, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4226_l1}, +/*h(7954)=4227 */ {7954, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(202)=4230 */ {202, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4230_l1}, +/*h(12745)=4231 */ {12745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4231_l1}, +/*h(10161)=4232 */ {10161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11758)=4234 */ {11758, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4234_l1}, +/*h(13355)=4235 */ {13355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4235_l1}, +/*h(4006)=4236 */ {4006, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4236_l1}, +/*h(1422)=4237 */ {1422, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4237_l1}, +/*h(5603)=4238 */ {5603, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4238_l1}, +/*h(435)=4239 */ {435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4239_l1}, +/*h(15562)=4240 */ {15562, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4240_l1}, +/*h(6213)=4241 */ {6213, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4241_l1}, +/*h(14575)=4242 */ {14575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4242_l1}, +/*h(11991)=4243 */ {11991, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4243_l1}, +/*h(5226)=4244 */ {5226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14198)=4248 */ {14198, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4248_l1}, +/*h(7433)=4249 */ {7433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4249_l1}, +/*h(15795)=4250 */ {15795, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4250_l1}, +/*h(6446)=4251 */ {6446, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4251_l1}, +/*h(8043)=4252 */ {8043, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(291)=4255 */ {291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4255_l1}, +/*h(8653)=4256 */ {8653, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4256_l1}, +/*h(6069)=4257 */ {6069, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4257_l1}, +/*h(7666)=4258 */ {7666, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2498)=4260 */ {2498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4260_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12457)=4263 */ {12457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4263_l1}, +/*h(14054)=4264 */ {14054, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4264_l1}, +/*h(11470)=4265 */ {11470, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4265_l1}, +/*h(2121)=4266 */ {2121, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4266_l1}, +/*h(10483)=4267 */ {10483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4267_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5315)=4269 */ {5315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(147)=4271 */ {147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4271_l1}, +/*h(12690)=4272 */ {12690, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4272_l1}, +/*h(3341)=4273 */ {3341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11703)=4275 */ {11703, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4275_l1}, +/*h(6535)=4276 */ {6535, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1367)=4278 */ {1367, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4278_l1}, +/*h(9729)=4279 */ {9729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4561)=4281 */ {4561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4281_l1}, +/*h(6158)=4282 */ {6158, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4282_l1}, +/*h(3574)=4283 */ {3574, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4283_l1}, +/*h(7755)=4284 */ {7755, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4284_l1}, +/*h(16117)=4285 */ {16117, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4285_l1}, +/*h(3)=4286 */ {3, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12546)=4288 */ {12546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4288_l1}, +/*h(9962)=4289 */ {9962, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4289_l1}, +/*h(7378)=4290 */ {7378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4290_l1}, +/*h(2210)=4291 */ {2210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4291_l1}, +/*h(6391)=4292 */ {6391, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4292_l1}, +/*h(14753)=4293 */ {14753, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4293_l1}, +/*h(1223)=4294 */ {1223, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12779)=4297 */ {12779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4297_l1}, +/*h(10195)=4298 */ {10195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4298_l1}, +/*h(3430)=4299 */ {3430, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4299_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2443)=4301 */ {2443, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4301_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12402)=4303 */ {12402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7234)=4305 */ {7234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4305_l1}, +/*h(469)=4306 */ {469, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4306_l1}, +/*h(2066)=4307 */ {2066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4307_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14609)=4309 */ {14609, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4309_l1}, +/*h(9441)=4310 */ {9441, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4310_l1}, +/*h(13622)=4311 */ {13622, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4311_l1}, +/*h(4273)=4312 */ {4273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4312_l1}, +/*h(5870)=4313 */ {5870, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4313_l1}, +/*h(10051)=4314 */ {10051, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4314_l1}, +/*h(7467)=4315 */ {7467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4315_l1}, +/*h(15829)=4316 */ {15829, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4316_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8077)=4318 */ {8077, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4318_l1}, +/*h(12258)=4319 */ {12258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4319_l1}, +/*h(9674)=4320 */ {9674, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4320_l1}, +/*h(325)=4321 */ {325, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4321_l1}, +/*h(8687)=4322 */ {8687, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4322_l1}, +/*h(6103)=4323 */ {6103, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4323_l1}, +/*h(14465)=4324 */ {14465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4324_l1}, +/*h(11881)=4325 */ {11881, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4325_l1}, +/*h(9297)=4326 */ {9297, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8310)=4328 */ {8310, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4328_l1}, +/*h(12491)=4329 */ {12491, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4329_l1}, +/*h(9907)=4330 */ {9907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2155)=4332 */ {2155, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4332_l1}, +/*h(10517)=4333 */ {10517, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12114)=4335 */ {12114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4335_l1}, +/*h(13711)=4336 */ {13711, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4336_l1}, +/*h(4362)=4337 */ {4362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4337_l1}, +/*h(1778)=4338 */ {1778, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4338_l1}, +/*h(5959)=4339 */ {5959, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4339_l1}, +/*h(14321)=4340 */ {14321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6569)=4342 */ {6569, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4342_l1}, +/*h(3985)=4343 */ {3985, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9763)=4345 */ {9763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4345_l1}, +/*h(7179)=4346 */ {7179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4346_l1}, +/*h(4595)=4347 */ {4595, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10373)=4349 */ {10373, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4349_l1}, +/*h(11970)=4350 */ {11970, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4350_l1}, +/*h(16151)=4351 */ {16151, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4351_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8399)=4353 */ {8399, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4353_l1}, +/*h(1634)=4354 */ {1634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4354_l1}, +/*h(14177)=4355 */ {14177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4355_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14787)=4359 */ {14787, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4359_l1}, +/*h(1257)=4360 */ {1257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4360_l1}, +/*h(9619)=4361 */ {9619, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4361_l1}, +/*h(270)=4362 */ {270, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4362_l1}, +/*h(1867)=4363 */ {1867, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4363_l1}, +/*h(10229)=4364 */ {10229, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4364_l1}, +/*h(14410)=4365 */ {14410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4365_l1}, +/*h(11826)=4366 */ {11826, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4366_l1}, +/*h(2477)=4367 */ {2477, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4367_l1}, +/*h(4074)=4368 */ {4074, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4368_l1}, +/*h(1490)=4369 */ {1490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4369_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14033)=4371 */ {14033, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4371_l1}, +/*h(503)=4372 */ {503, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4372_l1}, +/*h(6281)=4373 */ {6281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4373_l1}, +/*h(3697)=4374 */ {3697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4374_l1}, +/*h(7878)=4375 */ {7878, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4375_l1}, +/*h(9475)=4376 */ {9475, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4307)=4378 */ {4307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11682)=4381 */ {11682, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4381_l1}, +/*h(15863)=4382 */ {15863, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4382_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10695)=4384 */ {10695, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4384_l1}, +/*h(5527)=4385 */ {5527, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4385_l1}, +/*h(13889)=4386 */ {13889, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4386_l1}, +/*h(11305)=4387 */ {11305, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3553)=4390 */ {3553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4390_l1}, +/*h(11915)=4391 */ {11915, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4391_l1}, +/*h(9331)=4392 */ {9331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4392_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4163)=4394 */ {4163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4394_l1}, +/*h(12525)=4395 */ {12525, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4395_l1}, +/*h(9941)=4396 */ {9941, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4396_l1}, +/*h(11538)=4397 */ {11538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4397_l1}, +/*h(2189)=4398 */ {2189, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4398_l1}, +/*h(6370)=4399 */ {6370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4399_l1}, +/*h(3786)=4400 */ {3786, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4400_l1}, +/*h(16329)=4401 */ {16329, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4401_l1}, +/*h(13745)=4402 */ {13745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4402_l1}, +/*h(215)=4403 */ {215, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4403_l1}, +/*h(12758)=4404 */ {12758, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4404_l1}, +/*h(5993)=4405 */ {5993, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4405_l1}, +/*h(14355)=4406 */ {14355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6603)=4408 */ {6603, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4408_l1}, +/*h(4019)=4409 */ {4019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4409_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15575)=4413 */ {15575, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4413_l1}, +/*h(6226)=4414 */ {6226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4414_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1058)=4416 */ {1058, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4416_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13601)=4418 */ {13601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4418_l1}, +/*h(8433)=4419 */ {8433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4419_l1}, +/*h(12614)=4420 */ {12614, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4420_l1}, +/*h(3265)=4421 */ {3265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4421_l1}, +/*h(7446)=4422 */ {7446, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4422_l1}, +/*h(2278)=4423 */ {2278, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4423_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3875)=4425 */ {3875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4425_l1}, +/*h(12237)=4426 */ {12237, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4426_l1}, +/*h(13834)=4427 */ {13834, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4427_l1}, +/*h(4485)=4428 */ {4485, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4428_l1}, +/*h(1901)=4429 */ {1901, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4429_l1}, +/*h(10263)=4430 */ {10263, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4430_l1}, +/*h(3498)=4431 */ {3498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4431_l1}, +/*h(16041)=4432 */ {16041, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4432_l1}, +/*h(2511)=4433 */ {2511, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4433_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8289)=4435 */ {8289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4435_l1}, +/*h(5705)=4436 */ {5705, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4436_l1}, +/*h(14067)=4437 */ {14067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2134)=4439 */ {2134, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4439_l1}, +/*h(3731)=4440 */ {3731, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4440_l1}, +/*h(14677)=4441 */ {14677, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4441_l1}, +/*h(16274)=4442 */ {16274, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4341)=4444 */ {4341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4444_l1}, +/*h(5938)=4445 */ {5938, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4445_l1}, +/*h(10119)=4446 */ {10119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4446_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13313)=4449 */ {13313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4449_l1}, +/*h(10729)=4450 */ {10729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4450_l1}, +/*h(8145)=4451 */ {8145, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4451_l1}, +/*h(13923)=4452 */ {13923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4452_l1}, +/*h(11339)=4453 */ {11339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4453_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14533)=4456 */ {14533, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13546)=4458 */ {13546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4458_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12559)=4461 */ {12559, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4461_l1}, +/*h(9975)=4462 */ {9975, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15753)=4464 */ {15753, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4464_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8001)=4466 */ {8001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4466_l1}, +/*h(16363)=4467 */ {16363, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4467_l1}, +/*h(13779)=4468 */ {13779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4468_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8611)=4470 */ {8611, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4470_l1}, +/*h(6027)=4471 */ {6027, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15986)=4473 */ {15986, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4473_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4053)=4475 */ {4053, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4475_l1}, +/*h(8234)=4476 */ {8234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4476_l1}, +/*h(5650)=4477 */ {5650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4477_l1}, +/*h(482)=4478 */ {482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10441)=4481 */ {10441, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4481_l1}, +/*h(12038)=4482 */ {12038, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4482_l1}, +/*h(9454)=4483 */ {9454, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4483_l1}, +/*h(105)=4484 */ {105, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4484_l1}, +/*h(8467)=4485 */ {8467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4485_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3299)=4487 */ {3299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4487_l1}, +/*h(11661)=4488 */ {11661, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4488_l1}, +/*h(15842)=4489 */ {15842, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4489_l1}, +/*h(10674)=4490 */ {10674, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12271)=4492 */ {12271, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4492_l1}, +/*h(9687)=4493 */ {9687, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4493_l1}, +/*h(4519)=4494 */ {4519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4494_l1}, +/*h(15465)=4495 */ {15465, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4495_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14478)=4497 */ {14478, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4497_l1}, +/*h(16075)=4498 */ {16075, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4498_l1}, +/*h(2545)=4499 */ {2545, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4499_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8323)=4501 */ {8323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4501_l1}, +/*h(5739)=4502 */ {5739, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4502_l1}, +/*h(3155)=4503 */ {3155, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4503_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6349)=4506 */ {6349, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4506_l1}, +/*h(7946)=4507 */ {7946, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4507_l1}, +/*h(5362)=4508 */ {5362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(194)=4510 */ {194, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4510_l1}, +/*h(12737)=4511 */ {12737, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4511_l1}, +/*h(10153)=4512 */ {10153, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4512_l1}, +/*h(11750)=4513 */ {11750, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13347)=4515 */ {13347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8179)=4517 */ {8179, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(427)=4519 */ {427, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4519_l1}, +/*h(15554)=4520 */ {15554, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4520_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14567)=4522 */ {14567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4522_l1}, +/*h(11983)=4523 */ {11983, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4523_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(50)=4525 */ {50, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4525_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12593)=4527 */ {12593, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4527_l1}, +/*h(7425)=4528 */ {7425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2257)=4530 */ {2257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4530_l1}, +/*h(6438)=4531 */ {6438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4531_l1}, +/*h(8035)=4532 */ {8035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4532_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13813)=4534 */ {13813, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4534_l1}, +/*h(15410)=4535 */ {15410, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4535_l1}, +/*h(8645)=4536 */ {8645, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4536_l1}, +/*h(10242)=4537 */ {10242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4537_l1}, +/*h(14423)=4538 */ {14423, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4087)=4541 */ {4087, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4541_l1}, +/*h(12449)=4542 */ {12449, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4542_l1}, +/*h(9865)=4543 */ {9865, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4543_l1}, +/*h(7281)=4544 */ {7281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4544_l1}, +/*h(11462)=4545 */ {11462, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4545_l1}, +/*h(2113)=4546 */ {2113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4546_l1}, +/*h(10475)=4547 */ {10475, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4547_l1}, +/*h(7891)=4548 */ {7891, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(139)=4550 */ {139, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4550_l1}, +/*h(8501)=4551 */ {8501, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4551_l1}, +/*h(12682)=4552 */ {12682, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4552_l1}, +/*h(10098)=4553 */ {10098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4553_l1}, +/*h(11695)=4554 */ {11695, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4554_l1}, +/*h(2346)=4555 */ {2346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4555_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1359)=4558 */ {1359, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4553)=4561 */ {4553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4561_l1}, +/*h(6150)=4562 */ {6150, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4562_l1}, +/*h(3566)=4563 */ {3566, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4563_l1}, +/*h(16109)=4564 */ {16109, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4564_l1}, +/*h(13525)=4565 */ {13525, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9954)=4568 */ {9954, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4568_l1}, +/*h(7370)=4569 */ {7370, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6383)=4572 */ {6383, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4572_l1}, +/*h(12161)=4573 */ {12161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4573_l1}, +/*h(16342)=4574 */ {16342, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12771)=4577 */ {12771, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4577_l1}, +/*h(6006)=4578 */ {6006, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4578_l1}, +/*h(7603)=4579 */ {7603, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4579_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2435)=4581 */ {2435, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12394)=4583 */ {12394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4583_l1}, +/*h(9810)=4584 */ {9810, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4584_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2058)=4587 */ {2058, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4587_l1}, +/*h(14601)=4588 */ {14601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4588_l1}, +/*h(12017)=4589 */ {12017, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4589_l1}, +/*h(13614)=4590 */ {13614, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4590_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4265)=4592 */ {4265, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4592_l1}, +/*h(5862)=4593 */ {5862, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4593_l1}, +/*h(3278)=4594 */ {3278, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4594_l1}, +/*h(7459)=4595 */ {7459, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4595_l1}, +/*h(15821)=4596 */ {15821, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4596_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14834)=4598 */ {14834, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9666)=4600 */ {9666, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4600_l1}, +/*h(4498)=4601 */ {4498, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4601_l1}, +/*h(8679)=4602 */ {8679, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4602_l1}, +/*h(6095)=4603 */ {6095, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4603_l1}, +/*h(3511)=4604 */ {3511, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4604_l1}, +/*h(11873)=4605 */ {11873, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4605_l1}, +/*h(9289)=4606 */ {9289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4606_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8302)=4608 */ {8302, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4608_l1}, +/*h(9899)=4609 */ {9899, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4609_l1}, +/*h(7315)=4610 */ {7315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4610_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2147)=4612 */ {2147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4612_l1}, +/*h(10509)=4613 */ {10509, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4613_l1}, +/*h(12106)=4614 */ {12106, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4614_l1}, +/*h(9522)=4615 */ {9522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4615_l1}, +/*h(13703)=4616 */ {13703, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4616_l1}, +/*h(4354)=4617 */ {4354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4617_l1}, +/*h(1770)=4618 */ {1770, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4618_l1}, +/*h(14313)=4619 */ {14313, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4619_l1}, +/*h(11729)=4620 */ {11729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4620_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6561)=4622 */ {6561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4622_l1}, +/*h(10742)=4623 */ {10742, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4623_l1}, +/*h(12339)=4624 */ {12339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7171)=4626 */ {7171, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4626_l1}, +/*h(2003)=4627 */ {2003, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4627_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14546)=4629 */ {14546, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4629_l1}, +/*h(16143)=4630 */ {16143, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4630_l1}, +/*h(13559)=4631 */ {13559, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4631_l1}, +/*h(4210)=4632 */ {4210, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4632_l1}, +/*h(8391)=4633 */ {8391, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4633_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15766)=4636 */ {15766, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4636_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6417)=4638 */ {6417, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4638_l1}, +/*h(1249)=4639 */ {1249, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4639_l1}, +/*h(9611)=4640 */ {9611, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(262)=4642 */ {262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4642_l1}, +/*h(1859)=4643 */ {1859, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4643_l1}, +/*h(10221)=4644 */ {10221, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4644_l1}, +/*h(14402)=4645 */ {14402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4645_l1}, +/*h(9234)=4646 */ {9234, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4646_l1}, +/*h(2469)=4647 */ {2469, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4647_l1}, +/*h(4066)=4648 */ {4066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4648_l1}, +/*h(1482)=4649 */ {1482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4649_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14025)=4651 */ {14025, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4651_l1}, +/*h(15622)=4652 */ {15622, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4652_l1}, +/*h(6273)=4653 */ {6273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4653_l1}, +/*h(10454)=4654 */ {10454, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4654_l1}, +/*h(1105)=4655 */ {1105, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4299)=4658 */ {4299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4658_l1}, +/*h(1715)=4659 */ {1715, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4659_l1}, +/*h(14258)=4660 */ {14258, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4660_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15855)=4662 */ {15855, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4662_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3922)=4664 */ {3922, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4664_l1}, +/*h(5519)=4665 */ {5519, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4665_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11297)=4667 */ {11297, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4667_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6129)=4669 */ {6129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11907)=4671 */ {11907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4671_l1}, +/*h(9323)=4672 */ {9323, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4672_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12517)=4674 */ {12517, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4674_l1}, +/*h(9933)=4675 */ {9933, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4675_l1}, +/*h(14114)=4676 */ {14114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4676_l1}, +/*h(11530)=4677 */ {11530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4677_l1}, +/*h(2181)=4678 */ {2181, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4678_l1}, +/*h(3778)=4679 */ {3778, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4679_l1}, +/*h(7959)=4680 */ {7959, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4680_l1}, +/*h(16321)=4681 */ {16321, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4681_l1}, +/*h(207)=4682 */ {207, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4682_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5985)=4684 */ {5985, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4684_l1}, +/*h(14347)=4685 */ {14347, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4685_l1}, +/*h(11763)=4686 */ {11763, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6595)=4688 */ {6595, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4688_l1}, +/*h(4011)=4689 */ {4011, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4689_l1}, +/*h(1427)=4690 */ {1427, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4690_l1}, +/*h(13970)=4691 */ {13970, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4691_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15567)=4693 */ {15567, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4693_l1}, +/*h(6218)=4694 */ {6218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4694_l1}, +/*h(3634)=4695 */ {3634, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4695_l1}, +/*h(16177)=4696 */ {16177, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4696_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8425)=4699 */ {8425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4699_l1}, +/*h(5841)=4700 */ {5841, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4700_l1}, +/*h(7438)=4701 */ {7438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4701_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6451)=4704 */ {6451, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4704_l1}, +/*h(1283)=4705 */ {1283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4705_l1}, +/*h(12229)=4706 */ {12229, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4706_l1}, +/*h(13826)=4707 */ {13826, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4707_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1893)=4709 */ {1893, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4709_l1}, +/*h(10255)=4710 */ {10255, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4710_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16033)=4712 */ {16033, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4712_l1}, +/*h(2503)=4713 */ {2503, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4713_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5697)=4716 */ {5697, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4716_l1}, +/*h(14059)=4717 */ {14059, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4717_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2126)=4719 */ {2126, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4719_l1}, +/*h(14669)=4720 */ {14669, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4720_l1}, +/*h(1139)=4721 */ {1139, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4721_l1}, +/*h(16266)=4722 */ {16266, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4722_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4333)=4724 */ {4333, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4724_l1}, +/*h(1749)=4725 */ {1749, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4725_l1}, +/*h(3346)=4726 */ {3346, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4726_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15889)=4728 */ {15889, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4728_l1}, +/*h(10721)=4729 */ {10721, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4729_l1}, +/*h(8137)=4730 */ {8137, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4730_l1}, +/*h(5553)=4731 */ {5553, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4731_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4566)=4733 */ {4566, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4733_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6163)=4735 */ {6163, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13538)=4738 */ {13538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4738_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12551)=4740 */ {12551, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4740_l1}, +/*h(9967)=4741 */ {9967, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4741_l1}, +/*h(7383)=4742 */ {7383, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4742_l1}, +/*h(15745)=4743 */ {15745, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4743_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14758)=4745 */ {14758, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4745_l1}, +/*h(12174)=4746 */ {12174, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4746_l1}, +/*h(16355)=4747 */ {16355, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4747_l1}, +/*h(13771)=4748 */ {13771, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4748_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6019)=4750 */ {6019, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15978)=4753 */ {15978, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4753_l1}, +/*h(13394)=4754 */ {13394, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4754_l1}, +/*h(4045)=4755 */ {4045, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4755_l1}, +/*h(12407)=4756 */ {12407, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15601)=4759 */ {15601, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4759_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10433)=4761 */ {10433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4761_l1}, +/*h(16211)=4762 */ {16211, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4762_l1}, +/*h(9446)=4763 */ {9446, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4763_l1}, +/*h(97)=4764 */ {97, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4764_l1}, +/*h(8459)=4765 */ {8459, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4765_l1}, +/*h(5875)=4766 */ {5875, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4766_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11653)=4768 */ {11653, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4768_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10666)=4770 */ {10666, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4770_l1}, +/*h(8082)=4771 */ {8082, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4771_l1}, +/*h(12263)=4772 */ {12263, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4772_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15457)=4774 */ {15457, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4774_l1}, +/*h(1927)=4775 */ {1927, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4775_l1}, +/*h(10289)=4776 */ {10289, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4776_l1}, +/*h(14470)=4777 */ {14470, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4777_l1}, +/*h(16067)=4778 */ {16067, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4778_l1}, +/*h(2537)=4779 */ {2537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4779_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3147)=4782 */ {3147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4782_l1}, +/*h(11509)=4783 */ {11509, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4783_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6341)=4785 */ {6341, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4785_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12119)=4787 */ {12119, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4787_l1}, +/*h(5354)=4788 */ {5354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4367)=4790 */ {4367, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4790_l1}, +/*h(1783)=4791 */ {1783, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4791_l1}, +/*h(14326)=4792 */ {14326, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4792_l1}, +/*h(7561)=4793 */ {7561, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4793_l1}, +/*h(15923)=4794 */ {15923, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4794_l1}, +/*h(6574)=4795 */ {6574, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4795_l1}, +/*h(8171)=4796 */ {8171, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4796_l1}, +/*h(5587)=4797 */ {5587, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4797_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(419)=4799 */ {419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4799_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10378)=4801 */ {10378, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4801_l1}, +/*h(7794)=4802 */ {7794, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4802_l1}, +/*h(11975)=4803 */ {11975, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(42)=4805 */ {42, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4805_l1}, +/*h(12585)=4806 */ {12585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4806_l1}, +/*h(10001)=4807 */ {10001, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4807_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15779)=4809 */ {15779, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4809_l1}, +/*h(2249)=4810 */ {2249, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4810_l1}, +/*h(3846)=4811 */ {3846, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4811_l1}, +/*h(1262)=4812 */ {1262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4812_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(275)=4814 */ {275, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4814_l1}, +/*h(15402)=4815 */ {15402, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4815_l1}, +/*h(6053)=4816 */ {6053, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4816_l1}, +/*h(14415)=4817 */ {14415, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4817_l1}, +/*h(7650)=4818 */ {7650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4818_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2482)=4820 */ {2482, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4820_l1}, +/*h(4079)=4821 */ {4079, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4821_l1}, +/*h(1495)=4822 */ {1495, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4822_l1}, +/*h(14038)=4823 */ {14038, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4823_l1}, +/*h(7273)=4824 */ {7273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4824_l1}, +/*h(15635)=4825 */ {15635, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7883)=4827 */ {7883, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4827_l1}, +/*h(5299)=4828 */ {5299, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4828_l1}, +/*h(16245)=4829 */ {16245, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4829_l1}, +/*h(131)=4830 */ {131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4830_l1}, +/*h(8493)=4831 */ {8493, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4831_l1}, +/*h(12674)=4832 */ {12674, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4832_l1}, +/*h(10090)=4833 */ {10090, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4833_l1}, +/*h(11687)=4834 */ {11687, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4834_l1}, +/*h(2338)=4835 */ {2338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4835_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1351)=4837 */ {1351, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4837_l1}, +/*h(9713)=4838 */ {9713, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4838_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4545)=4840 */ {4545, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4840_l1}, +/*h(1961)=4841 */ {1961, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4841_l1}, +/*h(3558)=4842 */ {3558, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4842_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16101)=4844 */ {16101, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4844_l1}, +/*h(13517)=4845 */ {13517, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4845_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12530)=4847 */ {12530, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4847_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7362)=4849 */ {7362, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4849_l1}, +/*h(11543)=4850 */ {11543, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4850_l1}, +/*h(6375)=4851 */ {6375, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4851_l1}, +/*h(3791)=4852 */ {3791, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4852_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13750)=4855 */ {13750, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4855_l1}, +/*h(8582)=4856 */ {8582, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4856_l1}, +/*h(5998)=4857 */ {5998, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4857_l1}, +/*h(3414)=4858 */ {3414, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4858_l1}, +/*h(7595)=4859 */ {7595, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4859_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8205)=4862 */ {8205, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4862_l1}, +/*h(12386)=4863 */ {12386, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4863_l1}, +/*h(9802)=4864 */ {9802, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4864_l1}, +/*h(7218)=4865 */ {7218, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4865_l1}, +/*h(2050)=4866 */ {2050, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4866_l1}, +/*h(6231)=4867 */ {6231, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4867_l1}, +/*h(14593)=4868 */ {14593, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4868_l1}, +/*h(12009)=4869 */ {12009, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4869_l1}, +/*h(9425)=4870 */ {9425, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4870_l1}, +/*h(4257)=4871 */ {4257, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4871_l1}, +/*h(8438)=4872 */ {8438, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4872_l1}, +/*h(10035)=4873 */ {10035, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4873_l1}, +/*h(3270)=4874 */ {3270, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4874_l1}, +/*h(15813)=4875 */ {15813, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4875_l1}, +/*h(2283)=4876 */ {2283, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4876_l1}, +/*h(10645)=4877 */ {10645, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4877_l1}, +/*h(12242)=4878 */ {12242, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4878_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(309)=4880 */ {309, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4880_l1}, +/*h(4490)=4881 */ {4490, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4881_l1}, +/*h(1906)=4882 */ {1906, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4882_l1}, +/*h(14449)=4883 */ {14449, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4883_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9281)=4885 */ {9281, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4885_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4113)=4887 */ {4113, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4887_l1}, +/*h(8294)=4888 */ {8294, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4888_l1}, +/*h(9891)=4889 */ {9891, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4889_l1}, +/*h(7307)=4890 */ {7307, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4890_l1}, +/*h(15669)=4891 */ {15669, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4891_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7917)=4893 */ {7917, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4893_l1}, +/*h(12098)=4894 */ {12098, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4894_l1}, +/*h(16279)=4895 */ {16279, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4895_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1762)=4897 */ {1762, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4897_l1}, +/*h(5943)=4898 */ {5943, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4898_l1}, +/*h(14305)=4899 */ {14305, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4899_l1}, +/*h(11721)=4900 */ {11721, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4900_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10734)=4902 */ {10734, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4902_l1}, +/*h(3969)=4903 */ {3969, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4903_l1}, +/*h(12331)=4904 */ {12331, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4904_l1}, +/*h(9747)=4905 */ {9747, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4905_l1}, +/*h(4579)=4906 */ {4579, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4906_l1}, +/*h(1995)=4907 */ {1995, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4907_l1}, +/*h(10357)=4908 */ {10357, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4908_l1}, +/*h(14538)=4909 */ {14538, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4909_l1}, +/*h(16135)=4910 */ {16135, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4910_l1}, +/*h(13551)=4911 */ {13551, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4911_l1}, +/*h(21)=4912 */ {21, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4912_l1}, +/*h(1618)=4913 */ {1618, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4913_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14161)=4915 */ {14161, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4915_l1}, +/*h(15758)=4916 */ {15758, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4916_l1}, +/*h(6409)=4917 */ {6409, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4917_l1}, +/*h(3825)=4918 */ {3825, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4918_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9603)=4920 */ {9603, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10213)=4924 */ {10213, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4924_l1}, +/*h(11810)=4925 */ {11810, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4925_l1}, +/*h(9226)=4926 */ {9226, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4926_l1}, +/*h(6642)=4927 */ {6642, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4927_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1474)=4929 */ {1474, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4929_l1}, +/*h(14017)=4930 */ {14017, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4930_l1}, +/*h(11433)=4931 */ {11433, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4931_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10446)=4933 */ {10446, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4933_l1}, +/*h(3681)=4934 */ {3681, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4934_l1}, +/*h(1097)=4935 */ {1097, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4935_l1}, +/*h(9459)=4936 */ {9459, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4936_l1}, +/*h(4291)=4937 */ {4291, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4937_l1}, +/*h(1707)=4938 */ {1707, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4938_l1}, +/*h(10069)=4939 */ {10069, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4939_l1}, +/*h(14250)=4940 */ {14250, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4940_l1}, +/*h(15847)=4941 */ {15847, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4941_l1}, +/*h(2317)=4942 */ {2317, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4942_l1}, +/*h(3914)=4943 */ {3914, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4943_l1}, +/*h(1330)=4944 */ {1330, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4944_l1}, +/*h(5511)=4945 */ {5511, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4945_l1}, +/*h(13873)=4946 */ {13873, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4946_l1}, +/*h(343)=4947 */ {343, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4947_l1}, +/*h(6121)=4948 */ {6121, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4948_l1}, +/*h(3537)=4949 */ {3537, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4949_l1}, +/*h(14483)=4950 */ {14483, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4950_l1}, +/*h(9315)=4951 */ {9315, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4951_l1}, +/*h(2550)=4952 */ {2550, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4952_l1}, +/*h(4147)=4953 */ {4147, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4953_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9925)=4955 */ {9925, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4955_l1}, +/*h(11522)=4956 */ {11522, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4956_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6354)=4958 */ {6354, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4958_l1}, +/*h(7951)=4959 */ {7951, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4959_l1}, +/*h(5367)=4960 */ {5367, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4960_l1}, +/*h(13729)=4961 */ {13729, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4961_l1}, +/*h(199)=4962 */ {199, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4962_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12742)=4964 */ {12742, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4964_l1}, +/*h(14339)=4965 */ {14339, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4965_l1}, +/*h(11755)=4966 */ {11755, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1419)=4969 */ {1419, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4969_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13962)=4971 */ {13962, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4971_l1}, +/*h(15559)=4972 */ {15559, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4972_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10391)=4974 */ {10391, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4974_l1}, +/*h(3626)=4975 */ {3626, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4975_l1}, +/*h(16169)=4976 */ {16169, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4976_l1}, +/*h(13585)=4977 */ {13585, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4977_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8417)=4979 */ {8417, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4979_l1}, +/*h(5833)=4980 */ {5833, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4980_l1}, +/*h(14195)=4981 */ {14195, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4981_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2262)=4983 */ {2262, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4983_l1}, +/*h(14805)=4984 */ {14805, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4984_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9637)=4986 */ {9637, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8650)=4988 */ {8650, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4988_l1}, +/*h(6066)=4989 */ {6066, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4989_l1}, +/*h(10247)=4990 */ {10247, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4990_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13441)=4993 */ {13441, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4993_l1}, +/*h(8273)=4994 */ {8273, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4994_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14051)=4996 */ {14051, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4996_l1}, +/*h(11467)=4997 */ {11467, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4997_l1}, +/*h(2118)=4998 */ {2118, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_4998_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14661)=5000 */ {14661, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5000_l1}, +/*h(1131)=5001 */ {1131, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5001_l1}, +/*h(9493)=5002 */ {9493, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5002_l1}, +/*h(4325)=5003 */ {4325, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5003_l1}, +/*h(1741)=5004 */ {1741, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5004_l1}, +/*h(10103)=5005 */ {10103, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5005_l1}, +/*h(3338)=5006 */ {3338, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5006_l1}, +/*h(15881)=5007 */ {15881, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5007_l1}, +/*h(2351)=5008 */ {2351, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5008_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8129)=5010 */ {8129, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5010_l1}, +/*h(5545)=5011 */ {5545, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5011_l1}, +/*h(13907)=5012 */ {13907, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5012_l1}, +/*h(4558)=5013 */ {4558, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5013_l1}, +/*h(6155)=5014 */ {6155, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5014_l1}, +/*h(3571)=5015 */ {3571, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5015_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16114)=5017 */ {16114, xed3_phash_find_maplegacy_map1_opcode0x1_vv0_5017_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5019ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1111}, +/*h(1)=1 0x0F 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1112} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1113}, +/*h(1)=1 0x0F 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1114} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x05 not64 IGNORE66()*/ {2004}, +/*h(1)=1 0x0F 0x05 not64 IGNORE66()*/ {2004}, +/*h(2)=2 0x0F 0x05 mode64 FORCE64()*/ {1115} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6_vv0(const xed_decoded_inst_t* d) +{ +return 1116; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x07 not64*/ {0, 2005}, +/*h(5)=1 0x0F 0x07 not64*/ {5, 2005}, +/*h(2)=2 0x0F 0x07 mode64 norexw_prefix*/ {2, 1117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(4)=5 0x0F 0x07 not64*/ {4, 2005}, +/*empty slot1 */ {0,0}, +/*h(1)=7 0x0F 0x07 not64*/ {1, 2005}, +/*h(6)=8 0x0F 0x07 mode64 rexw_prefix*/ {6, 1118}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8_vv0(const xed_decoded_inst_t* d) +{ +return 1384; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[7] = { +/*h(0)=0 0x0F 0x09 WBNOINVD=0*/ {0, 2152}, +/*h(2)=1 0x0F 0x09 WBNOINVD=0*/ {2, 2152}, +/*h(7)=2 0x0F 0x09 WBNOINVD=1 f3_refining_prefix*/ {7, 2154}, +/*h(4)=3 0x0F 0x09 WBNOINVD=1 REP!=3*/ {4, 2153}, +/*h(6)=4 0x0F 0x09 WBNOINVD=1 REP!=3*/ {6, 2153}, +/*h(3)=5 0x0F 0x09 WBNOINVD=0*/ {3, 2152}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_WBNOINVD(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 7ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb_vv0(const xed_decoded_inst_t* d) +{ +return 1390; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0x0F 0x0D MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1937}, +/*h(1)=1 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(2)=2 0x0F 0x0D MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {1938}, +/*h(3)=3 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(4)=4 0x0F 0x0D MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {2151}, +/*h(5)=5 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(6)=6 0x0F 0x0D MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1939}, +/*h(7)=7 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(8)=8 0x0F 0x0D MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {1940}, +/*h(9)=9 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(10)=10 0x0F 0x0D MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1941}, +/*h(11)=11 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(12)=12 0x0F 0x0D MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {1942}, +/*h(13)=13 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696}, +/*h(14)=14 0x0F 0x0D MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1943}, +/*h(15)=15 0x0F 0x0D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {696} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe_vv0(const xed_decoded_inst_t* d) +{ +return 1955; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x10_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x10 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1119}, +/*h(10)=1 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1147}, +/*h(12)=2 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1127}, +/*h(1)=3 0x0F 0x10 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1120}, +/*h(11)=4 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1148}, +/*h(13)=5 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1128}, +/*h(2)=6 0x0F 0x10 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1135}, +/*h(8)=7 0x0F 0x10 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1147}, +/*h(14)=8 0x0F 0x10 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1127}, +/*h(3)=9 0x0F 0x10 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1136}, +/*h(9)=10 0x0F 0x10 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1148}, +/*h(15)=11 0x0F 0x10 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1128} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x11_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x11 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1121}, +/*h(10)=1 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1149}, +/*h(12)=2 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1129}, +/*h(1)=3 0x0F 0x11 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1122}, +/*h(11)=4 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1150}, +/*h(13)=5 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1130}, +/*h(2)=6 0x0F 0x11 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1137}, +/*h(8)=7 0x0F 0x11 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1149}, +/*h(14)=8 0x0F 0x11 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1129}, +/*h(3)=9 0x0F 0x11 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1138}, +/*h(9)=10 0x0F 0x11 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1150}, +/*h(15)=11 0x0F 0x11 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1130} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x12_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[11] = { +/*h(0)=0 0x0F 0x12 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 759}, +/*h(8)=1 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1151}, +/*h(11)=2 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1152}, +/*h(14)=3 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1131}, +/*h(1)=4 0x0F 0x12 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 758}, +/*h(9)=5 0x0F 0x12 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1152}, +/*h(12)=6 0x0F 0x12 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1131}, +/*h(15)=7 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1132}, +/*h(2)=8 0x0F 0x12 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1139}, +/*h(10)=9 0x0F 0x12 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1151}, +/*h(13)=10 0x0F 0x12 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((4*key % 31) % 11); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x13_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x13 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 760}, +/*h(2)=1 0x0F 0x13 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1140} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x14_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x14 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1123}, +/*h(1)=1 0x0F 0x14 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1124}, +/*h(2)=2 0x0F 0x14 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1141}, +/*h(3)=3 0x0F 0x14 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1142} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x15_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x15 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1125}, +/*h(1)=1 0x0F 0x15 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1126}, +/*h(2)=2 0x0F 0x15 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1143}, +/*h(3)=3 0x0F 0x15 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1144} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x16_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[7] = { +/*h(0)=0 0x0F 0x16 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 762}, +/*h(14)=1 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1133}, +/*h(12)=2 0x0F 0x16 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1133}, +/*h(1)=3 0x0F 0x16 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 761}, +/*h(15)=4 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1134}, +/*h(13)=5 0x0F 0x16 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1134}, +/*h(2)=6 0x0F 0x16 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1145} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 7); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x17_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x17 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 763}, +/*h(2)=1 0x0F 0x17 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1146} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x18_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0x0F 0x18 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {672}, +/*h(1)=1 0x0F 0x18 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {676}, +/*h(2)=2 0x0F 0x18 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {673}, +/*h(3)=3 0x0F 0x18 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {677}, +/*h(4)=4 0x0F 0x18 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {674}, +/*h(5)=5 0x0F 0x18 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {678}, +/*h(6)=6 0x0F 0x18 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {675}, +/*h(7)=7 0x0F 0x18 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {679}, +/*h(8)=8 0x0F 0x18 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {680}, +/*h(9)=9 0x0F 0x18 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {681}, +/*h(10)=10 0x0F 0x18 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {682}, +/*h(11)=11 0x0F 0x18 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {683}, +/*h(12)=12 0x0F 0x18 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {686}, +/*h(13)=13 0x0F 0x18 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {684}, +/*h(14)=14 0x0F 0x18 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {687}, +/*h(15)=15 0x0F 0x18 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {685} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x19_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {688}, +/*h(1)=1 0x0F 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {689} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(687)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {687, 700}, +/*h(77)=1 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {77, 697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(93)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 93; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(719)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {719, 2041}, +/*h(109)=1 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {109, 697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(78)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 78; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(94)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 94; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(110)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 110; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(79)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 79; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(849)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {849, 2036}, +/*h(95)=1 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {95, 697} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(111)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {111, 697}, +/*h(721)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {721, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(623)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {623, 2040}, +/*h(13)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(902)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {902, 702}, +/*h(525)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {525, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(781)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(141)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {141, 700}, +/*h(751)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {751, 2040} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(653)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(909)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 29; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(541)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(797)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(534)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {534, 702}, +/*h(157)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {157, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(669)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(171)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {171, 702}, +/*h(925)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {925, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(45)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 700}, +/*h(655)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {655, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(934)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {934, 702}, +/*h(557)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {557, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(813)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(783)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {783, 700}, +/*h(173)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {173, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(918)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {918, 702}, +/*h(685)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {685, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(941)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {14, 700}, +/*h(1001)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {1001, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(526)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {526, 700}, +/*h(149)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {149, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(782)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(654)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(910)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 30; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(542)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {542, 700}, +/*h(919)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {919, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(798)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {158, 700}, +/*h(535)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {535, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(670)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(926)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {926, 700}, +/*h(549)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {549, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(46)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 46; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(558)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {558, 700}, +/*h(791)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {791, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(814)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(174)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1002)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {1002, 2036}, +/*h(15)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {150, 702}, +/*h(527)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {527, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(143)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(678)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {678, 702}, +/*h(911)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {911, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(31)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 31; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(543)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(799)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(159)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {159, 700}, +/*h(769)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {769, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(671)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(550)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {550, 702}, +/*h(927)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {927, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(657)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {657, 702}, +/*h(47)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(559)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(815)=0 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {815, 700}, +/*h(205)=1 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {205, 2045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(785)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {785, 702}, +/*h(175)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {175, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(710)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {710, 2039}, +/*h(943)=1 0x0F 0x1A MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {943, 700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(234)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {234, 2048}, +/*h(1)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1, 702}, +/*h(611)=2 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {611, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(513)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(129)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {129, 702}, +/*h(739)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {739, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(874)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {874, 2036}, +/*h(641)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {641, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(897)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 17; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(906)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {906, 702}, +/*h(529)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {529, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(522)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {522, 702}, +/*h(145)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {145, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(913)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(33)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {33, 702}, +/*h(643)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {643, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(778)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {778, 702}, +/*h(545)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {545, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(801)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(771)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {771, 702}, +/*h(161)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {161, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(673)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(929)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 5; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(517)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1006)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64*/ {1006, 2037}, +/*h(773)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {773, 702}, +/*h(19)=2 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {19, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(133)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(645)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {645, 702}, +/*h(35)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {35, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(901)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 21; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(533)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 533; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(789)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(661)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(917)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(37)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 37; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(805)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(165)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {165, 702}, +/*h(775)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {775, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(677)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(933)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9, 702}, +/*h(619)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {619, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(521)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(777)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {777, 702}, +/*h(167)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {167, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(747)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {747, 2039}, +/*h(514)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {514, 702}, +/*h(137)=2 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {137, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(39)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {39, 702}, +/*h(649)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {649, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(905)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 25; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(914)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {914, 702}, +/*h(537)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {537, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(793)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(153)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(665)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(921)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(651)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {651, 702}, +/*h(41)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {41, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(553)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(809)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(546)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {546, 702}, +/*h(169)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {169, 702}, +/*h(779)=2 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {779, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(681)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(937)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 702}, +/*h(989)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {989, 2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(770)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(130)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(642)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(898)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(18)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {18, 702}, +/*h(1005)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64*/ {1005, 2037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(530)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {530, 702}, +/*h(907)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {907, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(786)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(146)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(658)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(34)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 34; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(802)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(162)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {162, 702}, +/*h(539)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {539, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(674)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(930)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 702}, +/*h(993)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {993, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(518)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(774)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {774, 702}, +/*h(1007)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64*/ {1007, 2037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(134)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(646)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 22; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(790)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(662)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(38)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 38; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(806)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(166)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 702}, +/*h(997)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {997, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(138)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {138, 702}, +/*h(515)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {515, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(650)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(538)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {538, 702}, +/*h(915)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {915, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(794)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(154)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(666)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {666, 702}, +/*h(899)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {899, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(922)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(42)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 42; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(554)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(810)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {810, 702}, +/*h(577)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {577, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(170)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {170, 702}, +/*h(547)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {547, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(682)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(938)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(990)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {990, 2038}, +/*h(3)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3, 702}, +/*h(613)=2 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {613, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((8*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(741)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {741, 2039}, +/*h(131)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {131, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(531)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(787)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(147)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(659)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(803)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(163)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(675)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(931)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(617)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {617, 2039}, +/*h(7)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(519)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(135)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {135, 702}, +/*h(745)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {745, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(647)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(903)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(23)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 23; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(151)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(663)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(551)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(807)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(679)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(935)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(998)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {998, 2036}, +/*h(11)=1 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11, 702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(523)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(139)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(27)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 27; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(155)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(667)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(923)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(43)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 43; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(555)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(811)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(683)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(939)=0 0x0F 0x1A MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {702} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(833)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {833, 2036}, +/*h(223)=1 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {223, 2045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(961)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(977)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(865)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(837)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(965)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(853)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(981)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(869)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(231)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {231, 2048}, +/*h(841)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {841, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(969)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(857)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(985)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(873)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(834)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(962)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {962, 2036}, +/*h(729)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {729, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(850)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {978, 2036}, +/*h(601)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {601, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(866)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(994)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(838)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(966)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {966, 2036}, +/*h(589)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {589, 2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(854)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {854, 2036}, +/*h(621)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {621, 2040} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(982)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {982, 2036}, +/*h(605)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {605, 2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(870)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(842)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {842, 2036}, +/*h(609)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {609, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(970)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {970, 2036}, +/*h(593)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {593, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(858)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(225)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {225, 2048}, +/*h(835)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {835, 2036}, +/*h(602)=2 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {602, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(586)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {586, 2039}, +/*h(963)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {963, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(851)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(979)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(867)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_385_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(618)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {618, 2039}, +/*h(995)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {995, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(839)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {839, 2036}, +/*h(229)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {229, 2048} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(967)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(622)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {622, 2040}, +/*h(855)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {855, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(606)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {606, 2041}, +/*h(983)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {983, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(871)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(999)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(843)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(594)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {594, 2039}, +/*h(971)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {971, 2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(859)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(987)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(875)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1003)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2036} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 1003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(877)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64*/ {2037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 877; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(878)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64*/ {2037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(879)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix mode64*/ {2037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(845)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {845, 2038}, +/*h(235)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {235, 2048} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(973)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(861)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(846)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(974)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(862)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(237)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {237, 2045}, +/*h(847)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {847, 2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(742)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {742, 2039}, +/*h(975)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {975, 2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(863)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(614)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {614, 2039}, +/*h(991)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix not64*/ {991, 2038} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(705)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(737)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(581)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 581; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(99)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {99, 2054}, +/*h(709)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {709, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(597)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(725)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(585)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(713)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {713, 2039}, +/*h(103)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {103, 2055} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(578)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(610)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {610, 2039}, +/*h(233)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {233, 2048} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(582)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(598)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {598, 2039}, +/*h(221)=1 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {221, 2045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(726)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(202)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32*/ {202, 2046}, +/*h(579)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {579, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(707)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {707, 2039}, +/*h(97)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {97, 2054} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(595)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(723)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(206)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {206, 2045}, +/*h(583)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {583, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(711)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(599)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(727)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(238)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {238, 2045}, +/*h(615)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {615, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(743)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(587)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(105)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {105, 2056}, +/*h(715)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {715, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {226, 2048}, +/*h(603)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {603, 2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(731)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(749)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {2040} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(750)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {2040} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(717)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(733)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(590)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(718)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(734)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(214)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32*/ {214, 2047}, +/*h(591)=1 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {591, 2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(607)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(735)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(222)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {2045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(207)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {2045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 207; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(239)=0 0x0F 0x1A MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {2045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(194)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32*/ {2046} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(198)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32*/ {2046} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32*/ {2047} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(218)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32*/ {2047} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(230)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {2048} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {2048} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(66)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2053} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 66; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(82)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2053} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 82; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(70)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2053} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 70; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(86)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2053} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 86; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(74)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2053} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 74; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(90)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2053} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 90; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(98)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2054} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 98; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(101)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2055} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(102)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2055} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(106)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2056} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(107)=0 0x0F 0x1A MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2056} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1a_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[408] = { +/*h(233)=0 */ {233, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_0_l1}, +/*h(843)=1 */ {843, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(555)=3 */ {555, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(34)=5 */ {34, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_5_l1}, +/*h(877)=6 */ {877, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_6_l1}, +/*h(733)=7 */ {733, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_7_l1}, +/*h(589)=8 */ {589, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_8_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(678)=11 */ {678, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_11_l1}, +/*h(534)=12 */ {534, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_12_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(623)=14 */ {623, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(102)=16 */ {102, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(801)=18 */ {801, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_18_l1}, +/*h(657)=19 */ {657, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_19_l1}, +/*h(513)=20 */ {513, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_20_l1}, +/*h(746)=21 */ {746, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_21_l1}, +/*h(979)=22 */ {979, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_22_l1}, +/*h(225)=23 */ {225, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_23_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(547)=26 */ {547, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_26_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26)=28 */ {26, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_28_l1}, +/*h(869)=29 */ {869, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_29_l1}, +/*h(725)=30 */ {725, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_30_l1}, +/*h(581)=31 */ {581, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_31_l1}, +/*h(814)=32 */ {814, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_32_l1}, +/*h(670)=33 */ {670, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_33_l1}, +/*h(903)=34 */ {903, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_34_l1}, +/*h(149)=35 */ {149, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_35_l1}, +/*h(5)=36 */ {5, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_36_l1}, +/*h(238)=37 */ {238, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_37_l1}, +/*h(94)=38 */ {94, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_38_l1}, +/*h(937)=39 */ {937, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(793)=41 */ {793, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_41_l1}, +/*h(39)=42 */ {39, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=44 */ {738, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_44_l1}, +/*h(594)=45 */ {594, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_45_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(683)=47 */ {683, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(539)=49 */ {539, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_49_l1}, +/*h(1005)=50 */ {1005, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_50_l1}, +/*h(861)=51 */ {861, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_51_l1}, +/*h(107)=52 */ {107, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_52_l1}, +/*h(717)=53 */ {717, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(806)=55 */ {806, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_55_l1}, +/*h(662)=56 */ {662, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_56_l1}, +/*h(518)=57 */ {518, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_57_l1}, +/*h(751)=58 */ {751, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_58_l1}, +/*h(607)=59 */ {607, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_59_l1}, +/*h(230)=60 */ {230, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_60_l1}, +/*h(86)=61 */ {86, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_61_l1}, +/*h(929)=62 */ {929, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_62_l1}, +/*h(785)=63 */ {785, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_63_l1}, +/*h(31)=64 */ {31, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_64_l1}, +/*h(874)=65 */ {874, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(730)=67 */ {730, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_67_l1}, +/*h(586)=68 */ {586, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_68_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(675)=70 */ {675, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_70_l1}, +/*h(531)=71 */ {531, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_71_l1}, +/*h(154)=72 */ {154, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_72_l1}, +/*h(997)=73 */ {997, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_73_l1}, +/*h(853)=74 */ {853, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_74_l1}, +/*h(99)=75 */ {99, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_75_l1}, +/*h(942)=76 */ {942, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_76_l1}, +/*h(798)=77 */ {798, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(654)=79 */ {654, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_79_l1}, +/*h(133)=80 */ {133, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_80_l1}, +/*h(743)=81 */ {743, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_81_l1}, +/*h(599)=82 */ {599, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_82_l1}, +/*h(222)=83 */ {222, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_83_l1}, +/*h(78)=84 */ {78, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_84_l1}, +/*h(921)=85 */ {921, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_85_l1}, +/*h(167)=86 */ {167, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_86_l1}, +/*h(23)=87 */ {23, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_87_l1}, +/*h(866)=88 */ {866, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_88_l1}, +/*h(722)=89 */ {722, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_89_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(578)=91 */ {578, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_91_l1}, +/*h(811)=92 */ {811, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_92_l1}, +/*h(667)=93 */ {667, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_93_l1}, +/*h(523)=94 */ {523, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_94_l1}, +/*h(146)=95 */ {146, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_95_l1}, +/*h(989)=96 */ {989, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_96_l1}, +/*h(235)=97 */ {235, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_97_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(934)=99 */ {934, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_99_l1}, +/*h(790)=100 */ {790, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_100_l1}, +/*h(646)=101 */ {646, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_101_l1}, +/*h(879)=102 */ {879, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(735)=104 */ {735, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_104_l1}, +/*h(214)=105 */ {214, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(70)=107 */ {70, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_107_l1}, +/*h(913)=108 */ {913, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_108_l1}, +/*h(769)=109 */ {769, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_109_l1}, +/*h(1002)=110 */ {1002, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_110_l1}, +/*h(858)=111 */ {858, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_111_l1}, +/*h(714)=112 */ {714, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_112_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(803)=114 */ {803, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_114_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(659)=116 */ {659, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_116_l1}, +/*h(515)=117 */ {515, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_117_l1}, +/*h(981)=118 */ {981, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_118_l1}, +/*h(227)=119 */ {227, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_119_l1}, +/*h(837)=120 */ {837, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(549)=122 */ {549, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_122_l1}, +/*h(782)=123 */ {782, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(871)=125 */ {871, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_125_l1}, +/*h(727)=126 */ {727, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(206)=128 */ {206, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(905)=130 */ {905, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_130_l1}, +/*h(151)=131 */ {151, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_131_l1}, +/*h(994)=132 */ {994, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_132_l1}, +/*h(617)=133 */ {617, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_133_l1}, +/*h(850)=134 */ {850, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_134_l1}, +/*h(706)=135 */ {706, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_135_l1}, +/*h(939)=136 */ {939, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_136_l1}, +/*h(795)=137 */ {795, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_137_l1}, +/*h(651)=138 */ {651, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(130)=140 */ {130, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_140_l1}, +/*h(973)=141 */ {973, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(918)=144 */ {918, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_144_l1}, +/*h(541)=145 */ {541, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_145_l1}, +/*h(1007)=146 */ {1007, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(863)=148 */ {863, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_148_l1}, +/*h(719)=149 */ {719, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(198)=151 */ {198, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(897)=153 */ {897, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_153_l1}, +/*h(143)=154 */ {143, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_154_l1}, +/*h(986)=155 */ {986, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_155_l1}, +/*h(609)=156 */ {609, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(931)=158 */ {931, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_158_l1}, +/*h(554)=159 */ {554, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_159_l1}, +/*h(787)=160 */ {787, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_160_l1}, +/*h(643)=161 */ {643, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(965)=164 */ {965, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_164_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(677)=166 */ {677, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_166_l1}, +/*h(910)=167 */ {910, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_167_l1}, +/*h(533)=168 */ {533, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_168_l1}, +/*h(999)=169 */ {999, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_169_l1}, +/*h(622)=170 */ {622, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_170_l1}, +/*h(101)=171 */ {101, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_171_l1}, +/*h(711)=172 */ {711, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(46)=175 */ {46, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(745)=177 */ {745, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_177_l1}, +/*h(601)=178 */ {601, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_178_l1}, +/*h(834)=179 */ {834, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(923)=181 */ {923, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_181_l1}, +/*h(779)=182 */ {779, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_182_l1}, +/*h(25)=183 */ {25, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(813)=188 */ {813, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_188_l1}, +/*h(669)=189 */ {669, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_189_l1}, +/*h(902)=190 */ {902, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(614)=192 */ {614, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_192_l1}, +/*h(237)=193 */ {237, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_193_l1}, +/*h(93)=194 */ {93, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(559)=196 */ {559, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_196_l1}, +/*h(38)=197 */ {38, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(737)=200 */ {737, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_200_l1}, +/*h(593)=201 */ {593, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_201_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(682)=203 */ {682, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_203_l1}, +/*h(915)=204 */ {915, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_204_l1}, +/*h(771)=205 */ {771, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_205_l1}, +/*h(17)=206 */ {17, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(106)=208 */ {106, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(805)=211 */ {805, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_211_l1}, +/*h(661)=212 */ {661, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_212_l1}, +/*h(517)=213 */ {517, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_213_l1}, +/*h(750)=214 */ {750, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_214_l1}, +/*h(606)=215 */ {606, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_215_l1}, +/*h(229)=216 */ {229, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_216_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(551)=218 */ {551, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_218_l1}, +/*h(174)=219 */ {174, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_219_l1}, +/*h(30)=220 */ {30, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_220_l1}, +/*h(873)=221 */ {873, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(729)=223 */ {729, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_223_l1}, +/*h(585)=224 */ {585, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(674)=226 */ {674, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_226_l1}, +/*h(907)=227 */ {907, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_227_l1}, +/*h(153)=228 */ {153, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_228_l1}, +/*h(619)=229 */ {619, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_229_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(98)=231 */ {98, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_231_l1}, +/*h(941)=232 */ {941, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_232_l1}, +/*h(797)=233 */ {797, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_233_l1}, +/*h(43)=234 */ {43, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_234_l1}, +/*h(653)=235 */ {653, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(742)=237 */ {742, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_237_l1}, +/*h(221)=238 */ {221, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(687)=240 */ {687, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_240_l1}, +/*h(543)=241 */ {543, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_241_l1}, +/*h(166)=242 */ {166, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_242_l1}, +/*h(22)=243 */ {22, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_243_l1}, +/*h(865)=244 */ {865, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_244_l1}, +/*h(721)=245 */ {721, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_245_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(577)=247 */ {577, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(899)=249 */ {899, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_249_l1}, +/*h(522)=250 */ {522, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=252 */ {234, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(90)=254 */ {90, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_254_l1}, +/*h(933)=255 */ {933, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_255_l1}, +/*h(789)=256 */ {789, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_256_l1}, +/*h(35)=257 */ {35, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_257_l1}, +/*h(878)=258 */ {878, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_258_l1}, +/*h(734)=259 */ {734, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_259_l1}, +/*h(967)=260 */ {967, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_260_l1}, +/*h(590)=261 */ {590, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(679)=263 */ {679, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_263_l1}, +/*h(535)=264 */ {535, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1001)=266 */ {1001, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_266_l1}, +/*h(857)=267 */ {857, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_267_l1}, +/*h(103)=268 */ {103, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(802)=270 */ {802, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_270_l1}, +/*h(658)=271 */ {658, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(747)=273 */ {747, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(226)=275 */ {226, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_275_l1}, +/*h(82)=276 */ {82, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(171)=278 */ {171, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_278_l1}, +/*h(781)=279 */ {781, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_279_l1}, +/*h(27)=280 */ {27, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_280_l1}, +/*h(870)=281 */ {870, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_281_l1}, +/*h(726)=282 */ {726, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_282_l1}, +/*h(582)=283 */ {582, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_283_l1}, +/*h(205)=284 */ {205, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_284_l1}, +/*h(671)=285 */ {671, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(150)=287 */ {150, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_287_l1}, +/*h(993)=288 */ {993, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_288_l1}, +/*h(239)=289 */ {239, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_289_l1}, +/*h(849)=290 */ {849, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_290_l1}, +/*h(705)=291 */ {705, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_291_l1}, +/*h(938)=292 */ {938, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_292_l1}, +/*h(794)=293 */ {794, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_293_l1}, +/*h(650)=294 */ {650, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=296 */ {739, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_296_l1}, +/*h(595)=297 */ {595, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_297_l1}, +/*h(218)=298 */ {218, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_298_l1}, +/*h(74)=299 */ {74, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_299_l1}, +/*h(917)=300 */ {917, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_300_l1}, +/*h(163)=301 */ {163, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_301_l1}, +/*h(1006)=302 */ {1006, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(862)=304 */ {862, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_304_l1}, +/*h(718)=305 */ {718, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_305_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(807)=307 */ {807, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_307_l1}, +/*h(663)=308 */ {663, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_308_l1}, +/*h(519)=309 */ {519, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_309_l1}, +/*h(142)=310 */ {142, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_310_l1}, +/*h(985)=311 */ {985, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_311_l1}, +/*h(231)=312 */ {231, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(930)=314 */ {930, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_314_l1}, +/*h(553)=315 */ {553, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_315_l1}, +/*h(786)=316 */ {786, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_316_l1}, +/*h(642)=317 */ {642, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_317_l1}, +/*h(875)=318 */ {875, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_318_l1}, +/*h(731)=319 */ {731, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_319_l1}, +/*h(587)=320 */ {587, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_320_l1}, +/*h(210)=321 */ {210, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_321_l1}, +/*h(66)=322 */ {66, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_322_l1}, +/*h(909)=323 */ {909, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_323_l1}, +/*h(155)=324 */ {155, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_324_l1}, +/*h(998)=325 */ {998, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_325_l1}, +/*h(621)=326 */ {621, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(710)=328 */ {710, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_328_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(799)=330 */ {799, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_330_l1}, +/*h(655)=331 */ {655, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_331_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(134)=333 */ {134, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_333_l1}, +/*h(977)=334 */ {977, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_334_l1}, +/*h(223)=335 */ {223, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_335_l1}, +/*h(79)=336 */ {79, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_336_l1}, +/*h(922)=337 */ {922, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_337_l1}, +/*h(778)=338 */ {778, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(867)=340 */ {867, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(723)=342 */ {723, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_342_l1}, +/*h(202)=343 */ {202, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(901)=346 */ {901, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_346_l1}, +/*h(147)=347 */ {147, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_347_l1}, +/*h(613)=348 */ {613, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_348_l1}, +/*h(846)=349 */ {846, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(935)=351 */ {935, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_351_l1}, +/*h(791)=352 */ {791, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_352_l1}, +/*h(37)=353 */ {37, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_353_l1}, +/*h(647)=354 */ {647, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(969)=356 */ {969, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(681)=359 */ {681, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_359_l1}, +/*h(914)=360 */ {914, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_360_l1}, +/*h(770)=361 */ {770, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_361_l1}, +/*h(1003)=362 */ {1003, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_362_l1}, +/*h(859)=363 */ {859, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_363_l1}, +/*h(105)=364 */ {105, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(194)=366 */ {194, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(139)=369 */ {139, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_369_l1}, +/*h(749)=370 */ {749, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_370_l1}, +/*h(605)=371 */ {605, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_371_l1}, +/*h(838)=372 */ {838, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(550)=374 */ {550, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_374_l1}, +/*h(783)=375 */ {783, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_375_l1}, +/*h(29)=376 */ {29, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(961)=379 */ {961, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_379_l1}, +/*h(207)=380 */ {207, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(673)=382 */ {673, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_382_l1}, +/*h(906)=383 */ {906, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(618)=385 */ {618, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_385_l1}, +/*h(851)=386 */ {851, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_386_l1}, +/*h(97)=387 */ {97, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(42)=390 */ {42, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(741)=392 */ {741, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_392_l1}, +/*h(974)=393 */ {974, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_393_l1}, +/*h(597)=394 */ {597, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=396 */ {686, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_396_l1}, +/*h(919)=397 */ {919, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_397_l1}, +/*h(775)=398 */ {775, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_398_l1}, +/*h(21)=399 */ {21, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(110)=401 */ {110, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_401_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(809)=403 */ {809, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_403_l1}, +/*h(665)=404 */ {665, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_404_l1}, +/*h(898)=405 */ {898, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_405_l1}, +/*h(521)=406 */ {521, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_406_l1}, +/*h(987)=407 */ {987, xed3_phash_find_maplegacy_map1_opcode0x1a_vv0_407_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 408ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(687)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {687, 701}, +/*h(77)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {77, 698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(93)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 93; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(719)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {719, 2044}, +/*h(109)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {109, 698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(78)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 78; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(94)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 94; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(110)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 110; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(79)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 79; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(849)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {849, 2035}, +/*h(95)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {95, 698} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(111)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {111, 698}, +/*h(721)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {721, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(845)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {845, 699}, +/*h(235)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {235, 2052} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(973)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(861)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 703}, +/*h(989)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {989, 699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(877)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 877; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(18)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {18, 703}, +/*h(1005)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {1005, 699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(846)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(974)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(862)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(990)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {990, 699}, +/*h(3)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3, 703}, +/*h(613)=2 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {613, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((8*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(878)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1006)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {1006, 699}, +/*h(773)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {773, 703}, +/*h(19)=2 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {19, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(237)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {237, 2049}, +/*h(847)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {847, 699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(742)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {742, 2042}, +/*h(975)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {975, 699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(863)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(614)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {614, 2042}, +/*h(991)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {991, 699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(879)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(774)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {774, 703}, +/*h(1007)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] f3_refining_prefix*/ {1007, 699} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(623)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {623, 2043}, +/*h(13)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(902)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {902, 703}, +/*h(525)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {525, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(781)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(141)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {141, 701}, +/*h(751)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {751, 2043} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(653)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(909)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 29; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(541)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(797)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(534)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {534, 703}, +/*h(157)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {157, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(669)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(171)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {171, 703}, +/*h(925)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {925, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(45)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 701}, +/*h(655)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {655, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(934)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {934, 703}, +/*h(557)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {557, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(813)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(783)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {783, 701}, +/*h(173)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {173, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(918)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {918, 703}, +/*h(685)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {685, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(941)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {14, 701}, +/*h(1001)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {1001, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(526)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {526, 701}, +/*h(149)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {149, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(782)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(654)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(910)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 30; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(542)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {542, 701}, +/*h(919)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {919, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(798)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {158, 701}, +/*h(535)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {535, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(670)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(926)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {926, 701}, +/*h(549)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {549, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(46)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 46; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(558)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {558, 701}, +/*h(791)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {791, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(814)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(174)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1002)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {1002, 2035}, +/*h(15)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {150, 703}, +/*h(527)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {527, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(143)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(678)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {678, 703}, +/*h(911)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {911, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(31)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 31; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(543)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(799)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(159)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {159, 701}, +/*h(769)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {769, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(671)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(550)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {550, 703}, +/*h(927)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {927, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(657)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {657, 703}, +/*h(47)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(559)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(815)=0 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {815, 701}, +/*h(205)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {205, 2049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(785)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {785, 703}, +/*h(175)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {175, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(710)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {710, 2042}, +/*h(943)=1 0x0F 0x1B MPXMODE=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {943, 701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(234)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {234, 2052}, +/*h(1)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1, 703}, +/*h(611)=2 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {611, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(513)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(129)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {129, 703}, +/*h(739)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {739, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(874)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {874, 2035}, +/*h(641)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {641, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(897)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 17; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(906)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {906, 703}, +/*h(529)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {529, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(522)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {522, 703}, +/*h(145)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {145, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(913)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(33)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {33, 703}, +/*h(643)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {643, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(778)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {778, 703}, +/*h(545)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {545, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(801)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(771)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {771, 703}, +/*h(161)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {161, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(673)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(929)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 5; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(517)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(133)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(645)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {645, 703}, +/*h(35)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {35, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(901)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 21; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(533)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 533; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(789)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(661)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(917)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(37)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 37; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(805)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(165)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {165, 703}, +/*h(775)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {775, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(677)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(933)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9, 703}, +/*h(619)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {619, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(521)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(777)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {777, 703}, +/*h(167)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {167, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(747)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {747, 2042}, +/*h(514)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {514, 703}, +/*h(137)=2 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {137, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(39)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {39, 703}, +/*h(649)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {649, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(905)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 25; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(914)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {914, 703}, +/*h(537)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {537, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(793)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(153)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(665)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(921)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(651)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {651, 703}, +/*h(41)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {41, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(553)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(809)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(546)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {546, 703}, +/*h(169)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {169, 703}, +/*h(779)=2 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {779, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(681)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(937)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(770)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(130)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(642)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(898)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(530)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {530, 703}, +/*h(907)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {907, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(786)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(146)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(658)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(34)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 34; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(802)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(162)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {162, 703}, +/*h(539)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {539, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(674)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(930)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 703}, +/*h(993)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {993, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(518)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(134)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(646)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 22; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(790)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(662)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(38)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 38; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(806)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(166)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 703}, +/*h(997)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {997, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(138)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {138, 703}, +/*h(515)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {515, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(650)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(538)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {538, 703}, +/*h(915)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {915, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(794)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(154)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(666)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {666, 703}, +/*h(899)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {899, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(922)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(42)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 42; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(554)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(810)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {810, 703}, +/*h(577)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {577, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(170)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {170, 703}, +/*h(547)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {547, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(682)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(938)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(741)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {741, 2042}, +/*h(131)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {131, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(531)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(787)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(147)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(659)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(803)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(163)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(675)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(931)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(617)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {617, 2042}, +/*h(7)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(519)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(135)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {135, 703}, +/*h(745)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {745, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(647)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(903)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(23)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 23; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(151)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(663)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(551)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(807)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(679)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(935)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(998)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {998, 2035}, +/*h(11)=1 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11, 703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(523)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(139)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(27)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 27; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(155)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(667)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(923)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(43)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 43; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(555)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(811)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(683)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(939)=0 0x0F 0x1B MPXMODE=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {703} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(833)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {833, 2035}, +/*h(223)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {223, 2049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(961)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(977)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(865)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(837)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(965)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(853)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(981)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(869)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(231)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {231, 2052}, +/*h(841)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {841, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(969)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(857)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(985)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(873)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(834)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(962)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {962, 2035}, +/*h(729)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {729, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(850)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {978, 2035}, +/*h(601)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {601, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(866)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(994)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(838)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(966)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {966, 2035}, +/*h(589)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {589, 2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(854)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {854, 2035}, +/*h(621)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {621, 2043} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(982)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {982, 2035}, +/*h(605)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {605, 2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(870)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(842)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {842, 2035}, +/*h(609)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {609, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(970)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {970, 2035}, +/*h(593)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {593, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(858)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(225)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {225, 2052}, +/*h(835)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {835, 2035}, +/*h(602)=2 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {602, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(586)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {586, 2042}, +/*h(963)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {963, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(851)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(979)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(867)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_385_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(618)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {618, 2042}, +/*h(995)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {995, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(839)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {839, 2035}, +/*h(229)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {229, 2052} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(967)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(622)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {622, 2043}, +/*h(855)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {855, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(606)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {606, 2044}, +/*h(983)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {983, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(871)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(999)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(843)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(594)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {594, 2042}, +/*h(971)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {971, 2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(859)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(987)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(875)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1003)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f3_refining_prefix*/ {2035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 1003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(705)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(737)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(581)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 581; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(99)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {99, 2058}, +/*h(709)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {709, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(597)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(725)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(585)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(713)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {713, 2042}, +/*h(103)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {103, 2059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(578)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(610)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {610, 2042}, +/*h(233)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {233, 2052} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(582)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(598)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {598, 2042}, +/*h(221)=1 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {221, 2049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(726)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(202)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32*/ {202, 2050}, +/*h(579)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {579, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(707)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {707, 2042}, +/*h(97)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {97, 2058} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(595)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(723)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(206)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {206, 2049}, +/*h(583)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {583, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(711)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(599)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(727)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(238)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {238, 2049}, +/*h(615)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {615, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(743)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(587)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(105)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {105, 2060}, +/*h(715)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {715, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {226, 2052}, +/*h(603)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {603, 2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(731)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() f2_refining_prefix*/ {2042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(749)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {2043} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(750)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix mode64*/ {2043} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(717)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(733)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(590)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(718)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(734)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(214)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32*/ {214, 2051}, +/*h(591)=1 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {591, 2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(607)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(735)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix not64*/ {2044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(222)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {2049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(207)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {2049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 207; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(239)=0 0x0F 0x1B MPXMODE=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix REFINING66()*/ {2049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(194)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32*/ {2050} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(198)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode16 eamode32*/ {2050} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32*/ {2051} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(218)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode32 eamode32*/ {2051} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(230)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {2052} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() osz_refining_prefix REFINING66() mode64*/ {2052} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(66)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 66; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(82)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 82; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(70)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 70; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(86)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 86; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(74)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 74; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(90)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() no_refining_prefix not64 eamode32*/ {2057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 90; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(98)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=0 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2058} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 98; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(101)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(102)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=1 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(106)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2060} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(107)=0 0x0F 0x1B MPXMODE=1 MOD[mm] MOD=2 REG[rrr] RM[nnn] MODRM() no_refining_prefix mode64*/ {2060} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = key - 107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1b_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[408] = { +/*h(233)=0 */ {233, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_0_l1}, +/*h(843)=1 */ {843, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(555)=3 */ {555, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(34)=5 */ {34, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_5_l1}, +/*h(877)=6 */ {877, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_6_l1}, +/*h(733)=7 */ {733, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_7_l1}, +/*h(589)=8 */ {589, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_8_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(678)=11 */ {678, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_11_l1}, +/*h(534)=12 */ {534, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_12_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(623)=14 */ {623, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(102)=16 */ {102, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(801)=18 */ {801, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_18_l1}, +/*h(657)=19 */ {657, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_19_l1}, +/*h(513)=20 */ {513, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_20_l1}, +/*h(746)=21 */ {746, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_21_l1}, +/*h(979)=22 */ {979, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_22_l1}, +/*h(225)=23 */ {225, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_23_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(547)=26 */ {547, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_26_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26)=28 */ {26, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_28_l1}, +/*h(869)=29 */ {869, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_29_l1}, +/*h(725)=30 */ {725, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_30_l1}, +/*h(581)=31 */ {581, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_31_l1}, +/*h(814)=32 */ {814, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_32_l1}, +/*h(670)=33 */ {670, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_33_l1}, +/*h(903)=34 */ {903, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_34_l1}, +/*h(149)=35 */ {149, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_35_l1}, +/*h(5)=36 */ {5, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_36_l1}, +/*h(238)=37 */ {238, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_37_l1}, +/*h(94)=38 */ {94, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_38_l1}, +/*h(937)=39 */ {937, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(793)=41 */ {793, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_41_l1}, +/*h(39)=42 */ {39, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=44 */ {738, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_44_l1}, +/*h(594)=45 */ {594, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_45_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(683)=47 */ {683, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(539)=49 */ {539, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_49_l1}, +/*h(18)=50 */ {18, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_50_l1}, +/*h(861)=51 */ {861, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_51_l1}, +/*h(107)=52 */ {107, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_52_l1}, +/*h(717)=53 */ {717, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(806)=55 */ {806, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_55_l1}, +/*h(662)=56 */ {662, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_56_l1}, +/*h(518)=57 */ {518, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_57_l1}, +/*h(751)=58 */ {751, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_58_l1}, +/*h(607)=59 */ {607, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_59_l1}, +/*h(230)=60 */ {230, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_60_l1}, +/*h(86)=61 */ {86, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_61_l1}, +/*h(929)=62 */ {929, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_62_l1}, +/*h(785)=63 */ {785, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_63_l1}, +/*h(31)=64 */ {31, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_64_l1}, +/*h(874)=65 */ {874, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(730)=67 */ {730, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_67_l1}, +/*h(586)=68 */ {586, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_68_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(675)=70 */ {675, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_70_l1}, +/*h(531)=71 */ {531, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_71_l1}, +/*h(154)=72 */ {154, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_72_l1}, +/*h(997)=73 */ {997, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_73_l1}, +/*h(853)=74 */ {853, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_74_l1}, +/*h(99)=75 */ {99, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_75_l1}, +/*h(942)=76 */ {942, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_76_l1}, +/*h(798)=77 */ {798, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(654)=79 */ {654, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_79_l1}, +/*h(133)=80 */ {133, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_80_l1}, +/*h(743)=81 */ {743, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_81_l1}, +/*h(599)=82 */ {599, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_82_l1}, +/*h(222)=83 */ {222, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_83_l1}, +/*h(78)=84 */ {78, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_84_l1}, +/*h(921)=85 */ {921, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_85_l1}, +/*h(167)=86 */ {167, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_86_l1}, +/*h(23)=87 */ {23, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_87_l1}, +/*h(866)=88 */ {866, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_88_l1}, +/*h(722)=89 */ {722, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_89_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(578)=91 */ {578, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_91_l1}, +/*h(811)=92 */ {811, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_92_l1}, +/*h(667)=93 */ {667, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_93_l1}, +/*h(523)=94 */ {523, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_94_l1}, +/*h(146)=95 */ {146, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_95_l1}, +/*h(2)=96 */ {2, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_96_l1}, +/*h(235)=97 */ {235, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_97_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(934)=99 */ {934, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_99_l1}, +/*h(790)=100 */ {790, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_100_l1}, +/*h(646)=101 */ {646, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_101_l1}, +/*h(879)=102 */ {879, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(735)=104 */ {735, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_104_l1}, +/*h(214)=105 */ {214, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(70)=107 */ {70, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_107_l1}, +/*h(913)=108 */ {913, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_108_l1}, +/*h(769)=109 */ {769, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_109_l1}, +/*h(1002)=110 */ {1002, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_110_l1}, +/*h(858)=111 */ {858, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_111_l1}, +/*h(714)=112 */ {714, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_112_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(803)=114 */ {803, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_114_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(659)=116 */ {659, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_116_l1}, +/*h(515)=117 */ {515, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_117_l1}, +/*h(981)=118 */ {981, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_118_l1}, +/*h(227)=119 */ {227, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_119_l1}, +/*h(837)=120 */ {837, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(549)=122 */ {549, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_122_l1}, +/*h(782)=123 */ {782, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(871)=125 */ {871, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_125_l1}, +/*h(727)=126 */ {727, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(206)=128 */ {206, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(905)=130 */ {905, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_130_l1}, +/*h(151)=131 */ {151, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_131_l1}, +/*h(994)=132 */ {994, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_132_l1}, +/*h(617)=133 */ {617, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_133_l1}, +/*h(850)=134 */ {850, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_134_l1}, +/*h(706)=135 */ {706, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_135_l1}, +/*h(939)=136 */ {939, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_136_l1}, +/*h(795)=137 */ {795, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_137_l1}, +/*h(651)=138 */ {651, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(130)=140 */ {130, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_140_l1}, +/*h(973)=141 */ {973, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(918)=144 */ {918, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_144_l1}, +/*h(541)=145 */ {541, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_145_l1}, +/*h(774)=146 */ {774, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(863)=148 */ {863, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_148_l1}, +/*h(719)=149 */ {719, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(198)=151 */ {198, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(897)=153 */ {897, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_153_l1}, +/*h(143)=154 */ {143, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_154_l1}, +/*h(986)=155 */ {986, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_155_l1}, +/*h(609)=156 */ {609, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(931)=158 */ {931, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_158_l1}, +/*h(554)=159 */ {554, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_159_l1}, +/*h(787)=160 */ {787, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_160_l1}, +/*h(643)=161 */ {643, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(965)=164 */ {965, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_164_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(677)=166 */ {677, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_166_l1}, +/*h(910)=167 */ {910, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_167_l1}, +/*h(533)=168 */ {533, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_168_l1}, +/*h(999)=169 */ {999, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_169_l1}, +/*h(622)=170 */ {622, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_170_l1}, +/*h(101)=171 */ {101, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_171_l1}, +/*h(711)=172 */ {711, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(46)=175 */ {46, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(745)=177 */ {745, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_177_l1}, +/*h(601)=178 */ {601, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_178_l1}, +/*h(834)=179 */ {834, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(923)=181 */ {923, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_181_l1}, +/*h(779)=182 */ {779, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_182_l1}, +/*h(25)=183 */ {25, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(813)=188 */ {813, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_188_l1}, +/*h(669)=189 */ {669, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_189_l1}, +/*h(902)=190 */ {902, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(614)=192 */ {614, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_192_l1}, +/*h(237)=193 */ {237, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_193_l1}, +/*h(93)=194 */ {93, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(559)=196 */ {559, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_196_l1}, +/*h(38)=197 */ {38, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(737)=200 */ {737, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_200_l1}, +/*h(593)=201 */ {593, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_201_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(682)=203 */ {682, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_203_l1}, +/*h(915)=204 */ {915, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_204_l1}, +/*h(771)=205 */ {771, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_205_l1}, +/*h(17)=206 */ {17, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(106)=208 */ {106, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(805)=211 */ {805, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_211_l1}, +/*h(661)=212 */ {661, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_212_l1}, +/*h(517)=213 */ {517, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_213_l1}, +/*h(750)=214 */ {750, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_214_l1}, +/*h(606)=215 */ {606, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_215_l1}, +/*h(229)=216 */ {229, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_216_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(551)=218 */ {551, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_218_l1}, +/*h(174)=219 */ {174, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_219_l1}, +/*h(30)=220 */ {30, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_220_l1}, +/*h(873)=221 */ {873, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(729)=223 */ {729, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_223_l1}, +/*h(585)=224 */ {585, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(674)=226 */ {674, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_226_l1}, +/*h(907)=227 */ {907, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_227_l1}, +/*h(153)=228 */ {153, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_228_l1}, +/*h(619)=229 */ {619, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_229_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(98)=231 */ {98, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_231_l1}, +/*h(941)=232 */ {941, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_232_l1}, +/*h(797)=233 */ {797, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_233_l1}, +/*h(43)=234 */ {43, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_234_l1}, +/*h(653)=235 */ {653, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(742)=237 */ {742, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_237_l1}, +/*h(221)=238 */ {221, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(687)=240 */ {687, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_240_l1}, +/*h(543)=241 */ {543, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_241_l1}, +/*h(166)=242 */ {166, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_242_l1}, +/*h(22)=243 */ {22, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_243_l1}, +/*h(865)=244 */ {865, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_244_l1}, +/*h(721)=245 */ {721, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_245_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(577)=247 */ {577, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(899)=249 */ {899, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_249_l1}, +/*h(522)=250 */ {522, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=252 */ {234, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(90)=254 */ {90, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_254_l1}, +/*h(933)=255 */ {933, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_255_l1}, +/*h(789)=256 */ {789, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_256_l1}, +/*h(35)=257 */ {35, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_257_l1}, +/*h(878)=258 */ {878, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_258_l1}, +/*h(734)=259 */ {734, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_259_l1}, +/*h(967)=260 */ {967, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_260_l1}, +/*h(590)=261 */ {590, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(679)=263 */ {679, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_263_l1}, +/*h(535)=264 */ {535, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1001)=266 */ {1001, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_266_l1}, +/*h(857)=267 */ {857, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_267_l1}, +/*h(103)=268 */ {103, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(802)=270 */ {802, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_270_l1}, +/*h(658)=271 */ {658, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(747)=273 */ {747, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(226)=275 */ {226, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_275_l1}, +/*h(82)=276 */ {82, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(171)=278 */ {171, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_278_l1}, +/*h(781)=279 */ {781, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_279_l1}, +/*h(27)=280 */ {27, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_280_l1}, +/*h(870)=281 */ {870, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_281_l1}, +/*h(726)=282 */ {726, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_282_l1}, +/*h(582)=283 */ {582, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_283_l1}, +/*h(205)=284 */ {205, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_284_l1}, +/*h(671)=285 */ {671, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(150)=287 */ {150, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_287_l1}, +/*h(993)=288 */ {993, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_288_l1}, +/*h(239)=289 */ {239, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_289_l1}, +/*h(849)=290 */ {849, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_290_l1}, +/*h(705)=291 */ {705, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_291_l1}, +/*h(938)=292 */ {938, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_292_l1}, +/*h(794)=293 */ {794, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_293_l1}, +/*h(650)=294 */ {650, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=296 */ {739, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_296_l1}, +/*h(595)=297 */ {595, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_297_l1}, +/*h(218)=298 */ {218, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_298_l1}, +/*h(74)=299 */ {74, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_299_l1}, +/*h(917)=300 */ {917, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_300_l1}, +/*h(163)=301 */ {163, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_301_l1}, +/*h(19)=302 */ {19, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(862)=304 */ {862, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_304_l1}, +/*h(718)=305 */ {718, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_305_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(807)=307 */ {807, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_307_l1}, +/*h(663)=308 */ {663, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_308_l1}, +/*h(519)=309 */ {519, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_309_l1}, +/*h(142)=310 */ {142, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_310_l1}, +/*h(985)=311 */ {985, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_311_l1}, +/*h(231)=312 */ {231, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(930)=314 */ {930, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_314_l1}, +/*h(553)=315 */ {553, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_315_l1}, +/*h(786)=316 */ {786, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_316_l1}, +/*h(642)=317 */ {642, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_317_l1}, +/*h(875)=318 */ {875, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_318_l1}, +/*h(731)=319 */ {731, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_319_l1}, +/*h(587)=320 */ {587, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_320_l1}, +/*h(210)=321 */ {210, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_321_l1}, +/*h(66)=322 */ {66, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_322_l1}, +/*h(909)=323 */ {909, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_323_l1}, +/*h(155)=324 */ {155, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_324_l1}, +/*h(998)=325 */ {998, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_325_l1}, +/*h(621)=326 */ {621, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(710)=328 */ {710, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_328_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(799)=330 */ {799, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_330_l1}, +/*h(655)=331 */ {655, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_331_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(134)=333 */ {134, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_333_l1}, +/*h(977)=334 */ {977, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_334_l1}, +/*h(223)=335 */ {223, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_335_l1}, +/*h(79)=336 */ {79, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_336_l1}, +/*h(922)=337 */ {922, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_337_l1}, +/*h(778)=338 */ {778, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(867)=340 */ {867, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(723)=342 */ {723, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_342_l1}, +/*h(202)=343 */ {202, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(901)=346 */ {901, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_346_l1}, +/*h(147)=347 */ {147, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_347_l1}, +/*h(613)=348 */ {613, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_348_l1}, +/*h(846)=349 */ {846, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(935)=351 */ {935, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_351_l1}, +/*h(791)=352 */ {791, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_352_l1}, +/*h(37)=353 */ {37, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_353_l1}, +/*h(647)=354 */ {647, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(969)=356 */ {969, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(681)=359 */ {681, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_359_l1}, +/*h(914)=360 */ {914, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_360_l1}, +/*h(770)=361 */ {770, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_361_l1}, +/*h(1003)=362 */ {1003, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_362_l1}, +/*h(859)=363 */ {859, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_363_l1}, +/*h(105)=364 */ {105, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(194)=366 */ {194, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(139)=369 */ {139, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_369_l1}, +/*h(749)=370 */ {749, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_370_l1}, +/*h(605)=371 */ {605, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_371_l1}, +/*h(838)=372 */ {838, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(550)=374 */ {550, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_374_l1}, +/*h(783)=375 */ {783, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_375_l1}, +/*h(29)=376 */ {29, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(961)=379 */ {961, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_379_l1}, +/*h(207)=380 */ {207, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(673)=382 */ {673, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_382_l1}, +/*h(906)=383 */ {906, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(618)=385 */ {618, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_385_l1}, +/*h(851)=386 */ {851, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_386_l1}, +/*h(97)=387 */ {97, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(42)=390 */ {42, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(741)=392 */ {741, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_392_l1}, +/*h(974)=393 */ {974, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_393_l1}, +/*h(597)=394 */ {597, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=396 */ {686, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_396_l1}, +/*h(919)=397 */ {919, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_397_l1}, +/*h(775)=398 */ {775, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_398_l1}, +/*h(21)=399 */ {21, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(110)=401 */ {110, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_401_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(809)=403 */ {809, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_403_l1}, +/*h(665)=404 */ {665, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_404_l1}, +/*h(898)=405 */ {898, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_405_l1}, +/*h(521)=406 */ {521, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_406_l1}, +/*h(987)=407 */ {987, xed3_phash_find_maplegacy_map1_opcode0x1b_vv0_407_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 408ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[192] = { +/*h(0)=0 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=0*/ {0, 735}, +/*h(160)=1 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {160, 730}, +/*h(192)=2 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix*/ {192, 725}, +/*h(43)=3 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {43, 734}, +/*h(139)=4 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {139, 734}, +/*h(235)=5 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {235, 734}, +/*h(22)=6 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {22, 734}, +/*h(182)=7 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {182, 734}, +/*h(214)=8 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {214, 734}, +/*h(1)=9 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() no_refining_prefix CLDEMOTE=1*/ {1, 2119}, +/*h(161)=10 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {161, 730}, +/*h(193)=11 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix*/ {193, 725}, +/*h(44)=12 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {44, 731}, +/*h(140)=13 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {140, 727}, +/*h(236)=14 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {236, 731}, +/*h(23)=15 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 734}, +/*h(183)=16 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {183, 734}, +/*h(215)=17 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {215, 734}, +/*h(2)=18 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2, 734}, +/*h(162)=19 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {162, 734}, +/*h(194)=20 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {194, 734}, +/*h(45)=21 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {45, 731}, +/*h(141)=22 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {141, 727}, +/*h(237)=23 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {237, 731}, +/*h(24)=24 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {24, 729}, +/*h(184)=25 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {184, 733}, +/*h(216)=26 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {216, 729}, +/*h(3)=27 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 734}, +/*h(163)=28 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {163, 734}, +/*h(195)=29 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {195, 734}, +/*h(46)=30 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {46, 734}, +/*h(142)=31 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {142, 734}, +/*h(238)=32 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {238, 734}, +/*h(25)=33 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {25, 729}, +/*h(185)=34 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {185, 733}, +/*h(217)=35 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {217, 729}, +/*h(4)=36 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix*/ {4, 726}, +/*h(164)=37 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {164, 730}, +/*h(196)=38 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix*/ {196, 725}, +/*h(47)=39 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 734}, +/*h(143)=40 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {143, 734}, +/*h(239)=41 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {239, 734}, +/*h(26)=42 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {26, 734}, +/*h(186)=43 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {186, 734}, +/*h(218)=44 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {218, 734}, +/*h(5)=45 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() osz_refining_prefix*/ {5, 726}, +/*h(165)=46 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {165, 730}, +/*h(197)=47 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f3_refining_prefix*/ {197, 725}, +/*h(48)=48 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {48, 732}, +/*h(144)=49 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {144, 728}, +/*h(240)=50 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {240, 732}, +/*h(27)=51 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 734}, +/*h(187)=52 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {187, 734}, +/*h(219)=53 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {219, 734}, +/*h(6)=54 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {6, 734}, +/*h(166)=55 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {166, 734}, +/*h(198)=56 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {198, 734}, +/*h(49)=57 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {49, 732}, +/*h(145)=58 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {145, 728}, +/*h(241)=59 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {241, 732}, +/*h(28)=60 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {28, 729}, +/*h(188)=61 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {188, 733}, +/*h(220)=62 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {220, 729}, +/*h(7)=63 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 734}, +/*h(167)=64 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {167, 734}, +/*h(199)=65 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {199, 734}, +/*h(50)=66 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {50, 734}, +/*h(146)=67 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {146, 734}, +/*h(242)=68 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {242, 734}, +/*h(29)=69 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {29, 729}, +/*h(189)=70 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {189, 733}, +/*h(221)=71 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {221, 729}, +/*h(8)=72 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {8, 727}, +/*h(168)=73 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {168, 731}, +/*h(200)=74 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {200, 727}, +/*h(51)=75 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 734}, +/*h(147)=76 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {147, 734}, +/*h(243)=77 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {243, 734}, +/*h(30)=78 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {30, 734}, +/*h(190)=79 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {190, 734}, +/*h(222)=80 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {222, 734}, +/*h(9)=81 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {9, 727}, +/*h(169)=82 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {169, 731}, +/*h(201)=83 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {201, 727}, +/*h(52)=84 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {52, 732}, +/*h(148)=85 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {148, 728}, +/*h(244)=86 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {244, 732}, +/*h(31)=87 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 734}, +/*h(191)=88 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {191, 734}, +/*h(223)=89 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {223, 734}, +/*h(10)=90 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {10, 734}, +/*h(170)=91 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {170, 734}, +/*h(202)=92 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {202, 734}, +/*h(53)=93 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {53, 732}, +/*h(149)=94 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {149, 728}, +/*h(245)=95 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {245, 732}, +/*h(32)=96 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {32, 730}, +/*h(128)=97 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix*/ {128, 724}, +/*h(224)=98 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {224, 730}, +/*h(11)=99 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 734}, +/*h(171)=100 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {171, 734}, +/*h(203)=101 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {203, 734}, +/*h(54)=102 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {54, 734}, +/*h(150)=103 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {150, 734}, +/*h(246)=104 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {246, 734}, +/*h(33)=105 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {33, 730}, +/*h(129)=106 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix*/ {129, 724}, +/*h(225)=107 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {225, 730}, +/*h(12)=108 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {12, 727}, +/*h(172)=109 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {172, 731}, +/*h(204)=110 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {204, 727}, +/*h(55)=111 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 734}, +/*h(151)=112 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {151, 734}, +/*h(247)=113 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {247, 734}, +/*h(34)=114 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {34, 734}, +/*h(130)=115 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {130, 734}, +/*h(226)=116 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {226, 734}, +/*h(13)=117 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {13, 727}, +/*h(173)=118 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {173, 731}, +/*h(205)=119 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {205, 727}, +/*h(56)=120 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {56, 733}, +/*h(152)=121 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {152, 729}, +/*h(248)=122 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {248, 733}, +/*h(35)=123 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {35, 734}, +/*h(131)=124 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {131, 734}, +/*h(227)=125 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {227, 734}, +/*h(14)=126 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {14, 734}, +/*h(174)=127 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {174, 734}, +/*h(206)=128 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {206, 734}, +/*h(57)=129 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {57, 733}, +/*h(153)=130 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {153, 729}, +/*h(249)=131 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {249, 733}, +/*h(36)=132 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {36, 730}, +/*h(132)=133 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix*/ {132, 724}, +/*h(228)=134 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {228, 730}, +/*h(15)=135 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 734}, +/*h(175)=136 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {175, 734}, +/*h(207)=137 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {207, 734}, +/*h(58)=138 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {58, 734}, +/*h(154)=139 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {154, 734}, +/*h(250)=140 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {250, 734}, +/*h(37)=141 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {37, 730}, +/*h(133)=142 0x0F 0x1C MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() f2_refining_prefix*/ {133, 724}, +/*h(229)=143 0x0F 0x1C MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {229, 730}, +/*h(16)=144 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {16, 728}, +/*h(176)=145 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {176, 732}, +/*h(208)=146 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {208, 728}, +/*h(59)=147 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 734}, +/*h(155)=148 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {155, 734}, +/*h(251)=149 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {251, 734}, +/*h(38)=150 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {38, 734}, +/*h(134)=151 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {134, 734}, +/*h(230)=152 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {230, 734}, +/*h(17)=153 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {17, 728}, +/*h(177)=154 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {177, 732}, +/*h(209)=155 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {209, 728}, +/*h(60)=156 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {60, 733}, +/*h(156)=157 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {156, 729}, +/*h(252)=158 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {252, 733}, +/*h(39)=159 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 734}, +/*h(135)=160 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {135, 734}, +/*h(231)=161 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {231, 734}, +/*h(18)=162 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {18, 734}, +/*h(178)=163 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {178, 734}, +/*h(210)=164 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {210, 734}, +/*h(61)=165 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {61, 733}, +/*h(157)=166 0x0F 0x1C MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {157, 729}, +/*h(253)=167 0x0F 0x1C MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {253, 733}, +/*h(40)=168 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {40, 731}, +/*h(136)=169 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {136, 727}, +/*h(232)=170 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {232, 731}, +/*h(19)=171 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {19, 734}, +/*h(179)=172 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {179, 734}, +/*h(211)=173 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {211, 734}, +/*h(62)=174 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {62, 734}, +/*h(158)=175 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {158, 734}, +/*h(254)=176 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {254, 734}, +/*h(41)=177 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {41, 731}, +/*h(137)=178 0x0F 0x1C MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {137, 727}, +/*h(233)=179 0x0F 0x1C MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {233, 731}, +/*h(20)=180 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 728}, +/*h(180)=181 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {180, 732}, +/*h(212)=182 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {212, 728}, +/*h(63)=183 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 734}, +/*h(159)=184 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {159, 734}, +/*h(255)=185 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {255, 734}, +/*h(42)=186 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {42, 734}, +/*h(138)=187 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {138, 734}, +/*h(234)=188 0x0F 0x1C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {234, 734}, +/*h(21)=189 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {21, 728}, +/*h(181)=190 0x0F 0x1C MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {181, 732}, +/*h(213)=191 0x0F 0x1C MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {213, 728} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CLDEMOTE_MOD3_OSZ_REG_REP(d); +hidx = ((9*key % 863) % 192); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x1D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {690}, +/*h(1)=1 0x0F 0x1D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {691} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 704}, +/*h(10946)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10946, 706}, +/*h(4181)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4181, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((9*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6713_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(512)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {512, 704}, +/*h(11458)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11458, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1528_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13506)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13506, 705}, +/*h(2560)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2560, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4608)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4608, 704}, +/*h(15554)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15554, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5804_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6656; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2747_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1536)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1536, 704}, +/*h(12482)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12482, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3584)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3584, 704}, +/*h(14530)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14530, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7023_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5632)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1792; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(32)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 32; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2854_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1926_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11490)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11490, 705}, +/*h(544)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {544, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8640_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2592)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2592, 704}, +/*h(13538)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13538, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4640)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4640, 704}, +/*h(15586)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15586, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8736, 704}, +/*h(1971)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1971, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8040_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10784, 704}, +/*h(4019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4019, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5602_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12832, 704}, +/*h(6067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6067, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14880, 704}, +/*h(8115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8115, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_707_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1568)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1568, 704}, +/*h(12514)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12514, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7421_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14562)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14562, 705}, +/*h(3616)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3616, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2545_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7712, 704}, +/*h(947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {947, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9760, 704}, +/*h(2995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2995, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6821_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11808, 704}, +/*h(5043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5043, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13856, 704}, +/*h(7091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7091, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1945_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15904, 704}, +/*h(9139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9139, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8804_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5071_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(64)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 64; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(576)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2624)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2624; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8768, 704}, +/*h(2003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {2003, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10816, 704}, +/*h(4051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4051, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12864, 704}, +/*h(6099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6099, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14912, 704}, +/*h(8147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8147, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1600)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3648)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3648; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2943_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7744, 704}, +/*h(979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {979, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7219_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9792, 704}, +/*h(3027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3027, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4781_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11840, 704}, +/*h(5075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5075, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13888, 704}, +/*h(7123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7123, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9057_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15936, 704}, +/*h(9171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {9171, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1869_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11778, 706}, +/*h(832)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {832, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8583_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2880, 704}, +/*h(13826)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13826, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4928, 704}, +/*h(15874)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15874, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1856, 704}, +/*h(12802)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12802, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14850, 706}, +/*h(3904)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3904, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(96)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 96; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(608)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2656; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8836_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8800, 704}, +/*h(2035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2035, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3960_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10848, 704}, +/*h(4083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4083, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12896, 704}, +/*h(6131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {6131, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14944, 704}, +/*h(8179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {8179, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1632)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7776, 704}, +/*h(1011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {1011, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5179_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9824, 704}, +/*h(3059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3059, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2741_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11872, 704}, +/*h(5107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {5107, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13920, 704}, +/*h(7155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {7155, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7017_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15968, 704}, +/*h(9203)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {9203, 716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8981_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {864, 704}, +/*h(11810)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11810, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6543_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2912, 704}, +/*h(13858)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13858, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15906, 706}, +/*h(4960)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4960, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5943_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13152, 704}, +/*h(6387)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6387, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1067_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15200, 704}, +/*h(8435)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8435, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12834, 706}, +/*h(1888)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1888, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5324_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3936, 704}, +/*h(14882)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14882, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2886_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14176, 704}, +/*h(7411)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7411, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16224, 704}, +/*h(9459)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9459, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_991_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {128, 704}, +/*h(11074)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11074, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13122, 709}, +/*h(2176)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2176, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5267_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4224, 704}, +/*h(15170)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15170, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8924_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1152, 704}, +/*h(12098)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12098, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6486_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3200, 704}, +/*h(14146)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14146, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4048_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16194, 709}, +/*h(5248)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5248, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5886_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15488)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(640)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6784, 704}, +/*h(19)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {19, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8832, 704}, +/*h(2067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2067, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1920_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10880, 704}, +/*h(4115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4115, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8634_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12928, 704}, +/*h(6163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6163, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14976, 704}, +/*h(8211)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8211, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5577_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7808, 704}, +/*h(1043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1043, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9856, 704}, +/*h(3091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3091, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_701_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11904, 704}, +/*h(5139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5139, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13952, 704}, +/*h(7187)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7187, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4977_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16000, 704}, +/*h(9235)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9235, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6941_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {896, 704}, +/*h(11842)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11842, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4503_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13890, 706}, +/*h(2944)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2944, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2065_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4992, 704}, +/*h(15938)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15938, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5722_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1920, 704}, +/*h(12866)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12866, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3284_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3968, 704}, +/*h(14914)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14914, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11106, 710}, +/*h(160)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {160, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5665_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2208, 704}, +/*h(13154)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13154, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4256, 704}, +/*h(15202)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15202, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14496)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6884_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1184, 704}, +/*h(12130)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12130, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4446_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14178, 710}, +/*h(3232)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3232, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2008_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5280, 704}, +/*h(16226)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16226, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13472)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13472; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15520)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2720, 704}, +/*h(6901)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6901, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4768, 704}, +/*h(8949)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8949, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6816, 704}, +/*h(2635)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2635, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8864, 704}, +/*h(4683)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4683, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1699_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1696, 704}, +/*h(5877)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5877, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3744, 704}, +/*h(7925)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7925, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5792, 704}, +/*h(1611)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1611, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3536_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7840, 704}, +/*h(3659)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3659, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4901_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11874, 706}, +/*h(928)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {928, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2976, 704}, +/*h(13922)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13922, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5024, 704}, +/*h(15970)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15970, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3682_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1952, 704}, +/*h(12898)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12898, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14946, 706}, +/*h(4000)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4000, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6063_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {192, 704}, +/*h(11138)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11138, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3625_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2240, 704}, +/*h(13186)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13186, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15234, 711}, +/*h(4288)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4288, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8384, 704}, +/*h(1619)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1619, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3025_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10432, 704}, +/*h(3667)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3667, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12480)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12480, 704}, +/*h(5715)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5715, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14528)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14528, 704}, +/*h(7763)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7763, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12162, 711}, +/*h(1216)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1216, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3264, 704}, +/*h(14210)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14210, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5312, 704}, +/*h(16258)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16258, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9408, 704}, +/*h(2643)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2643, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1806_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11456, 704}, +/*h(4691)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4691, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8520_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13504)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13504, 704}, +/*h(6739)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6739, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6082_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15552)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15552, 704}, +/*h(8787)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8787, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5772_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2861_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {960, 704}, +/*h(11906)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11906, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3008, 704}, +/*h(13954)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13954, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16002, 706}, +/*h(5056)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5056, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1642_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12930, 706}, +/*h(1984)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1984, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4032, 704}, +/*h(14978)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14978, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1042_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4023_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {224, 704}, +/*h(11170)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11170, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1585_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13218, 712}, +/*h(2272)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2272, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8299_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4320, 704}, +/*h(15266)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15266, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8416, 704}, +/*h(1651)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1651, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_985_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10464, 704}, +/*h(3699)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3699, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7699_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12512)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12512, 704}, +/*h(5747)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5747, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14560)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14560, 704}, +/*h(7795)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7795, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2804_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1248, 704}, +/*h(12194)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12194, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3296, 704}, +/*h(14242)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14242, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7080_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16290, 712}, +/*h(5344)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5344, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4642_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7392, 704}, +/*h(627)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {627, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2204_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9440, 704}, +/*h(2675)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2675, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8918_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11488)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11488, 704}, +/*h(4723)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4723, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13536)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13536, 704}, +/*h(6771)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6771, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4042_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15584)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15584, 704}, +/*h(8819)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8819, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_821_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {992, 704}, +/*h(11938)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11938, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13986, 706}, +/*h(3040)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3040, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5088, 704}, +/*h(16034)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16034, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11232, 704}, +/*h(15413)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15413, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2058_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15328, 704}, +/*h(11147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11147, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8754_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2016, 704}, +/*h(12962)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12962, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6316_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4064, 704}, +/*h(15010)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15010, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5716_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_839_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16352, 704}, +/*h(12171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12171, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_817_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6912_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2946_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(528)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {528, 704}, +/*h(11474)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11474, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_508_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2576)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2576, 704}, +/*h(13522)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13522, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7222_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15570)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15570, 707}, +/*h(4624)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4624, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9060_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10768, 704}, +/*h(4003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4003, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6622_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12816, 704}, +/*h(6051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6051, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14864, 704}, +/*h(8099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8099, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1727_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12498)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12498, 707}, +/*h(1552)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1552, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3600)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3600, 704}, +/*h(14546)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14546, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5648)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5648; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11792, 704}, +/*h(5027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5027, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13840, 704}, +/*h(7075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7075, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2965_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15888, 704}, +/*h(9123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9123, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6091_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(48)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 48; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_906_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(560)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {560, 704}, +/*h(11506)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11506, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7620_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13554)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13554, 707}, +/*h(2608)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2608, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4656, 704}, +/*h(15602)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15602, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8752, 704}, +/*h(1987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1987, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7020_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10800, 704}, +/*h(4035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4035, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4582_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12848, 704}, +/*h(6083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6083, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14896, 704}, +/*h(8131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8131, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8839_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1584)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1584, 704}, +/*h(12530)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12530, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6401_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3632)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3632, 704}, +/*h(14578)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14578, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1525_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7728, 704}, +/*h(963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {963, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8239_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9776, 704}, +/*h(3011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3011, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5801_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11824, 704}, +/*h(5059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5059, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3363_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13872, 704}, +/*h(7107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7107, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_925_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15920, 704}, +/*h(9155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {9155, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(80)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 80; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1013_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(592)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 592; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2640)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7418_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8784, 704}, +/*h(2019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2019, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4980_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10832, 704}, +/*h(4067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4067, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12880, 704}, +/*h(6115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {6115, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14928, 704}, +/*h(8163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {8163, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1616)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7760, 704}, +/*h(995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {995, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6199_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9808, 704}, +/*h(3043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3043, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3761_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11856, 704}, +/*h(5091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {5091, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1323_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13904, 704}, +/*h(7139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {7139, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8037_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15952, 704}, +/*h(9187)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {9187, 716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {848, 704}, +/*h(11794)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11794, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7563_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13842, 706}, +/*h(2896)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2896, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4944, 704}, +/*h(15890)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15890, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8782_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1872, 704}, +/*h(12818)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12818, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3920, 704}, +/*h(14866)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14866, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3849_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1411_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15472)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15472; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(624)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 624; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6768, 704}, +/*h(3)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8816, 704}, +/*h(2051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2051, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2940_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10864, 704}, +/*h(4099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4099, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12912, 704}, +/*h(6147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6147, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14960, 704}, +/*h(8195)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8195, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1648)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1648; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9035_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7792, 704}, +/*h(1027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1027, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4159_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9840, 704}, +/*h(3075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3075, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1721_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11888, 704}, +/*h(5123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5123, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13936, 704}, +/*h(7171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7171, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5997_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15984, 704}, +/*h(9219)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9219, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11826, 706}, +/*h(880)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {880, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5523_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2928, 704}, +/*h(13874)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13874, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3085_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4976, 704}, +/*h(15922)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15922, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6742_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1904, 704}, +/*h(12850)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12850, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4304_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14898, 706}, +/*h(3952)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3952, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {144, 704}, +/*h(11090)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11090, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2192, 704}, +/*h(13138)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13138, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15186, 709}, +/*h(4240)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4240, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14480)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7904_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12114, 709}, +/*h(1168)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1168, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3216, 704}, +/*h(14162)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14162, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3028_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5264, 704}, +/*h(16210)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16210, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15504)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 656; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6800, 704}, +/*h(35)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {35, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8848, 704}, +/*h(13029)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13029, 704}, +/*h(2083)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2083, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_900_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4131, 705}, +/*h(15077)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15077, 704}, +/*h(10896)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10896, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7613_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12944, 704}, +/*h(8763)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8763, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14992, 704}, +/*h(10811)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10811, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6995_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4557_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7824, 704}, +/*h(1059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1059, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2119_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9872, 704}, +/*h(3107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3107, 705}, +/*h(14053)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14053, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8833_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16101)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16101, 704}, +/*h(11920)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11920, 704}, +/*h(5155)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5155, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6394_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13968, 704}, +/*h(9787)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9787, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3956_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16016, 704}, +/*h(11835)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11835, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5921_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {912, 704}, +/*h(11858)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11858, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2960, 704}, +/*h(13906)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13906, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1045_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15954, 706}, +/*h(5008)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5008, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4702_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12882, 706}, +/*h(1936)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1936, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3984, 704}, +/*h(14930)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14930, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7083_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {176, 704}, +/*h(11122)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11122, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4645_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13170, 710}, +/*h(2224)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2224, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4272, 704}, +/*h(15218)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15218, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8921_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4045_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14512)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5864_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1200, 704}, +/*h(12146)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12146, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3426_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3248, 704}, +/*h(14194)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14194, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_988_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16242, 710}, +/*h(5296)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5296, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13488)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15536)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15536, 704}, +/*h(8771)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8771, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4954_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3881_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {944, 704}, +/*h(11890)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11890, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1443_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13938, 706}, +/*h(2992)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2992, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8157_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5040, 704}, +/*h(15986)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15986, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2662_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1968, 704}, +/*h(12914)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12914, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4016, 704}, +/*h(14962)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14962, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2062_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5043_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11154, 711}, +/*h(208)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {208, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2256, 704}, +/*h(13202)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13202, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4304, 704}, +/*h(15250)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15250, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4443_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8400, 704}, +/*h(1635)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1635, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2005_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10448, 704}, +/*h(3683)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3683, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12496)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12496, 704}, +/*h(5731)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5731, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14544)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14544, 704}, +/*h(7779)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7779, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3824_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1232, 704}, +/*h(12178)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12178, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14226, 711}, +/*h(3280)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3280, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5328, 704}, +/*h(16274)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16274, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5662_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7376, 704}, +/*h(611)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {611, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3224_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9424, 704}, +/*h(2659)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2659, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_786_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11472)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11472, 704}, +/*h(4707)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4707, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13520)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13520, 704}, +/*h(6755)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6755, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5062_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15568)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15568, 704}, +/*h(8803)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8803, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5971_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3792; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9028_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11922, 706}, +/*h(976)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {976, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8555_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3024, 704}, +/*h(13970)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13970, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5072, 704}, +/*h(16018)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16018, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2000, 704}, +/*h(12946)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12946, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7336_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14994, 706}, +/*h(4048)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4048, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {240, 704}, +/*h(11186)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11186, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2288, 704}, +/*h(13234)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13234, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7279_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15282, 712}, +/*h(4336)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4336, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8432, 704}, +/*h(1667)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1667, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10480)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10480, 704}, +/*h(3715)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3715, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6679_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12528)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12528, 704}, +/*h(5763)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5763, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14576)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14576, 704}, +/*h(7811)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7811, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1784_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12210, 712}, +/*h(1264)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1264, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3312, 704}, +/*h(14258)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14258, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6060_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5360, 704}, +/*h(16306)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16306, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3622_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7408, 704}, +/*h(643)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {643, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9456, 704}, +/*h(2691)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2691, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7898_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11504)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11504, 704}, +/*h(4739)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4739, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13552)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13552, 704}, +/*h(6787)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6787, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15600)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15600, 704}, +/*h(8835)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8835, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1008, 704}, +/*h(11954)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11954, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6515_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3056, 704}, +/*h(14002)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14002, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4077_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5104, 704}, +/*h(16050)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16050, 706}, +/*h(9285)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9285, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1639_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7152, 704}, +/*h(11333)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11333, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9200, 704}, +/*h(5019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {5019, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11248, 704}, +/*h(7067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {7067, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7734_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12978, 706}, +/*h(2032)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2032, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8261)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8261, 704}, +/*h(4080)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4080, 704}, +/*h(15026)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15026, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2858_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6128, 704}, +/*h(10309)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10309, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8176, 704}, +/*h(3995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3995, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10224, 704}, +/*h(6043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {6043, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8971_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4320_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 704}, +/*h(6769)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6769, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1882_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2052)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2052, 704}, +/*h(8817)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8817, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4100, 704}, +/*h(10865)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10865, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6148, 704}, +/*h(12913)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12913, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3720_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8196, 704}, +/*h(14961)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14961, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10244; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7996_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1028)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1028, 704}, +/*h(7793)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7793, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_663_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3076)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3076, 704}, +/*h(9841)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9841, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5124)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5124, 704}, +/*h(11889)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11889, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4939_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7172, 704}, +/*h(13937)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13937, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9220, 704}, +/*h(15985)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15985, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13316)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13316; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15364)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15364; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(516)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {516, 704}, +/*h(11462)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11462, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2564)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2564, 704}, +/*h(13510)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13510, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15558)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15558, 705}, +/*h(4612)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4612, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6660)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6660; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8708)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10756)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2811_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12804, 704}, +/*h(1858)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {1858, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {3906, 709}, +/*h(14852)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14852, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7068_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12486)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12486, 705}, +/*h(1540)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1540, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4630_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3588)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3588, 704}, +/*h(14534)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14534, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5636)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7684)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9732)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4030_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {834, 709}, +/*h(11780)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11780, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1592_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {2882, 709}, +/*h(13828)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13828, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15876)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15876, 704}, +/*h(4930)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {4930, 709}, +/*h(9111)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {9111, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(772)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2820; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8964)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(66)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {66, 705}, +/*h(11012)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11012, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4794_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2114, 705}, +/*h(13060)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13060, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15108)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15108, 704}, +/*h(4162)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4162, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1796)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5892; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9988)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9988; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12036)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12036, 704}, +/*h(1090)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1090, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3575_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3138, 705}, +/*h(14084)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14084, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5186, 705}, +/*h(16132)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16132, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2280_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(36)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {36, 704}, +/*h(6801)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6801, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8994_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2084)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2084, 704}, +/*h(8849)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8849, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6556_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4132)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4132, 704}, +/*h(10897)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10897, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6180, 704}, +/*h(12945)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12945, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1680_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8228, 704}, +/*h(14993)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14993, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12324)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14372)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1060)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1060, 704}, +/*h(7825)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7825, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7775_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3108)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3108, 704}, +/*h(9873)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9873, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5337_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5156)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5156, 704}, +/*h(11921)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11921, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2899_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7204, 704}, +/*h(13969)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13969, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9252, 704}, +/*h(16017)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16017, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11300; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13348)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13348; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15396)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(548)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {548, 704}, +/*h(11494)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11494, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3809_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13542)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13542, 705}, +/*h(2596)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2596, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4644)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4644, 704}, +/*h(15590)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15590, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6692)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5647_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8740)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8740, 704}, +/*h(1975)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1975, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10788)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10788, 704}, +/*h(4023)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4023, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_771_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12836, 704}, +/*h(6071)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6071, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7485_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14884, 704}, +/*h(8119)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8119, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5028_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1572)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1572, 704}, +/*h(12518)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12518, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2590_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3620)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3620, 704}, +/*h(14566)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14566, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5668)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6866_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7716)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7716, 704}, +/*h(951)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {951, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4428_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9764)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9764, 704}, +/*h(2999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2999, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1990_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11812)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11812, 704}, +/*h(5047)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5047, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8704_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13860, 704}, +/*h(7095)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7095, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15908, 704}, +/*h(9143)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9143, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2852)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2852; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6948)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6948; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8996)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(98)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {98, 705}, +/*h(11044)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11044, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2754_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13092)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13092, 704}, +/*h(2146)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2146, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_316_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4194, 705}, +/*h(15140)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15140, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1828)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3876)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5924)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8849_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7972)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6411_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10020)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3973_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1122, 705}, +/*h(12068)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12068, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3170, 705}, +/*h(14116)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14116, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16164, 704}, +/*h(5218)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5218, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(68)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {68, 704}, +/*h(6833)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6833, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2116, 704}, +/*h(8881)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8881, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4516_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4164, 704}, +/*h(10929)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10929, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2078_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6212, 704}, +/*h(12977)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12977, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8792_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8260, 704}, +/*h(15025)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15025, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12356)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14404)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14404; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1092)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1092, 704}, +/*h(7857)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7857, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5735_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3140, 704}, +/*h(9905)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9905, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5188, 704}, +/*h(11953)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11953, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_859_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7236, 704}, +/*h(14001)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14001, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7573_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9284)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9284, 704}, +/*h(16049)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16049, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11332)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13380)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13380; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15428)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(580)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2628)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2628; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4676)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6045_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6724)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6724; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3607_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8772)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8772, 704}, +/*h(2007)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {2007, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10820, 704}, +/*h(4055)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4055, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7883_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12868, 704}, +/*h(6103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6103, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5445_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14916, 704}, +/*h(8151)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8151, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1604)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3652)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5700)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5700; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4826_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7748)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7748, 704}, +/*h(983)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {983, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2388_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9796)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9796, 704}, +/*h(3031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3031, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11844, 704}, +/*h(5079)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5079, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6664_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13892, 704}, +/*h(7127)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7127, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4226_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15940, 704}, +/*h(9175)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {9175, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {836, 704}, +/*h(11782)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11782, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3752_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13830)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13830, 706}, +/*h(2884)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2884, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4932, 704}, +/*h(15878)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15878, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8028_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6980)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9028)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11076)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11076, 704}, +/*h(130)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {130, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_714_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2178, 705}, +/*h(13124)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13124, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7428_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4226, 705}, +/*h(15172)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15172, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1860, 704}, +/*h(12806)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12806, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3908, 704}, +/*h(14854)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14854, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10052)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10052; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1933_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1154, 705}, +/*h(12100)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12100, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8647_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14148, 704}, +/*h(3202)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3202, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5250, 705}, +/*h(16196)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16196, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {100, 704}, +/*h(6865)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6865, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2148, 704}, +/*h(8913)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8913, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2476_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4196, 704}, +/*h(10961)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10961, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6244, 704}, +/*h(13009)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13009, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6752_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8292, 704}, +/*h(15057)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15057, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12388)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14436)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14436; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1124)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1124, 704}, +/*h(7889)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7889, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3695_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3172, 704}, +/*h(9937)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9937, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5220, 704}, +/*h(11985)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11985, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7268, 704}, +/*h(14033)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14033, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9316)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9316, 704}, +/*h(16081)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16081, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11364)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11364; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13412)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15460)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15460; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(612)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2660)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2660; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4708)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6756)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1567_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8804, 704}, +/*h(2039)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2039, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10852)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10852, 704}, +/*h(4087)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4087, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5843_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12900, 704}, +/*h(6135)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {6135, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14948)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14948, 704}, +/*h(8183)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {8183, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1636)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3684)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5732)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2786_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7780)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7780, 704}, +/*h(1015)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {1015, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9828)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9828, 704}, +/*h(3063)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3063, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7062_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11876)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11876, 704}, +/*h(5111)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {5111, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4624_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13924)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13924, 704}, +/*h(7159)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {7159, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2186_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15972)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15972, 704}, +/*h(9207)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {9207, 716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11814)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11814, 706}, +/*h(868)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {868, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1712_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2916, 704}, +/*h(13862)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13862, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8426_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4964)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4964, 704}, +/*h(15910)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15910, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7012)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7012; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9060)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9060; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {162, 705}, +/*h(11108)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11108, 704}, +/*h(4343)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4343, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7826_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6391)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6391, 707}, +/*h(2210)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2210, 705}, +/*h(13156)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13156, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5388_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15204, 704}, +/*h(8439)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8439, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2931_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1892, 704}, +/*h(12838)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12838, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14886, 706}, +/*h(3940)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3940, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5988)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5988; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8036)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10084)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10084; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9045_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12132)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12132, 704}, +/*h(5367)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5367, 707}, +/*h(1186)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1186, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6607_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7415)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7415, 707}, +/*h(3234)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3234, 705}, +/*h(14180)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14180, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16228, 704}, +/*h(9463)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9463, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6897, 704}, +/*h(132)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {132, 704}, +/*h(11078)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11078, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2180, 704}, +/*h(13126)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13126, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_436_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15174)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15174, 709}, +/*h(4228)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4228, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8324)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10372)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12420)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12420; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14468)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14468; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12102, 709}, +/*h(1156)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1156, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1655_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3204, 704}, +/*h(14150)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14150, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8369_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5252, 704}, +/*h(16198)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16198, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7300; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9348)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9348; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1055_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11396)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13444)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13444; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15492)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15492; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(644)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2692)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4740)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4740; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1965_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6788)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6788, 704}, +/*h(23)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {23, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8679_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8836, 704}, +/*h(2071)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2071, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10884, 704}, +/*h(4119)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4119, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3803_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12932, 704}, +/*h(6167)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6167, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1365_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14980)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14980, 704}, +/*h(8215)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8215, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1668)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3716)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3716; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5764)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5764; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_746_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7812)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7812, 704}, +/*h(1047)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1047, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9860, 704}, +/*h(3095)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3095, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11908, 704}, +/*h(5143)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5143, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2584_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13956, 704}, +/*h(7191)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7191, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16004, 704}, +/*h(9239)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9239, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {900, 704}, +/*h(11846)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11846, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8824_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2948)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2948, 704}, +/*h(13894)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13894, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15942)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15942, 706}, +/*h(4996)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4996, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7044)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7044; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9092)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9092; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_891_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12870, 706}, +/*h(1924)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1924, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3972)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3972, 704}, +/*h(14918)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14918, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6020)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8068)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8068; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10116; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12164; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14212; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {164, 704}, +/*h(11110)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11110, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_834_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13158)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13158, 710}, +/*h(2212)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2212, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7548_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4260, 704}, +/*h(15206)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15206, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8356)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10404)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10404; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12452)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14500)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14500; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2053_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1188, 704}, +/*h(12134)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12134, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8767_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3236, 704}, +/*h(14182)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14182, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6329_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16230, 710}, +/*h(5284)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5284, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7332)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9380)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9380; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11428)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13476)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13476; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15524)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15524; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7239_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(676)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {676, 704}, +/*h(4857)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4857, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4801_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2724)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2724, 704}, +/*h(6905)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6905, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4772)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6820; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2018, 714}, +/*h(12964)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12964, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8476_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15012)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15012, 704}, +/*h(4066)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4066, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6020_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1700)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1700, 704}, +/*h(5881)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5881, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3748)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3748; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5796)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9892; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2981_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11940, 704}, +/*h(994)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {994, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_543_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3042, 715}, +/*h(13988)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13988, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {5090, 720}, +/*h(16036)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16036, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {932, 704}, +/*h(11878)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11878, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6784_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13926)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13926, 706}, +/*h(2980)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2980, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4346_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5028)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5028, 704}, +/*h(15974)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15974, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7076)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7076; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9124)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9124; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11172; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1956, 704}, +/*h(12902)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12902, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5565_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4004, 704}, +/*h(14950)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14950, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6052)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6052; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8100; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12196; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14244; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11142)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11142, 711}, +/*h(196)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {196, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7946_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2244, 704}, +/*h(13190)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13190, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5508_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4292, 704}, +/*h(15238)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15238, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8388)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8388, 704}, +/*h(1623)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1623, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7346_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10436)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10436, 704}, +/*h(3671)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3671, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4908_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12484)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12484, 704}, +/*h(5719)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5719, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2470_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14532)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14532, 704}, +/*h(7767)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7767, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1220, 704}, +/*h(12166)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12166, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6727_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14214, 711}, +/*h(3268)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3268, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4289_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5316)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5316, 704}, +/*h(16262)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16262, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1851_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7364)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7364, 704}, +/*h(599)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {599, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8565_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9412)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9412, 704}, +/*h(2647)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2647, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11460)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11460, 704}, +/*h(4695)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4695, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13508)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13508, 704}, +/*h(6743)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6743, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1251_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15556)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15556, 704}, +/*h(8791)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8791, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(708)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2756)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6852)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6852; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2160_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2, 705}, +/*h(10948)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10948, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12996)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12996, 704}, +/*h(2050)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2050, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6436_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4098, 705}, +/*h(15044)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15044, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1732)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3780)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5828)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5817_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7876)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9924)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_941_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1026, 705}, +/*h(11972)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11972, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7655_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3074, 705}, +/*h(14020)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14020, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16068)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16068, 704}, +/*h(5122)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5122, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11910)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11910, 706}, +/*h(964)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {964, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4744_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3012)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3012, 704}, +/*h(13958)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13958, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5060)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5060, 704}, +/*h(16006)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16006, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7108)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7108; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9156)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11204; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15300; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1988)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1988, 704}, +/*h(12934)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12934, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3525_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14982)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14982, 706}, +/*h(4036)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4036, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6084)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6084; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8132)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10180; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16324)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {228, 704}, +/*h(11174)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11174, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5906_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2276, 704}, +/*h(13222)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13222, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3468_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15270, 712}, +/*h(4324)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4324, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6372)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7744_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8420)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8420, 704}, +/*h(1655)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1655, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10468)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10468, 704}, +/*h(3703)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3703, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2868_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12516)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12516, 704}, +/*h(5751)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5751, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14564)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14564, 704}, +/*h(7799)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7799, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12198)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12198, 712}, +/*h(1252)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1252, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4687_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3300, 704}, +/*h(14246)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14246, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5348)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5348, 704}, +/*h(16294)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16294, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7396)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7396, 704}, +/*h(631)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {631, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6525_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9444)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9444, 704}, +/*h(2679)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2679, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4087_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11492)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11492, 704}, +/*h(4727)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4727, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1649_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13540)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13540, 704}, +/*h(6775)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6775, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8363_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15588)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15588, 704}, +/*h(8823)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8823, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(740)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 740; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2788)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2788; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4836; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4996_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10980)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10980, 704}, +/*h(34)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {34, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6834_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2082, 705}, +/*h(13028)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13028, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4130, 705}, +/*h(15076)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15076, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1764)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1764; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3812)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5860; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8053_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1058, 705}, +/*h(12004)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12004, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5615_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14052)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14052, 704}, +/*h(3106)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3106, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5154, 705}, +/*h(16100)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16100, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5142_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(996)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {996, 704}, +/*h(11942)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11942, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2704_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3044)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3044, 704}, +/*h(13990)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13990, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16038)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16038, 706}, +/*h(5092)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5092, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9188, 704}, +/*h(13369)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13369, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11236, 704}, +/*h(15417)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15417, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8817_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13284)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15332)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3923_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12966, 706}, +/*h(2020)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2020, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1485_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4068)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4068, 704}, +/*h(15014)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15014, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6116; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8164; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3323_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10212, 704}, +/*h(14393)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14393, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16356)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 704}, +/*h(6785)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6785, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2068)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2068, 704}, +/*h(8833)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8833, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4116, 704}, +/*h(10881)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10881, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6164, 704}, +/*h(12929)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12929, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2700_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8212, 704}, +/*h(14977)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14977, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14356)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2081_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1044)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1044, 704}, +/*h(7809)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7809, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8795_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3092)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3092, 704}, +/*h(9857)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9857, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5140, 704}, +/*h(11905)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11905, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3919_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7188, 704}, +/*h(13953)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13953, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1481_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9236, 704}, +/*h(16001)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16001, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11284)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13332)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15380)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15380; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7267_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11478)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11478, 707}, +/*h(532)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {532, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4829_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2580)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2580, 704}, +/*h(13526)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13526, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4628)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4628, 704}, +/*h(15574)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15574, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6676)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6667_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8724)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8724, 704}, +/*h(1959)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1959, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10772)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10772, 704}, +/*h(4007)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4007, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1791_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12820, 704}, +/*h(6055)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6055, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14868, 704}, +/*h(8103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8103, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6048_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1556)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1556, 704}, +/*h(12502)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12502, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14550)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14550, 707}, +/*h(3604)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3604, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5652)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7886_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7700)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7700; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5448_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9748)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9748, 704}, +/*h(2983)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2983, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3010_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11796)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11796, 704}, +/*h(5031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5031, 712}, +/*h(850)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {850, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13844, 704}, +/*h(7079)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7079, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15892, 704}, +/*h(9127)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9127, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(788)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 788; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2836; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8980)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11028)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11028, 704}, +/*h(82)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {82, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3774_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2130, 707}, +/*h(13076)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13076, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1336_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4178, 707}, +/*h(15124)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15124, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1812)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3860; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4993_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1106, 707}, +/*h(12052)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12052, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2555_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14100, 704}, +/*h(3154)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3154, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5202, 707}, +/*h(16148)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16148, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1260_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(52)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {52, 704}, +/*h(6817)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6817, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2100, 704}, +/*h(8865)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8865, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5536_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4148, 704}, +/*h(10913)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10913, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3098_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6196, 704}, +/*h(12961)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12961, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8244, 704}, +/*h(15009)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15009, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14388)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1076)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1076, 704}, +/*h(7841)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7841, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3124)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3124, 704}, +/*h(9889)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9889, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5172, 704}, +/*h(11937)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11937, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1879_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7220, 704}, +/*h(13985)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13985, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9268, 704}, +/*h(16033)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16033, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11316)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11316; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13364)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13364; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15412)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(564)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {564, 704}, +/*h(11510)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11510, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2789_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2612)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2612, 704}, +/*h(13558)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13558, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15606)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15606, 707}, +/*h(4660)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4660, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6708)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8756)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8756, 704}, +/*h(1991)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1991, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2189_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10804, 704}, +/*h(4039)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4039, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8903_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12852)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12852, 704}, +/*h(6087)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6087, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6465_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14900, 704}, +/*h(8135)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8135, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4008_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12534)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12534, 707}, +/*h(1588)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1588, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1570_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3636)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3636, 704}, +/*h(14582)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14582, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5684)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5846_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7732)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7732, 704}, +/*h(967)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {967, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9780)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9780, 704}, +/*h(3015)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3015, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_970_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11828)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11828, 704}, +/*h(5063)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5063, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7684_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13876)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13876, 704}, +/*h(7111)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7111, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15924)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15924, 704}, +/*h(9159)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {9159, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 820; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4772_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9048_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6964)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9012)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9012; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {114, 707}, +/*h(11060)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11060, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1734_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2162, 707}, +/*h(13108)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13108, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8448_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15156)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15156, 704}, +/*h(4210)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4210, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3892; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7988)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7988; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10036)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12084)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12084, 704}, +/*h(1138)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1138, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3186, 707}, +/*h(14132)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14132, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5234, 707}, +/*h(16180)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16180, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8372_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(84)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {84, 704}, +/*h(6849)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6849, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2132)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2132, 704}, +/*h(8897)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8897, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3496_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4180, 704}, +/*h(10945)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10945, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1058_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6228, 704}, +/*h(12993)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12993, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7772_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8276, 704}, +/*h(15041)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15041, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10324)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12372)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14420)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14420; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1108)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1108, 704}, +/*h(7873)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7873, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4715_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3156)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3156, 704}, +/*h(9921)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9921, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2277_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5204, 704}, +/*h(11969)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11969, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8991_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7252, 704}, +/*h(14017)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14017, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9300, 704}, +/*h(16065)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16065, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11348)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11348; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13396)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15444)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15444; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(596)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2644)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4692)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6740)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6740; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8788)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8788, 704}, +/*h(2023)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2023, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10836, 704}, +/*h(4071)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4071, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6863_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12884, 704}, +/*h(6119)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {6119, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4425_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14932, 704}, +/*h(8167)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {8167, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1620)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3668)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5716)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5716; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3806_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7764)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7764, 704}, +/*h(999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {999, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1368_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9812)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9812, 704}, +/*h(3047)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3047, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8082_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11860, 704}, +/*h(5095)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {5095, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5644_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13908, 704}, +/*h(7143)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {7143, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3206_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15956, 704}, +/*h(9191)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {9191, 716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(852)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {852, 704}, +/*h(11798)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11798, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2732_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2900, 704}, +/*h(13846)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13846, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15894)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15894, 706}, +/*h(4948)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4948, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6996)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4570_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9044)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9044; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {146, 707}, +/*h(11092)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11092, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8846_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13140, 704}, +/*h(2194)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2194, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4242, 707}, +/*h(15188)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15188, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3951_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12822, 706}, +/*h(1876)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1876, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1513_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3924)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3924, 704}, +/*h(14870)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14870, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5972)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8020)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10068)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10068; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_913_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1170, 707}, +/*h(12116)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12116, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3218, 707}, +/*h(14164)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14164, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5189_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16212, 704}, +/*h(5266)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5266, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {116, 704}, +/*h(6881)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6881, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3894_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2164, 704}, +/*h(8929)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8929, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10977, 704}, +/*h(4212)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4212, 704}, +/*h(15158)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {15158, 722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6260, 704}, +/*h(13025)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13025, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10356)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12404)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12404; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7570_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14452)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1140, 704}, +/*h(7905)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7905, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3188, 704}, +/*h(9953)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9953, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5236, 704}, +/*h(12001)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12001, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6951_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7284)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7284, 704}, +/*h(14049)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14049, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9332)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2075_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11380)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11380; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13428)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15476)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15476; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(628)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 628; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2676)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4724)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4724; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2985_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6772)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6772, 704}, +/*h(7)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_547_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8820, 704}, +/*h(2055)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2055, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10868, 704}, +/*h(4103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4103, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4823_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12916, 704}, +/*h(6151)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6151, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2385_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14964)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14964, 704}, +/*h(8199)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8199, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1652)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3700)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3700; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5748)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5748; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1766_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7796)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7796, 704}, +/*h(1031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1031, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9844, 704}, +/*h(3079)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3079, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6042_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11892, 704}, +/*h(5127)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5127, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3604_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13940, 704}, +/*h(7175)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7175, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15988)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15988, 704}, +/*h(9223)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9223, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {884, 704}, +/*h(11830)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11830, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13878)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13878, 706}, +/*h(2932)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2932, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4980)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4980, 704}, +/*h(15926)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15926, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7028)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9076)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9076; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11124)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11124; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13172; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1911_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1908, 704}, +/*h(12854)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12854, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8625_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3956)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3956, 704}, +/*h(14902)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14902, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8052)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8052; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10100; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14196; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16244; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4292_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11094, 709}, +/*h(148)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {148, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2196, 704}, +/*h(13142)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13142, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8568_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4244, 704}, +/*h(15190)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15190, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10388)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12436)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12436; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14484)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14484; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3073_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1172, 704}, +/*h(12118)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12118, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14166)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14166, 709}, +/*h(3220)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3220, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7349_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5268, 704}, +/*h(16214)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16214, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7316)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7316; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9364)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9364; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11412)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13460)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13460; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15508)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15508; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(660)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 660; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2708)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4756)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_945_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6804, 704}, +/*h(10985)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10985, 704}, +/*h(39)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {39, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7659_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2087)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2087, 705}, +/*h(13033)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13033, 704}, +/*h(8852)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8852, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2782_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12948)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12948, 704}, +/*h(2002)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {2002, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4050, 713}, +/*h(14996)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14996, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1684)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3732)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5780)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8878_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7828)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7828, 704}, +/*h(1063)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1063, 705}, +/*h(12009)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12009, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14057, 704}, +/*h(9876)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9876, 704}, +/*h(3111)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3111, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4001_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {978, 713}, +/*h(11924)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11924, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1563_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3026, 713}, +/*h(13972)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13972, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8277_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16020)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16020, 704}, +/*h(5074)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5074, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1090_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11862)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11862, 706}, +/*h(916)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {916, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7804_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2964)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2964, 704}, +/*h(13910)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13910, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5366_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5012)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5012, 704}, +/*h(15958)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15958, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7060)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7060; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9108)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9108; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11156)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13204; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9023_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1940, 704}, +/*h(12886)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12886, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6585_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14934)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14934, 706}, +/*h(3988)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3988, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6036)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8084)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8084; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10132)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12180; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {180, 704}, +/*h(11126)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11126, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2228, 704}, +/*h(13174)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13174, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6528_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15222, 710}, +/*h(4276)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4276, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6324)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8372)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10420)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10420; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12468)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12468; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14516)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14516, 704}, +/*h(7751)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7751, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1033_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12150, 710}, +/*h(1204)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1204, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7747_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3252, 704}, +/*h(14198)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14198, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5309_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5300, 704}, +/*h(16246)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16246, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7348)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7348; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9396)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11444)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11444; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4709_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13492)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13492, 704}, +/*h(6727)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6727, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15540)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15540, 704}, +/*h(8775)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8775, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(692)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2740)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2740; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4788)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4788; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6836)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6836; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8884)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10932)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_742_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2034, 714}, +/*h(12980)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12980, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4082, 715}, +/*h(15028)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15028, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1716)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1716; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3764)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3764; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5812)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7860)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7860; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9908)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {1010, 714}, +/*h(11956)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11956, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14004, 704}, +/*h(3058)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3058, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {5106, 720}, +/*h(16052)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16052, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(948)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {948, 704}, +/*h(11894)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11894, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5764_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2996)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2996, 704}, +/*h(13942)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13942, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15990)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15990, 706}, +/*h(5044)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5044, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7092)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7092; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9140)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11188)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15284)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6983_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12918, 706}, +/*h(1972)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1972, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4545_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4020)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4020, 704}, +/*h(14966)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14966, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6068)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6068; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8116; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10164)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10164; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12212; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14260)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(212)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {212, 704}, +/*h(11158)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11158, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6926_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13206)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13206, 711}, +/*h(2260)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2260, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4488_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4308)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4308, 704}, +/*h(15254)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15254, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6356)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8764_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8404)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8404, 704}, +/*h(1639)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1639, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10452)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10452, 704}, +/*h(3687)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3687, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3888_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12500)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12500, 704}, +/*h(5735)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5735, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1450_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14548)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14548, 704}, +/*h(7783)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7783, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1236)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1236, 704}, +/*h(12182)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12182, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5707_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3284)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3284, 704}, +/*h(14230)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14230, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3269_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16278, 711}, +/*h(5332)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5332, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_831_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7380)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7380, 704}, +/*h(615)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {615, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7545_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9428)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9428, 704}, +/*h(2663)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2663, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11476)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11476, 704}, +/*h(4711)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4711, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13524)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13524, 704}, +/*h(6759)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6759, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15572)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15572, 704}, +/*h(8807)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8807, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(724)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 724; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2772)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4820)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4820; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6868)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8916)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(18)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {18, 707}, +/*h(10964)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10964, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2066, 707}, +/*h(13012)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13012, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5416_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15060)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15060, 704}, +/*h(4114)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4114, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1748)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1748; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3796)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5844)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7892)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7892; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9940)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9073_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11988)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11988, 704}, +/*h(1042)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1042, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6635_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3090, 707}, +/*h(14036)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14036, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5138, 707}, +/*h(16084)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16084, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6162_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(980)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {980, 704}, +/*h(11926)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11926, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3724_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13974)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13974, 706}, +/*h(3028)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3028, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5076)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5076, 704}, +/*h(16022)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16022, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7124)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7124; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9172)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9172; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11220)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15316)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15316; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4943_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2004)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2004, 704}, +/*h(12950)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12950, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4052)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4052, 704}, +/*h(14998)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14998, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6100)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6100; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8148)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10196)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10196; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12244)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12244; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7324_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11190)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11190, 712}, +/*h(244)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {244, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2292)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2292, 704}, +/*h(13238)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13238, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2448_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4340)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4340, 704}, +/*h(15286)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15286, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6388)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6724_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8436)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8436, 704}, +/*h(1671)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1671, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10484)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10484, 704}, +/*h(3719)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3719, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1848_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12532)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12532, 704}, +/*h(5767)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5767, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14580)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14580, 704}, +/*h(7815)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7815, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1268)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1268, 704}, +/*h(12214)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12214, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3667_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14262)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14262, 712}, +/*h(3316)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3316, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5364)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5364, 704}, +/*h(16310)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16310, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7943_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7412)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7412, 704}, +/*h(647)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {647, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9460)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9460, 704}, +/*h(2695)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2695, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3067_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11508)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11508, 704}, +/*h(4743)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4743, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13556)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13556, 704}, +/*h(6791)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6791, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15604)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15604, 704}, +/*h(8839)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8839, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(756)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2804)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4852)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4852; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6900)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8948)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8948; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(50)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {50, 707}, +/*h(10996)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10996, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5814_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13044)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13044, 704}, +/*h(2098)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2098, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3376_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4146, 707}, +/*h(15092)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15092, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1780)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3828)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5876)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7924)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9972)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7033_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1074, 707}, +/*h(12020)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12020, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4595_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3122, 707}, +/*h(14068)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14068, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2157_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16116)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16116, 704}, +/*h(5170)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5170, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11958)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11958, 706}, +/*h(1012)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1012, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1684_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3060)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3060, 704}, +/*h(14006)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14006, 706}, +/*h(7241)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7241, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9289, 704}, +/*h(5108)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5108, 704}, +/*h(16054)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16054, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5959_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7156)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7156, 704}, +/*h(13921)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13921, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9204)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9204, 704}, +/*h(15969)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15969, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11252)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13300)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13300; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15348)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15348; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2903_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6217, 704}, +/*h(2036)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2036, 704}, +/*h(12982)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12982, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_465_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15030, 706}, +/*h(8265)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8265, 704}, +/*h(4084)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4084, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6132)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6132, 704}, +/*h(12897)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12897, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4740_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8180)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8180, 704}, +/*h(14945)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14945, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10228)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12276)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14324)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16372)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8641_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 704}, +/*h(6773)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6773, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2056, 704}, +/*h(8821)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8821, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3765_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4104, 704}, +/*h(10869)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10869, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6152, 704}, +/*h(12917)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12917, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8041_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8200, 704}, +/*h(14965)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14965, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1032, 704}, +/*h(7797)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7797, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4984_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3080, 704}, +/*h(9845)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9845, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2546_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5128, 704}, +/*h(11893)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11893, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7176, 704}, +/*h(13941)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13941, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6822_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9224, 704}, +/*h(15989)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15989, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11466, 705}, +/*h(520)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {520, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1018_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2568)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2568, 704}, +/*h(13514)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13514, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7732_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4616)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4616, 704}, +/*h(15562)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15562, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1862)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {1862, 709}, +/*h(12808)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12808, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(14856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14856, 704}, +/*h(8091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {8091, 711}, +/*h(3910)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {3910, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1544)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1544, 704}, +/*h(12490)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12490, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8951_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14538)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14538, 705}, +/*h(3592)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3592, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5640)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4075_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8351_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11784, 704}, +/*h(838)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {838, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5913_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {2886, 709}, +/*h(13832)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13832, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {9115, 711}, +/*h(4934)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {4934, 709}, +/*h(15880)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15880, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2401_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11016, 704}, +/*h(70)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {70, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2118)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2118, 705}, +/*h(13064)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13064, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6677_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4166)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4166, 705}, +/*h(15112)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15112, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6058_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1094, 705}, +/*h(12040)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12040, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7896_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14088, 704}, +/*h(3142)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3142, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5458_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5190)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5190, 705}, +/*h(16136)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16136, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6601_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(40)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {40, 704}, +/*h(6805)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6805, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2088, 704}, +/*h(8853)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8853, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4136, 704}, +/*h(10901)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10901, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6184, 704}, +/*h(12949)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12949, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6001_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8232, 704}, +/*h(14997)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14997, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5382_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1064, 704}, +/*h(7829)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7829, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3112, 704}, +/*h(9877)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9877, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5160, 704}, +/*h(11925)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11925, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7208, 704}, +/*h(13973)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13973, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4782_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9256, 704}, +/*h(16021)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16021, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9058_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1416_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(552)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {552, 704}, +/*h(11498)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11498, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2600)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2600, 704}, +/*h(13546)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13546, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5692_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15594)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15594, 705}, +/*h(4648)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4648, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8744, 704}, +/*h(1979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1979, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7530_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10792, 704}, +/*h(4027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4027, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5092_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12840, 704}, +/*h(6075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6075, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14888, 704}, +/*h(8123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8123, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12522)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12522, 705}, +/*h(1576)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1576, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6911_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3624)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3624, 704}, +/*h(14570)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14570, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7720, 704}, +/*h(955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {955, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8749_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9768, 704}, +/*h(3003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {3003, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11816, 704}, +/*h(5051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5051, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3873_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13864, 704}, +/*h(7099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7099, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15912, 704}, +/*h(9147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9147, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_961_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {102, 705}, +/*h(11048)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11048, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7075_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2150, 705}, +/*h(13096)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13096, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15144, 704}, +/*h(4198)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4198, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12072, 704}, +/*h(1126)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1126, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5856_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3174)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3174, 705}, +/*h(14120)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14120, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3418_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5222, 705}, +/*h(16168)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16168, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(72)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {72, 704}, +/*h(6837)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6837, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2120, 704}, +/*h(8885)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8885, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8837_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4168, 704}, +/*h(10933)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10933, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6399_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6216, 704}, +/*h(12981)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12981, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8264, 704}, +/*h(15029)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15029, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3342_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1096, 704}, +/*h(7861)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7861, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_904_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3144, 704}, +/*h(9909)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9909, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7618_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5192, 704}, +/*h(11957)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11957, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5180_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7240, 704}, +/*h(14005)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14005, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2742_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9288, 704}, +/*h(16053)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16053, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(584)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2632)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7928_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8776, 704}, +/*h(2011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {2011, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10824, 704}, +/*h(4059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4059, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3052_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12872, 704}, +/*h(6107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6107, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14920, 704}, +/*h(8155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8155, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1608)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3656; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7752, 704}, +/*h(987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {987, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6709_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9800, 704}, +/*h(3035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3035, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11848, 704}, +/*h(5083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5083, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1833_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13896, 704}, +/*h(7131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7131, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8547_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15944, 704}, +/*h(9179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {9179, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1359_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {840, 704}, +/*h(11786)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11786, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8073_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2888, 704}, +/*h(13834)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13834, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5635_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15882, 706}, +/*h(4936)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4936, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7473_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(134)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {134, 705}, +/*h(11080)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11080, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13128, 704}, +/*h(2182)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2182, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4230, 705}, +/*h(15176)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15176, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12810, 706}, +/*h(1864)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1864, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3912, 704}, +/*h(14858)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14858, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6254_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1158)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1158, 705}, +/*h(12104)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12104, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3206)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3206, 705}, +/*h(14152)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14152, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16200, 704}, +/*h(5254)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5254, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {104, 704}, +/*h(6869)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6869, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2152, 704}, +/*h(8917)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8917, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6797_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4200, 704}, +/*h(10965)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10965, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4359_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6248, 704}, +/*h(13013)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13013, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1921_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8296, 704}, +/*h(15061)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15061, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1302_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1128, 704}, +/*h(7893)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7893, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8016_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3176, 704}, +/*h(9941)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9941, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5578_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5224, 704}, +/*h(11989)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11989, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7272, 704}, +/*h(14037)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14037, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_702_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9320, 704}, +/*h(16085)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16085, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(616)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5888_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8808, 704}, +/*h(2043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2043, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3450_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10856, 704}, +/*h(4091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4091, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1012_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12904, 704}, +/*h(6139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {6139, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7726_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14952, 704}, +/*h(8187)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {8187, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1640)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7784, 704}, +/*h(1019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {1019, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9832, 704}, +/*h(3067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3067, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2231_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11880, 704}, +/*h(5115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {5115, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8945_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13928, 704}, +/*h(7163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {7163, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6507_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15976, 704}, +/*h(9211)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {9211, 716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {872, 704}, +/*h(11818)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11818, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6033_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13866, 706}, +/*h(2920)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2920, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3595_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4968, 704}, +/*h(15914)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15914, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4347, 707}, +/*h(166)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {166, 705}, +/*h(11112)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11112, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2995_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13160, 704}, +/*h(6395)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6395, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15208, 704}, +/*h(8443)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8443, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1896, 704}, +/*h(12842)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12842, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4814_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3944, 704}, +/*h(14890)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14890, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6652_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10088, 704}, +/*h(3323)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3323, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4214_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1190)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1190, 705}, +/*h(12136)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12136, 704}, +/*h(5371)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5371, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((9*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14184, 704}, +/*h(7419)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7419, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16232, 704}, +/*h(9467)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9467, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11082, 709}, +/*h(136)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {136, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2184, 704}, +/*h(13130)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13130, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4757_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4232, 704}, +/*h(15178)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15178, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14472)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14472; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8414_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1160, 704}, +/*h(12106)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12106, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5976_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14154, 709}, +/*h(3208)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3208, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3538_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5256, 704}, +/*h(16202)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16202, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15496)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(648)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 648; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6792, 704}, +/*h(27)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {27, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3848_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8840, 704}, +/*h(2075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2075, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10888, 704}, +/*h(4123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4123, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12936, 704}, +/*h(6171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6171, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14984, 704}, +/*h(8219)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8219, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5067_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7816, 704}, +/*h(1051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1051, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9864, 704}, +/*h(3099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3099, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11912, 704}, +/*h(5147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5147, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6905_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13960, 704}, +/*h(7195)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7195, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16008, 704}, +/*h(9243)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9243, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6431_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11850, 706}, +/*h(904)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {904, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3993_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2952, 704}, +/*h(13898)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13898, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1555_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5000, 704}, +/*h(15946)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15946, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1928, 704}, +/*h(12874)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12874, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2774_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14922, 706}, +/*h(3976)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3976, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {168, 704}, +/*h(11114)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11114, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2216, 704}, +/*h(13162)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13162, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15210, 710}, +/*h(4264)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4264, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14504)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12138, 710}, +/*h(1192)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1192, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3936_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3240, 704}, +/*h(14186)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14186, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5288, 704}, +/*h(16234)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16234, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13480)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15528)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15528; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6683_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4776, 704}, +/*h(595)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {595, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6083_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2022)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2022, 714}, +/*h(12968)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12968, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3645_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4070, 715}, +/*h(15016)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15016, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7302_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {998, 714}, +/*h(11944)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11944, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4864_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13992, 704}, +/*h(3046)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3046, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2426_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {5094, 720}, +/*h(16040)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16040, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {936, 704}, +/*h(11882)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11882, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2984, 704}, +/*h(13930)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13930, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8667_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15978, 706}, +/*h(5032)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5032, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12906, 706}, +/*h(1960)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1960, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_734_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4008, 704}, +/*h(14954)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14954, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {200, 704}, +/*h(11146)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11146, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13194, 711}, +/*h(2248)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2248, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_677_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4296, 704}, +/*h(15242)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15242, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8392, 704}, +/*h(1627)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1627, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2515_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10440, 704}, +/*h(3675)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3675, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12488)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12488, 704}, +/*h(5723)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5723, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6791_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14536)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14536, 704}, +/*h(7771)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7771, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4334_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1224, 704}, +/*h(12170)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12170, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1896_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3272, 704}, +/*h(14218)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14218, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16266, 711}, +/*h(5320)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5320, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7368, 704}, +/*h(603)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {603, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3734_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9416, 704}, +/*h(2651)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2651, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11464, 704}, +/*h(4699)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4699, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8010_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13512)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13512, 704}, +/*h(6747)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6747, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15560)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15560, 704}, +/*h(8795)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8795, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6481_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6, 705}, +/*h(10952)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10952, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4043_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2054)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2054, 705}, +/*h(13000)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13000, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15048, 704}, +/*h(4102)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4102, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5262_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11976, 704}, +/*h(1030)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1030, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2824_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3078)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3078, 705}, +/*h(14024)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14024, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5126)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5126, 705}, +/*h(16072)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16072, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2351_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {968, 704}, +/*h(11914)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11914, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9065_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13962, 706}, +/*h(3016)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3016, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5064, 704}, +/*h(16010)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16010, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1992, 704}, +/*h(12938)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12938, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7846_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4040, 704}, +/*h(14986)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14986, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3513_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11178, 712}, +/*h(232)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {232, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1075_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2280, 704}, +/*h(13226)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13226, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7789_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4328, 704}, +/*h(15274)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15274, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2913_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8424, 704}, +/*h(1659)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1659, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10472)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10472, 704}, +/*h(3707)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3707, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7189_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12520)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12520, 704}, +/*h(5755)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5755, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4751_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14568)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14568, 704}, +/*h(7803)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7803, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1256, 704}, +/*h(12202)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12202, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9008_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14250, 712}, +/*h(3304)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3304, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6570_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5352, 704}, +/*h(16298)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16298, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7400, 704}, +/*h(635)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {635, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9448, 704}, +/*h(2683)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2683, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11496)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11496, 704}, +/*h(4731)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4731, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5970_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13544)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13544, 704}, +/*h(6779)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6779, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3532_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15592)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15592, 704}, +/*h(8827)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8827, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2792; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(38)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {38, 705}, +/*h(10984)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10984, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13032, 704}, +/*h(2086)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2086, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4134)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4134, 705}, +/*h(15080)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15080, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3222_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1062, 705}, +/*h(12008)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12008, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_784_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3110)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3110, 705}, +/*h(14056)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14056, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16104, 704}, +/*h(5158)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5158, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11946, 706}, +/*h(1000)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1000, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7025_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3048, 704}, +/*h(13994)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13994, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5096, 704}, +/*h(16042)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16042, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6424_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11240, 704}, +/*h(7059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {7059, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3986_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13288, 704}, +/*h(9107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {9107, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2024, 704}, +/*h(12970)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12970, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5806_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15018, 706}, +/*h(4072)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4072, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12264, 704}, +/*h(8083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {8083, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2767_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14312, 704}, +/*h(10131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {10131, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7621_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {24, 704}, +/*h(6789)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6789, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2072, 704}, +/*h(8837)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8837, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2745_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4120, 704}, +/*h(10885)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10885, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6168, 704}, +/*h(12933)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12933, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7021_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8216, 704}, +/*h(14981)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14981, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6402_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1048, 704}, +/*h(7813)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7813, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3964_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3096, 704}, +/*h(9861)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9861, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1526_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5144, 704}, +/*h(11909)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11909, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7192, 704}, +/*h(13957)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13957, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5802_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9240, 704}, +/*h(16005)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16005, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2436_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(536)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {536, 704}, +/*h(11482)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11482, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13530)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13530, 707}, +/*h(2584)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2584, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6712_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4632)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4632, 704}, +/*h(15578)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15578, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8728, 704}, +/*h(1963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1963, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8550_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10776, 704}, +/*h(4011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4011, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12824, 704}, +/*h(6059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6059, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3674_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14872, 704}, +/*h(8107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8107, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1560)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1560, 704}, +/*h(12506)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12506, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7931_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3608)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3608, 704}, +/*h(14554)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14554, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5656; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3055_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7704, 704}, +/*h(939)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {939, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9752, 704}, +/*h(2987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2987, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11800, 704}, +/*h(5035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5035, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13848, 704}, +/*h(7083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7083, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15896, 704}, +/*h(9131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9131, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 792; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1381_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(86)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {86, 707}, +/*h(11032)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11032, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8095_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13080, 704}, +/*h(2134)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2134, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5657_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4182)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4182, 707}, +/*h(15128)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15128, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_162_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1110)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1110, 707}, +/*h(12056)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12056, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6876_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3158)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3158, 707}, +/*h(14104)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14104, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16152, 704}, +/*h(5206)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5206, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5581_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(56)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 704}, +/*h(6821)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6821, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2104, 704}, +/*h(8869)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8869, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4152, 704}, +/*h(10917)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10917, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7419_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6200, 704}, +/*h(12965)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12965, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4981_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8248, 704}, +/*h(15013)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15013, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4362_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1080, 704}, +/*h(7845)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7845, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1924_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3128, 704}, +/*h(9893)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9893, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8638_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5176, 704}, +/*h(11941)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11941, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7224, 704}, +/*h(13989)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13989, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9272, 704}, +/*h(16037)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16037, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11514)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11514, 707}, +/*h(568)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {568, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2616)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2616, 704}, +/*h(13562)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13562, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4672_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4664, 704}, +/*h(15610)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15610, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8948_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8760, 704}, +/*h(1995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1995, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10808, 704}, +/*h(4043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4043, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4072_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12856, 704}, +/*h(6091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6091, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1634_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14904, 704}, +/*h(8139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8139, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8329_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1592)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1592, 704}, +/*h(12538)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12538, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5891_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14586)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14586, 707}, +/*h(3640)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3640, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1015_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7736, 704}, +/*h(971)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {971, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7729_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9784, 704}, +/*h(3019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3019, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5291_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11832, 704}, +/*h(5067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5067, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2853_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13880, 704}, +/*h(7115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7115, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15928, 704}, +/*h(9163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {9163, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8493_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11064, 704}, +/*h(118)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {118, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6055_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2166)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2166, 707}, +/*h(13112)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13112, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4214, 707}, +/*h(15160)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15160, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7274_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1142)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1142, 707}, +/*h(12088)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12088, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14136, 704}, +/*h(3190)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3190, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5238)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5238, 707}, +/*h(16184)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16184, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3541_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(88)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {88, 704}, +/*h(6853)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6853, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2136, 704}, +/*h(8901)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8901, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7817_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4184, 704}, +/*h(10949)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10949, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5379_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6232, 704}, +/*h(12997)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12997, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2941_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8280, 704}, +/*h(15045)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15045, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1112, 704}, +/*h(7877)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7877, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9036_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3160, 704}, +/*h(9925)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9925, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6598_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5208, 704}, +/*h(11973)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11973, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4160_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7256, 704}, +/*h(14021)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14021, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1722_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9304, 704}, +/*h(16069)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16069, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(600)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2648)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2648; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6908_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8792, 704}, +/*h(2027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2027, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4470_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10840, 704}, +/*h(4075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4075, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2032_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12888, 704}, +/*h(6123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {6123, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8746_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14936, 704}, +/*h(8171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {8171, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1624)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1624; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3672)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7768, 704}, +/*h(1003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {1003, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9816, 704}, +/*h(3051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3051, 715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3251_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11864, 704}, +/*h(5099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=1*/ {5099, 2063} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_813_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13912, 704}, +/*h(7147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=1*/ {7147, 2062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7527_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15960, 704}, +/*h(9195)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {9195, 716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11802, 706}, +/*h(856)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {856, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7053_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2904, 704}, +/*h(13850)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13850, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4615_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4952, 704}, +/*h(15898)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15898, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9048; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6453_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {150, 707}, +/*h(11096)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11096, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4015_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2198)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2198, 707}, +/*h(13144)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13144, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1577_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15192, 704}, +/*h(4246)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4246, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1880, 704}, +/*h(12826)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12826, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5834_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14874, 706}, +/*h(3928)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3928, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5234_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12120, 704}, +/*h(1174)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1174, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3222, 707}, +/*h(14168)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14168, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5270, 707}, +/*h(16216)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16216, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 704}, +/*h(6885)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6885, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8933)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8933, 704}, +/*h(2168)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2168, 704}, +/*h(13114)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {13114, 722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5777_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4216, 704}, +/*h(15162)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {15162, 722}, +/*h(10981)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10981, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((9*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1144, 704}, +/*h(7909)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7909, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6996_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3192, 704}, +/*h(14138)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {14138, 723}, +/*h(9957)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9957, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4558_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12005)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12005, 704}, +/*h(16186)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {16186, 723}, +/*h(5240)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5240, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15480)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(632)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2680)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6776, 704}, +/*h(11)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4868_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8824, 704}, +/*h(2059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2059, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10872, 704}, +/*h(4107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4107, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12920, 704}, +/*h(6155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6155, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6706_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14968, 704}, +/*h(8203)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8203, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1656)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1656; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3704)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6087_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7800, 704}, +/*h(1035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1035, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3649_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9848, 704}, +/*h(3083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3083, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1211_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11896, 704}, +/*h(5131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5131, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7925_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13944, 704}, +/*h(7179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7179, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15992, 704}, +/*h(9227)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9227, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7451_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {888, 704}, +/*h(11834)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11834, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2936, 704}, +/*h(13882)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13882, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2575_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15930, 706}, +/*h(4984)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4984, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9080)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12858, 706}, +/*h(1912)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1912, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3794_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3960)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3960, 704}, +/*h(14906)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14906, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6008)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8613_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {152, 704}, +/*h(11098)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11098, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13146, 709}, +/*h(2200)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2200, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3737_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4248, 704}, +/*h(15194)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15194, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8013_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14488)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7394_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1176, 704}, +/*h(12122)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12122, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4956_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3224, 704}, +/*h(14170)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14170, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16218, 709}, +/*h(5272)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5272, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9368)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15512)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(664)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2712)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6808, 704}, +/*h(43)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {43, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8856, 704}, +/*h(4675)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4675, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_389_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10904, 704}, +/*h(6723)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6723, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2006)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {2006, 713}, +/*h(12952)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12952, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4665_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15000, 704}, +/*h(4054)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4054, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1688)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3736)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4047_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7832, 704}, +/*h(1067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1067, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1608_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9880, 704}, +/*h(5699)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5699, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7747)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7747, 706}, +/*h(11928)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11928, 704}, +/*h(982)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {982, 713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5884_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3030, 713}, +/*h(13976)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13976, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3446_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5078)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5078, 713}, +/*h(16024)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16024, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {920, 704}, +/*h(11866)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11866, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2973_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13914, 706}, +/*h(2968)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2968, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5016, 704}, +/*h(15962)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15962, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7064)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11160)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1944, 704}, +/*h(12890)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12890, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1754_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3992)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3992, 704}, +/*h(14938)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14938, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10136)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6573_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11130, 710}, +/*h(184)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {184, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4135_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2232, 704}, +/*h(13178)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13178, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1697_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4280, 704}, +/*h(15226)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15226, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8411_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10424)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12472)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12472, 704}, +/*h(5707)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5707, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7811_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14520)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14520, 704}, +/*h(7755)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7755, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1208, 704}, +/*h(12154)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12154, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2916_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14202, 710}, +/*h(3256)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3256, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_478_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5304, 704}, +/*h(16250)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16250, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9400)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11448)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9030_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13496)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13496, 704}, +/*h(6731)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6731, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6592_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15544)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15544, 704}, +/*h(8779)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8779, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(696)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2744)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4792)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4792; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6840)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8888)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10936)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5063_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12984, 704}, +/*h(2038)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {2038, 714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2625_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4086)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {4086, 715}, +/*h(15032)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15032, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1720)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3768)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5816)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7864)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9912)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6282_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {1014, 714}, +/*h(11960)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11960, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {3062, 715}, +/*h(14008)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14008, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16056, 704}, +/*h(5110)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {5110, 720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11898, 706}, +/*h(952)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {952, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_933_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3000)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3000, 704}, +/*h(13946)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13946, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7647_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5048)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5048, 704}, +/*h(15994)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15994, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9144)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9144; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11192)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13240)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1976, 704}, +/*h(12922)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12922, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8866_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14970, 706}, +/*h(4024)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4024, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6072)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8120)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10168)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16312)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16312; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4533_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {216, 704}, +/*h(11162)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11162, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2095_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2264)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2264, 704}, +/*h(13210)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13210, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8809_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15258, 711}, +/*h(4312)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4312, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6360)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3933_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8408)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8408, 704}, +/*h(1643)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1643, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10456)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10456, 704}, +/*h(3691)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3691, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12504)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12504, 704}, +/*h(5739)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5739, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5771_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14552)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14552, 704}, +/*h(7787)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7787, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12186, 711}, +/*h(1240)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1240, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_876_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3288)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3288, 704}, +/*h(14234)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14234, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7590_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5336)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5336, 704}, +/*h(16282)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16282, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7384)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7384, 704}, +/*h(619)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {619, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2714_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9432)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9432, 704}, +/*h(2667)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2667, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11480)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11480, 704}, +/*h(4715)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4715, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6990_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13528)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13528, 704}, +/*h(6763)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6763, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15576)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15576, 704}, +/*h(8811)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8811, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(728)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2776)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4824)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6872)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8920)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10968)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10968, 704}, +/*h(22)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {22, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3023_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2070, 707}, +/*h(13016)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13016, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4118)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4118, 707}, +/*h(15064)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15064, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1752)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3800)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5848)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7896)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9944)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1046, 707}, +/*h(11992)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11992, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1804_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14040, 704}, +/*h(3094)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3094, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5142)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5142, 707}, +/*h(16088)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16088, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(984)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {984, 704}, +/*h(11930)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11930, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8045_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3032)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3032, 704}, +/*h(13978)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13978, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5607_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16026, 706}, +/*h(5080)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5080, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7128)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9176)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11224)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12954, 706}, +/*h(2008)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2008, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6826_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4056)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4056, 704}, +/*h(15002)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15002, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6104)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8152)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10200)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14296)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14296; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2493_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(248)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {248, 704}, +/*h(11194)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11194, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13242, 712}, +/*h(2296)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2296, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6769_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4344)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4344, 704}, +/*h(15290)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15290, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6392)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8440)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8440, 704}, +/*h(1675)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1675, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8607_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10488)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10488, 704}, +/*h(3723)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3723, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12536)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12536, 704}, +/*h(5771)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5771, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3731_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14584)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14584, 704}, +/*h(7819)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7819, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1274_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1272)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1272, 704}, +/*h(12218)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12218, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7988_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3320)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3320, 704}, +/*h(14266)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14266, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5550_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16314, 712}, +/*h(5368)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5368, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7416)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7416, 704}, +/*h(651)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {651, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9464)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9464, 704}, +/*h(2699)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2699, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7388_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11512)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11512, 704}, +/*h(4747)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4747, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4950_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13560)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13560, 704}, +/*h(6795)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6795, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2512_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15608)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15608, 704}, +/*h(8843)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8843, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(760)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2808)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4856)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6904)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8952)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3421_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(54)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {54, 707}, +/*h(11000)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11000, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_983_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2102, 707}, +/*h(13048)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13048, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7697_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15096)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15096, 704}, +/*h(4150)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4150, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1784)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3832)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5880)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7928)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9976)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12024)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12024, 704}, +/*h(1078)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1078, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8916_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3126)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3126, 707}, +/*h(14072)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14072, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6478_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5174)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5174, 707}, +/*h(16120)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16120, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8443_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1016)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1016, 704}, +/*h(11962)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11962, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6005_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14010, 706}, +/*h(3064)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3064, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3566_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5112)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5112, 704}, +/*h(11877)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11877, 704}, +/*h(931)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {931, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13925)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13925, 704}, +/*h(7160)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7160, 704}, +/*h(2979)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2979, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7842_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9208)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9208, 704}, +/*h(15973)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15973, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11256)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13304)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15352)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15352; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7224_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2040)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2040, 704}, +/*h(12986)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12986, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4088)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4088, 704}, +/*h(10853)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10853, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2347_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12901)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12901, 704}, +/*h(1955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1955, 712}, +/*h(6136)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6136, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8184)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8184, 704}, +/*h(14949)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14949, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10232)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12280)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14328)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16376)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10947, 706}, +/*h(1)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3218_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2049, 704}, +/*h(12995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12995, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_780_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4097, 704}, +/*h(15043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15043, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1025, 704}, +/*h(11971)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11971, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1999_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14019)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14019, 706}, +/*h(3073)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3073, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5121, 704}, +/*h(16067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16067, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(513)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2561)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4609)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6657)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9022_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1708_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1537)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3585)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5633)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3616_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(33)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {33, 704}, +/*h(10979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10979, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2081, 704}, +/*h(13027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13027, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7892_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15075)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15075, 706}, +/*h(4129)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4129, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4854_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12003)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12003, 706}, +/*h(1057)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1057, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3105, 704}, +/*h(14051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14051, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5153, 704}, +/*h(16099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16099, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(545)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13539)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13539, 705}, +/*h(2593)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2593, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2706_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4641)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4641, 704}, +/*h(15587)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15587, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1569)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3925_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3617)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3617, 704}, +/*h(14563)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14563, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5665)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1032_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(65)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {65, 704}, +/*h(11011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11011, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13059)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13059, 708}, +/*h(2113)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2113, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5852_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4161, 704}, +/*h(15107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15107, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3414_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10390)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10390, 707}, +/*h(6209)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6209, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_976_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12438)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12438, 707}, +/*h(8257)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8257, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1089, 704}, +/*h(12035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12035, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3137, 704}, +/*h(14083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14083, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4633_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16131, 708}, +/*h(5185)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5185, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11414)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11414, 707}, +/*h(7233)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7233, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8909_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13462)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13462, 707}, +/*h(9281)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9281, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4032_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(577)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2625)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1601)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3649)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(97)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 97; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_773_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(609)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2657)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7778_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1633)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8997_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14465)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15489)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(641)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1665)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3445_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {897, 704}, +/*h(11843)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11843, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1007_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2945, 704}, +/*h(13891)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13891, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7721_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15939, 706}, +/*h(4993)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4993, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2226_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12867, 706}, +/*h(1921)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1921, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8940_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3969, 704}, +/*h(14915)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14915, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14497)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13473)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15521)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {929, 704}, +/*h(11875)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11875, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8119_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13923, 706}, +/*h(2977)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2977, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5681_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5025, 704}, +/*h(15971)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15971, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_186_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1953, 704}, +/*h(12899)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12899, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6900_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4001, 704}, +/*h(14947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14947, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1967_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12481)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14529)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8062_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_748_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13505)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15553)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11907, 706}, +/*h(961)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {961, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6079_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3009, 704}, +/*h(13955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13955, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3641_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5057, 704}, +/*h(16003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16003, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7298_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1985, 704}, +/*h(12931)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12931, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4860_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14979, 706}, +/*h(4033)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4033, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {225, 704}, +/*h(11171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11171, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2273, 704}, +/*h(13219)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13219, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4803_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15267, 712}, +/*h(4321)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4321, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10465)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12513)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14561)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12195, 712}, +/*h(1249)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1249, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3297, 704}, +/*h(14243)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14243, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3584_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5345, 704}, +/*h(16291)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16291, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11489)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13537)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15585)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {993, 704}, +/*h(11939)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11939, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4039_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3041, 704}, +/*h(13987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13987, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1601_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16035)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16035, 706}, +/*h(5089)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5089, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5258_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12963, 706}, +/*h(2017)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2017, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2820_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4065, 704}, +/*h(15011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15011, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4636_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {17, 704}, +/*h(10963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10963, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13011)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13011, 706}, +/*h(2065)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2065, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4113, 704}, +/*h(15059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15059, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1041, 704}, +/*h(11987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11987, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_979_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3089, 704}, +/*h(14035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14035, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16083)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16083, 706}, +/*h(5137)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5137, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2817_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(529)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2577)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4625)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1553)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3601)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5649)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10995)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10995, 706}, +/*h(49)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {49, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2097, 704}, +/*h(13043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13043, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6872_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4145, 704}, +/*h(15091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15091, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1996_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1073, 704}, +/*h(12019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12019, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8091_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14067)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14067, 706}, +/*h(3121)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3121, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5653_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5169, 704}, +/*h(16115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16115, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(561)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {561, 704}, +/*h(11507)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11507, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2609)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2609, 704}, +/*h(13555)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13555, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15603)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15603, 707}, +/*h(4657)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4657, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5962_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5343_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12531)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12531, 707}, +/*h(1585)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1585, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2905_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3633)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3633, 704}, +/*h(14579)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14579, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11027, 708}, +/*h(4262)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4262, 705}, +/*h(81)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {81, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5286)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5286, 705}, +/*h(1105)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1105, 704}, +/*h(12051)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12051, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(593)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2641)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1617)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3665)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8962_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15473)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(625)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6758_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1649)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8741_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4977, 704}, +/*h(15923)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15923, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14481)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15505)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(657)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2425_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11859, 706}, +/*h(913)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {913, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2961, 704}, +/*h(13907)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13907, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6701_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5009, 704}, +/*h(15955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15955, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1206_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1937, 704}, +/*h(12883)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12883, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7920_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14931, 706}, +/*h(3985)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3985, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12465)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14513)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13489)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15537)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_385_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {945, 704}, +/*h(11891)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11891, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7099_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2993, 704}, +/*h(13939)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13939, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4661_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15987, 706}, +/*h(5041)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5041, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12915, 706}, +/*h(1969)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1969, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5880_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4017, 704}, +/*h(14963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14963, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1547_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {209, 704}, +/*h(11155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11155, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13203, 711}, +/*h(2257)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2257, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5823_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4305, 704}, +/*h(15251)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15251, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12497)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2785_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14545)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1233, 704}, +/*h(12179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12179, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7042_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3281, 704}, +/*h(14227)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14227, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4604_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16275, 711}, +/*h(5329)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5329, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11473)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13521)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15569)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7497_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {977, 704}, +/*h(11923)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11923, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5059_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13971, 706}, +/*h(3025)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3025, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2621_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5073, 704}, +/*h(16019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16019, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2001, 704}, +/*h(12947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12947, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3840_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4049, 704}, +/*h(14995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14995, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8659_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11187, 712}, +/*h(241)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {241, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6221_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2289, 704}, +/*h(13235)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13235, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3783_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4337, 704}, +/*h(15283)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15283, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10481)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12529)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14577)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1265, 704}, +/*h(12211)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12211, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5002_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14259, 712}, +/*h(3313)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3313, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2564_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5361, 704}, +/*h(16307)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16307, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6840_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11505)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13553)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15601)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {9030, 709}, +/*h(4849)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4849, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2873_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8969_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8006)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8006, 709}, +/*h(3825)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3825, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10054)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {10054, 709}, +/*h(5873)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5873, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5457_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11955, 706}, +/*h(1009)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1009, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3019_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3057, 704}, +/*h(14003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14003, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5105, 704}, +/*h(16051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16051, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4238_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2033, 704}, +/*h(12979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12979, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1800_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15027, 706}, +/*h(4081)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4081, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_825_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5, 704}, +/*h(10951)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10951, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7539_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12999)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12999, 706}, +/*h(2053)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2053, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4101)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4101, 704}, +/*h(15047)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15047, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6149)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8197)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10245)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12293)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14341)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1029)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1029, 704}, +/*h(11975)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11975, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6320_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3077)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3077, 704}, +/*h(14023)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14023, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3882_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16071)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16071, 706}, +/*h(5125)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5125, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7173)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7173; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9221)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9221; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11269)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11269; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13317)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13317; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15365)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4791_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7282, 707}, +/*h(517)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {517, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9330, 707}, +/*h(2565)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2565, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9067_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11378, 707}, +/*h(4613)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4613, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13426, 707}, +/*h(6661)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6661, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15474)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15474, 707}, +/*h(8709)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8709, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10757)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {1859, 709}, +/*h(12805)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12805, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6029_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14853)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14853, 704}, +/*h(3907)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {3907, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8306, 707}, +/*h(1541)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1541, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1134_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10354, 707}, +/*h(3589)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3589, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7848_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12402, 707}, +/*h(5637)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5637, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14450, 707}, +/*h(7685)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7685, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9733)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11781)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11781, 704}, +/*h(835)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {835, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7248_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {2883, 709}, +/*h(13829)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13829, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4810_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {4931, 709}, +/*h(15877)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15877, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(773)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2821)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4869)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6917)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8965)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3736_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11013)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11013, 704}, +/*h(67)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {67, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1298_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2115, 705}, +/*h(13061)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13061, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8012_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4163, 705}, +/*h(15109)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15109, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1797)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3845)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5893)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7941)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9989)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1091)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1091, 705}, +/*h(12037)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12037, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14085)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14085, 704}, +/*h(3139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3139, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6793_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5187, 705}, +/*h(16133)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16133, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7937_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10983)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10983, 706}, +/*h(37)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {37, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5499_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2085)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2085, 704}, +/*h(13031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13031, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4133)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4133, 704}, +/*h(15079)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15079, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6181)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6181; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8229)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10277)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10277; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12325)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14373)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6718_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1061)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1061, 704}, +/*h(12007)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12007, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4280_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14055)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14055, 706}, +/*h(3109)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3109, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1842_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5157)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5157, 704}, +/*h(16103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16103, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7205)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7205; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9253)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11301)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11301; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13349)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15397)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2751_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7314, 707}, +/*h(549)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {549, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_313_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2597)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2597, 704}, +/*h(13543)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13543, 705}, +/*h(9362)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9362, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7027_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11410, 707}, +/*h(15591)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15591, 705}, +/*h(4645)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4645, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6693)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8741)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10789)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6427_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12837)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12837, 704}, +/*h(1891)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {1891, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3989_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {3939, 710}, +/*h(14885)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14885, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1532_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8338, 707}, +/*h(1573)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1573, 704}, +/*h(12519)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12519, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3621)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3621, 704}, +/*h(14567)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14567, 705}, +/*h(10386)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10386, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((9*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5669)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7717)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9765)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7646_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {867, 710}, +/*h(11813)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11813, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {2915, 710}, +/*h(13861)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13861, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2770_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15909)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15909, 704}, +/*h(4963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {4963, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4734_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(805)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2853)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4901)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6949)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8997)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1696_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(99)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {99, 705}, +/*h(11045)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11045, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2147, 705}, +/*h(13093)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13093, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5972_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15141)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15141, 704}, +/*h(4195)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4195, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1829)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1077_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3877)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3877; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5925)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5925; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7973)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10021)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12069)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12069, 704}, +/*h(1123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1123, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3171, 705}, +/*h(14117)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14117, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4753_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5219, 705}, +/*h(16165)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16165, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5897_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(69)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {69, 704}, +/*h(11015)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11015, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2117)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2117, 704}, +/*h(13063)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13063, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1021_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4165)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4165, 704}, +/*h(15111)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15111, 708}, +/*h(8346)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8346, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((9*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7735_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10394, 707}, +/*h(6213)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6213, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12357)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14405)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4678_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12039)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12039, 708}, +/*h(1093)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1093, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3141)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3141, 704}, +/*h(14087)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14087, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16135)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16135, 708}, +/*h(5189)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5189, 704}, +/*h(9370)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9370, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6516_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11418, 707}, +/*h(7237)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7237, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13381)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15429)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(581)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 581; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2629)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2629; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4677)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2549_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6725)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8773)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10821)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {1923, 711}, +/*h(12869)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12869, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1949_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3971, 711}, +/*h(14917)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14917, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1605)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3653)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5701)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7749)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9797)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5606_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {899, 711}, +/*h(11845)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11845, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13893)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13893, 704}, +/*h(2947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {2947, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4995)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {4995, 711}, +/*h(15941)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15941, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(837)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2885)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4933)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6981)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9029)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8808_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {131, 705}, +/*h(11077)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11077, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6370_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13125)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13125, 704}, +/*h(2179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2179, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3932_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4227, 705}, +/*h(15173)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15173, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1861)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3909)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5957)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8005)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10053)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7589_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1155, 705}, +/*h(12101)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12101, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3203, 705}, +/*h(14149)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14149, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16197)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16197, 704}, +/*h(5251)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5251, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3856_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6866, 706}, +/*h(101)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {101, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1418_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8914, 706}, +/*h(2149)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2149, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10962, 706}, +/*h(4197)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4197, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13010, 706}, +/*h(6245)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6245, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15058, 706}, +/*h(8293)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8293, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10341)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12389)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14437)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7890, 706}, +/*h(1125)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1125, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9938, 706}, +/*h(3173)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3173, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6913_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11986, 706}, +/*h(5221)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5221, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14034, 706}, +/*h(7269)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7269, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2037_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16082, 706}, +/*h(9317)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9317, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11365)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13413)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15461)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(613)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 613; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2661)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4709)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6757)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8805)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1637)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3685)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1728_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5733)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7781)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9829)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(869)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2917)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4965)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7013)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7013; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9061)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6768_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11109)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11109, 704}, +/*h(163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {163, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4330_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2211, 705}, +/*h(13157)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13157, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1892_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4259, 705}, +/*h(15205)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15205, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1893)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3941)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5989)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8037)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10085)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10085; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1187, 705}, +/*h(12133)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12133, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14181)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14181, 704}, +/*h(3235)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3235, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5283, 705}, +/*h(16229)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16229, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6898, 706}, +/*h(133)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {133, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8530_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8946, 706}, +/*h(2181)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2181, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6092_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10994, 706}, +/*h(4229)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4229, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13042, 706}, +/*h(6277)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6277, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15090, 706}, +/*h(8325)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8325, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10373)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12421)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14469)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7922, 706}, +/*h(1157)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1157, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9970, 706}, +/*h(3205)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3205, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4873_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12018, 706}, +/*h(5253)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5253, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14066, 706}, +/*h(7301)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7301, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16114, 706}, +/*h(9349)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9349, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11397)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13445)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15493)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(645)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2693)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4741)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1669)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3717)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8840_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5765)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7766_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11847)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11847, 706}, +/*h(901)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {901, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2949)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2949, 704}, +/*h(13895)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13895, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2890_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4997)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4997, 704}, +/*h(15943)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15943, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7045)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7045; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9093)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4728_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {195, 705}, +/*h(11141)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11141, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2243, 705}, +/*h(13189)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13189, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9004_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15237)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15237, 704}, +/*h(4291)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4291, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6547_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1925)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1925, 704}, +/*h(12871)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12871, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14919)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14919, 706}, +/*h(3973)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3973, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6021)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8069)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10117)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3509_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12165)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12165, 704}, +/*h(1219)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1219, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3267, 705}, +/*h(14213)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14213, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5315, 705}, +/*h(16261)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16261, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8928_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {6930, 708}, +/*h(165)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {165, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {8978, 708}, +/*h(2213)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2213, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4052_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11026, 708}, +/*h(4261)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4261, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13074, 708}, +/*h(6309)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6309, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15122, 708}, +/*h(8357)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8357, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10405)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12453)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14501)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14501; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7709_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {7954, 708}, +/*h(1189)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1189, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {10002, 708}, +/*h(3237)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3237, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2833_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12050, 708}, +/*h(5285)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5285, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14098, 708}, +/*h(7333)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7333, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16146, 708}, +/*h(9381)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9381, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11429)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13477)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13477; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15525)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(677)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2725)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4773)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1701)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3749)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5797)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5726_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(933)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {933, 704}, +/*h(11879)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11879, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2981)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2981, 704}, +/*h(13927)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13927, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_850_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15975)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15975, 706}, +/*h(5029)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5029, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7077)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7077; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9125)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {227, 705}, +/*h(11173)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11173, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13221)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13221, 704}, +/*h(2275)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2275, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6964_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4323, 705}, +/*h(15269)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15269, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4507_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12903, 706}, +/*h(1957)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1957, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2069_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4005)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4005, 704}, +/*h(14951)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14951, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6053)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8101)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10149)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1469_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1251, 705}, +/*h(12197)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12197, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3299, 705}, +/*h(14245)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14245, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5745_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16293)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16293, 704}, +/*h(5347)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5347, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6888_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {6962, 722}, +/*h(197)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {197, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4450_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {9010, 722}, +/*h(2245)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2245, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2012_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {11058, 722}, +/*h(4293)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4293, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8726_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {13106, 722}, +/*h(6341)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6341, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {15154, 722}, +/*h(8389)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8389, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10437)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1539)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1539, 706}, +/*h(12485)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12485, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8126_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3587)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3587, 706}, +/*h(14533)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14533, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1221)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1221; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3269)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3269; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5317)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5317; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7365)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9413)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2631_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(515)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {515, 706}, +/*h(11461)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11461, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13509)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13509, 704}, +/*h(2563)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2563, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6907_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4611)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4611, 706}, +/*h(15557)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15557, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(709)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2757)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4805)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1733)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3781)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5829)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(965)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {965, 704}, +/*h(11911)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11911, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1248_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13959)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13959, 706}, +/*h(3013)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3013, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7962_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5061)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5061, 704}, +/*h(16007)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16007, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7109)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7109; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9157)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9157; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11205)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11205; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13253)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15301)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15301; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1989)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1989, 704}, +/*h(12935)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12935, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4037)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4037, 704}, +/*h(14983)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14983, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6085)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6085; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8133)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10181)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10181; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12229)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14277)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14277; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3705_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16325)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4848_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11175)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11175, 712}, +/*h(229)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {229, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2277)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2277, 704}, +/*h(13223)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13223, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4325)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4325, 704}, +/*h(15271)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15271, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6373)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8421)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10469)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8524_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1571)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1571, 706}, +/*h(12517)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12517, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6086_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14565)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14565, 704}, +/*h(3619)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3619, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1253)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1253, 704}, +/*h(12199)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12199, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14247, 712}, +/*h(3301)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3301, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7905_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5349)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5349, 704}, +/*h(16295)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16295, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7397)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9445)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11493)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11493, 704}, +/*h(547)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {547, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7305_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2595)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2595, 706}, +/*h(13541)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13541, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4867_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4643)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4643, 706}, +/*h(15589)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15589, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(741)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2789)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4837)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1765)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3813)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5861)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1646_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11943)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11943, 706}, +/*h(997)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {997, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3045)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3045, 704}, +/*h(13991)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13991, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5922_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5093)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5093, 704}, +/*h(16039)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16039, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7141)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7141; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9189)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11237)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11237; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13285)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13285; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15333)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15333; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2021)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2021, 704}, +/*h(12967)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12967, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15015)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15015, 706}, +/*h(4069)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4069, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6117)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8165)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10213)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10213; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12261)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12261; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14309)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14309; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16357)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8957_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {21, 704}, +/*h(10967)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10967, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6519_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2069)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2069, 704}, +/*h(13015)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13015, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4081_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15063)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15063, 706}, +/*h(4117)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4117, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6165)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8213)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8213; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10261)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10261; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12309)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12309; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14357)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7738_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11991)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11991, 706}, +/*h(1045)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1045, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3093)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3093, 704}, +/*h(14039)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14039, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5141)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5141, 704}, +/*h(16087)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16087, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7189)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9237)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9237; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11285)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11285; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13333)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13333; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15381)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3771_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7298, 705}, +/*h(533)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {533, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1333_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9346, 705}, +/*h(2581)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2581, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8047_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11394, 705}, +/*h(4629)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4629, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5609_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13442, 705}, +/*h(6677)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6677, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15490)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15490, 705}, +/*h(8725)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8725, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10773)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {1875, 709}, +/*h(12821)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12821, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5009_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {3923, 709}, +/*h(14869)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14869, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8322, 705}, +/*h(1557)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1557, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10370, 705}, +/*h(3605)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3605, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6828_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12418, 705}, +/*h(5653)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5653, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14466, 705}, +/*h(7701)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7701, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1952_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9749)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8666_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {851, 709}, +/*h(11797)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11797, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6228_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13845)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13845, 704}, +/*h(2899)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {2899, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3790_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {4947, 709}, +/*h(15893)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15893, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(789)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2837)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4885)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6933)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8981)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(83)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {83, 707}, +/*h(11029)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11029, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13077)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13077, 704}, +/*h(2131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2131, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6992_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4179, 707}, +/*h(15125)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15125, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1813)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2097_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3861)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5909)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7957)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10005)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1497_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1107, 707}, +/*h(12053)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12053, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8211_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3155, 707}, +/*h(14101)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14101, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5773_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16149)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16149, 704}, +/*h(5203)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5203, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6917_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(53)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {53, 704}, +/*h(10999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10999, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13047)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13047, 706}, +/*h(2101)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2101, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2041_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4149)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4149, 704}, +/*h(15095)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15095, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6197)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8245)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10293)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12341)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14389)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5698_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1077)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1077, 704}, +/*h(12023)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12023, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3260_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3125)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3125, 704}, +/*h(14071)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14071, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_822_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16119)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16119, 706}, +/*h(5173)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5173, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7221)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7221; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9269)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9269; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2660_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15498)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15498, 705}, +/*h(11317)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11317, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13365)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1731_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11511)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11511, 707}, +/*h(565)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {565, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8445_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2613)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2613, 704}, +/*h(13559)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13559, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6007_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4661)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4661, 704}, +/*h(15607)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15607, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6709)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8757)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10805)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5407_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {1907, 710}, +/*h(12853)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12853, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2969_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14901)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14901, 704}, +/*h(3955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {3955, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1589)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1589, 704}, +/*h(12535)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12535, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7226_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14583)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14583, 707}, +/*h(3637)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3637, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5685)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7733)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9781)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6626_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11829)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11829, 704}, +/*h(883)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {883, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {2931, 710}, +/*h(13877)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13877, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {4979, 710}, +/*h(15925)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15925, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(821)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2869)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4917)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6965)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9013)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9013; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11061)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11061, 704}, +/*h(115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {115, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2163, 707}, +/*h(13109)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13109, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4211, 707}, +/*h(15157)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15157, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1845)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3893)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5941)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7989)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10037)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8609_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1139, 707}, +/*h(12085)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12085, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14133)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14133, 704}, +/*h(3187)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3187, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3733_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5235, 707}, +/*h(16181)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16181, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4877_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(85)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {85, 704}, +/*h(11031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11031, 708}, +/*h(4266)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4266, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8898, 706}, +/*h(2133)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2133, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6714_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12994, 706}, +/*h(6229)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6229, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15042, 706}, +/*h(8277)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8277, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10325)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12373)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14421)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3657_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7874, 706}, +/*h(1109)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1109, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1219_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9922, 706}, +/*h(3157)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3157, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7933_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11970, 706}, +/*h(5205)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5205, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14018, 706}, +/*h(7253)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7253, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3057_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16066, 706}, +/*h(9301)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9301, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11349)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13397)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15445)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(597)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2645)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3967_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4693)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6741)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8789)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10837)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12885)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12885, 704}, +/*h(1939)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {1939, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_929_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3987, 711}, +/*h(14933)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14933, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1621)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3669)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2748_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5717)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7765)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9813)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4586_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {915, 711}, +/*h(11861)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11861, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2148_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {2963, 711}, +/*h(13909)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13909, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15957)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15957, 704}, +/*h(5011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {5011, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(853)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2901)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4949)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6997)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9045)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9045; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7788_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {147, 707}, +/*h(11093)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11093, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5350_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2195, 707}, +/*h(13141)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13141, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15189)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15189, 704}, +/*h(4243)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4243, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1877)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1877; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3925)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3925; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5973)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8021)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10069)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12117)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12117, 704}, +/*h(1171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1171, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4131_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3219, 707}, +/*h(14165)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14165, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5267, 707}, +/*h(16213)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16213, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6882, 706}, +/*h(117)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {117, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8930, 706}, +/*h(2165)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2165, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10978, 706}, +/*h(4213)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4213, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4674_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13026, 706}, +/*h(6261)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6261, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15074, 706}, +/*h(8309)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8309, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10357)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12405)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14453)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7906, 706}, +/*h(1141)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1141, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8331_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9954, 706}, +/*h(3189)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3189, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12002, 706}, +/*h(5237)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5237, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14050, 706}, +/*h(7285)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7285, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1017_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16098, 706}, +/*h(9333)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9333, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11381)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13429)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15477)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15477; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(629)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 629; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2677)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4725)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1653)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3701)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5749)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(885)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2933)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3910_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15927)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15927, 706}, +/*h(4981)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4981, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7029)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9077)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9077; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5748_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {179, 707}, +/*h(11125)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11125, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13173)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13173, 704}, +/*h(2227)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2227, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_872_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4275, 707}, +/*h(15221)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15221, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1909)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3957)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3957, 704}, +/*h(14903)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14903, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6005)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8053)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6967_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10101)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4529_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1203, 707}, +/*h(12149)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12149, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2091_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3251, 707}, +/*h(14197)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14197, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8805_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16245)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16245, 704}, +/*h(5299)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5299, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {6914, 708}, +/*h(149)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {149, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {8962, 708}, +/*h(2197)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2197, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5072_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11010, 708}, +/*h(4245)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4245, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2634_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13058, 708}, +/*h(6293)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6293, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15106, 708}, +/*h(8341)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8341, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10389)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12437)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14485)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8729_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {7938, 708}, +/*h(1173)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1173, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6291_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {9986, 708}, +/*h(3221)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3221, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3853_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12034, 708}, +/*h(5269)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5269, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14082, 708}, +/*h(7317)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7317, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16130, 708}, +/*h(9365)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9365, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11413)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13461)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15509)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(661)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2709)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4757)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1685)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3733)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5781)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6746_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(917)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {917, 704}, +/*h(11863)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11863, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13911)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13911, 706}, +/*h(2965)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2965, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1870_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5013)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5013, 704}, +/*h(15959)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15959, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7061)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9109)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9109; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11157)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11157, 704}, +/*h(211)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {211, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2259, 707}, +/*h(13205)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13205, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7984_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4307, 707}, +/*h(15253)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15253, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5527_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1941)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1941, 704}, +/*h(12887)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12887, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3089_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3989)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3989, 704}, +/*h(14935)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14935, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6037)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8085)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8085; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10133)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1235, 707}, +/*h(12181)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12181, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14229)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14229, 704}, +/*h(3283)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3283, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6765_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5331, 707}, +/*h(16277)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16277, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7908_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {6946, 722}, +/*h(181)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {181, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5470_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {8994, 722}, +/*h(2229)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2229, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3032_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {11042, 722}, +/*h(4277)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4277, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {13090, 722}, +/*h(6325)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6325, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {15138, 722}, +/*h(8373)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8373, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10421)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12469)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14517)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1205)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1205; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3253)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5301)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5301; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7349)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9397)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11445)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13493)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15541)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(693)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2741)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4789)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1717)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3765)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5813)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4706_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11895)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11895, 706}, +/*h(949)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {949, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2997)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2997, 704}, +/*h(13943)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13943, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8982_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5045)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5045, 704}, +/*h(15991)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15991, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7093)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9141)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9141; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1668_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {243, 707}, +/*h(11189)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11189, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8382_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2291, 707}, +/*h(13237)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13237, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15285)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15285, 704}, +/*h(4339)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4339, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1973)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1973, 704}, +/*h(12919)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12919, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1049_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14967)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14967, 706}, +/*h(4021)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4021, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6069)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8117)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10165)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_449_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12213)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12213, 704}, +/*h(1267)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1267, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3315, 707}, +/*h(14261)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14261, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5363, 707}, +/*h(16309)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16309, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5868_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11159)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11159, 711}, +/*h(6978)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6978, 709}, +/*h(213)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {213, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2261)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2261, 704}, +/*h(13207)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13207, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_992_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15255, 711}, +/*h(4309)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4309, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6357)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6357; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8405)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10453)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12501)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12501, 704}, +/*h(1555)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1555, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3603)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3603, 706}, +/*h(14549)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14549, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4649_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8002, 709}, +/*h(1237)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1237, 704}, +/*h(12183)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12183, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2211_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3285)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3285, 704}, +/*h(14231)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14231, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8925_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5333)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5333, 704}, +/*h(16279)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16279, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7381)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7381; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9429)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1611_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(531)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {531, 706}, +/*h(11477)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11477, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2579)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2579, 706}, +/*h(13525)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13525, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5887_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15573)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15573, 704}, +/*h(4627)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4627, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(725)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2773)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4821)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1749)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3797)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5845)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2666_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(981)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {981, 704}, +/*h(11927)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11927, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3029)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3029, 704}, +/*h(13975)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13975, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6942_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16023)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16023, 706}, +/*h(5077)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5077, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7125)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9173)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9173; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11221)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11221; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13269)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13269; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3904_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15317)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15317; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12951)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12951, 706}, +/*h(2005)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2005, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4053)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4053, 704}, +/*h(14999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14999, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6101)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8149)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10197)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10197; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12245)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12245; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14293)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2685_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16341)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3828_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(245)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {245, 704}, +/*h(11191)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11191, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13239)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13239, 712}, +/*h(2293)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2293, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4341)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4341, 704}, +/*h(15287)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15287, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6389)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8437)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10485)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7504_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1587)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1587, 706}, +/*h(12533)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12533, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5066_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3635)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3635, 706}, +/*h(14581)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14581, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2609_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1269)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1269, 704}, +/*h(12215)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12215, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3317)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3317, 704}, +/*h(14263)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14263, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6885_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16311)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16311, 712}, +/*h(5365)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5365, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7413)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9461)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8723_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(563)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {563, 706}, +/*h(11509)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11509, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13557)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13557, 704}, +/*h(2611)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2611, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3847_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4659)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4659, 706}, +/*h(15605)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15605, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(757)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6986, 709}, +/*h(2805)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2805, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2919_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {9034, 709}, +/*h(4853)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4853, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4756_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(51)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {51, 707}, +/*h(10997)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10997, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2099, 707}, +/*h(13045)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13045, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9032_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15093)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15093, 704}, +/*h(4147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4147, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {5962, 709}, +/*h(1781)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1781, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8010, 709}, +/*h(3829)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3829, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9973)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3537_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12021)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12021, 704}, +/*h(1075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1075, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1099_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3123, 707}, +/*h(14069)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14069, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7813_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5171, 707}, +/*h(16117)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16117, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_626_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1013)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1013, 704}, +/*h(11959)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11959, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7340_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14007)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14007, 706}, +/*h(3061)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3061, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4902_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5109)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5109, 704}, +/*h(16055)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16055, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7157)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7157; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9205)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9205; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11253)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13301)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13301; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15349)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8559_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2037)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2037, 704}, +/*h(12983)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12983, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4085)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4085, 704}, +/*h(15031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15031, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6133)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8181)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8181; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10229)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12277)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12277; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14325)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14325; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16373)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9, 704}, +/*h(10955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10955, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2057, 704}, +/*h(13003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13003, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15051)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15051, 706}, +/*h(4105)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4105, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3927_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11979, 706}, +/*h(1033)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1033, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3081, 704}, +/*h(14027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14027, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5129, 704}, +/*h(16075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16075, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7286)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7286, 707}, +/*h(521)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {521, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6674_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9334)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9334, 707}, +/*h(2569)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2569, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11382)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11382, 707}, +/*h(4617)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4617, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1798_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13430)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13430, 707}, +/*h(6665)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6665, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8512_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15478)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15478, 707}, +/*h(8713)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8713, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3636_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1863)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {1863, 709}, +/*h(12809)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12809, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3911)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {3911, 709}, +/*h(14857)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14857, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8310)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8310, 707}, +/*h(1545)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1545, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10358)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10358, 707}, +/*h(3593)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3593, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3017_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12406)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12406, 707}, +/*h(5641)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5641, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_579_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14454)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14454, 707}, +/*h(7689)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7689, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4855_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(839)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {839, 709}, +/*h(11785)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11785, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13833, 704}, +/*h(2887)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {2887, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9131_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4935)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {4935, 709}, +/*h(15881)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15881, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1943_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8057_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(71)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {71, 705}, +/*h(11017)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11017, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5619_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13065, 704}, +/*h(2119)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2119, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4167)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4167, 705}, +/*h(15113)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15113, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6838_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1095)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1095, 705}, +/*h(12041)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12041, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4400_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3143)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3143, 705}, +/*h(14089)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14089, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1962_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16137, 704}, +/*h(5191)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5191, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(41)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {41, 704}, +/*h(10987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10987, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_668_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13035)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13035, 706}, +/*h(2089)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2089, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7382_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4137, 704}, +/*h(15083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15083, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1887_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1065, 704}, +/*h(12011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12011, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8601_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3113, 704}, +/*h(14059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14059, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16107, 706}, +/*h(5161)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5161, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7072_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(553)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {553, 704}, +/*h(11499)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11499, 705}, +/*h(7318)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7318, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4634_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9366)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9366, 707}, +/*h(13547)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13547, 705}, +/*h(2601)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2601, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4649)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4649, 704}, +/*h(15595)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15595, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1895)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {1895, 710}, +/*h(12841)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12841, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14889, 704}, +/*h(3943)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {3943, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5853_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8342, 707}, +/*h(12523)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12523, 705}, +/*h(1577)=2 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1577, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14571)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14571, 705}, +/*h(3625)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3625, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2815_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11817, 704}, +/*h(871)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {871, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2919)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {2919, 710}, +/*h(13865)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13865, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7091_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4967)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {4967, 710}, +/*h(15913)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15913, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9055_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6017_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11049, 704}, +/*h(103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {103, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3579_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2151)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2151, 705}, +/*h(13097)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13097, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4199)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4199, 705}, +/*h(15145)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15145, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7836_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4798_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1127)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1127, 705}, +/*h(12073)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12073, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14121, 704}, +/*h(3175)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3175, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9074_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5223)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5223, 705}, +/*h(16169)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16169, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1066_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11019)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11019, 708}, +/*h(73)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {73, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7780_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2121, 704}, +/*h(13067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13067, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5342_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4169, 704}, +/*h(15115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15115, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8999_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1097, 704}, +/*h(12043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12043, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14091)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14091, 708}, +/*h(3145)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3145, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5193, 704}, +/*h(16139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16139, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5032_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(585)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2633)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12873, 704}, +/*h(1927)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {1927, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3975)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3975, 711}, +/*h(14921)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14921, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1609)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3657)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_775_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {903, 711}, +/*h(11849)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11849, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2951)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {2951, 711}, +/*h(13897)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13897, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5051_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15945, 704}, +/*h(4999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {4999, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6415_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3977_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(135)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {135, 705}, +/*h(11081)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11081, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1539_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2183)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2183, 705}, +/*h(13129)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13129, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8253_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15177, 704}, +/*h(4231)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4231, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12105, 704}, +/*h(1159)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1159, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3207)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3207, 705}, +/*h(14153)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14153, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7034_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5255, 705}, +/*h(16201)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16201, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6870, 706}, +/*h(105)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {105, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5739_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8918, 706}, +/*h(2153)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2153, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10966, 706}, +/*h(4201)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4201, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_863_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13014, 706}, +/*h(6249)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6249, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7577_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15062, 706}, +/*h(8297)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8297, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6958_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7894)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7894, 706}, +/*h(1129)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1129, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4520_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9942)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9942, 706}, +/*h(3177)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3177, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2082_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11990)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11990, 706}, +/*h(5225)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5225, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14038)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14038, 706}, +/*h(7273)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7273, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16086)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16086, 706}, +/*h(9321)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9321, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15465)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(617)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2665)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1773_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1641)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7887_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(935)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {935, 712}, +/*h(11881)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11881, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1937_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(167)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {167, 705}, +/*h(11113)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11113, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8651_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13161, 704}, +/*h(2215)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2215, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4263)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4263, 705}, +/*h(15209)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15209, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8032_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_718_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1191)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1191, 705}, +/*h(12137)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12137, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7432_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3239)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3239, 705}, +/*h(14185)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14185, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4994_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16233, 704}, +/*h(5287)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5287, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6902)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6902, 706}, +/*h(137)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {137, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3699_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8950)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8950, 706}, +/*h(2185)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2185, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10998, 706}, +/*h(4233)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4233, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7975_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13046, 706}, +/*h(6281)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6281, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5537_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15094, 706}, +/*h(8329)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8329, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14473)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4918_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7926)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7926, 706}, +/*h(1161)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1161, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9974)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9974, 706}, +/*h(3209)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3209, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12022)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12022, 706}, +/*h(5257)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5257, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6756_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14070, 706}, +/*h(7305)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7305, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16118)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16118, 706}, +/*h(9353)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9353, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15497)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_952_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(649)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_971_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {905, 704}, +/*h(11851)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11851, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13899, 706}, +/*h(2953)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2953, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7211_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5001, 704}, +/*h(15947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15947, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4773_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9049_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11145, 704}, +/*h(199)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {199, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6611_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2247, 705}, +/*h(13193)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13193, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4295, 705}, +/*h(15241)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15241, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1929, 704}, +/*h(12875)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12875, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3977, 704}, +/*h(14923)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14923, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7830_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1223)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1223, 705}, +/*h(12169)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12169, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14217, 704}, +/*h(3271)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3271, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5319)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5319, 705}, +/*h(16265)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16265, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6934)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {6934, 708}, +/*h(169)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {169, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1659_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8982)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {8982, 708}, +/*h(2217)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2217, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11030, 708}, +/*h(4265)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4265, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13078)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13078, 708}, +/*h(6313)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6313, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3497_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15126)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15126, 708}, +/*h(8361)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8361, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7773_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14505)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2878_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7958)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {7958, 708}, +/*h(1193)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1193, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10006)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {10006, 708}, +/*h(3241)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3241, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12054)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12054, 708}, +/*h(5289)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5289, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14102, 708}, +/*h(7337)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7337, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16150, 708}, +/*h(9385)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9385, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13481)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15529)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_895_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11883, 706}, +/*h(937)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {937, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7609_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2985, 704}, +/*h(13931)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13931, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5033, 704}, +/*h(15979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15979, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7009_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(231)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {231, 705}, +/*h(11177)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11177, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4571_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2279)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2279, 705}, +/*h(13225)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13225, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15273, 704}, +/*h(4327)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4327, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8828_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1961, 704}, +/*h(12907)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12907, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14955, 706}, +/*h(4009)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4009, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3952_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5790_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12201, 704}, +/*h(1255)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1255, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3303)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3303, 705}, +/*h(14249)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14249, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5351)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5351, 705}, +/*h(16297)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16297, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2057_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {6966, 722}, +/*h(201)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {201, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8771_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {9014, 722}, +/*h(2249)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2249, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6333_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {11062, 722}, +/*h(4297)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4297, 704}, +/*h(15243)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15243, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3895_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13110)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {13110, 722}, +/*h(6345)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6345, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5733_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12489)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12489, 704}, +/*h(1543)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1543, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3295_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3591)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3591, 706}, +/*h(14537)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14537, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5114_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5321, 704}, +/*h(16267)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16267, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(519)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {519, 706}, +/*h(11465)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11465, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4514_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2567)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2567, 706}, +/*h(13513)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13513, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2076_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15561)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15561, 704}, +/*h(4615)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4615, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8007_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {969, 704}, +/*h(11915)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11915, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3017, 704}, +/*h(13963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13963, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3131_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16011)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16011, 706}, +/*h(5065)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5065, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6788_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12939, 706}, +/*h(1993)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1993, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4350_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4041, 704}, +/*h(14987)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14987, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1912_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {233, 704}, +/*h(11179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11179, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6731_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13227, 712}, +/*h(2281)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2281, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4293_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4329, 704}, +/*h(15275)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15275, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10473)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1575)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1575, 706}, +/*h(12521)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12521, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1255_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3623)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3623, 706}, +/*h(14569)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14569, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7950_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1257, 704}, +/*h(12203)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12203, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5512_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3305, 704}, +/*h(14251)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14251, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3074_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16299, 712}, +/*h(5353)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5353, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(551)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {551, 706}, +/*h(11497)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11497, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2474_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13545)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13545, 704}, +/*h(2599)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2599, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4647)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4647, 706}, +/*h(15593)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15593, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5221_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15081, 704}, +/*h(4135)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4135, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4002_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5159)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5159, 705}, +/*h(16105)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16105, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5967_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1001, 704}, +/*h(11947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11947, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3529_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13995)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13995, 706}, +/*h(3049)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3049, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1091_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5097, 704}, +/*h(16043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16043, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4748_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2025, 704}, +/*h(12971)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12971, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4073, 704}, +/*h(15019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15019, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4126_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10971, 706}, +/*h(25)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {25, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2073, 704}, +/*h(13019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13019, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8402_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4121, 704}, +/*h(15067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15067, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2907_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1049, 704}, +/*h(11995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11995, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14043)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14043, 706}, +/*h(3097)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3097, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5145, 704}, +/*h(16091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16091, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8092_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7302, 705}, +/*h(537)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {537, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9350)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9350, 705}, +/*h(2585)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2585, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11398)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11398, 705}, +/*h(4633)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4633, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_778_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13446)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13446, 705}, +/*h(6681)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6681, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15494)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15494, 705}, +/*h(8729)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8729, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2616_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12825, 704}, +/*h(1879)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {1879, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3927)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {3927, 709}, +/*h(14873)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14873, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6873_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8326, 705}, +/*h(1561)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1561, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10374)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10374, 705}, +/*h(3609)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3609, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1997_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12422)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12422, 705}, +/*h(5657)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5657, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8711_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14470)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14470, 705}, +/*h(7705)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7705, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3835_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(855)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {855, 709}, +/*h(11801)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11801, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {2903, 709}, +/*h(13849)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13849, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15897, 704}, +/*h(4951)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {4951, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7037_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(87)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {87, 707}, +/*h(11033)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11033, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4599_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2135)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2135, 707}, +/*h(13081)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13081, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15129, 704}, +/*h(4183)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4183, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5818_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12057, 704}, +/*h(1111)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1111, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3159)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3159, 707}, +/*h(14105)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14105, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_942_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5207)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5207, 707}, +/*h(16153)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16153, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2086_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(57)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {57, 704}, +/*h(11003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11003, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8800_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2105, 704}, +/*h(13051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13051, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6362_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15099, 706}, +/*h(4153)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4153, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_867_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12027, 706}, +/*h(1081)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1081, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7581_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3129, 704}, +/*h(14075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14075, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5177, 704}, +/*h(16123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16123, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2705_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6052_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(569)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {569, 704}, +/*h(11515)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11515, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13563)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13563, 707}, +/*h(2617)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2617, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4665)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4665, 704}, +/*h(15611)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15611, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1911)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {1911, 710}, +/*h(12857)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12857, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3959)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {3959, 710}, +/*h(14905)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14905, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4833_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1593)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1593, 704}, +/*h(12539)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12539, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3641)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3641, 704}, +/*h(14587)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14587, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1795_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(887)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {887, 710}, +/*h(11833)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11833, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8509_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13881, 704}, +/*h(2935)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {2935, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4983)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {4983, 710}, +/*h(15929)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15929, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8035_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4997_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(119)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {119, 707}, +/*h(11065)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11065, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2559_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13113, 704}, +/*h(2167)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2167, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4215)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4215, 707}, +/*h(15161)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15161, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6816_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3778_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1143)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1143, 707}, +/*h(12089)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12089, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1340_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3191)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3191, 707}, +/*h(14137)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14137, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8054_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16185, 704}, +/*h(5239)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5239, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6854)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6854, 706}, +/*h(89)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {89, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6759_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8902)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8902, 706}, +/*h(2137)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2137, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4321_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10950)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10950, 706}, +/*h(4185)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4185, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1883_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12998, 706}, +/*h(6233)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6233, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15046, 706}, +/*h(8281)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8281, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7978_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7878)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7878, 706}, +/*h(1113)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1113, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9926)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9926, 706}, +/*h(3161)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3161, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11974)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11974, 706}, +/*h(5209)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5209, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_664_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14022)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14022, 706}, +/*h(7257)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7257, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16070, 706}, +/*h(9305)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9305, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(601)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2649)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1943)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {1943, 711}, +/*h(12889)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12889, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14937, 704}, +/*h(3991)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3991, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1625)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3673)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8907_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11865, 704}, +/*h(919)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {919, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6469_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2967)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {2967, 711}, +/*h(13913)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13913, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4031_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5015)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {5015, 711}, +/*h(15961)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15961, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5995_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9049; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2957_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11097, 704}, +/*h(151)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {151, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2199)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2199, 707}, +/*h(13145)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13145, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7233_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4247, 707}, +/*h(15193)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15193, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1738_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1175)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1175, 707}, +/*h(12121)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12121, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8452_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14169, 704}, +/*h(3223)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3223, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6014_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5271)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5271, 707}, +/*h(16217)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16217, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7157_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6886, 706}, +/*h(121)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {121, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8934)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8934, 706}, +/*h(2169)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2169, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10982)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10982, 706}, +/*h(4217)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4217, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8995_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13030, 706}, +/*h(6265)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6265, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6557_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15078)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15078, 706}, +/*h(8313)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8313, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5938_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7910)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7910, 706}, +/*h(1145)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1145, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9958)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9958, 706}, +/*h(3193)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3193, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1062_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12006)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12006, 706}, +/*h(5241)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5241, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14054)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14054, 706}, +/*h(7289)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7289, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16102, 706}, +/*h(9337)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9337, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15481)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(633)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2681)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1657)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3705)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2937, 704}, +/*h(13883)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13883, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8231_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4985, 704}, +/*h(15931)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15931, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_917_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(183)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {183, 707}, +/*h(11129)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11129, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7631_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2231)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2231, 707}, +/*h(13177)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13177, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15225, 704}, +/*h(4279)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4279, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2736_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1913, 704}, +/*h(12859)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12859, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14907, 706}, +/*h(3961)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3961, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8850_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12153, 704}, +/*h(1207)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1207, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3255, 707}, +/*h(14201)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14201, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5303)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5303, 707}, +/*h(16249)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16249, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {6918, 708}, +/*h(153)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {153, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2679_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {8966, 708}, +/*h(2201)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2201, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {11014, 708}, +/*h(4249)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4249, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6955_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13062, 708}, +/*h(6297)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6297, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15110)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15110, 708}, +/*h(8345)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8345, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14489)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3898_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7942)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {7942, 708}, +/*h(1177)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1177, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9990)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {9990, 708}, +/*h(3225)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3225, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12038)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12038, 708}, +/*h(5273)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5273, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5736_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14086)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14086, 708}, +/*h(7321)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {7321, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3298_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16134)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16134, 708}, +/*h(9369)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9369, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13465)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15513)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(665)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2713)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8857)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10905)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1689)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3737)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9881)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4827_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1915_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {921, 704}, +/*h(11867)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11867, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2969, 704}, +/*h(13915)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13915, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15963, 706}, +/*h(5017)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5017, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9113)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8029_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(215)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {215, 707}, +/*h(11161)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11161, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5591_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13209, 704}, +/*h(2263)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2263, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4311)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4311, 707}, +/*h(15257)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15257, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12891, 706}, +/*h(1945)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1945, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3993, 704}, +/*h(14939)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14939, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6810_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1239)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1239, 707}, +/*h(12185)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12185, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4372_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3287)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3287, 707}, +/*h(14233)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14233, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16281, 704}, +/*h(5335)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5335, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3077_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6950)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {6950, 722}, +/*h(185)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {185, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_639_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {8998, 722}, +/*h(2233)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2233, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {11046, 722}, +/*h(4281)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4281, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4915_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {13094, 722}, +/*h(6329)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6329, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15142)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {15142, 722}, +/*h(8377)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8377, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10425)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12473)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14521)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9401)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11449)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13497)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15545)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(697)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2745)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4793)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6841)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8889)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10937)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12985)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1721)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3769)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5817)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7865)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9913)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11961)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16057)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16057; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9027_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {953, 704}, +/*h(11899)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11899, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6589_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13947, 706}, +/*h(3001)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3001, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5049)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5049, 704}, +/*h(15995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15995, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1713_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7097)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9145)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5989_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11193)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11193, 704}, +/*h(247)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {247, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3551_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2295, 707}, +/*h(13241)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13241, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15289)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7808_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1977, 704}, +/*h(12923)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12923, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5370_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4025)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4025, 704}, +/*h(14971)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14971, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8121)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10169)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4770_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1271)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1271, 707}, +/*h(12217)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12217, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14265, 704}, +/*h(3319)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3319, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1037_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(217)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {217, 704}, +/*h(11163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {11163, 711}, +/*h(6982)=2 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6982, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7751_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2265)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2265, 704}, +/*h(13211)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {13211, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5313_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4313)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4313, 704}, +/*h(15259)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {15259, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6361)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8409)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10457)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1559)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1559, 706}, +/*h(12505)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12505, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14553)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14553, 704}, +/*h(3607)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3607, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8970_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1241)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1241, 704}, +/*h(12187)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {12187, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6532_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {14235, 711}, +/*h(3289)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3289, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4094_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5337)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5337, 704}, +/*h(16283)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {16283, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1656_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7385)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9433)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5932_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11481)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11481, 704}, +/*h(535)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {535, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3494_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2583)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2583, 706}, +/*h(13529)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13529, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1056_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4631)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4631, 706}, +/*h(15577)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15577, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(729)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2777)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4825)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6873)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8921)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10969)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3785_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1753)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3801)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5849)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7897)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9945)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11993)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14041)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5023_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6987_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11931, 706}, +/*h(985)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {985, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3033)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3033, 704}, +/*h(13979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13979, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5081)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5081, 704}, +/*h(16027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16027, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7129)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9177)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11225)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13273)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5768_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2009)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2009, 704}, +/*h(12955)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12955, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3330_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15003)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15003, 706}, +/*h(4057)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4057, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6105)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8153)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10201)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16345)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(249)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {249, 704}, +/*h(11195)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {11195, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5711_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2297)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2297, 704}, +/*h(13243)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {13243, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3273_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {15291, 712}, +/*h(4345)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4345, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6393)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7549_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8441)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10489)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12537)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12537, 704}, +/*h(1591)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1591, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3639)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3639, 706}, +/*h(14585)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14585, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6930_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {12219, 712}, +/*h(1273)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1273, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3321)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3321, 704}, +/*h(14267)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {14267, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2054_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5369)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5369, 704}, +/*h(16315)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {16315, 712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7417)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9465)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3892_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(567)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {567, 706}, +/*h(11513)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11513, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2615)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2615, 706}, +/*h(13561)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13561, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15609)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15609, 704}, +/*h(4663)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4663, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(761)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2809)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8953)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9077_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11001)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {11001, 704}, +/*h(55)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {55, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6639_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2103)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2103, 707}, +/*h(13049)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13049, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4201_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4151)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4151, 707}, +/*h(15097)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {15097, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1785)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3833)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7929)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9977)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7858_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1079)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1079, 707}, +/*h(12025)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12025, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5420_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14073)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14073, 704}, +/*h(3127)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3127, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2982_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5175)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5175, 707}, +/*h(16121)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16121, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4947_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1017)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1017, 704}, +/*h(11963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11963, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2509_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3065)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3065, 704}, +/*h(14011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14011, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16059)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {16059, 706}, +/*h(5113)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {5113, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6785_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7161)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9209)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11257)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13305)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15353)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3728_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12987, 706}, +/*h(2041)=1 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2041, 704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4089)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4089, 704}, +/*h(15035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15035, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6137)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8185)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10233)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12281)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14329)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16377)=0 0x0F 0x1E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5836_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7055_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15458)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14498)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13474)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15522)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5785_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8198)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10246)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7174)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13318)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15366)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6182)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14374)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7206)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9254)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13350)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15398)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6214; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8262)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10310)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6077_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12358)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12358; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14406)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14406; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7238)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9286)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11334)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11334; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13382)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13382; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15430)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6246)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8913_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4037_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12390)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14438)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9318)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11366)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13414)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15462)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2994_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2214, 705}, +/*h(8979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {8979, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6310)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6310, 705}, +/*h(13075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13075, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4832_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8358)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8358, 705}, +/*h(15123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15123, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10406)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10406; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12454)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14502)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1775_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3238)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3238, 705}, +/*h(10003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {10003, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6051_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7334)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7334, 705}, +/*h(14099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14099, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3613_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9382)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9382, 705}, +/*h(16147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16147, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11430)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13478)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15526)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(198)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {198, 705}, +/*h(6963)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {6963, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2246)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2246, 705}, +/*h(9011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {9011, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7668_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4294, 705}, +/*h(11059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {11059, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6342, 705}, +/*h(13107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {13107, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2792_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8390)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8390, 705}, +/*h(15155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {15155, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10438)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5318)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7366)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9414)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {230, 705}, +/*h(6995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6995, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8066_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2278, 705}, +/*h(9043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {9043, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5628_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4326, 705}, +/*h(11091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11091, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6374)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6374, 705}, +/*h(13139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13139, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_752_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8422)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8422, 705}, +/*h(15187)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15187, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10470)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1254)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1254, 705}, +/*h(8019)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8019, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6847_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3302, 705}, +/*h(10067)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {10067, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4409_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5350)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5350, 705}, +/*h(12115)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12115, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7398)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7398, 705}, +/*h(14163)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14163, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9446)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9446, 705}, +/*h(16211)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16211, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(42)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 42; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3886_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6943_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(74)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 74; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2042_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14474)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7315_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2218, 705}, +/*h(8983)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {8983, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6314, 705}, +/*h(13079)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {13079, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8362, 705}, +/*h(15127)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {15127, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12458)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14506)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8534_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1194, 705}, +/*h(7959)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {7959, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6096_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3242, 705}, +/*h(10007)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {10007, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3658_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5290, 705}, +/*h(12055)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {12055, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7338, 705}, +/*h(14103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {14103, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9386, 705}, +/*h(16151)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {16151, 708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3058_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13482)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15530)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {202, 705}, +/*h(6967)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {6967, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2250, 705}, +/*h(9015)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {9015, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2837_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4298, 705}, +/*h(11063)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {11063, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6346, 705}, +/*h(13111)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {13111, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8394, 705}, +/*h(15159)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {15159, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {234, 705}, +/*h(6999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6999, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3235_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {2282, 705}, +/*h(9047)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {9047, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_797_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {4330, 705}, +/*h(11095)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11095, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7511_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {6378, 705}, +/*h(13143)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13143, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5073_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8426, 705}, +/*h(15191)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15191, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10474)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {1258, 705}, +/*h(8023)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8023, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2016_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {3306, 705}, +/*h(10071)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {10071, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8730_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {5354, 705}, +/*h(12119)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12119, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6292_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7402, 705}, +/*h(14167)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14167, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9450, 705}, +/*h(16215)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16215, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4778_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15395)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14403)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15427)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14435)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13411)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15459)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1558)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1558, 706}, +/*h(8323)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8323, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5770_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3606)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3606, 706}, +/*h(10371)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10371, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5654)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5654, 706}, +/*h(12419)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12419, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_894_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7702)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7702, 706}, +/*h(14467)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14467, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(534)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {534, 706}, +/*h(7299)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7299, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6989_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2582)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2582, 706}, +/*h(9347)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9347, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4551_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4630)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4630, 706}, +/*h(11395)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11395, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6678)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6678, 706}, +/*h(13443)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13443, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8726)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8726, 706}, +/*h(15491)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15491, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1590)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1590, 706}, +/*h(8355)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8355, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3730_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3638)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3638, 706}, +/*h(10403)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10403, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1292_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5686)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5686, 706}, +/*h(12451)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12451, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8006_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7734)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7734, 706}, +/*h(14499)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14499, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(566)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {566, 706}, +/*h(7331)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7331, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4949_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2614)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2614, 706}, +/*h(9379)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9379, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2511_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4662)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4662, 706}, +/*h(11427)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11427, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6710)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6710, 706}, +/*h(13475)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13475, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6787_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8758)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8758, 706}, +/*h(15523)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15523, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1622)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1622, 706}, +/*h(8387)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8387, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1690_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3670)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3670, 706}, +/*h(10435)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10435, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8404_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5718)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5718, 706}, +/*h(12483)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12483, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7766)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7766, 706}, +/*h(14531)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14531, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5347_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(598)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {598, 706}, +/*h(7363)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7363, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2909_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2646)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2646, 706}, +/*h(9411)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9411, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4694)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4694, 706}, +/*h(11459)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11459, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6742)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6742, 706}, +/*h(13507)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13507, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4747_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8790)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8790, 706}, +/*h(15555)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15555, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2088_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1654)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1654, 706}, +/*h(8419)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8419, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8802_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3702)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3702, 706}, +/*h(10467)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10467, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5750)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5750, 706}, +/*h(12515)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12515, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3307_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(630)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {630, 706}, +/*h(7395)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7395, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_869_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2678)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2678, 706}, +/*h(9443)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9443, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7583_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4726)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4726, 706}, +/*h(11491)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11491, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14343)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11271)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13319)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15367)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6183)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8231)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8231; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10279)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12327)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14375)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14375; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7207)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7207; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9255; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5840_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11303)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13351)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15399)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6215)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6215; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8263)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10311)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10311; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12359)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12359; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14407)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14407; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7239)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9287)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9287; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11335)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11335; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13383)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13383; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15431)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10343)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12391)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14439)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7271)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9319)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11367)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13415)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15463)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6279)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1562)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1562, 706}, +/*h(8327)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8327, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_939_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3610)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3610, 706}, +/*h(10375)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10375, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7653_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5658, 706}, +/*h(12423)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12423, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7706, 706}, +/*h(14471)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14471, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(538)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {538, 706}, +/*h(7303)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7303, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2586)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2586, 706}, +/*h(9351)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9351, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8872_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4634)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4634, 706}, +/*h(11399)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11399, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6682, 706}, +/*h(13447)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13447, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3996_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8730, 706}, +/*h(15495)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15495, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6311)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6311; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1337_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1594)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1594, 706}, +/*h(8359)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8359, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8051_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3642)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3642, 706}, +/*h(10407)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10407, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5613_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5690, 706}, +/*h(12455)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12455, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7738, 706}, +/*h(14503)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14503, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2556_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(570)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {570, 706}, +/*h(7335)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7335, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2618)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2618, 706}, +/*h(9383)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9383, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6832_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4666, 706}, +/*h(11431)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11431, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4394_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6714, 706}, +/*h(13479)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13479, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1956_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8762, 706}, +/*h(15527)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15527, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6343)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8449_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1626)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1626, 706}, +/*h(8391)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8391, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6011_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3674, 706}, +/*h(10439)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10439, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3573_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5722, 706}, +/*h(12487)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {12487, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1135_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7770, 706}, +/*h(14535)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {14535, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_516_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(602)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {602, 706}, +/*h(7367)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7367, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2650)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2650, 706}, +/*h(9415)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9415, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4792_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4698, 706}, +/*h(11463)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11463, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6746, 706}, +/*h(13511)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {13511, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9068_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8794, 706}, +/*h(15559)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {15559, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6375)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6375; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6409_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1658, 706}, +/*h(8423)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {8423, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3706, 706}, +/*h(10471)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10471, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7628_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(634)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {634, 706}, +/*h(7399)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {7399, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2682, 706}, +/*h(9447)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {9447, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2752_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4730, 706}, +/*h(11495)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {11495, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2091)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15403)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(75)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 75; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14411)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15435)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12395)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14443)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13419)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15467)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12427)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14475)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11403)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13451)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15499)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10411)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12459)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14507)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11435)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13483)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15531)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8395)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10443)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12491)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14539)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9419)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11467)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13515)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15563)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8427)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8291_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6294, 707}, +/*h(10475)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {10475, 705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7403)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9451)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] no_refining_prefix*/ {705} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(514)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2562)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4610)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4907_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1538)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3586)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5634)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(546)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2594)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4642)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1048_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1570)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3618)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4705_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(578)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2626)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_827_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1602)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3650)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(610)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1634)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(642)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1023_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4055_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(530)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2578)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4626)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1554)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3602)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5650)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(562)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2610)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4904_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1586)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3634)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3685_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(594)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2642)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1618)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(626)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1650)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4058_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5075_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3035_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1295_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(518)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {518, 706}, +/*h(7283)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7283, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8009_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2566)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2566, 706}, +/*h(9331)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9331, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5571_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4614)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4614, 706}, +/*h(11379)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11379, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6662)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6662, 706}, +/*h(13427)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13427, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_695_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8710)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8710, 706}, +/*h(15475)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15475, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10758)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1542)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1542, 706}, +/*h(8307)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8307, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6790_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3590)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3590, 706}, +/*h(10355)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10355, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5638)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5638, 706}, +/*h(12403)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12403, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7686)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7686, 706}, +/*h(14451)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14451, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9734)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8407_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(550)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {550, 706}, +/*h(7315)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7315, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5969_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2598)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2598, 706}, +/*h(9363)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9363, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4646)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4646, 706}, +/*h(11411)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11411, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6694)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6694, 706}, +/*h(13459)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13459, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7807_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8742)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8742, 706}, +/*h(15507)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15507, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10790)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1574)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1574, 706}, +/*h(8339)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8339, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3622)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3622, 706}, +/*h(10387)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10387, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5670)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5670, 706}, +/*h(12435)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12435, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9026_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7718)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7718, 706}, +/*h(14483)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14483, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9766)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(582)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {582, 706}, +/*h(7347)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7347, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3929_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2630)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2630, 706}, +/*h(9395)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9395, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1491_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4678)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4678, 706}, +/*h(11443)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11443, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6726)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6726, 706}, +/*h(13491)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13491, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5767_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8774)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8774, 706}, +/*h(15539)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15539, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5148_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1606)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1606, 706}, +/*h(8371)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8371, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3654)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3654, 706}, +/*h(10419)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10419, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5702)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5702, 706}, +/*h(12467)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12467, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6986_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7750)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7750, 706}, +/*h(14515)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14515, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9798)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(614)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {614, 706}, +/*h(7379)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7379, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1889_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2662)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2662, 706}, +/*h(9427)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9427, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8603_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4710)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4710, 706}, +/*h(11475)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11475, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6165_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6758)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6758, 706}, +/*h(13523)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13523, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3727_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8806)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8806, 706}, +/*h(15571)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15571, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10854)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1638)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1638, 706}, +/*h(8403)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8403, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_670_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3686)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3686, 706}, +/*h(10451)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10451, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7384_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5734)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5734, 706}, +/*h(12499)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12499, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4946_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7782)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7782, 706}, +/*h(14547)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14547, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9830)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(646)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2694)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4742)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6790)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8838)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1670)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3718)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5766)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7814)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9862)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(678)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6961_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2726)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4774)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10918; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1702)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3750)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5798)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7846)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9894)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(710)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4921_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2758)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4806)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1734)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3782)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5830)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(742)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2881_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2790)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4838)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1766)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3814)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5862)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10774)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9750)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10806)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9782)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10838)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9814)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6774)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7798)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9846)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(662)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2710)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4758)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6806)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8854)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10902)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1686)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3734)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5782)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1886_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7830)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9878)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(694)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2742)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4790)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6838)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10934)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1718)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3766)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5814)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7862)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9910)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(726)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2774)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1750)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3798)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5846)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(758)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2806)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4854)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1782)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3830)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5878)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5616_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(522)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {522, 706}, +/*h(7287)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7287, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2570)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2570, 706}, +/*h(9335)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9335, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_740_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4618)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4618, 706}, +/*h(11383)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11383, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6666, 706}, +/*h(13431)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13431, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5016_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8714, 706}, +/*h(15479)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15479, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1546)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1546, 706}, +/*h(8311)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8311, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1959_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3594)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3594, 706}, +/*h(10359)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10359, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5642)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5642, 706}, +/*h(12407)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12407, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6235_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7690, 706}, +/*h(14455)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14455, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(554)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {554, 706}, +/*h(7319)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7319, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2602)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2602, 706}, +/*h(9367)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9367, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7852_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4650)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4650, 706}, +/*h(11415)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11415, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5414_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6698, 706}, +/*h(13463)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13463, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2976_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8746, 706}, +/*h(15511)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15511, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1578)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1578, 706}, +/*h(8343)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8343, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3626)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3626, 706}, +/*h(10391)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10391, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6633_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5674, 706}, +/*h(12439)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12439, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7722, 706}, +/*h(14487)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14487, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1536_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(586)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {586, 706}, +/*h(7351)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7351, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2634)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2634, 706}, +/*h(9399)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9399, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5812_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4682, 706}, +/*h(11447)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11447, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6730, 706}, +/*h(13495)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13495, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_936_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8778, 706}, +/*h(15543)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15543, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1610)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1610, 706}, +/*h(8375)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8375, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7031_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3658)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3658, 706}, +/*h(10423)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10423, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5706, 706}, +/*h(12471)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12471, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7754, 706}, +/*h(14519)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14519, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8648_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(618)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {618, 706}, +/*h(7383)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7383, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {2666, 706}, +/*h(9431)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9431, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3772_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {4714, 706}, +/*h(11479)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {11479, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1334_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {6762, 706}, +/*h(13527)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {13527, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8048_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8810, 706}, +/*h(15575)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {15575, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7429_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1642)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {1642, 706}, +/*h(8407)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8407, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4991_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {3690, 706}, +/*h(10455)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {10455, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {5738, 706}, +/*h(12503)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {12503, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7786, 706}, +/*h(14551)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {14551, 707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(650)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3570_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1674)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(682)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1706)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6804_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8023_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7849_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7028_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(666)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2714)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1690)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3738)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(698)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2746)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1722)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1754)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(762)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6659)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2031_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1942)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {1942, 711}, +/*h(8707)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8707, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8745_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3990)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3990, 711}, +/*h(10755)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10755, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6307_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6038)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {6038, 711}, +/*h(12803)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12803, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3869_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8086)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {8086, 711}, +/*h(14851)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14851, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5635)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {918, 711}, +/*h(7683)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7683, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_812_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {2966, 711}, +/*h(9731)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9731, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7526_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {5014, 711}, +/*h(11779)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11779, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5088_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {7062, 711}, +/*h(13827)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13827, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2650_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9110)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {9110, 711}, +/*h(15875)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15875, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6691)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1974)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1974, 712}, +/*h(8739)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8739, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4022)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4022, 712}, +/*h(10787)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10787, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4267_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6070, 712}, +/*h(12835)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12835, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1829_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8118)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8118, 712}, +/*h(14883)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14883, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5667)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(950)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {950, 712}, +/*h(7715)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7715, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7924_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2998, 712}, +/*h(9763)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9763, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5486_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5046, 712}, +/*h(11811)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11811, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3048_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7094, 712}, +/*h(13859)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13859, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9142)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9142, 712}, +/*h(15907)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15907, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(579)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2627)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1603)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3651)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(675)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2723)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4771)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1699)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7077_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3747)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(707)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2755)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1731)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5037_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(739)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1778_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1763)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2997_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6675)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1011_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1958)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1958, 712}, +/*h(8723)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8723, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4006)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4006, 712}, +/*h(10771)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10771, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6054)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6054, 712}, +/*h(12819)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12819, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8102, 712}, +/*h(14867)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14867, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5651)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(934)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {934, 712}, +/*h(7699)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7699, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2982)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2982, 712}, +/*h(9747)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9747, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5030, 712}, +/*h(11795)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11795, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4068_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7078)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7078, 712}, +/*h(13843)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13843, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1630_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9126)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9126, 712}, +/*h(15891)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15891, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6707)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1990)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1990, 713}, +/*h(8755)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8755, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4038)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4038, 713}, +/*h(10803)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10803, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6086)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6086, 713}, +/*h(12851)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12851, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_809_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8134)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {8134, 713}, +/*h(14899)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14899, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5683)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {966, 713}, +/*h(7731)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7731, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6904_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3014, 713}, +/*h(9779)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9779, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5062, 713}, +/*h(11827)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11827, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2028_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7110)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7110, 713}, +/*h(13875)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13875, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(659)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2707)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4755)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8716_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1683)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8097_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3731)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(691)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2739)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1715)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6057_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3763)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(723)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2771)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1747)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_758_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4415_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6663)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {1946, 711}, +/*h(8711)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8711, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {3994, 711}, +/*h(10759)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10759, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1476_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {6042, 711}, +/*h(12807)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12807, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {8090, 711}, +/*h(14855)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14855, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5639)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7571_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {922, 711}, +/*h(7687)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7687, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {2970, 711}, +/*h(9735)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9735, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2695_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {5018, 711}, +/*h(11783)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11783, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {7066, 711}, +/*h(13831)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13831, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {9114, 711}, +/*h(15879)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15879, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6695)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1978, 712}, +/*h(8743)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8743, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4026, 712}, +/*h(10791)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10791, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8588_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6074, 712}, +/*h(12839)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12839, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8122, 712}, +/*h(14887)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14887, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5671)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {954, 712}, +/*h(7719)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7719, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {3002, 712}, +/*h(9767)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9767, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5050, 712}, +/*h(11815)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11815, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7369_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7098, 712}, +/*h(13863)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13863, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4931_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9146, 712}, +/*h(15911)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15911, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(583)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 583; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2631)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2631; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4679)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10823)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1607)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3655)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5703)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9799)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10855)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9831)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10887)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9863)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(679)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2727)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4775)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6823)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8871)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10919)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1703)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3751)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5799)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7847)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9895)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(711)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2759)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4807)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6855)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1735)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3783)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5831)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7879)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9927)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1823_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(743)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2791)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4839)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6887)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8935)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1767)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3815)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5863)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7911)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9959)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6679)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {1962, 712}, +/*h(8727)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8727, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2894_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {4010, 712}, +/*h(10775)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10775, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {6058, 712}, +/*h(12823)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12823, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {8106, 712}, +/*h(14871)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {14871, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5655)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6551_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {938, 712}, +/*h(7703)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7703, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {2986, 712}, +/*h(9751)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9751, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {5034, 712}, +/*h(11799)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11799, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8389_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {7082, 712}, +/*h(13847)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13847, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5951_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {9130, 712}, +/*h(15895)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {15895, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6711)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3292_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1994, 713}, +/*h(8759)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {8759, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {4042, 713}, +/*h(10807)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {10807, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7568_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {6090, 713}, +/*h(12855)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {12855, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5687)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4511_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {970, 713}, +/*h(7735)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {7735, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2073_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {3018, 713}, +/*h(9783)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {9783, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8787_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {5066, 713}, +/*h(11831)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {11831, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6349_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {7114, 713}, +/*h(13879)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {13879, 706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10839)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9815)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10871)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9847)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(663)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2711)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4759)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6807)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8855)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1687)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3735)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5783)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7831)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9879)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(695)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2743)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4791)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6839)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8887)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10935)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1719)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3767)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5815)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7863)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9911)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(727)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2775)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4823)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6871)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8919)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1751)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3799)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5847)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7895)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9943)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(759)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2807)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4855)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8951)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1783)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3831)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5879)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7927)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9975)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(523)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2571)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4619)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6667)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8715)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10763)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1547)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3595)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5643)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7691)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9739)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(555)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2603)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4651)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6699)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8747)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1579)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3627)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5675)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7723)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9771)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(587)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(683)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2731)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1707)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3755)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(715)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2763)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1739)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(747)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1771)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(539)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2587)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4635)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6683)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8731)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1563)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3611)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5659)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7707)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9755)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5996_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(571)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 571; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2619)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4667)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6715)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1595)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3643)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5691)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7739)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(667)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2715)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4763)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_873_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1691)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3739)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(699)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2747)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1723)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3771)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(731)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1755)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(763)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6962_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] f2_refining_prefix*/ {706} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4816_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6035_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3995_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14482)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13458)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15506)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14514)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13490)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15538)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7001_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10482)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5782_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9458)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6166)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4861_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8214; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10262)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12310)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14358)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14358; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7190)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9238)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11286)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13334)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13334; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15382)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15382; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6198)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2821_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8246)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7097_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14390)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11318)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13366)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15414)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5057_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12374)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14422)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7254)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11350)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13398)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15446)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6262)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14486)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15510)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(182)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {182, 707}, +/*h(6947)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {6947, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2230, 707}, +/*h(8995)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {8995, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4278, 707}, +/*h(11043)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {11043, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6326, 707}, +/*h(13091)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {13091, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3812_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8374)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8374, 707}, +/*h(15139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {15139, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10422)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12470)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14518)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1206)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3254)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7350)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9398)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11446)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13494)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15542)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2372_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {214, 707}, +/*h(6979)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6979, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9086_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2262)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2262, 707}, +/*h(9027)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {9027, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6648_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4310)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4310, 707}, +/*h(11075)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11075, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6358)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6358, 707}, +/*h(13123)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13123, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1772_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8406)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8406, 707}, +/*h(15171)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15171, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10454)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1238)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1238, 707}, +/*h(8003)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8003, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7867_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3286)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3286, 707}, +/*h(10051)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {10051, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5429_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5334)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5334, 707}, +/*h(12099)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12099, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2991_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7382)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7382, 707}, +/*h(14147)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14147, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9430)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9430, 707}, +/*h(16195)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16195, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(246)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {246, 707}, +/*h(7011)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {7011, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7046_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2294, 707}, +/*h(9059)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {9059, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4608_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4342, 707}, +/*h(11107)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11107, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6390)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6390, 707}, +/*h(13155)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13155, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8884_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8438)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8438, 707}, +/*h(15203)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15203, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10486)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1270, 707}, +/*h(8035)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {8035, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3318)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3318, 707}, +/*h(10083)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {10083, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3389_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5366)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5366, 707}, +/*h(12131)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12131, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_951_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7414)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7414, 707}, +/*h(14179)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14179, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7665_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9462)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9462, 707}, +/*h(16227)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16227, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(58)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 58; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(90)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 90; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2045_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3062_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14458)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15482)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14490)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15514)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8733_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {186, 707}, +/*h(6951)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {6951, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6295_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2234, 707}, +/*h(8999)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {8999, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3857_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4282, 707}, +/*h(11047)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {11047, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1419_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6330, 707}, +/*h(13095)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {13095, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8378, 707}, +/*h(15143)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {15143, 2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10426)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12474)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14522)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9402)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11450)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13498)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15546)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6693_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {218, 707}, +/*h(6983)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {6983, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4255_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2266, 707}, +/*h(9031)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {9031, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1817_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4314, 707}, +/*h(11079)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {11079, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6362, 707}, +/*h(13127)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {13127, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8410)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8410, 707}, +/*h(15175)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {15175, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10458)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5474_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1242, 707}, +/*h(8007)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {8007, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3036_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3290, 707}, +/*h(10055)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {10055, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_598_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5338, 707}, +/*h(12103)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {12103, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7386)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7386, 707}, +/*h(14151)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {14151, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9434)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9434, 707}, +/*h(16199)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {16199, 709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4653_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {250, 707}, +/*h(7015)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {7015, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {2298, 707}, +/*h(9063)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {9063, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8929_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {4346, 707}, +/*h(11111)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {11111, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6491_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6394)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {6394, 707}, +/*h(13159)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {13159, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4053_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8442)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {8442, 707}, +/*h(15207)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {15207, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10490)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {1274, 707}, +/*h(8039)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {8039, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_996_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {3322, 707}, +/*h(10087)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {10087, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {5370, 707}, +/*h(12135)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {12135, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7418)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {7418, 707}, +/*h(14183)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {14183, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2834_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9466)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {9466, 707}, +/*h(16231)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {16231, 710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3758_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6815_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15411)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3954_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14419)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13395)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15443)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10483)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10263)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12311)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12311; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14359)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14359; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11287)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11287; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13335)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13335; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15383)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15383; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6199)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12343)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14391)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7223)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7223; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9271)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11319)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13367)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15415)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6231)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6231; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8279)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10327)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12375)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12375; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14423)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7656_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7255; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9303)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2780_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11351)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13399)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15447)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6263)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6327)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6359)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6359; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10487)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(59)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 59; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14395)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1083)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15419)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(91)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 91; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14427)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13403)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15451)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12411)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14459)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8099_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_785_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13435)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15483)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4840_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10395)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12443)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14491)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11419)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13467)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15515)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10427)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12475)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14523)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9403)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11451)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13499)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15547)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5036_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8411)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10459)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12507)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14555)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3817_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7387)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9435)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11483)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13531)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15579)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10491)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9091_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[rrr] RM[nnn] osz_refining_prefix*/ {707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(770)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(786)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_995_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(774)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1798)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3846)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5894)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(790)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2838)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1814)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3862)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5910)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(778)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3943_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(794)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9037_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(771)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(787)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8935_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(775)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2823)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4871)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6919)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8967)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7716_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1799)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3847)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2840_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5895)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7943)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9991)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(791)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2839)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3039_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4887)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6935)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1815)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3863)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5911)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(779)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9995)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11035)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6760_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13083)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10011)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12059)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b000] RM[nnn] f3_refining_prefix*/ {708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7087_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {5954, 709}, +/*h(10135)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {10135, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5958)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {5958, 709}, +/*h(10139)=1 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {10139, 711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(854)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2902)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2454_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4950)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9046; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1878)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3926)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5974)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7949_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8022)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(842)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7912_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5959)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5975)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(843)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9035)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11083)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8011)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10059)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7003)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9051)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10075)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10075; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b010] RM[nnn] f3_refining_prefix*/ {709} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3827_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5046_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2918; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4966)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7014)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7014; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9062)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9062; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5091_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1894)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3942)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5990)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8038)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10086)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10086; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(886)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2934)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4982)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4982; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7030)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9078)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9078; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4071_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1910)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3958)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6006)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8054)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(890)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5954_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6026_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9075)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9075; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3588_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6003)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8051)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5991)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7031)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9079)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9079; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11127)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11127; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13175)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13175; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15223)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15223; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6007)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8055)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10103)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12151)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14199)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7019)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9067)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9067; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3479_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5995)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8043)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10091)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(891)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2939)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4987)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7954_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7035)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5516_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9083)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11131)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3963)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6011)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8059)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10107)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10107; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b011] RM[nnn] f3_refining_prefix*/ {710} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6862_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1938)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(902)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2950)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4998)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7046)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7046; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9094)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9094; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1926)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3974)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6022)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8070)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10118)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10134)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6772_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7043)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9091)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6019)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8067)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8067; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6035)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7047)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7047; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9095)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11143)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13191)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2013_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15239)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6023)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8071)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10119)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10119; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5670_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12167)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12167; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14215)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14215; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16263)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7063)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6039)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8087)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8087; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5003)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6934_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7051)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8772_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8075)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8075; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix*/ {711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7061_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4822_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_411_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10166)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10151)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10167)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10167; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10155)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix*/ {712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5040_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7058_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9158)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9158; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11206)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13254)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10182)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7126)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7126; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9174)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11222)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13270)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15318)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6102)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8150)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10198)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12246)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14294)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16342)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16342; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3034)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5082)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2010)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4058)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6106)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10179)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10195)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2962_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11207)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11207; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13255; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15303)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10183)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12231)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12231; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14279)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16327)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11223)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11223; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13271)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15319)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10199)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10199; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12247)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12247; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14295)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14295; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16343)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16343; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10203)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b000] f3_refining_prefix*/ {714} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b001] f3_refining_prefix*/ {715} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9202)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10226)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9190)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10214)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10214; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9206)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10230)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1871_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9194)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10218)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9210)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10211)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10227)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10215)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10215; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_967_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10231)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10231; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10219)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b100] f3_refining_prefix*/ {716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11234)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8075_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11250)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12274)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11238)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3045_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12262)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11254)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12278)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11242)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12266)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11258)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11235)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11251)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12275)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11239)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11239; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12263)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12263; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11255)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11255; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12279)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11243)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12267)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4069_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11259)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b101] f3_refining_prefix*/ {717} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13282)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13298)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14322)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13286)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14310)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13302)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13302; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14326)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13290)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14314)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13306)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13283)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13299)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14323)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13287)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13287; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14311)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14311; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13303)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13303; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14327)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14327; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13291)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14315)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14315; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13307)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix*/ {718} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15330)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3000_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15346)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16370)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15334)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15334; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16358)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16358; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7520_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15350)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16374)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15338)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16362)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15354)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16378)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15331)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8656_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15347)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16371)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15335)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15335; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16359)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16359; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15351)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16375)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16375; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15339)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16363)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15355)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15355; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16379)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix*/ {719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6038_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6130)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6118)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6134)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5114)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b010] f3_refining_prefix CET=0*/ {720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7138)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7154)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8178)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7142)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7921_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8166)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7158)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7158; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8182)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3090_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7162)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8186)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b111] RM[0b011] f3_refining_prefix CET=0*/ {721} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 8186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(802)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(818)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2612_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2866)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2866; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4914)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(806)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7953_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2854)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4902)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(822)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6933_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2870)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4918)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4918; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(810)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2858)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4906)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6954)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9002)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11050)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13098)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15146)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(826)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2874)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8816_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4922)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6378_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6970)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9018)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11066)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=0*/ {722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1834)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3882)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5930)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7978)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10026)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12074)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14122)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16170)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1850)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3898)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5946)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7994)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10042)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12090)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=0*/ {723} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(803)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(819)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2867)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4915)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(807)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2855)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4903)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(823)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2871)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4919)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(811)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8778_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2859)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4907)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6955)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9003)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11051)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13099)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15147)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(827)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7758_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2875)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 2875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4923)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 4923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6971)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 6971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9019)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 9019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11067)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 11067; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13115)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 13115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15163)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W0 CET=1*/ {2066} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 15163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1835)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3883)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5931)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7979)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10027)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12075)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12075; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14123)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16171)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1851)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 1851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3899)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 3899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5947)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 5947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7995)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 7995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10043)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 10043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12091)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 12091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14139)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 14139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16187)=0 0x0F 0x1E MOD[0b11] MOD=3 REG[0b001] RM[nnn] f3_refining_prefix W1 mode64 CET=1*/ {2067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = key - 16187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1e_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[9152] = { +/*h(10946)=0 */ {10946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_0_l1}, +/*h(15127)=1 */ {15127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5778)=3 */ {5778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3_l1}, +/*h(9959)=4 */ {9959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4_l1}, +/*h(3194)=5 */ {3194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5_l1}, +/*h(610)=6 */ {610, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6_l1}, +/*h(4791)=7 */ {4791, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13153)=9 */ {13153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9_l1}, +/*h(6388)=10 */ {6388, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_10_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7985)=12 */ {7985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_12_l1}, +/*h(12166)=13 */ {12166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_13_l1}, +/*h(16347)=14 */ {16347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_14_l1}, +/*h(2817)=15 */ {2817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_15_l1}, +/*h(6998)=16 */ {6998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_16_l1}, +/*h(11179)=17 */ {11179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_17_l1}, +/*h(15360)=18 */ {15360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_18_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6011)=21 */ {6011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_21_l1}, +/*h(10192)=22 */ {10192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_22_l1}, +/*h(14373)=23 */ {14373, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_23_l1}, +/*h(843)=24 */ {843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_24_l1}, +/*h(15970)=25 */ {15970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_25_l1}, +/*h(9205)=26 */ {9205, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_26_l1}, +/*h(13386)=27 */ {13386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_27_l1}, +/*h(10802)=28 */ {10802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_28_l1}, +/*h(14983)=29 */ {14983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_29_l1}, +/*h(8218)=30 */ {8218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_30_l1}, +/*h(5634)=31 */ {5634, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_31_l1}, +/*h(9815)=32 */ {9815, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_32_l1}, +/*h(3050)=33 */ {3050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_33_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11412)=35 */ {11412, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_35_l1}, +/*h(4647)=36 */ {4647, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13009)=38 */ {13009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_38_l1}, +/*h(10425)=39 */ {10425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7841)=41 */ {7841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_41_l1}, +/*h(12022)=42 */ {12022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_42_l1}, +/*h(16203)=43 */ {16203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_43_l1}, +/*h(2673)=44 */ {2673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_44_l1}, +/*h(6854)=45 */ {6854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_45_l1}, +/*h(11035)=46 */ {11035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_46_l1}, +/*h(15216)=47 */ {15216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_47_l1}, +/*h(1686)=48 */ {1686, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_48_l1}, +/*h(5867)=49 */ {5867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_49_l1}, +/*h(10048)=50 */ {10048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_50_l1}, +/*h(3283)=51 */ {3283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_51_l1}, +/*h(699)=52 */ {699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_52_l1}, +/*h(4880)=53 */ {4880, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_53_l1}, +/*h(9061)=54 */ {9061, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_54_l1}, +/*h(13242)=55 */ {13242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3893)=57 */ {3893, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_57_l1}, +/*h(8074)=58 */ {8074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_58_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2906)=61 */ {2906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_61_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11268)=63 */ {11268, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_63_l1}, +/*h(15449)=64 */ {15449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12865)=66 */ {12865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_66_l1}, +/*h(6100)=67 */ {6100, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_67_l1}, +/*h(10281)=68 */ {10281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_68_l1}, +/*h(7697)=69 */ {7697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_69_l1}, +/*h(11878)=70 */ {11878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_70_l1}, +/*h(16059)=71 */ {16059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6710)=73 */ {6710, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_73_l1}, +/*h(10891)=74 */ {10891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_74_l1}, +/*h(15072)=75 */ {15072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_75_l1}, +/*h(8307)=76 */ {8307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_76_l1}, +/*h(5723)=77 */ {5723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_77_l1}, +/*h(9904)=78 */ {9904, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_78_l1}, +/*h(3139)=79 */ {3139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_79_l1}, +/*h(7320)=80 */ {7320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_80_l1}, +/*h(555)=81 */ {555, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_81_l1}, +/*h(4736)=82 */ {4736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_82_l1}, +/*h(8917)=83 */ {8917, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_83_l1}, +/*h(13098)=84 */ {13098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_84_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3749)=86 */ {3749, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_86_l1}, +/*h(7930)=87 */ {7930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_87_l1}, +/*h(5346)=88 */ {5346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_88_l1}, +/*h(16292)=89 */ {16292, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_89_l1}, +/*h(2762)=90 */ {2762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_90_l1}, +/*h(178)=91 */ {178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_91_l1}, +/*h(11124)=92 */ {11124, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_92_l1}, +/*h(15305)=93 */ {15305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5956)=95 */ {5956, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_95_l1}, +/*h(10137)=96 */ {10137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_96_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(788)=98 */ {788, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_98_l1}, +/*h(4969)=99 */ {4969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_99_l1}, +/*h(15915)=100 */ {15915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_100_l1}, +/*h(13331)=101 */ {13331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_101_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8163)=104 */ {8163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_104_l1}, +/*h(12344)=105 */ {12344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2995)=107 */ {2995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_107_l1}, +/*h(13941)=108 */ {13941, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15538)=110 */ {15538, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_110_l1}, +/*h(8773)=111 */ {8773, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_111_l1}, +/*h(12954)=112 */ {12954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_112_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10370)=114 */ {10370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_114_l1}, +/*h(14551)=115 */ {14551, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_115_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5202)=117 */ {5202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_117_l1}, +/*h(2618)=118 */ {2618, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(34)=120 */ {34, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_120_l1}, +/*h(4215)=121 */ {4215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5812)=123 */ {5812, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_123_l1}, +/*h(9993)=124 */ {9993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_124_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7409)=126 */ {7409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_126_l1}, +/*h(644)=127 */ {644, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_127_l1}, +/*h(4825)=128 */ {4825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_128_l1}, +/*h(2241)=129 */ {2241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_129_l1}, +/*h(13187)=130 */ {13187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8019)=133 */ {8019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_133_l1}, +/*h(12200)=134 */ {12200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2851)=136 */ {2851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_136_l1}, +/*h(7032)=137 */ {7032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15394)=139 */ {15394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_139_l1}, +/*h(12810)=140 */ {12810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10226)=142 */ {10226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_142_l1}, +/*h(14407)=143 */ {14407, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_143_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5058)=145 */ {5058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_145_l1}, +/*h(9239)=146 */ {9239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4071)=149 */ {4071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_149_l1}, +/*h(15017)=150 */ {15017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_150_l1}, +/*h(12433)=151 */ {12433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_151_l1}, +/*h(5668)=152 */ {5668, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_152_l1}, +/*h(9849)=153 */ {9849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_153_l1}, +/*h(7265)=154 */ {7265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_154_l1}, +/*h(11446)=155 */ {11446, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_155_l1}, +/*h(4681)=156 */ {4681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13043)=158 */ {13043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_158_l1}, +/*h(6278)=159 */ {6278, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_159_l1}, +/*h(10459)=160 */ {10459, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_160_l1}, +/*h(7875)=161 */ {7875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_161_l1}, +/*h(1110)=162 */ {1110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_162_l1}, +/*h(5291)=163 */ {5291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_163_l1}, +/*h(2707)=164 */ {2707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_164_l1}, +/*h(6888)=165 */ {6888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_165_l1}, +/*h(123)=166 */ {123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_166_l1}, +/*h(15250)=167 */ {15250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_167_l1}, +/*h(1720)=168 */ {1720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10082)=170 */ {10082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_170_l1}, +/*h(14263)=171 */ {14263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_171_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4914)=174 */ {4914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_174_l1}, +/*h(9095)=175 */ {9095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3927)=178 */ {3927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12289)=180 */ {12289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7121)=183 */ {7121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_183_l1}, +/*h(11302)=184 */ {11302, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_184_l1}, +/*h(15483)=185 */ {15483, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_185_l1}, +/*h(12899)=186 */ {12899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_186_l1}, +/*h(6134)=187 */ {6134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_187_l1}, +/*h(10315)=188 */ {10315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_188_l1}, +/*h(14496)=189 */ {14496, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_189_l1}, +/*h(966)=190 */ {966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_190_l1}, +/*h(5147)=191 */ {5147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_191_l1}, +/*h(9328)=192 */ {9328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_192_l1}, +/*h(2563)=193 */ {2563, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_193_l1}, +/*h(6744)=194 */ {6744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_194_l1}, +/*h(4160)=195 */ {4160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_195_l1}, +/*h(15106)=196 */ {15106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_196_l1}, +/*h(12522)=197 */ {12522, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9938)=199 */ {9938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_199_l1}, +/*h(7354)=200 */ {7354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4770)=202 */ {4770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_202_l1}, +/*h(8951)=203 */ {8951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_203_l1}, +/*h(2186)=204 */ {2186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_204_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3783)=206 */ {3783, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12145)=208 */ {12145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_208_l1}, +/*h(16326)=209 */ {16326, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6977)=211 */ {6977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_211_l1}, +/*h(11158)=212 */ {11158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_212_l1}, +/*h(15339)=213 */ {15339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_213_l1}, +/*h(1809)=214 */ {1809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_214_l1}, +/*h(5990)=215 */ {5990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_215_l1}, +/*h(10171)=216 */ {10171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_216_l1}, +/*h(14352)=217 */ {14352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(822)=219 */ {822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_219_l1}, +/*h(5003)=220 */ {5003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_220_l1}, +/*h(9184)=221 */ {9184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_221_l1}, +/*h(13365)=222 */ {13365, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_222_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14962)=224 */ {14962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_224_l1}, +/*h(8197)=225 */ {8197, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_225_l1}, +/*h(12378)=226 */ {12378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_226_l1}, +/*h(9794)=227 */ {9794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_227_l1}, +/*h(13975)=228 */ {13975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_228_l1}, +/*h(7210)=229 */ {7210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_229_l1}, +/*h(4626)=230 */ {4626, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_230_l1}, +/*h(8807)=231 */ {8807, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_231_l1}, +/*h(2042)=232 */ {2042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10404)=234 */ {10404, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_234_l1}, +/*h(3639)=235 */ {3639, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12001)=237 */ {12001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_237_l1}, +/*h(9417)=238 */ {9417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6833)=240 */ {6833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_240_l1}, +/*h(11014)=241 */ {11014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_241_l1}, +/*h(15195)=242 */ {15195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_242_l1}, +/*h(1665)=243 */ {1665, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_243_l1}, +/*h(5846)=244 */ {5846, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_244_l1}, +/*h(10027)=245 */ {10027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_245_l1}, +/*h(14208)=246 */ {14208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_246_l1}, +/*h(678)=247 */ {678, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_247_l1}, +/*h(4859)=248 */ {4859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_248_l1}, +/*h(9040)=249 */ {9040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_249_l1}, +/*h(2275)=250 */ {2275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3872)=252 */ {3872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_252_l1}, +/*h(8053)=253 */ {8053, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_253_l1}, +/*h(12234)=254 */ {12234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_254_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2885)=256 */ {2885, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_256_l1}, +/*h(7066)=257 */ {7066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15428)=259 */ {15428, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_259_l1}, +/*h(1898)=260 */ {1898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_260_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10260)=262 */ {10260, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_262_l1}, +/*h(14441)=263 */ {14441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_263_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11857)=265 */ {11857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_265_l1}, +/*h(16038)=266 */ {16038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_266_l1}, +/*h(9273)=267 */ {9273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_267_l1}, +/*h(6689)=268 */ {6689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_268_l1}, +/*h(10870)=269 */ {10870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_269_l1}, +/*h(15051)=270 */ {15051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12467)=272 */ {12467, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_272_l1}, +/*h(9883)=273 */ {9883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_273_l1}, +/*h(14064)=274 */ {14064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_274_l1}, +/*h(534)=275 */ {534, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_275_l1}, +/*h(4715)=276 */ {4715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_276_l1}, +/*h(8896)=277 */ {8896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_277_l1}, +/*h(2131)=278 */ {2131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_278_l1}, +/*h(6312)=279 */ {6312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3728)=281 */ {3728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_281_l1}, +/*h(7909)=282 */ {7909, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_282_l1}, +/*h(12090)=283 */ {12090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2741)=285 */ {2741, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_285_l1}, +/*h(6922)=286 */ {6922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_286_l1}, +/*h(4338)=287 */ {4338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_287_l1}, +/*h(15284)=288 */ {15284, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_288_l1}, +/*h(1754)=289 */ {1754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_289_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10116)=291 */ {10116, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_291_l1}, +/*h(14297)=292 */ {14297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15894)=294 */ {15894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_294_l1}, +/*h(9129)=295 */ {9129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14907)=298 */ {14907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12323)=300 */ {12323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9739)=302 */ {9739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_302_l1}, +/*h(7155)=303 */ {7155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_303_l1}, +/*h(11336)=304 */ {11336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_304_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1987)=306 */ {1987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_306_l1}, +/*h(12933)=307 */ {12933, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_307_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14530)=309 */ {14530, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_309_l1}, +/*h(7765)=310 */ {7765, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_310_l1}, +/*h(11946)=311 */ {11946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_311_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9362)=313 */ {9362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_313_l1}, +/*h(6778)=314 */ {6778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_314_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4194)=316 */ {4194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_316_l1}, +/*h(8375)=317 */ {8375, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9972)=319 */ {9972, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_319_l1}, +/*h(3207)=320 */ {3207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4804)=322 */ {4804, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_322_l1}, +/*h(8985)=323 */ {8985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_323_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3817)=327 */ {3817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_327_l1}, +/*h(12179)=328 */ {12179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_328_l1}, +/*h(16360)=329 */ {16360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7011)=332 */ {7011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_332_l1}, +/*h(11192)=333 */ {11192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6024)=336 */ {6024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_336_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14386)=338 */ {14386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_338_l1}, +/*h(11802)=339 */ {11802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_339_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9218)=341 */ {9218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_341_l1}, +/*h(13399)=342 */ {13399, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4050)=344 */ {4050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_344_l1}, +/*h(8231)=345 */ {8231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3063)=348 */ {3063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_348_l1}, +/*h(14009)=349 */ {14009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_349_l1}, +/*h(11425)=350 */ {11425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_350_l1}, +/*h(15606)=351 */ {15606, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_351_l1}, +/*h(8841)=352 */ {8841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_352_l1}, +/*h(6257)=353 */ {6257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_353_l1}, +/*h(10438)=354 */ {10438, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_354_l1}, +/*h(3673)=355 */ {3673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_355_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12035)=357 */ {12035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_357_l1}, +/*h(5270)=358 */ {5270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_358_l1}, +/*h(9451)=359 */ {9451, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_359_l1}, +/*h(6867)=360 */ {6867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_360_l1}, +/*h(102)=361 */ {102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_361_l1}, +/*h(4283)=362 */ {4283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_362_l1}, +/*h(1699)=363 */ {1699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_363_l1}, +/*h(5880)=364 */ {5880, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14242)=366 */ {14242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_366_l1}, +/*h(712)=367 */ {712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_367_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9074)=369 */ {9074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_369_l1}, +/*h(13255)=370 */ {13255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3906)=373 */ {3906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_373_l1}, +/*h(8087)=374 */ {8087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2919)=377 */ {2919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11281)=379 */ {11281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_379_l1}, +/*h(15462)=380 */ {15462, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6113)=382 */ {6113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_382_l1}, +/*h(10294)=383 */ {10294, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_383_l1}, +/*h(14475)=384 */ {14475, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_384_l1}, +/*h(11891)=385 */ {11891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_385_l1}, +/*h(5126)=386 */ {5126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_386_l1}, +/*h(9307)=387 */ {9307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_387_l1}, +/*h(13488)=388 */ {13488, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_388_l1}, +/*h(6723)=389 */ {6723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_389_l1}, +/*h(4139)=390 */ {4139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_390_l1}, +/*h(8320)=391 */ {8320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_391_l1}, +/*h(1555)=392 */ {1555, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_392_l1}, +/*h(5736)=393 */ {5736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_393_l1}, +/*h(3152)=394 */ {3152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_394_l1}, +/*h(14098)=395 */ {14098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_395_l1}, +/*h(11514)=396 */ {11514, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_396_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8930)=398 */ {8930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_398_l1}, +/*h(13111)=399 */ {13111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3762)=401 */ {3762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_401_l1}, +/*h(7943)=402 */ {7943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_402_l1}, +/*h(1178)=403 */ {1178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_403_l1}, +/*h(16305)=404 */ {16305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_404_l1}, +/*h(2775)=405 */ {2775, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11137)=407 */ {11137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_407_l1}, +/*h(15318)=408 */ {15318, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_408_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5969)=410 */ {5969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_410_l1}, +/*h(10150)=411 */ {10150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_411_l1}, +/*h(14331)=412 */ {14331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_412_l1}, +/*h(801)=413 */ {801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_413_l1}, +/*h(4982)=414 */ {4982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_414_l1}, +/*h(9163)=415 */ {9163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_415_l1}, +/*h(13344)=416 */ {13344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_416_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10760)=418 */ {10760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_418_l1}, +/*h(3995)=419 */ {3995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_419_l1}, +/*h(12357)=420 */ {12357, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13954)=423 */ {13954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_423_l1}, +/*h(7189)=424 */ {7189, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_424_l1}, +/*h(11370)=425 */ {11370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_425_l1}, +/*h(8786)=426 */ {8786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_426_l1}, +/*h(12967)=427 */ {12967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_427_l1}, +/*h(6202)=428 */ {6202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_428_l1}, +/*h(3618)=429 */ {3618, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_429_l1}, +/*h(7799)=430 */ {7799, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_430_l1}, +/*h(1034)=431 */ {1034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_431_l1}, +/*h(16161)=432 */ {16161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_432_l1}, +/*h(9396)=433 */ {9396, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_433_l1}, +/*h(2631)=434 */ {2631, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_434_l1}, +/*h(10993)=435 */ {10993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_435_l1}, +/*h(15174)=436 */ {15174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_436_l1}, +/*h(8409)=437 */ {8409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5825)=439 */ {5825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_439_l1}, +/*h(10006)=440 */ {10006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_440_l1}, +/*h(14187)=441 */ {14187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_441_l1}, +/*h(657)=442 */ {657, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_442_l1}, +/*h(4838)=443 */ {4838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_443_l1}, +/*h(9019)=444 */ {9019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_444_l1}, +/*h(13200)=445 */ {13200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3851)=447 */ {3851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_447_l1}, +/*h(8032)=448 */ {8032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_448_l1}, +/*h(1267)=449 */ {1267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_449_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2864)=451 */ {2864, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_451_l1}, +/*h(7045)=452 */ {7045, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_452_l1}, +/*h(11226)=453 */ {11226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_453_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1877)=455 */ {1877, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_455_l1}, +/*h(6058)=456 */ {6058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14420)=458 */ {14420, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_458_l1}, +/*h(890)=459 */ {890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16017)=461 */ {16017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_461_l1}, +/*h(13433)=462 */ {13433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10849)=464 */ {10849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_464_l1}, +/*h(15030)=465 */ {15030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5681)=467 */ {5681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_467_l1}, +/*h(9862)=468 */ {9862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_468_l1}, +/*h(14043)=469 */ {14043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_469_l1}, +/*h(513)=470 */ {513, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_470_l1}, +/*h(4694)=471 */ {4694, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_471_l1}, +/*h(8875)=472 */ {8875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_472_l1}, +/*h(13056)=473 */ {13056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_473_l1}, +/*h(6291)=474 */ {6291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_474_l1}, +/*h(3707)=475 */ {3707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_475_l1}, +/*h(7888)=476 */ {7888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_476_l1}, +/*h(1123)=477 */ {1123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_477_l1}, +/*h(16250)=478 */ {16250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6901)=480 */ {6901, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_480_l1}, +/*h(11082)=481 */ {11082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1733)=484 */ {1733, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_484_l1}, +/*h(5914)=485 */ {5914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_485_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14276)=487 */ {14276, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_487_l1}, +/*h(746)=488 */ {746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_488_l1}, +/*h(15873)=489 */ {15873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_489_l1}, +/*h(9108)=490 */ {9108, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_490_l1}, +/*h(13289)=491 */ {13289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_491_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14886)=493 */ {14886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_493_l1}, +/*h(8121)=494 */ {8121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_494_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13899)=497 */ {13899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_497_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11315)=499 */ {11315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_499_l1}, +/*h(15496)=500 */ {15496, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_500_l1}, +/*h(8731)=501 */ {8731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_501_l1}, +/*h(6147)=502 */ {6147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_502_l1}, +/*h(10328)=503 */ {10328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_503_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(979)=505 */ {979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_505_l1}, +/*h(11925)=506 */ {11925, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_506_l1}, +/*h(16106)=507 */ {16106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_507_l1}, +/*h(13522)=508 */ {13522, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_508_l1}, +/*h(6757)=509 */ {6757, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_509_l1}, +/*h(10938)=510 */ {10938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_510_l1}, +/*h(8354)=511 */ {8354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_511_l1}, +/*h(12535)=512 */ {12535, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_512_l1}, +/*h(5770)=513 */ {5770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3186)=515 */ {3186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_515_l1}, +/*h(602)=516 */ {602, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_516_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8964)=518 */ {8964, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_518_l1}, +/*h(2199)=519 */ {2199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3796)=521 */ {3796, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_521_l1}, +/*h(7977)=522 */ {7977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16339)=524 */ {16339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_524_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2809)=526 */ {2809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_526_l1}, +/*h(11171)=527 */ {11171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_527_l1}, +/*h(15352)=528 */ {15352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6003)=531 */ {6003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_531_l1}, +/*h(10184)=532 */ {10184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_532_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(835)=534 */ {835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_534_l1}, +/*h(15962)=535 */ {15962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_535_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13378)=537 */ {13378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_537_l1}, +/*h(10794)=538 */ {10794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8210)=540 */ {8210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_540_l1}, +/*h(12391)=541 */ {12391, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_541_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3042)=543 */ {3042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_543_l1}, +/*h(7223)=544 */ {7223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_544_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15585)=546 */ {15585, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_546_l1}, +/*h(2055)=547 */ {2055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_547_l1}, +/*h(13001)=548 */ {13001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_548_l1}, +/*h(10417)=549 */ {10417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_549_l1}, +/*h(3652)=550 */ {3652, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_550_l1}, +/*h(7833)=551 */ {7833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_551_l1}, +/*h(5249)=552 */ {5249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_552_l1}, +/*h(16195)=553 */ {16195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_553_l1}, +/*h(2665)=554 */ {2665, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_554_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11027)=556 */ {11027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_556_l1}, +/*h(8443)=557 */ {8443, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_557_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5859)=559 */ {5859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_559_l1}, +/*h(10040)=560 */ {10040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_560_l1}, +/*h(3275)=561 */ {3275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_561_l1}, +/*h(691)=562 */ {691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_562_l1}, +/*h(4872)=563 */ {4872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_563_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13234)=565 */ {13234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8066)=568 */ {8066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_568_l1}, +/*h(12247)=569 */ {12247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2898)=571 */ {2898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_571_l1}, +/*h(7079)=572 */ {7079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_572_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15441)=574 */ {15441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1911)=576 */ {1911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10273)=578 */ {10273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_578_l1}, +/*h(14454)=579 */ {14454, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_579_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16051)=581 */ {16051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_581_l1}, +/*h(9286)=582 */ {9286, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_582_l1}, +/*h(13467)=583 */ {13467, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_583_l1}, +/*h(10883)=584 */ {10883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_584_l1}, +/*h(4118)=585 */ {4118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_585_l1}, +/*h(8299)=586 */ {8299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_586_l1}, +/*h(5715)=587 */ {5715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_587_l1}, +/*h(9896)=588 */ {9896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_588_l1}, +/*h(3131)=589 */ {3131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_589_l1}, +/*h(7312)=590 */ {7312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_590_l1}, +/*h(547)=591 */ {547, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_591_l1}, +/*h(4728)=592 */ {4728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_592_l1}, +/*h(2144)=593 */ {2144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_593_l1}, +/*h(13090)=594 */ {13090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7922)=597 */ {7922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_597_l1}, +/*h(12103)=598 */ {12103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2754)=600 */ {2754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_600_l1}, +/*h(6935)=601 */ {6935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_601_l1}, +/*h(170)=602 */ {170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_602_l1}, +/*h(15297)=603 */ {15297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_603_l1}, +/*h(1767)=604 */ {1767, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_604_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10129)=606 */ {10129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_606_l1}, +/*h(14310)=607 */ {14310, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_607_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4961)=609 */ {4961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_609_l1}, +/*h(9142)=610 */ {9142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_610_l1}, +/*h(13323)=611 */ {13323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_611_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3974)=613 */ {3974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_613_l1}, +/*h(8155)=614 */ {8155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_614_l1}, +/*h(12336)=615 */ {12336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2987)=617 */ {2987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_617_l1}, +/*h(7168)=618 */ {7168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_618_l1}, +/*h(11349)=619 */ {11349, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_619_l1}, +/*h(15530)=620 */ {15530, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_620_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12946)=622 */ {12946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_622_l1}, +/*h(6181)=623 */ {6181, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_623_l1}, +/*h(10362)=624 */ {10362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_624_l1}, +/*h(7778)=625 */ {7778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_625_l1}, +/*h(11959)=626 */ {11959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_626_l1}, +/*h(5194)=627 */ {5194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_627_l1}, +/*h(2610)=628 */ {2610, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_628_l1}, +/*h(6791)=629 */ {6791, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_629_l1}, +/*h(26)=630 */ {26, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_630_l1}, +/*h(15153)=631 */ {15153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_631_l1}, +/*h(1623)=632 */ {1623, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_632_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9985)=634 */ {9985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_634_l1}, +/*h(14166)=635 */ {14166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_635_l1}, +/*h(7401)=636 */ {7401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_636_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4817)=638 */ {4817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_638_l1}, +/*h(8998)=639 */ {8998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_639_l1}, +/*h(13179)=640 */ {13179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3830)=642 */ {3830, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_642_l1}, +/*h(8011)=643 */ {8011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_643_l1}, +/*h(12192)=644 */ {12192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_644_l1}, +/*h(16373)=645 */ {16373, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_645_l1}, +/*h(2843)=646 */ {2843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_646_l1}, +/*h(7024)=647 */ {7024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_647_l1}, +/*h(11205)=648 */ {11205, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_648_l1}, +/*h(15386)=649 */ {15386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_649_l1}, +/*h(12802)=650 */ {12802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_650_l1}, +/*h(6037)=651 */ {6037, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_651_l1}, +/*h(10218)=652 */ {10218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(869)=654 */ {869, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_654_l1}, +/*h(5050)=655 */ {5050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13412)=657 */ {13412, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15009)=660 */ {15009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_660_l1}, +/*h(12425)=661 */ {12425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9841)=663 */ {9841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_663_l1}, +/*h(14022)=664 */ {14022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_664_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4673)=666 */ {4673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_666_l1}, +/*h(8854)=667 */ {8854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_667_l1}, +/*h(13035)=668 */ {13035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_668_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10451)=670 */ {10451, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_670_l1}, +/*h(7867)=671 */ {7867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_671_l1}, +/*h(12048)=672 */ {12048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_672_l1}, +/*h(5283)=673 */ {5283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_673_l1}, +/*h(2699)=674 */ {2699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_674_l1}, +/*h(6880)=675 */ {6880, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_675_l1}, +/*h(115)=676 */ {115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_676_l1}, +/*h(15242)=677 */ {15242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_677_l1}, +/*h(1712)=678 */ {1712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_678_l1}, +/*h(5893)=679 */ {5893, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_679_l1}, +/*h(10074)=680 */ {10074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_680_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(725)=683 */ {725, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_683_l1}, +/*h(4906)=684 */ {4906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13268)=686 */ {13268, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14865)=688 */ {14865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_688_l1}, +/*h(8100)=689 */ {8100, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_689_l1}, +/*h(12281)=690 */ {12281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_690_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13878)=692 */ {13878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_692_l1}, +/*h(7113)=693 */ {7113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15475)=695 */ {15475, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_695_l1}, +/*h(12891)=696 */ {12891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_696_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10307)=698 */ {10307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_698_l1}, +/*h(14488)=699 */ {14488, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_699_l1}, +/*h(7723)=700 */ {7723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_700_l1}, +/*h(5139)=701 */ {5139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_701_l1}, +/*h(16085)=702 */ {16085, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_702_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6736)=704 */ {6736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_704_l1}, +/*h(10917)=705 */ {10917, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_705_l1}, +/*h(15098)=706 */ {15098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_706_l1}, +/*h(12514)=707 */ {12514, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_707_l1}, +/*h(5749)=708 */ {5749, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_708_l1}, +/*h(9930)=709 */ {9930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_709_l1}, +/*h(7346)=710 */ {7346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_710_l1}, +/*h(581)=711 */ {581, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_711_l1}, +/*h(4762)=712 */ {4762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_712_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2178)=714 */ {2178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_714_l1}, +/*h(6359)=715 */ {6359, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7956)=717 */ {7956, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_717_l1}, +/*h(1191)=718 */ {1191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_718_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2788)=720 */ {2788, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_720_l1}, +/*h(6969)=721 */ {6969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_721_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15331)=723 */ {15331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_723_l1}, +/*h(1801)=724 */ {1801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_724_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10163)=726 */ {10163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_726_l1}, +/*h(14344)=727 */ {14344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4995)=730 */ {4995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_730_l1}, +/*h(9176)=731 */ {9176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_731_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10773)=733 */ {10773, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_733_l1}, +/*h(14954)=734 */ {14954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_734_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12370)=736 */ {12370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_736_l1}, +/*h(9786)=737 */ {9786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_737_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7202)=739 */ {7202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_739_l1}, +/*h(11383)=740 */ {11383, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_740_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2034)=742 */ {2034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_742_l1}, +/*h(6215)=743 */ {6215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_743_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14577)=745 */ {14577, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_745_l1}, +/*h(1047)=746 */ {1047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_746_l1}, +/*h(11993)=747 */ {11993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_747_l1}, +/*h(9409)=748 */ {9409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_748_l1}, +/*h(2644)=749 */ {2644, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_749_l1}, +/*h(6825)=750 */ {6825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_750_l1}, +/*h(4241)=751 */ {4241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_751_l1}, +/*h(15187)=752 */ {15187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_752_l1}, +/*h(1657)=753 */ {1657, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_753_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3254)=755 */ {3254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_755_l1}, +/*h(14200)=756 */ {14200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4851)=758 */ {4851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_758_l1}, +/*h(9032)=759 */ {9032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_759_l1}, +/*h(2267)=760 */ {2267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_760_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3864)=762 */ {3864, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_762_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12226)=764 */ {12226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7058)=767 */ {7058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_767_l1}, +/*h(11239)=768 */ {11239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_768_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1890)=770 */ {1890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_770_l1}, +/*h(6071)=771 */ {6071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14433)=773 */ {14433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(903)=775 */ {903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_775_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9265)=777 */ {9265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_777_l1}, +/*h(13446)=778 */ {13446, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_778_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15043)=780 */ {15043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_780_l1}, +/*h(8278)=781 */ {8278, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_781_l1}, +/*h(12459)=782 */ {12459, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_782_l1}, +/*h(9875)=783 */ {9875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_783_l1}, +/*h(3110)=784 */ {3110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_784_l1}, +/*h(7291)=785 */ {7291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_785_l1}, +/*h(4707)=786 */ {4707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_786_l1}, +/*h(8888)=787 */ {8888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_787_l1}, +/*h(2123)=788 */ {2123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_788_l1}, +/*h(6304)=789 */ {6304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_789_l1}, +/*h(10485)=790 */ {10485, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_790_l1}, +/*h(3720)=791 */ {3720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_791_l1}, +/*h(1136)=792 */ {1136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_792_l1}, +/*h(5317)=793 */ {5317, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_793_l1}, +/*h(16263)=794 */ {16263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_794_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6914)=796 */ {6914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_796_l1}, +/*h(11095)=797 */ {11095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_797_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1746)=799 */ {1746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_799_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14289)=802 */ {14289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_802_l1}, +/*h(759)=803 */ {759, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9121)=805 */ {9121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_805_l1}, +/*h(13302)=806 */ {13302, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_806_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3953)=808 */ {3953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_808_l1}, +/*h(8134)=809 */ {8134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_809_l1}, +/*h(12315)=810 */ {12315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_810_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2966)=812 */ {2966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_812_l1}, +/*h(7147)=813 */ {7147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_813_l1}, +/*h(11328)=814 */ {11328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_814_l1}, +/*h(15509)=815 */ {15509, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_815_l1}, +/*h(1979)=816 */ {1979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_816_l1}, +/*h(6160)=817 */ {6160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_817_l1}, +/*h(10341)=818 */ {10341, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_818_l1}, +/*h(14522)=819 */ {14522, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_819_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11938)=821 */ {11938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_821_l1}, +/*h(16119)=822 */ {16119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_822_l1}, +/*h(9354)=823 */ {9354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_823_l1}, +/*h(6770)=824 */ {6770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_824_l1}, +/*h(10951)=825 */ {10951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_825_l1}, +/*h(4186)=826 */ {4186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_826_l1}, +/*h(1602)=827 */ {1602, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_827_l1}, +/*h(5783)=828 */ {5783, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_828_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14145)=830 */ {14145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_830_l1}, +/*h(615)=831 */ {615, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_831_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8977)=833 */ {8977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_833_l1}, +/*h(13158)=834 */ {13158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_834_l1}, +/*h(6393)=835 */ {6393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_835_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3809)=837 */ {3809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_837_l1}, +/*h(1225)=838 */ {1225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_838_l1}, +/*h(12171)=839 */ {12171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2822)=841 */ {2822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_841_l1}, +/*h(7003)=842 */ {7003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_842_l1}, +/*h(11184)=843 */ {11184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_843_l1}, +/*h(15365)=844 */ {15365, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_844_l1}, +/*h(1835)=845 */ {1835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_845_l1}, +/*h(6016)=846 */ {6016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_846_l1}, +/*h(10197)=847 */ {10197, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_847_l1}, +/*h(14378)=848 */ {14378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_848_l1}, +/*h(11794)=849 */ {11794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_849_l1}, +/*h(15975)=850 */ {15975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_850_l1}, +/*h(9210)=851 */ {9210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_851_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4042)=854 */ {4042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12404)=856 */ {12404, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_856_l1}, +/*h(5639)=857 */ {5639, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_857_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14001)=859 */ {14001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_859_l1}, +/*h(11417)=860 */ {11417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_860_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8833)=862 */ {8833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_862_l1}, +/*h(13014)=863 */ {13014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_863_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3665)=865 */ {3665, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_865_l1}, +/*h(7846)=866 */ {7846, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_866_l1}, +/*h(12027)=867 */ {12027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_867_l1}, +/*h(16208)=868 */ {16208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_868_l1}, +/*h(2678)=869 */ {2678, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_869_l1}, +/*h(6859)=870 */ {6859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_870_l1}, +/*h(11040)=871 */ {11040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_871_l1}, +/*h(4275)=872 */ {4275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_872_l1}, +/*h(1691)=873 */ {1691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_873_l1}, +/*h(5872)=874 */ {5872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_874_l1}, +/*h(10053)=875 */ {10053, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_875_l1}, +/*h(14234)=876 */ {14234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_876_l1}, +/*h(704)=877 */ {704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_877_l1}, +/*h(4885)=878 */ {4885, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_878_l1}, +/*h(9066)=879 */ {9066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_879_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3898)=883 */ {3898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_883_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12260)=885 */ {12260, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_885_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13857)=887 */ {13857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_887_l1}, +/*h(7092)=888 */ {7092, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_888_l1}, +/*h(11273)=889 */ {11273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_889_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12870)=891 */ {12870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_891_l1}, +/*h(6105)=892 */ {6105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_892_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7702)=894 */ {7702, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_894_l1}, +/*h(11883)=895 */ {11883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_895_l1}, +/*h(16064)=896 */ {16064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_896_l1}, +/*h(9299)=897 */ {9299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_897_l1}, +/*h(13480)=898 */ {13480, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_898_l1}, +/*h(6715)=899 */ {6715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_899_l1}, +/*h(4131)=900 */ {4131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_900_l1}, +/*h(8312)=901 */ {8312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_901_l1}, +/*h(1547)=902 */ {1547, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_902_l1}, +/*h(5728)=903 */ {5728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_903_l1}, +/*h(9909)=904 */ {9909, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_904_l1}, +/*h(14090)=905 */ {14090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_905_l1}, +/*h(11506)=906 */ {11506, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_906_l1}, +/*h(4741)=907 */ {4741, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_907_l1}, +/*h(8922)=908 */ {8922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_908_l1}, +/*h(6338)=909 */ {6338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_909_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3754)=911 */ {3754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_911_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1170)=913 */ {1170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_913_l1}, +/*h(5351)=914 */ {5351, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_914_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6948)=916 */ {6948, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_916_l1}, +/*h(183)=917 */ {183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_917_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1780)=919 */ {1780, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_919_l1}, +/*h(5961)=920 */ {5961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14323)=922 */ {14323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_922_l1}, +/*h(793)=923 */ {793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_923_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9155)=925 */ {9155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_925_l1}, +/*h(13336)=926 */ {13336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_926_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10752)=928 */ {10752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_928_l1}, +/*h(3987)=929 */ {3987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_929_l1}, +/*h(8168)=930 */ {8168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_930_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9765)=932 */ {9765, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_932_l1}, +/*h(13946)=933 */ {13946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_933_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11362)=935 */ {11362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_935_l1}, +/*h(15543)=936 */ {15543, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_936_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6194)=938 */ {6194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_938_l1}, +/*h(3610)=939 */ {3610, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_939_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1026)=941 */ {1026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_941_l1}, +/*h(5207)=942 */ {5207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_942_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(39)=945 */ {39, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_945_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8401)=947 */ {8401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_947_l1}, +/*h(1636)=948 */ {1636, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_948_l1}, +/*h(5817)=949 */ {5817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_949_l1}, +/*h(3233)=950 */ {3233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_950_l1}, +/*h(14179)=951 */ {14179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_951_l1}, +/*h(649)=952 */ {649, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_952_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9011)=954 */ {9011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_954_l1}, +/*h(13192)=955 */ {13192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_955_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3843)=957 */ {3843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_957_l1}, +/*h(8024)=958 */ {8024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_958_l1}, +/*h(1259)=959 */ {1259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_959_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2856)=961 */ {2856, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_961_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11218)=963 */ {11218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_963_l1}, +/*h(15399)=964 */ {15399, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_964_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6050)=966 */ {6050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_966_l1}, +/*h(10231)=967 */ {10231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_967_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(882)=969 */ {882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_969_l1}, +/*h(5063)=970 */ {5063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_970_l1}, +/*h(16009)=971 */ {16009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_971_l1}, +/*h(13425)=972 */ {13425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_972_l1}, +/*h(6660)=973 */ {6660, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_973_l1}, +/*h(10841)=974 */ {10841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_974_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12438)=976 */ {12438, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_976_l1}, +/*h(5673)=977 */ {5673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_977_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14035)=979 */ {14035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_979_l1}, +/*h(7270)=980 */ {7270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_980_l1}, +/*h(11451)=981 */ {11451, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_981_l1}, +/*h(8867)=982 */ {8867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_982_l1}, +/*h(2102)=983 */ {2102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_983_l1}, +/*h(6283)=984 */ {6283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_984_l1}, +/*h(3699)=985 */ {3699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_985_l1}, +/*h(7880)=986 */ {7880, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_986_l1}, +/*h(1115)=987 */ {1115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_987_l1}, +/*h(16242)=988 */ {16242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_988_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2712)=990 */ {2712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_990_l1}, +/*h(11074)=991 */ {11074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_991_l1}, +/*h(15255)=992 */ {15255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_992_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5906)=995 */ {5906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_995_l1}, +/*h(10087)=996 */ {10087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_996_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=998 */ {738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_998_l1}, +/*h(4919)=999 */ {4919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_999_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13281)=1001 */ {13281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1001_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8113)=1004 */ {8113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1004_l1}, +/*h(12294)=1005 */ {12294, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1005_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13891)=1007 */ {13891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1007_l1}, +/*h(7126)=1008 */ {7126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1008_l1}, +/*h(11307)=1009 */ {11307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1009_l1}, +/*h(15488)=1010 */ {15488, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1010_l1}, +/*h(1958)=1011 */ {1958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1011_l1}, +/*h(6139)=1012 */ {6139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1012_l1}, +/*h(10320)=1013 */ {10320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1013_l1}, +/*h(14501)=1014 */ {14501, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1014_l1}, +/*h(971)=1015 */ {971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1015_l1}, +/*h(5152)=1016 */ {5152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1016_l1}, +/*h(16098)=1017 */ {16098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1017_l1}, +/*h(13514)=1018 */ {13514, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1018_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10930)=1020 */ {10930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1020_l1}, +/*h(15111)=1021 */ {15111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5762)=1023 */ {5762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1023_l1}, +/*h(9943)=1024 */ {9943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1024_l1}, +/*h(3178)=1025 */ {3178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1025_l1}, +/*h(594)=1026 */ {594, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1026_l1}, +/*h(4775)=1027 */ {4775, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13137)=1029 */ {13137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1029_l1}, +/*h(6372)=1030 */ {6372, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1030_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7969)=1032 */ {7969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1032_l1}, +/*h(12150)=1033 */ {12150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1033_l1}, +/*h(16331)=1034 */ {16331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1034_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2801)=1036 */ {2801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1036_l1}, +/*h(11163)=1037 */ {11163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1037_l1}, +/*h(15344)=1038 */ {15344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1038_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1814)=1040 */ {1814, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1040_l1}, +/*h(5995)=1041 */ {5995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1041_l1}, +/*h(10176)=1042 */ {10176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1042_l1}, +/*h(14357)=1043 */ {14357, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1043_l1}, +/*h(827)=1044 */ {827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1044_l1}, +/*h(15954)=1045 */ {15954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1045_l1}, +/*h(9189)=1046 */ {9189, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1046_l1}, +/*h(13370)=1047 */ {13370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1047_l1}, +/*h(10786)=1048 */ {10786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1048_l1}, +/*h(14967)=1049 */ {14967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1049_l1}, +/*h(8202)=1050 */ {8202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1050_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9799)=1052 */ {9799, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1052_l1}, +/*h(3034)=1053 */ {3034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1053_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11396)=1055 */ {11396, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1055_l1}, +/*h(4631)=1056 */ {4631, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1056_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12993)=1058 */ {12993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1058_l1}, +/*h(10409)=1059 */ {10409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1059_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7825)=1061 */ {7825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1061_l1}, +/*h(12006)=1062 */ {12006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1062_l1}, +/*h(16187)=1063 */ {16187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1063_l1}, +/*h(2657)=1064 */ {2657, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1064_l1}, +/*h(6838)=1065 */ {6838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1065_l1}, +/*h(11019)=1066 */ {11019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1066_l1}, +/*h(8435)=1067 */ {8435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1067_l1}, +/*h(1670)=1068 */ {1670, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1068_l1}, +/*h(5851)=1069 */ {5851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1069_l1}, +/*h(10032)=1070 */ {10032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1070_l1}, +/*h(3267)=1071 */ {3267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1071_l1}, +/*h(683)=1072 */ {683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1072_l1}, +/*h(4864)=1073 */ {4864, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1073_l1}, +/*h(9045)=1074 */ {9045, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1074_l1}, +/*h(13226)=1075 */ {13226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1075_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3877)=1077 */ {3877, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1077_l1}, +/*h(8058)=1078 */ {8058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1078_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2890)=1082 */ {2890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1082_l1}, +/*h(11252)=1083 */ {11252, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1083_l1}, +/*h(15433)=1084 */ {15433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1084_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12849)=1086 */ {12849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1086_l1}, +/*h(6084)=1087 */ {6084, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1087_l1}, +/*h(10265)=1088 */ {10265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1088_l1}, +/*h(7681)=1089 */ {7681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1089_l1}, +/*h(11862)=1090 */ {11862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1090_l1}, +/*h(16043)=1091 */ {16043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1091_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13459)=1093 */ {13459, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1093_l1}, +/*h(10875)=1094 */ {10875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1094_l1}, +/*h(15056)=1095 */ {15056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1095_l1}, +/*h(8291)=1096 */ {8291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1096_l1}, +/*h(5707)=1097 */ {5707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1097_l1}, +/*h(9888)=1098 */ {9888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1098_l1}, +/*h(3123)=1099 */ {3123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1099_l1}, +/*h(7304)=1100 */ {7304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1100_l1}, +/*h(539)=1101 */ {539, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1101_l1}, +/*h(4720)=1102 */ {4720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1102_l1}, +/*h(8901)=1103 */ {8901, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1103_l1}, +/*h(13082)=1104 */ {13082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1104_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3733)=1106 */ {3733, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1106_l1}, +/*h(7914)=1107 */ {7914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1107_l1}, +/*h(5330)=1108 */ {5330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1108_l1}, +/*h(16276)=1109 */ {16276, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1109_l1}, +/*h(2746)=1110 */ {2746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4343)=1112 */ {4343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1112_l1}, +/*h(15289)=1113 */ {15289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5940)=1115 */ {5940, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1115_l1}, +/*h(10121)=1116 */ {10121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(772)=1118 */ {772, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1118_l1}, +/*h(4953)=1119 */ {4953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1119_l1}, +/*h(15899)=1120 */ {15899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1120_l1}, +/*h(13315)=1121 */ {13315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8147)=1124 */ {8147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1124_l1}, +/*h(12328)=1125 */ {12328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9744)=1127 */ {9744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1127_l1}, +/*h(2979)=1128 */ {2979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15522)=1130 */ {15522, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1130_l1}, +/*h(8757)=1131 */ {8757, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1131_l1}, +/*h(12938)=1132 */ {12938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10354)=1134 */ {10354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1134_l1}, +/*h(7770)=1135 */ {7770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5186)=1137 */ {5186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1137_l1}, +/*h(9367)=1138 */ {9367, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(18)=1140 */ {18, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1140_l1}, +/*h(4199)=1141 */ {4199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5796)=1143 */ {5796, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1143_l1}, +/*h(9977)=1144 */ {9977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1144_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7393)=1146 */ {7393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1146_l1}, +/*h(628)=1147 */ {628, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1147_l1}, +/*h(4809)=1148 */ {4809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1148_l1}, +/*h(2225)=1149 */ {2225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1149_l1}, +/*h(13171)=1150 */ {13171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8003)=1153 */ {8003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1153_l1}, +/*h(12184)=1154 */ {12184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2835)=1156 */ {2835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1156_l1}, +/*h(7016)=1157 */ {7016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1157_l1}, +/*h(251)=1158 */ {251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1158_l1}, +/*h(15378)=1159 */ {15378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1159_l1}, +/*h(1848)=1160 */ {1848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10210)=1162 */ {10210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1162_l1}, +/*h(14391)=1163 */ {14391, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5042)=1165 */ {5042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1165_l1}, +/*h(9223)=1166 */ {9223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4055)=1169 */ {4055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1169_l1}, +/*h(15001)=1170 */ {15001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1170_l1}, +/*h(12417)=1171 */ {12417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1171_l1}, +/*h(5652)=1172 */ {5652, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1172_l1}, +/*h(9833)=1173 */ {9833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1173_l1}, +/*h(7249)=1174 */ {7249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1174_l1}, +/*h(11430)=1175 */ {11430, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1175_l1}, +/*h(15611)=1176 */ {15611, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13027)=1178 */ {13027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1178_l1}, +/*h(6262)=1179 */ {6262, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1179_l1}, +/*h(10443)=1180 */ {10443, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1180_l1}, +/*h(7859)=1181 */ {7859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1181_l1}, +/*h(1094)=1182 */ {1094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1182_l1}, +/*h(5275)=1183 */ {5275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1183_l1}, +/*h(2691)=1184 */ {2691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1184_l1}, +/*h(6872)=1185 */ {6872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1185_l1}, +/*h(107)=1186 */ {107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1186_l1}, +/*h(15234)=1187 */ {15234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1187_l1}, +/*h(1704)=1188 */ {1704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10066)=1190 */ {10066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1190_l1}, +/*h(14247)=1191 */ {14247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4898)=1194 */ {4898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1194_l1}, +/*h(9079)=1195 */ {9079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3911)=1198 */ {3911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1198_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12273)=1200 */ {12273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7105)=1203 */ {7105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1203_l1}, +/*h(11286)=1204 */ {11286, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1204_l1}, +/*h(15467)=1205 */ {15467, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1205_l1}, +/*h(12883)=1206 */ {12883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1206_l1}, +/*h(6118)=1207 */ {6118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1207_l1}, +/*h(10299)=1208 */ {10299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1208_l1}, +/*h(14480)=1209 */ {14480, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1209_l1}, +/*h(950)=1210 */ {950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1210_l1}, +/*h(5131)=1211 */ {5131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1211_l1}, +/*h(9312)=1212 */ {9312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1212_l1}, +/*h(13493)=1213 */ {13493, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1213_l1}, +/*h(6728)=1214 */ {6728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1214_l1}, +/*h(4144)=1215 */ {4144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1215_l1}, +/*h(15090)=1216 */ {15090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1216_l1}, +/*h(12506)=1217 */ {12506, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9922)=1219 */ {9922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1219_l1}, +/*h(14103)=1220 */ {14103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4754)=1222 */ {4754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1222_l1}, +/*h(8935)=1223 */ {8935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1223_l1}, +/*h(2170)=1224 */ {2170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3767)=1226 */ {3767, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1226_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12129)=1228 */ {12129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1228_l1}, +/*h(16310)=1229 */ {16310, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1229_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6961)=1231 */ {6961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1231_l1}, +/*h(11142)=1232 */ {11142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1232_l1}, +/*h(15323)=1233 */ {15323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1233_l1}, +/*h(1793)=1234 */ {1793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1234_l1}, +/*h(5974)=1235 */ {5974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1235_l1}, +/*h(10155)=1236 */ {10155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1236_l1}, +/*h(14336)=1237 */ {14336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(806)=1239 */ {806, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1239_l1}, +/*h(4987)=1240 */ {4987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1240_l1}, +/*h(9168)=1241 */ {9168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1241_l1}, +/*h(13349)=1242 */ {13349, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1242_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14946)=1244 */ {14946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1244_l1}, +/*h(8181)=1245 */ {8181, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1245_l1}, +/*h(12362)=1246 */ {12362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1246_l1}, +/*h(9778)=1247 */ {9778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1247_l1}, +/*h(13959)=1248 */ {13959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1248_l1}, +/*h(7194)=1249 */ {7194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1249_l1}, +/*h(4610)=1250 */ {4610, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1250_l1}, +/*h(8791)=1251 */ {8791, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1251_l1}, +/*h(2026)=1252 */ {2026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10388)=1254 */ {10388, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1254_l1}, +/*h(3623)=1255 */ {3623, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1255_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11985)=1257 */ {11985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1257_l1}, +/*h(9401)=1258 */ {9401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6817)=1260 */ {6817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1260_l1}, +/*h(10998)=1261 */ {10998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1261_l1}, +/*h(15179)=1262 */ {15179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1262_l1}, +/*h(1649)=1263 */ {1649, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1263_l1}, +/*h(5830)=1264 */ {5830, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1264_l1}, +/*h(10011)=1265 */ {10011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1265_l1}, +/*h(14192)=1266 */ {14192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1266_l1}, +/*h(662)=1267 */ {662, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1267_l1}, +/*h(4843)=1268 */ {4843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1268_l1}, +/*h(9024)=1269 */ {9024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1269_l1}, +/*h(2259)=1270 */ {2259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3856)=1272 */ {3856, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1272_l1}, +/*h(8037)=1273 */ {8037, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1273_l1}, +/*h(12218)=1274 */ {12218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1274_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2869)=1276 */ {2869, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1276_l1}, +/*h(7050)=1277 */ {7050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1277_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15412)=1279 */ {15412, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1279_l1}, +/*h(1882)=1280 */ {1882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1280_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10244)=1282 */ {10244, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1282_l1}, +/*h(14425)=1283 */ {14425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11841)=1285 */ {11841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1285_l1}, +/*h(16022)=1286 */ {16022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1286_l1}, +/*h(9257)=1287 */ {9257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1287_l1}, +/*h(6673)=1288 */ {6673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1288_l1}, +/*h(10854)=1289 */ {10854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1289_l1}, +/*h(15035)=1290 */ {15035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5686)=1292 */ {5686, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1292_l1}, +/*h(9867)=1293 */ {9867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1293_l1}, +/*h(14048)=1294 */ {14048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1294_l1}, +/*h(7283)=1295 */ {7283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1295_l1}, +/*h(4699)=1296 */ {4699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1296_l1}, +/*h(8880)=1297 */ {8880, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1297_l1}, +/*h(2115)=1298 */ {2115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1298_l1}, +/*h(6296)=1299 */ {6296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1299_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3712)=1301 */ {3712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1301_l1}, +/*h(7893)=1302 */ {7893, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1302_l1}, +/*h(12074)=1303 */ {12074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2725)=1305 */ {2725, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1305_l1}, +/*h(6906)=1306 */ {6906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1306_l1}, +/*h(4322)=1307 */ {4322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1307_l1}, +/*h(15268)=1308 */ {15268, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1308_l1}, +/*h(1738)=1309 */ {1738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10100)=1311 */ {10100, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1311_l1}, +/*h(14281)=1312 */ {14281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15878)=1314 */ {15878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1314_l1}, +/*h(9113)=1315 */ {9113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3945)=1318 */ {3945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1318_l1}, +/*h(14891)=1319 */ {14891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1319_l1}, +/*h(12307)=1320 */ {12307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7139)=1323 */ {7139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1323_l1}, +/*h(11320)=1324 */ {11320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1324_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1971)=1326 */ {1971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1326_l1}, +/*h(12917)=1327 */ {12917, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14514)=1329 */ {14514, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1329_l1}, +/*h(7749)=1330 */ {7749, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1330_l1}, +/*h(11930)=1331 */ {11930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1331_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9346)=1333 */ {9346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1333_l1}, +/*h(13527)=1334 */ {13527, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1334_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4178)=1336 */ {4178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1336_l1}, +/*h(1594)=1337 */ {1594, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1337_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9956)=1339 */ {9956, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1339_l1}, +/*h(3191)=1340 */ {3191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4788)=1342 */ {4788, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1342_l1}, +/*h(8969)=1343 */ {8969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6385)=1345 */ {6385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3801)=1347 */ {3801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1347_l1}, +/*h(1217)=1348 */ {1217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1348_l1}, +/*h(12163)=1349 */ {12163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1349_l1}, +/*h(16344)=1350 */ {16344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1350_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6995)=1352 */ {6995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1352_l1}, +/*h(11176)=1353 */ {11176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1353_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6008)=1356 */ {6008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14370)=1358 */ {14370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1358_l1}, +/*h(11786)=1359 */ {11786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9202)=1361 */ {9202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1361_l1}, +/*h(13383)=1362 */ {13383, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1362_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4034)=1364 */ {4034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1364_l1}, +/*h(8215)=1365 */ {8215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1365_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3047)=1368 */ {3047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1368_l1}, +/*h(13993)=1369 */ {13993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1369_l1}, +/*h(11409)=1370 */ {11409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1370_l1}, +/*h(15590)=1371 */ {15590, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1371_l1}, +/*h(8825)=1372 */ {8825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1372_l1}, +/*h(6241)=1373 */ {6241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1373_l1}, +/*h(10422)=1374 */ {10422, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1374_l1}, +/*h(3657)=1375 */ {3657, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1375_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12019)=1377 */ {12019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1377_l1}, +/*h(5254)=1378 */ {5254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1378_l1}, +/*h(9435)=1379 */ {9435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1379_l1}, +/*h(6851)=1380 */ {6851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1380_l1}, +/*h(86)=1381 */ {86, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1381_l1}, +/*h(4267)=1382 */ {4267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1382_l1}, +/*h(1683)=1383 */ {1683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1383_l1}, +/*h(5864)=1384 */ {5864, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14226)=1386 */ {14226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1386_l1}, +/*h(696)=1387 */ {696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9058)=1389 */ {9058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1389_l1}, +/*h(13239)=1390 */ {13239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8071)=1394 */ {8071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2903)=1397 */ {2903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11265)=1399 */ {11265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1399_l1}, +/*h(15446)=1400 */ {15446, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6097)=1402 */ {6097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1402_l1}, +/*h(10278)=1403 */ {10278, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1403_l1}, +/*h(14459)=1404 */ {14459, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1404_l1}, +/*h(11875)=1405 */ {11875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1405_l1}, +/*h(5110)=1406 */ {5110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1406_l1}, +/*h(9291)=1407 */ {9291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1407_l1}, +/*h(13472)=1408 */ {13472, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1408_l1}, +/*h(6707)=1409 */ {6707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1409_l1}, +/*h(4123)=1410 */ {4123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1410_l1}, +/*h(8304)=1411 */ {8304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1411_l1}, +/*h(1539)=1412 */ {1539, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1412_l1}, +/*h(5720)=1413 */ {5720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1413_l1}, +/*h(3136)=1414 */ {3136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1414_l1}, +/*h(14082)=1415 */ {14082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1415_l1}, +/*h(11498)=1416 */ {11498, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1416_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8914)=1418 */ {8914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1418_l1}, +/*h(13095)=1419 */ {13095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3746)=1421 */ {3746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1421_l1}, +/*h(7927)=1422 */ {7927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1422_l1}, +/*h(1162)=1423 */ {1162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1423_l1}, +/*h(16289)=1424 */ {16289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1424_l1}, +/*h(2759)=1425 */ {2759, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11121)=1427 */ {11121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1427_l1}, +/*h(15302)=1428 */ {15302, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1428_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5953)=1430 */ {5953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1430_l1}, +/*h(10134)=1431 */ {10134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1431_l1}, +/*h(14315)=1432 */ {14315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1432_l1}, +/*h(785)=1433 */ {785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1433_l1}, +/*h(4966)=1434 */ {4966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1434_l1}, +/*h(9147)=1435 */ {9147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1435_l1}, +/*h(13328)=1436 */ {13328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1436_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3979)=1439 */ {3979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1439_l1}, +/*h(8160)=1440 */ {8160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1440_l1}, +/*h(12341)=1441 */ {12341, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1441_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13938)=1443 */ {13938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1443_l1}, +/*h(7173)=1444 */ {7173, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1444_l1}, +/*h(11354)=1445 */ {11354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1445_l1}, +/*h(8770)=1446 */ {8770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1446_l1}, +/*h(12951)=1447 */ {12951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1447_l1}, +/*h(6186)=1448 */ {6186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1448_l1}, +/*h(3602)=1449 */ {3602, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1449_l1}, +/*h(7783)=1450 */ {7783, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1450_l1}, +/*h(1018)=1451 */ {1018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1451_l1}, +/*h(16145)=1452 */ {16145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1452_l1}, +/*h(9380)=1453 */ {9380, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1453_l1}, +/*h(2615)=1454 */ {2615, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15158)=1456 */ {15158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1456_l1}, +/*h(8393)=1457 */ {8393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1457_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5809)=1459 */ {5809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1459_l1}, +/*h(9990)=1460 */ {9990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1460_l1}, +/*h(14171)=1461 */ {14171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1461_l1}, +/*h(641)=1462 */ {641, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1462_l1}, +/*h(4822)=1463 */ {4822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1463_l1}, +/*h(9003)=1464 */ {9003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1464_l1}, +/*h(13184)=1465 */ {13184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3835)=1467 */ {3835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1467_l1}, +/*h(8016)=1468 */ {8016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1468_l1}, +/*h(1251)=1469 */ {1251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1469_l1}, +/*h(16378)=1470 */ {16378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1470_l1}, +/*h(2848)=1471 */ {2848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1471_l1}, +/*h(7029)=1472 */ {7029, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1472_l1}, +/*h(11210)=1473 */ {11210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1473_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1861)=1475 */ {1861, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1475_l1}, +/*h(6042)=1476 */ {6042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14404)=1478 */ {14404, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1478_l1}, +/*h(874)=1479 */ {874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1479_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16001)=1481 */ {16001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1481_l1}, +/*h(13417)=1482 */ {13417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1482_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10833)=1484 */ {10833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1484_l1}, +/*h(15014)=1485 */ {15014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1485_l1}, +/*h(8249)=1486 */ {8249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1486_l1}, +/*h(5665)=1487 */ {5665, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1487_l1}, +/*h(9846)=1488 */ {9846, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1488_l1}, +/*h(14027)=1489 */ {14027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1489_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11443)=1491 */ {11443, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1491_l1}, +/*h(8859)=1492 */ {8859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1492_l1}, +/*h(13040)=1493 */ {13040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1493_l1}, +/*h(6275)=1494 */ {6275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1494_l1}, +/*h(3691)=1495 */ {3691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1495_l1}, +/*h(7872)=1496 */ {7872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1496_l1}, +/*h(1107)=1497 */ {1107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1497_l1}, +/*h(16234)=1498 */ {16234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1498_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2704)=1500 */ {2704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1500_l1}, +/*h(6885)=1501 */ {6885, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1501_l1}, +/*h(11066)=1502 */ {11066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1717)=1504 */ {1717, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1504_l1}, +/*h(5898)=1505 */ {5898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1505_l1}, +/*h(3314)=1506 */ {3314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1506_l1}, +/*h(14260)=1507 */ {14260, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1507_l1}, +/*h(730)=1508 */ {730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9092)=1510 */ {9092, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1510_l1}, +/*h(13273)=1511 */ {13273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1511_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14870)=1513 */ {14870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1513_l1}, +/*h(8105)=1514 */ {8105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1514_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13883)=1517 */ {13883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11299)=1519 */ {11299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1519_l1}, +/*h(15480)=1520 */ {15480, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1520_l1}, +/*h(8715)=1521 */ {8715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1521_l1}, +/*h(6131)=1522 */ {6131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1522_l1}, +/*h(10312)=1523 */ {10312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1523_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(963)=1525 */ {963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1525_l1}, +/*h(11909)=1526 */ {11909, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1526_l1}, +/*h(16090)=1527 */ {16090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1527_l1}, +/*h(13506)=1528 */ {13506, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1528_l1}, +/*h(6741)=1529 */ {6741, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1529_l1}, +/*h(10922)=1530 */ {10922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1530_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8338)=1532 */ {8338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1532_l1}, +/*h(5754)=1533 */ {5754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1533_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3170)=1535 */ {3170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1535_l1}, +/*h(7351)=1536 */ {7351, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1536_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8948)=1538 */ {8948, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1538_l1}, +/*h(2183)=1539 */ {2183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1539_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3780)=1541 */ {3780, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1541_l1}, +/*h(7961)=1542 */ {7961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16323)=1544 */ {16323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1544_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2793)=1546 */ {2793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1546_l1}, +/*h(11155)=1547 */ {11155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1547_l1}, +/*h(15336)=1548 */ {15336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5987)=1551 */ {5987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1551_l1}, +/*h(10168)=1552 */ {10168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1552_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(819)=1554 */ {819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1554_l1}, +/*h(15946)=1555 */ {15946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1555_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13362)=1557 */ {13362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1557_l1}, +/*h(10778)=1558 */ {10778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8194)=1560 */ {8194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1560_l1}, +/*h(12375)=1561 */ {12375, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1561_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3026)=1563 */ {3026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1563_l1}, +/*h(7207)=1564 */ {7207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1564_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15569)=1566 */ {15569, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1566_l1}, +/*h(2039)=1567 */ {2039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1567_l1}, +/*h(12985)=1568 */ {12985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1568_l1}, +/*h(10401)=1569 */ {10401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1569_l1}, +/*h(14582)=1570 */ {14582, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1570_l1}, +/*h(7817)=1571 */ {7817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1571_l1}, +/*h(5233)=1572 */ {5233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1572_l1}, +/*h(9414)=1573 */ {9414, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1573_l1}, +/*h(2649)=1574 */ {2649, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11011)=1576 */ {11011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1576_l1}, +/*h(4246)=1577 */ {4246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1577_l1}, +/*h(8427)=1578 */ {8427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1578_l1}, +/*h(5843)=1579 */ {5843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1579_l1}, +/*h(10024)=1580 */ {10024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1580_l1}, +/*h(3259)=1581 */ {3259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1581_l1}, +/*h(675)=1582 */ {675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1582_l1}, +/*h(4856)=1583 */ {4856, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1583_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13218)=1585 */ {13218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1585_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8050)=1588 */ {8050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1588_l1}, +/*h(12231)=1589 */ {12231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1589_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2882)=1592 */ {2882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1592_l1}, +/*h(7063)=1593 */ {7063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1593_l1}, +/*h(15425)=1594 */ {15425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1895)=1596 */ {1895, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1596_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10257)=1598 */ {10257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1598_l1}, +/*h(14438)=1599 */ {14438, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1599_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16035)=1601 */ {16035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1601_l1}, +/*h(9270)=1602 */ {9270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1602_l1}, +/*h(13451)=1603 */ {13451, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1603_l1}, +/*h(10867)=1604 */ {10867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1604_l1}, +/*h(4102)=1605 */ {4102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1605_l1}, +/*h(8283)=1606 */ {8283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1606_l1}, +/*h(12464)=1607 */ {12464, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1607_l1}, +/*h(5699)=1608 */ {5699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1608_l1}, +/*h(3115)=1609 */ {3115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1609_l1}, +/*h(7296)=1610 */ {7296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1610_l1}, +/*h(531)=1611 */ {531, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1611_l1}, +/*h(4712)=1612 */ {4712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1612_l1}, +/*h(2128)=1613 */ {2128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1613_l1}, +/*h(13074)=1614 */ {13074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1614_l1}, +/*h(10490)=1615 */ {10490, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7906)=1617 */ {7906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1617_l1}, +/*h(5322)=1618 */ {5322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1618_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2738)=1620 */ {2738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1620_l1}, +/*h(6919)=1621 */ {6919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1621_l1}, +/*h(154)=1622 */ {154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1622_l1}, +/*h(15281)=1623 */ {15281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1623_l1}, +/*h(1751)=1624 */ {1751, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10113)=1626 */ {10113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1626_l1}, +/*h(14294)=1627 */ {14294, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1627_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4945)=1629 */ {4945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1629_l1}, +/*h(9126)=1630 */ {9126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1630_l1}, +/*h(13307)=1631 */ {13307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1631_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3958)=1633 */ {3958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1633_l1}, +/*h(8139)=1634 */ {8139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1634_l1}, +/*h(12320)=1635 */ {12320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1635_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9736)=1637 */ {9736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1637_l1}, +/*h(2971)=1638 */ {2971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1638_l1}, +/*h(11333)=1639 */ {11333, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1639_l1}, +/*h(15514)=1640 */ {15514, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12930)=1642 */ {12930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1642_l1}, +/*h(6165)=1643 */ {6165, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1643_l1}, +/*h(10346)=1644 */ {10346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1644_l1}, +/*h(7762)=1645 */ {7762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1645_l1}, +/*h(11943)=1646 */ {11943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1646_l1}, +/*h(5178)=1647 */ {5178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1647_l1}, +/*h(2594)=1648 */ {2594, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1648_l1}, +/*h(6775)=1649 */ {6775, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1649_l1}, +/*h(10)=1650 */ {10, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1650_l1}, +/*h(15137)=1651 */ {15137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1651_l1}, +/*h(8372)=1652 */ {8372, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1652_l1}, +/*h(1607)=1653 */ {1607, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1653_l1}, +/*h(9969)=1654 */ {9969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1654_l1}, +/*h(14150)=1655 */ {14150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1655_l1}, +/*h(7385)=1656 */ {7385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1656_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4801)=1658 */ {4801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1658_l1}, +/*h(8982)=1659 */ {8982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1659_l1}, +/*h(13163)=1660 */ {13163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1660_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3814)=1662 */ {3814, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1662_l1}, +/*h(7995)=1663 */ {7995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1663_l1}, +/*h(12176)=1664 */ {12176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1664_l1}, +/*h(16357)=1665 */ {16357, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1665_l1}, +/*h(2827)=1666 */ {2827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1666_l1}, +/*h(7008)=1667 */ {7008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1667_l1}, +/*h(243)=1668 */ {243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1668_l1}, +/*h(15370)=1669 */ {15370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1669_l1}, +/*h(1840)=1670 */ {1840, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1670_l1}, +/*h(6021)=1671 */ {6021, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1671_l1}, +/*h(10202)=1672 */ {10202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1672_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(853)=1674 */ {853, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1674_l1}, +/*h(5034)=1675 */ {5034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1675_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13396)=1677 */ {13396, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1677_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14993)=1680 */ {14993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1680_l1}, +/*h(12409)=1681 */ {12409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1681_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9825)=1683 */ {9825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1683_l1}, +/*h(14006)=1684 */ {14006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15603)=1686 */ {15603, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1686_l1}, +/*h(8838)=1687 */ {8838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1687_l1}, +/*h(13019)=1688 */ {13019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1688_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3670)=1690 */ {3670, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1690_l1}, +/*h(7851)=1691 */ {7851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1691_l1}, +/*h(12032)=1692 */ {12032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1692_l1}, +/*h(5267)=1693 */ {5267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1693_l1}, +/*h(2683)=1694 */ {2683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1694_l1}, +/*h(6864)=1695 */ {6864, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1695_l1}, +/*h(99)=1696 */ {99, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1696_l1}, +/*h(15226)=1697 */ {15226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1697_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5877)=1699 */ {5877, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1699_l1}, +/*h(10058)=1700 */ {10058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1700_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(709)=1703 */ {709, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1703_l1}, +/*h(4890)=1704 */ {4890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1704_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13252)=1706 */ {13252, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1706_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14849)=1708 */ {14849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1708_l1}, +/*h(8084)=1709 */ {8084, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1709_l1}, +/*h(12265)=1710 */ {12265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1710_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13862)=1712 */ {13862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1712_l1}, +/*h(7097)=1713 */ {7097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1713_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15459)=1715 */ {15459, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1715_l1}, +/*h(12875)=1716 */ {12875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1716_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10291)=1718 */ {10291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1718_l1}, +/*h(14472)=1719 */ {14472, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1719_l1}, +/*h(7707)=1720 */ {7707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1720_l1}, +/*h(5123)=1721 */ {5123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1721_l1}, +/*h(16069)=1722 */ {16069, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1722_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6720)=1724 */ {6720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1724_l1}, +/*h(10901)=1725 */ {10901, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1725_l1}, +/*h(15082)=1726 */ {15082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1726_l1}, +/*h(12498)=1727 */ {12498, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1727_l1}, +/*h(5733)=1728 */ {5733, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1728_l1}, +/*h(9914)=1729 */ {9914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1729_l1}, +/*h(7330)=1730 */ {7330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1730_l1}, +/*h(11511)=1731 */ {11511, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1731_l1}, +/*h(4746)=1732 */ {4746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1732_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2162)=1734 */ {2162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1734_l1}, +/*h(6343)=1735 */ {6343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7940)=1737 */ {7940, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1737_l1}, +/*h(1175)=1738 */ {1175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1738_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2772)=1740 */ {2772, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1740_l1}, +/*h(6953)=1741 */ {6953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1741_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15315)=1743 */ {15315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1743_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1785)=1745 */ {1785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1745_l1}, +/*h(10147)=1746 */ {10147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1746_l1}, +/*h(14328)=1747 */ {14328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4979)=1750 */ {4979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1750_l1}, +/*h(9160)=1751 */ {9160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1751_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10757)=1753 */ {10757, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1753_l1}, +/*h(14938)=1754 */ {14938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1754_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12354)=1756 */ {12354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1756_l1}, +/*h(9770)=1757 */ {9770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1757_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7186)=1759 */ {7186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1759_l1}, +/*h(11367)=1760 */ {11367, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1760_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2018)=1762 */ {2018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1762_l1}, +/*h(6199)=1763 */ {6199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1763_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14561)=1765 */ {14561, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1765_l1}, +/*h(1031)=1766 */ {1031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1766_l1}, +/*h(11977)=1767 */ {11977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1767_l1}, +/*h(9393)=1768 */ {9393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1768_l1}, +/*h(2628)=1769 */ {2628, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1769_l1}, +/*h(6809)=1770 */ {6809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1770_l1}, +/*h(4225)=1771 */ {4225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1771_l1}, +/*h(15171)=1772 */ {15171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1772_l1}, +/*h(1641)=1773 */ {1641, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10003)=1775 */ {10003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1775_l1}, +/*h(7419)=1776 */ {7419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1776_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4835)=1778 */ {4835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1778_l1}, +/*h(9016)=1779 */ {9016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1779_l1}, +/*h(2251)=1780 */ {2251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1780_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3848)=1782 */ {3848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1782_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12210)=1784 */ {12210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1784_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7042)=1787 */ {7042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1787_l1}, +/*h(11223)=1788 */ {11223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1874)=1790 */ {1874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1790_l1}, +/*h(6055)=1791 */ {6055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1791_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14417)=1793 */ {14417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1793_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(887)=1795 */ {887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1795_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9249)=1797 */ {9249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1797_l1}, +/*h(13430)=1798 */ {13430, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1798_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15027)=1800 */ {15027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1800_l1}, +/*h(8262)=1801 */ {8262, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1801_l1}, +/*h(12443)=1802 */ {12443, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1802_l1}, +/*h(9859)=1803 */ {9859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1803_l1}, +/*h(3094)=1804 */ {3094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1804_l1}, +/*h(7275)=1805 */ {7275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1805_l1}, +/*h(4691)=1806 */ {4691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1806_l1}, +/*h(8872)=1807 */ {8872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1807_l1}, +/*h(2107)=1808 */ {2107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1808_l1}, +/*h(6288)=1809 */ {6288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1809_l1}, +/*h(10469)=1810 */ {10469, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1810_l1}, +/*h(3704)=1811 */ {3704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1811_l1}, +/*h(1120)=1812 */ {1120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1812_l1}, +/*h(5301)=1813 */ {5301, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1813_l1}, +/*h(16247)=1814 */ {16247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1814_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6898)=1816 */ {6898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1816_l1}, +/*h(11079)=1817 */ {11079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1817_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1730)=1819 */ {1730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1819_l1}, +/*h(5911)=1820 */ {5911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14273)=1822 */ {14273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1822_l1}, +/*h(743)=1823 */ {743, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1823_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9105)=1825 */ {9105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1825_l1}, +/*h(13286)=1826 */ {13286, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1826_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3937)=1828 */ {3937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1828_l1}, +/*h(8118)=1829 */ {8118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1829_l1}, +/*h(12299)=1830 */ {12299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1830_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2950)=1832 */ {2950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1832_l1}, +/*h(7131)=1833 */ {7131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1833_l1}, +/*h(11312)=1834 */ {11312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1834_l1}, +/*h(15493)=1835 */ {15493, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1835_l1}, +/*h(1963)=1836 */ {1963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1836_l1}, +/*h(6144)=1837 */ {6144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1837_l1}, +/*h(10325)=1838 */ {10325, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1838_l1}, +/*h(14506)=1839 */ {14506, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11922)=1841 */ {11922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1841_l1}, +/*h(16103)=1842 */ {16103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1842_l1}, +/*h(9338)=1843 */ {9338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1843_l1}, +/*h(6754)=1844 */ {6754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1844_l1}, +/*h(10935)=1845 */ {10935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1845_l1}, +/*h(4170)=1846 */ {4170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1846_l1}, +/*h(1586)=1847 */ {1586, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1847_l1}, +/*h(5767)=1848 */ {5767, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1848_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14129)=1850 */ {14129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1850_l1}, +/*h(599)=1851 */ {599, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1851_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8961)=1853 */ {8961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1853_l1}, +/*h(13142)=1854 */ {13142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1854_l1}, +/*h(6377)=1855 */ {6377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1855_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3793)=1857 */ {3793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1857_l1}, +/*h(1209)=1858 */ {1209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1858_l1}, +/*h(12155)=1859 */ {12155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1859_l1}, +/*h(16336)=1860 */ {16336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1860_l1}, +/*h(2806)=1861 */ {2806, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1861_l1}, +/*h(6987)=1862 */ {6987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1862_l1}, +/*h(11168)=1863 */ {11168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1863_l1}, +/*h(15349)=1864 */ {15349, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1864_l1}, +/*h(1819)=1865 */ {1819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1865_l1}, +/*h(6000)=1866 */ {6000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1866_l1}, +/*h(10181)=1867 */ {10181, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1867_l1}, +/*h(14362)=1868 */ {14362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1868_l1}, +/*h(11778)=1869 */ {11778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1869_l1}, +/*h(15959)=1870 */ {15959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1870_l1}, +/*h(9194)=1871 */ {9194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1871_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4026)=1874 */ {4026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1874_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12388)=1876 */ {12388, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1876_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13985)=1879 */ {13985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1879_l1}, +/*h(11401)=1880 */ {11401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8817)=1882 */ {8817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1882_l1}, +/*h(12998)=1883 */ {12998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1883_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3649)=1885 */ {3649, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1885_l1}, +/*h(7830)=1886 */ {7830, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1886_l1}, +/*h(12011)=1887 */ {12011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1887_l1}, +/*h(16192)=1888 */ {16192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1888_l1}, +/*h(9427)=1889 */ {9427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1889_l1}, +/*h(6843)=1890 */ {6843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1890_l1}, +/*h(11024)=1891 */ {11024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1891_l1}, +/*h(4259)=1892 */ {4259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1892_l1}, +/*h(1675)=1893 */ {1675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1893_l1}, +/*h(5856)=1894 */ {5856, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1894_l1}, +/*h(10037)=1895 */ {10037, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1895_l1}, +/*h(14218)=1896 */ {14218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1896_l1}, +/*h(688)=1897 */ {688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1897_l1}, +/*h(4869)=1898 */ {4869, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1898_l1}, +/*h(9050)=1899 */ {9050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1899_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3882)=1903 */ {3882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12244)=1905 */ {12244, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1905_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13841)=1907 */ {13841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1907_l1}, +/*h(7076)=1908 */ {7076, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1908_l1}, +/*h(11257)=1909 */ {11257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1909_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12854)=1911 */ {12854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1911_l1}, +/*h(6089)=1912 */ {6089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1912_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14451)=1914 */ {14451, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1914_l1}, +/*h(11867)=1915 */ {11867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1915_l1}, +/*h(16048)=1916 */ {16048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1916_l1}, +/*h(9283)=1917 */ {9283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1917_l1}, +/*h(13464)=1918 */ {13464, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1918_l1}, +/*h(6699)=1919 */ {6699, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1919_l1}, +/*h(4115)=1920 */ {4115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1920_l1}, +/*h(15061)=1921 */ {15061, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1921_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5712)=1923 */ {5712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1923_l1}, +/*h(9893)=1924 */ {9893, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1924_l1}, +/*h(14074)=1925 */ {14074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1925_l1}, +/*h(11490)=1926 */ {11490, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1926_l1}, +/*h(4725)=1927 */ {4725, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1927_l1}, +/*h(8906)=1928 */ {8906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1928_l1}, +/*h(6322)=1929 */ {6322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1929_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3738)=1931 */ {3738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1931_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1154)=1933 */ {1154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1933_l1}, +/*h(5335)=1934 */ {5335, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1934_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6932)=1936 */ {6932, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1936_l1}, +/*h(167)=1937 */ {167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1937_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1764)=1939 */ {1764, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1939_l1}, +/*h(5945)=1940 */ {5945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1940_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14307)=1942 */ {14307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1942_l1}, +/*h(777)=1943 */ {777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1943_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9139)=1945 */ {9139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1945_l1}, +/*h(13320)=1946 */ {13320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1946_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3971)=1949 */ {3971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1949_l1}, +/*h(8152)=1950 */ {8152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1950_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9749)=1952 */ {9749, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1952_l1}, +/*h(13930)=1953 */ {13930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1953_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11346)=1955 */ {11346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1955_l1}, +/*h(8762)=1956 */ {8762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1956_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6178)=1958 */ {6178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1958_l1}, +/*h(10359)=1959 */ {10359, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1959_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=1961 */ {1010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1961_l1}, +/*h(5191)=1962 */ {5191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1962_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13553)=1964 */ {13553, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1964_l1}, +/*h(23)=1965 */ {23, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1965_l1}, +/*h(10969)=1966 */ {10969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1966_l1}, +/*h(8385)=1967 */ {8385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1967_l1}, +/*h(1620)=1968 */ {1620, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1968_l1}, +/*h(5801)=1969 */ {5801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1969_l1}, +/*h(3217)=1970 */ {3217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1970_l1}, +/*h(14163)=1971 */ {14163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1971_l1}, +/*h(633)=1972 */ {633, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1972_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8995)=1974 */ {8995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1974_l1}, +/*h(13176)=1975 */ {13176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1975_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3827)=1977 */ {3827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1977_l1}, +/*h(8008)=1978 */ {8008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1978_l1}, +/*h(1243)=1979 */ {1243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1979_l1}, +/*h(16370)=1980 */ {16370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1980_l1}, +/*h(2840)=1981 */ {2840, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1981_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11202)=1983 */ {11202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1983_l1}, +/*h(15383)=1984 */ {15383, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1984_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6034)=1986 */ {6034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1986_l1}, +/*h(10215)=1987 */ {10215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1987_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(866)=1989 */ {866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1989_l1}, +/*h(5047)=1990 */ {5047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1990_l1}, +/*h(15993)=1991 */ {15993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1991_l1}, +/*h(13409)=1992 */ {13409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1992_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10825)=1994 */ {10825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1994_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8241)=1996 */ {8241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1996_l1}, +/*h(12422)=1997 */ {12422, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1997_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14019)=1999 */ {14019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_1999_l1}, +/*h(7254)=2000 */ {7254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2000_l1}, +/*h(11435)=2001 */ {11435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2001_l1}, +/*h(8851)=2002 */ {8851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2002_l1}, +/*h(2086)=2003 */ {2086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2003_l1}, +/*h(6267)=2004 */ {6267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2004_l1}, +/*h(3683)=2005 */ {3683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2005_l1}, +/*h(7864)=2006 */ {7864, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2006_l1}, +/*h(1099)=2007 */ {1099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2007_l1}, +/*h(16226)=2008 */ {16226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2008_l1}, +/*h(9461)=2009 */ {9461, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2009_l1}, +/*h(2696)=2010 */ {2696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2010_l1}, +/*h(112)=2011 */ {112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2011_l1}, +/*h(11058)=2012 */ {11058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2012_l1}, +/*h(15239)=2013 */ {15239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2013_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5890)=2015 */ {5890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2015_l1}, +/*h(10071)=2016 */ {10071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2016_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(722)=2018 */ {722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2018_l1}, +/*h(4903)=2019 */ {4903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2019_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13265)=2021 */ {13265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8097)=2024 */ {8097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2024_l1}, +/*h(12278)=2025 */ {12278, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2929)=2027 */ {2929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2027_l1}, +/*h(7110)=2028 */ {7110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2028_l1}, +/*h(11291)=2029 */ {11291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2029_l1}, +/*h(15472)=2030 */ {15472, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2030_l1}, +/*h(1942)=2031 */ {1942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2031_l1}, +/*h(6123)=2032 */ {6123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2032_l1}, +/*h(10304)=2033 */ {10304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2033_l1}, +/*h(14485)=2034 */ {14485, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2034_l1}, +/*h(955)=2035 */ {955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2035_l1}, +/*h(5136)=2036 */ {5136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2036_l1}, +/*h(16082)=2037 */ {16082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2037_l1}, +/*h(13498)=2038 */ {13498, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2038_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10914)=2040 */ {10914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2040_l1}, +/*h(15095)=2041 */ {15095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2041_l1}, +/*h(8330)=2042 */ {8330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2042_l1}, +/*h(5746)=2043 */ {5746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2043_l1}, +/*h(9927)=2044 */ {9927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2044_l1}, +/*h(3162)=2045 */ {3162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2045_l1}, +/*h(578)=2046 */ {578, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2046_l1}, +/*h(4759)=2047 */ {4759, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13121)=2049 */ {13121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2049_l1}, +/*h(6356)=2050 */ {6356, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2050_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7953)=2052 */ {7953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2052_l1}, +/*h(12134)=2053 */ {12134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2053_l1}, +/*h(16315)=2054 */ {16315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2054_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2785)=2056 */ {2785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2056_l1}, +/*h(6966)=2057 */ {6966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2057_l1}, +/*h(11147)=2058 */ {11147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2058_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1798)=2060 */ {1798, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2060_l1}, +/*h(5979)=2061 */ {5979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2061_l1}, +/*h(10160)=2062 */ {10160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2062_l1}, +/*h(14341)=2063 */ {14341, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2063_l1}, +/*h(811)=2064 */ {811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2064_l1}, +/*h(15938)=2065 */ {15938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2065_l1}, +/*h(9173)=2066 */ {9173, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2066_l1}, +/*h(13354)=2067 */ {13354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2067_l1}, +/*h(10770)=2068 */ {10770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2068_l1}, +/*h(14951)=2069 */ {14951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2069_l1}, +/*h(8186)=2070 */ {8186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2070_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3018)=2073 */ {3018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2073_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11380)=2075 */ {11380, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2075_l1}, +/*h(4615)=2076 */ {4615, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2076_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12977)=2078 */ {12977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2078_l1}, +/*h(10393)=2079 */ {10393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2079_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7809)=2081 */ {7809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2081_l1}, +/*h(11990)=2082 */ {11990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2082_l1}, +/*h(16171)=2083 */ {16171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2083_l1}, +/*h(2641)=2084 */ {2641, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2084_l1}, +/*h(6822)=2085 */ {6822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2085_l1}, +/*h(11003)=2086 */ {11003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2086_l1}, +/*h(15184)=2087 */ {15184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2087_l1}, +/*h(1654)=2088 */ {1654, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2088_l1}, +/*h(5835)=2089 */ {5835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2089_l1}, +/*h(10016)=2090 */ {10016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2090_l1}, +/*h(3251)=2091 */ {3251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2091_l1}, +/*h(667)=2092 */ {667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2092_l1}, +/*h(4848)=2093 */ {4848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2093_l1}, +/*h(9029)=2094 */ {9029, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2094_l1}, +/*h(13210)=2095 */ {13210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2095_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3861)=2097 */ {3861, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2097_l1}, +/*h(8042)=2098 */ {8042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2098_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2874)=2102 */ {2874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15417)=2104 */ {15417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2104_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12833)=2106 */ {12833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2106_l1}, +/*h(6068)=2107 */ {6068, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2107_l1}, +/*h(10249)=2108 */ {10249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11846)=2110 */ {11846, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2110_l1}, +/*h(16027)=2111 */ {16027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6678)=2113 */ {6678, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2113_l1}, +/*h(10859)=2114 */ {10859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2114_l1}, +/*h(15040)=2115 */ {15040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2115_l1}, +/*h(8275)=2116 */ {8275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2116_l1}, +/*h(12456)=2117 */ {12456, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2117_l1}, +/*h(5691)=2118 */ {5691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2118_l1}, +/*h(3107)=2119 */ {3107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2119_l1}, +/*h(7288)=2120 */ {7288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2120_l1}, +/*h(523)=2121 */ {523, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2121_l1}, +/*h(4704)=2122 */ {4704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2122_l1}, +/*h(8885)=2123 */ {8885, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2123_l1}, +/*h(13066)=2124 */ {13066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2124_l1}, +/*h(10482)=2125 */ {10482, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2125_l1}, +/*h(3717)=2126 */ {3717, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2126_l1}, +/*h(7898)=2127 */ {7898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2127_l1}, +/*h(5314)=2128 */ {5314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2128_l1}, +/*h(16260)=2129 */ {16260, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2129_l1}, +/*h(2730)=2130 */ {2730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(146)=2132 */ {146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2132_l1}, +/*h(4327)=2133 */ {4327, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5924)=2135 */ {5924, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2135_l1}, +/*h(10105)=2136 */ {10105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2136_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(756)=2138 */ {756, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2138_l1}, +/*h(4937)=2139 */ {4937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2139_l1}, +/*h(15883)=2140 */ {15883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2140_l1}, +/*h(13299)=2141 */ {13299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8131)=2144 */ {8131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2144_l1}, +/*h(12312)=2145 */ {12312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9728)=2147 */ {9728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2147_l1}, +/*h(2963)=2148 */ {2963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2148_l1}, +/*h(7144)=2149 */ {7144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2149_l1}, +/*h(15506)=2150 */ {15506, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2150_l1}, +/*h(8741)=2151 */ {8741, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2151_l1}, +/*h(12922)=2152 */ {12922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10338)=2154 */ {10338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2154_l1}, +/*h(14519)=2155 */ {14519, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5170)=2157 */ {5170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2157_l1}, +/*h(2586)=2158 */ {2586, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2)=2160 */ {2, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2160_l1}, +/*h(4183)=2161 */ {4183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5780)=2164 */ {5780, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2164_l1}, +/*h(9961)=2165 */ {9961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2165_l1}, +/*h(7377)=2166 */ {7377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2166_l1}, +/*h(612)=2167 */ {612, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2167_l1}, +/*h(4793)=2168 */ {4793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2168_l1}, +/*h(2209)=2169 */ {2209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2169_l1}, +/*h(13155)=2170 */ {13155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1222)=2173 */ {1222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2173_l1}, +/*h(12168)=2174 */ {12168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2174_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2819)=2176 */ {2819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2176_l1}, +/*h(7000)=2177 */ {7000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2177_l1}, +/*h(235)=2178 */ {235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2178_l1}, +/*h(15362)=2179 */ {15362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2179_l1}, +/*h(1832)=2180 */ {1832, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10194)=2182 */ {10194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2182_l1}, +/*h(14375)=2183 */ {14375, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5026)=2185 */ {5026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2185_l1}, +/*h(9207)=2186 */ {9207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2186_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4039)=2189 */ {4039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2189_l1}, +/*h(14985)=2190 */ {14985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2190_l1}, +/*h(12401)=2191 */ {12401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2191_l1}, +/*h(5636)=2192 */ {5636, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2192_l1}, +/*h(9817)=2193 */ {9817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11414)=2195 */ {11414, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2195_l1}, +/*h(15595)=2196 */ {15595, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13011)=2198 */ {13011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2198_l1}, +/*h(6246)=2199 */ {6246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2199_l1}, +/*h(10427)=2200 */ {10427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2200_l1}, +/*h(7843)=2201 */ {7843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2201_l1}, +/*h(1078)=2202 */ {1078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2202_l1}, +/*h(5259)=2203 */ {5259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2203_l1}, +/*h(2675)=2204 */ {2675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2204_l1}, +/*h(6856)=2205 */ {6856, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2205_l1}, +/*h(91)=2206 */ {91, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2206_l1}, +/*h(15218)=2207 */ {15218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2207_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1688)=2209 */ {1688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2209_l1}, +/*h(10050)=2210 */ {10050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2210_l1}, +/*h(14231)=2211 */ {14231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2211_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4882)=2214 */ {4882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2214_l1}, +/*h(9063)=2215 */ {9063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12257)=2220 */ {12257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7089)=2223 */ {7089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2223_l1}, +/*h(11270)=2224 */ {11270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2224_l1}, +/*h(15451)=2225 */ {15451, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2225_l1}, +/*h(12867)=2226 */ {12867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2226_l1}, +/*h(6102)=2227 */ {6102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2227_l1}, +/*h(10283)=2228 */ {10283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2228_l1}, +/*h(14464)=2229 */ {14464, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2229_l1}, +/*h(934)=2230 */ {934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2230_l1}, +/*h(5115)=2231 */ {5115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2231_l1}, +/*h(9296)=2232 */ {9296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2232_l1}, +/*h(13477)=2233 */ {13477, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2233_l1}, +/*h(6712)=2234 */ {6712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2234_l1}, +/*h(4128)=2235 */ {4128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2235_l1}, +/*h(15074)=2236 */ {15074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2236_l1}, +/*h(12490)=2237 */ {12490, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9906)=2239 */ {9906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2239_l1}, +/*h(14087)=2240 */ {14087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2240_l1}, +/*h(7322)=2241 */ {7322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2241_l1}, +/*h(4738)=2242 */ {4738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2242_l1}, +/*h(8919)=2243 */ {8919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2243_l1}, +/*h(2154)=2244 */ {2154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3751)=2246 */ {3751, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2246_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12113)=2248 */ {12113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2248_l1}, +/*h(16294)=2249 */ {16294, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6945)=2251 */ {6945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2251_l1}, +/*h(11126)=2252 */ {11126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2252_l1}, +/*h(15307)=2253 */ {15307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1777)=2255 */ {1777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2255_l1}, +/*h(10139)=2256 */ {10139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2256_l1}, +/*h(14320)=2257 */ {14320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(790)=2259 */ {790, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2259_l1}, +/*h(4971)=2260 */ {4971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2260_l1}, +/*h(9152)=2261 */ {9152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2261_l1}, +/*h(13333)=2262 */ {13333, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2262_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14930)=2264 */ {14930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2264_l1}, +/*h(8165)=2265 */ {8165, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2265_l1}, +/*h(12346)=2266 */ {12346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2266_l1}, +/*h(9762)=2267 */ {9762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2267_l1}, +/*h(13943)=2268 */ {13943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2268_l1}, +/*h(7178)=2269 */ {7178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8775)=2271 */ {8775, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2271_l1}, +/*h(2010)=2272 */ {2010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2272_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10372)=2274 */ {10372, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2274_l1}, +/*h(3607)=2275 */ {3607, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2275_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11969)=2277 */ {11969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2277_l1}, +/*h(16150)=2278 */ {16150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2278_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6801)=2280 */ {6801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2280_l1}, +/*h(10982)=2281 */ {10982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2281_l1}, +/*h(15163)=2282 */ {15163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2282_l1}, +/*h(1633)=2283 */ {1633, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2283_l1}, +/*h(5814)=2284 */ {5814, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2284_l1}, +/*h(9995)=2285 */ {9995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2285_l1}, +/*h(7411)=2286 */ {7411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2286_l1}, +/*h(646)=2287 */ {646, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2287_l1}, +/*h(4827)=2288 */ {4827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2288_l1}, +/*h(9008)=2289 */ {9008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2289_l1}, +/*h(2243)=2290 */ {2243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3840)=2292 */ {3840, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2292_l1}, +/*h(8021)=2293 */ {8021, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2293_l1}, +/*h(12202)=2294 */ {12202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2853)=2296 */ {2853, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2296_l1}, +/*h(7034)=2297 */ {7034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2297_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15396)=2299 */ {15396, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2299_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1866)=2301 */ {1866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2301_l1}, +/*h(10228)=2302 */ {10228, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2302_l1}, +/*h(14409)=2303 */ {14409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11825)=2305 */ {11825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2305_l1}, +/*h(16006)=2306 */ {16006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2306_l1}, +/*h(9241)=2307 */ {9241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2307_l1}, +/*h(6657)=2308 */ {6657, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2308_l1}, +/*h(10838)=2309 */ {10838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2309_l1}, +/*h(15019)=2310 */ {15019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12435)=2312 */ {12435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2312_l1}, +/*h(9851)=2313 */ {9851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2313_l1}, +/*h(14032)=2314 */ {14032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2314_l1}, +/*h(7267)=2315 */ {7267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2315_l1}, +/*h(11448)=2316 */ {11448, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2316_l1}, +/*h(4683)=2317 */ {4683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2317_l1}, +/*h(2099)=2318 */ {2099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2318_l1}, +/*h(6280)=2319 */ {6280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2319_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3696)=2321 */ {3696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2321_l1}, +/*h(7877)=2322 */ {7877, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2322_l1}, +/*h(12058)=2323 */ {12058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2323_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2709)=2325 */ {2709, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2325_l1}, +/*h(6890)=2326 */ {6890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2326_l1}, +/*h(4306)=2327 */ {4306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2327_l1}, +/*h(15252)=2328 */ {15252, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2328_l1}, +/*h(1722)=2329 */ {1722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10084)=2331 */ {10084, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2331_l1}, +/*h(3319)=2332 */ {3319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4916)=2334 */ {4916, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2334_l1}, +/*h(9097)=2335 */ {9097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3929)=2338 */ {3929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2338_l1}, +/*h(14875)=2339 */ {14875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2339_l1}, +/*h(12291)=2340 */ {12291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7123)=2343 */ {7123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2343_l1}, +/*h(11304)=2344 */ {11304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2344_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8720)=2346 */ {8720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2346_l1}, +/*h(1955)=2347 */ {1955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14498)=2349 */ {14498, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2349_l1}, +/*h(7733)=2350 */ {7733, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2350_l1}, +/*h(11914)=2351 */ {11914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2351_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9330)=2353 */ {9330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2353_l1}, +/*h(6746)=2354 */ {6746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4162)=2356 */ {4162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2356_l1}, +/*h(8343)=2357 */ {8343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2357_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9940)=2359 */ {9940, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2359_l1}, +/*h(3175)=2360 */ {3175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2360_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4772)=2362 */ {4772, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2362_l1}, +/*h(8953)=2363 */ {8953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2363_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6369)=2365 */ {6369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2365_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3785)=2367 */ {3785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2367_l1}, +/*h(1201)=2368 */ {1201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2368_l1}, +/*h(12147)=2369 */ {12147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2369_l1}, +/*h(16328)=2370 */ {16328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6979)=2372 */ {6979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2372_l1}, +/*h(11160)=2373 */ {11160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2373_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1811)=2375 */ {1811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2375_l1}, +/*h(5992)=2376 */ {5992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14354)=2378 */ {14354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2378_l1}, +/*h(824)=2379 */ {824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2379_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9186)=2381 */ {9186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2381_l1}, +/*h(13367)=2382 */ {13367, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2382_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4018)=2384 */ {4018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2384_l1}, +/*h(8199)=2385 */ {8199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2385_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3031)=2388 */ {3031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2388_l1}, +/*h(13977)=2389 */ {13977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2389_l1}, +/*h(11393)=2390 */ {11393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2390_l1}, +/*h(15574)=2391 */ {15574, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2391_l1}, +/*h(8809)=2392 */ {8809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2392_l1}, +/*h(6225)=2393 */ {6225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2393_l1}, +/*h(10406)=2394 */ {10406, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2394_l1}, +/*h(14587)=2395 */ {14587, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12003)=2397 */ {12003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2397_l1}, +/*h(5238)=2398 */ {5238, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2398_l1}, +/*h(9419)=2399 */ {9419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2399_l1}, +/*h(6835)=2400 */ {6835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2400_l1}, +/*h(70)=2401 */ {70, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2401_l1}, +/*h(4251)=2402 */ {4251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2402_l1}, +/*h(1667)=2403 */ {1667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2403_l1}, +/*h(5848)=2404 */ {5848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2404_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14210)=2406 */ {14210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(680)=2408 */ {680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2408_l1}, +/*h(9042)=2409 */ {9042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2409_l1}, +/*h(13223)=2410 */ {13223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8055)=2414 */ {8055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2414_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2887)=2417 */ {2887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11249)=2419 */ {11249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2419_l1}, +/*h(15430)=2420 */ {15430, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6081)=2422 */ {6081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2422_l1}, +/*h(10262)=2423 */ {10262, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2423_l1}, +/*h(14443)=2424 */ {14443, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2424_l1}, +/*h(11859)=2425 */ {11859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2425_l1}, +/*h(5094)=2426 */ {5094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2426_l1}, +/*h(9275)=2427 */ {9275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2427_l1}, +/*h(13456)=2428 */ {13456, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2428_l1}, +/*h(6691)=2429 */ {6691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2429_l1}, +/*h(4107)=2430 */ {4107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2430_l1}, +/*h(8288)=2431 */ {8288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2431_l1}, +/*h(12469)=2432 */ {12469, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2432_l1}, +/*h(5704)=2433 */ {5704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2433_l1}, +/*h(3120)=2434 */ {3120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2434_l1}, +/*h(14066)=2435 */ {14066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2435_l1}, +/*h(11482)=2436 */ {11482, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2436_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8898)=2438 */ {8898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2438_l1}, +/*h(13079)=2439 */ {13079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3730)=2441 */ {3730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2441_l1}, +/*h(7911)=2442 */ {7911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2442_l1}, +/*h(1146)=2443 */ {1146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2443_l1}, +/*h(16273)=2444 */ {16273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2444_l1}, +/*h(2743)=2445 */ {2743, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11105)=2447 */ {11105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2447_l1}, +/*h(15286)=2448 */ {15286, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5937)=2450 */ {5937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2450_l1}, +/*h(10118)=2451 */ {10118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2451_l1}, +/*h(14299)=2452 */ {14299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2452_l1}, +/*h(769)=2453 */ {769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2453_l1}, +/*h(4950)=2454 */ {4950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2454_l1}, +/*h(9131)=2455 */ {9131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2455_l1}, +/*h(13312)=2456 */ {13312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3963)=2459 */ {3963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2459_l1}, +/*h(8144)=2460 */ {8144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2460_l1}, +/*h(12325)=2461 */ {12325, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2461_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13922)=2463 */ {13922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2463_l1}, +/*h(7157)=2464 */ {7157, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2464_l1}, +/*h(11338)=2465 */ {11338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2465_l1}, +/*h(8754)=2466 */ {8754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2466_l1}, +/*h(12935)=2467 */ {12935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2467_l1}, +/*h(6170)=2468 */ {6170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2468_l1}, +/*h(3586)=2469 */ {3586, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2469_l1}, +/*h(7767)=2470 */ {7767, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2470_l1}, +/*h(1002)=2471 */ {1002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2471_l1}, +/*h(16129)=2472 */ {16129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2472_l1}, +/*h(9364)=2473 */ {9364, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2473_l1}, +/*h(2599)=2474 */ {2599, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10961)=2476 */ {10961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2476_l1}, +/*h(15142)=2477 */ {15142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5793)=2479 */ {5793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2479_l1}, +/*h(9974)=2480 */ {9974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2480_l1}, +/*h(14155)=2481 */ {14155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2481_l1}, +/*h(625)=2482 */ {625, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2482_l1}, +/*h(4806)=2483 */ {4806, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2483_l1}, +/*h(8987)=2484 */ {8987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2484_l1}, +/*h(13168)=2485 */ {13168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2485_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3819)=2487 */ {3819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2487_l1}, +/*h(8000)=2488 */ {8000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2488_l1}, +/*h(1235)=2489 */ {1235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2489_l1}, +/*h(16362)=2490 */ {16362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2490_l1}, +/*h(2832)=2491 */ {2832, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2491_l1}, +/*h(7013)=2492 */ {7013, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2492_l1}, +/*h(11194)=2493 */ {11194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2493_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1845)=2495 */ {1845, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2495_l1}, +/*h(6026)=2496 */ {6026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2496_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14388)=2498 */ {14388, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2498_l1}, +/*h(858)=2499 */ {858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2499_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15985)=2501 */ {15985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2501_l1}, +/*h(13401)=2502 */ {13401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10817)=2504 */ {10817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2504_l1}, +/*h(14998)=2505 */ {14998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2505_l1}, +/*h(8233)=2506 */ {8233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2506_l1}, +/*h(5649)=2507 */ {5649, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2507_l1}, +/*h(9830)=2508 */ {9830, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2508_l1}, +/*h(14011)=2509 */ {14011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2509_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4662)=2511 */ {4662, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2511_l1}, +/*h(8843)=2512 */ {8843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2512_l1}, +/*h(13024)=2513 */ {13024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2513_l1}, +/*h(6259)=2514 */ {6259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2514_l1}, +/*h(3675)=2515 */ {3675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2515_l1}, +/*h(7856)=2516 */ {7856, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2516_l1}, +/*h(1091)=2517 */ {1091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2517_l1}, +/*h(16218)=2518 */ {16218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2518_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2688)=2520 */ {2688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2520_l1}, +/*h(6869)=2521 */ {6869, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2521_l1}, +/*h(11050)=2522 */ {11050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1701)=2524 */ {1701, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2524_l1}, +/*h(5882)=2525 */ {5882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2525_l1}, +/*h(3298)=2526 */ {3298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2526_l1}, +/*h(14244)=2527 */ {14244, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2527_l1}, +/*h(714)=2528 */ {714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9076)=2530 */ {9076, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2530_l1}, +/*h(13257)=2531 */ {13257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2531_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14854)=2533 */ {14854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2533_l1}, +/*h(8089)=2534 */ {8089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2534_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2921)=2537 */ {2921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2537_l1}, +/*h(13867)=2538 */ {13867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2538_l1}, +/*h(11283)=2539 */ {11283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2539_l1}, +/*h(15464)=2540 */ {15464, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6115)=2542 */ {6115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2542_l1}, +/*h(10296)=2543 */ {10296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2543_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(947)=2545 */ {947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2545_l1}, +/*h(11893)=2546 */ {11893, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2546_l1}, +/*h(16074)=2547 */ {16074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2547_l1}, +/*h(13490)=2548 */ {13490, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2548_l1}, +/*h(6725)=2549 */ {6725, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2549_l1}, +/*h(10906)=2550 */ {10906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2550_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8322)=2552 */ {8322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2552_l1}, +/*h(12503)=2553 */ {12503, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2553_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3154)=2555 */ {3154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2555_l1}, +/*h(570)=2556 */ {570, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2556_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8932)=2558 */ {8932, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2558_l1}, +/*h(2167)=2559 */ {2167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2559_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3764)=2561 */ {3764, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2561_l1}, +/*h(7945)=2562 */ {7945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2562_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16307)=2564 */ {16307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2564_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2777)=2566 */ {2777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2566_l1}, +/*h(193)=2567 */ {193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2567_l1}, +/*h(11139)=2568 */ {11139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2568_l1}, +/*h(15320)=2569 */ {15320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5971)=2571 */ {5971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2571_l1}, +/*h(10152)=2572 */ {10152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2572_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(803)=2574 */ {803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2574_l1}, +/*h(15930)=2575 */ {15930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2575_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13346)=2577 */ {13346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2577_l1}, +/*h(10762)=2578 */ {10762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8178)=2580 */ {8178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2580_l1}, +/*h(12359)=2581 */ {12359, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3010)=2583 */ {3010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2583_l1}, +/*h(7191)=2584 */ {7191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2584_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15553)=2586 */ {15553, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2586_l1}, +/*h(2023)=2587 */ {2023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2587_l1}, +/*h(12969)=2588 */ {12969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2588_l1}, +/*h(10385)=2589 */ {10385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2589_l1}, +/*h(14566)=2590 */ {14566, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2590_l1}, +/*h(7801)=2591 */ {7801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2591_l1}, +/*h(5217)=2592 */ {5217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2592_l1}, +/*h(9398)=2593 */ {9398, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2593_l1}, +/*h(2633)=2594 */ {2633, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10995)=2596 */ {10995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2596_l1}, +/*h(4230)=2597 */ {4230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2597_l1}, +/*h(8411)=2598 */ {8411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2598_l1}, +/*h(5827)=2599 */ {5827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2599_l1}, +/*h(10008)=2600 */ {10008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2600_l1}, +/*h(3243)=2601 */ {3243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2601_l1}, +/*h(659)=2602 */ {659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2602_l1}, +/*h(4840)=2603 */ {4840, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2603_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13202)=2605 */ {13202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2605_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8034)=2608 */ {8034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2608_l1}, +/*h(12215)=2609 */ {12215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2609_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2866)=2612 */ {2866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2612_l1}, +/*h(7047)=2613 */ {7047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2613_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15409)=2615 */ {15409, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2615_l1}, +/*h(1879)=2616 */ {1879, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2616_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10241)=2618 */ {10241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2618_l1}, +/*h(14422)=2619 */ {14422, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2619_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16019)=2621 */ {16019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2621_l1}, +/*h(9254)=2622 */ {9254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2622_l1}, +/*h(13435)=2623 */ {13435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2623_l1}, +/*h(10851)=2624 */ {10851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2624_l1}, +/*h(4086)=2625 */ {4086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2625_l1}, +/*h(8267)=2626 */ {8267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2626_l1}, +/*h(12448)=2627 */ {12448, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2627_l1}, +/*h(5683)=2628 */ {5683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2628_l1}, +/*h(3099)=2629 */ {3099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2629_l1}, +/*h(7280)=2630 */ {7280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2630_l1}, +/*h(515)=2631 */ {515, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2631_l1}, +/*h(4696)=2632 */ {4696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2632_l1}, +/*h(2112)=2633 */ {2112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2633_l1}, +/*h(13058)=2634 */ {13058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2634_l1}, +/*h(10474)=2635 */ {10474, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2635_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7890)=2637 */ {7890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2637_l1}, +/*h(5306)=2638 */ {5306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2638_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2722)=2640 */ {2722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2640_l1}, +/*h(6903)=2641 */ {6903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2641_l1}, +/*h(138)=2642 */ {138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2642_l1}, +/*h(15265)=2643 */ {15265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2643_l1}, +/*h(1735)=2644 */ {1735, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2644_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10097)=2646 */ {10097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2646_l1}, +/*h(14278)=2647 */ {14278, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2647_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4929)=2649 */ {4929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2649_l1}, +/*h(9110)=2650 */ {9110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2650_l1}, +/*h(13291)=2651 */ {13291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2651_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3942)=2653 */ {3942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2653_l1}, +/*h(8123)=2654 */ {8123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2654_l1}, +/*h(12304)=2655 */ {12304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2955)=2658 */ {2955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2658_l1}, +/*h(7136)=2659 */ {7136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2659_l1}, +/*h(15498)=2660 */ {15498, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2660_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12914)=2662 */ {12914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2662_l1}, +/*h(6149)=2663 */ {6149, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2663_l1}, +/*h(10330)=2664 */ {10330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2664_l1}, +/*h(7746)=2665 */ {7746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2665_l1}, +/*h(11927)=2666 */ {11927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2666_l1}, +/*h(5162)=2667 */ {5162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2667_l1}, +/*h(2578)=2668 */ {2578, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2668_l1}, +/*h(6759)=2669 */ {6759, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15121)=2671 */ {15121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2671_l1}, +/*h(8356)=2672 */ {8356, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2672_l1}, +/*h(1591)=2673 */ {1591, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2673_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9953)=2675 */ {9953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2675_l1}, +/*h(7369)=2676 */ {7369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2676_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4785)=2678 */ {4785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2678_l1}, +/*h(8966)=2679 */ {8966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2679_l1}, +/*h(13147)=2680 */ {13147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2680_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3798)=2682 */ {3798, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2682_l1}, +/*h(7979)=2683 */ {7979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2683_l1}, +/*h(12160)=2684 */ {12160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2684_l1}, +/*h(16341)=2685 */ {16341, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2685_l1}, +/*h(2811)=2686 */ {2811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2686_l1}, +/*h(6992)=2687 */ {6992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2687_l1}, +/*h(227)=2688 */ {227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2688_l1}, +/*h(15354)=2689 */ {15354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2689_l1}, +/*h(1824)=2690 */ {1824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2690_l1}, +/*h(6005)=2691 */ {6005, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2691_l1}, +/*h(10186)=2692 */ {10186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2692_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(837)=2694 */ {837, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2694_l1}, +/*h(5018)=2695 */ {5018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2695_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13380)=2697 */ {13380, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2697_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14977)=2700 */ {14977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2700_l1}, +/*h(12393)=2701 */ {12393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2701_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9809)=2703 */ {9809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2703_l1}, +/*h(13990)=2704 */ {13990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2704_l1}, +/*h(7225)=2705 */ {7225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2705_l1}, +/*h(15587)=2706 */ {15587, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2706_l1}, +/*h(8822)=2707 */ {8822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2707_l1}, +/*h(13003)=2708 */ {13003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2708_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10419)=2710 */ {10419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2710_l1}, +/*h(7835)=2711 */ {7835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2711_l1}, +/*h(12016)=2712 */ {12016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2712_l1}, +/*h(5251)=2713 */ {5251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2713_l1}, +/*h(2667)=2714 */ {2667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2714_l1}, +/*h(6848)=2715 */ {6848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2715_l1}, +/*h(83)=2716 */ {83, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2716_l1}, +/*h(15210)=2717 */ {15210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2717_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1680)=2719 */ {1680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2719_l1}, +/*h(5861)=2720 */ {5861, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2720_l1}, +/*h(10042)=2721 */ {10042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2721_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(693)=2723 */ {693, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2723_l1}, +/*h(4874)=2724 */ {4874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2724_l1}, +/*h(2290)=2725 */ {2290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2725_l1}, +/*h(13236)=2726 */ {13236, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2726_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8068)=2729 */ {8068, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2729_l1}, +/*h(12249)=2730 */ {12249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2730_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13846)=2732 */ {13846, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2732_l1}, +/*h(7081)=2733 */ {7081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2733_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15443)=2735 */ {15443, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2735_l1}, +/*h(12859)=2736 */ {12859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2736_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10275)=2738 */ {10275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2738_l1}, +/*h(14456)=2739 */ {14456, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2739_l1}, +/*h(7691)=2740 */ {7691, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2740_l1}, +/*h(5107)=2741 */ {5107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2741_l1}, +/*h(16053)=2742 */ {16053, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2742_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6704)=2744 */ {6704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2744_l1}, +/*h(10885)=2745 */ {10885, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2745_l1}, +/*h(15066)=2746 */ {15066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2746_l1}, +/*h(12482)=2747 */ {12482, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2747_l1}, +/*h(5717)=2748 */ {5717, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2748_l1}, +/*h(9898)=2749 */ {9898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2749_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7314)=2751 */ {7314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2751_l1}, +/*h(4730)=2752 */ {4730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2752_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2146)=2754 */ {2146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2754_l1}, +/*h(6327)=2755 */ {6327, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2755_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7924)=2757 */ {7924, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2757_l1}, +/*h(1159)=2758 */ {1159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2758_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2756)=2760 */ {2756, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2760_l1}, +/*h(6937)=2761 */ {6937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2761_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15299)=2763 */ {15299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2763_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1769)=2765 */ {1769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2765_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10131)=2767 */ {10131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2767_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4963)=2770 */ {4963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2770_l1}, +/*h(9144)=2771 */ {9144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14922)=2774 */ {14922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2774_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12338)=2776 */ {12338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2776_l1}, +/*h(9754)=2777 */ {9754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2777_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7170)=2779 */ {7170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2779_l1}, +/*h(11351)=2780 */ {11351, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2780_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2002)=2782 */ {2002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2782_l1}, +/*h(6183)=2783 */ {6183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2783_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14545)=2785 */ {14545, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2785_l1}, +/*h(1015)=2786 */ {1015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2786_l1}, +/*h(11961)=2787 */ {11961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2787_l1}, +/*h(9377)=2788 */ {9377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2788_l1}, +/*h(13558)=2789 */ {13558, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2789_l1}, +/*h(6793)=2790 */ {6793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2790_l1}, +/*h(4209)=2791 */ {4209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2791_l1}, +/*h(15155)=2792 */ {15155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2792_l1}, +/*h(1625)=2793 */ {1625, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2793_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9987)=2795 */ {9987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2795_l1}, +/*h(3222)=2796 */ {3222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2796_l1}, +/*h(7403)=2797 */ {7403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2797_l1}, +/*h(4819)=2798 */ {4819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2798_l1}, +/*h(9000)=2799 */ {9000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2799_l1}, +/*h(2235)=2800 */ {2235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2800_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3832)=2802 */ {3832, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2802_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12194)=2804 */ {12194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2804_l1}, +/*h(16375)=2805 */ {16375, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2805_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7026)=2807 */ {7026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2807_l1}, +/*h(11207)=2808 */ {11207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2808_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1858)=2811 */ {1858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2811_l1}, +/*h(6039)=2812 */ {6039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2812_l1}, +/*h(14401)=2813 */ {14401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2813_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(871)=2815 */ {871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2815_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9233)=2817 */ {9233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2817_l1}, +/*h(13414)=2818 */ {13414, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2818_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15011)=2820 */ {15011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2820_l1}, +/*h(8246)=2821 */ {8246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2821_l1}, +/*h(12427)=2822 */ {12427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2822_l1}, +/*h(9843)=2823 */ {9843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2823_l1}, +/*h(3078)=2824 */ {3078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2824_l1}, +/*h(7259)=2825 */ {7259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2825_l1}, +/*h(11440)=2826 */ {11440, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2826_l1}, +/*h(4675)=2827 */ {4675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2827_l1}, +/*h(2091)=2828 */ {2091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2828_l1}, +/*h(6272)=2829 */ {6272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2829_l1}, +/*h(10453)=2830 */ {10453, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2830_l1}, +/*h(3688)=2831 */ {3688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2831_l1}, +/*h(1104)=2832 */ {1104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2832_l1}, +/*h(12050)=2833 */ {12050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2833_l1}, +/*h(16231)=2834 */ {16231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2834_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6882)=2836 */ {6882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2836_l1}, +/*h(11063)=2837 */ {11063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2837_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1714)=2839 */ {1714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2839_l1}, +/*h(5895)=2840 */ {5895, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2840_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14257)=2842 */ {14257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2842_l1}, +/*h(727)=2843 */ {727, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2843_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9089)=2845 */ {9089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2845_l1}, +/*h(13270)=2846 */ {13270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2846_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3921)=2848 */ {3921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2848_l1}, +/*h(8102)=2849 */ {8102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2849_l1}, +/*h(12283)=2850 */ {12283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2850_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2934)=2852 */ {2934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2852_l1}, +/*h(7115)=2853 */ {7115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2853_l1}, +/*h(11296)=2854 */ {11296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2854_l1}, +/*h(15477)=2855 */ {15477, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2855_l1}, +/*h(8712)=2856 */ {8712, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2856_l1}, +/*h(1947)=2857 */ {1947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2857_l1}, +/*h(10309)=2858 */ {10309, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2858_l1}, +/*h(14490)=2859 */ {14490, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2859_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11906)=2861 */ {11906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2861_l1}, +/*h(16087)=2862 */ {16087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2862_l1}, +/*h(9322)=2863 */ {9322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2863_l1}, +/*h(6738)=2864 */ {6738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2864_l1}, +/*h(10919)=2865 */ {10919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2865_l1}, +/*h(4154)=2866 */ {4154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2866_l1}, +/*h(1570)=2867 */ {1570, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2867_l1}, +/*h(5751)=2868 */ {5751, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2868_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14113)=2870 */ {14113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2870_l1}, +/*h(7348)=2871 */ {7348, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2871_l1}, +/*h(583)=2872 */ {583, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2872_l1}, +/*h(8945)=2873 */ {8945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2873_l1}, +/*h(13126)=2874 */ {13126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2874_l1}, +/*h(6361)=2875 */ {6361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2875_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3777)=2877 */ {3777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2877_l1}, +/*h(7958)=2878 */ {7958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2878_l1}, +/*h(12139)=2879 */ {12139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2879_l1}, +/*h(16320)=2880 */ {16320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2880_l1}, +/*h(2790)=2881 */ {2790, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2881_l1}, +/*h(6971)=2882 */ {6971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2882_l1}, +/*h(11152)=2883 */ {11152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2883_l1}, +/*h(15333)=2884 */ {15333, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2884_l1}, +/*h(1803)=2885 */ {1803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2885_l1}, +/*h(5984)=2886 */ {5984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2886_l1}, +/*h(10165)=2887 */ {10165, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2887_l1}, +/*h(14346)=2888 */ {14346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2888_l1}, +/*h(816)=2889 */ {816, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2889_l1}, +/*h(15943)=2890 */ {15943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2890_l1}, +/*h(9178)=2891 */ {9178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2891_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4010)=2894 */ {4010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2894_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12372)=2896 */ {12372, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2896_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13969)=2899 */ {13969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2899_l1}, +/*h(11385)=2900 */ {11385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2900_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8801)=2902 */ {8801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2902_l1}, +/*h(12982)=2903 */ {12982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14579)=2905 */ {14579, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2905_l1}, +/*h(7814)=2906 */ {7814, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2906_l1}, +/*h(11995)=2907 */ {11995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2907_l1}, +/*h(16176)=2908 */ {16176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2908_l1}, +/*h(2646)=2909 */ {2646, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2909_l1}, +/*h(6827)=2910 */ {6827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2910_l1}, +/*h(11008)=2911 */ {11008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2911_l1}, +/*h(4243)=2912 */ {4243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2912_l1}, +/*h(1659)=2913 */ {1659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2913_l1}, +/*h(5840)=2914 */ {5840, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2914_l1}, +/*h(10021)=2915 */ {10021, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2915_l1}, +/*h(14202)=2916 */ {14202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2916_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(672)=2918 */ {672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2918_l1}, +/*h(9034)=2919 */ {9034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2919_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3866)=2923 */ {3866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2923_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12228)=2925 */ {12228, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2925_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13825)=2927 */ {13825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2927_l1}, +/*h(7060)=2928 */ {7060, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2928_l1}, +/*h(11241)=2929 */ {11241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2929_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12838)=2931 */ {12838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2931_l1}, +/*h(6073)=2932 */ {6073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14435)=2934 */ {14435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2934_l1}, +/*h(11851)=2935 */ {11851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2935_l1}, +/*h(16032)=2936 */ {16032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2936_l1}, +/*h(9267)=2937 */ {9267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2937_l1}, +/*h(13448)=2938 */ {13448, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2938_l1}, +/*h(6683)=2939 */ {6683, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2939_l1}, +/*h(4099)=2940 */ {4099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2940_l1}, +/*h(15045)=2941 */ {15045, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2941_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5696)=2943 */ {5696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2943_l1}, +/*h(9877)=2944 */ {9877, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2944_l1}, +/*h(14058)=2945 */ {14058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2945_l1}, +/*h(11474)=2946 */ {11474, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2946_l1}, +/*h(4709)=2947 */ {4709, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2947_l1}, +/*h(8890)=2948 */ {8890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2948_l1}, +/*h(6306)=2949 */ {6306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2949_l1}, +/*h(10487)=2950 */ {10487, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2950_l1}, +/*h(3722)=2951 */ {3722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2951_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1138)=2953 */ {1138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2953_l1}, +/*h(5319)=2954 */ {5319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2954_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6916)=2956 */ {6916, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2956_l1}, +/*h(151)=2957 */ {151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2957_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1748)=2959 */ {1748, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2959_l1}, +/*h(5929)=2960 */ {5929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2960_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14291)=2962 */ {14291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2962_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(761)=2964 */ {761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2964_l1}, +/*h(9123)=2965 */ {9123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2965_l1}, +/*h(13304)=2966 */ {13304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3955)=2969 */ {3955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2969_l1}, +/*h(8136)=2970 */ {8136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2970_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9733)=2972 */ {9733, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2972_l1}, +/*h(13914)=2973 */ {13914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2973_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11330)=2975 */ {11330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2975_l1}, +/*h(15511)=2976 */ {15511, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2976_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6162)=2978 */ {6162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2978_l1}, +/*h(10343)=2979 */ {10343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2979_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(994)=2981 */ {994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2981_l1}, +/*h(5175)=2982 */ {5175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2982_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13537)=2984 */ {13537, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2984_l1}, +/*h(7)=2985 */ {7, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2985_l1}, +/*h(10953)=2986 */ {10953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2986_l1}, +/*h(8369)=2987 */ {8369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2987_l1}, +/*h(1604)=2988 */ {1604, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2988_l1}, +/*h(5785)=2989 */ {5785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2989_l1}, +/*h(3201)=2990 */ {3201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2990_l1}, +/*h(14147)=2991 */ {14147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2991_l1}, +/*h(617)=2992 */ {617, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2992_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8979)=2994 */ {8979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2994_l1}, +/*h(6395)=2995 */ {6395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2995_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3811)=2997 */ {3811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2997_l1}, +/*h(7992)=2998 */ {7992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2998_l1}, +/*h(1227)=2999 */ {1227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_2999_l1}, +/*h(16354)=3000 */ {16354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3000_l1}, +/*h(2824)=3001 */ {2824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3001_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11186)=3003 */ {11186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3003_l1}, +/*h(15367)=3004 */ {15367, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3004_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6018)=3006 */ {6018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3006_l1}, +/*h(10199)=3007 */ {10199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3007_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5031)=3010 */ {5031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3010_l1}, +/*h(15977)=3011 */ {15977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3011_l1}, +/*h(13393)=3012 */ {13393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3012_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10809)=3014 */ {10809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3014_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8225)=3016 */ {8225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3016_l1}, +/*h(12406)=3017 */ {12406, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3017_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14003)=3019 */ {14003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3019_l1}, +/*h(7238)=3020 */ {7238, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3020_l1}, +/*h(11419)=3021 */ {11419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3021_l1}, +/*h(8835)=3022 */ {8835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3022_l1}, +/*h(2070)=3023 */ {2070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3023_l1}, +/*h(6251)=3024 */ {6251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3024_l1}, +/*h(3667)=3025 */ {3667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3025_l1}, +/*h(7848)=3026 */ {7848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3026_l1}, +/*h(1083)=3027 */ {1083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3027_l1}, +/*h(16210)=3028 */ {16210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3028_l1}, +/*h(9445)=3029 */ {9445, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3029_l1}, +/*h(2680)=3030 */ {2680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3030_l1}, +/*h(96)=3031 */ {96, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3031_l1}, +/*h(11042)=3032 */ {11042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3032_l1}, +/*h(15223)=3033 */ {15223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3033_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5874)=3035 */ {5874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3035_l1}, +/*h(10055)=3036 */ {10055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3036_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(706)=3038 */ {706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3038_l1}, +/*h(4887)=3039 */ {4887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3039_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13249)=3041 */ {13249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3041_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8081)=3044 */ {8081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3044_l1}, +/*h(12262)=3045 */ {12262, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3045_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2913)=3047 */ {2913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3047_l1}, +/*h(7094)=3048 */ {7094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3048_l1}, +/*h(11275)=3049 */ {11275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3049_l1}, +/*h(15456)=3050 */ {15456, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3050_l1}, +/*h(1926)=3051 */ {1926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3051_l1}, +/*h(6107)=3052 */ {6107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3052_l1}, +/*h(10288)=3053 */ {10288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3053_l1}, +/*h(14469)=3054 */ {14469, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3054_l1}, +/*h(939)=3055 */ {939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3055_l1}, +/*h(5120)=3056 */ {5120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3056_l1}, +/*h(16066)=3057 */ {16066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3057_l1}, +/*h(13482)=3058 */ {13482, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3058_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10898)=3060 */ {10898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3060_l1}, +/*h(15079)=3061 */ {15079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3061_l1}, +/*h(8314)=3062 */ {8314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3062_l1}, +/*h(5730)=3063 */ {5730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3063_l1}, +/*h(9911)=3064 */ {9911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3064_l1}, +/*h(3146)=3065 */ {3146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3065_l1}, +/*h(562)=3066 */ {562, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3066_l1}, +/*h(4743)=3067 */ {4743, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3067_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13105)=3069 */ {13105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3069_l1}, +/*h(6340)=3070 */ {6340, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3070_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7937)=3072 */ {7937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3072_l1}, +/*h(12118)=3073 */ {12118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3073_l1}, +/*h(16299)=3074 */ {16299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3074_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2769)=3076 */ {2769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3076_l1}, +/*h(6950)=3077 */ {6950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3077_l1}, +/*h(11131)=3078 */ {11131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3078_l1}, +/*h(15312)=3079 */ {15312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3079_l1}, +/*h(1782)=3080 */ {1782, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3080_l1}, +/*h(5963)=3081 */ {5963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3081_l1}, +/*h(10144)=3082 */ {10144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3082_l1}, +/*h(14325)=3083 */ {14325, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3083_l1}, +/*h(795)=3084 */ {795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3084_l1}, +/*h(15922)=3085 */ {15922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3085_l1}, +/*h(9157)=3086 */ {9157, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3086_l1}, +/*h(13338)=3087 */ {13338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3087_l1}, +/*h(10754)=3088 */ {10754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3088_l1}, +/*h(14935)=3089 */ {14935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3089_l1}, +/*h(8170)=3090 */ {8170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3090_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3002)=3093 */ {3002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11364)=3095 */ {11364, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3095_l1}, +/*h(15545)=3096 */ {15545, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3096_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12961)=3098 */ {12961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3098_l1}, +/*h(10377)=3099 */ {10377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3099_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7793)=3101 */ {7793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3101_l1}, +/*h(11974)=3102 */ {11974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3102_l1}, +/*h(16155)=3103 */ {16155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3103_l1}, +/*h(2625)=3104 */ {2625, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3104_l1}, +/*h(6806)=3105 */ {6806, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3105_l1}, +/*h(10987)=3106 */ {10987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3106_l1}, +/*h(15168)=3107 */ {15168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3107_l1}, +/*h(8403)=3108 */ {8403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3108_l1}, +/*h(5819)=3109 */ {5819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3109_l1}, +/*h(10000)=3110 */ {10000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3110_l1}, +/*h(3235)=3111 */ {3235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3111_l1}, +/*h(651)=3112 */ {651, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3112_l1}, +/*h(4832)=3113 */ {4832, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3113_l1}, +/*h(9013)=3114 */ {9013, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3114_l1}, +/*h(13194)=3115 */ {13194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3115_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3845)=3117 */ {3845, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3117_l1}, +/*h(8026)=3118 */ {8026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2858)=3122 */ {2858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11220)=3124 */ {11220, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3124_l1}, +/*h(15401)=3125 */ {15401, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3125_l1}, +/*h(12817)=3126 */ {12817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3126_l1}, +/*h(6052)=3127 */ {6052, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3127_l1}, +/*h(10233)=3128 */ {10233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11830)=3130 */ {11830, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3130_l1}, +/*h(16011)=3131 */ {16011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3131_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13427)=3133 */ {13427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3133_l1}, +/*h(10843)=3134 */ {10843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3134_l1}, +/*h(15024)=3135 */ {15024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3135_l1}, +/*h(8259)=3136 */ {8259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3136_l1}, +/*h(12440)=3137 */ {12440, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3137_l1}, +/*h(5675)=3138 */ {5675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3138_l1}, +/*h(3091)=3139 */ {3091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3139_l1}, +/*h(14037)=3140 */ {14037, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4688)=3142 */ {4688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3142_l1}, +/*h(8869)=3143 */ {8869, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3143_l1}, +/*h(13050)=3144 */ {13050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3144_l1}, +/*h(10466)=3145 */ {10466, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3145_l1}, +/*h(3701)=3146 */ {3701, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3146_l1}, +/*h(7882)=3147 */ {7882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3147_l1}, +/*h(5298)=3148 */ {5298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3148_l1}, +/*h(16244)=3149 */ {16244, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3149_l1}, +/*h(2714)=3150 */ {2714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(130)=3152 */ {130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3152_l1}, +/*h(4311)=3153 */ {4311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5908)=3155 */ {5908, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3155_l1}, +/*h(10089)=3156 */ {10089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(740)=3158 */ {740, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3158_l1}, +/*h(4921)=3159 */ {4921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13283)=3161 */ {13283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8115)=3164 */ {8115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3164_l1}, +/*h(12296)=3165 */ {12296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3165_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2947)=3168 */ {2947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3168_l1}, +/*h(7128)=3169 */ {7128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3169_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15490)=3171 */ {15490, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3171_l1}, +/*h(12906)=3172 */ {12906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10322)=3174 */ {10322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3174_l1}, +/*h(7738)=3175 */ {7738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5154)=3177 */ {5154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3177_l1}, +/*h(9335)=3178 */ {9335, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10932)=3180 */ {10932, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3180_l1}, +/*h(4167)=3181 */ {4167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3181_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12529)=3183 */ {12529, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3183_l1}, +/*h(5764)=3184 */ {5764, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3184_l1}, +/*h(9945)=3185 */ {9945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3185_l1}, +/*h(7361)=3186 */ {7361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3186_l1}, +/*h(596)=3187 */ {596, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3187_l1}, +/*h(4777)=3188 */ {4777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3188_l1}, +/*h(2193)=3189 */ {2193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3189_l1}, +/*h(13139)=3190 */ {13139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1206)=3193 */ {1206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3193_l1}, +/*h(12152)=3194 */ {12152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2803)=3196 */ {2803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3196_l1}, +/*h(6984)=3197 */ {6984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3197_l1}, +/*h(219)=3198 */ {219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3198_l1}, +/*h(15346)=3199 */ {15346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3199_l1}, +/*h(1816)=3200 */ {1816, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10178)=3202 */ {10178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3202_l1}, +/*h(14359)=3203 */ {14359, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5010)=3205 */ {5010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3205_l1}, +/*h(9191)=3206 */ {9191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4023)=3209 */ {4023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3209_l1}, +/*h(14969)=3210 */ {14969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3210_l1}, +/*h(12385)=3211 */ {12385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3211_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9801)=3213 */ {9801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7217)=3215 */ {7217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3215_l1}, +/*h(11398)=3216 */ {11398, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3216_l1}, +/*h(15579)=3217 */ {15579, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3217_l1}, +/*h(12995)=3218 */ {12995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3218_l1}, +/*h(6230)=3219 */ {6230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3219_l1}, +/*h(10411)=3220 */ {10411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3220_l1}, +/*h(7827)=3221 */ {7827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3221_l1}, +/*h(1062)=3222 */ {1062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3222_l1}, +/*h(5243)=3223 */ {5243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3223_l1}, +/*h(2659)=3224 */ {2659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3224_l1}, +/*h(6840)=3225 */ {6840, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3225_l1}, +/*h(75)=3226 */ {75, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3226_l1}, +/*h(15202)=3227 */ {15202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3227_l1}, +/*h(8437)=3228 */ {8437, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3228_l1}, +/*h(1672)=3229 */ {1672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3229_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3269)=3231 */ {3269, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3231_l1}, +/*h(14215)=3232 */ {14215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4866)=3234 */ {4866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3234_l1}, +/*h(9047)=3235 */ {9047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12241)=3240 */ {12241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7073)=3243 */ {7073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3243_l1}, +/*h(11254)=3244 */ {11254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3244_l1}, +/*h(15435)=3245 */ {15435, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3245_l1}, +/*h(1905)=3246 */ {1905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3246_l1}, +/*h(6086)=3247 */ {6086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3247_l1}, +/*h(10267)=3248 */ {10267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3248_l1}, +/*h(14448)=3249 */ {14448, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3249_l1}, +/*h(918)=3250 */ {918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3250_l1}, +/*h(5099)=3251 */ {5099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3251_l1}, +/*h(9280)=3252 */ {9280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3252_l1}, +/*h(13461)=3253 */ {13461, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3253_l1}, +/*h(6696)=3254 */ {6696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3254_l1}, +/*h(4112)=3255 */ {4112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3255_l1}, +/*h(15058)=3256 */ {15058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3256_l1}, +/*h(12474)=3257 */ {12474, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9890)=3259 */ {9890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3259_l1}, +/*h(14071)=3260 */ {14071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3260_l1}, +/*h(7306)=3261 */ {7306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3261_l1}, +/*h(4722)=3262 */ {4722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3262_l1}, +/*h(8903)=3263 */ {8903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3263_l1}, +/*h(2138)=3264 */ {2138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3735)=3266 */ {3735, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3266_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12097)=3268 */ {12097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3268_l1}, +/*h(16278)=3269 */ {16278, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6929)=3271 */ {6929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3271_l1}, +/*h(11110)=3272 */ {11110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3272_l1}, +/*h(15291)=3273 */ {15291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1761)=3275 */ {1761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3275_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10123)=3277 */ {10123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3277_l1}, +/*h(14304)=3278 */ {14304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3278_l1}, +/*h(774)=3279 */ {774, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3279_l1}, +/*h(4955)=3280 */ {4955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3280_l1}, +/*h(9136)=3281 */ {9136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3281_l1}, +/*h(13317)=3282 */ {13317, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3282_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14914)=3284 */ {14914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3284_l1}, +/*h(8149)=3285 */ {8149, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3285_l1}, +/*h(12330)=3286 */ {12330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3286_l1}, +/*h(9746)=3287 */ {9746, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3287_l1}, +/*h(13927)=3288 */ {13927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3288_l1}, +/*h(7162)=3289 */ {7162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3289_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15524)=3291 */ {15524, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3291_l1}, +/*h(1994)=3292 */ {1994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10356)=3294 */ {10356, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3294_l1}, +/*h(3591)=3295 */ {3591, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11953)=3297 */ {11953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3297_l1}, +/*h(16134)=3298 */ {16134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6785)=3300 */ {6785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3300_l1}, +/*h(10966)=3301 */ {10966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3301_l1}, +/*h(15147)=3302 */ {15147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3302_l1}, +/*h(1617)=3303 */ {1617, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3303_l1}, +/*h(5798)=3304 */ {5798, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3304_l1}, +/*h(9979)=3305 */ {9979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3305_l1}, +/*h(14160)=3306 */ {14160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3306_l1}, +/*h(630)=3307 */ {630, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3307_l1}, +/*h(4811)=3308 */ {4811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3308_l1}, +/*h(8992)=3309 */ {8992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3309_l1}, +/*h(2227)=3310 */ {2227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3824)=3312 */ {3824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3312_l1}, +/*h(8005)=3313 */ {8005, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3313_l1}, +/*h(12186)=3314 */ {12186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3314_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2837)=3316 */ {2837, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3316_l1}, +/*h(7018)=3317 */ {7018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15380)=3319 */ {15380, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3319_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1850)=3321 */ {1850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3321_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14393)=3323 */ {14393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3323_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11809)=3325 */ {11809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3325_l1}, +/*h(15990)=3326 */ {15990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3326_l1}, +/*h(9225)=3327 */ {9225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10822)=3329 */ {10822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3329_l1}, +/*h(15003)=3330 */ {15003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5654)=3332 */ {5654, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3332_l1}, +/*h(9835)=3333 */ {9835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3333_l1}, +/*h(14016)=3334 */ {14016, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3334_l1}, +/*h(7251)=3335 */ {7251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3335_l1}, +/*h(11432)=3336 */ {11432, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3336_l1}, +/*h(4667)=3337 */ {4667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3337_l1}, +/*h(2083)=3338 */ {2083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3338_l1}, +/*h(6264)=3339 */ {6264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3339_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3680)=3341 */ {3680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3341_l1}, +/*h(7861)=3342 */ {7861, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3342_l1}, +/*h(12042)=3343 */ {12042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3343_l1}, +/*h(9458)=3344 */ {9458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3344_l1}, +/*h(2693)=3345 */ {2693, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3345_l1}, +/*h(6874)=3346 */ {6874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3346_l1}, +/*h(4290)=3347 */ {4290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3347_l1}, +/*h(15236)=3348 */ {15236, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3348_l1}, +/*h(1706)=3349 */ {1706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10068)=3351 */ {10068, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3351_l1}, +/*h(3303)=3352 */ {3303, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3352_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4900)=3354 */ {4900, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3354_l1}, +/*h(9081)=3355 */ {9081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3355_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3913)=3358 */ {3913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3358_l1}, +/*h(14859)=3359 */ {14859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3359_l1}, +/*h(12275)=3360 */ {12275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3360_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7107)=3363 */ {7107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3363_l1}, +/*h(11288)=3364 */ {11288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8704)=3366 */ {8704, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3366_l1}, +/*h(1939)=3367 */ {1939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3367_l1}, +/*h(6120)=3368 */ {6120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3368_l1}, +/*h(14482)=3369 */ {14482, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3369_l1}, +/*h(7717)=3370 */ {7717, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3370_l1}, +/*h(11898)=3371 */ {11898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3371_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9314)=3373 */ {9314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3373_l1}, +/*h(13495)=3374 */ {13495, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4146)=3376 */ {4146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3376_l1}, +/*h(1562)=3377 */ {1562, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9924)=3379 */ {9924, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3379_l1}, +/*h(3159)=3380 */ {3159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4756)=3383 */ {4756, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3383_l1}, +/*h(8937)=3384 */ {8937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3384_l1}, +/*h(6353)=3385 */ {6353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3385_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3769)=3387 */ {3769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3387_l1}, +/*h(1185)=3388 */ {1185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3388_l1}, +/*h(12131)=3389 */ {12131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3389_l1}, +/*h(16312)=3390 */ {16312, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6963)=3392 */ {6963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3392_l1}, +/*h(11144)=3393 */ {11144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3393_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1795)=3395 */ {1795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3395_l1}, +/*h(5976)=3396 */ {5976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3396_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14338)=3398 */ {14338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3398_l1}, +/*h(808)=3399 */ {808, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9170)=3401 */ {9170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3401_l1}, +/*h(13351)=3402 */ {13351, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3402_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4002)=3404 */ {4002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3404_l1}, +/*h(8183)=3405 */ {8183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3015)=3408 */ {3015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3408_l1}, +/*h(13961)=3409 */ {13961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3409_l1}, +/*h(11377)=3410 */ {11377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3410_l1}, +/*h(15558)=3411 */ {15558, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3411_l1}, +/*h(8793)=3412 */ {8793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3412_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10390)=3414 */ {10390, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3414_l1}, +/*h(14571)=3415 */ {14571, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11987)=3417 */ {11987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3417_l1}, +/*h(5222)=3418 */ {5222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3418_l1}, +/*h(9403)=3419 */ {9403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3419_l1}, +/*h(6819)=3420 */ {6819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3420_l1}, +/*h(54)=3421 */ {54, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3421_l1}, +/*h(4235)=3422 */ {4235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3422_l1}, +/*h(1651)=3423 */ {1651, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3423_l1}, +/*h(5832)=3424 */ {5832, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3424_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14194)=3426 */ {14194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3426_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(664)=3428 */ {664, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3428_l1}, +/*h(9026)=3429 */ {9026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3429_l1}, +/*h(13207)=3430 */ {13207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3858)=3433 */ {3858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3433_l1}, +/*h(8039)=3434 */ {8039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3434_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2871)=3437 */ {2871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11233)=3439 */ {11233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3439_l1}, +/*h(15414)=3440 */ {15414, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3440_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6065)=3442 */ {6065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3442_l1}, +/*h(10246)=3443 */ {10246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3443_l1}, +/*h(14427)=3444 */ {14427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3444_l1}, +/*h(11843)=3445 */ {11843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3445_l1}, +/*h(5078)=3446 */ {5078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3446_l1}, +/*h(9259)=3447 */ {9259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3447_l1}, +/*h(13440)=3448 */ {13440, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3448_l1}, +/*h(6675)=3449 */ {6675, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3449_l1}, +/*h(4091)=3450 */ {4091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3450_l1}, +/*h(8272)=3451 */ {8272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3451_l1}, +/*h(12453)=3452 */ {12453, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3452_l1}, +/*h(5688)=3453 */ {5688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3453_l1}, +/*h(3104)=3454 */ {3104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3454_l1}, +/*h(14050)=3455 */ {14050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3455_l1}, +/*h(11466)=3456 */ {11466, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8882)=3458 */ {8882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3458_l1}, +/*h(13063)=3459 */ {13063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3459_l1}, +/*h(6298)=3460 */ {6298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3460_l1}, +/*h(3714)=3461 */ {3714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3461_l1}, +/*h(7895)=3462 */ {7895, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3462_l1}, +/*h(1130)=3463 */ {1130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3463_l1}, +/*h(16257)=3464 */ {16257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3464_l1}, +/*h(2727)=3465 */ {2727, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11089)=3467 */ {11089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3467_l1}, +/*h(15270)=3468 */ {15270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3468_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5921)=3470 */ {5921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3470_l1}, +/*h(10102)=3471 */ {10102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3471_l1}, +/*h(14283)=3472 */ {14283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3472_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(753)=3474 */ {753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3474_l1}, +/*h(9115)=3475 */ {9115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3475_l1}, +/*h(13296)=3476 */ {13296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3947)=3479 */ {3947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3479_l1}, +/*h(8128)=3480 */ {8128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3480_l1}, +/*h(12309)=3481 */ {12309, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13906)=3483 */ {13906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3483_l1}, +/*h(7141)=3484 */ {7141, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3484_l1}, +/*h(11322)=3485 */ {11322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3485_l1}, +/*h(8738)=3486 */ {8738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3486_l1}, +/*h(12919)=3487 */ {12919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3487_l1}, +/*h(6154)=3488 */ {6154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3488_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7751)=3490 */ {7751, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3490_l1}, +/*h(986)=3491 */ {986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3491_l1}, +/*h(16113)=3492 */ {16113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3492_l1}, +/*h(9348)=3493 */ {9348, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3493_l1}, +/*h(2583)=3494 */ {2583, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3494_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10945)=3496 */ {10945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3496_l1}, +/*h(15126)=3497 */ {15126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3497_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5777)=3499 */ {5777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3499_l1}, +/*h(9958)=3500 */ {9958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3500_l1}, +/*h(14139)=3501 */ {14139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3501_l1}, +/*h(609)=3502 */ {609, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3502_l1}, +/*h(4790)=3503 */ {4790, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3503_l1}, +/*h(8971)=3504 */ {8971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3504_l1}, +/*h(6387)=3505 */ {6387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3803)=3507 */ {3803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3507_l1}, +/*h(7984)=3508 */ {7984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3508_l1}, +/*h(1219)=3509 */ {1219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3509_l1}, +/*h(16346)=3510 */ {16346, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3510_l1}, +/*h(2816)=3511 */ {2816, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3511_l1}, +/*h(6997)=3512 */ {6997, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3512_l1}, +/*h(11178)=3513 */ {11178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1829)=3515 */ {1829, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3515_l1}, +/*h(6010)=3516 */ {6010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3516_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14372)=3518 */ {14372, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3518_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(842)=3520 */ {842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3520_l1}, +/*h(15969)=3521 */ {15969, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3521_l1}, +/*h(13385)=3522 */ {13385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10801)=3524 */ {10801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3524_l1}, +/*h(14982)=3525 */ {14982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3525_l1}, +/*h(8217)=3526 */ {8217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3526_l1}, +/*h(5633)=3527 */ {5633, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3527_l1}, +/*h(9814)=3528 */ {9814, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3528_l1}, +/*h(13995)=3529 */ {13995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3529_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11411)=3531 */ {11411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3531_l1}, +/*h(8827)=3532 */ {8827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3532_l1}, +/*h(13008)=3533 */ {13008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3533_l1}, +/*h(6243)=3534 */ {6243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3534_l1}, +/*h(10424)=3535 */ {10424, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3535_l1}, +/*h(3659)=3536 */ {3659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3536_l1}, +/*h(1075)=3537 */ {1075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3537_l1}, +/*h(16202)=3538 */ {16202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2672)=3540 */ {2672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3540_l1}, +/*h(6853)=3541 */ {6853, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3541_l1}, +/*h(11034)=3542 */ {11034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1685)=3544 */ {1685, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3544_l1}, +/*h(5866)=3545 */ {5866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3545_l1}, +/*h(3282)=3546 */ {3282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3546_l1}, +/*h(14228)=3547 */ {14228, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3547_l1}, +/*h(698)=3548 */ {698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9060)=3550 */ {9060, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3550_l1}, +/*h(2295)=3551 */ {2295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3551_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3892)=3553 */ {3892, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3553_l1}, +/*h(8073)=3554 */ {8073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3554_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2905)=3557 */ {2905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3557_l1}, +/*h(13851)=3558 */ {13851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3558_l1}, +/*h(11267)=3559 */ {11267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3559_l1}, +/*h(15448)=3560 */ {15448, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3560_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6099)=3562 */ {6099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3562_l1}, +/*h(10280)=3563 */ {10280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3563_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7696)=3565 */ {7696, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3565_l1}, +/*h(931)=3566 */ {931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3566_l1}, +/*h(16058)=3567 */ {16058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3567_l1}, +/*h(13474)=3568 */ {13474, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3568_l1}, +/*h(6709)=3569 */ {6709, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3569_l1}, +/*h(10890)=3570 */ {10890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3570_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8306)=3572 */ {8306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3572_l1}, +/*h(5722)=3573 */ {5722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3573_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3138)=3575 */ {3138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3575_l1}, +/*h(7319)=3576 */ {7319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8916)=3578 */ {8916, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3578_l1}, +/*h(2151)=3579 */ {2151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3579_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3748)=3581 */ {3748, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3581_l1}, +/*h(7929)=3582 */ {7929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3582_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16291)=3584 */ {16291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3584_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2761)=3586 */ {2761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3586_l1}, +/*h(177)=3587 */ {177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3587_l1}, +/*h(11123)=3588 */ {11123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3588_l1}, +/*h(15304)=3589 */ {15304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3589_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5955)=3591 */ {5955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3591_l1}, +/*h(10136)=3592 */ {10136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3592_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(787)=3594 */ {787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3594_l1}, +/*h(15914)=3595 */ {15914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3595_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13330)=3597 */ {13330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8162)=3600 */ {8162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3600_l1}, +/*h(12343)=3601 */ {12343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3601_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2994)=3603 */ {2994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3603_l1}, +/*h(7175)=3604 */ {7175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3604_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15537)=3606 */ {15537, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3606_l1}, +/*h(2007)=3607 */ {2007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3607_l1}, +/*h(12953)=3608 */ {12953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3608_l1}, +/*h(10369)=3609 */ {10369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3609_l1}, +/*h(14550)=3610 */ {14550, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3610_l1}, +/*h(7785)=3611 */ {7785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3611_l1}, +/*h(5201)=3612 */ {5201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3612_l1}, +/*h(16147)=3613 */ {16147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3613_l1}, +/*h(13563)=3614 */ {13563, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3614_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10979)=3616 */ {10979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3616_l1}, +/*h(4214)=3617 */ {4214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3617_l1}, +/*h(8395)=3618 */ {8395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3618_l1}, +/*h(5811)=3619 */ {5811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3619_l1}, +/*h(9992)=3620 */ {9992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3620_l1}, +/*h(3227)=3621 */ {3227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3621_l1}, +/*h(643)=3622 */ {643, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3622_l1}, +/*h(4824)=3623 */ {4824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3623_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13186)=3625 */ {13186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8018)=3628 */ {8018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3628_l1}, +/*h(12199)=3629 */ {12199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3629_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2850)=3632 */ {2850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3632_l1}, +/*h(7031)=3633 */ {7031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3633_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15393)=3635 */ {15393, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3635_l1}, +/*h(1863)=3636 */ {1863, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3636_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10225)=3638 */ {10225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3638_l1}, +/*h(14406)=3639 */ {14406, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3639_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16003)=3641 */ {16003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3641_l1}, +/*h(9238)=3642 */ {9238, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3642_l1}, +/*h(13419)=3643 */ {13419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3643_l1}, +/*h(10835)=3644 */ {10835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3644_l1}, +/*h(4070)=3645 */ {4070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3645_l1}, +/*h(8251)=3646 */ {8251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3646_l1}, +/*h(12432)=3647 */ {12432, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3647_l1}, +/*h(5667)=3648 */ {5667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3648_l1}, +/*h(3083)=3649 */ {3083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3649_l1}, +/*h(7264)=3650 */ {7264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3650_l1}, +/*h(11445)=3651 */ {11445, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3651_l1}, +/*h(4680)=3652 */ {4680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3652_l1}, +/*h(2096)=3653 */ {2096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3653_l1}, +/*h(13042)=3654 */ {13042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3654_l1}, +/*h(10458)=3655 */ {10458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7874)=3657 */ {7874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3657_l1}, +/*h(12055)=3658 */ {12055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3658_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2706)=3660 */ {2706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3660_l1}, +/*h(6887)=3661 */ {6887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3661_l1}, +/*h(122)=3662 */ {122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3662_l1}, +/*h(15249)=3663 */ {15249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3663_l1}, +/*h(1719)=3664 */ {1719, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3664_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10081)=3666 */ {10081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3666_l1}, +/*h(14262)=3667 */ {14262, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3667_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4913)=3669 */ {4913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3669_l1}, +/*h(9094)=3670 */ {9094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3670_l1}, +/*h(13275)=3671 */ {13275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3671_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3926)=3673 */ {3926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3673_l1}, +/*h(8107)=3674 */ {8107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3674_l1}, +/*h(12288)=3675 */ {12288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3675_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2939)=3678 */ {2939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3678_l1}, +/*h(7120)=3679 */ {7120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3679_l1}, +/*h(11301)=3680 */ {11301, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3680_l1}, +/*h(15482)=3681 */ {15482, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3681_l1}, +/*h(12898)=3682 */ {12898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3682_l1}, +/*h(6133)=3683 */ {6133, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3683_l1}, +/*h(10314)=3684 */ {10314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3684_l1}, +/*h(7730)=3685 */ {7730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3685_l1}, +/*h(11911)=3686 */ {11911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3686_l1}, +/*h(5146)=3687 */ {5146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3687_l1}, +/*h(2562)=3688 */ {2562, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3688_l1}, +/*h(6743)=3689 */ {6743, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3689_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15105)=3691 */ {15105, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3691_l1}, +/*h(8340)=3692 */ {8340, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3692_l1}, +/*h(1575)=3693 */ {1575, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9937)=3695 */ {9937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3695_l1}, +/*h(7353)=3696 */ {7353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3696_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4769)=3698 */ {4769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3698_l1}, +/*h(8950)=3699 */ {8950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3699_l1}, +/*h(13131)=3700 */ {13131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3700_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3782)=3702 */ {3782, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3702_l1}, +/*h(7963)=3703 */ {7963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3703_l1}, +/*h(12144)=3704 */ {12144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3704_l1}, +/*h(16325)=3705 */ {16325, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3705_l1}, +/*h(2795)=3706 */ {2795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3706_l1}, +/*h(6976)=3707 */ {6976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3707_l1}, +/*h(211)=3708 */ {211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3708_l1}, +/*h(15338)=3709 */ {15338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3709_l1}, +/*h(1808)=3710 */ {1808, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3710_l1}, +/*h(5989)=3711 */ {5989, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3711_l1}, +/*h(10170)=3712 */ {10170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3712_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(821)=3714 */ {821, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3714_l1}, +/*h(5002)=3715 */ {5002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13364)=3717 */ {13364, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3717_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14961)=3720 */ {14961, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3720_l1}, +/*h(12377)=3721 */ {12377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3721_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9793)=3723 */ {9793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3723_l1}, +/*h(13974)=3724 */ {13974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3724_l1}, +/*h(7209)=3725 */ {7209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3725_l1}, +/*h(4625)=3726 */ {4625, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3726_l1}, +/*h(15571)=3727 */ {15571, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3727_l1}, +/*h(12987)=3728 */ {12987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3728_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3638)=3730 */ {3638, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3730_l1}, +/*h(7819)=3731 */ {7819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3731_l1}, +/*h(12000)=3732 */ {12000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3732_l1}, +/*h(5235)=3733 */ {5235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3733_l1}, +/*h(2651)=3734 */ {2651, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3734_l1}, +/*h(6832)=3735 */ {6832, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3735_l1}, +/*h(67)=3736 */ {67, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3736_l1}, +/*h(15194)=3737 */ {15194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3737_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1664)=3739 */ {1664, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3739_l1}, +/*h(5845)=3740 */ {5845, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3740_l1}, +/*h(10026)=3741 */ {10026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3741_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(677)=3743 */ {677, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3743_l1}, +/*h(4858)=3744 */ {4858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3744_l1}, +/*h(2274)=3745 */ {2274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3745_l1}, +/*h(13220)=3746 */ {13220, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3746_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8052)=3749 */ {8052, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3749_l1}, +/*h(12233)=3750 */ {12233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13830)=3752 */ {13830, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3752_l1}, +/*h(7065)=3753 */ {7065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3753_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15427)=3755 */ {15427, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3755_l1}, +/*h(1897)=3756 */ {1897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3756_l1}, +/*h(12843)=3757 */ {12843, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3757_l1}, +/*h(10259)=3758 */ {10259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3758_l1}, +/*h(14440)=3759 */ {14440, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3759_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5091)=3761 */ {5091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3761_l1}, +/*h(16037)=3762 */ {16037, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3762_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6688)=3764 */ {6688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3764_l1}, +/*h(10869)=3765 */ {10869, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3765_l1}, +/*h(15050)=3766 */ {15050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3766_l1}, +/*h(12466)=3767 */ {12466, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3767_l1}, +/*h(5701)=3768 */ {5701, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3768_l1}, +/*h(9882)=3769 */ {9882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3769_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7298)=3771 */ {7298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3771_l1}, +/*h(11479)=3772 */ {11479, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3772_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2130)=3774 */ {2130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3774_l1}, +/*h(6311)=3775 */ {6311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3775_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7908)=3777 */ {7908, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3777_l1}, +/*h(1143)=3778 */ {1143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3778_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2740)=3780 */ {2740, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3780_l1}, +/*h(6921)=3781 */ {6921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3781_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15283)=3783 */ {15283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3783_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1753)=3785 */ {1753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3785_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10115)=3787 */ {10115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3787_l1}, +/*h(14296)=3788 */ {14296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4947)=3790 */ {4947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3790_l1}, +/*h(9128)=3791 */ {9128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3791_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14906)=3794 */ {14906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3794_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12322)=3796 */ {12322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3796_l1}, +/*h(9738)=3797 */ {9738, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3797_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7154)=3799 */ {7154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3799_l1}, +/*h(11335)=3800 */ {11335, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3800_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1986)=3802 */ {1986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3802_l1}, +/*h(6167)=3803 */ {6167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14529)=3805 */ {14529, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3805_l1}, +/*h(999)=3806 */ {999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3806_l1}, +/*h(11945)=3807 */ {11945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3807_l1}, +/*h(9361)=3808 */ {9361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3808_l1}, +/*h(13542)=3809 */ {13542, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3809_l1}, +/*h(6777)=3810 */ {6777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3810_l1}, +/*h(4193)=3811 */ {4193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3811_l1}, +/*h(15139)=3812 */ {15139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3812_l1}, +/*h(1609)=3813 */ {1609, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3813_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9971)=3815 */ {9971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3815_l1}, +/*h(3206)=3816 */ {3206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3816_l1}, +/*h(7387)=3817 */ {7387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3817_l1}, +/*h(4803)=3818 */ {4803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3818_l1}, +/*h(8984)=3819 */ {8984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3819_l1}, +/*h(2219)=3820 */ {2219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3816)=3822 */ {3816, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3822_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12178)=3824 */ {12178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3824_l1}, +/*h(16359)=3825 */ {16359, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7010)=3827 */ {7010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3827_l1}, +/*h(11191)=3828 */ {11191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3828_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6023)=3832 */ {6023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3832_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14385)=3834 */ {14385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3834_l1}, +/*h(855)=3835 */ {855, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3835_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9217)=3837 */ {9217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3837_l1}, +/*h(13398)=3838 */ {13398, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3838_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14995)=3840 */ {14995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3840_l1}, +/*h(8230)=3841 */ {8230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3841_l1}, +/*h(12411)=3842 */ {12411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3842_l1}, +/*h(9827)=3843 */ {9827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3843_l1}, +/*h(3062)=3844 */ {3062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3844_l1}, +/*h(7243)=3845 */ {7243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3845_l1}, +/*h(11424)=3846 */ {11424, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3846_l1}, +/*h(4659)=3847 */ {4659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3847_l1}, +/*h(2075)=3848 */ {2075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3848_l1}, +/*h(6256)=3849 */ {6256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3849_l1}, +/*h(10437)=3850 */ {10437, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3850_l1}, +/*h(3672)=3851 */ {3672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3851_l1}, +/*h(1088)=3852 */ {1088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3852_l1}, +/*h(12034)=3853 */ {12034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3853_l1}, +/*h(16215)=3854 */ {16215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6866)=3856 */ {6866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3856_l1}, +/*h(11047)=3857 */ {11047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3857_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1698)=3859 */ {1698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3859_l1}, +/*h(5879)=3860 */ {5879, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3860_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14241)=3862 */ {14241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3862_l1}, +/*h(711)=3863 */ {711, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3863_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9073)=3865 */ {9073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3865_l1}, +/*h(13254)=3866 */ {13254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3866_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3905)=3868 */ {3905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3868_l1}, +/*h(8086)=3869 */ {8086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3869_l1}, +/*h(12267)=3870 */ {12267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3870_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2918)=3872 */ {2918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3872_l1}, +/*h(7099)=3873 */ {7099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3873_l1}, +/*h(11280)=3874 */ {11280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3874_l1}, +/*h(15461)=3875 */ {15461, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3875_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1931)=3877 */ {1931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3877_l1}, +/*h(6112)=3878 */ {6112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3878_l1}, +/*h(10293)=3879 */ {10293, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3879_l1}, +/*h(14474)=3880 */ {14474, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3880_l1}, +/*h(11890)=3881 */ {11890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3881_l1}, +/*h(16071)=3882 */ {16071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3882_l1}, +/*h(9306)=3883 */ {9306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3883_l1}, +/*h(6722)=3884 */ {6722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3884_l1}, +/*h(10903)=3885 */ {10903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3885_l1}, +/*h(4138)=3886 */ {4138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3886_l1}, +/*h(1554)=3887 */ {1554, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3887_l1}, +/*h(5735)=3888 */ {5735, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3888_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14097)=3890 */ {14097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3890_l1}, +/*h(7332)=3891 */ {7332, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3891_l1}, +/*h(567)=3892 */ {567, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3892_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8929)=3894 */ {8929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3894_l1}, +/*h(13110)=3895 */ {13110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3895_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3761)=3897 */ {3761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3897_l1}, +/*h(7942)=3898 */ {7942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3898_l1}, +/*h(12123)=3899 */ {12123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3899_l1}, +/*h(16304)=3900 */ {16304, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3900_l1}, +/*h(2774)=3901 */ {2774, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3901_l1}, +/*h(6955)=3902 */ {6955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3902_l1}, +/*h(11136)=3903 */ {11136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3903_l1}, +/*h(15317)=3904 */ {15317, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3904_l1}, +/*h(1787)=3905 */ {1787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3905_l1}, +/*h(5968)=3906 */ {5968, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3906_l1}, +/*h(10149)=3907 */ {10149, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3907_l1}, +/*h(14330)=3908 */ {14330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3908_l1}, +/*h(800)=3909 */ {800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3909_l1}, +/*h(15927)=3910 */ {15927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3910_l1}, +/*h(9162)=3911 */ {9162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3911_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3994)=3914 */ {3994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3914_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12356)=3916 */ {12356, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3916_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13953)=3919 */ {13953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3919_l1}, +/*h(11369)=3920 */ {11369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8785)=3922 */ {8785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3922_l1}, +/*h(12966)=3923 */ {12966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3923_l1}, +/*h(6201)=3924 */ {6201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3924_l1}, +/*h(14563)=3925 */ {14563, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3925_l1}, +/*h(7798)=3926 */ {7798, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3926_l1}, +/*h(11979)=3927 */ {11979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3927_l1}, +/*h(16160)=3928 */ {16160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3928_l1}, +/*h(9395)=3929 */ {9395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3929_l1}, +/*h(6811)=3930 */ {6811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3930_l1}, +/*h(10992)=3931 */ {10992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3931_l1}, +/*h(4227)=3932 */ {4227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3932_l1}, +/*h(1643)=3933 */ {1643, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3933_l1}, +/*h(5824)=3934 */ {5824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3934_l1}, +/*h(10005)=3935 */ {10005, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3935_l1}, +/*h(14186)=3936 */ {14186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3936_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(656)=3938 */ {656, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3938_l1}, +/*h(4837)=3939 */ {4837, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3939_l1}, +/*h(9018)=3940 */ {9018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3940_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3850)=3943 */ {3850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3943_l1}, +/*h(1266)=3944 */ {1266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3944_l1}, +/*h(12212)=3945 */ {12212, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3945_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7044)=3948 */ {7044, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3948_l1}, +/*h(11225)=3949 */ {11225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3949_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12822)=3951 */ {12822, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3951_l1}, +/*h(6057)=3952 */ {6057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3952_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14419)=3954 */ {14419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3954_l1}, +/*h(889)=3955 */ {889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3955_l1}, +/*h(11835)=3956 */ {11835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3956_l1}, +/*h(9251)=3957 */ {9251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3957_l1}, +/*h(13432)=3958 */ {13432, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3958_l1}, +/*h(6667)=3959 */ {6667, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3959_l1}, +/*h(4083)=3960 */ {4083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3960_l1}, +/*h(15029)=3961 */ {15029, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3961_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5680)=3963 */ {5680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3963_l1}, +/*h(9861)=3964 */ {9861, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3964_l1}, +/*h(14042)=3965 */ {14042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3965_l1}, +/*h(11458)=3966 */ {11458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3966_l1}, +/*h(4693)=3967 */ {4693, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3967_l1}, +/*h(8874)=3968 */ {8874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3968_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6290)=3970 */ {6290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3970_l1}, +/*h(3706)=3971 */ {3706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3971_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1122)=3973 */ {1122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3973_l1}, +/*h(5303)=3974 */ {5303, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3974_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6900)=3976 */ {6900, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3976_l1}, +/*h(135)=3977 */ {135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3977_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1732)=3979 */ {1732, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3979_l1}, +/*h(5913)=3980 */ {5913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3980_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14275)=3982 */ {14275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3982_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(745)=3984 */ {745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3984_l1}, +/*h(15872)=3985 */ {15872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3985_l1}, +/*h(9107)=3986 */ {9107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3939)=3989 */ {3939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3989_l1}, +/*h(8120)=3990 */ {8120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3990_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13898)=3993 */ {13898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3993_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11314)=3995 */ {11314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3995_l1}, +/*h(8730)=3996 */ {8730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3996_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6146)=3998 */ {6146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3998_l1}, +/*h(10327)=3999 */ {10327, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_3999_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(978)=4001 */ {978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4001_l1}, +/*h(5159)=4002 */ {5159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4002_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13521)=4004 */ {13521, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4004_l1}, +/*h(6756)=4005 */ {6756, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4005_l1}, +/*h(10937)=4006 */ {10937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4006_l1}, +/*h(8353)=4007 */ {8353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4007_l1}, +/*h(12534)=4008 */ {12534, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4008_l1}, +/*h(5769)=4009 */ {5769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4009_l1}, +/*h(3185)=4010 */ {3185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4010_l1}, +/*h(7366)=4011 */ {7366, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4011_l1}, +/*h(601)=4012 */ {601, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4012_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8963)=4014 */ {8963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4014_l1}, +/*h(2198)=4015 */ {2198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4015_l1}, +/*h(6379)=4016 */ {6379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4016_l1}, +/*h(3795)=4017 */ {3795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4017_l1}, +/*h(7976)=4018 */ {7976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4018_l1}, +/*h(1211)=4019 */ {1211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4019_l1}, +/*h(16338)=4020 */ {16338, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4020_l1}, +/*h(2808)=4021 */ {2808, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11170)=4023 */ {11170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4023_l1}, +/*h(15351)=4024 */ {15351, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4024_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6002)=4026 */ {6002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4026_l1}, +/*h(10183)=4027 */ {10183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(834)=4030 */ {834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4030_l1}, +/*h(5015)=4031 */ {5015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4031_l1}, +/*h(13377)=4032 */ {13377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4032_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10793)=4034 */ {10793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4034_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8209)=4036 */ {8209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4036_l1}, +/*h(12390)=4037 */ {12390, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4037_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13987)=4039 */ {13987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4039_l1}, +/*h(7222)=4040 */ {7222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4040_l1}, +/*h(11403)=4041 */ {11403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4041_l1}, +/*h(8819)=4042 */ {8819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4042_l1}, +/*h(2054)=4043 */ {2054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4043_l1}, +/*h(6235)=4044 */ {6235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4044_l1}, +/*h(10416)=4045 */ {10416, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4045_l1}, +/*h(3651)=4046 */ {3651, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4046_l1}, +/*h(1067)=4047 */ {1067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4047_l1}, +/*h(16194)=4048 */ {16194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4048_l1}, +/*h(9429)=4049 */ {9429, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4049_l1}, +/*h(2664)=4050 */ {2664, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4050_l1}, +/*h(80)=4051 */ {80, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4051_l1}, +/*h(11026)=4052 */ {11026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4052_l1}, +/*h(15207)=4053 */ {15207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4053_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5858)=4055 */ {5858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4055_l1}, +/*h(3274)=4056 */ {3274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4056_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(690)=4058 */ {690, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4058_l1}, +/*h(4871)=4059 */ {4871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4059_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13233)=4061 */ {13233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8065)=4064 */ {8065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4064_l1}, +/*h(12246)=4065 */ {12246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4065_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2897)=4067 */ {2897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4067_l1}, +/*h(7078)=4068 */ {7078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4068_l1}, +/*h(11259)=4069 */ {11259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4069_l1}, +/*h(15440)=4070 */ {15440, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4070_l1}, +/*h(1910)=4071 */ {1910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4071_l1}, +/*h(6091)=4072 */ {6091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4072_l1}, +/*h(10272)=4073 */ {10272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4073_l1}, +/*h(14453)=4074 */ {14453, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4074_l1}, +/*h(7688)=4075 */ {7688, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4075_l1}, +/*h(923)=4076 */ {923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4076_l1}, +/*h(16050)=4077 */ {16050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4077_l1}, +/*h(13466)=4078 */ {13466, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4078_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10882)=4080 */ {10882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4080_l1}, +/*h(15063)=4081 */ {15063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4081_l1}, +/*h(8298)=4082 */ {8298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4082_l1}, +/*h(5714)=4083 */ {5714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4083_l1}, +/*h(9895)=4084 */ {9895, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4084_l1}, +/*h(3130)=4085 */ {3130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4085_l1}, +/*h(546)=4086 */ {546, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4086_l1}, +/*h(4727)=4087 */ {4727, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4087_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13089)=4089 */ {13089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4089_l1}, +/*h(6324)=4090 */ {6324, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4090_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7921)=4092 */ {7921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4092_l1}, +/*h(12102)=4093 */ {12102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4093_l1}, +/*h(16283)=4094 */ {16283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4094_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2753)=4096 */ {2753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4096_l1}, +/*h(6934)=4097 */ {6934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4097_l1}, +/*h(11115)=4098 */ {11115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4098_l1}, +/*h(15296)=4099 */ {15296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4099_l1}, +/*h(1766)=4100 */ {1766, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4100_l1}, +/*h(5947)=4101 */ {5947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4101_l1}, +/*h(10128)=4102 */ {10128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4102_l1}, +/*h(14309)=4103 */ {14309, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4103_l1}, +/*h(779)=4104 */ {779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4104_l1}, +/*h(15906)=4105 */ {15906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4105_l1}, +/*h(9141)=4106 */ {9141, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4106_l1}, +/*h(13322)=4107 */ {13322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14919)=4109 */ {14919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4109_l1}, +/*h(8154)=4110 */ {8154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2986)=4113 */ {2986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11348)=4115 */ {11348, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4115_l1}, +/*h(15529)=4116 */ {15529, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12945)=4118 */ {12945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4118_l1}, +/*h(10361)=4119 */ {10361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7777)=4121 */ {7777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4121_l1}, +/*h(11958)=4122 */ {11958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4122_l1}, +/*h(16139)=4123 */ {16139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4123_l1}, +/*h(13555)=4124 */ {13555, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4124_l1}, +/*h(6790)=4125 */ {6790, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4125_l1}, +/*h(10971)=4126 */ {10971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4126_l1}, +/*h(15152)=4127 */ {15152, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4127_l1}, +/*h(1622)=4128 */ {1622, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4128_l1}, +/*h(5803)=4129 */ {5803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4129_l1}, +/*h(9984)=4130 */ {9984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4130_l1}, +/*h(3219)=4131 */ {3219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4131_l1}, +/*h(635)=4132 */ {635, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4132_l1}, +/*h(4816)=4133 */ {4816, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4133_l1}, +/*h(8997)=4134 */ {8997, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4134_l1}, +/*h(13178)=4135 */ {13178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8010)=4138 */ {8010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16372)=4140 */ {16372, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2842)=4142 */ {2842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11204)=4144 */ {11204, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4144_l1}, +/*h(15385)=4145 */ {15385, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4145_l1}, +/*h(12801)=4146 */ {12801, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4146_l1}, +/*h(6036)=4147 */ {6036, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4147_l1}, +/*h(10217)=4148 */ {10217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11814)=4150 */ {11814, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4150_l1}, +/*h(15995)=4151 */ {15995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13411)=4153 */ {13411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4153_l1}, +/*h(10827)=4154 */ {10827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4154_l1}, +/*h(15008)=4155 */ {15008, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4155_l1}, +/*h(8243)=4156 */ {8243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4156_l1}, +/*h(12424)=4157 */ {12424, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4157_l1}, +/*h(5659)=4158 */ {5659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4158_l1}, +/*h(3075)=4159 */ {3075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4159_l1}, +/*h(14021)=4160 */ {14021, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4672)=4162 */ {4672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4162_l1}, +/*h(8853)=4163 */ {8853, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4163_l1}, +/*h(13034)=4164 */ {13034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4164_l1}, +/*h(10450)=4165 */ {10450, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4165_l1}, +/*h(3685)=4166 */ {3685, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4166_l1}, +/*h(7866)=4167 */ {7866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4167_l1}, +/*h(5282)=4168 */ {5282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4168_l1}, +/*h(9463)=4169 */ {9463, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4169_l1}, +/*h(2698)=4170 */ {2698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(114)=4172 */ {114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4172_l1}, +/*h(4295)=4173 */ {4295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5892)=4175 */ {5892, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4175_l1}, +/*h(10073)=4176 */ {10073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(724)=4178 */ {724, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4178_l1}, +/*h(4905)=4179 */ {4905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13267)=4181 */ {13267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4181_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8099)=4184 */ {8099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4184_l1}, +/*h(12280)=4185 */ {12280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2931)=4188 */ {2931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4188_l1}, +/*h(7112)=4189 */ {7112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4189_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15474)=4191 */ {15474, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4191_l1}, +/*h(12890)=4192 */ {12890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4192_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10306)=4194 */ {10306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4194_l1}, +/*h(14487)=4195 */ {14487, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5138)=4197 */ {5138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4197_l1}, +/*h(9319)=4198 */ {9319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4198_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10916)=4200 */ {10916, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4200_l1}, +/*h(4151)=4201 */ {4151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4201_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12513)=4203 */ {12513, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4203_l1}, +/*h(5748)=4204 */ {5748, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4204_l1}, +/*h(9929)=4205 */ {9929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4205_l1}, +/*h(7345)=4206 */ {7345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4206_l1}, +/*h(580)=4207 */ {580, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4207_l1}, +/*h(4761)=4208 */ {4761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4208_l1}, +/*h(2177)=4209 */ {2177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4209_l1}, +/*h(13123)=4210 */ {13123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7955)=4213 */ {7955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4213_l1}, +/*h(5371)=4214 */ {5371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4214_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2787)=4216 */ {2787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4216_l1}, +/*h(6968)=4217 */ {6968, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4217_l1}, +/*h(203)=4218 */ {203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4218_l1}, +/*h(15330)=4219 */ {15330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4219_l1}, +/*h(1800)=4220 */ {1800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10162)=4222 */ {10162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4222_l1}, +/*h(14343)=4223 */ {14343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4223_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4994)=4225 */ {4994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4225_l1}, +/*h(9175)=4226 */ {9175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4226_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4007)=4229 */ {4007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4229_l1}, +/*h(14953)=4230 */ {14953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4230_l1}, +/*h(12369)=4231 */ {12369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4231_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9785)=4233 */ {9785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7201)=4235 */ {7201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4235_l1}, +/*h(11382)=4236 */ {11382, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4236_l1}, +/*h(15563)=4237 */ {15563, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4237_l1}, +/*h(12979)=4238 */ {12979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4238_l1}, +/*h(6214)=4239 */ {6214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4239_l1}, +/*h(10395)=4240 */ {10395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4240_l1}, +/*h(7811)=4241 */ {7811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4241_l1}, +/*h(1046)=4242 */ {1046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4242_l1}, +/*h(5227)=4243 */ {5227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4243_l1}, +/*h(2643)=4244 */ {2643, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4244_l1}, +/*h(6824)=4245 */ {6824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4245_l1}, +/*h(59)=4246 */ {59, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4246_l1}, +/*h(15186)=4247 */ {15186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4247_l1}, +/*h(8421)=4248 */ {8421, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4248_l1}, +/*h(1656)=4249 */ {1656, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3253)=4251 */ {3253, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4251_l1}, +/*h(14199)=4252 */ {14199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4850)=4254 */ {4850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4254_l1}, +/*h(9031)=4255 */ {9031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4255_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3863)=4258 */ {3863, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12225)=4260 */ {12225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4260_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7057)=4263 */ {7057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4263_l1}, +/*h(11238)=4264 */ {11238, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4264_l1}, +/*h(15419)=4265 */ {15419, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4265_l1}, +/*h(1889)=4266 */ {1889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4266_l1}, +/*h(6070)=4267 */ {6070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4267_l1}, +/*h(10251)=4268 */ {10251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4268_l1}, +/*h(14432)=4269 */ {14432, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4269_l1}, +/*h(902)=4270 */ {902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4270_l1}, +/*h(5083)=4271 */ {5083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4271_l1}, +/*h(9264)=4272 */ {9264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4272_l1}, +/*h(13445)=4273 */ {13445, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4273_l1}, +/*h(6680)=4274 */ {6680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4274_l1}, +/*h(4096)=4275 */ {4096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4275_l1}, +/*h(15042)=4276 */ {15042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4276_l1}, +/*h(12458)=4277 */ {12458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4277_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9874)=4279 */ {9874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4279_l1}, +/*h(14055)=4280 */ {14055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4280_l1}, +/*h(7290)=4281 */ {7290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4281_l1}, +/*h(4706)=4282 */ {4706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4282_l1}, +/*h(8887)=4283 */ {8887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4283_l1}, +/*h(2122)=4284 */ {2122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4284_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3719)=4286 */ {3719, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12081)=4288 */ {12081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4288_l1}, +/*h(16262)=4289 */ {16262, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4289_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6913)=4291 */ {6913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4291_l1}, +/*h(11094)=4292 */ {11094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4292_l1}, +/*h(15275)=4293 */ {15275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1745)=4295 */ {1745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10107)=4297 */ {10107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4297_l1}, +/*h(14288)=4298 */ {14288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4298_l1}, +/*h(758)=4299 */ {758, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4299_l1}, +/*h(4939)=4300 */ {4939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4300_l1}, +/*h(9120)=4301 */ {9120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4301_l1}, +/*h(13301)=4302 */ {13301, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14898)=4304 */ {14898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4304_l1}, +/*h(8133)=4305 */ {8133, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4305_l1}, +/*h(12314)=4306 */ {12314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4306_l1}, +/*h(9730)=4307 */ {9730, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4307_l1}, +/*h(13911)=4308 */ {13911, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4308_l1}, +/*h(7146)=4309 */ {7146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15508)=4311 */ {15508, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4311_l1}, +/*h(1978)=4312 */ {1978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10340)=4314 */ {10340, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4314_l1}, +/*h(14521)=4315 */ {14521, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11937)=4317 */ {11937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4317_l1}, +/*h(16118)=4318 */ {16118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6769)=4320 */ {6769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4320_l1}, +/*h(10950)=4321 */ {10950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4321_l1}, +/*h(15131)=4322 */ {15131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4322_l1}, +/*h(1601)=4323 */ {1601, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4323_l1}, +/*h(5782)=4324 */ {5782, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4324_l1}, +/*h(9963)=4325 */ {9963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4325_l1}, +/*h(14144)=4326 */ {14144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4326_l1}, +/*h(7379)=4327 */ {7379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4327_l1}, +/*h(4795)=4328 */ {4795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4328_l1}, +/*h(8976)=4329 */ {8976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4329_l1}, +/*h(2211)=4330 */ {2211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4330_l1}, +/*h(6392)=4331 */ {6392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4331_l1}, +/*h(3808)=4332 */ {3808, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4332_l1}, +/*h(7989)=4333 */ {7989, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4333_l1}, +/*h(12170)=4334 */ {12170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4334_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2821)=4336 */ {2821, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4336_l1}, +/*h(7002)=4337 */ {7002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4337_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15364)=4339 */ {15364, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4339_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1834)=4341 */ {1834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4341_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10196)=4343 */ {10196, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4343_l1}, +/*h(14377)=4344 */ {14377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4344_l1}, +/*h(11793)=4345 */ {11793, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4345_l1}, +/*h(15974)=4346 */ {15974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4346_l1}, +/*h(9209)=4347 */ {9209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10806)=4349 */ {10806, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4349_l1}, +/*h(14987)=4350 */ {14987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4350_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12403)=4352 */ {12403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4352_l1}, +/*h(9819)=4353 */ {9819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4353_l1}, +/*h(14000)=4354 */ {14000, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4354_l1}, +/*h(7235)=4355 */ {7235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4355_l1}, +/*h(11416)=4356 */ {11416, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4356_l1}, +/*h(4651)=4357 */ {4651, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4357_l1}, +/*h(2067)=4358 */ {2067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4358_l1}, +/*h(13013)=4359 */ {13013, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3664)=4361 */ {3664, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4361_l1}, +/*h(7845)=4362 */ {7845, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4362_l1}, +/*h(12026)=4363 */ {12026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4363_l1}, +/*h(9442)=4364 */ {9442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4364_l1}, +/*h(2677)=4365 */ {2677, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4365_l1}, +/*h(6858)=4366 */ {6858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4366_l1}, +/*h(4274)=4367 */ {4274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4367_l1}, +/*h(15220)=4368 */ {15220, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4368_l1}, +/*h(1690)=4369 */ {1690, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4369_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10052)=4371 */ {10052, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4371_l1}, +/*h(3287)=4372 */ {3287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4884)=4374 */ {4884, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4374_l1}, +/*h(9065)=4375 */ {9065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4375_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3897)=4378 */ {3897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12259)=4380 */ {12259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7091)=4383 */ {7091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4383_l1}, +/*h(11272)=4384 */ {11272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1923)=4387 */ {1923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4387_l1}, +/*h(6104)=4388 */ {6104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14466)=4390 */ {14466, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4390_l1}, +/*h(11882)=4391 */ {11882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4391_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9298)=4393 */ {9298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4393_l1}, +/*h(6714)=4394 */ {6714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4130)=4396 */ {4130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4396_l1}, +/*h(8311)=4397 */ {8311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9908)=4399 */ {9908, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4399_l1}, +/*h(3143)=4400 */ {3143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11505)=4402 */ {11505, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4402_l1}, +/*h(4740)=4403 */ {4740, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4403_l1}, +/*h(8921)=4404 */ {8921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4404_l1}, +/*h(6337)=4405 */ {6337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3753)=4407 */ {3753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4407_l1}, +/*h(1169)=4408 */ {1169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4408_l1}, +/*h(12115)=4409 */ {12115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4409_l1}, +/*h(16296)=4410 */ {16296, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6947)=4412 */ {6947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4412_l1}, +/*h(11128)=4413 */ {11128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4413_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1779)=4415 */ {1779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4415_l1}, +/*h(5960)=4416 */ {5960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4416_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14322)=4418 */ {14322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4418_l1}, +/*h(792)=4419 */ {792, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9154)=4421 */ {9154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4421_l1}, +/*h(13335)=4422 */ {13335, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4422_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3986)=4424 */ {3986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4424_l1}, +/*h(8167)=4425 */ {8167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2999)=4428 */ {2999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4428_l1}, +/*h(13945)=4429 */ {13945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4429_l1}, +/*h(11361)=4430 */ {11361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4430_l1}, +/*h(15542)=4431 */ {15542, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4431_l1}, +/*h(8777)=4432 */ {8777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4432_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6193)=4434 */ {6193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4434_l1}, +/*h(10374)=4435 */ {10374, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4435_l1}, +/*h(14555)=4436 */ {14555, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4436_l1}, +/*h(11971)=4437 */ {11971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4437_l1}, +/*h(5206)=4438 */ {5206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4438_l1}, +/*h(9387)=4439 */ {9387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4439_l1}, +/*h(6803)=4440 */ {6803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4440_l1}, +/*h(38)=4441 */ {38, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4441_l1}, +/*h(4219)=4442 */ {4219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4442_l1}, +/*h(1635)=4443 */ {1635, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4443_l1}, +/*h(5816)=4444 */ {5816, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4444_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14178)=4446 */ {14178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4446_l1}, +/*h(7413)=4447 */ {7413, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4447_l1}, +/*h(648)=4448 */ {648, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9010)=4450 */ {9010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4450_l1}, +/*h(13191)=4451 */ {13191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4451_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3842)=4453 */ {3842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4453_l1}, +/*h(8023)=4454 */ {8023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2855)=4457 */ {2855, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4457_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11217)=4459 */ {11217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4459_l1}, +/*h(15398)=4460 */ {15398, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4460_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6049)=4462 */ {6049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4462_l1}, +/*h(10230)=4463 */ {10230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4463_l1}, +/*h(14411)=4464 */ {14411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4464_l1}, +/*h(881)=4465 */ {881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4465_l1}, +/*h(5062)=4466 */ {5062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4466_l1}, +/*h(9243)=4467 */ {9243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4467_l1}, +/*h(13424)=4468 */ {13424, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4468_l1}, +/*h(6659)=4469 */ {6659, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4469_l1}, +/*h(4075)=4470 */ {4075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4470_l1}, +/*h(8256)=4471 */ {8256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4471_l1}, +/*h(12437)=4472 */ {12437, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4472_l1}, +/*h(5672)=4473 */ {5672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4473_l1}, +/*h(3088)=4474 */ {3088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4474_l1}, +/*h(14034)=4475 */ {14034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4475_l1}, +/*h(11450)=4476 */ {11450, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8866)=4478 */ {8866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4478_l1}, +/*h(13047)=4479 */ {13047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4479_l1}, +/*h(6282)=4480 */ {6282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4480_l1}, +/*h(3698)=4481 */ {3698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4481_l1}, +/*h(7879)=4482 */ {7879, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4482_l1}, +/*h(1114)=4483 */ {1114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4483_l1}, +/*h(16241)=4484 */ {16241, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4484_l1}, +/*h(2711)=4485 */ {2711, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4485_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11073)=4487 */ {11073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4487_l1}, +/*h(15254)=4488 */ {15254, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4488_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5905)=4490 */ {5905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4490_l1}, +/*h(10086)=4491 */ {10086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4491_l1}, +/*h(14267)=4492 */ {14267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4492_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(737)=4494 */ {737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4494_l1}, +/*h(4918)=4495 */ {4918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4495_l1}, +/*h(9099)=4496 */ {9099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4496_l1}, +/*h(13280)=4497 */ {13280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4497_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3931)=4499 */ {3931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4499_l1}, +/*h(8112)=4500 */ {8112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4500_l1}, +/*h(12293)=4501 */ {12293, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4501_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13890)=4503 */ {13890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4503_l1}, +/*h(7125)=4504 */ {7125, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4504_l1}, +/*h(11306)=4505 */ {11306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4505_l1}, +/*h(8722)=4506 */ {8722, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4506_l1}, +/*h(12903)=4507 */ {12903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4507_l1}, +/*h(6138)=4508 */ {6138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14500)=4510 */ {14500, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4510_l1}, +/*h(970)=4511 */ {970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4511_l1}, +/*h(16097)=4512 */ {16097, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4512_l1}, +/*h(9332)=4513 */ {9332, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4513_l1}, +/*h(2567)=4514 */ {2567, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4514_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10929)=4516 */ {10929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4516_l1}, +/*h(15110)=4517 */ {15110, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5761)=4519 */ {5761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4519_l1}, +/*h(9942)=4520 */ {9942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4520_l1}, +/*h(14123)=4521 */ {14123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4521_l1}, +/*h(593)=4522 */ {593, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4522_l1}, +/*h(4774)=4523 */ {4774, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4523_l1}, +/*h(8955)=4524 */ {8955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4524_l1}, +/*h(13136)=4525 */ {13136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4525_l1}, +/*h(6371)=4526 */ {6371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4526_l1}, +/*h(3787)=4527 */ {3787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4527_l1}, +/*h(7968)=4528 */ {7968, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4528_l1}, +/*h(1203)=4529 */ {1203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4529_l1}, +/*h(16330)=4530 */ {16330, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4530_l1}, +/*h(2800)=4531 */ {2800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4531_l1}, +/*h(6981)=4532 */ {6981, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4532_l1}, +/*h(11162)=4533 */ {11162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4533_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1813)=4535 */ {1813, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4535_l1}, +/*h(5994)=4536 */ {5994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4536_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14356)=4538 */ {14356, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(826)=4540 */ {826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4540_l1}, +/*h(15953)=4541 */ {15953, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4541_l1}, +/*h(13369)=4542 */ {13369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10785)=4544 */ {10785, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4544_l1}, +/*h(14966)=4545 */ {14966, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4545_l1}, +/*h(8201)=4546 */ {8201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9798)=4548 */ {9798, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4548_l1}, +/*h(13979)=4549 */ {13979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4630)=4551 */ {4630, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4551_l1}, +/*h(8811)=4552 */ {8811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4552_l1}, +/*h(12992)=4553 */ {12992, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4553_l1}, +/*h(6227)=4554 */ {6227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4554_l1}, +/*h(10408)=4555 */ {10408, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4555_l1}, +/*h(3643)=4556 */ {3643, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4556_l1}, +/*h(1059)=4557 */ {1059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4557_l1}, +/*h(16186)=4558 */ {16186, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2656)=4560 */ {2656, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4560_l1}, +/*h(6837)=4561 */ {6837, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4561_l1}, +/*h(11018)=4562 */ {11018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4562_l1}, +/*h(8434)=4563 */ {8434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4563_l1}, +/*h(1669)=4564 */ {1669, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4564_l1}, +/*h(5850)=4565 */ {5850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4565_l1}, +/*h(3266)=4566 */ {3266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4566_l1}, +/*h(14212)=4567 */ {14212, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4567_l1}, +/*h(682)=4568 */ {682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4568_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9044)=4570 */ {9044, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4570_l1}, +/*h(2279)=4571 */ {2279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4571_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3876)=4573 */ {3876, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4573_l1}, +/*h(8057)=4574 */ {8057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2889)=4577 */ {2889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4577_l1}, +/*h(13835)=4578 */ {13835, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4578_l1}, +/*h(11251)=4579 */ {11251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4579_l1}, +/*h(15432)=4580 */ {15432, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4580_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6083)=4582 */ {6083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4582_l1}, +/*h(10264)=4583 */ {10264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4583_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7680)=4585 */ {7680, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4585_l1}, +/*h(915)=4586 */ {915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4586_l1}, +/*h(16042)=4587 */ {16042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4587_l1}, +/*h(13458)=4588 */ {13458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4588_l1}, +/*h(6693)=4589 */ {6693, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4589_l1}, +/*h(10874)=4590 */ {10874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4590_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8290)=4592 */ {8290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4592_l1}, +/*h(12471)=4593 */ {12471, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4593_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3122)=4595 */ {3122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4595_l1}, +/*h(538)=4596 */ {538, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4596_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8900)=4598 */ {8900, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4598_l1}, +/*h(2135)=4599 */ {2135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4599_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3732)=4602 */ {3732, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4602_l1}, +/*h(7913)=4603 */ {7913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4603_l1}, +/*h(16275)=4604 */ {16275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4604_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2745)=4606 */ {2745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4606_l1}, +/*h(161)=4607 */ {161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4607_l1}, +/*h(11107)=4608 */ {11107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4608_l1}, +/*h(15288)=4609 */ {15288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4609_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10120)=4612 */ {10120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4612_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(771)=4614 */ {771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4614_l1}, +/*h(15898)=4615 */ {15898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13314)=4617 */ {13314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4617_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8146)=4620 */ {8146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4620_l1}, +/*h(12327)=4621 */ {12327, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4621_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2978)=4623 */ {2978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4623_l1}, +/*h(7159)=4624 */ {7159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15521)=4626 */ {15521, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4626_l1}, +/*h(1991)=4627 */ {1991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4627_l1}, +/*h(12937)=4628 */ {12937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4628_l1}, +/*h(10353)=4629 */ {10353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4629_l1}, +/*h(14534)=4630 */ {14534, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4630_l1}, +/*h(7769)=4631 */ {7769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4631_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16131)=4633 */ {16131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4633_l1}, +/*h(9366)=4634 */ {9366, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4634_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10963)=4636 */ {10963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4636_l1}, +/*h(4198)=4637 */ {4198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4637_l1}, +/*h(8379)=4638 */ {8379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4638_l1}, +/*h(5795)=4639 */ {5795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4639_l1}, +/*h(9976)=4640 */ {9976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4640_l1}, +/*h(3211)=4641 */ {3211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4641_l1}, +/*h(627)=4642 */ {627, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4642_l1}, +/*h(4808)=4643 */ {4808, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4643_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13170)=4645 */ {13170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4645_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12183)=4649 */ {12183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4649_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2834)=4652 */ {2834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4652_l1}, +/*h(7015)=4653 */ {7015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4653_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15377)=4655 */ {15377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10209)=4658 */ {10209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4658_l1}, +/*h(14390)=4659 */ {14390, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4659_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15987)=4661 */ {15987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4661_l1}, +/*h(9222)=4662 */ {9222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4662_l1}, +/*h(13403)=4663 */ {13403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4663_l1}, +/*h(10819)=4664 */ {10819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4664_l1}, +/*h(4054)=4665 */ {4054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4665_l1}, +/*h(8235)=4666 */ {8235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4666_l1}, +/*h(12416)=4667 */ {12416, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4667_l1}, +/*h(5651)=4668 */ {5651, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4668_l1}, +/*h(3067)=4669 */ {3067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4669_l1}, +/*h(7248)=4670 */ {7248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4670_l1}, +/*h(11429)=4671 */ {11429, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4671_l1}, +/*h(15610)=4672 */ {15610, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4672_l1}, +/*h(2080)=4673 */ {2080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4673_l1}, +/*h(13026)=4674 */ {13026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4674_l1}, +/*h(10442)=4675 */ {10442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4675_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7858)=4677 */ {7858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4677_l1}, +/*h(12039)=4678 */ {12039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4678_l1}, +/*h(5274)=4679 */ {5274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4679_l1}, +/*h(2690)=4680 */ {2690, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4680_l1}, +/*h(6871)=4681 */ {6871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4681_l1}, +/*h(106)=4682 */ {106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4682_l1}, +/*h(15233)=4683 */ {15233, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4683_l1}, +/*h(1703)=4684 */ {1703, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10065)=4686 */ {10065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4686_l1}, +/*h(14246)=4687 */ {14246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4687_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4897)=4689 */ {4897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4689_l1}, +/*h(9078)=4690 */ {9078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4690_l1}, +/*h(13259)=4691 */ {13259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4691_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8091)=4694 */ {8091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4694_l1}, +/*h(12272)=4695 */ {12272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4695_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2923)=4698 */ {2923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4698_l1}, +/*h(7104)=4699 */ {7104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4699_l1}, +/*h(11285)=4700 */ {11285, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4700_l1}, +/*h(15466)=4701 */ {15466, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4701_l1}, +/*h(12882)=4702 */ {12882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4702_l1}, +/*h(6117)=4703 */ {6117, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4703_l1}, +/*h(10298)=4704 */ {10298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4704_l1}, +/*h(7714)=4705 */ {7714, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4705_l1}, +/*h(11895)=4706 */ {11895, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4706_l1}, +/*h(5130)=4707 */ {5130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4707_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6727)=4709 */ {6727, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4709_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15089)=4711 */ {15089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4711_l1}, +/*h(8324)=4712 */ {8324, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4712_l1}, +/*h(1559)=4713 */ {1559, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4713_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9921)=4715 */ {9921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4715_l1}, +/*h(14102)=4716 */ {14102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4716_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4753)=4718 */ {4753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4718_l1}, +/*h(8934)=4719 */ {8934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4719_l1}, +/*h(13115)=4720 */ {13115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4720_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3766)=4722 */ {3766, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4722_l1}, +/*h(7947)=4723 */ {7947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4723_l1}, +/*h(12128)=4724 */ {12128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4724_l1}, +/*h(5363)=4725 */ {5363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4725_l1}, +/*h(2779)=4726 */ {2779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4726_l1}, +/*h(6960)=4727 */ {6960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4727_l1}, +/*h(195)=4728 */ {195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4728_l1}, +/*h(15322)=4729 */ {15322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4729_l1}, +/*h(1792)=4730 */ {1792, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4730_l1}, +/*h(5973)=4731 */ {5973, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4731_l1}, +/*h(10154)=4732 */ {10154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4732_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(805)=4734 */ {805, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4734_l1}, +/*h(4986)=4735 */ {4986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13348)=4737 */ {13348, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4737_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14945)=4740 */ {14945, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4740_l1}, +/*h(12361)=4741 */ {12361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4741_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9777)=4743 */ {9777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4743_l1}, +/*h(13958)=4744 */ {13958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4744_l1}, +/*h(7193)=4745 */ {7193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4745_l1}, +/*h(4609)=4746 */ {4609, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4746_l1}, +/*h(8790)=4747 */ {8790, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4747_l1}, +/*h(12971)=4748 */ {12971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4748_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10387)=4750 */ {10387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4750_l1}, +/*h(7803)=4751 */ {7803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4751_l1}, +/*h(11984)=4752 */ {11984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4752_l1}, +/*h(5219)=4753 */ {5219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4753_l1}, +/*h(9400)=4754 */ {9400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4754_l1}, +/*h(2635)=4755 */ {2635, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4755_l1}, +/*h(51)=4756 */ {51, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4756_l1}, +/*h(15178)=4757 */ {15178, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4757_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1648)=4759 */ {1648, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4759_l1}, +/*h(5829)=4760 */ {5829, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4760_l1}, +/*h(10010)=4761 */ {10010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4761_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(661)=4763 */ {661, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4763_l1}, +/*h(4842)=4764 */ {4842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4764_l1}, +/*h(2258)=4765 */ {2258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4765_l1}, +/*h(13204)=4766 */ {13204, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4766_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8036)=4769 */ {8036, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4769_l1}, +/*h(1271)=4770 */ {1271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4770_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2868)=4772 */ {2868, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4772_l1}, +/*h(7049)=4773 */ {7049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15411)=4775 */ {15411, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4775_l1}, +/*h(1881)=4776 */ {1881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4776_l1}, +/*h(12827)=4777 */ {12827, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4777_l1}, +/*h(10243)=4778 */ {10243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4778_l1}, +/*h(14424)=4779 */ {14424, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4779_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5075)=4781 */ {5075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4781_l1}, +/*h(16021)=4782 */ {16021, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4782_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6672)=4784 */ {6672, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4784_l1}, +/*h(10853)=4785 */ {10853, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4785_l1}, +/*h(15034)=4786 */ {15034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4786_l1}, +/*h(12450)=4787 */ {12450, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4787_l1}, +/*h(5685)=4788 */ {5685, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4788_l1}, +/*h(9866)=4789 */ {9866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4789_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7282)=4791 */ {7282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4791_l1}, +/*h(4698)=4792 */ {4698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4792_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2114)=4794 */ {2114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4794_l1}, +/*h(6295)=4795 */ {6295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4795_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7892)=4797 */ {7892, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4797_l1}, +/*h(1127)=4798 */ {1127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4798_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6905)=4801 */ {6905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4801_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15267)=4803 */ {15267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1737)=4805 */ {1737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4805_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10099)=4807 */ {10099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4807_l1}, +/*h(14280)=4808 */ {14280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4808_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4931)=4810 */ {4931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4810_l1}, +/*h(9112)=4811 */ {9112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4811_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14890)=4814 */ {14890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4814_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12306)=4816 */ {12306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4816_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7138)=4819 */ {7138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4819_l1}, +/*h(11319)=4820 */ {11319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1970)=4822 */ {1970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4822_l1}, +/*h(6151)=4823 */ {6151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4823_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14513)=4825 */ {14513, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4825_l1}, +/*h(983)=4826 */ {983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4826_l1}, +/*h(11929)=4827 */ {11929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4827_l1}, +/*h(9345)=4828 */ {9345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4828_l1}, +/*h(13526)=4829 */ {13526, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4829_l1}, +/*h(6761)=4830 */ {6761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4830_l1}, +/*h(4177)=4831 */ {4177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4831_l1}, +/*h(15123)=4832 */ {15123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4832_l1}, +/*h(12539)=4833 */ {12539, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4833_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9955)=4835 */ {9955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4835_l1}, +/*h(3190)=4836 */ {3190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4836_l1}, +/*h(7371)=4837 */ {7371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4837_l1}, +/*h(4787)=4838 */ {4787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4838_l1}, +/*h(8968)=4839 */ {8968, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4839_l1}, +/*h(2203)=4840 */ {2203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4840_l1}, +/*h(6384)=4841 */ {6384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4841_l1}, +/*h(3800)=4842 */ {3800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4842_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12162)=4844 */ {12162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4844_l1}, +/*h(16343)=4845 */ {16343, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4845_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6994)=4847 */ {6994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4847_l1}, +/*h(11175)=4848 */ {11175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4848_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6007)=4852 */ {6007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4852_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14369)=4854 */ {14369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4854_l1}, +/*h(839)=4855 */ {839, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4855_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9201)=4857 */ {9201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4857_l1}, +/*h(13382)=4858 */ {13382, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4858_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14979)=4860 */ {14979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4860_l1}, +/*h(8214)=4861 */ {8214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4861_l1}, +/*h(12395)=4862 */ {12395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4862_l1}, +/*h(9811)=4863 */ {9811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4863_l1}, +/*h(3046)=4864 */ {3046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4864_l1}, +/*h(7227)=4865 */ {7227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4865_l1}, +/*h(11408)=4866 */ {11408, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4866_l1}, +/*h(4643)=4867 */ {4643, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4867_l1}, +/*h(2059)=4868 */ {2059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4868_l1}, +/*h(6240)=4869 */ {6240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4869_l1}, +/*h(10421)=4870 */ {10421, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4870_l1}, +/*h(3656)=4871 */ {3656, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4871_l1}, +/*h(1072)=4872 */ {1072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4872_l1}, +/*h(12018)=4873 */ {12018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4873_l1}, +/*h(16199)=4874 */ {16199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4874_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6850)=4876 */ {6850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4876_l1}, +/*h(11031)=4877 */ {11031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4877_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1682)=4879 */ {1682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4879_l1}, +/*h(5863)=4880 */ {5863, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14225)=4882 */ {14225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4882_l1}, +/*h(695)=4883 */ {695, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4883_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9057)=4885 */ {9057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4885_l1}, +/*h(13238)=4886 */ {13238, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4886_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3889)=4888 */ {3889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4888_l1}, +/*h(8070)=4889 */ {8070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4889_l1}, +/*h(12251)=4890 */ {12251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4890_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2902)=4892 */ {2902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4892_l1}, +/*h(7083)=4893 */ {7083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4893_l1}, +/*h(11264)=4894 */ {11264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4894_l1}, +/*h(15445)=4895 */ {15445, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4895_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1915)=4897 */ {1915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4897_l1}, +/*h(6096)=4898 */ {6096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4898_l1}, +/*h(10277)=4899 */ {10277, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4899_l1}, +/*h(14458)=4900 */ {14458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4900_l1}, +/*h(11874)=4901 */ {11874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4901_l1}, +/*h(16055)=4902 */ {16055, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4902_l1}, +/*h(9290)=4903 */ {9290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4903_l1}, +/*h(6706)=4904 */ {6706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4904_l1}, +/*h(10887)=4905 */ {10887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4905_l1}, +/*h(4122)=4906 */ {4122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4906_l1}, +/*h(1538)=4907 */ {1538, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4907_l1}, +/*h(5719)=4908 */ {5719, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4908_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14081)=4910 */ {14081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4910_l1}, +/*h(7316)=4911 */ {7316, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4911_l1}, +/*h(551)=4912 */ {551, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4912_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8913)=4914 */ {8913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4914_l1}, +/*h(13094)=4915 */ {13094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3745)=4917 */ {3745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4917_l1}, +/*h(7926)=4918 */ {7926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4918_l1}, +/*h(12107)=4919 */ {12107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4919_l1}, +/*h(16288)=4920 */ {16288, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4920_l1}, +/*h(2758)=4921 */ {2758, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4921_l1}, +/*h(6939)=4922 */ {6939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4922_l1}, +/*h(11120)=4923 */ {11120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4923_l1}, +/*h(15301)=4924 */ {15301, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4924_l1}, +/*h(1771)=4925 */ {1771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4925_l1}, +/*h(5952)=4926 */ {5952, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4926_l1}, +/*h(10133)=4927 */ {10133, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4927_l1}, +/*h(14314)=4928 */ {14314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4928_l1}, +/*h(784)=4929 */ {784, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4929_l1}, +/*h(4965)=4930 */ {4965, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4930_l1}, +/*h(9146)=4931 */ {9146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4931_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3978)=4934 */ {3978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4934_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12340)=4936 */ {12340, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4936_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13937)=4939 */ {13937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4939_l1}, +/*h(11353)=4940 */ {11353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4940_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8769)=4942 */ {8769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4942_l1}, +/*h(12950)=4943 */ {12950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4943_l1}, +/*h(6185)=4944 */ {6185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4944_l1}, +/*h(3601)=4945 */ {3601, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4945_l1}, +/*h(14547)=4946 */ {14547, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4946_l1}, +/*h(11963)=4947 */ {11963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4947_l1}, +/*h(16144)=4948 */ {16144, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4948_l1}, +/*h(2614)=4949 */ {2614, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4949_l1}, +/*h(6795)=4950 */ {6795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4950_l1}, +/*h(10976)=4951 */ {10976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4951_l1}, +/*h(4211)=4952 */ {4211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4952_l1}, +/*h(1627)=4953 */ {1627, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4953_l1}, +/*h(5808)=4954 */ {5808, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4954_l1}, +/*h(9989)=4955 */ {9989, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4955_l1}, +/*h(14170)=4956 */ {14170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4956_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(640)=4958 */ {640, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4958_l1}, +/*h(4821)=4959 */ {4821, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4959_l1}, +/*h(9002)=4960 */ {9002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4960_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3834)=4963 */ {3834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4963_l1}, +/*h(1250)=4964 */ {1250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4964_l1}, +/*h(12196)=4965 */ {12196, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4965_l1}, +/*h(16377)=4966 */ {16377, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7028)=4968 */ {7028, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4968_l1}, +/*h(11209)=4969 */ {11209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4969_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12806)=4971 */ {12806, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4971_l1}, +/*h(6041)=4972 */ {6041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4972_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14403)=4974 */ {14403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4974_l1}, +/*h(873)=4975 */ {873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4975_l1}, +/*h(11819)=4976 */ {11819, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4976_l1}, +/*h(9235)=4977 */ {9235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4977_l1}, +/*h(13416)=4978 */ {13416, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4978_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4067)=4980 */ {4067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4980_l1}, +/*h(15013)=4981 */ {15013, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4981_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5664)=4983 */ {5664, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4983_l1}, +/*h(9845)=4984 */ {9845, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4984_l1}, +/*h(14026)=4985 */ {14026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4985_l1}, +/*h(11442)=4986 */ {11442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4986_l1}, +/*h(4677)=4987 */ {4677, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4987_l1}, +/*h(8858)=4988 */ {8858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4988_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6274)=4990 */ {6274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4990_l1}, +/*h(10455)=4991 */ {10455, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4991_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1106)=4993 */ {1106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4993_l1}, +/*h(5287)=4994 */ {5287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4994_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6884)=4996 */ {6884, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4996_l1}, +/*h(119)=4997 */ {119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4997_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1716)=4999 */ {1716, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_4999_l1}, +/*h(5897)=5000 */ {5897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5000_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14259)=5002 */ {14259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5002_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(729)=5004 */ {729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5004_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9091)=5006 */ {9091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5006_l1}, +/*h(13272)=5007 */ {13272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5007_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3923)=5009 */ {3923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5009_l1}, +/*h(8104)=5010 */ {8104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5010_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13882)=5013 */ {13882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5013_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11298)=5015 */ {11298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5015_l1}, +/*h(15479)=5016 */ {15479, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5016_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6130)=5018 */ {6130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5018_l1}, +/*h(10311)=5019 */ {10311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5019_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(962)=5021 */ {962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5021_l1}, +/*h(5143)=5022 */ {5143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5022_l1}, +/*h(16089)=5023 */ {16089, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5023_l1}, +/*h(13505)=5024 */ {13505, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5024_l1}, +/*h(6740)=5025 */ {6740, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5025_l1}, +/*h(10921)=5026 */ {10921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5026_l1}, +/*h(8337)=5027 */ {8337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5027_l1}, +/*h(12518)=5028 */ {12518, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5028_l1}, +/*h(5753)=5029 */ {5753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5029_l1}, +/*h(3169)=5030 */ {3169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5030_l1}, +/*h(7350)=5031 */ {7350, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5031_l1}, +/*h(585)=5032 */ {585, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5032_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8947)=5034 */ {8947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5034_l1}, +/*h(2182)=5035 */ {2182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5035_l1}, +/*h(6363)=5036 */ {6363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5036_l1}, +/*h(3779)=5037 */ {3779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5037_l1}, +/*h(7960)=5038 */ {7960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5038_l1}, +/*h(1195)=5039 */ {1195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5039_l1}, +/*h(16322)=5040 */ {16322, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5040_l1}, +/*h(2792)=5041 */ {2792, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5041_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11154)=5043 */ {11154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5043_l1}, +/*h(15335)=5044 */ {15335, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5044_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5986)=5046 */ {5986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5046_l1}, +/*h(10167)=5047 */ {10167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(818)=5050 */ {818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5050_l1}, +/*h(4999)=5051 */ {4999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5051_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13361)=5053 */ {13361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5053_l1}, +/*h(10777)=5054 */ {10777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5054_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8193)=5056 */ {8193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5056_l1}, +/*h(12374)=5057 */ {12374, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5057_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13971)=5059 */ {13971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5059_l1}, +/*h(7206)=5060 */ {7206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5060_l1}, +/*h(11387)=5061 */ {11387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5061_l1}, +/*h(8803)=5062 */ {8803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5062_l1}, +/*h(2038)=5063 */ {2038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5063_l1}, +/*h(6219)=5064 */ {6219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5064_l1}, +/*h(10400)=5065 */ {10400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5065_l1}, +/*h(3635)=5066 */ {3635, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5066_l1}, +/*h(1051)=5067 */ {1051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5067_l1}, +/*h(5232)=5068 */ {5232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5068_l1}, +/*h(9413)=5069 */ {9413, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5069_l1}, +/*h(2648)=5070 */ {2648, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5070_l1}, +/*h(64)=5071 */ {64, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5071_l1}, +/*h(11010)=5072 */ {11010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5072_l1}, +/*h(15191)=5073 */ {15191, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5073_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5842)=5075 */ {5842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5075_l1}, +/*h(3258)=5076 */ {3258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5076_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(674)=5078 */ {674, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5078_l1}, +/*h(4855)=5079 */ {4855, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5079_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13217)=5081 */ {13217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5081_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8049)=5084 */ {8049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5084_l1}, +/*h(12230)=5085 */ {12230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5085_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2881)=5087 */ {2881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5087_l1}, +/*h(7062)=5088 */ {7062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5088_l1}, +/*h(11243)=5089 */ {11243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5089_l1}, +/*h(15424)=5090 */ {15424, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5090_l1}, +/*h(1894)=5091 */ {1894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5091_l1}, +/*h(6075)=5092 */ {6075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5092_l1}, +/*h(10256)=5093 */ {10256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5093_l1}, +/*h(14437)=5094 */ {14437, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5094_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(907)=5096 */ {907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5096_l1}, +/*h(16034)=5097 */ {16034, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5097_l1}, +/*h(9269)=5098 */ {9269, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5098_l1}, +/*h(13450)=5099 */ {13450, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5099_l1}, +/*h(10866)=5100 */ {10866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5100_l1}, +/*h(15047)=5101 */ {15047, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5101_l1}, +/*h(8282)=5102 */ {8282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5102_l1}, +/*h(5698)=5103 */ {5698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5103_l1}, +/*h(9879)=5104 */ {9879, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5104_l1}, +/*h(3114)=5105 */ {3114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5105_l1}, +/*h(530)=5106 */ {530, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5106_l1}, +/*h(4711)=5107 */ {4711, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13073)=5109 */ {13073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5109_l1}, +/*h(6308)=5110 */ {6308, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5110_l1}, +/*h(10489)=5111 */ {10489, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7905)=5113 */ {7905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5113_l1}, +/*h(16267)=5114 */ {16267, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5114_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2737)=5116 */ {2737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5116_l1}, +/*h(6918)=5117 */ {6918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5117_l1}, +/*h(11099)=5118 */ {11099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5118_l1}, +/*h(15280)=5119 */ {15280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5119_l1}, +/*h(1750)=5120 */ {1750, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5120_l1}, +/*h(5931)=5121 */ {5931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5121_l1}, +/*h(10112)=5122 */ {10112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5122_l1}, +/*h(14293)=5123 */ {14293, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5123_l1}, +/*h(763)=5124 */ {763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5124_l1}, +/*h(15890)=5125 */ {15890, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5125_l1}, +/*h(9125)=5126 */ {9125, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5126_l1}, +/*h(13306)=5127 */ {13306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14903)=5129 */ {14903, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5129_l1}, +/*h(8138)=5130 */ {8138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2970)=5133 */ {2970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11332)=5135 */ {11332, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5135_l1}, +/*h(15513)=5136 */ {15513, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5136_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12929)=5138 */ {12929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5138_l1}, +/*h(10345)=5139 */ {10345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7761)=5141 */ {7761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5141_l1}, +/*h(11942)=5142 */ {11942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5142_l1}, +/*h(16123)=5143 */ {16123, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5143_l1}, +/*h(13539)=5144 */ {13539, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5144_l1}, +/*h(6774)=5145 */ {6774, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5145_l1}, +/*h(10955)=5146 */ {10955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5146_l1}, +/*h(15136)=5147 */ {15136, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5147_l1}, +/*h(8371)=5148 */ {8371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5148_l1}, +/*h(5787)=5149 */ {5787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5149_l1}, +/*h(9968)=5150 */ {9968, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5150_l1}, +/*h(3203)=5151 */ {3203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5151_l1}, +/*h(619)=5152 */ {619, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5152_l1}, +/*h(4800)=5153 */ {4800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5153_l1}, +/*h(8981)=5154 */ {8981, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5154_l1}, +/*h(13162)=5155 */ {13162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3813)=5158 */ {3813, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5158_l1}, +/*h(7994)=5159 */ {7994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5159_l1}, +/*h(16356)=5160 */ {16356, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2826)=5162 */ {2826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5162_l1}, +/*h(242)=5163 */ {242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5163_l1}, +/*h(11188)=5164 */ {11188, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5164_l1}, +/*h(15369)=5165 */ {15369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5165_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6020)=5167 */ {6020, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5167_l1}, +/*h(10201)=5168 */ {10201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11798)=5170 */ {11798, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5170_l1}, +/*h(15979)=5171 */ {15979, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5171_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13395)=5173 */ {13395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10811)=5175 */ {10811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5175_l1}, +/*h(8227)=5176 */ {8227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5176_l1}, +/*h(12408)=5177 */ {12408, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5177_l1}, +/*h(5643)=5178 */ {5643, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5178_l1}, +/*h(3059)=5179 */ {3059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5179_l1}, +/*h(14005)=5180 */ {14005, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15602)=5182 */ {15602, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5182_l1}, +/*h(8837)=5183 */ {8837, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5183_l1}, +/*h(13018)=5184 */ {13018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5184_l1}, +/*h(10434)=5185 */ {10434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5185_l1}, +/*h(3669)=5186 */ {3669, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5186_l1}, +/*h(7850)=5187 */ {7850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5187_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5266)=5189 */ {5266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5189_l1}, +/*h(2682)=5190 */ {2682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(98)=5192 */ {98, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5192_l1}, +/*h(4279)=5193 */ {4279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5876)=5195 */ {5876, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5195_l1}, +/*h(10057)=5196 */ {10057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(708)=5198 */ {708, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5198_l1}, +/*h(4889)=5199 */ {4889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13251)=5201 */ {13251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5201_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14848)=5204 */ {14848, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5204_l1}, +/*h(8083)=5205 */ {8083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2915)=5208 */ {2915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5208_l1}, +/*h(7096)=5209 */ {7096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15458)=5211 */ {15458, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5211_l1}, +/*h(12874)=5212 */ {12874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5212_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10290)=5214 */ {10290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5214_l1}, +/*h(7706)=5215 */ {7706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5122)=5217 */ {5122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5217_l1}, +/*h(9303)=5218 */ {9303, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10900)=5220 */ {10900, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5220_l1}, +/*h(4135)=5221 */ {4135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12497)=5223 */ {12497, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5223_l1}, +/*h(5732)=5224 */ {5732, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5224_l1}, +/*h(9913)=5225 */ {9913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5225_l1}, +/*h(7329)=5226 */ {7329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5226_l1}, +/*h(11510)=5227 */ {11510, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5227_l1}, +/*h(4745)=5228 */ {4745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5228_l1}, +/*h(2161)=5229 */ {2161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5229_l1}, +/*h(13107)=5230 */ {13107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7939)=5233 */ {7939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5233_l1}, +/*h(1174)=5234 */ {1174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5234_l1}, +/*h(5355)=5235 */ {5355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5235_l1}, +/*h(2771)=5236 */ {2771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5236_l1}, +/*h(6952)=5237 */ {6952, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5237_l1}, +/*h(187)=5238 */ {187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5238_l1}, +/*h(15314)=5239 */ {15314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5239_l1}, +/*h(1784)=5240 */ {1784, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10146)=5242 */ {10146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5242_l1}, +/*h(14327)=5243 */ {14327, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5243_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4978)=5245 */ {4978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5245_l1}, +/*h(9159)=5246 */ {9159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5246_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10756)=5249 */ {10756, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5249_l1}, +/*h(3991)=5250 */ {3991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5250_l1}, +/*h(12353)=5251 */ {12353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5251_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9769)=5253 */ {9769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7185)=5255 */ {7185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5255_l1}, +/*h(11366)=5256 */ {11366, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5256_l1}, +/*h(15547)=5257 */ {15547, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5257_l1}, +/*h(12963)=5258 */ {12963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5258_l1}, +/*h(6198)=5259 */ {6198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5259_l1}, +/*h(10379)=5260 */ {10379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5260_l1}, +/*h(7795)=5261 */ {7795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5261_l1}, +/*h(1030)=5262 */ {1030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5262_l1}, +/*h(5211)=5263 */ {5211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5263_l1}, +/*h(9392)=5264 */ {9392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5264_l1}, +/*h(2627)=5265 */ {2627, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5265_l1}, +/*h(43)=5266 */ {43, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5266_l1}, +/*h(15170)=5267 */ {15170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5267_l1}, +/*h(8405)=5268 */ {8405, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5268_l1}, +/*h(1640)=5269 */ {1640, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10002)=5271 */ {10002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5271_l1}, +/*h(14183)=5272 */ {14183, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5272_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4834)=5274 */ {4834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5274_l1}, +/*h(9015)=5275 */ {9015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5275_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3847)=5278 */ {3847, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5278_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12209)=5280 */ {12209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5280_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7041)=5283 */ {7041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5283_l1}, +/*h(11222)=5284 */ {11222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5284_l1}, +/*h(15403)=5285 */ {15403, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5285_l1}, +/*h(1873)=5286 */ {1873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5286_l1}, +/*h(6054)=5287 */ {6054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5287_l1}, +/*h(10235)=5288 */ {10235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5288_l1}, +/*h(14416)=5289 */ {14416, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5289_l1}, +/*h(886)=5290 */ {886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5290_l1}, +/*h(5067)=5291 */ {5067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5291_l1}, +/*h(9248)=5292 */ {9248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5292_l1}, +/*h(13429)=5293 */ {13429, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5293_l1}, +/*h(6664)=5294 */ {6664, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15026)=5296 */ {15026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5296_l1}, +/*h(12442)=5297 */ {12442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5297_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9858)=5299 */ {9858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5299_l1}, +/*h(14039)=5300 */ {14039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5300_l1}, +/*h(7274)=5301 */ {7274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5301_l1}, +/*h(4690)=5302 */ {4690, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5302_l1}, +/*h(8871)=5303 */ {8871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5303_l1}, +/*h(2106)=5304 */ {2106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5304_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3703)=5306 */ {3703, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5306_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12065)=5308 */ {12065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5308_l1}, +/*h(16246)=5309 */ {16246, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11078)=5312 */ {11078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5312_l1}, +/*h(15259)=5313 */ {15259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5313_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1729)=5315 */ {1729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5315_l1}, +/*h(5910)=5316 */ {5910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5316_l1}, +/*h(10091)=5317 */ {10091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5317_l1}, +/*h(14272)=5318 */ {14272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5318_l1}, +/*h(742)=5319 */ {742, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5319_l1}, +/*h(4923)=5320 */ {4923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5320_l1}, +/*h(9104)=5321 */ {9104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5321_l1}, +/*h(13285)=5322 */ {13285, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5322_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14882)=5324 */ {14882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5324_l1}, +/*h(8117)=5325 */ {8117, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5325_l1}, +/*h(12298)=5326 */ {12298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13895)=5328 */ {13895, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5328_l1}, +/*h(7130)=5329 */ {7130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15492)=5331 */ {15492, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5331_l1}, +/*h(1962)=5332 */ {1962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10324)=5334 */ {10324, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5334_l1}, +/*h(14505)=5335 */ {14505, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11921)=5337 */ {11921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5337_l1}, +/*h(16102)=5338 */ {16102, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6753)=5340 */ {6753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5340_l1}, +/*h(10934)=5341 */ {10934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5341_l1}, +/*h(15115)=5342 */ {15115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5342_l1}, +/*h(12531)=5343 */ {12531, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5343_l1}, +/*h(5766)=5344 */ {5766, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5344_l1}, +/*h(9947)=5345 */ {9947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5345_l1}, +/*h(14128)=5346 */ {14128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5346_l1}, +/*h(598)=5347 */ {598, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5347_l1}, +/*h(4779)=5348 */ {4779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5348_l1}, +/*h(8960)=5349 */ {8960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5349_l1}, +/*h(2195)=5350 */ {2195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5350_l1}, +/*h(6376)=5351 */ {6376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5351_l1}, +/*h(3792)=5352 */ {3792, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5352_l1}, +/*h(7973)=5353 */ {7973, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5353_l1}, +/*h(12154)=5354 */ {12154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6986)=5357 */ {6986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5357_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15348)=5359 */ {15348, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1818)=5361 */ {1818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10180)=5363 */ {10180, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5363_l1}, +/*h(14361)=5364 */ {14361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5364_l1}, +/*h(11777)=5365 */ {11777, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5365_l1}, +/*h(15958)=5366 */ {15958, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5366_l1}, +/*h(9193)=5367 */ {9193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5367_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10790)=5369 */ {10790, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5369_l1}, +/*h(14971)=5370 */ {14971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12387)=5372 */ {12387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5372_l1}, +/*h(9803)=5373 */ {9803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5373_l1}, +/*h(13984)=5374 */ {13984, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5374_l1}, +/*h(7219)=5375 */ {7219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5375_l1}, +/*h(11400)=5376 */ {11400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5376_l1}, +/*h(4635)=5377 */ {4635, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5377_l1}, +/*h(2051)=5378 */ {2051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5378_l1}, +/*h(12997)=5379 */ {12997, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5379_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3648)=5381 */ {3648, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5381_l1}, +/*h(7829)=5382 */ {7829, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5382_l1}, +/*h(12010)=5383 */ {12010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5383_l1}, +/*h(9426)=5384 */ {9426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5384_l1}, +/*h(2661)=5385 */ {2661, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5385_l1}, +/*h(6842)=5386 */ {6842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5386_l1}, +/*h(4258)=5387 */ {4258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5387_l1}, +/*h(8439)=5388 */ {8439, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5388_l1}, +/*h(1674)=5389 */ {1674, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5389_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10036)=5391 */ {10036, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5391_l1}, +/*h(3271)=5392 */ {3271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5392_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4868)=5394 */ {4868, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5394_l1}, +/*h(9049)=5395 */ {9049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3881)=5398 */ {3881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12243)=5400 */ {12243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7075)=5403 */ {7075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5403_l1}, +/*h(11256)=5404 */ {11256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5404_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1907)=5407 */ {1907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5407_l1}, +/*h(6088)=5408 */ {6088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5408_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14450)=5410 */ {14450, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5410_l1}, +/*h(11866)=5411 */ {11866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5411_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9282)=5413 */ {9282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5413_l1}, +/*h(13463)=5414 */ {13463, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5414_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4114)=5416 */ {4114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5416_l1}, +/*h(8295)=5417 */ {8295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9892)=5419 */ {9892, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5419_l1}, +/*h(3127)=5420 */ {3127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11489)=5422 */ {11489, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5422_l1}, +/*h(4724)=5423 */ {4724, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5423_l1}, +/*h(8905)=5424 */ {8905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5424_l1}, +/*h(6321)=5425 */ {6321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3737)=5427 */ {3737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5427_l1}, +/*h(1153)=5428 */ {1153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5428_l1}, +/*h(12099)=5429 */ {12099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5429_l1}, +/*h(16280)=5430 */ {16280, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6931)=5432 */ {6931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5432_l1}, +/*h(4347)=5433 */ {4347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5433_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1763)=5435 */ {1763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5435_l1}, +/*h(5944)=5436 */ {5944, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5436_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14306)=5438 */ {14306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5438_l1}, +/*h(776)=5439 */ {776, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9138)=5441 */ {9138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5441_l1}, +/*h(13319)=5442 */ {13319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3970)=5444 */ {3970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5444_l1}, +/*h(8151)=5445 */ {8151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2983)=5448 */ {2983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5448_l1}, +/*h(13929)=5449 */ {13929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5449_l1}, +/*h(11345)=5450 */ {11345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5450_l1}, +/*h(15526)=5451 */ {15526, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5451_l1}, +/*h(8761)=5452 */ {8761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5452_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6177)=5454 */ {6177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5454_l1}, +/*h(10358)=5455 */ {10358, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5455_l1}, +/*h(14539)=5456 */ {14539, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5456_l1}, +/*h(11955)=5457 */ {11955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5457_l1}, +/*h(5190)=5458 */ {5190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5458_l1}, +/*h(9371)=5459 */ {9371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5459_l1}, +/*h(6787)=5460 */ {6787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5460_l1}, +/*h(22)=5461 */ {22, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5461_l1}, +/*h(4203)=5462 */ {4203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5462_l1}, +/*h(1619)=5463 */ {1619, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5463_l1}, +/*h(5800)=5464 */ {5800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5464_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14162)=5466 */ {14162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5466_l1}, +/*h(7397)=5467 */ {7397, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5467_l1}, +/*h(632)=5468 */ {632, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5468_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8994)=5470 */ {8994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5470_l1}, +/*h(13175)=5471 */ {13175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3826)=5473 */ {3826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5473_l1}, +/*h(8007)=5474 */ {8007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16369)=5476 */ {16369, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5476_l1}, +/*h(2839)=5477 */ {2839, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11201)=5479 */ {11201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5479_l1}, +/*h(15382)=5480 */ {15382, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5480_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6033)=5482 */ {6033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5482_l1}, +/*h(10214)=5483 */ {10214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5483_l1}, +/*h(14395)=5484 */ {14395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5484_l1}, +/*h(865)=5485 */ {865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5485_l1}, +/*h(5046)=5486 */ {5046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5486_l1}, +/*h(9227)=5487 */ {9227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5487_l1}, +/*h(13408)=5488 */ {13408, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5488_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4059)=5490 */ {4059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5490_l1}, +/*h(8240)=5491 */ {8240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5491_l1}, +/*h(12421)=5492 */ {12421, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5492_l1}, +/*h(5656)=5493 */ {5656, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5493_l1}, +/*h(3072)=5494 */ {3072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5494_l1}, +/*h(14018)=5495 */ {14018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5495_l1}, +/*h(11434)=5496 */ {11434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5496_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8850)=5498 */ {8850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5498_l1}, +/*h(13031)=5499 */ {13031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5499_l1}, +/*h(6266)=5500 */ {6266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5500_l1}, +/*h(3682)=5501 */ {3682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5501_l1}, +/*h(7863)=5502 */ {7863, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5502_l1}, +/*h(1098)=5503 */ {1098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5503_l1}, +/*h(16225)=5504 */ {16225, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5504_l1}, +/*h(2695)=5505 */ {2695, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11057)=5507 */ {11057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5507_l1}, +/*h(15238)=5508 */ {15238, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5889)=5510 */ {5889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5510_l1}, +/*h(10070)=5511 */ {10070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5511_l1}, +/*h(14251)=5512 */ {14251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5512_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(721)=5514 */ {721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5514_l1}, +/*h(4902)=5515 */ {4902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5515_l1}, +/*h(9083)=5516 */ {9083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5516_l1}, +/*h(13264)=5517 */ {13264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3915)=5519 */ {3915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5519_l1}, +/*h(8096)=5520 */ {8096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5520_l1}, +/*h(12277)=5521 */ {12277, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5521_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13874)=5523 */ {13874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5523_l1}, +/*h(7109)=5524 */ {7109, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5524_l1}, +/*h(11290)=5525 */ {11290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5525_l1}, +/*h(8706)=5526 */ {8706, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5526_l1}, +/*h(12887)=5527 */ {12887, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5527_l1}, +/*h(6122)=5528 */ {6122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14484)=5530 */ {14484, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5530_l1}, +/*h(954)=5531 */ {954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5531_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16081)=5533 */ {16081, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5533_l1}, +/*h(13497)=5534 */ {13497, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5534_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10913)=5536 */ {10913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5536_l1}, +/*h(15094)=5537 */ {15094, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5537_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5745)=5539 */ {5745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5539_l1}, +/*h(9926)=5540 */ {9926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5540_l1}, +/*h(14107)=5541 */ {14107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5541_l1}, +/*h(577)=5542 */ {577, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5542_l1}, +/*h(4758)=5543 */ {4758, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5543_l1}, +/*h(8939)=5544 */ {8939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5544_l1}, +/*h(13120)=5545 */ {13120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5545_l1}, +/*h(6355)=5546 */ {6355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5546_l1}, +/*h(3771)=5547 */ {3771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5547_l1}, +/*h(7952)=5548 */ {7952, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5548_l1}, +/*h(1187)=5549 */ {1187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5549_l1}, +/*h(16314)=5550 */ {16314, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5550_l1}, +/*h(2784)=5551 */ {2784, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5551_l1}, +/*h(6965)=5552 */ {6965, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5552_l1}, +/*h(11146)=5553 */ {11146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5553_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1797)=5555 */ {1797, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5555_l1}, +/*h(5978)=5556 */ {5978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5556_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14340)=5558 */ {14340, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(810)=5560 */ {810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5560_l1}, +/*h(15937)=5561 */ {15937, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5561_l1}, +/*h(9172)=5562 */ {9172, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5562_l1}, +/*h(13353)=5563 */ {13353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5563_l1}, +/*h(10769)=5564 */ {10769, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5564_l1}, +/*h(14950)=5565 */ {14950, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5565_l1}, +/*h(8185)=5566 */ {8185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5566_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9782)=5568 */ {9782, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5568_l1}, +/*h(13963)=5569 */ {13963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11379)=5571 */ {11379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5571_l1}, +/*h(8795)=5572 */ {8795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5572_l1}, +/*h(12976)=5573 */ {12976, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5573_l1}, +/*h(6211)=5574 */ {6211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5574_l1}, +/*h(10392)=5575 */ {10392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5575_l1}, +/*h(3627)=5576 */ {3627, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5576_l1}, +/*h(1043)=5577 */ {1043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5577_l1}, +/*h(11989)=5578 */ {11989, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5578_l1}, +/*h(16170)=5579 */ {16170, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5579_l1}, +/*h(2640)=5580 */ {2640, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5580_l1}, +/*h(6821)=5581 */ {6821, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5581_l1}, +/*h(11002)=5582 */ {11002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5582_l1}, +/*h(8418)=5583 */ {8418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5583_l1}, +/*h(1653)=5584 */ {1653, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5584_l1}, +/*h(5834)=5585 */ {5834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5585_l1}, +/*h(3250)=5586 */ {3250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5586_l1}, +/*h(14196)=5587 */ {14196, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5587_l1}, +/*h(666)=5588 */ {666, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5588_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9028)=5590 */ {9028, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5590_l1}, +/*h(2263)=5591 */ {2263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5591_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3860)=5593 */ {3860, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5593_l1}, +/*h(8041)=5594 */ {8041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2873)=5597 */ {2873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11235)=5599 */ {11235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5599_l1}, +/*h(15416)=5600 */ {15416, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5600_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6067)=5602 */ {6067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5602_l1}, +/*h(10248)=5603 */ {10248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5603_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(899)=5606 */ {899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5606_l1}, +/*h(16026)=5607 */ {16026, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5607_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13442)=5609 */ {13442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5609_l1}, +/*h(10858)=5610 */ {10858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5610_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8274)=5612 */ {8274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5612_l1}, +/*h(5690)=5613 */ {5690, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5613_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3106)=5615 */ {3106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5615_l1}, +/*h(7287)=5616 */ {7287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5616_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8884)=5618 */ {8884, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5618_l1}, +/*h(2119)=5619 */ {2119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5619_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10481)=5621 */ {10481, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5621_l1}, +/*h(3716)=5622 */ {3716, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5622_l1}, +/*h(7897)=5623 */ {7897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5623_l1}, +/*h(5313)=5624 */ {5313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5624_l1}, +/*h(16259)=5625 */ {16259, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5625_l1}, +/*h(2729)=5626 */ {2729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5626_l1}, +/*h(145)=5627 */ {145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5627_l1}, +/*h(11091)=5628 */ {11091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5628_l1}, +/*h(15272)=5629 */ {15272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5629_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10104)=5632 */ {10104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5632_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(755)=5634 */ {755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5634_l1}, +/*h(15882)=5635 */ {15882, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5635_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13298)=5637 */ {13298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5637_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8130)=5640 */ {8130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5640_l1}, +/*h(12311)=5641 */ {12311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5641_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2962)=5643 */ {2962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5643_l1}, +/*h(7143)=5644 */ {7143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5644_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15505)=5646 */ {15505, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5646_l1}, +/*h(1975)=5647 */ {1975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5647_l1}, +/*h(12921)=5648 */ {12921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5648_l1}, +/*h(10337)=5649 */ {10337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5649_l1}, +/*h(14518)=5650 */ {14518, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5650_l1}, +/*h(7753)=5651 */ {7753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5651_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16115)=5653 */ {16115, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5653_l1}, +/*h(9350)=5654 */ {9350, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5654_l1}, +/*h(13531)=5655 */ {13531, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5655_l1}, +/*h(10947)=5656 */ {10947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5656_l1}, +/*h(4182)=5657 */ {4182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5657_l1}, +/*h(8363)=5658 */ {8363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5658_l1}, +/*h(5779)=5659 */ {5779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5659_l1}, +/*h(9960)=5660 */ {9960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5660_l1}, +/*h(3195)=5661 */ {3195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5661_l1}, +/*h(611)=5662 */ {611, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5662_l1}, +/*h(4792)=5663 */ {4792, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5663_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13154)=5665 */ {13154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5665_l1}, +/*h(6389)=5666 */ {6389, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5666_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1221)=5669 */ {1221, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5669_l1}, +/*h(12167)=5670 */ {12167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5670_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2818)=5672 */ {2818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5672_l1}, +/*h(6999)=5673 */ {6999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5673_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15361)=5675 */ {15361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5675_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10193)=5678 */ {10193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5678_l1}, +/*h(14374)=5679 */ {14374, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5679_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15971)=5681 */ {15971, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5681_l1}, +/*h(9206)=5682 */ {9206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5682_l1}, +/*h(13387)=5683 */ {13387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5683_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4038)=5685 */ {4038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5685_l1}, +/*h(8219)=5686 */ {8219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5686_l1}, +/*h(12400)=5687 */ {12400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5687_l1}, +/*h(5635)=5688 */ {5635, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5688_l1}, +/*h(3051)=5689 */ {3051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5689_l1}, +/*h(7232)=5690 */ {7232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5690_l1}, +/*h(11413)=5691 */ {11413, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5691_l1}, +/*h(15594)=5692 */ {15594, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5692_l1}, +/*h(2064)=5693 */ {2064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5693_l1}, +/*h(13010)=5694 */ {13010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5694_l1}, +/*h(10426)=5695 */ {10426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5695_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7842)=5697 */ {7842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5697_l1}, +/*h(12023)=5698 */ {12023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5698_l1}, +/*h(5258)=5699 */ {5258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5699_l1}, +/*h(2674)=5700 */ {2674, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5700_l1}, +/*h(6855)=5701 */ {6855, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5701_l1}, +/*h(90)=5702 */ {90, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5702_l1}, +/*h(15217)=5703 */ {15217, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5703_l1}, +/*h(1687)=5704 */ {1687, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5704_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10049)=5706 */ {10049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5706_l1}, +/*h(14230)=5707 */ {14230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5707_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4881)=5709 */ {4881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5709_l1}, +/*h(9062)=5710 */ {9062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5710_l1}, +/*h(13243)=5711 */ {13243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5711_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8075)=5715 */ {8075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5715_l1}, +/*h(12256)=5716 */ {12256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5716_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2907)=5718 */ {2907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5718_l1}, +/*h(7088)=5719 */ {7088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5719_l1}, +/*h(11269)=5720 */ {11269, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5720_l1}, +/*h(15450)=5721 */ {15450, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5721_l1}, +/*h(12866)=5722 */ {12866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5722_l1}, +/*h(6101)=5723 */ {6101, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5723_l1}, +/*h(10282)=5724 */ {10282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5724_l1}, +/*h(7698)=5725 */ {7698, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5725_l1}, +/*h(11879)=5726 */ {11879, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5726_l1}, +/*h(5114)=5727 */ {5114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13476)=5729 */ {13476, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5729_l1}, +/*h(6711)=5730 */ {6711, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5730_l1}, +/*h(15073)=5731 */ {15073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5731_l1}, +/*h(8308)=5732 */ {8308, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5732_l1}, +/*h(1543)=5733 */ {1543, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5733_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9905)=5735 */ {9905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5735_l1}, +/*h(14086)=5736 */ {14086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5736_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4737)=5738 */ {4737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5738_l1}, +/*h(8918)=5739 */ {8918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5739_l1}, +/*h(13099)=5740 */ {13099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5740_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3750)=5742 */ {3750, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5742_l1}, +/*h(7931)=5743 */ {7931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5743_l1}, +/*h(12112)=5744 */ {12112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5744_l1}, +/*h(5347)=5745 */ {5347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5745_l1}, +/*h(2763)=5746 */ {2763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5746_l1}, +/*h(6944)=5747 */ {6944, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5747_l1}, +/*h(179)=5748 */ {179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5748_l1}, +/*h(15306)=5749 */ {15306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5749_l1}, +/*h(1776)=5750 */ {1776, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5750_l1}, +/*h(5957)=5751 */ {5957, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5751_l1}, +/*h(10138)=5752 */ {10138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5752_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(789)=5754 */ {789, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5754_l1}, +/*h(4970)=5755 */ {4970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5755_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13332)=5757 */ {13332, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5757_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14929)=5760 */ {14929, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5760_l1}, +/*h(8164)=5761 */ {8164, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5761_l1}, +/*h(12345)=5762 */ {12345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5762_l1}, +/*h(9761)=5763 */ {9761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5763_l1}, +/*h(13942)=5764 */ {13942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5764_l1}, +/*h(7177)=5765 */ {7177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5765_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15539)=5767 */ {15539, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5767_l1}, +/*h(12955)=5768 */ {12955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5768_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3606)=5770 */ {3606, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5770_l1}, +/*h(7787)=5771 */ {7787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5771_l1}, +/*h(11968)=5772 */ {11968, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5772_l1}, +/*h(5203)=5773 */ {5203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5773_l1}, +/*h(9384)=5774 */ {9384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5774_l1}, +/*h(2619)=5775 */ {2619, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5775_l1}, +/*h(35)=5776 */ {35, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5776_l1}, +/*h(15162)=5777 */ {15162, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5777_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1632)=5779 */ {1632, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5779_l1}, +/*h(5813)=5780 */ {5813, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5780_l1}, +/*h(9994)=5781 */ {9994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5781_l1}, +/*h(7410)=5782 */ {7410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5782_l1}, +/*h(645)=5783 */ {645, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5783_l1}, +/*h(4826)=5784 */ {4826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5784_l1}, +/*h(2242)=5785 */ {2242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5785_l1}, +/*h(13188)=5786 */ {13188, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5786_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8020)=5789 */ {8020, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5789_l1}, +/*h(1255)=5790 */ {1255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5790_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2852)=5792 */ {2852, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5792_l1}, +/*h(7033)=5793 */ {7033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5793_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15395)=5795 */ {15395, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5795_l1}, +/*h(1865)=5796 */ {1865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5796_l1}, +/*h(12811)=5797 */ {12811, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5797_l1}, +/*h(10227)=5798 */ {10227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5798_l1}, +/*h(14408)=5799 */ {14408, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5799_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5059)=5801 */ {5059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5801_l1}, +/*h(16005)=5802 */ {16005, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5802_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6656)=5804 */ {6656, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5804_l1}, +/*h(10837)=5805 */ {10837, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5805_l1}, +/*h(15018)=5806 */ {15018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5806_l1}, +/*h(12434)=5807 */ {12434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5807_l1}, +/*h(5669)=5808 */ {5669, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5808_l1}, +/*h(9850)=5809 */ {9850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5809_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7266)=5811 */ {7266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5811_l1}, +/*h(11447)=5812 */ {11447, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5812_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2098)=5814 */ {2098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5814_l1}, +/*h(6279)=5815 */ {6279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5815_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7876)=5817 */ {7876, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5817_l1}, +/*h(1111)=5818 */ {1111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5818_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2708)=5821 */ {2708, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5821_l1}, +/*h(6889)=5822 */ {6889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5822_l1}, +/*h(15251)=5823 */ {15251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5823_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1721)=5825 */ {1721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10083)=5827 */ {10083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5827_l1}, +/*h(14264)=5828 */ {14264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5828_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4915)=5830 */ {4915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5830_l1}, +/*h(9096)=5831 */ {9096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5831_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14874)=5834 */ {14874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5834_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12290)=5836 */ {12290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5836_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7122)=5839 */ {7122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5839_l1}, +/*h(11303)=5840 */ {11303, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5840_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1954)=5842 */ {1954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5842_l1}, +/*h(6135)=5843 */ {6135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5843_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14497)=5845 */ {14497, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5845_l1}, +/*h(967)=5846 */ {967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5846_l1}, +/*h(11913)=5847 */ {11913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5847_l1}, +/*h(9329)=5848 */ {9329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5848_l1}, +/*h(13510)=5849 */ {13510, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5849_l1}, +/*h(6745)=5850 */ {6745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5850_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15107)=5852 */ {15107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5852_l1}, +/*h(8342)=5853 */ {8342, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5853_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9939)=5855 */ {9939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5855_l1}, +/*h(3174)=5856 */ {3174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5856_l1}, +/*h(7355)=5857 */ {7355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5857_l1}, +/*h(4771)=5858 */ {4771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5858_l1}, +/*h(8952)=5859 */ {8952, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5859_l1}, +/*h(2187)=5860 */ {2187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5860_l1}, +/*h(6368)=5861 */ {6368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5861_l1}, +/*h(3784)=5862 */ {3784, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5862_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12146)=5864 */ {12146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5864_l1}, +/*h(16327)=5865 */ {16327, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5865_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11159)=5868 */ {11159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5868_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1810)=5871 */ {1810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5871_l1}, +/*h(5991)=5872 */ {5991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5872_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14353)=5874 */ {14353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5874_l1}, +/*h(823)=5875 */ {823, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5875_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9185)=5877 */ {9185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5877_l1}, +/*h(13366)=5878 */ {13366, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5878_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14963)=5880 */ {14963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5880_l1}, +/*h(8198)=5881 */ {8198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5881_l1}, +/*h(12379)=5882 */ {12379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5882_l1}, +/*h(9795)=5883 */ {9795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5883_l1}, +/*h(3030)=5884 */ {3030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5884_l1}, +/*h(7211)=5885 */ {7211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5885_l1}, +/*h(11392)=5886 */ {11392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5886_l1}, +/*h(4627)=5887 */ {4627, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5887_l1}, +/*h(2043)=5888 */ {2043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5888_l1}, +/*h(6224)=5889 */ {6224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5889_l1}, +/*h(10405)=5890 */ {10405, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5890_l1}, +/*h(14586)=5891 */ {14586, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5891_l1}, +/*h(1056)=5892 */ {1056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5892_l1}, +/*h(12002)=5893 */ {12002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5893_l1}, +/*h(9418)=5894 */ {9418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5894_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6834)=5896 */ {6834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5896_l1}, +/*h(11015)=5897 */ {11015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5897_l1}, +/*h(4250)=5898 */ {4250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5898_l1}, +/*h(1666)=5899 */ {1666, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5899_l1}, +/*h(5847)=5900 */ {5847, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5900_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14209)=5902 */ {14209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5902_l1}, +/*h(679)=5903 */ {679, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9041)=5905 */ {9041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5905_l1}, +/*h(13222)=5906 */ {13222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5906_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3873)=5908 */ {3873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5908_l1}, +/*h(8054)=5909 */ {8054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5909_l1}, +/*h(12235)=5910 */ {12235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5910_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2886)=5913 */ {2886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5913_l1}, +/*h(7067)=5914 */ {7067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5914_l1}, +/*h(15429)=5915 */ {15429, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1899)=5917 */ {1899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5917_l1}, +/*h(6080)=5918 */ {6080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5918_l1}, +/*h(10261)=5919 */ {10261, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5919_l1}, +/*h(14442)=5920 */ {14442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5920_l1}, +/*h(11858)=5921 */ {11858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5921_l1}, +/*h(16039)=5922 */ {16039, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5922_l1}, +/*h(9274)=5923 */ {9274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5923_l1}, +/*h(6690)=5924 */ {6690, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5924_l1}, +/*h(10871)=5925 */ {10871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5925_l1}, +/*h(4106)=5926 */ {4106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5926_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12468)=5928 */ {12468, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5928_l1}, +/*h(5703)=5929 */ {5703, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5929_l1}, +/*h(14065)=5930 */ {14065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5930_l1}, +/*h(7300)=5931 */ {7300, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5931_l1}, +/*h(535)=5932 */ {535, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8897)=5934 */ {8897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5934_l1}, +/*h(13078)=5935 */ {13078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5935_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3729)=5937 */ {3729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5937_l1}, +/*h(7910)=5938 */ {7910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5938_l1}, +/*h(12091)=5939 */ {12091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5939_l1}, +/*h(16272)=5940 */ {16272, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5940_l1}, +/*h(2742)=5941 */ {2742, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5941_l1}, +/*h(6923)=5942 */ {6923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5942_l1}, +/*h(11104)=5943 */ {11104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5943_l1}, +/*h(4339)=5944 */ {4339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5944_l1}, +/*h(1755)=5945 */ {1755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5945_l1}, +/*h(5936)=5946 */ {5936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5946_l1}, +/*h(10117)=5947 */ {10117, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5947_l1}, +/*h(14298)=5948 */ {14298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5948_l1}, +/*h(768)=5949 */ {768, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5949_l1}, +/*h(4949)=5950 */ {4949, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5950_l1}, +/*h(9130)=5951 */ {9130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5951_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3962)=5954 */ {3962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5954_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12324)=5956 */ {12324, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5956_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13921)=5959 */ {13921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5959_l1}, +/*h(11337)=5960 */ {11337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5960_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8753)=5962 */ {8753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5962_l1}, +/*h(12934)=5963 */ {12934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5963_l1}, +/*h(6169)=5964 */ {6169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5964_l1}, +/*h(3585)=5965 */ {3585, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5965_l1}, +/*h(7766)=5966 */ {7766, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5966_l1}, +/*h(11947)=5967 */ {11947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5967_l1}, +/*h(16128)=5968 */ {16128, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5968_l1}, +/*h(9363)=5969 */ {9363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5969_l1}, +/*h(6779)=5970 */ {6779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5970_l1}, +/*h(10960)=5971 */ {10960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5971_l1}, +/*h(4195)=5972 */ {4195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5972_l1}, +/*h(8376)=5973 */ {8376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5973_l1}, +/*h(1611)=5974 */ {1611, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5974_l1}, +/*h(9973)=5975 */ {9973, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5975_l1}, +/*h(14154)=5976 */ {14154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5976_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(624)=5978 */ {624, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5978_l1}, +/*h(4805)=5979 */ {4805, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5979_l1}, +/*h(8986)=5980 */ {8986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5980_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3818)=5983 */ {3818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5983_l1}, +/*h(1234)=5984 */ {1234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5984_l1}, +/*h(12180)=5985 */ {12180, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5985_l1}, +/*h(16361)=5986 */ {16361, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7012)=5988 */ {7012, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5988_l1}, +/*h(247)=5989 */ {247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5989_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1844)=5991 */ {1844, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5991_l1}, +/*h(6025)=5992 */ {6025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5992_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14387)=5994 */ {14387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5994_l1}, +/*h(857)=5995 */ {857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5995_l1}, +/*h(11803)=5996 */ {11803, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5996_l1}, +/*h(9219)=5997 */ {9219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5997_l1}, +/*h(13400)=5998 */ {13400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_5998_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4051)=6000 */ {4051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6000_l1}, +/*h(14997)=6001 */ {14997, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6001_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5648)=6003 */ {5648, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6003_l1}, +/*h(9829)=6004 */ {9829, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6004_l1}, +/*h(14010)=6005 */ {14010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6005_l1}, +/*h(11426)=6006 */ {11426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6006_l1}, +/*h(15607)=6007 */ {15607, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6007_l1}, +/*h(8842)=6008 */ {8842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6008_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6258)=6010 */ {6258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6010_l1}, +/*h(3674)=6011 */ {3674, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6011_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1090)=6013 */ {1090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6013_l1}, +/*h(5271)=6014 */ {5271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6014_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6868)=6016 */ {6868, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6016_l1}, +/*h(103)=6017 */ {103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6017_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5881)=6020 */ {5881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6020_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14243)=6022 */ {14243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6022_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(713)=6024 */ {713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6024_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9075)=6026 */ {9075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6026_l1}, +/*h(13256)=6027 */ {13256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3907)=6029 */ {3907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6029_l1}, +/*h(8088)=6030 */ {8088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6030_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13866)=6033 */ {13866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6033_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11282)=6035 */ {11282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6035_l1}, +/*h(15463)=6036 */ {15463, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6036_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6114)=6038 */ {6114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6038_l1}, +/*h(10295)=6039 */ {10295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6039_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(946)=6041 */ {946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6041_l1}, +/*h(5127)=6042 */ {5127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6042_l1}, +/*h(16073)=6043 */ {16073, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6043_l1}, +/*h(13489)=6044 */ {13489, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6044_l1}, +/*h(6724)=6045 */ {6724, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6045_l1}, +/*h(10905)=6046 */ {10905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6046_l1}, +/*h(8321)=6047 */ {8321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6047_l1}, +/*h(12502)=6048 */ {12502, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6048_l1}, +/*h(5737)=6049 */ {5737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6049_l1}, +/*h(3153)=6050 */ {3153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6050_l1}, +/*h(14099)=6051 */ {14099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6051_l1}, +/*h(11515)=6052 */ {11515, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6052_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8931)=6054 */ {8931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6054_l1}, +/*h(2166)=6055 */ {2166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6055_l1}, +/*h(6347)=6056 */ {6347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6056_l1}, +/*h(3763)=6057 */ {3763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6057_l1}, +/*h(7944)=6058 */ {7944, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6058_l1}, +/*h(1179)=6059 */ {1179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6059_l1}, +/*h(16306)=6060 */ {16306, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6060_l1}, +/*h(2776)=6061 */ {2776, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11138)=6063 */ {11138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6063_l1}, +/*h(15319)=6064 */ {15319, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6064_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5970)=6066 */ {5970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6066_l1}, +/*h(10151)=6067 */ {10151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6067_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(802)=6070 */ {802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6070_l1}, +/*h(4983)=6071 */ {4983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6071_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13345)=6073 */ {13345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6073_l1}, +/*h(10761)=6074 */ {10761, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6074_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8177)=6076 */ {8177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6076_l1}, +/*h(12358)=6077 */ {12358, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6077_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13955)=6079 */ {13955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6079_l1}, +/*h(7190)=6080 */ {7190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6080_l1}, +/*h(11371)=6081 */ {11371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6081_l1}, +/*h(8787)=6082 */ {8787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6082_l1}, +/*h(2022)=6083 */ {2022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6083_l1}, +/*h(6203)=6084 */ {6203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6084_l1}, +/*h(10384)=6085 */ {10384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6085_l1}, +/*h(3619)=6086 */ {3619, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6086_l1}, +/*h(1035)=6087 */ {1035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6087_l1}, +/*h(5216)=6088 */ {5216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6088_l1}, +/*h(9397)=6089 */ {9397, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6089_l1}, +/*h(2632)=6090 */ {2632, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6090_l1}, +/*h(48)=6091 */ {48, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6091_l1}, +/*h(10994)=6092 */ {10994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6092_l1}, +/*h(15175)=6093 */ {15175, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5826)=6095 */ {5826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6095_l1}, +/*h(10007)=6096 */ {10007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6096_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(658)=6098 */ {658, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6098_l1}, +/*h(4839)=6099 */ {4839, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6099_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13201)=6101 */ {13201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6101_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8033)=6104 */ {8033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6104_l1}, +/*h(12214)=6105 */ {12214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2865)=6107 */ {2865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6107_l1}, +/*h(7046)=6108 */ {7046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6108_l1}, +/*h(11227)=6109 */ {11227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6109_l1}, +/*h(15408)=6110 */ {15408, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6110_l1}, +/*h(1878)=6111 */ {1878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6111_l1}, +/*h(6059)=6112 */ {6059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6112_l1}, +/*h(10240)=6113 */ {10240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6113_l1}, +/*h(14421)=6114 */ {14421, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6114_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(891)=6116 */ {891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6116_l1}, +/*h(16018)=6117 */ {16018, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6117_l1}, +/*h(9253)=6118 */ {9253, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6118_l1}, +/*h(13434)=6119 */ {13434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6119_l1}, +/*h(10850)=6120 */ {10850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6120_l1}, +/*h(15031)=6121 */ {15031, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6121_l1}, +/*h(8266)=6122 */ {8266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6122_l1}, +/*h(5682)=6123 */ {5682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6123_l1}, +/*h(9863)=6124 */ {9863, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6124_l1}, +/*h(3098)=6125 */ {3098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6125_l1}, +/*h(514)=6126 */ {514, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6126_l1}, +/*h(4695)=6127 */ {4695, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13057)=6129 */ {13057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6129_l1}, +/*h(6292)=6130 */ {6292, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6130_l1}, +/*h(10473)=6131 */ {10473, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6131_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7889)=6133 */ {7889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6133_l1}, +/*h(5305)=6134 */ {5305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6134_l1}, +/*h(16251)=6135 */ {16251, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6135_l1}, +/*h(2721)=6136 */ {2721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6136_l1}, +/*h(6902)=6137 */ {6902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6137_l1}, +/*h(11083)=6138 */ {11083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6138_l1}, +/*h(15264)=6139 */ {15264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6139_l1}, +/*h(1734)=6140 */ {1734, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6140_l1}, +/*h(5915)=6141 */ {5915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6141_l1}, +/*h(10096)=6142 */ {10096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6142_l1}, +/*h(14277)=6143 */ {14277, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6143_l1}, +/*h(747)=6144 */ {747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6144_l1}, +/*h(15874)=6145 */ {15874, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6145_l1}, +/*h(9109)=6146 */ {9109, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6146_l1}, +/*h(13290)=6147 */ {13290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3941)=6149 */ {3941, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6149_l1}, +/*h(8122)=6150 */ {8122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2954)=6153 */ {2954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11316)=6155 */ {11316, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6155_l1}, +/*h(15497)=6156 */ {15497, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12913)=6158 */ {12913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6158_l1}, +/*h(10329)=6159 */ {10329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7745)=6161 */ {7745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6161_l1}, +/*h(11926)=6162 */ {11926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6162_l1}, +/*h(16107)=6163 */ {16107, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6163_l1}, +/*h(2577)=6164 */ {2577, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6164_l1}, +/*h(13523)=6165 */ {13523, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6165_l1}, +/*h(10939)=6166 */ {10939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6166_l1}, +/*h(15120)=6167 */ {15120, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6167_l1}, +/*h(1590)=6168 */ {1590, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6168_l1}, +/*h(5771)=6169 */ {5771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6169_l1}, +/*h(9952)=6170 */ {9952, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6170_l1}, +/*h(3187)=6171 */ {3187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6171_l1}, +/*h(603)=6172 */ {603, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6172_l1}, +/*h(4784)=6173 */ {4784, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6173_l1}, +/*h(8965)=6174 */ {8965, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6174_l1}, +/*h(13146)=6175 */ {13146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3797)=6178 */ {3797, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6178_l1}, +/*h(7978)=6179 */ {7978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16340)=6181 */ {16340, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6181_l1}, +/*h(2810)=6182 */ {2810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6182_l1}, +/*h(226)=6183 */ {226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6183_l1}, +/*h(11172)=6184 */ {11172, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6184_l1}, +/*h(15353)=6185 */ {15353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6004)=6187 */ {6004, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6187_l1}, +/*h(10185)=6188 */ {10185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11782)=6190 */ {11782, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6190_l1}, +/*h(15963)=6191 */ {15963, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13379)=6193 */ {13379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10795)=6195 */ {10795, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6195_l1}, +/*h(8211)=6196 */ {8211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6196_l1}, +/*h(12392)=6197 */ {12392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3043)=6199 */ {3043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6199_l1}, +/*h(13989)=6200 */ {13989, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15586)=6202 */ {15586, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6202_l1}, +/*h(8821)=6203 */ {8821, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6203_l1}, +/*h(13002)=6204 */ {13002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6204_l1}, +/*h(10418)=6205 */ {10418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6205_l1}, +/*h(3653)=6206 */ {3653, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6206_l1}, +/*h(7834)=6207 */ {7834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6207_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5250)=6209 */ {5250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6209_l1}, +/*h(9431)=6210 */ {9431, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(82)=6212 */ {82, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6212_l1}, +/*h(4263)=6213 */ {4263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5860)=6215 */ {5860, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6215_l1}, +/*h(10041)=6216 */ {10041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6216_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(692)=6218 */ {692, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6218_l1}, +/*h(4873)=6219 */ {4873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6219_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13235)=6221 */ {13235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8067)=6225 */ {8067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6225_l1}, +/*h(12248)=6226 */ {12248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6226_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2899)=6228 */ {2899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6228_l1}, +/*h(7080)=6229 */ {7080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6229_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15442)=6231 */ {15442, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6231_l1}, +/*h(12858)=6232 */ {12858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10274)=6234 */ {10274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6234_l1}, +/*h(14455)=6235 */ {14455, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5106)=6237 */ {5106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6237_l1}, +/*h(9287)=6238 */ {9287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4119)=6241 */ {4119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6241_l1}, +/*h(15065)=6242 */ {15065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6242_l1}, +/*h(12481)=6243 */ {12481, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6243_l1}, +/*h(5716)=6244 */ {5716, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6244_l1}, +/*h(9897)=6245 */ {9897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6245_l1}, +/*h(7313)=6246 */ {7313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6246_l1}, +/*h(11494)=6247 */ {11494, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6247_l1}, +/*h(4729)=6248 */ {4729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6248_l1}, +/*h(2145)=6249 */ {2145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6249_l1}, +/*h(13091)=6250 */ {13091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7923)=6253 */ {7923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6253_l1}, +/*h(1158)=6254 */ {1158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6254_l1}, +/*h(5339)=6255 */ {5339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6255_l1}, +/*h(2755)=6256 */ {2755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6256_l1}, +/*h(6936)=6257 */ {6936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6257_l1}, +/*h(171)=6258 */ {171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6258_l1}, +/*h(15298)=6259 */ {15298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6259_l1}, +/*h(1768)=6260 */ {1768, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6260_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10130)=6262 */ {10130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6262_l1}, +/*h(14311)=6263 */ {14311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6263_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4962)=6265 */ {4962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6265_l1}, +/*h(9143)=6266 */ {9143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6266_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3975)=6270 */ {3975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12337)=6272 */ {12337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6272_l1}, +/*h(9753)=6273 */ {9753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7169)=6275 */ {7169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6275_l1}, +/*h(11350)=6276 */ {11350, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6276_l1}, +/*h(15531)=6277 */ {15531, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6277_l1}, +/*h(12947)=6278 */ {12947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6278_l1}, +/*h(6182)=6279 */ {6182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6279_l1}, +/*h(10363)=6280 */ {10363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6280_l1}, +/*h(7779)=6281 */ {7779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6281_l1}, +/*h(1014)=6282 */ {1014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6282_l1}, +/*h(5195)=6283 */ {5195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6283_l1}, +/*h(9376)=6284 */ {9376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6284_l1}, +/*h(2611)=6285 */ {2611, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6285_l1}, +/*h(27)=6286 */ {27, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6286_l1}, +/*h(4208)=6287 */ {4208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6287_l1}, +/*h(15154)=6288 */ {15154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6288_l1}, +/*h(1624)=6289 */ {1624, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6289_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9986)=6291 */ {9986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6291_l1}, +/*h(14167)=6292 */ {14167, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4818)=6294 */ {4818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6294_l1}, +/*h(8999)=6295 */ {8999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3831)=6298 */ {3831, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12193)=6300 */ {12193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6300_l1}, +/*h(16374)=6301 */ {16374, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6301_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7025)=6303 */ {7025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6303_l1}, +/*h(11206)=6304 */ {11206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6304_l1}, +/*h(15387)=6305 */ {15387, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6305_l1}, +/*h(1857)=6306 */ {1857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6306_l1}, +/*h(6038)=6307 */ {6038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6307_l1}, +/*h(10219)=6308 */ {10219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6308_l1}, +/*h(14400)=6309 */ {14400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6309_l1}, +/*h(870)=6310 */ {870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6310_l1}, +/*h(5051)=6311 */ {5051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6311_l1}, +/*h(9232)=6312 */ {9232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6312_l1}, +/*h(13413)=6313 */ {13413, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6313_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15010)=6316 */ {15010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6316_l1}, +/*h(8245)=6317 */ {8245, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6317_l1}, +/*h(12426)=6318 */ {12426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6318_l1}, +/*h(9842)=6319 */ {9842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6319_l1}, +/*h(14023)=6320 */ {14023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6320_l1}, +/*h(7258)=6321 */ {7258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6321_l1}, +/*h(4674)=6322 */ {4674, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6322_l1}, +/*h(8855)=6323 */ {8855, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6323_l1}, +/*h(2090)=6324 */ {2090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6324_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3687)=6326 */ {3687, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12049)=6328 */ {12049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6328_l1}, +/*h(16230)=6329 */ {16230, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6329_l1}, +/*h(9465)=6330 */ {9465, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6881)=6332 */ {6881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6332_l1}, +/*h(11062)=6333 */ {11062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1713)=6335 */ {1713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6335_l1}, +/*h(5894)=6336 */ {5894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6336_l1}, +/*h(10075)=6337 */ {10075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6337_l1}, +/*h(14256)=6338 */ {14256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6338_l1}, +/*h(726)=6339 */ {726, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6339_l1}, +/*h(4907)=6340 */ {4907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6340_l1}, +/*h(9088)=6341 */ {9088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6341_l1}, +/*h(13269)=6342 */ {13269, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14866)=6344 */ {14866, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6344_l1}, +/*h(8101)=6345 */ {8101, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6345_l1}, +/*h(12282)=6346 */ {12282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6346_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2933)=6348 */ {2933, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6348_l1}, +/*h(7114)=6349 */ {7114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15476)=6351 */ {15476, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6351_l1}, +/*h(1946)=6352 */ {1946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6352_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10308)=6354 */ {10308, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6354_l1}, +/*h(14489)=6355 */ {14489, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6355_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11905)=6357 */ {11905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6357_l1}, +/*h(16086)=6358 */ {16086, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6737)=6360 */ {6737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6360_l1}, +/*h(10918)=6361 */ {10918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6361_l1}, +/*h(15099)=6362 */ {15099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6362_l1}, +/*h(1569)=6363 */ {1569, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6363_l1}, +/*h(5750)=6364 */ {5750, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6364_l1}, +/*h(9931)=6365 */ {9931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6365_l1}, +/*h(14112)=6366 */ {14112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6366_l1}, +/*h(7347)=6367 */ {7347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6367_l1}, +/*h(4763)=6368 */ {4763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6368_l1}, +/*h(8944)=6369 */ {8944, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6369_l1}, +/*h(2179)=6370 */ {2179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6370_l1}, +/*h(6360)=6371 */ {6360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6371_l1}, +/*h(3776)=6372 */ {3776, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6372_l1}, +/*h(7957)=6373 */ {7957, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6373_l1}, +/*h(12138)=6374 */ {12138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2789)=6377 */ {2789, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6377_l1}, +/*h(6970)=6378 */ {6970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6378_l1}, +/*h(15332)=6379 */ {15332, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6379_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1802)=6381 */ {1802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6381_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10164)=6383 */ {10164, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6383_l1}, +/*h(14345)=6384 */ {14345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15942)=6386 */ {15942, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6386_l1}, +/*h(9177)=6387 */ {9177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10774)=6389 */ {10774, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6389_l1}, +/*h(14955)=6390 */ {14955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12371)=6392 */ {12371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6392_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9787)=6394 */ {9787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6394_l1}, +/*h(7203)=6395 */ {7203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6395_l1}, +/*h(11384)=6396 */ {11384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6396_l1}, +/*h(4619)=6397 */ {4619, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6397_l1}, +/*h(2035)=6398 */ {2035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6398_l1}, +/*h(12981)=6399 */ {12981, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14578)=6401 */ {14578, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6401_l1}, +/*h(7813)=6402 */ {7813, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6402_l1}, +/*h(11994)=6403 */ {11994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6403_l1}, +/*h(9410)=6404 */ {9410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6404_l1}, +/*h(2645)=6405 */ {2645, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6405_l1}, +/*h(6826)=6406 */ {6826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4242)=6408 */ {4242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6408_l1}, +/*h(1658)=6409 */ {1658, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6409_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10020)=6411 */ {10020, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6411_l1}, +/*h(3255)=6412 */ {3255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6412_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4852)=6414 */ {4852, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6414_l1}, +/*h(9033)=6415 */ {9033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3865)=6418 */ {3865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6418_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12227)=6420 */ {12227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13824)=6423 */ {13824, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6423_l1}, +/*h(7059)=6424 */ {7059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6424_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1891)=6427 */ {1891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6427_l1}, +/*h(6072)=6428 */ {6072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6428_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14434)=6430 */ {14434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6430_l1}, +/*h(11850)=6431 */ {11850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6431_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9266)=6433 */ {9266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6433_l1}, +/*h(6682)=6434 */ {6682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6434_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4098)=6436 */ {4098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6436_l1}, +/*h(8279)=6437 */ {8279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3111)=6440 */ {3111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6440_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11473)=6442 */ {11473, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6442_l1}, +/*h(4708)=6443 */ {4708, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6443_l1}, +/*h(8889)=6444 */ {8889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6444_l1}, +/*h(6305)=6445 */ {6305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6445_l1}, +/*h(10486)=6446 */ {10486, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6446_l1}, +/*h(3721)=6447 */ {3721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6447_l1}, +/*h(1137)=6448 */ {1137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6448_l1}, +/*h(5318)=6449 */ {5318, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6449_l1}, +/*h(16264)=6450 */ {16264, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6450_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6915)=6452 */ {6915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6452_l1}, +/*h(150)=6453 */ {150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6453_l1}, +/*h(4331)=6454 */ {4331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6454_l1}, +/*h(1747)=6455 */ {1747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6455_l1}, +/*h(5928)=6456 */ {5928, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14290)=6458 */ {14290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6458_l1}, +/*h(760)=6459 */ {760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9122)=6461 */ {9122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6461_l1}, +/*h(13303)=6462 */ {13303, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3954)=6464 */ {3954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6464_l1}, +/*h(8135)=6465 */ {8135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9732)=6468 */ {9732, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6468_l1}, +/*h(2967)=6469 */ {2967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6469_l1}, +/*h(11329)=6470 */ {11329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6470_l1}, +/*h(15510)=6471 */ {15510, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6471_l1}, +/*h(8745)=6472 */ {8745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6472_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6161)=6474 */ {6161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6474_l1}, +/*h(10342)=6475 */ {10342, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6475_l1}, +/*h(14523)=6476 */ {14523, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6476_l1}, +/*h(11939)=6477 */ {11939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6477_l1}, +/*h(5174)=6478 */ {5174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6478_l1}, +/*h(9355)=6479 */ {9355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6479_l1}, +/*h(6771)=6480 */ {6771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6480_l1}, +/*h(6)=6481 */ {6, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6481_l1}, +/*h(4187)=6482 */ {4187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6482_l1}, +/*h(8368)=6483 */ {8368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6483_l1}, +/*h(1603)=6484 */ {1603, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6484_l1}, +/*h(5784)=6485 */ {5784, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6485_l1}, +/*h(14146)=6486 */ {14146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6486_l1}, +/*h(7381)=6487 */ {7381, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6487_l1}, +/*h(616)=6488 */ {616, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6488_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8978)=6490 */ {8978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6490_l1}, +/*h(13159)=6491 */ {13159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6491_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3810)=6493 */ {3810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6493_l1}, +/*h(1226)=6494 */ {1226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6494_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16353)=6496 */ {16353, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6496_l1}, +/*h(2823)=6497 */ {2823, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6497_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11185)=6499 */ {11185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6499_l1}, +/*h(15366)=6500 */ {15366, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6500_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6017)=6502 */ {6017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6502_l1}, +/*h(10198)=6503 */ {10198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6503_l1}, +/*h(14379)=6504 */ {14379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6504_l1}, +/*h(849)=6505 */ {849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6505_l1}, +/*h(5030)=6506 */ {5030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6506_l1}, +/*h(9211)=6507 */ {9211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6507_l1}, +/*h(13392)=6508 */ {13392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4043)=6510 */ {4043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6510_l1}, +/*h(8224)=6511 */ {8224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6511_l1}, +/*h(12405)=6512 */ {12405, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6512_l1}, +/*h(5640)=6513 */ {5640, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14002)=6515 */ {14002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6515_l1}, +/*h(11418)=6516 */ {11418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6516_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8834)=6518 */ {8834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6518_l1}, +/*h(13015)=6519 */ {13015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6519_l1}, +/*h(6250)=6520 */ {6250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6520_l1}, +/*h(3666)=6521 */ {3666, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6521_l1}, +/*h(7847)=6522 */ {7847, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6522_l1}, +/*h(1082)=6523 */ {1082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6523_l1}, +/*h(16209)=6524 */ {16209, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6524_l1}, +/*h(2679)=6525 */ {2679, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6525_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11041)=6527 */ {11041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6527_l1}, +/*h(15222)=6528 */ {15222, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10054)=6531 */ {10054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6531_l1}, +/*h(14235)=6532 */ {14235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6532_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(705)=6534 */ {705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6534_l1}, +/*h(4886)=6535 */ {4886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6535_l1}, +/*h(9067)=6536 */ {9067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6536_l1}, +/*h(13248)=6537 */ {13248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6537_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3899)=6539 */ {3899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6539_l1}, +/*h(8080)=6540 */ {8080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6540_l1}, +/*h(12261)=6541 */ {12261, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6541_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13858)=6543 */ {13858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6543_l1}, +/*h(7093)=6544 */ {7093, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6544_l1}, +/*h(11274)=6545 */ {11274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6545_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12871)=6547 */ {12871, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6547_l1}, +/*h(6106)=6548 */ {6106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14468)=6550 */ {14468, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6550_l1}, +/*h(938)=6551 */ {938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6551_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16065)=6553 */ {16065, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6553_l1}, +/*h(13481)=6554 */ {13481, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6554_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10897)=6556 */ {10897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6556_l1}, +/*h(15078)=6557 */ {15078, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6557_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5729)=6559 */ {5729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6559_l1}, +/*h(9910)=6560 */ {9910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6560_l1}, +/*h(14091)=6561 */ {14091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6561_l1}, +/*h(11507)=6562 */ {11507, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6562_l1}, +/*h(4742)=6563 */ {4742, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6563_l1}, +/*h(8923)=6564 */ {8923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6564_l1}, +/*h(13104)=6565 */ {13104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6565_l1}, +/*h(6339)=6566 */ {6339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6566_l1}, +/*h(3755)=6567 */ {3755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6567_l1}, +/*h(7936)=6568 */ {7936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6568_l1}, +/*h(1171)=6569 */ {1171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6569_l1}, +/*h(16298)=6570 */ {16298, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6570_l1}, +/*h(2768)=6571 */ {2768, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6571_l1}, +/*h(6949)=6572 */ {6949, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6572_l1}, +/*h(11130)=6573 */ {11130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6573_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5962)=6576 */ {5962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14324)=6578 */ {14324, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(794)=6580 */ {794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6580_l1}, +/*h(15921)=6581 */ {15921, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6581_l1}, +/*h(9156)=6582 */ {9156, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6582_l1}, +/*h(13337)=6583 */ {13337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6583_l1}, +/*h(10753)=6584 */ {10753, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6584_l1}, +/*h(14934)=6585 */ {14934, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6585_l1}, +/*h(8169)=6586 */ {8169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6586_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9766)=6588 */ {9766, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6588_l1}, +/*h(13947)=6589 */ {13947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6589_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11363)=6591 */ {11363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6591_l1}, +/*h(8779)=6592 */ {8779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6592_l1}, +/*h(12960)=6593 */ {12960, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6593_l1}, +/*h(6195)=6594 */ {6195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6594_l1}, +/*h(10376)=6595 */ {10376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6595_l1}, +/*h(3611)=6596 */ {3611, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6596_l1}, +/*h(1027)=6597 */ {1027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6597_l1}, +/*h(11973)=6598 */ {11973, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6598_l1}, +/*h(16154)=6599 */ {16154, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6599_l1}, +/*h(2624)=6600 */ {2624, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6600_l1}, +/*h(6805)=6601 */ {6805, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6601_l1}, +/*h(10986)=6602 */ {10986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6602_l1}, +/*h(8402)=6603 */ {8402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6603_l1}, +/*h(1637)=6604 */ {1637, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6604_l1}, +/*h(5818)=6605 */ {5818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6605_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7415)=6607 */ {7415, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6607_l1}, +/*h(650)=6608 */ {650, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6608_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9012)=6610 */ {9012, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6610_l1}, +/*h(2247)=6611 */ {2247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6611_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3844)=6613 */ {3844, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6613_l1}, +/*h(8025)=6614 */ {8025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6614_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2857)=6617 */ {2857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6617_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11219)=6619 */ {11219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6619_l1}, +/*h(15400)=6620 */ {15400, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6620_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6051)=6622 */ {6051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6622_l1}, +/*h(10232)=6623 */ {10232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6623_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(883)=6626 */ {883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6626_l1}, +/*h(16010)=6627 */ {16010, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6627_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13426)=6629 */ {13426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6629_l1}, +/*h(10842)=6630 */ {10842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6630_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8258)=6632 */ {8258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6632_l1}, +/*h(12439)=6633 */ {12439, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6633_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3090)=6635 */ {3090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6635_l1}, +/*h(7271)=6636 */ {7271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6636_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8868)=6638 */ {8868, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6638_l1}, +/*h(2103)=6639 */ {2103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6639_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10465)=6641 */ {10465, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6641_l1}, +/*h(3700)=6642 */ {3700, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6642_l1}, +/*h(7881)=6643 */ {7881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6643_l1}, +/*h(5297)=6644 */ {5297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6644_l1}, +/*h(16243)=6645 */ {16243, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6645_l1}, +/*h(2713)=6646 */ {2713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6646_l1}, +/*h(129)=6647 */ {129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6647_l1}, +/*h(11075)=6648 */ {11075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6648_l1}, +/*h(15256)=6649 */ {15256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6649_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5907)=6651 */ {5907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6651_l1}, +/*h(3323)=6652 */ {3323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=6654 */ {739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6654_l1}, +/*h(4920)=6655 */ {4920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13282)=6657 */ {13282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8114)=6660 */ {8114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6660_l1}, +/*h(12295)=6661 */ {12295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2946)=6663 */ {2946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6663_l1}, +/*h(7127)=6664 */ {7127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6664_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15489)=6666 */ {15489, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6666_l1}, +/*h(1959)=6667 */ {1959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6667_l1}, +/*h(12905)=6668 */ {12905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6668_l1}, +/*h(10321)=6669 */ {10321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6669_l1}, +/*h(14502)=6670 */ {14502, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6670_l1}, +/*h(7737)=6671 */ {7737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6671_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16099)=6673 */ {16099, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6673_l1}, +/*h(9334)=6674 */ {9334, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6674_l1}, +/*h(13515)=6675 */ {13515, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6675_l1}, +/*h(10931)=6676 */ {10931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6676_l1}, +/*h(4166)=6677 */ {4166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6677_l1}, +/*h(8347)=6678 */ {8347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6678_l1}, +/*h(5763)=6679 */ {5763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6679_l1}, +/*h(9944)=6680 */ {9944, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6680_l1}, +/*h(3179)=6681 */ {3179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6681_l1}, +/*h(7360)=6682 */ {7360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6682_l1}, +/*h(595)=6683 */ {595, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6683_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13138)=6685 */ {13138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6685_l1}, +/*h(6373)=6686 */ {6373, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1205)=6689 */ {1205, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6689_l1}, +/*h(12151)=6690 */ {12151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6690_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2802)=6692 */ {2802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6692_l1}, +/*h(6983)=6693 */ {6983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15345)=6695 */ {15345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6695_l1}, +/*h(1815)=6696 */ {1815, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6696_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10177)=6698 */ {10177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6698_l1}, +/*h(14358)=6699 */ {14358, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6699_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15955)=6701 */ {15955, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6701_l1}, +/*h(9190)=6702 */ {9190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6702_l1}, +/*h(13371)=6703 */ {13371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6703_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4022)=6705 */ {4022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6705_l1}, +/*h(8203)=6706 */ {8203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6706_l1}, +/*h(12384)=6707 */ {12384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6707_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3035)=6709 */ {3035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6709_l1}, +/*h(7216)=6710 */ {7216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6710_l1}, +/*h(11397)=6711 */ {11397, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6711_l1}, +/*h(15578)=6712 */ {15578, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6712_l1}, +/*h(2048)=6713 */ {2048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6713_l1}, +/*h(12994)=6714 */ {12994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6714_l1}, +/*h(10410)=6715 */ {10410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7826)=6717 */ {7826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6717_l1}, +/*h(12007)=6718 */ {12007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6718_l1}, +/*h(5242)=6719 */ {5242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6719_l1}, +/*h(2658)=6720 */ {2658, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6720_l1}, +/*h(6839)=6721 */ {6839, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6721_l1}, +/*h(74)=6722 */ {74, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6722_l1}, +/*h(15201)=6723 */ {15201, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6723_l1}, +/*h(1671)=6724 */ {1671, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6724_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10033)=6726 */ {10033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6726_l1}, +/*h(14214)=6727 */ {14214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4865)=6729 */ {4865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6729_l1}, +/*h(9046)=6730 */ {9046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6730_l1}, +/*h(13227)=6731 */ {13227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6731_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8059)=6735 */ {8059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6735_l1}, +/*h(12240)=6736 */ {12240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6736_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2891)=6738 */ {2891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6738_l1}, +/*h(7072)=6739 */ {7072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6739_l1}, +/*h(11253)=6740 */ {11253, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6740_l1}, +/*h(15434)=6741 */ {15434, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6741_l1}, +/*h(12850)=6742 */ {12850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6742_l1}, +/*h(6085)=6743 */ {6085, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6743_l1}, +/*h(10266)=6744 */ {10266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6744_l1}, +/*h(7682)=6745 */ {7682, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6745_l1}, +/*h(11863)=6746 */ {11863, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6746_l1}, +/*h(5098)=6747 */ {5098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13460)=6749 */ {13460, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6749_l1}, +/*h(6695)=6750 */ {6695, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15057)=6752 */ {15057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6752_l1}, +/*h(12473)=6753 */ {12473, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6753_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9889)=6755 */ {9889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6755_l1}, +/*h(14070)=6756 */ {14070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4721)=6758 */ {4721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6758_l1}, +/*h(8902)=6759 */ {8902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6759_l1}, +/*h(13083)=6760 */ {13083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6760_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3734)=6762 */ {3734, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6762_l1}, +/*h(7915)=6763 */ {7915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6763_l1}, +/*h(12096)=6764 */ {12096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6764_l1}, +/*h(5331)=6765 */ {5331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6765_l1}, +/*h(2747)=6766 */ {2747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6766_l1}, +/*h(6928)=6767 */ {6928, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6767_l1}, +/*h(163)=6768 */ {163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6768_l1}, +/*h(15290)=6769 */ {15290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6769_l1}, +/*h(1760)=6770 */ {1760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6770_l1}, +/*h(5941)=6771 */ {5941, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6771_l1}, +/*h(10122)=6772 */ {10122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6772_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(773)=6774 */ {773, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6774_l1}, +/*h(4954)=6775 */ {4954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6775_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13316)=6777 */ {13316, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6777_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14913)=6780 */ {14913, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6780_l1}, +/*h(8148)=6781 */ {8148, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6781_l1}, +/*h(12329)=6782 */ {12329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6782_l1}, +/*h(9745)=6783 */ {9745, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6783_l1}, +/*h(13926)=6784 */ {13926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6784_l1}, +/*h(7161)=6785 */ {7161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6785_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8758)=6787 */ {8758, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6787_l1}, +/*h(12939)=6788 */ {12939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10355)=6790 */ {10355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6790_l1}, +/*h(7771)=6791 */ {7771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6791_l1}, +/*h(11952)=6792 */ {11952, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6792_l1}, +/*h(5187)=6793 */ {5187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6793_l1}, +/*h(9368)=6794 */ {9368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6794_l1}, +/*h(2603)=6795 */ {2603, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6795_l1}, +/*h(19)=6796 */ {19, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6796_l1}, +/*h(10965)=6797 */ {10965, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6797_l1}, +/*h(15146)=6798 */ {15146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6798_l1}, +/*h(1616)=6799 */ {1616, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6799_l1}, +/*h(5797)=6800 */ {5797, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6800_l1}, +/*h(9978)=6801 */ {9978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6801_l1}, +/*h(7394)=6802 */ {7394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6802_l1}, +/*h(629)=6803 */ {629, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6803_l1}, +/*h(4810)=6804 */ {4810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6804_l1}, +/*h(2226)=6805 */ {2226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6805_l1}, +/*h(13172)=6806 */ {13172, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6806_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8004)=6809 */ {8004, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6809_l1}, +/*h(1239)=6810 */ {1239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6810_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2836)=6812 */ {2836, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6812_l1}, +/*h(7017)=6813 */ {7017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6813_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15379)=6815 */ {15379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6815_l1}, +/*h(1849)=6816 */ {1849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6816_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10211)=6818 */ {10211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6818_l1}, +/*h(14392)=6819 */ {14392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6819_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5043)=6821 */ {5043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6821_l1}, +/*h(15989)=6822 */ {15989, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6822_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10821)=6825 */ {10821, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6825_l1}, +/*h(15002)=6826 */ {15002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6826_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12418)=6828 */ {12418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6828_l1}, +/*h(9834)=6829 */ {9834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6829_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7250)=6831 */ {7250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6831_l1}, +/*h(4666)=6832 */ {4666, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6832_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2082)=6834 */ {2082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6834_l1}, +/*h(6263)=6835 */ {6263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6835_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7860)=6837 */ {7860, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6837_l1}, +/*h(1095)=6838 */ {1095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6838_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9457)=6840 */ {9457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6840_l1}, +/*h(2692)=6841 */ {2692, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6841_l1}, +/*h(6873)=6842 */ {6873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6842_l1}, +/*h(4289)=6843 */ {4289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6843_l1}, +/*h(15235)=6844 */ {15235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6844_l1}, +/*h(1705)=6845 */ {1705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6845_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10067)=6847 */ {10067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6847_l1}, +/*h(14248)=6848 */ {14248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6848_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4899)=6850 */ {4899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6850_l1}, +/*h(9080)=6851 */ {9080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6851_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14858)=6854 */ {14858, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12274)=6856 */ {12274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6856_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7106)=6859 */ {7106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6859_l1}, +/*h(11287)=6860 */ {11287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6860_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1938)=6862 */ {1938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6862_l1}, +/*h(6119)=6863 */ {6119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6863_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14481)=6865 */ {14481, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6865_l1}, +/*h(951)=6866 */ {951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6866_l1}, +/*h(11897)=6867 */ {11897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6867_l1}, +/*h(9313)=6868 */ {9313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6868_l1}, +/*h(13494)=6869 */ {13494, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6869_l1}, +/*h(6729)=6870 */ {6729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6870_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15091)=6872 */ {15091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6872_l1}, +/*h(8326)=6873 */ {8326, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6873_l1}, +/*h(12507)=6874 */ {12507, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6874_l1}, +/*h(9923)=6875 */ {9923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6875_l1}, +/*h(3158)=6876 */ {3158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6876_l1}, +/*h(7339)=6877 */ {7339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6877_l1}, +/*h(4755)=6878 */ {4755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6878_l1}, +/*h(8936)=6879 */ {8936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6879_l1}, +/*h(2171)=6880 */ {2171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6880_l1}, +/*h(6352)=6881 */ {6352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6881_l1}, +/*h(3768)=6882 */ {3768, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6882_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12130)=6884 */ {12130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6884_l1}, +/*h(16311)=6885 */ {16311, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6885_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6962)=6888 */ {6962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6888_l1}, +/*h(11143)=6889 */ {11143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6889_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1794)=6891 */ {1794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6891_l1}, +/*h(5975)=6892 */ {5975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6892_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14337)=6894 */ {14337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6894_l1}, +/*h(807)=6895 */ {807, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6895_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9169)=6897 */ {9169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6897_l1}, +/*h(13350)=6898 */ {13350, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6898_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14947)=6900 */ {14947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6900_l1}, +/*h(8182)=6901 */ {8182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6901_l1}, +/*h(12363)=6902 */ {12363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6902_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3014)=6904 */ {3014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6904_l1}, +/*h(7195)=6905 */ {7195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6905_l1}, +/*h(11376)=6906 */ {11376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6906_l1}, +/*h(4611)=6907 */ {4611, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6907_l1}, +/*h(2027)=6908 */ {2027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6908_l1}, +/*h(6208)=6909 */ {6208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6909_l1}, +/*h(10389)=6910 */ {10389, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6910_l1}, +/*h(14570)=6911 */ {14570, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6911_l1}, +/*h(1040)=6912 */ {1040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6912_l1}, +/*h(11986)=6913 */ {11986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6913_l1}, +/*h(9402)=6914 */ {9402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6914_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6818)=6916 */ {6818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6916_l1}, +/*h(10999)=6917 */ {10999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6917_l1}, +/*h(4234)=6918 */ {4234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6918_l1}, +/*h(1650)=6919 */ {1650, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6919_l1}, +/*h(5831)=6920 */ {5831, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14193)=6922 */ {14193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6922_l1}, +/*h(663)=6923 */ {663, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6923_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9025)=6925 */ {9025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6925_l1}, +/*h(13206)=6926 */ {13206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6926_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3857)=6928 */ {3857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6928_l1}, +/*h(8038)=6929 */ {8038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6929_l1}, +/*h(12219)=6930 */ {12219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6930_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2870)=6933 */ {2870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6933_l1}, +/*h(7051)=6934 */ {7051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6934_l1}, +/*h(15413)=6935 */ {15413, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6935_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1883)=6937 */ {1883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6937_l1}, +/*h(6064)=6938 */ {6064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6938_l1}, +/*h(10245)=6939 */ {10245, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6939_l1}, +/*h(14426)=6940 */ {14426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6940_l1}, +/*h(11842)=6941 */ {11842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6941_l1}, +/*h(16023)=6942 */ {16023, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6942_l1}, +/*h(9258)=6943 */ {9258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6943_l1}, +/*h(6674)=6944 */ {6674, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6944_l1}, +/*h(10855)=6945 */ {10855, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6945_l1}, +/*h(4090)=6946 */ {4090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6946_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12452)=6948 */ {12452, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6948_l1}, +/*h(5687)=6949 */ {5687, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6949_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14049)=6951 */ {14049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6951_l1}, +/*h(519)=6952 */ {519, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6952_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8881)=6954 */ {8881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6954_l1}, +/*h(13062)=6955 */ {13062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6955_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3713)=6957 */ {3713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6957_l1}, +/*h(7894)=6958 */ {7894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6958_l1}, +/*h(12075)=6959 */ {12075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6959_l1}, +/*h(16256)=6960 */ {16256, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6960_l1}, +/*h(2726)=6961 */ {2726, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6961_l1}, +/*h(6907)=6962 */ {6907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6962_l1}, +/*h(11088)=6963 */ {11088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6963_l1}, +/*h(4323)=6964 */ {4323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6964_l1}, +/*h(1739)=6965 */ {1739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6965_l1}, +/*h(5920)=6966 */ {5920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6966_l1}, +/*h(10101)=6967 */ {10101, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6967_l1}, +/*h(14282)=6968 */ {14282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6968_l1}, +/*h(752)=6969 */ {752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6969_l1}, +/*h(4933)=6970 */ {4933, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6970_l1}, +/*h(9114)=6971 */ {9114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6971_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3946)=6974 */ {3946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6974_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12308)=6976 */ {12308, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6976_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13905)=6979 */ {13905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6979_l1}, +/*h(7140)=6980 */ {7140, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6980_l1}, +/*h(11321)=6981 */ {11321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6981_l1}, +/*h(8737)=6982 */ {8737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6982_l1}, +/*h(12918)=6983 */ {12918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6983_l1}, +/*h(6153)=6984 */ {6153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6984_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14515)=6986 */ {14515, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6986_l1}, +/*h(11931)=6987 */ {11931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6987_l1}, +/*h(16112)=6988 */ {16112, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6988_l1}, +/*h(2582)=6989 */ {2582, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6989_l1}, +/*h(6763)=6990 */ {6763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6990_l1}, +/*h(10944)=6991 */ {10944, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6991_l1}, +/*h(4179)=6992 */ {4179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6992_l1}, +/*h(8360)=6993 */ {8360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6993_l1}, +/*h(1595)=6994 */ {1595, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6994_l1}, +/*h(5776)=6995 */ {5776, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6995_l1}, +/*h(14138)=6996 */ {14138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6996_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(608)=6998 */ {608, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6998_l1}, +/*h(4789)=6999 */ {4789, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_6999_l1}, +/*h(8970)=7000 */ {8970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7000_l1}, +/*h(6386)=7001 */ {6386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7001_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3802)=7003 */ {3802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7003_l1}, +/*h(1218)=7004 */ {1218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7004_l1}, +/*h(12164)=7005 */ {12164, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7005_l1}, +/*h(16345)=7006 */ {16345, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7006_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6996)=7008 */ {6996, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7008_l1}, +/*h(231)=7009 */ {231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7009_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1828)=7011 */ {1828, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7011_l1}, +/*h(6009)=7012 */ {6009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7012_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14371)=7014 */ {14371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7014_l1}, +/*h(841)=7015 */ {841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7015_l1}, +/*h(11787)=7016 */ {11787, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7016_l1}, +/*h(9203)=7017 */ {9203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7017_l1}, +/*h(13384)=7018 */ {13384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7018_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4035)=7020 */ {4035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7020_l1}, +/*h(14981)=7021 */ {14981, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5632)=7023 */ {5632, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7023_l1}, +/*h(9813)=7024 */ {9813, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7024_l1}, +/*h(13994)=7025 */ {13994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11410)=7027 */ {11410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7027_l1}, +/*h(8826)=7028 */ {8826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7028_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6242)=7030 */ {6242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7030_l1}, +/*h(10423)=7031 */ {10423, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7031_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1074)=7033 */ {1074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7033_l1}, +/*h(5255)=7034 */ {5255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7034_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6852)=7036 */ {6852, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7036_l1}, +/*h(87)=7037 */ {87, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7037_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1684)=7040 */ {1684, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7040_l1}, +/*h(5865)=7041 */ {5865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7041_l1}, +/*h(14227)=7042 */ {14227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7042_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(697)=7044 */ {697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7044_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9059)=7046 */ {9059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7046_l1}, +/*h(13240)=7047 */ {13240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8072)=7050 */ {8072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7050_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13850)=7053 */ {13850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7053_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11266)=7055 */ {11266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7055_l1}, +/*h(15447)=7056 */ {15447, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7056_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6098)=7058 */ {6098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7058_l1}, +/*h(10279)=7059 */ {10279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7059_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(930)=7061 */ {930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7061_l1}, +/*h(5111)=7062 */ {5111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7062_l1}, +/*h(16057)=7063 */ {16057, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7063_l1}, +/*h(13473)=7064 */ {13473, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7064_l1}, +/*h(6708)=7065 */ {6708, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7065_l1}, +/*h(10889)=7066 */ {10889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7066_l1}, +/*h(8305)=7067 */ {8305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7067_l1}, +/*h(12486)=7068 */ {12486, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7068_l1}, +/*h(5721)=7069 */ {5721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7069_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14083)=7071 */ {14083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7071_l1}, +/*h(7318)=7072 */ {7318, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7072_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8915)=7074 */ {8915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7074_l1}, +/*h(2150)=7075 */ {2150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7075_l1}, +/*h(6331)=7076 */ {6331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7076_l1}, +/*h(3747)=7077 */ {3747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7077_l1}, +/*h(7928)=7078 */ {7928, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7078_l1}, +/*h(1163)=7079 */ {1163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7079_l1}, +/*h(16290)=7080 */ {16290, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7080_l1}, +/*h(2760)=7081 */ {2760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7081_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11122)=7083 */ {11122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7083_l1}, +/*h(15303)=7084 */ {15303, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7084_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10135)=7087 */ {10135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7087_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(786)=7090 */ {786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7090_l1}, +/*h(4967)=7091 */ {4967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7091_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13329)=7093 */ {13329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8161)=7096 */ {8161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7096_l1}, +/*h(12342)=7097 */ {12342, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7097_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13939)=7099 */ {13939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7099_l1}, +/*h(7174)=7100 */ {7174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7100_l1}, +/*h(11355)=7101 */ {11355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7101_l1}, +/*h(8771)=7102 */ {8771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7102_l1}, +/*h(2006)=7103 */ {2006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7103_l1}, +/*h(6187)=7104 */ {6187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7104_l1}, +/*h(10368)=7105 */ {10368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7105_l1}, +/*h(3603)=7106 */ {3603, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7106_l1}, +/*h(1019)=7107 */ {1019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7107_l1}, +/*h(5200)=7108 */ {5200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7108_l1}, +/*h(16146)=7109 */ {16146, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7109_l1}, +/*h(13562)=7110 */ {13562, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7110_l1}, +/*h(32)=7111 */ {32, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7111_l1}, +/*h(10978)=7112 */ {10978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7112_l1}, +/*h(15159)=7113 */ {15159, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5810)=7115 */ {5810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7115_l1}, +/*h(9991)=7116 */ {9991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7116_l1}, +/*h(3226)=7117 */ {3226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7117_l1}, +/*h(642)=7118 */ {642, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7118_l1}, +/*h(4823)=7119 */ {4823, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13185)=7121 */ {13185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8017)=7124 */ {8017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7124_l1}, +/*h(12198)=7125 */ {12198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7125_l1}, +/*h(16379)=7126 */ {16379, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7126_l1}, +/*h(2849)=7127 */ {2849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7127_l1}, +/*h(7030)=7128 */ {7030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7128_l1}, +/*h(11211)=7129 */ {11211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7129_l1}, +/*h(15392)=7130 */ {15392, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1862)=7132 */ {1862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7132_l1}, +/*h(6043)=7133 */ {6043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7133_l1}, +/*h(14405)=7134 */ {14405, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(875)=7136 */ {875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7136_l1}, +/*h(16002)=7137 */ {16002, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7137_l1}, +/*h(9237)=7138 */ {9237, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7138_l1}, +/*h(13418)=7139 */ {13418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7139_l1}, +/*h(10834)=7140 */ {10834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7140_l1}, +/*h(15015)=7141 */ {15015, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7141_l1}, +/*h(8250)=7142 */ {8250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7142_l1}, +/*h(5666)=7143 */ {5666, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7143_l1}, +/*h(9847)=7144 */ {9847, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7144_l1}, +/*h(3082)=7145 */ {3082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11444)=7147 */ {11444, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7147_l1}, +/*h(4679)=7148 */ {4679, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7148_l1}, +/*h(13041)=7149 */ {13041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7149_l1}, +/*h(6276)=7150 */ {6276, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7150_l1}, +/*h(10457)=7151 */ {10457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7873)=7153 */ {7873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7153_l1}, +/*h(12054)=7154 */ {12054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7154_l1}, +/*h(16235)=7155 */ {16235, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7155_l1}, +/*h(2705)=7156 */ {2705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7156_l1}, +/*h(6886)=7157 */ {6886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7157_l1}, +/*h(11067)=7158 */ {11067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7158_l1}, +/*h(15248)=7159 */ {15248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7159_l1}, +/*h(1718)=7160 */ {1718, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7160_l1}, +/*h(5899)=7161 */ {5899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7161_l1}, +/*h(10080)=7162 */ {10080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7162_l1}, +/*h(3315)=7163 */ {3315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7163_l1}, +/*h(731)=7164 */ {731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7164_l1}, +/*h(4912)=7165 */ {4912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7165_l1}, +/*h(9093)=7166 */ {9093, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7166_l1}, +/*h(13274)=7167 */ {13274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3925)=7169 */ {3925, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7169_l1}, +/*h(8106)=7170 */ {8106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2938)=7173 */ {2938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11300)=7175 */ {11300, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7175_l1}, +/*h(15481)=7176 */ {15481, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12897)=7178 */ {12897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7178_l1}, +/*h(10313)=7179 */ {10313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7729)=7181 */ {7729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7181_l1}, +/*h(11910)=7182 */ {11910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7182_l1}, +/*h(16091)=7183 */ {16091, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7183_l1}, +/*h(2561)=7184 */ {2561, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7184_l1}, +/*h(6742)=7185 */ {6742, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7185_l1}, +/*h(10923)=7186 */ {10923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7186_l1}, +/*h(15104)=7187 */ {15104, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7187_l1}, +/*h(8339)=7188 */ {8339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7188_l1}, +/*h(5755)=7189 */ {5755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7189_l1}, +/*h(9936)=7190 */ {9936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7190_l1}, +/*h(3171)=7191 */ {3171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7191_l1}, +/*h(7352)=7192 */ {7352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7192_l1}, +/*h(587)=7193 */ {587, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7193_l1}, +/*h(8949)=7194 */ {8949, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7194_l1}, +/*h(13130)=7195 */ {13130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3781)=7198 */ {3781, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7198_l1}, +/*h(7962)=7199 */ {7962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16324)=7201 */ {16324, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7201_l1}, +/*h(2794)=7202 */ {2794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7202_l1}, +/*h(210)=7203 */ {210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7203_l1}, +/*h(11156)=7204 */ {11156, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7204_l1}, +/*h(15337)=7205 */ {15337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5988)=7207 */ {5988, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7207_l1}, +/*h(10169)=7208 */ {10169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(820)=7210 */ {820, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7210_l1}, +/*h(15947)=7211 */ {15947, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7211_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13363)=7213 */ {13363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10779)=7215 */ {10779, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7215_l1}, +/*h(8195)=7216 */ {8195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7216_l1}, +/*h(12376)=7217 */ {12376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3027)=7219 */ {3027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7219_l1}, +/*h(13973)=7220 */ {13973, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15570)=7222 */ {15570, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7222_l1}, +/*h(8805)=7223 */ {8805, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7223_l1}, +/*h(12986)=7224 */ {12986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7224_l1}, +/*h(10402)=7225 */ {10402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7225_l1}, +/*h(14583)=7226 */ {14583, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7226_l1}, +/*h(7818)=7227 */ {7818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5234)=7229 */ {5234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7229_l1}, +/*h(2650)=7230 */ {2650, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(66)=7232 */ {66, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7232_l1}, +/*h(4247)=7233 */ {4247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5844)=7235 */ {5844, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7235_l1}, +/*h(10025)=7236 */ {10025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7236_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4857)=7239 */ {4857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7239_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13219)=7241 */ {13219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7241_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8051)=7245 */ {8051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7245_l1}, +/*h(12232)=7246 */ {12232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7246_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2883)=7248 */ {2883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7248_l1}, +/*h(7064)=7249 */ {7064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15426)=7251 */ {15426, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7251_l1}, +/*h(12842)=7252 */ {12842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10258)=7254 */ {10258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7254_l1}, +/*h(14439)=7255 */ {14439, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7255_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5090)=7257 */ {5090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7257_l1}, +/*h(9271)=7258 */ {9271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4103)=7261 */ {4103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7261_l1}, +/*h(15049)=7262 */ {15049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7262_l1}, +/*h(12465)=7263 */ {12465, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7263_l1}, +/*h(5700)=7264 */ {5700, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7264_l1}, +/*h(9881)=7265 */ {9881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7265_l1}, +/*h(7297)=7266 */ {7297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7266_l1}, +/*h(11478)=7267 */ {11478, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7267_l1}, +/*h(4713)=7268 */ {4713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7268_l1}, +/*h(2129)=7269 */ {2129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7269_l1}, +/*h(13075)=7270 */ {13075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7270_l1}, +/*h(10491)=7271 */ {10491, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7907)=7273 */ {7907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7273_l1}, +/*h(1142)=7274 */ {1142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7274_l1}, +/*h(5323)=7275 */ {5323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7275_l1}, +/*h(2739)=7276 */ {2739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7276_l1}, +/*h(6920)=7277 */ {6920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7277_l1}, +/*h(155)=7278 */ {155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7278_l1}, +/*h(15282)=7279 */ {15282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7279_l1}, +/*h(1752)=7280 */ {1752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7280_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10114)=7282 */ {10114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7282_l1}, +/*h(14295)=7283 */ {14295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4946)=7285 */ {4946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7285_l1}, +/*h(9127)=7286 */ {9127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3959)=7290 */ {3959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12321)=7292 */ {12321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7292_l1}, +/*h(9737)=7293 */ {9737, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7153)=7295 */ {7153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7295_l1}, +/*h(11334)=7296 */ {11334, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7296_l1}, +/*h(15515)=7297 */ {15515, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7297_l1}, +/*h(12931)=7298 */ {12931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7298_l1}, +/*h(6166)=7299 */ {6166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7299_l1}, +/*h(10347)=7300 */ {10347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7300_l1}, +/*h(7763)=7301 */ {7763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7301_l1}, +/*h(998)=7302 */ {998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7302_l1}, +/*h(5179)=7303 */ {5179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7303_l1}, +/*h(9360)=7304 */ {9360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7304_l1}, +/*h(2595)=7305 */ {2595, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7305_l1}, +/*h(11)=7306 */ {11, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7306_l1}, +/*h(4192)=7307 */ {4192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7307_l1}, +/*h(15138)=7308 */ {15138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7308_l1}, +/*h(1608)=7309 */ {1608, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9970)=7311 */ {9970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7311_l1}, +/*h(14151)=7312 */ {14151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4802)=7314 */ {4802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7314_l1}, +/*h(8983)=7315 */ {8983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3815)=7318 */ {3815, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12177)=7320 */ {12177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7320_l1}, +/*h(16358)=7321 */ {16358, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7321_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7009)=7323 */ {7009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7323_l1}, +/*h(11190)=7324 */ {11190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7324_l1}, +/*h(15371)=7325 */ {15371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7325_l1}, +/*h(1841)=7326 */ {1841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7326_l1}, +/*h(6022)=7327 */ {6022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7327_l1}, +/*h(10203)=7328 */ {10203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7328_l1}, +/*h(14384)=7329 */ {14384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7329_l1}, +/*h(854)=7330 */ {854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7330_l1}, +/*h(5035)=7331 */ {5035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7331_l1}, +/*h(9216)=7332 */ {9216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7332_l1}, +/*h(13397)=7333 */ {13397, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14994)=7336 */ {14994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7336_l1}, +/*h(8229)=7337 */ {8229, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7337_l1}, +/*h(12410)=7338 */ {12410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7338_l1}, +/*h(9826)=7339 */ {9826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7339_l1}, +/*h(14007)=7340 */ {14007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7340_l1}, +/*h(7242)=7341 */ {7242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7341_l1}, +/*h(4658)=7342 */ {4658, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7342_l1}, +/*h(8839)=7343 */ {8839, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7343_l1}, +/*h(2074)=7344 */ {2074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7344_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3671)=7346 */ {3671, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7346_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12033)=7348 */ {12033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7348_l1}, +/*h(16214)=7349 */ {16214, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7349_l1}, +/*h(9449)=7350 */ {9449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7350_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6865)=7352 */ {6865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7352_l1}, +/*h(11046)=7353 */ {11046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7353_l1}, +/*h(15227)=7354 */ {15227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7354_l1}, +/*h(1697)=7355 */ {1697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7355_l1}, +/*h(5878)=7356 */ {5878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7356_l1}, +/*h(10059)=7357 */ {10059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7357_l1}, +/*h(14240)=7358 */ {14240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7358_l1}, +/*h(710)=7359 */ {710, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7359_l1}, +/*h(4891)=7360 */ {4891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7360_l1}, +/*h(9072)=7361 */ {9072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7361_l1}, +/*h(13253)=7362 */ {13253, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7362_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14850)=7364 */ {14850, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7364_l1}, +/*h(8085)=7365 */ {8085, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7365_l1}, +/*h(12266)=7366 */ {12266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2917)=7368 */ {2917, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7368_l1}, +/*h(7098)=7369 */ {7098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7369_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15460)=7371 */ {15460, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7371_l1}, +/*h(1930)=7372 */ {1930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10292)=7374 */ {10292, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7374_l1}, +/*h(14473)=7375 */ {14473, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7375_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11889)=7377 */ {11889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7377_l1}, +/*h(16070)=7378 */ {16070, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6721)=7380 */ {6721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7380_l1}, +/*h(10902)=7381 */ {10902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7381_l1}, +/*h(15083)=7382 */ {15083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7382_l1}, +/*h(1553)=7383 */ {1553, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7383_l1}, +/*h(12499)=7384 */ {12499, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7384_l1}, +/*h(9915)=7385 */ {9915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7385_l1}, +/*h(14096)=7386 */ {14096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7386_l1}, +/*h(566)=7387 */ {566, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7387_l1}, +/*h(4747)=7388 */ {4747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7388_l1}, +/*h(8928)=7389 */ {8928, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7389_l1}, +/*h(2163)=7390 */ {2163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7390_l1}, +/*h(6344)=7391 */ {6344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7391_l1}, +/*h(3760)=7392 */ {3760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7392_l1}, +/*h(7941)=7393 */ {7941, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7393_l1}, +/*h(12122)=7394 */ {12122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2773)=7397 */ {2773, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7397_l1}, +/*h(6954)=7398 */ {6954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15316)=7400 */ {15316, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7400_l1}, +/*h(1786)=7401 */ {1786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7401_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10148)=7403 */ {10148, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7403_l1}, +/*h(14329)=7404 */ {14329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7404_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15926)=7406 */ {15926, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7406_l1}, +/*h(9161)=7407 */ {9161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7407_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10758)=7409 */ {10758, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7409_l1}, +/*h(14939)=7410 */ {14939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12355)=7412 */ {12355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7412_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9771)=7414 */ {9771, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7414_l1}, +/*h(7187)=7415 */ {7187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7415_l1}, +/*h(11368)=7416 */ {11368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7416_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2019)=7418 */ {2019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7418_l1}, +/*h(12965)=7419 */ {12965, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14562)=7421 */ {14562, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7421_l1}, +/*h(7797)=7422 */ {7797, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7422_l1}, +/*h(11978)=7423 */ {11978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7423_l1}, +/*h(9394)=7424 */ {9394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7424_l1}, +/*h(2629)=7425 */ {2629, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7425_l1}, +/*h(6810)=7426 */ {6810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7426_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4226)=7428 */ {4226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7428_l1}, +/*h(8407)=7429 */ {8407, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7429_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10004)=7431 */ {10004, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7431_l1}, +/*h(3239)=7432 */ {3239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7432_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4836)=7434 */ {4836, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7434_l1}, +/*h(9017)=7435 */ {9017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3849)=7438 */ {3849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7438_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12211)=7440 */ {12211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7440_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7043)=7444 */ {7043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7444_l1}, +/*h(11224)=7445 */ {11224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1875)=7447 */ {1875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7447_l1}, +/*h(6056)=7448 */ {6056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14418)=7450 */ {14418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7450_l1}, +/*h(11834)=7451 */ {11834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7451_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9250)=7453 */ {9250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7453_l1}, +/*h(13431)=7454 */ {13431, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4082)=7456 */ {4082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7456_l1}, +/*h(8263)=7457 */ {8263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7457_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3095)=7460 */ {3095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7460_l1}, +/*h(14041)=7461 */ {14041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7461_l1}, +/*h(11457)=7462 */ {11457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7462_l1}, +/*h(4692)=7463 */ {4692, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7463_l1}, +/*h(8873)=7464 */ {8873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7464_l1}, +/*h(6289)=7465 */ {6289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7465_l1}, +/*h(10470)=7466 */ {10470, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7466_l1}, +/*h(3705)=7467 */ {3705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7467_l1}, +/*h(1121)=7468 */ {1121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7468_l1}, +/*h(5302)=7469 */ {5302, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7469_l1}, +/*h(16248)=7470 */ {16248, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7470_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6899)=7472 */ {6899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7472_l1}, +/*h(134)=7473 */ {134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7473_l1}, +/*h(4315)=7474 */ {4315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7474_l1}, +/*h(1731)=7475 */ {1731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7475_l1}, +/*h(5912)=7476 */ {5912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14274)=7478 */ {14274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7478_l1}, +/*h(744)=7479 */ {744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7479_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9106)=7481 */ {9106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7481_l1}, +/*h(13287)=7482 */ {13287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7482_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3938)=7484 */ {3938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7484_l1}, +/*h(8119)=7485 */ {8119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7485_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2951)=7489 */ {2951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7489_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11313)=7491 */ {11313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7491_l1}, +/*h(15494)=7492 */ {15494, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7492_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6145)=7494 */ {6145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7494_l1}, +/*h(10326)=7495 */ {10326, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7495_l1}, +/*h(14507)=7496 */ {14507, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7496_l1}, +/*h(11923)=7497 */ {11923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7497_l1}, +/*h(5158)=7498 */ {5158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7498_l1}, +/*h(9339)=7499 */ {9339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7499_l1}, +/*h(6755)=7500 */ {6755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7500_l1}, +/*h(10936)=7501 */ {10936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7501_l1}, +/*h(4171)=7502 */ {4171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7502_l1}, +/*h(8352)=7503 */ {8352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7503_l1}, +/*h(1587)=7504 */ {1587, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7504_l1}, +/*h(5768)=7505 */ {5768, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7505_l1}, +/*h(3184)=7506 */ {3184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7506_l1}, +/*h(7365)=7507 */ {7365, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7507_l1}, +/*h(600)=7508 */ {600, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8962)=7510 */ {8962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7510_l1}, +/*h(13143)=7511 */ {13143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7511_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3794)=7513 */ {3794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7513_l1}, +/*h(1210)=7514 */ {1210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7514_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16337)=7516 */ {16337, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7516_l1}, +/*h(2807)=7517 */ {2807, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7517_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11169)=7519 */ {11169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7519_l1}, +/*h(15350)=7520 */ {15350, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7520_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6001)=7522 */ {6001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7522_l1}, +/*h(10182)=7523 */ {10182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7523_l1}, +/*h(14363)=7524 */ {14363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7524_l1}, +/*h(833)=7525 */ {833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7525_l1}, +/*h(5014)=7526 */ {5014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7526_l1}, +/*h(9195)=7527 */ {9195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7527_l1}, +/*h(13376)=7528 */ {13376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4027)=7530 */ {4027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7530_l1}, +/*h(8208)=7531 */ {8208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7531_l1}, +/*h(12389)=7532 */ {12389, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7532_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13986)=7535 */ {13986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7535_l1}, +/*h(7221)=7536 */ {7221, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7536_l1}, +/*h(11402)=7537 */ {11402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7537_l1}, +/*h(8818)=7538 */ {8818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7538_l1}, +/*h(12999)=7539 */ {12999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7539_l1}, +/*h(6234)=7540 */ {6234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7540_l1}, +/*h(3650)=7541 */ {3650, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7541_l1}, +/*h(7831)=7542 */ {7831, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7542_l1}, +/*h(1066)=7543 */ {1066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7543_l1}, +/*h(16193)=7544 */ {16193, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7544_l1}, +/*h(2663)=7545 */ {2663, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7545_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11025)=7547 */ {11025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7547_l1}, +/*h(15206)=7548 */ {15206, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7548_l1}, +/*h(8441)=7549 */ {8441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5857)=7551 */ {5857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7551_l1}, +/*h(3273)=7552 */ {3273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7552_l1}, +/*h(14219)=7553 */ {14219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7553_l1}, +/*h(689)=7554 */ {689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7554_l1}, +/*h(4870)=7555 */ {4870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7555_l1}, +/*h(9051)=7556 */ {9051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7556_l1}, +/*h(13232)=7557 */ {13232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7557_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3883)=7559 */ {3883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7559_l1}, +/*h(8064)=7560 */ {8064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7560_l1}, +/*h(12245)=7561 */ {12245, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7561_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13842)=7563 */ {13842, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7563_l1}, +/*h(7077)=7564 */ {7077, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7564_l1}, +/*h(11258)=7565 */ {11258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1909)=7567 */ {1909, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7567_l1}, +/*h(6090)=7568 */ {6090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7568_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14452)=7570 */ {14452, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7570_l1}, +/*h(922)=7571 */ {922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7571_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16049)=7573 */ {16049, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7573_l1}, +/*h(13465)=7574 */ {13465, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10881)=7576 */ {10881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7576_l1}, +/*h(15062)=7577 */ {15062, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7577_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5713)=7579 */ {5713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7579_l1}, +/*h(9894)=7580 */ {9894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7580_l1}, +/*h(14075)=7581 */ {14075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7581_l1}, +/*h(545)=7582 */ {545, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7582_l1}, +/*h(4726)=7583 */ {4726, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7583_l1}, +/*h(8907)=7584 */ {8907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7584_l1}, +/*h(13088)=7585 */ {13088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7585_l1}, +/*h(6323)=7586 */ {6323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7586_l1}, +/*h(3739)=7587 */ {3739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7587_l1}, +/*h(7920)=7588 */ {7920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7588_l1}, +/*h(1155)=7589 */ {1155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7589_l1}, +/*h(16282)=7590 */ {16282, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7590_l1}, +/*h(2752)=7591 */ {2752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7591_l1}, +/*h(6933)=7592 */ {6933, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7592_l1}, +/*h(11114)=7593 */ {11114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7593_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1765)=7596 */ {1765, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7596_l1}, +/*h(5946)=7597 */ {5946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7597_l1}, +/*h(14308)=7598 */ {14308, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(778)=7600 */ {778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7600_l1}, +/*h(15905)=7601 */ {15905, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7601_l1}, +/*h(9140)=7602 */ {9140, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7602_l1}, +/*h(13321)=7603 */ {13321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7603_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14918)=7605 */ {14918, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7605_l1}, +/*h(8153)=7606 */ {8153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7606_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9750)=7608 */ {9750, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7608_l1}, +/*h(13931)=7609 */ {13931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7609_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11347)=7611 */ {11347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7611_l1}, +/*h(15528)=7612 */ {15528, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7612_l1}, +/*h(8763)=7613 */ {8763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7613_l1}, +/*h(6179)=7614 */ {6179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7614_l1}, +/*h(10360)=7615 */ {10360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7615_l1}, +/*h(3595)=7616 */ {3595, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7616_l1}, +/*h(1011)=7617 */ {1011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7617_l1}, +/*h(11957)=7618 */ {11957, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7618_l1}, +/*h(16138)=7619 */ {16138, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7619_l1}, +/*h(13554)=7620 */ {13554, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7620_l1}, +/*h(6789)=7621 */ {6789, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7621_l1}, +/*h(10970)=7622 */ {10970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7622_l1}, +/*h(8386)=7623 */ {8386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7623_l1}, +/*h(1621)=7624 */ {1621, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7624_l1}, +/*h(5802)=7625 */ {5802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3218)=7627 */ {3218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7627_l1}, +/*h(634)=7628 */ {634, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7628_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8996)=7630 */ {8996, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7630_l1}, +/*h(2231)=7631 */ {2231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7631_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3828)=7633 */ {3828, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7633_l1}, +/*h(8009)=7634 */ {8009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7634_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16371)=7636 */ {16371, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7636_l1}, +/*h(2841)=7637 */ {2841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7637_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11203)=7639 */ {11203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7639_l1}, +/*h(15384)=7640 */ {15384, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12800)=7642 */ {12800, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7642_l1}, +/*h(6035)=7643 */ {6035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7643_l1}, +/*h(10216)=7644 */ {10216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7644_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(867)=7646 */ {867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7646_l1}, +/*h(15994)=7647 */ {15994, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7647_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13410)=7649 */ {13410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7649_l1}, +/*h(10826)=7650 */ {10826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7650_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8242)=7652 */ {8242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7652_l1}, +/*h(5658)=7653 */ {5658, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7653_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3074)=7655 */ {3074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7655_l1}, +/*h(7255)=7656 */ {7255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7656_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2087)=7659 */ {2087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7659_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10449)=7661 */ {10449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7661_l1}, +/*h(3684)=7662 */ {3684, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7662_l1}, +/*h(7865)=7663 */ {7865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7663_l1}, +/*h(5281)=7664 */ {5281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7664_l1}, +/*h(16227)=7665 */ {16227, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7665_l1}, +/*h(2697)=7666 */ {2697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7666_l1}, +/*h(113)=7667 */ {113, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7667_l1}, +/*h(11059)=7668 */ {11059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7668_l1}, +/*h(15240)=7669 */ {15240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5891)=7671 */ {5891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7671_l1}, +/*h(10072)=7672 */ {10072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7672_l1}, +/*h(3307)=7673 */ {3307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7673_l1}, +/*h(723)=7674 */ {723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7674_l1}, +/*h(4904)=7675 */ {4904, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7675_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13266)=7677 */ {13266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7677_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8098)=7680 */ {8098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7680_l1}, +/*h(12279)=7681 */ {12279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7681_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2930)=7683 */ {2930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7683_l1}, +/*h(7111)=7684 */ {7111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15473)=7686 */ {15473, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7686_l1}, +/*h(8708)=7687 */ {8708, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7687_l1}, +/*h(1943)=7688 */ {1943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7688_l1}, +/*h(10305)=7689 */ {10305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7689_l1}, +/*h(14486)=7690 */ {14486, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7690_l1}, +/*h(7721)=7691 */ {7721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7691_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16083)=7693 */ {16083, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7693_l1}, +/*h(9318)=7694 */ {9318, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7694_l1}, +/*h(13499)=7695 */ {13499, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7695_l1}, +/*h(10915)=7696 */ {10915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7696_l1}, +/*h(4150)=7697 */ {4150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7697_l1}, +/*h(8331)=7698 */ {8331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7698_l1}, +/*h(5747)=7699 */ {5747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7699_l1}, +/*h(9928)=7700 */ {9928, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7700_l1}, +/*h(3163)=7701 */ {3163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7701_l1}, +/*h(7344)=7702 */ {7344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7702_l1}, +/*h(579)=7703 */ {579, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7703_l1}, +/*h(4760)=7704 */ {4760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7704_l1}, +/*h(13122)=7705 */ {13122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7705_l1}, +/*h(6357)=7706 */ {6357, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7706_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7954)=7709 */ {7954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7709_l1}, +/*h(12135)=7710 */ {12135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7710_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2786)=7712 */ {2786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7712_l1}, +/*h(6967)=7713 */ {6967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7713_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15329)=7715 */ {15329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7715_l1}, +/*h(1799)=7716 */ {1799, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7716_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10161)=7718 */ {10161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7718_l1}, +/*h(14342)=7719 */ {14342, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7719_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15939)=7721 */ {15939, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7721_l1}, +/*h(9174)=7722 */ {9174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7722_l1}, +/*h(13355)=7723 */ {13355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7723_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4006)=7725 */ {4006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7725_l1}, +/*h(8187)=7726 */ {8187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7726_l1}, +/*h(12368)=7727 */ {12368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3019)=7729 */ {3019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7729_l1}, +/*h(7200)=7730 */ {7200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7730_l1}, +/*h(11381)=7731 */ {11381, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7731_l1}, +/*h(15562)=7732 */ {15562, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7732_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12978)=7734 */ {12978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7734_l1}, +/*h(10394)=7735 */ {10394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7810)=7737 */ {7810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7737_l1}, +/*h(11991)=7738 */ {11991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7738_l1}, +/*h(5226)=7739 */ {5226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7739_l1}, +/*h(2642)=7740 */ {2642, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7740_l1}, +/*h(6823)=7741 */ {6823, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7741_l1}, +/*h(58)=7742 */ {58, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7742_l1}, +/*h(15185)=7743 */ {15185, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7743_l1}, +/*h(1655)=7744 */ {1655, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7744_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10017)=7746 */ {10017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7746_l1}, +/*h(14198)=7747 */ {14198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9030)=7750 */ {9030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7750_l1}, +/*h(13211)=7751 */ {13211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7751_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3862)=7754 */ {3862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7754_l1}, +/*h(8043)=7755 */ {8043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7755_l1}, +/*h(12224)=7756 */ {12224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2875)=7758 */ {2875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7758_l1}, +/*h(7056)=7759 */ {7056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7759_l1}, +/*h(11237)=7760 */ {11237, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7760_l1}, +/*h(15418)=7761 */ {15418, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7761_l1}, +/*h(12834)=7762 */ {12834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7762_l1}, +/*h(6069)=7763 */ {6069, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7763_l1}, +/*h(10250)=7764 */ {10250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11847)=7766 */ {11847, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7766_l1}, +/*h(5082)=7767 */ {5082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7767_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13444)=7769 */ {13444, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7769_l1}, +/*h(6679)=7770 */ {6679, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7770_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15041)=7772 */ {15041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7772_l1}, +/*h(12457)=7773 */ {12457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9873)=7775 */ {9873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7775_l1}, +/*h(14054)=7776 */ {14054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7776_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4705)=7778 */ {4705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7778_l1}, +/*h(8886)=7779 */ {8886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7779_l1}, +/*h(13067)=7780 */ {13067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7780_l1}, +/*h(10483)=7781 */ {10483, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7781_l1}, +/*h(3718)=7782 */ {3718, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7782_l1}, +/*h(7899)=7783 */ {7899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7783_l1}, +/*h(12080)=7784 */ {12080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7784_l1}, +/*h(5315)=7785 */ {5315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7785_l1}, +/*h(2731)=7786 */ {2731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7786_l1}, +/*h(6912)=7787 */ {6912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7787_l1}, +/*h(147)=7788 */ {147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7788_l1}, +/*h(15274)=7789 */ {15274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7789_l1}, +/*h(1744)=7790 */ {1744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7790_l1}, +/*h(5925)=7791 */ {5925, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7791_l1}, +/*h(10106)=7792 */ {10106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7792_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(757)=7795 */ {757, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7795_l1}, +/*h(4938)=7796 */ {4938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7796_l1}, +/*h(13300)=7797 */ {13300, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7797_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14897)=7800 */ {14897, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7800_l1}, +/*h(8132)=7801 */ {8132, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7801_l1}, +/*h(12313)=7802 */ {12313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7802_l1}, +/*h(9729)=7803 */ {9729, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7803_l1}, +/*h(13910)=7804 */ {13910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7804_l1}, +/*h(7145)=7805 */ {7145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7805_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15507)=7807 */ {15507, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7807_l1}, +/*h(12923)=7808 */ {12923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7808_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10339)=7810 */ {10339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7810_l1}, +/*h(7755)=7811 */ {7755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7811_l1}, +/*h(11936)=7812 */ {11936, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7812_l1}, +/*h(5171)=7813 */ {5171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7813_l1}, +/*h(9352)=7814 */ {9352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7814_l1}, +/*h(2587)=7815 */ {2587, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7815_l1}, +/*h(3)=7816 */ {3, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7816_l1}, +/*h(10949)=7817 */ {10949, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7817_l1}, +/*h(15130)=7818 */ {15130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7818_l1}, +/*h(1600)=7819 */ {1600, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7819_l1}, +/*h(5781)=7820 */ {5781, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7820_l1}, +/*h(9962)=7821 */ {9962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7821_l1}, +/*h(7378)=7822 */ {7378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7822_l1}, +/*h(613)=7823 */ {613, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7823_l1}, +/*h(4794)=7824 */ {4794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7824_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6391)=7826 */ {6391, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7826_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7988)=7829 */ {7988, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7829_l1}, +/*h(1223)=7830 */ {1223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7830_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2820)=7832 */ {2820, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7832_l1}, +/*h(7001)=7833 */ {7001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7833_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15363)=7835 */ {15363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7835_l1}, +/*h(1833)=7836 */ {1833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7836_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10195)=7838 */ {10195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7838_l1}, +/*h(14376)=7839 */ {14376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5027)=7841 */ {5027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7841_l1}, +/*h(15973)=7842 */ {15973, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7842_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10805)=7845 */ {10805, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7845_l1}, +/*h(14986)=7846 */ {14986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7846_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12402)=7848 */ {12402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7848_l1}, +/*h(9818)=7849 */ {9818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7849_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7234)=7851 */ {7234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7851_l1}, +/*h(11415)=7852 */ {11415, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7852_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2066)=7854 */ {2066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7854_l1}, +/*h(6247)=7855 */ {6247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7855_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7844)=7857 */ {7844, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7857_l1}, +/*h(1079)=7858 */ {1079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7858_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9441)=7860 */ {9441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7860_l1}, +/*h(2676)=7861 */ {2676, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7861_l1}, +/*h(6857)=7862 */ {6857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7862_l1}, +/*h(4273)=7863 */ {4273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7863_l1}, +/*h(15219)=7864 */ {15219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7864_l1}, +/*h(1689)=7865 */ {1689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7865_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10051)=7867 */ {10051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7867_l1}, +/*h(14232)=7868 */ {14232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7868_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4883)=7870 */ {4883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7870_l1}, +/*h(9064)=7871 */ {9064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7871_l1}, +/*h(2299)=7872 */ {2299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7872_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3896)=7874 */ {3896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7874_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12258)=7876 */ {12258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7876_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7090)=7879 */ {7090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7879_l1}, +/*h(11271)=7880 */ {11271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1922)=7882 */ {1922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7882_l1}, +/*h(6103)=7883 */ {6103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7883_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14465)=7885 */ {14465, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7885_l1}, +/*h(7700)=7886 */ {7700, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7886_l1}, +/*h(935)=7887 */ {935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7887_l1}, +/*h(9297)=7888 */ {9297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7888_l1}, +/*h(13478)=7889 */ {13478, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7889_l1}, +/*h(6713)=7890 */ {6713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7890_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15075)=7892 */ {15075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7892_l1}, +/*h(8310)=7893 */ {8310, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7893_l1}, +/*h(12491)=7894 */ {12491, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7894_l1}, +/*h(9907)=7895 */ {9907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7895_l1}, +/*h(3142)=7896 */ {3142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7896_l1}, +/*h(7323)=7897 */ {7323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7897_l1}, +/*h(4739)=7898 */ {4739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7898_l1}, +/*h(8920)=7899 */ {8920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7899_l1}, +/*h(2155)=7900 */ {2155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7900_l1}, +/*h(6336)=7901 */ {6336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7901_l1}, +/*h(3752)=7902 */ {3752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7902_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12114)=7904 */ {12114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7904_l1}, +/*h(16295)=7905 */ {16295, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7905_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6946)=7908 */ {6946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7908_l1}, +/*h(11127)=7909 */ {11127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7909_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1778)=7911 */ {1778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7911_l1}, +/*h(5959)=7912 */ {5959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7912_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14321)=7914 */ {14321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7914_l1}, +/*h(791)=7915 */ {791, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9153)=7917 */ {9153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7917_l1}, +/*h(13334)=7918 */ {13334, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7918_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14931)=7920 */ {14931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7920_l1}, +/*h(8166)=7921 */ {8166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7921_l1}, +/*h(12347)=7922 */ {12347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7922_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2998)=7924 */ {2998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7924_l1}, +/*h(7179)=7925 */ {7179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7925_l1}, +/*h(11360)=7926 */ {11360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7926_l1}, +/*h(15541)=7927 */ {15541, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7927_l1}, +/*h(2011)=7928 */ {2011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7928_l1}, +/*h(6192)=7929 */ {6192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7929_l1}, +/*h(10373)=7930 */ {10373, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7930_l1}, +/*h(14554)=7931 */ {14554, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7931_l1}, +/*h(1024)=7932 */ {1024, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7932_l1}, +/*h(11970)=7933 */ {11970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7933_l1}, +/*h(16151)=7934 */ {16151, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7934_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6802)=7936 */ {6802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7936_l1}, +/*h(10983)=7937 */ {10983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7937_l1}, +/*h(4218)=7938 */ {4218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7938_l1}, +/*h(1634)=7939 */ {1634, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7939_l1}, +/*h(5815)=7940 */ {5815, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7940_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14177)=7942 */ {14177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7942_l1}, +/*h(647)=7943 */ {647, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7943_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9009)=7945 */ {9009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7945_l1}, +/*h(13190)=7946 */ {13190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7946_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3841)=7948 */ {3841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7948_l1}, +/*h(8022)=7949 */ {8022, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7949_l1}, +/*h(12203)=7950 */ {12203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7950_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2854)=7953 */ {2854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7953_l1}, +/*h(7035)=7954 */ {7035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7954_l1}, +/*h(11216)=7955 */ {11216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7955_l1}, +/*h(15397)=7956 */ {15397, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7956_l1}, +/*h(1867)=7957 */ {1867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7957_l1}, +/*h(6048)=7958 */ {6048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7958_l1}, +/*h(10229)=7959 */ {10229, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7959_l1}, +/*h(14410)=7960 */ {14410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7960_l1}, +/*h(11826)=7961 */ {11826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7961_l1}, +/*h(16007)=7962 */ {16007, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7962_l1}, +/*h(9242)=7963 */ {9242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7963_l1}, +/*h(6658)=7964 */ {6658, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7964_l1}, +/*h(10839)=7965 */ {10839, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7965_l1}, +/*h(4074)=7966 */ {4074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12436)=7968 */ {12436, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7968_l1}, +/*h(5671)=7969 */ {5671, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7969_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14033)=7971 */ {14033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7971_l1}, +/*h(11449)=7972 */ {11449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7972_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8865)=7974 */ {8865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7974_l1}, +/*h(13046)=7975 */ {13046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7975_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3697)=7977 */ {3697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7977_l1}, +/*h(7878)=7978 */ {7878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7978_l1}, +/*h(12059)=7979 */ {12059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7979_l1}, +/*h(16240)=7980 */ {16240, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7980_l1}, +/*h(2710)=7981 */ {2710, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7981_l1}, +/*h(6891)=7982 */ {6891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7982_l1}, +/*h(11072)=7983 */ {11072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7983_l1}, +/*h(4307)=7984 */ {4307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7984_l1}, +/*h(1723)=7985 */ {1723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7985_l1}, +/*h(5904)=7986 */ {5904, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7986_l1}, +/*h(10085)=7987 */ {10085, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7987_l1}, +/*h(14266)=7988 */ {14266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7988_l1}, +/*h(736)=7989 */ {736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7989_l1}, +/*h(4917)=7990 */ {4917, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7990_l1}, +/*h(9098)=7991 */ {9098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7991_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3930)=7994 */ {3930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7994_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12292)=7996 */ {12292, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7996_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13889)=7999 */ {13889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_7999_l1}, +/*h(7124)=8000 */ {7124, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8000_l1}, +/*h(11305)=8001 */ {11305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8001_l1}, +/*h(8721)=8002 */ {8721, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8002_l1}, +/*h(12902)=8003 */ {12902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8003_l1}, +/*h(6137)=8004 */ {6137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8004_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7734)=8006 */ {7734, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8006_l1}, +/*h(11915)=8007 */ {11915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8007_l1}, +/*h(16096)=8008 */ {16096, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8008_l1}, +/*h(9331)=8009 */ {9331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8009_l1}, +/*h(6747)=8010 */ {6747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8010_l1}, +/*h(10928)=8011 */ {10928, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8011_l1}, +/*h(4163)=8012 */ {4163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8012_l1}, +/*h(8344)=8013 */ {8344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8013_l1}, +/*h(1579)=8014 */ {1579, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8014_l1}, +/*h(5760)=8015 */ {5760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8015_l1}, +/*h(9941)=8016 */ {9941, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8016_l1}, +/*h(14122)=8017 */ {14122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8017_l1}, +/*h(592)=8018 */ {592, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8018_l1}, +/*h(4773)=8019 */ {4773, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8019_l1}, +/*h(8954)=8020 */ {8954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8020_l1}, +/*h(6370)=8021 */ {6370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8021_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3786)=8023 */ {3786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8023_l1}, +/*h(1202)=8024 */ {1202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8024_l1}, +/*h(12148)=8025 */ {12148, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8025_l1}, +/*h(16329)=8026 */ {16329, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8026_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6980)=8028 */ {6980, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8028_l1}, +/*h(215)=8029 */ {215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8029_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1812)=8031 */ {1812, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8031_l1}, +/*h(5993)=8032 */ {5993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8032_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14355)=8034 */ {14355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8034_l1}, +/*h(825)=8035 */ {825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8035_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9187)=8037 */ {9187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8037_l1}, +/*h(13368)=8038 */ {13368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8038_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4019)=8040 */ {4019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8040_l1}, +/*h(14965)=8041 */ {14965, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8041_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9797)=8044 */ {9797, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8044_l1}, +/*h(13978)=8045 */ {13978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8045_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11394)=8047 */ {11394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8047_l1}, +/*h(15575)=8048 */ {15575, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8048_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6226)=8050 */ {6226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8050_l1}, +/*h(3642)=8051 */ {3642, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8051_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1058)=8053 */ {1058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8053_l1}, +/*h(5239)=8054 */ {5239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8054_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6836)=8056 */ {6836, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8056_l1}, +/*h(71)=8057 */ {71, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8057_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8433)=8059 */ {8433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8059_l1}, +/*h(1668)=8060 */ {1668, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8060_l1}, +/*h(5849)=8061 */ {5849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8061_l1}, +/*h(3265)=8062 */ {3265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8062_l1}, +/*h(14211)=8063 */ {14211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8063_l1}, +/*h(681)=8064 */ {681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8064_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9043)=8066 */ {9043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8066_l1}, +/*h(13224)=8067 */ {13224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8067_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8056)=8070 */ {8056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8070_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13834)=8073 */ {13834, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8073_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11250)=8075 */ {11250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8075_l1}, +/*h(15431)=8076 */ {15431, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8076_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6082)=8078 */ {6082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8078_l1}, +/*h(10263)=8079 */ {10263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8079_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(914)=8081 */ {914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8081_l1}, +/*h(5095)=8082 */ {5095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8082_l1}, +/*h(16041)=8083 */ {16041, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8083_l1}, +/*h(13457)=8084 */ {13457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8084_l1}, +/*h(6692)=8085 */ {6692, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8085_l1}, +/*h(10873)=8086 */ {10873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8086_l1}, +/*h(8289)=8087 */ {8289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8087_l1}, +/*h(12470)=8088 */ {12470, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8088_l1}, +/*h(5705)=8089 */ {5705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8089_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14067)=8091 */ {14067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8091_l1}, +/*h(7302)=8092 */ {7302, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8092_l1}, +/*h(11483)=8093 */ {11483, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8093_l1}, +/*h(8899)=8094 */ {8899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8094_l1}, +/*h(2134)=8095 */ {2134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8095_l1}, +/*h(6315)=8096 */ {6315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8096_l1}, +/*h(3731)=8097 */ {3731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8097_l1}, +/*h(7912)=8098 */ {7912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8098_l1}, +/*h(1147)=8099 */ {1147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8099_l1}, +/*h(16274)=8100 */ {16274, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8100_l1}, +/*h(2744)=8101 */ {2744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8101_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11106)=8103 */ {11106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8103_l1}, +/*h(15287)=8104 */ {15287, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8104_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10119)=8108 */ {10119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(770)=8110 */ {770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8110_l1}, +/*h(4951)=8111 */ {4951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13313)=8113 */ {13313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8145)=8116 */ {8145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8116_l1}, +/*h(12326)=8117 */ {12326, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13923)=8119 */ {13923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8119_l1}, +/*h(7158)=8120 */ {7158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8120_l1}, +/*h(11339)=8121 */ {11339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8121_l1}, +/*h(15520)=8122 */ {15520, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8122_l1}, +/*h(1990)=8123 */ {1990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8123_l1}, +/*h(6171)=8124 */ {6171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8124_l1}, +/*h(10352)=8125 */ {10352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8125_l1}, +/*h(3587)=8126 */ {3587, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8126_l1}, +/*h(1003)=8127 */ {1003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8127_l1}, +/*h(5184)=8128 */ {5184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8128_l1}, +/*h(16130)=8129 */ {16130, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8129_l1}, +/*h(13546)=8130 */ {13546, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8130_l1}, +/*h(16)=8131 */ {16, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8131_l1}, +/*h(10962)=8132 */ {10962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8132_l1}, +/*h(15143)=8133 */ {15143, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5794)=8135 */ {5794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8135_l1}, +/*h(9975)=8136 */ {9975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8136_l1}, +/*h(3210)=8137 */ {3210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8137_l1}, +/*h(626)=8138 */ {626, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8138_l1}, +/*h(4807)=8139 */ {4807, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13169)=8141 */ {13169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8001)=8144 */ {8001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8144_l1}, +/*h(12182)=8145 */ {12182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8145_l1}, +/*h(16363)=8146 */ {16363, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8146_l1}, +/*h(2833)=8147 */ {2833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8147_l1}, +/*h(7014)=8148 */ {7014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8148_l1}, +/*h(11195)=8149 */ {11195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8149_l1}, +/*h(15376)=8150 */ {15376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6027)=8153 */ {6027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8153_l1}, +/*h(10208)=8154 */ {10208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8154_l1}, +/*h(14389)=8155 */ {14389, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8155_l1}, +/*h(859)=8156 */ {859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8156_l1}, +/*h(15986)=8157 */ {15986, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8157_l1}, +/*h(9221)=8158 */ {9221, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8158_l1}, +/*h(13402)=8159 */ {13402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8159_l1}, +/*h(10818)=8160 */ {10818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8160_l1}, +/*h(14999)=8161 */ {14999, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8161_l1}, +/*h(8234)=8162 */ {8234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8162_l1}, +/*h(5650)=8163 */ {5650, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8163_l1}, +/*h(9831)=8164 */ {9831, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8164_l1}, +/*h(3066)=8165 */ {3066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8165_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11428)=8167 */ {11428, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8167_l1}, +/*h(4663)=8168 */ {4663, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13025)=8170 */ {13025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8170_l1}, +/*h(10441)=8171 */ {10441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8171_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7857)=8173 */ {7857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8173_l1}, +/*h(12038)=8174 */ {12038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8174_l1}, +/*h(16219)=8175 */ {16219, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8175_l1}, +/*h(2689)=8176 */ {2689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8176_l1}, +/*h(6870)=8177 */ {6870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8177_l1}, +/*h(11051)=8178 */ {11051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8178_l1}, +/*h(15232)=8179 */ {15232, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8179_l1}, +/*h(1702)=8180 */ {1702, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8180_l1}, +/*h(5883)=8181 */ {5883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8181_l1}, +/*h(10064)=8182 */ {10064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8182_l1}, +/*h(3299)=8183 */ {3299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8183_l1}, +/*h(715)=8184 */ {715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8184_l1}, +/*h(4896)=8185 */ {4896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8185_l1}, +/*h(9077)=8186 */ {9077, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8186_l1}, +/*h(13258)=8187 */ {13258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8187_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3909)=8189 */ {3909, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8189_l1}, +/*h(8090)=8190 */ {8090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2922)=8193 */ {2922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11284)=8195 */ {11284, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8195_l1}, +/*h(15465)=8196 */ {15465, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12881)=8198 */ {12881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8198_l1}, +/*h(6116)=8199 */ {6116, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8199_l1}, +/*h(10297)=8200 */ {10297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8200_l1}, +/*h(7713)=8201 */ {7713, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8201_l1}, +/*h(11894)=8202 */ {11894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8202_l1}, +/*h(16075)=8203 */ {16075, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13491)=8205 */ {13491, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8205_l1}, +/*h(10907)=8206 */ {10907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8206_l1}, +/*h(15088)=8207 */ {15088, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8207_l1}, +/*h(1558)=8208 */ {1558, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8208_l1}, +/*h(5739)=8209 */ {5739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8209_l1}, +/*h(9920)=8210 */ {9920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8210_l1}, +/*h(3155)=8211 */ {3155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8211_l1}, +/*h(7336)=8212 */ {7336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8212_l1}, +/*h(571)=8213 */ {571, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8213_l1}, +/*h(4752)=8214 */ {4752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8214_l1}, +/*h(13114)=8215 */ {13114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3765)=8218 */ {3765, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8218_l1}, +/*h(7946)=8219 */ {7946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8219_l1}, +/*h(5362)=8220 */ {5362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8220_l1}, +/*h(16308)=8221 */ {16308, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8221_l1}, +/*h(2778)=8222 */ {2778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8222_l1}, +/*h(194)=8223 */ {194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8223_l1}, +/*h(11140)=8224 */ {11140, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8224_l1}, +/*h(15321)=8225 */ {15321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5972)=8227 */ {5972, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8227_l1}, +/*h(10153)=8228 */ {10153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8228_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(804)=8230 */ {804, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8230_l1}, +/*h(15931)=8231 */ {15931, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8231_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13347)=8233 */ {13347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10763)=8235 */ {10763, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8235_l1}, +/*h(8179)=8236 */ {8179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8236_l1}, +/*h(12360)=8237 */ {12360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3011)=8239 */ {3011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8239_l1}, +/*h(13957)=8240 */ {13957, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15554)=8242 */ {15554, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8242_l1}, +/*h(8789)=8243 */ {8789, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8243_l1}, +/*h(12970)=8244 */ {12970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10386)=8246 */ {10386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8246_l1}, +/*h(7802)=8247 */ {7802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5218)=8249 */ {5218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8249_l1}, +/*h(9399)=8250 */ {9399, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(50)=8252 */ {50, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8252_l1}, +/*h(4231)=8253 */ {4231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5828)=8255 */ {5828, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8255_l1}, +/*h(10009)=8256 */ {10009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8256_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(660)=8259 */ {660, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8259_l1}, +/*h(4841)=8260 */ {4841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8260_l1}, +/*h(13203)=8261 */ {13203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8035)=8265 */ {8035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8265_l1}, +/*h(12216)=8266 */ {12216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8266_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2867)=8268 */ {2867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8268_l1}, +/*h(7048)=8269 */ {7048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15410)=8271 */ {15410, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8271_l1}, +/*h(12826)=8272 */ {12826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8272_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10242)=8274 */ {10242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8274_l1}, +/*h(14423)=8275 */ {14423, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8275_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5074)=8277 */ {5074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8277_l1}, +/*h(9255)=8278 */ {9255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8278_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4087)=8281 */ {4087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8281_l1}, +/*h(15033)=8282 */ {15033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8282_l1}, +/*h(12449)=8283 */ {12449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8283_l1}, +/*h(5684)=8284 */ {5684, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8284_l1}, +/*h(9865)=8285 */ {9865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8285_l1}, +/*h(7281)=8286 */ {7281, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8286_l1}, +/*h(11462)=8287 */ {11462, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8287_l1}, +/*h(4697)=8288 */ {4697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13059)=8290 */ {13059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8290_l1}, +/*h(6294)=8291 */ {6294, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8291_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7891)=8293 */ {7891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8293_l1}, +/*h(1126)=8294 */ {1126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8294_l1}, +/*h(5307)=8295 */ {5307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8295_l1}, +/*h(2723)=8296 */ {2723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8296_l1}, +/*h(6904)=8297 */ {6904, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8297_l1}, +/*h(139)=8298 */ {139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8298_l1}, +/*h(15266)=8299 */ {15266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8299_l1}, +/*h(1736)=8300 */ {1736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10098)=8302 */ {10098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8302_l1}, +/*h(14279)=8303 */ {14279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9111)=8306 */ {9111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8306_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3943)=8310 */ {3943, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12305)=8312 */ {12305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7137)=8315 */ {7137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8315_l1}, +/*h(11318)=8316 */ {11318, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8316_l1}, +/*h(15499)=8317 */ {15499, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8317_l1}, +/*h(12915)=8318 */ {12915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8318_l1}, +/*h(6150)=8319 */ {6150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8319_l1}, +/*h(10331)=8320 */ {10331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8320_l1}, +/*h(14512)=8321 */ {14512, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8321_l1}, +/*h(982)=8322 */ {982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8322_l1}, +/*h(5163)=8323 */ {5163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8323_l1}, +/*h(9344)=8324 */ {9344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8324_l1}, +/*h(2579)=8325 */ {2579, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8325_l1}, +/*h(6760)=8326 */ {6760, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8326_l1}, +/*h(4176)=8327 */ {4176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8327_l1}, +/*h(15122)=8328 */ {15122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8328_l1}, +/*h(12538)=8329 */ {12538, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9954)=8331 */ {9954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8331_l1}, +/*h(7370)=8332 */ {7370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4786)=8334 */ {4786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8334_l1}, +/*h(8967)=8335 */ {8967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8335_l1}, +/*h(2202)=8336 */ {2202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8336_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3799)=8338 */ {3799, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12161)=8340 */ {12161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8340_l1}, +/*h(16342)=8341 */ {16342, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8341_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6993)=8343 */ {6993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8343_l1}, +/*h(11174)=8344 */ {11174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8344_l1}, +/*h(15355)=8345 */ {15355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8345_l1}, +/*h(1825)=8346 */ {1825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8346_l1}, +/*h(6006)=8347 */ {6006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8347_l1}, +/*h(10187)=8348 */ {10187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8348_l1}, +/*h(14368)=8349 */ {14368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(838)=8351 */ {838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8351_l1}, +/*h(5019)=8352 */ {5019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8352_l1}, +/*h(13381)=8353 */ {13381, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8353_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14978)=8356 */ {14978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8356_l1}, +/*h(8213)=8357 */ {8213, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8357_l1}, +/*h(12394)=8358 */ {12394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8358_l1}, +/*h(9810)=8359 */ {9810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8359_l1}, +/*h(13991)=8360 */ {13991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8360_l1}, +/*h(7226)=8361 */ {7226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8361_l1}, +/*h(4642)=8362 */ {4642, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8362_l1}, +/*h(8823)=8363 */ {8823, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8363_l1}, +/*h(2058)=8364 */ {2058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10420)=8366 */ {10420, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8366_l1}, +/*h(3655)=8367 */ {3655, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8367_l1}, +/*h(12017)=8368 */ {12017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8368_l1}, +/*h(16198)=8369 */ {16198, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8369_l1}, +/*h(9433)=8370 */ {9433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6849)=8372 */ {6849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8372_l1}, +/*h(11030)=8373 */ {11030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8373_l1}, +/*h(15211)=8374 */ {15211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8374_l1}, +/*h(1681)=8375 */ {1681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8375_l1}, +/*h(5862)=8376 */ {5862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8376_l1}, +/*h(10043)=8377 */ {10043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8377_l1}, +/*h(14224)=8378 */ {14224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8378_l1}, +/*h(694)=8379 */ {694, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8379_l1}, +/*h(4875)=8380 */ {4875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8380_l1}, +/*h(9056)=8381 */ {9056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8381_l1}, +/*h(2291)=8382 */ {2291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8382_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3888)=8384 */ {3888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8384_l1}, +/*h(8069)=8385 */ {8069, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8385_l1}, +/*h(12250)=8386 */ {12250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8386_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2901)=8388 */ {2901, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8388_l1}, +/*h(7082)=8389 */ {7082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8389_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15444)=8391 */ {15444, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8391_l1}, +/*h(1914)=8392 */ {1914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8392_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10276)=8394 */ {10276, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8394_l1}, +/*h(14457)=8395 */ {14457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11873)=8397 */ {11873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8397_l1}, +/*h(16054)=8398 */ {16054, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6705)=8400 */ {6705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8400_l1}, +/*h(10886)=8401 */ {10886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8401_l1}, +/*h(15067)=8402 */ {15067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8402_l1}, +/*h(1537)=8403 */ {1537, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8403_l1}, +/*h(5718)=8404 */ {5718, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8404_l1}, +/*h(9899)=8405 */ {9899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8405_l1}, +/*h(14080)=8406 */ {14080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8406_l1}, +/*h(7315)=8407 */ {7315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8407_l1}, +/*h(4731)=8408 */ {4731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8408_l1}, +/*h(8912)=8409 */ {8912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8409_l1}, +/*h(2147)=8410 */ {2147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8410_l1}, +/*h(6328)=8411 */ {6328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8411_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7925)=8413 */ {7925, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8413_l1}, +/*h(12106)=8414 */ {12106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8414_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2757)=8417 */ {2757, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8417_l1}, +/*h(6938)=8418 */ {6938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8418_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15300)=8420 */ {15300, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8420_l1}, +/*h(1770)=8421 */ {1770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8421_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10132)=8423 */ {10132, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8423_l1}, +/*h(14313)=8424 */ {14313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8424_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15910)=8426 */ {15910, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8426_l1}, +/*h(9145)=8427 */ {9145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8427_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14923)=8430 */ {14923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12339)=8432 */ {12339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8432_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9755)=8434 */ {9755, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8434_l1}, +/*h(7171)=8435 */ {7171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8435_l1}, +/*h(11352)=8436 */ {11352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8436_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2003)=8438 */ {2003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8438_l1}, +/*h(12949)=8439 */ {12949, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14546)=8441 */ {14546, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8441_l1}, +/*h(7781)=8442 */ {7781, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8442_l1}, +/*h(11962)=8443 */ {11962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8443_l1}, +/*h(9378)=8444 */ {9378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8444_l1}, +/*h(13559)=8445 */ {13559, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8445_l1}, +/*h(6794)=8446 */ {6794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8446_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4210)=8448 */ {4210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8448_l1}, +/*h(1626)=8449 */ {1626, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8449_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9988)=8451 */ {9988, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8451_l1}, +/*h(3223)=8452 */ {3223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8452_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4820)=8454 */ {4820, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8454_l1}, +/*h(9001)=8455 */ {9001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8455_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3833)=8458 */ {3833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8458_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12195)=8460 */ {12195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8460_l1}, +/*h(16376)=8461 */ {16376, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8461_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7027)=8464 */ {7027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8464_l1}, +/*h(11208)=8465 */ {11208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1859)=8467 */ {1859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8467_l1}, +/*h(6040)=8468 */ {6040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8468_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14402)=8470 */ {14402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8470_l1}, +/*h(11818)=8471 */ {11818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9234)=8473 */ {9234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8473_l1}, +/*h(13415)=8474 */ {13415, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4066)=8476 */ {4066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8476_l1}, +/*h(8247)=8477 */ {8247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3079)=8480 */ {3079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8480_l1}, +/*h(14025)=8481 */ {14025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8481_l1}, +/*h(11441)=8482 */ {11441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8482_l1}, +/*h(4676)=8483 */ {4676, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8483_l1}, +/*h(8857)=8484 */ {8857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8484_l1}, +/*h(6273)=8485 */ {6273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8485_l1}, +/*h(10454)=8486 */ {10454, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8486_l1}, +/*h(3689)=8487 */ {3689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8487_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12051)=8489 */ {12051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8489_l1}, +/*h(9467)=8490 */ {9467, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6883)=8492 */ {6883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8492_l1}, +/*h(118)=8493 */ {118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8493_l1}, +/*h(4299)=8494 */ {4299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8494_l1}, +/*h(1715)=8495 */ {1715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8495_l1}, +/*h(5896)=8496 */ {5896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8496_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14258)=8498 */ {14258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8498_l1}, +/*h(728)=8499 */ {728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8499_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9090)=8501 */ {9090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8501_l1}, +/*h(13271)=8502 */ {13271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3922)=8504 */ {3922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8504_l1}, +/*h(8103)=8505 */ {8103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2935)=8509 */ {2935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8509_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11297)=8511 */ {11297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8511_l1}, +/*h(15478)=8512 */ {15478, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8512_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6129)=8514 */ {6129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8514_l1}, +/*h(10310)=8515 */ {10310, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8515_l1}, +/*h(14491)=8516 */ {14491, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8516_l1}, +/*h(11907)=8517 */ {11907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8517_l1}, +/*h(5142)=8518 */ {5142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8518_l1}, +/*h(9323)=8519 */ {9323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8519_l1}, +/*h(6739)=8520 */ {6739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8520_l1}, +/*h(10920)=8521 */ {10920, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8521_l1}, +/*h(4155)=8522 */ {4155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8522_l1}, +/*h(8336)=8523 */ {8336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8523_l1}, +/*h(1571)=8524 */ {1571, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8524_l1}, +/*h(5752)=8525 */ {5752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8525_l1}, +/*h(3168)=8526 */ {3168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8526_l1}, +/*h(7349)=8527 */ {7349, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8527_l1}, +/*h(584)=8528 */ {584, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8528_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8946)=8530 */ {8946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8530_l1}, +/*h(13127)=8531 */ {13127, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8531_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3778)=8533 */ {3778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8533_l1}, +/*h(7959)=8534 */ {7959, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8534_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16321)=8536 */ {16321, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8536_l1}, +/*h(2791)=8537 */ {2791, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8537_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11153)=8539 */ {11153, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8539_l1}, +/*h(15334)=8540 */ {15334, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5985)=8542 */ {5985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8542_l1}, +/*h(10166)=8543 */ {10166, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8543_l1}, +/*h(14347)=8544 */ {14347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8544_l1}, +/*h(817)=8545 */ {817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8545_l1}, +/*h(4998)=8546 */ {4998, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8546_l1}, +/*h(9179)=8547 */ {9179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8547_l1}, +/*h(13360)=8548 */ {13360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4011)=8550 */ {4011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8550_l1}, +/*h(8192)=8551 */ {8192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8551_l1}, +/*h(12373)=8552 */ {12373, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8552_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13970)=8555 */ {13970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8555_l1}, +/*h(7205)=8556 */ {7205, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8556_l1}, +/*h(11386)=8557 */ {11386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8557_l1}, +/*h(8802)=8558 */ {8802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8558_l1}, +/*h(12983)=8559 */ {12983, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8559_l1}, +/*h(6218)=8560 */ {6218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8560_l1}, +/*h(3634)=8561 */ {3634, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8561_l1}, +/*h(7815)=8562 */ {7815, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8562_l1}, +/*h(1050)=8563 */ {1050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8563_l1}, +/*h(16177)=8564 */ {16177, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8564_l1}, +/*h(2647)=8565 */ {2647, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11009)=8567 */ {11009, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8567_l1}, +/*h(15190)=8568 */ {15190, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8568_l1}, +/*h(8425)=8569 */ {8425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5841)=8571 */ {5841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8571_l1}, +/*h(3257)=8572 */ {3257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8572_l1}, +/*h(14203)=8573 */ {14203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8573_l1}, +/*h(673)=8574 */ {673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8574_l1}, +/*h(4854)=8575 */ {4854, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8575_l1}, +/*h(9035)=8576 */ {9035, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8576_l1}, +/*h(13216)=8577 */ {13216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8577_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3867)=8579 */ {3867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8579_l1}, +/*h(8048)=8580 */ {8048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8580_l1}, +/*h(12229)=8581 */ {12229, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13826)=8583 */ {13826, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8583_l1}, +/*h(7061)=8584 */ {7061, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8584_l1}, +/*h(11242)=8585 */ {11242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8585_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1893)=8587 */ {1893, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8587_l1}, +/*h(6074)=8588 */ {6074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8588_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14436)=8590 */ {14436, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8590_l1}, +/*h(906)=8591 */ {906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8591_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16033)=8593 */ {16033, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8593_l1}, +/*h(13449)=8594 */ {13449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10865)=8596 */ {10865, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8596_l1}, +/*h(15046)=8597 */ {15046, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5697)=8599 */ {5697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8599_l1}, +/*h(9878)=8600 */ {9878, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8600_l1}, +/*h(14059)=8601 */ {14059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8601_l1}, +/*h(529)=8602 */ {529, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8602_l1}, +/*h(11475)=8603 */ {11475, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8603_l1}, +/*h(8891)=8604 */ {8891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8604_l1}, +/*h(13072)=8605 */ {13072, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8605_l1}, +/*h(6307)=8606 */ {6307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8606_l1}, +/*h(3723)=8607 */ {3723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8607_l1}, +/*h(7904)=8608 */ {7904, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8608_l1}, +/*h(1139)=8609 */ {1139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8609_l1}, +/*h(16266)=8610 */ {16266, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8610_l1}, +/*h(2736)=8611 */ {2736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8611_l1}, +/*h(6917)=8612 */ {6917, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8612_l1}, +/*h(11098)=8613 */ {11098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8613_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1749)=8616 */ {1749, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8616_l1}, +/*h(5930)=8617 */ {5930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8617_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14292)=8619 */ {14292, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8619_l1}, +/*h(762)=8620 */ {762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8620_l1}, +/*h(15889)=8621 */ {15889, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8621_l1}, +/*h(9124)=8622 */ {9124, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8622_l1}, +/*h(13305)=8623 */ {13305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8623_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14902)=8625 */ {14902, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8625_l1}, +/*h(8137)=8626 */ {8137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8626_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9734)=8628 */ {9734, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8628_l1}, +/*h(13915)=8629 */ {13915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8629_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11331)=8631 */ {11331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8631_l1}, +/*h(15512)=8632 */ {15512, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8632_l1}, +/*h(8747)=8633 */ {8747, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8633_l1}, +/*h(6163)=8634 */ {6163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8634_l1}, +/*h(10344)=8635 */ {10344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8635_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(995)=8637 */ {995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8637_l1}, +/*h(11941)=8638 */ {11941, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8638_l1}, +/*h(16122)=8639 */ {16122, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8639_l1}, +/*h(13538)=8640 */ {13538, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8640_l1}, +/*h(6773)=8641 */ {6773, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8641_l1}, +/*h(10954)=8642 */ {10954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8642_l1}, +/*h(8370)=8643 */ {8370, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8643_l1}, +/*h(1605)=8644 */ {1605, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8644_l1}, +/*h(5786)=8645 */ {5786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8645_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3202)=8647 */ {3202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8647_l1}, +/*h(7383)=8648 */ {7383, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8648_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8980)=8650 */ {8980, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8650_l1}, +/*h(2215)=8651 */ {2215, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8651_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3812)=8653 */ {3812, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8653_l1}, +/*h(7993)=8654 */ {7993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8654_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16355)=8656 */ {16355, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8656_l1}, +/*h(2825)=8657 */ {2825, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11187)=8659 */ {11187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8659_l1}, +/*h(15368)=8660 */ {15368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8660_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6019)=8663 */ {6019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8663_l1}, +/*h(10200)=8664 */ {10200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8664_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(851)=8666 */ {851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8666_l1}, +/*h(15978)=8667 */ {15978, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8667_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13394)=8669 */ {13394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8669_l1}, +/*h(10810)=8670 */ {10810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8670_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8226)=8672 */ {8226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8672_l1}, +/*h(12407)=8673 */ {12407, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8673_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3058)=8675 */ {3058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8675_l1}, +/*h(7239)=8676 */ {7239, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8676_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15601)=8678 */ {15601, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8678_l1}, +/*h(2071)=8679 */ {2071, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8679_l1}, +/*h(13017)=8680 */ {13017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8680_l1}, +/*h(10433)=8681 */ {10433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8681_l1}, +/*h(3668)=8682 */ {3668, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8682_l1}, +/*h(7849)=8683 */ {7849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8683_l1}, +/*h(5265)=8684 */ {5265, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8684_l1}, +/*h(16211)=8685 */ {16211, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8685_l1}, +/*h(2681)=8686 */ {2681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8686_l1}, +/*h(97)=8687 */ {97, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8687_l1}, +/*h(11043)=8688 */ {11043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8688_l1}, +/*h(15224)=8689 */ {15224, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8689_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5875)=8691 */ {5875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8691_l1}, +/*h(10056)=8692 */ {10056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8692_l1}, +/*h(3291)=8693 */ {3291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8693_l1}, +/*h(707)=8694 */ {707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8694_l1}, +/*h(4888)=8695 */ {4888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8695_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13250)=8697 */ {13250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8697_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8082)=8700 */ {8082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8700_l1}, +/*h(12263)=8701 */ {12263, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8701_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2914)=8703 */ {2914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8703_l1}, +/*h(7095)=8704 */ {7095, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8704_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15457)=8706 */ {15457, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8706_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1927)=8708 */ {1927, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8708_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10289)=8710 */ {10289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8710_l1}, +/*h(14470)=8711 */ {14470, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8711_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16067)=8713 */ {16067, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8713_l1}, +/*h(9302)=8714 */ {9302, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8714_l1}, +/*h(13483)=8715 */ {13483, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8715_l1}, +/*h(10899)=8716 */ {10899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8716_l1}, +/*h(4134)=8717 */ {4134, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8717_l1}, +/*h(8315)=8718 */ {8315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8718_l1}, +/*h(5731)=8719 */ {5731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8719_l1}, +/*h(9912)=8720 */ {9912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8720_l1}, +/*h(3147)=8721 */ {3147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8721_l1}, +/*h(7328)=8722 */ {7328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8722_l1}, +/*h(563)=8723 */ {563, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8723_l1}, +/*h(4744)=8724 */ {4744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8724_l1}, +/*h(2160)=8725 */ {2160, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8725_l1}, +/*h(13106)=8726 */ {13106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8726_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7938)=8729 */ {7938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8729_l1}, +/*h(12119)=8730 */ {12119, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8730_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2770)=8732 */ {2770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8732_l1}, +/*h(6951)=8733 */ {6951, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8733_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15313)=8735 */ {15313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8735_l1}, +/*h(1783)=8736 */ {1783, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8736_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10145)=8738 */ {10145, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8738_l1}, +/*h(14326)=8739 */ {14326, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8739_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15923)=8741 */ {15923, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8741_l1}, +/*h(9158)=8742 */ {9158, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8742_l1}, +/*h(13339)=8743 */ {13339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8743_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3990)=8745 */ {3990, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8745_l1}, +/*h(8171)=8746 */ {8171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8746_l1}, +/*h(12352)=8747 */ {12352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3003)=8749 */ {3003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8749_l1}, +/*h(7184)=8750 */ {7184, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8750_l1}, +/*h(11365)=8751 */ {11365, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8751_l1}, +/*h(15546)=8752 */ {15546, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8752_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12962)=8754 */ {12962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8754_l1}, +/*h(6197)=8755 */ {6197, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8755_l1}, +/*h(10378)=8756 */ {10378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8756_l1}, +/*h(7794)=8757 */ {7794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8757_l1}, +/*h(11975)=8758 */ {11975, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8758_l1}, +/*h(5210)=8759 */ {5210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8759_l1}, +/*h(2626)=8760 */ {2626, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8760_l1}, +/*h(6807)=8761 */ {6807, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8761_l1}, +/*h(42)=8762 */ {42, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8762_l1}, +/*h(15169)=8763 */ {15169, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8763_l1}, +/*h(1639)=8764 */ {1639, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10001)=8766 */ {10001, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8766_l1}, +/*h(14182)=8767 */ {14182, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8767_l1}, +/*h(7417)=8768 */ {7417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8768_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4833)=8770 */ {4833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8770_l1}, +/*h(9014)=8771 */ {9014, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8771_l1}, +/*h(13195)=8772 */ {13195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8772_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3846)=8774 */ {3846, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8774_l1}, +/*h(8027)=8775 */ {8027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8775_l1}, +/*h(12208)=8776 */ {12208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8776_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2859)=8778 */ {2859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8778_l1}, +/*h(7040)=8779 */ {7040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8779_l1}, +/*h(11221)=8780 */ {11221, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8780_l1}, +/*h(15402)=8781 */ {15402, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8781_l1}, +/*h(12818)=8782 */ {12818, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8782_l1}, +/*h(6053)=8783 */ {6053, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8783_l1}, +/*h(10234)=8784 */ {10234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8784_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(885)=8786 */ {885, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8786_l1}, +/*h(5066)=8787 */ {5066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8787_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13428)=8789 */ {13428, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8789_l1}, +/*h(6663)=8790 */ {6663, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8790_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15025)=8792 */ {15025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8792_l1}, +/*h(12441)=8793 */ {12441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8793_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9857)=8795 */ {9857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8795_l1}, +/*h(14038)=8796 */ {14038, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8796_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4689)=8798 */ {4689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8798_l1}, +/*h(8870)=8799 */ {8870, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8799_l1}, +/*h(13051)=8800 */ {13051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8800_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3702)=8802 */ {3702, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8802_l1}, +/*h(7883)=8803 */ {7883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8803_l1}, +/*h(12064)=8804 */ {12064, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8804_l1}, +/*h(5299)=8805 */ {5299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8805_l1}, +/*h(2715)=8806 */ {2715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8806_l1}, +/*h(6896)=8807 */ {6896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8807_l1}, +/*h(131)=8808 */ {131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8808_l1}, +/*h(15258)=8809 */ {15258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8809_l1}, +/*h(1728)=8810 */ {1728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8810_l1}, +/*h(5909)=8811 */ {5909, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8811_l1}, +/*h(10090)=8812 */ {10090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8812_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(741)=8815 */ {741, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8815_l1}, +/*h(4922)=8816 */ {4922, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8816_l1}, +/*h(13284)=8817 */ {13284, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8817_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14881)=8820 */ {14881, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8820_l1}, +/*h(8116)=8821 */ {8116, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8821_l1}, +/*h(12297)=8822 */ {12297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8822_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13894)=8824 */ {13894, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8824_l1}, +/*h(7129)=8825 */ {7129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8726)=8827 */ {8726, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8827_l1}, +/*h(12907)=8828 */ {12907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8828_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10323)=8830 */ {10323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8830_l1}, +/*h(14504)=8831 */ {14504, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8831_l1}, +/*h(7739)=8832 */ {7739, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8832_l1}, +/*h(5155)=8833 */ {5155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8833_l1}, +/*h(9336)=8834 */ {9336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8834_l1}, +/*h(2571)=8835 */ {2571, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8835_l1}, +/*h(6752)=8836 */ {6752, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8836_l1}, +/*h(10933)=8837 */ {10933, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8837_l1}, +/*h(15114)=8838 */ {15114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8838_l1}, +/*h(12530)=8839 */ {12530, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8839_l1}, +/*h(5765)=8840 */ {5765, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8840_l1}, +/*h(9946)=8841 */ {9946, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8841_l1}, +/*h(7362)=8842 */ {7362, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8842_l1}, +/*h(597)=8843 */ {597, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8843_l1}, +/*h(4778)=8844 */ {4778, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8844_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2194)=8846 */ {2194, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8846_l1}, +/*h(6375)=8847 */ {6375, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8847_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7972)=8849 */ {7972, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8849_l1}, +/*h(1207)=8850 */ {1207, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8850_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2804)=8852 */ {2804, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8852_l1}, +/*h(6985)=8853 */ {6985, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8853_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15347)=8855 */ {15347, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8855_l1}, +/*h(1817)=8856 */ {1817, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8856_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10179)=8858 */ {10179, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8858_l1}, +/*h(14360)=8859 */ {14360, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8859_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11776)=8861 */ {11776, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8861_l1}, +/*h(5011)=8862 */ {5011, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8862_l1}, +/*h(9192)=8863 */ {9192, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8863_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10789)=8865 */ {10789, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8865_l1}, +/*h(14970)=8866 */ {14970, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8866_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12386)=8868 */ {12386, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8868_l1}, +/*h(9802)=8869 */ {9802, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8869_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7218)=8871 */ {7218, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8871_l1}, +/*h(4634)=8872 */ {4634, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8872_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2050)=8874 */ {2050, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8874_l1}, +/*h(6231)=8875 */ {6231, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8875_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1063)=8878 */ {1063, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8878_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9425)=8880 */ {9425, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8880_l1}, +/*h(2660)=8881 */ {2660, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8881_l1}, +/*h(6841)=8882 */ {6841, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8882_l1}, +/*h(4257)=8883 */ {4257, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8883_l1}, +/*h(15203)=8884 */ {15203, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8884_l1}, +/*h(1673)=8885 */ {1673, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8885_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3270)=8887 */ {3270, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8887_l1}, +/*h(14216)=8888 */ {14216, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8888_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4867)=8890 */ {4867, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8890_l1}, +/*h(9048)=8891 */ {9048, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8891_l1}, +/*h(2283)=8892 */ {2283, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8892_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3880)=8894 */ {3880, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8894_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12242)=8896 */ {12242, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8896_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7074)=8899 */ {7074, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8899_l1}, +/*h(11255)=8900 */ {11255, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8900_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1906)=8902 */ {1906, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8902_l1}, +/*h(6087)=8903 */ {6087, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14449)=8905 */ {14449, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8905_l1}, +/*h(7684)=8906 */ {7684, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8906_l1}, +/*h(919)=8907 */ {919, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8907_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13462)=8909 */ {13462, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8909_l1}, +/*h(6697)=8910 */ {6697, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8910_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15059)=8912 */ {15059, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8912_l1}, +/*h(8294)=8913 */ {8294, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8913_l1}, +/*h(12475)=8914 */ {12475, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8914_l1}, +/*h(9891)=8915 */ {9891, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8915_l1}, +/*h(3126)=8916 */ {3126, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8916_l1}, +/*h(7307)=8917 */ {7307, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8917_l1}, +/*h(4723)=8918 */ {4723, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8918_l1}, +/*h(8904)=8919 */ {8904, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8919_l1}, +/*h(2139)=8920 */ {2139, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8920_l1}, +/*h(6320)=8921 */ {6320, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8921_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3736)=8923 */ {3736, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8923_l1}, +/*h(12098)=8924 */ {12098, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8924_l1}, +/*h(16279)=8925 */ {16279, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8925_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6930)=8928 */ {6930, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8928_l1}, +/*h(11111)=8929 */ {11111, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8929_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1762)=8931 */ {1762, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8931_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14305)=8934 */ {14305, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8934_l1}, +/*h(775)=8935 */ {775, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8935_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9137)=8937 */ {9137, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8937_l1}, +/*h(13318)=8938 */ {13318, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8938_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14915)=8940 */ {14915, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8940_l1}, +/*h(8150)=8941 */ {8150, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8941_l1}, +/*h(12331)=8942 */ {12331, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8942_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2982)=8944 */ {2982, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8944_l1}, +/*h(7163)=8945 */ {7163, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8945_l1}, +/*h(11344)=8946 */ {11344, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8946_l1}, +/*h(15525)=8947 */ {15525, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8947_l1}, +/*h(1995)=8948 */ {1995, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8948_l1}, +/*h(6176)=8949 */ {6176, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8949_l1}, +/*h(10357)=8950 */ {10357, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8950_l1}, +/*h(14538)=8951 */ {14538, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8951_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11954)=8953 */ {11954, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8953_l1}, +/*h(16135)=8954 */ {16135, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8954_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6786)=8956 */ {6786, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8956_l1}, +/*h(10967)=8957 */ {10967, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8957_l1}, +/*h(4202)=8958 */ {4202, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8958_l1}, +/*h(1618)=8959 */ {1618, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8959_l1}, +/*h(5799)=8960 */ {5799, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8960_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14161)=8962 */ {14161, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8962_l1}, +/*h(631)=8963 */ {631, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8963_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8993)=8965 */ {8993, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8965_l1}, +/*h(13174)=8966 */ {13174, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8006)=8969 */ {8006, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8969_l1}, +/*h(12187)=8970 */ {12187, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8970_l1}, +/*h(16368)=8971 */ {16368, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8971_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2838)=8973 */ {2838, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8973_l1}, +/*h(7019)=8974 */ {7019, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8974_l1}, +/*h(11200)=8975 */ {11200, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8975_l1}, +/*h(15381)=8976 */ {15381, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8976_l1}, +/*h(1851)=8977 */ {1851, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8977_l1}, +/*h(6032)=8978 */ {6032, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8978_l1}, +/*h(10213)=8979 */ {10213, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8979_l1}, +/*h(14394)=8980 */ {14394, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8980_l1}, +/*h(11810)=8981 */ {11810, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8981_l1}, +/*h(15991)=8982 */ {15991, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8982_l1}, +/*h(9226)=8983 */ {9226, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8983_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10823)=8985 */ {10823, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8985_l1}, +/*h(4058)=8986 */ {4058, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12420)=8988 */ {12420, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8988_l1}, +/*h(5655)=8989 */ {5655, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8989_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14017)=8991 */ {14017, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8991_l1}, +/*h(11433)=8992 */ {11433, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8992_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8849)=8994 */ {8849, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8994_l1}, +/*h(13030)=8995 */ {13030, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8995_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3681)=8997 */ {3681, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8997_l1}, +/*h(7862)=8998 */ {7862, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8998_l1}, +/*h(12043)=8999 */ {12043, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_8999_l1}, +/*h(9459)=9000 */ {9459, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9000_l1}, +/*h(2694)=9001 */ {2694, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9001_l1}, +/*h(6875)=9002 */ {6875, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9002_l1}, +/*h(11056)=9003 */ {11056, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9003_l1}, +/*h(4291)=9004 */ {4291, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9004_l1}, +/*h(1707)=9005 */ {1707, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9005_l1}, +/*h(5888)=9006 */ {5888, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9006_l1}, +/*h(10069)=9007 */ {10069, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9007_l1}, +/*h(14250)=9008 */ {14250, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9008_l1}, +/*h(720)=9009 */ {720, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9009_l1}, +/*h(4901)=9010 */ {4901, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9010_l1}, +/*h(9082)=9011 */ {9082, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9011_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3914)=9015 */ {3914, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9015_l1}, +/*h(12276)=9016 */ {12276, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9016_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13873)=9019 */ {13873, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9019_l1}, +/*h(7108)=9020 */ {7108, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9020_l1}, +/*h(11289)=9021 */ {11289, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9021_l1}, +/*h(8705)=9022 */ {8705, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9022_l1}, +/*h(12886)=9023 */ {12886, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9023_l1}, +/*h(6121)=9024 */ {6121, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9024_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14483)=9026 */ {14483, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9026_l1}, +/*h(11899)=9027 */ {11899, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9027_l1}, +/*h(16080)=9028 */ {16080, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9028_l1}, +/*h(9315)=9029 */ {9315, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9029_l1}, +/*h(6731)=9030 */ {6731, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9030_l1}, +/*h(10912)=9031 */ {10912, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9031_l1}, +/*h(4147)=9032 */ {4147, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9032_l1}, +/*h(8328)=9033 */ {8328, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9033_l1}, +/*h(1563)=9034 */ {1563, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9034_l1}, +/*h(5744)=9035 */ {5744, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9035_l1}, +/*h(9925)=9036 */ {9925, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9036_l1}, +/*h(14106)=9037 */ {14106, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9037_l1}, +/*h(576)=9038 */ {576, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9038_l1}, +/*h(4757)=9039 */ {4757, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9039_l1}, +/*h(8938)=9040 */ {8938, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9040_l1}, +/*h(6354)=9041 */ {6354, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9041_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3770)=9043 */ {3770, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9043_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5367)=9045 */ {5367, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9045_l1}, +/*h(16313)=9046 */ {16313, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9046_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6964)=9048 */ {6964, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9048_l1}, +/*h(199)=9049 */ {199, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9049_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1796)=9051 */ {1796, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9051_l1}, +/*h(5977)=9052 */ {5977, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9052_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14339)=9054 */ {14339, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9054_l1}, +/*h(809)=9055 */ {809, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9055_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9171)=9057 */ {9171, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9057_l1}, +/*h(13352)=9058 */ {13352, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9058_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4003)=9060 */ {4003, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9060_l1}, +/*h(14949)=9061 */ {14949, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9781)=9064 */ {9781, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9064_l1}, +/*h(13962)=9065 */ {13962, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9065_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11378)=9067 */ {11378, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9067_l1}, +/*h(8794)=9068 */ {8794, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9068_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6210)=9070 */ {6210, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9070_l1}, +/*h(10391)=9071 */ {10391, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9071_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1042)=9073 */ {1042, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9073_l1}, +/*h(5223)=9074 */ {5223, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9074_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6820)=9076 */ {6820, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9076_l1}, +/*h(55)=9077 */ {55, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9077_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8417)=9079 */ {8417, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9079_l1}, +/*h(1652)=9080 */ {1652, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9080_l1}, +/*h(5833)=9081 */ {5833, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9081_l1}, +/*h(3249)=9082 */ {3249, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9082_l1}, +/*h(14195)=9083 */ {14195, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9083_l1}, +/*h(665)=9084 */ {665, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9084_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9027)=9086 */ {9027, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9086_l1}, +/*h(13208)=9087 */ {13208, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9087_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3859)=9089 */ {3859, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9089_l1}, +/*h(8040)=9090 */ {8040, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9090_l1}, +/*h(1275)=9091 */ {1275, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9091_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2872)=9093 */ {2872, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11234)=9095 */ {11234, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9095_l1}, +/*h(15415)=9096 */ {15415, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9096_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6066)=9098 */ {6066, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9098_l1}, +/*h(10247)=9099 */ {10247, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9099_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(898)=9101 */ {898, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9101_l1}, +/*h(5079)=9102 */ {5079, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9102_l1}, +/*h(16025)=9103 */ {16025, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9103_l1}, +/*h(13441)=9104 */ {13441, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9104_l1}, +/*h(6676)=9105 */ {6676, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9105_l1}, +/*h(10857)=9106 */ {10857, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9106_l1}, +/*h(8273)=9107 */ {8273, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9107_l1}, +/*h(12454)=9108 */ {12454, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9108_l1}, +/*h(5689)=9109 */ {5689, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9109_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14051)=9111 */ {14051, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9111_l1}, +/*h(7286)=9112 */ {7286, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9112_l1}, +/*h(11467)=9113 */ {11467, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9113_l1}, +/*h(8883)=9114 */ {8883, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9114_l1}, +/*h(2118)=9115 */ {2118, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9115_l1}, +/*h(6299)=9116 */ {6299, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9116_l1}, +/*h(3715)=9117 */ {3715, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9117_l1}, +/*h(7896)=9118 */ {7896, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9118_l1}, +/*h(1131)=9119 */ {1131, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9119_l1}, +/*h(16258)=9120 */ {16258, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9120_l1}, +/*h(2728)=9121 */ {2728, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11090)=9123 */ {11090, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9123_l1}, +/*h(15271)=9124 */ {15271, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9124_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10103)=9128 */ {10103, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(754)=9130 */ {754, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9130_l1}, +/*h(4935)=9131 */ {4935, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9131_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13297)=9133 */ {13297, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8129)=9136 */ {8129, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9136_l1}, +/*h(12310)=9137 */ {12310, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13907)=9139 */ {13907, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9139_l1}, +/*h(7142)=9140 */ {7142, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9140_l1}, +/*h(11323)=9141 */ {11323, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9141_l1}, +/*h(15504)=9142 */ {15504, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9142_l1}, +/*h(1974)=9143 */ {1974, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9143_l1}, +/*h(6155)=9144 */ {6155, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9144_l1}, +/*h(10336)=9145 */ {10336, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9145_l1}, +/*h(14517)=9146 */ {14517, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9146_l1}, +/*h(987)=9147 */ {987, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9147_l1}, +/*h(5168)=9148 */ {5168, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9148_l1}, +/*h(16114)=9149 */ {16114, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9149_l1}, +/*h(13530)=9150 */ {13530, xed3_phash_find_maplegacy_map1_opcode0x1e_vv0_9150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9152ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x1f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x1F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {692}, +/*h(1)=1 0x0F 0x1F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {693} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x20_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1155}, +/*h(1)=1 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1155}, +/*h(2)=2 0x0F 0x20 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64*/ {1156} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x21_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1159}, +/*h(1)=1 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1159}, +/*h(2)=2 0x0F 0x21 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64*/ {1160} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x22_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1153}, +/*h(1)=1 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1153}, +/*h(2)=2 0x0F 0x22 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64*/ {1154} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x23_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1157}, +/*h(1)=1 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() not64*/ {1157}, +/*h(2)=2 0x0F 0x23 MOD[mm] REG[rrr] RM[nnn] CR_WIDTH() mode64*/ {1158} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x28_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x28 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1391}, +/*h(1)=1 0x0F 0x28 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1392}, +/*h(2)=2 0x0F 0x28 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1418}, +/*h(3)=3 0x0F 0x28 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1419} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x29_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x29 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1393}, +/*h(1)=1 0x0F 0x29 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1394}, +/*h(2)=2 0x0F 0x29 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1420}, +/*h(3)=3 0x0F 0x29 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1421} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1395}, +/*h(13)=1 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {13, 1407}, +/*h(26)=2 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {26, 1435}, +/*empty slot1 */ {0,0}, +/*h(18)=4 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {18, 1422}, +/*h(31)=5 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {31, 1409}, +/*h(10)=6 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {10, 1433}, +/*empty slot1 */ {0,0}, +/*h(2)=8 0x0F 0x2A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1422}, +/*h(15)=9 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {15, 1407}, +/*h(28)=10 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {28, 1408}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=14 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {12, 1406}, +/*h(25)=15 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {25, 1436}, +/*empty slot1 */ {0,0}, +/*h(17)=17 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 1396}, +/*h(30)=18 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {30, 1408}, +/*h(9)=19 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {9, 1434}, +/*empty slot1 */ {0,0}, +/*h(1)=21 0x0F 0x2A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1396}, +/*h(14)=22 0x0F 0x2A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {14, 1406}, +/*h(27)=23 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {27, 1436}, +/*empty slot1 */ {0,0}, +/*h(19)=25 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {19, 1423}, +/*empty slot1 */ {0,0}, +/*h(11)=27 0x0F 0x2A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {11, 1434}, +/*h(24)=28 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {24, 1435}, +/*h(3)=29 0x0F 0x2A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1423}, +/*h(16)=30 0x0F 0x2A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16, 1395}, +/*h(29)=31 0x0F 0x2A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {29, 1409}, +/*h(8)=32 0x0F 0x2A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {8, 1433}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(0)=0 0x0F 0x2B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1397}, +/*h(10)=1 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2018}, +/*h(2)=2 0x0F 0x2B osz_refining_prefix REFINING66() MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 1424}, +/*h(12)=3 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2019}, +/*empty slot1 */ {0,0}, +/*h(14)=5 0x0F 0x2B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2019}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=8 0x0F 0x2B f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2018} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1398}, +/*h(13)=1 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {13, 1411}, +/*h(26)=2 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {26, 1439}, +/*empty slot1 */ {0,0}, +/*h(18)=4 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {18, 1425}, +/*h(31)=5 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {31, 1413}, +/*h(10)=6 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {10, 1437}, +/*empty slot1 */ {0,0}, +/*h(2)=8 0x0F 0x2C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1425}, +/*h(15)=9 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {15, 1411}, +/*h(28)=10 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {28, 1412}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=14 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {12, 1410}, +/*h(25)=15 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {25, 1440}, +/*empty slot1 */ {0,0}, +/*h(17)=17 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 1399}, +/*h(30)=18 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {30, 1412}, +/*h(9)=19 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {9, 1438}, +/*empty slot1 */ {0,0}, +/*h(1)=21 0x0F 0x2C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1399}, +/*h(14)=22 0x0F 0x2C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {14, 1410}, +/*h(27)=23 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {27, 1440}, +/*empty slot1 */ {0,0}, +/*h(19)=25 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {19, 1426}, +/*empty slot1 */ {0,0}, +/*h(11)=27 0x0F 0x2C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {11, 1438}, +/*h(24)=28 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {24, 1439}, +/*h(3)=29 0x0F 0x2C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1426}, +/*h(16)=30 0x0F 0x2C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16, 1398}, +/*h(29)=31 0x0F 0x2C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {29, 1413}, +/*h(8)=32 0x0F 0x2C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {8, 1437}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1400}, +/*h(13)=1 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {13, 1415}, +/*h(26)=2 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {26, 1443}, +/*empty slot1 */ {0,0}, +/*h(18)=4 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {18, 1427}, +/*h(31)=5 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {31, 1417}, +/*h(10)=6 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {10, 1441}, +/*empty slot1 */ {0,0}, +/*h(2)=8 0x0F 0x2D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1427}, +/*h(15)=9 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {15, 1415}, +/*h(28)=10 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {28, 1416}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=14 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {12, 1414}, +/*h(25)=15 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {25, 1444}, +/*empty slot1 */ {0,0}, +/*h(17)=17 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 1401}, +/*h(30)=18 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {30, 1416}, +/*h(9)=19 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {9, 1442}, +/*empty slot1 */ {0,0}, +/*h(1)=21 0x0F 0x2D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1401}, +/*h(14)=22 0x0F 0x2D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {14, 1414}, +/*h(27)=23 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {27, 1444}, +/*empty slot1 */ {0,0}, +/*h(19)=25 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {19, 1428}, +/*empty slot1 */ {0,0}, +/*h(11)=27 0x0F 0x2D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix*/ {11, 1442}, +/*h(24)=28 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix MODRM()*/ {24, 1443}, +/*h(3)=29 0x0F 0x2D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1428}, +/*h(16)=30 0x0F 0x2D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16, 1400}, +/*h(29)=31 0x0F 0x2D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() rexw_prefix*/ {29, 1417}, +/*h(8)=32 0x0F 0x2D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() norexw_prefix MODRM()*/ {8, 1441}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x2E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1402}, +/*h(1)=1 0x0F 0x2E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1403}, +/*h(2)=2 0x0F 0x2E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1429}, +/*h(3)=3 0x0F 0x2E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1430} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x2f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x2F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1404}, +/*h(1)=1 0x0F 0x2F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1405}, +/*h(2)=2 0x0F 0x2F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1431}, +/*h(3)=3 0x0F 0x2F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1432} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x30_vv0(const xed_decoded_inst_t* d) +{ +return 1161; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x31_vv0(const xed_decoded_inst_t* d) +{ +return 1162; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x32_vv0(const xed_decoded_inst_t* d) +{ +return 1163; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x33_vv0(const xed_decoded_inst_t* d) +{ +return 1164; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x34_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x34 not64*/ {1165}, +/*h(1)=1 0x0F 0x34 not64*/ {1165}, +/*h(2)=2 0x0F 0x34 mode64*/ {1166} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x35_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x35 not64*/ {1167}, +/*h(1)=1 0x0F 0x35 not64*/ {1167}, +/*h(2)=2 0x0F 0x35 mode64*/ {1168} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x37_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 0x0F 0x37 no_refining_prefix*/ {1918} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_OSZ_REP(d); +hidx = key - 0; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x40_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x40 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1169}, +/*h(1)=1 0x0F 0x40 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1170} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x41_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x41 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1171}, +/*h(1)=1 0x0F 0x41 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1172} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x42_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x42 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1173}, +/*h(1)=1 0x0F 0x42 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1174} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x43_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x43 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1175}, +/*h(1)=1 0x0F 0x43 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x44_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x44 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1177}, +/*h(1)=1 0x0F 0x44 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1178} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x45_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x45 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1179}, +/*h(1)=1 0x0F 0x45 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1180} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x46_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x46 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1181}, +/*h(1)=1 0x0F 0x46 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1182} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x47_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x47 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1183}, +/*h(1)=1 0x0F 0x47 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x48_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x48 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1445}, +/*h(1)=1 0x0F 0x48 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1446} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x49_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x49 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1447}, +/*h(1)=1 0x0F 0x49 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1448} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x4A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1449}, +/*h(1)=1 0x0F 0x4A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1450} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x4B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1451}, +/*h(1)=1 0x0F 0x4B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1452} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x4C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1453}, +/*h(1)=1 0x0F 0x4C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1454} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x4D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1455}, +/*h(1)=1 0x0F 0x4D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1456} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x4E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1457}, +/*h(1)=1 0x0F 0x4E MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1458} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x4f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x4F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1459}, +/*h(1)=1 0x0F 0x4F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1460} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x50_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(1)=1 0x0F 0x50 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1185}, +/*h(3)=2 0x0F 0x50 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1206} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x51_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x51 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1186}, +/*h(10)=1 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1217}, +/*h(12)=2 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1200}, +/*h(1)=3 0x0F 0x51 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1187}, +/*h(11)=4 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1218}, +/*h(13)=5 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1201}, +/*h(2)=6 0x0F 0x51 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1207}, +/*h(8)=7 0x0F 0x51 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1217}, +/*h(14)=8 0x0F 0x51 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1200}, +/*h(3)=9 0x0F 0x51 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1208}, +/*h(9)=10 0x0F 0x51 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1218}, +/*h(15)=11 0x0F 0x51 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x52_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(0)=0 0x0F 0x52 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1188}, +/*h(13)=1 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1203}, +/*h(12)=2 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1202}, +/*h(15)=3 0x0F 0x52 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1203}, +/*h(1)=4 0x0F 0x52 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1189}, +/*h(14)=5 0x0F 0x52 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((4*key % 17) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x53_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(0)=0 0x0F 0x53 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1190}, +/*h(13)=1 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1205}, +/*h(12)=2 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1204}, +/*h(15)=3 0x0F 0x53 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1205}, +/*h(1)=4 0x0F 0x53 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1191}, +/*h(14)=5 0x0F 0x53 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((4*key % 17) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x54_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x54 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1192}, +/*h(1)=1 0x0F 0x54 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1193}, +/*h(2)=2 0x0F 0x54 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1209}, +/*h(3)=3 0x0F 0x54 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1210} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x55_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x55 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1194}, +/*h(1)=1 0x0F 0x55 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1195}, +/*h(2)=2 0x0F 0x55 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1211}, +/*h(3)=3 0x0F 0x55 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1212} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x56_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x56 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1196}, +/*h(1)=1 0x0F 0x56 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1197}, +/*h(2)=2 0x0F 0x56 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1213}, +/*h(3)=3 0x0F 0x56 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1214} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x57_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x57 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1198}, +/*h(1)=1 0x0F 0x57 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1199}, +/*h(2)=2 0x0F 0x57 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1215}, +/*h(3)=3 0x0F 0x57 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1216} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x58_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x58 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1461}, +/*h(10)=1 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1509}, +/*h(12)=2 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1477}, +/*h(1)=3 0x0F 0x58 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1462}, +/*h(11)=4 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1510}, +/*h(13)=5 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1478}, +/*h(2)=6 0x0F 0x58 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1493}, +/*h(8)=7 0x0F 0x58 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1509}, +/*h(14)=8 0x0F 0x58 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1477}, +/*h(3)=9 0x0F 0x58 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1494}, +/*h(9)=10 0x0F 0x58 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1510}, +/*h(15)=11 0x0F 0x58 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1478} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x59_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x59 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1463}, +/*h(10)=1 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1511}, +/*h(12)=2 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1479}, +/*h(1)=3 0x0F 0x59 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1464}, +/*h(11)=4 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1512}, +/*h(13)=5 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1480}, +/*h(2)=6 0x0F 0x59 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1495}, +/*h(8)=7 0x0F 0x59 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1511}, +/*h(14)=8 0x0F 0x59 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1479}, +/*h(3)=9 0x0F 0x59 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1496}, +/*h(9)=10 0x0F 0x59 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1512}, +/*h(15)=11 0x0F 0x59 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1480} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x5A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1465}, +/*h(10)=1 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1513}, +/*h(12)=2 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1481}, +/*h(1)=3 0x0F 0x5A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1466}, +/*h(11)=4 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1514}, +/*h(13)=5 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1482}, +/*h(2)=6 0x0F 0x5A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1497}, +/*h(8)=7 0x0F 0x5A f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1513}, +/*h(14)=8 0x0F 0x5A f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1481}, +/*h(3)=9 0x0F 0x5A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1498}, +/*h(9)=10 0x0F 0x5A f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1514}, +/*h(15)=11 0x0F 0x5A f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1482} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 0x0F 0x5B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1467}, +/*h(1)=1 0x0F 0x5B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1468}, +/*h(2)=2 0x0F 0x5B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1499}, +/*h(3)=3 0x0F 0x5B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1500}, +/*h(12)=4 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1483}, +/*h(13)=5 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1484}, +/*h(14)=6 0x0F 0x5B f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1483}, +/*h(15)=7 0x0F 0x5B f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1484} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((18*key % 17) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x5C no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1469}, +/*h(10)=1 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1515}, +/*h(12)=2 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1485}, +/*h(1)=3 0x0F 0x5C no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1470}, +/*h(11)=4 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1516}, +/*h(13)=5 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1486}, +/*h(2)=6 0x0F 0x5C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1501}, +/*h(8)=7 0x0F 0x5C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1515}, +/*h(14)=8 0x0F 0x5C f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1485}, +/*h(3)=9 0x0F 0x5C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1502}, +/*h(9)=10 0x0F 0x5C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1516}, +/*h(15)=11 0x0F 0x5C f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1486} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x5D no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1471}, +/*h(10)=1 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1517}, +/*h(12)=2 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1487}, +/*h(1)=3 0x0F 0x5D no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1472}, +/*h(11)=4 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1518}, +/*h(13)=5 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1488}, +/*h(2)=6 0x0F 0x5D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1503}, +/*h(8)=7 0x0F 0x5D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1517}, +/*h(14)=8 0x0F 0x5D f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1487}, +/*h(3)=9 0x0F 0x5D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1504}, +/*h(9)=10 0x0F 0x5D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1518}, +/*h(15)=11 0x0F 0x5D f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1488} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x5E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1473}, +/*h(10)=1 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1519}, +/*h(12)=2 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1489}, +/*h(1)=3 0x0F 0x5E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1474}, +/*h(11)=4 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1520}, +/*h(13)=5 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1490}, +/*h(2)=6 0x0F 0x5E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1505}, +/*h(8)=7 0x0F 0x5E f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1519}, +/*h(14)=8 0x0F 0x5E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1489}, +/*h(3)=9 0x0F 0x5E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1506}, +/*h(9)=10 0x0F 0x5E f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1520}, +/*h(15)=11 0x0F 0x5E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1490} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x5f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x5F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1475}, +/*h(10)=1 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1521}, +/*h(12)=2 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1491}, +/*h(1)=3 0x0F 0x5F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1476}, +/*h(11)=4 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1522}, +/*h(13)=5 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1492}, +/*h(2)=6 0x0F 0x5F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1507}, +/*h(8)=7 0x0F 0x5F f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1521}, +/*h(14)=8 0x0F 0x5F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1491}, +/*h(3)=9 0x0F 0x5F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1508}, +/*h(9)=10 0x0F 0x5F f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1522}, +/*h(15)=11 0x0F 0x5F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1492} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x60_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x60 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1219}, +/*h(1)=1 0x0F 0x60 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1220}, +/*h(2)=2 0x0F 0x60 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1221}, +/*h(3)=3 0x0F 0x60 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1222} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x61_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x61 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1223}, +/*h(1)=1 0x0F 0x61 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1224}, +/*h(2)=2 0x0F 0x61 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1225}, +/*h(3)=3 0x0F 0x61 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x62_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x62 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1227}, +/*h(1)=1 0x0F 0x62 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1228}, +/*h(2)=2 0x0F 0x62 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1229}, +/*h(3)=3 0x0F 0x62 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1230} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x63_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x63 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1231}, +/*h(1)=1 0x0F 0x63 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1232}, +/*h(2)=2 0x0F 0x63 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1233}, +/*h(3)=3 0x0F 0x63 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1234} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x64_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x64 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1235}, +/*h(1)=1 0x0F 0x64 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1236}, +/*h(2)=2 0x0F 0x64 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1237}, +/*h(3)=3 0x0F 0x64 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x65_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x65 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1239}, +/*h(1)=1 0x0F 0x65 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1240}, +/*h(2)=2 0x0F 0x65 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1241}, +/*h(3)=3 0x0F 0x65 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x66_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x66 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1243}, +/*h(1)=1 0x0F 0x66 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1244}, +/*h(2)=2 0x0F 0x66 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1245}, +/*h(3)=3 0x0F 0x66 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x67_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x67 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1247}, +/*h(1)=1 0x0F 0x67 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1248}, +/*h(2)=2 0x0F 0x67 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1249}, +/*h(3)=3 0x0F 0x67 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x68_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x68 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1523}, +/*h(1)=1 0x0F 0x68 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1524}, +/*h(2)=2 0x0F 0x68 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1525}, +/*h(3)=3 0x0F 0x68 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1526} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x69_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x69 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1527}, +/*h(1)=1 0x0F 0x69 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1528}, +/*h(2)=2 0x0F 0x69 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1529}, +/*h(3)=3 0x0F 0x69 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x6A no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1531}, +/*h(1)=1 0x0F 0x6A no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1532}, +/*h(2)=2 0x0F 0x6A osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1533}, +/*h(3)=3 0x0F 0x6A osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x6B no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1535}, +/*h(1)=1 0x0F 0x6B no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1536}, +/*h(2)=2 0x0F 0x6B osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1537}, +/*h(3)=3 0x0F 0x6B osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1538} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x6C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1571}, +/*h(3)=1 0x0F 0x6C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1572} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0x0F 0x6D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1573}, +/*h(3)=1 0x0F 0x6D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1574} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(0)=0 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {0, 1549}, +/*empty slot1 */ {0,0}, +/*h(69)=2 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix*/ {69, 1564}, +/*h(1)=3 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {1, 1550}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=6 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {2, 1549}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=9 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {3, 1550}, +/*empty slot1 */ {0,0}, +/*h(72)=11 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {72, 1541}, +/*h(4)=12 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM()*/ {4, 1547}, +/*empty slot1 */ {0,0}, +/*h(73)=14 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {73, 1542}, +/*h(5)=15 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix*/ {5, 1548}, +/*empty slot1 */ {0,0}, +/*h(74)=17 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {74, 1541}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=20 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {75, 1542}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM()*/ {76, 1555}, +/*h(8)=24 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {8, 1541}, +/*empty slot1 */ {0,0}, +/*h(77)=26 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix*/ {77, 1556}, +/*h(9)=27 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {9, 1542}, +/*h(64)=28 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {64, 1549}, +/*empty slot1 */ {0,0}, +/*h(10)=30 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {10, 1541}, +/*h(65)=31 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {65, 1550}, +/*empty slot1 */ {0,0}, +/*h(11)=33 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {11, 1542}, +/*h(66)=34 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {66, 1549}, +/*empty slot1 */ {0,0}, +/*h(12)=36 0x0F 0x6E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM()*/ {12, 1539}, +/*h(67)=37 0x0F 0x6E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {67, 1550}, +/*empty slot1 */ {0,0}, +/*h(13)=39 0x0F 0x6E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix*/ {13, 1540}, +/*h(68)=40 0x0F 0x6E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM()*/ {68, 1563} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x6f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 0x0F 0x6F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1567}, +/*h(1)=1 0x0F 0x6F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1568}, +/*h(2)=2 0x0F 0x6F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1593}, +/*h(3)=3 0x0F 0x6F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1594}, +/*h(12)=4 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1575}, +/*h(13)=5 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1576}, +/*h(14)=6 0x0F 0x6F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1575}, +/*h(15)=7 0x0F 0x6F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1576} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((18*key % 17) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x70_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0x70 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {0, 1251}, +/*h(10)=1 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {10, 1268}, +/*h(12)=2 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {12, 1270}, +/*h(1)=3 0x0F 0x70 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1, 1252}, +/*h(11)=4 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {11, 1269}, +/*h(13)=5 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {13, 1271}, +/*h(2)=6 0x0F 0x70 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {2, 1266}, +/*h(8)=7 0x0F 0x70 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {8, 1268}, +/*h(14)=8 0x0F 0x70 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {14, 1270}, +/*h(3)=9 0x0F 0x70 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {3, 1267}, +/*h(9)=10 0x0F 0x70 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {9, 1269}, +/*h(15)=11 0x0F 0x70 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {15, 1271} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x71_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(11)=0 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8()*/ {11, 617}, +/*h(17)=1 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {17, 622}, +/*h(19)=2 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8()*/ {19, 623}, +/*h(25)=3 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {25, 628}, +/*h(27)=4 0x0F 0x71 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8()*/ {27, 629}, +/*h(9)=5 0x0F 0x71 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {9, 616} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REG_REP(d); +hidx = ((3*key % 11) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x72_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(11)=0 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8()*/ {11, 635}, +/*h(17)=1 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {17, 640}, +/*h(19)=2 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b100] RM[nnn] REFINING66() UIMM8()*/ {19, 641}, +/*h(25)=3 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {25, 646}, +/*h(27)=4 0x0F 0x72 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8()*/ {27, 647}, +/*h(9)=5 0x0F 0x72 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {9, 634} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REG_REP(d); +hidx = ((3*key % 11) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x73_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(31)=1 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b111] RM[nnn] REFINING66() UIMM8()*/ {31, 665}, +/*h(15)=2 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b011] RM[nnn] REFINING66() UIMM8()*/ {15, 664}, +/*h(25)=3 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {25, 658}, +/*h(9)=4 0x0F 0x73 no_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {9, 652}, +/*h(27)=5 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b110] RM[nnn] REFINING66() UIMM8()*/ {27, 659}, +/*h(11)=6 0x0F 0x73 osz_refining_prefix MOD[0b11] MOD=3 REG[0b010] RM[nnn] REFINING66() UIMM8()*/ {11, 653}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REG_REP(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x74_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x74 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1253}, +/*h(1)=1 0x0F 0x74 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1254}, +/*h(2)=2 0x0F 0x74 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1255}, +/*h(3)=3 0x0F 0x74 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1256} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x75_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x75 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1257}, +/*h(1)=1 0x0F 0x75 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1258}, +/*h(2)=2 0x0F 0x75 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1259}, +/*h(3)=3 0x0F 0x75 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1260} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x76_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0x76 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1261}, +/*h(1)=1 0x0F 0x76 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1262}, +/*h(2)=2 0x0F 0x76 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1263}, +/*h(3)=3 0x0F 0x76 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1264} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x77_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 0x0F 0x77 no_refining_prefix*/ {1265} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_OSZ_REP(d); +hidx = key - 0; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x78_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[198] = { +/*h(0)=0 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {0, 1581}, +/*h(265)=1 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {265, 2016}, +/*h(113)=2 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {113, 1582}, +/*h(305)=3 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {305, 2016}, +/*h(80)=4 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {80, 1581}, +/*h(1)=5 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {1, 1582}, +/*h(339)=6 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {339, 2016}, +/*h(114)=7 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {114, 1581}, +/*h(379)=8 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {379, 2016}, +/*h(81)=9 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {81, 1582}, +/*h(2)=10 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {2, 1581}, +/*h(267)=11 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {267, 2016}, +/*h(115)=12 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {115, 1582}, +/*h(307)=13 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {307, 2016}, +/*h(82)=14 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {82, 1581}, +/*h(3)=15 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {3, 1582}, +/*h(341)=16 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {341, 2016}, +/*h(116)=17 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {116, 1579}, +/*h(381)=18 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {381, 2016}, +/*h(83)=19 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {83, 1582}, +/*h(4)=20 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {4, 1579}, +/*h(269)=21 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {269, 2016}, +/*h(117)=22 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {117, 1580}, +/*h(309)=23 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {309, 2016}, +/*h(84)=24 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {84, 1579}, +/*h(5)=25 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {5, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(85)=29 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {85, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=36 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {345, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(273)=41 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {273, 2016}, +/*h(48)=42 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {48, 1581}, +/*h(313)=43 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {313, 2016}, +/*empty slot1 */ {0,0}, +/*h(9)=45 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()*/ {9, 2014}, +/*h(347)=46 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {347, 2016}, +/*h(49)=47 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {49, 1582}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(275)=51 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {275, 2016}, +/*h(50)=52 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {50, 1581}, +/*h(315)=53 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {315, 2016}, +/*empty slot1 */ {0,0}, +/*h(11)=55 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()*/ {11, 2014}, +/*h(349)=56 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {349, 2016}, +/*h(51)=57 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {51, 1582}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(277)=61 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {277, 2016}, +/*h(52)=62 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {52, 1579}, +/*h(317)=63 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {317, 2016}, +/*empty slot1 */ {0,0}, +/*h(13)=65 0x0F 0x78 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8() UIMM8_1()*/ {13, 2014}, +/*empty slot1 */ {0,0}, +/*h(53)=67 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {53, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(353)=76 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {353, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=80 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {16, 1581}, +/*h(281)=81 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {281, 2016}, +/*empty slot1 */ {0,0}, +/*h(321)=83 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {321, 2016}, +/*h(96)=84 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {96, 1581}, +/*h(17)=85 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {17, 1582}, +/*h(355)=86 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {355, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(97)=89 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {97, 1582}, +/*h(18)=90 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {18, 1581}, +/*h(283)=91 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {283, 2016}, +/*empty slot1 */ {0,0}, +/*h(323)=93 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {323, 2016}, +/*h(98)=94 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {98, 1581}, +/*h(19)=95 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {19, 1582}, +/*h(357)=96 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {357, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(99)=99 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {99, 1582}, +/*h(20)=100 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {20, 1579}, +/*h(285)=101 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {285, 2016}, +/*empty slot1 */ {0,0}, +/*h(325)=103 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {325, 2016}, +/*h(100)=104 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {100, 1579}, +/*h(21)=105 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {21, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(101)=109 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {101, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(361)=116 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {361, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(289)=121 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {289, 2016}, +/*h(64)=122 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {64, 1581}, +/*h(329)=123 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {329, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(363)=126 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {363, 2016}, +/*h(65)=127 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {65, 1582}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(291)=131 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {291, 2016}, +/*h(66)=132 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {66, 1581}, +/*h(331)=133 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {331, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(365)=136 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {365, 2016}, +/*h(67)=137 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {67, 1582}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(293)=141 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {293, 2016}, +/*h(68)=142 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {68, 1579}, +/*h(333)=143 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {333, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(69)=147 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {69, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(369)=156 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {369, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(257)=159 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {257, 2016}, +/*h(32)=160 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {32, 1581}, +/*h(297)=161 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {297, 2016}, +/*empty slot1 */ {0,0}, +/*h(337)=163 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {337, 2016}, +/*h(112)=164 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {112, 1581}, +/*h(33)=165 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {33, 1582}, +/*h(371)=166 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {371, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(259)=169 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {259, 2016}, +/*h(34)=170 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {34, 1581}, +/*h(299)=171 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {299, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(35)=175 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {35, 1582}, +/*h(373)=176 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {373, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(261)=179 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {261, 2016}, +/*h(36)=180 0x0F 0x78 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {36, 1579}, +/*h(301)=181 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {301, 2016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=185 0x0F 0x78 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {37, 1580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(377)=196 0x0F 0x78 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() UIMM8_1()*/ {377, 2016}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP(d); +hidx = ((5*key % 563) % 198); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x79_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[23] = { +/*h(0)=0 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {0, 1585}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {1, 1586}, +/*h(9)=4 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2015}, +/*empty slot1 */ {0,0}, +/*h(2)=6 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM() CR_WIDTH()*/ {2, 1585}, +/*h(33)=7 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {33, 2017}, +/*h(41)=8 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {41, 2017}, +/*h(3)=9 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 CR_WIDTH()*/ {3, 1586}, +/*h(11)=10 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2015}, +/*empty slot1 */ {0,0}, +/*h(4)=12 0x0F 0x79 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM() CR_WIDTH()*/ {4, 1583}, +/*h(35)=13 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {35, 2017}, +/*h(43)=14 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {43, 2017}, +/*h(5)=15 0x0F 0x79 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 CR_WIDTH()*/ {5, 1584}, +/*h(13)=16 0x0F 0x79 osz_refining_prefix REFINING66() MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2015}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=19 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {37, 2017}, +/*h(45)=20 0x0F 0x79 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 2017}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP(d); +hidx = (3*key % 23); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1595}, +/*h(2)=2 0x0F 0x7C osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1587}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1596}, +/*empty slot1 */ {0,0}, +/*h(11)=7 0x0F 0x7C f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1596}, +/*h(3)=8 0x0F 0x7C osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1588}, +/*h(8)=9 0x0F 0x7C f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1595} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1597}, +/*h(2)=2 0x0F 0x7D osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1589}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1598}, +/*empty slot1 */ {0,0}, +/*h(11)=7 0x0F 0x7D f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1598}, +/*h(3)=8 0x0F 0x7D osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1590}, +/*h(8)=9 0x0F 0x7D f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1597} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[48] = { +/*h(0)=0 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {0, 1553}, +/*h(125)=1 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {125, 1562}, +/*h(52)=2 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {52, 1561}, +/*h(8)=3 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {8, 1545}, +/*h(5)=4 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 norexw_prefix*/ {5, 1552}, +/*h(60)=5 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {60, 1561}, +/*h(115)=6 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {115, 1562}, +/*h(13)=7 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix*/ {13, 1544}, +/*h(68)=8 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM()*/ {68, 1565}, +/*h(123)=9 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {123, 1562}, +/*h(50)=10 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {50, 1561}, +/*h(76)=11 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix MODRM()*/ {76, 1557}, +/*h(3)=12 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {3, 1554}, +/*h(58)=13 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {58, 1561}, +/*h(113)=14 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {113, 1562}, +/*h(11)=15 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {11, 1546}, +/*h(66)=16 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {66, 1553}, +/*h(121)=17 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {121, 1562}, +/*h(48)=18 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {48, 1561}, +/*h(74)=19 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {74, 1545}, +/*h(1)=20 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {1, 1554}, +/*h(56)=21 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {56, 1561}, +/*h(53)=22 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {53, 1562}, +/*h(9)=23 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {9, 1546}, +/*h(64)=24 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {64, 1553}, +/*h(61)=25 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {61, 1562}, +/*h(116)=26 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {116, 1561}, +/*h(72)=27 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {72, 1545}, +/*h(69)=28 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 rexw_prefix*/ {69, 1566}, +/*h(124)=29 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {124, 1561}, +/*h(51)=30 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {51, 1562}, +/*h(77)=31 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() mode64 rexw_prefix*/ {77, 1558}, +/*h(4)=32 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM()*/ {4, 1551}, +/*h(59)=33 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {59, 1562}, +/*h(114)=34 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {114, 1561}, +/*h(12)=35 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() mode64 norexw_prefix MODRM()*/ {12, 1543}, +/*h(67)=36 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {67, 1554}, +/*h(122)=37 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {122, 1561}, +/*h(49)=38 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {49, 1562}, +/*h(75)=39 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {75, 1546}, +/*h(2)=40 0x0F 0x7E no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {2, 1553}, +/*h(57)=41 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {57, 1562}, +/*h(112)=42 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {112, 1561}, +/*h(10)=43 0x0F 0x7E osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() not64 MODRM()*/ {10, 1545}, +/*h(65)=44 0x0F 0x7E no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {65, 1554}, +/*h(120)=45 0x0F 0x7E f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {120, 1561}, +/*h(117)=46 0x0F 0x7E f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {117, 1562}, +/*h(73)=47 0x0F 0x7E osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() not64*/ {73, 1546} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((20*key % 157) % 48); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x7f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 0x0F 0x7F no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1569}, +/*h(1)=1 0x0F 0x7F no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1570}, +/*h(2)=2 0x0F 0x7F osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1591}, +/*h(3)=3 0x0F 0x7F osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1592}, +/*h(12)=4 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1577}, +/*h(13)=5 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1578}, +/*h(14)=6 0x0F 0x7F f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1577}, +/*h(15)=7 0x0F 0x7F f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1578} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((18*key % 17) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x80_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x80 not64 BRANCH_HINT() BRDISPz()*/ {835}, +/*h(1)=1 0x0F 0x80 not64 BRANCH_HINT() BRDISPz()*/ {835}, +/*h(2)=2 0x0F 0x80 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {834} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x81_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x81 not64 BRANCH_HINT() BRDISPz()*/ {838}, +/*h(1)=1 0x0F 0x81 not64 BRANCH_HINT() BRDISPz()*/ {838}, +/*h(2)=2 0x0F 0x81 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {839} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x82_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x82 not64 BRANCH_HINT() BRDISPz()*/ {842}, +/*h(1)=1 0x0F 0x82 not64 BRANCH_HINT() BRDISPz()*/ {842}, +/*h(2)=2 0x0F 0x82 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {843} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x83_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x83 not64 BRANCH_HINT() BRDISPz()*/ {846}, +/*h(1)=1 0x0F 0x83 not64 BRANCH_HINT() BRDISPz()*/ {846}, +/*h(2)=2 0x0F 0x83 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {847} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x84_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x84 not64 BRANCH_HINT() BRDISPz()*/ {850}, +/*h(1)=1 0x0F 0x84 not64 BRANCH_HINT() BRDISPz()*/ {850}, +/*h(2)=2 0x0F 0x84 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {851} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x85_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x85 not64 BRANCH_HINT() BRDISPz()*/ {854}, +/*h(1)=1 0x0F 0x85 not64 BRANCH_HINT() BRDISPz()*/ {854}, +/*h(2)=2 0x0F 0x85 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {855} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x86_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x86 not64 BRANCH_HINT() BRDISPz()*/ {858}, +/*h(1)=1 0x0F 0x86 not64 BRANCH_HINT() BRDISPz()*/ {858}, +/*h(2)=2 0x0F 0x86 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {859} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x87_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x87 not64 BRANCH_HINT() BRDISPz()*/ {862}, +/*h(1)=1 0x0F 0x87 not64 BRANCH_HINT() BRDISPz()*/ {862}, +/*h(2)=2 0x0F 0x87 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {863} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x88_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x88 not64 BRANCH_HINT() BRDISPz()*/ {866}, +/*h(1)=1 0x0F 0x88 not64 BRANCH_HINT() BRDISPz()*/ {866}, +/*h(2)=2 0x0F 0x88 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {867} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x89_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x89 not64 BRANCH_HINT() BRDISPz()*/ {870}, +/*h(1)=1 0x0F 0x89 not64 BRANCH_HINT() BRDISPz()*/ {870}, +/*h(2)=2 0x0F 0x89 mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {871} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x8A not64 BRANCH_HINT() BRDISPz()*/ {874}, +/*h(1)=1 0x0F 0x8A not64 BRANCH_HINT() BRDISPz()*/ {874}, +/*h(2)=2 0x0F 0x8A mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {875} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x8B not64 BRANCH_HINT() BRDISPz()*/ {878}, +/*h(1)=1 0x0F 0x8B not64 BRANCH_HINT() BRDISPz()*/ {878}, +/*h(2)=2 0x0F 0x8B mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {879} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x8C not64 BRANCH_HINT() BRDISPz()*/ {882}, +/*h(1)=1 0x0F 0x8C not64 BRANCH_HINT() BRDISPz()*/ {882}, +/*h(2)=2 0x0F 0x8C mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {883} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x8D not64 BRANCH_HINT() BRDISPz()*/ {886}, +/*h(1)=1 0x0F 0x8D not64 BRANCH_HINT() BRDISPz()*/ {886}, +/*h(2)=2 0x0F 0x8D mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {887} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x8E not64 BRANCH_HINT() BRDISPz()*/ {890}, +/*h(1)=1 0x0F 0x8E not64 BRANCH_HINT() BRDISPz()*/ {890}, +/*h(2)=2 0x0F 0x8E mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {891} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x8f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x0F 0x8F not64 BRANCH_HINT() BRDISPz()*/ {894}, +/*h(1)=1 0x0F 0x8F not64 BRANCH_HINT() BRDISPz()*/ {894}, +/*h(2)=2 0x0F 0x8F mode64 FORCE64() BRANCH_HINT() BRDISP32()*/ {895} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x90_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x90 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1272}, +/*h(1)=1 0x0F 0x90 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1273} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x91_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x91 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1274}, +/*h(1)=1 0x0F 0x91 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1275} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x92_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x92 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1276}, +/*h(1)=1 0x0F 0x92 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1277} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x93_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x93 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1278}, +/*h(1)=1 0x0F 0x93 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1279} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x94_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x94 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1280}, +/*h(1)=1 0x0F 0x94 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x95_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x95 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1282}, +/*h(1)=1 0x0F 0x95 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1283} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x96_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x96 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1284}, +/*h(1)=1 0x0F 0x96 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1285} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x97_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x97 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1286}, +/*h(1)=1 0x0F 0x97 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1287} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x98_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x98 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1599}, +/*h(1)=1 0x0F 0x98 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x99_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x99 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1601}, +/*h(1)=1 0x0F 0x99 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1602} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x9A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1603}, +/*h(1)=1 0x0F 0x9A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1604} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x9B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1605}, +/*h(1)=1 0x0F 0x9B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1606} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x9C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1607}, +/*h(1)=1 0x0F 0x9C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1608} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x9D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1609}, +/*h(1)=1 0x0F 0x9D MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1610} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x9E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1611}, +/*h(1)=1 0x0F 0x9E MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1612} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0x9f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0x9F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1613}, +/*h(1)=1 0x0F 0x9F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1614} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa0_vv0(const xed_decoded_inst_t* d) +{ +return 542; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa1_vv0(const xed_decoded_inst_t* d) +{ +return 361; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa2_vv0(const xed_decoded_inst_t* d) +{ +return 1288; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xA3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {564}, +/*h(1)=1 0x0F 0xA3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {565} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xA4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1620}, +/*h(1)=1 0x0F 0xA4 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1621} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xA5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1622}, +/*h(1)=1 0x0F 0xA5 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1623} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[11] = { +/*empty slot1 */ {0,0}, +/*h(429)=1 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix*/ {429, 1952}, +/*h(413)=2 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix*/ {413, 1951}, +/*h(397)=3 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode16*/ {397, 1953}, +/*h(431)=4 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix*/ {431, 1952}, +/*h(415)=5 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix*/ {415, 1951}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(430)=8 0x0F 0xA6 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix*/ {430, 1952}, +/*h(414)=9 0x0F 0xA6 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix*/ {414, 1951}, +/*h(398)=10 0x0F 0xA6 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix eamode32*/ {398, 1954} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD_REG_REP_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 11ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[7] = { +/*h(99)=0 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] f3_refining_prefix*/ {99, 1945}, +/*h(115)=1 0x0F 0xA7 MOD[0b11] REG[0b100] RM[0b000] f3_refining_prefix*/ {115, 1949}, +/*h(111)=2 0x0F 0xA7 MOD[0b11] REG[0b011] RM[0b000] f3_refining_prefix*/ {111, 1948}, +/*h(103)=3 0x0F 0xA7 MOD[0b11] REG[0b001] RM[0b000] f3_refining_prefix*/ {103, 1946}, +/*h(119)=4 0x0F 0xA7 MOD[0b11] REG[0b101] RM[0b000] f3_refining_prefix*/ {119, 1950}, +/*h(3)=5 0x0F 0xA7 MOD[0b11] REG[0b000] RM[0b000] not_refining*/ {3, 1944}, +/*h(107)=6 0x0F 0xA7 MOD[0b11] REG[0b010] RM[0b000] f3_refining_prefix*/ {107, 1947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD_REG_REP_RM(d); +hidx = ((9*key % 11) % 7); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa8_vv0(const xed_decoded_inst_t* d) +{ +return 543; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xa9_vv0(const xed_decoded_inst_t* d) +{ +return 362; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xaa_vv0(const xed_decoded_inst_t* d) +{ +return 1615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xab_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {570}, +/*h(1)=1 0x0F 0xAB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {567}, +/*h(2)=2 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {571}, +/*h(3)=3 0x0F 0xAB MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {571} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xac_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xAC MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1616}, +/*h(1)=1 0x0F 0xAC MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1617} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xad_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xAD MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1618}, +/*h(1)=1 0x0F 0xAD MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1619} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {0, 666}, +/*h(610)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {610, 2091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {2, 666}, +/*h(612)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {612, 2091}, +/*h(989)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64*/ {989, 2065} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {666} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 4; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1003)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1003, 2117}, +/*h(16)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {16, 667}, +/*h(626)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {626, 755} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(18)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {18, 667}, +/*h(628)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {628, 755}, +/*h(1005)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1005, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {20, 667}, +/*h(397)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix*/ {397, 2100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(512)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {668} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(514)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {668} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(516)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b000] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {668} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 516; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(528)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {528, 669}, +/*h(994)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {994, 2061} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(996)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {996, 2061}, +/*h(619)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix*/ {619, 2116}, +/*h(530)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {530, 669} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(66)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {66, 1912}, +/*h(532)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b001] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {532, 669}, +/*h(909)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix*/ {909, 2100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(32)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()*/ {32, 670}, +/*h(875)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {875, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(544)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()*/ {670} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(34)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()*/ {34, 670}, +/*h(877)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {877, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(546)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()*/ {546, 670}, +/*h(80)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {80, 1913} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(36)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()*/ {36, 670}, +/*h(413)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix*/ {413, 2101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(548)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b010] RM[nnn] no_refining_prefix MODRM()*/ {548, 670}, +/*h(925)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix*/ {925, 2101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(48)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()*/ {671} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 48; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(560)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()*/ {671} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 560; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(50)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()*/ {671} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 50; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(562)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()*/ {671} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(52)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()*/ {52, 671}, +/*h(429)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix*/ {429, 2102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(564)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b011] RM[nnn] no_refining_prefix MODRM()*/ {671} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 564; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(490)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {490, 2061}, +/*h(634)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {634, 2098}, +/*h(113)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix*/ {113, 754}, +/*h(867)=3 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {867, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(625)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix*/ {625, 754}, +/*h(1002)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {1002, 2061}, +/*h(104)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {104, 2150}, +/*h(481)=3 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {481, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(492)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {492, 2061}, +/*h(115)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix*/ {115, 754}, +/*h(869)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {869, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(627)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix*/ {627, 754}, +/*h(106)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {106, 2150}, +/*h(483)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {483, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(960)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()*/ {960, 2111}, +/*h(117)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix*/ {117, 754} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(629)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b111] RM[nnn] no_refining_prefix*/ {754} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 629; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(489)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {489, 2117}, +/*h(112)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {112, 755}, +/*h(578)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {578, 1914} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(624)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {624, 755}, +/*h(1001)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {1001, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(580)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {580, 1914}, +/*h(957)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix*/ {957, 2103}, +/*h(114)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {114, 755} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(116)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {116, 755}, +/*h(493)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {493, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(81)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix*/ {756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 81; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(593)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix*/ {593, 756}, +/*h(449)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix*/ {449, 2110} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(83)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix*/ {756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 83; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(595)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix*/ {756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(85)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix*/ {756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 85; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(597)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] no_refining_prefix*/ {756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(97)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix*/ {757} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 97; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(609)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix*/ {757} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(99)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix*/ {99, 757}, +/*h(997)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {997, 2117}, +/*h(620)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {620, 2150} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(611)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix*/ {757} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(101)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix*/ {757} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(613)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] no_refining_prefix*/ {613, 757}, +/*h(469)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0*/ {469, 2064} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(64)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {1912} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 64; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(68)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {1912} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 68; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(82)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {1913} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 82; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(84)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {1913} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 84; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(576)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {1914} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(592)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {1915} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 592; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(450)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()*/ {450, 2111}, +/*h(594)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {594, 1915}, +/*h(361)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {361, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(452)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()*/ {452, 2111}, +/*h(596)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b101] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {596, 1915}, +/*h(363)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {363, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {2061} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(992)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {2061} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(632)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {632, 2098}, +/*h(488)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {488, 2061}, +/*h(865)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {865, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1000)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {2061} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(482)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {482, 2061}, +/*h(105)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix*/ {105, 2116} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(484)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {484, 2061}, +/*h(107)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix*/ {107, 2116} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1004)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix MODRM()*/ {2061} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(465)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0*/ {2064} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(617)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix*/ {617, 2116}, +/*h(96)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {96, 2090}, +/*h(473)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0*/ {473, 2064} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(933)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix*/ {933, 2102}, +/*h(467)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0*/ {467, 2064} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(475)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0*/ {475, 2064}, +/*h(941)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix*/ {941, 2102}, +/*h(98)=2 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {98, 2090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(100)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix norexw_prefix MODRM()*/ {100, 2090}, +/*h(477)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W0*/ {477, 2064} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(981)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b101] RM[nnn] f3_refining_prefix W1 mode64*/ {2065} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(608)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix rexw_prefix MODRM()*/ {2091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(120)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {120, 2098}, +/*h(353)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {353, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(965)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix*/ {965, 2110}, +/*h(122)=1 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {122, 2098}, +/*h(355)=2 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {355, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((10*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(124)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {124, 2098}, +/*h(357)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {357, 2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(636)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b111] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {2098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(389)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix*/ {2100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(901)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b000] RM[nnn] mode64 f3_refining_prefix*/ {2100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(405)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix*/ {2101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(917)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b001] RM[nnn] mode64 f3_refining_prefix*/ {917, 2101}, +/*h(451)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix*/ {451, 2110} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(421)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b010] RM[nnn] mode64 f3_refining_prefix*/ {2102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(437)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix*/ {2103} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(949)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix*/ {2103} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(445)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b011] RM[nnn] mode64 f3_refining_prefix*/ {2103} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(961)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix*/ {2110} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(963)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix*/ {2110} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(453)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix*/ {2110} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(448)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()*/ {2111} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()*/ {2111} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(964)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b100] RM[nnn] f3_refining_prefix no66_prefix MODRM()*/ {2111} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(109)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix*/ {2116} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 109; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(621)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] osz_refining_prefix*/ {2116} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(616)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {616, 2150}, +/*h(993)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {993, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(618)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {618, 2150}, +/*h(995)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {995, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(491)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(108)=0 0x0F 0xAE MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {108, 2150}, +/*h(485)=1 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix*/ {485, 2117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(873)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(365)=0 0x0F 0xAE MOD[0b11] MOD=3 REG[0b110] RM[nnn] f2_refining_prefix*/ {2118} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xae_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[156] = { +/*h(610)=0 */ {610, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(877)=2 */ {877, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_2_l1}, +/*h(445)=3 */ {445, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_3_l1}, +/*h(68)=4 */ {68, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_4_l1}, +/*h(1000)=5 */ {1000, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(81)=9 */ {81, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_9_l1}, +/*h(636)=10 */ {636, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_10_l1}, +/*h(869)=11 */ {869, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_11_l1}, +/*h(437)=12 */ {437, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_12_l1}, +/*h(992)=13 */ {992, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(560)=15 */ {560, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_15_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(361)=17 */ {361, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_17_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1005)=19 */ {1005, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_19_l1}, +/*h(107)=20 */ {107, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_20_l1}, +/*h(429)=21 */ {429, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(353)=25 */ {353, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_25_l1}, +/*h(963)=26 */ {963, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_26_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(620)=28 */ {620, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(421)=30 */ {421, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_30_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(544)=32 */ {544, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(489)=34 */ {489, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_34_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(612)=36 */ {612, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(413)=38 */ {413, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_38_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(104)=42 */ {104, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(981)=45 */ {981, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_45_l1}, +/*h(83)=46 */ {83, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_46_l1}, +/*h(405)=47 */ {405, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_47_l1}, +/*h(960)=48 */ {960, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(994)=50 */ {994, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_50_l1}, +/*h(617)=51 */ {617, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_51_l1}, +/*h(562)=52 */ {562, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_52_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(363)=54 */ {363, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_54_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(397)=56 */ {397, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_56_l1}, +/*h(109)=57 */ {109, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_57_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(609)=59 */ {609, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_59_l1}, +/*h(465)=60 */ {465, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(355)=62 */ {355, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_62_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(389)=64 */ {389, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_64_l1}, +/*h(101)=65 */ {101, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(512)=67 */ {512, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_67_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(80)=69 */ {80, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_69_l1}, +/*h(491)=70 */ {491, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_70_l1}, +/*h(957)=71 */ {957, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4)=73 */ {4, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_73_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(449)=77 */ {449, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_77_l1}, +/*h(1004)=78 */ {1004, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_78_l1}, +/*h(106)=79 */ {106, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_79_l1}, +/*h(949)=80 */ {949, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_80_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(85)=83 */ {85, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_83_l1}, +/*h(873)=84 */ {873, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_84_l1}, +/*h(962)=85 */ {962, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_85_l1}, +/*h(64)=86 */ {64, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_86_l1}, +/*h(619)=87 */ {619, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_87_l1}, +/*h(941)=88 */ {941, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_88_l1}, +/*h(564)=89 */ {564, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_89_l1}, +/*h(365)=90 */ {365, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_90_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(865)=93 */ {865, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(611)=96 */ {611, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_96_l1}, +/*h(933)=97 */ {933, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_97_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(357)=99 */ {357, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_99_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1001)=101 */ {1001, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_101_l1}, +/*h(480)=102 */ {480, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_102_l1}, +/*h(48)=103 */ {48, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_103_l1}, +/*h(514)=104 */ {514, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_104_l1}, +/*h(82)=105 */ {82, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_105_l1}, +/*h(925)=106 */ {925, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_106_l1}, +/*h(493)=107 */ {493, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(616)=110 */ {616, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(595)=113 */ {595, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_113_l1}, +/*h(451)=114 */ {451, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_114_l1}, +/*h(629)=115 */ {629, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_115_l1}, +/*h(108)=116 */ {108, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(608)=119 */ {608, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(875)=121 */ {875, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_121_l1}, +/*h(964)=122 */ {964, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_122_l1}, +/*h(909)=123 */ {909, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_123_l1}, +/*h(621)=124 */ {621, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_124_l1}, +/*h(100)=125 */ {100, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(867)=130 */ {867, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(901)=132 */ {901, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_132_l1}, +/*h(469)=133 */ {469, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(592)=136 */ {592, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_136_l1}, +/*h(448)=137 */ {448, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_137_l1}, +/*h(1003)=138 */ {1003, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_138_l1}, +/*h(105)=139 */ {105, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_139_l1}, +/*h(50)=140 */ {50, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_140_l1}, +/*h(516)=141 */ {516, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_141_l1}, +/*h(84)=142 */ {84, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(961)=145 */ {961, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(618)=147 */ {618, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_147_l1}, +/*h(97)=148 */ {97, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(597)=150 */ {597, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_150_l1}, +/*h(453)=151 */ {453, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(576)=154 */ {576, xed3_phash_find_maplegacy_map1_opcode0xae_vv0_154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 156ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xaf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xAF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {497}, +/*h(1)=1 0x0F 0xAF MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {498} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {1291}, +/*h(1)=1 0x0F 0xB0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {1289}, +/*h(2)=2 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1292}, +/*h(3)=3 0x0F 0xB0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {1293}, +/*h(1)=1 0x0F 0xB1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {1290}, +/*h(2)=2 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1294}, +/*h(3)=3 0x0F 0xB1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 0x0F 0xB2 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1295} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {576}, +/*h(1)=1 0x0F 0xB3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {573}, +/*h(2)=2 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {577}, +/*h(3)=3 0x0F 0xB3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {577} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 0x0F 0xB4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 0x0F 0xB5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1297} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xB6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1298}, +/*h(1)=1 0x0F 0xB6 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1299} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xB7 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1300}, +/*h(1)=1 0x0F 0xB7 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1301} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6)=0 0x0F 0xB8 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1785}, +/*h(7)=1 0x0F 0xB8 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1786} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP(d); +hidx = key - 6; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xb9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xB9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1388}, +/*h(1)=1 0x0F 0xB9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xba_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(16)=0 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()*/ {562}, +/*h(17)=1 0x0F 0xBA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()*/ {562}, +/*h(18)=2 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {563}, +/*h(19)=3 0x0F 0xBA MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {563}, +/*h(20)=4 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() nolock_prefix*/ {568}, +/*h(21)=5 0x0F 0xBA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8() lock_prefix*/ {566}, +/*h(22)=6 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()*/ {569}, +/*h(23)=7 0x0F 0xBA MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()*/ {569}, +/*h(24)=8 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix*/ {574}, +/*h(25)=9 0x0F 0xBA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix*/ {572}, +/*h(26)=10 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {575}, +/*h(27)=11 0x0F 0xBA MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {575}, +/*h(28)=12 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() nolock_prefix*/ {580}, +/*h(29)=13 0x0F 0xBA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8() lock_prefix*/ {578}, +/*h(30)=14 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()*/ {581}, +/*h(31)=15 0x0F 0xBA MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()*/ {581} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 16; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {582}, +/*h(1)=1 0x0F 0xBB MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {579}, +/*h(2)=2 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {583}, +/*h(3)=3 0x0F 0xBB MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {583} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2123}, +/*h(4)=1 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2123}, +/*h(6)=2 0x0F 0xBC refining_f3 TZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2125}, +/*h(8)=3 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2123}, +/*h(12)=4 0x0F 0xBC not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2123}, +/*h(14)=5 0x0F 0xBC refining_f3 TZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2121}, +/*h(1)=6 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2124}, +/*h(5)=7 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2124}, +/*h(7)=8 0x0F 0xBC refining_f3 TZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2126}, +/*h(9)=9 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2124}, +/*h(13)=10 0x0F 0xBC not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2124}, +/*h(15)=11 0x0F 0xBC refining_f3 TZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP_TZCNT(d); +hidx = ((18*key % 47) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2132}, +/*h(10)=1 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {10, 2133}, +/*h(12)=2 0x0F 0xBD refining_f3 LZCNT=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2134}, +/*h(1)=3 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1, 2132}, +/*h(11)=4 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2133}, +/*h(13)=5 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {13, 2130}, +/*h(2)=6 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2, 2133}, +/*h(8)=7 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2132}, +/*h(14)=8 0x0F 0xBD refining_f3 LZCNT=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {14, 2135}, +/*h(3)=9 0x0F 0xBD not_refining_f3 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2133}, +/*h(9)=10 0x0F 0xBD not_refining_f3 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {9, 2132}, +/*h(15)=11 0x0F 0xBD f3_refining_prefix LZCNT=1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LZCNT_MOD3_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbe_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xBE MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1624}, +/*h(1)=1 0x0F 0xBE MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1625} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xbf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xBF MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1626}, +/*h(1)=1 0x0F 0xBF MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1627} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {1304}, +/*h(1)=1 0x0F 0xC0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {1302}, +/*h(2)=2 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1305}, +/*h(3)=3 0x0F 0xC0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1305} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {1306}, +/*h(1)=1 0x0F 0xC1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {1303}, +/*h(2)=2 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1307}, +/*h(3)=3 0x0F 0xC1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1307} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x0F 0xC2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {0, 1308}, +/*h(10)=1 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {10, 1327}, +/*h(12)=2 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {12, 1321}, +/*h(1)=3 0x0F 0xC2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1, 1309}, +/*h(11)=4 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {11, 1328}, +/*h(13)=5 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {13, 1322}, +/*h(2)=6 0x0F 0xC2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {2, 1323}, +/*h(8)=7 0x0F 0xC2 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {8, 1327}, +/*h(14)=8 0x0F 0xC2 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() UIMM8()*/ {14, 1321}, +/*h(3)=9 0x0F 0xC2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {3, 1324}, +/*h(9)=10 0x0F 0xC2 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {9, 1328}, +/*h(15)=11 0x0F 0xC2 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66() UIMM8()*/ {15, 1322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((3*key % 17) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(0)=0 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {0, 1310}, +/*h(64)=1 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {64, 1310}, +/*h(2)=2 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {2, 1310}, +/*h(66)=3 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {66, 1310}, +/*h(4)=4 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 norexw_prefix MODRM()*/ {4, 1311}, +/*h(68)=5 0x0F 0xC3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 rexw_prefix MODRM()*/ {68, 1312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(d); +hidx = ((8*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xC4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1313}, +/*h(1)=1 0x0F 0xC4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1314}, +/*h(2)=2 0x0F 0xC4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {1315}, +/*h(3)=3 0x0F 0xC4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {1316} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(1)=1 0x0F 0xC5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1, 1317}, +/*h(3)=2 0x0F 0xC5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {3, 1318} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xC6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {1319}, +/*h(1)=1 0x0F 0xC6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1320}, +/*h(2)=2 0x0F 0xC6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM() UIMM8()*/ {1325}, +/*h(3)=3 0x0F 0xC6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() UIMM8()*/ {1326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1572)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {1572, 590}, +/*h(208)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {208, 584} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1232)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {1232, 584}, +/*h(999)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {999, 2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(212)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {212, 584}, +/*h(1576)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {1576, 593} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1236)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {1236, 584}, +/*h(1003)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {1003, 2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {216, 584}, +/*h(970)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {970, 2176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1994)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {1994, 2176}, +/*h(1240)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {1240, 584} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(209)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {209, 584}, +/*h(1573)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1573, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1233)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {584} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1056)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {1056, 590}, +/*h(213)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {213, 584}, +/*h(2043)=2 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {2043, 2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1237)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {584} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1237; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1060)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {1060, 590}, +/*h(217)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {217, 584} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1241)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] osz_refining_prefix REFINING66() MODRM()*/ {584} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(569)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix*/ {569, 589}, +/*h(2022)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2022, 2108}, +/*h(192)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {192, 585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1216)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {1216, 585}, +/*h(229)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {229, 586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(196)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {196, 585}, +/*h(2026)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {2026, 2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1220)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {1220, 585}, +/*h(233)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {233, 586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(200)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1224)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(193)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(230)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {230, 2099}, +/*h(1217)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {1217, 585}, +/*h(984)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {984, 587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_186_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1184)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1184, 2093}, +/*h(197)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {197, 585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(234)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {234, 2099}, +/*h(1221)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {1221, 585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1188)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1188, 2093}, +/*h(201)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {201, 585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1225)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] no_refining_prefix MODRM()*/ {585} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(224)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1248)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {1248, 586}, +/*h(1015)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {1015, 2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(228)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {228, 586}, +/*h(1825)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1825, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1252)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(232)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {232, 586}, +/*h(1219)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1219, 2075}, +/*h(1829)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1829, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1256)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(225)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1249)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1253)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {586} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1253; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1257)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] no_refining_prefix MODRM()*/ {1257, 586}, +/*h(37)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {37, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(960)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1984)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1120)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1120, 2095}, +/*h(976)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {976, 587}, +/*h(133)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {133, 2096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2000)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {2000, 587}, +/*h(1157)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1157, 2097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(964)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1988)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1988; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(980)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {980, 587}, +/*h(137)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {137, 2096}, +/*h(1124)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1124, 2095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2004)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {2004, 587}, +/*h(1161)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1161, 2097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(968)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1992)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1254)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {1254, 2099}, +/*h(2008)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {2008, 587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(961)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(998)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {998, 2108}, +/*h(1985)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {1985, 587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(977)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1014)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {1014, 2108}, +/*h(2001)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {2001, 587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(965)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1002)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {1002, 2109}, +/*h(1989)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {1989, 587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(981)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {981, 587}, +/*h(227)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {227, 2099}, +/*h(1824)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {1824, 590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2005)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {2005, 587}, +/*h(1251)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {1251, 2099}, +/*h(1018)=2 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {1018, 2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(969)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1993)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(985)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {985, 587}, +/*h(231)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {231, 2099}, +/*h(1218)=2 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1218, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2009)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] f3_refining_prefix IGNORE66() MODRM()*/ {2009, 587}, +/*h(1255)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {1255, 2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(33)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 33; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1057)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1057, 588}, +/*h(824)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {824, 591}, +/*h(214)=2 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {214, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(168)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {168, 2092}, +/*h(545)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {545, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1192)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1192, 2093}, +/*h(1569)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1569, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(801)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2023)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2023, 2108}, +/*h(49)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {49, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1073)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1073; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(561)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1585)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(817)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1841)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1061)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(549)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(195)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {195, 2075}, +/*h(805)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {805, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(53)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {53, 588}, +/*h(2027)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {2027, 2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1077)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1077; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(565)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 565; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(136)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {136, 2096}, +/*h(1589)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1589, 588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(821)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {821, 588}, +/*h(211)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {211, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1845)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() lock_prefix*/ {1845, 588}, +/*h(1235)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1235, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(41)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix*/ {589} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 41; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(553)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix*/ {589} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(809)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix*/ {809, 589}, +/*h(199)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {199, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(57)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix*/ {589} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 57; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(825)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() lock_prefix*/ {825, 589}, +/*h(215)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {215, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(32)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {32, 590}, +/*h(1019)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {1019, 2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(544)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1568)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1568; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(800)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(48)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 48; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1072)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(560)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 560; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1584)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(816)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {816, 590}, +/*h(1193)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1193, 2093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1840)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {1840, 590}, +/*h(243)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {243, 2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2010)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {2010, 2176}, +/*h(36)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {36, 590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(548)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(804)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {804, 590}, +/*h(1270)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {1270, 2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1828)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(52)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 52; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1076)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1076; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(564)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 564; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1588)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(210)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {210, 2075}, +/*h(820)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {820, 590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_162_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(247)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {247, 2099}, +/*h(1234)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1234, 2075}, +/*h(1844)=2 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 IMMUNE66() MODRM() nolock_prefix*/ {1844, 590} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(40)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {591} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 40; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(552)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {591} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 552; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(808)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {591} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(56)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {591} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 56; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(568)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 norexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {591} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 568; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1065)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix*/ {592} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1065; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1577)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix*/ {592} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1833)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix*/ {1833, 592}, +/*h(1223)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1223, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1081)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix*/ {592} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1593)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix*/ {592} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1239)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1239, 2075}, +/*h(1849)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() lock_prefix*/ {1849, 592} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1064)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {593} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1832)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {1832, 593}, +/*h(235)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {235, 2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1080)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {593} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1592)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {593} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1592; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1848)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] mode64 rexw_prefix IMMUNE66() MODRM() nolock_prefix*/ {1848, 593}, +/*h(1238)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1238, 2075}, +/*h(251)=2 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {251, 2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(194)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(198)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {198, 2075}, +/*h(1185)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1185, 2093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1222)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(202)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1226)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(218)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1242)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(203)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1227)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {1010, 2108}, +/*h(1243)=1 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not_refining*/ {1243, 2075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(160)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(164)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 164; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(161)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1152)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {1152, 2097}, +/*h(165)=1 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {165, 2092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(169)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1189)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(96)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 96; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(100)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 100; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(104)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(97)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 97; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(101)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 101; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(105)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1128)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1121)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1125)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1129)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(128)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(132)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(129)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() norexw_prefix no_refining_prefix*/ {2096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1156)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1160)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1153)=0 0x0F 0xC7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() rexw_prefix no_refining_prefix*/ {2097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(226)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1250)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1266)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(246)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1258)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(250)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1274)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1267)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1271)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1259)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1275)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not_refining*/ {2099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(994)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2018)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2034)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2038)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(995)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2019)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1011)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2035)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2039)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix not64*/ {2108} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2042)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[nnn] f3_refining_prefix mode64*/ {2109} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {2176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(971)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {2176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1995)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {2176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 1995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(987)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {2176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2011)=0 0x0F 0xC7 MOD[0b11] MOD=3 REG[0b110] RM[nnn] f3_refining_prefix mode64*/ {2176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = key - 2011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc7_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[248] = { +/*h(233)=0 */ {233, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_0_l1}, +/*h(1076)=1 */ {1076, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1254)=3 */ {1254, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1576)=5 */ {1576, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_5_l1}, +/*h(2042)=6 */ {2042, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_6_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1233)=8 */ {1233, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_8_l1}, +/*h(246)=9 */ {246, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_9_l1}, +/*h(568)=10 */ {568, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_10_l1}, +/*h(801)=11 */ {801, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_11_l1}, +/*h(1267)=12 */ {1267, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_12_l1}, +/*h(136)=13 */ {136, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_13_l1}, +/*h(225)=14 */ {225, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1157)=16 */ {1157, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1568)=19 */ {1568, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_19_l1}, +/*h(2034)=20 */ {2034, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1225)=22 */ {1225, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_22_l1}, +/*h(1081)=23 */ {1081, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_23_l1}, +/*h(560)=24 */ {560, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_24_l1}, +/*h(1259)=25 */ {1259, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_25_l1}, +/*h(128)=26 */ {128, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_26_l1}, +/*h(971)=27 */ {971, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_27_l1}, +/*h(1060)=28 */ {1060, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1992)=30 */ {1992, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_30_l1}, +/*h(251)=31 */ {251, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_31_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2026)=33 */ {2026, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_33_l1}, +/*h(52)=34 */ {52, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_34_l1}, +/*h(1128)=35 */ {1128, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_35_l1}, +/*h(230)=36 */ {230, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_36_l1}, +/*h(1073)=37 */ {1073, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_37_l1}, +/*h(552)=38 */ {552, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_38_l1}, +/*h(1018)=39 */ {1018, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1573)=41 */ {1573, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_41_l1}, +/*h(2039)=42 */ {2039, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1984)=44 */ {1984, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_44_l1}, +/*h(243)=45 */ {243, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_45_l1}, +/*h(565)=46 */ {565, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_46_l1}, +/*h(2018)=47 */ {2018, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(133)=49 */ {133, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_49_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1065)=51 */ {1065, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_51_l1}, +/*h(544)=52 */ {544, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_52_l1}, +/*h(1010)=53 */ {1010, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1188)=55 */ {1188, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_55_l1}, +/*h(57)=56 */ {57, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1222)=58 */ {1222, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_58_l1}, +/*h(235)=59 */ {235, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_59_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2010)=61 */ {2010, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_61_l1}, +/*h(1256)=62 */ {1256, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_62_l1}, +/*h(968)=63 */ {968, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_63_l1}, +/*h(214)=64 */ {214, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1002)=66 */ {1002, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_66_l1}, +/*h(1235)=67 */ {1235, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_67_l1}, +/*h(104)=68 */ {104, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_68_l1}, +/*h(193)=69 */ {193, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_69_l1}, +/*h(2023)=70 */ {2023, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_70_l1}, +/*h(1125)=71 */ {1125, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_71_l1}, +/*h(227)=72 */ {227, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_72_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(549)=74 */ {549, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_74_l1}, +/*h(1015)=75 */ {1015, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_75_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(960)=77 */ {960, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_77_l1}, +/*h(1193)=78 */ {1193, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_78_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(994)=80 */ {994, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_80_l1}, +/*h(1227)=81 */ {1227, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_81_l1}, +/*h(96)=82 */ {96, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_82_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(41)=84 */ {41, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_84_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(219)=86 */ {219, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(164)=88 */ {164, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_88_l1}, +/*h(1994)=89 */ {1994, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_89_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1185)=91 */ {1185, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_91_l1}, +/*h(808)=92 */ {808, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_92_l1}, +/*h(1274)=93 */ {1274, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_93_l1}, +/*h(986)=94 */ {986, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_94_l1}, +/*h(1219)=95 */ {1219, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(33)=97 */ {33, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_97_l1}, +/*h(1253)=98 */ {1253, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_98_l1}, +/*h(965)=99 */ {965, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_99_l1}, +/*h(211)=100 */ {211, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(999)=103 */ {999, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_103_l1}, +/*h(101)=104 */ {101, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_104_l1}, +/*h(800)=105 */ {800, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_105_l1}, +/*h(1266)=106 */ {1266, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1588)=108 */ {1588, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_108_l1}, +/*h(224)=109 */ {224, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_109_l1}, +/*h(1156)=110 */ {1156, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_110_l1}, +/*h(169)=111 */ {169, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(203)=114 */ {203, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_114_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1224)=117 */ {1224, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_117_l1}, +/*h(1080)=118 */ {1080, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1258)=120 */ {1258, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(970)=122 */ {970, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(161)=124 */ {161, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_124_l1}, +/*h(1237)=125 */ {1237, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_125_l1}, +/*h(250)=126 */ {250, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(195)=128 */ {195, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_128_l1}, +/*h(1271)=129 */ {1271, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_129_l1}, +/*h(1593)=130 */ {1593, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_130_l1}, +/*h(229)=131 */ {229, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_131_l1}, +/*h(1072)=132 */ {1072, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_132_l1}, +/*h(1161)=133 */ {1161, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_133_l1}, +/*h(1250)=134 */ {1250, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1572)=136 */ {1572, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_136_l1}, +/*h(2038)=137 */ {2038, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(242)=139 */ {242, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(564)=141 */ {564, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(132)=143 */ {132, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_143_l1}, +/*h(1585)=144 */ {1585, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_144_l1}, +/*h(1064)=145 */ {1064, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1153)=147 */ {1153, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_147_l1}, +/*h(1242)=148 */ {1242, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(200)=150 */ {200, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_150_l1}, +/*h(56)=151 */ {56, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=153 */ {234, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_153_l1}, +/*h(1077)=154 */ {1077, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1255)=156 */ {1255, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1577)=158 */ {1577, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_158_l1}, +/*h(2043)=159 */ {2043, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1988)=161 */ {1988, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_161_l1}, +/*h(247)=162 */ {247, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_162_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2022)=164 */ {2022, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_164_l1}, +/*h(48)=165 */ {48, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_165_l1}, +/*h(137)=166 */ {137, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_166_l1}, +/*h(226)=167 */ {226, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(548)=169 */ {548, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_169_l1}, +/*h(1014)=170 */ {1014, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1192)=172 */ {1192, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_172_l1}, +/*h(2035)=173 */ {2035, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1226)=175 */ {1226, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(561)=177 */ {561, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_177_l1}, +/*h(40)=178 */ {40, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(129)=180 */ {129, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_180_l1}, +/*h(218)=181 */ {218, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_181_l1}, +/*h(1061)=182 */ {1061, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_182_l1}, +/*h(1993)=183 */ {1993, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_183_l1}, +/*h(1239)=184 */ {1239, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1184)=186 */ {1184, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_186_l1}, +/*h(2027)=187 */ {2027, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_187_l1}, +/*h(1129)=188 */ {1129, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_188_l1}, +/*h(231)=189 */ {231, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_189_l1}, +/*h(1828)=190 */ {1828, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_190_l1}, +/*h(553)=191 */ {553, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_191_l1}, +/*h(1019)=192 */ {1019, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_192_l1}, +/*h(1252)=193 */ {1252, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_193_l1}, +/*h(964)=194 */ {964, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_194_l1}, +/*h(210)=195 */ {210, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(998)=197 */ {998, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_197_l1}, +/*h(1841)=198 */ {1841, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_198_l1}, +/*h(100)=199 */ {100, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2019)=201 */ {2019, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_201_l1}, +/*h(1121)=202 */ {1121, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_202_l1}, +/*h(977)=203 */ {977, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(168)=205 */ {168, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_205_l1}, +/*h(1011)=206 */ {1011, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1189)=208 */ {1189, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_208_l1}, +/*h(202)=209 */ {202, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1223)=212 */ {1223, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_212_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2011)=214 */ {2011, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_214_l1}, +/*h(37)=215 */ {37, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_215_l1}, +/*h(969)=216 */ {969, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_216_l1}, +/*h(215)=217 */ {215, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(160)=219 */ {160, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_219_l1}, +/*h(1003)=220 */ {1003, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_220_l1}, +/*h(105)=221 */ {105, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_221_l1}, +/*h(194)=222 */ {194, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_222_l1}, +/*h(1270)=223 */ {1270, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_223_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1592)=225 */ {1592, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_225_l1}, +/*h(1825)=226 */ {1825, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_226_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1160)=228 */ {1160, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_228_l1}, +/*h(1249)=229 */ {1249, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_229_l1}, +/*h(961)=230 */ {961, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_230_l1}, +/*h(817)=231 */ {817, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_231_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(995)=234 */ {995, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_234_l1}, +/*h(97)=235 */ {97, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1584)=239 */ {1584, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_239_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1152)=241 */ {1152, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_241_l1}, +/*h(1995)=242 */ {1995, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_242_l1}, +/*h(1241)=243 */ {1241, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_243_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(199)=245 */ {199, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_245_l1}, +/*h(1275)=246 */ {1275, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_246_l1}, +/*h(987)=247 */ {987, xed3_phash_find_maplegacy_map1_opcode0xc7_vv0_247_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 248ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc8_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xc9_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xca_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcb_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcc_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcd_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xce_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xcf_vv0(const xed_decoded_inst_t* d) +{ +return 1628; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1342}, +/*h(2)=2 0x0F 0xD0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1339}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1343}, +/*empty slot1 */ {0,0}, +/*h(11)=7 0x0F 0xD0 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1343}, +/*h(3)=8 0x0F 0xD0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1340}, +/*h(8)=9 0x0F 0xD0 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1342} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {618}, +/*h(1)=1 0x0F 0xD1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {619}, +/*h(2)=2 0x0F 0xD1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {620}, +/*h(3)=3 0x0F 0xD1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {621} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {636}, +/*h(1)=1 0x0F 0xD2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {637}, +/*h(2)=2 0x0F 0xD2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {638}, +/*h(3)=3 0x0F 0xD2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {639} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {654}, +/*h(1)=1 0x0F 0xD3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {655}, +/*h(2)=2 0x0F 0xD3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {656}, +/*h(3)=3 0x0F 0xD3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {657} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1329}, +/*h(1)=1 0x0F 0xD4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1330}, +/*h(2)=2 0x0F 0xD4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1331}, +/*h(3)=3 0x0F 0xD4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1332} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1333}, +/*h(1)=1 0x0F 0xD5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1334}, +/*h(2)=2 0x0F 0xD5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1335}, +/*h(3)=3 0x0F 0xD5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1336} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(13)=0 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1341}, +/*empty slot1 */ {0,0}, +/*h(2)=2 0x0F 0xD6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1559}, +/*h(15)=3 0x0F 0xD6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1341}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=6 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1344}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=9 0x0F 0xD6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1344}, +/*h(3)=10 0x0F 0xD6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1560}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(1)=1 0x0F 0xD7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 1337}, +/*h(3)=2 0x0F 0xD7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1338} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1629}, +/*h(1)=1 0x0F 0xD8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1630}, +/*h(2)=2 0x0F 0xD8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1631}, +/*h(3)=3 0x0F 0xD8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1632} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xd9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xD9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1633}, +/*h(1)=1 0x0F 0xD9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1634}, +/*h(2)=2 0x0F 0xD9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1635}, +/*h(3)=3 0x0F 0xD9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1636} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xda_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xDA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1637}, +/*h(1)=1 0x0F 0xDA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1638}, +/*h(2)=2 0x0F 0xDA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1639}, +/*h(3)=3 0x0F 0xDA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1640} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xDB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1641}, +/*h(1)=1 0x0F 0xDB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1642}, +/*h(2)=2 0x0F 0xDB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1643}, +/*h(3)=3 0x0F 0xDB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1644} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xDC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1645}, +/*h(1)=1 0x0F 0xDC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1646}, +/*h(2)=2 0x0F 0xDC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1647}, +/*h(3)=3 0x0F 0xDC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1648} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xDD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1649}, +/*h(1)=1 0x0F 0xDD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1650}, +/*h(2)=2 0x0F 0xDD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1651}, +/*h(3)=3 0x0F 0xDD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1652} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xde_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xDE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1653}, +/*h(1)=1 0x0F 0xDE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1654}, +/*h(2)=2 0x0F 0xDE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1655}, +/*h(3)=3 0x0F 0xDE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1656} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xdf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xDF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1657}, +/*h(1)=1 0x0F 0xDF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1658}, +/*h(2)=2 0x0F 0xDF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1659}, +/*h(3)=3 0x0F 0xDF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1660} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE0 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1345}, +/*h(1)=1 0x0F 0xE0 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1346}, +/*h(2)=2 0x0F 0xE0 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1347}, +/*h(3)=3 0x0F 0xE0 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1348} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {624}, +/*h(1)=1 0x0F 0xE1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {625}, +/*h(2)=2 0x0F 0xE1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {626}, +/*h(3)=3 0x0F 0xE1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {627} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {642}, +/*h(1)=1 0x0F 0xE2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {643}, +/*h(2)=2 0x0F 0xE2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {644}, +/*h(3)=3 0x0F 0xE2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {645} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1349}, +/*h(1)=1 0x0F 0xE3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1350}, +/*h(2)=2 0x0F 0xE3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1351}, +/*h(3)=3 0x0F 0xE3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1352} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1353}, +/*h(1)=1 0x0F 0xE4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1354}, +/*h(2)=2 0x0F 0xE4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1355}, +/*h(3)=3 0x0F 0xE4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1357}, +/*h(1)=1 0x0F 0xE5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1358}, +/*h(2)=2 0x0F 0xE5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1359}, +/*h(3)=3 0x0F 0xE5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(13)=0 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {13, 1366}, +/*empty slot1 */ {0,0}, +/*h(10)=2 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {10, 1367}, +/*h(2)=3 0x0F 0xE6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1362}, +/*h(15)=4 0x0F 0xE6 f3_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {15, 1366}, +/*empty slot1 */ {0,0}, +/*h(12)=6 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {12, 1365}, +/*empty slot1 */ {0,0}, +/*h(9)=8 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {9, 1368}, +/*h(14)=9 0x0F 0xE6 f3_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {14, 1365}, +/*empty slot1 */ {0,0}, +/*h(11)=11 0x0F 0xE6 f2_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] IGNORE66()*/ {11, 1368}, +/*h(3)=12 0x0F 0xE6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {3, 1363}, +/*empty slot1 */ {0,0}, +/*h(8)=14 0x0F 0xE6 f2_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM()*/ {8, 1367} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0F 0xE7 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 1361}, +/*h(2)=1 0x0F 0xE7 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {2, 1364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1661}, +/*h(1)=1 0x0F 0xE8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1662}, +/*h(2)=2 0x0F 0xE8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1663}, +/*h(3)=3 0x0F 0xE8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1664} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xe9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xE9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1665}, +/*h(1)=1 0x0F 0xE9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1666}, +/*h(2)=2 0x0F 0xE9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1667}, +/*h(3)=3 0x0F 0xE9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1668} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xea_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xEA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1669}, +/*h(1)=1 0x0F 0xEA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1670}, +/*h(2)=2 0x0F 0xEA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1671}, +/*h(3)=3 0x0F 0xEA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1672} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xeb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xEB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1673}, +/*h(1)=1 0x0F 0xEB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1674}, +/*h(2)=2 0x0F 0xEB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1675}, +/*h(3)=3 0x0F 0xEB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1676} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xec_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xEC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1677}, +/*h(1)=1 0x0F 0xEC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1678}, +/*h(2)=2 0x0F 0xEC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1679}, +/*h(3)=3 0x0F 0xEC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1680} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xed_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xED no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1681}, +/*h(1)=1 0x0F 0xED no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1682}, +/*h(2)=2 0x0F 0xED osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1683}, +/*h(3)=3 0x0F 0xED osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1684} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xee_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xEE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1685}, +/*h(1)=1 0x0F 0xEE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1686}, +/*h(2)=2 0x0F 0xEE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1687}, +/*h(3)=3 0x0F 0xEE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1688} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xef_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xEF no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1689}, +/*h(1)=1 0x0F 0xEF no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1690}, +/*h(2)=2 0x0F 0xEF osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1691}, +/*h(3)=3 0x0F 0xEF osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1692} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4)=0 0x0F 0xF0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] IGNORE66() MODRM() f2_refining_prefix*/ {1383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REP(d); +hidx = key - 4; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF1 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {630}, +/*h(1)=1 0x0F 0xF1 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {631}, +/*h(2)=2 0x0F 0xF1 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {632}, +/*h(3)=3 0x0F 0xF1 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {633} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF2 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {648}, +/*h(1)=1 0x0F 0xF2 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {649}, +/*h(2)=2 0x0F 0xF2 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {650}, +/*h(3)=3 0x0F 0xF2 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {651} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF3 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {660}, +/*h(1)=1 0x0F 0xF3 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {661}, +/*h(2)=2 0x0F 0xF3 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {662}, +/*h(3)=3 0x0F 0xF3 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {663} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF4 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1369}, +/*h(1)=1 0x0F 0xF4 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1370}, +/*h(2)=2 0x0F 0xF4 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1371}, +/*h(3)=3 0x0F 0xF4 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1372} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF5 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1373}, +/*h(1)=1 0x0F 0xF5 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1374}, +/*h(2)=2 0x0F 0xF5 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1375}, +/*h(3)=3 0x0F 0xF5 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1376} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF6 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1377}, +/*h(1)=1 0x0F 0xF6 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1378}, +/*h(2)=2 0x0F 0xF6 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1379}, +/*h(3)=3 0x0F 0xF6 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(1)=1 0x0F 0xF7 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] OVERRIDE_SEG0()*/ {1, 1381}, +/*h(3)=2 0x0F 0xF7 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66() OVERRIDE_SEG0()*/ {3, 1382} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF8 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1693}, +/*h(1)=1 0x0F 0xF8 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1694}, +/*h(2)=2 0x0F 0xF8 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1695}, +/*h(3)=3 0x0F 0xF8 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1696} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xf9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xF9 no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1697}, +/*h(1)=1 0x0F 0xF9 no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1698}, +/*h(2)=2 0x0F 0xF9 osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1699}, +/*h(3)=3 0x0F 0xF9 osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xFA no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1701}, +/*h(1)=1 0x0F 0xFA no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1702}, +/*h(2)=2 0x0F 0xFA osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1703}, +/*h(3)=3 0x0F 0xFA osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1704} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xFB no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1705}, +/*h(1)=1 0x0F 0xFB no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1706}, +/*h(2)=2 0x0F 0xFB osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1707}, +/*h(3)=3 0x0F 0xFB osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1708} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xFC no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1709}, +/*h(1)=1 0x0F 0xFC no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1710}, +/*h(2)=2 0x0F 0xFC osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1711}, +/*h(3)=3 0x0F 0xFC osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1712} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xFD no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1713}, +/*h(1)=1 0x0F 0xFD no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1714}, +/*h(2)=2 0x0F 0xFD osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1715}, +/*h(3)=3 0x0F 0xFD osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1716} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xfe_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x0F 0xFE no_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1717}, +/*h(1)=1 0x0F 0xFE no_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1718}, +/*h(2)=2 0x0F 0xFE osz_refining_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] REFINING66() MODRM()*/ {1719}, +/*h(3)=3 0x0F 0xFE osz_refining_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] REFINING66()*/ {1720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_OSZ_REP(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map1_opcode0xff_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1386}, +/*h(1)=1 0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1386}, +/*h(2)=2 0x0F 0xFF MODE_SHORT_UD0=0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {1386}, +/*h(3)=3 0x0F 0xFF MODE_SHORT_UD0=0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1387}, +/*h(4)=4 0x0F 0xFF MODE_SHORT_UD0=1*/ {1385}, +/*h(5)=5 0x0F 0xFF MODE_SHORT_UD0=1*/ {1385}, +/*h(6)=6 0x0F 0xFF MODE_SHORT_UD0=1*/ {1385}, +/*h(7)=7 0x0F 0xFF MODE_SHORT_UD0=1*/ {1385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD_MODE_SHORT_UD0(d); +hidx = key - 0; +if(hidx <= 7) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {183}, +/*h(1)=1 0x00 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {173}, +/*h(2)=2 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {184}, +/*h(3)=3 0x00 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {185}, +/*h(1)=1 0x01 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {174}, +/*h(2)=2 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {186}, +/*h(3)=3 0x01 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x02 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {187}, +/*h(1)=1 0x02 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x03 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {189}, +/*h(1)=1 0x03 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4_vv0(const xed_decoded_inst_t* d) +{ +return 191; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5_vv0(const xed_decoded_inst_t* d) +{ +return 192; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x06 not64*/ {535}, +/*h(1)=1 0x06 not64*/ {535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x07 not64*/ {357}, +/*h(1)=1 0x07 not64*/ {357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {207}, +/*h(1)=1 0x08 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {197}, +/*h(2)=2 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {208}, +/*h(3)=3 0x08 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {208} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {209}, +/*h(1)=1 0x09 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {198}, +/*h(2)=2 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {210}, +/*h(3)=3 0x09 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {210} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {211}, +/*h(1)=1 0x0A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {212} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {213}, +/*h(1)=1 0x0B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {214} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc_vv0(const xed_decoded_inst_t* d) +{ +return 215; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd_vv0(const xed_decoded_inst_t* d) +{ +return 216; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x0E not64*/ {536}, +/*h(1)=1 0x0E not64*/ {536} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x10_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {231}, +/*h(1)=1 0x10 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {221}, +/*h(2)=2 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {232}, +/*h(3)=3 0x10 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {232} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x11_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {233}, +/*h(1)=1 0x11 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {222}, +/*h(2)=2 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {234}, +/*h(3)=3 0x11 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {234} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x12_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x12 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {235}, +/*h(1)=1 0x12 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x13_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x13 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {237}, +/*h(1)=1 0x13 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x14_vv0(const xed_decoded_inst_t* d) +{ +return 239; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x15_vv0(const xed_decoded_inst_t* d) +{ +return 240; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x16_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x16 not64*/ {537}, +/*h(1)=1 0x16 not64*/ {537} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x17_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x17 not64*/ {358}, +/*h(1)=1 0x17 not64*/ {358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x18_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {255}, +/*h(1)=1 0x18 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {245}, +/*h(2)=2 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {256}, +/*h(3)=3 0x18 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {256} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x19_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {257}, +/*h(1)=1 0x19 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {246}, +/*h(2)=2 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {258}, +/*h(3)=3 0x19 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {258} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x1A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {260}, +/*h(1)=1 0x1A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x1B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {262}, +/*h(1)=1 0x1B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {261} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1c_vv0(const xed_decoded_inst_t* d) +{ +return 263; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1d_vv0(const xed_decoded_inst_t* d) +{ +return 264; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x1E not64*/ {538}, +/*h(1)=1 0x1E not64*/ {538} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x1f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x1F not64*/ {359}, +/*h(1)=1 0x1F not64*/ {359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x20_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {279}, +/*h(1)=1 0x20 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {269}, +/*h(2)=2 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {280}, +/*h(3)=3 0x20 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x21_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {281}, +/*h(1)=1 0x21 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {270}, +/*h(2)=2 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {282}, +/*h(3)=3 0x21 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x22_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x22 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {284}, +/*h(1)=1 0x22 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {283} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x23_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x23 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {286}, +/*h(1)=1 0x23 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {285} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x24_vv0(const xed_decoded_inst_t* d) +{ +return 287; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x25_vv0(const xed_decoded_inst_t* d) +{ +return 288; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x27_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x27 not64*/ {764}, +/*h(1)=1 0x27 not64*/ {764} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x28_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {303}, +/*h(1)=1 0x28 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {293}, +/*h(2)=2 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {304}, +/*h(3)=3 0x28 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {304} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x29_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {305}, +/*h(1)=1 0x29 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {294}, +/*h(2)=2 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {306}, +/*h(3)=3 0x29 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {306} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x2A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {308}, +/*h(1)=1 0x2A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {307} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x2B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {310}, +/*h(1)=1 0x2B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2c_vv0(const xed_decoded_inst_t* d) +{ +return 311; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2d_vv0(const xed_decoded_inst_t* d) +{ +return 312; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x2f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x2F not64*/ {765}, +/*h(1)=1 0x2F not64*/ {765} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x30_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {327}, +/*h(1)=1 0x30 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {317}, +/*h(2)=2 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {328}, +/*h(3)=3 0x30 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x31_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {329}, +/*h(1)=1 0x31 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {318}, +/*h(2)=2 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {330}, +/*h(3)=3 0x31 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {330} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x32_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x32 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {332}, +/*h(1)=1 0x32 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {331} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x33_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x33 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {334}, +/*h(1)=1 0x33 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {333} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x34_vv0(const xed_decoded_inst_t* d) +{ +return 335; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x35_vv0(const xed_decoded_inst_t* d) +{ +return 336; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x37_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x37 not64*/ {766}, +/*h(1)=1 0x37 not64*/ {766} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x38_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {345}, +/*h(1)=1 0x38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {346} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x39_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x39 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {347}, +/*h(1)=1 0x39 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {348} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {349}, +/*h(1)=1 0x3A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {350} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x3B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {351}, +/*h(1)=1 0x3B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {352} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3c_vv0(const xed_decoded_inst_t* d) +{ +return 353; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3d_vv0(const xed_decoded_inst_t* d) +{ +return 354; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x3f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x3F not64*/ {767}, +/*h(1)=1 0x3F not64*/ {767} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x40_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x41_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x42_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x43_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x44_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x45_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x46_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x47_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_0 SRM[rrr] not64*/ {513}, +/*h(1)=1 0b0100_0 SRM[rrr] not64*/ {513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x48_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x49_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x4f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0b0100_1 SRM[rrr] not64*/ {520}, +/*h(1)=1 0b0100_1 SRM[rrr] not64*/ {520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x50_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x51_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x52_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x53_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x54_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x55_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x56_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x57_vv0(const xed_decoded_inst_t* d) +{ +return 539; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x58_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x59_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5a_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5b_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5c_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5d_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5e_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x5f_vv0(const xed_decoded_inst_t* d) +{ +return 360; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x60_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x60 mode16 no66_prefix*/ {0, 768}, +/*h(4)=1 0x60 mode16 66_prefix*/ {4, 770}, +/*h(1)=2 0x60 mode32 no66_prefix*/ {1, 771}, +/*h(5)=3 0x60 mode32 66_prefix*/ {5, 769} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ(d); +hidx = ((9*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x61_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x61 mode16 no66_prefix*/ {0, 772}, +/*h(4)=1 0x61 mode16 66_prefix*/ {4, 774}, +/*h(1)=2 0x61 mode32 no66_prefix*/ {1, 775}, +/*h(5)=3 0x61 mode32 66_prefix*/ {5, 773} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ(d); +hidx = ((9*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x62_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x62 mode16 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 776}, +/*h(8)=1 0x62 mode16 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 778}, +/*h(2)=2 0x62 mode32 no66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 779}, +/*h(10)=3 0x62 mode32 66_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 777} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ(d); +hidx = ((8*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x63_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(0)=0 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {780}, +/*h(1)=1 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {781}, +/*h(2)=2 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {780}, +/*h(3)=3 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64*/ {781}, +/*h(4)=4 0x63 MOD[mm] MOD!=3 REG[rrr] RM[nnn] mode64 MODRM()*/ {782}, +/*h(5)=5 0x63 MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64*/ {783} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE(d); +hidx = key - 0; +if(hidx <= 5) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x68_vv0(const xed_decoded_inst_t* d) +{ +return 540; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x69_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x69 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMMz()*/ {493}, +/*h(1)=1 0x69 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMMz()*/ {494} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6a_vv0(const xed_decoded_inst_t* d) +{ +return 541; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x6B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SIMM8()*/ {495}, +/*h(1)=1 0x6B MOD[0b11] MOD=3 REG[rrr] RM[nnn] SIMM8()*/ {496} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0x6C norep*/ {0, 786}, +/*h(2)=1 0x6C repne*/ {2, 785}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0x6C repe*/ {3, 784} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0x6D mode16 no66_prefix norep*/ {0, 793}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0x6D mode32 no66_prefix norep*/ {1, 805}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0x6D mode16 no66_prefix repe*/ {24, 787}, +/*h(2)=6 0x6D mode64 norexw_prefix no66_prefix norep*/ {2, 806}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0x6D mode32 no66_prefix repe*/ {25, 797}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0x6D mode16 no66_prefix repne*/ {48, 790}, +/*h(26)=11 0x6D mode64 norexw_prefix no66_prefix repe*/ {26, 798}, +/*h(4)=12 0x6D mode16 66_prefix norep*/ {4, 804}, +/*h(49)=13 0x6D mode32 no66_prefix repne*/ {49, 801}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0x6D mode32 66_prefix norep*/ {5, 794}, +/*h(50)=16 0x6D mode64 rexw_prefix repne*/ {50, 803}, +/*h(28)=17 0x6D mode16 66_prefix repe*/ {28, 796}, +/*h(6)=18 0x6D mode64 norexw_prefix 66_prefix norep*/ {6, 795}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0x6D mode32 66_prefix repe*/ {29, 788}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0x6D mode16 66_prefix repne*/ {52, 800}, +/*h(30)=23 0x6D mode64 norexw_prefix 66_prefix repe*/ {30, 789}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0x6D mode32 66_prefix repne*/ {53, 791}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0x6D mode64 rexw_prefix repne*/ {54, 803}, +/*h(32)=29 0x6D mode16 no66_prefix norep*/ {32, 793}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0x6D mode32 no66_prefix norep*/ {33, 805}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0x6D mode16 no66_prefix repe*/ {56, 787}, +/*h(34)=35 0x6D mode64 rexw_prefix norep*/ {34, 807}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0x6D mode32 no66_prefix repe*/ {57, 797}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0x6D mode64 rexw_prefix repe*/ {58, 799}, +/*h(36)=41 0x6D mode16 66_prefix norep*/ {36, 804}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0x6D mode32 66_prefix norep*/ {37, 794}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0x6D mode16 66_prefix repe*/ {60, 796}, +/*h(38)=47 0x6D mode64 rexw_prefix norep*/ {38, 807}, +/*h(16)=48 0x6D mode16 no66_prefix repne*/ {16, 790}, +/*h(61)=49 0x6D mode32 66_prefix repe*/ {61, 788}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0x6D mode32 no66_prefix repne*/ {17, 801}, +/*h(62)=52 0x6D mode64 rexw_prefix repe*/ {62, 799}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0x6D mode64 norexw_prefix no66_prefix repne*/ {18, 802}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0x6D mode16 66_prefix repne*/ {20, 800}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0x6D mode32 66_prefix repne*/ {21, 791}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0x6D mode64 norexw_prefix 66_prefix repne*/ {22, 792} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0x6E norep OVERRIDE_SEG0()*/ {0, 810}, +/*h(2)=1 0x6E repne OVERRIDE_SEG0()*/ {2, 809}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0x6E repe OVERRIDE_SEG0()*/ {3, 808} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x6f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0x6F mode16 no66_prefix norep OVERRIDE_SEG0()*/ {0, 817}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0x6F mode32 no66_prefix norep OVERRIDE_SEG0()*/ {1, 829}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0x6F mode16 no66_prefix repe OVERRIDE_SEG0()*/ {24, 811}, +/*h(2)=6 0x6F mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0()*/ {2, 830}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0x6F mode32 no66_prefix repe OVERRIDE_SEG0()*/ {25, 821}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0x6F mode16 no66_prefix repne OVERRIDE_SEG0()*/ {48, 814}, +/*h(26)=11 0x6F mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0()*/ {26, 822}, +/*h(4)=12 0x6F mode16 66_prefix norep OVERRIDE_SEG0()*/ {4, 828}, +/*h(49)=13 0x6F mode32 no66_prefix repne OVERRIDE_SEG0()*/ {49, 825}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0x6F mode32 66_prefix norep OVERRIDE_SEG0()*/ {5, 818}, +/*h(50)=16 0x6F mode64 rexw_prefix repne OVERRIDE_SEG0()*/ {50, 827}, +/*h(28)=17 0x6F mode16 66_prefix repe OVERRIDE_SEG0()*/ {28, 820}, +/*h(6)=18 0x6F mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0()*/ {6, 819}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0x6F mode32 66_prefix repe OVERRIDE_SEG0()*/ {29, 812}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0x6F mode16 66_prefix repne OVERRIDE_SEG0()*/ {52, 824}, +/*h(30)=23 0x6F mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0()*/ {30, 813}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0x6F mode32 66_prefix repne OVERRIDE_SEG0()*/ {53, 815}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0x6F mode64 rexw_prefix repne OVERRIDE_SEG0()*/ {54, 827}, +/*h(32)=29 0x6F mode16 no66_prefix norep OVERRIDE_SEG0()*/ {32, 817}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0x6F mode32 no66_prefix norep OVERRIDE_SEG0()*/ {33, 829}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0x6F mode16 no66_prefix repe OVERRIDE_SEG0()*/ {56, 811}, +/*h(34)=35 0x6F mode64 rexw_prefix norep OVERRIDE_SEG0()*/ {34, 831}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0x6F mode32 no66_prefix repe OVERRIDE_SEG0()*/ {57, 821}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0x6F mode64 rexw_prefix repe OVERRIDE_SEG0()*/ {58, 823}, +/*h(36)=41 0x6F mode16 66_prefix norep OVERRIDE_SEG0()*/ {36, 828}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0x6F mode32 66_prefix norep OVERRIDE_SEG0()*/ {37, 818}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0x6F mode16 66_prefix repe OVERRIDE_SEG0()*/ {60, 820}, +/*h(38)=47 0x6F mode64 rexw_prefix norep OVERRIDE_SEG0()*/ {38, 831}, +/*h(16)=48 0x6F mode16 no66_prefix repne OVERRIDE_SEG0()*/ {16, 814}, +/*h(61)=49 0x6F mode32 66_prefix repe OVERRIDE_SEG0()*/ {61, 812}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0x6F mode32 no66_prefix repne OVERRIDE_SEG0()*/ {17, 825}, +/*h(62)=52 0x6F mode64 rexw_prefix repe OVERRIDE_SEG0()*/ {62, 823}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0x6F mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0()*/ {18, 826}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0x6F mode16 66_prefix repne OVERRIDE_SEG0()*/ {20, 824}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0x6F mode32 66_prefix repne OVERRIDE_SEG0()*/ {21, 815}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0x6F mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0()*/ {22, 816} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x70_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x70 not64 BRANCH_HINT() BRDISP8()*/ {833}, +/*h(1)=1 0x70 not64 BRANCH_HINT() BRDISP8()*/ {833}, +/*h(2)=2 0x70 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {832} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x71_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x71 not64 BRANCH_HINT() BRDISP8()*/ {837}, +/*h(1)=1 0x71 not64 BRANCH_HINT() BRDISP8()*/ {837}, +/*h(2)=2 0x71 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {836} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x72_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x72 not64 BRANCH_HINT() BRDISP8()*/ {841}, +/*h(1)=1 0x72 not64 BRANCH_HINT() BRDISP8()*/ {841}, +/*h(2)=2 0x72 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {840} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x73_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x73 not64 BRANCH_HINT() BRDISP8()*/ {845}, +/*h(1)=1 0x73 not64 BRANCH_HINT() BRDISP8()*/ {845}, +/*h(2)=2 0x73 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {844} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x74_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x74 not64 BRANCH_HINT() BRDISP8()*/ {849}, +/*h(1)=1 0x74 not64 BRANCH_HINT() BRDISP8()*/ {849}, +/*h(2)=2 0x74 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {848} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x75_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x75 not64 BRANCH_HINT() BRDISP8()*/ {853}, +/*h(1)=1 0x75 not64 BRANCH_HINT() BRDISP8()*/ {853}, +/*h(2)=2 0x75 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {852} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x76_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x76 not64 BRANCH_HINT() BRDISP8()*/ {857}, +/*h(1)=1 0x76 not64 BRANCH_HINT() BRDISP8()*/ {857}, +/*h(2)=2 0x76 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {856} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x77_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x77 not64 BRANCH_HINT() BRDISP8()*/ {861}, +/*h(1)=1 0x77 not64 BRANCH_HINT() BRDISP8()*/ {861}, +/*h(2)=2 0x77 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {860} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x78_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x78 not64 BRANCH_HINT() BRDISP8()*/ {865}, +/*h(1)=1 0x78 not64 BRANCH_HINT() BRDISP8()*/ {865}, +/*h(2)=2 0x78 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {864} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x79_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x79 not64 BRANCH_HINT() BRDISP8()*/ {869}, +/*h(1)=1 0x79 not64 BRANCH_HINT() BRDISP8()*/ {869}, +/*h(2)=2 0x79 mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {868} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x7A not64 BRANCH_HINT() BRDISP8()*/ {873}, +/*h(1)=1 0x7A not64 BRANCH_HINT() BRDISP8()*/ {873}, +/*h(2)=2 0x7A mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {872} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x7B not64 BRANCH_HINT() BRDISP8()*/ {877}, +/*h(1)=1 0x7B not64 BRANCH_HINT() BRDISP8()*/ {877}, +/*h(2)=2 0x7B mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {876} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x7C not64 BRANCH_HINT() BRDISP8()*/ {881}, +/*h(1)=1 0x7C not64 BRANCH_HINT() BRDISP8()*/ {881}, +/*h(2)=2 0x7C mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {880} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x7D not64 BRANCH_HINT() BRDISP8()*/ {885}, +/*h(1)=1 0x7D not64 BRANCH_HINT() BRDISP8()*/ {885}, +/*h(2)=2 0x7D mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {884} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x7E not64 BRANCH_HINT() BRDISP8()*/ {889}, +/*h(1)=1 0x7E not64 BRANCH_HINT() BRDISP8()*/ {889}, +/*h(2)=2 0x7E mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {888} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x7f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0x7F not64 BRANCH_HINT() BRDISP8()*/ {893}, +/*h(1)=1 0x7F not64 BRANCH_HINT() BRDISP8()*/ {893}, +/*h(2)=2 0x7F mode64 FORCE64() BRANCH_HINT() BRDISP8()*/ {892} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x80_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(0)=0 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {175}, +/*h(1)=1 0x80 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix*/ {169}, +/*h(2)=2 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()*/ {176}, +/*h(3)=3 0x80 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()*/ {176}, +/*h(4)=4 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {199}, +/*h(5)=5 0x80 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix*/ {193}, +/*h(6)=6 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()*/ {200}, +/*h(7)=7 0x80 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()*/ {200}, +/*h(8)=8 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {223}, +/*h(9)=9 0x80 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix*/ {217}, +/*h(10)=10 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()*/ {224}, +/*h(11)=11 0x80 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()*/ {224}, +/*h(12)=12 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {247}, +/*h(13)=13 0x80 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix*/ {241}, +/*h(14)=14 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()*/ {248}, +/*h(15)=15 0x80 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()*/ {248}, +/*h(16)=16 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() nolock_prefix*/ {271}, +/*h(17)=17 0x80 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8() lock_prefix*/ {265}, +/*h(18)=18 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {272}, +/*h(19)=19 0x80 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {272}, +/*h(20)=20 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {295}, +/*h(21)=21 0x80 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix*/ {289}, +/*h(22)=22 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()*/ {296}, +/*h(23)=23 0x80 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()*/ {296}, +/*h(24)=24 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() nolock_prefix*/ {319}, +/*h(25)=25 0x80 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8() lock_prefix*/ {313}, +/*h(26)=26 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {320}, +/*h(27)=27 0x80 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {320}, +/*h(28)=28 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()*/ {337}, +/*h(29)=29 0x80 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()*/ {337}, +/*h(30)=30 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()*/ {338}, +/*h(31)=31 0x80 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()*/ {338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 31) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x81_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(0)=0 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {177}, +/*h(1)=1 0x81 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz() lock_prefix*/ {170}, +/*h(2)=2 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {178}, +/*h(3)=3 0x81 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {178}, +/*h(4)=4 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {201}, +/*h(5)=5 0x81 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz() lock_prefix*/ {194}, +/*h(6)=6 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()*/ {202}, +/*h(7)=7 0x81 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()*/ {202}, +/*h(8)=8 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {225}, +/*h(9)=9 0x81 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMMz() lock_prefix*/ {218}, +/*h(10)=10 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz()*/ {226}, +/*h(11)=11 0x81 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMMz()*/ {226}, +/*h(12)=12 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {249}, +/*h(13)=13 0x81 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMMz() lock_prefix*/ {242}, +/*h(14)=14 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz()*/ {250}, +/*h(15)=15 0x81 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMMz()*/ {250}, +/*h(16)=16 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {273}, +/*h(17)=17 0x81 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMMz() lock_prefix*/ {266}, +/*h(18)=18 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz()*/ {274}, +/*h(19)=19 0x81 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMMz()*/ {274}, +/*h(20)=20 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {297}, +/*h(21)=21 0x81 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMMz() lock_prefix*/ {290}, +/*h(22)=22 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz()*/ {298}, +/*h(23)=23 0x81 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMMz()*/ {298}, +/*h(24)=24 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() nolock_prefix*/ {321}, +/*h(25)=25 0x81 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMMz() lock_prefix*/ {314}, +/*h(26)=26 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz()*/ {322}, +/*h(27)=27 0x81 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMMz()*/ {322}, +/*h(28)=28 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz()*/ {339}, +/*h(29)=29 0x81 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMMz()*/ {339}, +/*h(30)=30 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz()*/ {340}, +/*h(31)=31 0x81 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMMz()*/ {340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 31) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x82_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[116] = { +/*h(0)=0 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {0, 179}, +/*h(34)=1 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8()*/ {34, 228}, +/*empty slot1 */ {0,0}, +/*h(68)=3 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix*/ {68, 275}, +/*h(102)=4 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8()*/ {102, 324}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(81)=7 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {81, 291}, +/*h(115)=8 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8()*/ {115, 342}, +/*empty slot1 */ {0,0}, +/*h(5)=10 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {5, 171}, +/*h(39)=11 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8()*/ {39, 228}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(18)=14 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8()*/ {18, 204}, +/*h(52)=15 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {52, 251}, +/*empty slot1 */ {0,0}, +/*h(86)=17 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8()*/ {86, 300}, +/*empty slot1 */ {0,0}, +/*h(65)=19 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix*/ {65, 267}, +/*empty slot1 */ {0,0}, +/*h(99)=21 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8()*/ {99, 324}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(23)=24 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8()*/ {23, 204}, +/*h(112)=25 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8()*/ {112, 341}, +/*empty slot1 */ {0,0}, +/*h(2)=27 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8()*/ {2, 180}, +/*h(36)=28 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {36, 227}, +/*empty slot1 */ {0,0}, +/*h(70)=30 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8()*/ {70, 276}, +/*empty slot1 */ {0,0}, +/*h(49)=32 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {49, 243}, +/*empty slot1 */ {0,0}, +/*h(83)=34 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8()*/ {83, 300}, +/*h(117)=35 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8()*/ {117, 341}, +/*empty slot1 */ {0,0}, +/*h(7)=37 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8()*/ {7, 180}, +/*h(96)=38 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix*/ {96, 323}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=41 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {20, 203}, +/*empty slot1 */ {0,0}, +/*h(54)=43 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8()*/ {54, 252}, +/*empty slot1 */ {0,0}, +/*h(33)=45 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {33, 219}, +/*empty slot1 */ {0,0}, +/*h(67)=47 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8()*/ {67, 276}, +/*h(101)=48 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix*/ {101, 315}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(80)=51 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {80, 299}, +/*h(114)=52 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8()*/ {114, 342}, +/*empty slot1 */ {0,0}, +/*h(4)=54 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {4, 179}, +/*empty slot1 */ {0,0}, +/*h(38)=56 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8()*/ {38, 228}, +/*empty slot1 */ {0,0}, +/*h(17)=58 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {17, 195}, +/*empty slot1 */ {0,0}, +/*h(51)=60 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8()*/ {51, 252}, +/*h(85)=61 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {85, 291}, +/*empty slot1 */ {0,0}, +/*h(119)=63 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8()*/ {119, 342}, +/*h(64)=64 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() nolock_prefix*/ {64, 275}, +/*h(98)=65 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8()*/ {98, 324}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=69 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8()*/ {22, 204}, +/*empty slot1 */ {0,0}, +/*h(1)=71 0x82 MOD[mm] MOD!=3 REG[0b000] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {1, 171}, +/*empty slot1 */ {0,0}, +/*h(35)=73 0x82 MOD[0b11] MOD=3 REG[0b010] RM[nnn] not64 SIMM8()*/ {35, 228}, +/*h(69)=74 0x82 MOD[mm] MOD!=3 REG[0b100] RM[nnn] not64 MODRM() UIMM8() lock_prefix*/ {69, 267}, +/*empty slot1 */ {0,0}, +/*h(103)=76 0x82 MOD[0b11] MOD=3 REG[0b110] RM[nnn] not64 UIMM8()*/ {103, 324}, +/*h(48)=77 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {48, 251}, +/*h(82)=78 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8()*/ {82, 300}, +/*empty slot1 */ {0,0}, +/*h(116)=80 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8()*/ {116, 341}, +/*empty slot1 */ {0,0}, +/*h(6)=82 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8()*/ {6, 180}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(19)=86 0x82 MOD[0b11] MOD=3 REG[0b001] RM[nnn] not64 SIMM8()*/ {19, 204}, +/*h(53)=87 0x82 MOD[mm] MOD!=3 REG[0b011] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {53, 243}, +/*empty slot1 */ {0,0}, +/*h(87)=89 0x82 MOD[0b11] MOD=3 REG[0b101] RM[nnn] not64 SIMM8()*/ {87, 300}, +/*h(32)=90 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {32, 227}, +/*h(66)=91 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8()*/ {66, 276}, +/*empty slot1 */ {0,0}, +/*h(100)=93 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() nolock_prefix*/ {100, 323}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(113)=97 0x82 MOD[mm] MOD!=3 REG[0b111] RM[nnn] not64 MODRM() SIMM8()*/ {113, 341}, +/*empty slot1 */ {0,0}, +/*h(3)=99 0x82 MOD[0b11] MOD=3 REG[0b000] RM[nnn] not64 SIMM8()*/ {3, 180}, +/*h(37)=100 0x82 MOD[mm] MOD!=3 REG[0b010] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {37, 219}, +/*empty slot1 */ {0,0}, +/*h(71)=102 0x82 MOD[0b11] MOD=3 REG[0b100] RM[nnn] not64 UIMM8()*/ {71, 276}, +/*h(16)=103 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {16, 203}, +/*h(50)=104 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8()*/ {50, 252}, +/*empty slot1 */ {0,0}, +/*h(84)=106 0x82 MOD[mm] MOD!=3 REG[0b101] RM[nnn] not64 MODRM() SIMM8() nolock_prefix*/ {84, 299}, +/*h(118)=107 0x82 MOD[0b11] MOD=3 REG[0b111] RM[nnn] not64 SIMM8()*/ {118, 342}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(97)=110 0x82 MOD[mm] MOD!=3 REG[0b110] RM[nnn] not64 MODRM() UIMM8() lock_prefix*/ {97, 315}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=113 0x82 MOD[mm] MOD!=3 REG[0b001] RM[nnn] not64 MODRM() SIMM8() lock_prefix*/ {21, 195}, +/*empty slot1 */ {0,0}, +/*h(55)=115 0x82 MOD[0b11] MOD=3 REG[0b011] RM[nnn] not64 SIMM8()*/ {55, 252} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_MODE_REG(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 116ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x83_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(0)=0 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {181}, +/*h(1)=1 0x83 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8() lock_prefix*/ {172}, +/*h(2)=2 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()*/ {182}, +/*h(3)=3 0x83 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()*/ {182}, +/*h(4)=4 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {205}, +/*h(5)=5 0x83 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8() lock_prefix*/ {196}, +/*h(6)=6 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()*/ {206}, +/*h(7)=7 0x83 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()*/ {206}, +/*h(8)=8 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {229}, +/*h(9)=9 0x83 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() SIMM8() lock_prefix*/ {220}, +/*h(10)=10 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()*/ {230}, +/*h(11)=11 0x83 MOD[0b11] MOD=3 REG[0b010] RM[nnn] SIMM8()*/ {230}, +/*h(12)=12 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {253}, +/*h(13)=13 0x83 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() SIMM8() lock_prefix*/ {244}, +/*h(14)=14 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()*/ {254}, +/*h(15)=15 0x83 MOD[0b11] MOD=3 REG[0b011] RM[nnn] SIMM8()*/ {254}, +/*h(16)=16 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {277}, +/*h(17)=17 0x83 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() SIMM8() lock_prefix*/ {268}, +/*h(18)=18 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8()*/ {278}, +/*h(19)=19 0x83 MOD[0b11] MOD=3 REG[0b100] RM[nnn] SIMM8()*/ {278}, +/*h(20)=20 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {301}, +/*h(21)=21 0x83 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() SIMM8() lock_prefix*/ {292}, +/*h(22)=22 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()*/ {302}, +/*h(23)=23 0x83 MOD[0b11] MOD=3 REG[0b101] RM[nnn] SIMM8()*/ {302}, +/*h(24)=24 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() nolock_prefix*/ {325}, +/*h(25)=25 0x83 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() SIMM8() lock_prefix*/ {316}, +/*h(26)=26 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8()*/ {326}, +/*h(27)=27 0x83 MOD[0b11] MOD=3 REG[0b110] RM[nnn] SIMM8()*/ {326}, +/*h(28)=28 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()*/ {343}, +/*h(29)=29 0x83 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() SIMM8()*/ {343}, +/*h(30)=30 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()*/ {344}, +/*h(31)=31 0x83 MOD[0b11] MOD=3 REG[0b111] RM[nnn] SIMM8()*/ {344} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 31) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x84_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x84 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {467}, +/*h(1)=1 0x84 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {468} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x85_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x85 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {469}, +/*h(1)=1 0x85 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {470} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x86_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {897}, +/*h(1)=1 0x86 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {896}, +/*h(2)=2 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {898}, +/*h(3)=3 0x86 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {898} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x87_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() nolock_prefix*/ {900}, +/*h(1)=1 0x87 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() lock_prefix*/ {899}, +/*h(2)=2 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {901}, +/*h(3)=3 0x87 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {901} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x88_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x88 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {599}, +/*h(1)=1 0x88 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x89_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x89 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {600}, +/*h(1)=1 0x89 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {601} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x8A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {602}, +/*h(1)=1 0x8A MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {603} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8b_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x8B MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {604}, +/*h(1)=1 0x8B MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {605} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x8C MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {606}, +/*h(1)=1 0x8C MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {607} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 0x8D MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() REMOVE_SEGMENT()*/ {904} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8e_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x8E MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {608}, +/*h(1)=1 0x8E MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {609} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x8f_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x8F MOD[mm] MOD!=3 REG[0b000] RM[nnn] DF64() MODRM()*/ {355}, +/*h(1)=1 0x8F MOD[0b11] MOD=3 REG[0b000] RM[nnn] DF64()*/ {356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x90_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[131] = { +/*h(0)=0 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix*/ {0, 694}, +/*h(44)=1 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*h(88)=2 0b1001_0 SRM[rrr] SRM!=0*/ {88, 902}, +/*h(1)=3 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix*/ {1, 694}, +/*h(45)=4 0b1001_0 SRM[rrr] SRM!=0*/ {45, 902}, +/*h(89)=5 0b1001_0 SRM[rrr] SRM!=0*/ {89, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=7 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(47)=10 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(4)=12 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix*/ {4, 694}, +/*h(48)=13 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*h(92)=14 0b1001_0 SRM[rrr] SRM!=0*/ {92, 902}, +/*h(5)=15 0b1001_0 SRM[0b000] SRM=0 not_refining_f3 norexb_prefix*/ {5, 694}, +/*h(49)=16 0b1001_0 SRM[rrr] SRM!=0*/ {49, 902}, +/*h(93)=17 0b1001_0 SRM[rrr] SRM!=0*/ {93, 902}, +/*h(6)=18 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0*/ {6, 695}, +/*empty slot1 */ {0,0}, +/*h(94)=20 0b1001_0 SRM[rrr] SRM!=0*/ {94, 902}, +/*h(7)=21 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1*/ {7, 905}, +/*empty slot1 */ {0,0}, +/*h(95)=23 0b1001_0 SRM[rrr] SRM!=0*/ {95, 902}, +/*h(8)=24 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {8, 903}, +/*h(52)=25 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*h(96)=26 0b1001_0 SRM[rrr] SRM!=0*/ {96, 902}, +/*h(9)=27 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {9, 903}, +/*h(53)=28 0b1001_0 SRM[rrr] SRM!=0*/ {53, 902}, +/*h(97)=29 0b1001_0 SRM[rrr] SRM!=0*/ {97, 902}, +/*empty slot1 */ {0,0}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=34 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902}, +/*empty slot1 */ {0,0}, +/*h(12)=36 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {12, 903}, +/*h(56)=37 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*h(100)=38 0b1001_0 SRM[rrr] SRM!=0*/ {100, 902}, +/*h(13)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {13, 903}, +/*h(57)=40 0b1001_0 SRM[rrr] SRM!=0*/ {57, 902}, +/*h(101)=41 0b1001_0 SRM[rrr] SRM!=0*/ {101, 902}, +/*h(14)=42 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=0*/ {14, 695}, +/*empty slot1 */ {0,0}, +/*h(102)=44 0b1001_0 SRM[rrr] SRM!=0*/ {102, 902}, +/*h(15)=45 0b1001_0 SRM[0b000] SRM=0 refining_f3 P4=1*/ {15, 905}, +/*empty slot1 */ {0,0}, +/*h(103)=47 0b1001_0 SRM[rrr] SRM!=0*/ {103, 902}, +/*h(16)=48 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(60)=49 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*h(104)=50 0b1001_0 SRM[rrr] SRM!=0*/ {104, 902}, +/*h(17)=51 0b1001_0 SRM[rrr] SRM!=0*/ {17, 902}, +/*h(61)=52 0b1001_0 SRM[rrr] SRM!=0*/ {61, 902}, +/*h(105)=53 0b1001_0 SRM[rrr] SRM!=0*/ {105, 902}, +/*empty slot1 */ {0,0}, +/*h(62)=55 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=58 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(64)=61 0b1001_0 SRM[rrr] SRM!=0*/ {64, 902}, +/*h(108)=62 0b1001_0 SRM[rrr] SRM!=0*/ {108, 902}, +/*h(21)=63 0b1001_0 SRM[rrr] SRM!=0*/ {21, 902}, +/*h(65)=64 0b1001_0 SRM[rrr] SRM!=0*/ {65, 902}, +/*h(109)=65 0b1001_0 SRM[rrr] SRM!=0*/ {109, 902}, +/*h(22)=66 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*empty slot1 */ {0,0}, +/*h(110)=68 0b1001_0 SRM[rrr] SRM!=0*/ {110, 902}, +/*h(23)=69 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(111)=71 0b1001_0 SRM[rrr] SRM!=0*/ {111, 902}, +/*h(24)=72 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*h(68)=73 0b1001_0 SRM[rrr] SRM!=0*/ {68, 902}, +/*h(112)=74 0b1001_0 SRM[rrr] SRM!=0*/ {112, 902}, +/*h(25)=75 0b1001_0 SRM[rrr] SRM!=0*/ {25, 902}, +/*h(69)=76 0b1001_0 SRM[rrr] SRM!=0*/ {69, 902}, +/*h(113)=77 0b1001_0 SRM[rrr] SRM!=0*/ {113, 902}, +/*empty slot1 */ {0,0}, +/*h(70)=79 0b1001_0 SRM[rrr] SRM!=0*/ {70, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(71)=82 0b1001_0 SRM[rrr] SRM!=0*/ {71, 902}, +/*empty slot1 */ {0,0}, +/*h(28)=84 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(72)=85 0b1001_0 SRM[rrr] SRM!=0*/ {72, 902}, +/*h(116)=86 0b1001_0 SRM[rrr] SRM!=0*/ {116, 902}, +/*h(29)=87 0b1001_0 SRM[rrr] SRM!=0*/ {29, 902}, +/*h(73)=88 0b1001_0 SRM[rrr] SRM!=0*/ {73, 902}, +/*h(117)=89 0b1001_0 SRM[rrr] SRM!=0*/ {117, 902}, +/*h(30)=90 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*h(118)=92 0b1001_0 SRM[rrr] SRM!=0*/ {118, 902}, +/*h(31)=93 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(119)=95 0b1001_0 SRM[rrr] SRM!=0*/ {119, 902}, +/*h(32)=96 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*h(76)=97 0b1001_0 SRM[rrr] SRM!=0*/ {76, 902}, +/*h(120)=98 0b1001_0 SRM[rrr] SRM!=0*/ {120, 902}, +/*h(33)=99 0b1001_0 SRM[rrr] SRM!=0*/ {33, 902}, +/*h(77)=100 0b1001_0 SRM[rrr] SRM!=0*/ {77, 902}, +/*h(121)=101 0b1001_0 SRM[rrr] SRM!=0*/ {121, 902}, +/*empty slot1 */ {0,0}, +/*h(78)=103 0b1001_0 SRM[rrr] SRM!=0*/ {78, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(79)=106 0b1001_0 SRM[rrr] SRM!=0*/ {79, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=108 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*h(80)=109 0b1001_0 SRM[rrr] SRM!=0*/ {80, 902}, +/*h(124)=110 0b1001_0 SRM[rrr] SRM!=0*/ {124, 902}, +/*h(37)=111 0b1001_0 SRM[rrr] SRM!=0*/ {37, 902}, +/*h(81)=112 0b1001_0 SRM[rrr] SRM!=0*/ {81, 902}, +/*h(125)=113 0b1001_0 SRM[rrr] SRM!=0*/ {125, 902}, +/*h(38)=114 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*h(126)=116 0b1001_0 SRM[rrr] SRM!=0*/ {126, 902}, +/*h(39)=117 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(127)=119 0b1001_0 SRM[rrr] SRM!=0*/ {127, 902}, +/*h(40)=120 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*h(84)=121 0b1001_0 SRM[rrr] SRM!=0*/ {84, 902}, +/*empty slot1 */ {0,0}, +/*h(41)=123 0b1001_0 SRM[rrr] SRM!=0*/ {41, 902}, +/*h(85)=124 0b1001_0 SRM[rrr] SRM!=0*/ {85, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=127 0b1001_0 SRM[rrr] SRM!=0*/ {86, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(87)=130 0b1001_0 SRM[rrr] SRM!=0*/ {87, 902} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_P4_REP_REXB_SRM(d); +hidx = (3*key % 131); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x91_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x92_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x93_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x94_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x95_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x96_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x97_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*empty slot1 */ {0,0}, +/*h(34)=1 0b1001_0 SRM[rrr] SRM!=0*/ {34, 902}, +/*empty slot1 */ {0,0}, +/*h(47)=3 0b1001_0 SRM[rrr] SRM!=0*/ {47, 902}, +/*empty slot1 */ {0,0}, +/*h(26)=5 0b1001_0 SRM[rrr] SRM!=0*/ {26, 902}, +/*h(60)=6 0b1001_0 SRM[rrr] SRM!=0*/ {60, 902}, +/*empty slot1 */ {0,0}, +/*h(39)=8 0b1001_0 SRM[rrr] SRM!=0*/ {39, 902}, +/*empty slot1 */ {0,0}, +/*h(18)=10 0b1001_0 SRM[rrr] SRM!=0*/ {18, 902}, +/*h(52)=11 0b1001_0 SRM[rrr] SRM!=0*/ {52, 902}, +/*empty slot1 */ {0,0}, +/*h(31)=13 0b1001_0 SRM[rrr] SRM!=0*/ {31, 902}, +/*empty slot1 */ {0,0}, +/*h(10)=15 0b1001_0 SRM[rrr] SRM!=0*/ {10, 902}, +/*h(44)=16 0b1001_0 SRM[rrr] SRM!=0*/ {44, 902}, +/*empty slot1 */ {0,0}, +/*h(23)=18 0b1001_0 SRM[rrr] SRM!=0*/ {23, 902}, +/*empty slot1 */ {0,0}, +/*h(36)=20 0b1001_0 SRM[rrr] SRM!=0*/ {36, 902}, +/*empty slot1 */ {0,0}, +/*h(15)=22 0b1001_0 SRM[rrr] SRM!=0*/ {15, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=25 0b1001_0 SRM[rrr] SRM!=0*/ {28, 902}, +/*h(62)=26 0b1001_0 SRM[rrr] SRM!=0*/ {62, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=30 0b1001_0 SRM[rrr] SRM!=0*/ {20, 902}, +/*h(54)=31 0b1001_0 SRM[rrr] SRM!=0*/ {54, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=34 0b1001_0 SRM[rrr] SRM!=0*/ {12, 902}, +/*empty slot1 */ {0,0}, +/*h(46)=36 0b1001_0 SRM[rrr] SRM!=0*/ {46, 902}, +/*empty slot1 */ {0,0}, +/*h(59)=38 0b1001_0 SRM[rrr] SRM!=0*/ {59, 902}, +/*h(4)=39 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {4, 903}, +/*h(38)=40 0b1001_0 SRM[rrr] SRM!=0*/ {38, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=43 0b1001_0 SRM[rrr] SRM!=0*/ {51, 902}, +/*empty slot1 */ {0,0}, +/*h(30)=45 0b1001_0 SRM[rrr] SRM!=0*/ {30, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=48 0b1001_0 SRM[rrr] SRM!=0*/ {43, 902}, +/*empty slot1 */ {0,0}, +/*h(22)=50 0b1001_0 SRM[rrr] SRM!=0*/ {22, 902}, +/*h(56)=51 0b1001_0 SRM[rrr] SRM!=0*/ {56, 902}, +/*empty slot1 */ {0,0}, +/*h(35)=53 0b1001_0 SRM[rrr] SRM!=0*/ {35, 902}, +/*h(14)=54 0b1001_0 SRM[rrr] SRM!=0*/ {14, 902}, +/*h(48)=55 0b1001_0 SRM[rrr] SRM!=0*/ {48, 902}, +/*empty slot1 */ {0,0}, +/*h(27)=57 0b1001_0 SRM[rrr] SRM!=0*/ {27, 902}, +/*empty slot1 */ {0,0}, +/*h(6)=59 0b1001_0 SRM[rrr] SRM=0 not_refining_f3 rexb_prefix*/ {6, 903}, +/*h(40)=60 0b1001_0 SRM[rrr] SRM!=0*/ {40, 902}, +/*empty slot1 */ {0,0}, +/*h(19)=62 0b1001_0 SRM[rrr] SRM!=0*/ {19, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=65 0b1001_0 SRM[rrr] SRM!=0*/ {32, 902}, +/*empty slot1 */ {0,0}, +/*h(11)=67 0b1001_0 SRM[rrr] SRM!=0*/ {11, 902}, +/*empty slot1 */ {0,0}, +/*h(24)=69 0b1001_0 SRM[rrr] SRM!=0*/ {24, 902}, +/*empty slot1 */ {0,0}, +/*h(58)=71 0b1001_0 SRM[rrr] SRM!=0*/ {58, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=74 0b1001_0 SRM[rrr] SRM!=0*/ {16, 902}, +/*h(50)=75 0b1001_0 SRM[rrr] SRM!=0*/ {50, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=78 0b1001_0 SRM[rrr] SRM!=0*/ {63, 902}, +/*h(8)=79 0b1001_0 SRM[rrr] SRM!=0*/ {8, 902}, +/*h(42)=80 0b1001_0 SRM[rrr] SRM!=0*/ {42, 902}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(55)=83 0b1001_0 SRM[rrr] SRM!=0*/ {55, 902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP_REXB_SRM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x98_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x98 mode16 no66_prefix*/ {0, 906}, +/*h(14)=1 0x98 mode64 rexw_prefix*/ {14, 909}, +/*h(9)=2 0x98 mode32 no66_prefix*/ {9, 911}, +/*h(4)=3 0x98 mode16 66_prefix*/ {4, 910}, +/*h(2)=4 0x98 mode64 norexw_prefix no66_prefix*/ {2, 912}, +/*h(13)=5 0x98 mode32 66_prefix*/ {13, 907}, +/*h(8)=6 0x98 mode16 no66_prefix*/ {8, 906}, +/*h(6)=7 0x98 mode64 norexw_prefix 66_prefix*/ {6, 908}, +/*h(1)=8 0x98 mode32 no66_prefix*/ {1, 911}, +/*h(12)=9 0x98 mode16 66_prefix*/ {12, 910}, +/*h(10)=10 0x98 mode64 rexw_prefix*/ {10, 909}, +/*h(5)=11 0x98 mode32 66_prefix*/ {5, 907} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REXW(d); +hidx = ((8*key % 29) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x99_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x99 mode16 no66_prefix*/ {0, 913}, +/*h(14)=1 0x99 mode64 rexw_prefix*/ {14, 916}, +/*h(9)=2 0x99 mode32 no66_prefix*/ {9, 918}, +/*h(4)=3 0x99 mode16 66_prefix*/ {4, 917}, +/*h(2)=4 0x99 mode64 norexw_prefix no66_prefix*/ {2, 919}, +/*h(13)=5 0x99 mode32 66_prefix*/ {13, 914}, +/*h(8)=6 0x99 mode16 no66_prefix*/ {8, 913}, +/*h(6)=7 0x99 mode64 norexw_prefix 66_prefix*/ {6, 915}, +/*h(1)=8 0x99 mode32 no66_prefix*/ {1, 918}, +/*h(12)=9 0x99 mode16 66_prefix*/ {12, 917}, +/*h(10)=10 0x99 mode64 rexw_prefix*/ {10, 916}, +/*h(5)=11 0x99 mode32 66_prefix*/ {5, 914} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REXW(d); +hidx = ((8*key % 29) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9a_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0x9A not64 BRDISPz() UIMM16()*/ {921}, +/*h(1)=1 0x9A not64 BRDISPz() UIMM16()*/ {921} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9b_vv0(const xed_decoded_inst_t* d) +{ +return 922; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9c_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x9C mode16 no66_prefix*/ {0, 923}, +/*h(14)=1 0x9C mode64 rexw_prefix DF64()*/ {14, 929}, +/*h(9)=2 0x9C mode32 no66_prefix*/ {9, 926}, +/*h(4)=3 0x9C mode16 66_prefix*/ {4, 927}, +/*h(2)=4 0x9C mode64 norexw_prefix no66_prefix DF64()*/ {2, 928}, +/*h(13)=5 0x9C mode32 66_prefix*/ {13, 924}, +/*h(8)=6 0x9C mode16 no66_prefix*/ {8, 923}, +/*h(6)=7 0x9C mode64 norexw_prefix 66_prefix*/ {6, 925}, +/*h(1)=8 0x9C mode32 no66_prefix*/ {1, 926}, +/*h(12)=9 0x9C mode16 66_prefix*/ {12, 927}, +/*h(10)=10 0x9C mode64 rexw_prefix DF64()*/ {10, 929}, +/*h(5)=11 0x9C mode32 66_prefix*/ {5, 924} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REXW(d); +hidx = ((8*key % 29) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9d_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0x9D mode16 no66_prefix*/ {0, 930}, +/*h(14)=1 0x9D mode64 rexw_prefix DF64()*/ {14, 936}, +/*h(9)=2 0x9D mode32 no66_prefix*/ {9, 934}, +/*h(4)=3 0x9D mode16 66_prefix*/ {4, 933}, +/*h(2)=4 0x9D mode64 norexw_prefix no66_prefix DF64()*/ {2, 935}, +/*h(13)=5 0x9D mode32 66_prefix*/ {13, 931}, +/*h(8)=6 0x9D mode16 no66_prefix*/ {8, 930}, +/*h(6)=7 0x9D mode64 norexw_prefix 66_prefix*/ {6, 932}, +/*h(1)=8 0x9D mode32 no66_prefix*/ {1, 934}, +/*h(12)=9 0x9D mode16 66_prefix*/ {12, 933}, +/*h(10)=10 0x9D mode64 rexw_prefix DF64()*/ {10, 936}, +/*h(5)=11 0x9D mode32 66_prefix*/ {5, 931} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REXW(d); +hidx = ((8*key % 29) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9e_vv0(const xed_decoded_inst_t* d) +{ +return 937; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0x9f_vv0(const xed_decoded_inst_t* d) +{ +return 938; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa0_vv0(const xed_decoded_inst_t* d) +{ +return 610; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa1_vv0(const xed_decoded_inst_t* d) +{ +return 611; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa2_vv0(const xed_decoded_inst_t* d) +{ +return 612; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa3_vv0(const xed_decoded_inst_t* d) +{ +return 613; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0xA4 norep OVERRIDE_SEG1()*/ {0, 941}, +/*h(2)=1 0xA4 repne OVERRIDE_SEG1()*/ {2, 940}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0xA4 repe OVERRIDE_SEG1()*/ {3, 939} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0xA5 mode16 no66_prefix norep OVERRIDE_SEG1()*/ {0, 948}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0xA5 mode32 no66_prefix norep OVERRIDE_SEG1()*/ {1, 958}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0xA5 mode16 no66_prefix repe OVERRIDE_SEG1()*/ {24, 942}, +/*h(2)=6 0xA5 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG1()*/ {2, 959}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0xA5 mode32 no66_prefix repe OVERRIDE_SEG1()*/ {25, 952}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0xA5 mode16 no66_prefix repne OVERRIDE_SEG1()*/ {48, 945}, +/*h(26)=11 0xA5 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG1()*/ {26, 953}, +/*h(4)=12 0xA5 mode16 66_prefix norep OVERRIDE_SEG1()*/ {4, 957}, +/*h(49)=13 0xA5 mode32 no66_prefix repne OVERRIDE_SEG1()*/ {49, 955}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0xA5 mode32 66_prefix norep OVERRIDE_SEG1()*/ {5, 949}, +/*h(50)=16 0xA5 mode64 rexw_prefix repne OVERRIDE_SEG1()*/ {50, 961}, +/*h(28)=17 0xA5 mode16 66_prefix repe OVERRIDE_SEG1()*/ {28, 951}, +/*h(6)=18 0xA5 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG1()*/ {6, 950}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0xA5 mode32 66_prefix repe OVERRIDE_SEG1()*/ {29, 943}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0xA5 mode16 66_prefix repne OVERRIDE_SEG1()*/ {52, 954}, +/*h(30)=23 0xA5 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG1()*/ {30, 944}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0xA5 mode32 66_prefix repne OVERRIDE_SEG1()*/ {53, 946}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0xA5 mode64 rexw_prefix repne OVERRIDE_SEG1()*/ {54, 961}, +/*h(32)=29 0xA5 mode16 no66_prefix norep OVERRIDE_SEG1()*/ {32, 948}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0xA5 mode32 no66_prefix norep OVERRIDE_SEG1()*/ {33, 958}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0xA5 mode16 no66_prefix repe OVERRIDE_SEG1()*/ {56, 942}, +/*h(34)=35 0xA5 mode64 rexw_prefix norep OVERRIDE_SEG1()*/ {34, 962}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0xA5 mode32 no66_prefix repe OVERRIDE_SEG1()*/ {57, 952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0xA5 mode64 rexw_prefix repe OVERRIDE_SEG1()*/ {58, 960}, +/*h(36)=41 0xA5 mode16 66_prefix norep OVERRIDE_SEG1()*/ {36, 957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0xA5 mode32 66_prefix norep OVERRIDE_SEG1()*/ {37, 949}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0xA5 mode16 66_prefix repe OVERRIDE_SEG1()*/ {60, 951}, +/*h(38)=47 0xA5 mode64 rexw_prefix norep OVERRIDE_SEG1()*/ {38, 962}, +/*h(16)=48 0xA5 mode16 no66_prefix repne OVERRIDE_SEG1()*/ {16, 945}, +/*h(61)=49 0xA5 mode32 66_prefix repe OVERRIDE_SEG1()*/ {61, 943}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0xA5 mode32 no66_prefix repne OVERRIDE_SEG1()*/ {17, 955}, +/*h(62)=52 0xA5 mode64 rexw_prefix repe OVERRIDE_SEG1()*/ {62, 960}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0xA5 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG1()*/ {18, 956}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0xA5 mode16 66_prefix repne OVERRIDE_SEG1()*/ {20, 954}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0xA5 mode32 66_prefix repne OVERRIDE_SEG1()*/ {21, 946}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0xA5 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG1()*/ {22, 947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0xA6 norep OVERRIDE_SEG0()*/ {0, 965}, +/*h(2)=1 0xA6 repne OVERRIDE_SEG0()*/ {2, 964}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0xA6 repe OVERRIDE_SEG0()*/ {3, 963} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0xA7 mode16 no66_prefix norep OVERRIDE_SEG0()*/ {0, 972}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0xA7 mode32 no66_prefix norep OVERRIDE_SEG0()*/ {1, 982}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0xA7 mode16 no66_prefix repe OVERRIDE_SEG0()*/ {24, 966}, +/*h(2)=6 0xA7 mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0()*/ {2, 983}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0xA7 mode32 no66_prefix repe OVERRIDE_SEG0()*/ {25, 976}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0xA7 mode16 no66_prefix repne OVERRIDE_SEG0()*/ {48, 969}, +/*h(26)=11 0xA7 mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0()*/ {26, 977}, +/*h(4)=12 0xA7 mode16 66_prefix norep OVERRIDE_SEG0()*/ {4, 981}, +/*h(49)=13 0xA7 mode32 no66_prefix repne OVERRIDE_SEG0()*/ {49, 979}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0xA7 mode32 66_prefix norep OVERRIDE_SEG0()*/ {5, 973}, +/*h(50)=16 0xA7 mode64 rexw_prefix repne OVERRIDE_SEG0()*/ {50, 985}, +/*h(28)=17 0xA7 mode16 66_prefix repe OVERRIDE_SEG0()*/ {28, 975}, +/*h(6)=18 0xA7 mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0()*/ {6, 974}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0xA7 mode32 66_prefix repe OVERRIDE_SEG0()*/ {29, 967}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0xA7 mode16 66_prefix repne OVERRIDE_SEG0()*/ {52, 978}, +/*h(30)=23 0xA7 mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0()*/ {30, 968}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0xA7 mode32 66_prefix repne OVERRIDE_SEG0()*/ {53, 970}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0xA7 mode64 rexw_prefix repne OVERRIDE_SEG0()*/ {54, 985}, +/*h(32)=29 0xA7 mode16 no66_prefix norep OVERRIDE_SEG0()*/ {32, 972}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0xA7 mode32 no66_prefix norep OVERRIDE_SEG0()*/ {33, 982}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0xA7 mode16 no66_prefix repe OVERRIDE_SEG0()*/ {56, 966}, +/*h(34)=35 0xA7 mode64 rexw_prefix norep OVERRIDE_SEG0()*/ {34, 986}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0xA7 mode32 no66_prefix repe OVERRIDE_SEG0()*/ {57, 976}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0xA7 mode64 rexw_prefix repe OVERRIDE_SEG0()*/ {58, 984}, +/*h(36)=41 0xA7 mode16 66_prefix norep OVERRIDE_SEG0()*/ {36, 981}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0xA7 mode32 66_prefix norep OVERRIDE_SEG0()*/ {37, 973}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0xA7 mode16 66_prefix repe OVERRIDE_SEG0()*/ {60, 975}, +/*h(38)=47 0xA7 mode64 rexw_prefix norep OVERRIDE_SEG0()*/ {38, 986}, +/*h(16)=48 0xA7 mode16 no66_prefix repne OVERRIDE_SEG0()*/ {16, 969}, +/*h(61)=49 0xA7 mode32 66_prefix repe OVERRIDE_SEG0()*/ {61, 967}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0xA7 mode32 no66_prefix repne OVERRIDE_SEG0()*/ {17, 979}, +/*h(62)=52 0xA7 mode64 rexw_prefix repe OVERRIDE_SEG0()*/ {62, 984}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0xA7 mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0()*/ {18, 980}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0xA7 mode16 66_prefix repne OVERRIDE_SEG0()*/ {20, 978}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0xA7 mode32 66_prefix repne OVERRIDE_SEG0()*/ {21, 970}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0xA7 mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0()*/ {22, 971} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa8_vv0(const xed_decoded_inst_t* d) +{ +return 471; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xa9_vv0(const xed_decoded_inst_t* d) +{ +return 472; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xaa_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0xAA norep*/ {0, 989}, +/*h(2)=1 0xAA repne*/ {2, 988}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0xAA repe*/ {3, 987} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xab_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0xAB mode16 no66_prefix norep*/ {0, 996}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0xAB mode32 no66_prefix norep*/ {1, 1006}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0xAB mode16 no66_prefix repe*/ {24, 990}, +/*h(2)=6 0xAB mode64 norexw_prefix no66_prefix norep*/ {2, 1007}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0xAB mode32 no66_prefix repe*/ {25, 1000}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0xAB mode16 no66_prefix repne*/ {48, 993}, +/*h(26)=11 0xAB mode64 norexw_prefix no66_prefix repe*/ {26, 1001}, +/*h(4)=12 0xAB mode16 66_prefix norep*/ {4, 1005}, +/*h(49)=13 0xAB mode32 no66_prefix repne*/ {49, 1003}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0xAB mode32 66_prefix norep*/ {5, 997}, +/*h(50)=16 0xAB mode64 rexw_prefix repne*/ {50, 1009}, +/*h(28)=17 0xAB mode16 66_prefix repe*/ {28, 999}, +/*h(6)=18 0xAB mode64 norexw_prefix 66_prefix norep*/ {6, 998}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0xAB mode32 66_prefix repe*/ {29, 991}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0xAB mode16 66_prefix repne*/ {52, 1002}, +/*h(30)=23 0xAB mode64 norexw_prefix 66_prefix repe*/ {30, 992}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0xAB mode32 66_prefix repne*/ {53, 994}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0xAB mode64 rexw_prefix repne*/ {54, 1009}, +/*h(32)=29 0xAB mode16 no66_prefix norep*/ {32, 996}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0xAB mode32 no66_prefix norep*/ {33, 1006}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0xAB mode16 no66_prefix repe*/ {56, 990}, +/*h(34)=35 0xAB mode64 rexw_prefix norep*/ {34, 1010}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0xAB mode32 no66_prefix repe*/ {57, 1000}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0xAB mode64 rexw_prefix repe*/ {58, 1008}, +/*h(36)=41 0xAB mode16 66_prefix norep*/ {36, 1005}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0xAB mode32 66_prefix norep*/ {37, 997}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0xAB mode16 66_prefix repe*/ {60, 999}, +/*h(38)=47 0xAB mode64 rexw_prefix norep*/ {38, 1010}, +/*h(16)=48 0xAB mode16 no66_prefix repne*/ {16, 993}, +/*h(61)=49 0xAB mode32 66_prefix repe*/ {61, 991}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0xAB mode32 no66_prefix repne*/ {17, 1003}, +/*h(62)=52 0xAB mode64 rexw_prefix repe*/ {62, 1008}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0xAB mode64 norexw_prefix no66_prefix repne*/ {18, 1004}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0xAB mode16 66_prefix repne*/ {20, 1002}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0xAB mode32 66_prefix repne*/ {21, 994}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0xAB mode64 norexw_prefix 66_prefix repne*/ {22, 995} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xac_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0xAC norep OVERRIDE_SEG0()*/ {0, 1013}, +/*h(2)=1 0xAC repne OVERRIDE_SEG0()*/ {2, 1012}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0xAC repe OVERRIDE_SEG0()*/ {3, 1011} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xad_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0xAD mode16 no66_prefix norep OVERRIDE_SEG0()*/ {0, 1020}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0xAD mode32 no66_prefix norep OVERRIDE_SEG0()*/ {1, 1030}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0xAD mode16 no66_prefix repe OVERRIDE_SEG0()*/ {24, 1014}, +/*h(2)=6 0xAD mode64 norexw_prefix no66_prefix norep OVERRIDE_SEG0()*/ {2, 1031}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0xAD mode32 no66_prefix repe OVERRIDE_SEG0()*/ {25, 1024}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0xAD mode16 no66_prefix repne OVERRIDE_SEG0()*/ {48, 1017}, +/*h(26)=11 0xAD mode64 norexw_prefix no66_prefix repe OVERRIDE_SEG0()*/ {26, 1025}, +/*h(4)=12 0xAD mode16 66_prefix norep OVERRIDE_SEG0()*/ {4, 1029}, +/*h(49)=13 0xAD mode32 no66_prefix repne OVERRIDE_SEG0()*/ {49, 1027}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0xAD mode32 66_prefix norep OVERRIDE_SEG0()*/ {5, 1021}, +/*h(50)=16 0xAD mode64 rexw_prefix repne OVERRIDE_SEG0()*/ {50, 1033}, +/*h(28)=17 0xAD mode16 66_prefix repe OVERRIDE_SEG0()*/ {28, 1023}, +/*h(6)=18 0xAD mode64 norexw_prefix 66_prefix norep OVERRIDE_SEG0()*/ {6, 1022}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0xAD mode32 66_prefix repe OVERRIDE_SEG0()*/ {29, 1015}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0xAD mode16 66_prefix repne OVERRIDE_SEG0()*/ {52, 1026}, +/*h(30)=23 0xAD mode64 norexw_prefix 66_prefix repe OVERRIDE_SEG0()*/ {30, 1016}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0xAD mode32 66_prefix repne OVERRIDE_SEG0()*/ {53, 1018}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0xAD mode64 rexw_prefix repne OVERRIDE_SEG0()*/ {54, 1033}, +/*h(32)=29 0xAD mode16 no66_prefix norep OVERRIDE_SEG0()*/ {32, 1020}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0xAD mode32 no66_prefix norep OVERRIDE_SEG0()*/ {33, 1030}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0xAD mode16 no66_prefix repe OVERRIDE_SEG0()*/ {56, 1014}, +/*h(34)=35 0xAD mode64 rexw_prefix norep OVERRIDE_SEG0()*/ {34, 1034}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0xAD mode32 no66_prefix repe OVERRIDE_SEG0()*/ {57, 1024}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0xAD mode64 rexw_prefix repe OVERRIDE_SEG0()*/ {58, 1032}, +/*h(36)=41 0xAD mode16 66_prefix norep OVERRIDE_SEG0()*/ {36, 1029}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0xAD mode32 66_prefix norep OVERRIDE_SEG0()*/ {37, 1021}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0xAD mode16 66_prefix repe OVERRIDE_SEG0()*/ {60, 1023}, +/*h(38)=47 0xAD mode64 rexw_prefix norep OVERRIDE_SEG0()*/ {38, 1034}, +/*h(16)=48 0xAD mode16 no66_prefix repne OVERRIDE_SEG0()*/ {16, 1017}, +/*h(61)=49 0xAD mode32 66_prefix repe OVERRIDE_SEG0()*/ {61, 1015}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0xAD mode32 no66_prefix repne OVERRIDE_SEG0()*/ {17, 1027}, +/*h(62)=52 0xAD mode64 rexw_prefix repe OVERRIDE_SEG0()*/ {62, 1032}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0xAD mode64 norexw_prefix no66_prefix repne OVERRIDE_SEG0()*/ {18, 1028}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0xAD mode16 66_prefix repne OVERRIDE_SEG0()*/ {20, 1026}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0xAD mode32 66_prefix repne OVERRIDE_SEG0()*/ {21, 1018}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0xAD mode64 norexw_prefix 66_prefix repne OVERRIDE_SEG0()*/ {22, 1019} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xae_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 0xAE norep*/ {0, 1037}, +/*h(2)=1 0xAE repne*/ {2, 1036}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=4 0xAE repe*/ {3, 1035} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xaf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 0xAF mode16 no66_prefix norep*/ {0, 1044}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=3 0xAF mode32 no66_prefix norep*/ {1, 1054}, +/*empty slot1 */ {0,0}, +/*h(24)=5 0xAF mode16 no66_prefix repe*/ {24, 1038}, +/*h(2)=6 0xAF mode64 norexw_prefix no66_prefix norep*/ {2, 1055}, +/*empty slot1 */ {0,0}, +/*h(25)=8 0xAF mode32 no66_prefix repe*/ {25, 1048}, +/*empty slot1 */ {0,0}, +/*h(48)=10 0xAF mode16 no66_prefix repne*/ {48, 1041}, +/*h(26)=11 0xAF mode64 norexw_prefix no66_prefix repe*/ {26, 1049}, +/*h(4)=12 0xAF mode16 66_prefix norep*/ {4, 1053}, +/*h(49)=13 0xAF mode32 no66_prefix repne*/ {49, 1051}, +/*empty slot1 */ {0,0}, +/*h(5)=15 0xAF mode32 66_prefix norep*/ {5, 1045}, +/*h(50)=16 0xAF mode64 rexw_prefix repne*/ {50, 1057}, +/*h(28)=17 0xAF mode16 66_prefix repe*/ {28, 1047}, +/*h(6)=18 0xAF mode64 norexw_prefix 66_prefix norep*/ {6, 1046}, +/*empty slot1 */ {0,0}, +/*h(29)=20 0xAF mode32 66_prefix repe*/ {29, 1039}, +/*empty slot1 */ {0,0}, +/*h(52)=22 0xAF mode16 66_prefix repne*/ {52, 1050}, +/*h(30)=23 0xAF mode64 norexw_prefix 66_prefix repe*/ {30, 1040}, +/*empty slot1 */ {0,0}, +/*h(53)=25 0xAF mode32 66_prefix repne*/ {53, 1042}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=28 0xAF mode64 rexw_prefix repne*/ {54, 1057}, +/*h(32)=29 0xAF mode16 no66_prefix norep*/ {32, 1044}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=32 0xAF mode32 no66_prefix norep*/ {33, 1054}, +/*empty slot1 */ {0,0}, +/*h(56)=34 0xAF mode16 no66_prefix repe*/ {56, 1038}, +/*h(34)=35 0xAF mode64 rexw_prefix norep*/ {34, 1058}, +/*empty slot1 */ {0,0}, +/*h(57)=37 0xAF mode32 no66_prefix repe*/ {57, 1048}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=40 0xAF mode64 rexw_prefix repe*/ {58, 1056}, +/*h(36)=41 0xAF mode16 66_prefix norep*/ {36, 1053}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=44 0xAF mode32 66_prefix norep*/ {37, 1045}, +/*empty slot1 */ {0,0}, +/*h(60)=46 0xAF mode16 66_prefix repe*/ {60, 1047}, +/*h(38)=47 0xAF mode64 rexw_prefix norep*/ {38, 1058}, +/*h(16)=48 0xAF mode16 no66_prefix repne*/ {16, 1041}, +/*h(61)=49 0xAF mode32 66_prefix repe*/ {61, 1039}, +/*empty slot1 */ {0,0}, +/*h(17)=51 0xAF mode32 no66_prefix repne*/ {17, 1051}, +/*h(62)=52 0xAF mode64 rexw_prefix repe*/ {62, 1056}, +/*empty slot1 */ {0,0}, +/*h(18)=54 0xAF mode64 norexw_prefix no66_prefix repne*/ {18, 1052}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0xAF mode16 66_prefix repne*/ {20, 1050}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=63 0xAF mode32 66_prefix repne*/ {21, 1042}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=66 0xAF mode64 norexw_prefix 66_prefix repne*/ {22, 1043} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REP_REXW(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb0_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb1_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb2_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb3_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb4_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb5_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb6_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb7_vv0(const xed_decoded_inst_t* d) +{ +return 614; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb8_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xb9_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xba_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbb_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbc_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbd_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbe_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xbf_vv0(const xed_decoded_inst_t* d) +{ +return 615; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xC0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {363}, +/*h(1)=1 0xC0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {364}, +/*h(2)=2 0xC0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8()*/ {375}, +/*h(3)=3 0xC0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8()*/ {376}, +/*h(4)=4 0xC0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8()*/ {387}, +/*h(5)=5 0xC0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {388}, +/*h(6)=6 0xC0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8()*/ {399}, +/*h(7)=7 0xC0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()*/ {400}, +/*h(8)=8 0xC0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()*/ {411}, +/*h(9)=9 0xC0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {412}, +/*h(10)=10 0xC0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8()*/ {435}, +/*h(11)=11 0xC0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()*/ {436}, +/*h(12)=12 0xC0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8()*/ {413}, +/*h(13)=13 0xC0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {414}, +/*h(14)=14 0xC0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8()*/ {447}, +/*h(15)=15 0xC0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()*/ {448} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xC1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {365}, +/*h(1)=1 0xC1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {366}, +/*h(2)=2 0xC1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM8()*/ {378}, +/*h(3)=3 0xC1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM8()*/ {377}, +/*h(4)=4 0xC1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() UIMM8()*/ {389}, +/*h(5)=5 0xC1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {390}, +/*h(6)=6 0xC1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() UIMM8()*/ {401}, +/*h(7)=7 0xC1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()*/ {402}, +/*h(8)=8 0xC1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() UIMM8()*/ {415}, +/*h(9)=9 0xC1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {416}, +/*h(10)=10 0xC1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() UIMM8()*/ {437}, +/*h(11)=11 0xC1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] UIMM8()*/ {438}, +/*h(12)=12 0xC1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() UIMM8()*/ {417}, +/*h(13)=13 0xC1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {418}, +/*h(14)=14 0xC1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() UIMM8()*/ {449}, +/*h(15)=15 0xC1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()*/ {450} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc2_vv0(const xed_decoded_inst_t* d) +{ +return 1059; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc3_vv0(const xed_decoded_inst_t* d) +{ +return 1060; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {0, 1061}, +/*h(2)=1 0xC4 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {2, 1061} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {0, 1062}, +/*h(2)=1 0xC5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] not64 MODRM()*/ {2, 1062} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[29] = { +/*h(0)=0 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {0, 595}, +/*h(81)=1 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {81, 594}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(65)=4 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {65, 594}, +/*empty slot1 */ {0,0}, +/*h(112)=6 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {112, 595}, +/*h(15)=7 0xC6 MOD[0b11] MOD=3 REG[0b111] RM[0b000] UIMM8()*/ {15, 2138}, +/*h(49)=8 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {49, 594}, +/*h(96)=9 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {96, 595}, +/*empty slot1 */ {0,0}, +/*h(33)=11 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {33, 594}, +/*h(80)=12 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {80, 595}, +/*empty slot1 */ {0,0}, +/*h(17)=14 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {17, 594}, +/*empty slot1 */ {0,0}, +/*h(64)=16 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {64, 595}, +/*h(1)=17 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {1, 594}, +/*empty slot1 */ {0,0}, +/*h(48)=19 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {48, 595}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=22 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {32, 595}, +/*empty slot1 */ {0,0}, +/*h(113)=24 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {113, 594}, +/*h(16)=25 0xC6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM8()*/ {16, 595}, +/*empty slot1 */ {0,0}, +/*h(97)=27 0xC6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM8()*/ {97, 594}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 29ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[29] = { +/*h(0)=0 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {0, 597}, +/*h(81)=1 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {81, 596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(65)=4 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {65, 596}, +/*empty slot1 */ {0,0}, +/*h(112)=6 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {112, 597}, +/*h(15)=7 0xC7 MOD[0b11] MOD=3 REG[0b111] RM[0b000] BRDISPz()*/ {15, 2136}, +/*h(49)=8 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {49, 596}, +/*h(96)=9 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {96, 597}, +/*empty slot1 */ {0,0}, +/*h(33)=11 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {33, 596}, +/*h(80)=12 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {80, 597}, +/*empty slot1 */ {0,0}, +/*h(17)=14 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {17, 596}, +/*empty slot1 */ {0,0}, +/*h(64)=16 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {64, 597}, +/*h(1)=17 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {1, 596}, +/*empty slot1 */ {0,0}, +/*h(48)=19 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {48, 597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=22 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {32, 597}, +/*empty slot1 */ {0,0}, +/*h(113)=24 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {113, 596}, +/*h(16)=25 0xC7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {16, 597}, +/*empty slot1 */ {0,0}, +/*h(97)=27 0xC7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {97, 596}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 29ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc8_vv0(const xed_decoded_inst_t* d) +{ +return 1063; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xc9_vv0(const xed_decoded_inst_t* d) +{ +return 1064; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xca_vv0(const xed_decoded_inst_t* d) +{ +return 1065; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcb_vv0(const xed_decoded_inst_t* d) +{ +return 1066; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcc_vv0(const xed_decoded_inst_t* d) +{ +return 1067; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcd_vv0(const xed_decoded_inst_t* d) +{ +return 1068; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xce_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xCE not64*/ {1069}, +/*h(1)=1 0xCE not64*/ {1069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xcf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0xCF mode16 no66_prefix*/ {0, 1070}, +/*h(14)=1 0xCF mode64 rexw_prefix*/ {14, 1076}, +/*h(9)=2 0xCF mode32 no66_prefix*/ {9, 1074}, +/*h(4)=3 0xCF mode16 66_prefix*/ {4, 1073}, +/*h(2)=4 0xCF mode64 norexw_prefix no66_prefix*/ {2, 1075}, +/*h(13)=5 0xCF mode32 66_prefix*/ {13, 1071}, +/*h(8)=6 0xCF mode16 no66_prefix*/ {8, 1070}, +/*h(6)=7 0xCF mode64 norexw_prefix 66_prefix*/ {6, 1072}, +/*h(1)=8 0xCF mode32 no66_prefix*/ {1, 1074}, +/*h(12)=9 0xCF mode16 66_prefix*/ {12, 1073}, +/*h(10)=10 0xCF mode64 rexw_prefix*/ {10, 1076}, +/*h(5)=11 0xCF mode32 66_prefix*/ {5, 1071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE_OSZ_REXW(d); +hidx = ((8*key % 29) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xD0 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE()*/ {367}, +/*h(1)=1 0xD0 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE()*/ {368}, +/*h(2)=2 0xD0 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE()*/ {379}, +/*h(3)=3 0xD0 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE()*/ {380}, +/*h(4)=4 0xD0 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE()*/ {391}, +/*h(5)=5 0xD0 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE()*/ {392}, +/*h(6)=6 0xD0 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE()*/ {403}, +/*h(7)=7 0xD0 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE()*/ {404}, +/*h(8)=8 0xD0 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE()*/ {419}, +/*h(9)=9 0xD0 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE()*/ {420}, +/*h(10)=10 0xD0 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE()*/ {439}, +/*h(11)=11 0xD0 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE()*/ {440}, +/*h(12)=12 0xD0 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE()*/ {421}, +/*h(13)=13 0xD0 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE()*/ {422}, +/*h(14)=14 0xD0 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE()*/ {451}, +/*h(15)=15 0xD0 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE()*/ {452} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xD1 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() ONE()*/ {369}, +/*h(1)=1 0xD1 MOD[0b11] MOD=3 REG[0b000] RM[nnn] ONE()*/ {370}, +/*h(2)=2 0xD1 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() ONE()*/ {381}, +/*h(3)=3 0xD1 MOD[0b11] MOD=3 REG[0b001] RM[nnn] ONE()*/ {382}, +/*h(4)=4 0xD1 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() ONE()*/ {393}, +/*h(5)=5 0xD1 MOD[0b11] MOD=3 REG[0b010] RM[nnn] ONE()*/ {394}, +/*h(6)=6 0xD1 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() ONE()*/ {405}, +/*h(7)=7 0xD1 MOD[0b11] MOD=3 REG[0b011] RM[nnn] ONE()*/ {406}, +/*h(8)=8 0xD1 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() ONE()*/ {425}, +/*h(9)=9 0xD1 MOD[0b11] MOD=3 REG[0b100] RM[nnn] ONE()*/ {426}, +/*h(10)=10 0xD1 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM() ONE()*/ {441}, +/*h(11)=11 0xD1 MOD[0b11] MOD=3 REG[0b101] RM[nnn] ONE()*/ {442}, +/*h(12)=12 0xD1 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() ONE()*/ {423}, +/*h(13)=13 0xD1 MOD[0b11] MOD=3 REG[0b110] RM[nnn] ONE()*/ {424}, +/*h(14)=14 0xD1 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM() ONE()*/ {453}, +/*h(15)=15 0xD1 MOD[0b11] MOD=3 REG[0b111] RM[nnn] ONE()*/ {454} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd2_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xD2 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {371}, +/*h(1)=1 0xD2 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {372}, +/*h(2)=2 0xD2 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {383}, +/*h(3)=3 0xD2 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {384}, +/*h(4)=4 0xD2 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {395}, +/*h(5)=5 0xD2 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {396}, +/*h(6)=6 0xD2 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {407}, +/*h(7)=7 0xD2 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {408}, +/*h(8)=8 0xD2 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {427}, +/*h(9)=9 0xD2 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {428}, +/*h(10)=10 0xD2 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {443}, +/*h(11)=11 0xD2 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {444}, +/*h(12)=12 0xD2 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {429}, +/*h(13)=13 0xD2 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {430}, +/*h(14)=14 0xD2 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {455}, +/*h(15)=15 0xD2 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {456} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xD3 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {373}, +/*h(1)=1 0xD3 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {374}, +/*h(2)=2 0xD3 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {385}, +/*h(3)=3 0xD3 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {386}, +/*h(4)=4 0xD3 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {397}, +/*h(5)=5 0xD3 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {398}, +/*h(6)=6 0xD3 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {409}, +/*h(7)=7 0xD3 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {410}, +/*h(8)=8 0xD3 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {431}, +/*h(9)=9 0xD3 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {432}, +/*h(10)=10 0xD3 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {445}, +/*h(11)=11 0xD3 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {446}, +/*h(12)=12 0xD3 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {433}, +/*h(13)=13 0xD3 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {434}, +/*h(14)=14 0xD3 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {457}, +/*h(15)=15 0xD3 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {458} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd4_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xD4 not64 UIMM8()*/ {1077}, +/*h(1)=1 0xD4 not64 UIMM8()*/ {1077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd5_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xD5 not64 UIMM8()*/ {1078}, +/*h(1)=1 0xD5 not64 UIMM8()*/ {1078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xD6 not64*/ {1079}, +/*h(1)=1 0xD6 not64*/ {1079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd7_vv0(const xed_decoded_inst_t* d) +{ +return 1080; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xD8 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1}, +/*h(1)=1 0xD8 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {2}, +/*h(2)=2 0xD8 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {5}, +/*h(3)=3 0xD8 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {6}, +/*h(4)=4 0xD8 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {30}, +/*h(5)=5 0xD8 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {32}, +/*h(6)=6 0xD8 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {9}, +/*h(7)=7 0xD8 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {10}, +/*h(8)=8 0xD8 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {14}, +/*h(9)=9 0xD8 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {15}, +/*h(10)=10 0xD8 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {18}, +/*h(11)=11 0xD8 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {19}, +/*h(12)=12 0xD8 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {22}, +/*h(13)=13 0xD8 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {23}, +/*h(14)=14 0xD8 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {26}, +/*h(15)=15 0xD8 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {27} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {0, 34}, +/*h(1597)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1597, 47}, +/*h(610)=2 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {610, 60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(256)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {256, 34}, +/*h(1243)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {1243, 76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(512)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {512, 34}, +/*h(1499)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {1499, 77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(768)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1024)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1024, 34}, +/*h(37)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {37, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1280)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1536)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1536; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1792)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1792, 34}, +/*h(195)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {195, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(128)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {128, 34}, +/*h(1725)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1725, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_421_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(384)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {384, 34}, +/*h(1981)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1981, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(640)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_982_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(896)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1152)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1408)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1408; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1664)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1664, 34}, +/*h(67)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {67, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_810_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1920)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {8, 34}, +/*h(995)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {995, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(264)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {264, 34}, +/*h(1251)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {1251, 83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(520)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(776)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1051_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1032)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1032, 34}, +/*h(45)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {45, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1288)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_316_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1544)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1800)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1800, 34}, +/*h(203)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {203, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(136)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 136; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1002)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {1002, 57}, +/*h(392)=1 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {392, 34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_629_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(648)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {648, 34}, +/*h(1635)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {1635, 85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_910_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(904)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {904, 34}, +/*h(1891)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {1891, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1160)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1416)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1672)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1928)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {2, 34}, +/*h(989)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {989, 75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_586_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(258)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {258, 34}, +/*h(1245)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {1245, 76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_867_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(514)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {514, 34}, +/*h(1501)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {1501, 77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(770)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1026)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1282)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_695_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1538)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_975_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1794)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1794, 34}, +/*h(197)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {197, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(130)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(386)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(642)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(898)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1154)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1410)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_835_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1666)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1666, 34}, +/*h(69)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {69, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1922)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {10, 34}, +/*h(997)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {997, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(266)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(522)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1076_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(778)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1034)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1290)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1546)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_903_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1802)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1802, 34}, +/*h(205)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {205, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(138)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(394)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {394, 34}, +/*h(1381)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {1381, 84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(650)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {650, 34}, +/*h(1637)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {1637, 85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(906)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {906, 34}, +/*h(1893)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {1893, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1162)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1418)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1674)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1044_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1930)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 4; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(260)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(516)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 516; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(772)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1028)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1028, 34}, +/*h(41)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {41, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1284)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(930)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {930, 38}, +/*h(1540)=1 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1540, 34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1796)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(132)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(388)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(644)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {644, 34}, +/*h(34)=1 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {34, 38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(900)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1156)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1412)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1668)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1924)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 12; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(268)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(524)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 524; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(780)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1036)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1036, 34}, +/*h(49)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {49, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1292)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_928_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1548)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1804)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(140)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(396)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(652)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(908)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1164)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {34} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1164; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_788_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1420)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1420, 34}, +/*h(433)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {433, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1069_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1676)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1676, 34}, +/*h(689)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {689, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1932)=0 0xD9 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {1932, 34}, +/*h(1322)=1 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1322, 38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_800_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(988)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {988, 55}, +/*h(1)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1081_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1244)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1244, 55}, +/*h(257)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {257, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1500)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1500, 55}, +/*h(513)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {513, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(769)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1025)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1281)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1537)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(196)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {196, 53}, +/*h(1793)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1793, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(129)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(385)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(641)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1884)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1884, 55}, +/*h(897)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {897, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1153)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1153; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1049_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1409)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(68)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {68, 54}, +/*h(1665)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1665, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1921)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_728_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(996)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {996, 61}, +/*h(9)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {9, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1009_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1252)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {1252, 61}, +/*h(265)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {265, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(521)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(777)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1033)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_836_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1289)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1289; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1545)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(204)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {204, 53}, +/*h(1801)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1801, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(137)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(393)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {393, 35}, +/*h(1003)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {1003, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1636)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {1636, 62}, +/*h(649)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {649, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1892)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {1892, 62}, +/*h(905)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {905, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1161)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1417)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1673)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1673; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1929)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 3; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(259)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(515)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(771)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(40)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {40, 38}, +/*h(1027)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1027, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(296)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {296, 38}, +/*h(1283)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1283, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1539)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1795)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1728)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {1728, 48}, +/*h(131)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {131, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1984)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {1984, 48}, +/*h(387)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {387, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1253)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {1253, 83}, +/*h(643)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {643, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(899)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1155)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1411)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(680)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {680, 38}, +/*h(1667)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1667, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_621_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(936)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {936, 38}, +/*h(1923)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1923, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1034_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 11; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1864)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {1864, 51}, +/*h(267)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {267, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(523)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(779)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(48)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {48, 41}, +/*h(1035)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1035, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1291)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1547)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1803)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1736)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {1736, 51}, +/*h(139)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {139, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(395)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(651)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_721_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(907)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1163)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1163; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(432)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {432, 41}, +/*h(1419)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1419, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(688)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {688, 41}, +/*h(1675)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1675, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(944)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {944, 41}, +/*h(1931)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1931, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(992)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {992, 56}, +/*h(5)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {5, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1248)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {1248, 56}, +/*h(261)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {261, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_678_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(517)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(773)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(42)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {42, 38}, +/*h(1029)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1029, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(298)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {298, 38}, +/*h(1285)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1285, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1541)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_786_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(200)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {200, 51}, +/*h(1797)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1797, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1730)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {1730, 52}, +/*h(133)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {133, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_538_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1986)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {1986, 52}, +/*h(389)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {389, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_818_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1632)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {1632, 56}, +/*h(35)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {35, 67}, +/*h(645)=2 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {645, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1099_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1888)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {1888, 56}, +/*h(901)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {901, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1157)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1157; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1413)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(682)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {682, 38}, +/*h(1669)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1669, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_927_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(938)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {938, 38}, +/*h(1925)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1925, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {13, 35}, +/*h(1610)=1 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {1610, 49}, +/*h(1000)=2 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {1000, 59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1866)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {1866, 49}, +/*h(269)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {269, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(525)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_887_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(781)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(50)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {50, 41}, +/*h(1037)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1037, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1293)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1293; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1549)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_714_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(208)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {208, 55}, +/*h(1805)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1805, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1738)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {1738, 49}, +/*h(141)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {141, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_465_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1384)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {1384, 59}, +/*h(397)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {397, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_746_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1640)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {1640, 59}, +/*h(653)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {653, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1027_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1896)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {1896, 59}, +/*h(909)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {909, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1165)=0 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(434)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {434, 41}, +/*h(1421)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1421, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(690)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {690, 41}, +/*h(1677)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1677, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(336)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {336, 55}, +/*h(1933)=1 0xD9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1933, 35} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1007_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(32)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {32, 38}, +/*h(1629)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {1629, 78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(288)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {288, 38}, +/*h(1275)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {1275, 91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(544)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {544, 38}, +/*h(1531)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {1531, 92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(800)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {800, 38}, +/*h(1787)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {1787, 93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1056)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1312)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1312, 38}, +/*h(325)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {325, 69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1568)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1568; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1824)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(160)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {160, 38}, +/*h(1757)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {1757, 78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(416)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(672)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_694_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(928)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1184)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1440)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1696)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1696, 38}, +/*h(99)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {99, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1952)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1952, 38}, +/*h(355)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {355, 80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(552)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 552; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(808)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1064)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1064, 38}, +/*h(77)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {77, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1043_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1320)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1320, 38}, +/*h(333)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {333, 69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1576)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1832)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1832, 38}, +/*h(235)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {235, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1075_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(168)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {168, 38}, +/*h(1765)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {1765, 85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(424)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {424, 38}, +/*h(2021)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {2021, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1192)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1448)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1704)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1704, 38}, +/*h(107)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {107, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1960)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(290)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {290, 38}, +/*h(1277)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {1277, 91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(546)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {546, 38}, +/*h(1533)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {1533, 92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(802)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1058)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1314)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1570)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1826)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1826, 38}, +/*h(1216)=1 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {1216, 48}, +/*h(229)=2 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {229, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(162)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(418)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(674)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1186)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1442)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1698)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1698, 38}, +/*h(101)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {101, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1954)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1954, 38}, +/*h(357)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {357, 80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(554)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(810)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1066)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1578)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1834)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1834, 38}, +/*h(237)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {237, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(170)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(426)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1194)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1450)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1706)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1962)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(36)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 36; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(292)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(548)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(804)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1060)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1060, 38}, +/*h(73)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {73, 68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1316)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1316, 38}, +/*h(329)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {329, 69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1572)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1572; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1828)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(164)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {164, 38}, +/*h(1761)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {1761, 85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_744_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(420)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {420, 38}, +/*h(2017)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {2017, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(676)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(932)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1188)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1444)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1444; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1700)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1700; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1956)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(44)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 44; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(300)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {300, 38}, +/*h(1897)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {1897, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(556)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 556; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1093_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(812)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1068)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1068, 38}, +/*h(81)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {81, 72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(714)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {714, 49}, +/*h(1324)=1 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1324, 38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1580)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1836)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1836; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(172)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {172, 38}, +/*h(1769)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {1769, 85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_672_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(428)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {428, 38}, +/*h(2025)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {2025, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_952_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(684)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(940)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1196)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1196; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1452)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {38} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_780_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1708)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1708, 38}, +/*h(721)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {721, 74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1964)=0 0xD9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {1964, 38}, +/*h(977)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {977, 75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(304)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {304, 41}, +/*h(1901)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {1901, 86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(560)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 560; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(816)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_690_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1072)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1072, 41}, +/*h(85)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {85, 72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_970_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1328)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1584)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1840)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1840, 41}, +/*h(243)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {243, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(176)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {176, 41}, +/*h(1773)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {1773, 85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1200)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1456)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1456, 41}, +/*h(469)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {469, 73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1712)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1712, 41}, +/*h(725)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {725, 74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1968)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1968, 41}, +/*h(371)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {371, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_790_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(56)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {56, 41}, +/*h(1653)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {1653, 93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(312)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {312, 41}, +/*h(1909)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {1909, 94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(568)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 568; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(824)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {824, 41}, +/*h(1811)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1811, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1080)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1080; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1336)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1592)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1592; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1848)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1848, 41}, +/*h(861)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {861, 75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_930_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(184)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {184, 41}, +/*h(1171)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1171, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1211_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(440)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {440, 41}, +/*h(1427)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1427, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(696)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(952)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 952; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1208)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1208, 41}, +/*h(221)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {221, 72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1039_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1464)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1464, 41}, +/*h(477)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {477, 73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1720)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1720, 41}, +/*h(123)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {123, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1976)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1976, 41}, +/*h(379)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {379, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(306)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(562)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(818)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_995_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1074)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1074, 41}, +/*h(464)=1 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {464, 55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1330)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1586)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1842)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1842, 41}, +/*h(245)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {245, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(178)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(946)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1202)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1458)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1714)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_682_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1970)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1970, 41}, +/*h(373)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {373, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1096_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(58)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 58; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(314)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(570)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(826)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {826, 41}, +/*h(1813)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1813, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1082)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1338)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1594)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1850)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(186)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {186, 41}, +/*h(1173)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1173, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(442)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {442, 41}, +/*h(1429)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1429, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(698)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_783_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(954)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1210)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1466)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1722)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1722, 41}, +/*h(125)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {125, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1978)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1978, 41}, +/*h(381)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {381, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(52)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {52, 41}, +/*h(1649)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {1649, 93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(308)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {308, 41}, +/*h(1905)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {1905, 94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(564)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 564; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(820)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 820; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1076)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1076; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1332)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1588)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1844)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(180)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 180; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(436)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 436; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(692)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(948)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 948; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1204)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1204, 41}, +/*h(217)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {217, 72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1460)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1460, 41}, +/*h(473)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {473, 73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1716)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1716, 41}, +/*h(729)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {729, 74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_988_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1972)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(60)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {60, 41}, +/*h(1657)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {1657, 93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(316)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {316, 41}, +/*h(1913)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {1913, 94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(572)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 572; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_948_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(828)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1084)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1084; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1340)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1340; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1596)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1596, 41}, +/*h(609)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {609, 81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1852)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1852, 41}, +/*h(865)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {865, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(188)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(444)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {444, 41}, +/*h(2041)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {2041, 94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_808_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(700)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 700; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1089_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(956)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1212)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1212, 41}, +/*h(225)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {225, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(858)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {858, 55}, +/*h(1468)=1 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {1468, 41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1724)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1724; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_916_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1980)=0 0xD9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {41} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(305)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(561)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(817)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1683)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1683, 64}, +/*h(1073)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1073, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1329)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1329; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1585)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1037_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(244)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {244, 63}, +/*h(1841)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1841, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(177)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(945)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1201)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1457)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1713)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(372)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {372, 63}, +/*h(1969)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1969, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(57)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 57; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(313)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 313; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(569)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(825)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 825; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1081)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1081; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1337)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_684_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1593)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1849)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(185)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_716_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(441)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 441; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_997_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(697)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(953)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1209)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1465)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_824_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(124)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {124, 63}, +/*h(1721)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1721, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(380)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {380, 63}, +/*h(1977)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1977, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1648)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1648, 63}, +/*h(51)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {51, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_954_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1904)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1904, 63}, +/*h(307)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {307, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(563)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(819)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 819; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(465)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {465, 73}, +/*h(1075)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1075, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1331)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1062_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1587)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1843)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(179)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 179; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1094_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(435)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(691)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(947)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_641_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {216, 55}, +/*h(1203)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1203, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_922_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(472)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {472, 55}, +/*h(1459)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1459, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(728)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {728, 55}, +/*h(1715)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1715, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1971)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1656)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1656, 63}, +/*h(59)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {59, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_882_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1912)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1912, 63}, +/*h(315)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {315, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1181)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1181, 64}, +/*h(571)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {571, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(827)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1083)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1083; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1339)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1595)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(864)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {864, 56}, +/*h(1851)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1851, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(187)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2040)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2040, 63}, +/*h(443)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {443, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(699)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(955)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 955; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(224)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {224, 56}, +/*h(1211)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1211, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1467)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1467, 47}, +/*h(857)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {857, 75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1723)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1979)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_979_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1650)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1650, 63}, +/*h(53)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {53, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1260_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1906)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1906, 63}, +/*h(309)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {309, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(565)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 565; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(821)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1077)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1077; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1333)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1333; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1589)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(248)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {248, 63}, +/*h(1845)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1845, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(181)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 181; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(437)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(693)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(949)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_947_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(218)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {218, 55}, +/*h(1205)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1205, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1228_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(474)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {474, 55}, +/*h(1461)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1461, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(730)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {730, 55}, +/*h(1717)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1717, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(376)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {376, 63}, +/*h(1973)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1973, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_907_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1658)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1658, 63}, +/*h(61)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {61, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1914)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1914, 63}, +/*h(317)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {317, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(573)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 573; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(829)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_734_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1085)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1085; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1341)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(866)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {866, 60}, +/*h(1853)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1853, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(189)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2042)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2042, 63}, +/*h(445)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {445, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(701)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(957)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_875_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {226, 60}, +/*h(1213)=1 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {1213, 47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1469)=0 0xD9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {47} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_718_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(64)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {64, 48}, +/*h(1661)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {1661, 93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_999_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(320)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {320, 48}, +/*h(1917)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {1917, 94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1279_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(576)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {576, 48}, +/*h(1563)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1563, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(832)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {832, 48}, +/*h(1819)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1819, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1088)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {48} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1088; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1344)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {48} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1344; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1600)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {1600, 48}, +/*h(613)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {613, 81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1856)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {1856, 48}, +/*h(869)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {869, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_858_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(192)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {192, 48}, +/*h(1179)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1179, 64}, +/*h(1789)=2 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {1789, 93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(448)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {448, 48}, +/*h(2045)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {2045, 94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(704)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {48} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(960)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {48} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_966_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1472)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {48} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1472; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(74)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 74; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(330)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(586)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(842)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_779_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1098)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1098; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1060_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1354)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(202)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(458)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(970)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1226)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1482)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1994)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {49} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(76)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {50} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 76; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(332)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {50} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 332; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(588)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {50} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_804_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(844)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {50} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1085_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1100)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {1100, 50}, +/*h(113)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {113, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1356)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {1356, 50}, +/*h(369)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {369, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1612)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {50} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1868)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {50} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_645_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(72)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 72; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(328)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 328; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(584)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(840)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1096)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {1096, 51}, +/*h(109)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {109, 79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_754_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1352)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {1352, 51}, +/*h(365)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {365, 80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1608)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {1608, 51}, +/*h(621)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {621, 81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1067_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(456)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(968)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1224)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1480)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {51} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1992)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {1992, 51}, +/*h(1005)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {1005, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(66)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 66; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(322)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {322, 52}, +/*h(1309)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1309, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(578)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {578, 52}, +/*h(1565)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1565, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_570_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(834)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {834, 52}, +/*h(1821)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1821, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_851_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1090)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1346)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1602)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1858)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(194)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(450)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 450; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_711_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_991_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1218)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {1218, 52}, +/*h(608)=1 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {608, 56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1474)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {52} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(452)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_736_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(708)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(964)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1220)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1476)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1476; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1732)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_844_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1988)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1988; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(460)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 460; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_663_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(716)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {716, 53}, +/*h(106)=1 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {106, 57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_944_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(972)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1228)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1484)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {53} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1484; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_491_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1740)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {1740, 53}, +/*h(753)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {753, 89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_772_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1996)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {1996, 53}, +/*h(1009)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {1009, 90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(324)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {54} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 324; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(580)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {54} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_876_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(836)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {54} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 836; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1092)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {54} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1092; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1348)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {1348, 54}, +/*h(361)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {361, 80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1604)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {1604, 54}, +/*h(617)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {617, 81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_704_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1860)=0 0xD9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {1860, 54}, +/*h(873)=1 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {873, 82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(80)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 80; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(592)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 592; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(848)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_401_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1104)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1104, 55}, +/*h(117)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {117, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1360)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1360; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_962_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1616)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1616, 55}, +/*h(19)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {19, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1243_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1872)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1872, 55}, +/*h(275)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {275, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(976)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1232)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_822_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1488)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1488, 55}, +/*h(501)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {501, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1744)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1744, 55}, +/*h(757)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {757, 89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2000)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {2000, 55}, +/*h(1013)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {1013, 90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(88)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {88, 55}, +/*h(1685)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1685, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_782_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(344)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {344, 55}, +/*h(1941)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1941, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(600)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(856)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1112)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1112; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1368)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1368; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_890_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1624)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1624, 55}, +/*h(27)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {27, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1880)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1880, 55}, +/*h(283)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {283, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(984)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1240)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1240, 55}, +/*h(253)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {253, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1496)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1496, 55}, +/*h(509)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {509, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1031_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1752)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1752, 55}, +/*h(765)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {765, 89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2008)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {2008, 55}, +/*h(411)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {411, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(82)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 82; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(338)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 338; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(594)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(850)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1106)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_987_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1362)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1618)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1618, 55}, +/*h(21)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {21, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1874)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1874, 55}, +/*h(277)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {277, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1020_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(466)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(978)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1234)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1490)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1746)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2002)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(90)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 90; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(346)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(602)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1114)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1370)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1626)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1626, 55}, +/*h(29)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {29, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1882)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1882, 55}, +/*h(285)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {285, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1242)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1056_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1498)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1144)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1144, 63}, +/*h(157)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {157, 64}, +/*h(1754)=2 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1754, 55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_321_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2010)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {2010, 55}, +/*h(413)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {413, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(84)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 84; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(340)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {340, 55}, +/*h(1937)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1937, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(596)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(852)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 852; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1108)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1108, 55}, +/*h(121)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {121, 87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1364)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1364; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1620)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1876)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(212)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {212, 55}, +/*h(1809)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1809, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(468)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 468; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(724)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 724; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_872_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(980)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1236)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1492)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1492, 55}, +/*h(505)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {505, 88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1748)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {1748, 55}, +/*h(761)=1 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {761, 89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_699_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2004)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {2004, 55}, +/*h(1394)=1 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1394, 63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(92)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {92, 55}, +/*h(1689)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1689, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(348)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {348, 55}, +/*h(1945)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1945, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(604)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_659_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(860)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {860, 55}, +/*h(250)=1 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {250, 63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1116)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1116; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1372)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1372; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1628)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1628; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(220)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(476)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 476; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(732)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1756)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2012)=0 0xD9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {55} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2012; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_429_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(96)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {96, 56}, +/*h(1693)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1693, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(352)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {352, 56}, +/*h(1949)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1949, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1120)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1120; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1376)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1376; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_850_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1504)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_958_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1760)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {1760, 56}, +/*h(163)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {163, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2016)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {56} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_943_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(362)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {362, 57}, +/*h(1349)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {1349, 71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(618)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(874)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1130)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1386)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1386; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1642)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1898)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_803_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(234)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(490)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1258)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_911_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1514)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1192_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1770)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {1770, 57}, +/*h(173)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {173, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2026)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {57} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_968_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(108)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {58} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 108; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(364)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {58} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 364; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(620)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {58} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(876)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {58} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_796_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1132)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {1132, 58}, +/*h(145)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {145, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1077_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1388)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {1388, 58}, +/*h(401)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {401, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1644)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {1644, 58}, +/*h(657)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {657, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1900)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {58} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(104)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 104; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(360)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {360, 59}, +/*h(1347)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {1347, 71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(616)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(872)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1128)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1128; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(232)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_778_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(488)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(744)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1256)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_605_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1512)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1768)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {1768, 59}, +/*h(171)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {171, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2024)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {59} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(98)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 98; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1016_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(354)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 354; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1122)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1378)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1634)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1890)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(482)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(994)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1250)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_983_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1506)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1762)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {1762, 60}, +/*h(165)=1 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {165, 67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2018)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {60} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(228)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(484)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 484; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(740)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 740; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1508)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1508; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1764)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1764; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2020)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(236)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(492)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 492; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(748)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 748; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1004)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1260)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1516)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1516; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1772)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {61} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2028)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {2028, 61}, +/*h(1041)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1041, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(100)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {62} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 100; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(356)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {62} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 356; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(612)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {62} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(868)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {62} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1124)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {62} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1124; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1380)=0 0xD9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {62} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1380; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(112)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {112, 63}, +/*h(1099)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {1099, 70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(368)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {368, 63}, +/*h(1355)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {1355, 71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(624)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 624; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(880)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1136)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1136, 63}, +/*h(149)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {149, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1392)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1392, 63}, +/*h(405)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {405, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(240)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_706_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(496)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1008)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1264)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1264; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1520)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_814_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1776)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1776, 63}, +/*h(789)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {789, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1095_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2032)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2032, 63}, +/*h(1045)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1045, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(120)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {120, 63}, +/*h(1107)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {1107, 76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_774_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(632)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1055_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(888)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1400)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_633_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(504)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {504, 63}, +/*h(1491)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {1491, 77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_914_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(760)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {760, 63}, +/*h(1747)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {1747, 78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1016)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1272)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1528)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1528, 63}, +/*h(541)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {541, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_742_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1784)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1784, 63}, +/*h(797)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {797, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(114)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {114, 63}, +/*h(1101)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {1101, 70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_871_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(370)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {370, 63}, +/*h(1357)=1 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {1357, 71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(626)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(882)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1138)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(498)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(754)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1010)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1266)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1522)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1778)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2034)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(122)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {122, 63}, +/*h(1109)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {1109, 76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_799_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(378)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(634)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(890)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1146)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_626_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1402)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_939_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(506)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {506, 63}, +/*h(1493)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {1493, 77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {762, 63}, +/*h(1749)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {1749, 78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1018)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1274)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1530)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1048_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1786)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(116)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 116; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(628)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 628; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(884)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_724_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1140)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1140, 63}, +/*h(153)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {153, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1396)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1652)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1908)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(500)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 500; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(756)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1012)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1012; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1268)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1524)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1524, 63}, +/*h(537)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {537, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1780)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {1780, 63}, +/*h(793)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {793, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2036)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {2036, 63}, +/*h(1049)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {1049, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(636)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(892)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 892; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1148)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1404)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1404; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1660)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1660; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1916)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(252)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(508)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 508; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(764)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 764; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1020)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1276)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1532)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1532; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1788)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1788; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2044)=0 0xD9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {63} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2044; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_656_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 17; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_937_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(273)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(529)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(785)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1297)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1045_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1553)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(913)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 913; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1169)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_905_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1425)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1425; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1681)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 25; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_865_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(281)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1305)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1561)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1817)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1817; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(409)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 409; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(665)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(921)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1177)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1433)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1433; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(531)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1397)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {1397, 92}, +/*h(787)=1 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {787, 64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_789_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1043)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1070_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1299)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1299; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1555)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(147)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(403)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(659)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(915)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1939)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(539)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_436_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1051)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1051; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_998_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1307)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1307; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(155)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(667)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 667; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(923)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1435)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1691)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1947)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(533)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 533; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1301)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1301; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1557)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1557; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(661)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(917)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1023_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1053)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(669)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_883_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(925)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 925; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1437)=0 0xD9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(33)=0 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 33; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(161)=0 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(169)=0 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_745_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(43)=0 0xD9 MOD[0b11] MOD=3 REG[0b010] RM[0b000]*/ {67} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 43; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(65)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 65; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(193)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(201)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(75)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {68} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 75; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(321)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(449)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(457)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(323)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 323; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(451)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_737_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(331)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 331; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(459)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(453)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(461)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {69} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1089)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1089; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1217)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1097)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1225)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1091)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1091; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1219)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1227)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1093)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1221)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1221; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1229)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {70} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1229; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1345)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1473)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1353)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1481)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1475)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_705_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1483)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1477)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1477; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1485)=0 0xD9 MOD[0b11] MOD=3 REG[0b100] RM[0b101]*/ {71} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(209)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(89)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 89; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_384_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(83)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 83; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(211)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(91)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 91; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(213)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 213; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(93)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b000]*/ {72} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 93; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(337)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 337; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(345)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 345; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(339)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 339; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(467)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(347)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 347; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(475)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_971_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(341)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 341; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(349)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {73} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 349; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(593)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(601)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(595)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(723)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(603)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(731)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(597)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(605)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(733)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b010]*/ {74} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_921_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(849)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_989_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(985)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(851)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(979)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(249)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {249, 87}, +/*h(859)=1 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {859, 75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(987)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(853)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(981)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b011]*/ {75} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1105)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1233)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1113)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1113; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1241)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1235)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1115)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1237)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1237; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1117)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b100]*/ {76} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1117; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1361)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1361; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1489)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1369)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1369; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1497)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1363)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1371)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1371; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1365)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1365; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1373)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b101]*/ {77} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1373; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1617)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1745)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1625)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1753)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_773_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1619)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_701_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1627)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1755)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1621)=0 0xD9 MOD[0b11] MOD=3 REG[0b101] RM[0b110]*/ {78} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(97)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 97; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(105)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 105; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(233)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b000]*/ {79} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(353)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 353; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(481)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(489)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(363)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 363; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(491)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_967_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(485)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(493)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b001]*/ {80} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(737)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 737; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(745)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(611)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_942_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(739)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(619)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(747)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(741)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(749)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b010]*/ {81} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(993)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1001)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(867)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1010_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(875)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(877)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b011]*/ {82} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 877; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1057_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1121)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1121; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1249)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1129)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1129; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1257)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1123)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1123; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1131)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1131; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1259)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1125)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_301_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1133)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1261)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b100]*/ {83} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1261; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1377)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1505)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1385)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1385; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1513)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1379)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1379; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1507)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1387)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1387; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1515)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1509)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1389)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1389; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_722_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1517)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b101]*/ {84} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1633)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1641)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_769_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1763)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1643)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1771)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1645)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b110]*/ {85} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1889)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2019)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1899)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_978_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2027)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2029)=0 0xD9 MOD[0b11] MOD=3 REG[0b110] RM[0b111]*/ {86} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(241)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 241; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(115)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 115; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(251)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b000]*/ {87} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(497)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(377)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 377; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(499)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(507)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b001]*/ {88} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(625)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 625; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(633)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(627)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_797_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(635)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(763)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_963_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(629)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 629; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(637)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b010]*/ {89} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(881)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(889)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1017)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(883)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1078_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1011)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(891)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1006_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1019)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(885)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(893)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1021)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b011]*/ {90} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_913_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1137)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1137; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1265)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_840_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1145)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1145; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1273)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1139)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1267)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1267; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1147)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1147; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1141)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1141; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1269)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1269; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1149)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b100]*/ {91} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1149; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1393)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1521)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1521; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1401)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1529)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1529; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1395)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1395; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1523)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1403)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1525)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1405)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b101]*/ {92} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1777)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1785)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1651)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1779)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1659)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1659; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1781)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b110]*/ {93} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2033)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_765_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1907)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2035)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1915)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 1915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2043)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2037)=0 0xD9 MOD[0b11] MOD=3 REG[0b111] RM[0b111]*/ {94} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = key - 2037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xd9_vv0(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[1296] = { +/*h(610)=0 */ {610, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_0_l1}, +/*h(1220)=1 */ {1220, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1_l1}, +/*h(233)=2 */ {233, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_2_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(466)=4 */ {466, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_4_l1}, +/*h(1076)=5 */ {1076, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_5_l1}, +/*h(89)=6 */ {89, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_6_l1}, +/*h(699)=7 */ {699, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_7_l1}, +/*h(1309)=8 */ {1309, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_8_l1}, +/*h(932)=9 */ {932, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_9_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1165)=12 */ {1165, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_12_l1}, +/*h(178)=13 */ {178, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(411)=15 */ {411, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_15_l1}, +/*h(1021)=16 */ {1021, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_16_l1}, +/*h(34)=17 */ {34, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_17_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1864)=19 */ {1864, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_19_l1}, +/*h(877)=20 */ {877, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(500)=22 */ {500, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_22_l1}, +/*h(123)=23 */ {123, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_23_l1}, +/*h(733)=24 */ {733, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_24_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(356)=26 */ {356, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_26_l1}, +/*h(1576)=27 */ {1576, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_27_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1809)=30 */ {1809, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_30_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2042)=32 */ {2042, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(68)=34 */ {68, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_34_l1}, +/*h(1288)=35 */ {1288, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_35_l1}, +/*h(1898)=36 */ {1898, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1521)=38 */ {1521, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_38_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(157)=40 */ {157, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_40_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1377)=42 */ {1377, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1000)=44 */ {1000, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_44_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1233)=46 */ {1233, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_46_l1}, +/*h(1843)=47 */ {1843, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_47_l1}, +/*h(856)=48 */ {856, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_48_l1}, +/*h(1466)=49 */ {1466, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_49_l1}, +/*h(1089)=50 */ {1089, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_50_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(712)=52 */ {712, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_52_l1}, +/*h(1322)=53 */ {1322, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_53_l1}, +/*h(945)=54 */ {945, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_54_l1}, +/*h(1555)=55 */ {1555, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_55_l1}, +/*h(568)=56 */ {568, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1788)=58 */ {1788, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_58_l1}, +/*h(1411)=59 */ {1411, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_59_l1}, +/*h(2021)=60 */ {2021, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_60_l1}, +/*h(1034)=61 */ {1034, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_61_l1}, +/*h(657)=62 */ {657, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_62_l1}, +/*h(1267)=63 */ {1267, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_63_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(890)=65 */ {890, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_65_l1}, +/*h(1500)=66 */ {1500, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_66_l1}, +/*h(1123)=67 */ {1123, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_67_l1}, +/*h(136)=68 */ {136, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_68_l1}, +/*h(746)=69 */ {746, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_69_l1}, +/*h(369)=70 */ {369, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_70_l1}, +/*h(979)=71 */ {979, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_71_l1}, +/*h(1589)=72 */ {1589, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_72_l1}, +/*h(602)=73 */ {602, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_73_l1}, +/*h(225)=74 */ {225, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_74_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(458)=77 */ {458, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_77_l1}, +/*h(81)=78 */ {81, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_78_l1}, +/*h(691)=79 */ {691, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_79_l1}, +/*h(1301)=80 */ {1301, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_80_l1}, +/*h(314)=81 */ {314, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_81_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1157)=84 */ {1157, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_84_l1}, +/*h(170)=85 */ {170, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_85_l1}, +/*h(780)=86 */ {780, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_86_l1}, +/*h(403)=87 */ {403, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_87_l1}, +/*h(1013)=88 */ {1013, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_88_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(636)=90 */ {636, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_90_l1}, +/*h(259)=91 */ {259, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_91_l1}, +/*h(869)=92 */ {869, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_92_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(492)=94 */ {492, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_94_l1}, +/*h(115)=95 */ {115, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_95_l1}, +/*h(725)=96 */ {725, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_96_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1945)=98 */ {1945, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1568)=100 */ {1568, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(204)=102 */ {204, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(437)=104 */ {437, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_104_l1}, +/*h(2034)=105 */ {2034, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_105_l1}, +/*h(1657)=106 */ {1657, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1280)=108 */ {1280, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_108_l1}, +/*h(1890)=109 */ {1890, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_109_l1}, +/*h(1513)=110 */ {1513, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(149)=112 */ {149, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_112_l1}, +/*h(1746)=113 */ {1746, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_113_l1}, +/*h(1369)=114 */ {1369, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_114_l1}, +/*h(1979)=115 */ {1979, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_115_l1}, +/*h(992)=116 */ {992, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_116_l1}, +/*h(1602)=117 */ {1602, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_117_l1}, +/*h(1225)=118 */ {1225, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(848)=120 */ {848, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_120_l1}, +/*h(1458)=121 */ {1458, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_121_l1}, +/*h(1081)=122 */ {1081, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_122_l1}, +/*h(1691)=123 */ {1691, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_123_l1}, +/*h(704)=124 */ {704, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_124_l1}, +/*h(1314)=125 */ {1314, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_125_l1}, +/*h(1924)=126 */ {1924, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_126_l1}, +/*h(1547)=127 */ {1547, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_127_l1}, +/*h(560)=128 */ {560, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(793)=130 */ {793, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_130_l1}, +/*h(1403)=131 */ {1403, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_131_l1}, +/*h(416)=132 */ {416, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_132_l1}, +/*h(1026)=133 */ {1026, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_133_l1}, +/*h(1636)=134 */ {1636, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_134_l1}, +/*h(1259)=135 */ {1259, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(882)=137 */ {882, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_137_l1}, +/*h(505)=138 */ {505, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_138_l1}, +/*h(1115)=139 */ {1115, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_139_l1}, +/*h(1725)=140 */ {1725, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_140_l1}, +/*h(738)=141 */ {738, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_141_l1}, +/*h(361)=142 */ {361, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(594)=145 */ {594, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_145_l1}, +/*h(217)=146 */ {217, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_146_l1}, +/*h(827)=147 */ {827, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_147_l1}, +/*h(1437)=148 */ {1437, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_148_l1}, +/*h(450)=149 */ {450, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_149_l1}, +/*h(73)=150 */ {73, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1293)=152 */ {1293, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_152_l1}, +/*h(306)=153 */ {306, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(539)=155 */ {539, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_155_l1}, +/*h(1149)=156 */ {1149, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_156_l1}, +/*h(162)=157 */ {162, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_157_l1}, +/*h(772)=158 */ {772, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_158_l1}, +/*h(395)=159 */ {395, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_159_l1}, +/*h(1005)=160 */ {1005, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(628)=162 */ {628, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_162_l1}, +/*h(251)=163 */ {251, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_163_l1}, +/*h(861)=164 */ {861, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_164_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(484)=166 */ {484, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(107)=168 */ {107, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1937)=170 */ {1937, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(573)=172 */ {573, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(196)=174 */ {196, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_174_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1416)=176 */ {1416, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_176_l1}, +/*h(2026)=177 */ {2026, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_177_l1}, +/*h(1649)=178 */ {1649, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1272)=180 */ {1272, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_180_l1}, +/*h(285)=181 */ {285, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_181_l1}, +/*h(1505)=182 */ {1505, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_182_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1128)=184 */ {1128, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_184_l1}, +/*h(1738)=185 */ {1738, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_185_l1}, +/*h(1361)=186 */ {1361, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_186_l1}, +/*h(1971)=187 */ {1971, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_187_l1}, +/*h(984)=188 */ {984, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_188_l1}, +/*h(1594)=189 */ {1594, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_189_l1}, +/*h(1217)=190 */ {1217, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(840)=192 */ {840, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_192_l1}, +/*h(1450)=193 */ {1450, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1683)=195 */ {1683, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_195_l1}, +/*h(696)=196 */ {696, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1916)=198 */ {1916, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_198_l1}, +/*h(1539)=199 */ {1539, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_199_l1}, +/*h(552)=200 */ {552, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_200_l1}, +/*h(1162)=201 */ {1162, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_201_l1}, +/*h(1772)=202 */ {1772, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_202_l1}, +/*h(785)=203 */ {785, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_203_l1}, +/*h(1395)=204 */ {1395, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_204_l1}, +/*h(1018)=205 */ {1018, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_205_l1}, +/*h(1628)=206 */ {1628, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_206_l1}, +/*h(641)=207 */ {641, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_207_l1}, +/*h(1251)=208 */ {1251, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_208_l1}, +/*h(874)=209 */ {874, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_209_l1}, +/*h(1484)=210 */ {1484, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_210_l1}, +/*h(497)=211 */ {497, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_211_l1}, +/*h(1107)=212 */ {1107, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_212_l1}, +/*h(730)=213 */ {730, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_213_l1}, +/*h(1340)=214 */ {1340, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_214_l1}, +/*h(353)=215 */ {353, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(586)=217 */ {586, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_217_l1}, +/*h(1196)=218 */ {1196, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_218_l1}, +/*h(209)=219 */ {209, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_219_l1}, +/*h(819)=220 */ {819, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_220_l1}, +/*h(1429)=221 */ {1429, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_221_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(65)=223 */ {65, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_223_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(298)=225 */ {298, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_225_l1}, +/*h(908)=226 */ {908, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_226_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(531)=228 */ {531, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_228_l1}, +/*h(1141)=229 */ {1141, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_229_l1}, +/*h(764)=230 */ {764, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1984)=232 */ {1984, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_232_l1}, +/*h(997)=233 */ {997, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_233_l1}, +/*h(620)=234 */ {620, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_234_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(243)=236 */ {243, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_236_l1}, +/*h(853)=237 */ {853, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_237_l1}, +/*h(476)=238 */ {476, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(99)=240 */ {99, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(332)=242 */ {332, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_242_l1}, +/*h(1929)=243 */ {1929, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_243_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(565)=245 */ {565, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_245_l1}, +/*h(188)=246 */ {188, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_246_l1}, +/*h(1785)=247 */ {1785, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_247_l1}, +/*h(1408)=248 */ {1408, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_248_l1}, +/*h(2018)=249 */ {2018, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_249_l1}, +/*h(44)=250 */ {44, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_250_l1}, +/*h(1641)=251 */ {1641, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_251_l1}, +/*h(1264)=252 */ {1264, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_252_l1}, +/*h(277)=253 */ {277, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1497)=255 */ {1497, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_255_l1}, +/*h(1120)=256 */ {1120, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_256_l1}, +/*h(1730)=257 */ {1730, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1353)=259 */ {1353, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_259_l1}, +/*h(976)=260 */ {976, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_260_l1}, +/*h(1586)=261 */ {1586, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1209)=263 */ {1209, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_263_l1}, +/*h(1819)=264 */ {1819, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_264_l1}, +/*h(1442)=265 */ {1442, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_265_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(688)=268 */ {688, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1908)=270 */ {1908, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_270_l1}, +/*h(921)=271 */ {921, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_271_l1}, +/*h(1531)=272 */ {1531, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_272_l1}, +/*h(1154)=273 */ {1154, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_273_l1}, +/*h(1764)=274 */ {1764, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_274_l1}, +/*h(777)=275 */ {777, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_275_l1}, +/*h(1387)=276 */ {1387, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_276_l1}, +/*h(1010)=277 */ {1010, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_277_l1}, +/*h(1620)=278 */ {1620, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_278_l1}, +/*h(633)=279 */ {633, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_279_l1}, +/*h(1243)=280 */ {1243, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_280_l1}, +/*h(866)=281 */ {866, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_281_l1}, +/*h(1476)=282 */ {1476, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_282_l1}, +/*h(489)=283 */ {489, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_283_l1}, +/*h(1099)=284 */ {1099, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_284_l1}, +/*h(722)=285 */ {722, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_285_l1}, +/*h(1332)=286 */ {1332, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_286_l1}, +/*h(345)=287 */ {345, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_287_l1}, +/*h(955)=288 */ {955, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_288_l1}, +/*h(1565)=289 */ {1565, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_289_l1}, +/*h(1188)=290 */ {1188, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_290_l1}, +/*h(201)=291 */ {201, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_291_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(434)=293 */ {434, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(57)=295 */ {57, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_295_l1}, +/*h(667)=296 */ {667, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_296_l1}, +/*h(1277)=297 */ {1277, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_297_l1}, +/*h(900)=298 */ {900, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(523)=300 */ {523, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_300_l1}, +/*h(1133)=301 */ {1133, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_301_l1}, +/*h(756)=302 */ {756, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(379)=304 */ {379, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_304_l1}, +/*h(989)=305 */ {989, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_305_l1}, +/*h(612)=306 */ {612, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_306_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(235)=308 */ {235, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_308_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(468)=310 */ {468, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(91)=312 */ {91, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_312_l1}, +/*h(701)=313 */ {701, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_313_l1}, +/*h(324)=314 */ {324, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_314_l1}, +/*h(1921)=315 */ {1921, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_315_l1}, +/*h(1544)=316 */ {1544, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_316_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(180)=318 */ {180, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_318_l1}, +/*h(1777)=319 */ {1777, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_319_l1}, +/*h(1400)=320 */ {1400, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_320_l1}, +/*h(413)=321 */ {413, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_321_l1}, +/*h(36)=322 */ {36, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_322_l1}, +/*h(1633)=323 */ {1633, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_323_l1}, +/*h(1256)=324 */ {1256, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_324_l1}, +/*h(1866)=325 */ {1866, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1489)=327 */ {1489, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_327_l1}, +/*h(1112)=328 */ {1112, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_328_l1}, +/*h(125)=329 */ {125, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1345)=331 */ {1345, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_331_l1}, +/*h(968)=332 */ {968, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_332_l1}, +/*h(1578)=333 */ {1578, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1201)=335 */ {1201, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_335_l1}, +/*h(1811)=336 */ {1811, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_336_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2044)=338 */ {2044, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(680)=340 */ {680, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_340_l1}, +/*h(1290)=341 */ {1290, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_341_l1}, +/*h(1900)=342 */ {1900, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_342_l1}, +/*h(913)=343 */ {913, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_343_l1}, +/*h(1523)=344 */ {1523, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_344_l1}, +/*h(1146)=345 */ {1146, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_345_l1}, +/*h(1756)=346 */ {1756, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_346_l1}, +/*h(769)=347 */ {769, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_347_l1}, +/*h(1379)=348 */ {1379, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_348_l1}, +/*h(1002)=349 */ {1002, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_349_l1}, +/*h(1612)=350 */ {1612, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_350_l1}, +/*h(625)=351 */ {625, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_351_l1}, +/*h(1235)=352 */ {1235, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_352_l1}, +/*h(248)=353 */ {248, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_353_l1}, +/*h(858)=354 */ {858, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_354_l1}, +/*h(481)=355 */ {481, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_355_l1}, +/*h(1091)=356 */ {1091, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_356_l1}, +/*h(104)=357 */ {104, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_357_l1}, +/*h(714)=358 */ {714, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_358_l1}, +/*h(337)=359 */ {337, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_359_l1}, +/*h(947)=360 */ {947, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_360_l1}, +/*h(1557)=361 */ {1557, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_361_l1}, +/*h(570)=362 */ {570, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_362_l1}, +/*h(193)=363 */ {193, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_363_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1413)=365 */ {1413, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_365_l1}, +/*h(426)=366 */ {426, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_366_l1}, +/*h(49)=367 */ {49, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_367_l1}, +/*h(659)=368 */ {659, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_368_l1}, +/*h(1269)=369 */ {1269, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_369_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(892)=371 */ {892, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_371_l1}, +/*h(515)=372 */ {515, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_372_l1}, +/*h(1125)=373 */ {1125, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_373_l1}, +/*h(138)=374 */ {138, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_374_l1}, +/*h(748)=375 */ {748, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_375_l1}, +/*h(371)=376 */ {371, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_376_l1}, +/*h(981)=377 */ {981, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(604)=379 */ {604, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_379_l1}, +/*h(227)=380 */ {227, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_380_l1}, +/*h(1824)=381 */ {1824, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_381_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(460)=383 */ {460, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_383_l1}, +/*h(83)=384 */ {83, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_384_l1}, +/*h(693)=385 */ {693, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_385_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1913)=387 */ {1913, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1536)=389 */ {1536, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_389_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1769)=391 */ {1769, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_391_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(405)=393 */ {405, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_393_l1}, +/*h(2002)=394 */ {2002, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_394_l1}, +/*h(1625)=395 */ {1625, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1248)=397 */ {1248, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_397_l1}, +/*h(1858)=398 */ {1858, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_398_l1}, +/*h(1481)=399 */ {1481, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(117)=401 */ {117, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_401_l1}, +/*h(1714)=402 */ {1714, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_402_l1}, +/*h(1337)=403 */ {1337, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_403_l1}, +/*h(1947)=404 */ {1947, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_404_l1}, +/*h(960)=405 */ {960, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_405_l1}, +/*h(1570)=406 */ {1570, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1803)=408 */ {1803, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_408_l1}, +/*h(816)=409 */ {816, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_409_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1049)=411 */ {1049, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_411_l1}, +/*h(1659)=412 */ {1659, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_412_l1}, +/*h(672)=413 */ {672, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_413_l1}, +/*h(1282)=414 */ {1282, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_414_l1}, +/*h(1892)=415 */ {1892, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_415_l1}, +/*h(1515)=416 */ {1515, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_416_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1138)=418 */ {1138, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_418_l1}, +/*h(761)=419 */ {761, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_419_l1}, +/*h(1371)=420 */ {1371, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_420_l1}, +/*h(1981)=421 */ {1981, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_421_l1}, +/*h(994)=422 */ {994, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_422_l1}, +/*h(617)=423 */ {617, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_423_l1}, +/*h(1227)=424 */ {1227, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_424_l1}, +/*h(240)=425 */ {240, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_425_l1}, +/*h(850)=426 */ {850, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_426_l1}, +/*h(473)=427 */ {473, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_427_l1}, +/*h(1083)=428 */ {1083, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_428_l1}, +/*h(1693)=429 */ {1693, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_429_l1}, +/*h(706)=430 */ {706, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_430_l1}, +/*h(329)=431 */ {329, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_431_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1549)=433 */ {1549, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_433_l1}, +/*h(562)=434 */ {562, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_434_l1}, +/*h(185)=435 */ {185, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_435_l1}, +/*h(795)=436 */ {795, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_436_l1}, +/*h(1405)=437 */ {1405, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_437_l1}, +/*h(418)=438 */ {418, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_438_l1}, +/*h(41)=439 */ {41, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_439_l1}, +/*h(651)=440 */ {651, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_440_l1}, +/*h(1261)=441 */ {1261, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_441_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(884)=443 */ {884, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_443_l1}, +/*h(507)=444 */ {507, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_444_l1}, +/*h(1117)=445 */ {1117, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_445_l1}, +/*h(130)=446 */ {130, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_446_l1}, +/*h(740)=447 */ {740, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_447_l1}, +/*h(363)=448 */ {363, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_448_l1}, +/*h(1960)=449 */ {1960, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_449_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(596)=451 */ {596, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_451_l1}, +/*h(219)=452 */ {219, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_452_l1}, +/*h(829)=453 */ {829, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_453_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(452)=455 */ {452, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_455_l1}, +/*h(75)=456 */ {75, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_456_l1}, +/*h(1672)=457 */ {1672, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_457_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1905)=459 */ {1905, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(541)=461 */ {541, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_461_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1761)=463 */ {1761, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_463_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1384)=465 */ {1384, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_465_l1}, +/*h(1994)=466 */ {1994, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_466_l1}, +/*h(1617)=467 */ {1617, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_467_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(253)=469 */ {253, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_469_l1}, +/*h(1850)=470 */ {1850, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_470_l1}, +/*h(1473)=471 */ {1473, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(109)=473 */ {109, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_473_l1}, +/*h(1706)=474 */ {1706, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_474_l1}, +/*h(1329)=475 */ {1329, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_475_l1}, +/*h(1939)=476 */ {1939, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_476_l1}, +/*h(952)=477 */ {952, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1795)=480 */ {1795, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_480_l1}, +/*h(808)=481 */ {808, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_481_l1}, +/*h(1418)=482 */ {1418, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_482_l1}, +/*h(1041)=483 */ {1041, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_483_l1}, +/*h(1651)=484 */ {1651, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_484_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1274)=486 */ {1274, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_486_l1}, +/*h(1884)=487 */ {1884, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_487_l1}, +/*h(1507)=488 */ {1507, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_488_l1}, +/*h(520)=489 */ {520, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_489_l1}, +/*h(1130)=490 */ {1130, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_490_l1}, +/*h(753)=491 */ {753, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_491_l1}, +/*h(1363)=492 */ {1363, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_492_l1}, +/*h(376)=493 */ {376, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_493_l1}, +/*h(986)=494 */ {986, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_494_l1}, +/*h(609)=495 */ {609, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_495_l1}, +/*h(1219)=496 */ {1219, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_496_l1}, +/*h(232)=497 */ {232, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_497_l1}, +/*h(842)=498 */ {842, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_498_l1}, +/*h(1452)=499 */ {1452, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_499_l1}, +/*h(465)=500 */ {465, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_500_l1}, +/*h(1685)=501 */ {1685, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_501_l1}, +/*h(698)=502 */ {698, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(321)=504 */ {321, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_504_l1}, +/*h(1541)=505 */ {1541, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_505_l1}, +/*h(554)=506 */ {554, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_506_l1}, +/*h(1164)=507 */ {1164, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_507_l1}, +/*h(177)=508 */ {177, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_508_l1}, +/*h(1397)=509 */ {1397, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_509_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1020)=511 */ {1020, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_511_l1}, +/*h(33)=512 */ {33, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_512_l1}, +/*h(1253)=513 */ {1253, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_513_l1}, +/*h(266)=514 */ {266, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_514_l1}, +/*h(876)=515 */ {876, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(499)=517 */ {499, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_517_l1}, +/*h(1109)=518 */ {1109, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_518_l1}, +/*h(732)=519 */ {732, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(355)=521 */ {355, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_521_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(588)=523 */ {588, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_523_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(211)=525 */ {211, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_525_l1}, +/*h(821)=526 */ {821, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_526_l1}, +/*h(2041)=527 */ {2041, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_527_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(67)=529 */ {67, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_529_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1897)=531 */ {1897, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_531_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1520)=533 */ {1520, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_533_l1}, +/*h(533)=534 */ {533, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_534_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1753)=536 */ {1753, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_536_l1}, +/*h(1376)=537 */ {1376, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_537_l1}, +/*h(1986)=538 */ {1986, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_538_l1}, +/*h(12)=539 */ {12, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_539_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1232)=541 */ {1232, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_541_l1}, +/*h(245)=542 */ {245, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1465)=544 */ {1465, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_544_l1}, +/*h(1088)=545 */ {1088, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_545_l1}, +/*h(101)=546 */ {101, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(944)=549 */ {944, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1177)=552 */ {1177, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_552_l1}, +/*h(1787)=553 */ {1787, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_553_l1}, +/*h(1410)=554 */ {1410, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_554_l1}, +/*h(2020)=555 */ {2020, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_555_l1}, +/*h(1033)=556 */ {1033, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_556_l1}, +/*h(1643)=557 */ {1643, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_557_l1}, +/*h(1266)=558 */ {1266, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_558_l1}, +/*h(1876)=559 */ {1876, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_559_l1}, +/*h(889)=560 */ {889, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_560_l1}, +/*h(1499)=561 */ {1499, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_561_l1}, +/*h(1122)=562 */ {1122, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_562_l1}, +/*h(1732)=563 */ {1732, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_563_l1}, +/*h(745)=564 */ {745, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_564_l1}, +/*h(1355)=565 */ {1355, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_565_l1}, +/*h(978)=566 */ {978, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_566_l1}, +/*h(1588)=567 */ {1588, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_567_l1}, +/*h(601)=568 */ {601, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_568_l1}, +/*h(224)=569 */ {224, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_569_l1}, +/*h(1821)=570 */ {1821, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_570_l1}, +/*h(1444)=571 */ {1444, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_571_l1}, +/*h(457)=572 */ {457, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_572_l1}, +/*h(80)=573 */ {80, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_573_l1}, +/*h(690)=574 */ {690, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(313)=576 */ {313, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_576_l1}, +/*h(923)=577 */ {923, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_577_l1}, +/*h(1533)=578 */ {1533, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_578_l1}, +/*h(1156)=579 */ {1156, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_579_l1}, +/*h(169)=580 */ {169, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_580_l1}, +/*h(779)=581 */ {779, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_581_l1}, +/*h(1389)=582 */ {1389, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_582_l1}, +/*h(1012)=583 */ {1012, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_583_l1}, +/*h(25)=584 */ {25, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_584_l1}, +/*h(635)=585 */ {635, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_585_l1}, +/*h(1245)=586 */ {1245, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_586_l1}, +/*h(868)=587 */ {868, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_587_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(491)=589 */ {491, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_589_l1}, +/*h(1101)=590 */ {1101, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_590_l1}, +/*h(724)=591 */ {724, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_591_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(347)=593 */ {347, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_593_l1}, +/*h(957)=594 */ {957, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_594_l1}, +/*h(580)=595 */ {580, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_595_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(203)=597 */ {203, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(436)=599 */ {436, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_599_l1}, +/*h(2033)=600 */ {2033, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_600_l1}, +/*h(1656)=601 */ {1656, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_601_l1}, +/*h(669)=602 */ {669, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_602_l1}, +/*h(292)=603 */ {292, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_603_l1}, +/*h(1889)=604 */ {1889, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_604_l1}, +/*h(1512)=605 */ {1512, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_605_l1}, +/*h(525)=606 */ {525, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_606_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1745)=608 */ {1745, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_608_l1}, +/*h(1368)=609 */ {1368, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_609_l1}, +/*h(381)=610 */ {381, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_610_l1}, +/*h(4)=611 */ {4, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_611_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1224)=613 */ {1224, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_613_l1}, +/*h(237)=614 */ {237, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_614_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1457)=616 */ {1457, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_616_l1}, +/*h(1080)=617 */ {1080, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_617_l1}, +/*h(93)=618 */ {93, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_618_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(936)=621 */ {936, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_621_l1}, +/*h(1546)=622 */ {1546, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_622_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1169)=624 */ {1169, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_624_l1}, +/*h(1779)=625 */ {1779, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_625_l1}, +/*h(1402)=626 */ {1402, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_626_l1}, +/*h(2012)=627 */ {2012, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_627_l1}, +/*h(1025)=628 */ {1025, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_628_l1}, +/*h(1635)=629 */ {1635, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_629_l1}, +/*h(1258)=630 */ {1258, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_630_l1}, +/*h(1868)=631 */ {1868, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_631_l1}, +/*h(881)=632 */ {881, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_632_l1}, +/*h(1491)=633 */ {1491, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_633_l1}, +/*h(1114)=634 */ {1114, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_634_l1}, +/*h(1724)=635 */ {1724, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_635_l1}, +/*h(737)=636 */ {737, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_636_l1}, +/*h(1347)=637 */ {1347, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_637_l1}, +/*h(970)=638 */ {970, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_638_l1}, +/*h(1580)=639 */ {1580, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_639_l1}, +/*h(593)=640 */ {593, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_640_l1}, +/*h(216)=641 */ {216, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_641_l1}, +/*h(1813)=642 */ {1813, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_642_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(449)=644 */ {449, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_644_l1}, +/*h(72)=645 */ {72, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_645_l1}, +/*h(682)=646 */ {682, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_646_l1}, +/*h(1292)=647 */ {1292, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_647_l1}, +/*h(305)=648 */ {305, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_648_l1}, +/*h(915)=649 */ {915, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_649_l1}, +/*h(1525)=650 */ {1525, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_650_l1}, +/*h(1148)=651 */ {1148, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_651_l1}, +/*h(161)=652 */ {161, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_652_l1}, +/*h(771)=653 */ {771, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_653_l1}, +/*h(1381)=654 */ {1381, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_654_l1}, +/*h(1004)=655 */ {1004, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_655_l1}, +/*h(17)=656 */ {17, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_656_l1}, +/*h(627)=657 */ {627, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_657_l1}, +/*h(1237)=658 */ {1237, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_658_l1}, +/*h(250)=659 */ {250, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_659_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(483)=661 */ {483, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_661_l1}, +/*h(1093)=662 */ {1093, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_662_l1}, +/*h(106)=663 */ {106, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_663_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(339)=665 */ {339, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_665_l1}, +/*h(949)=666 */ {949, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_666_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(572)=668 */ {572, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_668_l1}, +/*h(195)=669 */ {195, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2025)=672 */ {2025, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_672_l1}, +/*h(1648)=673 */ {1648, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_673_l1}, +/*h(661)=674 */ {661, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_674_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1504)=677 */ {1504, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_677_l1}, +/*h(517)=678 */ {517, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_678_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(140)=680 */ {140, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_680_l1}, +/*h(1360)=681 */ {1360, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_681_l1}, +/*h(373)=682 */ {373, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_682_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1593)=684 */ {1593, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(229)=686 */ {229, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(85)=690 */ {85, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_690_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1305)=692 */ {1305, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_692_l1}, +/*h(1915)=693 */ {1915, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_693_l1}, +/*h(928)=694 */ {928, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_694_l1}, +/*h(1538)=695 */ {1538, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_695_l1}, +/*h(1161)=696 */ {1161, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_696_l1}, +/*h(1771)=697 */ {1771, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_697_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1394)=699 */ {1394, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_699_l1}, +/*h(1017)=700 */ {1017, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_700_l1}, +/*h(1627)=701 */ {1627, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_701_l1}, +/*h(640)=702 */ {640, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_702_l1}, +/*h(1250)=703 */ {1250, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_703_l1}, +/*h(873)=704 */ {873, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_704_l1}, +/*h(1483)=705 */ {1483, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_705_l1}, +/*h(496)=706 */ {496, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_706_l1}, +/*h(1106)=707 */ {1106, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_707_l1}, +/*h(729)=708 */ {729, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_708_l1}, +/*h(1339)=709 */ {1339, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_709_l1}, +/*h(1949)=710 */ {1949, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_710_l1}, +/*h(962)=711 */ {962, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_711_l1}, +/*h(1572)=712 */ {1572, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_712_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(208)=714 */ {208, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_714_l1}, +/*h(818)=715 */ {818, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_715_l1}, +/*h(441)=716 */ {441, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_716_l1}, +/*h(1051)=717 */ {1051, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_717_l1}, +/*h(1661)=718 */ {1661, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_718_l1}, +/*h(674)=719 */ {674, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_719_l1}, +/*h(1284)=720 */ {1284, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_720_l1}, +/*h(907)=721 */ {907, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_721_l1}, +/*h(1517)=722 */ {1517, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_722_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(153)=724 */ {153, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_724_l1}, +/*h(763)=725 */ {763, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_725_l1}, +/*h(1373)=726 */ {1373, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_726_l1}, +/*h(386)=727 */ {386, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_727_l1}, +/*h(996)=728 */ {996, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_728_l1}, +/*h(619)=729 */ {619, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_729_l1}, +/*h(1229)=730 */ {1229, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_730_l1}, +/*h(242)=731 */ {242, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_731_l1}, +/*h(852)=732 */ {852, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_732_l1}, +/*h(475)=733 */ {475, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_733_l1}, +/*h(1085)=734 */ {1085, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_734_l1}, +/*h(98)=735 */ {98, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_735_l1}, +/*h(708)=736 */ {708, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_736_l1}, +/*h(331)=737 */ {331, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_737_l1}, +/*h(1928)=738 */ {1928, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_738_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(564)=740 */ {564, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_740_l1}, +/*h(187)=741 */ {187, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_741_l1}, +/*h(797)=742 */ {797, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_742_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2017)=744 */ {2017, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_744_l1}, +/*h(43)=745 */ {43, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_745_l1}, +/*h(1640)=746 */ {1640, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_746_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(509)=750 */ {509, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(132)=752 */ {132, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_752_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(365)=754 */ {365, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_754_l1}, +/*h(1962)=755 */ {1962, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_755_l1}, +/*h(1585)=756 */ {1585, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(221)=758 */ {221, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_758_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(77)=762 */ {77, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_762_l1}, +/*h(1674)=763 */ {1674, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_763_l1}, +/*h(1297)=764 */ {1297, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_764_l1}, +/*h(1907)=765 */ {1907, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_765_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1530)=767 */ {1530, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_767_l1}, +/*h(1153)=768 */ {1153, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_768_l1}, +/*h(1763)=769 */ {1763, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_769_l1}, +/*h(776)=770 */ {776, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_770_l1}, +/*h(1386)=771 */ {1386, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_771_l1}, +/*h(1009)=772 */ {1009, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_772_l1}, +/*h(1619)=773 */ {1619, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_773_l1}, +/*h(632)=774 */ {632, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_774_l1}, +/*h(1242)=775 */ {1242, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_775_l1}, +/*h(865)=776 */ {865, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_776_l1}, +/*h(1475)=777 */ {1475, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_777_l1}, +/*h(488)=778 */ {488, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_778_l1}, +/*h(1098)=779 */ {1098, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_779_l1}, +/*h(721)=780 */ {721, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_780_l1}, +/*h(1331)=781 */ {1331, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_781_l1}, +/*h(1941)=782 */ {1941, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_782_l1}, +/*h(954)=783 */ {954, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_783_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(200)=786 */ {200, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_786_l1}, +/*h(810)=787 */ {810, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_787_l1}, +/*h(433)=788 */ {433, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_788_l1}, +/*h(1043)=789 */ {1043, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_789_l1}, +/*h(1653)=790 */ {1653, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_790_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1276)=792 */ {1276, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_792_l1}, +/*h(899)=793 */ {899, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_793_l1}, +/*h(1509)=794 */ {1509, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_794_l1}, +/*h(522)=795 */ {522, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_795_l1}, +/*h(145)=796 */ {145, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_796_l1}, +/*h(755)=797 */ {755, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_797_l1}, +/*h(1365)=798 */ {1365, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_798_l1}, +/*h(378)=799 */ {378, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_799_l1}, +/*h(988)=800 */ {988, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_800_l1}, +/*h(611)=801 */ {611, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_801_l1}, +/*h(1221)=802 */ {1221, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_802_l1}, +/*h(234)=803 */ {234, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_803_l1}, +/*h(844)=804 */ {844, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_804_l1}, +/*h(467)=805 */ {467, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_805_l1}, +/*h(1077)=806 */ {1077, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_806_l1}, +/*h(90)=807 */ {90, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_807_l1}, +/*h(700)=808 */ {700, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_808_l1}, +/*h(323)=809 */ {323, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_809_l1}, +/*h(1920)=810 */ {1920, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_810_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(556)=812 */ {556, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_812_l1}, +/*h(179)=813 */ {179, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_813_l1}, +/*h(789)=814 */ {789, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_814_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(35)=818 */ {35, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_818_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(268)=820 */ {268, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(501)=822 */ {501, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_822_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(124)=824 */ {124, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_824_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1344)=826 */ {1344, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_826_l1}, +/*h(357)=827 */ {357, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_827_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1200)=830 */ {1200, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_830_l1}, +/*h(213)=831 */ {213, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_831_l1}, +/*h(1433)=832 */ {1433, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_832_l1}, +/*h(2043)=833 */ {2043, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_833_l1}, +/*h(1056)=834 */ {1056, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_834_l1}, +/*h(69)=835 */ {69, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_835_l1}, +/*h(1289)=836 */ {1289, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_836_l1}, +/*h(1899)=837 */ {1899, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_837_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1522)=839 */ {1522, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_839_l1}, +/*h(1145)=840 */ {1145, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_840_l1}, +/*h(1755)=841 */ {1755, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_841_l1}, +/*h(768)=842 */ {768, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_842_l1}, +/*h(1378)=843 */ {1378, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_843_l1}, +/*h(1988)=844 */ {1988, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_844_l1}, +/*h(1001)=845 */ {1001, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_845_l1}, +/*h(624)=846 */ {624, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_846_l1}, +/*h(1234)=847 */ {1234, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_847_l1}, +/*h(1844)=848 */ {1844, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_848_l1}, +/*h(857)=849 */ {857, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_849_l1}, +/*h(480)=850 */ {480, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_850_l1}, +/*h(1090)=851 */ {1090, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_851_l1}, +/*h(1700)=852 */ {1700, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_852_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(336)=854 */ {336, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_854_l1}, +/*h(946)=855 */ {946, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_855_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(569)=857 */ {569, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_857_l1}, +/*h(1789)=858 */ {1789, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_858_l1}, +/*h(802)=859 */ {802, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_859_l1}, +/*h(1412)=860 */ {1412, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_860_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(48)=862 */ {48, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_862_l1}, +/*h(1645)=863 */ {1645, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_863_l1}, +/*h(1268)=864 */ {1268, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_864_l1}, +/*h(281)=865 */ {281, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_865_l1}, +/*h(891)=866 */ {891, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_866_l1}, +/*h(1501)=867 */ {1501, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_867_l1}, +/*h(1124)=868 */ {1124, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_868_l1}, +/*h(137)=869 */ {137, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_869_l1}, +/*h(747)=870 */ {747, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_870_l1}, +/*h(1357)=871 */ {1357, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_871_l1}, +/*h(980)=872 */ {980, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_872_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(603)=874 */ {603, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_874_l1}, +/*h(226)=875 */ {226, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_875_l1}, +/*h(836)=876 */ {836, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_876_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(459)=878 */ {459, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_878_l1}, +/*h(82)=879 */ {82, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_879_l1}, +/*h(692)=880 */ {692, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1912)=882 */ {1912, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_882_l1}, +/*h(925)=883 */ {925, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_883_l1}, +/*h(548)=884 */ {548, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_884_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(171)=886 */ {171, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_886_l1}, +/*h(781)=887 */ {781, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_887_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(27)=890 */ {27, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_890_l1}, +/*h(637)=891 */ {637, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_891_l1}, +/*h(260)=892 */ {260, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_892_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1480)=894 */ {1480, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_894_l1}, +/*h(493)=895 */ {493, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_895_l1}, +/*h(116)=896 */ {116, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_896_l1}, +/*h(1713)=897 */ {1713, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_897_l1}, +/*h(1336)=898 */ {1336, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_898_l1}, +/*h(349)=899 */ {349, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_899_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1192)=902 */ {1192, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_902_l1}, +/*h(205)=903 */ {205, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1425)=905 */ {1425, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_905_l1}, +/*h(2035)=906 */ {2035, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_906_l1}, +/*h(1658)=907 */ {1658, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_907_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1281)=909 */ {1281, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_909_l1}, +/*h(1891)=910 */ {1891, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_910_l1}, +/*h(1514)=911 */ {1514, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_911_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1137)=913 */ {1137, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_913_l1}, +/*h(1747)=914 */ {1747, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_914_l1}, +/*h(1370)=915 */ {1370, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_915_l1}, +/*h(1980)=916 */ {1980, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_916_l1}, +/*h(993)=917 */ {993, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_917_l1}, +/*h(616)=918 */ {616, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_918_l1}, +/*h(1226)=919 */ {1226, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_919_l1}, +/*h(1836)=920 */ {1836, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_920_l1}, +/*h(849)=921 */ {849, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_921_l1}, +/*h(472)=922 */ {472, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_922_l1}, +/*h(1082)=923 */ {1082, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_923_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(328)=926 */ {328, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_926_l1}, +/*h(938)=927 */ {938, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_927_l1}, +/*h(1548)=928 */ {1548, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_928_l1}, +/*h(561)=929 */ {561, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_929_l1}, +/*h(1171)=930 */ {1171, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_930_l1}, +/*h(1781)=931 */ {1781, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_931_l1}, +/*h(1404)=932 */ {1404, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(40)=934 */ {40, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_934_l1}, +/*h(1637)=935 */ {1637, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_935_l1}, +/*h(1260)=936 */ {1260, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_936_l1}, +/*h(273)=937 */ {273, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_937_l1}, +/*h(883)=938 */ {883, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_938_l1}, +/*h(1493)=939 */ {1493, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_939_l1}, +/*h(1116)=940 */ {1116, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_940_l1}, +/*h(129)=941 */ {129, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_941_l1}, +/*h(739)=942 */ {739, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_942_l1}, +/*h(1349)=943 */ {1349, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_943_l1}, +/*h(972)=944 */ {972, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_944_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(595)=946 */ {595, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_946_l1}, +/*h(218)=947 */ {218, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_947_l1}, +/*h(828)=948 */ {828, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_948_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(451)=950 */ {451, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_950_l1}, +/*h(74)=951 */ {74, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_951_l1}, +/*h(684)=952 */ {684, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_952_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1904)=954 */ {1904, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_954_l1}, +/*h(917)=955 */ {917, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_955_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(163)=958 */ {163, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_958_l1}, +/*h(773)=959 */ {773, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_959_l1}, +/*h(396)=960 */ {396, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_960_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(19)=962 */ {19, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_962_l1}, +/*h(629)=963 */ {629, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_963_l1}, +/*h(252)=964 */ {252, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_964_l1}, +/*h(1849)=965 */ {1849, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_965_l1}, +/*h(1472)=966 */ {1472, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_966_l1}, +/*h(485)=967 */ {485, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_967_l1}, +/*h(108)=968 */ {108, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_968_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1328)=970 */ {1328, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_970_l1}, +/*h(341)=971 */ {341, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_971_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1561)=973 */ {1561, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_973_l1}, +/*h(1184)=974 */ {1184, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_974_l1}, +/*h(197)=975 */ {197, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_975_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1417)=977 */ {1417, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_977_l1}, +/*h(2027)=978 */ {2027, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_978_l1}, +/*h(1650)=979 */ {1650, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_979_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1273)=981 */ {1273, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_981_l1}, +/*h(896)=982 */ {896, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_982_l1}, +/*h(1506)=983 */ {1506, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_983_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1129)=985 */ {1129, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_985_l1}, +/*h(752)=986 */ {752, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_986_l1}, +/*h(1362)=987 */ {1362, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_987_l1}, +/*h(1972)=988 */ {1972, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_988_l1}, +/*h(985)=989 */ {985, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_989_l1}, +/*h(1595)=990 */ {1595, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_990_l1}, +/*h(608)=991 */ {608, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_991_l1}, +/*h(1828)=992 */ {1828, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_992_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(464)=995 */ {464, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_995_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(697)=997 */ {697, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_997_l1}, +/*h(1307)=998 */ {1307, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_998_l1}, +/*h(1917)=999 */ {1917, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_999_l1}, +/*h(930)=1000 */ {930, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1000_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1163)=1002 */ {1163, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1002_l1}, +/*h(1773)=1003 */ {1773, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1003_l1}, +/*h(1396)=1004 */ {1396, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1004_l1}, +/*h(409)=1005 */ {409, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1005_l1}, +/*h(1019)=1006 */ {1019, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1006_l1}, +/*h(1629)=1007 */ {1629, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1007_l1}, +/*h(642)=1008 */ {642, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1008_l1}, +/*h(1252)=1009 */ {1252, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1009_l1}, +/*h(875)=1010 */ {875, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1010_l1}, +/*h(1485)=1011 */ {1485, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1011_l1}, +/*h(498)=1012 */ {498, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1012_l1}, +/*h(121)=1013 */ {121, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1013_l1}, +/*h(731)=1014 */ {731, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1014_l1}, +/*h(1341)=1015 */ {1341, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1015_l1}, +/*h(354)=1016 */ {354, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1016_l1}, +/*h(964)=1017 */ {964, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1017_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(210)=1020 */ {210, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1020_l1}, +/*h(820)=1021 */ {820, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1021_l1}, +/*h(2040)=1022 */ {2040, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1022_l1}, +/*h(1053)=1023 */ {1053, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1023_l1}, +/*h(66)=1024 */ {66, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1024_l1}, +/*h(676)=1025 */ {676, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1896)=1027 */ {1896, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(155)=1030 */ {155, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1030_l1}, +/*h(765)=1031 */ {765, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1031_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(388)=1033 */ {388, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1033_l1}, +/*h(11)=1034 */ {11, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1034_l1}, +/*h(621)=1035 */ {621, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1035_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(244)=1037 */ {244, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1037_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(477)=1039 */ {477, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1039_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(100)=1041 */ {100, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1041_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(333)=1043 */ {333, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1043_l1}, +/*h(1930)=1044 */ {1930, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1044_l1}, +/*h(1553)=1045 */ {1553, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1045_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(189)=1047 */ {189, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1047_l1}, +/*h(1786)=1048 */ {1786, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1048_l1}, +/*h(1409)=1049 */ {1409, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1049_l1}, +/*h(2019)=1050 */ {2019, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1050_l1}, +/*h(45)=1051 */ {45, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1051_l1}, +/*h(1642)=1052 */ {1642, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1052_l1}, +/*h(1265)=1053 */ {1265, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1053_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(888)=1055 */ {888, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1055_l1}, +/*h(1498)=1056 */ {1498, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1056_l1}, +/*h(1121)=1057 */ {1121, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1057_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(744)=1059 */ {744, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1059_l1}, +/*h(1354)=1060 */ {1354, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1060_l1}, +/*h(977)=1061 */ {977, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1061_l1}, +/*h(1587)=1062 */ {1587, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1062_l1}, +/*h(600)=1063 */ {600, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1063_l1}, +/*h(1210)=1064 */ {1210, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1064_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(456)=1067 */ {456, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1067_l1}, +/*h(1066)=1068 */ {1066, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1068_l1}, +/*h(689)=1069 */ {689, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1069_l1}, +/*h(1299)=1070 */ {1299, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1070_l1}, +/*h(1909)=1071 */ {1909, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1071_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1532)=1073 */ {1532, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1073_l1}, +/*h(1155)=1074 */ {1155, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1074_l1}, +/*h(1765)=1075 */ {1765, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1075_l1}, +/*h(778)=1076 */ {778, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1076_l1}, +/*h(401)=1077 */ {401, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1077_l1}, +/*h(1011)=1078 */ {1011, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1078_l1}, +/*h(1621)=1079 */ {1621, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1079_l1}, +/*h(634)=1080 */ {634, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1080_l1}, +/*h(1244)=1081 */ {1244, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1081_l1}, +/*h(867)=1082 */ {867, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1082_l1}, +/*h(1477)=1083 */ {1477, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1083_l1}, +/*h(490)=1084 */ {490, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1084_l1}, +/*h(113)=1085 */ {113, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1085_l1}, +/*h(723)=1086 */ {723, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1086_l1}, +/*h(1333)=1087 */ {1333, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1087_l1}, +/*h(346)=1088 */ {346, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1088_l1}, +/*h(956)=1089 */ {956, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1089_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(202)=1092 */ {202, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1092_l1}, +/*h(812)=1093 */ {812, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1093_l1}, +/*h(435)=1094 */ {435, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1094_l1}, +/*h(1045)=1095 */ {1045, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1095_l1}, +/*h(58)=1096 */ {58, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1096_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1888)=1099 */ {1888, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1099_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(524)=1101 */ {524, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1101_l1}, +/*h(147)=1102 */ {147, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1102_l1}, +/*h(757)=1103 */ {757, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(380)=1105 */ {380, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1105_l1}, +/*h(3)=1106 */ {3, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1106_l1}, +/*h(613)=1107 */ {613, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(236)=1109 */ {236, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1109_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(469)=1111 */ {469, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1689)=1113 */ {1689, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(325)=1115 */ {325, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1115_l1}, +/*h(1922)=1116 */ {1922, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1116_l1}, +/*h(1545)=1117 */ {1545, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(181)=1119 */ {181, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1119_l1}, +/*h(1778)=1120 */ {1778, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1120_l1}, +/*h(1401)=1121 */ {1401, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(37)=1123 */ {37, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1123_l1}, +/*h(1634)=1124 */ {1634, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1124_l1}, +/*h(1257)=1125 */ {1257, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(880)=1127 */ {880, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1127_l1}, +/*h(1490)=1128 */ {1490, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1128_l1}, +/*h(1113)=1129 */ {1113, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1129_l1}, +/*h(1723)=1130 */ {1723, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1130_l1}, +/*h(736)=1131 */ {736, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1131_l1}, +/*h(1346)=1132 */ {1346, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1132_l1}, +/*h(1956)=1133 */ {1956, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(592)=1135 */ {592, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1135_l1}, +/*h(1202)=1136 */ {1202, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1136_l1}, +/*h(825)=1137 */ {825, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1137_l1}, +/*h(1435)=1138 */ {1435, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1138_l1}, +/*h(2045)=1139 */ {2045, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1139_l1}, +/*h(1058)=1140 */ {1058, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1140_l1}, +/*h(1668)=1141 */ {1668, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1141_l1}, +/*h(1291)=1142 */ {1291, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1142_l1}, +/*h(1901)=1143 */ {1901, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1143_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(537)=1145 */ {537, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1145_l1}, +/*h(1147)=1146 */ {1147, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1146_l1}, +/*h(1757)=1147 */ {1757, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1147_l1}, +/*h(770)=1148 */ {770, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1148_l1}, +/*h(1380)=1149 */ {1380, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1149_l1}, +/*h(1003)=1150 */ {1003, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(626)=1152 */ {626, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1152_l1}, +/*h(1236)=1153 */ {1236, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1153_l1}, +/*h(249)=1154 */ {249, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1154_l1}, +/*h(1469)=1155 */ {1469, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1155_l1}, +/*h(482)=1156 */ {482, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1156_l1}, +/*h(1092)=1157 */ {1092, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1157_l1}, +/*h(105)=1158 */ {105, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(338)=1160 */ {338, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1160_l1}, +/*h(948)=1161 */ {948, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1181)=1163 */ {1181, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1163_l1}, +/*h(194)=1164 */ {194, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1164_l1}, +/*h(804)=1165 */ {804, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1165_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2024)=1167 */ {2024, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1167_l1}, +/*h(50)=1168 */ {50, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(283)=1171 */ {283, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1171_l1}, +/*h(893)=1172 */ {893, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1172_l1}, +/*h(516)=1173 */ {516, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1736)=1175 */ {1736, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1175_l1}, +/*h(749)=1176 */ {749, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1176_l1}, +/*h(372)=1177 */ {372, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1177_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1592)=1179 */ {1592, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1179_l1}, +/*h(605)=1180 */ {605, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1180_l1}, +/*h(228)=1181 */ {228, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1181_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1448)=1183 */ {1448, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1183_l1}, +/*h(461)=1184 */ {461, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1184_l1}, +/*h(84)=1185 */ {84, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1185_l1}, +/*h(1681)=1186 */ {1681, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1186_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1914)=1188 */ {1914, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1537)=1190 */ {1537, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1190_l1}, +/*h(1160)=1191 */ {1160, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1191_l1}, +/*h(173)=1192 */ {173, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1192_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1393)=1194 */ {1393, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1194_l1}, +/*h(1016)=1195 */ {1016, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1195_l1}, +/*h(29)=1196 */ {29, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1249)=1198 */ {1249, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1198_l1}, +/*h(872)=1199 */ {872, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1199_l1}, +/*h(1482)=1200 */ {1482, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1105)=1202 */ {1105, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1202_l1}, +/*h(728)=1203 */ {728, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1203_l1}, +/*h(1338)=1204 */ {1338, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1204_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(584)=1207 */ {584, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1207_l1}, +/*h(1194)=1208 */ {1194, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1208_l1}, +/*h(1804)=1209 */ {1804, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1209_l1}, +/*h(817)=1210 */ {817, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1210_l1}, +/*h(1427)=1211 */ {1427, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1211_l1}, +/*h(2037)=1212 */ {2037, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1212_l1}, +/*h(1660)=1213 */ {1660, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(296)=1215 */ {296, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1215_l1}, +/*h(1893)=1216 */ {1893, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1216_l1}, +/*h(1516)=1217 */ {1516, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1217_l1}, +/*h(529)=1218 */ {529, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1218_l1}, +/*h(1139)=1219 */ {1139, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1219_l1}, +/*h(1749)=1220 */ {1749, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1220_l1}, +/*h(1372)=1221 */ {1372, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1221_l1}, +/*h(385)=1222 */ {385, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1222_l1}, +/*h(995)=1223 */ {995, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1223_l1}, +/*h(618)=1224 */ {618, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1224_l1}, +/*h(1228)=1225 */ {1228, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1225_l1}, +/*h(241)=1226 */ {241, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1226_l1}, +/*h(851)=1227 */ {851, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1227_l1}, +/*h(474)=1228 */ {474, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1228_l1}, +/*h(1084)=1229 */ {1084, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1229_l1}, +/*h(97)=1230 */ {97, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(330)=1232 */ {330, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1232_l1}, +/*h(940)=1233 */ {940, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(563)=1235 */ {563, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1235_l1}, +/*h(1173)=1236 */ {1173, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1236_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2016)=1239 */ {2016, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1239_l1}, +/*h(42)=1240 */ {42, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1240_l1}, +/*h(652)=1241 */ {652, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1241_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(275)=1243 */ {275, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1243_l1}, +/*h(885)=1244 */ {885, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1244_l1}, +/*h(508)=1245 */ {508, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1245_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1728)=1247 */ {1728, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1247_l1}, +/*h(741)=1248 */ {741, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1248_l1}, +/*h(364)=1249 */ {364, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1584)=1251 */ {1584, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1251_l1}, +/*h(597)=1252 */ {597, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1252_l1}, +/*h(220)=1253 */ {220, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1253_l1}, +/*h(1817)=1254 */ {1817, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1254_l1}, +/*h(1440)=1255 */ {1440, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1255_l1}, +/*h(453)=1256 */ {453, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1256_l1}, +/*h(76)=1257 */ {76, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1257_l1}, +/*h(1673)=1258 */ {1673, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1906)=1260 */ {1906, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1260_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1529)=1262 */ {1529, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1262_l1}, +/*h(1152)=1263 */ {1152, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1263_l1}, +/*h(165)=1264 */ {165, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1385)=1266 */ {1385, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1266_l1}, +/*h(1008)=1267 */ {1008, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1267_l1}, +/*h(21)=1268 */ {21, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1241)=1270 */ {1241, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1270_l1}, +/*h(864)=1271 */ {864, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1271_l1}, +/*h(1474)=1272 */ {1474, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1272_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1097)=1274 */ {1097, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1274_l1}, +/*h(720)=1275 */ {720, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1275_l1}, +/*h(1330)=1276 */ {1330, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(953)=1278 */ {953, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1278_l1}, +/*h(1563)=1279 */ {1563, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1279_l1}, +/*h(1186)=1280 */ {1186, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1280_l1}, +/*h(1796)=1281 */ {1796, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(432)=1283 */ {432, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1283_l1}, +/*h(2029)=1284 */ {2029, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1284_l1}, +/*h(1652)=1285 */ {1652, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1285_l1}, +/*h(665)=1286 */ {665, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1286_l1}, +/*h(1275)=1287 */ {1275, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1287_l1}, +/*h(898)=1288 */ {898, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1288_l1}, +/*h(1508)=1289 */ {1508, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1289_l1}, +/*h(521)=1290 */ {521, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1290_l1}, +/*h(1131)=1291 */ {1131, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1291_l1}, +/*h(754)=1292 */ {754, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1292_l1}, +/*h(1364)=1293 */ {1364, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1293_l1}, +/*h(377)=1294 */ {377, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1294_l1}, +/*h(987)=1295 */ {987, xed3_phash_find_maplegacy_map0_opcode0xd9_vv0_1295_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 1296ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xda_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[194] = { +/*h(0)=0 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {0, 95}, +/*empty slot1 */ {0,0}, +/*h(34)=2 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {34, 97}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(68)=5 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {68, 99}, +/*empty slot1 */ {0,0}, +/*h(102)=7 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {102, 101}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(81)=11 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {81, 111}, +/*empty slot1 */ {0,0}, +/*h(26)=13 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {26, 105}, +/*h(115)=14 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {115, 112}, +/*h(60)=15 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {60, 107}, +/*empty slot1 */ {0,0}, +/*h(5)=17 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {5, 113}, +/*h(94)=18 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {94, 109}, +/*empty slot1 */ {0,0}, +/*h(39)=20 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {39, 114}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(18)=24 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {18, 97}, +/*empty slot1 */ {0,0}, +/*h(52)=26 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {52, 99}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=29 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {86, 101}, +/*empty slot1 */ {0,0}, +/*h(120)=31 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {120, 103}, +/*empty slot1 */ {0,0}, +/*h(65)=33 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {65, 111}, +/*h(10)=34 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {10, 105}, +/*h(99)=35 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {99, 112}, +/*empty slot1 */ {0,0}, +/*h(44)=37 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {44, 107}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=40 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {78, 109}, +/*h(23)=41 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {23, 114}, +/*h(112)=42 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {112, 95}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=45 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {2, 97}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(36)=48 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {36, 99}, +/*empty slot1 */ {0,0}, +/*h(70)=50 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {70, 101}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(104)=53 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {104, 103}, +/*empty slot1 */ {0,0}, +/*h(49)=55 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {49, 111}, +/*empty slot1 */ {0,0}, +/*h(83)=57 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {83, 112}, +/*empty slot1 */ {0,0}, +/*h(28)=59 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {28, 107}, +/*h(117)=60 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {117, 113}, +/*h(62)=61 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {62, 109}, +/*empty slot1 */ {0,0}, +/*h(7)=63 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {7, 114}, +/*h(96)=64 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {96, 95}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=69 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 99}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(54)=72 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {54, 101}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=75 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {88, 103}, +/*h(33)=76 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {33, 111}, +/*h(122)=77 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {122, 105}, +/*empty slot1 */ {0,0}, +/*h(67)=79 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {67, 112}, +/*h(12)=80 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12, 107}, +/*h(101)=81 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {101, 113}, +/*empty slot1 */ {0,0}, +/*h(46)=83 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {46, 109}, +/*empty slot1 */ {0,0}, +/*h(80)=85 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {80, 95}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(114)=88 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {114, 97}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(4)=91 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {4, 99}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(38)=94 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {38, 101}, +/*empty slot1 */ {0,0}, +/*h(72)=96 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {72, 103}, +/*empty slot1 */ {0,0}, +/*h(17)=98 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {17, 111}, +/*h(106)=99 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {106, 105}, +/*h(51)=100 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {51, 112}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(85)=103 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {85, 113}, +/*h(30)=104 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {30, 109}, +/*h(119)=105 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {119, 114}, +/*empty slot1 */ {0,0}, +/*h(64)=107 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {64, 95}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(98)=110 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {98, 97}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=115 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {22, 101}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=118 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {56, 103}, +/*h(1)=119 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1, 111}, +/*h(90)=120 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {90, 105}, +/*empty slot1 */ {0,0}, +/*h(35)=122 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {35, 112}, +/*h(124)=123 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {124, 107}, +/*empty slot1 */ {0,0}, +/*h(69)=125 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {69, 113}, +/*h(14)=126 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14, 109}, +/*h(103)=127 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {103, 114}, +/*empty slot1 */ {0,0}, +/*h(48)=129 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {48, 95}, +/*empty slot1 */ {0,0}, +/*h(82)=131 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {82, 97}, +/*empty slot1 */ {0,0}, +/*h(27)=133 0xDA MOD[0b11] MOD=3 REG[0b101] RM[0b001]*/ {27, 115}, +/*h(116)=134 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {116, 99}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(6)=137 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {6, 101}, +/*empty slot1 */ {0,0}, +/*h(40)=139 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {40, 103}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=142 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {74, 105}, +/*empty slot1 */ {0,0}, +/*h(19)=144 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {19, 112}, +/*h(108)=145 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {108, 107}, +/*h(53)=146 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {53, 113}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(87)=149 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {87, 114}, +/*h(32)=150 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {32, 95}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(66)=153 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {66, 97}, +/*empty slot1 */ {0,0}, +/*h(100)=155 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {100, 99}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=161 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {24, 103}, +/*h(113)=162 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {113, 111}, +/*empty slot1 */ {0,0}, +/*h(58)=164 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {58, 105}, +/*h(3)=165 0xDA MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {3, 112}, +/*h(92)=166 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {92, 107}, +/*empty slot1 */ {0,0}, +/*h(37)=168 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {37, 113}, +/*h(126)=169 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {126, 109}, +/*h(71)=170 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {71, 114}, +/*empty slot1 */ {0,0}, +/*h(16)=172 0xDA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {16, 95}, +/*empty slot1 */ {0,0}, +/*h(50)=174 0xDA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {50, 97}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(84)=177 0xDA MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {84, 99}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(118)=180 0xDA MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {118, 101}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=183 0xDA MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8, 103}, +/*h(97)=184 0xDA MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {97, 111}, +/*h(42)=185 0xDA MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {42, 105}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=188 0xDA MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {76, 107}, +/*h(21)=189 0xDA MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {21, 113}, +/*h(110)=190 0xDA MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {110, 109}, +/*empty slot1 */ {0,0}, +/*h(55)=192 0xDA MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {55, 114}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 194ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[192] = { +/*h(0)=0 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {0, 116}, +/*empty slot1 */ {0,0}, +/*h(34)=2 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {34, 119}, +/*h(123)=3 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {123, 136}, +/*empty slot1 */ {0,0}, +/*h(68)=5 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {68, 122}, +/*h(13)=6 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {13, 137}, +/*h(102)=7 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {102, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(81)=11 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {81, 127}, +/*empty slot1 */ {0,0}, +/*h(26)=13 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {26, 36}, +/*h(115)=14 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {115, 128}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5)=17 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {5, 129}, +/*h(94)=18 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {94, 42}, +/*h(39)=19 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {39, 130}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=22 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100]*/ {73, 133}, +/*h(18)=23 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {18, 119}, +/*h(107)=24 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {107, 136}, +/*empty slot1 */ {0,0}, +/*h(52)=26 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {52, 122}, +/*empty slot1 */ {0,0}, +/*h(86)=28 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {86, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(65)=33 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {65, 127}, +/*h(10)=34 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {10, 36}, +/*h(99)=35 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {99, 128}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=39 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {78, 42}, +/*empty slot1 */ {0,0}, +/*h(23)=41 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {23, 130}, +/*h(112)=42 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {112, 116}, +/*h(57)=43 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b011]*/ {57, 132}, +/*empty slot1 */ {0,0}, +/*h(2)=45 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {2, 119}, +/*h(91)=46 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {91, 136}, +/*h(36)=47 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {36, 122}, +/*h(125)=48 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {125, 137}, +/*empty slot1 */ {0,0}, +/*h(70)=50 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {70, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(49)=54 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {49, 127}, +/*empty slot1 */ {0,0}, +/*h(83)=56 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {83, 128}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(117)=59 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {117, 129}, +/*empty slot1 */ {0,0}, +/*h(62)=61 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {62, 42}, +/*h(7)=62 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {7, 130}, +/*h(96)=63 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {96, 116}, +/*empty slot1 */ {0,0}, +/*h(41)=65 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b010]*/ {41, 131}, +/*empty slot1 */ {0,0}, +/*h(75)=67 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {75, 136}, +/*empty slot1 */ {0,0}, +/*h(20)=69 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 122}, +/*h(109)=70 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {109, 137}, +/*h(54)=71 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {54, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(33)=75 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {33, 127}, +/*h(122)=76 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {122, 36}, +/*empty slot1 */ {0,0}, +/*h(67)=78 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {67, 128}, +/*empty slot1 */ {0,0}, +/*h(101)=80 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {101, 129}, +/*empty slot1 */ {0,0}, +/*h(46)=82 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {46, 42}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(80)=85 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {80, 116}, +/*h(25)=86 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001]*/ {25, 135}, +/*h(114)=87 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {114, 119}, +/*empty slot1 */ {0,0}, +/*h(59)=89 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {59, 136}, +/*h(4)=90 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {4, 122}, +/*h(93)=91 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {93, 137}, +/*empty slot1 */ {0,0}, +/*h(38)=93 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {38, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(17)=97 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {17, 127}, +/*h(106)=98 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {106, 36}, +/*h(51)=99 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {51, 128}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(85)=102 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {85, 129}, +/*h(30)=103 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {30, 42}, +/*h(119)=104 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {119, 130}, +/*empty slot1 */ {0,0}, +/*h(64)=106 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {64, 116}, +/*h(9)=107 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {9, 134}, +/*h(98)=108 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {98, 119}, +/*empty slot1 */ {0,0}, +/*h(43)=110 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {43, 136}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=113 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {77, 137}, +/*h(22)=114 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {22, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=118 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1, 127}, +/*h(90)=119 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {90, 36}, +/*empty slot1 */ {0,0}, +/*h(35)=121 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {35, 128}, +/*empty slot1 */ {0,0}, +/*h(69)=123 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {69, 129}, +/*empty slot1 */ {0,0}, +/*h(14)=125 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14, 42}, +/*h(103)=126 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {103, 130}, +/*h(48)=127 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {48, 116}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(82)=130 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {82, 119}, +/*h(27)=131 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {27, 136}, +/*h(116)=132 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {116, 122}, +/*empty slot1 */ {0,0}, +/*h(61)=134 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {61, 137}, +/*h(6)=135 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {6, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=141 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {74, 36}, +/*h(19)=142 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {19, 128}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(53)=145 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {53, 129}, +/*empty slot1 */ {0,0}, +/*h(87)=147 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {87, 130}, +/*empty slot1 */ {0,0}, +/*h(32)=149 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {32, 116}, +/*empty slot1 */ {0,0}, +/*h(66)=151 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {66, 119}, +/*empty slot1 */ {0,0}, +/*h(11)=153 0xDB MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {11, 136}, +/*h(100)=154 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {100, 122}, +/*h(45)=155 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {45, 137}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(113)=160 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {113, 127}, +/*empty slot1 */ {0,0}, +/*h(58)=162 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {58, 36}, +/*h(3)=163 0xDB MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {3, 128}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(37)=166 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {37, 129}, +/*h(126)=167 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {126, 42}, +/*empty slot1 */ {0,0}, +/*h(71)=169 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {71, 130}, +/*h(16)=170 0xDB MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {16, 116}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(50)=173 0xDB MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {50, 119}, +/*empty slot1 */ {0,0}, +/*h(84)=175 0xDB MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {84, 122}, +/*empty slot1 */ {0,0}, +/*h(29)=177 0xDB MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {29, 137}, +/*h(118)=178 0xDB MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {118, 124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(97)=182 0xDB MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {97, 127}, +/*h(42)=183 0xDB MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {42, 36}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=187 0xDB MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {21, 129}, +/*h(110)=188 0xDB MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {110, 42}, +/*empty slot1 */ {0,0}, +/*h(55)=190 0xDB MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {55, 130}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 192ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdc_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 0xDC MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {3}, +/*h(1)=1 0xDC MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {4}, +/*h(2)=2 0xDC MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {7}, +/*h(3)=3 0xDC MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {8}, +/*h(4)=4 0xDC MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {31}, +/*h(5)=5 0xDC MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {33}, +/*h(6)=6 0xDC MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {13}, +/*h(7)=7 0xDC MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {11}, +/*h(8)=8 0xDC MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {16}, +/*h(9)=9 0xDC MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {21}, +/*h(10)=10 0xDC MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {20}, +/*h(11)=11 0xDC MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {17}, +/*h(12)=12 0xDC MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {24}, +/*h(13)=13 0xDC MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {29}, +/*h(14)=14 0xDC MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {28}, +/*h(15)=15 0xDC MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {25} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 15) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdd_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[257] = { +/*h(0)=0 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {0, 37}, +/*empty slot1 */ {0,0}, +/*h(172)=2 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {172, 39}, +/*h(1)=3 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1, 154}, +/*empty slot1 */ {0,0}, +/*h(173)=5 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {173, 40}, +/*h(2)=6 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {2, 37}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=9 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {3, 154}, +/*h(89)=10 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {89, 156}, +/*empty slot1 */ {0,0}, +/*h(4)=12 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {4, 37}, +/*empty slot1 */ {0,0}, +/*h(176)=14 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {176, 43}, +/*h(5)=15 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {5, 154}, +/*h(91)=16 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {91, 156}, +/*h(177)=17 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {177, 44}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(178)=20 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {178, 43}, +/*empty slot1 */ {0,0}, +/*h(93)=22 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {93, 156}, +/*h(179)=23 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {179, 44}, +/*h(8)=24 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {8, 37}, +/*empty slot1 */ {0,0}, +/*h(180)=26 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {180, 43}, +/*h(9)=27 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {9, 154}, +/*empty slot1 */ {0,0}, +/*h(181)=29 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {181, 44}, +/*h(10)=30 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {10, 37}, +/*h(96)=31 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {96, 145}, +/*empty slot1 */ {0,0}, +/*h(11)=33 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {11, 154}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=36 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {12, 37}, +/*h(98)=37 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {98, 149}, +/*h(184)=38 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {184, 43}, +/*h(13)=39 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {13, 154}, +/*empty slot1 */ {0,0}, +/*h(185)=41 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {185, 44}, +/*empty slot1 */ {0,0}, +/*h(100)=43 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {100, 151}, +/*h(186)=44 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {186, 43}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(187)=47 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {187, 44}, +/*h(16)=48 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {16, 120}, +/*empty slot1 */ {0,0}, +/*h(188)=50 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {188, 43}, +/*h(17)=51 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {17, 66}, +/*empty slot1 */ {0,0}, +/*h(189)=53 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {189, 44}, +/*h(18)=54 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {18, 120}, +/*h(104)=55 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {104, 148}, +/*empty slot1 */ {0,0}, +/*h(19)=57 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {19, 66}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=60 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {20, 120}, +/*h(106)=61 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {106, 146}, +/*h(192)=62 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {192, 138}, +/*h(21)=63 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {21, 66}, +/*empty slot1 */ {0,0}, +/*h(193)=65 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {193, 155}, +/*empty slot1 */ {0,0}, +/*h(108)=67 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {108, 147}, +/*h(194)=68 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {194, 142}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(195)=71 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {195, 155}, +/*h(24)=72 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {24, 120}, +/*empty slot1 */ {0,0}, +/*h(196)=74 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {196, 143}, +/*h(25)=75 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {25, 66}, +/*empty slot1 */ {0,0}, +/*h(197)=77 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {197, 155}, +/*h(26)=78 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {26, 120}, +/*h(112)=79 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {112, 152}, +/*empty slot1 */ {0,0}, +/*h(27)=81 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {27, 66}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=84 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {28, 120}, +/*h(114)=85 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {114, 152}, +/*h(200)=86 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {200, 141}, +/*h(29)=87 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {29, 66}, +/*empty slot1 */ {0,0}, +/*h(201)=89 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {201, 155}, +/*empty slot1 */ {0,0}, +/*h(116)=91 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {116, 152}, +/*h(202)=92 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {202, 139}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(203)=95 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {203, 155}, +/*h(32)=96 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {32, 39}, +/*empty slot1 */ {0,0}, +/*h(204)=98 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 rexw_prefix MODRM()*/ {204, 143}, +/*h(33)=99 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {33, 40}, +/*empty slot1 */ {0,0}, +/*h(205)=101 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {205, 155}, +/*h(34)=102 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {34, 39}, +/*h(120)=103 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {120, 152}, +/*empty slot1 */ {0,0}, +/*h(35)=105 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {35, 40}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(36)=108 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {36, 39}, +/*h(122)=109 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {122, 152}, +/*empty slot1 */ {0,0}, +/*h(37)=111 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {37, 40}, +/*empty slot1 */ {0,0}, +/*h(209)=113 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {209, 156}, +/*empty slot1 */ {0,0}, +/*h(124)=115 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {124, 152}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(211)=119 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {211, 156}, +/*h(40)=120 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {40, 39}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=123 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {41, 40}, +/*empty slot1 */ {0,0}, +/*h(213)=125 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {213, 156}, +/*h(42)=126 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {42, 39}, +/*h(128)=127 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {128, 37}, +/*empty slot1 */ {0,0}, +/*h(43)=129 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {43, 40}, +/*h(129)=130 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {129, 154}, +/*empty slot1 */ {0,0}, +/*h(44)=132 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {44, 39}, +/*h(130)=133 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {130, 37}, +/*empty slot1 */ {0,0}, +/*h(45)=135 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {45, 40}, +/*h(131)=136 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {131, 154}, +/*h(217)=137 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {217, 156}, +/*empty slot1 */ {0,0}, +/*h(132)=139 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {132, 37}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(133)=142 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {133, 154}, +/*h(219)=143 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {219, 156}, +/*h(48)=144 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {48, 43}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(49)=147 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {49, 44}, +/*empty slot1 */ {0,0}, +/*h(221)=149 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {221, 156}, +/*h(50)=150 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {50, 43}, +/*h(136)=151 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {136, 37}, +/*empty slot1 */ {0,0}, +/*h(51)=153 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {51, 44}, +/*h(137)=154 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {137, 154}, +/*empty slot1 */ {0,0}, +/*h(52)=156 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {52, 43}, +/*h(138)=157 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {138, 37}, +/*h(224)=158 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 no66_prefix MODRM()*/ {224, 145}, +/*h(53)=159 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {53, 44}, +/*h(139)=160 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {139, 154}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(140)=163 0xDD MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {140, 37}, +/*h(226)=164 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 no66_prefix MODRM()*/ {226, 149}, +/*empty slot1 */ {0,0}, +/*h(141)=166 0xDD MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {141, 154}, +/*empty slot1 */ {0,0}, +/*h(56)=168 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {56, 43}, +/*empty slot1 */ {0,0}, +/*h(228)=170 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {228, 150}, +/*h(57)=171 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {57, 44}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=174 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {58, 43}, +/*h(144)=175 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {144, 120}, +/*empty slot1 */ {0,0}, +/*h(59)=177 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {59, 44}, +/*h(145)=178 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {145, 66}, +/*empty slot1 */ {0,0}, +/*h(60)=180 0xDD MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {60, 43}, +/*h(146)=181 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {146, 120}, +/*h(232)=182 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode16 66_prefix MODRM()*/ {232, 148}, +/*h(61)=183 0xDD MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {61, 44}, +/*h(147)=184 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {147, 66}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(148)=187 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {148, 120}, +/*h(234)=188 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode32 66_prefix MODRM()*/ {234, 146}, +/*empty slot1 */ {0,0}, +/*h(149)=190 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {149, 66}, +/*empty slot1 */ {0,0}, +/*h(64)=192 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 no66_prefix MODRM()*/ {64, 138}, +/*empty slot1 */ {0,0}, +/*h(236)=194 0xDD MOD[mm] MOD!=3 REG[0b110] RM[nnn] mode64 rexw_prefix MODRM()*/ {236, 150}, +/*h(65)=195 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {65, 155}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(66)=198 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 no66_prefix MODRM()*/ {66, 142}, +/*h(152)=199 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {152, 120}, +/*empty slot1 */ {0,0}, +/*h(67)=201 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {67, 155}, +/*h(153)=202 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {153, 66}, +/*empty slot1 */ {0,0}, +/*h(68)=204 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix no66_prefix MODRM()*/ {68, 144}, +/*h(154)=205 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {154, 120}, +/*h(240)=206 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {240, 152}, +/*h(69)=207 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {69, 155}, +/*h(155)=208 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {155, 66}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(156)=211 0xDD MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {156, 120}, +/*h(242)=212 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {242, 152}, +/*empty slot1 */ {0,0}, +/*h(157)=214 0xDD MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {157, 66}, +/*empty slot1 */ {0,0}, +/*h(72)=216 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode16 66_prefix MODRM()*/ {72, 141}, +/*empty slot1 */ {0,0}, +/*h(244)=218 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {244, 152}, +/*h(73)=219 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {73, 155}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=222 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode32 66_prefix MODRM()*/ {74, 139}, +/*h(160)=223 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {160, 39}, +/*empty slot1 */ {0,0}, +/*h(75)=225 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {75, 155}, +/*h(161)=226 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {161, 40}, +/*empty slot1 */ {0,0}, +/*h(76)=228 0xDD MOD[mm] MOD!=3 REG[0b100] RM[nnn] mode64 norexw_prefix 66_prefix MODRM()*/ {76, 140}, +/*h(162)=229 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {162, 39}, +/*h(248)=230 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {248, 152}, +/*h(77)=231 0xDD MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {77, 155}, +/*h(163)=232 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {163, 40}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(164)=235 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {164, 39}, +/*h(250)=236 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {250, 152}, +/*empty slot1 */ {0,0}, +/*h(165)=238 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {165, 40}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(252)=242 0xDD MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {252, 152}, +/*h(81)=243 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {81, 156}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(168)=247 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {168, 39}, +/*empty slot1 */ {0,0}, +/*h(83)=249 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {83, 156}, +/*h(169)=250 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {169, 40}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(170)=253 0xDD MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {170, 39}, +/*empty slot1 */ {0,0}, +/*h(85)=255 0xDD MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {85, 156}, +/*h(171)=256 0xDD MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {171, 40} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_OSZ_REG_REXW(d); +hidx = (3*key % 257); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xde_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[206] = { +/*h(0)=0 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {0, 96}, +/*h(89)=1 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {89, 160}, +/*h(34)=2 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {34, 98}, +/*h(123)=3 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {123, 161}, +/*empty slot1 */ {0,0}, +/*h(68)=5 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {68, 100}, +/*empty slot1 */ {0,0}, +/*h(13)=7 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {13, 162}, +/*h(102)=8 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {102, 102}, +/*h(47)=9 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {47, 163}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(81)=12 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {81, 157}, +/*empty slot1 */ {0,0}, +/*h(26)=14 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {26, 106}, +/*h(115)=15 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {115, 158}, +/*h(60)=16 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {60, 108}, +/*empty slot1 */ {0,0}, +/*h(5)=18 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {5, 12}, +/*h(94)=19 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {94, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=23 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {73, 160}, +/*empty slot1 */ {0,0}, +/*h(18)=25 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {18, 98}, +/*h(107)=26 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {107, 161}, +/*empty slot1 */ {0,0}, +/*h(52)=28 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {52, 100}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=31 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {86, 102}, +/*h(31)=32 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {31, 163}, +/*h(120)=33 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {120, 104}, +/*empty slot1 */ {0,0}, +/*h(65)=35 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {65, 157}, +/*empty slot1 */ {0,0}, +/*h(10)=37 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {10, 106}, +/*h(99)=38 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {99, 158}, +/*h(44)=39 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {44, 108}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=42 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {78, 110}, +/*empty slot1 */ {0,0}, +/*h(23)=44 0xDE MOD[0b11] MOD=3 REG[0b011] RM[0b001]*/ {23, 159}, +/*h(112)=45 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {112, 96}, +/*h(57)=46 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {57, 160}, +/*empty slot1 */ {0,0}, +/*h(2)=48 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {2, 98}, +/*h(91)=49 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {91, 161}, +/*empty slot1 */ {0,0}, +/*h(36)=51 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {36, 100}, +/*h(125)=52 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {125, 162}, +/*empty slot1 */ {0,0}, +/*h(70)=54 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {70, 102}, +/*h(15)=55 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {15, 163}, +/*h(104)=56 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {104, 104}, +/*empty slot1 */ {0,0}, +/*h(49)=58 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {49, 157}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(83)=61 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {83, 158}, +/*h(28)=62 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {28, 108}, +/*h(117)=63 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {117, 12}, +/*empty slot1 */ {0,0}, +/*h(62)=65 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {62, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(96)=68 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {96, 96}, +/*h(41)=69 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {41, 160}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=72 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {75, 161}, +/*empty slot1 */ {0,0}, +/*h(20)=74 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 100}, +/*h(109)=75 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {109, 162}, +/*empty slot1 */ {0,0}, +/*h(54)=77 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {54, 102}, +/*empty slot1 */ {0,0}, +/*h(88)=79 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {88, 104}, +/*empty slot1 */ {0,0}, +/*h(33)=81 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {33, 157}, +/*h(122)=82 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {122, 106}, +/*empty slot1 */ {0,0}, +/*h(67)=84 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {67, 158}, +/*h(12)=85 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12, 108}, +/*h(101)=86 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {101, 12}, +/*empty slot1 */ {0,0}, +/*h(46)=88 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {46, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(80)=91 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {80, 96}, +/*h(25)=92 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {25, 160}, +/*h(114)=93 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {114, 98}, +/*empty slot1 */ {0,0}, +/*h(59)=95 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {59, 161}, +/*empty slot1 */ {0,0}, +/*h(4)=97 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {4, 100}, +/*h(93)=98 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {93, 162}, +/*h(38)=99 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {38, 102}, +/*empty slot1 */ {0,0}, +/*h(127)=101 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {127, 163}, +/*h(72)=102 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {72, 104}, +/*empty slot1 */ {0,0}, +/*h(17)=104 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {17, 157}, +/*h(106)=105 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {106, 106}, +/*empty slot1 */ {0,0}, +/*h(51)=107 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {51, 158}, +/*empty slot1 */ {0,0}, +/*h(85)=109 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {85, 12}, +/*empty slot1 */ {0,0}, +/*h(30)=111 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {30, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(64)=114 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {64, 96}, +/*h(9)=115 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {9, 160}, +/*h(98)=116 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {98, 98}, +/*empty slot1 */ {0,0}, +/*h(43)=118 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {43, 161}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=121 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {77, 162}, +/*h(22)=122 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {22, 102}, +/*h(111)=123 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {111, 163}, +/*empty slot1 */ {0,0}, +/*h(56)=125 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {56, 104}, +/*empty slot1 */ {0,0}, +/*h(1)=127 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1, 157}, +/*h(90)=128 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {90, 106}, +/*empty slot1 */ {0,0}, +/*h(35)=130 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {35, 158}, +/*h(124)=131 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {124, 108}, +/*h(69)=132 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {69, 12}, +/*empty slot1 */ {0,0}, +/*h(14)=134 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(48)=137 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {48, 96}, +/*empty slot1 */ {0,0}, +/*h(82)=139 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {82, 98}, +/*empty slot1 */ {0,0}, +/*h(27)=141 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {27, 161}, +/*h(116)=142 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {116, 100}, +/*empty slot1 */ {0,0}, +/*h(61)=144 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {61, 162}, +/*h(6)=145 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {6, 102}, +/*h(95)=146 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {95, 163}, +/*empty slot1 */ {0,0}, +/*h(40)=148 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {40, 104}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=151 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {74, 106}, +/*h(19)=152 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {19, 158}, +/*empty slot1 */ {0,0}, +/*h(108)=154 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {108, 108}, +/*h(53)=155 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {53, 12}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(32)=160 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {32, 96}, +/*h(121)=161 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {121, 160}, +/*h(66)=162 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {66, 98}, +/*empty slot1 */ {0,0}, +/*h(11)=164 0xDE MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {11, 161}, +/*h(100)=165 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {100, 100}, +/*empty slot1 */ {0,0}, +/*h(45)=167 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {45, 162}, +/*empty slot1 */ {0,0}, +/*h(79)=169 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {79, 163}, +/*empty slot1 */ {0,0}, +/*h(24)=171 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {24, 104}, +/*h(113)=172 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {113, 157}, +/*empty slot1 */ {0,0}, +/*h(58)=174 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {58, 106}, +/*h(3)=175 0xDE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {3, 158}, +/*h(92)=176 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {92, 108}, +/*empty slot1 */ {0,0}, +/*h(37)=178 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {37, 12}, +/*h(126)=179 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {126, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(16)=183 0xDE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {16, 96}, +/*h(105)=184 0xDE MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {105, 160}, +/*h(50)=185 0xDE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {50, 98}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(84)=188 0xDE MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {84, 100}, +/*empty slot1 */ {0,0}, +/*h(29)=190 0xDE MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {29, 162}, +/*h(118)=191 0xDE MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {118, 102}, +/*h(63)=192 0xDE MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {63, 163}, +/*empty slot1 */ {0,0}, +/*h(8)=194 0xDE MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8, 104}, +/*h(97)=195 0xDE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {97, 157}, +/*empty slot1 */ {0,0}, +/*h(42)=197 0xDE MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {42, 106}, +/*empty slot1 */ {0,0}, +/*h(76)=199 0xDE MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {76, 108}, +/*empty slot1 */ {0,0}, +/*h(21)=201 0xDE MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {21, 12}, +/*h(110)=202 0xDE MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {110, 110}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 206ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xdf_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[193] = { +/*h(0)=0 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {0, 117}, +/*empty slot1 */ {0,0}, +/*h(34)=2 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {34, 121}, +/*h(123)=3 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {123, 167}, +/*empty slot1 */ {0,0}, +/*h(68)=5 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {68, 123}, +/*h(13)=6 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {13, 168}, +/*h(102)=7 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {102, 125}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(81)=11 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {81, 166}, +/*empty slot1 */ {0,0}, +/*h(26)=13 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {26, 118}, +/*h(115)=14 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {115, 65}, +/*h(60)=15 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {60, 165}, +/*empty slot1 */ {0,0}, +/*h(5)=17 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {5, 45}, +/*h(94)=18 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {94, 126}, +/*h(39)=19 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {39, 46}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(18)=24 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {18, 121}, +/*h(107)=25 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {107, 167}, +/*h(52)=26 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {52, 123}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=29 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {86, 125}, +/*empty slot1 */ {0,0}, +/*h(120)=31 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {120, 164}, +/*empty slot1 */ {0,0}, +/*h(65)=33 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {65, 166}, +/*h(10)=34 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {10, 118}, +/*h(99)=35 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {99, 65}, +/*empty slot1 */ {0,0}, +/*h(44)=37 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {44, 165}, +/*empty slot1 */ {0,0}, +/*h(78)=39 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {78, 126}, +/*empty slot1 */ {0,0}, +/*h(23)=41 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {23, 46}, +/*h(112)=42 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {112, 117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=45 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {2, 121}, +/*h(91)=46 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {91, 167}, +/*empty slot1 */ {0,0}, +/*h(36)=48 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {36, 123}, +/*h(125)=49 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {125, 168}, +/*h(70)=50 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {70, 125}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(104)=53 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {104, 164}, +/*h(49)=54 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {49, 166}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(83)=57 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {83, 65}, +/*h(28)=58 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {28, 165}, +/*h(117)=59 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {117, 45}, +/*empty slot1 */ {0,0}, +/*h(62)=61 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {62, 126}, +/*h(7)=62 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {7, 46}, +/*h(96)=63 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {96, 117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=68 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {75, 167}, +/*h(20)=69 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 123}, +/*h(109)=70 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {109, 168}, +/*empty slot1 */ {0,0}, +/*h(54)=72 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {54, 125}, +/*empty slot1 */ {0,0}, +/*h(88)=74 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {88, 164}, +/*empty slot1 */ {0,0}, +/*h(33)=76 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {33, 166}, +/*h(122)=77 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {122, 118}, +/*h(67)=78 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {67, 65}, +/*empty slot1 */ {0,0}, +/*h(12)=80 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {12, 165}, +/*h(101)=81 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {101, 45}, +/*h(46)=82 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {46, 126}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(80)=85 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {80, 117}, +/*empty slot1 */ {0,0}, +/*h(114)=87 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {114, 121}, +/*empty slot1 */ {0,0}, +/*h(59)=89 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {59, 167}, +/*empty slot1 */ {0,0}, +/*h(4)=91 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {4, 123}, +/*h(93)=92 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {93, 168}, +/*h(38)=93 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {38, 125}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(72)=96 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {72, 164}, +/*h(17)=97 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {17, 166}, +/*h(106)=98 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {106, 118}, +/*empty slot1 */ {0,0}, +/*h(51)=100 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {51, 65}, +/*empty slot1 */ {0,0}, +/*h(85)=102 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {85, 45}, +/*empty slot1 */ {0,0}, +/*h(30)=104 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {30, 126}, +/*h(119)=105 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {119, 46}, +/*h(64)=106 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {64, 117}, +/*empty slot1 */ {0,0}, +/*h(9)=108 0xDF MOD[0b11] MOD=3 REG[0b100] RM[0b000]*/ {9, 153}, +/*h(98)=109 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {98, 121}, +/*empty slot1 */ {0,0}, +/*h(43)=111 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {43, 167}, +/*empty slot1 */ {0,0}, +/*h(77)=113 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {77, 168}, +/*empty slot1 */ {0,0}, +/*h(22)=115 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {22, 125}, +/*empty slot1 */ {0,0}, +/*h(56)=117 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {56, 164}, +/*empty slot1 */ {0,0}, +/*h(1)=119 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {1, 166}, +/*h(90)=120 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {90, 118}, +/*h(35)=121 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {35, 65}, +/*h(124)=122 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {124, 165}, +/*empty slot1 */ {0,0}, +/*h(69)=124 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {69, 45}, +/*h(14)=125 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {14, 126}, +/*h(103)=126 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {103, 46}, +/*empty slot1 */ {0,0}, +/*h(48)=128 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {48, 117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(82)=131 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {82, 121}, +/*h(27)=132 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {27, 167}, +/*h(116)=133 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {116, 123}, +/*empty slot1 */ {0,0}, +/*h(61)=135 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {61, 168}, +/*h(6)=136 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {6, 125}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(40)=139 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {40, 164}, +/*empty slot1 */ {0,0}, +/*h(74)=141 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {74, 118}, +/*empty slot1 */ {0,0}, +/*h(19)=143 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {19, 65}, +/*h(108)=144 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {108, 165}, +/*h(53)=145 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {53, 45}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(87)=148 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {87, 46}, +/*h(32)=149 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {32, 117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(66)=152 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {66, 121}, +/*empty slot1 */ {0,0}, +/*h(11)=154 0xDF MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {11, 167}, +/*h(100)=155 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {100, 123}, +/*h(45)=156 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {45, 168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=160 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {24, 164}, +/*h(113)=161 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {113, 166}, +/*empty slot1 */ {0,0}, +/*h(58)=163 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {58, 118}, +/*h(3)=164 0xDF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {3, 65}, +/*h(92)=165 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {92, 165}, +/*empty slot1 */ {0,0}, +/*h(37)=167 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {37, 45}, +/*h(126)=168 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {126, 126}, +/*h(71)=169 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {71, 46}, +/*empty slot1 */ {0,0}, +/*h(16)=171 0xDF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM()*/ {16, 117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(50)=174 0xDF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {50, 121}, +/*empty slot1 */ {0,0}, +/*h(84)=176 0xDF MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {84, 123}, +/*empty slot1 */ {0,0}, +/*h(29)=178 0xDF MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {29, 168}, +/*h(118)=179 0xDF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {118, 125}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=182 0xDF MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {8, 164}, +/*h(97)=183 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {97, 166}, +/*h(42)=184 0xDF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {42, 118}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=187 0xDF MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {76, 165}, +/*h(21)=188 0xDF MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {21, 45}, +/*h(110)=189 0xDF MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {110, 126}, +/*empty slot1 */ {0,0}, +/*h(55)=191 0xDF MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {55, 46}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_RM(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 193ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe0_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {0, 1083}, +/*h(5)=1 0xE0 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {5, 1082}, +/*empty slot1 */ {0,0}, +/*h(7)=3 0xE0 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {7, 1088}, +/*empty slot1 */ {0,0}, +/*h(4)=5 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {4, 1083}, +/*empty slot1 */ {0,0}, +/*h(1)=7 0xE0 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {1, 1081}, +/*h(6)=8 0xE0 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {6, 1083}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODEP5_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe1_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {0, 1087}, +/*h(5)=1 0xE1 MODEP5=1 REP=2 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {5, 1084}, +/*empty slot1 */ {0,0}, +/*h(7)=3 0xE1 MODEP5=1 REP=3 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {7, 1086}, +/*empty slot1 */ {0,0}, +/*h(4)=5 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {4, 1087}, +/*empty slot1 */ {0,0}, +/*h(1)=7 0xE1 MODEP5=1 REP=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {1, 1085}, +/*h(6)=8 0xE1 MODEP5=0 DF64() BRDISP8() IMMUNE66_LOOP64()*/ {6, 1087}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODEP5_REP(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe2_vv0(const xed_decoded_inst_t* d) +{ +return 1089; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe3_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*empty slot1 */ {0,0}, +/*h(5)=1 0xE3 eamode16 BRDISP8()*/ {5, 1090}, +/*h(10)=2 0xE3 eamode32 mode64 BRDISP8() FORCE64()*/ {10, 1092}, +/*h(2)=3 0xE3 eamode32 not64 BRDISP8()*/ {2, 1091}, +/*h(7)=4 0xE3 eamode64 BRDISP8() FORCE64()*/ {7, 1093}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=7 0xE3 eamode16 BRDISP8()*/ {9, 1090}, +/*h(1)=8 0xE3 eamode16 BRDISP8()*/ {1, 1090}, +/*h(6)=9 0xE3 eamode32 not64 BRDISP8()*/ {6, 1091}, +/*h(11)=10 0xE3 eamode64 BRDISP8() FORCE64()*/ {11, 1093}, +/*h(3)=11 0xE3 eamode64 BRDISP8() FORCE64()*/ {3, 1093}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MODE(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 13ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe4_vv0(const xed_decoded_inst_t* d) +{ +return 1094; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe5_vv0(const xed_decoded_inst_t* d) +{ +return 1095; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe6_vv0(const xed_decoded_inst_t* d) +{ +return 1098; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe7_vv0(const xed_decoded_inst_t* d) +{ +return 1099; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe8_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0xE8 not64 BRDISPz()*/ {523}, +/*h(1)=1 0xE8 not64 BRDISPz()*/ {523}, +/*h(2)=2 0xE8 mode64 BRDISP32() DF64() FORCE64()*/ {524} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xe9_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0xE9 not64 BRDISPz()*/ {527}, +/*h(1)=1 0xE9 not64 BRDISPz()*/ {527}, +/*h(2)=2 0xE9 mode64 FORCE64() BRDISP32()*/ {528} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xea_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 0xEA not64 BRDISPz() UIMM16()*/ {532}, +/*h(1)=1 0xEA not64 BRDISPz() UIMM16()*/ {532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xeb_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 0xEB not64 BRDISP8()*/ {529}, +/*h(1)=1 0xEB not64 BRDISP8()*/ {529}, +/*h(2)=2 0xEB mode64 FORCE64() BRDISP8()*/ {530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MODE(d); +hidx = key - 0; +if(hidx <= 2) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xec_vv0(const xed_decoded_inst_t* d) +{ +return 1096; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xed_vv0(const xed_decoded_inst_t* d) +{ +return 1097; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xee_vv0(const xed_decoded_inst_t* d) +{ +return 1100; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xef_vv0(const xed_decoded_inst_t* d) +{ +return 1101; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf1_vv0(const xed_decoded_inst_t* d) +{ +return 1102; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf4_vv0(const xed_decoded_inst_t* d) +{ +return 1103; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf5_vv0(const xed_decoded_inst_t* d) +{ +return 1104; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf6_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(0)=0 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8()*/ {459}, +/*h(1)=1 0xF6 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMM8()*/ {459}, +/*h(2)=2 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()*/ {461}, +/*h(3)=3 0xF6 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMM8()*/ {461}, +/*h(4)=4 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8()*/ {460}, +/*h(5)=5 0xF6 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMM8()*/ {460}, +/*h(6)=6 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()*/ {462}, +/*h(7)=7 0xF6 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMM8()*/ {462}, +/*h(8)=8 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix*/ {475}, +/*h(9)=9 0xF6 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix*/ {473}, +/*h(10)=10 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {476}, +/*h(11)=11 0xF6 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {476}, +/*h(12)=12 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix*/ {481}, +/*h(13)=13 0xF6 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix*/ {479}, +/*h(14)=14 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {482}, +/*h(15)=15 0xF6 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {482}, +/*h(16)=16 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {485}, +/*h(17)=17 0xF6 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {485}, +/*h(18)=18 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {486}, +/*h(19)=19 0xF6 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {486}, +/*h(20)=20 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {489}, +/*h(21)=21 0xF6 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {489}, +/*h(22)=22 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {490}, +/*h(23)=23 0xF6 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {490}, +/*h(24)=24 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {499}, +/*h(25)=25 0xF6 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {499}, +/*h(26)=26 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {500}, +/*h(27)=27 0xF6 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {500}, +/*h(28)=28 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {503}, +/*h(29)=29 0xF6 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {503}, +/*h(30)=30 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {504}, +/*h(31)=31 0xF6 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {504} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 31) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf7_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(0)=0 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {463}, +/*h(1)=1 0xF7 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() SIMMz()*/ {463}, +/*h(2)=2 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {465}, +/*h(3)=3 0xF7 MOD[0b11] MOD=3 REG[0b000] RM[nnn] SIMMz()*/ {465}, +/*h(4)=4 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz()*/ {464}, +/*h(5)=5 0xF7 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() SIMMz()*/ {464}, +/*h(6)=6 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()*/ {466}, +/*h(7)=7 0xF7 MOD[0b11] MOD=3 REG[0b001] RM[nnn] SIMMz()*/ {466}, +/*h(8)=8 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() nolock_prefix*/ {477}, +/*h(9)=9 0xF7 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() lock_prefix*/ {474}, +/*h(10)=10 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {478}, +/*h(11)=11 0xF7 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {478}, +/*h(12)=12 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() nolock_prefix*/ {483}, +/*h(13)=13 0xF7 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM() lock_prefix*/ {480}, +/*h(14)=14 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {484}, +/*h(15)=15 0xF7 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {484}, +/*h(16)=16 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {487}, +/*h(17)=17 0xF7 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {487}, +/*h(18)=18 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {488}, +/*h(19)=19 0xF7 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {488}, +/*h(20)=20 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {491}, +/*h(21)=21 0xF7 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {491}, +/*h(22)=22 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {492}, +/*h(23)=23 0xF7 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {492}, +/*h(24)=24 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {501}, +/*h(25)=25 0xF7 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {501}, +/*h(26)=26 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {502}, +/*h(27)=27 0xF7 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {502}, +/*h(28)=28 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {505}, +/*h(29)=29 0xF7 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {505}, +/*h(30)=30 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {506}, +/*h(31)=31 0xF7 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {506} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 31) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf8_vv0(const xed_decoded_inst_t* d) +{ +return 1105; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xf9_vv0(const xed_decoded_inst_t* d) +{ +return 1106; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfa_vv0(const xed_decoded_inst_t* d) +{ +return 1107; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfb_vv0(const xed_decoded_inst_t* d) +{ +return 1108; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfc_vv0(const xed_decoded_inst_t* d) +{ +return 1109; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfd_vv0(const xed_decoded_inst_t* d) +{ +return 1110; +(void)d; +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xfe_vv0(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix*/ {509}, +/*h(1)=1 0xFE MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix*/ {507}, +/*h(2)=2 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {510}, +/*h(3)=3 0xFE MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {510}, +/*h(4)=4 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix*/ {516}, +/*h(5)=5 0xFE MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix*/ {514}, +/*h(6)=6 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {517}, +/*h(7)=7 0xFE MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {517} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = key - 0; +if(hidx <= 7) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_maplegacy_map0_opcode0xff_vv0(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() nolock_prefix*/ {0, 511}, +/*h(13)=1 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {13, 920}, +/*h(26)=2 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64()*/ {26, 534}, +/*h(5)=3 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() lock_prefix*/ {5, 515}, +/*h(18)=4 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK()*/ {18, 526}, +/*empty slot1 */ {0,0}, +/*h(10)=6 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK()*/ {10, 522}, +/*empty slot1 */ {0,0}, +/*h(2)=8 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {2, 512}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(7)=11 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {7, 519}, +/*h(20)=12 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {20, 531}, +/*empty slot1 */ {0,0}, +/*h(12)=14 0xFF MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {12, 920}, +/*h(25)=15 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM()*/ {25, 533}, +/*h(4)=16 0xFF MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() nolock_prefix*/ {4, 518}, +/*h(17)=17 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK()*/ {17, 525}, +/*empty slot1 */ {0,0}, +/*h(9)=19 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK()*/ {9, 521}, +/*empty slot1 */ {0,0}, +/*h(1)=21 0xFF MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() lock_prefix*/ {1, 508}, +/*empty slot1 */ {0,0}, +/*h(27)=23 0xFF MOD[0b11] MOD=3 REG[0b110] RM[nnn] DF64()*/ {27, 534}, +/*h(6)=24 0xFF MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {6, 519}, +/*h(19)=25 0xFF MOD[0b11] MOD=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK()*/ {19, 526}, +/*empty slot1 */ {0,0}, +/*h(11)=27 0xFF MOD[0b11] MOD=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() CET_NO_TRACK()*/ {11, 522}, +/*h(24)=28 0xFF MOD[mm] MOD!=3 REG[0b110] RM[nnn] DF64() MODRM()*/ {24, 533}, +/*h(3)=29 0xFF MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {3, 512}, +/*h(16)=30 0xFF MOD[mm] MOD!=3 REG[0b100] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK()*/ {16, 525}, +/*empty slot1 */ {0,0}, +/*h(8)=32 0xFF MOD[mm] MOD!=3 REG[0b010] RM[nnn] DF64() IMMUNE66_LOOP64() MODRM() CET_NO_TRACK()*/ {8, 521}, +/*h(21)=33 0xFF MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {21, 531} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_LOCK_MOD3_REG(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-vv1.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv1.h new file mode 100644 index 0000000..249de1c --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv1.h @@ -0,0 +1,9028 @@ +/// @file include-private/xed3-phash-vv1.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_VV1_H) +# define INCLUDE_PRIVATE_XED3_PHASH_VV1_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-operand-lu.h" +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x0_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x4_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xc_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xd_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xe_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x13_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x16_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x17_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x18_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x19_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x20_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x21_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x22_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x23_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x24_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x25_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x28_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x29_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x30_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x31_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x32_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x33_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x34_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x35_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x36_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x37_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x38_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x39_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x40_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x41_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x45_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x46_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x47_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x49_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x4b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x50_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x51_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x52_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x53_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x58_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x59_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x78_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x79_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x8c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x8e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x90_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x91_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x92_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x93_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x96_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x97_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x98_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x99_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xaa_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xab_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xac_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xad_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xae_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xaf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xba_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbc_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbd_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbe_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xcf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdc_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdd_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xde_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf3_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x0_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x1_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xa_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xc_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xd_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xe_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x14_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x15_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x16_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x17_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x18_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x19_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x1d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x20_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x21_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x22_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x30_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x31_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x32_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x33_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x38_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x39_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x40_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x41_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x42_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x44_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x46_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x48_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x49_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x60_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x61_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x62_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x63_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x68_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x69_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x78_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x79_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xce_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xcf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xdf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xf0_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x10_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x11_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x12_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x13_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x14_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x15_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x16_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x17_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x28_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x29_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x41_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x42_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x44_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x45_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x46_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x47_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x4a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x4b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x50_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x51_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x52_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x53_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x54_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x55_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x56_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x57_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x58_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x59_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x60_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x61_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x62_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x63_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x64_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x65_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x66_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x67_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x68_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x69_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6a_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6b_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x70_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x71_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x72_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x73_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x74_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x75_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x76_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x77_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7c_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7d_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7e_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7f_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x90_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x91_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x92_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x93_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x98_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x99_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xae_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc4_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd0_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd1_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd3_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd4_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xda_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdc_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdd_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xde_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdf_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe0_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe1_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe3_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe4_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xea_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xeb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xec_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xed_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xee_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xef_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf0_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf1_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf2_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf3_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf4_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf5_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf6_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf7_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf8_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf9_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfa_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfb_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfc_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfd_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfe_vv1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x0_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x00 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3073}, +/*h(2)=1 VV1 0x00 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3071}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x00 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3074}, +/*h(3)=4 VV1 0x00 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3072} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x01 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3017}, +/*h(2)=1 VV1 0x01 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3015}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x01 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3018}, +/*h(3)=4 VV1 0x01 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3016} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x02 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3021}, +/*h(2)=1 VV1 0x02 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3019}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x02 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3022}, +/*h(3)=4 VV1 0x02 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3020} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x03 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3025}, +/*h(2)=1 VV1 0x03 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3023}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x03 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3026}, +/*h(3)=4 VV1 0x03 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3024} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x4_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x04 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3303}, +/*h(2)=1 VV1 0x04 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3301}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x04 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3304}, +/*h(3)=4 VV1 0x04 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3302} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x05 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3029}, +/*h(2)=1 VV1 0x05 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3027}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x05 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3030}, +/*h(3)=4 VV1 0x05 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3028} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x06 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3033}, +/*h(2)=1 VV1 0x06 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3031}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x06 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3034}, +/*h(3)=4 VV1 0x06 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3032} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x07 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3037}, +/*h(2)=1 VV1 0x07 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3035}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x07 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3038}, +/*h(3)=4 VV1 0x07 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3036} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x08 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3077}, +/*h(2)=1 VV1 0x08 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3075}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x08 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3078}, +/*h(3)=4 VV1 0x08 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3076} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x09 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3081}, +/*h(2)=1 VV1 0x09 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3079}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x09 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3082}, +/*h(3)=4 VV1 0x09 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3080} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x0A VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3085}, +/*h(2)=1 VV1 0x0A VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3083}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x0A VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3086}, +/*h(3)=4 VV1 0x0A VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3084} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x0B VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3045}, +/*h(2)=1 VV1 0x0B VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3043}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x0B VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3046}, +/*h(3)=4 VV1 0x0B VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3044} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xc_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2711}, +/*h(20)=1 VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2712}, +/*h(4)=2 VV1 0x0C VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2710}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x0C VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2713} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xd_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2703}, +/*h(20)=1 VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2704}, +/*h(4)=2 VV1 0x0D VL128 V66 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2702}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x0D VL256 V66 V0F38 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2705} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xe_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2745}, +/*h(93)=3 VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 2748}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x0E VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 2747}, +/*h(29)=7 VV1 0x0E VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2746} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2749}, +/*h(93)=3 VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 2752}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x0F VL256 V66 V0F38 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 2751}, +/*h(29)=7 VV1 0x0F VL128 V66 V0F38 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2750} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x13_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x13 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0*/ {28, 3503}, +/*h(93)=3 VV1 0x13 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0*/ {93, 3506}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x13 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() W0*/ {92, 3505}, +/*h(29)=7 VV1 0x13 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0*/ {29, 3504} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x16_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x16 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3739}, +/*h(21)=1 VV1 0x16 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3740} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 20; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x17_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x17 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2744}, +/*h(15)=1 VV1 0x17 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2742}, +/*h(46)=2 VV1 0x17 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2743}, +/*h(14)=3 VV1 0x17 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2741}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x18_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x18 norexw_prefix VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2720}, +/*h(93)=3 VV1 0x18 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 2723}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x18 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 2721}, +/*h(29)=7 VV1 0x18 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2722} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x19_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(92)=0 VV1 0x19 norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2724}, +/*h(93)=1 VV1 0x19 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2725} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 92; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(92)=0 VV1 0x1A norexw_prefix VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2726} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 92; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x1C VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2856}, +/*h(15)=1 VV1 0x1C V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2854}, +/*h(46)=2 VV1 0x1C VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2855}, +/*h(14)=3 VV1 0x1C V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2853}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x1D VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2860}, +/*h(15)=1 VV1 0x1D V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2858}, +/*h(46)=2 VV1 0x1D VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2859}, +/*h(14)=3 VV1 0x1D V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2857}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x1e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x1E VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2864}, +/*h(15)=1 VV1 0x1E V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2862}, +/*h(46)=2 VV1 0x1E VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2863}, +/*h(14)=3 VV1 0x1E V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2861}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x20_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x20 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3369}, +/*h(15)=1 VV1 0x20 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3367}, +/*h(46)=2 VV1 0x20 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3370}, +/*h(14)=3 VV1 0x20 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3368}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x21_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x21 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3373}, +/*h(15)=1 VV1 0x21 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3371}, +/*h(46)=2 VV1 0x21 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3374}, +/*h(14)=3 VV1 0x21 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3372}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x22_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x22 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3377}, +/*h(15)=1 VV1 0x22 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3375}, +/*h(46)=2 VV1 0x22 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3378}, +/*h(14)=3 VV1 0x22 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3376}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x23_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x23 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3381}, +/*h(15)=1 VV1 0x23 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3379}, +/*h(46)=2 VV1 0x23 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3382}, +/*h(14)=3 VV1 0x23 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3380}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x24_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x24 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3385}, +/*h(15)=1 VV1 0x24 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3383}, +/*h(46)=2 VV1 0x24 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3386}, +/*h(14)=3 VV1 0x24 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3384}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x25_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x25 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3389}, +/*h(15)=1 VV1 0x25 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3387}, +/*h(46)=2 VV1 0x25 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3390}, +/*h(14)=3 VV1 0x25 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3388}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x28_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x28 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3065}, +/*h(2)=1 VV1 0x28 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3063}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x28 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3066}, +/*h(3)=4 VV1 0x28 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3064} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x29_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x29 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2997}, +/*h(2)=1 VV1 0x29 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2995}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x29 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2998}, +/*h(3)=4 VV1 0x29 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2996} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(46)=0 VV1 0x2A V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3472}, +/*h(14)=1 VV1 0x2A V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3471} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x2B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2893}, +/*h(2)=1 VV1 0x2B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2891}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x2B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2894}, +/*h(3)=4 VV1 0x2B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2892} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x2C V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2734}, +/*h(4)=1 VV1 0x2C V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2733} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x2D V66 VL256 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2738}, +/*h(4)=1 VV1 0x2D V66 VL128 V0F38 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x2E V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2736}, +/*h(4)=1 VV1 0x2E V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2735} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x2f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x2F V66 V0F38 VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2740}, +/*h(4)=1 VV1 0x2F V66 V0F38 VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2739} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x30_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x30 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3393}, +/*h(15)=1 VV1 0x30 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3391}, +/*h(46)=2 VV1 0x30 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3394}, +/*h(14)=3 VV1 0x30 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3392}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x31_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x31 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3397}, +/*h(15)=1 VV1 0x31 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3395}, +/*h(46)=2 VV1 0x31 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3398}, +/*h(14)=3 VV1 0x31 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3396}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x32_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x32 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3401}, +/*h(15)=1 VV1 0x32 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3399}, +/*h(46)=2 VV1 0x32 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3402}, +/*h(14)=3 VV1 0x32 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3400}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x33_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x33 V66 V0F38 VL256 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3405}, +/*h(15)=1 VV1 0x33 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3403}, +/*h(46)=2 VV1 0x33 V66 V0F38 VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3406}, +/*h(14)=3 VV1 0x33 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3404}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x34_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x34 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3409}, +/*h(15)=1 VV1 0x34 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3407}, +/*h(46)=2 VV1 0x34 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3410}, +/*h(14)=3 VV1 0x34 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3408}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x35_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x35 VL256 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3413}, +/*h(15)=1 VV1 0x35 VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3411}, +/*h(46)=2 VV1 0x35 VL256 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3414}, +/*h(14)=3 VV1 0x35 VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3412}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x36_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {3737}, +/*h(21)=1 VV1 0x36 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {3738} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 20; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x37_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x37 V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3013}, +/*h(2)=1 VV1 0x37 V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3011}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x37 V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3014}, +/*h(3)=4 VV1 0x37 V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3012} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x38_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x38 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3275}, +/*h(2)=1 VV1 0x38 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3273}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x38 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3276}, +/*h(3)=4 VV1 0x38 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3274} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x39_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x39 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3283}, +/*h(2)=1 VV1 0x39 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3281}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x39 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3284}, +/*h(3)=4 VV1 0x39 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3282} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x3A V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3291}, +/*h(2)=1 VV1 0x3A V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3289}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x3A V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3292}, +/*h(3)=4 VV1 0x3A V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3290} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x3B V66 V0F38 VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3295}, +/*h(2)=1 VV1 0x3B V66 V0F38 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3293}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x3B V66 V0F38 VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3296}, +/*h(3)=4 VV1 0x3B V66 V0F38 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3294} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x3C VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3251}, +/*h(2)=1 VV1 0x3C VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3249}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x3C VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3252}, +/*h(3)=4 VV1 0x3C VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3250} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x3D VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3259}, +/*h(2)=1 VV1 0x3D VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3257}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x3D VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3260}, +/*h(3)=4 VV1 0x3D VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3258} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x3E VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3267}, +/*h(2)=1 VV1 0x3E VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3265}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x3E VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3268}, +/*h(3)=4 VV1 0x3E VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3266} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x3f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x3F VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3271}, +/*h(2)=1 VV1 0x3F VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3269}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x3F VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3272}, +/*h(3)=4 VV1 0x3F VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3270} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x40_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x40 VL256 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3057}, +/*h(2)=1 VV1 0x40 VL128 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3055}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x40 VL256 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3058}, +/*h(3)=4 VV1 0x40 VL128 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3056} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x41_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0x41 V66 V0F38 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2865}, +/*h(15)=1 VV1 0x41 V66 V0F38 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2866} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x45_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x45 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3771}, +/*h(23)=1 VV1 0x45 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3777}, +/*h(7)=2 VV1 0x45 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3775}, +/*h(20)=3 VV1 0x45 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3772}, +/*h(4)=4 VV1 0x45 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3770}, +/*h(22)=5 VV1 0x45 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3776}, +/*h(6)=6 VV1 0x45 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3774}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x45 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3773} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x46_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0*/ {5, 3779}, +/*h(20)=1 VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {20, 3780}, +/*h(4)=2 VV1 0x46 V0F38 V66 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0*/ {4, 3778}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x46 V0F38 V66 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3781} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x47_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x47 VL128 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3763}, +/*h(23)=1 VV1 0x47 VL256 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3769}, +/*h(7)=2 VV1 0x47 VL128 V0F38 V66 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3767}, +/*h(20)=3 VV1 0x47 VL256 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3764}, +/*h(4)=4 VV1 0x47 VL128 V0F38 V66 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3762}, +/*h(22)=5 VV1 0x47 VL256 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3768}, +/*h(6)=6 VV1 0x47 VL128 V0F38 V66 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3766}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x47 VL256 V0F38 V66 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3765} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x49_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(3204)=0 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3204, 3957}, +/*h(11317)=1 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11317, 3968}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(7428)=4 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7428, 3958}, +/*h(3076)=5 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3076, 3957}, +/*empty slot1 */ {0,0}, +/*h(11277)=7 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11277, 3968}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11309)=10 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11309, 3968}, +/*empty slot1 */ {0,0}, +/*h(7940)=12 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7940, 3958}, +/*h(3588)=13 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3588, 3957}, +/*empty slot1 */ {0,0}, +/*h(3077)=15 VV1 0x49 VNP V0F38 MOD[0b11] MOD=3 REG[0b000] RM[0b000] VL128 W0 mode64 NOVSR*/ {3077, 3966}, +/*h(11269)=16 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11269, 3968}, +/*h(7812)=17 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7812, 3958}, +/*h(3460)=18 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3460, 3957}, +/*h(11301)=19 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11301, 3968}, +/*h(7300)=20 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7300, 3958}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(7172)=25 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7172, 3958}, +/*h(3972)=26 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3972, 3957}, +/*empty slot1 */ {0,0}, +/*h(11293)=28 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11293, 3968}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3844)=31 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3844, 3957}, +/*empty slot1 */ {0,0}, +/*h(7684)=33 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7684, 3958}, +/*h(3332)=34 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3332, 3957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11285)=37 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11285, 3968}, +/*h(7556)=38 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {7556, 3958}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11325)=42 VV1 0x49 VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[0b000] VL128 W0 mode64 NOVSR*/ {11325, 3968}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8068)=46 VV1 0x49 V66 V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {8068, 3958}, +/*h(3716)=47 VV1 0x49 VNP V0F38 MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 mode64 NOVSR*/ {3716, 3957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REG_REXW_RM_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((10*key % 89) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x4b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(500)=0 VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR*/ {500, 3967}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(244)=4 VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR*/ {244, 3965}, +/*h(372)=5 VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() VL128 W0 mode64 NOVSR*/ {372, 3964} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x50_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0*/ {5, 3941}, +/*h(20)=1 VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {20, 3944}, +/*h(4)=2 VV1 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0*/ {4, 3942}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x50 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3943} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x51_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0*/ {5, 3945}, +/*h(20)=1 VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {20, 3948}, +/*h(4)=2 VV1 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0*/ {4, 3946}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x51 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3947} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x52_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0*/ {5, 3949}, +/*h(20)=1 VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {20, 3952}, +/*h(4)=2 VV1 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0*/ {4, 3950}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x52 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3951} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x53_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0*/ {5, 3953}, +/*h(20)=1 VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {20, 3956}, +/*h(4)=2 VV1 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0*/ {4, 3954}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x53 V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3955} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x58_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3753}, +/*h(93)=3 VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3756}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x58 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3755}, +/*h(29)=7 VV1 0x58 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3754} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x59_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3757}, +/*h(93)=3 VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3760}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x59 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3759}, +/*h(29)=7 VV1 0x59 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3758} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(92)=0 VV1 0x5A VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3761} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 92; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(53)=0 VV1 0x5C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64*/ {3959} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = key - 53; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x5e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(5)=0 VV1 0x5E VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64*/ {5, 3963}, +/*h(21)=1 VV1 0x5E V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64*/ {21, 3962}, +/*h(37)=2 VV1 0x5E VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64*/ {37, 3960}, +/*h(53)=3 VV1 0x5E VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64*/ {53, 3961} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x78_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3745}, +/*h(93)=3 VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3748}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x78 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3747}, +/*h(29)=7 VV1 0x78 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3746} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x79_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3749}, +/*h(93)=3 VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3752}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x79 VL256 V66 V0F38 W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3751}, +/*h(29)=7 VV1 0x79 VL128 V66 V0F38 W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3750} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x8c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=2 VV1 0x8C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3724}, +/*h(4)=3 VV1 0x8C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3723}, +/*h(22)=4 VV1 0x8C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3728}, +/*h(6)=5 VV1 0x8C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3727}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x8e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=2 VV1 0x8E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3726}, +/*h(4)=3 VV1 0x8E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3725}, +/*h(22)=4 VV1 0x8E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3730}, +/*h(6)=5 VV1 0x8E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3729}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x90_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(178)=0 VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {178, 3713}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=6 VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {59, 3712}, +/*h(51)=7 VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {51, 3714}, +/*h(187)=8 VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {187, 3711}, +/*h(179)=9 VV1 0x90 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {179, 3713}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=12 VV1 0x90 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {58, 3712}, +/*h(50)=13 VV1 0x90 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {50, 3714}, +/*h(186)=14 VV1 0x90 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {186, 3711} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x91_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(178)=0 VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {178, 3717}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=6 VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {59, 3716}, +/*h(51)=7 VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {51, 3718}, +/*h(187)=8 VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {187, 3715}, +/*h(179)=9 VV1 0x91 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {179, 3717}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=12 VV1 0x91 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {58, 3716}, +/*h(50)=13 VV1 0x91 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {50, 3718}, +/*h(186)=14 VV1 0x91 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {186, 3715} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x92_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(178)=0 VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {178, 3705}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=6 VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {59, 3704}, +/*h(51)=7 VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {51, 3706}, +/*h(187)=8 VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {187, 3703}, +/*h(179)=9 VV1 0x92 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {179, 3705}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=12 VV1 0x92 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {58, 3704}, +/*h(50)=13 VV1 0x92 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {50, 3706}, +/*h(186)=14 VV1 0x92 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {186, 3703} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x93_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(178)=0 VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {178, 3709}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=6 VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {59, 3708}, +/*h(51)=7 VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {51, 3710}, +/*h(187)=8 VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {187, 3707}, +/*h(179)=9 VV1 0x93 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {179, 3709}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=12 VV1 0x93 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {58, 3708}, +/*h(50)=13 VV1 0x93 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_XMM() eanot16*/ {50, 3710}, +/*h(186)=14 VV1 0x93 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] RM=4 VMODRM_YMM() eanot16*/ {186, 3707} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x96_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x96 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3560}, +/*h(23)=1 VV1 0x96 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3550}, +/*h(7)=2 VV1 0x96 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3548}, +/*h(20)=3 VV1 0x96 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3561}, +/*h(4)=4 VV1 0x96 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3559}, +/*h(22)=5 VV1 0x96 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3549}, +/*h(6)=6 VV1 0x96 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3547}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x96 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3562} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x97_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x97 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3584}, +/*h(23)=1 VV1 0x97 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3574}, +/*h(7)=2 VV1 0x97 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3572}, +/*h(20)=3 VV1 0x97 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3585}, +/*h(4)=4 VV1 0x97 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3583}, +/*h(22)=5 VV1 0x97 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3573}, +/*h(6)=6 VV1 0x97 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3571}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x97 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3586} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x98_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x98 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3516}, +/*h(23)=1 VV1 0x98 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3514}, +/*h(7)=2 VV1 0x98 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3512}, +/*h(20)=3 VV1 0x98 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3517}, +/*h(4)=4 VV1 0x98 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3515}, +/*h(22)=5 VV1 0x98 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3513}, +/*h(6)=6 VV1 0x98 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3511}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x98 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3518} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x99_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x99 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3521}, +/*h(5)=1 VV1 0x99 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3522}, +/*h(6)=2 VV1 0x99 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3519}, +/*h(7)=3 VV1 0x99 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x9A VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3600}, +/*h(23)=1 VV1 0x9A VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3598}, +/*h(7)=2 VV1 0x9A VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3596}, +/*h(20)=3 VV1 0x9A VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3601}, +/*h(4)=4 VV1 0x9A VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3599}, +/*h(22)=5 VV1 0x9A VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3597}, +/*h(6)=6 VV1 0x9A VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3595}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x9A VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3602} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x9B V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3605}, +/*h(5)=1 VV1 0x9B V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3606}, +/*h(6)=2 VV1 0x9B V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3603}, +/*h(7)=3 VV1 0x9B V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3604} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x9C VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3636}, +/*h(23)=1 VV1 0x9C VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3634}, +/*h(7)=2 VV1 0x9C VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3632}, +/*h(20)=3 VV1 0x9C VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3637}, +/*h(4)=4 VV1 0x9C VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3635}, +/*h(22)=5 VV1 0x9C VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3633}, +/*h(6)=6 VV1 0x9C VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3631}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x9C VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3638} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x9D V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3641}, +/*h(5)=1 VV1 0x9D V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3642}, +/*h(6)=2 VV1 0x9D V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3639}, +/*h(7)=3 VV1 0x9D V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3640} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x9E VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3672}, +/*h(23)=1 VV1 0x9E VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3670}, +/*h(7)=2 VV1 0x9E VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3668}, +/*h(20)=3 VV1 0x9E VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3673}, +/*h(4)=4 VV1 0x9E VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3671}, +/*h(22)=5 VV1 0x9E VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3669}, +/*h(6)=6 VV1 0x9E VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3667}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x9E VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3674} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0x9f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x9F V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3677}, +/*h(5)=1 VV1 0x9F V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3678}, +/*h(6)=2 VV1 0x9F V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3675}, +/*h(7)=3 VV1 0x9F V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3676} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xA6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3564}, +/*h(23)=1 VV1 0xA6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3554}, +/*h(7)=2 VV1 0xA6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3552}, +/*h(20)=3 VV1 0xA6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3565}, +/*h(4)=4 VV1 0xA6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3563}, +/*h(22)=5 VV1 0xA6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3553}, +/*h(6)=6 VV1 0xA6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3551}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xA6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3566} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xA7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3588}, +/*h(23)=1 VV1 0xA7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3578}, +/*h(7)=2 VV1 0xA7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3576}, +/*h(20)=3 VV1 0xA7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3589}, +/*h(4)=4 VV1 0xA7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3587}, +/*h(22)=5 VV1 0xA7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3577}, +/*h(6)=6 VV1 0xA7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3575}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xA7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3590} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xA8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3528}, +/*h(23)=1 VV1 0xA8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3526}, +/*h(7)=2 VV1 0xA8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3524}, +/*h(20)=3 VV1 0xA8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3529}, +/*h(4)=4 VV1 0xA8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3527}, +/*h(22)=5 VV1 0xA8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3525}, +/*h(6)=6 VV1 0xA8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3523}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xA8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3530} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xa9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xA9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3533}, +/*h(5)=1 VV1 0xA9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3534}, +/*h(6)=2 VV1 0xA9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3531}, +/*h(7)=3 VV1 0xA9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xaa_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xAA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3612}, +/*h(23)=1 VV1 0xAA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3610}, +/*h(7)=2 VV1 0xAA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3608}, +/*h(20)=3 VV1 0xAA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3613}, +/*h(4)=4 VV1 0xAA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3611}, +/*h(22)=5 VV1 0xAA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3609}, +/*h(6)=6 VV1 0xAA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3607}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xAA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3614} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xab_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xAB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3617}, +/*h(5)=1 VV1 0xAB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3618}, +/*h(6)=2 VV1 0xAB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3615}, +/*h(7)=3 VV1 0xAB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3616} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xac_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xAC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3648}, +/*h(23)=1 VV1 0xAC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3646}, +/*h(7)=2 VV1 0xAC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3644}, +/*h(20)=3 VV1 0xAC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3649}, +/*h(4)=4 VV1 0xAC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3647}, +/*h(22)=5 VV1 0xAC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3645}, +/*h(6)=6 VV1 0xAC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3643}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xAC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3650} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xad_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xAD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3653}, +/*h(5)=1 VV1 0xAD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3654}, +/*h(6)=2 VV1 0xAD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3651}, +/*h(7)=3 VV1 0xAD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3652} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xae_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xAE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3684}, +/*h(23)=1 VV1 0xAE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3682}, +/*h(7)=2 VV1 0xAE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3680}, +/*h(20)=3 VV1 0xAE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3685}, +/*h(4)=4 VV1 0xAE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3683}, +/*h(22)=5 VV1 0xAE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3681}, +/*h(6)=6 VV1 0xAE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3679}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xAE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3686} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xaf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xAF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3689}, +/*h(5)=1 VV1 0xAF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3690}, +/*h(6)=2 VV1 0xAF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3687}, +/*h(7)=3 VV1 0xAF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3688} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xB6 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3568}, +/*h(23)=1 VV1 0xB6 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3558}, +/*h(7)=2 VV1 0xB6 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3556}, +/*h(20)=3 VV1 0xB6 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3569}, +/*h(4)=4 VV1 0xB6 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3567}, +/*h(22)=5 VV1 0xB6 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3557}, +/*h(6)=6 VV1 0xB6 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3555}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xB6 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3570} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xB7 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3592}, +/*h(23)=1 VV1 0xB7 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3582}, +/*h(7)=2 VV1 0xB7 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3580}, +/*h(20)=3 VV1 0xB7 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3593}, +/*h(4)=4 VV1 0xB7 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3591}, +/*h(22)=5 VV1 0xB7 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3581}, +/*h(6)=6 VV1 0xB7 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3579}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xB7 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3594} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xB8 VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3540}, +/*h(23)=1 VV1 0xB8 VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3538}, +/*h(7)=2 VV1 0xB8 VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3536}, +/*h(20)=3 VV1 0xB8 VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3541}, +/*h(4)=4 VV1 0xB8 VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3539}, +/*h(22)=5 VV1 0xB8 VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3537}, +/*h(6)=6 VV1 0xB8 VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3535}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xB8 VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3542} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xb9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xB9 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3545}, +/*h(5)=1 VV1 0xB9 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3546}, +/*h(6)=2 VV1 0xB9 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3543}, +/*h(7)=3 VV1 0xB9 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3544} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xba_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xBA VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3624}, +/*h(23)=1 VV1 0xBA VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3622}, +/*h(7)=2 VV1 0xBA VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3620}, +/*h(20)=3 VV1 0xBA VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3625}, +/*h(4)=4 VV1 0xBA VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3623}, +/*h(22)=5 VV1 0xBA VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3621}, +/*h(6)=6 VV1 0xBA VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3619}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xBA VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3626} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xBB V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3629}, +/*h(5)=1 VV1 0xBB V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3630}, +/*h(6)=2 VV1 0xBB V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3627}, +/*h(7)=3 VV1 0xBB V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3628} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbc_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xBC VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3660}, +/*h(23)=1 VV1 0xBC VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3658}, +/*h(7)=2 VV1 0xBC VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3656}, +/*h(20)=3 VV1 0xBC VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3661}, +/*h(4)=4 VV1 0xBC VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3659}, +/*h(22)=5 VV1 0xBC VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3657}, +/*h(6)=6 VV1 0xBC VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3655}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xBC VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3662} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbd_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xBD V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3665}, +/*h(5)=1 VV1 0xBD V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3666}, +/*h(6)=2 VV1 0xBD V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3663}, +/*h(7)=3 VV1 0xBD V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3664} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbe_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0xBE VL128 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3696}, +/*h(23)=1 VV1 0xBE VL256 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3694}, +/*h(7)=2 VV1 0xBE VL128 V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3692}, +/*h(20)=3 VV1 0xBE VL256 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3697}, +/*h(4)=4 VV1 0xBE VL128 V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3695}, +/*h(22)=5 VV1 0xBE VL256 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3693}, +/*h(6)=6 VV1 0xBE VL128 V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3691}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0xBE VL256 V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3698} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xbf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0xBF V66 V0F38 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3701}, +/*h(5)=1 VV1 0xBF V66 V0F38 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3702}, +/*h(6)=2 VV1 0xBF V66 V0F38 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3699}, +/*h(7)=3 VV1 0xBF V66 V0F38 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3700} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xcf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0*/ {5, 3937}, +/*h(20)=1 VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0*/ {20, 3940}, +/*h(4)=2 VV1 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0*/ {4, 3938}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0xCF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3939} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0xDB VL128 V66 V0F38 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {3498}, +/*h(15)=1 VV1 0xDB VL128 V66 V0F38 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3497} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdc_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256*/ {10, 3484}, +/*h(2)=1 VV1 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128*/ {2, 3482}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256*/ {11, 3483}, +/*h(3)=4 VV1 0xDC V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128*/ {3, 3481} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdd_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256*/ {10, 3488}, +/*h(2)=1 VV1 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128*/ {2, 3486}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256*/ {11, 3487}, +/*h(3)=4 VV1 0xDD V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128*/ {3, 3485} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xde_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256*/ {10, 3492}, +/*h(2)=1 VV1 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128*/ {2, 3490}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256*/ {11, 3491}, +/*h(3)=4 VV1 0xDE V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128*/ {3, 3489} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xdf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256*/ {10, 3496}, +/*h(2)=1 VV1 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128*/ {2, 3494}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256*/ {11, 3495}, +/*h(3)=4 VV1 0xDF V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128*/ {3, 3493} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3794}, +/*h(8)=1 VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3794}, +/*h(5)=2 VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3797}, +/*h(13)=3 VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 3799}, +/*h(4)=4 VV1 0xF2 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3795}, +/*h(12)=5 VV1 0xF2 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3798}, +/*h(3)=6 VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3796}, +/*h(11)=7 VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3796}, +/*h(2)=8 VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3794}, +/*h(10)=9 VV1 0xF2 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3794}, +/*h(1)=10 VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3796}, +/*h(9)=11 VV1 0xF2 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3796} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = ((10*key % 67) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf3_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[72] = { +/*h(89)=0 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {89, 3814}, +/*h(18)=1 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {18, 3806}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(72)=4 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {72, 3800}, +/*h(90)=5 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {90, 3812}, +/*h(19)=6 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {19, 3808}, +/*empty slot1 */ {0,0}, +/*h(16)=8 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {16, 3806}, +/*h(73)=9 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {73, 3802}, +/*h(91)=10 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {91, 3814}, +/*h(20)=11 VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 3807}, +/*h(88)=12 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {88, 3812}, +/*h(17)=13 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {17, 3808}, +/*h(74)=14 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {74, 3800}, +/*h(92)=15 VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {92, 3816}, +/*h(21)=16 VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {21, 3809}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(75)=19 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {75, 3802}, +/*h(93)=20 VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {93, 3817}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=24 VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {76, 3804}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=29 VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {77, 3805}, +/*empty slot1 */ {0,0}, +/*h(24)=31 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {24, 3812}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(25)=36 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {25, 3814}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=40 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {8, 3800}, +/*h(26)=41 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {26, 3812}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(80)=44 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {80, 3806}, +/*h(9)=45 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {9, 3802}, +/*h(27)=46 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {27, 3814}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(81)=49 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {81, 3808}, +/*h(10)=50 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {10, 3800}, +/*h(28)=51 VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {28, 3813}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(82)=54 VV1 0xF3 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {82, 3806}, +/*h(11)=55 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {11, 3802}, +/*h(29)=56 VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {29, 3815}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(83)=59 VV1 0xF3 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {83, 3808}, +/*h(12)=60 VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {12, 3801}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(84)=64 VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {84, 3810}, +/*h(13)=65 VV1 0xF3 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {13, 3803}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(85)=69 VV1 0xF3 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {85, 3811}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REG_REXW_VEX_PREFIX_VL(d); +hidx = ((5*key % 89) % 72); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3818}, +/*h(45)=1 VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 3787}, +/*empty slot1 */ {0,0}, +/*h(1)=3 VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3820}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=6 VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3818}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=9 VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3820}, +/*h(48)=10 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {48, 3788}, +/*empty slot1 */ {0,0}, +/*h(4)=12 VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3819}, +/*h(49)=13 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 3790}, +/*empty slot1 */ {0,0}, +/*h(5)=15 VV1 0xF5 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3821}, +/*h(50)=16 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {50, 3788}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(51)=19 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 3790}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(52)=22 VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {52, 3789}, +/*empty slot1 */ {0,0}, +/*h(8)=24 VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3818}, +/*h(53)=25 VV1 0xF5 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 3791}, +/*empty slot1 */ {0,0}, +/*h(9)=27 VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3820}, +/*empty slot1 */ {0,0}, +/*h(32)=29 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {32, 3782}, +/*h(10)=30 VV1 0xF5 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3818}, +/*empty slot1 */ {0,0}, +/*h(33)=32 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {33, 3784}, +/*h(11)=33 VV1 0xF5 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3820}, +/*h(56)=34 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 3788}, +/*h(34)=35 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {34, 3782}, +/*h(12)=36 VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3822}, +/*h(57)=37 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3790}, +/*h(35)=38 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {35, 3784}, +/*h(13)=39 VV1 0xF5 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 3823}, +/*h(58)=40 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 3788}, +/*h(36)=41 VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {36, 3783}, +/*empty slot1 */ {0,0}, +/*h(59)=43 VV1 0xF5 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3790}, +/*h(37)=44 VV1 0xF5 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {37, 3785}, +/*empty slot1 */ {0,0}, +/*h(60)=46 VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 3792}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(61)=49 VV1 0xF5 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3793}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(40)=53 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {40, 3782}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=56 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {41, 3784}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(42)=59 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {42, 3782}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=62 VV1 0xF5 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {43, 3784}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=65 VV1 0xF5 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {44, 3786}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(34)=0 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {34, 3850}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=3 VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {44, 3853}, +/*h(36)=4 VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {36, 3851}, +/*empty slot1 */ {0,0}, +/*h(41)=6 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {41, 3848}, +/*h(33)=7 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {33, 3848}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(43)=10 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {43, 3848}, +/*h(35)=11 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {35, 3848}, +/*h(40)=12 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {40, 3850}, +/*h(32)=13 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {32, 3850}, +/*h(45)=14 VV1 0xF6 VF2 V0F38 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 3852}, +/*h(37)=15 VV1 0xF6 VF2 V0F38 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {37, 3849}, +/*empty slot1 */ {0,0}, +/*h(42)=17 VV1 0xF6 VF2 V0F38 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {42, 3850} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map2_opcode0xf7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[67] = { +/*h(0)=0 VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3824}, +/*h(45)=1 VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 3847}, +/*empty slot1 */ {0,0}, +/*h(1)=3 VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3826}, +/*empty slot1 */ {0,0}, +/*h(24)=5 VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {24, 3830}, +/*h(2)=6 VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3824}, +/*empty slot1 */ {0,0}, +/*h(25)=8 VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 3832}, +/*h(3)=9 VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3826}, +/*h(48)=10 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {48, 3836}, +/*h(26)=11 VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {26, 3830}, +/*h(4)=12 VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3825}, +/*h(49)=13 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 3838}, +/*h(27)=14 VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 3832}, +/*h(5)=15 VV1 0xF7 V0F38 VNP W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3827}, +/*h(50)=16 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {50, 3836}, +/*h(28)=17 VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3834}, +/*empty slot1 */ {0,0}, +/*h(51)=19 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 3838}, +/*h(29)=20 VV1 0xF7 V0F38 V66 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3835}, +/*empty slot1 */ {0,0}, +/*h(52)=22 VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {52, 3837}, +/*empty slot1 */ {0,0}, +/*h(8)=24 VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3824}, +/*h(53)=25 VV1 0xF7 V0F38 VF3 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 3839}, +/*empty slot1 */ {0,0}, +/*h(9)=27 VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3826}, +/*empty slot1 */ {0,0}, +/*h(32)=29 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {32, 3842}, +/*h(10)=30 VV1 0xF7 V0F38 VNP not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3824}, +/*empty slot1 */ {0,0}, +/*h(33)=32 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {33, 3844}, +/*h(11)=33 VV1 0xF7 V0F38 VNP not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3826}, +/*h(56)=34 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 3836}, +/*h(34)=35 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {34, 3842}, +/*h(12)=36 VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3828}, +/*h(57)=37 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3838}, +/*h(35)=38 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {35, 3844}, +/*h(13)=39 VV1 0xF7 V0F38 VNP W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 3829}, +/*h(58)=40 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 3836}, +/*h(36)=41 VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {36, 3843}, +/*empty slot1 */ {0,0}, +/*h(59)=43 VV1 0xF7 V0F38 VF3 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3838}, +/*h(37)=44 VV1 0xF7 V0F38 VF2 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {37, 3845}, +/*empty slot1 */ {0,0}, +/*h(60)=46 VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 3840}, +/*empty slot1 */ {0,0}, +/*h(16)=48 VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16, 3830}, +/*h(61)=49 VV1 0xF7 V0F38 VF3 W1 VL128 mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3841}, +/*empty slot1 */ {0,0}, +/*h(17)=51 VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 3832}, +/*empty slot1 */ {0,0}, +/*h(40)=53 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {40, 3842}, +/*h(18)=54 VV1 0xF7 V0F38 V66 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {18, 3830}, +/*empty slot1 */ {0,0}, +/*h(41)=56 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {41, 3844}, +/*h(19)=57 VV1 0xF7 V0F38 V66 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {19, 3832}, +/*empty slot1 */ {0,0}, +/*h(42)=59 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {42, 3842}, +/*h(20)=60 VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3831}, +/*empty slot1 */ {0,0}, +/*h(43)=62 VV1 0xF7 V0F38 VF2 not64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {43, 3844}, +/*h(21)=63 VV1 0xF7 V0F38 V66 W0 mode64 VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3833}, +/*empty slot1 */ {0,0}, +/*h(44)=65 VV1 0xF7 V0F38 VF2 W1 VL128 mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {44, 3846}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 67); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x0_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3733}, +/*h(95)=1 VV1 0x00 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3734} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 94; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x1_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3735}, +/*h(95)=1 VV1 0x01 VL256 V0F3A V66 W1 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3736} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 94; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x02 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {5, 3742}, +/*h(20)=1 VV1 0x02 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {20, 3743}, +/*h(4)=2 VV1 0x02 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {4, 3741}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x02 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {21, 3744} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {28, 2714}, +/*h(93)=3 VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {93, 2717}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x04 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {92, 2716}, +/*h(29)=7 VV1 0x04 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {29, 2715} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {28, 2706}, +/*h(93)=3 VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {93, 2709}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x05 VL256 V66 V0F3A norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {92, 2708}, +/*h(29)=7 VV1 0x05 VL128 V66 V0F3A norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {29, 2707} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2718}, +/*h(21)=1 VV1 0x06 VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2719} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 20; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x08 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {47, 3172}, +/*h(15)=1 VV1 0x08 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {15, 3170}, +/*h(46)=2 VV1 0x08 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {46, 3171}, +/*h(14)=3 VV1 0x08 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {14, 3169}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(47)=0 VV1 0x09 VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {47, 3168}, +/*h(15)=1 VV1 0x09 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {15, 3166}, +/*h(46)=2 VV1 0x09 VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {46, 3167}, +/*h(14)=3 VV1 0x09 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {14, 3165}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xa_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 VV1 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3175}, +/*h(3)=1 VV1 0x0A V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3176} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 VV1 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3173}, +/*h(3)=1 VV1 0x0B V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3174} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xc_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x0C VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 2572}, +/*h(2)=1 VV1 0x0C VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 2570}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x0C VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 2573}, +/*h(3)=4 VV1 0x0C VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 2571} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xd_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x0D VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 2568}, +/*h(2)=1 VV1 0x0D VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 2566}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x0D VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 2569}, +/*h(3)=4 VV1 0x0D VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 2567} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xe_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x0E VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 3163}, +/*h(2)=1 VV1 0x0E VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 3161}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x0E VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 3164}, +/*h(3)=4 VV1 0x0E VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 3162} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x0F VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 3159}, +/*h(2)=1 VV1 0x0F VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 3157}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x0F VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 3160}, +/*h(3)=4 VV1 0x0F VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 3158} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x14_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0x14 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3415}, +/*h(15)=1 VV1 0x14 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3416} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x15_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0x15 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3417}, +/*h(15)=1 VV1 0x15 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3418} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x16_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(123)=0 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {123, 3425}, +/*h(115)=1 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {115, 3425}, +/*h(120)=2 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {120, 3424}, +/*h(112)=3 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {112, 3424}, +/*h(125)=4 VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {125, 3421}, +/*h(117)=5 VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {117, 3423}, +/*h(122)=6 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {122, 3424}, +/*h(114)=7 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {114, 3424}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=10 VV1 0x16 VL128 V66 V0F3A mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {124, 3420}, +/*h(116)=11 VV1 0x16 VL128 V66 V0F3A mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {116, 3422}, +/*empty slot1 */ {0,0}, +/*h(121)=13 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {121, 3425}, +/*h(113)=14 VV1 0x16 VL128 V66 V0F3A not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {113, 3425}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x17_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0x17 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2682}, +/*h(15)=1 VV1 0x17 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2683} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x18_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2727}, +/*h(21)=1 VV1 0x18 norexw_prefix VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2728} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 20; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x19_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(92)=0 VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2674}, +/*h(93)=1 VV1 0x19 norexw_prefix VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2675} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 92; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x1d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x1D VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0*/ {28, 3507}, +/*h(93)=3 VV1 0x1D VL256 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0*/ {93, 3510}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=6 VV1 0x1D VL256 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8() W0*/ {92, 3509}, +/*h(29)=7 VV1 0x1D VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8() W0*/ {29, 3508} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x20_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 VV1 0x20 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3426}, +/*h(3)=1 VV1 0x20 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3427} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x21_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 VV1 0x21 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2729}, +/*h(3)=1 VV1 0x21 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2730} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x22_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*h(26)=1 VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {26, 3432}, +/*h(18)=2 VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {18, 3432}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=5 VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {28, 3434}, +/*h(20)=6 VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {20, 3430}, +/*empty slot1 */ {0,0}, +/*h(25)=8 VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {25, 3433}, +/*h(17)=9 VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {17, 3433}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=12 VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {27, 3433}, +/*h(19)=13 VV1 0x22 VL128 V66 V0F3A not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {19, 3433}, +/*h(24)=14 VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {24, 3432}, +/*h(16)=15 VV1 0x22 VL128 V66 V0F3A not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {16, 3432}, +/*h(29)=16 VV1 0x22 VL128 V66 V0F3A mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {29, 3435}, +/*h(21)=17 VV1 0x22 VL128 V66 V0F3A mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {21, 3431} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x30_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(31)=0 VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()*/ {31, 3871}, +/*h(29)=1 VV1 0x30 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()*/ {29, 3914} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x31_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(31)=0 VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()*/ {31, 3916}, +/*h(29)=1 VV1 0x31 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()*/ {29, 3915} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x32_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(31)=0 VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()*/ {31, 3870}, +/*h(29)=1 VV1 0x32 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()*/ {29, 3911} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x33_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(31)=0 VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR UIMM8()*/ {31, 3913}, +/*h(29)=1 VV1 0x33 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR UIMM8()*/ {29, 3912} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x38_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x38 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3719}, +/*h(21)=1 VV1 0x38 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3720} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 20; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x39_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(92)=0 VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3721}, +/*h(93)=1 VV1 0x39 VL256 V66 V0F3A W0 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3722} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 92; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x40_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x40 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 2680}, +/*h(2)=1 VV1 0x40 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 2678}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x40 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 2681}, +/*h(3)=4 VV1 0x40 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 2679} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x41_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 VV1 0x41 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2676}, +/*h(3)=1 VV1 0x41 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2677} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x42_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x42 VL256 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 3307}, +/*h(2)=1 VV1 0x42 VL128 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 3305}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x42 VL256 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 3308}, +/*h(3)=4 VV1 0x42 VL128 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 3306} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x44_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 UIMM8()*/ {10, 3502}, +/*h(2)=1 VV1 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 UIMM8()*/ {2, 3500}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 UIMM8()*/ {11, 3501}, +/*h(3)=4 VV1 0x44 V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 UIMM8()*/ {3, 3499} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x46_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20)=0 VV1 0x46 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3731}, +/*h(21)=1 VV1 0x46 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3732} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 20; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x48_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x48 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2515}, +/*h(23)=1 VV1 0x48 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2521}, +/*h(7)=2 VV1 0x48 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2519}, +/*h(20)=3 VV1 0x48 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2516}, +/*h(4)=4 VV1 0x48 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2514}, +/*h(22)=5 VV1 0x48 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2520}, +/*h(6)=6 VV1 0x48 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2518}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x48 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2517} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x49_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x49 VL128 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2523}, +/*h(23)=1 VV1 0x49 VL256 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2529}, +/*h(7)=2 VV1 0x49 VL128 V66 V0F3A W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2527}, +/*h(20)=3 VV1 0x49 VL256 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2524}, +/*h(4)=4 VV1 0x49 VL128 V66 V0F3A W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2522}, +/*h(22)=5 VV1 0x49 VL256 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2528}, +/*h(6)=6 VV1 0x49 VL128 V66 V0F3A W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2526}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x49 VL256 V66 V0F3A W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2525} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 3468}, +/*h(20)=1 VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 3469}, +/*h(4)=2 VV1 0x4A V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 3467}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x4A V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 3470} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 3464}, +/*h(20)=1 VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 3465}, +/*h(4)=2 VV1 0x4B V66 V0F3A VL128 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 3463}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x4B V66 V0F3A VL256 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 3466} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x4c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 3460}, +/*h(20)=1 VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 3461}, +/*h(4)=2 VV1 0x4C VL128 V66 V0F3A norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 3459}, +/*empty slot1 */ {0,0}, +/*h(21)=4 VV1 0x4C VL256 V66 V0F3A norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 3462} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x5C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2387}, +/*h(23)=1 VV1 0x5C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2393}, +/*h(7)=2 VV1 0x5C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2389}, +/*h(20)=3 VV1 0x5C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2390}, +/*h(4)=4 VV1 0x5C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2386}, +/*h(22)=5 VV1 0x5C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2392}, +/*h(6)=6 VV1 0x5C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2388}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x5C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2391} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x5D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2395}, +/*h(23)=1 VV1 0x5D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2401}, +/*h(7)=2 VV1 0x5D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2397}, +/*h(20)=3 VV1 0x5D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2398}, +/*h(4)=4 VV1 0x5D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2394}, +/*h(22)=5 VV1 0x5D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2400}, +/*h(6)=6 VV1 0x5D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2396}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x5D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2399} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x5E V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2403}, +/*h(23)=1 VV1 0x5E V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2409}, +/*h(7)=2 VV1 0x5E V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2405}, +/*h(20)=3 VV1 0x5E V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2406}, +/*h(4)=4 VV1 0x5E V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2402}, +/*h(22)=5 VV1 0x5E V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2408}, +/*h(6)=6 VV1 0x5E V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2404}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x5E V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2407} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x5f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x5F V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2411}, +/*h(23)=1 VV1 0x5F V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2417}, +/*h(7)=2 VV1 0x5F V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2413}, +/*h(20)=3 VV1 0x5F V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2414}, +/*h(4)=4 VV1 0x5F V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2410}, +/*h(22)=5 VV1 0x5F V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2416}, +/*h(6)=6 VV1 0x5F V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2412}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x5F V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2415} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x60_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(123)=0 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {123, 3449}, +/*h(115)=1 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {115, 3449}, +/*h(120)=2 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {120, 3448}, +/*h(112)=3 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {112, 3448}, +/*h(125)=4 VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {125, 3453}, +/*h(117)=5 VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {117, 3451}, +/*h(122)=6 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {122, 3448}, +/*h(114)=7 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {114, 3448}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=10 VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {124, 3452}, +/*h(116)=11 VV1 0x60 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {116, 3450}, +/*empty slot1 */ {0,0}, +/*h(121)=13 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {121, 3449}, +/*h(113)=14 VV1 0x60 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {113, 3449}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x61_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(123)=0 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {123, 3437}, +/*h(115)=1 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {115, 3437}, +/*h(120)=2 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {120, 3436}, +/*h(112)=3 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {112, 3436}, +/*h(125)=4 VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {125, 3441}, +/*h(117)=5 VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {117, 3439}, +/*h(122)=6 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {122, 3436}, +/*h(114)=7 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {114, 3436}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=10 VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {124, 3440}, +/*h(116)=11 VV1 0x61 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {116, 3438}, +/*empty slot1 */ {0,0}, +/*h(121)=13 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {121, 3437}, +/*h(113)=14 VV1 0x61 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {113, 3437}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x62_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0x62 VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3454}, +/*h(15)=1 VV1 0x62 VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3455} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x63_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(123)=0 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {123, 3443}, +/*h(115)=1 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {115, 3443}, +/*h(120)=2 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {120, 3442}, +/*h(112)=3 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {112, 3442}, +/*h(125)=4 VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {125, 3447}, +/*h(117)=5 VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {117, 3445}, +/*h(122)=6 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {122, 3442}, +/*h(114)=7 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {114, 3442}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=10 VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W1 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {124, 3446}, +/*h(116)=11 VV1 0x63 VL128 V66 V0F3A NOVSR mode64 W0 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {116, 3444}, +/*empty slot1 */ {0,0}, +/*h(121)=13 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {121, 3443}, +/*h(113)=14 VV1 0x63 VL128 V66 V0F3A NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {113, 3443}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x68_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x68 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2419}, +/*h(23)=1 VV1 0x68 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2425}, +/*h(7)=2 VV1 0x68 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2421}, +/*h(20)=3 VV1 0x68 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2422}, +/*h(4)=4 VV1 0x68 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2418}, +/*h(22)=5 VV1 0x68 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2424}, +/*h(6)=6 VV1 0x68 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2420}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x68 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2423} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x69_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x69 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2427}, +/*h(23)=1 VV1 0x69 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2433}, +/*h(7)=2 VV1 0x69 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2429}, +/*h(20)=3 VV1 0x69 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2430}, +/*h(4)=4 VV1 0x69 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2426}, +/*h(22)=5 VV1 0x69 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2432}, +/*h(6)=6 VV1 0x69 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2428}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x69 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2431} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x6A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2434}, +/*h(5)=1 VV1 0x6A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2435}, +/*h(6)=2 VV1 0x6A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2436}, +/*h(7)=3 VV1 0x6A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2437} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x6B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2438}, +/*h(5)=1 VV1 0x6B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2439}, +/*h(6)=2 VV1 0x6B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2440}, +/*h(7)=3 VV1 0x6B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2441} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x6C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2443}, +/*h(23)=1 VV1 0x6C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2449}, +/*h(7)=2 VV1 0x6C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2445}, +/*h(20)=3 VV1 0x6C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2446}, +/*h(4)=4 VV1 0x6C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2442}, +/*h(22)=5 VV1 0x6C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2448}, +/*h(6)=6 VV1 0x6C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2444}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x6C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2447} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x6D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2451}, +/*h(23)=1 VV1 0x6D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2457}, +/*h(7)=2 VV1 0x6D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2453}, +/*h(20)=3 VV1 0x6D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2454}, +/*h(4)=4 VV1 0x6D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2450}, +/*h(22)=5 VV1 0x6D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2456}, +/*h(6)=6 VV1 0x6D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2452}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x6D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2455} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x6E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2458}, +/*h(5)=1 VV1 0x6E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2459}, +/*h(6)=2 VV1 0x6E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2460}, +/*h(7)=3 VV1 0x6E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2461} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x6f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x6F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2462}, +/*h(5)=1 VV1 0x6F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2463}, +/*h(6)=2 VV1 0x6F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2464}, +/*h(7)=3 VV1 0x6F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2465} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x78_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x78 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2467}, +/*h(23)=1 VV1 0x78 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2473}, +/*h(7)=2 VV1 0x78 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2469}, +/*h(20)=3 VV1 0x78 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2470}, +/*h(4)=4 VV1 0x78 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2466}, +/*h(22)=5 VV1 0x78 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2472}, +/*h(6)=6 VV1 0x78 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2468}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x78 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2471} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x79_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x79 V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2475}, +/*h(23)=1 VV1 0x79 V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2481}, +/*h(7)=2 VV1 0x79 V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2477}, +/*h(20)=3 VV1 0x79 V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2478}, +/*h(4)=4 VV1 0x79 V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2474}, +/*h(22)=5 VV1 0x79 V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2480}, +/*h(6)=6 VV1 0x79 V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2476}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x79 V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2479} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x7A V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2482}, +/*h(5)=1 VV1 0x7A V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2483}, +/*h(6)=2 VV1 0x7A V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2484}, +/*h(7)=3 VV1 0x7A V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2485} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x7B V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2486}, +/*h(5)=1 VV1 0x7B V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2487}, +/*h(6)=2 VV1 0x7B V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2488}, +/*h(7)=3 VV1 0x7B V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2489} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x7C V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2491}, +/*h(23)=1 VV1 0x7C V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2497}, +/*h(7)=2 VV1 0x7C V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2493}, +/*h(20)=3 VV1 0x7C V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2494}, +/*h(4)=4 VV1 0x7C V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2490}, +/*h(22)=5 VV1 0x7C V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2496}, +/*h(6)=6 VV1 0x7C V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2492}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x7C V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2495} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 VV1 0x7D V66 W0 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {5, 2499}, +/*h(23)=1 VV1 0x7D V66 W1 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {23, 2505}, +/*h(7)=2 VV1 0x7D V66 W1 VL128 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {7, 2501}, +/*h(20)=3 VV1 0x7D V66 W0 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {20, 2502}, +/*h(4)=4 VV1 0x7D V66 W0 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {4, 2498}, +/*h(22)=5 VV1 0x7D V66 W1 VL256 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {22, 2504}, +/*h(6)=6 VV1 0x7D V66 W1 VL128 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {6, 2500}, +/*empty slot1 */ {0,0}, +/*h(21)=8 VV1 0x7D V66 W0 VL256 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {21, 2503} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x7E V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2506}, +/*h(5)=1 VV1 0x7E V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2507}, +/*h(6)=2 VV1 0x7E V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2508}, +/*h(7)=3 VV1 0x7E V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2509} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0x7f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(4)=0 VV1 0x7F V66 W0 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2510}, +/*h(5)=1 VV1 0x7F V66 W0 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2511}, +/*h(6)=2 VV1 0x7F V66 W1 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2512}, +/*h(7)=3 VV1 0x7F V66 W1 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2513} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX(d); +hidx = key - 4; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xce_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {23, 3935}, +/*h(7)=2 VV1 0xCE V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {7, 3933}, +/*empty slot1 */ {0,0}, +/*h(22)=4 VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8()*/ {22, 3936}, +/*h(6)=5 VV1 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8()*/ {6, 3934}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xcf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {23, 3931}, +/*h(7)=2 VV1 0xCF V66 V0F3A MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {7, 3929}, +/*empty slot1 */ {0,0}, +/*h(22)=4 VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8()*/ {22, 3932}, +/*h(6)=5 VV1 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8()*/ {6, 3930}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xdf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0xDF VL128 V66 V0F3A NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3480}, +/*h(15)=1 VV1 0xDF VL128 V66 V0F3A NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3479} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map3_opcode0xf0_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(178)=0 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {178, 3856}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(188)=3 VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {188, 3859}, +/*h(180)=4 VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {180, 3857}, +/*empty slot1 */ {0,0}, +/*h(185)=6 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {185, 3854}, +/*h(177)=7 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {177, 3854}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(187)=10 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {187, 3854}, +/*h(179)=11 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {179, 3854}, +/*h(184)=12 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {184, 3856}, +/*h(176)=13 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {176, 3856}, +/*h(189)=14 VV1 0xF0 VF2 V0F3A W1 VL128 NOVSR mode64 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {189, 3858}, +/*h(181)=15 VV1 0xF0 VF2 V0F3A W0 mode64 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {181, 3855}, +/*empty slot1 */ {0,0}, +/*h(186)=17 VV1 0xF0 VF2 V0F3A not64 VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {186, 3856} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x10_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[96] = { +/*h(125)=0 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 3330}, +/*h(93)=1 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3330}, +/*h(61)=2 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3330}, +/*h(29)=3 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3330}, +/*empty slot1 */ {0,0}, +/*h(118)=5 VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {118, 3333}, +/*h(86)=6 VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {86, 3333}, +/*h(54)=7 VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {54, 3333}, +/*h(22)=8 VV1 0x10 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {22, 3333}, +/*h(115)=9 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {115, 3334}, +/*h(83)=10 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {83, 3334}, +/*h(51)=11 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 3334}, +/*h(19)=12 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {19, 3334}, +/*h(126)=13 VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {126, 3329}, +/*h(94)=14 VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {94, 3329}, +/*h(62)=15 VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {62, 3329}, +/*h(30)=16 VV1 0x10 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {30, 3329}, +/*empty slot1 */ {0,0}, +/*h(119)=18 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {119, 3334}, +/*h(87)=19 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {87, 3334}, +/*h(55)=20 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 3334}, +/*h(23)=21 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3334}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(127)=26 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {127, 3330}, +/*h(95)=27 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {95, 3330}, +/*h(63)=28 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 3330}, +/*h(31)=29 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3330}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(117)=35 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {117, 3334}, +/*h(85)=36 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {85, 3334}, +/*h(53)=37 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 3334}, +/*h(21)=38 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3334}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(46)=42 VV1 0x10 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3341}, +/*h(14)=43 VV1 0x10 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3337}, +/*h(121)=44 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 3330}, +/*h(89)=45 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {89, 3330}, +/*h(57)=46 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3330}, +/*h(25)=47 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 3330}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(47)=55 VV1 0x10 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3342}, +/*h(15)=56 VV1 0x10 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3338}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=70 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 3330}, +/*h(91)=71 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {91, 3330}, +/*h(59)=72 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3330}, +/*h(27)=73 VV1 0x10 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 3330}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(38)=77 VV1 0x10 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 3349}, +/*h(6)=78 VV1 0x10 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3345}, +/*h(113)=79 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {113, 3334}, +/*h(81)=80 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {81, 3334}, +/*h(49)=81 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 3334}, +/*h(17)=82 VV1 0x10 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 3334}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(39)=90 VV1 0x10 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 3350}, +/*h(7)=91 VV1 0x10 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3346}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((13*key % 139) % 96); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x11_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[96] = { +/*h(125)=0 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 3332}, +/*h(93)=1 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3332}, +/*h(61)=2 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3332}, +/*h(29)=3 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3332}, +/*empty slot1 */ {0,0}, +/*h(118)=5 VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {118, 3335}, +/*h(86)=6 VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {86, 3335}, +/*h(54)=7 VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {54, 3335}, +/*h(22)=8 VV1 0x11 VF2 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {22, 3335}, +/*h(115)=9 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {115, 3336}, +/*h(83)=10 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {83, 3336}, +/*h(51)=11 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 3336}, +/*h(19)=12 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {19, 3336}, +/*h(126)=13 VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {126, 3331}, +/*h(94)=14 VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {94, 3331}, +/*h(62)=15 VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {62, 3331}, +/*h(30)=16 VV1 0x11 VF3 V0F MOD[mm] MOD!=3 NOVSR REG[rrr] RM[nnn] MODRM()*/ {30, 3331}, +/*empty slot1 */ {0,0}, +/*h(119)=18 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {119, 3336}, +/*h(87)=19 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {87, 3336}, +/*h(55)=20 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 3336}, +/*h(23)=21 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3336}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(127)=26 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {127, 3332}, +/*h(95)=27 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {95, 3332}, +/*h(63)=28 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 3332}, +/*h(31)=29 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3332}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(117)=35 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {117, 3336}, +/*h(85)=36 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {85, 3336}, +/*h(53)=37 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 3336}, +/*h(21)=38 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3336}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(46)=42 VV1 0x11 V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3343}, +/*h(14)=43 VV1 0x11 V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3339}, +/*h(121)=44 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 3332}, +/*h(89)=45 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {89, 3332}, +/*h(57)=46 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3332}, +/*h(25)=47 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 3332}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(47)=55 VV1 0x11 V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3344}, +/*h(15)=56 VV1 0x11 V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3340}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=70 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 3332}, +/*h(91)=71 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {91, 3332}, +/*h(59)=72 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3332}, +/*h(27)=73 VV1 0x11 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 3332}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(38)=77 VV1 0x11 VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 3351}, +/*h(6)=78 VV1 0x11 VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3347}, +/*h(113)=79 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {113, 3336}, +/*h(81)=80 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {81, 3336}, +/*h(49)=81 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 3336}, +/*h(17)=82 VV1 0x11 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 3336}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(39)=90 VV1 0x11 VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 3352}, +/*h(7)=91 VV1 0x11 VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3348}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((13*key % 139) % 96); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x12_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3355}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3156}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x12 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2834}, +/*h(10)=6 VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3353}, +/*h(23)=7 VV1 0x12 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2810}, +/*h(2)=8 VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3355}, +/*empty slot1 */ {0,0}, +/*h(62)=10 VV1 0x12 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2835}, +/*h(7)=11 VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3156}, +/*h(54)=12 VV1 0x12 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {54, 2811}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3353}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3355}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x12 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2833}, +/*empty slot1 */ {0,0}, +/*h(22)=20 VV1 0x12 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2809}, +/*h(1)=21 VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3156}, +/*h(14)=22 VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3353}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x12 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3355}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x12 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3156}, +/*empty slot1 */ {0,0}, +/*h(63)=31 VV1 0x12 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2836}, +/*h(8)=32 VV1 0x12 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3353}, +/*h(55)=33 VV1 0x12 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 2812} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x13_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(14)=1 VV1 0x13 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3354}, +/*h(6)=2 VV1 0x13 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3356} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x14_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0x14 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3317}, +/*h(10)=1 VV1 0x14 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3315}, +/*h(2)=2 VV1 0x14 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3313}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0x14 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3320}, +/*h(1)=6 VV1 0x14 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3318}, +/*h(11)=7 VV1 0x14 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3316}, +/*h(3)=8 VV1 0x14 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3314}, +/*h(8)=9 VV1 0x14 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3319} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x15_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0x15 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3213}, +/*h(10)=1 VV1 0x15 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3211}, +/*h(2)=2 VV1 0x15 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3209}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0x15 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3216}, +/*h(1)=6 VV1 0x15 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3214}, +/*h(11)=7 VV1 0x15 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3212}, +/*h(3)=8 VV1 0x15 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3210}, +/*h(8)=9 VV1 0x15 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3215} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x16_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(0)=0 VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3359}, +/*h(3)=1 VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3155}, +/*h(30)=2 VV1 0x16 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2829}, +/*h(7)=3 VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3155}, +/*h(10)=4 VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3357}, +/*empty slot1 */ {0,0}, +/*h(14)=6 VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3357}, +/*h(4)=7 VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3359}, +/*h(31)=8 VV1 0x16 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2830}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=11 VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3155}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=14 VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3357}, +/*empty slot1 */ {0,0}, +/*h(62)=16 VV1 0x16 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2831}, +/*empty slot1 */ {0,0}, +/*h(5)=18 VV1 0x16 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3155}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=21 VV1 0x16 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3357}, +/*h(2)=22 VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3359}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=27 VV1 0x16 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2832}, +/*empty slot1 */ {0,0}, +/*h(6)=29 VV1 0x16 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3359}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((11*key % 37) % 32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x17_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(14)=1 VV1 0x17 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3358}, +/*h(6)=2 VV1 0x17 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3360} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x28_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(47)=0 VV1 0x28 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2782}, +/*h(39)=1 VV1 0x28 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 2790}, +/*empty slot1 */ {0,0}, +/*h(15)=3 VV1 0x28 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2778}, +/*h(7)=4 VV1 0x28 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2786}, +/*h(46)=5 VV1 0x28 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2781}, +/*h(38)=6 VV1 0x28 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 2789}, +/*empty slot1 */ {0,0}, +/*h(14)=8 VV1 0x28 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2777}, +/*h(6)=9 VV1 0x28 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2785}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 13ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x29_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(47)=0 VV1 0x29 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2784}, +/*h(39)=1 VV1 0x29 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 2792}, +/*empty slot1 */ {0,0}, +/*h(15)=3 VV1 0x29 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2780}, +/*h(7)=4 VV1 0x29 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2788}, +/*h(46)=5 VV1 0x29 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2783}, +/*h(38)=6 VV1 0x29 VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 2791}, +/*empty slot1 */ {0,0}, +/*h(14)=8 VV1 0x29 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2779}, +/*h(6)=9 VV1 0x29 VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2787}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 13ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(34)=0 VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {34, 2648}, +/*empty slot1 */ {0,0}, +/*h(60)=2 VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 2658}, +/*empty slot1 */ {0,0}, +/*h(52)=4 VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {52, 2656}, +/*empty slot1 */ {0,0}, +/*h(44)=6 VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {44, 2652}, +/*h(57)=7 VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 2655}, +/*h(36)=8 VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {36, 2650}, +/*h(49)=9 VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 2655}, +/*empty slot1 */ {0,0}, +/*h(41)=11 VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {41, 2649}, +/*empty slot1 */ {0,0}, +/*h(33)=13 VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {33, 2649}, +/*empty slot1 */ {0,0}, +/*h(59)=15 VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 2655}, +/*empty slot1 */ {0,0}, +/*h(51)=17 VV1 0x2A VF3 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 2655}, +/*empty slot1 */ {0,0}, +/*h(43)=19 VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {43, 2649}, +/*h(56)=20 VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 2654}, +/*h(35)=21 VV1 0x2A VF2 V0F not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {35, 2649}, +/*h(48)=22 VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {48, 2654}, +/*h(61)=23 VV1 0x2A VF3 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 2659}, +/*h(40)=24 VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {40, 2648}, +/*h(53)=25 VV1 0x2A VF3 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 2657}, +/*h(32)=26 VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {32, 2648}, +/*h(45)=27 VV1 0x2A VF2 V0F mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {45, 2653}, +/*h(58)=28 VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 2654}, +/*h(37)=29 VV1 0x2A VF2 V0F mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {37, 2651}, +/*h(50)=30 VV1 0x2A VF3 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {50, 2654}, +/*empty slot1 */ {0,0}, +/*h(42)=32 VV1 0x2A VF2 V0F not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {42, 2648}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(14)=0 VV1 0x2B V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3475}, +/*h(38)=1 VV1 0x2B VNP V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 3478}, +/*h(46)=2 VV1 0x2B V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3476}, +/*h(6)=3 VV1 0x2B VNP V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3477} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((4*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[24] = { +/*h(178)=0 VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {178, 2628}, +/*h(189)=1 VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {189, 2633}, +/*h(243)=2 VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {243, 2641}, +/*h(248)=3 VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {248, 2640}, +/*h(179)=4 VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {179, 2629}, +/*h(184)=5 VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {184, 2628}, +/*h(244)=6 VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {244, 2642}, +/*h(249)=7 VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {249, 2641}, +/*h(180)=8 VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {180, 2630}, +/*h(185)=9 VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {185, 2629}, +/*h(245)=10 VV1 0x2C VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {245, 2643}, +/*h(250)=11 VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {250, 2640}, +/*h(181)=12 VV1 0x2C VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {181, 2631}, +/*h(186)=13 VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {186, 2628}, +/*h(240)=14 VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {240, 2640}, +/*h(251)=15 VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {251, 2641}, +/*h(176)=16 VV1 0x2C VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {176, 2628}, +/*h(187)=17 VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {187, 2629}, +/*h(241)=18 VV1 0x2C VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {241, 2641}, +/*h(252)=19 VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {252, 2644}, +/*h(177)=20 VV1 0x2C VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {177, 2629}, +/*h(188)=21 VV1 0x2C VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {188, 2632}, +/*h(242)=22 VV1 0x2C VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {242, 2640}, +/*h(253)=23 VV1 0x2C VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {253, 2645} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX(d); +hidx = ((4*key % 43) % 24); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[24] = { +/*h(178)=0 VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {178, 2622}, +/*h(189)=1 VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {189, 2627}, +/*h(243)=2 VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {243, 2635}, +/*h(248)=3 VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {248, 2634}, +/*h(179)=4 VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {179, 2623}, +/*h(184)=5 VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {184, 2622}, +/*h(244)=6 VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {244, 2636}, +/*h(249)=7 VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {249, 2635}, +/*h(180)=8 VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {180, 2624}, +/*h(185)=9 VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {185, 2623}, +/*h(245)=10 VV1 0x2D VF3 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {245, 2637}, +/*h(250)=11 VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {250, 2634}, +/*h(181)=12 VV1 0x2D VF2 V0F NOVSR mode64 norexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {181, 2625}, +/*h(186)=13 VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {186, 2622}, +/*h(240)=14 VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {240, 2634}, +/*h(251)=15 VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {251, 2635}, +/*h(176)=16 VV1 0x2D VF2 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {176, 2622}, +/*h(187)=17 VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {187, 2623}, +/*h(241)=18 VV1 0x2D VF3 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {241, 2635}, +/*h(252)=19 VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {252, 2638}, +/*h(177)=20 VV1 0x2D VF2 V0F NOVSR not64 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {177, 2623}, +/*h(188)=21 VV1 0x2D VF2 V0F NOVSR mode64 rexw_prefix MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {188, 2626}, +/*h(242)=22 VV1 0x2D VF3 V0F NOVSR not64 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {242, 2634}, +/*h(253)=23 VV1 0x2D VF3 V0F NOVSR mode64 rexw_prefix MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {253, 2639} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX(d); +hidx = ((4*key % 43) % 24); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(15)=0 VV1 0x2E V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3310}, +/*h(7)=1 VV1 0x2E VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3312}, +/*h(14)=2 VV1 0x2E V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3309}, +/*h(6)=3 VV1 0x2E VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x2f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(15)=0 VV1 0x2F V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2587}, +/*h(7)=1 VV1 0x2F VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2589}, +/*h(14)=2 VV1 0x2F V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2586}, +/*h(6)=3 VV1 0x2F VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2588} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x41_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {23, 3880}, +/*h(17)=2 VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3861}, +/*h(19)=3 VV1 0x41 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3884}, +/*h(21)=4 VV1 0x41 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3879} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x42_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {23, 3882}, +/*h(17)=2 VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3860}, +/*h(19)=3 VV1 0x42 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3883}, +/*h(21)=4 VV1 0x42 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3881} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x44_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(13)=0 VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {13, 3867}, +/*h(31)=1 VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {31, 3903}, +/*h(15)=2 VV1 0x44 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {15, 3904}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(29)=7 VV1 0x44 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {29, 3902} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x45_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {23, 3906}, +/*h(17)=2 VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3869}, +/*h(19)=3 VV1 0x45 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3907}, +/*h(21)=4 VV1 0x45 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3905} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x46_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {23, 3924}, +/*h(17)=2 VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3873}, +/*h(19)=3 VV1 0x46 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3925}, +/*h(21)=4 VV1 0x46 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3923} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x47_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {23, 3927}, +/*h(17)=2 VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3874}, +/*h(19)=3 VV1 0x47 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3928}, +/*h(21)=4 VV1 0x47 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3926} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x4a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(23)=1 VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {23, 3876}, +/*h(17)=2 VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3878}, +/*h(19)=3 VV1 0x4A VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3877}, +/*h(21)=4 VV1 0x4A V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3875} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x4b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(17)=2 VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {17, 3922}, +/*h(19)=3 VV1 0x4B VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W1*/ {19, 3921}, +/*h(21)=4 VV1 0x4B V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL256 W0*/ {21, 3872} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x50_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(7)=0 VV1 0x50 VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3363}, +/*h(39)=1 VV1 0x50 VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 3364}, +/*h(15)=2 VV1 0x50 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3361}, +/*h(47)=3 VV1 0x50 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((9*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x51_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[144] = { +/*h(89)=0 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {89, 3208}, +/*empty slot1 */ {0,0}, +/*h(123)=2 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 3208}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(47)=6 VV1 0x51 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3200}, +/*empty slot1 */ {0,0}, +/*h(81)=8 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {81, 3206}, +/*h(26)=9 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {26, 3207}, +/*h(115)=10 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {115, 3206}, +/*h(60)=11 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 3207}, +/*empty slot1 */ {0,0}, +/*h(94)=13 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {94, 3207}, +/*h(39)=14 VV1 0x51 VL256 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 3204}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(18)=17 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {18, 3205}, +/*empty slot1 */ {0,0}, +/*h(52)=19 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {52, 3205}, +/*empty slot1 */ {0,0}, +/*h(86)=21 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {86, 3205}, +/*h(31)=22 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3208}, +/*h(120)=23 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 3207}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(23)=30 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3206}, +/*h(112)=31 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {112, 3205}, +/*h(57)=32 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3208}, +/*empty slot1 */ {0,0}, +/*h(91)=34 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {91, 3208}, +/*empty slot1 */ {0,0}, +/*h(125)=36 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 3208}, +/*empty slot1 */ {0,0}, +/*h(15)=38 VV1 0x51 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3198}, +/*empty slot1 */ {0,0}, +/*h(49)=40 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 3206}, +/*empty slot1 */ {0,0}, +/*h(83)=42 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {83, 3206}, +/*h(28)=43 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3207}, +/*h(117)=44 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {117, 3206}, +/*h(62)=45 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 3207}, +/*h(7)=46 VV1 0x51 VL128 VNP NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3202}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=51 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3205}, +/*empty slot1 */ {0,0}, +/*h(54)=53 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {54, 3205}, +/*empty slot1 */ {0,0}, +/*h(88)=55 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {88, 3207}, +/*empty slot1 */ {0,0}, +/*h(122)=57 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {122, 3207}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(46)=61 VV1 0x51 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3199}, +/*empty slot1 */ {0,0}, +/*h(80)=63 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {80, 3205}, +/*h(25)=64 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 3208}, +/*h(114)=65 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {114, 3205}, +/*h(59)=66 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3208}, +/*empty slot1 */ {0,0}, +/*h(93)=68 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3208}, +/*h(38)=69 VV1 0x51 VL256 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 3203}, +/*h(127)=70 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {127, 3208}, +/*empty slot1 */ {0,0}, +/*h(17)=72 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 3206}, +/*empty slot1 */ {0,0}, +/*h(51)=74 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 3206}, +/*empty slot1 */ {0,0}, +/*h(85)=76 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {85, 3206}, +/*h(30)=77 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 3207}, +/*h(119)=78 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {119, 3206}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=85 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3205}, +/*empty slot1 */ {0,0}, +/*h(56)=87 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 3207}, +/*empty slot1 */ {0,0}, +/*h(90)=89 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {90, 3207}, +/*empty slot1 */ {0,0}, +/*h(124)=91 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {124, 3207}, +/*empty slot1 */ {0,0}, +/*h(14)=93 VV1 0x51 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3197}, +/*empty slot1 */ {0,0}, +/*h(48)=95 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {48, 3205}, +/*empty slot1 */ {0,0}, +/*h(82)=97 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {82, 3205}, +/*h(27)=98 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 3208}, +/*h(116)=99 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {116, 3205}, +/*h(61)=100 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3208}, +/*h(6)=101 VV1 0x51 VL128 VNP NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3201}, +/*h(95)=102 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {95, 3208}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(19)=106 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {19, 3206}, +/*empty slot1 */ {0,0}, +/*h(53)=108 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 3206}, +/*empty slot1 */ {0,0}, +/*h(87)=110 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {87, 3206}, +/*empty slot1 */ {0,0}, +/*h(121)=112 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 3208}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=119 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {24, 3207}, +/*h(113)=120 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {113, 3206}, +/*h(58)=121 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 3207}, +/*empty slot1 */ {0,0}, +/*h(92)=123 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3207}, +/*empty slot1 */ {0,0}, +/*h(126)=125 VV1 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {126, 3207}, +/*empty slot1 */ {0,0}, +/*h(16)=127 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16, 3205}, +/*empty slot1 */ {0,0}, +/*h(50)=129 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {50, 3205}, +/*empty slot1 */ {0,0}, +/*h(84)=131 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {84, 3205}, +/*h(29)=132 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3208}, +/*h(118)=133 VV1 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {118, 3205}, +/*h(63)=134 VV1 0x51 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 3208}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=140 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3206}, +/*empty slot1 */ {0,0}, +/*h(55)=142 VV1 0x51 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 3206}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 144ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x52_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[72] = { +/*h(24)=0 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {24, 3195}, +/*h(122)=1 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {122, 3195}, +/*h(25)=2 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 3196}, +/*empty slot1 */ {0,0}, +/*h(123)=4 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 3196}, +/*h(26)=5 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {26, 3195}, +/*empty slot1 */ {0,0}, +/*h(124)=7 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {124, 3195}, +/*h(27)=8 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 3196}, +/*empty slot1 */ {0,0}, +/*h(125)=10 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 3196}, +/*h(28)=11 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3195}, +/*empty slot1 */ {0,0}, +/*h(126)=13 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {126, 3195}, +/*h(29)=14 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3196}, +/*empty slot1 */ {0,0}, +/*h(127)=16 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {127, 3196}, +/*h(30)=17 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 3195}, +/*h(6)=18 VV1 0x52 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3191}, +/*empty slot1 */ {0,0}, +/*h(31)=20 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3196}, +/*h(7)=21 VV1 0x52 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3192}, +/*h(56)=22 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(57)=25 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3196}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=28 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=31 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3196}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(60)=34 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(61)=37 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3196}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(62)=40 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 3195}, +/*h(38)=41 VV1 0x52 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 3193}, +/*empty slot1 */ {0,0}, +/*h(63)=43 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 3196}, +/*h(39)=44 VV1 0x52 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 3194}, +/*h(88)=45 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {88, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(89)=48 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {89, 3196}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=51 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {90, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=54 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {91, 3196}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=57 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(93)=60 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3196}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=63 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {94, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(95)=66 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {95, 3196}, +/*empty slot1 */ {0,0}, +/*h(120)=68 VV1 0x52 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 3195}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(121)=71 VV1 0x52 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 3196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((3*key % 73) % 72); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x53_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[72] = { +/*h(24)=0 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {24, 3189}, +/*h(122)=1 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {122, 3189}, +/*h(25)=2 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 3190}, +/*empty slot1 */ {0,0}, +/*h(123)=4 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 3190}, +/*h(26)=5 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {26, 3189}, +/*empty slot1 */ {0,0}, +/*h(124)=7 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {124, 3189}, +/*h(27)=8 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 3190}, +/*empty slot1 */ {0,0}, +/*h(125)=10 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 3190}, +/*h(28)=11 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3189}, +/*empty slot1 */ {0,0}, +/*h(126)=13 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {126, 3189}, +/*h(29)=14 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3190}, +/*empty slot1 */ {0,0}, +/*h(127)=16 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {127, 3190}, +/*h(30)=17 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 3189}, +/*h(6)=18 VV1 0x53 VNP VL128 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3185}, +/*empty slot1 */ {0,0}, +/*h(31)=20 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3190}, +/*h(7)=21 VV1 0x53 VNP VL128 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3186}, +/*h(56)=22 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(57)=25 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 3190}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=28 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=31 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 3190}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(60)=34 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(61)=37 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 3190}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(62)=40 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 3189}, +/*h(38)=41 VV1 0x53 VNP VL256 NOVSR V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 3187}, +/*empty slot1 */ {0,0}, +/*h(63)=43 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 3190}, +/*h(39)=44 VV1 0x53 VNP VL256 NOVSR V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 3188}, +/*h(88)=45 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {88, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(89)=48 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {89, 3190}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=51 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {90, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=54 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {91, 3190}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=57 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(93)=60 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 3190}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=63 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {94, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(95)=66 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {95, 3190}, +/*empty slot1 */ {0,0}, +/*h(120)=68 VV1 0x53 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 3189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(121)=71 VV1 0x53 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 3190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = ((3*key % 73) % 72); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x54_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0x54 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2554}, +/*h(10)=1 VV1 0x54 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2552}, +/*h(2)=2 VV1 0x54 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2550}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0x54 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2557}, +/*h(1)=6 VV1 0x54 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2555}, +/*h(11)=7 VV1 0x54 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2553}, +/*h(3)=8 VV1 0x54 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2551}, +/*h(8)=9 VV1 0x54 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2556} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x55_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0x55 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2562}, +/*h(10)=1 VV1 0x55 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2560}, +/*h(2)=2 VV1 0x55 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2558}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0x55 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2565}, +/*h(1)=6 VV1 0x55 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2563}, +/*h(11)=7 VV1 0x55 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2561}, +/*h(3)=8 VV1 0x55 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2559}, +/*h(8)=9 VV1 0x55 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2564} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x56_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0x56 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3245}, +/*h(10)=1 VV1 0x56 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3243}, +/*h(2)=2 VV1 0x56 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3241}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0x56 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3248}, +/*h(1)=6 VV1 0x56 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3246}, +/*h(11)=7 VV1 0x56 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3244}, +/*h(3)=8 VV1 0x56 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3242}, +/*h(8)=9 VV1 0x56 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3247} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x57_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0x57 VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3325}, +/*h(10)=1 VV1 0x57 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3323}, +/*h(2)=2 VV1 0x57 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3321}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0x57 VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3328}, +/*h(1)=6 VV1 0x57 VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3326}, +/*h(11)=7 VV1 0x57 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3324}, +/*h(3)=8 VV1 0x57 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3322}, +/*h(8)=9 VV1 0x57 VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3327} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x58_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x58 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2534}, +/*h(13)=1 VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2539}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2539}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2541}, +/*h(10)=6 VV1 0x58 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2532}, +/*h(23)=7 VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2541}, +/*h(2)=8 VV1 0x58 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2530}, +/*h(15)=9 VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2541}, +/*h(28)=10 VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2538}, +/*h(7)=11 VV1 0x58 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2541}, +/*h(20)=12 VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2538}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2538}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2538}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2540}, +/*h(9)=19 VV1 0x58 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2537}, +/*h(22)=20 VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2540}, +/*h(1)=21 VV1 0x58 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2535}, +/*h(14)=22 VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2540}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2540}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0x58 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2533}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x58 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2531}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2539}, +/*h(8)=32 VV1 0x58 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2536}, +/*h(21)=33 VV1 0x58 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2539} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x59_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x59 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3233}, +/*h(13)=1 VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 3238}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3238}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3240}, +/*h(10)=6 VV1 0x59 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3231}, +/*h(23)=7 VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3240}, +/*h(2)=8 VV1 0x59 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3229}, +/*h(15)=9 VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3240}, +/*h(28)=10 VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3237}, +/*h(7)=11 VV1 0x59 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3240}, +/*h(20)=12 VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3237}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3237}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3237}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 3239}, +/*h(9)=19 VV1 0x59 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3236}, +/*h(22)=20 VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3239}, +/*h(1)=21 VV1 0x59 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3234}, +/*h(14)=22 VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3239}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3239}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0x59 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3232}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x59 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3230}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3238}, +/*h(8)=32 VV1 0x59 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3235}, +/*h(21)=33 VV1 0x59 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3238} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[144] = { +/*h(89)=0 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {89, 2661}, +/*empty slot1 */ {0,0}, +/*h(123)=2 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 2661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(47)=6 VV1 0x5A V66 VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2609}, +/*empty slot1 */ {0,0}, +/*h(81)=8 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {81, 2647}, +/*h(26)=9 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {26, 2660}, +/*h(115)=10 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {115, 2647}, +/*h(60)=11 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {60, 2660}, +/*empty slot1 */ {0,0}, +/*h(94)=13 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {94, 2660}, +/*h(39)=14 VV1 0x5A VNP VL256 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 2621}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(18)=17 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {18, 2646}, +/*empty slot1 */ {0,0}, +/*h(52)=19 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {52, 2646}, +/*empty slot1 */ {0,0}, +/*h(86)=21 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {86, 2646}, +/*h(31)=22 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2661}, +/*h(120)=23 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 2660}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(23)=30 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2647}, +/*h(112)=31 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {112, 2646}, +/*h(57)=32 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {57, 2661}, +/*empty slot1 */ {0,0}, +/*h(91)=34 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {91, 2661}, +/*empty slot1 */ {0,0}, +/*h(125)=36 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 2661}, +/*empty slot1 */ {0,0}, +/*h(15)=38 VV1 0x5A V66 VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2607}, +/*empty slot1 */ {0,0}, +/*h(49)=40 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {49, 2647}, +/*empty slot1 */ {0,0}, +/*h(83)=42 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {83, 2647}, +/*h(28)=43 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2660}, +/*h(117)=44 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {117, 2647}, +/*h(62)=45 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2660}, +/*h(7)=46 VV1 0x5A VNP VL128 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2619}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(20)=51 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2646}, +/*empty slot1 */ {0,0}, +/*h(54)=53 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {54, 2646}, +/*empty slot1 */ {0,0}, +/*h(88)=55 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {88, 2660}, +/*empty slot1 */ {0,0}, +/*h(122)=57 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {122, 2660}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(46)=61 VV1 0x5A V66 VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2608}, +/*empty slot1 */ {0,0}, +/*h(80)=63 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {80, 2646}, +/*h(25)=64 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {25, 2661}, +/*h(114)=65 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {114, 2646}, +/*h(59)=66 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {59, 2661}, +/*empty slot1 */ {0,0}, +/*h(93)=68 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {93, 2661}, +/*h(38)=69 VV1 0x5A VNP VL256 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 2620}, +/*h(127)=70 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {127, 2661}, +/*empty slot1 */ {0,0}, +/*h(17)=72 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {17, 2647}, +/*empty slot1 */ {0,0}, +/*h(51)=74 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {51, 2647}, +/*empty slot1 */ {0,0}, +/*h(85)=76 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {85, 2647}, +/*h(30)=77 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2660}, +/*h(119)=78 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {119, 2647}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(22)=85 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2646}, +/*empty slot1 */ {0,0}, +/*h(56)=87 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {56, 2660}, +/*empty slot1 */ {0,0}, +/*h(90)=89 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {90, 2660}, +/*empty slot1 */ {0,0}, +/*h(124)=91 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {124, 2660}, +/*empty slot1 */ {0,0}, +/*h(14)=93 VV1 0x5A V66 VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2606}, +/*empty slot1 */ {0,0}, +/*h(48)=95 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {48, 2646}, +/*empty slot1 */ {0,0}, +/*h(82)=97 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {82, 2646}, +/*h(27)=98 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {27, 2661}, +/*h(116)=99 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {116, 2646}, +/*h(61)=100 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {61, 2661}, +/*h(6)=101 VV1 0x5A VNP VL128 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2618}, +/*h(95)=102 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {95, 2661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(19)=106 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {19, 2647}, +/*empty slot1 */ {0,0}, +/*h(53)=108 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {53, 2647}, +/*empty slot1 */ {0,0}, +/*h(87)=110 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {87, 2647}, +/*empty slot1 */ {0,0}, +/*h(121)=112 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 2661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=119 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {24, 2660}, +/*h(113)=120 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {113, 2647}, +/*h(58)=121 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {58, 2660}, +/*empty slot1 */ {0,0}, +/*h(92)=123 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {92, 2660}, +/*empty slot1 */ {0,0}, +/*h(126)=125 VV1 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {126, 2660}, +/*empty slot1 */ {0,0}, +/*h(16)=127 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {16, 2646}, +/*empty slot1 */ {0,0}, +/*h(50)=129 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {50, 2646}, +/*empty slot1 */ {0,0}, +/*h(84)=131 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {84, 2646}, +/*h(29)=132 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2661}, +/*h(118)=133 VV1 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {118, 2646}, +/*h(63)=134 VV1 0x5A VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(21)=140 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2647}, +/*empty slot1 */ {0,0}, +/*h(55)=142 VV1 0x5A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 2647}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 144ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[22] = { +/*empty slot1 */ {0,0}, +/*h(47)=1 VV1 0x5B VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2613}, +/*h(39)=2 VV1 0x5B VL256 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {39, 2597}, +/*h(31)=3 VV1 0x5B VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2615}, +/*empty slot1 */ {0,0}, +/*h(15)=5 VV1 0x5B VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2611}, +/*h(62)=6 VV1 0x5B VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2616}, +/*h(7)=7 VV1 0x5B VL128 VNP V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2595}, +/*empty slot1 */ {0,0}, +/*h(46)=9 VV1 0x5B VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2612}, +/*h(38)=10 VV1 0x5B VL256 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {38, 2596}, +/*h(30)=11 VV1 0x5B VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2614}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=14 VV1 0x5B VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2610}, +/*h(6)=15 VV1 0x5B VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2594}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=20 VV1 0x5B VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2617}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 22ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x5C VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 3221}, +/*h(13)=1 VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 3226}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 3226}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 3228}, +/*h(10)=6 VV1 0x5C V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3219}, +/*h(23)=7 VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 3228}, +/*h(2)=8 VV1 0x5C V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3217}, +/*h(15)=9 VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3228}, +/*h(28)=10 VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 3225}, +/*h(7)=11 VV1 0x5C VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 3228}, +/*h(20)=12 VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 3225}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 3225}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 3225}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 3227}, +/*h(9)=19 VV1 0x5C VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 3224}, +/*h(22)=20 VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 3227}, +/*h(1)=21 VV1 0x5C VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 3222}, +/*h(14)=22 VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3227}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 3227}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0x5C V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3220}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x5C V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3218}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 3226}, +/*h(8)=32 VV1 0x5C VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 3223}, +/*h(21)=33 VV1 0x5C VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 3226} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x5D VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2769}, +/*h(13)=1 VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2774}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2774}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2776}, +/*h(10)=6 VV1 0x5D V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2767}, +/*h(23)=7 VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2776}, +/*h(2)=8 VV1 0x5D V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2765}, +/*h(15)=9 VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2776}, +/*h(28)=10 VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2773}, +/*h(7)=11 VV1 0x5D VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2776}, +/*h(20)=12 VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2773}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2773}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2773}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2775}, +/*h(9)=19 VV1 0x5D VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2772}, +/*h(22)=20 VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2775}, +/*h(1)=21 VV1 0x5D VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2770}, +/*h(14)=22 VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2775}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2775}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0x5D V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2768}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x5D V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2766}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2774}, +/*h(8)=32 VV1 0x5D VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2771}, +/*h(21)=33 VV1 0x5D VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2774} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x5E VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2666}, +/*h(13)=1 VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2671}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2671}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2673}, +/*h(10)=6 VV1 0x5E V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2664}, +/*h(23)=7 VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2673}, +/*h(2)=8 VV1 0x5E V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2662}, +/*h(15)=9 VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2673}, +/*h(28)=10 VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2670}, +/*h(7)=11 VV1 0x5E VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2673}, +/*h(20)=12 VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2670}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2670}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2670}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2672}, +/*h(9)=19 VV1 0x5E VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2669}, +/*h(22)=20 VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2672}, +/*h(1)=21 VV1 0x5E VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2667}, +/*h(14)=22 VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2672}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2672}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0x5E V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2665}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x5E V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2663}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2671}, +/*h(8)=32 VV1 0x5E VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2668}, +/*h(21)=33 VV1 0x5E VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2671} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x5f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0x5F VNP V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {0, 2757}, +/*h(13)=1 VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2762}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2762}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2764}, +/*h(10)=6 VV1 0x5F V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2755}, +/*h(23)=7 VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2764}, +/*h(2)=8 VV1 0x5F V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2753}, +/*h(15)=9 VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2764}, +/*h(28)=10 VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {28, 2761}, +/*h(7)=11 VV1 0x5F VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {7, 2764}, +/*h(20)=12 VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {20, 2761}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2761}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2761}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2763}, +/*h(9)=19 VV1 0x5F VNP V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {9, 2760}, +/*h(22)=20 VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2763}, +/*h(1)=21 VV1 0x5F VNP V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {1, 2758}, +/*h(14)=22 VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2763}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {6, 2763}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0x5F V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2756}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0x5F V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2754}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {29, 2762}, +/*h(8)=32 VV1 0x5F VNP V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {8, 2759}, +/*h(21)=33 VV1 0x5F VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {21, 2762} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x60_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x60 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3137}, +/*h(2)=1 VV1 0x60 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3135}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x60 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3138}, +/*h(3)=4 VV1 0x60 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3136} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x61_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x61 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3141}, +/*h(2)=1 VV1 0x61 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3139}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x61 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3142}, +/*h(3)=4 VV1 0x61 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3140} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x62_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x62 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3145}, +/*h(2)=1 VV1 0x62 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3143}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x62 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3146}, +/*h(3)=4 VV1 0x62 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3144} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x63_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x63 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2881}, +/*h(2)=1 VV1 0x63 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2879}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x63 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2882}, +/*h(3)=4 VV1 0x63 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2880} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x64_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x64 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3001}, +/*h(2)=1 VV1 0x64 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2999}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x64 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3002}, +/*h(3)=4 VV1 0x64 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3000} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x65_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x65 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3005}, +/*h(2)=1 VV1 0x65 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3003}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x65 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3006}, +/*h(3)=4 VV1 0x65 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3004} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x66_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x66 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3009}, +/*h(2)=1 VV1 0x66 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3007}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x66 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3010}, +/*h(3)=4 VV1 0x66 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3008} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x67_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x67 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2889}, +/*h(2)=1 VV1 0x67 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2887}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x67 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2890}, +/*h(3)=4 VV1 0x67 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2888} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x68_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x68 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3121}, +/*h(2)=1 VV1 0x68 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3119}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x68 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3122}, +/*h(3)=4 VV1 0x68 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3120} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x69_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x69 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3125}, +/*h(2)=1 VV1 0x69 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3123}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x69 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3126}, +/*h(3)=4 VV1 0x69 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3124} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6a_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x6A VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3129}, +/*h(2)=1 VV1 0x6A VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3127}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x6A VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3130}, +/*h(3)=4 VV1 0x6A VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3128} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6b_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x6B VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2885}, +/*h(2)=1 VV1 0x6B VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2883}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x6B VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2886}, +/*h(3)=4 VV1 0x6B VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2884} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x6C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3149}, +/*h(2)=1 VV1 0x6C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3147}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x6C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3150}, +/*h(3)=4 VV1 0x6C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3148} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x6D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3133}, +/*h(2)=1 VV1 0x6D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3131}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x6D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3134}, +/*h(3)=4 VV1 0x6D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3132} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(123)=0 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 2794}, +/*h(115)=1 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {115, 2794}, +/*h(120)=2 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 2793}, +/*h(112)=3 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {112, 2793}, +/*h(125)=4 VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 2802}, +/*h(117)=5 VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {117, 2798}, +/*h(122)=6 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {122, 2793}, +/*h(114)=7 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {114, 2793}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=10 VV1 0x6E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {124, 2801}, +/*h(116)=11 VV1 0x6E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {116, 2797}, +/*empty slot1 */ {0,0}, +/*h(121)=13 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 2794}, +/*h(113)=14 VV1 0x6E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {113, 2794}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x6f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(47)=0 VV1 0x6F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2818}, +/*h(31)=1 VV1 0x6F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2822}, +/*h(15)=2 VV1 0x6F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2814}, +/*h(62)=3 VV1 0x6F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2823}, +/*h(46)=4 VV1 0x6F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2817}, +/*h(30)=5 VV1 0x6F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2821}, +/*h(14)=6 VV1 0x6F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2813}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=9 VV1 0x6F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2824} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x70_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(47)=0 VV1 0x70 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {47, 2870}, +/*empty slot1 */ {0,0}, +/*h(31)=2 VV1 0x70 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {31, 2872}, +/*h(23)=3 VV1 0x70 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {23, 2876}, +/*h(15)=4 VV1 0x70 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {15, 2868}, +/*h(62)=5 VV1 0x70 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {62, 2873}, +/*h(54)=6 VV1 0x70 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {54, 2877}, +/*h(46)=7 VV1 0x70 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {46, 2869}, +/*empty slot1 */ {0,0}, +/*h(30)=9 VV1 0x70 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {30, 2871}, +/*h(22)=10 VV1 0x70 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {22, 2875}, +/*h(14)=11 VV1 0x70 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {14, 2867}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=15 VV1 0x70 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {63, 2874}, +/*h(55)=16 VV1 0x70 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {55, 2878} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x71_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(21)=0 VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {21, 2915}, +/*h(85)=1 VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {85, 2918}, +/*h(29)=2 VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {29, 2897}, +/*h(93)=3 VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {93, 2900}, +/*h(25)=4 VV1 0x71 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {25, 2933}, +/*h(89)=5 VV1 0x71 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {89, 2936} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_VEX_PREFIX_VL(d); +hidx = ((5*key % 11) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x72_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(21)=0 VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {21, 2921}, +/*h(85)=1 VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {85, 2924}, +/*h(29)=2 VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {29, 2903}, +/*h(93)=3 VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {93, 2906}, +/*h(25)=4 VV1 0x72 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {25, 2939}, +/*h(89)=5 VV1 0x72 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b100] RM[nnn] UIMM8()*/ {89, 2942} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_VEX_PREFIX_VL(d); +hidx = ((5*key % 11) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x73_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[14] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(31)=2 VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()*/ {31, 3153}, +/*h(23)=3 VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()*/ {23, 3151}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(93)=6 VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {93, 2912}, +/*h(85)=7 VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {85, 2930}, +/*empty slot1 */ {0,0}, +/*h(95)=9 VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b111] RM[nnn] UIMM8()*/ {95, 3154}, +/*h(87)=10 VV1 0x73 VL256 V66 V0F MOD[0b11] MOD=3 REG[0b011] RM[nnn] UIMM8()*/ {87, 3152}, +/*empty slot1 */ {0,0}, +/*h(29)=12 VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b110] RM[nnn] UIMM8()*/ {29, 2909}, +/*h(21)=13 VV1 0x73 VL128 V66 V0F MOD[0b11] MOD=3 REG[0b010] RM[nnn] UIMM8()*/ {21, 2927} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 14ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x74_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x74 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2985}, +/*h(2)=1 VV1 0x74 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2983}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x74 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2986}, +/*h(3)=4 VV1 0x74 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2984} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x75_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x75 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2989}, +/*h(2)=1 VV1 0x75 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2987}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x75 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2990}, +/*h(3)=4 VV1 0x75 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2988} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x76_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0x76 V66 V0F VL256 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2993}, +/*h(2)=1 VV1 0x76 V66 V0F VL128 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2991}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0x76 V66 V0F VL256 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2994}, +/*h(3)=4 VV1 0x76 V66 V0F VL128 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2992} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x77_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(19)=2 VV1 0x77 VNP V0F VL256 NOVSR*/ {19, 2684}, +/*h(3)=3 VV1 0x77 VNP V0F VL128 NOVSR*/ {3, 2685} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7c_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(13)=0 VV1 0x7C VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2693}, +/*h(5)=1 VV1 0x7C VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2691}, +/*h(10)=2 VV1 0x7C VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2688}, +/*h(2)=3 VV1 0x7C VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2686}, +/*empty slot1 */ {0,0}, +/*h(12)=5 VV1 0x7C VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2692}, +/*h(4)=6 VV1 0x7C VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2690}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=10 VV1 0x7C VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2689}, +/*h(3)=11 VV1 0x7C VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2687}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 13ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7d_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(13)=0 VV1 0x7D VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2701}, +/*h(5)=1 VV1 0x7D VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2699}, +/*h(10)=2 VV1 0x7D VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2696}, +/*h(2)=3 VV1 0x7D VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2694}, +/*empty slot1 */ {0,0}, +/*h(12)=5 VV1 0x7D VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2700}, +/*h(4)=6 VV1 0x7D VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2698}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=10 VV1 0x7D VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2697}, +/*h(3)=11 VV1 0x7D VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2695}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 13ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7e_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(123)=0 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {123, 2796}, +/*empty slot1 */ {0,0}, +/*h(115)=2 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {115, 2796}, +/*empty slot1 */ {0,0}, +/*h(251)=4 VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {251, 2806}, +/*h(120)=5 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {120, 2795}, +/*h(243)=6 VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {243, 2806}, +/*h(112)=7 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {112, 2795}, +/*h(125)=8 VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {125, 2804}, +/*h(248)=9 VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {248, 2805}, +/*h(117)=10 VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {117, 2800}, +/*h(240)=11 VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {240, 2805}, +/*h(253)=12 VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {253, 2806}, +/*h(122)=13 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {122, 2795}, +/*h(245)=14 VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {245, 2806}, +/*h(114)=15 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {114, 2795}, +/*empty slot1 */ {0,0}, +/*h(250)=17 VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {250, 2805}, +/*empty slot1 */ {0,0}, +/*h(242)=19 VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {242, 2805}, +/*empty slot1 */ {0,0}, +/*h(124)=21 VV1 0x7E VL128 V66 V0F mode64 rexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {124, 2803}, +/*empty slot1 */ {0,0}, +/*h(116)=23 VV1 0x7E VL128 V66 V0F mode64 norexw_prefix NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {116, 2799}, +/*empty slot1 */ {0,0}, +/*h(252)=25 VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {252, 2805}, +/*h(121)=26 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {121, 2796}, +/*h(244)=27 VV1 0x7E VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {244, 2805}, +/*h(113)=28 VV1 0x7E VL128 V66 V0F not64 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {113, 2796}, +/*empty slot1 */ {0,0}, +/*h(249)=30 VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {249, 2806}, +/*empty slot1 */ {0,0}, +/*h(241)=32 VV1 0x7E VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {241, 2806}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x7f_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(47)=0 VV1 0x7F VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2820}, +/*h(31)=1 VV1 0x7F VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2826}, +/*h(15)=2 VV1 0x7F VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2816}, +/*h(62)=3 VV1 0x7F VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2827}, +/*h(46)=4 VV1 0x7F VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2819}, +/*h(30)=5 VV1 0x7F VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2825}, +/*h(14)=6 VV1 0x7F VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2815}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=9 VV1 0x7F VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2828} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x90_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(13)=0 VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {13, 3862}, +/*h(31)=1 VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {31, 3890}, +/*h(15)=2 VV1 0x90 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {15, 3897}, +/*h(28)=3 VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR*/ {28, 3886}, +/*h(12)=4 VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR*/ {12, 3863}, +/*h(30)=5 VV1 0x90 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR*/ {30, 3891}, +/*h(14)=6 VV1 0x90 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR*/ {14, 3898}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(29)=9 VV1 0x90 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {29, 3885} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x91_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=2 VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR*/ {28, 3887}, +/*h(12)=3 VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOVSR*/ {12, 3864}, +/*h(30)=4 VV1 0x91 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR*/ {30, 3892}, +/*h(14)=5 VV1 0x91 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOVSR*/ {14, 3899}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x92_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*empty slot1 */ {0,0}, +/*h(115)=1 VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {115, 3888}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(49)=5 VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {49, 3865}, +/*h(117)=6 VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {117, 3888}, +/*h(185)=7 VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {185, 3894}, +/*h(177)=8 VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {177, 3894}, +/*empty slot1 */ {0,0}, +/*h(51)=10 VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {51, 3865}, +/*empty slot1 */ {0,0}, +/*h(187)=12 VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {187, 3894}, +/*h(179)=13 VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {179, 3894}, +/*empty slot1 */ {0,0}, +/*h(53)=15 VV1 0x92 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {53, 3865}, +/*h(189)=16 VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR*/ {189, 3900}, +/*h(113)=17 VV1 0x92 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {113, 3888}, +/*h(181)=18 VV1 0x92 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR*/ {181, 3893}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x93_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*empty slot1 */ {0,0}, +/*h(115)=1 VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {115, 3889}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(49)=5 VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {49, 3866}, +/*h(117)=6 VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {117, 3889}, +/*h(185)=7 VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {185, 3896}, +/*h(177)=8 VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {177, 3896}, +/*empty slot1 */ {0,0}, +/*h(51)=10 VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {51, 3866}, +/*empty slot1 */ {0,0}, +/*h(187)=12 VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {187, 3896}, +/*h(179)=13 VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 not64 NOVSR*/ {179, 3896}, +/*empty slot1 */ {0,0}, +/*h(53)=15 VV1 0x93 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {53, 3866}, +/*h(189)=16 VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 mode64 NOVSR*/ {189, 3901}, +/*h(113)=17 VV1 0x93 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {113, 3889}, +/*h(181)=18 VV1 0x93 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 mode64 NOVSR*/ {181, 3895}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x98_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(13)=0 VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {13, 3868}, +/*h(31)=1 VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {31, 3909}, +/*h(15)=2 VV1 0x98 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {15, 3910}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(29)=7 VV1 0x98 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {29, 3908} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0x99_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(13)=0 VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {13, 3920}, +/*h(31)=1 VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {31, 3918}, +/*h(15)=2 VV1 0x99 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W1 NOVSR*/ {15, 3919}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(29)=7 VV1 0x99 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] VL128 W0 NOVSR*/ {29, 3917} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xae_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(52)=0 VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {52, 3457}, +/*h(54)=1 VV1 0xAE VL128 VNP V0F NOVSR MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {54, 3458}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 VV1 0xC2 VNP VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {0, 2578}, +/*h(13)=1 VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {13, 2583}, +/*empty slot1 */ {0,0}, +/*h(5)=3 VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {5, 2583}, +/*empty slot1 */ {0,0}, +/*h(31)=5 VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {31, 2585}, +/*h(10)=6 VV1 0xC2 V66 VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 2576}, +/*h(23)=7 VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {23, 2585}, +/*h(2)=8 VV1 0xC2 V66 VL128 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 2574}, +/*h(15)=9 VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {15, 2585}, +/*h(28)=10 VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {28, 2582}, +/*h(7)=11 VV1 0xC2 VF3 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {7, 2585}, +/*h(20)=12 VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {20, 2582}, +/*empty slot1 */ {0,0}, +/*h(12)=14 VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {12, 2582}, +/*empty slot1 */ {0,0}, +/*h(4)=16 VV1 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {4, 2582}, +/*empty slot1 */ {0,0}, +/*h(30)=18 VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {30, 2584}, +/*h(9)=19 VV1 0xC2 VNP VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 2581}, +/*h(22)=20 VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {22, 2584}, +/*h(1)=21 VV1 0xC2 VNP VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1, 2579}, +/*h(14)=22 VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {14, 2584}, +/*empty slot1 */ {0,0}, +/*h(6)=24 VV1 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {6, 2584}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=27 VV1 0xC2 V66 VL256 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 2577}, +/*empty slot1 */ {0,0}, +/*h(3)=29 VV1 0xC2 V66 VL128 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 2575}, +/*empty slot1 */ {0,0}, +/*h(29)=31 VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {29, 2583}, +/*h(8)=32 VV1 0xC2 VNP VL256 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 2580}, +/*h(21)=33 VV1 0xC2 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {21, 2583} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc4_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 VV1 0xC4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {3428}, +/*h(3)=1 VV1 0xC4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3429} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = key - 2; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15)=0 VV1 0xC5 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3419} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 15; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xc6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 VV1 0xC6 VL128 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {0, 3181}, +/*h(10)=1 VV1 0xC6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {10, 3179}, +/*h(2)=2 VV1 0xC6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2, 3177}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(9)=5 VV1 0xC6 VL256 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {9, 3184}, +/*h(1)=6 VV1 0xC6 VL128 VNP V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {1, 3182}, +/*h(11)=7 VV1 0xC6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {11, 3180}, +/*h(3)=8 VV1 0xC6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {3, 3178}, +/*h(8)=9 VV1 0xC6 VL256 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {8, 3183} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd0_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(13)=0 VV1 0xD0 VL256 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2549}, +/*h(5)=1 VV1 0xD0 VL128 VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {5, 2547}, +/*h(10)=2 VV1 0xD0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2544}, +/*h(2)=3 VV1 0xD0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2542}, +/*empty slot1 */ {0,0}, +/*h(12)=5 VV1 0xD0 VL256 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2548}, +/*h(4)=6 VV1 0xD0 VL128 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {4, 2546}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=10 VV1 0xD0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2545}, +/*h(3)=11 VV1 0xD0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2543}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 13ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd1_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2916}, +/*h(2)=1 VV1 0xD1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2913}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2917}, +/*h(3)=4 VV1 0xD1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2914} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2922}, +/*h(2)=1 VV1 0xD2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2919}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2923}, +/*h(3)=4 VV1 0xD2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2920} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd3_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2928}, +/*h(2)=1 VV1 0xD3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2925}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2929}, +/*h(3)=4 VV1 0xD3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2926} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd4_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2957}, +/*h(2)=1 VV1 0xD4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2955}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2958}, +/*h(3)=4 VV1 0xD4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2956} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3053}, +/*h(2)=1 VV1 0xD5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3051}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3054}, +/*h(3)=4 VV1 0xD5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3052} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14)=0 VV1 0xD6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2807}, +/*h(15)=1 VV1 0xD6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2808} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 14; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(47)=0 VV1 0xD7 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 3366}, +/*h(15)=1 VV1 0xD7 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 3365}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3097}, +/*h(2)=1 VV1 0xD8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3095}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3098}, +/*h(3)=4 VV1 0xD8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3096} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xd9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xD9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3101}, +/*h(2)=1 VV1 0xD9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3099}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xD9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3102}, +/*h(3)=4 VV1 0xD9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3100} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xda_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3287}, +/*h(2)=1 VV1 0xDA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3285}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3288}, +/*h(3)=4 VV1 0xDA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3286} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2843}, +/*h(2)=1 VV1 0xDB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2841}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2844}, +/*h(3)=4 VV1 0xDB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2842} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdc_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2969}, +/*h(2)=1 VV1 0xDC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2967}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2970}, +/*h(3)=4 VV1 0xDC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2968} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdd_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2973}, +/*h(2)=1 VV1 0xDD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2971}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2974}, +/*h(3)=4 VV1 0xDD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2972} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xde_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3263}, +/*h(2)=1 VV1 0xDE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3261}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3264}, +/*h(3)=4 VV1 0xDE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3262} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xdf_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xDF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2847}, +/*h(2)=1 VV1 0xDF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2845}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xDF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2848}, +/*h(3)=4 VV1 0xDF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2846} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe0_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE0 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2977}, +/*h(2)=1 VV1 0xE0 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2975}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE0 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2978}, +/*h(3)=4 VV1 0xE0 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2976} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe1_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2934}, +/*h(2)=1 VV1 0xE1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2931}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2935}, +/*h(3)=4 VV1 0xE1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2932} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2940}, +/*h(2)=1 VV1 0xE2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2937}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2941}, +/*h(3)=4 VV1 0xE2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2938} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe3_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2981}, +/*h(2)=1 VV1 0xE3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2979}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2982}, +/*h(3)=4 VV1 0xE3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2980} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe4_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3041}, +/*h(2)=1 VV1 0xE4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3039}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3042}, +/*h(3)=4 VV1 0xE4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3040} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3049}, +/*h(2)=1 VV1 0xE5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3047}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3050}, +/*h(3)=4 VV1 0xE5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3048} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(47)=0 VV1 0xE6 VL256 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {47, 2605}, +/*empty slot1 */ {0,0}, +/*h(31)=2 VV1 0xE6 VL128 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {31, 2591}, +/*h(23)=3 VV1 0xE6 VL128 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {23, 2599}, +/*h(15)=4 VV1 0xE6 VL128 V66 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {15, 2603}, +/*h(62)=5 VV1 0xE6 VL256 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {62, 2592}, +/*h(54)=6 VV1 0xE6 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {54, 2600}, +/*h(46)=7 VV1 0xE6 VL256 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 2604}, +/*empty slot1 */ {0,0}, +/*h(30)=9 VV1 0xE6 VL128 VF3 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {30, 2590}, +/*h(22)=10 VV1 0xE6 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2598}, +/*h(14)=11 VV1 0xE6 VL128 V66 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 2602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(63)=15 VV1 0xE6 VL256 VF3 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {63, 2593}, +/*h(55)=16 VV1 0xE6 VL256 VF2 V0F NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {55, 2601} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(46)=0 VV1 0xE7 V66 V0F VL256 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {46, 3474}, +/*h(14)=1 VV1 0xE7 V66 V0F VL128 NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {14, 3473} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3089}, +/*h(2)=1 VV1 0xE8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3087}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3090}, +/*h(3)=4 VV1 0xE8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3088} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xe9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xE9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3093}, +/*h(2)=1 VV1 0xE9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3091}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xE9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3094}, +/*h(3)=4 VV1 0xE9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3092} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xea_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xEA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3279}, +/*h(2)=1 VV1 0xEA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3277}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xEA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3280}, +/*h(3)=4 VV1 0xEA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3278} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xeb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xEB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2839}, +/*h(2)=1 VV1 0xEB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2837}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xEB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2840}, +/*h(3)=4 VV1 0xEB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2838} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xec_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xEC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2961}, +/*h(2)=1 VV1 0xEC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2959}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xEC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2962}, +/*h(3)=4 VV1 0xEC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2960} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xed_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xED VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2965}, +/*h(2)=1 VV1 0xED VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2963}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xED VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2966}, +/*h(3)=4 VV1 0xED VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2964} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xee_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xEE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3255}, +/*h(2)=1 VV1 0xEE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3253}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xEE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3256}, +/*h(3)=4 VV1 0xEE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3254} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xef_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xEF VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2851}, +/*h(2)=1 VV1 0xEF VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2849}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xEF VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2852}, +/*h(3)=4 VV1 0xEF VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2850} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf0_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(54)=0 VV1 0xF0 VL256 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {54, 2732}, +/*h(22)=1 VV1 0xF0 VL128 VF2 V0F NOVSR MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {22, 2731} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf1_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF1 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2898}, +/*h(2)=1 VV1 0xF1 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2895}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF1 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2899}, +/*h(3)=4 VV1 0xF1 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2896} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf2_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF2 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2904}, +/*h(2)=1 VV1 0xF2 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2901}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF2 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2905}, +/*h(3)=4 VV1 0xF2 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2902} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf3_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF3 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2910}, +/*h(2)=1 VV1 0xF3 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2907}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF3 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2911}, +/*h(3)=4 VV1 0xF3 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2908} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf4_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF4 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3061}, +/*h(2)=1 VV1 0xF4 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3059}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF4 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3062}, +/*h(3)=4 VV1 0xF4 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3060} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf5_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF5 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3299}, +/*h(2)=1 VV1 0xF5 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3297}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF5 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3300}, +/*h(3)=4 VV1 0xF5 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3298} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf6_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF6 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3069}, +/*h(2)=1 VV1 0xF6 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3067}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF6 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3070}, +/*h(3)=4 VV1 0xF6 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3068} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf7_vv1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15)=0 VV1 0xF7 V0F V66 VL128 NOVSR MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3456} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 15; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf8_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF8 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3105}, +/*h(2)=1 VV1 0xF8 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3103}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF8 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3106}, +/*h(3)=4 VV1 0xF8 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3104} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xf9_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xF9 VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3109}, +/*h(2)=1 VV1 0xF9 VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3107}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xF9 VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3110}, +/*h(3)=4 VV1 0xF9 VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3108} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfa_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xFA VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3113}, +/*h(2)=1 VV1 0xFA VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3111}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xFA VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3114}, +/*h(3)=4 VV1 0xFA VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3112} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfb_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xFB VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 3117}, +/*h(2)=1 VV1 0xFB VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 3115}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xFB VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 3118}, +/*h(3)=4 VV1 0xFB VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 3116} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfc_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xFC VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2945}, +/*h(2)=1 VV1 0xFC VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2943}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xFC VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2946}, +/*h(3)=4 VV1 0xFC VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2944} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfd_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xFD VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2949}, +/*h(2)=1 VV1 0xFD VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2947}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xFD VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2950}, +/*h(3)=4 VV1 0xFD VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2948} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapvex_map1_opcode0xfe_vv1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 VV1 0xFE VL256 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {10, 2953}, +/*h(2)=1 VV1 0xFE VL128 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2, 2951}, +/*empty slot1 */ {0,0}, +/*h(11)=3 VV1 0xFE VL256 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {11, 2954}, +/*h(3)=4 VV1 0xFE VL128 V66 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {3, 2952} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-vv2.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv2.h new file mode 100644 index 0000000..c388899 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv2.h @@ -0,0 +1,140344 @@ +/// @file include-private/xed3-phash-vv2.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_VV2_H) +# define INCLUDE_PRIVATE_XED3_PHASH_VV2_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-operand-lu.h" +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x0_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x10_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x11_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x12_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x13_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x14_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x15_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x16_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x18_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x19_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x20_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x21_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x22_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x23_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x24_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x25_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x26_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x27_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x29_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x30_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x31_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x32_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x33_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x34_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x35_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x36_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x37_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x38_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x40_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x42_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x43_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x44_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x45_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x46_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x47_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x50_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x51_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x52_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x53_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x54_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x55_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x58_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x59_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x5a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x5b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x62_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x63_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x64_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x65_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x66_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x68_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x70_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x71_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x72_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x73_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x75_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x76_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x77_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x78_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x79_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x83_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x88_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x89_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x90_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x91_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x92_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x93_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x96_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x97_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x98_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x99_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa0_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa1_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa2_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa3_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xaa_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xab_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xac_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xad_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xae_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xaf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb5_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xba_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbe_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xca_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xdc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xdd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xde_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xdf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x0_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x5_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xa_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x14_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x15_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x16_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x17_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x18_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x19_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x20_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x21_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x22_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x23_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x25_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x26_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x27_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x38_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x39_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x42_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x43_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x44_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x50_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x51_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x54_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x55_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x56_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x57_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x66_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x67_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x70_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x71_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x72_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x73_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xc2_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xce_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xcf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x10_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x11_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x1d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x58_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x59_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x6e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_516_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_563_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_550_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_221_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_582_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_316_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_645_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_384_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_663_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_367_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_647_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_606_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_389_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_543_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_523_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_616_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_701_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_85_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_570_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_491_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_638_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_538_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_633_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_450_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_287_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_684_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_664_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_723_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_487_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_677_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_482_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_530_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_689_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_204_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_262_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_731_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x13_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x2c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x2d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x42_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x43_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x56_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x57_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x96_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x97_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x98_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x99_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xaa_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xab_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xac_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xad_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xae_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xaf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xba_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbe_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xd6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xd7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_97_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_2_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_4_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_45_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x13_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x14_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x15_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x16_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x17_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x28_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x29_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x54_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x55_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x56_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x57_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x58_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x59_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_155_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_79_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_26_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_53_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_30_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_40_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_65_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_56_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_1_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_148_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_38_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_160_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_72_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_11_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_35_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x60_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x61_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x62_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x63_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x64_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x65_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x66_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x67_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x68_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x69_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6c_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6d_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x70_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x71_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x72_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x73_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x74_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x75_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x76_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_93_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_10_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_693_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_83_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_649_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_552_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_818_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1164_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_983_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_944_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_54_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_722_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_625_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_293_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_737_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1015_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_683_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_796_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_600_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1044_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_849_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_713_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1230_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1035_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1479_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_869_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_642_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_715_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_579_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_976_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_781_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_698_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_947_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_810_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_615_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_171_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_88_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1049_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1162_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1091_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_896_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_564_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1008_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_813_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_593_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_940_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_720_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_525_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_81_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1208_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_876_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_17_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_783_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_588_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_937_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_298_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_20_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1425_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_756_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_561_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1005_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_922_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_913_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1078_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_942_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_520_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_981_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_883_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_688_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_8_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1398_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_815_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_620_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_22_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_969_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_539_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1039_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_788_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_554_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_971_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1069_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_303_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1376_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1139_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_808_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1461_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1130_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_86_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_964_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_659_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_493_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_49_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1010_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_556_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_905_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_71_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_393_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_198_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1178_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_569_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_817_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1032_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_878_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_547_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_348_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_711_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1058_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_960_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_167_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_84_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_475_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_507_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1216_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_60_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_704_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_833_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1050_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_953_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1082_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_719_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_967_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_611_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_643_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_545_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_67_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_99_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_777_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_679_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_738_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_74_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_557_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_784_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_686_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_935_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_733_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1330_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_157_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_852_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_650_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_672_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1033_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_899_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_801_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_675_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1471_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_695_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1046_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_851_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_768_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1337_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_892_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_366_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_532_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1019_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1473_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1112_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_253_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_502_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1041_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_958_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_822_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_627_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_978_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_895_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_31_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_951_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1063_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_634_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_607_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_636_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_597_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_836_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1085_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_517_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_629_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_656_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_729_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_790_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_946_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_863_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1073_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_990_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_897_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_702_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1053_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1290_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1207_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_568_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_431_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_153_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_890_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_714_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1017_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1380_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_602_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_407_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_770_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_312_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_775_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1024_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_692_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1375_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7a_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_841_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_61_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1135_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_769_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_379_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1453_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1000_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_610_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1294_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_927_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_537_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_873_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_483_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_506_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_800_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1031_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_641_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_665_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1349_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_959_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_515_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1199_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_809_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_832_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_52_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1126_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_674_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_968_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_991_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_601_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1285_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_936_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_546_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_180_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_864_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_474_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_21_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1095_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_705_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1022_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_632_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_760_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1054_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1077_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_687_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1371_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_918_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_528_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1212_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_846_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_456_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_66_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_791_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_34_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1108_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_718_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_266_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_950_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_560_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_583_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_877_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_43_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1117_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_727_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_751_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_361_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1045_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_592_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_886_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_909_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_519_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1203_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_855_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_465_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_75_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_98_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_782_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1013_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_623_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_941_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_551_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_282_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_966_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_576_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_599_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_209_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_893_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_51_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1125_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_735_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_758_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_368_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1442_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1052_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1093_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_703_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1387_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1411_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1021_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_631_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_241_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1252_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_862_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_472_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_82_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_105_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1179_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_789_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1420_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1030_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_640_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_273_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1347_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_957_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_567_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_798_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_42_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1116_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_726_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_767_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_377_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1451_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1061_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1084_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_694_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1378_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_926_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_536_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_146_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1220_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1243_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_853_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_463_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_73_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1275_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_885_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_495_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_518_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_128_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1202_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_812_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_359_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1433_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1043_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_653_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_676_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_286_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_970_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1012_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_622_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_939_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_549_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_159_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_780_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_0_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_24_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1098_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_708_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_318_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1338_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_948_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_558_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_191_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_875_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_485_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_33_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1107_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_717_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_327_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_350_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1424_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1034_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_644_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_685_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1370_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_980_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1003_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_613_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_223_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1297_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_844_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_454_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_64_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1138_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_771_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_381_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_678_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1362_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_972_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_995_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_605_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1289_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_837_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_57_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1131_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_764_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1448_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_25_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1099_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_709_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_343_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1027_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_637_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_868_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_478_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_501_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1185_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_795_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_119_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1193_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_803_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_413_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_436_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_46_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_730_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_962_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_572_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_595_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_205_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_889_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_930_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_540_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1248_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_858_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_468_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_78_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1089_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_699_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1016_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_626_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_236_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_834_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_444_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_467_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_77_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_761_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_993_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_603_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_920_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_961_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_571_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_181_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_499_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_109_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_340_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1414_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1047_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_657_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_267_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1288_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_898_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_508_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_141_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1215_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_825_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_435_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1446_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1056_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_666_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_276_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1374_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_984_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_594_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_635_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_245_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1319_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_929_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_952_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_562_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_172_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_794_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_404_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_14_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1088_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1111_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_721_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_331_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1405_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_69_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_753_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_363_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_386_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1070_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_680_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_911_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_521_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_544_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_154_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_838_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_880_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_490_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1174_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_807_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_417_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_27_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1038_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_648_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_258_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_186_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_816_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_36_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_59_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1133_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_743_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_975_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_585_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_195_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_218_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_902_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_512_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_553_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1237_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_847_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_871_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_481_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_91_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_712_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1006_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1029_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_639_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1323_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_671_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_281_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_988_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_598_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_830_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_440_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1147_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_757_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_18_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1092_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_725_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_336_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1410_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1251_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1274_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_884_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_494_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_104_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_352_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1426_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1036_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_646_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_669_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_279_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1353_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_963_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_510_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_120_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1194_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_804_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_828_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_48_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1122_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1163_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_773_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_383_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1457_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_16_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1090_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_700_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_310_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1322_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_932_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_542_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1249_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_859_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_469_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1257_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_867_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_477_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_87_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_110_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1184_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1025_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_268_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_604_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_921_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_531_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_763_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_373_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1447_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1057_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1080_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_690_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_662_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_272_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_503_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_820_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1156_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_766_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_9_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1083_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1315_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_925_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1242_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_12_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1086_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_696_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_306_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_329_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_170_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1244_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_854_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_464_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_488_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_823_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_750_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_360_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1434_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_982_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1299_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1149_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_759_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1443_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_3_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_161_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1235_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_845_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_455_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_497_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_814_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_655_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_265_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1339_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_949_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_973_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1394_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1004_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_614_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_224_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1321_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_931_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_541_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_89_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_406_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_742_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1059_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_900_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1217_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_827_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_437_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_47_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1068_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1385_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1227_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_80_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_415_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_732_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_342_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1026_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_574_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_891_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1313_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_923_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_533_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_143_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_850_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_460_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_7_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1081_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_691_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_301_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_325_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1399_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1009_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_619_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_660_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_954_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_977_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_587_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_197_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1271_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_819_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_429_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_39_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1113_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1136_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_746_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_356_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1430_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_917_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_527_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1211_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1075_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_295_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1369_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1392_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1002_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_612_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_222_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_581_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_423_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_740_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_590_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_200_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_908_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_749_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1066_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_255_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_96_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_23_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1097_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_707_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_835_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_445_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_55_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1129_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1152_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_762_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_372_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_994_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1311_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1256_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_866_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_476_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_500_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_341_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_658_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_509_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_826_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_667_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_277_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_985_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_173_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1247_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_857_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_15_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_332_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1071_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_681_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_291_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_912_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_522_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1229_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_839_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_449_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_101_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1175_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_785_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_395_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_418_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_28_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_259_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1333_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_943_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_577_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_187_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_5_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1079_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1260_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_870_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_480_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_90_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_608_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_458_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_68_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1142_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_752_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_776_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_617_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_934_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1270_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_123_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1428_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1355_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_965_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_575_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_997_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1020_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_630_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_240_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1314_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_50_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1124_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_734_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_344_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_526_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_535_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_829_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_41_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_621_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_231_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1305_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_915_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1233_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1074_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_317_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1391_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_263_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_580_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_127_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1201_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_811_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_421_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_739_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_986_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_596_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_206_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1280_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1304_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_914_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_524_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_134_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1145_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_755_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_365_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1439_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1462_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1072_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_682_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_292_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_334_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1408_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1018_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_628_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_651_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_261_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1335_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_945_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_492_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_102_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_786_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_419_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_29_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1103_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_427_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_37_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_744_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_354_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_586_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_903_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_513_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_848_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_92_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1166_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1007_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1324_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_979_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_589_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1296_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_906_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_748_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1065_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_716_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_326_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1400_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_254_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_95_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1192_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_802_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_412_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_505_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_409_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_246_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_754_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_673_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_591_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1278_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1182_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1196_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1100_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1114_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_63_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_555_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_459_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1064_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_901_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_805_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_115_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_19_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1401_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_364_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_283_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_888_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_792_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_806_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_710_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_724_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1137_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_974_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_151_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_165_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_578_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_496_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_511_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1189_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1011_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_70_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1438_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1357_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_924_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_534_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_144_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1328_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1232_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_938_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_842_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_548_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_452_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_158_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_62_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1150_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_856_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_466_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_76_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1269_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_879_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_489_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_210_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1284_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_894_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_504_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_32_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_422_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_498_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_402_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_416_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_320_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_238_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_843_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_747_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_584_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1225_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1239_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_188_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_106_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_121_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_831_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_654_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_668_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1177_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_999_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1014_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_140_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_44_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_58_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1441_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1345_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_486_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_308_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_226_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_882_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1390_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1309_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1213_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_787_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_609_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_624_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1214_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1118_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1132_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1051_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_955_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1382_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1300_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_559_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_573_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_396_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_904_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_919_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_741_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_397_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_219_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_234_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_176_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1346_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1250_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_956_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_860_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_566_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_470_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_190_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_94_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1264_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1168_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_874_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_778_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_484_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_388_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_13_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1087_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_793_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_697_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_403_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_307_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_618_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_228_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1302_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_358_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1432_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1042_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_652_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_824_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_728_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_661_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_565_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_992_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_910_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_169_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_183_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_6_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_514_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_529_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_351_l1(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7e_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7f_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc2_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc5_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd1_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd2_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd3_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd5_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xda_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xde_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdf_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe0_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe1_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe2_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe3_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe5_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe7_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xea_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xeb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xec_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xed_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xee_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xef_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf1_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf2_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf3_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf4_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf5_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf6_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf8_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf9_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfa_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfb_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfc_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfd_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfe_vv2(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x0_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6596}, +/*h(4)=1 EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6595}, +/*h(38)=2 EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6598}, +/*h(20)=3 EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6597}, +/*h(6)=4 EVV 0x00 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6594}, +/*h(36)=5 EVV 0x00 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6446}, +/*h(4)=1 EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6445}, +/*h(38)=2 EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6448}, +/*h(20)=3 EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6447}, +/*h(6)=4 EVV 0x04 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6444}, +/*h(36)=5 EVV 0x04 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6449} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6560}, +/*h(4)=1 EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6559}, +/*h(38)=2 EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6562}, +/*h(20)=3 EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6561}, +/*h(6)=4 EVV 0x0B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6558}, +/*h(36)=5 EVV 0x0B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6563} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5255}, +/*h(10)=3 EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5258}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5263}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5255}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5259}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5263}, +/*h(74)=13 EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5254}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x0C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5259}, +/*h(42)=17 EVV 0x0C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5262} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5243}, +/*h(46)=1 EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5250}, +/*h(12)=2 EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5247}, +/*h(77)=3 EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5243}, +/*h(13)=4 EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5247}, +/*h(78)=5 EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5242}, +/*h(44)=6 EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5251}, +/*h(14)=7 EVV 0x0D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5246}, +/*h(45)=8 EVV 0x0D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x10_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[210] = { +/*h(1654)=0 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1654, 6664}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1388)=4 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1388, 6663}, +/*empty slot1 */ {0,0}, +/*h(124)=6 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {124, 6661}, +/*h(1754)=7 EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 6541}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=10 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {86, 6660}, +/*h(1108)=11 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1108, 6661}, +/*h(628)=12 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {628, 6665}, +/*empty slot1 */ {0,0}, +/*h(1398)=14 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1398, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1612)=17 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1612, 6665}, +/*h(1132)=18 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1132, 6661}, +/*h(728)=19 EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {728, 6542}, +/*empty slot1 */ {0,0}, +/*h(1498)=21 EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 6539}, +/*h(638)=22 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {638, 6664}, +/*empty slot1 */ {0,0}, +/*h(1636)=24 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1636, 6665}, +/*empty slot1 */ {0,0}, +/*h(372)=26 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {372, 6663}, +/*h(1622)=27 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1622, 6664}, +/*h(1142)=28 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1142, 6660}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1356)=31 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1356, 6663}, +/*empty slot1 */ {0,0}, +/*h(472)=33 EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {472, 6540}, +/*h(1646)=34 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1646, 6664}, +/*h(1242)=35 EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 6537}, +/*h(382)=36 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {382, 6662}, +/*empty slot1 */ {0,0}, +/*h(1380)=38 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1380, 6663}, +/*h(596)=39 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {596, 6665}, +/*h(116)=40 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {116, 6661}, +/*h(1366)=41 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1366, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1100)=45 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1100, 6661}, +/*h(620)=46 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {620, 6665}, +/*h(216)=47 EVV 0x10 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {216, 6538}, +/*h(1390)=48 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1390, 6662}, +/*empty slot1 */ {0,0}, +/*h(126)=50 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {126, 6660}, +/*h(1604)=51 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1604, 6665}, +/*h(1124)=52 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1124, 6661}, +/*h(340)=53 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {340, 6663}, +/*empty slot1 */ {0,0}, +/*h(1110)=55 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1110, 6660}, +/*h(630)=56 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {630, 6664}, +/*empty slot1 */ {0,0}, +/*h(1628)=58 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1628, 6665}, +/*empty slot1 */ {0,0}, +/*h(364)=60 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {364, 6663}, +/*h(1614)=61 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1614, 6664}, +/*h(1134)=62 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1134, 6660}, +/*h(730)=63 EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 6541}, +/*empty slot1 */ {0,0}, +/*h(1348)=65 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1348, 6663}, +/*empty slot1 */ {0,0}, +/*h(84)=67 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {84, 6661}, +/*h(1638)=68 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1638, 6664}, +/*empty slot1 */ {0,0}, +/*h(374)=70 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {374, 6662}, +/*empty slot1 */ {0,0}, +/*h(1372)=72 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1372, 6663}, +/*h(588)=73 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {588, 6665}, +/*h(108)=74 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {108, 6661}, +/*h(1358)=75 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1358, 6662}, +/*empty slot1 */ {0,0}, +/*h(474)=77 EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 6539}, +/*empty slot1 */ {0,0}, +/*h(1092)=79 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1092, 6661}, +/*h(612)=80 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {612, 6665}, +/*empty slot1 */ {0,0}, +/*h(1382)=82 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1382, 6662}, +/*h(598)=83 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {598, 6664}, +/*h(118)=84 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {118, 6660}, +/*empty slot1 */ {0,0}, +/*h(1116)=86 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1116, 6661}, +/*h(332)=87 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {332, 6663}, +/*empty slot1 */ {0,0}, +/*h(1102)=89 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1102, 6660}, +/*h(622)=90 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {622, 6664}, +/*h(218)=91 EVV 0x10 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 6537}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(356)=94 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {356, 6663}, +/*h(1606)=95 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1606, 6664}, +/*h(1126)=96 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1126, 6660}, +/*h(342)=97 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {342, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=101 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6661}, +/*h(1630)=102 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1630, 6664}, +/*empty slot1 */ {0,0}, +/*h(366)=104 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {366, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(580)=107 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {580, 6665}, +/*h(100)=108 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {100, 6661}, +/*h(1350)=109 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1350, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=114 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {604, 6665}, +/*empty slot1 */ {0,0}, +/*h(1374)=116 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1374, 6662}, +/*h(590)=117 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {590, 6664}, +/*h(110)=118 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {110, 6660}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(324)=121 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {324, 6663}, +/*empty slot1 */ {0,0}, +/*h(1094)=123 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1094, 6660}, +/*h(614)=124 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {614, 6664}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(348)=128 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {348, 6663}, +/*empty slot1 */ {0,0}, +/*h(1118)=130 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1118, 6660}, +/*h(334)=131 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {334, 6662}, +/*h(1660)=132 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1660, 6665}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(68)=135 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {68, 6661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(358)=138 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {358, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=142 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {92, 6661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=145 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {78, 6660}, +/*h(1404)=146 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1404, 6663}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(582)=151 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {582, 6664}, +/*h(102)=152 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {102, 6660}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=158 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {606, 6664}, +/*empty slot1 */ {0,0}, +/*h(1148)=160 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1148, 6661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(326)=165 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {326, 6662}, +/*h(1652)=166 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1652, 6665}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=172 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {350, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1662)=176 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1662, 6664}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(70)=179 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {70, 6660}, +/*h(1396)=180 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1396, 6663}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=186 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {94, 6660}, +/*empty slot1 */ {0,0}, +/*h(636)=188 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {636, 6665}, +/*empty slot1 */ {0,0}, +/*h(1406)=190 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1406, 6662}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1620)=193 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1620, 6665}, +/*h(1140)=194 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1140, 6661}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1644)=200 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1644, 6665}, +/*empty slot1 */ {0,0}, +/*h(380)=202 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {380, 6663}, +/*empty slot1 */ {0,0}, +/*h(1150)=204 EVV 0x10 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1150, 6660}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1364)=207 EVV 0x10 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1364, 6663}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((22*key % 941) % 210); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x11_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[210] = { +/*h(1654)=0 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1654, 6640}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1388)=4 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1388, 6639}, +/*empty slot1 */ {0,0}, +/*h(124)=6 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {124, 6637}, +/*h(1754)=7 EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5470}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=10 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {86, 6636}, +/*h(1108)=11 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1108, 6637}, +/*h(628)=12 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {628, 6641}, +/*empty slot1 */ {0,0}, +/*h(1398)=14 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1398, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1612)=17 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1612, 6641}, +/*h(1132)=18 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1132, 6637}, +/*h(728)=19 EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {728, 5471}, +/*empty slot1 */ {0,0}, +/*h(1498)=21 EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5474}, +/*h(638)=22 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {638, 6640}, +/*empty slot1 */ {0,0}, +/*h(1636)=24 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1636, 6641}, +/*empty slot1 */ {0,0}, +/*h(372)=26 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {372, 6639}, +/*h(1622)=27 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1622, 6640}, +/*h(1142)=28 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1142, 6636}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1356)=31 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1356, 6639}, +/*empty slot1 */ {0,0}, +/*h(472)=33 EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {472, 5475}, +/*h(1646)=34 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1646, 6640}, +/*h(1242)=35 EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5472}, +/*h(382)=36 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {382, 6638}, +/*empty slot1 */ {0,0}, +/*h(1380)=38 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1380, 6639}, +/*h(596)=39 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {596, 6641}, +/*h(116)=40 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {116, 6637}, +/*h(1366)=41 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1366, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1100)=45 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1100, 6637}, +/*h(620)=46 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {620, 6641}, +/*h(216)=47 EVV 0x11 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {216, 5473}, +/*h(1390)=48 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1390, 6638}, +/*empty slot1 */ {0,0}, +/*h(126)=50 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {126, 6636}, +/*h(1604)=51 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1604, 6641}, +/*h(1124)=52 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1124, 6637}, +/*h(340)=53 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {340, 6639}, +/*empty slot1 */ {0,0}, +/*h(1110)=55 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1110, 6636}, +/*h(630)=56 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {630, 6640}, +/*empty slot1 */ {0,0}, +/*h(1628)=58 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1628, 6641}, +/*empty slot1 */ {0,0}, +/*h(364)=60 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {364, 6639}, +/*h(1614)=61 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1614, 6640}, +/*h(1134)=62 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1134, 6636}, +/*h(730)=63 EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5470}, +/*empty slot1 */ {0,0}, +/*h(1348)=65 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1348, 6639}, +/*empty slot1 */ {0,0}, +/*h(84)=67 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {84, 6637}, +/*h(1638)=68 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1638, 6640}, +/*empty slot1 */ {0,0}, +/*h(374)=70 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {374, 6638}, +/*empty slot1 */ {0,0}, +/*h(1372)=72 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1372, 6639}, +/*h(588)=73 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {588, 6641}, +/*h(108)=74 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {108, 6637}, +/*h(1358)=75 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1358, 6638}, +/*empty slot1 */ {0,0}, +/*h(474)=77 EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5474}, +/*empty slot1 */ {0,0}, +/*h(1092)=79 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1092, 6637}, +/*h(612)=80 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {612, 6641}, +/*empty slot1 */ {0,0}, +/*h(1382)=82 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1382, 6638}, +/*h(598)=83 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {598, 6640}, +/*h(118)=84 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {118, 6636}, +/*empty slot1 */ {0,0}, +/*h(1116)=86 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1116, 6637}, +/*h(332)=87 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {332, 6639}, +/*empty slot1 */ {0,0}, +/*h(1102)=89 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1102, 6636}, +/*h(622)=90 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {622, 6640}, +/*h(218)=91 EVV 0x11 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5472}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(356)=94 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {356, 6639}, +/*h(1606)=95 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1606, 6640}, +/*h(1126)=96 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1126, 6636}, +/*h(342)=97 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {342, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=101 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6637}, +/*h(1630)=102 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1630, 6640}, +/*empty slot1 */ {0,0}, +/*h(366)=104 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {366, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(580)=107 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {580, 6641}, +/*h(100)=108 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {100, 6637}, +/*h(1350)=109 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1350, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=114 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {604, 6641}, +/*empty slot1 */ {0,0}, +/*h(1374)=116 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1374, 6638}, +/*h(590)=117 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {590, 6640}, +/*h(110)=118 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {110, 6636}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(324)=121 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {324, 6639}, +/*empty slot1 */ {0,0}, +/*h(1094)=123 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1094, 6636}, +/*h(614)=124 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {614, 6640}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(348)=128 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {348, 6639}, +/*empty slot1 */ {0,0}, +/*h(1118)=130 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1118, 6636}, +/*h(334)=131 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {334, 6638}, +/*h(1660)=132 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1660, 6641}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(68)=135 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {68, 6637}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(358)=138 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {358, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=142 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {92, 6637}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=145 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {78, 6636}, +/*h(1404)=146 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1404, 6639}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(582)=151 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {582, 6640}, +/*h(102)=152 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {102, 6636}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=158 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {606, 6640}, +/*empty slot1 */ {0,0}, +/*h(1148)=160 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1148, 6637}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(326)=165 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {326, 6638}, +/*h(1652)=166 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1652, 6641}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=172 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {350, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1662)=176 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1662, 6640}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(70)=179 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {70, 6636}, +/*h(1396)=180 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1396, 6639}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=186 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {94, 6636}, +/*empty slot1 */ {0,0}, +/*h(636)=188 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {636, 6641}, +/*empty slot1 */ {0,0}, +/*h(1406)=190 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1406, 6638}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1620)=193 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1620, 6641}, +/*h(1140)=194 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1140, 6637}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1644)=200 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1644, 6641}, +/*empty slot1 */ {0,0}, +/*h(380)=202 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {380, 6639}, +/*empty slot1 */ {0,0}, +/*h(1150)=204 EVV 0x11 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1150, 6636}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1364)=207 EVV 0x11 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1364, 6639}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((22*key % 941) % 210); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x12_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[210] = { +/*h(1654)=0 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1654, 6622}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1388)=4 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1388, 6621}, +/*empty slot1 */ {0,0}, +/*h(124)=6 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {124, 6619}, +/*h(1754)=7 EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=10 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {86, 6618}, +/*h(1108)=11 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1108, 6619}, +/*h(628)=12 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {628, 6623}, +/*empty slot1 */ {0,0}, +/*h(1398)=14 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1398, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1612)=17 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1612, 6623}, +/*h(1132)=18 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1132, 6619}, +/*h(728)=19 EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {728, 5483}, +/*empty slot1 */ {0,0}, +/*h(1498)=21 EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5486}, +/*h(638)=22 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {638, 6622}, +/*empty slot1 */ {0,0}, +/*h(1636)=24 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1636, 6623}, +/*empty slot1 */ {0,0}, +/*h(372)=26 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {372, 6621}, +/*h(1622)=27 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1622, 6622}, +/*h(1142)=28 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1142, 6618}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1356)=31 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1356, 6621}, +/*empty slot1 */ {0,0}, +/*h(472)=33 EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {472, 5487}, +/*h(1646)=34 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1646, 6622}, +/*h(1242)=35 EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5484}, +/*h(382)=36 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {382, 6620}, +/*empty slot1 */ {0,0}, +/*h(1380)=38 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1380, 6621}, +/*h(596)=39 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {596, 6623}, +/*h(116)=40 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {116, 6619}, +/*h(1366)=41 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1366, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1100)=45 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1100, 6619}, +/*h(620)=46 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {620, 6623}, +/*h(216)=47 EVV 0x12 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {216, 5485}, +/*h(1390)=48 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1390, 6620}, +/*empty slot1 */ {0,0}, +/*h(126)=50 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {126, 6618}, +/*h(1604)=51 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1604, 6623}, +/*h(1124)=52 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1124, 6619}, +/*h(340)=53 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {340, 6621}, +/*empty slot1 */ {0,0}, +/*h(1110)=55 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1110, 6618}, +/*h(630)=56 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {630, 6622}, +/*empty slot1 */ {0,0}, +/*h(1628)=58 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1628, 6623}, +/*empty slot1 */ {0,0}, +/*h(364)=60 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {364, 6621}, +/*h(1614)=61 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1614, 6622}, +/*h(1134)=62 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1134, 6618}, +/*h(730)=63 EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5482}, +/*empty slot1 */ {0,0}, +/*h(1348)=65 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1348, 6621}, +/*empty slot1 */ {0,0}, +/*h(84)=67 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {84, 6619}, +/*h(1638)=68 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1638, 6622}, +/*empty slot1 */ {0,0}, +/*h(374)=70 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {374, 6620}, +/*empty slot1 */ {0,0}, +/*h(1372)=72 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1372, 6621}, +/*h(588)=73 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {588, 6623}, +/*h(108)=74 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {108, 6619}, +/*h(1358)=75 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1358, 6620}, +/*empty slot1 */ {0,0}, +/*h(474)=77 EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5486}, +/*empty slot1 */ {0,0}, +/*h(1092)=79 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1092, 6619}, +/*h(612)=80 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {612, 6623}, +/*empty slot1 */ {0,0}, +/*h(1382)=82 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1382, 6620}, +/*h(598)=83 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {598, 6622}, +/*h(118)=84 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {118, 6618}, +/*empty slot1 */ {0,0}, +/*h(1116)=86 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1116, 6619}, +/*h(332)=87 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {332, 6621}, +/*empty slot1 */ {0,0}, +/*h(1102)=89 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1102, 6618}, +/*h(622)=90 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {622, 6622}, +/*h(218)=91 EVV 0x12 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(356)=94 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {356, 6621}, +/*h(1606)=95 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1606, 6622}, +/*h(1126)=96 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1126, 6618}, +/*h(342)=97 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {342, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=101 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6619}, +/*h(1630)=102 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1630, 6622}, +/*empty slot1 */ {0,0}, +/*h(366)=104 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {366, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(580)=107 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {580, 6623}, +/*h(100)=108 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {100, 6619}, +/*h(1350)=109 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1350, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=114 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {604, 6623}, +/*empty slot1 */ {0,0}, +/*h(1374)=116 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1374, 6620}, +/*h(590)=117 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {590, 6622}, +/*h(110)=118 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {110, 6618}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(324)=121 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {324, 6621}, +/*empty slot1 */ {0,0}, +/*h(1094)=123 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1094, 6618}, +/*h(614)=124 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {614, 6622}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(348)=128 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {348, 6621}, +/*empty slot1 */ {0,0}, +/*h(1118)=130 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1118, 6618}, +/*h(334)=131 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {334, 6620}, +/*h(1660)=132 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1660, 6623}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(68)=135 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {68, 6619}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(358)=138 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {358, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=142 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {92, 6619}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=145 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {78, 6618}, +/*h(1404)=146 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1404, 6621}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(582)=151 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {582, 6622}, +/*h(102)=152 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {102, 6618}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=158 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {606, 6622}, +/*empty slot1 */ {0,0}, +/*h(1148)=160 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1148, 6619}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(326)=165 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {326, 6620}, +/*h(1652)=166 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1652, 6623}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=172 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {350, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1662)=176 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1662, 6622}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(70)=179 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {70, 6618}, +/*h(1396)=180 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1396, 6621}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=186 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {94, 6618}, +/*empty slot1 */ {0,0}, +/*h(636)=188 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {636, 6623}, +/*empty slot1 */ {0,0}, +/*h(1406)=190 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1406, 6620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1620)=193 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1620, 6623}, +/*h(1140)=194 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1140, 6619}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1644)=200 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1644, 6623}, +/*empty slot1 */ {0,0}, +/*h(380)=202 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {380, 6621}, +/*empty slot1 */ {0,0}, +/*h(1150)=204 EVV 0x12 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1150, 6618}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1364)=207 EVV 0x12 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1364, 6621}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((22*key % 941) % 210); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x13_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[58] = { +/*h(472)=0 EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {472, 5481}, +/*empty slot1 */ {0,0}, +/*h(602)=2 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4208}, +/*empty slot1 */ {0,0}, +/*h(344)=4 EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {344, 4214}, +/*h(603)=5 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 4209}, +/*h(474)=6 EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5480}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {216, 5479}, +/*empty slot1 */ {0,0}, +/*h(346)=10 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4213}, +/*empty slot1 */ {0,0}, +/*h(88)=12 EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {88, 4212}, +/*h(347)=13 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 4209}, +/*h(218)=14 EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5478}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=18 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4211}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=21 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 4209}, +/*h(1624)=22 EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1624, 4210}, +/*h(1883)=23 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1883, 4209}, +/*h(1754)=24 EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5476}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1626)=28 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 4208}, +/*empty slot1 */ {0,0}, +/*h(1368)=30 EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1368, 4214}, +/*h(1627)=31 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1627, 4209}, +/*h(1498)=32 EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=36 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 4213}, +/*empty slot1 */ {0,0}, +/*h(1112)=38 EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1112, 4212}, +/*h(1371)=39 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1371, 4209}, +/*h(1242)=40 EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5478}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1114)=44 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 4211}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1115)=47 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1115, 4209}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(728)=50 EVV 0x13 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {728, 5477}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=54 EVV 0x13 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {600, 4210}, +/*h(859)=55 EVV 0x13 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 4209}, +/*h(730)=56 EVV 0x13 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5476}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 97) % 58); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x14_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[594] = { +/*h(598)=0 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {598, 5602}, +/*h(120)=1 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {120, 5599}, +/*empty slot1 */ {0,0}, +/*h(360)=3 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {360, 5601}, +/*empty slot1 */ {0,0}, +/*h(600)=5 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {600, 5597}, +/*h(121)=6 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {121, 5599}, +/*empty slot1 */ {0,0}, +/*h(361)=8 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {361, 5601}, +/*empty slot1 */ {0,0}, +/*h(601)=10 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {601, 5597}, +/*h(122)=11 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {122, 5598}, +/*empty slot1 */ {0,0}, +/*h(362)=13 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {362, 5600}, +/*empty slot1 */ {0,0}, +/*h(602)=15 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {602, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=21 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {124, 5605}, +/*empty slot1 */ {0,0}, +/*h(364)=23 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {364, 5607}, +/*empty slot1 */ {0,0}, +/*h(604)=25 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {604, 5603}, +/*h(125)=26 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {125, 5605}, +/*empty slot1 */ {0,0}, +/*h(365)=28 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {365, 5607}, +/*empty slot1 */ {0,0}, +/*h(605)=30 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {605, 5603}, +/*h(126)=31 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {126, 5604}, +/*empty slot1 */ {0,0}, +/*h(366)=33 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {366, 5606}, +/*empty slot1 */ {0,0}, +/*h(606)=35 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {606, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(368)=43 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {368, 5601}, +/*empty slot1 */ {0,0}, +/*h(608)=45 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {608, 5597}, +/*h(728)=46 EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {728, 5495}, +/*empty slot1 */ {0,0}, +/*h(369)=48 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {369, 5601}, +/*h(1088)=49 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1088, 5599}, +/*h(609)=50 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {609, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(370)=53 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {370, 5600}, +/*h(1089)=54 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1089, 5599}, +/*h(610)=55 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {610, 5596}, +/*h(730)=56 EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5494}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1090)=59 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1090, 5598}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(372)=63 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {372, 5607}, +/*empty slot1 */ {0,0}, +/*h(612)=65 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {612, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(373)=68 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {373, 5607}, +/*h(1092)=69 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1092, 5605}, +/*h(613)=70 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {613, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(374)=73 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {374, 5606}, +/*h(1093)=74 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1093, 5605}, +/*h(614)=75 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {614, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1094)=79 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1094, 5604}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(376)=83 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {376, 5601}, +/*empty slot1 */ {0,0}, +/*h(616)=85 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {616, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(377)=88 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {377, 5601}, +/*h(1096)=89 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1096, 5599}, +/*h(617)=90 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {617, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(378)=93 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {378, 5600}, +/*h(1097)=94 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1097, 5599}, +/*h(618)=95 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {618, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1098)=99 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1098, 5598}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(380)=103 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {380, 5607}, +/*empty slot1 */ {0,0}, +/*h(620)=105 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {620, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(381)=108 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {381, 5607}, +/*h(1100)=109 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1100, 5605}, +/*h(621)=110 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {621, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(382)=113 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {382, 5606}, +/*h(1101)=114 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1101, 5605}, +/*h(622)=115 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {622, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1102)=119 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1102, 5604}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(624)=125 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {624, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1104)=129 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1104, 5599}, +/*h(625)=130 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {625, 5597}, +/*h(1344)=131 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1344, 5601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1105)=134 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1105, 5599}, +/*h(626)=135 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {626, 5596}, +/*h(1345)=136 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1345, 5601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1106)=139 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1106, 5598}, +/*empty slot1 */ {0,0}, +/*h(1346)=141 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1346, 5600}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(628)=145 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {628, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1108)=149 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1108, 5605}, +/*h(629)=150 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {629, 5603}, +/*h(1348)=151 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1348, 5607}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1109)=154 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1109, 5605}, +/*h(630)=155 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {630, 5602}, +/*h(1349)=156 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1349, 5607}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1110)=159 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1110, 5604}, +/*empty slot1 */ {0,0}, +/*h(1350)=161 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1350, 5606}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(632)=165 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {632, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=169 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1112, 5599}, +/*h(633)=170 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {633, 5597}, +/*h(1352)=171 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1352, 5601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1113)=174 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1113, 5599}, +/*h(634)=175 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {634, 5596}, +/*h(1353)=176 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1353, 5601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1114)=179 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1114, 5598}, +/*empty slot1 */ {0,0}, +/*h(1354)=181 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1354, 5600}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(636)=185 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {636, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1116)=189 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1116, 5605}, +/*h(637)=190 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {637, 5603}, +/*h(1356)=191 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1356, 5607}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1117)=194 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1117, 5605}, +/*h(638)=195 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {638, 5602}, +/*h(1357)=196 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1357, 5607}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1118)=199 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1118, 5604}, +/*empty slot1 */ {0,0}, +/*h(1358)=201 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1358, 5606}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1120)=209 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1120, 5599}, +/*empty slot1 */ {0,0}, +/*h(1360)=211 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1360, 5601}, +/*empty slot1 */ {0,0}, +/*h(1600)=213 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1600, 5597}, +/*h(1121)=214 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1121, 5599}, +/*empty slot1 */ {0,0}, +/*h(1361)=216 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1361, 5601}, +/*empty slot1 */ {0,0}, +/*h(1601)=218 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1601, 5597}, +/*h(1122)=219 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1122, 5598}, +/*h(1242)=220 EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5496}, +/*h(1362)=221 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1362, 5600}, +/*empty slot1 */ {0,0}, +/*h(1602)=223 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1602, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1124)=229 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1124, 5605}, +/*empty slot1 */ {0,0}, +/*h(1364)=231 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1364, 5607}, +/*empty slot1 */ {0,0}, +/*h(1604)=233 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1604, 5603}, +/*h(1125)=234 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1125, 5605}, +/*empty slot1 */ {0,0}, +/*h(1365)=236 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1365, 5607}, +/*empty slot1 */ {0,0}, +/*h(1605)=238 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1605, 5603}, +/*h(1126)=239 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1126, 5604}, +/*empty slot1 */ {0,0}, +/*h(1366)=241 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1366, 5606}, +/*empty slot1 */ {0,0}, +/*h(1606)=243 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1606, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1128)=249 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1128, 5599}, +/*empty slot1 */ {0,0}, +/*h(1368)=251 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1368, 5601}, +/*empty slot1 */ {0,0}, +/*h(1608)=253 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1608, 5597}, +/*h(1129)=254 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1129, 5599}, +/*empty slot1 */ {0,0}, +/*h(1369)=256 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1369, 5601}, +/*empty slot1 */ {0,0}, +/*h(1609)=258 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1609, 5597}, +/*h(1130)=259 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1130, 5598}, +/*empty slot1 */ {0,0}, +/*h(1370)=261 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1370, 5600}, +/*empty slot1 */ {0,0}, +/*h(1610)=263 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1610, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1132)=269 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1132, 5605}, +/*empty slot1 */ {0,0}, +/*h(1372)=271 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1372, 5607}, +/*empty slot1 */ {0,0}, +/*h(1612)=273 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1612, 5603}, +/*h(1133)=274 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1133, 5605}, +/*empty slot1 */ {0,0}, +/*h(1373)=276 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1373, 5607}, +/*empty slot1 */ {0,0}, +/*h(1613)=278 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1613, 5603}, +/*h(1134)=279 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1134, 5604}, +/*empty slot1 */ {0,0}, +/*h(1374)=281 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1374, 5606}, +/*empty slot1 */ {0,0}, +/*h(1614)=283 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1614, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1136)=289 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1136, 5599}, +/*empty slot1 */ {0,0}, +/*h(1376)=291 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1376, 5601}, +/*empty slot1 */ {0,0}, +/*h(1616)=293 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1616, 5597}, +/*h(1137)=294 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1137, 5599}, +/*empty slot1 */ {0,0}, +/*h(1377)=296 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1377, 5601}, +/*empty slot1 */ {0,0}, +/*h(1617)=298 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1617, 5597}, +/*h(1138)=299 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1138, 5598}, +/*empty slot1 */ {0,0}, +/*h(1378)=301 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1378, 5600}, +/*h(1498)=302 EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5498}, +/*h(1618)=303 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1618, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1140)=309 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1140, 5605}, +/*empty slot1 */ {0,0}, +/*h(1380)=311 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1380, 5607}, +/*empty slot1 */ {0,0}, +/*h(1620)=313 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1620, 5603}, +/*h(1141)=314 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1141, 5605}, +/*empty slot1 */ {0,0}, +/*h(1381)=316 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1381, 5607}, +/*empty slot1 */ {0,0}, +/*h(1621)=318 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1621, 5603}, +/*h(1142)=319 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1142, 5604}, +/*h(64)=320 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 5599}, +/*h(1382)=321 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1382, 5606}, +/*empty slot1 */ {0,0}, +/*h(1622)=323 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1622, 5602}, +/*empty slot1 */ {0,0}, +/*h(65)=325 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 5599}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1144)=329 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1144, 5599}, +/*h(66)=330 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {66, 5598}, +/*h(1384)=331 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1384, 5601}, +/*empty slot1 */ {0,0}, +/*h(1624)=333 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1624, 5597}, +/*h(1145)=334 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1145, 5599}, +/*empty slot1 */ {0,0}, +/*h(1385)=336 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1385, 5601}, +/*empty slot1 */ {0,0}, +/*h(1625)=338 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1625, 5597}, +/*h(1146)=339 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1146, 5598}, +/*h(68)=340 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {68, 5605}, +/*h(1386)=341 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1386, 5600}, +/*empty slot1 */ {0,0}, +/*h(1626)=343 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1626, 5596}, +/*empty slot1 */ {0,0}, +/*h(69)=345 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {69, 5605}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1148)=349 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1148, 5605}, +/*h(70)=350 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {70, 5604}, +/*h(1388)=351 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1388, 5607}, +/*empty slot1 */ {0,0}, +/*h(1628)=353 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1628, 5603}, +/*h(1149)=354 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1149, 5605}, +/*empty slot1 */ {0,0}, +/*h(1389)=356 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1389, 5607}, +/*empty slot1 */ {0,0}, +/*h(1629)=358 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1629, 5603}, +/*h(1150)=359 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1150, 5604}, +/*h(72)=360 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5599}, +/*h(1390)=361 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1390, 5606}, +/*empty slot1 */ {0,0}, +/*h(1630)=363 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1630, 5602}, +/*empty slot1 */ {0,0}, +/*h(73)=365 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5599}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=370 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {74, 5598}, +/*h(1392)=371 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1392, 5601}, +/*empty slot1 */ {0,0}, +/*h(1632)=373 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1632, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1393)=376 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1393, 5601}, +/*empty slot1 */ {0,0}, +/*h(1633)=378 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1633, 5597}, +/*empty slot1 */ {0,0}, +/*h(76)=380 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5605}, +/*h(1394)=381 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1394, 5600}, +/*empty slot1 */ {0,0}, +/*h(1634)=383 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1634, 5596}, +/*h(1754)=384 EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5494}, +/*h(77)=385 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5605}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=390 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {78, 5604}, +/*h(1396)=391 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1396, 5607}, +/*empty slot1 */ {0,0}, +/*h(1636)=393 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1636, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1397)=396 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1397, 5607}, +/*empty slot1 */ {0,0}, +/*h(1637)=398 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1637, 5603}, +/*empty slot1 */ {0,0}, +/*h(80)=400 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {80, 5599}, +/*h(1398)=401 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1398, 5606}, +/*h(320)=402 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {320, 5601}, +/*h(1638)=403 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1638, 5602}, +/*empty slot1 */ {0,0}, +/*h(81)=405 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {81, 5599}, +/*empty slot1 */ {0,0}, +/*h(321)=407 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {321, 5601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(82)=410 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {82, 5598}, +/*h(1400)=411 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1400, 5601}, +/*h(322)=412 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {322, 5600}, +/*h(1640)=413 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1640, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1401)=416 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1401, 5601}, +/*empty slot1 */ {0,0}, +/*h(1641)=418 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1641, 5597}, +/*empty slot1 */ {0,0}, +/*h(84)=420 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {84, 5605}, +/*h(1402)=421 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1402, 5600}, +/*h(324)=422 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {324, 5607}, +/*h(1642)=423 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1642, 5596}, +/*empty slot1 */ {0,0}, +/*h(85)=425 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {85, 5605}, +/*empty slot1 */ {0,0}, +/*h(325)=427 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {325, 5607}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=430 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {86, 5604}, +/*h(1404)=431 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1404, 5607}, +/*h(326)=432 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {326, 5606}, +/*h(1644)=433 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1644, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1405)=436 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1405, 5607}, +/*empty slot1 */ {0,0}, +/*h(1645)=438 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1645, 5603}, +/*empty slot1 */ {0,0}, +/*h(88)=440 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {88, 5599}, +/*h(1406)=441 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1406, 5606}, +/*h(328)=442 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {328, 5601}, +/*h(1646)=443 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1646, 5602}, +/*empty slot1 */ {0,0}, +/*h(89)=445 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {89, 5599}, +/*empty slot1 */ {0,0}, +/*h(329)=447 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {329, 5601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=450 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {90, 5598}, +/*empty slot1 */ {0,0}, +/*h(330)=452 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {330, 5600}, +/*h(1648)=453 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1648, 5597}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1649)=458 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1649, 5597}, +/*empty slot1 */ {0,0}, +/*h(92)=460 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {92, 5605}, +/*empty slot1 */ {0,0}, +/*h(332)=462 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {332, 5607}, +/*h(1650)=463 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1650, 5596}, +/*empty slot1 */ {0,0}, +/*h(93)=465 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {93, 5605}, +/*empty slot1 */ {0,0}, +/*h(333)=467 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {333, 5607}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=470 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {94, 5604}, +/*empty slot1 */ {0,0}, +/*h(334)=472 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {334, 5606}, +/*h(1652)=473 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1652, 5603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1653)=478 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1653, 5603}, +/*empty slot1 */ {0,0}, +/*h(96)=480 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {96, 5599}, +/*h(216)=481 EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {216, 5497}, +/*h(336)=482 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {336, 5601}, +/*h(1654)=483 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1654, 5602}, +/*h(576)=484 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {576, 5597}, +/*h(97)=485 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {97, 5599}, +/*empty slot1 */ {0,0}, +/*h(337)=487 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {337, 5601}, +/*empty slot1 */ {0,0}, +/*h(577)=489 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {577, 5597}, +/*h(98)=490 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {98, 5598}, +/*h(218)=491 EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5496}, +/*h(338)=492 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {338, 5600}, +/*h(1656)=493 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1656, 5597}, +/*h(578)=494 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {578, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1657)=498 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1657, 5597}, +/*empty slot1 */ {0,0}, +/*h(100)=500 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {100, 5605}, +/*empty slot1 */ {0,0}, +/*h(340)=502 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {340, 5607}, +/*h(1658)=503 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1658, 5596}, +/*h(580)=504 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {580, 5603}, +/*h(101)=505 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {101, 5605}, +/*empty slot1 */ {0,0}, +/*h(341)=507 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {341, 5607}, +/*empty slot1 */ {0,0}, +/*h(581)=509 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {581, 5603}, +/*h(102)=510 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {102, 5604}, +/*empty slot1 */ {0,0}, +/*h(342)=512 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {342, 5606}, +/*h(1660)=513 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1660, 5603}, +/*h(582)=514 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {582, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1661)=518 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1661, 5603}, +/*empty slot1 */ {0,0}, +/*h(104)=520 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {104, 5599}, +/*empty slot1 */ {0,0}, +/*h(344)=522 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {344, 5601}, +/*h(1662)=523 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1662, 5602}, +/*h(584)=524 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {584, 5597}, +/*h(105)=525 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {105, 5599}, +/*empty slot1 */ {0,0}, +/*h(345)=527 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {345, 5601}, +/*empty slot1 */ {0,0}, +/*h(585)=529 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {585, 5597}, +/*h(106)=530 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {106, 5598}, +/*empty slot1 */ {0,0}, +/*h(346)=532 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {346, 5600}, +/*empty slot1 */ {0,0}, +/*h(586)=534 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {586, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(108)=540 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {108, 5605}, +/*empty slot1 */ {0,0}, +/*h(348)=542 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {348, 5607}, +/*empty slot1 */ {0,0}, +/*h(588)=544 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {588, 5603}, +/*h(109)=545 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {109, 5605}, +/*empty slot1 */ {0,0}, +/*h(349)=547 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {349, 5607}, +/*empty slot1 */ {0,0}, +/*h(589)=549 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {589, 5603}, +/*h(110)=550 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {110, 5604}, +/*empty slot1 */ {0,0}, +/*h(350)=552 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {350, 5606}, +/*empty slot1 */ {0,0}, +/*h(590)=554 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {590, 5602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(112)=560 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {112, 5599}, +/*empty slot1 */ {0,0}, +/*h(352)=562 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {352, 5601}, +/*h(472)=563 EVV 0x14 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {472, 5499}, +/*h(592)=564 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {592, 5597}, +/*h(113)=565 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {113, 5599}, +/*empty slot1 */ {0,0}, +/*h(353)=567 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {353, 5601}, +/*empty slot1 */ {0,0}, +/*h(593)=569 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {593, 5597}, +/*h(114)=570 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {114, 5598}, +/*empty slot1 */ {0,0}, +/*h(354)=572 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {354, 5600}, +/*h(474)=573 EVV 0x14 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5498}, +/*h(594)=574 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {594, 5596}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=580 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {116, 5605}, +/*empty slot1 */ {0,0}, +/*h(356)=582 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {356, 5607}, +/*empty slot1 */ {0,0}, +/*h(596)=584 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {596, 5603}, +/*h(117)=585 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {117, 5605}, +/*empty slot1 */ {0,0}, +/*h(357)=587 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {357, 5607}, +/*empty slot1 */ {0,0}, +/*h(597)=589 EVV 0x14 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {597, 5603}, +/*h(118)=590 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {118, 5604}, +/*empty slot1 */ {0,0}, +/*h(358)=592 EVV 0x14 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {358, 5606}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 599) % 594); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x15_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[594] = { +/*h(598)=0 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {598, 5578}, +/*h(120)=1 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {120, 5575}, +/*empty slot1 */ {0,0}, +/*h(360)=3 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {360, 5577}, +/*empty slot1 */ {0,0}, +/*h(600)=5 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {600, 5573}, +/*h(121)=6 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {121, 5575}, +/*empty slot1 */ {0,0}, +/*h(361)=8 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {361, 5577}, +/*empty slot1 */ {0,0}, +/*h(601)=10 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {601, 5573}, +/*h(122)=11 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {122, 5574}, +/*empty slot1 */ {0,0}, +/*h(362)=13 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {362, 5576}, +/*empty slot1 */ {0,0}, +/*h(602)=15 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {602, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(124)=21 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {124, 5581}, +/*empty slot1 */ {0,0}, +/*h(364)=23 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {364, 5583}, +/*empty slot1 */ {0,0}, +/*h(604)=25 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {604, 5579}, +/*h(125)=26 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {125, 5581}, +/*empty slot1 */ {0,0}, +/*h(365)=28 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {365, 5583}, +/*empty slot1 */ {0,0}, +/*h(605)=30 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {605, 5579}, +/*h(126)=31 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {126, 5580}, +/*empty slot1 */ {0,0}, +/*h(366)=33 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {366, 5582}, +/*empty slot1 */ {0,0}, +/*h(606)=35 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {606, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(368)=43 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {368, 5577}, +/*empty slot1 */ {0,0}, +/*h(608)=45 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {608, 5573}, +/*h(728)=46 EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {728, 5489}, +/*empty slot1 */ {0,0}, +/*h(369)=48 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {369, 5577}, +/*h(1088)=49 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1088, 5575}, +/*h(609)=50 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {609, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(370)=53 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {370, 5576}, +/*h(1089)=54 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1089, 5575}, +/*h(610)=55 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {610, 5572}, +/*h(730)=56 EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5488}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1090)=59 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1090, 5574}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(372)=63 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {372, 5583}, +/*empty slot1 */ {0,0}, +/*h(612)=65 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {612, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(373)=68 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {373, 5583}, +/*h(1092)=69 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1092, 5581}, +/*h(613)=70 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {613, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(374)=73 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {374, 5582}, +/*h(1093)=74 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1093, 5581}, +/*h(614)=75 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {614, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1094)=79 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1094, 5580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(376)=83 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {376, 5577}, +/*empty slot1 */ {0,0}, +/*h(616)=85 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {616, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(377)=88 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {377, 5577}, +/*h(1096)=89 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1096, 5575}, +/*h(617)=90 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {617, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(378)=93 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {378, 5576}, +/*h(1097)=94 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1097, 5575}, +/*h(618)=95 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {618, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1098)=99 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1098, 5574}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(380)=103 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {380, 5583}, +/*empty slot1 */ {0,0}, +/*h(620)=105 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {620, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(381)=108 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {381, 5583}, +/*h(1100)=109 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1100, 5581}, +/*h(621)=110 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {621, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(382)=113 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {382, 5582}, +/*h(1101)=114 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1101, 5581}, +/*h(622)=115 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {622, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1102)=119 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1102, 5580}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(624)=125 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {624, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1104)=129 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1104, 5575}, +/*h(625)=130 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {625, 5573}, +/*h(1344)=131 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1344, 5577}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1105)=134 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1105, 5575}, +/*h(626)=135 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {626, 5572}, +/*h(1345)=136 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1345, 5577}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1106)=139 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1106, 5574}, +/*empty slot1 */ {0,0}, +/*h(1346)=141 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1346, 5576}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(628)=145 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {628, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1108)=149 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1108, 5581}, +/*h(629)=150 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {629, 5579}, +/*h(1348)=151 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1348, 5583}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1109)=154 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1109, 5581}, +/*h(630)=155 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {630, 5578}, +/*h(1349)=156 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1349, 5583}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1110)=159 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1110, 5580}, +/*empty slot1 */ {0,0}, +/*h(1350)=161 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1350, 5582}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(632)=165 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {632, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=169 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1112, 5575}, +/*h(633)=170 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {633, 5573}, +/*h(1352)=171 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1352, 5577}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1113)=174 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1113, 5575}, +/*h(634)=175 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {634, 5572}, +/*h(1353)=176 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1353, 5577}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1114)=179 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1114, 5574}, +/*empty slot1 */ {0,0}, +/*h(1354)=181 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1354, 5576}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(636)=185 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {636, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1116)=189 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1116, 5581}, +/*h(637)=190 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {637, 5579}, +/*h(1356)=191 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1356, 5583}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1117)=194 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1117, 5581}, +/*h(638)=195 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {638, 5578}, +/*h(1357)=196 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1357, 5583}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1118)=199 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1118, 5580}, +/*empty slot1 */ {0,0}, +/*h(1358)=201 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1358, 5582}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1120)=209 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1120, 5575}, +/*empty slot1 */ {0,0}, +/*h(1360)=211 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1360, 5577}, +/*empty slot1 */ {0,0}, +/*h(1600)=213 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1600, 5573}, +/*h(1121)=214 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1121, 5575}, +/*empty slot1 */ {0,0}, +/*h(1361)=216 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1361, 5577}, +/*empty slot1 */ {0,0}, +/*h(1601)=218 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1601, 5573}, +/*h(1122)=219 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1122, 5574}, +/*h(1242)=220 EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5490}, +/*h(1362)=221 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1362, 5576}, +/*empty slot1 */ {0,0}, +/*h(1602)=223 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1602, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1124)=229 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1124, 5581}, +/*empty slot1 */ {0,0}, +/*h(1364)=231 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1364, 5583}, +/*empty slot1 */ {0,0}, +/*h(1604)=233 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1604, 5579}, +/*h(1125)=234 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1125, 5581}, +/*empty slot1 */ {0,0}, +/*h(1365)=236 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1365, 5583}, +/*empty slot1 */ {0,0}, +/*h(1605)=238 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1605, 5579}, +/*h(1126)=239 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1126, 5580}, +/*empty slot1 */ {0,0}, +/*h(1366)=241 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1366, 5582}, +/*empty slot1 */ {0,0}, +/*h(1606)=243 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1606, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1128)=249 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1128, 5575}, +/*empty slot1 */ {0,0}, +/*h(1368)=251 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1368, 5577}, +/*empty slot1 */ {0,0}, +/*h(1608)=253 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1608, 5573}, +/*h(1129)=254 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1129, 5575}, +/*empty slot1 */ {0,0}, +/*h(1369)=256 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1369, 5577}, +/*empty slot1 */ {0,0}, +/*h(1609)=258 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1609, 5573}, +/*h(1130)=259 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1130, 5574}, +/*empty slot1 */ {0,0}, +/*h(1370)=261 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1370, 5576}, +/*empty slot1 */ {0,0}, +/*h(1610)=263 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1610, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1132)=269 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1132, 5581}, +/*empty slot1 */ {0,0}, +/*h(1372)=271 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1372, 5583}, +/*empty slot1 */ {0,0}, +/*h(1612)=273 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1612, 5579}, +/*h(1133)=274 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1133, 5581}, +/*empty slot1 */ {0,0}, +/*h(1373)=276 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1373, 5583}, +/*empty slot1 */ {0,0}, +/*h(1613)=278 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1613, 5579}, +/*h(1134)=279 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1134, 5580}, +/*empty slot1 */ {0,0}, +/*h(1374)=281 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1374, 5582}, +/*empty slot1 */ {0,0}, +/*h(1614)=283 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1614, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1136)=289 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1136, 5575}, +/*empty slot1 */ {0,0}, +/*h(1376)=291 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1376, 5577}, +/*empty slot1 */ {0,0}, +/*h(1616)=293 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1616, 5573}, +/*h(1137)=294 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1137, 5575}, +/*empty slot1 */ {0,0}, +/*h(1377)=296 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1377, 5577}, +/*empty slot1 */ {0,0}, +/*h(1617)=298 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1617, 5573}, +/*h(1138)=299 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1138, 5574}, +/*empty slot1 */ {0,0}, +/*h(1378)=301 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1378, 5576}, +/*h(1498)=302 EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5492}, +/*h(1618)=303 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1618, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1140)=309 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1140, 5581}, +/*empty slot1 */ {0,0}, +/*h(1380)=311 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1380, 5583}, +/*empty slot1 */ {0,0}, +/*h(1620)=313 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1620, 5579}, +/*h(1141)=314 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1141, 5581}, +/*empty slot1 */ {0,0}, +/*h(1381)=316 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1381, 5583}, +/*empty slot1 */ {0,0}, +/*h(1621)=318 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1621, 5579}, +/*h(1142)=319 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1142, 5580}, +/*h(64)=320 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 5575}, +/*h(1382)=321 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1382, 5582}, +/*empty slot1 */ {0,0}, +/*h(1622)=323 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1622, 5578}, +/*empty slot1 */ {0,0}, +/*h(65)=325 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 5575}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1144)=329 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1144, 5575}, +/*h(66)=330 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {66, 5574}, +/*h(1384)=331 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1384, 5577}, +/*empty slot1 */ {0,0}, +/*h(1624)=333 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1624, 5573}, +/*h(1145)=334 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1145, 5575}, +/*empty slot1 */ {0,0}, +/*h(1385)=336 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1385, 5577}, +/*empty slot1 */ {0,0}, +/*h(1625)=338 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1625, 5573}, +/*h(1146)=339 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {1146, 5574}, +/*h(68)=340 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {68, 5581}, +/*h(1386)=341 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1386, 5576}, +/*empty slot1 */ {0,0}, +/*h(1626)=343 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1626, 5572}, +/*empty slot1 */ {0,0}, +/*h(69)=345 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {69, 5581}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1148)=349 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1148, 5581}, +/*h(70)=350 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {70, 5580}, +/*h(1388)=351 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1388, 5583}, +/*empty slot1 */ {0,0}, +/*h(1628)=353 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1628, 5579}, +/*h(1149)=354 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1149, 5581}, +/*empty slot1 */ {0,0}, +/*h(1389)=356 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1389, 5583}, +/*empty slot1 */ {0,0}, +/*h(1629)=358 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1629, 5579}, +/*h(1150)=359 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {1150, 5580}, +/*h(72)=360 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5575}, +/*h(1390)=361 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1390, 5582}, +/*empty slot1 */ {0,0}, +/*h(1630)=363 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1630, 5578}, +/*empty slot1 */ {0,0}, +/*h(73)=365 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5575}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=370 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {74, 5574}, +/*h(1392)=371 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1392, 5577}, +/*empty slot1 */ {0,0}, +/*h(1632)=373 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1632, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1393)=376 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1393, 5577}, +/*empty slot1 */ {0,0}, +/*h(1633)=378 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1633, 5573}, +/*empty slot1 */ {0,0}, +/*h(76)=380 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5581}, +/*h(1394)=381 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1394, 5576}, +/*empty slot1 */ {0,0}, +/*h(1634)=383 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1634, 5572}, +/*h(1754)=384 EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5488}, +/*h(77)=385 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5581}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(78)=390 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {78, 5580}, +/*h(1396)=391 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1396, 5583}, +/*empty slot1 */ {0,0}, +/*h(1636)=393 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1636, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1397)=396 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1397, 5583}, +/*empty slot1 */ {0,0}, +/*h(1637)=398 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1637, 5579}, +/*empty slot1 */ {0,0}, +/*h(80)=400 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {80, 5575}, +/*h(1398)=401 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1398, 5582}, +/*h(320)=402 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {320, 5577}, +/*h(1638)=403 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1638, 5578}, +/*empty slot1 */ {0,0}, +/*h(81)=405 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {81, 5575}, +/*empty slot1 */ {0,0}, +/*h(321)=407 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {321, 5577}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(82)=410 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {82, 5574}, +/*h(1400)=411 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1400, 5577}, +/*h(322)=412 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {322, 5576}, +/*h(1640)=413 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1640, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1401)=416 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1401, 5577}, +/*empty slot1 */ {0,0}, +/*h(1641)=418 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1641, 5573}, +/*empty slot1 */ {0,0}, +/*h(84)=420 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {84, 5581}, +/*h(1402)=421 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {1402, 5576}, +/*h(324)=422 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {324, 5583}, +/*h(1642)=423 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1642, 5572}, +/*empty slot1 */ {0,0}, +/*h(85)=425 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {85, 5581}, +/*empty slot1 */ {0,0}, +/*h(325)=427 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {325, 5583}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=430 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {86, 5580}, +/*h(1404)=431 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1404, 5583}, +/*h(326)=432 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {326, 5582}, +/*h(1644)=433 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1644, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1405)=436 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1405, 5583}, +/*empty slot1 */ {0,0}, +/*h(1645)=438 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1645, 5579}, +/*empty slot1 */ {0,0}, +/*h(88)=440 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {88, 5575}, +/*h(1406)=441 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {1406, 5582}, +/*h(328)=442 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {328, 5577}, +/*h(1646)=443 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1646, 5578}, +/*empty slot1 */ {0,0}, +/*h(89)=445 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {89, 5575}, +/*empty slot1 */ {0,0}, +/*h(329)=447 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {329, 5577}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=450 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {90, 5574}, +/*empty slot1 */ {0,0}, +/*h(330)=452 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {330, 5576}, +/*h(1648)=453 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1648, 5573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1649)=458 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1649, 5573}, +/*empty slot1 */ {0,0}, +/*h(92)=460 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {92, 5581}, +/*empty slot1 */ {0,0}, +/*h(332)=462 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {332, 5583}, +/*h(1650)=463 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1650, 5572}, +/*empty slot1 */ {0,0}, +/*h(93)=465 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {93, 5581}, +/*empty slot1 */ {0,0}, +/*h(333)=467 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {333, 5583}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=470 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {94, 5580}, +/*empty slot1 */ {0,0}, +/*h(334)=472 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {334, 5582}, +/*h(1652)=473 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1652, 5579}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1653)=478 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1653, 5579}, +/*empty slot1 */ {0,0}, +/*h(96)=480 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {96, 5575}, +/*h(216)=481 EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {216, 5491}, +/*h(336)=482 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {336, 5577}, +/*h(1654)=483 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1654, 5578}, +/*h(576)=484 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {576, 5573}, +/*h(97)=485 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {97, 5575}, +/*empty slot1 */ {0,0}, +/*h(337)=487 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {337, 5577}, +/*empty slot1 */ {0,0}, +/*h(577)=489 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {577, 5573}, +/*h(98)=490 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {98, 5574}, +/*h(218)=491 EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5490}, +/*h(338)=492 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {338, 5576}, +/*h(1656)=493 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1656, 5573}, +/*h(578)=494 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {578, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1657)=498 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1657, 5573}, +/*empty slot1 */ {0,0}, +/*h(100)=500 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {100, 5581}, +/*empty slot1 */ {0,0}, +/*h(340)=502 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {340, 5583}, +/*h(1658)=503 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1658, 5572}, +/*h(580)=504 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {580, 5579}, +/*h(101)=505 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {101, 5581}, +/*empty slot1 */ {0,0}, +/*h(341)=507 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {341, 5583}, +/*empty slot1 */ {0,0}, +/*h(581)=509 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {581, 5579}, +/*h(102)=510 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {102, 5580}, +/*empty slot1 */ {0,0}, +/*h(342)=512 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {342, 5582}, +/*h(1660)=513 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1660, 5579}, +/*h(582)=514 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {582, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1661)=518 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1661, 5579}, +/*empty slot1 */ {0,0}, +/*h(104)=520 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {104, 5575}, +/*empty slot1 */ {0,0}, +/*h(344)=522 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {344, 5577}, +/*h(1662)=523 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1662, 5578}, +/*h(584)=524 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {584, 5573}, +/*h(105)=525 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {105, 5575}, +/*empty slot1 */ {0,0}, +/*h(345)=527 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {345, 5577}, +/*empty slot1 */ {0,0}, +/*h(585)=529 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {585, 5573}, +/*h(106)=530 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {106, 5574}, +/*empty slot1 */ {0,0}, +/*h(346)=532 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {346, 5576}, +/*empty slot1 */ {0,0}, +/*h(586)=534 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {586, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(108)=540 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {108, 5581}, +/*empty slot1 */ {0,0}, +/*h(348)=542 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {348, 5583}, +/*empty slot1 */ {0,0}, +/*h(588)=544 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {588, 5579}, +/*h(109)=545 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {109, 5581}, +/*empty slot1 */ {0,0}, +/*h(349)=547 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {349, 5583}, +/*empty slot1 */ {0,0}, +/*h(589)=549 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {589, 5579}, +/*h(110)=550 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {110, 5580}, +/*empty slot1 */ {0,0}, +/*h(350)=552 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {350, 5582}, +/*empty slot1 */ {0,0}, +/*h(590)=554 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {590, 5578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(112)=560 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {112, 5575}, +/*empty slot1 */ {0,0}, +/*h(352)=562 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {352, 5577}, +/*h(472)=563 EVV 0x15 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {472, 5493}, +/*h(592)=564 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {592, 5573}, +/*h(113)=565 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {113, 5575}, +/*empty slot1 */ {0,0}, +/*h(353)=567 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {353, 5577}, +/*empty slot1 */ {0,0}, +/*h(593)=569 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {593, 5573}, +/*h(114)=570 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {114, 5574}, +/*empty slot1 */ {0,0}, +/*h(354)=572 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {354, 5576}, +/*h(474)=573 EVV 0x15 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5492}, +/*h(594)=574 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {594, 5572}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=580 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {116, 5581}, +/*empty slot1 */ {0,0}, +/*h(356)=582 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {356, 5583}, +/*empty slot1 */ {0,0}, +/*h(596)=584 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {596, 5579}, +/*h(117)=585 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {117, 5581}, +/*empty slot1 */ {0,0}, +/*h(357)=587 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {357, 5583}, +/*empty slot1 */ {0,0}, +/*h(597)=589 EVV 0x15 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {597, 5579}, +/*h(118)=590 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {118, 5580}, +/*empty slot1 */ {0,0}, +/*h(358)=592 EVV 0x15 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {358, 5582}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 599) % 594); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x16_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5270}, +/*h(73)=1 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5273}, +/*h(77)=2 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5267}, +/*h(41)=3 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5275}, +/*h(45)=4 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5271}, +/*h(72)=5 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5273}, +/*h(76)=6 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5267}, +/*h(40)=7 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5275}, +/*h(44)=8 EVV 0x16 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5271}, +/*h(74)=9 EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5272}, +/*h(78)=10 EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5266}, +/*h(42)=11 EVV 0x16 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5274} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 43) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x18_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(602)=0 EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4130}, +/*h(600)=1 EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()*/ {600, 4129}, +/*h(346)=2 EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4134}, +/*h(344)=3 EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()*/ {344, 4133}, +/*h(90)=4 EVV 0x18 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4132}, +/*h(88)=5 EVV 0x18 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()*/ {88, 4131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x19_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(600)=0 EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()*/ {600, 6057}, +/*h(350)=1 EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4128}, +/*h(348)=2 EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()*/ {348, 4127}, +/*h(346)=3 EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6054}, +/*h(344)=4 EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()*/ {344, 6055}, +/*h(606)=5 EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4126}, +/*h(604)=6 EVV 0x19 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()*/ {604, 4125}, +/*h(602)=7 EVV 0x19 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6056} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 11) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(348)=0 EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()*/ {348, 6059}, +/*h(604)=1 EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()*/ {604, 6060}, +/*h(344)=2 EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()*/ {344, 4120}, +/*h(600)=3 EVV 0x1A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()*/ {600, 4119} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(604)=0 EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4()*/ {604, 4121}, +/*h(600)=1 EVV 0x1B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8()*/ {600, 6058} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=2 EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {44, 6237}, +/*h(172)=3 EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {172, 6239}, +/*h(300)=4 EVV 0x1C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {300, 6241}, +/*h(46)=5 EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {46, 6236}, +/*h(174)=6 EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {174, 6238}, +/*h(302)=7 EVV 0x1C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {302, 6240}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=2 EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6243}, +/*h(172)=3 EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {172, 6245}, +/*h(300)=4 EVV 0x1D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {300, 6247}, +/*h(46)=5 EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {46, 6242}, +/*h(174)=6 EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {174, 6244}, +/*h(302)=7 EVV 0x1D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {302, 6246}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(89)=0 EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 5074}, +/*h(602)=1 EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5071}, +/*empty slot1 */ {0,0}, +/*h(345)=3 EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 5076}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=6 EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 5074}, +/*h(601)=7 EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 5072}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=10 EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 5076}, +/*h(90)=11 EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5073}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=14 EVV 0x1E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 5072}, +/*h(346)=15 EVV 0x1E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5075}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x1f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(94)=0 EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5079}, +/*h(350)=1 EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 5081}, +/*h(606)=2 EVV 0x1F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 5077}, +/*h(92)=3 EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 5080}, +/*h(348)=4 EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 5082}, +/*h(604)=5 EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 5078}, +/*h(93)=6 EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 5080}, +/*h(349)=7 EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 5082}, +/*h(605)=8 EVV 0x1F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 5078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 13) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x20_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 6527}, +/*h(1498)=1 EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 6527}, +/*h(728)=2 EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {728, 6530}, +/*h(218)=3 EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 6525}, +/*h(1242)=4 EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 6525}, +/*h(472)=5 EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {472, 6528}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x20 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {216, 6526}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 6529}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1624, 6536}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1368, 6534}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1112, 6532}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 6535}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 6533}, +/*h(600)=30 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {600, 6536}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 6531}, +/*h(344)=33 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {344, 6534}, +/*h(1628)=34 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1628, 6536}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {88, 6532}, +/*h(1372)=37 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1372, 6534}, +/*h(602)=38 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 6535}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1116, 6532}, +/*h(346)=41 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 6533}, +/*h(1630)=42 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 6535}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 6531}, +/*h(1374)=45 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 6533}, +/*h(604)=46 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {604, 6536}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 6531}, +/*h(348)=49 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {348, 6534}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x20 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {92, 6532}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 6535}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 6533}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x20 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 6531}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x20 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 6529}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x21_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5414}, +/*h(1498)=1 EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5414}, +/*h(728)=2 EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {728, 5411}, +/*h(218)=3 EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5412}, +/*h(1242)=4 EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5412}, +/*h(472)=5 EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {472, 5415}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x21 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {216, 5413}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5410}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1624, 5441}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1368, 5445}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1112, 5443}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5440}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5444}, +/*h(600)=30 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {600, 5441}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5442}, +/*h(344)=33 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {344, 5445}, +/*h(1628)=34 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1628, 5441}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {88, 5443}, +/*h(1372)=37 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1372, 5445}, +/*h(602)=38 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5440}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1116, 5443}, +/*h(346)=41 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5444}, +/*h(1630)=42 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5440}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5442}, +/*h(1374)=45 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5444}, +/*h(604)=46 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {604, 5441}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5442}, +/*h(348)=49 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {348, 5445}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x21 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {92, 5443}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5440}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5444}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x21 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5442}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x21 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5410}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x22_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5426}, +/*h(1498)=1 EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5426}, +/*h(728)=2 EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {728, 5423}, +/*h(218)=3 EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5424}, +/*h(1242)=4 EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5424}, +/*h(472)=5 EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {472, 5427}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x22 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {216, 5425}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5422}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1624, 5447}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1368, 5451}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1112, 5449}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5446}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5450}, +/*h(600)=30 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {600, 5447}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5448}, +/*h(344)=33 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {344, 5451}, +/*h(1628)=34 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1628, 5447}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {88, 5449}, +/*h(1372)=37 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1372, 5451}, +/*h(602)=38 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5446}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1116, 5449}, +/*h(346)=41 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5450}, +/*h(1630)=42 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5446}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5448}, +/*h(1374)=45 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5450}, +/*h(604)=46 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {604, 5447}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5448}, +/*h(348)=49 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {348, 5451}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x22 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {92, 5449}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5446}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5450}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x22 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5448}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x22 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5422}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x23_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5420}, +/*h(1498)=1 EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5420}, +/*h(728)=2 EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {728, 5417}, +/*h(218)=3 EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5418}, +/*h(1242)=4 EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5418}, +/*h(472)=5 EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {472, 5421}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x23 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {216, 5419}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5416}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1624, 5459}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1368, 5463}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1112, 5461}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5458}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5462}, +/*h(600)=30 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {600, 5459}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5460}, +/*h(344)=33 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {344, 5463}, +/*h(1628)=34 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1628, 5459}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {88, 5461}, +/*h(1372)=37 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1372, 5463}, +/*h(602)=38 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5458}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1116, 5461}, +/*h(346)=41 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5462}, +/*h(1630)=42 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5458}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5460}, +/*h(1374)=45 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5462}, +/*h(604)=46 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {604, 5459}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5460}, +/*h(348)=49 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {348, 5463}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x23 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {92, 5461}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5458}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5462}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x23 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5460}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x23 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5416}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x24_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5438}, +/*h(1498)=1 EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5438}, +/*h(728)=2 EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {728, 5435}, +/*h(218)=3 EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5436}, +/*h(1242)=4 EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5436}, +/*h(472)=5 EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {472, 5439}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x24 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {216, 5437}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5434}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1624, 5465}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1368, 5469}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1112, 5467}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5464}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5468}, +/*h(600)=30 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {600, 5465}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5466}, +/*h(344)=33 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {344, 5469}, +/*h(1628)=34 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1628, 5465}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {88, 5467}, +/*h(1372)=37 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1372, 5469}, +/*h(602)=38 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5464}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1116, 5467}, +/*h(346)=41 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5468}, +/*h(1630)=42 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5464}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5466}, +/*h(1374)=45 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5468}, +/*h(604)=46 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {604, 5465}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5466}, +/*h(348)=49 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {348, 5469}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x24 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {92, 5467}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5464}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5468}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x24 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5466}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x24 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5434}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x25_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=2 EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {600, 5453}, +/*h(218)=3 EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5430}, +/*empty slot1 */ {0,0}, +/*h(1624)=5 EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {1624, 5453}, +/*h(1242)=6 EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5430}, +/*empty slot1 */ {0,0}, +/*h(602)=8 EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5452}, +/*h(344)=9 EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {344, 5457}, +/*empty slot1 */ {0,0}, +/*h(1626)=11 EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 5452}, +/*h(1368)=12 EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {1368, 5457}, +/*empty slot1 */ {0,0}, +/*h(728)=14 EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {728, 5429}, +/*h(346)=15 EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5456}, +/*h(88)=16 EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {88, 5455}, +/*empty slot1 */ {0,0}, +/*h(1370)=18 EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 5456}, +/*h(1112)=19 EVV 0x25 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {1112, 5455}, +/*h(730)=20 EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5428}, +/*h(472)=21 EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {472, 5433}, +/*h(90)=22 EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5454}, +/*h(1754)=23 EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5428}, +/*empty slot1 */ {0,0}, +/*h(1114)=25 EVV 0x25 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 5454}, +/*empty slot1 */ {0,0}, +/*h(474)=27 EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5432}, +/*h(216)=28 EVV 0x25 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {216, 5431}, +/*empty slot1 */ {0,0}, +/*h(1498)=30 EVV 0x25 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5432} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 31); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x26_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[24] = { +/*h(74)=0 EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {74, 6718}, +/*h(78)=1 EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {78, 6724}, +/*h(8)=2 EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6715}, +/*h(12)=3 EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6721}, +/*h(90)=4 EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {90, 6730}, +/*h(94)=5 EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {94, 6736}, +/*h(24)=6 EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {24, 6727}, +/*h(28)=7 EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {28, 6733}, +/*h(10)=8 EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {10, 6714}, +/*h(14)=9 EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {14, 6720}, +/*h(40)=10 EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6717}, +/*h(44)=11 EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6723}, +/*h(26)=12 EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {26, 6726}, +/*h(30)=13 EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {30, 6732}, +/*h(56)=14 EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {56, 6729}, +/*h(60)=15 EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {60, 6735}, +/*h(42)=16 EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {42, 6716}, +/*h(46)=17 EVV 0x26 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {46, 6722}, +/*h(72)=18 EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6719}, +/*h(76)=19 EVV 0x26 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6725}, +/*h(58)=20 EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {58, 6728}, +/*h(62)=21 EVV 0x26 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {62, 6734}, +/*h(88)=22 EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {88, 6731}, +/*h(92)=23 EVV 0x26 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {92, 6737} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((15*key % 59) % 24); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x27_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[54] = { +/*h(89)=0 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {89, 5771}, +/*h(13)=1 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5767}, +/*empty slot1 */ {0,0}, +/*h(26)=3 EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {26, 5772}, +/*h(60)=4 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {60, 5781}, +/*h(94)=5 EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {94, 5776}, +/*h(73)=6 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5759}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(10)=9 EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {10, 5760}, +/*h(44)=10 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5769}, +/*h(78)=11 EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {78, 5764}, +/*h(57)=12 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {57, 5775}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=16 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {28, 5779}, +/*h(62)=17 EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {62, 5780}, +/*h(41)=18 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5763}, +/*empty slot1 */ {0,0}, +/*h(88)=20 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {88, 5771}, +/*empty slot1 */ {0,0}, +/*h(12)=22 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5767}, +/*h(46)=23 EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {46, 5768}, +/*h(25)=24 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {25, 5773}, +/*h(93)=25 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {93, 5777}, +/*h(72)=26 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5759}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(30)=29 EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {30, 5778}, +/*h(9)=30 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5761}, +/*h(77)=31 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5765}, +/*h(56)=32 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {56, 5775}, +/*h(90)=33 EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {90, 5770}, +/*empty slot1 */ {0,0}, +/*h(14)=35 EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {14, 5766}, +/*empty slot1 */ {0,0}, +/*h(61)=37 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {61, 5781}, +/*h(40)=38 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5763}, +/*h(74)=39 EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {74, 5758}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=43 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5769}, +/*h(24)=44 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {24, 5773}, +/*h(58)=45 EVV 0x27 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {58, 5774}, +/*h(92)=46 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {92, 5777}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(29)=49 EVV 0x27 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {29, 5779}, +/*h(8)=50 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5761}, +/*h(42)=51 EVV 0x27 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {42, 5762}, +/*h(76)=52 EVV 0x27 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5765}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 54ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1164)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1164, 5530}, +/*h(2761)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2761, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3212)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3212; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1228)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3276)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1196)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1196, 5530}, +/*h(2793)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2793, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3244)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3244; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1260)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1260, 5530}, +/*h(650)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {650, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3308)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3308; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1180)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1180, 5530}, +/*h(2777)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2777, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3228)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1244)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1244; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1462)=0 EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0*/ {1462, 6512}, +/*h(3292)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3292, 5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 7) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1212)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1212, 5530}, +/*h(2809)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2809, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3260)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3260; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(666)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {666, 5535}, +/*h(1276)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1276, 5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3324)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3324, 5530}, +/*h(2714)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2714, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1166)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1166, 5530}, +/*h(2763)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2763, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1240)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1240, 5531}, +/*h(3214)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3214, 5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1230)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1230, 5530}, +/*h(2217)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2217, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3278)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1198)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1198, 5530}, +/*h(2185)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2185, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3246)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3246, 5530}, +/*h(1272)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1272, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(652)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {652, 5534}, +/*h(2249)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2249, 5533}, +/*h(1262)=2 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1262, 5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2700)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2700, 5534}, +/*h(3310)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3310, 5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1182)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1182, 5530}, +/*h(2779)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2779, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3230)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3230, 5530}, +/*h(1256)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1256, 5531}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1246)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1246, 5530}, +/*h(2233)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2233, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3294)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1214)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1214, 5530}, +/*h(2201)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2201, 5533}, +/*h(2811)=2 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2811, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3262)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1278)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1278, 5530}, +/*h(2265)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2265, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3326)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3326, 5530}, +/*h(2716)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2716, 5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1160)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3208)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1224)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3272)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1192)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3240)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3240; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3304)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3304; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1176)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3224)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3224; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3288)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3288; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1208)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3256)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3256; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3320)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3320; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1162)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3210)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3210, 5531}, +/*h(249)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {249, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1226)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3274)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1194)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3242)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1258)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3306)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3306, 5531}, +/*h(2696)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2696, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1178)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3226)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1242)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3290)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1210)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3258)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1274)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1274, 5531}, +/*h(664)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {664, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3322)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3322; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(174)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {174, 5532}, +/*h(1161)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1161, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2222)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2222, 5532}, +/*h(3209)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3209, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1225)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2286)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2286, 5532}, +/*h(3273)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3273, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(206)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {206, 5532}, +/*h(1193)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1193, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2254)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2254, 5532}, +/*h(3241)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3241, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1257)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1257; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3305)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3305; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(190)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {190, 5532}, +/*h(1177)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1177, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3225)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3225; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(254)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {254, 5532}, +/*h(1241)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1241, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2302)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2302, 5532}, +/*h(3289)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3289, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(222)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {222, 5532}, +/*h(1209)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1209, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2270)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2270, 5532}, +/*h(3257)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3257, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1273)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1273; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3321)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3321; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2760)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2760, 5535}, +/*h(1163)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1163, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3211)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3211, 5531}, +/*h(250)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {250, 5533}, +/*h(1470)=2 EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0*/ {1470, 6521} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1227)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3275)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2792)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2792, 5535}, +/*h(1195)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1195, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3243)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1259)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1259, 5531}, +/*h(649)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {649, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2697)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2697, 5535}, +/*h(3307)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3307, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2776)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2776, 5535}, +/*h(1179)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1179, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3227)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1243)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3291)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2808)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2808, 5535}, +/*h(1211)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1211, 5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3259)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3259; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1275)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5531} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3323)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3323, 5531}, +/*h(2713)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2713, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(750)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {750, 5534}, +/*h(140)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {140, 5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2188)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(204)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 204; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2252)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(172)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 172; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2220)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(236)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2284)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(156)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {156, 5532}, +/*h(766)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {766, 5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2814)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2814, 5534}, +/*h(2204)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2204, 5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(220)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2268)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(188)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2236)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(252)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2300)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2300; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2190)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2190, 5532}, +/*h(216)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {216, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(238)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(158)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 158; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2206)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2206, 5532}, +/*h(232)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {232, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2238)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5532} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(746)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {746, 5535}, +/*h(136)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {136, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2184)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2184, 5533}, +/*h(2794)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2794, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(200)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2248)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(168)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2216)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2280)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2280, 5533}, +/*h(683)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {683, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {762, 5535}, +/*h(152)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {152, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2810)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2810, 5535}, +/*h(2200)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2200, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2264)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2264, 5533}, +/*h(667)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {667, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(184)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2232)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(248)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2296)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2296, 5533}, +/*h(699)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {699, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(138)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2796)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2796, 5534}, +/*h(2186)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2186, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(202)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2250)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(170)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2218)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(234)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2282)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(764)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {764, 5534}, +/*h(154)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {154, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2202)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(218)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2266)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(186)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2234)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2298)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(747)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {747, 5535}, +/*h(137)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {137, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(201)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 201; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(169)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 169; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(233)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(684)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {684, 5534}, +/*h(2281)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2281, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(153)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {153, 5533}, +/*h(763)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {763, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(217)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 217; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(185)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 185; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(700)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {700, 5534}, +/*h(2297)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2297, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(139)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 139; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2187)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(203)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(654)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {654, 5534}, +/*h(2251)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2251, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(171)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 171; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2219)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(686)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {686, 5534}, +/*h(2283)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2283, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(155)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 155; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2203)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(670)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {670, 5534}, +/*h(2267)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2267, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(187)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2235)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(251)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(702)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {702, 5534}, +/*h(2299)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2299, 5533} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(716)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 716; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2764)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2764; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2732)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(748)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 748; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(668)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(732)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 732; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2780)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2748)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2748; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2812)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2702)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(718)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2766)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(760)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {760, 5535}, +/*h(2734)=1 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2734, 5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2798)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2718)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2718, 5534}, +/*h(744)=1 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {744, 5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(734)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2782)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2750)=0 EVV 0x28 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5534} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(648)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 648; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(680)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2728)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2712)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(728)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(696)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2744)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2698)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2762)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(682)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2730)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2778)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(698)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2746)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(713)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(681)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 681; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2729)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(745)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(665)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 665; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(729)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 729; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(697)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 697; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2745)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(761)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(651)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 651; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2699)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(715)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2731)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2795)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2715)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(731)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 731; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2747)=0 EVV 0x28 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5535} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(438)=0 EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0*/ {6510} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(950)=0 EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0*/ {6511} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(446)=0 EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {6519} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(958)=0 EVV 0x28 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0*/ {6520} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x28_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[294] = { +/*h(233)=0 */ {233, xed3_phash_find_mapevex_map2_opcode0x28_vv2_0_l1}, +/*h(699)=1 */ {699, xed3_phash_find_mapevex_map2_opcode0x28_vv2_1_l1}, +/*h(2762)=2 */ {2762, xed3_phash_find_mapevex_map2_opcode0x28_vv2_2_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3228)=4 */ {3228, xed3_phash_find_mapevex_map2_opcode0x28_vv2_4_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2796)=6 */ {2796, xed3_phash_find_mapevex_map2_opcode0x28_vv2_6_l1}, +/*h(3262)=7 */ {3262, xed3_phash_find_mapevex_map2_opcode0x28_vv2_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2220)=10 */ {2220, xed3_phash_find_mapevex_map2_opcode0x28_vv2_10_l1}, +/*h(712)=11 */ {712, xed3_phash_find_mapevex_map2_opcode0x28_vv2_11_l1}, +/*h(1178)=12 */ {1178, xed3_phash_find_mapevex_map2_opcode0x28_vv2_12_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2254)=14 */ {2254, xed3_phash_find_mapevex_map2_opcode0x28_vv2_14_l1}, +/*h(746)=15 */ {746, xed3_phash_find_mapevex_map2_opcode0x28_vv2_15_l1}, +/*h(2809)=16 */ {2809, xed3_phash_find_mapevex_map2_opcode0x28_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3275)=18 */ {3275, xed3_phash_find_mapevex_map2_opcode0x28_vv2_18_l1}, +/*h(170)=19 */ {170, xed3_phash_find_mapevex_map2_opcode0x28_vv2_19_l1}, +/*h(2233)=20 */ {2233, xed3_phash_find_mapevex_map2_opcode0x28_vv2_20_l1}, +/*h(2699)=21 */ {2699, xed3_phash_find_mapevex_map2_opcode0x28_vv2_21_l1}, +/*h(958)=22 */ {958, xed3_phash_find_mapevex_map2_opcode0x28_vv2_22_l1}, +/*h(204)=23 */ {204, xed3_phash_find_mapevex_map2_opcode0x28_vv2_23_l1}, +/*h(670)=24 */ {670, xed3_phash_find_mapevex_map2_opcode0x28_vv2_24_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1225)=26 */ {1225, xed3_phash_find_mapevex_map2_opcode0x28_vv2_26_l1}, +/*h(238)=27 */ {238, xed3_phash_find_mapevex_map2_opcode0x28_vv2_27_l1}, +/*h(3288)=28 */ {3288, xed3_phash_find_mapevex_map2_opcode0x28_vv2_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(649)=30 */ {649, xed3_phash_find_mapevex_map2_opcode0x28_vv2_30_l1}, +/*h(2712)=31 */ {2712, xed3_phash_find_mapevex_map2_opcode0x28_vv2_31_l1}, +/*h(3322)=32 */ {3322, xed3_phash_find_mapevex_map2_opcode0x28_vv2_32_l1}, +/*h(217)=33 */ {217, xed3_phash_find_mapevex_map2_opcode0x28_vv2_33_l1}, +/*h(683)=34 */ {683, xed3_phash_find_mapevex_map2_opcode0x28_vv2_34_l1}, +/*h(2746)=35 */ {2746, xed3_phash_find_mapevex_map2_opcode0x28_vv2_35_l1}, +/*h(3212)=36 */ {3212, xed3_phash_find_mapevex_map2_opcode0x28_vv2_36_l1}, +/*h(251)=37 */ {251, xed3_phash_find_mapevex_map2_opcode0x28_vv2_37_l1}, +/*h(950)=38 */ {950, xed3_phash_find_mapevex_map2_opcode0x28_vv2_38_l1}, +/*h(2780)=39 */ {2780, xed3_phash_find_mapevex_map2_opcode0x28_vv2_39_l1}, +/*h(1272)=40 */ {1272, xed3_phash_find_mapevex_map2_opcode0x28_vv2_40_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2814)=43 */ {2814, xed3_phash_find_mapevex_map2_opcode0x28_vv2_43_l1}, +/*h(696)=44 */ {696, xed3_phash_find_mapevex_map2_opcode0x28_vv2_44_l1}, +/*h(1162)=45 */ {1162, xed3_phash_find_mapevex_map2_opcode0x28_vv2_45_l1}, +/*h(3225)=46 */ {3225, xed3_phash_find_mapevex_map2_opcode0x28_vv2_46_l1}, +/*h(2238)=47 */ {2238, xed3_phash_find_mapevex_map2_opcode0x28_vv2_47_l1}, +/*h(730)=48 */ {730, xed3_phash_find_mapevex_map2_opcode0x28_vv2_48_l1}, +/*h(2793)=49 */ {2793, xed3_phash_find_mapevex_map2_opcode0x28_vv2_49_l1}, +/*h(3259)=50 */ {3259, xed3_phash_find_mapevex_map2_opcode0x28_vv2_50_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(764)=52 */ {764, xed3_phash_find_mapevex_map2_opcode0x28_vv2_52_l1}, +/*h(2217)=53 */ {2217, xed3_phash_find_mapevex_map2_opcode0x28_vv2_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(188)=55 */ {188, xed3_phash_find_mapevex_map2_opcode0x28_vv2_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(654)=57 */ {654, xed3_phash_find_mapevex_map2_opcode0x28_vv2_57_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(222)=59 */ {222, xed3_phash_find_mapevex_map2_opcode0x28_vv2_59_l1}, +/*h(3272)=60 */ {3272, xed3_phash_find_mapevex_map2_opcode0x28_vv2_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1243)=63 */ {1243, xed3_phash_find_mapevex_map2_opcode0x28_vv2_63_l1}, +/*h(2696)=64 */ {2696, xed3_phash_find_mapevex_map2_opcode0x28_vv2_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(201)=66 */ {201, xed3_phash_find_mapevex_map2_opcode0x28_vv2_66_l1}, +/*h(667)=67 */ {667, xed3_phash_find_mapevex_map2_opcode0x28_vv2_67_l1}, +/*h(2730)=68 */ {2730, xed3_phash_find_mapevex_map2_opcode0x28_vv2_68_l1}, +/*h(235)=69 */ {235, xed3_phash_find_mapevex_map2_opcode0x28_vv2_69_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2298)=71 */ {2298, xed3_phash_find_mapevex_map2_opcode0x28_vv2_71_l1}, +/*h(2764)=72 */ {2764, xed3_phash_find_mapevex_map2_opcode0x28_vv2_72_l1}, +/*h(1256)=73 */ {1256, xed3_phash_find_mapevex_map2_opcode0x28_vv2_73_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2188)=75 */ {2188, xed3_phash_find_mapevex_map2_opcode0x28_vv2_75_l1}, +/*h(2798)=76 */ {2798, xed3_phash_find_mapevex_map2_opcode0x28_vv2_76_l1}, +/*h(680)=77 */ {680, xed3_phash_find_mapevex_map2_opcode0x28_vv2_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2222)=79 */ {2222, xed3_phash_find_mapevex_map2_opcode0x28_vv2_79_l1}, +/*h(248)=80 */ {248, xed3_phash_find_mapevex_map2_opcode0x28_vv2_80_l1}, +/*h(714)=81 */ {714, xed3_phash_find_mapevex_map2_opcode0x28_vv2_81_l1}, +/*h(2777)=82 */ {2777, xed3_phash_find_mapevex_map2_opcode0x28_vv2_82_l1}, +/*h(3243)=83 */ {3243, xed3_phash_find_mapevex_map2_opcode0x28_vv2_83_l1}, +/*h(138)=84 */ {138, xed3_phash_find_mapevex_map2_opcode0x28_vv2_84_l1}, +/*h(748)=85 */ {748, xed3_phash_find_mapevex_map2_opcode0x28_vv2_85_l1}, +/*h(2811)=86 */ {2811, xed3_phash_find_mapevex_map2_opcode0x28_vv2_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(172)=88 */ {172, xed3_phash_find_mapevex_map2_opcode0x28_vv2_88_l1}, +/*h(2235)=89 */ {2235, xed3_phash_find_mapevex_map2_opcode0x28_vv2_89_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(206)=92 */ {206, xed3_phash_find_mapevex_map2_opcode0x28_vv2_92_l1}, +/*h(3256)=93 */ {3256, xed3_phash_find_mapevex_map2_opcode0x28_vv2_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(761)=95 */ {761, xed3_phash_find_mapevex_map2_opcode0x28_vv2_95_l1}, +/*h(1227)=96 */ {1227, xed3_phash_find_mapevex_map2_opcode0x28_vv2_96_l1}, +/*h(3290)=97 */ {3290, xed3_phash_find_mapevex_map2_opcode0x28_vv2_97_l1}, +/*h(185)=98 */ {185, xed3_phash_find_mapevex_map2_opcode0x28_vv2_98_l1}, +/*h(651)=99 */ {651, xed3_phash_find_mapevex_map2_opcode0x28_vv2_99_l1}, +/*h(2248)=100 */ {2248, xed3_phash_find_mapevex_map2_opcode0x28_vv2_100_l1}, +/*h(2714)=101 */ {2714, xed3_phash_find_mapevex_map2_opcode0x28_vv2_101_l1}, +/*h(219)=102 */ {219, xed3_phash_find_mapevex_map2_opcode0x28_vv2_102_l1}, +/*h(2282)=103 */ {2282, xed3_phash_find_mapevex_map2_opcode0x28_vv2_103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2748)=105 */ {2748, xed3_phash_find_mapevex_map2_opcode0x28_vv2_105_l1}, +/*h(1240)=106 */ {1240, xed3_phash_find_mapevex_map2_opcode0x28_vv2_106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2782)=108 */ {2782, xed3_phash_find_mapevex_map2_opcode0x28_vv2_108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(664)=110 */ {664, xed3_phash_find_mapevex_map2_opcode0x28_vv2_110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(232)=112 */ {232, xed3_phash_find_mapevex_map2_opcode0x28_vv2_112_l1}, +/*h(698)=113 */ {698, xed3_phash_find_mapevex_map2_opcode0x28_vv2_113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2761)=115 */ {2761, xed3_phash_find_mapevex_map2_opcode0x28_vv2_115_l1}, +/*h(3227)=116 */ {3227, xed3_phash_find_mapevex_map2_opcode0x28_vv2_116_l1}, +/*h(732)=117 */ {732, xed3_phash_find_mapevex_map2_opcode0x28_vv2_117_l1}, +/*h(2185)=118 */ {2185, xed3_phash_find_mapevex_map2_opcode0x28_vv2_118_l1}, +/*h(2795)=119 */ {2795, xed3_phash_find_mapevex_map2_opcode0x28_vv2_119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(766)=121 */ {766, xed3_phash_find_mapevex_map2_opcode0x28_vv2_121_l1}, +/*h(2219)=122 */ {2219, xed3_phash_find_mapevex_map2_opcode0x28_vv2_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(190)=125 */ {190, xed3_phash_find_mapevex_map2_opcode0x28_vv2_125_l1}, +/*h(3240)=126 */ {3240, xed3_phash_find_mapevex_map2_opcode0x28_vv2_126_l1}, +/*h(745)=127 */ {745, xed3_phash_find_mapevex_map2_opcode0x28_vv2_127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2808)=129 */ {2808, xed3_phash_find_mapevex_map2_opcode0x28_vv2_129_l1}, +/*h(3274)=130 */ {3274, xed3_phash_find_mapevex_map2_opcode0x28_vv2_130_l1}, +/*h(169)=131 */ {169, xed3_phash_find_mapevex_map2_opcode0x28_vv2_131_l1}, +/*h(2232)=132 */ {2232, xed3_phash_find_mapevex_map2_opcode0x28_vv2_132_l1}, +/*h(2698)=133 */ {2698, xed3_phash_find_mapevex_map2_opcode0x28_vv2_133_l1}, +/*h(3308)=134 */ {3308, xed3_phash_find_mapevex_map2_opcode0x28_vv2_134_l1}, +/*h(203)=135 */ {203, xed3_phash_find_mapevex_map2_opcode0x28_vv2_135_l1}, +/*h(2266)=136 */ {2266, xed3_phash_find_mapevex_map2_opcode0x28_vv2_136_l1}, +/*h(2732)=137 */ {2732, xed3_phash_find_mapevex_map2_opcode0x28_vv2_137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1224)=139 */ {1224, xed3_phash_find_mapevex_map2_opcode0x28_vv2_139_l1}, +/*h(2300)=140 */ {2300, xed3_phash_find_mapevex_map2_opcode0x28_vv2_140_l1}, +/*h(2766)=141 */ {2766, xed3_phash_find_mapevex_map2_opcode0x28_vv2_141_l1}, +/*h(648)=142 */ {648, xed3_phash_find_mapevex_map2_opcode0x28_vv2_142_l1}, +/*h(1258)=143 */ {1258, xed3_phash_find_mapevex_map2_opcode0x28_vv2_143_l1}, +/*h(3321)=144 */ {3321, xed3_phash_find_mapevex_map2_opcode0x28_vv2_144_l1}, +/*h(216)=145 */ {216, xed3_phash_find_mapevex_map2_opcode0x28_vv2_145_l1}, +/*h(682)=146 */ {682, xed3_phash_find_mapevex_map2_opcode0x28_vv2_146_l1}, +/*h(2745)=147 */ {2745, xed3_phash_find_mapevex_map2_opcode0x28_vv2_147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1470)=149 */ {1470, xed3_phash_find_mapevex_map2_opcode0x28_vv2_149_l1}, +/*h(716)=150 */ {716, xed3_phash_find_mapevex_map2_opcode0x28_vv2_150_l1}, +/*h(2779)=151 */ {2779, xed3_phash_find_mapevex_map2_opcode0x28_vv2_151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(750)=154 */ {750, xed3_phash_find_mapevex_map2_opcode0x28_vv2_154_l1}, +/*h(2203)=155 */ {2203, xed3_phash_find_mapevex_map2_opcode0x28_vv2_155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(174)=158 */ {174, xed3_phash_find_mapevex_map2_opcode0x28_vv2_158_l1}, +/*h(3224)=159 */ {3224, xed3_phash_find_mapevex_map2_opcode0x28_vv2_159_l1}, +/*h(729)=160 */ {729, xed3_phash_find_mapevex_map2_opcode0x28_vv2_160_l1}, +/*h(2792)=161 */ {2792, xed3_phash_find_mapevex_map2_opcode0x28_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3258)=163 */ {3258, xed3_phash_find_mapevex_map2_opcode0x28_vv2_163_l1}, +/*h(763)=164 */ {763, xed3_phash_find_mapevex_map2_opcode0x28_vv2_164_l1}, +/*h(2216)=165 */ {2216, xed3_phash_find_mapevex_map2_opcode0x28_vv2_165_l1}, +/*h(1462)=166 */ {1462, xed3_phash_find_mapevex_map2_opcode0x28_vv2_166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(187)=168 */ {187, xed3_phash_find_mapevex_map2_opcode0x28_vv2_168_l1}, +/*h(2250)=169 */ {2250, xed3_phash_find_mapevex_map2_opcode0x28_vv2_169_l1}, +/*h(2716)=170 */ {2716, xed3_phash_find_mapevex_map2_opcode0x28_vv2_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1208)=172 */ {1208, xed3_phash_find_mapevex_map2_opcode0x28_vv2_172_l1}, +/*h(2284)=173 */ {2284, xed3_phash_find_mapevex_map2_opcode0x28_vv2_173_l1}, +/*h(2750)=174 */ {2750, xed3_phash_find_mapevex_map2_opcode0x28_vv2_174_l1}, +/*h(1242)=175 */ {1242, xed3_phash_find_mapevex_map2_opcode0x28_vv2_175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3305)=177 */ {3305, xed3_phash_find_mapevex_map2_opcode0x28_vv2_177_l1}, +/*h(200)=178 */ {200, xed3_phash_find_mapevex_map2_opcode0x28_vv2_178_l1}, +/*h(666)=179 */ {666, xed3_phash_find_mapevex_map2_opcode0x28_vv2_179_l1}, +/*h(2729)=180 */ {2729, xed3_phash_find_mapevex_map2_opcode0x28_vv2_180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=182 */ {234, xed3_phash_find_mapevex_map2_opcode0x28_vv2_182_l1}, +/*h(700)=183 */ {700, xed3_phash_find_mapevex_map2_opcode0x28_vv2_183_l1}, +/*h(2763)=184 */ {2763, xed3_phash_find_mapevex_map2_opcode0x28_vv2_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(734)=187 */ {734, xed3_phash_find_mapevex_map2_opcode0x28_vv2_187_l1}, +/*h(2187)=188 */ {2187, xed3_phash_find_mapevex_map2_opcode0x28_vv2_188_l1}, +/*h(446)=189 */ {446, xed3_phash_find_mapevex_map2_opcode0x28_vv2_189_l1}, +/*h(158)=190 */ {158, xed3_phash_find_mapevex_map2_opcode0x28_vv2_190_l1}, +/*h(3208)=191 */ {3208, xed3_phash_find_mapevex_map2_opcode0x28_vv2_191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(713)=193 */ {713, xed3_phash_find_mapevex_map2_opcode0x28_vv2_193_l1}, +/*h(2776)=194 */ {2776, xed3_phash_find_mapevex_map2_opcode0x28_vv2_194_l1}, +/*h(3242)=195 */ {3242, xed3_phash_find_mapevex_map2_opcode0x28_vv2_195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(747)=197 */ {747, xed3_phash_find_mapevex_map2_opcode0x28_vv2_197_l1}, +/*h(2810)=198 */ {2810, xed3_phash_find_mapevex_map2_opcode0x28_vv2_198_l1}, +/*h(3276)=199 */ {3276, xed3_phash_find_mapevex_map2_opcode0x28_vv2_199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(171)=201 */ {171, xed3_phash_find_mapevex_map2_opcode0x28_vv2_201_l1}, +/*h(2234)=202 */ {2234, xed3_phash_find_mapevex_map2_opcode0x28_vv2_202_l1}, +/*h(2700)=203 */ {2700, xed3_phash_find_mapevex_map2_opcode0x28_vv2_203_l1}, +/*h(1192)=204 */ {1192, xed3_phash_find_mapevex_map2_opcode0x28_vv2_204_l1}, +/*h(438)=205 */ {438, xed3_phash_find_mapevex_map2_opcode0x28_vv2_205_l1}, +/*h(2268)=206 */ {2268, xed3_phash_find_mapevex_map2_opcode0x28_vv2_206_l1}, +/*h(760)=207 */ {760, xed3_phash_find_mapevex_map2_opcode0x28_vv2_207_l1}, +/*h(1226)=208 */ {1226, xed3_phash_find_mapevex_map2_opcode0x28_vv2_208_l1}, +/*h(2302)=209 */ {2302, xed3_phash_find_mapevex_map2_opcode0x28_vv2_209_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(184)=211 */ {184, xed3_phash_find_mapevex_map2_opcode0x28_vv2_211_l1}, +/*h(650)=212 */ {650, xed3_phash_find_mapevex_map2_opcode0x28_vv2_212_l1}, +/*h(2713)=213 */ {2713, xed3_phash_find_mapevex_map2_opcode0x28_vv2_213_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(218)=215 */ {218, xed3_phash_find_mapevex_map2_opcode0x28_vv2_215_l1}, +/*h(684)=216 */ {684, xed3_phash_find_mapevex_map2_opcode0x28_vv2_216_l1}, +/*h(2747)=217 */ {2747, xed3_phash_find_mapevex_map2_opcode0x28_vv2_217_l1}, +/*h(252)=218 */ {252, xed3_phash_find_mapevex_map2_opcode0x28_vv2_218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(718)=220 */ {718, xed3_phash_find_mapevex_map2_opcode0x28_vv2_220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1273)=222 */ {1273, xed3_phash_find_mapevex_map2_opcode0x28_vv2_222_l1}, +/*h(142)=223 */ {142, xed3_phash_find_mapevex_map2_opcode0x28_vv2_223_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(697)=226 */ {697, xed3_phash_find_mapevex_map2_opcode0x28_vv2_226_l1}, +/*h(2760)=227 */ {2760, xed3_phash_find_mapevex_map2_opcode0x28_vv2_227_l1}, +/*h(3226)=228 */ {3226, xed3_phash_find_mapevex_map2_opcode0x28_vv2_228_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(731)=230 */ {731, xed3_phash_find_mapevex_map2_opcode0x28_vv2_230_l1}, +/*h(2794)=231 */ {2794, xed3_phash_find_mapevex_map2_opcode0x28_vv2_231_l1}, +/*h(3260)=232 */ {3260, xed3_phash_find_mapevex_map2_opcode0x28_vv2_232_l1}, +/*h(155)=233 */ {155, xed3_phash_find_mapevex_map2_opcode0x28_vv2_233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2218)=235 */ {2218, xed3_phash_find_mapevex_map2_opcode0x28_vv2_235_l1}, +/*h(3294)=236 */ {3294, xed3_phash_find_mapevex_map2_opcode0x28_vv2_236_l1}, +/*h(1176)=237 */ {1176, xed3_phash_find_mapevex_map2_opcode0x28_vv2_237_l1}, +/*h(2252)=238 */ {2252, xed3_phash_find_mapevex_map2_opcode0x28_vv2_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(744)=240 */ {744, xed3_phash_find_mapevex_map2_opcode0x28_vv2_240_l1}, +/*h(1210)=241 */ {1210, xed3_phash_find_mapevex_map2_opcode0x28_vv2_241_l1}, +/*h(2286)=242 */ {2286, xed3_phash_find_mapevex_map2_opcode0x28_vv2_242_l1}, +/*h(168)=243 */ {168, xed3_phash_find_mapevex_map2_opcode0x28_vv2_243_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1244)=245 */ {1244, xed3_phash_find_mapevex_map2_opcode0x28_vv2_245_l1}, +/*h(2697)=246 */ {2697, xed3_phash_find_mapevex_map2_opcode0x28_vv2_246_l1}, +/*h(202)=247 */ {202, xed3_phash_find_mapevex_map2_opcode0x28_vv2_247_l1}, +/*h(668)=248 */ {668, xed3_phash_find_mapevex_map2_opcode0x28_vv2_248_l1}, +/*h(2265)=249 */ {2265, xed3_phash_find_mapevex_map2_opcode0x28_vv2_249_l1}, +/*h(2731)=250 */ {2731, xed3_phash_find_mapevex_map2_opcode0x28_vv2_250_l1}, +/*h(236)=251 */ {236, xed3_phash_find_mapevex_map2_opcode0x28_vv2_251_l1}, +/*h(702)=252 */ {702, xed3_phash_find_mapevex_map2_opcode0x28_vv2_252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1257)=255 */ {1257, xed3_phash_find_mapevex_map2_opcode0x28_vv2_255_l1}, +/*h(3320)=256 */ {3320, xed3_phash_find_mapevex_map2_opcode0x28_vv2_256_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(681)=259 */ {681, xed3_phash_find_mapevex_map2_opcode0x28_vv2_259_l1}, +/*h(2744)=260 */ {2744, xed3_phash_find_mapevex_map2_opcode0x28_vv2_260_l1}, +/*h(249)=261 */ {249, xed3_phash_find_mapevex_map2_opcode0x28_vv2_261_l1}, +/*h(715)=262 */ {715, xed3_phash_find_mapevex_map2_opcode0x28_vv2_262_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2778)=264 */ {2778, xed3_phash_find_mapevex_map2_opcode0x28_vv2_264_l1}, +/*h(3244)=265 */ {3244, xed3_phash_find_mapevex_map2_opcode0x28_vv2_265_l1}, +/*h(139)=266 */ {139, xed3_phash_find_mapevex_map2_opcode0x28_vv2_266_l1}, +/*h(2202)=267 */ {2202, xed3_phash_find_mapevex_map2_opcode0x28_vv2_267_l1}, +/*h(2812)=268 */ {2812, xed3_phash_find_mapevex_map2_opcode0x28_vv2_268_l1}, +/*h(3278)=269 */ {3278, xed3_phash_find_mapevex_map2_opcode0x28_vv2_269_l1}, +/*h(1160)=270 */ {1160, xed3_phash_find_mapevex_map2_opcode0x28_vv2_270_l1}, +/*h(2236)=271 */ {2236, xed3_phash_find_mapevex_map2_opcode0x28_vv2_271_l1}, +/*h(2702)=272 */ {2702, xed3_phash_find_mapevex_map2_opcode0x28_vv2_272_l1}, +/*h(728)=273 */ {728, xed3_phash_find_mapevex_map2_opcode0x28_vv2_273_l1}, +/*h(1194)=274 */ {1194, xed3_phash_find_mapevex_map2_opcode0x28_vv2_274_l1}, +/*h(2270)=275 */ {2270, xed3_phash_find_mapevex_map2_opcode0x28_vv2_275_l1}, +/*h(762)=276 */ {762, xed3_phash_find_mapevex_map2_opcode0x28_vv2_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1228)=278 */ {1228, xed3_phash_find_mapevex_map2_opcode0x28_vv2_278_l1}, +/*h(3291)=279 */ {3291, xed3_phash_find_mapevex_map2_opcode0x28_vv2_279_l1}, +/*h(186)=280 */ {186, xed3_phash_find_mapevex_map2_opcode0x28_vv2_280_l1}, +/*h(652)=281 */ {652, xed3_phash_find_mapevex_map2_opcode0x28_vv2_281_l1}, +/*h(2715)=282 */ {2715, xed3_phash_find_mapevex_map2_opcode0x28_vv2_282_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(220)=284 */ {220, xed3_phash_find_mapevex_map2_opcode0x28_vv2_284_l1}, +/*h(686)=285 */ {686, xed3_phash_find_mapevex_map2_opcode0x28_vv2_285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(254)=288 */ {254, xed3_phash_find_mapevex_map2_opcode0x28_vv2_288_l1}, +/*h(3304)=289 */ {3304, xed3_phash_find_mapevex_map2_opcode0x28_vv2_289_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(665)=291 */ {665, xed3_phash_find_mapevex_map2_opcode0x28_vv2_291_l1}, +/*h(1275)=292 */ {1275, xed3_phash_find_mapevex_map2_opcode0x28_vv2_292_l1}, +/*h(2728)=293 */ {2728, xed3_phash_find_mapevex_map2_opcode0x28_vv2_293_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 294ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x29_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[300] = { +/*h(1198)=0 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1198, 5164}, +/*empty slot1 */ {0,0}, +/*h(1166)=2 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1166, 5164}, +/*h(1273)=3 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1273, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1241)=6 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1241, 5165}, +/*empty slot1 */ {0,0}, +/*h(1209)=8 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1209, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1177)=11 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1177, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(760)=15 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {760, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(728)=18 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {728, 5169}, +/*h(236)=19 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {236, 5166}, +/*h(696)=20 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {696, 5169}, +/*h(204)=21 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {204, 5166}, +/*empty slot1 */ {0,0}, +/*h(664)=23 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {664, 5169}, +/*h(172)=24 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {172, 5166}, +/*empty slot1 */ {0,0}, +/*h(140)=26 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {140, 5166}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1274)=31 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1274, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1242)=34 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1242, 5165}, +/*h(750)=35 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {750, 5168}, +/*h(1210)=36 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1210, 5165}, +/*h(718)=37 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {718, 5168}, +/*empty slot1 */ {0,0}, +/*h(1178)=39 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1178, 5165}, +/*h(686)=40 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {686, 5168}, +/*empty slot1 */ {0,0}, +/*h(654)=42 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {654, 5168}, +/*h(761)=43 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {761, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(729)=46 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {729, 5169}, +/*empty slot1 */ {0,0}, +/*h(697)=48 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {697, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(665)=51 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {665, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(248)=55 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {248, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=58 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {216, 5167}, +/*h(1275)=59 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1275, 5165}, +/*h(184)=60 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {184, 5167}, +/*empty slot1 */ {0,0}, +/*h(1243)=62 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1243, 5165}, +/*h(152)=63 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {152, 5167}, +/*h(1211)=64 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1211, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1179)=67 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1179, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(762)=71 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {762, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(730)=74 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {730, 5169}, +/*h(238)=75 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {238, 5166}, +/*h(698)=76 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {698, 5169}, +/*h(206)=77 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {206, 5166}, +/*empty slot1 */ {0,0}, +/*h(666)=79 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {666, 5169}, +/*h(174)=80 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {174, 5166}, +/*empty slot1 */ {0,0}, +/*h(142)=82 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {142, 5166}, +/*h(249)=83 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {249, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(217)=86 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {217, 5167}, +/*h(1276)=87 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1276, 5164}, +/*h(185)=88 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {185, 5167}, +/*empty slot1 */ {0,0}, +/*h(1244)=90 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1244, 5164}, +/*h(153)=91 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {153, 5167}, +/*h(1212)=92 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1212, 5164}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1180)=95 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1180, 5164}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(763)=99 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {763, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(731)=102 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {731, 5169}, +/*empty slot1 */ {0,0}, +/*h(699)=104 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {699, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(667)=107 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {667, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(250)=111 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {250, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(218)=114 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {218, 5167}, +/*empty slot1 */ {0,0}, +/*h(186)=116 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {186, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(154)=119 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {154, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1256)=126 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1256, 5165}, +/*h(764)=127 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {764, 5168}, +/*h(1470)=128 EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0*/ {1470, 6545}, +/*h(1224)=129 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1224, 5165}, +/*h(732)=130 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {732, 5168}, +/*h(1192)=131 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1192, 5165}, +/*h(700)=132 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {700, 5168}, +/*empty slot1 */ {0,0}, +/*h(1160)=134 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1160, 5165}, +/*h(668)=135 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {668, 5168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(251)=139 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {251, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(219)=142 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {219, 5167}, +/*h(1278)=143 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1278, 5164}, +/*h(187)=144 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {187, 5167}, +/*empty slot1 */ {0,0}, +/*h(1246)=146 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1246, 5164}, +/*h(155)=147 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {155, 5167}, +/*h(1214)=148 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1214, 5164}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1182)=151 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1182, 5164}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1257)=154 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1257, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1225)=157 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1225, 5165}, +/*empty slot1 */ {0,0}, +/*h(1193)=159 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1193, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1161)=162 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1161, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(744)=166 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {744, 5169}, +/*h(252)=167 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {252, 5166}, +/*h(958)=168 EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0*/ {958, 6544}, +/*h(712)=169 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {712, 5169}, +/*h(220)=170 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {220, 5166}, +/*h(680)=171 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {680, 5169}, +/*h(188)=172 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {188, 5166}, +/*empty slot1 */ {0,0}, +/*h(648)=174 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {648, 5169}, +/*h(156)=175 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {156, 5166}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1258)=182 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1258, 5165}, +/*h(766)=183 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {766, 5168}, +/*empty slot1 */ {0,0}, +/*h(1226)=185 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1226, 5165}, +/*h(734)=186 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {734, 5168}, +/*h(1194)=187 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1194, 5165}, +/*h(702)=188 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {702, 5168}, +/*empty slot1 */ {0,0}, +/*h(1162)=190 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1162, 5165}, +/*h(670)=191 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {670, 5168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(745)=194 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {745, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(713)=197 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {713, 5169}, +/*empty slot1 */ {0,0}, +/*h(681)=199 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {681, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(649)=202 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {649, 5169}, +/*empty slot1 */ {0,0}, +/*h(1462)=204 EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0*/ {1462, 6506}, +/*empty slot1 */ {0,0}, +/*h(232)=206 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {232, 5167}, +/*empty slot1 */ {0,0}, +/*h(446)=208 EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {446, 6543}, +/*h(200)=209 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {200, 5167}, +/*h(1259)=210 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1259, 5165}, +/*h(168)=211 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {168, 5167}, +/*empty slot1 */ {0,0}, +/*h(1227)=213 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1227, 5165}, +/*h(136)=214 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {136, 5167}, +/*h(1195)=215 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1195, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1163)=218 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1163, 5165}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(746)=222 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {746, 5169}, +/*h(254)=223 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {254, 5166}, +/*empty slot1 */ {0,0}, +/*h(714)=225 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {714, 5169}, +/*h(222)=226 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {222, 5166}, +/*h(682)=227 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {682, 5169}, +/*h(190)=228 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {190, 5166}, +/*empty slot1 */ {0,0}, +/*h(650)=230 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {650, 5169}, +/*h(158)=231 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {158, 5166}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(233)=234 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {233, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(201)=237 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {201, 5167}, +/*h(1260)=238 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1260, 5164}, +/*h(169)=239 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {169, 5167}, +/*empty slot1 */ {0,0}, +/*h(1228)=241 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1228, 5164}, +/*h(137)=242 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {137, 5167}, +/*h(1196)=243 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1196, 5164}, +/*h(950)=244 EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0*/ {950, 6505}, +/*empty slot1 */ {0,0}, +/*h(1164)=246 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1164, 5164}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(747)=250 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {747, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(715)=253 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {715, 5169}, +/*empty slot1 */ {0,0}, +/*h(683)=255 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {683, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(651)=258 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {651, 5169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(234)=262 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {234, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(202)=265 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {202, 5167}, +/*empty slot1 */ {0,0}, +/*h(170)=267 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {170, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(138)=270 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {138, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1272)=275 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1272, 5165}, +/*empty slot1 */ {0,0}, +/*h(1240)=277 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1240, 5165}, +/*h(748)=278 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {748, 5168}, +/*empty slot1 */ {0,0}, +/*h(1208)=280 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1208, 5165}, +/*h(716)=281 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {716, 5168}, +/*h(1176)=282 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {1176, 5165}, +/*h(684)=283 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {684, 5168}, +/*h(438)=284 EVV 0x29 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0*/ {438, 6504}, +/*empty slot1 */ {0,0}, +/*h(652)=286 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {652, 5168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(235)=290 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {235, 5167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(203)=293 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {203, 5167}, +/*h(1262)=294 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1262, 5164}, +/*h(171)=295 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {171, 5167}, +/*empty slot1 */ {0,0}, +/*h(1230)=297 EVV 0x29 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {1230, 5164}, +/*h(139)=298 EVV 0x29 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {139, 5167}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((28*key % 599) % 300); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(690)=0 EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {690, 4992}, +/*h(178)=1 EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {178, 4991}, +/*h(1470)=2 EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0*/ {1470, 6000}, +/*h(958)=3 EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0*/ {958, 6002}, +/*h(446)=4 EVV 0x2A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {446, 6001}, +/*h(1202)=5 EVV 0x2A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {1202, 4990} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 6265}, +/*h(10)=3 EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6260}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 6263}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 6265}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 6261}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 6263}, +/*h(74)=13 EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6264}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x2B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 6261}, +/*h(42)=17 EVV 0x2B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6262} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5883}, +/*h(14)=1 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5873}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5882}, +/*h(15)=4 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 5871}, +/*h(111)=5 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 5871}, +/*h(43)=6 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 5878}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5876}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5879}, +/*h(45)=12 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5876}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5879}, +/*h(46)=15 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5875}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5877}, +/*h(47)=18 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 5871}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 5878}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5872}, +/*h(8)=24 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5881}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5872}, +/*h(9)=27 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5881}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5870}, +/*h(10)=30 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5880}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 5871}, +/*h(11)=33 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 5878}, +/*h(107)=34 EVV 0x2C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 5878}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5874}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5883}, +/*h(13)=39 EVV 0x2C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5874}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x2d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 5887}, +/*h(15)=2 EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 5885}, +/*h(12)=3 EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 5886}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 5884}, +/*h(11)=6 EVV 0x2D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 5888}, +/*h(8)=7 EVV 0x2D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 5889} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x30_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 6548}, +/*h(1498)=1 EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 6548}, +/*h(728)=2 EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {728, 6551}, +/*h(218)=3 EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 6546}, +/*h(1242)=4 EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 6546}, +/*h(472)=5 EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {472, 6549}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x30 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_HALFMEM()*/ {216, 6547}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 6550}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1624, 6557}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1368, 6555}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1112, 6553}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 6556}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 6554}, +/*h(600)=30 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {600, 6557}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 6552}, +/*h(344)=33 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {344, 6555}, +/*h(1628)=34 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1628, 6557}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {88, 6553}, +/*h(1372)=37 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1372, 6555}, +/*h(602)=38 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 6556}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {1116, 6553}, +/*h(346)=41 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 6554}, +/*h(1630)=42 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 6556}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 6552}, +/*h(1374)=45 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 6554}, +/*h(604)=46 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {604, 6557}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 6552}, +/*h(348)=49 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {348, 6555}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x30 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_HALFMEM()*/ {92, 6553}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 6556}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 6554}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x30 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 6552}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x30 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 6550}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x31_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5384}, +/*h(1498)=1 EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5384}, +/*h(728)=2 EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {728, 5381}, +/*h(218)=3 EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5382}, +/*h(1242)=4 EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5382}, +/*h(472)=5 EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {472, 5385}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x31 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {216, 5383}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5380}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1624, 5501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1368, 5505}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1112, 5503}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5504}, +/*h(600)=30 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {600, 5501}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5502}, +/*h(344)=33 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {344, 5505}, +/*h(1628)=34 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1628, 5501}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {88, 5503}, +/*h(1372)=37 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1372, 5505}, +/*h(602)=38 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5500}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {1116, 5503}, +/*h(346)=41 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5504}, +/*h(1630)=42 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5500}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5502}, +/*h(1374)=45 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5504}, +/*h(604)=46 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {604, 5501}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5502}, +/*h(348)=49 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {348, 5505}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x31 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_QUARTERMEM()*/ {92, 5503}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5504}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x31 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x31 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5380}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x32_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5396}, +/*h(1498)=1 EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5396}, +/*h(728)=2 EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {728, 5393}, +/*h(218)=3 EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5394}, +/*h(1242)=4 EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5394}, +/*h(472)=5 EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {472, 5397}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x32 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {216, 5395}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5392}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1624, 5507}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1368, 5511}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1112, 5509}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5506}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5510}, +/*h(600)=30 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {600, 5507}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5508}, +/*h(344)=33 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {344, 5511}, +/*h(1628)=34 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1628, 5507}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {88, 5509}, +/*h(1372)=37 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1372, 5511}, +/*h(602)=38 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5506}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {1116, 5509}, +/*h(346)=41 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5510}, +/*h(1630)=42 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5506}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5508}, +/*h(1374)=45 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5510}, +/*h(604)=46 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {604, 5507}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5508}, +/*h(348)=49 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {348, 5511}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x32 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_8_BITS() NELEM_EIGHTHMEM()*/ {92, 5509}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5506}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5510}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x32 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5508}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x32 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5392}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x33_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5390}, +/*h(1498)=1 EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5390}, +/*h(728)=2 EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {728, 5387}, +/*h(218)=3 EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5388}, +/*h(1242)=4 EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5388}, +/*h(472)=5 EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {472, 5391}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x33 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_HALFMEM()*/ {216, 5389}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5386}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1624, 5519}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1368, 5523}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1112, 5521}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5518}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5522}, +/*h(600)=30 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {600, 5519}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5520}, +/*h(344)=33 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {344, 5523}, +/*h(1628)=34 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1628, 5519}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {88, 5521}, +/*h(1372)=37 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1372, 5523}, +/*h(602)=38 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5518}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {1116, 5521}, +/*h(346)=41 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5522}, +/*h(1630)=42 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5518}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5520}, +/*h(1374)=45 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5522}, +/*h(604)=46 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {604, 5519}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5520}, +/*h(348)=49 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {348, 5523}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x33 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_HALFMEM()*/ {92, 5521}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5518}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5522}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x33 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5520}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x33 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5386}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x34_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[66] = { +/*h(474)=0 EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5408}, +/*h(1498)=1 EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5408}, +/*h(728)=2 EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {728, 5405}, +/*h(218)=3 EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5406}, +/*h(1242)=4 EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5406}, +/*h(472)=5 EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {472, 5409}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x34 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {216, 5407}, +/*empty slot1 */ {0,0}, +/*h(730)=10 EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5404}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1624)=18 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1624, 5525}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1368)=21 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1368, 5529}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1112)=24 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1112, 5527}, +/*empty slot1 */ {0,0}, +/*h(1626)=26 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1626, 5524}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1370)=29 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1370, 5528}, +/*h(600)=30 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {600, 5525}, +/*empty slot1 */ {0,0}, +/*h(1114)=32 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1114, 5526}, +/*h(344)=33 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {344, 5529}, +/*h(1628)=34 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1628, 5525}, +/*empty slot1 */ {0,0}, +/*h(88)=36 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {88, 5527}, +/*h(1372)=37 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1372, 5529}, +/*h(602)=38 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {602, 5524}, +/*empty slot1 */ {0,0}, +/*h(1116)=40 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {1116, 5527}, +/*h(346)=41 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {346, 5528}, +/*h(1630)=42 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {1630, 5524}, +/*empty slot1 */ {0,0}, +/*h(90)=44 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {90, 5526}, +/*h(1374)=45 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {1374, 5528}, +/*h(604)=46 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {604, 5525}, +/*empty slot1 */ {0,0}, +/*h(1118)=48 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {1118, 5526}, +/*h(348)=49 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {348, 5529}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=52 EVV 0x34 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ESIZE_16_BITS() NELEM_QUARTERMEM()*/ {92, 5527}, +/*empty slot1 */ {0,0}, +/*h(606)=54 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR*/ {606, 5524}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=57 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR*/ {350, 5528}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=60 EVV 0x34 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR*/ {94, 5526}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1754)=64 EVV 0x34 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5404}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 79) % 66); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x35_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=2 EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {600, 5513}, +/*h(218)=3 EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 5400}, +/*empty slot1 */ {0,0}, +/*h(1624)=5 EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {1624, 5513}, +/*h(1242)=6 EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 5400}, +/*empty slot1 */ {0,0}, +/*h(602)=8 EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5512}, +/*h(344)=9 EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {344, 5517}, +/*empty slot1 */ {0,0}, +/*h(1626)=11 EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 5512}, +/*h(1368)=12 EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {1368, 5517}, +/*empty slot1 */ {0,0}, +/*h(728)=14 EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {728, 5399}, +/*h(346)=15 EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5516}, +/*h(88)=16 EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {88, 5515}, +/*empty slot1 */ {0,0}, +/*h(1370)=18 EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 5516}, +/*h(1112)=19 EVV 0x35 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALFMEM()*/ {1112, 5515}, +/*h(730)=20 EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 5398}, +/*h(472)=21 EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {472, 5403}, +/*h(90)=22 EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5514}, +/*h(1754)=23 EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 5398}, +/*empty slot1 */ {0,0}, +/*h(1114)=25 EVV 0x35 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 5514}, +/*empty slot1 */ {0,0}, +/*h(474)=27 EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 5402}, +/*h(216)=28 EVV 0x35 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_HALFMEM()*/ {216, 5401}, +/*empty slot1 */ {0,0}, +/*h(1498)=30 EVV 0x35 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 5402} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 31); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x36_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5282}, +/*h(73)=1 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5213}, +/*h(77)=2 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5279}, +/*h(41)=3 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5215}, +/*h(45)=4 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5283}, +/*h(72)=5 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5213}, +/*h(76)=6 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5279}, +/*h(40)=7 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5215}, +/*h(44)=8 EVV 0x36 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5283}, +/*h(74)=9 EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5212}, +/*h(78)=10 EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5278}, +/*h(42)=11 EVV 0x36 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5214} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 43) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x37_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5177}, +/*h(46)=1 EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0*/ {46, 5180}, +/*h(12)=2 EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5179}, +/*h(77)=3 EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5177}, +/*h(13)=4 EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5179}, +/*h(78)=5 EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0*/ {78, 5176}, +/*h(44)=6 EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5181}, +/*h(14)=7 EVV 0x37 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0*/ {14, 5178}, +/*h(45)=8 EVV 0x37 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5181} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x38_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[599] = { +/*h(1198)=0 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1198, 6484}, +/*h(200)=1 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {200, 6481}, +/*h(2796)=2 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2796, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2198)=5 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2198, 6480}, +/*h(1200)=6 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1200, 6485}, +/*h(202)=7 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {202, 6481}, +/*h(2798)=8 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2798, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2200)=11 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2200, 6481}, +/*h(1202)=12 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1202, 6485}, +/*h(204)=13 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {204, 6480}, +/*h(2800)=14 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2800, 6483}, +/*empty slot1 */ {0,0}, +/*h(3200)=16 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3200, 6485}, +/*h(2202)=17 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2202, 6481}, +/*h(1204)=18 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1204, 6484}, +/*h(206)=19 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {206, 6480}, +/*h(2802)=20 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2802, 6483}, +/*empty slot1 */ {0,0}, +/*h(3202)=22 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3202, 6485}, +/*h(2204)=23 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2204, 6480}, +/*h(1206)=24 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1206, 6484}, +/*h(208)=25 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {208, 6481}, +/*h(2804)=26 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2804, 6482}, +/*empty slot1 */ {0,0}, +/*h(3204)=28 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3204, 6484}, +/*h(2206)=29 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2206, 6480}, +/*h(1208)=30 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1208, 6485}, +/*h(210)=31 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {210, 6481}, +/*h(2806)=32 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2806, 6482}, +/*empty slot1 */ {0,0}, +/*h(3206)=34 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3206, 6484}, +/*h(2208)=35 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2208, 6481}, +/*h(1210)=36 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1210, 6485}, +/*h(212)=37 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {212, 6480}, +/*h(2808)=38 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2808, 6483}, +/*empty slot1 */ {0,0}, +/*h(3208)=40 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3208, 6485}, +/*h(2210)=41 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2210, 6481}, +/*h(1212)=42 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1212, 6484}, +/*h(214)=43 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {214, 6480}, +/*h(2810)=44 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2810, 6483}, +/*empty slot1 */ {0,0}, +/*h(3210)=46 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3210, 6485}, +/*h(2212)=47 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2212, 6480}, +/*h(1214)=48 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1214, 6484}, +/*h(216)=49 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {216, 6481}, +/*h(2812)=50 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2812, 6482}, +/*empty slot1 */ {0,0}, +/*h(3212)=52 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3212, 6484}, +/*h(2214)=53 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2214, 6480}, +/*h(1216)=54 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1216, 6485}, +/*h(218)=55 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {218, 6481}, +/*h(2814)=56 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2814, 6482}, +/*empty slot1 */ {0,0}, +/*h(3214)=58 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3214, 6484}, +/*h(2216)=59 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2216, 6481}, +/*h(1218)=60 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1218, 6485}, +/*h(220)=61 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {220, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3216)=64 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3216, 6485}, +/*h(2218)=65 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2218, 6481}, +/*h(1220)=66 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1220, 6484}, +/*h(222)=67 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {222, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3218)=70 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3218, 6485}, +/*h(2220)=71 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2220, 6480}, +/*h(1222)=72 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1222, 6484}, +/*h(224)=73 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {224, 6481}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3220)=76 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3220, 6484}, +/*h(2222)=77 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2222, 6480}, +/*h(1224)=78 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1224, 6485}, +/*h(226)=79 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {226, 6481}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3222)=82 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3222, 6484}, +/*h(2224)=83 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2224, 6481}, +/*h(1226)=84 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1226, 6485}, +/*h(228)=85 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {228, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3224)=88 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3224, 6485}, +/*h(2226)=89 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2226, 6481}, +/*h(1228)=90 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1228, 6484}, +/*h(230)=91 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {230, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3226)=94 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3226, 6485}, +/*h(2228)=95 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2228, 6480}, +/*h(1230)=96 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1230, 6484}, +/*h(232)=97 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {232, 6481}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3228)=100 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3228, 6484}, +/*h(2230)=101 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2230, 6480}, +/*h(1232)=102 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1232, 6485}, +/*h(234)=103 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {234, 6481}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3230)=106 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3230, 6484}, +/*h(2232)=107 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2232, 6481}, +/*h(1234)=108 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1234, 6485}, +/*h(236)=109 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {236, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3232)=112 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3232, 6485}, +/*h(2234)=113 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2234, 6481}, +/*h(1236)=114 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1236, 6484}, +/*h(238)=115 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {238, 6480}, +/*h(438)=116 EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0*/ {438, 6513}, +/*empty slot1 */ {0,0}, +/*h(3234)=118 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3234, 6485}, +/*h(2236)=119 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2236, 6480}, +/*h(1238)=120 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1238, 6484}, +/*h(240)=121 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {240, 6481}, +/*empty slot1 */ {0,0}, +/*h(640)=123 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {640, 6483}, +/*h(3236)=124 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3236, 6484}, +/*h(2238)=125 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2238, 6480}, +/*h(1240)=126 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1240, 6485}, +/*h(242)=127 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {242, 6481}, +/*empty slot1 */ {0,0}, +/*h(642)=129 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {642, 6483}, +/*h(3238)=130 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3238, 6484}, +/*h(2240)=131 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2240, 6481}, +/*h(1242)=132 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1242, 6485}, +/*h(244)=133 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {244, 6480}, +/*empty slot1 */ {0,0}, +/*h(644)=135 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {644, 6482}, +/*h(3240)=136 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3240, 6485}, +/*h(2242)=137 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2242, 6481}, +/*h(1244)=138 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1244, 6484}, +/*h(246)=139 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {246, 6480}, +/*h(446)=140 EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {446, 6516}, +/*h(646)=141 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {646, 6482}, +/*h(3242)=142 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3242, 6485}, +/*h(2244)=143 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2244, 6480}, +/*h(1246)=144 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1246, 6484}, +/*h(248)=145 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {248, 6481}, +/*empty slot1 */ {0,0}, +/*h(648)=147 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {648, 6483}, +/*h(3244)=148 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3244, 6484}, +/*h(2246)=149 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2246, 6480}, +/*h(1248)=150 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1248, 6485}, +/*h(250)=151 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {250, 6481}, +/*empty slot1 */ {0,0}, +/*h(650)=153 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {650, 6483}, +/*h(3246)=154 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3246, 6484}, +/*h(2248)=155 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2248, 6481}, +/*h(1250)=156 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1250, 6485}, +/*h(252)=157 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {252, 6480}, +/*empty slot1 */ {0,0}, +/*h(652)=159 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {652, 6482}, +/*h(3248)=160 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3248, 6485}, +/*h(2250)=161 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2250, 6481}, +/*h(1252)=162 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1252, 6484}, +/*h(254)=163 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {254, 6480}, +/*empty slot1 */ {0,0}, +/*h(654)=165 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {654, 6482}, +/*h(3250)=166 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3250, 6485}, +/*h(2252)=167 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2252, 6480}, +/*h(1254)=168 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1254, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(656)=171 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {656, 6483}, +/*h(3252)=172 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3252, 6484}, +/*h(2254)=173 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2254, 6480}, +/*h(1256)=174 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1256, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(658)=177 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {658, 6483}, +/*h(3254)=178 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3254, 6484}, +/*h(2256)=179 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2256, 6481}, +/*h(1258)=180 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1258, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(660)=183 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {660, 6482}, +/*h(3256)=184 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3256, 6485}, +/*h(2258)=185 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2258, 6481}, +/*h(1260)=186 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1260, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(662)=189 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {662, 6482}, +/*h(3258)=190 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3258, 6485}, +/*h(2260)=191 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2260, 6480}, +/*h(1262)=192 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1262, 6484}, +/*h(1462)=193 EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0*/ {1462, 6515}, +/*empty slot1 */ {0,0}, +/*h(664)=195 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {664, 6483}, +/*h(3260)=196 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3260, 6484}, +/*h(2262)=197 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2262, 6480}, +/*h(1264)=198 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1264, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(666)=201 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {666, 6483}, +/*h(3262)=202 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3262, 6484}, +/*h(2264)=203 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2264, 6481}, +/*h(1266)=204 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1266, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(668)=207 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {668, 6482}, +/*h(3264)=208 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3264, 6485}, +/*h(2266)=209 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2266, 6481}, +/*h(1268)=210 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1268, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(670)=213 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {670, 6482}, +/*h(3266)=214 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3266, 6485}, +/*h(2268)=215 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2268, 6480}, +/*h(1270)=216 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1270, 6484}, +/*h(1470)=217 EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0*/ {1470, 6518}, +/*empty slot1 */ {0,0}, +/*h(672)=219 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {672, 6483}, +/*h(3268)=220 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3268, 6484}, +/*h(2270)=221 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2270, 6480}, +/*h(1272)=222 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1272, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(674)=225 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {674, 6483}, +/*h(3270)=226 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3270, 6484}, +/*h(2272)=227 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2272, 6481}, +/*h(1274)=228 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1274, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(676)=231 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {676, 6482}, +/*h(3272)=232 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3272, 6485}, +/*h(2274)=233 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2274, 6481}, +/*h(1276)=234 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1276, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(678)=237 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {678, 6482}, +/*h(3274)=238 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3274, 6485}, +/*h(2276)=239 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2276, 6480}, +/*h(1278)=240 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1278, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(680)=243 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {680, 6483}, +/*h(3276)=244 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3276, 6484}, +/*h(2278)=245 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2278, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(682)=249 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {682, 6483}, +/*h(3278)=250 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3278, 6484}, +/*h(2280)=251 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2280, 6481}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(684)=255 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {684, 6482}, +/*h(3280)=256 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3280, 6485}, +/*h(2282)=257 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2282, 6481}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(686)=261 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {686, 6482}, +/*h(3282)=262 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3282, 6485}, +/*h(2284)=263 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2284, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(688)=267 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {688, 6483}, +/*h(3284)=268 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3284, 6484}, +/*h(2286)=269 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2286, 6480}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(690)=273 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {690, 6483}, +/*h(3286)=274 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3286, 6484}, +/*h(2288)=275 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2288, 6481}, +/*empty slot1 */ {0,0}, +/*h(2688)=277 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2688, 6483}, +/*empty slot1 */ {0,0}, +/*h(692)=279 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {692, 6482}, +/*h(3288)=280 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3288, 6485}, +/*h(2290)=281 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2290, 6481}, +/*empty slot1 */ {0,0}, +/*h(2690)=283 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2690, 6483}, +/*empty slot1 */ {0,0}, +/*h(694)=285 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {694, 6482}, +/*h(3290)=286 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3290, 6485}, +/*h(2292)=287 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2292, 6480}, +/*empty slot1 */ {0,0}, +/*h(2692)=289 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2692, 6482}, +/*empty slot1 */ {0,0}, +/*h(696)=291 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {696, 6483}, +/*h(3292)=292 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3292, 6484}, +/*h(2294)=293 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2294, 6480}, +/*empty slot1 */ {0,0}, +/*h(2694)=295 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2694, 6482}, +/*empty slot1 */ {0,0}, +/*h(698)=297 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {698, 6483}, +/*h(3294)=298 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3294, 6484}, +/*h(2296)=299 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2296, 6481}, +/*empty slot1 */ {0,0}, +/*h(2696)=301 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2696, 6483}, +/*empty slot1 */ {0,0}, +/*h(700)=303 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {700, 6482}, +/*h(3296)=304 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3296, 6485}, +/*h(2298)=305 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2298, 6481}, +/*empty slot1 */ {0,0}, +/*h(2698)=307 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2698, 6483}, +/*empty slot1 */ {0,0}, +/*h(702)=309 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {702, 6482}, +/*h(3298)=310 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3298, 6485}, +/*h(2300)=311 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2300, 6480}, +/*empty slot1 */ {0,0}, +/*h(2700)=313 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2700, 6482}, +/*empty slot1 */ {0,0}, +/*h(704)=315 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {704, 6483}, +/*h(3300)=316 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3300, 6484}, +/*h(2302)=317 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2302, 6480}, +/*empty slot1 */ {0,0}, +/*h(2702)=319 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2702, 6482}, +/*empty slot1 */ {0,0}, +/*h(706)=321 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {706, 6483}, +/*h(3302)=322 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3302, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2704)=325 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2704, 6483}, +/*empty slot1 */ {0,0}, +/*h(708)=327 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {708, 6482}, +/*h(3304)=328 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3304, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2706)=331 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2706, 6483}, +/*empty slot1 */ {0,0}, +/*h(710)=333 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {710, 6482}, +/*h(3306)=334 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3306, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2708)=337 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2708, 6482}, +/*empty slot1 */ {0,0}, +/*h(712)=339 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {712, 6483}, +/*h(3308)=340 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3308, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2710)=343 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2710, 6482}, +/*empty slot1 */ {0,0}, +/*h(714)=345 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {714, 6483}, +/*h(3310)=346 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3310, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2712)=349 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2712, 6483}, +/*empty slot1 */ {0,0}, +/*h(716)=351 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {716, 6482}, +/*h(3312)=352 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3312, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2714)=355 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2714, 6483}, +/*empty slot1 */ {0,0}, +/*h(718)=357 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {718, 6482}, +/*h(3314)=358 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3314, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2716)=361 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2716, 6482}, +/*empty slot1 */ {0,0}, +/*h(720)=363 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {720, 6483}, +/*h(3316)=364 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3316, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2718)=367 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2718, 6482}, +/*empty slot1 */ {0,0}, +/*h(722)=369 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {722, 6483}, +/*h(3318)=370 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3318, 6484}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2720)=373 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2720, 6483}, +/*empty slot1 */ {0,0}, +/*h(724)=375 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {724, 6482}, +/*h(3320)=376 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3320, 6485}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2722)=379 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2722, 6483}, +/*empty slot1 */ {0,0}, +/*h(726)=381 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {726, 6482}, +/*h(3322)=382 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {3322, 6485}, +/*empty slot1 */ {0,0}, +/*h(128)=384 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {128, 6481}, +/*h(2724)=385 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2724, 6482}, +/*empty slot1 */ {0,0}, +/*h(728)=387 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {728, 6483}, +/*h(3324)=388 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3324, 6484}, +/*empty slot1 */ {0,0}, +/*h(130)=390 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {130, 6481}, +/*h(2726)=391 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2726, 6482}, +/*empty slot1 */ {0,0}, +/*h(730)=393 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {730, 6483}, +/*h(3326)=394 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3326, 6484}, +/*empty slot1 */ {0,0}, +/*h(132)=396 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {132, 6480}, +/*h(2728)=397 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2728, 6483}, +/*empty slot1 */ {0,0}, +/*h(732)=399 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {732, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(134)=402 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {134, 6480}, +/*h(2730)=403 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2730, 6483}, +/*empty slot1 */ {0,0}, +/*h(734)=405 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {734, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(136)=408 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {136, 6481}, +/*h(2732)=409 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2732, 6482}, +/*empty slot1 */ {0,0}, +/*h(736)=411 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {736, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(138)=414 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {138, 6481}, +/*h(2734)=415 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2734, 6482}, +/*empty slot1 */ {0,0}, +/*h(738)=417 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {738, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(140)=420 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {140, 6480}, +/*h(2736)=421 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2736, 6483}, +/*empty slot1 */ {0,0}, +/*h(740)=423 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {740, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(142)=426 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {142, 6480}, +/*h(2738)=427 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2738, 6483}, +/*empty slot1 */ {0,0}, +/*h(742)=429 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {742, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(144)=432 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {144, 6481}, +/*h(2740)=433 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2740, 6482}, +/*empty slot1 */ {0,0}, +/*h(744)=435 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {744, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(146)=438 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {146, 6481}, +/*h(2742)=439 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2742, 6482}, +/*empty slot1 */ {0,0}, +/*h(746)=441 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {746, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(148)=444 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {148, 6480}, +/*h(2744)=445 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2744, 6483}, +/*empty slot1 */ {0,0}, +/*h(748)=447 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {748, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(150)=450 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {150, 6480}, +/*h(2746)=451 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2746, 6483}, +/*empty slot1 */ {0,0}, +/*h(750)=453 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {750, 6482}, +/*h(950)=454 EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0*/ {950, 6514}, +/*empty slot1 */ {0,0}, +/*h(152)=456 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {152, 6481}, +/*h(2748)=457 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2748, 6482}, +/*empty slot1 */ {0,0}, +/*h(752)=459 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {752, 6483}, +/*empty slot1 */ {0,0}, +/*h(1152)=461 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1152, 6485}, +/*h(154)=462 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {154, 6481}, +/*h(2750)=463 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2750, 6482}, +/*empty slot1 */ {0,0}, +/*h(754)=465 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {754, 6483}, +/*empty slot1 */ {0,0}, +/*h(1154)=467 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1154, 6485}, +/*h(156)=468 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {156, 6480}, +/*h(2752)=469 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2752, 6483}, +/*empty slot1 */ {0,0}, +/*h(756)=471 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {756, 6482}, +/*empty slot1 */ {0,0}, +/*h(1156)=473 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1156, 6484}, +/*h(158)=474 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {158, 6480}, +/*h(2754)=475 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2754, 6483}, +/*empty slot1 */ {0,0}, +/*h(758)=477 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {758, 6482}, +/*h(958)=478 EVV 0x38 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0*/ {958, 6517}, +/*h(1158)=479 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1158, 6484}, +/*h(160)=480 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {160, 6481}, +/*h(2756)=481 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2756, 6482}, +/*empty slot1 */ {0,0}, +/*h(760)=483 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {760, 6483}, +/*empty slot1 */ {0,0}, +/*h(1160)=485 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1160, 6485}, +/*h(162)=486 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {162, 6481}, +/*h(2758)=487 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2758, 6482}, +/*empty slot1 */ {0,0}, +/*h(762)=489 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {762, 6483}, +/*empty slot1 */ {0,0}, +/*h(1162)=491 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1162, 6485}, +/*h(164)=492 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {164, 6480}, +/*h(2760)=493 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2760, 6483}, +/*empty slot1 */ {0,0}, +/*h(764)=495 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {764, 6482}, +/*empty slot1 */ {0,0}, +/*h(1164)=497 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1164, 6484}, +/*h(166)=498 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {166, 6480}, +/*h(2762)=499 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2762, 6483}, +/*empty slot1 */ {0,0}, +/*h(766)=501 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {766, 6482}, +/*empty slot1 */ {0,0}, +/*h(1166)=503 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1166, 6484}, +/*h(168)=504 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {168, 6481}, +/*h(2764)=505 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2764, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1168)=509 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1168, 6485}, +/*h(170)=510 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {170, 6481}, +/*h(2766)=511 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2766, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1170)=515 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1170, 6485}, +/*h(172)=516 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {172, 6480}, +/*h(2768)=517 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2768, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1172)=521 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1172, 6484}, +/*h(174)=522 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {174, 6480}, +/*h(2770)=523 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2770, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1174)=527 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1174, 6484}, +/*h(176)=528 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {176, 6481}, +/*h(2772)=529 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2772, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1176)=533 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1176, 6485}, +/*h(178)=534 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {178, 6481}, +/*h(2774)=535 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2774, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2176)=538 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2176, 6481}, +/*h(1178)=539 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1178, 6485}, +/*h(180)=540 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {180, 6480}, +/*h(2776)=541 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2776, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2178)=544 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2178, 6481}, +/*h(1180)=545 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1180, 6484}, +/*h(182)=546 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {182, 6480}, +/*h(2778)=547 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2778, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2180)=550 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2180, 6480}, +/*h(1182)=551 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1182, 6484}, +/*h(184)=552 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {184, 6481}, +/*h(2780)=553 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2780, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2182)=556 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2182, 6480}, +/*h(1184)=557 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1184, 6485}, +/*h(186)=558 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {186, 6481}, +/*h(2782)=559 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2782, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2184)=562 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2184, 6481}, +/*h(1186)=563 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1186, 6485}, +/*h(188)=564 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {188, 6480}, +/*h(2784)=565 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2784, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2186)=568 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2186, 6481}, +/*h(1188)=569 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1188, 6484}, +/*h(190)=570 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {190, 6480}, +/*h(2786)=571 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2786, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2188)=574 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2188, 6480}, +/*h(1190)=575 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1190, 6484}, +/*h(192)=576 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {192, 6481}, +/*h(2788)=577 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2788, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2190)=580 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2190, 6480}, +/*h(1192)=581 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1192, 6485}, +/*h(194)=582 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {194, 6481}, +/*h(2790)=583 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2790, 6482}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2192)=586 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2192, 6481}, +/*h(1194)=587 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {1194, 6485}, +/*h(196)=588 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {196, 6480}, +/*h(2792)=589 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2792, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2194)=592 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2194, 6481}, +/*h(1196)=593 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1196, 6484}, +/*h(198)=594 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {198, 6480}, +/*h(2794)=595 EVV 0x38 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {2794, 6483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2196)=598 EVV 0x38 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2196, 6480} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 599); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1156)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1156, 5356}, +/*h(2753)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2753, 5361}, +/*h(169)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {169, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1230)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1230, 5362}, +/*h(2217)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2217, 5365}, +/*h(3204)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3204, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1220)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(684)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {684, 5366}, +/*h(3268)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3268, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2785)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2785, 5361}, +/*h(201)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {201, 5365}, +/*h(1188)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1188, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3236)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3236, 5356}, +/*h(652)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {652, 5366}, +/*h(2249)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2249, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1252)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3300)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3300, 5356}, +/*h(716)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {716, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(185)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {185, 5365}, +/*h(1172)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1172, 5356}, +/*h(2769)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2769, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3220)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3220, 5356}, +/*h(1246)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1246, 5362}, +/*h(2233)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2233, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3210)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3210, 5363}, +/*h(1236)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1236, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3284)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2801)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2801, 5361}, +/*h(217)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {217, 5365}, +/*h(1204)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1204, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2265)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2265, 5365}, +/*h(668)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {668, 5366}, +/*h(3252)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3252, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1268)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(732)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {732, 5366}, +/*h(3316)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3316, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2755)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2755, 5361}, +/*h(171)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {171, 5365}, +/*h(1158)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1158, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3206)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3206, 5356}, +/*h(2219)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2219, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1222)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1222, 5356}, +/*h(235)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {235, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3270)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3270, 5356}, +/*h(686)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {686, 5366}, +/*h(2283)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2283, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1190)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1190, 5356}, +/*h(2177)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2177, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3238)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1254)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1254, 5356}, +/*h(644)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {644, 5360}, +/*h(2241)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2241, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2692)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2692, 5360}, +/*h(3302)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3302, 5356}, +/*h(718)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {718, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1174)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3222)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2225)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2225, 5359}, +/*h(251)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {251, 5365}, +/*h(1238)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1238, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3286)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3286, 5356}, +/*h(702)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {702, 5366}, +/*h(2299)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2299, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1206)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1206, 5356}, +/*h(2803)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2803, 5361}, +/*h(219)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {219, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(670)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {670, 5366}, +/*h(2267)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2267, 5365}, +/*h(3254)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3254, 5356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(660)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {660, 5360}, +/*h(1270)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {1270, 5356}, +/*h(3244)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3244, 5362}, +/*h(2257)=3 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2257, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2708)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2708, 5360}, +/*h(3318)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {3318, 5356}, +/*h(734)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {734, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_567_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1152)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1152; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3200)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1216)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3264)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3264, 5357}, +/*h(680)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {680, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1184)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(648)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {648, 5367}, +/*h(3232)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3232, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1248)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1248, 5357}, +/*h(2235)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2235, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3296)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3296, 5357}, +/*h(712)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {712, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1168)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1168; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3216)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1232)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1232; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(696)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {696, 5367}, +/*h(3280)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3280, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1200)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1200, 5357}, +/*h(2187)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2187, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3248)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3248, 5357}, +/*h(664)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {664, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2251)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2251, 5365}, +/*h(1264)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1264, 5357}, +/*h(654)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {654, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((11*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2702)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2702, 5366}, +/*h(3312)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3312, 5357}, +/*h(728)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {728, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1154)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3202)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1218)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3266)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3266, 5357}, +/*h(682)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {682, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1186)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3234)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3234, 5357}, +/*h(650)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {650, 5367}, +/*h(1260)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1260, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1250)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1250, 5357}, +/*h(3224)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3224, 5363}, +/*h(640)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {640, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3298)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3298, 5357}, +/*h(714)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {714, 5367}, +/*h(2688)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2688, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1170)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3218)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3218, 5357}, +/*h(1244)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1244, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3208)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3208, 5363}, +/*h(1234)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1234, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3282)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3282, 5357}, +/*h(698)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {698, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1202)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_355_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3250)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3250, 5357}, +/*h(1276)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1276, 5362}, +/*h(666)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {666, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(656)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {656, 5361}, +/*h(1266)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1266, 5357}, +/*h(3240)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3240, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3314)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3314, 5357}, +/*h(730)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {730, 5367}, +/*h(2704)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2704, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2750)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2750, 5366}, +/*h(166)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {166, 5358}, +/*h(1153)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1153, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(240)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {240, 5359}, +/*h(1227)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1227, 5363}, +/*h(2214)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2214, 5358}, +/*h(3201)=3 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3201, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2204)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2204, 5364}, +/*h(2814)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2814, 5366}, +/*h(1217)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1217, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3265)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3265, 5357}, +/*h(681)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {681, 5367}, +/*h(2278)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2278, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(198)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {198, 5358}, +/*h(1185)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1185, 5357}, +/*h(2782)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2782, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(649)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {649, 5367}, +/*h(1259)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1259, 5363}, +/*h(3233)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3233, 5357}, +/*h(2246)=3 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2246, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1249)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3297)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3297; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2766)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2766, 5366}, +/*h(182)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {182, 5358}, +/*h(1169)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1169, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1243)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1243, 5363}, +/*h(3217)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3217, 5357}, +/*h(2230)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2230, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2220)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2220, 5364}, +/*h(1233)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1233, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3281)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3281, 5357}, +/*h(697)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {697, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1201)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1201, 5357}, +/*h(2798)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2798, 5366}, +/*h(214)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {214, 5358}, +/*h(2188)=3 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2188, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_577_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(665)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {665, 5367}, +/*h(2262)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2262, 5358}, +/*h(3249)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3249, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1265)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1265; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(729)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {729, 5367}, +/*h(3313)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3313, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_482_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1155)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1155, 5357}, +/*h(168)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {168, 5365}, +/*h(2752)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2752, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2216)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2216, 5365}, +/*h(3203)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3203, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(232)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {232, 5365}, +/*h(1219)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1219, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3267)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3267, 5357}, +/*h(2280)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2280, 5365}, +/*h(683)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {683, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1187)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1187; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(651)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {651, 5367}, +/*h(3235)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3235, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2238)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2238, 5364}, +/*h(1251)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1251, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_520_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3299)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3299, 5357}, +/*h(715)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {715, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2768)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2768, 5361}, +/*h(1171)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1171, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2232)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2232, 5365}, +/*h(3219)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3219, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2222)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2222, 5364}, +/*h(1235)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1235, 5357}, +/*h(248)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {248, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2296)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2296, 5365}, +/*h(3283)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3283, 5357}, +/*h(699)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {699, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2800)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2800, 5361}, +/*h(216)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {216, 5365}, +/*h(1203)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1203, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3251)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2254)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2254, 5364}, +/*h(3241)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3241, 5363}, +/*h(657)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {657, 5361}, +/*h(1267)=3 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1267, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((12*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(731)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {731, 5367}, +/*h(2705)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2705, 5361}, +/*h(3315)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {3315, 5357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(132)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {132, 5358}, +/*h(2716)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2716, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2180)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2180; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2780)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2780, 5366}, +/*h(196)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {196, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2244)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2244, 5358}, +/*h(1257)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1257, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2748)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2748, 5366}, +/*h(164)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {164, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(238)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {238, 5364}, +/*h(2212)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2212, 5358}, +/*h(1225)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1225, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_530_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2202)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2202, 5365}, +/*h(2812)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2812, 5366}, +/*h(228)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {228, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2276)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2276; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2732)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2732, 5366}, +/*h(148)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {148, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2196)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2196; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2796)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2796, 5366}, +/*h(212)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {212, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2260)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2260, 5358}, +/*h(1273)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1273, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(180)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {180, 5358}, +/*h(2764)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2764, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_570_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1241)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1241, 5363}, +/*h(2228)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2228, 5358}, +/*h(254)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {254, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_465_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2218)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2218, 5365}, +/*h(244)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {244, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2292)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2292; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(744)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {744, 5367}, +/*h(2718)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2718, 5366}, +/*h(134)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {134, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1195)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1195, 5363}, +/*h(208)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {208, 5359}, +/*h(2792)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2792, 5367}, +/*h(2182)=3 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2182, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((10*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(230)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(150)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {150, 5358}, +/*h(760)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {760, 5367}, +/*h(2734)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {2734, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2808)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2808, 5367}, +/*h(224)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {224, 5359}, +/*h(1211)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1211, 5363}, +/*h(2198)=3 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2198, 5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(246)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2294)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {5358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(738)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {738, 5361}, +/*h(3322)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3322, 5363}, +/*h(128)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {128, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2786)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2786, 5361}, +/*h(202)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {202, 5365}, +/*h(2176)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2176, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_385_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2776)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2776, 5367}, +/*h(192)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {192, 5359}, +/*h(1179)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1179, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3227)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3227, 5363}, +/*h(643)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {643, 5361}, +/*h(2240)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2240, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2744)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2744, 5367}, +/*h(160)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {160, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2208)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2208, 5359}, +/*h(234)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {234, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(675)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {675, 5361}, +/*h(2272)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2272, 5359}, +/*h(3259)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3259, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2728)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2728, 5367}, +/*h(144)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {144, 5359}, +/*h(754)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {754, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2802)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2802, 5361}, +/*h(218)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {218, 5365}, +/*h(2192)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2192, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2256)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2256, 5359}, +/*h(3243)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3243, 5363}, +/*h(659)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {659, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_450_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2760)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2760, 5367}, +/*h(176)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {176, 5359}, +/*h(1163)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1163, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(250)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {250, 5365}, +/*h(2224)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2224, 5359}, +/*h(3211)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3211, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3275)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3275, 5363}, +/*h(691)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {691, 5361}, +/*h(2288)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2288, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3324)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3324, 5362}, +/*h(740)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {740, 5360}, +/*h(2714)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2714, 5367}, +/*h(130)=3 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {130, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2178)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2178, 5359}, +/*h(2788)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2788, 5360}, +/*h(204)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {204, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2778)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2778, 5367}, +/*h(194)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {194, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2242)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(162)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {162, 5359}, +/*h(2746)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2746, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2210)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2810)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2810, 5367}, +/*h(226)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {226, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2274)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2730)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2730, 5367}, +/*h(146)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {146, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2804)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2804, 5360}, +/*h(2194)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2194, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(210)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {210, 5359}, +/*h(2794)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2794, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2258)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2762)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2762, 5367}, +/*h(178)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {178, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2226)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2290)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2290; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(129)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {129, 5359}, +/*h(2713)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2713, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2777)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2777, 5367}, +/*h(1180)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1180, 5362}, +/*h(193)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {193, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(161)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 161; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2209)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(225)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {225, 5359}, +/*h(1212)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1212, 5362}, +/*h(2809)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2809, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3260)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3260, 5362}, +/*h(676)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {676, 5360}, +/*h(2273)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2273, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2729)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2729, 5367}, +/*h(145)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {145, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2193)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2193; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1196)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1196, 5362}, +/*h(2793)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2793, 5367}, +/*h(209)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {209, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(177)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {177, 5359}, +/*h(2761)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2761, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_550_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1228)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1228, 5362}, +/*h(241)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {241, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3276)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3276, 5362}, +/*h(692)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {692, 5360}, +/*h(2289)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2289, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2715)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2715, 5367}, +/*h(131)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {131, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1192)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1192, 5363}, +/*h(2179)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2179, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(195)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {195, 5359}, +/*h(1182)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1182, 5362}, +/*h(2779)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2779, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(646)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {646, 5360}, +/*h(1256)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1256, 5363}, +/*h(2243)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2243, 5359}, +/*h(3230)=3 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3230, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((12*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2747)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2747, 5367}, +/*h(163)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {163, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1224)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1224, 5363}, +/*h(2211)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2211, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(227)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {227, 5359}, +/*h(2201)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2201, 5365}, +/*h(2811)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2811, 5367}, +/*h(1214)=3 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1214, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2275)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2275, 5359}, +/*h(678)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {678, 5360}, +/*h(3262)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3262, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(147)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {147, 5359}, +/*h(2731)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2731, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1208)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1208, 5363}, +/*h(2195)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2195, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2185)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2185, 5365}, +/*h(2795)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2795, 5367}, +/*h(1198)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1198, 5362}, +/*h(211)=3 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {211, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3246)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3246, 5362}, +/*h(662)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {662, 5360}, +/*h(2259)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2259, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_365_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1166)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {1166, 5362}, +/*h(2763)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2763, 5367}, +/*h(179)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {179, 5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1240)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1240, 5363}, +/*h(2227)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2227, 5359}, +/*h(3214)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3214, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(243)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2291)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2291; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(708)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {708, 5360}, +/*h(3292)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3292, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2756)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2756, 5360}, +/*h(172)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {172, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(750)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {750, 5366}, +/*h(2724)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2724, 5360}, +/*h(140)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {140, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3308)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3308, 5362}, +/*h(724)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {724, 5360}, +/*h(2698)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2698, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2772)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2772, 5360}, +/*h(188)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {188, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(766)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {766, 5366}, +/*h(2740)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2740, 5360}, +/*h(156)=2 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {156, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(756)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {5360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 756; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(720)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {720, 5361}, +/*h(2694)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2694, 5360}, +/*h(3304)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3304, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(710)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {5360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2758)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2758, 5360}, +/*h(1161)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1161, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2726)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2726, 5360}, +/*h(142)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {142, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3326)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3326, 5362}, +/*h(742)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {742, 5360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2790)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2790, 5360}, +/*h(206)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {206, 5364}, +/*h(1193)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1193, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_507_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3320)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3320, 5363}, +/*h(2710)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2710, 5360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(726)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {726, 5360}, +/*h(3310)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3310, 5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_248_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2774)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2774, 5360}, +/*h(190)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {190, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3278)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {3278, 5362}, +/*h(694)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {694, 5360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2742)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2742, 5360}, +/*h(158)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {158, 5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(758)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {5360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2806)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {2806, 5360}, +/*h(222)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {222, 5364}, +/*h(1209)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {1209, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3288)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3288, 5363}, +/*h(704)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {704, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(672)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {672, 5361}, +/*h(3256)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3256, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2720)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2720, 5361}, +/*h(136)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {136, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2784)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2784, 5361}, +/*h(200)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {200, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3272)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3272, 5363}, +/*h(688)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {688, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_547_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2736)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2736, 5361}, +/*h(152)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {152, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(642)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {642, 5361}, +/*h(3226)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3226, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2690)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3290)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3290, 5363}, +/*h(706)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {706, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2754)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2754, 5361}, +/*h(170)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {170, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3258)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3258, 5363}, +/*h(674)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {674, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2722)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3242)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3242, 5363}, +/*h(658)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {658, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2706)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3306)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3306, 5363}, +/*h(722)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {722, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_555_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(186)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {186, 5365}, +/*h(2770)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2770, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(690)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(154)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {154, 5365}, +/*h(764)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {764, 5366}, +/*h(2738)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2738, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3225)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3225, 5363}, +/*h(641)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {641, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2689)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2689; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(705)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {705, 5361}, +/*h(2302)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2302, 5364}, +/*h(3289)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3289, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2270)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2270, 5364}, +/*h(673)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {673, 5361}, +/*h(3257)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3257, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(137)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {137, 5365}, +/*h(747)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {747, 5367}, +/*h(2721)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2721, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3321)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3321, 5363}, +/*h(737)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {737, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_350_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3305)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3305, 5363}, +/*h(721)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {721, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2286)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {2286, 5364}, +/*h(3273)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3273, 5363}, +/*h(689)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {689, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2737)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2737, 5361}, +/*h(153)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {153, 5365}, +/*h(763)=2 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {763, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(753)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2691)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3291)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3291, 5363}, +/*h(707)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {707, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2723)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2723, 5361}, +/*h(139)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {139, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3323)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3323, 5363}, +/*h(739)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {739, 5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2787)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2787, 5361}, +/*h(203)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {203, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2707)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(723)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 723; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_333_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2771)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2771, 5361}, +/*h(187)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {187, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2739)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {2739, 5361}, +/*h(155)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {155, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {5361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1164)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1164; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3212)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3212; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3228)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3228; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1262)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1262; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3294)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3294; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1278)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {5362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1160)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1160; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1176)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1176; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1272)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1272; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1162)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1226)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3274)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1194)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1258)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1258; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1178)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1242)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1210)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1274)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3209)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3209; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1177)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1177; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2697)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2697, 5367}, +/*h(3307)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {3307, 5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1275)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1275; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2252)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(236)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2284)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2284; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_563_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(220)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 220; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2268)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2268; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2236)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2236; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(252)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 252; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2300)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2300; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2190)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(174)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2206)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {5364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2184)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2248)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2200)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2264)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2264, 5365}, +/*h(667)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {667, 5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(184)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 184; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(138)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {138, 5365}, +/*h(748)=1 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {748, 5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2186)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2250)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2282)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2266)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2234)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2298)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(233)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 233; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2281)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(249)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 249; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(700)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {700, 5366}, +/*h(2297)=1 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {2297, 5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2203)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5365} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2700)=0 EVV 0x39 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {5366} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2700; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2696)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2696; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2712)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(762)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(713)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(745)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2745)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2745; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(761)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2699)=0 EVV 0x39 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {5367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2699; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(438)=0 EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0*/ {6507} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(950)=0 EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0*/ {6508} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1462)=0 EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0*/ {6509} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(446)=0 EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {6522} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(958)=0 EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 MASK=0*/ {6523} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1470)=0 EVV 0x39 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 MASK=0*/ {6524} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x39_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[582] = { +/*h(1220)=0 */ {1220, xed3_phash_find_mapevex_map2_opcode0x39_vv2_0_l1}, +/*h(233)=1 */ {233, xed3_phash_find_mapevex_map2_opcode0x39_vv2_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(699)=3 */ {699, xed3_phash_find_mapevex_map2_opcode0x39_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2762)=5 */ {2762, xed3_phash_find_mapevex_map2_opcode0x39_vv2_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3228)=7 */ {3228, xed3_phash_find_mapevex_map2_opcode0x39_vv2_7_l1}, +/*h(644)=8 */ {644, xed3_phash_find_mapevex_map2_opcode0x39_vv2_8_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2707)=10 */ {2707, xed3_phash_find_mapevex_map2_opcode0x39_vv2_10_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2186)=12 */ {2186, xed3_phash_find_mapevex_map2_opcode0x39_vv2_12_l1}, +/*h(2796)=13 */ {2796, xed3_phash_find_mapevex_map2_opcode0x39_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3262)=15 */ {3262, xed3_phash_find_mapevex_map2_opcode0x39_vv2_15_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2220)=20 */ {2220, xed3_phash_find_mapevex_map2_opcode0x39_vv2_20_l1}, +/*h(246)=21 */ {246, xed3_phash_find_mapevex_map2_opcode0x39_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(712)=23 */ {712, xed3_phash_find_mapevex_map2_opcode0x39_vv2_23_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1178)=25 */ {1178, xed3_phash_find_mapevex_map2_opcode0x39_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2254)=28 */ {2254, xed3_phash_find_mapevex_map2_opcode0x39_vv2_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(136)=30 */ {136, xed3_phash_find_mapevex_map2_opcode0x39_vv2_30_l1}, +/*h(746)=31 */ {746, xed3_phash_find_mapevex_map2_opcode0x39_vv2_31_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2809)=33 */ {2809, xed3_phash_find_mapevex_map2_opcode0x39_vv2_33_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3275)=35 */ {3275, xed3_phash_find_mapevex_map2_opcode0x39_vv2_35_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(170)=38 */ {170, xed3_phash_find_mapevex_map2_opcode0x39_vv2_38_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2233)=40 */ {2233, xed3_phash_find_mapevex_map2_opcode0x39_vv2_40_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2699)=42 */ {2699, xed3_phash_find_mapevex_map2_opcode0x39_vv2_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(958)=44 */ {958, xed3_phash_find_mapevex_map2_opcode0x39_vv2_44_l1}, +/*h(204)=45 */ {204, xed3_phash_find_mapevex_map2_opcode0x39_vv2_45_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(670)=48 */ {670, xed3_phash_find_mapevex_map2_opcode0x39_vv2_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(238)=53 */ {238, xed3_phash_find_mapevex_map2_opcode0x39_vv2_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3288)=55 */ {3288, xed3_phash_find_mapevex_map2_opcode0x39_vv2_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1170)=58 */ {1170, xed3_phash_find_mapevex_map2_opcode0x39_vv2_58_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(649)=60 */ {649, xed3_phash_find_mapevex_map2_opcode0x39_vv2_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2712)=62 */ {2712, xed3_phash_find_mapevex_map2_opcode0x39_vv2_62_l1}, +/*h(3322)=63 */ {3322, xed3_phash_find_mapevex_map2_opcode0x39_vv2_63_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(217)=65 */ {217, xed3_phash_find_mapevex_map2_opcode0x39_vv2_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(683)=68 */ {683, xed3_phash_find_mapevex_map2_opcode0x39_vv2_68_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2746)=70 */ {2746, xed3_phash_find_mapevex_map2_opcode0x39_vv2_70_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3212)=72 */ {3212, xed3_phash_find_mapevex_map2_opcode0x39_vv2_72_l1}, +/*h(251)=73 */ {251, xed3_phash_find_mapevex_map2_opcode0x39_vv2_73_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2691)=75 */ {2691, xed3_phash_find_mapevex_map2_opcode0x39_vv2_75_l1}, +/*h(950)=76 */ {950, xed3_phash_find_mapevex_map2_opcode0x39_vv2_76_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2780)=78 */ {2780, xed3_phash_find_mapevex_map2_opcode0x39_vv2_78_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3246)=80 */ {3246, xed3_phash_find_mapevex_map2_opcode0x39_vv2_80_l1}, +/*h(1272)=81 */ {1272, xed3_phash_find_mapevex_map2_opcode0x39_vv2_81_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2814)=85 */ {2814, xed3_phash_find_mapevex_map2_opcode0x39_vv2_85_l1}, +/*h(230)=86 */ {230, xed3_phash_find_mapevex_map2_opcode0x39_vv2_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(696)=88 */ {696, xed3_phash_find_mapevex_map2_opcode0x39_vv2_88_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1162)=90 */ {1162, xed3_phash_find_mapevex_map2_opcode0x39_vv2_90_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3225)=92 */ {3225, xed3_phash_find_mapevex_map2_opcode0x39_vv2_92_l1}, +/*h(2238)=93 */ {2238, xed3_phash_find_mapevex_map2_opcode0x39_vv2_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(730)=95 */ {730, xed3_phash_find_mapevex_map2_opcode0x39_vv2_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2793)=98 */ {2793, xed3_phash_find_mapevex_map2_opcode0x39_vv2_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3259)=100 */ {3259, xed3_phash_find_mapevex_map2_opcode0x39_vv2_100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(764)=103 */ {764, xed3_phash_find_mapevex_map2_opcode0x39_vv2_103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2217)=105 */ {2217, xed3_phash_find_mapevex_map2_opcode0x39_vv2_105_l1}, +/*h(243)=106 */ {243, xed3_phash_find_mapevex_map2_opcode0x39_vv2_106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(188)=110 */ {188, xed3_phash_find_mapevex_map2_opcode0x39_vv2_110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3238)=112 */ {3238, xed3_phash_find_mapevex_map2_opcode0x39_vv2_112_l1}, +/*h(654)=113 */ {654, xed3_phash_find_mapevex_map2_opcode0x39_vv2_113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2196)=117 */ {2196, xed3_phash_find_mapevex_map2_opcode0x39_vv2_117_l1}, +/*h(222)=118 */ {222, xed3_phash_find_mapevex_map2_opcode0x39_vv2_118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3272)=120 */ {3272, xed3_phash_find_mapevex_map2_opcode0x39_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1154)=122 */ {1154, xed3_phash_find_mapevex_map2_opcode0x39_vv2_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1243)=125 */ {1243, xed3_phash_find_mapevex_map2_opcode0x39_vv2_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2696)=127 */ {2696, xed3_phash_find_mapevex_map2_opcode0x39_vv2_127_l1}, +/*h(3306)=128 */ {3306, xed3_phash_find_mapevex_map2_opcode0x39_vv2_128_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(201)=130 */ {201, xed3_phash_find_mapevex_map2_opcode0x39_vv2_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3251)=132 */ {3251, xed3_phash_find_mapevex_map2_opcode0x39_vv2_132_l1}, +/*h(667)=133 */ {667, xed3_phash_find_mapevex_map2_opcode0x39_vv2_133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2730)=135 */ {2730, xed3_phash_find_mapevex_map2_opcode0x39_vv2_135_l1}, +/*h(756)=136 */ {756, xed3_phash_find_mapevex_map2_opcode0x39_vv2_136_l1}, +/*h(2209)=137 */ {2209, xed3_phash_find_mapevex_map2_opcode0x39_vv2_137_l1}, +/*h(235)=138 */ {235, xed3_phash_find_mapevex_map2_opcode0x39_vv2_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2298)=140 */ {2298, xed3_phash_find_mapevex_map2_opcode0x39_vv2_140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2764)=143 */ {2764, xed3_phash_find_mapevex_map2_opcode0x39_vv2_143_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1256)=145 */ {1256, xed3_phash_find_mapevex_map2_opcode0x39_vv2_145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2798)=150 */ {2798, xed3_phash_find_mapevex_map2_opcode0x39_vv2_150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(680)=153 */ {680, xed3_phash_find_mapevex_map2_opcode0x39_vv2_153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3209)=157 */ {3209, xed3_phash_find_mapevex_map2_opcode0x39_vv2_157_l1}, +/*h(248)=158 */ {248, xed3_phash_find_mapevex_map2_opcode0x39_vv2_158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(714)=160 */ {714, xed3_phash_find_mapevex_map2_opcode0x39_vv2_160_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2777)=163 */ {2777, xed3_phash_find_mapevex_map2_opcode0x39_vv2_163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3243)=165 */ {3243, xed3_phash_find_mapevex_map2_opcode0x39_vv2_165_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2722)=167 */ {2722, xed3_phash_find_mapevex_map2_opcode0x39_vv2_167_l1}, +/*h(748)=168 */ {748, xed3_phash_find_mapevex_map2_opcode0x39_vv2_168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2811)=170 */ {2811, xed3_phash_find_mapevex_map2_opcode0x39_vv2_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2290)=173 */ {2290, xed3_phash_find_mapevex_map2_opcode0x39_vv2_173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(172)=175 */ {172, xed3_phash_find_mapevex_map2_opcode0x39_vv2_175_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3222)=177 */ {3222, xed3_phash_find_mapevex_map2_opcode0x39_vv2_177_l1}, +/*h(2235)=178 */ {2235, xed3_phash_find_mapevex_map2_opcode0x39_vv2_178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2180)=182 */ {2180, xed3_phash_find_mapevex_map2_opcode0x39_vv2_182_l1}, +/*h(206)=183 */ {206, xed3_phash_find_mapevex_map2_opcode0x39_vv2_183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3256)=185 */ {3256, xed3_phash_find_mapevex_map2_opcode0x39_vv2_185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(761)=188 */ {761, xed3_phash_find_mapevex_map2_opcode0x39_vv2_188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1227)=190 */ {1227, xed3_phash_find_mapevex_map2_opcode0x39_vv2_190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3290)=193 */ {3290, xed3_phash_find_mapevex_map2_opcode0x39_vv2_193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(185)=195 */ {185, xed3_phash_find_mapevex_map2_opcode0x39_vv2_195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(651)=197 */ {651, xed3_phash_find_mapevex_map2_opcode0x39_vv2_197_l1}, +/*h(2248)=198 */ {2248, xed3_phash_find_mapevex_map2_opcode0x39_vv2_198_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2714)=200 */ {2714, xed3_phash_find_mapevex_map2_opcode0x39_vv2_200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2193)=202 */ {2193, xed3_phash_find_mapevex_map2_opcode0x39_vv2_202_l1}, +/*h(219)=203 */ {219, xed3_phash_find_mapevex_map2_opcode0x39_vv2_203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2282)=205 */ {2282, xed3_phash_find_mapevex_map2_opcode0x39_vv2_205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2748)=208 */ {2748, xed3_phash_find_mapevex_map2_opcode0x39_vv2_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1240)=210 */ {1240, xed3_phash_find_mapevex_map2_opcode0x39_vv2_210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2782)=215 */ {2782, xed3_phash_find_mapevex_map2_opcode0x39_vv2_215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(664)=217 */ {664, xed3_phash_find_mapevex_map2_opcode0x39_vv2_217_l1}, +/*h(1274)=218 */ {1274, xed3_phash_find_mapevex_map2_opcode0x39_vv2_218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(753)=220 */ {753, xed3_phash_find_mapevex_map2_opcode0x39_vv2_220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2206)=222 */ {2206, xed3_phash_find_mapevex_map2_opcode0x39_vv2_222_l1}, +/*h(232)=223 */ {232, xed3_phash_find_mapevex_map2_opcode0x39_vv2_223_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(698)=225 */ {698, xed3_phash_find_mapevex_map2_opcode0x39_vv2_225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1164)=227 */ {1164, xed3_phash_find_mapevex_map2_opcode0x39_vv2_227_l1}, +/*h(2761)=228 */ {2761, xed3_phash_find_mapevex_map2_opcode0x39_vv2_228_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3227)=230 */ {3227, xed3_phash_find_mapevex_map2_opcode0x39_vv2_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2706)=232 */ {2706, xed3_phash_find_mapevex_map2_opcode0x39_vv2_232_l1}, +/*h(732)=233 */ {732, xed3_phash_find_mapevex_map2_opcode0x39_vv2_233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2795)=235 */ {2795, xed3_phash_find_mapevex_map2_opcode0x39_vv2_235_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2274)=238 */ {2274, xed3_phash_find_mapevex_map2_opcode0x39_vv2_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(766)=240 */ {766, xed3_phash_find_mapevex_map2_opcode0x39_vv2_240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2219)=242 */ {2219, xed3_phash_find_mapevex_map2_opcode0x39_vv2_242_l1}, +/*h(1232)=243 */ {1232, xed3_phash_find_mapevex_map2_opcode0x39_vv2_243_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1177)=247 */ {1177, xed3_phash_find_mapevex_map2_opcode0x39_vv2_247_l1}, +/*h(190)=248 */ {190, xed3_phash_find_mapevex_map2_opcode0x39_vv2_248_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3240)=250 */ {3240, xed3_phash_find_mapevex_map2_opcode0x39_vv2_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(745)=253 */ {745, xed3_phash_find_mapevex_map2_opcode0x39_vv2_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2808)=255 */ {2808, xed3_phash_find_mapevex_map2_opcode0x39_vv2_255_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3274)=257 */ {3274, xed3_phash_find_mapevex_map2_opcode0x39_vv2_257_l1}, +/*h(690)=258 */ {690, xed3_phash_find_mapevex_map2_opcode0x39_vv2_258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(169)=260 */ {169, xed3_phash_find_mapevex_map2_opcode0x39_vv2_260_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2232)=262 */ {2232, xed3_phash_find_mapevex_map2_opcode0x39_vv2_262_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2698)=265 */ {2698, xed3_phash_find_mapevex_map2_opcode0x39_vv2_265_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2177)=267 */ {2177, xed3_phash_find_mapevex_map2_opcode0x39_vv2_267_l1}, +/*h(203)=268 */ {203, xed3_phash_find_mapevex_map2_opcode0x39_vv2_268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2266)=270 */ {2266, xed3_phash_find_mapevex_map2_opcode0x39_vv2_270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2732)=272 */ {2732, xed3_phash_find_mapevex_map2_opcode0x39_vv2_272_l1}, +/*h(758)=273 */ {758, xed3_phash_find_mapevex_map2_opcode0x39_vv2_273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1224)=275 */ {1224, xed3_phash_find_mapevex_map2_opcode0x39_vv2_275_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2300)=278 */ {2300, xed3_phash_find_mapevex_map2_opcode0x39_vv2_278_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2766)=280 */ {2766, xed3_phash_find_mapevex_map2_opcode0x39_vv2_280_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(648)=282 */ {648, xed3_phash_find_mapevex_map2_opcode0x39_vv2_282_l1}, +/*h(1258)=283 */ {1258, xed3_phash_find_mapevex_map2_opcode0x39_vv2_283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3321)=285 */ {3321, xed3_phash_find_mapevex_map2_opcode0x39_vv2_285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2190)=287 */ {2190, xed3_phash_find_mapevex_map2_opcode0x39_vv2_287_l1}, +/*h(216)=288 */ {216, xed3_phash_find_mapevex_map2_opcode0x39_vv2_288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(682)=290 */ {682, xed3_phash_find_mapevex_map2_opcode0x39_vv2_290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2745)=292 */ {2745, xed3_phash_find_mapevex_map2_opcode0x39_vv2_292_l1}, +/*h(161)=293 */ {161, xed3_phash_find_mapevex_map2_opcode0x39_vv2_293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(250)=295 */ {250, xed3_phash_find_mapevex_map2_opcode0x39_vv2_295_l1}, +/*h(1470)=296 */ {1470, xed3_phash_find_mapevex_map2_opcode0x39_vv2_296_l1}, +/*h(2690)=297 */ {2690, xed3_phash_find_mapevex_map2_opcode0x39_vv2_297_l1}, +/*h(716)=298 */ {716, xed3_phash_find_mapevex_map2_opcode0x39_vv2_298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2779)=300 */ {2779, xed3_phash_find_mapevex_map2_opcode0x39_vv2_300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2258)=303 */ {2258, xed3_phash_find_mapevex_map2_opcode0x39_vv2_303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(750)=305 */ {750, xed3_phash_find_mapevex_map2_opcode0x39_vv2_305_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2203)=307 */ {2203, xed3_phash_find_mapevex_map2_opcode0x39_vv2_307_l1}, +/*h(1216)=308 */ {1216, xed3_phash_find_mapevex_map2_opcode0x39_vv2_308_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2292)=310 */ {2292, xed3_phash_find_mapevex_map2_opcode0x39_vv2_310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1161)=312 */ {1161, xed3_phash_find_mapevex_map2_opcode0x39_vv2_312_l1}, +/*h(174)=313 */ {174, xed3_phash_find_mapevex_map2_opcode0x39_vv2_313_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3224)=315 */ {3224, xed3_phash_find_mapevex_map2_opcode0x39_vv2_315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(729)=318 */ {729, xed3_phash_find_mapevex_map2_opcode0x39_vv2_318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2792)=320 */ {2792, xed3_phash_find_mapevex_map2_opcode0x39_vv2_320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3258)=322 */ {3258, xed3_phash_find_mapevex_map2_opcode0x39_vv2_322_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(763)=325 */ {763, xed3_phash_find_mapevex_map2_opcode0x39_vv2_325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2216)=327 */ {2216, xed3_phash_find_mapevex_map2_opcode0x39_vv2_327_l1}, +/*h(242)=328 */ {242, xed3_phash_find_mapevex_map2_opcode0x39_vv2_328_l1}, +/*h(1462)=329 */ {1462, xed3_phash_find_mapevex_map2_opcode0x39_vv2_329_l1}, +/*h(3292)=330 */ {3292, xed3_phash_find_mapevex_map2_opcode0x39_vv2_330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1174)=332 */ {1174, xed3_phash_find_mapevex_map2_opcode0x39_vv2_332_l1}, +/*h(187)=333 */ {187, xed3_phash_find_mapevex_map2_opcode0x39_vv2_333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2250)=335 */ {2250, xed3_phash_find_mapevex_map2_opcode0x39_vv2_335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2716)=337 */ {2716, xed3_phash_find_mapevex_map2_opcode0x39_vv2_337_l1}, +/*h(3326)=338 */ {3326, xed3_phash_find_mapevex_map2_opcode0x39_vv2_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1208)=340 */ {1208, xed3_phash_find_mapevex_map2_opcode0x39_vv2_340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2284)=343 */ {2284, xed3_phash_find_mapevex_map2_opcode0x39_vv2_343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2750)=345 */ {2750, xed3_phash_find_mapevex_map2_opcode0x39_vv2_345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3216)=347 */ {3216, xed3_phash_find_mapevex_map2_opcode0x39_vv2_347_l1}, +/*h(1242)=348 */ {1242, xed3_phash_find_mapevex_map2_opcode0x39_vv2_348_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3305)=350 */ {3305, xed3_phash_find_mapevex_map2_opcode0x39_vv2_350_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1187)=352 */ {1187, xed3_phash_find_mapevex_map2_opcode0x39_vv2_352_l1}, +/*h(200)=353 */ {200, xed3_phash_find_mapevex_map2_opcode0x39_vv2_353_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(666)=355 */ {666, xed3_phash_find_mapevex_map2_opcode0x39_vv2_355_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2729)=357 */ {2729, xed3_phash_find_mapevex_map2_opcode0x39_vv2_357_l1}, +/*h(755)=358 */ {755, xed3_phash_find_mapevex_map2_opcode0x39_vv2_358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=360 */ {234, xed3_phash_find_mapevex_map2_opcode0x39_vv2_360_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3284)=362 */ {3284, xed3_phash_find_mapevex_map2_opcode0x39_vv2_362_l1}, +/*h(700)=363 */ {700, xed3_phash_find_mapevex_map2_opcode0x39_vv2_363_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2763)=365 */ {2763, xed3_phash_find_mapevex_map2_opcode0x39_vv2_365_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2242)=367 */ {2242, xed3_phash_find_mapevex_map2_opcode0x39_vv2_367_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(734)=370 */ {734, xed3_phash_find_mapevex_map2_opcode0x39_vv2_370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2187)=372 */ {2187, xed3_phash_find_mapevex_map2_opcode0x39_vv2_372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(446)=374 */ {446, xed3_phash_find_mapevex_map2_opcode0x39_vv2_374_l1}, +/*h(2276)=375 */ {2276, xed3_phash_find_mapevex_map2_opcode0x39_vv2_375_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(158)=377 */ {158, xed3_phash_find_mapevex_map2_opcode0x39_vv2_377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3208)=380 */ {3208, xed3_phash_find_mapevex_map2_opcode0x39_vv2_380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3297)=382 */ {3297, xed3_phash_find_mapevex_map2_opcode0x39_vv2_382_l1}, +/*h(713)=383 */ {713, xed3_phash_find_mapevex_map2_opcode0x39_vv2_383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2776)=385 */ {2776, xed3_phash_find_mapevex_map2_opcode0x39_vv2_385_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3242)=387 */ {3242, xed3_phash_find_mapevex_map2_opcode0x39_vv2_387_l1}, +/*h(1268)=388 */ {1268, xed3_phash_find_mapevex_map2_opcode0x39_vv2_388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(747)=390 */ {747, xed3_phash_find_mapevex_map2_opcode0x39_vv2_390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2200)=392 */ {2200, xed3_phash_find_mapevex_map2_opcode0x39_vv2_392_l1}, +/*h(2810)=393 */ {2810, xed3_phash_find_mapevex_map2_opcode0x39_vv2_393_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3276)=395 */ {3276, xed3_phash_find_mapevex_map2_opcode0x39_vv2_395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(171)=397 */ {171, xed3_phash_find_mapevex_map2_opcode0x39_vv2_397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2234)=400 */ {2234, xed3_phash_find_mapevex_map2_opcode0x39_vv2_400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2700)=402 */ {2700, xed3_phash_find_mapevex_map2_opcode0x39_vv2_402_l1}, +/*h(3310)=403 */ {3310, xed3_phash_find_mapevex_map2_opcode0x39_vv2_403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1192)=405 */ {1192, xed3_phash_find_mapevex_map2_opcode0x39_vv2_405_l1}, +/*h(438)=406 */ {438, xed3_phash_find_mapevex_map2_opcode0x39_vv2_406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2268)=408 */ {2268, xed3_phash_find_mapevex_map2_opcode0x39_vv2_408_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(760)=410 */ {760, xed3_phash_find_mapevex_map2_opcode0x39_vv2_410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3200)=412 */ {3200, xed3_phash_find_mapevex_map2_opcode0x39_vv2_412_l1}, +/*h(1226)=413 */ {1226, xed3_phash_find_mapevex_map2_opcode0x39_vv2_413_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2302)=415 */ {2302, xed3_phash_find_mapevex_map2_opcode0x39_vv2_415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2768)=417 */ {2768, xed3_phash_find_mapevex_map2_opcode0x39_vv2_417_l1}, +/*h(184)=418 */ {184, xed3_phash_find_mapevex_map2_opcode0x39_vv2_418_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(650)=420 */ {650, xed3_phash_find_mapevex_map2_opcode0x39_vv2_420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2713)=422 */ {2713, xed3_phash_find_mapevex_map2_opcode0x39_vv2_422_l1}, +/*h(3323)=423 */ {3323, xed3_phash_find_mapevex_map2_opcode0x39_vv2_423_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(218)=425 */ {218, xed3_phash_find_mapevex_map2_opcode0x39_vv2_425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(684)=427 */ {684, xed3_phash_find_mapevex_map2_opcode0x39_vv2_427_l1}, +/*h(2281)=428 */ {2281, xed3_phash_find_mapevex_map2_opcode0x39_vv2_428_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2747)=430 */ {2747, xed3_phash_find_mapevex_map2_opcode0x39_vv2_430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2226)=432 */ {2226, xed3_phash_find_mapevex_map2_opcode0x39_vv2_432_l1}, +/*h(252)=433 */ {252, xed3_phash_find_mapevex_map2_opcode0x39_vv2_433_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(718)=435 */ {718, xed3_phash_find_mapevex_map2_opcode0x39_vv2_435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1184)=437 */ {1184, xed3_phash_find_mapevex_map2_opcode0x39_vv2_437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1273)=440 */ {1273, xed3_phash_find_mapevex_map2_opcode0x39_vv2_440_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(142)=442 */ {142, xed3_phash_find_mapevex_map2_opcode0x39_vv2_442_l1}, +/*h(752)=443 */ {752, xed3_phash_find_mapevex_map2_opcode0x39_vv2_443_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1218)=445 */ {1218, xed3_phash_find_mapevex_map2_opcode0x39_vv2_445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(697)=447 */ {697, xed3_phash_find_mapevex_map2_opcode0x39_vv2_447_l1}, +/*h(2294)=448 */ {2294, xed3_phash_find_mapevex_map2_opcode0x39_vv2_448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2760)=450 */ {2760, xed3_phash_find_mapevex_map2_opcode0x39_vv2_450_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3226)=452 */ {3226, xed3_phash_find_mapevex_map2_opcode0x39_vv2_452_l1}, +/*h(1252)=453 */ {1252, xed3_phash_find_mapevex_map2_opcode0x39_vv2_453_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(731)=455 */ {731, xed3_phash_find_mapevex_map2_opcode0x39_vv2_455_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2184)=457 */ {2184, xed3_phash_find_mapevex_map2_opcode0x39_vv2_457_l1}, +/*h(2794)=458 */ {2794, xed3_phash_find_mapevex_map2_opcode0x39_vv2_458_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3260)=460 */ {3260, xed3_phash_find_mapevex_map2_opcode0x39_vv2_460_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(155)=462 */ {155, xed3_phash_find_mapevex_map2_opcode0x39_vv2_462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2218)=465 */ {2218, xed3_phash_find_mapevex_map2_opcode0x39_vv2_465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3294)=467 */ {3294, xed3_phash_find_mapevex_map2_opcode0x39_vv2_467_l1}, +/*h(710)=468 */ {710, xed3_phash_find_mapevex_map2_opcode0x39_vv2_468_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1176)=470 */ {1176, xed3_phash_find_mapevex_map2_opcode0x39_vv2_470_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2252)=472 */ {2252, xed3_phash_find_mapevex_map2_opcode0x39_vv2_472_l1}, +/*h(1265)=473 */ {1265, xed3_phash_find_mapevex_map2_opcode0x39_vv2_473_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(744)=475 */ {744, xed3_phash_find_mapevex_map2_opcode0x39_vv2_475_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1210)=477 */ {1210, xed3_phash_find_mapevex_map2_opcode0x39_vv2_477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2286)=480 */ {2286, xed3_phash_find_mapevex_map2_opcode0x39_vv2_480_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(168)=482 */ {168, xed3_phash_find_mapevex_map2_opcode0x39_vv2_482_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1244)=485 */ {1244, xed3_phash_find_mapevex_map2_opcode0x39_vv2_485_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2697)=487 */ {2697, xed3_phash_find_mapevex_map2_opcode0x39_vv2_487_l1}, +/*h(723)=488 */ {723, xed3_phash_find_mapevex_map2_opcode0x39_vv2_488_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(202)=490 */ {202, xed3_phash_find_mapevex_map2_opcode0x39_vv2_490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(668)=492 */ {668, xed3_phash_find_mapevex_map2_opcode0x39_vv2_492_l1}, +/*h(1278)=493 */ {1278, xed3_phash_find_mapevex_map2_opcode0x39_vv2_493_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2731)=495 */ {2731, xed3_phash_find_mapevex_map2_opcode0x39_vv2_495_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2210)=497 */ {2210, xed3_phash_find_mapevex_map2_opcode0x39_vv2_497_l1}, +/*h(236)=498 */ {236, xed3_phash_find_mapevex_map2_opcode0x39_vv2_498_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(702)=500 */ {702, xed3_phash_find_mapevex_map2_opcode0x39_vv2_500_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1168)=502 */ {1168, xed3_phash_find_mapevex_map2_opcode0x39_vv2_502_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1257)=505 */ {1257, xed3_phash_find_mapevex_map2_opcode0x39_vv2_505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3320)=507 */ {3320, xed3_phash_find_mapevex_map2_opcode0x39_vv2_507_l1}, +/*h(736)=508 */ {736, xed3_phash_find_mapevex_map2_opcode0x39_vv2_508_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1202)=510 */ {1202, xed3_phash_find_mapevex_map2_opcode0x39_vv2_510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(681)=512 */ {681, xed3_phash_find_mapevex_map2_opcode0x39_vv2_512_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2744)=515 */ {2744, xed3_phash_find_mapevex_map2_opcode0x39_vv2_515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3210)=517 */ {3210, xed3_phash_find_mapevex_map2_opcode0x39_vv2_517_l1}, +/*h(249)=518 */ {249, xed3_phash_find_mapevex_map2_opcode0x39_vv2_518_l1}, +/*h(2689)=519 */ {2689, xed3_phash_find_mapevex_map2_opcode0x39_vv2_519_l1}, +/*h(715)=520 */ {715, xed3_phash_find_mapevex_map2_opcode0x39_vv2_520_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2778)=522 */ {2778, xed3_phash_find_mapevex_map2_opcode0x39_vv2_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3244)=525 */ {3244, xed3_phash_find_mapevex_map2_opcode0x39_vv2_525_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(139)=527 */ {139, xed3_phash_find_mapevex_map2_opcode0x39_vv2_527_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2812)=530 */ {2812, xed3_phash_find_mapevex_map2_opcode0x39_vv2_530_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3278)=532 */ {3278, xed3_phash_find_mapevex_map2_opcode0x39_vv2_532_l1}, +/*h(2291)=533 */ {2291, xed3_phash_find_mapevex_map2_opcode0x39_vv2_533_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1160)=535 */ {1160, xed3_phash_find_mapevex_map2_opcode0x39_vv2_535_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2236)=537 */ {2236, xed3_phash_find_mapevex_map2_opcode0x39_vv2_537_l1}, +/*h(1249)=538 */ {1249, xed3_phash_find_mapevex_map2_opcode0x39_vv2_538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(728)=540 */ {728, xed3_phash_find_mapevex_map2_opcode0x39_vv2_540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1194)=542 */ {1194, xed3_phash_find_mapevex_map2_opcode0x39_vv2_542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2270)=545 */ {2270, xed3_phash_find_mapevex_map2_opcode0x39_vv2_545_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(152)=547 */ {152, xed3_phash_find_mapevex_map2_opcode0x39_vv2_547_l1}, +/*h(762)=548 */ {762, xed3_phash_find_mapevex_map2_opcode0x39_vv2_548_l1}, +/*h(3202)=549 */ {3202, xed3_phash_find_mapevex_map2_opcode0x39_vv2_549_l1}, +/*h(1228)=550 */ {1228, xed3_phash_find_mapevex_map2_opcode0x39_vv2_550_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3291)=552 */ {3291, xed3_phash_find_mapevex_map2_opcode0x39_vv2_552_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(186)=555 */ {186, xed3_phash_find_mapevex_map2_opcode0x39_vv2_555_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(652)=557 */ {652, xed3_phash_find_mapevex_map2_opcode0x39_vv2_557_l1}, +/*h(1262)=558 */ {1262, xed3_phash_find_mapevex_map2_opcode0x39_vv2_558_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2715)=560 */ {2715, xed3_phash_find_mapevex_map2_opcode0x39_vv2_560_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2804)=562 */ {2804, xed3_phash_find_mapevex_map2_opcode0x39_vv2_562_l1}, +/*h(220)=563 */ {220, xed3_phash_find_mapevex_map2_opcode0x39_vv2_563_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=565 */ {686, xed3_phash_find_mapevex_map2_opcode0x39_vv2_565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1152)=567 */ {1152, xed3_phash_find_mapevex_map2_opcode0x39_vv2_567_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(254)=570 */ {254, xed3_phash_find_mapevex_map2_opcode0x39_vv2_570_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3304)=572 */ {3304, xed3_phash_find_mapevex_map2_opcode0x39_vv2_572_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1186)=575 */ {1186, xed3_phash_find_mapevex_map2_opcode0x39_vv2_575_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(665)=577 */ {665, xed3_phash_find_mapevex_map2_opcode0x39_vv2_577_l1}, +/*h(1275)=578 */ {1275, xed3_phash_find_mapevex_map2_opcode0x39_vv2_578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2728)=580 */ {2728, xed3_phash_find_mapevex_map2_opcode0x39_vv2_580_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 582ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[599] = { +/*h(1198)=0 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1198, 6502}, +/*h(200)=1 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {200, 6499}, +/*h(2796)=2 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2796, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2198)=5 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2198, 6498}, +/*h(1200)=6 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1200, 6503}, +/*h(202)=7 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {202, 6499}, +/*h(2798)=8 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2798, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2200)=11 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2200, 6499}, +/*h(1202)=12 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1202, 6503}, +/*h(204)=13 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {204, 6498}, +/*h(2800)=14 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2800, 6501}, +/*empty slot1 */ {0,0}, +/*h(3200)=16 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3200, 6503}, +/*h(2202)=17 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2202, 6499}, +/*h(1204)=18 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1204, 6502}, +/*h(206)=19 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {206, 6498}, +/*h(2802)=20 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2802, 6501}, +/*empty slot1 */ {0,0}, +/*h(3202)=22 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3202, 6503}, +/*h(2204)=23 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2204, 6498}, +/*h(1206)=24 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1206, 6502}, +/*h(208)=25 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {208, 6499}, +/*h(2804)=26 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2804, 6500}, +/*empty slot1 */ {0,0}, +/*h(3204)=28 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3204, 6502}, +/*h(2206)=29 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2206, 6498}, +/*h(1208)=30 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1208, 6503}, +/*h(210)=31 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {210, 6499}, +/*h(2806)=32 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2806, 6500}, +/*empty slot1 */ {0,0}, +/*h(3206)=34 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3206, 6502}, +/*h(2208)=35 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2208, 6499}, +/*h(1210)=36 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1210, 6503}, +/*h(212)=37 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {212, 6498}, +/*h(2808)=38 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2808, 6501}, +/*empty slot1 */ {0,0}, +/*h(3208)=40 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3208, 6503}, +/*h(2210)=41 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2210, 6499}, +/*h(1212)=42 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1212, 6502}, +/*h(214)=43 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {214, 6498}, +/*h(2810)=44 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2810, 6501}, +/*empty slot1 */ {0,0}, +/*h(3210)=46 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3210, 6503}, +/*h(2212)=47 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2212, 6498}, +/*h(1214)=48 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1214, 6502}, +/*h(216)=49 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {216, 6499}, +/*h(2812)=50 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2812, 6500}, +/*empty slot1 */ {0,0}, +/*h(3212)=52 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3212, 6502}, +/*h(2214)=53 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2214, 6498}, +/*h(1216)=54 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1216, 6503}, +/*h(218)=55 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {218, 6499}, +/*h(2814)=56 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2814, 6500}, +/*empty slot1 */ {0,0}, +/*h(3214)=58 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3214, 6502}, +/*h(2216)=59 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2216, 6499}, +/*h(1218)=60 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1218, 6503}, +/*h(220)=61 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {220, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3216)=64 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3216, 6503}, +/*h(2218)=65 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2218, 6499}, +/*h(1220)=66 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1220, 6502}, +/*h(222)=67 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {222, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3218)=70 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3218, 6503}, +/*h(2220)=71 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2220, 6498}, +/*h(1222)=72 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1222, 6502}, +/*h(224)=73 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {224, 6499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3220)=76 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3220, 6502}, +/*h(2222)=77 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2222, 6498}, +/*h(1224)=78 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1224, 6503}, +/*h(226)=79 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {226, 6499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3222)=82 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3222, 6502}, +/*h(2224)=83 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2224, 6499}, +/*h(1226)=84 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1226, 6503}, +/*h(228)=85 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {228, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3224)=88 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3224, 6503}, +/*h(2226)=89 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2226, 6499}, +/*h(1228)=90 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1228, 6502}, +/*h(230)=91 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {230, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3226)=94 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3226, 6503}, +/*h(2228)=95 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2228, 6498}, +/*h(1230)=96 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1230, 6502}, +/*h(232)=97 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {232, 6499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3228)=100 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3228, 6502}, +/*h(2230)=101 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2230, 6498}, +/*h(1232)=102 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1232, 6503}, +/*h(234)=103 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {234, 6499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3230)=106 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3230, 6502}, +/*h(2232)=107 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2232, 6499}, +/*h(1234)=108 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1234, 6503}, +/*h(236)=109 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {236, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3232)=112 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3232, 6503}, +/*h(2234)=113 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2234, 6499}, +/*h(1236)=114 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1236, 6502}, +/*h(238)=115 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {238, 6498}, +/*h(438)=116 EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 MASK=0*/ {438, 6004}, +/*empty slot1 */ {0,0}, +/*h(3234)=118 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3234, 6503}, +/*h(2236)=119 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2236, 6498}, +/*h(1238)=120 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1238, 6502}, +/*h(240)=121 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {240, 6499}, +/*empty slot1 */ {0,0}, +/*h(640)=123 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {640, 6501}, +/*h(3236)=124 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3236, 6502}, +/*h(2238)=125 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2238, 6498}, +/*h(1240)=126 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1240, 6503}, +/*h(242)=127 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {242, 6499}, +/*empty slot1 */ {0,0}, +/*h(642)=129 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {642, 6501}, +/*h(3238)=130 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3238, 6502}, +/*h(2240)=131 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2240, 6499}, +/*h(1242)=132 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1242, 6503}, +/*h(244)=133 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {244, 6498}, +/*empty slot1 */ {0,0}, +/*h(644)=135 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {644, 6500}, +/*h(3240)=136 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3240, 6503}, +/*h(2242)=137 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2242, 6499}, +/*h(1244)=138 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1244, 6502}, +/*h(246)=139 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {246, 6498}, +/*empty slot1 */ {0,0}, +/*h(646)=141 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {646, 6500}, +/*h(3242)=142 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3242, 6503}, +/*h(2244)=143 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2244, 6498}, +/*h(1246)=144 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1246, 6502}, +/*h(248)=145 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {248, 6499}, +/*empty slot1 */ {0,0}, +/*h(648)=147 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {648, 6501}, +/*h(3244)=148 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3244, 6502}, +/*h(2246)=149 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2246, 6498}, +/*h(1248)=150 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1248, 6503}, +/*h(250)=151 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {250, 6499}, +/*empty slot1 */ {0,0}, +/*h(650)=153 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {650, 6501}, +/*h(3246)=154 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3246, 6502}, +/*h(2248)=155 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2248, 6499}, +/*h(1250)=156 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1250, 6503}, +/*h(252)=157 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {252, 6498}, +/*empty slot1 */ {0,0}, +/*h(652)=159 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {652, 6500}, +/*h(3248)=160 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3248, 6503}, +/*h(2250)=161 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2250, 6499}, +/*h(1252)=162 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1252, 6502}, +/*h(254)=163 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {254, 6498}, +/*empty slot1 */ {0,0}, +/*h(654)=165 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {654, 6500}, +/*h(3250)=166 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3250, 6503}, +/*h(2252)=167 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2252, 6498}, +/*h(1254)=168 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1254, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(656)=171 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {656, 6501}, +/*h(3252)=172 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3252, 6502}, +/*h(2254)=173 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2254, 6498}, +/*h(1256)=174 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1256, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(658)=177 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {658, 6501}, +/*h(3254)=178 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3254, 6502}, +/*h(2256)=179 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2256, 6499}, +/*h(1258)=180 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1258, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(660)=183 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {660, 6500}, +/*h(3256)=184 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3256, 6503}, +/*h(2258)=185 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2258, 6499}, +/*h(1260)=186 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1260, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(662)=189 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {662, 6500}, +/*h(3258)=190 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3258, 6503}, +/*h(2260)=191 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2260, 6498}, +/*h(1262)=192 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1262, 6502}, +/*h(1462)=193 EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 MASK=0*/ {1462, 6003}, +/*empty slot1 */ {0,0}, +/*h(664)=195 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {664, 6501}, +/*h(3260)=196 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3260, 6502}, +/*h(2262)=197 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2262, 6498}, +/*h(1264)=198 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1264, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(666)=201 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {666, 6501}, +/*h(3262)=202 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3262, 6502}, +/*h(2264)=203 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2264, 6499}, +/*h(1266)=204 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1266, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(668)=207 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {668, 6500}, +/*h(3264)=208 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3264, 6503}, +/*h(2266)=209 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2266, 6499}, +/*h(1268)=210 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1268, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(670)=213 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {670, 6500}, +/*h(3266)=214 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3266, 6503}, +/*h(2268)=215 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2268, 6498}, +/*h(1270)=216 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1270, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(672)=219 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {672, 6501}, +/*h(3268)=220 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3268, 6502}, +/*h(2270)=221 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2270, 6498}, +/*h(1272)=222 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1272, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(674)=225 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {674, 6501}, +/*h(3270)=226 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3270, 6502}, +/*h(2272)=227 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2272, 6499}, +/*h(1274)=228 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1274, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(676)=231 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {676, 6500}, +/*h(3272)=232 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3272, 6503}, +/*h(2274)=233 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2274, 6499}, +/*h(1276)=234 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1276, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(678)=237 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {678, 6500}, +/*h(3274)=238 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3274, 6503}, +/*h(2276)=239 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2276, 6498}, +/*h(1278)=240 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1278, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(680)=243 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {680, 6501}, +/*h(3276)=244 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3276, 6502}, +/*h(2278)=245 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2278, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(682)=249 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {682, 6501}, +/*h(3278)=250 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3278, 6502}, +/*h(2280)=251 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2280, 6499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(684)=255 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {684, 6500}, +/*h(3280)=256 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3280, 6503}, +/*h(2282)=257 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2282, 6499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(686)=261 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {686, 6500}, +/*h(3282)=262 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3282, 6503}, +/*h(2284)=263 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2284, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(688)=267 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {688, 6501}, +/*h(3284)=268 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3284, 6502}, +/*h(2286)=269 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2286, 6498}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(690)=273 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {690, 6501}, +/*h(3286)=274 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3286, 6502}, +/*h(2288)=275 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2288, 6499}, +/*empty slot1 */ {0,0}, +/*h(2688)=277 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2688, 6501}, +/*empty slot1 */ {0,0}, +/*h(692)=279 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {692, 6500}, +/*h(3288)=280 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3288, 6503}, +/*h(2290)=281 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2290, 6499}, +/*empty slot1 */ {0,0}, +/*h(2690)=283 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2690, 6501}, +/*empty slot1 */ {0,0}, +/*h(694)=285 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {694, 6500}, +/*h(3290)=286 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3290, 6503}, +/*h(2292)=287 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2292, 6498}, +/*empty slot1 */ {0,0}, +/*h(2692)=289 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2692, 6500}, +/*empty slot1 */ {0,0}, +/*h(696)=291 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {696, 6501}, +/*h(3292)=292 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3292, 6502}, +/*h(2294)=293 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2294, 6498}, +/*empty slot1 */ {0,0}, +/*h(2694)=295 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2694, 6500}, +/*empty slot1 */ {0,0}, +/*h(698)=297 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {698, 6501}, +/*h(3294)=298 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3294, 6502}, +/*h(2296)=299 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2296, 6499}, +/*empty slot1 */ {0,0}, +/*h(2696)=301 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2696, 6501}, +/*empty slot1 */ {0,0}, +/*h(700)=303 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {700, 6500}, +/*h(3296)=304 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3296, 6503}, +/*h(2298)=305 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2298, 6499}, +/*empty slot1 */ {0,0}, +/*h(2698)=307 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2698, 6501}, +/*empty slot1 */ {0,0}, +/*h(702)=309 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {702, 6500}, +/*h(3298)=310 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3298, 6503}, +/*h(2300)=311 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2300, 6498}, +/*empty slot1 */ {0,0}, +/*h(2700)=313 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2700, 6500}, +/*empty slot1 */ {0,0}, +/*h(704)=315 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {704, 6501}, +/*h(3300)=316 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3300, 6502}, +/*h(2302)=317 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2302, 6498}, +/*empty slot1 */ {0,0}, +/*h(2702)=319 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2702, 6500}, +/*empty slot1 */ {0,0}, +/*h(706)=321 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {706, 6501}, +/*h(3302)=322 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3302, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2704)=325 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2704, 6501}, +/*empty slot1 */ {0,0}, +/*h(708)=327 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {708, 6500}, +/*h(3304)=328 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3304, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2706)=331 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2706, 6501}, +/*empty slot1 */ {0,0}, +/*h(710)=333 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {710, 6500}, +/*h(3306)=334 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3306, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2708)=337 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2708, 6500}, +/*empty slot1 */ {0,0}, +/*h(712)=339 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {712, 6501}, +/*h(3308)=340 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3308, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2710)=343 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2710, 6500}, +/*empty slot1 */ {0,0}, +/*h(714)=345 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {714, 6501}, +/*h(3310)=346 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3310, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2712)=349 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2712, 6501}, +/*empty slot1 */ {0,0}, +/*h(716)=351 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {716, 6500}, +/*h(3312)=352 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3312, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2714)=355 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2714, 6501}, +/*empty slot1 */ {0,0}, +/*h(718)=357 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {718, 6500}, +/*h(3314)=358 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3314, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2716)=361 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2716, 6500}, +/*empty slot1 */ {0,0}, +/*h(720)=363 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {720, 6501}, +/*h(3316)=364 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3316, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2718)=367 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2718, 6500}, +/*empty slot1 */ {0,0}, +/*h(722)=369 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {722, 6501}, +/*h(3318)=370 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3318, 6502}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2720)=373 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2720, 6501}, +/*empty slot1 */ {0,0}, +/*h(724)=375 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {724, 6500}, +/*h(3320)=376 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3320, 6503}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2722)=379 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2722, 6501}, +/*empty slot1 */ {0,0}, +/*h(726)=381 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {726, 6500}, +/*h(3322)=382 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {3322, 6503}, +/*empty slot1 */ {0,0}, +/*h(128)=384 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {128, 6499}, +/*h(2724)=385 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2724, 6500}, +/*empty slot1 */ {0,0}, +/*h(728)=387 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {728, 6501}, +/*h(3324)=388 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3324, 6502}, +/*empty slot1 */ {0,0}, +/*h(130)=390 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {130, 6499}, +/*h(2726)=391 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2726, 6500}, +/*empty slot1 */ {0,0}, +/*h(730)=393 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {730, 6501}, +/*h(3326)=394 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {3326, 6502}, +/*empty slot1 */ {0,0}, +/*h(132)=396 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {132, 6498}, +/*h(2728)=397 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2728, 6501}, +/*empty slot1 */ {0,0}, +/*h(732)=399 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {732, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(134)=402 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {134, 6498}, +/*h(2730)=403 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2730, 6501}, +/*empty slot1 */ {0,0}, +/*h(734)=405 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {734, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(136)=408 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {136, 6499}, +/*h(2732)=409 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2732, 6500}, +/*empty slot1 */ {0,0}, +/*h(736)=411 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {736, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(138)=414 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {138, 6499}, +/*h(2734)=415 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2734, 6500}, +/*empty slot1 */ {0,0}, +/*h(738)=417 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {738, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(140)=420 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {140, 6498}, +/*h(2736)=421 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2736, 6501}, +/*empty slot1 */ {0,0}, +/*h(740)=423 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {740, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(142)=426 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {142, 6498}, +/*h(2738)=427 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2738, 6501}, +/*empty slot1 */ {0,0}, +/*h(742)=429 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {742, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(144)=432 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {144, 6499}, +/*h(2740)=433 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2740, 6500}, +/*empty slot1 */ {0,0}, +/*h(744)=435 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {744, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(146)=438 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {146, 6499}, +/*h(2742)=439 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2742, 6500}, +/*empty slot1 */ {0,0}, +/*h(746)=441 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {746, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(148)=444 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {148, 6498}, +/*h(2744)=445 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2744, 6501}, +/*empty slot1 */ {0,0}, +/*h(748)=447 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {748, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(150)=450 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {150, 6498}, +/*h(2746)=451 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2746, 6501}, +/*empty slot1 */ {0,0}, +/*h(750)=453 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {750, 6500}, +/*h(950)=454 EVV 0x3A VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 MASK=0*/ {950, 6005}, +/*empty slot1 */ {0,0}, +/*h(152)=456 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {152, 6499}, +/*h(2748)=457 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2748, 6500}, +/*empty slot1 */ {0,0}, +/*h(752)=459 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {752, 6501}, +/*empty slot1 */ {0,0}, +/*h(1152)=461 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1152, 6503}, +/*h(154)=462 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {154, 6499}, +/*h(2750)=463 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2750, 6500}, +/*empty slot1 */ {0,0}, +/*h(754)=465 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {754, 6501}, +/*empty slot1 */ {0,0}, +/*h(1154)=467 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1154, 6503}, +/*h(156)=468 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {156, 6498}, +/*h(2752)=469 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2752, 6501}, +/*empty slot1 */ {0,0}, +/*h(756)=471 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {756, 6500}, +/*empty slot1 */ {0,0}, +/*h(1156)=473 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1156, 6502}, +/*h(158)=474 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {158, 6498}, +/*h(2754)=475 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2754, 6501}, +/*empty slot1 */ {0,0}, +/*h(758)=477 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {758, 6500}, +/*empty slot1 */ {0,0}, +/*h(1158)=479 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1158, 6502}, +/*h(160)=480 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {160, 6499}, +/*h(2756)=481 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2756, 6500}, +/*empty slot1 */ {0,0}, +/*h(760)=483 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {760, 6501}, +/*empty slot1 */ {0,0}, +/*h(1160)=485 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1160, 6503}, +/*h(162)=486 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {162, 6499}, +/*h(2758)=487 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2758, 6500}, +/*empty slot1 */ {0,0}, +/*h(762)=489 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {762, 6501}, +/*empty slot1 */ {0,0}, +/*h(1162)=491 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1162, 6503}, +/*h(164)=492 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {164, 6498}, +/*h(2760)=493 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2760, 6501}, +/*empty slot1 */ {0,0}, +/*h(764)=495 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {764, 6500}, +/*empty slot1 */ {0,0}, +/*h(1164)=497 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1164, 6502}, +/*h(166)=498 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {166, 6498}, +/*h(2762)=499 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2762, 6501}, +/*empty slot1 */ {0,0}, +/*h(766)=501 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {766, 6500}, +/*empty slot1 */ {0,0}, +/*h(1166)=503 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1166, 6502}, +/*h(168)=504 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {168, 6499}, +/*h(2764)=505 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2764, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1168)=509 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1168, 6503}, +/*h(170)=510 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {170, 6499}, +/*h(2766)=511 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2766, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1170)=515 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1170, 6503}, +/*h(172)=516 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {172, 6498}, +/*h(2768)=517 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2768, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1172)=521 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1172, 6502}, +/*h(174)=522 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {174, 6498}, +/*h(2770)=523 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2770, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1174)=527 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1174, 6502}, +/*h(176)=528 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {176, 6499}, +/*h(2772)=529 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2772, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1176)=533 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1176, 6503}, +/*h(178)=534 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {178, 6499}, +/*h(2774)=535 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2774, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2176)=538 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2176, 6499}, +/*h(1178)=539 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1178, 6503}, +/*h(180)=540 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {180, 6498}, +/*h(2776)=541 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2776, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2178)=544 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2178, 6499}, +/*h(1180)=545 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1180, 6502}, +/*h(182)=546 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {182, 6498}, +/*h(2778)=547 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2778, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2180)=550 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2180, 6498}, +/*h(1182)=551 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1182, 6502}, +/*h(184)=552 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {184, 6499}, +/*h(2780)=553 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2780, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2182)=556 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2182, 6498}, +/*h(1184)=557 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1184, 6503}, +/*h(186)=558 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {186, 6499}, +/*h(2782)=559 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2782, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2184)=562 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2184, 6499}, +/*h(1186)=563 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1186, 6503}, +/*h(188)=564 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {188, 6498}, +/*h(2784)=565 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2784, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2186)=568 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2186, 6499}, +/*h(1188)=569 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1188, 6502}, +/*h(190)=570 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {190, 6498}, +/*h(2786)=571 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2786, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2188)=574 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2188, 6498}, +/*h(1190)=575 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1190, 6502}, +/*h(192)=576 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {192, 6499}, +/*h(2788)=577 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2788, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2190)=580 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2190, 6498}, +/*h(1192)=581 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1192, 6503}, +/*h(194)=582 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {194, 6499}, +/*h(2790)=583 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {2790, 6500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2192)=586 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2192, 6499}, +/*h(1194)=587 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {1194, 6503}, +/*h(196)=588 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {196, 6498}, +/*h(2792)=589 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2792, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2194)=592 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2194, 6499}, +/*h(1196)=593 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {1196, 6502}, +/*h(198)=594 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {198, 6498}, +/*h(2794)=595 EVV 0x3A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {2794, 6501}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2196)=598 EVV 0x3A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {2196, 6498} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 599); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5369}, +/*h(76)=1 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5375}, +/*h(8)=2 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5371}, +/*h(12)=3 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5377}, +/*h(41)=4 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5373}, +/*h(45)=5 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5379}, +/*h(74)=6 EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5368}, +/*h(78)=7 EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5374}, +/*h(10)=8 EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5370}, +/*h(14)=9 EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5376}, +/*h(40)=10 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5373}, +/*h(44)=11 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5379}, +/*h(73)=12 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5369}, +/*h(77)=13 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5375}, +/*h(9)=14 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5371}, +/*h(13)=15 EVV 0x3B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5377}, +/*h(42)=16 EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5372}, +/*h(46)=17 EVV 0x3B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5378} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6458}, +/*h(4)=1 EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6457}, +/*h(38)=2 EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6460}, +/*h(20)=3 EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6459}, +/*h(6)=4 EVV 0x3C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6456}, +/*h(36)=5 EVV 0x3C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6461} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5333}, +/*h(76)=1 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5339}, +/*h(8)=2 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5335}, +/*h(12)=3 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5341}, +/*h(41)=4 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5337}, +/*h(45)=5 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5343}, +/*h(74)=6 EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5332}, +/*h(78)=7 EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5338}, +/*h(10)=8 EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5334}, +/*h(14)=9 EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5340}, +/*h(40)=10 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5337}, +/*h(44)=11 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5343}, +/*h(73)=12 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5333}, +/*h(77)=13 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5339}, +/*h(9)=14 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5335}, +/*h(13)=15 EVV 0x3D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5341}, +/*h(42)=16 EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5336}, +/*h(46)=17 EVV 0x3D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6476}, +/*h(4)=1 EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6475}, +/*h(38)=2 EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6478}, +/*h(20)=3 EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6477}, +/*h(6)=4 EVV 0x3E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6474}, +/*h(36)=5 EVV 0x3E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6479} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x3f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5345}, +/*h(76)=1 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5351}, +/*h(8)=2 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5347}, +/*h(12)=3 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5353}, +/*h(41)=4 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5349}, +/*h(45)=5 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5355}, +/*h(74)=6 EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5344}, +/*h(78)=7 EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5350}, +/*h(10)=8 EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5346}, +/*h(14)=9 EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5352}, +/*h(40)=10 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5349}, +/*h(44)=11 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5355}, +/*h(73)=12 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5345}, +/*h(77)=13 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5351}, +/*h(9)=14 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5347}, +/*h(13)=15 EVV 0x3F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5353}, +/*h(42)=16 EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5348}, +/*h(46)=17 EVV 0x3F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5354} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x40_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5537}, +/*h(76)=1 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6581}, +/*h(8)=2 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5539}, +/*h(12)=3 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6577}, +/*h(41)=4 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5541}, +/*h(45)=5 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6579}, +/*h(74)=6 EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5536}, +/*h(78)=7 EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6580}, +/*h(10)=8 EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5538}, +/*h(14)=9 EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6576}, +/*h(40)=10 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5541}, +/*h(44)=11 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6579}, +/*h(73)=12 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5537}, +/*h(77)=13 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6581}, +/*h(9)=14 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5539}, +/*h(13)=15 EVV 0x40 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6577}, +/*h(42)=16 EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5540}, +/*h(46)=17 EVV 0x40 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6578} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x42_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[47] = { +/*h(89)=0 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 4808}, +/*empty slot1 */ {0,0}, +/*h(602)=2 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4804}, +/*h(348)=3 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 4803}, +/*h(94)=4 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4800}, +/*empty slot1 */ {0,0}, +/*h(607)=6 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {607, 4798}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=10 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 4810}, +/*h(91)=11 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 4805}, +/*empty slot1 */ {0,0}, +/*h(604)=13 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 4799}, +/*h(350)=14 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4802}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(863)=17 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {863, 4798}, +/*h(88)=18 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 4808}, +/*empty slot1 */ {0,0}, +/*h(601)=20 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 4806}, +/*h(347)=21 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 4805}, +/*h(93)=22 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 4801}, +/*empty slot1 */ {0,0}, +/*h(606)=24 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4797}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=28 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 4810}, +/*h(90)=29 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4807}, +/*empty slot1 */ {0,0}, +/*h(603)=31 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 4805}, +/*h(349)=32 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 4803}, +/*h(95)=33 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {95, 4798}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=38 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 4806}, +/*h(346)=39 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4809}, +/*h(92)=40 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 4801}, +/*h(859)=41 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 4805}, +/*h(605)=42 EVV 0x42 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 4799}, +/*h(351)=43 EVV 0x42 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {351, 4798}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 47ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x43_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4814}, +/*h(15)=2 EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {15, 4812}, +/*h(12)=3 EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4813}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4811}, +/*h(11)=6 EVV 0x43 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {11, 4815}, +/*h(8)=7 EVV 0x43 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4816} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x44_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(601)=0 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 6019}, +/*h(88)=1 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 6021}, +/*h(94)=2 EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 6026}, +/*h(349)=3 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 6029}, +/*h(604)=4 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 6025}, +/*h(90)=5 EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6020}, +/*h(345)=6 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 6023}, +/*h(600)=7 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 6019}, +/*h(606)=8 EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 6024}, +/*h(93)=9 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 6027}, +/*h(348)=10 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 6029}, +/*h(602)=11 EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6018}, +/*h(89)=12 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 6021}, +/*h(344)=13 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 6023}, +/*h(350)=14 EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 6028}, +/*h(605)=15 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 6025}, +/*h(92)=16 EVV 0x44 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 6027}, +/*h(346)=17 EVV 0x44 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6022} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((11*key % 83) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x45_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5723}, +/*h(76)=1 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5729}, +/*h(8)=2 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5725}, +/*h(12)=3 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5731}, +/*h(41)=4 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5727}, +/*h(45)=5 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5733}, +/*h(74)=6 EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5722}, +/*h(78)=7 EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5728}, +/*h(10)=8 EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5724}, +/*h(14)=9 EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5730}, +/*h(40)=10 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5727}, +/*h(44)=11 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5733}, +/*h(73)=12 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5723}, +/*h(77)=13 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5729}, +/*h(9)=14 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5725}, +/*h(13)=15 EVV 0x45 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5731}, +/*h(42)=16 EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5726}, +/*h(46)=17 EVV 0x45 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5732} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x46_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5687}, +/*h(76)=1 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5693}, +/*h(8)=2 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5689}, +/*h(12)=3 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5695}, +/*h(41)=4 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5691}, +/*h(45)=5 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5697}, +/*h(74)=6 EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5686}, +/*h(78)=7 EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5692}, +/*h(10)=8 EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5688}, +/*h(14)=9 EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5694}, +/*h(40)=10 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5691}, +/*h(44)=11 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5697}, +/*h(73)=12 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5687}, +/*h(77)=13 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5693}, +/*h(9)=14 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5689}, +/*h(13)=15 EVV 0x46 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5695}, +/*h(42)=16 EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5690}, +/*h(46)=17 EVV 0x46 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5696} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x47_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5651}, +/*h(76)=1 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5657}, +/*h(8)=2 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5653}, +/*h(12)=3 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5659}, +/*h(41)=4 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5655}, +/*h(45)=5 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5661}, +/*h(74)=6 EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5650}, +/*h(78)=7 EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5656}, +/*h(10)=8 EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5652}, +/*h(14)=9 EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5658}, +/*h(40)=10 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5655}, +/*h(44)=11 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5661}, +/*h(73)=12 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5651}, +/*h(77)=13 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5657}, +/*h(9)=14 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5653}, +/*h(13)=15 EVV 0x47 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5659}, +/*h(42)=16 EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5654}, +/*h(46)=17 EVV 0x47 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5660} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(601)=0 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 5825}, +/*h(88)=1 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 5827}, +/*h(94)=2 EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5820}, +/*h(349)=3 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 5823}, +/*h(604)=4 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 5819}, +/*h(90)=5 EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5826}, +/*h(345)=6 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 5829}, +/*h(600)=7 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 5825}, +/*h(606)=8 EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 5818}, +/*h(93)=9 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 5821}, +/*h(348)=10 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 5823}, +/*h(602)=11 EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5824}, +/*h(89)=12 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 5827}, +/*h(344)=13 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 5829}, +/*h(350)=14 EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 5822}, +/*h(605)=15 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 5819}, +/*h(92)=16 EVV 0x4C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 5821}, +/*h(346)=17 EVV 0x4C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5828} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((11*key % 83) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(10)=0 EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 5832}, +/*h(12)=1 EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 5831}, +/*h(14)=2 EVV 0x4D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 5830}, +/*h(8)=3 EVV 0x4D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 5833} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(601)=0 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 5861}, +/*h(88)=1 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 5863}, +/*h(94)=2 EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5856}, +/*h(349)=3 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 5859}, +/*h(604)=4 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 5855}, +/*h(90)=5 EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5862}, +/*h(345)=6 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 5865}, +/*h(600)=7 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 5861}, +/*h(606)=8 EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 5854}, +/*h(93)=9 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 5857}, +/*h(348)=10 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 5859}, +/*h(602)=11 EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5860}, +/*h(89)=12 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 5863}, +/*h(344)=13 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 5865}, +/*h(350)=14 EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 5858}, +/*h(605)=15 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 5855}, +/*h(92)=16 EVV 0x4E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 5857}, +/*h(346)=17 EVV 0x4E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5864} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((11*key % 83) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x4f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(10)=0 EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 5868}, +/*h(12)=1 EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 5867}, +/*h(14)=2 EVV 0x4F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 5866}, +/*h(8)=3 EVV 0x4F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 5869} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x50_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 3974}, +/*h(10)=3 EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 3969}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 3972}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 3974}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 3970}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 3972}, +/*h(74)=13 EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 3973}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x50 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 3970}, +/*h(42)=17 EVV 0x50 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 3971} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x51_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 3980}, +/*h(10)=3 EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 3975}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 3978}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 3980}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 3976}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 3978}, +/*h(74)=13 EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 3979}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x51 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 3976}, +/*h(42)=17 EVV 0x51 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 3977} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x52_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[29] = { +/*h(58)=0 EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {58, 4007}, +/*h(10)=1 EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 3981}, +/*empty slot1 */ {0,0}, +/*h(88)=3 EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {88, 4010}, +/*h(40)=4 EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 3984}, +/*empty slot1 */ {0,0}, +/*h(89)=6 EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {89, 4010}, +/*h(41)=7 EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 3984}, +/*h(80)=8 EVV 0x52 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()*/ {80, 4061}, +/*h(90)=9 EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {90, 4009}, +/*h(42)=10 EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 3983}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(72)=13 EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 3986}, +/*h(24)=14 EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {24, 4006}, +/*empty slot1 */ {0,0}, +/*h(73)=16 EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 3986}, +/*h(25)=17 EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {25, 4006}, +/*empty slot1 */ {0,0}, +/*h(74)=19 EVV 0x52 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 3985}, +/*h(26)=20 EVV 0x52 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {26, 4005}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=23 EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {56, 4008}, +/*h(8)=24 EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 3982}, +/*empty slot1 */ {0,0}, +/*h(57)=26 EVV 0x52 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {57, 4008}, +/*h(9)=27 EVV 0x52 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 3982}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 29); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x53_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 3992}, +/*h(10)=3 EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 3987}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 3990}, +/*h(80)=7 EVV 0x53 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() BCRC=0 VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()*/ {80, 4062}, +/*h(72)=8 EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 3992}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 3988}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 3990}, +/*h(74)=13 EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 3991}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x53 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 3988}, +/*h(42)=17 EVV 0x53 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 3989} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x54_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(348)=0 EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {348, 6859}, +/*h(346)=1 EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6852}, +/*h(344)=2 EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {344, 6853}, +/*h(94)=3 EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 6856}, +/*h(92)=4 EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {92, 6857}, +/*h(90)=5 EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6850}, +/*h(88)=6 EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {88, 6851}, +/*h(606)=7 EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 6860}, +/*h(604)=8 EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {604, 6861}, +/*h(602)=9 EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6854}, +/*h(600)=10 EVV 0x54 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {600, 6855}, +/*h(350)=11 EVV 0x54 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 6858} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((15*key % 31) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x55_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(601)=0 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 4064}, +/*h(88)=1 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 4066}, +/*h(94)=2 EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4071}, +/*h(349)=3 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 4074}, +/*h(604)=4 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 4070}, +/*h(90)=5 EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4065}, +/*h(345)=6 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 4068}, +/*h(600)=7 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 4064}, +/*h(606)=8 EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4069}, +/*h(93)=9 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 4072}, +/*h(348)=10 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 4074}, +/*h(602)=11 EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4063}, +/*h(89)=12 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 4066}, +/*h(344)=13 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 4068}, +/*h(350)=14 EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4073}, +/*h(605)=15 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 4070}, +/*h(92)=16 EVV 0x55 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 4072}, +/*h(346)=17 EVV 0x55 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4067} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((11*key % 83) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x58_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(602)=0 EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5132}, +/*h(600)=1 EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()*/ {600, 5131}, +/*h(346)=2 EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5140}, +/*h(344)=3 EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()*/ {344, 5139}, +/*h(90)=4 EVV 0x58 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5136}, +/*h(88)=5 EVV 0x58 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE1()*/ {88, 5135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x59_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(348)=0 EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()*/ {348, 5149}, +/*h(346)=1 EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6063}, +/*h(344)=2 EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()*/ {344, 6064}, +/*h(94)=3 EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5147}, +/*h(92)=4 EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()*/ {92, 5146}, +/*h(90)=5 EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6061}, +/*h(88)=6 EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()*/ {88, 6062}, +/*h(606)=7 EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 5144}, +/*h(604)=8 EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE1()*/ {604, 5143}, +/*h(602)=9 EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6065}, +/*h(600)=10 EVV 0x59 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE2()*/ {600, 6066}, +/*h(350)=11 EVV 0x59 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 5150} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((15*key % 31) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x5a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(348)=0 EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()*/ {348, 6068}, +/*h(604)=1 EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE2()*/ {604, 6069}, +/*h(344)=2 EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()*/ {344, 4123}, +/*h(600)=3 EVV 0x5A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE4()*/ {600, 4122} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x5b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(604)=0 EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_TUPLE4()*/ {604, 4124}, +/*h(600)=1 EVV 0x5B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_TUPLE8()*/ {600, 6067} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x62_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(348)=0 EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT()*/ {348, 6888}, +/*h(346)=1 EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6883}, +/*h(344)=2 EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT()*/ {344, 6882}, +/*h(94)=3 EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 6887}, +/*h(92)=4 EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT()*/ {92, 6886}, +/*h(90)=5 EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6881}, +/*h(88)=6 EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT()*/ {88, 6880}, +/*h(606)=7 EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 6891}, +/*h(604)=8 EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_GSCAT()*/ {604, 6890}, +/*h(602)=9 EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6885}, +/*h(600)=10 EVV 0x62 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_GSCAT()*/ {600, 6884}, +/*h(350)=11 EVV 0x62 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 6889} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((15*key % 31) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x63_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=2 EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT()*/ {600, 6872}, +/*h(94)=3 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 6875}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1118)=6 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1118, 6875}, +/*empty slot1 */ {0,0}, +/*h(602)=8 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6873}, +/*h(344)=9 EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT()*/ {344, 6870}, +/*empty slot1 */ {0,0}, +/*h(1626)=11 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 6873}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=14 EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT()*/ {604, 6878}, +/*h(346)=15 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6871}, +/*h(88)=16 EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_GSCAT()*/ {88, 6868}, +/*empty slot1 */ {0,0}, +/*h(1370)=18 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 6871}, +/*empty slot1 */ {0,0}, +/*h(606)=20 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 6879}, +/*h(348)=21 EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT()*/ {348, 6876}, +/*h(90)=22 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6869}, +/*h(1630)=23 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1630, 6879}, +/*empty slot1 */ {0,0}, +/*h(1114)=25 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 6869}, +/*empty slot1 */ {0,0}, +/*h(350)=27 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 6877}, +/*h(92)=28 EVV 0x63 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_GSCAT()*/ {92, 6874}, +/*empty slot1 */ {0,0}, +/*h(1374)=30 EVV 0x63 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1374, 6877} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 31); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x64_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5120}, +/*h(76)=1 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5126}, +/*h(8)=2 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5122}, +/*h(12)=3 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5128}, +/*h(41)=4 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5124}, +/*h(45)=5 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5130}, +/*h(74)=6 EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5119}, +/*h(78)=7 EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5125}, +/*h(10)=8 EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5121}, +/*h(14)=9 EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5127}, +/*h(40)=10 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5124}, +/*h(44)=11 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5130}, +/*h(73)=12 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5120}, +/*h(77)=13 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5126}, +/*h(9)=14 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5122}, +/*h(13)=15 EVV 0x64 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5128}, +/*h(42)=16 EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5123}, +/*h(46)=17 EVV 0x64 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5129} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x65_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4114}, +/*h(76)=1 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4108}, +/*h(8)=2 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4116}, +/*h(12)=3 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4110}, +/*h(41)=4 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4118}, +/*h(45)=5 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4112}, +/*h(74)=6 EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4113}, +/*h(78)=7 EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4107}, +/*h(10)=8 EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4115}, +/*h(14)=9 EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4109}, +/*h(40)=10 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4118}, +/*h(44)=11 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4112}, +/*h(73)=12 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4114}, +/*h(77)=13 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4108}, +/*h(9)=14 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4116}, +/*h(13)=15 EVV 0x65 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4110}, +/*h(42)=16 EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4117}, +/*h(46)=17 EVV 0x65 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4111} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x66_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6334}, +/*h(72)=1 EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6331}, +/*h(42)=2 EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6328}, +/*h(78)=3 EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6336}, +/*h(12)=4 EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6333}, +/*h(74)=5 EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6330}, +/*h(8)=6 EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6327}, +/*h(44)=7 EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6335}, +/*h(14)=8 EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6332}, +/*h(40)=9 EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6329}, +/*h(76)=10 EVV 0x66 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6337}, +/*h(10)=11 EVV 0x66 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x68_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[36] = { +/*empty slot1 */ {0,0}, +/*h(99)=1 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()*/ {99, 7015}, +/*empty slot1 */ {0,0}, +/*h(38)=3 EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {38, 7012}, +/*h(174)=4 EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 MASK=0*/ {174, 7022}, +/*h(162)=5 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()*/ {162, 7017}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(163)=8 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()*/ {163, 7017}, +/*empty slot1 */ {0,0}, +/*h(102)=10 EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 MASK=0*/ {102, 7014}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(42)=15 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()*/ {42, 7019}, +/*empty slot1 */ {0,0}, +/*h(166)=17 EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 MASK=0*/ {166, 7016}, +/*h(43)=18 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()*/ {43, 7019}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(106)=22 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()*/ {106, 7021}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(107)=25 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()*/ {107, 7021}, +/*empty slot1 */ {0,0}, +/*h(46)=27 EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 MASK=0*/ {46, 7018}, +/*h(34)=28 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()*/ {34, 7013}, +/*h(170)=29 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()*/ {170, 7023}, +/*empty slot1 */ {0,0}, +/*h(35)=31 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()*/ {35, 7013}, +/*h(171)=32 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULL()*/ {171, 7023}, +/*empty slot1 */ {0,0}, +/*h(110)=34 EVV 0x68 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 MASK=0*/ {110, 7020}, +/*h(98)=35 EVV 0x68 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULL()*/ {98, 7015} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 37) % 36); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x70_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(14)=0 EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6916}, +/*h(46)=1 EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6918}, +/*h(78)=2 EVV 0x70 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6920}, +/*h(12)=3 EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6917}, +/*h(44)=4 EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6919}, +/*h(76)=5 EVV 0x70 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6921} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x71_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 6909}, +/*h(76)=1 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6915}, +/*h(8)=2 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 6905}, +/*h(12)=3 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6911}, +/*h(41)=4 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 6907}, +/*h(45)=5 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6913}, +/*h(74)=6 EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6908}, +/*h(78)=7 EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6914}, +/*h(10)=8 EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6904}, +/*h(14)=9 EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6910}, +/*h(40)=10 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 6907}, +/*h(44)=11 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6913}, +/*h(73)=12 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 6909}, +/*h(77)=13 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6915}, +/*h(9)=14 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 6905}, +/*h(13)=15 EVV 0x71 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6911}, +/*h(42)=16 EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6906}, +/*h(46)=17 EVV 0x71 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6912} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x72_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[258] = { +/*h(426)=0 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {426, 3995}, +/*empty slot1 */ {0,0}, +/*h(128)=2 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {128, 3994}, +/*empty slot1 */ {0,0}, +/*h(682)=4 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {682, 3997}, +/*empty slot1 */ {0,0}, +/*h(384)=6 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {384, 3996}, +/*h(108)=7 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {108, 6953}, +/*h(129)=8 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {129, 3994}, +/*empty slot1 */ {0,0}, +/*h(640)=10 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {640, 3998}, +/*h(364)=11 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {364, 6955}, +/*h(385)=12 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {385, 3996}, +/*empty slot1 */ {0,0}, +/*h(130)=14 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {130, 3993}, +/*h(620)=15 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {620, 6957}, +/*h(641)=16 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {641, 3998}, +/*empty slot1 */ {0,0}, +/*h(386)=18 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {386, 3995}, +/*h(110)=19 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {110, 6952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(642)=22 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {642, 3997}, +/*h(366)=23 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {366, 6954}, +/*empty slot1 */ {0,0}, +/*h(68)=25 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {68, 6953}, +/*empty slot1 */ {0,0}, +/*h(622)=27 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {622, 6956}, +/*empty slot1 */ {0,0}, +/*h(324)=29 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {324, 6955}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(176)=32 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {176, 3994}, +/*h(580)=33 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {580, 6957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(432)=36 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {432, 3996}, +/*h(70)=37 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {70, 6952}, +/*h(177)=38 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {177, 3994}, +/*empty slot1 */ {0,0}, +/*h(688)=40 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {688, 3998}, +/*h(326)=41 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {326, 6954}, +/*h(433)=42 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {433, 3996}, +/*empty slot1 */ {0,0}, +/*h(178)=44 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {178, 3993}, +/*h(582)=45 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {582, 6956}, +/*h(689)=46 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {689, 3998}, +/*empty slot1 */ {0,0}, +/*h(434)=48 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {434, 3995}, +/*empty slot1 */ {0,0}, +/*h(136)=50 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {136, 3994}, +/*empty slot1 */ {0,0}, +/*h(690)=52 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {690, 3997}, +/*empty slot1 */ {0,0}, +/*h(392)=54 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {392, 3996}, +/*h(116)=55 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {116, 6953}, +/*h(137)=56 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {137, 3994}, +/*empty slot1 */ {0,0}, +/*h(648)=58 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {648, 3998}, +/*h(372)=59 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {372, 6955}, +/*h(393)=60 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {393, 3996}, +/*empty slot1 */ {0,0}, +/*h(138)=62 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {138, 3993}, +/*h(628)=63 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {628, 6957}, +/*h(649)=64 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {649, 3998}, +/*empty slot1 */ {0,0}, +/*h(394)=66 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {394, 3995}, +/*h(118)=67 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {118, 6952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(650)=70 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {650, 3997}, +/*h(374)=71 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {374, 6954}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6953}, +/*empty slot1 */ {0,0}, +/*h(630)=75 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {630, 6956}, +/*empty slot1 */ {0,0}, +/*h(332)=77 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {332, 6955}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(184)=80 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {184, 3994}, +/*h(588)=81 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {588, 6957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(440)=84 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {440, 3996}, +/*h(78)=85 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {78, 6952}, +/*h(185)=86 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {185, 3994}, +/*empty slot1 */ {0,0}, +/*h(696)=88 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {696, 3998}, +/*h(334)=89 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {334, 6954}, +/*h(441)=90 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {441, 3996}, +/*empty slot1 */ {0,0}, +/*h(186)=92 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {186, 3993}, +/*h(590)=93 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {590, 6956}, +/*h(697)=94 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {697, 3998}, +/*empty slot1 */ {0,0}, +/*h(442)=96 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {442, 3995}, +/*empty slot1 */ {0,0}, +/*h(144)=98 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {144, 3994}, +/*empty slot1 */ {0,0}, +/*h(698)=100 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {698, 3997}, +/*empty slot1 */ {0,0}, +/*h(400)=102 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {400, 3996}, +/*h(124)=103 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {124, 6953}, +/*h(145)=104 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {145, 3994}, +/*empty slot1 */ {0,0}, +/*h(656)=106 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {656, 3998}, +/*h(380)=107 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {380, 6955}, +/*h(401)=108 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {401, 3996}, +/*empty slot1 */ {0,0}, +/*h(146)=110 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {146, 3993}, +/*h(636)=111 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {636, 6957}, +/*h(657)=112 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {657, 3998}, +/*empty slot1 */ {0,0}, +/*h(402)=114 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {402, 3995}, +/*h(126)=115 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {126, 6952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(658)=118 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {658, 3997}, +/*h(382)=119 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {382, 6954}, +/*empty slot1 */ {0,0}, +/*h(84)=121 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {84, 6953}, +/*empty slot1 */ {0,0}, +/*h(638)=123 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {638, 6956}, +/*empty slot1 */ {0,0}, +/*h(340)=125 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {340, 6955}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(596)=129 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {596, 6957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(86)=133 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {86, 6952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(342)=137 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {342, 6954}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(598)=141 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {598, 6956}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=146 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {152, 3994}, +/*h(216)=147 EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {216, 4000}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(408)=150 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {408, 3996}, +/*h(472)=151 EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {472, 4002}, +/*h(153)=152 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {153, 3994}, +/*h(217)=153 EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {217, 4000}, +/*h(664)=154 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {664, 3998}, +/*h(728)=155 EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {728, 4004}, +/*h(409)=156 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {409, 3996}, +/*h(473)=157 EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {473, 4002}, +/*h(154)=158 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {154, 3993}, +/*h(218)=159 EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 3999}, +/*h(665)=160 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {665, 3998}, +/*h(729)=161 EVV 0x72 VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {729, 4004}, +/*h(410)=162 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {410, 3995}, +/*h(474)=163 EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 4001}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(666)=166 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {666, 3997}, +/*h(730)=167 EVV 0x72 VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 4003}, +/*empty slot1 */ {0,0}, +/*h(92)=169 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {92, 6953}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(348)=173 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {348, 6955}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=177 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {604, 6957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=181 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {94, 6952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=185 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {350, 6954}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=189 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {606, 6956}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(160)=194 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {160, 3994}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(416)=198 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {416, 3996}, +/*empty slot1 */ {0,0}, +/*h(161)=200 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {161, 3994}, +/*empty slot1 */ {0,0}, +/*h(672)=202 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {672, 3998}, +/*empty slot1 */ {0,0}, +/*h(417)=204 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {417, 3996}, +/*empty slot1 */ {0,0}, +/*h(162)=206 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {162, 3993}, +/*empty slot1 */ {0,0}, +/*h(673)=208 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {673, 3998}, +/*empty slot1 */ {0,0}, +/*h(418)=210 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {418, 3995}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(674)=214 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {674, 3997}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(100)=217 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {100, 6953}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(356)=221 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {356, 6955}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(612)=225 EVV 0x72 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {612, 6957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(102)=229 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {102, 6952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(358)=233 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {358, 6954}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(614)=237 EVV 0x72 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {614, 6956}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(168)=242 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {168, 3994}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(424)=246 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {424, 3996}, +/*empty slot1 */ {0,0}, +/*h(169)=248 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {169, 3994}, +/*empty slot1 */ {0,0}, +/*h(680)=250 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {680, 3998}, +/*empty slot1 */ {0,0}, +/*h(425)=252 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {425, 3996}, +/*empty slot1 */ {0,0}, +/*h(170)=254 EVV 0x72 VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {170, 3993}, +/*empty slot1 */ {0,0}, +/*h(681)=256 EVV 0x72 VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {681, 3998}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 383) % 258); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x73_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 6945}, +/*h(76)=1 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6951}, +/*h(8)=2 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 6941}, +/*h(12)=3 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6947}, +/*h(41)=4 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 6943}, +/*h(45)=5 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6949}, +/*h(74)=6 EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6944}, +/*h(78)=7 EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6950}, +/*h(10)=8 EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6940}, +/*h(14)=9 EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6946}, +/*h(40)=10 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 6943}, +/*h(44)=11 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6949}, +/*h(73)=12 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 6945}, +/*h(77)=13 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6951}, +/*h(9)=14 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 6941}, +/*h(13)=15 EVV 0x73 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6947}, +/*h(42)=16 EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6942}, +/*h(46)=17 EVV 0x73 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x75_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6406}, +/*h(72)=1 EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6837}, +/*h(42)=2 EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6834}, +/*h(78)=3 EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6408}, +/*h(12)=4 EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6405}, +/*h(74)=5 EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6836}, +/*h(8)=6 EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6833}, +/*h(44)=7 EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6407}, +/*h(14)=8 EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6404}, +/*h(40)=9 EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6835}, +/*h(76)=10 EVV 0x75 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6409}, +/*h(10)=11 EVV 0x75 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6832} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x76_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5217}, +/*h(76)=1 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5235}, +/*h(8)=2 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5219}, +/*h(12)=3 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5237}, +/*h(41)=4 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5221}, +/*h(45)=5 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5239}, +/*h(74)=6 EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5216}, +/*h(78)=7 EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5234}, +/*h(10)=8 EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5218}, +/*h(14)=9 EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5236}, +/*h(40)=10 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5221}, +/*h(44)=11 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5239}, +/*h(73)=12 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5217}, +/*h(77)=13 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5235}, +/*h(9)=14 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5219}, +/*h(13)=15 EVV 0x76 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5237}, +/*h(42)=16 EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5220}, +/*h(46)=17 EVV 0x76 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x77_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5229}, +/*h(76)=1 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5223}, +/*h(8)=2 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5231}, +/*h(12)=3 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5225}, +/*h(41)=4 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5233}, +/*h(45)=5 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5227}, +/*h(74)=6 EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5228}, +/*h(78)=7 EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5222}, +/*h(10)=8 EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5230}, +/*h(14)=9 EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5224}, +/*h(40)=10 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5233}, +/*h(44)=11 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5227}, +/*h(73)=12 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5229}, +/*h(77)=13 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5223}, +/*h(9)=14 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5231}, +/*h(13)=15 EVV 0x77 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5225}, +/*h(42)=16 EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5232}, +/*h(46)=17 EVV 0x77 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x78_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(602)=0 EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6344}, +/*h(600)=1 EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()*/ {600, 6345}, +/*h(346)=2 EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6341}, +/*h(344)=3 EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()*/ {344, 6342}, +/*h(90)=4 EVV 0x78 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6338}, +/*h(88)=5 EVV 0x78 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_TUPLE1_BYTE()*/ {88, 6339} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x79_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(602)=0 EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6353}, +/*h(600)=1 EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()*/ {600, 6354}, +/*h(346)=2 EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6350}, +/*h(344)=3 EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()*/ {344, 6351}, +/*h(90)=4 EVV 0x79 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6347}, +/*h(88)=5 EVV 0x79 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_TUPLE1_WORD()*/ {88, 6348} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(602)=0 EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6346}, +/*h(90)=1 EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6340}, +/*h(346)=2 EVV 0x7A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6343} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(602)=0 EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6355}, +/*h(90)=1 EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6349}, +/*h(346)=2 EVV 0x7B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6352} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[36] = { +/*h(1398)=0 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR*/ {1398, 5141}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1382)=4 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR*/ {1382, 5141}, +/*h(374)=5 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR*/ {374, 5137}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(358)=9 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR*/ {358, 5137}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2426)=12 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W1 NOEVSR*/ {2426, 5145}, +/*empty slot1 */ {0,0}, +/*h(2418)=14 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR*/ {2418, 5133}, +/*empty slot1 */ {0,0}, +/*h(2410)=16 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 mode64 W0 NOEVSR*/ {2410, 5134}, +/*h(1402)=17 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 mode64 NOEVSR*/ {1402, 5151}, +/*h(2402)=18 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR*/ {2402, 5133}, +/*h(1394)=19 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR*/ {1394, 5141}, +/*empty slot1 */ {0,0}, +/*h(1386)=21 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 mode64 W0 NOEVSR*/ {1386, 5142}, +/*h(378)=22 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR*/ {378, 5148}, +/*h(1378)=23 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 not64 NOEVSR*/ {1378, 5141}, +/*h(370)=24 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR*/ {370, 5137}, +/*empty slot1 */ {0,0}, +/*h(362)=26 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR*/ {362, 5138}, +/*empty slot1 */ {0,0}, +/*h(354)=28 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR*/ {354, 5137}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2422)=31 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR*/ {2422, 5133}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2406)=35 EVV 0x7C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 not64 NOEVSR*/ {2406, 5133} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 36ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6412}, +/*h(72)=1 EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6843}, +/*h(42)=2 EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6840}, +/*h(78)=3 EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6414}, +/*h(12)=4 EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6411}, +/*h(74)=5 EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6842}, +/*h(8)=6 EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6839}, +/*h(44)=7 EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6413}, +/*h(14)=8 EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6410}, +/*h(40)=9 EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6841}, +/*h(76)=10 EVV 0x7D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6415}, +/*h(10)=11 EVV 0x7D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6838} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5285}, +/*h(76)=1 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5303}, +/*h(8)=2 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5287}, +/*h(12)=3 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5305}, +/*h(41)=4 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5289}, +/*h(45)=5 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5307}, +/*h(74)=6 EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5284}, +/*h(78)=7 EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5302}, +/*h(10)=8 EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5286}, +/*h(14)=9 EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5304}, +/*h(40)=10 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5289}, +/*h(44)=11 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5307}, +/*h(73)=12 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5285}, +/*h(77)=13 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5303}, +/*h(9)=14 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5287}, +/*h(13)=15 EVV 0x7E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5305}, +/*h(42)=16 EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5288}, +/*h(46)=17 EVV 0x7E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5306} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x7f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5297}, +/*h(76)=1 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5291}, +/*h(8)=2 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5299}, +/*h(12)=3 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5293}, +/*h(41)=4 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5301}, +/*h(45)=5 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5295}, +/*h(74)=6 EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5296}, +/*h(78)=7 EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5290}, +/*h(10)=8 EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5298}, +/*h(14)=9 EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5292}, +/*h(40)=10 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5301}, +/*h(44)=11 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5295}, +/*h(73)=12 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5297}, +/*h(77)=13 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5291}, +/*h(9)=14 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5299}, +/*h(13)=15 EVV 0x7F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5293}, +/*h(42)=16 EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5300}, +/*h(46)=17 EVV 0x7F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x83_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6849}, +/*h(46)=1 EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6846}, +/*h(12)=2 EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6845}, +/*h(77)=3 EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6849}, +/*h(13)=4 EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6845}, +/*h(78)=5 EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6848}, +/*h(44)=6 EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6847}, +/*h(14)=7 EVV 0x83 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6844}, +/*h(45)=8 EVV 0x83 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6847} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x88_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(348)=0 EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()*/ {348, 4419}, +/*h(346)=1 EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4426}, +/*h(344)=2 EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()*/ {344, 4425}, +/*h(94)=3 EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4418}, +/*h(92)=4 EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()*/ {92, 4417}, +/*h(90)=5 EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4424}, +/*h(88)=6 EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()*/ {88, 4423}, +/*h(606)=7 EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4416}, +/*h(604)=8 EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()*/ {604, 4415}, +/*h(602)=9 EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4422}, +/*h(600)=10 EVV 0x88 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()*/ {600, 4421}, +/*h(350)=11 EVV 0x88 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4420} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((15*key % 31) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x89_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(348)=0 EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()*/ {348, 5318}, +/*h(346)=1 EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5313}, +/*h(344)=2 EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()*/ {344, 5312}, +/*h(94)=3 EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5317}, +/*h(92)=4 EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()*/ {92, 5316}, +/*h(90)=5 EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5311}, +/*h(88)=6 EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()*/ {88, 5310}, +/*h(606)=7 EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 5315}, +/*h(604)=8 EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_GSCAT()*/ {604, 5314}, +/*h(602)=9 EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5309}, +/*h(600)=10 EVV 0x89 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_GSCAT()*/ {600, 5308}, +/*h(350)=11 EVV 0x89 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 5319} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((15*key % 31) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=2 EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {600, 4167}, +/*h(94)=3 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4164}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1118)=6 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1118, 4164}, +/*empty slot1 */ {0,0}, +/*h(602)=8 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4168}, +/*h(344)=9 EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {344, 4171}, +/*empty slot1 */ {0,0}, +/*h(1626)=11 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 4168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=14 EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {604, 4161}, +/*h(346)=15 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4172}, +/*h(88)=16 EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {88, 4169}, +/*empty slot1 */ {0,0}, +/*h(1370)=18 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 4172}, +/*empty slot1 */ {0,0}, +/*h(606)=20 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4162}, +/*h(348)=21 EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {348, 4165}, +/*h(90)=22 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4170}, +/*h(1630)=23 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1630, 4162}, +/*empty slot1 */ {0,0}, +/*h(1114)=25 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 4170}, +/*empty slot1 */ {0,0}, +/*h(350)=27 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4166}, +/*h(92)=28 EVV 0x8A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {92, 4163}, +/*empty slot1 */ {0,0}, +/*h(1374)=30 EVV 0x8A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1374, 4166} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 31); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=2 EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {600, 5200}, +/*h(94)=3 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5209}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1118)=6 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1118, 5209}, +/*empty slot1 */ {0,0}, +/*h(602)=8 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 5201}, +/*h(344)=9 EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {344, 5204}, +/*empty slot1 */ {0,0}, +/*h(1626)=11 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 5201}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=14 EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {604, 5206}, +/*h(346)=15 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 5205}, +/*h(88)=16 EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {88, 5202}, +/*empty slot1 */ {0,0}, +/*h(1370)=18 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 5205}, +/*empty slot1 */ {0,0}, +/*h(606)=20 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 5207}, +/*h(348)=21 EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {348, 5210}, +/*h(90)=22 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 5203}, +/*h(1630)=23 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1630, 5207}, +/*empty slot1 */ {0,0}, +/*h(1114)=25 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 5203}, +/*empty slot1 */ {0,0}, +/*h(350)=27 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 5211}, +/*h(92)=28 EVV 0x8B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {92, 5208}, +/*empty slot1 */ {0,0}, +/*h(1374)=30 EVV 0x8B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1374, 5211} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 31); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6418}, +/*h(72)=1 EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6831}, +/*h(42)=2 EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6828}, +/*h(78)=3 EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6420}, +/*h(12)=4 EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6417}, +/*h(74)=5 EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6830}, +/*h(8)=6 EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6827}, +/*h(44)=7 EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6419}, +/*h(14)=8 EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6416}, +/*h(40)=9 EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6829}, +/*h(76)=10 EVV 0x8D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6421}, +/*h(10)=11 EVV 0x8D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6826} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x8f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(42)=0 EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {42, 6864}, +/*h(8)=1 EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6863}, +/*h(72)=2 EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6867}, +/*h(10)=3 EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {10, 6862}, +/*h(74)=4 EVV 0x8F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {74, 6866}, +/*h(40)=5 EVV 0x8F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6865} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((8*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x90_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 5323}, +/*h(486)=1 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 5321}, +/*h(1510)=2 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 5322}, +/*h(484)=3 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 5321}, +/*h(2534)=4 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 5320}, +/*h(1508)=5 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 5322}, +/*h(2532)=6 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 5320}, +/*h(502)=7 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 5324}, +/*h(1526)=8 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 5325}, +/*h(500)=9 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 5324}, +/*h(2550)=10 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 5323}, +/*h(1524)=11 EVV 0x90 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 5325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x91_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 5329}, +/*h(486)=1 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 5327}, +/*h(1510)=2 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 5328}, +/*h(484)=3 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 5327}, +/*h(2534)=4 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 5326}, +/*h(1508)=5 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 5328}, +/*h(2532)=6 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 5326}, +/*h(502)=7 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 5330}, +/*h(1526)=8 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 5331}, +/*h(500)=9 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 5330}, +/*h(2550)=10 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 5329}, +/*h(1524)=11 EVV 0x91 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 5331} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x92_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 4785}, +/*h(486)=1 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 4789}, +/*h(1510)=2 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 4790}, +/*h(484)=3 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 4789}, +/*h(2534)=4 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 4788}, +/*h(1508)=5 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 4790}, +/*h(2532)=6 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 4788}, +/*h(502)=7 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 4786}, +/*h(1526)=8 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 4787}, +/*h(500)=9 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 4786}, +/*h(2550)=10 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 4785}, +/*h(1524)=11 EVV 0x92 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 4787} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x93_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 4791}, +/*h(486)=1 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 4795}, +/*h(1510)=2 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 4796}, +/*h(484)=3 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 4795}, +/*h(2534)=4 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 4794}, +/*h(1508)=5 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 4796}, +/*h(2532)=6 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 4794}, +/*h(502)=7 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 4792}, +/*h(1526)=8 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 4793}, +/*h(500)=9 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 4792}, +/*h(2550)=10 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 4791}, +/*h(1524)=11 EVV 0x93 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 4793} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x96_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4534}, +/*h(14)=1 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4524}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4533}, +/*h(15)=4 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4522}, +/*h(111)=5 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4522}, +/*h(43)=6 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4529}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4527}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4530}, +/*h(45)=12 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4527}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4530}, +/*h(46)=15 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4526}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4528}, +/*h(47)=18 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4522}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4529}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4523}, +/*h(8)=24 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4532}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4523}, +/*h(9)=27 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4532}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4521}, +/*h(10)=30 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4531}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4522}, +/*h(11)=33 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4529}, +/*h(107)=34 EVV 0x96 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4529}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4525}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4534}, +/*h(13)=39 EVV 0x96 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4525}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x97_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4636}, +/*h(14)=1 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4626}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4635}, +/*h(15)=4 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4624}, +/*h(111)=5 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4624}, +/*h(43)=6 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4631}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4629}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4632}, +/*h(45)=12 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4629}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4632}, +/*h(46)=15 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4628}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4630}, +/*h(47)=18 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4624}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4631}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4625}, +/*h(8)=24 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4634}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4625}, +/*h(9)=27 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4634}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4623}, +/*h(10)=30 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4633}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4624}, +/*h(11)=33 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4631}, +/*h(107)=34 EVV 0x97 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4631}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4627}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4636}, +/*h(13)=39 EVV 0x97 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4627}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x98_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4474}, +/*h(14)=1 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4464}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4473}, +/*h(15)=4 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4462}, +/*h(111)=5 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4462}, +/*h(43)=6 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4469}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4467}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4470}, +/*h(45)=12 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4467}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4470}, +/*h(46)=15 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4466}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4468}, +/*h(47)=18 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4462}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4469}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4463}, +/*h(8)=24 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4472}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4463}, +/*h(9)=27 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4472}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4461}, +/*h(10)=30 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4471}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4462}, +/*h(11)=33 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4469}, +/*h(107)=34 EVV 0x98 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4469}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4465}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4474}, +/*h(13)=39 EVV 0x98 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4465}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x99_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4478}, +/*h(15)=2 EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4476}, +/*h(12)=3 EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4477}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4475}, +/*h(11)=6 EVV 0x99 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4479}, +/*h(8)=7 EVV 0x99 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4480} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4576}, +/*h(14)=1 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4566}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4575}, +/*h(15)=4 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4564}, +/*h(111)=5 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4564}, +/*h(43)=6 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4571}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4569}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4572}, +/*h(45)=12 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4569}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4572}, +/*h(46)=15 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4568}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4570}, +/*h(47)=18 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4564}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4571}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4565}, +/*h(8)=24 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4574}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4565}, +/*h(9)=27 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4574}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4563}, +/*h(10)=30 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4573}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4564}, +/*h(11)=33 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4571}, +/*h(107)=34 EVV 0x9A V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4571}, +/*h(80)=35 EVV 0x9A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()*/ {80, 4057}, +/*h(12)=36 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4567}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4576}, +/*h(13)=39 EVV 0x9A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4567}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4580}, +/*h(15)=2 EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4578}, +/*empty slot1 */ {0,0}, +/*h(12)=4 EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4579}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4577}, +/*h(11)=7 EVV 0x9B V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4581}, +/*h(16)=8 EVV 0x9B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()*/ {16, 4058}, +/*h(8)=9 EVV 0x9B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4582} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4678}, +/*h(14)=1 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4668}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4677}, +/*h(15)=4 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4666}, +/*h(111)=5 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4666}, +/*h(43)=6 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4673}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4671}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4674}, +/*h(45)=12 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4671}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4674}, +/*h(46)=15 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4670}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4672}, +/*h(47)=18 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4666}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4673}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4667}, +/*h(8)=24 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4676}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4667}, +/*h(9)=27 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4676}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4665}, +/*h(10)=30 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4675}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4666}, +/*h(11)=33 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4673}, +/*h(107)=34 EVV 0x9C V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4673}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4669}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4678}, +/*h(13)=39 EVV 0x9C V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4669}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4682}, +/*h(15)=2 EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4680}, +/*h(12)=3 EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4681}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4679}, +/*h(11)=6 EVV 0x9D V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4683}, +/*h(8)=7 EVV 0x9D V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4684} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4738}, +/*h(14)=1 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4728}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4737}, +/*h(15)=4 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4726}, +/*h(111)=5 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4726}, +/*h(43)=6 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4733}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4731}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4734}, +/*h(45)=12 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4731}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4734}, +/*h(46)=15 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4730}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4732}, +/*h(47)=18 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4726}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4733}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4727}, +/*h(8)=24 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4736}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4727}, +/*h(9)=27 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4736}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4725}, +/*h(10)=30 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4735}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4726}, +/*h(11)=33 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4733}, +/*h(107)=34 EVV 0x9E V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4733}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4729}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4738}, +/*h(13)=39 EVV 0x9E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4729}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0x9f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4742}, +/*h(15)=2 EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4740}, +/*h(12)=3 EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4741}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4739}, +/*h(11)=6 EVV 0x9F V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4743}, +/*h(8)=7 EVV 0x9F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4744} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa0_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 5611}, +/*h(486)=1 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 5609}, +/*h(1510)=2 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 5610}, +/*h(484)=3 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 5609}, +/*h(2534)=4 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 5608}, +/*h(1508)=5 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 5610}, +/*h(2532)=6 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 5608}, +/*h(502)=7 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 5612}, +/*h(1526)=8 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 5613}, +/*h(500)=9 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 5612}, +/*h(2550)=10 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 5611}, +/*h(1524)=11 EVV 0xA0 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 5613} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa1_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 5617}, +/*h(486)=1 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 5615}, +/*h(1510)=2 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 5616}, +/*h(484)=3 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 5615}, +/*h(2534)=4 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 5614}, +/*h(1508)=5 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 5616}, +/*h(2532)=6 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 5614}, +/*h(502)=7 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 5618}, +/*h(1526)=8 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 5619}, +/*h(500)=9 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 5618}, +/*h(2550)=10 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 5617}, +/*h(1524)=11 EVV 0xA1 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 5619} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa2_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 5890}, +/*h(486)=1 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 5894}, +/*h(1510)=2 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 5895}, +/*h(484)=3 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 5894}, +/*h(2534)=4 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 5893}, +/*h(1508)=5 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 5895}, +/*h(2532)=6 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 5893}, +/*h(502)=7 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 5891}, +/*h(1526)=8 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 5892}, +/*h(500)=9 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 5891}, +/*h(2550)=10 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 5890}, +/*h(1524)=11 EVV 0xA2 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 5892} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa3_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(2548)=0 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2548, 5896}, +/*h(486)=1 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {486, 5900}, +/*h(1510)=2 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1510, 5901}, +/*h(484)=3 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W0 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {484, 5900}, +/*h(2534)=4 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2534, 5899}, +/*h(1508)=5 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W0 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {1508, 5901}, +/*h(2532)=6 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W0 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {2532, 5899}, +/*h(502)=7 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {502, 5897}, +/*h(1526)=8 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1526, 5898}, +/*h(500)=9 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL128 W1 UISA_VMODRM_XMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {500, 5897}, +/*h(2550)=10 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL512 W1 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {2550, 5896}, +/*h(1524)=11 EVV 0xA3 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] RM=4 BCRC=0 VL256 W1 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {1524, 5898} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 37) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4548}, +/*h(14)=1 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4538}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4547}, +/*h(15)=4 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4536}, +/*h(111)=5 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4536}, +/*h(43)=6 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4543}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4541}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4544}, +/*h(45)=12 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4541}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4544}, +/*h(46)=15 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4540}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4542}, +/*h(47)=18 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4536}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4543}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4537}, +/*h(8)=24 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4546}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4537}, +/*h(9)=27 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4546}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4535}, +/*h(10)=30 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4545}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4536}, +/*h(11)=33 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4543}, +/*h(107)=34 EVV 0xA6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4543}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4539}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4548}, +/*h(13)=39 EVV 0xA6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4539}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4650}, +/*h(14)=1 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4640}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4649}, +/*h(15)=4 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4638}, +/*h(111)=5 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4638}, +/*h(43)=6 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4645}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4643}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4646}, +/*h(45)=12 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4643}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4646}, +/*h(46)=15 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4642}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4644}, +/*h(47)=18 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4638}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4645}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4639}, +/*h(8)=24 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4648}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4639}, +/*h(9)=27 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4648}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4637}, +/*h(10)=30 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4647}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4638}, +/*h(11)=33 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4645}, +/*h(107)=34 EVV 0xA7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4645}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4641}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4650}, +/*h(13)=39 EVV 0xA7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4641}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4494}, +/*h(14)=1 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4484}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4493}, +/*h(15)=4 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4482}, +/*h(111)=5 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4482}, +/*h(43)=6 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4489}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4487}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4490}, +/*h(45)=12 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4487}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4490}, +/*h(46)=15 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4486}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4488}, +/*h(47)=18 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4482}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4489}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4483}, +/*h(8)=24 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4492}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4483}, +/*h(9)=27 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4492}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4481}, +/*h(10)=30 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4491}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4482}, +/*h(11)=33 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4489}, +/*h(107)=34 EVV 0xA8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4489}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4485}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4494}, +/*h(13)=39 EVV 0xA8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4485}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xa9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4498}, +/*h(15)=2 EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4496}, +/*h(12)=3 EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4497}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4495}, +/*h(11)=6 EVV 0xA9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4499}, +/*h(8)=7 EVV 0xA9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4500} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xaa_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4596}, +/*h(14)=1 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4586}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4595}, +/*h(15)=4 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4584}, +/*h(111)=5 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4584}, +/*h(43)=6 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4591}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4589}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4592}, +/*h(45)=12 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4589}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4592}, +/*h(46)=15 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4588}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4590}, +/*h(47)=18 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4584}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4591}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4585}, +/*h(8)=24 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4594}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4585}, +/*h(9)=27 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4594}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4583}, +/*h(10)=30 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4593}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4584}, +/*h(11)=33 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4591}, +/*h(107)=34 EVV 0xAA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4591}, +/*h(80)=35 EVV 0xAA VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()*/ {80, 4059}, +/*h(12)=36 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4587}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4596}, +/*h(13)=39 EVV 0xAA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4587}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xab_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4600}, +/*h(15)=2 EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4598}, +/*empty slot1 */ {0,0}, +/*h(12)=4 EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4599}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4597}, +/*h(11)=7 EVV 0xAB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4601}, +/*h(16)=8 EVV 0xAB VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_TUPLE1_4X()*/ {16, 4060}, +/*h(8)=9 EVV 0xAB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4602} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xac_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4698}, +/*h(14)=1 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4688}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4697}, +/*h(15)=4 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4686}, +/*h(111)=5 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4686}, +/*h(43)=6 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4693}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4691}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4694}, +/*h(45)=12 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4691}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4694}, +/*h(46)=15 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4690}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4692}, +/*h(47)=18 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4686}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4693}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4687}, +/*h(8)=24 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4696}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4687}, +/*h(9)=27 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4696}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4685}, +/*h(10)=30 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4695}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4686}, +/*h(11)=33 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4693}, +/*h(107)=34 EVV 0xAC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4693}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4689}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4698}, +/*h(13)=39 EVV 0xAC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4689}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xad_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4702}, +/*h(15)=2 EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4700}, +/*h(12)=3 EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4701}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4699}, +/*h(11)=6 EVV 0xAD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4703}, +/*h(8)=7 EVV 0xAD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4704} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xae_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4758}, +/*h(14)=1 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4748}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4757}, +/*h(15)=4 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4746}, +/*h(111)=5 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4746}, +/*h(43)=6 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4753}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4751}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4754}, +/*h(45)=12 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4751}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4754}, +/*h(46)=15 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4750}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4752}, +/*h(47)=18 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4746}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4753}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4747}, +/*h(8)=24 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4756}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4747}, +/*h(9)=27 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4756}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4745}, +/*h(10)=30 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4755}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4746}, +/*h(11)=33 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4753}, +/*h(107)=34 EVV 0xAE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4753}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4749}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4758}, +/*h(13)=39 EVV 0xAE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4749}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xaf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4762}, +/*h(15)=2 EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4760}, +/*h(12)=3 EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4761}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4759}, +/*h(11)=6 EVV 0xAF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4763}, +/*h(8)=7 EVV 0xAF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4764} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6825}, +/*h(46)=1 EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6822}, +/*h(12)=2 EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6821}, +/*h(77)=3 EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6825}, +/*h(13)=4 EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6821}, +/*h(78)=5 EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6824}, +/*h(44)=6 EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6823}, +/*h(14)=7 EVV 0xB4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6820}, +/*h(45)=8 EVV 0xB4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6823} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb5_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6819}, +/*h(46)=1 EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6816}, +/*h(12)=2 EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6815}, +/*h(77)=3 EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6819}, +/*h(13)=4 EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6815}, +/*h(78)=5 EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6818}, +/*h(44)=6 EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6817}, +/*h(14)=7 EVV 0xB5 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6814}, +/*h(45)=8 EVV 0xB5 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6817} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4562}, +/*h(14)=1 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4552}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4561}, +/*h(15)=4 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4550}, +/*h(111)=5 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4550}, +/*h(43)=6 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4557}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4555}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4558}, +/*h(45)=12 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4555}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4558}, +/*h(46)=15 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4554}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4556}, +/*h(47)=18 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4550}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4557}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4551}, +/*h(8)=24 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4560}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4551}, +/*h(9)=27 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4560}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4549}, +/*h(10)=30 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4559}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4550}, +/*h(11)=33 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4557}, +/*h(107)=34 EVV 0xB6 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4557}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4553}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4562}, +/*h(13)=39 EVV 0xB6 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4553}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4664}, +/*h(14)=1 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4654}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4663}, +/*h(15)=4 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4652}, +/*h(111)=5 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4652}, +/*h(43)=6 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4659}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4657}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4660}, +/*h(45)=12 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4657}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4660}, +/*h(46)=15 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4656}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4658}, +/*h(47)=18 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4652}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4659}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4653}, +/*h(8)=24 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4662}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4653}, +/*h(9)=27 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4662}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4651}, +/*h(10)=30 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4661}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4652}, +/*h(11)=33 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4659}, +/*h(107)=34 EVV 0xB7 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4659}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4655}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4664}, +/*h(13)=39 EVV 0xB7 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4655}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4514}, +/*h(14)=1 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4504}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4513}, +/*h(15)=4 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4502}, +/*h(111)=5 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4502}, +/*h(43)=6 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4509}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4507}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4510}, +/*h(45)=12 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4507}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4510}, +/*h(46)=15 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4506}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4508}, +/*h(47)=18 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4502}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4509}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4503}, +/*h(8)=24 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4512}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4503}, +/*h(9)=27 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4512}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4501}, +/*h(10)=30 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4511}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4502}, +/*h(11)=33 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4509}, +/*h(107)=34 EVV 0xB8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4509}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4505}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4514}, +/*h(13)=39 EVV 0xB8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4505}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xb9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4518}, +/*h(15)=2 EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4516}, +/*h(12)=3 EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4517}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4515}, +/*h(11)=6 EVV 0xB9 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4519}, +/*h(8)=7 EVV 0xB9 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4520} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xba_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4616}, +/*h(14)=1 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4606}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4615}, +/*h(15)=4 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4604}, +/*h(111)=5 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4604}, +/*h(43)=6 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4611}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4609}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4612}, +/*h(45)=12 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4609}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4612}, +/*h(46)=15 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4608}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4610}, +/*h(47)=18 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4604}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4611}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4605}, +/*h(8)=24 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4614}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4605}, +/*h(9)=27 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4614}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4603}, +/*h(10)=30 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4613}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4604}, +/*h(11)=33 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4611}, +/*h(107)=34 EVV 0xBA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4611}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4607}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4616}, +/*h(13)=39 EVV 0xBA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4607}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4620}, +/*h(15)=2 EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4618}, +/*h(12)=3 EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4619}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4617}, +/*h(11)=6 EVV 0xBB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4621}, +/*h(8)=7 EVV 0xBB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4622} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4718}, +/*h(14)=1 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4708}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4717}, +/*h(15)=4 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4706}, +/*h(111)=5 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4706}, +/*h(43)=6 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4713}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4711}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4714}, +/*h(45)=12 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4711}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4714}, +/*h(46)=15 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4710}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4712}, +/*h(47)=18 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4706}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4713}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4707}, +/*h(8)=24 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4716}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4707}, +/*h(9)=27 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4716}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4705}, +/*h(10)=30 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4715}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4706}, +/*h(11)=33 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4713}, +/*h(107)=34 EVV 0xBC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4713}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4709}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4718}, +/*h(13)=39 EVV 0xBC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4709}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4722}, +/*h(15)=2 EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4720}, +/*h(12)=3 EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4721}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4719}, +/*h(11)=6 EVV 0xBD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4723}, +/*h(8)=7 EVV 0xBD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4724} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbe_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 4778}, +/*h(14)=1 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4768}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 4777}, +/*h(15)=4 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4766}, +/*h(111)=5 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4766}, +/*h(43)=6 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 4773}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4771}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 4774}, +/*h(45)=12 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4771}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 4774}, +/*h(46)=15 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4770}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 4772}, +/*h(47)=18 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4766}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 4773}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4767}, +/*h(8)=24 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 4776}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4767}, +/*h(9)=27 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 4776}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4765}, +/*h(10)=30 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 4775}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4766}, +/*h(11)=33 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 4773}, +/*h(107)=34 EVV 0xBE V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 4773}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4769}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 4778}, +/*h(13)=39 EVV 0xBE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4769}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xbf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4782}, +/*h(15)=2 EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {15, 4780}, +/*h(12)=3 EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4781}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4779}, +/*h(11)=6 EVV 0xBF V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 4783}, +/*h(8)=7 EVV 0xBF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4784} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(601)=0 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 6007}, +/*h(88)=1 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 6009}, +/*h(94)=2 EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 6014}, +/*h(349)=3 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 6017}, +/*h(604)=4 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 6013}, +/*h(90)=5 EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6008}, +/*h(345)=6 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 6011}, +/*h(600)=7 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 6007}, +/*h(606)=8 EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 6012}, +/*h(93)=9 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 6015}, +/*h(348)=10 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 6017}, +/*h(602)=11 EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6006}, +/*h(89)=12 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 6009}, +/*h(344)=13 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 6011}, +/*h(350)=14 EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 6016}, +/*h(605)=15 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 6013}, +/*h(92)=16 EVV 0xC4 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 6015}, +/*h(346)=17 EVV 0xC4 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((11*key % 83) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(20326)=0 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20326, 4054}, +/*h(20372)=1 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20372, 4017}, +/*h(20310)=2 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20310, 4050}, +/*h(20452)=3 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20452, 4053}, +/*h(20390)=4 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20390, 4021}, +/*h(20260)=5 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20260, 4022}, +/*h(20436)=6 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20436, 4049}, +/*h(20374)=7 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20374, 4017}, +/*h(20244)=8 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20244, 4018}, +/*h(20454)=9 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20454, 4053}, +/*h(20324)=10 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20324, 4054}, +/*h(20262)=11 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20262, 4022}, +/*h(20438)=12 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20438, 4049}, +/*h(20308)=13 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20308, 4050}, +/*h(20246)=14 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20246, 4018}, +/*h(20388)=15 EVV 0xC6 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_YMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20388, 4021} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REG_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 17) % 16); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(20326)=0 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20326, 4056}, +/*h(20372)=1 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20372, 4019}, +/*h(20310)=2 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20310, 4052}, +/*h(20452)=3 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20452, 4055}, +/*h(20390)=4 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20390, 4023}, +/*h(20260)=5 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20260, 4024}, +/*h(20436)=6 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20436, 4051}, +/*h(20374)=7 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20374, 4019}, +/*h(20244)=8 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20244, 4020}, +/*h(20454)=9 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20454, 4055}, +/*h(20324)=10 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20324, 4056}, +/*h(20262)=11 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20262, 4024}, +/*h(20438)=12 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20438, 4051}, +/*h(20308)=13 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b101] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20308, 4052}, +/*h(20246)=14 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b001] RM[nnn] BCRC=0 VL512 W0 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_32_BITS() NELEM_GSCAT()*/ {20246, 4020}, +/*h(20388)=15 EVV 0xC7 V66 V0F38 MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 VL512 W1 RM=4 UISA_VMODRM_ZMM() eanot16 NOVSR ZEROING=0 ESIZE_64_BITS() NELEM_GSCAT()*/ {20388, 4023} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REG_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 17) % 16); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xc8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[28] = { +/*empty slot1 */ {0,0}, +/*h(604)=1 EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 4013}, +/*h(605)=2 EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 4013}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=6 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4011}, +/*empty slot1 */ {0,0}, +/*h(95)=8 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {95, 4012}, +/*h(351)=9 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {351, 4012}, +/*h(607)=10 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {607, 4012}, +/*h(863)=11 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {863, 4012}, +/*empty slot1 */ {0,0}, +/*h(600)=13 EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 4016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(601)=17 EVV 0xC8 V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 4016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(602)=21 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4014}, +/*empty slot1 */ {0,0}, +/*h(91)=23 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 4015}, +/*h(347)=24 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 4015}, +/*h(603)=25 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 4015}, +/*h(859)=26 EVV 0xC8 V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 4015}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 31) % 28); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xca_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[28] = { +/*empty slot1 */ {0,0}, +/*h(604)=1 EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 4027}, +/*h(605)=2 EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 4027}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=6 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4025}, +/*empty slot1 */ {0,0}, +/*h(95)=8 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {95, 4026}, +/*h(351)=9 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {351, 4026}, +/*h(607)=10 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {607, 4026}, +/*h(863)=11 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {863, 4026}, +/*empty slot1 */ {0,0}, +/*h(600)=13 EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 4030}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(601)=17 EVV 0xCA V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 4030}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(602)=21 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4028}, +/*empty slot1 */ {0,0}, +/*h(91)=23 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 4029}, +/*h(347)=24 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 4029}, +/*h(603)=25 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 4029}, +/*h(859)=26 EVV 0xCA V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 4029}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 31) % 28); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4034}, +/*h(15)=2 EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {15, 4032}, +/*h(12)=3 EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4033}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4031}, +/*h(11)=6 EVV 0xCB V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {11, 4035}, +/*h(8)=7 EVV 0xCB V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4036} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[28] = { +/*empty slot1 */ {0,0}, +/*h(604)=1 EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 4039}, +/*h(605)=2 EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 4039}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=6 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4037}, +/*empty slot1 */ {0,0}, +/*h(95)=8 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {95, 4038}, +/*h(351)=9 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {351, 4038}, +/*h(607)=10 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {607, 4038}, +/*h(863)=11 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {863, 4038}, +/*empty slot1 */ {0,0}, +/*h(600)=13 EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 4042}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(601)=17 EVV 0xCC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 4042}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(602)=21 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4040}, +/*empty slot1 */ {0,0}, +/*h(91)=23 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 4041}, +/*h(347)=24 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 4041}, +/*h(603)=25 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 4041}, +/*h(859)=26 EVV 0xCC V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 4041}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 31) % 28); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {10, 4046}, +/*h(15)=2 EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {15, 4044}, +/*h(12)=3 EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4045}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {14, 4043}, +/*h(11)=6 EVV 0xCD V66 V0F38 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {11, 4047}, +/*h(8)=7 EVV 0xCD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4048} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xcf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(42)=0 EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6978}, +/*h(8)=1 EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6977}, +/*h(72)=2 EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6981}, +/*h(10)=3 EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6976}, +/*h(74)=4 EVV 0xCF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6980}, +/*h(40)=5 EVV 0xCF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6979} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xdc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {10, 6995}, +/*h(78)=2 EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0*/ {78, 6998}, +/*empty slot1 */ {0,0}, +/*h(46)=4 EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0*/ {46, 6996}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0xDC V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0*/ {14, 6994}, +/*h(74)=7 EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {74, 6999}, +/*empty slot1 */ {0,0}, +/*h(42)=9 EVV 0xDC V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {42, 6997} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xdd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {10, 7001}, +/*h(78)=2 EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0*/ {78, 7004}, +/*empty slot1 */ {0,0}, +/*h(46)=4 EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0*/ {46, 7002}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0xDD V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0*/ {14, 7000}, +/*h(74)=7 EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {74, 7005}, +/*empty slot1 */ {0,0}, +/*h(42)=9 EVV 0xDD V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {42, 7003} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xde_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {10, 6983}, +/*h(78)=2 EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0*/ {78, 6986}, +/*empty slot1 */ {0,0}, +/*h(46)=4 EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0*/ {46, 6984}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0xDE V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0*/ {14, 6982}, +/*h(74)=7 EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {74, 6987}, +/*empty slot1 */ {0,0}, +/*h(42)=9 EVV 0xDE V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {42, 6985} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map2_opcode0xdf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {10, 6989}, +/*h(78)=2 EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0*/ {78, 6992}, +/*empty slot1 */ {0,0}, +/*h(46)=4 EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0*/ {46, 6990}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0xDF V66 V0F38 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0*/ {14, 6988}, +/*h(74)=7 EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {74, 6993}, +/*empty slot1 */ {0,0}, +/*h(42)=9 EVV 0xDF V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_128_BITS() NELEM_FULLMEM()*/ {42, 6991} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x0_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(348)=0 EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 5281}, +/*empty slot1 */ {0,0}, +/*h(604)=2 EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 5277}, +/*h(350)=3 EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 5280}, +/*empty slot1 */ {0,0}, +/*h(606)=5 EVV 0x00 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 5276}, +/*h(349)=6 EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 5281}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(605)=9 EVV 0x00 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 5277} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(348)=0 EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 5269}, +/*empty slot1 */ {0,0}, +/*h(604)=2 EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 5265}, +/*h(350)=3 EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 5268}, +/*empty slot1 */ {0,0}, +/*h(606)=5 EVV 0x01 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 5264}, +/*h(349)=6 EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 5269}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(605)=9 EVV 0x01 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 5265} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 4096}, +/*h(76)=1 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 4102}, +/*h(8)=2 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 4098}, +/*h(12)=3 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 4104}, +/*h(41)=4 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 4100}, +/*h(45)=5 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 4106}, +/*h(74)=6 EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 4095}, +/*h(78)=7 EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 4101}, +/*h(10)=8 EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 4097}, +/*h(14)=9 EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 4103}, +/*h(40)=10 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 4100}, +/*h(44)=11 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 4106}, +/*h(73)=12 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 4096}, +/*h(77)=13 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 4102}, +/*h(9)=14 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 4098}, +/*h(13)=15 EVV 0x03 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 4104}, +/*h(42)=16 EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 4099}, +/*h(46)=17 EVV 0x03 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 4105} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(89)=0 EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 5257}, +/*h(602)=1 EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 5252}, +/*empty slot1 */ {0,0}, +/*h(345)=3 EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 5261}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=6 EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 5257}, +/*h(601)=7 EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 5253}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=10 EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 5261}, +/*h(90)=11 EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {90, 5256}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=14 EVV 0x04 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 5253}, +/*h(346)=15 EVV 0x04 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 5260}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x5_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(94)=0 EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()*/ {94, 5244}, +/*h(350)=1 EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 5248}, +/*h(606)=2 EVV 0x05 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 5240}, +/*h(92)=3 EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {92, 5245}, +/*h(348)=4 EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 5249}, +/*h(604)=5 EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 5241}, +/*h(93)=6 EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {93, 5245}, +/*h(349)=7 EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 5249}, +/*h(605)=8 EVV 0x05 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 5241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 13) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[26] = { +/*h(601)=0 EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 5843}, +/*h(538)=1 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {538, 7567}, +/*h(603)=2 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {603, 5842}, +/*h(344)=3 EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 5847}, +/*h(281)=4 EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {281, 7566}, +/*h(346)=5 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 5846}, +/*h(283)=6 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {283, 7568}, +/*h(24)=7 EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {24, 7564}, +/*h(89)=8 EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 5845}, +/*h(26)=9 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {26, 7563}, +/*h(91)=10 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {91, 5842}, +/*h(859)=11 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {859, 5842}, +/*h(600)=12 EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 5843}, +/*h(537)=13 EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {537, 7569}, +/*h(602)=14 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 5841}, +/*h(539)=15 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {539, 7568}, +/*h(280)=16 EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {280, 7566}, +/*h(345)=17 EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 5847}, +/*h(282)=18 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {282, 7565}, +/*h(347)=19 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {347, 5842}, +/*h(88)=20 EVV 0x08 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 5845}, +/*h(25)=21 EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {25, 7564}, +/*h(90)=22 EVV 0x08 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {90, 5844}, +/*h(27)=23 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {27, 7568}, +/*h(795)=24 EVV 0x08 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {795, 7568}, +/*h(536)=25 EVV 0x08 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {536, 7569} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((14*key % 277) % 26); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[23] = { +/*empty slot1 */ {0,0}, +/*h(348)=1 EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 5840}, +/*h(94)=2 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()*/ {94, 5837}, +/*h(607)=3 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {607, 5835}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=6 EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 5836}, +/*h(350)=7 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 5839}, +/*h(863)=8 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {863, 5835}, +/*empty slot1 */ {0,0}, +/*h(93)=10 EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {93, 5838}, +/*empty slot1 */ {0,0}, +/*h(606)=12 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 5834}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(349)=15 EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 5840}, +/*h(95)=16 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {95, 5835}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=19 EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {92, 5838}, +/*h(605)=20 EVV 0x09 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 5836}, +/*h(351)=21 EVV 0x09 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {351, 5835}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 23ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xa_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(0)=0 EVV 0x0A VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {0, 7572}, +/*h(10)=1 EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()*/ {10, 5851}, +/*h(2)=2 EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8()*/ {2, 7570}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=7 EVV 0x0A V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {11, 5852}, +/*h(3)=8 EVV 0x0A VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {3, 7571}, +/*h(8)=9 EVV 0x0A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 5853} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0,0}, +/*h(15)=1 EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()*/ {15, 5849}, +/*h(12)=2 EVV 0x0B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 5850}, +/*h(14)=3 EVV 0x0B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()*/ {14, 5848}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 UIMM8()*/ {22, 6310}, +/*h(4)=1 EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()*/ {4, 6309}, +/*h(38)=2 EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 UIMM8()*/ {38, 6312}, +/*h(20)=3 EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()*/ {20, 6311}, +/*h(6)=4 EVV 0x0F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 UIMM8()*/ {6, 6308}, +/*h(36)=5 EVV 0x0F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()*/ {36, 6313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x14_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 EVV 0x14 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {94, 6422}, +/*h(90)=1 EVV 0x14 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_WRITER_STORE_BYTE()*/ {90, 6423} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x15_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 EVV 0x15 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {94, 6430}, +/*h(90)=1 EVV 0x15 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_WRITER_STORE_WORD()*/ {90, 6431} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x16_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(746)=0 EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {746, 6426}, +/*h(738)=1 EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {738, 6426}, +/*empty slot1 */ {0,0}, +/*h(722)=3 EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {722, 6427}, +/*h(714)=4 EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {714, 6426}, +/*h(706)=5 EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {706, 6426}, +/*empty slot1 */ {0,0}, +/*h(758)=7 EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {758, 6428}, +/*h(750)=8 EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {750, 6424}, +/*h(742)=9 EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {742, 6424}, +/*empty slot1 */ {0,0}, +/*h(726)=11 EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {726, 6425}, +/*h(718)=12 EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {718, 6424}, +/*h(710)=13 EVV 0x16 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {710, 6424}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(754)=16 EVV 0x16 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_WRITER_STORE()*/ {754, 6429} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x17_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 EVV 0x17 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8()*/ {94, 4439}, +/*h(90)=1 EVV 0x17 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {90, 4440} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x18_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(42)=0 EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 4839}, +/*h(78)=1 EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6192}, +/*h(40)=2 EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {40, 4840}, +/*h(76)=3 EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {76, 6193}, +/*h(46)=4 EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6190}, +/*h(74)=5 EVV 0x18 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 4837}, +/*h(44)=6 EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {44, 6191}, +/*h(72)=7 EVV 0x18 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {72, 4838} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((28*key % 29) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x19_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(602)=0 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 4427}, +/*h(348)=1 EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {348, 6163}, +/*empty slot1 */ {0,0}, +/*h(1374)=3 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {1374, 6162}, +/*h(604)=4 EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {604, 6165}, +/*h(350)=5 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 6162}, +/*h(1630)=6 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {1630, 6164}, +/*empty slot1 */ {0,0}, +/*h(606)=8 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 6164}, +/*empty slot1 */ {0,0}, +/*h(344)=10 EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {344, 4430}, +/*empty slot1 */ {0,0}, +/*h(1370)=12 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {1370, 4429}, +/*h(600)=13 EVV 0x19 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {600, 4428}, +/*h(346)=14 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 4429}, +/*h(1626)=15 EVV 0x19 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {1626, 4427}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(78)=0 EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 4841}, +/*h(72)=1 EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()*/ {72, 6189}, +/*h(74)=2 EVV 0x1A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 6188}, +/*h(76)=3 EVV 0x1A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()*/ {76, 4842} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(602)=0 EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 6160}, +/*h(604)=1 EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()*/ {604, 4432}, +/*h(1630)=2 EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {1630, 4431}, +/*h(606)=3 EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 4431}, +/*h(600)=4 EVV 0x1B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()*/ {600, 6161}, +/*h(1626)=5 EVV 0x1B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {1626, 6160} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[23] = { +/*empty slot1 */ {0,0}, +/*h(602)=1 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 4229}, +/*h(1115)=2 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {1115, 4230}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=5 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {91, 4230}, +/*empty slot1 */ {0,0}, +/*h(1371)=7 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {1371, 4230}, +/*h(88)=8 EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()*/ {88, 4233}, +/*empty slot1 */ {0,0}, +/*h(347)=10 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {347, 4230}, +/*h(1114)=11 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {1114, 4232}, +/*h(1627)=12 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {1627, 4230}, +/*h(344)=13 EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()*/ {344, 4235}, +/*h(90)=14 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {90, 4232}, +/*h(603)=15 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {603, 4230}, +/*h(1370)=16 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {1370, 4234}, +/*h(1883)=17 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {1883, 4230}, +/*h(600)=18 EVV 0x1D V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_HALFMEM()*/ {600, 4231}, +/*h(346)=19 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 4234}, +/*h(859)=20 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {859, 4230}, +/*h(1626)=21 EVV 0x1D V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {1626, 4229}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 23ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 5189}, +/*h(76)=1 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 5195}, +/*h(8)=2 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 5191}, +/*h(12)=3 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 5197}, +/*h(41)=4 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 5193}, +/*h(45)=5 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 5199}, +/*h(74)=6 EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()*/ {74, 5188}, +/*h(78)=7 EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()*/ {78, 5194}, +/*h(10)=8 EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()*/ {10, 5190}, +/*h(14)=9 EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()*/ {14, 5196}, +/*h(40)=10 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 5193}, +/*h(44)=11 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 5199}, +/*h(73)=12 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 5189}, +/*h(77)=13 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 5195}, +/*h(9)=14 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 5191}, +/*h(13)=15 EVV 0x1E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 5197}, +/*h(42)=16 EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()*/ {42, 5192}, +/*h(46)=17 EVV 0x1E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()*/ {46, 5198} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x1f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 5153}, +/*h(76)=1 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 5183}, +/*h(8)=2 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 5155}, +/*h(12)=3 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 5185}, +/*h(41)=4 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 5157}, +/*h(45)=5 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 5187}, +/*h(74)=6 EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()*/ {74, 5152}, +/*h(78)=7 EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()*/ {78, 5182}, +/*h(10)=8 EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()*/ {10, 5154}, +/*h(14)=9 EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()*/ {14, 5184}, +/*h(40)=10 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 5157}, +/*h(44)=11 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 5187}, +/*h(73)=12 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 5153}, +/*h(77)=13 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 5183}, +/*h(9)=14 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 5155}, +/*h(13)=15 EVV 0x1F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 5185}, +/*h(42)=16 EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()*/ {42, 5156}, +/*h(46)=17 EVV 0x1F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()*/ {46, 5186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x20_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 EVV 0x20 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_GPR_READER_BYTE()*/ {10, 6435}, +/*h(14)=1 EVV 0x20 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {14, 6434} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x21_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(18)=0 EVV 0x21 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE1()*/ {18, 4850}, +/*h(22)=1 EVV 0x21 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0 UIMM8()*/ {22, 4849} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x22_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(102)=0 EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8()*/ {102, 6436}, +/*empty slot1 */ {0,0}, +/*h(86)=2 EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8()*/ {86, 6437}, +/*h(78)=3 EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8()*/ {78, 6436}, +/*h(70)=4 EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8()*/ {70, 6436}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(114)=7 EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_GPR_READER()*/ {114, 6441}, +/*h(106)=8 EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()*/ {106, 6438}, +/*h(98)=9 EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()*/ {98, 6438}, +/*h(82)=10 EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()*/ {82, 6439}, +/*h(74)=11 EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()*/ {74, 6438}, +/*h(66)=12 EVV 0x22 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 ZEROING=0 MASK=0 UIMM8() ESIZE_32_BITS() NELEM_GPR_READER()*/ {66, 6438}, +/*empty slot1 */ {0,0}, +/*h(118)=14 EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 ZEROING=0 MASK=0 UIMM8()*/ {118, 6440}, +/*h(110)=15 EVV 0x22 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 ZEROING=0 MASK=0 UIMM8()*/ {110, 6436} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-4)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x23_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 5908}, +/*h(73)=1 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 5903}, +/*h(77)=2 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 5907}, +/*h(41)=3 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 5905}, +/*h(45)=4 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 5909}, +/*h(72)=5 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 5903}, +/*h(76)=6 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 5907}, +/*h(40)=7 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 5905}, +/*h(44)=8 EVV 0x23 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 5909}, +/*h(74)=9 EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 5902}, +/*h(78)=10 EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 5906}, +/*h(42)=11 EVV 0x23 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 5904} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 43) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x25_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 5747}, +/*h(76)=1 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 5753}, +/*h(8)=2 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 5749}, +/*h(12)=3 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 5755}, +/*h(41)=4 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 5751}, +/*h(45)=5 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 5757}, +/*h(74)=6 EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 5746}, +/*h(78)=7 EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 5752}, +/*h(10)=8 EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 5748}, +/*h(14)=9 EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 5754}, +/*h(40)=10 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 5751}, +/*h(44)=11 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 5757}, +/*h(73)=12 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 5747}, +/*h(77)=13 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 5753}, +/*h(9)=14 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 5749}, +/*h(13)=15 EVV 0x25 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 5755}, +/*h(42)=16 EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 5750}, +/*h(46)=17 EVV 0x25 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 5756} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x26_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[78] = { +/*h(26)=0 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {26, 7497}, +/*h(606)=1 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 4817}, +/*h(27)=2 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {27, 7502}, +/*empty slot1 */ {0,0}, +/*h(607)=4 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {607, 4818}, +/*h(344)=5 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 4830}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=8 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 4830}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(346)=11 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 4829}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(347)=14 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {347, 4825}, +/*h(795)=15 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {795, 7502}, +/*empty slot1 */ {0,0}, +/*h(348)=17 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 4823}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(349)=20 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 4823}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=23 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 4822}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(351)=26 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {351, 4818}, +/*h(88)=27 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 4828}, +/*h(536)=28 EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {536, 7503}, +/*empty slot1 */ {0,0}, +/*h(89)=30 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 4828}, +/*h(537)=31 EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {537, 7503}, +/*empty slot1 */ {0,0}, +/*h(90)=33 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {90, 4827}, +/*h(538)=34 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {538, 7501}, +/*empty slot1 */ {0,0}, +/*h(91)=36 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {91, 4825}, +/*h(539)=37 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {539, 7502}, +/*empty slot1 */ {0,0}, +/*h(92)=39 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {92, 4821}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(93)=42 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {93, 4821}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=45 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()*/ {94, 4820}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(95)=48 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {95, 4818}, +/*h(859)=49 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {859, 4825}, +/*h(280)=50 EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {280, 7500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(281)=53 EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {281, 7500}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(282)=56 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {282, 7499}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(283)=59 EVV 0x26 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {283, 7502}, +/*empty slot1 */ {0,0}, +/*h(863)=61 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {863, 4818}, +/*h(600)=62 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 4826}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(601)=65 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 4826}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(602)=68 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 4824}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=71 EVV 0x26 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {603, 4825}, +/*h(24)=72 EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {24, 7498}, +/*empty slot1 */ {0,0}, +/*h(604)=74 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 4819}, +/*h(25)=75 EVV 0x26 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {25, 7498}, +/*empty slot1 */ {0,0}, +/*h(605)=77 EVV 0x26 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 4819} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 79) % 78); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x27_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(0)=0 EVV 0x27 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {0, 7506}, +/*empty slot1 */ {0,0}, +/*h(10)=2 EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()*/ {10, 4834}, +/*h(2)=3 EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8()*/ {2, 7504}, +/*h(15)=4 EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()*/ {15, 4832}, +/*empty slot1 */ {0,0}, +/*h(12)=6 EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4833}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=9 EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()*/ {14, 4831}, +/*empty slot1 */ {0,0}, +/*h(11)=11 EVV 0x27 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {11, 4835}, +/*h(3)=12 EVV 0x27 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {3, 7505}, +/*empty slot1 */ {0,0}, +/*h(8)=14 EVV 0x27 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4836} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x38_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(42)=0 EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 4845}, +/*h(78)=1 EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6198}, +/*h(40)=2 EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {40, 4846}, +/*h(76)=3 EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {76, 6199}, +/*h(46)=4 EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6196}, +/*h(74)=5 EVV 0x38 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 4843}, +/*h(44)=6 EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {44, 6197}, +/*h(72)=7 EVV 0x38 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {72, 4844} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((28*key % 29) % 8); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x39_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(602)=0 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 4433}, +/*h(348)=1 EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {348, 6169}, +/*empty slot1 */ {0,0}, +/*h(1374)=3 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {1374, 6168}, +/*h(604)=4 EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE2()*/ {604, 6171}, +/*h(350)=5 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 6168}, +/*h(1630)=6 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {1630, 6170}, +/*empty slot1 */ {0,0}, +/*h(606)=8 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 6170}, +/*empty slot1 */ {0,0}, +/*h(344)=10 EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {344, 4436}, +/*empty slot1 */ {0,0}, +/*h(1370)=12 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {1370, 4435}, +/*h(600)=13 EVV 0x39 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE4()*/ {600, 4434}, +/*h(346)=14 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 4435}, +/*h(1626)=15 EVV 0x39 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {1626, 4433}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(78)=0 EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 4847}, +/*h(72)=1 EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()*/ {72, 6195}, +/*h(74)=2 EVV 0x3A V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 6194}, +/*h(76)=3 EVV 0x3A V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()*/ {76, 4848} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(602)=0 EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 6166}, +/*h(604)=1 EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_TUPLE4()*/ {604, 4438}, +/*h(1630)=2 EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {1630, 4437}, +/*h(606)=3 EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 4437}, +/*h(600)=4 EVV 0x3B V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_TUPLE8()*/ {600, 6167}, +/*h(1626)=5 EVV 0x3B V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {1626, 6166} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()*/ {46, 6394}, +/*h(72)=1 EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6391}, +/*h(42)=2 EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()*/ {42, 6388}, +/*h(78)=3 EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()*/ {78, 6396}, +/*h(12)=4 EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6393}, +/*h(74)=5 EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()*/ {74, 6390}, +/*h(8)=6 EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6387}, +/*h(44)=7 EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6395}, +/*h(14)=8 EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()*/ {14, 6392}, +/*h(40)=9 EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6389}, +/*h(76)=10 EVV 0x3E V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6397}, +/*h(10)=11 EVV 0x3E V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()*/ {10, 6386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x3f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()*/ {46, 6400}, +/*h(72)=1 EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {72, 6361}, +/*h(42)=2 EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()*/ {42, 6358}, +/*h(78)=3 EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()*/ {78, 6402}, +/*h(12)=4 EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6399}, +/*h(74)=5 EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()*/ {74, 6360}, +/*h(8)=6 EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {8, 6357}, +/*h(44)=7 EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6401}, +/*h(14)=8 EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()*/ {14, 6398}, +/*h(40)=9 EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {40, 6359}, +/*h(76)=10 EVV 0x3F V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6403}, +/*h(10)=11 EVV 0x3F V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()*/ {10, 6356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x42_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(42)=0 EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 6156}, +/*h(8)=1 EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {8, 6155}, +/*h(72)=2 EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {72, 6159}, +/*h(10)=3 EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 6154}, +/*h(74)=4 EVV 0x42 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 6158}, +/*h(40)=5 EVV 0x42 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {40, 6157} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x43_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 5916}, +/*h(73)=1 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 5911}, +/*h(77)=2 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 5915}, +/*h(41)=3 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 5913}, +/*h(45)=4 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 5917}, +/*h(72)=5 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 5911}, +/*h(76)=6 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 5915}, +/*h(40)=7 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 5913}, +/*h(44)=8 EVV 0x43 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 5917}, +/*h(74)=9 EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 5910}, +/*h(78)=10 EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 5914}, +/*h(42)=11 EVV 0x43 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 5912} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 43) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x44_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()*/ {10, 7007}, +/*h(78)=2 EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()*/ {78, 7010}, +/*empty slot1 */ {0,0}, +/*h(46)=4 EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()*/ {46, 7008}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0x44 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {14, 7006}, +/*h(74)=7 EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()*/ {74, 7011}, +/*empty slot1 */ {0,0}, +/*h(42)=9 EVV 0x44 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_64_BITS() NELEM_FULLMEM()*/ {42, 7009} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x50_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 6772}, +/*h(14)=1 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6762}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 6771}, +/*h(15)=4 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {15, 6767}, +/*h(111)=5 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {111, 6767}, +/*h(43)=6 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {43, 6774}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 6765}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 6775}, +/*h(45)=12 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 6765}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 6775}, +/*h(46)=15 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6764}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 6773}, +/*h(47)=18 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {47, 6767}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {75, 6774}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 6768}, +/*h(8)=24 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 6770}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 6768}, +/*h(9)=27 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 6770}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6766}, +/*h(10)=30 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 6769}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {79, 6767}, +/*h(11)=33 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {11, 6774}, +/*h(107)=34 EVV 0x50 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {107, 6774}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 6763}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 6772}, +/*h(13)=39 EVV 0x50 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 6763}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x51_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()*/ {10, 6779}, +/*h(15)=2 EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()*/ {15, 6777}, +/*h(12)=3 EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 6778}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()*/ {14, 6776}, +/*h(11)=6 EVV 0x51 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {11, 6780}, +/*h(8)=7 EVV 0x51 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 6781} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x54_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[41] = { +/*h(41)=0 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 4454}, +/*h(14)=1 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 4444}, +/*empty slot1 */ {0,0}, +/*h(42)=3 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 4453}, +/*h(15)=4 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {15, 4442}, +/*h(111)=5 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {111, 4442}, +/*h(43)=6 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {43, 4449}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=9 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 4447}, +/*empty slot1 */ {0,0}, +/*h(72)=11 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 4450}, +/*h(45)=12 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 4447}, +/*empty slot1 */ {0,0}, +/*h(73)=14 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 4450}, +/*h(46)=15 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 4446}, +/*empty slot1 */ {0,0}, +/*h(74)=17 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 4448}, +/*h(47)=18 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {47, 4442}, +/*empty slot1 */ {0,0}, +/*h(75)=20 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {75, 4449}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=23 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 4443}, +/*h(8)=24 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 4452}, +/*empty slot1 */ {0,0}, +/*h(77)=26 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 4443}, +/*h(9)=27 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 4452}, +/*empty slot1 */ {0,0}, +/*h(78)=29 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 4441}, +/*h(10)=30 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 4451}, +/*empty slot1 */ {0,0}, +/*h(79)=32 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 UIMM8()*/ {79, 4442}, +/*h(11)=33 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {11, 4449}, +/*h(107)=34 EVV 0x54 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 UIMM8()*/ {107, 4449}, +/*empty slot1 */ {0,0}, +/*h(12)=36 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 4445}, +/*empty slot1 */ {0,0}, +/*h(40)=38 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 4454}, +/*h(13)=39 EVV 0x54 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 4445}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 41); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x55_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()*/ {10, 4458}, +/*h(15)=2 EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()*/ {15, 4456}, +/*h(12)=3 EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 4457}, +/*empty slot1 */ {0,0}, +/*h(14)=5 EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()*/ {14, 4455}, +/*h(11)=6 EVV 0x55 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {11, 4459}, +/*h(8)=7 EVV 0x55 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 4460} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x56_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[78] = { +/*h(26)=0 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {26, 7553}, +/*h(606)=1 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR UIMM8()*/ {606, 6786}, +/*h(27)=2 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {27, 7558}, +/*empty slot1 */ {0,0}, +/*h(607)=4 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {607, 6787}, +/*h(344)=5 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 6792}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=8 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 6792}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(346)=11 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 6791}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(347)=14 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {347, 6794}, +/*h(795)=15 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {795, 7558}, +/*empty slot1 */ {0,0}, +/*h(348)=17 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 6785}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(349)=20 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 6785}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(350)=23 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR UIMM8()*/ {350, 6784}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(351)=26 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {351, 6787}, +/*h(88)=27 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 6790}, +/*h(536)=28 EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {536, 7559}, +/*empty slot1 */ {0,0}, +/*h(89)=30 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 6790}, +/*h(537)=31 EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {537, 7559}, +/*empty slot1 */ {0,0}, +/*h(90)=33 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {90, 6789}, +/*h(538)=34 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {538, 7557}, +/*empty slot1 */ {0,0}, +/*h(91)=36 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {91, 6794}, +/*h(539)=37 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {539, 7558}, +/*empty slot1 */ {0,0}, +/*h(92)=39 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {92, 6783}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(93)=42 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {93, 6783}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=45 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR UIMM8()*/ {94, 6782}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(95)=48 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {95, 6787}, +/*h(859)=49 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {859, 6794}, +/*h(280)=50 EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {280, 7556}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(281)=53 EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {281, 7556}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(282)=56 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {282, 7555}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(283)=59 EVV 0x56 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {283, 7558}, +/*empty slot1 */ {0,0}, +/*h(863)=61 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR UIMM8()*/ {863, 6787}, +/*h(600)=62 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 6795}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(601)=65 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 6795}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(602)=68 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 6793}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=71 EVV 0x56 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR UIMM8()*/ {603, 6794}, +/*h(24)=72 EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {24, 7554}, +/*empty slot1 */ {0,0}, +/*h(604)=74 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 6788}, +/*h(25)=75 EVV 0x56 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {25, 7554}, +/*empty slot1 */ {0,0}, +/*h(605)=77 EVV 0x56 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 6788} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 79) % 78); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x57_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(0)=0 EVV 0x57 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {0, 7562}, +/*empty slot1 */ {0,0}, +/*h(10)=2 EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 UIMM8()*/ {10, 6799}, +/*h(2)=3 EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 UIMM8()*/ {2, 7560}, +/*h(15)=4 EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 UIMM8()*/ {15, 6797}, +/*empty slot1 */ {0,0}, +/*h(12)=6 EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {12, 6798}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=9 EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 UIMM8()*/ {14, 6796}, +/*empty slot1 */ {0,0}, +/*h(11)=11 EVV 0x57 V66 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {11, 6800}, +/*h(3)=12 EVV 0x57 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 UIMM8()*/ {3, 7561}, +/*empty slot1 */ {0,0}, +/*h(8)=14 EVV 0x57 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 6801} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x66_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[54] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=13 EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {24, 7480}, +/*h(280)=14 EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {280, 7482}, +/*h(536)=15 EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {536, 7484}, +/*h(25)=16 EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {25, 7480}, +/*h(281)=17 EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {281, 7482}, +/*h(537)=18 EVV 0x66 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {537, 7484}, +/*h(26)=19 EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8()*/ {26, 7479}, +/*h(282)=20 EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8()*/ {282, 7481}, +/*h(538)=21 EVV 0x66 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8()*/ {538, 7483}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=28 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 6179}, +/*h(344)=29 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 6181}, +/*h(600)=30 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 6183}, +/*h(89)=31 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 6179}, +/*h(345)=32 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 6181}, +/*h(601)=33 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 6183}, +/*h(90)=34 EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR ZEROING=0 UIMM8()*/ {90, 6178}, +/*h(346)=35 EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR ZEROING=0 UIMM8()*/ {346, 6180}, +/*h(602)=36 EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR ZEROING=0 UIMM8()*/ {602, 6182}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=40 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {92, 6173}, +/*h(348)=41 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {348, 6175}, +/*h(604)=42 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {604, 6177}, +/*h(93)=43 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {93, 6173}, +/*h(349)=44 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {349, 6175}, +/*h(605)=45 EVV 0x66 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {605, 6177}, +/*h(94)=46 EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 UIMM8()*/ {94, 6172}, +/*h(350)=47 EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR ZEROING=0 UIMM8()*/ {350, 6174}, +/*h(606)=48 EVV 0x66 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR ZEROING=0 UIMM8()*/ {606, 6176}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 59) % 54); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x67_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(26)=0 EVV 0x67 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8()*/ {26, 7485}, +/*h(94)=1 EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 UIMM8()*/ {94, 6184}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=4 EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 6187}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=7 EVV 0x67 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 UIMM8()*/ {90, 6186}, +/*empty slot1 */ {0,0}, +/*h(24)=9 EVV 0x67 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7486}, +/*h(92)=10 EVV 0x67 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {92, 6185}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x70_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(14)=0 EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6922}, +/*h(46)=1 EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6924}, +/*h(78)=2 EVV 0x70 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6926}, +/*h(12)=3 EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6923}, +/*h(44)=4 EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6925}, +/*h(76)=5 EVV 0x70 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6927} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x71_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 6897}, +/*h(76)=1 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 6903}, +/*h(8)=2 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 6893}, +/*h(12)=3 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 6899}, +/*h(41)=4 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 6895}, +/*h(45)=5 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 6901}, +/*h(74)=6 EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 6896}, +/*h(78)=7 EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6902}, +/*h(10)=8 EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 6892}, +/*h(14)=9 EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6898}, +/*h(40)=10 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 6895}, +/*h(44)=11 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 6901}, +/*h(73)=12 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 6897}, +/*h(77)=13 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 6903}, +/*h(9)=14 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 6893}, +/*h(13)=15 EVV 0x71 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 6899}, +/*h(42)=16 EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 6894}, +/*h(46)=17 EVV 0x71 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6900} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x72_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(14)=0 EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6958}, +/*h(46)=1 EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6960}, +/*h(78)=2 EVV 0x72 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6962}, +/*h(12)=3 EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {12, 6959}, +/*h(44)=4 EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {44, 6961}, +/*h(76)=5 EVV 0x72 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {76, 6963} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0x73_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 6933}, +/*h(76)=1 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 6939}, +/*h(8)=2 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {8, 6929}, +/*h(12)=3 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 6935}, +/*h(41)=4 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {41, 6931}, +/*h(45)=5 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 6937}, +/*h(74)=6 EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {74, 6932}, +/*h(78)=7 EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6938}, +/*h(10)=8 EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {10, 6928}, +/*h(14)=9 EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6934}, +/*h(40)=10 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {40, 6931}, +/*h(44)=11 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 6937}, +/*h(73)=12 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 6933}, +/*h(77)=13 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 6939}, +/*h(9)=14 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {9, 6929}, +/*h(13)=15 EVV 0x73 V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 6935}, +/*h(42)=16 EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {42, 6930}, +/*h(46)=17 EVV 0x73 V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6936} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xc2_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {0, 7035}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7043}, +/*h(32)=4 EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {32, 7037}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7043}, +/*h(64)=8 EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {64, 7040}, +/*h(1)=9 EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {1, 7035}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7043}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {33, 7037}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0xC2 VF3 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7043}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0xC2 VNP V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_16_BITS() NELEM_FULL()*/ {65, 7040}, +/*h(2)=18 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()*/ {2, 7034}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8()*/ {26, 7041}, +/*h(34)=22 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()*/ {34, 7036}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8()*/ {58, 7041}, +/*h(66)=26 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()*/ {66, 7038}, +/*h(3)=27 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {3, 7039}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8()*/ {90, 7041}, +/*h(27)=30 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {27, 7042}, +/*h(35)=31 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {35, 7039}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 ZEROING=0 UIMM8()*/ {122, 7041}, +/*h(59)=34 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {59, 7042}, +/*h(67)=35 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {67, 7039}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {91, 7042}, +/*h(99)=39 EVV 0xC2 VNP V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {99, 7039}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0xC2 VF3 V0F3A MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {123, 7042}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xce_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 6975}, +/*h(46)=1 EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6972}, +/*h(12)=2 EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 6971}, +/*h(77)=3 EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 6975}, +/*h(13)=4 EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 6971}, +/*h(78)=5 EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6974}, +/*h(44)=6 EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 6973}, +/*h(14)=7 EVV 0xCE V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6970}, +/*h(45)=8 EVV 0xCE V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 6973} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map3_opcode0xcf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 6969}, +/*h(46)=1 EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 6966}, +/*h(12)=2 EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 6965}, +/*h(77)=3 EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 6969}, +/*h(13)=4 EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 6965}, +/*h(78)=5 EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 6968}, +/*h(44)=6 EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 6967}, +/*h(14)=7 EVV 0xCF V66 V0F3A MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 6964}, +/*h(45)=8 EVV 0xCF V66 V0F3A MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 6967} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x10_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=8 EVV 0x10 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ESIZE_16_BITS() NELEM_SCALAR()*/ {216, 7527}, +/*h(250)=9 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {250, 7529}, +/*h(242)=10 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {242, 7529}, +/*h(234)=11 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {234, 7529}, +/*h(226)=12 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {226, 7529}, +/*h(218)=13 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {218, 7529}, +/*h(210)=14 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {210, 7529}, +/*h(202)=15 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {202, 7529}, +/*h(194)=16 EVV 0x10 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {194, 7529}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x11_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(202)=0 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {202, 7530}, +/*h(506)=1 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {506, 7530}, +/*h(482)=2 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {482, 7530}, +/*h(458)=3 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {458, 7530}, +/*h(242)=4 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {242, 7530}, +/*h(218)=5 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {218, 7530}, +/*h(194)=6 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {194, 7530}, +/*h(498)=7 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {498, 7530}, +/*h(474)=8 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {474, 7530}, +/*h(450)=9 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {450, 7530}, +/*h(234)=10 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {234, 7530}, +/*h(210)=11 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {210, 7530}, +/*h(216)=12 EVV 0x11 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_SCALAR()*/ {216, 7528}, +/*h(490)=13 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {490, 7530}, +/*h(466)=14 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {466, 7530}, +/*h(250)=15 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {250, 7530}, +/*h(226)=16 EVV 0x11 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {226, 7530} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((20*key % 149) % 17); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x1d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[218] = { +/*h(0)=0 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {0, 7169}, +/*h(539)=1 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {539, 7168}, +/*empty slot1 */ {0,0}, +/*h(787)=3 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {787, 7168}, +/*h(88)=4 EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 7118}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(89)=9 EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 7118}, +/*h(2)=10 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {2, 7167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=14 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7117}, +/*h(3)=15 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {3, 7168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=19 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {91, 7122}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(48)=22 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {48, 7169}, +/*empty slot1 */ {0,0}, +/*h(296)=24 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {296, 7169}, +/*empty slot1 */ {0,0}, +/*h(544)=26 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {544, 7169}, +/*empty slot1 */ {0,0}, +/*h(792)=28 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {792, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(50)=32 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {50, 7167}, +/*empty slot1 */ {0,0}, +/*h(298)=34 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {298, 7167}, +/*empty slot1 */ {0,0}, +/*h(546)=36 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {546, 7167}, +/*h(51)=37 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {51, 7168}, +/*h(794)=38 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {794, 7167}, +/*h(299)=39 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {299, 7168}, +/*h(8)=40 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {8, 7169}, +/*h(547)=41 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {547, 7168}, +/*h(256)=42 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {256, 7169}, +/*h(795)=43 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {795, 7168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=46 EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 7120}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(10)=50 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7167}, +/*h(345)=51 EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 7120}, +/*h(258)=52 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {258, 7167}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=55 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7168}, +/*h(346)=56 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7119}, +/*h(259)=57 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {259, 7168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(347)=61 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {347, 7122}, +/*h(56)=62 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 7169}, +/*empty slot1 */ {0,0}, +/*h(304)=64 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {304, 7169}, +/*empty slot1 */ {0,0}, +/*h(552)=66 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {552, 7169}, +/*empty slot1 */ {0,0}, +/*h(800)=68 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {800, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=72 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7167}, +/*empty slot1 */ {0,0}, +/*h(306)=74 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {306, 7167}, +/*empty slot1 */ {0,0}, +/*h(554)=76 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {554, 7167}, +/*h(59)=77 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 7168}, +/*h(802)=78 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {802, 7167}, +/*h(307)=79 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {307, 7168}, +/*h(16)=80 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {16, 7169}, +/*h(555)=81 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {555, 7168}, +/*h(264)=82 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {264, 7169}, +/*h(803)=83 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {803, 7168}, +/*h(512)=84 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {512, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=88 EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 7123}, +/*empty slot1 */ {0,0}, +/*h(18)=90 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {18, 7167}, +/*empty slot1 */ {0,0}, +/*h(266)=92 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {266, 7167}, +/*h(601)=93 EVV 0x1D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 7123}, +/*h(514)=94 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {514, 7167}, +/*h(19)=95 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {19, 7168}, +/*empty slot1 */ {0,0}, +/*h(267)=97 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {267, 7168}, +/*h(602)=98 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7121}, +/*h(515)=99 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {515, 7168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=103 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {603, 7122}, +/*h(312)=104 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {312, 7169}, +/*empty slot1 */ {0,0}, +/*h(560)=106 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {560, 7169}, +/*empty slot1 */ {0,0}, +/*h(808)=108 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {808, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(314)=114 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {314, 7167}, +/*empty slot1 */ {0,0}, +/*h(562)=116 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {562, 7167}, +/*empty slot1 */ {0,0}, +/*h(810)=118 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {810, 7167}, +/*h(315)=119 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {315, 7168}, +/*h(24)=120 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 7169}, +/*h(563)=121 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {563, 7168}, +/*h(272)=122 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {272, 7169}, +/*h(811)=123 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {811, 7168}, +/*h(520)=124 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {520, 7169}, +/*empty slot1 */ {0,0}, +/*h(768)=126 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {768, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=130 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7167}, +/*empty slot1 */ {0,0}, +/*h(274)=132 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {274, 7167}, +/*empty slot1 */ {0,0}, +/*h(522)=134 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {522, 7167}, +/*h(27)=135 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7168}, +/*h(770)=136 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {770, 7167}, +/*h(275)=137 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {275, 7168}, +/*empty slot1 */ {0,0}, +/*h(523)=139 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {523, 7168}, +/*empty slot1 */ {0,0}, +/*h(771)=141 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {771, 7168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(859)=145 EVV 0x1D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {859, 7122}, +/*h(568)=146 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {568, 7169}, +/*empty slot1 */ {0,0}, +/*h(816)=148 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {816, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(570)=156 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {570, 7167}, +/*empty slot1 */ {0,0}, +/*h(818)=158 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {818, 7167}, +/*empty slot1 */ {0,0}, +/*h(32)=160 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {32, 7169}, +/*h(571)=161 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {571, 7168}, +/*h(280)=162 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {280, 7169}, +/*h(819)=163 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {819, 7168}, +/*h(528)=164 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {528, 7169}, +/*empty slot1 */ {0,0}, +/*h(776)=166 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {776, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(34)=170 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {34, 7167}, +/*empty slot1 */ {0,0}, +/*h(282)=172 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {282, 7167}, +/*empty slot1 */ {0,0}, +/*h(530)=174 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {530, 7167}, +/*h(35)=175 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {35, 7168}, +/*h(778)=176 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {778, 7167}, +/*h(283)=177 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {283, 7168}, +/*empty slot1 */ {0,0}, +/*h(531)=179 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {531, 7168}, +/*empty slot1 */ {0,0}, +/*h(779)=181 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {779, 7168}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(824)=188 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {824, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(826)=198 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {826, 7167}, +/*empty slot1 */ {0,0}, +/*h(40)=200 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {40, 7169}, +/*empty slot1 */ {0,0}, +/*h(288)=202 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {288, 7169}, +/*h(827)=203 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {827, 7168}, +/*h(536)=204 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {536, 7169}, +/*empty slot1 */ {0,0}, +/*h(784)=206 EVV 0x1D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {784, 7169}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(42)=210 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {42, 7167}, +/*empty slot1 */ {0,0}, +/*h(290)=212 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {290, 7167}, +/*empty slot1 */ {0,0}, +/*h(538)=214 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {538, 7167}, +/*h(43)=215 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {43, 7168}, +/*h(786)=216 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {786, 7167}, +/*h(291)=217 EVV 0x1D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {291, 7168} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 619) % 218); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[27] = { +/*h(246)=0 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {246, 7164}, +/*empty slot1 */ {0,0}, +/*h(238)=2 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {238, 7161}, +/*h(230)=3 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {230, 7161}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(214)=7 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {214, 7158}, +/*h(206)=8 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {206, 7161}, +/*empty slot1 */ {0,0}, +/*h(198)=10 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {198, 7161}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(242)=15 EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {242, 7166}, +/*h(234)=16 EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {234, 7163}, +/*h(247)=17 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {247, 7165}, +/*h(226)=18 EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {226, 7163}, +/*h(239)=19 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {239, 7162}, +/*h(231)=20 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {231, 7162}, +/*h(210)=21 EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {210, 7160}, +/*h(202)=22 EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {202, 7163}, +/*h(215)=23 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {215, 7159}, +/*h(194)=24 EVV 0x2A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {194, 7163}, +/*h(207)=25 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {207, 7162}, +/*h(199)=26 EVV 0x2A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {199, 7162} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 27ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(3522)=0 EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3522, 7217}, +/*h(3479)=1 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 7213}, +/*h(3542)=2 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3542, 7218}, +/*h(3530)=3 EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3530, 7217}, +/*h(3474)=4 EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3474, 7214}, +/*h(3462)=5 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3462, 7215}, +/*h(3463)=6 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3463, 7216}, +/*h(3535)=7 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3535, 7216}, +/*h(3470)=8 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3470, 7215}, +/*h(3458)=9 EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3458, 7217}, +/*h(3543)=10 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3543, 7219}, +/*h(3478)=11 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3478, 7212}, +/*h(3466)=12 EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3466, 7217}, +/*h(3538)=13 EVV 0x2C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3538, 7220}, +/*h(3526)=14 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3526, 7215}, +/*h(3527)=15 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3527, 7216}, +/*h(3471)=16 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3471, 7216}, +/*h(3534)=17 EVV 0x2C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3534, 7215} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((26*key % 331) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(3522)=0 EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3522, 7142}, +/*h(3479)=1 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 7138}, +/*h(3542)=2 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3542, 7143}, +/*h(3530)=3 EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3530, 7142}, +/*h(3474)=4 EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3474, 7139}, +/*h(3462)=5 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3462, 7140}, +/*h(3463)=6 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3463, 7141}, +/*h(3535)=7 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3535, 7141}, +/*h(3470)=8 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3470, 7140}, +/*h(3458)=9 EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3458, 7142}, +/*h(3543)=10 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3543, 7144}, +/*h(3478)=11 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3478, 7137}, +/*h(3466)=12 EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3466, 7142}, +/*h(3538)=13 EVV 0x2D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3538, 7145}, +/*h(3526)=14 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3526, 7140}, +/*h(3527)=15 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3527, 7141}, +/*h(3471)=16 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3471, 7141}, +/*h(3534)=17 EVV 0x2D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3534, 7140} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((26*key % 331) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(54)=0 EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0*/ {54, 7611}, +/*h(55)=1 EVV 0x2E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0*/ {55, 7612}, +/*h(50)=2 EVV 0x2E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR()*/ {50, 7613} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x2f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(54)=0 EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0*/ {54, 7044}, +/*h(55)=1 EVV 0x2F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0*/ {55, 7045}, +/*h(50)=2 EVV 0x2F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_SCALAR()*/ {50, 7046} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7591} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24)=0 EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {24, 7592}, +/*h(1011)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {1011, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(491)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {491, 7599}, +/*h(25)=1 EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {25, 7592} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(282)=0 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7593} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(746)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {746, 7598}, +/*h(280)=1 EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {280, 7594} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*empty slot1 */ {0,0}, +/*h(192)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {192, 7600}, +/*h(281)=2 EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {281, 7594} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(538)=0 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7595} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(27)=0 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7596} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 27; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(283)=0 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7596} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 283; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(539)=0 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {539, 7596}, +/*h(251)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {251, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(706)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {706, 7598}, +/*h(795)=1 EVV 0x51 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {795, 7596}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1002)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {1002, 7598}, +/*h(536)=1 EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {536, 7597}, +/*h(248)=2 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {248, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(537)=0 EVV 0x51 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {537, 7597}, +/*h(1003)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {1003, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(715)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {715, 7599}, +/*h(482)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {482, 7598}, +/*h(194)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {194, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {450, 7598}, +/*h(971)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {971, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(962)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {962, 7598}, +/*h(496)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {496, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(226)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {226, 7598}, +/*h(747)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {747, 7599}, +/*h(459)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {459, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(240)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {240, 7600}, +/*h(994)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {994, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(210)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {210, 7598}, +/*h(731)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {731, 7599}, +/*h(498)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {498, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(466)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {978, 7598}, +/*h(224)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {224, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(763)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {763, 7599}, +/*h(475)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {475, 7599}, +/*h(242)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {242, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(754)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {754, 7598}, +/*h(987)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {987, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1010)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(490)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {490, 7598}, +/*h(202)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {202, 7598}, +/*h(723)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {723, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(458)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {458, 7598}, +/*h(979)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {979, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(504)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {504, 7600}, +/*h(216)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {216, 7600}, +/*h(970)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {970, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(755)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {755, 7599}, +/*h(467)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {467, 7599}, +/*h(234)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {234, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(451)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {451, 7599}, +/*h(506)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {506, 7598}, +/*h(218)=2 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {218, 7598}, +/*h(739)=3 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {739, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(474)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {474, 7598}, +/*h(707)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {707, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(730)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {730, 7598}, +/*h(1018)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {1018, 7598} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(986)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {986, 7598}, +/*h(232)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {232, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(250)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {250, 7598}, +/*h(483)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {483, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {762, 7598}, +/*h(995)=1 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {995, 7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(195)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(963)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(211)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 211; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(243)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(499)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(203)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 203; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(507)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1019)=0 EVV 0x51 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {7599} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(448)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {448, 7600}, +/*h(736)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {736, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(704)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(960)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(992)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(208)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(464)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {464, 7600}, +/*h(752)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {752, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(976)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1008)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(200)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(744)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {744, 7600}, +/*h(456)=1 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {456, 7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(968)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(488)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1000)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(472)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 472; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(728)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(984)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(760)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1016)=0 EVV 0x51 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7600} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x51_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[109] = { +/*h(466)=0 */ {466, xed3_phash_find_mapevex_map5_opcode0x51_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1000)=3 */ {1000, xed3_phash_find_mapevex_map5_opcode0x51_vv2_3_l1}, +/*h(712)=4 */ {712, xed3_phash_find_mapevex_map5_opcode0x51_vv2_4_l1}, +/*h(746)=5 */ {746, xed3_phash_find_mapevex_map5_opcode0x51_vv2_5_l1}, +/*h(979)=6 */ {979, xed3_phash_find_mapevex_map5_opcode0x51_vv2_6_l1}, +/*h(26)=7 */ {26, xed3_phash_find_mapevex_map5_opcode0x51_vv2_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(992)=9 */ {992, xed3_phash_find_mapevex_map5_opcode0x51_vv2_9_l1}, +/*h(704)=10 */ {704, xed3_phash_find_mapevex_map5_opcode0x51_vv2_10_l1}, +/*h(738)=11 */ {738, xed3_phash_find_mapevex_map5_opcode0x51_vv2_11_l1}, +/*h(971)=12 */ {971, xed3_phash_find_mapevex_map5_opcode0x51_vv2_12_l1}, +/*h(251)=13 */ {251, xed3_phash_find_mapevex_map5_opcode0x51_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(984)=15 */ {984, xed3_phash_find_mapevex_map5_opcode0x51_vv2_15_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1018)=17 */ {1018, xed3_phash_find_mapevex_map5_opcode0x51_vv2_17_l1}, +/*h(963)=18 */ {963, xed3_phash_find_mapevex_map5_opcode0x51_vv2_18_l1}, +/*h(243)=19 */ {243, xed3_phash_find_mapevex_map5_opcode0x51_vv2_19_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(976)=21 */ {976, xed3_phash_find_mapevex_map5_opcode0x51_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=23 */ {1010, xed3_phash_find_mapevex_map5_opcode0x51_vv2_23_l1}, +/*h(722)=24 */ {722, xed3_phash_find_mapevex_map5_opcode0x51_vv2_24_l1}, +/*h(235)=25 */ {235, xed3_phash_find_mapevex_map5_opcode0x51_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(968)=28 */ {968, xed3_phash_find_mapevex_map5_opcode0x51_vv2_28_l1}, +/*h(248)=29 */ {248, xed3_phash_find_mapevex_map5_opcode0x51_vv2_29_l1}, +/*h(714)=30 */ {714, xed3_phash_find_mapevex_map5_opcode0x51_vv2_30_l1}, +/*h(282)=31 */ {282, xed3_phash_find_mapevex_map5_opcode0x51_vv2_31_l1}, +/*h(227)=32 */ {227, xed3_phash_find_mapevex_map5_opcode0x51_vv2_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(960)=34 */ {960, xed3_phash_find_mapevex_map5_opcode0x51_vv2_34_l1}, +/*h(240)=35 */ {240, xed3_phash_find_mapevex_map5_opcode0x51_vv2_35_l1}, +/*h(706)=36 */ {706, xed3_phash_find_mapevex_map5_opcode0x51_vv2_36_l1}, +/*h(507)=37 */ {507, xed3_phash_find_mapevex_map5_opcode0x51_vv2_37_l1}, +/*h(219)=38 */ {219, xed3_phash_find_mapevex_map5_opcode0x51_vv2_38_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(232)=41 */ {232, xed3_phash_find_mapevex_map5_opcode0x51_vv2_41_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(499)=43 */ {499, xed3_phash_find_mapevex_map5_opcode0x51_vv2_43_l1}, +/*h(211)=44 */ {211, xed3_phash_find_mapevex_map5_opcode0x51_vv2_44_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(224)=47 */ {224, xed3_phash_find_mapevex_map5_opcode0x51_vv2_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(491)=49 */ {491, xed3_phash_find_mapevex_map5_opcode0x51_vv2_49_l1}, +/*h(203)=50 */ {203, xed3_phash_find_mapevex_map5_opcode0x51_vv2_50_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(504)=53 */ {504, xed3_phash_find_mapevex_map5_opcode0x51_vv2_53_l1}, +/*h(538)=54 */ {538, xed3_phash_find_mapevex_map5_opcode0x51_vv2_54_l1}, +/*h(483)=55 */ {483, xed3_phash_find_mapevex_map5_opcode0x51_vv2_55_l1}, +/*h(195)=56 */ {195, xed3_phash_find_mapevex_map5_opcode0x51_vv2_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(496)=59 */ {496, xed3_phash_find_mapevex_map5_opcode0x51_vv2_59_l1}, +/*h(208)=60 */ {208, xed3_phash_find_mapevex_map5_opcode0x51_vv2_60_l1}, +/*h(763)=61 */ {763, xed3_phash_find_mapevex_map5_opcode0x51_vv2_61_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(488)=65 */ {488, xed3_phash_find_mapevex_map5_opcode0x51_vv2_65_l1}, +/*h(200)=66 */ {200, xed3_phash_find_mapevex_map5_opcode0x51_vv2_66_l1}, +/*h(755)=67 */ {755, xed3_phash_find_mapevex_map5_opcode0x51_vv2_67_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(480)=71 */ {480, xed3_phash_find_mapevex_map5_opcode0x51_vv2_71_l1}, +/*h(192)=72 */ {192, xed3_phash_find_mapevex_map5_opcode0x51_vv2_72_l1}, +/*h(747)=73 */ {747, xed3_phash_find_mapevex_map5_opcode0x51_vv2_73_l1}, +/*h(27)=74 */ {27, xed3_phash_find_mapevex_map5_opcode0x51_vv2_74_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(760)=76 */ {760, xed3_phash_find_mapevex_map5_opcode0x51_vv2_76_l1}, +/*h(472)=77 */ {472, xed3_phash_find_mapevex_map5_opcode0x51_vv2_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=79 */ {739, xed3_phash_find_mapevex_map5_opcode0x51_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(752)=83 */ {752, xed3_phash_find_mapevex_map5_opcode0x51_vv2_83_l1}, +/*h(1019)=84 */ {1019, xed3_phash_find_mapevex_map5_opcode0x51_vv2_84_l1}, +/*h(731)=85 */ {731, xed3_phash_find_mapevex_map5_opcode0x51_vv2_85_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(744)=89 */ {744, xed3_phash_find_mapevex_map5_opcode0x51_vv2_89_l1}, +/*h(1011)=90 */ {1011, xed3_phash_find_mapevex_map5_opcode0x51_vv2_90_l1}, +/*h(723)=91 */ {723, xed3_phash_find_mapevex_map5_opcode0x51_vv2_91_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(736)=95 */ {736, xed3_phash_find_mapevex_map5_opcode0x51_vv2_95_l1}, +/*h(1003)=96 */ {1003, xed3_phash_find_mapevex_map5_opcode0x51_vv2_96_l1}, +/*h(715)=97 */ {715, xed3_phash_find_mapevex_map5_opcode0x51_vv2_97_l1}, +/*h(283)=98 */ {283, xed3_phash_find_mapevex_map5_opcode0x51_vv2_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1016)=100 */ {1016, xed3_phash_find_mapevex_map5_opcode0x51_vv2_100_l1}, +/*h(728)=101 */ {728, xed3_phash_find_mapevex_map5_opcode0x51_vv2_101_l1}, +/*h(995)=102 */ {995, xed3_phash_find_mapevex_map5_opcode0x51_vv2_102_l1}, +/*h(707)=103 */ {707, xed3_phash_find_mapevex_map5_opcode0x51_vv2_103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1008)=106 */ {1008, xed3_phash_find_mapevex_map5_opcode0x51_vv2_106_l1}, +/*h(720)=107 */ {720, xed3_phash_find_mapevex_map5_opcode0x51_vv2_107_l1}, +/*h(987)=108 */ {987, xed3_phash_find_mapevex_map5_opcode0x51_vv2_108_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 109ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x58_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {0, 7025}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7033}, +/*h(32)=4 EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {32, 7027}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7033}, +/*h(64)=8 EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {64, 7030}, +/*h(1)=9 EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {1, 7025}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7033}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {33, 7027}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0x58 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7033}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0x58 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {65, 7030}, +/*h(2)=18 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 7024}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7031}, +/*h(34)=22 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 7026}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7031}, +/*h(66)=26 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 7028}, +/*h(3)=27 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 7029}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {90, 7031}, +/*h(27)=30 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7032}, +/*h(35)=31 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 7029}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {122, 7031}, +/*h(59)=34 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 7032}, +/*h(67)=35 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 7029}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 7032}, +/*h(99)=39 EVV 0x58 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 7029}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0x58 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 7032}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x59_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {0, 7536}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7544}, +/*h(32)=4 EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {32, 7538}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7544}, +/*h(64)=8 EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {64, 7541}, +/*h(1)=9 EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {1, 7536}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7544}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {33, 7538}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0x59 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7544}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0x59 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {65, 7541}, +/*h(2)=18 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 7535}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7542}, +/*h(34)=22 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 7537}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7542}, +/*h(66)=26 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 7539}, +/*h(3)=27 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 7540}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {90, 7542}, +/*h(27)=30 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7543}, +/*h(35)=31 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 7540}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {122, 7542}, +/*h(59)=34 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 7543}, +/*h(67)=35 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 7540}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 7543}, +/*h(99)=39 EVV 0x59 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 7540}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0x59 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 7543}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(704)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {704, 7136}, +/*h(94)=1 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 7054} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(935)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {935, 7132}, +/*h(92)=1 EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 7055}, +/*h(702)=2 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {702, 7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(93)=0 EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 7055}, +/*h(703)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {703, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(350)=0 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {7056} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(348)=0 EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 7057}, +/*h(958)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {958, 7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(959)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {959, 7132}, +/*h(349)=1 EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 7057} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(606)=0 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {7058} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(472)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {472, 7136}, +/*h(95)=1 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {95, 7059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(728)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {728, 7136}, +/*h(351)=1 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {351, 7059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(984)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {984, 7136}, +/*h(607)=1 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {607, 7059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(863)=0 EVV 0x5A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {7059} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(604)=0 EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {7060} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(605)=0 EVV 0x5A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {7060} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7068} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24)=0 EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {24, 7069}, +/*h(1011)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {1011, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25)=0 EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7069} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 25; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(282)=0 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(280)=0 EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(281)=0 EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(538)=0 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(404)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {404, 7133}, +/*h(27)=1 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {27, 7073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(660)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {660, 7133}, +/*h(283)=1 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {283, 7073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(539)=0 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 EVV 0x5A VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(536)=0 EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {536, 7074}, +/*h(1002)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {1002, 7134}, +/*h(159)=2 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {159, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(537)=0 EVV 0x5A VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(744)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {744, 7136}, +/*h(134)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {134, 7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(390)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {390, 7131}, +/*h(1000)=1 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {1000, 7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(646)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(902)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(166)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {166, 7131}, +/*h(399)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {399, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(422)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(678)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(180)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {180, 7133}, +/*h(934)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {934, 7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {150, 7131}, +/*h(760)=1 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {760, 7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(406)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {406, 7131}, +/*h(927)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {927, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(662)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(918)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {918, 7131}, +/*h(164)=1 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {164, 7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(182)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {182, 7131}, +/*h(415)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {415, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(438)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {438, 7131}, +/*h(671)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {671, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(694)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(950)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1008)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {1008, 7136}, +/*h(398)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {398, 7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(654)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(910)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(174)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {174, 7131}, +/*h(407)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {407, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(430)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {430, 7131}, +/*h(663)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {663, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {158, 7131}, +/*h(391)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {391, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(414)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(670)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {670, 7131}, +/*h(903)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {903, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(926)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {926, 7131}, +/*h(172)=1 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {172, 7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(190)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {7131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(446)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1*/ {446, 7131}, +/*h(679)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {679, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(135)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(647)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {1010, 7134}, +/*h(167)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {167, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(151)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(919)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(183)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(439)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(695)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(951)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(143)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(655)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(911)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(175)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 175; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(431)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(687)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(943)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(191)=0 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(968)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {968, 7136}, +/*h(447)=1 EVV 0x5A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {447, 7132} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(132)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(388)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(644)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(900)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(420)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 420; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(676)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(932)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(148)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {450, 7134}, +/*h(916)=1 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {916, 7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(436)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {436, 7133}, +/*h(203)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {203, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(692)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(948)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {948, 7133}, +/*h(194)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {194, 7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(140)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(396)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(652)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(908)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(428)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(684)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(940)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {940, 7133}, +/*h(707)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {707, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(156)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(412)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(668)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(924)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(188)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {7133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(444)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {444, 7133}, +/*h(211)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {211, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(234)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {234, 7134}, +/*h(700)=1 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {700, 7133}, +/*h(467)=2 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {467, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(956)=0 EVV 0x5A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {956, 7133}, +/*h(202)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {202, 7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {226, 7134}, +/*h(459)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {459, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(482)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {482, 7134}, +/*h(715)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {715, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(240)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {240, 7136}, +/*h(994)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {994, 7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(466)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {978, 7134}, +/*h(224)=1 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {224, 7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(242)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {242, 7134}, +/*h(475)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {475, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(498)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {498, 7134}, +/*h(731)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {731, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(754)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {754, 7134}, +/*h(987)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {987, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(458)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {458, 7134}, +/*h(979)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {979, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {216, 7136}, +/*h(970)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {970, 7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(490)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {490, 7134}, +/*h(723)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {723, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(218)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {218, 7134}, +/*h(451)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {451, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(474)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(986)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {986, 7134}, +/*h(232)=1 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {232, 7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(250)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(506)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {506, 7134}, +/*h(739)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {739, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {762, 7134}, +/*h(995)=1 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {995, 7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1018)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {7134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(195)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(963)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(243)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(499)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(971)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(491)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(747)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1003)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(251)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(507)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(763)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1019)=0 EVV 0x5A VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {7135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(192)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(448)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(960)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(992)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(208)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(464)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(976)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(496)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(200)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(456)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(488)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(248)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(504)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1016)=0 EVV 0x5A VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {7136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5a_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[218] = { +/*h(466)=0 */ {466, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_0_l1}, +/*h(932)=1 */ {932, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(644)=3 */ {644, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(678)=5 */ {678, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_5_l1}, +/*h(911)=6 */ {911, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_6_l1}, +/*h(1000)=7 */ {1000, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_7_l1}, +/*h(712)=8 */ {712, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_8_l1}, +/*h(191)=9 */ {191, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_9_l1}, +/*h(280)=10 */ {280, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_10_l1}, +/*h(746)=11 */ {746, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_11_l1}, +/*h(979)=12 */ {979, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_12_l1}, +/*h(924)=13 */ {924, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26)=15 */ {26, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_15_l1}, +/*h(958)=16 */ {958, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(903)=18 */ {903, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_18_l1}, +/*h(992)=19 */ {992, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_19_l1}, +/*h(704)=20 */ {704, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_20_l1}, +/*h(183)=21 */ {183, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=23 */ {738, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_23_l1}, +/*h(971)=24 */ {971, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_24_l1}, +/*h(450)=25 */ {450, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_25_l1}, +/*h(539)=26 */ {539, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_26_l1}, +/*h(251)=27 */ {251, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_27_l1}, +/*h(950)=28 */ {950, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(662)=30 */ {662, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_30_l1}, +/*h(984)=31 */ {984, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_31_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(175)=33 */ {175, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_33_l1}, +/*h(1018)=34 */ {1018, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_34_l1}, +/*h(730)=35 */ {730, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_35_l1}, +/*h(963)=36 */ {963, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(908)=38 */ {908, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_38_l1}, +/*h(243)=39 */ {243, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_39_l1}, +/*h(942)=40 */ {942, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_40_l1}, +/*h(188)=41 */ {188, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_41_l1}, +/*h(654)=42 */ {654, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_42_l1}, +/*h(976)=43 */ {976, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_43_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=46 */ {1010, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_46_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(722)=48 */ {722, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(900)=50 */ {900, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_50_l1}, +/*h(235)=51 */ {235, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_51_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(180)=53 */ {180, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_53_l1}, +/*h(646)=54 */ {646, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_54_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(968)=56 */ {968, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1002)=58 */ {1002, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_58_l1}, +/*h(248)=59 */ {248, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_59_l1}, +/*h(714)=60 */ {714, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(282)=62 */ {282, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_62_l1}, +/*h(604)=63 */ {604, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_63_l1}, +/*h(227)=64 */ {227, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_64_l1}, +/*h(172)=65 */ {172, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(350)=67 */ {350, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_67_l1}, +/*h(960)=68 */ {960, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_68_l1}, +/*h(439)=69 */ {439, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_69_l1}, +/*h(151)=70 */ {151, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_70_l1}, +/*h(240)=71 */ {240, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_71_l1}, +/*h(706)=72 */ {706, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_72_l1}, +/*h(795)=73 */ {795, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_73_l1}, +/*h(507)=74 */ {507, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_74_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(219)=76 */ {219, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_76_l1}, +/*h(164)=77 */ {164, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(863)=79 */ {863, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(431)=81 */ {431, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_81_l1}, +/*h(143)=82 */ {143, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_82_l1}, +/*h(232)=83 */ {232, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_83_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(499)=86 */ {499, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(211)=88 */ {211, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_88_l1}, +/*h(910)=89 */ {910, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_89_l1}, +/*h(156)=90 */ {156, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_90_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(190)=92 */ {190, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_92_l1}, +/*h(423)=93 */ {423, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_93_l1}, +/*h(135)=94 */ {135, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_94_l1}, +/*h(224)=95 */ {224, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25)=98 */ {25, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_98_l1}, +/*h(491)=99 */ {491, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_99_l1}, +/*h(203)=100 */ {203, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_100_l1}, +/*h(902)=101 */ {902, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_101_l1}, +/*h(148)=102 */ {148, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(703)=104 */ {703, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_104_l1}, +/*h(415)=105 */ {415, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_105_l1}, +/*h(504)=106 */ {504, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_106_l1}, +/*h(216)=107 */ {216, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(538)=109 */ {538, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_109_l1}, +/*h(250)=110 */ {250, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_110_l1}, +/*h(483)=111 */ {483, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_111_l1}, +/*h(195)=112 */ {195, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_112_l1}, +/*h(428)=113 */ {428, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_113_l1}, +/*h(140)=114 */ {140, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_114_l1}, +/*h(606)=115 */ {606, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_115_l1}, +/*h(695)=116 */ {695, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_116_l1}, +/*h(407)=117 */ {407, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_117_l1}, +/*h(496)=118 */ {496, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_118_l1}, +/*h(962)=119 */ {962, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_119_l1}, +/*h(208)=120 */ {208, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(763)=122 */ {763, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_122_l1}, +/*h(475)=123 */ {475, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(420)=125 */ {420, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_125_l1}, +/*h(132)=126 */ {132, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(687)=128 */ {687, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_128_l1}, +/*h(399)=129 */ {399, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_129_l1}, +/*h(488)=130 */ {488, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(200)=132 */ {200, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(755)=134 */ {755, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_134_l1}, +/*h(467)=135 */ {467, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(412)=137 */ {412, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(679)=140 */ {679, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_140_l1}, +/*h(391)=141 */ {391, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(480)=143 */ {480, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_143_l1}, +/*h(192)=144 */ {192, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_144_l1}, +/*h(281)=145 */ {281, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_145_l1}, +/*h(747)=146 */ {747, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_146_l1}, +/*h(459)=147 */ {459, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_147_l1}, +/*h(692)=148 */ {692, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_148_l1}, +/*h(404)=149 */ {404, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(959)=151 */ {959, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_151_l1}, +/*h(671)=152 */ {671, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_152_l1}, +/*h(760)=153 */ {760, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(472)=155 */ {472, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=158 */ {739, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_158_l1}, +/*h(451)=159 */ {451, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_159_l1}, +/*h(684)=160 */ {684, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_160_l1}, +/*h(396)=161 */ {396, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(951)=163 */ {951, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_163_l1}, +/*h(663)=164 */ {663, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_164_l1}, +/*h(142)=165 */ {142, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_165_l1}, +/*h(752)=166 */ {752, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_166_l1}, +/*h(464)=167 */ {464, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1019)=169 */ {1019, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_169_l1}, +/*h(731)=170 */ {731, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_170_l1}, +/*h(210)=171 */ {210, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_171_l1}, +/*h(676)=172 */ {676, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_172_l1}, +/*h(388)=173 */ {388, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(943)=175 */ {943, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_175_l1}, +/*h(422)=176 */ {422, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_176_l1}, +/*h(655)=177 */ {655, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_177_l1}, +/*h(744)=178 */ {744, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_178_l1}, +/*h(456)=179 */ {456, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1011)=181 */ {1011, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_181_l1}, +/*h(723)=182 */ {723, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_182_l1}, +/*h(202)=183 */ {202, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_183_l1}, +/*h(668)=184 */ {668, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(935)=187 */ {935, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_187_l1}, +/*h(414)=188 */ {414, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_188_l1}, +/*h(647)=189 */ {647, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_189_l1}, +/*h(736)=190 */ {736, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_190_l1}, +/*h(448)=191 */ {448, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_191_l1}, +/*h(537)=192 */ {537, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_192_l1}, +/*h(1003)=193 */ {1003, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_193_l1}, +/*h(715)=194 */ {715, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_194_l1}, +/*h(194)=195 */ {194, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_195_l1}, +/*h(660)=196 */ {660, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(605)=198 */ {605, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_198_l1}, +/*h(694)=199 */ {694, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_199_l1}, +/*h(927)=200 */ {927, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_200_l1}, +/*h(1016)=201 */ {1016, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_201_l1}, +/*h(728)=202 */ {728, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_202_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(995)=205 */ {995, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_205_l1}, +/*h(474)=206 */ {474, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_206_l1}, +/*h(707)=207 */ {707, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_207_l1}, +/*h(652)=208 */ {652, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=211 */ {686, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_211_l1}, +/*h(919)=212 */ {919, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_212_l1}, +/*h(1008)=213 */ {1008, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_213_l1}, +/*h(720)=214 */ {720, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_214_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(987)=217 */ {987, xed3_phash_find_mapevex_map5_opcode0x5a_vv2_217_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 218ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[104] = { +/*empty slot1 */ {0,0}, +/*h(29)=1 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {29, 7125}, +/*h(602)=2 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7065}, +/*h(30)=3 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {30, 7124}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(537)=6 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {537, 7053}, +/*h(89)=7 EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {89, 7062}, +/*h(538)=8 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 7051}, +/*h(90)=9 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7061}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(473)=12 EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {473, 7173}, +/*h(25)=13 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {25, 7048}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(284)=16 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {284, 7127}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(543)=19 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {543, 7129}, +/*h(219)=20 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {219, 7175}, +/*empty slot1 */ {0,0}, +/*h(344)=22 EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {344, 7064}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=25 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {603, 7066}, +/*h(31)=26 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {31, 7129}, +/*h(728)=27 EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {728, 7176}, +/*h(280)=28 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {280, 7050}, +/*empty slot1 */ {0,0}, +/*h(987)=30 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {987, 7175}, +/*h(539)=31 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {539, 7052}, +/*h(91)=32 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {91, 7066}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(474)=35 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 7172}, +/*h(26)=36 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 7047}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(285)=39 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {285, 7127}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=45 EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {345, 7064}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(729)=50 EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {729, 7176}, +/*h(281)=51 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {281, 7050}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(540)=54 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {540, 7130}, +/*h(216)=55 EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {216, 7171}, +/*empty slot1 */ {0,0}, +/*h(799)=57 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {799, 7129}, +/*h(475)=58 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {475, 7175}, +/*h(27)=59 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {27, 7052}, +/*h(600)=60 EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {600, 7067}, +/*empty slot1 */ {0,0}, +/*h(286)=62 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {286, 7126}, +/*h(859)=63 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {859, 7066}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(346)=68 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7063}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(730)=73 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 7174}, +/*h(282)=74 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 7049}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(541)=77 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {541, 7130}, +/*h(217)=78 EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {217, 7171}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=82 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {28, 7125}, +/*h(601)=83 EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {601, 7067}, +/*empty slot1 */ {0,0}, +/*h(287)=85 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {287, 7129}, +/*empty slot1 */ {0,0}, +/*h(536)=87 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {536, 7053}, +/*h(88)=88 EVV 0x5B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {88, 7062}, +/*empty slot1 */ {0,0}, +/*h(795)=90 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {795, 7052}, +/*h(347)=91 EVV 0x5B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {347, 7066}, +/*empty slot1 */ {0,0}, +/*h(472)=93 EVV 0x5B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {472, 7173}, +/*h(24)=94 EVV 0x5B VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24, 7048}, +/*empty slot1 */ {0,0}, +/*h(731)=96 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {731, 7175}, +/*h(283)=97 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {283, 7052}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(542)=100 EVV 0x5B VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {542, 7128}, +/*h(218)=101 EVV 0x5B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 7170}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((23*key % 229) % 104); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {0, 7602}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7610}, +/*h(32)=4 EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {32, 7604}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7610}, +/*h(64)=8 EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {64, 7607}, +/*h(1)=9 EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {1, 7602}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7610}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {33, 7604}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0x5C VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7610}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0x5C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {65, 7607}, +/*h(2)=18 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 7601}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7608}, +/*h(34)=22 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 7603}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7608}, +/*h(66)=26 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 7605}, +/*h(3)=27 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 7606}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {90, 7608}, +/*h(27)=30 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7609}, +/*h(35)=31 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 7606}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {122, 7608}, +/*h(59)=34 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 7609}, +/*h(67)=35 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 7606}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 7609}, +/*h(99)=39 EVV 0x5C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 7606}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0x5C VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 7609}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {0, 7518}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7526}, +/*h(32)=4 EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {32, 7520}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7526}, +/*h(64)=8 EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {64, 7523}, +/*h(1)=9 EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {1, 7518}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7526}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {33, 7520}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0x5D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7526}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0x5D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {65, 7523}, +/*h(2)=18 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 7517}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7524}, +/*h(34)=22 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 7519}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7524}, +/*h(66)=26 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 7521}, +/*h(3)=27 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {3, 7522}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {90, 7524}, +/*h(27)=30 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {27, 7525}, +/*h(35)=31 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {35, 7522}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {122, 7524}, +/*h(59)=34 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {59, 7525}, +/*h(67)=35 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {67, 7522}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {91, 7525}, +/*h(99)=39 EVV 0x5D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {99, 7522}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0x5D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {123, 7525}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {0, 7268}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7276}, +/*h(32)=4 EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {32, 7270}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7276}, +/*h(64)=8 EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {64, 7273}, +/*h(1)=9 EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {1, 7268}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7276}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {33, 7270}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0x5E VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7276}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0x5E VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {65, 7273}, +/*h(2)=18 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 7267}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7274}, +/*h(34)=22 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 7269}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7274}, +/*h(66)=26 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 7271}, +/*h(3)=27 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 7272}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {90, 7274}, +/*h(27)=30 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7275}, +/*h(35)=31 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 7272}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {122, 7274}, +/*h(59)=34 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 7275}, +/*h(67)=35 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 7272}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 7275}, +/*h(99)=39 EVV 0x5E VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 7272}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0x5E VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 7275}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x5f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[50] = { +/*h(0)=0 EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {0, 7508}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=3 EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7516}, +/*h(32)=4 EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {32, 7510}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(56)=7 EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7516}, +/*h(64)=8 EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {64, 7513}, +/*h(1)=9 EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {1, 7508}, +/*empty slot1 */ {0,0}, +/*h(88)=11 EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {88, 7516}, +/*empty slot1 */ {0,0}, +/*h(33)=13 EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {33, 7510}, +/*empty slot1 */ {0,0}, +/*h(120)=15 EVV 0x5F VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {120, 7516}, +/*empty slot1 */ {0,0}, +/*h(65)=17 EVV 0x5F VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {65, 7513}, +/*h(2)=18 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 7507}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=21 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7514}, +/*h(34)=22 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 7509}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=25 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7514}, +/*h(66)=26 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 7511}, +/*h(3)=27 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {3, 7512}, +/*empty slot1 */ {0,0}, +/*h(90)=29 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {90, 7514}, +/*h(27)=30 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {27, 7515}, +/*h(35)=31 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {35, 7512}, +/*empty slot1 */ {0,0}, +/*h(122)=33 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {122, 7514}, +/*h(59)=34 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {59, 7515}, +/*h(67)=35 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {67, 7512}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {91, 7515}, +/*h(99)=39 EVV 0x5F VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {99, 7512}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=42 EVV 0x5F VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {123, 7515}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 71) % 50); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x6e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 EVV 0x6E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0*/ {94, 7531}, +/*h(90)=1 EVV 0x6E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_READER()*/ {90, 7532} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5556)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5556, 7193}, +/*h(388)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {388, 7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16772)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16772, 7184}, +/*h(21940)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21940, 7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(420)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {420, 7184}, +/*h(29077)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29077, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16804)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_516_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(396)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {396, 7184}, +/*h(21911)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21911, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16780)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7570)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7570, 7223}, +/*h(1415)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1415, 7196}, +/*h(428)=2 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {428, 7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16812)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16812, 7184}, +/*h(17799)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17799, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(404)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {404, 7184}, +/*h(29061)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29061, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16788)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16788, 7184}, +/*h(9646)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9646, 7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(436)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {436, 7184}, +/*h(29093)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29093, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16820)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16820, 7184}, +/*h(17807)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17807, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(390)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21942)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21942, 7193}, +/*h(16774)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16774, 7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_563_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(422)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {422, 7184}, +/*h(1409)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1409, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16806)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16806, 7184}, +/*h(17793)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17793, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(398)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16782)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16782, 7184}, +/*h(9640)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9640, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(430)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16814)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16814, 7184}, +/*h(17801)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17801, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_641_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(406)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {406, 7184}, +/*h(29063)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29063, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16790)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29095)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29095, 7189}, +/*h(1425)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1425, 7192}, +/*h(438)=2 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {438, 7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11654)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11654, 7224}, +/*h(16822)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16822, 7184} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(384)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21936)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21936, 7194}, +/*h(16768)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16768, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(416)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {416, 7185}, +/*h(21931)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21931, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16800)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(392)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16776)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(424)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16808)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(400)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16784)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(432)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {432, 7185}, +/*h(1419)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1419, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16816)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(386)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {386, 7185}, +/*h(5554)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5554, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_299_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16770)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16770, 7185}, +/*h(21938)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21938, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(418)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16802)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16802, 7185}, +/*h(15815)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15815, 7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(394)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16778)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(426)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {426, 7185}, +/*h(1413)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1413, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16810)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16810, 7185}, +/*h(15823)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15823, 7225}, +/*h(17797)=2 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17797, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(402)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16786)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(434)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {434, 7185}, +/*h(1421)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1421, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(17805)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17805, 7196}, +/*h(11650)=1 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11650, 7226}, +/*h(16818)=2 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16818, 7185}, +/*h(15831)=3 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15831, 7228} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5553)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5553, 7194}, +/*h(385)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {385, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16769)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(417)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16801)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(393)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16777)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1412)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1412, 7191}, +/*h(425)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {425, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15822)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15822, 7224}, +/*h(16809)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16809, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(401)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16785)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1420)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1420, 7191}, +/*h(433)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {433, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15830)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15830, 7227}, +/*h(16817)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16817, 7185}, +/*h(17804)=2 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17804, 7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(387)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {387, 7185}, +/*h(5555)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5555, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21939)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21939, 7194}, +/*h(16771)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16771, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(419)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16803)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11718)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11718, 7224}, +/*h(395)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {395, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16779)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_626_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1414)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1414, 7191}, +/*h(427)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {427, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17798)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17798, 7191}, +/*h(16811)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16811, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(403)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16787)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1422)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1422, 7191}, +/*h(435)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {435, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17806)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17806, 7191}, +/*h(16819)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16819, 7185} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4484)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4484, 7186}, +/*h(25999)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25999, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20868)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20868, 7186}, +/*h(26036)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {26036, 7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11658)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11658, 7226}, +/*h(4516)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4516, 7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20900)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4492)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4492; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20876)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20876, 7186}, +/*h(3542)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3542, 7227} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4524)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4524, 7186}, +/*h(26039)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {26039, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20908)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20908, 7186}, +/*h(21895)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21895, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4500)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4500; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20884)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4532)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4532; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20916)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9654)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9654, 7195}, +/*h(4486)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4486, 7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20870)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4518)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20902)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20902, 7186}, +/*h(21889)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21889, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4494)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20878)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4526)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4526, 7186}, +/*h(5513)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5513, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20910)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4502)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20886)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4534)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4534, 7186}, +/*h(5521)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5521, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21905)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21905, 7194}, +/*h(15750)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15750, 7224}, +/*h(20918)=2 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20918, 7186} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9648)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9648, 7197}, +/*h(4480)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4480, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20864)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4512)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20896)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4488)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20872)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4520)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4520, 7187}, +/*h(5507)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5507, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20904)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4496)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20880)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4528)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4528, 7187}, +/*h(5515)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5515, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20912)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20912, 7187}, +/*h(21899)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21899, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4482)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4482, 7187}, +/*h(9650)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9650, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_624_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26034)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26034, 7197}, +/*h(20866)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20866, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4514)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4514, 7187}, +/*h(3527)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3527, 7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20898)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4490)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20874)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4522)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4522, 7187}, +/*h(5509)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5509, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20906)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20906, 7187}, +/*h(21893)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21893, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4498)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20882)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4530)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4530, 7187}, +/*h(3543)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3543, 7228} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21901)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21901, 7196}, +/*h(20914)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20914, 7187}, +/*h(15746)=2 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15746, 7226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4481)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4481, 7187}, +/*h(9649)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9649, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20865)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20865, 7187}, +/*h(26033)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26033, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3526)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3526, 7224}, +/*h(4513)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4513, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20897)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4489)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20873)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4521)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4521, 7187}, +/*h(5508)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5508, 7193}, +/*h(3534)=2 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3534, 7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21892)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21892, 7193}, +/*h(20905)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20905, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4497)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20881)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5516)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5516, 7193}, +/*h(4529)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4529, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21900)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21900, 7193}, +/*h(20913)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20913, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_449_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9651)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9651, 7197}, +/*h(4483)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4483, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20867)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20867, 7187}, +/*h(26035)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26035, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4515)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20899)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26006)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {26006, 7195}, +/*h(4491)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4491, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20875)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5510)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5510, 7193}, +/*h(4523)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4523, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21894)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21894, 7193}, +/*h(20907)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20907, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4499)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20883)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20883, 7187}, +/*h(13741)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13741, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4531)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21902)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21902, 7193}, +/*h(20915)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20915, 7187} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8580)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7630)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7630, 7224}, +/*h(24964)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24964, 7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8612)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8612, 7188}, +/*h(30127)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30127, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24996)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8588)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24972)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8620)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25004)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8596)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24980)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8628)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8628, 7188}, +/*h(9615)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9615, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25012)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25012; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8582)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24966)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8614)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8614, 7188}, +/*h(9601)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9601, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24998)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8590)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24974)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8622)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8622, 7188}, +/*h(9609)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9609, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25006)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8598)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24982)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7188} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24982; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8630)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8630, 7188}, +/*h(9617)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9617, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25014)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25014, 7188}, +/*h(26001)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26001, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(389)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {389, 7189}, +/*h(5557)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5557, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16773)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16773, 7189}, +/*h(21941)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21941, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4485)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3535)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3535, 7225}, +/*h(26037)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {26037, 7196}, +/*h(20869)=2 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20869, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13749)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13749, 7196}, +/*h(8581)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8581, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24965)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12677)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12677, 7189}, +/*h(17845)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17845, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1408)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1408, 7192}, +/*h(421)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {421, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15818)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15818, 7226}, +/*h(17792)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17792, 7192}, +/*h(16805)=2 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16805, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4517)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4517, 7189}, +/*h(3530)=1 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3530, 7226}, +/*h(26032)=2 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26032, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21888)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21888, 7194}, +/*h(20901)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20901, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7626)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7626, 7226}, +/*h(8613)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8613, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25984)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25984, 7197}, +/*h(24997)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24997, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11722)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11722, 7226}, +/*h(12709)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12709, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(397)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16781)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4493)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_484_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20877)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20877, 7189}, +/*h(13735)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13735, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8589)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24973)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12685)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29069)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(429)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17800)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17800, 7192}, +/*h(16813)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16813, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3538)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3538, 7229}, +/*h(4525)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4525, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21896)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21896, 7194}, +/*h(20909)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20909, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8621)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8621, 7189}, +/*h(9608)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9608, 7197}, +/*h(7634)=2 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7634, 7229} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25005)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11730)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11730, 7229}, +/*h(12717)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12717, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1431)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1431, 7196}, +/*h(29101)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29101, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(405)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16789)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4501)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4501; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20885)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8597)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24981)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12693)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(437)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16821)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_381_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5520)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5520, 7194}, +/*h(4533)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4533, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20917)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9616)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9616, 7197}, +/*h(8629)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8629, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_615_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26000)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26000, 7197}, +/*h(25013)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25013, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12725)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29109)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29109; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5559)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5559, 7196}, +/*h(391)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {391, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9633)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9633, 7197}, +/*h(16775)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16775, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4487)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4487, 7189}, +/*h(9655)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9655, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20871)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8583)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8583, 7189}, +/*h(13751)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13751, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_316_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(30135)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30135, 7196}, +/*h(24967)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24967, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17847)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17847, 7196}, +/*h(12679)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12679, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17794)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17794, 7192}, +/*h(16807)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16807, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_623_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5506)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5506, 7194}, +/*h(4519)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4519, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20903)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9602)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9602, 7197}, +/*h(8615)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8615, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24999)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12711)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(399)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16783)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4495)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20879)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8591)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24975)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12687)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12687, 7189}, +/*h(5545)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5545, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29071)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1418)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1418, 7192}, +/*h(431)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {431, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16815)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5514)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5514, 7194}, +/*h(4527)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4527, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20911)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9610)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9610, 7197}, +/*h(8623)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8623, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25994)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25994, 7197}, +/*h(25007)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25007, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12719)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29103)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(407)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 407; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16791)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15826)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15826, 7229}, +/*h(4503)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4503, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20887)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1457)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1457, 7192}, +/*h(8599)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8599, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24983)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24983; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12695)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(29079)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29079, 7189}, +/*h(21937)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21937, 7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1426)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1426, 7192}, +/*h(439)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {439, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11655)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11655, 7225}, +/*h(16823)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16823, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5522)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5522, 7194}, +/*h(4535)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4535, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20919)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20919, 7189}, +/*h(21906)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21906, 7194}, +/*h(15751)=2 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15751, 7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9618)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9618, 7197}, +/*h(8631)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8631, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26002)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26002, 7197}, +/*h(25015)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25015, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7559)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7559, 7225}, +/*h(12727)=1 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12727, 7189} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(29111)=0 EVV 0x78 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29111, 7189}, +/*h(1441)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1441, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8576)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24960)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8608)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24992)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8584)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24968)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_682_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8616)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8616, 7190}, +/*h(9603)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9603, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25000)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25000, 7190}, +/*h(25987)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25987, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8592)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8592, 7190}, +/*h(1450)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1450, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24976)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_643_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9611)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9611, 7197}, +/*h(15766)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15766, 7221}, +/*h(8624)=2 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8624, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25008)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25008, 7190}, +/*h(25995)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25995, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8578)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24962)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8610)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24994)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8586)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8586, 7190}, +/*h(1444)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1444, 7191}, +/*h(30101)=2 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30101, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24970)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8618)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8618, 7190}, +/*h(9605)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9605, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25002)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25002, 7190}, +/*h(25989)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25989, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8594)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24978)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {24978, 7190}, +/*h(17836)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17836, 7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8626)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8626, 7190}, +/*h(3458)=1 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3458, 7226}, +/*h(7639)=2 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7639, 7228} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25010)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25010, 7190}, +/*h(25997)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25997, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8577)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24961)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7622)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7622, 7224}, +/*h(8609)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8609, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24993)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8585)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24969)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_416_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9604)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9604, 7195}, +/*h(8617)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8617, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25988)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25988, 7195}, +/*h(25001)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25001, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8593)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3462)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3462, 7224}, +/*h(24977)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {24977, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7638)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7638, 7227}, +/*h(8625)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8625, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25996)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25996, 7195}, +/*h(25009)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25009, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8579)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24963)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8611)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24995)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8587)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_645_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17829)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17829, 7196}, +/*h(24971)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {24971, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8619)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25990)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25990, 7195}, +/*h(25003)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25003, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8595)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24979)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9614)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9614, 7195}, +/*h(8627)=1 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8627, 7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25011)=0 EVV 0x78 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7190} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17796)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17828)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1452)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_384_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1428)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1428, 7191}, +/*h(30085)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30085, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17812)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1460)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1460, 7191}, +/*h(30117)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30117, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17844)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1446)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1446, 7191}, +/*h(30103)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30103, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17830)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1454)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17838)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_548_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1430)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1430, 7191}, +/*h(30087)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30087, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17814)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1462)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1462, 7191}, +/*h(30119)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30119, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17846)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1440)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17824)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1416)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1448)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17832)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1424)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17808)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1456)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17840)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1410)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1442)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17826)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17826, 7192}, +/*h(11671)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11671, 7222} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17802)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17834)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17810)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1458)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17842)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11670)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11670, 7221}, +/*h(17825)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17825, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1417)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1449)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17833)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17809)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17841)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7566)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7566, 7224}, +/*h(1411)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1411, 7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17795)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1443)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17827)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17803)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1451)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17835)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1427)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17811)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1459)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17843)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7192} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5540)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5540; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21924)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5548)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21932)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5524)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5524; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21908)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5542)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21926)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5518)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5550)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21934)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5526)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21910)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5558)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5504)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5536)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5536; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21920)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5512)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5544)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21928)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21904)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5552)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5552; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21890)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5538)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21922)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21898)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5546)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21930)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5505)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5537)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21921)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21897)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21929)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21891)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5539)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21923)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5547)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5523)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21907)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9636)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26020)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9612)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9612, 7195}, +/*h(15767)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15767, 7222} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9644)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26028)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9620)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26004)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9652)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9606)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9638)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26022)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25998)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26030)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9622)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26038)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13701)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1445)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5541)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21925)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21925; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9637)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26021)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13733)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5517)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9613)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9613; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7554)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7554, 7226}, +/*h(11735)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11735, 7228}, +/*h(13709)=2 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13709, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30093)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1453)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17837)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5549)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21933)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9645)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26029)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7623)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7623, 7225}, +/*h(30125)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30125, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1429)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17813)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5525)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21909)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3466)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3466, 7226}, +/*h(9621)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9621, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26005)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7562)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7562, 7226}, +/*h(13717)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13717, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1461)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9653)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7631)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7631, 7225}, +/*h(30133)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30133, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11666)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11666, 7223}, +/*h(5511)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5511, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15762)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15762, 7223}, +/*h(9607)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9607, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25991)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13703)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1447)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17831)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5543)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21927)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9639)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26023)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1423)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5519)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21903)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13711)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30095)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1455)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1455; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17839)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5551)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21935)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9647)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26031)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13743)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17815)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5527)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9623)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9623; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26007)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13719)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7618)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7618, 7226}, +/*h(1463)=1 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1463, 7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21943)=0 EVV 0x78 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {7196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9600)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9632)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26016)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25992)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3522)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3522, 7226}, +/*h(26024)=1 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26024, 7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25986)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9634)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9634, 7197}, +/*h(3479)=1 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 7222} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26018)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9642)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26026)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25985)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26017)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25993)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9641)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26025)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9635)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26019)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9643)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26027)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9619)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26003)=0 EVV 0x78 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3478)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7221} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7574)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7221} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7575)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7222} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3474)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7223} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7558)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15814)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3470)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11662)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15758)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11726)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3463)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11719)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3471)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7567)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11663)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15759)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11727)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11714)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15810)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15754)=0 EVV 0x78 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11734)=0 EVV 0x78 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7227} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x78_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[696] = { +/*h(21892)=0 */ {21892, xed3_phash_find_mapevex_map5_opcode0x78_vv2_0_l1}, +/*h(8595)=1 */ {8595, xed3_phash_find_mapevex_map5_opcode0x78_vv2_1_l1}, +/*h(1453)=2 */ {1453, xed3_phash_find_mapevex_map5_opcode0x78_vv2_2_l1}, +/*h(17800)=3 */ {17800, xed3_phash_find_mapevex_map5_opcode0x78_vv2_3_l1}, +/*h(15826)=4 */ {15826, xed3_phash_find_mapevex_map5_opcode0x78_vv2_4_l1}, +/*h(26018)=5 */ {26018, xed3_phash_find_mapevex_map5_opcode0x78_vv2_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11734)=7 */ {11734, xed3_phash_find_mapevex_map5_opcode0x78_vv2_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21926)=9 */ {21926, xed3_phash_find_mapevex_map5_opcode0x78_vv2_9_l1}, +/*h(9616)=10 */ {9616, xed3_phash_find_mapevex_map5_opcode0x78_vv2_10_l1}, +/*h(24976)=11 */ {24976, xed3_phash_find_mapevex_map5_opcode0x78_vv2_11_l1}, +/*h(17834)=12 */ {17834, xed3_phash_find_mapevex_map5_opcode0x78_vv2_12_l1}, +/*h(5524)=13 */ {5524, xed3_phash_find_mapevex_map5_opcode0x78_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20884)=15 */ {20884, xed3_phash_find_mapevex_map5_opcode0x78_vv2_15_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9650)=19 */ {9650, xed3_phash_find_mapevex_map5_opcode0x78_vv2_19_l1}, +/*h(25997)=20 */ {25997, xed3_phash_find_mapevex_map5_opcode0x78_vv2_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5558)=22 */ {5558, xed3_phash_find_mapevex_map5_opcode0x78_vv2_22_l1}, +/*h(390)=23 */ {390, xed3_phash_find_mapevex_map5_opcode0x78_vv2_23_l1}, +/*h(15750)=24 */ {15750, xed3_phash_find_mapevex_map5_opcode0x78_vv2_24_l1}, +/*h(8608)=25 */ {8608, xed3_phash_find_mapevex_map5_opcode0x78_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17813)=27 */ {17813, xed3_phash_find_mapevex_map5_opcode0x78_vv2_27_l1}, +/*h(11658)=28 */ {11658, xed3_phash_find_mapevex_map5_opcode0x78_vv2_28_l1}, +/*h(26031)=29 */ {26031, xed3_phash_find_mapevex_map5_opcode0x78_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7566)=31 */ {7566, xed3_phash_find_mapevex_map5_opcode0x78_vv2_31_l1}, +/*h(424)=32 */ {424, xed3_phash_find_mapevex_map5_opcode0x78_vv2_32_l1}, +/*h(21939)=33 */ {21939, xed3_phash_find_mapevex_map5_opcode0x78_vv2_33_l1}, +/*h(3474)=34 */ {3474, xed3_phash_find_mapevex_map5_opcode0x78_vv2_34_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17847)=36 */ {17847, xed3_phash_find_mapevex_map5_opcode0x78_vv2_36_l1}, +/*h(5537)=37 */ {5537, xed3_phash_find_mapevex_map5_opcode0x78_vv2_37_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20897)=39 */ {20897, xed3_phash_find_mapevex_map5_opcode0x78_vv2_39_l1}, +/*h(8587)=40 */ {8587, xed3_phash_find_mapevex_map5_opcode0x78_vv2_40_l1}, +/*h(1445)=41 */ {1445, xed3_phash_find_mapevex_map5_opcode0x78_vv2_41_l1}, +/*h(15818)=42 */ {15818, xed3_phash_find_mapevex_map5_opcode0x78_vv2_42_l1}, +/*h(4495)=43 */ {4495, xed3_phash_find_mapevex_map5_opcode0x78_vv2_43_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11726)=46 */ {11726, xed3_phash_find_mapevex_map5_opcode0x78_vv2_46_l1}, +/*h(403)=47 */ {403, xed3_phash_find_mapevex_map5_opcode0x78_vv2_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7634)=49 */ {7634, xed3_phash_find_mapevex_map5_opcode0x78_vv2_49_l1}, +/*h(24968)=50 */ {24968, xed3_phash_find_mapevex_map5_opcode0x78_vv2_50_l1}, +/*h(11671)=51 */ {11671, xed3_phash_find_mapevex_map5_opcode0x78_vv2_51_l1}, +/*h(5516)=52 */ {5516, xed3_phash_find_mapevex_map5_opcode0x78_vv2_52_l1}, +/*h(3542)=53 */ {3542, xed3_phash_find_mapevex_map5_opcode0x78_vv2_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1424)=55 */ {1424, xed3_phash_find_mapevex_map5_opcode0x78_vv2_55_l1}, +/*h(437)=56 */ {437, xed3_phash_find_mapevex_map5_opcode0x78_vv2_56_l1}, +/*h(16784)=57 */ {16784, xed3_phash_find_mapevex_map5_opcode0x78_vv2_57_l1}, +/*h(9642)=58 */ {9642, xed3_phash_find_mapevex_map5_opcode0x78_vv2_58_l1}, +/*h(25989)=59 */ {25989, xed3_phash_find_mapevex_map5_opcode0x78_vv2_59_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5550)=61 */ {5550, xed3_phash_find_mapevex_map5_opcode0x78_vv2_61_l1}, +/*h(21897)=62 */ {21897, xed3_phash_find_mapevex_map5_opcode0x78_vv2_62_l1}, +/*h(20910)=63 */ {20910, xed3_phash_find_mapevex_map5_opcode0x78_vv2_63_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1458)=65 */ {1458, xed3_phash_find_mapevex_map5_opcode0x78_vv2_65_l1}, +/*h(15831)=66 */ {15831, xed3_phash_find_mapevex_map5_opcode0x78_vv2_66_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26023)=68 */ {26023, xed3_phash_find_mapevex_map5_opcode0x78_vv2_68_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7558)=70 */ {7558, xed3_phash_find_mapevex_map5_opcode0x78_vv2_70_l1}, +/*h(21931)=71 */ {21931, xed3_phash_find_mapevex_map5_opcode0x78_vv2_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3466)=73 */ {3466, xed3_phash_find_mapevex_map5_opcode0x78_vv2_73_l1}, +/*h(24981)=74 */ {24981, xed3_phash_find_mapevex_map5_opcode0x78_vv2_74_l1}, +/*h(17839)=75 */ {17839, xed3_phash_find_mapevex_map5_opcode0x78_vv2_75_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8579)=79 */ {8579, xed3_phash_find_mapevex_map5_opcode0x78_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15810)=81 */ {15810, xed3_phash_find_mapevex_map5_opcode0x78_vv2_81_l1}, +/*h(9655)=82 */ {9655, xed3_phash_find_mapevex_map5_opcode0x78_vv2_82_l1}, +/*h(26002)=83 */ {26002, xed3_phash_find_mapevex_map5_opcode0x78_vv2_83_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11718)=85 */ {11718, xed3_phash_find_mapevex_map5_opcode0x78_vv2_85_l1}, +/*h(21910)=86 */ {21910, xed3_phash_find_mapevex_map5_opcode0x78_vv2_86_l1}, +/*h(9600)=87 */ {9600, xed3_phash_find_mapevex_map5_opcode0x78_vv2_87_l1}, +/*h(7626)=88 */ {7626, xed3_phash_find_mapevex_map5_opcode0x78_vv2_88_l1}, +/*h(24960)=89 */ {24960, xed3_phash_find_mapevex_map5_opcode0x78_vv2_89_l1}, +/*h(11663)=90 */ {11663, xed3_phash_find_mapevex_map5_opcode0x78_vv2_90_l1}, +/*h(3534)=91 */ {3534, xed3_phash_find_mapevex_map5_opcode0x78_vv2_91_l1}, +/*h(26036)=92 */ {26036, xed3_phash_find_mapevex_map5_opcode0x78_vv2_92_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1416)=94 */ {1416, xed3_phash_find_mapevex_map5_opcode0x78_vv2_94_l1}, +/*h(429)=95 */ {429, xed3_phash_find_mapevex_map5_opcode0x78_vv2_95_l1}, +/*h(16776)=96 */ {16776, xed3_phash_find_mapevex_map5_opcode0x78_vv2_96_l1}, +/*h(3479)=97 */ {3479, xed3_phash_find_mapevex_map5_opcode0x78_vv2_97_l1}, +/*h(24994)=98 */ {24994, xed3_phash_find_mapevex_map5_opcode0x78_vv2_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5542)=100 */ {5542, xed3_phash_find_mapevex_map5_opcode0x78_vv2_100_l1}, +/*h(21889)=101 */ {21889, xed3_phash_find_mapevex_map5_opcode0x78_vv2_101_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1450)=103 */ {1450, xed3_phash_find_mapevex_map5_opcode0x78_vv2_103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15823)=105 */ {15823, xed3_phash_find_mapevex_map5_opcode0x78_vv2_105_l1}, +/*h(4500)=106 */ {4500, xed3_phash_find_mapevex_map5_opcode0x78_vv2_106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21923)=110 */ {21923, xed3_phash_find_mapevex_map5_opcode0x78_vv2_110_l1}, +/*h(9613)=111 */ {9613, xed3_phash_find_mapevex_map5_opcode0x78_vv2_111_l1}, +/*h(7639)=112 */ {7639, xed3_phash_find_mapevex_map5_opcode0x78_vv2_112_l1}, +/*h(24973)=113 */ {24973, xed3_phash_find_mapevex_map5_opcode0x78_vv2_113_l1}, +/*h(17831)=114 */ {17831, xed3_phash_find_mapevex_map5_opcode0x78_vv2_114_l1}, +/*h(5521)=115 */ {5521, xed3_phash_find_mapevex_map5_opcode0x78_vv2_115_l1}, +/*h(20881)=116 */ {20881, xed3_phash_find_mapevex_map5_opcode0x78_vv2_116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1429)=118 */ {1429, xed3_phash_find_mapevex_map5_opcode0x78_vv2_118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16789)=120 */ {16789, xed3_phash_find_mapevex_map5_opcode0x78_vv2_120_l1}, +/*h(9647)=121 */ {9647, xed3_phash_find_mapevex_map5_opcode0x78_vv2_121_l1}, +/*h(25994)=122 */ {25994, xed3_phash_find_mapevex_map5_opcode0x78_vv2_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5555)=124 */ {5555, xed3_phash_find_mapevex_map5_opcode0x78_vv2_124_l1}, +/*h(21902)=125 */ {21902, xed3_phash_find_mapevex_map5_opcode0x78_vv2_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7618)=127 */ {7618, xed3_phash_find_mapevex_map5_opcode0x78_vv2_127_l1}, +/*h(17810)=128 */ {17810, xed3_phash_find_mapevex_map5_opcode0x78_vv2_128_l1}, +/*h(11655)=129 */ {11655, xed3_phash_find_mapevex_map5_opcode0x78_vv2_129_l1}, +/*h(3526)=130 */ {3526, xed3_phash_find_mapevex_map5_opcode0x78_vv2_130_l1}, +/*h(26028)=131 */ {26028, xed3_phash_find_mapevex_map5_opcode0x78_vv2_131_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1408)=133 */ {1408, xed3_phash_find_mapevex_map5_opcode0x78_vv2_133_l1}, +/*h(21936)=134 */ {21936, xed3_phash_find_mapevex_map5_opcode0x78_vv2_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3471)=136 */ {3471, xed3_phash_find_mapevex_map5_opcode0x78_vv2_136_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17844)=138 */ {17844, xed3_phash_find_mapevex_map5_opcode0x78_vv2_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8584)=141 */ {8584, xed3_phash_find_mapevex_map5_opcode0x78_vv2_141_l1}, +/*h(1442)=142 */ {1442, xed3_phash_find_mapevex_map5_opcode0x78_vv2_142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15815)=144 */ {15815, xed3_phash_find_mapevex_map5_opcode0x78_vv2_144_l1}, +/*h(4492)=145 */ {4492, xed3_phash_find_mapevex_map5_opcode0x78_vv2_145_l1}, +/*h(26007)=146 */ {26007, xed3_phash_find_mapevex_map5_opcode0x78_vv2_146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(400)=148 */ {400, xed3_phash_find_mapevex_map5_opcode0x78_vv2_148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9605)=150 */ {9605, xed3_phash_find_mapevex_map5_opcode0x78_vv2_150_l1}, +/*h(7631)=151 */ {7631, xed3_phash_find_mapevex_map5_opcode0x78_vv2_151_l1}, +/*h(24965)=152 */ {24965, xed3_phash_find_mapevex_map5_opcode0x78_vv2_152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5513)=154 */ {5513, xed3_phash_find_mapevex_map5_opcode0x78_vv2_154_l1}, +/*h(20873)=155 */ {20873, xed3_phash_find_mapevex_map5_opcode0x78_vv2_155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1421)=157 */ {1421, xed3_phash_find_mapevex_map5_opcode0x78_vv2_157_l1}, +/*h(16781)=158 */ {16781, xed3_phash_find_mapevex_map5_opcode0x78_vv2_158_l1}, +/*h(9639)=159 */ {9639, xed3_phash_find_mapevex_map5_opcode0x78_vv2_159_l1}, +/*h(25986)=160 */ {25986, xed3_phash_find_mapevex_map5_opcode0x78_vv2_160_l1}, +/*h(24999)=161 */ {24999, xed3_phash_find_mapevex_map5_opcode0x78_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5547)=163 */ {5547, xed3_phash_find_mapevex_map5_opcode0x78_vv2_163_l1}, +/*h(21894)=164 */ {21894, xed3_phash_find_mapevex_map5_opcode0x78_vv2_164_l1}, +/*h(8597)=165 */ {8597, xed3_phash_find_mapevex_map5_opcode0x78_vv2_165_l1}, +/*h(1455)=166 */ {1455, xed3_phash_find_mapevex_map5_opcode0x78_vv2_166_l1}, +/*h(17802)=167 */ {17802, xed3_phash_find_mapevex_map5_opcode0x78_vv2_167_l1}, +/*h(16815)=168 */ {16815, xed3_phash_find_mapevex_map5_opcode0x78_vv2_168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26020)=170 */ {26020, xed3_phash_find_mapevex_map5_opcode0x78_vv2_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21928)=173 */ {21928, xed3_phash_find_mapevex_map5_opcode0x78_vv2_173_l1}, +/*h(9618)=174 */ {9618, xed3_phash_find_mapevex_map5_opcode0x78_vv2_174_l1}, +/*h(3463)=175 */ {3463, xed3_phash_find_mapevex_map5_opcode0x78_vv2_175_l1}, +/*h(17836)=176 */ {17836, xed3_phash_find_mapevex_map5_opcode0x78_vv2_176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5526)=178 */ {5526, xed3_phash_find_mapevex_map5_opcode0x78_vv2_178_l1}, +/*h(20886)=179 */ {20886, xed3_phash_find_mapevex_map5_opcode0x78_vv2_179_l1}, +/*h(8576)=180 */ {8576, xed3_phash_find_mapevex_map5_opcode0x78_vv2_180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9652)=183 */ {9652, xed3_phash_find_mapevex_map5_opcode0x78_vv2_183_l1}, +/*h(25999)=184 */ {25999, xed3_phash_find_mapevex_map5_opcode0x78_vv2_184_l1}, +/*h(25012)=185 */ {25012, xed3_phash_find_mapevex_map5_opcode0x78_vv2_185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(392)=187 */ {392, xed3_phash_find_mapevex_map5_opcode0x78_vv2_187_l1}, +/*h(21907)=188 */ {21907, xed3_phash_find_mapevex_map5_opcode0x78_vv2_188_l1}, +/*h(8610)=189 */ {8610, xed3_phash_find_mapevex_map5_opcode0x78_vv2_189_l1}, +/*h(7623)=190 */ {7623, xed3_phash_find_mapevex_map5_opcode0x78_vv2_190_l1}, +/*h(17815)=191 */ {17815, xed3_phash_find_mapevex_map5_opcode0x78_vv2_191_l1}, +/*h(5505)=192 */ {5505, xed3_phash_find_mapevex_map5_opcode0x78_vv2_192_l1}, +/*h(4518)=193 */ {4518, xed3_phash_find_mapevex_map5_opcode0x78_vv2_193_l1}, +/*h(26033)=194 */ {26033, xed3_phash_find_mapevex_map5_opcode0x78_vv2_194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1413)=196 */ {1413, xed3_phash_find_mapevex_map5_opcode0x78_vv2_196_l1}, +/*h(21941)=197 */ {21941, xed3_phash_find_mapevex_map5_opcode0x78_vv2_197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5539)=202 */ {5539, xed3_phash_find_mapevex_map5_opcode0x78_vv2_202_l1}, +/*h(20899)=203 */ {20899, xed3_phash_find_mapevex_map5_opcode0x78_vv2_203_l1}, +/*h(8589)=204 */ {8589, xed3_phash_find_mapevex_map5_opcode0x78_vv2_204_l1}, +/*h(1447)=205 */ {1447, xed3_phash_find_mapevex_map5_opcode0x78_vv2_205_l1}, +/*h(17794)=206 */ {17794, xed3_phash_find_mapevex_map5_opcode0x78_vv2_206_l1}, +/*h(4497)=207 */ {4497, xed3_phash_find_mapevex_map5_opcode0x78_vv2_207_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(405)=211 */ {405, xed3_phash_find_mapevex_map5_opcode0x78_vv2_211_l1}, +/*h(21920)=212 */ {21920, xed3_phash_find_mapevex_map5_opcode0x78_vv2_212_l1}, +/*h(9610)=213 */ {9610, xed3_phash_find_mapevex_map5_opcode0x78_vv2_213_l1}, +/*h(24970)=214 */ {24970, xed3_phash_find_mapevex_map5_opcode0x78_vv2_214_l1}, +/*h(17828)=215 */ {17828, xed3_phash_find_mapevex_map5_opcode0x78_vv2_215_l1}, +/*h(5518)=216 */ {5518, xed3_phash_find_mapevex_map5_opcode0x78_vv2_216_l1}, +/*h(4531)=217 */ {4531, xed3_phash_find_mapevex_map5_opcode0x78_vv2_217_l1}, +/*h(20878)=218 */ {20878, xed3_phash_find_mapevex_map5_opcode0x78_vv2_218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1426)=220 */ {1426, xed3_phash_find_mapevex_map5_opcode0x78_vv2_220_l1}, +/*h(16786)=221 */ {16786, xed3_phash_find_mapevex_map5_opcode0x78_vv2_221_l1}, +/*h(9644)=222 */ {9644, xed3_phash_find_mapevex_map5_opcode0x78_vv2_222_l1}, +/*h(25991)=223 */ {25991, xed3_phash_find_mapevex_map5_opcode0x78_vv2_223_l1}, +/*h(25004)=224 */ {25004, xed3_phash_find_mapevex_map5_opcode0x78_vv2_224_l1}, +/*h(5552)=225 */ {5552, xed3_phash_find_mapevex_map5_opcode0x78_vv2_225_l1}, +/*h(384)=226 */ {384, xed3_phash_find_mapevex_map5_opcode0x78_vv2_226_l1}, +/*h(21899)=227 */ {21899, xed3_phash_find_mapevex_map5_opcode0x78_vv2_227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30117)=229 */ {30117, xed3_phash_find_mapevex_map5_opcode0x78_vv2_229_l1}, +/*h(17807)=230 */ {17807, xed3_phash_find_mapevex_map5_opcode0x78_vv2_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26025)=232 */ {26025, xed3_phash_find_mapevex_map5_opcode0x78_vv2_232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(418)=235 */ {418, xed3_phash_find_mapevex_map5_opcode0x78_vv2_235_l1}, +/*h(21933)=236 */ {21933, xed3_phash_find_mapevex_map5_opcode0x78_vv2_236_l1}, +/*h(9623)=237 */ {9623, xed3_phash_find_mapevex_map5_opcode0x78_vv2_237_l1}, +/*h(24983)=238 */ {24983, xed3_phash_find_mapevex_map5_opcode0x78_vv2_238_l1}, +/*h(17841)=239 */ {17841, xed3_phash_find_mapevex_map5_opcode0x78_vv2_239_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13749)=243 */ {13749, xed3_phash_find_mapevex_map5_opcode0x78_vv2_243_l1}, +/*h(29109)=244 */ {29109, xed3_phash_find_mapevex_map5_opcode0x78_vv2_244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4489)=246 */ {4489, xed3_phash_find_mapevex_map5_opcode0x78_vv2_246_l1}, +/*h(26004)=247 */ {26004, xed3_phash_find_mapevex_map5_opcode0x78_vv2_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(397)=250 */ {397, xed3_phash_find_mapevex_map5_opcode0x78_vv2_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9602)=252 */ {9602, xed3_phash_find_mapevex_map5_opcode0x78_vv2_252_l1}, +/*h(24962)=253 */ {24962, xed3_phash_find_mapevex_map5_opcode0x78_vv2_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5510)=255 */ {5510, xed3_phash_find_mapevex_map5_opcode0x78_vv2_255_l1}, +/*h(26038)=256 */ {26038, xed3_phash_find_mapevex_map5_opcode0x78_vv2_256_l1}, +/*h(20870)=257 */ {20870, xed3_phash_find_mapevex_map5_opcode0x78_vv2_257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1418)=259 */ {1418, xed3_phash_find_mapevex_map5_opcode0x78_vv2_259_l1}, +/*h(16778)=260 */ {16778, xed3_phash_find_mapevex_map5_opcode0x78_vv2_260_l1}, +/*h(9636)=261 */ {9636, xed3_phash_find_mapevex_map5_opcode0x78_vv2_261_l1}, +/*h(24996)=262 */ {24996, xed3_phash_find_mapevex_map5_opcode0x78_vv2_262_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5544)=264 */ {5544, xed3_phash_find_mapevex_map5_opcode0x78_vv2_264_l1}, +/*h(21891)=265 */ {21891, xed3_phash_find_mapevex_map5_opcode0x78_vv2_265_l1}, +/*h(20904)=266 */ {20904, xed3_phash_find_mapevex_map5_opcode0x78_vv2_266_l1}, +/*h(8594)=267 */ {8594, xed3_phash_find_mapevex_map5_opcode0x78_vv2_267_l1}, +/*h(1452)=268 */ {1452, xed3_phash_find_mapevex_map5_opcode0x78_vv2_268_l1}, +/*h(17799)=269 */ {17799, xed3_phash_find_mapevex_map5_opcode0x78_vv2_269_l1}, +/*h(4502)=270 */ {4502, xed3_phash_find_mapevex_map5_opcode0x78_vv2_270_l1}, +/*h(26017)=271 */ {26017, xed3_phash_find_mapevex_map5_opcode0x78_vv2_271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21925)=275 */ {21925, xed3_phash_find_mapevex_map5_opcode0x78_vv2_275_l1}, +/*h(9615)=276 */ {9615, xed3_phash_find_mapevex_map5_opcode0x78_vv2_276_l1}, +/*h(24975)=277 */ {24975, xed3_phash_find_mapevex_map5_opcode0x78_vv2_277_l1}, +/*h(17833)=278 */ {17833, xed3_phash_find_mapevex_map5_opcode0x78_vv2_278_l1}, +/*h(5523)=279 */ {5523, xed3_phash_find_mapevex_map5_opcode0x78_vv2_279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13741)=281 */ {13741, xed3_phash_find_mapevex_map5_opcode0x78_vv2_281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1431)=283 */ {1431, xed3_phash_find_mapevex_map5_opcode0x78_vv2_283_l1}, +/*h(16791)=284 */ {16791, xed3_phash_find_mapevex_map5_opcode0x78_vv2_284_l1}, +/*h(9649)=285 */ {9649, xed3_phash_find_mapevex_map5_opcode0x78_vv2_285_l1}, +/*h(25996)=286 */ {25996, xed3_phash_find_mapevex_map5_opcode0x78_vv2_286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5557)=288 */ {5557, xed3_phash_find_mapevex_map5_opcode0x78_vv2_288_l1}, +/*h(21904)=289 */ {21904, xed3_phash_find_mapevex_map5_opcode0x78_vv2_289_l1}, +/*h(20917)=290 */ {20917, xed3_phash_find_mapevex_map5_opcode0x78_vv2_290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17812)=293 */ {17812, xed3_phash_find_mapevex_map5_opcode0x78_vv2_293_l1}, +/*h(4515)=294 */ {4515, xed3_phash_find_mapevex_map5_opcode0x78_vv2_294_l1}, +/*h(26030)=295 */ {26030, xed3_phash_find_mapevex_map5_opcode0x78_vv2_295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1410)=297 */ {1410, xed3_phash_find_mapevex_map5_opcode0x78_vv2_297_l1}, +/*h(423)=298 */ {423, xed3_phash_find_mapevex_map5_opcode0x78_vv2_298_l1}, +/*h(21938)=299 */ {21938, xed3_phash_find_mapevex_map5_opcode0x78_vv2_299_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17846)=302 */ {17846, xed3_phash_find_mapevex_map5_opcode0x78_vv2_302_l1}, +/*h(5536)=303 */ {5536, xed3_phash_find_mapevex_map5_opcode0x78_vv2_303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20896)=305 */ {20896, xed3_phash_find_mapevex_map5_opcode0x78_vv2_305_l1}, +/*h(30101)=306 */ {30101, xed3_phash_find_mapevex_map5_opcode0x78_vv2_306_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16804)=308 */ {16804, xed3_phash_find_mapevex_map5_opcode0x78_vv2_308_l1}, +/*h(4494)=309 */ {4494, xed3_phash_find_mapevex_map5_opcode0x78_vv2_309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(402)=312 */ {402, xed3_phash_find_mapevex_map5_opcode0x78_vv2_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15762)=314 */ {15762, xed3_phash_find_mapevex_map5_opcode0x78_vv2_314_l1}, +/*h(8620)=315 */ {8620, xed3_phash_find_mapevex_map5_opcode0x78_vv2_315_l1}, +/*h(30135)=316 */ {30135, xed3_phash_find_mapevex_map5_opcode0x78_vv2_316_l1}, +/*h(11670)=317 */ {11670, xed3_phash_find_mapevex_map5_opcode0x78_vv2_317_l1}, +/*h(5515)=318 */ {5515, xed3_phash_find_mapevex_map5_opcode0x78_vv2_318_l1}, +/*h(20875)=319 */ {20875, xed3_phash_find_mapevex_map5_opcode0x78_vv2_319_l1}, +/*h(13733)=320 */ {13733, xed3_phash_find_mapevex_map5_opcode0x78_vv2_320_l1}, +/*h(1423)=321 */ {1423, xed3_phash_find_mapevex_map5_opcode0x78_vv2_321_l1}, +/*h(29093)=322 */ {29093, xed3_phash_find_mapevex_map5_opcode0x78_vv2_322_l1}, +/*h(16783)=323 */ {16783, xed3_phash_find_mapevex_map5_opcode0x78_vv2_323_l1}, +/*h(9641)=324 */ {9641, xed3_phash_find_mapevex_map5_opcode0x78_vv2_324_l1}, +/*h(25988)=325 */ {25988, xed3_phash_find_mapevex_map5_opcode0x78_vv2_325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5549)=327 */ {5549, xed3_phash_find_mapevex_map5_opcode0x78_vv2_327_l1}, +/*h(21896)=328 */ {21896, xed3_phash_find_mapevex_map5_opcode0x78_vv2_328_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1457)=330 */ {1457, xed3_phash_find_mapevex_map5_opcode0x78_vv2_330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15830)=332 */ {15830, xed3_phash_find_mapevex_map5_opcode0x78_vv2_332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26022)=334 */ {26022, xed3_phash_find_mapevex_map5_opcode0x78_vv2_334_l1}, +/*h(12725)=335 */ {12725, xed3_phash_find_mapevex_map5_opcode0x78_vv2_335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21930)=337 */ {21930, xed3_phash_find_mapevex_map5_opcode0x78_vv2_337_l1}, +/*h(9620)=338 */ {9620, xed3_phash_find_mapevex_map5_opcode0x78_vv2_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24980)=340 */ {24980, xed3_phash_find_mapevex_map5_opcode0x78_vv2_340_l1}, +/*h(17838)=341 */ {17838, xed3_phash_find_mapevex_map5_opcode0x78_vv2_341_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8578)=344 */ {8578, xed3_phash_find_mapevex_map5_opcode0x78_vv2_344_l1}, +/*h(30093)=345 */ {30093, xed3_phash_find_mapevex_map5_opcode0x78_vv2_345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9654)=348 */ {9654, xed3_phash_find_mapevex_map5_opcode0x78_vv2_348_l1}, +/*h(26001)=349 */ {26001, xed3_phash_find_mapevex_map5_opcode0x78_vv2_349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(394)=351 */ {394, xed3_phash_find_mapevex_map5_opcode0x78_vv2_351_l1}, +/*h(21909)=352 */ {21909, xed3_phash_find_mapevex_map5_opcode0x78_vv2_352_l1}, +/*h(15754)=353 */ {15754, xed3_phash_find_mapevex_map5_opcode0x78_vv2_353_l1}, +/*h(30127)=354 */ {30127, xed3_phash_find_mapevex_map5_opcode0x78_vv2_354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11662)=356 */ {11662, xed3_phash_find_mapevex_map5_opcode0x78_vv2_356_l1}, +/*h(5507)=357 */ {5507, xed3_phash_find_mapevex_map5_opcode0x78_vv2_357_l1}, +/*h(26035)=358 */ {26035, xed3_phash_find_mapevex_map5_opcode0x78_vv2_358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7570)=360 */ {7570, xed3_phash_find_mapevex_map5_opcode0x78_vv2_360_l1}, +/*h(21943)=361 */ {21943, xed3_phash_find_mapevex_map5_opcode0x78_vv2_361_l1}, +/*h(9633)=362 */ {9633, xed3_phash_find_mapevex_map5_opcode0x78_vv2_362_l1}, +/*h(3478)=363 */ {3478, xed3_phash_find_mapevex_map5_opcode0x78_vv2_363_l1}, +/*h(24993)=364 */ {24993, xed3_phash_find_mapevex_map5_opcode0x78_vv2_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5541)=366 */ {5541, xed3_phash_find_mapevex_map5_opcode0x78_vv2_366_l1}, +/*h(21888)=367 */ {21888, xed3_phash_find_mapevex_map5_opcode0x78_vv2_367_l1}, +/*h(8591)=368 */ {8591, xed3_phash_find_mapevex_map5_opcode0x78_vv2_368_l1}, +/*h(1449)=369 */ {1449, xed3_phash_find_mapevex_map5_opcode0x78_vv2_369_l1}, +/*h(17796)=370 */ {17796, xed3_phash_find_mapevex_map5_opcode0x78_vv2_370_l1}, +/*h(15822)=371 */ {15822, xed3_phash_find_mapevex_map5_opcode0x78_vv2_371_l1}, +/*h(4499)=372 */ {4499, xed3_phash_find_mapevex_map5_opcode0x78_vv2_372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11730)=374 */ {11730, xed3_phash_find_mapevex_map5_opcode0x78_vv2_374_l1}, +/*h(407)=375 */ {407, xed3_phash_find_mapevex_map5_opcode0x78_vv2_375_l1}, +/*h(21922)=376 */ {21922, xed3_phash_find_mapevex_map5_opcode0x78_vv2_376_l1}, +/*h(15767)=377 */ {15767, xed3_phash_find_mapevex_map5_opcode0x78_vv2_377_l1}, +/*h(7638)=378 */ {7638, xed3_phash_find_mapevex_map5_opcode0x78_vv2_378_l1}, +/*h(24972)=379 */ {24972, xed3_phash_find_mapevex_map5_opcode0x78_vv2_379_l1}, +/*h(17830)=380 */ {17830, xed3_phash_find_mapevex_map5_opcode0x78_vv2_380_l1}, +/*h(5520)=381 */ {5520, xed3_phash_find_mapevex_map5_opcode0x78_vv2_381_l1}, +/*h(20880)=382 */ {20880, xed3_phash_find_mapevex_map5_opcode0x78_vv2_382_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30085)=384 */ {30085, xed3_phash_find_mapevex_map5_opcode0x78_vv2_384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9646)=386 */ {9646, xed3_phash_find_mapevex_map5_opcode0x78_vv2_386_l1}, +/*h(25993)=387 */ {25993, xed3_phash_find_mapevex_map5_opcode0x78_vv2_387_l1}, +/*h(25006)=388 */ {25006, xed3_phash_find_mapevex_map5_opcode0x78_vv2_388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5554)=390 */ {5554, xed3_phash_find_mapevex_map5_opcode0x78_vv2_390_l1}, +/*h(15746)=391 */ {15746, xed3_phash_find_mapevex_map5_opcode0x78_vv2_391_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30119)=393 */ {30119, xed3_phash_find_mapevex_map5_opcode0x78_vv2_393_l1}, +/*h(17809)=394 */ {17809, xed3_phash_find_mapevex_map5_opcode0x78_vv2_394_l1}, +/*h(11654)=395 */ {11654, xed3_phash_find_mapevex_map5_opcode0x78_vv2_395_l1}, +/*h(4512)=396 */ {4512, xed3_phash_find_mapevex_map5_opcode0x78_vv2_396_l1}, +/*h(26027)=397 */ {26027, xed3_phash_find_mapevex_map5_opcode0x78_vv2_397_l1}, +/*h(7562)=398 */ {7562, xed3_phash_find_mapevex_map5_opcode0x78_vv2_398_l1}, +/*h(29077)=399 */ {29077, xed3_phash_find_mapevex_map5_opcode0x78_vv2_399_l1}, +/*h(21935)=400 */ {21935, xed3_phash_find_mapevex_map5_opcode0x78_vv2_400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3470)=402 */ {3470, xed3_phash_find_mapevex_map5_opcode0x78_vv2_402_l1}, +/*h(17843)=403 */ {17843, xed3_phash_find_mapevex_map5_opcode0x78_vv2_403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13751)=407 */ {13751, xed3_phash_find_mapevex_map5_opcode0x78_vv2_407_l1}, +/*h(1441)=408 */ {1441, xed3_phash_find_mapevex_map5_opcode0x78_vv2_408_l1}, +/*h(16801)=409 */ {16801, xed3_phash_find_mapevex_map5_opcode0x78_vv2_409_l1}, +/*h(15814)=410 */ {15814, xed3_phash_find_mapevex_map5_opcode0x78_vv2_410_l1}, +/*h(26006)=411 */ {26006, xed3_phash_find_mapevex_map5_opcode0x78_vv2_411_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11722)=413 */ {11722, xed3_phash_find_mapevex_map5_opcode0x78_vv2_413_l1}, +/*h(399)=414 */ {399, xed3_phash_find_mapevex_map5_opcode0x78_vv2_414_l1}, +/*h(15759)=415 */ {15759, xed3_phash_find_mapevex_map5_opcode0x78_vv2_415_l1}, +/*h(9604)=416 */ {9604, xed3_phash_find_mapevex_map5_opcode0x78_vv2_416_l1}, +/*h(7630)=417 */ {7630, xed3_phash_find_mapevex_map5_opcode0x78_vv2_417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5512)=419 */ {5512, xed3_phash_find_mapevex_map5_opcode0x78_vv2_419_l1}, +/*h(3538)=420 */ {3538, xed3_phash_find_mapevex_map5_opcode0x78_vv2_420_l1}, +/*h(20872)=421 */ {20872, xed3_phash_find_mapevex_map5_opcode0x78_vv2_421_l1}, +/*h(7575)=422 */ {7575, xed3_phash_find_mapevex_map5_opcode0x78_vv2_422_l1}, +/*h(1420)=423 */ {1420, xed3_phash_find_mapevex_map5_opcode0x78_vv2_423_l1}, +/*h(16780)=424 */ {16780, xed3_phash_find_mapevex_map5_opcode0x78_vv2_424_l1}, +/*h(9638)=425 */ {9638, xed3_phash_find_mapevex_map5_opcode0x78_vv2_425_l1}, +/*h(25985)=426 */ {25985, xed3_phash_find_mapevex_map5_opcode0x78_vv2_426_l1}, +/*h(24998)=427 */ {24998, xed3_phash_find_mapevex_map5_opcode0x78_vv2_427_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5546)=429 */ {5546, xed3_phash_find_mapevex_map5_opcode0x78_vv2_429_l1}, +/*h(21893)=430 */ {21893, xed3_phash_find_mapevex_map5_opcode0x78_vv2_430_l1}, +/*h(8596)=431 */ {8596, xed3_phash_find_mapevex_map5_opcode0x78_vv2_431_l1}, +/*h(1454)=432 */ {1454, xed3_phash_find_mapevex_map5_opcode0x78_vv2_432_l1}, +/*h(17801)=433 */ {17801, xed3_phash_find_mapevex_map5_opcode0x78_vv2_433_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26019)=435 */ {26019, xed3_phash_find_mapevex_map5_opcode0x78_vv2_435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11735)=437 */ {11735, xed3_phash_find_mapevex_map5_opcode0x78_vv2_437_l1}, +/*h(29069)=438 */ {29069, xed3_phash_find_mapevex_map5_opcode0x78_vv2_438_l1}, +/*h(21927)=439 */ {21927, xed3_phash_find_mapevex_map5_opcode0x78_vv2_439_l1}, +/*h(9617)=440 */ {9617, xed3_phash_find_mapevex_map5_opcode0x78_vv2_440_l1}, +/*h(3462)=441 */ {3462, xed3_phash_find_mapevex_map5_opcode0x78_vv2_441_l1}, +/*h(17835)=442 */ {17835, xed3_phash_find_mapevex_map5_opcode0x78_vv2_442_l1}, +/*h(5525)=443 */ {5525, xed3_phash_find_mapevex_map5_opcode0x78_vv2_443_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20885)=445 */ {20885, xed3_phash_find_mapevex_map5_opcode0x78_vv2_445_l1}, +/*h(13743)=446 */ {13743, xed3_phash_find_mapevex_map5_opcode0x78_vv2_446_l1}, +/*h(29103)=447 */ {29103, xed3_phash_find_mapevex_map5_opcode0x78_vv2_447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9651)=449 */ {9651, xed3_phash_find_mapevex_map5_opcode0x78_vv2_449_l1}, +/*h(25998)=450 */ {25998, xed3_phash_find_mapevex_map5_opcode0x78_vv2_450_l1}, +/*h(25011)=451 */ {25011, xed3_phash_find_mapevex_map5_opcode0x78_vv2_451_l1}, +/*h(11714)=452 */ {11714, xed3_phash_find_mapevex_map5_opcode0x78_vv2_452_l1}, +/*h(5559)=453 */ {5559, xed3_phash_find_mapevex_map5_opcode0x78_vv2_453_l1}, +/*h(15751)=454 */ {15751, xed3_phash_find_mapevex_map5_opcode0x78_vv2_454_l1}, +/*h(7622)=455 */ {7622, xed3_phash_find_mapevex_map5_opcode0x78_vv2_455_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17814)=457 */ {17814, xed3_phash_find_mapevex_map5_opcode0x78_vv2_457_l1}, +/*h(5504)=458 */ {5504, xed3_phash_find_mapevex_map5_opcode0x78_vv2_458_l1}, +/*h(3530)=459 */ {3530, xed3_phash_find_mapevex_map5_opcode0x78_vv2_459_l1}, +/*h(20864)=460 */ {20864, xed3_phash_find_mapevex_map5_opcode0x78_vv2_460_l1}, +/*h(7567)=461 */ {7567, xed3_phash_find_mapevex_map5_opcode0x78_vv2_461_l1}, +/*h(1412)=462 */ {1412, xed3_phash_find_mapevex_map5_opcode0x78_vv2_462_l1}, +/*h(21940)=463 */ {21940, xed3_phash_find_mapevex_map5_opcode0x78_vv2_463_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5538)=467 */ {5538, xed3_phash_find_mapevex_map5_opcode0x78_vv2_467_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20898)=469 */ {20898, xed3_phash_find_mapevex_map5_opcode0x78_vv2_469_l1}, +/*h(8588)=470 */ {8588, xed3_phash_find_mapevex_map5_opcode0x78_vv2_470_l1}, +/*h(30103)=471 */ {30103, xed3_phash_find_mapevex_map5_opcode0x78_vv2_471_l1}, +/*h(17793)=472 */ {17793, xed3_phash_find_mapevex_map5_opcode0x78_vv2_472_l1}, +/*h(4496)=473 */ {4496, xed3_phash_find_mapevex_map5_opcode0x78_vv2_473_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13701)=475 */ {13701, xed3_phash_find_mapevex_map5_opcode0x78_vv2_475_l1}, +/*h(11727)=476 */ {11727, xed3_phash_find_mapevex_map5_opcode0x78_vv2_476_l1}, +/*h(29061)=477 */ {29061, xed3_phash_find_mapevex_map5_opcode0x78_vv2_477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9609)=479 */ {9609, xed3_phash_find_mapevex_map5_opcode0x78_vv2_479_l1}, +/*h(24969)=480 */ {24969, xed3_phash_find_mapevex_map5_opcode0x78_vv2_480_l1}, +/*h(17827)=481 */ {17827, xed3_phash_find_mapevex_map5_opcode0x78_vv2_481_l1}, +/*h(5517)=482 */ {5517, xed3_phash_find_mapevex_map5_opcode0x78_vv2_482_l1}, +/*h(3543)=483 */ {3543, xed3_phash_find_mapevex_map5_opcode0x78_vv2_483_l1}, +/*h(13735)=484 */ {13735, xed3_phash_find_mapevex_map5_opcode0x78_vv2_484_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1425)=486 */ {1425, xed3_phash_find_mapevex_map5_opcode0x78_vv2_486_l1}, +/*h(16785)=487 */ {16785, xed3_phash_find_mapevex_map5_opcode0x78_vv2_487_l1}, +/*h(9643)=488 */ {9643, xed3_phash_find_mapevex_map5_opcode0x78_vv2_488_l1}, +/*h(25990)=489 */ {25990, xed3_phash_find_mapevex_map5_opcode0x78_vv2_489_l1}, +/*h(12693)=490 */ {12693, xed3_phash_find_mapevex_map5_opcode0x78_vv2_490_l1}, +/*h(5551)=491 */ {5551, xed3_phash_find_mapevex_map5_opcode0x78_vv2_491_l1}, +/*h(21898)=492 */ {21898, xed3_phash_find_mapevex_map5_opcode0x78_vv2_492_l1}, +/*h(20911)=493 */ {20911, xed3_phash_find_mapevex_map5_opcode0x78_vv2_493_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1459)=495 */ {1459, xed3_phash_find_mapevex_map5_opcode0x78_vv2_495_l1}, +/*h(17806)=496 */ {17806, xed3_phash_find_mapevex_map5_opcode0x78_vv2_496_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3522)=498 */ {3522, xed3_phash_find_mapevex_map5_opcode0x78_vv2_498_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7559)=500 */ {7559, xed3_phash_find_mapevex_map5_opcode0x78_vv2_500_l1}, +/*h(417)=501 */ {417, xed3_phash_find_mapevex_map5_opcode0x78_vv2_501_l1}, +/*h(21932)=502 */ {21932, xed3_phash_find_mapevex_map5_opcode0x78_vv2_502_l1}, +/*h(9622)=503 */ {9622, xed3_phash_find_mapevex_map5_opcode0x78_vv2_503_l1}, +/*h(24982)=504 */ {24982, xed3_phash_find_mapevex_map5_opcode0x78_vv2_504_l1}, +/*h(17840)=505 */ {17840, xed3_phash_find_mapevex_map5_opcode0x78_vv2_505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8580)=509 */ {8580, xed3_phash_find_mapevex_map5_opcode0x78_vv2_509_l1}, +/*h(30095)=510 */ {30095, xed3_phash_find_mapevex_map5_opcode0x78_vv2_510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4488)=512 */ {4488, xed3_phash_find_mapevex_map5_opcode0x78_vv2_512_l1}, +/*h(26003)=513 */ {26003, xed3_phash_find_mapevex_map5_opcode0x78_vv2_513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11719)=515 */ {11719, xed3_phash_find_mapevex_map5_opcode0x78_vv2_515_l1}, +/*h(21911)=516 */ {21911, xed3_phash_find_mapevex_map5_opcode0x78_vv2_516_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9601)=518 */ {9601, xed3_phash_find_mapevex_map5_opcode0x78_vv2_518_l1}, +/*h(24961)=519 */ {24961, xed3_phash_find_mapevex_map5_opcode0x78_vv2_519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5509)=521 */ {5509, xed3_phash_find_mapevex_map5_opcode0x78_vv2_521_l1}, +/*h(3535)=522 */ {3535, xed3_phash_find_mapevex_map5_opcode0x78_vv2_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1417)=524 */ {1417, xed3_phash_find_mapevex_map5_opcode0x78_vv2_524_l1}, +/*h(430)=525 */ {430, xed3_phash_find_mapevex_map5_opcode0x78_vv2_525_l1}, +/*h(16777)=526 */ {16777, xed3_phash_find_mapevex_map5_opcode0x78_vv2_526_l1}, +/*h(9635)=527 */ {9635, xed3_phash_find_mapevex_map5_opcode0x78_vv2_527_l1}, +/*h(24995)=528 */ {24995, xed3_phash_find_mapevex_map5_opcode0x78_vv2_528_l1}, +/*h(12685)=529 */ {12685, xed3_phash_find_mapevex_map5_opcode0x78_vv2_529_l1}, +/*h(5543)=530 */ {5543, xed3_phash_find_mapevex_map5_opcode0x78_vv2_530_l1}, +/*h(21890)=531 */ {21890, xed3_phash_find_mapevex_map5_opcode0x78_vv2_531_l1}, +/*h(20903)=532 */ {20903, xed3_phash_find_mapevex_map5_opcode0x78_vv2_532_l1}, +/*h(8593)=533 */ {8593, xed3_phash_find_mapevex_map5_opcode0x78_vv2_533_l1}, +/*h(1451)=534 */ {1451, xed3_phash_find_mapevex_map5_opcode0x78_vv2_534_l1}, +/*h(17798)=535 */ {17798, xed3_phash_find_mapevex_map5_opcode0x78_vv2_535_l1}, +/*h(4501)=536 */ {4501, xed3_phash_find_mapevex_map5_opcode0x78_vv2_536_l1}, +/*h(26016)=537 */ {26016, xed3_phash_find_mapevex_map5_opcode0x78_vv2_537_l1}, +/*h(12719)=538 */ {12719, xed3_phash_find_mapevex_map5_opcode0x78_vv2_538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21924)=540 */ {21924, xed3_phash_find_mapevex_map5_opcode0x78_vv2_540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9614)=542 */ {9614, xed3_phash_find_mapevex_map5_opcode0x78_vv2_542_l1}, +/*h(24974)=543 */ {24974, xed3_phash_find_mapevex_map5_opcode0x78_vv2_543_l1}, +/*h(17832)=544 */ {17832, xed3_phash_find_mapevex_map5_opcode0x78_vv2_544_l1}, +/*h(5522)=545 */ {5522, xed3_phash_find_mapevex_map5_opcode0x78_vv2_545_l1}, +/*h(20882)=546 */ {20882, xed3_phash_find_mapevex_map5_opcode0x78_vv2_546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30087)=548 */ {30087, xed3_phash_find_mapevex_map5_opcode0x78_vv2_548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16790)=550 */ {16790, xed3_phash_find_mapevex_map5_opcode0x78_vv2_550_l1}, +/*h(9648)=551 */ {9648, xed3_phash_find_mapevex_map5_opcode0x78_vv2_551_l1}, +/*h(25995)=552 */ {25995, xed3_phash_find_mapevex_map5_opcode0x78_vv2_552_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5556)=554 */ {5556, xed3_phash_find_mapevex_map5_opcode0x78_vv2_554_l1}, +/*h(21903)=555 */ {21903, xed3_phash_find_mapevex_map5_opcode0x78_vv2_555_l1}, +/*h(20916)=556 */ {20916, xed3_phash_find_mapevex_map5_opcode0x78_vv2_556_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17811)=559 */ {17811, xed3_phash_find_mapevex_map5_opcode0x78_vv2_559_l1}, +/*h(3527)=560 */ {3527, xed3_phash_find_mapevex_map5_opcode0x78_vv2_560_l1}, +/*h(26029)=561 */ {26029, xed3_phash_find_mapevex_map5_opcode0x78_vv2_561_l1}, +/*h(13719)=562 */ {13719, xed3_phash_find_mapevex_map5_opcode0x78_vv2_562_l1}, +/*h(1409)=563 */ {1409, xed3_phash_find_mapevex_map5_opcode0x78_vv2_563_l1}, +/*h(21937)=564 */ {21937, xed3_phash_find_mapevex_map5_opcode0x78_vv2_564_l1}, +/*h(16769)=565 */ {16769, xed3_phash_find_mapevex_map5_opcode0x78_vv2_565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17845)=568 */ {17845, xed3_phash_find_mapevex_map5_opcode0x78_vv2_568_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8585)=571 */ {8585, xed3_phash_find_mapevex_map5_opcode0x78_vv2_571_l1}, +/*h(1443)=572 */ {1443, xed3_phash_find_mapevex_map5_opcode0x78_vv2_572_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16803)=574 */ {16803, xed3_phash_find_mapevex_map5_opcode0x78_vv2_574_l1}, +/*h(4493)=575 */ {4493, xed3_phash_find_mapevex_map5_opcode0x78_vv2_575_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12711)=577 */ {12711, xed3_phash_find_mapevex_map5_opcode0x78_vv2_577_l1}, +/*h(401)=578 */ {401, xed3_phash_find_mapevex_map5_opcode0x78_vv2_578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9606)=580 */ {9606, xed3_phash_find_mapevex_map5_opcode0x78_vv2_580_l1}, +/*h(8619)=581 */ {8619, xed3_phash_find_mapevex_map5_opcode0x78_vv2_581_l1}, +/*h(24966)=582 */ {24966, xed3_phash_find_mapevex_map5_opcode0x78_vv2_582_l1}, +/*h(17824)=583 */ {17824, xed3_phash_find_mapevex_map5_opcode0x78_vv2_583_l1}, +/*h(5514)=584 */ {5514, xed3_phash_find_mapevex_map5_opcode0x78_vv2_584_l1}, +/*h(20874)=585 */ {20874, xed3_phash_find_mapevex_map5_opcode0x78_vv2_585_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1422)=587 */ {1422, xed3_phash_find_mapevex_map5_opcode0x78_vv2_587_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9640)=589 */ {9640, xed3_phash_find_mapevex_map5_opcode0x78_vv2_589_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25987)=591 */ {25987, xed3_phash_find_mapevex_map5_opcode0x78_vv2_591_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5548)=593 */ {5548, xed3_phash_find_mapevex_map5_opcode0x78_vv2_593_l1}, +/*h(21895)=594 */ {21895, xed3_phash_find_mapevex_map5_opcode0x78_vv2_594_l1}, +/*h(8598)=595 */ {8598, xed3_phash_find_mapevex_map5_opcode0x78_vv2_595_l1}, +/*h(1456)=596 */ {1456, xed3_phash_find_mapevex_map5_opcode0x78_vv2_596_l1}, +/*h(17803)=597 */ {17803, xed3_phash_find_mapevex_map5_opcode0x78_vv2_597_l1}, +/*h(16816)=598 */ {16816, xed3_phash_find_mapevex_map5_opcode0x78_vv2_598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26021)=600 */ {26021, xed3_phash_find_mapevex_map5_opcode0x78_vv2_600_l1}, +/*h(13711)=601 */ {13711, xed3_phash_find_mapevex_map5_opcode0x78_vv2_601_l1}, +/*h(29071)=602 */ {29071, xed3_phash_find_mapevex_map5_opcode0x78_vv2_602_l1}, +/*h(21929)=603 */ {21929, xed3_phash_find_mapevex_map5_opcode0x78_vv2_603_l1}, +/*h(9619)=604 */ {9619, xed3_phash_find_mapevex_map5_opcode0x78_vv2_604_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24979)=606 */ {24979, xed3_phash_find_mapevex_map5_opcode0x78_vv2_606_l1}, +/*h(17837)=607 */ {17837, xed3_phash_find_mapevex_map5_opcode0x78_vv2_607_l1}, +/*h(5527)=608 */ {5527, xed3_phash_find_mapevex_map5_opcode0x78_vv2_608_l1}, +/*h(20887)=609 */ {20887, xed3_phash_find_mapevex_map5_opcode0x78_vv2_609_l1}, +/*h(8577)=610 */ {8577, xed3_phash_find_mapevex_map5_opcode0x78_vv2_610_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9653)=613 */ {9653, xed3_phash_find_mapevex_map5_opcode0x78_vv2_613_l1}, +/*h(4485)=614 */ {4485, xed3_phash_find_mapevex_map5_opcode0x78_vv2_614_l1}, +/*h(26000)=615 */ {26000, xed3_phash_find_mapevex_map5_opcode0x78_vv2_615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(393)=617 */ {393, xed3_phash_find_mapevex_map5_opcode0x78_vv2_617_l1}, +/*h(21908)=618 */ {21908, xed3_phash_find_mapevex_map5_opcode0x78_vv2_618_l1}, +/*h(8611)=619 */ {8611, xed3_phash_find_mapevex_map5_opcode0x78_vv2_619_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5506)=623 */ {5506, xed3_phash_find_mapevex_map5_opcode0x78_vv2_623_l1}, +/*h(26034)=624 */ {26034, xed3_phash_find_mapevex_map5_opcode0x78_vv2_624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1414)=626 */ {1414, xed3_phash_find_mapevex_map5_opcode0x78_vv2_626_l1}, +/*h(21942)=627 */ {21942, xed3_phash_find_mapevex_map5_opcode0x78_vv2_627_l1}, +/*h(9632)=628 */ {9632, xed3_phash_find_mapevex_map5_opcode0x78_vv2_628_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24992)=630 */ {24992, xed3_phash_find_mapevex_map5_opcode0x78_vv2_630_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5540)=632 */ {5540, xed3_phash_find_mapevex_map5_opcode0x78_vv2_632_l1}, +/*h(20900)=633 */ {20900, xed3_phash_find_mapevex_map5_opcode0x78_vv2_633_l1}, +/*h(8590)=634 */ {8590, xed3_phash_find_mapevex_map5_opcode0x78_vv2_634_l1}, +/*h(1448)=635 */ {1448, xed3_phash_find_mapevex_map5_opcode0x78_vv2_635_l1}, +/*h(17795)=636 */ {17795, xed3_phash_find_mapevex_map5_opcode0x78_vv2_636_l1}, +/*h(16808)=637 */ {16808, xed3_phash_find_mapevex_map5_opcode0x78_vv2_637_l1}, +/*h(4498)=638 */ {4498, xed3_phash_find_mapevex_map5_opcode0x78_vv2_638_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13703)=640 */ {13703, xed3_phash_find_mapevex_map5_opcode0x78_vv2_640_l1}, +/*h(29063)=641 */ {29063, xed3_phash_find_mapevex_map5_opcode0x78_vv2_641_l1}, +/*h(21921)=642 */ {21921, xed3_phash_find_mapevex_map5_opcode0x78_vv2_642_l1}, +/*h(15766)=643 */ {15766, xed3_phash_find_mapevex_map5_opcode0x78_vv2_643_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17829)=645 */ {17829, xed3_phash_find_mapevex_map5_opcode0x78_vv2_645_l1}, +/*h(5519)=646 */ {5519, xed3_phash_find_mapevex_map5_opcode0x78_vv2_646_l1}, +/*h(4532)=647 */ {4532, xed3_phash_find_mapevex_map5_opcode0x78_vv2_647_l1}, +/*h(20879)=648 */ {20879, xed3_phash_find_mapevex_map5_opcode0x78_vv2_648_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1427)=650 */ {1427, xed3_phash_find_mapevex_map5_opcode0x78_vv2_650_l1}, +/*h(16787)=651 */ {16787, xed3_phash_find_mapevex_map5_opcode0x78_vv2_651_l1}, +/*h(9645)=652 */ {9645, xed3_phash_find_mapevex_map5_opcode0x78_vv2_652_l1}, +/*h(25992)=653 */ {25992, xed3_phash_find_mapevex_map5_opcode0x78_vv2_653_l1}, +/*h(25005)=654 */ {25005, xed3_phash_find_mapevex_map5_opcode0x78_vv2_654_l1}, +/*h(12695)=655 */ {12695, xed3_phash_find_mapevex_map5_opcode0x78_vv2_655_l1}, +/*h(5553)=656 */ {5553, xed3_phash_find_mapevex_map5_opcode0x78_vv2_656_l1}, +/*h(21900)=657 */ {21900, xed3_phash_find_mapevex_map5_opcode0x78_vv2_657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1461)=659 */ {1461, xed3_phash_find_mapevex_map5_opcode0x78_vv2_659_l1}, +/*h(17808)=660 */ {17808, xed3_phash_find_mapevex_map5_opcode0x78_vv2_660_l1}, +/*h(16821)=661 */ {16821, xed3_phash_find_mapevex_map5_opcode0x78_vv2_661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26026)=663 */ {26026, xed3_phash_find_mapevex_map5_opcode0x78_vv2_663_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(419)=665 */ {419, xed3_phash_find_mapevex_map5_opcode0x78_vv2_665_l1}, +/*h(21934)=666 */ {21934, xed3_phash_find_mapevex_map5_opcode0x78_vv2_666_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17842)=669 */ {17842, xed3_phash_find_mapevex_map5_opcode0x78_vv2_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8582)=673 */ {8582, xed3_phash_find_mapevex_map5_opcode0x78_vv2_673_l1}, +/*h(1440)=674 */ {1440, xed3_phash_find_mapevex_map5_opcode0x78_vv2_674_l1}, +/*h(16800)=675 */ {16800, xed3_phash_find_mapevex_map5_opcode0x78_vv2_675_l1}, +/*h(4490)=676 */ {4490, xed3_phash_find_mapevex_map5_opcode0x78_vv2_676_l1}, +/*h(26005)=677 */ {26005, xed3_phash_find_mapevex_map5_opcode0x78_vv2_677_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(398)=680 */ {398, xed3_phash_find_mapevex_map5_opcode0x78_vv2_680_l1}, +/*h(15758)=681 */ {15758, xed3_phash_find_mapevex_map5_opcode0x78_vv2_681_l1}, +/*h(9603)=682 */ {9603, xed3_phash_find_mapevex_map5_opcode0x78_vv2_682_l1}, +/*h(24963)=683 */ {24963, xed3_phash_find_mapevex_map5_opcode0x78_vv2_683_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11666)=685 */ {11666, xed3_phash_find_mapevex_map5_opcode0x78_vv2_685_l1}, +/*h(26039)=686 */ {26039, xed3_phash_find_mapevex_map5_opcode0x78_vv2_686_l1}, +/*h(20871)=687 */ {20871, xed3_phash_find_mapevex_map5_opcode0x78_vv2_687_l1}, +/*h(7574)=688 */ {7574, xed3_phash_find_mapevex_map5_opcode0x78_vv2_688_l1}, +/*h(1419)=689 */ {1419, xed3_phash_find_mapevex_map5_opcode0x78_vv2_689_l1}, +/*h(16779)=690 */ {16779, xed3_phash_find_mapevex_map5_opcode0x78_vv2_690_l1}, +/*h(9637)=691 */ {9637, xed3_phash_find_mapevex_map5_opcode0x78_vv2_691_l1}, +/*h(25984)=692 */ {25984, xed3_phash_find_mapevex_map5_opcode0x78_vv2_692_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5545)=694 */ {5545, xed3_phash_find_mapevex_map5_opcode0x78_vv2_694_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 696ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5556)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5556, 7098}, +/*h(388)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {388, 7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16772)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16772, 7089}, +/*h(21940)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21940, 7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(420)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {420, 7089}, +/*h(29077)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29077, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16804)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_516_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(396)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {396, 7089}, +/*h(21911)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21911, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16780)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16780; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7570)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7570, 7151}, +/*h(1415)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1415, 7101}, +/*h(428)=2 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {428, 7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16812)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16812, 7089}, +/*h(17799)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17799, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(404)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {404, 7089}, +/*h(29061)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29061, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16788)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16788, 7089}, +/*h(9646)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9646, 7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(436)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {436, 7089}, +/*h(29093)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29093, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16820)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16820, 7089}, +/*h(17807)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17807, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(390)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21942)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21942, 7098}, +/*h(16774)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16774, 7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_563_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(422)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {422, 7089}, +/*h(1409)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1409, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16806)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16806, 7089}, +/*h(17793)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17793, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(398)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16782)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16782, 7089}, +/*h(9640)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9640, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(430)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16814)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16814, 7089}, +/*h(17801)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17801, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_641_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(406)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {406, 7089}, +/*h(29063)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29063, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_550_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16790)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29095)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29095, 7094}, +/*h(1425)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1425, 7097}, +/*h(438)=2 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {438, 7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11654)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11654, 7152}, +/*h(16822)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16822, 7089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(384)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 384; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21936)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21936, 7099}, +/*h(16768)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16768, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(416)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {416, 7090}, +/*h(21931)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21931, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16800)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(392)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16776)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(424)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16808)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(400)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 400; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16784)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_689_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(432)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {432, 7090}, +/*h(1419)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1419, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16816)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(386)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {386, 7090}, +/*h(5554)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5554, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_299_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16770)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16770, 7090}, +/*h(21938)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21938, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(418)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16802)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16802, 7090}, +/*h(15815)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15815, 7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(394)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16778)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(426)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {426, 7090}, +/*h(1413)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1413, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16810)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16810, 7090}, +/*h(15823)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15823, 7153}, +/*h(17797)=2 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17797, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(402)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 402; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_221_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16786)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(434)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {434, 7090}, +/*h(1421)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1421, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(17805)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17805, 7101}, +/*h(11650)=1 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11650, 7154}, +/*h(16818)=2 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16818, 7090}, +/*h(15831)=3 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15831, 7156} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5553)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5553, 7099}, +/*h(385)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {385, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16769)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16769; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(417)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16801)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(393)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16777)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16777; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1412)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1412, 7096}, +/*h(425)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {425, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15822)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15822, 7152}, +/*h(16809)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16809, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(401)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 401; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16785)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1420)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1420, 7096}, +/*h(433)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {433, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15830)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15830, 7155}, +/*h(16817)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16817, 7090}, +/*h(17804)=2 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17804, 7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(387)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {387, 7090}, +/*h(5555)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5555, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21939)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21939, 7099}, +/*h(16771)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16771, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(419)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 419; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16803)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11718)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11718, 7152}, +/*h(395)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {395, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16779)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16779; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_626_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1414)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1414, 7096}, +/*h(427)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {427, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17798)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17798, 7096}, +/*h(16811)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16811, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(403)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 403; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16787)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16787; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1422)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1422, 7096}, +/*h(435)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {435, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17806)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17806, 7096}, +/*h(16819)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {16819, 7090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4484)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4484, 7091}, +/*h(25999)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25999, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20868)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20868, 7091}, +/*h(26036)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {26036, 7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11658)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11658, 7154}, +/*h(4516)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4516, 7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20900)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4492)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4492; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20876)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20876, 7091}, +/*h(3542)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3542, 7155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4524)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4524, 7091}, +/*h(26039)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {26039, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20908)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20908, 7091}, +/*h(21895)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21895, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4500)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4500; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20884)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4532)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4532; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20916)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20916; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9654)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9654, 7100}, +/*h(4486)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4486, 7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20870)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4518)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20902)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20902, 7091}, +/*h(21889)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21889, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4494)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20878)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4526)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4526, 7091}, +/*h(5513)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5513, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20910)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4502)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20886)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4534)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4534, 7091}, +/*h(5521)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5521, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21905)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21905, 7099}, +/*h(15750)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15750, 7152}, +/*h(20918)=2 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20918, 7091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9648)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9648, 7102}, +/*h(4480)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4480, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20864)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4512)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20896)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4488)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20872)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_357_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4520)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4520, 7092}, +/*h(5507)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5507, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20904)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4496)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20880)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4528)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4528, 7092}, +/*h(5515)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5515, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20912)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20912, 7092}, +/*h(21899)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21899, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4482)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4482, 7092}, +/*h(9650)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9650, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_624_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26034)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26034, 7102}, +/*h(20866)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20866, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4514)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4514, 7092}, +/*h(3527)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3527, 7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20898)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4490)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20874)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4522)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4522, 7092}, +/*h(5509)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5509, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20906)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20906, 7092}, +/*h(21893)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21893, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4498)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20882)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4530)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4530, 7092}, +/*h(3543)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3543, 7156} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21901)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21901, 7101}, +/*h(20914)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20914, 7092}, +/*h(15746)=2 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15746, 7154} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4481)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4481, 7092}, +/*h(9649)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9649, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20865)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20865, 7092}, +/*h(26033)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26033, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3526)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3526, 7152}, +/*h(4513)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4513, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20897)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4489)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20873)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4521)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4521, 7092}, +/*h(5508)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5508, 7098}, +/*h(3534)=2 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3534, 7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21892)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21892, 7098}, +/*h(20905)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20905, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4497)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4497; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20881)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5516)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5516, 7098}, +/*h(4529)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4529, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21900)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21900, 7098}, +/*h(20913)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20913, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_449_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9651)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9651, 7102}, +/*h(4483)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4483, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20867)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20867, 7092}, +/*h(26035)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26035, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4515)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20899)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26006)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {26006, 7100}, +/*h(4491)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4491, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20875)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5510)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5510, 7098}, +/*h(4523)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {4523, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21894)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21894, 7098}, +/*h(20907)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20907, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4499)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20883)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20883, 7092}, +/*h(13741)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13741, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4531)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21902)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21902, 7098}, +/*h(20915)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {20915, 7092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8580)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7630)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7630, 7152}, +/*h(24964)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24964, 7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8612)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8612, 7093}, +/*h(30127)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30127, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24996)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8588)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24972)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8620)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25004)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8596)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24980)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8628)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8628, 7093}, +/*h(9615)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9615, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25012)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25012; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8582)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_582_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24966)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8614)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8614, 7093}, +/*h(9601)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9601, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24998)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8590)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_543_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24974)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8622)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8622, 7093}, +/*h(9609)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9609, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25006)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8598)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24982)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24982; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8630)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8630, 7093}, +/*h(9617)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9617, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25014)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25014, 7093}, +/*h(26001)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26001, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(389)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {389, 7094}, +/*h(5557)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5557, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16773)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16773, 7094}, +/*h(21941)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21941, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4485)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4485; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3535)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3535, 7153}, +/*h(26037)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {26037, 7101}, +/*h(20869)=2 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20869, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13749)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13749, 7101}, +/*h(8581)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8581, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24965)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12677)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12677, 7094}, +/*h(17845)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17845, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1408)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1408, 7097}, +/*h(421)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {421, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(15818)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15818, 7154}, +/*h(17792)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17792, 7097}, +/*h(16805)=2 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16805, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4517)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4517, 7094}, +/*h(3530)=1 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3530, 7154}, +/*h(26032)=2 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26032, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21888)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21888, 7099}, +/*h(20901)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20901, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7626)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7626, 7154}, +/*h(8613)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8613, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25984)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25984, 7102}, +/*h(24997)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24997, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11722)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11722, 7154}, +/*h(12709)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12709, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(397)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16781)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4493)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4493; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_484_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20877)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20877, 7094}, +/*h(13735)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13735, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8589)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24973)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24973; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12685)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29069)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(429)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17800)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17800, 7097}, +/*h(16813)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16813, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3538)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3538, 7157}, +/*h(4525)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4525, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21896)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21896, 7099}, +/*h(20909)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20909, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8621)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8621, 7094}, +/*h(9608)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9608, 7102}, +/*h(7634)=2 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7634, 7157} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25005)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11730)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11730, 7157}, +/*h(12717)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12717, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1431)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1431, 7101}, +/*h(29101)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29101, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(405)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 405; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16789)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16789; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4501)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4501; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20885)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20885; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8597)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24981)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12693)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12693; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(437)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16821)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_381_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5520)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5520, 7099}, +/*h(4533)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4533, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20917)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9616)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9616, 7102}, +/*h(8629)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8629, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_615_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26000)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26000, 7102}, +/*h(25013)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25013, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12725)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29109)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29109; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5559)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5559, 7101}, +/*h(391)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {391, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9633)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9633, 7102}, +/*h(16775)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16775, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4487)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4487, 7094}, +/*h(9655)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9655, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_687_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20871)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8583)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8583, 7094}, +/*h(13751)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13751, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_316_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(30135)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30135, 7101}, +/*h(24967)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24967, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17847)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17847, 7101}, +/*h(12679)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12679, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17794)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17794, 7097}, +/*h(16807)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16807, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_623_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5506)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5506, 7099}, +/*h(4519)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4519, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20903)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_252_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9602)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9602, 7102}, +/*h(8615)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8615, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24999)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12711)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(399)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16783)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4495)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20879)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8591)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24975)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12687)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12687, 7094}, +/*h(5545)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5545, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29071)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1418)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1418, 7097}, +/*h(431)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {431, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16815)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5514)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5514, 7099}, +/*h(4527)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4527, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20911)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9610)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9610, 7102}, +/*h(8623)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8623, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25994)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25994, 7102}, +/*h(25007)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25007, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12719)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29103)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(407)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 407; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16791)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15826)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15826, 7157}, +/*h(4503)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4503, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20887)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1457)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1457, 7097}, +/*h(8599)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8599, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24983)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24983; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12695)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(29079)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29079, 7094}, +/*h(21937)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21937, 7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1426)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1426, 7097}, +/*h(439)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {439, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11655)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11655, 7153}, +/*h(16823)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16823, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5522)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {5522, 7099}, +/*h(4535)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4535, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20919)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20919, 7094}, +/*h(21906)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {21906, 7099}, +/*h(15751)=2 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15751, 7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9618)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9618, 7102}, +/*h(8631)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8631, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26002)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26002, 7102}, +/*h(25015)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25015, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7559)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7559, 7153}, +/*h(12727)=1 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12727, 7094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(29111)=0 EVV 0x79 VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29111, 7094}, +/*h(1441)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1441, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8576)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24960)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8608)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24992)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8584)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24968)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24968; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_682_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8616)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8616, 7095}, +/*h(9603)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9603, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25000)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25000, 7095}, +/*h(25987)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25987, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8592)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8592, 7095}, +/*h(1450)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1450, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24976)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_643_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9611)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9611, 7102}, +/*h(15766)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15766, 7149}, +/*h(8624)=2 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8624, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25008)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25008, 7095}, +/*h(25995)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {25995, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8578)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24962)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8610)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24994)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8586)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8586, 7095}, +/*h(1444)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1444, 7096}, +/*h(30101)=2 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30101, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24970)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8618)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8618, 7095}, +/*h(9605)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9605, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25002)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25002, 7095}, +/*h(25989)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25989, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8594)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24978)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {24978, 7095}, +/*h(17836)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17836, 7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8626)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8626, 7095}, +/*h(3458)=1 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3458, 7154}, +/*h(7639)=2 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7639, 7156} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25010)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25010, 7095}, +/*h(25997)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25997, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8577)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24961)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7622)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7622, 7152}, +/*h(8609)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8609, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24993)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8585)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24969)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_416_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9604)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9604, 7100}, +/*h(8617)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8617, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25988)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25988, 7100}, +/*h(25001)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25001, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8593)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3462)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3462, 7152}, +/*h(24977)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {24977, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7638)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7638, 7155}, +/*h(8625)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8625, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25996)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25996, 7100}, +/*h(25009)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25009, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8579)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_683_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24963)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8611)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24995)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8587)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_645_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17829)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17829, 7101}, +/*h(24971)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {24971, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8619)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25990)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25990, 7100}, +/*h(25003)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {25003, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8595)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24979)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9614)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9614, 7100}, +/*h(8627)=1 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {8627, 7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25011)=0 EVV 0x79 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {7095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17796)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17828)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17828; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1452)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_384_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1428)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1428, 7096}, +/*h(30085)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30085, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17812)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1460)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1460, 7096}, +/*h(30117)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30117, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17844)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1446)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1446, 7096}, +/*h(30103)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30103, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17830)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1454)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17838)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_548_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1430)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1430, 7096}, +/*h(30087)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30087, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17814)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1462)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1462, 7096}, +/*h(30119)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30119, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17846)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1440)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1440; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17824)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17824; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1416)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1448)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17832)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1424)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17808)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17808; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1456)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17840)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1410)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1442)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17826)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17826, 7097}, +/*h(11671)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11671, 7150} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17802)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17834)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17810)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1458)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17842)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11670)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11670, 7149}, +/*h(17825)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {17825, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1417)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1417; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1449)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17833)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17809)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17841)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7566)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7566, 7152}, +/*h(1411)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {1411, 7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17795)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1443)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17827)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17803)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1451)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17835)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1427)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1427; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17811)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1459)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17843)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5540)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5540; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21924)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5548)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21932)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5524)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5524; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21908)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5542)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21926)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5518)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5550)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21934)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5526)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21910)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5558)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7098} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5504)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5536)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5536; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21920)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5512)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5544)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21928)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21904)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5552)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5552; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_531_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21890)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5538)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21922)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21898)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5546)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21930)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5505)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5505; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5537)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21921)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21921; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21897)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21929)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21891)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5539)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21923)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5547)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5523)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21907)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7099} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9636)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26020)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9612)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9612, 7100}, +/*h(15767)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15767, 7150} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9644)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26028)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9620)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26004)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9652)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9606)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9638)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26022)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25998)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26030)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9622)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26038)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7100} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13701)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1445)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5541)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5541; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21925)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21925; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9637)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26021)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26021; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13733)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5517)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9613)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9613; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7554)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7554, 7154}, +/*h(11735)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11735, 7156}, +/*h(13709)=2 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13709, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30093)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1453)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17837)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5549)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5549; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21933)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21933; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9645)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26029)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7623)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7623, 7153}, +/*h(30125)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30125, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1429)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17813)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5525)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21909)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3466)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3466, 7154}, +/*h(9621)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9621, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26005)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7562)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7562, 7154}, +/*h(13717)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13717, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1461)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9653)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7631)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7631, 7153}, +/*h(30133)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30133, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11666)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {11666, 7151}, +/*h(5511)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5511, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15762)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {15762, 7151}, +/*h(9607)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9607, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25991)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13703)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1447)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17831)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5543)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21927)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9639)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26023)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_321_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1423)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5519)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21903)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13711)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30095)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1455)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1455; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17839)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5551)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21935)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9647)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26031)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13743)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17815)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5527)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9623)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9623; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26007)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13719)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7618)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7618, 7154}, +/*h(1463)=1 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1463, 7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21943)=0 EVV 0x79 V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7101} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9600)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9632)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9632; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26016)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_653_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25992)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3522)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {3522, 7154}, +/*h(26024)=1 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {26024, 7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25986)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9634)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {9634, 7102}, +/*h(3479)=1 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 7150} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26018)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9642)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_663_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26026)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25985)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26017)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25993)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9641)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26025)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9635)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9635; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26019)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9643)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26027)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9619)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26003)=0 EVV 0x79 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7102} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3478)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_688_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7574)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7149} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7575)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7150} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3474)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7151} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7558)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15814)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3470)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11662)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15758)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11726)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7152} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3463)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11719)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3471)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7567)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11663)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15759)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11727)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7153} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11714)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7154} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15810)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7154} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15754)=0 EVV 0x79 VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE*/ {7154} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11734)=0 EVV 0x79 VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7155} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x79_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[696] = { +/*h(21892)=0 */ {21892, xed3_phash_find_mapevex_map5_opcode0x79_vv2_0_l1}, +/*h(8595)=1 */ {8595, xed3_phash_find_mapevex_map5_opcode0x79_vv2_1_l1}, +/*h(1453)=2 */ {1453, xed3_phash_find_mapevex_map5_opcode0x79_vv2_2_l1}, +/*h(17800)=3 */ {17800, xed3_phash_find_mapevex_map5_opcode0x79_vv2_3_l1}, +/*h(15826)=4 */ {15826, xed3_phash_find_mapevex_map5_opcode0x79_vv2_4_l1}, +/*h(26018)=5 */ {26018, xed3_phash_find_mapevex_map5_opcode0x79_vv2_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11734)=7 */ {11734, xed3_phash_find_mapevex_map5_opcode0x79_vv2_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21926)=9 */ {21926, xed3_phash_find_mapevex_map5_opcode0x79_vv2_9_l1}, +/*h(9616)=10 */ {9616, xed3_phash_find_mapevex_map5_opcode0x79_vv2_10_l1}, +/*h(24976)=11 */ {24976, xed3_phash_find_mapevex_map5_opcode0x79_vv2_11_l1}, +/*h(17834)=12 */ {17834, xed3_phash_find_mapevex_map5_opcode0x79_vv2_12_l1}, +/*h(5524)=13 */ {5524, xed3_phash_find_mapevex_map5_opcode0x79_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20884)=15 */ {20884, xed3_phash_find_mapevex_map5_opcode0x79_vv2_15_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9650)=19 */ {9650, xed3_phash_find_mapevex_map5_opcode0x79_vv2_19_l1}, +/*h(25997)=20 */ {25997, xed3_phash_find_mapevex_map5_opcode0x79_vv2_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5558)=22 */ {5558, xed3_phash_find_mapevex_map5_opcode0x79_vv2_22_l1}, +/*h(390)=23 */ {390, xed3_phash_find_mapevex_map5_opcode0x79_vv2_23_l1}, +/*h(15750)=24 */ {15750, xed3_phash_find_mapevex_map5_opcode0x79_vv2_24_l1}, +/*h(8608)=25 */ {8608, xed3_phash_find_mapevex_map5_opcode0x79_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17813)=27 */ {17813, xed3_phash_find_mapevex_map5_opcode0x79_vv2_27_l1}, +/*h(11658)=28 */ {11658, xed3_phash_find_mapevex_map5_opcode0x79_vv2_28_l1}, +/*h(26031)=29 */ {26031, xed3_phash_find_mapevex_map5_opcode0x79_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7566)=31 */ {7566, xed3_phash_find_mapevex_map5_opcode0x79_vv2_31_l1}, +/*h(424)=32 */ {424, xed3_phash_find_mapevex_map5_opcode0x79_vv2_32_l1}, +/*h(21939)=33 */ {21939, xed3_phash_find_mapevex_map5_opcode0x79_vv2_33_l1}, +/*h(3474)=34 */ {3474, xed3_phash_find_mapevex_map5_opcode0x79_vv2_34_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17847)=36 */ {17847, xed3_phash_find_mapevex_map5_opcode0x79_vv2_36_l1}, +/*h(5537)=37 */ {5537, xed3_phash_find_mapevex_map5_opcode0x79_vv2_37_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20897)=39 */ {20897, xed3_phash_find_mapevex_map5_opcode0x79_vv2_39_l1}, +/*h(8587)=40 */ {8587, xed3_phash_find_mapevex_map5_opcode0x79_vv2_40_l1}, +/*h(1445)=41 */ {1445, xed3_phash_find_mapevex_map5_opcode0x79_vv2_41_l1}, +/*h(15818)=42 */ {15818, xed3_phash_find_mapevex_map5_opcode0x79_vv2_42_l1}, +/*h(4495)=43 */ {4495, xed3_phash_find_mapevex_map5_opcode0x79_vv2_43_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11726)=46 */ {11726, xed3_phash_find_mapevex_map5_opcode0x79_vv2_46_l1}, +/*h(403)=47 */ {403, xed3_phash_find_mapevex_map5_opcode0x79_vv2_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7634)=49 */ {7634, xed3_phash_find_mapevex_map5_opcode0x79_vv2_49_l1}, +/*h(24968)=50 */ {24968, xed3_phash_find_mapevex_map5_opcode0x79_vv2_50_l1}, +/*h(11671)=51 */ {11671, xed3_phash_find_mapevex_map5_opcode0x79_vv2_51_l1}, +/*h(5516)=52 */ {5516, xed3_phash_find_mapevex_map5_opcode0x79_vv2_52_l1}, +/*h(3542)=53 */ {3542, xed3_phash_find_mapevex_map5_opcode0x79_vv2_53_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1424)=55 */ {1424, xed3_phash_find_mapevex_map5_opcode0x79_vv2_55_l1}, +/*h(437)=56 */ {437, xed3_phash_find_mapevex_map5_opcode0x79_vv2_56_l1}, +/*h(16784)=57 */ {16784, xed3_phash_find_mapevex_map5_opcode0x79_vv2_57_l1}, +/*h(9642)=58 */ {9642, xed3_phash_find_mapevex_map5_opcode0x79_vv2_58_l1}, +/*h(25989)=59 */ {25989, xed3_phash_find_mapevex_map5_opcode0x79_vv2_59_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5550)=61 */ {5550, xed3_phash_find_mapevex_map5_opcode0x79_vv2_61_l1}, +/*h(21897)=62 */ {21897, xed3_phash_find_mapevex_map5_opcode0x79_vv2_62_l1}, +/*h(20910)=63 */ {20910, xed3_phash_find_mapevex_map5_opcode0x79_vv2_63_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1458)=65 */ {1458, xed3_phash_find_mapevex_map5_opcode0x79_vv2_65_l1}, +/*h(15831)=66 */ {15831, xed3_phash_find_mapevex_map5_opcode0x79_vv2_66_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26023)=68 */ {26023, xed3_phash_find_mapevex_map5_opcode0x79_vv2_68_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7558)=70 */ {7558, xed3_phash_find_mapevex_map5_opcode0x79_vv2_70_l1}, +/*h(21931)=71 */ {21931, xed3_phash_find_mapevex_map5_opcode0x79_vv2_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3466)=73 */ {3466, xed3_phash_find_mapevex_map5_opcode0x79_vv2_73_l1}, +/*h(24981)=74 */ {24981, xed3_phash_find_mapevex_map5_opcode0x79_vv2_74_l1}, +/*h(17839)=75 */ {17839, xed3_phash_find_mapevex_map5_opcode0x79_vv2_75_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8579)=79 */ {8579, xed3_phash_find_mapevex_map5_opcode0x79_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15810)=81 */ {15810, xed3_phash_find_mapevex_map5_opcode0x79_vv2_81_l1}, +/*h(9655)=82 */ {9655, xed3_phash_find_mapevex_map5_opcode0x79_vv2_82_l1}, +/*h(26002)=83 */ {26002, xed3_phash_find_mapevex_map5_opcode0x79_vv2_83_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11718)=85 */ {11718, xed3_phash_find_mapevex_map5_opcode0x79_vv2_85_l1}, +/*h(21910)=86 */ {21910, xed3_phash_find_mapevex_map5_opcode0x79_vv2_86_l1}, +/*h(9600)=87 */ {9600, xed3_phash_find_mapevex_map5_opcode0x79_vv2_87_l1}, +/*h(7626)=88 */ {7626, xed3_phash_find_mapevex_map5_opcode0x79_vv2_88_l1}, +/*h(24960)=89 */ {24960, xed3_phash_find_mapevex_map5_opcode0x79_vv2_89_l1}, +/*h(11663)=90 */ {11663, xed3_phash_find_mapevex_map5_opcode0x79_vv2_90_l1}, +/*h(3534)=91 */ {3534, xed3_phash_find_mapevex_map5_opcode0x79_vv2_91_l1}, +/*h(26036)=92 */ {26036, xed3_phash_find_mapevex_map5_opcode0x79_vv2_92_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1416)=94 */ {1416, xed3_phash_find_mapevex_map5_opcode0x79_vv2_94_l1}, +/*h(429)=95 */ {429, xed3_phash_find_mapevex_map5_opcode0x79_vv2_95_l1}, +/*h(16776)=96 */ {16776, xed3_phash_find_mapevex_map5_opcode0x79_vv2_96_l1}, +/*h(3479)=97 */ {3479, xed3_phash_find_mapevex_map5_opcode0x79_vv2_97_l1}, +/*h(24994)=98 */ {24994, xed3_phash_find_mapevex_map5_opcode0x79_vv2_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5542)=100 */ {5542, xed3_phash_find_mapevex_map5_opcode0x79_vv2_100_l1}, +/*h(21889)=101 */ {21889, xed3_phash_find_mapevex_map5_opcode0x79_vv2_101_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1450)=103 */ {1450, xed3_phash_find_mapevex_map5_opcode0x79_vv2_103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15823)=105 */ {15823, xed3_phash_find_mapevex_map5_opcode0x79_vv2_105_l1}, +/*h(4500)=106 */ {4500, xed3_phash_find_mapevex_map5_opcode0x79_vv2_106_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21923)=110 */ {21923, xed3_phash_find_mapevex_map5_opcode0x79_vv2_110_l1}, +/*h(9613)=111 */ {9613, xed3_phash_find_mapevex_map5_opcode0x79_vv2_111_l1}, +/*h(7639)=112 */ {7639, xed3_phash_find_mapevex_map5_opcode0x79_vv2_112_l1}, +/*h(24973)=113 */ {24973, xed3_phash_find_mapevex_map5_opcode0x79_vv2_113_l1}, +/*h(17831)=114 */ {17831, xed3_phash_find_mapevex_map5_opcode0x79_vv2_114_l1}, +/*h(5521)=115 */ {5521, xed3_phash_find_mapevex_map5_opcode0x79_vv2_115_l1}, +/*h(20881)=116 */ {20881, xed3_phash_find_mapevex_map5_opcode0x79_vv2_116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1429)=118 */ {1429, xed3_phash_find_mapevex_map5_opcode0x79_vv2_118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16789)=120 */ {16789, xed3_phash_find_mapevex_map5_opcode0x79_vv2_120_l1}, +/*h(9647)=121 */ {9647, xed3_phash_find_mapevex_map5_opcode0x79_vv2_121_l1}, +/*h(25994)=122 */ {25994, xed3_phash_find_mapevex_map5_opcode0x79_vv2_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5555)=124 */ {5555, xed3_phash_find_mapevex_map5_opcode0x79_vv2_124_l1}, +/*h(21902)=125 */ {21902, xed3_phash_find_mapevex_map5_opcode0x79_vv2_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7618)=127 */ {7618, xed3_phash_find_mapevex_map5_opcode0x79_vv2_127_l1}, +/*h(17810)=128 */ {17810, xed3_phash_find_mapevex_map5_opcode0x79_vv2_128_l1}, +/*h(11655)=129 */ {11655, xed3_phash_find_mapevex_map5_opcode0x79_vv2_129_l1}, +/*h(3526)=130 */ {3526, xed3_phash_find_mapevex_map5_opcode0x79_vv2_130_l1}, +/*h(26028)=131 */ {26028, xed3_phash_find_mapevex_map5_opcode0x79_vv2_131_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1408)=133 */ {1408, xed3_phash_find_mapevex_map5_opcode0x79_vv2_133_l1}, +/*h(21936)=134 */ {21936, xed3_phash_find_mapevex_map5_opcode0x79_vv2_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3471)=136 */ {3471, xed3_phash_find_mapevex_map5_opcode0x79_vv2_136_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17844)=138 */ {17844, xed3_phash_find_mapevex_map5_opcode0x79_vv2_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8584)=141 */ {8584, xed3_phash_find_mapevex_map5_opcode0x79_vv2_141_l1}, +/*h(1442)=142 */ {1442, xed3_phash_find_mapevex_map5_opcode0x79_vv2_142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15815)=144 */ {15815, xed3_phash_find_mapevex_map5_opcode0x79_vv2_144_l1}, +/*h(4492)=145 */ {4492, xed3_phash_find_mapevex_map5_opcode0x79_vv2_145_l1}, +/*h(26007)=146 */ {26007, xed3_phash_find_mapevex_map5_opcode0x79_vv2_146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(400)=148 */ {400, xed3_phash_find_mapevex_map5_opcode0x79_vv2_148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9605)=150 */ {9605, xed3_phash_find_mapevex_map5_opcode0x79_vv2_150_l1}, +/*h(7631)=151 */ {7631, xed3_phash_find_mapevex_map5_opcode0x79_vv2_151_l1}, +/*h(24965)=152 */ {24965, xed3_phash_find_mapevex_map5_opcode0x79_vv2_152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5513)=154 */ {5513, xed3_phash_find_mapevex_map5_opcode0x79_vv2_154_l1}, +/*h(20873)=155 */ {20873, xed3_phash_find_mapevex_map5_opcode0x79_vv2_155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1421)=157 */ {1421, xed3_phash_find_mapevex_map5_opcode0x79_vv2_157_l1}, +/*h(16781)=158 */ {16781, xed3_phash_find_mapevex_map5_opcode0x79_vv2_158_l1}, +/*h(9639)=159 */ {9639, xed3_phash_find_mapevex_map5_opcode0x79_vv2_159_l1}, +/*h(25986)=160 */ {25986, xed3_phash_find_mapevex_map5_opcode0x79_vv2_160_l1}, +/*h(24999)=161 */ {24999, xed3_phash_find_mapevex_map5_opcode0x79_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5547)=163 */ {5547, xed3_phash_find_mapevex_map5_opcode0x79_vv2_163_l1}, +/*h(21894)=164 */ {21894, xed3_phash_find_mapevex_map5_opcode0x79_vv2_164_l1}, +/*h(8597)=165 */ {8597, xed3_phash_find_mapevex_map5_opcode0x79_vv2_165_l1}, +/*h(1455)=166 */ {1455, xed3_phash_find_mapevex_map5_opcode0x79_vv2_166_l1}, +/*h(17802)=167 */ {17802, xed3_phash_find_mapevex_map5_opcode0x79_vv2_167_l1}, +/*h(16815)=168 */ {16815, xed3_phash_find_mapevex_map5_opcode0x79_vv2_168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26020)=170 */ {26020, xed3_phash_find_mapevex_map5_opcode0x79_vv2_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21928)=173 */ {21928, xed3_phash_find_mapevex_map5_opcode0x79_vv2_173_l1}, +/*h(9618)=174 */ {9618, xed3_phash_find_mapevex_map5_opcode0x79_vv2_174_l1}, +/*h(3463)=175 */ {3463, xed3_phash_find_mapevex_map5_opcode0x79_vv2_175_l1}, +/*h(17836)=176 */ {17836, xed3_phash_find_mapevex_map5_opcode0x79_vv2_176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5526)=178 */ {5526, xed3_phash_find_mapevex_map5_opcode0x79_vv2_178_l1}, +/*h(20886)=179 */ {20886, xed3_phash_find_mapevex_map5_opcode0x79_vv2_179_l1}, +/*h(8576)=180 */ {8576, xed3_phash_find_mapevex_map5_opcode0x79_vv2_180_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9652)=183 */ {9652, xed3_phash_find_mapevex_map5_opcode0x79_vv2_183_l1}, +/*h(25999)=184 */ {25999, xed3_phash_find_mapevex_map5_opcode0x79_vv2_184_l1}, +/*h(25012)=185 */ {25012, xed3_phash_find_mapevex_map5_opcode0x79_vv2_185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(392)=187 */ {392, xed3_phash_find_mapevex_map5_opcode0x79_vv2_187_l1}, +/*h(21907)=188 */ {21907, xed3_phash_find_mapevex_map5_opcode0x79_vv2_188_l1}, +/*h(8610)=189 */ {8610, xed3_phash_find_mapevex_map5_opcode0x79_vv2_189_l1}, +/*h(7623)=190 */ {7623, xed3_phash_find_mapevex_map5_opcode0x79_vv2_190_l1}, +/*h(17815)=191 */ {17815, xed3_phash_find_mapevex_map5_opcode0x79_vv2_191_l1}, +/*h(5505)=192 */ {5505, xed3_phash_find_mapevex_map5_opcode0x79_vv2_192_l1}, +/*h(4518)=193 */ {4518, xed3_phash_find_mapevex_map5_opcode0x79_vv2_193_l1}, +/*h(26033)=194 */ {26033, xed3_phash_find_mapevex_map5_opcode0x79_vv2_194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1413)=196 */ {1413, xed3_phash_find_mapevex_map5_opcode0x79_vv2_196_l1}, +/*h(21941)=197 */ {21941, xed3_phash_find_mapevex_map5_opcode0x79_vv2_197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5539)=202 */ {5539, xed3_phash_find_mapevex_map5_opcode0x79_vv2_202_l1}, +/*h(20899)=203 */ {20899, xed3_phash_find_mapevex_map5_opcode0x79_vv2_203_l1}, +/*h(8589)=204 */ {8589, xed3_phash_find_mapevex_map5_opcode0x79_vv2_204_l1}, +/*h(1447)=205 */ {1447, xed3_phash_find_mapevex_map5_opcode0x79_vv2_205_l1}, +/*h(17794)=206 */ {17794, xed3_phash_find_mapevex_map5_opcode0x79_vv2_206_l1}, +/*h(4497)=207 */ {4497, xed3_phash_find_mapevex_map5_opcode0x79_vv2_207_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(405)=211 */ {405, xed3_phash_find_mapevex_map5_opcode0x79_vv2_211_l1}, +/*h(21920)=212 */ {21920, xed3_phash_find_mapevex_map5_opcode0x79_vv2_212_l1}, +/*h(9610)=213 */ {9610, xed3_phash_find_mapevex_map5_opcode0x79_vv2_213_l1}, +/*h(24970)=214 */ {24970, xed3_phash_find_mapevex_map5_opcode0x79_vv2_214_l1}, +/*h(17828)=215 */ {17828, xed3_phash_find_mapevex_map5_opcode0x79_vv2_215_l1}, +/*h(5518)=216 */ {5518, xed3_phash_find_mapevex_map5_opcode0x79_vv2_216_l1}, +/*h(4531)=217 */ {4531, xed3_phash_find_mapevex_map5_opcode0x79_vv2_217_l1}, +/*h(20878)=218 */ {20878, xed3_phash_find_mapevex_map5_opcode0x79_vv2_218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1426)=220 */ {1426, xed3_phash_find_mapevex_map5_opcode0x79_vv2_220_l1}, +/*h(16786)=221 */ {16786, xed3_phash_find_mapevex_map5_opcode0x79_vv2_221_l1}, +/*h(9644)=222 */ {9644, xed3_phash_find_mapevex_map5_opcode0x79_vv2_222_l1}, +/*h(25991)=223 */ {25991, xed3_phash_find_mapevex_map5_opcode0x79_vv2_223_l1}, +/*h(25004)=224 */ {25004, xed3_phash_find_mapevex_map5_opcode0x79_vv2_224_l1}, +/*h(5552)=225 */ {5552, xed3_phash_find_mapevex_map5_opcode0x79_vv2_225_l1}, +/*h(384)=226 */ {384, xed3_phash_find_mapevex_map5_opcode0x79_vv2_226_l1}, +/*h(21899)=227 */ {21899, xed3_phash_find_mapevex_map5_opcode0x79_vv2_227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30117)=229 */ {30117, xed3_phash_find_mapevex_map5_opcode0x79_vv2_229_l1}, +/*h(17807)=230 */ {17807, xed3_phash_find_mapevex_map5_opcode0x79_vv2_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26025)=232 */ {26025, xed3_phash_find_mapevex_map5_opcode0x79_vv2_232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(418)=235 */ {418, xed3_phash_find_mapevex_map5_opcode0x79_vv2_235_l1}, +/*h(21933)=236 */ {21933, xed3_phash_find_mapevex_map5_opcode0x79_vv2_236_l1}, +/*h(9623)=237 */ {9623, xed3_phash_find_mapevex_map5_opcode0x79_vv2_237_l1}, +/*h(24983)=238 */ {24983, xed3_phash_find_mapevex_map5_opcode0x79_vv2_238_l1}, +/*h(17841)=239 */ {17841, xed3_phash_find_mapevex_map5_opcode0x79_vv2_239_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13749)=243 */ {13749, xed3_phash_find_mapevex_map5_opcode0x79_vv2_243_l1}, +/*h(29109)=244 */ {29109, xed3_phash_find_mapevex_map5_opcode0x79_vv2_244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4489)=246 */ {4489, xed3_phash_find_mapevex_map5_opcode0x79_vv2_246_l1}, +/*h(26004)=247 */ {26004, xed3_phash_find_mapevex_map5_opcode0x79_vv2_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(397)=250 */ {397, xed3_phash_find_mapevex_map5_opcode0x79_vv2_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9602)=252 */ {9602, xed3_phash_find_mapevex_map5_opcode0x79_vv2_252_l1}, +/*h(24962)=253 */ {24962, xed3_phash_find_mapevex_map5_opcode0x79_vv2_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5510)=255 */ {5510, xed3_phash_find_mapevex_map5_opcode0x79_vv2_255_l1}, +/*h(26038)=256 */ {26038, xed3_phash_find_mapevex_map5_opcode0x79_vv2_256_l1}, +/*h(20870)=257 */ {20870, xed3_phash_find_mapevex_map5_opcode0x79_vv2_257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1418)=259 */ {1418, xed3_phash_find_mapevex_map5_opcode0x79_vv2_259_l1}, +/*h(16778)=260 */ {16778, xed3_phash_find_mapevex_map5_opcode0x79_vv2_260_l1}, +/*h(9636)=261 */ {9636, xed3_phash_find_mapevex_map5_opcode0x79_vv2_261_l1}, +/*h(24996)=262 */ {24996, xed3_phash_find_mapevex_map5_opcode0x79_vv2_262_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5544)=264 */ {5544, xed3_phash_find_mapevex_map5_opcode0x79_vv2_264_l1}, +/*h(21891)=265 */ {21891, xed3_phash_find_mapevex_map5_opcode0x79_vv2_265_l1}, +/*h(20904)=266 */ {20904, xed3_phash_find_mapevex_map5_opcode0x79_vv2_266_l1}, +/*h(8594)=267 */ {8594, xed3_phash_find_mapevex_map5_opcode0x79_vv2_267_l1}, +/*h(1452)=268 */ {1452, xed3_phash_find_mapevex_map5_opcode0x79_vv2_268_l1}, +/*h(17799)=269 */ {17799, xed3_phash_find_mapevex_map5_opcode0x79_vv2_269_l1}, +/*h(4502)=270 */ {4502, xed3_phash_find_mapevex_map5_opcode0x79_vv2_270_l1}, +/*h(26017)=271 */ {26017, xed3_phash_find_mapevex_map5_opcode0x79_vv2_271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21925)=275 */ {21925, xed3_phash_find_mapevex_map5_opcode0x79_vv2_275_l1}, +/*h(9615)=276 */ {9615, xed3_phash_find_mapevex_map5_opcode0x79_vv2_276_l1}, +/*h(24975)=277 */ {24975, xed3_phash_find_mapevex_map5_opcode0x79_vv2_277_l1}, +/*h(17833)=278 */ {17833, xed3_phash_find_mapevex_map5_opcode0x79_vv2_278_l1}, +/*h(5523)=279 */ {5523, xed3_phash_find_mapevex_map5_opcode0x79_vv2_279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13741)=281 */ {13741, xed3_phash_find_mapevex_map5_opcode0x79_vv2_281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1431)=283 */ {1431, xed3_phash_find_mapevex_map5_opcode0x79_vv2_283_l1}, +/*h(16791)=284 */ {16791, xed3_phash_find_mapevex_map5_opcode0x79_vv2_284_l1}, +/*h(9649)=285 */ {9649, xed3_phash_find_mapevex_map5_opcode0x79_vv2_285_l1}, +/*h(25996)=286 */ {25996, xed3_phash_find_mapevex_map5_opcode0x79_vv2_286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5557)=288 */ {5557, xed3_phash_find_mapevex_map5_opcode0x79_vv2_288_l1}, +/*h(21904)=289 */ {21904, xed3_phash_find_mapevex_map5_opcode0x79_vv2_289_l1}, +/*h(20917)=290 */ {20917, xed3_phash_find_mapevex_map5_opcode0x79_vv2_290_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17812)=293 */ {17812, xed3_phash_find_mapevex_map5_opcode0x79_vv2_293_l1}, +/*h(4515)=294 */ {4515, xed3_phash_find_mapevex_map5_opcode0x79_vv2_294_l1}, +/*h(26030)=295 */ {26030, xed3_phash_find_mapevex_map5_opcode0x79_vv2_295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1410)=297 */ {1410, xed3_phash_find_mapevex_map5_opcode0x79_vv2_297_l1}, +/*h(423)=298 */ {423, xed3_phash_find_mapevex_map5_opcode0x79_vv2_298_l1}, +/*h(21938)=299 */ {21938, xed3_phash_find_mapevex_map5_opcode0x79_vv2_299_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17846)=302 */ {17846, xed3_phash_find_mapevex_map5_opcode0x79_vv2_302_l1}, +/*h(5536)=303 */ {5536, xed3_phash_find_mapevex_map5_opcode0x79_vv2_303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20896)=305 */ {20896, xed3_phash_find_mapevex_map5_opcode0x79_vv2_305_l1}, +/*h(30101)=306 */ {30101, xed3_phash_find_mapevex_map5_opcode0x79_vv2_306_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16804)=308 */ {16804, xed3_phash_find_mapevex_map5_opcode0x79_vv2_308_l1}, +/*h(4494)=309 */ {4494, xed3_phash_find_mapevex_map5_opcode0x79_vv2_309_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(402)=312 */ {402, xed3_phash_find_mapevex_map5_opcode0x79_vv2_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15762)=314 */ {15762, xed3_phash_find_mapevex_map5_opcode0x79_vv2_314_l1}, +/*h(8620)=315 */ {8620, xed3_phash_find_mapevex_map5_opcode0x79_vv2_315_l1}, +/*h(30135)=316 */ {30135, xed3_phash_find_mapevex_map5_opcode0x79_vv2_316_l1}, +/*h(11670)=317 */ {11670, xed3_phash_find_mapevex_map5_opcode0x79_vv2_317_l1}, +/*h(5515)=318 */ {5515, xed3_phash_find_mapevex_map5_opcode0x79_vv2_318_l1}, +/*h(20875)=319 */ {20875, xed3_phash_find_mapevex_map5_opcode0x79_vv2_319_l1}, +/*h(13733)=320 */ {13733, xed3_phash_find_mapevex_map5_opcode0x79_vv2_320_l1}, +/*h(1423)=321 */ {1423, xed3_phash_find_mapevex_map5_opcode0x79_vv2_321_l1}, +/*h(29093)=322 */ {29093, xed3_phash_find_mapevex_map5_opcode0x79_vv2_322_l1}, +/*h(16783)=323 */ {16783, xed3_phash_find_mapevex_map5_opcode0x79_vv2_323_l1}, +/*h(9641)=324 */ {9641, xed3_phash_find_mapevex_map5_opcode0x79_vv2_324_l1}, +/*h(25988)=325 */ {25988, xed3_phash_find_mapevex_map5_opcode0x79_vv2_325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5549)=327 */ {5549, xed3_phash_find_mapevex_map5_opcode0x79_vv2_327_l1}, +/*h(21896)=328 */ {21896, xed3_phash_find_mapevex_map5_opcode0x79_vv2_328_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1457)=330 */ {1457, xed3_phash_find_mapevex_map5_opcode0x79_vv2_330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15830)=332 */ {15830, xed3_phash_find_mapevex_map5_opcode0x79_vv2_332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26022)=334 */ {26022, xed3_phash_find_mapevex_map5_opcode0x79_vv2_334_l1}, +/*h(12725)=335 */ {12725, xed3_phash_find_mapevex_map5_opcode0x79_vv2_335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21930)=337 */ {21930, xed3_phash_find_mapevex_map5_opcode0x79_vv2_337_l1}, +/*h(9620)=338 */ {9620, xed3_phash_find_mapevex_map5_opcode0x79_vv2_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24980)=340 */ {24980, xed3_phash_find_mapevex_map5_opcode0x79_vv2_340_l1}, +/*h(17838)=341 */ {17838, xed3_phash_find_mapevex_map5_opcode0x79_vv2_341_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8578)=344 */ {8578, xed3_phash_find_mapevex_map5_opcode0x79_vv2_344_l1}, +/*h(30093)=345 */ {30093, xed3_phash_find_mapevex_map5_opcode0x79_vv2_345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9654)=348 */ {9654, xed3_phash_find_mapevex_map5_opcode0x79_vv2_348_l1}, +/*h(26001)=349 */ {26001, xed3_phash_find_mapevex_map5_opcode0x79_vv2_349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(394)=351 */ {394, xed3_phash_find_mapevex_map5_opcode0x79_vv2_351_l1}, +/*h(21909)=352 */ {21909, xed3_phash_find_mapevex_map5_opcode0x79_vv2_352_l1}, +/*h(15754)=353 */ {15754, xed3_phash_find_mapevex_map5_opcode0x79_vv2_353_l1}, +/*h(30127)=354 */ {30127, xed3_phash_find_mapevex_map5_opcode0x79_vv2_354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11662)=356 */ {11662, xed3_phash_find_mapevex_map5_opcode0x79_vv2_356_l1}, +/*h(5507)=357 */ {5507, xed3_phash_find_mapevex_map5_opcode0x79_vv2_357_l1}, +/*h(26035)=358 */ {26035, xed3_phash_find_mapevex_map5_opcode0x79_vv2_358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7570)=360 */ {7570, xed3_phash_find_mapevex_map5_opcode0x79_vv2_360_l1}, +/*h(21943)=361 */ {21943, xed3_phash_find_mapevex_map5_opcode0x79_vv2_361_l1}, +/*h(9633)=362 */ {9633, xed3_phash_find_mapevex_map5_opcode0x79_vv2_362_l1}, +/*h(3478)=363 */ {3478, xed3_phash_find_mapevex_map5_opcode0x79_vv2_363_l1}, +/*h(24993)=364 */ {24993, xed3_phash_find_mapevex_map5_opcode0x79_vv2_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5541)=366 */ {5541, xed3_phash_find_mapevex_map5_opcode0x79_vv2_366_l1}, +/*h(21888)=367 */ {21888, xed3_phash_find_mapevex_map5_opcode0x79_vv2_367_l1}, +/*h(8591)=368 */ {8591, xed3_phash_find_mapevex_map5_opcode0x79_vv2_368_l1}, +/*h(1449)=369 */ {1449, xed3_phash_find_mapevex_map5_opcode0x79_vv2_369_l1}, +/*h(17796)=370 */ {17796, xed3_phash_find_mapevex_map5_opcode0x79_vv2_370_l1}, +/*h(15822)=371 */ {15822, xed3_phash_find_mapevex_map5_opcode0x79_vv2_371_l1}, +/*h(4499)=372 */ {4499, xed3_phash_find_mapevex_map5_opcode0x79_vv2_372_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11730)=374 */ {11730, xed3_phash_find_mapevex_map5_opcode0x79_vv2_374_l1}, +/*h(407)=375 */ {407, xed3_phash_find_mapevex_map5_opcode0x79_vv2_375_l1}, +/*h(21922)=376 */ {21922, xed3_phash_find_mapevex_map5_opcode0x79_vv2_376_l1}, +/*h(15767)=377 */ {15767, xed3_phash_find_mapevex_map5_opcode0x79_vv2_377_l1}, +/*h(7638)=378 */ {7638, xed3_phash_find_mapevex_map5_opcode0x79_vv2_378_l1}, +/*h(24972)=379 */ {24972, xed3_phash_find_mapevex_map5_opcode0x79_vv2_379_l1}, +/*h(17830)=380 */ {17830, xed3_phash_find_mapevex_map5_opcode0x79_vv2_380_l1}, +/*h(5520)=381 */ {5520, xed3_phash_find_mapevex_map5_opcode0x79_vv2_381_l1}, +/*h(20880)=382 */ {20880, xed3_phash_find_mapevex_map5_opcode0x79_vv2_382_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30085)=384 */ {30085, xed3_phash_find_mapevex_map5_opcode0x79_vv2_384_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9646)=386 */ {9646, xed3_phash_find_mapevex_map5_opcode0x79_vv2_386_l1}, +/*h(25993)=387 */ {25993, xed3_phash_find_mapevex_map5_opcode0x79_vv2_387_l1}, +/*h(25006)=388 */ {25006, xed3_phash_find_mapevex_map5_opcode0x79_vv2_388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5554)=390 */ {5554, xed3_phash_find_mapevex_map5_opcode0x79_vv2_390_l1}, +/*h(15746)=391 */ {15746, xed3_phash_find_mapevex_map5_opcode0x79_vv2_391_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30119)=393 */ {30119, xed3_phash_find_mapevex_map5_opcode0x79_vv2_393_l1}, +/*h(17809)=394 */ {17809, xed3_phash_find_mapevex_map5_opcode0x79_vv2_394_l1}, +/*h(11654)=395 */ {11654, xed3_phash_find_mapevex_map5_opcode0x79_vv2_395_l1}, +/*h(4512)=396 */ {4512, xed3_phash_find_mapevex_map5_opcode0x79_vv2_396_l1}, +/*h(26027)=397 */ {26027, xed3_phash_find_mapevex_map5_opcode0x79_vv2_397_l1}, +/*h(7562)=398 */ {7562, xed3_phash_find_mapevex_map5_opcode0x79_vv2_398_l1}, +/*h(29077)=399 */ {29077, xed3_phash_find_mapevex_map5_opcode0x79_vv2_399_l1}, +/*h(21935)=400 */ {21935, xed3_phash_find_mapevex_map5_opcode0x79_vv2_400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3470)=402 */ {3470, xed3_phash_find_mapevex_map5_opcode0x79_vv2_402_l1}, +/*h(17843)=403 */ {17843, xed3_phash_find_mapevex_map5_opcode0x79_vv2_403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13751)=407 */ {13751, xed3_phash_find_mapevex_map5_opcode0x79_vv2_407_l1}, +/*h(1441)=408 */ {1441, xed3_phash_find_mapevex_map5_opcode0x79_vv2_408_l1}, +/*h(16801)=409 */ {16801, xed3_phash_find_mapevex_map5_opcode0x79_vv2_409_l1}, +/*h(15814)=410 */ {15814, xed3_phash_find_mapevex_map5_opcode0x79_vv2_410_l1}, +/*h(26006)=411 */ {26006, xed3_phash_find_mapevex_map5_opcode0x79_vv2_411_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11722)=413 */ {11722, xed3_phash_find_mapevex_map5_opcode0x79_vv2_413_l1}, +/*h(399)=414 */ {399, xed3_phash_find_mapevex_map5_opcode0x79_vv2_414_l1}, +/*h(15759)=415 */ {15759, xed3_phash_find_mapevex_map5_opcode0x79_vv2_415_l1}, +/*h(9604)=416 */ {9604, xed3_phash_find_mapevex_map5_opcode0x79_vv2_416_l1}, +/*h(7630)=417 */ {7630, xed3_phash_find_mapevex_map5_opcode0x79_vv2_417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5512)=419 */ {5512, xed3_phash_find_mapevex_map5_opcode0x79_vv2_419_l1}, +/*h(3538)=420 */ {3538, xed3_phash_find_mapevex_map5_opcode0x79_vv2_420_l1}, +/*h(20872)=421 */ {20872, xed3_phash_find_mapevex_map5_opcode0x79_vv2_421_l1}, +/*h(7575)=422 */ {7575, xed3_phash_find_mapevex_map5_opcode0x79_vv2_422_l1}, +/*h(1420)=423 */ {1420, xed3_phash_find_mapevex_map5_opcode0x79_vv2_423_l1}, +/*h(16780)=424 */ {16780, xed3_phash_find_mapevex_map5_opcode0x79_vv2_424_l1}, +/*h(9638)=425 */ {9638, xed3_phash_find_mapevex_map5_opcode0x79_vv2_425_l1}, +/*h(25985)=426 */ {25985, xed3_phash_find_mapevex_map5_opcode0x79_vv2_426_l1}, +/*h(24998)=427 */ {24998, xed3_phash_find_mapevex_map5_opcode0x79_vv2_427_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5546)=429 */ {5546, xed3_phash_find_mapevex_map5_opcode0x79_vv2_429_l1}, +/*h(21893)=430 */ {21893, xed3_phash_find_mapevex_map5_opcode0x79_vv2_430_l1}, +/*h(8596)=431 */ {8596, xed3_phash_find_mapevex_map5_opcode0x79_vv2_431_l1}, +/*h(1454)=432 */ {1454, xed3_phash_find_mapevex_map5_opcode0x79_vv2_432_l1}, +/*h(17801)=433 */ {17801, xed3_phash_find_mapevex_map5_opcode0x79_vv2_433_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26019)=435 */ {26019, xed3_phash_find_mapevex_map5_opcode0x79_vv2_435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11735)=437 */ {11735, xed3_phash_find_mapevex_map5_opcode0x79_vv2_437_l1}, +/*h(29069)=438 */ {29069, xed3_phash_find_mapevex_map5_opcode0x79_vv2_438_l1}, +/*h(21927)=439 */ {21927, xed3_phash_find_mapevex_map5_opcode0x79_vv2_439_l1}, +/*h(9617)=440 */ {9617, xed3_phash_find_mapevex_map5_opcode0x79_vv2_440_l1}, +/*h(3462)=441 */ {3462, xed3_phash_find_mapevex_map5_opcode0x79_vv2_441_l1}, +/*h(17835)=442 */ {17835, xed3_phash_find_mapevex_map5_opcode0x79_vv2_442_l1}, +/*h(5525)=443 */ {5525, xed3_phash_find_mapevex_map5_opcode0x79_vv2_443_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20885)=445 */ {20885, xed3_phash_find_mapevex_map5_opcode0x79_vv2_445_l1}, +/*h(13743)=446 */ {13743, xed3_phash_find_mapevex_map5_opcode0x79_vv2_446_l1}, +/*h(29103)=447 */ {29103, xed3_phash_find_mapevex_map5_opcode0x79_vv2_447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9651)=449 */ {9651, xed3_phash_find_mapevex_map5_opcode0x79_vv2_449_l1}, +/*h(25998)=450 */ {25998, xed3_phash_find_mapevex_map5_opcode0x79_vv2_450_l1}, +/*h(25011)=451 */ {25011, xed3_phash_find_mapevex_map5_opcode0x79_vv2_451_l1}, +/*h(11714)=452 */ {11714, xed3_phash_find_mapevex_map5_opcode0x79_vv2_452_l1}, +/*h(5559)=453 */ {5559, xed3_phash_find_mapevex_map5_opcode0x79_vv2_453_l1}, +/*h(15751)=454 */ {15751, xed3_phash_find_mapevex_map5_opcode0x79_vv2_454_l1}, +/*h(7622)=455 */ {7622, xed3_phash_find_mapevex_map5_opcode0x79_vv2_455_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17814)=457 */ {17814, xed3_phash_find_mapevex_map5_opcode0x79_vv2_457_l1}, +/*h(5504)=458 */ {5504, xed3_phash_find_mapevex_map5_opcode0x79_vv2_458_l1}, +/*h(3530)=459 */ {3530, xed3_phash_find_mapevex_map5_opcode0x79_vv2_459_l1}, +/*h(20864)=460 */ {20864, xed3_phash_find_mapevex_map5_opcode0x79_vv2_460_l1}, +/*h(7567)=461 */ {7567, xed3_phash_find_mapevex_map5_opcode0x79_vv2_461_l1}, +/*h(1412)=462 */ {1412, xed3_phash_find_mapevex_map5_opcode0x79_vv2_462_l1}, +/*h(21940)=463 */ {21940, xed3_phash_find_mapevex_map5_opcode0x79_vv2_463_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5538)=467 */ {5538, xed3_phash_find_mapevex_map5_opcode0x79_vv2_467_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20898)=469 */ {20898, xed3_phash_find_mapevex_map5_opcode0x79_vv2_469_l1}, +/*h(8588)=470 */ {8588, xed3_phash_find_mapevex_map5_opcode0x79_vv2_470_l1}, +/*h(30103)=471 */ {30103, xed3_phash_find_mapevex_map5_opcode0x79_vv2_471_l1}, +/*h(17793)=472 */ {17793, xed3_phash_find_mapevex_map5_opcode0x79_vv2_472_l1}, +/*h(4496)=473 */ {4496, xed3_phash_find_mapevex_map5_opcode0x79_vv2_473_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13701)=475 */ {13701, xed3_phash_find_mapevex_map5_opcode0x79_vv2_475_l1}, +/*h(11727)=476 */ {11727, xed3_phash_find_mapevex_map5_opcode0x79_vv2_476_l1}, +/*h(29061)=477 */ {29061, xed3_phash_find_mapevex_map5_opcode0x79_vv2_477_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9609)=479 */ {9609, xed3_phash_find_mapevex_map5_opcode0x79_vv2_479_l1}, +/*h(24969)=480 */ {24969, xed3_phash_find_mapevex_map5_opcode0x79_vv2_480_l1}, +/*h(17827)=481 */ {17827, xed3_phash_find_mapevex_map5_opcode0x79_vv2_481_l1}, +/*h(5517)=482 */ {5517, xed3_phash_find_mapevex_map5_opcode0x79_vv2_482_l1}, +/*h(3543)=483 */ {3543, xed3_phash_find_mapevex_map5_opcode0x79_vv2_483_l1}, +/*h(13735)=484 */ {13735, xed3_phash_find_mapevex_map5_opcode0x79_vv2_484_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1425)=486 */ {1425, xed3_phash_find_mapevex_map5_opcode0x79_vv2_486_l1}, +/*h(16785)=487 */ {16785, xed3_phash_find_mapevex_map5_opcode0x79_vv2_487_l1}, +/*h(9643)=488 */ {9643, xed3_phash_find_mapevex_map5_opcode0x79_vv2_488_l1}, +/*h(25990)=489 */ {25990, xed3_phash_find_mapevex_map5_opcode0x79_vv2_489_l1}, +/*h(12693)=490 */ {12693, xed3_phash_find_mapevex_map5_opcode0x79_vv2_490_l1}, +/*h(5551)=491 */ {5551, xed3_phash_find_mapevex_map5_opcode0x79_vv2_491_l1}, +/*h(21898)=492 */ {21898, xed3_phash_find_mapevex_map5_opcode0x79_vv2_492_l1}, +/*h(20911)=493 */ {20911, xed3_phash_find_mapevex_map5_opcode0x79_vv2_493_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1459)=495 */ {1459, xed3_phash_find_mapevex_map5_opcode0x79_vv2_495_l1}, +/*h(17806)=496 */ {17806, xed3_phash_find_mapevex_map5_opcode0x79_vv2_496_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3522)=498 */ {3522, xed3_phash_find_mapevex_map5_opcode0x79_vv2_498_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7559)=500 */ {7559, xed3_phash_find_mapevex_map5_opcode0x79_vv2_500_l1}, +/*h(417)=501 */ {417, xed3_phash_find_mapevex_map5_opcode0x79_vv2_501_l1}, +/*h(21932)=502 */ {21932, xed3_phash_find_mapevex_map5_opcode0x79_vv2_502_l1}, +/*h(9622)=503 */ {9622, xed3_phash_find_mapevex_map5_opcode0x79_vv2_503_l1}, +/*h(24982)=504 */ {24982, xed3_phash_find_mapevex_map5_opcode0x79_vv2_504_l1}, +/*h(17840)=505 */ {17840, xed3_phash_find_mapevex_map5_opcode0x79_vv2_505_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8580)=509 */ {8580, xed3_phash_find_mapevex_map5_opcode0x79_vv2_509_l1}, +/*h(30095)=510 */ {30095, xed3_phash_find_mapevex_map5_opcode0x79_vv2_510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4488)=512 */ {4488, xed3_phash_find_mapevex_map5_opcode0x79_vv2_512_l1}, +/*h(26003)=513 */ {26003, xed3_phash_find_mapevex_map5_opcode0x79_vv2_513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11719)=515 */ {11719, xed3_phash_find_mapevex_map5_opcode0x79_vv2_515_l1}, +/*h(21911)=516 */ {21911, xed3_phash_find_mapevex_map5_opcode0x79_vv2_516_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9601)=518 */ {9601, xed3_phash_find_mapevex_map5_opcode0x79_vv2_518_l1}, +/*h(24961)=519 */ {24961, xed3_phash_find_mapevex_map5_opcode0x79_vv2_519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5509)=521 */ {5509, xed3_phash_find_mapevex_map5_opcode0x79_vv2_521_l1}, +/*h(3535)=522 */ {3535, xed3_phash_find_mapevex_map5_opcode0x79_vv2_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1417)=524 */ {1417, xed3_phash_find_mapevex_map5_opcode0x79_vv2_524_l1}, +/*h(430)=525 */ {430, xed3_phash_find_mapevex_map5_opcode0x79_vv2_525_l1}, +/*h(16777)=526 */ {16777, xed3_phash_find_mapevex_map5_opcode0x79_vv2_526_l1}, +/*h(9635)=527 */ {9635, xed3_phash_find_mapevex_map5_opcode0x79_vv2_527_l1}, +/*h(24995)=528 */ {24995, xed3_phash_find_mapevex_map5_opcode0x79_vv2_528_l1}, +/*h(12685)=529 */ {12685, xed3_phash_find_mapevex_map5_opcode0x79_vv2_529_l1}, +/*h(5543)=530 */ {5543, xed3_phash_find_mapevex_map5_opcode0x79_vv2_530_l1}, +/*h(21890)=531 */ {21890, xed3_phash_find_mapevex_map5_opcode0x79_vv2_531_l1}, +/*h(20903)=532 */ {20903, xed3_phash_find_mapevex_map5_opcode0x79_vv2_532_l1}, +/*h(8593)=533 */ {8593, xed3_phash_find_mapevex_map5_opcode0x79_vv2_533_l1}, +/*h(1451)=534 */ {1451, xed3_phash_find_mapevex_map5_opcode0x79_vv2_534_l1}, +/*h(17798)=535 */ {17798, xed3_phash_find_mapevex_map5_opcode0x79_vv2_535_l1}, +/*h(4501)=536 */ {4501, xed3_phash_find_mapevex_map5_opcode0x79_vv2_536_l1}, +/*h(26016)=537 */ {26016, xed3_phash_find_mapevex_map5_opcode0x79_vv2_537_l1}, +/*h(12719)=538 */ {12719, xed3_phash_find_mapevex_map5_opcode0x79_vv2_538_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21924)=540 */ {21924, xed3_phash_find_mapevex_map5_opcode0x79_vv2_540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9614)=542 */ {9614, xed3_phash_find_mapevex_map5_opcode0x79_vv2_542_l1}, +/*h(24974)=543 */ {24974, xed3_phash_find_mapevex_map5_opcode0x79_vv2_543_l1}, +/*h(17832)=544 */ {17832, xed3_phash_find_mapevex_map5_opcode0x79_vv2_544_l1}, +/*h(5522)=545 */ {5522, xed3_phash_find_mapevex_map5_opcode0x79_vv2_545_l1}, +/*h(20882)=546 */ {20882, xed3_phash_find_mapevex_map5_opcode0x79_vv2_546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30087)=548 */ {30087, xed3_phash_find_mapevex_map5_opcode0x79_vv2_548_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16790)=550 */ {16790, xed3_phash_find_mapevex_map5_opcode0x79_vv2_550_l1}, +/*h(9648)=551 */ {9648, xed3_phash_find_mapevex_map5_opcode0x79_vv2_551_l1}, +/*h(25995)=552 */ {25995, xed3_phash_find_mapevex_map5_opcode0x79_vv2_552_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5556)=554 */ {5556, xed3_phash_find_mapevex_map5_opcode0x79_vv2_554_l1}, +/*h(21903)=555 */ {21903, xed3_phash_find_mapevex_map5_opcode0x79_vv2_555_l1}, +/*h(20916)=556 */ {20916, xed3_phash_find_mapevex_map5_opcode0x79_vv2_556_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17811)=559 */ {17811, xed3_phash_find_mapevex_map5_opcode0x79_vv2_559_l1}, +/*h(3527)=560 */ {3527, xed3_phash_find_mapevex_map5_opcode0x79_vv2_560_l1}, +/*h(26029)=561 */ {26029, xed3_phash_find_mapevex_map5_opcode0x79_vv2_561_l1}, +/*h(13719)=562 */ {13719, xed3_phash_find_mapevex_map5_opcode0x79_vv2_562_l1}, +/*h(1409)=563 */ {1409, xed3_phash_find_mapevex_map5_opcode0x79_vv2_563_l1}, +/*h(21937)=564 */ {21937, xed3_phash_find_mapevex_map5_opcode0x79_vv2_564_l1}, +/*h(16769)=565 */ {16769, xed3_phash_find_mapevex_map5_opcode0x79_vv2_565_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17845)=568 */ {17845, xed3_phash_find_mapevex_map5_opcode0x79_vv2_568_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8585)=571 */ {8585, xed3_phash_find_mapevex_map5_opcode0x79_vv2_571_l1}, +/*h(1443)=572 */ {1443, xed3_phash_find_mapevex_map5_opcode0x79_vv2_572_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16803)=574 */ {16803, xed3_phash_find_mapevex_map5_opcode0x79_vv2_574_l1}, +/*h(4493)=575 */ {4493, xed3_phash_find_mapevex_map5_opcode0x79_vv2_575_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12711)=577 */ {12711, xed3_phash_find_mapevex_map5_opcode0x79_vv2_577_l1}, +/*h(401)=578 */ {401, xed3_phash_find_mapevex_map5_opcode0x79_vv2_578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9606)=580 */ {9606, xed3_phash_find_mapevex_map5_opcode0x79_vv2_580_l1}, +/*h(8619)=581 */ {8619, xed3_phash_find_mapevex_map5_opcode0x79_vv2_581_l1}, +/*h(24966)=582 */ {24966, xed3_phash_find_mapevex_map5_opcode0x79_vv2_582_l1}, +/*h(17824)=583 */ {17824, xed3_phash_find_mapevex_map5_opcode0x79_vv2_583_l1}, +/*h(5514)=584 */ {5514, xed3_phash_find_mapevex_map5_opcode0x79_vv2_584_l1}, +/*h(20874)=585 */ {20874, xed3_phash_find_mapevex_map5_opcode0x79_vv2_585_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1422)=587 */ {1422, xed3_phash_find_mapevex_map5_opcode0x79_vv2_587_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9640)=589 */ {9640, xed3_phash_find_mapevex_map5_opcode0x79_vv2_589_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25987)=591 */ {25987, xed3_phash_find_mapevex_map5_opcode0x79_vv2_591_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5548)=593 */ {5548, xed3_phash_find_mapevex_map5_opcode0x79_vv2_593_l1}, +/*h(21895)=594 */ {21895, xed3_phash_find_mapevex_map5_opcode0x79_vv2_594_l1}, +/*h(8598)=595 */ {8598, xed3_phash_find_mapevex_map5_opcode0x79_vv2_595_l1}, +/*h(1456)=596 */ {1456, xed3_phash_find_mapevex_map5_opcode0x79_vv2_596_l1}, +/*h(17803)=597 */ {17803, xed3_phash_find_mapevex_map5_opcode0x79_vv2_597_l1}, +/*h(16816)=598 */ {16816, xed3_phash_find_mapevex_map5_opcode0x79_vv2_598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26021)=600 */ {26021, xed3_phash_find_mapevex_map5_opcode0x79_vv2_600_l1}, +/*h(13711)=601 */ {13711, xed3_phash_find_mapevex_map5_opcode0x79_vv2_601_l1}, +/*h(29071)=602 */ {29071, xed3_phash_find_mapevex_map5_opcode0x79_vv2_602_l1}, +/*h(21929)=603 */ {21929, xed3_phash_find_mapevex_map5_opcode0x79_vv2_603_l1}, +/*h(9619)=604 */ {9619, xed3_phash_find_mapevex_map5_opcode0x79_vv2_604_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24979)=606 */ {24979, xed3_phash_find_mapevex_map5_opcode0x79_vv2_606_l1}, +/*h(17837)=607 */ {17837, xed3_phash_find_mapevex_map5_opcode0x79_vv2_607_l1}, +/*h(5527)=608 */ {5527, xed3_phash_find_mapevex_map5_opcode0x79_vv2_608_l1}, +/*h(20887)=609 */ {20887, xed3_phash_find_mapevex_map5_opcode0x79_vv2_609_l1}, +/*h(8577)=610 */ {8577, xed3_phash_find_mapevex_map5_opcode0x79_vv2_610_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9653)=613 */ {9653, xed3_phash_find_mapevex_map5_opcode0x79_vv2_613_l1}, +/*h(4485)=614 */ {4485, xed3_phash_find_mapevex_map5_opcode0x79_vv2_614_l1}, +/*h(26000)=615 */ {26000, xed3_phash_find_mapevex_map5_opcode0x79_vv2_615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(393)=617 */ {393, xed3_phash_find_mapevex_map5_opcode0x79_vv2_617_l1}, +/*h(21908)=618 */ {21908, xed3_phash_find_mapevex_map5_opcode0x79_vv2_618_l1}, +/*h(8611)=619 */ {8611, xed3_phash_find_mapevex_map5_opcode0x79_vv2_619_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5506)=623 */ {5506, xed3_phash_find_mapevex_map5_opcode0x79_vv2_623_l1}, +/*h(26034)=624 */ {26034, xed3_phash_find_mapevex_map5_opcode0x79_vv2_624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1414)=626 */ {1414, xed3_phash_find_mapevex_map5_opcode0x79_vv2_626_l1}, +/*h(21942)=627 */ {21942, xed3_phash_find_mapevex_map5_opcode0x79_vv2_627_l1}, +/*h(9632)=628 */ {9632, xed3_phash_find_mapevex_map5_opcode0x79_vv2_628_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24992)=630 */ {24992, xed3_phash_find_mapevex_map5_opcode0x79_vv2_630_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5540)=632 */ {5540, xed3_phash_find_mapevex_map5_opcode0x79_vv2_632_l1}, +/*h(20900)=633 */ {20900, xed3_phash_find_mapevex_map5_opcode0x79_vv2_633_l1}, +/*h(8590)=634 */ {8590, xed3_phash_find_mapevex_map5_opcode0x79_vv2_634_l1}, +/*h(1448)=635 */ {1448, xed3_phash_find_mapevex_map5_opcode0x79_vv2_635_l1}, +/*h(17795)=636 */ {17795, xed3_phash_find_mapevex_map5_opcode0x79_vv2_636_l1}, +/*h(16808)=637 */ {16808, xed3_phash_find_mapevex_map5_opcode0x79_vv2_637_l1}, +/*h(4498)=638 */ {4498, xed3_phash_find_mapevex_map5_opcode0x79_vv2_638_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13703)=640 */ {13703, xed3_phash_find_mapevex_map5_opcode0x79_vv2_640_l1}, +/*h(29063)=641 */ {29063, xed3_phash_find_mapevex_map5_opcode0x79_vv2_641_l1}, +/*h(21921)=642 */ {21921, xed3_phash_find_mapevex_map5_opcode0x79_vv2_642_l1}, +/*h(15766)=643 */ {15766, xed3_phash_find_mapevex_map5_opcode0x79_vv2_643_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17829)=645 */ {17829, xed3_phash_find_mapevex_map5_opcode0x79_vv2_645_l1}, +/*h(5519)=646 */ {5519, xed3_phash_find_mapevex_map5_opcode0x79_vv2_646_l1}, +/*h(4532)=647 */ {4532, xed3_phash_find_mapevex_map5_opcode0x79_vv2_647_l1}, +/*h(20879)=648 */ {20879, xed3_phash_find_mapevex_map5_opcode0x79_vv2_648_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1427)=650 */ {1427, xed3_phash_find_mapevex_map5_opcode0x79_vv2_650_l1}, +/*h(16787)=651 */ {16787, xed3_phash_find_mapevex_map5_opcode0x79_vv2_651_l1}, +/*h(9645)=652 */ {9645, xed3_phash_find_mapevex_map5_opcode0x79_vv2_652_l1}, +/*h(25992)=653 */ {25992, xed3_phash_find_mapevex_map5_opcode0x79_vv2_653_l1}, +/*h(25005)=654 */ {25005, xed3_phash_find_mapevex_map5_opcode0x79_vv2_654_l1}, +/*h(12695)=655 */ {12695, xed3_phash_find_mapevex_map5_opcode0x79_vv2_655_l1}, +/*h(5553)=656 */ {5553, xed3_phash_find_mapevex_map5_opcode0x79_vv2_656_l1}, +/*h(21900)=657 */ {21900, xed3_phash_find_mapevex_map5_opcode0x79_vv2_657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1461)=659 */ {1461, xed3_phash_find_mapevex_map5_opcode0x79_vv2_659_l1}, +/*h(17808)=660 */ {17808, xed3_phash_find_mapevex_map5_opcode0x79_vv2_660_l1}, +/*h(16821)=661 */ {16821, xed3_phash_find_mapevex_map5_opcode0x79_vv2_661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26026)=663 */ {26026, xed3_phash_find_mapevex_map5_opcode0x79_vv2_663_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(419)=665 */ {419, xed3_phash_find_mapevex_map5_opcode0x79_vv2_665_l1}, +/*h(21934)=666 */ {21934, xed3_phash_find_mapevex_map5_opcode0x79_vv2_666_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17842)=669 */ {17842, xed3_phash_find_mapevex_map5_opcode0x79_vv2_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8582)=673 */ {8582, xed3_phash_find_mapevex_map5_opcode0x79_vv2_673_l1}, +/*h(1440)=674 */ {1440, xed3_phash_find_mapevex_map5_opcode0x79_vv2_674_l1}, +/*h(16800)=675 */ {16800, xed3_phash_find_mapevex_map5_opcode0x79_vv2_675_l1}, +/*h(4490)=676 */ {4490, xed3_phash_find_mapevex_map5_opcode0x79_vv2_676_l1}, +/*h(26005)=677 */ {26005, xed3_phash_find_mapevex_map5_opcode0x79_vv2_677_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(398)=680 */ {398, xed3_phash_find_mapevex_map5_opcode0x79_vv2_680_l1}, +/*h(15758)=681 */ {15758, xed3_phash_find_mapevex_map5_opcode0x79_vv2_681_l1}, +/*h(9603)=682 */ {9603, xed3_phash_find_mapevex_map5_opcode0x79_vv2_682_l1}, +/*h(24963)=683 */ {24963, xed3_phash_find_mapevex_map5_opcode0x79_vv2_683_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11666)=685 */ {11666, xed3_phash_find_mapevex_map5_opcode0x79_vv2_685_l1}, +/*h(26039)=686 */ {26039, xed3_phash_find_mapevex_map5_opcode0x79_vv2_686_l1}, +/*h(20871)=687 */ {20871, xed3_phash_find_mapevex_map5_opcode0x79_vv2_687_l1}, +/*h(7574)=688 */ {7574, xed3_phash_find_mapevex_map5_opcode0x79_vv2_688_l1}, +/*h(1419)=689 */ {1419, xed3_phash_find_mapevex_map5_opcode0x79_vv2_689_l1}, +/*h(16779)=690 */ {16779, xed3_phash_find_mapevex_map5_opcode0x79_vv2_690_l1}, +/*h(9637)=691 */ {9637, xed3_phash_find_mapevex_map5_opcode0x79_vv2_691_l1}, +/*h(25984)=692 */ {25984, xed3_phash_find_mapevex_map5_opcode0x79_vv2_692_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5545)=694 */ {5545, xed3_phash_find_mapevex_map5_opcode0x79_vv2_694_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 696ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[78] = { +/*h(158)=0 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {158, 7237}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(159)=3 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {159, 7242}, +/*h(923)=4 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {923, 7235}, +/*h(344)=5 EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {344, 7180}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=8 EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {345, 7180}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(346)=11 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7179}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(347)=14 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 7182}, +/*empty slot1 */ {0,0}, +/*h(927)=16 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {927, 7242}, +/*h(664)=17 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {664, 7236}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(665)=20 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {665, 7236}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(666)=23 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {666, 7234}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(667)=26 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {667, 7235}, +/*h(88)=27 EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {88, 7178}, +/*empty slot1 */ {0,0}, +/*h(668)=29 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {668, 7243}, +/*h(89)=30 EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {89, 7178}, +/*empty slot1 */ {0,0}, +/*h(669)=32 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {669, 7243}, +/*h(90)=33 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7177}, +/*empty slot1 */ {0,0}, +/*h(670)=35 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {670, 7241}, +/*h(91)=36 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 7182}, +/*empty slot1 */ {0,0}, +/*h(671)=38 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {671, 7242}, +/*h(408)=39 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {408, 7233}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(409)=42 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {409, 7233}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(410)=45 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {410, 7232}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(411)=48 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {411, 7235}, +/*h(859)=49 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 7182}, +/*empty slot1 */ {0,0}, +/*h(412)=51 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {412, 7240}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(413)=54 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {413, 7240}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(414)=57 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {414, 7239}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(415)=60 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {415, 7242}, +/*h(152)=61 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {152, 7231}, +/*h(600)=62 EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {600, 7183}, +/*empty slot1 */ {0,0}, +/*h(153)=64 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {153, 7231}, +/*h(601)=65 EVV 0x7A V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {601, 7183}, +/*empty slot1 */ {0,0}, +/*h(154)=67 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {154, 7230}, +/*h(602)=68 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7181}, +/*empty slot1 */ {0,0}, +/*h(155)=70 EVV 0x7A VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {155, 7235}, +/*h(603)=71 EVV 0x7A V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 7182}, +/*empty slot1 */ {0,0}, +/*h(156)=73 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {156, 7238}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(157)=76 EVV 0x7A VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {157, 7238}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 79) % 78); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(708)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {708, 7082}, +/*h(6863)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6863, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_367_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5706)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5706, 7249}, +/*h(15055)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {15055, 7087}, +/*h(8900)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8900, 7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(716)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {716, 7082}, +/*h(3910)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3910, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2753)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2753, 7085}, +/*h(1766)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1766, 7247}, +/*h(8908)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8908, 7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3918)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3918, 7247}, +/*h(724)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {724, 7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8916)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8916, 7082}, +/*h(2761)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2761, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_588_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(710)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {710, 7082}, +/*h(5878)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {5878, 7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3734)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {3734, 7244}, +/*h(8902)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8902, 7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(718)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8910)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_507_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(726)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {7082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8918)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8918, 7082}, +/*h(2763)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2763, 7085}, +/*h(3750)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3750, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((9*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(704)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {704, 7083}, +/*h(8079)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8079, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8896)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3906)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3906, 7249}, +/*h(712)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {712, 7083}, +/*h(8087)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {8087, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_713_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8904)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8904, 7083}, +/*h(5710)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5710, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_672_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5718)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {5718, 7244}, +/*h(8912)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8912, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3730)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3730, 7246}, +/*h(7911)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7911, 7248}, +/*h(8898)=2 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8898, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8906)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8906, 7083}, +/*h(7919)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7919, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(722)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {722, 7083}, +/*h(5890)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5890, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3746)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3746, 7249}, +/*h(7927)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7927, 7251}, +/*h(8914)=2 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8914, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(705)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 705; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7910)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7910, 7247}, +/*h(5703)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5703, 7248}, +/*h(8897)=2 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8897, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(713)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5711)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5711, 7248}, +/*h(8905)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8905, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(721)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8913)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {8913, 7083}, +/*h(7926)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7926, 7250}, +/*h(2758)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2758, 7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_695_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8082)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8082, 7246}, +/*h(707)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {707, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_647_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8899)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1702)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1702, 7247}, +/*h(715)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {715, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_606_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8907)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1710)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1710, 7247}, +/*h(723)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {723, 7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8915)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2756)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2756, 7084}, +/*h(8911)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8911, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7754)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7754, 7249}, +/*h(10948)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10948, 7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5958)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5958, 7247}, +/*h(2764)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2764, 7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(10956)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10956, 7084}, +/*h(3814)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3814, 7247}, +/*h(4801)=2 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4801, 7088}, +/*h(1607)=3 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1607, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((7*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2772)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2772, 7084}, +/*h(5966)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5966, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4809)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4809, 7088}, +/*h(1615)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1615, 7248}, +/*h(10964)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10964, 7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10950)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10950, 7084}, +/*h(5782)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {5782, 7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2766)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1986)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1986, 7249}, +/*h(10958)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10958, 7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2774)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5798)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5798, 7247}, +/*h(4811)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4811, 7088}, +/*h(10966)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10966, 7084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2752)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10944)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_566_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2760)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2760, 7085}, +/*h(5954)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5954, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7758)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7758, 7247}, +/*h(10952)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10952, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2768)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7766)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7766, 7244}, +/*h(10960)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10960, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2754)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2754, 7085}, +/*h(1767)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1767, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5778)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5778, 7246}, +/*h(10946)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10946, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2762)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2762, 7085}, +/*h(1775)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1775, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10954)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_698_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1783)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {1783, 7251}, +/*h(7938)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7938, 7249}, +/*h(2770)=2 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2770, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10962)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10962, 7085}, +/*h(5794)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5794, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7751)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7751, 7248}, +/*h(10945)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10945, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10953)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10953, 7085}, +/*h(7759)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7759, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1782)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {1782, 7250}, +/*h(2769)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2769, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4806)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4806, 7086}, +/*h(10961)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10961, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2755)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10947)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_411_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1606)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1606, 7247}, +/*h(10955)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10955, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_418_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3758)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3758, 7247}, +/*h(2771)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {2771, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1991)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1991, 7248}, +/*h(10963)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {10963, 7085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10959)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {10959, 7087}, +/*h(4804)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4804, 7086}, +/*h(1610)=2 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1610, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12996)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4812)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4812, 7086}, +/*h(8006)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {8006, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5862)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5862, 7247}, +/*h(3655)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3655, 7248}, +/*h(13004)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13004, 7086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4820)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4820, 7086}, +/*h(8014)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {8014, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13012)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13012, 7086}, +/*h(3663)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3663, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7830)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7830, 7244}, +/*h(12998)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {12998, 7086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4814)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4034)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {4034, 7249}, +/*h(13006)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13006, 7086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4822)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {7086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13014)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13014, 7086}, +/*h(7846)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7846, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(709)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7914)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7914, 7249}, +/*h(8901)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8901, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1770)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1770, 7249}, +/*h(2757)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {2757, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10949)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_478_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3818)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3818, 7249}, +/*h(4805)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4805, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12997)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5866)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5866, 7249}, +/*h(6853)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6853, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15045)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15045; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(717)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {717, 7087}, +/*h(3911)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3911, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7922)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7922, 7252}, +/*h(8909)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8909, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2765)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {2765, 7087}, +/*h(1778)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {1778, 7252}, +/*h(5959)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5959, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10957)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8007)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8007, 7248}, +/*h(3826)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {3826, 7252}, +/*h(4813)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4813, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_389_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13005)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5874)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {5874, 7252}, +/*h(6861)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6861, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15053)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(725)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 725; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1542)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1542, 7247}, +/*h(8917)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8917, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2773)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_543_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3590)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3590, 7247}, +/*h(10965)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {10965, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4821)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5638)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5638, 7247}, +/*h(13013)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13013, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6869)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7686)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7686, 7247}, +/*h(15061)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {15061, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8086)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {8086, 7244}, +/*h(711)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {711, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3735)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {3735, 7245}, +/*h(8903)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8903, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2759)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1602)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1602, 7249}, +/*h(10951)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {10951, 7087}, +/*h(5783)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {5783, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4807)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(12999)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12999, 7087}, +/*h(7831)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7831, 7245}, +/*h(3650)=2 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3650, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6855)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6855, 7087}, +/*h(1687)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1687, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5698)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5698, 7249}, +/*h(15047)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {15047, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(719)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2767)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4815)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3658)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3658, 7249}, +/*h(13007)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13007, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1714)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {1714, 7252}, +/*h(5895)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5895, 7248}, +/*h(727)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {727, 7087}, +/*h(8102)=3 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {8102, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((11*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8919)=0 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8919, 7087}, +/*h(3751)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3751, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3762)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {3762, 7252}, +/*h(2775)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {2775, 7087}, +/*h(7943)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7943, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5799)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5799, 7248}, +/*h(1618)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1618, 7246}, +/*h(10967)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {10967, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_569_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5810)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {5810, 7252}, +/*h(4823)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4823, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3666)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3666, 7246}, +/*h(13015)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13015, 7087}, +/*h(7847)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7847, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7858)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7858, 7252}, +/*h(1703)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1703, 7248}, +/*h(6871)=2 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6871, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5714)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5714, 7246}, +/*h(15063)=1 EVV 0x7B V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {15063, 7087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4800)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12992)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1614)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1614, 7247}, +/*h(8002)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8002, 7249}, +/*h(4808)=2 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4808, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13000)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1622)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {1622, 7244}, +/*h(4816)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4816, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13008)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4802)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4802, 7088}, +/*h(3815)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3815, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1671)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1671, 7248}, +/*h(12994)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {12994, 7088}, +/*h(7826)=2 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7826, 7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4810)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4810, 7088}, +/*h(3823)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3823, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13002)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4818)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4818, 7088}, +/*h(3831)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {3831, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7842)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7842, 7249}, +/*h(13010)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {13010, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12993)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13001)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3830)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {3830, 7250}, +/*h(4817)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4817, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1686)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {1686, 7244}, +/*h(13009)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {13009, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4803)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12995)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3654)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3654, 7247}, +/*h(13003)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {13003, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5806)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5806, 7247}, +/*h(4819)=1 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {4819, 7088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13011)=0 EVV 0x7B V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_QUARTER()*/ {13011, 7088}, +/*h(4039)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4039, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_656_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1558)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3606)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5654)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7702)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1814)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3862)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5910)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7958)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1942)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_699_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3990)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6038)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3670)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1878)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3926)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {3926, 7244}, +/*h(1719)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {1719, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5974)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {5974, 7244}, +/*h(3767)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {3767, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8022)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {8022, 7244}, +/*h(5815)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {5815, 7251}, +/*h(1634)=2 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1634, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1750)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3798)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5846)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7894)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2006)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4054)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6102)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8150)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0*/ {7244} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7714)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7714, 7249}, +/*h(1559)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1559, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3607)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_718_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5655)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_523_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7703)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7970)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7970, 7249}, +/*h(1815)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1815, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3863)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1730)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1730, 7249}, +/*h(5911)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {5911, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_682_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3778)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3778, 7249}, +/*h(7959)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7959, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8098)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8098, 7249}, +/*h(1943)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1943, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3991)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1858)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1858, 7249}, +/*h(6039)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {6039, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7778)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7778, 7249}, +/*h(1623)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1623, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3671)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1538)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1538, 7249}, +/*h(5719)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {5719, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3586)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3586, 7249}, +/*h(7767)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7767, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4086)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {4086, 7250}, +/*h(1879)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1879, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6134)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {6134, 7250}, +/*h(3927)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {3927, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1794)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1794, 7249}, +/*h(8182)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {8182, 7250}, +/*h(5975)=2 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {5975, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3842)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3842, 7249}, +/*h(8023)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {8023, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7906)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7906, 7249}, +/*h(1751)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {1751, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_666_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3799)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1666)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1666, 7249}, +/*h(5847)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {5847, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3714)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3714, 7249}, +/*h(7895)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7895, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2007)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4055)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1922)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1922, 7249}, +/*h(6103)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {6103, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3970)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3970, 7249}, +/*h(8151)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0 mode64 ZEROING=0 MASK=0*/ {8151, 7245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1554)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3602)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5650)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {5650, 7246}, +/*h(1846)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {1846, 7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_457_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7698)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7698, 7246}, +/*h(3894)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {3894, 7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1810)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1810, 7246}, +/*h(5991)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5991, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3858)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3858, 7246}, +/*h(8039)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8039, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5906)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_616_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7954)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1682)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1682, 7246}, +/*h(5863)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5863, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_548_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1938)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1938, 7246}, +/*h(6119)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6119, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3986)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3986, 7246}, +/*h(8167)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8167, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6034)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7762)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1874)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1874, 7246}, +/*h(6055)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6055, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3922)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3922, 7246}, +/*h(8103)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8103, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5970)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8018)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8018, 7246}, +/*h(1863)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1863, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1746)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3794)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5842)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7890)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2002)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {2002, 7246}, +/*h(3599)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3599, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4050)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {4050, 7246}, +/*h(5647)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5647, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6098)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {6098, 7246}, +/*h(7695)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7695, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8146)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 mode64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7246} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1798)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_701_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3846)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3846, 7247}, +/*h(1639)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1639, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5894)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5894, 7247}, +/*h(3687)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3687, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7942)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7942, 7247}, +/*h(5735)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5735, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_85_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1670)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3718)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5766)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7814)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1926)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3974)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6022)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8070)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5702)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7750)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_570_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1862)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_491_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1734)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3782)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5830)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_638_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7878)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_649_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1990)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4038)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {4038, 7247}, +/*h(1831)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1831, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6086)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {6086, 7247}, +/*h(3879)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3879, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8134)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {8134, 7247}, +/*h(5927)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5927, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1574)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3622)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5670)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5670, 7247}, +/*h(1866)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1866, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_721_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7718)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7718, 7247}, +/*h(3914)=1 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3914, 7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1830)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_538_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3878)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5926)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7974)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1958)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4006)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {4006, 7247}, +/*h(1799)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1799, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6054)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {6054, 7247}, +/*h(3847)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3847, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1638)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3686)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5734)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7782)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7782; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1894)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3942)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5990)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8038)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2022)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4070)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6118)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_633_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8166)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1550)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3598)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5646)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7694)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1806)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3854)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3854, 7247}, +/*h(1647)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1647, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_465_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5902)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5902, 7247}, +/*h(3695)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3695, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7950)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7950, 7247}, +/*h(5743)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5743, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1678)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3726)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5774)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7822)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1934)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3982)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3982; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6030)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8078)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8078; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3662)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1870)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_450_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1742)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3790)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5838)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7886)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7886; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1998)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4046)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {4046, 7247}, +/*h(1839)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1839, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6094)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {6094, 7247}, +/*h(3887)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3887, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8142)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {8142, 7247}, +/*h(5935)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5935, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1582)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3630)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3630; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5678)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7726)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1838)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3886)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {3886, 7247}, +/*h(1679)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1679, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_302_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5934)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {5934, 7247}, +/*h(3727)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3727, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7982)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7982, 7247}, +/*h(5775)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5775, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7854)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1966)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4014)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4014; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6062)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6062; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8110)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8110; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1646)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3694)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5742)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7790)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7790; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1902)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3950)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5998)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8046)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8046; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_287_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8162)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8162, 7249}, +/*h(1774)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {1774, 7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3822)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5870)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7918)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7918; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2030)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {7247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4078)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {4078, 7247}, +/*h(1871)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1871, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6126)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {6126, 7247}, +/*h(3919)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3919, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_592_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8174)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0*/ {8174, 7247}, +/*h(5967)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5967, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1543)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1994)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1994, 7249}, +/*h(3591)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3591, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4042)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {4042, 7249}, +/*h(5639)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5639, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6090)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {6090, 7249}, +/*h(7687)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7687, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3719)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1586)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {1586, 7252}, +/*h(5767)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5767, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_684_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3634)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {3634, 7252}, +/*h(7815)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7815, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1927)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3975)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1842)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {1842, 7252}, +/*h(6023)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6023, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3890)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {3890, 7252}, +/*h(8071)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8071, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1735)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3783)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1650)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {1650, 7252}, +/*h(5831)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5831, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3698)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {3698, 7252}, +/*h(7879)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7879, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1906)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {1906, 7252}, +/*h(6087)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6087, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_517_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3954)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {3954, 7252}, +/*h(8135)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8135, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1575)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2026)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {2026, 7249}, +/*h(3623)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3623, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4074)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {4074, 7249}, +/*h(5671)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5671, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6122)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {6122, 7249}, +/*h(7719)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7719, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7975)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1959)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4007)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7783)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8050)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {8050, 7252}, +/*h(1895)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1895, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_664_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3943)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8178)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {8178, 7252}, +/*h(2023)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {2023, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4071)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1551)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1807)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3855)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5903)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_723_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7951)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_644_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7823)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7823; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1935)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_460_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3983)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3983; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6031)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8015)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8015; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1743)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3791)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5839)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7887)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7887; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1999)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4047)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4047; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_671_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6095)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8143)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1583)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1583; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2034)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {2034, 7252}, +/*h(3631)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3631, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_596_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4082)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {4082, 7252}, +/*h(5679)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5679, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_401_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6130)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {6130, 7252}, +/*h(7727)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7727, 7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7983)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7983; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1711)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3759)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_675_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5807)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7855)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1967)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4015)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4015; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6063)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8111)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8111; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7791)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1903)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_623_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3951)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5999)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8047)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8047; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5871)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2031)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4079)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4079; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6127)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6127; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8175)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7248} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8175; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5634)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_539_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7682)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5762)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7810)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7810; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6018)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8066)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7746)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7746, 7249}, +/*h(1591)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {1591, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_487_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5826)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7874)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6082)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8130)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8130, 7249}, +/*h(1975)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {1975, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_229_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1570)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1570, 7249}, +/*h(5751)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {5751, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3618)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3618, 7249}, +/*h(7799)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7799, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5666)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1826)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1826, 7249}, +/*h(6007)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {6007, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3874)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3874, 7249}, +/*h(8055)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {8055, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5922)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1698)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1698, 7249}, +/*h(5879)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {5879, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1954)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1954, 7249}, +/*h(6135)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {6135, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4002)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {4002, 7249}, +/*h(8183)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {8183, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6050)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3682)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3682, 7249}, +/*h(7863)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7863, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5730)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1890)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1890, 7249}, +/*h(6071)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {6071, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_598_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3938)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3938, 7249}, +/*h(8119)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {8119, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5986)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8034)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_714_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1762)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {1762, 7249}, +/*h(5943)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {5943, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3810)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {3810, 7249}, +/*h(7991)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7991, 7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5858)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5858; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2018)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_677_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4066)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_482_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6114)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1546)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3594)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5642)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7690)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1802)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3850)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5898)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7946)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1674)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3722)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5770)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5770; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7818)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7818; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1930)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3978)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6026)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8074)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5962)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8010)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1738)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3786)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5834)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7882)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8138)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1578)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_725_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3626)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_530_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5674)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7722)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1834)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3882)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3882; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_689_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5930)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_494_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7978)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1706)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3754)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5802)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7850)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1962)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4010)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6058)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8106)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8106; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1642)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3690)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_204_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5738)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7786)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1898)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3946)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_362_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5994)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8042)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {8042, 7249}, +/*h(1654)=1 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {1654, 7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8170)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {7249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1590)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3638)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5686)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7734)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_262_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5942)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7990)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1718)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3766)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5814)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_719_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7862)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_731_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1974)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4022)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6070)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8118)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3702)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5750)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7798)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1910)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3958)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6006)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8054)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_404_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2038)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0*/ {7250} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3639)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5687)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7735)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1847)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3895)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4023)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1655)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3703)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1911)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3959)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2039)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_662_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4087)=0 EVV 0x7B VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1 mode64 ZEROING=0 MASK=0*/ {7251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4087; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5682)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_294_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7730)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5938)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7986)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1970)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4018)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6066)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8114)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5746)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7794)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6002)=0 EVV 0x7B VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W1 mode64 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {7252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7b_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[732] = { +/*h(5778)=0 */ {5778, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_0_l1}, +/*h(1830)=1 */ {1830, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_1_l1}, +/*h(5634)=2 */ {5634, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_2_l1}, +/*h(1686)=3 */ {1686, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_3_l1}, +/*h(8074)=4 */ {8074, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_4_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1542)=6 */ {1542, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_6_l1}, +/*h(1775)=7 */ {1775, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_7_l1}, +/*h(3982)=8 */ {3982, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_8_l1}, +/*h(7786)=9 */ {7786, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_9_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4071)=11 */ {4071, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_11_l1}, +/*h(3694)=12 */ {3694, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_12_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6134)=14 */ {6134, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3783)=16 */ {3783, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_16_l1}, +/*h(5990)=17 */ {5990, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_17_l1}, +/*h(3639)=18 */ {3639, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_18_l1}, +/*h(5846)=19 */ {5846, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_19_l1}, +/*h(1898)=20 */ {1898, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_20_l1}, +/*h(5702)=21 */ {5702, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_21_l1}, +/*h(8896)=22 */ {8896, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_22_l1}, +/*h(5935)=23 */ {5935, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_23_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1610)=25 */ {1610, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5647)=27 */ {5647, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_27_l1}, +/*h(7854)=28 */ {7854, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_28_l1}, +/*h(3906)=29 */ {3906, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3762)=32 */ {3762, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7799)=34 */ {7799, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_34_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6058)=36 */ {6058, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1966)=40 */ {1966, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_40_l1}, +/*h(5770)=41 */ {5770, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_41_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13001)=43 */ {13001, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_43_l1}, +/*h(1678)=44 */ {1678, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_44_l1}, +/*h(8066)=45 */ {8066, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_45_l1}, +/*h(1911)=46 */ {1911, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_46_l1}, +/*h(7922)=47 */ {7922, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_47_l1}, +/*h(1767)=48 */ {1767, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_48_l1}, +/*h(3974)=49 */ {3974, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_49_l1}, +/*h(7778)=50 */ {7778, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_50_l1}, +/*h(3830)=51 */ {3830, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_51_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3686)=53 */ {3686, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_53_l1}, +/*h(725)=54 */ {725, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_54_l1}, +/*h(3919)=55 */ {3919, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2034)=59 */ {2034, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_59_l1}, +/*h(5838)=60 */ {5838, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_60_l1}, +/*h(6071)=61 */ {6071, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_61_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1746)=63 */ {1746, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_63_l1}, +/*h(5927)=64 */ {5927, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1602)=66 */ {1602, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_66_l1}, +/*h(7990)=67 */ {7990, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_67_l1}, +/*h(4042)=68 */ {4042, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_68_l1}, +/*h(7846)=69 */ {7846, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_69_l1}, +/*h(8079)=70 */ {8079, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_70_l1}, +/*h(7702)=71 */ {7702, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_71_l1}, +/*h(3754)=72 */ {3754, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_72_l1}, +/*h(2767)=73 */ {2767, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_73_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7791)=75 */ {7791, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_75_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6050)=77 */ {6050, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5906)=79 */ {5906, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_79_l1}, +/*h(1958)=80 */ {1958, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_80_l1}, +/*h(5762)=81 */ {5762, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_81_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1814)=83 */ {1814, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_83_l1}, +/*h(12993)=84 */ {12993, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_84_l1}, +/*h(1670)=85 */ {1670, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_85_l1}, +/*h(1903)=86 */ {1903, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7914)=88 */ {7914, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_88_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1615)=91 */ {1615, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_91_l1}, +/*h(3822)=92 */ {3822, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_92_l1}, +/*h(4055)=93 */ {4055, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3911)=95 */ {3911, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_95_l1}, +/*h(6118)=96 */ {6118, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_96_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3767)=98 */ {3767, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2026)=100 */ {2026, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_100_l1}, +/*h(5830)=101 */ {5830, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_101_l1}, +/*h(6063)=102 */ {6063, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_102_l1}, +/*h(5686)=103 */ {5686, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_103_l1}, +/*h(1738)=104 */ {1738, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_104_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5775)=107 */ {5775, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4034)=109 */ {4034, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_109_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3890)=111 */ {3890, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_111_l1}, +/*h(7694)=112 */ {7694, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_112_l1}, +/*h(7927)=113 */ {7927, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_113_l1}, +/*h(2759)=114 */ {2759, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_114_l1}, +/*h(3602)=115 */ {3602, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_115_l1}, +/*h(7783)=116 */ {7783, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_116_l1}, +/*h(4822)=117 */ {4822, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5898)=120 */ {5898, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1806)=123 */ {1806, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2039)=125 */ {2039, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8050)=127 */ {8050, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7906)=129 */ {7906, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_129_l1}, +/*h(3958)=130 */ {3958, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_130_l1}, +/*h(7762)=131 */ {7762, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_131_l1}, +/*h(1607)=132 */ {1607, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4047)=134 */ {4047, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_134_l1}, +/*h(3670)=135 */ {3670, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_135_l1}, +/*h(709)=136 */ {709, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_136_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3759)=138 */ {3759, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_138_l1}, +/*h(5966)=139 */ {5966, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_139_l1}, +/*h(2018)=140 */ {2018, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6055)=143 */ {6055, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_143_l1}, +/*h(5678)=144 */ {5678, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_144_l1}, +/*h(1730)=145 */ {1730, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_145_l1}, +/*h(8118)=146 */ {8118, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_146_l1}, +/*h(1586)=147 */ {1586, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_147_l1}, +/*h(7974)=148 */ {7974, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_148_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7830)=150 */ {7830, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_150_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3882)=152 */ {3882, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_152_l1}, +/*h(7686)=153 */ {7686, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_153_l1}, +/*h(7919)=154 */ {7919, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3594)=156 */ {3594, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_156_l1}, +/*h(4814)=157 */ {4814, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_157_l1}, +/*h(6034)=158 */ {6034, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_158_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5890)=161 */ {5890, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_161_l1}, +/*h(1942)=162 */ {1942, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_162_l1}, +/*h(5746)=163 */ {5746, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_163_l1}, +/*h(1798)=164 */ {1798, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_164_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2031)=166 */ {2031, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_166_l1}, +/*h(1654)=167 */ {1654, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1743)=170 */ {1743, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_170_l1}, +/*h(3950)=171 */ {3950, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_171_l1}, +/*h(7754)=172 */ {7754, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4039)=175 */ {4039, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_175_l1}, +/*h(3662)=176 */ {3662, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_176_l1}, +/*h(3895)=177 */ {3895, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_177_l1}, +/*h(6102)=178 */ {6102, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_178_l1}, +/*h(3751)=179 */ {3751, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_179_l1}, +/*h(5958)=180 */ {5958, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_180_l1}, +/*h(3607)=181 */ {3607, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_181_l1}, +/*h(5814)=182 */ {5814, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_182_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1866)=184 */ {1866, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5903)=186 */ {5903, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_186_l1}, +/*h(8110)=187 */ {8110, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_187_l1}, +/*h(1578)=188 */ {1578, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4018)=190 */ {4018, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_190_l1}, +/*h(7822)=191 */ {7822, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8055)=193 */ {8055, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_193_l1}, +/*h(15053)=194 */ {15053, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_194_l1}, +/*h(7911)=195 */ {7911, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3586)=197 */ {3586, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_197_l1}, +/*h(4806)=198 */ {4806, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_198_l1}, +/*h(6026)=199 */ {6026, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6869)=201 */ {6869, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_201_l1}, +/*h(714)=202 */ {714, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_202_l1}, +/*h(1934)=203 */ {1934, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_203_l1}, +/*h(5738)=204 */ {5738, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_204_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8178)=206 */ {8178, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_206_l1}, +/*h(1646)=207 */ {1646, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_207_l1}, +/*h(8034)=208 */ {8034, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_208_l1}, +/*h(4086)=209 */ {4086, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_209_l1}, +/*h(7890)=210 */ {7890, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_210_l1}, +/*h(1735)=211 */ {1735, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_211_l1}, +/*h(3942)=212 */ {3942, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_212_l1}, +/*h(1591)=213 */ {1591, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_213_l1}, +/*h(3798)=214 */ {3798, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_214_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3654)=216 */ {3654, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_216_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3887)=218 */ {3887, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_218_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8911)=220 */ {8911, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3599)=222 */ {3599, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_222_l1}, +/*h(5806)=223 */ {5806, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_223_l1}, +/*h(1858)=224 */ {1858, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1714)=227 */ {1714, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5751)=229 */ {5751, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_229_l1}, +/*h(7958)=230 */ {7958, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_230_l1}, +/*h(4010)=231 */ {4010, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_231_l1}, +/*h(7814)=232 */ {7814, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_232_l1}, +/*h(8047)=233 */ {8047, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_233_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15045)=235 */ {15045, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_235_l1}, +/*h(3722)=236 */ {3722, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_236_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7759)=238 */ {7759, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6018)=240 */ {6018, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5874)=242 */ {5874, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_242_l1}, +/*h(706)=243 */ {706, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_243_l1}, +/*h(1926)=244 */ {1926, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_244_l1}, +/*h(5730)=245 */ {5730, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_245_l1}, +/*h(1782)=246 */ {1782, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_246_l1}, +/*h(8170)=247 */ {8170, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_247_l1}, +/*h(1638)=248 */ {1638, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_248_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1871)=250 */ {1871, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_250_l1}, +/*h(7882)=251 */ {7882, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_251_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1583)=254 */ {1583, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_254_l1}, +/*h(3790)=255 */ {3790, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_255_l1}, +/*h(4023)=256 */ {4023, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_256_l1}, +/*h(12995)=257 */ {12995, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3879)=259 */ {3879, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3735)=261 */ {3735, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_261_l1}, +/*h(5942)=262 */ {5942, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_262_l1}, +/*h(1994)=263 */ {1994, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_263_l1}, +/*h(5798)=264 */ {5798, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_264_l1}, +/*h(6031)=265 */ {6031, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_265_l1}, +/*h(5654)=266 */ {5654, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_266_l1}, +/*h(1706)=267 */ {1706, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_267_l1}, +/*h(719)=268 */ {719, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5743)=270 */ {5743, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8183)=272 */ {8183, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_272_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8039)=274 */ {8039, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_274_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3714)=276 */ {3714, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7751)=279 */ {7751, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13008)=282 */ {13008, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_282_l1}, +/*h(5866)=283 */ {5866, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2761)=286 */ {2761, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_286_l1}, +/*h(8162)=287 */ {8162, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_287_l1}, +/*h(2007)=288 */ {2007, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1863)=290 */ {1863, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_290_l1}, +/*h(4070)=291 */ {4070, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_291_l1}, +/*h(7874)=292 */ {7874, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_292_l1}, +/*h(1719)=293 */ {1719, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_293_l1}, +/*h(7730)=294 */ {7730, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_294_l1}, +/*h(1575)=295 */ {1575, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_295_l1}, +/*h(3782)=296 */ {3782, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_296_l1}, +/*h(4015)=297 */ {4015, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_297_l1}, +/*h(3638)=298 */ {3638, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3727)=302 */ {3727, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1986)=304 */ {1986, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_304_l1}, +/*h(4803)=305 */ {4803, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_305_l1}, +/*h(1842)=306 */ {1842, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_306_l1}, +/*h(5646)=307 */ {5646, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_307_l1}, +/*h(5879)=308 */ {5879, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_308_l1}, +/*h(8086)=309 */ {8086, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_309_l1}, +/*h(1554)=310 */ {1554, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_310_l1}, +/*h(5735)=311 */ {5735, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_311_l1}, +/*h(2774)=312 */ {2774, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_312_l1}, +/*h(8175)=313 */ {8175, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_313_l1}, +/*h(7798)=314 */ {7798, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_314_l1}, +/*h(3850)=315 */ {3850, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7887)=317 */ {7887, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6002)=322 */ {6002, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_322_l1}, +/*h(13000)=323 */ {13000, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_323_l1}, +/*h(5858)=324 */ {5858, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_324_l1}, +/*h(1910)=325 */ {1910, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_325_l1}, +/*h(5714)=326 */ {5714, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_326_l1}, +/*h(1766)=327 */ {1766, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1999)=329 */ {1999, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_329_l1}, +/*h(1622)=330 */ {1622, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_330_l1}, +/*h(8010)=331 */ {8010, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_331_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1711)=333 */ {1711, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_333_l1}, +/*h(3918)=334 */ {3918, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_334_l1}, +/*h(7722)=335 */ {7722, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4007)=338 */ {4007, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_338_l1}, +/*h(3630)=339 */ {3630, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_339_l1}, +/*h(3863)=340 */ {3863, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_340_l1}, +/*h(6070)=341 */ {6070, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_341_l1}, +/*h(3719)=342 */ {3719, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_342_l1}, +/*h(5926)=343 */ {5926, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_343_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5782)=345 */ {5782, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1834)=347 */ {1834, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_347_l1}, +/*h(5638)=348 */ {5638, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_348_l1}, +/*h(5871)=349 */ {5871, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_349_l1}, +/*h(8078)=350 */ {8078, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_350_l1}, +/*h(1546)=351 */ {1546, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_351_l1}, +/*h(2766)=352 */ {2766, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_352_l1}, +/*h(8167)=353 */ {8167, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_353_l1}, +/*h(7790)=354 */ {7790, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3842)=356 */ {3842, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3698)=358 */ {3698, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7735)=360 */ {7735, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_360_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5994)=362 */ {5994, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_362_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12992)=364 */ {12992, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1902)=366 */ {1902, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_366_l1}, +/*h(5706)=367 */ {5706, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_367_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8146)=369 */ {8146, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_369_l1}, +/*h(1991)=370 */ {1991, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_370_l1}, +/*h(8002)=371 */ {8002, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_371_l1}, +/*h(1847)=372 */ {1847, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_372_l1}, +/*h(4054)=373 */ {4054, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_373_l1}, +/*h(7858)=374 */ {7858, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_374_l1}, +/*h(3910)=375 */ {3910, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_375_l1}, +/*h(7714)=376 */ {7714, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_376_l1}, +/*h(3766)=377 */ {3766, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3622)=379 */ {3622, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_379_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3855)=381 */ {3855, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_381_l1}, +/*h(6062)=382 */ {6062, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_382_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1970)=385 */ {1970, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_385_l1}, +/*h(5774)=386 */ {5774, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_386_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6007)=388 */ {6007, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_388_l1}, +/*h(13005)=389 */ {13005, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_389_l1}, +/*h(5863)=390 */ {5863, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_390_l1}, +/*h(8070)=391 */ {8070, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_391_l1}, +/*h(1538)=392 */ {1538, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_392_l1}, +/*h(7926)=393 */ {7926, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_393_l1}, +/*h(3978)=394 */ {3978, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_394_l1}, +/*h(7782)=395 */ {7782, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_395_l1}, +/*h(4821)=396 */ {4821, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_396_l1}, +/*h(8015)=397 */ {8015, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3690)=399 */ {3690, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6130)=401 */ {6130, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_401_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5986)=403 */ {5986, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_403_l1}, +/*h(2038)=404 */ {2038, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_404_l1}, +/*h(5842)=405 */ {5842, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1894)=407 */ {1894, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_407_l1}, +/*h(5698)=408 */ {5698, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_408_l1}, +/*h(1750)=409 */ {1750, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_409_l1}, +/*h(8138)=410 */ {8138, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_410_l1}, +/*h(1606)=411 */ {1606, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_411_l1}, +/*h(4800)=412 */ {4800, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_412_l1}, +/*h(1839)=413 */ {1839, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_413_l1}, +/*h(7850)=414 */ {7850, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_414_l1}, +/*h(6863)=415 */ {6863, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1551)=417 */ {1551, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_417_l1}, +/*h(3758)=418 */ {3758, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_418_l1}, +/*h(3991)=419 */ {3991, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3847)=422 */ {3847, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_422_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3703)=424 */ {3703, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_424_l1}, +/*h(5910)=425 */ {5910, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_425_l1}, +/*h(1962)=426 */ {1962, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_426_l1}, +/*h(5766)=427 */ {5766, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_427_l1}, +/*h(5999)=428 */ {5999, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_428_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12997)=430 */ {12997, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_430_l1}, +/*h(1674)=431 */ {1674, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_431_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5711)=433 */ {5711, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_433_l1}, +/*h(7918)=434 */ {7918, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_434_l1}, +/*h(3970)=435 */ {3970, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3826)=437 */ {3826, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7863)=440 */ {7863, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_440_l1}, +/*h(721)=441 */ {721, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_441_l1}, +/*h(6122)=442 */ {6122, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2030)=445 */ {2030, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_445_l1}, +/*h(5834)=446 */ {5834, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_446_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1742)=450 */ {1742, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_450_l1}, +/*h(1975)=451 */ {1975, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_451_l1}, +/*h(10947)=452 */ {10947, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_452_l1}, +/*h(7986)=453 */ {7986, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_453_l1}, +/*h(1831)=454 */ {1831, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_454_l1}, +/*h(7842)=455 */ {7842, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_455_l1}, +/*h(1687)=456 */ {1687, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_456_l1}, +/*h(3894)=457 */ {3894, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_457_l1}, +/*h(1543)=458 */ {1543, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_458_l1}, +/*h(3750)=459 */ {3750, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_459_l1}, +/*h(3983)=460 */ {3983, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_460_l1}, +/*h(3606)=461 */ {3606, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_461_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3695)=465 */ {3695, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_465_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6135)=467 */ {6135, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_467_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5991)=469 */ {5991, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_469_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1666)=471 */ {1666, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_471_l1}, +/*h(8054)=472 */ {8054, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_472_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5703)=474 */ {5703, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8143)=476 */ {8143, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_476_l1}, +/*h(7766)=477 */ {7766, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_477_l1}, +/*h(3818)=478 */ {3818, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7855)=480 */ {7855, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_480_l1}, +/*h(713)=481 */ {713, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_481_l1}, +/*h(6114)=482 */ {6114, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_482_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5970)=485 */ {5970, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_485_l1}, +/*h(2022)=486 */ {2022, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_486_l1}, +/*h(5826)=487 */ {5826, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_487_l1}, +/*h(1878)=488 */ {1878, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_488_l1}, +/*h(5682)=489 */ {5682, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_489_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1734)=491 */ {1734, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_491_l1}, +/*h(1967)=492 */ {1967, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_492_l1}, +/*h(1590)=493 */ {1590, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_493_l1}, +/*h(7978)=494 */ {7978, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_494_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13002)=496 */ {13002, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_496_l1}, +/*h(1679)=497 */ {1679, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_497_l1}, +/*h(7690)=498 */ {7690, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_498_l1}, +/*h(8910)=499 */ {8910, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_499_l1}, +/*h(2755)=500 */ {2755, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_500_l1}, +/*h(3975)=501 */ {3975, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_501_l1}, +/*h(3598)=502 */ {3598, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_502_l1}, +/*h(3831)=503 */ {3831, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_503_l1}, +/*h(6038)=504 */ {6038, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_504_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3687)=506 */ {3687, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_506_l1}, +/*h(726)=507 */ {726, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_507_l1}, +/*h(6127)=508 */ {6127, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_508_l1}, +/*h(5750)=509 */ {5750, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_509_l1}, +/*h(1802)=510 */ {1802, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5839)=512 */ {5839, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_512_l1}, +/*h(8046)=513 */ {8046, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_513_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3954)=517 */ {3954, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_517_l1}, +/*h(7758)=518 */ {7758, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_518_l1}, +/*h(7991)=519 */ {7991, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7847)=521 */ {7847, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_521_l1}, +/*h(705)=522 */ {705, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_522_l1}, +/*h(7703)=523 */ {7703, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_523_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2768)=525 */ {2768, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_525_l1}, +/*h(5962)=526 */ {5962, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_526_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1870)=529 */ {1870, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_529_l1}, +/*h(5674)=530 */ {5674, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_530_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8114)=532 */ {8114, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_532_l1}, +/*h(1959)=533 */ {1959, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_533_l1}, +/*h(1582)=534 */ {1582, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_534_l1}, +/*h(7970)=535 */ {7970, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_535_l1}, +/*h(4022)=536 */ {4022, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_536_l1}, +/*h(1671)=537 */ {1671, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_537_l1}, +/*h(3878)=538 */ {3878, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_538_l1}, +/*h(7682)=539 */ {7682, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_539_l1}, +/*h(3734)=540 */ {3734, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_540_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3590)=543 */ {3590, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_543_l1}, +/*h(3823)=544 */ {3823, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_544_l1}, +/*h(6030)=545 */ {6030, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_545_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(718)=547 */ {718, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_547_l1}, +/*h(6119)=548 */ {6119, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_548_l1}, +/*h(5742)=549 */ {5742, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8182)=551 */ {8182, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_551_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1650)=553 */ {1650, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_553_l1}, +/*h(8038)=554 */ {8038, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_554_l1}, +/*h(5687)=555 */ {5687, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_555_l1}, +/*h(7894)=556 */ {7894, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_556_l1}, +/*h(3946)=557 */ {3946, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_557_l1}, +/*h(7750)=558 */ {7750, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_558_l1}, +/*h(10944)=559 */ {10944, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_559_l1}, +/*h(7983)=560 */ {7983, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_560_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3658)=562 */ {3658, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_562_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7695)=564 */ {7695, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_564_l1}, +/*h(8915)=565 */ {8915, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_565_l1}, +/*h(5954)=566 */ {5954, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_566_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2006)=568 */ {2006, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_568_l1}, +/*h(5810)=569 */ {5810, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_569_l1}, +/*h(1862)=570 */ {1862, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_570_l1}, +/*h(5666)=571 */ {5666, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_571_l1}, +/*h(1718)=572 */ {1718, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_572_l1}, +/*h(8106)=573 */ {8106, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_573_l1}, +/*h(1574)=574 */ {1574, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_574_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1807)=576 */ {1807, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_576_l1}, +/*h(4014)=577 */ {4014, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_577_l1}, +/*h(7818)=578 */ {7818, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3726)=581 */ {3726, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3959)=583 */ {3959, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_583_l1}, +/*h(10957)=584 */ {10957, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_584_l1}, +/*h(3815)=585 */ {3815, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_585_l1}, +/*h(6022)=586 */ {6022, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_586_l1}, +/*h(3671)=587 */ {3671, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_587_l1}, +/*h(5878)=588 */ {5878, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_588_l1}, +/*h(1930)=589 */ {1930, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_589_l1}, +/*h(5734)=590 */ {5734, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_590_l1}, +/*h(2773)=591 */ {2773, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_591_l1}, +/*h(5967)=592 */ {5967, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_592_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1642)=594 */ {1642, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_594_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4082)=596 */ {4082, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_596_l1}, +/*h(7886)=597 */ {7886, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_597_l1}, +/*h(8119)=598 */ {8119, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_598_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3794)=600 */ {3794, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_600_l1}, +/*h(7975)=601 */ {7975, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_601_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3650)=603 */ {3650, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_603_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6090)=605 */ {6090, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_605_l1}, +/*h(8907)=606 */ {8907, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_606_l1}, +/*h(2752)=607 */ {2752, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_607_l1}, +/*h(1998)=608 */ {1998, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_608_l1}, +/*h(5802)=609 */ {5802, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_609_l1}, +/*h(4815)=610 */ {4815, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_610_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1710)=613 */ {1710, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_613_l1}, +/*h(8098)=614 */ {8098, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_614_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7954)=616 */ {7954, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_616_l1}, +/*h(1799)=617 */ {1799, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_617_l1}, +/*h(7810)=618 */ {7810, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_618_l1}, +/*h(1655)=619 */ {1655, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_619_l1}, +/*h(3862)=620 */ {3862, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_620_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3718)=622 */ {3718, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_622_l1}, +/*h(3951)=623 */ {3951, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_623_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10949)=625 */ {10949, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3663)=628 */ {3663, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_628_l1}, +/*h(5870)=629 */ {5870, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_629_l1}, +/*h(1922)=630 */ {1922, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_630_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1778)=632 */ {1778, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_632_l1}, +/*h(8166)=633 */ {8166, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_633_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5815)=635 */ {5815, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_635_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4074)=637 */ {4074, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_637_l1}, +/*h(7878)=638 */ {7878, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_638_l1}, +/*h(8111)=639 */ {8111, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_639_l1}, +/*h(7734)=640 */ {7734, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_640_l1}, +/*h(3786)=641 */ {3786, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_641_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7823)=644 */ {7823, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_644_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6082)=646 */ {6082, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_646_l1}, +/*h(8899)=647 */ {8899, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_647_l1}, +/*h(5938)=648 */ {5938, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_648_l1}, +/*h(1990)=649 */ {1990, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_649_l1}, +/*h(5794)=650 */ {5794, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_650_l1}, +/*h(4807)=651 */ {4807, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_651_l1}, +/*h(1846)=652 */ {1846, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1702)=654 */ {1702, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_654_l1}, +/*h(1935)=655 */ {1935, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_655_l1}, +/*h(1558)=656 */ {1558, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_656_l1}, +/*h(7946)=657 */ {7946, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_657_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1647)=660 */ {1647, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_660_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4087)=662 */ {4087, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_662_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3943)=664 */ {3943, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_664_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3799)=666 */ {3799, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_666_l1}, +/*h(6006)=667 */ {6006, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_667_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3655)=669 */ {3655, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6095)=671 */ {6095, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_671_l1}, +/*h(5718)=672 */ {5718, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_672_l1}, +/*h(1770)=673 */ {1770, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_673_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5807)=675 */ {5807, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_675_l1}, +/*h(8014)=676 */ {8014, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_676_l1}, +/*h(4066)=677 */ {4066, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_677_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8103)=680 */ {8103, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_680_l1}, +/*h(7726)=681 */ {7726, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_681_l1}, +/*h(3778)=682 */ {3778, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_682_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3634)=684 */ {3634, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_684_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5930)=689 */ {5930, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_689_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10954)=691 */ {10954, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_691_l1}, +/*h(1838)=692 */ {1838, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_692_l1}, +/*h(5642)=693 */ {5642, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8082)=695 */ {8082, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_695_l1}, +/*h(1927)=696 */ {1927, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_696_l1}, +/*h(1550)=697 */ {1550, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_697_l1}, +/*h(1783)=698 */ {1783, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_698_l1}, +/*h(3990)=699 */ {3990, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_699_l1}, +/*h(7794)=700 */ {7794, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_700_l1}, +/*h(1639)=701 */ {1639, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_701_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4079)=703 */ {4079, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_703_l1}, +/*h(3702)=704 */ {3702, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_704_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3791)=707 */ {3791, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_707_l1}, +/*h(5998)=708 */ {5998, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_708_l1}, +/*h(12996)=709 */ {12996, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_709_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1906)=712 */ {1906, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_712_l1}, +/*h(5710)=713 */ {5710, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_713_l1}, +/*h(5943)=714 */ {5943, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_714_l1}, +/*h(8150)=715 */ {8150, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_715_l1}, +/*h(5799)=716 */ {5799, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_716_l1}, +/*h(8006)=717 */ {8006, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_717_l1}, +/*h(5655)=718 */ {5655, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_718_l1}, +/*h(7862)=719 */ {7862, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_719_l1}, +/*h(720)=720 */ {720, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_720_l1}, +/*h(3914)=721 */ {3914, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_721_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7951)=723 */ {7951, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_723_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3626)=725 */ {3626, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_725_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6066)=727 */ {6066, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5922)=730 */ {5922, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_730_l1}, +/*h(1974)=731 */ {1974, xed3_phash_find_mapevex_map5_opcode0x7b_vv2_731_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 732ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[26] = { +/*h(601)=0 EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {601, 7211}, +/*h(538)=1 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 7202}, +/*h(603)=2 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 7210}, +/*h(344)=3 EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {344, 7208}, +/*h(281)=4 EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {281, 7201}, +/*h(346)=5 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7207}, +/*h(283)=6 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {283, 7203}, +/*h(24)=7 EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {24, 7199}, +/*h(89)=8 EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {89, 7206}, +/*h(26)=9 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 7198}, +/*h(91)=10 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 7210}, +/*h(859)=11 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 7210}, +/*h(600)=12 EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {600, 7211}, +/*h(537)=13 EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {537, 7204}, +/*h(602)=14 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7209}, +/*h(539)=15 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {539, 7203}, +/*h(280)=16 EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {280, 7201}, +/*h(345)=17 EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {345, 7208}, +/*h(282)=18 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 7200}, +/*h(347)=19 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 7210}, +/*h(88)=20 EVV 0x7C V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {88, 7206}, +/*h(25)=21 EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {25, 7199}, +/*h(90)=22 EVV 0x7C V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7205}, +/*h(27)=23 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {27, 7203}, +/*h(795)=24 EVV 0x7C VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {795, 7203}, +/*h(536)=25 EVV 0x7C VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {536, 7204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((14*key % 277) % 26); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[59] = { +/*h(472)=0 EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {472, 7263}, +/*h(728)=1 EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {728, 7266}, +/*h(217)=2 EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {217, 7261}, +/*h(473)=3 EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {473, 7263}, +/*h(729)=4 EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {729, 7266}, +/*h(218)=5 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 7260}, +/*h(474)=6 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 7262}, +/*h(730)=7 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 7264}, +/*h(219)=8 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {219, 7265}, +/*h(475)=9 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {475, 7265}, +/*h(731)=10 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {731, 7265}, +/*h(987)=11 EVV 0x7D VF3 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {987, 7265}, +/*empty slot1 */ {0,0}, +/*h(24)=13 EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {24, 7104}, +/*h(280)=14 EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {280, 7106}, +/*h(536)=15 EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {536, 7109}, +/*h(25)=16 EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {25, 7104}, +/*h(281)=17 EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {281, 7106}, +/*h(537)=18 EVV 0x7D VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {537, 7109}, +/*h(26)=19 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 7103}, +/*h(282)=20 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 7105}, +/*h(538)=21 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 7107}, +/*h(27)=22 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {27, 7108}, +/*h(283)=23 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {283, 7108}, +/*h(539)=24 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {539, 7108}, +/*h(795)=25 EVV 0x7D VNP MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {795, 7108}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=28 EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {88, 7111}, +/*h(344)=29 EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {344, 7113}, +/*h(600)=30 EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {600, 7116}, +/*h(89)=31 EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {89, 7111}, +/*h(345)=32 EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {345, 7113}, +/*h(601)=33 EVV 0x7D V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {601, 7116}, +/*h(90)=34 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7110}, +/*h(346)=35 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7112}, +/*h(602)=36 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7114}, +/*h(91)=37 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {91, 7115}, +/*h(347)=38 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {347, 7115}, +/*h(603)=39 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {603, 7115}, +/*h(859)=40 EVV 0x7D V66 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {859, 7115}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=43 EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {152, 7254}, +/*h(408)=44 EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {408, 7256}, +/*h(664)=45 EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {664, 7259}, +/*h(153)=46 EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {153, 7254}, +/*h(409)=47 EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {409, 7256}, +/*h(665)=48 EVV 0x7D VF2 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {665, 7259}, +/*h(154)=49 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {154, 7253}, +/*h(410)=50 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {410, 7255}, +/*h(666)=51 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {666, 7257}, +/*h(155)=52 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {155, 7258}, +/*h(411)=53 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {411, 7258}, +/*h(667)=54 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {667, 7258}, +/*h(923)=55 EVV 0x7D VF2 MAP5 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {923, 7258}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=58 EVV 0x7D VF3 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {216, 7261} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 59); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map5_opcode0x7e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(94)=0 EVV 0x7E V66 MAP5 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0*/ {94, 7533}, +/*h(90)=1 EVV 0x7E V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR ZEROING=0 MASK=0 ESIZE_16_BITS() NELEM_GPR_WRITER_STORE()*/ {90, 7534} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x13_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[218] = { +/*h(0)=0 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {0, 7148}, +/*h(539)=1 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {539, 7147}, +/*empty slot1 */ {0,0}, +/*h(787)=3 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {787, 7147}, +/*h(88)=4 EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {88, 7076}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(89)=9 EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {89, 7076}, +/*h(2)=10 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {2, 7146}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=14 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7075}, +/*h(3)=15 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {3, 7147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=19 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 7080}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(48)=22 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {48, 7148}, +/*empty slot1 */ {0,0}, +/*h(296)=24 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {296, 7148}, +/*empty slot1 */ {0,0}, +/*h(544)=26 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {544, 7148}, +/*empty slot1 */ {0,0}, +/*h(792)=28 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {792, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(50)=32 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {50, 7146}, +/*empty slot1 */ {0,0}, +/*h(298)=34 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {298, 7146}, +/*empty slot1 */ {0,0}, +/*h(546)=36 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {546, 7146}, +/*h(51)=37 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {51, 7147}, +/*h(794)=38 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {794, 7146}, +/*h(299)=39 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {299, 7147}, +/*h(8)=40 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7148}, +/*h(547)=41 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {547, 7147}, +/*h(256)=42 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {256, 7148}, +/*h(795)=43 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {795, 7147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=46 EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {344, 7078}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(10)=50 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7146}, +/*h(345)=51 EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {345, 7078}, +/*h(258)=52 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {258, 7146}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=55 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {11, 7147}, +/*h(346)=56 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7077}, +/*h(259)=57 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {259, 7147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(347)=61 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 7080}, +/*h(56)=62 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {56, 7148}, +/*empty slot1 */ {0,0}, +/*h(304)=64 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {304, 7148}, +/*empty slot1 */ {0,0}, +/*h(552)=66 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {552, 7148}, +/*empty slot1 */ {0,0}, +/*h(800)=68 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {800, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=72 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {58, 7146}, +/*empty slot1 */ {0,0}, +/*h(306)=74 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {306, 7146}, +/*empty slot1 */ {0,0}, +/*h(554)=76 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {554, 7146}, +/*h(59)=77 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {59, 7147}, +/*h(802)=78 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {802, 7146}, +/*h(307)=79 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {307, 7147}, +/*h(16)=80 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {16, 7148}, +/*h(555)=81 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {555, 7147}, +/*h(264)=82 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {264, 7148}, +/*h(803)=83 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {803, 7147}, +/*h(512)=84 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {512, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=88 EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {600, 7081}, +/*empty slot1 */ {0,0}, +/*h(18)=90 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {18, 7146}, +/*empty slot1 */ {0,0}, +/*h(266)=92 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {266, 7146}, +/*h(601)=93 EVV 0x13 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_HALF()*/ {601, 7081}, +/*h(514)=94 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {514, 7146}, +/*h(19)=95 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {19, 7147}, +/*empty slot1 */ {0,0}, +/*h(267)=97 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {267, 7147}, +/*h(602)=98 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7079}, +/*h(515)=99 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {515, 7147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=103 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 7080}, +/*h(312)=104 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {312, 7148}, +/*empty slot1 */ {0,0}, +/*h(560)=106 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {560, 7148}, +/*empty slot1 */ {0,0}, +/*h(808)=108 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {808, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(314)=114 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {314, 7146}, +/*empty slot1 */ {0,0}, +/*h(562)=116 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {562, 7146}, +/*empty slot1 */ {0,0}, +/*h(810)=118 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {810, 7146}, +/*h(315)=119 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {315, 7147}, +/*h(24)=120 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {24, 7148}, +/*h(563)=121 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {563, 7147}, +/*h(272)=122 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {272, 7148}, +/*h(811)=123 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {811, 7147}, +/*h(520)=124 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {520, 7148}, +/*empty slot1 */ {0,0}, +/*h(768)=126 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {768, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=130 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7146}, +/*empty slot1 */ {0,0}, +/*h(274)=132 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {274, 7146}, +/*empty slot1 */ {0,0}, +/*h(522)=134 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {522, 7146}, +/*h(27)=135 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {27, 7147}, +/*h(770)=136 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {770, 7146}, +/*h(275)=137 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {275, 7147}, +/*empty slot1 */ {0,0}, +/*h(523)=139 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {523, 7147}, +/*empty slot1 */ {0,0}, +/*h(771)=141 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {771, 7147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(859)=145 EVV 0x13 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 7080}, +/*h(568)=146 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {568, 7148}, +/*empty slot1 */ {0,0}, +/*h(816)=148 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {816, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(570)=156 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {570, 7146}, +/*empty slot1 */ {0,0}, +/*h(818)=158 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {818, 7146}, +/*empty slot1 */ {0,0}, +/*h(32)=160 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {32, 7148}, +/*h(571)=161 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {571, 7147}, +/*h(280)=162 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {280, 7148}, +/*h(819)=163 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {819, 7147}, +/*h(528)=164 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {528, 7148}, +/*empty slot1 */ {0,0}, +/*h(776)=166 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {776, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(34)=170 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {34, 7146}, +/*empty slot1 */ {0,0}, +/*h(282)=172 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {282, 7146}, +/*empty slot1 */ {0,0}, +/*h(530)=174 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {530, 7146}, +/*h(35)=175 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {35, 7147}, +/*h(778)=176 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {778, 7146}, +/*h(283)=177 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {283, 7147}, +/*empty slot1 */ {0,0}, +/*h(531)=179 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {531, 7147}, +/*empty slot1 */ {0,0}, +/*h(779)=181 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {779, 7147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(824)=188 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {824, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(826)=198 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {826, 7146}, +/*empty slot1 */ {0,0}, +/*h(40)=200 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {40, 7148}, +/*empty slot1 */ {0,0}, +/*h(288)=202 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {288, 7148}, +/*h(827)=203 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {827, 7147}, +/*h(536)=204 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {536, 7148}, +/*empty slot1 */ {0,0}, +/*h(784)=206 EVV 0x13 VNP MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {784, 7148}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(42)=210 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {42, 7146}, +/*empty slot1 */ {0,0}, +/*h(290)=212 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {290, 7146}, +/*empty slot1 */ {0,0}, +/*h(538)=214 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {538, 7146}, +/*h(43)=215 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {43, 7147}, +/*h(786)=216 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {786, 7146}, +/*h(291)=217 EVV 0x13 VNP MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {291, 7147} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 619) % 218); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x2c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7585}, +/*h(11)=1 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7586}, +/*h(43)=2 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7586}, +/*h(75)=3 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7586}, +/*h(107)=4 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7586}, +/*h(8)=5 EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7582}, +/*h(40)=6 EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7584}, +/*h(72)=7 EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7587}, +/*h(9)=8 EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7582}, +/*h(41)=9 EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7584}, +/*h(73)=10 EVV 0x2C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7587}, +/*h(10)=11 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7581}, +/*h(42)=12 EVV 0x2C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7583} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x2d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7588}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0x2D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7589}, +/*h(8)=4 EVV 0x2D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7590} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x42_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(91)=0 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 7492}, +/*h(347)=1 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 7492}, +/*h(603)=2 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 7492}, +/*h(859)=3 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 7492}, +/*h(88)=4 EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {88, 7488}, +/*h(344)=5 EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {344, 7490}, +/*h(600)=6 EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {600, 7493}, +/*h(89)=7 EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {89, 7488}, +/*h(345)=8 EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {345, 7490}, +/*h(601)=9 EVV 0x42 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {601, 7493}, +/*h(90)=10 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7487}, +/*h(346)=11 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7489}, +/*h(602)=12 EVV 0x42 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7491} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x43_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7494}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0x43 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {11, 7495}, +/*h(8)=4 EVV 0x43 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7496} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(89)=0 EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {89, 7546}, +/*h(602)=1 EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7549}, +/*empty slot1 */ {0,0}, +/*h(345)=3 EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {345, 7548}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=6 EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {88, 7546}, +/*h(601)=7 EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {601, 7550}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=10 EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {344, 7548}, +/*h(90)=11 EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7545}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=14 EVV 0x4C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {600, 7550}, +/*h(346)=15 EVV 0x4C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7547}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 EVV 0x4D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7551}, +/*h(8)=1 EVV 0x4D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7552} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(89)=0 EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {89, 7574}, +/*h(602)=1 EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 7577}, +/*empty slot1 */ {0,0}, +/*h(345)=3 EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {345, 7576}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=6 EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {88, 7574}, +/*h(601)=7 EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {601, 7578}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=10 EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {344, 7576}, +/*h(90)=11 EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 7573}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=14 EVV 0x4E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_16_BITS() NELEM_FULL()*/ {600, 7578}, +/*h(346)=15 EVV 0x4E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 7575}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x4f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 EVV 0x4F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7579}, +/*h(8)=1 EVV 0x4F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7580} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x56_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[47] = { +/*empty slot1 */ {0,0}, +/*h(16)=1 EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {16, 7278}, +/*empty slot1 */ {0,0}, +/*h(48)=3 EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {48, 7280}, +/*h(17)=4 EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {17, 7278}, +/*h(80)=5 EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {80, 7283}, +/*h(49)=6 EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {49, 7280}, +/*h(18)=7 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {18, 7277}, +/*h(81)=8 EVV 0x56 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {81, 7283}, +/*h(50)=9 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {50, 7279}, +/*h(19)=10 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {19, 7282}, +/*h(82)=11 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {82, 7281}, +/*h(51)=12 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {51, 7282}, +/*empty slot1 */ {0,0}, +/*h(83)=14 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {83, 7282}, +/*empty slot1 */ {0,0}, +/*h(115)=16 EVV 0x56 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {115, 7282}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=25 EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {24, 7328}, +/*empty slot1 */ {0,0}, +/*h(56)=27 EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {56, 7330}, +/*h(25)=28 EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {25, 7328}, +/*h(88)=29 EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {88, 7333}, +/*h(57)=30 EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {57, 7330}, +/*h(26)=31 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {26, 7327}, +/*h(89)=32 EVV 0x56 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {89, 7333}, +/*h(58)=33 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {58, 7329}, +/*h(27)=34 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {27, 7332}, +/*h(90)=35 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {90, 7331}, +/*h(59)=36 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {59, 7332}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {91, 7332}, +/*empty slot1 */ {0,0}, +/*h(123)=40 EVV 0x56 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {123, 7332}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 47); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x57_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(26)=0 EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7334}, +/*h(18)=1 EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {18, 7284}, +/*h(27)=2 EVV 0x57 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7335}, +/*h(19)=3 EVV 0x57 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {19, 7285}, +/*h(24)=4 EVV 0x57 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 7336}, +/*h(16)=5 EVV 0x57 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {16, 7286} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = ((8*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x96_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7341}, +/*h(11)=1 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7342}, +/*h(43)=2 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7342}, +/*h(75)=3 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7342}, +/*h(107)=4 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7342}, +/*h(8)=5 EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7338}, +/*h(40)=6 EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7340}, +/*h(72)=7 EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7343}, +/*h(9)=8 EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7338}, +/*h(41)=9 EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7340}, +/*h(73)=10 EVV 0x96 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7343}, +/*h(10)=11 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7337}, +/*h(42)=12 EVV 0x96 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7339} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x97_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7392}, +/*h(11)=1 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7393}, +/*h(43)=2 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7393}, +/*h(75)=3 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7393}, +/*h(107)=4 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7393}, +/*h(8)=5 EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7389}, +/*h(40)=6 EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7391}, +/*h(72)=7 EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7394}, +/*h(9)=8 EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7389}, +/*h(41)=9 EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7391}, +/*h(73)=10 EVV 0x97 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7394}, +/*h(10)=11 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7388}, +/*h(42)=12 EVV 0x97 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x98_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7301}, +/*h(11)=1 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7302}, +/*h(43)=2 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7302}, +/*h(75)=3 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7302}, +/*h(107)=4 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7302}, +/*h(8)=5 EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7298}, +/*h(40)=6 EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7300}, +/*h(72)=7 EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7303}, +/*h(9)=8 EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7298}, +/*h(41)=9 EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7300}, +/*h(73)=10 EVV 0x98 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7303}, +/*h(10)=11 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7297}, +/*h(42)=12 EVV 0x98 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7299} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x99_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7304}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0x99 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7305}, +/*h(8)=4 EVV 0x99 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7306} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7362}, +/*h(11)=1 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7363}, +/*h(43)=2 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7363}, +/*h(75)=3 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7363}, +/*h(107)=4 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7363}, +/*h(8)=5 EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7359}, +/*h(40)=6 EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7361}, +/*h(72)=7 EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7364}, +/*h(9)=8 EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7359}, +/*h(41)=9 EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7361}, +/*h(73)=10 EVV 0x9A V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7364}, +/*h(10)=11 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7358}, +/*h(42)=12 EVV 0x9A V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7365}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0x9B V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7366}, +/*h(8)=4 EVV 0x9B V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7367} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7423}, +/*h(11)=1 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7424}, +/*h(43)=2 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7424}, +/*h(75)=3 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7424}, +/*h(107)=4 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7424}, +/*h(8)=5 EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7420}, +/*h(40)=6 EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7422}, +/*h(72)=7 EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7425}, +/*h(9)=8 EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7420}, +/*h(41)=9 EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7422}, +/*h(73)=10 EVV 0x9C V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7425}, +/*h(10)=11 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7419}, +/*h(42)=12 EVV 0x9C V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7421} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7426}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0x9D V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7427}, +/*h(8)=4 EVV 0x9D V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7428} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7453}, +/*h(11)=1 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7454}, +/*h(43)=2 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7454}, +/*h(75)=3 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7454}, +/*h(107)=4 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7454}, +/*h(8)=5 EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7450}, +/*h(40)=6 EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7452}, +/*h(72)=7 EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7455}, +/*h(9)=8 EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7450}, +/*h(41)=9 EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7452}, +/*h(73)=10 EVV 0x9E V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7455}, +/*h(10)=11 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7449}, +/*h(42)=12 EVV 0x9E V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7451} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0x9f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7456}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0x9F V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7457}, +/*h(8)=4 EVV 0x9F V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7458} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7348}, +/*h(11)=1 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7349}, +/*h(43)=2 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7349}, +/*h(75)=3 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7349}, +/*h(107)=4 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7349}, +/*h(8)=5 EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7345}, +/*h(40)=6 EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7347}, +/*h(72)=7 EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7350}, +/*h(9)=8 EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7345}, +/*h(41)=9 EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7347}, +/*h(73)=10 EVV 0xA6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7350}, +/*h(10)=11 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7344}, +/*h(42)=12 EVV 0xA6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7346} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7399}, +/*h(11)=1 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7400}, +/*h(43)=2 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7400}, +/*h(75)=3 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7400}, +/*h(107)=4 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7400}, +/*h(8)=5 EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7396}, +/*h(40)=6 EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7398}, +/*h(72)=7 EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7401}, +/*h(9)=8 EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7396}, +/*h(41)=9 EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7398}, +/*h(73)=10 EVV 0xA7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7401}, +/*h(10)=11 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7395}, +/*h(42)=12 EVV 0xA7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7397} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7311}, +/*h(11)=1 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7312}, +/*h(43)=2 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7312}, +/*h(75)=3 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7312}, +/*h(107)=4 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7312}, +/*h(8)=5 EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7308}, +/*h(40)=6 EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7310}, +/*h(72)=7 EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7313}, +/*h(9)=8 EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7308}, +/*h(41)=9 EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7310}, +/*h(73)=10 EVV 0xA8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7313}, +/*h(10)=11 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7307}, +/*h(42)=12 EVV 0xA8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xa9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7314}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xA9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7315}, +/*h(8)=4 EVV 0xA9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7316} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xaa_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7372}, +/*h(11)=1 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7373}, +/*h(43)=2 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7373}, +/*h(75)=3 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7373}, +/*h(107)=4 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7373}, +/*h(8)=5 EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7369}, +/*h(40)=6 EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7371}, +/*h(72)=7 EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7374}, +/*h(9)=8 EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7369}, +/*h(41)=9 EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7371}, +/*h(73)=10 EVV 0xAA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7374}, +/*h(10)=11 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7368}, +/*h(42)=12 EVV 0xAA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7370} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xab_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7375}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xAB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7376}, +/*h(8)=4 EVV 0xAB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7377} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xac_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7433}, +/*h(11)=1 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7434}, +/*h(43)=2 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7434}, +/*h(75)=3 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7434}, +/*h(107)=4 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7434}, +/*h(8)=5 EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7430}, +/*h(40)=6 EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7432}, +/*h(72)=7 EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7435}, +/*h(9)=8 EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7430}, +/*h(41)=9 EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7432}, +/*h(73)=10 EVV 0xAC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7435}, +/*h(10)=11 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7429}, +/*h(42)=12 EVV 0xAC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7431} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xad_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7436}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xAD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7437}, +/*h(8)=4 EVV 0xAD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7438} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xae_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7463}, +/*h(11)=1 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7464}, +/*h(43)=2 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7464}, +/*h(75)=3 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7464}, +/*h(107)=4 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7464}, +/*h(8)=5 EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7460}, +/*h(40)=6 EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7462}, +/*h(72)=7 EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7465}, +/*h(9)=8 EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7460}, +/*h(41)=9 EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7462}, +/*h(73)=10 EVV 0xAE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7465}, +/*h(10)=11 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7459}, +/*h(42)=12 EVV 0xAE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7461} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xaf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7466}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xAF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7467}, +/*h(8)=4 EVV 0xAF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7468} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7355}, +/*h(11)=1 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7356}, +/*h(43)=2 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7356}, +/*h(75)=3 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7356}, +/*h(107)=4 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7356}, +/*h(8)=5 EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7352}, +/*h(40)=6 EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7354}, +/*h(72)=7 EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7357}, +/*h(9)=8 EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7352}, +/*h(41)=9 EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7354}, +/*h(73)=10 EVV 0xB6 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7357}, +/*h(10)=11 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7351}, +/*h(42)=12 EVV 0xB6 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7353} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7406}, +/*h(11)=1 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7407}, +/*h(43)=2 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7407}, +/*h(75)=3 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7407}, +/*h(107)=4 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7407}, +/*h(8)=5 EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7403}, +/*h(40)=6 EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7405}, +/*h(72)=7 EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7408}, +/*h(9)=8 EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7403}, +/*h(41)=9 EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7405}, +/*h(73)=10 EVV 0xB7 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7408}, +/*h(10)=11 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7402}, +/*h(42)=12 EVV 0xB7 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7404} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7321}, +/*h(11)=1 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7322}, +/*h(43)=2 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7322}, +/*h(75)=3 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7322}, +/*h(107)=4 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7322}, +/*h(8)=5 EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7318}, +/*h(40)=6 EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7320}, +/*h(72)=7 EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7323}, +/*h(9)=8 EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7318}, +/*h(41)=9 EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7320}, +/*h(73)=10 EVV 0xB8 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7323}, +/*h(10)=11 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7317}, +/*h(42)=12 EVV 0xB8 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7319} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xb9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7324}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xB9 V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7325}, +/*h(8)=4 EVV 0xB9 V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7326} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xba_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7382}, +/*h(11)=1 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7383}, +/*h(43)=2 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7383}, +/*h(75)=3 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7383}, +/*h(107)=4 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7383}, +/*h(8)=5 EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7379}, +/*h(40)=6 EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7381}, +/*h(72)=7 EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7384}, +/*h(9)=8 EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7379}, +/*h(41)=9 EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7381}, +/*h(73)=10 EVV 0xBA V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7384}, +/*h(10)=11 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7378}, +/*h(42)=12 EVV 0xBA V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7385}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xBB V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7386}, +/*h(8)=4 EVV 0xBB V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7387} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7443}, +/*h(11)=1 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7444}, +/*h(43)=2 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7444}, +/*h(75)=3 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7444}, +/*h(107)=4 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7444}, +/*h(8)=5 EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7440}, +/*h(40)=6 EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7442}, +/*h(72)=7 EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7445}, +/*h(9)=8 EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7440}, +/*h(41)=9 EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7442}, +/*h(73)=10 EVV 0xBC V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7445}, +/*h(10)=11 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7439}, +/*h(42)=12 EVV 0xBC V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7441} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7446}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xBD V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7447}, +/*h(8)=4 EVV 0xBD V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7448} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbe_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[13] = { +/*h(74)=0 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 7473}, +/*h(11)=1 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {11, 7474}, +/*h(43)=2 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {43, 7474}, +/*h(75)=3 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {75, 7474}, +/*h(107)=4 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {107, 7474}, +/*h(8)=5 EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {8, 7470}, +/*h(40)=6 EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {40, 7472}, +/*h(72)=7 EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {72, 7475}, +/*h(9)=8 EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_16_BITS() NELEM_FULL()*/ {9, 7470}, +/*h(41)=9 EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_16_BITS() NELEM_FULL()*/ {41, 7472}, +/*h(73)=10 EVV 0xBE V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_16_BITS() NELEM_FULL()*/ {73, 7475}, +/*h(10)=11 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 7469}, +/*h(42)=12 EVV 0xBE V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 7471} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((3*key % 19) % 13); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xbf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(10)=0 EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {10, 7476}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(11)=3 EVV 0xBF V66 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {11, 7477}, +/*h(8)=4 EVV 0xBF V66 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_16_BITS() NELEM_SCALAR()*/ {8, 7478} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xd6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[47] = { +/*empty slot1 */ {0,0}, +/*h(16)=1 EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {16, 7288}, +/*empty slot1 */ {0,0}, +/*h(48)=3 EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {48, 7290}, +/*h(17)=4 EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {17, 7288}, +/*h(80)=5 EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {80, 7293}, +/*h(49)=6 EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {49, 7290}, +/*h(18)=7 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {18, 7287}, +/*h(81)=8 EVV 0xD6 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {81, 7293}, +/*h(50)=9 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {50, 7289}, +/*h(19)=10 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {19, 7292}, +/*h(82)=11 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {82, 7291}, +/*h(51)=12 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {51, 7292}, +/*empty slot1 */ {0,0}, +/*h(83)=14 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {83, 7292}, +/*empty slot1 */ {0,0}, +/*h(115)=16 EVV 0xD6 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {115, 7292}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=25 EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {24, 7410}, +/*empty slot1 */ {0,0}, +/*h(56)=27 EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {56, 7412}, +/*h(25)=28 EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {25, 7410}, +/*h(88)=29 EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {88, 7415}, +/*h(57)=30 EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {57, 7412}, +/*h(26)=31 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {26, 7409}, +/*h(89)=32 EVV 0xD6 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {89, 7415}, +/*h(58)=33 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {58, 7411}, +/*h(27)=34 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {27, 7414}, +/*h(90)=35 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {90, 7413}, +/*h(59)=36 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {59, 7414}, +/*empty slot1 */ {0,0}, +/*h(91)=38 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {91, 7414}, +/*empty slot1 */ {0,0}, +/*h(123)=40 EVV 0xD6 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {123, 7414}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (3*key % 47); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map6_opcode0xd7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(26)=0 EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {26, 7416}, +/*h(18)=1 EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] FIX_ROUND_LEN128() W0*/ {18, 7294}, +/*h(27)=2 EVV 0xD7 VF3 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 7417}, +/*h(19)=3 EVV 0xD7 VF2 MAP6 MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {19, 7295}, +/*h(24)=4 EVV 0xD7 VF3 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 7418}, +/*h(16)=5 EVV 0xD7 VF2 MAP6 MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() FIX_ROUND_LEN128() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {16, 7296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(d); +hidx = ((8*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(156)=0 EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR()*/ {156, 5007}, +/*h(910)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {910, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(234)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {234, 5025}, +/*h(412)=1 EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR()*/ {412, 5007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(668)=0 EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR()*/ {5007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26)=0 EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 5043}, +/*h(458)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {458, 5025}, +/*h(924)=2 EVV 0x10 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ESIZE_64_BITS() NELEM_SCALAR()*/ {924, 5007} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(134)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {134, 5009}, +/*h(422)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {422, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(390)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {390, 5009}, +/*h(678)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {678, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(934)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {934, 5009}, +/*h(646)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {646, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(902)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(166)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {150, 5009}, +/*h(472)=1 EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR()*/ {472, 5023} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(406)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 406; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(950)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {950, 5009}, +/*h(662)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {662, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(918)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 918; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(182)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(438)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(694)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(430)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {430, 5009}, +/*h(142)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {142, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(398)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(654)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(174)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {158, 5009}, +/*h(446)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {446, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(92)=0 EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {92, 5032}, +/*h(702)=1 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {702, 5009}, +/*h(414)=2 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {414, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(958)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {958, 5009}, +/*h(348)=1 EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {348, 5036}, +/*h(670)=2 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {670, 5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(926)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(190)=0 EVV 0x10 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5009} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR()*/ {216, 5023}, +/*h(970)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {970, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(728)=0 EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR()*/ {5023} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(984)=0 EVV 0x10 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ESIZE_32_BITS() NELEM_SCALAR()*/ {5023} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(194)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 194; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {450, 5025}, +/*h(738)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {738, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(994)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {994, 5025}, +/*h(706)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {706, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(226)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 226; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(482)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(466)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1010, 5025}, +/*h(722)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {722, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(978)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(498)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(754)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(490)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {490, 5025}, +/*h(202)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {202, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(714)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {714, 5025}, +/*h(282)=1 EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 5047} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(746)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {746, 5025}, +/*h(280)=1 EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {280, 5048} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1002)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1002, 5025}, +/*h(536)=1 EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {536, 5040} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(218)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(474)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {474, 5025}, +/*h(762)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {762, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(730)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {730, 5025}, +/*h(1018)=1 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1018, 5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(250)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {250, 5025}, +/*h(538)=1 EVV 0x10 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 5039} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(506)=0 EVV 0x10 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5025} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(606)=0 EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {5027} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(604)=0 EVV 0x10 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {5028} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(94)=0 EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {5031} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 94; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(350)=0 EVV 0x10 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5035} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24)=0 EVV 0x10 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {5044} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 24; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x10_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[84] = { +/*h(466)=0 */ {466, xed3_phash_find_mapevex_map1_opcode0x10_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(678)=2 */ {678, xed3_phash_find_mapevex_map1_opcode0x10_vv2_2_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(280)=4 */ {280, xed3_phash_find_mapevex_map1_opcode0x10_vv2_4_l1}, +/*h(26)=5 */ {26, xed3_phash_find_mapevex_map1_opcode0x10_vv2_5_l1}, +/*h(348)=6 */ {348, xed3_phash_find_mapevex_map1_opcode0x10_vv2_6_l1}, +/*h(94)=7 */ {94, xed3_phash_find_mapevex_map1_opcode0x10_vv2_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=9 */ {738, xed3_phash_find_mapevex_map1_opcode0x10_vv2_9_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(950)=11 */ {950, xed3_phash_find_mapevex_map1_opcode0x10_vv2_11_l1}, +/*h(984)=12 */ {984, xed3_phash_find_mapevex_map1_opcode0x10_vv2_12_l1}, +/*h(1018)=13 */ {1018, xed3_phash_find_mapevex_map1_opcode0x10_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(942)=15 */ {942, xed3_phash_find_mapevex_map1_opcode0x10_vv2_15_l1}, +/*h(654)=16 */ {654, xed3_phash_find_mapevex_map1_opcode0x10_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=18 */ {1010, xed3_phash_find_mapevex_map1_opcode0x10_vv2_18_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(934)=20 */ {934, xed3_phash_find_mapevex_map1_opcode0x10_vv2_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(536)=22 */ {536, xed3_phash_find_mapevex_map1_opcode0x10_vv2_22_l1}, +/*h(282)=23 */ {282, xed3_phash_find_mapevex_map1_opcode0x10_vv2_23_l1}, +/*h(604)=24 */ {604, xed3_phash_find_mapevex_map1_opcode0x10_vv2_24_l1}, +/*h(926)=25 */ {926, xed3_phash_find_mapevex_map1_opcode0x10_vv2_25_l1}, +/*h(350)=26 */ {350, xed3_phash_find_mapevex_map1_opcode0x10_vv2_26_l1}, +/*h(994)=27 */ {994, xed3_phash_find_mapevex_map1_opcode0x10_vv2_27_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(918)=29 */ {918, xed3_phash_find_mapevex_map1_opcode0x10_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(986)=32 */ {986, xed3_phash_find_mapevex_map1_opcode0x10_vv2_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(910)=34 */ {910, xed3_phash_find_mapevex_map1_opcode0x10_vv2_34_l1}, +/*h(190)=35 */ {190, xed3_phash_find_mapevex_map1_opcode0x10_vv2_35_l1}, +/*h(978)=36 */ {978, xed3_phash_find_mapevex_map1_opcode0x10_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(902)=39 */ {902, xed3_phash_find_mapevex_map1_opcode0x10_vv2_39_l1}, +/*h(182)=40 */ {182, xed3_phash_find_mapevex_map1_opcode0x10_vv2_40_l1}, +/*h(970)=41 */ {970, xed3_phash_find_mapevex_map1_opcode0x10_vv2_41_l1}, +/*h(538)=42 */ {538, xed3_phash_find_mapevex_map1_opcode0x10_vv2_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(606)=44 */ {606, xed3_phash_find_mapevex_map1_opcode0x10_vv2_44_l1}, +/*h(174)=45 */ {174, xed3_phash_find_mapevex_map1_opcode0x10_vv2_45_l1}, +/*h(962)=46 */ {962, xed3_phash_find_mapevex_map1_opcode0x10_vv2_46_l1}, +/*h(242)=47 */ {242, xed3_phash_find_mapevex_map1_opcode0x10_vv2_47_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(166)=49 */ {166, xed3_phash_find_mapevex_map1_opcode0x10_vv2_49_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=52 */ {234, xed3_phash_find_mapevex_map1_opcode0x10_vv2_52_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(446)=54 */ {446, xed3_phash_find_mapevex_map1_opcode0x10_vv2_54_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(226)=56 */ {226, xed3_phash_find_mapevex_map1_opcode0x10_vv2_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(438)=58 */ {438, xed3_phash_find_mapevex_map1_opcode0x10_vv2_58_l1}, +/*h(472)=59 */ {472, xed3_phash_find_mapevex_map1_opcode0x10_vv2_59_l1}, +/*h(506)=60 */ {506, xed3_phash_find_mapevex_map1_opcode0x10_vv2_60_l1}, +/*h(218)=61 */ {218, xed3_phash_find_mapevex_map1_opcode0x10_vv2_61_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(430)=63 */ {430, xed3_phash_find_mapevex_map1_opcode0x10_vv2_63_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(498)=65 */ {498, xed3_phash_find_mapevex_map1_opcode0x10_vv2_65_l1}, +/*h(210)=66 */ {210, xed3_phash_find_mapevex_map1_opcode0x10_vv2_66_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(422)=68 */ {422, xed3_phash_find_mapevex_map1_opcode0x10_vv2_68_l1}, +/*h(24)=69 */ {24, xed3_phash_find_mapevex_map1_opcode0x10_vv2_69_l1}, +/*h(490)=70 */ {490, xed3_phash_find_mapevex_map1_opcode0x10_vv2_70_l1}, +/*h(668)=71 */ {668, xed3_phash_find_mapevex_map1_opcode0x10_vv2_71_l1}, +/*h(92)=72 */ {92, xed3_phash_find_mapevex_map1_opcode0x10_vv2_72_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(482)=74 */ {482, xed3_phash_find_mapevex_map1_opcode0x10_vv2_74_l1}, +/*h(194)=75 */ {194, xed3_phash_find_mapevex_map1_opcode0x10_vv2_75_l1}, +/*h(694)=76 */ {694, xed3_phash_find_mapevex_map1_opcode0x10_vv2_76_l1}, +/*h(406)=77 */ {406, xed3_phash_find_mapevex_map1_opcode0x10_vv2_77_l1}, +/*h(728)=78 */ {728, xed3_phash_find_mapevex_map1_opcode0x10_vv2_78_l1}, +/*h(762)=79 */ {762, xed3_phash_find_mapevex_map1_opcode0x10_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=81 */ {686, xed3_phash_find_mapevex_map1_opcode0x10_vv2_81_l1}, +/*h(398)=82 */ {398, xed3_phash_find_mapevex_map1_opcode0x10_vv2_82_l1}, +/*h(754)=83 */ {754, xed3_phash_find_mapevex_map1_opcode0x10_vv2_83_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 84ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(156)=0 EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {156, 5008}, +/*h(1986)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1986, 5026}, +/*h(910)=2 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {910, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_97_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(412)=0 EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {5008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1422)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1422, 5010}, +/*h(668)=1 EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {668, 5008} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(924)=0 EVV 0x11 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {924, 5008}, +/*h(1678)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1678, 5010}, +/*h(458)=2 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {458, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(134)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {134, 5010}, +/*h(1498)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1498, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1158)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1158; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(390)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(194)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {194, 5026}, +/*h(1414)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1414, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2010)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {2010, 5026}, +/*h(646)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {646, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(450)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {450, 5026}, +/*h(1958)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1958, 5010}, +/*h(1670)=2 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1670, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(902)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(706)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {706, 5026}, +/*h(1926)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1926, 5010}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1530)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1530, 5026}, +/*h(166)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {166, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1190)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(422)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {422, 5010}, +/*h(1786)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1786, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1446)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1446, 5010}, +/*h(226)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {226, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(678)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {678, 5010}, +/*h(1754)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1754, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(482)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {482, 5026}, +/*h(1702)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1702, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(934)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {150, 5010}, +/*h(1514)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1514, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1174)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(406)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {406, 5010}, +/*h(694)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {694, 5010}, +/*h(1770)=2 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1770, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(210)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {210, 5026}, +/*h(1430)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1430, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(662)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {662, 5010}, +/*h(2026)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {2026, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1686)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1686, 5010}, +/*h(466)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {466, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(918)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 918; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1942)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(182)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {182, 5010}, +/*h(1258)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1258, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1206)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1206; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(438)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 438; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1462)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(498)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {498, 5026}, +/*h(1718)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1718, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(950)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1974)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1974, 5010}, +/*h(754)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {754, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1218)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1218, 5026}, +/*h(142)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {142, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1166)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1166; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(398)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {398, 5010}, +/*h(1762)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1762, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(654)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {654, 5010}, +/*h(2018)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {2018, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(714)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {714, 5026}, +/*h(1934)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1934, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(174)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1198)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1198; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1506)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1506, 5026}, +/*h(430)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {430, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(234)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {234, 5026}, +/*h(1454)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1454, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1710)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1710, 5010}, +/*h(202)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {202, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(746)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {746, 5026}, +/*h(1966)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1966, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {158, 5010}, +/*h(1234)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1234, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1182)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(414)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {414, 5010}, +/*h(1778)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1778, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(218)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {218, 5026}, +/*h(1438)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1438, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2034)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {2034, 5026}, +/*h(670)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {670, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(474)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {474, 5026}, +/*h(1694)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1694, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(926)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {926, 5010}, +/*h(2002)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {2002, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1950)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1950, 5010}, +/*h(730)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {730, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(190)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1214)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1214, 5010}, +/*h(604)=1 EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {604, 5030} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(446)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {446, 5010}, +/*h(1522)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1522, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1470)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1470, 5010}, +/*h(250)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {250, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(702)=0 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {702, 5010}, +/*h(92)=1 EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {92, 5034} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(506)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {506, 5026}, +/*h(1726)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1726, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(348)=0 EVV 0x11 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {348, 5038}, +/*h(958)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {958, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {762, 5026}, +/*h(1982)=1 EVV 0x11 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {1982, 5010} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(216)=0 EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5024} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 216; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1226)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1226, 5026}, +/*h(472)=1 EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR()*/ {472, 5024} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(728)=0 EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5024} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 728; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(984)=0 EVV 0x11 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_SCALAR()*/ {984, 5024}, +/*h(1738)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1738, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1474)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1730)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1250)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(994)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1490)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1010, 5026}, +/*h(722)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {722, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1746)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(978)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(242)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1266)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1482)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(970)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1994)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24)=0 EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {24, 5046}, +/*h(490)=1 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {490, 5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1002)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1242)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(986)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1274)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1018)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2042)=0 EVV 0x11 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5026} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(606)=0 EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {5029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1630)=0 EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {5029} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1630; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(94)=0 EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {5033} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 94; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1118)=0 EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {5033} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(350)=0 EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1374)=0 EVV 0x11 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5037} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(538)=0 EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {5041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1562)=0 EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {5041} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(536)=0 EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {5042} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 536; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {5045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1050)=0 EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {5045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(282)=0 EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1306)=0 EVV 0x11 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5049} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(280)=0 EVV 0x11 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {5050} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x11_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[154] = { +/*h(466)=0 */ {466, xed3_phash_find_mapevex_map1_opcode0x11_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2042)=3 */ {2042, xed3_phash_find_mapevex_map1_opcode0x11_vv2_3_l1}, +/*h(1754)=4 */ {1754, xed3_phash_find_mapevex_map1_opcode0x11_vv2_4_l1}, +/*h(390)=5 */ {390, xed3_phash_find_mapevex_map1_opcode0x11_vv2_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(280)=7 */ {280, xed3_phash_find_mapevex_map1_opcode0x11_vv2_7_l1}, +/*h(746)=8 */ {746, xed3_phash_find_mapevex_map1_opcode0x11_vv2_8_l1}, +/*h(458)=9 */ {458, xed3_phash_find_mapevex_map1_opcode0x11_vv2_9_l1}, +/*h(26)=10 */ {26, xed3_phash_find_mapevex_map1_opcode0x11_vv2_10_l1}, +/*h(348)=11 */ {348, xed3_phash_find_mapevex_map1_opcode0x11_vv2_11_l1}, +/*h(2034)=12 */ {2034, xed3_phash_find_mapevex_map1_opcode0x11_vv2_12_l1}, +/*h(1746)=13 */ {1746, xed3_phash_find_mapevex_map1_opcode0x11_vv2_13_l1}, +/*h(94)=14 */ {94, xed3_phash_find_mapevex_map1_opcode0x11_vv2_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=16 */ {738, xed3_phash_find_mapevex_map1_opcode0x11_vv2_16_l1}, +/*h(450)=17 */ {450, xed3_phash_find_mapevex_map1_opcode0x11_vv2_17_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(950)=20 */ {950, xed3_phash_find_mapevex_map1_opcode0x11_vv2_20_l1}, +/*h(2026)=21 */ {2026, xed3_phash_find_mapevex_map1_opcode0x11_vv2_21_l1}, +/*h(1738)=22 */ {1738, xed3_phash_find_mapevex_map1_opcode0x11_vv2_22_l1}, +/*h(1306)=23 */ {1306, xed3_phash_find_mapevex_map1_opcode0x11_vv2_23_l1}, +/*h(1018)=24 */ {1018, xed3_phash_find_mapevex_map1_opcode0x11_vv2_24_l1}, +/*h(730)=25 */ {730, xed3_phash_find_mapevex_map1_opcode0x11_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1374)=27 */ {1374, xed3_phash_find_mapevex_map1_opcode0x11_vv2_27_l1}, +/*h(942)=28 */ {942, xed3_phash_find_mapevex_map1_opcode0x11_vv2_28_l1}, +/*h(2018)=29 */ {2018, xed3_phash_find_mapevex_map1_opcode0x11_vv2_29_l1}, +/*h(1730)=30 */ {1730, xed3_phash_find_mapevex_map1_opcode0x11_vv2_30_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=33 */ {1010, xed3_phash_find_mapevex_map1_opcode0x11_vv2_33_l1}, +/*h(1942)=34 */ {1942, xed3_phash_find_mapevex_map1_opcode0x11_vv2_34_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(934)=37 */ {934, xed3_phash_find_mapevex_map1_opcode0x11_vv2_37_l1}, +/*h(2010)=38 */ {2010, xed3_phash_find_mapevex_map1_opcode0x11_vv2_38_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(536)=40 */ {536, xed3_phash_find_mapevex_map1_opcode0x11_vv2_40_l1}, +/*h(1002)=41 */ {1002, xed3_phash_find_mapevex_map1_opcode0x11_vv2_41_l1}, +/*h(714)=42 */ {714, xed3_phash_find_mapevex_map1_opcode0x11_vv2_42_l1}, +/*h(282)=43 */ {282, xed3_phash_find_mapevex_map1_opcode0x11_vv2_43_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(604)=45 */ {604, xed3_phash_find_mapevex_map1_opcode0x11_vv2_45_l1}, +/*h(2002)=46 */ {2002, xed3_phash_find_mapevex_map1_opcode0x11_vv2_46_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(350)=48 */ {350, xed3_phash_find_mapevex_map1_opcode0x11_vv2_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(994)=50 */ {994, xed3_phash_find_mapevex_map1_opcode0x11_vv2_50_l1}, +/*h(706)=51 */ {706, xed3_phash_find_mapevex_map1_opcode0x11_vv2_51_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1206)=53 */ {1206, xed3_phash_find_mapevex_map1_opcode0x11_vv2_53_l1}, +/*h(918)=54 */ {918, xed3_phash_find_mapevex_map1_opcode0x11_vv2_54_l1}, +/*h(1994)=55 */ {1994, xed3_phash_find_mapevex_map1_opcode0x11_vv2_55_l1}, +/*h(1562)=56 */ {1562, xed3_phash_find_mapevex_map1_opcode0x11_vv2_56_l1}, +/*h(1274)=57 */ {1274, xed3_phash_find_mapevex_map1_opcode0x11_vv2_57_l1}, +/*h(986)=58 */ {986, xed3_phash_find_mapevex_map1_opcode0x11_vv2_58_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1630)=60 */ {1630, xed3_phash_find_mapevex_map1_opcode0x11_vv2_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1198)=62 */ {1198, xed3_phash_find_mapevex_map1_opcode0x11_vv2_62_l1}, +/*h(1986)=63 */ {1986, xed3_phash_find_mapevex_map1_opcode0x11_vv2_63_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(190)=65 */ {190, xed3_phash_find_mapevex_map1_opcode0x11_vv2_65_l1}, +/*h(1266)=66 */ {1266, xed3_phash_find_mapevex_map1_opcode0x11_vv2_66_l1}, +/*h(978)=67 */ {978, xed3_phash_find_mapevex_map1_opcode0x11_vv2_67_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1190)=70 */ {1190, xed3_phash_find_mapevex_map1_opcode0x11_vv2_70_l1}, +/*h(902)=71 */ {902, xed3_phash_find_mapevex_map1_opcode0x11_vv2_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1258)=74 */ {1258, xed3_phash_find_mapevex_map1_opcode0x11_vv2_74_l1}, +/*h(970)=75 */ {970, xed3_phash_find_mapevex_map1_opcode0x11_vv2_75_l1}, +/*h(216)=76 */ {216, xed3_phash_find_mapevex_map1_opcode0x11_vv2_76_l1}, +/*h(538)=77 */ {538, xed3_phash_find_mapevex_map1_opcode0x11_vv2_77_l1}, +/*h(250)=78 */ {250, xed3_phash_find_mapevex_map1_opcode0x11_vv2_78_l1}, +/*h(1182)=79 */ {1182, xed3_phash_find_mapevex_map1_opcode0x11_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(606)=81 */ {606, xed3_phash_find_mapevex_map1_opcode0x11_vv2_81_l1}, +/*h(174)=82 */ {174, xed3_phash_find_mapevex_map1_opcode0x11_vv2_82_l1}, +/*h(1250)=83 */ {1250, xed3_phash_find_mapevex_map1_opcode0x11_vv2_83_l1}, +/*h(962)=84 */ {962, xed3_phash_find_mapevex_map1_opcode0x11_vv2_84_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(242)=86 */ {242, xed3_phash_find_mapevex_map1_opcode0x11_vv2_86_l1}, +/*h(1462)=87 */ {1462, xed3_phash_find_mapevex_map1_opcode0x11_vv2_87_l1}, +/*h(1174)=88 */ {1174, xed3_phash_find_mapevex_map1_opcode0x11_vv2_88_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1530)=91 */ {1530, xed3_phash_find_mapevex_map1_opcode0x11_vv2_91_l1}, +/*h(1242)=92 */ {1242, xed3_phash_find_mapevex_map1_opcode0x11_vv2_92_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=95 */ {234, xed3_phash_find_mapevex_map1_opcode0x11_vv2_95_l1}, +/*h(1166)=96 */ {1166, xed3_phash_find_mapevex_map1_opcode0x11_vv2_96_l1}, +/*h(412)=97 */ {412, xed3_phash_find_mapevex_map1_opcode0x11_vv2_97_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1522)=99 */ {1522, xed3_phash_find_mapevex_map1_opcode0x11_vv2_99_l1}, +/*h(1234)=100 */ {1234, xed3_phash_find_mapevex_map1_opcode0x11_vv2_100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(226)=104 */ {226, xed3_phash_find_mapevex_map1_opcode0x11_vv2_104_l1}, +/*h(1158)=105 */ {1158, xed3_phash_find_mapevex_map1_opcode0x11_vv2_105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(438)=107 */ {438, xed3_phash_find_mapevex_map1_opcode0x11_vv2_107_l1}, +/*h(1514)=108 */ {1514, xed3_phash_find_mapevex_map1_opcode0x11_vv2_108_l1}, +/*h(1226)=109 */ {1226, xed3_phash_find_mapevex_map1_opcode0x11_vv2_109_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(506)=111 */ {506, xed3_phash_find_mapevex_map1_opcode0x11_vv2_111_l1}, +/*h(218)=112 */ {218, xed3_phash_find_mapevex_map1_opcode0x11_vv2_112_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1506)=116 */ {1506, xed3_phash_find_mapevex_map1_opcode0x11_vv2_116_l1}, +/*h(1218)=117 */ {1218, xed3_phash_find_mapevex_map1_opcode0x11_vv2_117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(498)=120 */ {498, xed3_phash_find_mapevex_map1_opcode0x11_vv2_120_l1}, +/*h(210)=121 */ {210, xed3_phash_find_mapevex_map1_opcode0x11_vv2_121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1786)=124 */ {1786, xed3_phash_find_mapevex_map1_opcode0x11_vv2_124_l1}, +/*h(1498)=125 */ {1498, xed3_phash_find_mapevex_map1_opcode0x11_vv2_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24)=128 */ {24, xed3_phash_find_mapevex_map1_opcode0x11_vv2_128_l1}, +/*h(202)=129 */ {202, xed3_phash_find_mapevex_map1_opcode0x11_vv2_129_l1}, +/*h(1422)=130 */ {1422, xed3_phash_find_mapevex_map1_opcode0x11_vv2_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(92)=132 */ {92, xed3_phash_find_mapevex_map1_opcode0x11_vv2_132_l1}, +/*h(1778)=133 */ {1778, xed3_phash_find_mapevex_map1_opcode0x11_vv2_133_l1}, +/*h(1490)=134 */ {1490, xed3_phash_find_mapevex_map1_opcode0x11_vv2_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(482)=137 */ {482, xed3_phash_find_mapevex_map1_opcode0x11_vv2_137_l1}, +/*h(194)=138 */ {194, xed3_phash_find_mapevex_map1_opcode0x11_vv2_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1770)=141 */ {1770, xed3_phash_find_mapevex_map1_opcode0x11_vv2_141_l1}, +/*h(1482)=142 */ {1482, xed3_phash_find_mapevex_map1_opcode0x11_vv2_142_l1}, +/*h(728)=143 */ {728, xed3_phash_find_mapevex_map1_opcode0x11_vv2_143_l1}, +/*h(1050)=144 */ {1050, xed3_phash_find_mapevex_map1_opcode0x11_vv2_144_l1}, +/*h(762)=145 */ {762, xed3_phash_find_mapevex_map1_opcode0x11_vv2_145_l1}, +/*h(474)=146 */ {474, xed3_phash_find_mapevex_map1_opcode0x11_vv2_146_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1118)=148 */ {1118, xed3_phash_find_mapevex_map1_opcode0x11_vv2_148_l1}, +/*h(686)=149 */ {686, xed3_phash_find_mapevex_map1_opcode0x11_vv2_149_l1}, +/*h(1762)=150 */ {1762, xed3_phash_find_mapevex_map1_opcode0x11_vv2_150_l1}, +/*h(1474)=151 */ {1474, xed3_phash_find_mapevex_map1_opcode0x11_vv2_151_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(754)=153 */ {754, xed3_phash_find_mapevex_map1_opcode0x11_vv2_153_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 154ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1340)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1340, 4923}, +/*h(2992)=1 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2992, 5022} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(948)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {948, 5021}, +/*h(3388)=1 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {3388, 4923}, +/*h(50)=2 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {50, 4985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2994)=0 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2994, 5022}, +/*h(1342)=1 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1342, 4923} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3390)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {3390, 4923}, +/*h(950)=1 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {950, 5021} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1336)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {4924} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1336; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3384)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {3384, 4924}, +/*h(944)=1 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {944, 5022} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1338)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {1338, 4924}, +/*h(118)=1 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {118, 4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3386)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {3386, 4924}, +/*h(946)=1 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {946, 5022} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3510)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {3510, 5017}, +/*h(316)=1 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {316, 4925} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_2_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2364)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {2364, 4925}, +/*h(102)=1 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {102, 4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(318)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4925} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2366)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4925} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(312)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {312, 4926}, +/*h(3506)=1 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {3506, 5018} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1462)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1462, 5017}, +/*h(98)=1 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {98, 4985}, +/*h(2360)=2 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {2360, 4926} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 17) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_4_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(170)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {170, 4983}, +/*h(3508)=1 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {3508, 5017}, +/*h(314)=2 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {314, 4926} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2362)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {4926} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(828)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {828, 4927}, +/*h(2480)=1 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2480, 5020}, +/*h(218)=2 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {218, 4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2876)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2876, 4927}, +/*h(436)=1 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {436, 5019} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(830)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {830, 4927}, +/*h(2482)=1 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2482, 5020} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2878)=0 EVV 0x12 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2878, 4927}, +/*h(6)=1 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {6, 4977}, +/*h(438)=2 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {438, 5019} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(824)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {824, 4928}, +/*h(70)=1 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {70, 4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(432)=0 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {432, 5020}, +/*h(2872)=1 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {2872, 4928} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(826)=0 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {4928} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(434)=0 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {434, 5020}, +/*h(2)=1 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {2, 4985}, +/*h(2874)=2 EVV 0x12 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_MOVDDUP()*/ {2874, 4928} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(38)=0 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 38; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3504)=0 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {3504, 5018}, +/*h(22)=1 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {22, 4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(86)=0 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 86; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(54)=0 EVV 0x12 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {4977} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 54; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(138)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(202)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 202; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(234)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(154)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(186)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(250)=0 EVV 0x12 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {4983} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(66)=0 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {4985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 66; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(34)=0 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {4985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 34; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(18)=0 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {4985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 18; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(82)=0 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {4985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 82; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(114)=0 EVV 0x12 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {4985} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1460)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {5017} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1460; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1456)=0 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {5018} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1458)=0 EVV 0x12 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {5018} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2484)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {5019} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2484; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2486)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {5019} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_45_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2996)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5021} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2998)=0 EVV 0x12 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5021} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x12_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[72] = { +/*h(34)=0 */ {34, xed3_phash_find_mapevex_map1_opcode0x12_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(102)=2 */ {102, xed3_phash_find_mapevex_map1_opcode0x12_vv2_2_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3508)=4 */ {3508, xed3_phash_find_mapevex_map1_opcode0x12_vv2_4_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1458)=6 */ {1458, xed3_phash_find_mapevex_map1_opcode0x12_vv2_6_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(18)=8 */ {18, xed3_phash_find_mapevex_map1_opcode0x12_vv2_8_l1}, +/*h(950)=9 */ {950, xed3_phash_find_mapevex_map1_opcode0x12_vv2_9_l1}, +/*h(86)=10 */ {86, xed3_phash_find_mapevex_map1_opcode0x12_vv2_10_l1}, +/*h(2992)=11 */ {2992, xed3_phash_find_mapevex_map1_opcode0x12_vv2_11_l1}, +/*h(154)=12 */ {154, xed3_phash_find_mapevex_map1_opcode0x12_vv2_12_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2484)=14 */ {2484, xed3_phash_find_mapevex_map1_opcode0x12_vv2_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(434)=16 */ {434, xed3_phash_find_mapevex_map1_opcode0x12_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(70)=18 */ {70, xed3_phash_find_mapevex_map1_opcode0x12_vv2_18_l1}, +/*h(2366)=19 */ {2366, xed3_phash_find_mapevex_map1_opcode0x12_vv2_19_l1}, +/*h(138)=20 */ {138, xed3_phash_find_mapevex_map1_opcode0x12_vv2_20_l1}, +/*h(3510)=21 */ {3510, xed3_phash_find_mapevex_map1_opcode0x12_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1460)=23 */ {1460, xed3_phash_find_mapevex_map1_opcode0x12_vv2_23_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(54)=26 */ {54, xed3_phash_find_mapevex_map1_opcode0x12_vv2_26_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2994)=28 */ {2994, xed3_phash_find_mapevex_map1_opcode0x12_vv2_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(944)=30 */ {944, xed3_phash_find_mapevex_map1_opcode0x12_vv2_30_l1}, +/*h(2486)=31 */ {2486, xed3_phash_find_mapevex_map1_opcode0x12_vv2_31_l1}, +/*h(114)=32 */ {114, xed3_phash_find_mapevex_map1_opcode0x12_vv2_32_l1}, +/*h(436)=33 */ {436, xed3_phash_find_mapevex_map1_opcode0x12_vv2_33_l1}, +/*h(38)=34 */ {38, xed3_phash_find_mapevex_map1_opcode0x12_vv2_34_l1}, +/*h(826)=35 */ {826, xed3_phash_find_mapevex_map1_opcode0x12_vv2_35_l1}, +/*h(250)=36 */ {250, xed3_phash_find_mapevex_map1_opcode0x12_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(318)=38 */ {318, xed3_phash_find_mapevex_map1_opcode0x12_vv2_38_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1462)=40 */ {1462, xed3_phash_find_mapevex_map1_opcode0x12_vv2_40_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3504)=42 */ {3504, xed3_phash_find_mapevex_map1_opcode0x12_vv2_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(234)=44 */ {234, xed3_phash_find_mapevex_map1_opcode0x12_vv2_44_l1}, +/*h(2996)=45 */ {2996, xed3_phash_find_mapevex_map1_opcode0x12_vv2_45_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(946)=47 */ {946, xed3_phash_find_mapevex_map1_opcode0x12_vv2_47_l1}, +/*h(82)=48 */ {82, xed3_phash_find_mapevex_map1_opcode0x12_vv2_48_l1}, +/*h(1336)=49 */ {1336, xed3_phash_find_mapevex_map1_opcode0x12_vv2_49_l1}, +/*h(438)=50 */ {438, xed3_phash_find_mapevex_map1_opcode0x12_vv2_50_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2480)=52 */ {2480, xed3_phash_find_mapevex_map1_opcode0x12_vv2_52_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(66)=56 */ {66, xed3_phash_find_mapevex_map1_opcode0x12_vv2_56_l1}, +/*h(2362)=57 */ {2362, xed3_phash_find_mapevex_map1_opcode0x12_vv2_57_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3506)=59 */ {3506, xed3_phash_find_mapevex_map1_opcode0x12_vv2_59_l1}, +/*h(202)=60 */ {202, xed3_phash_find_mapevex_map1_opcode0x12_vv2_60_l1}, +/*h(1456)=61 */ {1456, xed3_phash_find_mapevex_map1_opcode0x12_vv2_61_l1}, +/*h(2998)=62 */ {2998, xed3_phash_find_mapevex_map1_opcode0x12_vv2_62_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(948)=64 */ {948, xed3_phash_find_mapevex_map1_opcode0x12_vv2_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(118)=66 */ {118, xed3_phash_find_mapevex_map1_opcode0x12_vv2_66_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(186)=68 */ {186, xed3_phash_find_mapevex_map1_opcode0x12_vv2_68_l1}, +/*h(2482)=69 */ {2482, xed3_phash_find_mapevex_map1_opcode0x12_vv2_69_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(432)=71 */ {432, xed3_phash_find_mapevex_map1_opcode0x12_vv2_71_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 72ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x13_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(186)=0 EVV 0x13 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {186, 4984}, +/*h(50)=1 EVV 0x13 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {50, 4986} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x14_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 5997}, +/*h(14)=1 EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5990}, +/*h(66)=2 EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 5994}, +/*h(77)=3 EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5989}, +/*h(32)=4 EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 5999}, +/*h(46)=5 EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5992}, +/*h(1)=6 EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 5997}, +/*h(12)=7 EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5991}, +/*h(64)=8 EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 5995}, +/*h(78)=9 EVV 0x14 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5988}, +/*h(33)=10 EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 5999}, +/*h(44)=11 EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5993}, +/*h(2)=12 EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 5996}, +/*h(13)=13 EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5991}, +/*h(65)=14 EVV 0x14 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 5995}, +/*h(76)=15 EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5989}, +/*h(34)=16 EVV 0x14 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 5998}, +/*h(45)=17 EVV 0x14 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5993} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x15_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 5985}, +/*h(14)=1 EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5978}, +/*h(66)=2 EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 5982}, +/*h(77)=3 EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5977}, +/*h(32)=4 EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 5987}, +/*h(46)=5 EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5980}, +/*h(1)=6 EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 5985}, +/*h(12)=7 EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5979}, +/*h(64)=8 EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 5983}, +/*h(78)=9 EVV 0x15 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5976}, +/*h(33)=10 EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 5987}, +/*h(44)=11 EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5981}, +/*h(2)=12 EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 5984}, +/*h(13)=13 EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5979}, +/*h(65)=14 EVV 0x15 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 5983}, +/*h(76)=15 EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5977}, +/*h(34)=16 EVV 0x15 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 5986}, +/*h(45)=17 EVV 0x15 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5981} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x16_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[96] = { +/*empty slot1 */ {0,0}, +/*h(2992)=1 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2992, 5016}, +/*h(3504)=2 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {3504, 5012}, +/*h(250)=3 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {250, 4978}, +/*h(154)=4 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {154, 4978}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2486)=7 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {2486, 5013}, +/*h(2998)=8 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2998, 5015}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(34)=15 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {34, 4980}, +/*empty slot1 */ {0,0}, +/*h(1456)=17 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {1456, 5012}, +/*empty slot1 */ {0,0}, +/*h(2480)=19 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2480, 5014}, +/*empty slot1 */ {0,0}, +/*h(66)=21 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {66, 4980}, +/*h(438)=22 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {438, 5013}, +/*h(950)=23 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {950, 5015}, +/*h(1462)=24 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1462, 5011}, +/*empty slot1 */ {0,0}, +/*h(54)=26 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {54, 4982}, +/*h(98)=27 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {98, 4980}, +/*h(2)=28 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {2, 4980}, +/*h(2994)=29 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2994, 5016}, +/*h(3506)=30 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {3506, 5012}, +/*empty slot1 */ {0,0}, +/*h(86)=32 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {86, 4982}, +/*empty slot1 */ {0,0}, +/*h(432)=34 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {432, 5014}, +/*h(944)=35 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {944, 5016}, +/*h(170)=36 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {170, 4978}, +/*empty slot1 */ {0,0}, +/*h(118)=38 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {118, 4982}, +/*h(22)=39 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {22, 4982}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(202)=42 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {202, 4978}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1458)=45 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {1458, 5012}, +/*empty slot1 */ {0,0}, +/*h(2482)=47 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {2482, 5014}, +/*h(234)=48 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {234, 4978}, +/*h(138)=49 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {138, 4978}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2996)=57 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2996, 5015}, +/*h(3508)=58 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {3508, 5011}, +/*h(114)=59 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {114, 4980}, +/*h(18)=60 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {18, 4980}, +/*empty slot1 */ {0,0}, +/*h(434)=62 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {434, 5014}, +/*h(946)=63 EVV 0x16 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {946, 5016}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(50)=66 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {50, 4980}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(38)=71 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {38, 4982}, +/*h(82)=72 EVV 0x16 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {82, 4980}, +/*h(1460)=73 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1460, 5011}, +/*empty slot1 */ {0,0}, +/*h(2484)=75 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {2484, 5013}, +/*empty slot1 */ {0,0}, +/*h(70)=77 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {70, 4982}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(102)=83 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {102, 4982}, +/*h(6)=84 EVV 0x16 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 MASK=0*/ {6, 4982}, +/*empty slot1 */ {0,0}, +/*h(3510)=86 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {3510, 5011}, +/*h(186)=87 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {186, 4978}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(436)=90 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {436, 5013}, +/*h(948)=91 EVV 0x16 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {948, 5015}, +/*empty slot1 */ {0,0}, +/*h(218)=93 EVV 0x16 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {218, 4978}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((14*key % 269) % 96); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x17_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(186)=0 EVV 0x17 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {186, 4979}, +/*h(50)=1 EVV 0x17 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_TUPLE2()*/ {50, 4981} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x28_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(606)=0 EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4891}, +/*h(24)=1 EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {24, 4908}, +/*h(280)=2 EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {280, 4912}, +/*h(536)=3 EVV 0x28 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {536, 4904}, +/*h(92)=4 EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {92, 4896}, +/*h(348)=5 EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {348, 4900}, +/*h(604)=6 EVV 0x28 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {604, 4892}, +/*h(26)=7 EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 4907}, +/*h(282)=8 EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 4911}, +/*h(538)=9 EVV 0x28 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 4903}, +/*h(94)=10 EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4895}, +/*h(350)=11 EVV 0x28 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4899} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 59) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x29_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[36] = { +/*h(94)=0 EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4897}, +/*h(26)=1 EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 4909}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(604)=8 EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {604, 4894}, +/*h(536)=9 EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {536, 4906}, +/*empty slot1 */ {0,0}, +/*h(1630)=11 EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1630, 4893}, +/*h(1562)=12 EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1562, 4905}, +/*empty slot1 */ {0,0}, +/*h(606)=14 EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4893}, +/*h(538)=15 EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 4905}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(348)=19 EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {348, 4902}, +/*h(280)=20 EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {280, 4914}, +/*empty slot1 */ {0,0}, +/*h(1374)=22 EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1374, 4901}, +/*h(1306)=23 EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1306, 4913}, +/*empty slot1 */ {0,0}, +/*h(350)=25 EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4901}, +/*h(282)=26 EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 4913}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=30 EVV 0x29 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {92, 4898}, +/*h(24)=31 EVV 0x29 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {24, 4910}, +/*empty slot1 */ {0,0}, +/*h(1118)=33 EVV 0x29 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1118, 4897}, +/*h(1050)=34 EVV 0x29 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1050, 4909}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 41) % 36); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[72] = { +/*h(178)=0 EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {178, 4270}, +/*empty slot1 */ {0,0}, +/*h(246)=2 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {246, 4277}, +/*empty slot1 */ {0,0}, +/*h(170)=4 EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {170, 4266}, +/*empty slot1 */ {0,0}, +/*h(238)=6 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {238, 4271}, +/*h(183)=7 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {183, 4269}, +/*h(162)=8 EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {162, 4266}, +/*empty slot1 */ {0,0}, +/*h(230)=10 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {230, 4271}, +/*h(175)=11 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {175, 4264}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(167)=15 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {167, 4264}, +/*h(146)=16 EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {146, 4267}, +/*empty slot1 */ {0,0}, +/*h(214)=18 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {214, 4272}, +/*empty slot1 */ {0,0}, +/*h(138)=20 EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {138, 4266}, +/*empty slot1 */ {0,0}, +/*h(206)=22 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {206, 4271}, +/*h(151)=23 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {151, 4265}, +/*h(130)=24 EVV 0x2A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {130, 4266}, +/*empty slot1 */ {0,0}, +/*h(198)=26 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {198, 4271}, +/*h(143)=27 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {143, 4264}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(135)=31 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {135, 4264}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(182)=34 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {182, 4268}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(174)=38 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {174, 4264}, +/*empty slot1 */ {0,0}, +/*h(242)=40 EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {242, 4279}, +/*empty slot1 */ {0,0}, +/*h(166)=42 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {166, 4264}, +/*empty slot1 */ {0,0}, +/*h(234)=44 EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {234, 4275}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(247)=47 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {247, 4278}, +/*h(226)=48 EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {226, 4275}, +/*empty slot1 */ {0,0}, +/*h(150)=50 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {150, 4265}, +/*h(239)=51 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {239, 4273}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(142)=54 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {142, 4264}, +/*h(231)=55 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {231, 4273}, +/*h(210)=56 EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {210, 4276}, +/*empty slot1 */ {0,0}, +/*h(134)=58 EVV 0x2A VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {134, 4264}, +/*empty slot1 */ {0,0}, +/*h(202)=60 EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {202, 4275}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(215)=63 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {215, 4274}, +/*h(194)=64 EVV 0x2A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {194, 4275}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(207)=67 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {207, 4273}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(199)=71 EVV 0x2A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {199, 4273} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 72ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(562)=0 EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {562, 4998}, +/*h(698)=1 EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {698, 4995}, +/*h(1074)=2 EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {1074, 4996}, +/*h(50)=3 EVV 0x2B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {50, 4997}, +/*h(1210)=4 EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {1210, 4993}, +/*h(186)=5 EVV 0x2B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {186, 4994} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[120] = { +/*empty slot1 */ {0,0}, +/*h(2455)=1 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {2455, 4332}, +/*h(3502)=2 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3502, 4347}, +/*empty slot1 */ {0,0}, +/*h(2510)=4 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2510, 4329}, +/*h(2514)=5 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2514, 4337}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2447)=12 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2447, 4331}, +/*h(3494)=13 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3494, 4347}, +/*h(3498)=14 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3498, 4351}, +/*h(2502)=15 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2502, 4329}, +/*h(2506)=16 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2506, 4333}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2519)=20 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {2519, 4336}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2439)=23 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2439, 4331}, +/*empty slot1 */ {0,0}, +/*h(3490)=25 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3490, 4351}, +/*empty slot1 */ {0,0}, +/*h(2498)=27 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2498, 4333}, +/*empty slot1 */ {0,0}, +/*h(3503)=29 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3503, 4349}, +/*empty slot1 */ {0,0}, +/*h(2511)=31 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2511, 4331}, +/*empty slot1 */ {0,0}, +/*h(3562)=33 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3562, 4351}, +/*h(3566)=34 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3566, 4347}, +/*h(3478)=35 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {3478, 4348}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3495)=40 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3495, 4349}, +/*empty slot1 */ {0,0}, +/*h(2503)=42 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2503, 4331}, +/*empty slot1 */ {0,0}, +/*h(3554)=44 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3554, 4351}, +/*h(3558)=45 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3558, 4347}, +/*h(3470)=46 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3470, 4347}, +/*h(3474)=47 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {3474, 4352}, +/*h(2478)=48 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2478, 4329}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3462)=57 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3462, 4347}, +/*h(3466)=58 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3466, 4351}, +/*h(2470)=59 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2470, 4329}, +/*h(2474)=60 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2474, 4333}, +/*h(3567)=61 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3567, 4349}, +/*h(3479)=62 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 4350}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3538)=66 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {3538, 4355}, +/*h(3542)=67 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {3542, 4353}, +/*empty slot1 */ {0,0}, +/*h(3458)=69 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3458, 4351}, +/*empty slot1 */ {0,0}, +/*h(2466)=71 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2466, 4333}, +/*h(3559)=72 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3559, 4349}, +/*h(3471)=73 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3471, 4349}, +/*empty slot1 */ {0,0}, +/*h(2479)=75 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2479, 4331}, +/*empty slot1 */ {0,0}, +/*h(3530)=77 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3530, 4351}, +/*h(3534)=78 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3534, 4347}, +/*h(2538)=79 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2538, 4333}, +/*h(2542)=80 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2542, 4329}, +/*h(2454)=81 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {2454, 4330}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3463)=84 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3463, 4349}, +/*empty slot1 */ {0,0}, +/*h(2471)=86 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2471, 4331}, +/*empty slot1 */ {0,0}, +/*h(3522)=88 EVV 0x2C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3522, 4351}, +/*h(3526)=89 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3526, 4347}, +/*h(2530)=90 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2530, 4333}, +/*h(2534)=91 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2534, 4329}, +/*h(2446)=92 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2446, 4329}, +/*h(2450)=93 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2450, 4334}, +/*h(3543)=94 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3543, 4354}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2438)=103 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2438, 4329}, +/*h(2442)=104 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2442, 4333}, +/*h(3535)=105 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3535, 4349}, +/*empty slot1 */ {0,0}, +/*h(2543)=107 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2543, 4331}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2518)=113 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {2518, 4335}, +/*empty slot1 */ {0,0}, +/*h(2434)=115 EVV 0x2C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2434, 4333}, +/*h(3527)=116 EVV 0x2C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3527, 4349}, +/*empty slot1 */ {0,0}, +/*h(2535)=118 EVV 0x2C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2535, 4331}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((27*key % 227) % 120); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[120] = { +/*empty slot1 */ {0,0}, +/*h(2455)=1 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {2455, 4246}, +/*h(3502)=2 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3502, 4283}, +/*empty slot1 */ {0,0}, +/*h(2510)=4 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2510, 4243}, +/*h(2514)=5 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2514, 4251}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2447)=12 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2447, 4245}, +/*h(3494)=13 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3494, 4283}, +/*h(3498)=14 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3498, 4287}, +/*h(2502)=15 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2502, 4243}, +/*h(2506)=16 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2506, 4247}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2519)=20 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {2519, 4250}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2439)=23 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2439, 4245}, +/*empty slot1 */ {0,0}, +/*h(3490)=25 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3490, 4287}, +/*empty slot1 */ {0,0}, +/*h(2498)=27 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2498, 4247}, +/*empty slot1 */ {0,0}, +/*h(3503)=29 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3503, 4285}, +/*empty slot1 */ {0,0}, +/*h(2511)=31 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2511, 4245}, +/*empty slot1 */ {0,0}, +/*h(3562)=33 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3562, 4287}, +/*h(3566)=34 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3566, 4283}, +/*h(3478)=35 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {3478, 4284}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3495)=40 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3495, 4285}, +/*empty slot1 */ {0,0}, +/*h(2503)=42 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2503, 4245}, +/*empty slot1 */ {0,0}, +/*h(3554)=44 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3554, 4287}, +/*h(3558)=45 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3558, 4283}, +/*h(3470)=46 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3470, 4283}, +/*h(3474)=47 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {3474, 4288}, +/*h(2478)=48 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2478, 4243}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3462)=57 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3462, 4283}, +/*h(3466)=58 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3466, 4287}, +/*h(2470)=59 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2470, 4243}, +/*h(2474)=60 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2474, 4247}, +/*h(3567)=61 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3567, 4285}, +/*h(3479)=62 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 4286}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3538)=66 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {3538, 4291}, +/*h(3542)=67 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {3542, 4289}, +/*empty slot1 */ {0,0}, +/*h(3458)=69 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3458, 4287}, +/*empty slot1 */ {0,0}, +/*h(2466)=71 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2466, 4247}, +/*h(3559)=72 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3559, 4285}, +/*h(3471)=73 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3471, 4285}, +/*empty slot1 */ {0,0}, +/*h(2479)=75 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2479, 4245}, +/*empty slot1 */ {0,0}, +/*h(3530)=77 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3530, 4287}, +/*h(3534)=78 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3534, 4283}, +/*h(2538)=79 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2538, 4247}, +/*h(2542)=80 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2542, 4243}, +/*h(2454)=81 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {2454, 4244}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3463)=84 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3463, 4285}, +/*empty slot1 */ {0,0}, +/*h(2471)=86 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2471, 4245}, +/*empty slot1 */ {0,0}, +/*h(3522)=88 EVV 0x2D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3522, 4287}, +/*h(3526)=89 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3526, 4283}, +/*h(2530)=90 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2530, 4247}, +/*h(2534)=91 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2534, 4243}, +/*h(2446)=92 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2446, 4243}, +/*h(2450)=93 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2450, 4248}, +/*h(3543)=94 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3543, 4290}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2438)=103 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2438, 4243}, +/*h(2442)=104 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2442, 4247}, +/*h(3535)=105 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3535, 4285}, +/*empty slot1 */ {0,0}, +/*h(2543)=107 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2543, 4245}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2518)=113 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {2518, 4249}, +/*empty slot1 */ {0,0}, +/*h(2434)=115 EVV 0x2D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2434, 4247}, +/*h(3527)=116 EVV 0x2D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3527, 4285}, +/*empty slot1 */ {0,0}, +/*h(2535)=118 EVV 0x2D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2535, 4245}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((27*key % 227) % 120); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(191)=0 EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0*/ {191, 5971}, +/*h(190)=1 EVV 0x2E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {190, 5970}, +/*h(50)=2 EVV 0x2E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()*/ {50, 5975}, +/*h(55)=3 EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0*/ {55, 5974}, +/*h(54)=4 EVV 0x2E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {54, 5973}, +/*h(186)=5 EVV 0x2E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()*/ {186, 5972} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((28*key % 29) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x2f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(191)=0 EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 NOEVSR ZEROING=0 MASK=0*/ {191, 4156}, +/*h(190)=1 EVV 0x2F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {190, 4155}, +/*h(50)=2 EVV 0x2F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()*/ {50, 4160}, +/*h(55)=3 EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 NOEVSR ZEROING=0 MASK=0*/ {55, 4159}, +/*h(54)=4 EVV 0x2F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {54, 4158}, +/*h(186)=5 EVV 0x2F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR() FIX_ROUND_LEN128()*/ {186, 4157} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(d); +hidx = ((28*key % 29) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(606)=0 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {5930} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(472)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {472, 5949}, +/*h(95)=1 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {95, 5931} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(728)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {728, 5949}, +/*h(351)=1 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {351, 5931} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(984)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {984, 5949}, +/*h(607)=1 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {607, 5931} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(863)=0 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5931} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(604)=0 EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5932} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(605)=0 EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5932} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(704)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {704, 5949}, +/*h(94)=1 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 5933} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(935)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {935, 5945}, +/*h(92)=1 EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 5934}, +/*h(702)=2 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {702, 5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(93)=0 EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 5934}, +/*h(703)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {703, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(350)=0 EVV 0x51 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5935} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(348)=0 EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 5936}, +/*h(958)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {958, 5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(959)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {959, 5945}, +/*h(349)=1 EVV 0x51 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 5936} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(538)=0 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {5937} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(404)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {404, 5946}, +/*h(27)=1 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {27, 5938} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(660)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {660, 5946}, +/*h(283)=1 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {283, 5938} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(539)=0 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5938} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5938} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(536)=0 EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {536, 5939}, +/*h(1002)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1002, 5947}, +/*h(159)=2 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {159, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(537)=0 EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {5939} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {5940} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24)=0 EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24, 5941}, +/*h(1011)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {1011, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25)=0 EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {5941} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 25; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(282)=0 EVV 0x51 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5942} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(280)=0 EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {5943} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(281)=0 EVV 0x51 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {5943} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(744)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {744, 5949}, +/*h(134)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {134, 5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(390)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {390, 5944}, +/*h(1000)=1 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {1000, 5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(646)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(902)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(166)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {166, 5944}, +/*h(399)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {399, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(422)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(678)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(180)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {180, 5946}, +/*h(934)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {934, 5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {150, 5944}, +/*h(760)=1 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {760, 5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(406)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {406, 5944}, +/*h(927)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {927, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(662)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(918)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {918, 5944}, +/*h(164)=1 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {164, 5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(182)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {182, 5944}, +/*h(415)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {415, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(438)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {438, 5944}, +/*h(671)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {671, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(694)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(950)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1008)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {1008, 5949}, +/*h(398)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {398, 5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(654)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(910)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(174)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {174, 5944}, +/*h(407)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {407, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(430)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {430, 5944}, +/*h(663)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {663, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {158, 5944}, +/*h(391)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {391, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(414)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(670)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {670, 5944}, +/*h(903)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {903, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(926)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {926, 5944}, +/*h(172)=1 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {172, 5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(190)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {5944} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(446)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {446, 5944}, +/*h(679)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {679, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(135)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(647)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1010, 5947}, +/*h(167)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {167, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(151)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(919)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(183)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(439)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(695)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(951)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(143)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(655)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(911)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(175)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 175; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(431)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(687)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(943)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(191)=0 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(968)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {968, 5949}, +/*h(447)=1 EVV 0x51 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {447, 5945} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(132)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(388)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(644)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(900)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(420)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 420; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(676)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(932)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(148)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {450, 5947}, +/*h(916)=1 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {916, 5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(436)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {436, 5946}, +/*h(203)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {203, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(692)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(948)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {948, 5946}, +/*h(194)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {194, 5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(140)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(396)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(652)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(908)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(428)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(684)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(940)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {940, 5946}, +/*h(707)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {707, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(156)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(412)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(668)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(924)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(188)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {5946} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(444)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {444, 5946}, +/*h(211)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {211, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(234)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {234, 5947}, +/*h(700)=1 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {700, 5946}, +/*h(467)=2 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {467, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(956)=0 EVV 0x51 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {956, 5946}, +/*h(202)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {202, 5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {226, 5947}, +/*h(459)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {459, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(482)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {482, 5947}, +/*h(715)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {715, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(240)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {240, 5949}, +/*h(994)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {994, 5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(466)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {978, 5947}, +/*h(224)=1 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {224, 5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(242)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {242, 5947}, +/*h(475)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {475, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(498)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {498, 5947}, +/*h(731)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {731, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(754)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {754, 5947}, +/*h(987)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {987, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(458)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {458, 5947}, +/*h(979)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {979, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {216, 5949}, +/*h(970)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {970, 5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(490)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {490, 5947}, +/*h(723)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {723, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(218)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {218, 5947}, +/*h(451)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {451, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(474)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(986)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {986, 5947}, +/*h(232)=1 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {232, 5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(250)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(506)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {506, 5947}, +/*h(739)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {739, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {762, 5947}, +/*h(995)=1 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {995, 5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1018)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {5947} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(195)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(963)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(243)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(499)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(971)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(491)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(747)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1003)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(251)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(507)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(763)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1019)=0 EVV 0x51 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {5948} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(192)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(448)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(960)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(992)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(208)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(464)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(976)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(496)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(200)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(456)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(488)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(248)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(504)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1016)=0 EVV 0x51 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {5949} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x51_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[218] = { +/*h(466)=0 */ {466, xed3_phash_find_mapevex_map1_opcode0x51_vv2_0_l1}, +/*h(932)=1 */ {932, xed3_phash_find_mapevex_map1_opcode0x51_vv2_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(644)=3 */ {644, xed3_phash_find_mapevex_map1_opcode0x51_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(678)=5 */ {678, xed3_phash_find_mapevex_map1_opcode0x51_vv2_5_l1}, +/*h(911)=6 */ {911, xed3_phash_find_mapevex_map1_opcode0x51_vv2_6_l1}, +/*h(1000)=7 */ {1000, xed3_phash_find_mapevex_map1_opcode0x51_vv2_7_l1}, +/*h(712)=8 */ {712, xed3_phash_find_mapevex_map1_opcode0x51_vv2_8_l1}, +/*h(191)=9 */ {191, xed3_phash_find_mapevex_map1_opcode0x51_vv2_9_l1}, +/*h(280)=10 */ {280, xed3_phash_find_mapevex_map1_opcode0x51_vv2_10_l1}, +/*h(746)=11 */ {746, xed3_phash_find_mapevex_map1_opcode0x51_vv2_11_l1}, +/*h(979)=12 */ {979, xed3_phash_find_mapevex_map1_opcode0x51_vv2_12_l1}, +/*h(924)=13 */ {924, xed3_phash_find_mapevex_map1_opcode0x51_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26)=15 */ {26, xed3_phash_find_mapevex_map1_opcode0x51_vv2_15_l1}, +/*h(958)=16 */ {958, xed3_phash_find_mapevex_map1_opcode0x51_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(903)=18 */ {903, xed3_phash_find_mapevex_map1_opcode0x51_vv2_18_l1}, +/*h(992)=19 */ {992, xed3_phash_find_mapevex_map1_opcode0x51_vv2_19_l1}, +/*h(704)=20 */ {704, xed3_phash_find_mapevex_map1_opcode0x51_vv2_20_l1}, +/*h(183)=21 */ {183, xed3_phash_find_mapevex_map1_opcode0x51_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=23 */ {738, xed3_phash_find_mapevex_map1_opcode0x51_vv2_23_l1}, +/*h(971)=24 */ {971, xed3_phash_find_mapevex_map1_opcode0x51_vv2_24_l1}, +/*h(450)=25 */ {450, xed3_phash_find_mapevex_map1_opcode0x51_vv2_25_l1}, +/*h(539)=26 */ {539, xed3_phash_find_mapevex_map1_opcode0x51_vv2_26_l1}, +/*h(251)=27 */ {251, xed3_phash_find_mapevex_map1_opcode0x51_vv2_27_l1}, +/*h(950)=28 */ {950, xed3_phash_find_mapevex_map1_opcode0x51_vv2_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(662)=30 */ {662, xed3_phash_find_mapevex_map1_opcode0x51_vv2_30_l1}, +/*h(984)=31 */ {984, xed3_phash_find_mapevex_map1_opcode0x51_vv2_31_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(175)=33 */ {175, xed3_phash_find_mapevex_map1_opcode0x51_vv2_33_l1}, +/*h(1018)=34 */ {1018, xed3_phash_find_mapevex_map1_opcode0x51_vv2_34_l1}, +/*h(730)=35 */ {730, xed3_phash_find_mapevex_map1_opcode0x51_vv2_35_l1}, +/*h(963)=36 */ {963, xed3_phash_find_mapevex_map1_opcode0x51_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(908)=38 */ {908, xed3_phash_find_mapevex_map1_opcode0x51_vv2_38_l1}, +/*h(243)=39 */ {243, xed3_phash_find_mapevex_map1_opcode0x51_vv2_39_l1}, +/*h(942)=40 */ {942, xed3_phash_find_mapevex_map1_opcode0x51_vv2_40_l1}, +/*h(188)=41 */ {188, xed3_phash_find_mapevex_map1_opcode0x51_vv2_41_l1}, +/*h(654)=42 */ {654, xed3_phash_find_mapevex_map1_opcode0x51_vv2_42_l1}, +/*h(976)=43 */ {976, xed3_phash_find_mapevex_map1_opcode0x51_vv2_43_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=46 */ {1010, xed3_phash_find_mapevex_map1_opcode0x51_vv2_46_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(722)=48 */ {722, xed3_phash_find_mapevex_map1_opcode0x51_vv2_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(900)=50 */ {900, xed3_phash_find_mapevex_map1_opcode0x51_vv2_50_l1}, +/*h(235)=51 */ {235, xed3_phash_find_mapevex_map1_opcode0x51_vv2_51_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(180)=53 */ {180, xed3_phash_find_mapevex_map1_opcode0x51_vv2_53_l1}, +/*h(646)=54 */ {646, xed3_phash_find_mapevex_map1_opcode0x51_vv2_54_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(968)=56 */ {968, xed3_phash_find_mapevex_map1_opcode0x51_vv2_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1002)=58 */ {1002, xed3_phash_find_mapevex_map1_opcode0x51_vv2_58_l1}, +/*h(248)=59 */ {248, xed3_phash_find_mapevex_map1_opcode0x51_vv2_59_l1}, +/*h(714)=60 */ {714, xed3_phash_find_mapevex_map1_opcode0x51_vv2_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(282)=62 */ {282, xed3_phash_find_mapevex_map1_opcode0x51_vv2_62_l1}, +/*h(604)=63 */ {604, xed3_phash_find_mapevex_map1_opcode0x51_vv2_63_l1}, +/*h(227)=64 */ {227, xed3_phash_find_mapevex_map1_opcode0x51_vv2_64_l1}, +/*h(172)=65 */ {172, xed3_phash_find_mapevex_map1_opcode0x51_vv2_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(350)=67 */ {350, xed3_phash_find_mapevex_map1_opcode0x51_vv2_67_l1}, +/*h(960)=68 */ {960, xed3_phash_find_mapevex_map1_opcode0x51_vv2_68_l1}, +/*h(439)=69 */ {439, xed3_phash_find_mapevex_map1_opcode0x51_vv2_69_l1}, +/*h(151)=70 */ {151, xed3_phash_find_mapevex_map1_opcode0x51_vv2_70_l1}, +/*h(240)=71 */ {240, xed3_phash_find_mapevex_map1_opcode0x51_vv2_71_l1}, +/*h(706)=72 */ {706, xed3_phash_find_mapevex_map1_opcode0x51_vv2_72_l1}, +/*h(795)=73 */ {795, xed3_phash_find_mapevex_map1_opcode0x51_vv2_73_l1}, +/*h(507)=74 */ {507, xed3_phash_find_mapevex_map1_opcode0x51_vv2_74_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(219)=76 */ {219, xed3_phash_find_mapevex_map1_opcode0x51_vv2_76_l1}, +/*h(164)=77 */ {164, xed3_phash_find_mapevex_map1_opcode0x51_vv2_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(863)=79 */ {863, xed3_phash_find_mapevex_map1_opcode0x51_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(431)=81 */ {431, xed3_phash_find_mapevex_map1_opcode0x51_vv2_81_l1}, +/*h(143)=82 */ {143, xed3_phash_find_mapevex_map1_opcode0x51_vv2_82_l1}, +/*h(232)=83 */ {232, xed3_phash_find_mapevex_map1_opcode0x51_vv2_83_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(499)=86 */ {499, xed3_phash_find_mapevex_map1_opcode0x51_vv2_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(211)=88 */ {211, xed3_phash_find_mapevex_map1_opcode0x51_vv2_88_l1}, +/*h(910)=89 */ {910, xed3_phash_find_mapevex_map1_opcode0x51_vv2_89_l1}, +/*h(156)=90 */ {156, xed3_phash_find_mapevex_map1_opcode0x51_vv2_90_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(190)=92 */ {190, xed3_phash_find_mapevex_map1_opcode0x51_vv2_92_l1}, +/*h(423)=93 */ {423, xed3_phash_find_mapevex_map1_opcode0x51_vv2_93_l1}, +/*h(135)=94 */ {135, xed3_phash_find_mapevex_map1_opcode0x51_vv2_94_l1}, +/*h(224)=95 */ {224, xed3_phash_find_mapevex_map1_opcode0x51_vv2_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25)=98 */ {25, xed3_phash_find_mapevex_map1_opcode0x51_vv2_98_l1}, +/*h(491)=99 */ {491, xed3_phash_find_mapevex_map1_opcode0x51_vv2_99_l1}, +/*h(203)=100 */ {203, xed3_phash_find_mapevex_map1_opcode0x51_vv2_100_l1}, +/*h(902)=101 */ {902, xed3_phash_find_mapevex_map1_opcode0x51_vv2_101_l1}, +/*h(148)=102 */ {148, xed3_phash_find_mapevex_map1_opcode0x51_vv2_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(703)=104 */ {703, xed3_phash_find_mapevex_map1_opcode0x51_vv2_104_l1}, +/*h(415)=105 */ {415, xed3_phash_find_mapevex_map1_opcode0x51_vv2_105_l1}, +/*h(504)=106 */ {504, xed3_phash_find_mapevex_map1_opcode0x51_vv2_106_l1}, +/*h(216)=107 */ {216, xed3_phash_find_mapevex_map1_opcode0x51_vv2_107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(538)=109 */ {538, xed3_phash_find_mapevex_map1_opcode0x51_vv2_109_l1}, +/*h(250)=110 */ {250, xed3_phash_find_mapevex_map1_opcode0x51_vv2_110_l1}, +/*h(483)=111 */ {483, xed3_phash_find_mapevex_map1_opcode0x51_vv2_111_l1}, +/*h(195)=112 */ {195, xed3_phash_find_mapevex_map1_opcode0x51_vv2_112_l1}, +/*h(428)=113 */ {428, xed3_phash_find_mapevex_map1_opcode0x51_vv2_113_l1}, +/*h(140)=114 */ {140, xed3_phash_find_mapevex_map1_opcode0x51_vv2_114_l1}, +/*h(606)=115 */ {606, xed3_phash_find_mapevex_map1_opcode0x51_vv2_115_l1}, +/*h(695)=116 */ {695, xed3_phash_find_mapevex_map1_opcode0x51_vv2_116_l1}, +/*h(407)=117 */ {407, xed3_phash_find_mapevex_map1_opcode0x51_vv2_117_l1}, +/*h(496)=118 */ {496, xed3_phash_find_mapevex_map1_opcode0x51_vv2_118_l1}, +/*h(962)=119 */ {962, xed3_phash_find_mapevex_map1_opcode0x51_vv2_119_l1}, +/*h(208)=120 */ {208, xed3_phash_find_mapevex_map1_opcode0x51_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(763)=122 */ {763, xed3_phash_find_mapevex_map1_opcode0x51_vv2_122_l1}, +/*h(475)=123 */ {475, xed3_phash_find_mapevex_map1_opcode0x51_vv2_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(420)=125 */ {420, xed3_phash_find_mapevex_map1_opcode0x51_vv2_125_l1}, +/*h(132)=126 */ {132, xed3_phash_find_mapevex_map1_opcode0x51_vv2_126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(687)=128 */ {687, xed3_phash_find_mapevex_map1_opcode0x51_vv2_128_l1}, +/*h(399)=129 */ {399, xed3_phash_find_mapevex_map1_opcode0x51_vv2_129_l1}, +/*h(488)=130 */ {488, xed3_phash_find_mapevex_map1_opcode0x51_vv2_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(200)=132 */ {200, xed3_phash_find_mapevex_map1_opcode0x51_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(755)=134 */ {755, xed3_phash_find_mapevex_map1_opcode0x51_vv2_134_l1}, +/*h(467)=135 */ {467, xed3_phash_find_mapevex_map1_opcode0x51_vv2_135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(412)=137 */ {412, xed3_phash_find_mapevex_map1_opcode0x51_vv2_137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(679)=140 */ {679, xed3_phash_find_mapevex_map1_opcode0x51_vv2_140_l1}, +/*h(391)=141 */ {391, xed3_phash_find_mapevex_map1_opcode0x51_vv2_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(480)=143 */ {480, xed3_phash_find_mapevex_map1_opcode0x51_vv2_143_l1}, +/*h(192)=144 */ {192, xed3_phash_find_mapevex_map1_opcode0x51_vv2_144_l1}, +/*h(281)=145 */ {281, xed3_phash_find_mapevex_map1_opcode0x51_vv2_145_l1}, +/*h(747)=146 */ {747, xed3_phash_find_mapevex_map1_opcode0x51_vv2_146_l1}, +/*h(459)=147 */ {459, xed3_phash_find_mapevex_map1_opcode0x51_vv2_147_l1}, +/*h(692)=148 */ {692, xed3_phash_find_mapevex_map1_opcode0x51_vv2_148_l1}, +/*h(404)=149 */ {404, xed3_phash_find_mapevex_map1_opcode0x51_vv2_149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(959)=151 */ {959, xed3_phash_find_mapevex_map1_opcode0x51_vv2_151_l1}, +/*h(671)=152 */ {671, xed3_phash_find_mapevex_map1_opcode0x51_vv2_152_l1}, +/*h(760)=153 */ {760, xed3_phash_find_mapevex_map1_opcode0x51_vv2_153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(472)=155 */ {472, xed3_phash_find_mapevex_map1_opcode0x51_vv2_155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=158 */ {739, xed3_phash_find_mapevex_map1_opcode0x51_vv2_158_l1}, +/*h(451)=159 */ {451, xed3_phash_find_mapevex_map1_opcode0x51_vv2_159_l1}, +/*h(684)=160 */ {684, xed3_phash_find_mapevex_map1_opcode0x51_vv2_160_l1}, +/*h(396)=161 */ {396, xed3_phash_find_mapevex_map1_opcode0x51_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(951)=163 */ {951, xed3_phash_find_mapevex_map1_opcode0x51_vv2_163_l1}, +/*h(663)=164 */ {663, xed3_phash_find_mapevex_map1_opcode0x51_vv2_164_l1}, +/*h(142)=165 */ {142, xed3_phash_find_mapevex_map1_opcode0x51_vv2_165_l1}, +/*h(752)=166 */ {752, xed3_phash_find_mapevex_map1_opcode0x51_vv2_166_l1}, +/*h(464)=167 */ {464, xed3_phash_find_mapevex_map1_opcode0x51_vv2_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1019)=169 */ {1019, xed3_phash_find_mapevex_map1_opcode0x51_vv2_169_l1}, +/*h(731)=170 */ {731, xed3_phash_find_mapevex_map1_opcode0x51_vv2_170_l1}, +/*h(210)=171 */ {210, xed3_phash_find_mapevex_map1_opcode0x51_vv2_171_l1}, +/*h(676)=172 */ {676, xed3_phash_find_mapevex_map1_opcode0x51_vv2_172_l1}, +/*h(388)=173 */ {388, xed3_phash_find_mapevex_map1_opcode0x51_vv2_173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(943)=175 */ {943, xed3_phash_find_mapevex_map1_opcode0x51_vv2_175_l1}, +/*h(422)=176 */ {422, xed3_phash_find_mapevex_map1_opcode0x51_vv2_176_l1}, +/*h(655)=177 */ {655, xed3_phash_find_mapevex_map1_opcode0x51_vv2_177_l1}, +/*h(744)=178 */ {744, xed3_phash_find_mapevex_map1_opcode0x51_vv2_178_l1}, +/*h(456)=179 */ {456, xed3_phash_find_mapevex_map1_opcode0x51_vv2_179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1011)=181 */ {1011, xed3_phash_find_mapevex_map1_opcode0x51_vv2_181_l1}, +/*h(723)=182 */ {723, xed3_phash_find_mapevex_map1_opcode0x51_vv2_182_l1}, +/*h(202)=183 */ {202, xed3_phash_find_mapevex_map1_opcode0x51_vv2_183_l1}, +/*h(668)=184 */ {668, xed3_phash_find_mapevex_map1_opcode0x51_vv2_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(935)=187 */ {935, xed3_phash_find_mapevex_map1_opcode0x51_vv2_187_l1}, +/*h(414)=188 */ {414, xed3_phash_find_mapevex_map1_opcode0x51_vv2_188_l1}, +/*h(647)=189 */ {647, xed3_phash_find_mapevex_map1_opcode0x51_vv2_189_l1}, +/*h(736)=190 */ {736, xed3_phash_find_mapevex_map1_opcode0x51_vv2_190_l1}, +/*h(448)=191 */ {448, xed3_phash_find_mapevex_map1_opcode0x51_vv2_191_l1}, +/*h(537)=192 */ {537, xed3_phash_find_mapevex_map1_opcode0x51_vv2_192_l1}, +/*h(1003)=193 */ {1003, xed3_phash_find_mapevex_map1_opcode0x51_vv2_193_l1}, +/*h(715)=194 */ {715, xed3_phash_find_mapevex_map1_opcode0x51_vv2_194_l1}, +/*h(194)=195 */ {194, xed3_phash_find_mapevex_map1_opcode0x51_vv2_195_l1}, +/*h(660)=196 */ {660, xed3_phash_find_mapevex_map1_opcode0x51_vv2_196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(605)=198 */ {605, xed3_phash_find_mapevex_map1_opcode0x51_vv2_198_l1}, +/*h(694)=199 */ {694, xed3_phash_find_mapevex_map1_opcode0x51_vv2_199_l1}, +/*h(927)=200 */ {927, xed3_phash_find_mapevex_map1_opcode0x51_vv2_200_l1}, +/*h(1016)=201 */ {1016, xed3_phash_find_mapevex_map1_opcode0x51_vv2_201_l1}, +/*h(728)=202 */ {728, xed3_phash_find_mapevex_map1_opcode0x51_vv2_202_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(995)=205 */ {995, xed3_phash_find_mapevex_map1_opcode0x51_vv2_205_l1}, +/*h(474)=206 */ {474, xed3_phash_find_mapevex_map1_opcode0x51_vv2_206_l1}, +/*h(707)=207 */ {707, xed3_phash_find_mapevex_map1_opcode0x51_vv2_207_l1}, +/*h(652)=208 */ {652, xed3_phash_find_mapevex_map1_opcode0x51_vv2_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=211 */ {686, xed3_phash_find_mapevex_map1_opcode0x51_vv2_211_l1}, +/*h(919)=212 */ {919, xed3_phash_find_mapevex_map1_opcode0x51_vv2_212_l1}, +/*h(1008)=213 */ {1008, xed3_phash_find_mapevex_map1_opcode0x51_vv2_213_l1}, +/*h(720)=214 */ {720, xed3_phash_find_mapevex_map1_opcode0x51_vv2_214_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(987)=217 */ {987, xed3_phash_find_mapevex_map1_opcode0x51_vv2_217_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 218ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x54_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 6049}, +/*h(14)=1 EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6042}, +/*h(66)=2 EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 6052}, +/*h(77)=3 EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6047}, +/*h(32)=4 EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 6051}, +/*h(46)=5 EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6044}, +/*h(1)=6 EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 6049}, +/*h(12)=7 EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6043}, +/*h(64)=8 EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 6053}, +/*h(78)=9 EVV 0x54 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6046}, +/*h(33)=10 EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 6051}, +/*h(44)=11 EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6045}, +/*h(2)=12 EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 6048}, +/*h(13)=13 EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6043}, +/*h(65)=14 EVV 0x54 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 6053}, +/*h(76)=15 EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6047}, +/*h(34)=16 EVV 0x54 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 6050}, +/*h(45)=17 EVV 0x54 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6045} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x55_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 6037}, +/*h(14)=1 EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6030}, +/*h(66)=2 EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 6040}, +/*h(77)=3 EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6035}, +/*h(32)=4 EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 6039}, +/*h(46)=5 EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6032}, +/*h(1)=6 EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 6037}, +/*h(12)=7 EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6031}, +/*h(64)=8 EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 6041}, +/*h(78)=9 EVV 0x55 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6034}, +/*h(33)=10 EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 6039}, +/*h(44)=11 EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6033}, +/*h(2)=12 EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 6036}, +/*h(13)=13 EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6031}, +/*h(65)=14 EVV 0x55 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 6041}, +/*h(76)=15 EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6035}, +/*h(34)=16 EVV 0x55 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 6038}, +/*h(45)=17 EVV 0x55 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6033} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x56_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 6231}, +/*h(14)=1 EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6224}, +/*h(66)=2 EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 6234}, +/*h(77)=3 EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6229}, +/*h(32)=4 EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 6233}, +/*h(46)=5 EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6226}, +/*h(1)=6 EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 6231}, +/*h(12)=7 EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6225}, +/*h(64)=8 EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 6235}, +/*h(78)=9 EVV 0x56 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6228}, +/*h(33)=10 EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 6233}, +/*h(44)=11 EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6227}, +/*h(2)=12 EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 6230}, +/*h(13)=13 EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6225}, +/*h(65)=14 EVV 0x56 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 6235}, +/*h(76)=15 EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6229}, +/*h(34)=16 EVV 0x56 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 6232}, +/*h(45)=17 EVV 0x56 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6227} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x57_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 6809}, +/*h(14)=1 EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 6802}, +/*h(66)=2 EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 6812}, +/*h(77)=3 EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 6807}, +/*h(32)=4 EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 6811}, +/*h(46)=5 EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 6804}, +/*h(1)=6 EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 6809}, +/*h(12)=7 EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 6803}, +/*h(64)=8 EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 6813}, +/*h(78)=9 EVV 0x57 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 6806}, +/*h(33)=10 EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 6811}, +/*h(44)=11 EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 6805}, +/*h(2)=12 EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 6808}, +/*h(13)=13 EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 6803}, +/*h(65)=14 EVV 0x57 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 6813}, +/*h(76)=15 EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 6807}, +/*h(34)=16 EVV 0x57 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 6810}, +/*h(45)=17 EVV 0x57 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 6805} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x58_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 4086}, +/*h(46)=1 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4080}, +/*h(54)=2 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {54, 4089}, +/*h(24)=3 EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 4094}, +/*h(32)=4 EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 4088}, +/*h(78)=5 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4075}, +/*h(86)=6 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {86, 4089}, +/*h(56)=7 EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 4094}, +/*h(64)=8 EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 4084}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {118, 4089}, +/*h(88)=11 EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 4094}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4076}, +/*h(23)=14 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {23, 4090}, +/*h(120)=15 EVV 0x58 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 4094}, +/*h(1)=16 EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 4086}, +/*h(47)=17 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4076}, +/*h(55)=18 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {55, 4090}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 4088}, +/*h(79)=21 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4076}, +/*h(87)=22 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {87, 4090}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0x58 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 4084}, +/*h(111)=25 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4076}, +/*h(119)=26 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {119, 4090}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 4085}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {26, 4092}, +/*h(34)=36 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 4087}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {58, 4092}, +/*h(66)=40 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 4082}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {90, 4092}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {122, 4092}, +/*h(3)=48 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 4083}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 4093}, +/*h(35)=52 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 4083}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 4093}, +/*h(67)=56 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 4083}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 4093}, +/*h(99)=60 EVV 0x58 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 4083}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0x58 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 4093}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4079}, +/*h(20)=66 EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 4091}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4081}, +/*h(52)=70 EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 4091}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4077}, +/*h(84)=74 EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 4091}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0x58 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 4091}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4079}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4081}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0x58 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4077}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0x58 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4078}, +/*h(22)=98 EVV 0x58 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {22, 4089}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x59_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 5062}, +/*h(46)=1 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5056}, +/*h(54)=2 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {54, 5065}, +/*h(24)=3 EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 5070}, +/*h(32)=4 EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 5064}, +/*h(78)=5 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5051}, +/*h(86)=6 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {86, 5065}, +/*h(56)=7 EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 5070}, +/*h(64)=8 EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 5060}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {118, 5065}, +/*h(88)=11 EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 5070}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 5052}, +/*h(23)=14 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {23, 5066}, +/*h(120)=15 EVV 0x59 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 5070}, +/*h(1)=16 EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 5062}, +/*h(47)=17 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 5052}, +/*h(55)=18 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {55, 5066}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 5064}, +/*h(79)=21 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 5052}, +/*h(87)=22 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {87, 5066}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0x59 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 5060}, +/*h(111)=25 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 5052}, +/*h(119)=26 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {119, 5066}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 5061}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {26, 5068}, +/*h(34)=36 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 5063}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {58, 5068}, +/*h(66)=40 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 5058}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {90, 5068}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {122, 5068}, +/*h(3)=48 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 5059}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 5069}, +/*h(35)=52 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 5059}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 5069}, +/*h(67)=56 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 5059}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 5069}, +/*h(99)=60 EVV 0x59 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 5059}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0x59 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 5069}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5055}, +/*h(20)=66 EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 5067}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5057}, +/*h(52)=70 EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 5067}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5053}, +/*h(84)=74 EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 5067}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0x59 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 5067}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5055}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5057}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0x59 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5053}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0x59 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5054}, +/*h(22)=98 EVV 0x59 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {22, 5065}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(606)=0 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4194} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_155_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(472)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {472, 4282}, +/*h(95)=1 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {95, 4195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(728)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {728, 4282}, +/*h(351)=1 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {351, 4195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(984)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {984, 4282}, +/*h(607)=1 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {607, 4195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_79_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(863)=0 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(604)=0 EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(605)=0 EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4196} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 605; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(704)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {704, 4282}, +/*h(94)=1 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(935)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {935, 4253}, +/*h(92)=1 EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 4198}, +/*h(702)=2 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {702, 4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(93)=0 EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 4198}, +/*h(703)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {703, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(350)=0 EVV 0x5A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4199} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(348)=0 EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 4200}, +/*h(958)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {958, 4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(959)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {959, 4253}, +/*h(349)=1 EVV 0x5A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 4200} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(538)=0 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4222} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(404)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {404, 4254}, +/*h(27)=1 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {27, 4223} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(660)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {660, 4254}, +/*h(283)=1 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {283, 4223} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_26_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(539)=0 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4223} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(795)=0 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4223} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 795; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(536)=0 EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {536, 4224}, +/*h(1002)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1002, 4280}, +/*h(159)=2 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {159, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(537)=0 EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4224} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 537; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26)=0 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 26; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24)=0 EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {24, 4226}, +/*h(1011)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {1011, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25)=0 EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4226} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 25; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(282)=0 EVV 0x5A VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4227} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(280)=0 EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4228} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 280; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(281)=0 EVV 0x5A VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4228} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 281; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(744)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {744, 4282}, +/*h(134)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {134, 4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(390)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {390, 4252}, +/*h(1000)=1 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {1000, 4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(646)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(902)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(166)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {166, 4252}, +/*h(399)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {399, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(422)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(678)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_53_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(180)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {180, 4254}, +/*h(934)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {934, 4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(150)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {150, 4252}, +/*h(760)=1 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {760, 4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(406)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {406, 4252}, +/*h(927)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {927, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_30_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(662)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(918)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {918, 4252}, +/*h(164)=1 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {164, 4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(182)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {182, 4252}, +/*h(415)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {415, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(438)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {438, 4252}, +/*h(671)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {671, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(694)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(950)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(142)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1008)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {1008, 4282}, +/*h(398)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {398, 4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(654)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(910)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(174)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {174, 4252}, +/*h(407)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {407, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_164_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(430)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {430, 4252}, +/*h(663)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {663, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(686)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_40_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(942)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(158)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {158, 4252}, +/*h(391)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {391, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(414)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(670)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {670, 4252}, +/*h(903)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {903, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_65_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(926)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {926, 4252}, +/*h(172)=1 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {172, 4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(190)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {4252} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(446)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {446, 4252}, +/*h(679)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {679, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(135)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(647)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1010)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {1010, 4280}, +/*h(167)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {167, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(151)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 151; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(919)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(183)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(439)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(695)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(951)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(143)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 143; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(655)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(911)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(175)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 175; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(431)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(687)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(943)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(191)=0 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_56_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(968)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {968, 4282}, +/*h(447)=1 EVV 0x5A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {447, 4253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(132)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 132; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(388)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(644)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(900)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 900; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(420)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 420; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(676)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 676; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_1_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(932)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(148)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 148; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {450, 4280}, +/*h(916)=1 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {916, 4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(436)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {436, 4254}, +/*h(203)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {203, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_148_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(692)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 692; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(948)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {948, 4254}, +/*h(194)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {194, 4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(140)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 140; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(396)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 396; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(652)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_38_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(908)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(428)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_160_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(684)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 684; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(940)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {940, 4254}, +/*h(707)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {707, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(156)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 156; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(412)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 412; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(668)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 668; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(924)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(188)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {4254} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 188; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(444)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {444, 4254}, +/*h(211)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {211, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_135_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(234)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {234, 4280}, +/*h(700)=1 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {700, 4254}, +/*h(467)=2 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {467, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(956)=0 EVV 0x5A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {956, 4254}, +/*h(202)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {202, 4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_72_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(962)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(226)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {226, 4280}, +/*h(459)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {459, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(482)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {482, 4280}, +/*h(715)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {715, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(738)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(240)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {240, 4282}, +/*h(994)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {994, 4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(210)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(466)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(722)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(978)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {978, 4280}, +/*h(224)=1 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {224, 4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(242)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {242, 4280}, +/*h(475)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {475, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(498)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {498, 4280}, +/*h(731)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {731, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(754)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {754, 4280}, +/*h(987)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {987, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(458)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {458, 4280}, +/*h(979)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {979, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(714)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(216)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {216, 4282}, +/*h(970)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {970, 4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(490)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {490, 4280}, +/*h(723)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {723, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_11_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(746)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(218)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {218, 4280}, +/*h(451)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {451, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(474)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_35_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(730)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(986)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {986, 4280}, +/*h(232)=1 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {232, 4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(250)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(506)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {506, 4280}, +/*h(739)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {739, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(762)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {762, 4280}, +/*h(995)=1 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {995, 4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1018)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {4280} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(195)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 195; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(963)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(227)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 227; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(243)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 243; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(499)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 499; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(971)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 971; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(235)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 235; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(491)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(747)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 747; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1003)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(219)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 219; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(251)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 251; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(507)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(763)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1019)=0 EVV 0x5A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {4281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1019; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(192)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 192; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(448)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(960)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(992)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(208)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 208; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(464)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(976)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(496)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 496; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(200)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 200; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(456)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(488)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(248)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 248; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(504)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 504; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1016)=0 EVV 0x5A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {4282} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = key - 1016; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5a_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[218] = { +/*h(466)=0 */ {466, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_0_l1}, +/*h(932)=1 */ {932, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_1_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(644)=3 */ {644, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(678)=5 */ {678, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_5_l1}, +/*h(911)=6 */ {911, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_6_l1}, +/*h(1000)=7 */ {1000, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_7_l1}, +/*h(712)=8 */ {712, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_8_l1}, +/*h(191)=9 */ {191, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_9_l1}, +/*h(280)=10 */ {280, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_10_l1}, +/*h(746)=11 */ {746, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_11_l1}, +/*h(979)=12 */ {979, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_12_l1}, +/*h(924)=13 */ {924, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_13_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26)=15 */ {26, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_15_l1}, +/*h(958)=16 */ {958, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(903)=18 */ {903, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_18_l1}, +/*h(992)=19 */ {992, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_19_l1}, +/*h(704)=20 */ {704, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_20_l1}, +/*h(183)=21 */ {183, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(738)=23 */ {738, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_23_l1}, +/*h(971)=24 */ {971, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_24_l1}, +/*h(450)=25 */ {450, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_25_l1}, +/*h(539)=26 */ {539, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_26_l1}, +/*h(251)=27 */ {251, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_27_l1}, +/*h(950)=28 */ {950, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_28_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(662)=30 */ {662, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_30_l1}, +/*h(984)=31 */ {984, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_31_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(175)=33 */ {175, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_33_l1}, +/*h(1018)=34 */ {1018, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_34_l1}, +/*h(730)=35 */ {730, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_35_l1}, +/*h(963)=36 */ {963, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(908)=38 */ {908, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_38_l1}, +/*h(243)=39 */ {243, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_39_l1}, +/*h(942)=40 */ {942, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_40_l1}, +/*h(188)=41 */ {188, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_41_l1}, +/*h(654)=42 */ {654, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_42_l1}, +/*h(976)=43 */ {976, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_43_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1010)=46 */ {1010, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_46_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(722)=48 */ {722, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(900)=50 */ {900, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_50_l1}, +/*h(235)=51 */ {235, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_51_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(180)=53 */ {180, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_53_l1}, +/*h(646)=54 */ {646, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_54_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(968)=56 */ {968, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_56_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1002)=58 */ {1002, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_58_l1}, +/*h(248)=59 */ {248, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_59_l1}, +/*h(714)=60 */ {714, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_60_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(282)=62 */ {282, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_62_l1}, +/*h(604)=63 */ {604, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_63_l1}, +/*h(227)=64 */ {227, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_64_l1}, +/*h(172)=65 */ {172, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_65_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(350)=67 */ {350, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_67_l1}, +/*h(960)=68 */ {960, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_68_l1}, +/*h(439)=69 */ {439, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_69_l1}, +/*h(151)=70 */ {151, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_70_l1}, +/*h(240)=71 */ {240, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_71_l1}, +/*h(706)=72 */ {706, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_72_l1}, +/*h(795)=73 */ {795, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_73_l1}, +/*h(507)=74 */ {507, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_74_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(219)=76 */ {219, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_76_l1}, +/*h(164)=77 */ {164, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_77_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(863)=79 */ {863, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_79_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(431)=81 */ {431, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_81_l1}, +/*h(143)=82 */ {143, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_82_l1}, +/*h(232)=83 */ {232, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_83_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(499)=86 */ {499, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_86_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(211)=88 */ {211, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_88_l1}, +/*h(910)=89 */ {910, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_89_l1}, +/*h(156)=90 */ {156, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_90_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(190)=92 */ {190, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_92_l1}, +/*h(423)=93 */ {423, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_93_l1}, +/*h(135)=94 */ {135, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_94_l1}, +/*h(224)=95 */ {224, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25)=98 */ {25, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_98_l1}, +/*h(491)=99 */ {491, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_99_l1}, +/*h(203)=100 */ {203, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_100_l1}, +/*h(902)=101 */ {902, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_101_l1}, +/*h(148)=102 */ {148, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(703)=104 */ {703, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_104_l1}, +/*h(415)=105 */ {415, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_105_l1}, +/*h(504)=106 */ {504, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_106_l1}, +/*h(216)=107 */ {216, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(538)=109 */ {538, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_109_l1}, +/*h(250)=110 */ {250, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_110_l1}, +/*h(483)=111 */ {483, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_111_l1}, +/*h(195)=112 */ {195, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_112_l1}, +/*h(428)=113 */ {428, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_113_l1}, +/*h(140)=114 */ {140, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_114_l1}, +/*h(606)=115 */ {606, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_115_l1}, +/*h(695)=116 */ {695, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_116_l1}, +/*h(407)=117 */ {407, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_117_l1}, +/*h(496)=118 */ {496, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_118_l1}, +/*h(962)=119 */ {962, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_119_l1}, +/*h(208)=120 */ {208, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(763)=122 */ {763, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_122_l1}, +/*h(475)=123 */ {475, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(420)=125 */ {420, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_125_l1}, +/*h(132)=126 */ {132, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(687)=128 */ {687, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_128_l1}, +/*h(399)=129 */ {399, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_129_l1}, +/*h(488)=130 */ {488, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(200)=132 */ {200, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(755)=134 */ {755, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_134_l1}, +/*h(467)=135 */ {467, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_135_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(412)=137 */ {412, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(679)=140 */ {679, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_140_l1}, +/*h(391)=141 */ {391, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(480)=143 */ {480, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_143_l1}, +/*h(192)=144 */ {192, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_144_l1}, +/*h(281)=145 */ {281, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_145_l1}, +/*h(747)=146 */ {747, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_146_l1}, +/*h(459)=147 */ {459, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_147_l1}, +/*h(692)=148 */ {692, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_148_l1}, +/*h(404)=149 */ {404, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(959)=151 */ {959, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_151_l1}, +/*h(671)=152 */ {671, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_152_l1}, +/*h(760)=153 */ {760, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_153_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(472)=155 */ {472, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_155_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=158 */ {739, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_158_l1}, +/*h(451)=159 */ {451, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_159_l1}, +/*h(684)=160 */ {684, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_160_l1}, +/*h(396)=161 */ {396, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(951)=163 */ {951, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_163_l1}, +/*h(663)=164 */ {663, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_164_l1}, +/*h(142)=165 */ {142, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_165_l1}, +/*h(752)=166 */ {752, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_166_l1}, +/*h(464)=167 */ {464, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1019)=169 */ {1019, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_169_l1}, +/*h(731)=170 */ {731, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_170_l1}, +/*h(210)=171 */ {210, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_171_l1}, +/*h(676)=172 */ {676, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_172_l1}, +/*h(388)=173 */ {388, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(943)=175 */ {943, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_175_l1}, +/*h(422)=176 */ {422, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_176_l1}, +/*h(655)=177 */ {655, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_177_l1}, +/*h(744)=178 */ {744, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_178_l1}, +/*h(456)=179 */ {456, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1011)=181 */ {1011, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_181_l1}, +/*h(723)=182 */ {723, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_182_l1}, +/*h(202)=183 */ {202, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_183_l1}, +/*h(668)=184 */ {668, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(935)=187 */ {935, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_187_l1}, +/*h(414)=188 */ {414, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_188_l1}, +/*h(647)=189 */ {647, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_189_l1}, +/*h(736)=190 */ {736, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_190_l1}, +/*h(448)=191 */ {448, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_191_l1}, +/*h(537)=192 */ {537, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_192_l1}, +/*h(1003)=193 */ {1003, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_193_l1}, +/*h(715)=194 */ {715, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_194_l1}, +/*h(194)=195 */ {194, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_195_l1}, +/*h(660)=196 */ {660, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_196_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(605)=198 */ {605, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_198_l1}, +/*h(694)=199 */ {694, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_199_l1}, +/*h(927)=200 */ {927, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_200_l1}, +/*h(1016)=201 */ {1016, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_201_l1}, +/*h(728)=202 */ {728, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_202_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(995)=205 */ {995, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_205_l1}, +/*h(474)=206 */ {474, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_206_l1}, +/*h(707)=207 */ {707, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_207_l1}, +/*h(652)=208 */ {652, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(686)=211 */ {686, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_211_l1}, +/*h(919)=212 */ {919, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_212_l1}, +/*h(1008)=213 */ {1008, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_213_l1}, +/*h(720)=214 */ {720, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_214_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(987)=217 */ {987, xed3_phash_find_mapevex_map1_opcode0x5a_vv2_217_l1}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 218ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[104] = { +/*empty slot1 */ {0,0}, +/*h(29)=1 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {29, 6106}, +/*h(602)=2 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4215}, +/*h(30)=3 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {30, 6105}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(537)=6 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {537, 4182}, +/*h(89)=7 EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {89, 4219}, +/*h(538)=8 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {538, 4180}, +/*h(90)=9 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4218}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(473)=12 EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {473, 4321}, +/*h(25)=13 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {25, 4184}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(284)=16 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {284, 6108}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(543)=19 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {543, 6110}, +/*h(219)=20 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {219, 4316}, +/*empty slot1 */ {0,0}, +/*h(344)=22 EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {344, 4221}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=25 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {603, 4216}, +/*h(31)=26 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {31, 6110}, +/*h(728)=27 EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {728, 4317}, +/*h(280)=28 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {280, 4186}, +/*empty slot1 */ {0,0}, +/*h(987)=30 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {987, 4316}, +/*h(539)=31 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {539, 4181}, +/*h(91)=32 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {91, 4216}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(474)=35 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 4320}, +/*h(26)=36 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {26, 4183}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(285)=39 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {285, 6108}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(345)=45 EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {345, 4221}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(729)=50 EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {729, 4317}, +/*h(281)=51 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {281, 4186}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(540)=54 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {540, 6111}, +/*h(216)=55 EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {216, 4319}, +/*empty slot1 */ {0,0}, +/*h(799)=57 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {799, 6110}, +/*h(475)=58 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {475, 4316}, +/*h(27)=59 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {27, 4181}, +/*h(600)=60 EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {600, 4217}, +/*empty slot1 */ {0,0}, +/*h(286)=62 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {286, 6107}, +/*h(859)=63 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {859, 4216}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(346)=68 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4220}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(730)=73 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 4315}, +/*h(282)=74 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {282, 4185}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(541)=77 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {541, 6111}, +/*h(217)=78 EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {217, 4319}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(28)=82 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {28, 6106}, +/*h(601)=83 EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {601, 4217}, +/*empty slot1 */ {0,0}, +/*h(287)=85 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {287, 6110}, +/*empty slot1 */ {0,0}, +/*h(536)=87 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {536, 4182}, +/*h(88)=88 EVV 0x5B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {88, 4219}, +/*empty slot1 */ {0,0}, +/*h(795)=90 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {795, 4181}, +/*h(347)=91 EVV 0x5B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {347, 4216}, +/*empty slot1 */ {0,0}, +/*h(472)=93 EVV 0x5B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {472, 4321}, +/*h(24)=94 EVV 0x5B VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24, 4184}, +/*empty slot1 */ {0,0}, +/*h(731)=96 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {731, 4316}, +/*h(283)=97 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {283, 4181}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(542)=100 EVV 0x5B VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {542, 6109}, +/*h(218)=101 EVV 0x5B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 4318}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((23*key % 229) % 104); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 5961}, +/*h(46)=1 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5955}, +/*h(54)=2 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {54, 5964}, +/*h(24)=3 EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 5969}, +/*h(32)=4 EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 5963}, +/*h(78)=5 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5950}, +/*h(86)=6 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {86, 5964}, +/*h(56)=7 EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 5969}, +/*h(64)=8 EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 5959}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {118, 5964}, +/*h(88)=11 EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 5969}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 5951}, +/*h(23)=14 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {23, 5965}, +/*h(120)=15 EVV 0x5C VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 5969}, +/*h(1)=16 EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 5961}, +/*h(47)=17 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 5951}, +/*h(55)=18 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {55, 5965}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 5963}, +/*h(79)=21 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 5951}, +/*h(87)=22 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {87, 5965}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0x5C VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 5959}, +/*h(111)=25 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 5951}, +/*h(119)=26 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {119, 5965}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 5960}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {26, 5967}, +/*h(34)=36 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 5962}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {58, 5967}, +/*h(66)=40 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 5957}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {90, 5967}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {122, 5967}, +/*h(3)=48 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 5958}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 5968}, +/*h(35)=52 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 5958}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 5968}, +/*h(67)=56 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 5958}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 5968}, +/*h(99)=60 EVV 0x5C VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 5958}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0x5C VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 5968}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5954}, +/*h(20)=66 EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 5966}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5956}, +/*h(52)=70 EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 5966}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5952}, +/*h(84)=74 EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 5966}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0x5C VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 5966}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5954}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5956}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0x5C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5952}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0x5C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5953}, +/*h(22)=98 EVV 0x5C VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {22, 5964}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 4882}, +/*h(46)=1 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4876}, +/*h(54)=2 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {54, 4885}, +/*h(24)=3 EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 4890}, +/*h(32)=4 EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 4884}, +/*h(78)=5 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4871}, +/*h(86)=6 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {86, 4885}, +/*h(56)=7 EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 4890}, +/*h(64)=8 EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 4880}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {118, 4885}, +/*h(88)=11 EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 4890}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {15, 4872}, +/*h(23)=14 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {23, 4886}, +/*h(120)=15 EVV 0x5D VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 4890}, +/*h(1)=16 EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 4882}, +/*h(47)=17 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {47, 4872}, +/*h(55)=18 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {55, 4886}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 4884}, +/*h(79)=21 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {79, 4872}, +/*h(87)=22 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {87, 4886}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0x5D VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 4880}, +/*h(111)=25 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {111, 4872}, +/*h(119)=26 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {119, 4886}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 4881}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {26, 4888}, +/*h(34)=36 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 4883}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {58, 4888}, +/*h(66)=40 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 4878}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {90, 4888}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {122, 4888}, +/*h(3)=48 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {3, 4879}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {27, 4889}, +/*h(35)=52 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {35, 4879}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {59, 4889}, +/*h(67)=56 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {67, 4879}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {91, 4889}, +/*h(99)=60 EVV 0x5D VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {99, 4879}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0x5D VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {123, 4889}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4875}, +/*h(20)=66 EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 4887}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4877}, +/*h(52)=70 EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 4887}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4873}, +/*h(84)=74 EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 4887}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0x5D VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 4887}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4875}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4877}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0x5D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4873}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0x5D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4874}, +/*h(22)=98 EVV 0x5D VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {22, 4885}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 4406}, +/*h(46)=1 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4400}, +/*h(54)=2 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {54, 4409}, +/*h(24)=3 EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 4414}, +/*h(32)=4 EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 4408}, +/*h(78)=5 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4395}, +/*h(86)=6 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {86, 4409}, +/*h(56)=7 EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 4414}, +/*h(64)=8 EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 4404}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {118, 4409}, +/*h(88)=11 EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 4414}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {15, 4396}, +/*h(23)=14 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {23, 4410}, +/*h(120)=15 EVV 0x5E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 4414}, +/*h(1)=16 EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 4406}, +/*h(47)=17 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {47, 4396}, +/*h(55)=18 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {55, 4410}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 4408}, +/*h(79)=21 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {79, 4396}, +/*h(87)=22 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {87, 4410}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0x5E VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 4404}, +/*h(111)=25 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1*/ {111, 4396}, +/*h(119)=26 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W1*/ {119, 4410}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 4405}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {26, 4412}, +/*h(34)=36 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 4407}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {58, 4412}, +/*h(66)=40 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 4402}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {90, 4412}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {122, 4412}, +/*h(3)=48 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {3, 4403}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {27, 4413}, +/*h(35)=52 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {35, 4403}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {59, 4413}, +/*h(67)=56 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {67, 4403}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {91, 4413}, +/*h(99)=60 EVV 0x5E VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0*/ {99, 4403}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0x5E VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() W0*/ {123, 4413}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4399}, +/*h(20)=66 EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 4411}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4401}, +/*h(52)=70 EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 4411}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4397}, +/*h(84)=74 EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 4411}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0x5E VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 4411}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4399}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4401}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0x5E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4397}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0x5E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4398}, +/*h(22)=98 EVV 0x5E VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {22, 4409}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x5f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {0, 4862}, +/*h(46)=1 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 4856}, +/*h(54)=2 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {54, 4865}, +/*h(24)=3 EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 4870}, +/*h(32)=4 EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {32, 4864}, +/*h(78)=5 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 4851}, +/*h(86)=6 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {86, 4865}, +/*h(56)=7 EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 4870}, +/*h(64)=8 EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {64, 4860}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {118, 4865}, +/*h(88)=11 EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 4870}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {15, 4852}, +/*h(23)=14 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {23, 4866}, +/*h(120)=15 EVV 0x5F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 4870}, +/*h(1)=16 EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {1, 4862}, +/*h(47)=17 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {47, 4852}, +/*h(55)=18 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {55, 4866}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {33, 4864}, +/*h(79)=21 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {79, 4852}, +/*h(87)=22 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {87, 4866}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0x5F VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {65, 4860}, +/*h(111)=25 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1*/ {111, 4852}, +/*h(119)=26 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1*/ {119, 4866}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {2, 4861}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {26, 4868}, +/*h(34)=36 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {34, 4863}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {58, 4868}, +/*h(66)=40 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {66, 4858}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {90, 4868}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0*/ {122, 4868}, +/*h(3)=48 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {3, 4859}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {27, 4869}, +/*h(35)=52 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {35, 4859}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {59, 4869}, +/*h(67)=56 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {67, 4859}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {91, 4869}, +/*h(99)=60 EVV 0x5F VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0*/ {99, 4859}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0x5F VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0*/ {123, 4869}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 4855}, +/*h(20)=66 EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 4867}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 4857}, +/*h(52)=70 EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 4867}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 4853}, +/*h(84)=74 EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 4867}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0x5F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 4867}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 4855}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 4857}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0x5F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 4853}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0x5F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 4854}, +/*h(22)=98 EVV 0x5F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1*/ {22, 4865}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x60_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6752}, +/*h(4)=1 EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6751}, +/*h(38)=2 EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6754}, +/*h(20)=3 EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6753}, +/*h(6)=4 EVV 0x60 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6750}, +/*h(36)=5 EVV 0x60 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6755} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x61_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6758}, +/*h(4)=1 EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6757}, +/*h(38)=2 EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6760}, +/*h(20)=3 EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6759}, +/*h(6)=4 EVV 0x61 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6756}, +/*h(36)=5 EVV 0x61 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6761} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x62_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5795}, +/*h(10)=3 EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5796}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5799}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5795}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5797}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5799}, +/*h(74)=13 EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5794}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x62 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5797}, +/*h(42)=17 EVV 0x62 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5798} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x63_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6256}, +/*h(4)=1 EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6255}, +/*h(38)=2 EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6258}, +/*h(20)=3 EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6257}, +/*h(6)=4 EVV 0x63 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6254}, +/*h(36)=5 EVV 0x63 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x64_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0*/ {22, 6376}, +/*h(4)=1 EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6375}, +/*h(38)=2 EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0*/ {38, 6378}, +/*h(20)=3 EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6377}, +/*h(6)=4 EVV 0x64 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0*/ {6, 6374}, +/*h(36)=5 EVV 0x64 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x65_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0*/ {22, 6382}, +/*h(4)=1 EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6381}, +/*h(38)=2 EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0*/ {38, 6384}, +/*h(20)=3 EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6383}, +/*h(6)=4 EVV 0x65 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0*/ {6, 6380}, +/*h(36)=5 EVV 0x65 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x66_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5171}, +/*h(10)=3 EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {10, 5172}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5175}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5171}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5173}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5175}, +/*h(74)=13 EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {74, 5170}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x66 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5173}, +/*h(42)=17 EVV 0x66 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {42, 5174} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x67_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6268}, +/*h(4)=1 EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6267}, +/*h(38)=2 EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6270}, +/*h(20)=3 EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6269}, +/*h(6)=4 EVV 0x67 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6266}, +/*h(36)=5 EVV 0x67 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6271} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x68_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6740}, +/*h(4)=1 EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6739}, +/*h(38)=2 EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6742}, +/*h(20)=3 EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6741}, +/*h(6)=4 EVV 0x68 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6738}, +/*h(36)=5 EVV 0x68 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6743} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x69_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6746}, +/*h(4)=1 EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6745}, +/*h(38)=2 EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6748}, +/*h(20)=3 EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6747}, +/*h(6)=4 EVV 0x69 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6744}, +/*h(36)=5 EVV 0x69 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6749} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5783}, +/*h(10)=3 EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5784}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5787}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5783}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5785}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5787}, +/*h(74)=13 EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5782}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x6A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5785}, +/*h(42)=17 EVV 0x6A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5786} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6b_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 6253}, +/*h(10)=3 EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 6248}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 6251}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 6253}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 6249}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 6251}, +/*h(74)=13 EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 6252}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x6B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 6249}, +/*h(42)=17 EVV 0x6B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 6250} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6c_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5801}, +/*h(46)=1 EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5804}, +/*h(12)=2 EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5803}, +/*h(77)=3 EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5801}, +/*h(13)=4 EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5803}, +/*h(78)=5 EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5800}, +/*h(44)=6 EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5805}, +/*h(14)=7 EVV 0x6C V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5802}, +/*h(45)=8 EVV 0x6C V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5805} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6d_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5789}, +/*h(46)=1 EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5792}, +/*h(12)=2 EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5791}, +/*h(77)=3 EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5789}, +/*h(13)=4 EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5791}, +/*h(78)=5 EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5788}, +/*h(44)=6 EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5793}, +/*h(14)=7 EVV 0x6D V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5790}, +/*h(45)=8 EVV 0x6D V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5793} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(746)=0 EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {746, 4917}, +/*h(738)=1 EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {738, 4917}, +/*empty slot1 */ {0,0}, +/*h(722)=3 EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {722, 4918}, +/*h(714)=4 EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {714, 4917}, +/*h(706)=5 EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER()*/ {706, 4917}, +/*empty slot1 */ {0,0}, +/*h(758)=7 EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0*/ {758, 4999}, +/*h(750)=8 EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {750, 4915}, +/*h(742)=9 EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {742, 4915}, +/*empty slot1 */ {0,0}, +/*h(726)=11 EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0*/ {726, 4916}, +/*h(718)=12 EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {718, 4915}, +/*h(710)=13 EVV 0x6E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {710, 4915}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(754)=16 EVV 0x6E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER()*/ {754, 5000} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x6f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[59] = { +/*h(472)=0 EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {472, 4962}, +/*h(728)=1 EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {728, 4954}, +/*h(158)=2 EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {158, 6200}, +/*h(414)=3 EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {414, 6204}, +/*h(670)=4 EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {670, 6208}, +/*h(218)=5 EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 4957}, +/*h(474)=6 EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 4961}, +/*h(730)=7 EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 4953}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(220)=11 EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {220, 4970}, +/*h(476)=12 EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {476, 4974}, +/*h(732)=13 EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {732, 4966}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(222)=17 EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {222, 4969}, +/*h(478)=18 EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {478, 4973}, +/*h(734)=19 EVV 0x6F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {734, 4965}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=28 EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {88, 4934}, +/*h(344)=29 EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {344, 4938}, +/*h(600)=30 EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {600, 4930}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=34 EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4933}, +/*h(346)=35 EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4937}, +/*h(602)=36 EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4929}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=40 EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {92, 4946}, +/*h(348)=41 EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {348, 4950}, +/*h(604)=42 EVV 0x6F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULLMEM()*/ {604, 4942}, +/*h(152)=43 EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {152, 6213}, +/*h(408)=44 EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {408, 6217}, +/*h(664)=45 EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ESIZE_8_BITS() NELEM_FULLMEM()*/ {664, 6221}, +/*h(94)=46 EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4945}, +/*h(350)=47 EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4949}, +/*h(606)=48 EVV 0x6F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4941}, +/*h(154)=49 EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {154, 6212}, +/*h(410)=50 EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {410, 6216}, +/*h(666)=51 EVV 0x6F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {666, 6220}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(156)=55 EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {156, 6201}, +/*h(412)=56 EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {412, 6205}, +/*h(668)=57 EVV 0x6F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ESIZE_16_BITS() NELEM_FULLMEM()*/ {668, 6209}, +/*h(216)=58 EVV 0x6F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULLMEM()*/ {216, 4958} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 59); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x70_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[59] = { +/*h(472)=0 EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {472, 6603}, +/*h(728)=1 EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {728, 6605}, +/*h(158)=2 EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()*/ {158, 6606}, +/*h(414)=3 EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()*/ {414, 6608}, +/*h(670)=4 EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()*/ {670, 6610}, +/*h(218)=5 EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()*/ {218, 6600}, +/*h(474)=6 EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()*/ {474, 6602}, +/*h(730)=7 EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()*/ {730, 6604}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(220)=11 EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {220, 6601}, +/*h(476)=12 EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {476, 6603}, +/*h(732)=13 EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {732, 6605}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(222)=17 EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()*/ {222, 6600}, +/*h(478)=18 EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()*/ {478, 6602}, +/*h(734)=19 EVV 0x70 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()*/ {734, 6604}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=28 EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 5623}, +/*h(344)=29 EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 5625}, +/*h(600)=30 EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 5621}, +/*h(89)=31 EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 5623}, +/*h(345)=32 EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 5625}, +/*h(601)=33 EVV 0x70 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 5621}, +/*h(90)=34 EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR UIMM8()*/ {90, 5622}, +/*h(346)=35 EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR UIMM8()*/ {346, 5624}, +/*h(602)=36 EVV 0x70 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR UIMM8()*/ {602, 5620}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=43 EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {152, 6607}, +/*h(408)=44 EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {408, 6609}, +/*h(664)=45 EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {664, 6611}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(154)=49 EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR UIMM8()*/ {154, 6606}, +/*h(410)=50 EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 NOEVSR UIMM8()*/ {410, 6608}, +/*h(666)=51 EVV 0x70 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 NOEVSR UIMM8()*/ {666, 6610}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(156)=55 EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {156, 6607}, +/*h(412)=56 EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {412, 6609}, +/*h(668)=57 EVV 0x70 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {668, 6611}, +/*h(216)=58 EVV 0x70 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 NOEVSR UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {216, 6601} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 59); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x71_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(306)=0 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 UIMM8()*/ {306, 6652}, +/*h(184)=1 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {184, 6631}, +/*h(186)=2 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 UIMM8()*/ {186, 6630}, +/*h(168)=3 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {168, 6673}, +/*h(170)=4 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 UIMM8()*/ {170, 6672}, +/*h(48)=5 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {48, 6645}, +/*h(304)=6 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {304, 6653}, +/*h(58)=7 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 UIMM8()*/ {58, 6626}, +/*h(314)=8 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 UIMM8()*/ {314, 6634}, +/*h(42)=9 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 UIMM8()*/ {42, 6668}, +/*h(298)=10 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 UIMM8()*/ {298, 6676}, +/*h(176)=11 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] BCRC=0 MODRM() VL256 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {176, 6649}, +/*h(178)=12 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 UIMM8()*/ {178, 6648}, +/*h(56)=13 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {56, 6627}, +/*h(312)=14 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {312, 6635}, +/*h(40)=15 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL128 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {40, 6669}, +/*h(296)=16 EVV 0x71 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] BCRC=0 MODRM() VL512 UIMM8() ESIZE_16_BITS() NELEM_FULLMEM()*/ {296, 6677}, +/*h(50)=17 EVV 0x71 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 UIMM8()*/ {50, 6644} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REG_VEX_PREFIX_VL(d); +hidx = ((24*key % 101) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x72_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[144] = { +/*h(585)=0 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {585, 5701}, +/*h(601)=1 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {601, 5629}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(64)=4 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {64, 5587}, +/*h(80)=5 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {80, 5669}, +/*h(96)=6 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {96, 5593}, +/*h(112)=7 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {112, 5681}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(586)=12 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W0 UIMM8()*/ {586, 5700}, +/*h(602)=13 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W0 UIMM8()*/ {602, 5628}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(65)=16 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {65, 5587}, +/*h(81)=17 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {81, 5669}, +/*h(97)=18 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {97, 5593}, +/*h(113)=19 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {113, 5681}, +/*h(320)=20 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {320, 5589}, +/*h(336)=21 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {336, 5673}, +/*h(352)=22 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {352, 5595}, +/*h(368)=23 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {368, 5685}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(66)=28 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W0 UIMM8()*/ {66, 5586}, +/*h(82)=29 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W0 UIMM8()*/ {82, 5668}, +/*h(98)=30 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL128 W1 UIMM8()*/ {98, 5592}, +/*h(114)=31 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL128 W1 UIMM8()*/ {114, 5680}, +/*h(321)=32 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {321, 5589}, +/*h(337)=33 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {337, 5673}, +/*h(353)=34 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {353, 5595}, +/*h(369)=35 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {369, 5685}, +/*h(576)=36 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {576, 5585}, +/*h(592)=37 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {592, 5665}, +/*h(608)=38 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {608, 5591}, +/*h(624)=39 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {624, 5677}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(322)=44 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W0 UIMM8()*/ {322, 5588}, +/*h(338)=45 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W0 UIMM8()*/ {338, 5672}, +/*h(354)=46 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL256 W1 UIMM8()*/ {354, 5594}, +/*h(370)=47 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL256 W1 UIMM8()*/ {370, 5684}, +/*h(577)=48 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {577, 5585}, +/*h(593)=49 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {593, 5665}, +/*h(609)=50 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {609, 5591}, +/*h(625)=51 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {625, 5677}, +/*h(68)=52 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {68, 5563}, +/*empty slot1 */ {0,0}, +/*h(100)=54 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {100, 5569}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(578)=60 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W0 UIMM8()*/ {578, 5584}, +/*h(594)=61 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W0 UIMM8()*/ {594, 5664}, +/*h(610)=62 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b000] RM[nnn] VL512 W1 UIMM8()*/ {610, 5590}, +/*h(626)=63 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b100] RM[nnn] VL512 W1 UIMM8()*/ {626, 5676}, +/*h(69)=64 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {69, 5563}, +/*empty slot1 */ {0,0}, +/*h(101)=66 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {101, 5569}, +/*empty slot1 */ {0,0}, +/*h(324)=68 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {324, 5565}, +/*empty slot1 */ {0,0}, +/*h(356)=70 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {356, 5571}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(70)=76 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W0 UIMM8()*/ {70, 5562}, +/*empty slot1 */ {0,0}, +/*h(102)=78 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL128 W1 UIMM8()*/ {102, 5568}, +/*empty slot1 */ {0,0}, +/*h(325)=80 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {325, 5565}, +/*empty slot1 */ {0,0}, +/*h(357)=82 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {357, 5571}, +/*empty slot1 */ {0,0}, +/*h(580)=84 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {580, 5561}, +/*empty slot1 */ {0,0}, +/*h(612)=86 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {612, 5567}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(326)=92 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W0 UIMM8()*/ {326, 5564}, +/*empty slot1 */ {0,0}, +/*h(358)=94 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL256 W1 UIMM8()*/ {358, 5570}, +/*empty slot1 */ {0,0}, +/*h(581)=96 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {581, 5561}, +/*empty slot1 */ {0,0}, +/*h(613)=98 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {613, 5567}, +/*empty slot1 */ {0,0}, +/*h(72)=100 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {72, 5705}, +/*h(88)=101 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {88, 5633}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(582)=108 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W0 UIMM8()*/ {582, 5560}, +/*empty slot1 */ {0,0}, +/*h(614)=110 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b001] RM[nnn] VL512 W1 UIMM8()*/ {614, 5566}, +/*empty slot1 */ {0,0}, +/*h(73)=112 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {73, 5705}, +/*h(89)=113 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {89, 5633}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(328)=116 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {328, 5709}, +/*h(344)=117 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {344, 5637}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(74)=124 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W0 UIMM8()*/ {74, 5704}, +/*h(90)=125 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W0 UIMM8()*/ {90, 5632}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(329)=128 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {329, 5709}, +/*h(345)=129 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {345, 5637}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(584)=132 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {584, 5701}, +/*h(600)=133 EVV 0x72 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {600, 5629}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(330)=140 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W0 UIMM8()*/ {330, 5708}, +/*h(346)=141 EVV 0x72 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W0 UIMM8()*/ {346, 5636}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REG_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 191) % 144); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x73_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[192] = { +/*h(3281)=0 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3281, 5713}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3282)=3 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3282, 5713}, +/*empty slot1 */ {0,0}, +/*h(2768)=5 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2768, 5721}, +/*h(3283)=6 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3283, 5713}, +/*empty slot1 */ {0,0}, +/*h(2769)=8 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2769, 5721}, +/*h(3284)=9 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8()*/ {3284, 5712}, +/*empty slot1 */ {0,0}, +/*h(2770)=11 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2770, 5721}, +/*empty slot1 */ {0,0}, +/*h(2256)=13 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2256, 5717}, +/*h(2771)=14 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2771, 5721}, +/*h(3286)=15 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8()*/ {3286, 5712}, +/*h(2257)=16 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2257, 5717}, +/*h(2772)=17 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8()*/ {2772, 5720}, +/*empty slot1 */ {0,0}, +/*h(2258)=19 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2258, 5717}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2259)=22 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2259, 5717}, +/*h(2774)=23 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8()*/ {2774, 5720}, +/*empty slot1 */ {0,0}, +/*h(2260)=25 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8()*/ {2260, 5716}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1232)=29 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1232, 5713}, +/*empty slot1 */ {0,0}, +/*h(2262)=31 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8()*/ {2262, 5716}, +/*h(1233)=32 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1233, 5713}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1234)=35 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1234, 5713}, +/*empty slot1 */ {0,0}, +/*h(720)=37 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {720, 5721}, +/*h(1235)=38 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1235, 5713}, +/*empty slot1 */ {0,0}, +/*h(721)=40 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {721, 5721}, +/*h(1236)=41 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8()*/ {1236, 5712}, +/*empty slot1 */ {0,0}, +/*h(722)=43 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {722, 5721}, +/*empty slot1 */ {0,0}, +/*h(208)=45 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {208, 5717}, +/*h(723)=46 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {723, 5721}, +/*h(1238)=47 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL512 W1 UIMM8()*/ {1238, 5712}, +/*h(209)=48 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {209, 5717}, +/*h(724)=49 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8()*/ {724, 5720}, +/*empty slot1 */ {0,0}, +/*h(210)=51 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {210, 5717}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(211)=54 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {211, 5717}, +/*h(726)=55 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL256 W1 UIMM8()*/ {726, 5720}, +/*empty slot1 */ {0,0}, +/*h(212)=57 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8()*/ {212, 5716}, +/*empty slot1 */ {0,0}, +/*h(1242)=59 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {1242, 6659}, +/*h(1178)=60 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {1178, 6659}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(214)=63 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b010] RM[nnn] VL128 W1 UIMM8()*/ {214, 5716}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(730)=67 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {730, 6657}, +/*h(666)=68 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {666, 6657}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1246)=71 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()*/ {1246, 6658}, +/*h(1182)=72 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()*/ {1182, 6658}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(218)=75 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {218, 6655}, +/*h(154)=76 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b011] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {154, 6655}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(734)=79 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()*/ {734, 6656}, +/*h(670)=80 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()*/ {670, 6656}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(222)=87 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {222, 6654}, +/*h(158)=88 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b011] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {158, 6654}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3312)=93 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3312, 5641}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3313)=96 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3313, 5641}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3314)=99 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3314, 5641}, +/*empty slot1 */ {0,0}, +/*h(2800)=101 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2800, 5649}, +/*h(3315)=102 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3315, 5641}, +/*empty slot1 */ {0,0}, +/*h(2801)=104 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2801, 5649}, +/*h(3316)=105 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8()*/ {3316, 5640}, +/*empty slot1 */ {0,0}, +/*h(2802)=107 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2802, 5649}, +/*empty slot1 */ {0,0}, +/*h(2288)=109 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2288, 5645}, +/*h(2803)=110 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2803, 5649}, +/*h(3318)=111 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8()*/ {3318, 5640}, +/*h(2289)=112 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2289, 5645}, +/*h(2804)=113 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8()*/ {2804, 5648}, +/*empty slot1 */ {0,0}, +/*h(2290)=115 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2290, 5645}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2291)=118 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {2291, 5645}, +/*h(2806)=119 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8()*/ {2806, 5648}, +/*empty slot1 */ {0,0}, +/*h(2292)=121 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8()*/ {2292, 5644}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1264)=125 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1264, 5641}, +/*empty slot1 */ {0,0}, +/*h(2294)=127 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8()*/ {2294, 5644}, +/*h(1265)=128 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1265, 5641}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1266)=131 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1266, 5641}, +/*empty slot1 */ {0,0}, +/*h(752)=133 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {752, 5649}, +/*h(1267)=134 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {1267, 5641}, +/*empty slot1 */ {0,0}, +/*h(753)=136 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {753, 5649}, +/*h(1268)=137 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8()*/ {1268, 5640}, +/*empty slot1 */ {0,0}, +/*h(754)=139 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {754, 5649}, +/*empty slot1 */ {0,0}, +/*h(240)=141 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {240, 5645}, +/*h(755)=142 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {755, 5649}, +/*h(1270)=143 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL512 W1 UIMM8()*/ {1270, 5640}, +/*h(241)=144 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {241, 5645}, +/*h(756)=145 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8()*/ {756, 5648}, +/*empty slot1 */ {0,0}, +/*h(242)=147 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {242, 5645}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(243)=150 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {243, 5645}, +/*h(758)=151 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL256 W1 UIMM8()*/ {758, 5648}, +/*empty slot1 */ {0,0}, +/*h(244)=153 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8()*/ {244, 5644}, +/*empty slot1 */ {0,0}, +/*h(1274)=155 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {1274, 6617}, +/*h(1210)=156 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {1210, 6617}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(246)=159 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b110] RM[nnn] VL128 W1 UIMM8()*/ {246, 5644}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(762)=163 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {762, 6615}, +/*h(698)=164 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {698, 6615}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1278)=167 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()*/ {1278, 6616}, +/*h(1214)=168 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL512 ZEROING=0 MASK=0 UIMM8()*/ {1214, 6616}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(250)=171 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {250, 6613}, +/*h(186)=172 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b111] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_8_BITS() NELEM_FULLMEM()*/ {186, 6613}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(766)=175 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()*/ {766, 6614}, +/*h(702)=176 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL256 ZEROING=0 MASK=0 UIMM8()*/ {702, 6614}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(254)=183 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {254, 6612}, +/*h(190)=184 EVV 0x73 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[0b111] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {190, 6612}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(3280)=190 EVV 0x73 V66 V0F MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {3280, 5713}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REG_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 193) % 192); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x74_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0*/ {22, 6364}, +/*h(4)=1 EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6363}, +/*h(38)=2 EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0*/ {38, 6366}, +/*h(20)=3 EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6365}, +/*h(6)=4 EVV 0x74 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0*/ {6, 6362}, +/*h(36)=5 EVV 0x74 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6367} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x75_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0*/ {22, 6370}, +/*h(4)=1 EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6369}, +/*h(38)=2 EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0*/ {38, 6372}, +/*h(20)=3 EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6371}, +/*h(6)=4 EVV 0x75 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0*/ {6, 6368}, +/*h(36)=5 EVV 0x75 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6373} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x76_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5159}, +/*h(10)=3 EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0*/ {10, 5160}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5163}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5159}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5161}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5163}, +/*h(74)=13 EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0*/ {74, 5158}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0x76 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5161}, +/*h(42)=17 EVV 0x76 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0*/ {42, 5162} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8644)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25028)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8676)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8676, 4308}, +/*h(4495)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4495, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25060)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25060, 4308}, +/*h(20879)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20879, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8652)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25036)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8684)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8684, 4308}, +/*h(4503)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4503, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1303_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25068)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25068, 4308}, +/*h(20887)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20887, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8660)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8660; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25044)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25044; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8692)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8692, 4308}, +/*h(9679)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9679, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25076)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25076; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8646)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25030)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_444_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8678)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8678, 4308}, +/*h(4497)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4497, 4328}, +/*h(9665)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9665, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20881)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20881, 4328}, +/*h(25062)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25062, 4308}, +/*h(26049)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26049, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8654)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25038)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8686)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8686, 4308}, +/*h(9673)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9673, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25070)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25070, 4308}, +/*h(26057)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26057, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4481)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4481, 4328}, +/*h(8662)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8662, 4308}, +/*h(9649)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9649, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25046)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25046, 4308}, +/*h(20865)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20865, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9681)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9681, 6125}, +/*h(4513)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4513, 4328}, +/*h(8694)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8694, 4308} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25078)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25078, 4308}, +/*h(20897)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20897, 4328}, +/*h(26065)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26065, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(453)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16837)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_649_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5536)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5536, 6136}, +/*h(9717)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9717, 6124}, +/*h(4549)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4549, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20933)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20933, 4309}, +/*h(26101)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {26101, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8645)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8645, 4309}, +/*h(13813)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13813, 6124}, +/*h(9632)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9632, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26016)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26016, 6139}, +/*h(30197)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30197, 6124}, +/*h(25029)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25029, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11754)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11754, 4360}, +/*h(12741)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12741, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1455)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1455, 6138}, +/*h(468)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {468, 4311}, +/*h(29125)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29125, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(485)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {485, 4309}, +/*h(24961)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24961, 4324}, +/*h(1472)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1472, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16869)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(400)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {400, 4326}, +/*h(4581)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4581, 4309}, +/*h(5568)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5568, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20965)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20965, 4309}, +/*h(21952)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21952, 6122}, +/*h(16784)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16784, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4496)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4496, 4328}, +/*h(8677)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8677, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25061)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8592)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8592, 4324}, +/*h(12773)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12773, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29157)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29157, 4309}, +/*h(24976)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24976, 4324}, +/*h(500)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {500, 4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(461)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16845)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_566_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5544)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5544, 6136}, +/*h(4557)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4557, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20941)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9640)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9640, 6139}, +/*h(8653)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8653, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1066_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26024)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26024, 6139}, +/*h(25037)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25037, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12749)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29133)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1027_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1480)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1480, 6120}, +/*h(493)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {493, 4309}, +/*h(24969)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24969, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_832_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17864)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17864, 6120}, +/*h(16877)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16877, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4589)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21960)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21960, 6122}, +/*h(20973)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20973, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8685)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25069)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12781)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29165)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(469)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16853)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4565)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4565, 4309}, +/*h(5552)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5552, 6136}, +/*h(384)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {384, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21936)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21936, 6136}, +/*h(16768)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16768, 4326}, +/*h(20949)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20949, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8661)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_983_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25045)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25045, 4309}, +/*h(26032)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26032, 6139}, +/*h(20864)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20864, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8576)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8576, 4324}, +/*h(12757)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12757, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(484)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {484, 4311}, +/*h(29141)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29141, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(24977)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24977, 4324}, +/*h(501)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {501, 4309}, +/*h(1488)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1488, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_749_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17872)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17872, 6120}, +/*h(16885)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16885, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4597)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20981)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_847_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4512)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4512, 4328}, +/*h(8693)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8693, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20896)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20896, 4328}, +/*h(25077)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25077, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8608)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8608, 4324}, +/*h(12789)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12789, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1347_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24992)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24992, 4324}, +/*h(29173)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29173, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(455)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {455, 4309}, +/*h(5623)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5623, 6124}, +/*h(1442)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1442, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16839)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16839, 4309}, +/*h(22007)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {22007, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4551)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4551, 4309}, +/*h(5538)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5538, 6136}, +/*h(9719)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9719, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_805_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26103)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {26103, 6124}, +/*h(21922)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21922, 6136}, +/*h(20935)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20935, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3479)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 4359}, +/*h(8647)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8647, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25031)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_903_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7575)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7575, 4359}, +/*h(12743)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12743, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(470)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {470, 4311}, +/*h(29127)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29127, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(487)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17858)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17858, 6120}, +/*h(16871)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16871, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(402)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {402, 4326}, +/*h(4583)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4583, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20967)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4498)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4498, 4328}, +/*h(8679)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8679, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20882)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20882, 4328}, +/*h(25063)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25063, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8594)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8594, 4324}, +/*h(12775)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12775, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(24978)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24978, 4324}, +/*h(502)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {502, 4311}, +/*h(29159)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29159, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1450)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1450, 6134}, +/*h(463)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {463, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17834)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17834, 6134}, +/*h(16847)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16847, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4559)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_722_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21930)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21930, 6136}, +/*h(20943)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20943, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8655)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25039)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12751)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29135)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(495)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17866)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17866, 6120}, +/*h(16879)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16879, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4591)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20975)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8687)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25071)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12783)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29167)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29167; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1458)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1458, 6134}, +/*h(471)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {471, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1432_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17842)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17842, 6134}, +/*h(16855)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16855, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4567)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_639_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16770)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16770, 4326}, +/*h(20951)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20951, 4309}, +/*h(21938)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21938, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4482)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4482, 4328}, +/*h(3495)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3495, 4358}, +/*h(8663)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8663, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1335_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20866)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20866, 4328}, +/*h(25047)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25047, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_737_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8578)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8578, 4324}, +/*h(12759)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12759, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(486)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {486, 4311}, +/*h(29143)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29143, 4309}, +/*h(24962)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24962, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(503)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {503, 4309}, +/*h(24979)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24979, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16887)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {16887, 4309}, +/*h(11719)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {11719, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(418)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {418, 4326}, +/*h(4599)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {4599, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16802)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16802, 4326}, +/*h(15815)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {15815, 4358}, +/*h(20983)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {20983, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4514)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4514, 4328}, +/*h(8695)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {8695, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20898)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20898, 4328}, +/*h(25079)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {25079, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8610)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8610, 4324}, +/*h(12791)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {12791, 4309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29175)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {29175, 4309}, +/*h(24994)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24994, 4324}, +/*h(1505)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1505, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8640)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25024)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8672)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_683_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25056)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25056, 4310}, +/*h(20875)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20875, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8648)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8648, 4310}, +/*h(9635)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9635, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_932_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25032)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25032, 4310}, +/*h(26019)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26019, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8680)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26051)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26051, 6125}, +/*h(20883)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20883, 4328}, +/*h(25064)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25064, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1044_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8656)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8656, 4310}, +/*h(9643)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9643, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25040)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25040, 4310}, +/*h(26027)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26027, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_713_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8688)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25072)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8642)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25026)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8674)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8674, 4310}, +/*h(4493)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4493, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25058)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25058, 4310}, +/*h(20877)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20877, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8650)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8650, 4310}, +/*h(7663)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {7663, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25034)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25034, 4310}, +/*h(26021)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {26021, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8682)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8682, 4310}, +/*h(4501)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4501, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25066)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25066, 4310}, +/*h(20885)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20885, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8658)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8658, 4310}, +/*h(3490)=1 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3490, 4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25042)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1064_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3522)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3522, 4360}, +/*h(8690)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8690, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25074)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8641)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25025)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4492)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4492, 4327}, +/*h(8673)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8673, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20876)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20876, 4327}, +/*h(25057)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25057, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8649)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25033)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4500)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4500, 4327}, +/*h(8681)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8681, 4310}, +/*h(9668)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9668, 6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20884)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20884, 4327}, +/*h(25065)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25065, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8657)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25041)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9676)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9676, 6123}, +/*h(8689)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8689, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26060)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26060, 6123}, +/*h(25073)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25073, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8643)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25027)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4494)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4494, 4327}, +/*h(8675)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8675, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20878)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20878, 4327}, +/*h(25059)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25059, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_910_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9638)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9638, 6137}, +/*h(8651)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8651, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25035)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8683)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20886)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20886, 4327}, +/*h(25067)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25067, 4310}, +/*h(26054)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26054, 6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9646)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9646, 6137}, +/*h(8659)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8659, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25043)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8691)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26062)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26062, 6123}, +/*h(25075)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25075, 4310} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29109)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29109, 4323}, +/*h(5620)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5620, 6121}, +/*h(452)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {452, 4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16836)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16836, 4311}, +/*h(22004)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {22004, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16868)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(460)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {460, 4311}, +/*h(1447)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1447, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16844)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16844, 4311}, +/*h(17831)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17831, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(492)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {492, 4311}, +/*h(24968)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24968, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16876)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16852)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16852, 4311}, +/*h(17839)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17839, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16884)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(454)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {454, 4311}, +/*h(29111)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29111, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_678_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(17825)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17825, 6134}, +/*h(22006)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {22006, 6121}, +/*h(16838)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16838, 4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16870)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(462)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16846)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(494)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {494, 4311}, +/*h(24970)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24970, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16878)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16854)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16854, 4311}, +/*h(11686)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {11686, 4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11718)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {11718, 4356}, +/*h(16886)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16886, 4311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(448)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16832)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16864)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(456)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16840)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(488)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {488, 4312}, +/*h(24964)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24964, 4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16872)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(464)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16848)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_810_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(24972)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24972, 4322}, +/*h(496)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {496, 4312}, +/*h(1483)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1483, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16880)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {450, 4312}, +/*h(5618)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5618, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1464_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11666)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {11666, 4361}, +/*h(16834)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16834, 4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(482)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16866)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16866, 4312}, +/*h(12685)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12685, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(458)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16842)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(490)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {490, 4312}, +/*h(24966)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24966, 4322}, +/*h(1477)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1477, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1049_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(17861)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {17861, 6124}, +/*h(12693)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12693, 4323}, +/*h(16874)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16874, 4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(466)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {466, 4312}, +/*h(1453)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1453, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16850)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(498)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16882)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16882, 4312}, +/*h(17869)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {17869, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_739_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(30093)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30093, 6138}, +/*h(5617)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5617, 6122}, +/*h(449)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {449, 4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16833)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16833, 4312}, +/*h(22001)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {22001, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(481)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16865)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(457)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17828)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17828, 6133}, +/*h(16841)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16841, 4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(489)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {489, 4312}, +/*h(24965)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24965, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16873)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(465)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17836)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17836, 6133}, +/*h(16849)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16849, 4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(497)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {497, 4312}, +/*h(24973)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24973, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16881)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1091_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(451)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16835)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16867)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(459)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16843)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(491)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {491, 4312}, +/*h(24967)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24967, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16875)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(467)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16851)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24975)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24975, 4323}, +/*h(499)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {499, 4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16883)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4312} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4548)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26100)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26100, 6123}, +/*h(20932)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20932, 4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4580)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4580, 4313}, +/*h(399)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {399, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20964)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20964, 4313}, +/*h(16783)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16783, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4556)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4556; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20940)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_803_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4588)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4588, 4313}, +/*h(407)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {407, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20972)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20972, 4313}, +/*h(16791)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16791, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4564)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4564; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20948)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20948; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4596)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20980)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4550)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20934)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20934, 4313}, +/*h(15766)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {15766, 4357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4582)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4582, 4313}, +/*h(401)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {401, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1042_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20966)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20966, 4313}, +/*h(16785)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16785, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4558)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20942)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4590)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4590, 4313}, +/*h(5577)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5577, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20974)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4566)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4566, 4313}, +/*h(385)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {385, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20950)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20950, 4313}, +/*h(15782)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15782, 4356}, +/*h(16769)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16769, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4598)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4598, 4313}, +/*h(5585)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5585, 6122}, +/*h(417)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {417, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_876_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20982)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20982, 4313}, +/*h(16801)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16801, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4544)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20928)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4576)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4576, 4314}, +/*h(395)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {395, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1476_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20960)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20960, 4314}, +/*h(16779)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16779, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4552)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4552; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20936)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5571)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5571, 6122}, +/*h(403)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {403, 4326}, +/*h(4584)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4584, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21955)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21955, 6122}, +/*h(20968)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20968, 4314}, +/*h(16787)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16787, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4560)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4560; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20944)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4592)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4592, 4314}, +/*h(5579)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5579, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20976)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20976, 4314}, +/*h(21963)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21963, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_866_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9714)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9714, 6125}, +/*h(4546)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4546, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_671_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20930)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20930, 4314}, +/*h(26098)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26098, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4578)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20962)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20962, 4314}, +/*h(16781)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16781, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_783_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4554)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4554, 4314}, +/*h(5541)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5541, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_588_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20938)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20938, 4314}, +/*h(21925)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21925, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4586)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4586, 4314}, +/*h(405)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {405, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20970)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4562)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4562, 4314}, +/*h(5549)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5549, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20946)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20946, 4314}, +/*h(21933)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21933, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4594)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15810)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15810, 4360}, +/*h(20978)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20978, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3558)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3558, 4356}, +/*h(4545)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4545, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20929)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(396)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {396, 4325}, +/*h(4577)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4577, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_908_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16780)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16780, 4325}, +/*h(20961)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20961, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3566)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3566, 4356}, +/*h(4553)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4553, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20937)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1020_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29061)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29061, 4323}, +/*h(4585)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4585, 4314}, +/*h(404)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {404, 4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_825_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16788)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16788, 4325}, +/*h(20969)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20969, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4561)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20945)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_937_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4593)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4593, 4314}, +/*h(29069)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29069, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20977)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4547)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20931)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(398)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {398, 4325}, +/*h(4579)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4579, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1259_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16782)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16782, 4325}, +/*h(20963)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20963, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4555)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20939)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(29063)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29063, 4323}, +/*h(4587)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4587, 4314}, +/*h(5574)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5574, 6121}, +/*h(406)=3 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {406, 4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16790)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16790, 4325}, +/*h(20971)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20971, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4563)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20947)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4595)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4595, 4314}, +/*h(29071)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29071, 4323}, +/*h(5582)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5582, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21966)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21966, 6121}, +/*h(20979)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20979, 4314} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8580)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8612)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24996)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24996, 4322}, +/*h(1507)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1507, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8588)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8620)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_478_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1515)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1515, 6120}, +/*h(25004)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25004, 4322}, +/*h(25991)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25991, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((10*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8596)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24980)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24980, 4322}, +/*h(1491)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1491, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8628)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8628; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25012)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25012, 4322}, +/*h(25999)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25999, 6138}, +/*h(1523)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1523, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8582)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8614)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_913_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24998)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8590)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24974)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24974, 4322}, +/*h(1485)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1485, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8622)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25006)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8598)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1078_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24982)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24982, 4322}, +/*h(1493)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1493, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_942_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3462)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3462, 4356}, +/*h(8630)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8630, 4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25014)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4322} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25014; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(389)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {389, 4323}, +/*h(5557)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5557, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16773)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16773, 4323}, +/*h(21941)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21941, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1313_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3498)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3498, 4360}, +/*h(4485)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4485, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26037)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {26037, 6138}, +/*h(20869)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20869, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_520_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7594)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7594, 4360}, +/*h(8581)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8581, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12677)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(421)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15818)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15818, 4360}, +/*h(16805)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16805, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4517)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20901)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8613)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8613, 4323}, +/*h(13781)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13781, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24997)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_883_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17877)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {17877, 6124}, +/*h(12709)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12709, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(436)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {436, 4325}, +/*h(1423)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1423, 6138}, +/*h(29093)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29093, 4323}, +/*h(5604)=3 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5604, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(397)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8589)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(429)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15826)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {15826, 4364}, +/*h(16813)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16813, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4525)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20909)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8621)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1516)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1516, 6119}, +/*h(25005)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25005, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12717)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1431)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1431, 6138}, +/*h(29101)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29101, 4323}, +/*h(5612)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5612, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21957)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {21957, 6124}, +/*h(16789)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16789, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8597)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24981)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(420)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {420, 4325}, +/*h(29077)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29077, 4323}, +/*h(5588)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5588, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(437)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16821)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_815_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4533)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4533, 4323}, +/*h(9701)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9701, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20917)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9616)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9616, 6139}, +/*h(13797)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13797, 6124}, +/*h(8629)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8629, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1315_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1524)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1524, 6119}, +/*h(30181)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30181, 6124}, +/*h(25013)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25013, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12725)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12725, 4323}, +/*h(17893)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {17893, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(391)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_773_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16775)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16775, 4323}, +/*h(21943)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21943, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4487)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20871)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_871_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8583)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8583, 4323}, +/*h(13751)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13751, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17847)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17847, 6138}, +/*h(12679)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12679, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16807)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9687)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9687, 6124}, +/*h(4519)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4519, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20903)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20903, 4323}, +/*h(26071)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {26071, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_539_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13783)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13783, 6124}, +/*h(9602)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9602, 6139}, +/*h(8615)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8615, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1510)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1510, 6119}, +/*h(30167)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30167, 6124}, +/*h(24999)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24999, 4323}, +/*h(25986)=3 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25986, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12711)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1039_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(29095)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29095, 4323}, +/*h(438)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {438, 4325}, +/*h(5606)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5606, 6121}, +/*h(1425)=3 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1425, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8591)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12687)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(431)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16815)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5514)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5514, 6136}, +/*h(4527)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4527, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20911)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9610)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9610, 6139}, +/*h(8623)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8623, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25007)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25007, 4323}, +/*h(25994)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25994, 6139}, +/*h(1518)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1518, 6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12719)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29103)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13767)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13767, 6124}, +/*h(8599)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8599, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1494)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1494, 6119}, +/*h(30151)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30151, 6124}, +/*h(24983)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {24983, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1400_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12695)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12695, 4323}, +/*h(17863)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {17863, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(5590)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5590, 6121}, +/*h(422)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {422, 4325}, +/*h(1409)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1409, 6134}, +/*h(29079)=3 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {29079, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5607)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5607, 6124}, +/*h(439)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {439, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11655)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {11655, 4358}, +/*h(16823)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {16823, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5522)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5522, 6136}, +/*h(4535)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {4535, 4323}, +/*h(9703)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9703, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21906)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21906, 6136}, +/*h(26087)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {26087, 6124}, +/*h(20919)=2 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {20919, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8631)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {8631, 4323}, +/*h(3463)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3463, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(25015)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25015, 4323}, +/*h(1526)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1526, 6119}, +/*h(26002)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26002, 6139}, +/*h(30183)=3 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30183, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1069_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7559)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {7559, 4358}, +/*h(12727)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {12727, 4323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24960)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8584)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8616)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25000)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8624)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8624; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25008)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8586)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8618)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8618, 4324}, +/*h(9605)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9605, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25002)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {25002, 4324}, +/*h(1513)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1513, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_239_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8626)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8626, 4324}, +/*h(9613)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9613, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25010)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {25010, 4324}, +/*h(1521)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1521, 6120}, +/*h(25997)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {25997, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8577)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7622)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7622, 4356}, +/*h(8609)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8609, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_778_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1504)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1504, 6120}, +/*h(24993)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24993, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8585)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_891_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7630)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7630, 4356}, +/*h(8617)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8617, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25001)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8593)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_808_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7638)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {7638, 4362}, +/*h(8625)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8625, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25009)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8579)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1474)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1474, 6120}, +/*h(24963)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24963, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8611)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24995)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8587)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1482)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1482, 6120}, +/*h(24971)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24971, 4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8619)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25003)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8595)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8627)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25011)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4324} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(388)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16772)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16804)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(428)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16812)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16820)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16820, 4325}, +/*h(21988)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21988, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(390)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16774)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1010_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16806)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16806, 4325}, +/*h(21974)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21974, 6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(430)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {430, 4325}, +/*h(1417)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1417, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_927_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16814)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16814, 4325}, +/*h(17801)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17801, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21990)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21990, 6121}, +/*h(16822)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16822, 4325}, +/*h(17809)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17809, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(416)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {416, 4326}, +/*h(5584)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5584, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1444_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16800)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16800, 4326}, +/*h(21968)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21968, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(392)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16776)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(424)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1361_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16808)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16808, 4326}, +/*h(17795)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17795, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(432)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16816)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_834_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(386)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {386, 4326}, +/*h(5554)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5554, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(394)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16778)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(426)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16810)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16810, 4326}, +/*h(15823)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {15823, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21954)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21954, 6122}, +/*h(16786)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16786, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(434)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11650)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11650, 4360}, +/*h(15831)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15831, 4363}, +/*h(16818)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16818, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(393)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15790)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15790, 4356}, +/*h(16777)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16777, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_988_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1412)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1412, 6133}, +/*h(425)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {425, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16809)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_905_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1420)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1420, 6133}, +/*h(5601)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5601, 6122}, +/*h(433)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {433, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16817)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16817, 4326}, +/*h(21985)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21985, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(387)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {387, 4326}, +/*h(5555)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5555, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16771)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(419)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {419, 4326}, +/*h(5587)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5587, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16803)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16803, 4326}, +/*h(21971)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21971, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1414)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1414, 6133}, +/*h(427)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {427, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17798)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17798, 6133}, +/*h(16811)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16811, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(435)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(17806)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17806, 6133}, +/*h(21987)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21987, 6122}, +/*h(16819)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16819, 4326} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4484)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4484; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20868)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9684)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9684, 6123}, +/*h(4516)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4516, 4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20900)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20900, 4327}, +/*h(26068)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26068, 6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4524)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4524, 4327}, +/*h(5511)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5511, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20908)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20908, 4327}, +/*h(21895)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21895, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9700)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9700, 6123}, +/*h(4532)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4532, 4327}, +/*h(5519)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5519, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20916)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20916, 4327}, +/*h(21903)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21903, 6138}, +/*h(26084)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26084, 6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_744_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9654)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9654, 6137}, +/*h(4486)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4486, 4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20870)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20870, 4327}, +/*h(26038)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {26038, 6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4518)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26070)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26070, 6123}, +/*h(20902)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20902, 4327}, +/*h(21889)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21889, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4526)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20910)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20910, 4327}, +/*h(21897)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21897, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4502)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4502, 4327}, +/*h(9670)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9670, 6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4534)=0 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15750)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15750, 4356}, +/*h(20918)=1 EVV 0x78 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20918, 4327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9648)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9648, 6139}, +/*h(4480)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4480, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4488)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20872)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4520)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20904)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_817_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20880)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20880, 4328}, +/*h(26048)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26048, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4528)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4528; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20912)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4490)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4490, 4328}, +/*h(3503)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {3503, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20874)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4522)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20906)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1032_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4530)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4530, 4328}, +/*h(9698)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9698, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20914)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4489)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20873)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5508)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5508, 6135}, +/*h(4521)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4521, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21892)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21892, 6135}, +/*h(20905)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20905, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5516)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5516, 6135}, +/*h(9697)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9697, 6125}, +/*h(4529)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4529, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21900)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21900, 6135}, +/*h(26081)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26081, 6125}, +/*h(20913)=2 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20913, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9651)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9651, 6139}, +/*h(4483)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4483, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_766_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20867)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20867, 4328}, +/*h(26035)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26035, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4515)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26067)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26067, 6125}, +/*h(20899)=1 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20899, 4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4491)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4523)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20907)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_795_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4499)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4499, 4328}, +/*h(9667)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9667, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4531)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20915)=0 EVV 0x78 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4328} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2438)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2438, 4338}, +/*h(1451)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1451, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6534)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6534, 4338}, +/*h(5547)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5547, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10630)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10630; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14726)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2502)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6598)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5526)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5526, 6135}, +/*h(9707)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9707, 6125}, +/*h(10694)=2 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10694, 4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1075_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14790)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {14790, 4338}, +/*h(9622)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9622, 6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2470)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6566)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6566, 4338}, +/*h(11734)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {11734, 4362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_711_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10662)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10662, 4338}, +/*h(15830)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {15830, 4362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14758)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2534)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2534, 4338}, +/*h(26023)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {26023, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6630)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6630, 4338}, +/*h(1462)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1462, 6133}, +/*h(30119)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30119, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5558)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5558, 6135}, +/*h(10726)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10726, 4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14822)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1058_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2446)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2446, 4338}, +/*h(1459)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1459, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6542)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10638)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14734)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2510)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1090_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5619)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5619, 6122}, +/*h(30095)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30095, 6138}, +/*h(6606)=2 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6606, 4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10702)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10702, 4338}, +/*h(9715)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9715, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14798)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2478)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6574)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10670)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14766)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2542)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2542, 4338}, +/*h(26031)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {26031, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6638)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6638, 4338}, +/*h(30127)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30127, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10734)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14830)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4338} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2454)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4339} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6550)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4339} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_877_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10646)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {10646, 4339}, +/*h(15814)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15814, 4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14742)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4339} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2439)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6535)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9644)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9644, 6137}, +/*h(10631)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {10631, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14727)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25992)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25992, 6139}, +/*h(2503)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2503, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6599)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1299_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11682)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11682, 4360}, +/*h(10695)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {10695, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_507_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9623)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9623, 6138}, +/*h(14791)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {14791, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1484)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1484, 6119}, +/*h(2471)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2471, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_936_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5580)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5580, 6121}, +/*h(6567)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {6567, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10663)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_838_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15746)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15746, 4360}, +/*h(14759)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {14759, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2535)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2450)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2450, 4343}, +/*h(6631)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {6631, 4340}, +/*h(7618)=2 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7618, 4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_968_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5559)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5559, 6138}, +/*h(10727)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {10727, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10642)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {10642, 4343}, +/*h(9655)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9655, 6138}, +/*h(14823)=2 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {14823, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2447)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5556)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5556, 6135}, +/*h(6543)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {6543, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9652)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9652, 6137}, +/*h(10639)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {10639, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14735)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26000)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26000, 6139}, +/*h(2511)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2511, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6607)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11690)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11690, 4360}, +/*h(10703)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {10703, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14799)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2479)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2479, 4340}, +/*h(30149)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30149, 6124}, +/*h(1492)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1492, 6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6575)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10671)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15754)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15754, 4360}, +/*h(14767)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {14767, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_982_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3530)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3530, 4360}, +/*h(2543)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {2543, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7626)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7626, 4360}, +/*h(6639)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {6639, 4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10735)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14831)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4340} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7623)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {7623, 4358}, +/*h(2455)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {2455, 4341} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6551)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4341} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10647)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4341} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14743)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4341} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2434)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2434, 4342}, +/*h(6615)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {6615, 4345} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6530)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6530, 4342}, +/*h(10711)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {10711, 4345} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10626)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1036_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14722)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {14722, 4342}, +/*h(13735)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13735, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1263_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25987)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25987, 6139}, +/*h(1511)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1511, 6124}, +/*h(2498)=2 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2498, 4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6594)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6594, 4342}, +/*h(1426)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1426, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10690)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14786)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2466)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2466, 4342}, +/*h(7634)=1 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {7634, 4364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_802_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6562)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6562, 4342}, +/*h(5575)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5575, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10658)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {10658, 4342}, +/*h(9671)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9671, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14754)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2530)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6626)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10722)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9650)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9650, 6139}, +/*h(14818)=1 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {14818, 4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2442)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6538)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10634)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {10634, 4342}, +/*h(9647)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9647, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14730)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {14730, 4342}, +/*h(13743)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13743, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1180_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2506)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2506, 4342}, +/*h(1519)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1519, 6124}, +/*h(25995)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25995, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6602)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10698)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14794)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2474)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6570)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6570, 4342}, +/*h(5583)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5583, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10666)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14762)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2538)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6634)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10730)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14826)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4342} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_967_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6546)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {6546, 4343}, +/*h(11714)=1 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11714, 4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14738)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4343} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2518)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4344} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1007_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1446)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1446, 6133}, +/*h(30103)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30103, 6138}, +/*h(6614)=2 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {6614, 4344} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10710)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {10710, 4344}, +/*h(5542)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5542, 6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14806)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4344} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2519)=0 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4345} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9639)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {9639, 6138}, +/*h(14807)=1 EVV 0x78 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {14807, 4345} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1527)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1527, 6124}, +/*h(2514)=1 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2514, 4346}, +/*h(26003)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26003, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6610)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4346} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10706)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4346} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14802)=0 EVV 0x78 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4346} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7558)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11654)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3526)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3494)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7590)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7654)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11750)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15846)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3470)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7566)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7566; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11662)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15758)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3534)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11726)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15822)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3502)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7598)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11694)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7662)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11758)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15854)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4356} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3478)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7574)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11670)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4357} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15751)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3527)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7591)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11687)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15783)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3559)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3474)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {3474, 4361}, +/*h(7655)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {7655, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_769_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7570)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {7570, 4361}, +/*h(11751)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {11751, 4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15847)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3471)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7567)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11663)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15759)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3535)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7631)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7631; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11727)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7599)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11695)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15791)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3567)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11759)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15855)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() not64 NOEVSR ZEROING=0 MASK=0*/ {4358} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11671)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15767)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4359} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3458)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3458, 4360}, +/*h(7639)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7639, 4363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7554)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7554, 4360}, +/*h(11735)=1 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11735, 4363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7586)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15778)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3554)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7650)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11746)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15842)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3466)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7562)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11658)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11722)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15786)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3562)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7658)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15850)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4360} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15762)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4361} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3542)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4362} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3543)=0 EVV 0x78 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4363} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3538)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11730)=0 EVV 0x78 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4364} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1476)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1476, 6119}, +/*h(30133)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30133, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17860)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17860; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(30165)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30165, 6124}, +/*h(25984)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25984, 6139}, +/*h(1508)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1508, 6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17892)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {17892, 6119}, +/*h(13711)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13711, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17868)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17900)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {17900, 6119}, +/*h(13719)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13719, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17876)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17908)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1478)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1478, 6119}, +/*h(30135)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30135, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17862)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17894)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1486)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17870)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17902)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17878)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17910)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6119} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17856)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17888)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_695_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1512)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1512, 6120}, +/*h(25988)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25988, 6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17896)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_612_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1520)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1520, 6120}, +/*h(25996)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25996, 6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17904)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1506)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17890)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17890, 6120}, +/*h(13709)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13709, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1046_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1514)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1514, 6120}, +/*h(25990)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25990, 6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_851_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17898)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17898, 6120}, +/*h(13717)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {13717, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1490)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17874)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25998)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25998, 6137}, +/*h(1522)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1522, 6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17906)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1473)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17857)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17889)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1481)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17865)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17897)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1489)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17873)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17905)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1475)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17859)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17891)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17867)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17899)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17875)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17907)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6120} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5572)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5572; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21956)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21964)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21996)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21972)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21958)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5614)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21998)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6121} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_873_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5622)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5622, 6121}, +/*h(1441)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1441, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1473_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5600)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5600, 6122}, +/*h(1419)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1419, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21984)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21984, 6122}, +/*h(17803)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17803, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5576)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5608)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5608, 6122}, +/*h(1427)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1427, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21992)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21992, 6122}, +/*h(17811)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17811, 6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5616)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22000)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 22000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5570)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5602)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5602, 6122}, +/*h(1421)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1421, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21986)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21986, 6122}, +/*h(17805)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17805, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5578)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21962)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5610)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5610, 6122}, +/*h(1429)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {1429, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21994)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21994, 6122}, +/*h(17813)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {17813, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5586)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21970)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22002)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 22002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5569)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21953)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21961)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_822_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1428)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1428, 6133}, +/*h(30085)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30085, 6138}, +/*h(5609)=2 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5609, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17812)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17812, 6133}, +/*h(21993)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21993, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21969)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1422)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1422, 6133}, +/*h(5603)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5603, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(30087)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30087, 6138}, +/*h(5611)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5611, 6122}, +/*h(1430)=2 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1430, 6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_978_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17814)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17814, 6133}, +/*h(21995)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21995, 6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22003)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6122} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 22003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26052)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26052; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9708)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9708, 6123}, +/*h(5527)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5527, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26092)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26092, 6123}, +/*h(21911)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21911, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9716)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9716; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9702)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9702, 6123}, +/*h(5521)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5521, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26086)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26086, 6123}, +/*h(21905)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21905, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9678)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9710)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26094)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6123} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26094; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9686)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9686, 6123}, +/*h(5505)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5505, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9718)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9718, 6123}, +/*h(5537)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5537, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26102)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26102, 6123}, +/*h(21921)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21921, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5573)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5573; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9669)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26053)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13765)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1509)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1509, 6124}, +/*h(25985)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25985, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1424)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1424, 6134}, +/*h(5605)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5605, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17808)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17808, 6134}, +/*h(21989)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {21989, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21904)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21904, 6136}, +/*h(26085)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {26085, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5581)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5581; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21965)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9677)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26061)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13773)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30157)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30157; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_829_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1517)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1517, 6124}, +/*h(25993)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25993, 6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17901)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5613)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5613; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21997)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9709)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26093)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13805)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30189)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1408)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1408, 6134}, +/*h(5589)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5589, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17792)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17792, 6134}, +/*h(21973)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {21973, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_980_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5504)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5504, 6136}, +/*h(9685)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {9685, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21888)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21888, 6136}, +/*h(26069)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {26069, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_746_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26001)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26001, 6139}, +/*h(1525)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {1525, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17909)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1440)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1440, 6134}, +/*h(5621)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5621, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17824)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17824, 6134}, +/*h(22005)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {22005, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1479)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1479; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21959)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26055)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17895)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17810)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17810, 6134}, +/*h(21991)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {21991, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9618)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9618, 6139}, +/*h(13799)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13799, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1487)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17871)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21967)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26063)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13775)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30159)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30159; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17903)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5615)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21999)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9711)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26095)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13807)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30191)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1495)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17879)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1410)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1410, 6134}, +/*h(5591)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {5591, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17794)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17794, 6134}, +/*h(21975)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {21975, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17911)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9634)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9634, 6139}, +/*h(13815)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {13815, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26018)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26018, 6139}, +/*h(30199)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {30199, 6124} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9664)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9696)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9696, 6125}, +/*h(5515)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5515, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26080)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26080, 6125}, +/*h(21899)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21899, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9672)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_734_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26056)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9704)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9704, 6125}, +/*h(5523)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5523, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26088)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26088, 6125}, +/*h(21907)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21907, 6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9680)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26064)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9712)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26096)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9666)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26050)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26082)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26082, 6125}, +/*h(21901)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {21901, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9674)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26058)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_949_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9706)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9706, 6125}, +/*h(5525)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {5525, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26090)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9682)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26066)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5524)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5524, 6135}, +/*h(9705)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9705, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21908)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21908, 6135}, +/*h(26089)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26089, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9713)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26097)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5518)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5518, 6135}, +/*h(9699)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9699, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21902)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21902, 6135}, +/*h(26083)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26083, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9675)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26059)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21910)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21910, 6135}, +/*h(26091)=1 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26091, 6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9683)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26099)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6125} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17796)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1444)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1444, 6133}, +/*h(30101)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30101, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17804)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1452)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1460)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1460, 6133}, +/*h(30117)=1 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {30117, 6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17844)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17830)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1454)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17838)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17846)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6133} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1416)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17800)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1448)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17832)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1456)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17840)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17826)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1418)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17802)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17793)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1449)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17833)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1457)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17841)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1411)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1443)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17827)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17835)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17843)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6134} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5540)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5540; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21924)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5548)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21932)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21940)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5510)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21894)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21926)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5550)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21934)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21942)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6135} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21920)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5512)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21896)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21928)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5520)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5506)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21890)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21898)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5546)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5513)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5545)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21929)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5553)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21937)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5507)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21891)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5539)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21923)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21931)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21939)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6136} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9604)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9636)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26020)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9612)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26028)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9620)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26004)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26036)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9606)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26022)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9614)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26030)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26006)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6137} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1413)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17797)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5509)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21893)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25989)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13701)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1445)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17829)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9637)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_685_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13733)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5517)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17837)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9645)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26029)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13741)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30125)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21909)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9621)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26005)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1461)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17845)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9653)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13749)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1415)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17799)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9607)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13703)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5543)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21927)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17807)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9615)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5551)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21935)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17815)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26007)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1463)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26039)=0 EVV 0x78 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {6138} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9600)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9608)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9642)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26026)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26034)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9601)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9633)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26017)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9609)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9641)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26025)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9617)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26033)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9603)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9611)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2_1292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9619)=0 EVV 0x78 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6139} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x78_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[1488] = { +/*h(21892)=0 */ {21892, xed3_phash_find_mapevex_map1_opcode0x78_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8595)=3 */ {8595, xed3_phash_find_mapevex_map1_opcode0x78_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1453)=5 */ {1453, xed3_phash_find_mapevex_map1_opcode0x78_vv2_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17800)=7 */ {17800, xed3_phash_find_mapevex_map1_opcode0x78_vv2_7_l1}, +/*h(15826)=8 */ {15826, xed3_phash_find_mapevex_map1_opcode0x78_vv2_8_l1}, +/*h(9671)=9 */ {9671, xed3_phash_find_mapevex_map1_opcode0x78_vv2_9_l1}, +/*h(4503)=10 */ {4503, xed3_phash_find_mapevex_map1_opcode0x78_vv2_10_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26018)=12 */ {26018, xed3_phash_find_mapevex_map1_opcode0x78_vv2_12_l1}, +/*h(25031)=13 */ {25031, xed3_phash_find_mapevex_map1_opcode0x78_vv2_13_l1}, +/*h(17889)=14 */ {17889, xed3_phash_find_mapevex_map1_opcode0x78_vv2_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11734)=16 */ {11734, xed3_phash_find_mapevex_map1_opcode0x78_vv2_16_l1}, +/*h(5579)=17 */ {5579, xed3_phash_find_mapevex_map1_opcode0x78_vv2_17_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21926)=19 */ {21926, xed3_phash_find_mapevex_map1_opcode0x78_vv2_19_l1}, +/*h(20939)=20 */ {20939, xed3_phash_find_mapevex_map1_opcode0x78_vv2_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9616)=22 */ {9616, xed3_phash_find_mapevex_map1_opcode0x78_vv2_22_l1}, +/*h(2474)=23 */ {2474, xed3_phash_find_mapevex_map1_opcode0x78_vv2_23_l1}, +/*h(1487)=24 */ {1487, xed3_phash_find_mapevex_map1_opcode0x78_vv2_24_l1}, +/*h(24976)=25 */ {24976, xed3_phash_find_mapevex_map1_opcode0x78_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17834)=27 */ {17834, xed3_phash_find_mapevex_map1_opcode0x78_vv2_27_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5524)=29 */ {5524, xed3_phash_find_mapevex_map1_opcode0x78_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26052)=31 */ {26052, xed3_phash_find_mapevex_map1_opcode0x78_vv2_31_l1}, +/*h(20884)=32 */ {20884, xed3_phash_find_mapevex_map1_opcode0x78_vv2_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5613)=36 */ {5613, xed3_phash_find_mapevex_map1_opcode0x78_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21960)=39 */ {21960, xed3_phash_find_mapevex_map1_opcode0x78_vv2_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9650)=41 */ {9650, xed3_phash_find_mapevex_map1_opcode0x78_vv2_41_l1}, +/*h(3495)=42 */ {3495, xed3_phash_find_mapevex_map1_opcode0x78_vv2_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25997)=44 */ {25997, xed3_phash_find_mapevex_map1_opcode0x78_vv2_44_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17868)=46 */ {17868, xed3_phash_find_mapevex_map1_opcode0x78_vv2_46_l1}, +/*h(16881)=47 */ {16881, xed3_phash_find_mapevex_map1_opcode0x78_vv2_47_l1}, +/*h(5558)=48 */ {5558, xed3_phash_find_mapevex_map1_opcode0x78_vv2_48_l1}, +/*h(390)=49 */ {390, xed3_phash_find_mapevex_map1_opcode0x78_vv2_49_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21905)=51 */ {21905, xed3_phash_find_mapevex_map1_opcode0x78_vv2_51_l1}, +/*h(15750)=52 */ {15750, xed3_phash_find_mapevex_map1_opcode0x78_vv2_52_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8608)=54 */ {8608, xed3_phash_find_mapevex_map1_opcode0x78_vv2_54_l1}, +/*h(6634)=55 */ {6634, xed3_phash_find_mapevex_map1_opcode0x78_vv2_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17813)=58 */ {17813, xed3_phash_find_mapevex_map1_opcode0x78_vv2_58_l1}, +/*h(11658)=59 */ {11658, xed3_phash_find_mapevex_map1_opcode0x78_vv2_59_l1}, +/*h(10671)=60 */ {10671, xed3_phash_find_mapevex_map1_opcode0x78_vv2_60_l1}, +/*h(9684)=61 */ {9684, xed3_phash_find_mapevex_map1_opcode0x78_vv2_61_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26031)=63 */ {26031, xed3_phash_find_mapevex_map1_opcode0x78_vv2_63_l1}, +/*h(25044)=64 */ {25044, xed3_phash_find_mapevex_map1_opcode0x78_vv2_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17902)=66 */ {17902, xed3_phash_find_mapevex_map1_opcode0x78_vv2_66_l1}, +/*h(7566)=67 */ {7566, xed3_phash_find_mapevex_map1_opcode0x78_vv2_67_l1}, +/*h(1411)=68 */ {1411, xed3_phash_find_mapevex_map1_opcode0x78_vv2_68_l1}, +/*h(424)=69 */ {424, xed3_phash_find_mapevex_map1_opcode0x78_vv2_69_l1}, +/*h(21939)=70 */ {21939, xed3_phash_find_mapevex_map1_opcode0x78_vv2_70_l1}, +/*h(16771)=71 */ {16771, xed3_phash_find_mapevex_map1_opcode0x78_vv2_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8642)=73 */ {8642, xed3_phash_find_mapevex_map1_opcode0x78_vv2_73_l1}, +/*h(3474)=74 */ {3474, xed3_phash_find_mapevex_map1_opcode0x78_vv2_74_l1}, +/*h(30157)=75 */ {30157, xed3_phash_find_mapevex_map1_opcode0x78_vv2_75_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17847)=78 */ {17847, xed3_phash_find_mapevex_map1_opcode0x78_vv2_78_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5537)=80 */ {5537, xed3_phash_find_mapevex_map1_opcode0x78_vv2_80_l1}, +/*h(4550)=81 */ {4550, xed3_phash_find_mapevex_map1_opcode0x78_vv2_81_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26065)=83 */ {26065, xed3_phash_find_mapevex_map1_opcode0x78_vv2_83_l1}, +/*h(14742)=84 */ {14742, xed3_phash_find_mapevex_map1_opcode0x78_vv2_84_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8587)=86 */ {8587, xed3_phash_find_mapevex_map1_opcode0x78_vv2_86_l1}, +/*h(1445)=87 */ {1445, xed3_phash_find_mapevex_map1_opcode0x78_vv2_87_l1}, +/*h(458)=88 */ {458, xed3_phash_find_mapevex_map1_opcode0x78_vv2_88_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17792)=90 */ {17792, xed3_phash_find_mapevex_map1_opcode0x78_vv2_90_l1}, +/*h(15818)=91 */ {15818, xed3_phash_find_mapevex_map1_opcode0x78_vv2_91_l1}, +/*h(14831)=92 */ {14831, xed3_phash_find_mapevex_map1_opcode0x78_vv2_92_l1}, +/*h(4495)=93 */ {4495, xed3_phash_find_mapevex_map1_opcode0x78_vv2_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30191)=95 */ {30191, xed3_phash_find_mapevex_map1_opcode0x78_vv2_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11726)=99 */ {11726, xed3_phash_find_mapevex_map1_opcode0x78_vv2_99_l1}, +/*h(5571)=100 */ {5571, xed3_phash_find_mapevex_map1_opcode0x78_vv2_100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26099)=102 */ {26099, xed3_phash_find_mapevex_map1_opcode0x78_vv2_102_l1}, +/*h(20931)=103 */ {20931, xed3_phash_find_mapevex_map1_opcode0x78_vv2_103_l1}, +/*h(9608)=104 */ {9608, xed3_phash_find_mapevex_map1_opcode0x78_vv2_104_l1}, +/*h(8621)=105 */ {8621, xed3_phash_find_mapevex_map1_opcode0x78_vv2_105_l1}, +/*h(7634)=106 */ {7634, xed3_phash_find_mapevex_map1_opcode0x78_vv2_106_l1}, +/*h(1479)=107 */ {1479, xed3_phash_find_mapevex_map1_opcode0x78_vv2_107_l1}, +/*h(24968)=108 */ {24968, xed3_phash_find_mapevex_map1_opcode0x78_vv2_108_l1}, +/*h(17826)=109 */ {17826, xed3_phash_find_mapevex_map1_opcode0x78_vv2_109_l1}, +/*h(22007)=110 */ {22007, xed3_phash_find_mapevex_map1_opcode0x78_vv2_110_l1}, +/*h(11671)=111 */ {11671, xed3_phash_find_mapevex_map1_opcode0x78_vv2_111_l1}, +/*h(5516)=112 */ {5516, xed3_phash_find_mapevex_map1_opcode0x78_vv2_112_l1}, +/*h(3542)=113 */ {3542, xed3_phash_find_mapevex_map1_opcode0x78_vv2_113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20876)=115 */ {20876, xed3_phash_find_mapevex_map1_opcode0x78_vv2_115_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1424)=119 */ {1424, xed3_phash_find_mapevex_map1_opcode0x78_vv2_119_l1}, +/*h(437)=120 */ {437, xed3_phash_find_mapevex_map1_opcode0x78_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21952)=122 */ {21952, xed3_phash_find_mapevex_map1_opcode0x78_vv2_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9642)=124 */ {9642, xed3_phash_find_mapevex_map1_opcode0x78_vv2_124_l1}, +/*h(8655)=125 */ {8655, xed3_phash_find_mapevex_map1_opcode0x78_vv2_125_l1}, +/*h(25989)=126 */ {25989, xed3_phash_find_mapevex_map1_opcode0x78_vv2_126_l1}, +/*h(1513)=127 */ {1513, xed3_phash_find_mapevex_map1_opcode0x78_vv2_127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17860)=129 */ {17860, xed3_phash_find_mapevex_map1_opcode0x78_vv2_129_l1}, +/*h(16873)=130 */ {16873, xed3_phash_find_mapevex_map1_opcode0x78_vv2_130_l1}, +/*h(5550)=131 */ {5550, xed3_phash_find_mapevex_map1_opcode0x78_vv2_131_l1}, +/*h(4563)=132 */ {4563, xed3_phash_find_mapevex_map1_opcode0x78_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21897)=134 */ {21897, xed3_phash_find_mapevex_map1_opcode0x78_vv2_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12781)=137 */ {12781, xed3_phash_find_mapevex_map1_opcode0x78_vv2_137_l1}, +/*h(6626)=138 */ {6626, xed3_phash_find_mapevex_map1_opcode0x78_vv2_138_l1}, +/*h(1458)=139 */ {1458, xed3_phash_find_mapevex_map1_opcode0x78_vv2_139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17805)=141 */ {17805, xed3_phash_find_mapevex_map1_opcode0x78_vv2_141_l1}, +/*h(15831)=142 */ {15831, xed3_phash_find_mapevex_map1_opcode0x78_vv2_142_l1}, +/*h(10663)=143 */ {10663, xed3_phash_find_mapevex_map1_opcode0x78_vv2_143_l1}, +/*h(9676)=144 */ {9676, xed3_phash_find_mapevex_map1_opcode0x78_vv2_144_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26023)=146 */ {26023, xed3_phash_find_mapevex_map1_opcode0x78_vv2_146_l1}, +/*h(25036)=147 */ {25036, xed3_phash_find_mapevex_map1_opcode0x78_vv2_147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17894)=149 */ {17894, xed3_phash_find_mapevex_map1_opcode0x78_vv2_149_l1}, +/*h(7558)=150 */ {7558, xed3_phash_find_mapevex_map1_opcode0x78_vv2_150_l1}, +/*h(5584)=151 */ {5584, xed3_phash_find_mapevex_map1_opcode0x78_vv2_151_l1}, +/*h(4597)=152 */ {4597, xed3_phash_find_mapevex_map1_opcode0x78_vv2_152_l1}, +/*h(21931)=153 */ {21931, xed3_phash_find_mapevex_map1_opcode0x78_vv2_153_l1}, +/*h(20944)=154 */ {20944, xed3_phash_find_mapevex_map1_opcode0x78_vv2_154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9621)=156 */ {9621, xed3_phash_find_mapevex_map1_opcode0x78_vv2_156_l1}, +/*h(3466)=157 */ {3466, xed3_phash_find_mapevex_map1_opcode0x78_vv2_157_l1}, +/*h(30149)=158 */ {30149, xed3_phash_find_mapevex_map1_opcode0x78_vv2_158_l1}, +/*h(24981)=159 */ {24981, xed3_phash_find_mapevex_map1_opcode0x78_vv2_159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17839)=161 */ {17839, xed3_phash_find_mapevex_map1_opcode0x78_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9710)=163 */ {9710, xed3_phash_find_mapevex_map1_opcode0x78_vv2_163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26057)=166 */ {26057, xed3_phash_find_mapevex_map1_opcode0x78_vv2_166_l1}, +/*h(14734)=167 */ {14734, xed3_phash_find_mapevex_map1_opcode0x78_vv2_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8579)=169 */ {8579, xed3_phash_find_mapevex_map1_opcode0x78_vv2_169_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5618)=171 */ {5618, xed3_phash_find_mapevex_map1_opcode0x78_vv2_171_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21965)=173 */ {21965, xed3_phash_find_mapevex_map1_opcode0x78_vv2_173_l1}, +/*h(15810)=174 */ {15810, xed3_phash_find_mapevex_map1_opcode0x78_vv2_174_l1}, +/*h(9655)=175 */ {9655, xed3_phash_find_mapevex_map1_opcode0x78_vv2_175_l1}, +/*h(4487)=176 */ {4487, xed3_phash_find_mapevex_map1_opcode0x78_vv2_176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26002)=178 */ {26002, xed3_phash_find_mapevex_map1_opcode0x78_vv2_178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17873)=180 */ {17873, xed3_phash_find_mapevex_map1_opcode0x78_vv2_180_l1}, +/*h(11718)=181 */ {11718, xed3_phash_find_mapevex_map1_opcode0x78_vv2_181_l1}, +/*h(6550)=182 */ {6550, xed3_phash_find_mapevex_map1_opcode0x78_vv2_182_l1}, +/*h(395)=183 */ {395, xed3_phash_find_mapevex_map1_opcode0x78_vv2_183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21910)=185 */ {21910, xed3_phash_find_mapevex_map1_opcode0x78_vv2_185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9600)=187 */ {9600, xed3_phash_find_mapevex_map1_opcode0x78_vv2_187_l1}, +/*h(13781)=188 */ {13781, xed3_phash_find_mapevex_map1_opcode0x78_vv2_188_l1}, +/*h(7626)=189 */ {7626, xed3_phash_find_mapevex_map1_opcode0x78_vv2_189_l1}, +/*h(24960)=190 */ {24960, xed3_phash_find_mapevex_map1_opcode0x78_vv2_190_l1}, +/*h(484)=191 */ {484, xed3_phash_find_mapevex_map1_opcode0x78_vv2_191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21999)=193 */ {21999, xed3_phash_find_mapevex_map1_opcode0x78_vv2_193_l1}, +/*h(11663)=194 */ {11663, xed3_phash_find_mapevex_map1_opcode0x78_vv2_194_l1}, +/*h(5508)=195 */ {5508, xed3_phash_find_mapevex_map1_opcode0x78_vv2_195_l1}, +/*h(3534)=196 */ {3534, xed3_phash_find_mapevex_map1_opcode0x78_vv2_196_l1}, +/*h(26036)=197 */ {26036, xed3_phash_find_mapevex_map1_opcode0x78_vv2_197_l1}, +/*h(20868)=198 */ {20868, xed3_phash_find_mapevex_map1_opcode0x78_vv2_198_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17907)=200 */ {17907, xed3_phash_find_mapevex_map1_opcode0x78_vv2_200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1416)=202 */ {1416, xed3_phash_find_mapevex_map1_opcode0x78_vv2_202_l1}, +/*h(429)=203 */ {429, xed3_phash_find_mapevex_map1_opcode0x78_vv2_203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16776)=205 */ {16776, xed3_phash_find_mapevex_map1_opcode0x78_vv2_205_l1}, +/*h(14802)=206 */ {14802, xed3_phash_find_mapevex_map1_opcode0x78_vv2_206_l1}, +/*h(9634)=207 */ {9634, xed3_phash_find_mapevex_map1_opcode0x78_vv2_207_l1}, +/*h(3479)=208 */ {3479, xed3_phash_find_mapevex_map1_opcode0x78_vv2_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1505)=210 */ {1505, xed3_phash_find_mapevex_map1_opcode0x78_vv2_210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16865)=213 */ {16865, xed3_phash_find_mapevex_map1_opcode0x78_vv2_213_l1}, +/*h(5542)=214 */ {5542, xed3_phash_find_mapevex_map1_opcode0x78_vv2_214_l1}, +/*h(4555)=215 */ {4555, xed3_phash_find_mapevex_map1_opcode0x78_vv2_215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21889)=217 */ {21889, xed3_phash_find_mapevex_map1_opcode0x78_vv2_217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8592)=220 */ {8592, xed3_phash_find_mapevex_map1_opcode0x78_vv2_220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1450)=222 */ {1450, xed3_phash_find_mapevex_map1_opcode0x78_vv2_222_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17797)=224 */ {17797, xed3_phash_find_mapevex_map1_opcode0x78_vv2_224_l1}, +/*h(15823)=225 */ {15823, xed3_phash_find_mapevex_map1_opcode0x78_vv2_225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9668)=227 */ {9668, xed3_phash_find_mapevex_map1_opcode0x78_vv2_227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25028)=230 */ {25028, xed3_phash_find_mapevex_map1_opcode0x78_vv2_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5576)=234 */ {5576, xed3_phash_find_mapevex_map1_opcode0x78_vv2_234_l1}, +/*h(4589)=235 */ {4589, xed3_phash_find_mapevex_map1_opcode0x78_vv2_235_l1}, +/*h(21923)=236 */ {21923, xed3_phash_find_mapevex_map1_opcode0x78_vv2_236_l1}, +/*h(20936)=237 */ {20936, xed3_phash_find_mapevex_map1_opcode0x78_vv2_237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9613)=239 */ {9613, xed3_phash_find_mapevex_map1_opcode0x78_vv2_239_l1}, +/*h(7639)=240 */ {7639, xed3_phash_find_mapevex_map1_opcode0x78_vv2_240_l1}, +/*h(1484)=241 */ {1484, xed3_phash_find_mapevex_map1_opcode0x78_vv2_241_l1}, +/*h(24973)=242 */ {24973, xed3_phash_find_mapevex_map1_opcode0x78_vv2_242_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17831)=244 */ {17831, xed3_phash_find_mapevex_map1_opcode0x78_vv2_244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5521)=246 */ {5521, xed3_phash_find_mapevex_map1_opcode0x78_vv2_246_l1}, +/*h(4534)=247 */ {4534, xed3_phash_find_mapevex_map1_opcode0x78_vv2_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26049)=249 */ {26049, xed3_phash_find_mapevex_map1_opcode0x78_vv2_249_l1}, +/*h(14726)=250 */ {14726, xed3_phash_find_mapevex_map1_opcode0x78_vv2_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1429)=253 */ {1429, xed3_phash_find_mapevex_map1_opcode0x78_vv2_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21957)=256 */ {21957, xed3_phash_find_mapevex_map1_opcode0x78_vv2_256_l1}, +/*h(20970)=257 */ {20970, xed3_phash_find_mapevex_map1_opcode0x78_vv2_257_l1}, +/*h(9647)=258 */ {9647, xed3_phash_find_mapevex_map1_opcode0x78_vv2_258_l1}, +/*h(8660)=259 */ {8660, xed3_phash_find_mapevex_map1_opcode0x78_vv2_259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25994)=261 */ {25994, xed3_phash_find_mapevex_map1_opcode0x78_vv2_261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17865)=263 */ {17865, xed3_phash_find_mapevex_map1_opcode0x78_vv2_263_l1}, +/*h(16878)=264 */ {16878, xed3_phash_find_mapevex_map1_opcode0x78_vv2_264_l1}, +/*h(6542)=265 */ {6542, xed3_phash_find_mapevex_map1_opcode0x78_vv2_265_l1}, +/*h(5555)=266 */ {5555, xed3_phash_find_mapevex_map1_opcode0x78_vv2_266_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21902)=268 */ {21902, xed3_phash_find_mapevex_map1_opcode0x78_vv2_268_l1}, +/*h(20915)=269 */ {20915, xed3_phash_find_mapevex_map1_opcode0x78_vv2_269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13773)=271 */ {13773, xed3_phash_find_mapevex_map1_opcode0x78_vv2_271_l1}, +/*h(7618)=272 */ {7618, xed3_phash_find_mapevex_map1_opcode0x78_vv2_272_l1}, +/*h(1463)=273 */ {1463, xed3_phash_find_mapevex_map1_opcode0x78_vv2_273_l1}, +/*h(29133)=274 */ {29133, xed3_phash_find_mapevex_map1_opcode0x78_vv2_274_l1}, +/*h(17810)=275 */ {17810, xed3_phash_find_mapevex_map1_opcode0x78_vv2_275_l1}, +/*h(11655)=276 */ {11655, xed3_phash_find_mapevex_map1_opcode0x78_vv2_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9681)=278 */ {9681, xed3_phash_find_mapevex_map1_opcode0x78_vv2_278_l1}, +/*h(3526)=279 */ {3526, xed3_phash_find_mapevex_map1_opcode0x78_vv2_279_l1}, +/*h(26028)=280 */ {26028, xed3_phash_find_mapevex_map1_opcode0x78_vv2_280_l1}, +/*h(25041)=281 */ {25041, xed3_phash_find_mapevex_map1_opcode0x78_vv2_281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17899)=283 */ {17899, xed3_phash_find_mapevex_map1_opcode0x78_vv2_283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1408)=285 */ {1408, xed3_phash_find_mapevex_map1_opcode0x78_vv2_285_l1}, +/*h(421)=286 */ {421, xed3_phash_find_mapevex_map1_opcode0x78_vv2_286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21936)=288 */ {21936, xed3_phash_find_mapevex_map1_opcode0x78_vv2_288_l1}, +/*h(14794)=289 */ {14794, xed3_phash_find_mapevex_map1_opcode0x78_vv2_289_l1}, +/*h(13807)=290 */ {13807, xed3_phash_find_mapevex_map1_opcode0x78_vv2_290_l1}, +/*h(3471)=291 */ {3471, xed3_phash_find_mapevex_map1_opcode0x78_vv2_291_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(29167)=293 */ {29167, xed3_phash_find_mapevex_map1_opcode0x78_vv2_293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17844)=295 */ {17844, xed3_phash_find_mapevex_map1_opcode0x78_vv2_295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9715)=297 */ {9715, xed3_phash_find_mapevex_map1_opcode0x78_vv2_297_l1}, +/*h(4547)=298 */ {4547, xed3_phash_find_mapevex_map1_opcode0x78_vv2_298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26062)=300 */ {26062, xed3_phash_find_mapevex_map1_opcode0x78_vv2_300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8584)=303 */ {8584, xed3_phash_find_mapevex_map1_opcode0x78_vv2_303_l1}, +/*h(6610)=304 */ {6610, xed3_phash_find_mapevex_map1_opcode0x78_vv2_304_l1}, +/*h(1442)=305 */ {1442, xed3_phash_find_mapevex_map1_opcode0x78_vv2_305_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21970)=307 */ {21970, xed3_phash_find_mapevex_map1_opcode0x78_vv2_307_l1}, +/*h(15815)=308 */ {15815, xed3_phash_find_mapevex_map1_opcode0x78_vv2_308_l1}, +/*h(10647)=309 */ {10647, xed3_phash_find_mapevex_map1_opcode0x78_vv2_309_l1}, +/*h(4492)=310 */ {4492, xed3_phash_find_mapevex_map1_opcode0x78_vv2_310_l1}, +/*h(2518)=311 */ {2518, xed3_phash_find_mapevex_map1_opcode0x78_vv2_311_l1}, +/*h(26007)=312 */ {26007, xed3_phash_find_mapevex_map1_opcode0x78_vv2_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17878)=314 */ {17878, xed3_phash_find_mapevex_map1_opcode0x78_vv2_314_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5568)=317 */ {5568, xed3_phash_find_mapevex_map1_opcode0x78_vv2_317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26096)=319 */ {26096, xed3_phash_find_mapevex_map1_opcode0x78_vv2_319_l1}, +/*h(20928)=320 */ {20928, xed3_phash_find_mapevex_map1_opcode0x78_vv2_320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9605)=322 */ {9605, xed3_phash_find_mapevex_map1_opcode0x78_vv2_322_l1}, +/*h(7631)=323 */ {7631, xed3_phash_find_mapevex_map1_opcode0x78_vv2_323_l1}, +/*h(30133)=324 */ {30133, xed3_phash_find_mapevex_map1_opcode0x78_vv2_324_l1}, +/*h(24965)=325 */ {24965, xed3_phash_find_mapevex_map1_opcode0x78_vv2_325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22004)=327 */ {22004, xed3_phash_find_mapevex_map1_opcode0x78_vv2_327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5513)=329 */ {5513, xed3_phash_find_mapevex_map1_opcode0x78_vv2_329_l1}, +/*h(4526)=330 */ {4526, xed3_phash_find_mapevex_map1_opcode0x78_vv2_330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20873)=332 */ {20873, xed3_phash_find_mapevex_map1_opcode0x78_vv2_332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1421)=336 */ {1421, xed3_phash_find_mapevex_map1_opcode0x78_vv2_336_l1}, +/*h(434)=337 */ {434, xed3_phash_find_mapevex_map1_opcode0x78_vv2_337_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16781)=339 */ {16781, xed3_phash_find_mapevex_map1_opcode0x78_vv2_339_l1}, +/*h(10626)=340 */ {10626, xed3_phash_find_mapevex_map1_opcode0x78_vv2_340_l1}, +/*h(9639)=341 */ {9639, xed3_phash_find_mapevex_map1_opcode0x78_vv2_341_l1}, +/*h(8652)=342 */ {8652, xed3_phash_find_mapevex_map1_opcode0x78_vv2_342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25986)=344 */ {25986, xed3_phash_find_mapevex_map1_opcode0x78_vv2_344_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17857)=346 */ {17857, xed3_phash_find_mapevex_map1_opcode0x78_vv2_346_l1}, +/*h(16870)=347 */ {16870, xed3_phash_find_mapevex_map1_opcode0x78_vv2_347_l1}, +/*h(5547)=348 */ {5547, xed3_phash_find_mapevex_map1_opcode0x78_vv2_348_l1}, +/*h(4560)=349 */ {4560, xed3_phash_find_mapevex_map1_opcode0x78_vv2_349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21894)=351 */ {21894, xed3_phash_find_mapevex_map1_opcode0x78_vv2_351_l1}, +/*h(20907)=352 */ {20907, xed3_phash_find_mapevex_map1_opcode0x78_vv2_352_l1}, +/*h(13765)=353 */ {13765, xed3_phash_find_mapevex_map1_opcode0x78_vv2_353_l1}, +/*h(8597)=354 */ {8597, xed3_phash_find_mapevex_map1_opcode0x78_vv2_354_l1}, +/*h(2442)=355 */ {2442, xed3_phash_find_mapevex_map1_opcode0x78_vv2_355_l1}, +/*h(1455)=356 */ {1455, xed3_phash_find_mapevex_map1_opcode0x78_vv2_356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17802)=358 */ {17802, xed3_phash_find_mapevex_map1_opcode0x78_vv2_358_l1}, +/*h(16815)=359 */ {16815, xed3_phash_find_mapevex_map1_opcode0x78_vv2_359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9673)=361 */ {9673, xed3_phash_find_mapevex_map1_opcode0x78_vv2_361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26020)=363 */ {26020, xed3_phash_find_mapevex_map1_opcode0x78_vv2_363_l1}, +/*h(25033)=364 */ {25033, xed3_phash_find_mapevex_map1_opcode0x78_vv2_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17891)=366 */ {17891, xed3_phash_find_mapevex_map1_opcode0x78_vv2_366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5581)=368 */ {5581, xed3_phash_find_mapevex_map1_opcode0x78_vv2_368_l1}, +/*h(4594)=369 */ {4594, xed3_phash_find_mapevex_map1_opcode0x78_vv2_369_l1}, +/*h(21928)=370 */ {21928, xed3_phash_find_mapevex_map1_opcode0x78_vv2_370_l1}, +/*h(20941)=371 */ {20941, xed3_phash_find_mapevex_map1_opcode0x78_vv2_371_l1}, +/*h(14786)=372 */ {14786, xed3_phash_find_mapevex_map1_opcode0x78_vv2_372_l1}, +/*h(9618)=373 */ {9618, xed3_phash_find_mapevex_map1_opcode0x78_vv2_373_l1}, +/*h(3463)=374 */ {3463, xed3_phash_find_mapevex_map1_opcode0x78_vv2_374_l1}, +/*h(1489)=375 */ {1489, xed3_phash_find_mapevex_map1_opcode0x78_vv2_375_l1}, +/*h(24978)=376 */ {24978, xed3_phash_find_mapevex_map1_opcode0x78_vv2_376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17836)=378 */ {17836, xed3_phash_find_mapevex_map1_opcode0x78_vv2_378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5526)=380 */ {5526, xed3_phash_find_mapevex_map1_opcode0x78_vv2_380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26054)=383 */ {26054, xed3_phash_find_mapevex_map1_opcode0x78_vv2_383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8576)=386 */ {8576, xed3_phash_find_mapevex_map1_opcode0x78_vv2_386_l1}, +/*h(6602)=387 */ {6602, xed3_phash_find_mapevex_map1_opcode0x78_vv2_387_l1}, +/*h(5615)=388 */ {5615, xed3_phash_find_mapevex_map1_opcode0x78_vv2_388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21962)=390 */ {21962, xed3_phash_find_mapevex_map1_opcode0x78_vv2_390_l1}, +/*h(20975)=391 */ {20975, xed3_phash_find_mapevex_map1_opcode0x78_vv2_391_l1}, +/*h(9652)=392 */ {9652, xed3_phash_find_mapevex_map1_opcode0x78_vv2_392_l1}, +/*h(4484)=393 */ {4484, xed3_phash_find_mapevex_map1_opcode0x78_vv2_393_l1}, +/*h(2510)=394 */ {2510, xed3_phash_find_mapevex_map1_opcode0x78_vv2_394_l1}, +/*h(25999)=395 */ {25999, xed3_phash_find_mapevex_map1_opcode0x78_vv2_395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17870)=397 */ {17870, xed3_phash_find_mapevex_map1_opcode0x78_vv2_397_l1}, +/*h(16883)=398 */ {16883, xed3_phash_find_mapevex_map1_opcode0x78_vv2_398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(392)=400 */ {392, xed3_phash_find_mapevex_map1_opcode0x78_vv2_400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21907)=402 */ {21907, xed3_phash_find_mapevex_map1_opcode0x78_vv2_402_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8610)=405 */ {8610, xed3_phash_find_mapevex_map1_opcode0x78_vv2_405_l1}, +/*h(7623)=406 */ {7623, xed3_phash_find_mapevex_map1_opcode0x78_vv2_406_l1}, +/*h(30125)=407 */ {30125, xed3_phash_find_mapevex_map1_opcode0x78_vv2_407_l1}, +/*h(481)=408 */ {481, xed3_phash_find_mapevex_map1_opcode0x78_vv2_408_l1}, +/*h(17815)=409 */ {17815, xed3_phash_find_mapevex_map1_opcode0x78_vv2_409_l1}, +/*h(21996)=410 */ {21996, xed3_phash_find_mapevex_map1_opcode0x78_vv2_410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5505)=412 */ {5505, xed3_phash_find_mapevex_map1_opcode0x78_vv2_412_l1}, +/*h(4518)=413 */ {4518, xed3_phash_find_mapevex_map1_opcode0x78_vv2_413_l1}, +/*h(26033)=414 */ {26033, xed3_phash_find_mapevex_map1_opcode0x78_vv2_414_l1}, +/*h(20865)=415 */ {20865, xed3_phash_find_mapevex_map1_opcode0x78_vv2_415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17904)=417 */ {17904, xed3_phash_find_mapevex_map1_opcode0x78_vv2_417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1413)=419 */ {1413, xed3_phash_find_mapevex_map1_opcode0x78_vv2_419_l1}, +/*h(426)=420 */ {426, xed3_phash_find_mapevex_map1_opcode0x78_vv2_420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21941)=422 */ {21941, xed3_phash_find_mapevex_map1_opcode0x78_vv2_422_l1}, +/*h(15786)=423 */ {15786, xed3_phash_find_mapevex_map1_opcode0x78_vv2_423_l1}, +/*h(14799)=424 */ {14799, xed3_phash_find_mapevex_map1_opcode0x78_vv2_424_l1}, +/*h(8644)=425 */ {8644, xed3_phash_find_mapevex_map1_opcode0x78_vv2_425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30159)=427 */ {30159, xed3_phash_find_mapevex_map1_opcode0x78_vv2_427_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11694)=430 */ {11694, xed3_phash_find_mapevex_map1_opcode0x78_vv2_430_l1}, +/*h(5539)=431 */ {5539, xed3_phash_find_mapevex_map1_opcode0x78_vv2_431_l1}, +/*h(4552)=432 */ {4552, xed3_phash_find_mapevex_map1_opcode0x78_vv2_432_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26067)=434 */ {26067, xed3_phash_find_mapevex_map1_opcode0x78_vv2_434_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8589)=437 */ {8589, xed3_phash_find_mapevex_map1_opcode0x78_vv2_437_l1}, +/*h(6615)=438 */ {6615, xed3_phash_find_mapevex_map1_opcode0x78_vv2_438_l1}, +/*h(1447)=439 */ {1447, xed3_phash_find_mapevex_map1_opcode0x78_vv2_439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17794)=441 */ {17794, xed3_phash_find_mapevex_map1_opcode0x78_vv2_441_l1}, +/*h(16807)=442 */ {16807, xed3_phash_find_mapevex_map1_opcode0x78_vv2_442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9665)=444 */ {9665, xed3_phash_find_mapevex_map1_opcode0x78_vv2_444_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25025)=447 */ {25025, xed3_phash_find_mapevex_map1_opcode0x78_vv2_447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5573)=451 */ {5573, xed3_phash_find_mapevex_map1_opcode0x78_vv2_451_l1}, +/*h(405)=452 */ {405, xed3_phash_find_mapevex_map1_opcode0x78_vv2_452_l1}, +/*h(21920)=453 */ {21920, xed3_phash_find_mapevex_map1_opcode0x78_vv2_453_l1}, +/*h(26101)=454 */ {26101, xed3_phash_find_mapevex_map1_opcode0x78_vv2_454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9610)=456 */ {9610, xed3_phash_find_mapevex_map1_opcode0x78_vv2_456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1481)=458 */ {1481, xed3_phash_find_mapevex_map1_opcode0x78_vv2_458_l1}, +/*h(24970)=459 */ {24970, xed3_phash_find_mapevex_map1_opcode0x78_vv2_459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17828)=461 */ {17828, xed3_phash_find_mapevex_map1_opcode0x78_vv2_461_l1}, +/*h(15854)=462 */ {15854, xed3_phash_find_mapevex_map1_opcode0x78_vv2_462_l1}, +/*h(5518)=463 */ {5518, xed3_phash_find_mapevex_map1_opcode0x78_vv2_463_l1}, +/*h(4531)=464 */ {4531, xed3_phash_find_mapevex_map1_opcode0x78_vv2_464_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20878)=466 */ {20878, xed3_phash_find_mapevex_map1_opcode0x78_vv2_466_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12749)=469 */ {12749, xed3_phash_find_mapevex_map1_opcode0x78_vv2_469_l1}, +/*h(1426)=470 */ {1426, xed3_phash_find_mapevex_map1_opcode0x78_vv2_470_l1}, +/*h(5607)=471 */ {5607, xed3_phash_find_mapevex_map1_opcode0x78_vv2_471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21954)=473 */ {21954, xed3_phash_find_mapevex_map1_opcode0x78_vv2_473_l1}, +/*h(20967)=474 */ {20967, xed3_phash_find_mapevex_map1_opcode0x78_vv2_474_l1}, +/*h(9644)=475 */ {9644, xed3_phash_find_mapevex_map1_opcode0x78_vv2_475_l1}, +/*h(8657)=476 */ {8657, xed3_phash_find_mapevex_map1_opcode0x78_vv2_476_l1}, +/*h(2502)=477 */ {2502, xed3_phash_find_mapevex_map1_opcode0x78_vv2_477_l1}, +/*h(25991)=478 */ {25991, xed3_phash_find_mapevex_map1_opcode0x78_vv2_478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17862)=480 */ {17862, xed3_phash_find_mapevex_map1_opcode0x78_vv2_480_l1}, +/*h(16875)=481 */ {16875, xed3_phash_find_mapevex_map1_opcode0x78_vv2_481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5552)=483 */ {5552, xed3_phash_find_mapevex_map1_opcode0x78_vv2_483_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21899)=485 */ {21899, xed3_phash_find_mapevex_map1_opcode0x78_vv2_485_l1}, +/*h(20912)=486 */ {20912, xed3_phash_find_mapevex_map1_opcode0x78_vv2_486_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12783)=488 */ {12783, xed3_phash_find_mapevex_map1_opcode0x78_vv2_488_l1}, +/*h(2447)=489 */ {2447, xed3_phash_find_mapevex_map1_opcode0x78_vv2_489_l1}, +/*h(30117)=490 */ {30117, xed3_phash_find_mapevex_map1_opcode0x78_vv2_490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17807)=492 */ {17807, xed3_phash_find_mapevex_map1_opcode0x78_vv2_492_l1}, +/*h(21988)=493 */ {21988, xed3_phash_find_mapevex_map1_opcode0x78_vv2_493_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9678)=495 */ {9678, xed3_phash_find_mapevex_map1_opcode0x78_vv2_495_l1}, +/*h(8691)=496 */ {8691, xed3_phash_find_mapevex_map1_opcode0x78_vv2_496_l1}, +/*h(26025)=497 */ {26025, xed3_phash_find_mapevex_map1_opcode0x78_vv2_497_l1}, +/*h(25038)=498 */ {25038, xed3_phash_find_mapevex_map1_opcode0x78_vv2_498_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17896)=500 */ {17896, xed3_phash_find_mapevex_map1_opcode0x78_vv2_500_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5586)=502 */ {5586, xed3_phash_find_mapevex_map1_opcode0x78_vv2_502_l1}, +/*h(418)=503 */ {418, xed3_phash_find_mapevex_map1_opcode0x78_vv2_503_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21933)=505 */ {21933, xed3_phash_find_mapevex_map1_opcode0x78_vv2_505_l1}, +/*h(15778)=506 */ {15778, xed3_phash_find_mapevex_map1_opcode0x78_vv2_506_l1}, +/*h(9623)=507 */ {9623, xed3_phash_find_mapevex_map1_opcode0x78_vv2_507_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30151)=510 */ {30151, xed3_phash_find_mapevex_map1_opcode0x78_vv2_510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17841)=512 */ {17841, xed3_phash_find_mapevex_map1_opcode0x78_vv2_512_l1}, +/*h(11686)=513 */ {11686, xed3_phash_find_mapevex_map1_opcode0x78_vv2_513_l1}, +/*h(9712)=514 */ {9712, xed3_phash_find_mapevex_map1_opcode0x78_vv2_514_l1}, +/*h(4544)=515 */ {4544, xed3_phash_find_mapevex_map1_opcode0x78_vv2_515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26059)=517 */ {26059, xed3_phash_find_mapevex_map1_opcode0x78_vv2_517_l1}, +/*h(25072)=518 */ {25072, xed3_phash_find_mapevex_map1_opcode0x78_vv2_518_l1}, +/*h(13749)=519 */ {13749, xed3_phash_find_mapevex_map1_opcode0x78_vv2_519_l1}, +/*h(7594)=520 */ {7594, xed3_phash_find_mapevex_map1_opcode0x78_vv2_520_l1}, +/*h(6607)=521 */ {6607, xed3_phash_find_mapevex_map1_opcode0x78_vv2_521_l1}, +/*h(5620)=522 */ {5620, xed3_phash_find_mapevex_map1_opcode0x78_vv2_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21967)=524 */ {21967, xed3_phash_find_mapevex_map1_opcode0x78_vv2_524_l1}, +/*h(20980)=525 */ {20980, xed3_phash_find_mapevex_map1_opcode0x78_vv2_525_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4489)=527 */ {4489, xed3_phash_find_mapevex_map1_opcode0x78_vv2_527_l1}, +/*h(3502)=528 */ {3502, xed3_phash_find_mapevex_map1_opcode0x78_vv2_528_l1}, +/*h(26004)=529 */ {26004, xed3_phash_find_mapevex_map1_opcode0x78_vv2_529_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17875)=532 */ {17875, xed3_phash_find_mapevex_map1_opcode0x78_vv2_532_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(397)=534 */ {397, xed3_phash_find_mapevex_map1_opcode0x78_vv2_534_l1}, +/*h(4578)=535 */ {4578, xed3_phash_find_mapevex_map1_opcode0x78_vv2_535_l1}, +/*h(26093)=536 */ {26093, xed3_phash_find_mapevex_map1_opcode0x78_vv2_536_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9602)=539 */ {9602, xed3_phash_find_mapevex_map1_opcode0x78_vv2_539_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1473)=541 */ {1473, xed3_phash_find_mapevex_map1_opcode0x78_vv2_541_l1}, +/*h(24962)=542 */ {24962, xed3_phash_find_mapevex_map1_opcode0x78_vv2_542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22001)=544 */ {22001, xed3_phash_find_mapevex_map1_opcode0x78_vv2_544_l1}, +/*h(15846)=545 */ {15846, xed3_phash_find_mapevex_map1_opcode0x78_vv2_545_l1}, +/*h(5510)=546 */ {5510, xed3_phash_find_mapevex_map1_opcode0x78_vv2_546_l1}, +/*h(4523)=547 */ {4523, xed3_phash_find_mapevex_map1_opcode0x78_vv2_547_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26038)=549 */ {26038, xed3_phash_find_mapevex_map1_opcode0x78_vv2_549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17909)=551 */ {17909, xed3_phash_find_mapevex_map1_opcode0x78_vv2_551_l1}, +/*h(11754)=552 */ {11754, xed3_phash_find_mapevex_map1_opcode0x78_vv2_552_l1}, +/*h(1418)=553 */ {1418, xed3_phash_find_mapevex_map1_opcode0x78_vv2_553_l1}, +/*h(431)=554 */ {431, xed3_phash_find_mapevex_map1_opcode0x78_vv2_554_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16778)=556 */ {16778, xed3_phash_find_mapevex_map1_opcode0x78_vv2_556_l1}, +/*h(15791)=557 */ {15791, xed3_phash_find_mapevex_map1_opcode0x78_vv2_557_l1}, +/*h(9636)=558 */ {9636, xed3_phash_find_mapevex_map1_opcode0x78_vv2_558_l1}, +/*h(8649)=559 */ {8649, xed3_phash_find_mapevex_map1_opcode0x78_vv2_559_l1}, +/*h(7662)=560 */ {7662, xed3_phash_find_mapevex_map1_opcode0x78_vv2_560_l1}, +/*h(1507)=561 */ {1507, xed3_phash_find_mapevex_map1_opcode0x78_vv2_561_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16867)=564 */ {16867, xed3_phash_find_mapevex_map1_opcode0x78_vv2_564_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5544)=566 */ {5544, xed3_phash_find_mapevex_map1_opcode0x78_vv2_566_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21891)=568 */ {21891, xed3_phash_find_mapevex_map1_opcode0x78_vv2_568_l1}, +/*h(20904)=569 */ {20904, xed3_phash_find_mapevex_map1_opcode0x78_vv2_569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8594)=571 */ {8594, xed3_phash_find_mapevex_map1_opcode0x78_vv2_571_l1}, +/*h(2439)=572 */ {2439, xed3_phash_find_mapevex_map1_opcode0x78_vv2_572_l1}, +/*h(1452)=573 */ {1452, xed3_phash_find_mapevex_map1_opcode0x78_vv2_573_l1}, +/*h(465)=574 */ {465, xed3_phash_find_mapevex_map1_opcode0x78_vv2_574_l1}, +/*h(17799)=575 */ {17799, xed3_phash_find_mapevex_map1_opcode0x78_vv2_575_l1}, +/*h(16812)=576 */ {16812, xed3_phash_find_mapevex_map1_opcode0x78_vv2_576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9670)=578 */ {9670, xed3_phash_find_mapevex_map1_opcode0x78_vv2_578_l1}, +/*h(8683)=579 */ {8683, xed3_phash_find_mapevex_map1_opcode0x78_vv2_579_l1}, +/*h(26017)=580 */ {26017, xed3_phash_find_mapevex_map1_opcode0x78_vv2_580_l1}, +/*h(25030)=581 */ {25030, xed3_phash_find_mapevex_map1_opcode0x78_vv2_581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17888)=583 */ {17888, xed3_phash_find_mapevex_map1_opcode0x78_vv2_583_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5578)=585 */ {5578, xed3_phash_find_mapevex_map1_opcode0x78_vv2_585_l1}, +/*h(4591)=586 */ {4591, xed3_phash_find_mapevex_map1_opcode0x78_vv2_586_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21925)=588 */ {21925, xed3_phash_find_mapevex_map1_opcode0x78_vv2_588_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9615)=590 */ {9615, xed3_phash_find_mapevex_map1_opcode0x78_vv2_590_l1}, +/*h(8628)=591 */ {8628, xed3_phash_find_mapevex_map1_opcode0x78_vv2_591_l1}, +/*h(1486)=592 */ {1486, xed3_phash_find_mapevex_map1_opcode0x78_vv2_592_l1}, +/*h(24975)=593 */ {24975, xed3_phash_find_mapevex_map1_opcode0x78_vv2_593_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17833)=595 */ {17833, xed3_phash_find_mapevex_map1_opcode0x78_vv2_595_l1}, +/*h(16846)=596 */ {16846, xed3_phash_find_mapevex_map1_opcode0x78_vv2_596_l1}, +/*h(5523)=597 */ {5523, xed3_phash_find_mapevex_map1_opcode0x78_vv2_597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26051)=600 */ {26051, xed3_phash_find_mapevex_map1_opcode0x78_vv2_600_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13741)=602 */ {13741, xed3_phash_find_mapevex_map1_opcode0x78_vv2_602_l1}, +/*h(7586)=603 */ {7586, xed3_phash_find_mapevex_map1_opcode0x78_vv2_603_l1}, +/*h(6599)=604 */ {6599, xed3_phash_find_mapevex_map1_opcode0x78_vv2_604_l1}, +/*h(1431)=605 */ {1431, xed3_phash_find_mapevex_map1_opcode0x78_vv2_605_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21959)=607 */ {21959, xed3_phash_find_mapevex_map1_opcode0x78_vv2_607_l1}, +/*h(16791)=608 */ {16791, xed3_phash_find_mapevex_map1_opcode0x78_vv2_608_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9649)=610 */ {9649, xed3_phash_find_mapevex_map1_opcode0x78_vv2_610_l1}, +/*h(3494)=611 */ {3494, xed3_phash_find_mapevex_map1_opcode0x78_vv2_611_l1}, +/*h(25996)=612 */ {25996, xed3_phash_find_mapevex_map1_opcode0x78_vv2_612_l1}, +/*h(25009)=613 */ {25009, xed3_phash_find_mapevex_map1_opcode0x78_vv2_613_l1}, +/*h(17867)=614 */ {17867, xed3_phash_find_mapevex_map1_opcode0x78_vv2_614_l1}, +/*h(16880)=615 */ {16880, xed3_phash_find_mapevex_map1_opcode0x78_vv2_615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5557)=617 */ {5557, xed3_phash_find_mapevex_map1_opcode0x78_vv2_617_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21904)=619 */ {21904, xed3_phash_find_mapevex_map1_opcode0x78_vv2_619_l1}, +/*h(20917)=620 */ {20917, xed3_phash_find_mapevex_map1_opcode0x78_vv2_620_l1}, +/*h(14762)=621 */ {14762, xed3_phash_find_mapevex_map1_opcode0x78_vv2_621_l1}, +/*h(13775)=622 */ {13775, xed3_phash_find_mapevex_map1_opcode0x78_vv2_622_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(29135)=625 */ {29135, xed3_phash_find_mapevex_map1_opcode0x78_vv2_625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17812)=627 */ {17812, xed3_phash_find_mapevex_map1_opcode0x78_vv2_627_l1}, +/*h(10670)=628 */ {10670, xed3_phash_find_mapevex_map1_opcode0x78_vv2_628_l1}, +/*h(9683)=629 */ {9683, xed3_phash_find_mapevex_map1_opcode0x78_vv2_629_l1}, +/*h(4515)=630 */ {4515, xed3_phash_find_mapevex_map1_opcode0x78_vv2_630_l1}, +/*h(26030)=631 */ {26030, xed3_phash_find_mapevex_map1_opcode0x78_vv2_631_l1}, +/*h(25043)=632 */ {25043, xed3_phash_find_mapevex_map1_opcode0x78_vv2_632_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17901)=634 */ {17901, xed3_phash_find_mapevex_map1_opcode0x78_vv2_634_l1}, +/*h(11746)=635 */ {11746, xed3_phash_find_mapevex_map1_opcode0x78_vv2_635_l1}, +/*h(1410)=636 */ {1410, xed3_phash_find_mapevex_map1_opcode0x78_vv2_636_l1}, +/*h(423)=637 */ {423, xed3_phash_find_mapevex_map1_opcode0x78_vv2_637_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21938)=639 */ {21938, xed3_phash_find_mapevex_map1_opcode0x78_vv2_639_l1}, +/*h(15783)=640 */ {15783, xed3_phash_find_mapevex_map1_opcode0x78_vv2_640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8641)=642 */ {8641, xed3_phash_find_mapevex_map1_opcode0x78_vv2_642_l1}, +/*h(7654)=643 */ {7654, xed3_phash_find_mapevex_map1_opcode0x78_vv2_643_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17846)=646 */ {17846, xed3_phash_find_mapevex_map1_opcode0x78_vv2_646_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5536)=649 */ {5536, xed3_phash_find_mapevex_map1_opcode0x78_vv2_649_l1}, +/*h(3562)=650 */ {3562, xed3_phash_find_mapevex_map1_opcode0x78_vv2_650_l1}, +/*h(26064)=651 */ {26064, xed3_phash_find_mapevex_map1_opcode0x78_vv2_651_l1}, +/*h(20896)=652 */ {20896, xed3_phash_find_mapevex_map1_opcode0x78_vv2_652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8586)=654 */ {8586, xed3_phash_find_mapevex_map1_opcode0x78_vv2_654_l1}, +/*h(7599)=655 */ {7599, xed3_phash_find_mapevex_map1_opcode0x78_vv2_655_l1}, +/*h(30101)=656 */ {30101, xed3_phash_find_mapevex_map1_opcode0x78_vv2_656_l1}, +/*h(457)=657 */ {457, xed3_phash_find_mapevex_map1_opcode0x78_vv2_657_l1}, +/*h(21972)=658 */ {21972, xed3_phash_find_mapevex_map1_opcode0x78_vv2_658_l1}, +/*h(16804)=659 */ {16804, xed3_phash_find_mapevex_map1_opcode0x78_vv2_659_l1}, +/*h(14830)=660 */ {14830, xed3_phash_find_mapevex_map1_opcode0x78_vv2_660_l1}, +/*h(4494)=661 */ {4494, xed3_phash_find_mapevex_map1_opcode0x78_vv2_661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5570)=668 */ {5570, xed3_phash_find_mapevex_map1_opcode0x78_vv2_668_l1}, +/*h(402)=669 */ {402, xed3_phash_find_mapevex_map1_opcode0x78_vv2_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26098)=671 */ {26098, xed3_phash_find_mapevex_map1_opcode0x78_vv2_671_l1}, +/*h(15762)=672 */ {15762, xed3_phash_find_mapevex_map1_opcode0x78_vv2_672_l1}, +/*h(9607)=673 */ {9607, xed3_phash_find_mapevex_map1_opcode0x78_vv2_673_l1}, +/*h(8620)=674 */ {8620, xed3_phash_find_mapevex_map1_opcode0x78_vv2_674_l1}, +/*h(30135)=675 */ {30135, xed3_phash_find_mapevex_map1_opcode0x78_vv2_675_l1}, +/*h(24967)=676 */ {24967, xed3_phash_find_mapevex_map1_opcode0x78_vv2_676_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17825)=678 */ {17825, xed3_phash_find_mapevex_map1_opcode0x78_vv2_678_l1}, +/*h(11670)=679 */ {11670, xed3_phash_find_mapevex_map1_opcode0x78_vv2_679_l1}, +/*h(5515)=680 */ {5515, xed3_phash_find_mapevex_map1_opcode0x78_vv2_680_l1}, +/*h(4528)=681 */ {4528, xed3_phash_find_mapevex_map1_opcode0x78_vv2_681_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20875)=683 */ {20875, xed3_phash_find_mapevex_map1_opcode0x78_vv2_683_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13733)=685 */ {13733, xed3_phash_find_mapevex_map1_opcode0x78_vv2_685_l1}, +/*h(11759)=686 */ {11759, xed3_phash_find_mapevex_map1_opcode0x78_vv2_686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1423)=688 */ {1423, xed3_phash_find_mapevex_map1_opcode0x78_vv2_688_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16783)=691 */ {16783, xed3_phash_find_mapevex_map1_opcode0x78_vv2_691_l1}, +/*h(9641)=692 */ {9641, xed3_phash_find_mapevex_map1_opcode0x78_vv2_692_l1}, +/*h(8654)=693 */ {8654, xed3_phash_find_mapevex_map1_opcode0x78_vv2_693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25988)=695 */ {25988, xed3_phash_find_mapevex_map1_opcode0x78_vv2_695_l1}, +/*h(25001)=696 */ {25001, xed3_phash_find_mapevex_map1_opcode0x78_vv2_696_l1}, +/*h(17859)=697 */ {17859, xed3_phash_find_mapevex_map1_opcode0x78_vv2_697_l1}, +/*h(16872)=698 */ {16872, xed3_phash_find_mapevex_map1_opcode0x78_vv2_698_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5549)=700 */ {5549, xed3_phash_find_mapevex_map1_opcode0x78_vv2_700_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21896)=702 */ {21896, xed3_phash_find_mapevex_map1_opcode0x78_vv2_702_l1}, +/*h(20909)=703 */ {20909, xed3_phash_find_mapevex_map1_opcode0x78_vv2_703_l1}, +/*h(14754)=704 */ {14754, xed3_phash_find_mapevex_map1_opcode0x78_vv2_704_l1}, +/*h(13767)=705 */ {13767, xed3_phash_find_mapevex_map1_opcode0x78_vv2_705_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1457)=707 */ {1457, xed3_phash_find_mapevex_map1_opcode0x78_vv2_707_l1}, +/*h(470)=708 */ {470, xed3_phash_find_mapevex_map1_opcode0x78_vv2_708_l1}, +/*h(17804)=709 */ {17804, xed3_phash_find_mapevex_map1_opcode0x78_vv2_709_l1}, +/*h(21985)=710 */ {21985, xed3_phash_find_mapevex_map1_opcode0x78_vv2_710_l1}, +/*h(15830)=711 */ {15830, xed3_phash_find_mapevex_map1_opcode0x78_vv2_711_l1}, +/*h(9675)=712 */ {9675, xed3_phash_find_mapevex_map1_opcode0x78_vv2_712_l1}, +/*h(8688)=713 */ {8688, xed3_phash_find_mapevex_map1_opcode0x78_vv2_713_l1}, +/*h(26022)=714 */ {26022, xed3_phash_find_mapevex_map1_opcode0x78_vv2_714_l1}, +/*h(25035)=715 */ {25035, xed3_phash_find_mapevex_map1_opcode0x78_vv2_715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17893)=717 */ {17893, xed3_phash_find_mapevex_map1_opcode0x78_vv2_717_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5583)=719 */ {5583, xed3_phash_find_mapevex_map1_opcode0x78_vv2_719_l1}, +/*h(4596)=720 */ {4596, xed3_phash_find_mapevex_map1_opcode0x78_vv2_720_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21930)=722 */ {21930, xed3_phash_find_mapevex_map1_opcode0x78_vv2_722_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9620)=724 */ {9620, xed3_phash_find_mapevex_map1_opcode0x78_vv2_724_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2478)=726 */ {2478, xed3_phash_find_mapevex_map1_opcode0x78_vv2_726_l1}, +/*h(1491)=727 */ {1491, xed3_phash_find_mapevex_map1_opcode0x78_vv2_727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17838)=729 */ {17838, xed3_phash_find_mapevex_map1_opcode0x78_vv2_729_l1}, +/*h(16851)=730 */ {16851, xed3_phash_find_mapevex_map1_opcode0x78_vv2_730_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9709)=732 */ {9709, xed3_phash_find_mapevex_map1_opcode0x78_vv2_732_l1}, +/*h(3554)=733 */ {3554, xed3_phash_find_mapevex_map1_opcode0x78_vv2_733_l1}, +/*h(26056)=734 */ {26056, xed3_phash_find_mapevex_map1_opcode0x78_vv2_734_l1}, +/*h(25069)=735 */ {25069, xed3_phash_find_mapevex_map1_opcode0x78_vv2_735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8578)=737 */ {8578, xed3_phash_find_mapevex_map1_opcode0x78_vv2_737_l1}, +/*h(7591)=738 */ {7591, xed3_phash_find_mapevex_map1_opcode0x78_vv2_738_l1}, +/*h(30093)=739 */ {30093, xed3_phash_find_mapevex_map1_opcode0x78_vv2_739_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21964)=741 */ {21964, xed3_phash_find_mapevex_map1_opcode0x78_vv2_741_l1}, +/*h(20977)=742 */ {20977, xed3_phash_find_mapevex_map1_opcode0x78_vv2_742_l1}, +/*h(14822)=743 */ {14822, xed3_phash_find_mapevex_map1_opcode0x78_vv2_743_l1}, +/*h(9654)=744 */ {9654, xed3_phash_find_mapevex_map1_opcode0x78_vv2_744_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26001)=746 */ {26001, xed3_phash_find_mapevex_map1_opcode0x78_vv2_746_l1}, +/*h(25014)=747 */ {25014, xed3_phash_find_mapevex_map1_opcode0x78_vv2_747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17872)=749 */ {17872, xed3_phash_find_mapevex_map1_opcode0x78_vv2_749_l1}, +/*h(10730)=750 */ {10730, xed3_phash_find_mapevex_map1_opcode0x78_vv2_750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(394)=752 */ {394, xed3_phash_find_mapevex_map1_opcode0x78_vv2_752_l1}, +/*h(21909)=753 */ {21909, xed3_phash_find_mapevex_map1_opcode0x78_vv2_753_l1}, +/*h(26090)=754 */ {26090, xed3_phash_find_mapevex_map1_opcode0x78_vv2_754_l1}, +/*h(15754)=755 */ {15754, xed3_phash_find_mapevex_map1_opcode0x78_vv2_755_l1}, +/*h(8612)=756 */ {8612, xed3_phash_find_mapevex_map1_opcode0x78_vv2_756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30127)=758 */ {30127, xed3_phash_find_mapevex_map1_opcode0x78_vv2_758_l1}, +/*h(483)=759 */ {483, xed3_phash_find_mapevex_map1_opcode0x78_vv2_759_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21998)=761 */ {21998, xed3_phash_find_mapevex_map1_opcode0x78_vv2_761_l1}, +/*h(11662)=762 */ {11662, xed3_phash_find_mapevex_map1_opcode0x78_vv2_762_l1}, +/*h(5507)=763 */ {5507, xed3_phash_find_mapevex_map1_opcode0x78_vv2_763_l1}, +/*h(4520)=764 */ {4520, xed3_phash_find_mapevex_map1_opcode0x78_vv2_764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26035)=766 */ {26035, xed3_phash_find_mapevex_map1_opcode0x78_vv2_766_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17906)=768 */ {17906, xed3_phash_find_mapevex_map1_opcode0x78_vv2_768_l1}, +/*h(7570)=769 */ {7570, xed3_phash_find_mapevex_map1_opcode0x78_vv2_769_l1}, +/*h(1415)=770 */ {1415, xed3_phash_find_mapevex_map1_opcode0x78_vv2_770_l1}, +/*h(428)=771 */ {428, xed3_phash_find_mapevex_map1_opcode0x78_vv2_771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21943)=773 */ {21943, xed3_phash_find_mapevex_map1_opcode0x78_vv2_773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9633)=775 */ {9633, xed3_phash_find_mapevex_map1_opcode0x78_vv2_775_l1}, +/*h(8646)=776 */ {8646, xed3_phash_find_mapevex_map1_opcode0x78_vv2_776_l1}, +/*h(3478)=777 */ {3478, xed3_phash_find_mapevex_map1_opcode0x78_vv2_777_l1}, +/*h(1504)=778 */ {1504, xed3_phash_find_mapevex_map1_opcode0x78_vv2_778_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16864)=781 */ {16864, xed3_phash_find_mapevex_map1_opcode0x78_vv2_781_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5541)=783 */ {5541, xed3_phash_find_mapevex_map1_opcode0x78_vv2_783_l1}, +/*h(3567)=784 */ {3567, xed3_phash_find_mapevex_map1_opcode0x78_vv2_784_l1}, +/*h(21888)=785 */ {21888, xed3_phash_find_mapevex_map1_opcode0x78_vv2_785_l1}, +/*h(20901)=786 */ {20901, xed3_phash_find_mapevex_map1_opcode0x78_vv2_786_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8591)=788 */ {8591, xed3_phash_find_mapevex_map1_opcode0x78_vv2_788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1449)=790 */ {1449, xed3_phash_find_mapevex_map1_opcode0x78_vv2_790_l1}, +/*h(462)=791 */ {462, xed3_phash_find_mapevex_map1_opcode0x78_vv2_791_l1}, +/*h(17796)=792 */ {17796, xed3_phash_find_mapevex_map1_opcode0x78_vv2_792_l1}, +/*h(16809)=793 */ {16809, xed3_phash_find_mapevex_map1_opcode0x78_vv2_793_l1}, +/*h(15822)=794 */ {15822, xed3_phash_find_mapevex_map1_opcode0x78_vv2_794_l1}, +/*h(9667)=795 */ {9667, xed3_phash_find_mapevex_map1_opcode0x78_vv2_795_l1}, +/*h(8680)=796 */ {8680, xed3_phash_find_mapevex_map1_opcode0x78_vv2_796_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25027)=798 */ {25027, xed3_phash_find_mapevex_map1_opcode0x78_vv2_798_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12717)=800 */ {12717, xed3_phash_find_mapevex_map1_opcode0x78_vv2_800_l1}, +/*h(11730)=801 */ {11730, xed3_phash_find_mapevex_map1_opcode0x78_vv2_801_l1}, +/*h(5575)=802 */ {5575, xed3_phash_find_mapevex_map1_opcode0x78_vv2_802_l1}, +/*h(407)=803 */ {407, xed3_phash_find_mapevex_map1_opcode0x78_vv2_803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21922)=805 */ {21922, xed3_phash_find_mapevex_map1_opcode0x78_vv2_805_l1}, +/*h(15767)=806 */ {15767, xed3_phash_find_mapevex_map1_opcode0x78_vv2_806_l1}, +/*h(9612)=807 */ {9612, xed3_phash_find_mapevex_map1_opcode0x78_vv2_807_l1}, +/*h(7638)=808 */ {7638, xed3_phash_find_mapevex_map1_opcode0x78_vv2_808_l1}, +/*h(2470)=809 */ {2470, xed3_phash_find_mapevex_map1_opcode0x78_vv2_809_l1}, +/*h(1483)=810 */ {1483, xed3_phash_find_mapevex_map1_opcode0x78_vv2_810_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17830)=812 */ {17830, xed3_phash_find_mapevex_map1_opcode0x78_vv2_812_l1}, +/*h(16843)=813 */ {16843, xed3_phash_find_mapevex_map1_opcode0x78_vv2_813_l1}, +/*h(5520)=814 */ {5520, xed3_phash_find_mapevex_map1_opcode0x78_vv2_814_l1}, +/*h(9701)=815 */ {9701, xed3_phash_find_mapevex_map1_opcode0x78_vv2_815_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26048)=817 */ {26048, xed3_phash_find_mapevex_map1_opcode0x78_vv2_817_l1}, +/*h(25061)=818 */ {25061, xed3_phash_find_mapevex_map1_opcode0x78_vv2_818_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12751)=820 */ {12751, xed3_phash_find_mapevex_map1_opcode0x78_vv2_820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30085)=822 */ {30085, xed3_phash_find_mapevex_map1_opcode0x78_vv2_822_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21956)=824 */ {21956, xed3_phash_find_mapevex_map1_opcode0x78_vv2_824_l1}, +/*h(16788)=825 */ {16788, xed3_phash_find_mapevex_map1_opcode0x78_vv2_825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9646)=827 */ {9646, xed3_phash_find_mapevex_map1_opcode0x78_vv2_827_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25993)=829 */ {25993, xed3_phash_find_mapevex_map1_opcode0x78_vv2_829_l1}, +/*h(25006)=830 */ {25006, xed3_phash_find_mapevex_map1_opcode0x78_vv2_830_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17864)=832 */ {17864, xed3_phash_find_mapevex_map1_opcode0x78_vv2_832_l1}, +/*h(10722)=833 */ {10722, xed3_phash_find_mapevex_map1_opcode0x78_vv2_833_l1}, +/*h(5554)=834 */ {5554, xed3_phash_find_mapevex_map1_opcode0x78_vv2_834_l1}, +/*h(4567)=835 */ {4567, xed3_phash_find_mapevex_map1_opcode0x78_vv2_835_l1}, +/*h(21901)=836 */ {21901, xed3_phash_find_mapevex_map1_opcode0x78_vv2_836_l1}, +/*h(20914)=837 */ {20914, xed3_phash_find_mapevex_map1_opcode0x78_vv2_837_l1}, +/*h(15746)=838 */ {15746, xed3_phash_find_mapevex_map1_opcode0x78_vv2_838_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30119)=841 */ {30119, xed3_phash_find_mapevex_map1_opcode0x78_vv2_841_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17809)=844 */ {17809, xed3_phash_find_mapevex_map1_opcode0x78_vv2_844_l1}, +/*h(11654)=845 */ {11654, xed3_phash_find_mapevex_map1_opcode0x78_vv2_845_l1}, +/*h(9680)=846 */ {9680, xed3_phash_find_mapevex_map1_opcode0x78_vv2_846_l1}, +/*h(4512)=847 */ {4512, xed3_phash_find_mapevex_map1_opcode0x78_vv2_847_l1}, +/*h(2538)=848 */ {2538, xed3_phash_find_mapevex_map1_opcode0x78_vv2_848_l1}, +/*h(26027)=849 */ {26027, xed3_phash_find_mapevex_map1_opcode0x78_vv2_849_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13717)=851 */ {13717, xed3_phash_find_mapevex_map1_opcode0x78_vv2_851_l1}, +/*h(7562)=852 */ {7562, xed3_phash_find_mapevex_map1_opcode0x78_vv2_852_l1}, +/*h(6575)=853 */ {6575, xed3_phash_find_mapevex_map1_opcode0x78_vv2_853_l1}, +/*h(5588)=854 */ {5588, xed3_phash_find_mapevex_map1_opcode0x78_vv2_854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21935)=856 */ {21935, xed3_phash_find_mapevex_map1_opcode0x78_vv2_856_l1}, +/*h(20948)=857 */ {20948, xed3_phash_find_mapevex_map1_opcode0x78_vv2_857_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3470)=859 */ {3470, xed3_phash_find_mapevex_map1_opcode0x78_vv2_859_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17843)=863 */ {17843, xed3_phash_find_mapevex_map1_opcode0x78_vv2_863_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9714)=866 */ {9714, xed3_phash_find_mapevex_map1_opcode0x78_vv2_866_l1}, +/*h(3559)=867 */ {3559, xed3_phash_find_mapevex_map1_opcode0x78_vv2_867_l1}, +/*h(26061)=868 */ {26061, xed3_phash_find_mapevex_map1_opcode0x78_vv2_868_l1}, +/*h(25074)=869 */ {25074, xed3_phash_find_mapevex_map1_opcode0x78_vv2_869_l1}, +/*h(14738)=870 */ {14738, xed3_phash_find_mapevex_map1_opcode0x78_vv2_870_l1}, +/*h(13751)=871 */ {13751, xed3_phash_find_mapevex_map1_opcode0x78_vv2_871_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1441)=873 */ {1441, xed3_phash_find_mapevex_map1_opcode0x78_vv2_873_l1}, +/*h(29111)=874 */ {29111, xed3_phash_find_mapevex_map1_opcode0x78_vv2_874_l1}, +/*h(21969)=875 */ {21969, xed3_phash_find_mapevex_map1_opcode0x78_vv2_875_l1}, +/*h(16801)=876 */ {16801, xed3_phash_find_mapevex_map1_opcode0x78_vv2_876_l1}, +/*h(15814)=877 */ {15814, xed3_phash_find_mapevex_map1_opcode0x78_vv2_877_l1}, +/*h(4491)=878 */ {4491, xed3_phash_find_mapevex_map1_opcode0x78_vv2_878_l1}, +/*h(8672)=879 */ {8672, xed3_phash_find_mapevex_map1_opcode0x78_vv2_879_l1}, +/*h(26006)=880 */ {26006, xed3_phash_find_mapevex_map1_opcode0x78_vv2_880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17877)=883 */ {17877, xed3_phash_find_mapevex_map1_opcode0x78_vv2_883_l1}, +/*h(11722)=884 */ {11722, xed3_phash_find_mapevex_map1_opcode0x78_vv2_884_l1}, +/*h(10735)=885 */ {10735, xed3_phash_find_mapevex_map1_opcode0x78_vv2_885_l1}, +/*h(399)=886 */ {399, xed3_phash_find_mapevex_map1_opcode0x78_vv2_886_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26095)=888 */ {26095, xed3_phash_find_mapevex_map1_opcode0x78_vv2_888_l1}, +/*h(15759)=889 */ {15759, xed3_phash_find_mapevex_map1_opcode0x78_vv2_889_l1}, +/*h(9604)=890 */ {9604, xed3_phash_find_mapevex_map1_opcode0x78_vv2_890_l1}, +/*h(7630)=891 */ {7630, xed3_phash_find_mapevex_map1_opcode0x78_vv2_891_l1}, +/*h(1475)=892 */ {1475, xed3_phash_find_mapevex_map1_opcode0x78_vv2_892_l1}, +/*h(24964)=893 */ {24964, xed3_phash_find_mapevex_map1_opcode0x78_vv2_893_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22003)=895 */ {22003, xed3_phash_find_mapevex_map1_opcode0x78_vv2_895_l1}, +/*h(16835)=896 */ {16835, xed3_phash_find_mapevex_map1_opcode0x78_vv2_896_l1}, +/*h(5512)=897 */ {5512, xed3_phash_find_mapevex_map1_opcode0x78_vv2_897_l1}, +/*h(4525)=898 */ {4525, xed3_phash_find_mapevex_map1_opcode0x78_vv2_898_l1}, +/*h(3538)=899 */ {3538, xed3_phash_find_mapevex_map1_opcode0x78_vv2_899_l1}, +/*h(20872)=900 */ {20872, xed3_phash_find_mapevex_map1_opcode0x78_vv2_900_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17911)=902 */ {17911, xed3_phash_find_mapevex_map1_opcode0x78_vv2_902_l1}, +/*h(7575)=903 */ {7575, xed3_phash_find_mapevex_map1_opcode0x78_vv2_903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1420)=905 */ {1420, xed3_phash_find_mapevex_map1_opcode0x78_vv2_905_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16780)=908 */ {16780, xed3_phash_find_mapevex_map1_opcode0x78_vv2_908_l1}, +/*h(14806)=909 */ {14806, xed3_phash_find_mapevex_map1_opcode0x78_vv2_909_l1}, +/*h(9638)=910 */ {9638, xed3_phash_find_mapevex_map1_opcode0x78_vv2_910_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25985)=912 */ {25985, xed3_phash_find_mapevex_map1_opcode0x78_vv2_912_l1}, +/*h(24998)=913 */ {24998, xed3_phash_find_mapevex_map1_opcode0x78_vv2_913_l1}, +/*h(17856)=914 */ {17856, xed3_phash_find_mapevex_map1_opcode0x78_vv2_914_l1}, +/*h(16869)=915 */ {16869, xed3_phash_find_mapevex_map1_opcode0x78_vv2_915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5546)=917 */ {5546, xed3_phash_find_mapevex_map1_opcode0x78_vv2_917_l1}, +/*h(4559)=918 */ {4559, xed3_phash_find_mapevex_map1_opcode0x78_vv2_918_l1}, +/*h(21893)=919 */ {21893, xed3_phash_find_mapevex_map1_opcode0x78_vv2_919_l1}, +/*h(20906)=920 */ {20906, xed3_phash_find_mapevex_map1_opcode0x78_vv2_920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8596)=922 */ {8596, xed3_phash_find_mapevex_map1_opcode0x78_vv2_922_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1454)=924 */ {1454, xed3_phash_find_mapevex_map1_opcode0x78_vv2_924_l1}, +/*h(467)=925 */ {467, xed3_phash_find_mapevex_map1_opcode0x78_vv2_925_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17801)=927 */ {17801, xed3_phash_find_mapevex_map1_opcode0x78_vv2_927_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9672)=929 */ {9672, xed3_phash_find_mapevex_map1_opcode0x78_vv2_929_l1}, +/*h(8685)=930 */ {8685, xed3_phash_find_mapevex_map1_opcode0x78_vv2_930_l1}, +/*h(2530)=931 */ {2530, xed3_phash_find_mapevex_map1_opcode0x78_vv2_931_l1}, +/*h(26019)=932 */ {26019, xed3_phash_find_mapevex_map1_opcode0x78_vv2_932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13709)=934 */ {13709, xed3_phash_find_mapevex_map1_opcode0x78_vv2_934_l1}, +/*h(11735)=935 */ {11735, xed3_phash_find_mapevex_map1_opcode0x78_vv2_935_l1}, +/*h(5580)=936 */ {5580, xed3_phash_find_mapevex_map1_opcode0x78_vv2_936_l1}, +/*h(29069)=937 */ {29069, xed3_phash_find_mapevex_map1_opcode0x78_vv2_937_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21927)=939 */ {21927, xed3_phash_find_mapevex_map1_opcode0x78_vv2_939_l1}, +/*h(20940)=940 */ {20940, xed3_phash_find_mapevex_map1_opcode0x78_vv2_940_l1}, +/*h(9617)=941 */ {9617, xed3_phash_find_mapevex_map1_opcode0x78_vv2_941_l1}, +/*h(3462)=942 */ {3462, xed3_phash_find_mapevex_map1_opcode0x78_vv2_942_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1488)=944 */ {1488, xed3_phash_find_mapevex_map1_opcode0x78_vv2_944_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17835)=946 */ {17835, xed3_phash_find_mapevex_map1_opcode0x78_vv2_946_l1}, +/*h(16848)=947 */ {16848, xed3_phash_find_mapevex_map1_opcode0x78_vv2_947_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5525)=949 */ {5525, xed3_phash_find_mapevex_map1_opcode0x78_vv2_949_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26053)=951 */ {26053, xed3_phash_find_mapevex_map1_opcode0x78_vv2_951_l1}, +/*h(20885)=952 */ {20885, xed3_phash_find_mapevex_map1_opcode0x78_vv2_952_l1}, +/*h(13743)=953 */ {13743, xed3_phash_find_mapevex_map1_opcode0x78_vv2_953_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5614)=956 */ {5614, xed3_phash_find_mapevex_map1_opcode0x78_vv2_956_l1}, +/*h(29103)=957 */ {29103, xed3_phash_find_mapevex_map1_opcode0x78_vv2_957_l1}, +/*h(21961)=958 */ {21961, xed3_phash_find_mapevex_map1_opcode0x78_vv2_958_l1}, +/*h(20974)=959 */ {20974, xed3_phash_find_mapevex_map1_opcode0x78_vv2_959_l1}, +/*h(10638)=960 */ {10638, xed3_phash_find_mapevex_map1_opcode0x78_vv2_960_l1}, +/*h(9651)=961 */ {9651, xed3_phash_find_mapevex_map1_opcode0x78_vv2_961_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25998)=963 */ {25998, xed3_phash_find_mapevex_map1_opcode0x78_vv2_963_l1}, +/*h(25011)=964 */ {25011, xed3_phash_find_mapevex_map1_opcode0x78_vv2_964_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17869)=966 */ {17869, xed3_phash_find_mapevex_map1_opcode0x78_vv2_966_l1}, +/*h(11714)=967 */ {11714, xed3_phash_find_mapevex_map1_opcode0x78_vv2_967_l1}, +/*h(5559)=968 */ {5559, xed3_phash_find_mapevex_map1_opcode0x78_vv2_968_l1}, +/*h(391)=969 */ {391, xed3_phash_find_mapevex_map1_opcode0x78_vv2_969_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21906)=971 */ {21906, xed3_phash_find_mapevex_map1_opcode0x78_vv2_971_l1}, +/*h(15751)=972 */ {15751, xed3_phash_find_mapevex_map1_opcode0x78_vv2_972_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7622)=974 */ {7622, xed3_phash_find_mapevex_map1_opcode0x78_vv2_974_l1}, +/*h(2454)=975 */ {2454, xed3_phash_find_mapevex_map1_opcode0x78_vv2_975_l1}, +/*h(480)=976 */ {480, xed3_phash_find_mapevex_map1_opcode0x78_vv2_976_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17814)=978 */ {17814, xed3_phash_find_mapevex_map1_opcode0x78_vv2_978_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5504)=980 */ {5504, xed3_phash_find_mapevex_map1_opcode0x78_vv2_980_l1}, +/*h(4517)=981 */ {4517, xed3_phash_find_mapevex_map1_opcode0x78_vv2_981_l1}, +/*h(3530)=982 */ {3530, xed3_phash_find_mapevex_map1_opcode0x78_vv2_982_l1}, +/*h(26032)=983 */ {26032, xed3_phash_find_mapevex_map1_opcode0x78_vv2_983_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17903)=985 */ {17903, xed3_phash_find_mapevex_map1_opcode0x78_vv2_985_l1}, +/*h(7567)=986 */ {7567, xed3_phash_find_mapevex_map1_opcode0x78_vv2_986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1412)=988 */ {1412, xed3_phash_find_mapevex_map1_opcode0x78_vv2_988_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21940)=990 */ {21940, xed3_phash_find_mapevex_map1_opcode0x78_vv2_990_l1}, +/*h(16772)=991 */ {16772, xed3_phash_find_mapevex_map1_opcode0x78_vv2_991_l1}, +/*h(14798)=992 */ {14798, xed3_phash_find_mapevex_map1_opcode0x78_vv2_992_l1}, +/*h(8643)=993 */ {8643, xed3_phash_find_mapevex_map1_opcode0x78_vv2_993_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10706)=999 */ {10706, xed3_phash_find_mapevex_map1_opcode0x78_vv2_999_l1}, +/*h(5538)=1000 */ {5538, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1000_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26066)=1002 */ {26066, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1002_l1}, +/*h(20898)=1003 */ {20898, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1003_l1}, +/*h(14743)=1004 */ {14743, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1004_l1}, +/*h(8588)=1005 */ {8588, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1005_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30103)=1007 */ {30103, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1007_l1}, +/*h(459)=1008 */ {459, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1008_l1}, +/*h(17793)=1009 */ {17793, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1009_l1}, +/*h(21974)=1010 */ {21974, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1010_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9664)=1012 */ {9664, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1012_l1}, +/*h(4496)=1013 */ {4496, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1013_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25024)=1015 */ {25024, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1015_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13701)=1017 */ {13701, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1017_l1}, +/*h(11727)=1018 */ {11727, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1018_l1}, +/*h(5572)=1019 */ {5572, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1019_l1}, +/*h(404)=1020 */ {404, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1020_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26100)=1022 */ {26100, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1022_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9609)=1024 */ {9609, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1024_l1}, +/*h(8622)=1025 */ {8622, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1480)=1027 */ {1480, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17827)=1029 */ {17827, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1029_l1}, +/*h(16840)=1030 */ {16840, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1030_l1}, +/*h(5517)=1031 */ {5517, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1031_l1}, +/*h(9698)=1032 */ {9698, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1032_l1}, +/*h(3543)=1033 */ {3543, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1033_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20877)=1035 */ {20877, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1035_l1}, +/*h(13735)=1036 */ {13735, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1036_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1425)=1039 */ {1425, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1039_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21953)=1041 */ {21953, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1041_l1}, +/*h(16785)=1042 */ {16785, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1042_l1}, +/*h(10630)=1043 */ {10630, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1043_l1}, +/*h(9643)=1044 */ {9643, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1044_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25990)=1046 */ {25990, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1046_l1}, +/*h(25003)=1047 */ {25003, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17861)=1049 */ {17861, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1049_l1}, +/*h(6538)=1050 */ {6538, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1050_l1}, +/*h(5551)=1051 */ {5551, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1051_l1}, +/*h(4564)=1052 */ {4564, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1052_l1}, +/*h(21898)=1053 */ {21898, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1053_l1}, +/*h(20911)=1054 */ {20911, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1054_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1459)=1058 */ {1459, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1058_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17806)=1061 */ {17806, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9677)=1063 */ {9677, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1063_l1}, +/*h(3522)=1064 */ {3522, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1064_l1}, +/*h(2535)=1065 */ {2535, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1065_l1}, +/*h(26024)=1066 */ {26024, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1066_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17895)=1068 */ {17895, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1068_l1}, +/*h(7559)=1069 */ {7559, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1069_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5585)=1071 */ {5585, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1071_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21932)=1073 */ {21932, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1073_l1}, +/*h(20945)=1074 */ {20945, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1074_l1}, +/*h(9622)=1075 */ {9622, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1075_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1493)=1078 */ {1493, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1078_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17840)=1080 */ {17840, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1080_l1}, +/*h(16853)=1081 */ {16853, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1081_l1}, +/*h(10698)=1082 */ {10698, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1082_l1}, +/*h(9711)=1083 */ {9711, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1083_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26058)=1085 */ {26058, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1085_l1}, +/*h(25071)=1086 */ {25071, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1086_l1}, +/*h(14735)=1087 */ {14735, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1087_l1}, +/*h(8580)=1088 */ {8580, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1088_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30095)=1090 */ {30095, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1090_l1}, +/*h(451)=1091 */ {451, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1091_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21966)=1093 */ {21966, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4488)=1095 */ {4488, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1095_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26003)=1097 */ {26003, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1097_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17874)=1100 */ {17874, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1100_l1}, +/*h(11719)=1101 */ {11719, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1101_l1}, +/*h(6551)=1102 */ {6551, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1102_l1}, +/*h(396)=1103 */ {396, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21911)=1105 */ {21911, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9601)=1107 */ {9601, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1107_l1}, +/*h(8614)=1108 */ {8614, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1472)=1110 */ {1472, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22000)=1112 */ {22000, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1112_l1}, +/*h(16832)=1113 */ {16832, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1113_l1}, +/*h(5509)=1114 */ {5509, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1114_l1}, +/*h(4522)=1115 */ {4522, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1115_l1}, +/*h(3535)=1116 */ {3535, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1116_l1}, +/*h(26037)=1117 */ {26037, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17908)=1119 */ {17908, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1417)=1122 */ {1417, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15790)=1125 */ {15790, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9635)=1127 */ {9635, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1506)=1129 */ {1506, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1129_l1}, +/*h(24995)=1130 */ {24995, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12685)=1132 */ {12685, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1132_l1}, +/*h(10711)=1133 */ {10711, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1133_l1}, +/*h(5543)=1134 */ {5543, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1134_l1}, +/*h(4556)=1135 */ {4556, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1135_l1}, +/*h(21890)=1136 */ {21890, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1136_l1}, +/*h(26071)=1137 */ {26071, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8593)=1139 */ {8593, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1451)=1141 */ {1451, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1141_l1}, +/*h(464)=1142 */ {464, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17798)=1144 */ {17798, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1144_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9669)=1146 */ {9669, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1146_l1}, +/*h(4501)=1147 */ {4501, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26016)=1149 */ {26016, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12719)=1152 */ {12719, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5577)=1154 */ {5577, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21924)=1156 */ {21924, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1156_l1}, +/*h(20937)=1157 */ {20937, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1157_l1}, +/*h(9614)=1158 */ {9614, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1158_l1}, +/*h(8627)=1159 */ {8627, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1485)=1161 */ {1485, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1161_l1}, +/*h(498)=1162 */ {498, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1162_l1}, +/*h(17832)=1163 */ {17832, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1163_l1}, +/*h(16845)=1164 */ {16845, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1164_l1}, +/*h(10690)=1165 */ {10690, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1165_l1}, +/*h(5522)=1166 */ {5522, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26050)=1168 */ {26050, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1168_l1}, +/*h(20882)=1169 */ {20882, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1169_l1}, +/*h(14727)=1170 */ {14727, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6598)=1172 */ {6598, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1172_l1}, +/*h(30087)=1173 */ {30087, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21958)=1175 */ {21958, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1175_l1}, +/*h(16790)=1176 */ {16790, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9648)=1178 */ {9648, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1178_l1}, +/*h(8661)=1179 */ {8661, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1179_l1}, +/*h(25995)=1180 */ {25995, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1180_l1}, +/*h(25008)=1181 */ {25008, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1181_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17866)=1183 */ {17866, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5556)=1185 */ {5556, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1185_l1}, +/*h(388)=1186 */ {388, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1186_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21903)=1188 */ {21903, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17811)=1195 */ {17811, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9682)=1197 */ {9682, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1197_l1}, +/*h(4514)=1198 */ {4514, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1198_l1}, +/*h(3527)=1199 */ {3527, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1199_l1}, +/*h(26029)=1200 */ {26029, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1200_l1}, +/*h(25042)=1201 */ {25042, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1201_l1}, +/*h(13719)=1202 */ {13719, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1202_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1409)=1205 */ {1409, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21937)=1207 */ {21937, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1207_l1}, +/*h(15782)=1208 */ {15782, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8640)=1210 */ {8640, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17845)=1214 */ {17845, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1214_l1}, +/*h(12677)=1215 */ {12677, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1215_l1}, +/*h(11690)=1216 */ {11690, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1216_l1}, +/*h(9716)=1217 */ {9716, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1217_l1}, +/*h(4548)=1218 */ {4548, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1218_l1}, +/*h(26063)=1219 */ {26063, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1219_l1}, +/*h(25076)=1220 */ {25076, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8585)=1222 */ {8585, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1222_l1}, +/*h(7598)=1223 */ {7598, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1223_l1}, +/*h(1443)=1224 */ {1443, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1224_l1}, +/*h(456)=1225 */ {456, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21971)=1227 */ {21971, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4493)=1230 */ {4493, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1230_l1}, +/*h(2519)=1231 */ {2519, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1231_l1}, +/*h(30189)=1232 */ {30189, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17879)=1234 */ {17879, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1234_l1}, +/*h(12711)=1235 */ {12711, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1235_l1}, +/*h(5569)=1236 */ {5569, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1236_l1}, +/*h(401)=1237 */ {401, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26097)=1239 */ {26097, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1239_l1}, +/*h(20929)=1240 */ {20929, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1240_l1}, +/*h(9606)=1241 */ {9606, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1241_l1}, +/*h(8619)=1242 */ {8619, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1242_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1477)=1244 */ {1477, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17824)=1246 */ {17824, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1246_l1}, +/*h(16837)=1247 */ {16837, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1247_l1}, +/*h(15850)=1248 */ {15850, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1248_l1}, +/*h(5514)=1249 */ {5514, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20874)=1252 */ {20874, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11758)=1255 */ {11758, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1255_l1}, +/*h(1422)=1256 */ {1422, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1256_l1}, +/*h(435)=1257 */ {435, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16782)=1259 */ {16782, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9640)=1261 */ {9640, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25987)=1263 */ {25987, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1263_l1}, +/*h(25000)=1264 */ {25000, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17858)=1266 */ {17858, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1266_l1}, +/*h(6535)=1267 */ {6535, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1267_l1}, +/*h(5548)=1268 */ {5548, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1268_l1}, +/*h(4561)=1269 */ {4561, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21895)=1271 */ {21895, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8598)=1274 */ {8598, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1274_l1}, +/*h(1456)=1275 */ {1456, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1275_l1}, +/*h(469)=1276 */ {469, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17803)=1278 */ {17803, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1278_l1}, +/*h(16816)=1279 */ {16816, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1279_l1}, +/*h(9674)=1280 */ {9674, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1280_l1}, +/*h(8687)=1281 */ {8687, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26021)=1283 */ {26021, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13711)=1285 */ {13711, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5582)=1288 */ {5582, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21929)=1290 */ {21929, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1290_l1}, +/*h(20942)=1291 */ {20942, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1291_l1}, +/*h(9619)=1292 */ {9619, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1490)=1295 */ {1490, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1295_l1}, +/*h(24979)=1296 */ {24979, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1296_l1}, +/*h(17837)=1297 */ {17837, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1297_l1}, +/*h(16850)=1298 */ {16850, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1298_l1}, +/*h(11682)=1299 */ {11682, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1299_l1}, +/*h(5527)=1300 */ {5527, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26055)=1302 */ {26055, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1302_l1}, +/*h(20887)=1303 */ {20887, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8577)=1305 */ {8577, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1305_l1}, +/*h(7590)=1306 */ {7590, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1306_l1}, +/*h(5616)=1307 */ {5616, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1307_l1}, +/*h(448)=1308 */ {448, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1308_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21963)=1310 */ {21963, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9653)=1312 */ {9653, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1312_l1}, +/*h(3498)=1313 */ {3498, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1313_l1}, +/*h(26000)=1314 */ {26000, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1314_l1}, +/*h(30181)=1315 */ {30181, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17871)=1317 */ {17871, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1317_l1}, +/*h(16884)=1318 */ {16884, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(393)=1320 */ {393, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21908)=1322 */ {21908, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1322_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14766)=1324 */ {14766, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1324_l1}, +/*h(8611)=1325 */ {8611, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(482)=1327 */ {482, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21997)=1329 */ {21997, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1329_l1}, +/*h(15842)=1330 */ {15842, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1330_l1}, +/*h(5506)=1331 */ {5506, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1331_l1}, +/*h(9687)=1332 */ {9687, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26034)=1334 */ {26034, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1334_l1}, +/*h(20866)=1335 */ {20866, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17905)=1337 */ {17905, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1337_l1}, +/*h(11750)=1338 */ {11750, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1338_l1}, +/*h(1414)=1339 */ {1414, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1339_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21942)=1341 */ {21942, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1341_l1}, +/*h(16774)=1342 */ {16774, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9632)=1344 */ {9632, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1344_l1}, +/*h(7658)=1345 */ {7658, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24992)=1347 */ {24992, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11695)=1350 */ {11695, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1350_l1}, +/*h(5540)=1351 */ {5540, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1351_l1}, +/*h(3566)=1352 */ {3566, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1352_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26068)=1354 */ {26068, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8590)=1357 */ {8590, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1357_l1}, +/*h(1448)=1358 */ {1448, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1358_l1}, +/*h(461)=1359 */ {461, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17795)=1361 */ {17795, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9666)=1363 */ {9666, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1363_l1}, +/*h(4498)=1364 */ {4498, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25026)=1366 */ {25026, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13703)=1368 */ {13703, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1368_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5574)=1371 */ {5574, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1371_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21921)=1373 */ {21921, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1373_l1}, +/*h(15766)=1374 */ {15766, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1374_l1}, +/*h(9611)=1375 */ {9611, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1375_l1}, +/*h(8624)=1376 */ {8624, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1482)=1378 */ {1482, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1378_l1}, +/*h(495)=1379 */ {495, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1379_l1}, +/*h(17829)=1380 */ {17829, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1380_l1}, +/*h(16842)=1381 */ {16842, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1381_l1}, +/*h(15855)=1382 */ {15855, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1382_l1}, +/*h(5519)=1383 */ {5519, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20879)=1386 */ {20879, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1386_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1427)=1390 */ {1427, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21955)=1393 */ {21955, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1393_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9645)=1395 */ {9645, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1395_l1}, +/*h(3490)=1396 */ {3490, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1396_l1}, +/*h(25992)=1397 */ {25992, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1397_l1}, +/*h(1516)=1398 */ {1516, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17863)=1400 */ {17863, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1400_l1}, +/*h(16876)=1401 */ {16876, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1401_l1}, +/*h(5553)=1402 */ {5553, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1402_l1}, +/*h(385)=1403 */ {385, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21900)=1405 */ {21900, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14758)=1407 */ {14758, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1407_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1461)=1410 */ {1461, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17808)=1412 */ {17808, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1412_l1}, +/*h(16821)=1413 */ {16821, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1413_l1}, +/*h(10666)=1414 */ {10666, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1414_l1}, +/*h(9679)=1415 */ {9679, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26026)=1417 */ {26026, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1417_l1}, +/*h(25039)=1418 */ {25039, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1418_l1}, +/*h(17897)=1419 */ {17897, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6574)=1421 */ {6574, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1421_l1}, +/*h(5587)=1422 */ {5587, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1422_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21934)=1424 */ {21934, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1424_l1}, +/*h(20947)=1425 */ {20947, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13805)=1427 */ {13805, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1427_l1}, +/*h(7650)=1428 */ {7650, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1428_l1}, +/*h(1495)=1429 */ {1495, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1429_l1}, +/*h(29165)=1430 */ {29165, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17842)=1432 */ {17842, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1432_l1}, +/*h(11687)=1433 */ {11687, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1433_l1}, +/*h(9713)=1434 */ {9713, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1434_l1}, +/*h(3558)=1435 */ {3558, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26060)=1437 */ {26060, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8582)=1439 */ {8582, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1440)=1441 */ {1440, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1441_l1}, +/*h(453)=1442 */ {453, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21968)=1444 */ {21968, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1444_l1}, +/*h(20981)=1445 */ {20981, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1445_l1}, +/*h(14826)=1446 */ {14826, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1446_l1}, +/*h(3503)=1447 */ {3503, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26005)=1449 */ {26005, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1449_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17876)=1451 */ {17876, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1451_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10734)=1453 */ {10734, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1453_l1}, +/*h(398)=1454 */ {398, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26094)=1456 */ {26094, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1456_l1}, +/*h(15758)=1457 */ {15758, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1457_l1}, +/*h(9603)=1458 */ {9603, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1458_l1}, +/*h(8616)=1459 */ {8616, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1474)=1461 */ {1474, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1461_l1}, +/*h(487)=1462 */ {487, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1462_l1}, +/*h(22002)=1463 */ {22002, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1463_l1}, +/*h(11666)=1464 */ {11666, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1464_l1}, +/*h(15847)=1465 */ {15847, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1465_l1}, +/*h(5511)=1466 */ {5511, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1466_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26039)=1468 */ {26039, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1468_l1}, +/*h(20871)=1469 */ {20871, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1469_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17910)=1471 */ {17910, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1471_l1}, +/*h(7574)=1472 */ {7574, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1472_l1}, +/*h(1419)=1473 */ {1419, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1473_l1}, +/*h(432)=1474 */ {432, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16779)=1476 */ {16779, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9637)=1478 */ {9637, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1478_l1}, +/*h(7663)=1479 */ {7663, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1479_l1}, +/*h(25984)=1480 */ {25984, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1480_l1}, +/*h(24997)=1481 */ {24997, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12687)=1483 */ {12687, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1483_l1}, +/*h(16868)=1484 */ {16868, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1484_l1}, +/*h(5545)=1485 */ {5545, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1485_l1}, +/*h(4558)=1486 */ {4558, xed3_phash_find_mapevex_map1_opcode0x78_vv2_1486_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 1488ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8644)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8644; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_230_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25028)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_93_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8676)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8676, 4201}, +/*h(4495)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4495, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25060)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25060, 4201}, +/*h(20879)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20879, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8652)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8652; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25036)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_10_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8684)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8684, 4201}, +/*h(4503)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4503, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1303_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25068)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25068, 4201}, +/*h(20887)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20887, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8660)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8660; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25044)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25044; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8692)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8692, 4201}, +/*h(9679)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9679, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25076)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25076; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_776_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8646)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25030)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_444_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8678)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8678, 4201}, +/*h(4497)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4497, 4242}, +/*h(9665)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9665, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20881)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20881, 4242}, +/*h(25062)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25062, 4201}, +/*h(26049)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26049, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_693_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8654)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25038)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8686)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8686, 4201}, +/*h(9673)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9673, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25070)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25070, 4201}, +/*h(26057)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26057, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4481)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4481, 4242}, +/*h(8662)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8662, 4201}, +/*h(9649)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9649, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25046)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25046, 4201}, +/*h(20865)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20865, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9681)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9681, 6083}, +/*h(4513)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4513, 4242}, +/*h(8694)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {8694, 4201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_83_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25078)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {25078, 4201}, +/*h(20897)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20897, 4242}, +/*h(26065)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26065, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(453)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 453; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16837)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_649_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5536)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5536, 6094}, +/*h(9717)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9717, 6082}, +/*h(4549)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4549, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20933)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20933, 4202}, +/*h(26101)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {26101, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8645)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8645, 4202}, +/*h(13813)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13813, 6082}, +/*h(9632)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9632, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1149_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26016)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26016, 6097}, +/*h(30197)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30197, 6082}, +/*h(25029)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25029, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_552_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11754)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11754, 4296}, +/*h(12741)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12741, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1455)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1455, 6096}, +/*h(468)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {468, 4204}, +/*h(29125)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29125, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(485)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {485, 4202}, +/*h(24961)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24961, 4238}, +/*h(1472)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1472, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16869)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(400)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {400, 4240}, +/*h(4581)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4581, 4202}, +/*h(5568)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5568, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20965)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20965, 4202}, +/*h(21952)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21952, 6080}, +/*h(16784)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16784, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4496)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4496, 4242}, +/*h(8677)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8677, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_818_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25061)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8592)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8592, 4238}, +/*h(12773)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12773, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29157)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29157, 4202}, +/*h(24976)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24976, 4238}, +/*h(500)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {500, 4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(461)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1164_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16845)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_566_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5544)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5544, 6094}, +/*h(4557)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4557, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_371_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20941)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9640)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9640, 6097}, +/*h(8653)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8653, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1066_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26024)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26024, 6097}, +/*h(25037)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25037, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12749)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29133)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29133; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1027_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1480)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1480, 6078}, +/*h(493)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {493, 4202}, +/*h(24969)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24969, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_832_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17864)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17864, 6078}, +/*h(16877)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16877, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4589)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21960)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21960, 6080}, +/*h(20973)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20973, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_930_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8685)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8685; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_735_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25069)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25069; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12781)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12781; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29165)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29165; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(469)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 469; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1081_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16853)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4565)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4565, 4202}, +/*h(5552)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5552, 6094}, +/*h(384)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {384, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21936)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21936, 6094}, +/*h(16768)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16768, 4240}, +/*h(20949)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20949, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1179_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8661)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8661; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_983_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25045)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25045, 4202}, +/*h(26032)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26032, 6097}, +/*h(20864)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20864, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8576)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8576, 4238}, +/*h(12757)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12757, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(484)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {484, 4204}, +/*h(29141)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29141, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_944_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(24977)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24977, 4238}, +/*h(501)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {501, 4202}, +/*h(1488)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1488, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_749_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17872)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17872, 6078}, +/*h(16885)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16885, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4597)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1445_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20981)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_847_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4512)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4512, 4242}, +/*h(8693)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8693, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20896)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20896, 4242}, +/*h(25077)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25077, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_54_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8608)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8608, 4238}, +/*h(12789)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12789, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1347_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24992)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24992, 4238}, +/*h(29173)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29173, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_305_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(455)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {455, 4202}, +/*h(5623)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5623, 6082}, +/*h(1442)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1442, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16839)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16839, 4202}, +/*h(22007)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {22007, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4551)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4551, 4202}, +/*h(5538)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5538, 6094}, +/*h(9719)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9719, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_805_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26103)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {26103, 6082}, +/*h(21922)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21922, 6094}, +/*h(20935)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20935, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3479)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {3479, 4295}, +/*h(8647)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8647, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25031)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_903_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7575)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7575, 4295}, +/*h(12743)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12743, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(470)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {470, 4204}, +/*h(29127)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29127, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(487)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17858)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17858, 6078}, +/*h(16871)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16871, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(402)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {402, 4240}, +/*h(4583)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4583, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20967)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1364_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4498)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4498, 4242}, +/*h(8679)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8679, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1169_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20882)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20882, 4242}, +/*h(25063)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25063, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8594)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8594, 4238}, +/*h(12775)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12775, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_376_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(24978)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24978, 4238}, +/*h(502)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {502, 4204}, +/*h(29159)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29159, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1450)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1450, 6092}, +/*h(463)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {463, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17834)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17834, 6092}, +/*h(16847)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16847, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_918_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4559)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_722_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21930)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21930, 6094}, +/*h(20943)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20943, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8655)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25039)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_820_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12751)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_625_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29135)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1379_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(495)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17866)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17866, 6078}, +/*h(16879)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16879, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4591)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20975)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8687)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25071)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12783)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_293_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29167)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29167; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_139_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1458)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1458, 6092}, +/*h(471)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {471, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1432_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17842)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17842, 6092}, +/*h(16855)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16855, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4567)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_639_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16770)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16770, 4240}, +/*h(20951)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20951, 4202}, +/*h(21938)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21938, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4482)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4482, 4242}, +/*h(3495)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3495, 4294}, +/*h(8663)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8663, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1335_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20866)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20866, 4242}, +/*h(25047)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25047, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_737_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8578)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8578, 4238}, +/*h(12759)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12759, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(486)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {486, 4204}, +/*h(29143)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29143, 4202}, +/*h(24962)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24962, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1296_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(503)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {503, 4202}, +/*h(24979)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24979, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1101_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16887)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {16887, 4202}, +/*h(11719)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {11719, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(418)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {418, 4240}, +/*h(4599)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4599, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(16802)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16802, 4240}, +/*h(15815)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {15815, 4294}, +/*h(20983)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {20983, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1198_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4514)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4514, 4242}, +/*h(8695)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8695, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1003_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20898)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20898, 4242}, +/*h(25079)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {25079, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8610)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8610, 4238}, +/*h(12791)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {12791, 4202} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29175)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {29175, 4202}, +/*h(24994)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24994, 4238}, +/*h(1505)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1505, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8640)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8640; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1015_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25024)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8672)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_683_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25056)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25056, 4203}, +/*h(20875)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20875, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8648)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8648, 4203}, +/*h(9635)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9635, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_932_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25032)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25032, 4203}, +/*h(26019)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26019, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_796_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8680)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_600_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26051)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26051, 6083}, +/*h(20883)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20883, 4242}, +/*h(25064)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25064, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1044_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8656)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8656, 4203}, +/*h(9643)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9643, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_849_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25040)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25040, 4203}, +/*h(26027)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26027, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_713_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8688)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8688; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25072)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25072; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8642)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25026)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1230_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8674)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8674, 4203}, +/*h(4493)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4493, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1035_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25058)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25058, 4203}, +/*h(20877)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20877, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1479_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8650)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8650, 4203}, +/*h(7663)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {7663, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25034)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25034, 4203}, +/*h(26021)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {26021, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8682)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8682, 4203}, +/*h(4501)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4501, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25066)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25066, 4203}, +/*h(20885)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20885, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8658)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8658, 4203}, +/*h(3490)=1 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3490, 4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25042)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1064_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3522)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3522, 4296}, +/*h(8690)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8690, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_869_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25074)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25074; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_642_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8641)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25025)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4492)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4492, 4241}, +/*h(8673)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8673, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20876)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20876, 4241}, +/*h(25057)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25057, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8649)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8649; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25033)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4500)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4500, 4241}, +/*h(8681)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8681, 4203}, +/*h(9668)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9668, 6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20884)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20884, 4241}, +/*h(25065)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25065, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8657)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8657; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25041)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25041; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9676)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9676, 6081}, +/*h(8689)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8689, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26060)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26060, 6081}, +/*h(25073)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25073, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8643)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8643; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_798_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25027)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4494)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4494, 4241}, +/*h(8675)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8675, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20878)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20878, 4241}, +/*h(25059)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25059, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_910_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9638)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9638, 6095}, +/*h(8651)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8651, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_715_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25035)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_579_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8683)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20886)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20886, 4241}, +/*h(25067)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25067, 4203}, +/*h(26054)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26054, 6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_827_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9646)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9646, 6095}, +/*h(8659)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8659, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25043)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25043; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8691)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8691; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26062)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26062, 6081}, +/*h(25075)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {25075, 4203} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29109)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29109, 4237}, +/*h(5620)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5620, 6079}, +/*h(452)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {452, 4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16836)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16836, 4204}, +/*h(22004)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {22004, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16868)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_439_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(460)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {460, 4204}, +/*h(1447)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1447, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16844)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16844, 4204}, +/*h(17831)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17831, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(492)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {492, 4204}, +/*h(24968)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24968, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16876)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16852)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16852, 4204}, +/*h(17839)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17839, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16884)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16884; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_874_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(454)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {454, 4204}, +/*h(29111)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29111, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_678_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(17825)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17825, 6092}, +/*h(22006)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {22006, 6079}, +/*h(16838)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16838, 4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16870)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_791_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(462)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16846)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(494)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {494, 4204}, +/*h(24970)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24970, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16878)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16854)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16854, 4204}, +/*h(11686)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {11686, 4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11718)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {11718, 4292}, +/*h(16886)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {16886, 4204} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(448)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16832)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_976_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(480)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 480; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_781_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16864)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16864; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(456)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16840)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(488)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {488, 4205}, +/*h(24964)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24964, 4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_698_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16872)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(464)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 464; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_947_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16848)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16848; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_810_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(24972)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24972, 4236}, +/*h(496)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {496, 4205}, +/*h(1483)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1483, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_615_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16880)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16880; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_171_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(450)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {450, 4205}, +/*h(5618)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5618, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1464_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11666)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {11666, 4297}, +/*h(16834)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16834, 4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1327_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(482)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16866)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16866, 4205}, +/*h(12685)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12685, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_88_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(458)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1381_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16842)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1244_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(490)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {490, 4205}, +/*h(24966)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24966, 4236}, +/*h(1477)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1477, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1049_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(17861)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {17861, 6082}, +/*h(12693)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12693, 4237}, +/*h(16874)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16874, 4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(466)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {466, 4205}, +/*h(1453)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1453, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16850)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1162_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(498)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16882)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16882, 4205}, +/*h(17869)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {17869, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_739_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(30093)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30093, 6096}, +/*h(5617)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5617, 6080}, +/*h(449)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {449, 4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16833)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16833, 4205}, +/*h(22001)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {22001, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(481)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16865)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(457)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17828)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17828, 6091}, +/*h(16841)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16841, 4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(489)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {489, 4205}, +/*h(24965)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24965, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16873)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(465)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 465; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17836)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17836, 6091}, +/*h(16849)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {16849, 4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_242_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(497)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {497, 4205}, +/*h(24973)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24973, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16881)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16881; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1091_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(451)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 451; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_896_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16835)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(483)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 483; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_564_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16867)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1008_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(459)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 459; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_813_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16843)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(491)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {491, 4205}, +/*h(24967)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24967, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16875)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(467)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 467; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16851)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_593_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24975)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24975, 4237}, +/*h(499)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {499, 4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_398_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16883)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4205} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16883; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1218_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4548)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1022_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26100)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26100, 6081}, +/*h(20932)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20932, 4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4580)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4580, 4206}, +/*h(399)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {399, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20964)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20964, 4206}, +/*h(16783)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16783, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4556)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4556; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_940_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20940)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_803_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4588)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4588, 4206}, +/*h(407)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {407, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20972)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20972, 4206}, +/*h(16791)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16791, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1052_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4564)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4564; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20948)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20948; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_720_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4596)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_525_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20980)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_81_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4550)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20934)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20934, 4206}, +/*h(15766)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {15766, 4293} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4582)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4582, 4206}, +/*h(401)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {401, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1042_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20966)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20966, 4206}, +/*h(16785)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16785, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4558)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20942)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4590)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4590, 4206}, +/*h(5577)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5577, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20974)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4206} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4566)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4566, 4206}, +/*h(385)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {385, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1208_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20950)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20950, 4206}, +/*h(15782)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15782, 4292}, +/*h(16769)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16769, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1071_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4598)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {4598, 4206}, +/*h(5585)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5585, 6080}, +/*h(417)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {417, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_876_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20982)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {20982, 4206}, +/*h(16801)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16801, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4544)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4544; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20928)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4576)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4576, 4207}, +/*h(395)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {395, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1476_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20960)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20960, 4207}, +/*h(16779)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16779, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4552)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4552; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_237_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20936)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5571)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5571, 6080}, +/*h(403)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {403, 4240}, +/*h(4584)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4584, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1393_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21955)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21955, 6080}, +/*h(20968)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20968, 4207}, +/*h(16787)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16787, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4560)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4560; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20944)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_17_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4592)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4592, 4207}, +/*h(5579)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5579, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1310_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20976)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20976, 4207}, +/*h(21963)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21963, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_866_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9714)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9714, 6083}, +/*h(4546)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4546, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_671_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20930)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20930, 4207}, +/*h(26098)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26098, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4578)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20962)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20962, 4207}, +/*h(16781)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16781, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_783_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4554)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4554, 4207}, +/*h(5541)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5541, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_588_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20938)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20938, 4207}, +/*h(21925)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21925, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4586)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4586, 4207}, +/*h(405)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {405, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20970)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4562)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4562, 4207}, +/*h(5549)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5549, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20946)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20946, 4207}, +/*h(21933)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21933, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4594)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_174_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15810)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15810, 4296}, +/*h(20978)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20978, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1435_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3558)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3558, 4292}, +/*h(4545)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4545, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20929)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1103_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(396)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {396, 4239}, +/*h(4577)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4577, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_908_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16780)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16780, 4239}, +/*h(20961)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20961, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3566)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3566, 4292}, +/*h(4553)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4553, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20937)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1020_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(29061)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29061, 4237}, +/*h(4585)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4585, 4207}, +/*h(404)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {404, 4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_825_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16788)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16788, 4239}, +/*h(20969)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20969, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4561)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4561; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1074_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20945)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_937_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4593)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4593, 4207}, +/*h(29069)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29069, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_742_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20977)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20977; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_298_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4547)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4547; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20931)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(398)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {398, 4239}, +/*h(4579)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4579, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1259_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16782)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16782, 4239}, +/*h(20963)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20963, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4555)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4555; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_20_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20939)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(29063)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29063, 4237}, +/*h(4587)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4587, 4207}, +/*h(5574)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5574, 6079}, +/*h(406)=3 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {406, 4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1176_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16790)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16790, 4239}, +/*h(20971)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20971, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4563)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4563; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1425_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20947)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4595)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4595, 4207}, +/*h(29071)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29071, 4237}, +/*h(5582)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5582, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21966)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21966, 6079}, +/*h(20979)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {20979, 4207} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1088_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8580)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8580; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_756_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8612)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_561_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24996)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24996, 4236}, +/*h(1507)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1507, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1005_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8588)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8588; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8620)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_478_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1515)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1515, 6078}, +/*h(25004)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25004, 4236}, +/*h(25991)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25991, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((10*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_922_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8596)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8596; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24980)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24980, 4236}, +/*h(1491)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1491, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8628)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8628; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25012)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25012, 4236}, +/*h(25999)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25999, 6096}, +/*h(1523)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1523, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8582)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1108_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8614)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_913_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24998)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8590)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1161_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24974)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24974, 4236}, +/*h(1485)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1485, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1025_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8622)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_830_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25006)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1274_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8598)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1078_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(24982)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {24982, 4236}, +/*h(1493)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1493, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_942_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3462)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3462, 4292}, +/*h(8630)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {8630, 4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25014)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4236} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25014; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(389)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {389, 4237}, +/*h(5557)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5557, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16773)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16773, 4237}, +/*h(21941)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21941, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1313_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3498)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3498, 4296}, +/*h(4485)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4485, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26037)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {26037, 6096}, +/*h(20869)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20869, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_520_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7594)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7594, 4296}, +/*h(8581)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8581, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1215_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12677)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(421)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 421; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15818)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15818, 4296}, +/*h(16805)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16805, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_981_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4517)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_786_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20901)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8613)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8613, 4237}, +/*h(13781)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13781, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24997)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_883_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17877)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {17877, 6082}, +/*h(12709)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12709, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_688_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(436)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {436, 4239}, +/*h(1423)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1423, 6096}, +/*h(29093)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29093, 4237}, +/*h(5604)=3 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5604, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(397)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 397; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8589)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8589; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(429)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 429; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_8_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15826)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {15826, 4300}, +/*h(16813)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16813, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_898_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4525)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4525; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_703_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20909)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8621)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1398_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1516)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1516, 6077}, +/*h(25005)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25005, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12717)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1431)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1431, 6096}, +/*h(29101)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29101, 4237}, +/*h(5612)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5612, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21957)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {21957, 6082}, +/*h(16789)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16789, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8597)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8597; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24981)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_854_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(420)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {420, 4239}, +/*h(29077)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29077, 4237}, +/*h(5588)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5588, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(437)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 437; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16821)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_815_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4533)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4533, 4237}, +/*h(9701)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9701, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_620_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20917)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_22_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9616)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9616, 6097}, +/*h(13797)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13797, 6082}, +/*h(8629)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8629, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1315_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1524)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1524, 6077}, +/*h(30181)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30181, 6082}, +/*h(25013)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25013, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12725)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12725, 4237}, +/*h(17893)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {17893, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_969_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(391)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_773_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16775)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16775, 4237}, +/*h(21943)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21943, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4487)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20871)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_871_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8583)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8583, 4237}, +/*h(13751)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13751, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17847)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17847, 6096}, +/*h(12679)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12679, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(423)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 423; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16807)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1332_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9687)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9687, 6082}, +/*h(4519)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4519, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1137_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20903)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20903, 4237}, +/*h(26071)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {26071, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_539_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13783)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13783, 6082}, +/*h(9602)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9602, 6097}, +/*h(8615)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8615, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1510)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1510, 6077}, +/*h(30167)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30167, 6082}, +/*h(24999)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24999, 4237}, +/*h(25986)=3 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25986, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12711)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1039_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(29095)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29095, 4237}, +/*h(438)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {438, 4239}, +/*h(5606)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5606, 6079}, +/*h(1425)=3 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1425, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 11) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_788_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8591)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12687)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_554_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(431)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 431; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16815)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1249_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5514)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5514, 6094}, +/*h(4527)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4527, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20911)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9610)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9610, 6097}, +/*h(8623)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8623, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25007)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25007, 4237}, +/*h(25994)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25994, 6097}, +/*h(1518)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1518, 6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12719)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_957_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(29103)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 29103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13767)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13767, 6082}, +/*h(8599)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8599, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1494)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1494, 6077}, +/*h(30151)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30151, 6082}, +/*h(24983)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {24983, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1400_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12695)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12695, 4237}, +/*h(17863)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {17863, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(5590)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5590, 6079}, +/*h(422)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {422, 4239}, +/*h(1409)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1409, 6092}, +/*h(29079)=3 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {29079, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_471_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5607)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5607, 6082}, +/*h(439)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {439, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11655)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {11655, 4294}, +/*h(16823)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {16823, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1166_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5522)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5522, 6094}, +/*h(4535)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4535, 4237}, +/*h(9703)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9703, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_971_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21906)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21906, 6094}, +/*h(26087)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {26087, 6082}, +/*h(20919)=2 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {20919, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8631)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8631, 4237}, +/*h(3463)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3463, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(25015)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25015, 4237}, +/*h(1526)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1526, 6077}, +/*h(26002)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26002, 6097}, +/*h(30183)=3 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30183, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1069_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7559)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {7559, 4294}, +/*h(12727)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12727, 4237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24960)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_303_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8584)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8584; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8616)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25000)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1376_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8624)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8624; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25008)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8586)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8618)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8618, 4238}, +/*h(9605)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9605, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25002)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {25002, 4238}, +/*h(1513)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1513, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_239_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8626)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8626, 4238}, +/*h(9613)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9613, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25010)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {25010, 4238}, +/*h(1521)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1521, 6078}, +/*h(25997)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {25997, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8577)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8577; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_974_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7622)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7622, 4292}, +/*h(8609)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8609, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_778_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1504)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1504, 6078}, +/*h(24993)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24993, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1222_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8585)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8585; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_891_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7630)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7630, 4292}, +/*h(8617)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8617, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25001)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25001; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1139_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8593)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8593; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_808_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7638)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {7638, 4298}, +/*h(8625)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {8625, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25009)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8579)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8579; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1461_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1474)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1474, 6078}, +/*h(24963)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24963, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8611)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1130_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(24995)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 24995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_86_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8587)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8587; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1482)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1482, 6078}, +/*h(24971)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {24971, 4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8619)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1047_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25003)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8595)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8595; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8627)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8627; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_964_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25011)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4238} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(388)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 388; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16772)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16772; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_659_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16804)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_771_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(428)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 428; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16812)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16812; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_493_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16820)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16820, 4239}, +/*h(21988)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21988, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_49_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(390)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 390; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1342_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16774)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {4239} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1010_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16806)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16806, 4239}, +/*h(21974)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21974, 6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1122_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(430)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {430, 4239}, +/*h(1417)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1417, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_927_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16814)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16814, 4239}, +/*h(17801)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17801, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21990)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {21990, 6079}, +/*h(16822)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {16822, 4239}, +/*h(17809)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17809, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(416)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {416, 4240}, +/*h(5584)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5584, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1444_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16800)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16800, 4240}, +/*h(21968)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21968, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(392)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 392; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16776)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16776; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(424)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 424; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1361_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16808)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16808, 4240}, +/*h(17795)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17795, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(432)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 432; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16816)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_834_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(386)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {386, 4240}, +/*h(5554)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5554, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(394)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 394; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_556_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16778)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(426)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_225_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16810)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16810, 4240}, +/*h(15823)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {15823, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_473_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21954)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21954, 6080}, +/*h(16786)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16786, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(434)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_142_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(11650)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11650, 4296}, +/*h(15831)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {15831, 4299}, +/*h(16818)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16818, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(393)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 393; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15790)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15790, 4292}, +/*h(16777)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16777, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_988_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1412)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1412, 6091}, +/*h(425)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {425, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16809)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_905_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1420)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1420, 6091}, +/*h(5601)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5601, 6080}, +/*h(433)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {433, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_710_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16817)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16817, 4240}, +/*h(21985)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21985, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(387)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {387, 4240}, +/*h(5555)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5555, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_71_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16771)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 16771; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1422_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(419)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {419, 4240}, +/*h(5587)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5587, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(16803)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16803, 4240}, +/*h(21971)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21971, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1339_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1414)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1414, 6091}, +/*h(427)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {427, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1144_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17798)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17798, 6091}, +/*h(16811)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16811, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(435)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 435; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(17806)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17806, 6091}, +/*h(21987)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21987, 6080}, +/*h(16819)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {16819, 4240} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_393_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4484)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4484; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_198_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20868)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9684)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9684, 6081}, +/*h(4516)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4516, 4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1354_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20900)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20900, 4241}, +/*h(26068)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26068, 6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1466_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4524)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4524, 4241}, +/*h(5511)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5511, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1271_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20908)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20908, 4241}, +/*h(21895)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21895, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(9700)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9700, 6081}, +/*h(4532)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4532, 4241}, +/*h(5519)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5519, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(20916)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20916, 4241}, +/*h(21903)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21903, 6096}, +/*h(26084)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26084, 6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_744_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9654)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9654, 6095}, +/*h(4486)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4486, 4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20870)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20870, 4241}, +/*h(26038)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {26038, 6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4518)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_217_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(26070)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26070, 6081}, +/*h(20902)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20902, 4241}, +/*h(21889)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21889, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4526)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20910)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20910, 4241}, +/*h(21897)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21897, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4502)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4502, 4241}, +/*h(9670)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9670, 6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4534)=0 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15750)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15750, 4292}, +/*h(20918)=1 EVV 0x79 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {20918, 4241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1178_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9648)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9648, 6097}, +/*h(4480)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4480, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1095_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4488)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4488; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20872)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20872; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_764_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4520)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_569_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20904)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_817_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20880)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20880, 4242}, +/*h(26048)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26048, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4528)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4528; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20912)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4490)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4490, 4242}, +/*h(3503)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {3503, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20874)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4522)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4522; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20906)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1032_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4530)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4530, 4242}, +/*h(9698)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9698, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_837_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20914)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4489)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20873)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5508)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5508, 6093}, +/*h(4521)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4521, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21892)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21892, 6093}, +/*h(20905)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20905, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_112_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5516)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5516, 6093}, +/*h(9697)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9697, 6083}, +/*h(4529)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4529, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1405_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(21900)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21900, 6093}, +/*h(26081)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26081, 6083}, +/*h(20913)=2 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20913, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9651)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9651, 6097}, +/*h(4483)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4483, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_766_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(20867)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20867, 4242}, +/*h(26035)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26035, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4515)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4515; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26067)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26067, 6083}, +/*h(20899)=1 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {20899, 4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_878_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4491)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4491; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_547_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4523)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4523; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20907)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_795_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4499)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4499, 4242}, +/*h(9667)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9667, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4531)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4531; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(20915)=0 EVV 0x79 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {4242} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 20915; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2438)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2438, 4255}, +/*h(1451)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1451, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_348_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6534)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6534, 4255}, +/*h(5547)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5547, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1043_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10630)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10630; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14726)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2502)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6598)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_380_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5526)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5526, 6093}, +/*h(9707)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9707, 6083}, +/*h(10694)=2 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10694, 4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1075_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14790)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {14790, 4255}, +/*h(9622)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9622, 6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_809_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2470)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6566)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6566, 4255}, +/*h(11734)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {11734, 4298} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_711_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10662)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10662, 4255}, +/*h(15830)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {15830, 4298} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14758)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2534)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2534, 4255}, +/*h(26023)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {26023, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_841_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6630)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6630, 4255}, +/*h(1462)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1462, 6091}, +/*h(30119)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30119, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5558)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5558, 6093}, +/*h(10726)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10726, 4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_743_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14822)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1058_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2446)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2446, 4255}, +/*h(1459)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1459, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6542)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_960_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10638)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_167_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14734)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2510)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1090_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5619)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5619, 6080}, +/*h(30095)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30095, 6096}, +/*h(6606)=2 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6606, 4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10702)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {10702, 4255}, +/*h(9715)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9715, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14798)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2478)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6574)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10670)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14766)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2542)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2542, 4255}, +/*h(26031)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {26031, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_758_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6638)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6638, 4255}, +/*h(30127)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30127, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10734)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14830)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_975_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2454)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4256} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6550)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4256} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_877_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10646)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {10646, 4256}, +/*h(15814)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {15814, 4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_84_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14742)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4256} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2439)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6535)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_475_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9644)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9644, 6095}, +/*h(10631)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {10631, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14727)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1397_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25992)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25992, 6097}, +/*h(2503)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2503, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6599)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1299_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11682)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11682, 4296}, +/*h(10695)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {10695, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_507_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9623)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9623, 6096}, +/*h(14791)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {14791, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1484)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1484, 6077}, +/*h(2471)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2471, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_936_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5580)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5580, 6079}, +/*h(6567)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {6567, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10663)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_838_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15746)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15746, 4296}, +/*h(14759)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {14759, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2535)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2450)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2450, 4260}, +/*h(6631)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {6631, 4257}, +/*h(7618)=2 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7618, 4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_968_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5559)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5559, 6096}, +/*h(10727)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {10727, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10642)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {10642, 4260}, +/*h(9655)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9655, 6096}, +/*h(14823)=2 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {14823, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2447)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5556)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5556, 6093}, +/*h(6543)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {6543, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9652)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {9652, 6095}, +/*h(10639)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {10639, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14735)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26000)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26000, 6097}, +/*h(2511)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2511, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6607)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1216_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(11690)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11690, 4296}, +/*h(10703)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {10703, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14799)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2479)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2479, 4257}, +/*h(30149)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30149, 6082}, +/*h(1492)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1492, 6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_853_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6575)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_60_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10671)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_755_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(15754)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {15754, 4296}, +/*h(14767)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {14767, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_982_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3530)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3530, 4296}, +/*h(2543)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {2543, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7626)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7626, 4296}, +/*h(6639)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {6639, 4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10735)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10735; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14831)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7623)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {7623, 4294}, +/*h(2455)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {2455, 4258} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6551)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4258} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10647)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4258} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10647; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14743)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4258} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2434)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2434, 4259}, +/*h(6615)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {6615, 4262} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6530)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6530, 4259}, +/*h(10711)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {10711, 4262} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10626)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1036_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14722)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {14722, 4259}, +/*h(13735)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13735, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1263_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(25987)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25987, 6097}, +/*h(1511)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1511, 6082}, +/*h(2498)=2 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2498, 4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6594)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6594, 4259}, +/*h(1426)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1426, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10690)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14786)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2466)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2466, 4259}, +/*h(7634)=1 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {7634, 4300} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_802_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6562)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6562, 4259}, +/*h(5575)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5575, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10658)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {10658, 4259}, +/*h(9671)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9671, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_704_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14754)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2530)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6626)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_833_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10722)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9650)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9650, 6097}, +/*h(14818)=1 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {14818, 4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2442)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1050_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6538)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10634)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {10634, 4259}, +/*h(9647)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9647, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_953_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(14730)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {14730, 4259}, +/*h(13743)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13743, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1180_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2506)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {2506, 4259}, +/*h(1519)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1519, 6082}, +/*h(25995)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25995, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_387_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6602)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1082_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10698)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14794)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2474)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_719_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6570)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {6570, 4259}, +/*h(5583)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5583, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10666)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14762)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2538)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6634)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_750_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10730)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1446_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14826)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() FIX_ROUND_LEN128()*/ {4259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_967_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6546)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {6546, 4260}, +/*h(11714)=1 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {11714, 4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14738)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4260} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14738; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2518)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4261} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1007_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1446)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1446, 6091}, +/*h(30103)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30103, 6096}, +/*h(6614)=2 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {6614, 4261} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10710)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {10710, 4261}, +/*h(5542)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5542, 6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_909_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14806)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4261} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2519)=0 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4262} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9639)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {9639, 6096}, +/*h(14807)=1 EVV 0x79 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {14807, 4262} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1527)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1527, 6082}, +/*h(2514)=1 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {2514, 4263}, +/*h(26003)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26003, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6610)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4263} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10706)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4263} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(14802)=0 EVV 0x79 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_LDOP_Q() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4263} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 14802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7558)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11654)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3526)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_611_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3494)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7590)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_643_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7654)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11750)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_545_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15846)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3470)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_67_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7566)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7566; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_762_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11662)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15758)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3534)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_99_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11726)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_794_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15822)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_528_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3502)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3502; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7598)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11694)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7662)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11758)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15854)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 NOEVSR ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4292} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15854; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_777_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3478)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4293} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1472_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7574)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4293} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_679_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11670)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4293} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15751)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3527)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_738_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7591)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1433_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11687)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15783)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_867_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3559)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3559; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_74_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3474)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {3474, 4297}, +/*h(7655)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {7655, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_769_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7570)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {7570, 4297}, +/*h(11751)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {11751, 4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15847)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3471)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3471; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7567)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_194_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11663)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11663; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_889_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15759)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3535)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7631)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7631; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1018_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11727)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11727; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7599)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7599; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1350_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11695)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11695; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_557_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15791)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15791; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_784_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3567)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3567; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_686_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11759)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15855)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 NOEVSR ZEROING=0 MASK=0*/ {4294} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15855; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11671)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4295} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15767)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4295} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3458)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {3458, 4296}, +/*h(7639)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {7639, 4299} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_935_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7554)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {7554, 4296}, +/*h(11735)=1 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {11735, 4299} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7586)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15778)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15778; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_733_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3554)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1428_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7650)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11746)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1330_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15842)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_157_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3466)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_852_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7562)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11658)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_884_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11722)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11722; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15786)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15786; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_650_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3562)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7658)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15850)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() FIX_ROUND_LEN128()*/ {4296} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_672_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15762)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4297} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3542)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE FIX_ROUND_LEN128()*/ {4298} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1033_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3543)=0 EVV 0x79 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 NOEVSR ZEROING=0 MASK=0 EVEXRR_ONE*/ {4299} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_899_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3538)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4300} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_801_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(11730)=0 EVV 0x79 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_LDOP_D() EVEXRR_ONE FIX_ROUND_LEN128()*/ {4300} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 11730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_324_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1476)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1476, 6077}, +/*h(30133)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30133, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17860)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17860; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1480_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(30165)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30165, 6082}, +/*h(25984)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25984, 6097}, +/*h(1508)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1508, 6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17892)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {17892, 6077}, +/*h(13711)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13711, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17868)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17868; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17900)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {17900, 6077}, +/*h(13719)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13719, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17876)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17876; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1119_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17908)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_675_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1478)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1478, 6077}, +/*h(30135)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30135, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17862)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17894)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_592_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1486)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1486; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17870)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17902)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_314_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17878)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1471_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17910)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6077} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17856)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17856; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17888)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17888; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_695_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1512)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1512, 6078}, +/*h(25988)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25988, 6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17896)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_612_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1520)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1520, 6078}, +/*h(25996)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25996, 6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17904)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17904; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1129_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1506)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17890)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17890, 6078}, +/*h(13709)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13709, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1046_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1514)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1514, 6078}, +/*h(25990)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25990, 6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_851_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17898)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {17898, 6078}, +/*h(13717)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13717, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1490)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1490; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17874)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17874; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(25998)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {25998, 6095}, +/*h(1522)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {1522, 6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_768_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17906)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_541_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1473)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1473; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17857)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17857; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17889)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17889; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1481)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1481; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17865)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17865; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17897)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17897; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1489)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1489; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17873)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17873; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1337_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17905)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17905; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_892_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1475)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1475; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17859)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17859; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_366_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17891)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17867)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17867; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17899)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17899; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_532_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17875)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17875; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17907)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6078} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1019_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5572)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5572; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21956)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21956; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21964)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21964; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21996)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21996; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21972)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21972; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21958)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5614)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21998)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6079} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_873_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5622)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {5622, 6079}, +/*h(1441)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1441, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1473_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5600)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5600, 6080}, +/*h(1419)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1419, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21984)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21984, 6080}, +/*h(17803)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17803, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5576)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5576; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5608)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5608, 6080}, +/*h(1427)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1427, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21992)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21992, 6080}, +/*h(17811)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17811, 6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5616)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5616; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1112_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22000)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 22000; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5570)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5602)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5602, 6080}, +/*h(1421)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1421, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21986)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21986, 6080}, +/*h(17805)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17805, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5578)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5578; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21962)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_253_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5610)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5610, 6080}, +/*h(1429)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {1429, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21994)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21994, 6080}, +/*h(17813)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {17813, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_502_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5586)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21970)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1463_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22002)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 22002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5569)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5569; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1041_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21953)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21953; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_958_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21961)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_822_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1428)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1428, 6091}, +/*h(30085)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30085, 6096}, +/*h(5609)=2 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5609, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_627_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17812)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17812, 6091}, +/*h(21993)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21993, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_875_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21969)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21969; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1422)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1422, 6091}, +/*h(5603)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5603, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1173_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(30087)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30087, 6096}, +/*h(5611)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {5611, 6080}, +/*h(1430)=2 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1430, 6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_978_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17814)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {17814, 6091}, +/*h(21995)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {21995, 6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_895_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(22003)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6080} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 22003; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_31_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26052)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26052; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9708)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9708, 6081}, +/*h(5527)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5527, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1105_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26092)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26092, 6081}, +/*h(21911)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21911, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9716)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9716; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9702)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9702, 6081}, +/*h(5521)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5521, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26086)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26086, 6081}, +/*h(21905)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21905, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9678)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9710)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26094)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6081} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26094; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9686)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9686, 6081}, +/*h(5505)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5505, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9718)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {9718, 6081}, +/*h(5537)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5537, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26102)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {26102, 6081}, +/*h(21921)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21921, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5573)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5573; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1146_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9669)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9669; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_951_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26053)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13765)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1509)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1509, 6082}, +/*h(25985)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25985, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1424)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1424, 6092}, +/*h(5605)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5605, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1412_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17808)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17808, 6092}, +/*h(21989)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {21989, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21904)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21904, 6094}, +/*h(26085)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {26085, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5581)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5581; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21965)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1063_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9677)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9677; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_868_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26061)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13773)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30157)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30157; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_829_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1517)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1517, 6082}, +/*h(25993)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {25993, 6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_634_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17901)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5613)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5613; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21997)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9709)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9709; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26093)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26093; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13805)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30189)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30189; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_285_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1408)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1408, 6092}, +/*h(5589)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5589, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17792)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17792, 6092}, +/*h(21973)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {21973, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_980_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5504)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5504, 6094}, +/*h(9685)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {9685, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21888)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21888, 6094}, +/*h(26069)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {26069, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_746_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26001)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26001, 6097}, +/*h(1525)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {1525, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17909)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1440)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1440, 6092}, +/*h(5621)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5621, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17824)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17824, 6092}, +/*h(22005)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {22005, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1479)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1479; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_607_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21959)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26055)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17895)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17810)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17810, 6092}, +/*h(21991)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {21991, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9618)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9618, 6097}, +/*h(13799)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13799, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1487)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17871)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21967)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26063)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13775)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30159)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30159; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17903)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5615)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21999)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9711)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26095)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26095; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13807)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30191)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30191; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1495)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17879)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_636_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1410)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {1410, 6092}, +/*h(5591)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {5591, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(17794)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {17794, 6092}, +/*h(21975)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {21975, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_902_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17911)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_207_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9634)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {9634, 6097}, +/*h(13815)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13815, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26018)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {26018, 6097}, +/*h(30199)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {30199, 6082} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1012_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9664)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9664; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9696)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9696, 6083}, +/*h(5515)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5515, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26080)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26080, 6083}, +/*h(21899)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21899, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9672)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9672; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_734_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26056)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26056; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_597_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9704)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9704, 6083}, +/*h(5523)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {5523, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26088)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26088, 6083}, +/*h(21907)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {21907, 6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9680)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9680; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26064)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26064; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9712)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26096)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26096; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9666)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26050)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_836_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(26082)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26082, 6083}, +/*h(21901)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {21901, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9674)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9674; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1085_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26058)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26058; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_949_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(9706)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9706, 6083}, +/*h(5525)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {5525, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26090)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26090; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9682)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26066)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5524)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5524, 6093}, +/*h(9705)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9705, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21908)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21908, 6093}, +/*h(26089)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26089, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1434_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9713)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9713; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26097)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26097; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5518)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {5518, 6093}, +/*h(9699)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {9699, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21902)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21902, 6093}, +/*h(26083)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26083, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9675)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9675; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_517_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26059)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26059; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(21910)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {21910, 6093}, +/*h(26091)=1 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {26091, 6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_629_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9683)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9683; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26099)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6083} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26099; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17796)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17796; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_656_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1444)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1444, 6091}, +/*h(30101)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30101, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17804)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17804; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1452)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1452; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1460)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1460, 6091}, +/*h(30117)=1 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {30117, 6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17844)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17844; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_812_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17830)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1454)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1454; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_729_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17838)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17846)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6091} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1416)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1416; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17800)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1448)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1448; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1163_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17832)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1456)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1456; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17840)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17826)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17826; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1418)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1418; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17802)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17793)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17793; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_790_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1449)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1449; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17833)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17833; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_707_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1457)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1457; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17841)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17841; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1411)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1411; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1443)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1443; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17827)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17827; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_946_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17835)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17835; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_863_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17843)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6092} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17843; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5540)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5540; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21924)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21924; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1268_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5548)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5548; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1073_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21932)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_990_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21940)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21940; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5510)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21894)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21926)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_131_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5550)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1424_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21934)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21942)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6093} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_453_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21920)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21920; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_897_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5512)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5512; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_702_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21896)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21928)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5520)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5520; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5506)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21890)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1053_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21898)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5546)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5546; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5513)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5513; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1485_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5545)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5545; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1290_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21929)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21929; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5553)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5553; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1207_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21937)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21937; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5507)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5507; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_568_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21891)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21891; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_431_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5539)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5539; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21923)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21923; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_153_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21931)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21931; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21939)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21939; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_890_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9604)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9604; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9636)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9636; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26020)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26020; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_807_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9612)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9612; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26028)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26028; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9620)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9620; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26004)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26004; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26036)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1241_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9606)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_714_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26022)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9614)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_631_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26030)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_880_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26006)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6095} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1413)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1413; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17797)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5509)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5509; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21893)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(25989)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 25989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1017_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13701)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13701; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1445)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1445; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1380_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17829)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17829; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9637)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9637; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_685_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13733)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13733; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5517)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5517; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17837)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17837; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1395_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9645)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9645; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1200_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26029)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_602_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13741)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13741; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_407_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(30125)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 30125; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_753_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21909)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9621)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9621; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1449_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26005)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1410_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1461)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1461; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17845)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9653)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9653; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13749)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_770_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1415)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17799)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9607)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9607; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1368_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13703)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5543)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_939_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21927)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17807)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9615)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9615; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5551)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(21935)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 21935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(17815)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 17815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_312_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26007)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1463)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26039)=0 EVV 0x79 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6096} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26039; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9600)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9600; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9608)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9608; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_124_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9642)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9642; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26026)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1334_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26034)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1107_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9601)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9601; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_775_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9633)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9633; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26017)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26017; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1024_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9609)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9609; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_692_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9641)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9641; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26025)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26025; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9617)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9617; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(26033)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 26033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1458_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9603)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9603; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1375_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9611)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9611; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2_1292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(9619)=0 EVV 0x79 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6097} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 9619; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x79_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[1488] = { +/*h(21892)=0 */ {21892, xed3_phash_find_mapevex_map1_opcode0x79_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8595)=3 */ {8595, xed3_phash_find_mapevex_map1_opcode0x79_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1453)=5 */ {1453, xed3_phash_find_mapevex_map1_opcode0x79_vv2_5_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17800)=7 */ {17800, xed3_phash_find_mapevex_map1_opcode0x79_vv2_7_l1}, +/*h(15826)=8 */ {15826, xed3_phash_find_mapevex_map1_opcode0x79_vv2_8_l1}, +/*h(9671)=9 */ {9671, xed3_phash_find_mapevex_map1_opcode0x79_vv2_9_l1}, +/*h(4503)=10 */ {4503, xed3_phash_find_mapevex_map1_opcode0x79_vv2_10_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26018)=12 */ {26018, xed3_phash_find_mapevex_map1_opcode0x79_vv2_12_l1}, +/*h(25031)=13 */ {25031, xed3_phash_find_mapevex_map1_opcode0x79_vv2_13_l1}, +/*h(17889)=14 */ {17889, xed3_phash_find_mapevex_map1_opcode0x79_vv2_14_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11734)=16 */ {11734, xed3_phash_find_mapevex_map1_opcode0x79_vv2_16_l1}, +/*h(5579)=17 */ {5579, xed3_phash_find_mapevex_map1_opcode0x79_vv2_17_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21926)=19 */ {21926, xed3_phash_find_mapevex_map1_opcode0x79_vv2_19_l1}, +/*h(20939)=20 */ {20939, xed3_phash_find_mapevex_map1_opcode0x79_vv2_20_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9616)=22 */ {9616, xed3_phash_find_mapevex_map1_opcode0x79_vv2_22_l1}, +/*h(2474)=23 */ {2474, xed3_phash_find_mapevex_map1_opcode0x79_vv2_23_l1}, +/*h(1487)=24 */ {1487, xed3_phash_find_mapevex_map1_opcode0x79_vv2_24_l1}, +/*h(24976)=25 */ {24976, xed3_phash_find_mapevex_map1_opcode0x79_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17834)=27 */ {17834, xed3_phash_find_mapevex_map1_opcode0x79_vv2_27_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5524)=29 */ {5524, xed3_phash_find_mapevex_map1_opcode0x79_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26052)=31 */ {26052, xed3_phash_find_mapevex_map1_opcode0x79_vv2_31_l1}, +/*h(20884)=32 */ {20884, xed3_phash_find_mapevex_map1_opcode0x79_vv2_32_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5613)=36 */ {5613, xed3_phash_find_mapevex_map1_opcode0x79_vv2_36_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21960)=39 */ {21960, xed3_phash_find_mapevex_map1_opcode0x79_vv2_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9650)=41 */ {9650, xed3_phash_find_mapevex_map1_opcode0x79_vv2_41_l1}, +/*h(3495)=42 */ {3495, xed3_phash_find_mapevex_map1_opcode0x79_vv2_42_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25997)=44 */ {25997, xed3_phash_find_mapevex_map1_opcode0x79_vv2_44_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17868)=46 */ {17868, xed3_phash_find_mapevex_map1_opcode0x79_vv2_46_l1}, +/*h(16881)=47 */ {16881, xed3_phash_find_mapevex_map1_opcode0x79_vv2_47_l1}, +/*h(5558)=48 */ {5558, xed3_phash_find_mapevex_map1_opcode0x79_vv2_48_l1}, +/*h(390)=49 */ {390, xed3_phash_find_mapevex_map1_opcode0x79_vv2_49_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21905)=51 */ {21905, xed3_phash_find_mapevex_map1_opcode0x79_vv2_51_l1}, +/*h(15750)=52 */ {15750, xed3_phash_find_mapevex_map1_opcode0x79_vv2_52_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8608)=54 */ {8608, xed3_phash_find_mapevex_map1_opcode0x79_vv2_54_l1}, +/*h(6634)=55 */ {6634, xed3_phash_find_mapevex_map1_opcode0x79_vv2_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17813)=58 */ {17813, xed3_phash_find_mapevex_map1_opcode0x79_vv2_58_l1}, +/*h(11658)=59 */ {11658, xed3_phash_find_mapevex_map1_opcode0x79_vv2_59_l1}, +/*h(10671)=60 */ {10671, xed3_phash_find_mapevex_map1_opcode0x79_vv2_60_l1}, +/*h(9684)=61 */ {9684, xed3_phash_find_mapevex_map1_opcode0x79_vv2_61_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26031)=63 */ {26031, xed3_phash_find_mapevex_map1_opcode0x79_vv2_63_l1}, +/*h(25044)=64 */ {25044, xed3_phash_find_mapevex_map1_opcode0x79_vv2_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17902)=66 */ {17902, xed3_phash_find_mapevex_map1_opcode0x79_vv2_66_l1}, +/*h(7566)=67 */ {7566, xed3_phash_find_mapevex_map1_opcode0x79_vv2_67_l1}, +/*h(1411)=68 */ {1411, xed3_phash_find_mapevex_map1_opcode0x79_vv2_68_l1}, +/*h(424)=69 */ {424, xed3_phash_find_mapevex_map1_opcode0x79_vv2_69_l1}, +/*h(21939)=70 */ {21939, xed3_phash_find_mapevex_map1_opcode0x79_vv2_70_l1}, +/*h(16771)=71 */ {16771, xed3_phash_find_mapevex_map1_opcode0x79_vv2_71_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8642)=73 */ {8642, xed3_phash_find_mapevex_map1_opcode0x79_vv2_73_l1}, +/*h(3474)=74 */ {3474, xed3_phash_find_mapevex_map1_opcode0x79_vv2_74_l1}, +/*h(30157)=75 */ {30157, xed3_phash_find_mapevex_map1_opcode0x79_vv2_75_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17847)=78 */ {17847, xed3_phash_find_mapevex_map1_opcode0x79_vv2_78_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5537)=80 */ {5537, xed3_phash_find_mapevex_map1_opcode0x79_vv2_80_l1}, +/*h(4550)=81 */ {4550, xed3_phash_find_mapevex_map1_opcode0x79_vv2_81_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26065)=83 */ {26065, xed3_phash_find_mapevex_map1_opcode0x79_vv2_83_l1}, +/*h(14742)=84 */ {14742, xed3_phash_find_mapevex_map1_opcode0x79_vv2_84_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8587)=86 */ {8587, xed3_phash_find_mapevex_map1_opcode0x79_vv2_86_l1}, +/*h(1445)=87 */ {1445, xed3_phash_find_mapevex_map1_opcode0x79_vv2_87_l1}, +/*h(458)=88 */ {458, xed3_phash_find_mapevex_map1_opcode0x79_vv2_88_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17792)=90 */ {17792, xed3_phash_find_mapevex_map1_opcode0x79_vv2_90_l1}, +/*h(15818)=91 */ {15818, xed3_phash_find_mapevex_map1_opcode0x79_vv2_91_l1}, +/*h(14831)=92 */ {14831, xed3_phash_find_mapevex_map1_opcode0x79_vv2_92_l1}, +/*h(4495)=93 */ {4495, xed3_phash_find_mapevex_map1_opcode0x79_vv2_93_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30191)=95 */ {30191, xed3_phash_find_mapevex_map1_opcode0x79_vv2_95_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11726)=99 */ {11726, xed3_phash_find_mapevex_map1_opcode0x79_vv2_99_l1}, +/*h(5571)=100 */ {5571, xed3_phash_find_mapevex_map1_opcode0x79_vv2_100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26099)=102 */ {26099, xed3_phash_find_mapevex_map1_opcode0x79_vv2_102_l1}, +/*h(20931)=103 */ {20931, xed3_phash_find_mapevex_map1_opcode0x79_vv2_103_l1}, +/*h(9608)=104 */ {9608, xed3_phash_find_mapevex_map1_opcode0x79_vv2_104_l1}, +/*h(8621)=105 */ {8621, xed3_phash_find_mapevex_map1_opcode0x79_vv2_105_l1}, +/*h(7634)=106 */ {7634, xed3_phash_find_mapevex_map1_opcode0x79_vv2_106_l1}, +/*h(1479)=107 */ {1479, xed3_phash_find_mapevex_map1_opcode0x79_vv2_107_l1}, +/*h(24968)=108 */ {24968, xed3_phash_find_mapevex_map1_opcode0x79_vv2_108_l1}, +/*h(17826)=109 */ {17826, xed3_phash_find_mapevex_map1_opcode0x79_vv2_109_l1}, +/*h(22007)=110 */ {22007, xed3_phash_find_mapevex_map1_opcode0x79_vv2_110_l1}, +/*h(11671)=111 */ {11671, xed3_phash_find_mapevex_map1_opcode0x79_vv2_111_l1}, +/*h(5516)=112 */ {5516, xed3_phash_find_mapevex_map1_opcode0x79_vv2_112_l1}, +/*h(3542)=113 */ {3542, xed3_phash_find_mapevex_map1_opcode0x79_vv2_113_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20876)=115 */ {20876, xed3_phash_find_mapevex_map1_opcode0x79_vv2_115_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1424)=119 */ {1424, xed3_phash_find_mapevex_map1_opcode0x79_vv2_119_l1}, +/*h(437)=120 */ {437, xed3_phash_find_mapevex_map1_opcode0x79_vv2_120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21952)=122 */ {21952, xed3_phash_find_mapevex_map1_opcode0x79_vv2_122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9642)=124 */ {9642, xed3_phash_find_mapevex_map1_opcode0x79_vv2_124_l1}, +/*h(8655)=125 */ {8655, xed3_phash_find_mapevex_map1_opcode0x79_vv2_125_l1}, +/*h(25989)=126 */ {25989, xed3_phash_find_mapevex_map1_opcode0x79_vv2_126_l1}, +/*h(1513)=127 */ {1513, xed3_phash_find_mapevex_map1_opcode0x79_vv2_127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17860)=129 */ {17860, xed3_phash_find_mapevex_map1_opcode0x79_vv2_129_l1}, +/*h(16873)=130 */ {16873, xed3_phash_find_mapevex_map1_opcode0x79_vv2_130_l1}, +/*h(5550)=131 */ {5550, xed3_phash_find_mapevex_map1_opcode0x79_vv2_131_l1}, +/*h(4563)=132 */ {4563, xed3_phash_find_mapevex_map1_opcode0x79_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21897)=134 */ {21897, xed3_phash_find_mapevex_map1_opcode0x79_vv2_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12781)=137 */ {12781, xed3_phash_find_mapevex_map1_opcode0x79_vv2_137_l1}, +/*h(6626)=138 */ {6626, xed3_phash_find_mapevex_map1_opcode0x79_vv2_138_l1}, +/*h(1458)=139 */ {1458, xed3_phash_find_mapevex_map1_opcode0x79_vv2_139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17805)=141 */ {17805, xed3_phash_find_mapevex_map1_opcode0x79_vv2_141_l1}, +/*h(15831)=142 */ {15831, xed3_phash_find_mapevex_map1_opcode0x79_vv2_142_l1}, +/*h(10663)=143 */ {10663, xed3_phash_find_mapevex_map1_opcode0x79_vv2_143_l1}, +/*h(9676)=144 */ {9676, xed3_phash_find_mapevex_map1_opcode0x79_vv2_144_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26023)=146 */ {26023, xed3_phash_find_mapevex_map1_opcode0x79_vv2_146_l1}, +/*h(25036)=147 */ {25036, xed3_phash_find_mapevex_map1_opcode0x79_vv2_147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17894)=149 */ {17894, xed3_phash_find_mapevex_map1_opcode0x79_vv2_149_l1}, +/*h(7558)=150 */ {7558, xed3_phash_find_mapevex_map1_opcode0x79_vv2_150_l1}, +/*h(5584)=151 */ {5584, xed3_phash_find_mapevex_map1_opcode0x79_vv2_151_l1}, +/*h(4597)=152 */ {4597, xed3_phash_find_mapevex_map1_opcode0x79_vv2_152_l1}, +/*h(21931)=153 */ {21931, xed3_phash_find_mapevex_map1_opcode0x79_vv2_153_l1}, +/*h(20944)=154 */ {20944, xed3_phash_find_mapevex_map1_opcode0x79_vv2_154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9621)=156 */ {9621, xed3_phash_find_mapevex_map1_opcode0x79_vv2_156_l1}, +/*h(3466)=157 */ {3466, xed3_phash_find_mapevex_map1_opcode0x79_vv2_157_l1}, +/*h(30149)=158 */ {30149, xed3_phash_find_mapevex_map1_opcode0x79_vv2_158_l1}, +/*h(24981)=159 */ {24981, xed3_phash_find_mapevex_map1_opcode0x79_vv2_159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17839)=161 */ {17839, xed3_phash_find_mapevex_map1_opcode0x79_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9710)=163 */ {9710, xed3_phash_find_mapevex_map1_opcode0x79_vv2_163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26057)=166 */ {26057, xed3_phash_find_mapevex_map1_opcode0x79_vv2_166_l1}, +/*h(14734)=167 */ {14734, xed3_phash_find_mapevex_map1_opcode0x79_vv2_167_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8579)=169 */ {8579, xed3_phash_find_mapevex_map1_opcode0x79_vv2_169_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5618)=171 */ {5618, xed3_phash_find_mapevex_map1_opcode0x79_vv2_171_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21965)=173 */ {21965, xed3_phash_find_mapevex_map1_opcode0x79_vv2_173_l1}, +/*h(15810)=174 */ {15810, xed3_phash_find_mapevex_map1_opcode0x79_vv2_174_l1}, +/*h(9655)=175 */ {9655, xed3_phash_find_mapevex_map1_opcode0x79_vv2_175_l1}, +/*h(4487)=176 */ {4487, xed3_phash_find_mapevex_map1_opcode0x79_vv2_176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26002)=178 */ {26002, xed3_phash_find_mapevex_map1_opcode0x79_vv2_178_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17873)=180 */ {17873, xed3_phash_find_mapevex_map1_opcode0x79_vv2_180_l1}, +/*h(11718)=181 */ {11718, xed3_phash_find_mapevex_map1_opcode0x79_vv2_181_l1}, +/*h(6550)=182 */ {6550, xed3_phash_find_mapevex_map1_opcode0x79_vv2_182_l1}, +/*h(395)=183 */ {395, xed3_phash_find_mapevex_map1_opcode0x79_vv2_183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21910)=185 */ {21910, xed3_phash_find_mapevex_map1_opcode0x79_vv2_185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9600)=187 */ {9600, xed3_phash_find_mapevex_map1_opcode0x79_vv2_187_l1}, +/*h(13781)=188 */ {13781, xed3_phash_find_mapevex_map1_opcode0x79_vv2_188_l1}, +/*h(7626)=189 */ {7626, xed3_phash_find_mapevex_map1_opcode0x79_vv2_189_l1}, +/*h(24960)=190 */ {24960, xed3_phash_find_mapevex_map1_opcode0x79_vv2_190_l1}, +/*h(484)=191 */ {484, xed3_phash_find_mapevex_map1_opcode0x79_vv2_191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21999)=193 */ {21999, xed3_phash_find_mapevex_map1_opcode0x79_vv2_193_l1}, +/*h(11663)=194 */ {11663, xed3_phash_find_mapevex_map1_opcode0x79_vv2_194_l1}, +/*h(5508)=195 */ {5508, xed3_phash_find_mapevex_map1_opcode0x79_vv2_195_l1}, +/*h(3534)=196 */ {3534, xed3_phash_find_mapevex_map1_opcode0x79_vv2_196_l1}, +/*h(26036)=197 */ {26036, xed3_phash_find_mapevex_map1_opcode0x79_vv2_197_l1}, +/*h(20868)=198 */ {20868, xed3_phash_find_mapevex_map1_opcode0x79_vv2_198_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17907)=200 */ {17907, xed3_phash_find_mapevex_map1_opcode0x79_vv2_200_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1416)=202 */ {1416, xed3_phash_find_mapevex_map1_opcode0x79_vv2_202_l1}, +/*h(429)=203 */ {429, xed3_phash_find_mapevex_map1_opcode0x79_vv2_203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16776)=205 */ {16776, xed3_phash_find_mapevex_map1_opcode0x79_vv2_205_l1}, +/*h(14802)=206 */ {14802, xed3_phash_find_mapevex_map1_opcode0x79_vv2_206_l1}, +/*h(9634)=207 */ {9634, xed3_phash_find_mapevex_map1_opcode0x79_vv2_207_l1}, +/*h(3479)=208 */ {3479, xed3_phash_find_mapevex_map1_opcode0x79_vv2_208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1505)=210 */ {1505, xed3_phash_find_mapevex_map1_opcode0x79_vv2_210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16865)=213 */ {16865, xed3_phash_find_mapevex_map1_opcode0x79_vv2_213_l1}, +/*h(5542)=214 */ {5542, xed3_phash_find_mapevex_map1_opcode0x79_vv2_214_l1}, +/*h(4555)=215 */ {4555, xed3_phash_find_mapevex_map1_opcode0x79_vv2_215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21889)=217 */ {21889, xed3_phash_find_mapevex_map1_opcode0x79_vv2_217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8592)=220 */ {8592, xed3_phash_find_mapevex_map1_opcode0x79_vv2_220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1450)=222 */ {1450, xed3_phash_find_mapevex_map1_opcode0x79_vv2_222_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17797)=224 */ {17797, xed3_phash_find_mapevex_map1_opcode0x79_vv2_224_l1}, +/*h(15823)=225 */ {15823, xed3_phash_find_mapevex_map1_opcode0x79_vv2_225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9668)=227 */ {9668, xed3_phash_find_mapevex_map1_opcode0x79_vv2_227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25028)=230 */ {25028, xed3_phash_find_mapevex_map1_opcode0x79_vv2_230_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5576)=234 */ {5576, xed3_phash_find_mapevex_map1_opcode0x79_vv2_234_l1}, +/*h(4589)=235 */ {4589, xed3_phash_find_mapevex_map1_opcode0x79_vv2_235_l1}, +/*h(21923)=236 */ {21923, xed3_phash_find_mapevex_map1_opcode0x79_vv2_236_l1}, +/*h(20936)=237 */ {20936, xed3_phash_find_mapevex_map1_opcode0x79_vv2_237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9613)=239 */ {9613, xed3_phash_find_mapevex_map1_opcode0x79_vv2_239_l1}, +/*h(7639)=240 */ {7639, xed3_phash_find_mapevex_map1_opcode0x79_vv2_240_l1}, +/*h(1484)=241 */ {1484, xed3_phash_find_mapevex_map1_opcode0x79_vv2_241_l1}, +/*h(24973)=242 */ {24973, xed3_phash_find_mapevex_map1_opcode0x79_vv2_242_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17831)=244 */ {17831, xed3_phash_find_mapevex_map1_opcode0x79_vv2_244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5521)=246 */ {5521, xed3_phash_find_mapevex_map1_opcode0x79_vv2_246_l1}, +/*h(4534)=247 */ {4534, xed3_phash_find_mapevex_map1_opcode0x79_vv2_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26049)=249 */ {26049, xed3_phash_find_mapevex_map1_opcode0x79_vv2_249_l1}, +/*h(14726)=250 */ {14726, xed3_phash_find_mapevex_map1_opcode0x79_vv2_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1429)=253 */ {1429, xed3_phash_find_mapevex_map1_opcode0x79_vv2_253_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21957)=256 */ {21957, xed3_phash_find_mapevex_map1_opcode0x79_vv2_256_l1}, +/*h(20970)=257 */ {20970, xed3_phash_find_mapevex_map1_opcode0x79_vv2_257_l1}, +/*h(9647)=258 */ {9647, xed3_phash_find_mapevex_map1_opcode0x79_vv2_258_l1}, +/*h(8660)=259 */ {8660, xed3_phash_find_mapevex_map1_opcode0x79_vv2_259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25994)=261 */ {25994, xed3_phash_find_mapevex_map1_opcode0x79_vv2_261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17865)=263 */ {17865, xed3_phash_find_mapevex_map1_opcode0x79_vv2_263_l1}, +/*h(16878)=264 */ {16878, xed3_phash_find_mapevex_map1_opcode0x79_vv2_264_l1}, +/*h(6542)=265 */ {6542, xed3_phash_find_mapevex_map1_opcode0x79_vv2_265_l1}, +/*h(5555)=266 */ {5555, xed3_phash_find_mapevex_map1_opcode0x79_vv2_266_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21902)=268 */ {21902, xed3_phash_find_mapevex_map1_opcode0x79_vv2_268_l1}, +/*h(20915)=269 */ {20915, xed3_phash_find_mapevex_map1_opcode0x79_vv2_269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13773)=271 */ {13773, xed3_phash_find_mapevex_map1_opcode0x79_vv2_271_l1}, +/*h(7618)=272 */ {7618, xed3_phash_find_mapevex_map1_opcode0x79_vv2_272_l1}, +/*h(1463)=273 */ {1463, xed3_phash_find_mapevex_map1_opcode0x79_vv2_273_l1}, +/*h(29133)=274 */ {29133, xed3_phash_find_mapevex_map1_opcode0x79_vv2_274_l1}, +/*h(17810)=275 */ {17810, xed3_phash_find_mapevex_map1_opcode0x79_vv2_275_l1}, +/*h(11655)=276 */ {11655, xed3_phash_find_mapevex_map1_opcode0x79_vv2_276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9681)=278 */ {9681, xed3_phash_find_mapevex_map1_opcode0x79_vv2_278_l1}, +/*h(3526)=279 */ {3526, xed3_phash_find_mapevex_map1_opcode0x79_vv2_279_l1}, +/*h(26028)=280 */ {26028, xed3_phash_find_mapevex_map1_opcode0x79_vv2_280_l1}, +/*h(25041)=281 */ {25041, xed3_phash_find_mapevex_map1_opcode0x79_vv2_281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17899)=283 */ {17899, xed3_phash_find_mapevex_map1_opcode0x79_vv2_283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1408)=285 */ {1408, xed3_phash_find_mapevex_map1_opcode0x79_vv2_285_l1}, +/*h(421)=286 */ {421, xed3_phash_find_mapevex_map1_opcode0x79_vv2_286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21936)=288 */ {21936, xed3_phash_find_mapevex_map1_opcode0x79_vv2_288_l1}, +/*h(14794)=289 */ {14794, xed3_phash_find_mapevex_map1_opcode0x79_vv2_289_l1}, +/*h(13807)=290 */ {13807, xed3_phash_find_mapevex_map1_opcode0x79_vv2_290_l1}, +/*h(3471)=291 */ {3471, xed3_phash_find_mapevex_map1_opcode0x79_vv2_291_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(29167)=293 */ {29167, xed3_phash_find_mapevex_map1_opcode0x79_vv2_293_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17844)=295 */ {17844, xed3_phash_find_mapevex_map1_opcode0x79_vv2_295_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9715)=297 */ {9715, xed3_phash_find_mapevex_map1_opcode0x79_vv2_297_l1}, +/*h(4547)=298 */ {4547, xed3_phash_find_mapevex_map1_opcode0x79_vv2_298_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26062)=300 */ {26062, xed3_phash_find_mapevex_map1_opcode0x79_vv2_300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8584)=303 */ {8584, xed3_phash_find_mapevex_map1_opcode0x79_vv2_303_l1}, +/*h(6610)=304 */ {6610, xed3_phash_find_mapevex_map1_opcode0x79_vv2_304_l1}, +/*h(1442)=305 */ {1442, xed3_phash_find_mapevex_map1_opcode0x79_vv2_305_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21970)=307 */ {21970, xed3_phash_find_mapevex_map1_opcode0x79_vv2_307_l1}, +/*h(15815)=308 */ {15815, xed3_phash_find_mapevex_map1_opcode0x79_vv2_308_l1}, +/*h(10647)=309 */ {10647, xed3_phash_find_mapevex_map1_opcode0x79_vv2_309_l1}, +/*h(4492)=310 */ {4492, xed3_phash_find_mapevex_map1_opcode0x79_vv2_310_l1}, +/*h(2518)=311 */ {2518, xed3_phash_find_mapevex_map1_opcode0x79_vv2_311_l1}, +/*h(26007)=312 */ {26007, xed3_phash_find_mapevex_map1_opcode0x79_vv2_312_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17878)=314 */ {17878, xed3_phash_find_mapevex_map1_opcode0x79_vv2_314_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5568)=317 */ {5568, xed3_phash_find_mapevex_map1_opcode0x79_vv2_317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26096)=319 */ {26096, xed3_phash_find_mapevex_map1_opcode0x79_vv2_319_l1}, +/*h(20928)=320 */ {20928, xed3_phash_find_mapevex_map1_opcode0x79_vv2_320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9605)=322 */ {9605, xed3_phash_find_mapevex_map1_opcode0x79_vv2_322_l1}, +/*h(7631)=323 */ {7631, xed3_phash_find_mapevex_map1_opcode0x79_vv2_323_l1}, +/*h(30133)=324 */ {30133, xed3_phash_find_mapevex_map1_opcode0x79_vv2_324_l1}, +/*h(24965)=325 */ {24965, xed3_phash_find_mapevex_map1_opcode0x79_vv2_325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22004)=327 */ {22004, xed3_phash_find_mapevex_map1_opcode0x79_vv2_327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5513)=329 */ {5513, xed3_phash_find_mapevex_map1_opcode0x79_vv2_329_l1}, +/*h(4526)=330 */ {4526, xed3_phash_find_mapevex_map1_opcode0x79_vv2_330_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20873)=332 */ {20873, xed3_phash_find_mapevex_map1_opcode0x79_vv2_332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1421)=336 */ {1421, xed3_phash_find_mapevex_map1_opcode0x79_vv2_336_l1}, +/*h(434)=337 */ {434, xed3_phash_find_mapevex_map1_opcode0x79_vv2_337_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16781)=339 */ {16781, xed3_phash_find_mapevex_map1_opcode0x79_vv2_339_l1}, +/*h(10626)=340 */ {10626, xed3_phash_find_mapevex_map1_opcode0x79_vv2_340_l1}, +/*h(9639)=341 */ {9639, xed3_phash_find_mapevex_map1_opcode0x79_vv2_341_l1}, +/*h(8652)=342 */ {8652, xed3_phash_find_mapevex_map1_opcode0x79_vv2_342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25986)=344 */ {25986, xed3_phash_find_mapevex_map1_opcode0x79_vv2_344_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17857)=346 */ {17857, xed3_phash_find_mapevex_map1_opcode0x79_vv2_346_l1}, +/*h(16870)=347 */ {16870, xed3_phash_find_mapevex_map1_opcode0x79_vv2_347_l1}, +/*h(5547)=348 */ {5547, xed3_phash_find_mapevex_map1_opcode0x79_vv2_348_l1}, +/*h(4560)=349 */ {4560, xed3_phash_find_mapevex_map1_opcode0x79_vv2_349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21894)=351 */ {21894, xed3_phash_find_mapevex_map1_opcode0x79_vv2_351_l1}, +/*h(20907)=352 */ {20907, xed3_phash_find_mapevex_map1_opcode0x79_vv2_352_l1}, +/*h(13765)=353 */ {13765, xed3_phash_find_mapevex_map1_opcode0x79_vv2_353_l1}, +/*h(8597)=354 */ {8597, xed3_phash_find_mapevex_map1_opcode0x79_vv2_354_l1}, +/*h(2442)=355 */ {2442, xed3_phash_find_mapevex_map1_opcode0x79_vv2_355_l1}, +/*h(1455)=356 */ {1455, xed3_phash_find_mapevex_map1_opcode0x79_vv2_356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17802)=358 */ {17802, xed3_phash_find_mapevex_map1_opcode0x79_vv2_358_l1}, +/*h(16815)=359 */ {16815, xed3_phash_find_mapevex_map1_opcode0x79_vv2_359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9673)=361 */ {9673, xed3_phash_find_mapevex_map1_opcode0x79_vv2_361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26020)=363 */ {26020, xed3_phash_find_mapevex_map1_opcode0x79_vv2_363_l1}, +/*h(25033)=364 */ {25033, xed3_phash_find_mapevex_map1_opcode0x79_vv2_364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17891)=366 */ {17891, xed3_phash_find_mapevex_map1_opcode0x79_vv2_366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5581)=368 */ {5581, xed3_phash_find_mapevex_map1_opcode0x79_vv2_368_l1}, +/*h(4594)=369 */ {4594, xed3_phash_find_mapevex_map1_opcode0x79_vv2_369_l1}, +/*h(21928)=370 */ {21928, xed3_phash_find_mapevex_map1_opcode0x79_vv2_370_l1}, +/*h(20941)=371 */ {20941, xed3_phash_find_mapevex_map1_opcode0x79_vv2_371_l1}, +/*h(14786)=372 */ {14786, xed3_phash_find_mapevex_map1_opcode0x79_vv2_372_l1}, +/*h(9618)=373 */ {9618, xed3_phash_find_mapevex_map1_opcode0x79_vv2_373_l1}, +/*h(3463)=374 */ {3463, xed3_phash_find_mapevex_map1_opcode0x79_vv2_374_l1}, +/*h(1489)=375 */ {1489, xed3_phash_find_mapevex_map1_opcode0x79_vv2_375_l1}, +/*h(24978)=376 */ {24978, xed3_phash_find_mapevex_map1_opcode0x79_vv2_376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17836)=378 */ {17836, xed3_phash_find_mapevex_map1_opcode0x79_vv2_378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5526)=380 */ {5526, xed3_phash_find_mapevex_map1_opcode0x79_vv2_380_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26054)=383 */ {26054, xed3_phash_find_mapevex_map1_opcode0x79_vv2_383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8576)=386 */ {8576, xed3_phash_find_mapevex_map1_opcode0x79_vv2_386_l1}, +/*h(6602)=387 */ {6602, xed3_phash_find_mapevex_map1_opcode0x79_vv2_387_l1}, +/*h(5615)=388 */ {5615, xed3_phash_find_mapevex_map1_opcode0x79_vv2_388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21962)=390 */ {21962, xed3_phash_find_mapevex_map1_opcode0x79_vv2_390_l1}, +/*h(20975)=391 */ {20975, xed3_phash_find_mapevex_map1_opcode0x79_vv2_391_l1}, +/*h(9652)=392 */ {9652, xed3_phash_find_mapevex_map1_opcode0x79_vv2_392_l1}, +/*h(4484)=393 */ {4484, xed3_phash_find_mapevex_map1_opcode0x79_vv2_393_l1}, +/*h(2510)=394 */ {2510, xed3_phash_find_mapevex_map1_opcode0x79_vv2_394_l1}, +/*h(25999)=395 */ {25999, xed3_phash_find_mapevex_map1_opcode0x79_vv2_395_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17870)=397 */ {17870, xed3_phash_find_mapevex_map1_opcode0x79_vv2_397_l1}, +/*h(16883)=398 */ {16883, xed3_phash_find_mapevex_map1_opcode0x79_vv2_398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(392)=400 */ {392, xed3_phash_find_mapevex_map1_opcode0x79_vv2_400_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21907)=402 */ {21907, xed3_phash_find_mapevex_map1_opcode0x79_vv2_402_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8610)=405 */ {8610, xed3_phash_find_mapevex_map1_opcode0x79_vv2_405_l1}, +/*h(7623)=406 */ {7623, xed3_phash_find_mapevex_map1_opcode0x79_vv2_406_l1}, +/*h(30125)=407 */ {30125, xed3_phash_find_mapevex_map1_opcode0x79_vv2_407_l1}, +/*h(481)=408 */ {481, xed3_phash_find_mapevex_map1_opcode0x79_vv2_408_l1}, +/*h(17815)=409 */ {17815, xed3_phash_find_mapevex_map1_opcode0x79_vv2_409_l1}, +/*h(21996)=410 */ {21996, xed3_phash_find_mapevex_map1_opcode0x79_vv2_410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5505)=412 */ {5505, xed3_phash_find_mapevex_map1_opcode0x79_vv2_412_l1}, +/*h(4518)=413 */ {4518, xed3_phash_find_mapevex_map1_opcode0x79_vv2_413_l1}, +/*h(26033)=414 */ {26033, xed3_phash_find_mapevex_map1_opcode0x79_vv2_414_l1}, +/*h(20865)=415 */ {20865, xed3_phash_find_mapevex_map1_opcode0x79_vv2_415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17904)=417 */ {17904, xed3_phash_find_mapevex_map1_opcode0x79_vv2_417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1413)=419 */ {1413, xed3_phash_find_mapevex_map1_opcode0x79_vv2_419_l1}, +/*h(426)=420 */ {426, xed3_phash_find_mapevex_map1_opcode0x79_vv2_420_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21941)=422 */ {21941, xed3_phash_find_mapevex_map1_opcode0x79_vv2_422_l1}, +/*h(15786)=423 */ {15786, xed3_phash_find_mapevex_map1_opcode0x79_vv2_423_l1}, +/*h(14799)=424 */ {14799, xed3_phash_find_mapevex_map1_opcode0x79_vv2_424_l1}, +/*h(8644)=425 */ {8644, xed3_phash_find_mapevex_map1_opcode0x79_vv2_425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30159)=427 */ {30159, xed3_phash_find_mapevex_map1_opcode0x79_vv2_427_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11694)=430 */ {11694, xed3_phash_find_mapevex_map1_opcode0x79_vv2_430_l1}, +/*h(5539)=431 */ {5539, xed3_phash_find_mapevex_map1_opcode0x79_vv2_431_l1}, +/*h(4552)=432 */ {4552, xed3_phash_find_mapevex_map1_opcode0x79_vv2_432_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26067)=434 */ {26067, xed3_phash_find_mapevex_map1_opcode0x79_vv2_434_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8589)=437 */ {8589, xed3_phash_find_mapevex_map1_opcode0x79_vv2_437_l1}, +/*h(6615)=438 */ {6615, xed3_phash_find_mapevex_map1_opcode0x79_vv2_438_l1}, +/*h(1447)=439 */ {1447, xed3_phash_find_mapevex_map1_opcode0x79_vv2_439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17794)=441 */ {17794, xed3_phash_find_mapevex_map1_opcode0x79_vv2_441_l1}, +/*h(16807)=442 */ {16807, xed3_phash_find_mapevex_map1_opcode0x79_vv2_442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9665)=444 */ {9665, xed3_phash_find_mapevex_map1_opcode0x79_vv2_444_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25025)=447 */ {25025, xed3_phash_find_mapevex_map1_opcode0x79_vv2_447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5573)=451 */ {5573, xed3_phash_find_mapevex_map1_opcode0x79_vv2_451_l1}, +/*h(405)=452 */ {405, xed3_phash_find_mapevex_map1_opcode0x79_vv2_452_l1}, +/*h(21920)=453 */ {21920, xed3_phash_find_mapevex_map1_opcode0x79_vv2_453_l1}, +/*h(26101)=454 */ {26101, xed3_phash_find_mapevex_map1_opcode0x79_vv2_454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9610)=456 */ {9610, xed3_phash_find_mapevex_map1_opcode0x79_vv2_456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1481)=458 */ {1481, xed3_phash_find_mapevex_map1_opcode0x79_vv2_458_l1}, +/*h(24970)=459 */ {24970, xed3_phash_find_mapevex_map1_opcode0x79_vv2_459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17828)=461 */ {17828, xed3_phash_find_mapevex_map1_opcode0x79_vv2_461_l1}, +/*h(15854)=462 */ {15854, xed3_phash_find_mapevex_map1_opcode0x79_vv2_462_l1}, +/*h(5518)=463 */ {5518, xed3_phash_find_mapevex_map1_opcode0x79_vv2_463_l1}, +/*h(4531)=464 */ {4531, xed3_phash_find_mapevex_map1_opcode0x79_vv2_464_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20878)=466 */ {20878, xed3_phash_find_mapevex_map1_opcode0x79_vv2_466_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12749)=469 */ {12749, xed3_phash_find_mapevex_map1_opcode0x79_vv2_469_l1}, +/*h(1426)=470 */ {1426, xed3_phash_find_mapevex_map1_opcode0x79_vv2_470_l1}, +/*h(5607)=471 */ {5607, xed3_phash_find_mapevex_map1_opcode0x79_vv2_471_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21954)=473 */ {21954, xed3_phash_find_mapevex_map1_opcode0x79_vv2_473_l1}, +/*h(20967)=474 */ {20967, xed3_phash_find_mapevex_map1_opcode0x79_vv2_474_l1}, +/*h(9644)=475 */ {9644, xed3_phash_find_mapevex_map1_opcode0x79_vv2_475_l1}, +/*h(8657)=476 */ {8657, xed3_phash_find_mapevex_map1_opcode0x79_vv2_476_l1}, +/*h(2502)=477 */ {2502, xed3_phash_find_mapevex_map1_opcode0x79_vv2_477_l1}, +/*h(25991)=478 */ {25991, xed3_phash_find_mapevex_map1_opcode0x79_vv2_478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17862)=480 */ {17862, xed3_phash_find_mapevex_map1_opcode0x79_vv2_480_l1}, +/*h(16875)=481 */ {16875, xed3_phash_find_mapevex_map1_opcode0x79_vv2_481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5552)=483 */ {5552, xed3_phash_find_mapevex_map1_opcode0x79_vv2_483_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21899)=485 */ {21899, xed3_phash_find_mapevex_map1_opcode0x79_vv2_485_l1}, +/*h(20912)=486 */ {20912, xed3_phash_find_mapevex_map1_opcode0x79_vv2_486_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12783)=488 */ {12783, xed3_phash_find_mapevex_map1_opcode0x79_vv2_488_l1}, +/*h(2447)=489 */ {2447, xed3_phash_find_mapevex_map1_opcode0x79_vv2_489_l1}, +/*h(30117)=490 */ {30117, xed3_phash_find_mapevex_map1_opcode0x79_vv2_490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17807)=492 */ {17807, xed3_phash_find_mapevex_map1_opcode0x79_vv2_492_l1}, +/*h(21988)=493 */ {21988, xed3_phash_find_mapevex_map1_opcode0x79_vv2_493_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9678)=495 */ {9678, xed3_phash_find_mapevex_map1_opcode0x79_vv2_495_l1}, +/*h(8691)=496 */ {8691, xed3_phash_find_mapevex_map1_opcode0x79_vv2_496_l1}, +/*h(26025)=497 */ {26025, xed3_phash_find_mapevex_map1_opcode0x79_vv2_497_l1}, +/*h(25038)=498 */ {25038, xed3_phash_find_mapevex_map1_opcode0x79_vv2_498_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17896)=500 */ {17896, xed3_phash_find_mapevex_map1_opcode0x79_vv2_500_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5586)=502 */ {5586, xed3_phash_find_mapevex_map1_opcode0x79_vv2_502_l1}, +/*h(418)=503 */ {418, xed3_phash_find_mapevex_map1_opcode0x79_vv2_503_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21933)=505 */ {21933, xed3_phash_find_mapevex_map1_opcode0x79_vv2_505_l1}, +/*h(15778)=506 */ {15778, xed3_phash_find_mapevex_map1_opcode0x79_vv2_506_l1}, +/*h(9623)=507 */ {9623, xed3_phash_find_mapevex_map1_opcode0x79_vv2_507_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30151)=510 */ {30151, xed3_phash_find_mapevex_map1_opcode0x79_vv2_510_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17841)=512 */ {17841, xed3_phash_find_mapevex_map1_opcode0x79_vv2_512_l1}, +/*h(11686)=513 */ {11686, xed3_phash_find_mapevex_map1_opcode0x79_vv2_513_l1}, +/*h(9712)=514 */ {9712, xed3_phash_find_mapevex_map1_opcode0x79_vv2_514_l1}, +/*h(4544)=515 */ {4544, xed3_phash_find_mapevex_map1_opcode0x79_vv2_515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26059)=517 */ {26059, xed3_phash_find_mapevex_map1_opcode0x79_vv2_517_l1}, +/*h(25072)=518 */ {25072, xed3_phash_find_mapevex_map1_opcode0x79_vv2_518_l1}, +/*h(13749)=519 */ {13749, xed3_phash_find_mapevex_map1_opcode0x79_vv2_519_l1}, +/*h(7594)=520 */ {7594, xed3_phash_find_mapevex_map1_opcode0x79_vv2_520_l1}, +/*h(6607)=521 */ {6607, xed3_phash_find_mapevex_map1_opcode0x79_vv2_521_l1}, +/*h(5620)=522 */ {5620, xed3_phash_find_mapevex_map1_opcode0x79_vv2_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21967)=524 */ {21967, xed3_phash_find_mapevex_map1_opcode0x79_vv2_524_l1}, +/*h(20980)=525 */ {20980, xed3_phash_find_mapevex_map1_opcode0x79_vv2_525_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4489)=527 */ {4489, xed3_phash_find_mapevex_map1_opcode0x79_vv2_527_l1}, +/*h(3502)=528 */ {3502, xed3_phash_find_mapevex_map1_opcode0x79_vv2_528_l1}, +/*h(26004)=529 */ {26004, xed3_phash_find_mapevex_map1_opcode0x79_vv2_529_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17875)=532 */ {17875, xed3_phash_find_mapevex_map1_opcode0x79_vv2_532_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(397)=534 */ {397, xed3_phash_find_mapevex_map1_opcode0x79_vv2_534_l1}, +/*h(4578)=535 */ {4578, xed3_phash_find_mapevex_map1_opcode0x79_vv2_535_l1}, +/*h(26093)=536 */ {26093, xed3_phash_find_mapevex_map1_opcode0x79_vv2_536_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9602)=539 */ {9602, xed3_phash_find_mapevex_map1_opcode0x79_vv2_539_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1473)=541 */ {1473, xed3_phash_find_mapevex_map1_opcode0x79_vv2_541_l1}, +/*h(24962)=542 */ {24962, xed3_phash_find_mapevex_map1_opcode0x79_vv2_542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22001)=544 */ {22001, xed3_phash_find_mapevex_map1_opcode0x79_vv2_544_l1}, +/*h(15846)=545 */ {15846, xed3_phash_find_mapevex_map1_opcode0x79_vv2_545_l1}, +/*h(5510)=546 */ {5510, xed3_phash_find_mapevex_map1_opcode0x79_vv2_546_l1}, +/*h(4523)=547 */ {4523, xed3_phash_find_mapevex_map1_opcode0x79_vv2_547_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26038)=549 */ {26038, xed3_phash_find_mapevex_map1_opcode0x79_vv2_549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17909)=551 */ {17909, xed3_phash_find_mapevex_map1_opcode0x79_vv2_551_l1}, +/*h(11754)=552 */ {11754, xed3_phash_find_mapevex_map1_opcode0x79_vv2_552_l1}, +/*h(1418)=553 */ {1418, xed3_phash_find_mapevex_map1_opcode0x79_vv2_553_l1}, +/*h(431)=554 */ {431, xed3_phash_find_mapevex_map1_opcode0x79_vv2_554_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16778)=556 */ {16778, xed3_phash_find_mapevex_map1_opcode0x79_vv2_556_l1}, +/*h(15791)=557 */ {15791, xed3_phash_find_mapevex_map1_opcode0x79_vv2_557_l1}, +/*h(9636)=558 */ {9636, xed3_phash_find_mapevex_map1_opcode0x79_vv2_558_l1}, +/*h(8649)=559 */ {8649, xed3_phash_find_mapevex_map1_opcode0x79_vv2_559_l1}, +/*h(7662)=560 */ {7662, xed3_phash_find_mapevex_map1_opcode0x79_vv2_560_l1}, +/*h(1507)=561 */ {1507, xed3_phash_find_mapevex_map1_opcode0x79_vv2_561_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16867)=564 */ {16867, xed3_phash_find_mapevex_map1_opcode0x79_vv2_564_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5544)=566 */ {5544, xed3_phash_find_mapevex_map1_opcode0x79_vv2_566_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21891)=568 */ {21891, xed3_phash_find_mapevex_map1_opcode0x79_vv2_568_l1}, +/*h(20904)=569 */ {20904, xed3_phash_find_mapevex_map1_opcode0x79_vv2_569_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8594)=571 */ {8594, xed3_phash_find_mapevex_map1_opcode0x79_vv2_571_l1}, +/*h(2439)=572 */ {2439, xed3_phash_find_mapevex_map1_opcode0x79_vv2_572_l1}, +/*h(1452)=573 */ {1452, xed3_phash_find_mapevex_map1_opcode0x79_vv2_573_l1}, +/*h(465)=574 */ {465, xed3_phash_find_mapevex_map1_opcode0x79_vv2_574_l1}, +/*h(17799)=575 */ {17799, xed3_phash_find_mapevex_map1_opcode0x79_vv2_575_l1}, +/*h(16812)=576 */ {16812, xed3_phash_find_mapevex_map1_opcode0x79_vv2_576_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9670)=578 */ {9670, xed3_phash_find_mapevex_map1_opcode0x79_vv2_578_l1}, +/*h(8683)=579 */ {8683, xed3_phash_find_mapevex_map1_opcode0x79_vv2_579_l1}, +/*h(26017)=580 */ {26017, xed3_phash_find_mapevex_map1_opcode0x79_vv2_580_l1}, +/*h(25030)=581 */ {25030, xed3_phash_find_mapevex_map1_opcode0x79_vv2_581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17888)=583 */ {17888, xed3_phash_find_mapevex_map1_opcode0x79_vv2_583_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5578)=585 */ {5578, xed3_phash_find_mapevex_map1_opcode0x79_vv2_585_l1}, +/*h(4591)=586 */ {4591, xed3_phash_find_mapevex_map1_opcode0x79_vv2_586_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21925)=588 */ {21925, xed3_phash_find_mapevex_map1_opcode0x79_vv2_588_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9615)=590 */ {9615, xed3_phash_find_mapevex_map1_opcode0x79_vv2_590_l1}, +/*h(8628)=591 */ {8628, xed3_phash_find_mapevex_map1_opcode0x79_vv2_591_l1}, +/*h(1486)=592 */ {1486, xed3_phash_find_mapevex_map1_opcode0x79_vv2_592_l1}, +/*h(24975)=593 */ {24975, xed3_phash_find_mapevex_map1_opcode0x79_vv2_593_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17833)=595 */ {17833, xed3_phash_find_mapevex_map1_opcode0x79_vv2_595_l1}, +/*h(16846)=596 */ {16846, xed3_phash_find_mapevex_map1_opcode0x79_vv2_596_l1}, +/*h(5523)=597 */ {5523, xed3_phash_find_mapevex_map1_opcode0x79_vv2_597_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26051)=600 */ {26051, xed3_phash_find_mapevex_map1_opcode0x79_vv2_600_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13741)=602 */ {13741, xed3_phash_find_mapevex_map1_opcode0x79_vv2_602_l1}, +/*h(7586)=603 */ {7586, xed3_phash_find_mapevex_map1_opcode0x79_vv2_603_l1}, +/*h(6599)=604 */ {6599, xed3_phash_find_mapevex_map1_opcode0x79_vv2_604_l1}, +/*h(1431)=605 */ {1431, xed3_phash_find_mapevex_map1_opcode0x79_vv2_605_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21959)=607 */ {21959, xed3_phash_find_mapevex_map1_opcode0x79_vv2_607_l1}, +/*h(16791)=608 */ {16791, xed3_phash_find_mapevex_map1_opcode0x79_vv2_608_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9649)=610 */ {9649, xed3_phash_find_mapevex_map1_opcode0x79_vv2_610_l1}, +/*h(3494)=611 */ {3494, xed3_phash_find_mapevex_map1_opcode0x79_vv2_611_l1}, +/*h(25996)=612 */ {25996, xed3_phash_find_mapevex_map1_opcode0x79_vv2_612_l1}, +/*h(25009)=613 */ {25009, xed3_phash_find_mapevex_map1_opcode0x79_vv2_613_l1}, +/*h(17867)=614 */ {17867, xed3_phash_find_mapevex_map1_opcode0x79_vv2_614_l1}, +/*h(16880)=615 */ {16880, xed3_phash_find_mapevex_map1_opcode0x79_vv2_615_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5557)=617 */ {5557, xed3_phash_find_mapevex_map1_opcode0x79_vv2_617_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21904)=619 */ {21904, xed3_phash_find_mapevex_map1_opcode0x79_vv2_619_l1}, +/*h(20917)=620 */ {20917, xed3_phash_find_mapevex_map1_opcode0x79_vv2_620_l1}, +/*h(14762)=621 */ {14762, xed3_phash_find_mapevex_map1_opcode0x79_vv2_621_l1}, +/*h(13775)=622 */ {13775, xed3_phash_find_mapevex_map1_opcode0x79_vv2_622_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(29135)=625 */ {29135, xed3_phash_find_mapevex_map1_opcode0x79_vv2_625_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17812)=627 */ {17812, xed3_phash_find_mapevex_map1_opcode0x79_vv2_627_l1}, +/*h(10670)=628 */ {10670, xed3_phash_find_mapevex_map1_opcode0x79_vv2_628_l1}, +/*h(9683)=629 */ {9683, xed3_phash_find_mapevex_map1_opcode0x79_vv2_629_l1}, +/*h(4515)=630 */ {4515, xed3_phash_find_mapevex_map1_opcode0x79_vv2_630_l1}, +/*h(26030)=631 */ {26030, xed3_phash_find_mapevex_map1_opcode0x79_vv2_631_l1}, +/*h(25043)=632 */ {25043, xed3_phash_find_mapevex_map1_opcode0x79_vv2_632_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17901)=634 */ {17901, xed3_phash_find_mapevex_map1_opcode0x79_vv2_634_l1}, +/*h(11746)=635 */ {11746, xed3_phash_find_mapevex_map1_opcode0x79_vv2_635_l1}, +/*h(1410)=636 */ {1410, xed3_phash_find_mapevex_map1_opcode0x79_vv2_636_l1}, +/*h(423)=637 */ {423, xed3_phash_find_mapevex_map1_opcode0x79_vv2_637_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21938)=639 */ {21938, xed3_phash_find_mapevex_map1_opcode0x79_vv2_639_l1}, +/*h(15783)=640 */ {15783, xed3_phash_find_mapevex_map1_opcode0x79_vv2_640_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8641)=642 */ {8641, xed3_phash_find_mapevex_map1_opcode0x79_vv2_642_l1}, +/*h(7654)=643 */ {7654, xed3_phash_find_mapevex_map1_opcode0x79_vv2_643_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17846)=646 */ {17846, xed3_phash_find_mapevex_map1_opcode0x79_vv2_646_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5536)=649 */ {5536, xed3_phash_find_mapevex_map1_opcode0x79_vv2_649_l1}, +/*h(3562)=650 */ {3562, xed3_phash_find_mapevex_map1_opcode0x79_vv2_650_l1}, +/*h(26064)=651 */ {26064, xed3_phash_find_mapevex_map1_opcode0x79_vv2_651_l1}, +/*h(20896)=652 */ {20896, xed3_phash_find_mapevex_map1_opcode0x79_vv2_652_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8586)=654 */ {8586, xed3_phash_find_mapevex_map1_opcode0x79_vv2_654_l1}, +/*h(7599)=655 */ {7599, xed3_phash_find_mapevex_map1_opcode0x79_vv2_655_l1}, +/*h(30101)=656 */ {30101, xed3_phash_find_mapevex_map1_opcode0x79_vv2_656_l1}, +/*h(457)=657 */ {457, xed3_phash_find_mapevex_map1_opcode0x79_vv2_657_l1}, +/*h(21972)=658 */ {21972, xed3_phash_find_mapevex_map1_opcode0x79_vv2_658_l1}, +/*h(16804)=659 */ {16804, xed3_phash_find_mapevex_map1_opcode0x79_vv2_659_l1}, +/*h(14830)=660 */ {14830, xed3_phash_find_mapevex_map1_opcode0x79_vv2_660_l1}, +/*h(4494)=661 */ {4494, xed3_phash_find_mapevex_map1_opcode0x79_vv2_661_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5570)=668 */ {5570, xed3_phash_find_mapevex_map1_opcode0x79_vv2_668_l1}, +/*h(402)=669 */ {402, xed3_phash_find_mapevex_map1_opcode0x79_vv2_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26098)=671 */ {26098, xed3_phash_find_mapevex_map1_opcode0x79_vv2_671_l1}, +/*h(15762)=672 */ {15762, xed3_phash_find_mapevex_map1_opcode0x79_vv2_672_l1}, +/*h(9607)=673 */ {9607, xed3_phash_find_mapevex_map1_opcode0x79_vv2_673_l1}, +/*h(8620)=674 */ {8620, xed3_phash_find_mapevex_map1_opcode0x79_vv2_674_l1}, +/*h(30135)=675 */ {30135, xed3_phash_find_mapevex_map1_opcode0x79_vv2_675_l1}, +/*h(24967)=676 */ {24967, xed3_phash_find_mapevex_map1_opcode0x79_vv2_676_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17825)=678 */ {17825, xed3_phash_find_mapevex_map1_opcode0x79_vv2_678_l1}, +/*h(11670)=679 */ {11670, xed3_phash_find_mapevex_map1_opcode0x79_vv2_679_l1}, +/*h(5515)=680 */ {5515, xed3_phash_find_mapevex_map1_opcode0x79_vv2_680_l1}, +/*h(4528)=681 */ {4528, xed3_phash_find_mapevex_map1_opcode0x79_vv2_681_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20875)=683 */ {20875, xed3_phash_find_mapevex_map1_opcode0x79_vv2_683_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13733)=685 */ {13733, xed3_phash_find_mapevex_map1_opcode0x79_vv2_685_l1}, +/*h(11759)=686 */ {11759, xed3_phash_find_mapevex_map1_opcode0x79_vv2_686_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1423)=688 */ {1423, xed3_phash_find_mapevex_map1_opcode0x79_vv2_688_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16783)=691 */ {16783, xed3_phash_find_mapevex_map1_opcode0x79_vv2_691_l1}, +/*h(9641)=692 */ {9641, xed3_phash_find_mapevex_map1_opcode0x79_vv2_692_l1}, +/*h(8654)=693 */ {8654, xed3_phash_find_mapevex_map1_opcode0x79_vv2_693_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25988)=695 */ {25988, xed3_phash_find_mapevex_map1_opcode0x79_vv2_695_l1}, +/*h(25001)=696 */ {25001, xed3_phash_find_mapevex_map1_opcode0x79_vv2_696_l1}, +/*h(17859)=697 */ {17859, xed3_phash_find_mapevex_map1_opcode0x79_vv2_697_l1}, +/*h(16872)=698 */ {16872, xed3_phash_find_mapevex_map1_opcode0x79_vv2_698_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5549)=700 */ {5549, xed3_phash_find_mapevex_map1_opcode0x79_vv2_700_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21896)=702 */ {21896, xed3_phash_find_mapevex_map1_opcode0x79_vv2_702_l1}, +/*h(20909)=703 */ {20909, xed3_phash_find_mapevex_map1_opcode0x79_vv2_703_l1}, +/*h(14754)=704 */ {14754, xed3_phash_find_mapevex_map1_opcode0x79_vv2_704_l1}, +/*h(13767)=705 */ {13767, xed3_phash_find_mapevex_map1_opcode0x79_vv2_705_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1457)=707 */ {1457, xed3_phash_find_mapevex_map1_opcode0x79_vv2_707_l1}, +/*h(470)=708 */ {470, xed3_phash_find_mapevex_map1_opcode0x79_vv2_708_l1}, +/*h(17804)=709 */ {17804, xed3_phash_find_mapevex_map1_opcode0x79_vv2_709_l1}, +/*h(21985)=710 */ {21985, xed3_phash_find_mapevex_map1_opcode0x79_vv2_710_l1}, +/*h(15830)=711 */ {15830, xed3_phash_find_mapevex_map1_opcode0x79_vv2_711_l1}, +/*h(9675)=712 */ {9675, xed3_phash_find_mapevex_map1_opcode0x79_vv2_712_l1}, +/*h(8688)=713 */ {8688, xed3_phash_find_mapevex_map1_opcode0x79_vv2_713_l1}, +/*h(26022)=714 */ {26022, xed3_phash_find_mapevex_map1_opcode0x79_vv2_714_l1}, +/*h(25035)=715 */ {25035, xed3_phash_find_mapevex_map1_opcode0x79_vv2_715_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17893)=717 */ {17893, xed3_phash_find_mapevex_map1_opcode0x79_vv2_717_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5583)=719 */ {5583, xed3_phash_find_mapevex_map1_opcode0x79_vv2_719_l1}, +/*h(4596)=720 */ {4596, xed3_phash_find_mapevex_map1_opcode0x79_vv2_720_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21930)=722 */ {21930, xed3_phash_find_mapevex_map1_opcode0x79_vv2_722_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9620)=724 */ {9620, xed3_phash_find_mapevex_map1_opcode0x79_vv2_724_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2478)=726 */ {2478, xed3_phash_find_mapevex_map1_opcode0x79_vv2_726_l1}, +/*h(1491)=727 */ {1491, xed3_phash_find_mapevex_map1_opcode0x79_vv2_727_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17838)=729 */ {17838, xed3_phash_find_mapevex_map1_opcode0x79_vv2_729_l1}, +/*h(16851)=730 */ {16851, xed3_phash_find_mapevex_map1_opcode0x79_vv2_730_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9709)=732 */ {9709, xed3_phash_find_mapevex_map1_opcode0x79_vv2_732_l1}, +/*h(3554)=733 */ {3554, xed3_phash_find_mapevex_map1_opcode0x79_vv2_733_l1}, +/*h(26056)=734 */ {26056, xed3_phash_find_mapevex_map1_opcode0x79_vv2_734_l1}, +/*h(25069)=735 */ {25069, xed3_phash_find_mapevex_map1_opcode0x79_vv2_735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8578)=737 */ {8578, xed3_phash_find_mapevex_map1_opcode0x79_vv2_737_l1}, +/*h(7591)=738 */ {7591, xed3_phash_find_mapevex_map1_opcode0x79_vv2_738_l1}, +/*h(30093)=739 */ {30093, xed3_phash_find_mapevex_map1_opcode0x79_vv2_739_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21964)=741 */ {21964, xed3_phash_find_mapevex_map1_opcode0x79_vv2_741_l1}, +/*h(20977)=742 */ {20977, xed3_phash_find_mapevex_map1_opcode0x79_vv2_742_l1}, +/*h(14822)=743 */ {14822, xed3_phash_find_mapevex_map1_opcode0x79_vv2_743_l1}, +/*h(9654)=744 */ {9654, xed3_phash_find_mapevex_map1_opcode0x79_vv2_744_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26001)=746 */ {26001, xed3_phash_find_mapevex_map1_opcode0x79_vv2_746_l1}, +/*h(25014)=747 */ {25014, xed3_phash_find_mapevex_map1_opcode0x79_vv2_747_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17872)=749 */ {17872, xed3_phash_find_mapevex_map1_opcode0x79_vv2_749_l1}, +/*h(10730)=750 */ {10730, xed3_phash_find_mapevex_map1_opcode0x79_vv2_750_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(394)=752 */ {394, xed3_phash_find_mapevex_map1_opcode0x79_vv2_752_l1}, +/*h(21909)=753 */ {21909, xed3_phash_find_mapevex_map1_opcode0x79_vv2_753_l1}, +/*h(26090)=754 */ {26090, xed3_phash_find_mapevex_map1_opcode0x79_vv2_754_l1}, +/*h(15754)=755 */ {15754, xed3_phash_find_mapevex_map1_opcode0x79_vv2_755_l1}, +/*h(8612)=756 */ {8612, xed3_phash_find_mapevex_map1_opcode0x79_vv2_756_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30127)=758 */ {30127, xed3_phash_find_mapevex_map1_opcode0x79_vv2_758_l1}, +/*h(483)=759 */ {483, xed3_phash_find_mapevex_map1_opcode0x79_vv2_759_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21998)=761 */ {21998, xed3_phash_find_mapevex_map1_opcode0x79_vv2_761_l1}, +/*h(11662)=762 */ {11662, xed3_phash_find_mapevex_map1_opcode0x79_vv2_762_l1}, +/*h(5507)=763 */ {5507, xed3_phash_find_mapevex_map1_opcode0x79_vv2_763_l1}, +/*h(4520)=764 */ {4520, xed3_phash_find_mapevex_map1_opcode0x79_vv2_764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26035)=766 */ {26035, xed3_phash_find_mapevex_map1_opcode0x79_vv2_766_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17906)=768 */ {17906, xed3_phash_find_mapevex_map1_opcode0x79_vv2_768_l1}, +/*h(7570)=769 */ {7570, xed3_phash_find_mapevex_map1_opcode0x79_vv2_769_l1}, +/*h(1415)=770 */ {1415, xed3_phash_find_mapevex_map1_opcode0x79_vv2_770_l1}, +/*h(428)=771 */ {428, xed3_phash_find_mapevex_map1_opcode0x79_vv2_771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21943)=773 */ {21943, xed3_phash_find_mapevex_map1_opcode0x79_vv2_773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9633)=775 */ {9633, xed3_phash_find_mapevex_map1_opcode0x79_vv2_775_l1}, +/*h(8646)=776 */ {8646, xed3_phash_find_mapevex_map1_opcode0x79_vv2_776_l1}, +/*h(3478)=777 */ {3478, xed3_phash_find_mapevex_map1_opcode0x79_vv2_777_l1}, +/*h(1504)=778 */ {1504, xed3_phash_find_mapevex_map1_opcode0x79_vv2_778_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16864)=781 */ {16864, xed3_phash_find_mapevex_map1_opcode0x79_vv2_781_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5541)=783 */ {5541, xed3_phash_find_mapevex_map1_opcode0x79_vv2_783_l1}, +/*h(3567)=784 */ {3567, xed3_phash_find_mapevex_map1_opcode0x79_vv2_784_l1}, +/*h(21888)=785 */ {21888, xed3_phash_find_mapevex_map1_opcode0x79_vv2_785_l1}, +/*h(20901)=786 */ {20901, xed3_phash_find_mapevex_map1_opcode0x79_vv2_786_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8591)=788 */ {8591, xed3_phash_find_mapevex_map1_opcode0x79_vv2_788_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1449)=790 */ {1449, xed3_phash_find_mapevex_map1_opcode0x79_vv2_790_l1}, +/*h(462)=791 */ {462, xed3_phash_find_mapevex_map1_opcode0x79_vv2_791_l1}, +/*h(17796)=792 */ {17796, xed3_phash_find_mapevex_map1_opcode0x79_vv2_792_l1}, +/*h(16809)=793 */ {16809, xed3_phash_find_mapevex_map1_opcode0x79_vv2_793_l1}, +/*h(15822)=794 */ {15822, xed3_phash_find_mapevex_map1_opcode0x79_vv2_794_l1}, +/*h(9667)=795 */ {9667, xed3_phash_find_mapevex_map1_opcode0x79_vv2_795_l1}, +/*h(8680)=796 */ {8680, xed3_phash_find_mapevex_map1_opcode0x79_vv2_796_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25027)=798 */ {25027, xed3_phash_find_mapevex_map1_opcode0x79_vv2_798_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12717)=800 */ {12717, xed3_phash_find_mapevex_map1_opcode0x79_vv2_800_l1}, +/*h(11730)=801 */ {11730, xed3_phash_find_mapevex_map1_opcode0x79_vv2_801_l1}, +/*h(5575)=802 */ {5575, xed3_phash_find_mapevex_map1_opcode0x79_vv2_802_l1}, +/*h(407)=803 */ {407, xed3_phash_find_mapevex_map1_opcode0x79_vv2_803_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21922)=805 */ {21922, xed3_phash_find_mapevex_map1_opcode0x79_vv2_805_l1}, +/*h(15767)=806 */ {15767, xed3_phash_find_mapevex_map1_opcode0x79_vv2_806_l1}, +/*h(9612)=807 */ {9612, xed3_phash_find_mapevex_map1_opcode0x79_vv2_807_l1}, +/*h(7638)=808 */ {7638, xed3_phash_find_mapevex_map1_opcode0x79_vv2_808_l1}, +/*h(2470)=809 */ {2470, xed3_phash_find_mapevex_map1_opcode0x79_vv2_809_l1}, +/*h(1483)=810 */ {1483, xed3_phash_find_mapevex_map1_opcode0x79_vv2_810_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17830)=812 */ {17830, xed3_phash_find_mapevex_map1_opcode0x79_vv2_812_l1}, +/*h(16843)=813 */ {16843, xed3_phash_find_mapevex_map1_opcode0x79_vv2_813_l1}, +/*h(5520)=814 */ {5520, xed3_phash_find_mapevex_map1_opcode0x79_vv2_814_l1}, +/*h(9701)=815 */ {9701, xed3_phash_find_mapevex_map1_opcode0x79_vv2_815_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26048)=817 */ {26048, xed3_phash_find_mapevex_map1_opcode0x79_vv2_817_l1}, +/*h(25061)=818 */ {25061, xed3_phash_find_mapevex_map1_opcode0x79_vv2_818_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12751)=820 */ {12751, xed3_phash_find_mapevex_map1_opcode0x79_vv2_820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30085)=822 */ {30085, xed3_phash_find_mapevex_map1_opcode0x79_vv2_822_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21956)=824 */ {21956, xed3_phash_find_mapevex_map1_opcode0x79_vv2_824_l1}, +/*h(16788)=825 */ {16788, xed3_phash_find_mapevex_map1_opcode0x79_vv2_825_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9646)=827 */ {9646, xed3_phash_find_mapevex_map1_opcode0x79_vv2_827_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25993)=829 */ {25993, xed3_phash_find_mapevex_map1_opcode0x79_vv2_829_l1}, +/*h(25006)=830 */ {25006, xed3_phash_find_mapevex_map1_opcode0x79_vv2_830_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17864)=832 */ {17864, xed3_phash_find_mapevex_map1_opcode0x79_vv2_832_l1}, +/*h(10722)=833 */ {10722, xed3_phash_find_mapevex_map1_opcode0x79_vv2_833_l1}, +/*h(5554)=834 */ {5554, xed3_phash_find_mapevex_map1_opcode0x79_vv2_834_l1}, +/*h(4567)=835 */ {4567, xed3_phash_find_mapevex_map1_opcode0x79_vv2_835_l1}, +/*h(21901)=836 */ {21901, xed3_phash_find_mapevex_map1_opcode0x79_vv2_836_l1}, +/*h(20914)=837 */ {20914, xed3_phash_find_mapevex_map1_opcode0x79_vv2_837_l1}, +/*h(15746)=838 */ {15746, xed3_phash_find_mapevex_map1_opcode0x79_vv2_838_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30119)=841 */ {30119, xed3_phash_find_mapevex_map1_opcode0x79_vv2_841_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17809)=844 */ {17809, xed3_phash_find_mapevex_map1_opcode0x79_vv2_844_l1}, +/*h(11654)=845 */ {11654, xed3_phash_find_mapevex_map1_opcode0x79_vv2_845_l1}, +/*h(9680)=846 */ {9680, xed3_phash_find_mapevex_map1_opcode0x79_vv2_846_l1}, +/*h(4512)=847 */ {4512, xed3_phash_find_mapevex_map1_opcode0x79_vv2_847_l1}, +/*h(2538)=848 */ {2538, xed3_phash_find_mapevex_map1_opcode0x79_vv2_848_l1}, +/*h(26027)=849 */ {26027, xed3_phash_find_mapevex_map1_opcode0x79_vv2_849_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13717)=851 */ {13717, xed3_phash_find_mapevex_map1_opcode0x79_vv2_851_l1}, +/*h(7562)=852 */ {7562, xed3_phash_find_mapevex_map1_opcode0x79_vv2_852_l1}, +/*h(6575)=853 */ {6575, xed3_phash_find_mapevex_map1_opcode0x79_vv2_853_l1}, +/*h(5588)=854 */ {5588, xed3_phash_find_mapevex_map1_opcode0x79_vv2_854_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21935)=856 */ {21935, xed3_phash_find_mapevex_map1_opcode0x79_vv2_856_l1}, +/*h(20948)=857 */ {20948, xed3_phash_find_mapevex_map1_opcode0x79_vv2_857_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3470)=859 */ {3470, xed3_phash_find_mapevex_map1_opcode0x79_vv2_859_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17843)=863 */ {17843, xed3_phash_find_mapevex_map1_opcode0x79_vv2_863_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9714)=866 */ {9714, xed3_phash_find_mapevex_map1_opcode0x79_vv2_866_l1}, +/*h(3559)=867 */ {3559, xed3_phash_find_mapevex_map1_opcode0x79_vv2_867_l1}, +/*h(26061)=868 */ {26061, xed3_phash_find_mapevex_map1_opcode0x79_vv2_868_l1}, +/*h(25074)=869 */ {25074, xed3_phash_find_mapevex_map1_opcode0x79_vv2_869_l1}, +/*h(14738)=870 */ {14738, xed3_phash_find_mapevex_map1_opcode0x79_vv2_870_l1}, +/*h(13751)=871 */ {13751, xed3_phash_find_mapevex_map1_opcode0x79_vv2_871_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1441)=873 */ {1441, xed3_phash_find_mapevex_map1_opcode0x79_vv2_873_l1}, +/*h(29111)=874 */ {29111, xed3_phash_find_mapevex_map1_opcode0x79_vv2_874_l1}, +/*h(21969)=875 */ {21969, xed3_phash_find_mapevex_map1_opcode0x79_vv2_875_l1}, +/*h(16801)=876 */ {16801, xed3_phash_find_mapevex_map1_opcode0x79_vv2_876_l1}, +/*h(15814)=877 */ {15814, xed3_phash_find_mapevex_map1_opcode0x79_vv2_877_l1}, +/*h(4491)=878 */ {4491, xed3_phash_find_mapevex_map1_opcode0x79_vv2_878_l1}, +/*h(8672)=879 */ {8672, xed3_phash_find_mapevex_map1_opcode0x79_vv2_879_l1}, +/*h(26006)=880 */ {26006, xed3_phash_find_mapevex_map1_opcode0x79_vv2_880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17877)=883 */ {17877, xed3_phash_find_mapevex_map1_opcode0x79_vv2_883_l1}, +/*h(11722)=884 */ {11722, xed3_phash_find_mapevex_map1_opcode0x79_vv2_884_l1}, +/*h(10735)=885 */ {10735, xed3_phash_find_mapevex_map1_opcode0x79_vv2_885_l1}, +/*h(399)=886 */ {399, xed3_phash_find_mapevex_map1_opcode0x79_vv2_886_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26095)=888 */ {26095, xed3_phash_find_mapevex_map1_opcode0x79_vv2_888_l1}, +/*h(15759)=889 */ {15759, xed3_phash_find_mapevex_map1_opcode0x79_vv2_889_l1}, +/*h(9604)=890 */ {9604, xed3_phash_find_mapevex_map1_opcode0x79_vv2_890_l1}, +/*h(7630)=891 */ {7630, xed3_phash_find_mapevex_map1_opcode0x79_vv2_891_l1}, +/*h(1475)=892 */ {1475, xed3_phash_find_mapevex_map1_opcode0x79_vv2_892_l1}, +/*h(24964)=893 */ {24964, xed3_phash_find_mapevex_map1_opcode0x79_vv2_893_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22003)=895 */ {22003, xed3_phash_find_mapevex_map1_opcode0x79_vv2_895_l1}, +/*h(16835)=896 */ {16835, xed3_phash_find_mapevex_map1_opcode0x79_vv2_896_l1}, +/*h(5512)=897 */ {5512, xed3_phash_find_mapevex_map1_opcode0x79_vv2_897_l1}, +/*h(4525)=898 */ {4525, xed3_phash_find_mapevex_map1_opcode0x79_vv2_898_l1}, +/*h(3538)=899 */ {3538, xed3_phash_find_mapevex_map1_opcode0x79_vv2_899_l1}, +/*h(20872)=900 */ {20872, xed3_phash_find_mapevex_map1_opcode0x79_vv2_900_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17911)=902 */ {17911, xed3_phash_find_mapevex_map1_opcode0x79_vv2_902_l1}, +/*h(7575)=903 */ {7575, xed3_phash_find_mapevex_map1_opcode0x79_vv2_903_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1420)=905 */ {1420, xed3_phash_find_mapevex_map1_opcode0x79_vv2_905_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16780)=908 */ {16780, xed3_phash_find_mapevex_map1_opcode0x79_vv2_908_l1}, +/*h(14806)=909 */ {14806, xed3_phash_find_mapevex_map1_opcode0x79_vv2_909_l1}, +/*h(9638)=910 */ {9638, xed3_phash_find_mapevex_map1_opcode0x79_vv2_910_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25985)=912 */ {25985, xed3_phash_find_mapevex_map1_opcode0x79_vv2_912_l1}, +/*h(24998)=913 */ {24998, xed3_phash_find_mapevex_map1_opcode0x79_vv2_913_l1}, +/*h(17856)=914 */ {17856, xed3_phash_find_mapevex_map1_opcode0x79_vv2_914_l1}, +/*h(16869)=915 */ {16869, xed3_phash_find_mapevex_map1_opcode0x79_vv2_915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5546)=917 */ {5546, xed3_phash_find_mapevex_map1_opcode0x79_vv2_917_l1}, +/*h(4559)=918 */ {4559, xed3_phash_find_mapevex_map1_opcode0x79_vv2_918_l1}, +/*h(21893)=919 */ {21893, xed3_phash_find_mapevex_map1_opcode0x79_vv2_919_l1}, +/*h(20906)=920 */ {20906, xed3_phash_find_mapevex_map1_opcode0x79_vv2_920_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8596)=922 */ {8596, xed3_phash_find_mapevex_map1_opcode0x79_vv2_922_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1454)=924 */ {1454, xed3_phash_find_mapevex_map1_opcode0x79_vv2_924_l1}, +/*h(467)=925 */ {467, xed3_phash_find_mapevex_map1_opcode0x79_vv2_925_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17801)=927 */ {17801, xed3_phash_find_mapevex_map1_opcode0x79_vv2_927_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9672)=929 */ {9672, xed3_phash_find_mapevex_map1_opcode0x79_vv2_929_l1}, +/*h(8685)=930 */ {8685, xed3_phash_find_mapevex_map1_opcode0x79_vv2_930_l1}, +/*h(2530)=931 */ {2530, xed3_phash_find_mapevex_map1_opcode0x79_vv2_931_l1}, +/*h(26019)=932 */ {26019, xed3_phash_find_mapevex_map1_opcode0x79_vv2_932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13709)=934 */ {13709, xed3_phash_find_mapevex_map1_opcode0x79_vv2_934_l1}, +/*h(11735)=935 */ {11735, xed3_phash_find_mapevex_map1_opcode0x79_vv2_935_l1}, +/*h(5580)=936 */ {5580, xed3_phash_find_mapevex_map1_opcode0x79_vv2_936_l1}, +/*h(29069)=937 */ {29069, xed3_phash_find_mapevex_map1_opcode0x79_vv2_937_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21927)=939 */ {21927, xed3_phash_find_mapevex_map1_opcode0x79_vv2_939_l1}, +/*h(20940)=940 */ {20940, xed3_phash_find_mapevex_map1_opcode0x79_vv2_940_l1}, +/*h(9617)=941 */ {9617, xed3_phash_find_mapevex_map1_opcode0x79_vv2_941_l1}, +/*h(3462)=942 */ {3462, xed3_phash_find_mapevex_map1_opcode0x79_vv2_942_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1488)=944 */ {1488, xed3_phash_find_mapevex_map1_opcode0x79_vv2_944_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17835)=946 */ {17835, xed3_phash_find_mapevex_map1_opcode0x79_vv2_946_l1}, +/*h(16848)=947 */ {16848, xed3_phash_find_mapevex_map1_opcode0x79_vv2_947_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5525)=949 */ {5525, xed3_phash_find_mapevex_map1_opcode0x79_vv2_949_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26053)=951 */ {26053, xed3_phash_find_mapevex_map1_opcode0x79_vv2_951_l1}, +/*h(20885)=952 */ {20885, xed3_phash_find_mapevex_map1_opcode0x79_vv2_952_l1}, +/*h(13743)=953 */ {13743, xed3_phash_find_mapevex_map1_opcode0x79_vv2_953_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5614)=956 */ {5614, xed3_phash_find_mapevex_map1_opcode0x79_vv2_956_l1}, +/*h(29103)=957 */ {29103, xed3_phash_find_mapevex_map1_opcode0x79_vv2_957_l1}, +/*h(21961)=958 */ {21961, xed3_phash_find_mapevex_map1_opcode0x79_vv2_958_l1}, +/*h(20974)=959 */ {20974, xed3_phash_find_mapevex_map1_opcode0x79_vv2_959_l1}, +/*h(10638)=960 */ {10638, xed3_phash_find_mapevex_map1_opcode0x79_vv2_960_l1}, +/*h(9651)=961 */ {9651, xed3_phash_find_mapevex_map1_opcode0x79_vv2_961_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25998)=963 */ {25998, xed3_phash_find_mapevex_map1_opcode0x79_vv2_963_l1}, +/*h(25011)=964 */ {25011, xed3_phash_find_mapevex_map1_opcode0x79_vv2_964_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17869)=966 */ {17869, xed3_phash_find_mapevex_map1_opcode0x79_vv2_966_l1}, +/*h(11714)=967 */ {11714, xed3_phash_find_mapevex_map1_opcode0x79_vv2_967_l1}, +/*h(5559)=968 */ {5559, xed3_phash_find_mapevex_map1_opcode0x79_vv2_968_l1}, +/*h(391)=969 */ {391, xed3_phash_find_mapevex_map1_opcode0x79_vv2_969_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21906)=971 */ {21906, xed3_phash_find_mapevex_map1_opcode0x79_vv2_971_l1}, +/*h(15751)=972 */ {15751, xed3_phash_find_mapevex_map1_opcode0x79_vv2_972_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7622)=974 */ {7622, xed3_phash_find_mapevex_map1_opcode0x79_vv2_974_l1}, +/*h(2454)=975 */ {2454, xed3_phash_find_mapevex_map1_opcode0x79_vv2_975_l1}, +/*h(480)=976 */ {480, xed3_phash_find_mapevex_map1_opcode0x79_vv2_976_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17814)=978 */ {17814, xed3_phash_find_mapevex_map1_opcode0x79_vv2_978_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5504)=980 */ {5504, xed3_phash_find_mapevex_map1_opcode0x79_vv2_980_l1}, +/*h(4517)=981 */ {4517, xed3_phash_find_mapevex_map1_opcode0x79_vv2_981_l1}, +/*h(3530)=982 */ {3530, xed3_phash_find_mapevex_map1_opcode0x79_vv2_982_l1}, +/*h(26032)=983 */ {26032, xed3_phash_find_mapevex_map1_opcode0x79_vv2_983_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17903)=985 */ {17903, xed3_phash_find_mapevex_map1_opcode0x79_vv2_985_l1}, +/*h(7567)=986 */ {7567, xed3_phash_find_mapevex_map1_opcode0x79_vv2_986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1412)=988 */ {1412, xed3_phash_find_mapevex_map1_opcode0x79_vv2_988_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21940)=990 */ {21940, xed3_phash_find_mapevex_map1_opcode0x79_vv2_990_l1}, +/*h(16772)=991 */ {16772, xed3_phash_find_mapevex_map1_opcode0x79_vv2_991_l1}, +/*h(14798)=992 */ {14798, xed3_phash_find_mapevex_map1_opcode0x79_vv2_992_l1}, +/*h(8643)=993 */ {8643, xed3_phash_find_mapevex_map1_opcode0x79_vv2_993_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10706)=999 */ {10706, xed3_phash_find_mapevex_map1_opcode0x79_vv2_999_l1}, +/*h(5538)=1000 */ {5538, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1000_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26066)=1002 */ {26066, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1002_l1}, +/*h(20898)=1003 */ {20898, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1003_l1}, +/*h(14743)=1004 */ {14743, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1004_l1}, +/*h(8588)=1005 */ {8588, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1005_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30103)=1007 */ {30103, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1007_l1}, +/*h(459)=1008 */ {459, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1008_l1}, +/*h(17793)=1009 */ {17793, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1009_l1}, +/*h(21974)=1010 */ {21974, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1010_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9664)=1012 */ {9664, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1012_l1}, +/*h(4496)=1013 */ {4496, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1013_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25024)=1015 */ {25024, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1015_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13701)=1017 */ {13701, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1017_l1}, +/*h(11727)=1018 */ {11727, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1018_l1}, +/*h(5572)=1019 */ {5572, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1019_l1}, +/*h(404)=1020 */ {404, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1020_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26100)=1022 */ {26100, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1022_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9609)=1024 */ {9609, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1024_l1}, +/*h(8622)=1025 */ {8622, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1025_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1480)=1027 */ {1480, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17827)=1029 */ {17827, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1029_l1}, +/*h(16840)=1030 */ {16840, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1030_l1}, +/*h(5517)=1031 */ {5517, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1031_l1}, +/*h(9698)=1032 */ {9698, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1032_l1}, +/*h(3543)=1033 */ {3543, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1033_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20877)=1035 */ {20877, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1035_l1}, +/*h(13735)=1036 */ {13735, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1036_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1425)=1039 */ {1425, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1039_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21953)=1041 */ {21953, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1041_l1}, +/*h(16785)=1042 */ {16785, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1042_l1}, +/*h(10630)=1043 */ {10630, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1043_l1}, +/*h(9643)=1044 */ {9643, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1044_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25990)=1046 */ {25990, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1046_l1}, +/*h(25003)=1047 */ {25003, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17861)=1049 */ {17861, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1049_l1}, +/*h(6538)=1050 */ {6538, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1050_l1}, +/*h(5551)=1051 */ {5551, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1051_l1}, +/*h(4564)=1052 */ {4564, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1052_l1}, +/*h(21898)=1053 */ {21898, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1053_l1}, +/*h(20911)=1054 */ {20911, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1054_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1459)=1058 */ {1459, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1058_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17806)=1061 */ {17806, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9677)=1063 */ {9677, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1063_l1}, +/*h(3522)=1064 */ {3522, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1064_l1}, +/*h(2535)=1065 */ {2535, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1065_l1}, +/*h(26024)=1066 */ {26024, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1066_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17895)=1068 */ {17895, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1068_l1}, +/*h(7559)=1069 */ {7559, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1069_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5585)=1071 */ {5585, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1071_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21932)=1073 */ {21932, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1073_l1}, +/*h(20945)=1074 */ {20945, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1074_l1}, +/*h(9622)=1075 */ {9622, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1075_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1493)=1078 */ {1493, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1078_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17840)=1080 */ {17840, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1080_l1}, +/*h(16853)=1081 */ {16853, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1081_l1}, +/*h(10698)=1082 */ {10698, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1082_l1}, +/*h(9711)=1083 */ {9711, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1083_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26058)=1085 */ {26058, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1085_l1}, +/*h(25071)=1086 */ {25071, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1086_l1}, +/*h(14735)=1087 */ {14735, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1087_l1}, +/*h(8580)=1088 */ {8580, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1088_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(30095)=1090 */ {30095, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1090_l1}, +/*h(451)=1091 */ {451, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1091_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21966)=1093 */ {21966, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4488)=1095 */ {4488, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1095_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26003)=1097 */ {26003, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1097_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17874)=1100 */ {17874, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1100_l1}, +/*h(11719)=1101 */ {11719, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1101_l1}, +/*h(6551)=1102 */ {6551, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1102_l1}, +/*h(396)=1103 */ {396, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21911)=1105 */ {21911, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1105_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9601)=1107 */ {9601, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1107_l1}, +/*h(8614)=1108 */ {8614, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1472)=1110 */ {1472, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1110_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(22000)=1112 */ {22000, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1112_l1}, +/*h(16832)=1113 */ {16832, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1113_l1}, +/*h(5509)=1114 */ {5509, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1114_l1}, +/*h(4522)=1115 */ {4522, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1115_l1}, +/*h(3535)=1116 */ {3535, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1116_l1}, +/*h(26037)=1117 */ {26037, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1117_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17908)=1119 */ {17908, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1119_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1417)=1122 */ {1417, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15790)=1125 */ {15790, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9635)=1127 */ {9635, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1127_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1506)=1129 */ {1506, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1129_l1}, +/*h(24995)=1130 */ {24995, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1130_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12685)=1132 */ {12685, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1132_l1}, +/*h(10711)=1133 */ {10711, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1133_l1}, +/*h(5543)=1134 */ {5543, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1134_l1}, +/*h(4556)=1135 */ {4556, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1135_l1}, +/*h(21890)=1136 */ {21890, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1136_l1}, +/*h(26071)=1137 */ {26071, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1137_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8593)=1139 */ {8593, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1139_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1451)=1141 */ {1451, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1141_l1}, +/*h(464)=1142 */ {464, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1142_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17798)=1144 */ {17798, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1144_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9669)=1146 */ {9669, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1146_l1}, +/*h(4501)=1147 */ {4501, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26016)=1149 */ {26016, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1149_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12719)=1152 */ {12719, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5577)=1154 */ {5577, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21924)=1156 */ {21924, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1156_l1}, +/*h(20937)=1157 */ {20937, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1157_l1}, +/*h(9614)=1158 */ {9614, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1158_l1}, +/*h(8627)=1159 */ {8627, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1485)=1161 */ {1485, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1161_l1}, +/*h(498)=1162 */ {498, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1162_l1}, +/*h(17832)=1163 */ {17832, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1163_l1}, +/*h(16845)=1164 */ {16845, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1164_l1}, +/*h(10690)=1165 */ {10690, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1165_l1}, +/*h(5522)=1166 */ {5522, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26050)=1168 */ {26050, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1168_l1}, +/*h(20882)=1169 */ {20882, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1169_l1}, +/*h(14727)=1170 */ {14727, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6598)=1172 */ {6598, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1172_l1}, +/*h(30087)=1173 */ {30087, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21958)=1175 */ {21958, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1175_l1}, +/*h(16790)=1176 */ {16790, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1176_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9648)=1178 */ {9648, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1178_l1}, +/*h(8661)=1179 */ {8661, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1179_l1}, +/*h(25995)=1180 */ {25995, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1180_l1}, +/*h(25008)=1181 */ {25008, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1181_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17866)=1183 */ {17866, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1183_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5556)=1185 */ {5556, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1185_l1}, +/*h(388)=1186 */ {388, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1186_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21903)=1188 */ {21903, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1188_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17811)=1195 */ {17811, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1195_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9682)=1197 */ {9682, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1197_l1}, +/*h(4514)=1198 */ {4514, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1198_l1}, +/*h(3527)=1199 */ {3527, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1199_l1}, +/*h(26029)=1200 */ {26029, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1200_l1}, +/*h(25042)=1201 */ {25042, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1201_l1}, +/*h(13719)=1202 */ {13719, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1202_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1409)=1205 */ {1409, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1205_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21937)=1207 */ {21937, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1207_l1}, +/*h(15782)=1208 */ {15782, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1208_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8640)=1210 */ {8640, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1210_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17845)=1214 */ {17845, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1214_l1}, +/*h(12677)=1215 */ {12677, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1215_l1}, +/*h(11690)=1216 */ {11690, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1216_l1}, +/*h(9716)=1217 */ {9716, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1217_l1}, +/*h(4548)=1218 */ {4548, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1218_l1}, +/*h(26063)=1219 */ {26063, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1219_l1}, +/*h(25076)=1220 */ {25076, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8585)=1222 */ {8585, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1222_l1}, +/*h(7598)=1223 */ {7598, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1223_l1}, +/*h(1443)=1224 */ {1443, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1224_l1}, +/*h(456)=1225 */ {456, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21971)=1227 */ {21971, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1227_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4493)=1230 */ {4493, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1230_l1}, +/*h(2519)=1231 */ {2519, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1231_l1}, +/*h(30189)=1232 */ {30189, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1232_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17879)=1234 */ {17879, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1234_l1}, +/*h(12711)=1235 */ {12711, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1235_l1}, +/*h(5569)=1236 */ {5569, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1236_l1}, +/*h(401)=1237 */ {401, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1237_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26097)=1239 */ {26097, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1239_l1}, +/*h(20929)=1240 */ {20929, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1240_l1}, +/*h(9606)=1241 */ {9606, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1241_l1}, +/*h(8619)=1242 */ {8619, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1242_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1477)=1244 */ {1477, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1244_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17824)=1246 */ {17824, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1246_l1}, +/*h(16837)=1247 */ {16837, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1247_l1}, +/*h(15850)=1248 */ {15850, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1248_l1}, +/*h(5514)=1249 */ {5514, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1249_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20874)=1252 */ {20874, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11758)=1255 */ {11758, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1255_l1}, +/*h(1422)=1256 */ {1422, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1256_l1}, +/*h(435)=1257 */ {435, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1257_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16782)=1259 */ {16782, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9640)=1261 */ {9640, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25987)=1263 */ {25987, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1263_l1}, +/*h(25000)=1264 */ {25000, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1264_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17858)=1266 */ {17858, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1266_l1}, +/*h(6535)=1267 */ {6535, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1267_l1}, +/*h(5548)=1268 */ {5548, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1268_l1}, +/*h(4561)=1269 */ {4561, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1269_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21895)=1271 */ {21895, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8598)=1274 */ {8598, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1274_l1}, +/*h(1456)=1275 */ {1456, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1275_l1}, +/*h(469)=1276 */ {469, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17803)=1278 */ {17803, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1278_l1}, +/*h(16816)=1279 */ {16816, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1279_l1}, +/*h(9674)=1280 */ {9674, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1280_l1}, +/*h(8687)=1281 */ {8687, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1281_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26021)=1283 */ {26021, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1283_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13711)=1285 */ {13711, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5582)=1288 */ {5582, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21929)=1290 */ {21929, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1290_l1}, +/*h(20942)=1291 */ {20942, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1291_l1}, +/*h(9619)=1292 */ {9619, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1490)=1295 */ {1490, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1295_l1}, +/*h(24979)=1296 */ {24979, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1296_l1}, +/*h(17837)=1297 */ {17837, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1297_l1}, +/*h(16850)=1298 */ {16850, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1298_l1}, +/*h(11682)=1299 */ {11682, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1299_l1}, +/*h(5527)=1300 */ {5527, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1300_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26055)=1302 */ {26055, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1302_l1}, +/*h(20887)=1303 */ {20887, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1303_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8577)=1305 */ {8577, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1305_l1}, +/*h(7590)=1306 */ {7590, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1306_l1}, +/*h(5616)=1307 */ {5616, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1307_l1}, +/*h(448)=1308 */ {448, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1308_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21963)=1310 */ {21963, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9653)=1312 */ {9653, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1312_l1}, +/*h(3498)=1313 */ {3498, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1313_l1}, +/*h(26000)=1314 */ {26000, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1314_l1}, +/*h(30181)=1315 */ {30181, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17871)=1317 */ {17871, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1317_l1}, +/*h(16884)=1318 */ {16884, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1318_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(393)=1320 */ {393, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21908)=1322 */ {21908, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1322_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14766)=1324 */ {14766, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1324_l1}, +/*h(8611)=1325 */ {8611, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1325_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(482)=1327 */ {482, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1327_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21997)=1329 */ {21997, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1329_l1}, +/*h(15842)=1330 */ {15842, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1330_l1}, +/*h(5506)=1331 */ {5506, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1331_l1}, +/*h(9687)=1332 */ {9687, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26034)=1334 */ {26034, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1334_l1}, +/*h(20866)=1335 */ {20866, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17905)=1337 */ {17905, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1337_l1}, +/*h(11750)=1338 */ {11750, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1338_l1}, +/*h(1414)=1339 */ {1414, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1339_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21942)=1341 */ {21942, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1341_l1}, +/*h(16774)=1342 */ {16774, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9632)=1344 */ {9632, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1344_l1}, +/*h(7658)=1345 */ {7658, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(24992)=1347 */ {24992, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(11695)=1350 */ {11695, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1350_l1}, +/*h(5540)=1351 */ {5540, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1351_l1}, +/*h(3566)=1352 */ {3566, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1352_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26068)=1354 */ {26068, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8590)=1357 */ {8590, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1357_l1}, +/*h(1448)=1358 */ {1448, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1358_l1}, +/*h(461)=1359 */ {461, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1359_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17795)=1361 */ {17795, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9666)=1363 */ {9666, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1363_l1}, +/*h(4498)=1364 */ {4498, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1364_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(25026)=1366 */ {25026, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1366_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13703)=1368 */ {13703, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1368_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5574)=1371 */ {5574, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1371_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21921)=1373 */ {21921, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1373_l1}, +/*h(15766)=1374 */ {15766, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1374_l1}, +/*h(9611)=1375 */ {9611, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1375_l1}, +/*h(8624)=1376 */ {8624, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1376_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1482)=1378 */ {1482, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1378_l1}, +/*h(495)=1379 */ {495, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1379_l1}, +/*h(17829)=1380 */ {17829, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1380_l1}, +/*h(16842)=1381 */ {16842, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1381_l1}, +/*h(15855)=1382 */ {15855, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1382_l1}, +/*h(5519)=1383 */ {5519, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(20879)=1386 */ {20879, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1386_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1427)=1390 */ {1427, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21955)=1393 */ {21955, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1393_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9645)=1395 */ {9645, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1395_l1}, +/*h(3490)=1396 */ {3490, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1396_l1}, +/*h(25992)=1397 */ {25992, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1397_l1}, +/*h(1516)=1398 */ {1516, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1398_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17863)=1400 */ {17863, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1400_l1}, +/*h(16876)=1401 */ {16876, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1401_l1}, +/*h(5553)=1402 */ {5553, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1402_l1}, +/*h(385)=1403 */ {385, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21900)=1405 */ {21900, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1405_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(14758)=1407 */ {14758, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1407_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1461)=1410 */ {1461, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1410_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17808)=1412 */ {17808, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1412_l1}, +/*h(16821)=1413 */ {16821, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1413_l1}, +/*h(10666)=1414 */ {10666, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1414_l1}, +/*h(9679)=1415 */ {9679, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1415_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26026)=1417 */ {26026, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1417_l1}, +/*h(25039)=1418 */ {25039, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1418_l1}, +/*h(17897)=1419 */ {17897, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6574)=1421 */ {6574, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1421_l1}, +/*h(5587)=1422 */ {5587, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1422_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21934)=1424 */ {21934, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1424_l1}, +/*h(20947)=1425 */ {20947, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1425_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13805)=1427 */ {13805, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1427_l1}, +/*h(7650)=1428 */ {7650, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1428_l1}, +/*h(1495)=1429 */ {1495, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1429_l1}, +/*h(29165)=1430 */ {29165, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17842)=1432 */ {17842, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1432_l1}, +/*h(11687)=1433 */ {11687, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1433_l1}, +/*h(9713)=1434 */ {9713, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1434_l1}, +/*h(3558)=1435 */ {3558, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26060)=1437 */ {26060, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1437_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8582)=1439 */ {8582, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1440)=1441 */ {1440, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1441_l1}, +/*h(453)=1442 */ {453, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(21968)=1444 */ {21968, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1444_l1}, +/*h(20981)=1445 */ {20981, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1445_l1}, +/*h(14826)=1446 */ {14826, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1446_l1}, +/*h(3503)=1447 */ {3503, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26005)=1449 */ {26005, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1449_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17876)=1451 */ {17876, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1451_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10734)=1453 */ {10734, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1453_l1}, +/*h(398)=1454 */ {398, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1454_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26094)=1456 */ {26094, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1456_l1}, +/*h(15758)=1457 */ {15758, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1457_l1}, +/*h(9603)=1458 */ {9603, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1458_l1}, +/*h(8616)=1459 */ {8616, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1459_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1474)=1461 */ {1474, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1461_l1}, +/*h(487)=1462 */ {487, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1462_l1}, +/*h(22002)=1463 */ {22002, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1463_l1}, +/*h(11666)=1464 */ {11666, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1464_l1}, +/*h(15847)=1465 */ {15847, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1465_l1}, +/*h(5511)=1466 */ {5511, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1466_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(26039)=1468 */ {26039, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1468_l1}, +/*h(20871)=1469 */ {20871, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1469_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(17910)=1471 */ {17910, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1471_l1}, +/*h(7574)=1472 */ {7574, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1472_l1}, +/*h(1419)=1473 */ {1419, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1473_l1}, +/*h(432)=1474 */ {432, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(16779)=1476 */ {16779, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1476_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(9637)=1478 */ {9637, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1478_l1}, +/*h(7663)=1479 */ {7663, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1479_l1}, +/*h(25984)=1480 */ {25984, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1480_l1}, +/*h(24997)=1481 */ {24997, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12687)=1483 */ {12687, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1483_l1}, +/*h(16868)=1484 */ {16868, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1484_l1}, +/*h(5545)=1485 */ {5545, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1485_l1}, +/*h(4558)=1486 */ {4558, xed3_phash_find_mapevex_map1_opcode0x79_vv2_1486_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 1488ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7a_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[137] = { +/*h(411)=0 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {411, 4373}, +/*h(731)=1 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {731, 4366}, +/*h(92)=2 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 6113}, +/*h(412)=3 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {412, 6150}, +/*h(732)=4 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {732, 6146}, +/*h(93)=5 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 6113}, +/*h(413)=6 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {413, 6150}, +/*h(733)=7 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {733, 6146}, +/*h(94)=8 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 6112}, +/*h(414)=9 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {414, 6149}, +/*h(734)=10 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {734, 6144}, +/*h(95)=11 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {95, 6117}, +/*h(415)=12 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {415, 6152}, +/*h(735)=13 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {735, 6145}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(600)=19 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {600, 6132}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(601)=22 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {601, 6132}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(602)=25 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 6130}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(603)=28 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {603, 6131}, +/*h(923)=29 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {923, 4373}, +/*empty slot1 */ {0,0}, +/*h(604)=31 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 6118}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(605)=34 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 6118}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(606)=37 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 6116}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(607)=40 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {607, 6117}, +/*h(927)=41 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {927, 6152}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=45 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {152, 4376}, +/*h(472)=46 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {472, 4371}, +/*empty slot1 */ {0,0}, +/*h(153)=48 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {153, 4376}, +/*h(473)=49 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {473, 4371}, +/*empty slot1 */ {0,0}, +/*h(154)=51 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {154, 4375}, +/*h(474)=52 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 4370}, +/*empty slot1 */ {0,0}, +/*h(155)=54 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {155, 4373}, +/*h(475)=55 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {475, 4366}, +/*empty slot1 */ {0,0}, +/*h(156)=57 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {156, 6148}, +/*h(476)=58 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {476, 6143}, +/*empty slot1 */ {0,0}, +/*h(157)=60 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {157, 6148}, +/*h(477)=61 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {477, 6143}, +/*empty slot1 */ {0,0}, +/*h(158)=63 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {158, 6147}, +/*h(478)=64 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {478, 6142}, +/*empty slot1 */ {0,0}, +/*h(159)=66 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {159, 6152}, +/*h(479)=67 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {479, 6145}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(344)=73 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {344, 6129}, +/*h(664)=74 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {664, 4374}, +/*empty slot1 */ {0,0}, +/*h(345)=76 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {345, 6129}, +/*h(665)=77 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {665, 4374}, +/*empty slot1 */ {0,0}, +/*h(346)=79 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 6128}, +/*h(666)=80 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {666, 4372}, +/*empty slot1 */ {0,0}, +/*h(347)=82 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {347, 6131}, +/*h(667)=83 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {667, 4373}, +/*h(987)=84 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {987, 4366}, +/*h(348)=85 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 6115}, +/*h(668)=86 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {668, 6153}, +/*empty slot1 */ {0,0}, +/*h(349)=88 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 6115}, +/*h(669)=89 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {669, 6153}, +/*empty slot1 */ {0,0}, +/*h(350)=91 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 6114}, +/*h(670)=92 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {670, 6151}, +/*empty slot1 */ {0,0}, +/*h(351)=94 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {351, 6117}, +/*h(671)=95 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {671, 6152}, +/*h(991)=96 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {991, 6145}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=100 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {216, 4369}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(217)=103 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {217, 4369}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(218)=106 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 4368}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(219)=109 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {219, 4366}, +/*empty slot1 */ {0,0}, +/*h(859)=111 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {859, 6131}, +/*h(220)=112 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {220, 6141}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(221)=115 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {221, 6141}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(222)=118 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {222, 6140}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(223)=121 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {223, 6145}, +/*empty slot1 */ {0,0}, +/*h(863)=123 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {863, 6117}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(88)=127 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {88, 6127}, +/*h(408)=128 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {408, 4378}, +/*h(728)=129 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {728, 4367}, +/*h(89)=130 EVV 0x7A V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {89, 6127}, +/*h(409)=131 EVV 0x7A VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_FULL()*/ {409, 4378}, +/*h(729)=132 EVV 0x7A VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {729, 4367}, +/*h(90)=133 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 6126}, +/*h(410)=134 EVV 0x7A VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {410, 4377}, +/*h(730)=135 EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 4365}, +/*h(91)=136 EVV 0x7A V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 NOEVSR*/ {91, 6131} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = (3*key % 137); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_841_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1030)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_451_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3078)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3078; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_61_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5126)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5126; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1135_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7174)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1159_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1286)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_769_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(750)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {750, 6070}, +/*h(3334)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3334, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_379_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5382)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5382, 4379}, +/*h(2798)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2798, 6072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1453_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7430)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7430, 4379}, +/*h(4846)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4846, 6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1000_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1158)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1158, 4379}, +/*h(2755)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2755, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_610_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3206)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3206, 4379}, +/*h(4803)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4803, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_220_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5254)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1294_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7302)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7302, 4379}, +/*h(8899)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8899, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1414)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_927_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3462)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_537_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5510)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_147_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7558)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1094)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1094; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3142)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_873_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5190)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_483_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7238)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7238; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_506_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1350)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3398)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3398; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5446)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_800_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7494)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_347_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1222)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3270)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1031_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5318)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_641_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7366)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_665_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1478)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_275_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3526)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1349_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5574)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_959_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7622)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_515_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1062)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1062; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_125_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3110)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3110; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1199_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5158)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5158; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_809_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7206)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7206, 4379}, +/*h(2038)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {2038, 4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_832_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1318)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_442_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3366)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_52_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5414)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1126_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7462)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_674_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1190)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1190, 4379}, +/*h(2787)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {2787, 6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_284_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3238)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3238, 4379}, +/*h(4835)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4835, 6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5286)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_968_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7334)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7334, 4379}, +/*h(8931)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8931, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_991_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1446)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_601_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3494)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3494; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5542)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1285_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7590)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1326_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1126)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1126; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_936_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3174)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3174; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_546_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5222)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5222; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_156_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7270)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_180_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1382)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1382; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3430)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3430; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_864_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5478)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5478; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_474_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7526)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_21_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1254)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1095_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3302)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3302, 4379}, +/*h(718)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {718, 6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_705_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2766)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2766, 6086}, +/*h(5350)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5350, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_315_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7398)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7398, 4379}, +/*h(4814)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4814, 6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_338_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1510)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3558)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1022_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5606)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_632_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7654)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_760_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1038)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1038, 4379}, +/*h(10997)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {10997, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_370_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3086)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3086, 4379}, +/*h(13045)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13045, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1444_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5134)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5134, 4379}, +/*h(15093)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {15093, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1054_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7182)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1077_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3878)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3878, 4386}, +/*h(1294)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1294, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_687_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3342)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3342, 4379}, +/*h(5926)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5926, 4386}, +/*h(758)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {758, 6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_297_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7974)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7974, 4386}, +/*h(2806)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2806, 6072}, +/*h(5390)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5390, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1371_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4854)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4854, 6074}, +/*h(7438)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7438, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_918_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3750)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3750, 4386}, +/*h(1166)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1166, 4379}, +/*h(8918)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8918, 6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_528_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10966)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10966, 6086}, +/*h(5798)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5798, 4386}, +/*h(3214)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3214, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7846)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7846, 4386}, +/*h(5262)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5262, 4379}, +/*h(13014)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13014, 6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1212_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7310)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7310; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1236_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1422)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_846_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3470)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3470; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_456_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5518)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_66_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7566)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7566; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3686)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3686, 4386}, +/*h(1102)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1102, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1181_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3150)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3150, 4379}, +/*h(5734)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5734, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_791_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7782)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7782, 4386}, +/*h(5198)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5198, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7246)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7246; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_424_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3942)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3942, 4386}, +/*h(1358)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1358, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_34_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5990)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5990, 4386}, +/*h(3406)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3406, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1108_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5454)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5454, 4379}, +/*h(8038)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8038, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_718_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7502)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7502, 4379}, +/*h(737)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {737, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_266_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1230)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3278)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_950_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5326)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_560_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7374)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_583_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4070)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4070, 4386}, +/*h(1486)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1486, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3534)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3534, 4379}, +/*h(6118)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6118, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1267_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8166)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8166, 4386}, +/*h(5582)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5582, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_877_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7630)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7630; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3654)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3654, 4386}, +/*h(13003)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {13003, 6090}, +/*h(1070)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1070, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_43_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5702)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5702, 4386}, +/*h(3118)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3118, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1117_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5166)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5166, 4379}, +/*h(7750)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7750, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_727_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7214)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7214; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_751_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1326)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1326; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_361_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3374)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3374; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5422)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5422; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1045_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7470)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7470, 4379}, +/*h(705)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {705, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_592_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1198)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1198, 4379}, +/*h(3782)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3782, 4386}, +/*h(2795)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {2795, 6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5830)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5830, 4386}, +/*h(3246)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3246, 4379}, +/*h(4843)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4843, 6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1276_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7878)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7878, 4386}, +/*h(5294)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5294, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_886_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7342)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7342, 4379}, +/*h(8939)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8939, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_909_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4038)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4038, 4386}, +/*h(1454)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1454, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_519_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6086)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6086, 4386}, +/*h(3502)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3502, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5550)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5550, 4379}, +/*h(8134)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8134, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1203_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7598)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1245_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1134)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_855_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3182)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_465_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5230)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5230; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_75_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7278)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7278; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_98_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3974)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3974, 4386}, +/*h(1390)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1390, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1172_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3438)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3438, 4379}, +/*h(6022)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6022, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_782_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8070)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8070, 4386}, +/*h(5486)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5486, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7534)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7534; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1403_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3846)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3846, 4386}, +/*h(1262)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1262, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1013_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5894)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5894, 4386}, +/*h(3310)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3310, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_623_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5358)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5358, 4379}, +/*h(7942)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7942, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_233_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7406)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7406; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1518)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1518; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3566)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3566; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_941_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5614)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5614; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_551_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7662)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7662; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_282_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1031)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1356_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1482)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1482, 4381}, +/*h(3079)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3079, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_966_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3530)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3530, 4381}, +/*h(5127)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5127, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_576_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5578)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5578, 4381}, +/*h(7175)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7175, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_599_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1287)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1287; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_209_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1738)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1738, 4390}, +/*h(3335)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3335, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1283_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3786)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3786, 4390}, +/*h(5383)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5383, 4379}, +/*h(1202)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1202, 4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_893_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7431)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7431, 4379}, +/*h(3250)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3250, 4385}, +/*h(5834)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5834, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_441_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2756)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2756, 6086}, +/*h(1159)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1159, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_51_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4804)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4804, 6088}, +/*h(3207)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3207, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1125_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1074)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1074, 4385}, +/*h(5255)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5255, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_735_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3122)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3122, 4385}, +/*h(7303)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7303, 4379}, +/*h(8900)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8900, 6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_758_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1415)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_368_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1866)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1866, 4390}, +/*h(3463)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3463, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1442_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5511)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5511, 4379}, +/*h(1330)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1330, 4385}, +/*h(3914)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3914, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1052_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3378)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3378, 4385}, +/*h(5962)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5962, 4390}, +/*h(7559)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7559, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1093_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13028)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {13028, 6074}, +/*h(1095)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1095, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_703_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1546)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1546, 4390}, +/*h(3143)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3143, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_313_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3594)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3594, 4390}, +/*h(5191)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5191, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1387_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5642)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5642, 4390}, +/*h(7239)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7239, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1411_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1351)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1351; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1021_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3399)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3399; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_631_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1266)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1266, 4385}, +/*h(5447)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5447, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_241_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3314)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3314, 4385}, +/*h(7495)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7495, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1252_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1223)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1223; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_862_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1674)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1674, 4390}, +/*h(3271)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3271, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_472_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5319)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5319, 4379}, +/*h(1138)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1138, 4385}, +/*h(3722)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3722, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_82_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3186)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3186, 4385}, +/*h(5770)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5770, 4390}, +/*h(7367)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7367, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_105_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1479)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1479; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1179_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1930)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1930, 4390}, +/*h(3527)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3527, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_789_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3978)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3978, 4390}, +/*h(5575)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5575, 4379}, +/*h(1394)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1394, 4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_399_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7623)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7623, 4379}, +/*h(3442)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3442, 4385}, +/*h(6026)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6026, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1420_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1063)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1030_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3111)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3111; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_640_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5159)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5159; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_250_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2039)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {2039, 4393}, +/*h(7207)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7207, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_273_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1319)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1347_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1770)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1770, 4390}, +/*h(3367)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3367, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_957_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5415)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5415, 4379}, +/*h(1234)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1234, 4382}, +/*h(3818)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3818, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_567_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3282)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3282, 4382}, +/*h(5866)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5866, 4390}, +/*h(7463)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7463, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_114_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8943)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8943, 6075}, +/*h(1191)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1191, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1188_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10991)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {10991, 6075}, +/*h(1642)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1642, 4390}, +/*h(3239)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3239, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_798_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3690)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3690, 4390}, +/*h(5287)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5287, 4379}, +/*h(13039)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13039, 6075}, +/*h(1106)=3 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1106, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_408_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(7335)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7335, 4379}, +/*h(3154)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3154, 4382}, +/*h(5738)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5738, 4390}, +/*h(15087)=3 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {15087, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1447)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1447; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_42_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3495)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3495; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1116_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5543)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_726_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7591)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_767_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1127)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1127; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_377_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1578)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1578, 4390}, +/*h(3175)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3175, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1451_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5223)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5223, 4379}, +/*h(1042)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1042, 4382}, +/*h(3626)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3626, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1061_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3090)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3090, 4382}, +/*h(5674)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5674, 4390}, +/*h(7271)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7271, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1084_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1383)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1383; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_694_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1834)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1834, 4390}, +/*h(3431)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3431, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_304_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3882)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3882, 4390}, +/*h(5479)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5479, 4379}, +/*h(1298)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1298, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1378_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7527)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7527, 4379}, +/*h(3346)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3346, 4382}, +/*h(5930)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5930, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_926_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1255)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1255; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_536_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3303)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3303, 4379}, +/*h(719)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {719, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_146_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1170)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1170, 4382}, +/*h(2767)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {2767, 6089}, +/*h(5351)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5351, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1220_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4815)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4815, 6089}, +/*h(7399)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7399, 4379}, +/*h(3218)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3218, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1243_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1511)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1511; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_853_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1962)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1962, 4390}, +/*h(3559)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3559, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_463_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5607)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5607, 4379}, +/*h(1426)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1426, 4382}, +/*h(4010)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4010, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_73_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3474)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3474, 4382}, +/*h(6058)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6058, 4390}, +/*h(7655)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7655, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_201_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10998)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {10998, 6072}, +/*h(1039)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1039, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1275_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13046)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {13046, 6074}, +/*h(3087)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3087, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_885_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5135)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5135; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_495_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7183)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_518_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3879)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3879, 4388}, +/*h(1295)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1295, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_128_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(759)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {759, 6075}, +/*h(3343)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3343, 4379}, +/*h(5927)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5927, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1202_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5391)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5391, 4379}, +/*h(7975)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7975, 4388}, +/*h(2807)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {2807, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_812_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7439)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7439, 4379}, +/*h(4855)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4855, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_359_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1167)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1167, 4379}, +/*h(3751)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3751, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1433_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5799)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5799, 4388}, +/*h(1618)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1618, 4391}, +/*h(3215)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3215, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1043_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3666)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3666, 4391}, +/*h(5263)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5263, 4379}, +/*h(7847)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7847, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_653_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5714)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5714, 4391}, +/*h(7311)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7311, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_676_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4007)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4007, 4388}, +/*h(1423)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1423, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_286_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3471)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3471, 4379}, +/*h(6055)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6055, 4388}, +/*h(1874)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1874, 4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8103)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8103, 4388}, +/*h(3922)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3922, 4391}, +/*h(5519)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5519, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_970_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5970)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5970, 4391}, +/*h(7567)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7567, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1012_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3687)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3687, 4388}, +/*h(1103)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1103, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_622_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3151)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3151, 4379}, +/*h(8929)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8929, 6071}, +/*h(5735)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5735, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 11) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_232_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10977)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {10977, 6073}, +/*h(5199)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5199, 4379}, +/*h(7783)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7783, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1306_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13025)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {13025, 6076}, +/*h(7247)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7247, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1329_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1359)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1359, 4379}, +/*h(3943)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3943, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_939_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5991)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5991, 4388}, +/*h(1810)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1810, 4391}, +/*h(3407)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3407, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_549_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3858)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3858, 4391}, +/*h(5455)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5455, 4379}, +/*h(8039)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8039, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_159_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5906)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5906, 4391}, +/*h(738)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {738, 6071}, +/*h(7503)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7503, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1170_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3815)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3815, 4388}, +/*h(1231)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1231, 4379}, +/*h(4802)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4802, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_780_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3279)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3279, 4379}, +/*h(5863)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5863, 4388}, +/*h(1682)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1682, 4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_390_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3730)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3730, 4391}, +/*h(7911)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7911, 4388}, +/*h(5327)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5327, 4379}, +/*h(8898)=3 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8898, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_0_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5778)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5778, 4391}, +/*h(7375)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7375, 4379}, +/*h(10946)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {10946, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_24_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1487)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1098_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3535)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_708_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5583)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5583; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_318_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7631)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7631; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1338_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1071)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1071, 4379}, +/*h(3655)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3655, 4388}, +/*h(13004)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13004, 6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_948_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5703)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5703, 4388}, +/*h(1522)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1522, 4385}, +/*h(3119)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3119, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_558_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3570)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3570, 4385}, +/*h(5167)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5167, 4379}, +/*h(7751)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7751, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_168_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5618)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5618, 4385}, +/*h(7215)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7215, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_191_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3911)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3911, 4388}, +/*h(1327)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1327, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3375)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3375, 4379}, +/*h(5959)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5959, 4388}, +/*h(1778)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1778, 4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_875_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8007)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8007, 4388}, +/*h(3826)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3826, 4394}, +/*h(5423)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5423, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_485_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5874)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5874, 4394}, +/*h(7471)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7471, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_33_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2796)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2796, 6072}, +/*h(3783)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3783, 4388}, +/*h(1199)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1199, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1107_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5831)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5831, 4388}, +/*h(3247)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3247, 4379}, +/*h(4844)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4844, 6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_717_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5295)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5295, 4379}, +/*h(7879)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7879, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_327_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8940)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {8940, 6070}, +/*h(7343)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7343, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_350_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1455)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1455, 4379}, +/*h(4039)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4039, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1424_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(6087)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6087, 4388}, +/*h(1906)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1906, 4394}, +/*h(3503)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3503, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1034_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3954)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3954, 4394}, +/*h(5551)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5551, 4379}, +/*h(8135)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8135, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_644_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6002)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6002, 4394}, +/*h(7599)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7599, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_685_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3719)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3719, 4388}, +/*h(1135)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1135, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3183)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3183; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1370_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5231)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5231; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_980_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7279)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7279; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1003_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1391)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1391; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_613_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3439)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3439; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_223_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5487)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5487; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1297_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7535)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7535; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_844_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1263)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1263, 4379}, +/*h(3847)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3847, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_454_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(5895)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5895, 4388}, +/*h(727)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {727, 6089}, +/*h(1714)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1714, 4394}, +/*h(3311)=3 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3311, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_64_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(2775)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {2775, 6089}, +/*h(5359)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5359, 4379}, +/*h(7943)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7943, 4388}, +/*h(3762)=3 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3762, 4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1138_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4823)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {4823, 6089}, +/*h(5810)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5810, 4394}, +/*h(7407)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7407, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1519)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1519; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_771_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1970)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1970, 4394}, +/*h(3567)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3567, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_381_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4018)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4018, 4394}, +/*h(5615)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5615, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1455_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6066)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6066, 4394}, +/*h(7663)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7663, 4379} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_678_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3630)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3630, 4386}, +/*h(1046)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1046, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5678)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5678, 4386}, +/*h(3094)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3094, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1362_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5142)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5142, 4380}, +/*h(7726)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7726, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_972_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7190)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7190; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_995_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1302)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1302, 4380}, +/*h(3886)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3886, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_605_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5934)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5934, 4386}, +/*h(3350)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3350, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7982)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7982, 4386}, +/*h(5398)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5398, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1289_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7446)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7446; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_837_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2771)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2771, 6087}, +/*h(3758)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3758, 4386}, +/*h(1174)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1174, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_447_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5806)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5806, 4386}, +/*h(3222)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3222, 4380}, +/*h(4819)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4819, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_57_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7854)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7854, 4386}, +/*h(5270)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5270, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1131_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7318)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7318, 4380}, +/*h(8915)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8915, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4014)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4014, 4386}, +/*h(1430)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1430, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_764_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6062)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6062, 4386}, +/*h(3478)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3478, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5526)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5526, 4380}, +/*h(8110)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8110, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1448_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7574)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_25_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1110)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1110, 4380}, +/*h(3694)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3694, 4386}, +/*h(13043)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {13043, 6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1099_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5742)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5742, 4386}, +/*h(3158)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3158, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_709_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7790)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7790, 4386}, +/*h(5206)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5206, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7254)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7254; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_343_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1366)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1417_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3414)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1027_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5462)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_637_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7510)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7510, 4380}, +/*h(745)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {745, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3822)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3822, 4386}, +/*h(1238)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1238, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1258_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5870)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5870, 4386}, +/*h(3286)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3286, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_868_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5334)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5334, 4380}, +/*h(7918)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7918, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_478_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7382)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7382; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_501_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1494)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1494, 4380}, +/*h(4078)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4078, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6126)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6126, 4386}, +/*h(3542)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3542, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1185_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8174)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8174, 4386}, +/*h(5590)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5590, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_795_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7638)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_119_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1047)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1047, 4380}, +/*h(3631)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3631, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1193_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5679)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5679, 4388}, +/*h(3095)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3095, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_803_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7727)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7727, 4388}, +/*h(5143)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5143, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_413_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7191)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7191, 4380}, +/*h(2023)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {2023, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_436_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3887)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3887, 4388}, +/*h(1303)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1303, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_46_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3351)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3351, 4380}, +/*h(5935)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5935, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1218)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1218, 4381}, +/*h(5399)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5399, 4380}, +/*h(7983)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7983, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_730_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3266)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3266, 4381}, +/*h(7447)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7447, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_278_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2772)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2772, 6086}, +/*h(1175)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1175, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4820)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4820, 6088}, +/*h(3223)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3223, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_962_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5271)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_572_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8916)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8916, 6084}, +/*h(7319)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7319, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_595_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1431)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1431, 4380}, +/*h(4015)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4015, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_205_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6063)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6063, 4388}, +/*h(3479)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3479, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1279_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1346)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1346, 4381}, +/*h(8111)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8111, 4388}, +/*h(5527)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5527, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_889_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3394)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3394, 4381}, +/*h(7575)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7575, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_930_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(13044)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {13044, 6074}, +/*h(1111)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1111, 4380}, +/*h(3695)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3695, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_540_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3159)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3159, 4380}, +/*h(5743)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5743, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_150_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7791)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7791, 4388}, +/*h(5207)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5207, 4380}, +/*h(1026)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1026, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1224_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3074)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3074, 4381}, +/*h(7255)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7255, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1248_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1367)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_858_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3415)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_468_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5463)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5463; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_78_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(746)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {746, 6071}, +/*h(7511)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7511, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1089_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1239)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1239, 4380}, +/*h(3823)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3823, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_699_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5871)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5871, 4388}, +/*h(3287)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3287, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_309_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5335)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5335, 4380}, +/*h(1154)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1154, 4381}, +/*h(7919)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7919, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3202)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3202, 4381}, +/*h(7383)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7383, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1406_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4079)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4079, 4388}, +/*h(1495)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1495, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1016_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3543)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3543, 4380}, +/*h(6127)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6127, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_626_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5591)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5591, 4380}, +/*h(8175)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8175, 4388}, +/*h(1410)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1410, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_236_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3458)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3458, 4381}, +/*h(7639)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7639, 4380} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_834_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5122)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5122; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_444_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7170)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7170; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_467_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1282)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1282, 4381}, +/*h(8047)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8047, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_77_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3330)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5378)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_761_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7426)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7426; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_993_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5250)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_603_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7298)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7298; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5506)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5506; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_920_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7554)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_961_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1090)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1090, 4381}, +/*h(7855)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7855, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_571_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3138)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3138; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_181_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5186)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5186; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7234)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7234; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_499_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5442)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_109_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7490)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7490, 4381}, +/*h(725)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {725, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_340_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5314)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5314; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1414_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7362)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1437_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1474)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1474, 4381}, +/*h(5655)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {5655, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1047_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3522)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3522, 4381}, +/*h(7703)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {7703, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_657_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5570)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_267_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7618)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7618; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1288_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7823)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7823, 4388}, +/*h(5239)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5239, 4384}, +/*h(1058)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1058, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_898_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3106)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3106, 4381}, +/*h(7287)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7287, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_508_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5154)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5154; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_118_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2034)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {2034, 4394}, +/*h(7202)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7202, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_141_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5495)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5495, 4384}, +/*h(1314)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1314, 4381}, +/*h(8079)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8079, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1215_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3362)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3362, 4381}, +/*h(7543)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7543, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_825_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5410)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_435_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7458)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1446_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8938)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8938, 6071}, +/*h(7951)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7951, 4388}, +/*h(1186)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1186, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1056_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3234)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3234, 4381}, +/*h(10986)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {10986, 6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_666_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13034)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {13034, 6076}, +/*h(5282)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5282, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_276_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7330)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7330; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_300_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1442)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1442, 4381}, +/*h(5623)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5623, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1374_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3490)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3490, 4381}, +/*h(7671)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7671, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_984_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5538)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_594_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7586)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7586; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_635_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1122)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1122, 4381}, +/*h(7887)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7887, 4388}, +/*h(5303)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5303, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_245_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3170)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3170, 4381}, +/*h(7351)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7351, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1319_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5218)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5218; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_929_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7266)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7266; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_952_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5559)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5559, 4384}, +/*h(1378)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1378, 4381}, +/*h(8143)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8143, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_562_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3426)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3426, 4381}, +/*h(7607)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7607, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_172_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5474)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5474; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1246_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7522)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7522, 4381}, +/*h(757)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {757, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_794_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8015)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8015, 4388}, +/*h(5431)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5431, 4384}, +/*h(1250)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1250, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_404_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(714)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {714, 6085}, +/*h(3298)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3298, 4381}, +/*h(7479)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7479, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_14_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5346)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5346, 4381}, +/*h(2762)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2762, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1088_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7394)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7394, 4381}, +/*h(4810)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4810, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1111_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1506)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1506, 4381}, +/*h(5687)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {5687, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_721_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3554)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3554, 4381}, +/*h(7735)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {7735, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_331_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5602)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1405_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7650)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_69_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1034)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1034, 4381}, +/*h(10993)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {10993, 6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1143_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3082)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3082, 4381}, +/*h(13041)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {13041, 6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_753_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5130)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5130, 4381}, +/*h(1559)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {1559, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_363_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7178)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7178, 4381}, +/*h(3607)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {3607, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_386_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1290)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1290, 4381}, +/*h(8055)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {8055, 4393}, +/*h(3874)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3874, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5922)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5922, 4390}, +/*h(754)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {754, 6071}, +/*h(3338)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3338, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1070_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2802)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {2802, 6073}, +/*h(5386)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5386, 4381}, +/*h(7970)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7970, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_680_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7434)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7434, 4381}, +/*h(4850)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4850, 6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1162)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1162, 4381}, +/*h(3746)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3746, 4390}, +/*h(7927)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {7927, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3210)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3210, 4381}, +/*h(5794)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5794, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_911_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7842)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7842, 4390}, +/*h(5258)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5258, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_521_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7306)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7306; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_544_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8183)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {8183, 4393}, +/*h(4002)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4002, 4390}, +/*h(1418)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1418, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_154_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6050)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6050, 4390}, +/*h(3466)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3466, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1228_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5514)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5514, 4381}, +/*h(8098)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8098, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_838_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7562)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_880_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3682)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3682, 4390}, +/*h(1098)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1098, 4381}, +/*h(7863)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {7863, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_490_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5730)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5730, 4390}, +/*h(3146)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3146, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_100_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7778)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7778, 4390}, +/*h(5194)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5194, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1174_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7242)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7242; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1197_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3938)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3938, 4390}, +/*h(1354)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1354, 4381}, +/*h(8119)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {8119, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_807_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3402)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3402, 4381}, +/*h(5986)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5986, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_417_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8034)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8034, 4390}, +/*h(5450)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5450, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_27_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7498)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7498; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1038_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7991)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {7991, 4393}, +/*h(1226)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1226, 4381}, +/*h(3810)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3810, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 13) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_648_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5858)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5858, 4390}, +/*h(3274)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3274, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_258_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5322)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5322, 4381}, +/*h(7906)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7906, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7370)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7370; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_186_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7626)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7626; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1206_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(12999)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {12999, 6089}, +/*h(7831)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {7831, 4389}, +/*h(1066)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1066, 4381}, +/*h(3650)=3 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3650, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((8*key % 7) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_816_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3114)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3114, 4381}, +/*h(5698)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5698, 4390}, +/*h(15047)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {15047, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_426_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7746)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7746, 4390}, +/*h(5162)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5162, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_36_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7210)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7210; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_59_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3906)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3906, 4390}, +/*h(1322)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1322, 4381}, +/*h(8087)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {8087, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1133_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5954)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5954, 4390}, +/*h(3370)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3370, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_743_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5418)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5418, 4381}, +/*h(8002)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8002, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_353_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7466)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7466; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1365_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(3778)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3778, 4390}, +/*h(2791)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {2791, 6075}, +/*h(7959)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {7959, 4389}, +/*h(1194)=3 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1194, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 29) % 4); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_975_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5826)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5826, 4390}, +/*h(3242)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3242, 4381}, +/*h(4839)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4839, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_585_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(5290)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5290, 4381}, +/*h(6887)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6887, 6075}, +/*h(7874)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7874, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_195_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7338)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7338, 4381}, +/*h(8935)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8935, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_218_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4034)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4034, 4390}, +/*h(1450)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1450, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1292_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3498)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3498, 4381}, +/*h(6082)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6082, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_902_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8130)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8130, 4390}, +/*h(5546)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5546, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_512_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7594)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7594; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_553_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3714)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3714, 4390}, +/*h(1130)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1130, 4381}, +/*h(7895)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {7895, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5762)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5762, 4390}, +/*h(3178)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3178, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1237_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5226)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5226, 4381}, +/*h(7810)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7810, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_847_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7274)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7274; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_871_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1386)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1386, 4381}, +/*h(8151)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {8151, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_481_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3434)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3434; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_91_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5482)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5482; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7530)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7530; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_712_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8023)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {8023, 4389}, +/*h(3842)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3842, 4390}, +/*h(1258)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1258, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_322_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(3306)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3306, 4381}, +/*h(5890)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5890, 4390}, +/*h(722)=2 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {722, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1396_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7938)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7938, 4390}, +/*h(2770)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2770, 6087}, +/*h(5354)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5354, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1006_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4818)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4818, 6090}, +/*h(7402)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7402, 4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1029_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1514)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1514; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_639_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3562)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3562; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5610)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5610; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1323_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7658)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() not64 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4381} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7658; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_671_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7722)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7722, 4390}, +/*h(5138)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5138, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_281_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2018)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {2018, 4390}, +/*h(7186)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7186, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_988_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5394)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5394, 4382}, +/*h(7978)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7978, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_598_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7442)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7442; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_830_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5266)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5266, 4382}, +/*h(6863)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6863, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_440_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7314)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7314, 4382}, +/*h(8911)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8911, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1147_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8106)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8106, 4390}, +/*h(5522)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5522, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_757_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7570)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7570; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_18_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5202)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5202, 4382}, +/*h(7786)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7786, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1092_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7250)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7250; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1115_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1362)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1362, 4382}, +/*h(3946)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3946, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_725_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5994)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5994, 4390}, +/*h(3410)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3410, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_336_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5458)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5458; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1410_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7506)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7506, 4382}, +/*h(741)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {741, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_177_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7914)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7914, 4390}, +/*h(5330)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5330, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1251_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7378)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7378; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1274_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(4074)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4074, 4390}, +/*h(5671)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5671, 4388}, +/*h(1490)=2 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1490, 4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_884_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(7719)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7719, 4388}, +/*h(3538)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3538, 4382}, +/*h(6122)=2 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6122, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_494_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5586)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5586, 4382}, +/*h(8170)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8170, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_104_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7634)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W0 ZEROING=0 MASK=0 BCRC=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4382} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_352_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3662)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3662, 4386}, +/*h(1078)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {1078, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1426_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8904)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8904, 6085}, +/*h(5710)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5710, 4386}, +/*h(3126)=2 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {3126, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1036_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(10952)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {10952, 6087}, +/*h(5174)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {5174, 4383}, +/*h(7758)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7758, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_646_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13000)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {13000, 6090}, +/*h(7222)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {7222, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_669_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3918)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3918, 4386}, +/*h(1334)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {1334, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_279_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5966)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5966, 4386}, +/*h(3382)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {3382, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1353_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5430)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {5430, 4383}, +/*h(8014)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8014, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_963_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7478)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {7478, 4383}, +/*h(713)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {713, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_510_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1206)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {1206, 4383}, +/*h(3790)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3790, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_120_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5838)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5838, 4386}, +/*h(3254)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {3254, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1194_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7886)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7886, 4386}, +/*h(5302)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {5302, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_804_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7350)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7350; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_828_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1462)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1462; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3510)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3510; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_48_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5558)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1122_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7606)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1163_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3726)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3726, 4386}, +/*h(1142)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {1142, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_773_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5774)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5774, 4386}, +/*h(3190)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {3190, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_383_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5238)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {5238, 4383}, +/*h(7822)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7822, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1457_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7286)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7286; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_16_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1398)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {1398, 4383}, +/*h(3982)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3982, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1090_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6030)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {6030, 4386}, +/*h(3446)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {3446, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_700_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8078)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8078, 4386}, +/*h(5494)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {5494, 4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_310_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7542)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1322_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1270)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1270; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_932_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3318)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3318; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_542_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5366)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5366; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_152_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7414)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7414; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1526)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1526; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1249_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3574)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_859_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5622)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_469_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7670)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=0 FIX_ROUND_LEN128()*/ {4383} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1257_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1079)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1079; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_867_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8905)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8905, 6085}, +/*h(3127)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {3127, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_477_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5175)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {5175, 4384}, +/*h(10953)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {10953, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_87_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7223)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {7223, 4384}, +/*h(13001)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {13001, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_110_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1335)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {1335, 4384}, +/*h(3919)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3919, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1184_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5967)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5967, 4388}, +/*h(3383)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {3383, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3791)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3791, 4388}, +/*h(1207)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {1207, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1025_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3255)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {3255, 4384}, +/*h(5839)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5839, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_268_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4047)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4047, 4388}, +/*h(1463)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {1463, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1342_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6095)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6095, 4388}, +/*h(3511)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {3511, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_604_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1143)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {1143, 4384}, +/*h(3727)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3727, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_214_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5775)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5775, 4388}, +/*h(3191)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {3191, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_921_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3983)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3983, 4388}, +/*h(1399)=1 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {1399, 4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_531_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3447)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {3447, 4384}, +/*h(6031)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6031, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_763_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1271)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1271; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_373_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3319)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3319; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1447_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5367)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5367; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1057_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7415)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7415; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1080_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1527)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1527; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_690_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3575)=0 EVV 0x7B VF2 V0F MOD[0b11] MOD=3 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 BCRC=1 FIX_ROUND_LEN128() AVX512_ROUND()*/ {4384} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_345_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5170)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5170, 4385}, +/*h(10948)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10948, 6086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1419_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7218)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7218, 4385}, +/*h(12996)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {12996, 6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_662_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8010)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8010, 4390}, +/*h(5426)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5426, 4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_272_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7474)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7474, 4385}, +/*h(709)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {709, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_503_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5298)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5298, 4385}, +/*h(7882)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7882, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7346)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7346; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_136_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1458)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1458, 4385}, +/*h(4042)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4042, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1210_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6090)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6090, 4390}, +/*h(3506)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3506, 4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_820_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8138)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8138, 4390}, +/*h(5554)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5554, 4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7602)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1156_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7818)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7818, 4390}, +/*h(5234)=1 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5234, 4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_766_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7282)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7282; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_9_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5490)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5490, 4385}, +/*h(8074)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {8074, 4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1083_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7538)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7538; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1315_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5362)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5362; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_925_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7410)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7410; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1242_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7666)=0 EVV 0x7B VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() mode64 W1 ZEROING=0 MASK=0 BCRC=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_12_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1542)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1542; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1086_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3590)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_696_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5638)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_306_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7686)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_329_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1798)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_170_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1670)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1244_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3718)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_854_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5766)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_464_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7814)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_488_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1926)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_823_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1606)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1606, 4386}, +/*h(10955)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {10955, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1862)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_750_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(716)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {716, 6084}, +/*h(3910)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3910, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_360_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5958)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5958, 4386}, +/*h(2764)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {2764, 6086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1434_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4812)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {4812, 6088}, +/*h(8006)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8006, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_982_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1734)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1734, 4386}, +/*h(747)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {747, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1299_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1990)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1149_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1574)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1574; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_759_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3622)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_369_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5670)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1443_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7718)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_3_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1830)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1830; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1702)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_161_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1958)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1235_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4006)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_845_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6054)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_455_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8102)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_497_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1638)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_814_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1894)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_655_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1766)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1766, 4386}, +/*h(2753)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2753, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_265_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3814)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3814, 4386}, +/*h(4801)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4801, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1339_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5862)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_949_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7910)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7910, 4386}, +/*h(8897)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8897, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_973_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2022)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1394_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1550)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1550; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1004_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3598)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3598; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_614_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5646)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5646; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_224_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7694)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7694; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_247_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1806)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1806, 4386}, +/*h(2793)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {2793, 6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1321_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3854)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3854, 4386}, +/*h(4841)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4841, 6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_931_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5902)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_541_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7950)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7950, 4386}, +/*h(8937)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8937, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_89_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1678)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1678; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_406_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1934)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_742_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1614)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1614, 4386}, +/*h(4808)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4808, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1059_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1870)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1870; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_900_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1742)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1742; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1217_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1998)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1998; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_827_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4046)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4046; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_437_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6094)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6094; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_47_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8142)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8142; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1068_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1582)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1582; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1385_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1838)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1227_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1710)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1710, 4386}, +/*h(723)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {723, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_80_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1966)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1966; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_415_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1646)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1646, 4386}, +/*h(10995)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {10995, 6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_732_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1902)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1902; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_342_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(756)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {756, 6070}, +/*h(3950)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3950, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1416_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2804)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2804, 6072}, +/*h(5998)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5998, 4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1026_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8046)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {8046, 4386}, +/*h(4852)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {4852, 6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_574_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1774)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_891_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2030)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] not64 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4386} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1313_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1558)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1558; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_923_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3606)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3606; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_533_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5654)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5654; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_143_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7702)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1814)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1240_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3862)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_850_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5910)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5910, 4387}, +/*h(742)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {742, 6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_460_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2790)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {2790, 6072}, +/*h(7958)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7958, 4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_7_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1686)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1081_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3734)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3734, 4387}, +/*h(8902)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {8902, 6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_691_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10950)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10950, 6086}, +/*h(5782)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5782, 4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_301_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7830)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7830, 4387}, +/*h(12998)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {12998, 6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_325_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1942)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1399_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3990)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1009_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6038)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_619_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8086)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8086; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_660_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1622)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1622; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_270_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3670)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3670; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5718)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_954_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7766)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_977_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1878)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_587_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3926)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3926; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_197_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5974)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1271_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8022)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_819_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1750)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1750; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_429_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3798)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3798; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_39_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5846)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1113_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7894)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1136_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2006)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_746_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4054)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_356_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6102)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6102; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1430_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8150)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W0 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4387} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8150; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_917_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1543)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1543; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_527_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3591)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5639)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1211_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7687)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7687; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1799)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1075_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1671)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_295_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1586)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1586, 4394}, +/*h(5767)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5767, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1369_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3634)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3634, 4394}, +/*h(7815)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7815, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1392_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1927)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1002_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3975)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_612_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1842)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1842, 4394}, +/*h(6023)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6023, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_222_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3890)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3890, 4394}, +/*h(8071)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8071, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_264_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10956)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10956, 6086}, +/*h(1607)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1607, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_581_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1863)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_423_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(748)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {748, 6070}, +/*h(1735)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1735, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_740_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1991)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_590_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1575)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1575; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_200_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2026)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {2026, 4390}, +/*h(3623)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3623, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_908_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1831)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_749_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1703)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1066_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1959)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1402_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4833)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4833, 6076}, +/*h(1639)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1639, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_255_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1895)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_96_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2754)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2754, 6087}, +/*h(1767)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1767, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_23_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4071)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4071; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1097_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1938)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1938, 4391}, +/*h(6119)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {6119, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_707_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3986)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3986, 4391}, +/*h(8167)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {8167, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_835_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1551)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1551; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_445_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2002)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {2002, 4391}, +/*h(3599)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3599, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_55_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4050)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4050, 4391}, +/*h(5647)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {5647, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1129_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6098)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {6098, 4391}, +/*h(7695)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {7695, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1152_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2794)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {2794, 6073}, +/*h(1807)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1807, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_762_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4842)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4842, 6076}, +/*h(3855)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3855, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_372_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5903)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_994_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1679)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1679; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1311_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1935)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1935; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_182_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10964)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {10964, 6086}, +/*h(1615)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1615, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1256_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(13012)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {13012, 6088}, +/*h(3663)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {3663, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_866_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5711)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_476_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7759)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_500_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1871)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1871; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_341_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1743)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1743; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_658_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1999)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_509_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1583)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1583; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_826_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1839)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1839; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_667_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1711)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_277_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3759)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5807)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_985_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1967)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1320_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10996)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {10996, 6072}, +/*h(1647)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {1647, 4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_173_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1903)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1247_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3951)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_857_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5999)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5999; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_15_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1775)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1775; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_332_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2031)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() not64 ZEROING=0 MASK=0*/ {4388} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1071_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1815)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1815; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_681_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3863)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3863; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_291_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1730)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1730, 4390}, +/*h(5911)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {5911, 4389}, +/*h(743)=2 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {743, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 5) % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_912_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(6855)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6855, 6089}, +/*h(1687)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {1687, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_522_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3735)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {3735, 4389}, +/*h(8903)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {8903, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((5*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_132_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1602)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1602, 4390}, +/*h(10951)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {10951, 6089}, +/*h(5783)=2 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {5783, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1229_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1943)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1943; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_839_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3991)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3991; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_449_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1858)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1858, 4390}, +/*h(6039)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {6039, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_101_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1623)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1623; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1175_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3671)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3671; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_785_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1538)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1538, 4390}, +/*h(5719)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {5719, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_395_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3586)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3586, 4390}, +/*h(7767)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {7767, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_418_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1879)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1879; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_28_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3927)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3927; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1794)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1794, 4390}, +/*h(5975)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {5975, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_259_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1751)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1333_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3799)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_943_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1666)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1666, 4390}, +/*h(5847)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {5847, 4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_577_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2007)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2007; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_187_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4055)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4055; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6103)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W0 ZEROING=0 MASK=0*/ {4389} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6103; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_5_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5634)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5634; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1079_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7682)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1260_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1922)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_870_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3970)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3970; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_480_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6018)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_90_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8066)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_608_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1986)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_458_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1570)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1570, 4390}, +/*h(5751)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {5751, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_68_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3618)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3618, 4390}, +/*h(7799)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {7799, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1142_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5666)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5666; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_752_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7714)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7714; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_776_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1826)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1826, 4390}, +/*h(6007)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {6007, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_617_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1698)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1698, 4390}, +/*h(5879)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {5879, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_934_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1954)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1954, 4390}, +/*h(6135)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {6135, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1270_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1634)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1634, 4390}, +/*h(5815)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {5815, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_123_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1890)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1890, 4390}, +/*h(6071)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {6071, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1428_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1762)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1762, 4390}, +/*h(5943)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {5943, 4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1355_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4066)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4066; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_965_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6114)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_575_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8162)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8162; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_997_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7690)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7690; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1020_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1802)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1802, 4390}, +/*h(2789)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {2789, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_630_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3850)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3850, 4390}, +/*h(4837)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {4837, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_240_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5898)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5898, 4390}, +/*h(6885)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6885, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1314_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7946)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7946, 4390}, +/*h(8933)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {8933, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_50_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1610)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1610, 4390}, +/*h(10959)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {10959, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1124_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3658)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3658, 4390}, +/*h(13007)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {13007, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_734_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5706)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5706, 4390}, +/*h(15055)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {15055, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_344_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7754)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_526_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1994)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_535_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1706)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3754)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3754; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5802)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5802; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_829_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7850)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7850; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_41_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1898)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1898; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8042)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() not64 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4390} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_621_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1554)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1554; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_231_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3602)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3602; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1305_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5650)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5650; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_915_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7698)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7698; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1233_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2786)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {2786, 6073}, +/*h(7954)=1 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7954, 4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1074_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7826)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7826, 4391}, +/*h(12994)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {12994, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_317_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6034)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6034; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1391_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8082)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_263_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7762)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7762; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_580_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8018)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8018; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_127_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1746)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1746; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1201_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3794)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_811_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5842)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5842; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_421_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7890)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7890; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_739_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8146)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W0 ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4391} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8146; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_986_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1590)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1590; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_596_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3638)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3638; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_206_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5686)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5686; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1280_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7734)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7734; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1304_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1846)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1846; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_914_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3894)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3894; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_524_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5942)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_134_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7990)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1145_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1718)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1718; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_755_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3766)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3766; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_365_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5814)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5814; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1439_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7862)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7862; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1462_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1974)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1974; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1072_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4022)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4022; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_682_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6070)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6070; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_292_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8118)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8118; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_334_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(4848)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {4848, 6076}, +/*h(1654)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1654, 4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1408_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3702)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3702; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1018_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5750)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {5750, 4392}, +/*h(8944)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {8944, 6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_628_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10992)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {10992, 6073}, +/*h(7798)=1 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7798, 4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 3) % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_651_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1910)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_261_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3958)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1335_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6006)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_945_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8054)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8054; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_492_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1782)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {1782, 4392}, +/*h(2769)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {2769, 6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_102_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3830)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {3830, 4392}, +/*h(4817)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {4817, 6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5878)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5878; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_786_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7926)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {7926, 4392}, +/*h(8913)=1 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {8913, 6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_419_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4086)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4086; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_29_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6134)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6134; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1103_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8182)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] mode64 W1 ZEROING=0 MASK=0 FIX_ROUND_LEN128()*/ {4392} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8182; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_427_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1591)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1591; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_37_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3639)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3639; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_744_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1847)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_354_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3895)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_586_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1719)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1719; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3767)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3767; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_903_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1975)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1975; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_513_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4023)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4023; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1655)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1655; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_848_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3703)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3703; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_92_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1911)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1911; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1166_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3959)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3959; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(1783)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 1783; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1007_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(3831)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 3831; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1324_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4087)=0 EVV 0x7B VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() AVX512_ROUND() mode64 W1 ZEROING=0 MASK=0*/ {4393} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4087; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_979_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5682)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5682; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_589_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7730)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7730; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1296_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(5938)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 5938; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_906_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7986)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7986; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_748_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(7858)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {7858, 4394}, +/*h(6871)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6871, 6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1065_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8114)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8114; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1106_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(1650)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {1650, 4394}, +/*h(10999)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {10999, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_716_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(3698)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {3698, 4394}, +/*h(13047)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {13047, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_326_l1(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(5746)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {5746, 4394}, +/*h(15095)=1 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {15095, 6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1400_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7794)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7794; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_254_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8050)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8050; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_95_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(7922)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 7922; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1192_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4082)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4082; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_802_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6130)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6130; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_412_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8178)=0 EVV 0x7B VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() mode64 W1 ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_READER() FIX_ROUND_LEN128()*/ {4394} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8178; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_505_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(740)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 740; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_409_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8932)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8932; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_246_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8948)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8948; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_754_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8934)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8934; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_673_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8942)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8942; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_591_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8950)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {6070} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8950; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1278_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(736)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 736; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1182_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8928)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8928; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1196_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(744)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 744; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1100_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8936)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8936; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1114_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(752)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_63_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8930)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8930; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8946)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8946; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_555_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(753)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 753; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_459_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8945)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1064_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(739)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 739; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_901_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(755)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 755; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_805_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8947)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6071} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_115_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2788)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2788; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_19_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10980)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10980; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1401_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10988)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10988; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_364_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10982)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10982; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_283_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10990)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {6072} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10990; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_888_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2784)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2784; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_792_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10976)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10976; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_806_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2792)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2792; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_710_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10984)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10984; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_724_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2800)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1137_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10978)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10978; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_974_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10994)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10994; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2785)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2785; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_151_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10985)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10985; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_165_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2801)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2801; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_578_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10979)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10979; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_496_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10987)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10987; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_511_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2803)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6073} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2803; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1189_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4836)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4836; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1011_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13036)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13036; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_70_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4838)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4838; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1438_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13030)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13030; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1357_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13038)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {6074} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13038; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_924_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10981)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10981; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_534_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13029)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13029; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_144_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15077)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15077; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1328_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(749)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 749; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1232_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8941)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8941; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_938_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2797)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2797; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_842_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10989)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10989; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_548_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4845)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4845; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_452_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13037)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13037; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_158_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6893)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6893; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_62_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15085)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15085; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1150_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8949)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_856_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2805)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_466_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4853)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_76_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6901)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1269_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10983)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10983; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_879_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13031)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13031; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_489_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15079)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15079; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_210_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(751)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 751; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1284_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2799)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2799; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_894_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4847)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4847; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_504_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6895)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6895; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_32_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8951)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8951; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_422_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6903)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {6075} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6903; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_498_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4832)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4832; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_402_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13024)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13024; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_416_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4840)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4840; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_320_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13032)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13032; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_238_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13040)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13040; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_843_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4834)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4834; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_747_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13026)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13026; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_584_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13042)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13042; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1225_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13033)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13033; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1239_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4849)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4849; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_188_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13027)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13027; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_106_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13035)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13035; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_121_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4851)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {6076} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4851; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_831_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(708)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 708; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_654_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8908)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8908; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_668_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(724)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 724; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1177_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(710)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 710; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_999_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8910)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8910; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1014_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(726)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {6084} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 726; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_140_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(704)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 704; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_44_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8896)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8896; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_58_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(712)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 712; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1441_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(720)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 720; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1345_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8912)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8912; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_486_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(706)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 706; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_308_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8906)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8906; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_226_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8914)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8914; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_882_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(721)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 721; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1390_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(707)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 707; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1309_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(715)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 715; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1213_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8907)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6085} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8907; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_787_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2758)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2758; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_609_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10958)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10958; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_624_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2774)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {6086} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2774; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1214_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2752)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2752; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1118_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10944)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10944; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1132_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2760)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2760; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1051_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2768)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2768; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_955_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10960)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10960; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1382_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10954)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10954; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1300_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10962)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10962; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_559_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10945)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10945; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_573_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2761)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2761; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_396_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10961)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10961; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_904_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10947)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10947; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_919_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2763)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2763; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_741_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10963)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6087} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10963; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_397_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4806)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4806; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_219_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13006)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13006; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_234_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4822)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {6088} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4822; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_176_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8901)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8901; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1346_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2757)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2757; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1250_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10949)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10949; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_956_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4805)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4805; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_860_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12997)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12997; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_566_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6853)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6853; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_470_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15045)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15045; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_190_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(717)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 717; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_94_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8909)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8909; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1264_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2765)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2765; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1168_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10957)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10957; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_874_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4813)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4813; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_778_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13005)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13005; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_484_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6861)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6861; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_388_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15053)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15053; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_13_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8917)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8917; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2773)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2773; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1087_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10965)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10965; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_793_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4821)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4821; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_697_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13013)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13013; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_403_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(6869)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 6869; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_307_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15061)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15061; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_618_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(711)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 711; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_228_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(2759)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 2759; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1302_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4807)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4807; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_358_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8919)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 8919; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1432_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(10967)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 10967; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1042_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13015)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13015; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_652_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(15063)=0 EVV 0x7B V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W0 NOEVSR*/ {6089} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 15063; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_824_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4800)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4800; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_728_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12992)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12992; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_661_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4816)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4816; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_565_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13008)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13008; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_992_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13002)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13002; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_910_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13010)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13010; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_169_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12993)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12993; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_183_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4809)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4809; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_6_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13009)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13009; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_514_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(12995)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 12995; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_529_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(4811)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 4811; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2_351_l1(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(13011)=0 EVV 0x7B V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {6090} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = key - 13011; +if(hidx == 0) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7b_vv2(const xed_decoded_inst_t* d) +{ +typedef xed_uint32_t (*xed_find_func_t)(const xed_decoded_inst_t*); +typedef struct {xed_uint32_t key; xed_find_func_t l2_func;} lu_entry_t; +static const lu_entry_t lu_table[1464] = { +/*h(10946)=0 */ {10946, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_0_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1830)=3 */ {1830, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_3_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5634)=5 */ {5634, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_5_l1}, +/*h(13009)=6 */ {13009, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_6_l1}, +/*h(1686)=7 */ {1686, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_7_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8074)=9 */ {8074, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_9_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1542)=12 */ {1542, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_12_l1}, +/*h(8917)=13 */ {8917, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_13_l1}, +/*h(2762)=14 */ {2762, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_14_l1}, +/*h(1775)=15 */ {1775, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_15_l1}, +/*h(3982)=16 */ {3982, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_16_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7786)=18 */ {7786, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_18_l1}, +/*h(10980)=19 */ {10980, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_19_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1254)=21 */ {1254, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_21_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4071)=23 */ {4071, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_23_l1}, +/*h(1487)=24 */ {1487, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_24_l1}, +/*h(13043)=25 */ {13043, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_25_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7498)=27 */ {7498, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_27_l1}, +/*h(3927)=28 */ {3927, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_28_l1}, +/*h(6134)=29 */ {6134, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_29_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8951)=32 */ {8951, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_32_l1}, +/*h(2796)=33 */ {2796, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_33_l1}, +/*h(5990)=34 */ {5990, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_34_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7210)=36 */ {7210, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_36_l1}, +/*h(3639)=37 */ {3639, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_37_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5846)=39 */ {5846, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_39_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1898)=41 */ {1898, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_41_l1}, +/*h(3495)=42 */ {3495, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_42_l1}, +/*h(5702)=43 */ {5702, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_43_l1}, +/*h(8896)=44 */ {8896, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_44_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5935)=46 */ {5935, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_46_l1}, +/*h(8142)=47 */ {8142, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_47_l1}, +/*h(5558)=48 */ {5558, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_48_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10959)=50 */ {10959, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_50_l1}, +/*h(4804)=51 */ {4804, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_51_l1}, +/*h(5414)=52 */ {5414, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_52_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4050)=55 */ {4050, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_55_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7854)=57 */ {7854, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_57_l1}, +/*h(712)=58 */ {712, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_58_l1}, +/*h(3906)=59 */ {3906, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_59_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5126)=61 */ {5126, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_61_l1}, +/*h(15085)=62 */ {15085, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_62_l1}, +/*h(8930)=63 */ {8930, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_63_l1}, +/*h(2775)=64 */ {2775, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_64_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7566)=66 */ {7566, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_66_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7799)=68 */ {7799, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_68_l1}, +/*h(10993)=69 */ {10993, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_69_l1}, +/*h(4838)=70 */ {4838, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_70_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6058)=73 */ {6058, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_73_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7278)=75 */ {7278, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_75_l1}, +/*h(6901)=76 */ {6901, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_76_l1}, +/*h(3330)=77 */ {3330, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_77_l1}, +/*h(746)=78 */ {746, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_78_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1966)=80 */ {1966, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_80_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5770)=82 */ {5770, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_82_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13001)=87 */ {13001, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_87_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1678)=89 */ {1678, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_89_l1}, +/*h(8066)=90 */ {8066, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_90_l1}, +/*h(5482)=91 */ {5482, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_91_l1}, +/*h(1911)=92 */ {1911, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_92_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8909)=94 */ {8909, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_94_l1}, +/*h(7922)=95 */ {7922, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_95_l1}, +/*h(2754)=96 */ {2754, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_96_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3974)=98 */ {3974, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_98_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7778)=100 */ {7778, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_100_l1}, +/*h(1623)=101 */ {1623, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_101_l1}, +/*h(4817)=102 */ {4817, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_102_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7634)=104 */ {7634, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_104_l1}, +/*h(1479)=105 */ {1479, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_105_l1}, +/*h(13035)=106 */ {13035, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_106_l1}, +/*h(3686)=107 */ {3686, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_107_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(725)=109 */ {725, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_109_l1}, +/*h(3919)=110 */ {3919, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_110_l1}, +/*h(6126)=111 */ {6126, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7346)=113 */ {7346, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_113_l1}, +/*h(8943)=114 */ {8943, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_114_l1}, +/*h(2788)=115 */ {2788, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_115_l1}, +/*h(3398)=116 */ {3398, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_116_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2034)=118 */ {2034, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_118_l1}, +/*h(3631)=119 */ {3631, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_119_l1}, +/*h(5838)=120 */ {5838, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_120_l1}, +/*h(4851)=121 */ {4851, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_121_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6071)=123 */ {6071, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_123_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3110)=125 */ {3110, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_125_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1746)=127 */ {1746, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_127_l1}, +/*h(759)=128 */ {759, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_128_l1}, +/*h(8134)=129 */ {8134, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_129_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10951)=132 */ {10951, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_132_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7990)=134 */ {7990, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_134_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4042)=136 */ {4042, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_136_l1}, +/*h(5639)=137 */ {5639, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_137_l1}, +/*h(13014)=138 */ {13014, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(704)=140 */ {704, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_140_l1}, +/*h(8079)=141 */ {8079, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_141_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7702)=143 */ {7702, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_143_l1}, +/*h(15077)=144 */ {15077, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_144_l1}, +/*h(3754)=145 */ {3754, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_145_l1}, +/*h(2767)=146 */ {2767, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_146_l1}, +/*h(7558)=147 */ {7558, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7791)=150 */ {7791, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_150_l1}, +/*h(10985)=151 */ {10985, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_151_l1}, +/*h(7414)=152 */ {7414, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6050)=154 */ {6050, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7270)=156 */ {7270, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6893)=158 */ {6893, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_158_l1}, +/*h(738)=159 */ {738, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1958)=161 */ {1958, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5762)=163 */ {5762, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2801)=165 */ {2801, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_165_l1}, +/*h(1814)=166 */ {1814, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5618)=168 */ {5618, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_168_l1}, +/*h(12993)=169 */ {12993, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_169_l1}, +/*h(1670)=170 */ {1670, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5474)=172 */ {5474, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_172_l1}, +/*h(1903)=173 */ {1903, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_173_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1526)=175 */ {1526, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_175_l1}, +/*h(8901)=176 */ {8901, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_176_l1}, +/*h(7914)=177 */ {7914, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_177_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1382)=180 */ {1382, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_180_l1}, +/*h(5186)=181 */ {5186, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_181_l1}, +/*h(10964)=182 */ {10964, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_182_l1}, +/*h(4809)=183 */ {4809, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_183_l1}, +/*h(3822)=184 */ {3822, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_184_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7626)=186 */ {7626, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_186_l1}, +/*h(4055)=187 */ {4055, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_187_l1}, +/*h(13027)=188 */ {13027, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_188_l1}, +/*h(1094)=189 */ {1094, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_189_l1}, +/*h(717)=190 */ {717, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_190_l1}, +/*h(3911)=191 */ {3911, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_191_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6118)=193 */ {6118, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_193_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8935)=195 */ {8935, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_195_l1}, +/*h(3767)=196 */ {3767, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_196_l1}, +/*h(5974)=197 */ {5974, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2026)=200 */ {2026, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_200_l1}, +/*h(10998)=201 */ {10998, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_201_l1}, +/*h(4843)=202 */ {4843, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_202_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6063)=205 */ {6063, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_205_l1}, +/*h(5686)=206 */ {5686, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1738)=209 */ {1738, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_209_l1}, +/*h(751)=210 */ {751, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_210_l1}, +/*h(5542)=211 */ {5542, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_211_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5775)=214 */ {5775, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_214_l1}, +/*h(7982)=215 */ {7982, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4034)=218 */ {4034, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_218_l1}, +/*h(13006)=219 */ {13006, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_219_l1}, +/*h(5254)=220 */ {5254, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3890)=222 */ {3890, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_222_l1}, +/*h(5487)=223 */ {5487, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_223_l1}, +/*h(7694)=224 */ {7694, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_224_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8914)=226 */ {8914, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_226_l1}, +/*h(7927)=227 */ {7927, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_227_l1}, +/*h(2759)=228 */ {2759, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_228_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3602)=231 */ {3602, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_231_l1}, +/*h(10977)=232 */ {10977, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_232_l1}, +/*h(7406)=233 */ {7406, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_233_l1}, +/*h(4822)=234 */ {4822, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_234_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3458)=236 */ {3458, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_236_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13040)=238 */ {13040, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_238_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6885)=240 */ {6885, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_240_l1}, +/*h(3314)=241 */ {3314, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_241_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7351)=245 */ {7351, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_245_l1}, +/*h(8948)=246 */ {8948, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_246_l1}, +/*h(2793)=247 */ {2793, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_247_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5610)=249 */ {5610, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_249_l1}, +/*h(2039)=250 */ {2039, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_250_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8050)=254 */ {8050, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_254_l1}, +/*h(1895)=255 */ {1895, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_255_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1518)=257 */ {1518, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_257_l1}, +/*h(7906)=258 */ {7906, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_258_l1}, +/*h(1751)=259 */ {1751, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_259_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3958)=261 */ {3958, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7762)=263 */ {7762, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_263_l1}, +/*h(10956)=264 */ {10956, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_264_l1}, +/*h(4801)=265 */ {4801, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_265_l1}, +/*h(1230)=266 */ {1230, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_266_l1}, +/*h(7618)=267 */ {7618, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_267_l1}, +/*h(4047)=268 */ {4047, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_268_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3670)=270 */ {3670, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_270_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(709)=272 */ {709, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_272_l1}, +/*h(1319)=273 */ {1319, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_273_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3526)=275 */ {3526, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_275_l1}, +/*h(7330)=276 */ {7330, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_276_l1}, +/*h(3759)=277 */ {3759, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_277_l1}, +/*h(2772)=278 */ {2772, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_278_l1}, +/*h(5966)=279 */ {5966, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_279_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2018)=281 */ {2018, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_281_l1}, +/*h(1031)=282 */ {1031, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_282_l1}, +/*h(10990)=283 */ {10990, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_283_l1}, +/*h(4835)=284 */ {4835, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_284_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1874)=286 */ {1874, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_286_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5678)=288 */ {5678, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_288_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(743)=291 */ {743, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_291_l1}, +/*h(8118)=292 */ {8118, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1586)=295 */ {1586, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_295_l1}, +/*h(3183)=296 */ {3183, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_296_l1}, +/*h(2806)=297 */ {2806, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_297_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5623)=300 */ {5623, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_300_l1}, +/*h(12998)=301 */ {12998, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_301_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3882)=304 */ {3882, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_304_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7686)=306 */ {7686, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_306_l1}, +/*h(15061)=307 */ {15061, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_307_l1}, +/*h(8906)=308 */ {8906, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_308_l1}, +/*h(7919)=309 */ {7919, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_309_l1}, +/*h(7542)=310 */ {7542, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_310_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3594)=313 */ {3594, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_313_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4814)=315 */ {4814, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6034)=317 */ {6034, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_317_l1}, +/*h(7631)=318 */ {7631, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_318_l1}, +/*h(7254)=319 */ {7254, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_319_l1}, +/*h(13032)=320 */ {13032, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_320_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(722)=322 */ {722, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_322_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1942)=325 */ {1942, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_325_l1}, +/*h(15095)=326 */ {15095, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_326_l1}, +/*h(8940)=327 */ {8940, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_327_l1}, +/*h(2785)=328 */ {2785, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_328_l1}, +/*h(1798)=329 */ {1798, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5602)=331 */ {5602, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_331_l1}, +/*h(2031)=332 */ {2031, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_332_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4848)=334 */ {4848, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_334_l1}, +/*h(8042)=335 */ {8042, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_335_l1}, +/*h(5458)=336 */ {5458, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_336_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1510)=338 */ {1510, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_338_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5314)=340 */ {5314, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_340_l1}, +/*h(1743)=341 */ {1743, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_341_l1}, +/*h(756)=342 */ {756, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_342_l1}, +/*h(1366)=343 */ {1366, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_343_l1}, +/*h(7754)=344 */ {7754, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_344_l1}, +/*h(10948)=345 */ {10948, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_345_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1222)=347 */ {1222, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4039)=350 */ {4039, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_350_l1}, +/*h(13011)=351 */ {13011, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_351_l1}, +/*h(3662)=352 */ {3662, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_352_l1}, +/*h(7466)=353 */ {7466, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_353_l1}, +/*h(3895)=354 */ {3895, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_354_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6102)=356 */ {6102, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_356_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8919)=358 */ {8919, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_358_l1}, +/*h(3751)=359 */ {3751, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_359_l1}, +/*h(2764)=360 */ {2764, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_360_l1}, +/*h(3374)=361 */ {3374, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_361_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3607)=363 */ {3607, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_363_l1}, +/*h(10982)=364 */ {10982, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_364_l1}, +/*h(5814)=365 */ {5814, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_365_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1866)=368 */ {1866, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_368_l1}, +/*h(5670)=369 */ {5670, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_369_l1}, +/*h(13045)=370 */ {13045, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_370_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5903)=372 */ {5903, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_372_l1}, +/*h(3319)=373 */ {3319, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_373_l1}, +/*h(8110)=374 */ {8110, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1578)=377 */ {1578, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_377_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2798)=379 */ {2798, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_379_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4018)=381 */ {4018, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_381_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7822)=383 */ {7822, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8055)=386 */ {8055, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_386_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15053)=388 */ {15053, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_388_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8898)=390 */ {8898, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_390_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7534)=392 */ {7534, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_392_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3586)=395 */ {3586, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_395_l1}, +/*h(10961)=396 */ {10961, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_396_l1}, +/*h(4806)=397 */ {4806, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6026)=399 */ {6026, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_399_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7246)=401 */ {7246, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_401_l1}, +/*h(13024)=402 */ {13024, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_402_l1}, +/*h(6869)=403 */ {6869, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_403_l1}, +/*h(714)=404 */ {714, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_404_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1934)=406 */ {1934, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15087)=408 */ {15087, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_408_l1}, +/*h(8932)=409 */ {8932, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_409_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8178)=412 */ {8178, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_412_l1}, +/*h(2023)=413 */ {2023, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_413_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10995)=415 */ {10995, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_415_l1}, +/*h(4840)=416 */ {4840, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_416_l1}, +/*h(8034)=417 */ {8034, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_417_l1}, +/*h(1879)=418 */ {1879, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_418_l1}, +/*h(4086)=419 */ {4086, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_419_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7890)=421 */ {7890, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_421_l1}, +/*h(6903)=422 */ {6903, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_422_l1}, +/*h(748)=423 */ {748, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_423_l1}, +/*h(3942)=424 */ {3942, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_424_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7746)=426 */ {7746, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_426_l1}, +/*h(1591)=427 */ {1591, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_427_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3798)=429 */ {3798, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_429_l1}, +/*h(7602)=430 */ {7602, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1447)=432 */ {1447, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_432_l1}, +/*h(13003)=433 */ {13003, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_433_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7458)=435 */ {7458, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_435_l1}, +/*h(3887)=436 */ {3887, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_436_l1}, +/*h(6094)=437 */ {6094, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_437_l1}, +/*h(3510)=438 */ {3510, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_438_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8911)=440 */ {8911, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_440_l1}, +/*h(2756)=441 */ {2756, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_441_l1}, +/*h(3366)=442 */ {3366, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_442_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7170)=444 */ {7170, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_444_l1}, +/*h(2002)=445 */ {2002, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_445_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4819)=447 */ {4819, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_447_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1858)=449 */ {1858, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_449_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3078)=451 */ {3078, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_451_l1}, +/*h(13037)=452 */ {13037, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_452_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(727)=454 */ {727, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_454_l1}, +/*h(8102)=455 */ {8102, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_455_l1}, +/*h(5518)=456 */ {5518, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_456_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5751)=458 */ {5751, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_458_l1}, +/*h(8945)=459 */ {8945, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_459_l1}, +/*h(2790)=460 */ {2790, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_460_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4010)=463 */ {4010, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_463_l1}, +/*h(7814)=464 */ {7814, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_464_l1}, +/*h(5230)=465 */ {5230, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_465_l1}, +/*h(4853)=466 */ {4853, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_466_l1}, +/*h(8047)=467 */ {8047, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_467_l1}, +/*h(5463)=468 */ {5463, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_468_l1}, +/*h(7670)=469 */ {7670, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_469_l1}, +/*h(15045)=470 */ {15045, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_470_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3722)=472 */ {3722, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_472_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7526)=474 */ {7526, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_474_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7759)=476 */ {7759, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_476_l1}, +/*h(10953)=477 */ {10953, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_477_l1}, +/*h(7382)=478 */ {7382, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_478_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6018)=480 */ {6018, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_480_l1}, +/*h(3434)=481 */ {3434, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_481_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7238)=483 */ {7238, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_483_l1}, +/*h(6861)=484 */ {6861, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_484_l1}, +/*h(5874)=485 */ {5874, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_485_l1}, +/*h(706)=486 */ {706, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_486_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1926)=488 */ {1926, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_488_l1}, +/*h(15079)=489 */ {15079, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_489_l1}, +/*h(5730)=490 */ {5730, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_490_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2769)=492 */ {2769, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_492_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8170)=494 */ {8170, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_494_l1}, +/*h(7183)=495 */ {7183, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_495_l1}, +/*h(10987)=496 */ {10987, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_496_l1}, +/*h(1638)=497 */ {1638, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_497_l1}, +/*h(4832)=498 */ {4832, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_498_l1}, +/*h(5442)=499 */ {5442, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_499_l1}, +/*h(1871)=500 */ {1871, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_500_l1}, +/*h(4078)=501 */ {4078, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_501_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7882)=503 */ {7882, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_503_l1}, +/*h(6895)=504 */ {6895, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_504_l1}, +/*h(740)=505 */ {740, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_505_l1}, +/*h(1350)=506 */ {1350, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_506_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5154)=508 */ {5154, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_508_l1}, +/*h(1583)=509 */ {1583, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_509_l1}, +/*h(3790)=510 */ {3790, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_510_l1}, +/*h(2803)=511 */ {2803, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_511_l1}, +/*h(7594)=512 */ {7594, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_512_l1}, +/*h(4023)=513 */ {4023, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_513_l1}, +/*h(12995)=514 */ {12995, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_514_l1}, +/*h(1062)=515 */ {1062, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_515_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3879)=518 */ {3879, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_518_l1}, +/*h(6086)=519 */ {6086, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_519_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7306)=521 */ {7306, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_521_l1}, +/*h(8903)=522 */ {8903, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_522_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5942)=524 */ {5942, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_524_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1994)=526 */ {1994, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_526_l1}, +/*h(3591)=527 */ {3591, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_527_l1}, +/*h(10966)=528 */ {10966, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_528_l1}, +/*h(4811)=529 */ {4811, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_529_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6031)=531 */ {6031, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_531_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5654)=533 */ {5654, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_533_l1}, +/*h(13029)=534 */ {13029, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_534_l1}, +/*h(1706)=535 */ {1706, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_535_l1}, +/*h(719)=536 */ {719, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_536_l1}, +/*h(5510)=537 */ {5510, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_537_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5743)=540 */ {5743, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_540_l1}, +/*h(8937)=541 */ {8937, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_541_l1}, +/*h(5366)=542 */ {5366, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_542_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8183)=544 */ {8183, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_544_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5222)=546 */ {5222, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_546_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4845)=548 */ {4845, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_548_l1}, +/*h(3858)=549 */ {3858, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_549_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7662)=551 */ {7662, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_551_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3714)=553 */ {3714, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_553_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(753)=555 */ {753, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_555_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7751)=558 */ {7751, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_558_l1}, +/*h(10945)=559 */ {10945, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_559_l1}, +/*h(7374)=560 */ {7374, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_560_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7607)=562 */ {7607, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_562_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13008)=565 */ {13008, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_565_l1}, +/*h(6853)=566 */ {6853, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_566_l1}, +/*h(5866)=567 */ {5866, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_567_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3138)=571 */ {3138, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_571_l1}, +/*h(8916)=572 */ {8916, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_572_l1}, +/*h(2761)=573 */ {2761, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_573_l1}, +/*h(1774)=574 */ {1774, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_574_l1}, +/*h(8162)=575 */ {8162, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_575_l1}, +/*h(5578)=576 */ {5578, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_576_l1}, +/*h(2007)=577 */ {2007, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_577_l1}, +/*h(10979)=578 */ {10979, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_578_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8018)=580 */ {8018, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_580_l1}, +/*h(1863)=581 */ {1863, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_581_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4070)=583 */ {4070, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_583_l1}, +/*h(13042)=584 */ {13042, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_584_l1}, +/*h(6887)=585 */ {6887, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_585_l1}, +/*h(1719)=586 */ {1719, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_586_l1}, +/*h(3926)=587 */ {3926, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_587_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7730)=589 */ {7730, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_589_l1}, +/*h(1575)=590 */ {1575, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_590_l1}, +/*h(8950)=591 */ {8950, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_591_l1}, +/*h(2795)=592 */ {2795, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_592_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7586)=594 */ {7586, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_594_l1}, +/*h(4015)=595 */ {4015, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_595_l1}, +/*h(3638)=596 */ {3638, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_596_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7442)=598 */ {7442, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_598_l1}, +/*h(1287)=599 */ {1287, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_599_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3494)=601 */ {3494, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_601_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7298)=603 */ {7298, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_603_l1}, +/*h(3727)=604 */ {3727, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_604_l1}, +/*h(5934)=605 */ {5934, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_605_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1986)=608 */ {1986, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_608_l1}, +/*h(10958)=609 */ {10958, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_609_l1}, +/*h(4803)=610 */ {4803, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_610_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1842)=612 */ {1842, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_612_l1}, +/*h(3439)=613 */ {3439, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_613_l1}, +/*h(5646)=614 */ {5646, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_614_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5879)=617 */ {5879, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_617_l1}, +/*h(711)=618 */ {711, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_618_l1}, +/*h(8086)=619 */ {8086, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_619_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1554)=621 */ {1554, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_621_l1}, +/*h(8929)=622 */ {8929, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_622_l1}, +/*h(7942)=623 */ {7942, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_623_l1}, +/*h(2774)=624 */ {2774, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_624_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8175)=626 */ {8175, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_626_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10992)=628 */ {10992, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_628_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4837)=630 */ {4837, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_630_l1}, +/*h(1266)=631 */ {1266, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_631_l1}, +/*h(7654)=632 */ {7654, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_632_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7887)=635 */ {7887, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_635_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(745)=637 */ {745, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_637_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3562)=639 */ {3562, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_639_l1}, +/*h(5159)=640 */ {5159, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_640_l1}, +/*h(7366)=641 */ {7366, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_641_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6002)=644 */ {6002, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_644_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13000)=646 */ {13000, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_646_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5858)=648 */ {5858, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_648_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1910)=651 */ {1910, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_651_l1}, +/*h(15063)=652 */ {15063, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_652_l1}, +/*h(5714)=653 */ {5714, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_653_l1}, +/*h(8908)=654 */ {8908, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_654_l1}, +/*h(2753)=655 */ {2753, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_655_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5570)=657 */ {5570, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_657_l1}, +/*h(1999)=658 */ {1999, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_658_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1622)=660 */ {1622, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_660_l1}, +/*h(4816)=661 */ {4816, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_661_l1}, +/*h(8010)=662 */ {8010, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_662_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1478)=665 */ {1478, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_665_l1}, +/*h(13034)=666 */ {13034, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_666_l1}, +/*h(1711)=667 */ {1711, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_667_l1}, +/*h(724)=668 */ {724, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_668_l1}, +/*h(3918)=669 */ {3918, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_669_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7722)=671 */ {7722, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_671_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8942)=673 */ {8942, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_673_l1}, +/*h(2787)=674 */ {2787, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_674_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4007)=676 */ {4007, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_676_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3630)=678 */ {3630, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_678_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4850)=680 */ {4850, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_680_l1}, +/*h(3863)=681 */ {3863, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_681_l1}, +/*h(6070)=682 */ {6070, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_682_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3719)=685 */ {3719, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_685_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(758)=687 */ {758, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_687_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3575)=690 */ {3575, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_690_l1}, +/*h(10950)=691 */ {10950, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_691_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1834)=694 */ {1834, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_694_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5638)=696 */ {5638, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_696_l1}, +/*h(13013)=697 */ {13013, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_697_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5871)=699 */ {5871, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_699_l1}, +/*h(8078)=700 */ {8078, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_700_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1546)=703 */ {1546, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_703_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2766)=705 */ {2766, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_705_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3986)=707 */ {3986, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_707_l1}, +/*h(5583)=708 */ {5583, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_708_l1}, +/*h(7790)=709 */ {7790, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_709_l1}, +/*h(10984)=710 */ {10984, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_710_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3842)=712 */ {3842, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_712_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13047)=716 */ {13047, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_716_l1}, +/*h(7879)=717 */ {7879, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_717_l1}, +/*h(737)=718 */ {737, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_718_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7735)=721 */ {7735, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_721_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2800)=724 */ {2800, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_724_l1}, +/*h(5994)=725 */ {5994, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_725_l1}, +/*h(7591)=726 */ {7591, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_726_l1}, +/*h(7214)=727 */ {7214, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_727_l1}, +/*h(12992)=728 */ {12992, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_728_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3266)=730 */ {3266, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_730_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1902)=732 */ {1902, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_732_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15055)=734 */ {15055, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_734_l1}, +/*h(8900)=735 */ {8900, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_735_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8146)=739 */ {8146, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_739_l1}, +/*h(1991)=740 */ {1991, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_740_l1}, +/*h(10963)=741 */ {10963, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_741_l1}, +/*h(4808)=742 */ {4808, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_742_l1}, +/*h(8002)=743 */ {8002, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_743_l1}, +/*h(1847)=744 */ {1847, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_744_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4054)=746 */ {4054, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_746_l1}, +/*h(13026)=747 */ {13026, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_747_l1}, +/*h(6871)=748 */ {6871, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_748_l1}, +/*h(1703)=749 */ {1703, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_749_l1}, +/*h(716)=750 */ {716, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_750_l1}, +/*h(1326)=751 */ {1326, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_751_l1}, +/*h(7714)=752 */ {7714, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_752_l1}, +/*h(1559)=753 */ {1559, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_753_l1}, +/*h(8934)=754 */ {8934, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_754_l1}, +/*h(3766)=755 */ {3766, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_755_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7570)=757 */ {7570, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_757_l1}, +/*h(1415)=758 */ {1415, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_758_l1}, +/*h(3622)=759 */ {3622, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_759_l1}, +/*h(10997)=760 */ {10997, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_760_l1}, +/*h(7426)=761 */ {7426, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_761_l1}, +/*h(4842)=762 */ {4842, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_762_l1}, +/*h(1271)=763 */ {1271, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_763_l1}, +/*h(6062)=764 */ {6062, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_764_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7282)=766 */ {7282, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_766_l1}, +/*h(1127)=767 */ {1127, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_767_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(750)=769 */ {750, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_769_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1970)=771 */ {1970, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_771_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5774)=773 */ {5774, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_773_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6007)=776 */ {6007, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_776_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13005)=778 */ {13005, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_778_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1682)=780 */ {1682, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_780_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8070)=782 */ {8070, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_782_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1538)=785 */ {1538, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_785_l1}, +/*h(8913)=786 */ {8913, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_786_l1}, +/*h(2758)=787 */ {2758, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_787_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3978)=789 */ {3978, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_789_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7782)=791 */ {7782, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_791_l1}, +/*h(10976)=792 */ {10976, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_792_l1}, +/*h(4821)=793 */ {4821, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_793_l1}, +/*h(8015)=794 */ {8015, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_794_l1}, +/*h(7638)=795 */ {7638, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_795_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13039)=798 */ {13039, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_798_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7494)=800 */ {7494, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_800_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6130)=802 */ {6130, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_802_l1}, +/*h(7727)=803 */ {7727, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_803_l1}, +/*h(7350)=804 */ {7350, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_804_l1}, +/*h(8947)=805 */ {8947, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_805_l1}, +/*h(2792)=806 */ {2792, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_806_l1}, +/*h(5986)=807 */ {5986, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_807_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2038)=809 */ {2038, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_809_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5842)=811 */ {5842, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_811_l1}, +/*h(4855)=812 */ {4855, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_812_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1894)=814 */ {1894, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_814_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(15047)=816 */ {15047, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_816_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1750)=819 */ {1750, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_819_l1}, +/*h(8138)=820 */ {8138, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_820_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10955)=823 */ {10955, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_823_l1}, +/*h(4800)=824 */ {4800, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_824_l1}, +/*h(5410)=825 */ {5410, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_825_l1}, +/*h(1839)=826 */ {1839, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_826_l1}, +/*h(4046)=827 */ {4046, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_827_l1}, +/*h(1462)=828 */ {1462, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_828_l1}, +/*h(7850)=829 */ {7850, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_829_l1}, +/*h(6863)=830 */ {6863, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_830_l1}, +/*h(708)=831 */ {708, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_831_l1}, +/*h(1318)=832 */ {1318, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_832_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5122)=834 */ {5122, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_834_l1}, +/*h(1551)=835 */ {1551, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_835_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2771)=837 */ {2771, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_837_l1}, +/*h(7562)=838 */ {7562, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_838_l1}, +/*h(3991)=839 */ {3991, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_839_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1030)=841 */ {1030, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_841_l1}, +/*h(10989)=842 */ {10989, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_842_l1}, +/*h(4834)=843 */ {4834, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_843_l1}, +/*h(3847)=844 */ {3847, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_844_l1}, +/*h(6054)=845 */ {6054, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_845_l1}, +/*h(3470)=846 */ {3470, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_846_l1}, +/*h(7274)=847 */ {7274, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_847_l1}, +/*h(3703)=848 */ {3703, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_848_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(742)=850 */ {742, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_850_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1962)=853 */ {1962, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_853_l1}, +/*h(5766)=854 */ {5766, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_854_l1}, +/*h(3182)=855 */ {3182, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_855_l1}, +/*h(2805)=856 */ {2805, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_856_l1}, +/*h(5999)=857 */ {5999, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_857_l1}, +/*h(3415)=858 */ {3415, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_858_l1}, +/*h(5622)=859 */ {5622, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_859_l1}, +/*h(12997)=860 */ {12997, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_860_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1674)=862 */ {1674, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_862_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5478)=864 */ {5478, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_864_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5711)=866 */ {5711, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_866_l1}, +/*h(8905)=867 */ {8905, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_867_l1}, +/*h(7918)=868 */ {7918, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_868_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3970)=870 */ {3970, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_870_l1}, +/*h(8151)=871 */ {8151, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_871_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5190)=873 */ {5190, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_873_l1}, +/*h(4813)=874 */ {4813, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_874_l1}, +/*h(3826)=875 */ {3826, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_875_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7630)=877 */ {7630, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_877_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13031)=879 */ {13031, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_879_l1}, +/*h(7863)=880 */ {7863, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_880_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(721)=882 */ {721, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_882_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6122)=884 */ {6122, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_884_l1}, +/*h(5135)=885 */ {5135, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_885_l1}, +/*h(8939)=886 */ {8939, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_886_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2784)=888 */ {2784, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_888_l1}, +/*h(3394)=889 */ {3394, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_889_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2030)=891 */ {2030, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_891_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5834)=893 */ {5834, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_893_l1}, +/*h(4847)=894 */ {4847, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_894_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7287)=898 */ {7287, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_898_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1742)=900 */ {1742, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_900_l1}, +/*h(755)=901 */ {755, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_901_l1}, +/*h(8130)=902 */ {8130, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_902_l1}, +/*h(1975)=903 */ {1975, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_903_l1}, +/*h(10947)=904 */ {10947, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_904_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7986)=906 */ {7986, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_906_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1831)=908 */ {1831, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_908_l1}, +/*h(4038)=909 */ {4038, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_909_l1}, +/*h(13010)=910 */ {13010, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_910_l1}, +/*h(7842)=911 */ {7842, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_911_l1}, +/*h(6855)=912 */ {6855, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_912_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3894)=914 */ {3894, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_914_l1}, +/*h(7698)=915 */ {7698, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_915_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1543)=917 */ {1543, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_917_l1}, +/*h(8918)=918 */ {8918, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_918_l1}, +/*h(2763)=919 */ {2763, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_919_l1}, +/*h(7554)=920 */ {7554, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_920_l1}, +/*h(3983)=921 */ {3983, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_921_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3606)=923 */ {3606, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_923_l1}, +/*h(10981)=924 */ {10981, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_924_l1}, +/*h(7410)=925 */ {7410, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_925_l1}, +/*h(1255)=926 */ {1255, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_926_l1}, +/*h(3462)=927 */ {3462, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_927_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7266)=929 */ {7266, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_929_l1}, +/*h(13044)=930 */ {13044, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_930_l1}, +/*h(5902)=931 */ {5902, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_931_l1}, +/*h(3318)=932 */ {3318, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_932_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6135)=934 */ {6135, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_934_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3174)=936 */ {3174, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_936_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2797)=938 */ {2797, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_938_l1}, +/*h(1810)=939 */ {1810, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_939_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5614)=941 */ {5614, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_941_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1666)=943 */ {1666, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_943_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8054)=945 */ {8054, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_945_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5703)=948 */ {5703, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_948_l1}, +/*h(8897)=949 */ {8897, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_949_l1}, +/*h(5326)=950 */ {5326, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_950_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8143)=952 */ {8143, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_952_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7766)=954 */ {7766, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_954_l1}, +/*h(10960)=955 */ {10960, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_955_l1}, +/*h(4805)=956 */ {4805, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_956_l1}, +/*h(3818)=957 */ {3818, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_957_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7622)=959 */ {7622, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_959_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7855)=961 */ {7855, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_961_l1}, +/*h(5271)=962 */ {5271, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_962_l1}, +/*h(713)=963 */ {713, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_963_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6114)=965 */ {6114, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_965_l1}, +/*h(3530)=966 */ {3530, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_966_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8931)=968 */ {8931, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_968_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5970)=970 */ {5970, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_970_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7190)=972 */ {7190, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_972_l1}, +/*h(2022)=973 */ {2022, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_973_l1}, +/*h(10994)=974 */ {10994, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_974_l1}, +/*h(4839)=975 */ {4839, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_975_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1878)=977 */ {1878, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_977_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5682)=979 */ {5682, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_979_l1}, +/*h(7279)=980 */ {7279, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_980_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(747)=982 */ {747, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_982_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5538)=984 */ {5538, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_984_l1}, +/*h(1967)=985 */ {1967, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_985_l1}, +/*h(1590)=986 */ {1590, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_986_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7978)=988 */ {7978, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_988_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1446)=991 */ {1446, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_991_l1}, +/*h(13002)=992 */ {13002, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_992_l1}, +/*h(5250)=993 */ {5250, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_993_l1}, +/*h(1679)=994 */ {1679, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_994_l1}, +/*h(3886)=995 */ {3886, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_995_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7690)=997 */ {7690, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_997_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8910)=999 */ {8910, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_999_l1}, +/*h(2755)=1000 */ {2755, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1000_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3975)=1002 */ {3975, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1002_l1}, +/*h(1391)=1003 */ {1391, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1003_l1}, +/*h(3598)=1004 */ {3598, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1004_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4818)=1006 */ {4818, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1006_l1}, +/*h(3831)=1007 */ {3831, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1007_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6038)=1009 */ {6038, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1009_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13036)=1011 */ {13036, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1011_l1}, +/*h(3687)=1012 */ {3687, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1012_l1}, +/*h(5894)=1013 */ {5894, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1013_l1}, +/*h(726)=1014 */ {726, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1014_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6127)=1016 */ {6127, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1016_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8944)=1018 */ {8944, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1018_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2789)=1020 */ {2789, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1020_l1}, +/*h(3399)=1021 */ {3399, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1021_l1}, +/*h(5606)=1022 */ {5606, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1022_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5839)=1025 */ {5839, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1025_l1}, +/*h(4852)=1026 */ {4852, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1026_l1}, +/*h(5462)=1027 */ {5462, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1027_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1514)=1029 */ {1514, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1029_l1}, +/*h(3111)=1030 */ {3111, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1030_l1}, +/*h(5318)=1031 */ {5318, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1031_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3954)=1034 */ {3954, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1034_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10952)=1036 */ {10952, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1036_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7991)=1038 */ {7991, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1038_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13015)=1042 */ {13015, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1042_l1}, +/*h(3666)=1043 */ {3666, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1043_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(705)=1045 */ {705, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1045_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7703)=1047 */ {7703, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1047_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2768)=1051 */ {2768, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1051_l1}, +/*h(5962)=1052 */ {5962, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1052_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7182)=1054 */ {7182, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1054_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10986)=1056 */ {10986, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1056_l1}, +/*h(7415)=1057 */ {7415, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1057_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1870)=1059 */ {1870, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1059_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5674)=1061 */ {5674, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1061_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(739)=1064 */ {739, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1064_l1}, +/*h(8114)=1065 */ {8114, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1065_l1}, +/*h(1959)=1066 */ {1959, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1066_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1582)=1068 */ {1582, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1068_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2802)=1070 */ {2802, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1070_l1}, +/*h(1815)=1071 */ {1815, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1071_l1}, +/*h(4022)=1072 */ {4022, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1072_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12994)=1074 */ {12994, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1074_l1}, +/*h(1671)=1075 */ {1671, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1075_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3878)=1077 */ {3878, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1077_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7682)=1079 */ {7682, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1079_l1}, +/*h(1527)=1080 */ {1527, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1080_l1}, +/*h(8902)=1081 */ {8902, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1081_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7538)=1083 */ {7538, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1083_l1}, +/*h(1383)=1084 */ {1383, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1084_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3590)=1086 */ {3590, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1086_l1}, +/*h(10965)=1087 */ {10965, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1087_l1}, +/*h(4810)=1088 */ {4810, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1088_l1}, +/*h(3823)=1089 */ {3823, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1089_l1}, +/*h(6030)=1090 */ {6030, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1090_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7250)=1092 */ {7250, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1092_l1}, +/*h(13028)=1093 */ {13028, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1093_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(718)=1095 */ {718, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1095_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1938)=1097 */ {1938, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1097_l1}, +/*h(3535)=1098 */ {3535, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1098_l1}, +/*h(5742)=1099 */ {5742, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1099_l1}, +/*h(8936)=1100 */ {8936, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1100_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1794)=1102 */ {1794, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1102_l1}, +/*h(8182)=1103 */ {8182, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1103_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10999)=1106 */ {10999, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1106_l1}, +/*h(4844)=1107 */ {4844, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1107_l1}, +/*h(8038)=1108 */ {8038, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1108_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5687)=1111 */ {5687, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1111_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7894)=1113 */ {7894, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1113_l1}, +/*h(752)=1114 */ {752, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1114_l1}, +/*h(3946)=1115 */ {3946, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1115_l1}, +/*h(5543)=1116 */ {5543, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1116_l1}, +/*h(7750)=1117 */ {7750, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1117_l1}, +/*h(10944)=1118 */ {10944, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1118_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7983)=1120 */ {7983, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1120_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7606)=1122 */ {7606, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1122_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13007)=1124 */ {13007, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1124_l1}, +/*h(1074)=1125 */ {1074, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1125_l1}, +/*h(7462)=1126 */ {7462, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1126_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6098)=1129 */ {6098, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1129_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8915)=1131 */ {8915, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1131_l1}, +/*h(2760)=1132 */ {2760, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1132_l1}, +/*h(5954)=1133 */ {5954, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1133_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7174)=1135 */ {7174, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1135_l1}, +/*h(2006)=1136 */ {2006, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1136_l1}, +/*h(10978)=1137 */ {10978, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1137_l1}, +/*h(4823)=1138 */ {4823, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1138_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1862)=1140 */ {1862, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1140_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5666)=1142 */ {5666, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1142_l1}, +/*h(13041)=1143 */ {13041, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1143_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1718)=1145 */ {1718, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1145_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8106)=1147 */ {8106, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1147_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1574)=1149 */ {1574, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1149_l1}, +/*h(8949)=1150 */ {8949, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1150_l1}, +/*h(5378)=1151 */ {5378, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1151_l1}, +/*h(2794)=1152 */ {2794, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1152_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4014)=1154 */ {4014, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1154_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7818)=1156 */ {7818, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1156_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1286)=1159 */ {1286, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1159_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1519)=1161 */ {1519, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1161_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3726)=1163 */ {3726, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1163_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7530)=1165 */ {7530, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1165_l1}, +/*h(3959)=1166 */ {3959, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1166_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10957)=1168 */ {10957, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1168_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4802)=1170 */ {4802, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1170_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6022)=1172 */ {6022, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1172_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7242)=1174 */ {7242, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1174_l1}, +/*h(3671)=1175 */ {3671, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1175_l1}, +/*h(5878)=1176 */ {5878, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1176_l1}, +/*h(710)=1177 */ {710, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1177_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1930)=1179 */ {1930, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1179_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5734)=1181 */ {5734, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1181_l1}, +/*h(8928)=1182 */ {8928, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1182_l1}, +/*h(2773)=1183 */ {2773, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1183_l1}, +/*h(5967)=1184 */ {5967, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1184_l1}, +/*h(8174)=1185 */ {8174, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1185_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10991)=1188 */ {10991, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1188_l1}, +/*h(4836)=1189 */ {4836, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1189_l1}, +/*h(5446)=1190 */ {5446, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1190_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4082)=1192 */ {4082, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1192_l1}, +/*h(5679)=1193 */ {5679, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1193_l1}, +/*h(7886)=1194 */ {7886, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1194_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(744)=1196 */ {744, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1196_l1}, +/*h(8119)=1197 */ {8119, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1197_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5158)=1199 */ {5158, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1199_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3794)=1201 */ {3794, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1201_l1}, +/*h(2807)=1202 */ {2807, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1202_l1}, +/*h(7598)=1203 */ {7598, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1203_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12999)=1206 */ {12999, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1206_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6090)=1210 */ {6090, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1210_l1}, +/*h(7687)=1211 */ {7687, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1211_l1}, +/*h(7310)=1212 */ {7310, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1212_l1}, +/*h(8907)=1213 */ {8907, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1213_l1}, +/*h(2752)=1214 */ {2752, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1214_l1}, +/*h(7543)=1215 */ {7543, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1215_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1998)=1217 */ {1998, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1217_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5802)=1219 */ {5802, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1219_l1}, +/*h(4815)=1220 */ {4815, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1220_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3074)=1224 */ {3074, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1224_l1}, +/*h(13033)=1225 */ {13033, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1225_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(723)=1227 */ {723, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1227_l1}, +/*h(8098)=1228 */ {8098, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1228_l1}, +/*h(1943)=1229 */ {1943, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1229_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8941)=1232 */ {8941, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1232_l1}, +/*h(2786)=1233 */ {2786, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1233_l1}, +/*h(1799)=1234 */ {1799, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1234_l1}, +/*h(4006)=1235 */ {4006, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1235_l1}, +/*h(1422)=1236 */ {1422, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1236_l1}, +/*h(7810)=1237 */ {7810, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1237_l1}, +/*h(1655)=1238 */ {1655, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1238_l1}, +/*h(4849)=1239 */ {4849, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1239_l1}, +/*h(3862)=1240 */ {3862, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1240_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7666)=1242 */ {7666, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1242_l1}, +/*h(1511)=1243 */ {1511, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1243_l1}, +/*h(3718)=1244 */ {3718, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1244_l1}, +/*h(1134)=1245 */ {1134, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1245_l1}, +/*h(757)=1246 */ {757, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1246_l1}, +/*h(3951)=1247 */ {3951, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1247_l1}, +/*h(1367)=1248 */ {1367, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1248_l1}, +/*h(3574)=1249 */ {3574, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1249_l1}, +/*h(10949)=1250 */ {10949, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1250_l1}, +/*h(7378)=1251 */ {7378, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1251_l1}, +/*h(1223)=1252 */ {1223, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1252_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3430)=1254 */ {3430, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1254_l1}, +/*h(7234)=1255 */ {7234, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1255_l1}, +/*h(13012)=1256 */ {13012, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1256_l1}, +/*h(1079)=1257 */ {1079, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1257_l1}, +/*h(5870)=1258 */ {5870, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1258_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1922)=1260 */ {1922, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1260_l1}, +/*h(6103)=1261 */ {6103, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1261_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3142)=1263 */ {3142, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1263_l1}, +/*h(2765)=1264 */ {2765, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1264_l1}, +/*h(1778)=1265 */ {1778, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1265_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8166)=1267 */ {8166, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1267_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10983)=1269 */ {10983, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1269_l1}, +/*h(5815)=1270 */ {5815, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1270_l1}, +/*h(8022)=1271 */ {8022, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1271_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4074)=1274 */ {4074, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1274_l1}, +/*h(13046)=1275 */ {13046, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1275_l1}, +/*h(7878)=1276 */ {7878, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1276_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(736)=1278 */ {736, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1278_l1}, +/*h(8111)=1279 */ {8111, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1279_l1}, +/*h(7734)=1280 */ {7734, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1280_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3786)=1283 */ {3786, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1283_l1}, +/*h(2799)=1284 */ {2799, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1284_l1}, +/*h(7590)=1285 */ {7590, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1285_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7823)=1288 */ {7823, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1288_l1}, +/*h(7446)=1289 */ {7446, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1289_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6082)=1292 */ {6082, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1292_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8899)=1294 */ {8899, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1294_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5938)=1296 */ {5938, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1296_l1}, +/*h(7535)=1297 */ {7535, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1297_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1990)=1299 */ {1990, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1299_l1}, +/*h(10962)=1300 */ {10962, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1300_l1}, +/*h(5794)=1301 */ {5794, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1301_l1}, +/*h(4807)=1302 */ {4807, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1302_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1846)=1304 */ {1846, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1304_l1}, +/*h(5650)=1305 */ {5650, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1305_l1}, +/*h(13025)=1306 */ {13025, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1306_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1702)=1308 */ {1702, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1308_l1}, +/*h(715)=1309 */ {715, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1309_l1}, +/*h(5506)=1310 */ {5506, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1310_l1}, +/*h(1935)=1311 */ {1935, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1311_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1558)=1313 */ {1558, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1313_l1}, +/*h(8933)=1314 */ {8933, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1314_l1}, +/*h(5362)=1315 */ {5362, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1315_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1414)=1317 */ {1414, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1317_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5218)=1319 */ {5218, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1319_l1}, +/*h(10996)=1320 */ {10996, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1320_l1}, +/*h(4841)=1321 */ {4841, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1321_l1}, +/*h(1270)=1322 */ {1270, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1322_l1}, +/*h(7658)=1323 */ {7658, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1323_l1}, +/*h(4087)=1324 */ {4087, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1324_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1126)=1326 */ {1126, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1326_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(749)=1328 */ {749, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1328_l1}, +/*h(3943)=1329 */ {3943, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1329_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3566)=1331 */ {3566, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1331_l1}, +/*h(7370)=1332 */ {7370, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1332_l1}, +/*h(3799)=1333 */ {3799, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1333_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6006)=1335 */ {6006, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1335_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(13004)=1338 */ {13004, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1338_l1}, +/*h(5862)=1339 */ {5862, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1339_l1}, +/*h(3278)=1340 */ {3278, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1340_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6095)=1342 */ {6095, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1342_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5718)=1344 */ {5718, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1344_l1}, +/*h(8912)=1345 */ {8912, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1345_l1}, +/*h(2757)=1346 */ {2757, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1346_l1}, +/*h(1770)=1347 */ {1770, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1347_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5574)=1349 */ {5574, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1349_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5807)=1351 */ {5807, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1351_l1}, +/*h(4820)=1352 */ {4820, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1352_l1}, +/*h(8014)=1353 */ {8014, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1353_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4066)=1355 */ {4066, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1355_l1}, +/*h(1482)=1356 */ {1482, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1356_l1}, +/*h(13038)=1357 */ {13038, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1357_l1}, +/*h(5286)=1358 */ {5286, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1358_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3922)=1360 */ {3922, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1360_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7726)=1362 */ {7726, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1362_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8946)=1364 */ {8946, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1364_l1}, +/*h(2791)=1365 */ {2791, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1365_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3634)=1369 */ {3634, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1369_l1}, +/*h(5231)=1370 */ {5231, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1370_l1}, +/*h(4854)=1371 */ {4854, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1371_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7671)=1374 */ {7671, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1374_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5930)=1378 */ {5930, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1378_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10954)=1382 */ {10954, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1382_l1}, +/*h(3202)=1383 */ {3202, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1383_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1838)=1385 */ {1838, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1385_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5642)=1387 */ {5642, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1387_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(707)=1390 */ {707, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1390_l1}, +/*h(8082)=1391 */ {8082, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1391_l1}, +/*h(1927)=1392 */ {1927, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1392_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1550)=1394 */ {1550, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1394_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(2770)=1396 */ {2770, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1396_l1}, +/*h(1783)=1397 */ {1783, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1397_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3990)=1399 */ {3990, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1399_l1}, +/*h(7794)=1400 */ {7794, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1400_l1}, +/*h(10988)=1401 */ {10988, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1401_l1}, +/*h(4833)=1402 */ {4833, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1402_l1}, +/*h(3846)=1403 */ {3846, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1403_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7650)=1405 */ {7650, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1405_l1}, +/*h(4079)=1406 */ {4079, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1406_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3702)=1408 */ {3702, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1408_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(741)=1410 */ {741, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1410_l1}, +/*h(1351)=1411 */ {1351, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1411_l1}, +/*h(3558)=1412 */ {3558, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1412_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7362)=1414 */ {7362, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1414_l1}, +/*h(3791)=1415 */ {3791, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1415_l1}, +/*h(2804)=1416 */ {2804, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1416_l1}, +/*h(3414)=1417 */ {3414, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1417_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(12996)=1419 */ {12996, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1419_l1}, +/*h(1063)=1420 */ {1063, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1420_l1}, +/*h(3270)=1421 */ {3270, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1421_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1906)=1424 */ {1906, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1424_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8904)=1426 */ {8904, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1426_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5943)=1428 */ {5943, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1428_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8150)=1430 */ {8150, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1430_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(10967)=1432 */ {10967, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1432_l1}, +/*h(1618)=1433 */ {1618, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1433_l1}, +/*h(4812)=1434 */ {4812, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1434_l1}, +/*h(5422)=1435 */ {5422, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1435_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(5655)=1437 */ {5655, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1437_l1}, +/*h(13030)=1438 */ {13030, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1438_l1}, +/*h(7862)=1439 */ {7862, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1439_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(720)=1441 */ {720, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1441_l1}, +/*h(3914)=1442 */ {3914, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1442_l1}, +/*h(7718)=1443 */ {7718, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1443_l1}, +/*h(15093)=1444 */ {15093, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1444_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(8938)=1446 */ {8938, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1446_l1}, +/*h(5367)=1447 */ {5367, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1447_l1}, +/*h(7574)=1448 */ {7574, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1448_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(3626)=1451 */ {3626, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1451_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(4846)=1453 */ {4846, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1453_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(6066)=1455 */ {6066, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1455_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(7286)=1457 */ {7286, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1457_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(754)=1460 */ {754, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1460_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +/*h(1974)=1462 */ {1974, xed3_phash_find_mapevex_map1_opcode0x7b_vv2_1462_l1}, +/*empty slot2 */ {0, xed_phash_invalid_const}, +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 1464ULL, u.s.hi32); +return (*lu_table[hidx].l2_func)(d); +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7e_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(754)=0 EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_GPR_WRITER_STORE()*/ {754, 5002}, +/*h(706)=1 EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {706, 4921}, +/*h(1778)=2 EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {1778, 5004}, +/*h(758)=3 EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 mode64 NOEVSR ZEROING=0 MASK=0*/ {758, 5001}, +/*h(710)=4 EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {710, 4919}, +/*h(1782)=5 EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {1782, 5003}, +/*h(738)=6 EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {738, 4921}, +/*h(714)=7 EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {714, 4921}, +/*h(1762)=8 EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {1762, 5004}, +/*h(742)=9 EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {742, 4919}, +/*h(718)=10 EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {718, 4919}, +/*h(1766)=11 EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {1766, 5003}, +/*h(746)=12 EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 not64 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {746, 4921}, +/*h(722)=13 EVV 0x7E V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_GPR_WRITER_STORE()*/ {722, 4922}, +/*h(1770)=14 EVV 0x7E VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {1770, 5004}, +/*h(750)=15 EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 not64 NOEVSR ZEROING=0 MASK=0*/ {750, 4919}, +/*h(726)=16 EVV 0x7E V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 mode64 W0 NOEVSR ZEROING=0 MASK=0*/ {726, 4920}, +/*h(1774)=17 EVV 0x7E VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {1774, 5003} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((19*key % 73) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0x7f_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[108] = { +/*h(1370)=0 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1370, 4939}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(412)=4 EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {412, 6207}, +/*empty slot1 */ {0,0}, +/*h(344)=6 EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {344, 4940}, +/*h(474)=7 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 4963}, +/*empty slot1 */ {0,0}, +/*h(1502)=9 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1502, 4975}, +/*empty slot1 */ {0,0}, +/*h(1434)=11 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1434, 6218}, +/*h(414)=12 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {414, 6206}, +/*empty slot1 */ {0,0}, +/*h(346)=14 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {346, 4939}, +/*h(476)=15 EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {476, 4976}, +/*h(1374)=16 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1374, 4951}, +/*h(408)=17 EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {408, 6219}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(348)=22 EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {348, 4952}, +/*h(478)=23 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {478, 4975}, +/*empty slot1 */ {0,0}, +/*h(410)=25 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {410, 6218}, +/*empty slot1 */ {0,0}, +/*h(1438)=27 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {1438, 6206}, +/*empty slot1 */ {0,0}, +/*h(1754)=29 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1754, 4955}, +/*h(350)=30 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4951}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(728)=35 EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {728, 4956}, +/*h(1242)=36 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1242, 4959}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=42 EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {216, 4960}, +/*h(730)=43 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 4955}, +/*empty slot1 */ {0,0}, +/*h(1758)=45 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1758, 4967}, +/*empty slot1 */ {0,0}, +/*h(1690)=47 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1690, 6222}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(218)=50 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 4959}, +/*h(732)=51 EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {732, 4968}, +/*h(1246)=52 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1246, 4971}, +/*h(664)=53 EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {664, 6223}, +/*h(1178)=54 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1178, 6214}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(220)=58 EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {220, 4972}, +/*h(734)=59 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {734, 4967}, +/*h(152)=60 EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {152, 6215}, +/*h(666)=61 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {666, 6222}, +/*empty slot1 */ {0,0}, +/*h(1694)=63 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1694, 6210}, +/*empty slot1 */ {0,0}, +/*h(1626)=65 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {1626, 4931}, +/*h(222)=66 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {222, 4971}, +/*empty slot1 */ {0,0}, +/*h(154)=68 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {154, 6214}, +/*h(668)=69 EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {668, 6211}, +/*h(1182)=70 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1182, 6202}, +/*h(600)=71 EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {600, 4932}, +/*h(1114)=72 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {1114, 4935}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(156)=76 EVV 0x7F VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_16_BITS() NELEM_FULLMEM()*/ {156, 6203}, +/*h(670)=77 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {670, 6210}, +/*h(88)=78 EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {88, 4936}, +/*h(602)=79 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {602, 4931}, +/*empty slot1 */ {0,0}, +/*h(1630)=81 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {1630, 4943}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(158)=84 EVV 0x7F VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {158, 6202}, +/*empty slot1 */ {0,0}, +/*h(90)=86 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {90, 4935}, +/*h(604)=87 EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {604, 4944}, +/*h(1118)=88 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {1118, 4947}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(92)=94 EVV 0x7F V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 ESIZE_64_BITS() NELEM_FULLMEM()*/ {92, 4948}, +/*h(606)=95 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4943}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1498)=101 EVV 0x7F VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {1498, 4963}, +/*h(94)=102 EVV 0x7F V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4947}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(472)=107 EVV 0x7F VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {472, 4964} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((4*key % 137) % 108); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc2_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[100] = { +/*h(0)=0 EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {0, 4146}, +/*h(46)=1 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 ZEROING=0 UIMM8()*/ {46, 4140}, +/*h(54)=2 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8()*/ {54, 4149}, +/*h(24)=3 EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {24, 4154}, +/*h(32)=4 EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {32, 4148}, +/*h(78)=5 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 ZEROING=0 UIMM8()*/ {78, 4135}, +/*h(86)=6 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8()*/ {86, 4149}, +/*h(56)=7 EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {56, 4154}, +/*h(64)=8 EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {64, 4144}, +/*empty slot1 */ {0,0}, +/*h(118)=10 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8()*/ {118, 4149}, +/*h(88)=11 EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {88, 4154}, +/*empty slot1 */ {0,0}, +/*h(15)=13 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8()*/ {15, 4136}, +/*h(23)=14 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8()*/ {23, 4150}, +/*h(120)=15 EVV 0xC2 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_SCALAR()*/ {120, 4154}, +/*h(1)=16 EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {1, 4146}, +/*h(47)=17 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8()*/ {47, 4136}, +/*h(55)=18 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8()*/ {55, 4150}, +/*empty slot1 */ {0,0}, +/*h(33)=20 EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {33, 4148}, +/*h(79)=21 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8()*/ {79, 4136}, +/*h(87)=22 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8()*/ {87, 4150}, +/*empty slot1 */ {0,0}, +/*h(65)=24 EVV 0xC2 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ZEROING=0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {65, 4144}, +/*h(111)=25 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 ZEROING=0 UIMM8()*/ {111, 4136}, +/*h(119)=26 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W1 ZEROING=0 UIMM8()*/ {119, 4150}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2)=32 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 ZEROING=0 UIMM8()*/ {2, 4145}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(26)=35 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8()*/ {26, 4152}, +/*h(34)=36 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 ZEROING=0 UIMM8()*/ {34, 4147}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(58)=39 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8()*/ {58, 4152}, +/*h(66)=40 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 ZEROING=0 UIMM8()*/ {66, 4142}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(90)=43 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8()*/ {90, 4152}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(122)=47 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W0 ZEROING=0 UIMM8()*/ {122, 4152}, +/*h(3)=48 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {3, 4143}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(27)=51 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {27, 4153}, +/*h(35)=52 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {35, 4143}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(59)=55 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {59, 4153}, +/*h(67)=56 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {67, 4143}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(91)=59 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {91, 4153}, +/*h(99)=60 EVV 0xC2 VNP V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W0 ZEROING=0 UIMM8()*/ {99, 4143}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(123)=63 EVV 0xC2 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN128() SAE() W0 ZEROING=0 UIMM8()*/ {123, 4153}, +/*empty slot1 */ {0,0}, +/*h(12)=65 EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 4139}, +/*h(20)=66 EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {20, 4151}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(44)=69 EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 4141}, +/*h(52)=70 EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {52, 4151}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(76)=73 EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 4137}, +/*h(84)=74 EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {84, 4151}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(116)=78 EVV 0xC2 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_SCALAR()*/ {116, 4151}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(13)=81 EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 4139}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(45)=85 EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 4141}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(77)=89 EVV 0xC2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ZEROING=0 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 4137}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(14)=97 EVV 0xC2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 ZEROING=0 UIMM8()*/ {14, 4138}, +/*h(22)=98 EVV 0xC2 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] W1 ZEROING=0 UIMM8()*/ {22, 4149}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(d); +hidx = ((16*key % 127) % 100); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(10)=0 EVV 0xC4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 UIMM8() ESIZE_16_BITS() NELEM_GPR_READER_WORD()*/ {10, 6443}, +/*h(14)=1 EVV 0xC4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0 UIMM8()*/ {14, 6442} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc5_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(742)=0 EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64*/ {742, 6432}, +/*h(750)=1 EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64*/ {750, 6432}, +/*h(726)=2 EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() mode64 EVEXRR_ONE*/ {726, 6433}, +/*h(718)=3 EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64*/ {718, 6432}, +/*h(710)=4 EVV 0xC5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 NOEVSR ZEROING=0 MASK=0 UIMM8() not64*/ {710, 6432} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = ((6*key % 7) % 5); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xc6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(0)=0 EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {0, 5927}, +/*h(14)=1 EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 UIMM8()*/ {14, 5920}, +/*h(66)=2 EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 UIMM8()*/ {66, 5924}, +/*h(77)=3 EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {77, 5919}, +/*h(32)=4 EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {32, 5929}, +/*h(46)=5 EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 UIMM8()*/ {46, 5922}, +/*h(1)=6 EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {1, 5927}, +/*h(12)=7 EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {12, 5921}, +/*h(64)=8 EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {64, 5925}, +/*h(78)=9 EVV 0xC6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 UIMM8()*/ {78, 5918}, +/*h(33)=10 EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {33, 5929}, +/*h(44)=11 EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {44, 5923}, +/*h(2)=12 EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 UIMM8()*/ {2, 5926}, +/*h(13)=13 EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {13, 5921}, +/*h(65)=14 EVV 0xC6 VNP V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 UIMM8() ESIZE_32_BITS() NELEM_FULL()*/ {65, 5925}, +/*h(76)=15 EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {76, 5919}, +/*h(34)=16 EVV 0xC6 VNP V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 UIMM8()*/ {34, 5928}, +/*h(45)=17 EVV 0xC6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 UIMM8() ESIZE_64_BITS() NELEM_FULL()*/ {45, 5923} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((6*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd1_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6670}, +/*h(4)=1 EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()*/ {4, 6667}, +/*h(38)=2 EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6674}, +/*h(20)=3 EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()*/ {20, 6671}, +/*h(6)=4 EVV 0xD1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6666}, +/*h(36)=5 EVV 0xD1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()*/ {36, 6675} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd2_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(42)=0 EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5706}, +/*h(8)=1 EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {8, 5703}, +/*h(72)=2 EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {72, 5699}, +/*h(10)=3 EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5702}, +/*h(74)=4 EVV 0xD2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5698}, +/*h(40)=5 EVV 0xD2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {40, 5707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd3_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(14)=0 EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5714}, +/*h(46)=1 EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5718}, +/*h(78)=2 EVV 0xD3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5710}, +/*h(12)=3 EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {12, 5715}, +/*h(44)=4 EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {44, 5719}, +/*h(76)=5 EVV 0xD3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {76, 5711} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5090}, +/*h(46)=1 EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5093}, +/*h(12)=2 EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5092}, +/*h(77)=3 EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5090}, +/*h(13)=4 EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5092}, +/*h(78)=5 EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5089}, +/*h(44)=6 EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5094}, +/*h(14)=7 EVV 0xD4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5091}, +/*h(45)=8 EVV 0xD4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5094} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd5_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6584}, +/*h(4)=1 EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6583}, +/*h(38)=2 EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6586}, +/*h(20)=3 EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6585}, +/*h(6)=4 EVV 0xD5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6582}, +/*h(36)=5 EVV 0xD5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6587} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(190)=0 EVV 0xD6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR ZEROING=0 MASK=0*/ {190, 5005}, +/*h(186)=1 EVV 0xD6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 NOEVSR ZEROING=0 MASK=0 ESIZE_64_BITS() NELEM_SCALAR()*/ {186, 5006} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6698}, +/*h(4)=1 EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6697}, +/*h(38)=2 EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6700}, +/*h(20)=3 EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6699}, +/*h(6)=4 EVV 0xD8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6696}, +/*h(36)=5 EVV 0xD8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6701} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xd9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6704}, +/*h(4)=1 EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6703}, +/*h(38)=2 EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6706}, +/*h(20)=3 EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6705}, +/*h(6)=4 EVV 0xD9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6702}, +/*h(36)=5 EVV 0xD9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6707} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xda_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6494}, +/*h(4)=1 EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6493}, +/*h(38)=2 EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6496}, +/*h(20)=3 EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6495}, +/*h(6)=4 EVV 0xDA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6492}, +/*h(36)=5 EVV 0xDA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6497} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5096}, +/*h(76)=1 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5114}, +/*h(8)=2 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5098}, +/*h(12)=3 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5116}, +/*h(41)=4 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5100}, +/*h(45)=5 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5118}, +/*h(74)=6 EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5095}, +/*h(78)=7 EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5113}, +/*h(10)=8 EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5097}, +/*h(14)=9 EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5115}, +/*h(40)=10 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5100}, +/*h(44)=11 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5118}, +/*h(73)=12 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5096}, +/*h(77)=13 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5114}, +/*h(9)=14 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5098}, +/*h(13)=15 EVV 0xDB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5116}, +/*h(42)=16 EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5099}, +/*h(46)=17 EVV 0xDB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5117} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6292}, +/*h(4)=1 EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6291}, +/*h(38)=2 EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6294}, +/*h(20)=3 EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6293}, +/*h(6)=4 EVV 0xDC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6290}, +/*h(36)=5 EVV 0xDC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6295} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6298}, +/*h(4)=1 EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6297}, +/*h(38)=2 EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6300}, +/*h(20)=3 EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6299}, +/*h(6)=4 EVV 0xDD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6296}, +/*h(36)=5 EVV 0xDD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6301} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xde_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6470}, +/*h(4)=1 EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6469}, +/*h(38)=2 EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6472}, +/*h(20)=3 EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6471}, +/*h(6)=4 EVV 0xDE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6468}, +/*h(36)=5 EVV 0xDE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6473} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xdf_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5102}, +/*h(76)=1 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5108}, +/*h(8)=2 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5104}, +/*h(12)=3 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5110}, +/*h(41)=4 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5106}, +/*h(45)=5 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5112}, +/*h(74)=6 EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5101}, +/*h(78)=7 EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5107}, +/*h(10)=8 EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5103}, +/*h(14)=9 EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5109}, +/*h(40)=10 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5106}, +/*h(44)=11 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5112}, +/*h(73)=12 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5102}, +/*h(77)=13 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5108}, +/*h(9)=14 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5104}, +/*h(13)=15 EVV 0xDF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5110}, +/*h(42)=16 EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5105}, +/*h(46)=17 EVV 0xDF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5111} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe0_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6316}, +/*h(4)=1 EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6315}, +/*h(38)=2 EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6318}, +/*h(20)=3 EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6317}, +/*h(6)=4 EVV 0xE0 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6314}, +/*h(36)=5 EVV 0xE0 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6319} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe1_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6646}, +/*h(4)=1 EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()*/ {4, 6643}, +/*h(38)=2 EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6650}, +/*h(20)=3 EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()*/ {20, 6647}, +/*h(6)=4 EVV 0xE1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6642}, +/*h(36)=5 EVV 0xE1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()*/ {36, 6651} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe2_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(46)=0 EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5682}, +/*h(72)=1 EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {72, 5663}, +/*h(42)=2 EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5670}, +/*h(78)=3 EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5674}, +/*h(12)=4 EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {12, 5679}, +/*h(74)=5 EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5662}, +/*h(8)=6 EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {8, 5667}, +/*h(44)=7 EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {44, 5683}, +/*h(14)=8 EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5678}, +/*h(40)=9 EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {40, 5671}, +/*h(76)=10 EVV 0xE2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {76, 5675}, +/*h(10)=11 EVV 0xE2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5666} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 23) % 12); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe3_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6322}, +/*h(4)=1 EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6321}, +/*h(38)=2 EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6324}, +/*h(20)=3 EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6323}, +/*h(6)=4 EVV 0xE3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6320}, +/*h(36)=5 EVV 0xE3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6325} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6566}, +/*h(4)=1 EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6565}, +/*h(38)=2 EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6568}, +/*h(20)=3 EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6567}, +/*h(6)=4 EVV 0xE4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6564}, +/*h(36)=5 EVV 0xE4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6569} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe5_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6572}, +/*h(4)=1 EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6571}, +/*h(38)=2 EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6574}, +/*h(20)=3 EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6573}, +/*h(6)=4 EVV 0xE5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6570}, +/*h(36)=5 EVV 0xE5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6575} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[104] = { +/*h(218)=0 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0 NOEVSR*/ {218, 4176}, +/*h(477)=1 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {477, 6101}, +/*h(95)=2 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {95, 4302}, +/*h(668)=3 EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {668, 4189}, +/*h(927)=4 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {927, 4188}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(219)=8 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {219, 4174}, +/*h(478)=9 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {478, 6100}, +/*empty slot1 */ {0,0}, +/*h(669)=11 EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {669, 4189}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(220)=16 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {220, 6099}, +/*h(479)=17 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {479, 6103}, +/*empty slot1 */ {0,0}, +/*h(670)=19 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {670, 4187}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(221)=24 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {221, 6099}, +/*empty slot1 */ {0,0}, +/*h(412)=26 EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {412, 4193}, +/*h(671)=27 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {671, 4188}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(222)=32 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {222, 6098}, +/*empty slot1 */ {0,0}, +/*h(413)=34 EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {413, 4193}, +/*empty slot1 */ {0,0}, +/*h(604)=36 EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {604, 4303}, +/*h(863)=37 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {863, 4302}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(223)=40 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {223, 6103}, +/*empty slot1 */ {0,0}, +/*h(414)=42 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {414, 4192}, +/*empty slot1 */ {0,0}, +/*h(605)=44 EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {605, 4303}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(728)=47 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {728, 4175}, +/*h(987)=48 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {987, 4174}, +/*h(156)=49 EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {156, 4191}, +/*h(415)=50 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {415, 4188}, +/*empty slot1 */ {0,0}, +/*h(606)=52 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {606, 4301}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(729)=55 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {729, 4175}, +/*empty slot1 */ {0,0}, +/*h(157)=57 EVV 0xE6 VF2 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {157, 4191}, +/*empty slot1 */ {0,0}, +/*h(348)=59 EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {348, 4307}, +/*h(607)=60 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {607, 4302}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(730)=63 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0 NOEVSR*/ {730, 4173}, +/*empty slot1 */ {0,0}, +/*h(158)=65 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {158, 4190}, +/*empty slot1 */ {0,0}, +/*h(349)=67 EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {349, 4307}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(472)=70 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {472, 4179}, +/*h(731)=71 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {731, 4174}, +/*empty slot1 */ {0,0}, +/*h(159)=73 EVV 0xE6 VF2 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND() W1 NOEVSR*/ {159, 4188}, +/*empty slot1 */ {0,0}, +/*h(350)=75 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1 NOEVSR*/ {350, 4306}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(473)=78 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {473, 4179}, +/*h(732)=79 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {732, 6104}, +/*h(991)=80 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {991, 6103}, +/*empty slot1 */ {0,0}, +/*h(92)=82 EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {92, 4305}, +/*h(351)=83 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() SAE() W1 NOEVSR*/ {351, 4302}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(474)=86 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0 NOEVSR*/ {474, 4178}, +/*h(733)=87 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {733, 6104}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(93)=90 EVV 0xE6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {93, 4305}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(216)=93 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {216, 4177}, +/*h(475)=94 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W0 NOEVSR FIX_ROUND_LEN512()*/ {475, 4174}, +/*h(734)=95 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1 NOEVSR*/ {734, 6102}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(94)=98 EVV 0xE6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1 NOEVSR*/ {94, 4304}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(217)=101 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 NOEVSR ESIZE_32_BITS() NELEM_HALF()*/ {217, 4177}, +/*h(476)=102 EVV 0xE6 VF3 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 NOEVSR ESIZE_64_BITS() NELEM_FULL()*/ {476, 6101}, +/*h(735)=103 EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1 NOEVSR FIX_ROUND_LEN512() AVX512_ROUND()*/ {735, 6103} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(d); +hidx = ((8*key % 109) % 104); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe7_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(178)=0 EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {178, 4988}, +/*h(690)=1 EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {690, 4989}, +/*h(1202)=2 EVV 0xE7 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 NOEVSR ZEROING=0 MASK=0 ESIZE_32_BITS() NELEM_FULLMEM()*/ {1202, 4987} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6686}, +/*h(4)=1 EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6685}, +/*h(38)=2 EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6688}, +/*h(20)=3 EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6687}, +/*h(6)=4 EVV 0xE8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6684}, +/*h(36)=5 EVV 0xE8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6689} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xe9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6692}, +/*h(4)=1 EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6691}, +/*h(38)=2 EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6694}, +/*h(20)=3 EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6693}, +/*h(6)=4 EVV 0xE9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6690}, +/*h(36)=5 EVV 0xE9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6695} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xea_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6488}, +/*h(4)=1 EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6487}, +/*h(38)=2 EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6490}, +/*h(20)=3 EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6489}, +/*h(6)=4 EVV 0xEA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6486}, +/*h(36)=5 EVV 0xEA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6491} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xeb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5549}, +/*h(76)=1 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5555}, +/*h(8)=2 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5551}, +/*h(12)=3 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5557}, +/*h(41)=4 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5553}, +/*h(45)=5 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5559}, +/*h(74)=6 EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5548}, +/*h(78)=7 EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5554}, +/*h(10)=8 EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5550}, +/*h(14)=9 EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5556}, +/*h(40)=10 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5553}, +/*h(44)=11 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5559}, +/*h(73)=12 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5549}, +/*h(77)=13 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5555}, +/*h(9)=14 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5551}, +/*h(13)=15 EVV 0xEB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5557}, +/*h(42)=16 EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5552}, +/*h(46)=17 EVV 0xEB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5558} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xec_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6280}, +/*h(4)=1 EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6279}, +/*h(38)=2 EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6282}, +/*h(20)=3 EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6281}, +/*h(6)=4 EVV 0xEC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6278}, +/*h(36)=5 EVV 0xEC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6283} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xed_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6286}, +/*h(4)=1 EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6285}, +/*h(38)=2 EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6288}, +/*h(20)=3 EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6287}, +/*h(6)=4 EVV 0xED V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6284}, +/*h(36)=5 EVV 0xED V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6289} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xee_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6464}, +/*h(4)=1 EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6463}, +/*h(38)=2 EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6466}, +/*h(20)=3 EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6465}, +/*h(6)=4 EVV 0xEE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6462}, +/*h(36)=5 EVV 0xEE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6467} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xef_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*h(72)=0 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5807}, +/*h(76)=1 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5813}, +/*h(8)=2 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5809}, +/*h(12)=3 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5815}, +/*h(41)=4 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5811}, +/*h(45)=5 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5817}, +/*h(74)=6 EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5806}, +/*h(78)=7 EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5812}, +/*h(10)=8 EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5808}, +/*h(14)=9 EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5814}, +/*h(40)=10 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5811}, +/*h(44)=11 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5817}, +/*h(73)=12 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5807}, +/*h(77)=13 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5813}, +/*h(9)=14 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5809}, +/*h(13)=15 EVV 0xEF V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5815}, +/*h(42)=16 EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5810}, +/*h(46)=17 EVV 0xEF V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5816} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 47) % 18); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf1_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6628}, +/*h(4)=1 EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_MEM128()*/ {4, 6625}, +/*h(38)=2 EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6632}, +/*h(20)=3 EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_MEM128()*/ {20, 6629}, +/*h(6)=4 EVV 0xF1 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6624}, +/*h(36)=5 EVV 0xF1 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_MEM128()*/ {36, 6633} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf2_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(42)=0 EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5634}, +/*h(8)=1 EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {8, 5631}, +/*h(72)=2 EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {72, 5627}, +/*h(10)=3 EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5630}, +/*h(74)=4 EVV 0xF2 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5626}, +/*h(40)=5 EVV 0xF2 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W0 ESIZE_32_BITS() NELEM_MEM128()*/ {40, 5635} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((8*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf3_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(14)=0 EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5642}, +/*h(46)=1 EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5646}, +/*h(78)=2 EVV 0xF3 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5638}, +/*h(12)=3 EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {12, 5643}, +/*h(44)=4 EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {44, 5647}, +/*h(76)=5 EVV 0xF3 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 W1 ESIZE_64_BITS() NELEM_MEM128()*/ {76, 5639} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((9*key % 7) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf4_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5543}, +/*h(46)=1 EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5546}, +/*h(12)=2 EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5545}, +/*h(77)=3 EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5543}, +/*h(13)=4 EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5545}, +/*h(78)=5 EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5542}, +/*h(44)=6 EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5547}, +/*h(14)=7 EVV 0xF4 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5544}, +/*h(45)=8 EVV 0xF4 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5547} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf5_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6452}, +/*h(4)=1 EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6451}, +/*h(38)=2 EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6454}, +/*h(20)=3 EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6453}, +/*h(6)=4 EVV 0xF5 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6450}, +/*h(36)=5 EVV 0xF5 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6455} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf6_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*empty slot1 */ {0,0}, +/*h(10)=1 EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {10, 6589}, +/*h(78)=2 EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 ZEROING=0 MASK=0*/ {78, 6592}, +/*empty slot1 */ {0,0}, +/*h(46)=4 EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 ZEROING=0 MASK=0*/ {46, 6590}, +/*empty slot1 */ {0,0}, +/*h(14)=6 EVV 0xF6 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 ZEROING=0 MASK=0*/ {14, 6588}, +/*h(74)=7 EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {74, 6593}, +/*empty slot1 */ {0,0}, +/*h(42)=9 EVV 0xF6 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ZEROING=0 MASK=0 ESIZE_8_BITS() NELEM_FULLMEM()*/ {42, 6591} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf8_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6680}, +/*h(4)=1 EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6679}, +/*h(38)=2 EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6682}, +/*h(20)=3 EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6681}, +/*h(6)=4 EVV 0xF8 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6678}, +/*h(36)=5 EVV 0xF8 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6683} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xf9_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6710}, +/*h(4)=1 EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6709}, +/*h(38)=2 EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6712}, +/*h(20)=3 EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6711}, +/*h(6)=4 EVV 0xF9 V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6708}, +/*h(36)=5 EVV 0xF9 V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6713} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfa_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5735}, +/*h(10)=3 EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5736}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5739}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5735}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5737}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5739}, +/*h(74)=13 EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5734}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0xFA V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5737}, +/*h(42)=17 EVV 0xFA V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5738} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfb_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(76)=0 EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {76, 5741}, +/*h(46)=1 EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W1*/ {46, 5744}, +/*h(12)=2 EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {12, 5743}, +/*h(77)=3 EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W1 ESIZE_64_BITS() NELEM_FULL()*/ {77, 5741}, +/*h(13)=4 EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W1 ESIZE_64_BITS() NELEM_FULL()*/ {13, 5743}, +/*h(78)=5 EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W1*/ {78, 5740}, +/*h(44)=6 EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {44, 5745}, +/*h(14)=7 EVV 0xFB V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W1*/ {14, 5742}, +/*h(45)=8 EVV 0xFB V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W1 ESIZE_64_BITS() NELEM_FULL()*/ {45, 5745} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = ((12*key % 19) % 9); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfc_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6274}, +/*h(4)=1 EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_8_BITS() NELEM_FULLMEM()*/ {4, 6273}, +/*h(38)=2 EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6276}, +/*h(20)=3 EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_8_BITS() NELEM_FULLMEM()*/ {20, 6275}, +/*h(6)=4 EVV 0xFC V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6272}, +/*h(36)=5 EVV 0xFC V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_8_BITS() NELEM_FULLMEM()*/ {36, 6277} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfd_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(22)=0 EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256*/ {22, 6304}, +/*h(4)=1 EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL128 ESIZE_16_BITS() NELEM_FULLMEM()*/ {4, 6303}, +/*h(38)=2 EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512*/ {38, 6306}, +/*h(20)=3 EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL256 ESIZE_16_BITS() NELEM_FULLMEM()*/ {20, 6305}, +/*h(6)=4 EVV 0xFD V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128*/ {6, 6302}, +/*h(36)=5 EVV 0xFD V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] BCRC=0 MODRM() VL512 ESIZE_16_BITS() NELEM_FULLMEM()*/ {36, 6307} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(d); +hidx = ((5*key % 13) % 6); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapevex_map1_opcode0xfe_vv2(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[18] = { +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(73)=2 EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {73, 5084}, +/*h(10)=3 EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL128 W0*/ {10, 5085}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(41)=6 EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {41, 5088}, +/*empty slot1 */ {0,0}, +/*h(72)=8 EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL512 W0 ESIZE_32_BITS() NELEM_FULL()*/ {72, 5084}, +/*empty slot1 */ {0,0}, +/*h(9)=10 EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {9, 5086}, +/*empty slot1 */ {0,0}, +/*h(40)=12 EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL256 W0 ESIZE_32_BITS() NELEM_FULL()*/ {40, 5088}, +/*h(74)=13 EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL512 W0*/ {74, 5083}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(8)=16 EVV 0xFE V66 V0F MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() VL128 W0 ESIZE_32_BITS() NELEM_FULL()*/ {8, 5086}, +/*h(42)=17 EVV 0xFE V66 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn] VL256 W0*/ {42, 5087} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 18ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash-vv3.h b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv3.h new file mode 100644 index 0000000..4f8f896 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash-vv3.h @@ -0,0 +1,1389 @@ +/// @file include-private/xed3-phash-vv3.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_VV3_H) +# define INCLUDE_PRIVATE_XED3_PHASH_VV3_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-operand-lu.h" +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x85_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x86_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x87_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x8e_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x8f_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x95_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x96_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x97_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x9e_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x9f_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xa2_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xa3_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xa6_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xb6_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc0_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc1_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc2_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc3_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xcc_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xcd_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xce_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xcf_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xec_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xed_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xee_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xef_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x1_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x2_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x12_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x80_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x81_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x82_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x83_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x90_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x91_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x92_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x93_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x94_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x95_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x96_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x97_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x98_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x99_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x9a_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x9b_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc1_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc2_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc3_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc6_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc7_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xcb_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd1_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd2_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd3_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd6_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd7_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xdb_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xe1_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xe2_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xe3_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xopA_opcode0x10_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xopA_opcode0x12_vv3(const xed_decoded_inst_t* d); + +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x85_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x85 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2190}, +/*h(1)=1 XOPV 0x85 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2191} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x86_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x86 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2192}, +/*h(1)=1 XOPV 0x86 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2193} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x87_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x87 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2194}, +/*h(1)=1 XOPV 0x87 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2195} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x8e_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x8E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2242}, +/*h(1)=1 XOPV 0x8E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2243} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x8f_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x8F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2244}, +/*h(1)=1 XOPV 0x8F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2245} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x95_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x95 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2196}, +/*h(1)=1 XOPV 0x95 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2197} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x96_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x96 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2198}, +/*h(1)=1 XOPV 0x96 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2199} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x97_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x97 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2200}, +/*h(1)=1 XOPV 0x97 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2201} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x9e_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x9E VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2246}, +/*h(1)=1 XOPV 0x9E VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2247} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0x9f_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0x9F VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2248}, +/*h(1)=1 XOPV 0x9F VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2249} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xa2_vv3(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[14] = { +/*h(0)=0 XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {0, 2202}, +/*h(18)=1 XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {18, 2208}, +/*empty slot1 */ {0,0}, +/*h(2)=3 XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2, 2204}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(17)=7 XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {17, 2207}, +/*h(1)=8 XOPV 0xA2 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {1, 2203}, +/*empty slot1 */ {0,0}, +/*h(19)=10 XOPV 0xA2 VNP W1 VL256 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {19, 2209}, +/*h(3)=11 XOPV 0xA2 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {3, 2205}, +/*h(16)=12 XOPV 0xA2 VNP W0 VL256 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {16, 2206}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 14ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xa3_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2210}, +/*h(1)=1 XOPV 0xA3 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2211}, +/*h(2)=2 XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2212}, +/*h(3)=3 XOPV 0xA3 VNP W1 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2213} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xa6_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2214}, +/*h(1)=1 XOPV 0xA6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2215} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xb6_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() SE_IMM8()*/ {2216}, +/*h(1)=1 XOPV 0xB6 VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] SE_IMM8()*/ {2217} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc0_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2218}, +/*h(13)=1 XOPV 0xC0 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2219} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc1_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2224}, +/*h(13)=1 XOPV 0xC1 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2225} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc2_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2230}, +/*h(13)=1 XOPV 0xC2 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2231} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xc3_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2236}, +/*h(13)=1 XOPV 0xC3 VNP W0 VL128 NOVSR XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2237} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xcc_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xCC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2250}, +/*h(1)=1 XOPV 0xCC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2251} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xcd_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xCD VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2252}, +/*h(1)=1 XOPV 0xCD VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2253} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xce_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xCE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2254}, +/*h(1)=1 XOPV 0xCE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2255} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xcf_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xCF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2256}, +/*h(1)=1 XOPV 0xCF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2257} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xec_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xEC VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2258}, +/*h(1)=1 XOPV 0xEC VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2259} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xed_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xED VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2260}, +/*h(1)=1 XOPV 0xED VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2261} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xee_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xEE VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2262}, +/*h(1)=1 XOPV 0xEE VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2263} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop8_opcode0xef_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 XOPV 0xEF VNP W0 VL128 XMAP8 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM8()*/ {2264}, +/*h(1)=1 XOPV 0xEF VNP W0 VL128 XMAP8 MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM8()*/ {2265} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x1_vv3(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[55] = { +/*h(34)=0 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {34, 2356}, +/*h(13)=1 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {13, 2347}, +/*empty slot1 */ {0,0}, +/*h(26)=3 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {26, 2352}, +/*h(60)=4 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {60, 2369}, +/*empty slot1 */ {0,0}, +/*h(18)=6 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {18, 2348}, +/*h(52)=7 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {52, 2365}, +/*empty slot1 */ {0,0}, +/*h(10)=9 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {10, 2344}, +/*h(44)=10 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {44, 2361}, +/*empty slot1 */ {0,0}, +/*h(57)=12 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {57, 2370}, +/*h(36)=13 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {36, 2357}, +/*empty slot1 */ {0,0}, +/*h(49)=15 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {49, 2366}, +/*h(28)=16 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {28, 2353}, +/*empty slot1 */ {0,0}, +/*h(41)=18 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {41, 2362}, +/*h(20)=19 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {20, 2349}, +/*empty slot1 */ {0,0}, +/*h(33)=21 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {33, 2358}, +/*h(12)=22 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {12, 2345}, +/*empty slot1 */ {0,0}, +/*h(25)=24 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {25, 2354}, +/*h(59)=25 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {59, 2370}, +/*empty slot1 */ {0,0}, +/*h(17)=27 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {17, 2350}, +/*h(51)=28 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {51, 2366}, +/*empty slot1 */ {0,0}, +/*h(9)=30 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {9, 2346}, +/*h(43)=31 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {43, 2362}, +/*empty slot1 */ {0,0}, +/*h(56)=33 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {56, 2368}, +/*h(35)=34 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {35, 2358}, +/*empty slot1 */ {0,0}, +/*h(48)=36 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {48, 2364}, +/*h(27)=37 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {27, 2354}, +/*h(61)=38 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]*/ {61, 2371}, +/*h(40)=39 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {40, 2360}, +/*h(19)=40 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {19, 2350}, +/*h(53)=41 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {53, 2367}, +/*h(32)=42 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MODRM()*/ {32, 2356}, +/*h(11)=43 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {11, 2346}, +/*h(45)=44 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]*/ {45, 2363}, +/*h(24)=45 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MODRM()*/ {24, 2352}, +/*h(58)=46 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MODRM()*/ {58, 2368}, +/*h(37)=47 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]*/ {37, 2359}, +/*h(16)=48 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MODRM()*/ {16, 2348}, +/*h(50)=49 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {50, 2364}, +/*h(29)=50 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]*/ {29, 2355}, +/*h(8)=51 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {8, 2344}, +/*h(42)=52 XOPV 0x01 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MODRM()*/ {42, 2360}, +/*h(21)=53 XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]*/ {21, 2351}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REG_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 55ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x2_vv3(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(13)=0 XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {13, 2375}, +/*empty slot1 */ {0,0}, +/*h(52)=2 XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {52, 2377}, +/*h(10)=3 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {10, 2372}, +/*h(49)=4 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {49, 2378}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(12)=7 XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {12, 2373}, +/*h(51)=8 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {51, 2378}, +/*h(9)=9 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {9, 2374}, +/*empty slot1 */ {0,0}, +/*h(48)=11 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {48, 2376}, +/*h(53)=12 XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]*/ {53, 2379}, +/*h(11)=13 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {11, 2374}, +/*empty slot1 */ {0,0}, +/*h(50)=15 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MODRM()*/ {50, 2376}, +/*h(8)=16 XOPV 0x02 VNP not64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM()*/ {8, 2372} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_REG_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 17ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x12_vv3(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(49)=0 XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]*/ {49, 2380}, +/*h(51)=1 XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]*/ {51, 2381} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x80_vv3(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(13)=0 XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2267}, +/*h(12)=1 XOPV 0x80 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2266}, +/*h(77)=2 XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {77, 2269}, +/*h(76)=3 XOPV 0x80 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {76, 2268} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x81_vv3(const xed_decoded_inst_t* d) +{ +typedef struct {xed_uint32_t key; xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(13)=0 XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {13, 2271}, +/*h(12)=1 XOPV 0x81 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {12, 2270}, +/*h(77)=2 XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {77, 2273}, +/*h(76)=3 XOPV 0x81 VNP W0 VL256 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {76, 2272} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x82_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2274}, +/*h(13)=1 XOPV 0x82 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2275} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x83_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2276}, +/*h(13)=1 XOPV 0x83 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2277} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x90_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x90 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2220}, +/*h(1)=1 XOPV 0x90 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2221}, +/*h(2)=2 XOPV 0x90 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2222}, +/*h(3)=3 XOPV 0x90 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2223} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x91_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x91 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2226}, +/*h(1)=1 XOPV 0x91 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2227}, +/*h(2)=2 XOPV 0x91 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2228}, +/*h(3)=3 XOPV 0x91 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2229} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x92_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x92 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2232}, +/*h(1)=1 XOPV 0x92 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2233}, +/*h(2)=2 XOPV 0x92 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2234}, +/*h(3)=3 XOPV 0x92 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2235} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x93_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x93 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2238}, +/*h(1)=1 XOPV 0x93 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2239}, +/*h(2)=2 XOPV 0x93 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2240}, +/*h(3)=3 XOPV 0x93 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2241} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x94_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x94 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2278}, +/*h(1)=1 XOPV 0x94 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2279}, +/*h(2)=2 XOPV 0x94 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2280}, +/*h(3)=3 XOPV 0x94 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2281} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x95_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x95 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2282}, +/*h(1)=1 XOPV 0x95 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2283}, +/*h(2)=2 XOPV 0x95 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2284}, +/*h(3)=3 XOPV 0x95 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2285} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x96_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x96 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2286}, +/*h(1)=1 XOPV 0x96 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2287}, +/*h(2)=2 XOPV 0x96 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2288}, +/*h(3)=3 XOPV 0x96 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2289} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x97_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x97 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2290}, +/*h(1)=1 XOPV 0x97 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2291}, +/*h(2)=2 XOPV 0x97 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2292}, +/*h(3)=3 XOPV 0x97 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2293} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x98_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x98 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2320}, +/*h(1)=1 XOPV 0x98 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2321}, +/*h(2)=2 XOPV 0x98 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2322}, +/*h(3)=3 XOPV 0x98 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2323} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x99_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x99 VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2324}, +/*h(1)=1 XOPV 0x99 VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2325}, +/*h(2)=2 XOPV 0x99 VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2326}, +/*h(3)=3 XOPV 0x99 VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2327} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x9a_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x9A VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2328}, +/*h(1)=1 XOPV 0x9A VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2329}, +/*h(2)=2 XOPV 0x9A VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2330}, +/*h(3)=3 XOPV 0x9A VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2331} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0x9b_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x9B VNP W0 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2332}, +/*h(1)=1 XOPV 0x9B VNP W0 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2333}, +/*h(2)=2 XOPV 0x9B VNP W1 VL128 XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2334}, +/*h(3)=3 XOPV 0x9B VNP W1 VL128 XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2335} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc1_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2294}, +/*h(13)=1 XOPV 0xC1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2295} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc2_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2296}, +/*h(13)=1 XOPV 0xC2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2297} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc3_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2298}, +/*h(13)=1 XOPV 0xC3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2299} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc6_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2300}, +/*h(13)=1 XOPV 0xC6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2301} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xc7_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2302}, +/*h(13)=1 XOPV 0xC7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2303} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xcb_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2336}, +/*h(13)=1 XOPV 0xCB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2337} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd1_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2304}, +/*h(13)=1 XOPV 0xD1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2305} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd2_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2306}, +/*h(13)=1 XOPV 0xD2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2307} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd3_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2308}, +/*h(13)=1 XOPV 0xD3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2309} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd6_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2310}, +/*h(13)=1 XOPV 0xD6 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2311} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xd7_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2312}, +/*h(13)=1 XOPV 0xD7 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2313} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xdb_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2338}, +/*h(13)=1 XOPV 0xDB VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2339} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xe1_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2314}, +/*h(13)=1 XOPV 0xE1 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2315} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xe2_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2316}, +/*h(13)=1 XOPV 0xE2 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2317} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xop9_opcode0xe3_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(12)=0 XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM()*/ {2318}, +/*h(13)=1 XOPV 0xE3 VNP W0 VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[rrr] RM[nnn]*/ {2319} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 12; +if(hidx <= 1) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xopA_opcode0x10_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(24)=0 XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()*/ {2340}, +/*h(25)=1 XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()*/ {2342}, +/*h(26)=2 XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()*/ {2340}, +/*h(27)=3 XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()*/ {2342}, +/*h(28)=4 XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()*/ {2341}, +/*h(29)=5 XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()*/ {2343} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_MODE_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(d); +hidx = key - 24; +if(hidx <= 5) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +static xed_uint32_t xed3_phash_find_mapamd_xopA_opcode0x12_vv3(const xed_decoded_inst_t* d) +{ +typedef struct { xed_uint32_t value;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() UIMM32()*/ {2382}, +/*h(1)=1 XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()*/ {2383}, +/*h(2)=2 XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UIMM32()*/ {2384}, +/*h(3)=3 XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()*/ {2385} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_dec_lu_MOD3_REG_VEX_PREFIX_VL(d); +hidx = key - 0; +if(hidx <= 3) { + return lu_table[hidx].value; +} +else{ + return 0; +} +} +#endif diff --git a/CodeVirtualizer/build/obj/include-private/xed3-phash.h b/CodeVirtualizer/build/obj/include-private/xed3-phash.h new file mode 100644 index 0000000..712df25 --- /dev/null +++ b/CodeVirtualizer/build/obj/include-private/xed3-phash.h @@ -0,0 +1,37 @@ +/// @file include-private/xed3-phash.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(INCLUDE_PRIVATE_XED3_PHASH_H) +# define INCLUDE_PRIVATE_XED3_PHASH_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-phash-lu-vv0.h" +#include "xed3-phash-lu-vv1.h" +#include "xed3-phash-lu-vv2.h" +#include "xed3-phash-lu-vv3.h" +#define XED_PHASH_MAP_LIMIT 11 +const xed3_find_func_t* xed3_phash_lu[4][XED_PHASH_MAP_LIMIT] = { +{ xed3_phash_vv0_map_legacy_map0, xed3_phash_vv0_map_legacy_map1, xed3_phash_vv0_map_legacy_map2, xed3_phash_vv0_map_legacy_map3, xed3_phash_vv0_map_amd_3dnow, 0, 0, 0, 0, 0, 0 }, +{ 0, xed3_phash_vv1_map_vex_map1, xed3_phash_vv1_map_vex_map2, xed3_phash_vv1_map_vex_map3, 0, 0, 0, 0, 0, 0, 0 }, +{ 0, xed3_phash_vv2_map_evex_map1, xed3_phash_vv2_map_evex_map2, xed3_phash_vv2_map_evex_map3, 0, xed3_phash_vv2_map_evex_map5, xed3_phash_vv2_map_evex_map6, 0, 0, 0, 0 }, +{ 0, 0, 0, 0, 0, 0, 0, 0, xed3_phash_vv3_map_amd_xop8, xed3_phash_vv3_map_amd_xop9, xed3_phash_vv3_map_amd_xopA }, +}; +#endif diff --git a/CodeVirtualizer/build/obj/inline_nt.txt b/CodeVirtualizer/build/obj/inline_nt.txt new file mode 100644 index 0000000..c59d542 --- /dev/null +++ b/CodeVirtualizer/build/obj/inline_nt.txt @@ -0,0 +1,2120 @@ +nt: SEGMENT_DEFAULT_ENCODE +working rule: + BASE0=rIPa() -> nothing +inlining rule: rIPa():: + OUTREG=XED_REG_EIP EASZ=2 -> nothing + OUTREG=XED_REG_RIP EASZ=3 -> nothing + +new rule BASE0=XED_REG_EIP EASZ=2 -> nothing +new rule BASE0=XED_REG_RIP EASZ=3 -> nothing +working rule: + BASE0=ArSP() -> FB DEFAULT_SEG=1 value=0x1 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule BASE0=XED_REG_SP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1 +new rule BASE0=XED_REG_ESP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1 +new rule BASE0=XED_REG_RSP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1 +working rule: + BASE0=ArBP() -> FB DEFAULT_SEG=1 value=0x1 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule BASE0=XED_REG_BP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1 +new rule BASE0=XED_REG_EBP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1 +new rule BASE0=XED_REG_RBP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1 +working rule: + BASE0=ArAX() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule BASE0=XED_REG_AX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_EAX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_RAX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=ArCX() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule BASE0=XED_REG_CX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_ECX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_RCX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=ArDX() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule BASE0=XED_REG_DX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_EDX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_RDX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=ArBX() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule BASE0=XED_REG_BX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_EBX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_RBX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=ArSI() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule BASE0=XED_REG_SI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_ESI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_RSI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=ArDI() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule BASE0=XED_REG_DI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_EDI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_RDI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar8() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R8W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R8D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R8 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar9() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R9W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R9D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R9 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar10() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R10W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R10D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R10 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar11() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R11W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R11D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R11 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar12() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R12W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R12D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R12 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar13() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R13W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R13D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R13 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar14() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R14W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R14D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R14 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +working rule: + BASE0=Ar15() -> FB DEFAULT_SEG=0 value=0x0 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R15W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R15D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 +new rule BASE0=XED_REG_R15 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 +nt: SEGMENT_ENCODE +nt: SIB_REQUIRED_ENCODE +working rule: + EASZ=2 INDEX=GPR32e() -> FB NEED_SIB=1 value=0x1 +inlining rule: GPR32e():: + MODE=1 OUTREG=GPR32e_m32() -> nothing + MODE=2 OUTREG=GPR32e_m64() -> nothing + +new rule EASZ=2 MODE=1 INDEX=GPR32e_m32() -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=GPR32e_m64() -> FB NEED_SIB=1 value=0x1 +working rule: + EASZ=3 INDEX=GPR64e() -> FB NEED_SIB=1 value=0x1 +inlining rule: GPR64e():: + OUTREG=XED_REG_RAX -> nothing + OUTREG=XED_REG_RBX -> nothing + OUTREG=XED_REG_RCX -> nothing + OUTREG=XED_REG_RDX -> nothing + OUTREG=XED_REG_RSP -> nothing + OUTREG=XED_REG_RBP -> nothing + OUTREG=XED_REG_RSI -> nothing + OUTREG=XED_REG_RDI -> nothing + OUTREG=XED_REG_R8 -> nothing + OUTREG=XED_REG_R9 -> nothing + OUTREG=XED_REG_R10 -> nothing + OUTREG=XED_REG_R11 -> nothing + OUTREG=XED_REG_R12 -> nothing + OUTREG=XED_REG_R13 -> nothing + OUTREG=XED_REG_R14 -> nothing + OUTREG=XED_REG_R15 -> nothing + +new rule EASZ=3 INDEX=XED_REG_RAX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RBX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RCX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RDX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RSP -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RBP -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RSI -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_RDI -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R8 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R9 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R10 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R11 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R12 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R13 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R14 -> FB NEED_SIB=1 value=0x1 +new rule EASZ=3 INDEX=XED_REG_R15 -> FB NEED_SIB=1 value=0x1 +working rule: + EASZ!=1 BASE0=ArSP() -> FB NEED_SIB=1 value=0x1 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule EASZ!=1 BASE0=XED_REG_SP EASZ=1 -> FB NEED_SIB=1 value=0x1 +new rule EASZ!=1 BASE0=XED_REG_ESP EASZ=2 -> FB NEED_SIB=1 value=0x1 +new rule EASZ!=1 BASE0=XED_REG_RSP EASZ=3 -> FB NEED_SIB=1 value=0x1 +working rule: + EASZ!=1 BASE0=Ar12() -> FB NEED_SIB=1 value=0x1 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule EASZ!=1 BASE0=XED_REG_R12W EASZ=1 -> FB NEED_SIB=1 value=0x1 +new rule EASZ!=1 BASE0=XED_REG_R12D EASZ=2 -> FB NEED_SIB=1 value=0x1 +new rule EASZ!=1 BASE0=XED_REG_R12 EASZ=3 -> FB NEED_SIB=1 value=0x1 +working rule: + EASZ=2 MODE=1 INDEX=GPR32e_m32() -> FB NEED_SIB=1 value=0x1 +inlining rule: GPR32e_m32():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + +new rule EASZ=2 MODE=1 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=1 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1 +working rule: + EASZ=2 MODE=2 INDEX=GPR32e_m64() -> FB NEED_SIB=1 value=0x1 +inlining rule: GPR32e_m64():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + OUTREG=XED_REG_R8D -> nothing + OUTREG=XED_REG_R9D -> nothing + OUTREG=XED_REG_R10D -> nothing + OUTREG=XED_REG_R11D -> nothing + OUTREG=XED_REG_R12D -> nothing + OUTREG=XED_REG_R13D -> nothing + OUTREG=XED_REG_R14D -> nothing + OUTREG=XED_REG_R15D -> nothing + +new rule EASZ=2 MODE=2 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R8D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R9D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R10D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R11D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R12D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R13D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R14D -> FB NEED_SIB=1 value=0x1 +new rule EASZ=2 MODE=2 INDEX=XED_REG_R15D -> FB NEED_SIB=1 value=0x1 +nt: SIBBASE_ENCODE +nt: SIBBASE_ENCODE_SIB1 +working rule: + BASE0=ArAX() -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule BASE0=XED_REG_AX EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_EAX EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RAX EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 +working rule: + BASE0=Ar8() -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R8W EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R8D EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R8 EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 +working rule: + BASE0=ArCX() -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule BASE0=XED_REG_CX EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_ECX EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RCX EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 +working rule: + BASE0=Ar9() -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R9W EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R9D EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R9 EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 +working rule: + BASE0=ArDX() -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule BASE0=XED_REG_DX EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_EDX EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RDX EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 +working rule: + BASE0=Ar10() -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R10W EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R10D EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R10 EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 +working rule: + BASE0=ArBX() -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule BASE0=XED_REG_BX EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_EBX EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RBX EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 +working rule: + BASE0=Ar11() -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R11W EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R11D EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R11 EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 +working rule: + BASE0=ArSP() -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule BASE0=XED_REG_SP EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_ESP EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RSP EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 +working rule: + BASE0=Ar12() -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R12W EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R12D EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R12 EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 +working rule: + BASE0=ArBP() -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 +working rule: + BASE0=Ar13() -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 +working rule: + BASE0=ArSI() -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule BASE0=XED_REG_SI EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_ESI EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RSI EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 +working rule: + BASE0=Ar14() -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R14W EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R14D EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R14 EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 +working rule: + BASE0=ArDI() -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule BASE0=XED_REG_DI EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_EDI EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 +new rule BASE0=XED_REG_RDI EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 +working rule: + BASE0=Ar15() -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R15W EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R15D EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 +new rule BASE0=XED_REG_R15 EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 +nt: SIBINDEX_ENCODE +nt: SIBINDEX_ENCODE_SIB1 +working rule: + INDEX=ArAX() -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule INDEX=XED_REG_AX EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_EAX EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RAX EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 +working rule: + INDEX=Ar8() -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R8W EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R8D EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R8 EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 +working rule: + INDEX=ArCX() -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule INDEX=XED_REG_CX EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_ECX EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RCX EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 +working rule: + INDEX=Ar9() -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R9W EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R9D EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R9 EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 +working rule: + INDEX=ArDX() -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule INDEX=XED_REG_DX EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_EDX EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RDX EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 +working rule: + INDEX=Ar10() -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R10W EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R10D EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R10 EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 +working rule: + INDEX=ArBX() -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule INDEX=XED_REG_BX EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_EBX EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RBX EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 +working rule: + INDEX=Ar11() -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R11W EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R11D EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R11 EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 +working rule: + INDEX=Ar12() -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R12W EASZ=1 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R12D EASZ=2 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R12 EASZ=3 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 +working rule: + INDEX=ArBP() -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule INDEX=XED_REG_BP EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_EBP EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RBP EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 +working rule: + INDEX=Ar13() -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R13W EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R13D EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R13 EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 +working rule: + INDEX=ArSI() -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule INDEX=XED_REG_SI EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_ESI EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RSI EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 +working rule: + INDEX=Ar14() -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R14W EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R14D EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R14 EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 +working rule: + INDEX=ArDI() -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule INDEX=XED_REG_DI EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_EDI EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 +new rule INDEX=XED_REG_RDI EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 +working rule: + INDEX=Ar15() -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule INDEX=XED_REG_R15W EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R15D EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 +new rule INDEX=XED_REG_R15 EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 +nt: SIBSCALE_ENCODE +nt: MODRM_MOD_ENCODE +nt: MODRM_MOD_EA16_DISP0 +nt: MODRM_MOD_EA16_DISP8 +nt: MODRM_MOD_EA16_DISP16 +nt: MODRM_MOD_EA32_DISP0 +nt: MODRM_MOD_EA32_DISP8 +nt: MODRM_MOD_EA32_DISP32 +working rule: + BASE0=GPR32e() -> FB MOD=2 value=0x2 +inlining rule: GPR32e():: + MODE=1 OUTREG=GPR32e_m32() -> nothing + MODE=2 OUTREG=GPR32e_m64() -> nothing + +new rule MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2 +working rule: + BASE0=rIPa() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: rIPa():: + OUTREG=XED_REG_EIP EASZ=2 -> nothing + OUTREG=XED_REG_RIP EASZ=3 -> nothing + +new rule MODE=2 BASE0=XED_REG_EIP EASZ=2 -> FB MOD=0 value=0x0 +new rule MODE=2 BASE0=XED_REG_RIP EASZ=3 -> FB MOD=0 value=0x0 +working rule: + MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2 +inlining rule: GPR32e_m32():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + +new rule MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 +new rule MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 +working rule: + MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2 +inlining rule: GPR32e_m64():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + OUTREG=XED_REG_R8D -> nothing + OUTREG=XED_REG_R9D -> nothing + OUTREG=XED_REG_R10D -> nothing + OUTREG=XED_REG_R11D -> nothing + OUTREG=XED_REG_R12D -> nothing + OUTREG=XED_REG_R13D -> nothing + OUTREG=XED_REG_R14D -> nothing + OUTREG=XED_REG_R15D -> nothing + +new rule MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2 +new rule MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2 +nt: MODRM_MOD_EA64_DISP0 +nt: MODRM_MOD_EA64_DISP8 +working rule: + BASE0=GPR64e() -> FB MOD=1 value=0x1 +inlining rule: GPR64e():: + OUTREG=XED_REG_RAX -> nothing + OUTREG=XED_REG_RBX -> nothing + OUTREG=XED_REG_RCX -> nothing + OUTREG=XED_REG_RDX -> nothing + OUTREG=XED_REG_RSP -> nothing + OUTREG=XED_REG_RBP -> nothing + OUTREG=XED_REG_RSI -> nothing + OUTREG=XED_REG_RDI -> nothing + OUTREG=XED_REG_R8 -> nothing + OUTREG=XED_REG_R9 -> nothing + OUTREG=XED_REG_R10 -> nothing + OUTREG=XED_REG_R11 -> nothing + OUTREG=XED_REG_R12 -> nothing + OUTREG=XED_REG_R13 -> nothing + OUTREG=XED_REG_R14 -> nothing + OUTREG=XED_REG_R15 -> nothing + +new rule BASE0=XED_REG_RAX -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RBX -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RCX -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RDX -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RSP -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RSI -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_RDI -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R8 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R9 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R10 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R11 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R12 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R14 -> FB MOD=1 value=0x1 +new rule BASE0=XED_REG_R15 -> FB MOD=1 value=0x1 +nt: MODRM_MOD_EA64_DISP32 +nt: MODRM_RM_ENCODE +nt: MODRM_RM_ENCODE_EA16_SIB0 +nt: MODRM_RM_ENCODE_EA64_SIB0 +nt: MODRM_RM_ENCODE_EA32_SIB0 +nt: MODRM_RM_ENCODE_EANOT16_SIB1 +nt: SIB_NT +nt: DISP_NT +nt: ERROR +nt: DISP_WIDTH_0 +nt: DISP_WIDTH_8 +nt: DISP_WIDTH_16 +nt: DISP_WIDTH_32 +nt: DISP_WIDTH_0_8_16 +nt: DISP_WIDTH_0_8_32 +nt: FIXUP_EOSZ_ENC +nt: FIXUP_EASZ_ENC +nt: FIXUP_SMODE_ENC +nt: REMOVE_SEGMENT +nt: REMOVE_SEGMENT_AGEN1 +working rule: + SEG0=SEGe() -> FB ERROR=XED_ERROR_GENERAL_ERROR +inlining rule: SEGe():: + OUTREG=XED_REG_DS -> nothing + OUTREG=XED_REG_CS -> nothing + OUTREG=XED_REG_ES -> nothing + OUTREG=XED_REG_FS -> nothing + OUTREG=XED_REG_GS -> nothing + OUTREG=XED_REG_SS -> nothing + +new rule SEG0=XED_REG_DS -> FB ERROR=XED_ERROR_GENERAL_ERROR +new rule SEG0=XED_REG_CS -> FB ERROR=XED_ERROR_GENERAL_ERROR +new rule SEG0=XED_REG_ES -> FB ERROR=XED_ERROR_GENERAL_ERROR +new rule SEG0=XED_REG_FS -> FB ERROR=XED_ERROR_GENERAL_ERROR +new rule SEG0=XED_REG_GS -> FB ERROR=XED_ERROR_GENERAL_ERROR +new rule SEG0=XED_REG_SS -> FB ERROR=XED_ERROR_GENERAL_ERROR +nt: OVERRIDE_SEG0 +nt: OVERRIDE_SEG1 +nt: REX_PREFIX_ENC +nt: PREFIX_ENC +nt: DF64 +nt: OSZ_NONTERM_ENC +nt: REFINING66 +nt: IGNORE66 +nt: IMMUNE66 +nt: IMMUNE66_LOOP64 +nt: IMMUNE_REXW +nt: CR_WIDTH +nt: FORCE64 +nt: BRANCH_HINT +nt: CET_NO_TRACK +nt: VEXED_REX +nt: XOP_TYPE_ENC +nt: XOP_MAP_ENC +nt: XOP_REXXB_ENC +nt: BND_R_CHECK +nt: BND_B_CHECK +nt: VEX_TYPE_ENC +nt: VEX_REXR_ENC +nt: VEX_REXXB_ENC +nt: VEX_MAP_ENC +nt: VEX_REG_ENC +nt: VEX_ESCVL_ENC +nt: SE_IMM8 +nt: VMODRM_MOD_ENCODE +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArBP() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar13() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArBP() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar13() -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArAX() -> FB MOD=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArBX() -> FB MOD=0 value=0x0 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArCX() -> FB MOD=0 value=0x0 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArDX() -> FB MOD=0 value=0x0 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArSI() -> FB MOD=0 value=0x0 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArDI() -> FB MOD=0 value=0x0 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=ArSP() -> FB MOD=0 value=0x0 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar8() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar9() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar10() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar11() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar12() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar14() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=2 DISP_WIDTH=0 BASE0=Ar15() MODE=2 -> FB MOD=0 value=0x0 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArAX() -> FB MOD=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArBX() -> FB MOD=0 value=0x0 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArCX() -> FB MOD=0 value=0x0 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArDX() -> FB MOD=0 value=0x0 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArSI() -> FB MOD=0 value=0x0 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArDI() -> FB MOD=0 value=0x0 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=ArSP() -> FB MOD=0 value=0x0 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar8() -> FB MOD=0 value=0x0 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar9() -> FB MOD=0 value=0x0 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar10() -> FB MOD=0 value=0x0 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar11() -> FB MOD=0 value=0x0 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar12() -> FB MOD=0 value=0x0 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar14() -> FB MOD=0 value=0x0 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=0 BASE0=Ar15() -> FB MOD=0 value=0x0 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0 +new rule EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0 +working rule: + EASZ=3 DISP_WIDTH=8 BASE0=GPR64e() -> FB MOD=1 value=0x1 +inlining rule: GPR64e():: + OUTREG=XED_REG_RAX -> nothing + OUTREG=XED_REG_RBX -> nothing + OUTREG=XED_REG_RCX -> nothing + OUTREG=XED_REG_RDX -> nothing + OUTREG=XED_REG_RSP -> nothing + OUTREG=XED_REG_RBP -> nothing + OUTREG=XED_REG_RSI -> nothing + OUTREG=XED_REG_RDI -> nothing + OUTREG=XED_REG_R8 -> nothing + OUTREG=XED_REG_R9 -> nothing + OUTREG=XED_REG_R10 -> nothing + OUTREG=XED_REG_R11 -> nothing + OUTREG=XED_REG_R12 -> nothing + OUTREG=XED_REG_R13 -> nothing + OUTREG=XED_REG_R14 -> nothing + OUTREG=XED_REG_R15 -> nothing + +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RAX -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBX -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RCX -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDX -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSP -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSI -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDI -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R8 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R9 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R10 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R11 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R12 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R14 -> FB MOD=1 value=0x1 +new rule EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R15 -> FB MOD=1 value=0x1 +working rule: + EASZ=2 DISP_WIDTH=32 BASE0=GPR32e() -> FB MOD=2 value=0x2 +inlining rule: GPR32e():: + MODE=1 OUTREG=GPR32e_m32() -> nothing + MODE=2 OUTREG=GPR32e_m64() -> nothing + +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArAX() -> FB MOD=2 value=0x2 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_AX EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArBX() -> FB MOD=2 value=0x2 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BX EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArCX() -> FB MOD=2 value=0x2 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_CX EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArDX() -> FB MOD=2 value=0x2 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DX EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArSI() -> FB MOD=2 value=0x2 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SI EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArDI() -> FB MOD=2 value=0x2 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DI EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArSP() -> FB MOD=2 value=0x2 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SP EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=ArBP() -> FB MOD=2 value=0x2 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BP EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar8() -> FB MOD=2 value=0x2 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar9() -> FB MOD=2 value=0x2 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar10() -> FB MOD=2 value=0x2 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar11() -> FB MOD=2 value=0x2 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar12() -> FB MOD=2 value=0x2 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar13() -> FB MOD=2 value=0x2 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar14() -> FB MOD=2 value=0x2 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=3 DISP_WIDTH=32 BASE0=Ar15() -> FB MOD=2 value=0x2 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=2 value=0x2 +new rule EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=2 value=0x2 +working rule: + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=GPR32e_m32() -> FB MOD=2 value=0x2 +inlining rule: GPR32e_m32():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 +working rule: + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=GPR32e_m64() -> FB MOD=2 value=0x2 +inlining rule: GPR32e_m64():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + OUTREG=XED_REG_R8D -> nothing + OUTREG=XED_REG_R9D -> nothing + OUTREG=XED_REG_R10D -> nothing + OUTREG=XED_REG_R11D -> nothing + OUTREG=XED_REG_R12D -> nothing + OUTREG=XED_REG_R13D -> nothing + OUTREG=XED_REG_R14D -> nothing + OUTREG=XED_REG_R15D -> nothing + +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2 +new rule EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2 +nt: VSIB_ENC_BASE +working rule: + BASE0=ArAX() -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule BASE0=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 +new rule BASE0=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 +new rule BASE0=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 +working rule: + BASE0=ArCX() -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule BASE0=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 +new rule BASE0=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 +new rule BASE0=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 +working rule: + BASE0=ArDX() -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule BASE0=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 +new rule BASE0=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 +new rule BASE0=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 +working rule: + BASE0=ArBX() -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule BASE0=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 +new rule BASE0=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 +new rule BASE0=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 +working rule: + BASE0=ArSP() -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule BASE0=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 +new rule BASE0=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 +new rule BASE0=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 +working rule: + BASE0=ArBP() -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 +new rule BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 +new rule BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 +working rule: + BASE0=Ar13() -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 +new rule BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 +new rule BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 +working rule: + BASE0=ArSI() -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule BASE0=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 +new rule BASE0=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 +new rule BASE0=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 +working rule: + BASE0=ArDI() -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule BASE0=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 +new rule BASE0=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 +new rule BASE0=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 +working rule: + BASE0=Ar8() -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 +new rule BASE0=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 +new rule BASE0=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 +working rule: + BASE0=Ar9() -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 +new rule BASE0=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 +new rule BASE0=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 +working rule: + BASE0=Ar10() -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 +new rule BASE0=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 +new rule BASE0=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 +working rule: + BASE0=Ar11() -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 +new rule BASE0=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 +new rule BASE0=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 +working rule: + BASE0=Ar12() -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 +new rule BASE0=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 +new rule BASE0=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 +working rule: + BASE0=Ar14() -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 +new rule BASE0=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 +new rule BASE0=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 +working rule: + BASE0=Ar15() -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule BASE0=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 +new rule BASE0=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 +new rule BASE0=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 +nt: VSIB_ENC_SCALE +nt: VSIB_ENC +nt: VSIB_ENC_INDEX_XMM +nt: VSIB_ENC_INDEX_YMM +nt: DISP_WIDTH_8_32 +nt: NELEM_TUPLE1_4X +nt: EVEX_62_REXR_ENC +nt: EVEX_REXX_ENC +nt: EVEX_REXB_ENC +nt: EVEX_REXRR_ENC +nt: EVEX_MAP_ENC +nt: EVEX_REXW_VVVV_ENC +nt: EVEX_UPP_ENC +nt: EVEX_LL_ENC +nt: AVX512_EVEX_BYTE3_ENC +nt: AVX512_ROUND +nt: SAE +nt: ESIZE_128_BITS +nt: ESIZE_64_BITS +nt: ESIZE_32_BITS +nt: ESIZE_16_BITS +nt: ESIZE_8_BITS +nt: ESIZE_4_BITS +nt: ESIZE_2_BITS +nt: ESIZE_1_BITS +nt: NELEM_MOVDDUP +nt: NELEM_FULLMEM +nt: NELEM_HALFMEM +nt: NELEM_QUARTERMEM +nt: NELEM_EIGHTHMEM +nt: NELEM_GPR_READER_BYTE +nt: NELEM_GPR_READER_WORD +nt: NELEM_GPR_WRITER_LDOP_D +nt: NELEM_GPR_WRITER_LDOP_Q +nt: NELEM_GPR_WRITER_STORE_BYTE +nt: NELEM_GPR_WRITER_STORE_WORD +nt: NELEM_TUPLE1_BYTE +nt: NELEM_TUPLE1_WORD +nt: NELEM_SCALAR +nt: NELEM_TUPLE1_SUBDWORD +nt: NELEM_GPR_READER +nt: NELEM_GPR_READER_SUBDWORD +nt: NELEM_GPR_WRITER_LDOP +nt: NELEM_GPR_WRITER_STORE +nt: NELEM_GPR_WRITER_STORE_SUBDWORD +nt: NELEM_MEM128 +nt: NELEM_TUPLE1 +nt: NELEM_GSCAT +nt: NELEM_TUPLE2 +nt: NELEM_TUPLE4 +nt: NELEM_TUPLE8 +nt: NELEM_FULL +nt: NELEM_HALF +nt: FIX_ROUND_LEN512 +nt: FIX_ROUND_LEN128 +nt: UISA_ENC_INDEX_ZMM +nt: UISA_ENC_INDEX_YMM +nt: UISA_ENC_INDEX_XMM +nt: NELEM_QUARTER +nt: GPR8_R +nt: GPR8_B +nt: GPR8_SB +nt: SEGe +nt: GPR16e +nt: GPR32e +working rule: + MODE=1 OUTREG=GPR32e_m32() -> nothing +inlining rule: GPR32e_m32():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + +new rule MODE=1 OUTREG=XED_REG_EAX -> nothing +new rule MODE=1 OUTREG=XED_REG_EBX -> nothing +new rule MODE=1 OUTREG=XED_REG_ECX -> nothing +new rule MODE=1 OUTREG=XED_REG_EDX -> nothing +new rule MODE=1 OUTREG=XED_REG_ESP -> nothing +new rule MODE=1 OUTREG=XED_REG_EBP -> nothing +new rule MODE=1 OUTREG=XED_REG_ESI -> nothing +new rule MODE=1 OUTREG=XED_REG_EDI -> nothing +working rule: + MODE=2 OUTREG=GPR32e_m64() -> nothing +inlining rule: GPR32e_m64():: + OUTREG=XED_REG_EAX -> nothing + OUTREG=XED_REG_EBX -> nothing + OUTREG=XED_REG_ECX -> nothing + OUTREG=XED_REG_EDX -> nothing + OUTREG=XED_REG_ESP -> nothing + OUTREG=XED_REG_EBP -> nothing + OUTREG=XED_REG_ESI -> nothing + OUTREG=XED_REG_EDI -> nothing + OUTREG=XED_REG_R8D -> nothing + OUTREG=XED_REG_R9D -> nothing + OUTREG=XED_REG_R10D -> nothing + OUTREG=XED_REG_R11D -> nothing + OUTREG=XED_REG_R12D -> nothing + OUTREG=XED_REG_R13D -> nothing + OUTREG=XED_REG_R14D -> nothing + OUTREG=XED_REG_R15D -> nothing + +new rule MODE=2 OUTREG=XED_REG_EAX -> nothing +new rule MODE=2 OUTREG=XED_REG_EBX -> nothing +new rule MODE=2 OUTREG=XED_REG_ECX -> nothing +new rule MODE=2 OUTREG=XED_REG_EDX -> nothing +new rule MODE=2 OUTREG=XED_REG_ESP -> nothing +new rule MODE=2 OUTREG=XED_REG_EBP -> nothing +new rule MODE=2 OUTREG=XED_REG_ESI -> nothing +new rule MODE=2 OUTREG=XED_REG_EDI -> nothing +new rule MODE=2 OUTREG=XED_REG_R8D -> nothing +new rule MODE=2 OUTREG=XED_REG_R9D -> nothing +new rule MODE=2 OUTREG=XED_REG_R10D -> nothing +new rule MODE=2 OUTREG=XED_REG_R11D -> nothing +new rule MODE=2 OUTREG=XED_REG_R12D -> nothing +new rule MODE=2 OUTREG=XED_REG_R13D -> nothing +new rule MODE=2 OUTREG=XED_REG_R14D -> nothing +new rule MODE=2 OUTREG=XED_REG_R15D -> nothing +nt: GPR32e_m32 +nt: GPR32e_m64 +nt: GPR64e +nt: ArAX +nt: ArBX +nt: ArCX +nt: ArDX +nt: ArSI +nt: ArDI +nt: ArSP +nt: ArBP +nt: SrSP +nt: SrBP +nt: Ar8 +nt: Ar9 +nt: Ar10 +nt: Ar11 +nt: Ar12 +nt: Ar13 +nt: Ar14 +nt: Ar15 +nt: rIP +nt: rIPa +nt: OeAX +nt: OrAX +nt: OrDX +nt: OrCX +nt: OrBX +nt: OrSP +nt: OrBP +nt: rFLAGS +nt: MMX_R +nt: MMX_B +nt: GPRv_R +nt: GPRv_SB +nt: GPRz_R +nt: GPRv_B +nt: GPRz_B +nt: GPRy_B +nt: GPRy_R +nt: GPR64_R +nt: GPR64_B +nt: GPR64_SB +nt: GPR64_X +nt: GPR32_R +nt: GPR32_B +nt: GPR32_SB +nt: GPR32_X +nt: GPR16_R +nt: GPR16_B +nt: GPR16_SB +nt: CR_R +nt: CR_B +nt: DR_R +nt: X87 +nt: SEG +nt: SEG_MOV +nt: FINAL_DSEG +nt: FINAL_DSEG_NOT64 +nt: FINAL_DSEG_MODE64 +nt: FINAL_DSEG1 +nt: FINAL_DSEG1_NOT64 +nt: FINAL_DSEG1_MODE64 +nt: FINAL_ESEG +nt: FINAL_ESEG1 +nt: FINAL_SSEG1 +nt: FINAL_SSEG0 +nt: FINAL_SSEG +nt: FINAL_SSEG_NOT64 +nt: FINAL_SSEG_MODE64 +nt: XMM_R +nt: XMM_R_32 +nt: XMM_R_64 +nt: XMM_B +nt: XMM_B_32 +nt: XMM_B_64 +nt: BND_R +nt: BND_B +nt: A_GPR_R +working rule: + OUTREG=ArAX() -> FB REXR=0 value=0x0 FB REG=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_AX EASZ=1 -> FB REXR=0 value=0x0 FB REG=0 value=0x0 +new rule OUTREG=XED_REG_EAX EASZ=2 -> FB REXR=0 value=0x0 FB REG=0 value=0x0 +new rule OUTREG=XED_REG_RAX EASZ=3 -> FB REXR=0 value=0x0 FB REG=0 value=0x0 +working rule: + OUTREG=ArCX() -> FB REXR=0 value=0x0 FB REG=1 value=0x1 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_CX EASZ=1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1 +new rule OUTREG=XED_REG_ECX EASZ=2 -> FB REXR=0 value=0x0 FB REG=1 value=0x1 +new rule OUTREG=XED_REG_RCX EASZ=3 -> FB REXR=0 value=0x0 FB REG=1 value=0x1 +working rule: + OUTREG=ArDX() -> FB REXR=0 value=0x0 FB REG=2 value=0x2 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_DX EASZ=1 -> FB REXR=0 value=0x0 FB REG=2 value=0x2 +new rule OUTREG=XED_REG_EDX EASZ=2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2 +new rule OUTREG=XED_REG_RDX EASZ=3 -> FB REXR=0 value=0x0 FB REG=2 value=0x2 +working rule: + OUTREG=ArBX() -> FB REXR=0 value=0x0 FB REG=3 value=0x3 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_BX EASZ=1 -> FB REXR=0 value=0x0 FB REG=3 value=0x3 +new rule OUTREG=XED_REG_EBX EASZ=2 -> FB REXR=0 value=0x0 FB REG=3 value=0x3 +new rule OUTREG=XED_REG_RBX EASZ=3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3 +working rule: + OUTREG=ArSP() -> FB REXR=0 value=0x0 FB REG=4 value=0x4 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule OUTREG=XED_REG_SP EASZ=1 -> FB REXR=0 value=0x0 FB REG=4 value=0x4 +new rule OUTREG=XED_REG_ESP EASZ=2 -> FB REXR=0 value=0x0 FB REG=4 value=0x4 +new rule OUTREG=XED_REG_RSP EASZ=3 -> FB REXR=0 value=0x0 FB REG=4 value=0x4 +working rule: + OUTREG=ArBP() -> FB REXR=0 value=0x0 FB REG=5 value=0x5 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule OUTREG=XED_REG_BP EASZ=1 -> FB REXR=0 value=0x0 FB REG=5 value=0x5 +new rule OUTREG=XED_REG_EBP EASZ=2 -> FB REXR=0 value=0x0 FB REG=5 value=0x5 +new rule OUTREG=XED_REG_RBP EASZ=3 -> FB REXR=0 value=0x0 FB REG=5 value=0x5 +working rule: + OUTREG=ArSI() -> FB REXR=0 value=0x0 FB REG=6 value=0x6 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule OUTREG=XED_REG_SI EASZ=1 -> FB REXR=0 value=0x0 FB REG=6 value=0x6 +new rule OUTREG=XED_REG_ESI EASZ=2 -> FB REXR=0 value=0x0 FB REG=6 value=0x6 +new rule OUTREG=XED_REG_RSI EASZ=3 -> FB REXR=0 value=0x0 FB REG=6 value=0x6 +working rule: + OUTREG=ArDI() -> FB REXR=0 value=0x0 FB REG=7 value=0x7 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule OUTREG=XED_REG_DI EASZ=1 -> FB REXR=0 value=0x0 FB REG=7 value=0x7 +new rule OUTREG=XED_REG_EDI EASZ=2 -> FB REXR=0 value=0x0 FB REG=7 value=0x7 +new rule OUTREG=XED_REG_RDI EASZ=3 -> FB REXR=0 value=0x0 FB REG=7 value=0x7 +working rule: + OUTREG=Ar8() -> FB REXR=1 value=0x1 FB REG=0 value=0x0 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R8W EASZ=1 -> FB REXR=1 value=0x1 FB REG=0 value=0x0 +new rule OUTREG=XED_REG_R8D EASZ=2 -> FB REXR=1 value=0x1 FB REG=0 value=0x0 +new rule OUTREG=XED_REG_R8 EASZ=3 -> FB REXR=1 value=0x1 FB REG=0 value=0x0 +working rule: + OUTREG=Ar9() -> FB REXR=1 value=0x1 FB REG=1 value=0x1 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R9W EASZ=1 -> FB REXR=1 value=0x1 FB REG=1 value=0x1 +new rule OUTREG=XED_REG_R9D EASZ=2 -> FB REXR=1 value=0x1 FB REG=1 value=0x1 +new rule OUTREG=XED_REG_R9 EASZ=3 -> FB REXR=1 value=0x1 FB REG=1 value=0x1 +working rule: + OUTREG=Ar10() -> FB REXR=1 value=0x1 FB REG=2 value=0x2 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R10W EASZ=1 -> FB REXR=1 value=0x1 FB REG=2 value=0x2 +new rule OUTREG=XED_REG_R10D EASZ=2 -> FB REXR=1 value=0x1 FB REG=2 value=0x2 +new rule OUTREG=XED_REG_R10 EASZ=3 -> FB REXR=1 value=0x1 FB REG=2 value=0x2 +working rule: + OUTREG=Ar11() -> FB REXR=1 value=0x1 FB REG=3 value=0x3 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R11W EASZ=1 -> FB REXR=1 value=0x1 FB REG=3 value=0x3 +new rule OUTREG=XED_REG_R11D EASZ=2 -> FB REXR=1 value=0x1 FB REG=3 value=0x3 +new rule OUTREG=XED_REG_R11 EASZ=3 -> FB REXR=1 value=0x1 FB REG=3 value=0x3 +working rule: + OUTREG=Ar12() -> FB REXR=1 value=0x1 FB REG=4 value=0x4 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R12W EASZ=1 -> FB REXR=1 value=0x1 FB REG=4 value=0x4 +new rule OUTREG=XED_REG_R12D EASZ=2 -> FB REXR=1 value=0x1 FB REG=4 value=0x4 +new rule OUTREG=XED_REG_R12 EASZ=3 -> FB REXR=1 value=0x1 FB REG=4 value=0x4 +working rule: + OUTREG=Ar13() -> FB REXR=1 value=0x1 FB REG=5 value=0x5 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R13W EASZ=1 -> FB REXR=1 value=0x1 FB REG=5 value=0x5 +new rule OUTREG=XED_REG_R13D EASZ=2 -> FB REXR=1 value=0x1 FB REG=5 value=0x5 +new rule OUTREG=XED_REG_R13 EASZ=3 -> FB REXR=1 value=0x1 FB REG=5 value=0x5 +working rule: + OUTREG=Ar14() -> FB REXR=1 value=0x1 FB REG=6 value=0x6 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R14W EASZ=1 -> FB REXR=1 value=0x1 FB REG=6 value=0x6 +new rule OUTREG=XED_REG_R14D EASZ=2 -> FB REXR=1 value=0x1 FB REG=6 value=0x6 +new rule OUTREG=XED_REG_R14 EASZ=3 -> FB REXR=1 value=0x1 FB REG=6 value=0x6 +working rule: + OUTREG=Ar15() -> FB REXR=1 value=0x1 FB REG=7 value=0x7 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R15W EASZ=1 -> FB REXR=1 value=0x1 FB REG=7 value=0x7 +new rule OUTREG=XED_REG_R15D EASZ=2 -> FB REXR=1 value=0x1 FB REG=7 value=0x7 +new rule OUTREG=XED_REG_R15 EASZ=3 -> FB REXR=1 value=0x1 FB REG=7 value=0x7 +nt: A_GPR_B +working rule: + OUTREG=ArAX() -> FB REXB=0 value=0x0 FB RM=0 value=0x0 +inlining rule: ArAX():: + OUTREG=XED_REG_AX EASZ=1 -> nothing + OUTREG=XED_REG_EAX EASZ=2 -> nothing + OUTREG=XED_REG_RAX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB RM=0 value=0x0 +new rule OUTREG=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB RM=0 value=0x0 +new rule OUTREG=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB RM=0 value=0x0 +working rule: + OUTREG=ArCX() -> FB REXB=0 value=0x0 FB RM=1 value=0x1 +inlining rule: ArCX():: + OUTREG=XED_REG_CX EASZ=1 -> nothing + OUTREG=XED_REG_ECX EASZ=2 -> nothing + OUTREG=XED_REG_RCX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1 +new rule OUTREG=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB RM=1 value=0x1 +new rule OUTREG=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB RM=1 value=0x1 +working rule: + OUTREG=ArDX() -> FB REXB=0 value=0x0 FB RM=2 value=0x2 +inlining rule: ArDX():: + OUTREG=XED_REG_DX EASZ=1 -> nothing + OUTREG=XED_REG_EDX EASZ=2 -> nothing + OUTREG=XED_REG_RDX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB RM=2 value=0x2 +new rule OUTREG=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2 +new rule OUTREG=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB RM=2 value=0x2 +working rule: + OUTREG=ArBX() -> FB REXB=0 value=0x0 FB RM=3 value=0x3 +inlining rule: ArBX():: + OUTREG=XED_REG_BX EASZ=1 -> nothing + OUTREG=XED_REG_EBX EASZ=2 -> nothing + OUTREG=XED_REG_RBX EASZ=3 -> nothing + +new rule OUTREG=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB RM=3 value=0x3 +new rule OUTREG=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB RM=3 value=0x3 +new rule OUTREG=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3 +working rule: + OUTREG=ArSP() -> FB REXB=0 value=0x0 FB RM=4 value=0x4 +inlining rule: ArSP():: + OUTREG=XED_REG_SP EASZ=1 -> nothing + OUTREG=XED_REG_ESP EASZ=2 -> nothing + OUTREG=XED_REG_RSP EASZ=3 -> nothing + +new rule OUTREG=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB RM=4 value=0x4 +new rule OUTREG=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB RM=4 value=0x4 +new rule OUTREG=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB RM=4 value=0x4 +working rule: + OUTREG=ArBP() -> FB REXB=0 value=0x0 FB RM=5 value=0x5 +inlining rule: ArBP():: + OUTREG=XED_REG_BP EASZ=1 -> nothing + OUTREG=XED_REG_EBP EASZ=2 -> nothing + OUTREG=XED_REG_RBP EASZ=3 -> nothing + +new rule OUTREG=XED_REG_BP EASZ=1 -> FB REXB=0 value=0x0 FB RM=5 value=0x5 +new rule OUTREG=XED_REG_EBP EASZ=2 -> FB REXB=0 value=0x0 FB RM=5 value=0x5 +new rule OUTREG=XED_REG_RBP EASZ=3 -> FB REXB=0 value=0x0 FB RM=5 value=0x5 +working rule: + OUTREG=ArSI() -> FB REXB=0 value=0x0 FB RM=6 value=0x6 +inlining rule: ArSI():: + OUTREG=XED_REG_SI EASZ=1 -> nothing + OUTREG=XED_REG_ESI EASZ=2 -> nothing + OUTREG=XED_REG_RSI EASZ=3 -> nothing + +new rule OUTREG=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB RM=6 value=0x6 +new rule OUTREG=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB RM=6 value=0x6 +new rule OUTREG=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB RM=6 value=0x6 +working rule: + OUTREG=ArDI() -> FB REXB=0 value=0x0 FB RM=7 value=0x7 +inlining rule: ArDI():: + OUTREG=XED_REG_DI EASZ=1 -> nothing + OUTREG=XED_REG_EDI EASZ=2 -> nothing + OUTREG=XED_REG_RDI EASZ=3 -> nothing + +new rule OUTREG=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB RM=7 value=0x7 +new rule OUTREG=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB RM=7 value=0x7 +new rule OUTREG=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB RM=7 value=0x7 +working rule: + OUTREG=Ar8() -> FB REXB=1 value=0x1 FB RM=0 value=0x0 +inlining rule: Ar8():: + OUTREG=XED_REG_R8W EASZ=1 -> nothing + OUTREG=XED_REG_R8D EASZ=2 -> nothing + OUTREG=XED_REG_R8 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB RM=0 value=0x0 +new rule OUTREG=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB RM=0 value=0x0 +new rule OUTREG=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB RM=0 value=0x0 +working rule: + OUTREG=Ar9() -> FB REXB=1 value=0x1 FB RM=1 value=0x1 +inlining rule: Ar9():: + OUTREG=XED_REG_R9W EASZ=1 -> nothing + OUTREG=XED_REG_R9D EASZ=2 -> nothing + OUTREG=XED_REG_R9 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB RM=1 value=0x1 +new rule OUTREG=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB RM=1 value=0x1 +new rule OUTREG=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB RM=1 value=0x1 +working rule: + OUTREG=Ar10() -> FB REXB=1 value=0x1 FB RM=2 value=0x2 +inlining rule: Ar10():: + OUTREG=XED_REG_R10W EASZ=1 -> nothing + OUTREG=XED_REG_R10D EASZ=2 -> nothing + OUTREG=XED_REG_R10 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB RM=2 value=0x2 +new rule OUTREG=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB RM=2 value=0x2 +new rule OUTREG=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB RM=2 value=0x2 +working rule: + OUTREG=Ar11() -> FB REXB=1 value=0x1 FB RM=3 value=0x3 +inlining rule: Ar11():: + OUTREG=XED_REG_R11W EASZ=1 -> nothing + OUTREG=XED_REG_R11D EASZ=2 -> nothing + OUTREG=XED_REG_R11 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB RM=3 value=0x3 +new rule OUTREG=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB RM=3 value=0x3 +new rule OUTREG=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB RM=3 value=0x3 +working rule: + OUTREG=Ar12() -> FB REXB=1 value=0x1 FB RM=4 value=0x4 +inlining rule: Ar12():: + OUTREG=XED_REG_R12W EASZ=1 -> nothing + OUTREG=XED_REG_R12D EASZ=2 -> nothing + OUTREG=XED_REG_R12 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB RM=4 value=0x4 +new rule OUTREG=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB RM=4 value=0x4 +new rule OUTREG=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB RM=4 value=0x4 +working rule: + OUTREG=Ar13() -> FB REXB=1 value=0x1 FB RM=5 value=0x5 +inlining rule: Ar13():: + OUTREG=XED_REG_R13W EASZ=1 -> nothing + OUTREG=XED_REG_R13D EASZ=2 -> nothing + OUTREG=XED_REG_R13 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R13W EASZ=1 -> FB REXB=1 value=0x1 FB RM=5 value=0x5 +new rule OUTREG=XED_REG_R13D EASZ=2 -> FB REXB=1 value=0x1 FB RM=5 value=0x5 +new rule OUTREG=XED_REG_R13 EASZ=3 -> FB REXB=1 value=0x1 FB RM=5 value=0x5 +working rule: + OUTREG=Ar14() -> FB REXB=1 value=0x1 FB RM=6 value=0x6 +inlining rule: Ar14():: + OUTREG=XED_REG_R14W EASZ=1 -> nothing + OUTREG=XED_REG_R14D EASZ=2 -> nothing + OUTREG=XED_REG_R14 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB RM=6 value=0x6 +new rule OUTREG=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB RM=6 value=0x6 +new rule OUTREG=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB RM=6 value=0x6 +working rule: + OUTREG=Ar15() -> FB REXB=1 value=0x1 FB RM=7 value=0x7 +inlining rule: Ar15():: + OUTREG=XED_REG_R15W EASZ=1 -> nothing + OUTREG=XED_REG_R15D EASZ=2 -> nothing + OUTREG=XED_REG_R15 EASZ=3 -> nothing + +new rule OUTREG=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB RM=7 value=0x7 +new rule OUTREG=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB RM=7 value=0x7 +new rule OUTREG=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB RM=7 value=0x7 +nt: XMM_SE +nt: XMM_SE64 +nt: XMM_SE32 +nt: YMM_SE +nt: YMM_SE64 +nt: YMM_SE32 +nt: XMM_N +nt: XMM_N_32 +nt: XMM_N_64 +nt: YMM_N +nt: YMM_N_32 +nt: YMM_N_64 +nt: YMM_R +nt: YMM_R_32 +nt: YMM_R_64 +nt: YMM_B +nt: YMM_B_32 +nt: YMM_B_64 +nt: VGPRy_R +nt: VGPRy_B +nt: VGPRy_N +nt: VGPR32_N +nt: VGPR32_B +nt: VGPR32_R +nt: VGPR32_N_32 +nt: VGPR32_N_64 +nt: VGPR64_N +nt: VGPR32_R_32 +nt: VGPR32_R_64 +nt: VGPR64_R +nt: VGPR32_B_32 +nt: VGPR32_B_64 +nt: VGPR64_B +nt: MASK1 +nt: MASKNOT0 +nt: MASK_R +nt: MASK_B +nt: MASK_N +nt: MASK_N64 +nt: MASK_N32 +nt: XMM_R3 +nt: XMM_R3_32 +nt: XMM_R3_64 +nt: YMM_R3 +nt: YMM_R3_32 +nt: YMM_R3_64 +nt: ZMM_R3 +nt: ZMM_R3_32 +nt: ZMM_R3_64 +nt: XMM_B3 +nt: XMM_B3_32 +nt: XMM_B3_64 +nt: YMM_B3 +nt: YMM_B3_32 +nt: YMM_B3_64 +nt: ZMM_B3 +nt: ZMM_B3_32 +nt: ZMM_B3_64 +nt: XMM_N3 +nt: XMM_N3_32 +nt: XMM_N3_64 +nt: YMM_N3 +nt: YMM_N3_32 +nt: YMM_N3_64 +nt: ZMM_N3 +nt: ZMM_N3_32 +nt: ZMM_N3_64 +nt: TMM_R +nt: TMM_B +nt: TMM_N diff --git a/CodeVirtualizer/build/obj/nt_function_log.txt b/CodeVirtualizer/build/obj/nt_function_log.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/build/obj/prep-inputs b/CodeVirtualizer/build/obj/prep-inputs new file mode 100644 index 0000000..77f6730 --- /dev/null +++ b/CodeVirtualizer/build/obj/prep-inputs @@ -0,0 +1,370 @@ +C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/4fmaps-512-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/4fmaps-512/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/4vnniw-512-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/4vnniw-512/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/adl/adl-chips.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amd-3dnow-maps.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-fma4-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-fma4-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-vpermil2-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-vpermil2-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-dec.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-enc.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/amd-xop-maps.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/amdxop/xop-state-bits.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/cpuid-amd.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-3dnow.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-3dnow.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-base.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-base.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-chips.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-clzero.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-clzero.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-invlpgb.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-invlpgb.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-mcommit.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-mcommit.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-monitorx.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-monitorx.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-rdpru.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-rdpru.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-snp.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-snp.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-sse4a.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-sse4a.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-svm.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd-svm.txt +C:/$Fanta/IntelXED/xed/datafiles/amd/xed-amd3dnow-fields.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-operand-widths.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-reg-tables.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-reg-tables.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-regs.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-spr-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/amx-spr-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/amx-spr/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/avx-vnni-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/avx-vnni-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx-vnni/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-aes-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-aes-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-chips.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-fields.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-imm-enc.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-imm.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa-supp.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-movnt-store.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-movnt-store.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-operand-width.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pclmul-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pclmul-isa.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-pointer-width.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-reg-table.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-reg-table.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-regs.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-state-bits.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-vex-enc.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/avx-vex.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx/vex-maps.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-element-type-enum.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-element-types.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/bf16-opnd-widths.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-bf16/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-evex-disp8-enc-fp16.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-evex-disp8-fp16.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-evex-enc-map5-and-6.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-fp16-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/avx512-fp16-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/operand-types.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/state-bits.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-fp16/widths.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512-skx/skx-state-bits.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512cd/cpuid.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512cd/vconflict-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512cd/vconflict-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-addressing-dec.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-addressing-enc.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-disp8-enc.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-disp8.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-evex-dec.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-evex-enc.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-fields.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-foundation-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-foundation-isa.xed.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-kregs.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-operand-widths.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-pointer-width.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-table-mask.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-table-mask.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-b3.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-b3.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-n3.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-n3.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-r3.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-reg-tables-r3.txt +C:/$Fanta/IntelXED/xed/datafiles/avx512f/avx512-regs.txt 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+C:\$Fanta\IntelXED\xed\datafiles\knc\uisa-state-bits.txt diff --git a/CodeVirtualizer/build/obj/wkit/LICENSE b/CodeVirtualizer/build/obj/wkit/LICENSE new file mode 100644 index 0000000..7b1fcae --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/LICENSE @@ -0,0 +1,178 @@ + + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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In no event and under no legal theory, + whether in tort (including negligence), contract, or otherwise, + unless required by applicable law (such as deliberate and grossly + negligent acts) or agreed to in writing, shall any Contributor be + liable to You for damages, including any direct, indirect, special, + incidental, or consequential damages of any character arising as a + result of this License or out of the use or inability to use the + Work (including but not limited to damages for loss of goodwill, + work stoppage, computer failure or malfunction, or any and all + other commercial damages or losses), even if such Contributor + has been advised of the possibility of such damages. + + 9. Accepting Warranty or Additional Liability. While redistributing + the Work or Derivative Works thereof, You may choose to offer, + and charge a fee for, acceptance of support, warranty, indemnity, + or other liability obligations and/or rights consistent with this + License. However, in accepting such obligations, You may act only + on Your own behalf and on Your sole responsibility, not on behalf + of any other Contributor, and only if You agree to indemnify, + defend, and hold each Contributor harmless for any liability + incurred by, or claims asserted against, such Contributor by reason + of your accepting any such warranty or additional liability. + + END OF TERMS AND CONDITIONS + diff --git a/CodeVirtualizer/build/obj/wkit/README.md b/CodeVirtualizer/build/obj/wkit/README.md new file mode 100644 index 0000000..1952cfc --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/README.md @@ -0,0 +1,60 @@ +# Intel X86 Encoder Decoder (Intel XED) + +![.github/workflows/ci.yml](https://github.com/intelxed/xed/workflows/.github/workflows/ci.yml/badge.svg) + +## Doxygen API manual and source build manual: + +https://intelxed.github.io + +## Bugs: + +https://github.com/intelxed/xed/issues/new + + +## Abbreviated *GITHUB* building instructions: + +```shell +git clone https://github.com/intelxed/xed.git xed +git clone https://github.com/intelxed/mbuild.git mbuild +cd xed +./mfile.py +``` + +then get your libxed.a from the obj directory. +Add " --shared" if you want a shared object build. +Add " install" if you want the headers & libraries put in to a kit in the "kits" directory. +Add "C:/python3/python " before "./mfile.py" if on windows. + +## How to build the examples: + +There are two options: + +1) When building libxed you can also build the examples, from the main directory (above examples): + +```shell +./mfile.py examples +``` + +and the compiled examples will be in obj/examples. + +2) Build a compiled "kit" and the build the examples from within the kit: + +```shell +./mfile.py install +cd kits +cd +cd examples +./mfile.py +``` + + +See source build documentation for more information. + +## Binary size? + +Concerned about large libraries or binaries? There are several options: + +1. Consider building with "--limit-strings" +2. Strip the binaries +3. Consider doing an encoder-only or decoder-only build if you only need one or the other. + diff --git a/CodeVirtualizer/build/obj/wkit/examples/README.txt b/CodeVirtualizer/build/obj/wkit/examples/README.txt new file mode 100644 index 0000000..6d92252 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/README.txt @@ -0,0 +1,49 @@ +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + + +To build the examples, a relatively recent version of python 2.7 is required. + +================================ +STATIC LIBRARY XED BUILD: +================================ + + Linux or Mac: + + % ./mfile.py + + Windows: + + % C:/python27/python mfile.py + +================================ +DYNAMIC LIBRARY XED BUILD: +================================ + +If you have a a shared-object (or DLL build on windows) you must also include +"--shared" on the command line: + + Linux or Mac: + + % ./mfile.py --shared + + Windows: + + % C:/python27/python mfile.py --shared + +Add "--help" (no quotes) for more build options. diff --git a/CodeVirtualizer/build/obj/wkit/examples/avltree.c b/CodeVirtualizer/build/obj/wkit/examples/avltree.c new file mode 100644 index 0000000..59cc5c6 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/avltree.c @@ -0,0 +1,400 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "avltree.h" +#include +#include +#include +#include + +typedef struct avl_node_s { + avl_key_t key; + void* data; + int32_t balance_factor; + uint32_t height; + struct avl_node_s* left; + struct avl_node_s* right; +} avl_node_t; + +static void pad(int d) { + int i; + for(i=0;iheight, + n->balance_factor, + (uint64_t) n->key, + n->data); + print_node(n->left, cur_depth+1); + print_node(n->right, cur_depth+1); + } + else + fprintf(stdout, "*empty*\n"); + +} +#if 0 +static void print_tree(avl_tree_t* tree) { + printf("=============\n"); + if (tree->top) + print_node(tree->top, 0); + else + fprintf(stdout, "*empty tree*\n"); + printf("=============\n"); +} +#endif + +void avl_tree_init(avl_tree_t* tree) +{ + tree->top = 0; +} + +static void clear(avl_node_t* n, int free_data) // recursive +{ + if (n->left) + clear(n->left, free_data); + if (n->right) + clear(n->right, free_data); + if (free_data && n->data) + free((void*)n->data); + free((void*)n); +} +void avl_tree_clear(avl_tree_t* tree, int free_data) +{ + if (tree->top) { + clear(tree->top, free_data); + } + tree->top = 0; +} + +static avl_node_t* find_node(avl_node_t* n, avl_key_t key) //recursive +{ + if (n->key == key) + return n; + else if (n->key > key && n->left) + return find_node(n->left, key); + else if (n->right) + return find_node(n->right, key); + return 0; +} + +static void* find(avl_node_t* n, avl_key_t key) //recursive +{ + if (n) + { + avl_node_t* x = find_node(n,key); + if (x) + return x->data; + } + return 0; +} + +void* avl_find (avl_tree_t* tree, avl_key_t key) +{ + return find(tree->top, key); +} + + + + + + + + + + +static avl_node_t* find_node_lower_bound(avl_node_t* n, avl_key_t key, + avl_node_t** lb) //recursive +{ + //printf("NODE KEY=%lld\n", n->key); + if (n->key == key){ + *lb = n; + return n; + } + else if (n->key > key && n->left) { + //printf("\tGO LEFT\n"); + return find_node_lower_bound(n->left, key, lb); + } + + if (n->key < key) { + // store the max lower bound we encounter when node key is < search + // key. + if (*lb && (*lb)->key < n->key) + *lb = n; + else if (*lb == 0) + *lb = n; + } + + if (n->right) { + //printf("\tGO RIGHT\n"); + return find_node_lower_bound(n->right, key, lb); + } + return *lb; +} + +static void* find_lower_bound(avl_node_t* n, avl_key_t key, + avl_key_t* lbkey) // output +{ + avl_node_t* lbound = 0; + if (n) + { + (void) find_node_lower_bound(n,key, &lbound); + if (lbound) { + *lbkey = lbound->key; + return lbound->data; + } + } + return 0; +} +void* avl_find_lower_bound (avl_tree_t* tree, avl_key_t key, + avl_key_t* lbkey) // output +{ + return find_lower_bound(tree->top, key, lbkey); +} + + + + + + +static avl_node_t* make_node(avl_key_t key, void* value) +{ + avl_node_t* n = (avl_node_t*) malloc(sizeof(avl_node_t)); + assert(n != 0); + n->key = key; + n->data = value; + n->balance_factor = 0; + n->height = 1; + n->left = n->right = 0; + return n; +} + +static uint32_t mmax(uint32_t a, uint32_t b) { + return (a>b)?a:b; +} + +static uint32_t update_height(avl_node_t* n) +{ + avl_node_t* a = n->left; + avl_node_t* b = n->right; + return 1 + mmax((a?a->height:0), (b?b->height:0)); +} +static int32_t update_balance(avl_node_t* n) +{ + avl_node_t* a = n->left; + avl_node_t* b = n->right; + return (int32_t)(a?a->height:0) - (int32_t)(b?b->height:0); +} +static void update_height_and_balance(avl_node_t* n) +{ + n->height = update_height(n); + n->balance_factor = update_balance(n); +} +static avl_node_t* left_left(avl_node_t* n) // changes top node +{ + // knock the tree over to the right, making n->left in to the new top node. + // juggle subtrees + + avl_node_t* new_top = n->left; + avl_node_t* old_top = n; + old_top->left = new_top->right; + new_top->right = old_top; + update_height_and_balance(old_top); + update_height_and_balance(new_top); + return new_top; +} +static avl_node_t* left_right(avl_node_t* n) +{ + // replace n->left with n->left->right, juggle subtrees + avl_node_t* l_node = n->left; + avl_node_t* lr_node = n->left->right; + n->left = lr_node; + l_node->right = lr_node->left; + lr_node->left = l_node; + update_height_and_balance(l_node); + update_height_and_balance(lr_node); + return n; +} +static avl_node_t* right_left(avl_node_t* n) +{ + // replace n->right with n->right->left, juggle subtrees + avl_node_t* r_node = n->right; + avl_node_t* rl_node = n->right->left; + n->right = rl_node; + r_node->left = rl_node->right; + rl_node->right = r_node; + update_height_and_balance(r_node); + update_height_and_balance(rl_node); + return n; +} +static avl_node_t* right_right(avl_node_t* n) // changes top node +{ + // knock the tree over to the left, making n->right in to the new top node. + // juggle subtrees + avl_node_t* new_top = n->right; + avl_node_t* old_top = n; + old_top->right = new_top->left; + new_top->left = old_top; + update_height_and_balance(old_top); + update_height_and_balance(new_top); + return new_top; +} + +static avl_node_t* insert(avl_node_t* n, + avl_key_t key, void* value, int free_data) +{ + if (n->key == key) { + if (n->data && free_data) + free((void*)n->data); + n->data = value; + } + else if (n->key > key) { + if (n->left) { + n->left = insert(n->left, key, value, free_data); + update_height_and_balance(n); + } + else { + n->left = make_node(key,value); + update_height_and_balance(n); + } + } + else if (n->key < key) { + if (n->right) { + n->right = insert(n->right, key, value, free_data); + update_height_and_balance(n); + } + else { + n->right = make_node(key,value); + update_height_and_balance(n); + } + } + // rebalancing might change the current node + if (n->balance_factor >= 2) // heavy on the left + { + if (n->left->balance_factor == -1) { + // subtree is heavy right, make it heavy left, then knock it over + n = left_right(n); + n = left_left(n); + } + else if (n->left->balance_factor == 1) { + // subtree is heavy left, knock it over + n = left_left(n); + } + } + else if (n->balance_factor <= -2) // heavy on the right + { + if (n->right->balance_factor == 1) { + // subtree is heavy left, make it heavy right, then knock it over + n = right_left(n); + n = right_right(n); + } + else if (n->right->balance_factor == -1) { + // subtree is heavy right, knock it over + n = right_right(n); + } + } + update_height_and_balance(n); // FIXME: redundant, remove this + if (n->balance_factor <= -2 || n->balance_factor >= 2) { + printf("FAIL\n"); + print_node(n, 0); + assert (n->balance_factor < 2 && n->balance_factor > -2); + } + return n; +} + +void avl_insert(avl_tree_t* tree, avl_key_t key, void* value, int free_data) +{ + //rebalancing can change what the 'tree' points to as its top node. + if (tree->top) + tree->top = insert(tree->top, key, value, free_data); + else + tree->top = make_node(key,value); + //print_tree(tree); +} + + +typedef struct avl_link_node_s { + avl_node_t* node; + struct avl_link_node_s* next; +} avl_link_node_t; + +void avl_iter_begin( avl_iter_t* iter, avl_tree_t* tree) +{ + iter->head = 0; + iter->tail = 0; + if (tree->top) { + avl_link_node_t* n = (avl_link_node_t*)malloc(sizeof(avl_link_node_t)); + assert(n != 0); + n->node = tree->top; + n->next = 0; + iter->head = n; + iter->tail = n; + } + +} + +void* avl_iter_current(avl_iter_t* iter) +{ + return iter->head->node->data; +} + +static void add_link_node(avl_iter_t* iter, avl_node_t* anode) +{ + if (anode) + { + avl_link_node_t* n = (avl_link_node_t*)malloc(sizeof(avl_link_node_t)); + assert(n != 0); + n->next = 0; + n->node = anode; + iter->tail->next = n; + iter->tail = n; + } + } +void avl_iter_increment(avl_iter_t* iter) +{ + avl_link_node_t* p; + add_link_node(iter, iter->head->node->left); + add_link_node(iter, iter->head->node->right); + p = iter->head; + iter->head = p->next; + free(p); +} +int avl_iter_done(avl_iter_t* iter) +{ + return (iter->head == 0); +} + +void avl_iter_cleanup(avl_iter_t* iter) // call if end iteration early +{ + struct avl_link_node_s* p = iter->head; + while(p) { + struct avl_link_node_s* t = p; + p = t->next; + free(t); + } +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/avltree.h b/CodeVirtualizer/build/obj/wkit/examples/avltree.h new file mode 100644 index 0000000..8494a92 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/avltree.h @@ -0,0 +1,74 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#if !defined(_AVL_TREE_H_) +# define _AVL_TREE_H_ + +#include +#if defined(AVL_KEY_32_BIT) +typedef uint32_t avl_key_t; +#else +typedef uint64_t avl_key_t; +#endif + + +struct avl_node_s; // fwd decl + +typedef struct { + struct avl_node_s* top; +} avl_tree_t; + +void avl_tree_init(avl_tree_t* tree); + +// clear removes the tree nodes, not the data +void avl_tree_clear(avl_tree_t* tree, int free_data); + +void* avl_find(avl_tree_t* tree, avl_key_t key); + +// find the node with a key <= the given key. Returns found key value in +// lbkey and the data payoad as a return value. +void* avl_find_lower_bound(avl_tree_t* tree, avl_key_t key, + avl_key_t* lbkey); // output + + +// insert notices key collisions and will free the associated data if +// free_data is nonzero. +void avl_insert(avl_tree_t* tree, avl_key_t key, void* value, int free_data); + +#if 0 // DELETE not done yet. +// return 1 on failure, 0 on success +int avl_delete(avl_tree_t* tree, avl_key_t key, int free_data); +#endif + + +struct avl_link_node_s; // fwd decl + +typedef struct avl_iter_s { + struct avl_link_node_s* head; + struct avl_link_node_s* tail; +} avl_iter_t; + + +void avl_iter_begin( avl_iter_t* iter,avl_tree_t* tree); +void* avl_iter_current(avl_iter_t* iter); +void avl_iter_increment(avl_iter_t* iter); +int avl_iter_done(avl_iter_t* iter); +void avl_iter_cleanup(avl_iter_t* iter); // call if end iteration early + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/mfile.py b/CodeVirtualizer/build/obj/wkit/examples/mfile.py new file mode 100644 index 0000000..470766d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/mfile.py @@ -0,0 +1,91 @@ +#!/usr/bin/env python +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +import sys +import os + +def _find_dir(d): + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +def _fatal(m): + sys.stderr.write("\n\nXED build error: %s\n\n" % (m) ) + sys.exit(1) + +def _try_mbuild_import(): + try: + import mbuild + return True + except: + return False + +def _find_add_import(d): + p = _find_dir(d) + if p and os.path.exists(p): + sys.path = [p] + sys.path + return + _fatal("Could not find {} directory".format(d)) + +def _find_mbuild_import(): + if _try_mbuild_import(): + return + _find_add_import('mbuild') + + +def _find_common(): + p = os.path.dirname(_find_dir('xed_build_common.py')) + if p and os.path.exists(p): + sys.path = [p] + sys.path + return + _fatal("Could not find xed_build_common.py") + +def setup(): + if sys.version_info[0] == 3 and sys.version_info[1] < 4: + _fatal("Need python version 3.4 or later.") + elif sys.version_info[0] == 2 and sys.version_info[1] < 7: + _fatal("Need python version 2.7 or later.") + _find_mbuild_import() + # when building in the source tree the xed_build_common.py file is + # in the parent directory of the examples. When building in the + # kit that file is in the example source directory. + _find_common() + + +def work(): + import xed_build_common + import xed_examples_mbuild + try: + retval = xed_examples_mbuild.execute() + except Exception as e: + xed_build_common.handle_exception_and_die(e) + return retval + +if __name__ == "__main__": + setup() + retval = work() + sys.exit(retval) + diff --git a/CodeVirtualizer/build/obj/wkit/examples/udhelp.H b/CodeVirtualizer/build/obj/wkit/examples/udhelp.H new file mode 100644 index 0000000..c72e5f1 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/udhelp.H @@ -0,0 +1,80 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#if !defined(_UDHELP_H_) +#define _UDHELP_H_ + +#if defined(_MSC_VER) && defined(XED_DBGHELP) +// only try to use dbghelp on MSVS8 (2005) or later versions. +# if _MSC_VER >= 1400 +# define XED_USING_DEBUG_HELP +# endif +#endif + +#if defined(XED_USING_DEBUG_HELP) +#include +#include +extern "C" { +#include "xed-symbol-table.h" +} +class dbg_help_client_t { + + DWORD error; + HANDLE hProcess; + DWORD processId; + + DWORD64 gBaseOfDll; + DWORD64 actual_base; + char* gModule; + + bool initialized; + + static BOOL CALLBACK enum_modules( + LPSTR ModuleName, + DWORD64 BaseOfDll, + PVOID UserContext ); + + static BOOL CALLBACK dbg_help_client_t::enum_sym( + PSYMBOL_INFO pSymInfo, + ULONG SymbolSize, + PVOID UserContext); + + public: + + xed_symbol_table_t sym_tab; // EXPOSED + + dbg_help_client_t(); + + // returns 1 on success and 0 on failure. sets "initialized" to true on + // success + int init(char const* const fpath, + char const* const search_path); + bool valid() const { return initialized; } + + // if offset is nonzero, it will return best-fit symbols. If offset=0 + // then only exact symbols are returned. + bool get_symbol(DWORD64 address, char* symbol_name, + int sym_name_buflen, DWORD64* offset=0); + + xed_bool_t get_file_and_line(xed_uint64_t address, + char** filename, + xed_uint32_t* line, + xed_uint32_t* column); + bool cleanup(); +}; +#endif +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/udhelp.cpp b/CodeVirtualizer/build/obj/wkit/examples/udhelp.cpp new file mode 100644 index 0000000..5131e8d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/udhelp.cpp @@ -0,0 +1,323 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "udhelp.H" +#include +extern "C" { +#include "xed/xed-interface.h" +#include "xed-examples-util.h" // xed_strdup +} +#include +#include +#include +#include +#include +#include + +#if defined(XED_USING_DEBUG_HELP) && defined(XED_DECODER) +BOOL CALLBACK dbg_help_client_t::enum_modules( + LPSTR ModuleName, + DWORD64 BaseOfDll, + PVOID UserContext ) +{ + dbg_help_client_t* pthis = (dbg_help_client_t*)UserContext; + pthis->gBaseOfDll = BaseOfDll; + pthis->gModule=ModuleName; + return TRUE; +} + + + + +BOOL CALLBACK dbg_help_client_t::enum_sym( + PSYMBOL_INFO pSymInfo, + ULONG SymbolSize, + PVOID UserContext) +{ + dbg_help_client_t* pthis = (dbg_help_client_t*)UserContext; + xed_uint64_t addr = static_cast(pSymInfo->Address); + + xst_add_global_symbol(&pthis->sym_tab, + addr, + xed_strdup(pSymInfo->Name)); + return TRUE; + (void)SymbolSize; //pacify compiler warning about unused param +} + + +dbg_help_client_t::dbg_help_client_t() { + xed_symbol_table_init(&sym_tab); + initialized=false; +} + + +char* find_base_path(char* driver_name) { + char* x; + char* path = xed_strdup(driver_name); + x = strrchr(path,'\\'); + if (x) { + *x = 0; + } + else { + x = strrchr(path,'/'); + if (x) { + *x = 0; + } + else { + /* FIXME */ + } + } + return path; +} + +static char* append3(const char* s1, const char* s2, const char* s3) { + xed_uint_t n = 1; + char* p = 0; + assert(s1 != 0); + n += xed_strlen(s1); + if (s2) n += xed_strlen(s2); + if (s3) n += xed_strlen(s3); + p = (char*) malloc(sizeof(char)*n); + n=xed_strncpy(p,s1,n); + if (s2) n=xed_strncat(p,s2,n); + if (s3) n=xed_strncat(p,s3,n); + return p; +} + + + + +typedef union { + short a[2]; + int i; +} union16_t; + +void get_dll_version(char* file_name, short u[4]) { + VS_FIXEDFILEINFO* vsf; + DWORD verlen, error, handle; + UINT len; + BOOL ret; + char* ver; + + verlen = GetFileVersionInfoSize(file_name,&handle); + if (verlen == 0) { + error = GetLastError(); + fprintf(stderr,"GetFileVersionInfoSize: error code was %u (0x%x)\n", + error, error); + exit(1); + } + + ver = new char[verlen]; + ret = GetFileVersionInfo(file_name,handle,verlen,ver); + if (!ret) { + error = GetLastError(); + fprintf(stderr, + "GetFileVersionInfo: error code was %u (0x%x)\n", error, error); + exit(1); + } + + // get a pointer to a location in ver stored in vsf + ret = VerQueryValue(ver,"\\",(LPVOID*)&vsf,&len); + if (!ret) { + error = GetLastError(); + fprintf(stderr, + "VerQueryValue: error code was %u (0x%x)\n", error, error); + exit(1); + } + assert(len == sizeof(VS_FIXEDFILEINFO)); + + union16_t upper,lower; + upper.i = vsf->dwFileVersionMS; + lower.i = vsf->dwFileVersionLS; + u[0] = upper.a[1]; + u[1] = upper.a[0]; + u[2] = lower.a[1]; + u[3] = lower.a[0]; + + delete[] ver; +} + + + +int dbg_help_client_t::init(char const* const path, + char const* const search_path) +{ + DWORD64 dwBaseAddr=0; + + int chars; + char exe_path[MAX_PATH]; + chars = GetModuleFileName(NULL, exe_path, MAX_PATH); + if (chars == 0) { + fprintf(stderr,"Could not find base path for XED executable\n"); + fflush(stderr); + exit(1); + } + + char* dir = find_base_path(exe_path); + + char* dbghelp = append3(dir,"\\","dbghelp.dll"); +#if defined(PIN_CRT) + if (access(dbghelp,4) != 0) +#else + if (_access_s(dbghelp,4) != 0) +#endif + { + return 0; + } + + SymSetOptions(SYMOPT_UNDNAME | SYMOPT_LOAD_LINES ); + hProcess = GetCurrentProcess(); + + if (SymInitialize(hProcess, NULL, FALSE)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymInitialize returned error : %u 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + + if (search_path) + { + if (SymSetSearchPath(hProcess, search_path)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymSetSearchPath returned error : %u 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + } + + actual_base = SymLoadModuleEx(hProcess, NULL, path, NULL, + dwBaseAddr, 0, NULL, 0); + if (actual_base) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymLoadModuleEx returned error : %u 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + + + if (SymEnumerateModules64(hProcess, + (PSYM_ENUMMODULES_CALLBACK64)enum_modules, this)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymEnumerateModules64 returned error : %d 0x%x\n", + error, error); + fflush(stderr); + return 0; + } + + if (SymEnumSymbols(hProcess, actual_base, 0, enum_sym, this)) { + // nothing + } + else { + error = GetLastError(); + fprintf(stderr,"SymEnumSymbols failed: %d 0x%x\n", error, error); + fflush(stderr); + return 0; + } + + initialized = true; + return 1; +} + +bool dbg_help_client_t::get_symbol(DWORD64 address, char* symbol_name, + int sym_name_buflen, DWORD64* offset) +{ + DWORD64 displacement; + ULONG64 n = (sizeof(SYMBOL_INFO) + + sym_name_buflen*sizeof(TCHAR) + + sizeof(ULONG64) - 1) / sizeof(ULONG64); + ULONG64* buffer = new ULONG64[n]; + PSYMBOL_INFO pSymbol = (PSYMBOL_INFO)buffer; + + pSymbol->SizeOfStruct = sizeof(SYMBOL_INFO); + pSymbol->MaxNameLen = sym_name_buflen; + + if (SymFromAddr(hProcess, address, &displacement, pSymbol)) { + if (offset) + *offset = displacement; + if (offset || displacement == 0) { + xed_strncpy(symbol_name, pSymbol->Name, sym_name_buflen); + // force a null. WINDOWS doesn't have strlcpy() + symbol_name[sym_name_buflen-1] = 0; + delete [] buffer; + return 0; + } + else { + /* not at the beginning of a symbol and no offset was supplied */ + delete [] buffer; + return 1; + } + } + else { + error = GetLastError(); + fprintf(stderr, + "SymFromAddr returned error : %d 0x%x for address %llx\n", + error, error, address); + delete [] buffer; + return 1; + } + + +} + +bool dbg_help_client_t::cleanup() { + if (SymCleanup(hProcess)) { + return 0; + } + else { + error = GetLastError(); + fprintf(stderr, + "SymCleanup returned error : %d 0x%x\n", error,error); + return 1; + } +} + +xed_bool_t dbg_help_client_t::get_file_and_line(xed_uint64_t address, + char** filename, + xed_uint32_t* line, + xed_uint32_t* column) +{ + DWORD dw_column; + IMAGEHLP_LINE64 imgline; + imgline.SizeOfStruct = sizeof(IMAGEHLP_LINE64); + if (SymGetLineFromAddr64(hProcess, address, &dw_column, &imgline)) + { + xed_uint32_t len = xed_strlen(imgline.FileName); + *column = dw_column; + *line = imgline.LineNumber; + *filename =(char*) malloc(len+1); + xed_strncpy(*filename, imgline.FileName, len+1); + return 1; //success + } + return 0; //failed +} + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse-main.c b/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse-main.c new file mode 100644 index 0000000..c05d500 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse-main.c @@ -0,0 +1,1041 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// more natural assembly language parser + +#include +#include +#include +#include + +#include "xed-asmparse.h" + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" + +static xed_uint_t intel_asm_emits=0; + +static xed_bool_t test_has_relbr(const xed_inst_t* p); +static xed_bool_t has_relbr(xed_iclass_enum_t iclass); + +static void delete_string_list(xed_str_list_t* h) { + // clean up memory allocated + xed_str_list_t* p=h; + while(p) { + xed_str_list_t* t=0; + free(p->s); // free the string content + t = p->next; + free(p); // free the node itself + p = t; + } +} + + +static char* duplicate(char const* const s) { + return xed_strdup(s); +} + +static xed_str_list_t* split_string(const char* p) +{ + xed_str_list_t* q = xed_tokenize(p,";"); + // the strings returned from xed_tokenize are all part of the original + // string. we duplicate them for easier cleanup later + xed_str_list_t* a = q; + while(a) { + a->s = duplicate(a->s); + a = a->next; + } + return q; +} + +static xed_str_list_t* process_args(int argc, char** argv, + xed_uint_t* mode, + int* verbose) +{ + // sets mode, verbose and fills in a linked list of strings as the + // return value. Also sets intel_asm_emits. + + const char* usage = "Usage: %s [-16|-32|-64] [--emit] [-v|-q] \n" + "\tThe assembly line can have semicolon separators " + "to allow for multiple instructions.\n" + "\tThe --emit option changes output to Intel compiler __emit lines.\n" + "\n\n"; + + xed_str_list_t* string_list; + int i = 0; + unsigned int len = 0; + char* s = 0; + char* p = 0; + char* q = 0; + int keep_going = 1; + int mode_found = 0; + int first_arg = 1; + if (argc<=1) { + asp_error_printf(usage, argv[0]); + exit(1); + } + *mode = 32; + while(keep_going) { + keep_going = 0; + if (first_arg >= argc) + break; + if (strcmp("-32",argv[first_arg])==0) { + if (mode_found) { + asp_error_printf("Duplicate mode knob: %s\n", argv[first_arg]); + exit(1); + } + mode_found = 1; + keep_going = 1; + *mode = 32; + first_arg++; + } + else if (strcmp("-16",argv[first_arg])==0) { + if (mode_found) { + asp_error_printf("Duplicate mode knob: %s\n", argv[first_arg]); + exit(1); + } + mode_found = 1; + keep_going = 1; + *mode = 16; + first_arg++; + } + else if (strcmp("-64",argv[first_arg])==0) { + if (mode_found) { + asp_error_printf("Duplicate mode knob: %s\n", argv[first_arg]); + exit(1); + } + mode_found = 1; + keep_going = 1; + *mode = 64; + first_arg++; + } + else if (strcmp("-v",argv[first_arg])==0) { + keep_going = 1; + (*verbose)++; + first_arg++; + } + else if (strcmp("-q", argv[first_arg])== 0) { + keep_going = 1; + *verbose = 0; + first_arg++; + } + else if (strcmp("--emit", argv[first_arg])== 0) { + intel_asm_emits=1; + keep_going = 1; + first_arg++; + } + + } + for(i=first_arg;ifirst_arg) // spaces between secondary args + *p++ = ' '; + q = argv[i]; + while(*q) // copy argument + *p++ = *q++; + } + *p = 0; // null terminate + + string_list = split_string(s); + free(s); + return string_list; +} + +static void set_state(xed_state_t* dstate, xed_enc_line_parsed_t* v) { + xed_state_zero(dstate); + + if (v->mode == 16) { + dstate->stack_addr_width=XED_ADDRESS_WIDTH_16b; + dstate->mmode=XED_MACHINE_MODE_LEGACY_16; + } + else if (v->mode == 32) { + dstate->stack_addr_width=XED_ADDRESS_WIDTH_32b; + dstate->mmode=XED_MACHINE_MODE_LEGACY_32; + } + else if (v->mode == 64) { + dstate->stack_addr_width=XED_ADDRESS_WIDTH_64b; + dstate->mmode=XED_MACHINE_MODE_LONG_64; + } + else { + asp_error_printf("Invalid mode: %d\n", v->mode); + exit(1); + } + +} + +/* Make string p1 + "_" + p2, put it into result + Check if matching iclass exists. + If it exists, return true, otherwise false */ +static xed_bool_t probe_iclass_string(const char *p1, const char *p2, + char *result, int maxlen) { + xed_strncpy(result, p1, maxlen); + xed_strncat(result, "_", maxlen); + xed_strncat(result, p2, maxlen); + xed_iclass_enum_t valid_iclass = str2xed_iclass_enum_t(result); + return (valid_iclass != XED_ICLASS_INVALID); +} + +static void process_prefixes(xed_enc_line_parsed_t* v, + xed_encoder_instruction_t* inst) +{ + slist_t* q = v->prefixes; + while(q) { + if (strcmp(q->s, "LOCK") == 0) { + /* nothing required */ + } + else if (strcmp(q->s, "REP") == 0 || + strcmp(q->s, "REPE") == 0) { + xed_rep(inst); + } + else if (strcmp(q->s, "XRELEASE") == 0) { + xed_rep(inst); + } + else if (strcmp(q->s, "XACQUIRE") == 0) { + xed_repne(inst); + } + else if (strcmp(q->s, "REPNE") == 0) { + xed_repne(inst); + } + else if (strcmp(q->s, "DATA16") == 0) { + //FIXME: data16 + } + else if (strcmp(q->s, "DATA32") == 0) { + //FIXME: data32 + } + else if (strcmp(q->s, "ADDR16") == 0) { + //FIXME: addr16 + } + else if (strcmp(q->s, "ADDR32") == 0) { + //FIXME: addr32 + } + else if (strcmp(q->s, "REX") == 0) { + //FIXME: rex + } + else if (strcmp(q->s, "REXW") == 0) { + //FIXME: rexw + } + else { + asp_error_printf("Unhandled prefix: %s\n", q->s); + exit(1); + } + q = q->next; + } +} + +typedef struct { + const char* s; + xed_uint_t src; + xed_uint_t dst; +} bcast_info_t; + +static const bcast_info_t bcast[] = { + { "{1TO2}", 1, 2 }, + { "{1TO4}", 1, 4 }, + { "{1TO8}", 1, 8 }, + { "{1TO16}", 1, 16 }, + { "{1TO32}", 1, 32 }, + { "{1TO64}", 1, 64 }, + { 0, 0, 0} +}; + +static void process_mem_decorator(slist_t* decos, xed_encoder_operand_t* operand, xed_uint_t* pos) +{ + + slist_t* d = decos; + xed_uint_t i = *pos; + int found_a_bcast_decorator = 0; + while(d && !found_a_bcast_decorator) { + xed_uint_t j=0; + for(j=0;bcast[j].s;j++) { + if (strcmp(bcast[j].s,d->s)==0) { + //FIXME: RECORD WHICH DECORATOR IS FOUND SO WE CAN COMPUTE + // THE VL FOR FPCLASS AND VCMP TYPE INSTR. + operand[i++] = xed_other(XED_OPERAND_BCAST,1); + found_a_bcast_decorator = 1; + break; + } + } + d = d->next; + } + *pos = i; + + if (decos && !found_a_bcast_decorator) { + asp_error_printf("Bad memory decorator: "); + d = decos; + while (d) { + asp_error_printf("%s ", d->s); + d = d->next; + } + exit(1); + } +} + +static void check_too_many_operands(int op_pos) { + if (op_pos >= XED_ENCODER_OPERANDS_MAX) { + asp_error_printf("Too many operands\n"); + exit(1); + } +} + +static int process_rc_sae(char const* s,xed_encoder_operand_t* operand, xed_uint_t* pos) +{ +#if defined(XED_SUPPORTS_AVX512) + xed_uint_t i = *pos; + if (strcmp("{RNE-SAE}",s)==0) { + check_too_many_operands(i+1); + operand[i++] = xed_other(XED_OPERAND_ROUNDC,1); + operand[i++] = xed_other(XED_OPERAND_SAE,1); + *pos = i; + return 1; + } + else if (strcmp("{RD-SAE}",s)==0) { + check_too_many_operands(i+1); + operand[i++] = xed_other(XED_OPERAND_ROUNDC,2); + operand[i++] = xed_other(XED_OPERAND_SAE,1); + *pos = i; + return 1; + } + else if (strcmp("{RU-SAE}",s)==0) { + check_too_many_operands(i+1); + operand[i++] = xed_other(XED_OPERAND_ROUNDC,3); + operand[i++] = xed_other(XED_OPERAND_SAE,1); + *pos = i; + return 1; + } + else if (strcmp("{RZ-SAE}",s)==0) { + check_too_many_operands(i+1); + operand[i++] = xed_other(XED_OPERAND_ROUNDC,4); + operand[i++] = xed_other(XED_OPERAND_SAE,1); + *pos = i; + return 1; + } + else if (strcmp("{SAE}",s)==0) { + check_too_many_operands(i); + operand[i++] = xed_other(XED_OPERAND_SAE,1); + *pos = i; + return 1; + } +#endif + asp_error_printf("Unhandled decorator: %s\n",s); + exit(1); + return 0; + (void) operand; (void) pos; +} + + +static xed_uint_t get_nbits_signed(xed_int64_t imm_val) { + xed_uint_t nbits = 0; + xed_uint8_t legal_widths = 1|2|4|8; // bytes + xed_uint_t nbytes = 0; + nbytes = xed_shortest_width_signed(imm_val, legal_widths); + nbits = 8 * nbytes; + return nbits; +} +static xed_uint_t get_nbits_unsigned(xed_uint64_t imm_val) { + xed_uint_t nbits = 0; + xed_uint8_t legal_widths = 1|2|4|8; // bytes + xed_uint_t nbytes = 0; + nbytes = xed_shortest_width_unsigned(imm_val, legal_widths); + nbits = 8 * nbytes; + return nbits; +} + +static xed_uint_t get_nbits_signed_disp(xed_int64_t disp_val) { + // displacements are 1 or 4 bytes in 32/64b addressing. + // FIXME: In 16b addressing one can have 16b displacements. + xed_uint_t nbits = 0; + xed_uint8_t legal_widths = 1|4; // bytes + xed_uint_t nbytes = 0; + if (disp_val == 0) // FIXME: how to force nonzero displacement? + return 0; + nbytes = xed_shortest_width_signed(disp_val, legal_widths); + nbits = 8 * nbytes; + return nbits; +} + +static xed_reg_class_enum_t get_gpr_reg_class(xed_reg_enum_t reg) { + xed_reg_class_enum_t rc = xed_reg_class(reg); + if (rc == XED_REG_CLASS_GPR) { + rc = xed_gpr_reg_class(reg); + return rc; + } + return XED_REG_CLASS_INVALID; +} + +static void set_eosz(xed_reg_enum_t reg, + xed_uint_t* eosz) +{ + xed_reg_class_enum_t rc = get_gpr_reg_class(reg); + if (rc == XED_REG_CLASS_GPR16) { + if (*eosz < 16) + *eosz = 16; + } + else if (rc == XED_REG_CLASS_GPR32) { + if (*eosz < 32) + *eosz = 32; + } + else if (rc == XED_REG_CLASS_GPR64) { + asp_dbg_printf("#SET EOSZ 64\n"); + *eosz=64; + } +} + + +static void set_mode(xed_reg_enum_t reg, + int* mode) +{ + // only set mode if it is set to something too narrow. Note: instead + // we could simply only infer mode if the mode is not set explicitly + // (==0) which would facilitate some error checking. + + xed_reg_class_enum_t rc = get_gpr_reg_class(reg); + if (rc == XED_REG_CLASS_GPR16) { + if (*mode < 16) + *mode = 16; + if (reg >= XED_REG_R8W) + *mode = 64; + } + else if (rc == XED_REG_CLASS_GPR32) { + if (*mode < 32) + *mode = 32; + if (reg >= XED_REG_R8D) + *mode = 64; + } + else if (rc == XED_REG_CLASS_GPR64) { + *mode=64; + } +} + + +static void set_mode_vec(xed_reg_enum_t reg, + int* mode) +{ + //if using simd (xmm/ymm/zmm) regs > 7, then set 64b mode + xed_reg_class_enum_t rc = xed_reg_class(reg); + xed_uint_t regid = 0; + if (rc == XED_REG_CLASS_XMM) { + regid = reg - XED_REG_XMM0; + } + else if (rc == XED_REG_CLASS_YMM) { + regid = reg - XED_REG_YMM0; + } +#if defined(XED_SUPPORTS_AVX512) + else if (rc == XED_REG_CLASS_ZMM) { + regid = reg - XED_REG_ZMM0; + } +#endif + if (regid > 7 && *mode != 64) { + asp_printf("Forcing mode to 64b based on regs used\n"); + *mode = 64; + } +} + +static xed_bool_t string_number_is_signed(const char* s) +{ + if (*s == '+' || *s == '-') + return 1; + return 0; +} + +/* Return true for e.g. strings "0x0123", "-0123" + Return false if no padding zeroes */ +static xed_bool_t string_has_padding_zeroes(const char* s) +{ + if (*s == '+' || *s == '-') /* skip leading sign */ + s++; + if (*s == '0' && *(s + 1) == 'X') /* skip hexadecimal prefix */ + s += 2; + return (*s == '0'); +} + +/* A nibble is a 4 bits wide hexadecimal digit. + Note that decimal digits are not nibbles but + the difference is ignored for the purposes of detecting + the literal's width */ +static xed_uint_t count_nibbles(const char *s) +{ + if (*s == '+' || *s == '-') /* skip leading sign */ + s++; + if (*s == '0' && *(s + 1) == 'X') /* skip hexadecimal prefix */ + s += 2; + return xed_strlen(s); + } + +static char const* const kmasks[] = { "{K0}","{K1}","{K2}","{K3}","{K4}","{K5}","{K6}","{K7}", 0 }; + +/* If user padded the number with leading zeroes, consider this to be + an attempt to precisely control the width of the literal. Otherwise, + choose a width that is just wide enough to fit the value */ +static int get_constant_width(char *text, int64_t val) { + if (string_has_padding_zeroes(text)) + return 4 * count_nibbles(text); + if (string_number_is_signed(text)) + return get_nbits_signed(val); + return get_nbits_unsigned((xed_uint64_t)val); +} + +static void process_operand(xed_enc_line_parsed_t* v, + opnd_list_t* q, + xed_uint_t* noperand, + xed_encoder_operand_t* operands, + xed_uint_t* has_imm0, + xed_uint_t* eosz) +{ + slist_t* d = 0; + int found_a_kmask = 0; + + xed_uint_t i = *noperand; + + switch (q->type) { + case OPND_REG: { + xed_reg_enum_t reg = q->reg; + if (reg == XED_REG_INVALID) { + asp_error_printf("Bad register: %s\n", q->s); + exit(1); + } + + check_too_many_operands(i); + operands[i++] = xed_reg(reg); + set_eosz(reg, eosz); + set_mode_vec(reg, &(v->mode)); + } + break; + case OPND_DECORATOR: { + if (process_rc_sae(q->s, operands, &i)) { + check_too_many_operands(i); + } + else { + asp_error_printf("Bad decorator: %s\n", q->s); + exit(1); + } + } + break; + case OPND_IMM: { + xed_uint_t nbits = get_constant_width(q->s, q->imm); + uint64_t literal_val = (uint64_t)q->imm; + + if (has_relbr(v->iclass_e)) { + asp_dbg_printf("The literal is treated as relbranch\n"); + check_too_many_operands(i); + operands[i++] = xed_relbr(literal_val, nbits); + } + else { // literal immediate + if (*has_imm0 == 0) { + check_too_many_operands(i); + operands[i++] = xed_imm0(literal_val, nbits); //FIXME: cast or make imm0 signed? + *has_imm0 = 1; + } + else { + if (nbits != 8) { + asp_error_printf( + "The second literal constant can only be 8 bit wide\n"); + exit(1); + } + check_too_many_operands(i); + operands[i++] = xed_imm1(XED_STATIC_CAST(xed_uint8_t, q->imm)); + } + } + } + break; + case OPND_MEM: { + xed_reg_enum_t seg = XED_REG_INVALID; + xed_reg_enum_t base = XED_REG_INVALID; + xed_reg_enum_t indx = XED_REG_INVALID; + xed_uint_t scale = q->mem.nscale; + xed_uint_t displacement_bits = get_nbits_signed_disp(q->mem.ndisp); + xed_enc_displacement_t disp = xed_disp(q->mem.ndisp, displacement_bits); + xed_uint_t width_bits = q->mem.mem_bits; + + if (q->mem.base) + base = str2xed_reg_enum_t(q->mem.base); + if (q->mem.index) + indx = str2xed_reg_enum_t(q->mem.index); + if (q->mem.seg) + seg = str2xed_reg_enum_t(q->mem.seg); + + set_mode(base, &(v->mode)); + set_mode(indx, &(v->mode)); + set_mode_vec(indx, &(v->mode)); // for AVX512 gathers, scatters + check_too_many_operands(i); + operands[i++] = xed_mem_gbisd(seg, base, indx, scale, disp, width_bits); + process_mem_decorator(q->decorators, operands, &i); + } + break; + case OPND_FARPTR: { + if (*has_imm0) { + asp_error_printf( + "Long pointer cannot follow immediate operand\n"); + exit(1); + } + xed_uint16_t seg = (xed_uint16_t)q->farptr.seg_value; + xed_uint32_t offset = (xed_uint32_t)q->farptr.offset_value; + xed_uint_t seg_bits = get_constant_width(q->farptr.seg, + q->farptr.seg_value); + xed_uint_t offset_bits = get_constant_width(q->farptr.offset, + q->farptr.offset_value); + + seg_bits = seg_bits < 16 ? 16 : seg_bits; + if (seg_bits != 16) { + asp_error_printf( + "Segment value in far pointer must be 16 bits\n"); + exit(1); + } + + if (offset_bits > 32) { + asp_error_printf( + "Far pointer offset must be either 16 or 32 bits"); + exit(1); + } + + if (offset_bits <= 16) + offset_bits = 16; + else + offset_bits = 32; + *eosz = offset_bits; + + check_too_many_operands(i); + operands[i++] = xed_ptr(offset, offset_bits); + + /* segment is encoded as immediate and must follow offset */ + check_too_many_operands(i); + operands[i++] = xed_imm0(seg, seg_bits); + *has_imm0 = 1; + } + break; + default: + asp_error_printf("Bad operand encountered: %s", q->s); + exit(1); + } // switch (q->type) + + //Add k-mask decorators as operands. + //Not checking for multiple k-masks - Let XED do it; that would not encode. + d = q->decorators; + while(d && !found_a_kmask) { + xed_uint_t j; + for(j=0;kmasks[j];j++) { + if (strcmp(kmasks[j],d->s)==0) { + xed_reg_enum_t kreg = XED_REG_K0 + j; + check_too_many_operands(i); + operands[i++] = xed_reg(kreg); + found_a_kmask = 1; + break; + } + } + d = d->next; + } + *noperand = i; +} + + + +static xed_uint_t encode(xed_encoder_instruction_t* inst) +{ + xed_error_enum_t xed_error = XED_ERROR_NONE; + xed_bool_t convert_ok = 0; + xed_encoder_request_t enc_req; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int ilen = XED_MAX_INSTRUCTION_BYTES; + unsigned int olen = 0; + + + xed_encoder_request_zero_set_mode(&enc_req, &(inst->mode)); + convert_ok = xed_convert_to_encoder_request(&enc_req, inst); + if (!convert_ok) { + asp_error_printf("Conversion to encode request failed\n"); + exit(1); + } + xed_error = xed_encode(&enc_req, itext, ilen, &olen); + if (xed_error != XED_ERROR_NONE) { + asp_error_printf("Failed to encode input: %s\n", + xed_error_enum_t2str(xed_error)); + exit(1); + } + + if (intel_asm_emits) + xed_print_intel_asm_emit(itext,olen); + else + xed_print_bytes_pseudo_op(itext,olen); + return olen; +} + +static void process_other_decorator(char const* s, + xed_uint_t* noperand, + xed_encoder_operand_t* operands) + +{ + // handle zeroing. + // allow but ignore k-masks and broadcasts decorators. + + // rounding/sae indicators are required to be indepdent operands (at + // least for now) + +#if defined(XED_SUPPORTS_AVX512) + xed_uint_t i = *noperand; + + if (strcmp("{Z}",s) == 0) { + check_too_many_operands(i); + operands[i++] = xed_other(XED_OPERAND_ZEROING,1); + } + else { + + // allow kmasks, but nothing else + int j=0; + int found = 0; + for (j=0;kmasks[j];j++) { + if (strcmp(kmasks[j],s) == 0) { + found = 1; + break; + } + } + + if (!found) { + for(j=0;bcast[j].s;j++) { + if (strcmp(bcast[j].s,s)==0) { + found = 1; + break; + } + } + } + + if (!found) { + asp_error_printf("Unhandled decorator: %s\n",s); + exit(1); + } + } + + *noperand = i; +#else + (void) s; (void) noperand; (void)operands; +#endif + +} + +typedef struct { + const char *from; + const char *to; +} iclass_name_aliases_t; + + +static const iclass_name_aliases_t cmovcc_aliases[] = { + {"CMOVNAE" , "CMOVB"}, + {"CMOVC" , "CMOVB"}, + {"CMOVNA" , "CMOVBE"}, + {"CMOVNGE" , "CMOVL"}, + {"CMOVNG" , "CMOVLE"}, + {"CMOVAE" , "CMOVNB"}, + {"CMOVNC" , "CMOVNB"}, + {"CMOVA" , "CMOVNBE"}, + {"CMOVGE" , "CMOVNL"}, + {"CMOVG" , "CMOVNLE"}, + {"CMOVPO" , "CMOVNP"}, + {"CMOVNE" , "CMOVNZ"}, + {"CMOVPE" , "CMOVP"}, + {"CMOVE" , "CMOVZ"}, +}; +static const iclass_name_aliases_t setcc_aliases[] = { + {"SETNAE" , "SETB"}, + {"SETC" , "SETB"}, + {"SETNA" , "SETBE"}, + {"SETNGE" , "SETL"}, + {"SETNG" , "SETLE"}, + {"SETAE" , "SETNB"}, + {"SETNC" , "SETNB"}, + {"SETA" , "SETNBE"}, + {"SETGE" , "SETNL"}, + {"SETG" , "SETNLE"}, + {"SETPO" , "SETNP"}, + {"SETNE" , "SETNZ"}, + {"SETPE" , "SETP"}, + {"SETE" , "SETZ"}, +}; + +static const iclass_name_aliases_t jcc_aliases[] = { + {"JNAE" , "JB"}, + {"JC" , "JB"}, + {"JNA" , "JBE"}, + {"JNGE" , "JL"}, + {"JNG" , "JLE"}, + {"JAE" , "JNB"}, + {"JNC" , "JNB"}, + {"JA" , "JNBE"}, + {"JGE" , "JNL"}, + {"JG" , "JNLE"}, + {"JPO" , "JNP"}, + {"JNE" , "JNZ"}, + {"JPE" , "JP"}, + {"JE" , "JZ"}, +}; + +static xed_bool_t find_alias(const char* orig, + char* result, + int maxlen, + iclass_name_aliases_t const* const aliases, + size_t n_aliases) +{ + /* Internally, xed uses only one variant per each alias, + others have to be converted to it */ + + size_t i = 0; + for (i = 0; i < n_aliases; i++) { + const char *from = aliases[i].from; + const char *to = aliases[i].to; + if (!strncmp(orig, from, maxlen)) { + xed_strncpy(result, to, maxlen); + return 1; + } + } + return 0; +} + +/* Change result to alias mnemonic that is accepted by xed, return true + Otherwise keep it unchanged and return false */ +/* Internally, xed uses only one variant per each alias, + others have to be converted to it */ +static xed_bool_t find_jcc_alias(const char* orig, char* result, int maxlen) { + const size_t n_aliases = sizeof(jcc_aliases) / sizeof(jcc_aliases[0]); + return find_alias(orig, result, maxlen, jcc_aliases, n_aliases); +} +static xed_bool_t find_cmovcc_alias(const char* orig, char* result, int maxlen) { + const size_t n_aliases = sizeof(cmovcc_aliases) / sizeof(cmovcc_aliases[0]); + return find_alias(orig, result, maxlen, cmovcc_aliases, n_aliases); +} +static xed_bool_t find_setcc_alias(const char* orig, char* result, int maxlen) { + const size_t n_aliases = sizeof(setcc_aliases) / sizeof(setcc_aliases[0]); + return find_alias(orig, result, maxlen, setcc_aliases, n_aliases); +} + + +/* Try all known suffixes and prefixes with the original mnemonic if + certain operands or prefixes were seen. + Put (un)modified iclass string into result */ +static void revise_mnemonic(xed_enc_line_parsed_t *v, char* result, int maxlen) { + const char *orig = v->iclass_str; + assert(xed_strlen(orig) > 0); + + /* Try _NEAR and _FAR variants for "call" and "ret" */ + if (!v->seen_far_ptr && probe_iclass_string(orig, "NEAR", result, maxlen)) { + return; + } + else if (v->seen_far_ptr && probe_iclass_string(orig, "FAR", result, maxlen)) { + return; + } + /* all aliases for conditional jumps start with 'J' */ + if (orig[0] == 'J' && find_jcc_alias(orig,result, maxlen)) { + return; + } + if (strncmp(orig,"CMOV",4)==0 && find_cmovcc_alias(orig,result, maxlen)) { + return; + } + if (strncmp(orig,"SET",3)==0 && find_setcc_alias(orig,result, maxlen)) { + return; + } + + if (v->seen_cr && probe_iclass_string(orig, "CR", result, maxlen)) // mov_cr + return; + if (v->seen_dr && probe_iclass_string(orig, "DR", result, maxlen)) // mov_dr + return; + + /* iclasses contain all three forms: REP_, REPE_ and REPNE_ */ + if (v->seen_repne && probe_iclass_string("REPNE", orig, result, maxlen)) { + return; + } + else if (v->seen_repe && probe_iclass_string("REPE", orig, result, maxlen)) { + return; + } + else if (v->seen_repe && probe_iclass_string("REP", orig, result, maxlen)) { + return; + } + + if (v->seen_lock && probe_iclass_string(orig, "LOCK", result, maxlen)) { + return; + } + + /* string vs SSE instructions with similar mnemonics */ + if ((v->deduced_vector_length > 0) + && probe_iclass_string(orig, "XMM", result, maxlen)) + return; + + /* TODO handle remaining cases: + FXRSTOR vs FXRSTOR64 and other *SAVE/ *RSTR(64) + PEXTRW PEXTRW_SSE4 + VPEXTRW VPEXTRW_c5 + Long NOPs: XED_ICLASS_NOP2 - NOP9 */ + + /* Reaching the end of the function means no modifications */ + xed_strncpy(result, orig, maxlen); +} + +static xed_uint_t encode_with_xed(xed_enc_line_parsed_t* v) +{ + xed_encoder_instruction_t inst; + xed_state_t dstate; + xed_uint_t eosz=0; + xed_uint_t noperand=0; + xed_encoder_operand_t operand_array[XED_ENCODER_OPERANDS_MAX]; + opnd_list_t* q=0; + xed_uint_t has_imm0 = 0; + + if (v->iclass_str == 0) { + asp_error_printf("Did not find an instruction\n"); + exit(1); + } + + process_prefixes(v, &inst); + + /* Instruction's mnemonic is not always unambiguous; + iclass is sometimes affected by arguments and prefixes. + Use operand knowledge to adjust the mnemonic if needed */ + char revised_mnemonic[100] = { 0 }; + revise_mnemonic(v, revised_mnemonic, sizeof(revised_mnemonic)); + v->iclass_e = str2xed_iclass_enum_t(revised_mnemonic); + + // handle operands + q = v->opnds; + while(q) { + process_operand(v, q, &noperand, operand_array, &has_imm0, &eosz); + check_too_many_operands(noperand); + q = q->next; + } + + if (v->iclass_e == XED_ICLASS_INVALID) { + asp_error_printf("Bad instruction name: '%s'\n", revised_mnemonic); + exit(1); + } + + asp_dbg_printf("ICLASS [%s]\n", xed_iclass_enum_t2str(v->iclass_e)); + + // handle other operand decorators (zeroing, kmasks, broadcast masks) + q = v->opnds; + while(q) { + slist_t* r = q->decorators; + while(r) { + process_other_decorator(r->s, &noperand, operand_array); + check_too_many_operands(noperand); + r = r->next; + } + q = q->next; + } + if (eosz == 0) { + eosz = 32; + asp_dbg_printf("#Guessing 32b EOSZ\n"); + } + + if (eosz == 64) { + if (v->mode != 64) { + asp_dbg_printf("#Changing to 64b mode\n"); + } + v->mode = 64; + } + asp_dbg_printf("#MODE=%d, EOSZ=%d\n", v->mode, eosz); + set_state(&dstate, v); + xed_inst(&inst, dstate, v->iclass_e, eosz, noperand, operand_array); + return encode(&inst); +} + +/* Return true if the instruction accepts relative branch as an operand */ +static xed_bool_t test_has_relbr(const xed_inst_t* p) { + const unsigned noperands = xed_inst_noperands(p); + for (unsigned i = 0; i < noperands; i++) { + const xed_operand_t* o = xed_inst_operand(p, i); + if (xed_operand_name(o) == XED_OPERAND_RELBR) { + return 1; + } + } + return 0; +} + +/* relbr_table is an array initialized at startup that tells us if we have + * a relative branch displacement */ +static xed_bool_t relbr_table[XED_ICLASS_LAST]; + +static xed_bool_t has_relbr(xed_iclass_enum_t iclass) { + assert(iclass < XED_ICLASS_LAST); + return relbr_table[iclass]; +} +static void setup(void) { + memset(relbr_table, 0, sizeof(xed_bool_t)*XED_ICLASS_LAST); + + for (unsigned i = 0; i < XED_MAX_INST_TABLE_NODES; i++) { + const xed_inst_t *inst = xed_inst_table_base() + i; + xed_iclass_enum_t ic = xed_inst_iclass(inst); + assert(ic < XED_ICLASS_LAST); + relbr_table[ic] = test_has_relbr(inst); + } +} + +int main(int argc, char** argv) +{ + int verbose = 1; + xed_str_list_t* string_list = 0; + xed_str_list_t* p = 0; + xed_uint_t mode=0; + xed_uint_t length = 0; + + setup(); + xed_tables_init(); + + p = string_list = process_args(argc, argv, &mode, &verbose); + asp_set_verbosity(verbose); + + while(p) { + xed_uint_t olen = 0; + xed_enc_line_parsed_t* v = 0; + + v = asp_get_xed_enc_node(); + v->mode = mode; + + // we duplicate because the asp_delete_xed_enc_line_parsed_line_t + // will delete the string if still present when we call it. + v->input = duplicate(p->s); + + if (verbose > 0) + printf("#Assembling [%s]\n",v->input); + + asp_parse_line(v); + + if (verbose > 1) + asp_print_parsed_line(v); + + olen = encode_with_xed(v); + length += olen; + + asp_delete_xed_enc_line_parsed_t(v); + v = 0; + p = p->next; + } + + if (verbose > 0) + printf("#nbytes = %d\n",length); + + delete_string_list(string_list); + string_list = 0; + + return 0; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse.c b/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse.c new file mode 100644 index 0000000..ec51ec6 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse.c @@ -0,0 +1,1110 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// more natural assembly language parser + +#include +#include +#include // strcmp, strncmp +#include // malloc, free +#include // vprintf, fprintf +#include // isspace, isdigit, isalnum +#include + +#include "xed-examples-util.h" // xed_upcase_buf +#include "xed-asmparse.h" + +static int asp_dbg_verbosity = 1; + +/* PROTOTYPES */ +static char* asp_strdup(const char* s); +static void upcase(char* s); +static void delete_slist_t(slist_t* s); +static slist_t* get_slist_node(void); +static void clean_out_memparse_rec_t(memparse_rec_t* p); +static void delete_opnd_list_t(opnd_list_t* s); +static opnd_list_t* get_opnd_list_node(void); +static void add_decorator(opnd_list_t* onode, char* d); +static void grab_prefixes(char**p, xed_enc_line_parsed_t* v); +static void study_prefixes(xed_enc_line_parsed_t* v); +static void grab_inst(char**p, xed_enc_line_parsed_t* v); +static void grab_operand(char**p, xed_enc_line_parsed_t* v); +//static slist_t* reverse_list(slist_t* head); +static int isreg(char* s); +static int isdecorator(char* s); +static int64_t letter_cvt(char a, char base); +static int asm_isnumber(char* s, int64_t* onum, int arg_negative); +static int ismemref(char* s); +static int valid_decorator(char const* s); +static int grab_decorator(char* s, unsigned int pos, char** optr); +static void parse_reg(xed_enc_line_parsed_t* v, char* s, opnd_list_t* onode); +static void parse_decorator(char* s, opnd_list_t* onode); +static void parse_memref(char* s, opnd_list_t* onode); +static void refine_operand(xed_enc_line_parsed_t* v, char* s); +static void refine_operands(xed_enc_line_parsed_t* v); +static unsigned int skip_spaces(char *s, unsigned int offset); + +///////////////////////// + + +static char* asp_strdup(char const* s) { + return xed_strdup(s); +} + +/* Verbosity levels: + 0 - only errors and end result + 1 - informational messages about implicit decision made by encoder, + such as correction of operand sizes, bitness etc + 2 - debugging info */ +void asp_set_verbosity(int v) { + asp_dbg_verbosity = v; +} + +void asp_printf(const char* format, ...) { + if (asp_dbg_verbosity < 1) + return; + va_list args; + va_start(args, format); + vprintf(format, args); + va_end(args); +} + +void asp_dbg_printf(const char* format, ...) { + if (asp_dbg_verbosity < 2) + return; + va_list args; + va_start(args, format); + vprintf(format, args); + va_end(args); +} + +/* Errors are always printed to stderr */ +void asp_error_printf(const char* format, ...) { + va_list args; + va_start(args, format); + fprintf(stderr, "ERROR: "); + vfprintf(stderr, format, args); + va_end(args); +} + +static void upcase(char* s) { + (void)xed_upcase_buf(s); +} + + +static void delete_slist_t(slist_t* s) { + slist_t* p = s; + + while(p) { + slist_t* t = p; + p=p->next; + free(t->s); // FIXME: might free static stuff! + free(t); + } +} + +static slist_t* get_slist_node() { + slist_t* node = (slist_t*)malloc(sizeof(slist_t)); + assert(node != 0); + node->s = 0; + node->next = 0; + return node; +} + + + +static void clean_out_memparse_rec_t(memparse_rec_t* p) { + if (p->seg) + free(p->seg); + if (p->base) + free(p->base); + if (p->index) + free(p->index); + if (p->disp) + free(p->disp); + if (p->scale) + free(p->scale); + p->mem_size = 0; // not allocated! + p->mem_bits = 0; + p->ndisp = 0; +} + + +static void delete_opnd_list_t(opnd_list_t* s) { + opnd_list_t* p = s; + while(p) { + opnd_list_t* t = p; + free(p->s); + clean_out_memparse_rec_t(&p->mem); + delete_slist_t(p->decorators); + p = p->next; + free(t); + } +} + + +xed_enc_line_parsed_t* asp_get_xed_enc_node(void) { + xed_enc_line_parsed_t* v = (xed_enc_line_parsed_t*) + malloc(sizeof(xed_enc_line_parsed_t)); + assert(v != 0); + memset(v, 0, sizeof(xed_enc_line_parsed_t)); + return v; +} + +void asp_delete_xed_enc_line_parsed_t(xed_enc_line_parsed_t* v) { + if (v->iclass_str) + free(v->iclass_str); + if (v->input) + free(v->input); + + delete_slist_t(v->operands); + delete_slist_t(v->prefixes); + delete_opnd_list_t(v->opnds); + free(v); +} + +static opnd_list_t* get_opnd_list_node() { + opnd_list_t* p = (opnd_list_t*)malloc(sizeof(opnd_list_t)); + assert(p != 0); + memset(p, 0, sizeof(opnd_list_t)); + p->type = OPND_INVALID; + return p; +} + +static void add_decorator(opnd_list_t* onode, char* d) { + slist_t* dnode = get_slist_node(); + dnode->s = d; + dnode->next = onode->decorators; + onode->decorators = dnode; +} + +static char const* decorators[] = { + "{K0}", + "{K1}", + "{K2}", + "{K3}", + "{K4}", + "{K5}", + "{K6}", + "{K7}", + "{Z}", + "{RNE-SAE}", + "{RD-SAE}", + "{RU-SAE}", + "{RZ-SAE}", + "{SAE}", + "{1TO2}", + "{1TO4}", + "{1TO8}", + "{1TO16}", + "{1TO32}", + "{1TO64}", + 0 }; + +static char const* mem_size_qualifiers[] = { + "BYTE", + "WORD", + "DWORD", + "QWORD", + "XMMWORD", + "YMMWORD", + "ZMMWORD", + 0 +}; + +static char const* scales[] = { + "1", + "2", + "4", + "8", + 0 +}; + +static void study_prefixes(xed_enc_line_parsed_t* v) { + slist_t* p = v->prefixes; + while(p) { + if (strcmp("REPNE",p->s) == 0) + v->seen_repne = 1; + else if (strcmp("REPE",p->s) == 0) + v->seen_repe = 1; + else if (strcmp("REP",p->s) == 0) + v->seen_repe = 1; + else if (strcmp("LOCK",p->s) == 0) + v->seen_lock = 1; + p = p->next; + } +} + +static void grab_prefixes(char**p, xed_enc_line_parsed_t* v) +{ + // grab any matching strings up to next space + char const* prefixes[] = { "DATA16", "DATA32", + "ADDR16", "ADDR32", + "REX", "REWXW", + "XACQUIRE", "XRELEASE", + "LOCK", + "REP", "REPE", "REPNE", + 0 }; + char* h = asp_strdup(*p); + char* q = h; + char* r = h; + + unsigned int found=1; + + do { + unsigned int i=0; + + r = q; + while(*q) { + if (isspace(*q)) { + *q = 0; // jam a null + q++; + break; + } + q++; + } + found = 0; + for (i=0; prefixes[i]; i++) { + if (strcmp(r, prefixes[i]) == 0) { + slist_t* node = 0; + // matched a prefix + found = 1; + //grab the string, pointed to by r + asp_dbg_printf("PREFIX [%s]\n",r); + node = get_slist_node(); + node->s = asp_strdup(r); + if (v->prefixes) + node->next = v->prefixes; + v->prefixes = node; + + // advance q to next nonspace + while(*q && isspace(*q)) + q++; + break; + } + } + } + while(found); + + // r-h is the distance in the copy of the string we've advanced through so far. + *p = *p + (r-h); + free(h); +} + +static void grab_inst(char**p, xed_enc_line_parsed_t* v) +{ + + // grab next non-whitespace string + char* q = *p; + while(*q) { + if (isspace(*q)) { + *q = 0; // jam a null + q++; + break; + } + q++; + } + v->iclass_str = asp_strdup(*p); + /* Note that it is not the final iclass as it may require mangling */ + asp_dbg_printf("MNEMONIC [%s]\n",v->iclass_str); + *p = q; +} + +static void grab_operand(char**p, xed_enc_line_parsed_t* v) +{ + // grab next operand string (reg, memop) with decorations + slist_t* node = 0; + + char* q = *p; + char* r = 0; + while(*q && isspace(*q)) + q++; + // grab until next comma or end-of-string + r = q; + while(*q && *q != ',') + q++; + if (*q) { + *q = 0; // jam null or overwrite null + q++; + } + // remove trailing white space + if (q>r) { + char *z = q-1; // start at null + while (z > r) { + if (*z == 0) { + z--; + continue; + } + if (isspace(*z)) { + *z = 0; + z--; + continue; + } + break; + } + } + asp_dbg_printf("OPERAND: [%s]\n", r); + node = get_slist_node(); + node->s = asp_strdup(r); + if (v->operands) + node->next = v->operands; + v->operands = node; + *p = q; +} + + +#if 0 +/* + + a->b->c->d->0 + p q + + 0<-a b->c->d->0 + p q + + 0<-a<-b c->d->0 + p q t + + 0<-a<-b<-c d->0 + p q t + + 0<-a<-b<-c<-d 0 + p q t + + 0<-a<-b<-c<-d 0 + p q + + */ + +static slist_t* reverse_list(slist_t* head) { + slist_t* p = head; // prev + slist_t* q = 0; // current + slist_t* t = 0; // dangling head of rest of list + + if (p && p->next) { + q = p->next; + p->next = 0; // new end of list + } + else + return p; + + while(q) { + t = q->next; + q->next = p; + p = q; + q = t; + } + return p; +} +#endif + +static int isreg(char* s) { // including decorators + if (s) { + if (isalpha(s[0])) { + int i; + for(i=1;s[i];i++) + // allow alnum, dash & parens (x87), curlies, else bail + if ( !isalnum(s[i]) && + s[i] != '{' && + s[i] != '(' && + s[i] != ')' && + s[i] != '-' && + s[i] != '}' ) + return 0; + return 1; + } + } + return 0; +} +static int isdecorator(char* s) { + if (s) { + if (s[0] == '{') { + int i; + for(i=1;s[i];i++) + // allow alnum, dash & right-curly, else bail + if ( !isalnum(s[i]) && + s[i] != '-' && + s[i] != '}' ) + return 0; + return 1; + } + } + return 0; +} + +/* Return true if s matches pattern "num:num" */ +static int islongptr(char *s) { + if (!s) + return 0; + /* skip optional "far" */ + if (s[0] == 'F' && s[1] == 'A' && s[2] == 'R') { + s += 3; + s += skip_spaces(s, 0); + } + + int column_pos = -1; + for (int i = 0; s[i]; i++) { + if (s[i] == ':') { + column_pos = i; + break; + } + } + if (column_pos < 0) + return 0; + char *first = s; + char *second = s + column_pos + 1; + s[column_pos] = '\0'; // temporarily split the string + int64_t unused = 0; + int res = asm_isnumber(first, &unused, 0) + && asm_isnumber(second, &unused, 0); // both parts are numbers + s[column_pos] = ':'; // restore the separator + return res; +} + +static int64_t letter_cvt(char a, char base) { + return (int64_t)(a-base); +} + + +static int asm_isnumber(char* s, int64_t* onum, int arg_negative) { + // return 1/0 if the string s is a number, and store the number in + // onum. Handles base10, binary (0b prefix), octal (0 prefix) and hex + // (0x prefix) number strings. + + // The arg_negative will normally be zero, but I encountered a case + // when parsing displacements where the minus sign was already eaten by + // the parser and I didn't want to reallocate the string just to + // reassociate the minus sign with the number. So for that case, I + // added a arg_negative to allow me to force the number to be negative + // without there being an actual leading minus sign present. + + + int binary = 0; + int hex = 0; + int octal = 0; + int negative = 0; + unsigned int i = 0; + unsigned int j = 0; + unsigned int len = xed_strlen(s); + int64_t val = 0; + + if (arg_negative) { + negative = 1; + } + if (s[0]=='-') { + negative = 1; + i++; + } + if (s[0] == '+') { + i++; + } + + if (i < len && isdigit(s[i])) { //first digit + if (s[i]=='0' && i+1 < len) { + if (s[i+1] == 'B') { + binary = 1; + i+=2; + } + else if (s[i+1] == 'X') { + hex = 1; + i+=2; + } + else { + octal = 1; + i++; + } + } + + if (binary) { + for(j=i;j 'F') ) + return 0; // bad hex number + else if (isdigit(s[j])) + val = val << 4 | letter_cvt(s[j],'0'); + else + val = val << 4 | (letter_cvt(s[j],'A')+10 ); + } + } + else if (octal) { + for(j=i;j '7') + return 0; // bad octal number + else + val = val << 3 | letter_cvt(s[j],'0'); + } + } + else { //decimal + for(j=i;j> 63ULL) == 1) { + asp_error_printf("Bad immediate operand - too big to be negative: %s\n",s); + exit(1); + } + else { + val = - val; // FIXME: 2018-11-30 wcvt. error negeating unsigned value... + asp_dbg_printf("IMM value 0x%016llx\n",val); + } + } + *onum = val; + return 1; + } + return 0; +} + +static unsigned int skip_spaces(char *s, unsigned int offset) { + while (s[offset] && isspace(s[offset])) { + offset++; + } + return offset; +} + +static int ismemref(char* s) { // FIXME include directorators + if (s) { + unsigned int i=0,offset=0; + for(i=0;mem_size_qualifiers[i];i++) { + unsigned int len; + len = xed_strlen(mem_size_qualifiers[i]); + if (strncmp(mem_size_qualifiers[i],s,len) == 0) { + offset = len; + break; + } + } + offset = skip_spaces(s, offset); + /* skip optional "ptr" part of memref */ + if (!strncmp(s + offset, "PTR", 3)) { + offset += 3; + offset = skip_spaces(s, offset); + } + + if (s[offset] == '[') { + // search backwards from end as there might be some {...} decorators. + unsigned int len = xed_strlen(s); + for(i=len-1;i>offset && i>0;i--) { + if (s[i] == ']') + return 1; + } + } + } + return 0; +} + + +#define BLEN 100 + +static int valid_decorator(char const* s) { + int i=0; + while(decorators[i]) { + if (strcmp(decorators[i],s) == 0) + return 1; + i++; + } + return 0; +} +static int grab_decorator(char* s, unsigned int pos, char** optr) +{ + char tbuf[BLEN]; + int tpos=0; + char* p = s+pos; + int start = 0; + while(*p) { + if (start == 0 && *p == '{') { + start = 1; + tbuf[tpos++] = *p; + } + else if (start) { + tbuf[tpos++] = *p; + if (*p == '}') { + tbuf[tpos]=0; + if (valid_decorator(tbuf)) { + *optr = asp_strdup(tbuf); + return (int)(pos+1); + } + else { + asp_error_printf("Bad decorator: %s\n", tbuf); + exit(1); + } + } + } + else { + break; + } + p++; + pos++; + } + *optr = 0; + if (start) { // we started something but didn't finish it. + asp_error_printf("Bad decorator: %s\n", tbuf); + exit(1); + return -1; //notreached + } + return 0; +} + +static void parse_reg(xed_enc_line_parsed_t* v, char* s, opnd_list_t* onode) +{ + char tbuf[BLEN]; + unsigned int i=0; + unsigned int len=0; + + len = xed_strlen(s); + + while(is = asp_strdup(tbuf); + onode->type = OPND_REG; + onode->reg = str2xed_reg_enum_t(onode->s); + + if (onode->reg >= XED_REG_CR0 && onode->reg <= XED_REG_CR15) { + v->seen_cr = 1; + } + if (onode->reg >= XED_REG_DR0 && onode->reg <= XED_REG_DR7) { + v->seen_dr = 1; + } + + + while (is = 0; + onode->type = OPND_DECORATOR; + while (is==0) { + asp_dbg_printf("DECORATOR: %s\n",d); + onode->s = d; + //add_decorator(onode,d); + } + else { + asp_error_printf("Too many lone decorators %s\n",s); + exit(1); + } + } + if (d==0) + break; + } + if (onode->s == 0) { + asp_dbg_printf("No decorators: %s\n",s); + exit(1); + } +} + +static void parse_memref(char* s, opnd_list_t* onode) +{ + // [ seg:reg + index * [1,2,4,8] +/- disp ] + memparse_rec_t r = { 0 }; + r.len = xed_strlen(s); + assert(r.len < BLEN); + + char tbuf[BLEN]; + char stmp[BLEN]; + char *q; + unsigned int i=0; + int p=0; + int plusses=0; + int last_star=0; + unsigned int offset=0; + + for(i=0;mem_size_qualifiers[i];i++) { + unsigned int len; + len = xed_strlen(mem_size_qualifiers[i]); + if (strncmp(mem_size_qualifiers[i],s,len) == 0) { + asp_dbg_printf("MEM SIZE QUALIFIER: %s\n",mem_size_qualifiers[i]); + r.mem_size = mem_size_qualifiers[i]; // static string, not allocated + r.mem_bits = 1U << (i+3); + offset = len; + break; + } + } + /* skip optional "ptr" part */ + offset = skip_spaces(s, offset); + if (!strncmp(s+offset, "PTR", 3)) { + offset += 3; + } + + // remove spaces -- makes figuring out terminators much easier! + for(i=0;s[offset+i];i++) { + unsigned int src_pos = offset + i; + if (!isspace(s[src_pos])) + stmp[p++] = s[src_pos]; + } + stmp[p]=0; + p=0; + r.len=xed_strlen(stmp); + + + for(i=0;itype = OPND_MEM; + onode->mem = r; +} + +/* Extract semantic values from string: "far number:number" */ +static void parse_long_pointer(char* s, opnd_list_t* onode) +{ + /* skip optional "far" part */ + if (s[0] == 'F' && s[1] == 'A' && s[2] == 'R') { + s += 3; + s += skip_spaces(s, 0); + } + + int column_pos = -1; + for (int i = 0; s[i]; i++) { + if (s[i] == ':') { + column_pos = i; + break; + } + } + assert(column_pos >= 0); + char *first = s; + char *second = s + column_pos + 1; + s[column_pos] = '\0'; // split the string + int64_t first_num, second_num; + asm_isnumber(first, &first_num, 0); + asm_isnumber(second, &second_num, 0); + + onode->farptr.seg = s; + onode->farptr.offset = s + column_pos + 1; + onode->farptr.seg_value = first_num; + onode->farptr.offset_value = second_num; + onode->type = OPND_FARPTR; +} + +static void refine_operand(xed_enc_line_parsed_t* v, char* s) +{ + opnd_list_t* onode = get_opnd_list_node(); + int64_t num = 0; + + asp_dbg_printf("REFINE OPERAND [%s]\n", s); + if (isreg(s)) { + asp_dbg_printf("REGISTER-ish: %s\n",s); + parse_reg(v,s,onode); + } + else if (asm_isnumber(s,&num,0)) { + /* Actual meaning depends on opcode */ + asp_dbg_printf("Immediate or displacement: %s\n",s); + onode->type = OPND_IMM; + onode->s = asp_strdup(s); + onode->imm = num; + } + else if (ismemref(s)) { + // [ seg:reg + index * [1,2,4,8] + disp ] + asp_dbg_printf("MEMREF-ish\n"); + parse_memref(s,onode); + } + else if (isdecorator(s)) { + asp_dbg_printf("LONE DECORATOR\n"); + parse_decorator(s,onode); + } + else if (islongptr(s)) { + asp_dbg_printf("LONG POINTER\n"); + v->seen_far_ptr = 1; + parse_long_pointer(s,onode); + } + else { + asp_error_printf("Bad operand: %s\n",s); + exit(1); + } + // add onode to list + onode->next = v->opnds; + v->opnds = onode; +} + +static void refine_operands(xed_enc_line_parsed_t* v) +{ + slist_t* p = 0; + if (v->operands) { + //v->operands = reverse_list(v->operands); + p = v->operands; + while(p) { + refine_operand(v,p->s); + p = p->next; + } + } +} + + +void asp_parse_line(xed_enc_line_parsed_t* v) +{ + char* p = asp_strdup(v->input); + char* q = p; // for deletion + int inst = 0; + int prefixes = 0; + upcase(p); + while(*p) { + if (isspace(*p)) { + p++; continue; + } + if (prefixes==0) { + grab_prefixes(&p,v); + study_prefixes(v); + prefixes = 1; + continue; + } + if (inst==0) { + grab_inst(&p,v); + inst = 1; + continue; + } + if (inst==1) { // grab operands + grab_operand(&p, v); + continue; + } + + p++; + } + + refine_operands(v); + free(q); +} + + +void asp_print_parsed_line(xed_enc_line_parsed_t* v) { + slist_t* p=0; + opnd_list_t* q=0; + asp_printf("MODE: %d\n",v->mode); + asp_printf("MNEMONIC: %s\n",v->iclass_str); + asp_printf("PREFIXES: "); + p = v->prefixes; + while(p) { + asp_printf("%s ", p->s); + p = p->next; + } + asp_printf("\n"); + + asp_printf("OPERANDS: "); + p = v->operands; + while(p) { + asp_printf("<%s> ", p->s); + p = p->next; + } + asp_printf("\n"); + + + asp_printf("OPERANDS DECODED:\n"); + q = v->opnds; + while(q) { + slist_t* d = 0; + asp_printf("\t"); + if (q->s) asp_printf("%s ", q->s); + + switch (q->type) { + case OPND_REG: asp_printf("REG "); break; + case OPND_IMM: asp_printf("IMM 0x%016llx ", q->imm); break; + case OPND_DECORATOR: asp_printf("DECORATOR "); break; + case OPND_INVALID: asp_printf("INVALID "); break; + case OPND_MEM: + asp_printf("MEM "); break; + asp_printf("%d %s [%s:%s + %s*%s %s %s] ", + q->mem.len, + (q->mem.mem_size ? q->mem.mem_size : "n/a"), + (q->mem.seg ? q->mem.seg : "n/a"), + (q->mem.base ? q->mem.base : "n/a"), + (q->mem.index ? q->mem.index : "n/a"), + q->mem.scale, + (q->mem.minus ? "-" : "+"), + (q->mem.disp ? q->mem.disp : "n/a")); + break; + case OPND_FARPTR: + asp_printf("FAR PTR %s:%s", q->farptr.seg, q->farptr.offset); + break; + default: + assert(0 && "Unhandled operand type"); + break; + } + d = q->decorators; + while(d) { + asp_printf("%s ",d->s); + d = d->next; + } + + q = q->next; + asp_printf("\n"); + } + + +} + diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse.h b/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse.h new file mode 100644 index 0000000..aee96c1 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-asmparse.h @@ -0,0 +1,101 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include +#include + +#include "xed/xed-interface.h" + +typedef struct slist_s { + char* s; + struct slist_s* next; +} slist_t; + +typedef enum { + OPND_INVALID, + OPND_REG, + OPND_IMM, /* Literal that corresponds to immediate or displacement */ + OPND_MEM, + OPND_DECORATOR, + OPND_FARPTR +} opnd_type_t; + +typedef struct { + unsigned int len; + char* seg; + char* base; + char* index; + char* disp; + int64_t ndisp; // disp converted to a number + char* scale; + unsigned int nscale; // 0(invalid), 1,2,4,8 + int minus; + char const* mem_size; // NOT allocated; do not free. Pointer to static string + uint32_t mem_bits; // mem_size converted to bits +} memparse_rec_t; + +typedef struct { + char* seg; + char* offset; + int64_t seg_value; + int64_t offset_value; +} farptr_rec_t; + +typedef struct opnd_list_s { + char* s; + opnd_type_t type; + memparse_rec_t mem; + farptr_rec_t farptr; + slist_t* decorators; + int64_t imm; + xed_reg_enum_t reg; + struct opnd_list_s* next; +} opnd_list_t; + + +typedef struct { + char* input; + int valid; + int mode; // 16/32/64 + char* iclass_str; + xed_iclass_enum_t iclass_e; + slist_t* prefixes; // reversed + slist_t* operands; // reversed + opnd_list_t* opnds; + + /* parsing state used to resolve ambiguous cases */ + xed_bool_t seen_repe; + xed_bool_t seen_repne; + xed_bool_t seen_lock; + xed_bool_t seen_cr; + xed_bool_t seen_dr; + xed_bool_t seen_far_ptr; + int deduced_vector_length; +} xed_enc_line_parsed_t; + +void asp_set_verbosity(int v); +void asp_error_printf(const char* format, ...); +void asp_printf(const char* format, ...); +void asp_dbg_printf(const char* format, ...); + +xed_enc_line_parsed_t* asp_get_xed_enc_node(void); +void asp_delete_xed_enc_line_parsed_t(xed_enc_line_parsed_t* v); +void asp_parse_line(xed_enc_line_parsed_t* v); +void asp_print_parsed_line(xed_enc_line_parsed_t* v); + + diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-dec-print.c b/CodeVirtualizer/build/obj/wkit/examples/xed-dec-print.c new file mode 100644 index 0000000..ab85829 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-dec-print.c @@ -0,0 +1,62 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-dec-print.c +// decode and print + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + + // example instructions + xed_uint_t bytes = 2; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES] = { 0x00, 0x00 }; + + xed_tables_init(); + + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + xed_error = xed_decode(&xedd, itext,bytes); + if (xed_error == XED_ERROR_NONE) + { + ok = xed_format_context(XED_SYNTAX_ATT, &xedd, buffer, BUFLEN, 0, 0, 0); + if (ok) { + printf("%s\n", buffer); + return 0; + } + printf("Error disassembling\n"); + return 1; + } + printf("Decoding error\n"); + return 1; + (void) argv; (void)argc; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-elf.c b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-elf.c new file mode 100644 index 0000000..c6e7d12 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-elf.c @@ -0,0 +1,773 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed-disas-elf.h" // early, to get defines + +#if defined(XED_DECODER) && defined(XED_ELF_READER) + +//////////////////////////////////////////////////////////////////////////// + + +#include "xed-disas-elf.h" +#if defined(XED_PRECOMPILED_ELF_DWARF) +# include +#else // system version +# include +# if defined(XED_DWARF) +# include +# endif +#endif +#if defined(XED_DWARF) +# include +# include +#endif + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" +#include "xed-symbol-table.h" +#include "avltree.h" + +#include +#include +#include + +//////////////////////////////////////////////////////////////////////////// + + +// DWARF HANDLING + +#if defined(XED_DWARF) +static void dwarf_handler(Dwarf_Error err, Dwarf_Ptr errarg) +{ + (void)err; + (void)errarg; +} + +/* file 0 does not exist */ +typedef struct { + xed_uint32_t line; + xed_uint32_t file; +} line_number_entry_t; + +void line_number_entry_init(line_number_entry_t*p, + xed_uint32_t a_line, + xed_uint32_t a_file) +{ + p->line=a_line; + p->file=a_file; +} + +/* addresses -> line_number_entry_t values */ +static avl_tree_t line_number_table; //xed_uint64_t -> line_number_entry_t* + +/* start at 1, 0 means no file */ +static xed_uint32_t global_file_num = 1; + +/* global file num -> string */ +static avl_tree_t global_file_name_table; // xed_uint64_t -> char* + +/* local file num -> global file num. This one is restarted for each + * compilation unit. */ +static avl_tree_t file_name_table; // xed_uint64_t -> xed_uint64_t + +static char const* unknown = "Unknown"; + +static int find_line_number(xed_uint64_t addr, + char** file, + xed_uint32_t* line) +{ + line_number_entry_t* p = + (line_number_entry_t*) avl_find(&line_number_table, + addr); + if (!p) + return 0; + + char *q = (char*) avl_find(&global_file_name_table,p->file); + if (q) + *file = q; + else + *file = (char*)unknown; + *line = p->line; + return 1; +} + +//external interface, called indirectly +void find_line_number_info(xed_uint64_t addr) +{ + char* file_name; + xed_uint32_t line_number; + if (find_line_number(addr, + &file_name, + &line_number)) + { + printf(" # %s:%d", file_name, line_number); + } +} + + +static void read_dwarf_line_numbers(void* region, + unsigned int region_bytes) +{ + int dres; + Dwarf_Debug dbg; + Dwarf_Unsigned next_cu_offset;; + + elf_version(EV_CURRENT); + + Elf* elf = elf_memory(XED_STATIC_CAST(char*,region), region_bytes); + dres = dwarf_elf_init(elf, DW_DLC_READ, dwarf_handler, 0, &dbg, 0); + if (dres != DW_DLV_OK) + return; + + avl_tree_init(&line_number_table); + avl_tree_init(&global_file_name_table); + avl_tree_init(&file_name_table); + + while (1) + { + int i; + Dwarf_Die cu_die; + Dwarf_Half tag; + Dwarf_Line* line_buf; + Dwarf_Signed line_count; + + dres = dwarf_next_cu_header(dbg, 0, 0, 0, 0, &next_cu_offset, 0); + if (dres != DW_DLV_OK) + break; + // Doc says first die is compilation unit + if (dwarf_siblingof(dbg, 0, &cu_die, 0) != DW_DLV_OK) + continue; + if ( (dwarf_tag(cu_die, &tag, 0) != DW_DLV_OK) || + (tag != DW_TAG_compile_unit)) + { + dwarf_dealloc(dbg, cu_die, DW_DLA_DIE); + continue; + } + dres = dwarf_srclines(cu_die, &line_buf, &line_count, 0); + if (dres != DW_DLV_OK) + { + dwarf_dealloc(dbg, cu_die, DW_DLA_DIE); + continue; + } + for (i = 0; i < line_count; i++) + { + Dwarf_Addr line_addr; + Dwarf_Unsigned line_num, file_num; + Dwarf_Signed line_off; + Dwarf_Bool line_end; + char* file_name; + + dwarf_lineaddr(line_buf[i], &line_addr, 0); + dwarf_lineno(line_buf[i], &line_num, 0); + dwarf_line_srcfileno(line_buf[i], &file_num, 0); + dwarf_lineoff(line_buf[i], &line_off, 0); + dwarf_lineendsequence(line_buf[i], &line_end, 0); + + if (file_num) + { + dres = dwarf_linesrc(line_buf[i], &file_name, 0); + if (dres == DW_DLV_OK) { + + if ( avl_find(&file_name_table, file_num) == 0) + { + avl_insert(&file_name_table, + file_num, + (void*)(xed_addr_t)global_file_num,0); + + avl_insert(&global_file_name_table, + global_file_num, + xed_strdup(file_name),1); + global_file_num++; + } + dwarf_dealloc(dbg, file_name, DW_DLA_STRING); + } + } + xed_uint32_t gfn = (xed_uint32_t) (xed_addr_t) avl_find( + &file_name_table, file_num); + line_number_entry_t* p = + (line_number_entry_t*)malloc(sizeof(line_number_entry_t)); + line_number_entry_init(p, line_num, gfn); + avl_insert(&line_number_table, line_addr, p, 1); + + } /* for */ + avl_tree_clear(&file_name_table,0); + dwarf_srclines_dealloc(dbg, line_buf, line_count); + dwarf_dealloc(dbg, cu_die, DW_DLA_DIE); + } /* while */ + dwarf_finish(dbg, 0); + elf_end(elf); +} + +#endif +//////////////////////////////////////////////////////////////////////////// + + +char* +lookup32(Elf32_Word stoffset, + void* start, + unsigned int len, + Elf32_Off offset) +{ + char* p = (char*)start + offset; + char* q = p + stoffset; + if ((unsigned char*)q >= (unsigned char*)start+len) + return 0; + if ((unsigned char*)q < (unsigned char*)start) + return 0; + return q; +} + +char* +lookup64(Elf64_Word stoffset, + void* start, + unsigned int len, + Elf64_Off offset) +{ + char* p = (char*)start + offset; + char* q = p + stoffset; + if ((unsigned char*)q >= (unsigned char*)start+len) + return 0; + if ((unsigned char*)q < (unsigned char*)start) + return 0; + return q; +} + +void xed_disas_elf_init(void) { + xed_register_disassembly_callback(xed_disassembly_callback_function); +} + + + +void +disas_test32(xed_disas_info_t* fi, + void* start, + unsigned int length, + Elf32_Off offset, + Elf32_Word size, + Elf32_Addr runtime_vaddr, + xed_symbol_table_t* symbol_table) +{ + unsigned char* hard_limit = (unsigned char*)start + length; + + fi->s = (unsigned char*)start; + fi->a = (unsigned char*)start + offset; + if (fi->a > hard_limit) + fi->a = hard_limit; + if ((void*)(fi->a) < start) { + fprintf(stderr,"# malformed region limit. stopping\n"); + exit(1); + } + fi->q = fi->a + size; // end of region + if (fi->q > hard_limit) + fi->q = hard_limit; + + fi->runtime_vaddr = runtime_vaddr + fi->fake_base; + fi->runtime_vaddr_disas_start = fi->addr_start; + fi->runtime_vaddr_disas_end = fi->addr_end; + fi->symfn = get_symbol; + fi->caller_symbol_data = symbol_table; + fi->line_number_info_fn = 0; +#if defined(XED_DWARF) + fi->line_number_info_fn = find_line_number_info; +#endif + // pass in a function to retrieve valid symbol names + xed_disas_test(fi); +} + +static void +disas_test64(xed_disas_info_t* fi, + void* start, + unsigned int length, + Elf64_Off offset, + Elf64_Xword size, + Elf64_Addr runtime_vaddr, + xed_symbol_table_t* symbol_table) +{ + unsigned char* hard_limit = (unsigned char*)start + length; + fi->s = (unsigned char*)start; + + fi->a = (unsigned char*)start + offset; + if (fi->a > hard_limit) + fi->a = hard_limit; + if ((void*)(fi->a) < start) { + fprintf(stderr,"# malformed region limit. stopping\n"); + exit(1); + } + + fi->q = fi->a + size; // end of region + if (fi->q > hard_limit) + fi->q = hard_limit; + + fi->runtime_vaddr = runtime_vaddr + fi->fake_base; + fi->runtime_vaddr_disas_start = fi->addr_start; + fi->runtime_vaddr_disas_end = fi->addr_end; + fi->symfn = get_symbol; + fi->caller_symbol_data = symbol_table; + + fi->line_number_info_fn = 0; +#if defined(XED_DWARF) + fi->line_number_info_fn = find_line_number_info; +#endif + // pass in a function to retrieve valid symbol names + xed_disas_test(fi); +} + +#if !defined(EM_IAMCU) +# define EM_IAMCU 3 +#endif + +static int check_binary_32b(void* start) { + Elf32_Ehdr* elf_hdr = (Elf32_Ehdr*) start; + if ( elf_hdr->e_machine == EM_386 || + elf_hdr->e_machine == EM_IAMCU ) + return 1; + return 0; +} + +static int range_check(void* p, unsigned int esize, void* start, void* end) { + if (p < start || (unsigned char*)p+esize > (unsigned char*)end) + return 1; + return 0; +} + +void +process_elf32(xed_disas_info_t* fi, + void* start, + unsigned int length, + xed_symbol_table_t* symbol_table) +{ + Elf32_Ehdr* elf_hdr = (Elf32_Ehdr*) start; + Elf32_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf32_Shdr* shp = (Elf32_Shdr*) ((char*)start + shoff); + int sect_strings = elf_hdr->e_shstrndx; + xed_uint_t nsect = elf_hdr->e_shnum; + xed_uint_t i; + unsigned char* hard_limit = (unsigned char*)start + length; + + if ((void*)shp < start) + return; + + for(i=0;itarget_section) { + if (name && strcmp(fi->target_section, name)==0) + text = 1; + } + else if (shp[i].sh_flags & SHF_EXECINSTR) + text = 1; + } + + if (text && name) { + if (fi->xml_format == 0) { + printf("# SECTION " XED_FMT_D " ", i); + printf("%25s ", name); + printf("addr " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_addr)); + printf("offset " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_offset)); + printf("size " XED_FMT_LU " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_size)); + printf("type " XED_FMT_LU "\n", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_type)); + } + + xst_set_current_table(symbol_table,i); + disas_test32(fi, + start, length, shp[i].sh_offset, shp[i].sh_size, + shp[i].sh_addr, + symbol_table); + + } + + } +} + +/*-----------------------------------------------------------------*/ + +int check_binary_64b(void* start) { +#if !defined(EM_X86_64) /* EM_X86_64 is not present on android */ +# define EM_X86_64 62 +#endif +#if !defined(EM_L1OM) /* Oh, not zero */ +# define EM_L1OM 180 +#endif +#if !defined(EM_K1OM) /* Oh, not zero */ +# define EM_K1OM 181 +#endif + + Elf64_Ehdr* elf_hdr = (Elf64_Ehdr*) start; + if (elf_hdr->e_machine == EM_X86_64 || + elf_hdr->e_machine == EM_L1OM || + elf_hdr->e_machine == EM_K1OM) + return 1; + return 0; +} + + +/*-----------------------------------------------------------------*/ +void +process_elf64(xed_disas_info_t* fi, + void* start, + unsigned int length, + xed_symbol_table_t* symbol_table) +{ + Elf64_Ehdr* elf_hdr = (Elf64_Ehdr*) start; + Elf64_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf64_Shdr* shp = (Elf64_Shdr*) ((char*)start + shoff); + Elf64_Half sect_strings = elf_hdr->e_shstrndx; + Elf64_Half nsect = elf_hdr->e_shnum; + unsigned char* hard_limit = (unsigned char*)start + length; + unsigned int i; + xed_bool_t text = 0; + + if (CLIENT_VERBOSE1) + printf("# sections %d\n" , nsect); + + if ((void*)shp < start) + return; + + for( i=0;itarget_section) { + if (name && strcmp(fi->target_section, name)==0) + text = 1; + } + else if (shp[i].sh_flags & SHF_EXECINSTR) + text = 1; + } + + if (text && name) { + if (fi->xml_format == 0) { + printf("# SECTION " XED_FMT_U " ", i); + printf("%25s ", name); + printf("addr " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_addr)); + printf("offset " XED_FMT_LX " ", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_offset)); + printf("size " XED_FMT_LU "\n", + XED_STATIC_CAST(xed_uint64_t,shp[i].sh_size)); + } + xst_set_current_table(symbol_table,i); + disas_test64(fi, + start, length, shp[i].sh_offset, shp[i].sh_size, + shp[i].sh_addr, symbol_table); + } + } +} + + +void read_symbols64(void* start, + unsigned int len, + Elf64_Off offset, + Elf64_Xword size, + Elf64_Off string_table_offset, + xed_symbol_table_t* symtab) +{ + char* a = XED_STATIC_CAST(char*,start); + Elf64_Sym* p = XED_STATIC_CAST(Elf64_Sym*,a + offset); + Elf64_Sym* q = XED_STATIC_CAST(Elf64_Sym*,a + offset + size); + unsigned char* hard_limit = (unsigned char*)start + len; + if ((void*)p < start) + return; + if ((unsigned char*) p + sizeof(Elf64_Sym) > hard_limit) + p = (Elf64_Sym*)hard_limit; + if ((unsigned char*) q > hard_limit) + q = (Elf64_Sym*)hard_limit; + while(pst_info) == STT_FUNC) { + char* name = lookup64(p->st_name, start, len, string_table_offset); + if (name && xed_strlen(name) > 0) { + xst_add_local_symbol( + symtab, + XED_STATIC_CAST(xed_uint64_t,p->st_value), + name, p->st_shndx); + } + } + p++; + } +} + + +/*-----------------------------------------------------------------*/ + +static void print_comment64(unsigned int i, Elf64_Shdr* shp, char const* const s) +{ + fprintf(stdout,"# Found %s: %u",s, i); + // NOTE: casts required here because android gcc4.8.0 uses long long + // int for 64b integer and android-5 gcc490 uses long int. + fprintf(stdout," offset " XED_FMT_LX, (xed_uint64_t) shp[i].sh_offset); + fprintf(stdout," size " XED_FMT_LX "\n", (xed_uint64_t) shp[i].sh_size); +} +static void print_comment32(unsigned int i, Elf32_Shdr* shp, char const* const s) +{ + fprintf(stdout,"# Found %s: %u",s,i); + fprintf(stdout," offset %u",shp[i].sh_offset); + fprintf(stdout," size %u\n", shp[i].sh_size); +} + + + +static void +symbols_elf64(xed_disas_info_t* fi, + void* start, + unsigned int len, + xed_symbol_table_t* symtab) { + Elf64_Ehdr* elf_hdr = (Elf64_Ehdr*) start; + Elf64_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf64_Shdr* shp = (Elf64_Shdr*) ((char*)start + shoff); + Elf64_Half nsect = elf_hdr->e_shnum; + if (CLIENT_VERBOSE1) + printf("# sections %d\n" , nsect); + unsigned int i; + Elf64_Half sect_strings = elf_hdr->e_shstrndx; + Elf64_Off string_table_offset=0; + Elf64_Off dynamic_string_table_offset=0; + unsigned char* hard_limit = (unsigned char*)start + len; + + /* find the string_table_offset and the dynamic_string_table_offset */ + if ((void*)shp < start) + return; + + for( i=0;ixml_format == 0) { + print_comment64(i,shp, "strtab"); + } + string_table_offset = shp[i].sh_offset; + } + if (strcmp(name,".dynstr")==0) { + if (fi->xml_format == 0) { + print_comment64(i,shp, "dynamic strtab"); + } + dynamic_string_table_offset = shp[i].sh_offset; + } + } + } + } + /* now read the symbols */ + for( i=0;ixml_format == 0) { + print_comment64(i,shp, "symtab"); + } + read_symbols64(start, len, shp[i].sh_offset, shp[i].sh_size, + string_table_offset,symtab); + } + else if (shp[i].sh_type == SHT_DYNSYM && dynamic_string_table_offset) { + if (fi->xml_format == 0) { + print_comment64(i,shp, "dynamic symtab"); + } + read_symbols64(start, len, shp[i].sh_offset, shp[i].sh_size, + dynamic_string_table_offset, symtab); + } + } +} + + + +static void +read_symbols32(void* start, + unsigned int len, + Elf32_Off offset, + Elf32_Word size, + Elf32_Off string_table_offset, + xed_symbol_table_t* symtab) { + char* a = XED_STATIC_CAST(char*,start); + Elf32_Sym* p = XED_STATIC_CAST(Elf32_Sym*,a + offset); + Elf32_Sym* q = XED_STATIC_CAST(Elf32_Sym*,a + offset + size); + + unsigned char* hard_limit = (unsigned char*)start + len; + if ((void*)p < start) + return; + + if ((unsigned char*) p + sizeof(Elf32_Sym) > hard_limit) + p = (Elf32_Sym*)hard_limit; + if ((unsigned char*) q > hard_limit) + q = (Elf32_Sym*)hard_limit; + + while(pst_info) == STT_FUNC) { + char* name = lookup32(p->st_name, start, len, string_table_offset); + if (name && xed_strlen(name) > 0) { + xst_add_local_symbol( + symtab, + XED_STATIC_CAST(xed_uint64_t,p->st_value), + name, p->st_shndx); + } + } + p++; + } +} + + + +static void +symbols_elf32(xed_disas_info_t* fi, + void* start, + unsigned int len, + xed_symbol_table_t* symtab) +{ + Elf32_Ehdr* elf_hdr = (Elf32_Ehdr*) start; + Elf32_Off shoff = elf_hdr->e_shoff; // section hdr table offset + Elf32_Shdr* shp = (Elf32_Shdr*) ((char*)start + shoff); + Elf32_Half nsect = elf_hdr->e_shnum; + if (CLIENT_VERBOSE1) + printf("# sections %d\n" , nsect); + unsigned int i; + Elf32_Off string_table_offset=0; + Elf32_Off dynamic_string_table_offset=0; + int sect_strings = elf_hdr->e_shstrndx; + unsigned char* hard_limit = (unsigned char*)start + len; + + if ((void*)shp < start) + return; + + /* find the string_table_offset and the dynamic_string_table_offset */ + for( i=0;ixml_format == 0) { + print_comment32(i,shp, "strtab"); + } + string_table_offset = shp[i].sh_offset; + } + if (strcmp(name,".dynstr")==0) { + if (fi->xml_format == 0) { + print_comment32(i,shp, "dynamic strtab"); + } + dynamic_string_table_offset = shp[i].sh_offset; + } + } + } + } + + /* now read the symbols */ + for( i=0;ixml_format == 0) { + print_comment32(i,shp, "symtab"); + } + read_symbols32(start, len, shp[i].sh_offset, shp[i].sh_size, + string_table_offset, symtab); + } + else if (shp[i].sh_type == SHT_DYNSYM && dynamic_string_table_offset) + { + if (fi->xml_format == 0) { + print_comment32(i,shp, "dynamic symtab"); + } + read_symbols32(start, len, shp[i].sh_offset, shp[i].sh_size, + dynamic_string_table_offset, symtab); + } + } +} + + +void +xed_disas_elf(xed_disas_info_t* fi) +{ + void* region = 0; + unsigned int len = 0; + xed_symbol_table_t symbol_table; + + xed_disas_elf_init(); + xed_map_region(fi->input_file_name, ®ion, &len); + xed_symbol_table_init(&symbol_table); + +#if defined(XED_DWARF) + if (fi->line_numbers) + read_dwarf_line_numbers(region,len); +#endif + + if (check_binary_64b(region)) { + if (fi->sixty_four_bit == 0 && fi->use_binary_mode) { + /* modify the default dstate values because we were not expecting a + * 64b binary */ + fi->dstate.mmode = XED_MACHINE_MODE_LONG_64; + } + + symbols_elf64(fi,region, len, &symbol_table); + process_elf64(fi, region, len, &symbol_table); + } + else if (check_binary_32b(region)) { + symbols_elf32(fi, region, len, &symbol_table); + process_elf32(fi, region, len, &symbol_table); + } + else { + fprintf(stderr,"Not a recognized 32b or 64b ELF binary.\n"); + exit(1); + } + if (fi->xml_format == 0){ + xed_print_decode_stats(fi); + xed_print_encode_stats(fi); + } +} + + + +#endif +//////////////////////////////////////////////////////////////////////////// + diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-elf.h b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-elf.h new file mode 100644 index 0000000..374191e --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-elf.h @@ -0,0 +1,34 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-elf.h + +#if !defined(XED_DISAS_ELF_H) +# define XED_DISAS_ELF_H +#if defined(__linux) || defined(__linux__) || defined(__FreeBSD__) || defined(__NetBSD__) +# define XED_ELF_READER +#endif +# if defined(XED_ELF_READER) + + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" + +void xed_disas_elf(xed_disas_info_t* fi); + +# endif +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-filter.c b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-filter.c new file mode 100644 index 0000000..3d3c9f7 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-filter.c @@ -0,0 +1,105 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include +#include +#include +#include + +#include +#include "xed-examples-util.h" +#include "xed-disas-filter.h" +#include "xed-symbol-table.h" +#include "xed-nm-symtab.h" + +#define IMAX 32 +#define LINELEN 1024 + +static int len_hex(char *s) +{ + char *p = s; + while (isxdigit(*p)) + p++; + return (int)(p - s); +} + +static unsigned long get_ip(char *line) +{ + char *num; + for (num = line; *num; num++) { + int l; + if (isxdigit(*num) && (l = len_hex(num)) >= 8 && isspace(num[l])) { + return strtoul(num, NULL, 16); + } + } + return 0; +} + +/* Decode fields in lines of the form + + prefix hexbytes ... + + and replace it in the output with the decoded instruction. Each line + is assumed to be a single instruction for now. + + Optionally we look for a another hex address before prefix that gives + the IP. */ + +xed_uint_t disas_filter(xed_decoded_inst_t *inst, char *prefix, xed_disas_info_t *di) +{ + char line[LINELEN]; + + di->symfn = get_symbol; + xed_register_disassembly_callback(xed_disassembly_callback_function); + while (fgets(line, LINELEN, stdin)) { + xed_error_enum_t err; + char *insn = strstr(line, prefix), *ip; + xed_uint_t ilen; + char out[256]; + unsigned long val; + char *endp; + xed_uint8_t insnbuf[IMAX]; + + if (!insn) { + fputs(line, stdout); + continue; + } + + ip = insn + strlen(prefix); + ilen = 0; + do { + val = strtoul(ip, &endp, 16); + if (insn == endp) + break; + insnbuf[ilen++] = (xed_uint8_t)val; + ip = endp; + } while (ilen < IMAX); + xed_state_t state; + xed_state_zero(&state); + xed_state_set_machine_mode(&state, di->dstate.mmode); + xed_decoded_inst_zero_set_mode(inst, &state); + if ((err = xed_decode(inst, insnbuf, ilen)) != XED_ERROR_NONE) { + snprintf(out, sizeof out, "%s" , xed_error_enum_t2str(err)); + } else { + disassemble(di, out, sizeof out, inst, get_ip(line), + nm_symtab_init ? &nm_symtab : NULL); + } + printf("%.*s\t\t%s%s", (int)(insn - line), line, out, endp); + } + return 0; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-filter.h b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-filter.h new file mode 100644 index 0000000..8c20df9 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-filter.h @@ -0,0 +1,19 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +xed_uint_t disas_filter(xed_decoded_inst_t *inst, char *prefix, xed_disas_info_t *di); diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-hex.c b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-hex.c new file mode 100644 index 0000000..aa95352 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-hex.c @@ -0,0 +1,110 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// to avoid empty compilation unit on no-decoder compiles +#include "xed/xed-interface.h" + +#if defined(XED_DECODER) +#include "xed-examples-util.h" +#include "xed-disas-hex.h" + +#include +#include + + + +static FILE* +open_file(char const* const path, char const* const mode) +{ + FILE* f; +#if defined(XED_MSVC8_OR_LATER) && !defined(PIN_CRT) + errno_t err; + err = fopen_s(&f,path, mode); +#else + int err=0; + f = fopen(path, mode); + err = (f==0); +#endif + if (err) { + fprintf(stderr, "Could not open file: %s\n", path); + exit(1); + } + return f; +} + +static int read_byte(FILE* f, xed_uint8_t* b) { + int r; + unsigned int i; +#if defined(_WIN32) && !defined(PIN_CRT) + r = fscanf_s(f,"%2x", &i); +#else + r = fscanf(f,"%2x", &i); +#endif + if (b) + *b = (xed_uint8_t)i; + return r; +} + +void +xed_disas_hex(xed_disas_info_t* fi) +{ + xed_uint8_t* region = 0; + unsigned int len = 0; + unsigned int i = 0; + xed_uint8_t b = 0; + FILE* f = 0; + + // read file once to get length + f = open_file(fi->input_file_name, "r"); + while (read_byte(f,0) != -1) + { + len++; + } + fclose(f); + + region = (xed_uint8_t*) malloc(len); + if (region == 0) { + fprintf(stderr,"ERROR: Could not malloc region for hex file\n"); + exit(1); + } + + // read file again to read the bytes + f = open_file(fi->input_file_name, "r"); + while (read_byte(f,&b) != -1) + { + assert(i < len); + region[i++] = b; + } + fclose(f); + assert(i==len); + + fi->s = (unsigned char*)region; + fi->a = (unsigned char*)region; + fi->q = (unsigned char*)(region) + len; // end of region + fi->runtime_vaddr = 0; + fi->runtime_vaddr_disas_start = 0; + fi->runtime_vaddr_disas_end = 0; + fi->symfn = 0; + fi->caller_symbol_data = 0; + fi->line_number_info_fn = 0; + xed_disas_test(fi); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-hex.h b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-hex.h new file mode 100644 index 0000000..9252096 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-hex.h @@ -0,0 +1,30 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_DISAS_HEX_H) +# define XED_DISAS_HEX_H + + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" + +void +xed_disas_hex(xed_disas_info_t* fi); + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-macho.c b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-macho.c new file mode 100644 index 0000000..2ee3d0c --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-macho.c @@ -0,0 +1,463 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-macho.cpp + +#include "xed/xed-interface.h" // to get defines +#if defined(__APPLE__) && defined(XED_DECODER) + +// mac specific headers +#include +#include +#include +#include + +#include "xed-disas-macho.h" +#include "xed-examples-util.h" +#include "xed-symbol-table.h" + +#include + +//////////////////////////////////////////////////////////////////////////// + +xed_uint32_t +swap_endian(xed_uint32_t x) +{ + xed_uint32_t r = 0; + xed_uint32_t t = x; + xed_uint_t i; + for(i=0;i<4;i++) + { + xed_uint8_t b = (xed_uint8_t) (t&0xFF); + r =(r << 8) | b; + t = t >> 8; + } + return r; +} + +xed_uint32_t +read_fat_header_narch(xed_uint8_t const* const current_position) +{ + struct fat_header* fh = + XED_CAST(struct fat_header*,current_position); + + // we are little endian looking at big endian data + if (fh->magic == FAT_CIGAM) + { + xed_uint32_t narch = swap_endian(fh->nfat_arch); + return narch; + } + return 0; +} + +xed_bool_t +read_fat_header(xed_uint8_t const* const current_position, + xed_uint32_t fat_arch_slot, + xed_uint32_t* offset, + xed_uint32_t* size) +{ + struct fat_header* fh = + XED_CAST(struct fat_header*,current_position); + + // we are little endian looking at big endian data + if (fh->magic == FAT_CIGAM) + { + struct fat_arch* fa = + XED_CAST(struct fat_arch*,current_position + + sizeof(struct fat_header) + + fat_arch_slot*sizeof(struct fat_arch) ); + const cpu_type_t cpu_type = (cpu_type_t) swap_endian((xed_uint32_t)fa->cputype); + + if ((cpu_type & CPU_TYPE_I386) != 0) + { + if ((cpu_type & CPU_ARCH_ABI64) != 0) + printf ("# x86 64b\n"); + else + printf ("# x86 32b\n"); + *offset = swap_endian(fa->offset); + *size = swap_endian(fa->size); + return 1; + } + } + return 0; +} + + +static xed_bool_t +executable(xed_uint32_t flags) +{ + return ( (flags & S_ATTR_PURE_INSTRUCTIONS) !=0 || + (flags & S_ATTR_SOME_INSTRUCTIONS) !=0 ); +} + +void +process_segment32( xed_uint_t* sectoff, + xed_disas_info_t* decode_info, + xed_uint8_t* start, + xed_uint8_t* segment_position, + unsigned int bytes, + xed_symbol_table_t* symbol_table, + xed_uint64_t vmaddr) +{ + struct segment_command* sc = + XED_CAST(struct segment_command*,segment_position); + xed_uint8_t* start_of_section_data = + segment_position + sizeof(struct segment_command); + unsigned int i; + // look through the array of section headers for this segment. + for( i=0; i< sc->nsects;i++) + { + struct section* sp = + XED_CAST(struct section*, + start_of_section_data + i *sizeof(struct section)); + + if (executable(sp->flags)) + { + // this section is executable. Go get it and process it. + xed_uint8_t* section_text = start + sp->offset; + xed_uint32_t runtime_vaddr = sp->addr; + + decode_info->s = start; + decode_info->a = section_text; + decode_info->q = section_text + sp->size; + decode_info->runtime_vaddr = runtime_vaddr + decode_info->fake_base; + decode_info->runtime_vaddr_disas_start = (xed_uint64_t)decode_info->addr_start; + decode_info->runtime_vaddr_disas_end = (xed_uint64_t)decode_info->addr_end; + decode_info->symfn = get_symbol; + decode_info->caller_symbol_data = symbol_table; + decode_info->input_file_name = decode_info->input_file_name; + decode_info->line_number_info_fn = 0; + xst_set_current_table(symbol_table,i+1 + *sectoff); + xed_disas_test(decode_info); + + } + } + *sectoff += sc->nsects; + (void) bytes; (void) vmaddr; +} + + +void +process_segment64( xed_uint_t* sectoff, + xed_disas_info_t* decode_info, + xed_uint8_t* start, + xed_uint8_t* segment_position, + unsigned int bytes, + xed_symbol_table_t* symbol_table, + xed_uint64_t vmaddr) +{ + struct segment_command_64* sc = + XED_CAST(struct segment_command_64*,segment_position); + xed_uint8_t* start_of_section_data = + segment_position + sizeof(struct segment_command_64); + unsigned int i; + /* modify the default dstate values because we were not expecting a + * 64b binary */ + decode_info->dstate.mmode = XED_MACHINE_MODE_LONG_64; + // look through the array of section headers for this segment. + for( i=0; i< sc->nsects;i++) + { + struct section_64* sp = + XED_CAST(struct section_64*, + start_of_section_data + i *sizeof(struct section_64)); + if (executable(sp->flags)) + { + + // this section is executable. Go get it and process it. + xed_uint8_t* section_text = start + sp->offset; + xed_uint64_t runtime_vaddr = sp->addr; + + decode_info->s = start; + decode_info->a = section_text; + decode_info->q = section_text + sp->size; + decode_info->runtime_vaddr = runtime_vaddr + decode_info->fake_base; + decode_info->runtime_vaddr_disas_start = (xed_uint64_t)decode_info->addr_start; + decode_info->runtime_vaddr_disas_end = (xed_uint64_t)decode_info->addr_end; + decode_info->symfn = get_symbol; + decode_info->caller_symbol_data = symbol_table; + decode_info->input_file_name = decode_info->input_file_name; + decode_info->line_number_info_fn = 0; + xst_set_current_table(symbol_table,i + 1 + *sectoff); + xed_disas_test(decode_info); + + } + + } + *sectoff += sc->nsects; + (void) bytes; (void) vmaddr; +} + +//////////////////////////////////////////////////////////////////////////// + + +void process_symbols32(xed_disas_info_t* decode_info, + xed_uint8_t* pos, + xed_uint8_t* current_position, + xed_symbol_table_t* symbol_table) { + struct symtab_command* symtab = + XED_CAST(struct symtab_command*,current_position); + /* symbols */ + xed_uint32_t nsyms = symtab->nsyms; + xed_uint8_t* symoff = pos + symtab->symoff; + /* strings table */ + xed_uint8_t* stroff = pos + symtab->stroff; + /* xed_uint8_t* stroff_end = stroff + symtab->strsize; */ + xed_uint32_t i; + struct nlist* p; + p = XED_CAST(struct nlist*, symoff); + for(i=0;in_type & N_STAB) == 0 && + (p->n_type & N_TYPE) == N_SECT) + { + char* str=0; + str = XED_CAST(char*,stroff + p->n_un.n_strx); + + xst_add_local_symbol( + symbol_table, + XED_CAST(xed_uint64_t,p->n_value), + str, + p->n_sect); + } + p++; + } + (void)decode_info; +} + +void process_symbols64(xed_disas_info_t* decode_info, + xed_uint8_t* pos, + xed_uint8_t* current_position, + xed_symbol_table_t* symbol_table) { + struct symtab_command* symtab = + XED_CAST(struct symtab_command*,current_position); + /* symbols */ + xed_uint32_t nsyms = symtab->nsyms; + xed_uint8_t* symoff = pos + symtab->symoff; + /* strings table */ + xed_uint8_t* stroff = pos + symtab->stroff; + xed_uint32_t i; + struct nlist_64* p; + + p = XED_CAST(struct nlist_64*, symoff); + for(i=0;in_type & N_STAB) == 0 && + (p->n_type & N_TYPE) == N_SECT) + { + char* str=0; + str = XED_CAST(char*,stroff + p->n_un.n_strx); + + xst_add_local_symbol( + symbol_table, + XED_CAST(xed_uint64_t,p->n_value), + str, + p->n_sect); + } + p++; + } + (void)decode_info; +} + + +void process32(xed_disas_info_t* decode_info, + xed_uint8_t* current_position, + struct mach_header* mh, + xed_uint8_t* pos) +{ + xed_symbol_table_t symbol_table; + xed_uint_t i, sectoff=0; + if (CLIENT_VERBOSE2) + printf("Number of load command sections = %d\n", mh->ncmds); + // load commands point to segments which contain sections. + decode_info->dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + xed_uint8_t* tmp_current_position = current_position; + xed_symbol_table_init(&symbol_table); + + for( i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,tmp_current_position); + // FIXME: not handling LD_DYSYMTAB + if (lc->cmd == LC_SYMTAB) { + process_symbols32(decode_info, + pos, + tmp_current_position, + &symbol_table); + } + tmp_current_position += lc->cmdsize; + } + + for(i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,current_position); + + if (CLIENT_VERBOSE2) + printf("load command %d\n", i); + if (lc->cmd == LC_SEGMENT) { + if (CLIENT_VERBOSE2) + printf("\tload command %d is a LC_SEGMENT\n", i); + // we add the FAT offset to the start pointer to get to the + // relative start point. + struct segment_command* sc = + XED_CAST(struct segment_command*,lc); + process_segment32( §off, + decode_info, + pos, + current_position, + lc->cmdsize , + &symbol_table, + sc->vmaddr); + } + current_position += lc->cmdsize; + } +} +void process64(xed_disas_info_t* decode_info, + xed_uint8_t* current_position, + struct mach_header_64* mh, + xed_uint8_t* pos) +{ + + xed_uint_t i, sectoff=0; + xed_symbol_table_t symbol_table; + if (CLIENT_VERBOSE2) + printf("Number of load command sections = %d\n", mh->ncmds); + // load commands point to segments which contain sections. + xed_uint8_t* tmp_current_position = current_position; + xed_symbol_table_init(&symbol_table); + + for( i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,tmp_current_position); + // FIXME: not handling LD_DYSYMTAB + if ( lc->cmd == LC_SYMTAB ) { + process_symbols64(decode_info, + pos, + tmp_current_position, + &symbol_table); + } + tmp_current_position += lc->cmdsize; + } + + for( i=0;i< mh->ncmds; i++) { + struct load_command* lc = + XED_CAST(struct load_command*,current_position); + + if (CLIENT_VERBOSE2) + printf("load command %x\n", i); + if (lc->cmd == LC_SEGMENT_64) { + if (CLIENT_VERBOSE2) + printf("\tload command %d is a LC_SEGMENT\n", i); + // we add the FAT offset to the start pointer to get to the + // relative start point. + struct segment_command_64* sc = + XED_CAST(struct segment_command_64*,lc); + process_segment64( §off, + decode_info, + pos, + current_position, + lc->cmdsize, + &symbol_table, + sc->vmaddr ); + } + current_position += lc->cmdsize; + } +} + + +void +process_macho(xed_uint8_t* start, + unsigned int length, // FIXME: Use this! Trusting internal consistency of headers + xed_disas_info_t* decode_info) + +{ + xed_uint8_t* base_pos = start; + xed_uint32_t narch = read_fat_header_narch(base_pos); + xed_uint32_t fat_arch_slot=0; + + xed_uint32_t lim = 1; + + // we have one section if not a fat binary. + if (narch > lim) + lim = narch; + + for (fat_arch_slot = 0; fat_arch_slot < lim; fat_arch_slot++) + { + xed_uint32_t offset=0; + xed_uint32_t size; + xed_bool_t okay = 0; + + if (narch) // for fat binaries + okay = read_fat_header(base_pos, fat_arch_slot, &offset, &size); + + if (CLIENT_VERBOSE2 && !okay) + if (decode_info->xml_format == 0) + xedex_dwarn("Could not find x86 section of fat binary " + "-- checking for mach header"); + if (CLIENT_VERBOSE2) + printf("Offset of load sections = %x\n", offset); + + xed_uint8_t* current_position = base_pos + offset; + + if (narch > 0) + printf("# FAT ARCH SECTION = %d\n", fat_arch_slot); + struct mach_header* mh = + XED_CAST(struct mach_header*,current_position); + struct mach_header_64* mh64 = + XED_CAST(struct mach_header_64*,current_position); + if (mh->magic == MH_MAGIC) { + current_position += sizeof(struct mach_header); + process32(decode_info, + current_position, + mh, + start+offset); + } + else if (mh64->magic == MH_MAGIC_64) { + current_position += sizeof(struct mach_header_64); + process64(decode_info, + current_position, + mh64, + start+offset); + } + else + xedex_derror("Could not find mach header"); + } // for + + (void) length; +} + +void xed_disas_macho_init(void) { + xed_register_disassembly_callback(xed_disassembly_callback_function); +} + + +void +xed_disas_macho(xed_disas_info_t* fi) +{ + xed_uint8_t* region = 0; + void* vregion = 0; + unsigned int len = 0; + + xed_disas_macho_init(); + xed_map_region(fi->input_file_name, &vregion, &len); + + region = XED_CAST(xed_uint8_t*,vregion); + process_macho(region, len, fi); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-macho.h b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-macho.h new file mode 100644 index 0000000..9dca44b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-macho.h @@ -0,0 +1,29 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-macho.H +#if !defined(XED_DISAS_MACHO_H) +# define XED_DISAS_MACHO_H + +# if defined(__APPLE__) +# include "xed/xed-interface.h" +# include "xed-examples-util.h" + +void +xed_disas_macho(xed_disas_info_t* fi); +# endif +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-pecoff.cpp b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-pecoff.cpp new file mode 100644 index 0000000..dc2e524 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-pecoff.cpp @@ -0,0 +1,698 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-pecoff.cpp + +//// ONLY COMPILES IF -mno-cygwin is thrown on to GCC compilations +extern "C" { +#include "xed/xed-interface.h" // for XED_DECODER +} +#if defined(XED_DECODER) +#include +#include + +#if defined(XED_MSVC8_OR_LATER) && !defined(XED_64B) + // to enable the wow64 redirection function on MSVC8 +# define _WIN32_WINNT 0x0501 +#endif +#include +#include + +// xed headers -- THESE MUST BE AFTER THE WINDOWS HEADERS + +extern "C" { +#include "xed-disas-pecoff.h" + +// This really must be after the windows.h include +#include "xed-symbol-table.h" +} + +#if defined(XED_DBGHELP) +# include "udhelp.H" // dbghelp interface +#endif +using namespace std; + +static void +windows_error(const char* syscall, + const char* filename) +{ + printf("Mapped file:: %s",syscall); + printf(" for file %s failed: ", filename); + switch (GetLastError()) + { + case 2: + printf("File not found"); + break; + case 3: + printf("Path not found"); + break; + case 5: + printf("Access denied"); + break; + case 15: + printf("Invalid drive"); + break; + default: + printf("error code %u", + XED_STATIC_CAST(xed_uint32_t,GetLastError())); + break; + } + xedex_derror("Exiting."); +} + +typedef int (WINAPI *fptr_t)(void*); + +static fptr_t find_fn_ptr(const char* function_name) { + fptr_t p; + + p = (fptr_t) GetProcAddress( + GetModuleHandle(TEXT("kernel32.dll")), + function_name); + return p; +} + +static int find_wow64_redir(fptr_t* disable, fptr_t* revert) { + *disable = find_fn_ptr("Wow64DisableWow64FsRedirection"); + *revert = find_fn_ptr("Wow64RevertWow64FsRedirection"); + if (*disable && *revert) + return 1; // success + return 0; +} + +class pecoff_reader_t +{ + /// NT handle for the open file. + void* file_handle_; + + /// NT handle for the memory mapping. + void* map_handle_; + + void* base_; + xed_bool_t okay_; + xed_bool_t sixty_four_bit_; + + const IMAGE_FILE_HEADER* ifh; + const IMAGE_SECTION_HEADER* hdr; + const IMAGE_SECTION_HEADER* orig_hdr; + unsigned int nsections; + xed_uint64_t image_base; + xed_bool_t verbose; + + +public: + xed_uint32_t section_index; + + pecoff_reader_t(int arg_verbose=1) + { + verbose = arg_verbose; + init(); + } + ~pecoff_reader_t() + { + close(); + } + + void* base() const { return base_; } + xed_bool_t okay() const { return okay_; } + xed_bool_t sixty_four_bit() const { return sixty_four_bit_; } + + void + init() + { + file_handle_ = INVALID_HANDLE_VALUE; + map_handle_ = INVALID_HANDLE_VALUE; + okay_ = false; + sixty_four_bit_ = false; + + hdr=0; + orig_hdr=0; + nsections=0; + image_base=0; + section_index=0; + } + + void + close() + { + if (base_) + { + UnmapViewOfFile(base_); + } + if (map_handle_ != INVALID_HANDLE_VALUE) + { + CloseHandle(map_handle_); + } + if (file_handle_ != INVALID_HANDLE_VALUE) + { + CloseHandle(file_handle_); + } + + init(); + } + + + xed_bool_t + map_region(const char* input_file_name, + void*& vregion, + xed_uint32_t& len) + { + okay_ = false; + +#if defined(XED_MSVC8_OR_LATER) && !defined(XED_64B) + bool disabled_redirection = false; + void* old=0; + fptr_t disable, revert; + if (find_wow64_redir(&disable, &revert)) + if ( (*disable)(&old) ) + disabled_redirection = true; +#endif + + file_handle_ = CreateFileA(input_file_name, + GENERIC_READ, + FILE_SHARE_READ, + NULL, + OPEN_EXISTING, + FILE_FLAG_NO_BUFFERING + FILE_ATTRIBUTE_READONLY, + NULL); + +#if defined(XED_MSVC8_OR_LATER) && !defined(XED_64B) + if (disabled_redirection) { + if (! (*revert)(old)) { + fprintf(stderr,"Could not re-enable wow64 redirection. Dying...\n"); + exit(1); + } + } +#endif + if (file_handle_ == INVALID_HANDLE_VALUE) { + windows_error("CreateFile", input_file_name); + } + + map_handle_ = CreateFileMapping(file_handle_, + NULL, + PAGE_READONLY, + 0, + 0, + NULL); + + if (map_handle_ == INVALID_HANDLE_VALUE) { + windows_error("CreateFileMapping", input_file_name); + } + + base_ = MapViewOfFile(map_handle_, + FILE_MAP_READ, 0, 0, 0); + if (base_ != NULL) { + okay_ = true; + vregion = base_; + len = 0; //FIXME + return true; + } + CloseHandle(map_handle_); + map_handle_ = INVALID_HANDLE_VALUE; + + CloseHandle(file_handle_); + file_handle_ = INVALID_HANDLE_VALUE; + return false; + + } + + + xed_bool_t read_header() { + if (! parse_nt_file_header(&nsections, &image_base, &hdr)) { + xedex_derror("Could not read nt file header"); + return false; + } + + orig_hdr=hdr; + return true; + } + + + void read_coff_symbols() { + xed_uint32_t i; + xed_uint32_t sym_offset = ifh->PointerToSymbolTable; + xed_uint32_t nsym = ifh->NumberOfSymbols; + PIMAGE_SYMBOL p = (PIMAGE_SYMBOL)((char*)base() + sym_offset); + char* string_table_base = (char*)(p+nsym); + for(i=0;iCharacteristics); + if ((jhdr->Characteristics & IMAGE_SCN_CNT_CODE) == IMAGE_SCN_CNT_CODE) + { + printf(" CODE"); + xed_uint8_t* section_start; + xed_uint32_t section_size; + xed_uint64_t virtual_addr; + + virtual_addr = jhdr->VirtualAddress + image_base; + section_size = (jhdr->Misc.VirtualSize > 0 ? + jhdr->Misc.VirtualSize + : jhdr->SizeOfRawData); + section_start = (xed_uint8_t*)ptr_add(base_, + jhdr->PointerToRawData); + + printf(" VAddr " XED_FMT_LX16, virtual_addr); + printf(" SecStart %p" , section_start); + printf(" %016I64x" , (xed_uint64_t)jhdr->PointerToRawData); + printf(" SecSize " XED_FMT_08X,section_size); + } + printf("\n"); + } + } + + xed_bool_t + module_section_info( + const char* secname, + xed_uint8_t*& section_start, + xed_uint32_t& section_size, + xed_uint64_t& virtual_addr) + { + unsigned int i,ii; + char my_name[IMAGE_SIZEOF_SHORT_NAME]; + unsigned int match_len = 0; + + // Extract the name into a 0-padded 8 byte string. + if (secname) { + memset(my_name,0,IMAGE_SIZEOF_SHORT_NAME); + for( i=0;i(strlen(secname)); + if (match_len > IMAGE_SIZEOF_SHORT_NAME) + match_len = IMAGE_SIZEOF_SHORT_NAME; + } + + // There are section names that LOOK like .text$x but they really have + // a null string embedded in them. So when you strcmp, you hit the + // null. + + + for ( ii = section_index; ii < nsections; ii++, hdr++) + { + int found = 0; + if (hdr->SizeOfRawData == 0) + continue; + /* If no section name, match codde sections. If we have a + section name that matches , just disasssemble whatever they + want. */ + if (secname==0) { + if ((hdr->Characteristics & IMAGE_SCN_CNT_CODE) == + IMAGE_SCN_CNT_CODE) + found = 1; + } + else if (strncmp(reinterpret_cast(hdr->Name), + my_name, match_len) == 0) + { + found = 1; + } + if (found) { + // Found it. Extract the info and return. + virtual_addr = hdr->VirtualAddress + image_base; + section_size = (hdr->Misc.VirtualSize > 0 ? + hdr->Misc.VirtualSize + : hdr->SizeOfRawData); + section_start = (xed_uint8_t*)ptr_add(base_, + hdr->PointerToRawData); + section_index = ii+1; + hdr++; + return true; + } + } + section_index = ii; + return false; + } + +private: + static inline const void* + ptr_add(const void* ptr, unsigned int n) { + return static_cast(ptr)+n; + } + + xed_bool_t + is_valid_module() { + // Point to the DOS header and check it. + const IMAGE_DOS_HEADER* dh = static_cast(base_); + if (dh->e_magic != IMAGE_DOS_SIGNATURE) + return false; + + // Point to the PE signature word and check it. + const DWORD* sig = static_cast(ptr_add(base_, dh->e_lfanew)); + + // This must be a valid PE file with a valid DOS header. + if (*sig != IMAGE_NT_SIGNATURE) + return false; + + return true; + } + xed_bool_t + parse_nt_file_header(unsigned int* pnsections, + xed_uint64_t* pimage_base, + const IMAGE_SECTION_HEADER** phdr) + { + // Oh joy - the format of a .obj file on Windows is *different* + // from the format of a .exe file. Deal with that. + + // Check the header to see if this is a valid .exe file + if (is_valid_module()) + { + // Point to the DOS header. + const IMAGE_DOS_HEADER* dh = + static_cast(base_); + + // Point to the COFF File Header (just after the signature) + ifh = static_cast(ptr_add(base_, + dh->e_lfanew + 4)); + } + else + { + // Maybe this is a .obj file, which starts with the image file header + ifh = static_cast(base_); + } + + + +#if !defined(IMAGE_FILE_MACHINE_AMD64) +# define IMAGE_FILE_MACHINE_AMD64 0x8664 +#endif + + if (ifh->Machine == IMAGE_FILE_MACHINE_I386) { + if (verbose) + printf("# IA32 format\n"); + sixty_four_bit_ = false; + } + else if (ifh->Machine == IMAGE_FILE_MACHINE_AMD64) { + if (verbose) + printf("# Intel64 format\n"); + sixty_four_bit_ = true; + } + else { + // We only support Windows formats on IA32 and Intel64 + return false; + } + + *pimage_base = 0; + + // Very important to use the 32b header here because the + // unqualified IMAGE_OPTIONAL_HEADER gets the wrong version on + // win64! + const IMAGE_OPTIONAL_HEADER32* opthdr32 + = static_cast(ptr_add(ifh, sizeof(*ifh))); + + // Cygwin's w32api winnt.h header doesn't distinguish 32 and 64b. +#if !defined(IMAGE_NT_OPTIONAL_HDR32_MAGIC) +# define IMAGE_NT_OPTIONAL_HDR32_MAGIC IMAGE_NT_OPTIONAL_HDR_MAGIC +#endif + // And it lacks the definition for 64b headers +#if !defined(IMAGE_NT_OPTIONAL_HDR64_MAGIC) +# define IMAGE_NT_OPTIONAL_HDR64_MAGIC 0x20b +#endif + + if (ifh->SizeOfOptionalHeader > 0) + { + if (opthdr32->Magic == IMAGE_NT_OPTIONAL_HDR32_MAGIC) + { + *pimage_base = opthdr32->ImageBase; + } + else if (opthdr32->Magic == IMAGE_NT_OPTIONAL_HDR64_MAGIC) + { +#if defined(_MSC_VER) +# if _MSC_VER >= 1400 + const IMAGE_OPTIONAL_HEADER64* opthdr64 = + static_cast( + ptr_add(ifh, sizeof(*ifh))); + *pimage_base = opthdr64->ImageBase; +# else + xedex_derror("No support for 64b optional headers because " + "older MS compilers do not have the type yet"); +# endif +#else + xedex_derror("No support for 64b optional headers because " + "cygwin does nt have the type yet"); + return false; +#endif + } + else + { + // Optional header is not a form we recognize, so punt. + return false; + } + } + + // Point to the first of the Section Headers + *phdr = static_cast(ptr_add(opthdr32, + ifh->SizeOfOptionalHeader)); + *pnsections = ifh->NumberOfSections; + return true; + } + + + +}; + +//////////////////////////////////////////////////////////////////////////// +#if defined(XED_USING_DEBUG_HELP) +static dbg_help_client_t dbg_help; + +extern "C" void +print_file_and_line(xed_uint64_t addr) +{ + char* filename; + xed_uint32_t line, column; + + if (dbg_help.get_file_and_line(addr, &filename, &line, &column)) + { + if (column) + printf( " # %s:%d.%d", filename, line, column); + else + printf( " # %s:%d", filename, line); + free(filename); + } +} + +char* windows_symbols_callback(xed_uint64_t addr, void* closure) { + dbg_help_client_t* p = (dbg_help_client_t*)closure; + char buffer[2000]; + int r = p->get_symbol(addr, buffer, sizeof(char)*2000); + if (r == 0) { + int n = (int)strlen(buffer)+1; + char* symbol = new char[n]; + symbol[0]=0; + xed_strncat(symbol, buffer, n); + return symbol; + } + else { + return 0; + } +} + +int xed_pecoff_callback_function( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* caller_data) +{ + dbg_help_client_t* p = (dbg_help_client_t*)caller_data; + int r = p->get_symbol(address, symbol_buffer, buffer_length, offset); + if (r == 0) + return 1; + return 0; +} +#endif + +void xed_disas_pecoff_init() { +#if defined(XED_USING_DEBUG_HELP) + if (dbg_help.valid()) { + //xed_register_disassembly_callback(xed_pecoff_callback_function); + xed_register_disassembly_callback(xed_disassembly_callback_function); + } +#endif +} + +bool dot_obj(const char* s) { + int len = (int)strlen(s); + const char* p = s + len - 4; + if (strcmp(p,".obj") == 0 || + strcmp(p,".OBJ") == 0) + return true; + return false; +} + +void +process_pecoff(xed_uint8_t* start, + unsigned int length, + xed_disas_info_t& decode_info, + pecoff_reader_t& reader) +{ + xed_uint8_t* section_start = 0; + xed_uint32_t section_size = 0; + xed_uint64_t runtime_vaddr = 0; + + xed_bool_t okay = true; + xed_bool_t found = false; +#if defined(XED_USING_DEBUG_HELP) + int init_ok = dbg_help.init( decode_info.input_file_name, + decode_info.symbol_search_path); + if (init_ok == 0) { + if (CLIENT_VERBOSE0) { + if (dot_obj(decode_info.input_file_name)) + fprintf(stderr, + "WARNING: No COFF symbol support yet for OBJ files.\n"); + else + fprintf(stderr, + "WARNING: DBGHELP initialization failed. " + "Please copy the appropriate\n" + " (ia32,intel64) dbghelp.dll to the directory " + "where your xed.exe exists.\n" + " Version 6.9.3.113 or later is required.\n"); + fflush(stderr); + } + } +#endif + xed_disas_pecoff_init(); + + while(okay) { + okay = reader.module_section_info(decode_info.target_section, + section_start, + section_size, + runtime_vaddr); + if (okay) { + if (decode_info.xml_format == 0) + printf ("# SECTION %u\n", reader.section_index-1); + found = true; + + decode_info.s = XED_REINTERPRET_CAST(unsigned char*,start); + decode_info.a = + XED_REINTERPRET_CAST(unsigned char*,section_start); + decode_info.q = XED_REINTERPRET_CAST(unsigned char*, + section_start + section_size); + + decode_info.runtime_vaddr = runtime_vaddr + decode_info.fake_base; + decode_info.runtime_vaddr_disas_start = decode_info.addr_start; + decode_info.runtime_vaddr_disas_end = decode_info.addr_end; + +#if defined(XED_USING_DEBUG_HELP) + if (dbg_help.valid()) { + decode_info.line_number_info_fn = print_file_and_line; + + // This version is slow + //decode_info.symfn = windows_symbols_callback; + //decode_info.caller_symbol_data = &dbg_help; + + // This version is faster + decode_info.symfn = get_symbol; + decode_info.caller_symbol_data = &(dbg_help.sym_tab); + } +#endif + + xed_disas_test(&decode_info); + } + } + if (!found) + xedex_derror("text section not found"); +#if defined(XED_USING_DEBUG_HELP) + if (dbg_help.valid()) + dbg_help.cleanup(); +#endif + (void) length; +} + + + + +extern "C" void +xed_disas_pecoff(xed_disas_info_t* fi) +{ + xed_uint8_t* region = 0; + void* vregion = 0; + xed_uint32_t len = 0; + pecoff_reader_t image_reader(fi->xml_format==0); + xed_bool_t okay = image_reader.map_region(fi->input_file_name, + vregion, + len); + if (!okay) + xedex_derror("image read failed"); + if (CLIENT_VERBOSE1) + printf("Mapped image\n"); + image_reader.read_header(); + //image_reader.print_section_headers(); + + //image_reader.read_coff_symbols(); + region = XED_REINTERPRET_CAST(xed_uint8_t*,vregion); + + if (image_reader.sixty_four_bit() && + fi->sixty_four_bit == 0 && + fi->use_binary_mode) + { + /* modify the default dstate values because we were not expecting a + * 64b binary */ + fi->dstate.mmode = XED_MACHINE_MODE_LONG_64; + } + + process_pecoff(region, len, *fi, image_reader); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-pecoff.h b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-pecoff.h new file mode 100644 index 0000000..cb5673a --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-pecoff.h @@ -0,0 +1,30 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas-pecoff.h + + +#if !defined(XED_DISAS_PECOFF_H) +# define XED_DISAS_PECOFF_H + +# include "xed/xed-interface.h" +# include "xed-examples-util.h" + +void xed_disas_pecoff(xed_disas_info_t* fi); + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-raw.c b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-raw.c new file mode 100644 index 0000000..51a3f39 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-raw.c @@ -0,0 +1,45 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file disas-raw.c + +#include "xed/xed-interface.h" +#if defined(XED_DECODER) +#include "xed-examples-util.h" +#include "xed-disas-raw.h" + +void xed_disas_raw(xed_disas_info_t* fi) +{ + void* region = 0; + unsigned int len = 0; + xed_map_region(fi->input_file_name, ®ion, &len); + + fi->s = (unsigned char*)region; + fi->a = (unsigned char*)region; + fi->q = (unsigned char*)(region) + len; // end of region + fi->runtime_vaddr = fi->fake_base; + fi->runtime_vaddr_disas_start = 0; + fi->runtime_vaddr_disas_end = 0; + fi->symfn = 0; + fi->caller_symbol_data = 0; + fi->line_number_info_fn = 0; + xed_disas_test(fi); + if (fi->xml_format == 0) + xed_print_decode_stats(fi); +} + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-disas-raw.h b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-raw.h new file mode 100644 index 0000000..5af9af0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-disas-raw.h @@ -0,0 +1,28 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_DISAS_RAW_H) +# define XED_DISAS_RAW_H + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" + +void xed_disas_raw(xed_disas_info_t* fi); + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-dll-discovery.c b/CodeVirtualizer/build/obj/wkit/examples/xed-dll-discovery.c new file mode 100644 index 0000000..319f4c6 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-dll-discovery.c @@ -0,0 +1,121 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-min.cpp +/// @brief how to discover enum names for xed_iclass_enum_t + +/************************************************************************* + When using XED as a DLL or shared object, the enumerations can change + from one version of XED to another if instructions (or features) are + added. Each XED enumeration must be mapped to something your XED client + can use for indepedent compilation. This example shows how to discover + the XED values for the xed_iclass_enum_t and construct a mapping from + names that are constant to your tool to names that can vary. You would + need to this for each XED enumeration that your XED client uses. + + This builds a one map so that you can map things from your clients code + to XED's names as would be required for an encoder. For a decoder you'd + also need to invert the mapping so that you can mape from XED names to + your client's names. +**************************************************************************/ + +#include "xed/xed-interface.h" +#include +#include +#include +#include + +int main(int argc, char** argv); + + +typedef enum { /* these are the names that'll use in my code */ + MY_ICLASS_ADD, + MY_ICLASS_SUB, + MY_ICLASS_LAST +} my_iclass_enum_t; + +/* A mapping from my (simple) client names to the XED names which can + * vary. */ +typedef struct { + char const* const string_name; + int xed_name; /* discovered and passed to XED n*/ +} iclass_interface_t; + + +iclass_interface_t xed_iclass_interface[] = { + { "ADD", -1}, + { "SUB", -1} +}; + +void dump_inst(const xed_inst_t* p) { + /* N-squared maching... */ + xed_iclass_enum_t ic = xed_inst_iclass(p); + char const* const xed_name = xed_iclass_enum_t2str(ic); + iclass_interface_t* table_base = xed_iclass_interface; + int j=0; + + while( j < MY_ICLASS_LAST) { + if (strcmp(table_base[j].string_name, xed_name) == 0) { + if (table_base[j].xed_name == -1) { + printf("%s maps to %d\n", xed_name, (int)ic); + table_base[j].xed_name = ic; + } + break; + } + j++; + } +} + +void build_map_to_xed(void) { + int i; + for(i=0;i +#include +#include + +/* each write replaces the last node for that input */ + + +xed_dot_graph_supp_t* xed_dot_graph_supp_create( + xed_syntax_enum_t arg_syntax) +{ + xed_dot_graph_supp_t* gs = 0; + + gs = (xed_dot_graph_supp_t*)malloc(sizeof(xed_dot_graph_supp_t)); + assert( gs != 0 ); + gs->g = xed_dot_graph(); + gs->syntax = arg_syntax; + memset(gs->xed_reg_to_node, + 0, + sizeof(xed_dot_node_t*)*XED_REG_LAST); + + gs->start = xed_dot_node(gs->g, "start"); + return gs; +} + +void xed_dot_graph_supp_deallocate(xed_dot_graph_supp_t* gg) +{ + if (!gg) + return; + xed_dot_graph_deallocate(gg->g); +} + + +static xed_bool_t add_edge(xed_dot_graph_supp_t* gg, + xed_dot_node_t* n, + xed_reg_enum_t r, + xed_dot_edge_style_t s) +{ + xed_reg_enum_t r_enclosing; + xed_bool_t found = 0; + xed_dot_node_t* src = 0; + /* add edge to n */ + r_enclosing = xed_get_largest_enclosing_register(r); + src = gg->xed_reg_to_node[r_enclosing]; + if (src) { + xed_dot_edge(gg->g,src,n,s); + found = 1; + } + return found; +} + +static void add_read_operands(xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_dot_node_t* n) +{ + xed_uint_t i, noperands; + xed_reg_enum_t r; + const xed_inst_t* xi = 0; + xed_bool_t found = 0; + xi = xed_decoded_inst_inst(xedd); + noperands = xed_inst_noperands(xi); + + for( i=0; i < noperands ; i++) { + const unsigned int no_memop = 99; + unsigned int memop = no_memop; + const xed_operand_t* op = xed_inst_operand(xi,i); + xed_operand_enum_t opname = xed_operand_name(op); + if (xed_operand_is_register(opname) || + xed_operand_is_memory_addressing_register(opname)) { + + if (xed_operand_read(op)) { + /* add edge to n */ + r = xed_decoded_inst_get_reg(xedd, opname); + found |= add_edge(gg, n, r, XED_DOT_EDGE_SOLID); + } + continue; + } + if (opname == XED_OPERAND_MEM0) + memop = 0; + else if (opname == XED_OPERAND_MEM1 ) + memop = 1; + + if (memop != no_memop) { + /* get reads of base/index regs, if any */ + xed_reg_enum_t base, indx; + + base = xed_decoded_inst_get_base_reg(xedd,memop); + indx = xed_decoded_inst_get_index_reg(xedd,memop); + if (base != XED_REG_INVALID) + found |= add_edge(gg, n, base, XED_DOT_EDGE_SOLID); + + indx = xed_decoded_inst_get_index_reg(xedd,memop); + if (indx != XED_REG_INVALID) + found |= add_edge(gg, n, indx, XED_DOT_EDGE_SOLID); + } + } /* for */ + if (!found) { + /* add an edge from start */ + xed_dot_edge(gg->g, gg->start, n, XED_DOT_EDGE_SOLID); + } +} + +static void add_write_operands(xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_dot_node_t* n) +{ + xed_uint_t i, noperands; + xed_reg_enum_t r, r_enclosing; + const xed_inst_t* xi = 0; + xi = xed_decoded_inst_inst(xedd); + noperands = xed_inst_noperands(xi); + + for( i=0; i < noperands ; i++) { + const xed_operand_t* op = xed_inst_operand(xi,i); + xed_operand_enum_t opname = xed_operand_name(op); + if (xed_operand_is_register(opname) || + xed_operand_is_memory_addressing_register(opname)) { + + if (xed_operand_written(op)) { + /* set n as the source of the value. */ + /* ignoring partial writes */ + r = xed_decoded_inst_get_reg(xedd, opname); + + /* output dependences */ + (void) add_edge(gg,n,r,XED_DOT_EDGE_DASHED); + + r_enclosing = xed_get_largest_enclosing_register(r); + gg->xed_reg_to_node[r_enclosing] = n; + } + } + } /* for */ +} + + +#define XED_DOT_TMP_BUF_LEN (1024U) + +void xed_dot_graph_add_instruction( + xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instr_addr, + void* caller_data, + xed_disassembly_callback_fn_t disas_symbol_cb) +{ + /* + make a new node + + for each operand: + if read: + make edge from src node for that reg to the new node + for each operand: + if write: + install this node as the writer + + what about partial writes? + what about register nesting? + */ + char disasm_str[XED_DOT_TMP_BUF_LEN]; + char* p = 0; + size_t alen = 0; + int ok; + xed_bool_t ok2; + xed_dot_node_t* n = 0; + xed_uint32_t remaining_buffer_bytes = XED_DOT_TMP_BUF_LEN; + + // put addr on separate line in node label +#if defined(XED_WINDOWS) && !defined(PIN_CRT) + ok = sprintf_s(disasm_str, + XED_DOT_TMP_BUF_LEN, + XED_FMT_LX "\\n", + runtime_instr_addr); +#else + ok = sprintf(disasm_str, + XED_FMT_LX "\\n", + runtime_instr_addr); + +#endif + assert(ok > 0); + alen = strlen(disasm_str); + p = disasm_str + alen; + remaining_buffer_bytes -= XED_CAST(xed_uint32_t, alen); + + ok2 = xed_format_context(gg->syntax, + xedd, + p, + (int)remaining_buffer_bytes, + runtime_instr_addr, + caller_data, + disas_symbol_cb); + if (!ok2) { + (void)xed_strncpy(disasm_str,"???", XED_DOT_TMP_BUF_LEN); + } + + n = xed_dot_node(gg->g, disasm_str); + add_read_operands(gg,xedd,n); + add_write_operands(gg,xedd,n); +} + +void xed_dot_graph_dump( + FILE* f, + xed_dot_graph_supp_t* gg) +{ + xed_dot_dump(f, gg->g); +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-dot-prep.h b/CodeVirtualizer/build/obj/wkit/examples/xed-dot-prep.h new file mode 100644 index 0000000..8eb7dd9 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-dot-prep.h @@ -0,0 +1,51 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_DOT_PREP_H) +# define XED_DOT_PREP_H +#include "xed/xed-interface.h" +#include "xed-dot.h" + +typedef struct { + xed_syntax_enum_t syntax; + xed_dot_graph_t* g; + + // node that is last writer of the register + xed_dot_node_t* xed_reg_to_node[XED_REG_LAST]; + + xed_dot_node_t* start; +} xed_dot_graph_supp_t; + +xed_dot_graph_supp_t* xed_dot_graph_supp_create( + xed_syntax_enum_t arg_syntax); + +void xed_dot_graph_supp_deallocate( + xed_dot_graph_supp_t* gg); + +void xed_dot_graph_add_instruction( + xed_dot_graph_supp_t* gg, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instr_addr, + void* caller_data, + xed_disassembly_callback_fn_t disas_symbol_cb); + +void xed_dot_graph_dump( + FILE* f, + xed_dot_graph_supp_t* gg); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-dot.c b/CodeVirtualizer/build/obj/wkit/examples/xed-dot.c new file mode 100644 index 0000000..8bb2034 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-dot.c @@ -0,0 +1,118 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/* + take xed_decoded_inst_t* and add it to a graph. + The input operands are input edges. + The output operands are output edges. + Careful with "special" operands in new technologies + */ + +#include "xed-dot.h" +#include "xed-examples-util.h" +#include +#include + +xed_dot_graph_t* xed_dot_graph(void) { + xed_dot_graph_t* g = 0; + g = (xed_dot_graph_t*)malloc(sizeof(xed_dot_graph_t)); + assert(g != 0); + g->edges = 0; + g->nodes = 0; + return g; +} +static void delete_nodes(xed_dot_graph_t* g) { + xed_dot_node_t* p = g->nodes; + while(p) { + xed_dot_node_t* t = p; + p = p->next; + free(t); + } +} +static void delete_edges(xed_dot_graph_t* g) { + xed_dot_edge_t* p = g->edges; + while(p) { + xed_dot_edge_t* t = p; + p = p->next; + free(t); + } +} +void xed_dot_graph_deallocate(xed_dot_graph_t* g) +{ + delete_nodes(g); + delete_edges(g); + free(g); +} + +xed_dot_node_t* xed_dot_node(xed_dot_graph_t* g, + char const* const name) { + xed_dot_node_t* n = 0; + n = (xed_dot_node_t*)malloc(sizeof(xed_dot_node_t)); + assert(n != 0); + n->name = xed_strdup(name); + + n->next = g->nodes; + g->nodes = n; + return n; +} + + +void xed_dot_edge(xed_dot_graph_t* g, + xed_dot_node_t* src, + xed_dot_node_t* dst, + xed_dot_edge_style_t style) +{ + xed_dot_edge_t* e = 0; + e = (xed_dot_edge_t*)malloc(sizeof(xed_dot_edge_t)); + assert(e != 0); + e->src = src; + e->dst = dst; + e->style = style; + + e->next = g->edges; + g->edges = e; +} + + + +void xed_dot_dump(FILE* f, xed_dot_graph_t* g) { + xed_dot_edge_t* p = g->edges; + fprintf(f,"digraph {\n"); + while(p) { + fprintf(f, "\"%s\" -> \"%s\"", + p->src->name, + p->dst->name); + + switch(p->style) { + case XED_DOT_EDGE_SOLID: + break; /* nothing required */ + case XED_DOT_EDGE_DASHED: + fprintf(f, "[ style = dashed ]"); + break; + case XED_DOT_EDGE_DOTTED: + fprintf(f, "[ style = dotted ]"); + break; + default: + break; + } + + fprintf(f, ";\n"); + + p = p->next; + } + fprintf(f,"}\n"); +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-dot.h b/CodeVirtualizer/build/obj/wkit/examples/xed-dot.h new file mode 100644 index 0000000..9492b44 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-dot.h @@ -0,0 +1,61 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#if !defined(XED_DOT_H) +# define XED_DOT_H + +#include "xed/xed-interface.h" +#include + +typedef struct xed_dot_node_s { + char* name; + struct xed_dot_node_s* next; +} xed_dot_node_t; + +typedef enum { + XED_DOT_EDGE_SOLID, + XED_DOT_EDGE_DASHED, + XED_DOT_EDGE_DOTTED +} xed_dot_edge_style_t; + + +typedef struct xed_dot_edge_s { + xed_dot_node_t* src; + xed_dot_node_t* dst; + xed_dot_edge_style_t style; + struct xed_dot_edge_s* next; +} xed_dot_edge_t; + +typedef struct { + xed_dot_edge_t* edges; + xed_dot_node_t* nodes; +} xed_dot_graph_t; + + +xed_dot_graph_t* xed_dot_graph(void); +void xed_dot_graph_deallocate(xed_dot_graph_t* gg); + +xed_dot_node_t* xed_dot_node(xed_dot_graph_t* g, + char const* const name); + +void xed_dot_edge(xed_dot_graph_t* g, + xed_dot_node_t* src, + xed_dot_node_t* dst, + xed_dot_edge_style_t style); + +void xed_dot_dump(FILE* f, xed_dot_graph_t* g); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-enc-lang.c b/CodeVirtualizer/build/obj/wkit/examples/xed-enc-lang.c new file mode 100644 index 0000000..96729d6 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-enc-lang.c @@ -0,0 +1,645 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +// This is an example of how to use the encoder from scratch in the context +// of parsing a string from the command line. + +#include +#include +#include // strtol, ... +#include "xed/xed-interface.h" +#include "xed-examples-util.h" +#include "xed-enc-lang.h" + + +static void upcase(char* s) { + (void)xed_upcase_buf(s); +} + +xed_str_list_t* +tokenize(char const* const s, + char const* const delimiter) +{ + xed_str_list_t* slist = xed_tokenize(s, delimiter); + return slist; +} + +void slash_split(char const* const src, + char** first, // output + char** second) //output +{ + xed_str_list_t* sv = tokenize(src, "/"); + xed_str_list_t* p = sv; + xed_uint_t i=0; + for(; p ; i++, p=p->next) + { + if (i==0) { + *first = p->s; + *second = 0; + } + else if (i==1) + *second = p->s; + } +} + + + +typedef struct { + xed_bool_t valid; + unsigned int width_bits; + xed_uint64_t immed_val; +} immed_parser_t; + +static void immed_parser_init(immed_parser_t* self, + char const* const s, + char const* const tok0) +{ + xed_str_list_t* sv = tokenize(s,":"); + xed_uint_t sz = xed_str_list_size(sv); + self->valid = 0; + if (sz==2) { + xed_str_list_t* p = sv; + xed_uint_t i = 0; + for(; p ; i++, p=p->next) + { + if (i == 0 && strcmp(p->s,tok0) != 0) + return; + else if (i == 1) { + self->immed_val = convert_ascii_hex_to_int(p->s); + // nibbles to bits + self->width_bits = XED_CAST(unsigned int,strlen(p->s)*4); + self->valid = 1; + } + } + } +} + + +typedef struct { + xed_bool_t valid; + xed_reg_enum_t segment_reg; + xed_uint_t segno; +} seg_parser_t; + +static void seg_parser_init(seg_parser_t* self, + char const* const s) +{ + xed_str_list_t* sv = tokenize(s,":"); + xed_uint_t ntokens = xed_str_list_size(sv); + + self->valid=0; + self->segment_reg= XED_REG_INVALID; + self->segno=0; + + if (ntokens == 2) + { + xed_str_list_t* p = sv; + xed_uint_t i = 0; + xed_uint_t segid = 99; + for(; p ; i++, p=p->next) + { + if (i == 0) + { + if (strcmp(p->s,"SEG")==0 || strcmp(p->s,"SEG0")==0) + segid = 0; + else if (strcmp(p->s,"SEG1")==0) + segid = 1; + } + else if (i == 1 && segid < 2) + { + self->segno = segid; + self->segment_reg = str2xed_reg_enum_t(p->s); + + if (self->segment_reg != XED_REG_INVALID && + xed_reg_class(self->segment_reg) == XED_REG_CLASS_SR) + { + self->valid=1; + } + } + } + } + +} + + +static void +list2array(char** array, xed_str_list_t* sl, xed_uint_t n) +{ + xed_uint_t i=0; + xed_str_list_t* p = sl; + for( ; p && i < n ; i++, p=p->next) + array[i] = p->s; +} + +static xed_uint_t match(char const* const s, char const* const b) +{ + if (strcmp(s,b)==0) + return 1; + return 0; +} +static xed_uint_t skip(char const* const s) +{ + if (match(s,"-") || match(s,"NA")) + return 1; + return 0; +} + +typedef struct +{ + xed_bool_t valid; + xed_bool_t mem; + xed_bool_t agen; + xed_bool_t disp_valid; + char const* segment; + char const* base; + char const* indx; + char const* scale; + char const* disp; //displacement + xed_reg_enum_t segment_reg; + xed_reg_enum_t base_reg; + xed_reg_enum_t index_reg; + xed_uint8_t scale_val; + + xed_int64_t disp_val; + unsigned int disp_width_bits; + + xed_uint_t mem_len; +} mem_bis_parser_t; + // parse: MEMlength:[segment:]base,index,scale[,displacement] + // parse: AGEN:base,index,scale[,displacement] + // The displacement is optional + + // split on colons first + // MEM4:FS:EAX,EBX,4,223344 mem4 fs eax,ebx,4,22334455 -> 3 tokens + // MEM4:FS:EAX,EBX,4 mem4 fs eax,ebx,4 -> 3 tokens + // MEM4:EAX,EBX,4,223344 mem4 eax,ebx,4,223344.. -> 2 tokens + // MEM4:FS:EAX,EBX,4 mem4 fs eas,ebx,4 -> 3 tokens +static void mem_bis_parser_init(mem_bis_parser_t* self, char* s) +{ + xed_str_list_t* sv=0; + xed_uint_t ntokens=0; + xed_uint_t n_addr_tokens=0; + char* addr_token=0; + char* main_token=0; + xed_uint_t i=0; + xed_str_list_t* p = 0; + xed_str_list_t* sa = 0; + char* astr[4]; + + + self->valid = 0; + self->mem = 0; + self->agen = 0; + self->disp_valid = 0; + self->segment = "INVALID"; + self->base = "INVALID"; + self->indx = "INVALID"; + self->scale = "1"; + self->segment_reg = XED_REG_INVALID; + self->base_reg = XED_REG_INVALID; + self->index_reg = XED_REG_INVALID; + self->disp_val = 0; + self->disp_width_bits = 0; + self->mem_len = 0; + + upcase(s); + // split on colon first + sv = tokenize(s,":"); + ntokens = xed_str_list_size(sv); + + i=0; + p = sv; + if (ntokens !=2 && ntokens != 3) // 3 has segbase + return; + for( ; p ; i++, p=p->next) { + if (i==0) + main_token = p->s; + else if (i==1 && ntokens == 3) + self->segment = p->s; + else if (i==1 && ntokens == 2) + addr_token = p->s; + else if (i==2) + addr_token = p->s; + } + assert(main_token != 0); + if (strcmp(main_token,"AGEN")==0) + self->agen=1; + else if (strncmp(main_token,"MEM",3)==0) { + self->mem = 1; + } + else + return; + if (self->mem && strlen(main_token) > 3) { + char* mlen = main_token+3; + self->mem_len = XED_STATIC_CAST(xed_uint_t,strtol(mlen,0,0)); + } + + if (self->agen && strcmp(self->segment,"INVALID")!=0) + xedex_derror("AGENs cannot have segment overrides"); + + sa = tokenize(addr_token,","); + n_addr_tokens = xed_str_list_size(sa); + + if (n_addr_tokens == 0 || n_addr_tokens > 4) + xedex_derror("Bad addressing mode syntax for memop"); + + list2array(astr, sa, n_addr_tokens); + + if (!skip(astr[0])) + self->base = astr[0]; + + if (n_addr_tokens >= 2) + if (!skip(astr[1])) + self->indx = astr[1]; + + if (n_addr_tokens > 2) + self->scale = astr[2]; + if (skip(self->scale)) + self->scale = "1"; + if (match(self->scale,"1") || match(self->scale,"2") || + match(self->scale,"4") || match(self->scale,"8") ) { + self->valid=1; + self->scale_val = XED_CAST(xed_uint8_t,strtol(self->scale, 0, 10)); + self->segment_reg = str2xed_reg_enum_t(self->segment); + self->base_reg = str2xed_reg_enum_t(self->base); + self->index_reg = str2xed_reg_enum_t(self->indx); + + // look for a displacement + if (n_addr_tokens == 4 && strcmp(astr[3], "-") != 0) { + xed_uint64_t unsigned64_disp=0; + unsigned int nibbles = 0; + self->disp = astr[3]; + self->disp_valid = 1; + nibbles = xed_strlen(self->disp); + if (nibbles & 1) + xedex_derror("Displacement must have an even number of nibbles"); + unsigned64_disp = convert_ascii_hex_to_int(self->disp); + self->disp_width_bits = nibbles*4; // nibbles to bits + switch (self->disp_width_bits){ + case 8: self->disp_val = xed_sign_extend8_64((xed_int8_t)unsigned64_disp); + break; + case 16: self->disp_val = xed_sign_extend16_64((xed_int16_t)unsigned64_disp); + break; + case 32: self->disp_val = xed_sign_extend32_64((xed_int32_t)unsigned64_disp); + break; + case 64: self->disp_val = (xed_int64_t)unsigned64_disp; + break; + } + } + } +} + +static void find_vl(xed_reg_enum_t reg, xed_int_t* vl) +{ + // This will "grow" bad user settings. So if you try to specify /128 on + // the instruction and it sees a YMM or ZMM register operand, then + // it'll grow the VL to the right observed size. The right observed + // size might still be wrong, that is too small (as it can be for + // "shrinking" converts (PD2PS, PD2DQ, etc.). + xed_int_t nvl = *vl; + xed_reg_class_enum_t rc = xed_reg_class(reg); + if (rc == XED_REG_CLASS_XMM && nvl == -1) // not set and see xmm + *vl = 0; + else if (rc == XED_REG_CLASS_YMM && nvl < 1) // not set, set to xmm and then see ymm + *vl = 1; +#if defined(XED_SUPPORTS_AVX512) + else if (rc == XED_REG_CLASS_ZMM && nvl < 2) // not set, set to xmm or ymm and then see zmm + *vl = 2; +#endif +} + + +xed_encoder_request_t +parse_encode_request(ascii_encode_request_t areq) +{ + unsigned int i; + xed_encoder_request_t req; + char* cfirst=0; + char* csecond=0; + xed_str_list_t* tokens = 0; + unsigned int token_index = 0; + xed_str_list_t* p = 0; + xed_uint_t memop = 0; + xed_uint_t regnum = 0; + xed_uint_t operand_index = 0; + xed_iclass_enum_t iclass = XED_ICLASS_INVALID; + xed_int_t vl = -1; + xed_int_t uvl = -1; + + + + // this calls xed_encoder_request_zero() + xed_encoder_request_zero_set_mode(&req,&(areq.dstate)); + + /* This is the important function here. This encodes an instruction + from scratch. + + You must set: + the machine mode (machine width, addressing widths) + the iclass + for some instructions you need to specify prefixes (like REP or LOCK). + the operands: + + operand kind (XED_OPERAND_{AGEN,MEM0,MEM1,IMM0,IMM1, + RELBR,PTR,REG0...REG15} + + operand order + + xed_encoder_request_set_operand_order(&req,operand_index, + XED_OPERAND_*); + where the operand_index is a sequential index starting at zero. + + operand details + FOR MEMOPS: base,segment,index,scale, + displacement for memops, + FOR REGISTERS: register name + FOR IMMEDIATES: immediate values + */ + + tokens = tokenize(areq.command," "); + p = tokens; + + for ( ; p ; token_index++, p=p->next ) { + slash_split(p->s, &cfirst, &csecond); + assert(cfirst); + upcase(cfirst); + if (CLIENT_VERBOSE3) + printf( "[%s][%s][%s]\n", p->s, + (cfirst?cfirst:"NULL"), + (csecond?csecond:"NULL")); + + // consumed token, advance & exit + p = p->next; + break; + } + + // we can attempt to override the mode + if (csecond) + { + if (strcmp(csecond,"8")==0) + xed_encoder_request_set_effective_operand_width(&req, 8); + else if (strcmp(csecond,"16")==0) + xed_encoder_request_set_effective_operand_width(&req, 16); + else if (strcmp(csecond, "32")==0) + xed_encoder_request_set_effective_operand_width(&req, 32); + else if (strcmp(csecond,"64")==0) + xed_encoder_request_set_effective_operand_width(&req, 64); + + else if (strcmp(csecond,"128")==0) + uvl = 0; + else if (strcmp(csecond,"256")==0) + uvl = 1; + else if (strcmp(csecond,"512")==0) + uvl = 2; + } + + assert(cfirst != 0); + iclass = str2xed_iclass_enum_t(cfirst); + if (iclass == XED_ICLASS_INVALID) { + fprintf(stderr,"[XED CLIENT ERROR] Bad instruction name: %s\n", + cfirst); + exit(1); + } + xed_encoder_request_set_iclass(&req, iclass ); + + + // put the operands in the request. Loop through tokens + // (skip the opcode iclass, handled above) + for( i=token_index; p ; i++, operand_index++, p=p->next ) { + mem_bis_parser_t mem_bis; + seg_parser_t seg_parser; + immed_parser_t imm; + immed_parser_t simm; + immed_parser_t imm2; + immed_parser_t disp; + immed_parser_t ptr_disp; + xed_reg_enum_t reg = XED_REG_INVALID; + xed_operand_enum_t r; + + char* cres_reg=0; + char* csecond_x=0; //FIXME: not used + slash_split(p->s, &cres_reg, &csecond_x); + upcase(cres_reg); + // prune the AGEN or MEM(base,index,scale[,displacement]) text from + // cres_reg + + // FIXME: add MEM(immed) for the OC1_A and OC1_O types???? + mem_bis_parser_init(&mem_bis,cres_reg); + if (mem_bis.valid) { + xed_reg_class_enum_t rc = XED_REG_CLASS_INVALID; + xed_reg_class_enum_t rci = XED_REG_CLASS_INVALID; + + + if (mem_bis.mem) { + if (memop == 0) { + // Tell XED that we have a memory operand + xed_encoder_request_set_mem0(&req); + // Tell XED that the mem0 operand is the next operand: + xed_encoder_request_set_operand_order( + &req,operand_index, XED_OPERAND_MEM0); + } + else { + xed_encoder_request_set_mem1(&req); + // Tell XED that the mem1 operand is the next operand: + xed_encoder_request_set_operand_order( + &req,operand_index, XED_OPERAND_MEM1); + } + memop++; + } + else if (mem_bis.agen) { + // Tell XED we have an AGEN + xed_encoder_request_set_agen(&req); + // The AGEN is the next operand + xed_encoder_request_set_operand_order( + &req,operand_index, XED_OPERAND_AGEN); + } + else + assert(mem_bis.agen || mem_bis.mem); + + + rc = xed_gpr_reg_class(mem_bis.base_reg); + rci = xed_gpr_reg_class(mem_bis.index_reg); + if (mem_bis.base_reg == XED_REG_EIP) + xed_encoder_request_set_effective_address_size(&req, 32); + else if (rc == XED_REG_CLASS_GPR32 || rci == XED_REG_CLASS_GPR32) + xed_encoder_request_set_effective_address_size(&req, 32); + else if (rc == XED_REG_CLASS_GPR16 || rci == XED_REG_CLASS_GPR16) + xed_encoder_request_set_effective_address_size(&req, 16); + + // fill in the memory fields + xed_encoder_request_set_base0(&req, mem_bis.base_reg); + xed_encoder_request_set_index(&req, mem_bis.index_reg); + xed_encoder_request_set_scale(&req, mem_bis.scale_val); + xed_encoder_request_set_seg0(&req, mem_bis.segment_reg); + find_vl(mem_bis.index_reg, &vl); // for scatter/gather + if (mem_bis.mem_len) + xed_encoder_request_set_memory_operand_length( + &req, + mem_bis.mem_len ); // BYTES + if (mem_bis.disp_valid) + xed_encoder_request_set_memory_displacement( + &req, + mem_bis.disp_val, + mem_bis.disp_width_bits/8); + continue; + } + + + seg_parser_init(&seg_parser,cres_reg); + if (seg_parser.valid) { + if (CLIENT_VERBOSE3) + printf("Setting segment to %s\n", + xed_reg_enum_t2str(seg_parser.segment_reg)); + if (seg_parser.segno == 0) + xed_encoder_request_set_seg0(&req, seg_parser.segment_reg); + else + /* need SEG1 for MOVS[BWDQ]*/ + xed_encoder_request_set_seg1(&req, seg_parser.segment_reg); + + /* SEG/SEG0/SEG1 is NOT a normal operand. It is a setting, like + * the lock prefix. Normally the segment will be specified with + * normal memory operations. With memops without MODRM, or + * impliclit memops, we need a way of specifying the segment + * when it is not the default. This is the way. it does not + * change encoding forms. (When segments are "moved", they are + * REG operands, not SEG0/1, and are specified by name like EAX + * is.) */ + continue; + } + + + immed_parser_init(&imm,cres_reg, "IMM"); + + if (imm.valid) { + if (CLIENT_VERBOSE3) + printf("Setting immediate value to " XED_FMT_LX "\n", + imm.immed_val); + xed_encoder_request_set_uimm0_bits(&req, + imm.immed_val, + imm.width_bits); + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_IMM0); + continue; + } + immed_parser_init(&simm,cres_reg, "SIMM"); + if (simm.valid) { + if (CLIENT_VERBOSE3) + printf("Setting immediate value to " XED_FMT_LX "\n", + simm.immed_val); + xed_encoder_request_set_simm( + &req, + XED_STATIC_CAST(xed_int32_t,simm.immed_val), + simm.width_bits/8); //FIXME + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_IMM0); + continue; + } + + immed_parser_init(&imm2,cres_reg, "IMM2"); + if (imm2.valid) { + if (imm2.width_bits != 8) + xedex_derror("2nd immediate must be just 1 byte long"); + xed_encoder_request_set_uimm1(&req, (xed_uint8_t)imm2.immed_val); + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_IMM1); + continue; + } + + + immed_parser_init(&disp,cres_reg, "BRDISP"); + if (disp.valid) { + if (CLIENT_VERBOSE3) + printf("Setting displacement value to " XED_FMT_LX "\n", + disp.immed_val); + xed_encoder_request_set_branch_displacement( + &req, + XED_STATIC_CAST(xed_int32_t,disp.immed_val), + disp.width_bits/8); //FIXME + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_RELBR); + xed_encoder_request_set_relbr(&req); + continue; + } + + + immed_parser_init(&ptr_disp,cres_reg, "PTR"); + if (ptr_disp.valid) { + if (CLIENT_VERBOSE3) + printf("Setting pointer displacement value to " XED_FMT_LX "\n", + ptr_disp.immed_val); + xed_encoder_request_set_branch_displacement( + &req, + XED_STATIC_CAST(xed_int32_t,ptr_disp.immed_val), + ptr_disp.width_bits/8); //FIXME + xed_encoder_request_set_operand_order(&req, + operand_index, + XED_OPERAND_PTR); + xed_encoder_request_set_ptr(&req); + continue; + } + + reg = str2xed_reg_enum_t(cres_reg); + if (reg == XED_REG_INVALID) { + fprintf(stderr, + "[XED CLIENT ERROR] Bad register name: %s on operand %u\n", + cres_reg, i); + exit(1); + } + + if (areq.dstate.mmode != XED_MACHINE_MODE_LONG_64) + if (reg == XED_REG_DIL || reg == XED_REG_SPL || reg == XED_REG_BPL || reg == XED_REG_SIL) + { + fprintf(stderr, + "[XED CLIENT ERROR] Cannot use DIL/SPL/BPL/SIL outside of 64b mode\n"); + exit(1); + } + // The registers operands are numbered starting from the first one + // as XED_OPERAND_REG0. We increment regnum (below) every time we + // add a register operands. + r = XED_CAST(xed_operand_enum_t,XED_OPERAND_REG0 + regnum); + // store the register identifier in the operand storage field + xed_encoder_request_set_reg(&req, r, reg); + // store the operand storage field name in the encode-order array + xed_encoder_request_set_operand_order(&req, operand_index, r); + + find_vl(reg, &vl); + + regnum++; + } // for loop + + if (uvl == -1) + { + // no user VL setting, so use our observation-based guess. + if (vl>=0) + xed3_operand_set_vl(&req,(xed_uint_t)vl); + } + else + { + if (vl >= 0 && uvl < vl) + xedex_derror("User specified VL is smaller than largest observed register."); + // go with the user value. The encoder still might increase it + // based on observed values. But we test for that above so they'll + // get the feedback. + xed3_operand_set_vl(&req,(xed_uint_t)uvl); + } + return req; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-enc-lang.h b/CodeVirtualizer/build/obj/wkit/examples/xed-enc-lang.h new file mode 100644 index 0000000..ad55d7a --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-enc-lang.h @@ -0,0 +1,36 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-enc-lang.h + +#if !defined(XED_ENC_LANG_H) +# define XED_ENC_LANG_H + +#include "xed/xed-interface.h" + +typedef struct +{ + xed_state_t dstate; + char const* command; +} ascii_encode_request_t; + + +xed_encoder_request_t +parse_encode_request(ascii_encode_request_t areq); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-enc2-1.c b/CodeVirtualizer/build/obj/wkit/examples/xed-enc2-1.c new file mode 100644 index 0000000..416d59a --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-enc2-1.c @@ -0,0 +1,166 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed/xed-interface.h" +#include "xed/xed-enc2-m64-a64.h" +#include +#include + +static xed_uint32_t test_add_lock_byte(xed_uint8_t* output_buffer) +{ + xed_reg_enum_t reg0; + xed_reg_enum_t base; + xed_enc2_req_t request; + xed_enc2_req_t_init(&request, output_buffer); + reg0 = XED_REG_AH; + base = XED_REG_RBX; + xed_enc_add_lock_m8_r8_b_a64(&request,base,reg0); + return xed_enc2_encoded_length(&request); +} +static xed_uint32_t test_0_xed_enc_lea_rm_q_bisd32_a64(xed_uint8_t* output_buffer) +{ + xed_enc2_req_t* r; + xed_reg_enum_t reg0; + xed_reg_enum_t base; + xed_reg_enum_t index; + xed_uint_t scale; + xed_int32_t disp32; + xed_enc2_req_t request; + xed_enc2_req_t_init(&request, output_buffer); + r = &request; + reg0 = XED_REG_R11; + base = XED_REG_R12; + index = XED_REG_R13; + scale = 1; + disp32 = 0x11223344; + xed_enc_lea_r64_m_bisd32_a64(r /*req*/,reg0 /*gpr64*/,base /*gpr64*/,index /*gpr64*/,scale /*scale*/,disp32 /*int32*/); + return xed_enc2_encoded_length(r); +} + +xed_uint32_t test_0_xed_enc_vpblendvb_xxxx(xed_uint8_t* output_buffer) +{ + xed_enc2_req_t* r; + xed_reg_enum_t reg0; + xed_reg_enum_t reg1; + xed_reg_enum_t reg2; + xed_reg_enum_t reg3; + xed_enc2_req_t request; + xed_enc2_req_t_init(&request, output_buffer); + r = &request; + reg0 = XED_REG_XMM6; + reg1 = XED_REG_XMM7; + reg2 = XED_REG_XMM8; + reg3 = XED_REG_XMM9; + xed_enc_vpblendvb_x_x_x_x_128(r /*req*/,reg0 /*xmm*/,reg1 /*xmm*/,reg2 /*xmm*/,reg3 /*xmm*/); + return xed_enc2_encoded_length(r); +} + +// The decoder drags in a lot of stuff to the final executable. +#define DECO + +#if defined(DECO) +static void disassemble(xed_decoded_inst_t* xedd) +{ + xed_bool_t ok; + xed_print_info_t pi; +#define XBUFLEN 200 + char buf[XBUFLEN]; + + xed_init_print_info(&pi); + pi.p = xedd; + pi.blen = XBUFLEN; + pi.buf = buf; + pi.buf[0]=0; //allow use of strcat + + ok = xed_format_generic(&pi); + if (ok) + printf("Disassembly: %s\n", buf); + else + printf("Disassembly: %%ERROR%%\n"); +} + +static int decode(xed_uint8_t* buf, xed_uint32_t len) { + xed_decoded_inst_t xedd; + xed_error_enum_t err; + xed_state_t dstate; + static int first = 1; + if (first) { + xed_tables_init(); + first = 0; + } + xed_state_zero(&dstate); + dstate.mmode=XED_MACHINE_MODE_LONG_64; + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + err = xed_decode(&xedd, buf, len); + if (err == XED_ERROR_NONE) { + disassemble(&xedd); + return 0; + } + printf("ERROR: %s\n", xed_error_enum_t2str(err)); + return 1; +} +#endif + +static void dump(xed_uint8_t* buf, xed_uint32_t len) { + xed_uint_t i; + for(i=0;i +#include +#include + +static xed_uint32_t test_0_xed_enc_lea_rm_q_bisd32_a64(xed_uint8_t* output_buffer) +{ + xed_reg_enum_t dest; + xed_reg_enum_t base; + xed_reg_enum_t index; + xed_uint_t scale; + xed_int32_t disp32; + xed_enc2_req_t request; + xed_enc2_req_t_init(&request, output_buffer); + dest = XED_REG_XMM5; // INTENTIONAL ERROR FOR EXAMPLE. THIS SHOULD BE A GPR LIKE R11 + base = XED_REG_R12; + index = XED_REG_R13; + scale = 1; + disp32 = 0x11223344; + xed_enc_lea_r64_m_bisd32_a64_chk(&request /*req*/,dest /*gpr64*/,base /*gpr64*/,index /*gpr64*/,scale /*scale*/,disp32 /*int32*/); + return xed_enc2_encoded_length(&request); +} + + + +// The decoder drags in a lot of stuff to the final executable. +#define DECO + +#if defined(DECO) +static void disassemble(xed_decoded_inst_t* xedd) +{ + xed_bool_t ok; + xed_print_info_t pi; +#define XBUFLEN 200 + char buf[XBUFLEN]; + + xed_init_print_info(&pi); + pi.p = xedd; + pi.blen = XBUFLEN; + pi.buf = buf; + pi.buf[0]=0; //allow use of strcat + + ok = xed_format_generic(&pi); + if (ok) + printf("Disassembly: %s\n", buf); + else + printf("Disassembly: %%ERROR%%\n"); +} + +static int decode(xed_uint8_t* buf, xed_uint32_t len) { + xed_decoded_inst_t xedd; + xed_error_enum_t err; + xed_state_t dstate; + static int first = 1; + if (first) { + xed_tables_init(); + first = 0; + } + xed_state_zero(&dstate); + dstate.mmode=XED_MACHINE_MODE_LONG_64; + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + err = xed_decode(&xedd, buf, len); + if (err == XED_ERROR_NONE) { + disassemble(&xedd); + return 0; + } + printf("ERROR: %s\n", xed_error_enum_t2str(err)); + return 1; +} +#endif + +static void dump(xed_uint8_t* buf, xed_uint32_t len) { + xed_uint_t i; + for(i=0;i +#include + +static xed_uint32_t test_push_reg(xed_uint8_t* output_buffer, + xed_reg_enum_t reg) +{ + xed_enc2_req_t request; + xed_enc2_req_t_init(&request, output_buffer); + xed_enc_push_r64(&request,reg); + return xed_enc2_encoded_length(&request); +} +static xed_uint32_t test_push_reg_short(xed_uint8_t* output_buffer, + xed_reg_enum_t reg) +{ + xed_enc2_req_t request; + xed_enc2_req_t_init(&request, output_buffer); + xed_enc_push_r64_vr1(&request,reg); + return xed_enc2_encoded_length(&request); +} + +static void disassemble(xed_decoded_inst_t* xedd) +{ + xed_bool_t ok; + xed_print_info_t pi; +#define XBUFLEN 200 + char buf[XBUFLEN]; + + xed_init_print_info(&pi); + pi.p = xedd; + pi.blen = XBUFLEN; + pi.buf = buf; + pi.buf[0]=0; //allow use of strcat + + ok = xed_format_generic(&pi); + if (ok) + printf("Disassembly: %s\n", buf); + else + printf("Disassembly: %%ERROR%%\n"); +} + +static int decode(xed_uint8_t* buf, xed_uint32_t len) { + xed_decoded_inst_t xedd; + xed_error_enum_t err; + xed_state_t dstate; + static int first = 1; + if (first) { + xed_tables_init(); + first = 0; + } + xed_state_zero(&dstate); + dstate.mmode=XED_MACHINE_MODE_LONG_64; + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + err = xed_decode(&xedd, buf, len); + if (err == XED_ERROR_NONE) { + disassemble(&xedd); + return 0; + } + printf("ERROR: %s\n", xed_error_enum_t2str(err)); + return 1; +} + +static void dump(xed_uint8_t* buf, xed_uint32_t len) { + xed_uint_t i; + for(i=0;i +#include +#include //strcmp +#include + +int main(int argc, char** argv); + + +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ +/* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ + +xed_uint64_t register_callback(xed_reg_enum_t reg, void* context, xed_bool_t* error) { + (void) context; // pacify compiler + (void) error; + + /* After we register this function (see xed_agen_register_callback in + * main()), this function is called as needed by xed_agen(). This + * function provides register values for xed_agen(). In a real usage, + * you would probably pass in a context (in your call to xed_agen()) + * that contains the actual values. */ + + + /* Note that AL is required for the XLAT instruction. That is the only + byte reg needed. Also note, that for real mode, raw segement + selectors are returned by this function. */ + + /* in reality, you'd have to return valid values for each case */ + + /* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ + + switch(reg) { + case XED_REG_RAX: + case XED_REG_EAX: + case XED_REG_AX: + return 0xAABBCC00; + break; + case XED_REG_AL: // FOR XLAT + break; + + case XED_REG_RCX: + case XED_REG_ECX: + case XED_REG_CX: + return 0xAABBCCDD; + break; + case XED_REG_RDX: + case XED_REG_EDX: + case XED_REG_DX: + break; + case XED_REG_RBX: + case XED_REG_EBX: + case XED_REG_BX: + return 0x11223344; + break; + case XED_REG_RSP: + case XED_REG_ESP: + case XED_REG_SP: + break; + case XED_REG_RBP: + case XED_REG_EBP: + case XED_REG_BP: + break; + case XED_REG_RSI: + case XED_REG_ESI: + case XED_REG_SI: + return 0x1122334455; + break; + case XED_REG_RDI: + case XED_REG_EDI: + case XED_REG_DI: + return 0x6655443322; + break; + case XED_REG_R8: + case XED_REG_R8D: + case XED_REG_R8W: + break; + case XED_REG_R9: + case XED_REG_R9D: + case XED_REG_R9W: + break; + case XED_REG_R10: + case XED_REG_R10D: + case XED_REG_R10W: + break; + case XED_REG_R11: + case XED_REG_R11D: + case XED_REG_R11W: + break; + case XED_REG_R12: + case XED_REG_R12D: + case XED_REG_R12W: + break; + case XED_REG_R13: + case XED_REG_R13D: + case XED_REG_R13W: + break; + case XED_REG_R14: + case XED_REG_R14D: + case XED_REG_R14W: + break; + case XED_REG_R15: + case XED_REG_R15D: + case XED_REG_R15W: + break; + case XED_REG_RIP: + return 0x7990100020003000ULL; + + case XED_REG_EIP: + case XED_REG_IP: + break; + case XED_REG_CS: + case XED_REG_DS: + case XED_REG_ES: + case XED_REG_SS: + case XED_REG_FS: + case XED_REG_GS: + break; + default: + assert(0); + } + return 0; +} + +xed_uint64_t segment_callback(xed_reg_enum_t reg, void* context, xed_bool_t* error) { + /* for protected mode, this function returns the valid segment base values */ + + /* in reality, you'd have to return valid valies for each case */ + /* THIS IS JUST AN EXAMPLE FOR TESTING AND DOES NOT RETURN REAL DATA */ + + (void) context; // pacify compiler + (void) error; + + switch(reg) { + case XED_REG_CS: + case XED_REG_DS: + case XED_REG_ES: + case XED_REG_SS: + return 0; + case XED_REG_FS: + return 0; + break; + case XED_REG_GS: + return 0; + break; + default: + assert(0); + break; + } + return 0; +} + + + + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + + xed_bool_t long_mode = 0; + xed_bool_t real_mode = 0; + xed_bool_t protected_16 = 0; + xed_state_t dstate; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int i; + unsigned int argcu = (unsigned int)argc; + unsigned int u; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + unsigned int isyntax; + xed_syntax_enum_t syntax; + unsigned int memop_index = 0; + unsigned int memops = 0; + xed_uint64_t out_addr = 0; + + xed_tables_init(); + + // register callbacks that provide actual values. These functions will + // be called by xed_agen() later on when values are needed. + xed_agen_register_callback( register_callback, segment_callback); + + xed_state_zero(&dstate); + //xed_set_verbosity( 99 ); + + if (argcu > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + if (argcu > 2 && strcmp(argv[1], "-r") == 0) + real_mode = 1; + if (argcu > 2 && strcmp(argv[1], "-16") == 0) + protected_16 = 1; + + if (long_mode) { + first_argv = 2; + dstate.mmode=XED_MACHINE_MODE_LONG_64; + } + else if (protected_16) { + first_argv = 2; + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_16, + XED_ADDRESS_WIDTH_16b, + XED_ADDRESS_WIDTH_16b); + } + else if (real_mode) { + first_argv = 2; + /* we say that real mode uses 16b addressing even though the + addresses returned are 20b long. */ + xed_state_init(&dstate, + XED_MACHINE_MODE_REAL_16, + XED_ADDRESS_WIDTH_16b, + XED_ADDRESS_WIDTH_16b); + } + else { + first_argv=1; + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_32, + XED_ADDRESS_WIDTH_32b, + XED_ADDRESS_WIDTH_32b); + } + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + for( i=first_argv ;i < argcu; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error = XED_ERROR_NONE; + unsigned int first_argv = 1; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t i=1; + xed_uint_t u=0; + xed_decoded_inst_t xedd; + xed_machine_mode_enum_t mmode=XED_MACHINE_MODE_LEGACY_32; + xed_address_width_enum_t stack_addr_width=XED_ADDRESS_WIDTH_32b; + xed_chip_features_t features; + xed_chip_enum_t chip = XED_CHIP_HASWELL; + xed_uint_t uargc = (xed_uint_t)argc; + xed_bool_t already_set_mode = 0; + xed_bool_t bmi = 1; + + xed_tables_init(); + + for( i=1 ; i < uargc ; i++ ) + { + if (strcmp(argv[i], "-64") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + first_argv++; + } + else if (strcmp(argv[i], "-16") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + + else if (strcmp(argv[i], "-chip") == 0) { + assert(i+1 < uargc); + chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(chip)); + assert(chip != XED_CHIP_INVALID); + first_argv+=2; + i++; + } + else if (strcmp(argv[i], "-nobmi") == 0) { + bmi = 0; + first_argv++; + i++; + } + else { // if not one of the thigns we're working on, break + break; + } + + } + + for( i=first_argv ;i < uargc; i++) { + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0 ; u < bytes ; u++ ) { + printf("%02x ", XED_STATIC_CAST(unsigned int,itext[u])); + } + printf("\n"); + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + xed_decoded_inst_set_input_chip(&xedd, chip); + + // Start with a HSW (default) and (conditionally) turn off BMI1 so that + // TZCNT decodes as BSF + xed_get_chip_features(&features, chip); + if (bmi == 0) { + xed_modify_chip_features(&features, XED_ISA_SET_BMI1, 0); + } + + xed_error = xed_decode_with_features(&xedd, + XED_REINTERPRET_CAST(const xed_uint8_t*,itext), + bytes, + &features); + switch(xed_error) + { + case XED_ERROR_NONE: { +#define OBUFLEN 1024 + char outbuf[OBUFLEN]; + if (xed_format_context(XED_SYNTAX_INTEL, &xedd, outbuf, OBUFLEN, 0, 0, 0)) { + printf("DISASM %s\n", outbuf); + } + else { + fprintf(stderr,"DISASM printing error\n"); + exit(1); + } + + } + break; + case XED_ERROR_BUFFER_TOO_SHORT: + fprintf(stderr,"Not enough bytes provided\n"); + exit(1); + case XED_ERROR_GENERAL_ERROR: + fprintf(stderr,"Could not decode given input.\n"); + exit(1); + default: + fprintf(stderr,"Unhandled error code %s\n", + xed_error_enum_t2str(xed_error)); + exit(1); + } + + return 0; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-ex-ild.c b/CodeVirtualizer/build/obj/wkit/examples/xed-ex-ild.c new file mode 100644 index 0000000..77bc31c --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-ex-ild.c @@ -0,0 +1,47 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#include "xed/xed-interface.h" +#include + +int main(int argc, char** argv); + +int main(int argc, char** argv) +{ + xed_bool_t long_mode = 1; + xed_decoded_inst_t xedd; + xed_state_t dstate; + unsigned char itext[15] = { 0xf2, 0x2e, 0x4f, 0x0F, 0x85, 0x99, + 0x00, 0x00, 0x00 }; + + xed_tables_init(); // one time per process + + if (long_mode) + dstate.mmode=XED_MACHINE_MODE_LONG_64; + else + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + xed_ild_decode(&xedd, itext, XED_MAX_INSTRUCTION_BYTES); + printf("length = %u\n",xed_decoded_inst_get_length(&xedd)); + + return 0; + (void) argc; (void) argv; //pacify compiler + +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-ex-ild2.c b/CodeVirtualizer/build/obj/wkit/examples/xed-ex-ild2.c new file mode 100644 index 0000000..25a1025 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-ex-ild2.c @@ -0,0 +1,168 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#include +#include +#include +#include +#include "xed-examples-util.h" + +int main(int argc, char** argv); + +#include "xed/xed-interface.h" + +#define BUFLEN 1024 +#define XDPRINT(x) printf("%23s = %d\n", #x , i-> x ); +#define XXPRINT(x) printf("%23s = 0x%x\n", #x ,i-> x ) +void print_ild(xed_decoded_inst_t* p) { + + char buf[BUFLEN]; + xed_chip_enum_t chip = xed_decoded_inst_get_input_chip(p); + xed_decoded_inst_dump(p, buf, BUFLEN); + printf("%23s = %s\n", "chip", + xed_chip_enum_t2str(chip)); +} + +#define MAX_INPUT_NIBBLES (XED_MAX_INSTRUCTION_BYTES*2) + +int main(int argc, char** argv) { + xed_decoded_inst_t ild; + xed_uint_t uargc = (xed_uint_t)argc; + xed_uint_t length = 0; + xed_uint_t dlen = 0; + xed_uint_t i,j,input_nibbles=0; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES]; + char src[MAX_INPUT_NIBBLES+1]; + xed_state_t dstate; + xed_decoded_inst_t xedd; + xed_uint_t first_argv; + xed_uint_t bytes; + xed_error_enum_t xed_error; + xed_chip_enum_t chip = XED_CHIP_INVALID; + int already_set_mode = 0; + + // initialize the XED tables -- one time. + xed_tables_init(); + + xed_state_zero(&dstate); + + first_argv = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_32b; + + for(i=1;i< uargc;i++) { + if (strcmp(argv[i], "-64") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LONG_64; + first_argv++; + } + else if (strcmp(argv[i], "-16") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_16; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-s16") == 0) { + already_set_mode = 1; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-chip") == 0) { + assert(i+1 < uargc); + chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(chip)); + assert(chip != XED_CHIP_INVALID); + first_argv+=2; + } + + } + + assert(first_argv < uargc); + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + + if (first_argv >= uargc) { + printf("Need some hex instruction nibbles"); + exit(1); + } + + for(i=first_argv;i +#include +#include +#include + +int main(int argc, char** argv); +void print_misc(xed_decoded_inst_t* xedd) { + xed_uint_t i=0; + const xed_operand_values_t* ov = xed_decoded_inst_operands_const(xedd); + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + xed_exception_enum_t e = xed_inst_exception(xi); + xed_uint_t np = xed_decoded_inst_get_nprefixes(xedd); + + xed_isa_set_enum_t isaset = xed_decoded_inst_get_isa_set(xedd); + + if (xed_operand_values_has_real_rep(ov)) { + xed_iclass_enum_t norep = + xed_rep_remove(xed_decoded_inst_get_iclass(xedd)); + printf("REAL REP "); + printf("\tcorresponding no-rep iclass: %s\n" , + xed_iclass_enum_t2str(norep)); + + } + if (xed_operand_values_has_rep_prefix(ov)) { + printf("F3 PREFIX\n"); + } + if (xed_operand_values_has_repne_prefix(ov)) { + printf("F2 PREFIX\n"); + } + if (xed_operand_values_has_address_size_prefix(ov)) { + printf("67 PREFIX\n"); + } + if (xed_operand_values_has_operand_size_prefix(ov)) { + /* this 66 prefix is not part of the opcode */ + printf("66-OSZ PREFIX\n"); + } + if (xed_operand_values_has_66_prefix(ov)) { + /* this is any 66 prefix including the above */ + printf("ANY 66 PREFIX\n"); + } + + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_RING0)) { + printf("RING0 only\n"); + } + + if (e != XED_EXCEPTION_INVALID) { + printf("EXCEPTION TYPE: %s\n", xed_exception_enum_t2str(e)); + } + if (xed_decoded_inst_is_broadcast(xedd)) + printf("BROADCAST\n"); + + if ( xed_classify_sse(xedd) || xed_classify_avx(xedd) || xed_classify_avx512(xedd) ) + { + if (xed_classify_avx512_maskop(xedd)) + printf("AVX512 KMASK-OP\n"); + else { + xed_bool_t sse = 0; + if (xed_classify_sse(xedd)) { + sse = 1; + printf("SSE\n"); + } + else if (xed_classify_avx(xedd)) + printf("AVX\n"); + else if (xed_classify_avx512(xedd)) + printf("AVX512\n"); + + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_SIMD_SCALAR)) + printf("SCALAR\n"); + else { + // xed_decoded_inst_vector_length_bits is only for VEX/EVEX instr. + // This will print 128 vl for FXSAVE and LD/ST MXCSR which is unfortunate. + xed_uint_t vl_bits = sse ? 128 : xed_decoded_inst_vector_length_bits(xedd); + printf("Vector length: %u\n", vl_bits); + } + + if (xed_classify_avx512(xedd)) { + xed_uint_t vec_elements = xed_decoded_inst_avx512_dest_elements(xedd); + printf( "AVX512 vector elements: %u\n", vec_elements); + } + } + } + + // does not include instructions that have XED_ATTRIBUTE_MASK_AS_CONTROL. + // does not include vetor instructions that have k0 as a mask register. + if (xed_decoded_inst_masked_vector_operation(xedd)) + printf("WRITE-MASKING\n"); + + if (np) + printf("Number of legacy prefixes: %u \n", np); + + printf("ISA SET: [%s]\n", xed_isa_set_enum_t2str(isaset)); + for(i=0; i0 && t<5) + printf("rounding mode override = %s\n", rounding_modes[t]); + } + +} + +void print_branch_hints(xed_decoded_inst_t* xedd) { + if (xed_operand_values_branch_not_taken_hint(xedd)) + printf("HINT: NOT TAKEN\n"); + else if (xed_operand_values_branch_taken_hint(xedd)) + printf("HINT: TAKEN\n"); + else if (xed_operand_values_cet_no_track(xedd)) + printf("CET NO-TRACK\n"); +} + +void print_attributes(xed_decoded_inst_t* xedd) { + /* Walk the attributes. Generally, you'll know the one you want to + * query and just access that one directly. */ + + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + + unsigned int i, nattributes = xed_attribute_max(); + + printf("ATTRIBUTES: "); + for(i=0;is.zf) { + printf("READS ZF\n"); + } + } +} + +void print_flags(xed_decoded_inst_t* xedd) { + unsigned int i, nflags; + if (xed_decoded_inst_uses_rflags(xedd)) { + const xed_simple_flag_t* rfi = xed_decoded_inst_get_rflags_info(xedd); + assert(rfi); + printf("FLAGS:\n"); + if (xed_simple_flag_reads_flags(rfi)) { + printf(" reads-rflags "); + } + else if (xed_simple_flag_writes_flags(rfi)) { + //XED provides may-write and must-write information + if (xed_simple_flag_get_may_write(rfi)) { + printf(" may-write-rflags "); + } + if (xed_simple_flag_get_must_write(rfi)) { + printf(" must-write-rflags "); + } + } + nflags = xed_simple_flag_get_nflags(rfi); + for( i=0;i> 3); + + printf(" %2u", xed_decoded_inst_operand_elements(xedd,i)); + printf(" %3u", xed_decoded_inst_operand_element_size_bits(xedd,i)); + + printf(" %10s", + xed_operand_element_type_enum_t2str( + xed_decoded_inst_operand_element_type(xedd,i))); + printf(" %10s\n", + xed_reg_class_enum_t2str( + xed_reg_class( + xed_decoded_inst_get_reg(xedd, op_name)))); + } +} + +int main(int argc, char** argv) { + xed_state_t dstate; + xed_decoded_inst_t xedd; + xed_uint_t i, bytes = 0; + xed_uint_t argcu = (xed_uint_t)argc; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t first_argv; + xed_bool_t already_set_mode = 0; + xed_chip_enum_t chip = XED_CHIP_INVALID; + char const* decode_text=0; + unsigned int len; + xed_error_enum_t xed_error; + +#if defined(XED_MPX) + unsigned int mpx_mode=0; +#endif +#if defined(XED_CET) + unsigned int cet_mode=0; +#endif + xed_tables_init(); + xed_state_zero(&dstate); + + first_argv = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_32; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_32b; + + for(i=1;i< argcu;i++) { + if (strcmp(argv[i], "-64") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LONG_64; + first_argv++; + } +#if defined(XED_MPX) + else if (strcmp(argv[i], "-mpx") == 0) { + mpx_mode = 1; + first_argv++; + } +#endif +#if defined(XED_CET) + else if (strcmp(argv[i], "-cet") == 0) { + cet_mode = 1; + first_argv++; + } +#endif + else if (strcmp(argv[i], "-16") == 0) { + assert(already_set_mode == 0); + already_set_mode = 1; + dstate.mmode=XED_MACHINE_MODE_LEGACY_16; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-s16") == 0) { + already_set_mode = 1; + dstate.stack_addr_width=XED_ADDRESS_WIDTH_16b; + first_argv++; + } + else if (strcmp(argv[i], "-chip") == 0) { + assert(i+1 < argcu); + chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(chip)); + assert(chip != XED_CHIP_INVALID); + first_argv+=2; + } + } + + assert(first_argv < argcu); + + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + xed_decoded_inst_set_input_chip(&xedd, chip); +#if defined(XED_MPX) + xed3_operand_set_mpxmode(&xedd, mpx_mode); +#endif +#if defined(XED_CET) + xed3_operand_set_cet(&xedd, cet_mode); +#endif + + // convert ascii hex to hex bytes + for(i=first_argv; i< argcu;i++) + decode_text = xedex_append_string(decode_text,argv[i]); + + len = (unsigned int) strlen(decode_text); + if ((len & 1) == 1) { + printf("Must supply even number of nibbles per substring\n"); + exit(1); + } + if (len > XED_MAX_INSTRUCTION_BYTES*2) { + printf("Must supply at most 30 nibbles (15 bytes)\n"); + exit(1); + } + + bytes = xed_convert_ascii_to_hex(decode_text, + itext, + XED_MAX_INSTRUCTION_BYTES); + if (bytes == 0) { + printf("Must supply some hex bytes\n"); + exit(1); + } + + printf("Attempting to decode: "); + for(i=0;i +#include +#include + +int main(int argc, char** argv); + + +void +usage(char* progname) +{ + fprintf(stderr,"Usage: %s [-16|-32|-64] [-s16|-s32] encode-string\n", + progname); + exit(1); +} + +ascii_encode_request_t +parse_args(int argc, char** argv) +{ + char const* c = 0; + unsigned int i = 1; + unsigned int argcu = (unsigned int)argc; + ascii_encode_request_t r; + if (argcu == 1) + usage(argv[0]); + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + r.dstate.stack_addr_width = XED_ADDRESS_WIDTH_32b; + + for( ; i< argcu; i++) + if (strcmp(argv[i],"-16")==0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_16; + else if (strcmp(argv[i],"-32")==0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + else if (strcmp("-64", argv[i]) == 0) { + r.dstate.mmode = XED_MACHINE_MODE_LONG_64; + } + else if (strcmp("-32", argv[i]) == 0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + else if (strcmp("-16", argv[i]) == 0) + r.dstate.mmode = XED_MACHINE_MODE_LEGACY_16; + else if (strcmp(argv[i],"-s32")==0) + r.dstate.stack_addr_width = XED_ADDRESS_WIDTH_32b; + else if (strcmp(argv[i],"-s16")==0) + r.dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + else + break; + + if (i == argcu) + usage(argv[0]); + + c = xed_strdup(argv[i++]); + for( ;i +#include +#include //strcmp, memset +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + + xed_bool_t long_mode = 0; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + int i; + unsigned int u; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + unsigned int isyntax; + xed_syntax_enum_t syntax; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + xed_format_options_t format_options; + + // one time initialization + xed_tables_init(); + xed_set_verbosity( 99 ); + memset(&format_options,0, sizeof(format_options)); + format_options.hex_address_before_symbolic_name=0; + format_options.xml_a=0; + format_options.omit_unit_scale=0; + format_options.no_sign_extend_signed_immediates=0; + + for(i=1;i +#include // malloc, etc. +#include //strcmp +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + xed_state_t dstate32, dstate64; + xed_uint8_t itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int ilen = XED_MAX_INSTRUCTION_BYTES; + unsigned int i, j, olen = 0, ninst=0; + xed_encoder_request_t enc_req; +#define NINST 50 + xed_encoder_instruction_t x[NINST]; + xed_bool_t convert_ok; +#if defined(XED_DECODER) + xed_bool_t ok; +# define DBUFLEN 1000 + char buffer[DBUFLEN]; + + xed_decoded_inst_t xedd; +#endif + + xed_tables_init(); + xed_state_zero(&dstate32); + xed_state_zero(&dstate64); + + dstate32.stack_addr_width=XED_ADDRESS_WIDTH_32b; + dstate32.mmode=XED_MACHINE_MODE_LEGACY_32; + + dstate64.stack_addr_width=XED_ADDRESS_WIDTH_64b; + dstate64.mmode=XED_MACHINE_MODE_LONG_64; + + xed_inst1(x+ninst, dstate64, XED_ICLASS_JMP, 64, + xed_relbr(0x11223344, 32)); + ninst++; + + /* using 0 for instructions that have the default effective operand + * width for their mode. The default effective operand width for 16b + * mode is 16b. The default effective operand width for 32b and 64b + * modes is 32b. */ + + // add an lock and xacquire + xed_inst2(x+ninst, dstate32, XED_ICLASS_XOR_LOCK, 0, + xed_mem_bd(XED_REG_EDX, xed_disp(0x11, 8), 32), + xed_reg(XED_REG_ECX) ); + xed_repne(x+ninst); // xacquire + ninst++; + + xed_inst2(x+ninst, + dstate32, XED_ICLASS_ADD, 0, + xed_reg(XED_REG_EAX), + xed_mem_bd(XED_REG_EDX, xed_disp(0x11223344, 32), 32)); + ninst++; + + xed_inst2(x+ninst, + dstate32, XED_ICLASS_ADD, 0, + xed_reg(XED_REG_EAX), + xed_mem_gbisd(XED_REG_FS, + XED_REG_EAX, + XED_REG_ESI,4, xed_disp(0x11223344, 32), 32)); + ninst++; + + // displacment-only LEA + xed_inst2(x+ninst, + dstate32, XED_ICLASS_LEA, 32, + xed_reg(XED_REG_EAX), + xed_mem_bd(XED_REG_INVALID, xed_disp(0x11223344, 32), 32)); + ninst++; + + + xed_inst0(x+ninst, dstate32, XED_ICLASS_REPE_CMPSB, 0); + ninst++; + + /* nondefault effective operand width for 32b mode so we must specify + it. XED could figure it out from the opcode, but currently does + not. */ + xed_inst0(x+ninst, dstate32, XED_ICLASS_REPE_CMPSW, 16); + ninst++; + + xed_inst0(x+ninst, dstate32, XED_ICLASS_REPE_CMPSD, 0); + ninst++; + + xed_inst1(x+ninst, dstate32, XED_ICLASS_PUSH, 0, xed_reg(XED_REG_ECX)); + ninst++; + + xed_inst2(x+ninst, dstate32, XED_ICLASS_XOR, 0, + xed_reg(XED_REG_ECX), + xed_reg(XED_REG_EDX)); + ninst++; + + + /* this one has a nondefault effective operand width for 64b mode so we + must specify it. XED could figure this output from the operands, + but currently it does not. */ + + xed_inst2(x+ninst, dstate64, XED_ICLASS_XOR, 64, + xed_reg(XED_REG_RCX), + xed_reg(XED_REG_RDX)); + ninst++; + + /* nondefault effective operand width for 64b mode so we must specify + it. XED could figure it out from the opcode, but currently does + not. */ + xed_inst0(x+ninst, dstate64, XED_ICLASS_REPE_CMPSQ, 64); + ninst++; + + /* here it is ambiguous from the opcode what the effective operand + * width is. I could use the operand, but do not do that yet. */ + xed_inst1(x+ninst, dstate64, XED_ICLASS_PUSH, 64, xed_reg(XED_REG_RCX)); + ninst++; + + /* again, here's one where I could infer that the operation is 64b from + * the memory operand, but not yet. */ + xed_inst1(x+ninst, dstate64, XED_ICLASS_PUSH, 64, + xed_mem_bd(XED_REG_RDX, xed_disp(0x11223344, 32), 64)); + ninst++; + + // move a 64b quantity in to RAX using only a 64b displacment + xed_inst2(x+ninst, dstate64, XED_ICLASS_MOV, 64, + xed_reg(XED_REG_RAX), + xed_mem_bd(XED_REG_INVALID, xed_disp(0x1122334455667788, 64), 64)); + ninst++; + + + + xed_inst1(x+ninst, dstate64, XED_ICLASS_JMP_FAR, 64, + xed_mem_bd(XED_REG_RAX, xed_disp(0x20, 8), 80)); + + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_ADD, 64, + xed_reg(XED_REG_RAX), + xed_imm0(0x77,8)); + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_ADD, 64, + xed_reg(XED_REG_RAX), + xed_imm0(0x44332211,32)); + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_MOV_CR, 64, + xed_reg(XED_REG_CR3), + xed_reg(XED_REG_RDI)); + ninst++; + + xed_inst2(x+ninst, + dstate64, XED_ICLASS_MOV, 32, + xed_mem_bisd(XED_REG_R8, XED_REG_RBP, 1, xed_disp(0xf8, 8), 32), + xed_simm0(0x0,32)); + ninst++; + + + // example showing how to set the effective address size to 32b in 64b + // mode. Normally XED deduces that from the memory operand base + // register, but in this case the memops are implicit. + xed_inst0(x+ninst, + dstate64, XED_ICLASS_STOSQ, 64); + xed_addr(x+ninst, 32); + ninst++; + + + xed_inst1(x+ninst, + dstate32, + XED_ICLASS_JECXZ, + 4, + xed_relbr(5, 8)); + ninst++; + + xed_inst1(x+ninst, + dstate64, + XED_ICLASS_JECXZ, + 4, + xed_relbr(5, 8)); + xed_addr(x+ninst,32); + ninst++; + + xed_inst1(x+ninst, + dstate64, + XED_ICLASS_JRCXZ, + 4, + xed_relbr(5, 8)); + ninst++; + + +#if defined(XED_AVX) + xed_inst2(x+ninst, + dstate64, + XED_ICLASS_VBROADCASTSD, + 32, + xed_reg(XED_REG_YMM4), + xed_mem_gbisd(XED_REG_GS,XED_REG_INVALID,0,0, + xed_disp(0x808, 32), + 64)); + ninst++; +#endif + +#if defined(XED_SUPPORTS_AVX512) + // example showing how to set EVEX features. + // increase the number of operands and use xed_other(...) + xed_inst5(x+ninst, + dstate64, + XED_ICLASS_VADDPS, + 32, + xed_reg(XED_REG_XMM1), + xed_reg(XED_REG_K1), + xed_reg(XED_REG_XMM2), + xed_mem_b(XED_REG_RCX, 16), + xed_other(XED_OPERAND_ZEROING,1)); + ninst++; +#endif + + + for(i=0;iencoder example. + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" +#include +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +int +main(int argc, char** argv) { + xed_error_enum_t xed_error; + xed_bool_t long_mode = 0; + xed_bool_t prot16 = 0; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int i; + unsigned int argcu = (unsigned int)argc; + unsigned int u; + xed_decoded_inst_t xedd; +#define BUFLEN 1000 + char buffer[BUFLEN]; + xed_bool_t ok; + unsigned int isyntax; + xed_syntax_enum_t syntax; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + xed_encoder_request_t* enc_req; + xed_uint8_t array[XED_MAX_INSTRUCTION_BYTES]; + unsigned int enc_olen, ilen = XED_MAX_INSTRUCTION_BYTES; + xed_error_enum_t encode_okay; + xed_bool_t change_to_long_mode = 0; + + xed_tables_init(); + xed_set_verbosity( 99 ); + + if (argcu > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + else if (argcu > 2 && strcmp(argv[1], "-16") == 0) + prot16 = 1; + + if (long_mode) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + } + else if (prot16) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width =XED_ADDRESS_WIDTH_16b; + } + else { + first_argv=1; + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + } + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + + for( i=first_argv ;i < argcu; i++) { + if (strlen(argv[i]) != 2) { + fprintf(stderr, "not two hex characters: \"%s\"\n", argv[i]); + exit(1); + } + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes, e.g., 48 89 C0\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +void print_operands(xed_decoded_inst_t* xedd) { + unsigned int i = 0; + xed_inst_t const* const xi = xed_decoded_inst_inst(xedd); + const unsigned int noperands = xed_inst_noperands(xi); + + for( i=0; i < noperands ; i++) { + xed_operand_t const* op = xed_inst_operand(xi,i); + xed_operand_enum_t op_name = xed_operand_name(op); + if (xed_operand_is_register(op_name)) { + xed_reg_enum_t reg = xed_decoded_inst_get_reg(xedd,op_name); + xed_operand_action_enum_t rw = xed_decoded_inst_operand_action(xedd,i); + printf("%2d: %5s %5s\n", + (int)i, + xed_reg_enum_t2str(reg), + xed_operand_action_enum_t2str(rw)); + } + } +} + + +int +main(int argc, char** argv) { + xed_error_enum_t xed_error; + xed_bool_t long_mode = 0; + xed_bool_t prot16 = 0; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int i; + unsigned int argcu = (unsigned int) argc; + unsigned int u; + xed_decoded_inst_t xedd; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + + xed_tables_init(); + xed_set_verbosity( 99 ); + + if (argcu > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + else if (argcu > 2 && strcmp(argv[1], "-16") == 0) + prot16 = 1; + + if (long_mode) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + } + else if (prot16) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width =XED_ADDRESS_WIDTH_16b; + } + else { + first_argv=1; + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + } + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + + for( i=first_argv ;i < argcu; i++) { + if (strlen(argv[i]) != 2) { + fprintf(stderr, "not two hex characters: \"%s\"\n", argv[i]); + exit(1); + } + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes, e.g., 48 89 C0\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include +#include //strcmp +#include + +int main(int argc, char** argv); + +void check_for_mov_to_cr3(xed_decoded_inst_t* xedd) +{ + if (xed_decoded_inst_get_iclass(xedd) == XED_ICLASS_MOV_CR) + { + // we know mov_cr has 2 operands so we do not check + // xed_inst_noperands. + + + // get the skeleton (static info) + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + + // get the dest operand (operand 0) + const xed_operand_t* op = xed_inst_operand(xi,0); + + xed_operand_enum_t op_name = xed_operand_name(op); + if (op_name == XED_OPERAND_REG0) + { + xed_reg_enum_t r = xed_decoded_inst_get_reg(xedd, op_name); + if (r == XED_REG_CR3) + { + printf("Found a mov to CR3\n"); + } + } + } +} + +int +main(int argc, char** argv) { + xed_error_enum_t xed_error; + xed_bool_t long_mode = 0; + xed_bool_t prot16 = 0; + unsigned int first_argv; + unsigned int bytes = 0; + unsigned char itext[XED_MAX_INSTRUCTION_BYTES]; + unsigned int i; + unsigned int argcu = (unsigned int) argc; + unsigned int u; + xed_decoded_inst_t xedd; + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + + xed_tables_init(); + xed_set_verbosity( 99 ); + + if (argcu > 2 && strcmp(argv[1], "-64") == 0) + long_mode = 1; + else if (argcu > 2 && strcmp(argv[1], "-16") == 0) + prot16 = 1; + + if (long_mode) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width =XED_ADDRESS_WIDTH_64b; + } + else if (prot16) { + first_argv = 2; + mmode=XED_MACHINE_MODE_LEGACY_16; + stack_addr_width =XED_ADDRESS_WIDTH_16b; + } + else { + first_argv=1; + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width =XED_ADDRESS_WIDTH_32b; + } + + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + + for( i=first_argv ;i < argcu; i++) { + if (strlen(argv[i]) != 2) { + fprintf(stderr, "not two hex characters: \"%s\"\n", argv[i]); + exit(1); + } + xed_uint8_t x = (xed_uint8_t)(xed_atoi_hex(argv[i])); + assert(bytes < XED_MAX_INSTRUCTION_BYTES); + itext[bytes++] = x; + } + if (bytes == 0) { + fprintf(stderr, "Must supply some hex bytes, e.g., 48 89 C0\n"); + exit(1); + } + + printf("PARSING BYTES: "); + for( u=0;u +#include // malloc, etc. +#include //strcmp +#include + + +xed_error_enum_t ex_make_patchable_instr(xed_encoder_instruction_t* to_enc, + xed_decoded_inst_t* xedd, + xed_uint8_t* itext, + xed_uint_t ilen) +{ + xed_encoder_request_t xede; + xed_bool_t convert_ok; + xed_error_enum_t xed_error; + xed_uint_t olen = 0; + + xed_encoder_request_zero_set_mode(&xede, &(to_enc->mode)); + convert_ok = xed_convert_to_encoder_request(&xede,to_enc); + if (!convert_ok) { + fprintf(stderr,"conversion to encode request failed\n"); + return XED_ERROR_GENERAL_ERROR; + } + xed_error = xed_encode(&xede, itext, ilen, &olen); + if (xed_error) + return xed_error; + + // decode in to xedd + xed_decoded_inst_zero_set_mode(xedd, &(to_enc->mode)); + xed_error = xed_decode(xedd, itext, olen); + + return xed_error; +} + + +#define NINST 50 +#define DBUFLEN 1000 + +int main(int argc, char** argv); + +int +main(int argc, char** argv) +{ + xed_error_enum_t xed_error; + xed_state_t dstate32, dstate64; + + xed_uint8_t itext[NINST][XED_MAX_INSTRUCTION_BYTES]; + unsigned int ilen[NINST]; + xed_encoder_instruction_t to_enc[NINST]; + xed_decoded_inst_t xedd[NINST]; + + unsigned int i, ninst=0; + + xed_bool_t ok; + char buffer[DBUFLEN]; + + for(i=0;i decode) */ + + for(i=0;i //strlen, memcmp, memset +#include //ptrdiff_t +#if defined(XED_MAC) || defined(XED_LINUX) || defined(XED_BSD) +# include +# include +# include +# include +# include +#endif +#include +#include +#include +#include "xed-dot-prep.h" + + +#include "xed/xed-ild.h" +#if defined(PTI_XED_TEST) +#include "pti-xed-test.h" +#endif + +#define DCAST(x) XED_STATIC_CAST(double,(x)) +#define XCAST(x) XED_STATIC_CAST(xed_int64_t,(x)) +#define U64CAST(x) XED_STATIC_CAST(xed_uint64_t,(x)) +#define ICAST(x) XED_STATIC_CAST(xed_int_t,(x)) +#define UCAST(x) XED_STATIC_CAST(xed_uint_t,(x)) + + +#define XED_TMP_BUF_LEN (1024*4) + + +#define XED_HISTO_MAX_CYCLES 10000 // must be divisible by cycles/bin +#define XED_HISTO_CYCLES_PER_BIN 50 +#define XED_HISTO_BINS (XED_HISTO_MAX_CYCLES/XED_HISTO_CYCLES_PER_BIN) + +typedef struct { + xed_uint64_t total_time ; + xed_uint64_t total_insts ; + xed_uint64_t total_ilen ; + xed_uint64_t total_olen ; + xed_uint64_t total_shorter ; + xed_uint64_t total_longer ; + xed_uint64_t bad_times ; + xed_uint64_t reset_counter; + + xed_uint64_t total_insts_tail; + xed_uint64_t total_time_tail; + xed_uint64_t perf_tail; + + xed_uint64_t histo[XED_HISTO_BINS]; +} xed_stats_t; + +#if defined(XED_DECODER) +static void +update_histogram(xed_stats_t* p, + xed_uint64_t delta) +{ + xed_uint32_t bin; + if (delta < XED_HISTO_MAX_CYCLES) + bin = XED_STATIC_CAST(xed_uint32_t, delta / XED_HISTO_CYCLES_PER_BIN); + else + bin = XED_HISTO_BINS-1; + p->histo[bin]++; +} + +static void +init_histogram(xed_stats_t* p) +{ + memset(p->histo, 0, + sizeof(xed_uint64_t)*XED_HISTO_BINS); +} + + +static void +xed_stats_update(xed_stats_t* p, + xed_uint64_t t1, + xed_uint64_t t2) +{ + if (t2 > t1) + { + xed_uint64_t delta = t2-t1; + p->total_time += delta; + update_histogram(p,delta); + } + else + p->bad_times++; + p->total_insts++; + p->reset_counter++; + if (p->reset_counter == 50) { + if (CLIENT_VERBOSE1) + printf("\n\nRESETTING STATS\n\n"); + // to ignore startup transients paging everything in. + init_histogram(p); + p->total_insts=0; + p->total_time=0; + } + //these guys count average on tail instructions - + //when all cpu caches and tables are full + if (p->total_insts >= p->perf_tail) { + p->total_insts_tail++; + p->total_time_tail += (t2-t1); + } +} + +static void +xed_stats_zero(xed_stats_t* p, + xed_disas_info_t* di) +{ + p->total_time = 0; + p->total_insts = 0; + p->total_ilen = 0; + p->total_olen = 0; + p->total_shorter = 0; + p->total_longer = 0; + p->bad_times = 0; + p->reset_counter = 0; + + p->total_time_tail = 0; + p->total_insts_tail = 0; + p->perf_tail = di->perf_tail_start; + + init_histogram(p); +} +#endif + +static xed_stats_t xed_dec_stats; +static xed_stats_t xed_enc_stats; + +void xed_disas_info_init(xed_disas_info_t* p) +{ + memset(p,0,sizeof(xed_disas_info_t)); +} + +xed_syntax_enum_t global_syntax = XED_SYNTAX_INTEL; +int client_verbose=0; + +//////////////////////////////////////////////////////////////////////////// + +static char xed_toupper(char c) { + if (c >= 'a' && c <= 'z') { + int t = c - 'a'; + char u = (char)(t+'A'); + return u; + } + return c; +} + +char* xed_upcase_buf(char* s) { + xed_uint_t len = XED_STATIC_CAST(xed_uint_t,strlen(s)); + xed_uint_t i; + for(i=0 ; i < len ; i++ ) + s[i] = xed_toupper(s[i]); + return s; +} + +static xed_uint8_t letter_cvt(char a, char base) { + return (xed_uint8_t)(a-base); +} + +static xed_uint8_t convert_nibble(char x) { + // convert ascii nibble to hex + xed_uint8_t rv = 0; + if (x >= '0' && x <= '9') + rv = letter_cvt(x, '0'); + else if (x >= 'A' && x <= 'F') + rv = (xed_uint8_t)(letter_cvt(x,'A') + 10U); + else if (x >= 'a' && x <= 'f') + rv = (xed_uint8_t)(letter_cvt(x,'a') + 10U); + else { + printf("Error converting hex digit. Nibble value 0x%x\n", x); + exit(1); + } + return rv; +} + + +xed_int64_t xed_atoi_hex(char* buf) { + xed_int64_t o=0; + xed_uint_t i; + xed_uint_t len = XED_STATIC_CAST(xed_uint_t,strlen(buf)); + for(i=0; i= (2*n+1)); /* including null */ + for( i=0 ; i< n; i++) { + buf[2*i+0] = nibble_to_ascii_hex(array[i]>>4); + buf[2*i+1] = nibble_to_ascii_hex(array[i]&0xF); + } + buf[2*i]=0; +} + + + +void XED_NORETURN xedex_derror(const char* s) { + printf("[XED CLIENT ERROR] %s\n",s); + exit(1); +} + +void xedex_dwarn(const char* s) { + printf("[XED CLIENT WARNING] %s\n",s); +} + + +//////////////////////////////////////////////////////////////////////////// + +#if defined(XED_DECODER) +//#define BINARY_DUMP + +#if defined (BINARY_DUMP) +int fd = 0; +void open_binary_output_file(void); +void open_binary_output_file(void) +{ + fd = open("output", O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU); + if (fd == -1) { + fprintf(stderr,"Could not open binary output file\n"); + exit(1); + } +} +#endif + +static XED_INLINE xed_error_enum_t +decode_internal(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + xed_uint_t max_bytes) +{ + xed_error_enum_t err = xed_decode(xedd,itext,max_bytes); + +#if defined (BINARY_DUMP) + if (err == XED_ERROR_NONE) + write(fd, itext, xed_decoded_inst_get_length(xedd)); +#endif + + return err; +} +#endif + +void init_xedd(xed_decoded_inst_t* xedd, + xed_disas_info_t* di) +{ + + +#if defined(XED_DECODER) + xed_decoded_inst_zero_set_mode(xedd, &(di->dstate)); +#endif + xed_decoded_inst_set_input_chip(xedd, di->chip); +#if defined(XED_MPX) + xed3_operand_set_mpxmode(xedd, di->mpx_mode); +#endif +#if defined(XED_CET) + xed3_operand_set_cet(xedd, di->cet_mode); +#endif + if (di->operand != XED_OPERAND_INVALID) + xed3_set_generic_operand(xedd, di->operand, di->operand_value); +} + +//////////////////////////////////////////////////////////////////////////// + +static void +dump_histo(xed_uint64_t* histo, + xed_uint32_t bins, + xed_uint32_t cycles_per_bin) +{ + xed_uint32_t i=0; + xed_uint64_t total=0; + double cdf = 0; + for(i=0;itotal_time); + printf("#Total instructions %s: " XED_FMT_LU "\n", dec_enc, + p->total_insts); + printf("#Total tail %s cycles: " XED_FMT_LU "\n", dec_enc, + p->total_time_tail); + printf("#Total tail instructions %s: " XED_FMT_LU "\n", dec_enc, + p->total_insts_tail); + + cpi = 1.0 * DCAST(p->total_time) / DCAST(p->total_insts); + printf("#Total cycles/instruction %s: %.2f\n" , dec_enc, cpi); + + cpi_tail = 1.0 * DCAST(p->total_time_tail) / + DCAST(p->total_insts_tail); + printf("#Total tail cycles/instruction %s: %.2f\n" , dec_enc, cpi_tail); + + if (p->bad_times) + printf("#Bad times: " XED_FMT_LU "\n", p->bad_times); + + if (di->histo) + dump_histo(p->histo, XED_HISTO_BINS, XED_HISTO_CYCLES_PER_BIN); +} + +void xed_print_decode_stats(xed_disas_info_t* di) +{ + print_decode_stats_internal(di, &xed_dec_stats, "XED3", "DECODE"); +} + +void xed_print_encode_stats(xed_disas_info_t* di) +{ + print_decode_stats_internal(di, &xed_enc_stats, "XED3", "ENCODE"); +} + + + +void +xed_map_region(const char* path, + void** start, + unsigned int* length) +{ +#if defined(_WIN32) + FILE* f; + size_t t,ilen; + xed_uint8_t* p; +#if defined(XED_MSVC8_OR_LATER) && !defined(PIN_CRT) + errno_t err; + fprintf(stderr,"#Opening %s\n", path); + err = fopen_s(&f,path,"rb"); +#else + int err=0; + fprintf(stderr,"#Opening %s\n", path); + f = fopen(path,"rb"); + err = (f==0); +#endif + if (err != 0) { + fprintf(stderr,"ERROR: Could not open %s\n", path); + exit(1); + } + err = fseek(f, 0, SEEK_END); + if (err != 0) { + fprintf(stderr,"ERROR: Could not fseek %s\n", path); + exit(1); + } + ilen = ftell(f); + fprintf(stderr,"#Trying to read " XED_FMT_SIZET "\n", ilen); + p = (xed_uint8_t*)malloc(ilen); + assert(p!=0); + t=0; + err = fseek(f,0, SEEK_SET); + if (err != 0) { + fprintf(stderr,"ERROR: Could not fseek to start of file %s\n", path); + exit(1); + } + + while(t < ilen) { + size_t n; + if (feof(f)) { + fprintf(stderr, "#Read EOF. Stopping.\n"); + break; + } + n = fread(p+t, 1, ilen-t,f); + t = t+n; + fprintf(stderr,"#Read " XED_FMT_SIZET " of " XED_FMT_SIZET " bytes\n", + t, ilen); + if (ferror(f)) { + fprintf(stderr, "Error in file read. Stopping.\n"); + break; + } + } + fclose(f); + *start = p; + *length = (unsigned int)ilen; + +#else + off_t ilen; + int fd; + fd = open(path, O_RDONLY); + if (fd == -1) { + printf("Could not open file: %s\n" , path); + exit(1); + } + ilen = lseek(fd, 0, SEEK_END); // find the size. + if (ilen == -1) + xedex_derror("lseek failed"); + else + *length = (unsigned int) ilen; + + lseek(fd, 0, SEEK_SET); // go to the beginning + *start = mmap(0, + *length, + PROT_READ|PROT_WRITE, + MAP_PRIVATE, + fd, + 0); + if (*start == (void*) -1) + xedex_derror("could not map region"); +#endif + if (CLIENT_VERBOSE1) + printf("Mapped " XED_FMT_U " bytes!\n", *length); +} + + +//////////////////////////////////////////////////////////////////////////// + +#if defined(XED_DECODER) + +static xed_disassembly_callback_fn_t registered_disasm_callback=0; + +void +xed_register_disassembly_callback(xed_disassembly_callback_fn_t f) +{ + registered_disasm_callback = f; +} + + +void disassemble(xed_disas_info_t* di, + char* buf, + int buflen, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + void* caller_data) +{ + xed_bool_t ok; + xed_print_info_t pi; + xed_init_print_info(&pi); + pi.p = xedd; + pi.blen = buflen; + pi.buf = buf; + + // passed back to symbolic disassembly function + pi.context = caller_data; + + // 0=use the default symbolic disassembly function registered via + // xed_register_disassembly_callback(). If nonzero, it would be a + // function pointer to a disassembly callback routine. See xed-disas.h + pi.disassembly_callback = registered_disasm_callback; + + pi.runtime_address = runtime_instruction_address; + pi.syntax = global_syntax; + pi.format_options_valid = 1; + pi.format_options = di->format_options; + pi.buf[0]=0; //allow use of strcat + + ok = xed_format_generic(&pi); + if (!ok) + { + pi.blen = xed_strncpy(pi.buf,"Error disassembling ",pi.blen); + pi.blen = xed_strncat(pi.buf, + xed_syntax_enum_t2str(pi.syntax), + pi.blen); + pi.blen = xed_strncat(pi.buf," syntax.",pi.blen); + } +} + +void xed_decode_error( xed_uint64_t runtime_instruction_address, + xed_uint64_t offset, + const xed_uint8_t* ptr, + xed_error_enum_t xed_error, + xed_uint_t length) +{ + char buf[XED_HEX_BUFLEN]; + printf("ERROR: %s Could not decode at offset: 0x" + XED_FMT_LX " len: %d PC: 0x" XED_FMT_LX ": [", + xed_error_enum_t2str(xed_error), + offset, + length, + runtime_instruction_address); + + xed_print_hex_line(buf, ptr, length, XED_HEX_BUFLEN); + printf("%s]\n",buf); +} + +static void +print_hex_line(const xed_uint8_t* p, + unsigned int length) +{ + char buf[XED_HEX_BUFLEN]; + unsigned int lim = XED_HEX_BUFLEN/2; + if (length < lim) + lim = length; + xed_print_hex_line(buf,p, lim, XED_HEX_BUFLEN); + printf("%s\n", buf); +} + +static void +print_attributes(xed_decoded_inst_t* xedd) { + /* Walk the attributes. Generally, you'll know the one you want to + * query and just access that one directly. */ + + const xed_inst_t* xi = xed_decoded_inst_inst(xedd); + + unsigned int i, nattributes = xed_attribute_max(); + + printf("ATTRIBUTES: "); + for(i=0;iencode_force); + + // encode it again... + et1 = xed_get_time(); + encode_okay = xed_encode(enc_req, array, ilen, &enc_olen); + et2 = xed_get_time(); + xed_stats_update(&xed_enc_stats, et1, et2); + if (encode_okay != XED_ERROR_NONE) { + if (CLIENT_VERBOSE) { + char buf[XED_TMP_BUF_LEN]; + char buf2[XED_TMP_BUF_LEN]; + int blen=XED_TMP_BUF_LEN; + xed_encode_request_print(enc_req, buf, XED_TMP_BUF_LEN); + blen = xed_strncpy(buf2,"Could not re-encode: ", blen); + blen = xed_strncat(buf2, buf, blen); + blen = xed_strncat(buf2,"\nError code was: ",blen); + blen = xed_strncat(buf2, + xed_error_enum_t2str(encode_okay),blen); + blen = xed_strncat(buf2, "\n",blen); + xedex_dwarn(buf2); + } + } + else { + retval_olen = enc_olen; + // See if it matched the original... + if (CLIENT_VERBOSE) { + char buf[XED_HEX_BUFLEN]; + xed_uint_t dec_length; + xed_print_hex_line(buf,array, enc_olen, XED_HEX_BUFLEN); + printf("Encodable! %s\n",buf); + dec_length = xed_decoded_inst_get_length(xedd); + if ((enc_olen != dec_length || + memcmp(decode_text_binary, array, enc_olen) )) { + char buf2[XED_TMP_BUF_LEN]; + char buf3[XED_TMP_BUF_LEN]; + printf("Discrepenacy after re-encoding. dec_len= " + XED_FMT_U " ", dec_length); + xed_print_hex_line(buf, decode_text_binary, + dec_length,XED_HEX_BUFLEN); + printf("[%s] ", buf); + printf("enc_olen= " XED_FMT_U "", enc_olen); + xed_print_hex_line(buf, array, enc_olen, XED_HEX_BUFLEN); + printf(" [%s] ", buf); + printf("for instruction: "); + xed_decoded_inst_dump(xedd, buf3,XED_TMP_BUF_LEN); + printf("%s\n", buf3); + printf("vs Encode request: "); + xed_encode_request_print(enc_req, buf2, XED_TMP_BUF_LEN); + printf("%s\n", buf2); + } + else + printf("Identical re-encoding\n"); + } + } + } + return retval_olen; +} +#endif +/////////////////////////////////////////////////////////////////////////// +#if defined(XED_DECODER) && defined(XED_AVX) +typedef enum { XED_AST_INPUT_NOTHING, + XED_AST_INPUT_SSE, + XED_AST_INPUT_AVX_SCALAR, + XED_AST_INPUT_AVX128, + XED_AST_INPUT_AVX256, + XED_AST_INPUT_VZEROALL, + XED_AST_INPUT_VZEROUPPER, + XED_AST_INPUT_XRSTOR, + XED_AST_INPUT_EVEX_SCALAR, + XED_AST_INPUT_EVEX128, + XED_AST_INPUT_EVEX256, + XED_AST_INPUT_EVEX512, + XED_AST_INPUT_LAST } xed_ast_input_enum_t; + +static char const* const xed_ast_input_enum_t_strings[] = { + "n/a", + "sse", + "avx.scalar", + "avx.128", + "avx.256", + "vzeroall", + "vzeroupper", + "xrstor", + "evex.scalar", + "evex.128", + "evex.256", + "evex.512" +}; + +static xed_uint8_t avx_extensions[XED_EXTENSION_LAST]; +static void init_interesting_avx(void) { + memset(avx_extensions,0,sizeof(xed_uint8_t)*XED_EXTENSION_LAST); + avx_extensions[XED_EXTENSION_AVX]=1; + avx_extensions[XED_EXTENSION_FMA]=1; + avx_extensions[XED_EXTENSION_F16C]=1; + avx_extensions[XED_EXTENSION_AVX2]=1; + avx_extensions[XED_EXTENSION_AVX2GATHER]=1; +#if defined(XED_SUPPORTS_AVX512) + avx_extensions[XED_EXTENSION_AVX512EVEX]=1; +#endif +} +static XED_INLINE int is_interesting_avx(xed_extension_enum_t extension) { + return avx_extensions[extension]; +} +static XED_INLINE xed_ast_input_enum_t avx_type(xed_decoded_inst_t* xedd) { + xed_uint32_t vl; +#if defined(XED_SUPPORTS_AVX512) + xed_uint32_t avx512 = (xed_decoded_inst_get_extension(xedd) == XED_EXTENSION_AVX512EVEX); +#else + xed_uint32_t avx512 = 0; +#endif + + // scalar ops are implicitly 128b + if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_SIMD_SCALAR)) + return avx512 ? XED_AST_INPUT_EVEX_SCALAR : XED_AST_INPUT_AVX_SCALAR; + + // look at the VEX.VL field + vl = xed3_operand_get_vl(xedd); + switch(vl) { + case 0: return avx512 ? XED_AST_INPUT_EVEX128 : XED_AST_INPUT_AVX128; + case 1: return avx512 ? XED_AST_INPUT_EVEX256 : XED_AST_INPUT_AVX256; + case 2: return XED_AST_INPUT_EVEX512; + default: return XED_AST_INPUT_NOTHING; + } +} +static int is_sse(xed_decoded_inst_t* xedd) { + const xed_extension_enum_t extension = xed_decoded_inst_get_extension(xedd); + const xed_category_enum_t category = xed_decoded_inst_get_category(xedd); + + if (extension == XED_EXTENSION_SSE) + { + if (category != XED_CATEGORY_MMX && + category != XED_CATEGORY_PREFETCH) /* exclude PREFETCH* insts */ + return 1; + } + else if (extension == XED_EXTENSION_SSE2 || + extension == XED_EXTENSION_SSSE3 || + extension == XED_EXTENSION_SSE4) + { + if (category != XED_CATEGORY_MMX) + return 1; + } + else if (extension == XED_EXTENSION_AES || + extension == XED_EXTENSION_PCLMULQDQ +#if defined(XED_SUPPORTS_SHA) + || extension == XED_EXTENSION_SHA +#endif + ) + { + return 1; + } + return 0; +} + +static char const* xed_ast_input_enum_t2str(xed_ast_input_enum_t e) { + assert(e < XED_AST_INPUT_LAST); + return xed_ast_input_enum_t_strings[e]; +} +static xed_ast_input_enum_t classify_avx_sse(xed_decoded_inst_t* xedd) +{ + xed_extension_enum_t ext = xed_decoded_inst_get_extension(xedd); + xed_iclass_enum_t iclass = xed_decoded_inst_get_iclass(xedd); + if (iclass == XED_ICLASS_VZEROALL) { + return XED_AST_INPUT_VZEROALL; + } + else if (iclass == XED_ICLASS_VZEROUPPER) { + return XED_AST_INPUT_VZEROUPPER; + } + else if (is_interesting_avx(ext)) { + return avx_type(xedd); + } + else if (is_sse(xedd)) { + return XED_AST_INPUT_SSE; + } + else if (iclass == XED_ICLASS_XRSTOR) { + return XED_AST_INPUT_XRSTOR; + } + return XED_AST_INPUT_NOTHING; +} +#endif // XED_AVX + +/////////////////////////////////////////////////////////////////////////// +#if defined(XED_DECODER) + +static int +all_zeros(xed_uint8_t* p, unsigned int len) +{ + unsigned int i; + for( i=0;isymfn) { + char* name = (*di->symfn)(runtime_instruction_address, + di->caller_symbol_data); + if (name) { + if (di->xml_format) + printf("\n%s\n", name); + else + printf("\nSYM %s:\n", name); + } + } +} + +static void +emit_hex(xed_decoded_inst_t* xedd, unsigned char* z) +{ + unsigned int dec_len; + char buffer[XED_HEX_BUFLEN]; + dec_len = xed_decoded_inst_get_length(xedd); + xed_print_hex_line(buffer, (xed_uint8_t*) z, + dec_len, XED_HEX_BUFLEN); + printf("%s",buffer); + emit_pad(dec_len); +} + +static void +emit_cat_ext(xed_decoded_inst_t* xedd, + xed_disas_info_t* di) +{ + printf("%-9s ", + xed_category_enum_t2str( + xed_decoded_inst_get_category(xedd))); + printf("%-10s ", + xed_extension_enum_t2str( + xed_decoded_inst_get_extension(xedd))); + + if (di->emit_isa_set) + printf("%-10s ", + xed_isa_set_enum_t2str( + xed_decoded_inst_get_isa_set(xedd))); + +} +static void +emit_resync_msg(unsigned char* z, unsigned int x) +{ + char buf[XED_HEX_BUFLEN]; + printf("ERROR: found symbol in the middle of" + " an instruction. Resynchronizing...\n"); + printf("ERROR: Rejecting: ["); + xed_print_hex_line(buf, z, x, XED_HEX_BUFLEN); + printf("%s]\n",buf); +} + +static void +emit_dec_sep_msg(unsigned int i) { + printf("\n==============================================\n"); + printf("Decoding instruction " XED_FMT_U "\n", i); + printf("==============================================\n"); +} + +static void +emit_addr_hex(xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_uint_t ilim) +{ + char tbuf[XED_HEX_BUFLEN]; + printf("Runtime Address " XED_FMT_LX , + runtime_instruction_address); + xed_print_hex_line(tbuf, (xed_uint8_t*) z, ilim, XED_HEX_BUFLEN); + printf(" [%s]\n", tbuf); +} + +static void +emit_cat_ext_ast(xed_decoded_inst_t* xedd, + xed_disas_info_t* di) +{ +#if defined(XED_AVX) + if (di->ast) + { + printf("%-11s ", + xed_ast_input_enum_t2str( + classify_avx_sse(xedd))); + } + else +#endif + { + emit_cat_ext(xedd,di); + } + (void)di; //pacify compiler +} + +static void +emit_line_num(xed_disas_info_t* di, + xed_error_enum_t xed_error, + xed_uint64_t runtime_instruction_address) +{ + if (di->line_numbers || + xed_error == XED_ERROR_INVALID_FOR_CHIP) + { + if (di->line_number_info_fn) + (*di->line_number_info_fn)( + runtime_instruction_address); + } +} + + +static void +emit_xml(xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_disas_info_t* di) +{ + char buffer[XED_TMP_BUF_LEN]; + unsigned int dec_len; + + printf("\n"); + printf(" " XED_FMT_LX "\n", + runtime_instruction_address); + printf(" %s\n", + xed_category_enum_t2str( xed_decoded_inst_get_category(xedd))); + printf(" %s\n", + xed_extension_enum_t2str(xed_decoded_inst_get_extension(xedd))); + printf(" "); + dec_len = xed_decoded_inst_get_length(xedd); + xed_print_hex_line(buffer, (xed_uint8_t*) z, + dec_len, XED_TMP_BUF_LEN); + printf("%s\n",buffer); + disassemble(di, buffer,XED_TMP_BUF_LEN, + xedd, runtime_instruction_address, + di->caller_symbol_data); + printf( " %s\n",buffer); + printf("\n"); +} + + +static void +emit_disasm(xed_disas_info_t* di, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_dot_graph_supp_t* gs, + xed_error_enum_t xed_error) +{ + if (CLIENT_VERBOSE1) { + char tbuf[XED_TMP_BUF_LEN]; + xed_decoded_inst_dump(xedd,tbuf, XED_TMP_BUF_LEN); + printf("%s\n",tbuf); + } + if (CLIENT_VERBOSE) { + emit_sym(di, runtime_instruction_address); + if (di->xml_format) + emit_xml(xedd, runtime_instruction_address, z, di); + else + { + char buffer[XED_TMP_BUF_LEN]; + char const* fmt = "XDIS " XED_FMT_LX ": "; + if (di->format_options.lowercase_hex==0) + fmt = "XDIS " XED_FMT_LX_UPPER ": "; + + printf(fmt, runtime_instruction_address); + emit_cat_ext_ast(xedd,di); + emit_hex(xedd, z); + disassemble(di, + buffer,XED_TMP_BUF_LEN, + xedd, + runtime_instruction_address, + di->caller_symbol_data); + printf( "%s",buffer); + if (gs) { + xed_dot_graph_add_instruction( + gs, + xedd, + runtime_instruction_address, + di->caller_symbol_data, + registered_disasm_callback); + } + + if (xed_error == XED_ERROR_INVALID_FOR_CHIP) { + di->errors_chip_check++; + printf(" # INVALID-FOR-CHIP"); + } + emit_line_num(di, xed_error, + runtime_instruction_address); + + printf( "\n"); + } + } +} +static unsigned int +check_resync(xed_disas_info_t* di, + xed_uint64_t runtime_instruction_address, + unsigned int length, + unsigned char* z) +{ + if (di->resync && di->symfn) + { + unsigned int x; + for ( x=1 ; xsymfn)(runtime_instruction_address+x, + di->caller_symbol_data); + if (name) + { + /* bad news. We found a symbol in the middle of an + * instruction. That probably means decoding is messed up. + * This usually happens because of data-in the code/text + * section. We should reject the current instruction and + * pick up at the symbol address. */ + emit_resync_msg(z,x); + return x; + } + } + } + return 0; +} + +static void XED_NORETURN +die_zero_len( + xed_uint64_t runtime_instruction_address, + unsigned char* z, + xed_disas_info_t* di, + xed_error_enum_t xed_error) +{ + printf("Zero length on decoded instruction!\n"); + xed_decode_error( runtime_instruction_address, + U64CAST(z-di->a), z, xed_error, 15); + xedex_derror("Dying"); +} + +void xed_disas_test(xed_disas_info_t* di) +{ + // this decodes are region defined by the input structure. + + static int first = 1; + xed_uint64_t errors = 0; + unsigned int m; + unsigned char* z; // our sliding pointer for decoding + unsigned char* zlimit; + unsigned int length; + int skipping; + int last_all_zeros; + unsigned int i; + int okay; + xed_decoded_inst_t xedd; + xed_uint64_t runtime_instruction_address; + xed_dot_graph_supp_t* gs = 0; + xed_bool_t graph_empty = 1; + unsigned int resync; + + if (di->dot_graph_output) { + xed_syntax_enum_t local_syntax = XED_SYNTAX_INTEL; + gs = xed_dot_graph_supp_create(local_syntax); + } + + if (first) { + xed_stats_zero(&xed_dec_stats, di); + first = 0; + } + + m = di->ninst; // number of things to decode + z = di->a; // set to start of region + + if (di->runtime_vaddr_disas_start) + if (di->runtime_vaddr_disas_start > di->runtime_vaddr) + z = (di->runtime_vaddr_disas_start - di->runtime_vaddr) + + di->a; + + zlimit = 0; + if (di->runtime_vaddr_disas_end) { + if (di->runtime_vaddr_disas_end > di->runtime_vaddr) + zlimit = (di->runtime_vaddr_disas_end - di->runtime_vaddr) + + di->a; + else /* end address is before start of this region -- skip it */ + goto finish; + } + + if (z >= di->q) /* start pointer is after end of section */ + goto finish; + + // for skipping long strings of zeros + skipping = 0; + last_all_zeros = 0; + for( i=0; i= zlimit) { + if (di->xml_format == 0) + printf("# end of range.\n"); + break; + } + if (z >= di->q) { + if (di->xml_format == 0) + printf("# end of text section.\n"); + break; + } + + /* if we get near the end of the section, clip the itext length */ + ilim = 15; + // we know z < di->q due to above if() statement. + if (z + ilim > di->q) { + // pointer diff is signed, but in this case guaranteed positive and <= ilim. + ilim = UCAST(di->q - z); + } + + if (CLIENT_VERBOSE3) + emit_dec_sep_msg(i); + + // if we get two full things of 0's in a row, start skipping. + if (all_zeros((xed_uint8_t*) z, ilim)) + { + if (skipping) { + z = z + ilim; + continue; + } + else if (last_all_zeros) { + printf("...\n"); + z = z + ilim; + skipping = 1; + continue; + } + else + last_all_zeros = 1; + } + else + { + skipping = 0; + last_all_zeros = 0; + } + + runtime_instruction_address = U64CAST(z-di->a) + + di->runtime_vaddr; + + if (CLIENT_VERBOSE3) + emit_addr_hex(runtime_instruction_address, z, ilim); + + okay = 0; + length = 0; + + init_xedd(&xedd, di); + + if ( di->decode_only ) + { + xed_uint64_t t1,t2; + xed_error_enum_t xed_error = XED_ERROR_NONE; + + t1 = xed_get_time(); + + //do the decode + xed_error = decode_internal( + &xedd, + XED_REINTERPRET_CAST(const xed_uint8_t*,z), + ilim); + + t2 = xed_get_time(); + + okay = (xed_error == XED_ERROR_NONE); +#if defined(PTI_XED_TEST) + if (okay) + pti_xed_test(&xedd, + XED_REINTERPRET_CAST(const xed_uint8_t*,z), + ilim, + runtime_instruction_address); +#endif + + xed_stats_update(&xed_dec_stats, t1, t2); + length = xed_decoded_inst_get_length(&xedd); + + if (okay && length == 0) + die_zero_len(runtime_instruction_address, z, di, xed_error); + + resync = check_resync(di, runtime_instruction_address, length, z); + if (resync) { + z += resync; + continue; + } + + xed_dec_stats.total_ilen += length; + +//we don't want to print out disassembly with ILD perf +#if !defined(XED_ILD_ONLY) && !defined(XED2_PERF_MEASURE) + + if (okay || xed_error == XED_ERROR_INVALID_FOR_CHIP) + { + // we still print it out if it is invalid for the chip. + // so that people can see the problematic instruction + emit_disasm(di, &xedd, + runtime_instruction_address, + z, gs, xed_error); + if (CLIENT_VERBOSE && gs) + graph_empty = 0; + } + + if (okay == 0) + { + errors++; + length = xed_decoded_inst_get_length(&xedd); + if (length == 0) + length = 1; + + xed_decode_error( runtime_instruction_address, + U64CAST(z-di->a), + z, + xed_error, + length); + + } // okay == 0 + } // decode_only + +# if defined(XED_ENCODER) && defined(XED_DECODER) + else // decode->encode + { + unsigned int olen = 0; + olen = disas_decode_encode_binary(di, + XED_REINTERPRET_CAST(const xed_uint8_t*,z), + ilim, + &xedd, + runtime_instruction_address); + + okay = (olen != 0); + if (!okay) { + errors++; + printf("-- Could not decode/encode at offset: " XED_FMT_LU "\n" , + U64CAST(z-di->a)); + // just give a length of 1B to see if we can restart decode... + length = 1; + } + else { + length = xed_decoded_inst_get_length(&xedd); + xed_dec_stats.total_ilen += length; + xed_dec_stats.total_olen += olen; + if (length > olen) + xed_dec_stats.total_shorter += (length - olen); + else + xed_dec_stats.total_longer += (olen - length); + } + } +# endif // XED_ENCODER & XED_DECODER +#endif //!defined(XED_ILD_ONLY) + + + z = z + length; + } //for i + + if (di->xml_format == 0) { + printf( "# Errors: " XED_FMT_LU "\n", errors); + } +finish: + + if (gs) { + if (graph_empty ==0 ) + xed_dot_graph_dump(di->dot_graph_output, gs); + xed_dot_graph_supp_deallocate(gs); + } + + di->errors += errors; +} +#endif + + +xed_uint8_t +convert_ascii_nibble(char c) +{ + if (c >= '0' && c <= '9') { + return letter_cvt(c,'0'); + } + else if (c >= 'a' && c <= 'f') { + return (xed_uint8_t)(letter_cvt(c,'a') + 10U); + } + else if (c >= 'A' && c <= 'F') { + return (xed_uint8_t)(letter_cvt(c,'A') + 10U); + } + else { + char buffer[XED_HEX_BUFLEN]; + char* x; + xed_strncpy(buffer,"Invalid character in hex string: ", XED_HEX_BUFLEN); + x= buffer+strlen(buffer); + *x++ = c; + *x++ = 0; + xedex_derror(buffer); + return 0; + } +} + + + +xed_uint64_t convert_ascii_hex_to_int(const char* s) { + xed_uint64_t retval = 0; + const char* p = s; + while (*p) { + retval = (retval << 4) + convert_ascii_nibble(*p); + p++; + } + return retval; +} + + +xed_uint8_t convert_ascii_nibbles(char c1, char c2) { + xed_uint8_t a = (xed_uint8_t)(convert_ascii_nibble(c1) * 16 + convert_ascii_nibble(c2)); + return a; +} + +unsigned int +xed_convert_ascii_to_hex(const char* src, xed_uint8_t* dst, + unsigned int max_bytes) +{ + unsigned int j; + unsigned int p = 0; + unsigned int i = 0; + + const unsigned int len = XED_STATIC_CAST(unsigned int,strlen(src)); + if ((len & 1) != 0) + xedex_derror("test string was not an even number of nibbles"); + + if (len > (max_bytes * 2) ) + xedex_derror("test string was too long"); + + for( j=0;j= '0' && c <= '9') + { + unsigned int digit = letter_cvt(c,'0'); + v = v*10 + digit; + } + else if (c == '_') /* skip underscores */ + continue; + else + { + break; + } + } + return v*sign; +} + +static xed_int64_t +convert_base16(const char* buf) +{ + xed_int64_t v = 0; + int len = XED_STATIC_CAST(int,strlen(buf)); + int start =0 ; + int i; + if (len > 2 && buf[0] == '0' && (buf[1] == 'x' || buf[1] == 'X')) + { + start = 2; + } + for(i=start;i= '0' && c <= '9') + { + unsigned int digit = letter_cvt(c, '0'); + v = v*16 + digit; + } + else if (c >= 'A' && c <= 'F') + { + unsigned int digit = letter_cvt(c,'A') + 10U; + v = v*16 + digit; + } + else if (c >= 'a' && c <= 'f') + { + unsigned int digit = letter_cvt(c,'a') + 10U; + v = v*16 + digit; + } + else if (c == '_') /* skip underscores */ + continue; + else + { + break; + } + } + return v; +} + +static xed_int64_t +xed_internal_strtoll(const char* buf, int base) +{ + switch(base) + { + case 0: + if (strlen(buf) > 2 && buf[0] == '0' && + (buf[1] == 'x' || buf[1] == 'X')) + { + return convert_base16(buf); + } + return convert_base10(buf); + case 10: + return convert_base10(buf); + case 16: + return convert_base16(buf); + default: + assert(0); + } + return 0; +} + + +xed_int64_t xed_strtoll(const char* buf, int base) +{ + xed_int64_t t; + // strtoll is missing on some compilers and buggy on some platforms + t = xed_internal_strtoll(buf,base); + return t; +} + +char* xed_strdup(char const* const src) { + unsigned int n = (unsigned int)strlen(src)+1; /* plus one for null */ + char* dst = (char*)malloc(n*sizeof(char)); + assert(dst != 0); + dst[0]=0; /* start w/ a null */ + xed_strncat(dst, src, ICAST(n)); + return dst; +} + +void xed_example_utils_init(void) { +#if defined(XED_DECODER) && defined (BINARY_DUMP) + open_binary_output_file(); +#endif +#if defined(XED_DECODER) && defined(XED_AVX) + init_interesting_avx(); +#endif +} + + +char const* xedex_append_string(char const* p, // p is free()'d + char const* x) +{ + char* m = 0; //returned pointer + char* n = 0; //temp ptr for copying + char const* t = 0; //temp ptr for copying + size_t tl = (p?strlen(p):0) + strlen(x) + 1; + m = n = (char*) malloc(tl); + assert(m!=0); + if (p) { + t = p; + while(*t) + *n++ = *t++; + } + + t = x; + while(*t) + *n++ = *t++; + *n++ = 0; // null terminate + if (p) + free((void*)p); + return m; +} + +//// +static xed_str_list_t* alloc_str_node(void) { + xed_str_list_t* p = (xed_str_list_t*)malloc(sizeof(xed_str_list_t)); + assert(p!=0); + return p; +} + +// MS does not have strsep() +static char* +portable_strsep(char** input_string, char const* const sep) +{ + char* p = *input_string; + if (p) { + // find token in input string + char* t = strpbrk(*input_string, sep); + if (t) { + *t = 0; // write a null at sep + *input_string = t+1; // advance pointer + return p; + } + // no token, just return input string + *input_string=0; // clear pointer + return p; + } + *input_string = 0; + return 0; +} + +xed_str_list_t* xed_tokenize(char const* const p, char const* const sep) +{ + // return a list of strings with their own storage for the tokens. if + // one were to free the list, one would have to just free the first + // token. The strsep() puts nulls in to a copy of the input string p + // replacing the delimiters. + + xed_str_list_t* head=0; + xed_str_list_t* last=0; + xed_str_list_t* cur=0; + char* token=0; + char* tmp_string=0; + + tmp_string = xed_strdup(p); + // puts a null in string at token and returns pointer to first token, + // updates tmp_string to point after null. + while(1) + { + token = portable_strsep(&tmp_string, sep); + if (!token) + break; + if (token[0]) // we know token is non-null + { + cur = alloc_str_node(); + if (!head) + head = cur; + cur->next = 0; + cur->s = token; + if (last) + last->next = cur; + last = cur; + } + } + return head; +} + + +xed_uint_t xed_str_list_size(xed_str_list_t* p) { //count chunks + unsigned int c = 0; + while(p) { + c++; + p = p->next; + } + return c; +} + +void xed_print_bytes_pseudo_op(const xed_uint8_t* array, unsigned int olen) { + unsigned int i; + printf(".byte "); + for(i=0;i0) + printf(","); + printf("0x%02x",(xed_uint32_t)(array[i])); + } + printf("\n"); +} + +void xed_print_intel_asm_emit(const xed_uint8_t* array, unsigned int olen) { + unsigned int i; + for(i=0;i +#include "xed/xed-interface.h" + +extern xed_syntax_enum_t global_syntax; +extern int client_verbose; + +#define CLIENT_VERBOSE (client_verbose > 1) +#define CLIENT_VERBOSE0 (client_verbose > 2) +#define CLIENT_VERBOSE1 (client_verbose > 3) +#define CLIENT_VERBOSE2 (client_verbose > 4) +#define CLIENT_VERBOSE3 (client_verbose > 5) + +char* xed_upcase_buf(char* s); + +/// Accepts K / M / G (or B) qualifiers ot multiply +xed_int64_t xed_atoi_general(char* buf, int mul); +xed_int64_t xed_atoi_hex(char* buf); + +/// Converts "112233" in to 0x112233 +xed_uint64_t convert_ascii_hex_to_int(const char* s); + + +unsigned int xed_convert_ascii_to_hex(const char* src, + xed_uint8_t* dst, + unsigned int max_bytes); + +#define XED_HEX_BUFLEN 200 +void xed_print_hex_line(char* buf, + const xed_uint8_t* array, + const unsigned int length, + const unsigned int buflen); + +void XED_NORETURN xedex_derror(const char* s); +void xedex_dwarn(const char* s); + +////////////////////////////////////////////////////////////////////// + + +typedef struct { + xed_state_t dstate; + xed_uint_t ninst; + xed_bool_t decode_only; + xed_bool_t sixty_four_bit; + xed_bool_t mpx_mode; + xed_bool_t cet_mode; + char* input_file_name; + char* symbol_search_path; // for dbghelp symbol caches + char* target_section; + xed_bool_t use_binary_mode; + xed_uint64_t addr_start; + xed_uint64_t addr_end; + xed_bool_t xml_format; + xed_uint64_t fake_base; + xed_bool_t resync; /* turn on/off symbol-based resynchronization */ + xed_bool_t line_numbers; /* control for printing file/line info */ + FILE* dot_graph_output; + unsigned int perf_tail_start; + xed_bool_t ast; + xed_bool_t histo; + xed_chip_enum_t chip; + xed_bool_t emit_isa_set; + xed_format_options_t format_options; + xed_operand_enum_t operand; + xed_uint32_t operand_value; + xed_bool_t encode_force; + + xed_uint64_t errors; + xed_uint64_t errors_chip_check; + + unsigned char* s; // start of image + unsigned char* a; // start of instructions to decode region + unsigned char* q; // end of region + // where this region would live at runtime + xed_uint64_t runtime_vaddr; + // where to start in program space, if not zero + xed_uint64_t runtime_vaddr_disas_start; + + // where to stop in program space, if not zero + xed_uint64_t runtime_vaddr_disas_end; + + // a function to convert addresses to symbols + char* (*symfn)(xed_uint64_t, void*); + void* caller_symbol_data; + + void (*line_number_info_fn)(xed_uint64_t addr); + +} xed_disas_info_t; + +void xed_disas_info_init(xed_disas_info_t* p); + +void xed_map_region(const char* path, + void** start, + unsigned int* length); + + + +void xed_disas_test(xed_disas_info_t* di); + + + +// returns 1 on success, 0 on failure +xed_uint_t disas_decode_binary(xed_disas_info_t* di, + const xed_uint8_t* hex_decode_text, + const unsigned int bytes, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address); + +// returns encode length on success, 0 on failure +xed_uint_t disas_decode_encode_binary(xed_disas_info_t* di, + const xed_uint8_t* decode_text_binary, + const unsigned int bytes, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address); + + +void xed_print_decode_stats(xed_disas_info_t* di); +void xed_print_encode_stats(xed_disas_info_t* di); + +void xed_register_disassembly_callback( + xed_disassembly_callback_fn_t f); + + +void disassemble(xed_disas_info_t* di, + char* buf, + int buflen, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_instruction_address, + void* caller_data); + +// 64b version missing on some MS compilers so I wrap it for portability. +// This function is rather limited and only handles base 10 and base 16. +xed_int64_t xed_strtoll(const char* buf, int base); + +char* xed_strdup(char const* const src); + +void xed_example_utils_init(void); + +void init_xedd(xed_decoded_inst_t* xedd, + xed_disas_info_t* di); + +char const* xedex_append_string(char const* p, // p is free()'d + char const* x); + +typedef struct xed_str_list_s { + char* s; + struct xed_str_list_s* next; +} xed_str_list_t; + +xed_str_list_t* xed_tokenize(char const* const p, char const* const sep); +xed_uint_t xed_str_list_size(xed_str_list_t* p); // counts chunks + +void xed_print_intel_asm_emit(const xed_uint8_t* array, unsigned int olen); +void xed_print_bytes_pseudo_op(const xed_uint8_t* array, unsigned int olen); +#endif // file diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-find-special.c b/CodeVirtualizer/build/obj/wkit/examples/xed-find-special.c new file mode 100644 index 0000000..af758c0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-find-special.c @@ -0,0 +1,92 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-tables.c +/// @brief a minimal example of accessing the XED internal tables + +#include +#include +#include "xed/xed-interface.h" +static char const* suffix_name(char const* s) { + char* p = strchr(s,'_'); + return p+1; +} + +typedef enum { + reptype_invalid, + reptype_rep, + reptype_repe, + reptype_repne +} reptype_enum_t; + +static reptype_enum_t get_reptype(char const* s) { + if (strncmp("REPNE",s,5) == 0) + return reptype_repne; + if (strncmp("REPE",s,4) == 0) + return reptype_repe; + if (strncmp("REP",s,3) == 0) + return reptype_rep; + return reptype_invalid; +} + +static char const* reptype_enum_t2str(reptype_enum_t r) { + switch(r) { + case reptype_repne: return "REPNE"; + case reptype_repe: return "REPE"; + case reptype_rep: return "REP"; + default: return "INVALID"; + } +} + +static void scan_inst(const xed_inst_t* p) { + xed_iclass_enum_t ic = xed_inst_iclass(p); + xed_category_enum_t cat = xed_inst_category(p); + if (xed_inst_get_attribute(p,XED_ATTRIBUTE_LOCKABLE)) { + char const* ics = xed_iclass_enum_t2str(ic); + printf("LOCKABLE %s\n", ics); + } + if (xed_inst_get_attribute(p,XED_ATTRIBUTE_REP)) { + char const* ics = xed_iclass_enum_t2str(ic); + reptype_enum_t rt = get_reptype(ics); + printf("REP* %s --> %s + %s\n", ics, reptype_enum_t2str(rt), suffix_name(ics)); + } + if (cat == XED_CATEGORY_STRINGOP || cat == XED_CATEGORY_IOSTRINGOP) { + char const* ics = xed_iclass_enum_t2str(ic); + printf("STRINGOP: %s\n", ics); + } + +} + +static void scan_insts(void) { + unsigned int i; + for(i=0;i + +int main(int argc, char** argv); + +int main(int argc, char** argv) { + xed_machine_mode_enum_t mmode; + xed_address_width_enum_t stack_addr_width; + xed_bool_t long_mode = 0; + // create the decoded instruction, and fill in the machine mode (dstate) + // make up a simple 2Byte instruction to decode + unsigned int bytes = 0; + unsigned char itext[15] = { 0xf, 0x85, 0x99, 0x00, 0x00, 0x00 }; + + // initialize the XED tables -- one time. + xed_tables_init(); + + // The state of the machine -- required for decoding + if (long_mode) { + mmode=XED_MACHINE_MODE_LONG_64; + stack_addr_width = XED_ADDRESS_WIDTH_64b; + } + else { + mmode=XED_MACHINE_MODE_LEGACY_32; + stack_addr_width = XED_ADDRESS_WIDTH_32b; + } + + // This is a test of error handling. I vary the instuction length from + // 0 bytes to 15 bytes. Normally, you should send in 15 bytes of itext + // unless you are near the end of a page and don't want to take a page + // fault or tlb miss. Note, you have to reinitialize the xedd each time + // you try to decode in to it. + + // Try different instruction lengths to see when XED recognizes an + // instruction as valid. + for(bytes = 0;bytes<=15;bytes++) { + xed_error_enum_t xed_error; + xed_decoded_inst_t xedd; + xed_decoded_inst_zero(&xedd); + xed_decoded_inst_set_mode(&xedd, mmode, stack_addr_width); + xed_error = xed_decode(&xedd, + XED_STATIC_CAST(const xed_uint8_t*,itext), + bytes); + printf("%d %s\n",(int)bytes, xed_error_enum_t2str(xed_error)); + } + return 0; + (void) argc; (void) argv; //pacify compiler +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-nm-symtab.c b/CodeVirtualizer/build/obj/wkit/examples/xed-nm-symtab.c new file mode 100644 index 0000000..9125651 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-nm-symtab.c @@ -0,0 +1,54 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include +#include +#include +#include "xed-symbol-table.h" +#include "xed-nm-symtab.h" + +xed_symbol_table_t nm_symtab; +xed_bool_t nm_symtab_init; + +void xed_read_nm_symtab(char *fn) +{ + char line[1024]; + FILE *f = fopen(fn, "r"); + if (!f) + return; + + xed_symbol_table_init(&nm_symtab); + nm_symtab_init = 1; + while (fgets(line, sizeof line, f)) { + unsigned long long adr; + char type, name[512+1]; + char *s; + + if (sscanf(line, "%llx %c %512s", &adr, &type, name) != 3) + continue; + s = malloc(strlen(name) + 1); + if (!s) + break; + strcpy(s, name); + xst_add_global_symbol( + &nm_symtab, + XED_STATIC_CAST(xed_uint64_t, adr), + s); + } + fclose(f); +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-nm-symtab.h b/CodeVirtualizer/build/obj/wkit/examples/xed-nm-symtab.h new file mode 100644 index 0000000..91ad716 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-nm-symtab.h @@ -0,0 +1,22 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +void xed_read_nm_symtab(char *fn); + +extern xed_symbol_table_t nm_symtab; +extern xed_bool_t nm_symtab_init; diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-rc-template.txt b/CodeVirtualizer/build/obj/wkit/examples/xed-rc-template.txt new file mode 100644 index 0000000..6130da2 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-rc-template.txt @@ -0,0 +1,25 @@ +1 VERSIONINFO +FILEFLAGSMASK 0x17L +FILEFLAGS 0x0L +FILEOS 0x4L +FILETYPE 0x1L +FILESUBTYPE 0x0L +BEGIN + BLOCK "StringFileInfo" + BEGIN + BLOCK "040904b0" + BEGIN + VALUE "CompanyName", "Intel Corporation" + VALUE "FileDescription", "Intel XED Executable" + VALUE "FileVersion", "" + VALUE "InternalName", "Intel XED Executable" + VALUE "LegalCopyright", "Copyright (C) 2002-%%YEAR%%, Intel Corporation. All rights reserved." + VALUE "ProductName", "Intel XED" + END + END + + BLOCK "VarFileInfo" + BEGIN + VALUE "Translation", 0x409, 1200 + END +END diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-reps.c b/CodeVirtualizer/build/obj/wkit/examples/xed-reps.c new file mode 100644 index 0000000..f8fa722 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-reps.c @@ -0,0 +1,107 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-min.c +/// @brief a minimal toy example of using the decoder. + +#include "xed/xed-interface.h" +#include + +int main(int argc, char** argv); + +int xtest(xed_iclass_enum_t a, xed_iclass_enum_t b) +{ + if (a != b) { + printf("MISMATCH: %s %s\n", + xed_iclass_enum_t2str(a), + xed_iclass_enum_t2str(b)); + return 1; + } + printf("MATCH: %s %s\n", + xed_iclass_enum_t2str(a), + xed_iclass_enum_t2str(b)); + return 0; +} + +int main(int argc, char** argv) +{ + xed_uint_t i=0; + int r=0; + + const xed_iclass_enum_t repe[] = { + XED_ICLASS_REPE_CMPSB, + XED_ICLASS_REPE_CMPSD, + XED_ICLASS_REPE_CMPSQ, + XED_ICLASS_REPE_CMPSW, + XED_ICLASS_REPE_SCASB, + XED_ICLASS_REPE_SCASD, + XED_ICLASS_REPE_SCASQ, + XED_ICLASS_REPE_SCASW, + XED_ICLASS_INVALID }; + const xed_iclass_enum_t repne[] = { + XED_ICLASS_REPNE_CMPSB, + XED_ICLASS_REPNE_CMPSD, + XED_ICLASS_REPNE_CMPSQ, + XED_ICLASS_REPNE_CMPSW, + XED_ICLASS_REPNE_SCASB, + XED_ICLASS_REPNE_SCASD, + XED_ICLASS_REPNE_SCASQ, + XED_ICLASS_REPNE_SCASW, + XED_ICLASS_INVALID }; + const xed_iclass_enum_t rep[] = { + XED_ICLASS_REP_INSB, + XED_ICLASS_REP_INSD, + XED_ICLASS_REP_INSW, + XED_ICLASS_REP_LODSB, + XED_ICLASS_REP_LODSD, + XED_ICLASS_REP_LODSQ, + XED_ICLASS_REP_LODSW, + XED_ICLASS_REP_MOVSB, + XED_ICLASS_REP_MOVSD, + XED_ICLASS_REP_MOVSQ, + XED_ICLASS_REP_MOVSW, + XED_ICLASS_REP_OUTSB, + XED_ICLASS_REP_OUTSD, + XED_ICLASS_REP_OUTSW, + XED_ICLASS_REP_STOSB, + XED_ICLASS_REP_STOSD, + XED_ICLASS_REP_STOSQ, + XED_ICLASS_REP_STOSW, + XED_ICLASS_INVALID }; + + + xed_tables_init(); + + for (i=0; repe[i]!=XED_ICLASS_INVALID; i++) { + xed_iclass_enum_t norep = xed_norep_map(repe[i]); + xed_iclass_enum_t xr = xed_repe_map(norep); + r |= xtest(repe[i],xr); + } + for (i=0; repne[i]!=XED_ICLASS_INVALID; i++) { + xed_iclass_enum_t norep = xed_norep_map(repne[i]); + xed_iclass_enum_t xr = xed_repne_map(norep); + r |= xtest(repne[i],xr); + } + for (i=0; rep[i]!=XED_ICLASS_INVALID; i++) { + xed_iclass_enum_t norep = xed_norep_map(rep[i]); + xed_iclass_enum_t xr = xed_rep_map(norep); + r |= xtest(rep[i],xr); + } + + return r; + (void) argc; (void) argv; //pacify compiler +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-size.c b/CodeVirtualizer/build/obj/wkit/examples/xed-size.c new file mode 100644 index 0000000..768e9b0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-size.c @@ -0,0 +1,34 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include "xed/xed-interface.h" +#include + +int main(int argc, char** argv); +int main(int argc, char** argv) { + /* I use this to keep track of the size of my per-instruction data structures */ + xed_decoded_inst_t x; + /*xed_tables_init(); */ + printf("xed_decoded_inst_t %12d\n", (int)sizeof(xed_decoded_inst_t)); + printf("xed_inst_t %12d\n", (int)sizeof(xed_inst_t)); + printf("xed_operand_t %12d\n", (int)sizeof(xed_operand_t)); + printf("xed_iform_info_t %12d\n", (int)sizeof(xed_iform_info_t)); + return 0; + (void) argc; (void) argv; //pacify compiler + (void) x; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-symbol-table.c b/CodeVirtualizer/build/obj/wkit/examples/xed-symbol-table.c new file mode 100644 index 0000000..485d54f --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-symbol-table.c @@ -0,0 +1,151 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#include +#include "xed/xed-interface.h" +#include "xed-examples-util.h" +#include "xed-symbol-table.h" + +////////////////////////////////////////////////////////////////////// +void xed_local_symbol_table_init(xed_local_symbol_table_t* p) +{ + avl_tree_init(&p->atree); +} + +void xed_symbol_table_init(xed_symbol_table_t* p) { + p->curtab = 0; + xed_local_symbol_table_init(&p->gtab); + avl_tree_init(&p->avl_lmap); +} + +xed_local_symbol_table_t* xst_get_local_map(xed_symbol_table_t* p, + xed_uint32_t section) +{ + xed_local_symbol_table_t* v = + (xed_local_symbol_table_t*) avl_find(&p->avl_lmap, section); + return v; +} + +xed_local_symbol_table_t* xst_make_local_map(xed_symbol_table_t* p, + xed_uint32_t section) +{ + xed_local_symbol_table_t* n = + (xed_local_symbol_table_t*) malloc(sizeof(xed_local_symbol_table_t)); + assert(n!=0); + xed_local_symbol_table_init(n); + avl_insert(&p->avl_lmap, section, n, 0); + return n; +} + +void xst_set_current_table(xed_symbol_table_t* p, + xed_uint32_t section) +{ + p->curtab = xst_get_local_map(p,section); +} + +void xst_add_local_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name, + xed_uint32_t section) +{ + xed_local_symbol_table_t* ltab = xst_get_local_map(p,section); + if (ltab == 0) + ltab = xst_make_local_map(p,section); + avl_insert(<ab->atree,addr, name, 0); +} + +void xst_add_global_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name) { + avl_insert(&p->gtab.atree,addr, name, 0); +} + + + +////////////////////////////////////////////////////////////////////// +static xed_bool_t +find_symbol_address(xed_local_symbol_table_t* ltab, + xed_uint64_t tgt, + xed_uint64_t* sym_addr) +{ + uint64_t lbkey=0; + void* sym = avl_find_lower_bound(<ab->atree, tgt, &lbkey); + if (sym) { + *sym_addr = lbkey; + return 1; + } + return 0; +} + +static xed_bool_t +find_symbol_address_global(xed_uint64_t tgt, + xed_symbol_table_t* symbol_table, + xed_uint64_t* sym_addr) /* output*/ +{ + xed_bool_t r = 0; + if (symbol_table) { + /* look global and then local */ + r = find_symbol_address(&symbol_table->gtab, tgt, sym_addr); + if (r == 0 && symbol_table->curtab) { + r = find_symbol_address(symbol_table->curtab, tgt, sym_addr); + } + } + return r; +} + + +char* get_symbol(xed_uint64_t a, void* caller_data) { + xed_symbol_table_t* symbol_table = (xed_symbol_table_t*)caller_data; + /* look in the global symbol table first */ + char* name = (char*)avl_find(&symbol_table->gtab.atree, a); + if (name) + return name; + /* look in the local symbol table if present */ + if (symbol_table->curtab) { + name = (char*)avl_find(&symbol_table->curtab->atree, a); + return name; + } + return 0; +} + + +int xed_disassembly_callback_function( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* caller_data) +{ + xed_uint64_t symbol_address; + xed_symbol_table_t* symbol_table = (xed_symbol_table_t*)caller_data; + xed_bool_t found = find_symbol_address_global(address, + symbol_table, + &symbol_address); + if (found) { + char* symbol = get_symbol(symbol_address, caller_data); + if (symbol) { + if (xed_strlen(symbol) < buffer_length) + xed_strncpy(symbol_buffer, symbol, (int)buffer_length); + else { + xed_strncpy(symbol_buffer, symbol, (int)(buffer_length-1)); + symbol_buffer[buffer_length-1]=0; + } + *offset = address - symbol_address; + return 1; + } + } + return 0; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-symbol-table.h b/CodeVirtualizer/build/obj/wkit/examples/xed-symbol-table.h new file mode 100644 index 0000000..731b4e4 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-symbol-table.h @@ -0,0 +1,70 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_SYMBOL_TABLE_H) +#define XED_SYMBOL_TABLE_H + +#include "xed/xed-interface.h" +#include "xed-examples-util.h" +#include "avltree.h" +#include + +typedef struct { + avl_tree_t atree; +} xed_local_symbol_table_t; + +void xed_local_symbol_table_init(xed_local_symbol_table_t* p); + +typedef struct { + xed_local_symbol_table_t gtab; + /* section number maps to a local symbol table */ + avl_tree_t avl_lmap; + /* the symbol table for the current section */ + xed_local_symbol_table_t* curtab; + +} xed_symbol_table_t; + +void xed_symbol_table_init(xed_symbol_table_t* p); + +xed_local_symbol_table_t* xst_get_local_map(xed_symbol_table_t* p, + xed_uint32_t section); + +xed_local_symbol_table_t* xst_make_local_map(xed_symbol_table_t* p, + xed_uint32_t section); + +void xst_set_current_table(xed_symbol_table_t* p, + xed_uint32_t section); + +void xst_add_local_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name, + xed_uint32_t section); + +void xst_add_global_symbol(xed_symbol_table_t* p, + xed_uint64_t addr, char* name); + +//////////////////////////////////////////////////////////////// + +char* get_symbol(xed_uint64_t a, void* symbol_table); + +int xed_disassembly_callback_function( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* caller_data); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed-tables.c b/CodeVirtualizer/build/obj/wkit/examples/xed-tables.c new file mode 100644 index 0000000..61f27e0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed-tables.c @@ -0,0 +1,93 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-tables.c +/// @brief a minimal example of accessing the XED internal tables + +#include +#include "xed/xed-interface.h" + + +void dump_operand(const xed_operand_t* op) { + printf("%s ", xed_operand_enum_t2str(xed_operand_name(op))); + printf("%s ", + xed_operand_visibility_enum_t2str(xed_operand_operand_visibility(op))); + printf("%s ", xed_operand_action_enum_t2str(xed_operand_rw(op))); + printf("%s ", xed_operand_type_enum_t2str(xed_operand_type(op))); + printf("%s ", xed_operand_element_xtype_enum_t2str(xed_operand_xtype(op))); + if (xed_operand_type(op) == XED_OPERAND_TYPE_NT_LOOKUP_FN) + printf("%s ", + xed_nonterminal_enum_t2str(xed_operand_nonterminal_name(op))); + if (xed_operand_type(op) == XED_OPERAND_TYPE_REG) + printf("%s ", xed_reg_enum_t2str(xed_operand_reg(op))); +} + + +void print_attributes(const xed_inst_t* xi) { + /* Walk the attributes. Generally, you'll know the one you want to + * query and just access that one directly. */ + + unsigned int i, nattributes = xed_attribute_max(); + + printf("ATTRIBUTES: "); + for(i=0;i + +int main(int argc, char** argv); + +typedef struct +{ + unsigned int len; + unsigned char itext[15]; +} xed_test_t; + +xed_test_t tests[] = { + { 2, { 0, 0 } }, + { 2, { 2, 0 } }, + { 2, { 0xF3, 0x90 } }, + { 0 } +}; + +int main(int argc, char** argv) { + unsigned int i,j; + xed_state_t dstate; + xed_tables_init(); + xed_state_zero(&dstate); + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_32, + XED_ADDRESS_WIDTH_32b, + XED_ADDRESS_WIDTH_32b); + for ( i=0; tests[i].len ; i++) { + xed_bool_t okay; + xed_error_enum_t xed_error; + xed_decoded_inst_t xedd; + xed_decoded_inst_zero_set_mode(&xedd, &dstate); + printf("Testing: "); + for( j=0; j< tests[i].len; j++) + printf("%02x ",XED_STATIC_CAST(unsigned int,tests[i].itext[j])); + printf("\n"); + + xed_error = xed_decode(&xedd, + XED_REINTERPRET_CAST(xed_uint8_t*,tests[i].itext), + tests[i].len); + + okay = (xed_error == XED_ERROR_NONE); + if (okay) { + printf("OK\n"); + } + } + (void) argc; (void) argv; //pacify compiler + return 0; +} diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed.c b/CodeVirtualizer/build/obj/wkit/examples/xed.c new file mode 100644 index 0000000..a0ce3e4 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed.c @@ -0,0 +1,949 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed.c + + +//////////////////////////////////////////////////////////////////////////// + +#include "xed/xed-interface.h" +#include "xed/xed-immdis.h" +#include "xed-examples-util.h" +#if defined(XED_ENCODER) +# include "xed-enc-lang.h" +#endif +#include "xed-disas-elf.h" +#include "xed-disas-macho.h" +#include "xed-disas-raw.h" +#include "xed-disas-hex.h" +#include "xed-disas-pecoff.h" +#include "xed-disas-filter.h" +#include "xed-symbol-table.h" +#include "xed-nm-symtab.h" + +#include +#include +#include +#include + +int main(int argc, char** argv); +static int intel_asm_emit = 0; + +//////////////////////////////////////////////////////////////////////////// +#if defined(XED_DECODER) +static xed_uint_t disas_decode( xed_disas_info_t* di, + const char* decode_text, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address) +{ + xed_uint8_t hex_decode_text[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t bytes = xed_convert_ascii_to_hex(decode_text, + hex_decode_text, + XED_MAX_INSTRUCTION_BYTES); + return disas_decode_binary(di, + hex_decode_text, + bytes, + xedd, + runtime_address); +} +#endif + +#if defined(XED_DECODER) && defined(XED_ENCODER) +static unsigned int disas_decode_encode(xed_disas_info_t* di, + const char* decode_text, + xed_decoded_inst_t* xedd, + xed_uint64_t runtime_address) +{ + xed_uint8_t hex_decode_text[XED_MAX_INSTRUCTION_BYTES]; + xed_uint_t bytes = xed_convert_ascii_to_hex( decode_text, + hex_decode_text, + XED_MAX_INSTRUCTION_BYTES); + return disas_decode_encode_binary(di, + hex_decode_text, + bytes, + xedd, + runtime_address); +} +#endif + +static FILE* +fopen_portable(char const* const file_name, + char const* const mode) +{ + FILE* f = 0; +#if defined(XED_WINDOWS) && !defined(PIN_CRT) + errno_t error = fopen_s(&f, file_name, mode); + if (error != 0) + return 0; +#else + f = fopen(file_name, mode); +#endif + return f; +} + + + +#if defined(XED_ENCODER) + +static unsigned int disas_encode(const xed_state_t* dstate, + const char* encode_text, + xed_operand_enum_t operand, + xed_uint32_t operand_value, + xed_bool_t encode_force) +{ + char buf[5000]; + xed_uint8_t array[XED_MAX_INSTRUCTION_BYTES]; + unsigned int ilen = XED_MAX_INSTRUCTION_BYTES; + unsigned int olen=0; + ascii_encode_request_t areq; + xed_encoder_request_t req; + xed_error_enum_t r; + + areq.dstate = *dstate; + areq.command = encode_text; + req = parse_encode_request(areq); + + if (operand != XED_OPERAND_INVALID) + xed3_set_generic_operand(&req, operand, operand_value); + + xed3_operand_set_encode_force(&req, encode_force); + + xed_encode_request_print(&req, buf, 5000); + printf("Request: %s", buf); + + r = xed_encode(&req, array, ilen, &olen); + if (r != XED_ERROR_NONE) { + printf("Could not encode: %s\n", encode_text); + printf("Error code was: %s\n", xed_error_enum_t2str(r)); + xedex_derror("Dying"); + } + else if (CLIENT_VERBOSE) { + char buf2[XED_HEX_BUFLEN]; + xed_print_hex_line(buf2,array, olen,XED_HEX_BUFLEN); + printf("Encodable! %s\n", buf2); + if (intel_asm_emit) + xed_print_intel_asm_emit(array,olen); + else + xed_print_bytes_pseudo_op(array,olen); + } + return olen; +} + +static void no_comments(char* buf) { + size_t i, len = strlen(buf); + for(i=0;i 0) + printf(", "); + printf("0x%02x",array[i]); + } + printf("\n"); + } + fclose(f); +} +#endif + +static void emit_version(void) { + printf("%s\n", xed_get_copyright()); + printf("XED version: [%s]\n\n", xed_get_version()); +} + +static void usage(char* prog) { + unsigned int i; + static const char* usage_msg[] = { + "One of the following is required:", +#if defined(__APPLE__) + "\t-i input_file (decode macho-format file)", +#elif defined(XED_ELF_READER) + "\t-i input_file (decode elf-format file)", +#elif defined(_WIN32) + "\t-i input_file (decode pecoff-format file)", +#endif + "\t-ir raw_input_file (decode a raw unformatted binary file)", + "\t-ih hex_input_file (decode a raw unformatted ASCII hex file)", + "\t-d hex-string (decode a sequence of bytes, must be last)", + "\t-j (just decode one instruction when using -d)", + "\t-F prefix (decode ascii hex bytes after prefix)", + "\t (running in filter mode from stdin)", +#if defined(XED_ENCODER) + "\t-ide input_file (decode/encode file)", + "\t-e instruction (encode, must be last)", + "\t-f (encode force, skip encoder chip check)", + "\t-ie file-to-assemble (assemble the contents of the file)", + "\t-de hex-string (decode-then-encode, must be last)", +#endif + "", + "Optional arguments:", + "", + "\t-v N (0=quiet, 1=errors, 2=useful-info, 3=trace,", + "\t 5=very verbose)", + "\t-xv N (XED engine verbosity, 0...99)", + "", + "\t-chip-check CHIP (count instructions that are not valid for CHIP)", + "\t-chip-check-list (list the valid chips)", + "", + "\t-s section (target section for file disassembly,", + "\t PECOFF and ELF formats only)", + "", + "\t-n N (number of instructions to decode. Default 100M,", + "\t accepts K/M/G qualifiers)", + " ", + "\t-b addr (Base address offset, for DLLs/shared libraries.", + "\t Use 0x for hex addresses)", + "\t-as addr (Address to start disassembling.", + "\t Use 0x for hex addresses)", + "\t-ae addr (Address to end disassembling.", + "\t Use 0x for hex addresses)", + "\t-no-resync (Disable symbol-based resynchronization algorithm", + "\t for disassembly)", + "\t-ast (Show the AVX/SSE transition classfication)", + "\t-histo (Histogram decode times)", + "", + "\t-I (Intel syntax for disassembly)", + "\t-A (ATT SYSV syntax for disassembly)", + "\t-isa-set (Emit the XED \"ISA set\" in dissasembly)", + "\t-xml (XML formatting)", + "\t-uc (upper case hex formatting)", + "\t-pmd (positive memory displacement formatting)", + "\t-nwm (Format AVX512 without curly braces for writemasks, include k0)", + "\t-emit (Output __emit statements for the Intel compiler)", + "\t-S file Read symbol table in \"nm\" format from file", +#if defined(XED_DWARF) + "\t-line (Emit line number information, if present)", +#endif + "\t-dot FN (Emit a register dependence graph file in dot format.", + "\t Best used with -as ADDR -ae ADDR to limit graph size.)", + "", + "\t-r (for REAL_16 mode, 16b addressing (20b addresses),", + "\t 16b default data size)", + "\t-r32 (for REAL_32 mode, 16b addressing (20b addresses),", + "\t 32b default data size)", + "\t-16 (for LEGACY_16 mode, 16b addressing,", + "\t 16b default data size)", + "\t-32 (for LEGACY_32 mode, 32b addressing,", + "\t 32b default data size -- default)", + "\t-64 (for LONG_64 mode w/64b addressing", + "\t Optional on windows/linux)", +#if defined(XED_MPX) + "\t-mpx (Turn on MPX mode for disassembly, default is off)", +#endif +#if defined(XED_CET) + "\t-cet (Turn on CET mode for disassembly, default is off)", +#endif + "\t-s32 (32b stack addressing, default, not in LONG_64 mode)", + "\t-s16 (16b stack addressing, not in LONG_64 mode)", + "\t-set OP VAL (Set a XED operand to some integer value)", + +#if defined(XED_USING_DEBUG_HELP) + "", + "\t-sp (Search path for windows symbols)", +#endif + "\t-version (The version message)", + "\t-help (This help message)", + " ", + 0 + }; + + emit_version(); + printf("Usage: %s [options]\n", prog); + for(i=0; usage_msg[i] ; i++) + printf("%s\n", usage_msg[i]); +} + + + +static char const* remove_spaces(char const* s) { //frees original string + xed_uint32_t i=0,c=0; + char* p=0; + + if (s == 0) + return 0; + + while(s[i]) { + if (s[i] != ' ') + c++; + i++; + } + c++; // add the null + p = (char*)malloc(c); + assert(p!=0); + i=0; + c=0; + while(s[i]) { + if (s[i] != ' ') + p[c++] = s[i]; + i++; + } + p[c]=0; + free((void*)s); + + return p; +} + + +static void +test_argc(int i, int argc) +{ + if (i+1 >= argc) + xedex_derror("Need more arguments. Use \"xed -help\" for usage."); +} + + + + +static void list_chips(void) +{ + xed_chip_enum_t c = XED_CHIP_INVALID; + int i=0; + for( ; c < XED_CHIP_LAST; i++ ) { + if (i > 0 && (i % 3) == 0) + printf("\n"); + printf("%-25s ", xed_chip_enum_t2str(c)); + c = (xed_chip_enum_t)(c + 1); + } + printf("\n"); +} + + +int +main(int argc, char** argv) +{ + xed_bool_t sixty_four_bit = 0; + xed_bool_t mpx_mode = 0; + xed_bool_t cet_mode = 0; + xed_bool_t decode_only = 1; + char* input_file_name = 0; + char* symbol_search_path = 0; + char const* decode_text=0; + char const* encode_text=0; + xed_state_t dstate; + xed_bool_t encode = 0; + xed_bool_t encode_force = 0; + xed_uint_t ninst = 100*1000*1000; // FIXME: should use maxint... + //perf_tail is for skipping first insts in performance measure mode + unsigned int perf_tail = 0; + xed_bool_t decode_encode = 0; + int i,j; + unsigned int loop_decode = 0; + xed_bool_t decode_raw = 0; + xed_bool_t decode_hex = 0; + xed_bool_t assemble = 0; + char* target_section = 0; + xed_bool_t use_binary_mode = 1; + xed_bool_t emit_isa_set = 0; + xed_uint64_t addr_start = 0; + xed_uint64_t addr_end = 0; + xed_uint64_t fake_base = 0; + xed_bool_t xml_format =0; + xed_bool_t resync = 0; + xed_bool_t ast = 0; + xed_bool_t histo = 0; + xed_bool_t line_numbers = 0; + xed_chip_enum_t xed_chip = XED_CHIP_INVALID; + xed_operand_enum_t operand = XED_OPERAND_INVALID; + xed_uint32_t operand_value = 0; + xed_bool_t filter = 0; + xed_bool_t just_decode_first_pattern=0; +#if defined(XED_LINUX) + char *prefix = NULL; +#endif + + char* dot_output_file_name = 0; + xed_bool_t dot = 0; + xed_decoded_inst_t xedd; + xed_uint_t retval_okay = 1; + unsigned int obytes=0; +#if defined(XED_DECODER) + xed_disas_info_t decode_info; +#endif +#if defined(XED_LINUX) + char *nm_symtab_fn = NULL; +#endif + + /* I have this here to test the functionality, if you are happy with + * the XED formatting options, then you do not need to set this or call + * xed_format_set_options() */ + + xed_format_options_t format_options; + memset(&format_options,0,sizeof(xed_format_options_t)); +#if defined(XED_NO_HEX_BEFORE_SYMBOLIC_NAMES) + format_options.hex_address_before_symbolic_name=0; +#else + format_options.hex_address_before_symbolic_name=1; +#endif + format_options.write_mask_curly_k0 = 1; + format_options.lowercase_hex = 1; + + xed_example_utils_init(); + + xed_state_init(&dstate, + XED_MACHINE_MODE_LEGACY_32, + XED_ADDRESS_WIDTH_32b, /* 2nd parameter ignored */ + XED_ADDRESS_WIDTH_32b); + + resync = 1; + client_verbose = 3; + xed_set_verbosity( client_verbose ); + for( i=1; i < argc ; i++ ) { +#if defined(XED_LINUX) + if (strcmp(argv[i], "-F") == 0) { + test_argc(i, argc); + filter = 1; + prefix = argv[++i]; + continue; + } else if (strcmp(argv[i], "-S") == 0) { + test_argc(i, argc); + nm_symtab_fn = argv[++i]; + continue; + } +#endif + if (strcmp(argv[i], "-no-resync") ==0) { + resync = 0; + continue; + } + if (strcmp(argv[i], "-ast") ==0) { + ast = 1; + continue; + } + if (strcmp(argv[i], "-histo") ==0) { + histo = 1; + continue; + } + else if (strcmp(argv[i],"-d")==0) { + test_argc(i,argc); + for(j=i+1; j< argc;j++) + decode_text = xedex_append_string(decode_text,argv[j]); + break; // leave the i=1...argc loop + } + else if (strcmp(argv[i],"-j")==0) { + just_decode_first_pattern=1; + continue; + } + else if (strcmp(argv[i],"-i")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + i++; + } +#if defined(XED_USING_DEBUG_HELP) + else if (strcmp(argv[i],"-sp")==0) { + test_argc(i,argc); + symbol_search_path = argv[i+1]; + i++; + } +#endif + else if (strcmp(argv[i],"-s")==0) { + test_argc(i,argc); + target_section = argv[i+1]; + i++; + } + else if (strcmp(argv[i],"-xml")==0) { + format_options.xml_a = 1; + format_options.xml_f = 1; + xml_format = 1; + } + else if (strcmp(argv[i],"-pmd")==0) { + format_options.positive_memory_displacements=1; + } + else if (strcmp(argv[i],"-uc")==0) { + format_options.lowercase_hex = 0; // use uppercase hex + } + else if (strcmp(argv[i],"-nwm")==0) { + format_options.write_mask_curly_k0 = 0; + } +#if defined(XED_DWARF) + else if (strcmp(argv[i],"-line")==0) { + line_numbers = 1; + } +#endif + else if (strcmp(argv[i],"-dot")==0) { + test_argc(i,argc); + dot_output_file_name = argv[i+1]; + dot = 1; + i++; + } + else if (strcmp(argv[i],"-ir")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + decode_raw = 1; + i++; + } + else if (strcmp(argv[i],"-ih")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + decode_hex = 1; + i++; + } +#if defined(XED_ENCODER) + else if (strcmp(argv[i],"-f") == 0) { + encode_force = 1; + continue; + } + else if (strcmp(argv[i],"-e") == 0) { + encode = 1; + test_argc(i,argc); + // merge the rest of the args in to the encode_text string. + for( j = i+1; j< argc; j++ ) { + encode_text = xedex_append_string(encode_text, argv[j]); + encode_text = xedex_append_string(encode_text, " "); + } + break; // leave the loop + } + else if (strcmp(argv[i],"-de")==0) { + test_argc(i,argc); + decode_encode = 1; + for(j=i+1; j< argc;j++) + decode_text = xedex_append_string(decode_text,argv[j]); + break; // leave the i=1...argc loop + } + else if (strcmp(argv[i],"-ie")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + assemble = 1; + i++; + } + else if (strcmp(argv[i],"-ide")==0) { + test_argc(i,argc); + input_file_name = argv[i+1]; + decode_only = 0; + i++; + } +#endif + else if (strcmp(argv[i],"-n") ==0) { + test_argc(i,argc); + ninst = XED_STATIC_CAST(xed_uint_t, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-perftail") ==0) { + // undocumented. not an interesting knob for most users. + test_argc(i,argc); + perf_tail = XED_STATIC_CAST(unsigned int, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-b") ==0) { + test_argc(i,argc); + fake_base = (xed_uint64_t)xed_atoi_general(argv[i+1],1000); + printf("ASSUMED BASE = " XED_FMT_LX "\n",fake_base); + i++; + } + else if (strcmp(argv[i],"-as") == 0 || strcmp(argv[i],"-sa") == 0) { + test_argc(i,argc); + addr_start = XED_STATIC_CAST(xed_uint64_t, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-ae") == 0 || strcmp(argv[i],"-ea") == 0) { + test_argc(i,argc); + addr_end = XED_STATIC_CAST(xed_uint64_t, + xed_atoi_general(argv[i+1],1000)); + i++; + } + + else if (strcmp(argv[i],"-loop") ==0) { + test_argc(i,argc); + loop_decode = XED_STATIC_CAST(unsigned int, + xed_atoi_general(argv[i+1],1000)); + i++; + } + else if (strcmp(argv[i],"-v") ==0) { + test_argc(i,argc); + client_verbose = XED_STATIC_CAST(int,xed_atoi_general(argv[i+1],1000)); + xed_set_verbosity(client_verbose); + + i++; + } + else if (strcmp(argv[i],"-xv") ==0) { + int xed_engine_verbose; + test_argc(i,argc); + xed_engine_verbose = XED_STATIC_CAST(xed_int_t, + xed_atoi_general(argv[i+1],1000)); + xed_set_verbosity(xed_engine_verbose); + i++; + } + else if (strcmp(argv[i],"-chip-check")==0) { + test_argc(i,argc); + xed_chip = str2xed_chip_enum_t(argv[i+1]); + printf("Setting chip to %s\n", xed_chip_enum_t2str(xed_chip)); + if (xed_chip == XED_CHIP_INVALID) { + printf("Invalid chip name specified. Use -chip-check-list to " + "see the valid chip names.\n"); + exit(1); + } + i++; + } + else if (strcmp(argv[i],"-chip-check-list")==0) { + list_chips(); + exit(0); + } + else if (strcmp(argv[i],"-A")==0) { + global_syntax = XED_SYNTAX_ATT; + } + else if (strcmp(argv[i],"-I")==0) { + global_syntax = XED_SYNTAX_INTEL; + } + else if (strcmp(argv[i],"-X")==0) { // undocumented + global_syntax = XED_SYNTAX_XED; + } + else if (strcmp(argv[i],"-isa-set")==0) { + emit_isa_set = 1; + } + else if (strcmp(argv[i],"-r32")==0) { + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_REAL_32; + dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-r")==0) { + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_REAL_16; + dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-16")==0) { + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_LEGACY_16; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-32")==0) { // default + sixty_four_bit = 0; + dstate.mmode = XED_MACHINE_MODE_LEGACY_32; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-64")==0) { + sixty_four_bit = 1; + dstate.mmode = XED_MACHINE_MODE_LONG_64; + use_binary_mode = 0; + } +#if defined(XED_MPX) + else if (strcmp(argv[i],"-mpx")==0) { + mpx_mode = 1; + } +#endif +#if defined(XED_CET) + else if (strcmp(argv[i],"-cet")==0) { + cet_mode = 1; + } +#endif + else if (strcmp(argv[i],"-s32")==0) { + dstate.stack_addr_width = XED_ADDRESS_WIDTH_32b; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-s16")==0) { + dstate.stack_addr_width = XED_ADDRESS_WIDTH_16b; + use_binary_mode = 0; + } + else if (strcmp(argv[i],"-set")==0) { + test_argc(i+1,argc); // need 2 args + operand = str2xed_operand_enum_t(argv[i+1]); + operand_value = XED_STATIC_CAST(xed_uint32_t, + xed_atoi_general(argv[i+2],1000)); + i += 2; + } +#if 0 + else if (strcmp(argv[i],"-ti") ==0) { + client_verbose = 5; + xed_set_verbosity(5); + test_immdis(); + exit(1); + } +#endif + else if (strcmp(argv[i],"-emit") ==0) { + intel_asm_emit = 1; + } + else if (strcmp(argv[i],"-version") == 0 ) { + emit_version(); + exit(0); + } + else { + usage(argv[0]); + exit(1); + } + } + if (!encode) { + if (input_file_name == 0 && + (decode_text == 0 || + strlen(decode_text) == 0) && !filter) + { + printf("ERROR: required argument(s) were missing\n"); + usage(argv[0]); + exit(1); + } + } + +#if defined(XED_LINUX) + if (nm_symtab_fn) { + if (!filter) { + printf("ERROR: -S only support with -F for now\n"); + exit(1); + } + xed_read_nm_symtab(nm_symtab_fn); + } +#endif + + if (CLIENT_VERBOSE2) + printf("Initializing XED tables...\n"); + + xed_tables_init(); + + if (CLIENT_VERBOSE2) + printf("Done initialing XED tables.\n"); + + if (decode_text) { + decode_text = remove_spaces(decode_text); + assert(decode_text); + } + +#if defined(XED_DECODER) + xed_format_set_options(format_options); +#endif + + if (CLIENT_VERBOSE1) + printf("#XED version: [%s]\n", xed_get_version()); + + retval_okay = 1; + obytes=0; + +#if defined(XED_DECODER) + xed_disas_info_init(&decode_info); + decode_info.input_file_name = input_file_name; + decode_info.symbol_search_path = symbol_search_path; + decode_info.dstate = dstate; + decode_info.ninst = ninst; + decode_info.decode_only = decode_only; + decode_info.sixty_four_bit = sixty_four_bit; + decode_info.target_section = target_section; + decode_info.use_binary_mode = use_binary_mode; + decode_info.addr_start = addr_start; + decode_info.addr_end = addr_end; + decode_info.xml_format = xml_format; + decode_info.fake_base = fake_base; + decode_info.resync = resync; + decode_info.line_numbers = line_numbers; + decode_info.perf_tail_start = perf_tail; + decode_info.ast = ast; + decode_info.histo = histo; + decode_info.chip = xed_chip; + decode_info.mpx_mode = mpx_mode; + decode_info.cet_mode = cet_mode; + decode_info.emit_isa_set = emit_isa_set; + decode_info.format_options = format_options; + decode_info.operand = operand; + decode_info.operand_value = operand_value; + decode_info.encode_force = encode_force; + + if (dot) + { + decode_info.dot_graph_output = fopen_portable(dot_output_file_name,"w"); + if (!decode_info.dot_graph_output) { + printf("Could not open %s\n", dot_output_file_name); + xedex_derror("Dying"); + } + } + + init_xedd(&xedd, &decode_info); + +#endif + +#if defined(XED_LINUX) + if (filter) + { +#if defined(XED_DECODER) + retval_okay = disas_filter(&xedd, prefix, &decode_info); +#endif + } else +#endif + + if (assemble) + { +#if defined(XED_ENCODER) + xed_assemble(&dstate, input_file_name); +#endif + } + else if (decode_encode) + { +#if defined(XED_DECODER) && defined(XED_ENCODER) + assert(decode_text); + obytes = disas_decode_encode(&decode_info, + decode_text, + &xedd, + fake_base); +#endif + retval_okay = (obytes != 0) ? 1 : 0; + } + else if (encode) + { +#if defined(XED_ENCODER) + assert(encode_text != 0); + obytes = disas_encode(&dstate, + encode_text, + operand, + operand_value, + encode_force); +#endif + } + else if (decode_text && strlen(decode_text) != 0) + { +#if defined(XED_DECODER) + if (loop_decode) + { + unsigned int k; + for(k=0;k 0); + } +#endif + } + else + { +#if defined(XED_DECODER) + if (xml_format) { + printf("\n"); + printf("\n"); + printf("1\n"); + } + if (decode_raw) { + xed_disas_raw(&decode_info); + } + else if (decode_hex) { + xed_disas_hex(&decode_info); + } + else + { +#if defined(__APPLE__) + xed_disas_macho(&decode_info); +#elif defined(XED_ELF_READER) + xed_disas_elf(&decode_info); +#elif defined(_WIN32) + xed_disas_pecoff(&decode_info); +#else + xedex_derror("No PECOFF, ELF or MACHO support compiled in"); +#endif + printf("# Total Errors: " XED_FMT_LU "\n", decode_info.errors); + if (decode_info.chip) + printf("# Total Chip Check Errors: " XED_FMT_LU "\n", + decode_info.errors_chip_check); + } +#endif // XED_DECODER + } + + if (xml_format) + printf("\n"); + + + if (retval_okay==0) + exit(1); + return 0; + (void) obytes; + (void) encode_text; +#if !defined(XED_DECODER) + // pacify the compiler for encoder-only builds: + (void) xedd; + (void) sixty_four_bit; + (void) decode_only; + (void) symbol_search_path; + (void) ninst; + (void) perf_tail; + (void) loop_decode; + (void) decode_raw; + (void) decode_hex; + (void) target_section; + (void) addr_start; + (void) addr_end; + (void) resync; + (void) ast; + (void) histo; + (void) line_numbers; + (void) dot_output_file_name; + (void) dot; + (void) use_binary_mode; + (void) emit_isa_set; +#endif +} + + +//////////////////////////////////////////////////////////////////////////// diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed_build_common.py b/CodeVirtualizer/build/obj/wkit/examples/xed_build_common.py new file mode 100644 index 0000000..2443f1d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed_build_common.py @@ -0,0 +1,608 @@ +#!/usr/bin/env python +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +from __future__ import print_function +import sys +import os +import re +import shutil +import copy +import time +import types +import optparse +import mbuild + +############################################################################ +class xed_exception_t(Exception): + def __init__(self,kind,value,msg=""): + self.kind = kind + self.value = value + self.msg = msg + def __str__(self): + return "KIND: %s VALUE: %d MSG: %s" % (kind, value, msg) + +def handle_exception_and_die(e): + if hasattr(e,'kind'): + if e.kind == 'die': + sys.stderr.write('ABORT: ' + e.msg + '\n') + sys.exit(e.value) + elif e.kind == 'exit': + sys.stderr.write('EXITING\n') + sys.exit(e.value) + else: + print(str(e)) + sys.exit(1) + +def cdie(s): + raise xed_exception_t("die", 1, s) +def cexit(r=0): + raise xed_exception_t("exit", r) + +def write_file(fn, stream): + """Write stream to fn""" + mbuild.vmsgb(1, "WRITING", fn) + f = open(fn,'w') + f.writelines(stream) + f.close() + +def add_to_flags(env,s): + env.add_to_var('CCFLAGS',s) + env.add_to_var('CXXFLAGS',s) + +def compile_with_pin_crt_lin_mac_common_cplusplus(env): + env.add_to_var('LINKFLAGS','-lstlport-dynamic') + env.add_to_var('CXXFLAGS','-fno-exceptions') + env.add_to_var('CXXFLAGS', '-fno-rtti') + +def _compile_with_pin_crt_lin_mac_common(env): + env.add_system_include_dir('%(pin_root)s/extras/stlport/include') + env.add_system_include_dir('%(pin_root)s/extras/libstdc++/include') + env.add_system_include_dir('%(pin_root)s/extras/crt/include') + env.add_system_include_dir( + '%(pin_root)s/extras/crt/include/arch-%(bionic_arch)s') + env.add_system_include_dir( + '%(pin_root)s/extras/crt/include/kernel/uapi') + env.add_system_include_dir( + '%(pin_root)s/extras/crt/include/kernel/uapi/asm-x86') + + env.add_to_var('LINKFLAGS','-nostdlib') + env.add_to_var('LINKFLAGS','-lc-dynamic') + env.add_to_var('LINKFLAGS','-lm-dynamic') + env.add_to_var('LINKFLAGS','-L%(pin_crt_dir)s') + + # FIXME: if we ever support kits with Pin CRT, we'll need to copy + # the PINCRT to the XED kit and use a different rpath. + env.add_to_var('example_linkflags','-Wl,-rpath,%(pin_crt_dir)s') + + # -lpin3dwarf FIXME + + if env['shared']: + # when building dynamic library + env['first_lib'] = '%(pin_crt_dir)s/crtbeginS%(OBJEXT)s' + env['first_example_lib'] = '%(pin_crt_dir)s/crtbegin%(OBJEXT)s' + + _add_to_flags(env,'-funwind-tables') + +def _compile_with_pin_crt_lin(env): + _compile_with_pin_crt_lin_mac_common(env) + env.add_define('TARGET_LINUX') + if env['shared']: + env['last_lib'] = '%(pin_crt_dir)s/crtendS%(OBJEXT)s' + env['last_example_lib'] = '%(pin_crt_dir)s/crtend%(OBJEXT)s' + +def _compile_with_pin_crt_mac(env): + _compile_with_pin_crt_lin_mac_common(env) + env.add_define('TARGET_MAC') + env.add_to_var('LINKFLAGS','-Wl,-no_new_main') + +def _compile_with_pin_crt_win(env): + env.add_include_dir('%(pin_root)s/extras/stlport/include') + env.add_include_dir('%(pin_root)s/extras') + env.add_include_dir('%(pin_root)s/extras/libstdc++/include') + env.add_include_dir('%(pin_root)s/extras/crt/include') + env.add_include_dir('%(pin_root)s/extras/crt') + env.add_include_dir('%(pin_root)s/extras/crt/include/arch-%(bionic_arch)s') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi/asm-x86') + + env.add_to_var('LINKFLAGS','/NODEFAULTLIB') + env.add_to_var('LINKFLAGS','stlport-static.lib') + env.add_to_var('LINKFLAGS','m-static.lib') + env.add_to_var('LINKFLAGS','c-static.lib') + env.add_to_var('LINKFLAGS','os-apis.lib') + env.add_to_var('LINKFLAGS','ntdll-%(arch)s.lib') + env.add_to_var('LINKFLAGS','/IGNORE:4210') + env.add_to_var('LINKFLAGS','/IGNORE:4049') + env.add_to_var('LINKFLAGS','/LIBPATH:%(pin_crt_dir)s') + env.add_to_var('LINKFLAGS','/LIBPATH:%(pin_root)s/%(pin_arch)s/lib-ext') + + # for DLLs + if env['shared']: + env['first_lib'] = '%(pin_crt_dir)s/crtbeginS%(OBJEXT)s' + + # for EXEs + env['first_example_lib'] = '%(pin_crt_dir)s/crtbegin%(OBJEXT)s' + + _add_to_flags(env,'/GR-') + _add_to_flags(env,'/GS-') + + env['original_windows_h_path'] = mbuild.join( + os.environ['WindowsSdkDir'], 'Include','um') + env.add_define('_WINDOWS_H_PATH_="%(original_windows_h_path)s"') + _add_to_flags(env,'/FIinclude/msvc_compat.h') + env.add_define('TARGET_WINDOWS') + +def _compile_with_pin_crt(env): + if env['arch'] == '32': + env['pin_arch'] = 'ia32' + env['bionic_arch'] = 'x86' + env.add_define('TARGET_IA32') + else: + env['pin_arch'] = 'intel64' + env['bionic_arch'] = 'x86_64' + env.add_define('TARGET_IA32E') + + env['pin_root'] = env['pin_crt'] + env['pin_crt_dir'] = '%(pin_root)s/%(pin_arch)s/runtime/pincrt' + env.add_define('__PIN__=1') + env.add_define('PIN_CRT=1') + + env.add_include_dir('%(pin_root)s/extras/stlport/include') + env.add_include_dir('%(pin_root)s/extras') + env.add_include_dir('%(pin_root)s/extras/libstdc++/include') + env.add_include_dir('%(pin_root)s/extras/crt/include') + env.add_include_dir('%(pin_root)s/extras/crt') + env.add_include_dir('%(pin_root)s/extras/crt/include/arch-%(bionic_arch)s') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi') + env.add_include_dir('%(pin_root)s/extras/crt/include/kernel/uapi/asm-x86') + + if get_arch(env) == '32': + env.add_define('__i386__') + else: + env.add_define('__LP64__') + + if env.on_linux(): + _compile_with_pin_crt_lin(env) + elif env.on_mac(): + _compile_with_pin_crt_mac(env) + elif env.on_windows(): + _compile_with_pin_crt_win(env) + +def _gcc_version_string(env): + gcc = env.expand('%(CC)s') + vstr = mbuild.get_gcc_version(gcc) + return vstr + +def _greater_than_gcc(env,amaj,amin,aver): + vstr = _gcc_version_string(env) + try: + (vmaj, vmin, vver) = vstr.split('.') + except: + return False + vmaj = int(vmaj) + vmin = int(vmin) + vver = int(vver) + if vmaj > amaj: + return True + if vmaj == amaj and vmin > amin: + return True + if vmaj == amaj and vmin == amin and vver >= aver: + return True + return False + +def set_env_gnu(env): + """Example of setting up the GNU GCC environment for compilation""" + env['LINK'] = env['CC'] + + flags = '' + + #coverage testing using the local compiler + #flags += ' -fprofile-arcs -ftest-coverage' + #env['LIBS'] += ' -lgcov' + + flags += ' -Wall' + # the windows compiler finds this stuff so flag it on other platforms + flags += ' -Wunused' + + # 2018-11-28: I am working on hammering out all the issues found by these knobs: + #flags += ' -Wconversion' + #flags += ' -Wsign-conversion' + + if env['use_werror']: + flags += ' -Werror' + if env['compiler'] != 'icc': + flags += ' -Wno-long-long' + flags += ' -Wno-unknown-pragmas' + flags += ' -fmessage-length=0' + flags += ' -pipe' + + # -pg is incompatible with -fomit-frame-pointer + if (re.search(r' -pg', env['CXXFLAGS']) == None and + re.search(r' -pg', env['CCFLAGS']) == None and + (env['compiler'] != 'icc' or env['icc_version'] not in ['7','8'])): + flags += ' -fomit-frame-pointer' + + if env['compiler'] != 'icc' or (env['compiler'] == 'icc' and + env['icc_version'] != '7'): + flags += ' -fno-exceptions' + + # 2019-06-05: disabled - no longer needed + # required for gcc421 xcode to avoidundefined symbols when linking tools. + #if env.on_mac(): + # flags += ' -fno-common' + + if env['build_os'] == 'win' or _greater_than_gcc(env,4,9,0): + flags += ' -Wformat-security' + flags += ' -Wformat' + else: + # gcc3.4.4 on windows has problems with %x for xed_int32_t. + # gcc4.9.2 works well. + flags += ' -Wno-format' + flags += ' -Wno-format-security' + + if env['compiler'] != 'icc': + # c99 is required for c++ style comments. + env['CSTD'] = 'c99' + env['CCFLAGS'] += ' -std=%(CSTD)s ' + if env['pedantic']: + env['CCFLAGS'] += ' -pedantic ' + + if env['shared']: + if not env.on_windows(): + # -fvisibility=hidden only works on gcc>4. If not gcc, + # assume it works. Really only a problem for older icc + # compilers. + if env['compiler'] == 'gcc': + vstr = _gcc_version_string(env) + mbuild.msgb("GCC VERSION", vstr) + if env['compiler'] != 'gcc' or _greater_than_gcc(env,4,0,0): + hidden = ' -fvisibility=hidden' + env['LINKFLAGS'] += hidden + flags += hidden + + env['CCFLAGS'] += flags + env['CCFLAGS'] += ' -Wstrict-prototypes' + env['CCFLAGS'] += ' -Wwrite-strings' + if env['compiler'] != 'icc': + env['CCFLAGS'] += ' -Wredundant-decls' + + # Disabled the following. Generates too many silly errors/warnings + #env['CCFLAGS'] += ' -Wmissing-prototypes' + + env['CXXFLAGS'] += flags + +def set_env_clang(env): + set_env_gnu(env) + +def set_env_ms(env): + """Set up the MSVS environment for compilation""" + flags = '' + cxxflags = '' + if env['clr']: + flags += ' /TP /clr ' + # linker fail suggested libcmt was a problem for CLR. 2007-07-17 + env['LINKFLAGS'] += ' /NODEFAULTLIB:libcmt' + + # remove dead code from executable + env['LINKFLAGS'] += ' /OPT:REF /OPT:ICF=3' + + # enable security features + if env['msvs_version'] and int(env['msvs_version']) >= 8: # MSVS2005 + env.add_to_var('LINKFLAGS','/NXCOMPAT') + env.add_to_var('LINKFLAGS','/DYNAMICBASE') + + + if env['msvs_version'] == '6': + flags += ' /w' # disable warnings + else: + #cxxflags += ' /wd4530'# disable warning on unhandled exceptions + #flags += ' /wd4214' # disable /W4 warning on nonstd typed-bitfields + if not env['clr']: + cxxflags += ' /EHsc' # use windows exceptions + if not env['clr']: + cxxflags += ' /GR-' # do not use RTTI + if env['msvs_version'] != '6': + flags += ' /W4' # Maximum warning level. + flags += ' /WX' # Warnings as errors. + flags += ' /wd4091' # disable dbghelp.h warning in msvs2015 + # Disable warnings about conditional expression is constant + # used by xed_assert()'s "while(0)" and + # a few other "if (1)..." things. + flags += ' /wd4127' + flags += ' /wd4505' # Disable warnings about unused functions. + flags += ' /wd4702' # Disable warnings about unreachable code + # (shows up in generated code). FIXME + flags += ' /wd4244' # Disable warnings about changing widths. + # Disable warnings about compiler limit in MSVC7(.NET / 2003) + flags += ' /wd4292' + + # /Zm200 is required on VC98 for xed-decode.cpp to avoid + # internal compiler error + #flags += ' /Zm200' + env['CCFLAGS'] += flags + env['CXXFLAGS'] += cxxflags + " " + flags + +def intel_compiler_disables(env): + """Return a comma separated string of compile warning number disables + for ICC/ICL.""" + disables = [] + disables.append( 810 ) # loss of precision + # value copied to temporary, reference to temporary used. + disables.append( 383 ) + disables.append( 108 ) # signed bit fields of 1 bit length + disables.append( 111 ) # statement is unreachable + disables.append( 1419 ) # external declaration in primary source file + disables.append( 981 ) # operands are evaluated in unspecified order + if env['icc_version'] != '7': + # function "strncat" or "strcpy" (etc.) was declared + # "deprecated" # NOT ON ECL7 + disables.append( 1478 ) + disables.append( 188 ) # enumerated type mixed with another type + disables.append( 310 ) # old-style parameter list (anachronism) + disables.append( 592 ) # variable "c" is used before its value is set + disables.append( 1418 ) # external definition with no prior declaration + disables.append( 186 ) # pointless comparison of unsigned integer with zero + disables.append( 279 ) # controlling expression is constant + disables.append( 128 ) # loop is not reachable from preceding code + disables.append( 177 ) # function was declared but never referenced + + # Explicit conversion of a 64-bit integral type to a smaller integral type. + #disables.append( 1683 ) + + if env['icc_version'] not in ['7','8','9']: + # non-pointer conversion/lose significant bits, ICL11 + disables.append( 2259 ) + return ",".join(map(str,disables)) + +def set_env_icc(env): + set_env_gnu(env) + env['CCFLAGS'] += ' -wd' + intel_compiler_disables(env) + env['CXXFLAGS'] += ' -wd' + intel_compiler_disables(env) + +def set_env_icl(env): + set_env_ms(env) + env['CCFLAGS'] += ' /Qwd' + intel_compiler_disables(env) + env['CXXFLAGS'] += ' /Qwd' + intel_compiler_disables(env) + +########################################################################### + +def xed_remove_files_glob(env): + """Clean up""" + mbuild.msgb("CLEANING") + try: + if 'build_dir' in env: + path = env['build_dir'] + if path != '.' and path != '..': + mbuild.remove_tree(path) + return + except: + cdie("clean failed") + +########################################################################### + + +def set_xed_defaults(env): + """External entry point: Users must call set_xed_defaults() or + xed_args(). This post-processes the environment""" + env.process_user_settings() + +def init_once(env): + p = os.path.join(env['src_dir'], 'scripts') + if os.path.exists(p): + sys.path.insert(0, p) + +def init(env): + # we make the python command contingent upon the mfile itself to catch + # build changes. + + if 'init' in env and env['init']: + return + env['init']=True + + env['mfile'] = env.src_dir_join('mfile.py') + env['arch'] = get_arch(env) + + if env['compiler'] == 'gnu': + set_env_gnu(env) + elif env['compiler'] == 'clang': + set_env_clang(env) + elif env['compiler'] == 'ms': + set_env_ms(env) + elif env['compiler'] == 'icc': + set_env_icc(env) + elif env['compiler'] == 'icl': + set_env_icl(env) + else: + cdie("Unknown compiler: " + env['compiler']) + + if env['pin_crt']: + _compile_with_pin_crt(env) + + if env['xed_messages']: + env.add_define('XED_MESSAGES') + if env['xed_asserts']: + env.add_define("XED_ASSERTS") + +def strip_file(env,fn,options=''): + if env.on_windows(): + return + fne = env.expand(fn) + mbuild.msgb("STRIPPING", fne) + strip_cmd = " ".join([env['strip'], options, fne]) + #mbuild.msgb("STRIP CMD", strip_cmd) + (retcode,stdout,stderr) = mbuild.run_command(strip_cmd) + if retcode != 0: + dump_lines("strip stdout", stdout) + dump_lines("strip stderr", stderr) + cdie("Could not strip " + fne) + +def src_dir_join(env, lst): + return [ mbuild.join(env['src_dir'],'src',x) for x in lst ] + +def build_dir_join(env, lst): + return [ mbuild.join(env['build_dir'],x)for x in lst] + +def make_lib_dll(env,base): + """Return the static or link lib and shared-lib name. For a given + base we return base.lib and base.dll on windows. base.so and + base.so on non-windows. Users link against the link lib.""" + + dll = env.shared_lib_name(base) + static_lib = env.static_lib_name(base) + + if env['shared']: + if env.on_windows(): + link_lib = static_lib + else: + link_lib = dll + else: + link_lib = static_lib + + return link_lib, dll + +def _xed_lib_dir_join(env, s): + return mbuild.join(env['xed_lib_dir'],s) + +def get_libxed_names(env): + libxed_lib, libxed_dll = make_lib_dll(env,'xed') + env['link_libxed'] = _xed_lib_dir_join(env,libxed_lib) + env['shd_libxed'] = _xed_lib_dir_join(env,libxed_dll) + + lib,dll = make_lib_dll(env,'xed-ild') + env['link_libild'] = _xed_lib_dir_join(env,lib) + env['shd_libild'] = _xed_lib_dir_join(env,dll) + +def installing(env): + if 'install' in env['targets'] or 'zip' in env['targets']: + return True + return False + +def _modify_search_path_mac(env, fn): + """Make example tools refer to the libxed.so from the lib directory + if doing and install. Mac only.""" + if not env['shared']: + return + if not env.on_mac(): + return + if not installing(env): + return + env['odll'] = '%(build_dir)s/libxed.dylib' + env['ndll'] = '"@loader_path/../lib/libxed.dylib"' + cmd = 'install_name_tool -change %(odll)s %(ndll)s ' + fn + cmd = env.expand(cmd) + env['odll'] = None + env['ndll'] = None + + mbuild.msgb("SHDOBJ SEARCH PATH", cmd) + (retcode,stdout,stderr) = mbuild.run_command(cmd) + if retcode != 0: + dump_lines("install_name_tool stdout", stdout) + dump_lines("install_name_tool stderr", stderr) + cdie("Could not modify dll path: " + cmd) + + +def get_arch(env): + if env['host_cpu'] == 'ia32': + arch = '32' + else: + arch = '64' + return arch + + +def dump_lines(s,lines): + if lines: + print("========") + print(s + ":") + for line in lines: + print(line.strip()) + print("========") + + +def prep(env): + mbuild.vmsgb(1, "PYTHON VERSION", "%d.%d.%d" % + (mbuild.get_python_version_tuple())) + + +########################################################################### +# ELF/DWARF (linux only) + +def _use_elf_dwarf(env): + """Do not call this directly. See cond_add_elf_dwarf. Tell the + build we want to use libelf and libdwarf. Some systems have these + libraries installed and this is sufficient for those systems.""" + + env['LIBS'] += ' -lelf' + env.add_define('XED_DWARF') + env['LIBS'] += ' -ldwarf' + + +def _add_elf_dwarf_precompiled(env): + """Do not call this directly. See cond_add_elf_dwarf. Set up to + use our precompiled libelf/libdwarf. """ + + env.add_include_dir('%(xedext_dir)s/external/include') + env.add_include_dir('%(xedext_dir)s/external/include/libelf') + + env.add_define('XED_PRECOMPILED_ELF_DWARF') + + env['extern_lib_dir'] = '%(xedext_dir)s/external/lin/lib%(arch)s' + + env['libdwarf'] = '%(extern_lib_dir)s/libdwarf.so' + env['libelf'] = env.expand('%(extern_lib_dir)s/libelf.so.0.8.13') + env['libelf_symlink'] = 'libelf.so.0' + env['libelf_license'] = env.expand('%(xedext_dir)s/external/EXTLICENSE.txt') + if env.on_freebsd(): + env['LINKFLAGS'] += " -Wl,-z,origin" + + env['LINKFLAGS'] += " -L%(extern_lib_dir)s" + if installing(env): + env['LINKFLAGS'] += " -Wl,-rpath,'$ORIGIN/../extlib'" + else: + # this case is a little ambiguous. If not making a kit we + # just use a full path to the source tree. + p = os.path.abspath(env.expand("%(extern_lib_dir)s")) + env['LINKFLAGS'] += " -Wl,-rpath," + p + + env['ext_libs' ].append(env['libelf']) + env['ext_libs' ].append(env['libdwarf']) + +def cond_add_elf_dwarf(env): + "Set up for using libelf/libdwarf on linux." + + if 'ext_libs' not in env: + env['ext_libs'] = [] + + if env['use_elf_dwarf']: + if not env.on_linux(): + die("No libelf/dwarf for this platform") + else: + return + + mbuild.msgb("ADDING ELF/DWARF") + # set up the preprocessor define and linker requirements. + _use_elf_dwarf(env) + + if env['use_elf_dwarf_precompiled']: + mbuild.msgb("ADDING ELF/DWARF PRECOMPILED") + _add_elf_dwarf_precompiled(env) + else: + env.add_include_dir('/usr/include/libdwarf') + +# +########################################################################### diff --git a/CodeVirtualizer/build/obj/wkit/examples/xed_examples_mbuild.py b/CodeVirtualizer/build/obj/wkit/examples/xed_examples_mbuild.py new file mode 100644 index 0000000..bd6b1c6 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/examples/xed_examples_mbuild.py @@ -0,0 +1,515 @@ +#!/usr/bin/env python +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +import sys +import os +import re +import shutil +import copy +import time +import types +import optparse +# sys.path is set up by calling script (mfile.py ususally) +import mbuild +import xed_build_common as xbc + +def ex_compile_and_link(env, dag, src, objs): + """Return the exe name - used for the examples""" + basename = os.path.basename(src) + exe = env.build_dir_join(env.resuffix(basename, env['EXEEXT'])) + all_obj = [] + + # first_example_lib and last_example_lib are for supporting + # compilations using custom C runtimes. + if 'first_example_lib' in env: + all_obj.append(env['first_example_lib']) + all_obj.extend(env.compile(dag, [src])) + all_obj.extend(objs) + if 'last_example_lib' in env: + all_obj.append(env['last_example_lib']) + + lc = env.link(all_obj, exe) + cmd = dag.add(env,lc) + return cmd.targets[0] + +########################################################################### + +def mkenv(): + """External entry point: create the environment""" + if sys.version_info[0] == 3 and sys.version_info[1] < 4: + _fatal("Need python version 3.4 or later.") + elif sys.version_info[0] == 2 and sys.version_info[1] < 7: + _fatal("Need python version 2.7 or later.") + # create an environment, parse args + env = mbuild.env_t() + standard_defaults = dict( doxygen_install='', + doxygen='', + clean=False, + die_on_errors=True, + xed_messages=False, + xed_asserts=False, + pedantic=True, + clr=False, + use_werror=True, + dbghelp=False, + install_dir='', + kit_kind='base', + win=False, + dev=False, + legal_header=None, + encoder=True, + enc2=True, + decoder=True, + ld_library_path=[], + ld_library_path_for_tests=[], + use_elf_dwarf=False, + use_elf_dwarf_precompiled=False, + strip='strip', + verbose = 1, + example_linkflags='', + example_flags='', + example_rpaths=[], + android=False, + xed_inc_dir=[], + xed_lib_dir='', + xed_enc2_libs=[], + xed_dir='', + build_cpp_examples=False, + set_copyright=False, + pin_crt='') + + env['xed_defaults'] = standard_defaults + env.set_defaults(env['xed_defaults']) + return env + +def xed_args(env): + """For command line invocation: parse the arguments""" + env.parser.add_option("--no-encoder", + dest="encoder", + action="store_false", + help="No encoder") + env.parser.add_option("--no-enc2", + dest="enc2", + action="store_false", + help="No enc2 encoder") + env.parser.add_option("--no-decoder", + dest="decoder", + action="store_false", + help="No decoder") + env.parser.add_option("--android", + dest="android", + action="store_true", + help="Android build (avoid rpath for examples)") + env.parser.add_option("--example-linkflags", + dest="example_linkflags", + action="store", + help="Extra link flags for the examples") + env.parser.add_option("--example-flags", + dest="example_flags", + action="store", + help="Extra compilation flags for the examples") + env.parser.add_option("--example-rpath", + dest="example_rpaths", + action="append", + help="Extra rpath dirs for examples") + env.parser.add_option("-c","--clean", + dest="clean", + action="store_true", + help="Clean targets") + env.parser.add_option("--keep-going", '-k', + action="store_false", + dest="die_on_errors", + help="Keep going after errors occur when building") + env.parser.add_option("--messages", + action="store_true", + dest="xed_messages", + help="Enable use xed's debug messages") + env.parser.add_option("--no-pedantic", + action="store_false", + dest="pedantic", + help="Disable -pedantic (gnu/clang compilers).") + env.parser.add_option("--asserts", + action="store_true", + dest="xed_asserts", + help="Enable use xed's asserts") + env.parser.add_option("--clr", + action="store_true", + dest="clr", + help="Compile for Microsoft CLR") + env.parser.add_option("--no-werror", + action="store_false", + dest="use_werror", + help="Disable use of -Werror on GNU compiles") + env.parser.add_option("--dbghelp", + action="store_true", + dest="dbghelp", + help="Use dbghelp.dll on windows.") + env.parser.add_option("--install-dir", + dest="install_dir", + action="store", + help="XED Install directory. " + + "Default: kits/xed-install-date-os-cpu") + env.parser.add_option("--kit-kind", + dest="kit_kind", + action="store", + help="Kit version string. " + + "The default is 'base'") + env.parser.add_option("--win", + action="store_true", + dest="win", + help="Add -mno-cygwin to GCC-on-windows compilation") + env.parser.add_option("--ld-library-path", + action="append", + dest="ld_library_path", + help="Specify additions to LD_LIBRARY_PATH " + + "for use when running ldd and making kits") + env.parser.add_option("--ld-library-path-for-tests", + action="append", + dest="ld_library_path_for_tests", + help="Specify additions to LD_LIBRARY_PATH " + + "for use when running the tests") + + # elf.h is different than libelf.h. + env.parser.add_option("--elf-dwarf", "--dwarf", + action="store_true", + dest="use_elf_dwarf", + help="Use libelf/libdwarf. (Linux only)") + env.parser.add_option("--elf-dwarf-precompiled", + action="store_true", + dest="use_elf_dwarf_precompiled", + help="Use precompiled libelf/libdwarf from " + + " the XED source distribution." + + " This is the currently required" + + " if you are installing a kit." + + " Implies the --elf-dwarf knob." + " (Linux only)") + env.parser.add_option("--strip", + action="store", + dest="strip", + help="Path to strip binary. (Linux only)") + env.parser.add_option("--pin-crt", + action="store", + dest="pin_crt", + help="Compile for the Pin C-runtime. Specify" + + " path to pin kit") + env.parser.add_option("--lib-dir", + action='store', + dest="xed_lib_dir", + help="directory where libxed* is located.") + env.parser.add_option("--enc2-lib", + action='append', + dest="xed_enc2_libs", + help="Filenames (with paths) of the XED enc2 libraries.") + env.parser.add_option("--inc-dir", + action="append", + dest="xed_inc_dir", + help="directory where xed generated headers are located.") + env.parser.add_option("--xed-dir", + action="store", + dest="xed_dir", + help="directory where xed sources are located.") + env.parser.add_option("--build-cpp-examples", + action="store_true", + dest="build_cpp_examples", + help="Build the C++ examples default: False.") + env.parser.add_option("--set-copyright", + action="store_true", + dest="set_copyright", + help="Set the Intel copyright on Windows XED executable") + + env.parse_args(env['xed_defaults']) + +def nchk(env,s): + #null string check or not set check + if s not in env or len(env[s]) == 0: + return True + return False + +def init(env): + xbc.init(env) + if nchk(env,'xed_lib_dir'): + env['xed_lib_dir'] = '../lib' + + + if nchk(env,'xed_enc2_libs'): + env['xed_enc2_libs'] = ( mbuild.glob(env['xed_lib_dir'],'*xed-chk-enc2-*') + + mbuild.glob(env['xed_lib_dir'],'*xed-enc2-*') ) + if nchk(env,'xed_enc2_libs'): + # do not build enc2 examples if libraries are missing + env['enc2'] = False + + if nchk(env,'xed_inc_dir'): + env['xed_inc_dir'] = ['../include'] + if nchk(env,'xed_dir'): + env['xed_dir'] = '..' + env.add_include_dir( env['src_dir'] ) # examples dir + for inc in env['xed_inc_dir']: + env.add_include_dir( inc ) + +def _wk_show_errors_only(): + #True means show errors only when building. + if mbuild.verbose(2): + return False # show output + return True # show errors only. + + +def _add_libxed_rpath(env): + """Make example tools refer to the libxed.so from the lib directory""" + if env['shared'] and env.on_linux() and not env['android']: + env['LINKFLAGS'] += " -Wl,-rpath,'$ORIGIN/../lib'" + + +def build_asmparse(env, dag, otherobj): + srcs = env.src_dir_join(['xed-asmparse.c']) + objs = env.compile(dag, srcs) + + exe = ex_compile_and_link(env, + dag, + env.src_dir_join('xed-asmparse-main.c'), + objs + otherobj + [env['link_libxed']]) + return exe + + + +def build_examples(env, work_queue): + """Build the examples""" + example_exes = [] + env['example_exes'] = [] # used by install + examples_dag = mbuild.dag_t('xedexamples', env=env) + + if not env.on_windows(): + for d in env['example_rpaths']: + env.add_to_var('example_linkflags', + '-Wl,-rpath,{}'.format(d)) + env.add_to_var('LINKFLAGS', env['example_linkflags']) + env.add_to_var('CCFLAGS', env['example_flags']) + env.add_to_var('CXXFLAGS', env['example_flags']) + mbuild.cmkdir(env['build_dir']) + + link_libxed = env['link_libxed'] + + if env['shared']: + _add_libxed_rpath(env) + + # C vs C++: env is for C++ and env_c is for C programs. + if env['compiler'] in ['gnu','clang', 'icc']: + env['LINK'] = env['CXX'] + env_c = copy.deepcopy(env) + if env_c['compiler'] in ['gnu','clang']: + env_c['LINK'] = '%(CC)s' + + if env['pin_crt']: + xbc.compile_with_pin_crt_lin_mac_common_cplusplus(env) + + # shared files + cc_shared_files = env.src_dir_join([ + 'xed-examples-util.c']) + if env['decoder']: + cc_shared_files.extend(env.src_dir_join([ + 'xed-dot.c', + 'xed-dot-prep.c'])) + + if env['encoder']: + cc_shared_files += env.src_dir_join([ 'xed-enc-lang.c']) + cc_shared_objs = env.compile( examples_dag, cc_shared_files) + # the XED command line tool + xed_cmdline_files = [ 'xed-disas-raw.c', + 'avltree.c', + 'xed-disas-hex.c', + 'xed-symbol-table.c'] + if env.on_windows() and env['set_copyright']: + # AUTOMATICALLY UPDATE YEAR IN THE RC FILE + year = time.strftime("%Y") + lines = open(env.src_dir_join('xed-rc-template.txt')).readlines() + lines = [ re.sub('%%YEAR%%',year,x) for x in lines ] + xbc.write_file(env.src_dir_join('xed.rc'), lines) + xed_cmdline_files.append("xed.rc") + + extra_libs = [] + if env['decoder']: + + if env.on_linux() or env.on_freebsd() or env.on_netbsd(): + xed_cmdline_files.append('xed-disas-filter.c') + xed_cmdline_files.append('xed-nm-symtab.c') + + elif env.on_mac(): + xed_cmdline_files.append('xed-disas-macho.c') + + elif env.on_windows(): + xed_cmdline_files.append('xed-disas-pecoff.cpp') + if ( env['dbghelp'] and + env['msvs_version'] not in ['6','7'] ): + env.add_define("XED_DBGHELP") + xed_cmdline_files.append('udhelp.cpp') + extra_libs = ['dbghelp.lib', 'version.lib' ] + + xed_cmdline_files = env.src_dir_join(xed_cmdline_files) + xed_cmdline_obj = copy.deepcopy(cc_shared_objs) + + # Env for cmdline tool (with libelf/dwarf on linux.) + if env.on_windows(): # still C++ + cenv = copy.deepcopy(env) + else: # lin/mac are C code only. + cenv = copy.deepcopy(env_c) + + if env.on_linux(): + xbc.cond_add_elf_dwarf(cenv) + + if env.on_linux() or env.on_freebsd() or env.on_netbsd(): + src_elf = env.src_dir_join('xed-disas-elf.c') + if env['use_elf_dwarf_precompiled']: + cenv2 = copy.deepcopy(cenv) + # need to remove -pedantic because of redundant typedef Elf in dwarf header file + cenv2.remove_from_var('CCFLAGS','-pedantic') + xed_cmdline_obj += cenv2.compile(examples_dag, [src_elf]) + else: + xed_cmdline_files.append(src_elf) + + xed_cmdline_obj += cenv.compile(examples_dag, xed_cmdline_files) + xed_cmdline = ex_compile_and_link(cenv, examples_dag, + env.src_dir_join('xed.c'), + xed_cmdline_obj + [link_libxed] + + extra_libs) + + mbuild.msgb("CMDLINE", xed_cmdline) + example_exes.append(xed_cmdline) + + if env['encoder']: + exe = build_asmparse(cenv, examples_dag, cc_shared_objs) + example_exes.append(exe) + + + ild_examples = [] + other_c_examples = [] + enc2_examples = [] + small_examples = ['xed-size.c'] + if env['enc2']: + enc2_examples += [ 'xed-enc2-1.c', + 'xed-enc2-2.c', + 'xed-enc2-3.c' ] + if env['encoder']: + small_examples += ['xed-ex5-enc.c'] + other_c_examples += ['xed-ex3.c'] + if env['decoder'] and env['encoder']: + other_c_examples += ['xed-ex6.c', + 'xed-ex9-patch.c' ] + if env['decoder']: + ild_examples += [ 'xed-ex-ild.c' ] + other_c_examples += ['xed-ex1.c', + 'xed-ex-ild2.c', + 'xed-min.c', + 'xed-reps.c', + 'xed-ex4.c', + 'xed-tester.c', + 'xed-dec-print.c', + 'xed-ex-agen.c', + 'xed-ex7.c', + 'xed-ex8.c', + 'xed-ex-cpuid.c', + 'xed-tables.c', + 'xed-find-special.c', + 'xed-dll-discovery.c'] + + # compile & link other_c_examples + for example in env.src_dir_join(other_c_examples): + example_exes.append(ex_compile_and_link(env_c, + examples_dag, + example, + cc_shared_objs + [ link_libxed ])) + # compile & link ild_examples + if os.path.exists(env['link_libild']): + for example in env.src_dir_join(ild_examples): + example_exes.append(ex_compile_and_link(env_c, + examples_dag, + example, + [ env['link_libild'] ])) + + # compile & link small_examples + for example in env.src_dir_join(small_examples): + example_exes.append(ex_compile_and_link(env_c, + examples_dag, + example, + [ link_libxed ])) + + for example in env.src_dir_join(enc2_examples): + example_exes.append(ex_compile_and_link( env_c, + examples_dag, + example, + env['xed_enc2_libs'] + [link_libxed] )) + + mbuild.vmsgb(4, "ALL EXAMPLES", "\n\t".join(example_exes)) + + examples_to_build = example_exes + env['example_exes'] = example_exes + + mbuild.msgb("BUILDING EXAMPLES") + okay = work_queue.build(examples_dag, + targets=examples_to_build, + die_on_errors=env['die_on_errors'], + show_progress=True, + show_output=True, + show_errors_only=_wk_show_errors_only()) + if not okay: + xbc.cdie( "XED EXAMPLES build failed") + mbuild.vmsgb(3, "XED EXAMPLES", "build succeeded") + return 0 + +def verify_args(env): + if env['use_elf_dwarf_precompiled']: + env['use_elf_dwarf'] = True + +def examples_work(env): + """External entry point for non-command line invocations. + Initialize the environment, build libxed, the examples, the kit + and run the tests""" + xbc.prep(env) + verify_args(env) + start_time=mbuild.get_time() + xbc.init_once(env) + + init(env) + + if 'clean' in env['targets'] or env['clean']: + xbc.xed_remove_files_glob(env) + if len(env['targets'])<=1: + xbc.cexit(0) + + mbuild.cmkdir(env['build_dir']) + + work_queue = mbuild.work_queue_t(env['jobs']) + + xbc.get_libxed_names(env) + retval = build_examples(env, work_queue) + end_time=mbuild.get_time() + mbuild.msgb("EXAMPLES BUILD ELAPSED TIME", + mbuild.get_elapsed_time(start_time, end_time)) + return retval + +def execute(): + """Main external entry point for command line invocations""" + + import mbuild + env = mkenv() + # xed_args() is skip-able for remote (import) invocation. The env + # from mkenv can be updated programmatically. One must call + # xbc.set_xed_defaults(env) if not calling xed_args(env) + xed_args(env) # parse command line knobs + retval = examples_work(env) + return retval diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-address-width-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-address-width-enum.h new file mode 100644 index 0000000..2931930 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-address-width-enum.h @@ -0,0 +1,54 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-address-width-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ADDRESS_WIDTH_ENUM_H) +# define XED_ADDRESS_WIDTH_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ADDRESS_WIDTH_INVALID_DEFINED 1 +#define XED_ADDRESS_WIDTH_16b_DEFINED 1 +#define XED_ADDRESS_WIDTH_32b_DEFINED 1 +#define XED_ADDRESS_WIDTH_64b_DEFINED 1 +#define XED_ADDRESS_WIDTH_LAST_DEFINED 1 +typedef enum { + XED_ADDRESS_WIDTH_INVALID=0, + XED_ADDRESS_WIDTH_16b=2, ///< 16b addressing + XED_ADDRESS_WIDTH_32b=4, ///< 32b addressing + XED_ADDRESS_WIDTH_64b=8, ///< 64b addressing + XED_ADDRESS_WIDTH_LAST +} xed_address_width_enum_t; + +/// This converts strings to #xed_address_width_enum_t types. +/// @param s A C-string. +/// @return #xed_address_width_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_address_width_enum_t str2xed_address_width_enum_t(const char* s); +/// This converts strings to #xed_address_width_enum_t types. +/// @param p An enumeration element of type xed_address_width_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_address_width_enum_t2str(const xed_address_width_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_address_width_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_address_width_enum_t xed_address_width_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-agen.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-agen.h new file mode 100644 index 0000000..e24092b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-agen.h @@ -0,0 +1,66 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-agen.h +/// + + +#ifndef XED_AGEN_H +# define XED_AGEN_H +#include "xed-decoded-inst.h" +#include "xed-error-enum.h" + + +/// A function for obtaining register values. 32b return values should be +/// zero extended to 64b. The error value is set to nonzero if the callback +/// experiences some sort of problem. @ingroup AGEN +typedef xed_uint64_t (*xed_register_callback_fn_t)(xed_reg_enum_t reg, + void* context, + xed_bool_t* error); + +/// A function for obtaining the segment base values. 32b return values +/// should be zero extended zero extended to 64b. The error value is set to +/// nonzero if the callback experiences some sort of problem. +/// @ingroup AGEN +typedef xed_uint64_t (*xed_segment_base_callback_fn_t)(xed_reg_enum_t reg, + void* context, + xed_bool_t* error); + + +/// Initialize the callback functions. Tell XED what to call when using +/// #xed_agen. +/// @ingroup AGEN +XED_DLL_EXPORT void xed_agen_register_callback(xed_register_callback_fn_t register_fn, + xed_segment_base_callback_fn_t segment_fn); + +/// Using the registered callbacks, compute the memory address for a +/// specified memop in a decoded instruction. memop_index can have the +/// value 0 for XED_OPERAND_MEM0, XED_OPERAND_AGEN, or 1 for +/// XED_OPERAND_MEM1. Any other value results in an error being +/// returned. The context parameter which is passed to the registered +/// callbacks can be used to identify which thread's state is being +/// referenced. The context parameter can also be used to specify which +/// element of a vector register should be returned for gather an scatter +/// operations. +/// @ingroup AGEN +XED_DLL_EXPORT xed_error_enum_t xed_agen(xed_decoded_inst_t* xedd, + unsigned int memop_index, + void* context, + xed_uint64_t* out_address); + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-attribute-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-attribute-enum.h new file mode 100644 index 0000000..be354c9 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-attribute-enum.h @@ -0,0 +1,234 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-attribute-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ATTRIBUTE_ENUM_H) +# define XED_ATTRIBUTE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ATTRIBUTE_INVALID_DEFINED 1 +#define XED_ATTRIBUTE_AMDONLY_DEFINED 1 +#define XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION_DEFINED 1 +#define XED_ATTRIBUTE_BROADCAST_ENABLED_DEFINED 1 +#define XED_ATTRIBUTE_BYTEOP_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_EIGHTHMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_FULL_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_FULLMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_READER_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_READER_BYTE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_READER_WORD_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GSCAT_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_HALF_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_HALFMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_MEM128_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_MOVDDUP_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_QUARTER_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_QUARTERMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_SCALAR_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_4X_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_BYTE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_WORD_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE2_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE4_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE8_DEFINED 1 +#define XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP_DEFINED 1 +#define XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT_DEFINED 1 +#define XED_ATTRIBUTE_DWORD_INDICES_DEFINED 1 +#define XED_ATTRIBUTE_ELEMENT_SIZE_D_DEFINED 1 +#define XED_ATTRIBUTE_ELEMENT_SIZE_Q_DEFINED 1 +#define XED_ATTRIBUTE_EXCEPTION_BR_DEFINED 1 +#define XED_ATTRIBUTE_FAR_XFER_DEFINED 1 +#define XED_ATTRIBUTE_FIXED_BASE0_DEFINED 1 +#define XED_ATTRIBUTE_FIXED_BASE1_DEFINED 1 +#define XED_ATTRIBUTE_GATHER_DEFINED 1 +#define XED_ATTRIBUTE_HALF_WIDE_OUTPUT_DEFINED 1 +#define XED_ATTRIBUTE_HLE_ACQ_ABLE_DEFINED 1 +#define XED_ATTRIBUTE_HLE_REL_ABLE_DEFINED 1 +#define XED_ATTRIBUTE_IGNORES_OSFXSR_DEFINED 1 +#define XED_ATTRIBUTE_IMPLICIT_ONE_DEFINED 1 +#define XED_ATTRIBUTE_INDEX_REG_IS_POINTER_DEFINED 1 +#define XED_ATTRIBUTE_INDIRECT_BRANCH_DEFINED 1 +#define XED_ATTRIBUTE_KMASK_DEFINED 1 +#define XED_ATTRIBUTE_LOCKABLE_DEFINED 1 +#define XED_ATTRIBUTE_LOCKED_DEFINED 1 +#define XED_ATTRIBUTE_MASKOP_DEFINED 1 +#define XED_ATTRIBUTE_MASKOP_EVEX_DEFINED 1 +#define XED_ATTRIBUTE_MASK_AS_CONTROL_DEFINED 1 +#define XED_ATTRIBUTE_MASK_VARIABLE_MEMOP_DEFINED 1 +#define XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION_DEFINED 1 +#define XED_ATTRIBUTE_MMX_EXCEPT_DEFINED 1 +#define XED_ATTRIBUTE_MPX_PREFIX_ABLE_DEFINED 1 +#define XED_ATTRIBUTE_MULTIDEST2_DEFINED 1 +#define XED_ATTRIBUTE_MULTISOURCE4_DEFINED 1 +#define XED_ATTRIBUTE_MXCSR_DEFINED 1 +#define XED_ATTRIBUTE_MXCSR_RD_DEFINED 1 +#define XED_ATTRIBUTE_NONTEMPORAL_DEFINED 1 +#define XED_ATTRIBUTE_NOP_DEFINED 1 +#define XED_ATTRIBUTE_NOTSX_DEFINED 1 +#define XED_ATTRIBUTE_NOTSX_COND_DEFINED 1 +#define XED_ATTRIBUTE_NO_RIP_REL_DEFINED 1 +#define XED_ATTRIBUTE_NO_SRC_DEST_MATCH_DEFINED 1 +#define XED_ATTRIBUTE_PREFETCH_DEFINED 1 +#define XED_ATTRIBUTE_PROTECTED_MODE_DEFINED 1 +#define XED_ATTRIBUTE_QWORD_INDICES_DEFINED 1 +#define XED_ATTRIBUTE_REP_DEFINED 1 +#define XED_ATTRIBUTE_REQUIRES_ALIGNMENT_DEFINED 1 +#define XED_ATTRIBUTE_RING0_DEFINED 1 +#define XED_ATTRIBUTE_SCALABLE_DEFINED 1 +#define XED_ATTRIBUTE_SCATTER_DEFINED 1 +#define XED_ATTRIBUTE_SIMD_SCALAR_DEFINED 1 +#define XED_ATTRIBUTE_SKIPLOW32_DEFINED 1 +#define XED_ATTRIBUTE_SKIPLOW64_DEFINED 1 +#define XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED_DEFINED 1 +#define XED_ATTRIBUTE_STACKPOP0_DEFINED 1 +#define XED_ATTRIBUTE_STACKPOP1_DEFINED 1 +#define XED_ATTRIBUTE_STACKPUSH0_DEFINED 1 +#define XED_ATTRIBUTE_STACKPUSH1_DEFINED 1 +#define XED_ATTRIBUTE_USES_DAZ_DEFINED 1 +#define XED_ATTRIBUTE_USES_FTZ_DEFINED 1 +#define XED_ATTRIBUTE_X87_CONTROL_DEFINED 1 +#define XED_ATTRIBUTE_X87_MMX_STATE_CW_DEFINED 1 +#define XED_ATTRIBUTE_X87_MMX_STATE_R_DEFINED 1 +#define XED_ATTRIBUTE_X87_MMX_STATE_W_DEFINED 1 +#define XED_ATTRIBUTE_X87_NOWAIT_DEFINED 1 +#define XED_ATTRIBUTE_XMM_STATE_CW_DEFINED 1 +#define XED_ATTRIBUTE_XMM_STATE_R_DEFINED 1 +#define XED_ATTRIBUTE_XMM_STATE_W_DEFINED 1 +#define XED_ATTRIBUTE_LAST_DEFINED 1 +typedef enum { + XED_ATTRIBUTE_INVALID, + XED_ATTRIBUTE_AMDONLY, + XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION, + XED_ATTRIBUTE_BROADCAST_ENABLED, + XED_ATTRIBUTE_BYTEOP, + XED_ATTRIBUTE_DISP8_EIGHTHMEM, + XED_ATTRIBUTE_DISP8_FULL, + XED_ATTRIBUTE_DISP8_FULLMEM, + XED_ATTRIBUTE_DISP8_GPR_READER, + XED_ATTRIBUTE_DISP8_GPR_READER_BYTE, + XED_ATTRIBUTE_DISP8_GPR_READER_WORD, + XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D, + XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q, + XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE, + XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE, + XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD, + XED_ATTRIBUTE_DISP8_GSCAT, + XED_ATTRIBUTE_DISP8_HALF, + XED_ATTRIBUTE_DISP8_HALFMEM, + XED_ATTRIBUTE_DISP8_MEM128, + XED_ATTRIBUTE_DISP8_MOVDDUP, + XED_ATTRIBUTE_DISP8_QUARTER, + XED_ATTRIBUTE_DISP8_QUARTERMEM, + XED_ATTRIBUTE_DISP8_SCALAR, + XED_ATTRIBUTE_DISP8_TUPLE1, + XED_ATTRIBUTE_DISP8_TUPLE1_4X, + XED_ATTRIBUTE_DISP8_TUPLE1_BYTE, + XED_ATTRIBUTE_DISP8_TUPLE1_WORD, + XED_ATTRIBUTE_DISP8_TUPLE2, + XED_ATTRIBUTE_DISP8_TUPLE4, + XED_ATTRIBUTE_DISP8_TUPLE8, + XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP, + XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT, + XED_ATTRIBUTE_DWORD_INDICES, + XED_ATTRIBUTE_ELEMENT_SIZE_D, + XED_ATTRIBUTE_ELEMENT_SIZE_Q, + XED_ATTRIBUTE_EXCEPTION_BR, + XED_ATTRIBUTE_FAR_XFER, + XED_ATTRIBUTE_FIXED_BASE0, + XED_ATTRIBUTE_FIXED_BASE1, + XED_ATTRIBUTE_GATHER, + XED_ATTRIBUTE_HALF_WIDE_OUTPUT, + XED_ATTRIBUTE_HLE_ACQ_ABLE, + XED_ATTRIBUTE_HLE_REL_ABLE, + XED_ATTRIBUTE_IGNORES_OSFXSR, + XED_ATTRIBUTE_IMPLICIT_ONE, + XED_ATTRIBUTE_INDEX_REG_IS_POINTER, + XED_ATTRIBUTE_INDIRECT_BRANCH, + XED_ATTRIBUTE_KMASK, + XED_ATTRIBUTE_LOCKABLE, + XED_ATTRIBUTE_LOCKED, + XED_ATTRIBUTE_MASKOP, + XED_ATTRIBUTE_MASKOP_EVEX, + XED_ATTRIBUTE_MASK_AS_CONTROL, + XED_ATTRIBUTE_MASK_VARIABLE_MEMOP, + XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION, + XED_ATTRIBUTE_MMX_EXCEPT, + XED_ATTRIBUTE_MPX_PREFIX_ABLE, + XED_ATTRIBUTE_MULTIDEST2, + XED_ATTRIBUTE_MULTISOURCE4, + XED_ATTRIBUTE_MXCSR, + XED_ATTRIBUTE_MXCSR_RD, + XED_ATTRIBUTE_NONTEMPORAL, + XED_ATTRIBUTE_NOP, + XED_ATTRIBUTE_NOTSX, + XED_ATTRIBUTE_NOTSX_COND, + XED_ATTRIBUTE_NO_RIP_REL, + XED_ATTRIBUTE_NO_SRC_DEST_MATCH, + XED_ATTRIBUTE_PREFETCH, + XED_ATTRIBUTE_PROTECTED_MODE, + XED_ATTRIBUTE_QWORD_INDICES, + XED_ATTRIBUTE_REP, + XED_ATTRIBUTE_REQUIRES_ALIGNMENT, + XED_ATTRIBUTE_RING0, + XED_ATTRIBUTE_SCALABLE, + XED_ATTRIBUTE_SCATTER, + XED_ATTRIBUTE_SIMD_SCALAR, + XED_ATTRIBUTE_SKIPLOW32, + XED_ATTRIBUTE_SKIPLOW64, + XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED, + XED_ATTRIBUTE_STACKPOP0, + XED_ATTRIBUTE_STACKPOP1, + XED_ATTRIBUTE_STACKPUSH0, + XED_ATTRIBUTE_STACKPUSH1, + XED_ATTRIBUTE_USES_DAZ, + XED_ATTRIBUTE_USES_FTZ, + XED_ATTRIBUTE_X87_CONTROL, + XED_ATTRIBUTE_X87_MMX_STATE_CW, + XED_ATTRIBUTE_X87_MMX_STATE_R, + XED_ATTRIBUTE_X87_MMX_STATE_W, + XED_ATTRIBUTE_X87_NOWAIT, + XED_ATTRIBUTE_XMM_STATE_CW, + XED_ATTRIBUTE_XMM_STATE_R, + XED_ATTRIBUTE_XMM_STATE_W, + XED_ATTRIBUTE_LAST +} xed_attribute_enum_t; + +/// This converts strings to #xed_attribute_enum_t types. +/// @param s A C-string. +/// @return #xed_attribute_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_attribute_enum_t str2xed_attribute_enum_t(const char* s); +/// This converts strings to #xed_attribute_enum_t types. +/// @param p An enumeration element of type xed_attribute_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_attribute_enum_t2str(const xed_attribute_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_attribute_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_attribute_enum_t xed_attribute_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-attributes.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-attributes.h new file mode 100644 index 0000000..b65263b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-attributes.h @@ -0,0 +1,28 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_ATTRIBUTES_H) +# define XED_ATTRIBUTES_H +#include "xed-types.h" + +typedef struct { + xed_uint64_t a1; + xed_uint64_t a2; +} xed_attributes_t; + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-build-defines.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-build-defines.h new file mode 100644 index 0000000..4386b12 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-build-defines.h @@ -0,0 +1,57 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#if !defined(XED_BUILD_DEFINES_H) +# define XED_BUILD_DEFINES_H + +# if !defined(XED_AMD_ENABLED) +# define XED_AMD_ENABLED +# endif +# if !defined(XED_AVX) +# define XED_AVX +# endif +# if !defined(XED_CET) +# define XED_CET +# endif +# if !defined(XED_DECODER) +# define XED_DECODER +# endif +# if !defined(XED_ENCODER) +# define XED_ENCODER +# endif +# if !defined(XED_GIT_VERSION) +# define XED_GIT_VERSION "12.0.1-72-gd57a3bd" +# endif +# if !defined(XED_MPX) +# define XED_MPX +# endif +# if !defined(XED_SUPPORTS_AVX512) +# define XED_SUPPORTS_AVX512 +# endif +# if !defined(XED_SUPPORTS_LZCNT_TZCNT) +# define XED_SUPPORTS_LZCNT_TZCNT +# endif +# if !defined(XED_SUPPORTS_SHA) +# define XED_SUPPORTS_SHA +# endif +# if !defined(XED_SUPPORTS_WBNOINVD) +# define XED_SUPPORTS_WBNOINVD +# endif +# if !defined(XED_VIA_ENABLED) +# define XED_VIA_ENABLED +# endif +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-category-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-category-enum.h new file mode 100644 index 0000000..7bf6e21 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-category-enum.h @@ -0,0 +1,256 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-category-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CATEGORY_ENUM_H) +# define XED_CATEGORY_ENUM_H +#include "xed-common-hdrs.h" +#define XED_CATEGORY_INVALID_DEFINED 1 +#define XED_CATEGORY_3DNOW_DEFINED 1 +#define XED_CATEGORY_ADOX_ADCX_DEFINED 1 +#define XED_CATEGORY_AES_DEFINED 1 +#define XED_CATEGORY_AMX_TILE_DEFINED 1 +#define XED_CATEGORY_AVX_DEFINED 1 +#define XED_CATEGORY_AVX2_DEFINED 1 +#define XED_CATEGORY_AVX2GATHER_DEFINED 1 +#define XED_CATEGORY_AVX512_DEFINED 1 +#define XED_CATEGORY_AVX512_4FMAPS_DEFINED 1 +#define XED_CATEGORY_AVX512_4VNNIW_DEFINED 1 +#define XED_CATEGORY_AVX512_BITALG_DEFINED 1 +#define XED_CATEGORY_AVX512_VBMI_DEFINED 1 +#define XED_CATEGORY_AVX512_VP2INTERSECT_DEFINED 1 +#define XED_CATEGORY_BINARY_DEFINED 1 +#define XED_CATEGORY_BITBYTE_DEFINED 1 +#define XED_CATEGORY_BLEND_DEFINED 1 +#define XED_CATEGORY_BMI1_DEFINED 1 +#define XED_CATEGORY_BMI2_DEFINED 1 +#define XED_CATEGORY_BROADCAST_DEFINED 1 +#define XED_CATEGORY_CALL_DEFINED 1 +#define XED_CATEGORY_CET_DEFINED 1 +#define XED_CATEGORY_CLDEMOTE_DEFINED 1 +#define XED_CATEGORY_CLFLUSHOPT_DEFINED 1 +#define XED_CATEGORY_CLWB_DEFINED 1 +#define XED_CATEGORY_CLZERO_DEFINED 1 +#define XED_CATEGORY_CMOV_DEFINED 1 +#define XED_CATEGORY_COMPRESS_DEFINED 1 +#define XED_CATEGORY_COND_BR_DEFINED 1 +#define XED_CATEGORY_CONFLICT_DEFINED 1 +#define XED_CATEGORY_CONVERT_DEFINED 1 +#define XED_CATEGORY_DATAXFER_DEFINED 1 +#define XED_CATEGORY_DECIMAL_DEFINED 1 +#define XED_CATEGORY_ENQCMD_DEFINED 1 +#define XED_CATEGORY_EXPAND_DEFINED 1 +#define XED_CATEGORY_FCMOV_DEFINED 1 +#define XED_CATEGORY_FLAGOP_DEFINED 1 +#define XED_CATEGORY_FMA4_DEFINED 1 +#define XED_CATEGORY_FP16_DEFINED 1 +#define XED_CATEGORY_GATHER_DEFINED 1 +#define XED_CATEGORY_GFNI_DEFINED 1 +#define XED_CATEGORY_HRESET_DEFINED 1 +#define XED_CATEGORY_IFMA_DEFINED 1 +#define XED_CATEGORY_INTERRUPT_DEFINED 1 +#define XED_CATEGORY_IO_DEFINED 1 +#define XED_CATEGORY_IOSTRINGOP_DEFINED 1 +#define XED_CATEGORY_KEYLOCKER_DEFINED 1 +#define XED_CATEGORY_KEYLOCKER_WIDE_DEFINED 1 +#define XED_CATEGORY_KMASK_DEFINED 1 +#define XED_CATEGORY_LEGACY_DEFINED 1 +#define XED_CATEGORY_LOGICAL_DEFINED 1 +#define XED_CATEGORY_LOGICAL_FP_DEFINED 1 +#define XED_CATEGORY_LZCNT_DEFINED 1 +#define XED_CATEGORY_MISC_DEFINED 1 +#define XED_CATEGORY_MMX_DEFINED 1 +#define XED_CATEGORY_MOVDIR_DEFINED 1 +#define XED_CATEGORY_MPX_DEFINED 1 +#define XED_CATEGORY_NOP_DEFINED 1 +#define XED_CATEGORY_PCLMULQDQ_DEFINED 1 +#define XED_CATEGORY_PCONFIG_DEFINED 1 +#define XED_CATEGORY_PKU_DEFINED 1 +#define XED_CATEGORY_POP_DEFINED 1 +#define XED_CATEGORY_PREFETCH_DEFINED 1 +#define XED_CATEGORY_PREFETCHWT1_DEFINED 1 +#define XED_CATEGORY_PTWRITE_DEFINED 1 +#define XED_CATEGORY_PUSH_DEFINED 1 +#define XED_CATEGORY_RDPID_DEFINED 1 +#define XED_CATEGORY_RDPRU_DEFINED 1 +#define XED_CATEGORY_RDRAND_DEFINED 1 +#define XED_CATEGORY_RDSEED_DEFINED 1 +#define XED_CATEGORY_RDWRFSGS_DEFINED 1 +#define XED_CATEGORY_RET_DEFINED 1 +#define XED_CATEGORY_ROTATE_DEFINED 1 +#define XED_CATEGORY_SCATTER_DEFINED 1 +#define XED_CATEGORY_SEGOP_DEFINED 1 +#define XED_CATEGORY_SEMAPHORE_DEFINED 1 +#define XED_CATEGORY_SERIALIZE_DEFINED 1 +#define XED_CATEGORY_SETCC_DEFINED 1 +#define XED_CATEGORY_SGX_DEFINED 1 +#define XED_CATEGORY_SHA_DEFINED 1 +#define XED_CATEGORY_SHIFT_DEFINED 1 +#define XED_CATEGORY_SMAP_DEFINED 1 +#define XED_CATEGORY_SSE_DEFINED 1 +#define XED_CATEGORY_STRINGOP_DEFINED 1 +#define XED_CATEGORY_STTNI_DEFINED 1 +#define XED_CATEGORY_SYSCALL_DEFINED 1 +#define XED_CATEGORY_SYSRET_DEFINED 1 +#define XED_CATEGORY_SYSTEM_DEFINED 1 +#define XED_CATEGORY_TBM_DEFINED 1 +#define XED_CATEGORY_TSX_LDTRK_DEFINED 1 +#define XED_CATEGORY_UINTR_DEFINED 1 +#define XED_CATEGORY_UNCOND_BR_DEFINED 1 +#define XED_CATEGORY_VAES_DEFINED 1 +#define XED_CATEGORY_VBMI2_DEFINED 1 +#define XED_CATEGORY_VEX_DEFINED 1 +#define XED_CATEGORY_VFMA_DEFINED 1 +#define XED_CATEGORY_VIA_PADLOCK_DEFINED 1 +#define XED_CATEGORY_VPCLMULQDQ_DEFINED 1 +#define XED_CATEGORY_VTX_DEFINED 1 +#define XED_CATEGORY_WAITPKG_DEFINED 1 +#define XED_CATEGORY_WIDENOP_DEFINED 1 +#define XED_CATEGORY_X87_ALU_DEFINED 1 +#define XED_CATEGORY_XOP_DEFINED 1 +#define XED_CATEGORY_XSAVE_DEFINED 1 +#define XED_CATEGORY_XSAVEOPT_DEFINED 1 +#define XED_CATEGORY_LAST_DEFINED 1 +typedef enum { + XED_CATEGORY_INVALID, + XED_CATEGORY_3DNOW, + XED_CATEGORY_ADOX_ADCX, + XED_CATEGORY_AES, + XED_CATEGORY_AMX_TILE, + XED_CATEGORY_AVX, + XED_CATEGORY_AVX2, + XED_CATEGORY_AVX2GATHER, + XED_CATEGORY_AVX512, + XED_CATEGORY_AVX512_4FMAPS, + XED_CATEGORY_AVX512_4VNNIW, + XED_CATEGORY_AVX512_BITALG, + XED_CATEGORY_AVX512_VBMI, + XED_CATEGORY_AVX512_VP2INTERSECT, + XED_CATEGORY_BINARY, + XED_CATEGORY_BITBYTE, + XED_CATEGORY_BLEND, + XED_CATEGORY_BMI1, + XED_CATEGORY_BMI2, + XED_CATEGORY_BROADCAST, + XED_CATEGORY_CALL, + XED_CATEGORY_CET, + XED_CATEGORY_CLDEMOTE, + XED_CATEGORY_CLFLUSHOPT, + XED_CATEGORY_CLWB, + XED_CATEGORY_CLZERO, + XED_CATEGORY_CMOV, + XED_CATEGORY_COMPRESS, + XED_CATEGORY_COND_BR, + XED_CATEGORY_CONFLICT, + XED_CATEGORY_CONVERT, + XED_CATEGORY_DATAXFER, + XED_CATEGORY_DECIMAL, + XED_CATEGORY_ENQCMD, + XED_CATEGORY_EXPAND, + XED_CATEGORY_FCMOV, + XED_CATEGORY_FLAGOP, + XED_CATEGORY_FMA4, + XED_CATEGORY_FP16, + XED_CATEGORY_GATHER, + XED_CATEGORY_GFNI, + XED_CATEGORY_HRESET, + XED_CATEGORY_IFMA, + XED_CATEGORY_INTERRUPT, + XED_CATEGORY_IO, + XED_CATEGORY_IOSTRINGOP, + XED_CATEGORY_KEYLOCKER, + XED_CATEGORY_KEYLOCKER_WIDE, + XED_CATEGORY_KMASK, + XED_CATEGORY_LEGACY, + XED_CATEGORY_LOGICAL, + XED_CATEGORY_LOGICAL_FP, + XED_CATEGORY_LZCNT, + XED_CATEGORY_MISC, + XED_CATEGORY_MMX, + XED_CATEGORY_MOVDIR, + XED_CATEGORY_MPX, + XED_CATEGORY_NOP, + XED_CATEGORY_PCLMULQDQ, + XED_CATEGORY_PCONFIG, + XED_CATEGORY_PKU, + XED_CATEGORY_POP, + XED_CATEGORY_PREFETCH, + XED_CATEGORY_PREFETCHWT1, + XED_CATEGORY_PTWRITE, + XED_CATEGORY_PUSH, + XED_CATEGORY_RDPID, + XED_CATEGORY_RDPRU, + XED_CATEGORY_RDRAND, + XED_CATEGORY_RDSEED, + XED_CATEGORY_RDWRFSGS, + XED_CATEGORY_RET, + XED_CATEGORY_ROTATE, + XED_CATEGORY_SCATTER, + XED_CATEGORY_SEGOP, + XED_CATEGORY_SEMAPHORE, + XED_CATEGORY_SERIALIZE, + XED_CATEGORY_SETCC, + XED_CATEGORY_SGX, + XED_CATEGORY_SHA, + XED_CATEGORY_SHIFT, + XED_CATEGORY_SMAP, + XED_CATEGORY_SSE, + XED_CATEGORY_STRINGOP, + XED_CATEGORY_STTNI, + XED_CATEGORY_SYSCALL, + XED_CATEGORY_SYSRET, + XED_CATEGORY_SYSTEM, + XED_CATEGORY_TBM, + XED_CATEGORY_TSX_LDTRK, + XED_CATEGORY_UINTR, + XED_CATEGORY_UNCOND_BR, + XED_CATEGORY_VAES, + XED_CATEGORY_VBMI2, + XED_CATEGORY_VEX, + XED_CATEGORY_VFMA, + XED_CATEGORY_VIA_PADLOCK, + XED_CATEGORY_VPCLMULQDQ, + XED_CATEGORY_VTX, + XED_CATEGORY_WAITPKG, + XED_CATEGORY_WIDENOP, + XED_CATEGORY_X87_ALU, + XED_CATEGORY_XOP, + XED_CATEGORY_XSAVE, + XED_CATEGORY_XSAVEOPT, + XED_CATEGORY_LAST +} xed_category_enum_t; + +/// This converts strings to #xed_category_enum_t types. +/// @param s A C-string. +/// @return #xed_category_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_category_enum_t str2xed_category_enum_t(const char* s); +/// This converts strings to #xed_category_enum_t types. +/// @param p An enumeration element of type xed_category_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_category_enum_t2str(const xed_category_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_category_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_category_enum_t xed_category_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-chip-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-chip-enum.h new file mode 100644 index 0000000..857922d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-chip-enum.h @@ -0,0 +1,176 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-chip-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CHIP_ENUM_H) +# define XED_CHIP_ENUM_H +#include "xed-common-hdrs.h" +#define XED_CHIP_INVALID_DEFINED 1 +#define XED_CHIP_I86_DEFINED 1 +#define XED_CHIP_I86FP_DEFINED 1 +#define XED_CHIP_I186_DEFINED 1 +#define XED_CHIP_I186FP_DEFINED 1 +#define XED_CHIP_I286REAL_DEFINED 1 +#define XED_CHIP_I286_DEFINED 1 +#define XED_CHIP_I2186FP_DEFINED 1 +#define XED_CHIP_I386REAL_DEFINED 1 +#define XED_CHIP_I386_DEFINED 1 +#define XED_CHIP_I386FP_DEFINED 1 +#define XED_CHIP_I486REAL_DEFINED 1 +#define XED_CHIP_I486_DEFINED 1 +#define XED_CHIP_PENTIUMREAL_DEFINED 1 +#define XED_CHIP_PENTIUM_DEFINED 1 +#define XED_CHIP_QUARK_DEFINED 1 +#define XED_CHIP_PENTIUMMMXREAL_DEFINED 1 +#define XED_CHIP_PENTIUMMMX_DEFINED 1 +#define XED_CHIP_ALLREAL_DEFINED 1 +#define XED_CHIP_PENTIUMPRO_DEFINED 1 +#define XED_CHIP_PENTIUM2_DEFINED 1 +#define XED_CHIP_PENTIUM3_DEFINED 1 +#define XED_CHIP_PENTIUM4_DEFINED 1 +#define XED_CHIP_P4PRESCOTT_DEFINED 1 +#define XED_CHIP_P4PRESCOTT_NOLAHF_DEFINED 1 +#define XED_CHIP_P4PRESCOTT_VTX_DEFINED 1 +#define XED_CHIP_MEROM_DEFINED 1 +#define XED_CHIP_PENRYN_DEFINED 1 +#define XED_CHIP_PENRYN_E_DEFINED 1 +#define XED_CHIP_NEHALEM_DEFINED 1 +#define XED_CHIP_WESTMERE_DEFINED 1 +#define XED_CHIP_BONNELL_DEFINED 1 +#define XED_CHIP_SALTWELL_DEFINED 1 +#define XED_CHIP_SILVERMONT_DEFINED 1 +#define XED_CHIP_VIA_DEFINED 1 +#define XED_CHIP_AMD_K10_DEFINED 1 +#define XED_CHIP_AMD_BULLDOZER_DEFINED 1 +#define XED_CHIP_AMD_PILEDRIVER_DEFINED 1 +#define XED_CHIP_AMD_ZEN_DEFINED 1 +#define XED_CHIP_AMD_ZENPLUS_DEFINED 1 +#define XED_CHIP_AMD_ZEN2_DEFINED 1 +#define XED_CHIP_AMD_FUTURE_DEFINED 1 +#define XED_CHIP_GOLDMONT_DEFINED 1 +#define XED_CHIP_GOLDMONT_PLUS_DEFINED 1 +#define XED_CHIP_TREMONT_DEFINED 1 +#define XED_CHIP_SNOW_RIDGE_DEFINED 1 +#define XED_CHIP_SANDYBRIDGE_DEFINED 1 +#define XED_CHIP_IVYBRIDGE_DEFINED 1 +#define XED_CHIP_HASWELL_DEFINED 1 +#define XED_CHIP_BROADWELL_DEFINED 1 +#define XED_CHIP_SKYLAKE_DEFINED 1 +#define XED_CHIP_COMET_LAKE_DEFINED 1 +#define XED_CHIP_SKYLAKE_SERVER_DEFINED 1 +#define XED_CHIP_CASCADE_LAKE_DEFINED 1 +#define XED_CHIP_COOPER_LAKE_DEFINED 1 +#define XED_CHIP_KNL_DEFINED 1 +#define XED_CHIP_KNM_DEFINED 1 +#define XED_CHIP_CANNONLAKE_DEFINED 1 +#define XED_CHIP_ICE_LAKE_DEFINED 1 +#define XED_CHIP_ICE_LAKE_SERVER_DEFINED 1 +#define XED_CHIP_TIGER_LAKE_DEFINED 1 +#define XED_CHIP_ALDER_LAKE_DEFINED 1 +#define XED_CHIP_SAPPHIRE_RAPIDS_DEFINED 1 +#define XED_CHIP_FUTURE_DEFINED 1 +#define XED_CHIP_ALL_DEFINED 1 +#define XED_CHIP_LAST_DEFINED 1 +typedef enum { + XED_CHIP_INVALID, + XED_CHIP_I86, + XED_CHIP_I86FP, + XED_CHIP_I186, + XED_CHIP_I186FP, + XED_CHIP_I286REAL, + XED_CHIP_I286, + XED_CHIP_I2186FP, + XED_CHIP_I386REAL, + XED_CHIP_I386, + XED_CHIP_I386FP, + XED_CHIP_I486REAL, + XED_CHIP_I486, + XED_CHIP_PENTIUMREAL, + XED_CHIP_PENTIUM, + XED_CHIP_QUARK, + XED_CHIP_PENTIUMMMXREAL, + XED_CHIP_PENTIUMMMX, + XED_CHIP_ALLREAL, + XED_CHIP_PENTIUMPRO, + XED_CHIP_PENTIUM2, + XED_CHIP_PENTIUM3, + XED_CHIP_PENTIUM4, + XED_CHIP_P4PRESCOTT, + XED_CHIP_P4PRESCOTT_NOLAHF, + XED_CHIP_P4PRESCOTT_VTX, + XED_CHIP_MEROM, + XED_CHIP_PENRYN, + XED_CHIP_PENRYN_E, + XED_CHIP_NEHALEM, + XED_CHIP_WESTMERE, + XED_CHIP_BONNELL, + XED_CHIP_SALTWELL, + XED_CHIP_SILVERMONT, + XED_CHIP_VIA, + XED_CHIP_AMD_K10, + XED_CHIP_AMD_BULLDOZER, + XED_CHIP_AMD_PILEDRIVER, + XED_CHIP_AMD_ZEN, + XED_CHIP_AMD_ZENPLUS, + XED_CHIP_AMD_ZEN2, + XED_CHIP_AMD_FUTURE, + XED_CHIP_GOLDMONT, + XED_CHIP_GOLDMONT_PLUS, + XED_CHIP_TREMONT, + XED_CHIP_SNOW_RIDGE, + XED_CHIP_SANDYBRIDGE, + XED_CHIP_IVYBRIDGE, + XED_CHIP_HASWELL, + XED_CHIP_BROADWELL, + XED_CHIP_SKYLAKE, + XED_CHIP_COMET_LAKE, + XED_CHIP_SKYLAKE_SERVER, + XED_CHIP_CASCADE_LAKE, + XED_CHIP_COOPER_LAKE, + XED_CHIP_KNL, + XED_CHIP_KNM, + XED_CHIP_CANNONLAKE, + XED_CHIP_ICE_LAKE, + XED_CHIP_ICE_LAKE_SERVER, + XED_CHIP_TIGER_LAKE, + XED_CHIP_ALDER_LAKE, + XED_CHIP_SAPPHIRE_RAPIDS, + XED_CHIP_FUTURE, + XED_CHIP_ALL, + XED_CHIP_LAST +} xed_chip_enum_t; + +/// This converts strings to #xed_chip_enum_t types. +/// @param s A C-string. +/// @return #xed_chip_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_chip_enum_t str2xed_chip_enum_t(const char* s); +/// This converts strings to #xed_chip_enum_t types. +/// @param p An enumeration element of type xed_chip_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_chip_enum_t2str(const xed_chip_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_chip_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_chip_enum_t xed_chip_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-chip-features.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-chip-features.h new file mode 100644 index 0000000..a6dd8b0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-chip-features.h @@ -0,0 +1,46 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_CHIP_FEATURES_H) +# define XED_CHIP_FEATURES_H + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-isa-set-enum.h" /* generated */ +#include "xed-chip-enum.h" /* generated */ + +#define XED_FEATURE_VECTOR_MAX 5 +/// @ingroup ISASET +typedef struct +{ + xed_uint64_t f[XED_FEATURE_VECTOR_MAX]; +} xed_chip_features_t; + + +/// fill in the contents of p with the vector of chip features. +XED_DLL_EXPORT void +xed_get_chip_features(xed_chip_features_t* p, xed_chip_enum_t chip); + +/// present = 1 to turn the feature on. present=0 to remove the feature. +XED_DLL_EXPORT void +xed_modify_chip_features(xed_chip_features_t* p, + xed_isa_set_enum_t isa_set, + xed_bool_t present); + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-common-defs.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-common-defs.h new file mode 100644 index 0000000..4f2d31f --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-common-defs.h @@ -0,0 +1,47 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-common-defs.h +/// @brief some pervasive defines + + + +#ifndef XED_COMMON_DEFS_H +# define XED_COMMON_DEFS_H + + // for most things it is 4, but one 64b mov allows 8 +#define XED_MAX_DISPLACEMENT_BYTES 8 + + // for most things it is max 4, but one 64b mov allows 8. +#define XED_MAX_IMMEDIATE_BYTES 8 + +#define XED_MAX_INSTRUCTION_BYTES 15 + + +#define XED_BYTE_MASK(x) ((x) & 0xFF) +#define XED_BYTE_CAST(x) (XED_STATIC_CAST(xed_uint8_t,x)) + +#endif + + + + + + + + + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-common-hdrs.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-common-hdrs.h new file mode 100644 index 0000000..a30a3e0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-common-hdrs.h @@ -0,0 +1,71 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-common-hdrs.h +/// + + + +#ifndef XED_COMMON_HDRS_H +# define XED_COMMON_HDRS_H + + + +#if defined(__FreeBSD__) || defined(__NetBSD__) +# define XED_BSD +#endif +#if defined(__linux__) +# define XED_LINUX +#endif +#if defined(_MSC_VER) +# define XED_WINDOWS +#endif +#if defined(__APPLE__) +# define XED_MAC +#endif + + +#if defined(XED_DLL) +// __declspec(dllexport) works with GNU GCC or MS compilers, but not ICC +// on linux + +# if defined(XED_WINDOWS) +# define XED_DLL_EXPORT __declspec(dllexport) +# define XED_DLL_IMPORT __declspec(dllimport) +# elif defined(XED_LINUX) || defined(XED_BSD) || defined(XED_MAC) +# define XED_DLL_EXPORT __attribute__((visibility("default"))) +# define XED_DLL_IMPORT +# else +# define XED_DLL_EXPORT +# define XED_DLL_IMPORT +# endif + +# if defined(XED_BUILD) + /* when building XED, we export symbols */ +# define XED_DLL_GLOBAL XED_DLL_EXPORT +# else + /* when building XED clients, we import symbols */ +# define XED_DLL_GLOBAL XED_DLL_IMPORT +# endif +#else +# define XED_DLL_EXPORT +# define XED_DLL_IMPORT +# define XED_DLL_GLOBAL +#endif + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-convert-table-init.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-convert-table-init.h new file mode 100644 index 0000000..339c977 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-convert-table-init.h @@ -0,0 +1,36 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-convert-table-init.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CONVERT_TABLE_INIT_H) +# define XED_CONVERT_TABLE_INIT_H +#include "xed-internal-header.h" +typedef struct { + + const char** table_name; + + xed_operand_enum_t opnd; + + unsigned int limit; + +} xed_convert_table_t; +extern xed_convert_table_t xed_convert_table[XED_OPERAND_CONVERT_LAST]; +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-cpuid-bit-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-cpuid-bit-enum.h new file mode 100644 index 0000000..fec7a4f --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-cpuid-bit-enum.h @@ -0,0 +1,254 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-cpuid-bit-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CPUID_BIT_ENUM_H) +# define XED_CPUID_BIT_ENUM_H +#include "xed-common-hdrs.h" +#define XED_CPUID_BIT_INVALID_DEFINED 1 +#define XED_CPUID_BIT_ADOXADCX_DEFINED 1 +#define XED_CPUID_BIT_AES_DEFINED 1 +#define XED_CPUID_BIT_AMX_BF16_DEFINED 1 +#define XED_CPUID_BIT_AMX_INT8_DEFINED 1 +#define XED_CPUID_BIT_AMX_TILES_DEFINED 1 +#define XED_CPUID_BIT_AVX_DEFINED 1 +#define XED_CPUID_BIT_AVX2_DEFINED 1 +#define XED_CPUID_BIT_AVX512BW_DEFINED 1 +#define XED_CPUID_BIT_AVX512CD_DEFINED 1 +#define XED_CPUID_BIT_AVX512DQ_DEFINED 1 +#define XED_CPUID_BIT_AVX512ER_DEFINED 1 +#define XED_CPUID_BIT_AVX512F_DEFINED 1 +#define XED_CPUID_BIT_AVX512IFMA_DEFINED 1 +#define XED_CPUID_BIT_AVX512PF_DEFINED 1 +#define XED_CPUID_BIT_AVX512VBMI_DEFINED 1 +#define XED_CPUID_BIT_AVX512VL_DEFINED 1 +#define XED_CPUID_BIT_AVX512_4FMAPS_DEFINED 1 +#define XED_CPUID_BIT_AVX512_4VNNIW_DEFINED 1 +#define XED_CPUID_BIT_AVX512_BITALG_DEFINED 1 +#define XED_CPUID_BIT_AVX512_FP16_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VBMI2_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VNNI_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VP2INTERSECT_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VPOPCNTDQ_DEFINED 1 +#define XED_CPUID_BIT_AVX_VNNI_DEFINED 1 +#define XED_CPUID_BIT_BF16_DEFINED 1 +#define XED_CPUID_BIT_BMI1_DEFINED 1 +#define XED_CPUID_BIT_BMI2_DEFINED 1 +#define XED_CPUID_BIT_CET_DEFINED 1 +#define XED_CPUID_BIT_CLDEMOTE_DEFINED 1 +#define XED_CPUID_BIT_CLFLUSH_DEFINED 1 +#define XED_CPUID_BIT_CLFLUSHOPT_DEFINED 1 +#define XED_CPUID_BIT_CLWB_DEFINED 1 +#define XED_CPUID_BIT_CMPXCHG16B_DEFINED 1 +#define XED_CPUID_BIT_ENQCMD_DEFINED 1 +#define XED_CPUID_BIT_F16C_DEFINED 1 +#define XED_CPUID_BIT_FMA_DEFINED 1 +#define XED_CPUID_BIT_FXSAVE_DEFINED 1 +#define XED_CPUID_BIT_GFNI_DEFINED 1 +#define XED_CPUID_BIT_HRESET_DEFINED 1 +#define XED_CPUID_BIT_INTEL64_DEFINED 1 +#define XED_CPUID_BIT_INTELPT_DEFINED 1 +#define XED_CPUID_BIT_INVPCID_DEFINED 1 +#define XED_CPUID_BIT_KLENABLED_DEFINED 1 +#define XED_CPUID_BIT_KLSUPPORTED_DEFINED 1 +#define XED_CPUID_BIT_KLWIDE_DEFINED 1 +#define XED_CPUID_BIT_LAHF_DEFINED 1 +#define XED_CPUID_BIT_LZCNT_DEFINED 1 +#define XED_CPUID_BIT_MCOMMIT_DEFINED 1 +#define XED_CPUID_BIT_MONITOR_DEFINED 1 +#define XED_CPUID_BIT_MONITORX_DEFINED 1 +#define XED_CPUID_BIT_MOVDIR64B_DEFINED 1 +#define XED_CPUID_BIT_MOVDIRI_DEFINED 1 +#define XED_CPUID_BIT_MOVEBE_DEFINED 1 +#define XED_CPUID_BIT_MPX_DEFINED 1 +#define XED_CPUID_BIT_OSPKU_DEFINED 1 +#define XED_CPUID_BIT_OSXSAVE_DEFINED 1 +#define XED_CPUID_BIT_PCLMULQDQ_DEFINED 1 +#define XED_CPUID_BIT_PCONFIG_DEFINED 1 +#define XED_CPUID_BIT_PKU_DEFINED 1 +#define XED_CPUID_BIT_POPCNT_DEFINED 1 +#define XED_CPUID_BIT_PREFETCHW_DEFINED 1 +#define XED_CPUID_BIT_PREFETCHWT1_DEFINED 1 +#define XED_CPUID_BIT_PTWRITE_DEFINED 1 +#define XED_CPUID_BIT_RDP_DEFINED 1 +#define XED_CPUID_BIT_RDPRU_DEFINED 1 +#define XED_CPUID_BIT_RDRAND_DEFINED 1 +#define XED_CPUID_BIT_RDSEED_DEFINED 1 +#define XED_CPUID_BIT_RDTSCP_DEFINED 1 +#define XED_CPUID_BIT_RDWRFSGS_DEFINED 1 +#define XED_CPUID_BIT_RTM_DEFINED 1 +#define XED_CPUID_BIT_SERIALIZE_DEFINED 1 +#define XED_CPUID_BIT_SGX_DEFINED 1 +#define XED_CPUID_BIT_SHA_DEFINED 1 +#define XED_CPUID_BIT_SMAP_DEFINED 1 +#define XED_CPUID_BIT_SMX_DEFINED 1 +#define XED_CPUID_BIT_SNP_DEFINED 1 +#define XED_CPUID_BIT_SSE_DEFINED 1 +#define XED_CPUID_BIT_SSE2_DEFINED 1 +#define XED_CPUID_BIT_SSE3_DEFINED 1 +#define XED_CPUID_BIT_SSE4_DEFINED 1 +#define XED_CPUID_BIT_SSE42_DEFINED 1 +#define XED_CPUID_BIT_SSE4A_DEFINED 1 +#define XED_CPUID_BIT_SSSE3_DEFINED 1 +#define XED_CPUID_BIT_TSX_LDTRK_DEFINED 1 +#define XED_CPUID_BIT_UINTR_DEFINED 1 +#define XED_CPUID_BIT_VAES_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_AES_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_AES_EN_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_PMM_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_PMM_EN_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_RNG_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_RNG_EN_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_SHA_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_SHA_EN_DEFINED 1 +#define XED_CPUID_BIT_VMX_DEFINED 1 +#define XED_CPUID_BIT_VPCLMULQDQ_DEFINED 1 +#define XED_CPUID_BIT_WAITPKG_DEFINED 1 +#define XED_CPUID_BIT_WBNOINVD_DEFINED 1 +#define XED_CPUID_BIT_XSAVE_DEFINED 1 +#define XED_CPUID_BIT_XSAVEC_DEFINED 1 +#define XED_CPUID_BIT_XSAVEOPT_DEFINED 1 +#define XED_CPUID_BIT_XSAVES_DEFINED 1 +#define XED_CPUID_BIT_LAST_DEFINED 1 +typedef enum { + XED_CPUID_BIT_INVALID, + XED_CPUID_BIT_ADOXADCX, + XED_CPUID_BIT_AES, + XED_CPUID_BIT_AMX_BF16, + XED_CPUID_BIT_AMX_INT8, + XED_CPUID_BIT_AMX_TILES, + XED_CPUID_BIT_AVX, + XED_CPUID_BIT_AVX2, + XED_CPUID_BIT_AVX512BW, + XED_CPUID_BIT_AVX512CD, + XED_CPUID_BIT_AVX512DQ, + XED_CPUID_BIT_AVX512ER, + XED_CPUID_BIT_AVX512F, + XED_CPUID_BIT_AVX512IFMA, + XED_CPUID_BIT_AVX512PF, + XED_CPUID_BIT_AVX512VBMI, + XED_CPUID_BIT_AVX512VL, + XED_CPUID_BIT_AVX512_4FMAPS, + XED_CPUID_BIT_AVX512_4VNNIW, + XED_CPUID_BIT_AVX512_BITALG, + XED_CPUID_BIT_AVX512_FP16, + XED_CPUID_BIT_AVX512_VBMI2, + XED_CPUID_BIT_AVX512_VNNI, + XED_CPUID_BIT_AVX512_VP2INTERSECT, + XED_CPUID_BIT_AVX512_VPOPCNTDQ, + XED_CPUID_BIT_AVX_VNNI, + XED_CPUID_BIT_BF16, + XED_CPUID_BIT_BMI1, + XED_CPUID_BIT_BMI2, + XED_CPUID_BIT_CET, + XED_CPUID_BIT_CLDEMOTE, + XED_CPUID_BIT_CLFLUSH, + XED_CPUID_BIT_CLFLUSHOPT, + XED_CPUID_BIT_CLWB, + XED_CPUID_BIT_CMPXCHG16B, + XED_CPUID_BIT_ENQCMD, + XED_CPUID_BIT_F16C, + XED_CPUID_BIT_FMA, + XED_CPUID_BIT_FXSAVE, + XED_CPUID_BIT_GFNI, + XED_CPUID_BIT_HRESET, + XED_CPUID_BIT_INTEL64, + XED_CPUID_BIT_INTELPT, + XED_CPUID_BIT_INVPCID, + XED_CPUID_BIT_KLENABLED, + XED_CPUID_BIT_KLSUPPORTED, + XED_CPUID_BIT_KLWIDE, + XED_CPUID_BIT_LAHF, + XED_CPUID_BIT_LZCNT, + XED_CPUID_BIT_MCOMMIT, + XED_CPUID_BIT_MONITOR, + XED_CPUID_BIT_MONITORX, + XED_CPUID_BIT_MOVDIR64B, + XED_CPUID_BIT_MOVDIRI, + XED_CPUID_BIT_MOVEBE, + XED_CPUID_BIT_MPX, + XED_CPUID_BIT_OSPKU, + XED_CPUID_BIT_OSXSAVE, + XED_CPUID_BIT_PCLMULQDQ, + XED_CPUID_BIT_PCONFIG, + XED_CPUID_BIT_PKU, + XED_CPUID_BIT_POPCNT, + XED_CPUID_BIT_PREFETCHW, + XED_CPUID_BIT_PREFETCHWT1, + XED_CPUID_BIT_PTWRITE, + XED_CPUID_BIT_RDP, + XED_CPUID_BIT_RDPRU, + XED_CPUID_BIT_RDRAND, + XED_CPUID_BIT_RDSEED, + XED_CPUID_BIT_RDTSCP, + XED_CPUID_BIT_RDWRFSGS, + XED_CPUID_BIT_RTM, + XED_CPUID_BIT_SERIALIZE, + XED_CPUID_BIT_SGX, + XED_CPUID_BIT_SHA, + XED_CPUID_BIT_SMAP, + XED_CPUID_BIT_SMX, + XED_CPUID_BIT_SNP, + XED_CPUID_BIT_SSE, + XED_CPUID_BIT_SSE2, + XED_CPUID_BIT_SSE3, + XED_CPUID_BIT_SSE4, + XED_CPUID_BIT_SSE42, + XED_CPUID_BIT_SSE4A, + XED_CPUID_BIT_SSSE3, + XED_CPUID_BIT_TSX_LDTRK, + XED_CPUID_BIT_UINTR, + XED_CPUID_BIT_VAES, + XED_CPUID_BIT_VIA_PADLOCK_AES, + XED_CPUID_BIT_VIA_PADLOCK_AES_EN, + XED_CPUID_BIT_VIA_PADLOCK_PMM, + XED_CPUID_BIT_VIA_PADLOCK_PMM_EN, + XED_CPUID_BIT_VIA_PADLOCK_RNG, + XED_CPUID_BIT_VIA_PADLOCK_RNG_EN, + XED_CPUID_BIT_VIA_PADLOCK_SHA, + XED_CPUID_BIT_VIA_PADLOCK_SHA_EN, + XED_CPUID_BIT_VMX, + XED_CPUID_BIT_VPCLMULQDQ, + XED_CPUID_BIT_WAITPKG, + XED_CPUID_BIT_WBNOINVD, + XED_CPUID_BIT_XSAVE, + XED_CPUID_BIT_XSAVEC, + XED_CPUID_BIT_XSAVEOPT, + XED_CPUID_BIT_XSAVES, + XED_CPUID_BIT_LAST +} xed_cpuid_bit_enum_t; + +/// This converts strings to #xed_cpuid_bit_enum_t types. +/// @param s A C-string. +/// @return #xed_cpuid_bit_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_cpuid_bit_enum_t str2xed_cpuid_bit_enum_t(const char* s); +/// This converts strings to #xed_cpuid_bit_enum_t types. +/// @param p An enumeration element of type xed_cpuid_bit_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_cpuid_bit_enum_t2str(const xed_cpuid_bit_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_cpuid_bit_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_cpuid_bit_enum_t xed_cpuid_bit_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-cpuid-rec.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-cpuid-rec.h new file mode 100644 index 0000000..420f811 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-cpuid-rec.h @@ -0,0 +1,55 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#ifndef XED_CPUID_REC_H +# define XED_CPUID_REC_H +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-cpuid-bit-enum.h" +#include "xed-isa-set-enum.h" + + +typedef struct { + xed_uint32_t leaf; // cpuid leaf + xed_uint32_t subleaf; // cpuid subleaf + xed_uint32_t bit; // the bit number for the feature + xed_reg_enum_t reg; // the register containing the bit (EAX,EBX,ECX,EDX) +} xed_cpuid_rec_t; + +#define XED_MAX_CPUID_BITS_PER_ISA_SET (4) + +/// Returns the name of the i'th cpuid bit associated with this isa-set. +/// Call this repeatedly, with 0 <= i < +/// XED_MAX_CPUID_BITS_PER_ISA_SET. Give up when i == +/// XED_MAX_CPUID_BITS_PER_ISA_SET or the return value is +/// XED_CPUID_BIT_INVALID. +XED_DLL_EXPORT +xed_cpuid_bit_enum_t +xed_get_cpuid_bit_for_isa_set(xed_isa_set_enum_t isaset, + xed_uint_t i); + +/// This provides the details of the CPUID bit specification, if the +/// enumeration value is not sufficient. Returns 1 on success and fills in +/// the structure pointed to by p. Returns 0 on failure. +XED_DLL_EXPORT +xed_int_t +xed_get_cpuid_rec(xed_cpuid_bit_enum_t cpuid_bit, + xed_cpuid_rec_t* p); + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-decode.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-decode.h new file mode 100644 index 0000000..2061d83 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-decode.h @@ -0,0 +1,69 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decode.h + + +#ifndef XED_DECODE_H +# define XED_DECODE_H + +#include "xed-decoded-inst.h" +#include "xed-error-enum.h" +#include "xed-chip-features.h" + +/// This is the main interface to the decoder. +/// @param xedd the decoded instruction of type #xed_decoded_inst_t . Mode/state sent in via xedd; See the #xed_state_t +/// @param itext the pointer to the array of instruction text bytes +/// @param bytes the length of the itext input array. 1 to 15 bytes, anything more is ignored. +/// @return #xed_error_enum_t indicating success (#XED_ERROR_NONE) or failure. Note failure can be due to not +/// enough bytes in the input array. +/// +/// The maximum instruction is 15B and XED will tell you how long the +/// actual instruction is via an API function call +/// xed_decoded_inst_get_length(). However, it is not always safe or +/// advisable for XED to read 15 bytes if the decode location is at the +/// boundary of some sort of protection limit. For example, if one is +/// decoding near the end of a page and the XED user does not want to cause +/// extra page faults, one might send in the number of bytes that would +/// stop at the page boundary. In this case, XED might not be able to +/// decode the instruction and would return an error. The XED user would +/// then have to decide if it was safe to touch the next page and try again +/// to decode with more bytes. Also sometimes the user process does not +/// have read access to the next page and this allows the user to prevent +/// XED from causing process termination by limiting the memory range that +/// XED will access. +/// +/// @ingroup DEC +XED_DLL_EXPORT xed_error_enum_t +xed_decode(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes); + +/// @ingroup DEC +/// See #xed_decode(). This version of the decode API adds a CPUID feature +/// vector to support restricting decode based on both a specified chip via +/// #xed_decoded_inst_set_input_chip() and a modify-able cpuid feature +/// vector obtained from #xed_get_chip_features(). +XED_DLL_EXPORT xed_error_enum_t +xed_decode_with_features(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes, + xed_chip_features_t* features); + + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-decoded-inst-api.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-decoded-inst-api.h new file mode 100644 index 0000000..39a8f2f --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-decoded-inst-api.h @@ -0,0 +1,699 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decoded-inst-api.h +/// + +#if !defined(XED_DECODED_INST_API_H) +# define XED_DECODED_INST_API_H + +#include "xed-decoded-inst.h" +#include "xed-operand-accessors.h" +#include "xed-state.h" +#include "xed-operand-values-interface.h" +#include "xed-print-info.h" + +/////////////////////////////////////////////////////// +/// API +/////////////////////////////////////////////////////// + +/// @name xed_decoded_inst_t High-level accessors +//@{ +/// @ingroup DEC +/// Return true if the instruction is valid +static XED_INLINE xed_bool_t +xed_decoded_inst_valid(const xed_decoded_inst_t* p ) { + return XED_STATIC_CAST(xed_bool_t,(p->_inst != 0)); +} +/// @ingroup DEC +/// Return the #xed_inst_t structure for this instruction. This is the +/// route to the basic operands form information. +static XED_INLINE const xed_inst_t* +xed_decoded_inst_inst( const xed_decoded_inst_t* p) { + return p->_inst; +} + + +/// @ingroup DEC +/// Return the instruction #xed_category_enum_t enumeration +static XED_INLINE xed_category_enum_t +xed_decoded_inst_get_category(const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_category(p->_inst); +} +/// @ingroup DEC +/// Return the instruction #xed_extension_enum_t enumeration +static XED_INLINE xed_extension_enum_t +xed_decoded_inst_get_extension( const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_extension(p->_inst); +} +/// @ingroup DEC +/// Return the instruction #xed_isa_set_enum_t enumeration +static XED_INLINE xed_isa_set_enum_t +xed_decoded_inst_get_isa_set(xed_decoded_inst_t const* const p) { + xed_assert(p->_inst != 0); + return xed_inst_isa_set(p->_inst); +} +/// @ingroup DEC +/// Return the instruction #xed_iclass_enum_t enumeration. +static XED_INLINE xed_iclass_enum_t +xed_decoded_inst_get_iclass( const xed_decoded_inst_t* p){ + xed_assert(p->_inst != 0); + return xed_inst_iclass(p->_inst); +} + +/// @name xed_decoded_inst_t Attributes and properties +//@{ +/// @ingroup DEC +/// Returns 1 if the attribute is defined for this instruction. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_get_attribute(const xed_decoded_inst_t* p, + xed_attribute_enum_t attr); + +/// @ingroup DEC +/// Returns the attribute bitvector +XED_DLL_EXPORT xed_attributes_t +xed_decoded_inst_get_attributes(const xed_decoded_inst_t* p); +//@} + +/// @ingroup DEC +/// Returns 1 if the instruction is xacquire. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_is_xacquire(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 1 if the instruction is xrelease. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_is_xrelease(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 1 if the instruction has mpx prefix. +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_has_mpx_prefix(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns the modrm byte +XED_DLL_EXPORT xed_uint8_t +xed_decoded_inst_get_modrm(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 1 iff the instruction uses destination-masking. This is 0 for +/// blend operations that use their mask field as a control. +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_masked_vector_operation(xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Returns 128, 256 or 512 for operations in the VEX, EVEX (or XOP) +/// encoding space and returns 0 for (most) nonvector operations. +/// This usually the content of the VEX.L or EVEX.LL field, reinterpreted. +/// Some GPR instructions (like the BMI1/BMI2) are encoded in the VEX space +/// and return non-zero values from this API. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_vector_length_bits(xed_decoded_inst_t const* const p); + +/// @ingroup DEC +/// Returns the number of legacy prefixes. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_nprefixes(const xed_decoded_inst_t* p); + +//@} + + +/// @name xed_decoded_inst_t Operands +//@{ +/// @ingroup DEC +/// Obtain a constant pointer to the operands +static XED_INLINE const xed_operand_values_t* +xed_decoded_inst_operands_const(const xed_decoded_inst_t* p) { + return p; +} +/// @ingroup DEC +/// Obtain a non-constant pointer to the operands +static XED_INLINE xed_operand_values_t* +xed_decoded_inst_operands(xed_decoded_inst_t* p) { + return p; +} + +/// Return the length in bits of the operand_index'th operand. +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_length_bits(const xed_decoded_inst_t* p, + unsigned int operand_index); + + +/// Deprecated -- returns the length in bytes of the operand_index'th +/// operand. Use #xed_decoded_inst_operand_length_bits() instead. +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_length(const xed_decoded_inst_t* p, + unsigned int operand_index); + + +/// Return the number of operands +/// @ingroup DEC +static XED_INLINE unsigned int +xed_decoded_inst_noperands(const xed_decoded_inst_t* p) { + unsigned int noperands = xed_inst_noperands(xed_decoded_inst_inst(p)); + return noperands; +} + + +/// Return the number of element in the operand (for SSE and AVX operands) +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_elements(const xed_decoded_inst_t* p, + unsigned int operand_index); + +/// Return the size of an element in bits (for SSE and AVX operands) +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_operand_element_size_bits(const xed_decoded_inst_t* p, + unsigned int operand_index); + +/// Return the type of an element of type #xed_operand_element_type_enum_t +/// (for SSE and AVX operands) +/// @ingroup DEC +XED_DLL_EXPORT xed_operand_element_type_enum_t +xed_decoded_inst_operand_element_type(const xed_decoded_inst_t* p, + unsigned int operand_index); + +/// Interpret the operand action in light of AVX512 masking and +/// zeroing/merging. If masking and merging are used together, the dest +/// operand may also be read. If masking and merging are used together, +/// the elemnents of dest operand register may be conditionally written (so +/// that input values live on in the output register). +/// @ingroup DEC +XED_DLL_EXPORT xed_operand_action_enum_t +xed_decoded_inst_operand_action(const xed_decoded_inst_t* p, + unsigned int operand_index); + +//@} + +/// @name xed_decoded_inst_t AVX512 Masking +//@{ +/// Returns true if the instruction uses write-masking +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_masking(const xed_decoded_inst_t* p); + +/// Returns true if the instruction uses write-masking with merging +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_merging(const xed_decoded_inst_t* p); + +/// Returns true if the instruction uses write-masking with zeroing +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_zeroing(const xed_decoded_inst_t* p); + +/// Returns the maximum number elements processed for an AVX512 vector +/// instruction. Scalars report 1 element. +/// @ingroup DEC +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_avx512_dest_elements(const xed_decoded_inst_t* p); + +//@} + +/// @name xed_decoded_inst_t Initialization +//@{ +/// @ingroup DEC +/// Zero the decode structure, but set the machine state/mode +/// information. Re-initializes all operands. +XED_DLL_EXPORT void +xed_decoded_inst_zero_set_mode(xed_decoded_inst_t* p, + const xed_state_t* dstate); + +/// @ingroup DEC +/// Zero the decode structure, but preserve the existing machine state/mode +/// information. Re-initializes all operands. +XED_DLL_EXPORT void xed_decoded_inst_zero_keep_mode(xed_decoded_inst_t* p); + + +/// @ingroup DEC +/// Zero the decode structure completely. Re-initializes all operands. +XED_DLL_EXPORT void xed_decoded_inst_zero(xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Set the machine mode and stack addressing width directly. This is NOT a +/// full initialization; Call #xed_decoded_inst_zero() before using this if +/// you want a clean slate. +static XED_INLINE void +xed_decoded_inst_set_mode(xed_decoded_inst_t* p, + xed_machine_mode_enum_t mmode, + xed_address_width_enum_t stack_addr_width) +{ + xed_state_t dstate; + dstate.mmode = mmode; + dstate.stack_addr_width = stack_addr_width; + xed_operand_values_set_mode(p, &dstate); +} + + + +/// @ingroup DEC +/// Zero the decode structure, but copy the existing machine state/mode +/// information from the supplied operands pointer. Same as +/// #xed_decoded_inst_zero_keep_mode. +XED_DLL_EXPORT void +xed_decoded_inst_zero_keep_mode_from_operands( + xed_decoded_inst_t* p, + const xed_operand_values_t* operands); + +/// @name xed_decoded_inst_t Length +//@{ +/// @ingroup DEC +/// Return the length of the decoded instruction in bytes. +static XED_INLINE xed_uint_t +xed_decoded_inst_get_length(const xed_decoded_inst_t* p) { + return p->_decoded_length; +} + +//@} + + +/// @name xed_decoded_inst_t get Byte +//@{ +/// @ingroup DEC +/// Read itext byte. +static XED_INLINE xed_uint8_t +xed_decoded_inst_get_byte(const xed_decoded_inst_t* p, xed_uint_t byte_index) +{ + /// Read a whole byte from the normal input bytes. + xed_uint8_t out = p->_byte_array._dec[byte_index]; + return out; +} + +//@} + +/// @name Modes +//@{ +/// @ingroup DEC +/// Returns 16/32/64 indicating the machine mode with in bits. This is +/// derived from the input mode information. +static XED_INLINE xed_uint_t +xed_decoded_inst_get_machine_mode_bits(const xed_decoded_inst_t* p) { + xed_uint_t mode = xed3_operand_get_mode(p); + if (mode == 2) return 64; + if (mode == 1) return 32; + return 16; +} +/// @ingroup DEC +/// Returns 16/32/64 indicating the stack addressing mode with in +/// bits. This is derived from the input mode information. +static XED_INLINE xed_uint_t +xed_decoded_inst_get_stack_address_mode_bits(const xed_decoded_inst_t* p) { + xed_uint_t smode = xed3_operand_get_smode(p); + if (smode == 2) return 64; + if (smode == 1) return 32; + return 16; +} + +/// Returns the operand width in bits: 8/16/32/64. This is different than +/// the #xed_operand_values_get_effective_operand_width() which only +/// returns 16/32/64. This factors in the BYTEOP attribute when computing +/// its return value. This function provides a information for that is only +/// useful for (scalable) GPR-operations. Individual operands have more +/// specific information available from +/// #xed_decoded_inst_operand_element_size_bits() +/// @ingroup DEC +XED_DLL_EXPORT xed_uint32_t +xed_decoded_inst_get_operand_width(const xed_decoded_inst_t* p); + +/// Return the user-specified #xed_chip_enum_t chip name, or +/// XED_CHIP_INVALID if not set. +/// @ingroup DEC +static XED_INLINE xed_chip_enum_t +xed_decoded_inst_get_input_chip(const xed_decoded_inst_t* p) { + return xed3_operand_get_chip(p); +} + +/// Set a user-specified #xed_chip_enum_t chip name for restricting decode +/// @ingroup DEC +static XED_INLINE void +xed_decoded_inst_set_input_chip(xed_decoded_inst_t* p, + xed_chip_enum_t chip) { + xed3_operand_set_chip(p,chip); +} + + +/// Indicate if this decoded instruction is valid for the specified +/// #xed_chip_enum_t chip +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_valid_for_chip(xed_decoded_inst_t const* const p, + xed_chip_enum_t chip); + +//@} + + + + +/// @name IFORM handling +//@{ + +/// @ingroup DEC +/// Return the instruction iform enum of type #xed_iform_enum_t . +static XED_INLINE xed_iform_enum_t +xed_decoded_inst_get_iform_enum(const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_iform_enum(p->_inst); +} + +/// @ingroup DEC +/// Return the instruction zero-based iform number based on masking the +/// corresponding #xed_iform_enum_t. This value is suitable for +/// dispatching. The maximum value for a particular iclass is provided by +/// #xed_iform_max_per_iclass() . +static XED_INLINE unsigned int +xed_decoded_inst_get_iform_enum_dispatch(const xed_decoded_inst_t* p) { + xed_assert(p->_inst != 0); + return xed_inst_iform_enum(p->_inst) - + xed_iform_first_per_iclass(xed_inst_iclass(p->_inst)); +} +//@} + + + + +/// @name xed_decoded_inst_t Printers +//@{ +/// @ingroup PRINT +/// Print out all the information about the decoded instruction to the +/// buffer buf whose length is maximally buflen. This is for debugging. +XED_DLL_EXPORT void +xed_decoded_inst_dump(const xed_decoded_inst_t* p, char* buf, int buflen); + + + +/// @ingroup PRINT +/// Print the instruction information in a verbose format. +/// This is for debugging. +/// @param p a #xed_decoded_inst_t for a decoded instruction +/// @param buf a buffer to write the disassembly in to. +/// @param buflen maximum length of the disassembly buffer +/// @param runtime_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches. +/// @return Returns 0 if the disassembly fails, 1 otherwise. +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_dump_xed_format(const xed_decoded_inst_t* p, + char* buf, + int buflen, + xed_uint64_t runtime_address) ; + + +/// Disassemble the decoded instruction using the specified syntax. +/// The output buffer must be at least 25 bytes long. Returns true if +/// disassembly proceeded without errors. +/// @param syntax a #xed_syntax_enum_t the specifies the disassembly format +/// @param xedd a #xed_decoded_inst_t for a decoded instruction +/// @param out_buffer a buffer to write the disassembly in to. +/// @param buffer_len maximum length of the disassembly buffer +/// @param runtime_instruction_address the address of the instruction being disassembled. If zero, the offset is printed for relative branches. If nonzero, XED attempts to print the target address for relative branches. +/// @param context A void* used only for the call back routine for symbolic disassembly if one is provided. Can be zero. +/// @param symbolic_callback A function pointer for obtaining symbolic disassembly. Can be zero. +/// @return Returns 0 if the disassembly fails, 1 otherwise. +///@ingroup PRINT +XED_DLL_EXPORT xed_bool_t +xed_format_context(xed_syntax_enum_t syntax, + const xed_decoded_inst_t* xedd, + char* out_buffer, + int buffer_len, + xed_uint64_t runtime_instruction_address, + void* context, + xed_disassembly_callback_fn_t symbolic_callback); + + +/// @ingroup PRINT +/// Disassemble the instruction information to a buffer. See the +/// #xed_print_info_t for the required public fields of the argument. +/// This is the preferred method of doing disassembly. +/// The output buffer must be at least 25 bytes long. +/// @param pi a #xed_print_info_t +/// @return Returns 0 if the disassembly fails, 1 otherwise. +XED_DLL_EXPORT xed_bool_t +xed_format_generic(xed_print_info_t* pi); + +//@} + +/// @name xed_decoded_inst_t Operand Field Details +//@{ +/// @ingroup DEC +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_seg_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_base_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx); +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_index_reg(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_scale(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_int64_t +xed_decoded_inst_get_memory_displacement(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +/// Result in BYTES +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_memory_displacement_width(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +/// Result in BITS +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_memory_displacement_width_bits(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_int32_t +xed_decoded_inst_get_branch_displacement(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Result in BYTES +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_branch_displacement_width(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Result in BITS +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_branch_displacement_width_bits( + const xed_decoded_inst_t* p); +/// @ingroup DEC +XED_DLL_EXPORT xed_uint64_t +xed_decoded_inst_get_unsigned_immediate(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return true if the first immediate (IMM0) is signed +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_immediate_is_signed(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return the immediate width in BYTES. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_immediate_width(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return the immediate width in BITS. +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_get_immediate_width_bits(const xed_decoded_inst_t* p); +/// @ingroup DEC +XED_DLL_EXPORT xed_int32_t +xed_decoded_inst_get_signed_immediate(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return the second immediate. +static XED_INLINE xed_uint8_t +xed_decoded_inst_get_second_immediate(const xed_decoded_inst_t* p) { + return xed3_operand_get_uimm1(p); +} + +/// @ingroup DEC +/// Return the specified register operand. The specifier is of type +/// #xed_operand_enum_t . +XED_DLL_EXPORT xed_reg_enum_t +xed_decoded_inst_get_reg(const xed_decoded_inst_t* p, + xed_operand_enum_t reg_operand); + + +/// See the comment on xed_decoded_inst_uses_rflags(). This can return +/// 0 if the flags are really not used by this instruction. +/// @ingroup DEC +XED_DLL_EXPORT const xed_simple_flag_t* +xed_decoded_inst_get_rflags_info( const xed_decoded_inst_t* p ); + +/// This returns 1 if the flags are read or written. This will return 0 +/// otherwise. This will return 0 if the flags are really not used by this +/// instruction. For some shifts/rotates, XED puts a flags operand in the +/// operand array before it knows if the flags are used because of +/// mode-dependent masking effects on the immediate. +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_uses_rflags(const xed_decoded_inst_t* p); + +/// @ingroup DEC +XED_DLL_EXPORT xed_uint_t +xed_decoded_inst_number_of_memory_operands(const xed_decoded_inst_t* p); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_mem_read(const xed_decoded_inst_t* p, unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_mem_written(const xed_decoded_inst_t* p, unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_mem_written_only(const xed_decoded_inst_t* p, + unsigned int mem_idx); +/// @ingroup DEC +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_conditionally_writes_registers(const xed_decoded_inst_t* p); +/// returns bytes +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_get_memory_operand_length(const xed_decoded_inst_t* p, + unsigned int memop_idx); + +/// Returns the addressing width in bits (16,32,64) for MEM0 (memop_idx==0) +/// or MEM1 (memop_idx==1). This factors in things like whether or not the +/// reference is an implicit stack push/pop reference, the machine mode and +// 67 prefixes if present. +/// @ingroup DEC +XED_DLL_EXPORT unsigned int +xed_decoded_inst_get_memop_address_width(const xed_decoded_inst_t* p, + xed_uint_t memop_idx); + + + +/// @ingroup DEC +/// Returns true if the instruction is a prefetch +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_is_prefetch(const xed_decoded_inst_t* p); + +/// @ingroup DEC +/// Return 1 for broadcast instructions or AVX512 load-op instructions using the broadcast feature +/// 0 otherwise. Logical OR of +/// #xed_decoded_inst_is_broadcast_instruction() and +/// #xed_decoded_inst_uses_embedded_broadcast(). +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_is_broadcast(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return 1 for broadcast instruction. (NOT including AVX512 load-op instructions) +/// 0 otherwise. Just a category check. +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_is_broadcast_instruction(const xed_decoded_inst_t* p); +/// @ingroup DEC +/// Return 1 for AVX512 load-op instructions using the broadcast feature, +/// 0 otherwise. +XED_DLL_EXPORT xed_bool_t +xed_decoded_inst_uses_embedded_broadcast(const xed_decoded_inst_t* p); + +//@} + + +/// @name xed_decoded_inst_t Modification +//@{ +// Modifying decoded instructions before re-encoding +/// @ingroup DEC +XED_DLL_EXPORT void +xed_decoded_inst_set_scale(xed_decoded_inst_t* p, xed_uint_t scale); +/// @ingroup DEC +/// Set the memory displacement using a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_memory_displacement(xed_decoded_inst_t* p, + xed_int64_t disp, + xed_uint_t length_bytes); +/// @ingroup DEC +/// Set the branch displacement using a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_branch_displacement(xed_decoded_inst_t* p, + xed_int32_t disp, + xed_uint_t length_bytes); +/// @ingroup DEC +/// Set the signed immediate a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_signed(xed_decoded_inst_t* p, + xed_int32_t x, + xed_uint_t length_bytes); +/// @ingroup DEC +/// Set the unsigned immediate a BYTE length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_unsigned(xed_decoded_inst_t* p, + xed_uint64_t x, + xed_uint_t length_bytes); + + +/// @ingroup DEC +/// Set the memory displacement a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_memory_displacement_bits(xed_decoded_inst_t* p, + xed_int64_t disp, + xed_uint_t length_bits); +/// @ingroup DEC +/// Set the branch displacement a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_branch_displacement_bits(xed_decoded_inst_t* p, + xed_int32_t disp, + xed_uint_t length_bits); +/// @ingroup DEC +/// Set the signed immediate a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_signed_bits(xed_decoded_inst_t* p, + xed_int32_t x, + xed_uint_t length_bits); +/// @ingroup DEC +/// Set the unsigned immediate a BITS length +XED_DLL_EXPORT void +xed_decoded_inst_set_immediate_unsigned_bits(xed_decoded_inst_t* p, + xed_uint64_t x, + xed_uint_t length_bits); + +//@} + +/// @name xed_decoded_inst_t User Data Field +//@{ +/// @ingroup DEC +/// Return a user data field for arbitrary use by the user after decoding. +static XED_INLINE xed_uint64_t +xed_decoded_inst_get_user_data(xed_decoded_inst_t* p) { + return p->u.user_data; +} +/// @ingroup DEC +/// Modify the user data field. +static XED_INLINE void +xed_decoded_inst_set_user_data(xed_decoded_inst_t* p, + xed_uint64_t new_value) { + p->u.user_data = new_value; +} +//@} + +/// @name xed_decoded_inst_t Classifiers +//@{ +/// @ingroup DEC +/// True for AVX512 (EVEX-encoded) SIMD and (VEX encoded) K-mask instructions +XED_DLL_EXPORT xed_bool_t +xed_classify_avx512(const xed_decoded_inst_t* d); +/// @ingroup DEC +/// True for AVX512 (VEX-encoded) K-mask operations +XED_DLL_EXPORT xed_bool_t +xed_classify_avx512_maskop(const xed_decoded_inst_t* d); +/// @ingroup DEC +/// True for AVX/AVX2 SIMD VEX-encoded operations. Does not include BMI/BMI2 instructions. +XED_DLL_EXPORT xed_bool_t +xed_classify_avx(const xed_decoded_inst_t* d); +/// @ingroup DEC +/// True for SSE/SSE2/etc. SIMD operations. Includes AES and PCLMULQDQ +XED_DLL_EXPORT xed_bool_t +xed_classify_sse(const xed_decoded_inst_t* d); + +//@} +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-decoded-inst.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-decoded-inst.h new file mode 100644 index 0000000..fb84340 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-decoded-inst.h @@ -0,0 +1,98 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-decoded-inst.h +/// + +#if !defined(XED_DECODER_STATE_H) +# define XED_DECODER_STATE_H +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-types.h" +#include "xed-inst.h" +#include "xed-flags.h" +#if defined(XED_ENCODER) +# include "xed-encoder-gen-defs.h" //generated +#endif +#include "xed-chip-enum.h" //generated +#include "xed-operand-element-type-enum.h" // a generated file +#include "xed-operand-storage.h" // a generated file + +typedef union { + xed_uint32_t i; + struct { + xed_uint8_t has_modrm; + xed_uint8_t has_disp; + xed_uint8_t has_imm; + } s; +} xed_ild_vars_t; + +struct xed_encoder_vars_s; +struct xed_decoder_vars_s; +/// @ingroup DEC +/// The main container for instructions. After decode, it holds an array of +/// operands with derived information from decode and also valid +/// #xed_inst_t pointer which describes the operand templates and the +/// operand order. See @ref DEC for API documentation. +typedef struct xed_decoded_inst_s { + /// The _operands are storage for information discovered during + /// decoding. They are also used by encode. The accessors for these + /// operands all have the form xed3_operand_{get,set}_*(). They should + /// be considered internal and subject to change over time. It is + /// preferred that you use xed_decoded_inst_*() or the + /// xed_operand_values_*() functions when available. + xed_operand_storage_t _operands; + +#if defined(XED_ENCODER) + /// Used for encode operand ordering. Not set by decode. + xed_uint8_t _operand_order[XED_ENCODE_ORDER_MAX_OPERANDS]; + /// Length of the _operand_order[] array. + xed_uint8_t _n_operand_order; +#endif + xed_uint8_t _decoded_length; + + /// when we decode an instruction, we set the _inst and get the + /// properites of that instruction here. This also points to the + /// operands template array. + const xed_inst_t* _inst; + + // decoder does not change it, encoder does + union { + xed_uint8_t* _enc; + const xed_uint8_t* _dec; + } _byte_array; + + // The ev field is stack allocated by xed_encode(). It is per-encode + // transitory data. + union { + /* user_data is available as a user data storage field after + * decoding. It does not live across re-encodes or re-decodes. */ + xed_uint64_t user_data; + xed_ild_vars_t ild_data; +#if defined(XED_ENCODER) + struct xed_encoder_vars_s* ev; +#endif + } u; + +} xed_decoded_inst_t; + +typedef xed_decoded_inst_t xed_operand_values_t; + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-disas.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-disas.h new file mode 100644 index 0000000..c43b9bd --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-disas.h @@ -0,0 +1,52 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-disas.h +/// + +#if !defined(XED_DISAS_H) +# define XED_DISAS_H + +#include "xed-types.h" + +/// @ingroup PRINT +/// A #xed_disassembly_callback_fn_t takes an address, a pointer to a +/// symbol buffer of buffer_length bytes, and a pointer to an offset. The +/// function fills in the symbol_buffer and sets the offset to the desired +/// offset for that symbol. If the function succeeds, it returns 1. +// The call back should return 0 if the buffer is not long enough to +// include the null termination.If no symbolic information is +// located, the function returns zero. +/// @param address The input address for which we want symbolic name and offset +/// @param symbol_buffer A buffer to hold the symbol name. The callback function should fill this in and terminate +/// with a null byte. +/// @param buffer_length The maximum length of the symbol_buffer including then null +/// @param offset A pointer to a xed_uint64_t to hold the offset from the provided symbol. +/// @param context This void* pointer passed to the disassembler's new interface so that the caller can identify +/// the proper context against which to resolve the symbols. +/// The disassembler passes this value to +/// the callback. The legacy formatters +/// that do not have context will pass zero for this parameter. +/// @return 0 on failure, 1 on success. +typedef int (*xed_disassembly_callback_fn_t)( + xed_uint64_t address, + char* symbol_buffer, + xed_uint32_t buffer_length, + xed_uint64_t* offset, + void* context); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode-check.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode-check.h new file mode 100644 index 0000000..6220651 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode-check.h @@ -0,0 +1,31 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#ifndef XED_ENCODE_CHECK_H +# define XED_ENCODE_CHECK_H +#include "xed-common-hdrs.h" +#include "xed-types.h" + + +/// turn off (or on) argument checking if using the checked encoder interface. +/// values 1, 0 +/// @ingroup ENC2 +XED_DLL_EXPORT void xed_enc2_set_check_args(xed_bool_t on); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode-direct.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode-direct.h new file mode 100644 index 0000000..c823e4b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode-direct.h @@ -0,0 +1,115 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + + +#ifndef XED_ENCODE_DIRECT_H +# define XED_ENCODE_DIRECT_H +#include "xed-common-hdrs.h" +#include "xed-portability.h" +#include "xed-types.h" +#include "xed-error-enum.h" +#include +#include + +/// This structure is filled in by the various XED ENC2 functions. It +/// should not be directly manipulated by user code. +/// @ingroup ENC2 +typedef struct { + xed_uint8_t* itext; // supplied by user during init + xed_uint32_t cursor; // where we write next byte + + xed_uint32_t has_sib:1; + xed_uint32_t has_disp8:1; + xed_uint32_t has_disp16:1; + xed_uint32_t has_disp32:1; + + xed_uint32_t rexw:1; // and vex, evex + xed_uint32_t rexr:1; // and vex, evex + xed_uint32_t rexx:1; // and vex, evex + xed_uint32_t rexb:1; // and vex, evex + + xed_uint32_t need_rex:1; // for SIL,DIL,BPL,SPL + xed_uint32_t evexrr:1; + xed_uint32_t vexl:1; + xed_uint32_t evexb:1; // also sae enabler for reg-only & vl=512 + + xed_uint32_t evexvv:1; + xed_uint32_t evexz:1; + xed_uint32_t evexll:2; // also rc bits in some case + + xed_uint32_t mod:2; + xed_uint32_t reg:3; + xed_uint32_t rm:3; + xed_uint32_t sibscale:2; + xed_uint32_t sibindex:3; + xed_uint32_t sibbase:3; + xed_uint32_t evexaaa:3; + xed_uint32_t map:3; + xed_uint32_t vexpp:3; // and evex + xed_uint32_t vvvv:4; + xed_uint32_t opcode_srm:3; /// for "partial opcode" instructions + + xed_uint8_t imm8_reg; // for _SE imm8-specified registers. + +} xed_enc2_req_payload_t; + + +/// A wrapper for #xed_enc2_req_payload_t . +/// @ingroup ENC2 +typedef union { + xed_enc2_req_payload_t s; +} xed_enc2_req_t; + +/// Zero out a #xed_enc2_req_t structure and set the output pointer. +/// Required before calling and any ENC2 encoding function. +/// @ingroup ENC2 +static XED_INLINE void xed_enc2_req_t_init(xed_enc2_req_t* r, xed_uint8_t* output_buffer) { + memset(r, 0, sizeof(xed_enc2_req_t)); + r->s.itext = output_buffer; +} + +/// Returns the number of bytes that were used for the encoding. +/// @ingroup ENC2 +static XED_INLINE xed_uint32_t xed_enc2_encoded_length(xed_enc2_req_t* r) { + return r->s.cursor; +} + + +/// Emit a legacy segment prefix byte in to the specified request's output buffer. +/// @ingroup ENC2 +XED_DLL_EXPORT void xed_emit_seg_prefix(xed_enc2_req_t* r, + xed_reg_enum_t reg); + + +typedef void (xed_user_abort_handler_t)(const char* format, va_list args); + +/// Set a function taking a variable-number-of-arguments (stdarg) to handle +/// the errors and die. The argument are like printf with a format string +/// followed by a varaible number of arguments. +/// @ingroup ENC2 +XED_DLL_EXPORT void xed_enc2_set_error_handler(xed_user_abort_handler_t* fn); + +/// The error handler routine. This function is called by encoder functions +/// upon detecting argument errors. It fist attempts to call the +/// user-registered handler (configured by #xed_enc2_set_error_handler() ), +/// or if no user handler is set, then this function calls printf() and +/// then abort(). If the user handler returns, abort() is still called. +/// @ingroup ENC2 +XED_DLL_EXPORT void xed_enc2_error(const char* fmt, ...); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode.h new file mode 100644 index 0000000..ce18b75 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encode.h @@ -0,0 +1,279 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encode.h + + +#ifndef XED_ENCODE_H +# define XED_ENCODE_H +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-error-enum.h" +#include "xed-operand-values-interface.h" +#include "xed-operand-width-enum.h" +#include "xed-encoder-iforms.h" //generated +#include "xed-encoder-gen-defs.h" //generated + +// we now (mostly) share the decode data structure +#include "xed-decoded-inst.h" + + +// establish a type equivalence for the xed_encoder_request_t and the +// corresponding xed_decoded_inst_t. + +/// @ingroup ENC +typedef struct xed_decoded_inst_s xed_encoder_request_s; +/// @ingroup ENC +typedef xed_decoded_inst_t xed_encoder_request_t; + + + +/// @ingroup ENC +XED_DLL_EXPORT xed_iclass_enum_t +xed_encoder_request_get_iclass( const xed_encoder_request_t* p); + +///////////////////////////////////////////////////////// +// set functions + +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_iclass( xed_encoder_request_t* p, + xed_iclass_enum_t iclass); + + +/// @name Primary Encode Functions +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_effective_operand_width( xed_encoder_request_t* p, + xed_uint_t width_bits); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_effective_address_size( xed_encoder_request_t* p, + xed_uint_t width_bits); +/*! @ingroup ENC + * + * Set the operands array element indexed by operand to the actual register + * name reg. + * + * @param[in] p xed_encoder_request_t + * @param[in] operand indicates which register operand storage field to use + * @param[in] reg the actual register represented (EAX, etc.) to store. + */ +XED_DLL_EXPORT void xed_encoder_request_set_reg(xed_encoder_request_t* p, + xed_operand_enum_t operand, + xed_reg_enum_t reg); +//@} + +/// @name Operand Order +//@{ +/*! @ingroup ENC + * Specify the name as the n'th operand in the operand order. + * + * The complication of this function is that the register operand names are + * specific to the position of the operand (REG0, REG1, REG2...). One can + * use this function for registers or one can use the + * xed_encoder_request_set_operand_name_reg() which takes integers instead + * of operand names. + * + * @param[in] p #xed_encoder_request_t + * @param[in] operand_index xed_uint_t representing n'th operand position + * @param[in] name #xed_operand_enum_t operand name. + */ +XED_DLL_EXPORT void +xed_encoder_request_set_operand_order(xed_encoder_request_t* p, + xed_uint_t operand_index, + xed_operand_enum_t name); + +/*! @ingroup ENC + * Retrieve the name of the n'th operand in the operand order. + * + * @param[in] p #xed_encoder_request_t + * @param[in] operand_index xed_uint_t representing n'th operand position + * @return The #xed_operand_enum_t operand name. + */ +XED_DLL_EXPORT xed_operand_enum_t +xed_encoder_request_get_operand_order(xed_encoder_request_t* p, + xed_uint_t operand_index); + + +/// @ingroup ENC +/// Retrieve the number of entries in the encoder operand order array +/// @return The number of entries in the encoder operand order array +static XED_INLINE xed_uint_t +xed_encoder_request_operand_order_entries(xed_encoder_request_t* p) +{ + return p->_n_operand_order; +} + +//@} + + +/// @name branches and far pointers +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_relbr(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_branch_displacement(xed_encoder_request_t* p, + xed_int32_t brdisp, + xed_uint_t nbytes); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_ptr(xed_encoder_request_t* p); +//@} + + +/// @name Immediates +//@{ +/// @ingroup ENC +/// Set the uimm0 using a BYTE width. +XED_DLL_EXPORT void xed_encoder_request_set_uimm0(xed_encoder_request_t* p, + xed_uint64_t uimm, + xed_uint_t nbytes); +/// @ingroup ENC +/// Set the uimm0 using a BIT width. +XED_DLL_EXPORT void xed_encoder_request_set_uimm0_bits(xed_encoder_request_t* p, + xed_uint64_t uimm, + xed_uint_t nbits); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_uimm1(xed_encoder_request_t* p, + xed_uint8_t uimm); +/// @ingroup ENC +/// same storage as uimm0 +XED_DLL_EXPORT void xed_encoder_request_set_simm(xed_encoder_request_t* p, + xed_int32_t simm, + xed_uint_t nbytes); + +/// @name Memory +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_memory_displacement(xed_encoder_request_t* p, + xed_int64_t memdisp, + xed_uint_t nbytes); + +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_agen(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_mem0(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_mem1(xed_encoder_request_t* p); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_memory_operand_length(xed_encoder_request_t* p, + xed_uint_t nbytes); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_seg0(xed_encoder_request_t* p, + xed_reg_enum_t seg_reg); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_seg1(xed_encoder_request_t* p, + xed_reg_enum_t seg_reg); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_base0(xed_encoder_request_t* p, + xed_reg_enum_t base_reg); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_base1(xed_encoder_request_t* p, + xed_reg_enum_t base_reg) ; +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_set_index(xed_encoder_request_t* p, + xed_reg_enum_t index_reg); +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_set_scale(xed_encoder_request_t* p, + xed_uint_t scale); +//@} + +////////////////////////////////////////////// +/// @ingroup ENC +static XED_INLINE const xed_operand_values_t* +xed_encoder_request_operands_const(const xed_encoder_request_t* p) { + return p; +} +/// @ingroup ENC +static XED_INLINE xed_operand_values_t* +xed_encoder_request_operands(xed_encoder_request_t* p) { + return p; +} + +/// @name Initialization +//@{ +/*! @ingroup ENC + * clear the operand order array + * @param[in] p xed_encoder_request_t + */ +XED_DLL_EXPORT void +xed_encoder_request_zero_operand_order(xed_encoder_request_t* p); + +/// @ingroup ENC +XED_DLL_EXPORT void +xed_encoder_request_zero_set_mode(xed_encoder_request_t* p, + const xed_state_t* dstate); +/// @ingroup ENC +XED_DLL_EXPORT void xed_encoder_request_zero(xed_encoder_request_t* p) ; +//@} + +struct xed_decoded_inst_s; //fwd decl +/// @ingroup ENC +/// Converts an decoder request to a valid encoder request. +XED_DLL_EXPORT void +xed_encoder_request_init_from_decode(struct xed_decoded_inst_s* d); + +/// @name String Printing +//@{ +/// @ingroup ENC +XED_DLL_EXPORT void xed_encode_request_print(const xed_encoder_request_t* p, + char* buf, xed_uint_t buflen); +//@} + + + + +/// @name Encoding +//@{ +/// This is the main interface to the encoder. The array should be +/// at most 15 bytes long. The ilen parameter should indicate +/// this length. If the array is too short, the encoder may fail to +/// encode the request. Failure is indicated by a return value of +/// type #xed_error_enum_t that is not equal to +/// #XED_ERROR_NONE. Otherwise, #XED_ERROR_NONE is returned and the +/// length of the encoded instruction is returned in olen. +/// +/// @param r encoder request description (#xed_encoder_request_t), includes mode info +/// @param array the encoded instruction bytes are stored here +/// @param ilen the input length of array. +/// @param olen the actual length of array used for encoding +/// @return success/failure as a #xed_error_enum_t +/// @ingroup ENC +XED_DLL_EXPORT xed_error_enum_t +xed_encode(xed_encoder_request_t* r, + xed_uint8_t* array, + const unsigned int ilen, + unsigned int* olen); + +/// This function will attempt to encode a NOP of exactly ilen +/// bytes. If such a NOP is not encodeable, then false will be returned. +/// +/// @param array the encoded instruction bytes are stored here +/// @param ilen the input length array. +/// @return success/failure as a #xed_error_enum_t +/// @ingroup ENC +XED_DLL_EXPORT xed_error_enum_t +xed_encode_nop(xed_uint8_t* array, + const unsigned int ilen); +//@} + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-gen-defs.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-gen-defs.h new file mode 100644 index 0000000..84b6190 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-gen-defs.h @@ -0,0 +1,32 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encoder-gen-defs.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENCODER_GEN_DEFS_H) +# define XED_ENCODER_GEN_DEFS_H +#define XED_ENCODE_ORDER_MAX_ENTRIES 32 +#define XED_ENCODE_ORDER_MAX_OPERANDS 5 +#define XED_ENCODE_MAX_FB_PATTERNS 121 +#define XED_ENCODE_MAX_EMIT_PATTERNS 199 +#define XED_ENCODE_FB_VALUES_TABLE_SIZE 3880 +#define XED_ENCODE_MAX_IFORMS 7639 +#define XED_ENC_GROUPS 535 +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-hl.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-hl.h new file mode 100644 index 0000000..6436968 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-hl.h @@ -0,0 +1,671 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#ifndef XED_ENCODER_HL_H +# define XED_ENCODER_HL_H +#include "xed-types.h" +#include "xed-reg-enum.h" +#include "xed-state.h" +#include "xed-iclass-enum.h" +#include "xed-portability.h" +#include "xed-encode.h" +#include "xed-util.h" + + +typedef struct { + xed_int64_t displacement; + xed_uint32_t displacement_bits; +} xed_enc_displacement_t; /* fixme bad name */ + +/// @name Memory Displacement +//@{ +/// @ingroup ENCHL +/// a memory displacement (not for branches) +/// @param displacement The value of the displacement +/// @param displacement_bits The width of the displacement in bits. Typically 8 or 32. +/// @returns #xed_enc_displacement_t +static XED_INLINE +xed_enc_displacement_t xed_disp(xed_int64_t displacement, + xed_uint32_t displacement_bits ) { + xed_enc_displacement_t x; + x.displacement = displacement; + x.displacement_bits = displacement_bits; + return x; +} +//@} + +typedef struct { + xed_reg_enum_t seg; + xed_reg_enum_t base; + xed_reg_enum_t index; + xed_uint32_t scale; + xed_enc_displacement_t disp; +} xed_memop_t; + + +typedef enum { + XED_ENCODER_OPERAND_TYPE_INVALID, + XED_ENCODER_OPERAND_TYPE_BRDISP, + XED_ENCODER_OPERAND_TYPE_REG, + XED_ENCODER_OPERAND_TYPE_IMM0, + XED_ENCODER_OPERAND_TYPE_SIMM0, + XED_ENCODER_OPERAND_TYPE_IMM1, + XED_ENCODER_OPERAND_TYPE_MEM, + XED_ENCODER_OPERAND_TYPE_PTR, + + /* special for things with suppressed implicit memops */ + XED_ENCODER_OPERAND_TYPE_SEG0, + + /* special for things with suppressed implicit memops */ + XED_ENCODER_OPERAND_TYPE_SEG1, + + /* specific operand storage fields -- must supply a name */ + XED_ENCODER_OPERAND_TYPE_OTHER +} xed_encoder_operand_type_t; + +typedef struct { + xed_encoder_operand_type_t type; + union { + xed_reg_enum_t reg; + xed_int32_t brdisp; + xed_uint64_t imm0; + xed_uint8_t imm1; + struct { + xed_operand_enum_t operand_name; + xed_uint32_t value; + } s; + xed_memop_t mem; + } u; + xed_uint32_t width_bits; +} xed_encoder_operand_t; + +/// @name Branch Displacement +//@{ +/// @ingroup ENCHL +/// a relative branch displacement operand +/// @param brdisp The branch displacement +/// @param width_bits The width of the displacement in bits. Typically 8 or 32. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_relbr(xed_int32_t brdisp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_BRDISP; + o.u.brdisp = brdisp; + o.width_bits = width_bits; + return o; +} +//@} + +/// @name Pointer Displacement +//@{ +/// @ingroup ENCHL +/// a relative displacement for a PTR operand -- the subsequent imm0 holds +///the 16b selector +/// @param brdisp The displacement for a far pointer operand +/// @param width_bits The width of the far pointr displacement in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_ptr(xed_int32_t brdisp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_PTR; + o.u.brdisp = brdisp; + o.width_bits = width_bits; + return o; +} +//@} + +/// @name Register and Immediate Operands +//@{ +/// @ingroup ENCHL +/// a register operand +/// @param reg A #xed_reg_enum_t register operand +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_reg(xed_reg_enum_t reg) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_REG; + o.u.reg = reg; + o.width_bits = 0; + return o; +} + +/// @ingroup ENCHL +/// a first immediate operand (known as IMM0) +/// @param v An immdediate operand. +/// @param width_bits The immediate width in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_imm0(xed_uint64_t v, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_IMM0; + o.u.imm0 = v; + o.width_bits = width_bits; + return o; +} +/// @ingroup ENCHL +/// an 32b signed immediate operand +/// @param v An signed immdediate operand. +/// @param width_bits The immediate width in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_simm0(xed_int32_t v, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_SIMM0; + /* sign conversion: we store the int32 in an uint64. It gets sign + extended. Later we convert it to the right width_bits for the + instruction. The maximum width_bits of a signed immediate is currently + 32b. */ + o.u.imm0 = XED_STATIC_CAST(xed_uint64_t,xed_sign_extend32_64(v)); + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// The 2nd immediate operand (known as IMM1) for rare instructions that require it. +/// @param v The 2nd immdediate (byte-width) operand +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_imm1(xed_uint8_t v) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_IMM1; + o.u.imm1 = v; + o.width_bits = 8; + return o; +} + + +/// @ingroup ENCHL +/// an operand storage field name and value +static XED_INLINE xed_encoder_operand_t xed_other( + xed_operand_enum_t operand_name, + xed_int32_t value) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_OTHER; + o.u.s.operand_name = operand_name; + o.u.s.value = XED_STATIC_CAST(xed_uint32_t,value); + o.width_bits = 0; + return o; +} +//@} + + +//@} + +/// @name Memory and Segment-releated Operands +//@{ + +/// @ingroup ENCHL +/// seg reg override for implicit suppressed memory ops +static XED_INLINE xed_encoder_operand_t xed_seg0(xed_reg_enum_t seg0) { + xed_encoder_operand_t o; + o.width_bits = 0; + o.type = XED_ENCODER_OPERAND_TYPE_SEG0; + o.u.reg = seg0; + return o; +} + +/// @ingroup ENCHL +/// seg reg override for implicit suppressed memory ops +static XED_INLINE xed_encoder_operand_t xed_seg1(xed_reg_enum_t seg1) { + xed_encoder_operand_t o; + o.width_bits = 0; + o.type = XED_ENCODER_OPERAND_TYPE_SEG1; + o.u.reg = seg1; + return o; +} + +/// @ingroup ENCHL +/// memory operand - base only +/// @param base The base register +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_b(xed_reg_enum_t base, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = XED_REG_INVALID; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp.displacement = 0; + o.u.mem.disp.displacement_bits = 0; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - base and displacement only +/// @param base The base register +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_bd(xed_reg_enum_t base, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = XED_REG_INVALID; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp =disp; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - base, index, scale, displacement +/// @param base The base register +/// @param index The index register +/// @param scale The scale for the index register value +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_bisd(xed_reg_enum_t base, + xed_reg_enum_t index, + xed_uint_t scale, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = XED_REG_INVALID; + o.u.mem.index= index; + o.u.mem.scale = scale; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} + + +/// @ingroup ENCHL +/// memory operand - segment and base only +/// @param seg The segment override register +/// @param base The base register +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gb(xed_reg_enum_t seg, + xed_reg_enum_t base, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = seg; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp.displacement = 0; + o.u.mem.disp.displacement_bits = 0; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - segment, base and displacement only +/// @param seg The segment override register +/// @param base The base register +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gbd(xed_reg_enum_t seg, + xed_reg_enum_t base, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = seg; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - segment and displacement only +/// @param seg The segment override register +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gd(xed_reg_enum_t seg, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = XED_REG_INVALID; + o.u.mem.seg = seg; + o.u.mem.index= XED_REG_INVALID; + o.u.mem.scale = 0; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} + +/// @ingroup ENCHL +/// memory operand - segment, base, index, scale, and displacement +/// @param seg The segment override register +/// @param base The base register +/// @param index The index register +/// @param scale The scale for the index register value +/// @param disp The displacement +/// @param width_bits The length of the memory reference in bits. +/// @returns xed_encoder_operand_t An operand. +static XED_INLINE xed_encoder_operand_t xed_mem_gbisd(xed_reg_enum_t seg, + xed_reg_enum_t base, + xed_reg_enum_t index, + xed_uint_t scale, + xed_enc_displacement_t disp, + xed_uint_t width_bits) { + xed_encoder_operand_t o; + o.type = XED_ENCODER_OPERAND_TYPE_MEM; + o.u.mem.base = base; + o.u.mem.seg = seg; + o.u.mem.index= index; + o.u.mem.scale = scale; + o.u.mem.disp = disp; + o.width_bits = width_bits; + return o; +} +//@} + +typedef union { + struct { + xed_uint32_t rep :1; + xed_uint32_t repne :1; + xed_uint32_t br_hint_taken :1; + xed_uint32_t br_hint_not_taken :1; + } s; + xed_uint32_t i; +} xed_encoder_prefixes_t; + +#define XED_ENCODER_OPERANDS_MAX 8 /* FIXME */ +typedef struct { + xed_state_t mode; + xed_iclass_enum_t iclass; /*FIXME: use iform instead? or allow either */ + xed_uint32_t effective_operand_width; + + /* the effective_address_width is only requires to be set for + * instructions * with implicit suppressed memops or memops with no + * base or index regs. When base or index regs are present, XED pick + * this up automatically from the register names. + + * FIXME: make effective_address_width required by all encodes for + * unifority. Add to xed_inst[0123]() APIs??? */ + xed_uint32_t effective_address_width; + + xed_encoder_prefixes_t prefixes; + xed_uint32_t noperands; + xed_encoder_operand_t operands[XED_ENCODER_OPERANDS_MAX]; +} xed_encoder_instruction_t; + +/// @name Instruction Properties and prefixes +//@{ +/// @ingroup ENCHL +/// This is to specify effective address size different than the +/// default. For things with base or index regs, XED picks it up from the +/// registers. But for things that have implicit memops, or no base or index +/// reg, we must allow the user to set the address width directly. +/// @param x The #xed_encoder_instruction_t being filled in. +/// @param width_bits The intended effective address size in bits. Values: 16, 32 or 64. +static XED_INLINE void xed_addr(xed_encoder_instruction_t* x, + xed_uint_t width_bits) { + x->effective_address_width = width_bits; +} + + +/// @ingroup ENCHL +/// To add a REP (0xF3) prefix. +/// @param x The #xed_encoder_instruction_t being filled in. +static XED_INLINE void xed_rep(xed_encoder_instruction_t* x) { + x->prefixes.s.rep=1; +} + +/// @ingroup ENCHL +/// To add a REPNE (0xF2) prefix. +/// @param x The #xed_encoder_instruction_t being filled in. +static XED_INLINE void xed_repne(xed_encoder_instruction_t* x) { + x->prefixes.s.repne=1; +} + + + + +/// @ingroup ENCHL +/// convert a #xed_encoder_instruction_t to a #xed_encoder_request_t for +/// encoding +XED_DLL_EXPORT xed_bool_t +xed_convert_to_encoder_request(xed_encoder_request_t* out, + xed_encoder_instruction_t* in); + +//@} + +/// @name Creating instructions from operands +//@{ + +/// @ingroup ENCHL +/// instruction with no operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +static XED_INLINE void xed_inst0( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->noperands = 0; +} + +/// @ingroup ENCHL +/// instruction with one operand +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the operand +static XED_INLINE void xed_inst1( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->noperands = 1; +} + +/// @ingroup ENCHL +/// instruction with two operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +static XED_INLINE void xed_inst2( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->noperands = 2; +} + +/// @ingroup ENCHL +/// instruction with three operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +/// @param op2 the 3rd operand +static XED_INLINE void xed_inst3( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1, + xed_encoder_operand_t op2) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->operands[2] = op2; + inst->noperands = 3; +} + + +/// @ingroup ENCHL +/// instruction with four operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +/// @param op2 the 3rd operand +/// @param op3 the 4th operand +static XED_INLINE void xed_inst4( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1, + xed_encoder_operand_t op2, + xed_encoder_operand_t op3) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->operands[2] = op2; + inst->operands[3] = op3; + inst->noperands = 4; +} + +/// @ingroup ENCHL +/// instruction with five operands +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param op0 the 1st operand +/// @param op1 the 2nd operand +/// @param op2 the 3rd operand +/// @param op3 the 4th operand +/// @param op4 the 5th operand +static XED_INLINE void xed_inst5( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_encoder_operand_t op0, + xed_encoder_operand_t op1, + xed_encoder_operand_t op2, + xed_encoder_operand_t op3, + xed_encoder_operand_t op4) { + + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + inst->operands[0] = op0; + inst->operands[1] = op1; + inst->operands[2] = op2; + inst->operands[3] = op3; + inst->operands[4] = op4; + inst->noperands = 5; +} + + +/// @ingroup ENCHL +/// instruction with an array of operands. The maximum number is +/// XED_ENCODER_OPERANDS_MAX. The array's contents are copied. +/// @param inst The #xed_encoder_instruction_t to be filled in +/// @param mode The xed_state_t including the machine mode and stack address width. +/// @param iclass The #xed_iclass_enum_t +/// @param effective_operand_width in bits +/// @param number_of_operands length of the subsequent array +/// @param operand_array An array of #xed_encoder_operand_t objects +static XED_INLINE void xed_inst( + xed_encoder_instruction_t* inst, + xed_state_t mode, + xed_iclass_enum_t iclass, + xed_uint_t effective_operand_width, + xed_uint_t number_of_operands, + const xed_encoder_operand_t* operand_array) { + + xed_uint_t i; + inst->mode=mode; + inst->iclass = iclass; + inst->effective_operand_width = effective_operand_width; + inst->effective_address_width = 0; + inst->prefixes.i = 0; + xed_assert(number_of_operands < XED_ENCODER_OPERANDS_MAX); + for(i=0;ioperands[i] = operand_array[i]; + } + inst->noperands = number_of_operands; +} + +//@} + +/* + xed_encoder_instruction_t x,y; + + xed_inst2(&x, state, XED_ICLASS_ADD, 32, + xed_reg(XED_REG_EAX), + xed_mem_bd(XED_REG_EDX, xed_disp(0x11223344, 32), 32)); + + xed_inst2(&y, state, XED_ICLASS_ADD, 32, + xed_reg(XED_REG_EAX), + xed_mem_gbisd(XED_REG_FS, XED_REG_EAX, XED_REG_ESI,4, + xed_disp(0x11223344, 32), 32)); + + */ + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-iforms.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-iforms.h new file mode 100644 index 0000000..7ec5253 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-encoder-iforms.h @@ -0,0 +1,77 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-encoder-iforms.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENCODER_IFORMS_H) +# define XED_ENCODER_IFORMS_H +#include "xed-types.h" +typedef struct xed_encoder_iforms_s { + xed_uint32_t x_SIBBASE_ENCODE; + xed_uint32_t x_SIBBASE_ENCODE_SIB1; + xed_uint32_t x_SIBINDEX_ENCODE; + xed_uint32_t x_MODRM_MOD_ENCODE; + xed_uint32_t x_MODRM_RM_ENCODE; + xed_uint32_t x_MODRM_RM_ENCODE_EA16_SIB0; + xed_uint32_t x_MODRM_RM_ENCODE_EA64_SIB0; + xed_uint32_t x_MODRM_RM_ENCODE_EA32_SIB0; + xed_uint32_t x_SIB_NT; + xed_uint32_t x_DISP_NT; + xed_uint32_t x_REMOVE_SEGMENT; + xed_uint32_t x_REX_PREFIX_ENC; + xed_uint32_t x_PREFIX_ENC; + xed_uint32_t x_VEXED_REX; + xed_uint32_t x_XOP_TYPE_ENC; + xed_uint32_t x_XOP_MAP_ENC; + xed_uint32_t x_XOP_REXXB_ENC; + xed_uint32_t x_VEX_TYPE_ENC; + xed_uint32_t x_VEX_REXR_ENC; + xed_uint32_t x_VEX_REXXB_ENC; + xed_uint32_t x_VEX_MAP_ENC; + xed_uint32_t x_VEX_REG_ENC; + xed_uint32_t x_VEX_ESCVL_ENC; + xed_uint32_t x_SE_IMM8; + xed_uint32_t x_VSIB_ENC_BASE; + xed_uint32_t x_VSIB_ENC; + xed_uint32_t x_EVEX_62_REXR_ENC; + xed_uint32_t x_EVEX_REXX_ENC; + xed_uint32_t x_EVEX_REXB_ENC; + xed_uint32_t x_EVEX_REXRR_ENC; + xed_uint32_t x_EVEX_MAP_ENC; + xed_uint32_t x_EVEX_REXW_VVVV_ENC; + xed_uint32_t x_EVEX_UPP_ENC; + xed_uint32_t x_AVX512_EVEX_BYTE3_ENC; + xed_uint32_t x_UIMMv; + xed_uint32_t x_SIMMz; + xed_uint32_t x_SIMM8; + xed_uint32_t x_UIMM8; + xed_uint32_t x_UIMM8_1; + xed_uint32_t x_UIMM16; + xed_uint32_t x_UIMM32; + xed_uint32_t x_BRDISP8; + xed_uint32_t x_BRDISP32; + xed_uint32_t x_BRDISPz; + xed_uint32_t x_MEMDISPv; + xed_uint32_t x_MEMDISP32; + xed_uint32_t x_MEMDISP16; + xed_uint32_t x_MEMDISP8; + xed_uint32_t x_MEMDISP; +} xed_encoder_iforms_t; +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-error-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-error-enum.h new file mode 100644 index 0000000..889790e --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-error-enum.h @@ -0,0 +1,90 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-error-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ERROR_ENUM_H) +# define XED_ERROR_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ERROR_NONE_DEFINED 1 +#define XED_ERROR_BUFFER_TOO_SHORT_DEFINED 1 +#define XED_ERROR_GENERAL_ERROR_DEFINED 1 +#define XED_ERROR_INVALID_FOR_CHIP_DEFINED 1 +#define XED_ERROR_BAD_REGISTER_DEFINED 1 +#define XED_ERROR_BAD_LOCK_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_REP_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_LEGACY_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_REX_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_EVEX_UBIT_DEFINED 1 +#define XED_ERROR_BAD_MAP_DEFINED 1 +#define XED_ERROR_BAD_EVEX_V_PRIME_DEFINED 1 +#define XED_ERROR_BAD_EVEX_Z_NO_MASKING_DEFINED 1 +#define XED_ERROR_NO_OUTPUT_POINTER_DEFINED 1 +#define XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED_DEFINED 1 +#define XED_ERROR_BAD_MEMOP_INDEX_DEFINED 1 +#define XED_ERROR_CALLBACK_PROBLEM_DEFINED 1 +#define XED_ERROR_GATHER_REGS_DEFINED 1 +#define XED_ERROR_INSTR_TOO_LONG_DEFINED 1 +#define XED_ERROR_INVALID_MODE_DEFINED 1 +#define XED_ERROR_BAD_EVEX_LL_DEFINED 1 +#define XED_ERROR_BAD_REG_MATCH_DEFINED 1 +#define XED_ERROR_LAST_DEFINED 1 +typedef enum { + XED_ERROR_NONE, ///< There was no error + XED_ERROR_BUFFER_TOO_SHORT, ///< There were not enough bytes in the given buffer + XED_ERROR_GENERAL_ERROR, ///< XED could not decode the given instruction + XED_ERROR_INVALID_FOR_CHIP, ///< The instruciton is not valid for the specified chip + XED_ERROR_BAD_REGISTER, ///< XED could not decode the given instruction because an invalid register encoding was used. + XED_ERROR_BAD_LOCK_PREFIX, ///< A lock prefix was found where none is allowed. + XED_ERROR_BAD_REP_PREFIX, ///< An F2 or F3 prefix was found where none is allowed. + XED_ERROR_BAD_LEGACY_PREFIX, ///< A 66, F2 or F3 prefix was found where none is allowed. + XED_ERROR_BAD_REX_PREFIX, ///< A REX prefix was found where none is allowed. + XED_ERROR_BAD_EVEX_UBIT, ///< An illegal value for the EVEX.U bit was present in the instruction. + XED_ERROR_BAD_MAP, ///< An illegal value for the MAP field was detected in the instruction. + XED_ERROR_BAD_EVEX_V_PRIME, ///< EVEX.V'=0 was detected in a non-64b mode instruction. + XED_ERROR_BAD_EVEX_Z_NO_MASKING, ///< EVEX.Z!=0 when EVEX.aaa==0 + XED_ERROR_NO_OUTPUT_POINTER, ///< The output pointer for xed_agen was zero + XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED, ///< One or both of the callbacks for xed_agen were missing. + XED_ERROR_BAD_MEMOP_INDEX, ///< Memop indices must be 0 or 1. + XED_ERROR_CALLBACK_PROBLEM, ///< The register or segment callback for xed_agen experienced a problem + XED_ERROR_GATHER_REGS, ///< The index, dest and mask regs for AVX2 gathers must be different. + XED_ERROR_INSTR_TOO_LONG, ///< Full decode of instruction would exeed 15B. + XED_ERROR_INVALID_MODE, ///< The instruction was not valid for the specified mode + XED_ERROR_BAD_EVEX_LL, ///< EVEX.LL must not ==3 unless using embedded rounding + XED_ERROR_BAD_REG_MATCH, ///< Source registers must not match the destination register for this instruction. + XED_ERROR_LAST +} xed_error_enum_t; + +/// This converts strings to #xed_error_enum_t types. +/// @param s A C-string. +/// @return #xed_error_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_error_enum_t str2xed_error_enum_t(const char* s); +/// This converts strings to #xed_error_enum_t types. +/// @param p An enumeration element of type xed_error_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_error_enum_t2str(const xed_error_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_error_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_error_enum_t xed_error_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-exception-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-exception-enum.h new file mode 100644 index 0000000..7aa5e89 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-exception-enum.h @@ -0,0 +1,156 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-exception-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_EXCEPTION_ENUM_H) +# define XED_EXCEPTION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_EXCEPTION_INVALID_DEFINED 1 +#define XED_EXCEPTION_AMX_E1_DEFINED 1 +#define XED_EXCEPTION_AMX_E2_DEFINED 1 +#define XED_EXCEPTION_AMX_E3_DEFINED 1 +#define XED_EXCEPTION_AMX_E4_DEFINED 1 +#define XED_EXCEPTION_AMX_E5_DEFINED 1 +#define XED_EXCEPTION_AMX_E6_DEFINED 1 +#define XED_EXCEPTION_AVX512_E1_DEFINED 1 +#define XED_EXCEPTION_AVX512_E10_DEFINED 1 +#define XED_EXCEPTION_AVX512_E10NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E11_DEFINED 1 +#define XED_EXCEPTION_AVX512_E12_DEFINED 1 +#define XED_EXCEPTION_AVX512_E12NP_DEFINED 1 +#define XED_EXCEPTION_AVX512_E1NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E2_DEFINED 1 +#define XED_EXCEPTION_AVX512_E3_DEFINED 1 +#define XED_EXCEPTION_AVX512_E3NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E4_DEFINED 1 +#define XED_EXCEPTION_AVX512_E4NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E5_DEFINED 1 +#define XED_EXCEPTION_AVX512_E5NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E6_DEFINED 1 +#define XED_EXCEPTION_AVX512_E6NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E7NM_DEFINED 1 +#define XED_EXCEPTION_AVX512_E7NM128_DEFINED 1 +#define XED_EXCEPTION_AVX512_E9NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_K20_DEFINED 1 +#define XED_EXCEPTION_AVX512_K21_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_1_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_11_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_12_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_2_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_2D_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_3_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_4_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_4M_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_5_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_5L_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_6_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_7_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_8_DEFINED 1 +#define XED_EXCEPTION_MMX_FP_DEFINED 1 +#define XED_EXCEPTION_MMX_FP_16ALIGN_DEFINED 1 +#define XED_EXCEPTION_MMX_MEM_DEFINED 1 +#define XED_EXCEPTION_MMX_NOFP_DEFINED 1 +#define XED_EXCEPTION_MMX_NOFP2_DEFINED 1 +#define XED_EXCEPTION_MMX_NOMEM_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_1_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_2_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_2D_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_3_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_4_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_4M_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_5_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_7_DEFINED 1 +#define XED_EXCEPTION_LAST_DEFINED 1 +typedef enum { + XED_EXCEPTION_INVALID, + XED_EXCEPTION_AMX_E1, + XED_EXCEPTION_AMX_E2, + XED_EXCEPTION_AMX_E3, + XED_EXCEPTION_AMX_E4, + XED_EXCEPTION_AMX_E5, + XED_EXCEPTION_AMX_E6, + XED_EXCEPTION_AVX512_E1, + XED_EXCEPTION_AVX512_E10, + XED_EXCEPTION_AVX512_E10NF, + XED_EXCEPTION_AVX512_E11, + XED_EXCEPTION_AVX512_E12, + XED_EXCEPTION_AVX512_E12NP, + XED_EXCEPTION_AVX512_E1NF, + XED_EXCEPTION_AVX512_E2, + XED_EXCEPTION_AVX512_E3, + XED_EXCEPTION_AVX512_E3NF, + XED_EXCEPTION_AVX512_E4, + XED_EXCEPTION_AVX512_E4NF, + XED_EXCEPTION_AVX512_E5, + XED_EXCEPTION_AVX512_E5NF, + XED_EXCEPTION_AVX512_E6, + XED_EXCEPTION_AVX512_E6NF, + XED_EXCEPTION_AVX512_E7NM, + XED_EXCEPTION_AVX512_E7NM128, + XED_EXCEPTION_AVX512_E9NF, + XED_EXCEPTION_AVX512_K20, + XED_EXCEPTION_AVX512_K21, + XED_EXCEPTION_AVX_TYPE_1, + XED_EXCEPTION_AVX_TYPE_11, + XED_EXCEPTION_AVX_TYPE_12, + XED_EXCEPTION_AVX_TYPE_2, + XED_EXCEPTION_AVX_TYPE_2D, + XED_EXCEPTION_AVX_TYPE_3, + XED_EXCEPTION_AVX_TYPE_4, + XED_EXCEPTION_AVX_TYPE_4M, + XED_EXCEPTION_AVX_TYPE_5, + XED_EXCEPTION_AVX_TYPE_5L, + XED_EXCEPTION_AVX_TYPE_6, + XED_EXCEPTION_AVX_TYPE_7, + XED_EXCEPTION_AVX_TYPE_8, + XED_EXCEPTION_MMX_FP, + XED_EXCEPTION_MMX_FP_16ALIGN, + XED_EXCEPTION_MMX_MEM, + XED_EXCEPTION_MMX_NOFP, + XED_EXCEPTION_MMX_NOFP2, + XED_EXCEPTION_MMX_NOMEM, + XED_EXCEPTION_SSE_TYPE_1, + XED_EXCEPTION_SSE_TYPE_2, + XED_EXCEPTION_SSE_TYPE_2D, + XED_EXCEPTION_SSE_TYPE_3, + XED_EXCEPTION_SSE_TYPE_4, + XED_EXCEPTION_SSE_TYPE_4M, + XED_EXCEPTION_SSE_TYPE_5, + XED_EXCEPTION_SSE_TYPE_7, + XED_EXCEPTION_LAST +} xed_exception_enum_t; + +/// This converts strings to #xed_exception_enum_t types. +/// @param s A C-string. +/// @return #xed_exception_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_exception_enum_t str2xed_exception_enum_t(const char* s); +/// This converts strings to #xed_exception_enum_t types. +/// @param p An enumeration element of type xed_exception_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_exception_enum_t2str(const xed_exception_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_exception_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_exception_enum_t xed_exception_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-extension-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-extension-enum.h new file mode 100644 index 0000000..ebff560 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-extension-enum.h @@ -0,0 +1,226 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-extension-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_EXTENSION_ENUM_H) +# define XED_EXTENSION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_EXTENSION_INVALID_DEFINED 1 +#define XED_EXTENSION_3DNOW_DEFINED 1 +#define XED_EXTENSION_3DNOW_PREFETCH_DEFINED 1 +#define XED_EXTENSION_ADOX_ADCX_DEFINED 1 +#define XED_EXTENSION_AES_DEFINED 1 +#define XED_EXTENSION_AMD_INVLPGB_DEFINED 1 +#define XED_EXTENSION_AMX_BF16_DEFINED 1 +#define XED_EXTENSION_AMX_INT8_DEFINED 1 +#define XED_EXTENSION_AMX_TILE_DEFINED 1 +#define XED_EXTENSION_AVX_DEFINED 1 +#define XED_EXTENSION_AVX2_DEFINED 1 +#define XED_EXTENSION_AVX2GATHER_DEFINED 1 +#define XED_EXTENSION_AVX512EVEX_DEFINED 1 +#define XED_EXTENSION_AVX512VEX_DEFINED 1 +#define XED_EXTENSION_AVXAES_DEFINED 1 +#define XED_EXTENSION_AVX_VNNI_DEFINED 1 +#define XED_EXTENSION_BASE_DEFINED 1 +#define XED_EXTENSION_BMI1_DEFINED 1 +#define XED_EXTENSION_BMI2_DEFINED 1 +#define XED_EXTENSION_CET_DEFINED 1 +#define XED_EXTENSION_CLDEMOTE_DEFINED 1 +#define XED_EXTENSION_CLFLUSHOPT_DEFINED 1 +#define XED_EXTENSION_CLFSH_DEFINED 1 +#define XED_EXTENSION_CLWB_DEFINED 1 +#define XED_EXTENSION_CLZERO_DEFINED 1 +#define XED_EXTENSION_ENQCMD_DEFINED 1 +#define XED_EXTENSION_F16C_DEFINED 1 +#define XED_EXTENSION_FMA_DEFINED 1 +#define XED_EXTENSION_FMA4_DEFINED 1 +#define XED_EXTENSION_GFNI_DEFINED 1 +#define XED_EXTENSION_HRESET_DEFINED 1 +#define XED_EXTENSION_INVPCID_DEFINED 1 +#define XED_EXTENSION_KEYLOCKER_DEFINED 1 +#define XED_EXTENSION_KEYLOCKER_WIDE_DEFINED 1 +#define XED_EXTENSION_LONGMODE_DEFINED 1 +#define XED_EXTENSION_LZCNT_DEFINED 1 +#define XED_EXTENSION_MCOMMIT_DEFINED 1 +#define XED_EXTENSION_MMX_DEFINED 1 +#define XED_EXTENSION_MONITOR_DEFINED 1 +#define XED_EXTENSION_MONITORX_DEFINED 1 +#define XED_EXTENSION_MOVBE_DEFINED 1 +#define XED_EXTENSION_MOVDIR_DEFINED 1 +#define XED_EXTENSION_MPX_DEFINED 1 +#define XED_EXTENSION_PAUSE_DEFINED 1 +#define XED_EXTENSION_PCLMULQDQ_DEFINED 1 +#define XED_EXTENSION_PCONFIG_DEFINED 1 +#define XED_EXTENSION_PKU_DEFINED 1 +#define XED_EXTENSION_PREFETCHWT1_DEFINED 1 +#define XED_EXTENSION_PTWRITE_DEFINED 1 +#define XED_EXTENSION_RDPID_DEFINED 1 +#define XED_EXTENSION_RDPRU_DEFINED 1 +#define XED_EXTENSION_RDRAND_DEFINED 1 +#define XED_EXTENSION_RDSEED_DEFINED 1 +#define XED_EXTENSION_RDTSCP_DEFINED 1 +#define XED_EXTENSION_RDWRFSGS_DEFINED 1 +#define XED_EXTENSION_RTM_DEFINED 1 +#define XED_EXTENSION_SERIALIZE_DEFINED 1 +#define XED_EXTENSION_SGX_DEFINED 1 +#define XED_EXTENSION_SGX_ENCLV_DEFINED 1 +#define XED_EXTENSION_SHA_DEFINED 1 +#define XED_EXTENSION_SMAP_DEFINED 1 +#define XED_EXTENSION_SMX_DEFINED 1 +#define XED_EXTENSION_SNP_DEFINED 1 +#define XED_EXTENSION_SSE_DEFINED 1 +#define XED_EXTENSION_SSE2_DEFINED 1 +#define XED_EXTENSION_SSE3_DEFINED 1 +#define XED_EXTENSION_SSE4_DEFINED 1 +#define XED_EXTENSION_SSE4A_DEFINED 1 +#define XED_EXTENSION_SSSE3_DEFINED 1 +#define XED_EXTENSION_SVM_DEFINED 1 +#define XED_EXTENSION_TBM_DEFINED 1 +#define XED_EXTENSION_TDX_DEFINED 1 +#define XED_EXTENSION_TSX_LDTRK_DEFINED 1 +#define XED_EXTENSION_UINTR_DEFINED 1 +#define XED_EXTENSION_VAES_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_AES_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_MONTMUL_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_RNG_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_SHA_DEFINED 1 +#define XED_EXTENSION_VMFUNC_DEFINED 1 +#define XED_EXTENSION_VPCLMULQDQ_DEFINED 1 +#define XED_EXTENSION_VTX_DEFINED 1 +#define XED_EXTENSION_WAITPKG_DEFINED 1 +#define XED_EXTENSION_WBNOINVD_DEFINED 1 +#define XED_EXTENSION_X87_DEFINED 1 +#define XED_EXTENSION_XOP_DEFINED 1 +#define XED_EXTENSION_XSAVE_DEFINED 1 +#define XED_EXTENSION_XSAVEC_DEFINED 1 +#define XED_EXTENSION_XSAVEOPT_DEFINED 1 +#define XED_EXTENSION_XSAVES_DEFINED 1 +#define XED_EXTENSION_LAST_DEFINED 1 +typedef enum { + XED_EXTENSION_INVALID, + XED_EXTENSION_3DNOW, + XED_EXTENSION_3DNOW_PREFETCH, + XED_EXTENSION_ADOX_ADCX, + XED_EXTENSION_AES, + XED_EXTENSION_AMD_INVLPGB, + XED_EXTENSION_AMX_BF16, + XED_EXTENSION_AMX_INT8, + XED_EXTENSION_AMX_TILE, + XED_EXTENSION_AVX, + XED_EXTENSION_AVX2, + XED_EXTENSION_AVX2GATHER, + XED_EXTENSION_AVX512EVEX, + XED_EXTENSION_AVX512VEX, + XED_EXTENSION_AVXAES, + XED_EXTENSION_AVX_VNNI, + XED_EXTENSION_BASE, + XED_EXTENSION_BMI1, + XED_EXTENSION_BMI2, + XED_EXTENSION_CET, + XED_EXTENSION_CLDEMOTE, + XED_EXTENSION_CLFLUSHOPT, + XED_EXTENSION_CLFSH, + XED_EXTENSION_CLWB, + XED_EXTENSION_CLZERO, + XED_EXTENSION_ENQCMD, + XED_EXTENSION_F16C, + XED_EXTENSION_FMA, + XED_EXTENSION_FMA4, + XED_EXTENSION_GFNI, + XED_EXTENSION_HRESET, + XED_EXTENSION_INVPCID, + XED_EXTENSION_KEYLOCKER, + XED_EXTENSION_KEYLOCKER_WIDE, + XED_EXTENSION_LONGMODE, + XED_EXTENSION_LZCNT, + XED_EXTENSION_MCOMMIT, + XED_EXTENSION_MMX, + XED_EXTENSION_MONITOR, + XED_EXTENSION_MONITORX, + XED_EXTENSION_MOVBE, + XED_EXTENSION_MOVDIR, + XED_EXTENSION_MPX, + XED_EXTENSION_PAUSE, + XED_EXTENSION_PCLMULQDQ, + XED_EXTENSION_PCONFIG, + XED_EXTENSION_PKU, + XED_EXTENSION_PREFETCHWT1, + XED_EXTENSION_PTWRITE, + XED_EXTENSION_RDPID, + XED_EXTENSION_RDPRU, + XED_EXTENSION_RDRAND, + XED_EXTENSION_RDSEED, + XED_EXTENSION_RDTSCP, + XED_EXTENSION_RDWRFSGS, + XED_EXTENSION_RTM, + XED_EXTENSION_SERIALIZE, + XED_EXTENSION_SGX, + XED_EXTENSION_SGX_ENCLV, + XED_EXTENSION_SHA, + XED_EXTENSION_SMAP, + XED_EXTENSION_SMX, + XED_EXTENSION_SNP, + XED_EXTENSION_SSE, + XED_EXTENSION_SSE2, + XED_EXTENSION_SSE3, + XED_EXTENSION_SSE4, + XED_EXTENSION_SSE4A, + XED_EXTENSION_SSSE3, + XED_EXTENSION_SVM, + XED_EXTENSION_TBM, + XED_EXTENSION_TDX, + XED_EXTENSION_TSX_LDTRK, + XED_EXTENSION_UINTR, + XED_EXTENSION_VAES, + XED_EXTENSION_VIA_PADLOCK_AES, + XED_EXTENSION_VIA_PADLOCK_MONTMUL, + XED_EXTENSION_VIA_PADLOCK_RNG, + XED_EXTENSION_VIA_PADLOCK_SHA, + XED_EXTENSION_VMFUNC, + XED_EXTENSION_VPCLMULQDQ, + XED_EXTENSION_VTX, + XED_EXTENSION_WAITPKG, + XED_EXTENSION_WBNOINVD, + XED_EXTENSION_X87, + XED_EXTENSION_XOP, + XED_EXTENSION_XSAVE, + XED_EXTENSION_XSAVEC, + XED_EXTENSION_XSAVEOPT, + XED_EXTENSION_XSAVES, + XED_EXTENSION_LAST +} xed_extension_enum_t; + +/// This converts strings to #xed_extension_enum_t types. +/// @param s A C-string. +/// @return #xed_extension_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_extension_enum_t str2xed_extension_enum_t(const char* s); +/// This converts strings to #xed_extension_enum_t types. +/// @param p An enumeration element of type xed_extension_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_extension_enum_t2str(const xed_extension_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_extension_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_extension_enum_t xed_extension_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-flag-action-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-flag-action-enum.h new file mode 100644 index 0000000..f7413bf --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-flag-action-enum.h @@ -0,0 +1,62 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-flag-action-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_FLAG_ACTION_ENUM_H) +# define XED_FLAG_ACTION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_FLAG_ACTION_INVALID_DEFINED 1 +#define XED_FLAG_ACTION_u_DEFINED 1 +#define XED_FLAG_ACTION_tst_DEFINED 1 +#define XED_FLAG_ACTION_mod_DEFINED 1 +#define XED_FLAG_ACTION_0_DEFINED 1 +#define XED_FLAG_ACTION_pop_DEFINED 1 +#define XED_FLAG_ACTION_ah_DEFINED 1 +#define XED_FLAG_ACTION_1_DEFINED 1 +#define XED_FLAG_ACTION_LAST_DEFINED 1 +typedef enum { + XED_FLAG_ACTION_INVALID, + XED_FLAG_ACTION_u, ///< undefined (treated as a write) + XED_FLAG_ACTION_tst, ///< test (read) + XED_FLAG_ACTION_mod, ///< modification (write) + XED_FLAG_ACTION_0, ///< value will be zero (write) + XED_FLAG_ACTION_pop, ///< value comes from the stack (write) + XED_FLAG_ACTION_ah, ///< value comes from AH (write) + XED_FLAG_ACTION_1, ///< value will be 1 (write) + XED_FLAG_ACTION_LAST +} xed_flag_action_enum_t; + +/// This converts strings to #xed_flag_action_enum_t types. +/// @param s A C-string. +/// @return #xed_flag_action_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_action_enum_t str2xed_flag_action_enum_t(const char* s); +/// This converts strings to #xed_flag_action_enum_t types. +/// @param p An enumeration element of type xed_flag_action_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_flag_action_enum_t2str(const xed_flag_action_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_flag_action_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_action_enum_t xed_flag_action_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-flag-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-flag-enum.h new file mode 100644 index 0000000..c941169 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-flag-enum.h @@ -0,0 +1,90 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-flag-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_FLAG_ENUM_H) +# define XED_FLAG_ENUM_H +#include "xed-common-hdrs.h" +#define XED_FLAG_INVALID_DEFINED 1 +#define XED_FLAG_of_DEFINED 1 +#define XED_FLAG_sf_DEFINED 1 +#define XED_FLAG_zf_DEFINED 1 +#define XED_FLAG_af_DEFINED 1 +#define XED_FLAG_pf_DEFINED 1 +#define XED_FLAG_cf_DEFINED 1 +#define XED_FLAG_df_DEFINED 1 +#define XED_FLAG_vif_DEFINED 1 +#define XED_FLAG_iopl_DEFINED 1 +#define XED_FLAG_if_DEFINED 1 +#define XED_FLAG_ac_DEFINED 1 +#define XED_FLAG_vm_DEFINED 1 +#define XED_FLAG_rf_DEFINED 1 +#define XED_FLAG_nt_DEFINED 1 +#define XED_FLAG_tf_DEFINED 1 +#define XED_FLAG_id_DEFINED 1 +#define XED_FLAG_vip_DEFINED 1 +#define XED_FLAG_fc0_DEFINED 1 +#define XED_FLAG_fc1_DEFINED 1 +#define XED_FLAG_fc2_DEFINED 1 +#define XED_FLAG_fc3_DEFINED 1 +#define XED_FLAG_LAST_DEFINED 1 +typedef enum { + XED_FLAG_INVALID, + XED_FLAG_of, ///<< overflow flag + XED_FLAG_sf, ///< sign flag + XED_FLAG_zf, ///< zero flag + XED_FLAG_af, ///< auxiliary flag + XED_FLAG_pf, ///< parity flag + XED_FLAG_cf, ///< carry flag + XED_FLAG_df, ///< direction flag + XED_FLAG_vif, ///< virtual interrupt flag + XED_FLAG_iopl, ///< I/O privilege level + XED_FLAG_if, ///< interrupt flag + XED_FLAG_ac, ///< alignment check + XED_FLAG_vm, ///< virtual-8086 mode + XED_FLAG_rf, ///< resume flag + XED_FLAG_nt, ///< nested task + XED_FLAG_tf, ///< traf flag + XED_FLAG_id, ///< ID flag + XED_FLAG_vip, ///< virtual interrupt pending + XED_FLAG_fc0, ///< x87 FC0 flag + XED_FLAG_fc1, ///< x87 FC1 flag + XED_FLAG_fc2, ///< x87 FC2 flag + XED_FLAG_fc3, ///< x87 FC3 flag + XED_FLAG_LAST +} xed_flag_enum_t; + +/// This converts strings to #xed_flag_enum_t types. +/// @param s A C-string. +/// @return #xed_flag_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_enum_t str2xed_flag_enum_t(const char* s); +/// This converts strings to #xed_flag_enum_t types. +/// @param p An enumeration element of type xed_flag_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_flag_enum_t2str(const xed_flag_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_flag_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_enum_t xed_flag_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-flags.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-flags.h new file mode 100644 index 0000000..c568304 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-flags.h @@ -0,0 +1,233 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-flags.h +/// + +#ifndef XED_FLAGS_H +# define XED_FLAGS_H + +#include "xed-types.h" +#include "xed-portability.h" +#include "xed-flag-enum.h" +#include "xed-flag-action-enum.h" +#include "xed-gen-table-defs.h" + + +//////////////////////////////////////////////////////////////////////////// +/// @ingroup FLAGS +/// a union of flags bits +union xed_flag_set_s { + xed_uint32_t flat; + struct { + xed_uint32_t cf:1; ///< bit 0 + xed_uint32_t must_be_1:1; + xed_uint32_t pf:1; + xed_uint32_t must_be_0a:1; + + xed_uint32_t af:1; ///< bit 4 + xed_uint32_t must_be_0b:1; + xed_uint32_t zf:1; + xed_uint32_t sf:1; + + xed_uint32_t tf:1; ///< bit 8 + xed_uint32_t _if:1; ///< underscore to avoid token clash + xed_uint32_t df:1; + xed_uint32_t of:1; + + xed_uint32_t iopl:2; ///< A 2-bit field, bits 12-13 + xed_uint32_t nt:1; + xed_uint32_t must_be_0c:1; + + xed_uint32_t rf:1; ///< bit 16 + xed_uint32_t vm:1; + xed_uint32_t ac:1; + xed_uint32_t vif:1; + + xed_uint32_t vip:1; ///< bit 20 + xed_uint32_t id:1; ///< bit 21 + xed_uint32_t must_be_0d:2; ///< bits 22-23 + + xed_uint32_t must_be_0e:4; ///< bits 24-27 + + // fc0,fc1,fc2,fc3 are not really part of rflags but I put them + // here to save space. These bits are only used for x87 + // instructions. + xed_uint32_t fc0:1; ///< x87 flag FC0 (not really part of rflags) + xed_uint32_t fc1:1; ///< x87 flag FC1 (not really part of rflags) + xed_uint32_t fc2:1; ///< x87 flag FC2 (not really part of rflags) + xed_uint32_t fc3:1; ///< x87 flag FC3 (not really part of rflags) + } s; + +}; + +typedef union xed_flag_set_s xed_flag_set_t; +/// @ingroup FLAGS +/// @name Flag-set accessors +//@{ +/// @ingroup FLAGS +/// print the flag set in the supplied buffer +XED_DLL_EXPORT int xed_flag_set_print(const xed_flag_set_t* p, char* buf, int buflen); +/// @ingroup FLAGS +/// returns true if this object has a subset of the flags of the +/// "other" object. +XED_DLL_EXPORT xed_bool_t xed_flag_set_is_subset_of(const xed_flag_set_t* p, + const xed_flag_set_t* other); +//@} + + +//////////////////////////////////////////////////////////////////////////// + +/// @ingroup FLAGS +/// Associated with each flag field there can be one action. +typedef struct xed_flag_enum_s { + xed_flag_enum_t flag; + // there are at most two actions per flag. The 2nd may be invalid. + xed_flag_action_enum_t action; +} xed_flag_action_t; + + + + +/// @ingroup FLAGS +/// @name Lowest-level flag-action accessors +//@{ +/// @ingroup FLAGS +/// get the name of the flag +XED_DLL_EXPORT xed_flag_enum_t +xed_flag_action_get_flag_name(const xed_flag_action_t* p); +/// @ingroup FLAGS +/// return the action +XED_DLL_EXPORT xed_flag_action_enum_t +xed_flag_action_get_action(const xed_flag_action_t* p, unsigned int i); +/// @ingroup FLAGS +/// returns true if the specified action is invalid. Only the 2nd flag might be invalid. +XED_DLL_EXPORT xed_bool_t +xed_flag_action_action_invalid(const xed_flag_action_enum_t a); +/// @ingroup FLAGS +/// print the flag & actions +XED_DLL_EXPORT int xed_flag_action_print(const xed_flag_action_t* p, char* buf, int buflen); +/// @ingroup FLAGS +/// returns true if either action is a read +XED_DLL_EXPORT xed_bool_t +xed_flag_action_read_flag(const xed_flag_action_t* p ); +/// @ingroup FLAGS +/// returns true if either action is a write +XED_DLL_EXPORT xed_bool_t +xed_flag_action_writes_flag(const xed_flag_action_t* p); + +/// @ingroup FLAGS +/// test to see if the specific action is a read +XED_DLL_EXPORT xed_bool_t +xed_flag_action_read_action( xed_flag_action_enum_t a); +/// @ingroup FLAGS +/// test to see if a specific action is a write +XED_DLL_EXPORT xed_bool_t +xed_flag_action_write_action( xed_flag_action_enum_t a); +//@} + +//////////////////////////////////////////////////////////////////////////// + +/// @ingroup FLAGS +/// A collection of #xed_flag_action_t's and unions of read and written flags +typedef struct xed_simple_flag_s +{ + ///number of flag actions associated with this record + xed_uint8_t nflags; + + xed_uint8_t may_write; /* 1/0, only using one bit */ + xed_uint8_t must_write; /* 1/0, only using one bit */ + + ///union of read flags + xed_flag_set_t read; + + /// union of written flags (includes undefined flags); + xed_flag_set_t written; + + /// union of undefined flags; + xed_flag_set_t undefined; + + // index in to the xed_flag_action_table. nflags limits the # of entries. + xed_uint16_t fa_index; + +} xed_simple_flag_t; + +/// @ingroup FLAGS +/// @name Accessing the simple flags (Mid-level access) +//@{ +/// @ingroup FLAGS +/// returns the number of flag-actions +XED_DLL_EXPORT unsigned int +xed_simple_flag_get_nflags(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// return union of bits for read flags +XED_DLL_EXPORT const xed_flag_set_t* +xed_simple_flag_get_read_flag_set(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// return union of bits for written flags +XED_DLL_EXPORT const xed_flag_set_t* +xed_simple_flag_get_written_flag_set(const xed_simple_flag_t* p); + + +/// @ingroup FLAGS +/// return union of bits for undefined flags +XED_DLL_EXPORT const xed_flag_set_t* +xed_simple_flag_get_undefined_flag_set(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// Indicates the flags are only conditionally written. Usually MAY-writes +/// of the flags instructions that are dependent on a REP count. +XED_DLL_EXPORT xed_bool_t xed_simple_flag_get_may_write(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// the flags always written +XED_DLL_EXPORT xed_bool_t xed_simple_flag_get_must_write(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// return the specific flag-action. Very detailed low level information +XED_DLL_EXPORT const xed_flag_action_t* +xed_simple_flag_get_flag_action(const xed_simple_flag_t* p, unsigned int i); + +/// @ingroup FLAGS +/// boolean test to see if flags are read, scans the flags +XED_DLL_EXPORT xed_bool_t +xed_simple_flag_reads_flags(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// boolean test to see if flags are written, scans the flags +XED_DLL_EXPORT xed_bool_t xed_simple_flag_writes_flags(const xed_simple_flag_t* p); + +/// @ingroup FLAGS +/// print the flags +XED_DLL_EXPORT int xed_simple_flag_print(const xed_simple_flag_t* p, char* buf, int buflen); + +/// @ingroup FLAGS +/// Return the flags as a mask +static XED_INLINE unsigned int xed_flag_set_mask(const xed_flag_set_t* p) { + return p->flat; // FIXME: could mask out the X87 flags +} + +//@} + +//////////////////////////////////////////////////////////////////////////// + + +//////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-format-options.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-format-options.h new file mode 100644 index 0000000..72665ac --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-format-options.h @@ -0,0 +1,68 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-format-options.h + + +#ifndef XED_FORMAT_OPTIONS_H +# define XED_FORMAT_OPTIONS_H +#include "xed-types.h" + + +/// @name Formatting options +//@{ + +/// Options for the disasembly formatting functions. Set once during +/// initialization by a calling #xed_format_set_options +/// @ingroup PRINT +typedef struct { + /// by default, XED prints the hex address before any symbolic name for + /// branch targets. If set to zero, then XED will not print the hex + /// address before a valid symbolic name. + unsigned int hex_address_before_symbolic_name; + + /// Simple XML output format for the Intel syntax disassembly. + unsigned int xml_a; + /// Include flags in the XML formatting (must also supply xml_a) + unsigned int xml_f; + + /// omit unit scale "*1" + unsigned int omit_unit_scale; + + /// do not sign extend signed immediates + unsigned int no_sign_extend_signed_immediates; + + /// write-mask-with-curly-brackets, omit k0 + unsigned int write_mask_curly_k0; + + /// lowercase hexadecimal + xed_bool_t lowercase_hex; + + /// Show negative memory displacements as + /// positive numbers. + xed_bool_t positive_memory_displacements; + +} xed_format_options_t; + +/// Optionally, customize the disassembly formatting options by passing +/// in a #xed_format_options_t structure. +/// @ingroup PRINT +XED_DLL_EXPORT void +xed_format_set_options(xed_format_options_t format_options); +//@} + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-gen-table-defs.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-gen-table-defs.h new file mode 100644 index 0000000..26eb1f7 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-gen-table-defs.h @@ -0,0 +1,39 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-gen-table-defs.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_GEN_TABLE_DEFS_H) +# define XED_GEN_TABLE_DEFS_H +#define XED_ICLASS_NAME_STR_MAX 142 +#define XED_MAX_ATTRIBUTE_COUNT 93 +#define XED_MAX_INST_TABLE_NODES 7614 +#define XED_MAX_OPERAND_TABLE_NODES 1502 +#define XED_MAX_OPERAND_SEQUENCES 8974 +#define XED_MAX_REQUIRED_SIMPLE_FLAGS_ENTRIES 99 +#define XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES 37 +#define XED_MAX_GLOBAL_FLAG_ACTIONS 472 +#define XED_MAX_IFORMS_PER_ICLASS 28 +#define XED_MAX_REQUIRED_ATTRIBUTES 205 +#define XED_MAX_CONVERT_PATTERNS 5 +#define XED_MAX_DECORATIONS_PER_OPERAND 3 +#define XED_MAX_MAP_VEX 3 +#define XED_MAX_MAP_EVEX 6 +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-get-time.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-get-time.h new file mode 100644 index 0000000..9c27cdc --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-get-time.h @@ -0,0 +1,75 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_GET_TIME_H) +# define XED_GET_TIME_H + +# include "xed-portability.h" +# include "xed-types.h" +# if defined(__INTEL_COMPILER) && __INTEL_COMPILER > 810 && !defined(_M_IA64) +# include +# endif +# if defined(__INTEL_COMPILER) && __INTEL_COMPILER >= 810 && !defined(_M_IA64) +# if __INTEL_COMPILER < 1000 +# pragma intrinsic(__rdtsc) +# endif +# endif +# if !defined(__INTEL_COMPILER) + /* MSVS8 and later */ +# if defined(_MSC_VER) && _MSC_VER >= 1400 && !defined(_M_IA64) +# include +# pragma intrinsic(__rdtsc) +# endif +# if defined(__GNUC__) +# if defined(__i386__) || defined(i386) || defined(i686) || defined(__x86_64__) +# include +# endif +# endif +# endif + + +static XED_INLINE xed_uint64_t xed_get_time(void) { + xed_union64_t ticks; +# if defined(__GNUC__) +# if defined(__i386__) || defined(i386) || defined(i686) || defined(__x86_64__) +# if __GNUC__ >= 5 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 9 && __GNUC_PATCHLEVEL__ >= 3) + ticks.u64 = __rdtsc(); +# else + __asm__ volatile ("rdtsc":"=a" (ticks.s.lo32), "=d"(ticks.s.hi32)); +# endif +# define XED_FOUND_RDTSC +# endif +# endif +# if defined(__INTEL_COMPILER) && __INTEL_COMPILER>=810 && !defined(_M_IA64) + ticks.u64 = __rdtsc(); +# define XED_FOUND_RDTSC +# endif +# if !defined(__INTEL_COMPILER) +# if !defined(XED_FOUND_RDTSC) && defined(_MSC_VER) && _MSC_VER >= 1400 && \ + !defined(_M_IA64) && !defined(_MANAGED) /* MSVS7, 8 */ + ticks.u64 = __rdtsc(); +# define XED_FOUND_RDTSC +# endif +# endif +# if !defined(XED_FOUND_RDTSC) + ticks.u64 = 0; +# endif + return ticks.u64; +} +#undef XED_FOUND_RDTSC +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-iclass-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iclass-enum.h new file mode 100644 index 0000000..1fd9867 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iclass-enum.h @@ -0,0 +1,3534 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-iclass-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ICLASS_ENUM_H) +# define XED_ICLASS_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ICLASS_INVALID_DEFINED 1 +#define XED_ICLASS_AAA_DEFINED 1 +#define XED_ICLASS_AAD_DEFINED 1 +#define XED_ICLASS_AAM_DEFINED 1 +#define XED_ICLASS_AAS_DEFINED 1 +#define XED_ICLASS_ADC_DEFINED 1 +#define XED_ICLASS_ADCX_DEFINED 1 +#define XED_ICLASS_ADC_LOCK_DEFINED 1 +#define XED_ICLASS_ADD_DEFINED 1 +#define XED_ICLASS_ADDPD_DEFINED 1 +#define XED_ICLASS_ADDPS_DEFINED 1 +#define XED_ICLASS_ADDSD_DEFINED 1 +#define XED_ICLASS_ADDSS_DEFINED 1 +#define XED_ICLASS_ADDSUBPD_DEFINED 1 +#define XED_ICLASS_ADDSUBPS_DEFINED 1 +#define XED_ICLASS_ADD_LOCK_DEFINED 1 +#define XED_ICLASS_ADOX_DEFINED 1 +#define XED_ICLASS_AESDEC_DEFINED 1 +#define XED_ICLASS_AESDEC128KL_DEFINED 1 +#define XED_ICLASS_AESDEC256KL_DEFINED 1 +#define XED_ICLASS_AESDECLAST_DEFINED 1 +#define XED_ICLASS_AESDECWIDE128KL_DEFINED 1 +#define XED_ICLASS_AESDECWIDE256KL_DEFINED 1 +#define XED_ICLASS_AESENC_DEFINED 1 +#define XED_ICLASS_AESENC128KL_DEFINED 1 +#define XED_ICLASS_AESENC256KL_DEFINED 1 +#define XED_ICLASS_AESENCLAST_DEFINED 1 +#define XED_ICLASS_AESENCWIDE128KL_DEFINED 1 +#define XED_ICLASS_AESENCWIDE256KL_DEFINED 1 +#define XED_ICLASS_AESIMC_DEFINED 1 +#define XED_ICLASS_AESKEYGENASSIST_DEFINED 1 +#define XED_ICLASS_AND_DEFINED 1 +#define XED_ICLASS_ANDN_DEFINED 1 +#define XED_ICLASS_ANDNPD_DEFINED 1 +#define XED_ICLASS_ANDNPS_DEFINED 1 +#define XED_ICLASS_ANDPD_DEFINED 1 +#define XED_ICLASS_ANDPS_DEFINED 1 +#define XED_ICLASS_AND_LOCK_DEFINED 1 +#define XED_ICLASS_ARPL_DEFINED 1 +#define XED_ICLASS_BEXTR_DEFINED 1 +#define XED_ICLASS_BEXTR_XOP_DEFINED 1 +#define XED_ICLASS_BLCFILL_DEFINED 1 +#define XED_ICLASS_BLCI_DEFINED 1 +#define XED_ICLASS_BLCIC_DEFINED 1 +#define XED_ICLASS_BLCMSK_DEFINED 1 +#define XED_ICLASS_BLCS_DEFINED 1 +#define XED_ICLASS_BLENDPD_DEFINED 1 +#define XED_ICLASS_BLENDPS_DEFINED 1 +#define XED_ICLASS_BLENDVPD_DEFINED 1 +#define XED_ICLASS_BLENDVPS_DEFINED 1 +#define XED_ICLASS_BLSFILL_DEFINED 1 +#define XED_ICLASS_BLSI_DEFINED 1 +#define XED_ICLASS_BLSIC_DEFINED 1 +#define XED_ICLASS_BLSMSK_DEFINED 1 +#define XED_ICLASS_BLSR_DEFINED 1 +#define XED_ICLASS_BNDCL_DEFINED 1 +#define XED_ICLASS_BNDCN_DEFINED 1 +#define XED_ICLASS_BNDCU_DEFINED 1 +#define XED_ICLASS_BNDLDX_DEFINED 1 +#define XED_ICLASS_BNDMK_DEFINED 1 +#define XED_ICLASS_BNDMOV_DEFINED 1 +#define XED_ICLASS_BNDSTX_DEFINED 1 +#define XED_ICLASS_BOUND_DEFINED 1 +#define XED_ICLASS_BSF_DEFINED 1 +#define XED_ICLASS_BSR_DEFINED 1 +#define XED_ICLASS_BSWAP_DEFINED 1 +#define XED_ICLASS_BT_DEFINED 1 +#define XED_ICLASS_BTC_DEFINED 1 +#define XED_ICLASS_BTC_LOCK_DEFINED 1 +#define XED_ICLASS_BTR_DEFINED 1 +#define XED_ICLASS_BTR_LOCK_DEFINED 1 +#define XED_ICLASS_BTS_DEFINED 1 +#define XED_ICLASS_BTS_LOCK_DEFINED 1 +#define XED_ICLASS_BZHI_DEFINED 1 +#define XED_ICLASS_CALL_FAR_DEFINED 1 +#define XED_ICLASS_CALL_NEAR_DEFINED 1 +#define XED_ICLASS_CBW_DEFINED 1 +#define XED_ICLASS_CDQ_DEFINED 1 +#define XED_ICLASS_CDQE_DEFINED 1 +#define XED_ICLASS_CLAC_DEFINED 1 +#define XED_ICLASS_CLC_DEFINED 1 +#define XED_ICLASS_CLD_DEFINED 1 +#define XED_ICLASS_CLDEMOTE_DEFINED 1 +#define XED_ICLASS_CLFLUSH_DEFINED 1 +#define XED_ICLASS_CLFLUSHOPT_DEFINED 1 +#define XED_ICLASS_CLGI_DEFINED 1 +#define XED_ICLASS_CLI_DEFINED 1 +#define XED_ICLASS_CLRSSBSY_DEFINED 1 +#define XED_ICLASS_CLTS_DEFINED 1 +#define XED_ICLASS_CLUI_DEFINED 1 +#define XED_ICLASS_CLWB_DEFINED 1 +#define XED_ICLASS_CLZERO_DEFINED 1 +#define XED_ICLASS_CMC_DEFINED 1 +#define XED_ICLASS_CMOVB_DEFINED 1 +#define XED_ICLASS_CMOVBE_DEFINED 1 +#define XED_ICLASS_CMOVL_DEFINED 1 +#define XED_ICLASS_CMOVLE_DEFINED 1 +#define XED_ICLASS_CMOVNB_DEFINED 1 +#define XED_ICLASS_CMOVNBE_DEFINED 1 +#define XED_ICLASS_CMOVNL_DEFINED 1 +#define XED_ICLASS_CMOVNLE_DEFINED 1 +#define XED_ICLASS_CMOVNO_DEFINED 1 +#define XED_ICLASS_CMOVNP_DEFINED 1 +#define XED_ICLASS_CMOVNS_DEFINED 1 +#define XED_ICLASS_CMOVNZ_DEFINED 1 +#define XED_ICLASS_CMOVO_DEFINED 1 +#define XED_ICLASS_CMOVP_DEFINED 1 +#define XED_ICLASS_CMOVS_DEFINED 1 +#define XED_ICLASS_CMOVZ_DEFINED 1 +#define XED_ICLASS_CMP_DEFINED 1 +#define XED_ICLASS_CMPPD_DEFINED 1 +#define XED_ICLASS_CMPPS_DEFINED 1 +#define XED_ICLASS_CMPSB_DEFINED 1 +#define XED_ICLASS_CMPSD_DEFINED 1 +#define XED_ICLASS_CMPSD_XMM_DEFINED 1 +#define XED_ICLASS_CMPSQ_DEFINED 1 +#define XED_ICLASS_CMPSS_DEFINED 1 +#define XED_ICLASS_CMPSW_DEFINED 1 +#define XED_ICLASS_CMPXCHG_DEFINED 1 +#define XED_ICLASS_CMPXCHG16B_DEFINED 1 +#define XED_ICLASS_CMPXCHG16B_LOCK_DEFINED 1 +#define XED_ICLASS_CMPXCHG8B_DEFINED 1 +#define XED_ICLASS_CMPXCHG8B_LOCK_DEFINED 1 +#define XED_ICLASS_CMPXCHG_LOCK_DEFINED 1 +#define XED_ICLASS_COMISD_DEFINED 1 +#define XED_ICLASS_COMISS_DEFINED 1 +#define XED_ICLASS_CPUID_DEFINED 1 +#define XED_ICLASS_CQO_DEFINED 1 +#define XED_ICLASS_CRC32_DEFINED 1 +#define XED_ICLASS_CVTDQ2PD_DEFINED 1 +#define XED_ICLASS_CVTDQ2PS_DEFINED 1 +#define XED_ICLASS_CVTPD2DQ_DEFINED 1 +#define XED_ICLASS_CVTPD2PI_DEFINED 1 +#define XED_ICLASS_CVTPD2PS_DEFINED 1 +#define XED_ICLASS_CVTPI2PD_DEFINED 1 +#define XED_ICLASS_CVTPI2PS_DEFINED 1 +#define XED_ICLASS_CVTPS2DQ_DEFINED 1 +#define XED_ICLASS_CVTPS2PD_DEFINED 1 +#define XED_ICLASS_CVTPS2PI_DEFINED 1 +#define XED_ICLASS_CVTSD2SI_DEFINED 1 +#define XED_ICLASS_CVTSD2SS_DEFINED 1 +#define XED_ICLASS_CVTSI2SD_DEFINED 1 +#define XED_ICLASS_CVTSI2SS_DEFINED 1 +#define XED_ICLASS_CVTSS2SD_DEFINED 1 +#define XED_ICLASS_CVTSS2SI_DEFINED 1 +#define XED_ICLASS_CVTTPD2DQ_DEFINED 1 +#define XED_ICLASS_CVTTPD2PI_DEFINED 1 +#define XED_ICLASS_CVTTPS2DQ_DEFINED 1 +#define XED_ICLASS_CVTTPS2PI_DEFINED 1 +#define XED_ICLASS_CVTTSD2SI_DEFINED 1 +#define XED_ICLASS_CVTTSS2SI_DEFINED 1 +#define XED_ICLASS_CWD_DEFINED 1 +#define XED_ICLASS_CWDE_DEFINED 1 +#define XED_ICLASS_DAA_DEFINED 1 +#define XED_ICLASS_DAS_DEFINED 1 +#define XED_ICLASS_DEC_DEFINED 1 +#define XED_ICLASS_DEC_LOCK_DEFINED 1 +#define XED_ICLASS_DIV_DEFINED 1 +#define XED_ICLASS_DIVPD_DEFINED 1 +#define XED_ICLASS_DIVPS_DEFINED 1 +#define XED_ICLASS_DIVSD_DEFINED 1 +#define XED_ICLASS_DIVSS_DEFINED 1 +#define XED_ICLASS_DPPD_DEFINED 1 +#define XED_ICLASS_DPPS_DEFINED 1 +#define XED_ICLASS_EMMS_DEFINED 1 +#define XED_ICLASS_ENCLS_DEFINED 1 +#define XED_ICLASS_ENCLU_DEFINED 1 +#define XED_ICLASS_ENCLV_DEFINED 1 +#define XED_ICLASS_ENCODEKEY128_DEFINED 1 +#define XED_ICLASS_ENCODEKEY256_DEFINED 1 +#define XED_ICLASS_ENDBR32_DEFINED 1 +#define XED_ICLASS_ENDBR64_DEFINED 1 +#define XED_ICLASS_ENQCMD_DEFINED 1 +#define XED_ICLASS_ENQCMDS_DEFINED 1 +#define XED_ICLASS_ENTER_DEFINED 1 +#define XED_ICLASS_EXTRACTPS_DEFINED 1 +#define XED_ICLASS_EXTRQ_DEFINED 1 +#define XED_ICLASS_F2XM1_DEFINED 1 +#define XED_ICLASS_FABS_DEFINED 1 +#define XED_ICLASS_FADD_DEFINED 1 +#define XED_ICLASS_FADDP_DEFINED 1 +#define XED_ICLASS_FBLD_DEFINED 1 +#define XED_ICLASS_FBSTP_DEFINED 1 +#define XED_ICLASS_FCHS_DEFINED 1 +#define XED_ICLASS_FCMOVB_DEFINED 1 +#define XED_ICLASS_FCMOVBE_DEFINED 1 +#define XED_ICLASS_FCMOVE_DEFINED 1 +#define XED_ICLASS_FCMOVNB_DEFINED 1 +#define XED_ICLASS_FCMOVNBE_DEFINED 1 +#define XED_ICLASS_FCMOVNE_DEFINED 1 +#define XED_ICLASS_FCMOVNU_DEFINED 1 +#define XED_ICLASS_FCMOVU_DEFINED 1 +#define XED_ICLASS_FCOM_DEFINED 1 +#define XED_ICLASS_FCOMI_DEFINED 1 +#define XED_ICLASS_FCOMIP_DEFINED 1 +#define XED_ICLASS_FCOMP_DEFINED 1 +#define XED_ICLASS_FCOMPP_DEFINED 1 +#define XED_ICLASS_FCOS_DEFINED 1 +#define XED_ICLASS_FDECSTP_DEFINED 1 +#define XED_ICLASS_FDISI8087_NOP_DEFINED 1 +#define XED_ICLASS_FDIV_DEFINED 1 +#define XED_ICLASS_FDIVP_DEFINED 1 +#define XED_ICLASS_FDIVR_DEFINED 1 +#define XED_ICLASS_FDIVRP_DEFINED 1 +#define XED_ICLASS_FEMMS_DEFINED 1 +#define XED_ICLASS_FENI8087_NOP_DEFINED 1 +#define XED_ICLASS_FFREE_DEFINED 1 +#define XED_ICLASS_FFREEP_DEFINED 1 +#define XED_ICLASS_FIADD_DEFINED 1 +#define XED_ICLASS_FICOM_DEFINED 1 +#define XED_ICLASS_FICOMP_DEFINED 1 +#define XED_ICLASS_FIDIV_DEFINED 1 +#define XED_ICLASS_FIDIVR_DEFINED 1 +#define XED_ICLASS_FILD_DEFINED 1 +#define XED_ICLASS_FIMUL_DEFINED 1 +#define XED_ICLASS_FINCSTP_DEFINED 1 +#define XED_ICLASS_FIST_DEFINED 1 +#define XED_ICLASS_FISTP_DEFINED 1 +#define XED_ICLASS_FISTTP_DEFINED 1 +#define XED_ICLASS_FISUB_DEFINED 1 +#define XED_ICLASS_FISUBR_DEFINED 1 +#define XED_ICLASS_FLD_DEFINED 1 +#define XED_ICLASS_FLD1_DEFINED 1 +#define XED_ICLASS_FLDCW_DEFINED 1 +#define XED_ICLASS_FLDENV_DEFINED 1 +#define XED_ICLASS_FLDL2E_DEFINED 1 +#define XED_ICLASS_FLDL2T_DEFINED 1 +#define XED_ICLASS_FLDLG2_DEFINED 1 +#define XED_ICLASS_FLDLN2_DEFINED 1 +#define XED_ICLASS_FLDPI_DEFINED 1 +#define XED_ICLASS_FLDZ_DEFINED 1 +#define XED_ICLASS_FMUL_DEFINED 1 +#define XED_ICLASS_FMULP_DEFINED 1 +#define XED_ICLASS_FNCLEX_DEFINED 1 +#define XED_ICLASS_FNINIT_DEFINED 1 +#define XED_ICLASS_FNOP_DEFINED 1 +#define XED_ICLASS_FNSAVE_DEFINED 1 +#define XED_ICLASS_FNSTCW_DEFINED 1 +#define XED_ICLASS_FNSTENV_DEFINED 1 +#define XED_ICLASS_FNSTSW_DEFINED 1 +#define XED_ICLASS_FPATAN_DEFINED 1 +#define XED_ICLASS_FPREM_DEFINED 1 +#define XED_ICLASS_FPREM1_DEFINED 1 +#define XED_ICLASS_FPTAN_DEFINED 1 +#define XED_ICLASS_FRNDINT_DEFINED 1 +#define XED_ICLASS_FRSTOR_DEFINED 1 +#define XED_ICLASS_FSCALE_DEFINED 1 +#define XED_ICLASS_FSETPM287_NOP_DEFINED 1 +#define XED_ICLASS_FSIN_DEFINED 1 +#define XED_ICLASS_FSINCOS_DEFINED 1 +#define XED_ICLASS_FSQRT_DEFINED 1 +#define XED_ICLASS_FST_DEFINED 1 +#define XED_ICLASS_FSTP_DEFINED 1 +#define XED_ICLASS_FSTPNCE_DEFINED 1 +#define XED_ICLASS_FSUB_DEFINED 1 +#define XED_ICLASS_FSUBP_DEFINED 1 +#define XED_ICLASS_FSUBR_DEFINED 1 +#define XED_ICLASS_FSUBRP_DEFINED 1 +#define XED_ICLASS_FTST_DEFINED 1 +#define XED_ICLASS_FUCOM_DEFINED 1 +#define XED_ICLASS_FUCOMI_DEFINED 1 +#define XED_ICLASS_FUCOMIP_DEFINED 1 +#define XED_ICLASS_FUCOMP_DEFINED 1 +#define XED_ICLASS_FUCOMPP_DEFINED 1 +#define XED_ICLASS_FWAIT_DEFINED 1 +#define XED_ICLASS_FXAM_DEFINED 1 +#define XED_ICLASS_FXCH_DEFINED 1 +#define XED_ICLASS_FXRSTOR_DEFINED 1 +#define XED_ICLASS_FXRSTOR64_DEFINED 1 +#define XED_ICLASS_FXSAVE_DEFINED 1 +#define XED_ICLASS_FXSAVE64_DEFINED 1 +#define XED_ICLASS_FXTRACT_DEFINED 1 +#define XED_ICLASS_FYL2X_DEFINED 1 +#define XED_ICLASS_FYL2XP1_DEFINED 1 +#define XED_ICLASS_GETSEC_DEFINED 1 +#define XED_ICLASS_GF2P8AFFINEINVQB_DEFINED 1 +#define XED_ICLASS_GF2P8AFFINEQB_DEFINED 1 +#define XED_ICLASS_GF2P8MULB_DEFINED 1 +#define XED_ICLASS_HADDPD_DEFINED 1 +#define XED_ICLASS_HADDPS_DEFINED 1 +#define XED_ICLASS_HLT_DEFINED 1 +#define XED_ICLASS_HRESET_DEFINED 1 +#define XED_ICLASS_HSUBPD_DEFINED 1 +#define XED_ICLASS_HSUBPS_DEFINED 1 +#define XED_ICLASS_IDIV_DEFINED 1 +#define XED_ICLASS_IMUL_DEFINED 1 +#define XED_ICLASS_IN_DEFINED 1 +#define XED_ICLASS_INC_DEFINED 1 +#define XED_ICLASS_INCSSPD_DEFINED 1 +#define XED_ICLASS_INCSSPQ_DEFINED 1 +#define XED_ICLASS_INC_LOCK_DEFINED 1 +#define XED_ICLASS_INSB_DEFINED 1 +#define XED_ICLASS_INSD_DEFINED 1 +#define XED_ICLASS_INSERTPS_DEFINED 1 +#define XED_ICLASS_INSERTQ_DEFINED 1 +#define XED_ICLASS_INSW_DEFINED 1 +#define XED_ICLASS_INT_DEFINED 1 +#define XED_ICLASS_INT1_DEFINED 1 +#define XED_ICLASS_INT3_DEFINED 1 +#define XED_ICLASS_INTO_DEFINED 1 +#define XED_ICLASS_INVD_DEFINED 1 +#define XED_ICLASS_INVEPT_DEFINED 1 +#define XED_ICLASS_INVLPG_DEFINED 1 +#define XED_ICLASS_INVLPGA_DEFINED 1 +#define XED_ICLASS_INVLPGB_DEFINED 1 +#define XED_ICLASS_INVPCID_DEFINED 1 +#define XED_ICLASS_INVVPID_DEFINED 1 +#define XED_ICLASS_IRET_DEFINED 1 +#define XED_ICLASS_IRETD_DEFINED 1 +#define XED_ICLASS_IRETQ_DEFINED 1 +#define XED_ICLASS_JB_DEFINED 1 +#define XED_ICLASS_JBE_DEFINED 1 +#define XED_ICLASS_JCXZ_DEFINED 1 +#define XED_ICLASS_JECXZ_DEFINED 1 +#define XED_ICLASS_JL_DEFINED 1 +#define XED_ICLASS_JLE_DEFINED 1 +#define XED_ICLASS_JMP_DEFINED 1 +#define XED_ICLASS_JMP_FAR_DEFINED 1 +#define XED_ICLASS_JNB_DEFINED 1 +#define XED_ICLASS_JNBE_DEFINED 1 +#define XED_ICLASS_JNL_DEFINED 1 +#define XED_ICLASS_JNLE_DEFINED 1 +#define XED_ICLASS_JNO_DEFINED 1 +#define XED_ICLASS_JNP_DEFINED 1 +#define XED_ICLASS_JNS_DEFINED 1 +#define XED_ICLASS_JNZ_DEFINED 1 +#define XED_ICLASS_JO_DEFINED 1 +#define XED_ICLASS_JP_DEFINED 1 +#define XED_ICLASS_JRCXZ_DEFINED 1 +#define XED_ICLASS_JS_DEFINED 1 +#define XED_ICLASS_JZ_DEFINED 1 +#define XED_ICLASS_KADDB_DEFINED 1 +#define XED_ICLASS_KADDD_DEFINED 1 +#define XED_ICLASS_KADDQ_DEFINED 1 +#define XED_ICLASS_KADDW_DEFINED 1 +#define XED_ICLASS_KANDB_DEFINED 1 +#define XED_ICLASS_KANDD_DEFINED 1 +#define XED_ICLASS_KANDNB_DEFINED 1 +#define XED_ICLASS_KANDND_DEFINED 1 +#define XED_ICLASS_KANDNQ_DEFINED 1 +#define XED_ICLASS_KANDNW_DEFINED 1 +#define XED_ICLASS_KANDQ_DEFINED 1 +#define XED_ICLASS_KANDW_DEFINED 1 +#define XED_ICLASS_KMOVB_DEFINED 1 +#define XED_ICLASS_KMOVD_DEFINED 1 +#define XED_ICLASS_KMOVQ_DEFINED 1 +#define XED_ICLASS_KMOVW_DEFINED 1 +#define XED_ICLASS_KNOTB_DEFINED 1 +#define XED_ICLASS_KNOTD_DEFINED 1 +#define XED_ICLASS_KNOTQ_DEFINED 1 +#define XED_ICLASS_KNOTW_DEFINED 1 +#define XED_ICLASS_KORB_DEFINED 1 +#define XED_ICLASS_KORD_DEFINED 1 +#define XED_ICLASS_KORQ_DEFINED 1 +#define XED_ICLASS_KORTESTB_DEFINED 1 +#define XED_ICLASS_KORTESTD_DEFINED 1 +#define XED_ICLASS_KORTESTQ_DEFINED 1 +#define XED_ICLASS_KORTESTW_DEFINED 1 +#define XED_ICLASS_KORW_DEFINED 1 +#define XED_ICLASS_KSHIFTLB_DEFINED 1 +#define XED_ICLASS_KSHIFTLD_DEFINED 1 +#define XED_ICLASS_KSHIFTLQ_DEFINED 1 +#define XED_ICLASS_KSHIFTLW_DEFINED 1 +#define XED_ICLASS_KSHIFTRB_DEFINED 1 +#define XED_ICLASS_KSHIFTRD_DEFINED 1 +#define XED_ICLASS_KSHIFTRQ_DEFINED 1 +#define XED_ICLASS_KSHIFTRW_DEFINED 1 +#define XED_ICLASS_KTESTB_DEFINED 1 +#define XED_ICLASS_KTESTD_DEFINED 1 +#define XED_ICLASS_KTESTQ_DEFINED 1 +#define XED_ICLASS_KTESTW_DEFINED 1 +#define XED_ICLASS_KUNPCKBW_DEFINED 1 +#define XED_ICLASS_KUNPCKDQ_DEFINED 1 +#define XED_ICLASS_KUNPCKWD_DEFINED 1 +#define XED_ICLASS_KXNORB_DEFINED 1 +#define XED_ICLASS_KXNORD_DEFINED 1 +#define XED_ICLASS_KXNORQ_DEFINED 1 +#define XED_ICLASS_KXNORW_DEFINED 1 +#define XED_ICLASS_KXORB_DEFINED 1 +#define XED_ICLASS_KXORD_DEFINED 1 +#define XED_ICLASS_KXORQ_DEFINED 1 +#define XED_ICLASS_KXORW_DEFINED 1 +#define XED_ICLASS_LAHF_DEFINED 1 +#define XED_ICLASS_LAR_DEFINED 1 +#define XED_ICLASS_LDDQU_DEFINED 1 +#define XED_ICLASS_LDMXCSR_DEFINED 1 +#define XED_ICLASS_LDS_DEFINED 1 +#define XED_ICLASS_LDTILECFG_DEFINED 1 +#define XED_ICLASS_LEA_DEFINED 1 +#define XED_ICLASS_LEAVE_DEFINED 1 +#define XED_ICLASS_LES_DEFINED 1 +#define XED_ICLASS_LFENCE_DEFINED 1 +#define XED_ICLASS_LFS_DEFINED 1 +#define XED_ICLASS_LGDT_DEFINED 1 +#define XED_ICLASS_LGS_DEFINED 1 +#define XED_ICLASS_LIDT_DEFINED 1 +#define XED_ICLASS_LLDT_DEFINED 1 +#define XED_ICLASS_LLWPCB_DEFINED 1 +#define XED_ICLASS_LMSW_DEFINED 1 +#define XED_ICLASS_LOADIWKEY_DEFINED 1 +#define XED_ICLASS_LODSB_DEFINED 1 +#define XED_ICLASS_LODSD_DEFINED 1 +#define XED_ICLASS_LODSQ_DEFINED 1 +#define XED_ICLASS_LODSW_DEFINED 1 +#define XED_ICLASS_LOOP_DEFINED 1 +#define XED_ICLASS_LOOPE_DEFINED 1 +#define XED_ICLASS_LOOPNE_DEFINED 1 +#define XED_ICLASS_LSL_DEFINED 1 +#define XED_ICLASS_LSS_DEFINED 1 +#define XED_ICLASS_LTR_DEFINED 1 +#define XED_ICLASS_LWPINS_DEFINED 1 +#define XED_ICLASS_LWPVAL_DEFINED 1 +#define XED_ICLASS_LZCNT_DEFINED 1 +#define XED_ICLASS_MASKMOVDQU_DEFINED 1 +#define XED_ICLASS_MASKMOVQ_DEFINED 1 +#define XED_ICLASS_MAXPD_DEFINED 1 +#define XED_ICLASS_MAXPS_DEFINED 1 +#define XED_ICLASS_MAXSD_DEFINED 1 +#define XED_ICLASS_MAXSS_DEFINED 1 +#define XED_ICLASS_MCOMMIT_DEFINED 1 +#define XED_ICLASS_MFENCE_DEFINED 1 +#define XED_ICLASS_MINPD_DEFINED 1 +#define XED_ICLASS_MINPS_DEFINED 1 +#define XED_ICLASS_MINSD_DEFINED 1 +#define XED_ICLASS_MINSS_DEFINED 1 +#define XED_ICLASS_MONITOR_DEFINED 1 +#define XED_ICLASS_MONITORX_DEFINED 1 +#define XED_ICLASS_MOV_DEFINED 1 +#define XED_ICLASS_MOVAPD_DEFINED 1 +#define XED_ICLASS_MOVAPS_DEFINED 1 +#define XED_ICLASS_MOVBE_DEFINED 1 +#define XED_ICLASS_MOVD_DEFINED 1 +#define XED_ICLASS_MOVDDUP_DEFINED 1 +#define XED_ICLASS_MOVDIR64B_DEFINED 1 +#define XED_ICLASS_MOVDIRI_DEFINED 1 +#define XED_ICLASS_MOVDQ2Q_DEFINED 1 +#define XED_ICLASS_MOVDQA_DEFINED 1 +#define XED_ICLASS_MOVDQU_DEFINED 1 +#define XED_ICLASS_MOVHLPS_DEFINED 1 +#define XED_ICLASS_MOVHPD_DEFINED 1 +#define XED_ICLASS_MOVHPS_DEFINED 1 +#define XED_ICLASS_MOVLHPS_DEFINED 1 +#define XED_ICLASS_MOVLPD_DEFINED 1 +#define XED_ICLASS_MOVLPS_DEFINED 1 +#define XED_ICLASS_MOVMSKPD_DEFINED 1 +#define XED_ICLASS_MOVMSKPS_DEFINED 1 +#define XED_ICLASS_MOVNTDQ_DEFINED 1 +#define XED_ICLASS_MOVNTDQA_DEFINED 1 +#define XED_ICLASS_MOVNTI_DEFINED 1 +#define XED_ICLASS_MOVNTPD_DEFINED 1 +#define XED_ICLASS_MOVNTPS_DEFINED 1 +#define XED_ICLASS_MOVNTQ_DEFINED 1 +#define XED_ICLASS_MOVNTSD_DEFINED 1 +#define XED_ICLASS_MOVNTSS_DEFINED 1 +#define XED_ICLASS_MOVQ_DEFINED 1 +#define XED_ICLASS_MOVQ2DQ_DEFINED 1 +#define XED_ICLASS_MOVSB_DEFINED 1 +#define XED_ICLASS_MOVSD_DEFINED 1 +#define XED_ICLASS_MOVSD_XMM_DEFINED 1 +#define XED_ICLASS_MOVSHDUP_DEFINED 1 +#define XED_ICLASS_MOVSLDUP_DEFINED 1 +#define XED_ICLASS_MOVSQ_DEFINED 1 +#define XED_ICLASS_MOVSS_DEFINED 1 +#define XED_ICLASS_MOVSW_DEFINED 1 +#define XED_ICLASS_MOVSX_DEFINED 1 +#define XED_ICLASS_MOVSXD_DEFINED 1 +#define XED_ICLASS_MOVUPD_DEFINED 1 +#define XED_ICLASS_MOVUPS_DEFINED 1 +#define XED_ICLASS_MOVZX_DEFINED 1 +#define XED_ICLASS_MOV_CR_DEFINED 1 +#define XED_ICLASS_MOV_DR_DEFINED 1 +#define XED_ICLASS_MPSADBW_DEFINED 1 +#define XED_ICLASS_MUL_DEFINED 1 +#define XED_ICLASS_MULPD_DEFINED 1 +#define XED_ICLASS_MULPS_DEFINED 1 +#define XED_ICLASS_MULSD_DEFINED 1 +#define XED_ICLASS_MULSS_DEFINED 1 +#define XED_ICLASS_MULX_DEFINED 1 +#define XED_ICLASS_MWAIT_DEFINED 1 +#define XED_ICLASS_MWAITX_DEFINED 1 +#define XED_ICLASS_NEG_DEFINED 1 +#define XED_ICLASS_NEG_LOCK_DEFINED 1 +#define XED_ICLASS_NOP_DEFINED 1 +#define XED_ICLASS_NOP2_DEFINED 1 +#define XED_ICLASS_NOP3_DEFINED 1 +#define XED_ICLASS_NOP4_DEFINED 1 +#define XED_ICLASS_NOP5_DEFINED 1 +#define XED_ICLASS_NOP6_DEFINED 1 +#define XED_ICLASS_NOP7_DEFINED 1 +#define XED_ICLASS_NOP8_DEFINED 1 +#define XED_ICLASS_NOP9_DEFINED 1 +#define XED_ICLASS_NOT_DEFINED 1 +#define XED_ICLASS_NOT_LOCK_DEFINED 1 +#define XED_ICLASS_OR_DEFINED 1 +#define XED_ICLASS_ORPD_DEFINED 1 +#define XED_ICLASS_ORPS_DEFINED 1 +#define XED_ICLASS_OR_LOCK_DEFINED 1 +#define XED_ICLASS_OUT_DEFINED 1 +#define XED_ICLASS_OUTSB_DEFINED 1 +#define XED_ICLASS_OUTSD_DEFINED 1 +#define XED_ICLASS_OUTSW_DEFINED 1 +#define XED_ICLASS_PABSB_DEFINED 1 +#define XED_ICLASS_PABSD_DEFINED 1 +#define XED_ICLASS_PABSW_DEFINED 1 +#define XED_ICLASS_PACKSSDW_DEFINED 1 +#define XED_ICLASS_PACKSSWB_DEFINED 1 +#define XED_ICLASS_PACKUSDW_DEFINED 1 +#define XED_ICLASS_PACKUSWB_DEFINED 1 +#define XED_ICLASS_PADDB_DEFINED 1 +#define XED_ICLASS_PADDD_DEFINED 1 +#define XED_ICLASS_PADDQ_DEFINED 1 +#define XED_ICLASS_PADDSB_DEFINED 1 +#define XED_ICLASS_PADDSW_DEFINED 1 +#define XED_ICLASS_PADDUSB_DEFINED 1 +#define XED_ICLASS_PADDUSW_DEFINED 1 +#define XED_ICLASS_PADDW_DEFINED 1 +#define XED_ICLASS_PALIGNR_DEFINED 1 +#define XED_ICLASS_PAND_DEFINED 1 +#define XED_ICLASS_PANDN_DEFINED 1 +#define XED_ICLASS_PAUSE_DEFINED 1 +#define XED_ICLASS_PAVGB_DEFINED 1 +#define XED_ICLASS_PAVGUSB_DEFINED 1 +#define XED_ICLASS_PAVGW_DEFINED 1 +#define XED_ICLASS_PBLENDVB_DEFINED 1 +#define XED_ICLASS_PBLENDW_DEFINED 1 +#define XED_ICLASS_PCLMULQDQ_DEFINED 1 +#define XED_ICLASS_PCMPEQB_DEFINED 1 +#define XED_ICLASS_PCMPEQD_DEFINED 1 +#define XED_ICLASS_PCMPEQQ_DEFINED 1 +#define XED_ICLASS_PCMPEQW_DEFINED 1 +#define XED_ICLASS_PCMPESTRI_DEFINED 1 +#define XED_ICLASS_PCMPESTRI64_DEFINED 1 +#define XED_ICLASS_PCMPESTRM_DEFINED 1 +#define XED_ICLASS_PCMPESTRM64_DEFINED 1 +#define XED_ICLASS_PCMPGTB_DEFINED 1 +#define XED_ICLASS_PCMPGTD_DEFINED 1 +#define XED_ICLASS_PCMPGTQ_DEFINED 1 +#define XED_ICLASS_PCMPGTW_DEFINED 1 +#define XED_ICLASS_PCMPISTRI_DEFINED 1 +#define XED_ICLASS_PCMPISTRI64_DEFINED 1 +#define XED_ICLASS_PCMPISTRM_DEFINED 1 +#define XED_ICLASS_PCONFIG_DEFINED 1 +#define XED_ICLASS_PDEP_DEFINED 1 +#define XED_ICLASS_PEXT_DEFINED 1 +#define XED_ICLASS_PEXTRB_DEFINED 1 +#define XED_ICLASS_PEXTRD_DEFINED 1 +#define XED_ICLASS_PEXTRQ_DEFINED 1 +#define XED_ICLASS_PEXTRW_DEFINED 1 +#define XED_ICLASS_PEXTRW_SSE4_DEFINED 1 +#define XED_ICLASS_PF2ID_DEFINED 1 +#define XED_ICLASS_PF2IW_DEFINED 1 +#define XED_ICLASS_PFACC_DEFINED 1 +#define XED_ICLASS_PFADD_DEFINED 1 +#define XED_ICLASS_PFCMPEQ_DEFINED 1 +#define XED_ICLASS_PFCMPGE_DEFINED 1 +#define XED_ICLASS_PFCMPGT_DEFINED 1 +#define XED_ICLASS_PFMAX_DEFINED 1 +#define XED_ICLASS_PFMIN_DEFINED 1 +#define XED_ICLASS_PFMUL_DEFINED 1 +#define XED_ICLASS_PFNACC_DEFINED 1 +#define XED_ICLASS_PFPNACC_DEFINED 1 +#define XED_ICLASS_PFRCP_DEFINED 1 +#define XED_ICLASS_PFRCPIT1_DEFINED 1 +#define XED_ICLASS_PFRCPIT2_DEFINED 1 +#define XED_ICLASS_PFRSQIT1_DEFINED 1 +#define XED_ICLASS_PFRSQRT_DEFINED 1 +#define XED_ICLASS_PFSUB_DEFINED 1 +#define XED_ICLASS_PFSUBR_DEFINED 1 +#define XED_ICLASS_PHADDD_DEFINED 1 +#define XED_ICLASS_PHADDSW_DEFINED 1 +#define XED_ICLASS_PHADDW_DEFINED 1 +#define XED_ICLASS_PHMINPOSUW_DEFINED 1 +#define XED_ICLASS_PHSUBD_DEFINED 1 +#define XED_ICLASS_PHSUBSW_DEFINED 1 +#define XED_ICLASS_PHSUBW_DEFINED 1 +#define XED_ICLASS_PI2FD_DEFINED 1 +#define XED_ICLASS_PI2FW_DEFINED 1 +#define XED_ICLASS_PINSRB_DEFINED 1 +#define XED_ICLASS_PINSRD_DEFINED 1 +#define XED_ICLASS_PINSRQ_DEFINED 1 +#define XED_ICLASS_PINSRW_DEFINED 1 +#define XED_ICLASS_PMADDUBSW_DEFINED 1 +#define XED_ICLASS_PMADDWD_DEFINED 1 +#define XED_ICLASS_PMAXSB_DEFINED 1 +#define XED_ICLASS_PMAXSD_DEFINED 1 +#define XED_ICLASS_PMAXSW_DEFINED 1 +#define XED_ICLASS_PMAXUB_DEFINED 1 +#define XED_ICLASS_PMAXUD_DEFINED 1 +#define XED_ICLASS_PMAXUW_DEFINED 1 +#define XED_ICLASS_PMINSB_DEFINED 1 +#define XED_ICLASS_PMINSD_DEFINED 1 +#define XED_ICLASS_PMINSW_DEFINED 1 +#define XED_ICLASS_PMINUB_DEFINED 1 +#define XED_ICLASS_PMINUD_DEFINED 1 +#define XED_ICLASS_PMINUW_DEFINED 1 +#define XED_ICLASS_PMOVMSKB_DEFINED 1 +#define XED_ICLASS_PMOVSXBD_DEFINED 1 +#define XED_ICLASS_PMOVSXBQ_DEFINED 1 +#define XED_ICLASS_PMOVSXBW_DEFINED 1 +#define XED_ICLASS_PMOVSXDQ_DEFINED 1 +#define XED_ICLASS_PMOVSXWD_DEFINED 1 +#define XED_ICLASS_PMOVSXWQ_DEFINED 1 +#define XED_ICLASS_PMOVZXBD_DEFINED 1 +#define XED_ICLASS_PMOVZXBQ_DEFINED 1 +#define XED_ICLASS_PMOVZXBW_DEFINED 1 +#define XED_ICLASS_PMOVZXDQ_DEFINED 1 +#define XED_ICLASS_PMOVZXWD_DEFINED 1 +#define XED_ICLASS_PMOVZXWQ_DEFINED 1 +#define XED_ICLASS_PMULDQ_DEFINED 1 +#define XED_ICLASS_PMULHRSW_DEFINED 1 +#define XED_ICLASS_PMULHRW_DEFINED 1 +#define XED_ICLASS_PMULHUW_DEFINED 1 +#define XED_ICLASS_PMULHW_DEFINED 1 +#define XED_ICLASS_PMULLD_DEFINED 1 +#define XED_ICLASS_PMULLW_DEFINED 1 +#define XED_ICLASS_PMULUDQ_DEFINED 1 +#define XED_ICLASS_POP_DEFINED 1 +#define XED_ICLASS_POPA_DEFINED 1 +#define XED_ICLASS_POPAD_DEFINED 1 +#define XED_ICLASS_POPCNT_DEFINED 1 +#define XED_ICLASS_POPF_DEFINED 1 +#define XED_ICLASS_POPFD_DEFINED 1 +#define XED_ICLASS_POPFQ_DEFINED 1 +#define XED_ICLASS_POR_DEFINED 1 +#define XED_ICLASS_PREFETCHNTA_DEFINED 1 +#define XED_ICLASS_PREFETCHT0_DEFINED 1 +#define XED_ICLASS_PREFETCHT1_DEFINED 1 +#define XED_ICLASS_PREFETCHT2_DEFINED 1 +#define XED_ICLASS_PREFETCHW_DEFINED 1 +#define XED_ICLASS_PREFETCHWT1_DEFINED 1 +#define XED_ICLASS_PREFETCH_EXCLUSIVE_DEFINED 1 +#define XED_ICLASS_PREFETCH_RESERVED_DEFINED 1 +#define XED_ICLASS_PSADBW_DEFINED 1 +#define XED_ICLASS_PSHUFB_DEFINED 1 +#define XED_ICLASS_PSHUFD_DEFINED 1 +#define XED_ICLASS_PSHUFHW_DEFINED 1 +#define XED_ICLASS_PSHUFLW_DEFINED 1 +#define XED_ICLASS_PSHUFW_DEFINED 1 +#define XED_ICLASS_PSIGNB_DEFINED 1 +#define XED_ICLASS_PSIGND_DEFINED 1 +#define XED_ICLASS_PSIGNW_DEFINED 1 +#define XED_ICLASS_PSLLD_DEFINED 1 +#define XED_ICLASS_PSLLDQ_DEFINED 1 +#define XED_ICLASS_PSLLQ_DEFINED 1 +#define XED_ICLASS_PSLLW_DEFINED 1 +#define XED_ICLASS_PSMASH_DEFINED 1 +#define XED_ICLASS_PSRAD_DEFINED 1 +#define XED_ICLASS_PSRAW_DEFINED 1 +#define XED_ICLASS_PSRLD_DEFINED 1 +#define XED_ICLASS_PSRLDQ_DEFINED 1 +#define XED_ICLASS_PSRLQ_DEFINED 1 +#define XED_ICLASS_PSRLW_DEFINED 1 +#define XED_ICLASS_PSUBB_DEFINED 1 +#define XED_ICLASS_PSUBD_DEFINED 1 +#define XED_ICLASS_PSUBQ_DEFINED 1 +#define XED_ICLASS_PSUBSB_DEFINED 1 +#define XED_ICLASS_PSUBSW_DEFINED 1 +#define XED_ICLASS_PSUBUSB_DEFINED 1 +#define XED_ICLASS_PSUBUSW_DEFINED 1 +#define XED_ICLASS_PSUBW_DEFINED 1 +#define XED_ICLASS_PSWAPD_DEFINED 1 +#define XED_ICLASS_PTEST_DEFINED 1 +#define XED_ICLASS_PTWRITE_DEFINED 1 +#define XED_ICLASS_PUNPCKHBW_DEFINED 1 +#define XED_ICLASS_PUNPCKHDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKHQDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKHWD_DEFINED 1 +#define XED_ICLASS_PUNPCKLBW_DEFINED 1 +#define XED_ICLASS_PUNPCKLDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKLQDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKLWD_DEFINED 1 +#define XED_ICLASS_PUSH_DEFINED 1 +#define XED_ICLASS_PUSHA_DEFINED 1 +#define XED_ICLASS_PUSHAD_DEFINED 1 +#define XED_ICLASS_PUSHF_DEFINED 1 +#define XED_ICLASS_PUSHFD_DEFINED 1 +#define XED_ICLASS_PUSHFQ_DEFINED 1 +#define XED_ICLASS_PVALIDATE_DEFINED 1 +#define XED_ICLASS_PXOR_DEFINED 1 +#define XED_ICLASS_RCL_DEFINED 1 +#define XED_ICLASS_RCPPS_DEFINED 1 +#define XED_ICLASS_RCPSS_DEFINED 1 +#define XED_ICLASS_RCR_DEFINED 1 +#define XED_ICLASS_RDFSBASE_DEFINED 1 +#define XED_ICLASS_RDGSBASE_DEFINED 1 +#define XED_ICLASS_RDMSR_DEFINED 1 +#define XED_ICLASS_RDPID_DEFINED 1 +#define XED_ICLASS_RDPKRU_DEFINED 1 +#define XED_ICLASS_RDPMC_DEFINED 1 +#define XED_ICLASS_RDPRU_DEFINED 1 +#define XED_ICLASS_RDRAND_DEFINED 1 +#define XED_ICLASS_RDSEED_DEFINED 1 +#define XED_ICLASS_RDSSPD_DEFINED 1 +#define XED_ICLASS_RDSSPQ_DEFINED 1 +#define XED_ICLASS_RDTSC_DEFINED 1 +#define XED_ICLASS_RDTSCP_DEFINED 1 +#define XED_ICLASS_REPE_CMPSB_DEFINED 1 +#define XED_ICLASS_REPE_CMPSD_DEFINED 1 +#define XED_ICLASS_REPE_CMPSQ_DEFINED 1 +#define XED_ICLASS_REPE_CMPSW_DEFINED 1 +#define XED_ICLASS_REPE_SCASB_DEFINED 1 +#define XED_ICLASS_REPE_SCASD_DEFINED 1 +#define XED_ICLASS_REPE_SCASQ_DEFINED 1 +#define XED_ICLASS_REPE_SCASW_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSB_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSD_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSQ_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSW_DEFINED 1 +#define XED_ICLASS_REPNE_SCASB_DEFINED 1 +#define XED_ICLASS_REPNE_SCASD_DEFINED 1 +#define XED_ICLASS_REPNE_SCASQ_DEFINED 1 +#define XED_ICLASS_REPNE_SCASW_DEFINED 1 +#define XED_ICLASS_REP_INSB_DEFINED 1 +#define XED_ICLASS_REP_INSD_DEFINED 1 +#define XED_ICLASS_REP_INSW_DEFINED 1 +#define XED_ICLASS_REP_LODSB_DEFINED 1 +#define XED_ICLASS_REP_LODSD_DEFINED 1 +#define XED_ICLASS_REP_LODSQ_DEFINED 1 +#define XED_ICLASS_REP_LODSW_DEFINED 1 +#define XED_ICLASS_REP_MONTMUL_DEFINED 1 +#define XED_ICLASS_REP_MOVSB_DEFINED 1 +#define XED_ICLASS_REP_MOVSD_DEFINED 1 +#define XED_ICLASS_REP_MOVSQ_DEFINED 1 +#define XED_ICLASS_REP_MOVSW_DEFINED 1 +#define XED_ICLASS_REP_OUTSB_DEFINED 1 +#define XED_ICLASS_REP_OUTSD_DEFINED 1 +#define XED_ICLASS_REP_OUTSW_DEFINED 1 +#define XED_ICLASS_REP_STOSB_DEFINED 1 +#define XED_ICLASS_REP_STOSD_DEFINED 1 +#define XED_ICLASS_REP_STOSQ_DEFINED 1 +#define XED_ICLASS_REP_STOSW_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTCBC_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTCFB_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTCTR_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTECB_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTOFB_DEFINED 1 +#define XED_ICLASS_REP_XSHA1_DEFINED 1 +#define XED_ICLASS_REP_XSHA256_DEFINED 1 +#define XED_ICLASS_REP_XSTORE_DEFINED 1 +#define XED_ICLASS_RET_FAR_DEFINED 1 +#define XED_ICLASS_RET_NEAR_DEFINED 1 +#define XED_ICLASS_RMPADJUST_DEFINED 1 +#define XED_ICLASS_RMPUPDATE_DEFINED 1 +#define XED_ICLASS_ROL_DEFINED 1 +#define XED_ICLASS_ROR_DEFINED 1 +#define XED_ICLASS_RORX_DEFINED 1 +#define XED_ICLASS_ROUNDPD_DEFINED 1 +#define XED_ICLASS_ROUNDPS_DEFINED 1 +#define XED_ICLASS_ROUNDSD_DEFINED 1 +#define XED_ICLASS_ROUNDSS_DEFINED 1 +#define XED_ICLASS_RSM_DEFINED 1 +#define XED_ICLASS_RSQRTPS_DEFINED 1 +#define XED_ICLASS_RSQRTSS_DEFINED 1 +#define XED_ICLASS_RSTORSSP_DEFINED 1 +#define XED_ICLASS_SAHF_DEFINED 1 +#define XED_ICLASS_SALC_DEFINED 1 +#define XED_ICLASS_SAR_DEFINED 1 +#define XED_ICLASS_SARX_DEFINED 1 +#define XED_ICLASS_SAVEPREVSSP_DEFINED 1 +#define XED_ICLASS_SBB_DEFINED 1 +#define XED_ICLASS_SBB_LOCK_DEFINED 1 +#define XED_ICLASS_SCASB_DEFINED 1 +#define XED_ICLASS_SCASD_DEFINED 1 +#define XED_ICLASS_SCASQ_DEFINED 1 +#define XED_ICLASS_SCASW_DEFINED 1 +#define XED_ICLASS_SEAMCALL_DEFINED 1 +#define XED_ICLASS_SEAMOPS_DEFINED 1 +#define XED_ICLASS_SEAMRET_DEFINED 1 +#define XED_ICLASS_SENDUIPI_DEFINED 1 +#define XED_ICLASS_SERIALIZE_DEFINED 1 +#define XED_ICLASS_SETB_DEFINED 1 +#define XED_ICLASS_SETBE_DEFINED 1 +#define XED_ICLASS_SETL_DEFINED 1 +#define XED_ICLASS_SETLE_DEFINED 1 +#define XED_ICLASS_SETNB_DEFINED 1 +#define XED_ICLASS_SETNBE_DEFINED 1 +#define XED_ICLASS_SETNL_DEFINED 1 +#define XED_ICLASS_SETNLE_DEFINED 1 +#define XED_ICLASS_SETNO_DEFINED 1 +#define XED_ICLASS_SETNP_DEFINED 1 +#define XED_ICLASS_SETNS_DEFINED 1 +#define XED_ICLASS_SETNZ_DEFINED 1 +#define XED_ICLASS_SETO_DEFINED 1 +#define XED_ICLASS_SETP_DEFINED 1 +#define XED_ICLASS_SETS_DEFINED 1 +#define XED_ICLASS_SETSSBSY_DEFINED 1 +#define XED_ICLASS_SETZ_DEFINED 1 +#define XED_ICLASS_SFENCE_DEFINED 1 +#define XED_ICLASS_SGDT_DEFINED 1 +#define XED_ICLASS_SHA1MSG1_DEFINED 1 +#define XED_ICLASS_SHA1MSG2_DEFINED 1 +#define XED_ICLASS_SHA1NEXTE_DEFINED 1 +#define XED_ICLASS_SHA1RNDS4_DEFINED 1 +#define XED_ICLASS_SHA256MSG1_DEFINED 1 +#define XED_ICLASS_SHA256MSG2_DEFINED 1 +#define XED_ICLASS_SHA256RNDS2_DEFINED 1 +#define XED_ICLASS_SHL_DEFINED 1 +#define XED_ICLASS_SHLD_DEFINED 1 +#define XED_ICLASS_SHLX_DEFINED 1 +#define XED_ICLASS_SHR_DEFINED 1 +#define XED_ICLASS_SHRD_DEFINED 1 +#define XED_ICLASS_SHRX_DEFINED 1 +#define XED_ICLASS_SHUFPD_DEFINED 1 +#define XED_ICLASS_SHUFPS_DEFINED 1 +#define XED_ICLASS_SIDT_DEFINED 1 +#define XED_ICLASS_SKINIT_DEFINED 1 +#define XED_ICLASS_SLDT_DEFINED 1 +#define XED_ICLASS_SLWPCB_DEFINED 1 +#define XED_ICLASS_SMSW_DEFINED 1 +#define XED_ICLASS_SQRTPD_DEFINED 1 +#define XED_ICLASS_SQRTPS_DEFINED 1 +#define XED_ICLASS_SQRTSD_DEFINED 1 +#define XED_ICLASS_SQRTSS_DEFINED 1 +#define XED_ICLASS_STAC_DEFINED 1 +#define XED_ICLASS_STC_DEFINED 1 +#define XED_ICLASS_STD_DEFINED 1 +#define XED_ICLASS_STGI_DEFINED 1 +#define XED_ICLASS_STI_DEFINED 1 +#define XED_ICLASS_STMXCSR_DEFINED 1 +#define XED_ICLASS_STOSB_DEFINED 1 +#define XED_ICLASS_STOSD_DEFINED 1 +#define XED_ICLASS_STOSQ_DEFINED 1 +#define XED_ICLASS_STOSW_DEFINED 1 +#define XED_ICLASS_STR_DEFINED 1 +#define XED_ICLASS_STTILECFG_DEFINED 1 +#define XED_ICLASS_STUI_DEFINED 1 +#define XED_ICLASS_SUB_DEFINED 1 +#define XED_ICLASS_SUBPD_DEFINED 1 +#define XED_ICLASS_SUBPS_DEFINED 1 +#define XED_ICLASS_SUBSD_DEFINED 1 +#define XED_ICLASS_SUBSS_DEFINED 1 +#define XED_ICLASS_SUB_LOCK_DEFINED 1 +#define XED_ICLASS_SWAPGS_DEFINED 1 +#define XED_ICLASS_SYSCALL_DEFINED 1 +#define XED_ICLASS_SYSCALL_AMD_DEFINED 1 +#define XED_ICLASS_SYSENTER_DEFINED 1 +#define XED_ICLASS_SYSEXIT_DEFINED 1 +#define XED_ICLASS_SYSRET_DEFINED 1 +#define XED_ICLASS_SYSRET64_DEFINED 1 +#define XED_ICLASS_SYSRET_AMD_DEFINED 1 +#define XED_ICLASS_T1MSKC_DEFINED 1 +#define XED_ICLASS_TDCALL_DEFINED 1 +#define XED_ICLASS_TDPBF16PS_DEFINED 1 +#define XED_ICLASS_TDPBSSD_DEFINED 1 +#define XED_ICLASS_TDPBSUD_DEFINED 1 +#define XED_ICLASS_TDPBUSD_DEFINED 1 +#define XED_ICLASS_TDPBUUD_DEFINED 1 +#define XED_ICLASS_TEST_DEFINED 1 +#define XED_ICLASS_TESTUI_DEFINED 1 +#define XED_ICLASS_TILELOADD_DEFINED 1 +#define XED_ICLASS_TILELOADDT1_DEFINED 1 +#define XED_ICLASS_TILERELEASE_DEFINED 1 +#define XED_ICLASS_TILESTORED_DEFINED 1 +#define XED_ICLASS_TILEZERO_DEFINED 1 +#define XED_ICLASS_TLBSYNC_DEFINED 1 +#define XED_ICLASS_TPAUSE_DEFINED 1 +#define XED_ICLASS_TZCNT_DEFINED 1 +#define XED_ICLASS_TZMSK_DEFINED 1 +#define XED_ICLASS_UCOMISD_DEFINED 1 +#define XED_ICLASS_UCOMISS_DEFINED 1 +#define XED_ICLASS_UD0_DEFINED 1 +#define XED_ICLASS_UD1_DEFINED 1 +#define XED_ICLASS_UD2_DEFINED 1 +#define XED_ICLASS_UIRET_DEFINED 1 +#define XED_ICLASS_UMONITOR_DEFINED 1 +#define XED_ICLASS_UMWAIT_DEFINED 1 +#define XED_ICLASS_UNPCKHPD_DEFINED 1 +#define XED_ICLASS_UNPCKHPS_DEFINED 1 +#define XED_ICLASS_UNPCKLPD_DEFINED 1 +#define XED_ICLASS_UNPCKLPS_DEFINED 1 +#define XED_ICLASS_V4FMADDPS_DEFINED 1 +#define XED_ICLASS_V4FMADDSS_DEFINED 1 +#define XED_ICLASS_V4FNMADDPS_DEFINED 1 +#define XED_ICLASS_V4FNMADDSS_DEFINED 1 +#define XED_ICLASS_VADDPD_DEFINED 1 +#define XED_ICLASS_VADDPH_DEFINED 1 +#define XED_ICLASS_VADDPS_DEFINED 1 +#define XED_ICLASS_VADDSD_DEFINED 1 +#define XED_ICLASS_VADDSH_DEFINED 1 +#define XED_ICLASS_VADDSS_DEFINED 1 +#define XED_ICLASS_VADDSUBPD_DEFINED 1 +#define XED_ICLASS_VADDSUBPS_DEFINED 1 +#define XED_ICLASS_VAESDEC_DEFINED 1 +#define XED_ICLASS_VAESDECLAST_DEFINED 1 +#define XED_ICLASS_VAESENC_DEFINED 1 +#define XED_ICLASS_VAESENCLAST_DEFINED 1 +#define XED_ICLASS_VAESIMC_DEFINED 1 +#define XED_ICLASS_VAESKEYGENASSIST_DEFINED 1 +#define XED_ICLASS_VALIGND_DEFINED 1 +#define XED_ICLASS_VALIGNQ_DEFINED 1 +#define XED_ICLASS_VANDNPD_DEFINED 1 +#define XED_ICLASS_VANDNPS_DEFINED 1 +#define XED_ICLASS_VANDPD_DEFINED 1 +#define XED_ICLASS_VANDPS_DEFINED 1 +#define XED_ICLASS_VBLENDMPD_DEFINED 1 +#define XED_ICLASS_VBLENDMPS_DEFINED 1 +#define XED_ICLASS_VBLENDPD_DEFINED 1 +#define XED_ICLASS_VBLENDPS_DEFINED 1 +#define XED_ICLASS_VBLENDVPD_DEFINED 1 +#define XED_ICLASS_VBLENDVPS_DEFINED 1 +#define XED_ICLASS_VBROADCASTF128_DEFINED 1 +#define XED_ICLASS_VBROADCASTF32X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTF32X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTF32X8_DEFINED 1 +#define XED_ICLASS_VBROADCASTF64X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTF64X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTI128_DEFINED 1 +#define XED_ICLASS_VBROADCASTI32X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTI32X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTI32X8_DEFINED 1 +#define XED_ICLASS_VBROADCASTI64X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTI64X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTSD_DEFINED 1 +#define XED_ICLASS_VBROADCASTSS_DEFINED 1 +#define XED_ICLASS_VCMPPD_DEFINED 1 +#define XED_ICLASS_VCMPPH_DEFINED 1 +#define XED_ICLASS_VCMPPS_DEFINED 1 +#define XED_ICLASS_VCMPSD_DEFINED 1 +#define XED_ICLASS_VCMPSH_DEFINED 1 +#define XED_ICLASS_VCMPSS_DEFINED 1 +#define XED_ICLASS_VCOMISD_DEFINED 1 +#define XED_ICLASS_VCOMISH_DEFINED 1 +#define XED_ICLASS_VCOMISS_DEFINED 1 +#define XED_ICLASS_VCOMPRESSPD_DEFINED 1 +#define XED_ICLASS_VCOMPRESSPS_DEFINED 1 +#define XED_ICLASS_VCVTDQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTDQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTDQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTNE2PS2BF16_DEFINED 1 +#define XED_ICLASS_VCVTNEPS2BF16_DEFINED 1 +#define XED_ICLASS_VCVTPD2DQ_DEFINED 1 +#define XED_ICLASS_VCVTPD2PH_DEFINED 1 +#define XED_ICLASS_VCVTPD2PS_DEFINED 1 +#define XED_ICLASS_VCVTPD2QQ_DEFINED 1 +#define XED_ICLASS_VCVTPD2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTPD2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2DQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2PD_DEFINED 1 +#define XED_ICLASS_VCVTPH2PS_DEFINED 1 +#define XED_ICLASS_VCVTPH2PSX_DEFINED 1 +#define XED_ICLASS_VCVTPH2QQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2UW_DEFINED 1 +#define XED_ICLASS_VCVTPH2W_DEFINED 1 +#define XED_ICLASS_VCVTPS2DQ_DEFINED 1 +#define XED_ICLASS_VCVTPS2PD_DEFINED 1 +#define XED_ICLASS_VCVTPS2PH_DEFINED 1 +#define XED_ICLASS_VCVTPS2PHX_DEFINED 1 +#define XED_ICLASS_VCVTPS2QQ_DEFINED 1 +#define XED_ICLASS_VCVTPS2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTPS2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTQQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTQQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTQQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTSD2SH_DEFINED 1 +#define XED_ICLASS_VCVTSD2SI_DEFINED 1 +#define XED_ICLASS_VCVTSD2SS_DEFINED 1 +#define XED_ICLASS_VCVTSD2USI_DEFINED 1 +#define XED_ICLASS_VCVTSH2SD_DEFINED 1 +#define XED_ICLASS_VCVTSH2SI_DEFINED 1 +#define XED_ICLASS_VCVTSH2SS_DEFINED 1 +#define XED_ICLASS_VCVTSH2USI_DEFINED 1 +#define XED_ICLASS_VCVTSI2SD_DEFINED 1 +#define XED_ICLASS_VCVTSI2SH_DEFINED 1 +#define XED_ICLASS_VCVTSI2SS_DEFINED 1 +#define XED_ICLASS_VCVTSS2SD_DEFINED 1 +#define XED_ICLASS_VCVTSS2SH_DEFINED 1 +#define XED_ICLASS_VCVTSS2SI_DEFINED 1 +#define XED_ICLASS_VCVTSS2USI_DEFINED 1 +#define XED_ICLASS_VCVTTPD2DQ_DEFINED 1 +#define XED_ICLASS_VCVTTPD2QQ_DEFINED 1 +#define XED_ICLASS_VCVTTPD2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTTPD2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2DQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2QQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2UW_DEFINED 1 +#define XED_ICLASS_VCVTTPH2W_DEFINED 1 +#define XED_ICLASS_VCVTTPS2DQ_DEFINED 1 +#define XED_ICLASS_VCVTTPS2QQ_DEFINED 1 +#define XED_ICLASS_VCVTTPS2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTTPS2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTTSD2SI_DEFINED 1 +#define XED_ICLASS_VCVTTSD2USI_DEFINED 1 +#define XED_ICLASS_VCVTTSH2SI_DEFINED 1 +#define XED_ICLASS_VCVTTSH2USI_DEFINED 1 +#define XED_ICLASS_VCVTTSS2SI_DEFINED 1 +#define XED_ICLASS_VCVTTSS2USI_DEFINED 1 +#define XED_ICLASS_VCVTUDQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTUDQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTUDQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTUQQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTUQQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTUQQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTUSI2SD_DEFINED 1 +#define XED_ICLASS_VCVTUSI2SH_DEFINED 1 +#define XED_ICLASS_VCVTUSI2SS_DEFINED 1 +#define XED_ICLASS_VCVTUW2PH_DEFINED 1 +#define XED_ICLASS_VCVTW2PH_DEFINED 1 +#define XED_ICLASS_VDBPSADBW_DEFINED 1 +#define XED_ICLASS_VDIVPD_DEFINED 1 +#define XED_ICLASS_VDIVPH_DEFINED 1 +#define XED_ICLASS_VDIVPS_DEFINED 1 +#define XED_ICLASS_VDIVSD_DEFINED 1 +#define XED_ICLASS_VDIVSH_DEFINED 1 +#define XED_ICLASS_VDIVSS_DEFINED 1 +#define XED_ICLASS_VDPBF16PS_DEFINED 1 +#define XED_ICLASS_VDPPD_DEFINED 1 +#define XED_ICLASS_VDPPS_DEFINED 1 +#define XED_ICLASS_VERR_DEFINED 1 +#define XED_ICLASS_VERW_DEFINED 1 +#define XED_ICLASS_VEXP2PD_DEFINED 1 +#define XED_ICLASS_VEXP2PS_DEFINED 1 +#define XED_ICLASS_VEXPANDPD_DEFINED 1 +#define XED_ICLASS_VEXPANDPS_DEFINED 1 +#define XED_ICLASS_VEXTRACTF128_DEFINED 1 +#define XED_ICLASS_VEXTRACTF32X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTF32X8_DEFINED 1 +#define XED_ICLASS_VEXTRACTF64X2_DEFINED 1 +#define XED_ICLASS_VEXTRACTF64X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTI128_DEFINED 1 +#define XED_ICLASS_VEXTRACTI32X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTI32X8_DEFINED 1 +#define XED_ICLASS_VEXTRACTI64X2_DEFINED 1 +#define XED_ICLASS_VEXTRACTI64X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTPS_DEFINED 1 +#define XED_ICLASS_VFCMADDCPH_DEFINED 1 +#define XED_ICLASS_VFCMADDCSH_DEFINED 1 +#define XED_ICLASS_VFCMULCPH_DEFINED 1 +#define XED_ICLASS_VFCMULCSH_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMPD_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMPS_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMSD_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMSS_DEFINED 1 +#define XED_ICLASS_VFMADD132PD_DEFINED 1 +#define XED_ICLASS_VFMADD132PH_DEFINED 1 +#define XED_ICLASS_VFMADD132PS_DEFINED 1 +#define XED_ICLASS_VFMADD132SD_DEFINED 1 +#define XED_ICLASS_VFMADD132SH_DEFINED 1 +#define XED_ICLASS_VFMADD132SS_DEFINED 1 +#define XED_ICLASS_VFMADD213PD_DEFINED 1 +#define XED_ICLASS_VFMADD213PH_DEFINED 1 +#define XED_ICLASS_VFMADD213PS_DEFINED 1 +#define XED_ICLASS_VFMADD213SD_DEFINED 1 +#define XED_ICLASS_VFMADD213SH_DEFINED 1 +#define XED_ICLASS_VFMADD213SS_DEFINED 1 +#define XED_ICLASS_VFMADD231PD_DEFINED 1 +#define XED_ICLASS_VFMADD231PH_DEFINED 1 +#define XED_ICLASS_VFMADD231PS_DEFINED 1 +#define XED_ICLASS_VFMADD231SD_DEFINED 1 +#define XED_ICLASS_VFMADD231SH_DEFINED 1 +#define XED_ICLASS_VFMADD231SS_DEFINED 1 +#define XED_ICLASS_VFMADDCPH_DEFINED 1 +#define XED_ICLASS_VFMADDCSH_DEFINED 1 +#define XED_ICLASS_VFMADDPD_DEFINED 1 +#define XED_ICLASS_VFMADDPS_DEFINED 1 +#define XED_ICLASS_VFMADDSD_DEFINED 1 +#define XED_ICLASS_VFMADDSS_DEFINED 1 +#define XED_ICLASS_VFMADDSUB132PD_DEFINED 1 +#define XED_ICLASS_VFMADDSUB132PH_DEFINED 1 +#define XED_ICLASS_VFMADDSUB132PS_DEFINED 1 +#define XED_ICLASS_VFMADDSUB213PD_DEFINED 1 +#define XED_ICLASS_VFMADDSUB213PH_DEFINED 1 +#define XED_ICLASS_VFMADDSUB213PS_DEFINED 1 +#define XED_ICLASS_VFMADDSUB231PD_DEFINED 1 +#define XED_ICLASS_VFMADDSUB231PH_DEFINED 1 +#define XED_ICLASS_VFMADDSUB231PS_DEFINED 1 +#define XED_ICLASS_VFMADDSUBPD_DEFINED 1 +#define XED_ICLASS_VFMADDSUBPS_DEFINED 1 +#define XED_ICLASS_VFMSUB132PD_DEFINED 1 +#define XED_ICLASS_VFMSUB132PH_DEFINED 1 +#define XED_ICLASS_VFMSUB132PS_DEFINED 1 +#define XED_ICLASS_VFMSUB132SD_DEFINED 1 +#define XED_ICLASS_VFMSUB132SH_DEFINED 1 +#define XED_ICLASS_VFMSUB132SS_DEFINED 1 +#define XED_ICLASS_VFMSUB213PD_DEFINED 1 +#define XED_ICLASS_VFMSUB213PH_DEFINED 1 +#define XED_ICLASS_VFMSUB213PS_DEFINED 1 +#define XED_ICLASS_VFMSUB213SD_DEFINED 1 +#define XED_ICLASS_VFMSUB213SH_DEFINED 1 +#define XED_ICLASS_VFMSUB213SS_DEFINED 1 +#define XED_ICLASS_VFMSUB231PD_DEFINED 1 +#define XED_ICLASS_VFMSUB231PH_DEFINED 1 +#define XED_ICLASS_VFMSUB231PS_DEFINED 1 +#define XED_ICLASS_VFMSUB231SD_DEFINED 1 +#define XED_ICLASS_VFMSUB231SH_DEFINED 1 +#define XED_ICLASS_VFMSUB231SS_DEFINED 1 +#define XED_ICLASS_VFMSUBADD132PD_DEFINED 1 +#define XED_ICLASS_VFMSUBADD132PH_DEFINED 1 +#define XED_ICLASS_VFMSUBADD132PS_DEFINED 1 +#define XED_ICLASS_VFMSUBADD213PD_DEFINED 1 +#define XED_ICLASS_VFMSUBADD213PH_DEFINED 1 +#define XED_ICLASS_VFMSUBADD213PS_DEFINED 1 +#define XED_ICLASS_VFMSUBADD231PD_DEFINED 1 +#define XED_ICLASS_VFMSUBADD231PH_DEFINED 1 +#define XED_ICLASS_VFMSUBADD231PS_DEFINED 1 +#define XED_ICLASS_VFMSUBADDPD_DEFINED 1 +#define XED_ICLASS_VFMSUBADDPS_DEFINED 1 +#define XED_ICLASS_VFMSUBPD_DEFINED 1 +#define XED_ICLASS_VFMSUBPS_DEFINED 1 +#define XED_ICLASS_VFMSUBSD_DEFINED 1 +#define XED_ICLASS_VFMSUBSS_DEFINED 1 +#define XED_ICLASS_VFMULCPH_DEFINED 1 +#define XED_ICLASS_VFMULCSH_DEFINED 1 +#define XED_ICLASS_VFNMADD132PD_DEFINED 1 +#define XED_ICLASS_VFNMADD132PH_DEFINED 1 +#define XED_ICLASS_VFNMADD132PS_DEFINED 1 +#define XED_ICLASS_VFNMADD132SD_DEFINED 1 +#define XED_ICLASS_VFNMADD132SH_DEFINED 1 +#define XED_ICLASS_VFNMADD132SS_DEFINED 1 +#define XED_ICLASS_VFNMADD213PD_DEFINED 1 +#define XED_ICLASS_VFNMADD213PH_DEFINED 1 +#define XED_ICLASS_VFNMADD213PS_DEFINED 1 +#define XED_ICLASS_VFNMADD213SD_DEFINED 1 +#define XED_ICLASS_VFNMADD213SH_DEFINED 1 +#define XED_ICLASS_VFNMADD213SS_DEFINED 1 +#define XED_ICLASS_VFNMADD231PD_DEFINED 1 +#define XED_ICLASS_VFNMADD231PH_DEFINED 1 +#define XED_ICLASS_VFNMADD231PS_DEFINED 1 +#define XED_ICLASS_VFNMADD231SD_DEFINED 1 +#define XED_ICLASS_VFNMADD231SH_DEFINED 1 +#define XED_ICLASS_VFNMADD231SS_DEFINED 1 +#define XED_ICLASS_VFNMADDPD_DEFINED 1 +#define XED_ICLASS_VFNMADDPS_DEFINED 1 +#define XED_ICLASS_VFNMADDSD_DEFINED 1 +#define XED_ICLASS_VFNMADDSS_DEFINED 1 +#define XED_ICLASS_VFNMSUB132PD_DEFINED 1 +#define XED_ICLASS_VFNMSUB132PH_DEFINED 1 +#define XED_ICLASS_VFNMSUB132PS_DEFINED 1 +#define XED_ICLASS_VFNMSUB132SD_DEFINED 1 +#define XED_ICLASS_VFNMSUB132SH_DEFINED 1 +#define XED_ICLASS_VFNMSUB132SS_DEFINED 1 +#define XED_ICLASS_VFNMSUB213PD_DEFINED 1 +#define XED_ICLASS_VFNMSUB213PH_DEFINED 1 +#define XED_ICLASS_VFNMSUB213PS_DEFINED 1 +#define XED_ICLASS_VFNMSUB213SD_DEFINED 1 +#define XED_ICLASS_VFNMSUB213SH_DEFINED 1 +#define XED_ICLASS_VFNMSUB213SS_DEFINED 1 +#define XED_ICLASS_VFNMSUB231PD_DEFINED 1 +#define XED_ICLASS_VFNMSUB231PH_DEFINED 1 +#define XED_ICLASS_VFNMSUB231PS_DEFINED 1 +#define XED_ICLASS_VFNMSUB231SD_DEFINED 1 +#define XED_ICLASS_VFNMSUB231SH_DEFINED 1 +#define XED_ICLASS_VFNMSUB231SS_DEFINED 1 +#define XED_ICLASS_VFNMSUBPD_DEFINED 1 +#define XED_ICLASS_VFNMSUBPS_DEFINED 1 +#define XED_ICLASS_VFNMSUBSD_DEFINED 1 +#define XED_ICLASS_VFNMSUBSS_DEFINED 1 +#define XED_ICLASS_VFPCLASSPD_DEFINED 1 +#define XED_ICLASS_VFPCLASSPH_DEFINED 1 +#define XED_ICLASS_VFPCLASSPS_DEFINED 1 +#define XED_ICLASS_VFPCLASSSD_DEFINED 1 +#define XED_ICLASS_VFPCLASSSH_DEFINED 1 +#define XED_ICLASS_VFPCLASSSS_DEFINED 1 +#define XED_ICLASS_VFRCZPD_DEFINED 1 +#define XED_ICLASS_VFRCZPS_DEFINED 1 +#define XED_ICLASS_VFRCZSD_DEFINED 1 +#define XED_ICLASS_VFRCZSS_DEFINED 1 +#define XED_ICLASS_VGATHERDPD_DEFINED 1 +#define XED_ICLASS_VGATHERDPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF0DPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF0DPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF0QPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF0QPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF1DPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF1DPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF1QPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF1QPS_DEFINED 1 +#define XED_ICLASS_VGATHERQPD_DEFINED 1 +#define XED_ICLASS_VGATHERQPS_DEFINED 1 +#define XED_ICLASS_VGETEXPPD_DEFINED 1 +#define XED_ICLASS_VGETEXPPH_DEFINED 1 +#define XED_ICLASS_VGETEXPPS_DEFINED 1 +#define XED_ICLASS_VGETEXPSD_DEFINED 1 +#define XED_ICLASS_VGETEXPSH_DEFINED 1 +#define XED_ICLASS_VGETEXPSS_DEFINED 1 +#define XED_ICLASS_VGETMANTPD_DEFINED 1 +#define XED_ICLASS_VGETMANTPH_DEFINED 1 +#define XED_ICLASS_VGETMANTPS_DEFINED 1 +#define XED_ICLASS_VGETMANTSD_DEFINED 1 +#define XED_ICLASS_VGETMANTSH_DEFINED 1 +#define XED_ICLASS_VGETMANTSS_DEFINED 1 +#define XED_ICLASS_VGF2P8AFFINEINVQB_DEFINED 1 +#define XED_ICLASS_VGF2P8AFFINEQB_DEFINED 1 +#define XED_ICLASS_VGF2P8MULB_DEFINED 1 +#define XED_ICLASS_VHADDPD_DEFINED 1 +#define XED_ICLASS_VHADDPS_DEFINED 1 +#define XED_ICLASS_VHSUBPD_DEFINED 1 +#define XED_ICLASS_VHSUBPS_DEFINED 1 +#define XED_ICLASS_VINSERTF128_DEFINED 1 +#define XED_ICLASS_VINSERTF32X4_DEFINED 1 +#define XED_ICLASS_VINSERTF32X8_DEFINED 1 +#define XED_ICLASS_VINSERTF64X2_DEFINED 1 +#define XED_ICLASS_VINSERTF64X4_DEFINED 1 +#define XED_ICLASS_VINSERTI128_DEFINED 1 +#define XED_ICLASS_VINSERTI32X4_DEFINED 1 +#define XED_ICLASS_VINSERTI32X8_DEFINED 1 +#define XED_ICLASS_VINSERTI64X2_DEFINED 1 +#define XED_ICLASS_VINSERTI64X4_DEFINED 1 +#define XED_ICLASS_VINSERTPS_DEFINED 1 +#define XED_ICLASS_VLDDQU_DEFINED 1 +#define XED_ICLASS_VLDMXCSR_DEFINED 1 +#define XED_ICLASS_VMASKMOVDQU_DEFINED 1 +#define XED_ICLASS_VMASKMOVPD_DEFINED 1 +#define XED_ICLASS_VMASKMOVPS_DEFINED 1 +#define XED_ICLASS_VMAXPD_DEFINED 1 +#define XED_ICLASS_VMAXPH_DEFINED 1 +#define XED_ICLASS_VMAXPS_DEFINED 1 +#define XED_ICLASS_VMAXSD_DEFINED 1 +#define XED_ICLASS_VMAXSH_DEFINED 1 +#define XED_ICLASS_VMAXSS_DEFINED 1 +#define XED_ICLASS_VMCALL_DEFINED 1 +#define XED_ICLASS_VMCLEAR_DEFINED 1 +#define XED_ICLASS_VMFUNC_DEFINED 1 +#define XED_ICLASS_VMINPD_DEFINED 1 +#define XED_ICLASS_VMINPH_DEFINED 1 +#define XED_ICLASS_VMINPS_DEFINED 1 +#define XED_ICLASS_VMINSD_DEFINED 1 +#define XED_ICLASS_VMINSH_DEFINED 1 +#define XED_ICLASS_VMINSS_DEFINED 1 +#define XED_ICLASS_VMLAUNCH_DEFINED 1 +#define XED_ICLASS_VMLOAD_DEFINED 1 +#define XED_ICLASS_VMMCALL_DEFINED 1 +#define XED_ICLASS_VMOVAPD_DEFINED 1 +#define XED_ICLASS_VMOVAPS_DEFINED 1 +#define XED_ICLASS_VMOVD_DEFINED 1 +#define XED_ICLASS_VMOVDDUP_DEFINED 1 +#define XED_ICLASS_VMOVDQA_DEFINED 1 +#define XED_ICLASS_VMOVDQA32_DEFINED 1 +#define XED_ICLASS_VMOVDQA64_DEFINED 1 +#define XED_ICLASS_VMOVDQU_DEFINED 1 +#define XED_ICLASS_VMOVDQU16_DEFINED 1 +#define XED_ICLASS_VMOVDQU32_DEFINED 1 +#define XED_ICLASS_VMOVDQU64_DEFINED 1 +#define XED_ICLASS_VMOVDQU8_DEFINED 1 +#define XED_ICLASS_VMOVHLPS_DEFINED 1 +#define XED_ICLASS_VMOVHPD_DEFINED 1 +#define XED_ICLASS_VMOVHPS_DEFINED 1 +#define XED_ICLASS_VMOVLHPS_DEFINED 1 +#define XED_ICLASS_VMOVLPD_DEFINED 1 +#define XED_ICLASS_VMOVLPS_DEFINED 1 +#define XED_ICLASS_VMOVMSKPD_DEFINED 1 +#define XED_ICLASS_VMOVMSKPS_DEFINED 1 +#define XED_ICLASS_VMOVNTDQ_DEFINED 1 +#define XED_ICLASS_VMOVNTDQA_DEFINED 1 +#define XED_ICLASS_VMOVNTPD_DEFINED 1 +#define XED_ICLASS_VMOVNTPS_DEFINED 1 +#define XED_ICLASS_VMOVQ_DEFINED 1 +#define XED_ICLASS_VMOVSD_DEFINED 1 +#define XED_ICLASS_VMOVSH_DEFINED 1 +#define XED_ICLASS_VMOVSHDUP_DEFINED 1 +#define XED_ICLASS_VMOVSLDUP_DEFINED 1 +#define XED_ICLASS_VMOVSS_DEFINED 1 +#define XED_ICLASS_VMOVUPD_DEFINED 1 +#define XED_ICLASS_VMOVUPS_DEFINED 1 +#define XED_ICLASS_VMOVW_DEFINED 1 +#define XED_ICLASS_VMPSADBW_DEFINED 1 +#define XED_ICLASS_VMPTRLD_DEFINED 1 +#define XED_ICLASS_VMPTRST_DEFINED 1 +#define XED_ICLASS_VMREAD_DEFINED 1 +#define XED_ICLASS_VMRESUME_DEFINED 1 +#define XED_ICLASS_VMRUN_DEFINED 1 +#define XED_ICLASS_VMSAVE_DEFINED 1 +#define XED_ICLASS_VMULPD_DEFINED 1 +#define XED_ICLASS_VMULPH_DEFINED 1 +#define XED_ICLASS_VMULPS_DEFINED 1 +#define XED_ICLASS_VMULSD_DEFINED 1 +#define XED_ICLASS_VMULSH_DEFINED 1 +#define XED_ICLASS_VMULSS_DEFINED 1 +#define XED_ICLASS_VMWRITE_DEFINED 1 +#define XED_ICLASS_VMXOFF_DEFINED 1 +#define XED_ICLASS_VMXON_DEFINED 1 +#define XED_ICLASS_VORPD_DEFINED 1 +#define XED_ICLASS_VORPS_DEFINED 1 +#define XED_ICLASS_VP2INTERSECTD_DEFINED 1 +#define XED_ICLASS_VP2INTERSECTQ_DEFINED 1 +#define XED_ICLASS_VP4DPWSSD_DEFINED 1 +#define XED_ICLASS_VP4DPWSSDS_DEFINED 1 +#define XED_ICLASS_VPABSB_DEFINED 1 +#define XED_ICLASS_VPABSD_DEFINED 1 +#define XED_ICLASS_VPABSQ_DEFINED 1 +#define XED_ICLASS_VPABSW_DEFINED 1 +#define XED_ICLASS_VPACKSSDW_DEFINED 1 +#define XED_ICLASS_VPACKSSWB_DEFINED 1 +#define XED_ICLASS_VPACKUSDW_DEFINED 1 +#define XED_ICLASS_VPACKUSWB_DEFINED 1 +#define XED_ICLASS_VPADDB_DEFINED 1 +#define XED_ICLASS_VPADDD_DEFINED 1 +#define XED_ICLASS_VPADDQ_DEFINED 1 +#define XED_ICLASS_VPADDSB_DEFINED 1 +#define XED_ICLASS_VPADDSW_DEFINED 1 +#define XED_ICLASS_VPADDUSB_DEFINED 1 +#define XED_ICLASS_VPADDUSW_DEFINED 1 +#define XED_ICLASS_VPADDW_DEFINED 1 +#define XED_ICLASS_VPALIGNR_DEFINED 1 +#define XED_ICLASS_VPAND_DEFINED 1 +#define XED_ICLASS_VPANDD_DEFINED 1 +#define XED_ICLASS_VPANDN_DEFINED 1 +#define XED_ICLASS_VPANDND_DEFINED 1 +#define XED_ICLASS_VPANDNQ_DEFINED 1 +#define XED_ICLASS_VPANDQ_DEFINED 1 +#define XED_ICLASS_VPAVGB_DEFINED 1 +#define XED_ICLASS_VPAVGW_DEFINED 1 +#define XED_ICLASS_VPBLENDD_DEFINED 1 +#define XED_ICLASS_VPBLENDMB_DEFINED 1 +#define XED_ICLASS_VPBLENDMD_DEFINED 1 +#define XED_ICLASS_VPBLENDMQ_DEFINED 1 +#define XED_ICLASS_VPBLENDMW_DEFINED 1 +#define XED_ICLASS_VPBLENDVB_DEFINED 1 +#define XED_ICLASS_VPBLENDW_DEFINED 1 +#define XED_ICLASS_VPBROADCASTB_DEFINED 1 +#define XED_ICLASS_VPBROADCASTD_DEFINED 1 +#define XED_ICLASS_VPBROADCASTMB2Q_DEFINED 1 +#define XED_ICLASS_VPBROADCASTMW2D_DEFINED 1 +#define XED_ICLASS_VPBROADCASTQ_DEFINED 1 +#define XED_ICLASS_VPBROADCASTW_DEFINED 1 +#define XED_ICLASS_VPCLMULQDQ_DEFINED 1 +#define XED_ICLASS_VPCMOV_DEFINED 1 +#define XED_ICLASS_VPCMPB_DEFINED 1 +#define XED_ICLASS_VPCMPD_DEFINED 1 +#define XED_ICLASS_VPCMPEQB_DEFINED 1 +#define XED_ICLASS_VPCMPEQD_DEFINED 1 +#define XED_ICLASS_VPCMPEQQ_DEFINED 1 +#define XED_ICLASS_VPCMPEQW_DEFINED 1 +#define XED_ICLASS_VPCMPESTRI_DEFINED 1 +#define XED_ICLASS_VPCMPESTRI64_DEFINED 1 +#define XED_ICLASS_VPCMPESTRM_DEFINED 1 +#define XED_ICLASS_VPCMPESTRM64_DEFINED 1 +#define XED_ICLASS_VPCMPGTB_DEFINED 1 +#define XED_ICLASS_VPCMPGTD_DEFINED 1 +#define XED_ICLASS_VPCMPGTQ_DEFINED 1 +#define XED_ICLASS_VPCMPGTW_DEFINED 1 +#define XED_ICLASS_VPCMPISTRI_DEFINED 1 +#define XED_ICLASS_VPCMPISTRI64_DEFINED 1 +#define XED_ICLASS_VPCMPISTRM_DEFINED 1 +#define XED_ICLASS_VPCMPQ_DEFINED 1 +#define XED_ICLASS_VPCMPUB_DEFINED 1 +#define XED_ICLASS_VPCMPUD_DEFINED 1 +#define XED_ICLASS_VPCMPUQ_DEFINED 1 +#define XED_ICLASS_VPCMPUW_DEFINED 1 +#define XED_ICLASS_VPCMPW_DEFINED 1 +#define XED_ICLASS_VPCOMB_DEFINED 1 +#define XED_ICLASS_VPCOMD_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSB_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSD_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSQ_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSW_DEFINED 1 +#define XED_ICLASS_VPCOMQ_DEFINED 1 +#define XED_ICLASS_VPCOMUB_DEFINED 1 +#define XED_ICLASS_VPCOMUD_DEFINED 1 +#define XED_ICLASS_VPCOMUQ_DEFINED 1 +#define XED_ICLASS_VPCOMUW_DEFINED 1 +#define XED_ICLASS_VPCOMW_DEFINED 1 +#define XED_ICLASS_VPCONFLICTD_DEFINED 1 +#define XED_ICLASS_VPCONFLICTQ_DEFINED 1 +#define XED_ICLASS_VPDPBUSD_DEFINED 1 +#define XED_ICLASS_VPDPBUSDS_DEFINED 1 +#define XED_ICLASS_VPDPWSSD_DEFINED 1 +#define XED_ICLASS_VPDPWSSDS_DEFINED 1 +#define XED_ICLASS_VPERM2F128_DEFINED 1 +#define XED_ICLASS_VPERM2I128_DEFINED 1 +#define XED_ICLASS_VPERMB_DEFINED 1 +#define XED_ICLASS_VPERMD_DEFINED 1 +#define XED_ICLASS_VPERMI2B_DEFINED 1 +#define XED_ICLASS_VPERMI2D_DEFINED 1 +#define XED_ICLASS_VPERMI2PD_DEFINED 1 +#define XED_ICLASS_VPERMI2PS_DEFINED 1 +#define XED_ICLASS_VPERMI2Q_DEFINED 1 +#define XED_ICLASS_VPERMI2W_DEFINED 1 +#define XED_ICLASS_VPERMIL2PD_DEFINED 1 +#define XED_ICLASS_VPERMIL2PS_DEFINED 1 +#define XED_ICLASS_VPERMILPD_DEFINED 1 +#define XED_ICLASS_VPERMILPS_DEFINED 1 +#define XED_ICLASS_VPERMPD_DEFINED 1 +#define XED_ICLASS_VPERMPS_DEFINED 1 +#define XED_ICLASS_VPERMQ_DEFINED 1 +#define XED_ICLASS_VPERMT2B_DEFINED 1 +#define XED_ICLASS_VPERMT2D_DEFINED 1 +#define XED_ICLASS_VPERMT2PD_DEFINED 1 +#define XED_ICLASS_VPERMT2PS_DEFINED 1 +#define XED_ICLASS_VPERMT2Q_DEFINED 1 +#define XED_ICLASS_VPERMT2W_DEFINED 1 +#define XED_ICLASS_VPERMW_DEFINED 1 +#define XED_ICLASS_VPEXPANDB_DEFINED 1 +#define XED_ICLASS_VPEXPANDD_DEFINED 1 +#define XED_ICLASS_VPEXPANDQ_DEFINED 1 +#define XED_ICLASS_VPEXPANDW_DEFINED 1 +#define XED_ICLASS_VPEXTRB_DEFINED 1 +#define XED_ICLASS_VPEXTRD_DEFINED 1 +#define XED_ICLASS_VPEXTRQ_DEFINED 1 +#define XED_ICLASS_VPEXTRW_DEFINED 1 +#define XED_ICLASS_VPEXTRW_C5_DEFINED 1 +#define XED_ICLASS_VPGATHERDD_DEFINED 1 +#define XED_ICLASS_VPGATHERDQ_DEFINED 1 +#define XED_ICLASS_VPGATHERQD_DEFINED 1 +#define XED_ICLASS_VPGATHERQQ_DEFINED 1 +#define XED_ICLASS_VPHADDBD_DEFINED 1 +#define XED_ICLASS_VPHADDBQ_DEFINED 1 +#define XED_ICLASS_VPHADDBW_DEFINED 1 +#define XED_ICLASS_VPHADDD_DEFINED 1 +#define XED_ICLASS_VPHADDDQ_DEFINED 1 +#define XED_ICLASS_VPHADDSW_DEFINED 1 +#define XED_ICLASS_VPHADDUBD_DEFINED 1 +#define XED_ICLASS_VPHADDUBQ_DEFINED 1 +#define XED_ICLASS_VPHADDUBW_DEFINED 1 +#define XED_ICLASS_VPHADDUDQ_DEFINED 1 +#define XED_ICLASS_VPHADDUWD_DEFINED 1 +#define XED_ICLASS_VPHADDUWQ_DEFINED 1 +#define XED_ICLASS_VPHADDW_DEFINED 1 +#define XED_ICLASS_VPHADDWD_DEFINED 1 +#define XED_ICLASS_VPHADDWQ_DEFINED 1 +#define XED_ICLASS_VPHMINPOSUW_DEFINED 1 +#define XED_ICLASS_VPHSUBBW_DEFINED 1 +#define XED_ICLASS_VPHSUBD_DEFINED 1 +#define XED_ICLASS_VPHSUBDQ_DEFINED 1 +#define XED_ICLASS_VPHSUBSW_DEFINED 1 +#define XED_ICLASS_VPHSUBW_DEFINED 1 +#define XED_ICLASS_VPHSUBWD_DEFINED 1 +#define XED_ICLASS_VPINSRB_DEFINED 1 +#define XED_ICLASS_VPINSRD_DEFINED 1 +#define XED_ICLASS_VPINSRQ_DEFINED 1 +#define XED_ICLASS_VPINSRW_DEFINED 1 +#define XED_ICLASS_VPLZCNTD_DEFINED 1 +#define XED_ICLASS_VPLZCNTQ_DEFINED 1 +#define XED_ICLASS_VPMACSDD_DEFINED 1 +#define XED_ICLASS_VPMACSDQH_DEFINED 1 +#define XED_ICLASS_VPMACSDQL_DEFINED 1 +#define XED_ICLASS_VPMACSSDD_DEFINED 1 +#define XED_ICLASS_VPMACSSDQH_DEFINED 1 +#define XED_ICLASS_VPMACSSDQL_DEFINED 1 +#define XED_ICLASS_VPMACSSWD_DEFINED 1 +#define XED_ICLASS_VPMACSSWW_DEFINED 1 +#define XED_ICLASS_VPMACSWD_DEFINED 1 +#define XED_ICLASS_VPMACSWW_DEFINED 1 +#define XED_ICLASS_VPMADCSSWD_DEFINED 1 +#define XED_ICLASS_VPMADCSWD_DEFINED 1 +#define XED_ICLASS_VPMADD52HUQ_DEFINED 1 +#define XED_ICLASS_VPMADD52LUQ_DEFINED 1 +#define XED_ICLASS_VPMADDUBSW_DEFINED 1 +#define XED_ICLASS_VPMADDWD_DEFINED 1 +#define XED_ICLASS_VPMASKMOVD_DEFINED 1 +#define XED_ICLASS_VPMASKMOVQ_DEFINED 1 +#define XED_ICLASS_VPMAXSB_DEFINED 1 +#define XED_ICLASS_VPMAXSD_DEFINED 1 +#define XED_ICLASS_VPMAXSQ_DEFINED 1 +#define XED_ICLASS_VPMAXSW_DEFINED 1 +#define XED_ICLASS_VPMAXUB_DEFINED 1 +#define XED_ICLASS_VPMAXUD_DEFINED 1 +#define XED_ICLASS_VPMAXUQ_DEFINED 1 +#define XED_ICLASS_VPMAXUW_DEFINED 1 +#define XED_ICLASS_VPMINSB_DEFINED 1 +#define XED_ICLASS_VPMINSD_DEFINED 1 +#define XED_ICLASS_VPMINSQ_DEFINED 1 +#define XED_ICLASS_VPMINSW_DEFINED 1 +#define XED_ICLASS_VPMINUB_DEFINED 1 +#define XED_ICLASS_VPMINUD_DEFINED 1 +#define XED_ICLASS_VPMINUQ_DEFINED 1 +#define XED_ICLASS_VPMINUW_DEFINED 1 +#define XED_ICLASS_VPMOVB2M_DEFINED 1 +#define XED_ICLASS_VPMOVD2M_DEFINED 1 +#define XED_ICLASS_VPMOVDB_DEFINED 1 +#define XED_ICLASS_VPMOVDW_DEFINED 1 +#define XED_ICLASS_VPMOVM2B_DEFINED 1 +#define XED_ICLASS_VPMOVM2D_DEFINED 1 +#define XED_ICLASS_VPMOVM2Q_DEFINED 1 +#define XED_ICLASS_VPMOVM2W_DEFINED 1 +#define XED_ICLASS_VPMOVMSKB_DEFINED 1 +#define XED_ICLASS_VPMOVQ2M_DEFINED 1 +#define XED_ICLASS_VPMOVQB_DEFINED 1 +#define XED_ICLASS_VPMOVQD_DEFINED 1 +#define XED_ICLASS_VPMOVQW_DEFINED 1 +#define XED_ICLASS_VPMOVSDB_DEFINED 1 +#define XED_ICLASS_VPMOVSDW_DEFINED 1 +#define XED_ICLASS_VPMOVSQB_DEFINED 1 +#define XED_ICLASS_VPMOVSQD_DEFINED 1 +#define XED_ICLASS_VPMOVSQW_DEFINED 1 +#define XED_ICLASS_VPMOVSWB_DEFINED 1 +#define XED_ICLASS_VPMOVSXBD_DEFINED 1 +#define XED_ICLASS_VPMOVSXBQ_DEFINED 1 +#define XED_ICLASS_VPMOVSXBW_DEFINED 1 +#define XED_ICLASS_VPMOVSXDQ_DEFINED 1 +#define XED_ICLASS_VPMOVSXWD_DEFINED 1 +#define XED_ICLASS_VPMOVSXWQ_DEFINED 1 +#define XED_ICLASS_VPMOVUSDB_DEFINED 1 +#define XED_ICLASS_VPMOVUSDW_DEFINED 1 +#define XED_ICLASS_VPMOVUSQB_DEFINED 1 +#define XED_ICLASS_VPMOVUSQD_DEFINED 1 +#define XED_ICLASS_VPMOVUSQW_DEFINED 1 +#define XED_ICLASS_VPMOVUSWB_DEFINED 1 +#define XED_ICLASS_VPMOVW2M_DEFINED 1 +#define XED_ICLASS_VPMOVWB_DEFINED 1 +#define XED_ICLASS_VPMOVZXBD_DEFINED 1 +#define XED_ICLASS_VPMOVZXBQ_DEFINED 1 +#define XED_ICLASS_VPMOVZXBW_DEFINED 1 +#define XED_ICLASS_VPMOVZXDQ_DEFINED 1 +#define XED_ICLASS_VPMOVZXWD_DEFINED 1 +#define XED_ICLASS_VPMOVZXWQ_DEFINED 1 +#define XED_ICLASS_VPMULDQ_DEFINED 1 +#define XED_ICLASS_VPMULHRSW_DEFINED 1 +#define XED_ICLASS_VPMULHUW_DEFINED 1 +#define XED_ICLASS_VPMULHW_DEFINED 1 +#define XED_ICLASS_VPMULLD_DEFINED 1 +#define XED_ICLASS_VPMULLQ_DEFINED 1 +#define XED_ICLASS_VPMULLW_DEFINED 1 +#define XED_ICLASS_VPMULTISHIFTQB_DEFINED 1 +#define XED_ICLASS_VPMULUDQ_DEFINED 1 +#define XED_ICLASS_VPOPCNTB_DEFINED 1 +#define XED_ICLASS_VPOPCNTD_DEFINED 1 +#define XED_ICLASS_VPOPCNTQ_DEFINED 1 +#define XED_ICLASS_VPOPCNTW_DEFINED 1 +#define XED_ICLASS_VPOR_DEFINED 1 +#define XED_ICLASS_VPORD_DEFINED 1 +#define XED_ICLASS_VPORQ_DEFINED 1 +#define XED_ICLASS_VPPERM_DEFINED 1 +#define XED_ICLASS_VPROLD_DEFINED 1 +#define XED_ICLASS_VPROLQ_DEFINED 1 +#define XED_ICLASS_VPROLVD_DEFINED 1 +#define XED_ICLASS_VPROLVQ_DEFINED 1 +#define XED_ICLASS_VPRORD_DEFINED 1 +#define XED_ICLASS_VPRORQ_DEFINED 1 +#define XED_ICLASS_VPRORVD_DEFINED 1 +#define XED_ICLASS_VPRORVQ_DEFINED 1 +#define XED_ICLASS_VPROTB_DEFINED 1 +#define XED_ICLASS_VPROTD_DEFINED 1 +#define XED_ICLASS_VPROTQ_DEFINED 1 +#define XED_ICLASS_VPROTW_DEFINED 1 +#define XED_ICLASS_VPSADBW_DEFINED 1 +#define XED_ICLASS_VPSCATTERDD_DEFINED 1 +#define XED_ICLASS_VPSCATTERDQ_DEFINED 1 +#define XED_ICLASS_VPSCATTERQD_DEFINED 1 +#define XED_ICLASS_VPSCATTERQQ_DEFINED 1 +#define XED_ICLASS_VPSHAB_DEFINED 1 +#define XED_ICLASS_VPSHAD_DEFINED 1 +#define XED_ICLASS_VPSHAQ_DEFINED 1 +#define XED_ICLASS_VPSHAW_DEFINED 1 +#define XED_ICLASS_VPSHLB_DEFINED 1 +#define XED_ICLASS_VPSHLD_DEFINED 1 +#define XED_ICLASS_VPSHLDD_DEFINED 1 +#define XED_ICLASS_VPSHLDQ_DEFINED 1 +#define XED_ICLASS_VPSHLDVD_DEFINED 1 +#define XED_ICLASS_VPSHLDVQ_DEFINED 1 +#define XED_ICLASS_VPSHLDVW_DEFINED 1 +#define XED_ICLASS_VPSHLDW_DEFINED 1 +#define XED_ICLASS_VPSHLQ_DEFINED 1 +#define XED_ICLASS_VPSHLW_DEFINED 1 +#define XED_ICLASS_VPSHRDD_DEFINED 1 +#define XED_ICLASS_VPSHRDQ_DEFINED 1 +#define XED_ICLASS_VPSHRDVD_DEFINED 1 +#define XED_ICLASS_VPSHRDVQ_DEFINED 1 +#define XED_ICLASS_VPSHRDVW_DEFINED 1 +#define XED_ICLASS_VPSHRDW_DEFINED 1 +#define XED_ICLASS_VPSHUFB_DEFINED 1 +#define XED_ICLASS_VPSHUFBITQMB_DEFINED 1 +#define XED_ICLASS_VPSHUFD_DEFINED 1 +#define XED_ICLASS_VPSHUFHW_DEFINED 1 +#define XED_ICLASS_VPSHUFLW_DEFINED 1 +#define XED_ICLASS_VPSIGNB_DEFINED 1 +#define XED_ICLASS_VPSIGND_DEFINED 1 +#define XED_ICLASS_VPSIGNW_DEFINED 1 +#define XED_ICLASS_VPSLLD_DEFINED 1 +#define XED_ICLASS_VPSLLDQ_DEFINED 1 +#define XED_ICLASS_VPSLLQ_DEFINED 1 +#define XED_ICLASS_VPSLLVD_DEFINED 1 +#define XED_ICLASS_VPSLLVQ_DEFINED 1 +#define XED_ICLASS_VPSLLVW_DEFINED 1 +#define XED_ICLASS_VPSLLW_DEFINED 1 +#define XED_ICLASS_VPSRAD_DEFINED 1 +#define XED_ICLASS_VPSRAQ_DEFINED 1 +#define XED_ICLASS_VPSRAVD_DEFINED 1 +#define XED_ICLASS_VPSRAVQ_DEFINED 1 +#define XED_ICLASS_VPSRAVW_DEFINED 1 +#define XED_ICLASS_VPSRAW_DEFINED 1 +#define XED_ICLASS_VPSRLD_DEFINED 1 +#define XED_ICLASS_VPSRLDQ_DEFINED 1 +#define XED_ICLASS_VPSRLQ_DEFINED 1 +#define XED_ICLASS_VPSRLVD_DEFINED 1 +#define XED_ICLASS_VPSRLVQ_DEFINED 1 +#define XED_ICLASS_VPSRLVW_DEFINED 1 +#define XED_ICLASS_VPSRLW_DEFINED 1 +#define XED_ICLASS_VPSUBB_DEFINED 1 +#define XED_ICLASS_VPSUBD_DEFINED 1 +#define XED_ICLASS_VPSUBQ_DEFINED 1 +#define XED_ICLASS_VPSUBSB_DEFINED 1 +#define XED_ICLASS_VPSUBSW_DEFINED 1 +#define XED_ICLASS_VPSUBUSB_DEFINED 1 +#define XED_ICLASS_VPSUBUSW_DEFINED 1 +#define XED_ICLASS_VPSUBW_DEFINED 1 +#define XED_ICLASS_VPTERNLOGD_DEFINED 1 +#define XED_ICLASS_VPTERNLOGQ_DEFINED 1 +#define XED_ICLASS_VPTEST_DEFINED 1 +#define XED_ICLASS_VPTESTMB_DEFINED 1 +#define XED_ICLASS_VPTESTMD_DEFINED 1 +#define XED_ICLASS_VPTESTMQ_DEFINED 1 +#define XED_ICLASS_VPTESTMW_DEFINED 1 +#define XED_ICLASS_VPTESTNMB_DEFINED 1 +#define XED_ICLASS_VPTESTNMD_DEFINED 1 +#define XED_ICLASS_VPTESTNMQ_DEFINED 1 +#define XED_ICLASS_VPTESTNMW_DEFINED 1 +#define XED_ICLASS_VPUNPCKHBW_DEFINED 1 +#define XED_ICLASS_VPUNPCKHDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKHQDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKHWD_DEFINED 1 +#define XED_ICLASS_VPUNPCKLBW_DEFINED 1 +#define XED_ICLASS_VPUNPCKLDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKLQDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKLWD_DEFINED 1 +#define XED_ICLASS_VPXOR_DEFINED 1 +#define XED_ICLASS_VPXORD_DEFINED 1 +#define XED_ICLASS_VPXORQ_DEFINED 1 +#define XED_ICLASS_VRANGEPD_DEFINED 1 +#define XED_ICLASS_VRANGEPS_DEFINED 1 +#define XED_ICLASS_VRANGESD_DEFINED 1 +#define XED_ICLASS_VRANGESS_DEFINED 1 +#define XED_ICLASS_VRCP14PD_DEFINED 1 +#define XED_ICLASS_VRCP14PS_DEFINED 1 +#define XED_ICLASS_VRCP14SD_DEFINED 1 +#define XED_ICLASS_VRCP14SS_DEFINED 1 +#define XED_ICLASS_VRCP28PD_DEFINED 1 +#define XED_ICLASS_VRCP28PS_DEFINED 1 +#define XED_ICLASS_VRCP28SD_DEFINED 1 +#define XED_ICLASS_VRCP28SS_DEFINED 1 +#define XED_ICLASS_VRCPPH_DEFINED 1 +#define XED_ICLASS_VRCPPS_DEFINED 1 +#define XED_ICLASS_VRCPSH_DEFINED 1 +#define XED_ICLASS_VRCPSS_DEFINED 1 +#define XED_ICLASS_VREDUCEPD_DEFINED 1 +#define XED_ICLASS_VREDUCEPH_DEFINED 1 +#define XED_ICLASS_VREDUCEPS_DEFINED 1 +#define XED_ICLASS_VREDUCESD_DEFINED 1 +#define XED_ICLASS_VREDUCESH_DEFINED 1 +#define XED_ICLASS_VREDUCESS_DEFINED 1 +#define XED_ICLASS_VRNDSCALEPD_DEFINED 1 +#define XED_ICLASS_VRNDSCALEPH_DEFINED 1 +#define XED_ICLASS_VRNDSCALEPS_DEFINED 1 +#define XED_ICLASS_VRNDSCALESD_DEFINED 1 +#define XED_ICLASS_VRNDSCALESH_DEFINED 1 +#define XED_ICLASS_VRNDSCALESS_DEFINED 1 +#define XED_ICLASS_VROUNDPD_DEFINED 1 +#define XED_ICLASS_VROUNDPS_DEFINED 1 +#define XED_ICLASS_VROUNDSD_DEFINED 1 +#define XED_ICLASS_VROUNDSS_DEFINED 1 +#define XED_ICLASS_VRSQRT14PD_DEFINED 1 +#define XED_ICLASS_VRSQRT14PS_DEFINED 1 +#define XED_ICLASS_VRSQRT14SD_DEFINED 1 +#define XED_ICLASS_VRSQRT14SS_DEFINED 1 +#define XED_ICLASS_VRSQRT28PD_DEFINED 1 +#define XED_ICLASS_VRSQRT28PS_DEFINED 1 +#define XED_ICLASS_VRSQRT28SD_DEFINED 1 +#define XED_ICLASS_VRSQRT28SS_DEFINED 1 +#define XED_ICLASS_VRSQRTPH_DEFINED 1 +#define XED_ICLASS_VRSQRTPS_DEFINED 1 +#define XED_ICLASS_VRSQRTSH_DEFINED 1 +#define XED_ICLASS_VRSQRTSS_DEFINED 1 +#define XED_ICLASS_VSCALEFPD_DEFINED 1 +#define XED_ICLASS_VSCALEFPH_DEFINED 1 +#define XED_ICLASS_VSCALEFPS_DEFINED 1 +#define XED_ICLASS_VSCALEFSD_DEFINED 1 +#define XED_ICLASS_VSCALEFSH_DEFINED 1 +#define XED_ICLASS_VSCALEFSS_DEFINED 1 +#define XED_ICLASS_VSCATTERDPD_DEFINED 1 +#define XED_ICLASS_VSCATTERDPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0DPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0DPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0QPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0QPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1DPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1DPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1QPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1QPS_DEFINED 1 +#define XED_ICLASS_VSCATTERQPD_DEFINED 1 +#define XED_ICLASS_VSCATTERQPS_DEFINED 1 +#define XED_ICLASS_VSHUFF32X4_DEFINED 1 +#define XED_ICLASS_VSHUFF64X2_DEFINED 1 +#define XED_ICLASS_VSHUFI32X4_DEFINED 1 +#define XED_ICLASS_VSHUFI64X2_DEFINED 1 +#define XED_ICLASS_VSHUFPD_DEFINED 1 +#define XED_ICLASS_VSHUFPS_DEFINED 1 +#define XED_ICLASS_VSQRTPD_DEFINED 1 +#define XED_ICLASS_VSQRTPH_DEFINED 1 +#define XED_ICLASS_VSQRTPS_DEFINED 1 +#define XED_ICLASS_VSQRTSD_DEFINED 1 +#define XED_ICLASS_VSQRTSH_DEFINED 1 +#define XED_ICLASS_VSQRTSS_DEFINED 1 +#define XED_ICLASS_VSTMXCSR_DEFINED 1 +#define XED_ICLASS_VSUBPD_DEFINED 1 +#define XED_ICLASS_VSUBPH_DEFINED 1 +#define XED_ICLASS_VSUBPS_DEFINED 1 +#define XED_ICLASS_VSUBSD_DEFINED 1 +#define XED_ICLASS_VSUBSH_DEFINED 1 +#define XED_ICLASS_VSUBSS_DEFINED 1 +#define XED_ICLASS_VTESTPD_DEFINED 1 +#define XED_ICLASS_VTESTPS_DEFINED 1 +#define XED_ICLASS_VUCOMISD_DEFINED 1 +#define XED_ICLASS_VUCOMISH_DEFINED 1 +#define XED_ICLASS_VUCOMISS_DEFINED 1 +#define XED_ICLASS_VUNPCKHPD_DEFINED 1 +#define XED_ICLASS_VUNPCKHPS_DEFINED 1 +#define XED_ICLASS_VUNPCKLPD_DEFINED 1 +#define XED_ICLASS_VUNPCKLPS_DEFINED 1 +#define XED_ICLASS_VXORPD_DEFINED 1 +#define XED_ICLASS_VXORPS_DEFINED 1 +#define XED_ICLASS_VZEROALL_DEFINED 1 +#define XED_ICLASS_VZEROUPPER_DEFINED 1 +#define XED_ICLASS_WBINVD_DEFINED 1 +#define XED_ICLASS_WBNOINVD_DEFINED 1 +#define XED_ICLASS_WRFSBASE_DEFINED 1 +#define XED_ICLASS_WRGSBASE_DEFINED 1 +#define XED_ICLASS_WRMSR_DEFINED 1 +#define XED_ICLASS_WRPKRU_DEFINED 1 +#define XED_ICLASS_WRSSD_DEFINED 1 +#define XED_ICLASS_WRSSQ_DEFINED 1 +#define XED_ICLASS_WRUSSD_DEFINED 1 +#define XED_ICLASS_WRUSSQ_DEFINED 1 +#define XED_ICLASS_XABORT_DEFINED 1 +#define XED_ICLASS_XADD_DEFINED 1 +#define XED_ICLASS_XADD_LOCK_DEFINED 1 +#define XED_ICLASS_XBEGIN_DEFINED 1 +#define XED_ICLASS_XCHG_DEFINED 1 +#define XED_ICLASS_XEND_DEFINED 1 +#define XED_ICLASS_XGETBV_DEFINED 1 +#define XED_ICLASS_XLAT_DEFINED 1 +#define XED_ICLASS_XOR_DEFINED 1 +#define XED_ICLASS_XORPD_DEFINED 1 +#define XED_ICLASS_XORPS_DEFINED 1 +#define XED_ICLASS_XOR_LOCK_DEFINED 1 +#define XED_ICLASS_XRESLDTRK_DEFINED 1 +#define XED_ICLASS_XRSTOR_DEFINED 1 +#define XED_ICLASS_XRSTOR64_DEFINED 1 +#define XED_ICLASS_XRSTORS_DEFINED 1 +#define XED_ICLASS_XRSTORS64_DEFINED 1 +#define XED_ICLASS_XSAVE_DEFINED 1 +#define XED_ICLASS_XSAVE64_DEFINED 1 +#define XED_ICLASS_XSAVEC_DEFINED 1 +#define XED_ICLASS_XSAVEC64_DEFINED 1 +#define XED_ICLASS_XSAVEOPT_DEFINED 1 +#define XED_ICLASS_XSAVEOPT64_DEFINED 1 +#define XED_ICLASS_XSAVES_DEFINED 1 +#define XED_ICLASS_XSAVES64_DEFINED 1 +#define XED_ICLASS_XSETBV_DEFINED 1 +#define XED_ICLASS_XSTORE_DEFINED 1 +#define XED_ICLASS_XSUSLDTRK_DEFINED 1 +#define XED_ICLASS_XTEST_DEFINED 1 +#define XED_ICLASS_LAST_DEFINED 1 +typedef enum { + XED_ICLASS_INVALID, + XED_ICLASS_AAA, + XED_ICLASS_AAD, + XED_ICLASS_AAM, + XED_ICLASS_AAS, + XED_ICLASS_ADC, + XED_ICLASS_ADCX, + XED_ICLASS_ADC_LOCK, + XED_ICLASS_ADD, + XED_ICLASS_ADDPD, + XED_ICLASS_ADDPS, + XED_ICLASS_ADDSD, + XED_ICLASS_ADDSS, + XED_ICLASS_ADDSUBPD, + XED_ICLASS_ADDSUBPS, + XED_ICLASS_ADD_LOCK, + XED_ICLASS_ADOX, + XED_ICLASS_AESDEC, + XED_ICLASS_AESDEC128KL, + XED_ICLASS_AESDEC256KL, + XED_ICLASS_AESDECLAST, + XED_ICLASS_AESDECWIDE128KL, + XED_ICLASS_AESDECWIDE256KL, + XED_ICLASS_AESENC, + XED_ICLASS_AESENC128KL, + XED_ICLASS_AESENC256KL, + XED_ICLASS_AESENCLAST, + XED_ICLASS_AESENCWIDE128KL, + XED_ICLASS_AESENCWIDE256KL, + XED_ICLASS_AESIMC, + XED_ICLASS_AESKEYGENASSIST, + XED_ICLASS_AND, + XED_ICLASS_ANDN, + XED_ICLASS_ANDNPD, + XED_ICLASS_ANDNPS, + XED_ICLASS_ANDPD, + XED_ICLASS_ANDPS, + XED_ICLASS_AND_LOCK, + XED_ICLASS_ARPL, + XED_ICLASS_BEXTR, + XED_ICLASS_BEXTR_XOP, + XED_ICLASS_BLCFILL, + XED_ICLASS_BLCI, + XED_ICLASS_BLCIC, + XED_ICLASS_BLCMSK, + XED_ICLASS_BLCS, + XED_ICLASS_BLENDPD, + XED_ICLASS_BLENDPS, + XED_ICLASS_BLENDVPD, + XED_ICLASS_BLENDVPS, + XED_ICLASS_BLSFILL, + XED_ICLASS_BLSI, + XED_ICLASS_BLSIC, + XED_ICLASS_BLSMSK, + XED_ICLASS_BLSR, + XED_ICLASS_BNDCL, + XED_ICLASS_BNDCN, + XED_ICLASS_BNDCU, + XED_ICLASS_BNDLDX, + XED_ICLASS_BNDMK, + XED_ICLASS_BNDMOV, + XED_ICLASS_BNDSTX, + XED_ICLASS_BOUND, + XED_ICLASS_BSF, + XED_ICLASS_BSR, + XED_ICLASS_BSWAP, + XED_ICLASS_BT, + XED_ICLASS_BTC, + XED_ICLASS_BTC_LOCK, + XED_ICLASS_BTR, + XED_ICLASS_BTR_LOCK, + XED_ICLASS_BTS, + XED_ICLASS_BTS_LOCK, + XED_ICLASS_BZHI, + XED_ICLASS_CALL_FAR, + XED_ICLASS_CALL_NEAR, + XED_ICLASS_CBW, + XED_ICLASS_CDQ, + XED_ICLASS_CDQE, + XED_ICLASS_CLAC, + XED_ICLASS_CLC, + XED_ICLASS_CLD, + XED_ICLASS_CLDEMOTE, + XED_ICLASS_CLFLUSH, + XED_ICLASS_CLFLUSHOPT, + XED_ICLASS_CLGI, + XED_ICLASS_CLI, + XED_ICLASS_CLRSSBSY, + XED_ICLASS_CLTS, + XED_ICLASS_CLUI, + XED_ICLASS_CLWB, + XED_ICLASS_CLZERO, + XED_ICLASS_CMC, + XED_ICLASS_CMOVB, + XED_ICLASS_CMOVBE, + XED_ICLASS_CMOVL, + XED_ICLASS_CMOVLE, + XED_ICLASS_CMOVNB, + XED_ICLASS_CMOVNBE, + XED_ICLASS_CMOVNL, + XED_ICLASS_CMOVNLE, + XED_ICLASS_CMOVNO, + XED_ICLASS_CMOVNP, + XED_ICLASS_CMOVNS, + XED_ICLASS_CMOVNZ, + XED_ICLASS_CMOVO, + XED_ICLASS_CMOVP, + XED_ICLASS_CMOVS, + XED_ICLASS_CMOVZ, + XED_ICLASS_CMP, + XED_ICLASS_CMPPD, + XED_ICLASS_CMPPS, + XED_ICLASS_CMPSB, + XED_ICLASS_CMPSD, + XED_ICLASS_CMPSD_XMM, + XED_ICLASS_CMPSQ, + XED_ICLASS_CMPSS, + XED_ICLASS_CMPSW, + XED_ICLASS_CMPXCHG, + XED_ICLASS_CMPXCHG16B, + XED_ICLASS_CMPXCHG16B_LOCK, + XED_ICLASS_CMPXCHG8B, + XED_ICLASS_CMPXCHG8B_LOCK, + XED_ICLASS_CMPXCHG_LOCK, + XED_ICLASS_COMISD, + XED_ICLASS_COMISS, + XED_ICLASS_CPUID, + XED_ICLASS_CQO, + XED_ICLASS_CRC32, + XED_ICLASS_CVTDQ2PD, + XED_ICLASS_CVTDQ2PS, + XED_ICLASS_CVTPD2DQ, + XED_ICLASS_CVTPD2PI, + XED_ICLASS_CVTPD2PS, + XED_ICLASS_CVTPI2PD, + XED_ICLASS_CVTPI2PS, + XED_ICLASS_CVTPS2DQ, + XED_ICLASS_CVTPS2PD, + XED_ICLASS_CVTPS2PI, + XED_ICLASS_CVTSD2SI, + XED_ICLASS_CVTSD2SS, + XED_ICLASS_CVTSI2SD, + XED_ICLASS_CVTSI2SS, + XED_ICLASS_CVTSS2SD, + XED_ICLASS_CVTSS2SI, + XED_ICLASS_CVTTPD2DQ, + XED_ICLASS_CVTTPD2PI, + XED_ICLASS_CVTTPS2DQ, + XED_ICLASS_CVTTPS2PI, + XED_ICLASS_CVTTSD2SI, + XED_ICLASS_CVTTSS2SI, + XED_ICLASS_CWD, + XED_ICLASS_CWDE, + XED_ICLASS_DAA, + XED_ICLASS_DAS, + XED_ICLASS_DEC, + XED_ICLASS_DEC_LOCK, + XED_ICLASS_DIV, + XED_ICLASS_DIVPD, + XED_ICLASS_DIVPS, + XED_ICLASS_DIVSD, + XED_ICLASS_DIVSS, + XED_ICLASS_DPPD, + XED_ICLASS_DPPS, + XED_ICLASS_EMMS, + XED_ICLASS_ENCLS, + XED_ICLASS_ENCLU, + XED_ICLASS_ENCLV, + XED_ICLASS_ENCODEKEY128, + XED_ICLASS_ENCODEKEY256, + XED_ICLASS_ENDBR32, + XED_ICLASS_ENDBR64, + XED_ICLASS_ENQCMD, + XED_ICLASS_ENQCMDS, + XED_ICLASS_ENTER, + XED_ICLASS_EXTRACTPS, + XED_ICLASS_EXTRQ, + XED_ICLASS_F2XM1, + XED_ICLASS_FABS, + XED_ICLASS_FADD, + XED_ICLASS_FADDP, + XED_ICLASS_FBLD, + XED_ICLASS_FBSTP, + XED_ICLASS_FCHS, + XED_ICLASS_FCMOVB, + XED_ICLASS_FCMOVBE, + XED_ICLASS_FCMOVE, + XED_ICLASS_FCMOVNB, + XED_ICLASS_FCMOVNBE, + XED_ICLASS_FCMOVNE, + XED_ICLASS_FCMOVNU, + XED_ICLASS_FCMOVU, + XED_ICLASS_FCOM, + XED_ICLASS_FCOMI, + XED_ICLASS_FCOMIP, + XED_ICLASS_FCOMP, + XED_ICLASS_FCOMPP, + XED_ICLASS_FCOS, + XED_ICLASS_FDECSTP, + XED_ICLASS_FDISI8087_NOP, + XED_ICLASS_FDIV, + XED_ICLASS_FDIVP, + XED_ICLASS_FDIVR, + XED_ICLASS_FDIVRP, + XED_ICLASS_FEMMS, + XED_ICLASS_FENI8087_NOP, + XED_ICLASS_FFREE, + XED_ICLASS_FFREEP, + XED_ICLASS_FIADD, + XED_ICLASS_FICOM, + XED_ICLASS_FICOMP, + XED_ICLASS_FIDIV, + XED_ICLASS_FIDIVR, + XED_ICLASS_FILD, + XED_ICLASS_FIMUL, + XED_ICLASS_FINCSTP, + XED_ICLASS_FIST, + XED_ICLASS_FISTP, + XED_ICLASS_FISTTP, + XED_ICLASS_FISUB, + XED_ICLASS_FISUBR, + XED_ICLASS_FLD, + XED_ICLASS_FLD1, + XED_ICLASS_FLDCW, + XED_ICLASS_FLDENV, + XED_ICLASS_FLDL2E, + XED_ICLASS_FLDL2T, + XED_ICLASS_FLDLG2, + XED_ICLASS_FLDLN2, + XED_ICLASS_FLDPI, + XED_ICLASS_FLDZ, + XED_ICLASS_FMUL, + XED_ICLASS_FMULP, + XED_ICLASS_FNCLEX, + XED_ICLASS_FNINIT, + XED_ICLASS_FNOP, + XED_ICLASS_FNSAVE, + XED_ICLASS_FNSTCW, + XED_ICLASS_FNSTENV, + XED_ICLASS_FNSTSW, + XED_ICLASS_FPATAN, + XED_ICLASS_FPREM, + XED_ICLASS_FPREM1, + XED_ICLASS_FPTAN, + XED_ICLASS_FRNDINT, + XED_ICLASS_FRSTOR, + XED_ICLASS_FSCALE, + XED_ICLASS_FSETPM287_NOP, + XED_ICLASS_FSIN, + XED_ICLASS_FSINCOS, + XED_ICLASS_FSQRT, + XED_ICLASS_FST, + XED_ICLASS_FSTP, + XED_ICLASS_FSTPNCE, + XED_ICLASS_FSUB, + XED_ICLASS_FSUBP, + XED_ICLASS_FSUBR, + XED_ICLASS_FSUBRP, + XED_ICLASS_FTST, + XED_ICLASS_FUCOM, + XED_ICLASS_FUCOMI, + XED_ICLASS_FUCOMIP, + XED_ICLASS_FUCOMP, + XED_ICLASS_FUCOMPP, + XED_ICLASS_FWAIT, + XED_ICLASS_FXAM, + XED_ICLASS_FXCH, + XED_ICLASS_FXRSTOR, + XED_ICLASS_FXRSTOR64, + XED_ICLASS_FXSAVE, + XED_ICLASS_FXSAVE64, + XED_ICLASS_FXTRACT, + XED_ICLASS_FYL2X, + XED_ICLASS_FYL2XP1, + XED_ICLASS_GETSEC, + XED_ICLASS_GF2P8AFFINEINVQB, + XED_ICLASS_GF2P8AFFINEQB, + XED_ICLASS_GF2P8MULB, + XED_ICLASS_HADDPD, + XED_ICLASS_HADDPS, + XED_ICLASS_HLT, + XED_ICLASS_HRESET, + XED_ICLASS_HSUBPD, + XED_ICLASS_HSUBPS, + XED_ICLASS_IDIV, + XED_ICLASS_IMUL, + XED_ICLASS_IN, + XED_ICLASS_INC, + XED_ICLASS_INCSSPD, + XED_ICLASS_INCSSPQ, + XED_ICLASS_INC_LOCK, + XED_ICLASS_INSB, + XED_ICLASS_INSD, + XED_ICLASS_INSERTPS, + XED_ICLASS_INSERTQ, + XED_ICLASS_INSW, + XED_ICLASS_INT, + XED_ICLASS_INT1, + XED_ICLASS_INT3, + XED_ICLASS_INTO, + XED_ICLASS_INVD, + XED_ICLASS_INVEPT, + XED_ICLASS_INVLPG, + XED_ICLASS_INVLPGA, + XED_ICLASS_INVLPGB, + XED_ICLASS_INVPCID, + XED_ICLASS_INVVPID, + XED_ICLASS_IRET, + XED_ICLASS_IRETD, + XED_ICLASS_IRETQ, + XED_ICLASS_JB, + XED_ICLASS_JBE, + XED_ICLASS_JCXZ, + XED_ICLASS_JECXZ, + XED_ICLASS_JL, + XED_ICLASS_JLE, + XED_ICLASS_JMP, + XED_ICLASS_JMP_FAR, + XED_ICLASS_JNB, + XED_ICLASS_JNBE, + XED_ICLASS_JNL, + XED_ICLASS_JNLE, + XED_ICLASS_JNO, + XED_ICLASS_JNP, + XED_ICLASS_JNS, + XED_ICLASS_JNZ, + XED_ICLASS_JO, + XED_ICLASS_JP, + XED_ICLASS_JRCXZ, + XED_ICLASS_JS, + XED_ICLASS_JZ, + XED_ICLASS_KADDB, + XED_ICLASS_KADDD, + XED_ICLASS_KADDQ, + XED_ICLASS_KADDW, + XED_ICLASS_KANDB, + XED_ICLASS_KANDD, + XED_ICLASS_KANDNB, + XED_ICLASS_KANDND, + XED_ICLASS_KANDNQ, + XED_ICLASS_KANDNW, + XED_ICLASS_KANDQ, + XED_ICLASS_KANDW, + XED_ICLASS_KMOVB, + XED_ICLASS_KMOVD, + XED_ICLASS_KMOVQ, + XED_ICLASS_KMOVW, + XED_ICLASS_KNOTB, + XED_ICLASS_KNOTD, + XED_ICLASS_KNOTQ, + XED_ICLASS_KNOTW, + XED_ICLASS_KORB, + XED_ICLASS_KORD, + XED_ICLASS_KORQ, + XED_ICLASS_KORTESTB, + XED_ICLASS_KORTESTD, + XED_ICLASS_KORTESTQ, + XED_ICLASS_KORTESTW, + XED_ICLASS_KORW, + XED_ICLASS_KSHIFTLB, + XED_ICLASS_KSHIFTLD, + XED_ICLASS_KSHIFTLQ, + XED_ICLASS_KSHIFTLW, + XED_ICLASS_KSHIFTRB, + XED_ICLASS_KSHIFTRD, + XED_ICLASS_KSHIFTRQ, + XED_ICLASS_KSHIFTRW, + XED_ICLASS_KTESTB, + XED_ICLASS_KTESTD, + XED_ICLASS_KTESTQ, + XED_ICLASS_KTESTW, + XED_ICLASS_KUNPCKBW, + XED_ICLASS_KUNPCKDQ, + XED_ICLASS_KUNPCKWD, + XED_ICLASS_KXNORB, + XED_ICLASS_KXNORD, + XED_ICLASS_KXNORQ, + XED_ICLASS_KXNORW, + XED_ICLASS_KXORB, + XED_ICLASS_KXORD, + XED_ICLASS_KXORQ, + XED_ICLASS_KXORW, + XED_ICLASS_LAHF, + XED_ICLASS_LAR, + XED_ICLASS_LDDQU, + XED_ICLASS_LDMXCSR, + XED_ICLASS_LDS, + XED_ICLASS_LDTILECFG, + XED_ICLASS_LEA, + XED_ICLASS_LEAVE, + XED_ICLASS_LES, + XED_ICLASS_LFENCE, + XED_ICLASS_LFS, + XED_ICLASS_LGDT, + XED_ICLASS_LGS, + XED_ICLASS_LIDT, + XED_ICLASS_LLDT, + XED_ICLASS_LLWPCB, + XED_ICLASS_LMSW, + XED_ICLASS_LOADIWKEY, + XED_ICLASS_LODSB, + XED_ICLASS_LODSD, + XED_ICLASS_LODSQ, + XED_ICLASS_LODSW, + XED_ICLASS_LOOP, + XED_ICLASS_LOOPE, + XED_ICLASS_LOOPNE, + XED_ICLASS_LSL, + XED_ICLASS_LSS, + XED_ICLASS_LTR, + XED_ICLASS_LWPINS, + XED_ICLASS_LWPVAL, + XED_ICLASS_LZCNT, + XED_ICLASS_MASKMOVDQU, + XED_ICLASS_MASKMOVQ, + XED_ICLASS_MAXPD, + XED_ICLASS_MAXPS, + XED_ICLASS_MAXSD, + XED_ICLASS_MAXSS, + XED_ICLASS_MCOMMIT, + XED_ICLASS_MFENCE, + XED_ICLASS_MINPD, + XED_ICLASS_MINPS, + XED_ICLASS_MINSD, + XED_ICLASS_MINSS, + XED_ICLASS_MONITOR, + XED_ICLASS_MONITORX, + XED_ICLASS_MOV, + XED_ICLASS_MOVAPD, + XED_ICLASS_MOVAPS, + XED_ICLASS_MOVBE, + XED_ICLASS_MOVD, + XED_ICLASS_MOVDDUP, + XED_ICLASS_MOVDIR64B, + XED_ICLASS_MOVDIRI, + XED_ICLASS_MOVDQ2Q, + XED_ICLASS_MOVDQA, + XED_ICLASS_MOVDQU, + XED_ICLASS_MOVHLPS, + XED_ICLASS_MOVHPD, + XED_ICLASS_MOVHPS, + XED_ICLASS_MOVLHPS, + XED_ICLASS_MOVLPD, + XED_ICLASS_MOVLPS, + XED_ICLASS_MOVMSKPD, + XED_ICLASS_MOVMSKPS, + XED_ICLASS_MOVNTDQ, + XED_ICLASS_MOVNTDQA, + XED_ICLASS_MOVNTI, + XED_ICLASS_MOVNTPD, + XED_ICLASS_MOVNTPS, + XED_ICLASS_MOVNTQ, + XED_ICLASS_MOVNTSD, + XED_ICLASS_MOVNTSS, + XED_ICLASS_MOVQ, + XED_ICLASS_MOVQ2DQ, + XED_ICLASS_MOVSB, + XED_ICLASS_MOVSD, + XED_ICLASS_MOVSD_XMM, + XED_ICLASS_MOVSHDUP, + XED_ICLASS_MOVSLDUP, + XED_ICLASS_MOVSQ, + XED_ICLASS_MOVSS, + XED_ICLASS_MOVSW, + XED_ICLASS_MOVSX, + XED_ICLASS_MOVSXD, + XED_ICLASS_MOVUPD, + XED_ICLASS_MOVUPS, + XED_ICLASS_MOVZX, + XED_ICLASS_MOV_CR, + XED_ICLASS_MOV_DR, + XED_ICLASS_MPSADBW, + XED_ICLASS_MUL, + XED_ICLASS_MULPD, + XED_ICLASS_MULPS, + XED_ICLASS_MULSD, + XED_ICLASS_MULSS, + XED_ICLASS_MULX, + XED_ICLASS_MWAIT, + XED_ICLASS_MWAITX, + XED_ICLASS_NEG, + XED_ICLASS_NEG_LOCK, + XED_ICLASS_NOP, + XED_ICLASS_NOP2, + XED_ICLASS_NOP3, + XED_ICLASS_NOP4, + XED_ICLASS_NOP5, + XED_ICLASS_NOP6, + XED_ICLASS_NOP7, + XED_ICLASS_NOP8, + XED_ICLASS_NOP9, + XED_ICLASS_NOT, + XED_ICLASS_NOT_LOCK, + XED_ICLASS_OR, + XED_ICLASS_ORPD, + XED_ICLASS_ORPS, + XED_ICLASS_OR_LOCK, + XED_ICLASS_OUT, + XED_ICLASS_OUTSB, + XED_ICLASS_OUTSD, + XED_ICLASS_OUTSW, + XED_ICLASS_PABSB, + XED_ICLASS_PABSD, + XED_ICLASS_PABSW, + XED_ICLASS_PACKSSDW, + XED_ICLASS_PACKSSWB, + XED_ICLASS_PACKUSDW, + XED_ICLASS_PACKUSWB, + XED_ICLASS_PADDB, + XED_ICLASS_PADDD, + XED_ICLASS_PADDQ, + XED_ICLASS_PADDSB, + XED_ICLASS_PADDSW, + XED_ICLASS_PADDUSB, + XED_ICLASS_PADDUSW, + XED_ICLASS_PADDW, + XED_ICLASS_PALIGNR, + XED_ICLASS_PAND, + XED_ICLASS_PANDN, + XED_ICLASS_PAUSE, + XED_ICLASS_PAVGB, + XED_ICLASS_PAVGUSB, + XED_ICLASS_PAVGW, + XED_ICLASS_PBLENDVB, + XED_ICLASS_PBLENDW, + XED_ICLASS_PCLMULQDQ, + XED_ICLASS_PCMPEQB, + XED_ICLASS_PCMPEQD, + XED_ICLASS_PCMPEQQ, + XED_ICLASS_PCMPEQW, + XED_ICLASS_PCMPESTRI, + XED_ICLASS_PCMPESTRI64, + XED_ICLASS_PCMPESTRM, + XED_ICLASS_PCMPESTRM64, + XED_ICLASS_PCMPGTB, + XED_ICLASS_PCMPGTD, + XED_ICLASS_PCMPGTQ, + XED_ICLASS_PCMPGTW, + XED_ICLASS_PCMPISTRI, + XED_ICLASS_PCMPISTRI64, + XED_ICLASS_PCMPISTRM, + XED_ICLASS_PCONFIG, + XED_ICLASS_PDEP, + XED_ICLASS_PEXT, + XED_ICLASS_PEXTRB, + XED_ICLASS_PEXTRD, + XED_ICLASS_PEXTRQ, + XED_ICLASS_PEXTRW, + XED_ICLASS_PEXTRW_SSE4, + XED_ICLASS_PF2ID, + XED_ICLASS_PF2IW, + XED_ICLASS_PFACC, + XED_ICLASS_PFADD, + XED_ICLASS_PFCMPEQ, + XED_ICLASS_PFCMPGE, + XED_ICLASS_PFCMPGT, + XED_ICLASS_PFMAX, + XED_ICLASS_PFMIN, + XED_ICLASS_PFMUL, + XED_ICLASS_PFNACC, + XED_ICLASS_PFPNACC, + XED_ICLASS_PFRCP, + XED_ICLASS_PFRCPIT1, + XED_ICLASS_PFRCPIT2, + XED_ICLASS_PFRSQIT1, + XED_ICLASS_PFRSQRT, + XED_ICLASS_PFSUB, + XED_ICLASS_PFSUBR, + XED_ICLASS_PHADDD, + XED_ICLASS_PHADDSW, + XED_ICLASS_PHADDW, + XED_ICLASS_PHMINPOSUW, + XED_ICLASS_PHSUBD, + XED_ICLASS_PHSUBSW, + XED_ICLASS_PHSUBW, + XED_ICLASS_PI2FD, + XED_ICLASS_PI2FW, + XED_ICLASS_PINSRB, + XED_ICLASS_PINSRD, + XED_ICLASS_PINSRQ, + XED_ICLASS_PINSRW, + XED_ICLASS_PMADDUBSW, + XED_ICLASS_PMADDWD, + XED_ICLASS_PMAXSB, + XED_ICLASS_PMAXSD, + XED_ICLASS_PMAXSW, + XED_ICLASS_PMAXUB, + XED_ICLASS_PMAXUD, + XED_ICLASS_PMAXUW, + XED_ICLASS_PMINSB, + XED_ICLASS_PMINSD, + XED_ICLASS_PMINSW, + XED_ICLASS_PMINUB, + XED_ICLASS_PMINUD, + XED_ICLASS_PMINUW, + XED_ICLASS_PMOVMSKB, + XED_ICLASS_PMOVSXBD, + XED_ICLASS_PMOVSXBQ, + XED_ICLASS_PMOVSXBW, + XED_ICLASS_PMOVSXDQ, + XED_ICLASS_PMOVSXWD, + XED_ICLASS_PMOVSXWQ, + XED_ICLASS_PMOVZXBD, + XED_ICLASS_PMOVZXBQ, + XED_ICLASS_PMOVZXBW, + XED_ICLASS_PMOVZXDQ, + XED_ICLASS_PMOVZXWD, + XED_ICLASS_PMOVZXWQ, + XED_ICLASS_PMULDQ, + XED_ICLASS_PMULHRSW, + XED_ICLASS_PMULHRW, + XED_ICLASS_PMULHUW, + XED_ICLASS_PMULHW, + XED_ICLASS_PMULLD, + XED_ICLASS_PMULLW, + XED_ICLASS_PMULUDQ, + XED_ICLASS_POP, + XED_ICLASS_POPA, + XED_ICLASS_POPAD, + XED_ICLASS_POPCNT, + XED_ICLASS_POPF, + XED_ICLASS_POPFD, + XED_ICLASS_POPFQ, + XED_ICLASS_POR, + XED_ICLASS_PREFETCHNTA, + XED_ICLASS_PREFETCHT0, + XED_ICLASS_PREFETCHT1, + XED_ICLASS_PREFETCHT2, + XED_ICLASS_PREFETCHW, + XED_ICLASS_PREFETCHWT1, + XED_ICLASS_PREFETCH_EXCLUSIVE, + XED_ICLASS_PREFETCH_RESERVED, + XED_ICLASS_PSADBW, + XED_ICLASS_PSHUFB, + XED_ICLASS_PSHUFD, + XED_ICLASS_PSHUFHW, + XED_ICLASS_PSHUFLW, + XED_ICLASS_PSHUFW, + XED_ICLASS_PSIGNB, + XED_ICLASS_PSIGND, + XED_ICLASS_PSIGNW, + XED_ICLASS_PSLLD, + XED_ICLASS_PSLLDQ, + XED_ICLASS_PSLLQ, + XED_ICLASS_PSLLW, + XED_ICLASS_PSMASH, + XED_ICLASS_PSRAD, + XED_ICLASS_PSRAW, + XED_ICLASS_PSRLD, + XED_ICLASS_PSRLDQ, + XED_ICLASS_PSRLQ, + XED_ICLASS_PSRLW, + XED_ICLASS_PSUBB, + XED_ICLASS_PSUBD, + XED_ICLASS_PSUBQ, + XED_ICLASS_PSUBSB, + XED_ICLASS_PSUBSW, + XED_ICLASS_PSUBUSB, + XED_ICLASS_PSUBUSW, + XED_ICLASS_PSUBW, + XED_ICLASS_PSWAPD, + XED_ICLASS_PTEST, + XED_ICLASS_PTWRITE, + XED_ICLASS_PUNPCKHBW, + XED_ICLASS_PUNPCKHDQ, + XED_ICLASS_PUNPCKHQDQ, + XED_ICLASS_PUNPCKHWD, + XED_ICLASS_PUNPCKLBW, + XED_ICLASS_PUNPCKLDQ, + XED_ICLASS_PUNPCKLQDQ, + XED_ICLASS_PUNPCKLWD, + XED_ICLASS_PUSH, + XED_ICLASS_PUSHA, + XED_ICLASS_PUSHAD, + XED_ICLASS_PUSHF, + XED_ICLASS_PUSHFD, + XED_ICLASS_PUSHFQ, + XED_ICLASS_PVALIDATE, + XED_ICLASS_PXOR, + XED_ICLASS_RCL, + XED_ICLASS_RCPPS, + XED_ICLASS_RCPSS, + XED_ICLASS_RCR, + XED_ICLASS_RDFSBASE, + XED_ICLASS_RDGSBASE, + XED_ICLASS_RDMSR, + XED_ICLASS_RDPID, + XED_ICLASS_RDPKRU, + XED_ICLASS_RDPMC, + XED_ICLASS_RDPRU, + XED_ICLASS_RDRAND, + XED_ICLASS_RDSEED, + XED_ICLASS_RDSSPD, + XED_ICLASS_RDSSPQ, + XED_ICLASS_RDTSC, + XED_ICLASS_RDTSCP, + XED_ICLASS_REPE_CMPSB, + XED_ICLASS_REPE_CMPSD, + XED_ICLASS_REPE_CMPSQ, + XED_ICLASS_REPE_CMPSW, + XED_ICLASS_REPE_SCASB, + XED_ICLASS_REPE_SCASD, + XED_ICLASS_REPE_SCASQ, + XED_ICLASS_REPE_SCASW, + XED_ICLASS_REPNE_CMPSB, + XED_ICLASS_REPNE_CMPSD, + XED_ICLASS_REPNE_CMPSQ, + XED_ICLASS_REPNE_CMPSW, + XED_ICLASS_REPNE_SCASB, + XED_ICLASS_REPNE_SCASD, + XED_ICLASS_REPNE_SCASQ, + XED_ICLASS_REPNE_SCASW, + XED_ICLASS_REP_INSB, + XED_ICLASS_REP_INSD, + XED_ICLASS_REP_INSW, + XED_ICLASS_REP_LODSB, + XED_ICLASS_REP_LODSD, + XED_ICLASS_REP_LODSQ, + XED_ICLASS_REP_LODSW, + XED_ICLASS_REP_MONTMUL, + XED_ICLASS_REP_MOVSB, + XED_ICLASS_REP_MOVSD, + XED_ICLASS_REP_MOVSQ, + XED_ICLASS_REP_MOVSW, + XED_ICLASS_REP_OUTSB, + XED_ICLASS_REP_OUTSD, + XED_ICLASS_REP_OUTSW, + XED_ICLASS_REP_STOSB, + XED_ICLASS_REP_STOSD, + XED_ICLASS_REP_STOSQ, + XED_ICLASS_REP_STOSW, + XED_ICLASS_REP_XCRYPTCBC, + XED_ICLASS_REP_XCRYPTCFB, + XED_ICLASS_REP_XCRYPTCTR, + XED_ICLASS_REP_XCRYPTECB, + XED_ICLASS_REP_XCRYPTOFB, + XED_ICLASS_REP_XSHA1, + XED_ICLASS_REP_XSHA256, + XED_ICLASS_REP_XSTORE, + XED_ICLASS_RET_FAR, + XED_ICLASS_RET_NEAR, + XED_ICLASS_RMPADJUST, + XED_ICLASS_RMPUPDATE, + XED_ICLASS_ROL, + XED_ICLASS_ROR, + XED_ICLASS_RORX, + XED_ICLASS_ROUNDPD, + XED_ICLASS_ROUNDPS, + XED_ICLASS_ROUNDSD, + XED_ICLASS_ROUNDSS, + XED_ICLASS_RSM, + XED_ICLASS_RSQRTPS, + XED_ICLASS_RSQRTSS, + XED_ICLASS_RSTORSSP, + XED_ICLASS_SAHF, + XED_ICLASS_SALC, + XED_ICLASS_SAR, + XED_ICLASS_SARX, + XED_ICLASS_SAVEPREVSSP, + XED_ICLASS_SBB, + XED_ICLASS_SBB_LOCK, + XED_ICLASS_SCASB, + XED_ICLASS_SCASD, + XED_ICLASS_SCASQ, + XED_ICLASS_SCASW, + XED_ICLASS_SEAMCALL, + XED_ICLASS_SEAMOPS, + XED_ICLASS_SEAMRET, + XED_ICLASS_SENDUIPI, + XED_ICLASS_SERIALIZE, + XED_ICLASS_SETB, + XED_ICLASS_SETBE, + XED_ICLASS_SETL, + XED_ICLASS_SETLE, + XED_ICLASS_SETNB, + XED_ICLASS_SETNBE, + XED_ICLASS_SETNL, + XED_ICLASS_SETNLE, + XED_ICLASS_SETNO, + XED_ICLASS_SETNP, + XED_ICLASS_SETNS, + XED_ICLASS_SETNZ, + XED_ICLASS_SETO, + XED_ICLASS_SETP, + XED_ICLASS_SETS, + XED_ICLASS_SETSSBSY, + XED_ICLASS_SETZ, + XED_ICLASS_SFENCE, + XED_ICLASS_SGDT, + XED_ICLASS_SHA1MSG1, + XED_ICLASS_SHA1MSG2, + XED_ICLASS_SHA1NEXTE, + XED_ICLASS_SHA1RNDS4, + XED_ICLASS_SHA256MSG1, + XED_ICLASS_SHA256MSG2, + XED_ICLASS_SHA256RNDS2, + XED_ICLASS_SHL, + XED_ICLASS_SHLD, + XED_ICLASS_SHLX, + XED_ICLASS_SHR, + XED_ICLASS_SHRD, + XED_ICLASS_SHRX, + XED_ICLASS_SHUFPD, + XED_ICLASS_SHUFPS, + XED_ICLASS_SIDT, + XED_ICLASS_SKINIT, + XED_ICLASS_SLDT, + XED_ICLASS_SLWPCB, + XED_ICLASS_SMSW, + XED_ICLASS_SQRTPD, + XED_ICLASS_SQRTPS, + XED_ICLASS_SQRTSD, + XED_ICLASS_SQRTSS, + XED_ICLASS_STAC, + XED_ICLASS_STC, + XED_ICLASS_STD, + XED_ICLASS_STGI, + XED_ICLASS_STI, + XED_ICLASS_STMXCSR, + XED_ICLASS_STOSB, + XED_ICLASS_STOSD, + XED_ICLASS_STOSQ, + XED_ICLASS_STOSW, + XED_ICLASS_STR, + XED_ICLASS_STTILECFG, + XED_ICLASS_STUI, + XED_ICLASS_SUB, + XED_ICLASS_SUBPD, + XED_ICLASS_SUBPS, + XED_ICLASS_SUBSD, + XED_ICLASS_SUBSS, + XED_ICLASS_SUB_LOCK, + XED_ICLASS_SWAPGS, + XED_ICLASS_SYSCALL, + XED_ICLASS_SYSCALL_AMD, + XED_ICLASS_SYSENTER, + XED_ICLASS_SYSEXIT, + XED_ICLASS_SYSRET, + XED_ICLASS_SYSRET64, + XED_ICLASS_SYSRET_AMD, + XED_ICLASS_T1MSKC, + XED_ICLASS_TDCALL, + XED_ICLASS_TDPBF16PS, + XED_ICLASS_TDPBSSD, + XED_ICLASS_TDPBSUD, + XED_ICLASS_TDPBUSD, + XED_ICLASS_TDPBUUD, + XED_ICLASS_TEST, + XED_ICLASS_TESTUI, + XED_ICLASS_TILELOADD, + XED_ICLASS_TILELOADDT1, + XED_ICLASS_TILERELEASE, + XED_ICLASS_TILESTORED, + XED_ICLASS_TILEZERO, + XED_ICLASS_TLBSYNC, + XED_ICLASS_TPAUSE, + XED_ICLASS_TZCNT, + XED_ICLASS_TZMSK, + XED_ICLASS_UCOMISD, + XED_ICLASS_UCOMISS, + XED_ICLASS_UD0, + XED_ICLASS_UD1, + XED_ICLASS_UD2, + XED_ICLASS_UIRET, + XED_ICLASS_UMONITOR, + XED_ICLASS_UMWAIT, + XED_ICLASS_UNPCKHPD, + XED_ICLASS_UNPCKHPS, + XED_ICLASS_UNPCKLPD, + XED_ICLASS_UNPCKLPS, + XED_ICLASS_V4FMADDPS, + XED_ICLASS_V4FMADDSS, + XED_ICLASS_V4FNMADDPS, + XED_ICLASS_V4FNMADDSS, + XED_ICLASS_VADDPD, + XED_ICLASS_VADDPH, + XED_ICLASS_VADDPS, + XED_ICLASS_VADDSD, + XED_ICLASS_VADDSH, + XED_ICLASS_VADDSS, + XED_ICLASS_VADDSUBPD, + XED_ICLASS_VADDSUBPS, + XED_ICLASS_VAESDEC, + XED_ICLASS_VAESDECLAST, + XED_ICLASS_VAESENC, + XED_ICLASS_VAESENCLAST, + XED_ICLASS_VAESIMC, + XED_ICLASS_VAESKEYGENASSIST, + XED_ICLASS_VALIGND, + XED_ICLASS_VALIGNQ, + XED_ICLASS_VANDNPD, + XED_ICLASS_VANDNPS, + XED_ICLASS_VANDPD, + XED_ICLASS_VANDPS, + XED_ICLASS_VBLENDMPD, + XED_ICLASS_VBLENDMPS, + XED_ICLASS_VBLENDPD, + XED_ICLASS_VBLENDPS, + XED_ICLASS_VBLENDVPD, + XED_ICLASS_VBLENDVPS, + XED_ICLASS_VBROADCASTF128, + XED_ICLASS_VBROADCASTF32X2, + XED_ICLASS_VBROADCASTF32X4, + XED_ICLASS_VBROADCASTF32X8, + XED_ICLASS_VBROADCASTF64X2, + XED_ICLASS_VBROADCASTF64X4, + XED_ICLASS_VBROADCASTI128, + XED_ICLASS_VBROADCASTI32X2, + XED_ICLASS_VBROADCASTI32X4, + XED_ICLASS_VBROADCASTI32X8, + XED_ICLASS_VBROADCASTI64X2, + XED_ICLASS_VBROADCASTI64X4, + XED_ICLASS_VBROADCASTSD, + XED_ICLASS_VBROADCASTSS, + XED_ICLASS_VCMPPD, + XED_ICLASS_VCMPPH, + XED_ICLASS_VCMPPS, + XED_ICLASS_VCMPSD, + XED_ICLASS_VCMPSH, + XED_ICLASS_VCMPSS, + XED_ICLASS_VCOMISD, + XED_ICLASS_VCOMISH, + XED_ICLASS_VCOMISS, + XED_ICLASS_VCOMPRESSPD, + XED_ICLASS_VCOMPRESSPS, + XED_ICLASS_VCVTDQ2PD, + XED_ICLASS_VCVTDQ2PH, + XED_ICLASS_VCVTDQ2PS, + XED_ICLASS_VCVTNE2PS2BF16, + XED_ICLASS_VCVTNEPS2BF16, + XED_ICLASS_VCVTPD2DQ, + XED_ICLASS_VCVTPD2PH, + XED_ICLASS_VCVTPD2PS, + XED_ICLASS_VCVTPD2QQ, + XED_ICLASS_VCVTPD2UDQ, + XED_ICLASS_VCVTPD2UQQ, + XED_ICLASS_VCVTPH2DQ, + XED_ICLASS_VCVTPH2PD, + XED_ICLASS_VCVTPH2PS, + XED_ICLASS_VCVTPH2PSX, + XED_ICLASS_VCVTPH2QQ, + XED_ICLASS_VCVTPH2UDQ, + XED_ICLASS_VCVTPH2UQQ, + XED_ICLASS_VCVTPH2UW, + XED_ICLASS_VCVTPH2W, + XED_ICLASS_VCVTPS2DQ, + XED_ICLASS_VCVTPS2PD, + XED_ICLASS_VCVTPS2PH, + XED_ICLASS_VCVTPS2PHX, + XED_ICLASS_VCVTPS2QQ, + XED_ICLASS_VCVTPS2UDQ, + XED_ICLASS_VCVTPS2UQQ, + XED_ICLASS_VCVTQQ2PD, + XED_ICLASS_VCVTQQ2PH, + XED_ICLASS_VCVTQQ2PS, + XED_ICLASS_VCVTSD2SH, + XED_ICLASS_VCVTSD2SI, + XED_ICLASS_VCVTSD2SS, + XED_ICLASS_VCVTSD2USI, + XED_ICLASS_VCVTSH2SD, + XED_ICLASS_VCVTSH2SI, + XED_ICLASS_VCVTSH2SS, + XED_ICLASS_VCVTSH2USI, + XED_ICLASS_VCVTSI2SD, + XED_ICLASS_VCVTSI2SH, + XED_ICLASS_VCVTSI2SS, + XED_ICLASS_VCVTSS2SD, + XED_ICLASS_VCVTSS2SH, + XED_ICLASS_VCVTSS2SI, + XED_ICLASS_VCVTSS2USI, + XED_ICLASS_VCVTTPD2DQ, + XED_ICLASS_VCVTTPD2QQ, + XED_ICLASS_VCVTTPD2UDQ, + XED_ICLASS_VCVTTPD2UQQ, + XED_ICLASS_VCVTTPH2DQ, + XED_ICLASS_VCVTTPH2QQ, + XED_ICLASS_VCVTTPH2UDQ, + XED_ICLASS_VCVTTPH2UQQ, + XED_ICLASS_VCVTTPH2UW, + XED_ICLASS_VCVTTPH2W, + XED_ICLASS_VCVTTPS2DQ, + XED_ICLASS_VCVTTPS2QQ, + XED_ICLASS_VCVTTPS2UDQ, + XED_ICLASS_VCVTTPS2UQQ, + XED_ICLASS_VCVTTSD2SI, + XED_ICLASS_VCVTTSD2USI, + XED_ICLASS_VCVTTSH2SI, + XED_ICLASS_VCVTTSH2USI, + XED_ICLASS_VCVTTSS2SI, + XED_ICLASS_VCVTTSS2USI, + XED_ICLASS_VCVTUDQ2PD, + XED_ICLASS_VCVTUDQ2PH, + XED_ICLASS_VCVTUDQ2PS, + XED_ICLASS_VCVTUQQ2PD, + XED_ICLASS_VCVTUQQ2PH, + XED_ICLASS_VCVTUQQ2PS, + XED_ICLASS_VCVTUSI2SD, + XED_ICLASS_VCVTUSI2SH, + XED_ICLASS_VCVTUSI2SS, + XED_ICLASS_VCVTUW2PH, + XED_ICLASS_VCVTW2PH, + XED_ICLASS_VDBPSADBW, + XED_ICLASS_VDIVPD, + XED_ICLASS_VDIVPH, + XED_ICLASS_VDIVPS, + XED_ICLASS_VDIVSD, + XED_ICLASS_VDIVSH, + XED_ICLASS_VDIVSS, + XED_ICLASS_VDPBF16PS, + XED_ICLASS_VDPPD, + XED_ICLASS_VDPPS, + XED_ICLASS_VERR, + XED_ICLASS_VERW, + XED_ICLASS_VEXP2PD, + XED_ICLASS_VEXP2PS, + XED_ICLASS_VEXPANDPD, + XED_ICLASS_VEXPANDPS, + XED_ICLASS_VEXTRACTF128, + XED_ICLASS_VEXTRACTF32X4, + XED_ICLASS_VEXTRACTF32X8, + XED_ICLASS_VEXTRACTF64X2, + XED_ICLASS_VEXTRACTF64X4, + XED_ICLASS_VEXTRACTI128, + XED_ICLASS_VEXTRACTI32X4, + XED_ICLASS_VEXTRACTI32X8, + XED_ICLASS_VEXTRACTI64X2, + XED_ICLASS_VEXTRACTI64X4, + XED_ICLASS_VEXTRACTPS, + XED_ICLASS_VFCMADDCPH, + XED_ICLASS_VFCMADDCSH, + XED_ICLASS_VFCMULCPH, + XED_ICLASS_VFCMULCSH, + XED_ICLASS_VFIXUPIMMPD, + XED_ICLASS_VFIXUPIMMPS, + XED_ICLASS_VFIXUPIMMSD, + XED_ICLASS_VFIXUPIMMSS, + XED_ICLASS_VFMADD132PD, + XED_ICLASS_VFMADD132PH, + XED_ICLASS_VFMADD132PS, + XED_ICLASS_VFMADD132SD, + XED_ICLASS_VFMADD132SH, + XED_ICLASS_VFMADD132SS, + XED_ICLASS_VFMADD213PD, + XED_ICLASS_VFMADD213PH, + XED_ICLASS_VFMADD213PS, + XED_ICLASS_VFMADD213SD, + XED_ICLASS_VFMADD213SH, + XED_ICLASS_VFMADD213SS, + XED_ICLASS_VFMADD231PD, + XED_ICLASS_VFMADD231PH, + XED_ICLASS_VFMADD231PS, + XED_ICLASS_VFMADD231SD, + XED_ICLASS_VFMADD231SH, + XED_ICLASS_VFMADD231SS, + XED_ICLASS_VFMADDCPH, + XED_ICLASS_VFMADDCSH, + XED_ICLASS_VFMADDPD, + XED_ICLASS_VFMADDPS, + XED_ICLASS_VFMADDSD, + XED_ICLASS_VFMADDSS, + XED_ICLASS_VFMADDSUB132PD, + XED_ICLASS_VFMADDSUB132PH, + XED_ICLASS_VFMADDSUB132PS, + XED_ICLASS_VFMADDSUB213PD, + XED_ICLASS_VFMADDSUB213PH, + XED_ICLASS_VFMADDSUB213PS, + XED_ICLASS_VFMADDSUB231PD, + XED_ICLASS_VFMADDSUB231PH, + XED_ICLASS_VFMADDSUB231PS, + XED_ICLASS_VFMADDSUBPD, + XED_ICLASS_VFMADDSUBPS, + XED_ICLASS_VFMSUB132PD, + XED_ICLASS_VFMSUB132PH, + XED_ICLASS_VFMSUB132PS, + XED_ICLASS_VFMSUB132SD, + XED_ICLASS_VFMSUB132SH, + XED_ICLASS_VFMSUB132SS, + XED_ICLASS_VFMSUB213PD, + XED_ICLASS_VFMSUB213PH, + XED_ICLASS_VFMSUB213PS, + XED_ICLASS_VFMSUB213SD, + XED_ICLASS_VFMSUB213SH, + XED_ICLASS_VFMSUB213SS, + XED_ICLASS_VFMSUB231PD, + XED_ICLASS_VFMSUB231PH, + XED_ICLASS_VFMSUB231PS, + XED_ICLASS_VFMSUB231SD, + XED_ICLASS_VFMSUB231SH, + XED_ICLASS_VFMSUB231SS, + XED_ICLASS_VFMSUBADD132PD, + XED_ICLASS_VFMSUBADD132PH, + XED_ICLASS_VFMSUBADD132PS, + XED_ICLASS_VFMSUBADD213PD, + XED_ICLASS_VFMSUBADD213PH, + XED_ICLASS_VFMSUBADD213PS, + XED_ICLASS_VFMSUBADD231PD, + XED_ICLASS_VFMSUBADD231PH, + XED_ICLASS_VFMSUBADD231PS, + XED_ICLASS_VFMSUBADDPD, + XED_ICLASS_VFMSUBADDPS, + XED_ICLASS_VFMSUBPD, + XED_ICLASS_VFMSUBPS, + XED_ICLASS_VFMSUBSD, + XED_ICLASS_VFMSUBSS, + XED_ICLASS_VFMULCPH, + XED_ICLASS_VFMULCSH, + XED_ICLASS_VFNMADD132PD, + XED_ICLASS_VFNMADD132PH, + XED_ICLASS_VFNMADD132PS, + XED_ICLASS_VFNMADD132SD, + XED_ICLASS_VFNMADD132SH, + XED_ICLASS_VFNMADD132SS, + XED_ICLASS_VFNMADD213PD, + XED_ICLASS_VFNMADD213PH, + XED_ICLASS_VFNMADD213PS, + XED_ICLASS_VFNMADD213SD, + XED_ICLASS_VFNMADD213SH, + XED_ICLASS_VFNMADD213SS, + XED_ICLASS_VFNMADD231PD, + XED_ICLASS_VFNMADD231PH, + XED_ICLASS_VFNMADD231PS, + XED_ICLASS_VFNMADD231SD, + XED_ICLASS_VFNMADD231SH, + XED_ICLASS_VFNMADD231SS, + XED_ICLASS_VFNMADDPD, + XED_ICLASS_VFNMADDPS, + XED_ICLASS_VFNMADDSD, + XED_ICLASS_VFNMADDSS, + XED_ICLASS_VFNMSUB132PD, + XED_ICLASS_VFNMSUB132PH, + XED_ICLASS_VFNMSUB132PS, + XED_ICLASS_VFNMSUB132SD, + XED_ICLASS_VFNMSUB132SH, + XED_ICLASS_VFNMSUB132SS, + XED_ICLASS_VFNMSUB213PD, + XED_ICLASS_VFNMSUB213PH, + XED_ICLASS_VFNMSUB213PS, + XED_ICLASS_VFNMSUB213SD, + XED_ICLASS_VFNMSUB213SH, + XED_ICLASS_VFNMSUB213SS, + XED_ICLASS_VFNMSUB231PD, + XED_ICLASS_VFNMSUB231PH, + XED_ICLASS_VFNMSUB231PS, + XED_ICLASS_VFNMSUB231SD, + XED_ICLASS_VFNMSUB231SH, + XED_ICLASS_VFNMSUB231SS, + XED_ICLASS_VFNMSUBPD, + XED_ICLASS_VFNMSUBPS, + XED_ICLASS_VFNMSUBSD, + XED_ICLASS_VFNMSUBSS, + XED_ICLASS_VFPCLASSPD, + XED_ICLASS_VFPCLASSPH, + XED_ICLASS_VFPCLASSPS, + XED_ICLASS_VFPCLASSSD, + XED_ICLASS_VFPCLASSSH, + XED_ICLASS_VFPCLASSSS, + XED_ICLASS_VFRCZPD, + XED_ICLASS_VFRCZPS, + XED_ICLASS_VFRCZSD, + XED_ICLASS_VFRCZSS, + XED_ICLASS_VGATHERDPD, + XED_ICLASS_VGATHERDPS, + XED_ICLASS_VGATHERPF0DPD, + XED_ICLASS_VGATHERPF0DPS, + XED_ICLASS_VGATHERPF0QPD, + XED_ICLASS_VGATHERPF0QPS, + XED_ICLASS_VGATHERPF1DPD, + XED_ICLASS_VGATHERPF1DPS, + XED_ICLASS_VGATHERPF1QPD, + XED_ICLASS_VGATHERPF1QPS, + XED_ICLASS_VGATHERQPD, + XED_ICLASS_VGATHERQPS, + XED_ICLASS_VGETEXPPD, + XED_ICLASS_VGETEXPPH, + XED_ICLASS_VGETEXPPS, + XED_ICLASS_VGETEXPSD, + XED_ICLASS_VGETEXPSH, + XED_ICLASS_VGETEXPSS, + XED_ICLASS_VGETMANTPD, + XED_ICLASS_VGETMANTPH, + XED_ICLASS_VGETMANTPS, + XED_ICLASS_VGETMANTSD, + XED_ICLASS_VGETMANTSH, + XED_ICLASS_VGETMANTSS, + XED_ICLASS_VGF2P8AFFINEINVQB, + XED_ICLASS_VGF2P8AFFINEQB, + XED_ICLASS_VGF2P8MULB, + XED_ICLASS_VHADDPD, + XED_ICLASS_VHADDPS, + XED_ICLASS_VHSUBPD, + XED_ICLASS_VHSUBPS, + XED_ICLASS_VINSERTF128, + XED_ICLASS_VINSERTF32X4, + XED_ICLASS_VINSERTF32X8, + XED_ICLASS_VINSERTF64X2, + XED_ICLASS_VINSERTF64X4, + XED_ICLASS_VINSERTI128, + XED_ICLASS_VINSERTI32X4, + XED_ICLASS_VINSERTI32X8, + XED_ICLASS_VINSERTI64X2, + XED_ICLASS_VINSERTI64X4, + XED_ICLASS_VINSERTPS, + XED_ICLASS_VLDDQU, + XED_ICLASS_VLDMXCSR, + XED_ICLASS_VMASKMOVDQU, + XED_ICLASS_VMASKMOVPD, + XED_ICLASS_VMASKMOVPS, + XED_ICLASS_VMAXPD, + XED_ICLASS_VMAXPH, + XED_ICLASS_VMAXPS, + XED_ICLASS_VMAXSD, + XED_ICLASS_VMAXSH, + XED_ICLASS_VMAXSS, + XED_ICLASS_VMCALL, + XED_ICLASS_VMCLEAR, + XED_ICLASS_VMFUNC, + XED_ICLASS_VMINPD, + XED_ICLASS_VMINPH, + XED_ICLASS_VMINPS, + XED_ICLASS_VMINSD, + XED_ICLASS_VMINSH, + XED_ICLASS_VMINSS, + XED_ICLASS_VMLAUNCH, + XED_ICLASS_VMLOAD, + XED_ICLASS_VMMCALL, + XED_ICLASS_VMOVAPD, + XED_ICLASS_VMOVAPS, + XED_ICLASS_VMOVD, + XED_ICLASS_VMOVDDUP, + XED_ICLASS_VMOVDQA, + XED_ICLASS_VMOVDQA32, + XED_ICLASS_VMOVDQA64, + XED_ICLASS_VMOVDQU, + XED_ICLASS_VMOVDQU16, + XED_ICLASS_VMOVDQU32, + XED_ICLASS_VMOVDQU64, + XED_ICLASS_VMOVDQU8, + XED_ICLASS_VMOVHLPS, + XED_ICLASS_VMOVHPD, + XED_ICLASS_VMOVHPS, + XED_ICLASS_VMOVLHPS, + XED_ICLASS_VMOVLPD, + XED_ICLASS_VMOVLPS, + XED_ICLASS_VMOVMSKPD, + XED_ICLASS_VMOVMSKPS, + XED_ICLASS_VMOVNTDQ, + XED_ICLASS_VMOVNTDQA, + XED_ICLASS_VMOVNTPD, + XED_ICLASS_VMOVNTPS, + XED_ICLASS_VMOVQ, + XED_ICLASS_VMOVSD, + XED_ICLASS_VMOVSH, + XED_ICLASS_VMOVSHDUP, + XED_ICLASS_VMOVSLDUP, + XED_ICLASS_VMOVSS, + XED_ICLASS_VMOVUPD, + XED_ICLASS_VMOVUPS, + XED_ICLASS_VMOVW, + XED_ICLASS_VMPSADBW, + XED_ICLASS_VMPTRLD, + XED_ICLASS_VMPTRST, + XED_ICLASS_VMREAD, + XED_ICLASS_VMRESUME, + XED_ICLASS_VMRUN, + XED_ICLASS_VMSAVE, + XED_ICLASS_VMULPD, + XED_ICLASS_VMULPH, + XED_ICLASS_VMULPS, + XED_ICLASS_VMULSD, + XED_ICLASS_VMULSH, + XED_ICLASS_VMULSS, + XED_ICLASS_VMWRITE, + XED_ICLASS_VMXOFF, + XED_ICLASS_VMXON, + XED_ICLASS_VORPD, + XED_ICLASS_VORPS, + XED_ICLASS_VP2INTERSECTD, + XED_ICLASS_VP2INTERSECTQ, + XED_ICLASS_VP4DPWSSD, + XED_ICLASS_VP4DPWSSDS, + XED_ICLASS_VPABSB, + XED_ICLASS_VPABSD, + XED_ICLASS_VPABSQ, + XED_ICLASS_VPABSW, + XED_ICLASS_VPACKSSDW, + XED_ICLASS_VPACKSSWB, + XED_ICLASS_VPACKUSDW, + XED_ICLASS_VPACKUSWB, + XED_ICLASS_VPADDB, + XED_ICLASS_VPADDD, + XED_ICLASS_VPADDQ, + XED_ICLASS_VPADDSB, + XED_ICLASS_VPADDSW, + XED_ICLASS_VPADDUSB, + XED_ICLASS_VPADDUSW, + XED_ICLASS_VPADDW, + XED_ICLASS_VPALIGNR, + XED_ICLASS_VPAND, + XED_ICLASS_VPANDD, + XED_ICLASS_VPANDN, + XED_ICLASS_VPANDND, + XED_ICLASS_VPANDNQ, + XED_ICLASS_VPANDQ, + XED_ICLASS_VPAVGB, + XED_ICLASS_VPAVGW, + XED_ICLASS_VPBLENDD, + XED_ICLASS_VPBLENDMB, + XED_ICLASS_VPBLENDMD, + XED_ICLASS_VPBLENDMQ, + XED_ICLASS_VPBLENDMW, + XED_ICLASS_VPBLENDVB, + XED_ICLASS_VPBLENDW, + XED_ICLASS_VPBROADCASTB, + XED_ICLASS_VPBROADCASTD, + XED_ICLASS_VPBROADCASTMB2Q, + XED_ICLASS_VPBROADCASTMW2D, + XED_ICLASS_VPBROADCASTQ, + XED_ICLASS_VPBROADCASTW, + XED_ICLASS_VPCLMULQDQ, + XED_ICLASS_VPCMOV, + XED_ICLASS_VPCMPB, + XED_ICLASS_VPCMPD, + XED_ICLASS_VPCMPEQB, + XED_ICLASS_VPCMPEQD, + XED_ICLASS_VPCMPEQQ, + XED_ICLASS_VPCMPEQW, + XED_ICLASS_VPCMPESTRI, + XED_ICLASS_VPCMPESTRI64, + XED_ICLASS_VPCMPESTRM, + XED_ICLASS_VPCMPESTRM64, + XED_ICLASS_VPCMPGTB, + XED_ICLASS_VPCMPGTD, + XED_ICLASS_VPCMPGTQ, + XED_ICLASS_VPCMPGTW, + XED_ICLASS_VPCMPISTRI, + XED_ICLASS_VPCMPISTRI64, + XED_ICLASS_VPCMPISTRM, + XED_ICLASS_VPCMPQ, + XED_ICLASS_VPCMPUB, + XED_ICLASS_VPCMPUD, + XED_ICLASS_VPCMPUQ, + XED_ICLASS_VPCMPUW, + XED_ICLASS_VPCMPW, + XED_ICLASS_VPCOMB, + XED_ICLASS_VPCOMD, + XED_ICLASS_VPCOMPRESSB, + XED_ICLASS_VPCOMPRESSD, + XED_ICLASS_VPCOMPRESSQ, + XED_ICLASS_VPCOMPRESSW, + XED_ICLASS_VPCOMQ, + XED_ICLASS_VPCOMUB, + XED_ICLASS_VPCOMUD, + XED_ICLASS_VPCOMUQ, + XED_ICLASS_VPCOMUW, + XED_ICLASS_VPCOMW, + XED_ICLASS_VPCONFLICTD, + XED_ICLASS_VPCONFLICTQ, + XED_ICLASS_VPDPBUSD, + XED_ICLASS_VPDPBUSDS, + XED_ICLASS_VPDPWSSD, + XED_ICLASS_VPDPWSSDS, + XED_ICLASS_VPERM2F128, + XED_ICLASS_VPERM2I128, + XED_ICLASS_VPERMB, + XED_ICLASS_VPERMD, + XED_ICLASS_VPERMI2B, + XED_ICLASS_VPERMI2D, + XED_ICLASS_VPERMI2PD, + XED_ICLASS_VPERMI2PS, + XED_ICLASS_VPERMI2Q, + XED_ICLASS_VPERMI2W, + XED_ICLASS_VPERMIL2PD, + XED_ICLASS_VPERMIL2PS, + XED_ICLASS_VPERMILPD, + XED_ICLASS_VPERMILPS, + XED_ICLASS_VPERMPD, + XED_ICLASS_VPERMPS, + XED_ICLASS_VPERMQ, + XED_ICLASS_VPERMT2B, + XED_ICLASS_VPERMT2D, + XED_ICLASS_VPERMT2PD, + XED_ICLASS_VPERMT2PS, + XED_ICLASS_VPERMT2Q, + XED_ICLASS_VPERMT2W, + XED_ICLASS_VPERMW, + XED_ICLASS_VPEXPANDB, + XED_ICLASS_VPEXPANDD, + XED_ICLASS_VPEXPANDQ, + XED_ICLASS_VPEXPANDW, + XED_ICLASS_VPEXTRB, + XED_ICLASS_VPEXTRD, + XED_ICLASS_VPEXTRQ, + XED_ICLASS_VPEXTRW, + XED_ICLASS_VPEXTRW_C5, + XED_ICLASS_VPGATHERDD, + XED_ICLASS_VPGATHERDQ, + XED_ICLASS_VPGATHERQD, + XED_ICLASS_VPGATHERQQ, + XED_ICLASS_VPHADDBD, + XED_ICLASS_VPHADDBQ, + XED_ICLASS_VPHADDBW, + XED_ICLASS_VPHADDD, + XED_ICLASS_VPHADDDQ, + XED_ICLASS_VPHADDSW, + XED_ICLASS_VPHADDUBD, + XED_ICLASS_VPHADDUBQ, + XED_ICLASS_VPHADDUBW, + XED_ICLASS_VPHADDUDQ, + XED_ICLASS_VPHADDUWD, + XED_ICLASS_VPHADDUWQ, + XED_ICLASS_VPHADDW, + XED_ICLASS_VPHADDWD, + XED_ICLASS_VPHADDWQ, + XED_ICLASS_VPHMINPOSUW, + XED_ICLASS_VPHSUBBW, + XED_ICLASS_VPHSUBD, + XED_ICLASS_VPHSUBDQ, + XED_ICLASS_VPHSUBSW, + XED_ICLASS_VPHSUBW, + XED_ICLASS_VPHSUBWD, + XED_ICLASS_VPINSRB, + XED_ICLASS_VPINSRD, + XED_ICLASS_VPINSRQ, + XED_ICLASS_VPINSRW, + XED_ICLASS_VPLZCNTD, + XED_ICLASS_VPLZCNTQ, + XED_ICLASS_VPMACSDD, + XED_ICLASS_VPMACSDQH, + XED_ICLASS_VPMACSDQL, + XED_ICLASS_VPMACSSDD, + XED_ICLASS_VPMACSSDQH, + XED_ICLASS_VPMACSSDQL, + XED_ICLASS_VPMACSSWD, + XED_ICLASS_VPMACSSWW, + XED_ICLASS_VPMACSWD, + XED_ICLASS_VPMACSWW, + XED_ICLASS_VPMADCSSWD, + XED_ICLASS_VPMADCSWD, + XED_ICLASS_VPMADD52HUQ, + XED_ICLASS_VPMADD52LUQ, + XED_ICLASS_VPMADDUBSW, + XED_ICLASS_VPMADDWD, + XED_ICLASS_VPMASKMOVD, + XED_ICLASS_VPMASKMOVQ, + XED_ICLASS_VPMAXSB, + XED_ICLASS_VPMAXSD, + XED_ICLASS_VPMAXSQ, + XED_ICLASS_VPMAXSW, + XED_ICLASS_VPMAXUB, + XED_ICLASS_VPMAXUD, + XED_ICLASS_VPMAXUQ, + XED_ICLASS_VPMAXUW, + XED_ICLASS_VPMINSB, + XED_ICLASS_VPMINSD, + XED_ICLASS_VPMINSQ, + XED_ICLASS_VPMINSW, + XED_ICLASS_VPMINUB, + XED_ICLASS_VPMINUD, + XED_ICLASS_VPMINUQ, + XED_ICLASS_VPMINUW, + XED_ICLASS_VPMOVB2M, + XED_ICLASS_VPMOVD2M, + XED_ICLASS_VPMOVDB, + XED_ICLASS_VPMOVDW, + XED_ICLASS_VPMOVM2B, + XED_ICLASS_VPMOVM2D, + XED_ICLASS_VPMOVM2Q, + XED_ICLASS_VPMOVM2W, + XED_ICLASS_VPMOVMSKB, + XED_ICLASS_VPMOVQ2M, + XED_ICLASS_VPMOVQB, + XED_ICLASS_VPMOVQD, + XED_ICLASS_VPMOVQW, + XED_ICLASS_VPMOVSDB, + XED_ICLASS_VPMOVSDW, + XED_ICLASS_VPMOVSQB, + XED_ICLASS_VPMOVSQD, + XED_ICLASS_VPMOVSQW, + XED_ICLASS_VPMOVSWB, + XED_ICLASS_VPMOVSXBD, + XED_ICLASS_VPMOVSXBQ, + XED_ICLASS_VPMOVSXBW, + XED_ICLASS_VPMOVSXDQ, + XED_ICLASS_VPMOVSXWD, + XED_ICLASS_VPMOVSXWQ, + XED_ICLASS_VPMOVUSDB, + XED_ICLASS_VPMOVUSDW, + XED_ICLASS_VPMOVUSQB, + XED_ICLASS_VPMOVUSQD, + XED_ICLASS_VPMOVUSQW, + XED_ICLASS_VPMOVUSWB, + XED_ICLASS_VPMOVW2M, + XED_ICLASS_VPMOVWB, + XED_ICLASS_VPMOVZXBD, + XED_ICLASS_VPMOVZXBQ, + XED_ICLASS_VPMOVZXBW, + XED_ICLASS_VPMOVZXDQ, + XED_ICLASS_VPMOVZXWD, + XED_ICLASS_VPMOVZXWQ, + XED_ICLASS_VPMULDQ, + XED_ICLASS_VPMULHRSW, + XED_ICLASS_VPMULHUW, + XED_ICLASS_VPMULHW, + XED_ICLASS_VPMULLD, + XED_ICLASS_VPMULLQ, + XED_ICLASS_VPMULLW, + XED_ICLASS_VPMULTISHIFTQB, + XED_ICLASS_VPMULUDQ, + XED_ICLASS_VPOPCNTB, + XED_ICLASS_VPOPCNTD, + XED_ICLASS_VPOPCNTQ, + XED_ICLASS_VPOPCNTW, + XED_ICLASS_VPOR, + XED_ICLASS_VPORD, + XED_ICLASS_VPORQ, + XED_ICLASS_VPPERM, + XED_ICLASS_VPROLD, + XED_ICLASS_VPROLQ, + XED_ICLASS_VPROLVD, + XED_ICLASS_VPROLVQ, + XED_ICLASS_VPRORD, + XED_ICLASS_VPRORQ, + XED_ICLASS_VPRORVD, + XED_ICLASS_VPRORVQ, + XED_ICLASS_VPROTB, + XED_ICLASS_VPROTD, + XED_ICLASS_VPROTQ, + XED_ICLASS_VPROTW, + XED_ICLASS_VPSADBW, + XED_ICLASS_VPSCATTERDD, + XED_ICLASS_VPSCATTERDQ, + XED_ICLASS_VPSCATTERQD, + XED_ICLASS_VPSCATTERQQ, + XED_ICLASS_VPSHAB, + XED_ICLASS_VPSHAD, + XED_ICLASS_VPSHAQ, + XED_ICLASS_VPSHAW, + XED_ICLASS_VPSHLB, + XED_ICLASS_VPSHLD, + XED_ICLASS_VPSHLDD, + XED_ICLASS_VPSHLDQ, + XED_ICLASS_VPSHLDVD, + XED_ICLASS_VPSHLDVQ, + XED_ICLASS_VPSHLDVW, + XED_ICLASS_VPSHLDW, + XED_ICLASS_VPSHLQ, + XED_ICLASS_VPSHLW, + XED_ICLASS_VPSHRDD, + XED_ICLASS_VPSHRDQ, + XED_ICLASS_VPSHRDVD, + XED_ICLASS_VPSHRDVQ, + XED_ICLASS_VPSHRDVW, + XED_ICLASS_VPSHRDW, + XED_ICLASS_VPSHUFB, + XED_ICLASS_VPSHUFBITQMB, + XED_ICLASS_VPSHUFD, + XED_ICLASS_VPSHUFHW, + XED_ICLASS_VPSHUFLW, + XED_ICLASS_VPSIGNB, + XED_ICLASS_VPSIGND, + XED_ICLASS_VPSIGNW, + XED_ICLASS_VPSLLD, + XED_ICLASS_VPSLLDQ, + XED_ICLASS_VPSLLQ, + XED_ICLASS_VPSLLVD, + XED_ICLASS_VPSLLVQ, + XED_ICLASS_VPSLLVW, + XED_ICLASS_VPSLLW, + XED_ICLASS_VPSRAD, + XED_ICLASS_VPSRAQ, + XED_ICLASS_VPSRAVD, + XED_ICLASS_VPSRAVQ, + XED_ICLASS_VPSRAVW, + XED_ICLASS_VPSRAW, + XED_ICLASS_VPSRLD, + XED_ICLASS_VPSRLDQ, + XED_ICLASS_VPSRLQ, + XED_ICLASS_VPSRLVD, + XED_ICLASS_VPSRLVQ, + XED_ICLASS_VPSRLVW, + XED_ICLASS_VPSRLW, + XED_ICLASS_VPSUBB, + XED_ICLASS_VPSUBD, + XED_ICLASS_VPSUBQ, + XED_ICLASS_VPSUBSB, + XED_ICLASS_VPSUBSW, + XED_ICLASS_VPSUBUSB, + XED_ICLASS_VPSUBUSW, + XED_ICLASS_VPSUBW, + XED_ICLASS_VPTERNLOGD, + XED_ICLASS_VPTERNLOGQ, + XED_ICLASS_VPTEST, + XED_ICLASS_VPTESTMB, + XED_ICLASS_VPTESTMD, + XED_ICLASS_VPTESTMQ, + XED_ICLASS_VPTESTMW, + XED_ICLASS_VPTESTNMB, + XED_ICLASS_VPTESTNMD, + XED_ICLASS_VPTESTNMQ, + XED_ICLASS_VPTESTNMW, + XED_ICLASS_VPUNPCKHBW, + XED_ICLASS_VPUNPCKHDQ, + XED_ICLASS_VPUNPCKHQDQ, + XED_ICLASS_VPUNPCKHWD, + XED_ICLASS_VPUNPCKLBW, + XED_ICLASS_VPUNPCKLDQ, + XED_ICLASS_VPUNPCKLQDQ, + XED_ICLASS_VPUNPCKLWD, + XED_ICLASS_VPXOR, + XED_ICLASS_VPXORD, + XED_ICLASS_VPXORQ, + XED_ICLASS_VRANGEPD, + XED_ICLASS_VRANGEPS, + XED_ICLASS_VRANGESD, + XED_ICLASS_VRANGESS, + XED_ICLASS_VRCP14PD, + XED_ICLASS_VRCP14PS, + XED_ICLASS_VRCP14SD, + XED_ICLASS_VRCP14SS, + XED_ICLASS_VRCP28PD, + XED_ICLASS_VRCP28PS, + XED_ICLASS_VRCP28SD, + XED_ICLASS_VRCP28SS, + XED_ICLASS_VRCPPH, + XED_ICLASS_VRCPPS, + XED_ICLASS_VRCPSH, + XED_ICLASS_VRCPSS, + XED_ICLASS_VREDUCEPD, + XED_ICLASS_VREDUCEPH, + XED_ICLASS_VREDUCEPS, + XED_ICLASS_VREDUCESD, + XED_ICLASS_VREDUCESH, + XED_ICLASS_VREDUCESS, + XED_ICLASS_VRNDSCALEPD, + XED_ICLASS_VRNDSCALEPH, + XED_ICLASS_VRNDSCALEPS, + XED_ICLASS_VRNDSCALESD, + XED_ICLASS_VRNDSCALESH, + XED_ICLASS_VRNDSCALESS, + XED_ICLASS_VROUNDPD, + XED_ICLASS_VROUNDPS, + XED_ICLASS_VROUNDSD, + XED_ICLASS_VROUNDSS, + XED_ICLASS_VRSQRT14PD, + XED_ICLASS_VRSQRT14PS, + XED_ICLASS_VRSQRT14SD, + XED_ICLASS_VRSQRT14SS, + XED_ICLASS_VRSQRT28PD, + XED_ICLASS_VRSQRT28PS, + XED_ICLASS_VRSQRT28SD, + XED_ICLASS_VRSQRT28SS, + XED_ICLASS_VRSQRTPH, + XED_ICLASS_VRSQRTPS, + XED_ICLASS_VRSQRTSH, + XED_ICLASS_VRSQRTSS, + XED_ICLASS_VSCALEFPD, + XED_ICLASS_VSCALEFPH, + XED_ICLASS_VSCALEFPS, + XED_ICLASS_VSCALEFSD, + XED_ICLASS_VSCALEFSH, + XED_ICLASS_VSCALEFSS, + XED_ICLASS_VSCATTERDPD, + XED_ICLASS_VSCATTERDPS, + XED_ICLASS_VSCATTERPF0DPD, + XED_ICLASS_VSCATTERPF0DPS, + XED_ICLASS_VSCATTERPF0QPD, + XED_ICLASS_VSCATTERPF0QPS, + XED_ICLASS_VSCATTERPF1DPD, + XED_ICLASS_VSCATTERPF1DPS, + XED_ICLASS_VSCATTERPF1QPD, + XED_ICLASS_VSCATTERPF1QPS, + XED_ICLASS_VSCATTERQPD, + XED_ICLASS_VSCATTERQPS, + XED_ICLASS_VSHUFF32X4, + XED_ICLASS_VSHUFF64X2, + XED_ICLASS_VSHUFI32X4, + XED_ICLASS_VSHUFI64X2, + XED_ICLASS_VSHUFPD, + XED_ICLASS_VSHUFPS, + XED_ICLASS_VSQRTPD, + XED_ICLASS_VSQRTPH, + XED_ICLASS_VSQRTPS, + XED_ICLASS_VSQRTSD, + XED_ICLASS_VSQRTSH, + XED_ICLASS_VSQRTSS, + XED_ICLASS_VSTMXCSR, + XED_ICLASS_VSUBPD, + XED_ICLASS_VSUBPH, + XED_ICLASS_VSUBPS, + XED_ICLASS_VSUBSD, + XED_ICLASS_VSUBSH, + XED_ICLASS_VSUBSS, + XED_ICLASS_VTESTPD, + XED_ICLASS_VTESTPS, + XED_ICLASS_VUCOMISD, + XED_ICLASS_VUCOMISH, + XED_ICLASS_VUCOMISS, + XED_ICLASS_VUNPCKHPD, + XED_ICLASS_VUNPCKHPS, + XED_ICLASS_VUNPCKLPD, + XED_ICLASS_VUNPCKLPS, + XED_ICLASS_VXORPD, + XED_ICLASS_VXORPS, + XED_ICLASS_VZEROALL, + XED_ICLASS_VZEROUPPER, + XED_ICLASS_WBINVD, + XED_ICLASS_WBNOINVD, + XED_ICLASS_WRFSBASE, + XED_ICLASS_WRGSBASE, + XED_ICLASS_WRMSR, + XED_ICLASS_WRPKRU, + XED_ICLASS_WRSSD, + XED_ICLASS_WRSSQ, + XED_ICLASS_WRUSSD, + XED_ICLASS_WRUSSQ, + XED_ICLASS_XABORT, + XED_ICLASS_XADD, + XED_ICLASS_XADD_LOCK, + XED_ICLASS_XBEGIN, + XED_ICLASS_XCHG, + XED_ICLASS_XEND, + XED_ICLASS_XGETBV, + XED_ICLASS_XLAT, + XED_ICLASS_XOR, + XED_ICLASS_XORPD, + XED_ICLASS_XORPS, + XED_ICLASS_XOR_LOCK, + XED_ICLASS_XRESLDTRK, + XED_ICLASS_XRSTOR, + XED_ICLASS_XRSTOR64, + XED_ICLASS_XRSTORS, + XED_ICLASS_XRSTORS64, + XED_ICLASS_XSAVE, + XED_ICLASS_XSAVE64, + XED_ICLASS_XSAVEC, + XED_ICLASS_XSAVEC64, + XED_ICLASS_XSAVEOPT, + XED_ICLASS_XSAVEOPT64, + XED_ICLASS_XSAVES, + XED_ICLASS_XSAVES64, + XED_ICLASS_XSETBV, + XED_ICLASS_XSTORE, + XED_ICLASS_XSUSLDTRK, + XED_ICLASS_XTEST, + XED_ICLASS_LAST +} xed_iclass_enum_t; + +/// This converts strings to #xed_iclass_enum_t types. +/// @param s A C-string. +/// @return #xed_iclass_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_iclass_enum_t str2xed_iclass_enum_t(const char* s); +/// This converts strings to #xed_iclass_enum_t types. +/// @param p An enumeration element of type xed_iclass_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_iclass_enum_t2str(const xed_iclass_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_iclass_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_iclass_enum_t xed_iclass_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-enum.h new file mode 100644 index 0000000..3decd82 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-enum.h @@ -0,0 +1,13779 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-iform-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_IFORM_ENUM_H) +# define XED_IFORM_ENUM_H +#include "xed-common-hdrs.h" +#include "xed-iclass-enum.h" +#define XED_IFORM_INVALID_DEFINED 1 +#define XED_IFORM_AAA_DEFINED 1 +#define XED_IFORM_AAD_IMMb_DEFINED 1 +#define XED_IFORM_AAM_IMMb_DEFINED 1 +#define XED_IFORM_AAS_DEFINED 1 +#define XED_IFORM_ADC_AL_IMMb_DEFINED 1 +#define XED_IFORM_ADC_GPR8_GPR8_10_DEFINED 1 +#define XED_IFORM_ADC_GPR8_GPR8_12_DEFINED 1 +#define XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED 1 +#define XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED 1 +#define XED_IFORM_ADC_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_ADC_GPRv_GPRv_11_DEFINED 1 +#define XED_IFORM_ADC_GPRv_GPRv_13_DEFINED 1 +#define XED_IFORM_ADC_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ADC_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_ADC_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_ADC_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED 1 +#define XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED 1 +#define XED_IFORM_ADC_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADC_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADC_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADC_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED 1 +#define XED_IFORM_ADCX_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED 1 +#define XED_IFORM_ADCX_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADD_AL_IMMb_DEFINED 1 +#define XED_IFORM_ADD_GPR8_GPR8_00_DEFINED 1 +#define XED_IFORM_ADD_GPR8_GPR8_02_DEFINED 1 +#define XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED 1 +#define XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED 1 +#define XED_IFORM_ADD_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_ADD_GPRv_GPRv_01_DEFINED 1 +#define XED_IFORM_ADD_GPRv_GPRv_03_DEFINED 1 +#define XED_IFORM_ADD_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ADD_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_ADD_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_ADD_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED 1 +#define XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED 1 +#define XED_IFORM_ADD_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADD_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADD_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADD_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_ADDPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_ADDPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_ADDSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_ADDSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED 1 +#define XED_IFORM_ADOX_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED 1 +#define XED_IFORM_ADOX_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_AND_AL_IMMb_DEFINED 1 +#define XED_IFORM_AND_GPR8_GPR8_20_DEFINED 1 +#define XED_IFORM_AND_GPR8_GPR8_22_DEFINED 1 +#define XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED 1 +#define XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED 1 +#define XED_IFORM_AND_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_AND_GPRv_GPRv_21_DEFINED 1 +#define XED_IFORM_AND_GPRv_GPRv_23_DEFINED 1 +#define XED_IFORM_AND_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_AND_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_AND_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_AND_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED 1 +#define XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED 1 +#define XED_IFORM_AND_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_AND_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_AND_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_AND_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ARPL_GPR16_GPR16_DEFINED 1 +#define XED_IFORM_ARPL_MEMw_GPR16_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCI_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCI_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCI_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCI_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCIC_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCIC_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCIC_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCIC_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCS_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCS_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCS_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCS_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLSI_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSI_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSI_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_BLSI_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BLSIC_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSIC_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSIC_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLSIC_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BLSR_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSR_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSR_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_BLSR_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BNDCL_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDCL_BND_GPR32_DEFINED 1 +#define XED_IFORM_BNDCL_BND_GPR64_DEFINED 1 +#define XED_IFORM_BNDCN_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDCN_BND_GPR32_DEFINED 1 +#define XED_IFORM_BNDCN_BND_GPR64_DEFINED 1 +#define XED_IFORM_BNDCU_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDCU_BND_GPR32_DEFINED 1 +#define XED_IFORM_BNDCU_BND_GPR64_DEFINED 1 +#define XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED 1 +#define XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED 1 +#define XED_IFORM_BNDMK_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDMOV_BND_BND_DEFINED 1 +#define XED_IFORM_BNDMOV_BND_MEMdq_DEFINED 1 +#define XED_IFORM_BNDMOV_BND_MEMq_DEFINED 1 +#define XED_IFORM_BNDMOV_MEMdq_BND_DEFINED 1 +#define XED_IFORM_BNDMOV_MEMq_BND_DEFINED 1 +#define XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED 1 +#define XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED 1 +#define XED_IFORM_BOUND_GPRv_MEMa16_DEFINED 1 +#define XED_IFORM_BOUND_GPRv_MEMa32_DEFINED 1 +#define XED_IFORM_BSF_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BSF_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_BSR_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BSR_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_BSWAP_GPRv_DEFINED 1 +#define XED_IFORM_BT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BT_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BT_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BT_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTC_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BTC_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BTC_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTC_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTR_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BTR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BTR_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTS_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BTS_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BTS_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTS_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_CALL_FAR_MEMp2_DEFINED 1 +#define XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED 1 +#define XED_IFORM_CALL_NEAR_GPRv_DEFINED 1 +#define XED_IFORM_CALL_NEAR_MEMv_DEFINED 1 +#define XED_IFORM_CALL_NEAR_RELBRd_DEFINED 1 +#define XED_IFORM_CALL_NEAR_RELBRz_DEFINED 1 +#define XED_IFORM_CBW_DEFINED 1 +#define XED_IFORM_CDQ_DEFINED 1 +#define XED_IFORM_CDQE_DEFINED 1 +#define XED_IFORM_CLAC_DEFINED 1 +#define XED_IFORM_CLC_DEFINED 1 +#define XED_IFORM_CLD_DEFINED 1 +#define XED_IFORM_CLDEMOTE_MEMu8_DEFINED 1 +#define XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED 1 +#define XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED 1 +#define XED_IFORM_CLGI_DEFINED 1 +#define XED_IFORM_CLI_DEFINED 1 +#define XED_IFORM_CLRSSBSY_MEMu64_DEFINED 1 +#define XED_IFORM_CLTS_DEFINED 1 +#define XED_IFORM_CLUI_DEFINED 1 +#define XED_IFORM_CLWB_MEMmprefetch_DEFINED 1 +#define XED_IFORM_CLZERO_DEFINED 1 +#define XED_IFORM_CMC_DEFINED 1 +#define XED_IFORM_CMOVB_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVL_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVL_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVO_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVO_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVP_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVP_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVS_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVS_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMP_AL_IMMb_DEFINED 1 +#define XED_IFORM_CMP_GPR8_GPR8_38_DEFINED 1 +#define XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED 1 +#define XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED 1 +#define XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED 1 +#define XED_IFORM_CMP_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_CMP_GPRv_GPRv_39_DEFINED 1 +#define XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED 1 +#define XED_IFORM_CMP_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_CMP_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_CMP_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMP_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED 1 +#define XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED 1 +#define XED_IFORM_CMP_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_CMP_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_CMP_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_CMP_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED 1 +#define XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED 1 +#define XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED 1 +#define XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_CMPSB_DEFINED 1 +#define XED_IFORM_CMPSD_DEFINED 1 +#define XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED 1 +#define XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED 1 +#define XED_IFORM_CMPSQ_DEFINED 1 +#define XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED 1 +#define XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED 1 +#define XED_IFORM_CMPSW_DEFINED 1 +#define XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_CMPXCHG16B_MEMdq_DEFINED 1 +#define XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED 1 +#define XED_IFORM_CMPXCHG8B_MEMq_DEFINED 1 +#define XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED 1 +#define XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_COMISS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_COMISS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_CPUID_DEFINED 1 +#define XED_IFORM_CQO_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_GPRv_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_MEMb_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_MEMv_DEFINED 1 +#define XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED 1 +#define XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED 1 +#define XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED 1 +#define XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED 1 +#define XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED 1 +#define XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED 1 +#define XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED 1 +#define XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED 1 +#define XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED 1 +#define XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED 1 +#define XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED 1 +#define XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED 1 +#define XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED 1 +#define XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED 1 +#define XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED 1 +#define XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED 1 +#define XED_IFORM_CWD_DEFINED 1 +#define XED_IFORM_CWDE_DEFINED 1 +#define XED_IFORM_DAA_DEFINED 1 +#define XED_IFORM_DAS_DEFINED 1 +#define XED_IFORM_DEC_GPR8_DEFINED 1 +#define XED_IFORM_DEC_GPRv_48_DEFINED 1 +#define XED_IFORM_DEC_GPRv_FFr1_DEFINED 1 +#define XED_IFORM_DEC_MEMb_DEFINED 1 +#define XED_IFORM_DEC_MEMv_DEFINED 1 +#define XED_IFORM_DEC_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_DEC_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_DIV_GPR8_DEFINED 1 +#define XED_IFORM_DIV_GPRv_DEFINED 1 +#define XED_IFORM_DIV_MEMb_DEFINED 1 +#define XED_IFORM_DIV_MEMv_DEFINED 1 +#define XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_DIVPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_DIVPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_DIVSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_DIVSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_EMMS_DEFINED 1 +#define XED_IFORM_ENCLS_DEFINED 1 +#define XED_IFORM_ENCLU_DEFINED 1 +#define XED_IFORM_ENCLV_DEFINED 1 +#define XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED 1 +#define XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED 1 +#define XED_IFORM_ENDBR32_DEFINED 1 +#define XED_IFORM_ENDBR64_DEFINED 1 +#define XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED 1 +#define XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED 1 +#define XED_IFORM_ENTER_IMMw_IMMb_DEFINED 1 +#define XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED 1 +#define XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED 1 +#define XED_IFORM_F2XM1_DEFINED 1 +#define XED_IFORM_FABS_DEFINED 1 +#define XED_IFORM_FADD_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FADD_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FADD_ST0_X87_DEFINED 1 +#define XED_IFORM_FADD_X87_ST0_DEFINED 1 +#define XED_IFORM_FADDP_X87_ST0_DEFINED 1 +#define XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED 1 +#define XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED 1 +#define XED_IFORM_FCHS_DEFINED 1 +#define XED_IFORM_FCMOVB_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVBE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNB_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNBE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNU_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVU_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOM_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FCOM_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED 1 +#define XED_IFORM_FCOMI_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOMIP_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED 1 +#define XED_IFORM_FCOMPP_DEFINED 1 +#define XED_IFORM_FCOS_DEFINED 1 +#define XED_IFORM_FDECSTP_DEFINED 1 +#define XED_IFORM_FDISI8087_NOP_DEFINED 1 +#define XED_IFORM_FDIV_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FDIV_ST0_X87_DEFINED 1 +#define XED_IFORM_FDIV_X87_ST0_DEFINED 1 +#define XED_IFORM_FDIVP_X87_ST0_DEFINED 1 +#define XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FDIVR_ST0_X87_DEFINED 1 +#define XED_IFORM_FDIVR_X87_ST0_DEFINED 1 +#define XED_IFORM_FDIVRP_X87_ST0_DEFINED 1 +#define XED_IFORM_FEMMS_DEFINED 1 +#define XED_IFORM_FENI8087_NOP_DEFINED 1 +#define XED_IFORM_FFREE_X87_DEFINED 1 +#define XED_IFORM_FFREEP_X87_DEFINED 1 +#define XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FILD_ST0_MEMm64int_DEFINED 1 +#define XED_IFORM_FILD_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FILD_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FINCSTP_DEFINED 1 +#define XED_IFORM_FIST_MEMmem16int_ST0_DEFINED 1 +#define XED_IFORM_FIST_MEMmem32int_ST0_DEFINED 1 +#define XED_IFORM_FISTP_MEMm64int_ST0_DEFINED 1 +#define XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED 1 +#define XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED 1 +#define XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED 1 +#define XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED 1 +#define XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED 1 +#define XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FLD_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FLD_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FLD_ST0_MEMmem80real_DEFINED 1 +#define XED_IFORM_FLD_ST0_X87_DEFINED 1 +#define XED_IFORM_FLD1_DEFINED 1 +#define XED_IFORM_FLDCW_MEMmem16_DEFINED 1 +#define XED_IFORM_FLDENV_MEMmem14_DEFINED 1 +#define XED_IFORM_FLDENV_MEMmem28_DEFINED 1 +#define XED_IFORM_FLDL2E_DEFINED 1 +#define XED_IFORM_FLDL2T_DEFINED 1 +#define XED_IFORM_FLDLG2_DEFINED 1 +#define XED_IFORM_FLDLN2_DEFINED 1 +#define XED_IFORM_FLDPI_DEFINED 1 +#define XED_IFORM_FLDZ_DEFINED 1 +#define XED_IFORM_FMUL_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FMUL_ST0_X87_DEFINED 1 +#define XED_IFORM_FMUL_X87_ST0_DEFINED 1 +#define XED_IFORM_FMULP_X87_ST0_DEFINED 1 +#define XED_IFORM_FNCLEX_DEFINED 1 +#define XED_IFORM_FNINIT_DEFINED 1 +#define XED_IFORM_FNOP_DEFINED 1 +#define XED_IFORM_FNSAVE_MEMmem108_DEFINED 1 +#define XED_IFORM_FNSAVE_MEMmem94_DEFINED 1 +#define XED_IFORM_FNSTCW_MEMmem16_DEFINED 1 +#define XED_IFORM_FNSTENV_MEMmem14_DEFINED 1 +#define XED_IFORM_FNSTENV_MEMmem28_DEFINED 1 +#define XED_IFORM_FNSTSW_AX_DEFINED 1 +#define XED_IFORM_FNSTSW_MEMmem16_DEFINED 1 +#define XED_IFORM_FPATAN_DEFINED 1 +#define XED_IFORM_FPREM_DEFINED 1 +#define XED_IFORM_FPREM1_DEFINED 1 +#define XED_IFORM_FPTAN_DEFINED 1 +#define XED_IFORM_FRNDINT_DEFINED 1 +#define XED_IFORM_FRSTOR_MEMmem108_DEFINED 1 +#define XED_IFORM_FRSTOR_MEMmem94_DEFINED 1 +#define XED_IFORM_FSCALE_DEFINED 1 +#define XED_IFORM_FSETPM287_NOP_DEFINED 1 +#define XED_IFORM_FSIN_DEFINED 1 +#define XED_IFORM_FSINCOS_DEFINED 1 +#define XED_IFORM_FSQRT_DEFINED 1 +#define XED_IFORM_FST_MEMm64real_ST0_DEFINED 1 +#define XED_IFORM_FST_MEMmem32real_ST0_DEFINED 1 +#define XED_IFORM_FST_X87_ST0_DEFINED 1 +#define XED_IFORM_FSTP_MEMm64real_ST0_DEFINED 1 +#define XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED 1 +#define XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED 1 +#define XED_IFORM_FSTP_X87_ST0_DEFINED 1 +#define XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED 1 +#define XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED 1 +#define XED_IFORM_FSTPNCE_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUB_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FSUB_ST0_X87_DEFINED 1 +#define XED_IFORM_FSUB_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUBP_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FSUBR_ST0_X87_DEFINED 1 +#define XED_IFORM_FSUBR_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUBRP_X87_ST0_DEFINED 1 +#define XED_IFORM_FTST_DEFINED 1 +#define XED_IFORM_FUCOM_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMI_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMIP_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMP_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMPP_DEFINED 1 +#define XED_IFORM_FWAIT_DEFINED 1 +#define XED_IFORM_FXAM_DEFINED 1 +#define XED_IFORM_FXCH_ST0_X87_DEFINED 1 +#define XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED 1 +#define XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED 1 +#define XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXTRACT_DEFINED 1 +#define XED_IFORM_FYL2X_DEFINED 1 +#define XED_IFORM_FYL2XP1_DEFINED 1 +#define XED_IFORM_GETSEC_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED 1 +#define XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_HADDPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_HADDPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_HLT_DEFINED 1 +#define XED_IFORM_HRESET_IMM8_DEFINED 1 +#define XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_IDIV_GPR8_DEFINED 1 +#define XED_IFORM_IDIV_GPRv_DEFINED 1 +#define XED_IFORM_IDIV_MEMb_DEFINED 1 +#define XED_IFORM_IDIV_MEMv_DEFINED 1 +#define XED_IFORM_IMUL_GPR8_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_IMUL_MEMb_DEFINED 1 +#define XED_IFORM_IMUL_MEMv_DEFINED 1 +#define XED_IFORM_IN_AL_DX_DEFINED 1 +#define XED_IFORM_IN_AL_IMMb_DEFINED 1 +#define XED_IFORM_IN_OeAX_DX_DEFINED 1 +#define XED_IFORM_IN_OeAX_IMMb_DEFINED 1 +#define XED_IFORM_INC_GPR8_DEFINED 1 +#define XED_IFORM_INC_GPRv_40_DEFINED 1 +#define XED_IFORM_INC_GPRv_FFr0_DEFINED 1 +#define XED_IFORM_INC_MEMb_DEFINED 1 +#define XED_IFORM_INC_MEMv_DEFINED 1 +#define XED_IFORM_INCSSPD_GPR32u8_DEFINED 1 +#define XED_IFORM_INCSSPQ_GPR64u8_DEFINED 1 +#define XED_IFORM_INC_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_INC_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_INSB_DEFINED 1 +#define XED_IFORM_INSD_DEFINED 1 +#define XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED 1 +#define XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED 1 +#define XED_IFORM_INSW_DEFINED 1 +#define XED_IFORM_INT_IMMb_DEFINED 1 +#define XED_IFORM_INT1_DEFINED 1 +#define XED_IFORM_INT3_DEFINED 1 +#define XED_IFORM_INTO_DEFINED 1 +#define XED_IFORM_INVD_DEFINED 1 +#define XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED 1 +#define XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED 1 +#define XED_IFORM_INVLPG_MEMb_DEFINED 1 +#define XED_IFORM_INVLPGA_ArAX_ECX_DEFINED 1 +#define XED_IFORM_INVLPGB_EAX_EDX_ECX_DEFINED 1 +#define XED_IFORM_INVLPGB_RAX_EDX_ECX_DEFINED 1 +#define XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED 1 +#define XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED 1 +#define XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED 1 +#define XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED 1 +#define XED_IFORM_IRET_DEFINED 1 +#define XED_IFORM_IRETD_DEFINED 1 +#define XED_IFORM_IRETQ_DEFINED 1 +#define XED_IFORM_JB_RELBRb_DEFINED 1 +#define XED_IFORM_JB_RELBRd_DEFINED 1 +#define XED_IFORM_JB_RELBRz_DEFINED 1 +#define XED_IFORM_JBE_RELBRb_DEFINED 1 +#define XED_IFORM_JBE_RELBRd_DEFINED 1 +#define XED_IFORM_JBE_RELBRz_DEFINED 1 +#define XED_IFORM_JCXZ_RELBRb_DEFINED 1 +#define XED_IFORM_JECXZ_RELBRb_DEFINED 1 +#define XED_IFORM_JL_RELBRb_DEFINED 1 +#define XED_IFORM_JL_RELBRd_DEFINED 1 +#define XED_IFORM_JL_RELBRz_DEFINED 1 +#define XED_IFORM_JLE_RELBRb_DEFINED 1 +#define XED_IFORM_JLE_RELBRd_DEFINED 1 +#define XED_IFORM_JLE_RELBRz_DEFINED 1 +#define XED_IFORM_JMP_GPRv_DEFINED 1 +#define XED_IFORM_JMP_MEMv_DEFINED 1 +#define XED_IFORM_JMP_RELBRb_DEFINED 1 +#define XED_IFORM_JMP_RELBRd_DEFINED 1 +#define XED_IFORM_JMP_RELBRz_DEFINED 1 +#define XED_IFORM_JMP_FAR_MEMp2_DEFINED 1 +#define XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED 1 +#define XED_IFORM_JNB_RELBRb_DEFINED 1 +#define XED_IFORM_JNB_RELBRd_DEFINED 1 +#define XED_IFORM_JNB_RELBRz_DEFINED 1 +#define XED_IFORM_JNBE_RELBRb_DEFINED 1 +#define XED_IFORM_JNBE_RELBRd_DEFINED 1 +#define XED_IFORM_JNBE_RELBRz_DEFINED 1 +#define XED_IFORM_JNL_RELBRb_DEFINED 1 +#define XED_IFORM_JNL_RELBRd_DEFINED 1 +#define XED_IFORM_JNL_RELBRz_DEFINED 1 +#define XED_IFORM_JNLE_RELBRb_DEFINED 1 +#define XED_IFORM_JNLE_RELBRd_DEFINED 1 +#define XED_IFORM_JNLE_RELBRz_DEFINED 1 +#define XED_IFORM_JNO_RELBRb_DEFINED 1 +#define XED_IFORM_JNO_RELBRd_DEFINED 1 +#define XED_IFORM_JNO_RELBRz_DEFINED 1 +#define XED_IFORM_JNP_RELBRb_DEFINED 1 +#define XED_IFORM_JNP_RELBRd_DEFINED 1 +#define XED_IFORM_JNP_RELBRz_DEFINED 1 +#define XED_IFORM_JNS_RELBRb_DEFINED 1 +#define XED_IFORM_JNS_RELBRd_DEFINED 1 +#define XED_IFORM_JNS_RELBRz_DEFINED 1 +#define XED_IFORM_JNZ_RELBRb_DEFINED 1 +#define XED_IFORM_JNZ_RELBRd_DEFINED 1 +#define XED_IFORM_JNZ_RELBRz_DEFINED 1 +#define XED_IFORM_JO_RELBRb_DEFINED 1 +#define XED_IFORM_JO_RELBRd_DEFINED 1 +#define XED_IFORM_JO_RELBRz_DEFINED 1 +#define XED_IFORM_JP_RELBRb_DEFINED 1 +#define XED_IFORM_JP_RELBRd_DEFINED 1 +#define XED_IFORM_JP_RELBRz_DEFINED 1 +#define XED_IFORM_JRCXZ_RELBRb_DEFINED 1 +#define XED_IFORM_JS_RELBRb_DEFINED 1 +#define XED_IFORM_JS_RELBRd_DEFINED 1 +#define XED_IFORM_JS_RELBRz_DEFINED 1 +#define XED_IFORM_JZ_RELBRb_DEFINED 1 +#define XED_IFORM_JZ_RELBRd_DEFINED 1 +#define XED_IFORM_JZ_RELBRz_DEFINED 1 +#define XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_LAHF_DEFINED 1 +#define XED_IFORM_LAR_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_LAR_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED 1 +#define XED_IFORM_LDMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_LDS_GPRz_MEMp_DEFINED 1 +#define XED_IFORM_LDTILECFG_MEM_DEFINED 1 +#define XED_IFORM_LEA_GPRv_AGEN_DEFINED 1 +#define XED_IFORM_LEAVE_DEFINED 1 +#define XED_IFORM_LES_GPRz_MEMp_DEFINED 1 +#define XED_IFORM_LFENCE_DEFINED 1 +#define XED_IFORM_LFS_GPRv_MEMp2_DEFINED 1 +#define XED_IFORM_LGDT_MEMs_DEFINED 1 +#define XED_IFORM_LGDT_MEMs64_DEFINED 1 +#define XED_IFORM_LGS_GPRv_MEMp2_DEFINED 1 +#define XED_IFORM_LIDT_MEMs_DEFINED 1 +#define XED_IFORM_LIDT_MEMs64_DEFINED 1 +#define XED_IFORM_LLDT_GPR16_DEFINED 1 +#define XED_IFORM_LLDT_MEMw_DEFINED 1 +#define XED_IFORM_LLWPCB_VGPRyy_DEFINED 1 +#define XED_IFORM_LMSW_GPR16_DEFINED 1 +#define XED_IFORM_LMSW_MEMw_DEFINED 1 +#define XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED 1 +#define XED_IFORM_LODSB_DEFINED 1 +#define XED_IFORM_LODSD_DEFINED 1 +#define XED_IFORM_LODSQ_DEFINED 1 +#define XED_IFORM_LODSW_DEFINED 1 +#define XED_IFORM_LOOP_RELBRb_DEFINED 1 +#define XED_IFORM_LOOPE_RELBRb_DEFINED 1 +#define XED_IFORM_LOOPNE_RELBRb_DEFINED 1 +#define XED_IFORM_LSL_GPRv_GPRz_DEFINED 1 +#define XED_IFORM_LSL_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_LSS_GPRv_MEMp2_DEFINED 1 +#define XED_IFORM_LTR_GPR16_DEFINED 1 +#define XED_IFORM_LTR_MEMw_DEFINED 1 +#define XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd_DEFINED 1 +#define XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd_DEFINED 1 +#define XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd_DEFINED 1 +#define XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd_DEFINED 1 +#define XED_IFORM_LZCNT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_LZCNT_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_MASKMOVDQU_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MAXPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MAXPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MAXSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_MAXSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_MCOMMIT_DEFINED 1 +#define XED_IFORM_MFENCE_DEFINED 1 +#define XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MINPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MINPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MINSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_MINSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_MONITOR_DEFINED 1 +#define XED_IFORM_MONITORX_DEFINED 1 +#define XED_IFORM_MOV_AL_MEMb_DEFINED 1 +#define XED_IFORM_MOV_GPR8_GPR8_88_DEFINED 1 +#define XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED 1 +#define XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED 1 +#define XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED 1 +#define XED_IFORM_MOV_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_MOV_GPRv_GPRv_89_DEFINED 1 +#define XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED 1 +#define XED_IFORM_MOV_GPRv_IMMv_DEFINED 1 +#define XED_IFORM_MOV_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_MOV_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_MOV_GPRv_SEG_DEFINED 1 +#define XED_IFORM_MOV_MEMb_AL_DEFINED 1 +#define XED_IFORM_MOV_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_MOV_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_MOV_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_MOV_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_MOV_MEMv_OrAX_DEFINED 1 +#define XED_IFORM_MOV_MEMw_SEG_DEFINED 1 +#define XED_IFORM_MOV_OrAX_MEMv_DEFINED 1 +#define XED_IFORM_MOV_SEG_GPR16_DEFINED 1 +#define XED_IFORM_MOV_SEG_MEMw_DEFINED 1 +#define XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED 1 +#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED 1 +#define XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED 1 +#define XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED 1 +#define XED_IFORM_MOVBE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_MOVBE_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_MOVD_GPR32_MMXd_DEFINED 1 +#define XED_IFORM_MOVD_GPR32_XMMd_DEFINED 1 +#define XED_IFORM_MOVD_MEMd_MMXd_DEFINED 1 +#define XED_IFORM_MOVD_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_MOVD_MMXq_GPR32_DEFINED 1 +#define XED_IFORM_MOVD_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_MOVD_XMMdq_GPR32_DEFINED 1 +#define XED_IFORM_MOVD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED 1 +#define XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED 1 +#define XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED 1 +#define XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED 1 +#define XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED 1 +#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED 1 +#define XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED 1 +#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED 1 +#define XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED 1 +#define XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED 1 +#define XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED 1 +#define XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED 1 +#define XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED 1 +#define XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED 1 +#define XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED 1 +#define XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED 1 +#define XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED 1 +#define XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED 1 +#define XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED 1 +#define XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED 1 +#define XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_MOVQ_GPR64_MMXq_DEFINED 1 +#define XED_IFORM_MOVQ_GPR64_XMMq_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_GPR64_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED 1 +#define XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED 1 +#define XED_IFORM_MOVSB_DEFINED 1 +#define XED_IFORM_MOVSD_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED 1 +#define XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVSQ_DEFINED 1 +#define XED_IFORM_MOVSS_MEMss_XMMss_DEFINED 1 +#define XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED 1 +#define XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED 1 +#define XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED 1 +#define XED_IFORM_MOVSW_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_GPR16_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_GPR8_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_MEMb_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED 1 +#define XED_IFORM_MOVSXD_GPRv_MEMz_DEFINED 1 +#define XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED 1 +#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED 1 +#define XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED 1 +#define XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_GPR16_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_GPR8_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_MEMb_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_MOV_CR_CR_GPR32_DEFINED 1 +#define XED_IFORM_MOV_CR_CR_GPR64_DEFINED 1 +#define XED_IFORM_MOV_CR_GPR32_CR_DEFINED 1 +#define XED_IFORM_MOV_CR_GPR64_CR_DEFINED 1 +#define XED_IFORM_MOV_DR_DR_GPR32_DEFINED 1 +#define XED_IFORM_MOV_DR_DR_GPR64_DEFINED 1 +#define XED_IFORM_MOV_DR_GPR32_DR_DEFINED 1 +#define XED_IFORM_MOV_DR_GPR64_DR_DEFINED 1 +#define XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_MUL_GPR8_DEFINED 1 +#define XED_IFORM_MUL_GPRv_DEFINED 1 +#define XED_IFORM_MUL_MEMb_DEFINED 1 +#define XED_IFORM_MUL_MEMv_DEFINED 1 +#define XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MULPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MULPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MULSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_MULSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_MWAIT_DEFINED 1 +#define XED_IFORM_MWAITX_DEFINED 1 +#define XED_IFORM_NEG_GPR8_DEFINED 1 +#define XED_IFORM_NEG_GPRv_DEFINED 1 +#define XED_IFORM_NEG_MEMb_DEFINED 1 +#define XED_IFORM_NEG_MEMv_DEFINED 1 +#define XED_IFORM_NEG_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_NEG_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_NOP_90_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r0_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r1_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r2_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r3_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r4_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r5_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r6_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r7_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1F_DEFINED 1 +#define XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED 1 +#define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r5_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r6_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r7_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1F_DEFINED 1 +#define XED_IFORM_NOT_GPR8_DEFINED 1 +#define XED_IFORM_NOT_GPRv_DEFINED 1 +#define XED_IFORM_NOT_MEMb_DEFINED 1 +#define XED_IFORM_NOT_MEMv_DEFINED 1 +#define XED_IFORM_NOT_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_NOT_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_OR_AL_IMMb_DEFINED 1 +#define XED_IFORM_OR_GPR8_GPR8_08_DEFINED 1 +#define XED_IFORM_OR_GPR8_GPR8_0A_DEFINED 1 +#define XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED 1 +#define XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED 1 +#define XED_IFORM_OR_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_OR_GPRv_GPRv_09_DEFINED 1 +#define XED_IFORM_OR_GPRv_GPRv_0B_DEFINED 1 +#define XED_IFORM_OR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_OR_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_OR_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_OR_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED 1 +#define XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED 1 +#define XED_IFORM_OR_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_OR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_OR_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_OR_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_OUT_DX_AL_DEFINED 1 +#define XED_IFORM_OUT_DX_OeAX_DEFINED 1 +#define XED_IFORM_OUT_IMMb_AL_DEFINED 1 +#define XED_IFORM_OUT_IMMb_OeAX_DEFINED 1 +#define XED_IFORM_OUTSB_DEFINED 1 +#define XED_IFORM_OUTSD_DEFINED 1 +#define XED_IFORM_OUTSW_DEFINED 1 +#define XED_IFORM_PABSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PABSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PABSD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PABSD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PABSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PABSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PAND_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAND_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAND_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PAND_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PANDN_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PANDN_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PAUSE_DEFINED 1 +#define XED_IFORM_PAVGB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAVGB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAVGW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAVGW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCONFIG_DEFINED 1 +#define XED_IFORM_PCONFIG64_DEFINED 1 +#define XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PF2ID_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PF2ID_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PF2IW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PF2IW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFACC_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFACC_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFADD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFADD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFMAX_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFMAX_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFMIN_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFMIN_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFMUL_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFMUL_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFNACC_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFNACC_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRCP_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRCP_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFSUB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFSUB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHADDD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHADDW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHADDW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PI2FD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PI2FD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PI2FW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PI2FW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED 1 +#define XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED 1 +#define XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMINSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINUB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMINUB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED 1 +#define XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED 1 +#define XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULHW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULLW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULLW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_POP_DS_DEFINED 1 +#define XED_IFORM_POP_ES_DEFINED 1 +#define XED_IFORM_POP_FS_DEFINED 1 +#define XED_IFORM_POP_GPRv_58_DEFINED 1 +#define XED_IFORM_POP_GPRv_8F_DEFINED 1 +#define XED_IFORM_POP_GS_DEFINED 1 +#define XED_IFORM_POP_MEMv_DEFINED 1 +#define XED_IFORM_POP_SS_DEFINED 1 +#define XED_IFORM_POPA_DEFINED 1 +#define XED_IFORM_POPAD_DEFINED 1 +#define XED_IFORM_POPCNT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_POPCNT_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_POPF_DEFINED 1 +#define XED_IFORM_POPFD_DEFINED 1 +#define XED_IFORM_POPFQ_DEFINED 1 +#define XED_IFORM_POR_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_POR_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_POR_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_POR_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHW_0F0Dr1_DEFINED 1 +#define XED_IFORM_PREFETCHW_0F0Dr3_DEFINED 1 +#define XED_IFORM_PREFETCHWT1_MEMu8_DEFINED 1 +#define XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED 1 +#define XED_IFORM_PSADBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSADBW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSIGND_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSIGND_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSLLD_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSLLD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSLLW_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSLLW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSMASH_RAX_DEFINED 1 +#define XED_IFORM_PSRAD_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRAD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRAW_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRAW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRLD_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRLD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRLW_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRLW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PTWRITE_GPRy_DEFINED 1 +#define XED_IFORM_PTWRITE_MEMy_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUSH_CS_DEFINED 1 +#define XED_IFORM_PUSH_DS_DEFINED 1 +#define XED_IFORM_PUSH_ES_DEFINED 1 +#define XED_IFORM_PUSH_FS_DEFINED 1 +#define XED_IFORM_PUSH_GPRv_50_DEFINED 1 +#define XED_IFORM_PUSH_GPRv_FFr6_DEFINED 1 +#define XED_IFORM_PUSH_GS_DEFINED 1 +#define XED_IFORM_PUSH_IMMb_DEFINED 1 +#define XED_IFORM_PUSH_IMMz_DEFINED 1 +#define XED_IFORM_PUSH_MEMv_DEFINED 1 +#define XED_IFORM_PUSH_SS_DEFINED 1 +#define XED_IFORM_PUSHA_DEFINED 1 +#define XED_IFORM_PUSHAD_DEFINED 1 +#define XED_IFORM_PUSHF_DEFINED 1 +#define XED_IFORM_PUSHFD_DEFINED 1 +#define XED_IFORM_PUSHFQ_DEFINED 1 +#define XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED 1 +#define XED_IFORM_PXOR_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PXOR_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_RCL_GPR8_CL_DEFINED 1 +#define XED_IFORM_RCL_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_RCL_GPR8_ONE_DEFINED 1 +#define XED_IFORM_RCL_GPRv_CL_DEFINED 1 +#define XED_IFORM_RCL_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_RCL_GPRv_ONE_DEFINED 1 +#define XED_IFORM_RCL_MEMb_CL_DEFINED 1 +#define XED_IFORM_RCL_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_RCL_MEMb_ONE_DEFINED 1 +#define XED_IFORM_RCL_MEMv_CL_DEFINED 1 +#define XED_IFORM_RCL_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_RCL_MEMv_ONE_DEFINED 1 +#define XED_IFORM_RCPPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_RCPPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_RCPSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_RCPSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_RCR_GPR8_CL_DEFINED 1 +#define XED_IFORM_RCR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_RCR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_RCR_GPRv_CL_DEFINED 1 +#define XED_IFORM_RCR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_RCR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_RCR_MEMb_CL_DEFINED 1 +#define XED_IFORM_RCR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_RCR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_RCR_MEMv_CL_DEFINED 1 +#define XED_IFORM_RCR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_RCR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_RDFSBASE_GPRy_DEFINED 1 +#define XED_IFORM_RDGSBASE_GPRy_DEFINED 1 +#define XED_IFORM_RDMSR_DEFINED 1 +#define XED_IFORM_RDPID_GPR32u32_DEFINED 1 +#define XED_IFORM_RDPID_GPR64u64_DEFINED 1 +#define XED_IFORM_RDPKRU_DEFINED 1 +#define XED_IFORM_RDPMC_DEFINED 1 +#define XED_IFORM_RDPRU_DEFINED 1 +#define XED_IFORM_RDRAND_GPRv_DEFINED 1 +#define XED_IFORM_RDSEED_GPRv_DEFINED 1 +#define XED_IFORM_RDSSPD_GPR32u32_DEFINED 1 +#define XED_IFORM_RDSSPQ_GPR64u64_DEFINED 1 +#define XED_IFORM_RDTSC_DEFINED 1 +#define XED_IFORM_RDTSCP_DEFINED 1 +#define XED_IFORM_REPE_CMPSB_DEFINED 1 +#define XED_IFORM_REPE_CMPSD_DEFINED 1 +#define XED_IFORM_REPE_CMPSQ_DEFINED 1 +#define XED_IFORM_REPE_CMPSW_DEFINED 1 +#define XED_IFORM_REPE_SCASB_DEFINED 1 +#define XED_IFORM_REPE_SCASD_DEFINED 1 +#define XED_IFORM_REPE_SCASQ_DEFINED 1 +#define XED_IFORM_REPE_SCASW_DEFINED 1 +#define XED_IFORM_REPNE_CMPSB_DEFINED 1 +#define XED_IFORM_REPNE_CMPSD_DEFINED 1 +#define XED_IFORM_REPNE_CMPSQ_DEFINED 1 +#define XED_IFORM_REPNE_CMPSW_DEFINED 1 +#define XED_IFORM_REPNE_SCASB_DEFINED 1 +#define XED_IFORM_REPNE_SCASD_DEFINED 1 +#define XED_IFORM_REPNE_SCASQ_DEFINED 1 +#define XED_IFORM_REPNE_SCASW_DEFINED 1 +#define XED_IFORM_REP_INSB_DEFINED 1 +#define XED_IFORM_REP_INSD_DEFINED 1 +#define XED_IFORM_REP_INSW_DEFINED 1 +#define XED_IFORM_REP_LODSB_DEFINED 1 +#define XED_IFORM_REP_LODSD_DEFINED 1 +#define XED_IFORM_REP_LODSQ_DEFINED 1 +#define XED_IFORM_REP_LODSW_DEFINED 1 +#define XED_IFORM_REP_MONTMUL_DEFINED 1 +#define XED_IFORM_REP_MOVSB_DEFINED 1 +#define XED_IFORM_REP_MOVSD_DEFINED 1 +#define XED_IFORM_REP_MOVSQ_DEFINED 1 +#define XED_IFORM_REP_MOVSW_DEFINED 1 +#define XED_IFORM_REP_OUTSB_DEFINED 1 +#define XED_IFORM_REP_OUTSD_DEFINED 1 +#define XED_IFORM_REP_OUTSW_DEFINED 1 +#define XED_IFORM_REP_STOSB_DEFINED 1 +#define XED_IFORM_REP_STOSD_DEFINED 1 +#define XED_IFORM_REP_STOSQ_DEFINED 1 +#define XED_IFORM_REP_STOSW_DEFINED 1 +#define XED_IFORM_REP_XCRYPTCBC_DEFINED 1 +#define XED_IFORM_REP_XCRYPTCFB_DEFINED 1 +#define XED_IFORM_REP_XCRYPTCTR_DEFINED 1 +#define XED_IFORM_REP_XCRYPTECB_DEFINED 1 +#define XED_IFORM_REP_XCRYPTOFB_DEFINED 1 +#define XED_IFORM_REP_XSHA1_DEFINED 1 +#define XED_IFORM_REP_XSHA256_DEFINED 1 +#define XED_IFORM_REP_XSTORE_DEFINED 1 +#define XED_IFORM_RET_FAR_DEFINED 1 +#define XED_IFORM_RET_FAR_IMMw_DEFINED 1 +#define XED_IFORM_RET_NEAR_DEFINED 1 +#define XED_IFORM_RET_NEAR_IMMw_DEFINED 1 +#define XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED 1 +#define XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED 1 +#define XED_IFORM_ROL_GPR8_CL_DEFINED 1 +#define XED_IFORM_ROL_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_ROL_GPR8_ONE_DEFINED 1 +#define XED_IFORM_ROL_GPRv_CL_DEFINED 1 +#define XED_IFORM_ROL_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ROL_GPRv_ONE_DEFINED 1 +#define XED_IFORM_ROL_MEMb_CL_DEFINED 1 +#define XED_IFORM_ROL_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_ROL_MEMb_ONE_DEFINED 1 +#define XED_IFORM_ROL_MEMv_CL_DEFINED 1 +#define XED_IFORM_ROL_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ROL_MEMv_ONE_DEFINED 1 +#define XED_IFORM_ROR_GPR8_CL_DEFINED 1 +#define XED_IFORM_ROR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_ROR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_ROR_GPRv_CL_DEFINED 1 +#define XED_IFORM_ROR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ROR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_ROR_MEMb_CL_DEFINED 1 +#define XED_IFORM_ROR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_ROR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_ROR_MEMv_CL_DEFINED 1 +#define XED_IFORM_ROR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ROR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_RORX_VGPR32d_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb_DEFINED 1 +#define XED_IFORM_RORX_VGPR64q_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED 1 +#define XED_IFORM_RSM_DEFINED 1 +#define XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_RSTORSSP_MEMu64_DEFINED 1 +#define XED_IFORM_SAHF_DEFINED 1 +#define XED_IFORM_SALC_DEFINED 1 +#define XED_IFORM_SAR_GPR8_CL_DEFINED 1 +#define XED_IFORM_SAR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_SAR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_SAR_GPRv_CL_DEFINED 1 +#define XED_IFORM_SAR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SAR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_SAR_MEMb_CL_DEFINED 1 +#define XED_IFORM_SAR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_SAR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_SAR_MEMv_CL_DEFINED 1 +#define XED_IFORM_SAR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SAR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_SAVEPREVSSP_DEFINED 1 +#define XED_IFORM_SBB_AL_IMMb_DEFINED 1 +#define XED_IFORM_SBB_GPR8_GPR8_18_DEFINED 1 +#define XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED 1 +#define XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED 1 +#define XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED 1 +#define XED_IFORM_SBB_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_SBB_GPRv_GPRv_19_DEFINED 1 +#define XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED 1 +#define XED_IFORM_SBB_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SBB_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_SBB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_SBB_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED 1 +#define XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED 1 +#define XED_IFORM_SBB_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SBB_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SBB_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SBB_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SCASB_DEFINED 1 +#define XED_IFORM_SCASD_DEFINED 1 +#define XED_IFORM_SCASQ_DEFINED 1 +#define XED_IFORM_SCASW_DEFINED 1 +#define XED_IFORM_SEAMCALL_DEFINED 1 +#define XED_IFORM_SEAMOPS_DEFINED 1 +#define XED_IFORM_SEAMRET_DEFINED 1 +#define XED_IFORM_SENDUIPI_GPR32u32_DEFINED 1 +#define XED_IFORM_SERIALIZE_DEFINED 1 +#define XED_IFORM_SETB_GPR8_DEFINED 1 +#define XED_IFORM_SETB_MEMb_DEFINED 1 +#define XED_IFORM_SETBE_GPR8_DEFINED 1 +#define XED_IFORM_SETBE_MEMb_DEFINED 1 +#define XED_IFORM_SETL_GPR8_DEFINED 1 +#define XED_IFORM_SETL_MEMb_DEFINED 1 +#define XED_IFORM_SETLE_GPR8_DEFINED 1 +#define XED_IFORM_SETLE_MEMb_DEFINED 1 +#define XED_IFORM_SETNB_GPR8_DEFINED 1 +#define XED_IFORM_SETNB_MEMb_DEFINED 1 +#define XED_IFORM_SETNBE_GPR8_DEFINED 1 +#define XED_IFORM_SETNBE_MEMb_DEFINED 1 +#define XED_IFORM_SETNL_GPR8_DEFINED 1 +#define XED_IFORM_SETNL_MEMb_DEFINED 1 +#define XED_IFORM_SETNLE_GPR8_DEFINED 1 +#define XED_IFORM_SETNLE_MEMb_DEFINED 1 +#define XED_IFORM_SETNO_GPR8_DEFINED 1 +#define XED_IFORM_SETNO_MEMb_DEFINED 1 +#define XED_IFORM_SETNP_GPR8_DEFINED 1 +#define XED_IFORM_SETNP_MEMb_DEFINED 1 +#define XED_IFORM_SETNS_GPR8_DEFINED 1 +#define XED_IFORM_SETNS_MEMb_DEFINED 1 +#define XED_IFORM_SETNZ_GPR8_DEFINED 1 +#define XED_IFORM_SETNZ_MEMb_DEFINED 1 +#define XED_IFORM_SETO_GPR8_DEFINED 1 +#define XED_IFORM_SETO_MEMb_DEFINED 1 +#define XED_IFORM_SETP_GPR8_DEFINED 1 +#define XED_IFORM_SETP_MEMb_DEFINED 1 +#define XED_IFORM_SETS_GPR8_DEFINED 1 +#define XED_IFORM_SETS_MEMb_DEFINED 1 +#define XED_IFORM_SETSSBSY_DEFINED 1 +#define XED_IFORM_SETZ_GPR8_DEFINED 1 +#define XED_IFORM_SETZ_MEMb_DEFINED 1 +#define XED_IFORM_SFENCE_DEFINED 1 +#define XED_IFORM_SGDT_MEMs_DEFINED 1 +#define XED_IFORM_SGDT_MEMs64_DEFINED 1 +#define XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED 1 +#define XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED 1 +#define XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED 1 +#define XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED 1 +#define XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED 1 +#define XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED 1 +#define XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED 1 +#define XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED 1 +#define XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED 1 +#define XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED 1 +#define XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED 1 +#define XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED 1 +#define XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED 1 +#define XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED 1 +#define XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED 1 +#define XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED 1 +#define XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED 1 +#define XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED 1 +#define XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED 1 +#define XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED 1 +#define XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED 1 +#define XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED 1 +#define XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED 1 +#define XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED 1 +#define XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED 1 +#define XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_SHR_GPR8_CL_DEFINED 1 +#define XED_IFORM_SHR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_SHR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_SHR_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_SHR_MEMb_CL_DEFINED 1 +#define XED_IFORM_SHR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_SHR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_SHR_MEMv_CL_DEFINED 1 +#define XED_IFORM_SHR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SHR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED 1 +#define XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED 1 +#define XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED 1 +#define XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_SIDT_MEMs_DEFINED 1 +#define XED_IFORM_SIDT_MEMs64_DEFINED 1 +#define XED_IFORM_SKINIT_EAX_DEFINED 1 +#define XED_IFORM_SLDT_GPRv_DEFINED 1 +#define XED_IFORM_SLDT_MEMw_DEFINED 1 +#define XED_IFORM_SLWPCB_VGPRyy_DEFINED 1 +#define XED_IFORM_SMSW_GPRv_DEFINED 1 +#define XED_IFORM_SMSW_MEMw_DEFINED 1 +#define XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_STAC_DEFINED 1 +#define XED_IFORM_STC_DEFINED 1 +#define XED_IFORM_STD_DEFINED 1 +#define XED_IFORM_STGI_DEFINED 1 +#define XED_IFORM_STI_DEFINED 1 +#define XED_IFORM_STMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_STOSB_DEFINED 1 +#define XED_IFORM_STOSD_DEFINED 1 +#define XED_IFORM_STOSQ_DEFINED 1 +#define XED_IFORM_STOSW_DEFINED 1 +#define XED_IFORM_STR_GPRv_DEFINED 1 +#define XED_IFORM_STR_MEMw_DEFINED 1 +#define XED_IFORM_STTILECFG_MEM_DEFINED 1 +#define XED_IFORM_STUI_DEFINED 1 +#define XED_IFORM_SUB_AL_IMMb_DEFINED 1 +#define XED_IFORM_SUB_GPR8_GPR8_28_DEFINED 1 +#define XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED 1 +#define XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED 1 +#define XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED 1 +#define XED_IFORM_SUB_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_SUB_GPRv_GPRv_29_DEFINED 1 +#define XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED 1 +#define XED_IFORM_SUB_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SUB_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_SUB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_SUB_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED 1 +#define XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED 1 +#define XED_IFORM_SUB_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SUB_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SUB_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SUB_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_SUBPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_SUBPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_SUBSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_SUBSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SWAPGS_DEFINED 1 +#define XED_IFORM_SYSCALL_DEFINED 1 +#define XED_IFORM_SYSCALL_AMD_DEFINED 1 +#define XED_IFORM_SYSENTER_DEFINED 1 +#define XED_IFORM_SYSEXIT_DEFINED 1 +#define XED_IFORM_SYSRET_DEFINED 1 +#define XED_IFORM_SYSRET64_DEFINED 1 +#define XED_IFORM_SYSRET_AMD_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_TDCALL_DEFINED 1 +#define XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TEST_AL_IMMb_DEFINED 1 +#define XED_IFORM_TEST_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED 1 +#define XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED 1 +#define XED_IFORM_TEST_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED 1 +#define XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED 1 +#define XED_IFORM_TEST_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED 1 +#define XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED 1 +#define XED_IFORM_TEST_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED 1 +#define XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED 1 +#define XED_IFORM_TEST_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_TESTUI_DEFINED 1 +#define XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_TILERELEASE_DEFINED 1 +#define XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TILEZERO_TMMu32_DEFINED 1 +#define XED_IFORM_TLBSYNC_DEFINED 1 +#define XED_IFORM_TPAUSE_GPR32u32_DEFINED 1 +#define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_TZCNT_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_TZMSK_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_TZMSK_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_TZMSK_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_TZMSK_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_UD0_DEFINED 1 +#define XED_IFORM_UD0_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_UD0_GPR32_MEMd_DEFINED 1 +#define XED_IFORM_UD1_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_UD1_GPR32_MEMd_DEFINED 1 +#define XED_IFORM_UD2_DEFINED 1 +#define XED_IFORM_UIRET_DEFINED 1 +#define XED_IFORM_UMONITOR_GPRa_DEFINED 1 +#define XED_IFORM_UMWAIT_GPR32_DEFINED 1 +#define XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED 1 +#define XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED 1 +#define XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VERR_GPR16_DEFINED 1 +#define XED_IFORM_VERR_MEMw_DEFINED 1 +#define XED_IFORM_VERW_GPR16_DEFINED 1 +#define XED_IFORM_VERW_MEMw_DEFINED 1 +#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VLDMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMCALL_DEFINED 1 +#define XED_IFORM_VMCLEAR_MEMq_DEFINED 1 +#define XED_IFORM_VMFUNC_DEFINED 1 +#define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMLAUNCH_DEFINED 1 +#define XED_IFORM_VMLOAD_ArAX_DEFINED 1 +#define XED_IFORM_VMMCALL_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED 1 +#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED 1 +#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED 1 +#define XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED 1 +#define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED 1 +#define XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED 1 +#define XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED 1 +#define XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED 1 +#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED 1 +#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VMPTRLD_MEMq_DEFINED 1 +#define XED_IFORM_VMPTRST_MEMq_DEFINED 1 +#define XED_IFORM_VMREAD_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_VMREAD_GPR64_GPR64_DEFINED 1 +#define XED_IFORM_VMREAD_MEMd_GPR32_DEFINED 1 +#define XED_IFORM_VMREAD_MEMq_GPR64_DEFINED 1 +#define XED_IFORM_VMRESUME_DEFINED 1 +#define XED_IFORM_VMRUN_ArAX_DEFINED 1 +#define XED_IFORM_VMSAVE_DEFINED 1 +#define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED 1 +#define XED_IFORM_VMXOFF_DEFINED 1 +#define XED_IFORM_VMXON_MEMq_DEFINED 1 +#define XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED 1 +#define XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED 1 +#define XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSTMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VZEROALL_DEFINED 1 +#define XED_IFORM_VZEROUPPER_DEFINED 1 +#define XED_IFORM_WBINVD_DEFINED 1 +#define XED_IFORM_WBNOINVD_DEFINED 1 +#define XED_IFORM_WRFSBASE_GPRy_DEFINED 1 +#define XED_IFORM_WRGSBASE_GPRy_DEFINED 1 +#define XED_IFORM_WRMSR_DEFINED 1 +#define XED_IFORM_WRPKRU_DEFINED 1 +#define XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED 1 +#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED 1 +#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED 1 +#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED 1 +#define XED_IFORM_XABORT_IMMb_DEFINED 1 +#define XED_IFORM_XADD_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_XADD_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_XADD_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XADD_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XBEGIN_RELBRz_DEFINED 1 +#define XED_IFORM_XCHG_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_XCHG_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_XCHG_GPRv_OrAX_DEFINED 1 +#define XED_IFORM_XCHG_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XCHG_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XEND_DEFINED 1 +#define XED_IFORM_XGETBV_DEFINED 1 +#define XED_IFORM_XLAT_DEFINED 1 +#define XED_IFORM_XOR_AL_IMMb_DEFINED 1 +#define XED_IFORM_XOR_GPR8_GPR8_30_DEFINED 1 +#define XED_IFORM_XOR_GPR8_GPR8_32_DEFINED 1 +#define XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED 1 +#define XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED 1 +#define XED_IFORM_XOR_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_XOR_GPRv_GPRv_31_DEFINED 1 +#define XED_IFORM_XOR_GPRv_GPRv_33_DEFINED 1 +#define XED_IFORM_XOR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_XOR_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_XOR_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_XOR_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED 1 +#define XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED 1 +#define XED_IFORM_XOR_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XOR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_XOR_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_XOR_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_XRESLDTRK_DEFINED 1 +#define XED_IFORM_XRSTOR_MEMmxsave_DEFINED 1 +#define XED_IFORM_XRSTOR64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XRSTORS_MEMmxsave_DEFINED 1 +#define XED_IFORM_XRSTORS64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVE_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVE64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEC_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEC64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVES_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVES64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSETBV_DEFINED 1 +#define XED_IFORM_XSTORE_DEFINED 1 +#define XED_IFORM_XSUSLDTRK_DEFINED 1 +#define XED_IFORM_XTEST_DEFINED 1 +#define XED_IFORM_LAST_DEFINED 1 +typedef enum { + XED_IFORM_INVALID=0, + XED_IFORM_AAA=1, + XED_IFORM_AAD_IMMb=2, + XED_IFORM_AAM_IMMb=3, + XED_IFORM_AAS=4, + XED_IFORM_ADC_AL_IMMb=5, + XED_IFORM_ADC_GPR8_GPR8_10=6, + XED_IFORM_ADC_GPR8_GPR8_12=7, + XED_IFORM_ADC_GPR8_IMMb_80r2=8, + XED_IFORM_ADC_GPR8_IMMb_82r2=9, + XED_IFORM_ADC_GPR8_MEMb=10, + XED_IFORM_ADC_GPRv_GPRv_11=11, + XED_IFORM_ADC_GPRv_GPRv_13=12, + XED_IFORM_ADC_GPRv_IMMb=13, + XED_IFORM_ADC_GPRv_IMMz=14, + XED_IFORM_ADC_GPRv_MEMv=15, + XED_IFORM_ADC_MEMb_GPR8=16, + XED_IFORM_ADC_MEMb_IMMb_80r2=17, + XED_IFORM_ADC_MEMb_IMMb_82r2=18, + XED_IFORM_ADC_MEMv_GPRv=19, + XED_IFORM_ADC_MEMv_IMMb=20, + XED_IFORM_ADC_MEMv_IMMz=21, + XED_IFORM_ADC_OrAX_IMMz=22, + XED_IFORM_ADCX_GPR32d_GPR32d=23, + XED_IFORM_ADCX_GPR32d_MEMd=24, + XED_IFORM_ADCX_GPR64q_GPR64q=25, + XED_IFORM_ADCX_GPR64q_MEMq=26, + XED_IFORM_ADC_LOCK_MEMb_GPR8=27, + XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2=28, + XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2=29, + XED_IFORM_ADC_LOCK_MEMv_GPRv=30, + XED_IFORM_ADC_LOCK_MEMv_IMMb=31, + XED_IFORM_ADC_LOCK_MEMv_IMMz=32, + XED_IFORM_ADD_AL_IMMb=33, + XED_IFORM_ADD_GPR8_GPR8_00=34, + XED_IFORM_ADD_GPR8_GPR8_02=35, + XED_IFORM_ADD_GPR8_IMMb_80r0=36, + XED_IFORM_ADD_GPR8_IMMb_82r0=37, + XED_IFORM_ADD_GPR8_MEMb=38, + XED_IFORM_ADD_GPRv_GPRv_01=39, + XED_IFORM_ADD_GPRv_GPRv_03=40, + XED_IFORM_ADD_GPRv_IMMb=41, + XED_IFORM_ADD_GPRv_IMMz=42, + XED_IFORM_ADD_GPRv_MEMv=43, + XED_IFORM_ADD_MEMb_GPR8=44, + XED_IFORM_ADD_MEMb_IMMb_80r0=45, + XED_IFORM_ADD_MEMb_IMMb_82r0=46, + XED_IFORM_ADD_MEMv_GPRv=47, + XED_IFORM_ADD_MEMv_IMMb=48, + XED_IFORM_ADD_MEMv_IMMz=49, + XED_IFORM_ADD_OrAX_IMMz=50, + XED_IFORM_ADDPD_XMMpd_MEMpd=51, + XED_IFORM_ADDPD_XMMpd_XMMpd=52, + XED_IFORM_ADDPS_XMMps_MEMps=53, + XED_IFORM_ADDPS_XMMps_XMMps=54, + XED_IFORM_ADDSD_XMMsd_MEMsd=55, + XED_IFORM_ADDSD_XMMsd_XMMsd=56, + XED_IFORM_ADDSS_XMMss_MEMss=57, + XED_IFORM_ADDSS_XMMss_XMMss=58, + XED_IFORM_ADDSUBPD_XMMpd_MEMpd=59, + XED_IFORM_ADDSUBPD_XMMpd_XMMpd=60, + XED_IFORM_ADDSUBPS_XMMps_MEMps=61, + XED_IFORM_ADDSUBPS_XMMps_XMMps=62, + XED_IFORM_ADD_LOCK_MEMb_GPR8=63, + XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0=64, + XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0=65, + XED_IFORM_ADD_LOCK_MEMv_GPRv=66, + XED_IFORM_ADD_LOCK_MEMv_IMMb=67, + XED_IFORM_ADD_LOCK_MEMv_IMMz=68, + XED_IFORM_ADOX_GPR32d_GPR32d=69, + XED_IFORM_ADOX_GPR32d_MEMd=70, + XED_IFORM_ADOX_GPR64q_GPR64q=71, + XED_IFORM_ADOX_GPR64q_MEMq=72, + XED_IFORM_AESDEC_XMMdq_MEMdq=73, + XED_IFORM_AESDEC_XMMdq_XMMdq=74, + XED_IFORM_AESDEC128KL_XMMu8_MEMu8=75, + XED_IFORM_AESDEC256KL_XMMu8_MEMu8=76, + XED_IFORM_AESDECLAST_XMMdq_MEMdq=77, + XED_IFORM_AESDECLAST_XMMdq_XMMdq=78, + XED_IFORM_AESDECWIDE128KL_MEMu8=79, + XED_IFORM_AESDECWIDE256KL_MEMu8=80, + XED_IFORM_AESENC_XMMdq_MEMdq=81, + XED_IFORM_AESENC_XMMdq_XMMdq=82, + XED_IFORM_AESENC128KL_XMMu8_MEMu8=83, + XED_IFORM_AESENC256KL_XMMu8_MEMu8=84, + XED_IFORM_AESENCLAST_XMMdq_MEMdq=85, + XED_IFORM_AESENCLAST_XMMdq_XMMdq=86, + XED_IFORM_AESENCWIDE128KL_MEMu8=87, + XED_IFORM_AESENCWIDE256KL_MEMu8=88, + XED_IFORM_AESIMC_XMMdq_MEMdq=89, + XED_IFORM_AESIMC_XMMdq_XMMdq=90, + XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb=91, + XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb=92, + XED_IFORM_AND_AL_IMMb=93, + XED_IFORM_AND_GPR8_GPR8_20=94, + XED_IFORM_AND_GPR8_GPR8_22=95, + XED_IFORM_AND_GPR8_IMMb_80r4=96, + XED_IFORM_AND_GPR8_IMMb_82r4=97, + XED_IFORM_AND_GPR8_MEMb=98, + XED_IFORM_AND_GPRv_GPRv_21=99, + XED_IFORM_AND_GPRv_GPRv_23=100, + XED_IFORM_AND_GPRv_IMMb=101, + XED_IFORM_AND_GPRv_IMMz=102, + XED_IFORM_AND_GPRv_MEMv=103, + XED_IFORM_AND_MEMb_GPR8=104, + XED_IFORM_AND_MEMb_IMMb_80r4=105, + XED_IFORM_AND_MEMb_IMMb_82r4=106, + XED_IFORM_AND_MEMv_GPRv=107, + XED_IFORM_AND_MEMv_IMMb=108, + XED_IFORM_AND_MEMv_IMMz=109, + XED_IFORM_AND_OrAX_IMMz=110, + XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd=111, + XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d=112, + XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq=113, + XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q=114, + XED_IFORM_ANDNPD_XMMxuq_MEMxuq=115, + XED_IFORM_ANDNPD_XMMxuq_XMMxuq=116, + XED_IFORM_ANDNPS_XMMxud_MEMxud=117, + XED_IFORM_ANDNPS_XMMxud_XMMxud=118, + XED_IFORM_ANDPD_XMMxuq_MEMxuq=119, + XED_IFORM_ANDPD_XMMxuq_XMMxuq=120, + XED_IFORM_ANDPS_XMMxud_MEMxud=121, + XED_IFORM_ANDPS_XMMxud_XMMxud=122, + XED_IFORM_AND_LOCK_MEMb_GPR8=123, + XED_IFORM_AND_LOCK_MEMb_IMMb_80r4=124, + XED_IFORM_AND_LOCK_MEMb_IMMb_82r4=125, + XED_IFORM_AND_LOCK_MEMv_GPRv=126, + XED_IFORM_AND_LOCK_MEMv_IMMb=127, + XED_IFORM_AND_LOCK_MEMv_IMMz=128, + XED_IFORM_ARPL_GPR16_GPR16=129, + XED_IFORM_ARPL_MEMw_GPR16=130, + XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d=131, + XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d=132, + XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q=133, + XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q=134, + XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd=135, + XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd=136, + XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd=137, + XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd=138, + XED_IFORM_BLCFILL_VGPR32d_MEMd=139, + XED_IFORM_BLCFILL_VGPR32d_VGPR32d=140, + XED_IFORM_BLCFILL_VGPRyy_MEMy=141, + XED_IFORM_BLCFILL_VGPRyy_VGPRyy=142, + XED_IFORM_BLCI_VGPR32d_MEMd=143, + XED_IFORM_BLCI_VGPR32d_VGPR32d=144, + XED_IFORM_BLCI_VGPRyy_MEMy=145, + XED_IFORM_BLCI_VGPRyy_VGPRyy=146, + XED_IFORM_BLCIC_VGPR32d_MEMd=147, + XED_IFORM_BLCIC_VGPR32d_VGPR32d=148, + XED_IFORM_BLCIC_VGPRyy_MEMy=149, + XED_IFORM_BLCIC_VGPRyy_VGPRyy=150, + XED_IFORM_BLCMSK_VGPR32d_MEMd=151, + XED_IFORM_BLCMSK_VGPR32d_VGPR32d=152, + XED_IFORM_BLCMSK_VGPRyy_MEMy=153, + XED_IFORM_BLCMSK_VGPRyy_VGPRyy=154, + XED_IFORM_BLCS_VGPR32d_MEMd=155, + XED_IFORM_BLCS_VGPR32d_VGPR32d=156, + XED_IFORM_BLCS_VGPRyy_MEMy=157, + XED_IFORM_BLCS_VGPRyy_VGPRyy=158, + XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb=159, + XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb=160, + XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb=161, + XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb=162, + XED_IFORM_BLENDVPD_XMMdq_MEMdq=163, + XED_IFORM_BLENDVPD_XMMdq_XMMdq=164, + XED_IFORM_BLENDVPS_XMMdq_MEMdq=165, + XED_IFORM_BLENDVPS_XMMdq_XMMdq=166, + XED_IFORM_BLSFILL_VGPR32d_MEMd=167, + XED_IFORM_BLSFILL_VGPR32d_VGPR32d=168, + XED_IFORM_BLSFILL_VGPRyy_MEMy=169, + XED_IFORM_BLSFILL_VGPRyy_VGPRyy=170, + XED_IFORM_BLSI_VGPR32d_MEMd=171, + XED_IFORM_BLSI_VGPR32d_VGPR32d=172, + XED_IFORM_BLSI_VGPR64q_MEMq=173, + XED_IFORM_BLSI_VGPR64q_VGPR64q=174, + XED_IFORM_BLSIC_VGPR32d_MEMd=175, + XED_IFORM_BLSIC_VGPR32d_VGPR32d=176, + XED_IFORM_BLSIC_VGPRyy_MEMy=177, + XED_IFORM_BLSIC_VGPRyy_VGPRyy=178, + XED_IFORM_BLSMSK_VGPR32d_MEMd=179, + XED_IFORM_BLSMSK_VGPR32d_VGPR32d=180, + XED_IFORM_BLSMSK_VGPR64q_MEMq=181, + XED_IFORM_BLSMSK_VGPR64q_VGPR64q=182, + XED_IFORM_BLSR_VGPR32d_MEMd=183, + XED_IFORM_BLSR_VGPR32d_VGPR32d=184, + XED_IFORM_BLSR_VGPR64q_MEMq=185, + XED_IFORM_BLSR_VGPR64q_VGPR64q=186, + XED_IFORM_BNDCL_BND_AGEN=187, + XED_IFORM_BNDCL_BND_GPR32=188, + XED_IFORM_BNDCL_BND_GPR64=189, + XED_IFORM_BNDCN_BND_AGEN=190, + XED_IFORM_BNDCN_BND_GPR32=191, + XED_IFORM_BNDCN_BND_GPR64=192, + XED_IFORM_BNDCU_BND_AGEN=193, + XED_IFORM_BNDCU_BND_GPR32=194, + XED_IFORM_BNDCU_BND_GPR64=195, + XED_IFORM_BNDLDX_BND_MEMbnd32=196, + XED_IFORM_BNDLDX_BND_MEMbnd64=197, + XED_IFORM_BNDMK_BND_AGEN=198, + XED_IFORM_BNDMOV_BND_BND=199, + XED_IFORM_BNDMOV_BND_MEMdq=200, + XED_IFORM_BNDMOV_BND_MEMq=201, + XED_IFORM_BNDMOV_MEMdq_BND=202, + XED_IFORM_BNDMOV_MEMq_BND=203, + XED_IFORM_BNDSTX_MEMbnd32_BND=204, + XED_IFORM_BNDSTX_MEMbnd64_BND=205, + XED_IFORM_BOUND_GPRv_MEMa16=206, + XED_IFORM_BOUND_GPRv_MEMa32=207, + XED_IFORM_BSF_GPRv_GPRv=208, + XED_IFORM_BSF_GPRv_MEMv=209, + XED_IFORM_BSR_GPRv_GPRv=210, + XED_IFORM_BSR_GPRv_MEMv=211, + XED_IFORM_BSWAP_GPRv=212, + XED_IFORM_BT_GPRv_GPRv=213, + XED_IFORM_BT_GPRv_IMMb=214, + XED_IFORM_BT_MEMv_GPRv=215, + XED_IFORM_BT_MEMv_IMMb=216, + XED_IFORM_BTC_GPRv_GPRv=217, + XED_IFORM_BTC_GPRv_IMMb=218, + XED_IFORM_BTC_MEMv_GPRv=219, + XED_IFORM_BTC_MEMv_IMMb=220, + XED_IFORM_BTC_LOCK_MEMv_GPRv=221, + XED_IFORM_BTC_LOCK_MEMv_IMMb=222, + XED_IFORM_BTR_GPRv_GPRv=223, + XED_IFORM_BTR_GPRv_IMMb=224, + XED_IFORM_BTR_MEMv_GPRv=225, + XED_IFORM_BTR_MEMv_IMMb=226, + XED_IFORM_BTR_LOCK_MEMv_GPRv=227, + XED_IFORM_BTR_LOCK_MEMv_IMMb=228, + XED_IFORM_BTS_GPRv_GPRv=229, + XED_IFORM_BTS_GPRv_IMMb=230, + XED_IFORM_BTS_MEMv_GPRv=231, + XED_IFORM_BTS_MEMv_IMMb=232, + XED_IFORM_BTS_LOCK_MEMv_GPRv=233, + XED_IFORM_BTS_LOCK_MEMv_IMMb=234, + XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d=235, + XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d=236, + XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q=237, + XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q=238, + XED_IFORM_CALL_FAR_MEMp2=239, + XED_IFORM_CALL_FAR_PTRp_IMMw=240, + XED_IFORM_CALL_NEAR_GPRv=241, + XED_IFORM_CALL_NEAR_MEMv=242, + XED_IFORM_CALL_NEAR_RELBRd=243, + XED_IFORM_CALL_NEAR_RELBRz=244, + XED_IFORM_CBW=245, + XED_IFORM_CDQ=246, + XED_IFORM_CDQE=247, + XED_IFORM_CLAC=248, + XED_IFORM_CLC=249, + XED_IFORM_CLD=250, + XED_IFORM_CLDEMOTE_MEMu8=251, + XED_IFORM_CLFLUSH_MEMmprefetch=252, + XED_IFORM_CLFLUSHOPT_MEMmprefetch=253, + XED_IFORM_CLGI=254, + XED_IFORM_CLI=255, + XED_IFORM_CLRSSBSY_MEMu64=256, + XED_IFORM_CLTS=257, + XED_IFORM_CLUI=258, + XED_IFORM_CLWB_MEMmprefetch=259, + XED_IFORM_CLZERO=260, + XED_IFORM_CMC=261, + XED_IFORM_CMOVB_GPRv_GPRv=262, + XED_IFORM_CMOVB_GPRv_MEMv=263, + XED_IFORM_CMOVBE_GPRv_GPRv=264, + XED_IFORM_CMOVBE_GPRv_MEMv=265, + XED_IFORM_CMOVL_GPRv_GPRv=266, + XED_IFORM_CMOVL_GPRv_MEMv=267, + XED_IFORM_CMOVLE_GPRv_GPRv=268, + XED_IFORM_CMOVLE_GPRv_MEMv=269, + XED_IFORM_CMOVNB_GPRv_GPRv=270, + XED_IFORM_CMOVNB_GPRv_MEMv=271, + XED_IFORM_CMOVNBE_GPRv_GPRv=272, + XED_IFORM_CMOVNBE_GPRv_MEMv=273, + XED_IFORM_CMOVNL_GPRv_GPRv=274, + XED_IFORM_CMOVNL_GPRv_MEMv=275, + XED_IFORM_CMOVNLE_GPRv_GPRv=276, + XED_IFORM_CMOVNLE_GPRv_MEMv=277, + XED_IFORM_CMOVNO_GPRv_GPRv=278, + XED_IFORM_CMOVNO_GPRv_MEMv=279, + XED_IFORM_CMOVNP_GPRv_GPRv=280, + XED_IFORM_CMOVNP_GPRv_MEMv=281, + XED_IFORM_CMOVNS_GPRv_GPRv=282, + XED_IFORM_CMOVNS_GPRv_MEMv=283, + XED_IFORM_CMOVNZ_GPRv_GPRv=284, + XED_IFORM_CMOVNZ_GPRv_MEMv=285, + XED_IFORM_CMOVO_GPRv_GPRv=286, + XED_IFORM_CMOVO_GPRv_MEMv=287, + XED_IFORM_CMOVP_GPRv_GPRv=288, + XED_IFORM_CMOVP_GPRv_MEMv=289, + XED_IFORM_CMOVS_GPRv_GPRv=290, + XED_IFORM_CMOVS_GPRv_MEMv=291, + XED_IFORM_CMOVZ_GPRv_GPRv=292, + XED_IFORM_CMOVZ_GPRv_MEMv=293, + XED_IFORM_CMP_AL_IMMb=294, + XED_IFORM_CMP_GPR8_GPR8_38=295, + XED_IFORM_CMP_GPR8_GPR8_3A=296, + XED_IFORM_CMP_GPR8_IMMb_80r7=297, + XED_IFORM_CMP_GPR8_IMMb_82r7=298, + XED_IFORM_CMP_GPR8_MEMb=299, + XED_IFORM_CMP_GPRv_GPRv_39=300, + XED_IFORM_CMP_GPRv_GPRv_3B=301, + XED_IFORM_CMP_GPRv_IMMb=302, + XED_IFORM_CMP_GPRv_IMMz=303, + XED_IFORM_CMP_GPRv_MEMv=304, + XED_IFORM_CMP_MEMb_GPR8=305, + XED_IFORM_CMP_MEMb_IMMb_80r7=306, + XED_IFORM_CMP_MEMb_IMMb_82r7=307, + XED_IFORM_CMP_MEMv_GPRv=308, + XED_IFORM_CMP_MEMv_IMMb=309, + XED_IFORM_CMP_MEMv_IMMz=310, + XED_IFORM_CMP_OrAX_IMMz=311, + XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb=312, + XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb=313, + XED_IFORM_CMPPS_XMMps_MEMps_IMMb=314, + XED_IFORM_CMPPS_XMMps_XMMps_IMMb=315, + XED_IFORM_CMPSB=316, + XED_IFORM_CMPSD=317, + XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb=318, + XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb=319, + XED_IFORM_CMPSQ=320, + XED_IFORM_CMPSS_XMMss_MEMss_IMMb=321, + XED_IFORM_CMPSS_XMMss_XMMss_IMMb=322, + XED_IFORM_CMPSW=323, + XED_IFORM_CMPXCHG_GPR8_GPR8=324, + XED_IFORM_CMPXCHG_GPRv_GPRv=325, + XED_IFORM_CMPXCHG_MEMb_GPR8=326, + XED_IFORM_CMPXCHG_MEMv_GPRv=327, + XED_IFORM_CMPXCHG16B_MEMdq=328, + XED_IFORM_CMPXCHG16B_LOCK_MEMdq=329, + XED_IFORM_CMPXCHG8B_MEMq=330, + XED_IFORM_CMPXCHG8B_LOCK_MEMq=331, + XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8=332, + XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv=333, + XED_IFORM_COMISD_XMMsd_MEMsd=334, + XED_IFORM_COMISD_XMMsd_XMMsd=335, + XED_IFORM_COMISS_XMMss_MEMss=336, + XED_IFORM_COMISS_XMMss_XMMss=337, + XED_IFORM_CPUID=338, + XED_IFORM_CQO=339, + XED_IFORM_CRC32_GPRyy_GPR8b=340, + XED_IFORM_CRC32_GPRyy_GPRv=341, + XED_IFORM_CRC32_GPRyy_MEMb=342, + XED_IFORM_CRC32_GPRyy_MEMv=343, + XED_IFORM_CVTDQ2PD_XMMpd_MEMq=344, + XED_IFORM_CVTDQ2PD_XMMpd_XMMq=345, + XED_IFORM_CVTDQ2PS_XMMps_MEMdq=346, + XED_IFORM_CVTDQ2PS_XMMps_XMMdq=347, + XED_IFORM_CVTPD2DQ_XMMdq_MEMpd=348, + XED_IFORM_CVTPD2DQ_XMMdq_XMMpd=349, + XED_IFORM_CVTPD2PI_MMXq_MEMpd=350, + XED_IFORM_CVTPD2PI_MMXq_XMMpd=351, + XED_IFORM_CVTPD2PS_XMMps_MEMpd=352, + XED_IFORM_CVTPD2PS_XMMps_XMMpd=353, + XED_IFORM_CVTPI2PD_XMMpd_MEMq=354, + XED_IFORM_CVTPI2PD_XMMpd_MMXq=355, + XED_IFORM_CVTPI2PS_XMMq_MEMq=356, + XED_IFORM_CVTPI2PS_XMMq_MMXq=357, + XED_IFORM_CVTPS2DQ_XMMdq_MEMps=358, + XED_IFORM_CVTPS2DQ_XMMdq_XMMps=359, + XED_IFORM_CVTPS2PD_XMMpd_MEMq=360, + XED_IFORM_CVTPS2PD_XMMpd_XMMq=361, + XED_IFORM_CVTPS2PI_MMXq_MEMq=362, + XED_IFORM_CVTPS2PI_MMXq_XMMq=363, + XED_IFORM_CVTSD2SI_GPR32d_MEMsd=364, + XED_IFORM_CVTSD2SI_GPR32d_XMMsd=365, + XED_IFORM_CVTSD2SI_GPR64q_MEMsd=366, + XED_IFORM_CVTSD2SI_GPR64q_XMMsd=367, + XED_IFORM_CVTSD2SS_XMMss_MEMsd=368, + XED_IFORM_CVTSD2SS_XMMss_XMMsd=369, + XED_IFORM_CVTSI2SD_XMMsd_GPR32d=370, + XED_IFORM_CVTSI2SD_XMMsd_GPR64q=371, + XED_IFORM_CVTSI2SD_XMMsd_MEMd=372, + XED_IFORM_CVTSI2SD_XMMsd_MEMq=373, + XED_IFORM_CVTSI2SS_XMMss_GPR32d=374, + XED_IFORM_CVTSI2SS_XMMss_GPR64q=375, + XED_IFORM_CVTSI2SS_XMMss_MEMd=376, + XED_IFORM_CVTSI2SS_XMMss_MEMq=377, + XED_IFORM_CVTSS2SD_XMMsd_MEMss=378, + XED_IFORM_CVTSS2SD_XMMsd_XMMss=379, + XED_IFORM_CVTSS2SI_GPR32d_MEMss=380, + XED_IFORM_CVTSS2SI_GPR32d_XMMss=381, + XED_IFORM_CVTSS2SI_GPR64q_MEMss=382, + XED_IFORM_CVTSS2SI_GPR64q_XMMss=383, + XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd=384, + XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd=385, + XED_IFORM_CVTTPD2PI_MMXq_MEMpd=386, + XED_IFORM_CVTTPD2PI_MMXq_XMMpd=387, + XED_IFORM_CVTTPS2DQ_XMMdq_MEMps=388, + XED_IFORM_CVTTPS2DQ_XMMdq_XMMps=389, + XED_IFORM_CVTTPS2PI_MMXq_MEMq=390, + XED_IFORM_CVTTPS2PI_MMXq_XMMq=391, + XED_IFORM_CVTTSD2SI_GPR32d_MEMsd=392, + XED_IFORM_CVTTSD2SI_GPR32d_XMMsd=393, + XED_IFORM_CVTTSD2SI_GPR64q_MEMsd=394, + XED_IFORM_CVTTSD2SI_GPR64q_XMMsd=395, + XED_IFORM_CVTTSS2SI_GPR32d_MEMss=396, + XED_IFORM_CVTTSS2SI_GPR32d_XMMss=397, + XED_IFORM_CVTTSS2SI_GPR64q_MEMss=398, + XED_IFORM_CVTTSS2SI_GPR64q_XMMss=399, + XED_IFORM_CWD=400, + XED_IFORM_CWDE=401, + XED_IFORM_DAA=402, + XED_IFORM_DAS=403, + XED_IFORM_DEC_GPR8=404, + XED_IFORM_DEC_GPRv_48=405, + XED_IFORM_DEC_GPRv_FFr1=406, + XED_IFORM_DEC_MEMb=407, + XED_IFORM_DEC_MEMv=408, + XED_IFORM_DEC_LOCK_MEMb=409, + XED_IFORM_DEC_LOCK_MEMv=410, + XED_IFORM_DIV_GPR8=411, + XED_IFORM_DIV_GPRv=412, + XED_IFORM_DIV_MEMb=413, + XED_IFORM_DIV_MEMv=414, + XED_IFORM_DIVPD_XMMpd_MEMpd=415, + XED_IFORM_DIVPD_XMMpd_XMMpd=416, + XED_IFORM_DIVPS_XMMps_MEMps=417, + XED_IFORM_DIVPS_XMMps_XMMps=418, + XED_IFORM_DIVSD_XMMsd_MEMsd=419, + XED_IFORM_DIVSD_XMMsd_XMMsd=420, + XED_IFORM_DIVSS_XMMss_MEMss=421, + XED_IFORM_DIVSS_XMMss_XMMss=422, + XED_IFORM_DPPD_XMMdq_MEMdq_IMMb=423, + XED_IFORM_DPPD_XMMdq_XMMdq_IMMb=424, + XED_IFORM_DPPS_XMMdq_MEMdq_IMMb=425, + XED_IFORM_DPPS_XMMdq_XMMdq_IMMb=426, + XED_IFORM_EMMS=427, + XED_IFORM_ENCLS=428, + XED_IFORM_ENCLU=429, + XED_IFORM_ENCLV=430, + XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8=431, + XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8=432, + XED_IFORM_ENDBR32=433, + XED_IFORM_ENDBR64=434, + XED_IFORM_ENQCMD_GPRa_MEMu32=435, + XED_IFORM_ENQCMDS_GPRa_MEMu32=436, + XED_IFORM_ENTER_IMMw_IMMb=437, + XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb=438, + XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb=439, + XED_IFORM_EXTRQ_XMMq_IMMb_IMMb=440, + XED_IFORM_EXTRQ_XMMq_XMMdq=441, + XED_IFORM_F2XM1=442, + XED_IFORM_FABS=443, + XED_IFORM_FADD_ST0_MEMm64real=444, + XED_IFORM_FADD_ST0_MEMmem32real=445, + XED_IFORM_FADD_ST0_X87=446, + XED_IFORM_FADD_X87_ST0=447, + XED_IFORM_FADDP_X87_ST0=448, + XED_IFORM_FBLD_ST0_MEMmem80dec=449, + XED_IFORM_FBSTP_MEMmem80dec_ST0=450, + XED_IFORM_FCHS=451, + XED_IFORM_FCMOVB_ST0_X87=452, + XED_IFORM_FCMOVBE_ST0_X87=453, + XED_IFORM_FCMOVE_ST0_X87=454, + XED_IFORM_FCMOVNB_ST0_X87=455, + XED_IFORM_FCMOVNBE_ST0_X87=456, + XED_IFORM_FCMOVNE_ST0_X87=457, + XED_IFORM_FCMOVNU_ST0_X87=458, + XED_IFORM_FCMOVU_ST0_X87=459, + XED_IFORM_FCOM_ST0_MEMm64real=460, + XED_IFORM_FCOM_ST0_MEMmem32real=461, + XED_IFORM_FCOM_ST0_X87=462, + XED_IFORM_FCOM_ST0_X87_DCD0=463, + XED_IFORM_FCOMI_ST0_X87=464, + XED_IFORM_FCOMIP_ST0_X87=465, + XED_IFORM_FCOMP_ST0_MEMm64real=466, + XED_IFORM_FCOMP_ST0_MEMmem32real=467, + XED_IFORM_FCOMP_ST0_X87=468, + XED_IFORM_FCOMP_ST0_X87_DCD1=469, + XED_IFORM_FCOMP_ST0_X87_DED0=470, + XED_IFORM_FCOMPP=471, + XED_IFORM_FCOS=472, + XED_IFORM_FDECSTP=473, + XED_IFORM_FDISI8087_NOP=474, + XED_IFORM_FDIV_ST0_MEMm64real=475, + XED_IFORM_FDIV_ST0_MEMmem32real=476, + XED_IFORM_FDIV_ST0_X87=477, + XED_IFORM_FDIV_X87_ST0=478, + XED_IFORM_FDIVP_X87_ST0=479, + XED_IFORM_FDIVR_ST0_MEMm64real=480, + XED_IFORM_FDIVR_ST0_MEMmem32real=481, + XED_IFORM_FDIVR_ST0_X87=482, + XED_IFORM_FDIVR_X87_ST0=483, + XED_IFORM_FDIVRP_X87_ST0=484, + XED_IFORM_FEMMS=485, + XED_IFORM_FENI8087_NOP=486, + XED_IFORM_FFREE_X87=487, + XED_IFORM_FFREEP_X87=488, + XED_IFORM_FIADD_ST0_MEMmem16int=489, + XED_IFORM_FIADD_ST0_MEMmem32int=490, + XED_IFORM_FICOM_ST0_MEMmem16int=491, + XED_IFORM_FICOM_ST0_MEMmem32int=492, + XED_IFORM_FICOMP_ST0_MEMmem16int=493, + XED_IFORM_FICOMP_ST0_MEMmem32int=494, + XED_IFORM_FIDIV_ST0_MEMmem16int=495, + XED_IFORM_FIDIV_ST0_MEMmem32int=496, + XED_IFORM_FIDIVR_ST0_MEMmem16int=497, + XED_IFORM_FIDIVR_ST0_MEMmem32int=498, + XED_IFORM_FILD_ST0_MEMm64int=499, + XED_IFORM_FILD_ST0_MEMmem16int=500, + XED_IFORM_FILD_ST0_MEMmem32int=501, + XED_IFORM_FIMUL_ST0_MEMmem16int=502, + XED_IFORM_FIMUL_ST0_MEMmem32int=503, + XED_IFORM_FINCSTP=504, + XED_IFORM_FIST_MEMmem16int_ST0=505, + XED_IFORM_FIST_MEMmem32int_ST0=506, + XED_IFORM_FISTP_MEMm64int_ST0=507, + XED_IFORM_FISTP_MEMmem16int_ST0=508, + XED_IFORM_FISTP_MEMmem32int_ST0=509, + XED_IFORM_FISTTP_MEMm64int_ST0=510, + XED_IFORM_FISTTP_MEMmem16int_ST0=511, + XED_IFORM_FISTTP_MEMmem32int_ST0=512, + XED_IFORM_FISUB_ST0_MEMmem16int=513, + XED_IFORM_FISUB_ST0_MEMmem32int=514, + XED_IFORM_FISUBR_ST0_MEMmem16int=515, + XED_IFORM_FISUBR_ST0_MEMmem32int=516, + XED_IFORM_FLD_ST0_MEMm64real=517, + XED_IFORM_FLD_ST0_MEMmem32real=518, + XED_IFORM_FLD_ST0_MEMmem80real=519, + XED_IFORM_FLD_ST0_X87=520, + XED_IFORM_FLD1=521, + XED_IFORM_FLDCW_MEMmem16=522, + XED_IFORM_FLDENV_MEMmem14=523, + XED_IFORM_FLDENV_MEMmem28=524, + XED_IFORM_FLDL2E=525, + XED_IFORM_FLDL2T=526, + XED_IFORM_FLDLG2=527, + XED_IFORM_FLDLN2=528, + XED_IFORM_FLDPI=529, + XED_IFORM_FLDZ=530, + XED_IFORM_FMUL_ST0_MEMm64real=531, + XED_IFORM_FMUL_ST0_MEMmem32real=532, + XED_IFORM_FMUL_ST0_X87=533, + XED_IFORM_FMUL_X87_ST0=534, + XED_IFORM_FMULP_X87_ST0=535, + XED_IFORM_FNCLEX=536, + XED_IFORM_FNINIT=537, + XED_IFORM_FNOP=538, + XED_IFORM_FNSAVE_MEMmem108=539, + XED_IFORM_FNSAVE_MEMmem94=540, + XED_IFORM_FNSTCW_MEMmem16=541, + XED_IFORM_FNSTENV_MEMmem14=542, + XED_IFORM_FNSTENV_MEMmem28=543, + XED_IFORM_FNSTSW_AX=544, + XED_IFORM_FNSTSW_MEMmem16=545, + XED_IFORM_FPATAN=546, + XED_IFORM_FPREM=547, + XED_IFORM_FPREM1=548, + XED_IFORM_FPTAN=549, + XED_IFORM_FRNDINT=550, + XED_IFORM_FRSTOR_MEMmem108=551, + XED_IFORM_FRSTOR_MEMmem94=552, + XED_IFORM_FSCALE=553, + XED_IFORM_FSETPM287_NOP=554, + XED_IFORM_FSIN=555, + XED_IFORM_FSINCOS=556, + XED_IFORM_FSQRT=557, + XED_IFORM_FST_MEMm64real_ST0=558, + XED_IFORM_FST_MEMmem32real_ST0=559, + XED_IFORM_FST_X87_ST0=560, + XED_IFORM_FSTP_MEMm64real_ST0=561, + XED_IFORM_FSTP_MEMmem32real_ST0=562, + XED_IFORM_FSTP_MEMmem80real_ST0=563, + XED_IFORM_FSTP_X87_ST0=564, + XED_IFORM_FSTP_X87_ST0_DFD0=565, + XED_IFORM_FSTP_X87_ST0_DFD1=566, + XED_IFORM_FSTPNCE_X87_ST0=567, + XED_IFORM_FSUB_ST0_MEMm64real=568, + XED_IFORM_FSUB_ST0_MEMmem32real=569, + XED_IFORM_FSUB_ST0_X87=570, + XED_IFORM_FSUB_X87_ST0=571, + XED_IFORM_FSUBP_X87_ST0=572, + XED_IFORM_FSUBR_ST0_MEMm64real=573, + XED_IFORM_FSUBR_ST0_MEMmem32real=574, + XED_IFORM_FSUBR_ST0_X87=575, + XED_IFORM_FSUBR_X87_ST0=576, + XED_IFORM_FSUBRP_X87_ST0=577, + XED_IFORM_FTST=578, + XED_IFORM_FUCOM_ST0_X87=579, + XED_IFORM_FUCOMI_ST0_X87=580, + XED_IFORM_FUCOMIP_ST0_X87=581, + XED_IFORM_FUCOMP_ST0_X87=582, + XED_IFORM_FUCOMPP=583, + XED_IFORM_FWAIT=584, + XED_IFORM_FXAM=585, + XED_IFORM_FXCH_ST0_X87=586, + XED_IFORM_FXCH_ST0_X87_DDC1=587, + XED_IFORM_FXCH_ST0_X87_DFC1=588, + XED_IFORM_FXRSTOR_MEMmfpxenv=589, + XED_IFORM_FXRSTOR64_MEMmfpxenv=590, + XED_IFORM_FXSAVE_MEMmfpxenv=591, + XED_IFORM_FXSAVE64_MEMmfpxenv=592, + XED_IFORM_FXTRACT=593, + XED_IFORM_FYL2X=594, + XED_IFORM_FYL2XP1=595, + XED_IFORM_GETSEC=596, + XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8=597, + XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8=598, + XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8=599, + XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8=600, + XED_IFORM_GF2P8MULB_XMMu8_MEMu8=601, + XED_IFORM_GF2P8MULB_XMMu8_XMMu8=602, + XED_IFORM_HADDPD_XMMpd_MEMpd=603, + XED_IFORM_HADDPD_XMMpd_XMMpd=604, + XED_IFORM_HADDPS_XMMps_MEMps=605, + XED_IFORM_HADDPS_XMMps_XMMps=606, + XED_IFORM_HLT=607, + XED_IFORM_HRESET_IMM8=608, + XED_IFORM_HSUBPD_XMMpd_MEMpd=609, + XED_IFORM_HSUBPD_XMMpd_XMMpd=610, + XED_IFORM_HSUBPS_XMMps_MEMps=611, + XED_IFORM_HSUBPS_XMMps_XMMps=612, + XED_IFORM_IDIV_GPR8=613, + XED_IFORM_IDIV_GPRv=614, + XED_IFORM_IDIV_MEMb=615, + XED_IFORM_IDIV_MEMv=616, + XED_IFORM_IMUL_GPR8=617, + XED_IFORM_IMUL_GPRv=618, + XED_IFORM_IMUL_GPRv_GPRv=619, + XED_IFORM_IMUL_GPRv_GPRv_IMMb=620, + XED_IFORM_IMUL_GPRv_GPRv_IMMz=621, + XED_IFORM_IMUL_GPRv_MEMv=622, + XED_IFORM_IMUL_GPRv_MEMv_IMMb=623, + XED_IFORM_IMUL_GPRv_MEMv_IMMz=624, + XED_IFORM_IMUL_MEMb=625, + XED_IFORM_IMUL_MEMv=626, + XED_IFORM_IN_AL_DX=627, + XED_IFORM_IN_AL_IMMb=628, + XED_IFORM_IN_OeAX_DX=629, + XED_IFORM_IN_OeAX_IMMb=630, + XED_IFORM_INC_GPR8=631, + XED_IFORM_INC_GPRv_40=632, + XED_IFORM_INC_GPRv_FFr0=633, + XED_IFORM_INC_MEMb=634, + XED_IFORM_INC_MEMv=635, + XED_IFORM_INCSSPD_GPR32u8=636, + XED_IFORM_INCSSPQ_GPR64u8=637, + XED_IFORM_INC_LOCK_MEMb=638, + XED_IFORM_INC_LOCK_MEMv=639, + XED_IFORM_INSB=640, + XED_IFORM_INSD=641, + XED_IFORM_INSERTPS_XMMps_MEMd_IMMb=642, + XED_IFORM_INSERTPS_XMMps_XMMps_IMMb=643, + XED_IFORM_INSERTQ_XMMq_XMMdq=644, + XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb=645, + XED_IFORM_INSW=646, + XED_IFORM_INT_IMMb=647, + XED_IFORM_INT1=648, + XED_IFORM_INT3=649, + XED_IFORM_INTO=650, + XED_IFORM_INVD=651, + XED_IFORM_INVEPT_GPR32_MEMdq=652, + XED_IFORM_INVEPT_GPR64_MEMdq=653, + XED_IFORM_INVLPG_MEMb=654, + XED_IFORM_INVLPGA_ArAX_ECX=655, + XED_IFORM_INVLPGB_EAX_EDX_ECX=656, + XED_IFORM_INVLPGB_RAX_EDX_ECX=657, + XED_IFORM_INVPCID_GPR32_MEMdq=658, + XED_IFORM_INVPCID_GPR64_MEMdq=659, + XED_IFORM_INVVPID_GPR32_MEMdq=660, + XED_IFORM_INVVPID_GPR64_MEMdq=661, + XED_IFORM_IRET=662, + XED_IFORM_IRETD=663, + XED_IFORM_IRETQ=664, + XED_IFORM_JB_RELBRb=665, + XED_IFORM_JB_RELBRd=666, + XED_IFORM_JB_RELBRz=667, + XED_IFORM_JBE_RELBRb=668, + XED_IFORM_JBE_RELBRd=669, + XED_IFORM_JBE_RELBRz=670, + XED_IFORM_JCXZ_RELBRb=671, + XED_IFORM_JECXZ_RELBRb=672, + XED_IFORM_JL_RELBRb=673, + XED_IFORM_JL_RELBRd=674, + XED_IFORM_JL_RELBRz=675, + XED_IFORM_JLE_RELBRb=676, + XED_IFORM_JLE_RELBRd=677, + XED_IFORM_JLE_RELBRz=678, + XED_IFORM_JMP_GPRv=679, + XED_IFORM_JMP_MEMv=680, + XED_IFORM_JMP_RELBRb=681, + XED_IFORM_JMP_RELBRd=682, + XED_IFORM_JMP_RELBRz=683, + XED_IFORM_JMP_FAR_MEMp2=684, + XED_IFORM_JMP_FAR_PTRp_IMMw=685, + XED_IFORM_JNB_RELBRb=686, + XED_IFORM_JNB_RELBRd=687, + XED_IFORM_JNB_RELBRz=688, + XED_IFORM_JNBE_RELBRb=689, + XED_IFORM_JNBE_RELBRd=690, + XED_IFORM_JNBE_RELBRz=691, + XED_IFORM_JNL_RELBRb=692, + XED_IFORM_JNL_RELBRd=693, + XED_IFORM_JNL_RELBRz=694, + XED_IFORM_JNLE_RELBRb=695, + XED_IFORM_JNLE_RELBRd=696, + XED_IFORM_JNLE_RELBRz=697, + XED_IFORM_JNO_RELBRb=698, + XED_IFORM_JNO_RELBRd=699, + XED_IFORM_JNO_RELBRz=700, + XED_IFORM_JNP_RELBRb=701, + XED_IFORM_JNP_RELBRd=702, + XED_IFORM_JNP_RELBRz=703, + XED_IFORM_JNS_RELBRb=704, + XED_IFORM_JNS_RELBRd=705, + XED_IFORM_JNS_RELBRz=706, + XED_IFORM_JNZ_RELBRb=707, + XED_IFORM_JNZ_RELBRd=708, + XED_IFORM_JNZ_RELBRz=709, + XED_IFORM_JO_RELBRb=710, + XED_IFORM_JO_RELBRd=711, + XED_IFORM_JO_RELBRz=712, + XED_IFORM_JP_RELBRb=713, + XED_IFORM_JP_RELBRd=714, + XED_IFORM_JP_RELBRz=715, + XED_IFORM_JRCXZ_RELBRb=716, + XED_IFORM_JS_RELBRb=717, + XED_IFORM_JS_RELBRd=718, + XED_IFORM_JS_RELBRz=719, + XED_IFORM_JZ_RELBRb=720, + XED_IFORM_JZ_RELBRd=721, + XED_IFORM_JZ_RELBRz=722, + XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512=723, + XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512=724, + XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=725, + XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512=726, + XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512=727, + XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512=728, + XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512=729, + XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512=730, + XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512=731, + XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512=732, + XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=733, + XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512=734, + XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512=735, + XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512=736, + XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512=737, + XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512=738, + XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512=739, + XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512=740, + XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512=741, + XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512=742, + XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512=743, + XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512=744, + XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512=745, + XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512=746, + XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512=747, + XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512=748, + XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512=749, + XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512=750, + XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512=751, + XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512=752, + XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512=753, + XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512=754, + XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512=755, + XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512=756, + XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512=757, + XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512=758, + XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512=759, + XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512=760, + XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=761, + XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512=762, + XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512=763, + XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512=764, + XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512=765, + XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512=766, + XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512=767, + XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512=768, + XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512=769, + XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512=770, + XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512=771, + XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512=772, + XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512=773, + XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512=774, + XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512=775, + XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512=776, + XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512=777, + XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512=778, + XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512=779, + XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=780, + XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512=781, + XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512=782, + XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512=783, + XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=784, + XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512=785, + XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512=786, + XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512=787, + XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=788, + XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512=789, + XED_IFORM_LAHF=790, + XED_IFORM_LAR_GPRv_GPRv=791, + XED_IFORM_LAR_GPRv_MEMw=792, + XED_IFORM_LDDQU_XMMpd_MEMdq=793, + XED_IFORM_LDMXCSR_MEMd=794, + XED_IFORM_LDS_GPRz_MEMp=795, + XED_IFORM_LDTILECFG_MEM=796, + XED_IFORM_LEA_GPRv_AGEN=797, + XED_IFORM_LEAVE=798, + XED_IFORM_LES_GPRz_MEMp=799, + XED_IFORM_LFENCE=800, + XED_IFORM_LFS_GPRv_MEMp2=801, + XED_IFORM_LGDT_MEMs=802, + XED_IFORM_LGDT_MEMs64=803, + XED_IFORM_LGS_GPRv_MEMp2=804, + XED_IFORM_LIDT_MEMs=805, + XED_IFORM_LIDT_MEMs64=806, + XED_IFORM_LLDT_GPR16=807, + XED_IFORM_LLDT_MEMw=808, + XED_IFORM_LLWPCB_VGPRyy=809, + XED_IFORM_LMSW_GPR16=810, + XED_IFORM_LMSW_MEMw=811, + XED_IFORM_LOADIWKEY_XMMu8_XMMu8=812, + XED_IFORM_LODSB=813, + XED_IFORM_LODSD=814, + XED_IFORM_LODSQ=815, + XED_IFORM_LODSW=816, + XED_IFORM_LOOP_RELBRb=817, + XED_IFORM_LOOPE_RELBRb=818, + XED_IFORM_LOOPNE_RELBRb=819, + XED_IFORM_LSL_GPRv_GPRz=820, + XED_IFORM_LSL_GPRv_MEMw=821, + XED_IFORM_LSS_GPRv_MEMp2=822, + XED_IFORM_LTR_GPR16=823, + XED_IFORM_LTR_MEMw=824, + XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd=825, + XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd=826, + XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd=827, + XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd=828, + XED_IFORM_LZCNT_GPRv_GPRv=829, + XED_IFORM_LZCNT_GPRv_MEMv=830, + XED_IFORM_MASKMOVDQU_XMMdq_XMMdq=831, + XED_IFORM_MASKMOVQ_MMXq_MMXq=832, + XED_IFORM_MAXPD_XMMpd_MEMpd=833, + XED_IFORM_MAXPD_XMMpd_XMMpd=834, + XED_IFORM_MAXPS_XMMps_MEMps=835, + XED_IFORM_MAXPS_XMMps_XMMps=836, + XED_IFORM_MAXSD_XMMsd_MEMsd=837, + XED_IFORM_MAXSD_XMMsd_XMMsd=838, + XED_IFORM_MAXSS_XMMss_MEMss=839, + XED_IFORM_MAXSS_XMMss_XMMss=840, + XED_IFORM_MCOMMIT=841, + XED_IFORM_MFENCE=842, + XED_IFORM_MINPD_XMMpd_MEMpd=843, + XED_IFORM_MINPD_XMMpd_XMMpd=844, + XED_IFORM_MINPS_XMMps_MEMps=845, + XED_IFORM_MINPS_XMMps_XMMps=846, + XED_IFORM_MINSD_XMMsd_MEMsd=847, + XED_IFORM_MINSD_XMMsd_XMMsd=848, + XED_IFORM_MINSS_XMMss_MEMss=849, + XED_IFORM_MINSS_XMMss_XMMss=850, + XED_IFORM_MONITOR=851, + XED_IFORM_MONITORX=852, + XED_IFORM_MOV_AL_MEMb=853, + XED_IFORM_MOV_GPR8_GPR8_88=854, + XED_IFORM_MOV_GPR8_GPR8_8A=855, + XED_IFORM_MOV_GPR8_IMMb_B0=856, + XED_IFORM_MOV_GPR8_IMMb_C6r0=857, + XED_IFORM_MOV_GPR8_MEMb=858, + XED_IFORM_MOV_GPRv_GPRv_89=859, + XED_IFORM_MOV_GPRv_GPRv_8B=860, + XED_IFORM_MOV_GPRv_IMMv=861, + XED_IFORM_MOV_GPRv_IMMz=862, + XED_IFORM_MOV_GPRv_MEMv=863, + XED_IFORM_MOV_GPRv_SEG=864, + XED_IFORM_MOV_MEMb_AL=865, + XED_IFORM_MOV_MEMb_GPR8=866, + XED_IFORM_MOV_MEMb_IMMb=867, + XED_IFORM_MOV_MEMv_GPRv=868, + XED_IFORM_MOV_MEMv_IMMz=869, + XED_IFORM_MOV_MEMv_OrAX=870, + XED_IFORM_MOV_MEMw_SEG=871, + XED_IFORM_MOV_OrAX_MEMv=872, + XED_IFORM_MOV_SEG_GPR16=873, + XED_IFORM_MOV_SEG_MEMw=874, + XED_IFORM_MOVAPD_MEMpd_XMMpd=875, + XED_IFORM_MOVAPD_XMMpd_MEMpd=876, + XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28=877, + XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29=878, + XED_IFORM_MOVAPS_MEMps_XMMps=879, + XED_IFORM_MOVAPS_XMMps_MEMps=880, + XED_IFORM_MOVAPS_XMMps_XMMps_0F28=881, + XED_IFORM_MOVAPS_XMMps_XMMps_0F29=882, + XED_IFORM_MOVBE_GPRv_MEMv=883, + XED_IFORM_MOVBE_MEMv_GPRv=884, + XED_IFORM_MOVD_GPR32_MMXd=885, + XED_IFORM_MOVD_GPR32_XMMd=886, + XED_IFORM_MOVD_MEMd_MMXd=887, + XED_IFORM_MOVD_MEMd_XMMd=888, + XED_IFORM_MOVD_MMXq_GPR32=889, + XED_IFORM_MOVD_MMXq_MEMd=890, + XED_IFORM_MOVD_XMMdq_GPR32=891, + XED_IFORM_MOVD_XMMdq_MEMd=892, + XED_IFORM_MOVDDUP_XMMdq_MEMq=893, + XED_IFORM_MOVDDUP_XMMdq_XMMq=894, + XED_IFORM_MOVDIR64B_GPRa_MEM=895, + XED_IFORM_MOVDIRI_MEMu32_GPR32u32=896, + XED_IFORM_MOVDIRI_MEMu64_GPR64u64=897, + XED_IFORM_MOVDQ2Q_MMXq_XMMq=898, + XED_IFORM_MOVDQA_MEMdq_XMMdq=899, + XED_IFORM_MOVDQA_XMMdq_MEMdq=900, + XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F=901, + XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F=902, + XED_IFORM_MOVDQU_MEMdq_XMMdq=903, + XED_IFORM_MOVDQU_XMMdq_MEMdq=904, + XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F=905, + XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F=906, + XED_IFORM_MOVHLPS_XMMq_XMMq=907, + XED_IFORM_MOVHPD_MEMq_XMMsd=908, + XED_IFORM_MOVHPD_XMMsd_MEMq=909, + XED_IFORM_MOVHPS_MEMq_XMMps=910, + XED_IFORM_MOVHPS_XMMq_MEMq=911, + XED_IFORM_MOVLHPS_XMMq_XMMq=912, + XED_IFORM_MOVLPD_MEMq_XMMsd=913, + XED_IFORM_MOVLPD_XMMsd_MEMq=914, + XED_IFORM_MOVLPS_MEMq_XMMq=915, + XED_IFORM_MOVLPS_XMMq_MEMq=916, + XED_IFORM_MOVMSKPD_GPR32_XMMpd=917, + XED_IFORM_MOVMSKPS_GPR32_XMMps=918, + XED_IFORM_MOVNTDQ_MEMdq_XMMdq=919, + XED_IFORM_MOVNTDQA_XMMdq_MEMdq=920, + XED_IFORM_MOVNTI_MEMd_GPR32=921, + XED_IFORM_MOVNTI_MEMq_GPR64=922, + XED_IFORM_MOVNTPD_MEMdq_XMMpd=923, + XED_IFORM_MOVNTPS_MEMdq_XMMps=924, + XED_IFORM_MOVNTQ_MEMq_MMXq=925, + XED_IFORM_MOVNTSD_MEMq_XMMq=926, + XED_IFORM_MOVNTSS_MEMd_XMMd=927, + XED_IFORM_MOVQ_GPR64_MMXq=928, + XED_IFORM_MOVQ_GPR64_XMMq=929, + XED_IFORM_MOVQ_MEMq_MMXq_0F7E=930, + XED_IFORM_MOVQ_MEMq_MMXq_0F7F=931, + XED_IFORM_MOVQ_MEMq_XMMq_0F7E=932, + XED_IFORM_MOVQ_MEMq_XMMq_0FD6=933, + XED_IFORM_MOVQ_MMXq_GPR64=934, + XED_IFORM_MOVQ_MMXq_MEMq_0F6E=935, + XED_IFORM_MOVQ_MMXq_MEMq_0F6F=936, + XED_IFORM_MOVQ_MMXq_MMXq_0F6F=937, + XED_IFORM_MOVQ_MMXq_MMXq_0F7F=938, + XED_IFORM_MOVQ_XMMdq_GPR64=939, + XED_IFORM_MOVQ_XMMdq_MEMq_0F6E=940, + XED_IFORM_MOVQ_XMMdq_MEMq_0F7E=941, + XED_IFORM_MOVQ_XMMdq_XMMq_0F7E=942, + XED_IFORM_MOVQ_XMMdq_XMMq_0FD6=943, + XED_IFORM_MOVQ2DQ_XMMdq_MMXq=944, + XED_IFORM_MOVSB=945, + XED_IFORM_MOVSD=946, + XED_IFORM_MOVSD_XMM_MEMsd_XMMsd=947, + XED_IFORM_MOVSD_XMM_XMMdq_MEMsd=948, + XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10=949, + XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11=950, + XED_IFORM_MOVSHDUP_XMMps_MEMps=951, + XED_IFORM_MOVSHDUP_XMMps_XMMps=952, + XED_IFORM_MOVSLDUP_XMMps_MEMps=953, + XED_IFORM_MOVSLDUP_XMMps_XMMps=954, + XED_IFORM_MOVSQ=955, + XED_IFORM_MOVSS_MEMss_XMMss=956, + XED_IFORM_MOVSS_XMMdq_MEMss=957, + XED_IFORM_MOVSS_XMMss_XMMss_0F10=958, + XED_IFORM_MOVSS_XMMss_XMMss_0F11=959, + XED_IFORM_MOVSW=960, + XED_IFORM_MOVSX_GPRv_GPR16=961, + XED_IFORM_MOVSX_GPRv_GPR8=962, + XED_IFORM_MOVSX_GPRv_MEMb=963, + XED_IFORM_MOVSX_GPRv_MEMw=964, + XED_IFORM_MOVSXD_GPRv_GPRz=965, + XED_IFORM_MOVSXD_GPRv_MEMz=966, + XED_IFORM_MOVUPD_MEMpd_XMMpd=967, + XED_IFORM_MOVUPD_XMMpd_MEMpd=968, + XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10=969, + XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11=970, + XED_IFORM_MOVUPS_MEMps_XMMps=971, + XED_IFORM_MOVUPS_XMMps_MEMps=972, + XED_IFORM_MOVUPS_XMMps_XMMps_0F10=973, + XED_IFORM_MOVUPS_XMMps_XMMps_0F11=974, + XED_IFORM_MOVZX_GPRv_GPR16=975, + XED_IFORM_MOVZX_GPRv_GPR8=976, + XED_IFORM_MOVZX_GPRv_MEMb=977, + XED_IFORM_MOVZX_GPRv_MEMw=978, + XED_IFORM_MOV_CR_CR_GPR32=979, + XED_IFORM_MOV_CR_CR_GPR64=980, + XED_IFORM_MOV_CR_GPR32_CR=981, + XED_IFORM_MOV_CR_GPR64_CR=982, + XED_IFORM_MOV_DR_DR_GPR32=983, + XED_IFORM_MOV_DR_DR_GPR64=984, + XED_IFORM_MOV_DR_GPR32_DR=985, + XED_IFORM_MOV_DR_GPR64_DR=986, + XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb=987, + XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb=988, + XED_IFORM_MUL_GPR8=989, + XED_IFORM_MUL_GPRv=990, + XED_IFORM_MUL_MEMb=991, + XED_IFORM_MUL_MEMv=992, + XED_IFORM_MULPD_XMMpd_MEMpd=993, + XED_IFORM_MULPD_XMMpd_XMMpd=994, + XED_IFORM_MULPS_XMMps_MEMps=995, + XED_IFORM_MULPS_XMMps_XMMps=996, + XED_IFORM_MULSD_XMMsd_MEMsd=997, + XED_IFORM_MULSD_XMMsd_XMMsd=998, + XED_IFORM_MULSS_XMMss_MEMss=999, + XED_IFORM_MULSS_XMMss_XMMss=1000, + XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd=1001, + XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d=1002, + XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq=1003, + XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q=1004, + XED_IFORM_MWAIT=1005, + XED_IFORM_MWAITX=1006, + XED_IFORM_NEG_GPR8=1007, + XED_IFORM_NEG_GPRv=1008, + XED_IFORM_NEG_MEMb=1009, + XED_IFORM_NEG_MEMv=1010, + XED_IFORM_NEG_LOCK_MEMb=1011, + XED_IFORM_NEG_LOCK_MEMv=1012, + XED_IFORM_NOP_90=1013, + XED_IFORM_NOP_GPRv_0F18r0=1014, + XED_IFORM_NOP_GPRv_0F18r1=1015, + XED_IFORM_NOP_GPRv_0F18r2=1016, + XED_IFORM_NOP_GPRv_0F18r3=1017, + XED_IFORM_NOP_GPRv_0F18r4=1018, + XED_IFORM_NOP_GPRv_0F18r5=1019, + XED_IFORM_NOP_GPRv_0F18r6=1020, + XED_IFORM_NOP_GPRv_0F18r7=1021, + XED_IFORM_NOP_GPRv_GPRv_0F0D=1022, + XED_IFORM_NOP_GPRv_GPRv_0F19=1023, + XED_IFORM_NOP_GPRv_GPRv_0F1A=1024, + XED_IFORM_NOP_GPRv_GPRv_0F1B=1025, + XED_IFORM_NOP_GPRv_GPRv_0F1C=1026, + XED_IFORM_NOP_GPRv_GPRv_0F1D=1027, + XED_IFORM_NOP_GPRv_GPRv_0F1E=1028, + XED_IFORM_NOP_GPRv_GPRv_0F1F=1029, + XED_IFORM_NOP_GPRv_MEM_0F1B=1030, + XED_IFORM_NOP_GPRv_MEMv_0F1A=1031, + XED_IFORM_NOP_MEMv_0F18r4=1032, + XED_IFORM_NOP_MEMv_0F18r5=1033, + XED_IFORM_NOP_MEMv_0F18r6=1034, + XED_IFORM_NOP_MEMv_0F18r7=1035, + XED_IFORM_NOP_MEMv_GPRv_0F19=1036, + XED_IFORM_NOP_MEMv_GPRv_0F1C=1037, + XED_IFORM_NOP_MEMv_GPRv_0F1D=1038, + XED_IFORM_NOP_MEMv_GPRv_0F1E=1039, + XED_IFORM_NOP_MEMv_GPRv_0F1F=1040, + XED_IFORM_NOT_GPR8=1041, + XED_IFORM_NOT_GPRv=1042, + XED_IFORM_NOT_MEMb=1043, + XED_IFORM_NOT_MEMv=1044, + XED_IFORM_NOT_LOCK_MEMb=1045, + XED_IFORM_NOT_LOCK_MEMv=1046, + XED_IFORM_OR_AL_IMMb=1047, + XED_IFORM_OR_GPR8_GPR8_08=1048, + XED_IFORM_OR_GPR8_GPR8_0A=1049, + XED_IFORM_OR_GPR8_IMMb_80r1=1050, + XED_IFORM_OR_GPR8_IMMb_82r1=1051, + XED_IFORM_OR_GPR8_MEMb=1052, + XED_IFORM_OR_GPRv_GPRv_09=1053, + XED_IFORM_OR_GPRv_GPRv_0B=1054, + XED_IFORM_OR_GPRv_IMMb=1055, + XED_IFORM_OR_GPRv_IMMz=1056, + XED_IFORM_OR_GPRv_MEMv=1057, + XED_IFORM_OR_MEMb_GPR8=1058, + XED_IFORM_OR_MEMb_IMMb_80r1=1059, + XED_IFORM_OR_MEMb_IMMb_82r1=1060, + XED_IFORM_OR_MEMv_GPRv=1061, + XED_IFORM_OR_MEMv_IMMb=1062, + XED_IFORM_OR_MEMv_IMMz=1063, + XED_IFORM_OR_OrAX_IMMz=1064, + XED_IFORM_ORPD_XMMxuq_MEMxuq=1065, + XED_IFORM_ORPD_XMMxuq_XMMxuq=1066, + XED_IFORM_ORPS_XMMxud_MEMxud=1067, + XED_IFORM_ORPS_XMMxud_XMMxud=1068, + XED_IFORM_OR_LOCK_MEMb_GPR8=1069, + XED_IFORM_OR_LOCK_MEMb_IMMb_80r1=1070, + XED_IFORM_OR_LOCK_MEMb_IMMb_82r1=1071, + XED_IFORM_OR_LOCK_MEMv_GPRv=1072, + XED_IFORM_OR_LOCK_MEMv_IMMb=1073, + XED_IFORM_OR_LOCK_MEMv_IMMz=1074, + XED_IFORM_OUT_DX_AL=1075, + XED_IFORM_OUT_DX_OeAX=1076, + XED_IFORM_OUT_IMMb_AL=1077, + XED_IFORM_OUT_IMMb_OeAX=1078, + XED_IFORM_OUTSB=1079, + XED_IFORM_OUTSD=1080, + XED_IFORM_OUTSW=1081, + XED_IFORM_PABSB_MMXq_MEMq=1082, + XED_IFORM_PABSB_MMXq_MMXq=1083, + XED_IFORM_PABSB_XMMdq_MEMdq=1084, + XED_IFORM_PABSB_XMMdq_XMMdq=1085, + XED_IFORM_PABSD_MMXq_MEMq=1086, + XED_IFORM_PABSD_MMXq_MMXq=1087, + XED_IFORM_PABSD_XMMdq_MEMdq=1088, + XED_IFORM_PABSD_XMMdq_XMMdq=1089, + XED_IFORM_PABSW_MMXq_MEMq=1090, + XED_IFORM_PABSW_MMXq_MMXq=1091, + XED_IFORM_PABSW_XMMdq_MEMdq=1092, + XED_IFORM_PABSW_XMMdq_XMMdq=1093, + XED_IFORM_PACKSSDW_MMXq_MEMq=1094, + XED_IFORM_PACKSSDW_MMXq_MMXq=1095, + XED_IFORM_PACKSSDW_XMMdq_MEMdq=1096, + XED_IFORM_PACKSSDW_XMMdq_XMMdq=1097, + XED_IFORM_PACKSSWB_MMXq_MEMq=1098, + XED_IFORM_PACKSSWB_MMXq_MMXq=1099, + XED_IFORM_PACKSSWB_XMMdq_MEMdq=1100, + XED_IFORM_PACKSSWB_XMMdq_XMMdq=1101, + XED_IFORM_PACKUSDW_XMMdq_MEMdq=1102, + XED_IFORM_PACKUSDW_XMMdq_XMMdq=1103, + XED_IFORM_PACKUSWB_MMXq_MEMq=1104, + XED_IFORM_PACKUSWB_MMXq_MMXq=1105, + XED_IFORM_PACKUSWB_XMMdq_MEMdq=1106, + XED_IFORM_PACKUSWB_XMMdq_XMMdq=1107, + XED_IFORM_PADDB_MMXq_MEMq=1108, + XED_IFORM_PADDB_MMXq_MMXq=1109, + XED_IFORM_PADDB_XMMdq_MEMdq=1110, + XED_IFORM_PADDB_XMMdq_XMMdq=1111, + XED_IFORM_PADDD_MMXq_MEMq=1112, + XED_IFORM_PADDD_MMXq_MMXq=1113, + XED_IFORM_PADDD_XMMdq_MEMdq=1114, + XED_IFORM_PADDD_XMMdq_XMMdq=1115, + XED_IFORM_PADDQ_MMXq_MEMq=1116, + XED_IFORM_PADDQ_MMXq_MMXq=1117, + XED_IFORM_PADDQ_XMMdq_MEMdq=1118, + XED_IFORM_PADDQ_XMMdq_XMMdq=1119, + XED_IFORM_PADDSB_MMXq_MEMq=1120, + XED_IFORM_PADDSB_MMXq_MMXq=1121, + XED_IFORM_PADDSB_XMMdq_MEMdq=1122, + XED_IFORM_PADDSB_XMMdq_XMMdq=1123, + XED_IFORM_PADDSW_MMXq_MEMq=1124, + XED_IFORM_PADDSW_MMXq_MMXq=1125, + XED_IFORM_PADDSW_XMMdq_MEMdq=1126, + XED_IFORM_PADDSW_XMMdq_XMMdq=1127, + XED_IFORM_PADDUSB_MMXq_MEMq=1128, + XED_IFORM_PADDUSB_MMXq_MMXq=1129, + XED_IFORM_PADDUSB_XMMdq_MEMdq=1130, + XED_IFORM_PADDUSB_XMMdq_XMMdq=1131, + XED_IFORM_PADDUSW_MMXq_MEMq=1132, + XED_IFORM_PADDUSW_MMXq_MMXq=1133, + XED_IFORM_PADDUSW_XMMdq_MEMdq=1134, + XED_IFORM_PADDUSW_XMMdq_XMMdq=1135, + XED_IFORM_PADDW_MMXq_MEMq=1136, + XED_IFORM_PADDW_MMXq_MMXq=1137, + XED_IFORM_PADDW_XMMdq_MEMdq=1138, + XED_IFORM_PADDW_XMMdq_XMMdq=1139, + XED_IFORM_PALIGNR_MMXq_MEMq_IMMb=1140, + XED_IFORM_PALIGNR_MMXq_MMXq_IMMb=1141, + XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb=1142, + XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb=1143, + XED_IFORM_PAND_MMXq_MEMq=1144, + XED_IFORM_PAND_MMXq_MMXq=1145, + XED_IFORM_PAND_XMMdq_MEMdq=1146, + XED_IFORM_PAND_XMMdq_XMMdq=1147, + XED_IFORM_PANDN_MMXq_MEMq=1148, + XED_IFORM_PANDN_MMXq_MMXq=1149, + XED_IFORM_PANDN_XMMdq_MEMdq=1150, + XED_IFORM_PANDN_XMMdq_XMMdq=1151, + XED_IFORM_PAUSE=1152, + XED_IFORM_PAVGB_MMXq_MEMq=1153, + XED_IFORM_PAVGB_MMXq_MMXq=1154, + XED_IFORM_PAVGB_XMMdq_MEMdq=1155, + XED_IFORM_PAVGB_XMMdq_XMMdq=1156, + XED_IFORM_PAVGUSB_MMXq_MEMq=1157, + XED_IFORM_PAVGUSB_MMXq_MMXq=1158, + XED_IFORM_PAVGW_MMXq_MEMq=1159, + XED_IFORM_PAVGW_MMXq_MMXq=1160, + XED_IFORM_PAVGW_XMMdq_MEMdq=1161, + XED_IFORM_PAVGW_XMMdq_XMMdq=1162, + XED_IFORM_PBLENDVB_XMMdq_MEMdq=1163, + XED_IFORM_PBLENDVB_XMMdq_XMMdq=1164, + XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb=1165, + XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb=1166, + XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb=1167, + XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb=1168, + XED_IFORM_PCMPEQB_MMXq_MEMq=1169, + XED_IFORM_PCMPEQB_MMXq_MMXq=1170, + XED_IFORM_PCMPEQB_XMMdq_MEMdq=1171, + XED_IFORM_PCMPEQB_XMMdq_XMMdq=1172, + XED_IFORM_PCMPEQD_MMXq_MEMq=1173, + XED_IFORM_PCMPEQD_MMXq_MMXq=1174, + XED_IFORM_PCMPEQD_XMMdq_MEMdq=1175, + XED_IFORM_PCMPEQD_XMMdq_XMMdq=1176, + XED_IFORM_PCMPEQQ_XMMdq_MEMdq=1177, + XED_IFORM_PCMPEQQ_XMMdq_XMMdq=1178, + XED_IFORM_PCMPEQW_MMXq_MEMq=1179, + XED_IFORM_PCMPEQW_MMXq_MMXq=1180, + XED_IFORM_PCMPEQW_XMMdq_MEMdq=1181, + XED_IFORM_PCMPEQW_XMMdq_XMMdq=1182, + XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb=1183, + XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb=1184, + XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb=1185, + XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb=1186, + XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb=1187, + XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb=1188, + XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb=1189, + XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb=1190, + XED_IFORM_PCMPGTB_MMXq_MEMq=1191, + XED_IFORM_PCMPGTB_MMXq_MMXq=1192, + XED_IFORM_PCMPGTB_XMMdq_MEMdq=1193, + XED_IFORM_PCMPGTB_XMMdq_XMMdq=1194, + XED_IFORM_PCMPGTD_MMXq_MEMq=1195, + XED_IFORM_PCMPGTD_MMXq_MMXq=1196, + XED_IFORM_PCMPGTD_XMMdq_MEMdq=1197, + XED_IFORM_PCMPGTD_XMMdq_XMMdq=1198, + XED_IFORM_PCMPGTQ_XMMdq_MEMdq=1199, + XED_IFORM_PCMPGTQ_XMMdq_XMMdq=1200, + XED_IFORM_PCMPGTW_MMXq_MEMq=1201, + XED_IFORM_PCMPGTW_MMXq_MMXq=1202, + XED_IFORM_PCMPGTW_XMMdq_MEMdq=1203, + XED_IFORM_PCMPGTW_XMMdq_XMMdq=1204, + XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb=1205, + XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb=1206, + XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb=1207, + XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb=1208, + XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb=1209, + XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb=1210, + XED_IFORM_PCONFIG=1211, + XED_IFORM_PCONFIG64=1212, + XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd=1213, + XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d=1214, + XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq=1215, + XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q=1216, + XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd=1217, + XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d=1218, + XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq=1219, + XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q=1220, + XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb=1221, + XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb=1222, + XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb=1223, + XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb=1224, + XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb=1225, + XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb=1226, + XED_IFORM_PEXTRW_GPR32_MMXq_IMMb=1227, + XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb=1228, + XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb=1229, + XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb=1230, + XED_IFORM_PF2ID_MMXq_MEMq=1231, + XED_IFORM_PF2ID_MMXq_MMXq=1232, + XED_IFORM_PF2IW_MMXq_MEMq=1233, + XED_IFORM_PF2IW_MMXq_MMXq=1234, + XED_IFORM_PFACC_MMXq_MEMq=1235, + XED_IFORM_PFACC_MMXq_MMXq=1236, + XED_IFORM_PFADD_MMXq_MEMq=1237, + XED_IFORM_PFADD_MMXq_MMXq=1238, + XED_IFORM_PFCMPEQ_MMXq_MEMq=1239, + XED_IFORM_PFCMPEQ_MMXq_MMXq=1240, + XED_IFORM_PFCMPGE_MMXq_MEMq=1241, + XED_IFORM_PFCMPGE_MMXq_MMXq=1242, + XED_IFORM_PFCMPGT_MMXq_MEMq=1243, + XED_IFORM_PFCMPGT_MMXq_MMXq=1244, + XED_IFORM_PFMAX_MMXq_MEMq=1245, + XED_IFORM_PFMAX_MMXq_MMXq=1246, + XED_IFORM_PFMIN_MMXq_MEMq=1247, + XED_IFORM_PFMIN_MMXq_MMXq=1248, + XED_IFORM_PFMUL_MMXq_MEMq=1249, + XED_IFORM_PFMUL_MMXq_MMXq=1250, + XED_IFORM_PFNACC_MMXq_MEMq=1251, + XED_IFORM_PFNACC_MMXq_MMXq=1252, + XED_IFORM_PFPNACC_MMXq_MEMq=1253, + XED_IFORM_PFPNACC_MMXq_MMXq=1254, + XED_IFORM_PFRCP_MMXq_MEMq=1255, + XED_IFORM_PFRCP_MMXq_MMXq=1256, + XED_IFORM_PFRCPIT1_MMXq_MEMq=1257, + XED_IFORM_PFRCPIT1_MMXq_MMXq=1258, + XED_IFORM_PFRCPIT2_MMXq_MEMq=1259, + XED_IFORM_PFRCPIT2_MMXq_MMXq=1260, + XED_IFORM_PFRSQIT1_MMXq_MEMq=1261, + XED_IFORM_PFRSQIT1_MMXq_MMXq=1262, + XED_IFORM_PFRSQRT_MMXq_MEMq=1263, + XED_IFORM_PFRSQRT_MMXq_MMXq=1264, + XED_IFORM_PFSUB_MMXq_MEMq=1265, + XED_IFORM_PFSUB_MMXq_MMXq=1266, + XED_IFORM_PFSUBR_MMXq_MEMq=1267, + XED_IFORM_PFSUBR_MMXq_MMXq=1268, + XED_IFORM_PHADDD_MMXq_MEMq=1269, + XED_IFORM_PHADDD_MMXq_MMXq=1270, + XED_IFORM_PHADDD_XMMdq_MEMdq=1271, + XED_IFORM_PHADDD_XMMdq_XMMdq=1272, + XED_IFORM_PHADDSW_MMXq_MEMq=1273, + XED_IFORM_PHADDSW_MMXq_MMXq=1274, + XED_IFORM_PHADDSW_XMMdq_MEMdq=1275, + XED_IFORM_PHADDSW_XMMdq_XMMdq=1276, + XED_IFORM_PHADDW_MMXq_MEMq=1277, + XED_IFORM_PHADDW_MMXq_MMXq=1278, + XED_IFORM_PHADDW_XMMdq_MEMdq=1279, + XED_IFORM_PHADDW_XMMdq_XMMdq=1280, + XED_IFORM_PHMINPOSUW_XMMdq_MEMdq=1281, + XED_IFORM_PHMINPOSUW_XMMdq_XMMdq=1282, + XED_IFORM_PHSUBD_MMXq_MEMq=1283, + XED_IFORM_PHSUBD_MMXq_MMXq=1284, + XED_IFORM_PHSUBD_XMMdq_MEMdq=1285, + XED_IFORM_PHSUBD_XMMdq_XMMdq=1286, + XED_IFORM_PHSUBSW_MMXq_MEMq=1287, + XED_IFORM_PHSUBSW_MMXq_MMXq=1288, + XED_IFORM_PHSUBSW_XMMdq_MEMdq=1289, + XED_IFORM_PHSUBSW_XMMdq_XMMdq=1290, + XED_IFORM_PHSUBW_MMXq_MEMq=1291, + XED_IFORM_PHSUBW_MMXq_MMXq=1292, + XED_IFORM_PHSUBW_XMMdq_MEMdq=1293, + XED_IFORM_PHSUBW_XMMdq_XMMdq=1294, + XED_IFORM_PI2FD_MMXq_MEMq=1295, + XED_IFORM_PI2FD_MMXq_MMXq=1296, + XED_IFORM_PI2FW_MMXq_MEMq=1297, + XED_IFORM_PI2FW_MMXq_MMXq=1298, + XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb=1299, + XED_IFORM_PINSRB_XMMdq_MEMb_IMMb=1300, + XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb=1301, + XED_IFORM_PINSRD_XMMdq_MEMd_IMMb=1302, + XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb=1303, + XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb=1304, + XED_IFORM_PINSRW_MMXq_GPR32_IMMb=1305, + XED_IFORM_PINSRW_MMXq_MEMw_IMMb=1306, + XED_IFORM_PINSRW_XMMdq_GPR32_IMMb=1307, + XED_IFORM_PINSRW_XMMdq_MEMw_IMMb=1308, + XED_IFORM_PMADDUBSW_MMXq_MEMq=1309, + XED_IFORM_PMADDUBSW_MMXq_MMXq=1310, + XED_IFORM_PMADDUBSW_XMMdq_MEMdq=1311, + XED_IFORM_PMADDUBSW_XMMdq_XMMdq=1312, + XED_IFORM_PMADDWD_MMXq_MEMq=1313, + XED_IFORM_PMADDWD_MMXq_MMXq=1314, + XED_IFORM_PMADDWD_XMMdq_MEMdq=1315, + XED_IFORM_PMADDWD_XMMdq_XMMdq=1316, + XED_IFORM_PMAXSB_XMMdq_MEMdq=1317, + XED_IFORM_PMAXSB_XMMdq_XMMdq=1318, + XED_IFORM_PMAXSD_XMMdq_MEMdq=1319, + XED_IFORM_PMAXSD_XMMdq_XMMdq=1320, + XED_IFORM_PMAXSW_MMXq_MEMq=1321, + XED_IFORM_PMAXSW_MMXq_MMXq=1322, + XED_IFORM_PMAXSW_XMMdq_MEMdq=1323, + XED_IFORM_PMAXSW_XMMdq_XMMdq=1324, + XED_IFORM_PMAXUB_MMXq_MEMq=1325, + XED_IFORM_PMAXUB_MMXq_MMXq=1326, + XED_IFORM_PMAXUB_XMMdq_MEMdq=1327, + XED_IFORM_PMAXUB_XMMdq_XMMdq=1328, + XED_IFORM_PMAXUD_XMMdq_MEMdq=1329, + XED_IFORM_PMAXUD_XMMdq_XMMdq=1330, + XED_IFORM_PMAXUW_XMMdq_MEMdq=1331, + XED_IFORM_PMAXUW_XMMdq_XMMdq=1332, + XED_IFORM_PMINSB_XMMdq_MEMdq=1333, + XED_IFORM_PMINSB_XMMdq_XMMdq=1334, + XED_IFORM_PMINSD_XMMdq_MEMdq=1335, + XED_IFORM_PMINSD_XMMdq_XMMdq=1336, + XED_IFORM_PMINSW_MMXq_MEMq=1337, + XED_IFORM_PMINSW_MMXq_MMXq=1338, + XED_IFORM_PMINSW_XMMdq_MEMdq=1339, + XED_IFORM_PMINSW_XMMdq_XMMdq=1340, + XED_IFORM_PMINUB_MMXq_MEMq=1341, + XED_IFORM_PMINUB_MMXq_MMXq=1342, + XED_IFORM_PMINUB_XMMdq_MEMdq=1343, + XED_IFORM_PMINUB_XMMdq_XMMdq=1344, + XED_IFORM_PMINUD_XMMdq_MEMdq=1345, + XED_IFORM_PMINUD_XMMdq_XMMdq=1346, + XED_IFORM_PMINUW_XMMdq_MEMdq=1347, + XED_IFORM_PMINUW_XMMdq_XMMdq=1348, + XED_IFORM_PMOVMSKB_GPR32_MMXq=1349, + XED_IFORM_PMOVMSKB_GPR32_XMMdq=1350, + XED_IFORM_PMOVSXBD_XMMdq_MEMd=1351, + XED_IFORM_PMOVSXBD_XMMdq_XMMd=1352, + XED_IFORM_PMOVSXBQ_XMMdq_MEMw=1353, + XED_IFORM_PMOVSXBQ_XMMdq_XMMw=1354, + XED_IFORM_PMOVSXBW_XMMdq_MEMq=1355, + XED_IFORM_PMOVSXBW_XMMdq_XMMq=1356, + XED_IFORM_PMOVSXDQ_XMMdq_MEMq=1357, + XED_IFORM_PMOVSXDQ_XMMdq_XMMq=1358, + XED_IFORM_PMOVSXWD_XMMdq_MEMq=1359, + XED_IFORM_PMOVSXWD_XMMdq_XMMq=1360, + XED_IFORM_PMOVSXWQ_XMMdq_MEMd=1361, + XED_IFORM_PMOVSXWQ_XMMdq_XMMd=1362, + XED_IFORM_PMOVZXBD_XMMdq_MEMd=1363, + XED_IFORM_PMOVZXBD_XMMdq_XMMd=1364, + XED_IFORM_PMOVZXBQ_XMMdq_MEMw=1365, + XED_IFORM_PMOVZXBQ_XMMdq_XMMw=1366, + XED_IFORM_PMOVZXBW_XMMdq_MEMq=1367, + XED_IFORM_PMOVZXBW_XMMdq_XMMq=1368, + XED_IFORM_PMOVZXDQ_XMMdq_MEMq=1369, + XED_IFORM_PMOVZXDQ_XMMdq_XMMq=1370, + XED_IFORM_PMOVZXWD_XMMdq_MEMq=1371, + XED_IFORM_PMOVZXWD_XMMdq_XMMq=1372, + XED_IFORM_PMOVZXWQ_XMMdq_MEMd=1373, + XED_IFORM_PMOVZXWQ_XMMdq_XMMd=1374, + XED_IFORM_PMULDQ_XMMdq_MEMdq=1375, + XED_IFORM_PMULDQ_XMMdq_XMMdq=1376, + XED_IFORM_PMULHRSW_MMXq_MEMq=1377, + XED_IFORM_PMULHRSW_MMXq_MMXq=1378, + XED_IFORM_PMULHRSW_XMMdq_MEMdq=1379, + XED_IFORM_PMULHRSW_XMMdq_XMMdq=1380, + XED_IFORM_PMULHRW_MMXq_MEMq=1381, + XED_IFORM_PMULHRW_MMXq_MMXq=1382, + XED_IFORM_PMULHUW_MMXq_MEMq=1383, + XED_IFORM_PMULHUW_MMXq_MMXq=1384, + XED_IFORM_PMULHUW_XMMdq_MEMdq=1385, + XED_IFORM_PMULHUW_XMMdq_XMMdq=1386, + XED_IFORM_PMULHW_MMXq_MEMq=1387, + XED_IFORM_PMULHW_MMXq_MMXq=1388, + XED_IFORM_PMULHW_XMMdq_MEMdq=1389, + XED_IFORM_PMULHW_XMMdq_XMMdq=1390, + XED_IFORM_PMULLD_XMMdq_MEMdq=1391, + XED_IFORM_PMULLD_XMMdq_XMMdq=1392, + XED_IFORM_PMULLW_MMXq_MEMq=1393, + XED_IFORM_PMULLW_MMXq_MMXq=1394, + XED_IFORM_PMULLW_XMMdq_MEMdq=1395, + XED_IFORM_PMULLW_XMMdq_XMMdq=1396, + XED_IFORM_PMULUDQ_MMXq_MEMq=1397, + XED_IFORM_PMULUDQ_MMXq_MMXq=1398, + XED_IFORM_PMULUDQ_XMMdq_MEMdq=1399, + XED_IFORM_PMULUDQ_XMMdq_XMMdq=1400, + XED_IFORM_POP_DS=1401, + XED_IFORM_POP_ES=1402, + XED_IFORM_POP_FS=1403, + XED_IFORM_POP_GPRv_58=1404, + XED_IFORM_POP_GPRv_8F=1405, + XED_IFORM_POP_GS=1406, + XED_IFORM_POP_MEMv=1407, + XED_IFORM_POP_SS=1408, + XED_IFORM_POPA=1409, + XED_IFORM_POPAD=1410, + XED_IFORM_POPCNT_GPRv_GPRv=1411, + XED_IFORM_POPCNT_GPRv_MEMv=1412, + XED_IFORM_POPF=1413, + XED_IFORM_POPFD=1414, + XED_IFORM_POPFQ=1415, + XED_IFORM_POR_MMXq_MEMq=1416, + XED_IFORM_POR_MMXq_MMXq=1417, + XED_IFORM_POR_XMMdq_MEMdq=1418, + XED_IFORM_POR_XMMdq_XMMdq=1419, + XED_IFORM_PREFETCHNTA_MEMmprefetch=1420, + XED_IFORM_PREFETCHT0_MEMmprefetch=1421, + XED_IFORM_PREFETCHT1_MEMmprefetch=1422, + XED_IFORM_PREFETCHT2_MEMmprefetch=1423, + XED_IFORM_PREFETCHW_0F0Dr1=1424, + XED_IFORM_PREFETCHW_0F0Dr3=1425, + XED_IFORM_PREFETCHWT1_MEMu8=1426, + XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch=1427, + XED_IFORM_PREFETCH_RESERVED_0F0Dr4=1428, + XED_IFORM_PREFETCH_RESERVED_0F0Dr5=1429, + XED_IFORM_PREFETCH_RESERVED_0F0Dr6=1430, + XED_IFORM_PREFETCH_RESERVED_0F0Dr7=1431, + XED_IFORM_PSADBW_MMXq_MEMq=1432, + XED_IFORM_PSADBW_MMXq_MMXq=1433, + XED_IFORM_PSADBW_XMMdq_MEMdq=1434, + XED_IFORM_PSADBW_XMMdq_XMMdq=1435, + XED_IFORM_PSHUFB_MMXq_MEMq=1436, + XED_IFORM_PSHUFB_MMXq_MMXq=1437, + XED_IFORM_PSHUFB_XMMdq_MEMdq=1438, + XED_IFORM_PSHUFB_XMMdq_XMMdq=1439, + XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb=1440, + XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb=1441, + XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb=1442, + XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb=1443, + XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb=1444, + XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb=1445, + XED_IFORM_PSHUFW_MMXq_MEMq_IMMb=1446, + XED_IFORM_PSHUFW_MMXq_MMXq_IMMb=1447, + XED_IFORM_PSIGNB_MMXq_MEMq=1448, + XED_IFORM_PSIGNB_MMXq_MMXq=1449, + XED_IFORM_PSIGNB_XMMdq_MEMdq=1450, + XED_IFORM_PSIGNB_XMMdq_XMMdq=1451, + XED_IFORM_PSIGND_MMXq_MEMq=1452, + XED_IFORM_PSIGND_MMXq_MMXq=1453, + XED_IFORM_PSIGND_XMMdq_MEMdq=1454, + XED_IFORM_PSIGND_XMMdq_XMMdq=1455, + XED_IFORM_PSIGNW_MMXq_MEMq=1456, + XED_IFORM_PSIGNW_MMXq_MMXq=1457, + XED_IFORM_PSIGNW_XMMdq_MEMdq=1458, + XED_IFORM_PSIGNW_XMMdq_XMMdq=1459, + XED_IFORM_PSLLD_MMXq_IMMb=1460, + XED_IFORM_PSLLD_MMXq_MEMq=1461, + XED_IFORM_PSLLD_MMXq_MMXq=1462, + XED_IFORM_PSLLD_XMMdq_IMMb=1463, + XED_IFORM_PSLLD_XMMdq_MEMdq=1464, + XED_IFORM_PSLLD_XMMdq_XMMdq=1465, + XED_IFORM_PSLLDQ_XMMdq_IMMb=1466, + XED_IFORM_PSLLQ_MMXq_IMMb=1467, + XED_IFORM_PSLLQ_MMXq_MEMq=1468, + XED_IFORM_PSLLQ_MMXq_MMXq=1469, + XED_IFORM_PSLLQ_XMMdq_IMMb=1470, + XED_IFORM_PSLLQ_XMMdq_MEMdq=1471, + XED_IFORM_PSLLQ_XMMdq_XMMdq=1472, + XED_IFORM_PSLLW_MMXq_IMMb=1473, + XED_IFORM_PSLLW_MMXq_MEMq=1474, + XED_IFORM_PSLLW_MMXq_MMXq=1475, + XED_IFORM_PSLLW_XMMdq_IMMb=1476, + XED_IFORM_PSLLW_XMMdq_MEMdq=1477, + XED_IFORM_PSLLW_XMMdq_XMMdq=1478, + XED_IFORM_PSMASH_RAX=1479, + XED_IFORM_PSRAD_MMXq_IMMb=1480, + XED_IFORM_PSRAD_MMXq_MEMq=1481, + XED_IFORM_PSRAD_MMXq_MMXq=1482, + XED_IFORM_PSRAD_XMMdq_IMMb=1483, + XED_IFORM_PSRAD_XMMdq_MEMdq=1484, + XED_IFORM_PSRAD_XMMdq_XMMdq=1485, + XED_IFORM_PSRAW_MMXq_IMMb=1486, + XED_IFORM_PSRAW_MMXq_MEMq=1487, + XED_IFORM_PSRAW_MMXq_MMXq=1488, + XED_IFORM_PSRAW_XMMdq_IMMb=1489, + XED_IFORM_PSRAW_XMMdq_MEMdq=1490, + XED_IFORM_PSRAW_XMMdq_XMMdq=1491, + XED_IFORM_PSRLD_MMXq_IMMb=1492, + XED_IFORM_PSRLD_MMXq_MEMq=1493, + XED_IFORM_PSRLD_MMXq_MMXq=1494, + XED_IFORM_PSRLD_XMMdq_IMMb=1495, + XED_IFORM_PSRLD_XMMdq_MEMdq=1496, + XED_IFORM_PSRLD_XMMdq_XMMdq=1497, + XED_IFORM_PSRLDQ_XMMdq_IMMb=1498, + XED_IFORM_PSRLQ_MMXq_IMMb=1499, + XED_IFORM_PSRLQ_MMXq_MEMq=1500, + XED_IFORM_PSRLQ_MMXq_MMXq=1501, + XED_IFORM_PSRLQ_XMMdq_IMMb=1502, + XED_IFORM_PSRLQ_XMMdq_MEMdq=1503, + XED_IFORM_PSRLQ_XMMdq_XMMdq=1504, + XED_IFORM_PSRLW_MMXq_IMMb=1505, + XED_IFORM_PSRLW_MMXq_MEMq=1506, + XED_IFORM_PSRLW_MMXq_MMXq=1507, + XED_IFORM_PSRLW_XMMdq_IMMb=1508, + XED_IFORM_PSRLW_XMMdq_MEMdq=1509, + XED_IFORM_PSRLW_XMMdq_XMMdq=1510, + XED_IFORM_PSUBB_MMXq_MEMq=1511, + XED_IFORM_PSUBB_MMXq_MMXq=1512, + XED_IFORM_PSUBB_XMMdq_MEMdq=1513, + XED_IFORM_PSUBB_XMMdq_XMMdq=1514, + XED_IFORM_PSUBD_MMXq_MEMq=1515, + XED_IFORM_PSUBD_MMXq_MMXq=1516, + XED_IFORM_PSUBD_XMMdq_MEMdq=1517, + XED_IFORM_PSUBD_XMMdq_XMMdq=1518, + XED_IFORM_PSUBQ_MMXq_MEMq=1519, + XED_IFORM_PSUBQ_MMXq_MMXq=1520, + XED_IFORM_PSUBQ_XMMdq_MEMdq=1521, + XED_IFORM_PSUBQ_XMMdq_XMMdq=1522, + XED_IFORM_PSUBSB_MMXq_MEMq=1523, + XED_IFORM_PSUBSB_MMXq_MMXq=1524, + XED_IFORM_PSUBSB_XMMdq_MEMdq=1525, + XED_IFORM_PSUBSB_XMMdq_XMMdq=1526, + XED_IFORM_PSUBSW_MMXq_MEMq=1527, + XED_IFORM_PSUBSW_MMXq_MMXq=1528, + XED_IFORM_PSUBSW_XMMdq_MEMdq=1529, + XED_IFORM_PSUBSW_XMMdq_XMMdq=1530, + XED_IFORM_PSUBUSB_MMXq_MEMq=1531, + XED_IFORM_PSUBUSB_MMXq_MMXq=1532, + XED_IFORM_PSUBUSB_XMMdq_MEMdq=1533, + XED_IFORM_PSUBUSB_XMMdq_XMMdq=1534, + XED_IFORM_PSUBUSW_MMXq_MEMq=1535, + XED_IFORM_PSUBUSW_MMXq_MMXq=1536, + XED_IFORM_PSUBUSW_XMMdq_MEMdq=1537, + XED_IFORM_PSUBUSW_XMMdq_XMMdq=1538, + XED_IFORM_PSUBW_MMXq_MEMq=1539, + XED_IFORM_PSUBW_MMXq_MMXq=1540, + XED_IFORM_PSUBW_XMMdq_MEMdq=1541, + XED_IFORM_PSUBW_XMMdq_XMMdq=1542, + XED_IFORM_PSWAPD_MMXq_MEMq=1543, + XED_IFORM_PSWAPD_MMXq_MMXq=1544, + XED_IFORM_PTEST_XMMdq_MEMdq=1545, + XED_IFORM_PTEST_XMMdq_XMMdq=1546, + XED_IFORM_PTWRITE_GPRy=1547, + XED_IFORM_PTWRITE_MEMy=1548, + XED_IFORM_PUNPCKHBW_MMXq_MEMq=1549, + XED_IFORM_PUNPCKHBW_MMXq_MMXd=1550, + XED_IFORM_PUNPCKHBW_XMMdq_MEMdq=1551, + XED_IFORM_PUNPCKHBW_XMMdq_XMMq=1552, + XED_IFORM_PUNPCKHDQ_MMXq_MEMq=1553, + XED_IFORM_PUNPCKHDQ_MMXq_MMXd=1554, + XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq=1555, + XED_IFORM_PUNPCKHDQ_XMMdq_XMMq=1556, + XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq=1557, + XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq=1558, + XED_IFORM_PUNPCKHWD_MMXq_MEMq=1559, + XED_IFORM_PUNPCKHWD_MMXq_MMXd=1560, + XED_IFORM_PUNPCKHWD_XMMdq_MEMdq=1561, + XED_IFORM_PUNPCKHWD_XMMdq_XMMq=1562, + XED_IFORM_PUNPCKLBW_MMXq_MEMd=1563, + XED_IFORM_PUNPCKLBW_MMXq_MMXd=1564, + XED_IFORM_PUNPCKLBW_XMMdq_MEMdq=1565, + XED_IFORM_PUNPCKLBW_XMMdq_XMMq=1566, + XED_IFORM_PUNPCKLDQ_MMXq_MEMd=1567, + XED_IFORM_PUNPCKLDQ_MMXq_MMXd=1568, + XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq=1569, + XED_IFORM_PUNPCKLDQ_XMMdq_XMMq=1570, + XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq=1571, + XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq=1572, + XED_IFORM_PUNPCKLWD_MMXq_MEMd=1573, + XED_IFORM_PUNPCKLWD_MMXq_MMXd=1574, + XED_IFORM_PUNPCKLWD_XMMdq_MEMdq=1575, + XED_IFORM_PUNPCKLWD_XMMdq_XMMq=1576, + XED_IFORM_PUSH_CS=1577, + XED_IFORM_PUSH_DS=1578, + XED_IFORM_PUSH_ES=1579, + XED_IFORM_PUSH_FS=1580, + XED_IFORM_PUSH_GPRv_50=1581, + XED_IFORM_PUSH_GPRv_FFr6=1582, + XED_IFORM_PUSH_GS=1583, + XED_IFORM_PUSH_IMMb=1584, + XED_IFORM_PUSH_IMMz=1585, + XED_IFORM_PUSH_MEMv=1586, + XED_IFORM_PUSH_SS=1587, + XED_IFORM_PUSHA=1588, + XED_IFORM_PUSHAD=1589, + XED_IFORM_PUSHF=1590, + XED_IFORM_PUSHFD=1591, + XED_IFORM_PUSHFQ=1592, + XED_IFORM_PVALIDATE_RAX_ECX_EDX=1593, + XED_IFORM_PXOR_MMXq_MEMq=1594, + XED_IFORM_PXOR_MMXq_MMXq=1595, + XED_IFORM_PXOR_XMMdq_MEMdq=1596, + XED_IFORM_PXOR_XMMdq_XMMdq=1597, + XED_IFORM_RCL_GPR8_CL=1598, + XED_IFORM_RCL_GPR8_IMMb=1599, + XED_IFORM_RCL_GPR8_ONE=1600, + XED_IFORM_RCL_GPRv_CL=1601, + XED_IFORM_RCL_GPRv_IMMb=1602, + XED_IFORM_RCL_GPRv_ONE=1603, + XED_IFORM_RCL_MEMb_CL=1604, + XED_IFORM_RCL_MEMb_IMMb=1605, + XED_IFORM_RCL_MEMb_ONE=1606, + XED_IFORM_RCL_MEMv_CL=1607, + XED_IFORM_RCL_MEMv_IMMb=1608, + XED_IFORM_RCL_MEMv_ONE=1609, + XED_IFORM_RCPPS_XMMps_MEMps=1610, + XED_IFORM_RCPPS_XMMps_XMMps=1611, + XED_IFORM_RCPSS_XMMss_MEMss=1612, + XED_IFORM_RCPSS_XMMss_XMMss=1613, + XED_IFORM_RCR_GPR8_CL=1614, + XED_IFORM_RCR_GPR8_IMMb=1615, + XED_IFORM_RCR_GPR8_ONE=1616, + XED_IFORM_RCR_GPRv_CL=1617, + XED_IFORM_RCR_GPRv_IMMb=1618, + XED_IFORM_RCR_GPRv_ONE=1619, + XED_IFORM_RCR_MEMb_CL=1620, + XED_IFORM_RCR_MEMb_IMMb=1621, + XED_IFORM_RCR_MEMb_ONE=1622, + XED_IFORM_RCR_MEMv_CL=1623, + XED_IFORM_RCR_MEMv_IMMb=1624, + XED_IFORM_RCR_MEMv_ONE=1625, + XED_IFORM_RDFSBASE_GPRy=1626, + XED_IFORM_RDGSBASE_GPRy=1627, + XED_IFORM_RDMSR=1628, + XED_IFORM_RDPID_GPR32u32=1629, + XED_IFORM_RDPID_GPR64u64=1630, + XED_IFORM_RDPKRU=1631, + XED_IFORM_RDPMC=1632, + XED_IFORM_RDPRU=1633, + XED_IFORM_RDRAND_GPRv=1634, + XED_IFORM_RDSEED_GPRv=1635, + XED_IFORM_RDSSPD_GPR32u32=1636, + XED_IFORM_RDSSPQ_GPR64u64=1637, + XED_IFORM_RDTSC=1638, + XED_IFORM_RDTSCP=1639, + XED_IFORM_REPE_CMPSB=1640, + XED_IFORM_REPE_CMPSD=1641, + XED_IFORM_REPE_CMPSQ=1642, + XED_IFORM_REPE_CMPSW=1643, + XED_IFORM_REPE_SCASB=1644, + XED_IFORM_REPE_SCASD=1645, + XED_IFORM_REPE_SCASQ=1646, + XED_IFORM_REPE_SCASW=1647, + XED_IFORM_REPNE_CMPSB=1648, + XED_IFORM_REPNE_CMPSD=1649, + XED_IFORM_REPNE_CMPSQ=1650, + XED_IFORM_REPNE_CMPSW=1651, + XED_IFORM_REPNE_SCASB=1652, + XED_IFORM_REPNE_SCASD=1653, + XED_IFORM_REPNE_SCASQ=1654, + XED_IFORM_REPNE_SCASW=1655, + XED_IFORM_REP_INSB=1656, + XED_IFORM_REP_INSD=1657, + XED_IFORM_REP_INSW=1658, + XED_IFORM_REP_LODSB=1659, + XED_IFORM_REP_LODSD=1660, + XED_IFORM_REP_LODSQ=1661, + XED_IFORM_REP_LODSW=1662, + XED_IFORM_REP_MONTMUL=1663, + XED_IFORM_REP_MOVSB=1664, + XED_IFORM_REP_MOVSD=1665, + XED_IFORM_REP_MOVSQ=1666, + XED_IFORM_REP_MOVSW=1667, + XED_IFORM_REP_OUTSB=1668, + XED_IFORM_REP_OUTSD=1669, + XED_IFORM_REP_OUTSW=1670, + XED_IFORM_REP_STOSB=1671, + XED_IFORM_REP_STOSD=1672, + XED_IFORM_REP_STOSQ=1673, + XED_IFORM_REP_STOSW=1674, + XED_IFORM_REP_XCRYPTCBC=1675, + XED_IFORM_REP_XCRYPTCFB=1676, + XED_IFORM_REP_XCRYPTCTR=1677, + XED_IFORM_REP_XCRYPTECB=1678, + XED_IFORM_REP_XCRYPTOFB=1679, + XED_IFORM_REP_XSHA1=1680, + XED_IFORM_REP_XSHA256=1681, + XED_IFORM_REP_XSTORE=1682, + XED_IFORM_RET_FAR=1683, + XED_IFORM_RET_FAR_IMMw=1684, + XED_IFORM_RET_NEAR=1685, + XED_IFORM_RET_NEAR_IMMw=1686, + XED_IFORM_RMPADJUST_RAX_RCX_RDX=1687, + XED_IFORM_RMPUPDATE_RAX_RCX=1688, + XED_IFORM_ROL_GPR8_CL=1689, + XED_IFORM_ROL_GPR8_IMMb=1690, + XED_IFORM_ROL_GPR8_ONE=1691, + XED_IFORM_ROL_GPRv_CL=1692, + XED_IFORM_ROL_GPRv_IMMb=1693, + XED_IFORM_ROL_GPRv_ONE=1694, + XED_IFORM_ROL_MEMb_CL=1695, + XED_IFORM_ROL_MEMb_IMMb=1696, + XED_IFORM_ROL_MEMb_ONE=1697, + XED_IFORM_ROL_MEMv_CL=1698, + XED_IFORM_ROL_MEMv_IMMb=1699, + XED_IFORM_ROL_MEMv_ONE=1700, + XED_IFORM_ROR_GPR8_CL=1701, + XED_IFORM_ROR_GPR8_IMMb=1702, + XED_IFORM_ROR_GPR8_ONE=1703, + XED_IFORM_ROR_GPRv_CL=1704, + XED_IFORM_ROR_GPRv_IMMb=1705, + XED_IFORM_ROR_GPRv_ONE=1706, + XED_IFORM_ROR_MEMb_CL=1707, + XED_IFORM_ROR_MEMb_IMMb=1708, + XED_IFORM_ROR_MEMb_ONE=1709, + XED_IFORM_ROR_MEMv_CL=1710, + XED_IFORM_ROR_MEMv_IMMb=1711, + XED_IFORM_ROR_MEMv_ONE=1712, + XED_IFORM_RORX_VGPR32d_MEMd_IMMb=1713, + XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb=1714, + XED_IFORM_RORX_VGPR64q_MEMq_IMMb=1715, + XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb=1716, + XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb=1717, + XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb=1718, + XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb=1719, + XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb=1720, + XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb=1721, + XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb=1722, + XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb=1723, + XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb=1724, + XED_IFORM_RSM=1725, + XED_IFORM_RSQRTPS_XMMps_MEMps=1726, + XED_IFORM_RSQRTPS_XMMps_XMMps=1727, + XED_IFORM_RSQRTSS_XMMss_MEMss=1728, + XED_IFORM_RSQRTSS_XMMss_XMMss=1729, + XED_IFORM_RSTORSSP_MEMu64=1730, + XED_IFORM_SAHF=1731, + XED_IFORM_SALC=1732, + XED_IFORM_SAR_GPR8_CL=1733, + XED_IFORM_SAR_GPR8_IMMb=1734, + XED_IFORM_SAR_GPR8_ONE=1735, + XED_IFORM_SAR_GPRv_CL=1736, + XED_IFORM_SAR_GPRv_IMMb=1737, + XED_IFORM_SAR_GPRv_ONE=1738, + XED_IFORM_SAR_MEMb_CL=1739, + XED_IFORM_SAR_MEMb_IMMb=1740, + XED_IFORM_SAR_MEMb_ONE=1741, + XED_IFORM_SAR_MEMv_CL=1742, + XED_IFORM_SAR_MEMv_IMMb=1743, + XED_IFORM_SAR_MEMv_ONE=1744, + XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d=1745, + XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d=1746, + XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q=1747, + XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q=1748, + XED_IFORM_SAVEPREVSSP=1749, + XED_IFORM_SBB_AL_IMMb=1750, + XED_IFORM_SBB_GPR8_GPR8_18=1751, + XED_IFORM_SBB_GPR8_GPR8_1A=1752, + XED_IFORM_SBB_GPR8_IMMb_80r3=1753, + XED_IFORM_SBB_GPR8_IMMb_82r3=1754, + XED_IFORM_SBB_GPR8_MEMb=1755, + XED_IFORM_SBB_GPRv_GPRv_19=1756, + XED_IFORM_SBB_GPRv_GPRv_1B=1757, + XED_IFORM_SBB_GPRv_IMMb=1758, + XED_IFORM_SBB_GPRv_IMMz=1759, + XED_IFORM_SBB_GPRv_MEMv=1760, + XED_IFORM_SBB_MEMb_GPR8=1761, + XED_IFORM_SBB_MEMb_IMMb_80r3=1762, + XED_IFORM_SBB_MEMb_IMMb_82r3=1763, + XED_IFORM_SBB_MEMv_GPRv=1764, + XED_IFORM_SBB_MEMv_IMMb=1765, + XED_IFORM_SBB_MEMv_IMMz=1766, + XED_IFORM_SBB_OrAX_IMMz=1767, + XED_IFORM_SBB_LOCK_MEMb_GPR8=1768, + XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3=1769, + XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3=1770, + XED_IFORM_SBB_LOCK_MEMv_GPRv=1771, + XED_IFORM_SBB_LOCK_MEMv_IMMb=1772, + XED_IFORM_SBB_LOCK_MEMv_IMMz=1773, + XED_IFORM_SCASB=1774, + XED_IFORM_SCASD=1775, + XED_IFORM_SCASQ=1776, + XED_IFORM_SCASW=1777, + XED_IFORM_SEAMCALL=1778, + XED_IFORM_SEAMOPS=1779, + XED_IFORM_SEAMRET=1780, + XED_IFORM_SENDUIPI_GPR32u32=1781, + XED_IFORM_SERIALIZE=1782, + XED_IFORM_SETB_GPR8=1783, + XED_IFORM_SETB_MEMb=1784, + XED_IFORM_SETBE_GPR8=1785, + XED_IFORM_SETBE_MEMb=1786, + XED_IFORM_SETL_GPR8=1787, + XED_IFORM_SETL_MEMb=1788, + XED_IFORM_SETLE_GPR8=1789, + XED_IFORM_SETLE_MEMb=1790, + XED_IFORM_SETNB_GPR8=1791, + XED_IFORM_SETNB_MEMb=1792, + XED_IFORM_SETNBE_GPR8=1793, + XED_IFORM_SETNBE_MEMb=1794, + XED_IFORM_SETNL_GPR8=1795, + XED_IFORM_SETNL_MEMb=1796, + XED_IFORM_SETNLE_GPR8=1797, + XED_IFORM_SETNLE_MEMb=1798, + XED_IFORM_SETNO_GPR8=1799, + XED_IFORM_SETNO_MEMb=1800, + XED_IFORM_SETNP_GPR8=1801, + XED_IFORM_SETNP_MEMb=1802, + XED_IFORM_SETNS_GPR8=1803, + XED_IFORM_SETNS_MEMb=1804, + XED_IFORM_SETNZ_GPR8=1805, + XED_IFORM_SETNZ_MEMb=1806, + XED_IFORM_SETO_GPR8=1807, + XED_IFORM_SETO_MEMb=1808, + XED_IFORM_SETP_GPR8=1809, + XED_IFORM_SETP_MEMb=1810, + XED_IFORM_SETS_GPR8=1811, + XED_IFORM_SETS_MEMb=1812, + XED_IFORM_SETSSBSY=1813, + XED_IFORM_SETZ_GPR8=1814, + XED_IFORM_SETZ_MEMb=1815, + XED_IFORM_SFENCE=1816, + XED_IFORM_SGDT_MEMs=1817, + XED_IFORM_SGDT_MEMs64=1818, + XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA=1819, + XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA=1820, + XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA=1821, + XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA=1822, + XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA=1823, + XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA=1824, + XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA=1825, + XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA=1826, + XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA=1827, + XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA=1828, + XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA=1829, + XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA=1830, + XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA=1831, + XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA=1832, + XED_IFORM_SHL_GPR8_CL_D2r4=1833, + XED_IFORM_SHL_GPR8_CL_D2r6=1834, + XED_IFORM_SHL_GPR8_IMMb_C0r4=1835, + XED_IFORM_SHL_GPR8_IMMb_C0r6=1836, + XED_IFORM_SHL_GPR8_ONE_D0r4=1837, + XED_IFORM_SHL_GPR8_ONE_D0r6=1838, + XED_IFORM_SHL_GPRv_CL_D3r4=1839, + XED_IFORM_SHL_GPRv_CL_D3r6=1840, + XED_IFORM_SHL_GPRv_IMMb_C1r4=1841, + XED_IFORM_SHL_GPRv_IMMb_C1r6=1842, + XED_IFORM_SHL_GPRv_ONE_D1r4=1843, + XED_IFORM_SHL_GPRv_ONE_D1r6=1844, + XED_IFORM_SHL_MEMb_CL_D2r4=1845, + XED_IFORM_SHL_MEMb_CL_D2r6=1846, + XED_IFORM_SHL_MEMb_IMMb_C0r4=1847, + XED_IFORM_SHL_MEMb_IMMb_C0r6=1848, + XED_IFORM_SHL_MEMb_ONE_D0r4=1849, + XED_IFORM_SHL_MEMb_ONE_D0r6=1850, + XED_IFORM_SHL_MEMv_CL_D3r4=1851, + XED_IFORM_SHL_MEMv_CL_D3r6=1852, + XED_IFORM_SHL_MEMv_IMMb_C1r4=1853, + XED_IFORM_SHL_MEMv_IMMb_C1r6=1854, + XED_IFORM_SHL_MEMv_ONE_D1r4=1855, + XED_IFORM_SHL_MEMv_ONE_D1r6=1856, + XED_IFORM_SHLD_GPRv_GPRv_CL=1857, + XED_IFORM_SHLD_GPRv_GPRv_IMMb=1858, + XED_IFORM_SHLD_MEMv_GPRv_CL=1859, + XED_IFORM_SHLD_MEMv_GPRv_IMMb=1860, + XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d=1861, + XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d=1862, + XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q=1863, + XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q=1864, + XED_IFORM_SHR_GPR8_CL=1865, + XED_IFORM_SHR_GPR8_IMMb=1866, + XED_IFORM_SHR_GPR8_ONE=1867, + XED_IFORM_SHR_GPRv_CL=1868, + XED_IFORM_SHR_GPRv_IMMb=1869, + XED_IFORM_SHR_GPRv_ONE=1870, + XED_IFORM_SHR_MEMb_CL=1871, + XED_IFORM_SHR_MEMb_IMMb=1872, + XED_IFORM_SHR_MEMb_ONE=1873, + XED_IFORM_SHR_MEMv_CL=1874, + XED_IFORM_SHR_MEMv_IMMb=1875, + XED_IFORM_SHR_MEMv_ONE=1876, + XED_IFORM_SHRD_GPRv_GPRv_CL=1877, + XED_IFORM_SHRD_GPRv_GPRv_IMMb=1878, + XED_IFORM_SHRD_MEMv_GPRv_CL=1879, + XED_IFORM_SHRD_MEMv_GPRv_IMMb=1880, + XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d=1881, + XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d=1882, + XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q=1883, + XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q=1884, + XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb=1885, + XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb=1886, + XED_IFORM_SHUFPS_XMMps_MEMps_IMMb=1887, + XED_IFORM_SHUFPS_XMMps_XMMps_IMMb=1888, + XED_IFORM_SIDT_MEMs=1889, + XED_IFORM_SIDT_MEMs64=1890, + XED_IFORM_SKINIT_EAX=1891, + XED_IFORM_SLDT_GPRv=1892, + XED_IFORM_SLDT_MEMw=1893, + XED_IFORM_SLWPCB_VGPRyy=1894, + XED_IFORM_SMSW_GPRv=1895, + XED_IFORM_SMSW_MEMw=1896, + XED_IFORM_SQRTPD_XMMpd_MEMpd=1897, + XED_IFORM_SQRTPD_XMMpd_XMMpd=1898, + XED_IFORM_SQRTPS_XMMps_MEMps=1899, + XED_IFORM_SQRTPS_XMMps_XMMps=1900, + XED_IFORM_SQRTSD_XMMsd_MEMsd=1901, + XED_IFORM_SQRTSD_XMMsd_XMMsd=1902, + XED_IFORM_SQRTSS_XMMss_MEMss=1903, + XED_IFORM_SQRTSS_XMMss_XMMss=1904, + XED_IFORM_STAC=1905, + XED_IFORM_STC=1906, + XED_IFORM_STD=1907, + XED_IFORM_STGI=1908, + XED_IFORM_STI=1909, + XED_IFORM_STMXCSR_MEMd=1910, + XED_IFORM_STOSB=1911, + XED_IFORM_STOSD=1912, + XED_IFORM_STOSQ=1913, + XED_IFORM_STOSW=1914, + XED_IFORM_STR_GPRv=1915, + XED_IFORM_STR_MEMw=1916, + XED_IFORM_STTILECFG_MEM=1917, + XED_IFORM_STUI=1918, + XED_IFORM_SUB_AL_IMMb=1919, + XED_IFORM_SUB_GPR8_GPR8_28=1920, + XED_IFORM_SUB_GPR8_GPR8_2A=1921, + XED_IFORM_SUB_GPR8_IMMb_80r5=1922, + XED_IFORM_SUB_GPR8_IMMb_82r5=1923, + XED_IFORM_SUB_GPR8_MEMb=1924, + XED_IFORM_SUB_GPRv_GPRv_29=1925, + XED_IFORM_SUB_GPRv_GPRv_2B=1926, + XED_IFORM_SUB_GPRv_IMMb=1927, + XED_IFORM_SUB_GPRv_IMMz=1928, + XED_IFORM_SUB_GPRv_MEMv=1929, + XED_IFORM_SUB_MEMb_GPR8=1930, + XED_IFORM_SUB_MEMb_IMMb_80r5=1931, + XED_IFORM_SUB_MEMb_IMMb_82r5=1932, + XED_IFORM_SUB_MEMv_GPRv=1933, + XED_IFORM_SUB_MEMv_IMMb=1934, + XED_IFORM_SUB_MEMv_IMMz=1935, + XED_IFORM_SUB_OrAX_IMMz=1936, + XED_IFORM_SUBPD_XMMpd_MEMpd=1937, + XED_IFORM_SUBPD_XMMpd_XMMpd=1938, + XED_IFORM_SUBPS_XMMps_MEMps=1939, + XED_IFORM_SUBPS_XMMps_XMMps=1940, + XED_IFORM_SUBSD_XMMsd_MEMsd=1941, + XED_IFORM_SUBSD_XMMsd_XMMsd=1942, + XED_IFORM_SUBSS_XMMss_MEMss=1943, + XED_IFORM_SUBSS_XMMss_XMMss=1944, + XED_IFORM_SUB_LOCK_MEMb_GPR8=1945, + XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5=1946, + XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5=1947, + XED_IFORM_SUB_LOCK_MEMv_GPRv=1948, + XED_IFORM_SUB_LOCK_MEMv_IMMb=1949, + XED_IFORM_SUB_LOCK_MEMv_IMMz=1950, + XED_IFORM_SWAPGS=1951, + XED_IFORM_SYSCALL=1952, + XED_IFORM_SYSCALL_AMD=1953, + XED_IFORM_SYSENTER=1954, + XED_IFORM_SYSEXIT=1955, + XED_IFORM_SYSRET=1956, + XED_IFORM_SYSRET64=1957, + XED_IFORM_SYSRET_AMD=1958, + XED_IFORM_T1MSKC_VGPR32d_MEMd=1959, + XED_IFORM_T1MSKC_VGPR32d_VGPR32d=1960, + XED_IFORM_T1MSKC_VGPRyy_MEMy=1961, + XED_IFORM_T1MSKC_VGPRyy_VGPRyy=1962, + XED_IFORM_TDCALL=1963, + XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32=1964, + XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32=1965, + XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32=1966, + XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32=1967, + XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32=1968, + XED_IFORM_TEST_AL_IMMb=1969, + XED_IFORM_TEST_GPR8_GPR8=1970, + XED_IFORM_TEST_GPR8_IMMb_F6r0=1971, + XED_IFORM_TEST_GPR8_IMMb_F6r1=1972, + XED_IFORM_TEST_GPRv_GPRv=1973, + XED_IFORM_TEST_GPRv_IMMz_F7r0=1974, + XED_IFORM_TEST_GPRv_IMMz_F7r1=1975, + XED_IFORM_TEST_MEMb_GPR8=1976, + XED_IFORM_TEST_MEMb_IMMb_F6r0=1977, + XED_IFORM_TEST_MEMb_IMMb_F6r1=1978, + XED_IFORM_TEST_MEMv_GPRv=1979, + XED_IFORM_TEST_MEMv_IMMz_F7r0=1980, + XED_IFORM_TEST_MEMv_IMMz_F7r1=1981, + XED_IFORM_TEST_OrAX_IMMz=1982, + XED_IFORM_TESTUI=1983, + XED_IFORM_TILELOADD_TMMu32_MEMu32=1984, + XED_IFORM_TILELOADDT1_TMMu32_MEMu32=1985, + XED_IFORM_TILERELEASE=1986, + XED_IFORM_TILESTORED_MEMu32_TMMu32=1987, + XED_IFORM_TILEZERO_TMMu32=1988, + XED_IFORM_TLBSYNC=1989, + XED_IFORM_TPAUSE_GPR32u32=1990, + XED_IFORM_TZCNT_GPRv_GPRv=1991, + XED_IFORM_TZCNT_GPRv_MEMv=1992, + XED_IFORM_TZMSK_VGPR32d_MEMd=1993, + XED_IFORM_TZMSK_VGPR32d_VGPR32d=1994, + XED_IFORM_TZMSK_VGPRyy_MEMy=1995, + XED_IFORM_TZMSK_VGPRyy_VGPRyy=1996, + XED_IFORM_UCOMISD_XMMsd_MEMsd=1997, + XED_IFORM_UCOMISD_XMMsd_XMMsd=1998, + XED_IFORM_UCOMISS_XMMss_MEMss=1999, + XED_IFORM_UCOMISS_XMMss_XMMss=2000, + XED_IFORM_UD0=2001, + XED_IFORM_UD0_GPR32_GPR32=2002, + XED_IFORM_UD0_GPR32_MEMd=2003, + XED_IFORM_UD1_GPR32_GPR32=2004, + XED_IFORM_UD1_GPR32_MEMd=2005, + XED_IFORM_UD2=2006, + XED_IFORM_UIRET=2007, + XED_IFORM_UMONITOR_GPRa=2008, + XED_IFORM_UMWAIT_GPR32=2009, + XED_IFORM_UNPCKHPD_XMMpd_MEMdq=2010, + XED_IFORM_UNPCKHPD_XMMpd_XMMq=2011, + XED_IFORM_UNPCKHPS_XMMps_MEMdq=2012, + XED_IFORM_UNPCKHPS_XMMps_XMMdq=2013, + XED_IFORM_UNPCKLPD_XMMpd_MEMdq=2014, + XED_IFORM_UNPCKLPD_XMMpd_XMMq=2015, + XED_IFORM_UNPCKLPS_XMMps_MEMdq=2016, + XED_IFORM_UNPCKLPS_XMMps_XMMq=2017, + XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2018, + XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2019, + XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2020, + XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2021, + XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq=2022, + XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq=2023, + XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2024, + XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2025, + XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2026, + XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2027, + XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq=2028, + XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq=2029, + XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2030, + XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2031, + XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2032, + XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2033, + XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2034, + XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2035, + XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2036, + XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2037, + XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq=2038, + XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq=2039, + XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2040, + XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2041, + XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2042, + XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2043, + XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq=2044, + XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq=2045, + XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2046, + XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2047, + XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq=2048, + XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq=2049, + XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2050, + XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2051, + XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2052, + XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2053, + XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd=2054, + XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd=2055, + XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2056, + XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2057, + XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq=2058, + XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq=2059, + XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq=2060, + XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq=2061, + XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq=2062, + XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq=2063, + XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq=2064, + XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq=2065, + XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq=2066, + XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq=2067, + XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512=2068, + XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512=2069, + XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128=2070, + XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512=2071, + XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128=2072, + XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512=2073, + XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512=2074, + XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512=2075, + XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq=2076, + XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq=2077, + XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512=2078, + XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512=2079, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128=2080, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512=2081, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128=2082, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512=2083, + XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2084, + XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2085, + XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq=2086, + XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq=2087, + XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512=2088, + XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512=2089, + XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128=2090, + XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512=2091, + XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128=2092, + XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512=2093, + XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512=2094, + XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512=2095, + XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq=2096, + XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq=2097, + XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512=2098, + XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512=2099, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128=2100, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512=2101, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128=2102, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512=2103, + XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2104, + XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2105, + XED_IFORM_VAESIMC_XMMdq_MEMdq=2106, + XED_IFORM_VAESIMC_XMMdq_XMMdq=2107, + XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb=2108, + XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb=2109, + XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=2110, + XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=2111, + XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=2112, + XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=2113, + XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=2114, + XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=2115, + XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=2116, + XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=2117, + XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=2118, + XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=2119, + XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=2120, + XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=2121, + XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq=2122, + XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq=2123, + XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2124, + XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2125, + XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq=2126, + XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq=2127, + XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2128, + XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2129, + XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2130, + XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2131, + XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq=2132, + XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq=2133, + XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2134, + XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2135, + XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq=2136, + XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq=2137, + XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2138, + XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2139, + XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2140, + XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2141, + XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq=2142, + XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq=2143, + XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2144, + XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2145, + XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq=2146, + XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq=2147, + XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2148, + XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2149, + XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2150, + XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2151, + XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq=2152, + XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq=2153, + XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2154, + XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2155, + XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq=2156, + XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq=2157, + XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2158, + XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2159, + XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2160, + XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2161, + XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2162, + XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2163, + XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2164, + XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2165, + XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2166, + XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2167, + XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2168, + XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2169, + XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2170, + XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2171, + XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2172, + XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2173, + XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb=2174, + XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb=2175, + XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb=2176, + XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb=2177, + XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb=2178, + XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb=2179, + XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb=2180, + XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb=2181, + XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq=2182, + XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq=2183, + XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq=2184, + XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq=2185, + XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq=2186, + XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq=2187, + XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq=2188, + XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq=2189, + XED_IFORM_VBROADCASTF128_YMMqq_MEMdq=2190, + XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512=2191, + XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512=2192, + XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512=2193, + XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512=2194, + XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512=2195, + XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512=2196, + XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512=2197, + XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512=2198, + XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512=2199, + XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512=2200, + XED_IFORM_VBROADCASTI128_YMMqq_MEMdq=2201, + XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512=2202, + XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512=2203, + XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512=2204, + XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512=2205, + XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512=2206, + XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512=2207, + XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512=2208, + XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512=2209, + XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512=2210, + XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512=2211, + XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512=2212, + XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512=2213, + XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512=2214, + XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512=2215, + XED_IFORM_VBROADCASTSD_YMMqq_MEMq=2216, + XED_IFORM_VBROADCASTSD_YMMqq_XMMdq=2217, + XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512=2218, + XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512=2219, + XED_IFORM_VBROADCASTSS_XMMdq_MEMd=2220, + XED_IFORM_VBROADCASTSS_XMMdq_XMMdq=2221, + XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512=2222, + XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512=2223, + XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512=2224, + XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512=2225, + XED_IFORM_VBROADCASTSS_YMMqq_MEMd=2226, + XED_IFORM_VBROADCASTSS_YMMqq_XMMdq=2227, + XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512=2228, + XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512=2229, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2230, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2231, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2232, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2233, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2234, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2235, + XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb=2236, + XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb=2237, + XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb=2238, + XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb=2239, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=2240, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=2241, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512=2242, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512=2243, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512=2244, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512=2245, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2246, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2247, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2248, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2249, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2250, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2251, + XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb=2252, + XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb=2253, + XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb=2254, + XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb=2255, + XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2256, + XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2257, + XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb=2258, + XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb=2259, + XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=2260, + XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=2261, + XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2262, + XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2263, + XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb=2264, + XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb=2265, + XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512=2266, + XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512=2267, + XED_IFORM_VCOMISD_XMMq_MEMq=2268, + XED_IFORM_VCOMISD_XMMq_XMMq=2269, + XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512=2270, + XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512=2271, + XED_IFORM_VCOMISS_XMMd_MEMd=2272, + XED_IFORM_VCOMISS_XMMd_XMMd=2273, + XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512=2274, + XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512=2275, + XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512=2276, + XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512=2277, + XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512=2278, + XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512=2279, + XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512=2280, + XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2281, + XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512=2282, + XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512=2283, + XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512=2284, + XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512=2285, + XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512=2286, + XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2287, + XED_IFORM_VCVTDQ2PD_XMMdq_MEMq=2288, + XED_IFORM_VCVTDQ2PD_XMMdq_XMMq=2289, + XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512=2290, + XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512=2291, + XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512=2292, + XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512=2293, + XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq=2294, + XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq=2295, + XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512=2296, + XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512=2297, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128=2298, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256=2299, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512=2300, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512=2301, + XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512=2302, + XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512=2303, + XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq=2304, + XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq=2305, + XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512=2306, + XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512=2307, + XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512=2308, + XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512=2309, + XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq=2310, + XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq=2311, + XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512=2312, + XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512=2313, + XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128=2314, + XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512=2315, + XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256=2316, + XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512=2317, + XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512=2318, + XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512=2319, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128=2320, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256=2321, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512=2322, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512=2323, + XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512=2324, + XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512=2325, + XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq=2326, + XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq=2327, + XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq=2328, + XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq=2329, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2330, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2331, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2332, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2333, + XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2334, + XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2335, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128=2336, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256=2337, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512=2338, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512=2339, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512=2340, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512=2341, + XED_IFORM_VCVTPD2PS_XMMdq_MEMdq=2342, + XED_IFORM_VCVTPD2PS_XMMdq_MEMqq=2343, + XED_IFORM_VCVTPD2PS_XMMdq_XMMdq=2344, + XED_IFORM_VCVTPD2PS_XMMdq_YMMqq=2345, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128=2346, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256=2347, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128=2348, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256=2349, + XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512=2350, + XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512=2351, + XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2352, + XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2353, + XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2354, + XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2355, + XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2356, + XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2357, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2358, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2359, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2360, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2361, + XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2362, + XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2363, + XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2364, + XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2365, + XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2366, + XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2367, + XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2368, + XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2369, + XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512=2370, + XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512=2371, + XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512=2372, + XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512=2373, + XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512=2374, + XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512=2375, + XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512=2376, + XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512=2377, + XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512=2378, + XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512=2379, + XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512=2380, + XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512=2381, + XED_IFORM_VCVTPH2PS_XMMdq_MEMq=2382, + XED_IFORM_VCVTPH2PS_XMMdq_XMMq=2383, + XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512=2384, + XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512=2385, + XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512=2386, + XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512=2387, + XED_IFORM_VCVTPH2PS_YMMqq_MEMdq=2388, + XED_IFORM_VCVTPH2PS_YMMqq_XMMdq=2389, + XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512=2390, + XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512=2391, + XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512=2392, + XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512=2393, + XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512=2394, + XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512=2395, + XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512=2396, + XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512=2397, + XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512=2398, + XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512=2399, + XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512=2400, + XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512=2401, + XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512=2402, + XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512=2403, + XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512=2404, + XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512=2405, + XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512=2406, + XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512=2407, + XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512=2408, + XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512=2409, + XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512=2410, + XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512=2411, + XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512=2412, + XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512=2413, + XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512=2414, + XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512=2415, + XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512=2416, + XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512=2417, + XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512=2418, + XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512=2419, + XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512=2420, + XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512=2421, + XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512=2422, + XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512=2423, + XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512=2424, + XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512=2425, + XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512=2426, + XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512=2427, + XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq=2428, + XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq=2429, + XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2430, + XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2431, + XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2432, + XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2433, + XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq=2434, + XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq=2435, + XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2436, + XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2437, + XED_IFORM_VCVTPS2PD_XMMdq_MEMq=2438, + XED_IFORM_VCVTPS2PD_XMMdq_XMMq=2439, + XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512=2440, + XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512=2441, + XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512=2442, + XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512=2443, + XED_IFORM_VCVTPS2PD_YMMqq_MEMdq=2444, + XED_IFORM_VCVTPS2PD_YMMqq_XMMdq=2445, + XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512=2446, + XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512=2447, + XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb=2448, + XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512=2449, + XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512=2450, + XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512=2451, + XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb=2452, + XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb=2453, + XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512=2454, + XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512=2455, + XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb=2456, + XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512=2457, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128=2458, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256=2459, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512=2460, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512=2461, + XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512=2462, + XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512=2463, + XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2464, + XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2465, + XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2466, + XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2467, + XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2468, + XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2469, + XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2470, + XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2471, + XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2472, + XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2473, + XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2474, + XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2475, + XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2476, + XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2477, + XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2478, + XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2479, + XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2480, + XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2481, + XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512=2482, + XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512=2483, + XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512=2484, + XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512=2485, + XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512=2486, + XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512=2487, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128=2488, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256=2489, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512=2490, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512=2491, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512=2492, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512=2493, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2494, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2495, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2496, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2497, + XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2498, + XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2499, + XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512=2500, + XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512=2501, + XED_IFORM_VCVTSD2SI_GPR32d_MEMq=2502, + XED_IFORM_VCVTSD2SI_GPR32d_XMMq=2503, + XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512=2504, + XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512=2505, + XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512=2506, + XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512=2507, + XED_IFORM_VCVTSD2SI_GPR64q_MEMq=2508, + XED_IFORM_VCVTSD2SI_GPR64q_XMMq=2509, + XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq=2510, + XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq=2511, + XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512=2512, + XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512=2513, + XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512=2514, + XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512=2515, + XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512=2516, + XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512=2517, + XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512=2518, + XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512=2519, + XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512=2520, + XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512=2521, + XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512=2522, + XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512=2523, + XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512=2524, + XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512=2525, + XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512=2526, + XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512=2527, + XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512=2528, + XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512=2529, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d=2530, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q=2531, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd=2532, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq=2533, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512=2534, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512=2535, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512=2536, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512=2537, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512=2538, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512=2539, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512=2540, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512=2541, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d=2542, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q=2543, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd=2544, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq=2545, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512=2546, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512=2547, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512=2548, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512=2549, + XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd=2550, + XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd=2551, + XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512=2552, + XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512=2553, + XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512=2554, + XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512=2555, + XED_IFORM_VCVTSS2SI_GPR32d_MEMd=2556, + XED_IFORM_VCVTSS2SI_GPR32d_XMMd=2557, + XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512=2558, + XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512=2559, + XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512=2560, + XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512=2561, + XED_IFORM_VCVTSS2SI_GPR64q_MEMd=2562, + XED_IFORM_VCVTSS2SI_GPR64q_XMMd=2563, + XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512=2564, + XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512=2565, + XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512=2566, + XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512=2567, + XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq=2568, + XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq=2569, + XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq=2570, + XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq=2571, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2572, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2573, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2574, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2575, + XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2576, + XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2577, + XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2578, + XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2579, + XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2580, + XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2581, + XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2582, + XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2583, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2584, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2585, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2586, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2587, + XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2588, + XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2589, + XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2590, + XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2591, + XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2592, + XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2593, + XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2594, + XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2595, + XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512=2596, + XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512=2597, + XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512=2598, + XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512=2599, + XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512=2600, + XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512=2601, + XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512=2602, + XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512=2603, + XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512=2604, + XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512=2605, + XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512=2606, + XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512=2607, + XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512=2608, + XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512=2609, + XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512=2610, + XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512=2611, + XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512=2612, + XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512=2613, + XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512=2614, + XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512=2615, + XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512=2616, + XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512=2617, + XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512=2618, + XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512=2619, + XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512=2620, + XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512=2621, + XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512=2622, + XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512=2623, + XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512=2624, + XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512=2625, + XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512=2626, + XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512=2627, + XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512=2628, + XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512=2629, + XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512=2630, + XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512=2631, + XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq=2632, + XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq=2633, + XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2634, + XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2635, + XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2636, + XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2637, + XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq=2638, + XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq=2639, + XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2640, + XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2641, + XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2642, + XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2643, + XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2644, + XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2645, + XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2646, + XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2647, + XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2648, + XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2649, + XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2650, + XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2651, + XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2652, + XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2653, + XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2654, + XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2655, + XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2656, + XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2657, + XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2658, + XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2659, + XED_IFORM_VCVTTSD2SI_GPR32d_MEMq=2660, + XED_IFORM_VCVTTSD2SI_GPR32d_XMMq=2661, + XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512=2662, + XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512=2663, + XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512=2664, + XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512=2665, + XED_IFORM_VCVTTSD2SI_GPR64q_MEMq=2666, + XED_IFORM_VCVTTSD2SI_GPR64q_XMMq=2667, + XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512=2668, + XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512=2669, + XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512=2670, + XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512=2671, + XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512=2672, + XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512=2673, + XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512=2674, + XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512=2675, + XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512=2676, + XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512=2677, + XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512=2678, + XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512=2679, + XED_IFORM_VCVTTSS2SI_GPR32d_MEMd=2680, + XED_IFORM_VCVTTSS2SI_GPR32d_XMMd=2681, + XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512=2682, + XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512=2683, + XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512=2684, + XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512=2685, + XED_IFORM_VCVTTSS2SI_GPR64q_MEMd=2686, + XED_IFORM_VCVTTSS2SI_GPR64q_XMMd=2687, + XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512=2688, + XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512=2689, + XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512=2690, + XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512=2691, + XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512=2692, + XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512=2693, + XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512=2694, + XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512=2695, + XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512=2696, + XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512=2697, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128=2698, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256=2699, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512=2700, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512=2701, + XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512=2702, + XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512=2703, + XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512=2704, + XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512=2705, + XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512=2706, + XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512=2707, + XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512=2708, + XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512=2709, + XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512=2710, + XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512=2711, + XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512=2712, + XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512=2713, + XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512=2714, + XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512=2715, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128=2716, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256=2717, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512=2718, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512=2719, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512=2720, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512=2721, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2722, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2723, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2724, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2725, + XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2726, + XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2727, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512=2728, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512=2729, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512=2730, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512=2731, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512=2732, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512=2733, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512=2734, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512=2735, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512=2736, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512=2737, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512=2738, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512=2739, + XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512=2740, + XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512=2741, + XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512=2742, + XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512=2743, + XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512=2744, + XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512=2745, + XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512=2746, + XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512=2747, + XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512=2748, + XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512=2749, + XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512=2750, + XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512=2751, + XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=2752, + XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=2753, + XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=2754, + XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=2755, + XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=2756, + XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=2757, + XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq=2758, + XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq=2759, + XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2760, + XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2761, + XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2762, + XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2763, + XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq=2764, + XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq=2765, + XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2766, + XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2767, + XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2768, + XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2769, + XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2770, + XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2771, + XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2772, + XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2773, + XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq=2774, + XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq=2775, + XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2776, + XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2777, + XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2778, + XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2779, + XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq=2780, + XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq=2781, + XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2782, + XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2783, + XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq=2784, + XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq=2785, + XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2786, + XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2787, + XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2788, + XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2789, + XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd=2790, + XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd=2791, + XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2792, + XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2793, + XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512=2794, + XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512=2795, + XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512=2796, + XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512=2797, + XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512=2798, + XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512=2799, + XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb=2800, + XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb=2801, + XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb=2802, + XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb=2803, + XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb=2804, + XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb=2805, + XED_IFORM_VERR_GPR16=2806, + XED_IFORM_VERR_MEMw=2807, + XED_IFORM_VERW_GPR16=2808, + XED_IFORM_VERW_MEMw=2809, + XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=2810, + XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=2811, + XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=2812, + XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=2813, + XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512=2814, + XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512=2815, + XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512=2816, + XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512=2817, + XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512=2818, + XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2819, + XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512=2820, + XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512=2821, + XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512=2822, + XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512=2823, + XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512=2824, + XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2825, + XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb=2826, + XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb=2827, + XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512=2828, + XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2829, + XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512=2830, + XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2831, + XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2832, + XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2833, + XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512=2834, + XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2835, + XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512=2836, + XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2837, + XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2838, + XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2839, + XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb=2840, + XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb=2841, + XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512=2842, + XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2843, + XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512=2844, + XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2845, + XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2846, + XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2847, + XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512=2848, + XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2849, + XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512=2850, + XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2851, + XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2852, + XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2853, + XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb=2854, + XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512=2855, + XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb=2856, + XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512=2857, + XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2858, + XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2859, + XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=2860, + XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=2861, + XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=2862, + XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=2863, + XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2864, + XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2865, + XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2866, + XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2867, + XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=2868, + XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=2869, + XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=2870, + XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=2871, + XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2872, + XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2873, + XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2874, + XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2875, + XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2876, + XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2877, + XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2878, + XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2879, + XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2880, + XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2881, + XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2882, + XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2883, + XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2884, + XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2885, + XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2886, + XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2887, + XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2888, + XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2889, + XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq=2890, + XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq=2891, + XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2892, + XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2893, + XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2894, + XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2895, + XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq=2896, + XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq=2897, + XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2898, + XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2899, + XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2900, + XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2901, + XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2902, + XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2903, + XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2904, + XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2905, + XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq=2906, + XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq=2907, + XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2908, + XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2909, + XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2910, + XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2911, + XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq=2912, + XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq=2913, + XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2914, + XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2915, + XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq=2916, + XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq=2917, + XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2918, + XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2919, + XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2920, + XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2921, + XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd=2922, + XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd=2923, + XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2924, + XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2925, + XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq=2926, + XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq=2927, + XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2928, + XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2929, + XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2930, + XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2931, + XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq=2932, + XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq=2933, + XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2934, + XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2935, + XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2936, + XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2937, + XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2938, + XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2939, + XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2940, + XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2941, + XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq=2942, + XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq=2943, + XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2944, + XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2945, + XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2946, + XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2947, + XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq=2948, + XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq=2949, + XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2950, + XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2951, + XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq=2952, + XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq=2953, + XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2954, + XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2955, + XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2956, + XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2957, + XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd=2958, + XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd=2959, + XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2960, + XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2961, + XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq=2962, + XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq=2963, + XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2964, + XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2965, + XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2966, + XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2967, + XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq=2968, + XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq=2969, + XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2970, + XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2971, + XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2972, + XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2973, + XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2974, + XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2975, + XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2976, + XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2977, + XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq=2978, + XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq=2979, + XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2980, + XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2981, + XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2982, + XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2983, + XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq=2984, + XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq=2985, + XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2986, + XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2987, + XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq=2988, + XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq=2989, + XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2990, + XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2991, + XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2992, + XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2993, + XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd=2994, + XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd=2995, + XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2996, + XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2997, + XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2998, + XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2999, + XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=3000, + XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=3001, + XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=3002, + XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=3003, + XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3004, + XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3005, + XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3006, + XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3007, + XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3008, + XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3009, + XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3010, + XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3011, + XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3012, + XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3013, + XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3014, + XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3015, + XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3016, + XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3017, + XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq=3018, + XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq=3019, + XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq=3020, + XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd=3021, + XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd=3022, + XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd=3023, + XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq=3024, + XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq=3025, + XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3026, + XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3027, + XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3028, + XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3029, + XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq=3030, + XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq=3031, + XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3032, + XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3033, + XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3034, + XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3035, + XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3036, + XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3037, + XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3038, + XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3039, + XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq=3040, + XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq=3041, + XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3042, + XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3043, + XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3044, + XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3045, + XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq=3046, + XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq=3047, + XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3048, + XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3049, + XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq=3050, + XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq=3051, + XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3052, + XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3053, + XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3054, + XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3055, + XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq=3056, + XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq=3057, + XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3058, + XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3059, + XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3060, + XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3061, + XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3062, + XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3063, + XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3064, + XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3065, + XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq=3066, + XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq=3067, + XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3068, + XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3069, + XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3070, + XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3071, + XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq=3072, + XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq=3073, + XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3074, + XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3075, + XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq=3076, + XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq=3077, + XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3078, + XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3079, + XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3080, + XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3081, + XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq=3082, + XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq=3083, + XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3084, + XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3085, + XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3086, + XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3087, + XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3088, + XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3089, + XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3090, + XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3091, + XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq=3092, + XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq=3093, + XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3094, + XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3095, + XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3096, + XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3097, + XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq=3098, + XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq=3099, + XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3100, + XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3101, + XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3102, + XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3103, + XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3104, + XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3105, + XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3106, + XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3107, + XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3108, + XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3109, + XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3110, + XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3111, + XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3112, + XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3113, + XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq=3114, + XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq=3115, + XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3116, + XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3117, + XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3118, + XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3119, + XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq=3120, + XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq=3121, + XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3122, + XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3123, + XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3124, + XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3125, + XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3126, + XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3127, + XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3128, + XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3129, + XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq=3130, + XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq=3131, + XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3132, + XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3133, + XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3134, + XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3135, + XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq=3136, + XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq=3137, + XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3138, + XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3139, + XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq=3140, + XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq=3141, + XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3142, + XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3143, + XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3144, + XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3145, + XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd=3146, + XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd=3147, + XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3148, + XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3149, + XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq=3150, + XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq=3151, + XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3152, + XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3153, + XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3154, + XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3155, + XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq=3156, + XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq=3157, + XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3158, + XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3159, + XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3160, + XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3161, + XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3162, + XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3163, + XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3164, + XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3165, + XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq=3166, + XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq=3167, + XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3168, + XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3169, + XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3170, + XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3171, + XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq=3172, + XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq=3173, + XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3174, + XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3175, + XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq=3176, + XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq=3177, + XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3178, + XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3179, + XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3180, + XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3181, + XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd=3182, + XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd=3183, + XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3184, + XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3185, + XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq=3186, + XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq=3187, + XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3188, + XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3189, + XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3190, + XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3191, + XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq=3192, + XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq=3193, + XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3194, + XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3195, + XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3196, + XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3197, + XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3198, + XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3199, + XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3200, + XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3201, + XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq=3202, + XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq=3203, + XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3204, + XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3205, + XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3206, + XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3207, + XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq=3208, + XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq=3209, + XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3210, + XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3211, + XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq=3212, + XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq=3213, + XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3214, + XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3215, + XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3216, + XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3217, + XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd=3218, + XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd=3219, + XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3220, + XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3221, + XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq=3222, + XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq=3223, + XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3224, + XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3225, + XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3226, + XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3227, + XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq=3228, + XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq=3229, + XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3230, + XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3231, + XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3232, + XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3233, + XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3234, + XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3235, + XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3236, + XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3237, + XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq=3238, + XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq=3239, + XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3240, + XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3241, + XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3242, + XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3243, + XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq=3244, + XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq=3245, + XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3246, + XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3247, + XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq=3248, + XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq=3249, + XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3250, + XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3251, + XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3252, + XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3253, + XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq=3254, + XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq=3255, + XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3256, + XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3257, + XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3258, + XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3259, + XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3260, + XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3261, + XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3262, + XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3263, + XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq=3264, + XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq=3265, + XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3266, + XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3267, + XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3268, + XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3269, + XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq=3270, + XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq=3271, + XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3272, + XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3273, + XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq=3274, + XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq=3275, + XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3276, + XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3277, + XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3278, + XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3279, + XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq=3280, + XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq=3281, + XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3282, + XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3283, + XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3284, + XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3285, + XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3286, + XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3287, + XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3288, + XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3289, + XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq=3290, + XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq=3291, + XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3292, + XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3293, + XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3294, + XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3295, + XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq=3296, + XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq=3297, + XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3298, + XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3299, + XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3300, + XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3301, + XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3302, + XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3303, + XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3304, + XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3305, + XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3306, + XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3307, + XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3308, + XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3309, + XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3310, + XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3311, + XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3312, + XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3313, + XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3314, + XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3315, + XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3316, + XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3317, + XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3318, + XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3319, + XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3320, + XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3321, + XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3322, + XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3323, + XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq=3324, + XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq=3325, + XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq=3326, + XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd=3327, + XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd=3328, + XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd=3329, + XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3330, + XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3331, + XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=3332, + XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=3333, + XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=3334, + XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=3335, + XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3336, + XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3337, + XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq=3338, + XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq=3339, + XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3340, + XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3341, + XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3342, + XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3343, + XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq=3344, + XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq=3345, + XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3346, + XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3347, + XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3348, + XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3349, + XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3350, + XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3351, + XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3352, + XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3353, + XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq=3354, + XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq=3355, + XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3356, + XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3357, + XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3358, + XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3359, + XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq=3360, + XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq=3361, + XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3362, + XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3363, + XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq=3364, + XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq=3365, + XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3366, + XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3367, + XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3368, + XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3369, + XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd=3370, + XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd=3371, + XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3372, + XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3373, + XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq=3374, + XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq=3375, + XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3376, + XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3377, + XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3378, + XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3379, + XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq=3380, + XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq=3381, + XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3382, + XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3383, + XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3384, + XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3385, + XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3386, + XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3387, + XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3388, + XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3389, + XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq=3390, + XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq=3391, + XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3392, + XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3393, + XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3394, + XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3395, + XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq=3396, + XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq=3397, + XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3398, + XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3399, + XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq=3400, + XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq=3401, + XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3402, + XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3403, + XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3404, + XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3405, + XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd=3406, + XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd=3407, + XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3408, + XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3409, + XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq=3410, + XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq=3411, + XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3412, + XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3413, + XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3414, + XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3415, + XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq=3416, + XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq=3417, + XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3418, + XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3419, + XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3420, + XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3421, + XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3422, + XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3423, + XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3424, + XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3425, + XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq=3426, + XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq=3427, + XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3428, + XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3429, + XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3430, + XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3431, + XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq=3432, + XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq=3433, + XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3434, + XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3435, + XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq=3436, + XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq=3437, + XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3438, + XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3439, + XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3440, + XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3441, + XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd=3442, + XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd=3443, + XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3444, + XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3445, + XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3446, + XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3447, + XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3448, + XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3449, + XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3450, + XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3451, + XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3452, + XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3453, + XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3454, + XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3455, + XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3456, + XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3457, + XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq=3458, + XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq=3459, + XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq=3460, + XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd=3461, + XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd=3462, + XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd=3463, + XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq=3464, + XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq=3465, + XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3466, + XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3467, + XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3468, + XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3469, + XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq=3470, + XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq=3471, + XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3472, + XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3473, + XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3474, + XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3475, + XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3476, + XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3477, + XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3478, + XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3479, + XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq=3480, + XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq=3481, + XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3482, + XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3483, + XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3484, + XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3485, + XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq=3486, + XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq=3487, + XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3488, + XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3489, + XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq=3490, + XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq=3491, + XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3492, + XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3493, + XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3494, + XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3495, + XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd=3496, + XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd=3497, + XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3498, + XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3499, + XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq=3500, + XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq=3501, + XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3502, + XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3503, + XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3504, + XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3505, + XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq=3506, + XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq=3507, + XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3508, + XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3509, + XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3510, + XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3511, + XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3512, + XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3513, + XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3514, + XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3515, + XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq=3516, + XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq=3517, + XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3518, + XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3519, + XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3520, + XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3521, + XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq=3522, + XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq=3523, + XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3524, + XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3525, + XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq=3526, + XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq=3527, + XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3528, + XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3529, + XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3530, + XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3531, + XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd=3532, + XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd=3533, + XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3534, + XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3535, + XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq=3536, + XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq=3537, + XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3538, + XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3539, + XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3540, + XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3541, + XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq=3542, + XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq=3543, + XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3544, + XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3545, + XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3546, + XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3547, + XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3548, + XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3549, + XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3550, + XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3551, + XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq=3552, + XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq=3553, + XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3554, + XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3555, + XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3556, + XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3557, + XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq=3558, + XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq=3559, + XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3560, + XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3561, + XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq=3562, + XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq=3563, + XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3564, + XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3565, + XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3566, + XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3567, + XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd=3568, + XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd=3569, + XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3570, + XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3571, + XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3572, + XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3573, + XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3574, + XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3575, + XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3576, + XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3577, + XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3578, + XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3579, + XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3580, + XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3581, + XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3582, + XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3583, + XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq=3584, + XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq=3585, + XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq=3586, + XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd=3587, + XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd=3588, + XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd=3589, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128=3590, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256=3591, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512=3592, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3593, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512=3594, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512=3595, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128=3596, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256=3597, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512=3598, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512=3599, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512=3600, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512=3601, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128=3602, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256=3603, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512=3604, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3605, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512=3606, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512=3607, + XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512=3608, + XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3609, + XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512=3610, + XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512=3611, + XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512=3612, + XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3613, + XED_IFORM_VFRCZPD_XMMdq_MEMdq=3614, + XED_IFORM_VFRCZPD_XMMdq_XMMdq=3615, + XED_IFORM_VFRCZPD_YMMqq_MEMqq=3616, + XED_IFORM_VFRCZPD_YMMqq_YMMqq=3617, + XED_IFORM_VFRCZPS_XMMdq_MEMdq=3618, + XED_IFORM_VFRCZPS_XMMdq_XMMdq=3619, + XED_IFORM_VFRCZPS_YMMqq_MEMqq=3620, + XED_IFORM_VFRCZPS_YMMqq_YMMqq=3621, + XED_IFORM_VFRCZSD_XMMdq_MEMq=3622, + XED_IFORM_VFRCZSD_XMMdq_XMMq=3623, + XED_IFORM_VFRCZSS_XMMdq_MEMd=3624, + XED_IFORM_VFRCZSS_XMMdq_XMMd=3625, + XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3626, + XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128=3627, + XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3628, + XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256=3629, + XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3630, + XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3631, + XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128=3632, + XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256=3633, + XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256=3634, + XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512=3635, + XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=3636, + XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=3637, + XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=3638, + XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=3639, + XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=3640, + XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=3641, + XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=3642, + XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=3643, + XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3644, + XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128=3645, + XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3646, + XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256=3647, + XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3648, + XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3649, + XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256=3650, + XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128=3651, + XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256=3652, + XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512=3653, + XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512=3654, + XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512=3655, + XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512=3656, + XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512=3657, + XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512=3658, + XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3659, + XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512=3660, + XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512=3661, + XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512=3662, + XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512=3663, + XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512=3664, + XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512=3665, + XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512=3666, + XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512=3667, + XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512=3668, + XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512=3669, + XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512=3670, + XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3671, + XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3672, + XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3673, + XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3674, + XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3675, + XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3676, + XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3677, + XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=3678, + XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=3679, + XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=3680, + XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=3681, + XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=3682, + XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=3683, + XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=3684, + XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=3685, + XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=3686, + XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=3687, + XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=3688, + XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=3689, + XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=3690, + XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=3691, + XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=3692, + XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=3693, + XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=3694, + XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=3695, + XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=3696, + XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=3697, + XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=3698, + XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=3699, + XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=3700, + XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=3701, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3702, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3703, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8=3704, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8=3705, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3706, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3707, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8=3708, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8=3709, + XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3710, + XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3711, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3712, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3713, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8=3714, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8=3715, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3716, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3717, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8=3718, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8=3719, + XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3720, + XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3721, + XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3722, + XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3723, + XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8=3724, + XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8=3725, + XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3726, + XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3727, + XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8=3728, + XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8=3729, + XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3730, + XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3731, + XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq=3732, + XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq=3733, + XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq=3734, + XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq=3735, + XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq=3736, + XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq=3737, + XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq=3738, + XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq=3739, + XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq=3740, + XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq=3741, + XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq=3742, + XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq=3743, + XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq=3744, + XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq=3745, + XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq=3746, + XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq=3747, + XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb=3748, + XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb=3749, + XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=3750, + XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512=3751, + XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3752, + XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512=3753, + XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3754, + XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512=3755, + XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=3756, + XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512=3757, + XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3758, + XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512=3759, + XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3760, + XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512=3761, + XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb=3762, + XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb=3763, + XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=3764, + XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512=3765, + XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3766, + XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512=3767, + XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3768, + XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512=3769, + XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=3770, + XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512=3771, + XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3772, + XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512=3773, + XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3774, + XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512=3775, + XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb=3776, + XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb=3777, + XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512=3778, + XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512=3779, + XED_IFORM_VLDDQU_XMMdq_MEMdq=3780, + XED_IFORM_VLDDQU_YMMqq_MEMqq=3781, + XED_IFORM_VLDMXCSR_MEMd=3782, + XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq=3783, + XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq=3784, + XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq=3785, + XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq=3786, + XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq=3787, + XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq=3788, + XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq=3789, + XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq=3790, + XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq=3791, + XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq=3792, + XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq=3793, + XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3794, + XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3795, + XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3796, + XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3797, + XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq=3798, + XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq=3799, + XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3800, + XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3801, + XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3802, + XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3803, + XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3804, + XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3805, + XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3806, + XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3807, + XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq=3808, + XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq=3809, + XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3810, + XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3811, + XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3812, + XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3813, + XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq=3814, + XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq=3815, + XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3816, + XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3817, + XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq=3818, + XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq=3819, + XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3820, + XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3821, + XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3822, + XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3823, + XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd=3824, + XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd=3825, + XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3826, + XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3827, + XED_IFORM_VMCALL=3828, + XED_IFORM_VMCLEAR_MEMq=3829, + XED_IFORM_VMFUNC=3830, + XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq=3831, + XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq=3832, + XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3833, + XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3834, + XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3835, + XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3836, + XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq=3837, + XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq=3838, + XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3839, + XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3840, + XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3841, + XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3842, + XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3843, + XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3844, + XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3845, + XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3846, + XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq=3847, + XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq=3848, + XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3849, + XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3850, + XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3851, + XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3852, + XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq=3853, + XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq=3854, + XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3855, + XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3856, + XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq=3857, + XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq=3858, + XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3859, + XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3860, + XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3861, + XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3862, + XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd=3863, + XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd=3864, + XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3865, + XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3866, + XED_IFORM_VMLAUNCH=3867, + XED_IFORM_VMLOAD_ArAX=3868, + XED_IFORM_VMMCALL=3869, + XED_IFORM_VMOVAPD_MEMdq_XMMdq=3870, + XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512=3871, + XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512=3872, + XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512=3873, + XED_IFORM_VMOVAPD_MEMqq_YMMqq=3874, + XED_IFORM_VMOVAPD_XMMdq_MEMdq=3875, + XED_IFORM_VMOVAPD_XMMdq_XMMdq_28=3876, + XED_IFORM_VMOVAPD_XMMdq_XMMdq_29=3877, + XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512=3878, + XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512=3879, + XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512=3880, + XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512=3881, + XED_IFORM_VMOVAPD_YMMqq_MEMqq=3882, + XED_IFORM_VMOVAPD_YMMqq_YMMqq_28=3883, + XED_IFORM_VMOVAPD_YMMqq_YMMqq_29=3884, + XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512=3885, + XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3886, + XED_IFORM_VMOVAPS_MEMdq_XMMdq=3887, + XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512=3888, + XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512=3889, + XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512=3890, + XED_IFORM_VMOVAPS_MEMqq_YMMqq=3891, + XED_IFORM_VMOVAPS_XMMdq_MEMdq=3892, + XED_IFORM_VMOVAPS_XMMdq_XMMdq_28=3893, + XED_IFORM_VMOVAPS_XMMdq_XMMdq_29=3894, + XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512=3895, + XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512=3896, + XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512=3897, + XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512=3898, + XED_IFORM_VMOVAPS_YMMqq_MEMqq=3899, + XED_IFORM_VMOVAPS_YMMqq_YMMqq_28=3900, + XED_IFORM_VMOVAPS_YMMqq_YMMqq_29=3901, + XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512=3902, + XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3903, + XED_IFORM_VMOVD_GPR32d_XMMd=3904, + XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512=3905, + XED_IFORM_VMOVD_MEMd_XMMd=3906, + XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512=3907, + XED_IFORM_VMOVD_XMMdq_GPR32d=3908, + XED_IFORM_VMOVD_XMMdq_MEMd=3909, + XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512=3910, + XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512=3911, + XED_IFORM_VMOVDDUP_XMMdq_MEMq=3912, + XED_IFORM_VMOVDDUP_XMMdq_XMMq=3913, + XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512=3914, + XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512=3915, + XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512=3916, + XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512=3917, + XED_IFORM_VMOVDDUP_YMMqq_MEMqq=3918, + XED_IFORM_VMOVDDUP_YMMqq_YMMqq=3919, + XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512=3920, + XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512=3921, + XED_IFORM_VMOVDQA_MEMdq_XMMdq=3922, + XED_IFORM_VMOVDQA_MEMqq_YMMqq=3923, + XED_IFORM_VMOVDQA_XMMdq_MEMdq=3924, + XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F=3925, + XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F=3926, + XED_IFORM_VMOVDQA_YMMqq_MEMqq=3927, + XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F=3928, + XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F=3929, + XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512=3930, + XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512=3931, + XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512=3932, + XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512=3933, + XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512=3934, + XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512=3935, + XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512=3936, + XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512=3937, + XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512=3938, + XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512=3939, + XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512=3940, + XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512=3941, + XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512=3942, + XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512=3943, + XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512=3944, + XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512=3945, + XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512=3946, + XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512=3947, + XED_IFORM_VMOVDQU_MEMdq_XMMdq=3948, + XED_IFORM_VMOVDQU_MEMqq_YMMqq=3949, + XED_IFORM_VMOVDQU_XMMdq_MEMdq=3950, + XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F=3951, + XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F=3952, + XED_IFORM_VMOVDQU_YMMqq_MEMqq=3953, + XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F=3954, + XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F=3955, + XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512=3956, + XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512=3957, + XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512=3958, + XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512=3959, + XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512=3960, + XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512=3961, + XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512=3962, + XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512=3963, + XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512=3964, + XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512=3965, + XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512=3966, + XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512=3967, + XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512=3968, + XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512=3969, + XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512=3970, + XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512=3971, + XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512=3972, + XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512=3973, + XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512=3974, + XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512=3975, + XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512=3976, + XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512=3977, + XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512=3978, + XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512=3979, + XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512=3980, + XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512=3981, + XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512=3982, + XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512=3983, + XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512=3984, + XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512=3985, + XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512=3986, + XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512=3987, + XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512=3988, + XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512=3989, + XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512=3990, + XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512=3991, + XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq=3992, + XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512=3993, + XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512=3994, + XED_IFORM_VMOVHPD_MEMq_XMMdq=3995, + XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq=3996, + XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512=3997, + XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512=3998, + XED_IFORM_VMOVHPS_MEMq_XMMdq=3999, + XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq=4000, + XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512=4001, + XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq=4002, + XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512=4003, + XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512=4004, + XED_IFORM_VMOVLPD_MEMq_XMMq=4005, + XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq=4006, + XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512=4007, + XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512=4008, + XED_IFORM_VMOVLPS_MEMq_XMMq=4009, + XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq=4010, + XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512=4011, + XED_IFORM_VMOVMSKPD_GPR32d_XMMdq=4012, + XED_IFORM_VMOVMSKPD_GPR32d_YMMqq=4013, + XED_IFORM_VMOVMSKPS_GPR32d_XMMdq=4014, + XED_IFORM_VMOVMSKPS_GPR32d_YMMqq=4015, + XED_IFORM_VMOVNTDQ_MEMdq_XMMdq=4016, + XED_IFORM_VMOVNTDQ_MEMqq_YMMqq=4017, + XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512=4018, + XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512=4019, + XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512=4020, + XED_IFORM_VMOVNTDQA_XMMdq_MEMdq=4021, + XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512=4022, + XED_IFORM_VMOVNTDQA_YMMqq_MEMqq=4023, + XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512=4024, + XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512=4025, + XED_IFORM_VMOVNTPD_MEMdq_XMMdq=4026, + XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512=4027, + XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512=4028, + XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512=4029, + XED_IFORM_VMOVNTPD_MEMqq_YMMqq=4030, + XED_IFORM_VMOVNTPS_MEMdq_XMMdq=4031, + XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512=4032, + XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512=4033, + XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512=4034, + XED_IFORM_VMOVNTPS_MEMqq_YMMqq=4035, + XED_IFORM_VMOVQ_GPR64q_XMMq=4036, + XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512=4037, + XED_IFORM_VMOVQ_MEMq_XMMq_7E=4038, + XED_IFORM_VMOVQ_MEMq_XMMq_D6=4039, + XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512=4040, + XED_IFORM_VMOVQ_XMMdq_GPR64q=4041, + XED_IFORM_VMOVQ_XMMdq_MEMq_6E=4042, + XED_IFORM_VMOVQ_XMMdq_MEMq_7E=4043, + XED_IFORM_VMOVQ_XMMdq_XMMq_7E=4044, + XED_IFORM_VMOVQ_XMMdq_XMMq_D6=4045, + XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512=4046, + XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512=4047, + XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512=4048, + XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512=4049, + XED_IFORM_VMOVSD_MEMq_XMMq=4050, + XED_IFORM_VMOVSD_XMMdq_MEMq=4051, + XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10=4052, + XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11=4053, + XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512=4054, + XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4055, + XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512=4056, + XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512=4057, + XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4058, + XED_IFORM_VMOVSHDUP_XMMdq_MEMdq=4059, + XED_IFORM_VMOVSHDUP_XMMdq_XMMdq=4060, + XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512=4061, + XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512=4062, + XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512=4063, + XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512=4064, + XED_IFORM_VMOVSHDUP_YMMqq_MEMqq=4065, + XED_IFORM_VMOVSHDUP_YMMqq_YMMqq=4066, + XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512=4067, + XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=4068, + XED_IFORM_VMOVSLDUP_XMMdq_MEMdq=4069, + XED_IFORM_VMOVSLDUP_XMMdq_XMMdq=4070, + XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512=4071, + XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512=4072, + XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512=4073, + XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512=4074, + XED_IFORM_VMOVSLDUP_YMMqq_MEMqq=4075, + XED_IFORM_VMOVSLDUP_YMMqq_YMMqq=4076, + XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512=4077, + XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=4078, + XED_IFORM_VMOVSS_MEMd_XMMd=4079, + XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512=4080, + XED_IFORM_VMOVSS_XMMdq_MEMd=4081, + XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10=4082, + XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11=4083, + XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512=4084, + XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4085, + XED_IFORM_VMOVUPD_MEMdq_XMMdq=4086, + XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512=4087, + XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512=4088, + XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512=4089, + XED_IFORM_VMOVUPD_MEMqq_YMMqq=4090, + XED_IFORM_VMOVUPD_XMMdq_MEMdq=4091, + XED_IFORM_VMOVUPD_XMMdq_XMMdq_10=4092, + XED_IFORM_VMOVUPD_XMMdq_XMMdq_11=4093, + XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512=4094, + XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512=4095, + XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512=4096, + XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512=4097, + XED_IFORM_VMOVUPD_YMMqq_MEMqq=4098, + XED_IFORM_VMOVUPD_YMMqq_YMMqq_10=4099, + XED_IFORM_VMOVUPD_YMMqq_YMMqq_11=4100, + XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512=4101, + XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512=4102, + XED_IFORM_VMOVUPS_MEMdq_XMMdq=4103, + XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512=4104, + XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512=4105, + XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512=4106, + XED_IFORM_VMOVUPS_MEMqq_YMMqq=4107, + XED_IFORM_VMOVUPS_XMMdq_MEMdq=4108, + XED_IFORM_VMOVUPS_XMMdq_XMMdq_10=4109, + XED_IFORM_VMOVUPS_XMMdq_XMMdq_11=4110, + XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512=4111, + XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512=4112, + XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512=4113, + XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512=4114, + XED_IFORM_VMOVUPS_YMMqq_MEMqq=4115, + XED_IFORM_VMOVUPS_YMMqq_YMMqq_10=4116, + XED_IFORM_VMOVUPS_YMMqq_YMMqq_11=4117, + XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512=4118, + XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512=4119, + XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512=4120, + XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512=4121, + XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512=4122, + XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512=4123, + XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb=4124, + XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb=4125, + XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb=4126, + XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb=4127, + XED_IFORM_VMPTRLD_MEMq=4128, + XED_IFORM_VMPTRST_MEMq=4129, + XED_IFORM_VMREAD_GPR32_GPR32=4130, + XED_IFORM_VMREAD_GPR64_GPR64=4131, + XED_IFORM_VMREAD_MEMd_GPR32=4132, + XED_IFORM_VMREAD_MEMq_GPR64=4133, + XED_IFORM_VMRESUME=4134, + XED_IFORM_VMRUN_ArAX=4135, + XED_IFORM_VMSAVE=4136, + XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq=4137, + XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq=4138, + XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4139, + XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4140, + XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4141, + XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4142, + XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq=4143, + XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq=4144, + XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4145, + XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4146, + XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=4147, + XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4148, + XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=4149, + XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=4150, + XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=4151, + XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=4152, + XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq=4153, + XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq=4154, + XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4155, + XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4156, + XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4157, + XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4158, + XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq=4159, + XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq=4160, + XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4161, + XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4162, + XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq=4163, + XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq=4164, + XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4165, + XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4166, + XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=4167, + XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4168, + XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd=4169, + XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd=4170, + XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4171, + XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4172, + XED_IFORM_VMWRITE_GPR32_GPR32=4173, + XED_IFORM_VMWRITE_GPR32_MEMd=4174, + XED_IFORM_VMWRITE_GPR64_GPR64=4175, + XED_IFORM_VMWRITE_GPR64_MEMq=4176, + XED_IFORM_VMXOFF=4177, + XED_IFORM_VMXON_MEMq=4178, + XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq=4179, + XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq=4180, + XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4181, + XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4182, + XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq=4183, + XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq=4184, + XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4185, + XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4186, + XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4187, + XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4188, + XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq=4189, + XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq=4190, + XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4191, + XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4192, + XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq=4193, + XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq=4194, + XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4195, + XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4196, + XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4197, + XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4198, + XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512=4199, + XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512=4200, + XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512=4201, + XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512=4202, + XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512=4203, + XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512=4204, + XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512=4205, + XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512=4206, + XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512=4207, + XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512=4208, + XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512=4209, + XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512=4210, + XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4211, + XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4212, + XED_IFORM_VPABSB_XMMdq_MEMdq=4213, + XED_IFORM_VPABSB_XMMdq_XMMdq=4214, + XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512=4215, + XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512=4216, + XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512=4217, + XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512=4218, + XED_IFORM_VPABSB_YMMqq_MEMqq=4219, + XED_IFORM_VPABSB_YMMqq_YMMqq=4220, + XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512=4221, + XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512=4222, + XED_IFORM_VPABSD_XMMdq_MEMdq=4223, + XED_IFORM_VPABSD_XMMdq_XMMdq=4224, + XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512=4225, + XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512=4226, + XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512=4227, + XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512=4228, + XED_IFORM_VPABSD_YMMqq_MEMqq=4229, + XED_IFORM_VPABSD_YMMqq_YMMqq=4230, + XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512=4231, + XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512=4232, + XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512=4233, + XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512=4234, + XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512=4235, + XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512=4236, + XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512=4237, + XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512=4238, + XED_IFORM_VPABSW_XMMdq_MEMdq=4239, + XED_IFORM_VPABSW_XMMdq_XMMdq=4240, + XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512=4241, + XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512=4242, + XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512=4243, + XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512=4244, + XED_IFORM_VPABSW_YMMqq_MEMqq=4245, + XED_IFORM_VPABSW_YMMqq_YMMqq=4246, + XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512=4247, + XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512=4248, + XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq=4249, + XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq=4250, + XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512=4251, + XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512=4252, + XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512=4253, + XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512=4254, + XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq=4255, + XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq=4256, + XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512=4257, + XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512=4258, + XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq=4259, + XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq=4260, + XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512=4261, + XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512=4262, + XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512=4263, + XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512=4264, + XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq=4265, + XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq=4266, + XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512=4267, + XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512=4268, + XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq=4269, + XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq=4270, + XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512=4271, + XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512=4272, + XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq=4273, + XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq=4274, + XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512=4275, + XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512=4276, + XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512=4277, + XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512=4278, + XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq=4279, + XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq=4280, + XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512=4281, + XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512=4282, + XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq=4283, + XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq=4284, + XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512=4285, + XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512=4286, + XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512=4287, + XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512=4288, + XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq=4289, + XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq=4290, + XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4291, + XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4292, + XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq=4293, + XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq=4294, + XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4295, + XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4296, + XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4297, + XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4298, + XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq=4299, + XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq=4300, + XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4301, + XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4302, + XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq=4303, + XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq=4304, + XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4305, + XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4306, + XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4307, + XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4308, + XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq=4309, + XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq=4310, + XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4311, + XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4312, + XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq=4313, + XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq=4314, + XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4315, + XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4316, + XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4317, + XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4318, + XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq=4319, + XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq=4320, + XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=4321, + XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=4322, + XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=4323, + XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=4324, + XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq=4325, + XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq=4326, + XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=4327, + XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=4328, + XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq=4329, + XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq=4330, + XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=4331, + XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=4332, + XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=4333, + XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=4334, + XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq=4335, + XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq=4336, + XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=4337, + XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=4338, + XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq=4339, + XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq=4340, + XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4341, + XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4342, + XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq=4343, + XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq=4344, + XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4345, + XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4346, + XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4347, + XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4348, + XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq=4349, + XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq=4350, + XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4351, + XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4352, + XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq=4353, + XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq=4354, + XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4355, + XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4356, + XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4357, + XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4358, + XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq=4359, + XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq=4360, + XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4361, + XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4362, + XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq=4363, + XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq=4364, + XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4365, + XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4366, + XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4367, + XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4368, + XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb=4369, + XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb=4370, + XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4371, + XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4372, + XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb=4373, + XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb=4374, + XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4375, + XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4376, + XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4377, + XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4378, + XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq=4379, + XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq=4380, + XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq=4381, + XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq=4382, + XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4383, + XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4384, + XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4385, + XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4386, + XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4387, + XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4388, + XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq=4389, + XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq=4390, + XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq=4391, + XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq=4392, + XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4393, + XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4394, + XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4395, + XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4396, + XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4397, + XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4398, + XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4399, + XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4400, + XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4401, + XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4402, + XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4403, + XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4404, + XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4405, + XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4406, + XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4407, + XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4408, + XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4409, + XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4410, + XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq=4411, + XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq=4412, + XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4413, + XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4414, + XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq=4415, + XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq=4416, + XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4417, + XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4418, + XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4419, + XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4420, + XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq=4421, + XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq=4422, + XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4423, + XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4424, + XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq=4425, + XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq=4426, + XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4427, + XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4428, + XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4429, + XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4430, + XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb=4431, + XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb=4432, + XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb=4433, + XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb=4434, + XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4435, + XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4436, + XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4437, + XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4438, + XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4439, + XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4440, + XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4441, + XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4442, + XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4443, + XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4444, + XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4445, + XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4446, + XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4447, + XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4448, + XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4449, + XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4450, + XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4451, + XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4452, + XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4453, + XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4454, + XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4455, + XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4456, + XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4457, + XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4458, + XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq=4459, + XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq=4460, + XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq=4461, + XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq=4462, + XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb=4463, + XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb=4464, + XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb=4465, + XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb=4466, + XED_IFORM_VPBROADCASTB_XMMdq_MEMb=4467, + XED_IFORM_VPBROADCASTB_XMMdq_XMMb=4468, + XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512=4469, + XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512=4470, + XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512=4471, + XED_IFORM_VPBROADCASTB_YMMqq_MEMb=4472, + XED_IFORM_VPBROADCASTB_YMMqq_XMMb=4473, + XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512=4474, + XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512=4475, + XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512=4476, + XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512=4477, + XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512=4478, + XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512=4479, + XED_IFORM_VPBROADCASTD_XMMdq_MEMd=4480, + XED_IFORM_VPBROADCASTD_XMMdq_XMMd=4481, + XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512=4482, + XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512=4483, + XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512=4484, + XED_IFORM_VPBROADCASTD_YMMqq_MEMd=4485, + XED_IFORM_VPBROADCASTD_YMMqq_XMMd=4486, + XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512=4487, + XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512=4488, + XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512=4489, + XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512=4490, + XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512=4491, + XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512=4492, + XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512=4493, + XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512=4494, + XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD=4495, + XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512=4496, + XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512=4497, + XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD=4498, + XED_IFORM_VPBROADCASTQ_XMMdq_MEMq=4499, + XED_IFORM_VPBROADCASTQ_XMMdq_XMMq=4500, + XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512=4501, + XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512=4502, + XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512=4503, + XED_IFORM_VPBROADCASTQ_YMMqq_MEMq=4504, + XED_IFORM_VPBROADCASTQ_YMMqq_XMMq=4505, + XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512=4506, + XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512=4507, + XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512=4508, + XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512=4509, + XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512=4510, + XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512=4511, + XED_IFORM_VPBROADCASTW_XMMdq_MEMw=4512, + XED_IFORM_VPBROADCASTW_XMMdq_XMMw=4513, + XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512=4514, + XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512=4515, + XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512=4516, + XED_IFORM_VPBROADCASTW_YMMqq_MEMw=4517, + XED_IFORM_VPBROADCASTW_YMMqq_XMMw=4518, + XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512=4519, + XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512=4520, + XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512=4521, + XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512=4522, + XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512=4523, + XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512=4524, + XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb=4525, + XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb=4526, + XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512=4527, + XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512=4528, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8=4529, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512=4530, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8=4531, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512=4532, + XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512=4533, + XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512=4534, + XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq=4535, + XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq=4536, + XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq=4537, + XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq=4538, + XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq=4539, + XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq=4540, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512=4541, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512=4542, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512=4543, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512=4544, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512=4545, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512=4546, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512=4547, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512=4548, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512=4549, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512=4550, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512=4551, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512=4552, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4553, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4554, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4555, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4556, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4557, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4558, + XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq=4559, + XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq=4560, + XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq=4561, + XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq=4562, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=4563, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=4564, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=4565, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=4566, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=4567, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=4568, + XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq=4569, + XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq=4570, + XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq=4571, + XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq=4572, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=4573, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=4574, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=4575, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=4576, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=4577, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=4578, + XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq=4579, + XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq=4580, + XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq=4581, + XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq=4582, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4583, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4584, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4585, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4586, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4587, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4588, + XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq=4589, + XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq=4590, + XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq=4591, + XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq=4592, + XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb=4593, + XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb=4594, + XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb=4595, + XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb=4596, + XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb=4597, + XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb=4598, + XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb=4599, + XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb=4600, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4601, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4602, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4603, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4604, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4605, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4606, + XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq=4607, + XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq=4608, + XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq=4609, + XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq=4610, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512=4611, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512=4612, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512=4613, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512=4614, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512=4615, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512=4616, + XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq=4617, + XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq=4618, + XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq=4619, + XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq=4620, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512=4621, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512=4622, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512=4623, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512=4624, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512=4625, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512=4626, + XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq=4627, + XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq=4628, + XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq=4629, + XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq=4630, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4631, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4632, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4633, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4634, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4635, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4636, + XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq=4637, + XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq=4638, + XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq=4639, + XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq=4640, + XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb=4641, + XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb=4642, + XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb=4643, + XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb=4644, + XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb=4645, + XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb=4646, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512=4647, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512=4648, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512=4649, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512=4650, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512=4651, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512=4652, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4653, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4654, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4655, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4656, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4657, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4658, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=4659, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=4660, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=4661, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=4662, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=4663, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=4664, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=4665, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=4666, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=4667, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=4668, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=4669, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=4670, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=4671, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=4672, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=4673, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=4674, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=4675, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=4676, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512=4677, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512=4678, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512=4679, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512=4680, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512=4681, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512=4682, + XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb=4683, + XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb=4684, + XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb=4685, + XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb=4686, + XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512=4687, + XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512=4688, + XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512=4689, + XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512=4690, + XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512=4691, + XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512=4692, + XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512=4693, + XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512=4694, + XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512=4695, + XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512=4696, + XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512=4697, + XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512=4698, + XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512=4699, + XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512=4700, + XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512=4701, + XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512=4702, + XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512=4703, + XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4704, + XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512=4705, + XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512=4706, + XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512=4707, + XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512=4708, + XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512=4709, + XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512=4710, + XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb=4711, + XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb=4712, + XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb=4713, + XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb=4714, + XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb=4715, + XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb=4716, + XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb=4717, + XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb=4718, + XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb=4719, + XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb=4720, + XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb=4721, + XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb=4722, + XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512=4723, + XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512=4724, + XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512=4725, + XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512=4726, + XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=4727, + XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=4728, + XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512=4729, + XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512=4730, + XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512=4731, + XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512=4732, + XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=4733, + XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=4734, + XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4735, + XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4736, + XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32=4737, + XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32=4738, + XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4739, + XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4740, + XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32=4741, + XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32=4742, + XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4743, + XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4744, + XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4745, + XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4746, + XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32=4747, + XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32=4748, + XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4749, + XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4750, + XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32=4751, + XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32=4752, + XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4753, + XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4754, + XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4755, + XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4756, + XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32=4757, + XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32=4758, + XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4759, + XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4760, + XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32=4761, + XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32=4762, + XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4763, + XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4764, + XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4765, + XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4766, + XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32=4767, + XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32=4768, + XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4769, + XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4770, + XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32=4771, + XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32=4772, + XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4773, + XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4774, + XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb=4775, + XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb=4776, + XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb=4777, + XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb=4778, + XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4779, + XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4780, + XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4781, + XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4782, + XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4783, + XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4784, + XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq=4785, + XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq=4786, + XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4787, + XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4788, + XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4789, + XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4790, + XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4791, + XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4792, + XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4793, + XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4794, + XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4795, + XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4796, + XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4797, + XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4798, + XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4799, + XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4800, + XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4801, + XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4802, + XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4803, + XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4804, + XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4805, + XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4806, + XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4807, + XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4808, + XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4809, + XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4810, + XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4811, + XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4812, + XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4813, + XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4814, + XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4815, + XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4816, + XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4817, + XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4818, + XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4819, + XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4820, + XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4821, + XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4822, + XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4823, + XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4824, + XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4825, + XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4826, + XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4827, + XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4828, + XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4829, + XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4830, + XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4831, + XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4832, + XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4833, + XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4834, + XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4835, + XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4836, + XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4837, + XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4838, + XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb=4839, + XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb=4840, + XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq=4841, + XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq=4842, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=4843, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=4844, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4845, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4846, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4847, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4848, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4849, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4850, + XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb=4851, + XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb=4852, + XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq=4853, + XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq=4854, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4855, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4856, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4857, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4858, + XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb=4859, + XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb=4860, + XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq=4861, + XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq=4862, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=4863, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=4864, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4865, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4866, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=4867, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=4868, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4869, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4870, + XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb=4871, + XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb=4872, + XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq=4873, + XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq=4874, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=4875, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=4876, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4877, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4878, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4879, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4880, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4881, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4882, + XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb=4883, + XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb=4884, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4885, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4886, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4887, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4888, + XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4889, + XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4890, + XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq=4891, + XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq=4892, + XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4893, + XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4894, + XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb=4895, + XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb=4896, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=4897, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=4898, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4899, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4900, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=4901, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=4902, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4903, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4904, + XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4905, + XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4906, + XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4907, + XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4908, + XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4909, + XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4910, + XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4911, + XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4912, + XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4913, + XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4914, + XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4915, + XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4916, + XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4917, + XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4918, + XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4919, + XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4920, + XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4921, + XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4922, + XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4923, + XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4924, + XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4925, + XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4926, + XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4927, + XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4928, + XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4929, + XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4930, + XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4931, + XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4932, + XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4933, + XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4934, + XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4935, + XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4936, + XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4937, + XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4938, + XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4939, + XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4940, + XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4941, + XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4942, + XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4943, + XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4944, + XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4945, + XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4946, + XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512=4947, + XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512=4948, + XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512=4949, + XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512=4950, + XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512=4951, + XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512=4952, + XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512=4953, + XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512=4954, + XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512=4955, + XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512=4956, + XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512=4957, + XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512=4958, + XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512=4959, + XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512=4960, + XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512=4961, + XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512=4962, + XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512=4963, + XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4964, + XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512=4965, + XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512=4966, + XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512=4967, + XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512=4968, + XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512=4969, + XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512=4970, + XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb=4971, + XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512=4972, + XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb=4973, + XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512=4974, + XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb=4975, + XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512=4976, + XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb=4977, + XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512=4978, + XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb=4979, + XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512=4980, + XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb=4981, + XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512=4982, + XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15=4983, + XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5=4984, + XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512=4985, + XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512=4986, + XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb=4987, + XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5=4988, + XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4989, + XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128=4990, + XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256=4991, + XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256=4992, + XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512=4993, + XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=4994, + XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128=4995, + XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=4996, + XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256=4997, + XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=4998, + XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4999, + XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256=5000, + XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128=5001, + XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256=5002, + XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512=5003, + XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=5004, + XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128=5005, + XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=5006, + XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256=5007, + XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=5008, + XED_IFORM_VPHADDBD_XMMdq_MEMdq=5009, + XED_IFORM_VPHADDBD_XMMdq_XMMdq=5010, + XED_IFORM_VPHADDBQ_XMMdq_MEMdq=5011, + XED_IFORM_VPHADDBQ_XMMdq_XMMdq=5012, + XED_IFORM_VPHADDBW_XMMdq_MEMdq=5013, + XED_IFORM_VPHADDBW_XMMdq_XMMdq=5014, + XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq=5015, + XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq=5016, + XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq=5017, + XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq=5018, + XED_IFORM_VPHADDDQ_XMMdq_MEMdq=5019, + XED_IFORM_VPHADDDQ_XMMdq_XMMdq=5020, + XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq=5021, + XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq=5022, + XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq=5023, + XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq=5024, + XED_IFORM_VPHADDUBD_XMMdq_MEMdq=5025, + XED_IFORM_VPHADDUBD_XMMdq_XMMdq=5026, + XED_IFORM_VPHADDUBQ_XMMdq_MEMdq=5027, + XED_IFORM_VPHADDUBQ_XMMdq_XMMdq=5028, + XED_IFORM_VPHADDUBW_XMMdq_MEMdq=5029, + XED_IFORM_VPHADDUBW_XMMdq_XMMdq=5030, + XED_IFORM_VPHADDUDQ_XMMdq_MEMdq=5031, + XED_IFORM_VPHADDUDQ_XMMdq_XMMdq=5032, + XED_IFORM_VPHADDUWD_XMMdq_MEMdq=5033, + XED_IFORM_VPHADDUWD_XMMdq_XMMdq=5034, + XED_IFORM_VPHADDUWQ_XMMdq_MEMdq=5035, + XED_IFORM_VPHADDUWQ_XMMdq_XMMdq=5036, + XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq=5037, + XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq=5038, + XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq=5039, + XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq=5040, + XED_IFORM_VPHADDWD_XMMdq_MEMdq=5041, + XED_IFORM_VPHADDWD_XMMdq_XMMdq=5042, + XED_IFORM_VPHADDWQ_XMMdq_MEMdq=5043, + XED_IFORM_VPHADDWQ_XMMdq_XMMdq=5044, + XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq=5045, + XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq=5046, + XED_IFORM_VPHSUBBW_XMMdq_MEMdq=5047, + XED_IFORM_VPHSUBBW_XMMdq_XMMdq=5048, + XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq=5049, + XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq=5050, + XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq=5051, + XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq=5052, + XED_IFORM_VPHSUBDQ_XMMdq_MEMdq=5053, + XED_IFORM_VPHSUBDQ_XMMdq_XMMdq=5054, + XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq=5055, + XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq=5056, + XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq=5057, + XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq=5058, + XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq=5059, + XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq=5060, + XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq=5061, + XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq=5062, + XED_IFORM_VPHSUBWD_XMMdq_MEMdq=5063, + XED_IFORM_VPHSUBWD_XMMdq_XMMdq=5064, + XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb=5065, + XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb=5066, + XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512=5067, + XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512=5068, + XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb=5069, + XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb=5070, + XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512=5071, + XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512=5072, + XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb=5073, + XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb=5074, + XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512=5075, + XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512=5076, + XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb=5077, + XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb=5078, + XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512=5079, + XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512=5080, + XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5081, + XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5082, + XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5083, + XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5084, + XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=5085, + XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=5086, + XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5087, + XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5088, + XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5089, + XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5090, + XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=5091, + XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=5092, + XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq=5093, + XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq=5094, + XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq=5095, + XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq=5096, + XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq=5097, + XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq=5098, + XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq=5099, + XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq=5100, + XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq=5101, + XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq=5102, + XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq=5103, + XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq=5104, + XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq=5105, + XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq=5106, + XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq=5107, + XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq=5108, + XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq=5109, + XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq=5110, + XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq=5111, + XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq=5112, + XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq=5113, + XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq=5114, + XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq=5115, + XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq=5116, + XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5117, + XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5118, + XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5119, + XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5120, + XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5121, + XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5122, + XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5123, + XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5124, + XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5125, + XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5126, + XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5127, + XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5128, + XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq=5129, + XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq=5130, + XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5131, + XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5132, + XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5133, + XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5134, + XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq=5135, + XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq=5136, + XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5137, + XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5138, + XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq=5139, + XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq=5140, + XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512=5141, + XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512=5142, + XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512=5143, + XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512=5144, + XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq=5145, + XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq=5146, + XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512=5147, + XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512=5148, + XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq=5149, + XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq=5150, + XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq=5151, + XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq=5152, + XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq=5153, + XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq=5154, + XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq=5155, + XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq=5156, + XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq=5157, + XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq=5158, + XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5159, + XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5160, + XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5161, + XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5162, + XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq=5163, + XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq=5164, + XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5165, + XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5166, + XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq=5167, + XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq=5168, + XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=5169, + XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=5170, + XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=5171, + XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=5172, + XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq=5173, + XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq=5174, + XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=5175, + XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=5176, + XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=5177, + XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=5178, + XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=5179, + XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=5180, + XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=5181, + XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=5182, + XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq=5183, + XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq=5184, + XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5185, + XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5186, + XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5187, + XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5188, + XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq=5189, + XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq=5190, + XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5191, + XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5192, + XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq=5193, + XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq=5194, + XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5195, + XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5196, + XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq=5197, + XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq=5198, + XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5199, + XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5200, + XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5201, + XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5202, + XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq=5203, + XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq=5204, + XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5205, + XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5206, + XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq=5207, + XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq=5208, + XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5209, + XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5210, + XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5211, + XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5212, + XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5213, + XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5214, + XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5215, + XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5216, + XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5217, + XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5218, + XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq=5219, + XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq=5220, + XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5221, + XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5222, + XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq=5223, + XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq=5224, + XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5225, + XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5226, + XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5227, + XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5228, + XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq=5229, + XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq=5230, + XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5231, + XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5232, + XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5233, + XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5234, + XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq=5235, + XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq=5236, + XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5237, + XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5238, + XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq=5239, + XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq=5240, + XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=5241, + XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=5242, + XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=5243, + XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=5244, + XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq=5245, + XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq=5246, + XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=5247, + XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=5248, + XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=5249, + XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=5250, + XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=5251, + XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=5252, + XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=5253, + XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=5254, + XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq=5255, + XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq=5256, + XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5257, + XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5258, + XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5259, + XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5260, + XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq=5261, + XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq=5262, + XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5263, + XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5264, + XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq=5265, + XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq=5266, + XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5267, + XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5268, + XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq=5269, + XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq=5270, + XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5271, + XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5272, + XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5273, + XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5274, + XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq=5275, + XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq=5276, + XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5277, + XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5278, + XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq=5279, + XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq=5280, + XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5281, + XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5282, + XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5283, + XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5284, + XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5285, + XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5286, + XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5287, + XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5288, + XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5289, + XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5290, + XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq=5291, + XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq=5292, + XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5293, + XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5294, + XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq=5295, + XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq=5296, + XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5297, + XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5298, + XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5299, + XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5300, + XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512=5301, + XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512=5302, + XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512=5303, + XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512=5304, + XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512=5305, + XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512=5306, + XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512=5307, + XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512=5308, + XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512=5309, + XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512=5310, + XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512=5311, + XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512=5312, + XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512=5313, + XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512=5314, + XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512=5315, + XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512=5316, + XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512=5317, + XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512=5318, + XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512=5319, + XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512=5320, + XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512=5321, + XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512=5322, + XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512=5323, + XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512=5324, + XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512=5325, + XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512=5326, + XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512=5327, + XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512=5328, + XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512=5329, + XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512=5330, + XED_IFORM_VPMOVMSKB_GPR32d_XMMdq=5331, + XED_IFORM_VPMOVMSKB_GPR32d_YMMqq=5332, + XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512=5333, + XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512=5334, + XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512=5335, + XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512=5336, + XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512=5337, + XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512=5338, + XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512=5339, + XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512=5340, + XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512=5341, + XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512=5342, + XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512=5343, + XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512=5344, + XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512=5345, + XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512=5346, + XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512=5347, + XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512=5348, + XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512=5349, + XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512=5350, + XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512=5351, + XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512=5352, + XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512=5353, + XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512=5354, + XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512=5355, + XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512=5356, + XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512=5357, + XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512=5358, + XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512=5359, + XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512=5360, + XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512=5361, + XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512=5362, + XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512=5363, + XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512=5364, + XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512=5365, + XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512=5366, + XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512=5367, + XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512=5368, + XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512=5369, + XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512=5370, + XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512=5371, + XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512=5372, + XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512=5373, + XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512=5374, + XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512=5375, + XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512=5376, + XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512=5377, + XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512=5378, + XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512=5379, + XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512=5380, + XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512=5381, + XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512=5382, + XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512=5383, + XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512=5384, + XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512=5385, + XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512=5386, + XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512=5387, + XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512=5388, + XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512=5389, + XED_IFORM_VPMOVSXBD_XMMdq_MEMd=5390, + XED_IFORM_VPMOVSXBD_XMMdq_XMMd=5391, + XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512=5392, + XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512=5393, + XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512=5394, + XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512=5395, + XED_IFORM_VPMOVSXBD_YMMqq_MEMq=5396, + XED_IFORM_VPMOVSXBD_YMMqq_XMMq=5397, + XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5398, + XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5399, + XED_IFORM_VPMOVSXBQ_XMMdq_MEMw=5400, + XED_IFORM_VPMOVSXBQ_XMMdq_XMMw=5401, + XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5402, + XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5403, + XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5404, + XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5405, + XED_IFORM_VPMOVSXBQ_YMMqq_MEMd=5406, + XED_IFORM_VPMOVSXBQ_YMMqq_XMMd=5407, + XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5408, + XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5409, + XED_IFORM_VPMOVSXBW_XMMdq_MEMq=5410, + XED_IFORM_VPMOVSXBW_XMMdq_XMMq=5411, + XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512=5412, + XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512=5413, + XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512=5414, + XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512=5415, + XED_IFORM_VPMOVSXBW_YMMqq_MEMdq=5416, + XED_IFORM_VPMOVSXBW_YMMqq_XMMdq=5417, + XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5418, + XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5419, + XED_IFORM_VPMOVSXDQ_XMMdq_MEMq=5420, + XED_IFORM_VPMOVSXDQ_XMMdq_XMMq=5421, + XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5422, + XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5423, + XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5424, + XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5425, + XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq=5426, + XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq=5427, + XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5428, + XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5429, + XED_IFORM_VPMOVSXWD_XMMdq_MEMq=5430, + XED_IFORM_VPMOVSXWD_XMMdq_XMMq=5431, + XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512=5432, + XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512=5433, + XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512=5434, + XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512=5435, + XED_IFORM_VPMOVSXWD_YMMqq_MEMdq=5436, + XED_IFORM_VPMOVSXWD_YMMqq_XMMdq=5437, + XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5438, + XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5439, + XED_IFORM_VPMOVSXWQ_XMMdq_MEMd=5440, + XED_IFORM_VPMOVSXWQ_XMMdq_XMMd=5441, + XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5442, + XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5443, + XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5444, + XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5445, + XED_IFORM_VPMOVSXWQ_YMMqq_MEMq=5446, + XED_IFORM_VPMOVSXWQ_YMMqq_XMMq=5447, + XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5448, + XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5449, + XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512=5450, + XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512=5451, + XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512=5452, + XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512=5453, + XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512=5454, + XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512=5455, + XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512=5456, + XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512=5457, + XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512=5458, + XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512=5459, + XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512=5460, + XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512=5461, + XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512=5462, + XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512=5463, + XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512=5464, + XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512=5465, + XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512=5466, + XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512=5467, + XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512=5468, + XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512=5469, + XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512=5470, + XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512=5471, + XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512=5472, + XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512=5473, + XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512=5474, + XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512=5475, + XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512=5476, + XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512=5477, + XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512=5478, + XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512=5479, + XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512=5480, + XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512=5481, + XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512=5482, + XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512=5483, + XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512=5484, + XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512=5485, + XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512=5486, + XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512=5487, + XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512=5488, + XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512=5489, + XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512=5490, + XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512=5491, + XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512=5492, + XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512=5493, + XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512=5494, + XED_IFORM_VPMOVZXBD_XMMdq_MEMd=5495, + XED_IFORM_VPMOVZXBD_XMMdq_XMMd=5496, + XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512=5497, + XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512=5498, + XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512=5499, + XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512=5500, + XED_IFORM_VPMOVZXBD_YMMqq_MEMq=5501, + XED_IFORM_VPMOVZXBD_YMMqq_XMMq=5502, + XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5503, + XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5504, + XED_IFORM_VPMOVZXBQ_XMMdq_MEMw=5505, + XED_IFORM_VPMOVZXBQ_XMMdq_XMMw=5506, + XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5507, + XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5508, + XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5509, + XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5510, + XED_IFORM_VPMOVZXBQ_YMMqq_MEMd=5511, + XED_IFORM_VPMOVZXBQ_YMMqq_XMMd=5512, + XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5513, + XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5514, + XED_IFORM_VPMOVZXBW_XMMdq_MEMq=5515, + XED_IFORM_VPMOVZXBW_XMMdq_XMMq=5516, + XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512=5517, + XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512=5518, + XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512=5519, + XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512=5520, + XED_IFORM_VPMOVZXBW_YMMqq_MEMdq=5521, + XED_IFORM_VPMOVZXBW_YMMqq_XMMdq=5522, + XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5523, + XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5524, + XED_IFORM_VPMOVZXDQ_XMMdq_MEMq=5525, + XED_IFORM_VPMOVZXDQ_XMMdq_XMMq=5526, + XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5527, + XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5528, + XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5529, + XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5530, + XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq=5531, + XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq=5532, + XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5533, + XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5534, + XED_IFORM_VPMOVZXWD_XMMdq_MEMq=5535, + XED_IFORM_VPMOVZXWD_XMMdq_XMMq=5536, + XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512=5537, + XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512=5538, + XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512=5539, + XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512=5540, + XED_IFORM_VPMOVZXWD_YMMqq_MEMdq=5541, + XED_IFORM_VPMOVZXWD_YMMqq_XMMdq=5542, + XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5543, + XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5544, + XED_IFORM_VPMOVZXWQ_XMMdq_MEMd=5545, + XED_IFORM_VPMOVZXWQ_XMMdq_XMMd=5546, + XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5547, + XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5548, + XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5549, + XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5550, + XED_IFORM_VPMOVZXWQ_YMMqq_MEMq=5551, + XED_IFORM_VPMOVZXWQ_YMMqq_XMMq=5552, + XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5553, + XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5554, + XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq=5555, + XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq=5556, + XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512=5557, + XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512=5558, + XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512=5559, + XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512=5560, + XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq=5561, + XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq=5562, + XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512=5563, + XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512=5564, + XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq=5565, + XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq=5566, + XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5567, + XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5568, + XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5569, + XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5570, + XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq=5571, + XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq=5572, + XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5573, + XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5574, + XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq=5575, + XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq=5576, + XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5577, + XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5578, + XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq=5579, + XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq=5580, + XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5581, + XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5582, + XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5583, + XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5584, + XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq=5585, + XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq=5586, + XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5587, + XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5588, + XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq=5589, + XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq=5590, + XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5591, + XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5592, + XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5593, + XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5594, + XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq=5595, + XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq=5596, + XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5597, + XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5598, + XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq=5599, + XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq=5600, + XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5601, + XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5602, + XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5603, + XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5604, + XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5605, + XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5606, + XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5607, + XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5608, + XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5609, + XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5610, + XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq=5611, + XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq=5612, + XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5613, + XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5614, + XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq=5615, + XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq=5616, + XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5617, + XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5618, + XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5619, + XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5620, + XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512=5621, + XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512=5622, + XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512=5623, + XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512=5624, + XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512=5625, + XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512=5626, + XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq=5627, + XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq=5628, + XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512=5629, + XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512=5630, + XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq=5631, + XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq=5632, + XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512=5633, + XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512=5634, + XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512=5635, + XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512=5636, + XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512=5637, + XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512=5638, + XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512=5639, + XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512=5640, + XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512=5641, + XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512=5642, + XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5643, + XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5644, + XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5645, + XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5646, + XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512=5647, + XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512=5648, + XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5649, + XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5650, + XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5651, + XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5652, + XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512=5653, + XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512=5654, + XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512=5655, + XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512=5656, + XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512=5657, + XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512=5658, + XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512=5659, + XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512=5660, + XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq=5661, + XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq=5662, + XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq=5663, + XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq=5664, + XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5665, + XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5666, + XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5667, + XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5668, + XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5669, + XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5670, + XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5671, + XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5672, + XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5673, + XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5674, + XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5675, + XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5676, + XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq=5677, + XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq=5678, + XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq=5679, + XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5680, + XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5681, + XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5682, + XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5683, + XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5684, + XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5685, + XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5686, + XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5687, + XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5688, + XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5689, + XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5690, + XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5691, + XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5692, + XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5693, + XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5694, + XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5695, + XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5696, + XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5697, + XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5698, + XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5699, + XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5700, + XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5701, + XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5702, + XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5703, + XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5704, + XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5705, + XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5706, + XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5707, + XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5708, + XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5709, + XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5710, + XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5711, + XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5712, + XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5713, + XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5714, + XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5715, + XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5716, + XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5717, + XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5718, + XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5719, + XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5720, + XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5721, + XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5722, + XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5723, + XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5724, + XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5725, + XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5726, + XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5727, + XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb=5728, + XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq=5729, + XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb=5730, + XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq=5731, + XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq=5732, + XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb=5733, + XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq=5734, + XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb=5735, + XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq=5736, + XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq=5737, + XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb=5738, + XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq=5739, + XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb=5740, + XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq=5741, + XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq=5742, + XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb=5743, + XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq=5744, + XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb=5745, + XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq=5746, + XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq=5747, + XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq=5748, + XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq=5749, + XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512=5750, + XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512=5751, + XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq=5752, + XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq=5753, + XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512=5754, + XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512=5755, + XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512=5756, + XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512=5757, + XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5758, + XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256=5759, + XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512=5760, + XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5761, + XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5762, + XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5763, + XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5764, + XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256=5765, + XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512=5766, + XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5767, + XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5768, + XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5769, + XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq=5770, + XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq=5771, + XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq=5772, + XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq=5773, + XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq=5774, + XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq=5775, + XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq=5776, + XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq=5777, + XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq=5778, + XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq=5779, + XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq=5780, + XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq=5781, + XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq=5782, + XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq=5783, + XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq=5784, + XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq=5785, + XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq=5786, + XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq=5787, + XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5788, + XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5789, + XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5790, + XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5791, + XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5792, + XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5793, + XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5794, + XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5795, + XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5796, + XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5797, + XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5798, + XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5799, + XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5800, + XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5801, + XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5802, + XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5803, + XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5804, + XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5805, + XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5806, + XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5807, + XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5808, + XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5809, + XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5810, + XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5811, + XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5812, + XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5813, + XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5814, + XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5815, + XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5816, + XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5817, + XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5818, + XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5819, + XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5820, + XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5821, + XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5822, + XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5823, + XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq=5824, + XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq=5825, + XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq=5826, + XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq=5827, + XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq=5828, + XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq=5829, + XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5830, + XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5831, + XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5832, + XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5833, + XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5834, + XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5835, + XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5836, + XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5837, + XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5838, + XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5839, + XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5840, + XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5841, + XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5842, + XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5843, + XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5844, + XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5845, + XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5846, + XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5847, + XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5848, + XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5849, + XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5850, + XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5851, + XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5852, + XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5853, + XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5854, + XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5855, + XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5856, + XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5857, + XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5858, + XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5859, + XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5860, + XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5861, + XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5862, + XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5863, + XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5864, + XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5865, + XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq=5866, + XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq=5867, + XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5868, + XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5869, + XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq=5870, + XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq=5871, + XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5872, + XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5873, + XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5874, + XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5875, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512=5876, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512=5877, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512=5878, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512=5879, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512=5880, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512=5881, + XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb=5882, + XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb=5883, + XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5884, + XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5885, + XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb=5886, + XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb=5887, + XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5888, + XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5889, + XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5890, + XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5891, + XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb=5892, + XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb=5893, + XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5894, + XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5895, + XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb=5896, + XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb=5897, + XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5898, + XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5899, + XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5900, + XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5901, + XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb=5902, + XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb=5903, + XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5904, + XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5905, + XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb=5906, + XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb=5907, + XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5908, + XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5909, + XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5910, + XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5911, + XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq=5912, + XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq=5913, + XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq=5914, + XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq=5915, + XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq=5916, + XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq=5917, + XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq=5918, + XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq=5919, + XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq=5920, + XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq=5921, + XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq=5922, + XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq=5923, + XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb=5924, + XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq=5925, + XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq=5926, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5927, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5928, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5929, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5930, + XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb=5931, + XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq=5932, + XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq=5933, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5934, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5935, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5936, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=5937, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5938, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5939, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5940, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=5941, + XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb=5942, + XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512=5943, + XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512=5944, + XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb=5945, + XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512=5946, + XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512=5947, + XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512=5948, + XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512=5949, + XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb=5950, + XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq=5951, + XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq=5952, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5953, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5954, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5955, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5956, + XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb=5957, + XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq=5958, + XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq=5959, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5960, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5961, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5962, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=5963, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5964, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5965, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5966, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=5967, + XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq=5968, + XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq=5969, + XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5970, + XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5971, + XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq=5972, + XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq=5973, + XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5974, + XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5975, + XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5976, + XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5977, + XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq=5978, + XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq=5979, + XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5980, + XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5981, + XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq=5982, + XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq=5983, + XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5984, + XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5985, + XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5986, + XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5987, + XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5988, + XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5989, + XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5990, + XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5991, + XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5992, + XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5993, + XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb=5994, + XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq=5995, + XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq=5996, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5997, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5998, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5999, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6000, + XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb=6001, + XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq=6002, + XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq=6003, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6004, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6005, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6006, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6007, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6008, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6009, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6010, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6011, + XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb=6012, + XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq=6013, + XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq=6014, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=6015, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=6016, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6017, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6018, + XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb=6019, + XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq=6020, + XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq=6021, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=6022, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=6023, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6024, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=6025, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=6026, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=6027, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6028, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=6029, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=6030, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=6031, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6032, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6033, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=6034, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=6035, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6036, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=6037, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=6038, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=6039, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6040, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=6041, + XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq=6042, + XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq=6043, + XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6044, + XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6045, + XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq=6046, + XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq=6047, + XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6048, + XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6049, + XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6050, + XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6051, + XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6052, + XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6053, + XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6054, + XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6055, + XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6056, + XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6057, + XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6058, + XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6059, + XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6060, + XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6061, + XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6062, + XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6063, + XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb=6064, + XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq=6065, + XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq=6066, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=6067, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=6068, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6069, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6070, + XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb=6071, + XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq=6072, + XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq=6073, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6074, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6075, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6076, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6077, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6078, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6079, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6080, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6081, + XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb=6082, + XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq=6083, + XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq=6084, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=6085, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=6086, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6087, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6088, + XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb=6089, + XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq=6090, + XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq=6091, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=6092, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=6093, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6094, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=6095, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=6096, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=6097, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6098, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=6099, + XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb=6100, + XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512=6101, + XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512=6102, + XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb=6103, + XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512=6104, + XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512=6105, + XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512=6106, + XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512=6107, + XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb=6108, + XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq=6109, + XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq=6110, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=6111, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=6112, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6113, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6114, + XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb=6115, + XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq=6116, + XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq=6117, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=6118, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=6119, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6120, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=6121, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=6122, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=6123, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6124, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=6125, + XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq=6126, + XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq=6127, + XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6128, + XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6129, + XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq=6130, + XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq=6131, + XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6132, + XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6133, + XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6134, + XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6135, + XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq=6136, + XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq=6137, + XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6138, + XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6139, + XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq=6140, + XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq=6141, + XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6142, + XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6143, + XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6144, + XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6145, + XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6146, + XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6147, + XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6148, + XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6149, + XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6150, + XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6151, + XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb=6152, + XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq=6153, + XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq=6154, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=6155, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=6156, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6157, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6158, + XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb=6159, + XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq=6160, + XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq=6161, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6162, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6163, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6164, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6165, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6166, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6167, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6168, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6169, + XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq=6170, + XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq=6171, + XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6172, + XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6173, + XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq=6174, + XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq=6175, + XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6176, + XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6177, + XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6178, + XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6179, + XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq=6180, + XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq=6181, + XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6182, + XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6183, + XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq=6184, + XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq=6185, + XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6186, + XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6187, + XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6188, + XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6189, + XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq=6190, + XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq=6191, + XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6192, + XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6193, + XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq=6194, + XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq=6195, + XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6196, + XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6197, + XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6198, + XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6199, + XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq=6200, + XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq=6201, + XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=6202, + XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=6203, + XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=6204, + XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=6205, + XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq=6206, + XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq=6207, + XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=6208, + XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=6209, + XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq=6210, + XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq=6211, + XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=6212, + XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=6213, + XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=6214, + XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=6215, + XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq=6216, + XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq=6217, + XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=6218, + XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=6219, + XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq=6220, + XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq=6221, + XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6222, + XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6223, + XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq=6224, + XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq=6225, + XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6226, + XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6227, + XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6228, + XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6229, + XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq=6230, + XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq=6231, + XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6232, + XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6233, + XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq=6234, + XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq=6235, + XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6236, + XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6237, + XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6238, + XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6239, + XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq=6240, + XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq=6241, + XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6242, + XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6243, + XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq=6244, + XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq=6245, + XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6246, + XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6247, + XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6248, + XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6249, + XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=6250, + XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=6251, + XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6252, + XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6253, + XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6254, + XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6255, + XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=6256, + XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=6257, + XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6258, + XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6259, + XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6260, + XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6261, + XED_IFORM_VPTEST_XMMdq_MEMdq=6262, + XED_IFORM_VPTEST_XMMdq_XMMdq=6263, + XED_IFORM_VPTEST_YMMqq_MEMqq=6264, + XED_IFORM_VPTEST_YMMqq_YMMqq=6265, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=6266, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=6267, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=6268, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=6269, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=6270, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=6271, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=6272, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=6273, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=6274, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=6275, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=6276, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=6277, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=6278, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=6279, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=6280, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=6281, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=6282, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=6283, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=6284, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=6285, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=6286, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=6287, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=6288, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=6289, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=6290, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=6291, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=6292, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=6293, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=6294, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=6295, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=6296, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=6297, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=6298, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=6299, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=6300, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=6301, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=6302, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=6303, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=6304, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=6305, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=6306, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=6307, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=6308, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=6309, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=6310, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=6311, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=6312, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=6313, + XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq=6314, + XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq=6315, + XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6316, + XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6317, + XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq=6318, + XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq=6319, + XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6320, + XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6321, + XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6322, + XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6323, + XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq=6324, + XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq=6325, + XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6326, + XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6327, + XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq=6328, + XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq=6329, + XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6330, + XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6331, + XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6332, + XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6333, + XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq=6334, + XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq=6335, + XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6336, + XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6337, + XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq=6338, + XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq=6339, + XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6340, + XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6341, + XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6342, + XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6343, + XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq=6344, + XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq=6345, + XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6346, + XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6347, + XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq=6348, + XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq=6349, + XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6350, + XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6351, + XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6352, + XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6353, + XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq=6354, + XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq=6355, + XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6356, + XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6357, + XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq=6358, + XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq=6359, + XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6360, + XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6361, + XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6362, + XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6363, + XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq=6364, + XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq=6365, + XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6366, + XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6367, + XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq=6368, + XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq=6369, + XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6370, + XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6371, + XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6372, + XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6373, + XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq=6374, + XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq=6375, + XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6376, + XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6377, + XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq=6378, + XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq=6379, + XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6380, + XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6381, + XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6382, + XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6383, + XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq=6384, + XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq=6385, + XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6386, + XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6387, + XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq=6388, + XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq=6389, + XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6390, + XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6391, + XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6392, + XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6393, + XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq=6394, + XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq=6395, + XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq=6396, + XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq=6397, + XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6398, + XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6399, + XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6400, + XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6401, + XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6402, + XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6403, + XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6404, + XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6405, + XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6406, + XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6407, + XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6408, + XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6409, + XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6410, + XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6411, + XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6412, + XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6413, + XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6414, + XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6415, + XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6416, + XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6417, + XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6418, + XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6419, + XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6420, + XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6421, + XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6422, + XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6423, + XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6424, + XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6425, + XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512=6426, + XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512=6427, + XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512=6428, + XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512=6429, + XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6430, + XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6431, + XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512=6432, + XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512=6433, + XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512=6434, + XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512=6435, + XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6436, + XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6437, + XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6438, + XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6439, + XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6440, + XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6441, + XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6442, + XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6443, + XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6444, + XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6445, + XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6446, + XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6447, + XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6448, + XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6449, + XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512=6450, + XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512=6451, + XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512=6452, + XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512=6453, + XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512=6454, + XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6455, + XED_IFORM_VRCPPS_XMMdq_MEMdq=6456, + XED_IFORM_VRCPPS_XMMdq_XMMdq=6457, + XED_IFORM_VRCPPS_YMMqq_MEMqq=6458, + XED_IFORM_VRCPPS_YMMqq_YMMqq=6459, + XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6460, + XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6461, + XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd=6462, + XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd=6463, + XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6464, + XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6465, + XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6466, + XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6467, + XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6468, + XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6469, + XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=6470, + XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=6471, + XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=6472, + XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=6473, + XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=6474, + XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=6475, + XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6476, + XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6477, + XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6478, + XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6479, + XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6480, + XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6481, + XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6482, + XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6483, + XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=6484, + XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=6485, + XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6486, + XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6487, + XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6488, + XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6489, + XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6490, + XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6491, + XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6492, + XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6493, + XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=6494, + XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=6495, + XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=6496, + XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=6497, + XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=6498, + XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=6499, + XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6500, + XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6501, + XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6502, + XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6503, + XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6504, + XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6505, + XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6506, + XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6507, + XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=6508, + XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=6509, + XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6510, + XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6511, + XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb=6512, + XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb=6513, + XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb=6514, + XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb=6515, + XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb=6516, + XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb=6517, + XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb=6518, + XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb=6519, + XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb=6520, + XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb=6521, + XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb=6522, + XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb=6523, + XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512=6524, + XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512=6525, + XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512=6526, + XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512=6527, + XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6528, + XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6529, + XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512=6530, + XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512=6531, + XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512=6532, + XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512=6533, + XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6534, + XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6535, + XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6536, + XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6537, + XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6538, + XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6539, + XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6540, + XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6541, + XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6542, + XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6543, + XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6544, + XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6545, + XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6546, + XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6547, + XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512=6548, + XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512=6549, + XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512=6550, + XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512=6551, + XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512=6552, + XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6553, + XED_IFORM_VRSQRTPS_XMMdq_MEMdq=6554, + XED_IFORM_VRSQRTPS_XMMdq_XMMdq=6555, + XED_IFORM_VRSQRTPS_YMMqq_MEMqq=6556, + XED_IFORM_VRSQRTPS_YMMqq_YMMqq=6557, + XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6558, + XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6559, + XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd=6560, + XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd=6561, + XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6562, + XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6563, + XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6564, + XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6565, + XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6566, + XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6567, + XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6568, + XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6569, + XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=6570, + XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=6571, + XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=6572, + XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=6573, + XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6574, + XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6575, + XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6576, + XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6577, + XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6578, + XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6579, + XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6580, + XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6581, + XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6582, + XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6583, + XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6584, + XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6585, + XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6586, + XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6587, + XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6588, + XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6589, + XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256=6590, + XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512=6591, + XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=6592, + XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=6593, + XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=6594, + XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=6595, + XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=6596, + XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=6597, + XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=6598, + XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=6599, + XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6600, + XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6601, + XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6602, + XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6603, + XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256=6604, + XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512=6605, + XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6606, + XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6607, + XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6608, + XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6609, + XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6610, + XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6611, + XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6612, + XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6613, + XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6614, + XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6615, + XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6616, + XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6617, + XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6618, + XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6619, + XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6620, + XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6621, + XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb=6622, + XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb=6623, + XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6624, + XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6625, + XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6626, + XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6627, + XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb=6628, + XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb=6629, + XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6630, + XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6631, + XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb=6632, + XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb=6633, + XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6634, + XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6635, + XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6636, + XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6637, + XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb=6638, + XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb=6639, + XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6640, + XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6641, + XED_IFORM_VSQRTPD_XMMdq_MEMdq=6642, + XED_IFORM_VSQRTPD_XMMdq_XMMdq=6643, + XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512=6644, + XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512=6645, + XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512=6646, + XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512=6647, + XED_IFORM_VSQRTPD_YMMqq_MEMqq=6648, + XED_IFORM_VSQRTPD_YMMqq_YMMqq=6649, + XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512=6650, + XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512=6651, + XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512=6652, + XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512=6653, + XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512=6654, + XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512=6655, + XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512=6656, + XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6657, + XED_IFORM_VSQRTPS_XMMdq_MEMdq=6658, + XED_IFORM_VSQRTPS_XMMdq_XMMdq=6659, + XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512=6660, + XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512=6661, + XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512=6662, + XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512=6663, + XED_IFORM_VSQRTPS_YMMqq_MEMqq=6664, + XED_IFORM_VSQRTPS_YMMqq_YMMqq=6665, + XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512=6666, + XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512=6667, + XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq=6668, + XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq=6669, + XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6670, + XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6671, + XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6672, + XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6673, + XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd=6674, + XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd=6675, + XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6676, + XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6677, + XED_IFORM_VSTMXCSR_MEMd=6678, + XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq=6679, + XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq=6680, + XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6681, + XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6682, + XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6683, + XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6684, + XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq=6685, + XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq=6686, + XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6687, + XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6688, + XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6689, + XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6690, + XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=6691, + XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=6692, + XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=6693, + XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=6694, + XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq=6695, + XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq=6696, + XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6697, + XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6698, + XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6699, + XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6700, + XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq=6701, + XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq=6702, + XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6703, + XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6704, + XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq=6705, + XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq=6706, + XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6707, + XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6708, + XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6709, + XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6710, + XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd=6711, + XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd=6712, + XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6713, + XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6714, + XED_IFORM_VTESTPD_XMMdq_MEMdq=6715, + XED_IFORM_VTESTPD_XMMdq_XMMdq=6716, + XED_IFORM_VTESTPD_YMMqq_MEMqq=6717, + XED_IFORM_VTESTPD_YMMqq_YMMqq=6718, + XED_IFORM_VTESTPS_XMMdq_MEMdq=6719, + XED_IFORM_VTESTPS_XMMdq_XMMdq=6720, + XED_IFORM_VTESTPS_YMMqq_MEMqq=6721, + XED_IFORM_VTESTPS_YMMqq_YMMqq=6722, + XED_IFORM_VUCOMISD_XMMdq_MEMq=6723, + XED_IFORM_VUCOMISD_XMMdq_XMMq=6724, + XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512=6725, + XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512=6726, + XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512=6727, + XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512=6728, + XED_IFORM_VUCOMISS_XMMdq_MEMd=6729, + XED_IFORM_VUCOMISS_XMMdq_XMMd=6730, + XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512=6731, + XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512=6732, + XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq=6733, + XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq=6734, + XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6735, + XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6736, + XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6737, + XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6738, + XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq=6739, + XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq=6740, + XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6741, + XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6742, + XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq=6743, + XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq=6744, + XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6745, + XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6746, + XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6747, + XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6748, + XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq=6749, + XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq=6750, + XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6751, + XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6752, + XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq=6753, + XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq=6754, + XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6755, + XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6756, + XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6757, + XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6758, + XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq=6759, + XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq=6760, + XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6761, + XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6762, + XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq=6763, + XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq=6764, + XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6765, + XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6766, + XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6767, + XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6768, + XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq=6769, + XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq=6770, + XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6771, + XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6772, + XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq=6773, + XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq=6774, + XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6775, + XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6776, + XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq=6777, + XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq=6778, + XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6779, + XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6780, + XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6781, + XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6782, + XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq=6783, + XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq=6784, + XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6785, + XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6786, + XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq=6787, + XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq=6788, + XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6789, + XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6790, + XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6791, + XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6792, + XED_IFORM_VZEROALL=6793, + XED_IFORM_VZEROUPPER=6794, + XED_IFORM_WBINVD=6795, + XED_IFORM_WBNOINVD=6796, + XED_IFORM_WRFSBASE_GPRy=6797, + XED_IFORM_WRGSBASE_GPRy=6798, + XED_IFORM_WRMSR=6799, + XED_IFORM_WRPKRU=6800, + XED_IFORM_WRSSD_MEMu32_GPR32u32=6801, + XED_IFORM_WRSSQ_MEMu64_GPR64u64=6802, + XED_IFORM_WRUSSD_MEMu32_GPR32u32=6803, + XED_IFORM_WRUSSQ_MEMu64_GPR64u64=6804, + XED_IFORM_XABORT_IMMb=6805, + XED_IFORM_XADD_GPR8_GPR8=6806, + XED_IFORM_XADD_GPRv_GPRv=6807, + XED_IFORM_XADD_MEMb_GPR8=6808, + XED_IFORM_XADD_MEMv_GPRv=6809, + XED_IFORM_XADD_LOCK_MEMb_GPR8=6810, + XED_IFORM_XADD_LOCK_MEMv_GPRv=6811, + XED_IFORM_XBEGIN_RELBRz=6812, + XED_IFORM_XCHG_GPR8_GPR8=6813, + XED_IFORM_XCHG_GPRv_GPRv=6814, + XED_IFORM_XCHG_GPRv_OrAX=6815, + XED_IFORM_XCHG_MEMb_GPR8=6816, + XED_IFORM_XCHG_MEMv_GPRv=6817, + XED_IFORM_XEND=6818, + XED_IFORM_XGETBV=6819, + XED_IFORM_XLAT=6820, + XED_IFORM_XOR_AL_IMMb=6821, + XED_IFORM_XOR_GPR8_GPR8_30=6822, + XED_IFORM_XOR_GPR8_GPR8_32=6823, + XED_IFORM_XOR_GPR8_IMMb_80r6=6824, + XED_IFORM_XOR_GPR8_IMMb_82r6=6825, + XED_IFORM_XOR_GPR8_MEMb=6826, + XED_IFORM_XOR_GPRv_GPRv_31=6827, + XED_IFORM_XOR_GPRv_GPRv_33=6828, + XED_IFORM_XOR_GPRv_IMMb=6829, + XED_IFORM_XOR_GPRv_IMMz=6830, + XED_IFORM_XOR_GPRv_MEMv=6831, + XED_IFORM_XOR_MEMb_GPR8=6832, + XED_IFORM_XOR_MEMb_IMMb_80r6=6833, + XED_IFORM_XOR_MEMb_IMMb_82r6=6834, + XED_IFORM_XOR_MEMv_GPRv=6835, + XED_IFORM_XOR_MEMv_IMMb=6836, + XED_IFORM_XOR_MEMv_IMMz=6837, + XED_IFORM_XOR_OrAX_IMMz=6838, + XED_IFORM_XORPD_XMMxuq_MEMxuq=6839, + XED_IFORM_XORPD_XMMxuq_XMMxuq=6840, + XED_IFORM_XORPS_XMMxud_MEMxud=6841, + XED_IFORM_XORPS_XMMxud_XMMxud=6842, + XED_IFORM_XOR_LOCK_MEMb_GPR8=6843, + XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6=6844, + XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6=6845, + XED_IFORM_XOR_LOCK_MEMv_GPRv=6846, + XED_IFORM_XOR_LOCK_MEMv_IMMb=6847, + XED_IFORM_XOR_LOCK_MEMv_IMMz=6848, + XED_IFORM_XRESLDTRK=6849, + XED_IFORM_XRSTOR_MEMmxsave=6850, + XED_IFORM_XRSTOR64_MEMmxsave=6851, + XED_IFORM_XRSTORS_MEMmxsave=6852, + XED_IFORM_XRSTORS64_MEMmxsave=6853, + XED_IFORM_XSAVE_MEMmxsave=6854, + XED_IFORM_XSAVE64_MEMmxsave=6855, + XED_IFORM_XSAVEC_MEMmxsave=6856, + XED_IFORM_XSAVEC64_MEMmxsave=6857, + XED_IFORM_XSAVEOPT_MEMmxsave=6858, + XED_IFORM_XSAVEOPT64_MEMmxsave=6859, + XED_IFORM_XSAVES_MEMmxsave=6860, + XED_IFORM_XSAVES64_MEMmxsave=6861, + XED_IFORM_XSETBV=6862, + XED_IFORM_XSTORE=6863, + XED_IFORM_XSUSLDTRK=6864, + XED_IFORM_XTEST=6865, + XED_IFORM_LAST +} xed_iform_enum_t; + +/// This converts strings to #xed_iform_enum_t types. +/// @param s A C-string. +/// @return #xed_iform_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_iform_enum_t str2xed_iform_enum_t(const char* s); +/// This converts strings to #xed_iform_enum_t types. +/// @param p An enumeration element of type xed_iform_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_iform_enum_t2str(const xed_iform_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_iform_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_iform_enum_t xed_iform_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-map.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-map.h new file mode 100644 index 0000000..406730e --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iform-map.h @@ -0,0 +1,117 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-iform-map.h +/// + +#if !defined(XED_IFORM_MAP_H) +# define XED_IFORM_MAP_H + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-iform-enum.h" /* generated */ +#include "xed-iclass-enum.h" /* generated */ +#include "xed-category-enum.h" /* generated */ +#include "xed-extension-enum.h" /* generated */ +#include "xed-isa-set-enum.h" /* generated */ + +/// @ingroup IFORM +/// Statically available information about iforms. +/// Values are returned by #xed_iform_map(). +typedef struct xed_iform_info_s { + xed_uint32_t iclass :16; // xed_iclass_enum_t + xed_uint32_t category :8; //xed_category_enum_t + xed_uint32_t extension :8; //xed_extension_enum_t + + xed_uint32_t isa_set :16; //xed_isa_set_enum_t + /* if nonzero, index in to the disassembly string table */ + xed_uint32_t string_table_idx:16; +} xed_iform_info_t; + + +/// @ingroup IFORM +/// Map the #xed_iform_enum_t to a pointer to a #xed_iform_info_t which +/// indicates the #xed_iclass_enum_t, the #xed_category_enum_t and the +/// #xed_extension_enum_t for the iform. Returns 0 if the iform is not a +/// valid iform. +XED_DLL_EXPORT +const xed_iform_info_t* xed_iform_map(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return the maximum number of iforms for a particular iclass. This +/// function returns valid data as soon as global data is +/// initialized. (This function does not require a decoded instruction as +/// input). +XED_DLL_EXPORT +xed_uint32_t xed_iform_max_per_iclass(xed_iclass_enum_t iclass); + +/// @ingroup IFORM +/// Return the first of the iforms for a particular iclass. This function +/// returns valid data as soon as global data is initialized. (This +/// function does not require a decoded instruction as input). +XED_DLL_EXPORT +xed_uint32_t xed_iform_first_per_iclass(xed_iclass_enum_t iclass); + +/// @ingroup IFORM +/// Return the iclass for a given iform. This +/// function returns valid data as soon as global data is initialized. (This +/// function does not require a decoded instruction as input). +static +XED_INLINE xed_iclass_enum_t xed_iform_to_iclass(xed_iform_enum_t iform) { + const xed_iform_info_t* ii = xed_iform_map(iform); + if (ii) + return (xed_iclass_enum_t) ii->iclass; + return XED_ICLASS_INVALID; +} + +/// @ingroup IFORM +/// Return the category for a given iform. This +/// function returns valid data as soon as global data is initialized. (This +/// function does not require a decoded instruction as input). +XED_DLL_EXPORT +xed_category_enum_t xed_iform_to_category(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return the extension for a given iform. This function returns valid +/// data as soon as global data is initialized. (This function does not +/// require a decoded instruction as input). +XED_DLL_EXPORT +xed_extension_enum_t xed_iform_to_extension(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return the isa_set for a given iform. This function returns valid data +/// as soon as global data is initialized. (This function does not require +/// a decoded instruction as input). +XED_DLL_EXPORT +xed_isa_set_enum_t xed_iform_to_isa_set(xed_iform_enum_t iform); + +/// @ingroup IFORM +/// Return a pointer to a character string of the iclass. This +/// translates the internal disambiguated names to the more ambiguous +/// names that people like to see. This returns the ATT SYSV-syntax name. +XED_DLL_EXPORT +char const* xed_iform_to_iclass_string_att(xed_iform_enum_t iform); + + +/// @ingroup IFORM +/// Return a pointer to a character string of the iclass. This +/// translates the internal disambiguated names to the more ambiguous +/// names that people like to see. This returns the Intel-syntax name. +XED_DLL_EXPORT +char const* xed_iform_to_iclass_string_intel(xed_iform_enum_t iform); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-iformfl-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iformfl-enum.h new file mode 100644 index 0000000..0eb4992 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-iformfl-enum.h @@ -0,0 +1,6976 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-iformfl-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_IFORMFL_ENUM_H) +# define XED_IFORMFL_ENUM_H +#include "xed-common-hdrs.h" +#include "xed-iclass-enum.h" +#define XED_IFORMFL_AAA_FIRST_DEFINED 1 +#define XED_IFORMFL_AAA_LAST_DEFINED 1 +#define XED_IFORMFL_AAD_FIRST_DEFINED 1 +#define XED_IFORMFL_AAD_LAST_DEFINED 1 +#define XED_IFORMFL_AAM_FIRST_DEFINED 1 +#define XED_IFORMFL_AAM_LAST_DEFINED 1 +#define XED_IFORMFL_AAS_FIRST_DEFINED 1 +#define XED_IFORMFL_AAS_LAST_DEFINED 1 +#define XED_IFORMFL_ADC_FIRST_DEFINED 1 +#define XED_IFORMFL_ADC_LAST_DEFINED 1 +#define XED_IFORMFL_ADCX_FIRST_DEFINED 1 +#define XED_IFORMFL_ADCX_LAST_DEFINED 1 +#define XED_IFORMFL_ADC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_ADC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_ADD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_ADD_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_ADD_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_ADOX_FIRST_DEFINED 1 +#define XED_IFORMFL_ADOX_LAST_DEFINED 1 +#define XED_IFORMFL_AESDEC_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDEC_LAST_DEFINED 1 +#define XED_IFORMFL_AESDEC128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDEC128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESDEC256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDEC256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESDECLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDECLAST_LAST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENC_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENC_LAST_DEFINED 1 +#define XED_IFORMFL_AESENC128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENC128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENC256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENC256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENCLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENCLAST_LAST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESIMC_FIRST_DEFINED 1 +#define XED_IFORMFL_AESIMC_LAST_DEFINED 1 +#define XED_IFORMFL_AESKEYGENASSIST_FIRST_DEFINED 1 +#define XED_IFORMFL_AESKEYGENASSIST_LAST_DEFINED 1 +#define XED_IFORMFL_AND_FIRST_DEFINED 1 +#define XED_IFORMFL_AND_LAST_DEFINED 1 +#define XED_IFORMFL_ANDN_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDN_LAST_DEFINED 1 +#define XED_IFORMFL_ANDNPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDNPD_LAST_DEFINED 1 +#define XED_IFORMFL_ANDNPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDNPS_LAST_DEFINED 1 +#define XED_IFORMFL_ANDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDPD_LAST_DEFINED 1 +#define XED_IFORMFL_ANDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDPS_LAST_DEFINED 1 +#define XED_IFORMFL_AND_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_AND_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_ARPL_FIRST_DEFINED 1 +#define XED_IFORMFL_ARPL_LAST_DEFINED 1 +#define XED_IFORMFL_BEXTR_FIRST_DEFINED 1 +#define XED_IFORMFL_BEXTR_LAST_DEFINED 1 +#define XED_IFORMFL_BEXTR_XOP_FIRST_DEFINED 1 +#define XED_IFORMFL_BEXTR_XOP_LAST_DEFINED 1 +#define XED_IFORMFL_BLCFILL_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCFILL_LAST_DEFINED 1 +#define XED_IFORMFL_BLCI_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCI_LAST_DEFINED 1 +#define XED_IFORMFL_BLCIC_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCIC_LAST_DEFINED 1 +#define XED_IFORMFL_BLCMSK_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCMSK_LAST_DEFINED 1 +#define XED_IFORMFL_BLCS_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCS_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDPD_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDPS_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDVPD_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDVPS_LAST_DEFINED 1 +#define XED_IFORMFL_BLSFILL_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSFILL_LAST_DEFINED 1 +#define XED_IFORMFL_BLSI_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSI_LAST_DEFINED 1 +#define XED_IFORMFL_BLSIC_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSIC_LAST_DEFINED 1 +#define XED_IFORMFL_BLSMSK_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSMSK_LAST_DEFINED 1 +#define XED_IFORMFL_BLSR_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSR_LAST_DEFINED 1 +#define XED_IFORMFL_BNDCL_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDCL_LAST_DEFINED 1 +#define XED_IFORMFL_BNDCN_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDCN_LAST_DEFINED 1 +#define XED_IFORMFL_BNDCU_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDCU_LAST_DEFINED 1 +#define XED_IFORMFL_BNDLDX_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDLDX_LAST_DEFINED 1 +#define XED_IFORMFL_BNDMK_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDMK_LAST_DEFINED 1 +#define XED_IFORMFL_BNDMOV_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDMOV_LAST_DEFINED 1 +#define XED_IFORMFL_BNDSTX_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDSTX_LAST_DEFINED 1 +#define XED_IFORMFL_BOUND_FIRST_DEFINED 1 +#define XED_IFORMFL_BOUND_LAST_DEFINED 1 +#define XED_IFORMFL_BSF_FIRST_DEFINED 1 +#define XED_IFORMFL_BSF_LAST_DEFINED 1 +#define XED_IFORMFL_BSR_FIRST_DEFINED 1 +#define XED_IFORMFL_BSR_LAST_DEFINED 1 +#define XED_IFORMFL_BSWAP_FIRST_DEFINED 1 +#define XED_IFORMFL_BSWAP_LAST_DEFINED 1 +#define XED_IFORMFL_BT_FIRST_DEFINED 1 +#define XED_IFORMFL_BT_LAST_DEFINED 1 +#define XED_IFORMFL_BTC_FIRST_DEFINED 1 +#define XED_IFORMFL_BTC_LAST_DEFINED 1 +#define XED_IFORMFL_BTC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_BTC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_BTR_FIRST_DEFINED 1 +#define XED_IFORMFL_BTR_LAST_DEFINED 1 +#define XED_IFORMFL_BTR_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_BTR_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_BTS_FIRST_DEFINED 1 +#define XED_IFORMFL_BTS_LAST_DEFINED 1 +#define XED_IFORMFL_BTS_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_BTS_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_BZHI_FIRST_DEFINED 1 +#define XED_IFORMFL_BZHI_LAST_DEFINED 1 +#define XED_IFORMFL_CALL_FAR_FIRST_DEFINED 1 +#define XED_IFORMFL_CALL_FAR_LAST_DEFINED 1 +#define XED_IFORMFL_CALL_NEAR_FIRST_DEFINED 1 +#define XED_IFORMFL_CALL_NEAR_LAST_DEFINED 1 +#define XED_IFORMFL_CBW_FIRST_DEFINED 1 +#define XED_IFORMFL_CBW_LAST_DEFINED 1 +#define XED_IFORMFL_CDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CDQ_LAST_DEFINED 1 +#define XED_IFORMFL_CDQE_FIRST_DEFINED 1 +#define XED_IFORMFL_CDQE_LAST_DEFINED 1 +#define XED_IFORMFL_CLAC_FIRST_DEFINED 1 +#define XED_IFORMFL_CLAC_LAST_DEFINED 1 +#define XED_IFORMFL_CLC_FIRST_DEFINED 1 +#define XED_IFORMFL_CLC_LAST_DEFINED 1 +#define XED_IFORMFL_CLD_FIRST_DEFINED 1 +#define XED_IFORMFL_CLD_LAST_DEFINED 1 +#define XED_IFORMFL_CLDEMOTE_FIRST_DEFINED 1 +#define XED_IFORMFL_CLDEMOTE_LAST_DEFINED 1 +#define XED_IFORMFL_CLFLUSH_FIRST_DEFINED 1 +#define XED_IFORMFL_CLFLUSH_LAST_DEFINED 1 +#define XED_IFORMFL_CLFLUSHOPT_FIRST_DEFINED 1 +#define XED_IFORMFL_CLFLUSHOPT_LAST_DEFINED 1 +#define XED_IFORMFL_CLGI_FIRST_DEFINED 1 +#define XED_IFORMFL_CLGI_LAST_DEFINED 1 +#define XED_IFORMFL_CLI_FIRST_DEFINED 1 +#define XED_IFORMFL_CLI_LAST_DEFINED 1 +#define XED_IFORMFL_CLRSSBSY_FIRST_DEFINED 1 +#define XED_IFORMFL_CLRSSBSY_LAST_DEFINED 1 +#define XED_IFORMFL_CLTS_FIRST_DEFINED 1 +#define XED_IFORMFL_CLTS_LAST_DEFINED 1 +#define XED_IFORMFL_CLUI_FIRST_DEFINED 1 +#define XED_IFORMFL_CLUI_LAST_DEFINED 1 +#define XED_IFORMFL_CLWB_FIRST_DEFINED 1 +#define XED_IFORMFL_CLWB_LAST_DEFINED 1 +#define XED_IFORMFL_CLZERO_FIRST_DEFINED 1 +#define XED_IFORMFL_CLZERO_LAST_DEFINED 1 +#define XED_IFORMFL_CMC_FIRST_DEFINED 1 +#define XED_IFORMFL_CMC_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVB_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVB_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVBE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVBE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVL_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVL_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVLE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVLE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNB_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNB_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNBE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNL_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNL_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNLE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNLE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNO_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNO_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNP_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNP_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNS_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNZ_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNZ_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVO_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVO_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVP_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVP_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVS_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVZ_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVZ_LAST_DEFINED 1 +#define XED_IFORMFL_CMP_FIRST_DEFINED 1 +#define XED_IFORMFL_CMP_LAST_DEFINED 1 +#define XED_IFORMFL_CMPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPPD_LAST_DEFINED 1 +#define XED_IFORMFL_CMPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPPS_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSB_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSB_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSD_XMM_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSD_XMM_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSQ_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSS_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSW_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSW_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_COMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_COMISD_LAST_DEFINED 1 +#define XED_IFORMFL_COMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_COMISS_LAST_DEFINED 1 +#define XED_IFORMFL_CPUID_FIRST_DEFINED 1 +#define XED_IFORMFL_CPUID_LAST_DEFINED 1 +#define XED_IFORMFL_CQO_FIRST_DEFINED 1 +#define XED_IFORMFL_CQO_LAST_DEFINED 1 +#define XED_IFORMFL_CRC32_FIRST_DEFINED 1 +#define XED_IFORMFL_CRC32_LAST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CWD_FIRST_DEFINED 1 +#define XED_IFORMFL_CWD_LAST_DEFINED 1 +#define XED_IFORMFL_CWDE_FIRST_DEFINED 1 +#define XED_IFORMFL_CWDE_LAST_DEFINED 1 +#define XED_IFORMFL_DAA_FIRST_DEFINED 1 +#define XED_IFORMFL_DAA_LAST_DEFINED 1 +#define XED_IFORMFL_DAS_FIRST_DEFINED 1 +#define XED_IFORMFL_DAS_LAST_DEFINED 1 +#define XED_IFORMFL_DEC_FIRST_DEFINED 1 +#define XED_IFORMFL_DEC_LAST_DEFINED 1 +#define XED_IFORMFL_DEC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_DEC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_DIV_FIRST_DEFINED 1 +#define XED_IFORMFL_DIV_LAST_DEFINED 1 +#define XED_IFORMFL_DIVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVPD_LAST_DEFINED 1 +#define XED_IFORMFL_DIVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVPS_LAST_DEFINED 1 +#define XED_IFORMFL_DIVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVSD_LAST_DEFINED 1 +#define XED_IFORMFL_DIVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVSS_LAST_DEFINED 1 +#define XED_IFORMFL_DPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_DPPD_LAST_DEFINED 1 +#define XED_IFORMFL_DPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_DPPS_LAST_DEFINED 1 +#define XED_IFORMFL_EMMS_FIRST_DEFINED 1 +#define XED_IFORMFL_EMMS_LAST_DEFINED 1 +#define XED_IFORMFL_ENCLS_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCLS_LAST_DEFINED 1 +#define XED_IFORMFL_ENCLU_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCLU_LAST_DEFINED 1 +#define XED_IFORMFL_ENCLV_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCLV_LAST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY128_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY128_LAST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY256_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY256_LAST_DEFINED 1 +#define XED_IFORMFL_ENDBR32_FIRST_DEFINED 1 +#define XED_IFORMFL_ENDBR32_LAST_DEFINED 1 +#define XED_IFORMFL_ENDBR64_FIRST_DEFINED 1 +#define XED_IFORMFL_ENDBR64_LAST_DEFINED 1 +#define XED_IFORMFL_ENQCMD_FIRST_DEFINED 1 +#define XED_IFORMFL_ENQCMD_LAST_DEFINED 1 +#define XED_IFORMFL_ENQCMDS_FIRST_DEFINED 1 +#define XED_IFORMFL_ENQCMDS_LAST_DEFINED 1 +#define XED_IFORMFL_ENTER_FIRST_DEFINED 1 +#define XED_IFORMFL_ENTER_LAST_DEFINED 1 +#define XED_IFORMFL_EXTRACTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_EXTRACTPS_LAST_DEFINED 1 +#define XED_IFORMFL_EXTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_EXTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_F2XM1_FIRST_DEFINED 1 +#define XED_IFORMFL_F2XM1_LAST_DEFINED 1 +#define XED_IFORMFL_FABS_FIRST_DEFINED 1 +#define XED_IFORMFL_FABS_LAST_DEFINED 1 +#define XED_IFORMFL_FADD_FIRST_DEFINED 1 +#define XED_IFORMFL_FADD_LAST_DEFINED 1 +#define XED_IFORMFL_FADDP_FIRST_DEFINED 1 +#define XED_IFORMFL_FADDP_LAST_DEFINED 1 +#define XED_IFORMFL_FBLD_FIRST_DEFINED 1 +#define XED_IFORMFL_FBLD_LAST_DEFINED 1 +#define XED_IFORMFL_FBSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FBSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FCHS_FIRST_DEFINED 1 +#define XED_IFORMFL_FCHS_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVB_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVB_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVBE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVBE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNB_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNB_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNBE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNU_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNU_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVU_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVU_LAST_DEFINED 1 +#define XED_IFORMFL_FCOM_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOM_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMI_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMI_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMIP_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMIP_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMP_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMP_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMPP_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMPP_LAST_DEFINED 1 +#define XED_IFORMFL_FCOS_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOS_LAST_DEFINED 1 +#define XED_IFORMFL_FDECSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDECSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FDISI8087_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDISI8087_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_FDIV_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIV_LAST_DEFINED 1 +#define XED_IFORMFL_FDIVP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIVP_LAST_DEFINED 1 +#define XED_IFORMFL_FDIVR_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIVR_LAST_DEFINED 1 +#define XED_IFORMFL_FDIVRP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIVRP_LAST_DEFINED 1 +#define XED_IFORMFL_FEMMS_FIRST_DEFINED 1 +#define XED_IFORMFL_FEMMS_LAST_DEFINED 1 +#define XED_IFORMFL_FENI8087_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FENI8087_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_FFREE_FIRST_DEFINED 1 +#define XED_IFORMFL_FFREE_LAST_DEFINED 1 +#define XED_IFORMFL_FFREEP_FIRST_DEFINED 1 +#define XED_IFORMFL_FFREEP_LAST_DEFINED 1 +#define XED_IFORMFL_FIADD_FIRST_DEFINED 1 +#define XED_IFORMFL_FIADD_LAST_DEFINED 1 +#define XED_IFORMFL_FICOM_FIRST_DEFINED 1 +#define XED_IFORMFL_FICOM_LAST_DEFINED 1 +#define XED_IFORMFL_FICOMP_FIRST_DEFINED 1 +#define XED_IFORMFL_FICOMP_LAST_DEFINED 1 +#define XED_IFORMFL_FIDIV_FIRST_DEFINED 1 +#define XED_IFORMFL_FIDIV_LAST_DEFINED 1 +#define XED_IFORMFL_FIDIVR_FIRST_DEFINED 1 +#define XED_IFORMFL_FIDIVR_LAST_DEFINED 1 +#define XED_IFORMFL_FILD_FIRST_DEFINED 1 +#define XED_IFORMFL_FILD_LAST_DEFINED 1 +#define XED_IFORMFL_FIMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_FIMUL_LAST_DEFINED 1 +#define XED_IFORMFL_FINCSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FINCSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FIST_FIRST_DEFINED 1 +#define XED_IFORMFL_FIST_LAST_DEFINED 1 +#define XED_IFORMFL_FISTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FISTP_LAST_DEFINED 1 +#define XED_IFORMFL_FISTTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FISTTP_LAST_DEFINED 1 +#define XED_IFORMFL_FISUB_FIRST_DEFINED 1 +#define XED_IFORMFL_FISUB_LAST_DEFINED 1 +#define XED_IFORMFL_FISUBR_FIRST_DEFINED 1 +#define XED_IFORMFL_FISUBR_LAST_DEFINED 1 +#define XED_IFORMFL_FLD_FIRST_DEFINED 1 +#define XED_IFORMFL_FLD_LAST_DEFINED 1 +#define XED_IFORMFL_FLD1_FIRST_DEFINED 1 +#define XED_IFORMFL_FLD1_LAST_DEFINED 1 +#define XED_IFORMFL_FLDCW_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDCW_LAST_DEFINED 1 +#define XED_IFORMFL_FLDENV_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDENV_LAST_DEFINED 1 +#define XED_IFORMFL_FLDL2E_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDL2E_LAST_DEFINED 1 +#define XED_IFORMFL_FLDL2T_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDL2T_LAST_DEFINED 1 +#define XED_IFORMFL_FLDLG2_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDLG2_LAST_DEFINED 1 +#define XED_IFORMFL_FLDLN2_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDLN2_LAST_DEFINED 1 +#define XED_IFORMFL_FLDPI_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDPI_LAST_DEFINED 1 +#define XED_IFORMFL_FLDZ_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDZ_LAST_DEFINED 1 +#define XED_IFORMFL_FMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_FMUL_LAST_DEFINED 1 +#define XED_IFORMFL_FMULP_FIRST_DEFINED 1 +#define XED_IFORMFL_FMULP_LAST_DEFINED 1 +#define XED_IFORMFL_FNCLEX_FIRST_DEFINED 1 +#define XED_IFORMFL_FNCLEX_LAST_DEFINED 1 +#define XED_IFORMFL_FNINIT_FIRST_DEFINED 1 +#define XED_IFORMFL_FNINIT_LAST_DEFINED 1 +#define XED_IFORMFL_FNOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FNOP_LAST_DEFINED 1 +#define XED_IFORMFL_FNSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_FNSTCW_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSTCW_LAST_DEFINED 1 +#define XED_IFORMFL_FNSTENV_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSTENV_LAST_DEFINED 1 +#define XED_IFORMFL_FNSTSW_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSTSW_LAST_DEFINED 1 +#define XED_IFORMFL_FPATAN_FIRST_DEFINED 1 +#define XED_IFORMFL_FPATAN_LAST_DEFINED 1 +#define XED_IFORMFL_FPREM_FIRST_DEFINED 1 +#define XED_IFORMFL_FPREM_LAST_DEFINED 1 +#define XED_IFORMFL_FPREM1_FIRST_DEFINED 1 +#define XED_IFORMFL_FPREM1_LAST_DEFINED 1 +#define XED_IFORMFL_FPTAN_FIRST_DEFINED 1 +#define XED_IFORMFL_FPTAN_LAST_DEFINED 1 +#define XED_IFORMFL_FRNDINT_FIRST_DEFINED 1 +#define XED_IFORMFL_FRNDINT_LAST_DEFINED 1 +#define XED_IFORMFL_FRSTOR_FIRST_DEFINED 1 +#define XED_IFORMFL_FRSTOR_LAST_DEFINED 1 +#define XED_IFORMFL_FSCALE_FIRST_DEFINED 1 +#define XED_IFORMFL_FSCALE_LAST_DEFINED 1 +#define XED_IFORMFL_FSETPM287_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSETPM287_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_FSIN_FIRST_DEFINED 1 +#define XED_IFORMFL_FSIN_LAST_DEFINED 1 +#define XED_IFORMFL_FSINCOS_FIRST_DEFINED 1 +#define XED_IFORMFL_FSINCOS_LAST_DEFINED 1 +#define XED_IFORMFL_FSQRT_FIRST_DEFINED 1 +#define XED_IFORMFL_FSQRT_LAST_DEFINED 1 +#define XED_IFORMFL_FST_FIRST_DEFINED 1 +#define XED_IFORMFL_FST_LAST_DEFINED 1 +#define XED_IFORMFL_FSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FSTPNCE_FIRST_DEFINED 1 +#define XED_IFORMFL_FSTPNCE_LAST_DEFINED 1 +#define XED_IFORMFL_FSUB_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUB_LAST_DEFINED 1 +#define XED_IFORMFL_FSUBP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUBP_LAST_DEFINED 1 +#define XED_IFORMFL_FSUBR_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUBR_LAST_DEFINED 1 +#define XED_IFORMFL_FSUBRP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUBRP_LAST_DEFINED 1 +#define XED_IFORMFL_FTST_FIRST_DEFINED 1 +#define XED_IFORMFL_FTST_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOM_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOM_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMI_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMI_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMIP_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMIP_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMP_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMP_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMPP_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMPP_LAST_DEFINED 1 +#define XED_IFORMFL_FWAIT_FIRST_DEFINED 1 +#define XED_IFORMFL_FWAIT_LAST_DEFINED 1 +#define XED_IFORMFL_FXAM_FIRST_DEFINED 1 +#define XED_IFORMFL_FXAM_LAST_DEFINED 1 +#define XED_IFORMFL_FXCH_FIRST_DEFINED 1 +#define XED_IFORMFL_FXCH_LAST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR_FIRST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR_LAST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR64_FIRST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR64_LAST_DEFINED 1 +#define XED_IFORMFL_FXSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_FXSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_FXSAVE64_FIRST_DEFINED 1 +#define XED_IFORMFL_FXSAVE64_LAST_DEFINED 1 +#define XED_IFORMFL_FXTRACT_FIRST_DEFINED 1 +#define XED_IFORMFL_FXTRACT_LAST_DEFINED 1 +#define XED_IFORMFL_FYL2X_FIRST_DEFINED 1 +#define XED_IFORMFL_FYL2X_LAST_DEFINED 1 +#define XED_IFORMFL_FYL2XP1_FIRST_DEFINED 1 +#define XED_IFORMFL_FYL2XP1_LAST_DEFINED 1 +#define XED_IFORMFL_GETSEC_FIRST_DEFINED 1 +#define XED_IFORMFL_GETSEC_LAST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEINVQB_FIRST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEINVQB_LAST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEQB_LAST_DEFINED 1 +#define XED_IFORMFL_GF2P8MULB_FIRST_DEFINED 1 +#define XED_IFORMFL_GF2P8MULB_LAST_DEFINED 1 +#define XED_IFORMFL_HADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_HADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_HADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_HADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_HLT_FIRST_DEFINED 1 +#define XED_IFORMFL_HLT_LAST_DEFINED 1 +#define XED_IFORMFL_HRESET_FIRST_DEFINED 1 +#define XED_IFORMFL_HRESET_LAST_DEFINED 1 +#define XED_IFORMFL_HSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_HSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_HSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_HSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_IDIV_FIRST_DEFINED 1 +#define XED_IFORMFL_IDIV_LAST_DEFINED 1 +#define XED_IFORMFL_IMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_IMUL_LAST_DEFINED 1 +#define XED_IFORMFL_IN_FIRST_DEFINED 1 +#define XED_IFORMFL_IN_LAST_DEFINED 1 +#define XED_IFORMFL_INC_FIRST_DEFINED 1 +#define XED_IFORMFL_INC_LAST_DEFINED 1 +#define XED_IFORMFL_INCSSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_INCSSPD_LAST_DEFINED 1 +#define XED_IFORMFL_INCSSPQ_FIRST_DEFINED 1 +#define XED_IFORMFL_INCSSPQ_LAST_DEFINED 1 +#define XED_IFORMFL_INC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_INC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_INSB_FIRST_DEFINED 1 +#define XED_IFORMFL_INSB_LAST_DEFINED 1 +#define XED_IFORMFL_INSD_FIRST_DEFINED 1 +#define XED_IFORMFL_INSD_LAST_DEFINED 1 +#define XED_IFORMFL_INSERTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_INSERTPS_LAST_DEFINED 1 +#define XED_IFORMFL_INSERTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_INSERTQ_LAST_DEFINED 1 +#define XED_IFORMFL_INSW_FIRST_DEFINED 1 +#define XED_IFORMFL_INSW_LAST_DEFINED 1 +#define XED_IFORMFL_INT_FIRST_DEFINED 1 +#define XED_IFORMFL_INT_LAST_DEFINED 1 +#define XED_IFORMFL_INT1_FIRST_DEFINED 1 +#define XED_IFORMFL_INT1_LAST_DEFINED 1 +#define XED_IFORMFL_INT3_FIRST_DEFINED 1 +#define XED_IFORMFL_INT3_LAST_DEFINED 1 +#define XED_IFORMFL_INTO_FIRST_DEFINED 1 +#define XED_IFORMFL_INTO_LAST_DEFINED 1 +#define XED_IFORMFL_INVD_FIRST_DEFINED 1 +#define XED_IFORMFL_INVD_LAST_DEFINED 1 +#define XED_IFORMFL_INVEPT_FIRST_DEFINED 1 +#define XED_IFORMFL_INVEPT_LAST_DEFINED 1 +#define XED_IFORMFL_INVLPG_FIRST_DEFINED 1 +#define XED_IFORMFL_INVLPG_LAST_DEFINED 1 +#define XED_IFORMFL_INVLPGA_FIRST_DEFINED 1 +#define XED_IFORMFL_INVLPGA_LAST_DEFINED 1 +#define XED_IFORMFL_INVLPGB_FIRST_DEFINED 1 +#define XED_IFORMFL_INVLPGB_LAST_DEFINED 1 +#define XED_IFORMFL_INVPCID_FIRST_DEFINED 1 +#define XED_IFORMFL_INVPCID_LAST_DEFINED 1 +#define XED_IFORMFL_INVVPID_FIRST_DEFINED 1 +#define XED_IFORMFL_INVVPID_LAST_DEFINED 1 +#define XED_IFORMFL_IRET_FIRST_DEFINED 1 +#define XED_IFORMFL_IRET_LAST_DEFINED 1 +#define XED_IFORMFL_IRETD_FIRST_DEFINED 1 +#define XED_IFORMFL_IRETD_LAST_DEFINED 1 +#define XED_IFORMFL_IRETQ_FIRST_DEFINED 1 +#define XED_IFORMFL_IRETQ_LAST_DEFINED 1 +#define XED_IFORMFL_JB_FIRST_DEFINED 1 +#define XED_IFORMFL_JB_LAST_DEFINED 1 +#define XED_IFORMFL_JBE_FIRST_DEFINED 1 +#define XED_IFORMFL_JBE_LAST_DEFINED 1 +#define XED_IFORMFL_JCXZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JCXZ_LAST_DEFINED 1 +#define XED_IFORMFL_JECXZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JECXZ_LAST_DEFINED 1 +#define XED_IFORMFL_JL_FIRST_DEFINED 1 +#define XED_IFORMFL_JL_LAST_DEFINED 1 +#define XED_IFORMFL_JLE_FIRST_DEFINED 1 +#define XED_IFORMFL_JLE_LAST_DEFINED 1 +#define XED_IFORMFL_JMP_FIRST_DEFINED 1 +#define XED_IFORMFL_JMP_LAST_DEFINED 1 +#define XED_IFORMFL_JMP_FAR_FIRST_DEFINED 1 +#define XED_IFORMFL_JMP_FAR_LAST_DEFINED 1 +#define XED_IFORMFL_JNB_FIRST_DEFINED 1 +#define XED_IFORMFL_JNB_LAST_DEFINED 1 +#define XED_IFORMFL_JNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_JNBE_LAST_DEFINED 1 +#define XED_IFORMFL_JNL_FIRST_DEFINED 1 +#define XED_IFORMFL_JNL_LAST_DEFINED 1 +#define XED_IFORMFL_JNLE_FIRST_DEFINED 1 +#define XED_IFORMFL_JNLE_LAST_DEFINED 1 +#define XED_IFORMFL_JNO_FIRST_DEFINED 1 +#define XED_IFORMFL_JNO_LAST_DEFINED 1 +#define XED_IFORMFL_JNP_FIRST_DEFINED 1 +#define XED_IFORMFL_JNP_LAST_DEFINED 1 +#define XED_IFORMFL_JNS_FIRST_DEFINED 1 +#define XED_IFORMFL_JNS_LAST_DEFINED 1 +#define XED_IFORMFL_JNZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JNZ_LAST_DEFINED 1 +#define XED_IFORMFL_JO_FIRST_DEFINED 1 +#define XED_IFORMFL_JO_LAST_DEFINED 1 +#define XED_IFORMFL_JP_FIRST_DEFINED 1 +#define XED_IFORMFL_JP_LAST_DEFINED 1 +#define XED_IFORMFL_JRCXZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JRCXZ_LAST_DEFINED 1 +#define XED_IFORMFL_JS_FIRST_DEFINED 1 +#define XED_IFORMFL_JS_LAST_DEFINED 1 +#define XED_IFORMFL_JZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JZ_LAST_DEFINED 1 +#define XED_IFORMFL_KADDB_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDB_LAST_DEFINED 1 +#define XED_IFORMFL_KADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDD_LAST_DEFINED 1 +#define XED_IFORMFL_KADDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDQ_LAST_DEFINED 1 +#define XED_IFORMFL_KADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDW_LAST_DEFINED 1 +#define XED_IFORMFL_KANDB_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDB_LAST_DEFINED 1 +#define XED_IFORMFL_KANDD_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDD_LAST_DEFINED 1 +#define XED_IFORMFL_KANDNB_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDNB_LAST_DEFINED 1 +#define XED_IFORMFL_KANDND_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDND_LAST_DEFINED 1 +#define XED_IFORMFL_KANDNQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDNQ_LAST_DEFINED 1 +#define XED_IFORMFL_KANDNW_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDNW_LAST_DEFINED 1 +#define XED_IFORMFL_KANDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDQ_LAST_DEFINED 1 +#define XED_IFORMFL_KANDW_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDW_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVB_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVB_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVD_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVW_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVW_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTB_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTB_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTD_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTD_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTQ_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTW_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTW_LAST_DEFINED 1 +#define XED_IFORMFL_KORB_FIRST_DEFINED 1 +#define XED_IFORMFL_KORB_LAST_DEFINED 1 +#define XED_IFORMFL_KORD_FIRST_DEFINED 1 +#define XED_IFORMFL_KORD_LAST_DEFINED 1 +#define XED_IFORMFL_KORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KORQ_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTB_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTB_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTD_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTD_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTQ_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTW_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTW_LAST_DEFINED 1 +#define XED_IFORMFL_KORW_FIRST_DEFINED 1 +#define XED_IFORMFL_KORW_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLB_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLB_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLD_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLD_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLQ_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLW_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLW_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRB_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRB_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRD_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRD_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRW_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRW_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTB_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTB_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTD_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTD_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTQ_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTW_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTW_LAST_DEFINED 1 +#define XED_IFORMFL_KUNPCKBW_FIRST_DEFINED 1 +#define XED_IFORMFL_KUNPCKBW_LAST_DEFINED 1 +#define XED_IFORMFL_KUNPCKDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KUNPCKDQ_LAST_DEFINED 1 +#define XED_IFORMFL_KUNPCKWD_FIRST_DEFINED 1 +#define XED_IFORMFL_KUNPCKWD_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORB_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORB_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORD_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORD_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORQ_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORW_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORW_LAST_DEFINED 1 +#define XED_IFORMFL_KXORB_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORB_LAST_DEFINED 1 +#define XED_IFORMFL_KXORD_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORD_LAST_DEFINED 1 +#define XED_IFORMFL_KXORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORQ_LAST_DEFINED 1 +#define XED_IFORMFL_KXORW_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORW_LAST_DEFINED 1 +#define XED_IFORMFL_LAHF_FIRST_DEFINED 1 +#define XED_IFORMFL_LAHF_LAST_DEFINED 1 +#define XED_IFORMFL_LAR_FIRST_DEFINED 1 +#define XED_IFORMFL_LAR_LAST_DEFINED 1 +#define XED_IFORMFL_LDDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_LDDQU_LAST_DEFINED 1 +#define XED_IFORMFL_LDMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_LDMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_LDS_FIRST_DEFINED 1 +#define XED_IFORMFL_LDS_LAST_DEFINED 1 +#define XED_IFORMFL_LDTILECFG_FIRST_DEFINED 1 +#define XED_IFORMFL_LDTILECFG_LAST_DEFINED 1 +#define XED_IFORMFL_LEA_FIRST_DEFINED 1 +#define XED_IFORMFL_LEA_LAST_DEFINED 1 +#define XED_IFORMFL_LEAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_LEAVE_LAST_DEFINED 1 +#define XED_IFORMFL_LES_FIRST_DEFINED 1 +#define XED_IFORMFL_LES_LAST_DEFINED 1 +#define XED_IFORMFL_LFENCE_FIRST_DEFINED 1 +#define XED_IFORMFL_LFENCE_LAST_DEFINED 1 +#define XED_IFORMFL_LFS_FIRST_DEFINED 1 +#define XED_IFORMFL_LFS_LAST_DEFINED 1 +#define XED_IFORMFL_LGDT_FIRST_DEFINED 1 +#define XED_IFORMFL_LGDT_LAST_DEFINED 1 +#define XED_IFORMFL_LGS_FIRST_DEFINED 1 +#define XED_IFORMFL_LGS_LAST_DEFINED 1 +#define XED_IFORMFL_LIDT_FIRST_DEFINED 1 +#define XED_IFORMFL_LIDT_LAST_DEFINED 1 +#define XED_IFORMFL_LLDT_FIRST_DEFINED 1 +#define XED_IFORMFL_LLDT_LAST_DEFINED 1 +#define XED_IFORMFL_LLWPCB_FIRST_DEFINED 1 +#define XED_IFORMFL_LLWPCB_LAST_DEFINED 1 +#define XED_IFORMFL_LMSW_FIRST_DEFINED 1 +#define XED_IFORMFL_LMSW_LAST_DEFINED 1 +#define XED_IFORMFL_LOADIWKEY_FIRST_DEFINED 1 +#define XED_IFORMFL_LOADIWKEY_LAST_DEFINED 1 +#define XED_IFORMFL_LODSB_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSB_LAST_DEFINED 1 +#define XED_IFORMFL_LODSD_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSD_LAST_DEFINED 1 +#define XED_IFORMFL_LODSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSQ_LAST_DEFINED 1 +#define XED_IFORMFL_LODSW_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSW_LAST_DEFINED 1 +#define XED_IFORMFL_LOOP_FIRST_DEFINED 1 +#define XED_IFORMFL_LOOP_LAST_DEFINED 1 +#define XED_IFORMFL_LOOPE_FIRST_DEFINED 1 +#define XED_IFORMFL_LOOPE_LAST_DEFINED 1 +#define XED_IFORMFL_LOOPNE_FIRST_DEFINED 1 +#define XED_IFORMFL_LOOPNE_LAST_DEFINED 1 +#define XED_IFORMFL_LSL_FIRST_DEFINED 1 +#define XED_IFORMFL_LSL_LAST_DEFINED 1 +#define XED_IFORMFL_LSS_FIRST_DEFINED 1 +#define XED_IFORMFL_LSS_LAST_DEFINED 1 +#define XED_IFORMFL_LTR_FIRST_DEFINED 1 +#define XED_IFORMFL_LTR_LAST_DEFINED 1 +#define XED_IFORMFL_LWPINS_FIRST_DEFINED 1 +#define XED_IFORMFL_LWPINS_LAST_DEFINED 1 +#define XED_IFORMFL_LWPVAL_FIRST_DEFINED 1 +#define XED_IFORMFL_LWPVAL_LAST_DEFINED 1 +#define XED_IFORMFL_LZCNT_FIRST_DEFINED 1 +#define XED_IFORMFL_LZCNT_LAST_DEFINED 1 +#define XED_IFORMFL_MASKMOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_MASKMOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_MASKMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MASKMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_MAXPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXPD_LAST_DEFINED 1 +#define XED_IFORMFL_MAXPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXPS_LAST_DEFINED 1 +#define XED_IFORMFL_MAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_MAXSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXSS_LAST_DEFINED 1 +#define XED_IFORMFL_MCOMMIT_FIRST_DEFINED 1 +#define XED_IFORMFL_MCOMMIT_LAST_DEFINED 1 +#define XED_IFORMFL_MFENCE_FIRST_DEFINED 1 +#define XED_IFORMFL_MFENCE_LAST_DEFINED 1 +#define XED_IFORMFL_MINPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MINPD_LAST_DEFINED 1 +#define XED_IFORMFL_MINPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MINPS_LAST_DEFINED 1 +#define XED_IFORMFL_MINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MINSD_LAST_DEFINED 1 +#define XED_IFORMFL_MINSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MINSS_LAST_DEFINED 1 +#define XED_IFORMFL_MONITOR_FIRST_DEFINED 1 +#define XED_IFORMFL_MONITOR_LAST_DEFINED 1 +#define XED_IFORMFL_MONITORX_FIRST_DEFINED 1 +#define XED_IFORMFL_MONITORX_LAST_DEFINED 1 +#define XED_IFORMFL_MOV_FIRST_DEFINED 1 +#define XED_IFORMFL_MOV_LAST_DEFINED 1 +#define XED_IFORMFL_MOVAPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVAPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVAPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVAPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVBE_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVBE_LAST_DEFINED 1 +#define XED_IFORMFL_MOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDDUP_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDIR64B_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDIR64B_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDIRI_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDIRI_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDQ2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDQ2Q_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDQA_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_MOVHLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVHLPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVHPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVHPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVLHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVLHPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVLPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVLPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQA_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTI_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTI_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTSD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTSS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVQ2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVQ2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSB_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSB_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSD_XMM_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSD_XMM_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSHDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSHDUP_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSLDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSLDUP_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSW_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSW_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSX_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSX_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSXD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSXD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVUPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVUPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVUPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVUPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVZX_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVZX_LAST_DEFINED 1 +#define XED_IFORMFL_MOV_CR_FIRST_DEFINED 1 +#define XED_IFORMFL_MOV_CR_LAST_DEFINED 1 +#define XED_IFORMFL_MOV_DR_FIRST_DEFINED 1 +#define XED_IFORMFL_MOV_DR_LAST_DEFINED 1 +#define XED_IFORMFL_MPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_MPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_MUL_FIRST_DEFINED 1 +#define XED_IFORMFL_MUL_LAST_DEFINED 1 +#define XED_IFORMFL_MULPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MULPD_LAST_DEFINED 1 +#define XED_IFORMFL_MULPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MULPS_LAST_DEFINED 1 +#define XED_IFORMFL_MULSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MULSD_LAST_DEFINED 1 +#define XED_IFORMFL_MULSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MULSS_LAST_DEFINED 1 +#define XED_IFORMFL_MULX_FIRST_DEFINED 1 +#define XED_IFORMFL_MULX_LAST_DEFINED 1 +#define XED_IFORMFL_MWAIT_FIRST_DEFINED 1 +#define XED_IFORMFL_MWAIT_LAST_DEFINED 1 +#define XED_IFORMFL_MWAITX_FIRST_DEFINED 1 +#define XED_IFORMFL_MWAITX_LAST_DEFINED 1 +#define XED_IFORMFL_NEG_FIRST_DEFINED 1 +#define XED_IFORMFL_NEG_LAST_DEFINED 1 +#define XED_IFORMFL_NEG_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_NEG_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_NOT_FIRST_DEFINED 1 +#define XED_IFORMFL_NOT_LAST_DEFINED 1 +#define XED_IFORMFL_NOT_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_NOT_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_OR_FIRST_DEFINED 1 +#define XED_IFORMFL_OR_LAST_DEFINED 1 +#define XED_IFORMFL_ORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ORPD_LAST_DEFINED 1 +#define XED_IFORMFL_ORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ORPS_LAST_DEFINED 1 +#define XED_IFORMFL_OR_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_OR_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_OUT_FIRST_DEFINED 1 +#define XED_IFORMFL_OUT_LAST_DEFINED 1 +#define XED_IFORMFL_OUTSB_FIRST_DEFINED 1 +#define XED_IFORMFL_OUTSB_LAST_DEFINED 1 +#define XED_IFORMFL_OUTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_OUTSD_LAST_DEFINED 1 +#define XED_IFORMFL_OUTSW_FIRST_DEFINED 1 +#define XED_IFORMFL_OUTSW_LAST_DEFINED 1 +#define XED_IFORMFL_PABSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PABSB_LAST_DEFINED 1 +#define XED_IFORMFL_PABSD_FIRST_DEFINED 1 +#define XED_IFORMFL_PABSD_LAST_DEFINED 1 +#define XED_IFORMFL_PABSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PABSW_LAST_DEFINED 1 +#define XED_IFORMFL_PACKSSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKSSDW_LAST_DEFINED 1 +#define XED_IFORMFL_PACKSSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKSSWB_LAST_DEFINED 1 +#define XED_IFORMFL_PACKUSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKUSDW_LAST_DEFINED 1 +#define XED_IFORMFL_PACKUSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKUSWB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDB_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDD_LAST_DEFINED 1 +#define XED_IFORMFL_PADDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PADDSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDSB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_PADDUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDUSB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDUSW_LAST_DEFINED 1 +#define XED_IFORMFL_PADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDW_LAST_DEFINED 1 +#define XED_IFORMFL_PALIGNR_FIRST_DEFINED 1 +#define XED_IFORMFL_PALIGNR_LAST_DEFINED 1 +#define XED_IFORMFL_PAND_FIRST_DEFINED 1 +#define XED_IFORMFL_PAND_LAST_DEFINED 1 +#define XED_IFORMFL_PANDN_FIRST_DEFINED 1 +#define XED_IFORMFL_PANDN_LAST_DEFINED 1 +#define XED_IFORMFL_PAUSE_FIRST_DEFINED 1 +#define XED_IFORMFL_PAUSE_LAST_DEFINED 1 +#define XED_IFORMFL_PAVGB_FIRST_DEFINED 1 +#define XED_IFORMFL_PAVGB_LAST_DEFINED 1 +#define XED_IFORMFL_PAVGUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PAVGUSB_LAST_DEFINED 1 +#define XED_IFORMFL_PAVGW_FIRST_DEFINED 1 +#define XED_IFORMFL_PAVGW_LAST_DEFINED 1 +#define XED_IFORMFL_PBLENDVB_FIRST_DEFINED 1 +#define XED_IFORMFL_PBLENDVB_LAST_DEFINED 1 +#define XED_IFORMFL_PBLENDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PBLENDW_LAST_DEFINED 1 +#define XED_IFORMFL_PCLMULQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PCLMULQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQB_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQD_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQD_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQQ_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQW_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQW_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM64_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM64_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTB_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTB_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTD_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTD_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTQ_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTW_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTW_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRM_LAST_DEFINED 1 +#define XED_IFORMFL_PCONFIG_FIRST_DEFINED 1 +#define XED_IFORMFL_PCONFIG_LAST_DEFINED 1 +#define XED_IFORMFL_PDEP_FIRST_DEFINED 1 +#define XED_IFORMFL_PDEP_LAST_DEFINED 1 +#define XED_IFORMFL_PEXT_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXT_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRB_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRB_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRD_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRD_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_SSE4_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_SSE4_LAST_DEFINED 1 +#define XED_IFORMFL_PF2ID_FIRST_DEFINED 1 +#define XED_IFORMFL_PF2ID_LAST_DEFINED 1 +#define XED_IFORMFL_PF2IW_FIRST_DEFINED 1 +#define XED_IFORMFL_PF2IW_LAST_DEFINED 1 +#define XED_IFORMFL_PFACC_FIRST_DEFINED 1 +#define XED_IFORMFL_PFACC_LAST_DEFINED 1 +#define XED_IFORMFL_PFADD_FIRST_DEFINED 1 +#define XED_IFORMFL_PFADD_LAST_DEFINED 1 +#define XED_IFORMFL_PFCMPEQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PFCMPEQ_LAST_DEFINED 1 +#define XED_IFORMFL_PFCMPGE_FIRST_DEFINED 1 +#define XED_IFORMFL_PFCMPGE_LAST_DEFINED 1 +#define XED_IFORMFL_PFCMPGT_FIRST_DEFINED 1 +#define XED_IFORMFL_PFCMPGT_LAST_DEFINED 1 +#define XED_IFORMFL_PFMAX_FIRST_DEFINED 1 +#define XED_IFORMFL_PFMAX_LAST_DEFINED 1 +#define XED_IFORMFL_PFMIN_FIRST_DEFINED 1 +#define XED_IFORMFL_PFMIN_LAST_DEFINED 1 +#define XED_IFORMFL_PFMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_PFMUL_LAST_DEFINED 1 +#define XED_IFORMFL_PFNACC_FIRST_DEFINED 1 +#define XED_IFORMFL_PFNACC_LAST_DEFINED 1 +#define XED_IFORMFL_PFPNACC_FIRST_DEFINED 1 +#define XED_IFORMFL_PFPNACC_LAST_DEFINED 1 +#define XED_IFORMFL_PFRCP_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRCP_LAST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT1_LAST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT2_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT2_LAST_DEFINED 1 +#define XED_IFORMFL_PFRSQIT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRSQIT1_LAST_DEFINED 1 +#define XED_IFORMFL_PFRSQRT_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRSQRT_LAST_DEFINED 1 +#define XED_IFORMFL_PFSUB_FIRST_DEFINED 1 +#define XED_IFORMFL_PFSUB_LAST_DEFINED 1 +#define XED_IFORMFL_PFSUBR_FIRST_DEFINED 1 +#define XED_IFORMFL_PFSUBR_LAST_DEFINED 1 +#define XED_IFORMFL_PHADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_PHADDD_LAST_DEFINED 1 +#define XED_IFORMFL_PHADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_PHADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHADDW_LAST_DEFINED 1 +#define XED_IFORMFL_PHMINPOSUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHMINPOSUW_LAST_DEFINED 1 +#define XED_IFORMFL_PHSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PHSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_PHSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_PHSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_PI2FD_FIRST_DEFINED 1 +#define XED_IFORMFL_PI2FD_LAST_DEFINED 1 +#define XED_IFORMFL_PI2FW_FIRST_DEFINED 1 +#define XED_IFORMFL_PI2FW_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRB_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRB_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRD_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRD_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRQ_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRW_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRW_LAST_DEFINED 1 +#define XED_IFORMFL_PMADDUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMADDUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMADDWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMADDWD_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXSB_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXUB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXUB_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXUD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXUD_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXUW_LAST_DEFINED 1 +#define XED_IFORMFL_PMINSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINSB_LAST_DEFINED 1 +#define XED_IFORMFL_PMINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINSD_LAST_DEFINED 1 +#define XED_IFORMFL_PMINSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMINUB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINUB_LAST_DEFINED 1 +#define XED_IFORMFL_PMINUD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINUD_LAST_DEFINED 1 +#define XED_IFORMFL_PMINUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINUW_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVMSKB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVMSKB_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBW_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBW_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMULDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHRSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHRSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHRW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHRW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHUW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULLD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULLD_LAST_DEFINED 1 +#define XED_IFORMFL_PMULLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULLW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULUDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULUDQ_LAST_DEFINED 1 +#define XED_IFORMFL_POP_FIRST_DEFINED 1 +#define XED_IFORMFL_POP_LAST_DEFINED 1 +#define XED_IFORMFL_POPA_FIRST_DEFINED 1 +#define XED_IFORMFL_POPA_LAST_DEFINED 1 +#define XED_IFORMFL_POPAD_FIRST_DEFINED 1 +#define XED_IFORMFL_POPAD_LAST_DEFINED 1 +#define XED_IFORMFL_POPCNT_FIRST_DEFINED 1 +#define XED_IFORMFL_POPCNT_LAST_DEFINED 1 +#define XED_IFORMFL_POPF_FIRST_DEFINED 1 +#define XED_IFORMFL_POPF_LAST_DEFINED 1 +#define XED_IFORMFL_POPFD_FIRST_DEFINED 1 +#define XED_IFORMFL_POPFD_LAST_DEFINED 1 +#define XED_IFORMFL_POPFQ_FIRST_DEFINED 1 +#define XED_IFORMFL_POPFQ_LAST_DEFINED 1 +#define XED_IFORMFL_POR_FIRST_DEFINED 1 +#define XED_IFORMFL_POR_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHNTA_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHNTA_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT0_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT0_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT1_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT2_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT2_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHW_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHW_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHWT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHWT1_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_RESERVED_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_RESERVED_LAST_DEFINED 1 +#define XED_IFORMFL_PSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFB_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFD_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFHW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFHW_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFLW_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFW_LAST_DEFINED 1 +#define XED_IFORMFL_PSIGNB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSIGNB_LAST_DEFINED 1 +#define XED_IFORMFL_PSIGND_FIRST_DEFINED 1 +#define XED_IFORMFL_PSIGND_LAST_DEFINED 1 +#define XED_IFORMFL_PSIGNW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSIGNW_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLD_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLW_LAST_DEFINED 1 +#define XED_IFORMFL_PSMASH_FIRST_DEFINED 1 +#define XED_IFORMFL_PSMASH_LAST_DEFINED 1 +#define XED_IFORMFL_PSRAD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRAD_LAST_DEFINED 1 +#define XED_IFORMFL_PSRAW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRAW_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLD_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLW_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBB_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBSB_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBUSB_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBUSW_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_PSWAPD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSWAPD_LAST_DEFINED 1 +#define XED_IFORMFL_PTEST_FIRST_DEFINED 1 +#define XED_IFORMFL_PTEST_LAST_DEFINED 1 +#define XED_IFORMFL_PTWRITE_FIRST_DEFINED 1 +#define XED_IFORMFL_PTWRITE_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHBW_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHWD_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLBW_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLWD_LAST_DEFINED 1 +#define XED_IFORMFL_PUSH_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSH_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHA_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHA_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHAD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHAD_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHF_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHF_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHFD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHFD_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHFQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHFQ_LAST_DEFINED 1 +#define XED_IFORMFL_PVALIDATE_FIRST_DEFINED 1 +#define XED_IFORMFL_PVALIDATE_LAST_DEFINED 1 +#define XED_IFORMFL_PXOR_FIRST_DEFINED 1 +#define XED_IFORMFL_PXOR_LAST_DEFINED 1 +#define XED_IFORMFL_RCL_FIRST_DEFINED 1 +#define XED_IFORMFL_RCL_LAST_DEFINED 1 +#define XED_IFORMFL_RCPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_RCPPS_LAST_DEFINED 1 +#define XED_IFORMFL_RCPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_RCPSS_LAST_DEFINED 1 +#define XED_IFORMFL_RCR_FIRST_DEFINED 1 +#define XED_IFORMFL_RCR_LAST_DEFINED 1 +#define XED_IFORMFL_RDFSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_RDFSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_RDGSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_RDGSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_RDMSR_FIRST_DEFINED 1 +#define XED_IFORMFL_RDMSR_LAST_DEFINED 1 +#define XED_IFORMFL_RDPID_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPID_LAST_DEFINED 1 +#define XED_IFORMFL_RDPKRU_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPKRU_LAST_DEFINED 1 +#define XED_IFORMFL_RDPMC_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPMC_LAST_DEFINED 1 +#define XED_IFORMFL_RDPRU_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPRU_LAST_DEFINED 1 +#define XED_IFORMFL_RDRAND_FIRST_DEFINED 1 +#define XED_IFORMFL_RDRAND_LAST_DEFINED 1 +#define XED_IFORMFL_RDSEED_FIRST_DEFINED 1 +#define XED_IFORMFL_RDSEED_LAST_DEFINED 1 +#define XED_IFORMFL_RDSSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_RDSSPD_LAST_DEFINED 1 +#define XED_IFORMFL_RDSSPQ_FIRST_DEFINED 1 +#define XED_IFORMFL_RDSSPQ_LAST_DEFINED 1 +#define XED_IFORMFL_RDTSC_FIRST_DEFINED 1 +#define XED_IFORMFL_RDTSC_LAST_DEFINED 1 +#define XED_IFORMFL_RDTSCP_FIRST_DEFINED 1 +#define XED_IFORMFL_RDTSCP_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSB_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSW_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASB_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASD_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASW_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSB_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSW_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASB_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASD_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_INSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_INSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_INSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_INSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_INSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_INSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MONTMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MONTMUL_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCBC_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCBC_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCFB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCFB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCTR_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCTR_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTECB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTECB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTOFB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTOFB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA1_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA1_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA256_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA256_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XSTORE_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XSTORE_LAST_DEFINED 1 +#define XED_IFORMFL_RET_FAR_FIRST_DEFINED 1 +#define XED_IFORMFL_RET_FAR_LAST_DEFINED 1 +#define XED_IFORMFL_RET_NEAR_FIRST_DEFINED 1 +#define XED_IFORMFL_RET_NEAR_LAST_DEFINED 1 +#define XED_IFORMFL_RMPADJUST_FIRST_DEFINED 1 +#define XED_IFORMFL_RMPADJUST_LAST_DEFINED 1 +#define XED_IFORMFL_RMPUPDATE_FIRST_DEFINED 1 +#define XED_IFORMFL_RMPUPDATE_LAST_DEFINED 1 +#define XED_IFORMFL_ROL_FIRST_DEFINED 1 +#define XED_IFORMFL_ROL_LAST_DEFINED 1 +#define XED_IFORMFL_ROR_FIRST_DEFINED 1 +#define XED_IFORMFL_ROR_LAST_DEFINED 1 +#define XED_IFORMFL_RORX_FIRST_DEFINED 1 +#define XED_IFORMFL_RORX_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDPD_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDPS_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDSD_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDSS_LAST_DEFINED 1 +#define XED_IFORMFL_RSM_FIRST_DEFINED 1 +#define XED_IFORMFL_RSM_LAST_DEFINED 1 +#define XED_IFORMFL_RSQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_RSQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_RSQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_RSQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_RSTORSSP_FIRST_DEFINED 1 +#define XED_IFORMFL_RSTORSSP_LAST_DEFINED 1 +#define XED_IFORMFL_SAHF_FIRST_DEFINED 1 +#define XED_IFORMFL_SAHF_LAST_DEFINED 1 +#define XED_IFORMFL_SALC_FIRST_DEFINED 1 +#define XED_IFORMFL_SALC_LAST_DEFINED 1 +#define XED_IFORMFL_SAR_FIRST_DEFINED 1 +#define XED_IFORMFL_SAR_LAST_DEFINED 1 +#define XED_IFORMFL_SARX_FIRST_DEFINED 1 +#define XED_IFORMFL_SARX_LAST_DEFINED 1 +#define XED_IFORMFL_SAVEPREVSSP_FIRST_DEFINED 1 +#define XED_IFORMFL_SAVEPREVSSP_LAST_DEFINED 1 +#define XED_IFORMFL_SBB_FIRST_DEFINED 1 +#define XED_IFORMFL_SBB_LAST_DEFINED 1 +#define XED_IFORMFL_SBB_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_SBB_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_SCASB_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASB_LAST_DEFINED 1 +#define XED_IFORMFL_SCASD_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASD_LAST_DEFINED 1 +#define XED_IFORMFL_SCASQ_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASQ_LAST_DEFINED 1 +#define XED_IFORMFL_SCASW_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASW_LAST_DEFINED 1 +#define XED_IFORMFL_SEAMCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_SEAMCALL_LAST_DEFINED 1 +#define XED_IFORMFL_SEAMOPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SEAMOPS_LAST_DEFINED 1 +#define XED_IFORMFL_SEAMRET_FIRST_DEFINED 1 +#define XED_IFORMFL_SEAMRET_LAST_DEFINED 1 +#define XED_IFORMFL_SENDUIPI_FIRST_DEFINED 1 +#define XED_IFORMFL_SENDUIPI_LAST_DEFINED 1 +#define XED_IFORMFL_SERIALIZE_FIRST_DEFINED 1 +#define XED_IFORMFL_SERIALIZE_LAST_DEFINED 1 +#define XED_IFORMFL_SETB_FIRST_DEFINED 1 +#define XED_IFORMFL_SETB_LAST_DEFINED 1 +#define XED_IFORMFL_SETBE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETBE_LAST_DEFINED 1 +#define XED_IFORMFL_SETL_FIRST_DEFINED 1 +#define XED_IFORMFL_SETL_LAST_DEFINED 1 +#define XED_IFORMFL_SETLE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETLE_LAST_DEFINED 1 +#define XED_IFORMFL_SETNB_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNB_LAST_DEFINED 1 +#define XED_IFORMFL_SETNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNBE_LAST_DEFINED 1 +#define XED_IFORMFL_SETNL_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNL_LAST_DEFINED 1 +#define XED_IFORMFL_SETNLE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNLE_LAST_DEFINED 1 +#define XED_IFORMFL_SETNO_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNO_LAST_DEFINED 1 +#define XED_IFORMFL_SETNP_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNP_LAST_DEFINED 1 +#define XED_IFORMFL_SETNS_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNS_LAST_DEFINED 1 +#define XED_IFORMFL_SETNZ_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNZ_LAST_DEFINED 1 +#define XED_IFORMFL_SETO_FIRST_DEFINED 1 +#define XED_IFORMFL_SETO_LAST_DEFINED 1 +#define XED_IFORMFL_SETP_FIRST_DEFINED 1 +#define XED_IFORMFL_SETP_LAST_DEFINED 1 +#define XED_IFORMFL_SETS_FIRST_DEFINED 1 +#define XED_IFORMFL_SETS_LAST_DEFINED 1 +#define XED_IFORMFL_SETSSBSY_FIRST_DEFINED 1 +#define XED_IFORMFL_SETSSBSY_LAST_DEFINED 1 +#define XED_IFORMFL_SETZ_FIRST_DEFINED 1 +#define XED_IFORMFL_SETZ_LAST_DEFINED 1 +#define XED_IFORMFL_SFENCE_FIRST_DEFINED 1 +#define XED_IFORMFL_SFENCE_LAST_DEFINED 1 +#define XED_IFORMFL_SGDT_FIRST_DEFINED 1 +#define XED_IFORMFL_SGDT_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG1_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG1_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG2_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG2_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1NEXTE_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1NEXTE_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1RNDS4_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1RNDS4_LAST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG1_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG1_LAST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG2_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG2_LAST_DEFINED 1 +#define XED_IFORMFL_SHA256RNDS2_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA256RNDS2_LAST_DEFINED 1 +#define XED_IFORMFL_SHL_FIRST_DEFINED 1 +#define XED_IFORMFL_SHL_LAST_DEFINED 1 +#define XED_IFORMFL_SHLD_FIRST_DEFINED 1 +#define XED_IFORMFL_SHLD_LAST_DEFINED 1 +#define XED_IFORMFL_SHLX_FIRST_DEFINED 1 +#define XED_IFORMFL_SHLX_LAST_DEFINED 1 +#define XED_IFORMFL_SHR_FIRST_DEFINED 1 +#define XED_IFORMFL_SHR_LAST_DEFINED 1 +#define XED_IFORMFL_SHRD_FIRST_DEFINED 1 +#define XED_IFORMFL_SHRD_LAST_DEFINED 1 +#define XED_IFORMFL_SHRX_FIRST_DEFINED 1 +#define XED_IFORMFL_SHRX_LAST_DEFINED 1 +#define XED_IFORMFL_SHUFPD_FIRST_DEFINED 1 +#define XED_IFORMFL_SHUFPD_LAST_DEFINED 1 +#define XED_IFORMFL_SHUFPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SHUFPS_LAST_DEFINED 1 +#define XED_IFORMFL_SIDT_FIRST_DEFINED 1 +#define XED_IFORMFL_SIDT_LAST_DEFINED 1 +#define XED_IFORMFL_SKINIT_FIRST_DEFINED 1 +#define XED_IFORMFL_SKINIT_LAST_DEFINED 1 +#define XED_IFORMFL_SLDT_FIRST_DEFINED 1 +#define XED_IFORMFL_SLDT_LAST_DEFINED 1 +#define XED_IFORMFL_SLWPCB_FIRST_DEFINED 1 +#define XED_IFORMFL_SLWPCB_LAST_DEFINED 1 +#define XED_IFORMFL_SMSW_FIRST_DEFINED 1 +#define XED_IFORMFL_SMSW_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTPD_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTSD_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_STAC_FIRST_DEFINED 1 +#define XED_IFORMFL_STAC_LAST_DEFINED 1 +#define XED_IFORMFL_STC_FIRST_DEFINED 1 +#define XED_IFORMFL_STC_LAST_DEFINED 1 +#define XED_IFORMFL_STD_FIRST_DEFINED 1 +#define XED_IFORMFL_STD_LAST_DEFINED 1 +#define XED_IFORMFL_STGI_FIRST_DEFINED 1 +#define XED_IFORMFL_STGI_LAST_DEFINED 1 +#define XED_IFORMFL_STI_FIRST_DEFINED 1 +#define XED_IFORMFL_STI_LAST_DEFINED 1 +#define XED_IFORMFL_STMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_STMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_STOSB_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSB_LAST_DEFINED 1 +#define XED_IFORMFL_STOSD_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSD_LAST_DEFINED 1 +#define XED_IFORMFL_STOSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSQ_LAST_DEFINED 1 +#define XED_IFORMFL_STOSW_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSW_LAST_DEFINED 1 +#define XED_IFORMFL_STR_FIRST_DEFINED 1 +#define XED_IFORMFL_STR_LAST_DEFINED 1 +#define XED_IFORMFL_STTILECFG_FIRST_DEFINED 1 +#define XED_IFORMFL_STTILECFG_LAST_DEFINED 1 +#define XED_IFORMFL_STUI_FIRST_DEFINED 1 +#define XED_IFORMFL_STUI_LAST_DEFINED 1 +#define XED_IFORMFL_SUB_FIRST_DEFINED 1 +#define XED_IFORMFL_SUB_LAST_DEFINED 1 +#define XED_IFORMFL_SUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_SUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_SUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_SUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_SUB_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_SUB_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_SWAPGS_FIRST_DEFINED 1 +#define XED_IFORMFL_SWAPGS_LAST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_LAST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_AMD_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_AMD_LAST_DEFINED 1 +#define XED_IFORMFL_SYSENTER_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSENTER_LAST_DEFINED 1 +#define XED_IFORMFL_SYSEXIT_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSEXIT_LAST_DEFINED 1 +#define XED_IFORMFL_SYSRET_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSRET_LAST_DEFINED 1 +#define XED_IFORMFL_SYSRET64_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSRET64_LAST_DEFINED 1 +#define XED_IFORMFL_SYSRET_AMD_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSRET_AMD_LAST_DEFINED 1 +#define XED_IFORMFL_T1MSKC_FIRST_DEFINED 1 +#define XED_IFORMFL_T1MSKC_LAST_DEFINED 1 +#define XED_IFORMFL_TDCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_TDCALL_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBF16PS_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBF16PS_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBSSD_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBSUD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBSUD_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBUSD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBUSD_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBUUD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBUUD_LAST_DEFINED 1 +#define XED_IFORMFL_TEST_FIRST_DEFINED 1 +#define XED_IFORMFL_TEST_LAST_DEFINED 1 +#define XED_IFORMFL_TESTUI_FIRST_DEFINED 1 +#define XED_IFORMFL_TESTUI_LAST_DEFINED 1 +#define XED_IFORMFL_TILELOADD_FIRST_DEFINED 1 +#define XED_IFORMFL_TILELOADD_LAST_DEFINED 1 +#define XED_IFORMFL_TILELOADDT1_FIRST_DEFINED 1 +#define XED_IFORMFL_TILELOADDT1_LAST_DEFINED 1 +#define XED_IFORMFL_TILERELEASE_FIRST_DEFINED 1 +#define XED_IFORMFL_TILERELEASE_LAST_DEFINED 1 +#define XED_IFORMFL_TILESTORED_FIRST_DEFINED 1 +#define XED_IFORMFL_TILESTORED_LAST_DEFINED 1 +#define XED_IFORMFL_TILEZERO_FIRST_DEFINED 1 +#define XED_IFORMFL_TILEZERO_LAST_DEFINED 1 +#define XED_IFORMFL_TLBSYNC_FIRST_DEFINED 1 +#define XED_IFORMFL_TLBSYNC_LAST_DEFINED 1 +#define XED_IFORMFL_TPAUSE_FIRST_DEFINED 1 +#define XED_IFORMFL_TPAUSE_LAST_DEFINED 1 +#define XED_IFORMFL_TZCNT_FIRST_DEFINED 1 +#define XED_IFORMFL_TZCNT_LAST_DEFINED 1 +#define XED_IFORMFL_TZMSK_FIRST_DEFINED 1 +#define XED_IFORMFL_TZMSK_LAST_DEFINED 1 +#define XED_IFORMFL_UCOMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_UCOMISD_LAST_DEFINED 1 +#define XED_IFORMFL_UCOMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_UCOMISS_LAST_DEFINED 1 +#define XED_IFORMFL_UD0_FIRST_DEFINED 1 +#define XED_IFORMFL_UD0_LAST_DEFINED 1 +#define XED_IFORMFL_UD1_FIRST_DEFINED 1 +#define XED_IFORMFL_UD1_LAST_DEFINED 1 +#define XED_IFORMFL_UD2_FIRST_DEFINED 1 +#define XED_IFORMFL_UD2_LAST_DEFINED 1 +#define XED_IFORMFL_UIRET_FIRST_DEFINED 1 +#define XED_IFORMFL_UIRET_LAST_DEFINED 1 +#define XED_IFORMFL_UMONITOR_FIRST_DEFINED 1 +#define XED_IFORMFL_UMONITOR_LAST_DEFINED 1 +#define XED_IFORMFL_UMWAIT_FIRST_DEFINED 1 +#define XED_IFORMFL_UMWAIT_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPD_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPS_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPD_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VADDPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDPH_LAST_DEFINED 1 +#define XED_IFORMFL_VADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSH_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VAESDEC_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESDEC_LAST_DEFINED 1 +#define XED_IFORMFL_VAESDECLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESDECLAST_LAST_DEFINED 1 +#define XED_IFORMFL_VAESENC_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESENC_LAST_DEFINED 1 +#define XED_IFORMFL_VAESENCLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESENCLAST_LAST_DEFINED 1 +#define XED_IFORMFL_VAESIMC_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESIMC_LAST_DEFINED 1 +#define XED_IFORMFL_VAESKEYGENASSIST_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESKEYGENASSIST_LAST_DEFINED 1 +#define XED_IFORMFL_VALIGND_FIRST_DEFINED 1 +#define XED_IFORMFL_VALIGND_LAST_DEFINED 1 +#define XED_IFORMFL_VALIGNQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VALIGNQ_LAST_DEFINED 1 +#define XED_IFORMFL_VANDNPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDNPD_LAST_DEFINED 1 +#define XED_IFORMFL_VANDNPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDNPS_LAST_DEFINED 1 +#define XED_IFORMFL_VANDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VANDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPD_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF128_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF128_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI128_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI128_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSD_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPPD_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPPH_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPSH_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPSS_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMISD_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMISH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMISH_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMISS_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPD_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTNE2PS2BF16_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTNE2PS2BF16_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTNEPS2BF16_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTNEPS2BF16_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PSX_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PSX_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UW_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UW_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2W_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PHX_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PHX_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UW_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UW_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2W_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUW2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUW2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTW2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTW2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VDBPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VDBPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVPD_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVPH_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVPS_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVSD_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVSH_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVSS_LAST_DEFINED 1 +#define XED_IFORMFL_VDPBF16PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDPBF16PS_LAST_DEFINED 1 +#define XED_IFORMFL_VDPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VDPPD_LAST_DEFINED 1 +#define XED_IFORMFL_VDPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VERR_FIRST_DEFINED 1 +#define XED_IFORMFL_VERR_LAST_DEFINED 1 +#define XED_IFORMFL_VERW_FIRST_DEFINED 1 +#define XED_IFORMFL_VERW_LAST_DEFINED 1 +#define XED_IFORMFL_VEXP2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXP2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VEXP2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXP2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF128_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF128_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI128_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI128_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMULCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMULCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMULCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMULCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMULCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMULCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMULCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMULCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZSS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEINVQB_LAST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEQB_LAST_DEFINED 1 +#define XED_IFORMFL_VGF2P8MULB_FIRST_DEFINED 1 +#define XED_IFORMFL_VGF2P8MULB_LAST_DEFINED 1 +#define XED_IFORMFL_VHADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VHADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VHADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VHADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VHSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VHSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VHSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VHSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF128_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF128_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI128_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI128_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VLDDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_VLDDQU_LAST_DEFINED 1 +#define XED_IFORMFL_VLDMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_VLDMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXPH_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_VMCALL_LAST_DEFINED 1 +#define XED_IFORMFL_VMCLEAR_FIRST_DEFINED 1 +#define XED_IFORMFL_VMCLEAR_LAST_DEFINED 1 +#define XED_IFORMFL_VMFUNC_FIRST_DEFINED 1 +#define XED_IFORMFL_VMFUNC_LAST_DEFINED 1 +#define XED_IFORMFL_VMINPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMINPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINPH_LAST_DEFINED 1 +#define XED_IFORMFL_VMINPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMINSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMINSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMLAUNCH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMLAUNCH_LAST_DEFINED 1 +#define XED_IFORMFL_VMLOAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMLOAD_LAST_DEFINED 1 +#define XED_IFORMFL_VMMCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_VMMCALL_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVAPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVAPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVAPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVAPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDDUP_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA32_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA32_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA64_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA64_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU16_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU16_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU32_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU32_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU64_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU64_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU8_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU8_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVHLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVHLPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVHPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVHPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVLHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVLHPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVLPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVLPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQA_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSHDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSHDUP_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSLDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSLDUP_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVUPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVUPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVUPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVUPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVW_LAST_DEFINED 1 +#define XED_IFORMFL_VMPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VMPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_VMPTRLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMPTRLD_LAST_DEFINED 1 +#define XED_IFORMFL_VMPTRST_FIRST_DEFINED 1 +#define XED_IFORMFL_VMPTRST_LAST_DEFINED 1 +#define XED_IFORMFL_VMREAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMREAD_LAST_DEFINED 1 +#define XED_IFORMFL_VMRESUME_FIRST_DEFINED 1 +#define XED_IFORMFL_VMRESUME_LAST_DEFINED 1 +#define XED_IFORMFL_VMRUN_FIRST_DEFINED 1 +#define XED_IFORMFL_VMRUN_LAST_DEFINED 1 +#define XED_IFORMFL_VMSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_VMSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_VMULPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMULPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULPH_LAST_DEFINED 1 +#define XED_IFORMFL_VMULPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMULSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMULSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMULSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMWRITE_FIRST_DEFINED 1 +#define XED_IFORMFL_VMWRITE_LAST_DEFINED 1 +#define XED_IFORMFL_VMXOFF_FIRST_DEFINED 1 +#define XED_IFORMFL_VMXOFF_LAST_DEFINED 1 +#define XED_IFORMFL_VMXON_FIRST_DEFINED 1 +#define XED_IFORMFL_VMXON_LAST_DEFINED 1 +#define XED_IFORMFL_VORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VORPD_LAST_DEFINED 1 +#define XED_IFORMFL_VORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VORPS_LAST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTD_LAST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSD_LAST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSDS_FIRST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSDS_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKSSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKSSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKSSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKSSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKUSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKUSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKUSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKUSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDUSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDUSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPALIGNR_FIRST_DEFINED 1 +#define XED_IFORMFL_VPALIGNR_LAST_DEFINED 1 +#define XED_IFORMFL_VPAND_FIRST_DEFINED 1 +#define XED_IFORMFL_VPAND_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDN_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDN_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDND_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDND_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDNQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDNQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPAVGB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPAVGB_LAST_DEFINED 1 +#define XED_IFORMFL_VPAVGW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPAVGW_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDVB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDVB_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMB2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMB2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMW2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMW2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCLMULQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCLMULQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMOV_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMOV_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM64_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM64_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRM_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSDS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSDS_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSDS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSDS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERM2F128_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERM2F128_LAST_DEFINED 1 +#define XED_IFORMFL_VPERM2I128_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERM2I128_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2B_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2B_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2W_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMILPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMILPD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMILPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMILPS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMPS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2B_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2B_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2W_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRB_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRD_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_C5_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_C5_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHMINPOSUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHMINPOSUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRB_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRD_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRW_LAST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQH_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQH_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQL_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQL_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQH_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQH_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQL_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQL_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSWW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSWW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADCSSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADCSSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADCSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADCSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADD52HUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADD52HUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADD52LUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADD52LUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADDUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADDUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADDWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADDWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVB2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVB2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVD2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVD2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2B_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2B_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2W_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVMSKB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVMSKB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQ2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQ2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVW2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVW2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULHRSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULHRSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULHUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULHUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULHW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULHW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULTISHIFTQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULTISHIFTQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULUDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULUDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPOR_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOR_LAST_DEFINED 1 +#define XED_IFORMFL_VPORD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPORD_LAST_DEFINED 1 +#define XED_IFORMFL_VPORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPORQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPPERM_FIRST_DEFINED 1 +#define XED_IFORMFL_VPPERM_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORD_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFBITQMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFBITQMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFHW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFHW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSIGNB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSIGNB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSIGND_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSIGND_LAST_DEFINED 1 +#define XED_IFORMFL_VPSIGNW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSIGNW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGD_LAST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPTEST_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTEST_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPXOR_FIRST_DEFINED 1 +#define XED_IFORMFL_VPXOR_LAST_DEFINED 1 +#define XED_IFORMFL_VPXORD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPXORD_LAST_DEFINED 1 +#define XED_IFORMFL_VPXORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPXORQ_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGEPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGEPD_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGEPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGEPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGESD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGESD_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGESS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGESS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPPH_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPSH_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPSS_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPD_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPH_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPS_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCESD_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCESD_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCESH_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCESH_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCESS_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCESS_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPD_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPH_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESD_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESH_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESS_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPH_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSH_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPH_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSH_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTPH_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTSD_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTSH_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VSTMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_VSTMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBPH_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBSH_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_VTESTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VTESTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VTESTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VTESTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VUCOMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_VUCOMISD_LAST_DEFINED 1 +#define XED_IFORMFL_VUCOMISH_FIRST_DEFINED 1 +#define XED_IFORMFL_VUCOMISH_LAST_DEFINED 1 +#define XED_IFORMFL_VUCOMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_VUCOMISS_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPD_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPS_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPD_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPS_LAST_DEFINED 1 +#define XED_IFORMFL_VXORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VXORPD_LAST_DEFINED 1 +#define XED_IFORMFL_VXORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VXORPS_LAST_DEFINED 1 +#define XED_IFORMFL_VZEROALL_FIRST_DEFINED 1 +#define XED_IFORMFL_VZEROALL_LAST_DEFINED 1 +#define XED_IFORMFL_VZEROUPPER_FIRST_DEFINED 1 +#define XED_IFORMFL_VZEROUPPER_LAST_DEFINED 1 +#define XED_IFORMFL_WBINVD_FIRST_DEFINED 1 +#define XED_IFORMFL_WBINVD_LAST_DEFINED 1 +#define XED_IFORMFL_WBNOINVD_FIRST_DEFINED 1 +#define XED_IFORMFL_WBNOINVD_LAST_DEFINED 1 +#define XED_IFORMFL_WRFSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_WRFSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_WRGSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_WRGSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_WRMSR_FIRST_DEFINED 1 +#define XED_IFORMFL_WRMSR_LAST_DEFINED 1 +#define XED_IFORMFL_WRPKRU_FIRST_DEFINED 1 +#define XED_IFORMFL_WRPKRU_LAST_DEFINED 1 +#define XED_IFORMFL_WRSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_WRSSD_LAST_DEFINED 1 +#define XED_IFORMFL_WRSSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_WRSSQ_LAST_DEFINED 1 +#define XED_IFORMFL_WRUSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_WRUSSD_LAST_DEFINED 1 +#define XED_IFORMFL_WRUSSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_WRUSSQ_LAST_DEFINED 1 +#define XED_IFORMFL_XABORT_FIRST_DEFINED 1 +#define XED_IFORMFL_XABORT_LAST_DEFINED 1 +#define XED_IFORMFL_XADD_FIRST_DEFINED 1 +#define XED_IFORMFL_XADD_LAST_DEFINED 1 +#define XED_IFORMFL_XADD_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_XADD_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_XBEGIN_FIRST_DEFINED 1 +#define XED_IFORMFL_XBEGIN_LAST_DEFINED 1 +#define XED_IFORMFL_XCHG_FIRST_DEFINED 1 +#define XED_IFORMFL_XCHG_LAST_DEFINED 1 +#define XED_IFORMFL_XEND_FIRST_DEFINED 1 +#define XED_IFORMFL_XEND_LAST_DEFINED 1 +#define XED_IFORMFL_XGETBV_FIRST_DEFINED 1 +#define XED_IFORMFL_XGETBV_LAST_DEFINED 1 +#define XED_IFORMFL_XLAT_FIRST_DEFINED 1 +#define XED_IFORMFL_XLAT_LAST_DEFINED 1 +#define XED_IFORMFL_XOR_FIRST_DEFINED 1 +#define XED_IFORMFL_XOR_LAST_DEFINED 1 +#define XED_IFORMFL_XORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_XORPD_LAST_DEFINED 1 +#define XED_IFORMFL_XORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_XORPS_LAST_DEFINED 1 +#define XED_IFORMFL_XOR_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_XOR_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_XRESLDTRK_FIRST_DEFINED 1 +#define XED_IFORMFL_XRESLDTRK_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTOR_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTOR_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTOR64_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTOR64_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTORS_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTORS_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTORS64_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTORS64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVE64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVE64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEC_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEC_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEC64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEC64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVES_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVES_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVES64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVES64_LAST_DEFINED 1 +#define XED_IFORMFL_XSETBV_FIRST_DEFINED 1 +#define XED_IFORMFL_XSETBV_LAST_DEFINED 1 +#define XED_IFORMFL_XSTORE_FIRST_DEFINED 1 +#define XED_IFORMFL_XSTORE_LAST_DEFINED 1 +#define XED_IFORMFL_XSUSLDTRK_FIRST_DEFINED 1 +#define XED_IFORMFL_XSUSLDTRK_LAST_DEFINED 1 +#define XED_IFORMFL_XTEST_FIRST_DEFINED 1 +#define XED_IFORMFL_XTEST_LAST_DEFINED 1 +#define XED_IFORMFL_LAST_DEFINED 1 +typedef enum { + XED_IFORMFL_AAA_FIRST=1, + XED_IFORMFL_AAA_LAST=1, + XED_IFORMFL_AAD_FIRST=2, + XED_IFORMFL_AAD_LAST=2, + XED_IFORMFL_AAM_FIRST=3, + XED_IFORMFL_AAM_LAST=3, + XED_IFORMFL_AAS_FIRST=4, + XED_IFORMFL_AAS_LAST=4, + XED_IFORMFL_ADC_FIRST=5, + XED_IFORMFL_ADC_LAST=22, + XED_IFORMFL_ADCX_FIRST=23, + XED_IFORMFL_ADCX_LAST=26, + XED_IFORMFL_ADC_LOCK_FIRST=27, + XED_IFORMFL_ADC_LOCK_LAST=32, + XED_IFORMFL_ADD_FIRST=33, + XED_IFORMFL_ADD_LAST=50, + XED_IFORMFL_ADDPD_FIRST=51, + XED_IFORMFL_ADDPD_LAST=52, + XED_IFORMFL_ADDPS_FIRST=53, + XED_IFORMFL_ADDPS_LAST=54, + XED_IFORMFL_ADDSD_FIRST=55, + XED_IFORMFL_ADDSD_LAST=56, + XED_IFORMFL_ADDSS_FIRST=57, + XED_IFORMFL_ADDSS_LAST=58, + XED_IFORMFL_ADDSUBPD_FIRST=59, + XED_IFORMFL_ADDSUBPD_LAST=60, + XED_IFORMFL_ADDSUBPS_FIRST=61, + XED_IFORMFL_ADDSUBPS_LAST=62, + XED_IFORMFL_ADD_LOCK_FIRST=63, + XED_IFORMFL_ADD_LOCK_LAST=68, + XED_IFORMFL_ADOX_FIRST=69, + XED_IFORMFL_ADOX_LAST=72, + XED_IFORMFL_AESDEC_FIRST=73, + XED_IFORMFL_AESDEC_LAST=74, + XED_IFORMFL_AESDEC128KL_FIRST=75, + XED_IFORMFL_AESDEC128KL_LAST=75, + XED_IFORMFL_AESDEC256KL_FIRST=76, + XED_IFORMFL_AESDEC256KL_LAST=76, + XED_IFORMFL_AESDECLAST_FIRST=77, + XED_IFORMFL_AESDECLAST_LAST=78, + XED_IFORMFL_AESDECWIDE128KL_FIRST=79, + XED_IFORMFL_AESDECWIDE128KL_LAST=79, + XED_IFORMFL_AESDECWIDE256KL_FIRST=80, + XED_IFORMFL_AESDECWIDE256KL_LAST=80, + XED_IFORMFL_AESENC_FIRST=81, + XED_IFORMFL_AESENC_LAST=82, + XED_IFORMFL_AESENC128KL_FIRST=83, + XED_IFORMFL_AESENC128KL_LAST=83, + XED_IFORMFL_AESENC256KL_FIRST=84, + XED_IFORMFL_AESENC256KL_LAST=84, + XED_IFORMFL_AESENCLAST_FIRST=85, + XED_IFORMFL_AESENCLAST_LAST=86, + XED_IFORMFL_AESENCWIDE128KL_FIRST=87, + XED_IFORMFL_AESENCWIDE128KL_LAST=87, + XED_IFORMFL_AESENCWIDE256KL_FIRST=88, + XED_IFORMFL_AESENCWIDE256KL_LAST=88, + XED_IFORMFL_AESIMC_FIRST=89, + XED_IFORMFL_AESIMC_LAST=90, + XED_IFORMFL_AESKEYGENASSIST_FIRST=91, + XED_IFORMFL_AESKEYGENASSIST_LAST=92, + XED_IFORMFL_AND_FIRST=93, + XED_IFORMFL_AND_LAST=110, + XED_IFORMFL_ANDN_FIRST=111, + XED_IFORMFL_ANDN_LAST=114, + XED_IFORMFL_ANDNPD_FIRST=115, + XED_IFORMFL_ANDNPD_LAST=116, + XED_IFORMFL_ANDNPS_FIRST=117, + XED_IFORMFL_ANDNPS_LAST=118, + XED_IFORMFL_ANDPD_FIRST=119, + XED_IFORMFL_ANDPD_LAST=120, + XED_IFORMFL_ANDPS_FIRST=121, + XED_IFORMFL_ANDPS_LAST=122, + XED_IFORMFL_AND_LOCK_FIRST=123, + XED_IFORMFL_AND_LOCK_LAST=128, + XED_IFORMFL_ARPL_FIRST=129, + XED_IFORMFL_ARPL_LAST=130, + XED_IFORMFL_BEXTR_FIRST=131, + XED_IFORMFL_BEXTR_LAST=134, + XED_IFORMFL_BEXTR_XOP_FIRST=135, + XED_IFORMFL_BEXTR_XOP_LAST=138, + XED_IFORMFL_BLCFILL_FIRST=139, + XED_IFORMFL_BLCFILL_LAST=142, + XED_IFORMFL_BLCI_FIRST=143, + XED_IFORMFL_BLCI_LAST=146, + XED_IFORMFL_BLCIC_FIRST=147, + XED_IFORMFL_BLCIC_LAST=150, + XED_IFORMFL_BLCMSK_FIRST=151, + XED_IFORMFL_BLCMSK_LAST=154, + XED_IFORMFL_BLCS_FIRST=155, + XED_IFORMFL_BLCS_LAST=158, + XED_IFORMFL_BLENDPD_FIRST=159, + XED_IFORMFL_BLENDPD_LAST=160, + XED_IFORMFL_BLENDPS_FIRST=161, + XED_IFORMFL_BLENDPS_LAST=162, + XED_IFORMFL_BLENDVPD_FIRST=163, + XED_IFORMFL_BLENDVPD_LAST=164, + XED_IFORMFL_BLENDVPS_FIRST=165, + XED_IFORMFL_BLENDVPS_LAST=166, + XED_IFORMFL_BLSFILL_FIRST=167, + XED_IFORMFL_BLSFILL_LAST=170, + XED_IFORMFL_BLSI_FIRST=171, + XED_IFORMFL_BLSI_LAST=174, + XED_IFORMFL_BLSIC_FIRST=175, + XED_IFORMFL_BLSIC_LAST=178, + XED_IFORMFL_BLSMSK_FIRST=179, + XED_IFORMFL_BLSMSK_LAST=182, + XED_IFORMFL_BLSR_FIRST=183, + XED_IFORMFL_BLSR_LAST=186, + XED_IFORMFL_BNDCL_FIRST=187, + XED_IFORMFL_BNDCL_LAST=189, + XED_IFORMFL_BNDCN_FIRST=190, + XED_IFORMFL_BNDCN_LAST=192, + XED_IFORMFL_BNDCU_FIRST=193, + XED_IFORMFL_BNDCU_LAST=195, + XED_IFORMFL_BNDLDX_FIRST=196, + XED_IFORMFL_BNDLDX_LAST=197, + XED_IFORMFL_BNDMK_FIRST=198, + XED_IFORMFL_BNDMK_LAST=198, + XED_IFORMFL_BNDMOV_FIRST=199, + XED_IFORMFL_BNDMOV_LAST=203, + XED_IFORMFL_BNDSTX_FIRST=204, + XED_IFORMFL_BNDSTX_LAST=205, + XED_IFORMFL_BOUND_FIRST=206, + XED_IFORMFL_BOUND_LAST=207, + XED_IFORMFL_BSF_FIRST=208, + XED_IFORMFL_BSF_LAST=209, + XED_IFORMFL_BSR_FIRST=210, + XED_IFORMFL_BSR_LAST=211, + XED_IFORMFL_BSWAP_FIRST=212, + XED_IFORMFL_BSWAP_LAST=212, + XED_IFORMFL_BT_FIRST=213, + XED_IFORMFL_BT_LAST=216, + XED_IFORMFL_BTC_FIRST=217, + XED_IFORMFL_BTC_LAST=220, + XED_IFORMFL_BTC_LOCK_FIRST=221, + XED_IFORMFL_BTC_LOCK_LAST=222, + XED_IFORMFL_BTR_FIRST=223, + XED_IFORMFL_BTR_LAST=226, + XED_IFORMFL_BTR_LOCK_FIRST=227, + XED_IFORMFL_BTR_LOCK_LAST=228, + XED_IFORMFL_BTS_FIRST=229, + XED_IFORMFL_BTS_LAST=232, + XED_IFORMFL_BTS_LOCK_FIRST=233, + XED_IFORMFL_BTS_LOCK_LAST=234, + XED_IFORMFL_BZHI_FIRST=235, + XED_IFORMFL_BZHI_LAST=238, + XED_IFORMFL_CALL_FAR_FIRST=239, + XED_IFORMFL_CALL_FAR_LAST=240, + XED_IFORMFL_CALL_NEAR_FIRST=241, + XED_IFORMFL_CALL_NEAR_LAST=244, + XED_IFORMFL_CBW_FIRST=245, + XED_IFORMFL_CBW_LAST=245, + XED_IFORMFL_CDQ_FIRST=246, + XED_IFORMFL_CDQ_LAST=246, + XED_IFORMFL_CDQE_FIRST=247, + XED_IFORMFL_CDQE_LAST=247, + XED_IFORMFL_CLAC_FIRST=248, + XED_IFORMFL_CLAC_LAST=248, + XED_IFORMFL_CLC_FIRST=249, + XED_IFORMFL_CLC_LAST=249, + XED_IFORMFL_CLD_FIRST=250, + XED_IFORMFL_CLD_LAST=250, + XED_IFORMFL_CLDEMOTE_FIRST=251, + XED_IFORMFL_CLDEMOTE_LAST=251, + XED_IFORMFL_CLFLUSH_FIRST=252, + XED_IFORMFL_CLFLUSH_LAST=252, + XED_IFORMFL_CLFLUSHOPT_FIRST=253, + XED_IFORMFL_CLFLUSHOPT_LAST=253, + XED_IFORMFL_CLGI_FIRST=254, + XED_IFORMFL_CLGI_LAST=254, + XED_IFORMFL_CLI_FIRST=255, + XED_IFORMFL_CLI_LAST=255, + XED_IFORMFL_CLRSSBSY_FIRST=256, + XED_IFORMFL_CLRSSBSY_LAST=256, + XED_IFORMFL_CLTS_FIRST=257, + XED_IFORMFL_CLTS_LAST=257, + XED_IFORMFL_CLUI_FIRST=258, + XED_IFORMFL_CLUI_LAST=258, + XED_IFORMFL_CLWB_FIRST=259, + XED_IFORMFL_CLWB_LAST=259, + XED_IFORMFL_CLZERO_FIRST=260, + XED_IFORMFL_CLZERO_LAST=260, + XED_IFORMFL_CMC_FIRST=261, + XED_IFORMFL_CMC_LAST=261, + XED_IFORMFL_CMOVB_FIRST=262, + XED_IFORMFL_CMOVB_LAST=263, + XED_IFORMFL_CMOVBE_FIRST=264, + XED_IFORMFL_CMOVBE_LAST=265, + XED_IFORMFL_CMOVL_FIRST=266, + XED_IFORMFL_CMOVL_LAST=267, + XED_IFORMFL_CMOVLE_FIRST=268, + XED_IFORMFL_CMOVLE_LAST=269, + XED_IFORMFL_CMOVNB_FIRST=270, + XED_IFORMFL_CMOVNB_LAST=271, + XED_IFORMFL_CMOVNBE_FIRST=272, + XED_IFORMFL_CMOVNBE_LAST=273, + XED_IFORMFL_CMOVNL_FIRST=274, + XED_IFORMFL_CMOVNL_LAST=275, + XED_IFORMFL_CMOVNLE_FIRST=276, + XED_IFORMFL_CMOVNLE_LAST=277, + XED_IFORMFL_CMOVNO_FIRST=278, + XED_IFORMFL_CMOVNO_LAST=279, + XED_IFORMFL_CMOVNP_FIRST=280, + XED_IFORMFL_CMOVNP_LAST=281, + XED_IFORMFL_CMOVNS_FIRST=282, + XED_IFORMFL_CMOVNS_LAST=283, + XED_IFORMFL_CMOVNZ_FIRST=284, + XED_IFORMFL_CMOVNZ_LAST=285, + XED_IFORMFL_CMOVO_FIRST=286, + XED_IFORMFL_CMOVO_LAST=287, + XED_IFORMFL_CMOVP_FIRST=288, + XED_IFORMFL_CMOVP_LAST=289, + XED_IFORMFL_CMOVS_FIRST=290, + XED_IFORMFL_CMOVS_LAST=291, + XED_IFORMFL_CMOVZ_FIRST=292, + XED_IFORMFL_CMOVZ_LAST=293, + XED_IFORMFL_CMP_FIRST=294, + XED_IFORMFL_CMP_LAST=311, + XED_IFORMFL_CMPPD_FIRST=312, + XED_IFORMFL_CMPPD_LAST=313, + XED_IFORMFL_CMPPS_FIRST=314, + XED_IFORMFL_CMPPS_LAST=315, + XED_IFORMFL_CMPSB_FIRST=316, + XED_IFORMFL_CMPSB_LAST=316, + XED_IFORMFL_CMPSD_FIRST=317, + XED_IFORMFL_CMPSD_LAST=317, + XED_IFORMFL_CMPSD_XMM_FIRST=318, + XED_IFORMFL_CMPSD_XMM_LAST=319, + XED_IFORMFL_CMPSQ_FIRST=320, + XED_IFORMFL_CMPSQ_LAST=320, + XED_IFORMFL_CMPSS_FIRST=321, + XED_IFORMFL_CMPSS_LAST=322, + XED_IFORMFL_CMPSW_FIRST=323, + XED_IFORMFL_CMPSW_LAST=323, + XED_IFORMFL_CMPXCHG_FIRST=324, + XED_IFORMFL_CMPXCHG_LAST=327, + XED_IFORMFL_CMPXCHG16B_FIRST=328, + XED_IFORMFL_CMPXCHG16B_LAST=328, + XED_IFORMFL_CMPXCHG16B_LOCK_FIRST=329, + XED_IFORMFL_CMPXCHG16B_LOCK_LAST=329, + XED_IFORMFL_CMPXCHG8B_FIRST=330, + XED_IFORMFL_CMPXCHG8B_LAST=330, + XED_IFORMFL_CMPXCHG8B_LOCK_FIRST=331, + XED_IFORMFL_CMPXCHG8B_LOCK_LAST=331, + XED_IFORMFL_CMPXCHG_LOCK_FIRST=332, + XED_IFORMFL_CMPXCHG_LOCK_LAST=333, + XED_IFORMFL_COMISD_FIRST=334, + XED_IFORMFL_COMISD_LAST=335, + XED_IFORMFL_COMISS_FIRST=336, + XED_IFORMFL_COMISS_LAST=337, + XED_IFORMFL_CPUID_FIRST=338, + XED_IFORMFL_CPUID_LAST=338, + XED_IFORMFL_CQO_FIRST=339, + XED_IFORMFL_CQO_LAST=339, + XED_IFORMFL_CRC32_FIRST=340, + XED_IFORMFL_CRC32_LAST=343, + XED_IFORMFL_CVTDQ2PD_FIRST=344, + XED_IFORMFL_CVTDQ2PD_LAST=345, + XED_IFORMFL_CVTDQ2PS_FIRST=346, + XED_IFORMFL_CVTDQ2PS_LAST=347, + XED_IFORMFL_CVTPD2DQ_FIRST=348, + XED_IFORMFL_CVTPD2DQ_LAST=349, + XED_IFORMFL_CVTPD2PI_FIRST=350, + XED_IFORMFL_CVTPD2PI_LAST=351, + XED_IFORMFL_CVTPD2PS_FIRST=352, + XED_IFORMFL_CVTPD2PS_LAST=353, + XED_IFORMFL_CVTPI2PD_FIRST=354, + XED_IFORMFL_CVTPI2PD_LAST=355, + XED_IFORMFL_CVTPI2PS_FIRST=356, + XED_IFORMFL_CVTPI2PS_LAST=357, + XED_IFORMFL_CVTPS2DQ_FIRST=358, + XED_IFORMFL_CVTPS2DQ_LAST=359, + XED_IFORMFL_CVTPS2PD_FIRST=360, + XED_IFORMFL_CVTPS2PD_LAST=361, + XED_IFORMFL_CVTPS2PI_FIRST=362, + XED_IFORMFL_CVTPS2PI_LAST=363, + XED_IFORMFL_CVTSD2SI_FIRST=364, + XED_IFORMFL_CVTSD2SI_LAST=367, + XED_IFORMFL_CVTSD2SS_FIRST=368, + XED_IFORMFL_CVTSD2SS_LAST=369, + XED_IFORMFL_CVTSI2SD_FIRST=370, + XED_IFORMFL_CVTSI2SD_LAST=373, + XED_IFORMFL_CVTSI2SS_FIRST=374, + XED_IFORMFL_CVTSI2SS_LAST=377, + XED_IFORMFL_CVTSS2SD_FIRST=378, + XED_IFORMFL_CVTSS2SD_LAST=379, + XED_IFORMFL_CVTSS2SI_FIRST=380, + XED_IFORMFL_CVTSS2SI_LAST=383, + XED_IFORMFL_CVTTPD2DQ_FIRST=384, + XED_IFORMFL_CVTTPD2DQ_LAST=385, + XED_IFORMFL_CVTTPD2PI_FIRST=386, + XED_IFORMFL_CVTTPD2PI_LAST=387, + XED_IFORMFL_CVTTPS2DQ_FIRST=388, + XED_IFORMFL_CVTTPS2DQ_LAST=389, + XED_IFORMFL_CVTTPS2PI_FIRST=390, + XED_IFORMFL_CVTTPS2PI_LAST=391, + XED_IFORMFL_CVTTSD2SI_FIRST=392, + XED_IFORMFL_CVTTSD2SI_LAST=395, + XED_IFORMFL_CVTTSS2SI_FIRST=396, + XED_IFORMFL_CVTTSS2SI_LAST=399, + XED_IFORMFL_CWD_FIRST=400, + XED_IFORMFL_CWD_LAST=400, + XED_IFORMFL_CWDE_FIRST=401, + XED_IFORMFL_CWDE_LAST=401, + XED_IFORMFL_DAA_FIRST=402, + XED_IFORMFL_DAA_LAST=402, + XED_IFORMFL_DAS_FIRST=403, + XED_IFORMFL_DAS_LAST=403, + XED_IFORMFL_DEC_FIRST=404, + XED_IFORMFL_DEC_LAST=408, + XED_IFORMFL_DEC_LOCK_FIRST=409, + XED_IFORMFL_DEC_LOCK_LAST=410, + XED_IFORMFL_DIV_FIRST=411, + XED_IFORMFL_DIV_LAST=414, + XED_IFORMFL_DIVPD_FIRST=415, + XED_IFORMFL_DIVPD_LAST=416, + XED_IFORMFL_DIVPS_FIRST=417, + XED_IFORMFL_DIVPS_LAST=418, + XED_IFORMFL_DIVSD_FIRST=419, + XED_IFORMFL_DIVSD_LAST=420, + XED_IFORMFL_DIVSS_FIRST=421, + XED_IFORMFL_DIVSS_LAST=422, + XED_IFORMFL_DPPD_FIRST=423, + XED_IFORMFL_DPPD_LAST=424, + XED_IFORMFL_DPPS_FIRST=425, + XED_IFORMFL_DPPS_LAST=426, + XED_IFORMFL_EMMS_FIRST=427, + XED_IFORMFL_EMMS_LAST=427, + XED_IFORMFL_ENCLS_FIRST=428, + XED_IFORMFL_ENCLS_LAST=428, + XED_IFORMFL_ENCLU_FIRST=429, + XED_IFORMFL_ENCLU_LAST=429, + XED_IFORMFL_ENCLV_FIRST=430, + XED_IFORMFL_ENCLV_LAST=430, + XED_IFORMFL_ENCODEKEY128_FIRST=431, + XED_IFORMFL_ENCODEKEY128_LAST=431, + XED_IFORMFL_ENCODEKEY256_FIRST=432, + XED_IFORMFL_ENCODEKEY256_LAST=432, + XED_IFORMFL_ENDBR32_FIRST=433, + XED_IFORMFL_ENDBR32_LAST=433, + XED_IFORMFL_ENDBR64_FIRST=434, + XED_IFORMFL_ENDBR64_LAST=434, + XED_IFORMFL_ENQCMD_FIRST=435, + XED_IFORMFL_ENQCMD_LAST=435, + XED_IFORMFL_ENQCMDS_FIRST=436, + XED_IFORMFL_ENQCMDS_LAST=436, + XED_IFORMFL_ENTER_FIRST=437, + XED_IFORMFL_ENTER_LAST=437, + XED_IFORMFL_EXTRACTPS_FIRST=438, + XED_IFORMFL_EXTRACTPS_LAST=439, + XED_IFORMFL_EXTRQ_FIRST=440, + XED_IFORMFL_EXTRQ_LAST=441, + XED_IFORMFL_F2XM1_FIRST=442, + XED_IFORMFL_F2XM1_LAST=442, + XED_IFORMFL_FABS_FIRST=443, + XED_IFORMFL_FABS_LAST=443, + XED_IFORMFL_FADD_FIRST=444, + XED_IFORMFL_FADD_LAST=447, + XED_IFORMFL_FADDP_FIRST=448, + XED_IFORMFL_FADDP_LAST=448, + XED_IFORMFL_FBLD_FIRST=449, + XED_IFORMFL_FBLD_LAST=449, + XED_IFORMFL_FBSTP_FIRST=450, + XED_IFORMFL_FBSTP_LAST=450, + XED_IFORMFL_FCHS_FIRST=451, + XED_IFORMFL_FCHS_LAST=451, + XED_IFORMFL_FCMOVB_FIRST=452, + XED_IFORMFL_FCMOVB_LAST=452, + XED_IFORMFL_FCMOVBE_FIRST=453, + XED_IFORMFL_FCMOVBE_LAST=453, + XED_IFORMFL_FCMOVE_FIRST=454, + XED_IFORMFL_FCMOVE_LAST=454, + XED_IFORMFL_FCMOVNB_FIRST=455, + XED_IFORMFL_FCMOVNB_LAST=455, + XED_IFORMFL_FCMOVNBE_FIRST=456, + XED_IFORMFL_FCMOVNBE_LAST=456, + XED_IFORMFL_FCMOVNE_FIRST=457, + XED_IFORMFL_FCMOVNE_LAST=457, + XED_IFORMFL_FCMOVNU_FIRST=458, + XED_IFORMFL_FCMOVNU_LAST=458, + XED_IFORMFL_FCMOVU_FIRST=459, + XED_IFORMFL_FCMOVU_LAST=459, + XED_IFORMFL_FCOM_FIRST=460, + XED_IFORMFL_FCOM_LAST=463, + XED_IFORMFL_FCOMI_FIRST=464, + XED_IFORMFL_FCOMI_LAST=464, + XED_IFORMFL_FCOMIP_FIRST=465, + XED_IFORMFL_FCOMIP_LAST=465, + XED_IFORMFL_FCOMP_FIRST=466, + XED_IFORMFL_FCOMP_LAST=470, + XED_IFORMFL_FCOMPP_FIRST=471, + XED_IFORMFL_FCOMPP_LAST=471, + XED_IFORMFL_FCOS_FIRST=472, + XED_IFORMFL_FCOS_LAST=472, + XED_IFORMFL_FDECSTP_FIRST=473, + XED_IFORMFL_FDECSTP_LAST=473, + XED_IFORMFL_FDISI8087_NOP_FIRST=474, + XED_IFORMFL_FDISI8087_NOP_LAST=474, + XED_IFORMFL_FDIV_FIRST=475, + XED_IFORMFL_FDIV_LAST=478, + XED_IFORMFL_FDIVP_FIRST=479, + XED_IFORMFL_FDIVP_LAST=479, + XED_IFORMFL_FDIVR_FIRST=480, + XED_IFORMFL_FDIVR_LAST=483, + XED_IFORMFL_FDIVRP_FIRST=484, + XED_IFORMFL_FDIVRP_LAST=484, + XED_IFORMFL_FEMMS_FIRST=485, + XED_IFORMFL_FEMMS_LAST=485, + XED_IFORMFL_FENI8087_NOP_FIRST=486, + XED_IFORMFL_FENI8087_NOP_LAST=486, + XED_IFORMFL_FFREE_FIRST=487, + XED_IFORMFL_FFREE_LAST=487, + XED_IFORMFL_FFREEP_FIRST=488, + XED_IFORMFL_FFREEP_LAST=488, + XED_IFORMFL_FIADD_FIRST=489, + XED_IFORMFL_FIADD_LAST=490, + XED_IFORMFL_FICOM_FIRST=491, + XED_IFORMFL_FICOM_LAST=492, + XED_IFORMFL_FICOMP_FIRST=493, + XED_IFORMFL_FICOMP_LAST=494, + XED_IFORMFL_FIDIV_FIRST=495, + XED_IFORMFL_FIDIV_LAST=496, + XED_IFORMFL_FIDIVR_FIRST=497, + XED_IFORMFL_FIDIVR_LAST=498, + XED_IFORMFL_FILD_FIRST=499, + XED_IFORMFL_FILD_LAST=501, + XED_IFORMFL_FIMUL_FIRST=502, + XED_IFORMFL_FIMUL_LAST=503, + XED_IFORMFL_FINCSTP_FIRST=504, + XED_IFORMFL_FINCSTP_LAST=504, + XED_IFORMFL_FIST_FIRST=505, + XED_IFORMFL_FIST_LAST=506, + XED_IFORMFL_FISTP_FIRST=507, + XED_IFORMFL_FISTP_LAST=509, + XED_IFORMFL_FISTTP_FIRST=510, + XED_IFORMFL_FISTTP_LAST=512, + XED_IFORMFL_FISUB_FIRST=513, + XED_IFORMFL_FISUB_LAST=514, + XED_IFORMFL_FISUBR_FIRST=515, + XED_IFORMFL_FISUBR_LAST=516, + XED_IFORMFL_FLD_FIRST=517, + XED_IFORMFL_FLD_LAST=520, + XED_IFORMFL_FLD1_FIRST=521, + XED_IFORMFL_FLD1_LAST=521, + XED_IFORMFL_FLDCW_FIRST=522, + XED_IFORMFL_FLDCW_LAST=522, + XED_IFORMFL_FLDENV_FIRST=523, + XED_IFORMFL_FLDENV_LAST=524, + XED_IFORMFL_FLDL2E_FIRST=525, + XED_IFORMFL_FLDL2E_LAST=525, + XED_IFORMFL_FLDL2T_FIRST=526, + XED_IFORMFL_FLDL2T_LAST=526, + XED_IFORMFL_FLDLG2_FIRST=527, + XED_IFORMFL_FLDLG2_LAST=527, + XED_IFORMFL_FLDLN2_FIRST=528, + XED_IFORMFL_FLDLN2_LAST=528, + XED_IFORMFL_FLDPI_FIRST=529, + XED_IFORMFL_FLDPI_LAST=529, + XED_IFORMFL_FLDZ_FIRST=530, + XED_IFORMFL_FLDZ_LAST=530, + XED_IFORMFL_FMUL_FIRST=531, + XED_IFORMFL_FMUL_LAST=534, + XED_IFORMFL_FMULP_FIRST=535, + XED_IFORMFL_FMULP_LAST=535, + XED_IFORMFL_FNCLEX_FIRST=536, + XED_IFORMFL_FNCLEX_LAST=536, + XED_IFORMFL_FNINIT_FIRST=537, + XED_IFORMFL_FNINIT_LAST=537, + XED_IFORMFL_FNOP_FIRST=538, + XED_IFORMFL_FNOP_LAST=538, + XED_IFORMFL_FNSAVE_FIRST=539, + XED_IFORMFL_FNSAVE_LAST=540, + XED_IFORMFL_FNSTCW_FIRST=541, + XED_IFORMFL_FNSTCW_LAST=541, + XED_IFORMFL_FNSTENV_FIRST=542, + XED_IFORMFL_FNSTENV_LAST=543, + XED_IFORMFL_FNSTSW_FIRST=544, + XED_IFORMFL_FNSTSW_LAST=545, + XED_IFORMFL_FPATAN_FIRST=546, + XED_IFORMFL_FPATAN_LAST=546, + XED_IFORMFL_FPREM_FIRST=547, + XED_IFORMFL_FPREM_LAST=547, + XED_IFORMFL_FPREM1_FIRST=548, + XED_IFORMFL_FPREM1_LAST=548, + XED_IFORMFL_FPTAN_FIRST=549, + XED_IFORMFL_FPTAN_LAST=549, + XED_IFORMFL_FRNDINT_FIRST=550, + XED_IFORMFL_FRNDINT_LAST=550, + XED_IFORMFL_FRSTOR_FIRST=551, + XED_IFORMFL_FRSTOR_LAST=552, + XED_IFORMFL_FSCALE_FIRST=553, + XED_IFORMFL_FSCALE_LAST=553, + XED_IFORMFL_FSETPM287_NOP_FIRST=554, + XED_IFORMFL_FSETPM287_NOP_LAST=554, + XED_IFORMFL_FSIN_FIRST=555, + XED_IFORMFL_FSIN_LAST=555, + XED_IFORMFL_FSINCOS_FIRST=556, + XED_IFORMFL_FSINCOS_LAST=556, + XED_IFORMFL_FSQRT_FIRST=557, + XED_IFORMFL_FSQRT_LAST=557, + XED_IFORMFL_FST_FIRST=558, + XED_IFORMFL_FST_LAST=560, + XED_IFORMFL_FSTP_FIRST=561, + XED_IFORMFL_FSTP_LAST=566, + XED_IFORMFL_FSTPNCE_FIRST=567, + XED_IFORMFL_FSTPNCE_LAST=567, + XED_IFORMFL_FSUB_FIRST=568, + XED_IFORMFL_FSUB_LAST=571, + XED_IFORMFL_FSUBP_FIRST=572, + XED_IFORMFL_FSUBP_LAST=572, + XED_IFORMFL_FSUBR_FIRST=573, + XED_IFORMFL_FSUBR_LAST=576, + XED_IFORMFL_FSUBRP_FIRST=577, + XED_IFORMFL_FSUBRP_LAST=577, + XED_IFORMFL_FTST_FIRST=578, + XED_IFORMFL_FTST_LAST=578, + XED_IFORMFL_FUCOM_FIRST=579, + XED_IFORMFL_FUCOM_LAST=579, + XED_IFORMFL_FUCOMI_FIRST=580, + XED_IFORMFL_FUCOMI_LAST=580, + XED_IFORMFL_FUCOMIP_FIRST=581, + XED_IFORMFL_FUCOMIP_LAST=581, + XED_IFORMFL_FUCOMP_FIRST=582, + XED_IFORMFL_FUCOMP_LAST=582, + XED_IFORMFL_FUCOMPP_FIRST=583, + XED_IFORMFL_FUCOMPP_LAST=583, + XED_IFORMFL_FWAIT_FIRST=584, + XED_IFORMFL_FWAIT_LAST=584, + XED_IFORMFL_FXAM_FIRST=585, + XED_IFORMFL_FXAM_LAST=585, + XED_IFORMFL_FXCH_FIRST=586, + XED_IFORMFL_FXCH_LAST=588, + XED_IFORMFL_FXRSTOR_FIRST=589, + XED_IFORMFL_FXRSTOR_LAST=589, + XED_IFORMFL_FXRSTOR64_FIRST=590, + XED_IFORMFL_FXRSTOR64_LAST=590, + XED_IFORMFL_FXSAVE_FIRST=591, + XED_IFORMFL_FXSAVE_LAST=591, + XED_IFORMFL_FXSAVE64_FIRST=592, + XED_IFORMFL_FXSAVE64_LAST=592, + XED_IFORMFL_FXTRACT_FIRST=593, + XED_IFORMFL_FXTRACT_LAST=593, + XED_IFORMFL_FYL2X_FIRST=594, + XED_IFORMFL_FYL2X_LAST=594, + XED_IFORMFL_FYL2XP1_FIRST=595, + XED_IFORMFL_FYL2XP1_LAST=595, + XED_IFORMFL_GETSEC_FIRST=596, + XED_IFORMFL_GETSEC_LAST=596, + XED_IFORMFL_GF2P8AFFINEINVQB_FIRST=597, + XED_IFORMFL_GF2P8AFFINEINVQB_LAST=598, + XED_IFORMFL_GF2P8AFFINEQB_FIRST=599, + XED_IFORMFL_GF2P8AFFINEQB_LAST=600, + XED_IFORMFL_GF2P8MULB_FIRST=601, + XED_IFORMFL_GF2P8MULB_LAST=602, + XED_IFORMFL_HADDPD_FIRST=603, + XED_IFORMFL_HADDPD_LAST=604, + XED_IFORMFL_HADDPS_FIRST=605, + XED_IFORMFL_HADDPS_LAST=606, + XED_IFORMFL_HLT_FIRST=607, + XED_IFORMFL_HLT_LAST=607, + XED_IFORMFL_HRESET_FIRST=608, + XED_IFORMFL_HRESET_LAST=608, + XED_IFORMFL_HSUBPD_FIRST=609, + XED_IFORMFL_HSUBPD_LAST=610, + XED_IFORMFL_HSUBPS_FIRST=611, + XED_IFORMFL_HSUBPS_LAST=612, + XED_IFORMFL_IDIV_FIRST=613, + XED_IFORMFL_IDIV_LAST=616, + XED_IFORMFL_IMUL_FIRST=617, + XED_IFORMFL_IMUL_LAST=626, + XED_IFORMFL_IN_FIRST=627, + XED_IFORMFL_IN_LAST=630, + XED_IFORMFL_INC_FIRST=631, + XED_IFORMFL_INC_LAST=635, + XED_IFORMFL_INCSSPD_FIRST=636, + XED_IFORMFL_INCSSPD_LAST=636, + XED_IFORMFL_INCSSPQ_FIRST=637, + XED_IFORMFL_INCSSPQ_LAST=637, + XED_IFORMFL_INC_LOCK_FIRST=638, + XED_IFORMFL_INC_LOCK_LAST=639, + XED_IFORMFL_INSB_FIRST=640, + XED_IFORMFL_INSB_LAST=640, + XED_IFORMFL_INSD_FIRST=641, + XED_IFORMFL_INSD_LAST=641, + XED_IFORMFL_INSERTPS_FIRST=642, + XED_IFORMFL_INSERTPS_LAST=643, + XED_IFORMFL_INSERTQ_FIRST=644, + XED_IFORMFL_INSERTQ_LAST=645, + XED_IFORMFL_INSW_FIRST=646, + XED_IFORMFL_INSW_LAST=646, + XED_IFORMFL_INT_FIRST=647, + XED_IFORMFL_INT_LAST=647, + XED_IFORMFL_INT1_FIRST=648, + XED_IFORMFL_INT1_LAST=648, + XED_IFORMFL_INT3_FIRST=649, + XED_IFORMFL_INT3_LAST=649, + XED_IFORMFL_INTO_FIRST=650, + XED_IFORMFL_INTO_LAST=650, + XED_IFORMFL_INVD_FIRST=651, + XED_IFORMFL_INVD_LAST=651, + XED_IFORMFL_INVEPT_FIRST=652, + XED_IFORMFL_INVEPT_LAST=653, + XED_IFORMFL_INVLPG_FIRST=654, + XED_IFORMFL_INVLPG_LAST=654, + XED_IFORMFL_INVLPGA_FIRST=655, + XED_IFORMFL_INVLPGA_LAST=655, + XED_IFORMFL_INVLPGB_FIRST=656, + XED_IFORMFL_INVLPGB_LAST=657, + XED_IFORMFL_INVPCID_FIRST=658, + XED_IFORMFL_INVPCID_LAST=659, + XED_IFORMFL_INVVPID_FIRST=660, + XED_IFORMFL_INVVPID_LAST=661, + XED_IFORMFL_IRET_FIRST=662, + XED_IFORMFL_IRET_LAST=662, + XED_IFORMFL_IRETD_FIRST=663, + XED_IFORMFL_IRETD_LAST=663, + XED_IFORMFL_IRETQ_FIRST=664, + XED_IFORMFL_IRETQ_LAST=664, + XED_IFORMFL_JB_FIRST=665, + XED_IFORMFL_JB_LAST=667, + XED_IFORMFL_JBE_FIRST=668, + XED_IFORMFL_JBE_LAST=670, + XED_IFORMFL_JCXZ_FIRST=671, + XED_IFORMFL_JCXZ_LAST=671, + XED_IFORMFL_JECXZ_FIRST=672, + XED_IFORMFL_JECXZ_LAST=672, + XED_IFORMFL_JL_FIRST=673, + XED_IFORMFL_JL_LAST=675, + XED_IFORMFL_JLE_FIRST=676, + XED_IFORMFL_JLE_LAST=678, + XED_IFORMFL_JMP_FIRST=679, + XED_IFORMFL_JMP_LAST=683, + XED_IFORMFL_JMP_FAR_FIRST=684, + XED_IFORMFL_JMP_FAR_LAST=685, + XED_IFORMFL_JNB_FIRST=686, + XED_IFORMFL_JNB_LAST=688, + XED_IFORMFL_JNBE_FIRST=689, + XED_IFORMFL_JNBE_LAST=691, + XED_IFORMFL_JNL_FIRST=692, + XED_IFORMFL_JNL_LAST=694, + XED_IFORMFL_JNLE_FIRST=695, + XED_IFORMFL_JNLE_LAST=697, + XED_IFORMFL_JNO_FIRST=698, + XED_IFORMFL_JNO_LAST=700, + XED_IFORMFL_JNP_FIRST=701, + XED_IFORMFL_JNP_LAST=703, + XED_IFORMFL_JNS_FIRST=704, + XED_IFORMFL_JNS_LAST=706, + XED_IFORMFL_JNZ_FIRST=707, + XED_IFORMFL_JNZ_LAST=709, + XED_IFORMFL_JO_FIRST=710, + XED_IFORMFL_JO_LAST=712, + XED_IFORMFL_JP_FIRST=713, + XED_IFORMFL_JP_LAST=715, + XED_IFORMFL_JRCXZ_FIRST=716, + XED_IFORMFL_JRCXZ_LAST=716, + XED_IFORMFL_JS_FIRST=717, + XED_IFORMFL_JS_LAST=719, + XED_IFORMFL_JZ_FIRST=720, + XED_IFORMFL_JZ_LAST=722, + XED_IFORMFL_KADDB_FIRST=723, + XED_IFORMFL_KADDB_LAST=723, + XED_IFORMFL_KADDD_FIRST=724, + XED_IFORMFL_KADDD_LAST=724, + XED_IFORMFL_KADDQ_FIRST=725, + XED_IFORMFL_KADDQ_LAST=725, + XED_IFORMFL_KADDW_FIRST=726, + XED_IFORMFL_KADDW_LAST=726, + XED_IFORMFL_KANDB_FIRST=727, + XED_IFORMFL_KANDB_LAST=727, + XED_IFORMFL_KANDD_FIRST=728, + XED_IFORMFL_KANDD_LAST=728, + XED_IFORMFL_KANDNB_FIRST=729, + XED_IFORMFL_KANDNB_LAST=729, + XED_IFORMFL_KANDND_FIRST=730, + XED_IFORMFL_KANDND_LAST=730, + XED_IFORMFL_KANDNQ_FIRST=731, + XED_IFORMFL_KANDNQ_LAST=731, + XED_IFORMFL_KANDNW_FIRST=732, + XED_IFORMFL_KANDNW_LAST=732, + XED_IFORMFL_KANDQ_FIRST=733, + XED_IFORMFL_KANDQ_LAST=733, + XED_IFORMFL_KANDW_FIRST=734, + XED_IFORMFL_KANDW_LAST=734, + XED_IFORMFL_KMOVB_FIRST=735, + XED_IFORMFL_KMOVB_LAST=739, + XED_IFORMFL_KMOVD_FIRST=740, + XED_IFORMFL_KMOVD_LAST=744, + XED_IFORMFL_KMOVQ_FIRST=745, + XED_IFORMFL_KMOVQ_LAST=749, + XED_IFORMFL_KMOVW_FIRST=750, + XED_IFORMFL_KMOVW_LAST=754, + XED_IFORMFL_KNOTB_FIRST=755, + XED_IFORMFL_KNOTB_LAST=755, + XED_IFORMFL_KNOTD_FIRST=756, + XED_IFORMFL_KNOTD_LAST=756, + XED_IFORMFL_KNOTQ_FIRST=757, + XED_IFORMFL_KNOTQ_LAST=757, + XED_IFORMFL_KNOTW_FIRST=758, + XED_IFORMFL_KNOTW_LAST=758, + XED_IFORMFL_KORB_FIRST=759, + XED_IFORMFL_KORB_LAST=759, + XED_IFORMFL_KORD_FIRST=760, + XED_IFORMFL_KORD_LAST=760, + XED_IFORMFL_KORQ_FIRST=761, + XED_IFORMFL_KORQ_LAST=761, + XED_IFORMFL_KORTESTB_FIRST=762, + XED_IFORMFL_KORTESTB_LAST=762, + XED_IFORMFL_KORTESTD_FIRST=763, + XED_IFORMFL_KORTESTD_LAST=763, + XED_IFORMFL_KORTESTQ_FIRST=764, + XED_IFORMFL_KORTESTQ_LAST=764, + XED_IFORMFL_KORTESTW_FIRST=765, + XED_IFORMFL_KORTESTW_LAST=765, + XED_IFORMFL_KORW_FIRST=766, + XED_IFORMFL_KORW_LAST=766, + XED_IFORMFL_KSHIFTLB_FIRST=767, + XED_IFORMFL_KSHIFTLB_LAST=767, + XED_IFORMFL_KSHIFTLD_FIRST=768, + XED_IFORMFL_KSHIFTLD_LAST=768, + XED_IFORMFL_KSHIFTLQ_FIRST=769, + XED_IFORMFL_KSHIFTLQ_LAST=769, + XED_IFORMFL_KSHIFTLW_FIRST=770, + XED_IFORMFL_KSHIFTLW_LAST=770, + XED_IFORMFL_KSHIFTRB_FIRST=771, + XED_IFORMFL_KSHIFTRB_LAST=771, + XED_IFORMFL_KSHIFTRD_FIRST=772, + XED_IFORMFL_KSHIFTRD_LAST=772, + XED_IFORMFL_KSHIFTRQ_FIRST=773, + XED_IFORMFL_KSHIFTRQ_LAST=773, + XED_IFORMFL_KSHIFTRW_FIRST=774, + XED_IFORMFL_KSHIFTRW_LAST=774, + XED_IFORMFL_KTESTB_FIRST=775, + XED_IFORMFL_KTESTB_LAST=775, + XED_IFORMFL_KTESTD_FIRST=776, + XED_IFORMFL_KTESTD_LAST=776, + XED_IFORMFL_KTESTQ_FIRST=777, + XED_IFORMFL_KTESTQ_LAST=777, + XED_IFORMFL_KTESTW_FIRST=778, + XED_IFORMFL_KTESTW_LAST=778, + XED_IFORMFL_KUNPCKBW_FIRST=779, + XED_IFORMFL_KUNPCKBW_LAST=779, + XED_IFORMFL_KUNPCKDQ_FIRST=780, + XED_IFORMFL_KUNPCKDQ_LAST=780, + XED_IFORMFL_KUNPCKWD_FIRST=781, + XED_IFORMFL_KUNPCKWD_LAST=781, + XED_IFORMFL_KXNORB_FIRST=782, + XED_IFORMFL_KXNORB_LAST=782, + XED_IFORMFL_KXNORD_FIRST=783, + XED_IFORMFL_KXNORD_LAST=783, + XED_IFORMFL_KXNORQ_FIRST=784, + XED_IFORMFL_KXNORQ_LAST=784, + XED_IFORMFL_KXNORW_FIRST=785, + XED_IFORMFL_KXNORW_LAST=785, + XED_IFORMFL_KXORB_FIRST=786, + XED_IFORMFL_KXORB_LAST=786, + XED_IFORMFL_KXORD_FIRST=787, + XED_IFORMFL_KXORD_LAST=787, + XED_IFORMFL_KXORQ_FIRST=788, + XED_IFORMFL_KXORQ_LAST=788, + XED_IFORMFL_KXORW_FIRST=789, + XED_IFORMFL_KXORW_LAST=789, + XED_IFORMFL_LAHF_FIRST=790, + XED_IFORMFL_LAHF_LAST=790, + XED_IFORMFL_LAR_FIRST=791, + XED_IFORMFL_LAR_LAST=792, + XED_IFORMFL_LDDQU_FIRST=793, + XED_IFORMFL_LDDQU_LAST=793, + XED_IFORMFL_LDMXCSR_FIRST=794, + XED_IFORMFL_LDMXCSR_LAST=794, + XED_IFORMFL_LDS_FIRST=795, + XED_IFORMFL_LDS_LAST=795, + XED_IFORMFL_LDTILECFG_FIRST=796, + XED_IFORMFL_LDTILECFG_LAST=796, + XED_IFORMFL_LEA_FIRST=797, + XED_IFORMFL_LEA_LAST=797, + XED_IFORMFL_LEAVE_FIRST=798, + XED_IFORMFL_LEAVE_LAST=798, + XED_IFORMFL_LES_FIRST=799, + XED_IFORMFL_LES_LAST=799, + XED_IFORMFL_LFENCE_FIRST=800, + XED_IFORMFL_LFENCE_LAST=800, + XED_IFORMFL_LFS_FIRST=801, + XED_IFORMFL_LFS_LAST=801, + XED_IFORMFL_LGDT_FIRST=802, + XED_IFORMFL_LGDT_LAST=803, + XED_IFORMFL_LGS_FIRST=804, + XED_IFORMFL_LGS_LAST=804, + XED_IFORMFL_LIDT_FIRST=805, + XED_IFORMFL_LIDT_LAST=806, + XED_IFORMFL_LLDT_FIRST=807, + XED_IFORMFL_LLDT_LAST=808, + XED_IFORMFL_LLWPCB_FIRST=809, + XED_IFORMFL_LLWPCB_LAST=809, + XED_IFORMFL_LMSW_FIRST=810, + XED_IFORMFL_LMSW_LAST=811, + XED_IFORMFL_LOADIWKEY_FIRST=812, + XED_IFORMFL_LOADIWKEY_LAST=812, + XED_IFORMFL_LODSB_FIRST=813, + XED_IFORMFL_LODSB_LAST=813, + XED_IFORMFL_LODSD_FIRST=814, + XED_IFORMFL_LODSD_LAST=814, + XED_IFORMFL_LODSQ_FIRST=815, + XED_IFORMFL_LODSQ_LAST=815, + XED_IFORMFL_LODSW_FIRST=816, + XED_IFORMFL_LODSW_LAST=816, + XED_IFORMFL_LOOP_FIRST=817, + XED_IFORMFL_LOOP_LAST=817, + XED_IFORMFL_LOOPE_FIRST=818, + XED_IFORMFL_LOOPE_LAST=818, + XED_IFORMFL_LOOPNE_FIRST=819, + XED_IFORMFL_LOOPNE_LAST=819, + XED_IFORMFL_LSL_FIRST=820, + XED_IFORMFL_LSL_LAST=821, + XED_IFORMFL_LSS_FIRST=822, + XED_IFORMFL_LSS_LAST=822, + XED_IFORMFL_LTR_FIRST=823, + XED_IFORMFL_LTR_LAST=824, + XED_IFORMFL_LWPINS_FIRST=825, + XED_IFORMFL_LWPINS_LAST=826, + XED_IFORMFL_LWPVAL_FIRST=827, + XED_IFORMFL_LWPVAL_LAST=828, + XED_IFORMFL_LZCNT_FIRST=829, + XED_IFORMFL_LZCNT_LAST=830, + XED_IFORMFL_MASKMOVDQU_FIRST=831, + XED_IFORMFL_MASKMOVDQU_LAST=831, + XED_IFORMFL_MASKMOVQ_FIRST=832, + XED_IFORMFL_MASKMOVQ_LAST=832, + XED_IFORMFL_MAXPD_FIRST=833, + XED_IFORMFL_MAXPD_LAST=834, + XED_IFORMFL_MAXPS_FIRST=835, + XED_IFORMFL_MAXPS_LAST=836, + XED_IFORMFL_MAXSD_FIRST=837, + XED_IFORMFL_MAXSD_LAST=838, + XED_IFORMFL_MAXSS_FIRST=839, + XED_IFORMFL_MAXSS_LAST=840, + XED_IFORMFL_MCOMMIT_FIRST=841, + XED_IFORMFL_MCOMMIT_LAST=841, + XED_IFORMFL_MFENCE_FIRST=842, + XED_IFORMFL_MFENCE_LAST=842, + XED_IFORMFL_MINPD_FIRST=843, + XED_IFORMFL_MINPD_LAST=844, + XED_IFORMFL_MINPS_FIRST=845, + XED_IFORMFL_MINPS_LAST=846, + XED_IFORMFL_MINSD_FIRST=847, + XED_IFORMFL_MINSD_LAST=848, + XED_IFORMFL_MINSS_FIRST=849, + XED_IFORMFL_MINSS_LAST=850, + XED_IFORMFL_MONITOR_FIRST=851, + XED_IFORMFL_MONITOR_LAST=851, + XED_IFORMFL_MONITORX_FIRST=852, + XED_IFORMFL_MONITORX_LAST=852, + XED_IFORMFL_MOV_FIRST=853, + XED_IFORMFL_MOV_LAST=874, + XED_IFORMFL_MOVAPD_FIRST=875, + XED_IFORMFL_MOVAPD_LAST=878, + XED_IFORMFL_MOVAPS_FIRST=879, + XED_IFORMFL_MOVAPS_LAST=882, + XED_IFORMFL_MOVBE_FIRST=883, + XED_IFORMFL_MOVBE_LAST=884, + XED_IFORMFL_MOVD_FIRST=885, + XED_IFORMFL_MOVD_LAST=892, + XED_IFORMFL_MOVDDUP_FIRST=893, + XED_IFORMFL_MOVDDUP_LAST=894, + XED_IFORMFL_MOVDIR64B_FIRST=895, + XED_IFORMFL_MOVDIR64B_LAST=895, + XED_IFORMFL_MOVDIRI_FIRST=896, + XED_IFORMFL_MOVDIRI_LAST=897, + XED_IFORMFL_MOVDQ2Q_FIRST=898, + XED_IFORMFL_MOVDQ2Q_LAST=898, + XED_IFORMFL_MOVDQA_FIRST=899, + XED_IFORMFL_MOVDQA_LAST=902, + XED_IFORMFL_MOVDQU_FIRST=903, + XED_IFORMFL_MOVDQU_LAST=906, + XED_IFORMFL_MOVHLPS_FIRST=907, + XED_IFORMFL_MOVHLPS_LAST=907, + XED_IFORMFL_MOVHPD_FIRST=908, + XED_IFORMFL_MOVHPD_LAST=909, + XED_IFORMFL_MOVHPS_FIRST=910, + XED_IFORMFL_MOVHPS_LAST=911, + XED_IFORMFL_MOVLHPS_FIRST=912, + XED_IFORMFL_MOVLHPS_LAST=912, + XED_IFORMFL_MOVLPD_FIRST=913, + XED_IFORMFL_MOVLPD_LAST=914, + XED_IFORMFL_MOVLPS_FIRST=915, + XED_IFORMFL_MOVLPS_LAST=916, + XED_IFORMFL_MOVMSKPD_FIRST=917, + XED_IFORMFL_MOVMSKPD_LAST=917, + XED_IFORMFL_MOVMSKPS_FIRST=918, + XED_IFORMFL_MOVMSKPS_LAST=918, + XED_IFORMFL_MOVNTDQ_FIRST=919, + XED_IFORMFL_MOVNTDQ_LAST=919, + XED_IFORMFL_MOVNTDQA_FIRST=920, + XED_IFORMFL_MOVNTDQA_LAST=920, + XED_IFORMFL_MOVNTI_FIRST=921, + XED_IFORMFL_MOVNTI_LAST=922, + XED_IFORMFL_MOVNTPD_FIRST=923, + XED_IFORMFL_MOVNTPD_LAST=923, + XED_IFORMFL_MOVNTPS_FIRST=924, + XED_IFORMFL_MOVNTPS_LAST=924, + XED_IFORMFL_MOVNTQ_FIRST=925, + XED_IFORMFL_MOVNTQ_LAST=925, + XED_IFORMFL_MOVNTSD_FIRST=926, + XED_IFORMFL_MOVNTSD_LAST=926, + XED_IFORMFL_MOVNTSS_FIRST=927, + XED_IFORMFL_MOVNTSS_LAST=927, + XED_IFORMFL_MOVQ_FIRST=928, + XED_IFORMFL_MOVQ_LAST=943, + XED_IFORMFL_MOVQ2DQ_FIRST=944, + XED_IFORMFL_MOVQ2DQ_LAST=944, + XED_IFORMFL_MOVSB_FIRST=945, + XED_IFORMFL_MOVSB_LAST=945, + XED_IFORMFL_MOVSD_FIRST=946, + XED_IFORMFL_MOVSD_LAST=946, + XED_IFORMFL_MOVSD_XMM_FIRST=947, + XED_IFORMFL_MOVSD_XMM_LAST=950, + XED_IFORMFL_MOVSHDUP_FIRST=951, + XED_IFORMFL_MOVSHDUP_LAST=952, + XED_IFORMFL_MOVSLDUP_FIRST=953, + XED_IFORMFL_MOVSLDUP_LAST=954, + XED_IFORMFL_MOVSQ_FIRST=955, + XED_IFORMFL_MOVSQ_LAST=955, + XED_IFORMFL_MOVSS_FIRST=956, + XED_IFORMFL_MOVSS_LAST=959, + XED_IFORMFL_MOVSW_FIRST=960, + XED_IFORMFL_MOVSW_LAST=960, + XED_IFORMFL_MOVSX_FIRST=961, + XED_IFORMFL_MOVSX_LAST=964, + XED_IFORMFL_MOVSXD_FIRST=965, + XED_IFORMFL_MOVSXD_LAST=966, + XED_IFORMFL_MOVUPD_FIRST=967, + XED_IFORMFL_MOVUPD_LAST=970, + XED_IFORMFL_MOVUPS_FIRST=971, + XED_IFORMFL_MOVUPS_LAST=974, + XED_IFORMFL_MOVZX_FIRST=975, + XED_IFORMFL_MOVZX_LAST=978, + XED_IFORMFL_MOV_CR_FIRST=979, + XED_IFORMFL_MOV_CR_LAST=982, + XED_IFORMFL_MOV_DR_FIRST=983, + XED_IFORMFL_MOV_DR_LAST=986, + XED_IFORMFL_MPSADBW_FIRST=987, + XED_IFORMFL_MPSADBW_LAST=988, + XED_IFORMFL_MUL_FIRST=989, + XED_IFORMFL_MUL_LAST=992, + XED_IFORMFL_MULPD_FIRST=993, + XED_IFORMFL_MULPD_LAST=994, + XED_IFORMFL_MULPS_FIRST=995, + XED_IFORMFL_MULPS_LAST=996, + XED_IFORMFL_MULSD_FIRST=997, + XED_IFORMFL_MULSD_LAST=998, + XED_IFORMFL_MULSS_FIRST=999, + XED_IFORMFL_MULSS_LAST=1000, + XED_IFORMFL_MULX_FIRST=1001, + XED_IFORMFL_MULX_LAST=1004, + XED_IFORMFL_MWAIT_FIRST=1005, + XED_IFORMFL_MWAIT_LAST=1005, + XED_IFORMFL_MWAITX_FIRST=1006, + XED_IFORMFL_MWAITX_LAST=1006, + XED_IFORMFL_NEG_FIRST=1007, + XED_IFORMFL_NEG_LAST=1010, + XED_IFORMFL_NEG_LOCK_FIRST=1011, + XED_IFORMFL_NEG_LOCK_LAST=1012, + XED_IFORMFL_NOP_FIRST=1013, + XED_IFORMFL_NOP_LAST=1040, + XED_IFORMFL_NOT_FIRST=1041, + XED_IFORMFL_NOT_LAST=1044, + XED_IFORMFL_NOT_LOCK_FIRST=1045, + XED_IFORMFL_NOT_LOCK_LAST=1046, + XED_IFORMFL_OR_FIRST=1047, + XED_IFORMFL_OR_LAST=1064, + XED_IFORMFL_ORPD_FIRST=1065, + XED_IFORMFL_ORPD_LAST=1066, + XED_IFORMFL_ORPS_FIRST=1067, + XED_IFORMFL_ORPS_LAST=1068, + XED_IFORMFL_OR_LOCK_FIRST=1069, + XED_IFORMFL_OR_LOCK_LAST=1074, + XED_IFORMFL_OUT_FIRST=1075, + XED_IFORMFL_OUT_LAST=1078, + XED_IFORMFL_OUTSB_FIRST=1079, + XED_IFORMFL_OUTSB_LAST=1079, + XED_IFORMFL_OUTSD_FIRST=1080, + XED_IFORMFL_OUTSD_LAST=1080, + XED_IFORMFL_OUTSW_FIRST=1081, + XED_IFORMFL_OUTSW_LAST=1081, + XED_IFORMFL_PABSB_FIRST=1082, + XED_IFORMFL_PABSB_LAST=1085, + XED_IFORMFL_PABSD_FIRST=1086, + XED_IFORMFL_PABSD_LAST=1089, + XED_IFORMFL_PABSW_FIRST=1090, + XED_IFORMFL_PABSW_LAST=1093, + XED_IFORMFL_PACKSSDW_FIRST=1094, + XED_IFORMFL_PACKSSDW_LAST=1097, + XED_IFORMFL_PACKSSWB_FIRST=1098, + XED_IFORMFL_PACKSSWB_LAST=1101, + XED_IFORMFL_PACKUSDW_FIRST=1102, + XED_IFORMFL_PACKUSDW_LAST=1103, + XED_IFORMFL_PACKUSWB_FIRST=1104, + XED_IFORMFL_PACKUSWB_LAST=1107, + XED_IFORMFL_PADDB_FIRST=1108, + XED_IFORMFL_PADDB_LAST=1111, + XED_IFORMFL_PADDD_FIRST=1112, + XED_IFORMFL_PADDD_LAST=1115, + XED_IFORMFL_PADDQ_FIRST=1116, + XED_IFORMFL_PADDQ_LAST=1119, + XED_IFORMFL_PADDSB_FIRST=1120, + XED_IFORMFL_PADDSB_LAST=1123, + XED_IFORMFL_PADDSW_FIRST=1124, + XED_IFORMFL_PADDSW_LAST=1127, + XED_IFORMFL_PADDUSB_FIRST=1128, + XED_IFORMFL_PADDUSB_LAST=1131, + XED_IFORMFL_PADDUSW_FIRST=1132, + XED_IFORMFL_PADDUSW_LAST=1135, + XED_IFORMFL_PADDW_FIRST=1136, + XED_IFORMFL_PADDW_LAST=1139, + XED_IFORMFL_PALIGNR_FIRST=1140, + XED_IFORMFL_PALIGNR_LAST=1143, + XED_IFORMFL_PAND_FIRST=1144, + XED_IFORMFL_PAND_LAST=1147, + XED_IFORMFL_PANDN_FIRST=1148, + XED_IFORMFL_PANDN_LAST=1151, + XED_IFORMFL_PAUSE_FIRST=1152, + XED_IFORMFL_PAUSE_LAST=1152, + XED_IFORMFL_PAVGB_FIRST=1153, + XED_IFORMFL_PAVGB_LAST=1156, + XED_IFORMFL_PAVGUSB_FIRST=1157, + XED_IFORMFL_PAVGUSB_LAST=1158, + XED_IFORMFL_PAVGW_FIRST=1159, + XED_IFORMFL_PAVGW_LAST=1162, + XED_IFORMFL_PBLENDVB_FIRST=1163, + XED_IFORMFL_PBLENDVB_LAST=1164, + XED_IFORMFL_PBLENDW_FIRST=1165, + XED_IFORMFL_PBLENDW_LAST=1166, + XED_IFORMFL_PCLMULQDQ_FIRST=1167, + XED_IFORMFL_PCLMULQDQ_LAST=1168, + XED_IFORMFL_PCMPEQB_FIRST=1169, + XED_IFORMFL_PCMPEQB_LAST=1172, + XED_IFORMFL_PCMPEQD_FIRST=1173, + XED_IFORMFL_PCMPEQD_LAST=1176, + XED_IFORMFL_PCMPEQQ_FIRST=1177, + XED_IFORMFL_PCMPEQQ_LAST=1178, + XED_IFORMFL_PCMPEQW_FIRST=1179, + XED_IFORMFL_PCMPEQW_LAST=1182, + XED_IFORMFL_PCMPESTRI_FIRST=1183, + XED_IFORMFL_PCMPESTRI_LAST=1184, + XED_IFORMFL_PCMPESTRI64_FIRST=1185, + XED_IFORMFL_PCMPESTRI64_LAST=1186, + XED_IFORMFL_PCMPESTRM_FIRST=1187, + XED_IFORMFL_PCMPESTRM_LAST=1188, + XED_IFORMFL_PCMPESTRM64_FIRST=1189, + XED_IFORMFL_PCMPESTRM64_LAST=1190, + XED_IFORMFL_PCMPGTB_FIRST=1191, + XED_IFORMFL_PCMPGTB_LAST=1194, + XED_IFORMFL_PCMPGTD_FIRST=1195, + XED_IFORMFL_PCMPGTD_LAST=1198, + XED_IFORMFL_PCMPGTQ_FIRST=1199, + XED_IFORMFL_PCMPGTQ_LAST=1200, + XED_IFORMFL_PCMPGTW_FIRST=1201, + XED_IFORMFL_PCMPGTW_LAST=1204, + XED_IFORMFL_PCMPISTRI_FIRST=1205, + XED_IFORMFL_PCMPISTRI_LAST=1206, + XED_IFORMFL_PCMPISTRI64_FIRST=1207, + XED_IFORMFL_PCMPISTRI64_LAST=1208, + XED_IFORMFL_PCMPISTRM_FIRST=1209, + XED_IFORMFL_PCMPISTRM_LAST=1210, + XED_IFORMFL_PCONFIG_FIRST=1211, + XED_IFORMFL_PCONFIG_LAST=1212, + XED_IFORMFL_PDEP_FIRST=1213, + XED_IFORMFL_PDEP_LAST=1216, + XED_IFORMFL_PEXT_FIRST=1217, + XED_IFORMFL_PEXT_LAST=1220, + XED_IFORMFL_PEXTRB_FIRST=1221, + XED_IFORMFL_PEXTRB_LAST=1222, + XED_IFORMFL_PEXTRD_FIRST=1223, + XED_IFORMFL_PEXTRD_LAST=1224, + XED_IFORMFL_PEXTRQ_FIRST=1225, + XED_IFORMFL_PEXTRQ_LAST=1226, + XED_IFORMFL_PEXTRW_FIRST=1227, + XED_IFORMFL_PEXTRW_LAST=1228, + XED_IFORMFL_PEXTRW_SSE4_FIRST=1229, + XED_IFORMFL_PEXTRW_SSE4_LAST=1230, + XED_IFORMFL_PF2ID_FIRST=1231, + XED_IFORMFL_PF2ID_LAST=1232, + XED_IFORMFL_PF2IW_FIRST=1233, + XED_IFORMFL_PF2IW_LAST=1234, + XED_IFORMFL_PFACC_FIRST=1235, + XED_IFORMFL_PFACC_LAST=1236, + XED_IFORMFL_PFADD_FIRST=1237, + XED_IFORMFL_PFADD_LAST=1238, + XED_IFORMFL_PFCMPEQ_FIRST=1239, + XED_IFORMFL_PFCMPEQ_LAST=1240, + XED_IFORMFL_PFCMPGE_FIRST=1241, + XED_IFORMFL_PFCMPGE_LAST=1242, + XED_IFORMFL_PFCMPGT_FIRST=1243, + XED_IFORMFL_PFCMPGT_LAST=1244, + XED_IFORMFL_PFMAX_FIRST=1245, + XED_IFORMFL_PFMAX_LAST=1246, + XED_IFORMFL_PFMIN_FIRST=1247, + XED_IFORMFL_PFMIN_LAST=1248, + XED_IFORMFL_PFMUL_FIRST=1249, + XED_IFORMFL_PFMUL_LAST=1250, + XED_IFORMFL_PFNACC_FIRST=1251, + XED_IFORMFL_PFNACC_LAST=1252, + XED_IFORMFL_PFPNACC_FIRST=1253, + XED_IFORMFL_PFPNACC_LAST=1254, + XED_IFORMFL_PFRCP_FIRST=1255, + XED_IFORMFL_PFRCP_LAST=1256, + XED_IFORMFL_PFRCPIT1_FIRST=1257, + XED_IFORMFL_PFRCPIT1_LAST=1258, + XED_IFORMFL_PFRCPIT2_FIRST=1259, + XED_IFORMFL_PFRCPIT2_LAST=1260, + XED_IFORMFL_PFRSQIT1_FIRST=1261, + XED_IFORMFL_PFRSQIT1_LAST=1262, + XED_IFORMFL_PFRSQRT_FIRST=1263, + XED_IFORMFL_PFRSQRT_LAST=1264, + XED_IFORMFL_PFSUB_FIRST=1265, + XED_IFORMFL_PFSUB_LAST=1266, + XED_IFORMFL_PFSUBR_FIRST=1267, + XED_IFORMFL_PFSUBR_LAST=1268, + XED_IFORMFL_PHADDD_FIRST=1269, + XED_IFORMFL_PHADDD_LAST=1272, + XED_IFORMFL_PHADDSW_FIRST=1273, + XED_IFORMFL_PHADDSW_LAST=1276, + XED_IFORMFL_PHADDW_FIRST=1277, + XED_IFORMFL_PHADDW_LAST=1280, + XED_IFORMFL_PHMINPOSUW_FIRST=1281, + XED_IFORMFL_PHMINPOSUW_LAST=1282, + XED_IFORMFL_PHSUBD_FIRST=1283, + XED_IFORMFL_PHSUBD_LAST=1286, + XED_IFORMFL_PHSUBSW_FIRST=1287, + XED_IFORMFL_PHSUBSW_LAST=1290, + XED_IFORMFL_PHSUBW_FIRST=1291, + XED_IFORMFL_PHSUBW_LAST=1294, + XED_IFORMFL_PI2FD_FIRST=1295, + XED_IFORMFL_PI2FD_LAST=1296, + XED_IFORMFL_PI2FW_FIRST=1297, + XED_IFORMFL_PI2FW_LAST=1298, + XED_IFORMFL_PINSRB_FIRST=1299, + XED_IFORMFL_PINSRB_LAST=1300, + XED_IFORMFL_PINSRD_FIRST=1301, + XED_IFORMFL_PINSRD_LAST=1302, + XED_IFORMFL_PINSRQ_FIRST=1303, + XED_IFORMFL_PINSRQ_LAST=1304, + XED_IFORMFL_PINSRW_FIRST=1305, + XED_IFORMFL_PINSRW_LAST=1308, + XED_IFORMFL_PMADDUBSW_FIRST=1309, + XED_IFORMFL_PMADDUBSW_LAST=1312, + XED_IFORMFL_PMADDWD_FIRST=1313, + XED_IFORMFL_PMADDWD_LAST=1316, + XED_IFORMFL_PMAXSB_FIRST=1317, + XED_IFORMFL_PMAXSB_LAST=1318, + XED_IFORMFL_PMAXSD_FIRST=1319, + XED_IFORMFL_PMAXSD_LAST=1320, + XED_IFORMFL_PMAXSW_FIRST=1321, + XED_IFORMFL_PMAXSW_LAST=1324, + XED_IFORMFL_PMAXUB_FIRST=1325, + XED_IFORMFL_PMAXUB_LAST=1328, + XED_IFORMFL_PMAXUD_FIRST=1329, + XED_IFORMFL_PMAXUD_LAST=1330, + XED_IFORMFL_PMAXUW_FIRST=1331, + XED_IFORMFL_PMAXUW_LAST=1332, + XED_IFORMFL_PMINSB_FIRST=1333, + XED_IFORMFL_PMINSB_LAST=1334, + XED_IFORMFL_PMINSD_FIRST=1335, + XED_IFORMFL_PMINSD_LAST=1336, + XED_IFORMFL_PMINSW_FIRST=1337, + XED_IFORMFL_PMINSW_LAST=1340, + XED_IFORMFL_PMINUB_FIRST=1341, + XED_IFORMFL_PMINUB_LAST=1344, + XED_IFORMFL_PMINUD_FIRST=1345, + XED_IFORMFL_PMINUD_LAST=1346, + XED_IFORMFL_PMINUW_FIRST=1347, + XED_IFORMFL_PMINUW_LAST=1348, + XED_IFORMFL_PMOVMSKB_FIRST=1349, + XED_IFORMFL_PMOVMSKB_LAST=1350, + XED_IFORMFL_PMOVSXBD_FIRST=1351, + XED_IFORMFL_PMOVSXBD_LAST=1352, + XED_IFORMFL_PMOVSXBQ_FIRST=1353, + XED_IFORMFL_PMOVSXBQ_LAST=1354, + XED_IFORMFL_PMOVSXBW_FIRST=1355, + XED_IFORMFL_PMOVSXBW_LAST=1356, + XED_IFORMFL_PMOVSXDQ_FIRST=1357, + XED_IFORMFL_PMOVSXDQ_LAST=1358, + XED_IFORMFL_PMOVSXWD_FIRST=1359, + XED_IFORMFL_PMOVSXWD_LAST=1360, + XED_IFORMFL_PMOVSXWQ_FIRST=1361, + XED_IFORMFL_PMOVSXWQ_LAST=1362, + XED_IFORMFL_PMOVZXBD_FIRST=1363, + XED_IFORMFL_PMOVZXBD_LAST=1364, + XED_IFORMFL_PMOVZXBQ_FIRST=1365, + XED_IFORMFL_PMOVZXBQ_LAST=1366, + XED_IFORMFL_PMOVZXBW_FIRST=1367, + XED_IFORMFL_PMOVZXBW_LAST=1368, + XED_IFORMFL_PMOVZXDQ_FIRST=1369, + XED_IFORMFL_PMOVZXDQ_LAST=1370, + XED_IFORMFL_PMOVZXWD_FIRST=1371, + XED_IFORMFL_PMOVZXWD_LAST=1372, + XED_IFORMFL_PMOVZXWQ_FIRST=1373, + XED_IFORMFL_PMOVZXWQ_LAST=1374, + XED_IFORMFL_PMULDQ_FIRST=1375, + XED_IFORMFL_PMULDQ_LAST=1376, + XED_IFORMFL_PMULHRSW_FIRST=1377, + XED_IFORMFL_PMULHRSW_LAST=1380, + XED_IFORMFL_PMULHRW_FIRST=1381, + XED_IFORMFL_PMULHRW_LAST=1382, + XED_IFORMFL_PMULHUW_FIRST=1383, + XED_IFORMFL_PMULHUW_LAST=1386, + XED_IFORMFL_PMULHW_FIRST=1387, + XED_IFORMFL_PMULHW_LAST=1390, + XED_IFORMFL_PMULLD_FIRST=1391, + XED_IFORMFL_PMULLD_LAST=1392, + XED_IFORMFL_PMULLW_FIRST=1393, + XED_IFORMFL_PMULLW_LAST=1396, + XED_IFORMFL_PMULUDQ_FIRST=1397, + XED_IFORMFL_PMULUDQ_LAST=1400, + XED_IFORMFL_POP_FIRST=1401, + XED_IFORMFL_POP_LAST=1408, + XED_IFORMFL_POPA_FIRST=1409, + XED_IFORMFL_POPA_LAST=1409, + XED_IFORMFL_POPAD_FIRST=1410, + XED_IFORMFL_POPAD_LAST=1410, + XED_IFORMFL_POPCNT_FIRST=1411, + XED_IFORMFL_POPCNT_LAST=1412, + XED_IFORMFL_POPF_FIRST=1413, + XED_IFORMFL_POPF_LAST=1413, + XED_IFORMFL_POPFD_FIRST=1414, + XED_IFORMFL_POPFD_LAST=1414, + XED_IFORMFL_POPFQ_FIRST=1415, + XED_IFORMFL_POPFQ_LAST=1415, + XED_IFORMFL_POR_FIRST=1416, + XED_IFORMFL_POR_LAST=1419, + XED_IFORMFL_PREFETCHNTA_FIRST=1420, + XED_IFORMFL_PREFETCHNTA_LAST=1420, + XED_IFORMFL_PREFETCHT0_FIRST=1421, + XED_IFORMFL_PREFETCHT0_LAST=1421, + XED_IFORMFL_PREFETCHT1_FIRST=1422, + XED_IFORMFL_PREFETCHT1_LAST=1422, + XED_IFORMFL_PREFETCHT2_FIRST=1423, + XED_IFORMFL_PREFETCHT2_LAST=1423, + XED_IFORMFL_PREFETCHW_FIRST=1424, + XED_IFORMFL_PREFETCHW_LAST=1425, + XED_IFORMFL_PREFETCHWT1_FIRST=1426, + XED_IFORMFL_PREFETCHWT1_LAST=1426, + XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST=1427, + XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST=1427, + XED_IFORMFL_PREFETCH_RESERVED_FIRST=1428, + XED_IFORMFL_PREFETCH_RESERVED_LAST=1431, + XED_IFORMFL_PSADBW_FIRST=1432, + XED_IFORMFL_PSADBW_LAST=1435, + XED_IFORMFL_PSHUFB_FIRST=1436, + XED_IFORMFL_PSHUFB_LAST=1439, + XED_IFORMFL_PSHUFD_FIRST=1440, + XED_IFORMFL_PSHUFD_LAST=1441, + XED_IFORMFL_PSHUFHW_FIRST=1442, + XED_IFORMFL_PSHUFHW_LAST=1443, + XED_IFORMFL_PSHUFLW_FIRST=1444, + XED_IFORMFL_PSHUFLW_LAST=1445, + XED_IFORMFL_PSHUFW_FIRST=1446, + XED_IFORMFL_PSHUFW_LAST=1447, + XED_IFORMFL_PSIGNB_FIRST=1448, + XED_IFORMFL_PSIGNB_LAST=1451, + XED_IFORMFL_PSIGND_FIRST=1452, + XED_IFORMFL_PSIGND_LAST=1455, + XED_IFORMFL_PSIGNW_FIRST=1456, + XED_IFORMFL_PSIGNW_LAST=1459, + XED_IFORMFL_PSLLD_FIRST=1460, + XED_IFORMFL_PSLLD_LAST=1465, + XED_IFORMFL_PSLLDQ_FIRST=1466, + XED_IFORMFL_PSLLDQ_LAST=1466, + XED_IFORMFL_PSLLQ_FIRST=1467, + XED_IFORMFL_PSLLQ_LAST=1472, + XED_IFORMFL_PSLLW_FIRST=1473, + XED_IFORMFL_PSLLW_LAST=1478, + XED_IFORMFL_PSMASH_FIRST=1479, + XED_IFORMFL_PSMASH_LAST=1479, + XED_IFORMFL_PSRAD_FIRST=1480, + XED_IFORMFL_PSRAD_LAST=1485, + XED_IFORMFL_PSRAW_FIRST=1486, + XED_IFORMFL_PSRAW_LAST=1491, + XED_IFORMFL_PSRLD_FIRST=1492, + XED_IFORMFL_PSRLD_LAST=1497, + XED_IFORMFL_PSRLDQ_FIRST=1498, + XED_IFORMFL_PSRLDQ_LAST=1498, + XED_IFORMFL_PSRLQ_FIRST=1499, + XED_IFORMFL_PSRLQ_LAST=1504, + XED_IFORMFL_PSRLW_FIRST=1505, + XED_IFORMFL_PSRLW_LAST=1510, + XED_IFORMFL_PSUBB_FIRST=1511, + XED_IFORMFL_PSUBB_LAST=1514, + XED_IFORMFL_PSUBD_FIRST=1515, + XED_IFORMFL_PSUBD_LAST=1518, + XED_IFORMFL_PSUBQ_FIRST=1519, + XED_IFORMFL_PSUBQ_LAST=1522, + XED_IFORMFL_PSUBSB_FIRST=1523, + XED_IFORMFL_PSUBSB_LAST=1526, + XED_IFORMFL_PSUBSW_FIRST=1527, + XED_IFORMFL_PSUBSW_LAST=1530, + XED_IFORMFL_PSUBUSB_FIRST=1531, + XED_IFORMFL_PSUBUSB_LAST=1534, + XED_IFORMFL_PSUBUSW_FIRST=1535, + XED_IFORMFL_PSUBUSW_LAST=1538, + XED_IFORMFL_PSUBW_FIRST=1539, + XED_IFORMFL_PSUBW_LAST=1542, + XED_IFORMFL_PSWAPD_FIRST=1543, + XED_IFORMFL_PSWAPD_LAST=1544, + XED_IFORMFL_PTEST_FIRST=1545, + XED_IFORMFL_PTEST_LAST=1546, + XED_IFORMFL_PTWRITE_FIRST=1547, + XED_IFORMFL_PTWRITE_LAST=1548, + XED_IFORMFL_PUNPCKHBW_FIRST=1549, + XED_IFORMFL_PUNPCKHBW_LAST=1552, + XED_IFORMFL_PUNPCKHDQ_FIRST=1553, + XED_IFORMFL_PUNPCKHDQ_LAST=1556, + XED_IFORMFL_PUNPCKHQDQ_FIRST=1557, + XED_IFORMFL_PUNPCKHQDQ_LAST=1558, + XED_IFORMFL_PUNPCKHWD_FIRST=1559, + XED_IFORMFL_PUNPCKHWD_LAST=1562, + XED_IFORMFL_PUNPCKLBW_FIRST=1563, + XED_IFORMFL_PUNPCKLBW_LAST=1566, + XED_IFORMFL_PUNPCKLDQ_FIRST=1567, + XED_IFORMFL_PUNPCKLDQ_LAST=1570, + XED_IFORMFL_PUNPCKLQDQ_FIRST=1571, + XED_IFORMFL_PUNPCKLQDQ_LAST=1572, + XED_IFORMFL_PUNPCKLWD_FIRST=1573, + XED_IFORMFL_PUNPCKLWD_LAST=1576, + XED_IFORMFL_PUSH_FIRST=1577, + XED_IFORMFL_PUSH_LAST=1587, + XED_IFORMFL_PUSHA_FIRST=1588, + XED_IFORMFL_PUSHA_LAST=1588, + XED_IFORMFL_PUSHAD_FIRST=1589, + XED_IFORMFL_PUSHAD_LAST=1589, + XED_IFORMFL_PUSHF_FIRST=1590, + XED_IFORMFL_PUSHF_LAST=1590, + XED_IFORMFL_PUSHFD_FIRST=1591, + XED_IFORMFL_PUSHFD_LAST=1591, + XED_IFORMFL_PUSHFQ_FIRST=1592, + XED_IFORMFL_PUSHFQ_LAST=1592, + XED_IFORMFL_PVALIDATE_FIRST=1593, + XED_IFORMFL_PVALIDATE_LAST=1593, + XED_IFORMFL_PXOR_FIRST=1594, + XED_IFORMFL_PXOR_LAST=1597, + XED_IFORMFL_RCL_FIRST=1598, + XED_IFORMFL_RCL_LAST=1609, + XED_IFORMFL_RCPPS_FIRST=1610, + XED_IFORMFL_RCPPS_LAST=1611, + XED_IFORMFL_RCPSS_FIRST=1612, + XED_IFORMFL_RCPSS_LAST=1613, + XED_IFORMFL_RCR_FIRST=1614, + XED_IFORMFL_RCR_LAST=1625, + XED_IFORMFL_RDFSBASE_FIRST=1626, + XED_IFORMFL_RDFSBASE_LAST=1626, + XED_IFORMFL_RDGSBASE_FIRST=1627, + XED_IFORMFL_RDGSBASE_LAST=1627, + XED_IFORMFL_RDMSR_FIRST=1628, + XED_IFORMFL_RDMSR_LAST=1628, + XED_IFORMFL_RDPID_FIRST=1629, + XED_IFORMFL_RDPID_LAST=1630, + XED_IFORMFL_RDPKRU_FIRST=1631, + XED_IFORMFL_RDPKRU_LAST=1631, + XED_IFORMFL_RDPMC_FIRST=1632, + XED_IFORMFL_RDPMC_LAST=1632, + XED_IFORMFL_RDPRU_FIRST=1633, + XED_IFORMFL_RDPRU_LAST=1633, + XED_IFORMFL_RDRAND_FIRST=1634, + XED_IFORMFL_RDRAND_LAST=1634, + XED_IFORMFL_RDSEED_FIRST=1635, + XED_IFORMFL_RDSEED_LAST=1635, + XED_IFORMFL_RDSSPD_FIRST=1636, + XED_IFORMFL_RDSSPD_LAST=1636, + XED_IFORMFL_RDSSPQ_FIRST=1637, + XED_IFORMFL_RDSSPQ_LAST=1637, + XED_IFORMFL_RDTSC_FIRST=1638, + XED_IFORMFL_RDTSC_LAST=1638, + XED_IFORMFL_RDTSCP_FIRST=1639, + XED_IFORMFL_RDTSCP_LAST=1639, + XED_IFORMFL_REPE_CMPSB_FIRST=1640, + XED_IFORMFL_REPE_CMPSB_LAST=1640, + XED_IFORMFL_REPE_CMPSD_FIRST=1641, + XED_IFORMFL_REPE_CMPSD_LAST=1641, + XED_IFORMFL_REPE_CMPSQ_FIRST=1642, + XED_IFORMFL_REPE_CMPSQ_LAST=1642, + XED_IFORMFL_REPE_CMPSW_FIRST=1643, + XED_IFORMFL_REPE_CMPSW_LAST=1643, + XED_IFORMFL_REPE_SCASB_FIRST=1644, + XED_IFORMFL_REPE_SCASB_LAST=1644, + XED_IFORMFL_REPE_SCASD_FIRST=1645, + XED_IFORMFL_REPE_SCASD_LAST=1645, + XED_IFORMFL_REPE_SCASQ_FIRST=1646, + XED_IFORMFL_REPE_SCASQ_LAST=1646, + XED_IFORMFL_REPE_SCASW_FIRST=1647, + XED_IFORMFL_REPE_SCASW_LAST=1647, + XED_IFORMFL_REPNE_CMPSB_FIRST=1648, + XED_IFORMFL_REPNE_CMPSB_LAST=1648, + XED_IFORMFL_REPNE_CMPSD_FIRST=1649, + XED_IFORMFL_REPNE_CMPSD_LAST=1649, + XED_IFORMFL_REPNE_CMPSQ_FIRST=1650, + XED_IFORMFL_REPNE_CMPSQ_LAST=1650, + XED_IFORMFL_REPNE_CMPSW_FIRST=1651, + XED_IFORMFL_REPNE_CMPSW_LAST=1651, + XED_IFORMFL_REPNE_SCASB_FIRST=1652, + XED_IFORMFL_REPNE_SCASB_LAST=1652, + XED_IFORMFL_REPNE_SCASD_FIRST=1653, + XED_IFORMFL_REPNE_SCASD_LAST=1653, + XED_IFORMFL_REPNE_SCASQ_FIRST=1654, + XED_IFORMFL_REPNE_SCASQ_LAST=1654, + XED_IFORMFL_REPNE_SCASW_FIRST=1655, + XED_IFORMFL_REPNE_SCASW_LAST=1655, + XED_IFORMFL_REP_INSB_FIRST=1656, + XED_IFORMFL_REP_INSB_LAST=1656, + XED_IFORMFL_REP_INSD_FIRST=1657, + XED_IFORMFL_REP_INSD_LAST=1657, + XED_IFORMFL_REP_INSW_FIRST=1658, + XED_IFORMFL_REP_INSW_LAST=1658, + XED_IFORMFL_REP_LODSB_FIRST=1659, + XED_IFORMFL_REP_LODSB_LAST=1659, + XED_IFORMFL_REP_LODSD_FIRST=1660, + XED_IFORMFL_REP_LODSD_LAST=1660, + XED_IFORMFL_REP_LODSQ_FIRST=1661, + XED_IFORMFL_REP_LODSQ_LAST=1661, + XED_IFORMFL_REP_LODSW_FIRST=1662, + XED_IFORMFL_REP_LODSW_LAST=1662, + XED_IFORMFL_REP_MONTMUL_FIRST=1663, + XED_IFORMFL_REP_MONTMUL_LAST=1663, + XED_IFORMFL_REP_MOVSB_FIRST=1664, + XED_IFORMFL_REP_MOVSB_LAST=1664, + XED_IFORMFL_REP_MOVSD_FIRST=1665, + XED_IFORMFL_REP_MOVSD_LAST=1665, + XED_IFORMFL_REP_MOVSQ_FIRST=1666, + XED_IFORMFL_REP_MOVSQ_LAST=1666, + XED_IFORMFL_REP_MOVSW_FIRST=1667, + XED_IFORMFL_REP_MOVSW_LAST=1667, + XED_IFORMFL_REP_OUTSB_FIRST=1668, + XED_IFORMFL_REP_OUTSB_LAST=1668, + XED_IFORMFL_REP_OUTSD_FIRST=1669, + XED_IFORMFL_REP_OUTSD_LAST=1669, + XED_IFORMFL_REP_OUTSW_FIRST=1670, + XED_IFORMFL_REP_OUTSW_LAST=1670, + XED_IFORMFL_REP_STOSB_FIRST=1671, + XED_IFORMFL_REP_STOSB_LAST=1671, + XED_IFORMFL_REP_STOSD_FIRST=1672, + XED_IFORMFL_REP_STOSD_LAST=1672, + XED_IFORMFL_REP_STOSQ_FIRST=1673, + XED_IFORMFL_REP_STOSQ_LAST=1673, + XED_IFORMFL_REP_STOSW_FIRST=1674, + XED_IFORMFL_REP_STOSW_LAST=1674, + XED_IFORMFL_REP_XCRYPTCBC_FIRST=1675, + XED_IFORMFL_REP_XCRYPTCBC_LAST=1675, + XED_IFORMFL_REP_XCRYPTCFB_FIRST=1676, + XED_IFORMFL_REP_XCRYPTCFB_LAST=1676, + XED_IFORMFL_REP_XCRYPTCTR_FIRST=1677, + XED_IFORMFL_REP_XCRYPTCTR_LAST=1677, + XED_IFORMFL_REP_XCRYPTECB_FIRST=1678, + XED_IFORMFL_REP_XCRYPTECB_LAST=1678, + XED_IFORMFL_REP_XCRYPTOFB_FIRST=1679, + XED_IFORMFL_REP_XCRYPTOFB_LAST=1679, + XED_IFORMFL_REP_XSHA1_FIRST=1680, + XED_IFORMFL_REP_XSHA1_LAST=1680, + XED_IFORMFL_REP_XSHA256_FIRST=1681, + XED_IFORMFL_REP_XSHA256_LAST=1681, + XED_IFORMFL_REP_XSTORE_FIRST=1682, + XED_IFORMFL_REP_XSTORE_LAST=1682, + XED_IFORMFL_RET_FAR_FIRST=1683, + XED_IFORMFL_RET_FAR_LAST=1684, + XED_IFORMFL_RET_NEAR_FIRST=1685, + XED_IFORMFL_RET_NEAR_LAST=1686, + XED_IFORMFL_RMPADJUST_FIRST=1687, + XED_IFORMFL_RMPADJUST_LAST=1687, + XED_IFORMFL_RMPUPDATE_FIRST=1688, + XED_IFORMFL_RMPUPDATE_LAST=1688, + XED_IFORMFL_ROL_FIRST=1689, + XED_IFORMFL_ROL_LAST=1700, + XED_IFORMFL_ROR_FIRST=1701, + XED_IFORMFL_ROR_LAST=1712, + XED_IFORMFL_RORX_FIRST=1713, + XED_IFORMFL_RORX_LAST=1716, + XED_IFORMFL_ROUNDPD_FIRST=1717, + XED_IFORMFL_ROUNDPD_LAST=1718, + XED_IFORMFL_ROUNDPS_FIRST=1719, + XED_IFORMFL_ROUNDPS_LAST=1720, + XED_IFORMFL_ROUNDSD_FIRST=1721, + XED_IFORMFL_ROUNDSD_LAST=1722, + XED_IFORMFL_ROUNDSS_FIRST=1723, + XED_IFORMFL_ROUNDSS_LAST=1724, + XED_IFORMFL_RSM_FIRST=1725, + XED_IFORMFL_RSM_LAST=1725, + XED_IFORMFL_RSQRTPS_FIRST=1726, + XED_IFORMFL_RSQRTPS_LAST=1727, + XED_IFORMFL_RSQRTSS_FIRST=1728, + XED_IFORMFL_RSQRTSS_LAST=1729, + XED_IFORMFL_RSTORSSP_FIRST=1730, + XED_IFORMFL_RSTORSSP_LAST=1730, + XED_IFORMFL_SAHF_FIRST=1731, + XED_IFORMFL_SAHF_LAST=1731, + XED_IFORMFL_SALC_FIRST=1732, + XED_IFORMFL_SALC_LAST=1732, + XED_IFORMFL_SAR_FIRST=1733, + XED_IFORMFL_SAR_LAST=1744, + XED_IFORMFL_SARX_FIRST=1745, + XED_IFORMFL_SARX_LAST=1748, + XED_IFORMFL_SAVEPREVSSP_FIRST=1749, + XED_IFORMFL_SAVEPREVSSP_LAST=1749, + XED_IFORMFL_SBB_FIRST=1750, + XED_IFORMFL_SBB_LAST=1767, + XED_IFORMFL_SBB_LOCK_FIRST=1768, + XED_IFORMFL_SBB_LOCK_LAST=1773, + XED_IFORMFL_SCASB_FIRST=1774, + XED_IFORMFL_SCASB_LAST=1774, + XED_IFORMFL_SCASD_FIRST=1775, + XED_IFORMFL_SCASD_LAST=1775, + XED_IFORMFL_SCASQ_FIRST=1776, + XED_IFORMFL_SCASQ_LAST=1776, + XED_IFORMFL_SCASW_FIRST=1777, + XED_IFORMFL_SCASW_LAST=1777, + XED_IFORMFL_SEAMCALL_FIRST=1778, + XED_IFORMFL_SEAMCALL_LAST=1778, + XED_IFORMFL_SEAMOPS_FIRST=1779, + XED_IFORMFL_SEAMOPS_LAST=1779, + XED_IFORMFL_SEAMRET_FIRST=1780, + XED_IFORMFL_SEAMRET_LAST=1780, + XED_IFORMFL_SENDUIPI_FIRST=1781, + XED_IFORMFL_SENDUIPI_LAST=1781, + XED_IFORMFL_SERIALIZE_FIRST=1782, + XED_IFORMFL_SERIALIZE_LAST=1782, + XED_IFORMFL_SETB_FIRST=1783, + XED_IFORMFL_SETB_LAST=1784, + XED_IFORMFL_SETBE_FIRST=1785, + XED_IFORMFL_SETBE_LAST=1786, + XED_IFORMFL_SETL_FIRST=1787, + XED_IFORMFL_SETL_LAST=1788, + XED_IFORMFL_SETLE_FIRST=1789, + XED_IFORMFL_SETLE_LAST=1790, + XED_IFORMFL_SETNB_FIRST=1791, + XED_IFORMFL_SETNB_LAST=1792, + XED_IFORMFL_SETNBE_FIRST=1793, + XED_IFORMFL_SETNBE_LAST=1794, + XED_IFORMFL_SETNL_FIRST=1795, + XED_IFORMFL_SETNL_LAST=1796, + XED_IFORMFL_SETNLE_FIRST=1797, + XED_IFORMFL_SETNLE_LAST=1798, + XED_IFORMFL_SETNO_FIRST=1799, + XED_IFORMFL_SETNO_LAST=1800, + XED_IFORMFL_SETNP_FIRST=1801, + XED_IFORMFL_SETNP_LAST=1802, + XED_IFORMFL_SETNS_FIRST=1803, + XED_IFORMFL_SETNS_LAST=1804, + XED_IFORMFL_SETNZ_FIRST=1805, + XED_IFORMFL_SETNZ_LAST=1806, + XED_IFORMFL_SETO_FIRST=1807, + XED_IFORMFL_SETO_LAST=1808, + XED_IFORMFL_SETP_FIRST=1809, + XED_IFORMFL_SETP_LAST=1810, + XED_IFORMFL_SETS_FIRST=1811, + XED_IFORMFL_SETS_LAST=1812, + XED_IFORMFL_SETSSBSY_FIRST=1813, + XED_IFORMFL_SETSSBSY_LAST=1813, + XED_IFORMFL_SETZ_FIRST=1814, + XED_IFORMFL_SETZ_LAST=1815, + XED_IFORMFL_SFENCE_FIRST=1816, + XED_IFORMFL_SFENCE_LAST=1816, + XED_IFORMFL_SGDT_FIRST=1817, + XED_IFORMFL_SGDT_LAST=1818, + XED_IFORMFL_SHA1MSG1_FIRST=1819, + XED_IFORMFL_SHA1MSG1_LAST=1820, + XED_IFORMFL_SHA1MSG2_FIRST=1821, + XED_IFORMFL_SHA1MSG2_LAST=1822, + XED_IFORMFL_SHA1NEXTE_FIRST=1823, + XED_IFORMFL_SHA1NEXTE_LAST=1824, + XED_IFORMFL_SHA1RNDS4_FIRST=1825, + XED_IFORMFL_SHA1RNDS4_LAST=1826, + XED_IFORMFL_SHA256MSG1_FIRST=1827, + XED_IFORMFL_SHA256MSG1_LAST=1828, + XED_IFORMFL_SHA256MSG2_FIRST=1829, + XED_IFORMFL_SHA256MSG2_LAST=1830, + XED_IFORMFL_SHA256RNDS2_FIRST=1831, + XED_IFORMFL_SHA256RNDS2_LAST=1832, + XED_IFORMFL_SHL_FIRST=1833, + XED_IFORMFL_SHL_LAST=1856, + XED_IFORMFL_SHLD_FIRST=1857, + XED_IFORMFL_SHLD_LAST=1860, + XED_IFORMFL_SHLX_FIRST=1861, + XED_IFORMFL_SHLX_LAST=1864, + XED_IFORMFL_SHR_FIRST=1865, + XED_IFORMFL_SHR_LAST=1876, + XED_IFORMFL_SHRD_FIRST=1877, + XED_IFORMFL_SHRD_LAST=1880, + XED_IFORMFL_SHRX_FIRST=1881, + XED_IFORMFL_SHRX_LAST=1884, + XED_IFORMFL_SHUFPD_FIRST=1885, + XED_IFORMFL_SHUFPD_LAST=1886, + XED_IFORMFL_SHUFPS_FIRST=1887, + XED_IFORMFL_SHUFPS_LAST=1888, + XED_IFORMFL_SIDT_FIRST=1889, + XED_IFORMFL_SIDT_LAST=1890, + XED_IFORMFL_SKINIT_FIRST=1891, + XED_IFORMFL_SKINIT_LAST=1891, + XED_IFORMFL_SLDT_FIRST=1892, + XED_IFORMFL_SLDT_LAST=1893, + XED_IFORMFL_SLWPCB_FIRST=1894, + XED_IFORMFL_SLWPCB_LAST=1894, + XED_IFORMFL_SMSW_FIRST=1895, + XED_IFORMFL_SMSW_LAST=1896, + XED_IFORMFL_SQRTPD_FIRST=1897, + XED_IFORMFL_SQRTPD_LAST=1898, + XED_IFORMFL_SQRTPS_FIRST=1899, + XED_IFORMFL_SQRTPS_LAST=1900, + XED_IFORMFL_SQRTSD_FIRST=1901, + XED_IFORMFL_SQRTSD_LAST=1902, + XED_IFORMFL_SQRTSS_FIRST=1903, + XED_IFORMFL_SQRTSS_LAST=1904, + XED_IFORMFL_STAC_FIRST=1905, + XED_IFORMFL_STAC_LAST=1905, + XED_IFORMFL_STC_FIRST=1906, + XED_IFORMFL_STC_LAST=1906, + XED_IFORMFL_STD_FIRST=1907, + XED_IFORMFL_STD_LAST=1907, + XED_IFORMFL_STGI_FIRST=1908, + XED_IFORMFL_STGI_LAST=1908, + XED_IFORMFL_STI_FIRST=1909, + XED_IFORMFL_STI_LAST=1909, + XED_IFORMFL_STMXCSR_FIRST=1910, + XED_IFORMFL_STMXCSR_LAST=1910, + XED_IFORMFL_STOSB_FIRST=1911, + XED_IFORMFL_STOSB_LAST=1911, + XED_IFORMFL_STOSD_FIRST=1912, + XED_IFORMFL_STOSD_LAST=1912, + XED_IFORMFL_STOSQ_FIRST=1913, + XED_IFORMFL_STOSQ_LAST=1913, + XED_IFORMFL_STOSW_FIRST=1914, + XED_IFORMFL_STOSW_LAST=1914, + XED_IFORMFL_STR_FIRST=1915, + XED_IFORMFL_STR_LAST=1916, + XED_IFORMFL_STTILECFG_FIRST=1917, + XED_IFORMFL_STTILECFG_LAST=1917, + XED_IFORMFL_STUI_FIRST=1918, + XED_IFORMFL_STUI_LAST=1918, + XED_IFORMFL_SUB_FIRST=1919, + XED_IFORMFL_SUB_LAST=1936, + XED_IFORMFL_SUBPD_FIRST=1937, + XED_IFORMFL_SUBPD_LAST=1938, + XED_IFORMFL_SUBPS_FIRST=1939, + XED_IFORMFL_SUBPS_LAST=1940, + XED_IFORMFL_SUBSD_FIRST=1941, + XED_IFORMFL_SUBSD_LAST=1942, + XED_IFORMFL_SUBSS_FIRST=1943, + XED_IFORMFL_SUBSS_LAST=1944, + XED_IFORMFL_SUB_LOCK_FIRST=1945, + XED_IFORMFL_SUB_LOCK_LAST=1950, + XED_IFORMFL_SWAPGS_FIRST=1951, + XED_IFORMFL_SWAPGS_LAST=1951, + XED_IFORMFL_SYSCALL_FIRST=1952, + XED_IFORMFL_SYSCALL_LAST=1952, + XED_IFORMFL_SYSCALL_AMD_FIRST=1953, + XED_IFORMFL_SYSCALL_AMD_LAST=1953, + XED_IFORMFL_SYSENTER_FIRST=1954, + XED_IFORMFL_SYSENTER_LAST=1954, + XED_IFORMFL_SYSEXIT_FIRST=1955, + XED_IFORMFL_SYSEXIT_LAST=1955, + XED_IFORMFL_SYSRET_FIRST=1956, + XED_IFORMFL_SYSRET_LAST=1956, + XED_IFORMFL_SYSRET64_FIRST=1957, + XED_IFORMFL_SYSRET64_LAST=1957, + XED_IFORMFL_SYSRET_AMD_FIRST=1958, + XED_IFORMFL_SYSRET_AMD_LAST=1958, + XED_IFORMFL_T1MSKC_FIRST=1959, + XED_IFORMFL_T1MSKC_LAST=1962, + XED_IFORMFL_TDCALL_FIRST=1963, + XED_IFORMFL_TDCALL_LAST=1963, + XED_IFORMFL_TDPBF16PS_FIRST=1964, + XED_IFORMFL_TDPBF16PS_LAST=1964, + XED_IFORMFL_TDPBSSD_FIRST=1965, + XED_IFORMFL_TDPBSSD_LAST=1965, + XED_IFORMFL_TDPBSUD_FIRST=1966, + XED_IFORMFL_TDPBSUD_LAST=1966, + XED_IFORMFL_TDPBUSD_FIRST=1967, + XED_IFORMFL_TDPBUSD_LAST=1967, + XED_IFORMFL_TDPBUUD_FIRST=1968, + XED_IFORMFL_TDPBUUD_LAST=1968, + XED_IFORMFL_TEST_FIRST=1969, + XED_IFORMFL_TEST_LAST=1982, + XED_IFORMFL_TESTUI_FIRST=1983, + XED_IFORMFL_TESTUI_LAST=1983, + XED_IFORMFL_TILELOADD_FIRST=1984, + XED_IFORMFL_TILELOADD_LAST=1984, + XED_IFORMFL_TILELOADDT1_FIRST=1985, + XED_IFORMFL_TILELOADDT1_LAST=1985, + XED_IFORMFL_TILERELEASE_FIRST=1986, + XED_IFORMFL_TILERELEASE_LAST=1986, + XED_IFORMFL_TILESTORED_FIRST=1987, + XED_IFORMFL_TILESTORED_LAST=1987, + XED_IFORMFL_TILEZERO_FIRST=1988, + XED_IFORMFL_TILEZERO_LAST=1988, + XED_IFORMFL_TLBSYNC_FIRST=1989, + XED_IFORMFL_TLBSYNC_LAST=1989, + XED_IFORMFL_TPAUSE_FIRST=1990, + XED_IFORMFL_TPAUSE_LAST=1990, + XED_IFORMFL_TZCNT_FIRST=1991, + XED_IFORMFL_TZCNT_LAST=1992, + XED_IFORMFL_TZMSK_FIRST=1993, + XED_IFORMFL_TZMSK_LAST=1996, + XED_IFORMFL_UCOMISD_FIRST=1997, + XED_IFORMFL_UCOMISD_LAST=1998, + XED_IFORMFL_UCOMISS_FIRST=1999, + XED_IFORMFL_UCOMISS_LAST=2000, + XED_IFORMFL_UD0_FIRST=2001, + XED_IFORMFL_UD0_LAST=2003, + XED_IFORMFL_UD1_FIRST=2004, + XED_IFORMFL_UD1_LAST=2005, + XED_IFORMFL_UD2_FIRST=2006, + XED_IFORMFL_UD2_LAST=2006, + XED_IFORMFL_UIRET_FIRST=2007, + XED_IFORMFL_UIRET_LAST=2007, + XED_IFORMFL_UMONITOR_FIRST=2008, + XED_IFORMFL_UMONITOR_LAST=2008, + XED_IFORMFL_UMWAIT_FIRST=2009, + XED_IFORMFL_UMWAIT_LAST=2009, + XED_IFORMFL_UNPCKHPD_FIRST=2010, + XED_IFORMFL_UNPCKHPD_LAST=2011, + XED_IFORMFL_UNPCKHPS_FIRST=2012, + XED_IFORMFL_UNPCKHPS_LAST=2013, + XED_IFORMFL_UNPCKLPD_FIRST=2014, + XED_IFORMFL_UNPCKLPD_LAST=2015, + XED_IFORMFL_UNPCKLPS_FIRST=2016, + XED_IFORMFL_UNPCKLPS_LAST=2017, + XED_IFORMFL_V4FMADDPS_FIRST=2018, + XED_IFORMFL_V4FMADDPS_LAST=2018, + XED_IFORMFL_V4FMADDSS_FIRST=2019, + XED_IFORMFL_V4FMADDSS_LAST=2019, + XED_IFORMFL_V4FNMADDPS_FIRST=2020, + XED_IFORMFL_V4FNMADDPS_LAST=2020, + XED_IFORMFL_V4FNMADDSS_FIRST=2021, + XED_IFORMFL_V4FNMADDSS_LAST=2021, + XED_IFORMFL_VADDPD_FIRST=2022, + XED_IFORMFL_VADDPD_LAST=2031, + XED_IFORMFL_VADDPH_FIRST=2032, + XED_IFORMFL_VADDPH_LAST=2037, + XED_IFORMFL_VADDPS_FIRST=2038, + XED_IFORMFL_VADDPS_LAST=2047, + XED_IFORMFL_VADDSD_FIRST=2048, + XED_IFORMFL_VADDSD_LAST=2051, + XED_IFORMFL_VADDSH_FIRST=2052, + XED_IFORMFL_VADDSH_LAST=2053, + XED_IFORMFL_VADDSS_FIRST=2054, + XED_IFORMFL_VADDSS_LAST=2057, + XED_IFORMFL_VADDSUBPD_FIRST=2058, + XED_IFORMFL_VADDSUBPD_LAST=2061, + XED_IFORMFL_VADDSUBPS_FIRST=2062, + XED_IFORMFL_VADDSUBPS_LAST=2065, + XED_IFORMFL_VAESDEC_FIRST=2066, + XED_IFORMFL_VAESDEC_LAST=2075, + XED_IFORMFL_VAESDECLAST_FIRST=2076, + XED_IFORMFL_VAESDECLAST_LAST=2085, + XED_IFORMFL_VAESENC_FIRST=2086, + XED_IFORMFL_VAESENC_LAST=2095, + XED_IFORMFL_VAESENCLAST_FIRST=2096, + XED_IFORMFL_VAESENCLAST_LAST=2105, + XED_IFORMFL_VAESIMC_FIRST=2106, + XED_IFORMFL_VAESIMC_LAST=2107, + XED_IFORMFL_VAESKEYGENASSIST_FIRST=2108, + XED_IFORMFL_VAESKEYGENASSIST_LAST=2109, + XED_IFORMFL_VALIGND_FIRST=2110, + XED_IFORMFL_VALIGND_LAST=2115, + XED_IFORMFL_VALIGNQ_FIRST=2116, + XED_IFORMFL_VALIGNQ_LAST=2121, + XED_IFORMFL_VANDNPD_FIRST=2122, + XED_IFORMFL_VANDNPD_LAST=2131, + XED_IFORMFL_VANDNPS_FIRST=2132, + XED_IFORMFL_VANDNPS_LAST=2141, + XED_IFORMFL_VANDPD_FIRST=2142, + XED_IFORMFL_VANDPD_LAST=2151, + XED_IFORMFL_VANDPS_FIRST=2152, + XED_IFORMFL_VANDPS_LAST=2161, + XED_IFORMFL_VBLENDMPD_FIRST=2162, + XED_IFORMFL_VBLENDMPD_LAST=2167, + XED_IFORMFL_VBLENDMPS_FIRST=2168, + XED_IFORMFL_VBLENDMPS_LAST=2173, + XED_IFORMFL_VBLENDPD_FIRST=2174, + XED_IFORMFL_VBLENDPD_LAST=2177, + XED_IFORMFL_VBLENDPS_FIRST=2178, + XED_IFORMFL_VBLENDPS_LAST=2181, + XED_IFORMFL_VBLENDVPD_FIRST=2182, + XED_IFORMFL_VBLENDVPD_LAST=2185, + XED_IFORMFL_VBLENDVPS_FIRST=2186, + XED_IFORMFL_VBLENDVPS_LAST=2189, + XED_IFORMFL_VBROADCASTF128_FIRST=2190, + XED_IFORMFL_VBROADCASTF128_LAST=2190, + XED_IFORMFL_VBROADCASTF32X2_FIRST=2191, + XED_IFORMFL_VBROADCASTF32X2_LAST=2194, + XED_IFORMFL_VBROADCASTF32X4_FIRST=2195, + XED_IFORMFL_VBROADCASTF32X4_LAST=2196, + XED_IFORMFL_VBROADCASTF32X8_FIRST=2197, + XED_IFORMFL_VBROADCASTF32X8_LAST=2197, + XED_IFORMFL_VBROADCASTF64X2_FIRST=2198, + XED_IFORMFL_VBROADCASTF64X2_LAST=2199, + XED_IFORMFL_VBROADCASTF64X4_FIRST=2200, + XED_IFORMFL_VBROADCASTF64X4_LAST=2200, + XED_IFORMFL_VBROADCASTI128_FIRST=2201, + XED_IFORMFL_VBROADCASTI128_LAST=2201, + XED_IFORMFL_VBROADCASTI32X2_FIRST=2202, + XED_IFORMFL_VBROADCASTI32X2_LAST=2207, + XED_IFORMFL_VBROADCASTI32X4_FIRST=2208, + XED_IFORMFL_VBROADCASTI32X4_LAST=2209, + XED_IFORMFL_VBROADCASTI32X8_FIRST=2210, + XED_IFORMFL_VBROADCASTI32X8_LAST=2210, + XED_IFORMFL_VBROADCASTI64X2_FIRST=2211, + XED_IFORMFL_VBROADCASTI64X2_LAST=2212, + XED_IFORMFL_VBROADCASTI64X4_FIRST=2213, + XED_IFORMFL_VBROADCASTI64X4_LAST=2213, + XED_IFORMFL_VBROADCASTSD_FIRST=2214, + XED_IFORMFL_VBROADCASTSD_LAST=2219, + XED_IFORMFL_VBROADCASTSS_FIRST=2220, + XED_IFORMFL_VBROADCASTSS_LAST=2229, + XED_IFORMFL_VCMPPD_FIRST=2230, + XED_IFORMFL_VCMPPD_LAST=2239, + XED_IFORMFL_VCMPPH_FIRST=2240, + XED_IFORMFL_VCMPPH_LAST=2245, + XED_IFORMFL_VCMPPS_FIRST=2246, + XED_IFORMFL_VCMPPS_LAST=2255, + XED_IFORMFL_VCMPSD_FIRST=2256, + XED_IFORMFL_VCMPSD_LAST=2259, + XED_IFORMFL_VCMPSH_FIRST=2260, + XED_IFORMFL_VCMPSH_LAST=2261, + XED_IFORMFL_VCMPSS_FIRST=2262, + XED_IFORMFL_VCMPSS_LAST=2265, + XED_IFORMFL_VCOMISD_FIRST=2266, + XED_IFORMFL_VCOMISD_LAST=2269, + XED_IFORMFL_VCOMISH_FIRST=2270, + XED_IFORMFL_VCOMISH_LAST=2271, + XED_IFORMFL_VCOMISS_FIRST=2272, + XED_IFORMFL_VCOMISS_LAST=2275, + XED_IFORMFL_VCOMPRESSPD_FIRST=2276, + XED_IFORMFL_VCOMPRESSPD_LAST=2281, + XED_IFORMFL_VCOMPRESSPS_FIRST=2282, + XED_IFORMFL_VCOMPRESSPS_LAST=2287, + XED_IFORMFL_VCVTDQ2PD_FIRST=2288, + XED_IFORMFL_VCVTDQ2PD_LAST=2297, + XED_IFORMFL_VCVTDQ2PH_FIRST=2298, + XED_IFORMFL_VCVTDQ2PH_LAST=2303, + XED_IFORMFL_VCVTDQ2PS_FIRST=2304, + XED_IFORMFL_VCVTDQ2PS_LAST=2313, + XED_IFORMFL_VCVTNE2PS2BF16_FIRST=2314, + XED_IFORMFL_VCVTNE2PS2BF16_LAST=2319, + XED_IFORMFL_VCVTNEPS2BF16_FIRST=2320, + XED_IFORMFL_VCVTNEPS2BF16_LAST=2325, + XED_IFORMFL_VCVTPD2DQ_FIRST=2326, + XED_IFORMFL_VCVTPD2DQ_LAST=2335, + XED_IFORMFL_VCVTPD2PH_FIRST=2336, + XED_IFORMFL_VCVTPD2PH_LAST=2341, + XED_IFORMFL_VCVTPD2PS_FIRST=2342, + XED_IFORMFL_VCVTPD2PS_LAST=2351, + XED_IFORMFL_VCVTPD2QQ_FIRST=2352, + XED_IFORMFL_VCVTPD2QQ_LAST=2357, + XED_IFORMFL_VCVTPD2UDQ_FIRST=2358, + XED_IFORMFL_VCVTPD2UDQ_LAST=2363, + XED_IFORMFL_VCVTPD2UQQ_FIRST=2364, + XED_IFORMFL_VCVTPD2UQQ_LAST=2369, + XED_IFORMFL_VCVTPH2DQ_FIRST=2370, + XED_IFORMFL_VCVTPH2DQ_LAST=2375, + XED_IFORMFL_VCVTPH2PD_FIRST=2376, + XED_IFORMFL_VCVTPH2PD_LAST=2381, + XED_IFORMFL_VCVTPH2PS_FIRST=2382, + XED_IFORMFL_VCVTPH2PS_LAST=2391, + XED_IFORMFL_VCVTPH2PSX_FIRST=2392, + XED_IFORMFL_VCVTPH2PSX_LAST=2397, + XED_IFORMFL_VCVTPH2QQ_FIRST=2398, + XED_IFORMFL_VCVTPH2QQ_LAST=2403, + XED_IFORMFL_VCVTPH2UDQ_FIRST=2404, + XED_IFORMFL_VCVTPH2UDQ_LAST=2409, + XED_IFORMFL_VCVTPH2UQQ_FIRST=2410, + XED_IFORMFL_VCVTPH2UQQ_LAST=2415, + XED_IFORMFL_VCVTPH2UW_FIRST=2416, + XED_IFORMFL_VCVTPH2UW_LAST=2421, + XED_IFORMFL_VCVTPH2W_FIRST=2422, + XED_IFORMFL_VCVTPH2W_LAST=2427, + XED_IFORMFL_VCVTPS2DQ_FIRST=2428, + XED_IFORMFL_VCVTPS2DQ_LAST=2437, + XED_IFORMFL_VCVTPS2PD_FIRST=2438, + XED_IFORMFL_VCVTPS2PD_LAST=2447, + XED_IFORMFL_VCVTPS2PH_FIRST=2448, + XED_IFORMFL_VCVTPS2PH_LAST=2457, + XED_IFORMFL_VCVTPS2PHX_FIRST=2458, + XED_IFORMFL_VCVTPS2PHX_LAST=2463, + XED_IFORMFL_VCVTPS2QQ_FIRST=2464, + XED_IFORMFL_VCVTPS2QQ_LAST=2469, + XED_IFORMFL_VCVTPS2UDQ_FIRST=2470, + XED_IFORMFL_VCVTPS2UDQ_LAST=2475, + XED_IFORMFL_VCVTPS2UQQ_FIRST=2476, + XED_IFORMFL_VCVTPS2UQQ_LAST=2481, + XED_IFORMFL_VCVTQQ2PD_FIRST=2482, + XED_IFORMFL_VCVTQQ2PD_LAST=2487, + XED_IFORMFL_VCVTQQ2PH_FIRST=2488, + XED_IFORMFL_VCVTQQ2PH_LAST=2493, + XED_IFORMFL_VCVTQQ2PS_FIRST=2494, + XED_IFORMFL_VCVTQQ2PS_LAST=2499, + XED_IFORMFL_VCVTSD2SH_FIRST=2500, + XED_IFORMFL_VCVTSD2SH_LAST=2501, + XED_IFORMFL_VCVTSD2SI_FIRST=2502, + XED_IFORMFL_VCVTSD2SI_LAST=2509, + XED_IFORMFL_VCVTSD2SS_FIRST=2510, + XED_IFORMFL_VCVTSD2SS_LAST=2513, + XED_IFORMFL_VCVTSD2USI_FIRST=2514, + XED_IFORMFL_VCVTSD2USI_LAST=2517, + XED_IFORMFL_VCVTSH2SD_FIRST=2518, + XED_IFORMFL_VCVTSH2SD_LAST=2519, + XED_IFORMFL_VCVTSH2SI_FIRST=2520, + XED_IFORMFL_VCVTSH2SI_LAST=2523, + XED_IFORMFL_VCVTSH2SS_FIRST=2524, + XED_IFORMFL_VCVTSH2SS_LAST=2525, + XED_IFORMFL_VCVTSH2USI_FIRST=2526, + XED_IFORMFL_VCVTSH2USI_LAST=2529, + XED_IFORMFL_VCVTSI2SD_FIRST=2530, + XED_IFORMFL_VCVTSI2SD_LAST=2537, + XED_IFORMFL_VCVTSI2SH_FIRST=2538, + XED_IFORMFL_VCVTSI2SH_LAST=2541, + XED_IFORMFL_VCVTSI2SS_FIRST=2542, + XED_IFORMFL_VCVTSI2SS_LAST=2549, + XED_IFORMFL_VCVTSS2SD_FIRST=2550, + XED_IFORMFL_VCVTSS2SD_LAST=2553, + XED_IFORMFL_VCVTSS2SH_FIRST=2554, + XED_IFORMFL_VCVTSS2SH_LAST=2555, + XED_IFORMFL_VCVTSS2SI_FIRST=2556, + XED_IFORMFL_VCVTSS2SI_LAST=2563, + XED_IFORMFL_VCVTSS2USI_FIRST=2564, + XED_IFORMFL_VCVTSS2USI_LAST=2567, + XED_IFORMFL_VCVTTPD2DQ_FIRST=2568, + XED_IFORMFL_VCVTTPD2DQ_LAST=2577, + XED_IFORMFL_VCVTTPD2QQ_FIRST=2578, + XED_IFORMFL_VCVTTPD2QQ_LAST=2583, + XED_IFORMFL_VCVTTPD2UDQ_FIRST=2584, + XED_IFORMFL_VCVTTPD2UDQ_LAST=2589, + XED_IFORMFL_VCVTTPD2UQQ_FIRST=2590, + XED_IFORMFL_VCVTTPD2UQQ_LAST=2595, + XED_IFORMFL_VCVTTPH2DQ_FIRST=2596, + XED_IFORMFL_VCVTTPH2DQ_LAST=2601, + XED_IFORMFL_VCVTTPH2QQ_FIRST=2602, + XED_IFORMFL_VCVTTPH2QQ_LAST=2607, + XED_IFORMFL_VCVTTPH2UDQ_FIRST=2608, + XED_IFORMFL_VCVTTPH2UDQ_LAST=2613, + XED_IFORMFL_VCVTTPH2UQQ_FIRST=2614, + XED_IFORMFL_VCVTTPH2UQQ_LAST=2619, + XED_IFORMFL_VCVTTPH2UW_FIRST=2620, + XED_IFORMFL_VCVTTPH2UW_LAST=2625, + XED_IFORMFL_VCVTTPH2W_FIRST=2626, + XED_IFORMFL_VCVTTPH2W_LAST=2631, + XED_IFORMFL_VCVTTPS2DQ_FIRST=2632, + XED_IFORMFL_VCVTTPS2DQ_LAST=2641, + XED_IFORMFL_VCVTTPS2QQ_FIRST=2642, + XED_IFORMFL_VCVTTPS2QQ_LAST=2647, + XED_IFORMFL_VCVTTPS2UDQ_FIRST=2648, + XED_IFORMFL_VCVTTPS2UDQ_LAST=2653, + XED_IFORMFL_VCVTTPS2UQQ_FIRST=2654, + XED_IFORMFL_VCVTTPS2UQQ_LAST=2659, + XED_IFORMFL_VCVTTSD2SI_FIRST=2660, + XED_IFORMFL_VCVTTSD2SI_LAST=2667, + XED_IFORMFL_VCVTTSD2USI_FIRST=2668, + XED_IFORMFL_VCVTTSD2USI_LAST=2671, + XED_IFORMFL_VCVTTSH2SI_FIRST=2672, + XED_IFORMFL_VCVTTSH2SI_LAST=2675, + XED_IFORMFL_VCVTTSH2USI_FIRST=2676, + XED_IFORMFL_VCVTTSH2USI_LAST=2679, + XED_IFORMFL_VCVTTSS2SI_FIRST=2680, + XED_IFORMFL_VCVTTSS2SI_LAST=2687, + XED_IFORMFL_VCVTTSS2USI_FIRST=2688, + XED_IFORMFL_VCVTTSS2USI_LAST=2691, + XED_IFORMFL_VCVTUDQ2PD_FIRST=2692, + XED_IFORMFL_VCVTUDQ2PD_LAST=2697, + XED_IFORMFL_VCVTUDQ2PH_FIRST=2698, + XED_IFORMFL_VCVTUDQ2PH_LAST=2703, + XED_IFORMFL_VCVTUDQ2PS_FIRST=2704, + XED_IFORMFL_VCVTUDQ2PS_LAST=2709, + XED_IFORMFL_VCVTUQQ2PD_FIRST=2710, + XED_IFORMFL_VCVTUQQ2PD_LAST=2715, + XED_IFORMFL_VCVTUQQ2PH_FIRST=2716, + XED_IFORMFL_VCVTUQQ2PH_LAST=2721, + XED_IFORMFL_VCVTUQQ2PS_FIRST=2722, + XED_IFORMFL_VCVTUQQ2PS_LAST=2727, + XED_IFORMFL_VCVTUSI2SD_FIRST=2728, + XED_IFORMFL_VCVTUSI2SD_LAST=2731, + XED_IFORMFL_VCVTUSI2SH_FIRST=2732, + XED_IFORMFL_VCVTUSI2SH_LAST=2735, + XED_IFORMFL_VCVTUSI2SS_FIRST=2736, + XED_IFORMFL_VCVTUSI2SS_LAST=2739, + XED_IFORMFL_VCVTUW2PH_FIRST=2740, + XED_IFORMFL_VCVTUW2PH_LAST=2745, + XED_IFORMFL_VCVTW2PH_FIRST=2746, + XED_IFORMFL_VCVTW2PH_LAST=2751, + XED_IFORMFL_VDBPSADBW_FIRST=2752, + XED_IFORMFL_VDBPSADBW_LAST=2757, + XED_IFORMFL_VDIVPD_FIRST=2758, + XED_IFORMFL_VDIVPD_LAST=2767, + XED_IFORMFL_VDIVPH_FIRST=2768, + XED_IFORMFL_VDIVPH_LAST=2773, + XED_IFORMFL_VDIVPS_FIRST=2774, + XED_IFORMFL_VDIVPS_LAST=2783, + XED_IFORMFL_VDIVSD_FIRST=2784, + XED_IFORMFL_VDIVSD_LAST=2787, + XED_IFORMFL_VDIVSH_FIRST=2788, + XED_IFORMFL_VDIVSH_LAST=2789, + XED_IFORMFL_VDIVSS_FIRST=2790, + XED_IFORMFL_VDIVSS_LAST=2793, + XED_IFORMFL_VDPBF16PS_FIRST=2794, + XED_IFORMFL_VDPBF16PS_LAST=2799, + XED_IFORMFL_VDPPD_FIRST=2800, + XED_IFORMFL_VDPPD_LAST=2801, + XED_IFORMFL_VDPPS_FIRST=2802, + XED_IFORMFL_VDPPS_LAST=2805, + XED_IFORMFL_VERR_FIRST=2806, + XED_IFORMFL_VERR_LAST=2807, + XED_IFORMFL_VERW_FIRST=2808, + XED_IFORMFL_VERW_LAST=2809, + XED_IFORMFL_VEXP2PD_FIRST=2810, + XED_IFORMFL_VEXP2PD_LAST=2811, + XED_IFORMFL_VEXP2PS_FIRST=2812, + XED_IFORMFL_VEXP2PS_LAST=2813, + XED_IFORMFL_VEXPANDPD_FIRST=2814, + XED_IFORMFL_VEXPANDPD_LAST=2819, + XED_IFORMFL_VEXPANDPS_FIRST=2820, + XED_IFORMFL_VEXPANDPS_LAST=2825, + XED_IFORMFL_VEXTRACTF128_FIRST=2826, + XED_IFORMFL_VEXTRACTF128_LAST=2827, + XED_IFORMFL_VEXTRACTF32X4_FIRST=2828, + XED_IFORMFL_VEXTRACTF32X4_LAST=2831, + XED_IFORMFL_VEXTRACTF32X8_FIRST=2832, + XED_IFORMFL_VEXTRACTF32X8_LAST=2833, + XED_IFORMFL_VEXTRACTF64X2_FIRST=2834, + XED_IFORMFL_VEXTRACTF64X2_LAST=2837, + XED_IFORMFL_VEXTRACTF64X4_FIRST=2838, + XED_IFORMFL_VEXTRACTF64X4_LAST=2839, + XED_IFORMFL_VEXTRACTI128_FIRST=2840, + XED_IFORMFL_VEXTRACTI128_LAST=2841, + XED_IFORMFL_VEXTRACTI32X4_FIRST=2842, + XED_IFORMFL_VEXTRACTI32X4_LAST=2845, + XED_IFORMFL_VEXTRACTI32X8_FIRST=2846, + XED_IFORMFL_VEXTRACTI32X8_LAST=2847, + XED_IFORMFL_VEXTRACTI64X2_FIRST=2848, + XED_IFORMFL_VEXTRACTI64X2_LAST=2851, + XED_IFORMFL_VEXTRACTI64X4_FIRST=2852, + XED_IFORMFL_VEXTRACTI64X4_LAST=2853, + XED_IFORMFL_VEXTRACTPS_FIRST=2854, + XED_IFORMFL_VEXTRACTPS_LAST=2857, + XED_IFORMFL_VFCMADDCPH_FIRST=2858, + XED_IFORMFL_VFCMADDCPH_LAST=2863, + XED_IFORMFL_VFCMADDCSH_FIRST=2864, + XED_IFORMFL_VFCMADDCSH_LAST=2865, + XED_IFORMFL_VFCMULCPH_FIRST=2866, + XED_IFORMFL_VFCMULCPH_LAST=2871, + XED_IFORMFL_VFCMULCSH_FIRST=2872, + XED_IFORMFL_VFCMULCSH_LAST=2873, + XED_IFORMFL_VFIXUPIMMPD_FIRST=2874, + XED_IFORMFL_VFIXUPIMMPD_LAST=2879, + XED_IFORMFL_VFIXUPIMMPS_FIRST=2880, + XED_IFORMFL_VFIXUPIMMPS_LAST=2885, + XED_IFORMFL_VFIXUPIMMSD_FIRST=2886, + XED_IFORMFL_VFIXUPIMMSD_LAST=2887, + XED_IFORMFL_VFIXUPIMMSS_FIRST=2888, + XED_IFORMFL_VFIXUPIMMSS_LAST=2889, + XED_IFORMFL_VFMADD132PD_FIRST=2890, + XED_IFORMFL_VFMADD132PD_LAST=2899, + XED_IFORMFL_VFMADD132PH_FIRST=2900, + XED_IFORMFL_VFMADD132PH_LAST=2905, + XED_IFORMFL_VFMADD132PS_FIRST=2906, + XED_IFORMFL_VFMADD132PS_LAST=2915, + XED_IFORMFL_VFMADD132SD_FIRST=2916, + XED_IFORMFL_VFMADD132SD_LAST=2919, + XED_IFORMFL_VFMADD132SH_FIRST=2920, + XED_IFORMFL_VFMADD132SH_LAST=2921, + XED_IFORMFL_VFMADD132SS_FIRST=2922, + XED_IFORMFL_VFMADD132SS_LAST=2925, + XED_IFORMFL_VFMADD213PD_FIRST=2926, + XED_IFORMFL_VFMADD213PD_LAST=2935, + XED_IFORMFL_VFMADD213PH_FIRST=2936, + XED_IFORMFL_VFMADD213PH_LAST=2941, + XED_IFORMFL_VFMADD213PS_FIRST=2942, + XED_IFORMFL_VFMADD213PS_LAST=2951, + XED_IFORMFL_VFMADD213SD_FIRST=2952, + XED_IFORMFL_VFMADD213SD_LAST=2955, + XED_IFORMFL_VFMADD213SH_FIRST=2956, + XED_IFORMFL_VFMADD213SH_LAST=2957, + XED_IFORMFL_VFMADD213SS_FIRST=2958, + XED_IFORMFL_VFMADD213SS_LAST=2961, + XED_IFORMFL_VFMADD231PD_FIRST=2962, + XED_IFORMFL_VFMADD231PD_LAST=2971, + XED_IFORMFL_VFMADD231PH_FIRST=2972, + XED_IFORMFL_VFMADD231PH_LAST=2977, + XED_IFORMFL_VFMADD231PS_FIRST=2978, + XED_IFORMFL_VFMADD231PS_LAST=2987, + XED_IFORMFL_VFMADD231SD_FIRST=2988, + XED_IFORMFL_VFMADD231SD_LAST=2991, + XED_IFORMFL_VFMADD231SH_FIRST=2992, + XED_IFORMFL_VFMADD231SH_LAST=2993, + XED_IFORMFL_VFMADD231SS_FIRST=2994, + XED_IFORMFL_VFMADD231SS_LAST=2997, + XED_IFORMFL_VFMADDCPH_FIRST=2998, + XED_IFORMFL_VFMADDCPH_LAST=3003, + XED_IFORMFL_VFMADDCSH_FIRST=3004, + XED_IFORMFL_VFMADDCSH_LAST=3005, + XED_IFORMFL_VFMADDPD_FIRST=3006, + XED_IFORMFL_VFMADDPD_LAST=3011, + XED_IFORMFL_VFMADDPS_FIRST=3012, + XED_IFORMFL_VFMADDPS_LAST=3017, + XED_IFORMFL_VFMADDSD_FIRST=3018, + XED_IFORMFL_VFMADDSD_LAST=3020, + XED_IFORMFL_VFMADDSS_FIRST=3021, + XED_IFORMFL_VFMADDSS_LAST=3023, + XED_IFORMFL_VFMADDSUB132PD_FIRST=3024, + XED_IFORMFL_VFMADDSUB132PD_LAST=3033, + XED_IFORMFL_VFMADDSUB132PH_FIRST=3034, + XED_IFORMFL_VFMADDSUB132PH_LAST=3039, + XED_IFORMFL_VFMADDSUB132PS_FIRST=3040, + XED_IFORMFL_VFMADDSUB132PS_LAST=3049, + XED_IFORMFL_VFMADDSUB213PD_FIRST=3050, + XED_IFORMFL_VFMADDSUB213PD_LAST=3059, + XED_IFORMFL_VFMADDSUB213PH_FIRST=3060, + XED_IFORMFL_VFMADDSUB213PH_LAST=3065, + XED_IFORMFL_VFMADDSUB213PS_FIRST=3066, + XED_IFORMFL_VFMADDSUB213PS_LAST=3075, + XED_IFORMFL_VFMADDSUB231PD_FIRST=3076, + XED_IFORMFL_VFMADDSUB231PD_LAST=3085, + XED_IFORMFL_VFMADDSUB231PH_FIRST=3086, + XED_IFORMFL_VFMADDSUB231PH_LAST=3091, + XED_IFORMFL_VFMADDSUB231PS_FIRST=3092, + XED_IFORMFL_VFMADDSUB231PS_LAST=3101, + XED_IFORMFL_VFMADDSUBPD_FIRST=3102, + XED_IFORMFL_VFMADDSUBPD_LAST=3107, + XED_IFORMFL_VFMADDSUBPS_FIRST=3108, + XED_IFORMFL_VFMADDSUBPS_LAST=3113, + XED_IFORMFL_VFMSUB132PD_FIRST=3114, + XED_IFORMFL_VFMSUB132PD_LAST=3123, + XED_IFORMFL_VFMSUB132PH_FIRST=3124, + XED_IFORMFL_VFMSUB132PH_LAST=3129, + XED_IFORMFL_VFMSUB132PS_FIRST=3130, + XED_IFORMFL_VFMSUB132PS_LAST=3139, + XED_IFORMFL_VFMSUB132SD_FIRST=3140, + XED_IFORMFL_VFMSUB132SD_LAST=3143, + XED_IFORMFL_VFMSUB132SH_FIRST=3144, + XED_IFORMFL_VFMSUB132SH_LAST=3145, + XED_IFORMFL_VFMSUB132SS_FIRST=3146, + XED_IFORMFL_VFMSUB132SS_LAST=3149, + XED_IFORMFL_VFMSUB213PD_FIRST=3150, + XED_IFORMFL_VFMSUB213PD_LAST=3159, + XED_IFORMFL_VFMSUB213PH_FIRST=3160, + XED_IFORMFL_VFMSUB213PH_LAST=3165, + XED_IFORMFL_VFMSUB213PS_FIRST=3166, + XED_IFORMFL_VFMSUB213PS_LAST=3175, + XED_IFORMFL_VFMSUB213SD_FIRST=3176, + XED_IFORMFL_VFMSUB213SD_LAST=3179, + XED_IFORMFL_VFMSUB213SH_FIRST=3180, + XED_IFORMFL_VFMSUB213SH_LAST=3181, + XED_IFORMFL_VFMSUB213SS_FIRST=3182, + XED_IFORMFL_VFMSUB213SS_LAST=3185, + XED_IFORMFL_VFMSUB231PD_FIRST=3186, + XED_IFORMFL_VFMSUB231PD_LAST=3195, + XED_IFORMFL_VFMSUB231PH_FIRST=3196, + XED_IFORMFL_VFMSUB231PH_LAST=3201, + XED_IFORMFL_VFMSUB231PS_FIRST=3202, + XED_IFORMFL_VFMSUB231PS_LAST=3211, + XED_IFORMFL_VFMSUB231SD_FIRST=3212, + XED_IFORMFL_VFMSUB231SD_LAST=3215, + XED_IFORMFL_VFMSUB231SH_FIRST=3216, + XED_IFORMFL_VFMSUB231SH_LAST=3217, + XED_IFORMFL_VFMSUB231SS_FIRST=3218, + XED_IFORMFL_VFMSUB231SS_LAST=3221, + XED_IFORMFL_VFMSUBADD132PD_FIRST=3222, + XED_IFORMFL_VFMSUBADD132PD_LAST=3231, + XED_IFORMFL_VFMSUBADD132PH_FIRST=3232, + XED_IFORMFL_VFMSUBADD132PH_LAST=3237, + XED_IFORMFL_VFMSUBADD132PS_FIRST=3238, + XED_IFORMFL_VFMSUBADD132PS_LAST=3247, + XED_IFORMFL_VFMSUBADD213PD_FIRST=3248, + XED_IFORMFL_VFMSUBADD213PD_LAST=3257, + XED_IFORMFL_VFMSUBADD213PH_FIRST=3258, + XED_IFORMFL_VFMSUBADD213PH_LAST=3263, + XED_IFORMFL_VFMSUBADD213PS_FIRST=3264, + XED_IFORMFL_VFMSUBADD213PS_LAST=3273, + XED_IFORMFL_VFMSUBADD231PD_FIRST=3274, + XED_IFORMFL_VFMSUBADD231PD_LAST=3283, + XED_IFORMFL_VFMSUBADD231PH_FIRST=3284, + XED_IFORMFL_VFMSUBADD231PH_LAST=3289, + XED_IFORMFL_VFMSUBADD231PS_FIRST=3290, + XED_IFORMFL_VFMSUBADD231PS_LAST=3299, + XED_IFORMFL_VFMSUBADDPD_FIRST=3300, + XED_IFORMFL_VFMSUBADDPD_LAST=3305, + XED_IFORMFL_VFMSUBADDPS_FIRST=3306, + XED_IFORMFL_VFMSUBADDPS_LAST=3311, + XED_IFORMFL_VFMSUBPD_FIRST=3312, + XED_IFORMFL_VFMSUBPD_LAST=3317, + XED_IFORMFL_VFMSUBPS_FIRST=3318, + XED_IFORMFL_VFMSUBPS_LAST=3323, + XED_IFORMFL_VFMSUBSD_FIRST=3324, + XED_IFORMFL_VFMSUBSD_LAST=3326, + XED_IFORMFL_VFMSUBSS_FIRST=3327, + XED_IFORMFL_VFMSUBSS_LAST=3329, + XED_IFORMFL_VFMULCPH_FIRST=3330, + XED_IFORMFL_VFMULCPH_LAST=3335, + XED_IFORMFL_VFMULCSH_FIRST=3336, + XED_IFORMFL_VFMULCSH_LAST=3337, + XED_IFORMFL_VFNMADD132PD_FIRST=3338, + XED_IFORMFL_VFNMADD132PD_LAST=3347, + XED_IFORMFL_VFNMADD132PH_FIRST=3348, + XED_IFORMFL_VFNMADD132PH_LAST=3353, + XED_IFORMFL_VFNMADD132PS_FIRST=3354, + XED_IFORMFL_VFNMADD132PS_LAST=3363, + XED_IFORMFL_VFNMADD132SD_FIRST=3364, + XED_IFORMFL_VFNMADD132SD_LAST=3367, + XED_IFORMFL_VFNMADD132SH_FIRST=3368, + XED_IFORMFL_VFNMADD132SH_LAST=3369, + XED_IFORMFL_VFNMADD132SS_FIRST=3370, + XED_IFORMFL_VFNMADD132SS_LAST=3373, + XED_IFORMFL_VFNMADD213PD_FIRST=3374, + XED_IFORMFL_VFNMADD213PD_LAST=3383, + XED_IFORMFL_VFNMADD213PH_FIRST=3384, + XED_IFORMFL_VFNMADD213PH_LAST=3389, + XED_IFORMFL_VFNMADD213PS_FIRST=3390, + XED_IFORMFL_VFNMADD213PS_LAST=3399, + XED_IFORMFL_VFNMADD213SD_FIRST=3400, + XED_IFORMFL_VFNMADD213SD_LAST=3403, + XED_IFORMFL_VFNMADD213SH_FIRST=3404, + XED_IFORMFL_VFNMADD213SH_LAST=3405, + XED_IFORMFL_VFNMADD213SS_FIRST=3406, + XED_IFORMFL_VFNMADD213SS_LAST=3409, + XED_IFORMFL_VFNMADD231PD_FIRST=3410, + XED_IFORMFL_VFNMADD231PD_LAST=3419, + XED_IFORMFL_VFNMADD231PH_FIRST=3420, + XED_IFORMFL_VFNMADD231PH_LAST=3425, + XED_IFORMFL_VFNMADD231PS_FIRST=3426, + XED_IFORMFL_VFNMADD231PS_LAST=3435, + XED_IFORMFL_VFNMADD231SD_FIRST=3436, + XED_IFORMFL_VFNMADD231SD_LAST=3439, + XED_IFORMFL_VFNMADD231SH_FIRST=3440, + XED_IFORMFL_VFNMADD231SH_LAST=3441, + XED_IFORMFL_VFNMADD231SS_FIRST=3442, + XED_IFORMFL_VFNMADD231SS_LAST=3445, + XED_IFORMFL_VFNMADDPD_FIRST=3446, + XED_IFORMFL_VFNMADDPD_LAST=3451, + XED_IFORMFL_VFNMADDPS_FIRST=3452, + XED_IFORMFL_VFNMADDPS_LAST=3457, + XED_IFORMFL_VFNMADDSD_FIRST=3458, + XED_IFORMFL_VFNMADDSD_LAST=3460, + XED_IFORMFL_VFNMADDSS_FIRST=3461, + XED_IFORMFL_VFNMADDSS_LAST=3463, + XED_IFORMFL_VFNMSUB132PD_FIRST=3464, + XED_IFORMFL_VFNMSUB132PD_LAST=3473, + XED_IFORMFL_VFNMSUB132PH_FIRST=3474, + XED_IFORMFL_VFNMSUB132PH_LAST=3479, + XED_IFORMFL_VFNMSUB132PS_FIRST=3480, + XED_IFORMFL_VFNMSUB132PS_LAST=3489, + XED_IFORMFL_VFNMSUB132SD_FIRST=3490, + XED_IFORMFL_VFNMSUB132SD_LAST=3493, + XED_IFORMFL_VFNMSUB132SH_FIRST=3494, + XED_IFORMFL_VFNMSUB132SH_LAST=3495, + XED_IFORMFL_VFNMSUB132SS_FIRST=3496, + XED_IFORMFL_VFNMSUB132SS_LAST=3499, + XED_IFORMFL_VFNMSUB213PD_FIRST=3500, + XED_IFORMFL_VFNMSUB213PD_LAST=3509, + XED_IFORMFL_VFNMSUB213PH_FIRST=3510, + XED_IFORMFL_VFNMSUB213PH_LAST=3515, + XED_IFORMFL_VFNMSUB213PS_FIRST=3516, + XED_IFORMFL_VFNMSUB213PS_LAST=3525, + XED_IFORMFL_VFNMSUB213SD_FIRST=3526, + XED_IFORMFL_VFNMSUB213SD_LAST=3529, + XED_IFORMFL_VFNMSUB213SH_FIRST=3530, + XED_IFORMFL_VFNMSUB213SH_LAST=3531, + XED_IFORMFL_VFNMSUB213SS_FIRST=3532, + XED_IFORMFL_VFNMSUB213SS_LAST=3535, + XED_IFORMFL_VFNMSUB231PD_FIRST=3536, + XED_IFORMFL_VFNMSUB231PD_LAST=3545, + XED_IFORMFL_VFNMSUB231PH_FIRST=3546, + XED_IFORMFL_VFNMSUB231PH_LAST=3551, + XED_IFORMFL_VFNMSUB231PS_FIRST=3552, + XED_IFORMFL_VFNMSUB231PS_LAST=3561, + XED_IFORMFL_VFNMSUB231SD_FIRST=3562, + XED_IFORMFL_VFNMSUB231SD_LAST=3565, + XED_IFORMFL_VFNMSUB231SH_FIRST=3566, + XED_IFORMFL_VFNMSUB231SH_LAST=3567, + XED_IFORMFL_VFNMSUB231SS_FIRST=3568, + XED_IFORMFL_VFNMSUB231SS_LAST=3571, + XED_IFORMFL_VFNMSUBPD_FIRST=3572, + XED_IFORMFL_VFNMSUBPD_LAST=3577, + XED_IFORMFL_VFNMSUBPS_FIRST=3578, + XED_IFORMFL_VFNMSUBPS_LAST=3583, + XED_IFORMFL_VFNMSUBSD_FIRST=3584, + XED_IFORMFL_VFNMSUBSD_LAST=3586, + XED_IFORMFL_VFNMSUBSS_FIRST=3587, + XED_IFORMFL_VFNMSUBSS_LAST=3589, + XED_IFORMFL_VFPCLASSPD_FIRST=3590, + XED_IFORMFL_VFPCLASSPD_LAST=3595, + XED_IFORMFL_VFPCLASSPH_FIRST=3596, + XED_IFORMFL_VFPCLASSPH_LAST=3601, + XED_IFORMFL_VFPCLASSPS_FIRST=3602, + XED_IFORMFL_VFPCLASSPS_LAST=3607, + XED_IFORMFL_VFPCLASSSD_FIRST=3608, + XED_IFORMFL_VFPCLASSSD_LAST=3609, + XED_IFORMFL_VFPCLASSSH_FIRST=3610, + XED_IFORMFL_VFPCLASSSH_LAST=3611, + XED_IFORMFL_VFPCLASSSS_FIRST=3612, + XED_IFORMFL_VFPCLASSSS_LAST=3613, + XED_IFORMFL_VFRCZPD_FIRST=3614, + XED_IFORMFL_VFRCZPD_LAST=3617, + XED_IFORMFL_VFRCZPS_FIRST=3618, + XED_IFORMFL_VFRCZPS_LAST=3621, + XED_IFORMFL_VFRCZSD_FIRST=3622, + XED_IFORMFL_VFRCZSD_LAST=3623, + XED_IFORMFL_VFRCZSS_FIRST=3624, + XED_IFORMFL_VFRCZSS_LAST=3625, + XED_IFORMFL_VGATHERDPD_FIRST=3626, + XED_IFORMFL_VGATHERDPD_LAST=3630, + XED_IFORMFL_VGATHERDPS_FIRST=3631, + XED_IFORMFL_VGATHERDPS_LAST=3635, + XED_IFORMFL_VGATHERPF0DPD_FIRST=3636, + XED_IFORMFL_VGATHERPF0DPD_LAST=3636, + XED_IFORMFL_VGATHERPF0DPS_FIRST=3637, + XED_IFORMFL_VGATHERPF0DPS_LAST=3637, + XED_IFORMFL_VGATHERPF0QPD_FIRST=3638, + XED_IFORMFL_VGATHERPF0QPD_LAST=3638, + XED_IFORMFL_VGATHERPF0QPS_FIRST=3639, + XED_IFORMFL_VGATHERPF0QPS_LAST=3639, + XED_IFORMFL_VGATHERPF1DPD_FIRST=3640, + XED_IFORMFL_VGATHERPF1DPD_LAST=3640, + XED_IFORMFL_VGATHERPF1DPS_FIRST=3641, + XED_IFORMFL_VGATHERPF1DPS_LAST=3641, + XED_IFORMFL_VGATHERPF1QPD_FIRST=3642, + XED_IFORMFL_VGATHERPF1QPD_LAST=3642, + XED_IFORMFL_VGATHERPF1QPS_FIRST=3643, + XED_IFORMFL_VGATHERPF1QPS_LAST=3643, + XED_IFORMFL_VGATHERQPD_FIRST=3644, + XED_IFORMFL_VGATHERQPD_LAST=3648, + XED_IFORMFL_VGATHERQPS_FIRST=3649, + XED_IFORMFL_VGATHERQPS_LAST=3653, + XED_IFORMFL_VGETEXPPD_FIRST=3654, + XED_IFORMFL_VGETEXPPD_LAST=3659, + XED_IFORMFL_VGETEXPPH_FIRST=3660, + XED_IFORMFL_VGETEXPPH_LAST=3665, + XED_IFORMFL_VGETEXPPS_FIRST=3666, + XED_IFORMFL_VGETEXPPS_LAST=3671, + XED_IFORMFL_VGETEXPSD_FIRST=3672, + XED_IFORMFL_VGETEXPSD_LAST=3673, + XED_IFORMFL_VGETEXPSH_FIRST=3674, + XED_IFORMFL_VGETEXPSH_LAST=3675, + XED_IFORMFL_VGETEXPSS_FIRST=3676, + XED_IFORMFL_VGETEXPSS_LAST=3677, + XED_IFORMFL_VGETMANTPD_FIRST=3678, + XED_IFORMFL_VGETMANTPD_LAST=3683, + XED_IFORMFL_VGETMANTPH_FIRST=3684, + XED_IFORMFL_VGETMANTPH_LAST=3689, + XED_IFORMFL_VGETMANTPS_FIRST=3690, + XED_IFORMFL_VGETMANTPS_LAST=3695, + XED_IFORMFL_VGETMANTSD_FIRST=3696, + XED_IFORMFL_VGETMANTSD_LAST=3697, + XED_IFORMFL_VGETMANTSH_FIRST=3698, + XED_IFORMFL_VGETMANTSH_LAST=3699, + XED_IFORMFL_VGETMANTSS_FIRST=3700, + XED_IFORMFL_VGETMANTSS_LAST=3701, + XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST=3702, + XED_IFORMFL_VGF2P8AFFINEINVQB_LAST=3711, + XED_IFORMFL_VGF2P8AFFINEQB_FIRST=3712, + XED_IFORMFL_VGF2P8AFFINEQB_LAST=3721, + XED_IFORMFL_VGF2P8MULB_FIRST=3722, + XED_IFORMFL_VGF2P8MULB_LAST=3731, + XED_IFORMFL_VHADDPD_FIRST=3732, + XED_IFORMFL_VHADDPD_LAST=3735, + XED_IFORMFL_VHADDPS_FIRST=3736, + XED_IFORMFL_VHADDPS_LAST=3739, + XED_IFORMFL_VHSUBPD_FIRST=3740, + XED_IFORMFL_VHSUBPD_LAST=3743, + XED_IFORMFL_VHSUBPS_FIRST=3744, + XED_IFORMFL_VHSUBPS_LAST=3747, + XED_IFORMFL_VINSERTF128_FIRST=3748, + XED_IFORMFL_VINSERTF128_LAST=3749, + XED_IFORMFL_VINSERTF32X4_FIRST=3750, + XED_IFORMFL_VINSERTF32X4_LAST=3753, + XED_IFORMFL_VINSERTF32X8_FIRST=3754, + XED_IFORMFL_VINSERTF32X8_LAST=3755, + XED_IFORMFL_VINSERTF64X2_FIRST=3756, + XED_IFORMFL_VINSERTF64X2_LAST=3759, + XED_IFORMFL_VINSERTF64X4_FIRST=3760, + XED_IFORMFL_VINSERTF64X4_LAST=3761, + XED_IFORMFL_VINSERTI128_FIRST=3762, + XED_IFORMFL_VINSERTI128_LAST=3763, + XED_IFORMFL_VINSERTI32X4_FIRST=3764, + XED_IFORMFL_VINSERTI32X4_LAST=3767, + XED_IFORMFL_VINSERTI32X8_FIRST=3768, + XED_IFORMFL_VINSERTI32X8_LAST=3769, + XED_IFORMFL_VINSERTI64X2_FIRST=3770, + XED_IFORMFL_VINSERTI64X2_LAST=3773, + XED_IFORMFL_VINSERTI64X4_FIRST=3774, + XED_IFORMFL_VINSERTI64X4_LAST=3775, + XED_IFORMFL_VINSERTPS_FIRST=3776, + XED_IFORMFL_VINSERTPS_LAST=3779, + XED_IFORMFL_VLDDQU_FIRST=3780, + XED_IFORMFL_VLDDQU_LAST=3781, + XED_IFORMFL_VLDMXCSR_FIRST=3782, + XED_IFORMFL_VLDMXCSR_LAST=3782, + XED_IFORMFL_VMASKMOVDQU_FIRST=3783, + XED_IFORMFL_VMASKMOVDQU_LAST=3783, + XED_IFORMFL_VMASKMOVPD_FIRST=3784, + XED_IFORMFL_VMASKMOVPD_LAST=3787, + XED_IFORMFL_VMASKMOVPS_FIRST=3788, + XED_IFORMFL_VMASKMOVPS_LAST=3791, + XED_IFORMFL_VMAXPD_FIRST=3792, + XED_IFORMFL_VMAXPD_LAST=3801, + XED_IFORMFL_VMAXPH_FIRST=3802, + XED_IFORMFL_VMAXPH_LAST=3807, + XED_IFORMFL_VMAXPS_FIRST=3808, + XED_IFORMFL_VMAXPS_LAST=3817, + XED_IFORMFL_VMAXSD_FIRST=3818, + XED_IFORMFL_VMAXSD_LAST=3821, + XED_IFORMFL_VMAXSH_FIRST=3822, + XED_IFORMFL_VMAXSH_LAST=3823, + XED_IFORMFL_VMAXSS_FIRST=3824, + XED_IFORMFL_VMAXSS_LAST=3827, + XED_IFORMFL_VMCALL_FIRST=3828, + XED_IFORMFL_VMCALL_LAST=3828, + XED_IFORMFL_VMCLEAR_FIRST=3829, + XED_IFORMFL_VMCLEAR_LAST=3829, + XED_IFORMFL_VMFUNC_FIRST=3830, + XED_IFORMFL_VMFUNC_LAST=3830, + XED_IFORMFL_VMINPD_FIRST=3831, + XED_IFORMFL_VMINPD_LAST=3840, + XED_IFORMFL_VMINPH_FIRST=3841, + XED_IFORMFL_VMINPH_LAST=3846, + XED_IFORMFL_VMINPS_FIRST=3847, + XED_IFORMFL_VMINPS_LAST=3856, + XED_IFORMFL_VMINSD_FIRST=3857, + XED_IFORMFL_VMINSD_LAST=3860, + XED_IFORMFL_VMINSH_FIRST=3861, + XED_IFORMFL_VMINSH_LAST=3862, + XED_IFORMFL_VMINSS_FIRST=3863, + XED_IFORMFL_VMINSS_LAST=3866, + XED_IFORMFL_VMLAUNCH_FIRST=3867, + XED_IFORMFL_VMLAUNCH_LAST=3867, + XED_IFORMFL_VMLOAD_FIRST=3868, + XED_IFORMFL_VMLOAD_LAST=3868, + XED_IFORMFL_VMMCALL_FIRST=3869, + XED_IFORMFL_VMMCALL_LAST=3869, + XED_IFORMFL_VMOVAPD_FIRST=3870, + XED_IFORMFL_VMOVAPD_LAST=3886, + XED_IFORMFL_VMOVAPS_FIRST=3887, + XED_IFORMFL_VMOVAPS_LAST=3903, + XED_IFORMFL_VMOVD_FIRST=3904, + XED_IFORMFL_VMOVD_LAST=3911, + XED_IFORMFL_VMOVDDUP_FIRST=3912, + XED_IFORMFL_VMOVDDUP_LAST=3921, + XED_IFORMFL_VMOVDQA_FIRST=3922, + XED_IFORMFL_VMOVDQA_LAST=3929, + XED_IFORMFL_VMOVDQA32_FIRST=3930, + XED_IFORMFL_VMOVDQA32_LAST=3938, + XED_IFORMFL_VMOVDQA64_FIRST=3939, + XED_IFORMFL_VMOVDQA64_LAST=3947, + XED_IFORMFL_VMOVDQU_FIRST=3948, + XED_IFORMFL_VMOVDQU_LAST=3955, + XED_IFORMFL_VMOVDQU16_FIRST=3956, + XED_IFORMFL_VMOVDQU16_LAST=3964, + XED_IFORMFL_VMOVDQU32_FIRST=3965, + XED_IFORMFL_VMOVDQU32_LAST=3973, + XED_IFORMFL_VMOVDQU64_FIRST=3974, + XED_IFORMFL_VMOVDQU64_LAST=3982, + XED_IFORMFL_VMOVDQU8_FIRST=3983, + XED_IFORMFL_VMOVDQU8_LAST=3991, + XED_IFORMFL_VMOVHLPS_FIRST=3992, + XED_IFORMFL_VMOVHLPS_LAST=3993, + XED_IFORMFL_VMOVHPD_FIRST=3994, + XED_IFORMFL_VMOVHPD_LAST=3997, + XED_IFORMFL_VMOVHPS_FIRST=3998, + XED_IFORMFL_VMOVHPS_LAST=4001, + XED_IFORMFL_VMOVLHPS_FIRST=4002, + XED_IFORMFL_VMOVLHPS_LAST=4003, + XED_IFORMFL_VMOVLPD_FIRST=4004, + XED_IFORMFL_VMOVLPD_LAST=4007, + XED_IFORMFL_VMOVLPS_FIRST=4008, + XED_IFORMFL_VMOVLPS_LAST=4011, + XED_IFORMFL_VMOVMSKPD_FIRST=4012, + XED_IFORMFL_VMOVMSKPD_LAST=4013, + XED_IFORMFL_VMOVMSKPS_FIRST=4014, + XED_IFORMFL_VMOVMSKPS_LAST=4015, + XED_IFORMFL_VMOVNTDQ_FIRST=4016, + XED_IFORMFL_VMOVNTDQ_LAST=4020, + XED_IFORMFL_VMOVNTDQA_FIRST=4021, + XED_IFORMFL_VMOVNTDQA_LAST=4025, + XED_IFORMFL_VMOVNTPD_FIRST=4026, + XED_IFORMFL_VMOVNTPD_LAST=4030, + XED_IFORMFL_VMOVNTPS_FIRST=4031, + XED_IFORMFL_VMOVNTPS_LAST=4035, + XED_IFORMFL_VMOVQ_FIRST=4036, + XED_IFORMFL_VMOVQ_LAST=4048, + XED_IFORMFL_VMOVSD_FIRST=4049, + XED_IFORMFL_VMOVSD_LAST=4055, + XED_IFORMFL_VMOVSH_FIRST=4056, + XED_IFORMFL_VMOVSH_LAST=4058, + XED_IFORMFL_VMOVSHDUP_FIRST=4059, + XED_IFORMFL_VMOVSHDUP_LAST=4068, + XED_IFORMFL_VMOVSLDUP_FIRST=4069, + XED_IFORMFL_VMOVSLDUP_LAST=4078, + XED_IFORMFL_VMOVSS_FIRST=4079, + XED_IFORMFL_VMOVSS_LAST=4085, + XED_IFORMFL_VMOVUPD_FIRST=4086, + XED_IFORMFL_VMOVUPD_LAST=4102, + XED_IFORMFL_VMOVUPS_FIRST=4103, + XED_IFORMFL_VMOVUPS_LAST=4119, + XED_IFORMFL_VMOVW_FIRST=4120, + XED_IFORMFL_VMOVW_LAST=4123, + XED_IFORMFL_VMPSADBW_FIRST=4124, + XED_IFORMFL_VMPSADBW_LAST=4127, + XED_IFORMFL_VMPTRLD_FIRST=4128, + XED_IFORMFL_VMPTRLD_LAST=4128, + XED_IFORMFL_VMPTRST_FIRST=4129, + XED_IFORMFL_VMPTRST_LAST=4129, + XED_IFORMFL_VMREAD_FIRST=4130, + XED_IFORMFL_VMREAD_LAST=4133, + XED_IFORMFL_VMRESUME_FIRST=4134, + XED_IFORMFL_VMRESUME_LAST=4134, + XED_IFORMFL_VMRUN_FIRST=4135, + XED_IFORMFL_VMRUN_LAST=4135, + XED_IFORMFL_VMSAVE_FIRST=4136, + XED_IFORMFL_VMSAVE_LAST=4136, + XED_IFORMFL_VMULPD_FIRST=4137, + XED_IFORMFL_VMULPD_LAST=4146, + XED_IFORMFL_VMULPH_FIRST=4147, + XED_IFORMFL_VMULPH_LAST=4152, + XED_IFORMFL_VMULPS_FIRST=4153, + XED_IFORMFL_VMULPS_LAST=4162, + XED_IFORMFL_VMULSD_FIRST=4163, + XED_IFORMFL_VMULSD_LAST=4166, + XED_IFORMFL_VMULSH_FIRST=4167, + XED_IFORMFL_VMULSH_LAST=4168, + XED_IFORMFL_VMULSS_FIRST=4169, + XED_IFORMFL_VMULSS_LAST=4172, + XED_IFORMFL_VMWRITE_FIRST=4173, + XED_IFORMFL_VMWRITE_LAST=4176, + XED_IFORMFL_VMXOFF_FIRST=4177, + XED_IFORMFL_VMXOFF_LAST=4177, + XED_IFORMFL_VMXON_FIRST=4178, + XED_IFORMFL_VMXON_LAST=4178, + XED_IFORMFL_VORPD_FIRST=4179, + XED_IFORMFL_VORPD_LAST=4188, + XED_IFORMFL_VORPS_FIRST=4189, + XED_IFORMFL_VORPS_LAST=4198, + XED_IFORMFL_VP2INTERSECTD_FIRST=4199, + XED_IFORMFL_VP2INTERSECTD_LAST=4204, + XED_IFORMFL_VP2INTERSECTQ_FIRST=4205, + XED_IFORMFL_VP2INTERSECTQ_LAST=4210, + XED_IFORMFL_VP4DPWSSD_FIRST=4211, + XED_IFORMFL_VP4DPWSSD_LAST=4211, + XED_IFORMFL_VP4DPWSSDS_FIRST=4212, + XED_IFORMFL_VP4DPWSSDS_LAST=4212, + XED_IFORMFL_VPABSB_FIRST=4213, + XED_IFORMFL_VPABSB_LAST=4222, + XED_IFORMFL_VPABSD_FIRST=4223, + XED_IFORMFL_VPABSD_LAST=4232, + XED_IFORMFL_VPABSQ_FIRST=4233, + XED_IFORMFL_VPABSQ_LAST=4238, + XED_IFORMFL_VPABSW_FIRST=4239, + XED_IFORMFL_VPABSW_LAST=4248, + XED_IFORMFL_VPACKSSDW_FIRST=4249, + XED_IFORMFL_VPACKSSDW_LAST=4258, + XED_IFORMFL_VPACKSSWB_FIRST=4259, + XED_IFORMFL_VPACKSSWB_LAST=4268, + XED_IFORMFL_VPACKUSDW_FIRST=4269, + XED_IFORMFL_VPACKUSDW_LAST=4278, + XED_IFORMFL_VPACKUSWB_FIRST=4279, + XED_IFORMFL_VPACKUSWB_LAST=4288, + XED_IFORMFL_VPADDB_FIRST=4289, + XED_IFORMFL_VPADDB_LAST=4298, + XED_IFORMFL_VPADDD_FIRST=4299, + XED_IFORMFL_VPADDD_LAST=4308, + XED_IFORMFL_VPADDQ_FIRST=4309, + XED_IFORMFL_VPADDQ_LAST=4318, + XED_IFORMFL_VPADDSB_FIRST=4319, + XED_IFORMFL_VPADDSB_LAST=4328, + XED_IFORMFL_VPADDSW_FIRST=4329, + XED_IFORMFL_VPADDSW_LAST=4338, + XED_IFORMFL_VPADDUSB_FIRST=4339, + XED_IFORMFL_VPADDUSB_LAST=4348, + XED_IFORMFL_VPADDUSW_FIRST=4349, + XED_IFORMFL_VPADDUSW_LAST=4358, + XED_IFORMFL_VPADDW_FIRST=4359, + XED_IFORMFL_VPADDW_LAST=4368, + XED_IFORMFL_VPALIGNR_FIRST=4369, + XED_IFORMFL_VPALIGNR_LAST=4378, + XED_IFORMFL_VPAND_FIRST=4379, + XED_IFORMFL_VPAND_LAST=4382, + XED_IFORMFL_VPANDD_FIRST=4383, + XED_IFORMFL_VPANDD_LAST=4388, + XED_IFORMFL_VPANDN_FIRST=4389, + XED_IFORMFL_VPANDN_LAST=4392, + XED_IFORMFL_VPANDND_FIRST=4393, + XED_IFORMFL_VPANDND_LAST=4398, + XED_IFORMFL_VPANDNQ_FIRST=4399, + XED_IFORMFL_VPANDNQ_LAST=4404, + XED_IFORMFL_VPANDQ_FIRST=4405, + XED_IFORMFL_VPANDQ_LAST=4410, + XED_IFORMFL_VPAVGB_FIRST=4411, + XED_IFORMFL_VPAVGB_LAST=4420, + XED_IFORMFL_VPAVGW_FIRST=4421, + XED_IFORMFL_VPAVGW_LAST=4430, + XED_IFORMFL_VPBLENDD_FIRST=4431, + XED_IFORMFL_VPBLENDD_LAST=4434, + XED_IFORMFL_VPBLENDMB_FIRST=4435, + XED_IFORMFL_VPBLENDMB_LAST=4440, + XED_IFORMFL_VPBLENDMD_FIRST=4441, + XED_IFORMFL_VPBLENDMD_LAST=4446, + XED_IFORMFL_VPBLENDMQ_FIRST=4447, + XED_IFORMFL_VPBLENDMQ_LAST=4452, + XED_IFORMFL_VPBLENDMW_FIRST=4453, + XED_IFORMFL_VPBLENDMW_LAST=4458, + XED_IFORMFL_VPBLENDVB_FIRST=4459, + XED_IFORMFL_VPBLENDVB_LAST=4462, + XED_IFORMFL_VPBLENDW_FIRST=4463, + XED_IFORMFL_VPBLENDW_LAST=4466, + XED_IFORMFL_VPBROADCASTB_FIRST=4467, + XED_IFORMFL_VPBROADCASTB_LAST=4479, + XED_IFORMFL_VPBROADCASTD_FIRST=4480, + XED_IFORMFL_VPBROADCASTD_LAST=4492, + XED_IFORMFL_VPBROADCASTMB2Q_FIRST=4493, + XED_IFORMFL_VPBROADCASTMB2Q_LAST=4495, + XED_IFORMFL_VPBROADCASTMW2D_FIRST=4496, + XED_IFORMFL_VPBROADCASTMW2D_LAST=4498, + XED_IFORMFL_VPBROADCASTQ_FIRST=4499, + XED_IFORMFL_VPBROADCASTQ_LAST=4511, + XED_IFORMFL_VPBROADCASTW_FIRST=4512, + XED_IFORMFL_VPBROADCASTW_LAST=4524, + XED_IFORMFL_VPCLMULQDQ_FIRST=4525, + XED_IFORMFL_VPCLMULQDQ_LAST=4534, + XED_IFORMFL_VPCMOV_FIRST=4535, + XED_IFORMFL_VPCMOV_LAST=4540, + XED_IFORMFL_VPCMPB_FIRST=4541, + XED_IFORMFL_VPCMPB_LAST=4546, + XED_IFORMFL_VPCMPD_FIRST=4547, + XED_IFORMFL_VPCMPD_LAST=4552, + XED_IFORMFL_VPCMPEQB_FIRST=4553, + XED_IFORMFL_VPCMPEQB_LAST=4562, + XED_IFORMFL_VPCMPEQD_FIRST=4563, + XED_IFORMFL_VPCMPEQD_LAST=4572, + XED_IFORMFL_VPCMPEQQ_FIRST=4573, + XED_IFORMFL_VPCMPEQQ_LAST=4582, + XED_IFORMFL_VPCMPEQW_FIRST=4583, + XED_IFORMFL_VPCMPEQW_LAST=4592, + XED_IFORMFL_VPCMPESTRI_FIRST=4593, + XED_IFORMFL_VPCMPESTRI_LAST=4594, + XED_IFORMFL_VPCMPESTRI64_FIRST=4595, + XED_IFORMFL_VPCMPESTRI64_LAST=4596, + XED_IFORMFL_VPCMPESTRM_FIRST=4597, + XED_IFORMFL_VPCMPESTRM_LAST=4598, + XED_IFORMFL_VPCMPESTRM64_FIRST=4599, + XED_IFORMFL_VPCMPESTRM64_LAST=4600, + XED_IFORMFL_VPCMPGTB_FIRST=4601, + XED_IFORMFL_VPCMPGTB_LAST=4610, + XED_IFORMFL_VPCMPGTD_FIRST=4611, + XED_IFORMFL_VPCMPGTD_LAST=4620, + XED_IFORMFL_VPCMPGTQ_FIRST=4621, + XED_IFORMFL_VPCMPGTQ_LAST=4630, + XED_IFORMFL_VPCMPGTW_FIRST=4631, + XED_IFORMFL_VPCMPGTW_LAST=4640, + XED_IFORMFL_VPCMPISTRI_FIRST=4641, + XED_IFORMFL_VPCMPISTRI_LAST=4642, + XED_IFORMFL_VPCMPISTRI64_FIRST=4643, + XED_IFORMFL_VPCMPISTRI64_LAST=4644, + XED_IFORMFL_VPCMPISTRM_FIRST=4645, + XED_IFORMFL_VPCMPISTRM_LAST=4646, + XED_IFORMFL_VPCMPQ_FIRST=4647, + XED_IFORMFL_VPCMPQ_LAST=4652, + XED_IFORMFL_VPCMPUB_FIRST=4653, + XED_IFORMFL_VPCMPUB_LAST=4658, + XED_IFORMFL_VPCMPUD_FIRST=4659, + XED_IFORMFL_VPCMPUD_LAST=4664, + XED_IFORMFL_VPCMPUQ_FIRST=4665, + XED_IFORMFL_VPCMPUQ_LAST=4670, + XED_IFORMFL_VPCMPUW_FIRST=4671, + XED_IFORMFL_VPCMPUW_LAST=4676, + XED_IFORMFL_VPCMPW_FIRST=4677, + XED_IFORMFL_VPCMPW_LAST=4682, + XED_IFORMFL_VPCOMB_FIRST=4683, + XED_IFORMFL_VPCOMB_LAST=4684, + XED_IFORMFL_VPCOMD_FIRST=4685, + XED_IFORMFL_VPCOMD_LAST=4686, + XED_IFORMFL_VPCOMPRESSB_FIRST=4687, + XED_IFORMFL_VPCOMPRESSB_LAST=4692, + XED_IFORMFL_VPCOMPRESSD_FIRST=4693, + XED_IFORMFL_VPCOMPRESSD_LAST=4698, + XED_IFORMFL_VPCOMPRESSQ_FIRST=4699, + XED_IFORMFL_VPCOMPRESSQ_LAST=4704, + XED_IFORMFL_VPCOMPRESSW_FIRST=4705, + XED_IFORMFL_VPCOMPRESSW_LAST=4710, + XED_IFORMFL_VPCOMQ_FIRST=4711, + XED_IFORMFL_VPCOMQ_LAST=4712, + XED_IFORMFL_VPCOMUB_FIRST=4713, + XED_IFORMFL_VPCOMUB_LAST=4714, + XED_IFORMFL_VPCOMUD_FIRST=4715, + XED_IFORMFL_VPCOMUD_LAST=4716, + XED_IFORMFL_VPCOMUQ_FIRST=4717, + XED_IFORMFL_VPCOMUQ_LAST=4718, + XED_IFORMFL_VPCOMUW_FIRST=4719, + XED_IFORMFL_VPCOMUW_LAST=4720, + XED_IFORMFL_VPCOMW_FIRST=4721, + XED_IFORMFL_VPCOMW_LAST=4722, + XED_IFORMFL_VPCONFLICTD_FIRST=4723, + XED_IFORMFL_VPCONFLICTD_LAST=4728, + XED_IFORMFL_VPCONFLICTQ_FIRST=4729, + XED_IFORMFL_VPCONFLICTQ_LAST=4734, + XED_IFORMFL_VPDPBUSD_FIRST=4735, + XED_IFORMFL_VPDPBUSD_LAST=4744, + XED_IFORMFL_VPDPBUSDS_FIRST=4745, + XED_IFORMFL_VPDPBUSDS_LAST=4754, + XED_IFORMFL_VPDPWSSD_FIRST=4755, + XED_IFORMFL_VPDPWSSD_LAST=4764, + XED_IFORMFL_VPDPWSSDS_FIRST=4765, + XED_IFORMFL_VPDPWSSDS_LAST=4774, + XED_IFORMFL_VPERM2F128_FIRST=4775, + XED_IFORMFL_VPERM2F128_LAST=4776, + XED_IFORMFL_VPERM2I128_FIRST=4777, + XED_IFORMFL_VPERM2I128_LAST=4778, + XED_IFORMFL_VPERMB_FIRST=4779, + XED_IFORMFL_VPERMB_LAST=4784, + XED_IFORMFL_VPERMD_FIRST=4785, + XED_IFORMFL_VPERMD_LAST=4790, + XED_IFORMFL_VPERMI2B_FIRST=4791, + XED_IFORMFL_VPERMI2B_LAST=4796, + XED_IFORMFL_VPERMI2D_FIRST=4797, + XED_IFORMFL_VPERMI2D_LAST=4802, + XED_IFORMFL_VPERMI2PD_FIRST=4803, + XED_IFORMFL_VPERMI2PD_LAST=4808, + XED_IFORMFL_VPERMI2PS_FIRST=4809, + XED_IFORMFL_VPERMI2PS_LAST=4814, + XED_IFORMFL_VPERMI2Q_FIRST=4815, + XED_IFORMFL_VPERMI2Q_LAST=4820, + XED_IFORMFL_VPERMI2W_FIRST=4821, + XED_IFORMFL_VPERMI2W_LAST=4826, + XED_IFORMFL_VPERMIL2PD_FIRST=4827, + XED_IFORMFL_VPERMIL2PD_LAST=4832, + XED_IFORMFL_VPERMIL2PS_FIRST=4833, + XED_IFORMFL_VPERMIL2PS_LAST=4838, + XED_IFORMFL_VPERMILPD_FIRST=4839, + XED_IFORMFL_VPERMILPD_LAST=4858, + XED_IFORMFL_VPERMILPS_FIRST=4859, + XED_IFORMFL_VPERMILPS_LAST=4878, + XED_IFORMFL_VPERMPD_FIRST=4879, + XED_IFORMFL_VPERMPD_LAST=4888, + XED_IFORMFL_VPERMPS_FIRST=4889, + XED_IFORMFL_VPERMPS_LAST=4894, + XED_IFORMFL_VPERMQ_FIRST=4895, + XED_IFORMFL_VPERMQ_LAST=4904, + XED_IFORMFL_VPERMT2B_FIRST=4905, + XED_IFORMFL_VPERMT2B_LAST=4910, + XED_IFORMFL_VPERMT2D_FIRST=4911, + XED_IFORMFL_VPERMT2D_LAST=4916, + XED_IFORMFL_VPERMT2PD_FIRST=4917, + XED_IFORMFL_VPERMT2PD_LAST=4922, + XED_IFORMFL_VPERMT2PS_FIRST=4923, + XED_IFORMFL_VPERMT2PS_LAST=4928, + XED_IFORMFL_VPERMT2Q_FIRST=4929, + XED_IFORMFL_VPERMT2Q_LAST=4934, + XED_IFORMFL_VPERMT2W_FIRST=4935, + XED_IFORMFL_VPERMT2W_LAST=4940, + XED_IFORMFL_VPERMW_FIRST=4941, + XED_IFORMFL_VPERMW_LAST=4946, + XED_IFORMFL_VPEXPANDB_FIRST=4947, + XED_IFORMFL_VPEXPANDB_LAST=4952, + XED_IFORMFL_VPEXPANDD_FIRST=4953, + XED_IFORMFL_VPEXPANDD_LAST=4958, + XED_IFORMFL_VPEXPANDQ_FIRST=4959, + XED_IFORMFL_VPEXPANDQ_LAST=4964, + XED_IFORMFL_VPEXPANDW_FIRST=4965, + XED_IFORMFL_VPEXPANDW_LAST=4970, + XED_IFORMFL_VPEXTRB_FIRST=4971, + XED_IFORMFL_VPEXTRB_LAST=4974, + XED_IFORMFL_VPEXTRD_FIRST=4975, + XED_IFORMFL_VPEXTRD_LAST=4978, + XED_IFORMFL_VPEXTRQ_FIRST=4979, + XED_IFORMFL_VPEXTRQ_LAST=4982, + XED_IFORMFL_VPEXTRW_FIRST=4983, + XED_IFORMFL_VPEXTRW_LAST=4987, + XED_IFORMFL_VPEXTRW_C5_FIRST=4988, + XED_IFORMFL_VPEXTRW_C5_LAST=4988, + XED_IFORMFL_VPGATHERDD_FIRST=4989, + XED_IFORMFL_VPGATHERDD_LAST=4993, + XED_IFORMFL_VPGATHERDQ_FIRST=4994, + XED_IFORMFL_VPGATHERDQ_LAST=4998, + XED_IFORMFL_VPGATHERQD_FIRST=4999, + XED_IFORMFL_VPGATHERQD_LAST=5003, + XED_IFORMFL_VPGATHERQQ_FIRST=5004, + XED_IFORMFL_VPGATHERQQ_LAST=5008, + XED_IFORMFL_VPHADDBD_FIRST=5009, + XED_IFORMFL_VPHADDBD_LAST=5010, + XED_IFORMFL_VPHADDBQ_FIRST=5011, + XED_IFORMFL_VPHADDBQ_LAST=5012, + XED_IFORMFL_VPHADDBW_FIRST=5013, + XED_IFORMFL_VPHADDBW_LAST=5014, + XED_IFORMFL_VPHADDD_FIRST=5015, + XED_IFORMFL_VPHADDD_LAST=5018, + XED_IFORMFL_VPHADDDQ_FIRST=5019, + XED_IFORMFL_VPHADDDQ_LAST=5020, + XED_IFORMFL_VPHADDSW_FIRST=5021, + XED_IFORMFL_VPHADDSW_LAST=5024, + XED_IFORMFL_VPHADDUBD_FIRST=5025, + XED_IFORMFL_VPHADDUBD_LAST=5026, + XED_IFORMFL_VPHADDUBQ_FIRST=5027, + XED_IFORMFL_VPHADDUBQ_LAST=5028, + XED_IFORMFL_VPHADDUBW_FIRST=5029, + XED_IFORMFL_VPHADDUBW_LAST=5030, + XED_IFORMFL_VPHADDUDQ_FIRST=5031, + XED_IFORMFL_VPHADDUDQ_LAST=5032, + XED_IFORMFL_VPHADDUWD_FIRST=5033, + XED_IFORMFL_VPHADDUWD_LAST=5034, + XED_IFORMFL_VPHADDUWQ_FIRST=5035, + XED_IFORMFL_VPHADDUWQ_LAST=5036, + XED_IFORMFL_VPHADDW_FIRST=5037, + XED_IFORMFL_VPHADDW_LAST=5040, + XED_IFORMFL_VPHADDWD_FIRST=5041, + XED_IFORMFL_VPHADDWD_LAST=5042, + XED_IFORMFL_VPHADDWQ_FIRST=5043, + XED_IFORMFL_VPHADDWQ_LAST=5044, + XED_IFORMFL_VPHMINPOSUW_FIRST=5045, + XED_IFORMFL_VPHMINPOSUW_LAST=5046, + XED_IFORMFL_VPHSUBBW_FIRST=5047, + XED_IFORMFL_VPHSUBBW_LAST=5048, + XED_IFORMFL_VPHSUBD_FIRST=5049, + XED_IFORMFL_VPHSUBD_LAST=5052, + XED_IFORMFL_VPHSUBDQ_FIRST=5053, + XED_IFORMFL_VPHSUBDQ_LAST=5054, + XED_IFORMFL_VPHSUBSW_FIRST=5055, + XED_IFORMFL_VPHSUBSW_LAST=5058, + XED_IFORMFL_VPHSUBW_FIRST=5059, + XED_IFORMFL_VPHSUBW_LAST=5062, + XED_IFORMFL_VPHSUBWD_FIRST=5063, + XED_IFORMFL_VPHSUBWD_LAST=5064, + XED_IFORMFL_VPINSRB_FIRST=5065, + XED_IFORMFL_VPINSRB_LAST=5068, + XED_IFORMFL_VPINSRD_FIRST=5069, + XED_IFORMFL_VPINSRD_LAST=5072, + XED_IFORMFL_VPINSRQ_FIRST=5073, + XED_IFORMFL_VPINSRQ_LAST=5076, + XED_IFORMFL_VPINSRW_FIRST=5077, + XED_IFORMFL_VPINSRW_LAST=5080, + XED_IFORMFL_VPLZCNTD_FIRST=5081, + XED_IFORMFL_VPLZCNTD_LAST=5086, + XED_IFORMFL_VPLZCNTQ_FIRST=5087, + XED_IFORMFL_VPLZCNTQ_LAST=5092, + XED_IFORMFL_VPMACSDD_FIRST=5093, + XED_IFORMFL_VPMACSDD_LAST=5094, + XED_IFORMFL_VPMACSDQH_FIRST=5095, + XED_IFORMFL_VPMACSDQH_LAST=5096, + XED_IFORMFL_VPMACSDQL_FIRST=5097, + XED_IFORMFL_VPMACSDQL_LAST=5098, + XED_IFORMFL_VPMACSSDD_FIRST=5099, + XED_IFORMFL_VPMACSSDD_LAST=5100, + XED_IFORMFL_VPMACSSDQH_FIRST=5101, + XED_IFORMFL_VPMACSSDQH_LAST=5102, + XED_IFORMFL_VPMACSSDQL_FIRST=5103, + XED_IFORMFL_VPMACSSDQL_LAST=5104, + XED_IFORMFL_VPMACSSWD_FIRST=5105, + XED_IFORMFL_VPMACSSWD_LAST=5106, + XED_IFORMFL_VPMACSSWW_FIRST=5107, + XED_IFORMFL_VPMACSSWW_LAST=5108, + XED_IFORMFL_VPMACSWD_FIRST=5109, + XED_IFORMFL_VPMACSWD_LAST=5110, + XED_IFORMFL_VPMACSWW_FIRST=5111, + XED_IFORMFL_VPMACSWW_LAST=5112, + XED_IFORMFL_VPMADCSSWD_FIRST=5113, + XED_IFORMFL_VPMADCSSWD_LAST=5114, + XED_IFORMFL_VPMADCSWD_FIRST=5115, + XED_IFORMFL_VPMADCSWD_LAST=5116, + XED_IFORMFL_VPMADD52HUQ_FIRST=5117, + XED_IFORMFL_VPMADD52HUQ_LAST=5122, + XED_IFORMFL_VPMADD52LUQ_FIRST=5123, + XED_IFORMFL_VPMADD52LUQ_LAST=5128, + XED_IFORMFL_VPMADDUBSW_FIRST=5129, + XED_IFORMFL_VPMADDUBSW_LAST=5138, + XED_IFORMFL_VPMADDWD_FIRST=5139, + XED_IFORMFL_VPMADDWD_LAST=5148, + XED_IFORMFL_VPMASKMOVD_FIRST=5149, + XED_IFORMFL_VPMASKMOVD_LAST=5152, + XED_IFORMFL_VPMASKMOVQ_FIRST=5153, + XED_IFORMFL_VPMASKMOVQ_LAST=5156, + XED_IFORMFL_VPMAXSB_FIRST=5157, + XED_IFORMFL_VPMAXSB_LAST=5166, + XED_IFORMFL_VPMAXSD_FIRST=5167, + XED_IFORMFL_VPMAXSD_LAST=5176, + XED_IFORMFL_VPMAXSQ_FIRST=5177, + XED_IFORMFL_VPMAXSQ_LAST=5182, + XED_IFORMFL_VPMAXSW_FIRST=5183, + XED_IFORMFL_VPMAXSW_LAST=5192, + XED_IFORMFL_VPMAXUB_FIRST=5193, + XED_IFORMFL_VPMAXUB_LAST=5202, + XED_IFORMFL_VPMAXUD_FIRST=5203, + XED_IFORMFL_VPMAXUD_LAST=5212, + XED_IFORMFL_VPMAXUQ_FIRST=5213, + XED_IFORMFL_VPMAXUQ_LAST=5218, + XED_IFORMFL_VPMAXUW_FIRST=5219, + XED_IFORMFL_VPMAXUW_LAST=5228, + XED_IFORMFL_VPMINSB_FIRST=5229, + XED_IFORMFL_VPMINSB_LAST=5238, + XED_IFORMFL_VPMINSD_FIRST=5239, + XED_IFORMFL_VPMINSD_LAST=5248, + XED_IFORMFL_VPMINSQ_FIRST=5249, + XED_IFORMFL_VPMINSQ_LAST=5254, + XED_IFORMFL_VPMINSW_FIRST=5255, + XED_IFORMFL_VPMINSW_LAST=5264, + XED_IFORMFL_VPMINUB_FIRST=5265, + XED_IFORMFL_VPMINUB_LAST=5274, + XED_IFORMFL_VPMINUD_FIRST=5275, + XED_IFORMFL_VPMINUD_LAST=5284, + XED_IFORMFL_VPMINUQ_FIRST=5285, + XED_IFORMFL_VPMINUQ_LAST=5290, + XED_IFORMFL_VPMINUW_FIRST=5291, + XED_IFORMFL_VPMINUW_LAST=5300, + XED_IFORMFL_VPMOVB2M_FIRST=5301, + XED_IFORMFL_VPMOVB2M_LAST=5303, + XED_IFORMFL_VPMOVD2M_FIRST=5304, + XED_IFORMFL_VPMOVD2M_LAST=5306, + XED_IFORMFL_VPMOVDB_FIRST=5307, + XED_IFORMFL_VPMOVDB_LAST=5312, + XED_IFORMFL_VPMOVDW_FIRST=5313, + XED_IFORMFL_VPMOVDW_LAST=5318, + XED_IFORMFL_VPMOVM2B_FIRST=5319, + XED_IFORMFL_VPMOVM2B_LAST=5321, + XED_IFORMFL_VPMOVM2D_FIRST=5322, + XED_IFORMFL_VPMOVM2D_LAST=5324, + XED_IFORMFL_VPMOVM2Q_FIRST=5325, + XED_IFORMFL_VPMOVM2Q_LAST=5327, + XED_IFORMFL_VPMOVM2W_FIRST=5328, + XED_IFORMFL_VPMOVM2W_LAST=5330, + XED_IFORMFL_VPMOVMSKB_FIRST=5331, + XED_IFORMFL_VPMOVMSKB_LAST=5332, + XED_IFORMFL_VPMOVQ2M_FIRST=5333, + XED_IFORMFL_VPMOVQ2M_LAST=5335, + XED_IFORMFL_VPMOVQB_FIRST=5336, + XED_IFORMFL_VPMOVQB_LAST=5341, + XED_IFORMFL_VPMOVQD_FIRST=5342, + XED_IFORMFL_VPMOVQD_LAST=5347, + XED_IFORMFL_VPMOVQW_FIRST=5348, + XED_IFORMFL_VPMOVQW_LAST=5353, + XED_IFORMFL_VPMOVSDB_FIRST=5354, + XED_IFORMFL_VPMOVSDB_LAST=5359, + XED_IFORMFL_VPMOVSDW_FIRST=5360, + XED_IFORMFL_VPMOVSDW_LAST=5365, + XED_IFORMFL_VPMOVSQB_FIRST=5366, + XED_IFORMFL_VPMOVSQB_LAST=5371, + XED_IFORMFL_VPMOVSQD_FIRST=5372, + XED_IFORMFL_VPMOVSQD_LAST=5377, + XED_IFORMFL_VPMOVSQW_FIRST=5378, + XED_IFORMFL_VPMOVSQW_LAST=5383, + XED_IFORMFL_VPMOVSWB_FIRST=5384, + XED_IFORMFL_VPMOVSWB_LAST=5389, + XED_IFORMFL_VPMOVSXBD_FIRST=5390, + XED_IFORMFL_VPMOVSXBD_LAST=5399, + XED_IFORMFL_VPMOVSXBQ_FIRST=5400, + XED_IFORMFL_VPMOVSXBQ_LAST=5409, + XED_IFORMFL_VPMOVSXBW_FIRST=5410, + XED_IFORMFL_VPMOVSXBW_LAST=5419, + XED_IFORMFL_VPMOVSXDQ_FIRST=5420, + XED_IFORMFL_VPMOVSXDQ_LAST=5429, + XED_IFORMFL_VPMOVSXWD_FIRST=5430, + XED_IFORMFL_VPMOVSXWD_LAST=5439, + XED_IFORMFL_VPMOVSXWQ_FIRST=5440, + XED_IFORMFL_VPMOVSXWQ_LAST=5449, + XED_IFORMFL_VPMOVUSDB_FIRST=5450, + XED_IFORMFL_VPMOVUSDB_LAST=5455, + XED_IFORMFL_VPMOVUSDW_FIRST=5456, + XED_IFORMFL_VPMOVUSDW_LAST=5461, + XED_IFORMFL_VPMOVUSQB_FIRST=5462, + XED_IFORMFL_VPMOVUSQB_LAST=5467, + XED_IFORMFL_VPMOVUSQD_FIRST=5468, + XED_IFORMFL_VPMOVUSQD_LAST=5473, + XED_IFORMFL_VPMOVUSQW_FIRST=5474, + XED_IFORMFL_VPMOVUSQW_LAST=5479, + XED_IFORMFL_VPMOVUSWB_FIRST=5480, + XED_IFORMFL_VPMOVUSWB_LAST=5485, + XED_IFORMFL_VPMOVW2M_FIRST=5486, + XED_IFORMFL_VPMOVW2M_LAST=5488, + XED_IFORMFL_VPMOVWB_FIRST=5489, + XED_IFORMFL_VPMOVWB_LAST=5494, + XED_IFORMFL_VPMOVZXBD_FIRST=5495, + XED_IFORMFL_VPMOVZXBD_LAST=5504, + XED_IFORMFL_VPMOVZXBQ_FIRST=5505, + XED_IFORMFL_VPMOVZXBQ_LAST=5514, + XED_IFORMFL_VPMOVZXBW_FIRST=5515, + XED_IFORMFL_VPMOVZXBW_LAST=5524, + XED_IFORMFL_VPMOVZXDQ_FIRST=5525, + XED_IFORMFL_VPMOVZXDQ_LAST=5534, + XED_IFORMFL_VPMOVZXWD_FIRST=5535, + XED_IFORMFL_VPMOVZXWD_LAST=5544, + XED_IFORMFL_VPMOVZXWQ_FIRST=5545, + XED_IFORMFL_VPMOVZXWQ_LAST=5554, + XED_IFORMFL_VPMULDQ_FIRST=5555, + XED_IFORMFL_VPMULDQ_LAST=5564, + XED_IFORMFL_VPMULHRSW_FIRST=5565, + XED_IFORMFL_VPMULHRSW_LAST=5574, + XED_IFORMFL_VPMULHUW_FIRST=5575, + XED_IFORMFL_VPMULHUW_LAST=5584, + XED_IFORMFL_VPMULHW_FIRST=5585, + XED_IFORMFL_VPMULHW_LAST=5594, + XED_IFORMFL_VPMULLD_FIRST=5595, + XED_IFORMFL_VPMULLD_LAST=5604, + XED_IFORMFL_VPMULLQ_FIRST=5605, + XED_IFORMFL_VPMULLQ_LAST=5610, + XED_IFORMFL_VPMULLW_FIRST=5611, + XED_IFORMFL_VPMULLW_LAST=5620, + XED_IFORMFL_VPMULTISHIFTQB_FIRST=5621, + XED_IFORMFL_VPMULTISHIFTQB_LAST=5626, + XED_IFORMFL_VPMULUDQ_FIRST=5627, + XED_IFORMFL_VPMULUDQ_LAST=5636, + XED_IFORMFL_VPOPCNTB_FIRST=5637, + XED_IFORMFL_VPOPCNTB_LAST=5642, + XED_IFORMFL_VPOPCNTD_FIRST=5643, + XED_IFORMFL_VPOPCNTD_LAST=5648, + XED_IFORMFL_VPOPCNTQ_FIRST=5649, + XED_IFORMFL_VPOPCNTQ_LAST=5654, + XED_IFORMFL_VPOPCNTW_FIRST=5655, + XED_IFORMFL_VPOPCNTW_LAST=5660, + XED_IFORMFL_VPOR_FIRST=5661, + XED_IFORMFL_VPOR_LAST=5664, + XED_IFORMFL_VPORD_FIRST=5665, + XED_IFORMFL_VPORD_LAST=5670, + XED_IFORMFL_VPORQ_FIRST=5671, + XED_IFORMFL_VPORQ_LAST=5676, + XED_IFORMFL_VPPERM_FIRST=5677, + XED_IFORMFL_VPPERM_LAST=5679, + XED_IFORMFL_VPROLD_FIRST=5680, + XED_IFORMFL_VPROLD_LAST=5685, + XED_IFORMFL_VPROLQ_FIRST=5686, + XED_IFORMFL_VPROLQ_LAST=5691, + XED_IFORMFL_VPROLVD_FIRST=5692, + XED_IFORMFL_VPROLVD_LAST=5697, + XED_IFORMFL_VPROLVQ_FIRST=5698, + XED_IFORMFL_VPROLVQ_LAST=5703, + XED_IFORMFL_VPRORD_FIRST=5704, + XED_IFORMFL_VPRORD_LAST=5709, + XED_IFORMFL_VPRORQ_FIRST=5710, + XED_IFORMFL_VPRORQ_LAST=5715, + XED_IFORMFL_VPRORVD_FIRST=5716, + XED_IFORMFL_VPRORVD_LAST=5721, + XED_IFORMFL_VPRORVQ_FIRST=5722, + XED_IFORMFL_VPRORVQ_LAST=5727, + XED_IFORMFL_VPROTB_FIRST=5728, + XED_IFORMFL_VPROTB_LAST=5732, + XED_IFORMFL_VPROTD_FIRST=5733, + XED_IFORMFL_VPROTD_LAST=5737, + XED_IFORMFL_VPROTQ_FIRST=5738, + XED_IFORMFL_VPROTQ_LAST=5742, + XED_IFORMFL_VPROTW_FIRST=5743, + XED_IFORMFL_VPROTW_LAST=5747, + XED_IFORMFL_VPSADBW_FIRST=5748, + XED_IFORMFL_VPSADBW_LAST=5757, + XED_IFORMFL_VPSCATTERDD_FIRST=5758, + XED_IFORMFL_VPSCATTERDD_LAST=5760, + XED_IFORMFL_VPSCATTERDQ_FIRST=5761, + XED_IFORMFL_VPSCATTERDQ_LAST=5763, + XED_IFORMFL_VPSCATTERQD_FIRST=5764, + XED_IFORMFL_VPSCATTERQD_LAST=5766, + XED_IFORMFL_VPSCATTERQQ_FIRST=5767, + XED_IFORMFL_VPSCATTERQQ_LAST=5769, + XED_IFORMFL_VPSHAB_FIRST=5770, + XED_IFORMFL_VPSHAB_LAST=5772, + XED_IFORMFL_VPSHAD_FIRST=5773, + XED_IFORMFL_VPSHAD_LAST=5775, + XED_IFORMFL_VPSHAQ_FIRST=5776, + XED_IFORMFL_VPSHAQ_LAST=5778, + XED_IFORMFL_VPSHAW_FIRST=5779, + XED_IFORMFL_VPSHAW_LAST=5781, + XED_IFORMFL_VPSHLB_FIRST=5782, + XED_IFORMFL_VPSHLB_LAST=5784, + XED_IFORMFL_VPSHLD_FIRST=5785, + XED_IFORMFL_VPSHLD_LAST=5787, + XED_IFORMFL_VPSHLDD_FIRST=5788, + XED_IFORMFL_VPSHLDD_LAST=5793, + XED_IFORMFL_VPSHLDQ_FIRST=5794, + XED_IFORMFL_VPSHLDQ_LAST=5799, + XED_IFORMFL_VPSHLDVD_FIRST=5800, + XED_IFORMFL_VPSHLDVD_LAST=5805, + XED_IFORMFL_VPSHLDVQ_FIRST=5806, + XED_IFORMFL_VPSHLDVQ_LAST=5811, + XED_IFORMFL_VPSHLDVW_FIRST=5812, + XED_IFORMFL_VPSHLDVW_LAST=5817, + XED_IFORMFL_VPSHLDW_FIRST=5818, + XED_IFORMFL_VPSHLDW_LAST=5823, + XED_IFORMFL_VPSHLQ_FIRST=5824, + XED_IFORMFL_VPSHLQ_LAST=5826, + XED_IFORMFL_VPSHLW_FIRST=5827, + XED_IFORMFL_VPSHLW_LAST=5829, + XED_IFORMFL_VPSHRDD_FIRST=5830, + XED_IFORMFL_VPSHRDD_LAST=5835, + XED_IFORMFL_VPSHRDQ_FIRST=5836, + XED_IFORMFL_VPSHRDQ_LAST=5841, + XED_IFORMFL_VPSHRDVD_FIRST=5842, + XED_IFORMFL_VPSHRDVD_LAST=5847, + XED_IFORMFL_VPSHRDVQ_FIRST=5848, + XED_IFORMFL_VPSHRDVQ_LAST=5853, + XED_IFORMFL_VPSHRDVW_FIRST=5854, + XED_IFORMFL_VPSHRDVW_LAST=5859, + XED_IFORMFL_VPSHRDW_FIRST=5860, + XED_IFORMFL_VPSHRDW_LAST=5865, + XED_IFORMFL_VPSHUFB_FIRST=5866, + XED_IFORMFL_VPSHUFB_LAST=5875, + XED_IFORMFL_VPSHUFBITQMB_FIRST=5876, + XED_IFORMFL_VPSHUFBITQMB_LAST=5881, + XED_IFORMFL_VPSHUFD_FIRST=5882, + XED_IFORMFL_VPSHUFD_LAST=5891, + XED_IFORMFL_VPSHUFHW_FIRST=5892, + XED_IFORMFL_VPSHUFHW_LAST=5901, + XED_IFORMFL_VPSHUFLW_FIRST=5902, + XED_IFORMFL_VPSHUFLW_LAST=5911, + XED_IFORMFL_VPSIGNB_FIRST=5912, + XED_IFORMFL_VPSIGNB_LAST=5915, + XED_IFORMFL_VPSIGND_FIRST=5916, + XED_IFORMFL_VPSIGND_LAST=5919, + XED_IFORMFL_VPSIGNW_FIRST=5920, + XED_IFORMFL_VPSIGNW_LAST=5923, + XED_IFORMFL_VPSLLD_FIRST=5924, + XED_IFORMFL_VPSLLD_LAST=5941, + XED_IFORMFL_VPSLLDQ_FIRST=5942, + XED_IFORMFL_VPSLLDQ_LAST=5949, + XED_IFORMFL_VPSLLQ_FIRST=5950, + XED_IFORMFL_VPSLLQ_LAST=5967, + XED_IFORMFL_VPSLLVD_FIRST=5968, + XED_IFORMFL_VPSLLVD_LAST=5977, + XED_IFORMFL_VPSLLVQ_FIRST=5978, + XED_IFORMFL_VPSLLVQ_LAST=5987, + XED_IFORMFL_VPSLLVW_FIRST=5988, + XED_IFORMFL_VPSLLVW_LAST=5993, + XED_IFORMFL_VPSLLW_FIRST=5994, + XED_IFORMFL_VPSLLW_LAST=6011, + XED_IFORMFL_VPSRAD_FIRST=6012, + XED_IFORMFL_VPSRAD_LAST=6029, + XED_IFORMFL_VPSRAQ_FIRST=6030, + XED_IFORMFL_VPSRAQ_LAST=6041, + XED_IFORMFL_VPSRAVD_FIRST=6042, + XED_IFORMFL_VPSRAVD_LAST=6051, + XED_IFORMFL_VPSRAVQ_FIRST=6052, + XED_IFORMFL_VPSRAVQ_LAST=6057, + XED_IFORMFL_VPSRAVW_FIRST=6058, + XED_IFORMFL_VPSRAVW_LAST=6063, + XED_IFORMFL_VPSRAW_FIRST=6064, + XED_IFORMFL_VPSRAW_LAST=6081, + XED_IFORMFL_VPSRLD_FIRST=6082, + XED_IFORMFL_VPSRLD_LAST=6099, + XED_IFORMFL_VPSRLDQ_FIRST=6100, + XED_IFORMFL_VPSRLDQ_LAST=6107, + XED_IFORMFL_VPSRLQ_FIRST=6108, + XED_IFORMFL_VPSRLQ_LAST=6125, + XED_IFORMFL_VPSRLVD_FIRST=6126, + XED_IFORMFL_VPSRLVD_LAST=6135, + XED_IFORMFL_VPSRLVQ_FIRST=6136, + XED_IFORMFL_VPSRLVQ_LAST=6145, + XED_IFORMFL_VPSRLVW_FIRST=6146, + XED_IFORMFL_VPSRLVW_LAST=6151, + XED_IFORMFL_VPSRLW_FIRST=6152, + XED_IFORMFL_VPSRLW_LAST=6169, + XED_IFORMFL_VPSUBB_FIRST=6170, + XED_IFORMFL_VPSUBB_LAST=6179, + XED_IFORMFL_VPSUBD_FIRST=6180, + XED_IFORMFL_VPSUBD_LAST=6189, + XED_IFORMFL_VPSUBQ_FIRST=6190, + XED_IFORMFL_VPSUBQ_LAST=6199, + XED_IFORMFL_VPSUBSB_FIRST=6200, + XED_IFORMFL_VPSUBSB_LAST=6209, + XED_IFORMFL_VPSUBSW_FIRST=6210, + XED_IFORMFL_VPSUBSW_LAST=6219, + XED_IFORMFL_VPSUBUSB_FIRST=6220, + XED_IFORMFL_VPSUBUSB_LAST=6229, + XED_IFORMFL_VPSUBUSW_FIRST=6230, + XED_IFORMFL_VPSUBUSW_LAST=6239, + XED_IFORMFL_VPSUBW_FIRST=6240, + XED_IFORMFL_VPSUBW_LAST=6249, + XED_IFORMFL_VPTERNLOGD_FIRST=6250, + XED_IFORMFL_VPTERNLOGD_LAST=6255, + XED_IFORMFL_VPTERNLOGQ_FIRST=6256, + XED_IFORMFL_VPTERNLOGQ_LAST=6261, + XED_IFORMFL_VPTEST_FIRST=6262, + XED_IFORMFL_VPTEST_LAST=6265, + XED_IFORMFL_VPTESTMB_FIRST=6266, + XED_IFORMFL_VPTESTMB_LAST=6271, + XED_IFORMFL_VPTESTMD_FIRST=6272, + XED_IFORMFL_VPTESTMD_LAST=6277, + XED_IFORMFL_VPTESTMQ_FIRST=6278, + XED_IFORMFL_VPTESTMQ_LAST=6283, + XED_IFORMFL_VPTESTMW_FIRST=6284, + XED_IFORMFL_VPTESTMW_LAST=6289, + XED_IFORMFL_VPTESTNMB_FIRST=6290, + XED_IFORMFL_VPTESTNMB_LAST=6295, + XED_IFORMFL_VPTESTNMD_FIRST=6296, + XED_IFORMFL_VPTESTNMD_LAST=6301, + XED_IFORMFL_VPTESTNMQ_FIRST=6302, + XED_IFORMFL_VPTESTNMQ_LAST=6307, + XED_IFORMFL_VPTESTNMW_FIRST=6308, + XED_IFORMFL_VPTESTNMW_LAST=6313, + XED_IFORMFL_VPUNPCKHBW_FIRST=6314, + XED_IFORMFL_VPUNPCKHBW_LAST=6323, + XED_IFORMFL_VPUNPCKHDQ_FIRST=6324, + XED_IFORMFL_VPUNPCKHDQ_LAST=6333, + XED_IFORMFL_VPUNPCKHQDQ_FIRST=6334, + XED_IFORMFL_VPUNPCKHQDQ_LAST=6343, + XED_IFORMFL_VPUNPCKHWD_FIRST=6344, + XED_IFORMFL_VPUNPCKHWD_LAST=6353, + XED_IFORMFL_VPUNPCKLBW_FIRST=6354, + XED_IFORMFL_VPUNPCKLBW_LAST=6363, + XED_IFORMFL_VPUNPCKLDQ_FIRST=6364, + XED_IFORMFL_VPUNPCKLDQ_LAST=6373, + XED_IFORMFL_VPUNPCKLQDQ_FIRST=6374, + XED_IFORMFL_VPUNPCKLQDQ_LAST=6383, + XED_IFORMFL_VPUNPCKLWD_FIRST=6384, + XED_IFORMFL_VPUNPCKLWD_LAST=6393, + XED_IFORMFL_VPXOR_FIRST=6394, + XED_IFORMFL_VPXOR_LAST=6397, + XED_IFORMFL_VPXORD_FIRST=6398, + XED_IFORMFL_VPXORD_LAST=6403, + XED_IFORMFL_VPXORQ_FIRST=6404, + XED_IFORMFL_VPXORQ_LAST=6409, + XED_IFORMFL_VRANGEPD_FIRST=6410, + XED_IFORMFL_VRANGEPD_LAST=6415, + XED_IFORMFL_VRANGEPS_FIRST=6416, + XED_IFORMFL_VRANGEPS_LAST=6421, + XED_IFORMFL_VRANGESD_FIRST=6422, + XED_IFORMFL_VRANGESD_LAST=6423, + XED_IFORMFL_VRANGESS_FIRST=6424, + XED_IFORMFL_VRANGESS_LAST=6425, + XED_IFORMFL_VRCP14PD_FIRST=6426, + XED_IFORMFL_VRCP14PD_LAST=6431, + XED_IFORMFL_VRCP14PS_FIRST=6432, + XED_IFORMFL_VRCP14PS_LAST=6437, + XED_IFORMFL_VRCP14SD_FIRST=6438, + XED_IFORMFL_VRCP14SD_LAST=6439, + XED_IFORMFL_VRCP14SS_FIRST=6440, + XED_IFORMFL_VRCP14SS_LAST=6441, + XED_IFORMFL_VRCP28PD_FIRST=6442, + XED_IFORMFL_VRCP28PD_LAST=6443, + XED_IFORMFL_VRCP28PS_FIRST=6444, + XED_IFORMFL_VRCP28PS_LAST=6445, + XED_IFORMFL_VRCP28SD_FIRST=6446, + XED_IFORMFL_VRCP28SD_LAST=6447, + XED_IFORMFL_VRCP28SS_FIRST=6448, + XED_IFORMFL_VRCP28SS_LAST=6449, + XED_IFORMFL_VRCPPH_FIRST=6450, + XED_IFORMFL_VRCPPH_LAST=6455, + XED_IFORMFL_VRCPPS_FIRST=6456, + XED_IFORMFL_VRCPPS_LAST=6459, + XED_IFORMFL_VRCPSH_FIRST=6460, + XED_IFORMFL_VRCPSH_LAST=6461, + XED_IFORMFL_VRCPSS_FIRST=6462, + XED_IFORMFL_VRCPSS_LAST=6463, + XED_IFORMFL_VREDUCEPD_FIRST=6464, + XED_IFORMFL_VREDUCEPD_LAST=6469, + XED_IFORMFL_VREDUCEPH_FIRST=6470, + XED_IFORMFL_VREDUCEPH_LAST=6475, + XED_IFORMFL_VREDUCEPS_FIRST=6476, + XED_IFORMFL_VREDUCEPS_LAST=6481, + XED_IFORMFL_VREDUCESD_FIRST=6482, + XED_IFORMFL_VREDUCESD_LAST=6483, + XED_IFORMFL_VREDUCESH_FIRST=6484, + XED_IFORMFL_VREDUCESH_LAST=6485, + XED_IFORMFL_VREDUCESS_FIRST=6486, + XED_IFORMFL_VREDUCESS_LAST=6487, + XED_IFORMFL_VRNDSCALEPD_FIRST=6488, + XED_IFORMFL_VRNDSCALEPD_LAST=6493, + XED_IFORMFL_VRNDSCALEPH_FIRST=6494, + XED_IFORMFL_VRNDSCALEPH_LAST=6499, + XED_IFORMFL_VRNDSCALEPS_FIRST=6500, + XED_IFORMFL_VRNDSCALEPS_LAST=6505, + XED_IFORMFL_VRNDSCALESD_FIRST=6506, + XED_IFORMFL_VRNDSCALESD_LAST=6507, + XED_IFORMFL_VRNDSCALESH_FIRST=6508, + XED_IFORMFL_VRNDSCALESH_LAST=6509, + XED_IFORMFL_VRNDSCALESS_FIRST=6510, + XED_IFORMFL_VRNDSCALESS_LAST=6511, + XED_IFORMFL_VROUNDPD_FIRST=6512, + XED_IFORMFL_VROUNDPD_LAST=6515, + XED_IFORMFL_VROUNDPS_FIRST=6516, + XED_IFORMFL_VROUNDPS_LAST=6519, + XED_IFORMFL_VROUNDSD_FIRST=6520, + XED_IFORMFL_VROUNDSD_LAST=6521, + XED_IFORMFL_VROUNDSS_FIRST=6522, + XED_IFORMFL_VROUNDSS_LAST=6523, + XED_IFORMFL_VRSQRT14PD_FIRST=6524, + XED_IFORMFL_VRSQRT14PD_LAST=6529, + XED_IFORMFL_VRSQRT14PS_FIRST=6530, + XED_IFORMFL_VRSQRT14PS_LAST=6535, + XED_IFORMFL_VRSQRT14SD_FIRST=6536, + XED_IFORMFL_VRSQRT14SD_LAST=6537, + XED_IFORMFL_VRSQRT14SS_FIRST=6538, + XED_IFORMFL_VRSQRT14SS_LAST=6539, + XED_IFORMFL_VRSQRT28PD_FIRST=6540, + XED_IFORMFL_VRSQRT28PD_LAST=6541, + XED_IFORMFL_VRSQRT28PS_FIRST=6542, + XED_IFORMFL_VRSQRT28PS_LAST=6543, + XED_IFORMFL_VRSQRT28SD_FIRST=6544, + XED_IFORMFL_VRSQRT28SD_LAST=6545, + XED_IFORMFL_VRSQRT28SS_FIRST=6546, + XED_IFORMFL_VRSQRT28SS_LAST=6547, + XED_IFORMFL_VRSQRTPH_FIRST=6548, + XED_IFORMFL_VRSQRTPH_LAST=6553, + XED_IFORMFL_VRSQRTPS_FIRST=6554, + XED_IFORMFL_VRSQRTPS_LAST=6557, + XED_IFORMFL_VRSQRTSH_FIRST=6558, + XED_IFORMFL_VRSQRTSH_LAST=6559, + XED_IFORMFL_VRSQRTSS_FIRST=6560, + XED_IFORMFL_VRSQRTSS_LAST=6561, + XED_IFORMFL_VSCALEFPD_FIRST=6562, + XED_IFORMFL_VSCALEFPD_LAST=6567, + XED_IFORMFL_VSCALEFPH_FIRST=6568, + XED_IFORMFL_VSCALEFPH_LAST=6573, + XED_IFORMFL_VSCALEFPS_FIRST=6574, + XED_IFORMFL_VSCALEFPS_LAST=6579, + XED_IFORMFL_VSCALEFSD_FIRST=6580, + XED_IFORMFL_VSCALEFSD_LAST=6581, + XED_IFORMFL_VSCALEFSH_FIRST=6582, + XED_IFORMFL_VSCALEFSH_LAST=6583, + XED_IFORMFL_VSCALEFSS_FIRST=6584, + XED_IFORMFL_VSCALEFSS_LAST=6585, + XED_IFORMFL_VSCATTERDPD_FIRST=6586, + XED_IFORMFL_VSCATTERDPD_LAST=6588, + XED_IFORMFL_VSCATTERDPS_FIRST=6589, + XED_IFORMFL_VSCATTERDPS_LAST=6591, + XED_IFORMFL_VSCATTERPF0DPD_FIRST=6592, + XED_IFORMFL_VSCATTERPF0DPD_LAST=6592, + XED_IFORMFL_VSCATTERPF0DPS_FIRST=6593, + XED_IFORMFL_VSCATTERPF0DPS_LAST=6593, + XED_IFORMFL_VSCATTERPF0QPD_FIRST=6594, + XED_IFORMFL_VSCATTERPF0QPD_LAST=6594, + XED_IFORMFL_VSCATTERPF0QPS_FIRST=6595, + XED_IFORMFL_VSCATTERPF0QPS_LAST=6595, + XED_IFORMFL_VSCATTERPF1DPD_FIRST=6596, + XED_IFORMFL_VSCATTERPF1DPD_LAST=6596, + XED_IFORMFL_VSCATTERPF1DPS_FIRST=6597, + XED_IFORMFL_VSCATTERPF1DPS_LAST=6597, + XED_IFORMFL_VSCATTERPF1QPD_FIRST=6598, + XED_IFORMFL_VSCATTERPF1QPD_LAST=6598, + XED_IFORMFL_VSCATTERPF1QPS_FIRST=6599, + XED_IFORMFL_VSCATTERPF1QPS_LAST=6599, + XED_IFORMFL_VSCATTERQPD_FIRST=6600, + XED_IFORMFL_VSCATTERQPD_LAST=6602, + XED_IFORMFL_VSCATTERQPS_FIRST=6603, + XED_IFORMFL_VSCATTERQPS_LAST=6605, + XED_IFORMFL_VSHUFF32X4_FIRST=6606, + XED_IFORMFL_VSHUFF32X4_LAST=6609, + XED_IFORMFL_VSHUFF64X2_FIRST=6610, + XED_IFORMFL_VSHUFF64X2_LAST=6613, + XED_IFORMFL_VSHUFI32X4_FIRST=6614, + XED_IFORMFL_VSHUFI32X4_LAST=6617, + XED_IFORMFL_VSHUFI64X2_FIRST=6618, + XED_IFORMFL_VSHUFI64X2_LAST=6621, + XED_IFORMFL_VSHUFPD_FIRST=6622, + XED_IFORMFL_VSHUFPD_LAST=6631, + XED_IFORMFL_VSHUFPS_FIRST=6632, + XED_IFORMFL_VSHUFPS_LAST=6641, + XED_IFORMFL_VSQRTPD_FIRST=6642, + XED_IFORMFL_VSQRTPD_LAST=6651, + XED_IFORMFL_VSQRTPH_FIRST=6652, + XED_IFORMFL_VSQRTPH_LAST=6657, + XED_IFORMFL_VSQRTPS_FIRST=6658, + XED_IFORMFL_VSQRTPS_LAST=6667, + XED_IFORMFL_VSQRTSD_FIRST=6668, + XED_IFORMFL_VSQRTSD_LAST=6671, + XED_IFORMFL_VSQRTSH_FIRST=6672, + XED_IFORMFL_VSQRTSH_LAST=6673, + XED_IFORMFL_VSQRTSS_FIRST=6674, + XED_IFORMFL_VSQRTSS_LAST=6677, + XED_IFORMFL_VSTMXCSR_FIRST=6678, + XED_IFORMFL_VSTMXCSR_LAST=6678, + XED_IFORMFL_VSUBPD_FIRST=6679, + XED_IFORMFL_VSUBPD_LAST=6688, + XED_IFORMFL_VSUBPH_FIRST=6689, + XED_IFORMFL_VSUBPH_LAST=6694, + XED_IFORMFL_VSUBPS_FIRST=6695, + XED_IFORMFL_VSUBPS_LAST=6704, + XED_IFORMFL_VSUBSD_FIRST=6705, + XED_IFORMFL_VSUBSD_LAST=6708, + XED_IFORMFL_VSUBSH_FIRST=6709, + XED_IFORMFL_VSUBSH_LAST=6710, + XED_IFORMFL_VSUBSS_FIRST=6711, + XED_IFORMFL_VSUBSS_LAST=6714, + XED_IFORMFL_VTESTPD_FIRST=6715, + XED_IFORMFL_VTESTPD_LAST=6718, + XED_IFORMFL_VTESTPS_FIRST=6719, + XED_IFORMFL_VTESTPS_LAST=6722, + XED_IFORMFL_VUCOMISD_FIRST=6723, + XED_IFORMFL_VUCOMISD_LAST=6726, + XED_IFORMFL_VUCOMISH_FIRST=6727, + XED_IFORMFL_VUCOMISH_LAST=6728, + XED_IFORMFL_VUCOMISS_FIRST=6729, + XED_IFORMFL_VUCOMISS_LAST=6732, + XED_IFORMFL_VUNPCKHPD_FIRST=6733, + XED_IFORMFL_VUNPCKHPD_LAST=6742, + XED_IFORMFL_VUNPCKHPS_FIRST=6743, + XED_IFORMFL_VUNPCKHPS_LAST=6752, + XED_IFORMFL_VUNPCKLPD_FIRST=6753, + XED_IFORMFL_VUNPCKLPD_LAST=6762, + XED_IFORMFL_VUNPCKLPS_FIRST=6763, + XED_IFORMFL_VUNPCKLPS_LAST=6772, + XED_IFORMFL_VXORPD_FIRST=6773, + XED_IFORMFL_VXORPD_LAST=6782, + XED_IFORMFL_VXORPS_FIRST=6783, + XED_IFORMFL_VXORPS_LAST=6792, + XED_IFORMFL_VZEROALL_FIRST=6793, + XED_IFORMFL_VZEROALL_LAST=6793, + XED_IFORMFL_VZEROUPPER_FIRST=6794, + XED_IFORMFL_VZEROUPPER_LAST=6794, + XED_IFORMFL_WBINVD_FIRST=6795, + XED_IFORMFL_WBINVD_LAST=6795, + XED_IFORMFL_WBNOINVD_FIRST=6796, + XED_IFORMFL_WBNOINVD_LAST=6796, + XED_IFORMFL_WRFSBASE_FIRST=6797, + XED_IFORMFL_WRFSBASE_LAST=6797, + XED_IFORMFL_WRGSBASE_FIRST=6798, + XED_IFORMFL_WRGSBASE_LAST=6798, + XED_IFORMFL_WRMSR_FIRST=6799, + XED_IFORMFL_WRMSR_LAST=6799, + XED_IFORMFL_WRPKRU_FIRST=6800, + XED_IFORMFL_WRPKRU_LAST=6800, + XED_IFORMFL_WRSSD_FIRST=6801, + XED_IFORMFL_WRSSD_LAST=6801, + XED_IFORMFL_WRSSQ_FIRST=6802, + XED_IFORMFL_WRSSQ_LAST=6802, + XED_IFORMFL_WRUSSD_FIRST=6803, + XED_IFORMFL_WRUSSD_LAST=6803, + XED_IFORMFL_WRUSSQ_FIRST=6804, + XED_IFORMFL_WRUSSQ_LAST=6804, + XED_IFORMFL_XABORT_FIRST=6805, + XED_IFORMFL_XABORT_LAST=6805, + XED_IFORMFL_XADD_FIRST=6806, + XED_IFORMFL_XADD_LAST=6809, + XED_IFORMFL_XADD_LOCK_FIRST=6810, + XED_IFORMFL_XADD_LOCK_LAST=6811, + XED_IFORMFL_XBEGIN_FIRST=6812, + XED_IFORMFL_XBEGIN_LAST=6812, + XED_IFORMFL_XCHG_FIRST=6813, + XED_IFORMFL_XCHG_LAST=6817, + XED_IFORMFL_XEND_FIRST=6818, + XED_IFORMFL_XEND_LAST=6818, + XED_IFORMFL_XGETBV_FIRST=6819, + XED_IFORMFL_XGETBV_LAST=6819, + XED_IFORMFL_XLAT_FIRST=6820, + XED_IFORMFL_XLAT_LAST=6820, + XED_IFORMFL_XOR_FIRST=6821, + XED_IFORMFL_XOR_LAST=6838, + XED_IFORMFL_XORPD_FIRST=6839, + XED_IFORMFL_XORPD_LAST=6840, + XED_IFORMFL_XORPS_FIRST=6841, + XED_IFORMFL_XORPS_LAST=6842, + XED_IFORMFL_XOR_LOCK_FIRST=6843, + XED_IFORMFL_XOR_LOCK_LAST=6848, + XED_IFORMFL_XRESLDTRK_FIRST=6849, + XED_IFORMFL_XRESLDTRK_LAST=6849, + XED_IFORMFL_XRSTOR_FIRST=6850, + XED_IFORMFL_XRSTOR_LAST=6850, + XED_IFORMFL_XRSTOR64_FIRST=6851, + XED_IFORMFL_XRSTOR64_LAST=6851, + XED_IFORMFL_XRSTORS_FIRST=6852, + XED_IFORMFL_XRSTORS_LAST=6852, + XED_IFORMFL_XRSTORS64_FIRST=6853, + XED_IFORMFL_XRSTORS64_LAST=6853, + XED_IFORMFL_XSAVE_FIRST=6854, + XED_IFORMFL_XSAVE_LAST=6854, + XED_IFORMFL_XSAVE64_FIRST=6855, + XED_IFORMFL_XSAVE64_LAST=6855, + XED_IFORMFL_XSAVEC_FIRST=6856, + XED_IFORMFL_XSAVEC_LAST=6856, + XED_IFORMFL_XSAVEC64_FIRST=6857, + XED_IFORMFL_XSAVEC64_LAST=6857, + XED_IFORMFL_XSAVEOPT_FIRST=6858, + XED_IFORMFL_XSAVEOPT_LAST=6858, + XED_IFORMFL_XSAVEOPT64_FIRST=6859, + XED_IFORMFL_XSAVEOPT64_LAST=6859, + XED_IFORMFL_XSAVES_FIRST=6860, + XED_IFORMFL_XSAVES_LAST=6860, + XED_IFORMFL_XSAVES64_FIRST=6861, + XED_IFORMFL_XSAVES64_LAST=6861, + XED_IFORMFL_XSETBV_FIRST=6862, + XED_IFORMFL_XSETBV_LAST=6862, + XED_IFORMFL_XSTORE_FIRST=6863, + XED_IFORMFL_XSTORE_LAST=6863, + XED_IFORMFL_XSUSLDTRK_FIRST=6864, + XED_IFORMFL_XSUSLDTRK_LAST=6864, + XED_IFORMFL_XTEST_FIRST=6865, + XED_IFORMFL_XTEST_LAST=6865, + XED_IFORMFL_LAST +} xed_iformfl_enum_t; + +/// Returns the last element of the enumeration +/// @return xed_iformfl_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_iformfl_enum_t xed_iformfl_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-ild-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-ild-enum.h new file mode 100644 index 0000000..334f408 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-ild-enum.h @@ -0,0 +1,80 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-ild-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ILD_ENUM_H) +# define XED_ILD_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ILD_AMD_3DNOW_DEFINED 1 +#define XED_ILD_AMD_XOP8_DEFINED 1 +#define XED_ILD_AMD_XOP9_DEFINED 1 +#define XED_ILD_AMD_XOPA_DEFINED 1 +#define XED_ILD_EVEX_MAP1_DEFINED 1 +#define XED_ILD_EVEX_MAP2_DEFINED 1 +#define XED_ILD_EVEX_MAP3_DEFINED 1 +#define XED_ILD_EVEX_MAP5_DEFINED 1 +#define XED_ILD_EVEX_MAP6_DEFINED 1 +#define XED_ILD_LEGACY_MAP0_DEFINED 1 +#define XED_ILD_LEGACY_MAP1_DEFINED 1 +#define XED_ILD_LEGACY_MAP2_DEFINED 1 +#define XED_ILD_LEGACY_MAP3_DEFINED 1 +#define XED_ILD_VEX_MAP1_DEFINED 1 +#define XED_ILD_VEX_MAP2_DEFINED 1 +#define XED_ILD_VEX_MAP3_DEFINED 1 +#define XED_ILD_MAP_INVALID_DEFINED 1 +#define XED_ILD_LAST_DEFINED 1 +typedef enum { + XED_ILD_AMD_3DNOW=4, + XED_ILD_AMD_XOP8=8, + XED_ILD_AMD_XOP9=9, + XED_ILD_AMD_XOPA=10, + XED_ILD_EVEX_MAP1=1, + XED_ILD_EVEX_MAP2=2, + XED_ILD_EVEX_MAP3=3, + XED_ILD_EVEX_MAP5=5, + XED_ILD_EVEX_MAP6=6, + XED_ILD_LEGACY_MAP0=0, + XED_ILD_LEGACY_MAP1=1, + XED_ILD_LEGACY_MAP2=2, + XED_ILD_LEGACY_MAP3=3, + XED_ILD_VEX_MAP1=1, + XED_ILD_VEX_MAP2=2, + XED_ILD_VEX_MAP3=3, + XED_ILD_MAP_INVALID, + XED_ILD_LAST +} xed_ild_map_enum_t; + +/// This converts strings to #xed_ild_map_enum_t types. +/// @param s A C-string. +/// @return #xed_ild_map_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_ild_map_enum_t str2xed_ild_map_enum_t(const char* s); +/// This converts strings to #xed_ild_map_enum_t types. +/// @param p An enumeration element of type xed_ild_map_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_ild_map_enum_t2str(const xed_ild_map_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_ild_map_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_ild_map_enum_t xed_ild_map_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-ild.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-ild.h new file mode 100644 index 0000000..800c285 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-ild.h @@ -0,0 +1,61 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +/// @file xed-ild.h +/// instruction length decoder + +#if !defined(XED_ILD_H) +# define XED_ILD_H +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-types.h" +#include "xed-decoded-inst.h" + +#include "xed-operand-accessors.h" + + +/// This function just does instruction length decoding. +/// It does not return a fully decoded instruction. +/// @param xedd the decoded instruction of type #xed_decoded_inst_t . +/// Mode/state sent in via xedd; See the #xed_state_t . +/// @param itext the pointer to the array of instruction text bytes +/// @param bytes the length of the itext input array. +/// 1 to 15 bytes, anything more is ignored. +/// @return #xed_error_enum_t indicating success (#XED_ERROR_NONE) or +/// failure. +/// Only two failure codes are valid for this function: +/// #XED_ERROR_BUFFER_TOO_SHORT and #XED_ERROR_GENERAL_ERROR. +/// In general this function cannot tell if the instruction is valid or +/// not. For valid instructions, XED can figure out if enough bytes were +/// provided to decode the instruction. If not enough were provided, +/// XED returns #XED_ERROR_BUFFER_TOO_SHORT. +/// From this function, the #XED_ERROR_GENERAL_ERROR is an indication +/// that XED could not decode the instruction's length because the +/// instruction was so invalid that even its length +/// may across implmentations. +/// +/// @ingroup DEC +XED_DLL_EXPORT xed_error_enum_t +xed_ild_decode(xed_decoded_inst_t* xedd, + const xed_uint8_t* itext, + const unsigned int bytes); + + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-immdis.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-immdis.h new file mode 100644 index 0000000..32a2f48 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-immdis.h @@ -0,0 +1,199 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immdis.h +/// + + + +#ifndef XED_IMMDIS_H +# define XED_IMMDIS_H + +#include "xed-types.h" +#include "xed-common-defs.h" +#include "xed-util.h" + + +//////////////////////////////////////////////////////////////////////////// +// DEFINES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// TYPES +//////////////////////////////////////////////////////////////////////////// +//////////////////////////////////////////////////////////////////////////// +// PROTOTYPES +//////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////// +// GLOBALS +//////////////////////////////////////////////////////////////////////////// + +#define XED_MAX_IMMDIS_BYTES 8 + +// A union for speed of zeroing +union xed_immdis_values_t +{ + xed_uint8_t x[XED_MAX_IMMDIS_BYTES];// STORED LITTLE ENDIAN. BYTE 0 is LSB + xed_uint64_t q; +}; + +/// Stores immediates and displacements for the encoder & decoder. +typedef struct xed_immdis_s { + union xed_immdis_values_t value; + unsigned int currently_used_space :4; // current number of assigned bytes + unsigned int max_allocated_space :4; // max allocation, 4 or 8 + xed_bool_t present : 1; + xed_bool_t immediate_is_unsigned : 1; +} xed_immdis_t; + + + + +XED_DLL_EXPORT void xed_immdis_init(xed_immdis_t* p, xed_uint_t max_bytes); + +/// @name Sizes and lengths +//@{ +/// return the number of bytes added +XED_DLL_EXPORT unsigned int xed_immdis_get_bytes(const xed_immdis_t* p) ; + +//@} + +/// @name Accessors for the value of the immediate or displacement +//@{ +XED_DLL_EXPORT xed_int64_t +xed_immdis_get_signed64(const xed_immdis_t* p); + +XED_DLL_EXPORT xed_uint64_t +xed_immdis_get_unsigned64(const xed_immdis_t* p); + +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_zero(const xed_immdis_t* p) ; + +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_one(const xed_immdis_t* p) ; + +/// Access the i'th byte of the immediate +XED_DLL_EXPORT xed_uint8_t xed_immdis_get_byte(const xed_immdis_t* p, unsigned int i) ; +//@} + +/// @name Presence / absence of an immediate or displacement +//@{ +XED_DLL_EXPORT void xed_immdis_set_present(xed_immdis_t* p) ; + +/// True if the object has had a value or individual bytes added to it. +XED_DLL_EXPORT xed_bool_t xed_immdis_is_present(const xed_immdis_t* p) ; +//@} + + +/// @name Initialization and setup +//@{ +XED_DLL_EXPORT void xed_immdis_set_max_len(xed_immdis_t* p, unsigned int mx) ; +XED_DLL_EXPORT void +xed_immdis_zero(xed_immdis_t* p); + +XED_DLL_EXPORT unsigned int xed_immdis_get_max_length(const xed_immdis_t* p) ; + +//@} + +/// @name Signed vs Unsigned +//@{ +/// Return true if signed. +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_unsigned(const xed_immdis_t* p) ; +/// Return true if signed. +XED_DLL_EXPORT xed_bool_t +xed_immdis_is_signed(const xed_immdis_t* p) ; + +/// Set the immediate to be signed; For decoder use only. +XED_DLL_EXPORT void +xed_immdis_set_signed(xed_immdis_t* p) ; +/// Set the immediate to be unsigned; For decoder use only. +XED_DLL_EXPORT void +xed_immdis_set_unsigned( xed_immdis_t* p) ; +//@} + + +/// @name Adding / setting values +//@{ +XED_DLL_EXPORT void +xed_immdis_add_byte(xed_immdis_t* p, xed_uint8_t b); + + +XED_DLL_EXPORT void +xed_immdis_add_byte_array(xed_immdis_t* p, int nb, xed_uint8_t* ba); + +/// Add 1, 2, 4 or 8 bytes depending on the value x and the mask of +/// legal_widths. The default value of legal_widths = 0x5 only stops +/// adding bytes only on 1 or 4 byte quantities - depending on which +/// bytes of x are zero -- as is used for most memory addressing. You +/// can set legal_widths to 0x7 for branches (1, 2 or 4 byte branch +/// displacements). Or if you have an 8B displacement, you can set +/// legal_widths to 0x8. NOTE: add_shortest_width will add up to +/// XED_MAX_IMMDIS_BYTES if the x value requires it. NOTE: 16b memory +/// addressing can have 16b immediates. +XED_DLL_EXPORT void +xed_immdis_add_shortest_width_signed(xed_immdis_t* p, xed_int64_t x, xed_uint8_t legal_widths); + +/// See add_shortest_width_signed() +XED_DLL_EXPORT void +xed_immdis_add_shortest_width_unsigned(xed_immdis_t* p, xed_uint64_t x, xed_uint8_t legal_widths ); + + +/// add an 8 bit value to the byte array +XED_DLL_EXPORT void +xed_immdis_add8(xed_immdis_t* p, xed_int8_t d); + +/// add a 16 bit value to the byte array +XED_DLL_EXPORT void +xed_immdis_add16(xed_immdis_t* p, xed_int16_t d); + +/// add a 32 bit value to the byte array +XED_DLL_EXPORT void +xed_immdis_add32(xed_immdis_t* p, xed_int32_t d); + +/// add a 64 bit value to the byte array. +XED_DLL_EXPORT void +xed_immdis_add64(xed_immdis_t* p, xed_int64_t d); + +//@} + + +/// @name printing / debugging +//@{ + +/// just print the raw bytes in hex with a leading 0x +XED_DLL_EXPORT int xed_immdis_print(const xed_immdis_t* p, char* buf, int buflen); + +/// Print the value as a signed or unsigned number depending on the +/// value of the immediate_is_unsigned variable. +XED_DLL_EXPORT int +xed_immdis_print_signed_or_unsigned(const xed_immdis_t* p, char* buf, int buflen); + +/// print the signed value, appropriate width, with a leading 0x +XED_DLL_EXPORT int +xed_immdis_print_value_signed(const xed_immdis_t* p, char* buf, int buflen); + +/// print the unsigned value, appropriate width, with a leading 0x +XED_DLL_EXPORT int +xed_immdis_print_value_unsigned(const xed_immdis_t* p, char* buf, int buflen); + +#endif + +//@} + + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-immed.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-immed.h new file mode 100644 index 0000000..22e6c65 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-immed.h @@ -0,0 +1,48 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-immed.h +/// + +#ifndef XED_IMMED_H +# define XED_IMMED_H + +#include "xed-types.h" +#include "xed-common-defs.h" +#include "xed-util.h" + +XED_DLL_EXPORT xed_int64_t xed_immed_from_bytes(xed_int8_t* bytes, xed_uint_t n); + /* + Convert an array of bytes representing a Little Endian byte ordering + of a number (11 22 33 44 55.. 88), in to a a 64b SIGNED number. That gets + stored in memory in little endian format of course. + + Input 11 22 33 44 55 66 77 88, 8 + Output 0x8877665544332211 (stored in memory as (lsb) 11 22 33 44 55 66 77 88 (msb)) + + Input f0, 1 + Output 0xffff_ffff_ffff_fff0 (stored in memory as f0 ff ff ff ff ff ff ff) + + Input f0 00, 2 + Output 0x0000_0000_0000_00F0 (stored in memory a f0 00 00 00 00 00 00 00) + + Input 03, 1 + Output 0x0000_0000_0000_0030 (stored in memory a 30 00 00 00 00 00 00 00) + */ + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-init-pointer-names.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-init-pointer-names.h new file mode 100644 index 0000000..ceb07f7 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-init-pointer-names.h @@ -0,0 +1,27 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-init-pointer-names.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_INIT_POINTER_NAMES_H) +# define XED_INIT_POINTER_NAMES_H +#include "xed-internal-header.h" +#define XED_MAX_POINTER_NAMES 65 +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-init.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-init.h new file mode 100644 index 0000000..9f5249d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-init.h @@ -0,0 +1,35 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-init.h +/// + + + + +#if !defined(XED_INIT_H) +# define XED_INIT_H + + +/// @ingroup INIT +/// This is the call to initialize the XED encode and decode tables. It +/// must be called once before using XED. +void XED_DLL_EXPORT xed_tables_init(void); + +//////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-inst.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-inst.h new file mode 100644 index 0000000..fea79db --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-inst.h @@ -0,0 +1,368 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-inst.h + + +#if !defined(XED_INST_H) +# define XED_INST_H + +#include "xed-util.h" +#include "xed-portability.h" +#include "xed-category-enum.h" // generated +#include "xed-extension-enum.h" //generated +#include "xed-iclass-enum.h" //generated +#include "xed-operand-enum.h" // generated +#include "xed-operand-visibility-enum.h" //generated +#include "xed-operand-action-enum.h" // generated +#include "xed-operand-convert-enum.h" // generated +#include "xed-operand-type-enum.h" // generated +#include "xed-nonterminal-enum.h" // a generated file +#include "xed-operand-width-enum.h" // a generated file +#include "xed-operand-element-xtype-enum.h" // a generated file +#include "xed-reg-enum.h" // a generated file +#include "xed-attribute-enum.h" // a generated file +#include "xed-exception-enum.h" // a generated file +#include "xed-iform-enum.h" // a generated file +#include "xed-iform-map.h" +#include "xed-attributes.h" + +struct xed_decoded_inst_s; //fwd-decl + +typedef void (*xed_operand_extractor_fn_t)(struct xed_decoded_inst_s* xds); + + +/// @ingroup DEC +/// Constant information about an individual generic operand, like an +///operand template, describing the operand properties. See @ref DEC for +///API information. +typedef struct xed_operand_s +{ + xed_uint8_t _name; // xed_operand_enum_t + + // implicit, explicit, suppressed + xed_uint8_t _operand_visibility; // xed_operand_visibility_enum_t + xed_uint8_t _rw; // read or written // xed_operand_action_enum_t + + // width code, could be invalid (then use register name) + xed_uint8_t _oc2; // xed_operand_width_enum_t + + // IMM, IMM_CONST, NT_LOOKUP_FN, REG, ERROR + xed_uint8_t _type; //xed_operand_type_enum_t + xed_uint8_t _xtype; // xed data type: u32, f32, etc. //xed_operand_element_xtype_enum_t + xed_uint8_t _cvt_idx; // decoration index + xed_uint8_t _nt; + union { + xed_uint32_t _imm; // value for some constant immmed + xed_nonterminal_enum_t _nt; // for nt_lookup_fn's + xed_reg_enum_t _reg; // register name + } _u; +} xed_operand_t; + +/// @name xed_inst_t Template Operands Access +//@{ +/// @ingroup DEC +static XED_INLINE xed_operand_enum_t +xed_operand_name(const xed_operand_t* p) { + return (xed_operand_enum_t)p->_name; +} + + +/// @ingroup DEC +static XED_INLINE xed_operand_visibility_enum_t +xed_operand_operand_visibility( const xed_operand_t* p) { + return (xed_operand_visibility_enum_t)(p->_operand_visibility); +} + + +/// @ingroup DEC +/// @return The #xed_operand_type_enum_t of the operand template. +/// This is probably not what you want. +static XED_INLINE xed_operand_type_enum_t +xed_operand_type(const xed_operand_t* p) { + return (xed_operand_type_enum_t)p->_type; +} + +/// @ingroup DEC +/// @return The #xed_operand_element_xtype_enum_t of the operand template. +/// This is probably not what you want. +static XED_INLINE xed_operand_element_xtype_enum_t +xed_operand_xtype(const xed_operand_t* p) { + return (xed_operand_element_xtype_enum_t)p->_xtype; +} + + +/// @ingroup DEC +static XED_INLINE xed_operand_width_enum_t +xed_operand_width(const xed_operand_t* p) { + return (xed_operand_width_enum_t)p->_oc2; +} + +/// @ingroup DEC +/// @param p an operand template, #xed_operand_t. +/// @param eosz effective operand size of the instruction, 1 | 2 | 3 for +/// 16 | 32 | 64 bits respectively. 0 is invalid. +/// @return the actual width of operand in bits. +/// See xed_decoded_inst_operand_length_bits() for a more general solution. +XED_DLL_EXPORT xed_uint32_t +xed_operand_width_bits(const xed_operand_t* p, + const xed_uint32_t eosz); + +/// @ingroup DEC +static XED_INLINE xed_nonterminal_enum_t +xed_operand_nonterminal_name(const xed_operand_t* p) { + if (p->_nt) + return p->_u._nt; + return XED_NONTERMINAL_INVALID; +} + +/// @ingroup DEC +/// Careful with this one -- use #xed_decoded_inst_get_reg()! This one is +/// probably not what you think it is. It is only used for hard-coded +/// registers implicit in the instruction encoding. Most likely you want to +/// get the #xed_operand_enum_t and then look up the instruction using +/// #xed_decoded_inst_get_reg(). The hard-coded registers are also available +/// that way. +/// @param p an operand template, #xed_operand_t. +/// @return the implicit or suppressed registers, type #xed_reg_enum_t +static XED_INLINE xed_reg_enum_t xed_operand_reg(const xed_operand_t* p) { + if (xed_operand_type(p) == XED_OPERAND_TYPE_REG) + return p->_u._reg; + return XED_REG_INVALID; +} + + + +/// @ingroup DEC +/// Careful with this one; See #xed_operand_is_register(). +/// @param p an operand template, #xed_operand_t. +/// @return 1 if the operand template represents are register-type +/// operand. +/// +/// Related functions: +/// Use #xed_decoded_inst_get_reg() to get the decoded name of /// the +/// register, #xed_reg_enum_t. Use #xed_operand_is_register() to test +/// #xed_operand_enum_t names. +static XED_INLINE xed_uint_t +xed_operand_template_is_register(const xed_operand_t* p) { + return p->_nt || p->_type == XED_OPERAND_TYPE_REG; +} + +/// @ingroup DEC +/// @param p an operand template, #xed_operand_t. +/// These operands represent branch displacements, memory displacements and +/// various immediates +static XED_INLINE xed_uint32_t xed_operand_imm(const xed_operand_t* p) { + if (xed_operand_type(p) == XED_OPERAND_TYPE_IMM_CONST) + return p->_u._imm; + return 0; +} + +/// @ingroup DEC +/// Print the operand p into the buffer buf, of length buflen. +/// @param p an operand template, #xed_operand_t. +/// @param buf buffer that gets filled in +/// @param buflen maximum buffer length +XED_DLL_EXPORT void +xed_operand_print(const xed_operand_t* p, char* buf, int buflen); +//@} + +/// @name xed_inst_t Template Operand Enum Name Classification +//@{ +/// @ingroup DEC +/// Tests the enum for inclusion in XED_OPERAND_REG0 through XED_OPERAND_REG9. +/// @param name the operand name, type #xed_operand_enum_t +/// @return 1 if the operand name is REG0...REG9, 0 otherwise. +/// +///Note there are other registers for memory addressing; See +/// #xed_operand_is_memory_addressing_register . +static XED_INLINE xed_uint_t xed_operand_is_register(xed_operand_enum_t name) { + return name >= XED_OPERAND_REG0 && name <= XED_OPERAND_REG9; +} +/// @ingroup DEC +/// Tests the enum for inclusion in XED_OPERAND_{BASE0,BASE1,INDEX,SEG0,SEG1} +/// @param name the operand name, type #xed_operand_enum_t +/// @return 1 if the operand name is for a memory addressing register operand, 0 +/// otherwise. See also #xed_operand_is_register . +static XED_INLINE xed_uint_t +xed_operand_is_memory_addressing_register(xed_operand_enum_t name) { + return ( name == XED_OPERAND_BASE0 || + name == XED_OPERAND_INDEX || + name == XED_OPERAND_SEG0 || + name == XED_OPERAND_BASE1 || + name == XED_OPERAND_SEG1 ); +} + +//@} + +/// @name xed_inst_t Template Operand Read/Written +//@{ +/// @ingroup DEC +/// DEPRECATED: Returns the raw R/W action. There are many cases for conditional reads +/// and writes. See #xed_decoded_inst_operand_action(). +static XED_INLINE xed_operand_action_enum_t +xed_operand_rw(const xed_operand_t* p) { + return (xed_operand_action_enum_t)p->_rw; +} + +/// @ingroup DEC +/// If the operand is read, including conditional reads +XED_DLL_EXPORT xed_uint_t xed_operand_read(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is read-only, including conditional reads +XED_DLL_EXPORT xed_uint_t xed_operand_read_only(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is written, including conditional writes +XED_DLL_EXPORT xed_uint_t xed_operand_written(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is written-only, including conditional writes +XED_DLL_EXPORT xed_uint_t xed_operand_written_only(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand is read-and-written, conditional reads and conditional writes +XED_DLL_EXPORT xed_uint_t xed_operand_read_and_written(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand has a conditional read (may also write) +XED_DLL_EXPORT xed_uint_t xed_operand_conditional_read(const xed_operand_t* p); +/// @ingroup DEC +/// If the operand has a conditional write (may also read) +XED_DLL_EXPORT xed_uint_t xed_operand_conditional_write(const xed_operand_t* p); +//@} + + +/// @ingroup DEC +/// constant information about a decoded instruction form, including +/// the pointer to the constant operand properties #xed_operand_t for this +/// instruction form. +typedef struct xed_inst_s { + + + // rflags info -- index in to the 2 tables of flags information. + // If _flag_complex is true, then the data are in the + // xed_flags_complex_table[]. Otherwise, the data are in the + // xed_flags_simple_table[]. + + //xed_instruction_fixed_bit_confirmer_fn_t _confirmer; + + // number of operands in the operands array + xed_uint8_t _noperands; + xed_uint8_t _cpl; // the nominal CPL for the instruction. + xed_uint8_t _flag_complex; /* 1/0 valued, bool type */ + xed_uint8_t _exceptions; //xed_exception_enum_t + + xed_uint16_t _flag_info_index; + + xed_uint16_t _iform_enum; //xed_iform_enum_t + // index into the xed_operand[] array of xed_operand_t structures + xed_uint16_t _operand_base; + // index to table of xed_attributes_t structures + xed_uint16_t _attributes; + +} xed_inst_t; + +/// @name xed_inst_t Template Instruction Information +//@{ +/// @ingroup DEC +/// xed_inst_cpl() is DEPRECATED. Please use +/// "xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_RING0)" +/// instead. +///Return the current privilege level (CPL) required for execution, 0 or +///3. If the value is zero, then the instruction can only execute in ring 0. +XED_DLL_EXPORT unsigned int xed_inst_cpl(const xed_inst_t* p) ; + + +//These next few are not doxygen commented because I want people to use the +//higher level interface in xed-decoded-inst.h. +static XED_INLINE xed_iform_enum_t xed_inst_iform_enum(const xed_inst_t* p) { + return (xed_iform_enum_t)p->_iform_enum; +} + +static XED_INLINE xed_iclass_enum_t xed_inst_iclass(const xed_inst_t* p) { + return xed_iform_to_iclass(xed_inst_iform_enum(p)); +} + +static XED_INLINE xed_category_enum_t xed_inst_category(const xed_inst_t* p) { + return xed_iform_to_category(xed_inst_iform_enum(p)); +} + +static XED_INLINE xed_extension_enum_t xed_inst_extension(const xed_inst_t* p) { + return xed_iform_to_extension(xed_inst_iform_enum(p)); +} +static XED_INLINE xed_isa_set_enum_t xed_inst_isa_set(const xed_inst_t* p) { + return xed_iform_to_isa_set(xed_inst_iform_enum(p)); +} + + + +///@ingroup DEC +/// Number of instruction operands +static XED_INLINE unsigned int xed_inst_noperands(const xed_inst_t* p) { + return p->_noperands; +} + +///@ingroup DEC +/// Obtain a pointer to an individual operand +XED_DLL_EXPORT const xed_operand_t* +xed_inst_operand(const xed_inst_t* p, unsigned int i); + + + +XED_DLL_EXPORT xed_uint32_t xed_inst_flag_info_index(const xed_inst_t* p); + +//@} + +/// @name xed_inst_t Attribute access +//@{ +/// @ingroup DEC +/// Scan for the attribute attr and return 1 if it is found, 0 otherwise. +XED_DLL_EXPORT xed_uint32_t +xed_inst_get_attribute(const xed_inst_t* p, + xed_attribute_enum_t attr); + +/// @ingroup DEC +/// Return the attributes bit vector +XED_DLL_EXPORT xed_attributes_t +xed_inst_get_attributes(const xed_inst_t* p); + + +/// @ingroup DEC +/// Return the maximum number of defined attributes, independent of any +/// instruction. +XED_DLL_EXPORT unsigned int xed_attribute_max(void); + +/// @ingroup DEC +/// Return the i'th global attribute in a linear sequence, independent of +/// any instruction. This is used for scanning and printing all attributes. +XED_DLL_EXPORT xed_attribute_enum_t xed_attribute(unsigned int i); + +//@} + +/// @name Exceptions +//@{ +/// @ingroup DEC +/// Return #xed_exception_enum_t if present for the specified instruction. +/// This is currently only used for SSE and AVX instructions. +static XED_INLINE +xed_exception_enum_t xed_inst_exception(const xed_inst_t* p) { + return (xed_exception_enum_t)p->_exceptions; +} + +//@} +/// @ingroup DEC +/// Return the base of instruction table. +XED_DLL_EXPORT const xed_inst_t* xed_inst_table_base(void); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-interface.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-interface.h new file mode 100644 index 0000000..eb8c621 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-interface.h @@ -0,0 +1,89 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/* +/// @file xed-interface.h +/// +*/ + + + +#if !defined(XED_INTERFACE_H) +# define XED_INTERFACE_H + +#if defined(_WIN32) && defined(_MANAGED) +#pragma unmanaged +#endif + +#include "xed-build-defines.h" /* generated */ +#include "xed-portability.h" + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-operand-enum.h" + +#include "xed-init.h" +#include "xed-decode.h" +#include "xed-ild.h" + +#include "xed-state.h" /* dstate, legacy */ +#include "xed-syntax-enum.h" +#include "xed-reg-class-enum.h" /* generated */ +#include "xed-reg-class.h" + +#if defined(XED_ENCODER) +# include "xed-encode.h" +# include "xed-encoder-hl.h" +# include "xed-patch.h" +#endif +#if defined(XED_ENC2_ENCODER) +# include "xed-encode-direct.h" +# include "xed-encode-check.h" +#endif + +#include "xed-util.h" +#include "xed-operand-action.h" + +#include "xed-version.h" +#include "xed-decoded-inst.h" +#include "xed-decoded-inst-api.h" +#include "xed-inst.h" +#include "xed-iclass-enum.h" /* generated */ +#include "xed-category-enum.h" /* generated */ +#include "xed-extension-enum.h" /* generated */ +#include "xed-attribute-enum.h" /* generated */ +#include "xed-exception-enum.h" /* generated */ +#include "xed-operand-element-type-enum.h" /* generated */ +#include "xed-operand-element-xtype-enum.h" /* generated */ + +#include "xed-disas.h" // callbacks for disassembly +#include "xed-format-options.h" /* options for disassembly */ + +#include "xed-iform-enum.h" /* generated */ +/* indicates the first and last index of each iform, for building tables */ +#include "xed-iformfl-enum.h" /* generated */ +/* mapping iforms to iclass/category/extension */ +#include "xed-iform-map.h" +#include "xed-rep-prefix.h" + + +#include "xed-agen.h" +#include "xed-cpuid-rec.h" +#include "xed-isa-set.h" + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-isa-set-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-isa-set-enum.h new file mode 100644 index 0000000..6f98a76 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-isa-set-enum.h @@ -0,0 +1,410 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-isa-set-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ISA_SET_ENUM_H) +# define XED_ISA_SET_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ISA_SET_INVALID_DEFINED 1 +#define XED_ISA_SET_3DNOW_DEFINED 1 +#define XED_ISA_SET_3DNOW_PREFETCH_DEFINED 1 +#define XED_ISA_SET_ADOX_ADCX_DEFINED 1 +#define XED_ISA_SET_AES_DEFINED 1 +#define XED_ISA_SET_AMD_DEFINED 1 +#define XED_ISA_SET_AMD_INVLPGB_DEFINED 1 +#define XED_ISA_SET_AMX_BF16_DEFINED 1 +#define XED_ISA_SET_AMX_INT8_DEFINED 1 +#define XED_ISA_SET_AMX_TILE_DEFINED 1 +#define XED_ISA_SET_AVX_DEFINED 1 +#define XED_ISA_SET_AVX2_DEFINED 1 +#define XED_ISA_SET_AVX2GATHER_DEFINED 1 +#define XED_ISA_SET_AVX512BW_128_DEFINED 1 +#define XED_ISA_SET_AVX512BW_128N_DEFINED 1 +#define XED_ISA_SET_AVX512BW_256_DEFINED 1 +#define XED_ISA_SET_AVX512BW_512_DEFINED 1 +#define XED_ISA_SET_AVX512BW_KOP_DEFINED 1 +#define XED_ISA_SET_AVX512CD_128_DEFINED 1 +#define XED_ISA_SET_AVX512CD_256_DEFINED 1 +#define XED_ISA_SET_AVX512CD_512_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_128_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_128N_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_256_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_512_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_KOP_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512ER_512_DEFINED 1 +#define XED_ISA_SET_AVX512ER_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512F_128_DEFINED 1 +#define XED_ISA_SET_AVX512F_128N_DEFINED 1 +#define XED_ISA_SET_AVX512F_256_DEFINED 1 +#define XED_ISA_SET_AVX512F_512_DEFINED 1 +#define XED_ISA_SET_AVX512F_KOP_DEFINED 1 +#define XED_ISA_SET_AVX512F_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512PF_512_DEFINED 1 +#define XED_ISA_SET_AVX512_4FMAPS_512_DEFINED 1 +#define XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512_4VNNIW_512_DEFINED 1 +#define XED_ISA_SET_AVX512_BF16_128_DEFINED 1 +#define XED_ISA_SET_AVX512_BF16_256_DEFINED 1 +#define XED_ISA_SET_AVX512_BF16_512_DEFINED 1 +#define XED_ISA_SET_AVX512_BITALG_128_DEFINED 1 +#define XED_ISA_SET_AVX512_BITALG_256_DEFINED 1 +#define XED_ISA_SET_AVX512_BITALG_512_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_128_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_128N_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_256_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_512_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512_GFNI_128_DEFINED 1 +#define XED_ISA_SET_AVX512_GFNI_256_DEFINED 1 +#define XED_ISA_SET_AVX512_GFNI_512_DEFINED 1 +#define XED_ISA_SET_AVX512_IFMA_128_DEFINED 1 +#define XED_ISA_SET_AVX512_IFMA_256_DEFINED 1 +#define XED_ISA_SET_AVX512_IFMA_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VAES_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VAES_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VAES_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI2_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI2_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI2_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VNNI_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VNNI_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VNNI_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VP2INTERSECT_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VP2INTERSECT_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VP2INTERSECT_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VPCLMULQDQ_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VPCLMULQDQ_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VPCLMULQDQ_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VPOPCNTDQ_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VPOPCNTDQ_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VPOPCNTDQ_512_DEFINED 1 +#define XED_ISA_SET_AVXAES_DEFINED 1 +#define XED_ISA_SET_AVX_GFNI_DEFINED 1 +#define XED_ISA_SET_AVX_VNNI_DEFINED 1 +#define XED_ISA_SET_BMI1_DEFINED 1 +#define XED_ISA_SET_BMI2_DEFINED 1 +#define XED_ISA_SET_CET_DEFINED 1 +#define XED_ISA_SET_CLDEMOTE_DEFINED 1 +#define XED_ISA_SET_CLFLUSHOPT_DEFINED 1 +#define XED_ISA_SET_CLFSH_DEFINED 1 +#define XED_ISA_SET_CLWB_DEFINED 1 +#define XED_ISA_SET_CLZERO_DEFINED 1 +#define XED_ISA_SET_CMOV_DEFINED 1 +#define XED_ISA_SET_CMPXCHG16B_DEFINED 1 +#define XED_ISA_SET_ENQCMD_DEFINED 1 +#define XED_ISA_SET_F16C_DEFINED 1 +#define XED_ISA_SET_FAT_NOP_DEFINED 1 +#define XED_ISA_SET_FCMOV_DEFINED 1 +#define XED_ISA_SET_FMA_DEFINED 1 +#define XED_ISA_SET_FMA4_DEFINED 1 +#define XED_ISA_SET_FXSAVE_DEFINED 1 +#define XED_ISA_SET_FXSAVE64_DEFINED 1 +#define XED_ISA_SET_GFNI_DEFINED 1 +#define XED_ISA_SET_HRESET_DEFINED 1 +#define XED_ISA_SET_I186_DEFINED 1 +#define XED_ISA_SET_I286PROTECTED_DEFINED 1 +#define XED_ISA_SET_I286REAL_DEFINED 1 +#define XED_ISA_SET_I386_DEFINED 1 +#define XED_ISA_SET_I486_DEFINED 1 +#define XED_ISA_SET_I486REAL_DEFINED 1 +#define XED_ISA_SET_I86_DEFINED 1 +#define XED_ISA_SET_INVPCID_DEFINED 1 +#define XED_ISA_SET_KEYLOCKER_DEFINED 1 +#define XED_ISA_SET_KEYLOCKER_WIDE_DEFINED 1 +#define XED_ISA_SET_LAHF_DEFINED 1 +#define XED_ISA_SET_LONGMODE_DEFINED 1 +#define XED_ISA_SET_LWP_DEFINED 1 +#define XED_ISA_SET_LZCNT_DEFINED 1 +#define XED_ISA_SET_MCOMMIT_DEFINED 1 +#define XED_ISA_SET_MONITOR_DEFINED 1 +#define XED_ISA_SET_MONITORX_DEFINED 1 +#define XED_ISA_SET_MOVBE_DEFINED 1 +#define XED_ISA_SET_MOVDIR_DEFINED 1 +#define XED_ISA_SET_MPX_DEFINED 1 +#define XED_ISA_SET_PAUSE_DEFINED 1 +#define XED_ISA_SET_PCLMULQDQ_DEFINED 1 +#define XED_ISA_SET_PCONFIG_DEFINED 1 +#define XED_ISA_SET_PENTIUMMMX_DEFINED 1 +#define XED_ISA_SET_PENTIUMREAL_DEFINED 1 +#define XED_ISA_SET_PKU_DEFINED 1 +#define XED_ISA_SET_POPCNT_DEFINED 1 +#define XED_ISA_SET_PPRO_DEFINED 1 +#define XED_ISA_SET_PPRO_UD0_LONG_DEFINED 1 +#define XED_ISA_SET_PPRO_UD0_SHORT_DEFINED 1 +#define XED_ISA_SET_PREFETCHW_DEFINED 1 +#define XED_ISA_SET_PREFETCHWT1_DEFINED 1 +#define XED_ISA_SET_PREFETCH_NOP_DEFINED 1 +#define XED_ISA_SET_PTWRITE_DEFINED 1 +#define XED_ISA_SET_RDPID_DEFINED 1 +#define XED_ISA_SET_RDPMC_DEFINED 1 +#define XED_ISA_SET_RDPRU_DEFINED 1 +#define XED_ISA_SET_RDRAND_DEFINED 1 +#define XED_ISA_SET_RDSEED_DEFINED 1 +#define XED_ISA_SET_RDTSCP_DEFINED 1 +#define XED_ISA_SET_RDWRFSGS_DEFINED 1 +#define XED_ISA_SET_RTM_DEFINED 1 +#define XED_ISA_SET_SERIALIZE_DEFINED 1 +#define XED_ISA_SET_SGX_DEFINED 1 +#define XED_ISA_SET_SGX_ENCLV_DEFINED 1 +#define XED_ISA_SET_SHA_DEFINED 1 +#define XED_ISA_SET_SMAP_DEFINED 1 +#define XED_ISA_SET_SMX_DEFINED 1 +#define XED_ISA_SET_SNP_DEFINED 1 +#define XED_ISA_SET_SSE_DEFINED 1 +#define XED_ISA_SET_SSE2_DEFINED 1 +#define XED_ISA_SET_SSE2MMX_DEFINED 1 +#define XED_ISA_SET_SSE3_DEFINED 1 +#define XED_ISA_SET_SSE3X87_DEFINED 1 +#define XED_ISA_SET_SSE4_DEFINED 1 +#define XED_ISA_SET_SSE42_DEFINED 1 +#define XED_ISA_SET_SSE4A_DEFINED 1 +#define XED_ISA_SET_SSEMXCSR_DEFINED 1 +#define XED_ISA_SET_SSE_PREFETCH_DEFINED 1 +#define XED_ISA_SET_SSSE3_DEFINED 1 +#define XED_ISA_SET_SSSE3MMX_DEFINED 1 +#define XED_ISA_SET_SVM_DEFINED 1 +#define XED_ISA_SET_TBM_DEFINED 1 +#define XED_ISA_SET_TDX_DEFINED 1 +#define XED_ISA_SET_TSX_LDTRK_DEFINED 1 +#define XED_ISA_SET_UINTR_DEFINED 1 +#define XED_ISA_SET_VAES_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_AES_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_MONTMUL_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_RNG_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_SHA_DEFINED 1 +#define XED_ISA_SET_VMFUNC_DEFINED 1 +#define XED_ISA_SET_VPCLMULQDQ_DEFINED 1 +#define XED_ISA_SET_VTX_DEFINED 1 +#define XED_ISA_SET_WAITPKG_DEFINED 1 +#define XED_ISA_SET_WBNOINVD_DEFINED 1 +#define XED_ISA_SET_X87_DEFINED 1 +#define XED_ISA_SET_XOP_DEFINED 1 +#define XED_ISA_SET_XSAVE_DEFINED 1 +#define XED_ISA_SET_XSAVEC_DEFINED 1 +#define XED_ISA_SET_XSAVEOPT_DEFINED 1 +#define XED_ISA_SET_XSAVES_DEFINED 1 +#define XED_ISA_SET_LAST_DEFINED 1 +typedef enum { + XED_ISA_SET_INVALID, + XED_ISA_SET_3DNOW, + XED_ISA_SET_3DNOW_PREFETCH, + XED_ISA_SET_ADOX_ADCX, + XED_ISA_SET_AES, + XED_ISA_SET_AMD, + XED_ISA_SET_AMD_INVLPGB, + XED_ISA_SET_AMX_BF16, + XED_ISA_SET_AMX_INT8, + XED_ISA_SET_AMX_TILE, + XED_ISA_SET_AVX, + XED_ISA_SET_AVX2, + XED_ISA_SET_AVX2GATHER, + XED_ISA_SET_AVX512BW_128, + XED_ISA_SET_AVX512BW_128N, + XED_ISA_SET_AVX512BW_256, + XED_ISA_SET_AVX512BW_512, + XED_ISA_SET_AVX512BW_KOP, + XED_ISA_SET_AVX512CD_128, + XED_ISA_SET_AVX512CD_256, + XED_ISA_SET_AVX512CD_512, + XED_ISA_SET_AVX512DQ_128, + XED_ISA_SET_AVX512DQ_128N, + XED_ISA_SET_AVX512DQ_256, + XED_ISA_SET_AVX512DQ_512, + XED_ISA_SET_AVX512DQ_KOP, + XED_ISA_SET_AVX512DQ_SCALAR, + XED_ISA_SET_AVX512ER_512, + XED_ISA_SET_AVX512ER_SCALAR, + XED_ISA_SET_AVX512F_128, + XED_ISA_SET_AVX512F_128N, + XED_ISA_SET_AVX512F_256, + XED_ISA_SET_AVX512F_512, + XED_ISA_SET_AVX512F_KOP, + XED_ISA_SET_AVX512F_SCALAR, + XED_ISA_SET_AVX512PF_512, + XED_ISA_SET_AVX512_4FMAPS_512, + XED_ISA_SET_AVX512_4FMAPS_SCALAR, + XED_ISA_SET_AVX512_4VNNIW_512, + XED_ISA_SET_AVX512_BF16_128, + XED_ISA_SET_AVX512_BF16_256, + XED_ISA_SET_AVX512_BF16_512, + XED_ISA_SET_AVX512_BITALG_128, + XED_ISA_SET_AVX512_BITALG_256, + XED_ISA_SET_AVX512_BITALG_512, + XED_ISA_SET_AVX512_FP16_128, + XED_ISA_SET_AVX512_FP16_128N, + XED_ISA_SET_AVX512_FP16_256, + XED_ISA_SET_AVX512_FP16_512, + XED_ISA_SET_AVX512_FP16_SCALAR, + XED_ISA_SET_AVX512_GFNI_128, + XED_ISA_SET_AVX512_GFNI_256, + XED_ISA_SET_AVX512_GFNI_512, + XED_ISA_SET_AVX512_IFMA_128, + XED_ISA_SET_AVX512_IFMA_256, + XED_ISA_SET_AVX512_IFMA_512, + XED_ISA_SET_AVX512_VAES_128, + XED_ISA_SET_AVX512_VAES_256, + XED_ISA_SET_AVX512_VAES_512, + XED_ISA_SET_AVX512_VBMI2_128, + XED_ISA_SET_AVX512_VBMI2_256, + XED_ISA_SET_AVX512_VBMI2_512, + XED_ISA_SET_AVX512_VBMI_128, + XED_ISA_SET_AVX512_VBMI_256, + XED_ISA_SET_AVX512_VBMI_512, + XED_ISA_SET_AVX512_VNNI_128, + XED_ISA_SET_AVX512_VNNI_256, + XED_ISA_SET_AVX512_VNNI_512, + XED_ISA_SET_AVX512_VP2INTERSECT_128, + XED_ISA_SET_AVX512_VP2INTERSECT_256, + XED_ISA_SET_AVX512_VP2INTERSECT_512, + XED_ISA_SET_AVX512_VPCLMULQDQ_128, + XED_ISA_SET_AVX512_VPCLMULQDQ_256, + XED_ISA_SET_AVX512_VPCLMULQDQ_512, + XED_ISA_SET_AVX512_VPOPCNTDQ_128, + XED_ISA_SET_AVX512_VPOPCNTDQ_256, + XED_ISA_SET_AVX512_VPOPCNTDQ_512, + XED_ISA_SET_AVXAES, + XED_ISA_SET_AVX_GFNI, + XED_ISA_SET_AVX_VNNI, + XED_ISA_SET_BMI1, + XED_ISA_SET_BMI2, + XED_ISA_SET_CET, + XED_ISA_SET_CLDEMOTE, + XED_ISA_SET_CLFLUSHOPT, + XED_ISA_SET_CLFSH, + XED_ISA_SET_CLWB, + XED_ISA_SET_CLZERO, + XED_ISA_SET_CMOV, + XED_ISA_SET_CMPXCHG16B, + XED_ISA_SET_ENQCMD, + XED_ISA_SET_F16C, + XED_ISA_SET_FAT_NOP, + XED_ISA_SET_FCMOV, + XED_ISA_SET_FMA, + XED_ISA_SET_FMA4, + XED_ISA_SET_FXSAVE, + XED_ISA_SET_FXSAVE64, + XED_ISA_SET_GFNI, + XED_ISA_SET_HRESET, + XED_ISA_SET_I186, + XED_ISA_SET_I286PROTECTED, + XED_ISA_SET_I286REAL, + XED_ISA_SET_I386, + XED_ISA_SET_I486, + XED_ISA_SET_I486REAL, + XED_ISA_SET_I86, + XED_ISA_SET_INVPCID, + XED_ISA_SET_KEYLOCKER, + XED_ISA_SET_KEYLOCKER_WIDE, + XED_ISA_SET_LAHF, + XED_ISA_SET_LONGMODE, + XED_ISA_SET_LWP, + XED_ISA_SET_LZCNT, + XED_ISA_SET_MCOMMIT, + XED_ISA_SET_MONITOR, + XED_ISA_SET_MONITORX, + XED_ISA_SET_MOVBE, + XED_ISA_SET_MOVDIR, + XED_ISA_SET_MPX, + XED_ISA_SET_PAUSE, + XED_ISA_SET_PCLMULQDQ, + XED_ISA_SET_PCONFIG, + XED_ISA_SET_PENTIUMMMX, + XED_ISA_SET_PENTIUMREAL, + XED_ISA_SET_PKU, + XED_ISA_SET_POPCNT, + XED_ISA_SET_PPRO, + XED_ISA_SET_PPRO_UD0_LONG, + XED_ISA_SET_PPRO_UD0_SHORT, + XED_ISA_SET_PREFETCHW, + XED_ISA_SET_PREFETCHWT1, + XED_ISA_SET_PREFETCH_NOP, + XED_ISA_SET_PTWRITE, + XED_ISA_SET_RDPID, + XED_ISA_SET_RDPMC, + XED_ISA_SET_RDPRU, + XED_ISA_SET_RDRAND, + XED_ISA_SET_RDSEED, + XED_ISA_SET_RDTSCP, + XED_ISA_SET_RDWRFSGS, + XED_ISA_SET_RTM, + XED_ISA_SET_SERIALIZE, + XED_ISA_SET_SGX, + XED_ISA_SET_SGX_ENCLV, + XED_ISA_SET_SHA, + XED_ISA_SET_SMAP, + XED_ISA_SET_SMX, + XED_ISA_SET_SNP, + XED_ISA_SET_SSE, + XED_ISA_SET_SSE2, + XED_ISA_SET_SSE2MMX, + XED_ISA_SET_SSE3, + XED_ISA_SET_SSE3X87, + XED_ISA_SET_SSE4, + XED_ISA_SET_SSE42, + XED_ISA_SET_SSE4A, + XED_ISA_SET_SSEMXCSR, + XED_ISA_SET_SSE_PREFETCH, + XED_ISA_SET_SSSE3, + XED_ISA_SET_SSSE3MMX, + XED_ISA_SET_SVM, + XED_ISA_SET_TBM, + XED_ISA_SET_TDX, + XED_ISA_SET_TSX_LDTRK, + XED_ISA_SET_UINTR, + XED_ISA_SET_VAES, + XED_ISA_SET_VIA_PADLOCK_AES, + XED_ISA_SET_VIA_PADLOCK_MONTMUL, + XED_ISA_SET_VIA_PADLOCK_RNG, + XED_ISA_SET_VIA_PADLOCK_SHA, + XED_ISA_SET_VMFUNC, + XED_ISA_SET_VPCLMULQDQ, + XED_ISA_SET_VTX, + XED_ISA_SET_WAITPKG, + XED_ISA_SET_WBNOINVD, + XED_ISA_SET_X87, + XED_ISA_SET_XOP, + XED_ISA_SET_XSAVE, + XED_ISA_SET_XSAVEC, + XED_ISA_SET_XSAVEOPT, + XED_ISA_SET_XSAVES, + XED_ISA_SET_LAST +} xed_isa_set_enum_t; + +/// This converts strings to #xed_isa_set_enum_t types. +/// @param s A C-string. +/// @return #xed_isa_set_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_isa_set_enum_t str2xed_isa_set_enum_t(const char* s); +/// This converts strings to #xed_isa_set_enum_t types. +/// @param p An enumeration element of type xed_isa_set_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_isa_set_enum_t2str(const xed_isa_set_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_isa_set_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_isa_set_enum_t xed_isa_set_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-isa-set.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-isa-set.h new file mode 100644 index 0000000..6952f5a --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-isa-set.h @@ -0,0 +1,37 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-isa-set.h + + +#if !defined(XED_ISA_SET_H) +# define XED_ISA_SET_H + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-isa-set-enum.h" /* generated */ +#include "xed-chip-enum.h" /* generated */ + +/// @ingroup ISASET +/// return 1 if the isa_set is part included in the specified chip, 0 +/// otherwise. +XED_DLL_EXPORT xed_bool_t +xed_isa_set_is_valid_for_chip(xed_isa_set_enum_t isa_set, + xed_chip_enum_t chip); + + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-machine-mode-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-machine-mode-enum.h new file mode 100644 index 0000000..b6a6581 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-machine-mode-enum.h @@ -0,0 +1,62 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-machine-mode-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_MACHINE_MODE_ENUM_H) +# define XED_MACHINE_MODE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_MACHINE_MODE_INVALID_DEFINED 1 +#define XED_MACHINE_MODE_LONG_64_DEFINED 1 +#define XED_MACHINE_MODE_LONG_COMPAT_32_DEFINED 1 +#define XED_MACHINE_MODE_LONG_COMPAT_16_DEFINED 1 +#define XED_MACHINE_MODE_LEGACY_32_DEFINED 1 +#define XED_MACHINE_MODE_LEGACY_16_DEFINED 1 +#define XED_MACHINE_MODE_REAL_16_DEFINED 1 +#define XED_MACHINE_MODE_REAL_32_DEFINED 1 +#define XED_MACHINE_MODE_LAST_DEFINED 1 +typedef enum { + XED_MACHINE_MODE_INVALID, + XED_MACHINE_MODE_LONG_64, ///< 64b operating mode + XED_MACHINE_MODE_LONG_COMPAT_32, ///< 32b protected mode + XED_MACHINE_MODE_LONG_COMPAT_16, ///< 16b protected mode + XED_MACHINE_MODE_LEGACY_32, ///< 32b protected mode + XED_MACHINE_MODE_LEGACY_16, ///< 16b protected mode + XED_MACHINE_MODE_REAL_16, ///< 16b real mode + XED_MACHINE_MODE_REAL_32, ///< 32b real mode (CS.D bit = 1) + XED_MACHINE_MODE_LAST +} xed_machine_mode_enum_t; + +/// This converts strings to #xed_machine_mode_enum_t types. +/// @param s A C-string. +/// @return #xed_machine_mode_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_machine_mode_enum_t str2xed_machine_mode_enum_t(const char* s); +/// This converts strings to #xed_machine_mode_enum_t types. +/// @param p An enumeration element of type xed_machine_mode_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_machine_mode_enum_t2str(const xed_machine_mode_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_machine_mode_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_machine_mode_enum_t xed_machine_mode_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-mapu-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-mapu-enum.h new file mode 100644 index 0000000..63c70ce --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-mapu-enum.h @@ -0,0 +1,80 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-mapu-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_MAPU_ENUM_H) +# define XED_MAPU_ENUM_H +#include "xed-common-hdrs.h" +#define XED_MAPU_INVALID_DEFINED 1 +#define XED_MAPU_AMD_3DNOW_DEFINED 1 +#define XED_MAPU_AMD_XOP8_DEFINED 1 +#define XED_MAPU_AMD_XOP9_DEFINED 1 +#define XED_MAPU_AMD_XOPA_DEFINED 1 +#define XED_MAPU_EVEX_MAP1_DEFINED 1 +#define XED_MAPU_EVEX_MAP2_DEFINED 1 +#define XED_MAPU_EVEX_MAP3_DEFINED 1 +#define XED_MAPU_EVEX_MAP5_DEFINED 1 +#define XED_MAPU_EVEX_MAP6_DEFINED 1 +#define XED_MAPU_LEGACY_MAP0_DEFINED 1 +#define XED_MAPU_LEGACY_MAP1_DEFINED 1 +#define XED_MAPU_LEGACY_MAP2_DEFINED 1 +#define XED_MAPU_LEGACY_MAP3_DEFINED 1 +#define XED_MAPU_VEX_MAP1_DEFINED 1 +#define XED_MAPU_VEX_MAP2_DEFINED 1 +#define XED_MAPU_VEX_MAP3_DEFINED 1 +#define XED_MAPU_LAST_DEFINED 1 +typedef enum { + XED_MAPU_INVALID, + XED_MAPU_AMD_3DNOW, + XED_MAPU_AMD_XOP8, + XED_MAPU_AMD_XOP9, + XED_MAPU_AMD_XOPA, + XED_MAPU_EVEX_MAP1, + XED_MAPU_EVEX_MAP2, + XED_MAPU_EVEX_MAP3, + XED_MAPU_EVEX_MAP5, + XED_MAPU_EVEX_MAP6, + XED_MAPU_LEGACY_MAP0, + XED_MAPU_LEGACY_MAP1, + XED_MAPU_LEGACY_MAP2, + XED_MAPU_LEGACY_MAP3, + XED_MAPU_VEX_MAP1, + XED_MAPU_VEX_MAP2, + XED_MAPU_VEX_MAP3, + XED_MAPU_LAST +} xed_mapu_enum_t; + +/// This converts strings to #xed_mapu_enum_t types. +/// @param s A C-string. +/// @return #xed_mapu_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_mapu_enum_t str2xed_mapu_enum_t(const char* s); +/// This converts strings to #xed_mapu_enum_t types. +/// @param p An enumeration element of type xed_mapu_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_mapu_enum_t2str(const xed_mapu_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_mapu_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_mapu_enum_t xed_mapu_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-nonterminal-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-nonterminal-enum.h new file mode 100644 index 0000000..59b42ae --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-nonterminal-enum.h @@ -0,0 +1,562 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-nonterminal-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_NONTERMINAL_ENUM_H) +# define XED_NONTERMINAL_ENUM_H +#include "xed-common-hdrs.h" +#define XED_NONTERMINAL_INVALID_DEFINED 1 +#define XED_NONTERMINAL_AR10_DEFINED 1 +#define XED_NONTERMINAL_AR11_DEFINED 1 +#define XED_NONTERMINAL_AR12_DEFINED 1 +#define XED_NONTERMINAL_AR13_DEFINED 1 +#define XED_NONTERMINAL_AR14_DEFINED 1 +#define XED_NONTERMINAL_AR15_DEFINED 1 +#define XED_NONTERMINAL_AR8_DEFINED 1 +#define XED_NONTERMINAL_AR9_DEFINED 1 +#define XED_NONTERMINAL_ARAX_DEFINED 1 +#define XED_NONTERMINAL_ARBP_DEFINED 1 +#define XED_NONTERMINAL_ARBX_DEFINED 1 +#define XED_NONTERMINAL_ARCX_DEFINED 1 +#define XED_NONTERMINAL_ARDI_DEFINED 1 +#define XED_NONTERMINAL_ARDX_DEFINED 1 +#define XED_NONTERMINAL_ARSI_DEFINED 1 +#define XED_NONTERMINAL_ARSP_DEFINED 1 +#define XED_NONTERMINAL_ASZ_NONTERM_DEFINED 1 +#define XED_NONTERMINAL_AVX512_ROUND_DEFINED 1 +#define XED_NONTERMINAL_AVX_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_AVX_SPLITTER_DEFINED 1 +#define XED_NONTERMINAL_A_GPR_B_DEFINED 1 +#define XED_NONTERMINAL_A_GPR_R_DEFINED 1 +#define XED_NONTERMINAL_BND_B_DEFINED 1 +#define XED_NONTERMINAL_BND_B_CHECK_DEFINED 1 +#define XED_NONTERMINAL_BND_R_DEFINED 1 +#define XED_NONTERMINAL_BND_R_CHECK_DEFINED 1 +#define XED_NONTERMINAL_BRANCH_HINT_DEFINED 1 +#define XED_NONTERMINAL_BRDISP32_DEFINED 1 +#define XED_NONTERMINAL_BRDISP8_DEFINED 1 +#define XED_NONTERMINAL_BRDISPZ_DEFINED 1 +#define XED_NONTERMINAL_CET_NO_TRACK_DEFINED 1 +#define XED_NONTERMINAL_CR_B_DEFINED 1 +#define XED_NONTERMINAL_CR_R_DEFINED 1 +#define XED_NONTERMINAL_CR_WIDTH_DEFINED 1 +#define XED_NONTERMINAL_DF64_DEFINED 1 +#define XED_NONTERMINAL_DR_R_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_128_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_16_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_1_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_2_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_32_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_4_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_64_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_8_BITS_DEFINED 1 +#define XED_NONTERMINAL_EVEX_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_EVEX_SPLITTER_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG1_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG1_MODE64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG1_NOT64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG_MODE64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG_NOT64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_ESEG_DEFINED 1 +#define XED_NONTERMINAL_FINAL_ESEG1_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG0_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG1_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG_MODE64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG_NOT64_DEFINED 1 +#define XED_NONTERMINAL_FIX_ROUND_LEN128_DEFINED 1 +#define XED_NONTERMINAL_FIX_ROUND_LEN512_DEFINED 1 +#define XED_NONTERMINAL_FORCE64_DEFINED 1 +#define XED_NONTERMINAL_GPR16_B_DEFINED 1 +#define XED_NONTERMINAL_GPR16_R_DEFINED 1 +#define XED_NONTERMINAL_GPR16_SB_DEFINED 1 +#define XED_NONTERMINAL_GPR32_B_DEFINED 1 +#define XED_NONTERMINAL_GPR32_R_DEFINED 1 +#define XED_NONTERMINAL_GPR32_SB_DEFINED 1 +#define XED_NONTERMINAL_GPR32_X_DEFINED 1 +#define XED_NONTERMINAL_GPR64_B_DEFINED 1 +#define XED_NONTERMINAL_GPR64_R_DEFINED 1 +#define XED_NONTERMINAL_GPR64_SB_DEFINED 1 +#define XED_NONTERMINAL_GPR64_X_DEFINED 1 +#define XED_NONTERMINAL_GPR8_B_DEFINED 1 +#define XED_NONTERMINAL_GPR8_R_DEFINED 1 +#define XED_NONTERMINAL_GPR8_SB_DEFINED 1 +#define XED_NONTERMINAL_GPRV_B_DEFINED 1 +#define XED_NONTERMINAL_GPRV_R_DEFINED 1 +#define XED_NONTERMINAL_GPRV_SB_DEFINED 1 +#define XED_NONTERMINAL_GPRY_B_DEFINED 1 +#define XED_NONTERMINAL_GPRY_R_DEFINED 1 +#define XED_NONTERMINAL_GPRZ_B_DEFINED 1 +#define XED_NONTERMINAL_GPRZ_R_DEFINED 1 +#define XED_NONTERMINAL_IGNORE66_DEFINED 1 +#define XED_NONTERMINAL_IMMUNE66_DEFINED 1 +#define XED_NONTERMINAL_IMMUNE66_LOOP64_DEFINED 1 +#define XED_NONTERMINAL_IMMUNE_REXW_DEFINED 1 +#define XED_NONTERMINAL_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_ISA_DEFINED 1 +#define XED_NONTERMINAL_MASK1_DEFINED 1 +#define XED_NONTERMINAL_MASKNOT0_DEFINED 1 +#define XED_NONTERMINAL_MASK_B_DEFINED 1 +#define XED_NONTERMINAL_MASK_N_DEFINED 1 +#define XED_NONTERMINAL_MASK_N32_DEFINED 1 +#define XED_NONTERMINAL_MASK_N64_DEFINED 1 +#define XED_NONTERMINAL_MASK_R_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP16_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP32_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP8_DEFINED 1 +#define XED_NONTERMINAL_MEMDISPV_DEFINED 1 +#define XED_NONTERMINAL_MMX_B_DEFINED 1 +#define XED_NONTERMINAL_MMX_R_DEFINED 1 +#define XED_NONTERMINAL_MODRM_DEFINED 1 +#define XED_NONTERMINAL_MODRM16_DEFINED 1 +#define XED_NONTERMINAL_MODRM32_DEFINED 1 +#define XED_NONTERMINAL_MODRM64ALT32_DEFINED 1 +#define XED_NONTERMINAL_NELEM_EIGHTHMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_FULL_DEFINED 1 +#define XED_NONTERMINAL_NELEM_FULLMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GSCAT_DEFINED 1 +#define XED_NONTERMINAL_NELEM_HALF_DEFINED 1 +#define XED_NONTERMINAL_NELEM_HALFMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_MEM128_DEFINED 1 +#define XED_NONTERMINAL_NELEM_MOVDDUP_DEFINED 1 +#define XED_NONTERMINAL_NELEM_QUARTER_DEFINED 1 +#define XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_SCALAR_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_4X_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE2_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE4_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE8_DEFINED 1 +#define XED_NONTERMINAL_OEAX_DEFINED 1 +#define XED_NONTERMINAL_ONE_DEFINED 1 +#define XED_NONTERMINAL_ORAX_DEFINED 1 +#define XED_NONTERMINAL_ORBP_DEFINED 1 +#define XED_NONTERMINAL_ORBX_DEFINED 1 +#define XED_NONTERMINAL_ORCX_DEFINED 1 +#define XED_NONTERMINAL_ORDX_DEFINED 1 +#define XED_NONTERMINAL_ORSP_DEFINED 1 +#define XED_NONTERMINAL_OSZ_NONTERM_DEFINED 1 +#define XED_NONTERMINAL_OVERRIDE_SEG0_DEFINED 1 +#define XED_NONTERMINAL_OVERRIDE_SEG1_DEFINED 1 +#define XED_NONTERMINAL_PREFIXES_DEFINED 1 +#define XED_NONTERMINAL_REFINING66_DEFINED 1 +#define XED_NONTERMINAL_REMOVE_SEGMENT_DEFINED 1 +#define XED_NONTERMINAL_RFLAGS_DEFINED 1 +#define XED_NONTERMINAL_RIP_DEFINED 1 +#define XED_NONTERMINAL_RIPA_DEFINED 1 +#define XED_NONTERMINAL_SAE_DEFINED 1 +#define XED_NONTERMINAL_SEG_DEFINED 1 +#define XED_NONTERMINAL_SEG_MOV_DEFINED 1 +#define XED_NONTERMINAL_SE_IMM8_DEFINED 1 +#define XED_NONTERMINAL_SIB_DEFINED 1 +#define XED_NONTERMINAL_SIB_BASE0_DEFINED 1 +#define XED_NONTERMINAL_SIMM8_DEFINED 1 +#define XED_NONTERMINAL_SIMMZ_DEFINED 1 +#define XED_NONTERMINAL_SRBP_DEFINED 1 +#define XED_NONTERMINAL_SRSP_DEFINED 1 +#define XED_NONTERMINAL_TMM_B_DEFINED 1 +#define XED_NONTERMINAL_TMM_N_DEFINED 1 +#define XED_NONTERMINAL_TMM_R_DEFINED 1 +#define XED_NONTERMINAL_UIMM16_DEFINED 1 +#define XED_NONTERMINAL_UIMM32_DEFINED 1 +#define XED_NONTERMINAL_UIMM8_DEFINED 1 +#define XED_NONTERMINAL_UIMM8_1_DEFINED 1 +#define XED_NONTERMINAL_UIMMV_DEFINED 1 +#define XED_NONTERMINAL_UISA_VMODRM_XMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VMODRM_YMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VMODRM_ZMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_BASE_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_INDEX_XMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_INDEX_YMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_XMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_YMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_ZMM_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_B_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_B_32_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_B_64_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_N_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_N_32_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_N_64_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_R_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_R_32_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_R_64_DEFINED 1 +#define XED_NONTERMINAL_VGPR64_B_DEFINED 1 +#define XED_NONTERMINAL_VGPR64_N_DEFINED 1 +#define XED_NONTERMINAL_VGPR64_R_DEFINED 1 +#define XED_NONTERMINAL_VGPRY_B_DEFINED 1 +#define XED_NONTERMINAL_VGPRY_N_DEFINED 1 +#define XED_NONTERMINAL_VGPRY_R_DEFINED 1 +#define XED_NONTERMINAL_VMODRM_XMM_DEFINED 1 +#define XED_NONTERMINAL_VMODRM_YMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_BASE_DEFINED 1 +#define XED_NONTERMINAL_VSIB_INDEX_XMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_INDEX_YMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_XMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_YMM_DEFINED 1 +#define XED_NONTERMINAL_X87_DEFINED 1 +#define XED_NONTERMINAL_XMM_B_DEFINED 1 +#define XED_NONTERMINAL_XMM_B3_DEFINED 1 +#define XED_NONTERMINAL_XMM_B3_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_B3_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_B_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_B_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_N_DEFINED 1 +#define XED_NONTERMINAL_XMM_N3_DEFINED 1 +#define XED_NONTERMINAL_XMM_N3_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_N3_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_N_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_N_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_R_DEFINED 1 +#define XED_NONTERMINAL_XMM_R3_DEFINED 1 +#define XED_NONTERMINAL_XMM_R3_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_R3_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_R_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_R_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_SE_DEFINED 1 +#define XED_NONTERMINAL_XMM_SE32_DEFINED 1 +#define XED_NONTERMINAL_XMM_SE64_DEFINED 1 +#define XED_NONTERMINAL_XOP_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_YMM_B_DEFINED 1 +#define XED_NONTERMINAL_YMM_B3_DEFINED 1 +#define XED_NONTERMINAL_YMM_B3_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_B3_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_B_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_B_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_N_DEFINED 1 +#define XED_NONTERMINAL_YMM_N3_DEFINED 1 +#define XED_NONTERMINAL_YMM_N3_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_N3_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_N_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_N_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_R_DEFINED 1 +#define XED_NONTERMINAL_YMM_R3_DEFINED 1 +#define XED_NONTERMINAL_YMM_R3_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_R3_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_R_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_R_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_SE_DEFINED 1 +#define XED_NONTERMINAL_YMM_SE32_DEFINED 1 +#define XED_NONTERMINAL_YMM_SE64_DEFINED 1 +#define XED_NONTERMINAL_ZMM_B3_DEFINED 1 +#define XED_NONTERMINAL_ZMM_B3_32_DEFINED 1 +#define XED_NONTERMINAL_ZMM_B3_64_DEFINED 1 +#define XED_NONTERMINAL_ZMM_N3_DEFINED 1 +#define XED_NONTERMINAL_ZMM_N3_32_DEFINED 1 +#define XED_NONTERMINAL_ZMM_N3_64_DEFINED 1 +#define XED_NONTERMINAL_ZMM_R3_DEFINED 1 +#define XED_NONTERMINAL_ZMM_R3_32_DEFINED 1 +#define XED_NONTERMINAL_ZMM_R3_64_DEFINED 1 +#define XED_NONTERMINAL_LAST_DEFINED 1 +typedef enum { + XED_NONTERMINAL_INVALID, + XED_NONTERMINAL_AR10, + XED_NONTERMINAL_AR11, + XED_NONTERMINAL_AR12, + XED_NONTERMINAL_AR13, + XED_NONTERMINAL_AR14, + XED_NONTERMINAL_AR15, + XED_NONTERMINAL_AR8, + XED_NONTERMINAL_AR9, + XED_NONTERMINAL_ARAX, + XED_NONTERMINAL_ARBP, + XED_NONTERMINAL_ARBX, + XED_NONTERMINAL_ARCX, + XED_NONTERMINAL_ARDI, + XED_NONTERMINAL_ARDX, + XED_NONTERMINAL_ARSI, + XED_NONTERMINAL_ARSP, + XED_NONTERMINAL_ASZ_NONTERM, + XED_NONTERMINAL_AVX512_ROUND, + XED_NONTERMINAL_AVX_INSTRUCTIONS, + XED_NONTERMINAL_AVX_SPLITTER, + XED_NONTERMINAL_A_GPR_B, + XED_NONTERMINAL_A_GPR_R, + XED_NONTERMINAL_BND_B, + XED_NONTERMINAL_BND_B_CHECK, + XED_NONTERMINAL_BND_R, + XED_NONTERMINAL_BND_R_CHECK, + XED_NONTERMINAL_BRANCH_HINT, + XED_NONTERMINAL_BRDISP32, + XED_NONTERMINAL_BRDISP8, + XED_NONTERMINAL_BRDISPZ, + XED_NONTERMINAL_CET_NO_TRACK, + XED_NONTERMINAL_CR_B, + XED_NONTERMINAL_CR_R, + XED_NONTERMINAL_CR_WIDTH, + XED_NONTERMINAL_DF64, + XED_NONTERMINAL_DR_R, + XED_NONTERMINAL_ESIZE_128_BITS, + XED_NONTERMINAL_ESIZE_16_BITS, + XED_NONTERMINAL_ESIZE_1_BITS, + XED_NONTERMINAL_ESIZE_2_BITS, + XED_NONTERMINAL_ESIZE_32_BITS, + XED_NONTERMINAL_ESIZE_4_BITS, + XED_NONTERMINAL_ESIZE_64_BITS, + XED_NONTERMINAL_ESIZE_8_BITS, + XED_NONTERMINAL_EVEX_INSTRUCTIONS, + XED_NONTERMINAL_EVEX_SPLITTER, + XED_NONTERMINAL_FINAL_DSEG, + XED_NONTERMINAL_FINAL_DSEG1, + XED_NONTERMINAL_FINAL_DSEG1_MODE64, + XED_NONTERMINAL_FINAL_DSEG1_NOT64, + XED_NONTERMINAL_FINAL_DSEG_MODE64, + XED_NONTERMINAL_FINAL_DSEG_NOT64, + XED_NONTERMINAL_FINAL_ESEG, + XED_NONTERMINAL_FINAL_ESEG1, + XED_NONTERMINAL_FINAL_SSEG, + XED_NONTERMINAL_FINAL_SSEG0, + XED_NONTERMINAL_FINAL_SSEG1, + XED_NONTERMINAL_FINAL_SSEG_MODE64, + XED_NONTERMINAL_FINAL_SSEG_NOT64, + XED_NONTERMINAL_FIX_ROUND_LEN128, + XED_NONTERMINAL_FIX_ROUND_LEN512, + XED_NONTERMINAL_FORCE64, + XED_NONTERMINAL_GPR16_B, + XED_NONTERMINAL_GPR16_R, + XED_NONTERMINAL_GPR16_SB, + XED_NONTERMINAL_GPR32_B, + XED_NONTERMINAL_GPR32_R, + XED_NONTERMINAL_GPR32_SB, + XED_NONTERMINAL_GPR32_X, + XED_NONTERMINAL_GPR64_B, + XED_NONTERMINAL_GPR64_R, + XED_NONTERMINAL_GPR64_SB, + XED_NONTERMINAL_GPR64_X, + XED_NONTERMINAL_GPR8_B, + XED_NONTERMINAL_GPR8_R, + XED_NONTERMINAL_GPR8_SB, + XED_NONTERMINAL_GPRV_B, + XED_NONTERMINAL_GPRV_R, + XED_NONTERMINAL_GPRV_SB, + XED_NONTERMINAL_GPRY_B, + XED_NONTERMINAL_GPRY_R, + XED_NONTERMINAL_GPRZ_B, + XED_NONTERMINAL_GPRZ_R, + XED_NONTERMINAL_IGNORE66, + XED_NONTERMINAL_IMMUNE66, + XED_NONTERMINAL_IMMUNE66_LOOP64, + XED_NONTERMINAL_IMMUNE_REXW, + XED_NONTERMINAL_INSTRUCTIONS, + XED_NONTERMINAL_ISA, + XED_NONTERMINAL_MASK1, + XED_NONTERMINAL_MASKNOT0, + XED_NONTERMINAL_MASK_B, + XED_NONTERMINAL_MASK_N, + XED_NONTERMINAL_MASK_N32, + XED_NONTERMINAL_MASK_N64, + XED_NONTERMINAL_MASK_R, + XED_NONTERMINAL_MEMDISP, + XED_NONTERMINAL_MEMDISP16, + XED_NONTERMINAL_MEMDISP32, + XED_NONTERMINAL_MEMDISP8, + XED_NONTERMINAL_MEMDISPV, + XED_NONTERMINAL_MMX_B, + XED_NONTERMINAL_MMX_R, + XED_NONTERMINAL_MODRM, + XED_NONTERMINAL_MODRM16, + XED_NONTERMINAL_MODRM32, + XED_NONTERMINAL_MODRM64ALT32, + XED_NONTERMINAL_NELEM_EIGHTHMEM, + XED_NONTERMINAL_NELEM_FULL, + XED_NONTERMINAL_NELEM_FULLMEM, + XED_NONTERMINAL_NELEM_GPR_READER, + XED_NONTERMINAL_NELEM_GPR_READER_BYTE, + XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD, + XED_NONTERMINAL_NELEM_GPR_READER_WORD, + XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP, + XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D, + XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD, + XED_NONTERMINAL_NELEM_GSCAT, + XED_NONTERMINAL_NELEM_HALF, + XED_NONTERMINAL_NELEM_HALFMEM, + XED_NONTERMINAL_NELEM_MEM128, + XED_NONTERMINAL_NELEM_MOVDDUP, + XED_NONTERMINAL_NELEM_QUARTER, + XED_NONTERMINAL_NELEM_QUARTERMEM, + XED_NONTERMINAL_NELEM_SCALAR, + XED_NONTERMINAL_NELEM_TUPLE1, + XED_NONTERMINAL_NELEM_TUPLE1_4X, + XED_NONTERMINAL_NELEM_TUPLE1_BYTE, + XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD, + XED_NONTERMINAL_NELEM_TUPLE1_WORD, + XED_NONTERMINAL_NELEM_TUPLE2, + XED_NONTERMINAL_NELEM_TUPLE4, + XED_NONTERMINAL_NELEM_TUPLE8, + XED_NONTERMINAL_OEAX, + XED_NONTERMINAL_ONE, + XED_NONTERMINAL_ORAX, + XED_NONTERMINAL_ORBP, + XED_NONTERMINAL_ORBX, + XED_NONTERMINAL_ORCX, + XED_NONTERMINAL_ORDX, + XED_NONTERMINAL_ORSP, + XED_NONTERMINAL_OSZ_NONTERM, + XED_NONTERMINAL_OVERRIDE_SEG0, + XED_NONTERMINAL_OVERRIDE_SEG1, + XED_NONTERMINAL_PREFIXES, + XED_NONTERMINAL_REFINING66, + XED_NONTERMINAL_REMOVE_SEGMENT, + XED_NONTERMINAL_RFLAGS, + XED_NONTERMINAL_RIP, + XED_NONTERMINAL_RIPA, + XED_NONTERMINAL_SAE, + XED_NONTERMINAL_SEG, + XED_NONTERMINAL_SEG_MOV, + XED_NONTERMINAL_SE_IMM8, + XED_NONTERMINAL_SIB, + XED_NONTERMINAL_SIB_BASE0, + XED_NONTERMINAL_SIMM8, + XED_NONTERMINAL_SIMMZ, + XED_NONTERMINAL_SRBP, + XED_NONTERMINAL_SRSP, + XED_NONTERMINAL_TMM_B, + XED_NONTERMINAL_TMM_N, + XED_NONTERMINAL_TMM_R, + XED_NONTERMINAL_UIMM16, + XED_NONTERMINAL_UIMM32, + XED_NONTERMINAL_UIMM8, + XED_NONTERMINAL_UIMM8_1, + XED_NONTERMINAL_UIMMV, + XED_NONTERMINAL_UISA_VMODRM_XMM, + XED_NONTERMINAL_UISA_VMODRM_YMM, + XED_NONTERMINAL_UISA_VMODRM_ZMM, + XED_NONTERMINAL_UISA_VSIB_BASE, + XED_NONTERMINAL_UISA_VSIB_INDEX_XMM, + XED_NONTERMINAL_UISA_VSIB_INDEX_YMM, + XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM, + XED_NONTERMINAL_UISA_VSIB_XMM, + XED_NONTERMINAL_UISA_VSIB_YMM, + XED_NONTERMINAL_UISA_VSIB_ZMM, + XED_NONTERMINAL_VGPR32_B, + XED_NONTERMINAL_VGPR32_B_32, + XED_NONTERMINAL_VGPR32_B_64, + XED_NONTERMINAL_VGPR32_N, + XED_NONTERMINAL_VGPR32_N_32, + XED_NONTERMINAL_VGPR32_N_64, + XED_NONTERMINAL_VGPR32_R, + XED_NONTERMINAL_VGPR32_R_32, + XED_NONTERMINAL_VGPR32_R_64, + XED_NONTERMINAL_VGPR64_B, + XED_NONTERMINAL_VGPR64_N, + XED_NONTERMINAL_VGPR64_R, + XED_NONTERMINAL_VGPRY_B, + XED_NONTERMINAL_VGPRY_N, + XED_NONTERMINAL_VGPRY_R, + XED_NONTERMINAL_VMODRM_XMM, + XED_NONTERMINAL_VMODRM_YMM, + XED_NONTERMINAL_VSIB_BASE, + XED_NONTERMINAL_VSIB_INDEX_XMM, + XED_NONTERMINAL_VSIB_INDEX_YMM, + XED_NONTERMINAL_VSIB_XMM, + XED_NONTERMINAL_VSIB_YMM, + XED_NONTERMINAL_X87, + XED_NONTERMINAL_XMM_B, + XED_NONTERMINAL_XMM_B3, + XED_NONTERMINAL_XMM_B3_32, + XED_NONTERMINAL_XMM_B3_64, + XED_NONTERMINAL_XMM_B_32, + XED_NONTERMINAL_XMM_B_64, + XED_NONTERMINAL_XMM_N, + XED_NONTERMINAL_XMM_N3, + XED_NONTERMINAL_XMM_N3_32, + XED_NONTERMINAL_XMM_N3_64, + XED_NONTERMINAL_XMM_N_32, + XED_NONTERMINAL_XMM_N_64, + XED_NONTERMINAL_XMM_R, + XED_NONTERMINAL_XMM_R3, + XED_NONTERMINAL_XMM_R3_32, + XED_NONTERMINAL_XMM_R3_64, + XED_NONTERMINAL_XMM_R_32, + XED_NONTERMINAL_XMM_R_64, + XED_NONTERMINAL_XMM_SE, + XED_NONTERMINAL_XMM_SE32, + XED_NONTERMINAL_XMM_SE64, + XED_NONTERMINAL_XOP_INSTRUCTIONS, + XED_NONTERMINAL_YMM_B, + XED_NONTERMINAL_YMM_B3, + XED_NONTERMINAL_YMM_B3_32, + XED_NONTERMINAL_YMM_B3_64, + XED_NONTERMINAL_YMM_B_32, + XED_NONTERMINAL_YMM_B_64, + XED_NONTERMINAL_YMM_N, + XED_NONTERMINAL_YMM_N3, + XED_NONTERMINAL_YMM_N3_32, + XED_NONTERMINAL_YMM_N3_64, + XED_NONTERMINAL_YMM_N_32, + XED_NONTERMINAL_YMM_N_64, + XED_NONTERMINAL_YMM_R, + XED_NONTERMINAL_YMM_R3, + XED_NONTERMINAL_YMM_R3_32, + XED_NONTERMINAL_YMM_R3_64, + XED_NONTERMINAL_YMM_R_32, + XED_NONTERMINAL_YMM_R_64, + XED_NONTERMINAL_YMM_SE, + XED_NONTERMINAL_YMM_SE32, + XED_NONTERMINAL_YMM_SE64, + XED_NONTERMINAL_ZMM_B3, + XED_NONTERMINAL_ZMM_B3_32, + XED_NONTERMINAL_ZMM_B3_64, + XED_NONTERMINAL_ZMM_N3, + XED_NONTERMINAL_ZMM_N3_32, + XED_NONTERMINAL_ZMM_N3_64, + XED_NONTERMINAL_ZMM_R3, + XED_NONTERMINAL_ZMM_R3_32, + XED_NONTERMINAL_ZMM_R3_64, + XED_NONTERMINAL_LAST +} xed_nonterminal_enum_t; + +/// This converts strings to #xed_nonterminal_enum_t types. +/// @param s A C-string. +/// @return #xed_nonterminal_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_nonterminal_enum_t str2xed_nonterminal_enum_t(const char* s); +/// This converts strings to #xed_nonterminal_enum_t types. +/// @param p An enumeration element of type xed_nonterminal_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_nonterminal_enum_t2str(const xed_nonterminal_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_nonterminal_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_nonterminal_enum_t xed_nonterminal_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-accessors.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-accessors.h new file mode 100644 index 0000000..06eab37 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-accessors.h @@ -0,0 +1,1543 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-accessors.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ACCESSORS_H) +# define XED_OPERAND_ACCESSORS_H +#include "xed-decoded-inst.h" +#include "xed-operand-storage.h" +static XED_INLINE xed_bits_t xed3_operand_get_seg_ovd(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_seg_ovd(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_hint(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_hint(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_encode_force(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_encode_force(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_lock(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_lock(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_need_memdisp(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_need_memdisp(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_int64_t xed3_operand_get_disp(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_disp(xed_decoded_inst_t* d, xed_int64_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_disp_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_disp_width(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_brdisp_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_brdisp_width(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_df32(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_df32(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_df64(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_df64(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_norex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_norex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_needrex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_needrex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexw(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexw(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexx(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexx(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexb(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexb(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rep(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rep(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_osz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_osz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_prefix66(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_prefix66(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_asz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_asz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_eosz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_eosz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_easz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_easz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mod(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mod(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_reg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_srm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_srm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_realmode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_realmode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_chip_enum_t xed3_operand_get_chip(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_chip(xed_decoded_inst_t* d, xed_chip_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_smode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_smode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_modep5(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_modep5(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_modep55c(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_modep55c(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_p4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_p4(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_lzcnt(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_lzcnt(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_tzcnt(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_tzcnt(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mode_first_prefix(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mode_first_prefix(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mode_short_ud0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mode_short_ud0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm0signed(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm0signed(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_uint64_t xed3_operand_get_uimm0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_uimm0(xed_decoded_inst_t* d, xed_uint64_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_uimm1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_uimm1(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_imm_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm_width(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_using_default_segment0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_using_default_segment1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_default_seg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_default_seg(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_seg0(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_base0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_base0(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_index(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_index(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_scale(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_scale(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_need_sib(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_need_sib(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sibscale(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sibscale(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sibbase(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sibbase(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sibindex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sibindex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_seg1(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_base1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_base1(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mem0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mem0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mem1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mem1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_uint16_t xed3_operand_get_mem_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mem_width(xed_decoded_inst_t* d, xed_uint16_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_agen(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_agen(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_relbr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_relbr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ptr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ptr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg0(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg1(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg2(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg2(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg3(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg4(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg5(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg5(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg6(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg6(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg7(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg7(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg8(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg8(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg9(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg9(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_outreg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_outreg(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_encoder_preferred(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_encoder_preferred(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_error_enum_t xed3_operand_get_error(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_error(xed_decoded_inst_t* d, xed_error_enum_t opval); + +static XED_INLINE xed_iclass_enum_t xed3_operand_get_iclass(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_iclass(xed_decoded_inst_t* d, xed_iclass_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nelem(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nelem(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_element_size(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_element_size(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_map(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_map(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_out_of_bytes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_out_of_bytes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_first_f2f3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_first_f2f3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_last_f2f3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_last_f2f3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ild_f2(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ild_f2(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ild_f3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ild_f3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_max_bytes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_max_bytes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ild_seg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ild_seg(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nseg_prefixes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nseg_prefixes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nrexes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nrexes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nprefixes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nprefixes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nominal_opcode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_nominal_opcode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_has_modrm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_has_modrm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_has_sib(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_has_sib(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_modrm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_modrm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_sib(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_sib(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_disp(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_disp(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_imm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_imm1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm1_bytes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm1_bytes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_modrm_byte(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_modrm_byte(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_esrc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_esrc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexvalid(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexvalid(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_dummy(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_dummy(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_amd3dnow(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_amd3dnow(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mpxmode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mpxmode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_cet(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_cet(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_cldemote(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_cldemote(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexdest3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexdest3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexdest210(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexdest210(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vl(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vl(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vex_prefix(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vex_prefix(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vex_c4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vex_c4(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_bcast(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_bcast(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_must_use_evex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_must_use_evex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_zeroing(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_zeroing(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_llrc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_llrc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_bcrc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_bcrc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexrr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexrr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexdest4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexdest4(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mask(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mask(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_roundc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_roundc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sae(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sae(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_no_scale_disp8(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_no_scale_disp8(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ubit(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ubit(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_wbnoinvd(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_wbnoinvd(xed_decoded_inst_t* d, xed_bits_t opval); + +XED_DLL_EXPORT void xed3_get_generic_operand(const xed_decoded_inst_t* d, xed_operand_enum_t operand, void* ret_arg); + +XED_DLL_EXPORT void xed3_set_generic_operand(xed_decoded_inst_t* d, xed_operand_enum_t operand, xed_uint32_t val); + +static XED_INLINE xed_bits_t xed3_operand_get_seg_ovd(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.seg_ovd; +} +static XED_INLINE void xed3_operand_set_seg_ovd(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.seg_ovd = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_hint(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.hint; +} +static XED_INLINE void xed3_operand_set_hint(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.hint = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_encode_force(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.encode_force; +} +static XED_INLINE void xed3_operand_set_encode_force(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.encode_force = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_lock(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.lock; +} +static XED_INLINE void xed3_operand_set_lock(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.lock = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_need_memdisp(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.need_memdisp; +} +static XED_INLINE void xed3_operand_set_need_memdisp(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.need_memdisp = (xed_uint8_t)opval; +} +static XED_INLINE xed_int64_t xed3_operand_get_disp(const xed_decoded_inst_t* d) +{ +return (xed_int64_t)d->_operands.disp; +} +static XED_INLINE void xed3_operand_set_disp(xed_decoded_inst_t* d, xed_int64_t opval) +{ +d->_operands.disp = (xed_uint64_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_disp_width(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.disp_width; +} +static XED_INLINE void xed3_operand_set_disp_width(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.disp_width = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_brdisp_width(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.brdisp_width; +} +static XED_INLINE void xed3_operand_set_brdisp_width(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.brdisp_width = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_df32(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.df32; +} +static XED_INLINE void xed3_operand_set_df32(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.df32 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_df64(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.df64; +} +static XED_INLINE void xed3_operand_set_df64(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.df64 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_norex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.norex; +} +static XED_INLINE void xed3_operand_set_norex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.norex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_needrex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.needrex; +} +static XED_INLINE void xed3_operand_set_needrex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.needrex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rex; +} +static XED_INLINE void xed3_operand_set_rex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexw(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexw; +} +static XED_INLINE void xed3_operand_set_rexw(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexw = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexr; +} +static XED_INLINE void xed3_operand_set_rexr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexr = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexx(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexx; +} +static XED_INLINE void xed3_operand_set_rexx(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexx = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexb(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexb; +} +static XED_INLINE void xed3_operand_set_rexb(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexb = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rep(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rep; +} +static XED_INLINE void xed3_operand_set_rep(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rep = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_osz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.osz; +} +static XED_INLINE void xed3_operand_set_osz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.osz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_prefix66(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.prefix66; +} +static XED_INLINE void xed3_operand_set_prefix66(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.prefix66 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_asz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.asz; +} +static XED_INLINE void xed3_operand_set_asz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.asz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_eosz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.eosz; +} +static XED_INLINE void xed3_operand_set_eosz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.eosz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_easz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.easz; +} +static XED_INLINE void xed3_operand_set_easz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.easz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mod(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mod; +} +static XED_INLINE void xed3_operand_set_mod(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mod = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_reg(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.reg; +} +static XED_INLINE void xed3_operand_set_reg(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.reg = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_srm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.srm; +} +static XED_INLINE void xed3_operand_set_srm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.srm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rm; +} +static XED_INLINE void xed3_operand_set_rm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_realmode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.realmode; +} +static XED_INLINE void xed3_operand_set_realmode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.realmode = (xed_uint8_t)opval; +} +static XED_INLINE xed_chip_enum_t xed3_operand_get_chip(const xed_decoded_inst_t* d) +{ +return (xed_chip_enum_t)d->_operands.chip; +} +static XED_INLINE void xed3_operand_set_chip(xed_decoded_inst_t* d, xed_chip_enum_t opval) +{ +d->_operands.chip = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mode; +} +static XED_INLINE void xed3_operand_set_mode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_smode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.smode; +} +static XED_INLINE void xed3_operand_set_smode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.smode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_modep5(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.modep5; +} +static XED_INLINE void xed3_operand_set_modep5(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.modep5 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_modep55c(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.modep55c; +} +static XED_INLINE void xed3_operand_set_modep55c(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.modep55c = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_p4(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.p4; +} +static XED_INLINE void xed3_operand_set_p4(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.p4 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_lzcnt(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.lzcnt; +} +static XED_INLINE void xed3_operand_set_lzcnt(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.lzcnt = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_tzcnt(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.tzcnt; +} +static XED_INLINE void xed3_operand_set_tzcnt(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.tzcnt = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mode_first_prefix(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mode_first_prefix; +} +static XED_INLINE void xed3_operand_set_mode_first_prefix(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mode_first_prefix = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mode_short_ud0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mode_short_ud0; +} +static XED_INLINE void xed3_operand_set_mode_short_ud0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mode_short_ud0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm0; +} +static XED_INLINE void xed3_operand_set_imm0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm1; +} +static XED_INLINE void xed3_operand_set_imm1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm0signed(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm0signed; +} +static XED_INLINE void xed3_operand_set_imm0signed(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm0signed = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint64_t xed3_operand_get_uimm0(const xed_decoded_inst_t* d) +{ +return (xed_uint64_t)d->_operands.uimm0; +} +static XED_INLINE void xed3_operand_set_uimm0(xed_decoded_inst_t* d, xed_uint64_t opval) +{ +d->_operands.uimm0 = (xed_uint64_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_uimm1(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.uimm1; +} +static XED_INLINE void xed3_operand_set_uimm1(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.uimm1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_imm_width(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.imm_width; +} +static XED_INLINE void xed3_operand_set_imm_width(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.imm_width = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.using_default_segment0; +} +static XED_INLINE void xed3_operand_set_using_default_segment0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.using_default_segment0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.using_default_segment1; +} +static XED_INLINE void xed3_operand_set_using_default_segment1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.using_default_segment1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_default_seg(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.default_seg; +} +static XED_INLINE void xed3_operand_set_default_seg(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.default_seg = (xed_uint8_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg0(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.seg0; +} +static XED_INLINE void xed3_operand_set_seg0(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.seg0 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_base0(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.base0; +} +static XED_INLINE void xed3_operand_set_base0(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.base0 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_index(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.index; +} +static XED_INLINE void xed3_operand_set_index(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.index = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_scale(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.scale; +} +static XED_INLINE void xed3_operand_set_scale(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.scale = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_need_sib(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.need_sib; +} +static XED_INLINE void xed3_operand_set_need_sib(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.need_sib = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sibscale(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sibscale; +} +static XED_INLINE void xed3_operand_set_sibscale(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sibscale = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sibbase(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sibbase; +} +static XED_INLINE void xed3_operand_set_sibbase(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sibbase = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sibindex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sibindex; +} +static XED_INLINE void xed3_operand_set_sibindex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sibindex = (xed_uint8_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg1(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.seg1; +} +static XED_INLINE void xed3_operand_set_seg1(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.seg1 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_base1(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.base1; +} +static XED_INLINE void xed3_operand_set_base1(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.base1 = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mem0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mem0; +} +static XED_INLINE void xed3_operand_set_mem0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mem0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mem1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mem1; +} +static XED_INLINE void xed3_operand_set_mem1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mem1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint16_t xed3_operand_get_mem_width(const xed_decoded_inst_t* d) +{ +return (xed_uint16_t)d->_operands.mem_width; +} +static XED_INLINE void xed3_operand_set_mem_width(xed_decoded_inst_t* d, xed_uint16_t opval) +{ +d->_operands.mem_width = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_agen(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.agen; +} +static XED_INLINE void xed3_operand_set_agen(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.agen = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_relbr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.relbr; +} +static XED_INLINE void xed3_operand_set_relbr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.relbr = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ptr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ptr; +} +static XED_INLINE void xed3_operand_set_ptr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ptr = (xed_uint8_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg0(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg0; +} +static XED_INLINE void xed3_operand_set_reg0(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg0 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg1(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg1; +} +static XED_INLINE void xed3_operand_set_reg1(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg1 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg2(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg2; +} +static XED_INLINE void xed3_operand_set_reg2(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg2 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg3(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg3; +} +static XED_INLINE void xed3_operand_set_reg3(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg3 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg4(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg4; +} +static XED_INLINE void xed3_operand_set_reg4(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg4 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg5(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg5; +} +static XED_INLINE void xed3_operand_set_reg5(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg5 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg6(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg6; +} +static XED_INLINE void xed3_operand_set_reg6(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg6 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg7(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg7; +} +static XED_INLINE void xed3_operand_set_reg7(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg7 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg8(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg8; +} +static XED_INLINE void xed3_operand_set_reg8(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg8 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg9(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg9; +} +static XED_INLINE void xed3_operand_set_reg9(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg9 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_outreg(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.outreg; +} +static XED_INLINE void xed3_operand_set_outreg(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.outreg = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_encoder_preferred(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.encoder_preferred; +} +static XED_INLINE void xed3_operand_set_encoder_preferred(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.encoder_preferred = (xed_uint8_t)opval; +} +static XED_INLINE xed_error_enum_t xed3_operand_get_error(const xed_decoded_inst_t* d) +{ +return (xed_error_enum_t)d->_operands.error; +} +static XED_INLINE void xed3_operand_set_error(xed_decoded_inst_t* d, xed_error_enum_t opval) +{ +d->_operands.error = (xed_uint8_t)opval; +} +static XED_INLINE xed_iclass_enum_t xed3_operand_get_iclass(const xed_decoded_inst_t* d) +{ +return (xed_iclass_enum_t)d->_operands.iclass; +} +static XED_INLINE void xed3_operand_set_iclass(xed_decoded_inst_t* d, xed_iclass_enum_t opval) +{ +d->_operands.iclass = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nelem(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nelem; +} +static XED_INLINE void xed3_operand_set_nelem(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nelem = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_element_size(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.element_size; +} +static XED_INLINE void xed3_operand_set_element_size(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.element_size = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_map(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.map; +} +static XED_INLINE void xed3_operand_set_map(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.map = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_out_of_bytes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.out_of_bytes; +} +static XED_INLINE void xed3_operand_set_out_of_bytes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.out_of_bytes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_first_f2f3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.first_f2f3; +} +static XED_INLINE void xed3_operand_set_first_f2f3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.first_f2f3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_last_f2f3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.last_f2f3; +} +static XED_INLINE void xed3_operand_set_last_f2f3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.last_f2f3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ild_f2(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ild_f2; +} +static XED_INLINE void xed3_operand_set_ild_f2(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ild_f2 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ild_f3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ild_f3; +} +static XED_INLINE void xed3_operand_set_ild_f3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ild_f3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_max_bytes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.max_bytes; +} +static XED_INLINE void xed3_operand_set_max_bytes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.max_bytes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ild_seg(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ild_seg; +} +static XED_INLINE void xed3_operand_set_ild_seg(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ild_seg = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nseg_prefixes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nseg_prefixes; +} +static XED_INLINE void xed3_operand_set_nseg_prefixes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nseg_prefixes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nrexes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nrexes; +} +static XED_INLINE void xed3_operand_set_nrexes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nrexes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nprefixes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nprefixes; +} +static XED_INLINE void xed3_operand_set_nprefixes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nprefixes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nominal_opcode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nominal_opcode; +} +static XED_INLINE void xed3_operand_set_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nominal_opcode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_nominal_opcode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_nominal_opcode; +} +static XED_INLINE void xed3_operand_set_pos_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_nominal_opcode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_has_modrm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.has_modrm; +} +static XED_INLINE void xed3_operand_set_has_modrm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.has_modrm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_has_sib(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.has_sib; +} +static XED_INLINE void xed3_operand_set_has_sib(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.has_sib = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_modrm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_modrm; +} +static XED_INLINE void xed3_operand_set_pos_modrm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_modrm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_sib(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_sib; +} +static XED_INLINE void xed3_operand_set_pos_sib(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_sib = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_disp(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_disp; +} +static XED_INLINE void xed3_operand_set_pos_disp(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_disp = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_imm; +} +static XED_INLINE void xed3_operand_set_pos_imm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_imm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_imm1; +} +static XED_INLINE void xed3_operand_set_pos_imm1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_imm1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm1_bytes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm1_bytes; +} +static XED_INLINE void xed3_operand_set_imm1_bytes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm1_bytes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_modrm_byte(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.modrm_byte; +} +static XED_INLINE void xed3_operand_set_modrm_byte(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.modrm_byte = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_esrc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.esrc; +} +static XED_INLINE void xed3_operand_set_esrc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.esrc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexvalid(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexvalid; +} +static XED_INLINE void xed3_operand_set_vexvalid(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexvalid = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_dummy(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.dummy; +} +static XED_INLINE void xed3_operand_set_dummy(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.dummy = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_amd3dnow(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.amd3dnow; +} +static XED_INLINE void xed3_operand_set_amd3dnow(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.amd3dnow = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mpxmode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mpxmode; +} +static XED_INLINE void xed3_operand_set_mpxmode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mpxmode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_cet(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.cet; +} +static XED_INLINE void xed3_operand_set_cet(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.cet = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_cldemote(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.cldemote; +} +static XED_INLINE void xed3_operand_set_cldemote(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.cldemote = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexdest3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexdest3; +} +static XED_INLINE void xed3_operand_set_vexdest3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexdest3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexdest210(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexdest210; +} +static XED_INLINE void xed3_operand_set_vexdest210(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexdest210 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vl(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vl; +} +static XED_INLINE void xed3_operand_set_vl(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vl = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vex_prefix(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vex_prefix; +} +static XED_INLINE void xed3_operand_set_vex_prefix(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vex_prefix = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vex_c4(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vex_c4; +} +static XED_INLINE void xed3_operand_set_vex_c4(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vex_c4 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_bcast(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.bcast; +} +static XED_INLINE void xed3_operand_set_bcast(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.bcast = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_must_use_evex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.must_use_evex; +} +static XED_INLINE void xed3_operand_set_must_use_evex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.must_use_evex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_zeroing(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.zeroing; +} +static XED_INLINE void xed3_operand_set_zeroing(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.zeroing = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_llrc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.llrc; +} +static XED_INLINE void xed3_operand_set_llrc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.llrc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_bcrc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.bcrc; +} +static XED_INLINE void xed3_operand_set_bcrc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.bcrc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexrr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexrr; +} +static XED_INLINE void xed3_operand_set_rexrr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexrr = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexdest4(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexdest4; +} +static XED_INLINE void xed3_operand_set_vexdest4(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexdest4 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mask(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mask; +} +static XED_INLINE void xed3_operand_set_mask(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mask = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_roundc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.roundc; +} +static XED_INLINE void xed3_operand_set_roundc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.roundc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sae(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sae; +} +static XED_INLINE void xed3_operand_set_sae(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sae = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_no_scale_disp8(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.no_scale_disp8; +} +static XED_INLINE void xed3_operand_set_no_scale_disp8(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.no_scale_disp8 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ubit(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ubit; +} +static XED_INLINE void xed3_operand_set_ubit(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ubit = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_wbnoinvd(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.wbnoinvd; +} +static XED_INLINE void xed3_operand_set_wbnoinvd(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.wbnoinvd = (xed_uint8_t)opval; +} +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-action-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-action-enum.h new file mode 100644 index 0000000..9013ae8 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-action-enum.h @@ -0,0 +1,62 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-action-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ACTION_ENUM_H) +# define XED_OPERAND_ACTION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_ACTION_INVALID_DEFINED 1 +#define XED_OPERAND_ACTION_RW_DEFINED 1 +#define XED_OPERAND_ACTION_R_DEFINED 1 +#define XED_OPERAND_ACTION_W_DEFINED 1 +#define XED_OPERAND_ACTION_RCW_DEFINED 1 +#define XED_OPERAND_ACTION_CW_DEFINED 1 +#define XED_OPERAND_ACTION_CRW_DEFINED 1 +#define XED_OPERAND_ACTION_CR_DEFINED 1 +#define XED_OPERAND_ACTION_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_ACTION_INVALID, + XED_OPERAND_ACTION_RW, ///< Read and written (must write) + XED_OPERAND_ACTION_R, ///< Read-only + XED_OPERAND_ACTION_W, ///< Write-only (must write) + XED_OPERAND_ACTION_RCW, ///< Read and conditionlly written (may write) + XED_OPERAND_ACTION_CW, ///< Conditionlly written (may write) + XED_OPERAND_ACTION_CRW, ///< Conditionlly read, always written (must write) + XED_OPERAND_ACTION_CR, ///< Conditional read + XED_OPERAND_ACTION_LAST +} xed_operand_action_enum_t; + +/// This converts strings to #xed_operand_action_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_action_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_action_enum_t str2xed_operand_action_enum_t(const char* s); +/// This converts strings to #xed_operand_action_enum_t types. +/// @param p An enumeration element of type xed_operand_action_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_action_enum_t2str(const xed_operand_action_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_action_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_action_enum_t xed_operand_action_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-action.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-action.h new file mode 100644 index 0000000..4c90be8 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-action.h @@ -0,0 +1,36 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-action.h +/// + +#if !defined(XED_OPERAND_ACTION_H) +# define XED_OPERAND_ACTION_H + +#include "xed-types.h" +#include "xed-operand-action-enum.h" + +XED_DLL_EXPORT xed_uint_t xed_operand_action_read(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_read_only(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_written(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_written_only(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_read_and_written(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_conditional_read(const xed_operand_action_enum_t rw); +XED_DLL_EXPORT xed_uint_t xed_operand_action_conditional_write(const xed_operand_action_enum_t rw); + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-convert-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-convert-enum.h new file mode 100644 index 0000000..4426a21 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-convert-enum.h @@ -0,0 +1,56 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-convert-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_CONVERT_ENUM_H) +# define XED_OPERAND_CONVERT_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_CONVERT_INVALID_DEFINED 1 +#define XED_OPERAND_CONVERT_ZEROSTR_DEFINED 1 +#define XED_OPERAND_CONVERT_SAESTR_DEFINED 1 +#define XED_OPERAND_CONVERT_ROUNDC_DEFINED 1 +#define XED_OPERAND_CONVERT_BCASTSTR_DEFINED 1 +#define XED_OPERAND_CONVERT_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_CONVERT_INVALID, + XED_OPERAND_CONVERT_ZEROSTR, + XED_OPERAND_CONVERT_SAESTR, + XED_OPERAND_CONVERT_ROUNDC, + XED_OPERAND_CONVERT_BCASTSTR, + XED_OPERAND_CONVERT_LAST +} xed_operand_convert_enum_t; + +/// This converts strings to #xed_operand_convert_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_convert_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_convert_enum_t str2xed_operand_convert_enum_t(const char* s); +/// This converts strings to #xed_operand_convert_enum_t types. +/// @param p An enumeration element of type xed_operand_convert_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_convert_enum_t2str(const xed_operand_convert_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_convert_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_convert_enum_t xed_operand_convert_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-ctype-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-ctype-enum.h new file mode 100644 index 0000000..023ec55 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-ctype-enum.h @@ -0,0 +1,66 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-ctype-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_CTYPE_ENUM_H) +# define XED_OPERAND_CTYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_CTYPE_INVALID_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_BITS_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_CHIP_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_ERROR_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_INT64_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_REG_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_UINT16_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_UINT64_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_UINT8_T_DEFINED 1 +#define XED_OPERAND_CTYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_CTYPE_INVALID, + XED_OPERAND_CTYPE_XED_BITS_T, + XED_OPERAND_CTYPE_XED_CHIP_ENUM_T, + XED_OPERAND_CTYPE_XED_ERROR_ENUM_T, + XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T, + XED_OPERAND_CTYPE_XED_INT64_T, + XED_OPERAND_CTYPE_XED_REG_ENUM_T, + XED_OPERAND_CTYPE_XED_UINT16_T, + XED_OPERAND_CTYPE_XED_UINT64_T, + XED_OPERAND_CTYPE_XED_UINT8_T, + XED_OPERAND_CTYPE_LAST +} xed_operand_ctype_enum_t; + +/// This converts strings to #xed_operand_ctype_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_ctype_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_ctype_enum_t str2xed_operand_ctype_enum_t(const char* s); +/// This converts strings to #xed_operand_ctype_enum_t types. +/// @param p An enumeration element of type xed_operand_ctype_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_ctype_enum_t2str(const xed_operand_ctype_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_ctype_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_ctype_enum_t xed_operand_ctype_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-ctype-map.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-ctype-map.h new file mode 100644 index 0000000..13fe38b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-ctype-map.h @@ -0,0 +1,28 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-ctype-map.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_CTYPE_MAP_H) +# define XED_OPERAND_CTYPE_MAP_H +#include "xed-internal-header.h" +xed_operand_ctype_enum_t xed_operand_get_ctype(xed_operand_enum_t opname); +unsigned int xed_operand_decider_get_width(xed_operand_enum_t opname); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-element-type-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-element-type-enum.h new file mode 100644 index 0000000..8d321a1 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-element-type-enum.h @@ -0,0 +1,68 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-element-type-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ELEMENT_TYPE_ENUM_H) +# define XED_OPERAND_ELEMENT_TYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_ELEMENT_TYPE_INVALID_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_UINT_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_INT_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_SINGLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_DOUBLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_LONGBCD_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_STRUCT_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_VARIABLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_FLOAT16_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_BFLOAT16_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_ELEMENT_TYPE_INVALID, + XED_OPERAND_ELEMENT_TYPE_UINT, ///< Unsigned integer + XED_OPERAND_ELEMENT_TYPE_INT, ///< Signed integer + XED_OPERAND_ELEMENT_TYPE_SINGLE, ///< 32b FP single precision + XED_OPERAND_ELEMENT_TYPE_DOUBLE, ///< 64b FP double precision + XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE, ///< 80b FP x87 + XED_OPERAND_ELEMENT_TYPE_LONGBCD, ///< 80b decimal BCD + XED_OPERAND_ELEMENT_TYPE_STRUCT, ///< a structure of various fields + XED_OPERAND_ELEMENT_TYPE_VARIABLE, ///< depends on other fields in the instruction + XED_OPERAND_ELEMENT_TYPE_FLOAT16, ///< 16b floating point + XED_OPERAND_ELEMENT_TYPE_BFLOAT16, ///< bfloat16 floating point + XED_OPERAND_ELEMENT_TYPE_LAST +} xed_operand_element_type_enum_t; + +/// This converts strings to #xed_operand_element_type_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_element_type_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_type_enum_t str2xed_operand_element_type_enum_t(const char* s); +/// This converts strings to #xed_operand_element_type_enum_t types. +/// @param p An enumeration element of type xed_operand_element_type_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_element_type_enum_t2str(const xed_operand_element_type_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_element_type_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_type_enum_t xed_operand_element_type_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-element-xtype-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-element-xtype-enum.h new file mode 100644 index 0000000..1de7431 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-element-xtype-enum.h @@ -0,0 +1,92 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-element-xtype-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ELEMENT_XTYPE_ENUM_H) +# define XED_OPERAND_ELEMENT_XTYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_XTYPE_INVALID_DEFINED 1 +#define XED_OPERAND_XTYPE_2F16_DEFINED 1 +#define XED_OPERAND_XTYPE_B80_DEFINED 1 +#define XED_OPERAND_XTYPE_BF16_DEFINED 1 +#define XED_OPERAND_XTYPE_F16_DEFINED 1 +#define XED_OPERAND_XTYPE_F32_DEFINED 1 +#define XED_OPERAND_XTYPE_F64_DEFINED 1 +#define XED_OPERAND_XTYPE_F80_DEFINED 1 +#define XED_OPERAND_XTYPE_I1_DEFINED 1 +#define XED_OPERAND_XTYPE_I16_DEFINED 1 +#define XED_OPERAND_XTYPE_I32_DEFINED 1 +#define XED_OPERAND_XTYPE_I64_DEFINED 1 +#define XED_OPERAND_XTYPE_I8_DEFINED 1 +#define XED_OPERAND_XTYPE_INT_DEFINED 1 +#define XED_OPERAND_XTYPE_STRUCT_DEFINED 1 +#define XED_OPERAND_XTYPE_U128_DEFINED 1 +#define XED_OPERAND_XTYPE_U16_DEFINED 1 +#define XED_OPERAND_XTYPE_U256_DEFINED 1 +#define XED_OPERAND_XTYPE_U32_DEFINED 1 +#define XED_OPERAND_XTYPE_U64_DEFINED 1 +#define XED_OPERAND_XTYPE_U8_DEFINED 1 +#define XED_OPERAND_XTYPE_UINT_DEFINED 1 +#define XED_OPERAND_XTYPE_VAR_DEFINED 1 +#define XED_OPERAND_XTYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_XTYPE_INVALID, + XED_OPERAND_XTYPE_2F16, + XED_OPERAND_XTYPE_B80, + XED_OPERAND_XTYPE_BF16, + XED_OPERAND_XTYPE_F16, + XED_OPERAND_XTYPE_F32, + XED_OPERAND_XTYPE_F64, + XED_OPERAND_XTYPE_F80, + XED_OPERAND_XTYPE_I1, + XED_OPERAND_XTYPE_I16, + XED_OPERAND_XTYPE_I32, + XED_OPERAND_XTYPE_I64, + XED_OPERAND_XTYPE_I8, + XED_OPERAND_XTYPE_INT, + XED_OPERAND_XTYPE_STRUCT, + XED_OPERAND_XTYPE_U128, + XED_OPERAND_XTYPE_U16, + XED_OPERAND_XTYPE_U256, + XED_OPERAND_XTYPE_U32, + XED_OPERAND_XTYPE_U64, + XED_OPERAND_XTYPE_U8, + XED_OPERAND_XTYPE_UINT, + XED_OPERAND_XTYPE_VAR, + XED_OPERAND_XTYPE_LAST +} xed_operand_element_xtype_enum_t; + +/// This converts strings to #xed_operand_element_xtype_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_element_xtype_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_xtype_enum_t str2xed_operand_element_xtype_enum_t(const char* s); +/// This converts strings to #xed_operand_element_xtype_enum_t types. +/// @param p An enumeration element of type xed_operand_element_xtype_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_element_xtype_enum_t2str(const xed_operand_element_xtype_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_element_xtype_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_xtype_enum_t xed_operand_element_xtype_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-enum.h new file mode 100644 index 0000000..c442ec8 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-enum.h @@ -0,0 +1,300 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ENUM_H) +# define XED_OPERAND_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_INVALID_DEFINED 1 +#define XED_OPERAND_AGEN_DEFINED 1 +#define XED_OPERAND_AMD3DNOW_DEFINED 1 +#define XED_OPERAND_ASZ_DEFINED 1 +#define XED_OPERAND_BASE0_DEFINED 1 +#define XED_OPERAND_BASE1_DEFINED 1 +#define XED_OPERAND_BCAST_DEFINED 1 +#define XED_OPERAND_BCRC_DEFINED 1 +#define XED_OPERAND_BRDISP_WIDTH_DEFINED 1 +#define XED_OPERAND_CET_DEFINED 1 +#define XED_OPERAND_CHIP_DEFINED 1 +#define XED_OPERAND_CLDEMOTE_DEFINED 1 +#define XED_OPERAND_DEFAULT_SEG_DEFINED 1 +#define XED_OPERAND_DF32_DEFINED 1 +#define XED_OPERAND_DF64_DEFINED 1 +#define XED_OPERAND_DISP_DEFINED 1 +#define XED_OPERAND_DISP_WIDTH_DEFINED 1 +#define XED_OPERAND_DUMMY_DEFINED 1 +#define XED_OPERAND_EASZ_DEFINED 1 +#define XED_OPERAND_ELEMENT_SIZE_DEFINED 1 +#define XED_OPERAND_ENCODER_PREFERRED_DEFINED 1 +#define XED_OPERAND_ENCODE_FORCE_DEFINED 1 +#define XED_OPERAND_EOSZ_DEFINED 1 +#define XED_OPERAND_ERROR_DEFINED 1 +#define XED_OPERAND_ESRC_DEFINED 1 +#define XED_OPERAND_FIRST_F2F3_DEFINED 1 +#define XED_OPERAND_HAS_MODRM_DEFINED 1 +#define XED_OPERAND_HAS_SIB_DEFINED 1 +#define XED_OPERAND_HINT_DEFINED 1 +#define XED_OPERAND_ICLASS_DEFINED 1 +#define XED_OPERAND_ILD_F2_DEFINED 1 +#define XED_OPERAND_ILD_F3_DEFINED 1 +#define XED_OPERAND_ILD_SEG_DEFINED 1 +#define XED_OPERAND_IMM0_DEFINED 1 +#define XED_OPERAND_IMM0SIGNED_DEFINED 1 +#define XED_OPERAND_IMM1_DEFINED 1 +#define XED_OPERAND_IMM1_BYTES_DEFINED 1 +#define XED_OPERAND_IMM_WIDTH_DEFINED 1 +#define XED_OPERAND_INDEX_DEFINED 1 +#define XED_OPERAND_LAST_F2F3_DEFINED 1 +#define XED_OPERAND_LLRC_DEFINED 1 +#define XED_OPERAND_LOCK_DEFINED 1 +#define XED_OPERAND_LZCNT_DEFINED 1 +#define XED_OPERAND_MAP_DEFINED 1 +#define XED_OPERAND_MASK_DEFINED 1 +#define XED_OPERAND_MAX_BYTES_DEFINED 1 +#define XED_OPERAND_MEM0_DEFINED 1 +#define XED_OPERAND_MEM1_DEFINED 1 +#define XED_OPERAND_MEM_WIDTH_DEFINED 1 +#define XED_OPERAND_MOD_DEFINED 1 +#define XED_OPERAND_MODE_DEFINED 1 +#define XED_OPERAND_MODEP5_DEFINED 1 +#define XED_OPERAND_MODEP55C_DEFINED 1 +#define XED_OPERAND_MODE_FIRST_PREFIX_DEFINED 1 +#define XED_OPERAND_MODE_SHORT_UD0_DEFINED 1 +#define XED_OPERAND_MODRM_BYTE_DEFINED 1 +#define XED_OPERAND_MPXMODE_DEFINED 1 +#define XED_OPERAND_MUST_USE_EVEX_DEFINED 1 +#define XED_OPERAND_NEEDREX_DEFINED 1 +#define XED_OPERAND_NEED_MEMDISP_DEFINED 1 +#define XED_OPERAND_NEED_SIB_DEFINED 1 +#define XED_OPERAND_NELEM_DEFINED 1 +#define XED_OPERAND_NOMINAL_OPCODE_DEFINED 1 +#define XED_OPERAND_NOREX_DEFINED 1 +#define XED_OPERAND_NO_SCALE_DISP8_DEFINED 1 +#define XED_OPERAND_NPREFIXES_DEFINED 1 +#define XED_OPERAND_NREXES_DEFINED 1 +#define XED_OPERAND_NSEG_PREFIXES_DEFINED 1 +#define XED_OPERAND_OSZ_DEFINED 1 +#define XED_OPERAND_OUTREG_DEFINED 1 +#define XED_OPERAND_OUT_OF_BYTES_DEFINED 1 +#define XED_OPERAND_P4_DEFINED 1 +#define XED_OPERAND_POS_DISP_DEFINED 1 +#define XED_OPERAND_POS_IMM_DEFINED 1 +#define XED_OPERAND_POS_IMM1_DEFINED 1 +#define XED_OPERAND_POS_MODRM_DEFINED 1 +#define XED_OPERAND_POS_NOMINAL_OPCODE_DEFINED 1 +#define XED_OPERAND_POS_SIB_DEFINED 1 +#define XED_OPERAND_PREFIX66_DEFINED 1 +#define XED_OPERAND_PTR_DEFINED 1 +#define XED_OPERAND_REALMODE_DEFINED 1 +#define XED_OPERAND_REG_DEFINED 1 +#define XED_OPERAND_REG0_DEFINED 1 +#define XED_OPERAND_REG1_DEFINED 1 +#define XED_OPERAND_REG2_DEFINED 1 +#define XED_OPERAND_REG3_DEFINED 1 +#define XED_OPERAND_REG4_DEFINED 1 +#define XED_OPERAND_REG5_DEFINED 1 +#define XED_OPERAND_REG6_DEFINED 1 +#define XED_OPERAND_REG7_DEFINED 1 +#define XED_OPERAND_REG8_DEFINED 1 +#define XED_OPERAND_REG9_DEFINED 1 +#define XED_OPERAND_RELBR_DEFINED 1 +#define XED_OPERAND_REP_DEFINED 1 +#define XED_OPERAND_REX_DEFINED 1 +#define XED_OPERAND_REXB_DEFINED 1 +#define XED_OPERAND_REXR_DEFINED 1 +#define XED_OPERAND_REXRR_DEFINED 1 +#define XED_OPERAND_REXW_DEFINED 1 +#define XED_OPERAND_REXX_DEFINED 1 +#define XED_OPERAND_RM_DEFINED 1 +#define XED_OPERAND_ROUNDC_DEFINED 1 +#define XED_OPERAND_SAE_DEFINED 1 +#define XED_OPERAND_SCALE_DEFINED 1 +#define XED_OPERAND_SEG0_DEFINED 1 +#define XED_OPERAND_SEG1_DEFINED 1 +#define XED_OPERAND_SEG_OVD_DEFINED 1 +#define XED_OPERAND_SIBBASE_DEFINED 1 +#define XED_OPERAND_SIBINDEX_DEFINED 1 +#define XED_OPERAND_SIBSCALE_DEFINED 1 +#define XED_OPERAND_SMODE_DEFINED 1 +#define XED_OPERAND_SRM_DEFINED 1 +#define XED_OPERAND_TZCNT_DEFINED 1 +#define XED_OPERAND_UBIT_DEFINED 1 +#define XED_OPERAND_UIMM0_DEFINED 1 +#define XED_OPERAND_UIMM1_DEFINED 1 +#define XED_OPERAND_USING_DEFAULT_SEGMENT0_DEFINED 1 +#define XED_OPERAND_USING_DEFAULT_SEGMENT1_DEFINED 1 +#define XED_OPERAND_VEXDEST210_DEFINED 1 +#define XED_OPERAND_VEXDEST3_DEFINED 1 +#define XED_OPERAND_VEXDEST4_DEFINED 1 +#define XED_OPERAND_VEXVALID_DEFINED 1 +#define XED_OPERAND_VEX_C4_DEFINED 1 +#define XED_OPERAND_VEX_PREFIX_DEFINED 1 +#define XED_OPERAND_VL_DEFINED 1 +#define XED_OPERAND_WBNOINVD_DEFINED 1 +#define XED_OPERAND_ZEROING_DEFINED 1 +#define XED_OPERAND_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_INVALID, + XED_OPERAND_AGEN, + XED_OPERAND_AMD3DNOW, + XED_OPERAND_ASZ, + XED_OPERAND_BASE0, + XED_OPERAND_BASE1, + XED_OPERAND_BCAST, + XED_OPERAND_BCRC, + XED_OPERAND_BRDISP_WIDTH, + XED_OPERAND_CET, + XED_OPERAND_CHIP, + XED_OPERAND_CLDEMOTE, + XED_OPERAND_DEFAULT_SEG, + XED_OPERAND_DF32, + XED_OPERAND_DF64, + XED_OPERAND_DISP, + XED_OPERAND_DISP_WIDTH, + XED_OPERAND_DUMMY, + XED_OPERAND_EASZ, + XED_OPERAND_ELEMENT_SIZE, + XED_OPERAND_ENCODER_PREFERRED, + XED_OPERAND_ENCODE_FORCE, + XED_OPERAND_EOSZ, + XED_OPERAND_ERROR, + XED_OPERAND_ESRC, + XED_OPERAND_FIRST_F2F3, + XED_OPERAND_HAS_MODRM, + XED_OPERAND_HAS_SIB, + XED_OPERAND_HINT, + XED_OPERAND_ICLASS, + XED_OPERAND_ILD_F2, + XED_OPERAND_ILD_F3, + XED_OPERAND_ILD_SEG, + XED_OPERAND_IMM0, + XED_OPERAND_IMM0SIGNED, + XED_OPERAND_IMM1, + XED_OPERAND_IMM1_BYTES, + XED_OPERAND_IMM_WIDTH, + XED_OPERAND_INDEX, + XED_OPERAND_LAST_F2F3, + XED_OPERAND_LLRC, + XED_OPERAND_LOCK, + XED_OPERAND_LZCNT, + XED_OPERAND_MAP, + XED_OPERAND_MASK, + XED_OPERAND_MAX_BYTES, + XED_OPERAND_MEM0, + XED_OPERAND_MEM1, + XED_OPERAND_MEM_WIDTH, + XED_OPERAND_MOD, + XED_OPERAND_MODE, + XED_OPERAND_MODEP5, + XED_OPERAND_MODEP55C, + XED_OPERAND_MODE_FIRST_PREFIX, + XED_OPERAND_MODE_SHORT_UD0, + XED_OPERAND_MODRM_BYTE, + XED_OPERAND_MPXMODE, + XED_OPERAND_MUST_USE_EVEX, + XED_OPERAND_NEEDREX, + XED_OPERAND_NEED_MEMDISP, + XED_OPERAND_NEED_SIB, + XED_OPERAND_NELEM, + XED_OPERAND_NOMINAL_OPCODE, + XED_OPERAND_NOREX, + XED_OPERAND_NO_SCALE_DISP8, + XED_OPERAND_NPREFIXES, + XED_OPERAND_NREXES, + XED_OPERAND_NSEG_PREFIXES, + XED_OPERAND_OSZ, + XED_OPERAND_OUTREG, + XED_OPERAND_OUT_OF_BYTES, + XED_OPERAND_P4, + XED_OPERAND_POS_DISP, + XED_OPERAND_POS_IMM, + XED_OPERAND_POS_IMM1, + XED_OPERAND_POS_MODRM, + XED_OPERAND_POS_NOMINAL_OPCODE, + XED_OPERAND_POS_SIB, + XED_OPERAND_PREFIX66, + XED_OPERAND_PTR, + XED_OPERAND_REALMODE, + XED_OPERAND_REG, + XED_OPERAND_REG0, + XED_OPERAND_REG1, + XED_OPERAND_REG2, + XED_OPERAND_REG3, + XED_OPERAND_REG4, + XED_OPERAND_REG5, + XED_OPERAND_REG6, + XED_OPERAND_REG7, + XED_OPERAND_REG8, + XED_OPERAND_REG9, + XED_OPERAND_RELBR, + XED_OPERAND_REP, + XED_OPERAND_REX, + XED_OPERAND_REXB, + XED_OPERAND_REXR, + XED_OPERAND_REXRR, + XED_OPERAND_REXW, + XED_OPERAND_REXX, + XED_OPERAND_RM, + XED_OPERAND_ROUNDC, + XED_OPERAND_SAE, + XED_OPERAND_SCALE, + XED_OPERAND_SEG0, + XED_OPERAND_SEG1, + XED_OPERAND_SEG_OVD, + XED_OPERAND_SIBBASE, + XED_OPERAND_SIBINDEX, + XED_OPERAND_SIBSCALE, + XED_OPERAND_SMODE, + XED_OPERAND_SRM, + XED_OPERAND_TZCNT, + XED_OPERAND_UBIT, + XED_OPERAND_UIMM0, + XED_OPERAND_UIMM1, + XED_OPERAND_USING_DEFAULT_SEGMENT0, + XED_OPERAND_USING_DEFAULT_SEGMENT1, + XED_OPERAND_VEXDEST210, + XED_OPERAND_VEXDEST3, + XED_OPERAND_VEXDEST4, + XED_OPERAND_VEXVALID, + XED_OPERAND_VEX_C4, + XED_OPERAND_VEX_PREFIX, + XED_OPERAND_VL, + XED_OPERAND_WBNOINVD, + XED_OPERAND_ZEROING, + XED_OPERAND_LAST +} xed_operand_enum_t; + +/// This converts strings to #xed_operand_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_enum_t str2xed_operand_enum_t(const char* s); +/// This converts strings to #xed_operand_enum_t types. +/// @param p An enumeration element of type xed_operand_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_enum_t2str(const xed_operand_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_enum_t xed_operand_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-storage.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-storage.h new file mode 100644 index 0000000..ef2cba5 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-storage.h @@ -0,0 +1,158 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-storage.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_STORAGE_H) +# define XED_OPERAND_STORAGE_H +#include "xed-chip-enum.h" +#include "xed-error-enum.h" +#include "xed-iclass-enum.h" +#include "xed-reg-enum.h" +#include "xed-operand-element-type-enum.h" +typedef struct xed_operand_storage_s { + xed_uint8_t agen; + xed_uint8_t amd3dnow; + xed_uint8_t asz; + xed_uint8_t bcrc; + xed_uint8_t cet; + xed_uint8_t cldemote; + xed_uint8_t df32; + xed_uint8_t df64; + xed_uint8_t dummy; + xed_uint8_t encoder_preferred; + xed_uint8_t encode_force; + xed_uint8_t has_sib; + xed_uint8_t ild_f2; + xed_uint8_t ild_f3; + xed_uint8_t imm0; + xed_uint8_t imm0signed; + xed_uint8_t imm1; + xed_uint8_t lock; + xed_uint8_t lzcnt; + xed_uint8_t mem0; + xed_uint8_t mem1; + xed_uint8_t modep5; + xed_uint8_t modep55c; + xed_uint8_t mode_first_prefix; + xed_uint8_t mode_short_ud0; + xed_uint8_t mpxmode; + xed_uint8_t must_use_evex; + xed_uint8_t needrex; + xed_uint8_t need_sib; + xed_uint8_t norex; + xed_uint8_t no_scale_disp8; + xed_uint8_t osz; + xed_uint8_t out_of_bytes; + xed_uint8_t p4; + xed_uint8_t prefix66; + xed_uint8_t ptr; + xed_uint8_t realmode; + xed_uint8_t relbr; + xed_uint8_t rex; + xed_uint8_t rexb; + xed_uint8_t rexr; + xed_uint8_t rexrr; + xed_uint8_t rexw; + xed_uint8_t rexx; + xed_uint8_t sae; + xed_uint8_t tzcnt; + xed_uint8_t ubit; + xed_uint8_t using_default_segment0; + xed_uint8_t using_default_segment1; + xed_uint8_t vexdest3; + xed_uint8_t vexdest4; + xed_uint8_t vex_c4; + xed_uint8_t wbnoinvd; + xed_uint8_t zeroing; + xed_uint8_t default_seg; + xed_uint8_t easz; + xed_uint8_t eosz; + xed_uint8_t first_f2f3; + xed_uint8_t has_modrm; + xed_uint8_t last_f2f3; + xed_uint8_t llrc; + xed_uint8_t mod; + xed_uint8_t mode; + xed_uint8_t rep; + xed_uint8_t sibscale; + xed_uint8_t smode; + xed_uint8_t vex_prefix; + xed_uint8_t vl; + xed_uint8_t hint; + xed_uint8_t mask; + xed_uint8_t reg; + xed_uint8_t rm; + xed_uint8_t roundc; + xed_uint8_t seg_ovd; + xed_uint8_t sibbase; + xed_uint8_t sibindex; + xed_uint8_t srm; + xed_uint8_t vexdest210; + xed_uint8_t vexvalid; + xed_uint8_t error; + xed_uint8_t esrc; + xed_uint8_t map; + xed_uint8_t nelem; + xed_uint8_t scale; + xed_uint8_t bcast; + xed_uint8_t need_memdisp; + xed_uint8_t chip; + xed_uint8_t brdisp_width; + xed_uint8_t disp_width; + xed_uint8_t ild_seg; + xed_uint8_t imm1_bytes; + xed_uint8_t imm_width; + xed_uint8_t max_bytes; + xed_uint8_t modrm_byte; + xed_uint8_t nominal_opcode; + xed_uint8_t nprefixes; + xed_uint8_t nrexes; + xed_uint8_t nseg_prefixes; + xed_uint8_t pos_disp; + xed_uint8_t pos_imm; + xed_uint8_t pos_imm1; + xed_uint8_t pos_modrm; + xed_uint8_t pos_nominal_opcode; + xed_uint8_t pos_sib; + xed_uint8_t uimm1; + xed_uint16_t base0; + xed_uint16_t base1; + xed_uint16_t element_size; + xed_uint16_t index; + xed_uint16_t outreg; + xed_uint16_t reg0; + xed_uint16_t reg1; + xed_uint16_t reg2; + xed_uint16_t reg3; + xed_uint16_t reg4; + xed_uint16_t reg5; + xed_uint16_t reg6; + xed_uint16_t reg7; + xed_uint16_t reg8; + xed_uint16_t reg9; + xed_uint16_t seg0; + xed_uint16_t seg1; + xed_uint16_t iclass; + xed_uint16_t mem_width; + xed_uint64_t disp; + xed_uint64_t uimm0; +} xed_operand_storage_t; +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-type-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-type-enum.h new file mode 100644 index 0000000..59de908 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-type-enum.h @@ -0,0 +1,62 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-type-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_TYPE_ENUM_H) +# define XED_OPERAND_TYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_TYPE_INVALID_DEFINED 1 +#define XED_OPERAND_TYPE_ERROR_DEFINED 1 +#define XED_OPERAND_TYPE_IMM_DEFINED 1 +#define XED_OPERAND_TYPE_IMM_CONST_DEFINED 1 +#define XED_OPERAND_TYPE_NT_LOOKUP_FN_DEFINED 1 +#define XED_OPERAND_TYPE_NT_LOOKUP_FN2_DEFINED 1 +#define XED_OPERAND_TYPE_NT_LOOKUP_FN4_DEFINED 1 +#define XED_OPERAND_TYPE_REG_DEFINED 1 +#define XED_OPERAND_TYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_TYPE_INVALID, + XED_OPERAND_TYPE_ERROR, + XED_OPERAND_TYPE_IMM, + XED_OPERAND_TYPE_IMM_CONST, + XED_OPERAND_TYPE_NT_LOOKUP_FN, + XED_OPERAND_TYPE_NT_LOOKUP_FN2, + XED_OPERAND_TYPE_NT_LOOKUP_FN4, + XED_OPERAND_TYPE_REG, + XED_OPERAND_TYPE_LAST +} xed_operand_type_enum_t; + +/// This converts strings to #xed_operand_type_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_type_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_type_enum_t str2xed_operand_type_enum_t(const char* s); +/// This converts strings to #xed_operand_type_enum_t types. +/// @param p An enumeration element of type xed_operand_type_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_type_enum_t2str(const xed_operand_type_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_type_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_type_enum_t xed_operand_type_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-values-interface.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-values-interface.h new file mode 100644 index 0000000..72d9caf --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-values-interface.h @@ -0,0 +1,522 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-values-interface.h +/// + +#if !defined(XED_OPERAND_VALUES_INTERFACE_H) +# define XED_OPERAND_VALUES_INTERFACE_H + +#include "xed-common-hdrs.h" +#include "xed-common-defs.h" +#include "xed-portability.h" +#include "xed-util.h" +#include "xed-types.h" +#include "xed-state.h" // a generated file +#include "xed-operand-enum.h" // a generated file +#include "xed-decoded-inst.h" +#include "xed-reg-enum.h" // generated +#include "xed-iclass-enum.h" // generated +/// @name Initialization +//@{ +/// @ingroup OPERANDS +/// Initializes operand structure +XED_DLL_EXPORT void xed_operand_values_init(xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Initializes the operand storage and sets mode values. +XED_DLL_EXPORT void xed_operand_values_init_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate); + +/// @ingroup OPERANDS +/// Set the mode values +XED_DLL_EXPORT void +xed_operand_values_set_mode(xed_operand_values_t* p, + const xed_state_t* dstate); + +/// @ingroup OPERANDS +/// Initializes dst operand structure but preserves the existing +/// MODE/SMODE values from the src operand structure. +XED_DLL_EXPORT void +xed_operand_values_init_keep_mode( xed_operand_values_t* dst, + const xed_operand_values_t* src ); +//@} + +/////////////////////////////////////////////////////////// +/// @name String output +//@{ +/// @ingroup OPERANDS +/// Dump all the information about the operands to buf. +XED_DLL_EXPORT void +xed_operand_values_dump(const xed_operand_values_t* ov, + char* buf, + int buflen); +/// @ingroup OPERANDS +/// More tersely dump all the information about the operands to buf. +XED_DLL_EXPORT void +xed_operand_values_print_short(const xed_operand_values_t* ov, + char* buf, + int buflen); +//@} + +/// @name REP/REPNE Prefixes +//@{ +/// @ingroup OPERANDS +/// True if the instruction has a real REP prefix. This returns false if +/// there is no F2/F3 prefix or the F2/F3 prefix is used to refine the +/// opcode as in some SSE operations. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_real_rep(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if the instruction as a F3 REP prefix (used for opcode refining, +/// for rep for string operations, or ignored). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_rep_prefix(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if the instruction as a F2 REP prefix (used for opcode refining, +/// for rep for string operations, or ignored). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_repne_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// DO NOT USE - DEPRECATED. The correct way to do remove a rep prefix is by changing the iclass +XED_DLL_EXPORT void xed_operand_values_clear_rep(xed_operand_values_t* p); + +//@} + +/// @name Atomic / Locked operations +//@{ +/// @ingroup OPERANDS +/// Returns true if the memory operation has atomic read-modify-write +/// semantics. An XCHG accessing memory is atomic with or without a +/// LOCK prefix. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_atomic(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the memory operation has a valid lock prefix. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_lock_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the instruction could be re-encoded to have a lock +/// prefix but does not have one currently. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_lockable(const xed_operand_values_t* p); +//@} + + +/// @ingroup OPERANDS +/// Indicates if the default segment is being used. +/// @param[in] p the pointer to the #xed_operand_values_t structure. +/// @param[in] i 0 or 1, indicating which memory operation. +/// @return true if the memory operation is using the default segment for +/// the associated addressing mode base register. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_using_default_segment(const xed_operand_values_t* p, + unsigned int i); + + + +/// @ingroup OPERANDS +/// Returns The effective operand width in bits: 16/32/64. Note this is not +/// the same as the width of the operand which can vary! For 8 bit +/// operations, the effective operand width is the machine mode's default +/// width. If you also want to identify byte operations use the higher +/// level function #xed_decoded_inst_get_operand_width() . +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_effective_operand_width(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Returns The effective address width in bits: 16/32/64. +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_effective_address_width(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Returns The stack address width in bits: 16/32/64. +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_stack_address_width(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// True if there is a memory displacement +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_memory_displacement(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if there is a branch displacement +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_branch_displacement(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// True if there is a memory or branch displacement +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_displacement(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// Deprecated. Compatibility function for XED0. See has_memory_displacement(). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_displacement_for_memop(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return true if there is an immediate operand +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_immediate(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// ALIAS for has_displacement(). +/// Deprecated. See has_memory_displacement() and +/// has_branch_displacement(). +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_disp(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This indicates the presence of a 67 prefix. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_address_size_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This does not include the cases when the 66 prefix is used an +/// opcode-refining prefix for multibyte opcodes. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_operand_size_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This includes any 66 prefix that shows up even if it is ignored. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_66_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// This instruction has a REX prefix with the W bit set. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_rexw_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_segment_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return the segment prefix, if any, as a #xed_reg_enum_t value. +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_segment_prefix(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_is_prefetch(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_long_mode(const xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_get_real_mode(const xed_operand_values_t* p); + +/// @name Memory Addressing +//@{ +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_accesses_memory(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT unsigned int +xed_operand_values_number_of_memory_operands(const xed_operand_values_t* p); + +/// return bytes +/// @ingroup OPERANDS +XED_DLL_EXPORT unsigned int +xed_operand_values_get_memory_operand_length(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_get_base_reg(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_get_index_reg(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_reg_enum_t +xed_operand_values_get_seg_reg(const xed_operand_values_t* p, + unsigned int memop_idx); + +/// @ingroup OPERANDS +XED_DLL_EXPORT unsigned int +xed_operand_values_get_scale(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the instruction access memory but without using a MODRM +/// byte limiting its addressing modes. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_memop_without_modrm(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Returns true if the instruction has a MODRM byte. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_modrm_byte(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if the instruction has a SIB byte. +XED_DLL_EXPORT xed_bool_t +xed_operand_values_has_sib_byte(const xed_operand_values_t* p); +//@} + + +/// @ingroup OPERANDS +/// Returns true if 0x2E prefix on Jcc +XED_DLL_EXPORT xed_bool_t +xed_operand_values_branch_not_taken_hint(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true if 0x3E prefix on Jcc +XED_DLL_EXPORT xed_bool_t +xed_operand_values_branch_taken_hint(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Returns true for indirect call/jmp with 0x3E prefix (if the legacy prefix rules are obeyed) +XED_DLL_EXPORT xed_bool_t +xed_operand_values_cet_no_track(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_bool_t +xed_operand_values_is_nop(const xed_operand_values_t* p); + + +/// @name Immediates +//@{ +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_int64_t +xed_operand_values_get_immediate_int64(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint64_t +xed_operand_values_get_immediate_uint64(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return true if the first immediate (IMM0) is signed +XED_DLL_EXPORT xed_uint_t +xed_operand_values_get_immediate_is_signed(const xed_operand_values_t* p); + + +/// @ingroup OPERANDS +/// Return the i'th byte of the immediate +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_immediate_byte(const xed_operand_values_t* p, + unsigned int i); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_second_immediate(const xed_operand_values_t* p); +//@} + +/// @name Memory Displacements +//@{ +/// @ingroup OPERANDS +/// Return the memory displacement width in BYTES +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_memory_displacement_length(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Return the memory displacement width in BITS +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits( + const xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Return the raw memory displacement width in BITS(ignores scaling) +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_memory_displacement_length_bits_raw( + const xed_operand_values_t* p); + +/// Returns the potentially scaled value of the memory +/// displacement. Certain AVX512 memory displacements are scaled before +/// they are used. @ingroup OPERANDS +XED_DLL_EXPORT xed_int64_t +xed_operand_values_get_memory_displacement_int64(const xed_operand_values_t* p); + +/// Returns the unscaled (raw) memory displacement. Certain AVX512 memory +/// displacements are scaled before they are used. @ingroup OPERANDS +XED_DLL_EXPORT xed_int64_t +xed_operand_values_get_memory_displacement_int64_raw(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_memory_displacement_byte(const xed_operand_values_t* p, + unsigned int i); +//@} + +/// @name Branch Displacements +//@{ +/// @ingroup OPERANDS +/// Return the branch displacement width in bytes +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_branch_displacement_length(const xed_operand_values_t* p); +/// @ingroup OPERANDS +/// Return the branch displacement width in bits +XED_DLL_EXPORT xed_uint32_t +xed_operand_values_get_branch_displacement_length_bits( + const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_int32_t +xed_operand_values_get_branch_displacement_int32(const xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_uint8_t +xed_operand_values_get_branch_displacement_byte(const xed_operand_values_t* p, + unsigned int i); +//@} + + +/// @ingroup OPERANDS +XED_DLL_EXPORT xed_iclass_enum_t +xed_operand_values_get_iclass(const xed_operand_values_t* p); + +//////////////////////////////////////////////////// +// ENCODE API +//////////////////////////////////////////////////// +/// @name Encoding +//@{ +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_immediate(xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_branch_displacement(xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_memory_displacement(xed_operand_values_t* p); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_lock(xed_operand_values_t* p); +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_zero_segment_override(xed_operand_values_t* p); + + +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_set_iclass(xed_operand_values_t* p, + xed_iclass_enum_t iclass); + +/// @ingroup OPERANDS +/// width is bits 8, 16, 32, 64 +XED_DLL_EXPORT void +xed_operand_values_set_effective_operand_width(xed_operand_values_t* p, + unsigned int width); + +/// @ingroup OPERANDS +/// width is bits 16, 32, 64 +XED_DLL_EXPORT void +xed_operand_values_set_effective_address_width(xed_operand_values_t* p, + unsigned int width); +/// takes bytes, not bits, as an argument +/// @ingroup OPERANDS +XED_DLL_EXPORT void +xed_operand_values_set_memory_operand_length(xed_operand_values_t* p, + unsigned int memop_length); + + +/// @ingroup OPERANDS +/// Set the memory displacement using a BYTES length +XED_DLL_EXPORT void +xed_operand_values_set_memory_displacement(xed_operand_values_t* p, + xed_int64_t x, unsigned int len); +/// @ingroup OPERANDS +/// Set the memory displacement using a BITS length +XED_DLL_EXPORT void +xed_operand_values_set_memory_displacement_bits(xed_operand_values_t* p, + xed_int64_t x, + unsigned int len_bits); + +/// @ingroup OPERANDS +/// Indicate that we have a relative branch. +XED_DLL_EXPORT void xed_operand_values_set_relbr(xed_operand_values_t* p); + +/// @ingroup OPERANDS +/// Set the branch displacement using a BYTES length +XED_DLL_EXPORT void +xed_operand_values_set_branch_displacement(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len); +/// @ingroup OPERANDS +/// Set the branch displacement using a BITS length +XED_DLL_EXPORT void +xed_operand_values_set_branch_displacement_bits(xed_operand_values_t* p, + xed_int32_t x, + unsigned int len_bits); + +/// @ingroup OPERANDS +/// Set the signed immediate using a BYTES length +XED_DLL_EXPORT void +xed_operand_values_set_immediate_signed(xed_operand_values_t* p, + xed_int32_t x, + unsigned int bytes); +/// @ingroup OPERANDS +/// Set the signed immediate using a BITS length +XED_DLL_EXPORT void +xed_operand_values_set_immediate_signed_bits(xed_operand_values_t* p, + xed_int32_t x, + unsigned int bits); + + +/// @ingroup OPERANDS +/// Set the unsigned immediate using a BYTE length. +XED_DLL_EXPORT void +xed_operand_values_set_immediate_unsigned(xed_operand_values_t* p, + xed_uint64_t x, + unsigned int bytes); +/// @ingroup OPERANDS +/// Set the unsigned immediate using a BIT length. +XED_DLL_EXPORT void +xed_operand_values_set_immediate_unsigned_bits(xed_operand_values_t* p, + xed_uint64_t x, + unsigned int bits); + + + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_base_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_base); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_seg_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_seg); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_index_reg(xed_operand_values_t* p, + unsigned int memop_idx, + xed_reg_enum_t new_index); + +/// @ingroup OPERANDS +XED_DLL_EXPORT void xed_operand_values_set_scale(xed_operand_values_t* p, + xed_uint_t memop_idx, + xed_uint_t new_scale); + + +/// @ingroup OPERANDS +/// Set the operand storage field entry named 'operand_name' to the +/// register value specified by 'reg_name'. +XED_DLL_EXPORT void +xed_operand_values_set_operand_reg(xed_operand_values_t* p, + xed_operand_enum_t operand_name, + xed_reg_enum_t reg_name); + +//@} +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-visibility-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-visibility-enum.h new file mode 100644 index 0000000..f187900 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-visibility-enum.h @@ -0,0 +1,54 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-visibility-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_VISIBILITY_ENUM_H) +# define XED_OPERAND_VISIBILITY_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPVIS_INVALID_DEFINED 1 +#define XED_OPVIS_EXPLICIT_DEFINED 1 +#define XED_OPVIS_IMPLICIT_DEFINED 1 +#define XED_OPVIS_SUPPRESSED_DEFINED 1 +#define XED_OPVIS_LAST_DEFINED 1 +typedef enum { + XED_OPVIS_INVALID, + XED_OPVIS_EXPLICIT, ///< Shows up in operand encoding + XED_OPVIS_IMPLICIT, ///< Part of the opcode, but listed as an operand + XED_OPVIS_SUPPRESSED, ///< Part of the opcode, but not typically listed as an operand + XED_OPVIS_LAST +} xed_operand_visibility_enum_t; + +/// This converts strings to #xed_operand_visibility_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_visibility_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_visibility_enum_t str2xed_operand_visibility_enum_t(const char* s); +/// This converts strings to #xed_operand_visibility_enum_t types. +/// @param p An enumeration element of type xed_operand_visibility_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_visibility_enum_t2str(const xed_operand_visibility_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_visibility_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_visibility_enum_t xed_operand_visibility_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-width-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-width-enum.h new file mode 100644 index 0000000..c97e00c --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-operand-width-enum.h @@ -0,0 +1,300 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-operand-width-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_WIDTH_ENUM_H) +# define XED_OPERAND_WIDTH_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_WIDTH_INVALID_DEFINED 1 +#define XED_OPERAND_WIDTH_ASZ_DEFINED 1 +#define XED_OPERAND_WIDTH_SSZ_DEFINED 1 +#define XED_OPERAND_WIDTH_PSEUDO_DEFINED 1 +#define XED_OPERAND_WIDTH_PSEUDOX87_DEFINED 1 +#define XED_OPERAND_WIDTH_A16_DEFINED 1 +#define XED_OPERAND_WIDTH_A32_DEFINED 1 +#define XED_OPERAND_WIDTH_B_DEFINED 1 +#define XED_OPERAND_WIDTH_D_DEFINED 1 +#define XED_OPERAND_WIDTH_I8_DEFINED 1 +#define XED_OPERAND_WIDTH_U8_DEFINED 1 +#define XED_OPERAND_WIDTH_I16_DEFINED 1 +#define XED_OPERAND_WIDTH_U16_DEFINED 1 +#define XED_OPERAND_WIDTH_I32_DEFINED 1 +#define XED_OPERAND_WIDTH_U32_DEFINED 1 +#define XED_OPERAND_WIDTH_I64_DEFINED 1 +#define XED_OPERAND_WIDTH_U64_DEFINED 1 +#define XED_OPERAND_WIDTH_F16_DEFINED 1 +#define XED_OPERAND_WIDTH_F32_DEFINED 1 +#define XED_OPERAND_WIDTH_F64_DEFINED 1 +#define XED_OPERAND_WIDTH_DQ_DEFINED 1 +#define XED_OPERAND_WIDTH_XUB_DEFINED 1 +#define XED_OPERAND_WIDTH_XUW_DEFINED 1 +#define XED_OPERAND_WIDTH_XUD_DEFINED 1 +#define XED_OPERAND_WIDTH_XUQ_DEFINED 1 +#define XED_OPERAND_WIDTH_X128_DEFINED 1 +#define XED_OPERAND_WIDTH_XB_DEFINED 1 +#define XED_OPERAND_WIDTH_XW_DEFINED 1 +#define XED_OPERAND_WIDTH_XD_DEFINED 1 +#define XED_OPERAND_WIDTH_XQ_DEFINED 1 +#define XED_OPERAND_WIDTH_ZB_DEFINED 1 +#define XED_OPERAND_WIDTH_ZW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZD_DEFINED 1 +#define XED_OPERAND_WIDTH_ZQ_DEFINED 1 +#define XED_OPERAND_WIDTH_MB_DEFINED 1 +#define XED_OPERAND_WIDTH_MW_DEFINED 1 +#define XED_OPERAND_WIDTH_MD_DEFINED 1 +#define XED_OPERAND_WIDTH_MQ_DEFINED 1 +#define XED_OPERAND_WIDTH_M64INT_DEFINED 1 +#define XED_OPERAND_WIDTH_M64REAL_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM108_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM14_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM16_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM16INT_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM28_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM32INT_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM32REAL_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM80DEC_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM80REAL_DEFINED 1 +#define XED_OPERAND_WIDTH_F80_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM94_DEFINED 1 +#define XED_OPERAND_WIDTH_MFPXENV_DEFINED 1 +#define XED_OPERAND_WIDTH_MXSAVE_DEFINED 1 +#define XED_OPERAND_WIDTH_MPREFETCH_DEFINED 1 +#define XED_OPERAND_WIDTH_P_DEFINED 1 +#define XED_OPERAND_WIDTH_P2_DEFINED 1 +#define XED_OPERAND_WIDTH_PD_DEFINED 1 +#define XED_OPERAND_WIDTH_PS_DEFINED 1 +#define XED_OPERAND_WIDTH_PI_DEFINED 1 +#define XED_OPERAND_WIDTH_Q_DEFINED 1 +#define XED_OPERAND_WIDTH_S_DEFINED 1 +#define XED_OPERAND_WIDTH_S64_DEFINED 1 +#define XED_OPERAND_WIDTH_SD_DEFINED 1 +#define XED_OPERAND_WIDTH_SI_DEFINED 1 +#define XED_OPERAND_WIDTH_SS_DEFINED 1 +#define XED_OPERAND_WIDTH_V_DEFINED 1 +#define XED_OPERAND_WIDTH_Y_DEFINED 1 +#define XED_OPERAND_WIDTH_W_DEFINED 1 +#define XED_OPERAND_WIDTH_Z_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW8_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW5_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW3_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW2_DEFINED 1 +#define XED_OPERAND_WIDTH_I1_DEFINED 1 +#define XED_OPERAND_WIDTH_I2_DEFINED 1 +#define XED_OPERAND_WIDTH_I3_DEFINED 1 +#define XED_OPERAND_WIDTH_I4_DEFINED 1 +#define XED_OPERAND_WIDTH_I5_DEFINED 1 +#define XED_OPERAND_WIDTH_I6_DEFINED 1 +#define XED_OPERAND_WIDTH_I7_DEFINED 1 +#define XED_OPERAND_WIDTH_VAR_DEFINED 1 +#define XED_OPERAND_WIDTH_BND32_DEFINED 1 +#define XED_OPERAND_WIDTH_BND64_DEFINED 1 +#define XED_OPERAND_WIDTH_PMMSZ16_DEFINED 1 +#define XED_OPERAND_WIDTH_PMMSZ32_DEFINED 1 +#define XED_OPERAND_WIDTH_QQ_DEFINED 1 +#define XED_OPERAND_WIDTH_YUB_DEFINED 1 +#define XED_OPERAND_WIDTH_YUW_DEFINED 1 +#define XED_OPERAND_WIDTH_YUD_DEFINED 1 +#define XED_OPERAND_WIDTH_YUQ_DEFINED 1 +#define XED_OPERAND_WIDTH_Y128_DEFINED 1 +#define XED_OPERAND_WIDTH_YB_DEFINED 1 +#define XED_OPERAND_WIDTH_YW_DEFINED 1 +#define XED_OPERAND_WIDTH_YD_DEFINED 1 +#define XED_OPERAND_WIDTH_YQ_DEFINED 1 +#define XED_OPERAND_WIDTH_YPS_DEFINED 1 +#define XED_OPERAND_WIDTH_YPD_DEFINED 1 +#define XED_OPERAND_WIDTH_ZBF16_DEFINED 1 +#define XED_OPERAND_WIDTH_VV_DEFINED 1 +#define XED_OPERAND_WIDTH_ZV_DEFINED 1 +#define XED_OPERAND_WIDTH_WRD_DEFINED 1 +#define XED_OPERAND_WIDTH_MSKW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZMSKW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZF32_DEFINED 1 +#define XED_OPERAND_WIDTH_ZF64_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUB_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUD_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUQ_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI8_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI16_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI32_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI64_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU8_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU16_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU32_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU64_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU128_DEFINED 1 +#define XED_OPERAND_WIDTH_M384_DEFINED 1 +#define XED_OPERAND_WIDTH_M512_DEFINED 1 +#define XED_OPERAND_WIDTH_PTR_DEFINED 1 +#define XED_OPERAND_WIDTH_TMEMROW_DEFINED 1 +#define XED_OPERAND_WIDTH_TMEMCOL_DEFINED 1 +#define XED_OPERAND_WIDTH_TV_DEFINED 1 +#define XED_OPERAND_WIDTH_ZF16_DEFINED 1 +#define XED_OPERAND_WIDTH_Z2F16_DEFINED 1 +#define XED_OPERAND_WIDTH_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_WIDTH_INVALID, + XED_OPERAND_WIDTH_ASZ, + XED_OPERAND_WIDTH_SSZ, + XED_OPERAND_WIDTH_PSEUDO, + XED_OPERAND_WIDTH_PSEUDOX87, + XED_OPERAND_WIDTH_A16, + XED_OPERAND_WIDTH_A32, + XED_OPERAND_WIDTH_B, + XED_OPERAND_WIDTH_D, + XED_OPERAND_WIDTH_I8, + XED_OPERAND_WIDTH_U8, + XED_OPERAND_WIDTH_I16, + XED_OPERAND_WIDTH_U16, + XED_OPERAND_WIDTH_I32, + XED_OPERAND_WIDTH_U32, + XED_OPERAND_WIDTH_I64, + XED_OPERAND_WIDTH_U64, + XED_OPERAND_WIDTH_F16, + XED_OPERAND_WIDTH_F32, + XED_OPERAND_WIDTH_F64, + XED_OPERAND_WIDTH_DQ, + XED_OPERAND_WIDTH_XUB, + XED_OPERAND_WIDTH_XUW, + XED_OPERAND_WIDTH_XUD, + XED_OPERAND_WIDTH_XUQ, + XED_OPERAND_WIDTH_X128, + XED_OPERAND_WIDTH_XB, + XED_OPERAND_WIDTH_XW, + XED_OPERAND_WIDTH_XD, + XED_OPERAND_WIDTH_XQ, + XED_OPERAND_WIDTH_ZB, + XED_OPERAND_WIDTH_ZW, + XED_OPERAND_WIDTH_ZD, + XED_OPERAND_WIDTH_ZQ, + XED_OPERAND_WIDTH_MB, + XED_OPERAND_WIDTH_MW, + XED_OPERAND_WIDTH_MD, + XED_OPERAND_WIDTH_MQ, + XED_OPERAND_WIDTH_M64INT, + XED_OPERAND_WIDTH_M64REAL, + XED_OPERAND_WIDTH_MEM108, + XED_OPERAND_WIDTH_MEM14, + XED_OPERAND_WIDTH_MEM16, + XED_OPERAND_WIDTH_MEM16INT, + XED_OPERAND_WIDTH_MEM28, + XED_OPERAND_WIDTH_MEM32INT, + XED_OPERAND_WIDTH_MEM32REAL, + XED_OPERAND_WIDTH_MEM80DEC, + XED_OPERAND_WIDTH_MEM80REAL, + XED_OPERAND_WIDTH_F80, + XED_OPERAND_WIDTH_MEM94, + XED_OPERAND_WIDTH_MFPXENV, + XED_OPERAND_WIDTH_MXSAVE, + XED_OPERAND_WIDTH_MPREFETCH, + XED_OPERAND_WIDTH_P, + XED_OPERAND_WIDTH_P2, + XED_OPERAND_WIDTH_PD, + XED_OPERAND_WIDTH_PS, + XED_OPERAND_WIDTH_PI, + XED_OPERAND_WIDTH_Q, + XED_OPERAND_WIDTH_S, + XED_OPERAND_WIDTH_S64, + XED_OPERAND_WIDTH_SD, + XED_OPERAND_WIDTH_SI, + XED_OPERAND_WIDTH_SS, + XED_OPERAND_WIDTH_V, + XED_OPERAND_WIDTH_Y, + XED_OPERAND_WIDTH_W, + XED_OPERAND_WIDTH_Z, + XED_OPERAND_WIDTH_SPW8, + XED_OPERAND_WIDTH_SPW, + XED_OPERAND_WIDTH_SPW5, + XED_OPERAND_WIDTH_SPW3, + XED_OPERAND_WIDTH_SPW2, + XED_OPERAND_WIDTH_I1, + XED_OPERAND_WIDTH_I2, + XED_OPERAND_WIDTH_I3, + XED_OPERAND_WIDTH_I4, + XED_OPERAND_WIDTH_I5, + XED_OPERAND_WIDTH_I6, + XED_OPERAND_WIDTH_I7, + XED_OPERAND_WIDTH_VAR, + XED_OPERAND_WIDTH_BND32, + XED_OPERAND_WIDTH_BND64, + XED_OPERAND_WIDTH_PMMSZ16, + XED_OPERAND_WIDTH_PMMSZ32, + XED_OPERAND_WIDTH_QQ, + XED_OPERAND_WIDTH_YUB, + XED_OPERAND_WIDTH_YUW, + XED_OPERAND_WIDTH_YUD, + XED_OPERAND_WIDTH_YUQ, + XED_OPERAND_WIDTH_Y128, + XED_OPERAND_WIDTH_YB, + XED_OPERAND_WIDTH_YW, + XED_OPERAND_WIDTH_YD, + XED_OPERAND_WIDTH_YQ, + XED_OPERAND_WIDTH_YPS, + XED_OPERAND_WIDTH_YPD, + XED_OPERAND_WIDTH_ZBF16, + XED_OPERAND_WIDTH_VV, + XED_OPERAND_WIDTH_ZV, + XED_OPERAND_WIDTH_WRD, + XED_OPERAND_WIDTH_MSKW, + XED_OPERAND_WIDTH_ZMSKW, + XED_OPERAND_WIDTH_ZF32, + XED_OPERAND_WIDTH_ZF64, + XED_OPERAND_WIDTH_ZUB, + XED_OPERAND_WIDTH_ZUW, + XED_OPERAND_WIDTH_ZUD, + XED_OPERAND_WIDTH_ZUQ, + XED_OPERAND_WIDTH_ZI8, + XED_OPERAND_WIDTH_ZI16, + XED_OPERAND_WIDTH_ZI32, + XED_OPERAND_WIDTH_ZI64, + XED_OPERAND_WIDTH_ZU8, + XED_OPERAND_WIDTH_ZU16, + XED_OPERAND_WIDTH_ZU32, + XED_OPERAND_WIDTH_ZU64, + XED_OPERAND_WIDTH_ZU128, + XED_OPERAND_WIDTH_M384, + XED_OPERAND_WIDTH_M512, + XED_OPERAND_WIDTH_PTR, + XED_OPERAND_WIDTH_TMEMROW, + XED_OPERAND_WIDTH_TMEMCOL, + XED_OPERAND_WIDTH_TV, + XED_OPERAND_WIDTH_ZF16, + XED_OPERAND_WIDTH_Z2F16, + XED_OPERAND_WIDTH_LAST +} xed_operand_width_enum_t; + +/// This converts strings to #xed_operand_width_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_width_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_width_enum_t str2xed_operand_width_enum_t(const char* s); +/// This converts strings to #xed_operand_width_enum_t types. +/// @param p An enumeration element of type xed_operand_width_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_width_enum_t2str(const xed_operand_width_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_width_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_width_enum_t xed_operand_width_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-patch.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-patch.h new file mode 100644 index 0000000..e914d42 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-patch.h @@ -0,0 +1,63 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#ifndef XED_PATCH_H +# define XED_PATCH_H +#include "xed-encoder-hl.h" + +/// @name Patching decoded instructions +//@{ + + +/// Replace a memory displacement. +/// The widths of original displacement and replacement must match. +/// @param xedd A decoded instruction. +/// @param itext The corresponding encoder output, byte array. +/// @param disp A xed_enc_displacement_t object describing the new displacement. +/// @returns xed_bool_t 1=success, 0=failure +/// @ingroup ENCHLPATCH +XED_DLL_EXPORT xed_bool_t +xed_patch_disp(xed_decoded_inst_t* xedd, + xed_uint8_t* itext, + xed_enc_displacement_t disp); + +/// Replace a branch displacement. +/// The widths of original displacement and replacement must match. +/// @param xedd A decoded instruction. +/// @param itext The corresponding encoder output, byte array. +/// @param disp A xed_encoder_operand_t object describing the new displacement. +/// @returns xed_bool_t 1=success, 0=failure +/// @ingroup ENCHLPATCH +XED_DLL_EXPORT xed_bool_t +xed_patch_relbr(xed_decoded_inst_t* xedd, + xed_uint8_t* itext, + xed_encoder_operand_t disp); + +/// Replace an imm0 immediate value. +/// The widths of original immediate and replacement must match. +/// @param xedd A decoded instruction. +/// @param itext The corresponding encoder output, byte array. +/// @param imm0 A xed_encoder_operand_t object describing the new immediate. +/// @returns xed_bool_t 1=success, 0=failure +/// @ingroup ENCHLPATCH +XED_DLL_EXPORT xed_bool_t +xed_patch_imm0(xed_decoded_inst_t* xedd, + xed_uint8_t* itext, + xed_encoder_operand_t imm0); + +//@} +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-portability.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-portability.h new file mode 100644 index 0000000..1efd9a0 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-portability.h @@ -0,0 +1,186 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-portability.h +/// + +#ifndef XED_PORTABILITY_H +# define XED_PORTABILITY_H +# include "xed-common-hdrs.h" +# include "xed-types.h" + + +#define XED_STATIC_CAST(x,y) ((x) (y)) +#define XED_REINTERPRET_CAST(x,y) ((x) (y)) +#define XED_CAST(x,y) ((x) (y)) + + + +XED_DLL_EXPORT xed_uint_t xed_strlen(const char* s); +XED_DLL_EXPORT void xed_strcat(char* dst, const char* src); +XED_DLL_EXPORT void xed_strcpy(char* dst, const char* src); + +/// returns the number of bytes remaining for the next use of +/// #xed_strncpy() or #xed_strncat() . +XED_DLL_EXPORT int xed_strncpy(char* dst, const char* src, int len); + +/// returns the number of bytes remaining for the next use of +/// #xed_strncpy() or #xed_strncat() . +XED_DLL_EXPORT int xed_strncat(char* dst, const char* src, int len); + +#if defined(__INTEL_COMPILER) +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER >= 1400 +# define XED_MSVC8_OR_LATER 1 +# endif +# endif +#endif + +/* recognize VC98 */ +#if !defined(__INTEL_COMPILER) +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER == 1200 +# define XED_MSVC6 1 +# endif +# endif +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER == 1310 +# define XED_MSVC7 1 +# endif +# endif +# if defined(_WIN32) && defined(_MSC_VER) +# if _MSC_VER >= 1400 +# define XED_MSVC8_OR_LATER 1 +# endif +# if _MSC_VER == 1400 +# define XED_MSVC8 1 +# endif +# if _MSC_VER == 1500 +# define XED_MSVC9 1 +# endif +# if _MSC_VER >= 1500 +# define XED_MSVC9_OR_LATER 1 +# endif +# if _MSC_VER == 1600 +# define XED_MSVC10 1 +# endif +# if _MSC_VER >= 1600 +# define XED_MSVC10_OR_LATER 1 +# endif +# endif +#endif + +/* I've had compatibility problems here so I'm using a trivial indirection */ +#if defined(__GNUC__) +# if defined(__CYGWIN__) + /* cygwin's gcc 3.4.4 on windows complains */ +# define XED_FMT_X "%lx" +# define XED_FMT_08X "%08lx" +# define XED_FMT_D "%ld" +# define XED_FMT_U "%lu" +# define XED_FMT_9U "%9lu" +# else +# define XED_FMT_X "%x" +# define XED_FMT_08X "%08x" +# define XED_FMT_D "%d" +# define XED_FMT_U "%u" +# define XED_FMT_9U "%9u" +# endif +#else +# define XED_FMT_X "%x" +# define XED_FMT_08X "%08x" +# define XED_FMT_D "%d" +# define XED_FMT_U "%u" +# define XED_FMT_9U "%9u" +#endif + +// Go write portable code... Sigh +#if defined(__APPLE__) // clang *32b* and 64b +# define XED_FMT_SIZET "%lu" +#elif defined(__LP64__) // 64b gcc, icc +# define XED_FMT_SIZET "%lu" +#elif defined (_M_X64) // 64b msvs, ICL + // MSVS/x64 accepts %llu or %lu, icl/x64 does not) +# define XED_FMT_SIZET "%llu" +#else // 32b everything else +# define XED_FMT_SIZET "%u" +#endif + +#if defined(__GNUC__) && defined(__LP64__) && !defined(__APPLE__) +# define XED_FMT_LX "%lx" +# define XED_FMT_LX_UPPER "%lX" +# define XED_FMT_LU "%lu" +# define XED_FMT_LU12 "%12lu" +# define XED_FMT_LD "%ld" +# define XED_FMT_LX16 "%016lx" +# define XED_FMT_LX16_UPPER "%016lX" +#else +# define XED_FMT_LX "%llx" +# define XED_FMT_LX_UPPER "%llX" +# define XED_FMT_LU "%llu" +# define XED_FMT_LU12 "%12llu" +# define XED_FMT_LD "%lld" +# define XED_FMT_LX16 "%016llx" +# define XED_FMT_LX16_UPPER "%016llX" +#endif + +#if defined(__LP64__) || defined (_M_X64) +# define XED_64B 1 +#endif + +#if defined(_M_IA64) +# define XED_IPF +# define XED_FMT_SIZET "%lu" +#endif + +#if defined(__GNUC__) + /* gcc4.2.x has a bug with c99/gnu99 inlining */ +# if __GNUC__ == 4 && __GNUC_MINOR__ == 2 +# define XED_INLINE inline +# else +# if __GNUC__ == 2 +# define XED_INLINE +# else +# define XED_INLINE inline +# endif +# endif +# define XED_NORETURN __attribute__ ((noreturn)) +# if __GNUC__ == 2 +# define XED_NOINLINE +# else +# define XED_NOINLINE __attribute__ ((noinline)) +# endif +#else +# define XED_INLINE __inline +# if defined(XED_MSVC6) +# define XED_NOINLINE +# else +# define XED_NOINLINE __declspec(noinline) +# endif +# define XED_NORETURN __declspec(noreturn) +#endif + + + +#define XED_MAX(a, b) (((a) > (b)) ? (a):(b)) +#define XED_MIN(a, b) (((a) < (b)) ? (a):(b)) + + + + +#endif // XED_PORTABILITY_H + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-print-info.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-print-info.h new file mode 100644 index 0000000..694bfff --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-print-info.h @@ -0,0 +1,101 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_PRINT_INFO_H) +# define XED_PRINT_INFO_H + +#include "xed-types.h" +#include "xed-decoded-inst.h" +#include "xed-disas.h" // callback function type +#include "xed-syntax-enum.h" +#include "xed-format-options.h" + +/// @ingroup PRINT +/// This contains the information used by the various disassembly printers. +/// Call xed_init_print_info to initialize the fields. Then change the +/// required and optional fields when required. +typedef struct { + + ///////////////////////////////////////// + // REQUIRED FIELDS - users should set these + ///////////////////////////////////////// + + /// the decoded instruction to print + const xed_decoded_inst_t* p; + + /// pointer to the output buffer + char* buf; + + /// length of the output buffer. (bytes) Must be > 25 to start. + int blen; + + ///////////////////////////////////////// + // OPTIONAL FIELDS - user can set these + ///////////////////////////////////////// + + /// program counter location. Must be zero if not used. (Sometimes + /// instructions are disassembled in a temporary buffer at a different + /// location than where they may or will exist in memory). + xed_uint64_t runtime_address; + + /// disassembly_callback MUST be set to zero if not used! If zero, the + /// default disassembly callback is used (if one has been registered). + xed_disassembly_callback_fn_t disassembly_callback; + + /// passed to disassembly callback. Can be zero if not used. + void* context; + + /// default is Intel-syntax (dest on left) + xed_syntax_enum_t syntax; + + /// 1=indicated the format_options field is valid, 0=use default + /// formatting options from xed_format_set_options(). + int format_options_valid; + xed_format_options_t format_options; + + + ///////////////////////////////////////// + // NONPUBLIC FIELDS - Users should not use these! + ///////////////////////////////////////// + + /// internal, do not use + xed_bool_t emitted; + + /// internal, do not use + unsigned int operand_indx; + + /// internal, do not use + unsigned int skip_operand; + + /// internal, do not use + xed_reg_enum_t extra_index_operand; // for MPX + + /// internal, do not use + xed_bool_t implicit; + + /// internal, do not use + xed_bool_t truncate_eip_eosz16; + +} xed_print_info_t; + +// This function initializes the #xed_print_info_t structure. +// You must still set the required fields of that structure. +/// @ingroup PRINT +XED_DLL_EXPORT void xed_init_print_info(xed_print_info_t* pi); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-class-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-class-enum.h new file mode 100644 index 0000000..e97fd11 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-class-enum.h @@ -0,0 +1,102 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-reg-class-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_REG_CLASS_ENUM_H) +# define XED_REG_CLASS_ENUM_H +#include "xed-common-hdrs.h" +#define XED_REG_CLASS_INVALID_DEFINED 1 +#define XED_REG_CLASS_BNDCFG_DEFINED 1 +#define XED_REG_CLASS_BNDSTAT_DEFINED 1 +#define XED_REG_CLASS_BOUND_DEFINED 1 +#define XED_REG_CLASS_CR_DEFINED 1 +#define XED_REG_CLASS_DR_DEFINED 1 +#define XED_REG_CLASS_FLAGS_DEFINED 1 +#define XED_REG_CLASS_GPR_DEFINED 1 +#define XED_REG_CLASS_GPR16_DEFINED 1 +#define XED_REG_CLASS_GPR32_DEFINED 1 +#define XED_REG_CLASS_GPR64_DEFINED 1 +#define XED_REG_CLASS_GPR8_DEFINED 1 +#define XED_REG_CLASS_IP_DEFINED 1 +#define XED_REG_CLASS_MASK_DEFINED 1 +#define XED_REG_CLASS_MMX_DEFINED 1 +#define XED_REG_CLASS_MSR_DEFINED 1 +#define XED_REG_CLASS_MXCSR_DEFINED 1 +#define XED_REG_CLASS_PSEUDO_DEFINED 1 +#define XED_REG_CLASS_PSEUDOX87_DEFINED 1 +#define XED_REG_CLASS_SR_DEFINED 1 +#define XED_REG_CLASS_TMP_DEFINED 1 +#define XED_REG_CLASS_TREG_DEFINED 1 +#define XED_REG_CLASS_UIF_DEFINED 1 +#define XED_REG_CLASS_X87_DEFINED 1 +#define XED_REG_CLASS_XCR_DEFINED 1 +#define XED_REG_CLASS_XMM_DEFINED 1 +#define XED_REG_CLASS_YMM_DEFINED 1 +#define XED_REG_CLASS_ZMM_DEFINED 1 +#define XED_REG_CLASS_LAST_DEFINED 1 +typedef enum { + XED_REG_CLASS_INVALID, + XED_REG_CLASS_BNDCFG, + XED_REG_CLASS_BNDSTAT, + XED_REG_CLASS_BOUND, + XED_REG_CLASS_CR, + XED_REG_CLASS_DR, + XED_REG_CLASS_FLAGS, + XED_REG_CLASS_GPR, + XED_REG_CLASS_GPR16, + XED_REG_CLASS_GPR32, + XED_REG_CLASS_GPR64, + XED_REG_CLASS_GPR8, + XED_REG_CLASS_IP, + XED_REG_CLASS_MASK, + XED_REG_CLASS_MMX, + XED_REG_CLASS_MSR, + XED_REG_CLASS_MXCSR, + XED_REG_CLASS_PSEUDO, + XED_REG_CLASS_PSEUDOX87, + XED_REG_CLASS_SR, + XED_REG_CLASS_TMP, + XED_REG_CLASS_TREG, + XED_REG_CLASS_UIF, + XED_REG_CLASS_X87, + XED_REG_CLASS_XCR, + XED_REG_CLASS_XMM, + XED_REG_CLASS_YMM, + XED_REG_CLASS_ZMM, + XED_REG_CLASS_LAST +} xed_reg_class_enum_t; + +/// This converts strings to #xed_reg_class_enum_t types. +/// @param s A C-string. +/// @return #xed_reg_class_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_reg_class_enum_t str2xed_reg_class_enum_t(const char* s); +/// This converts strings to #xed_reg_class_enum_t types. +/// @param p An enumeration element of type xed_reg_class_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_reg_class_enum_t2str(const xed_reg_class_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_reg_class_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_reg_class_enum_t xed_reg_class_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-class.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-class.h new file mode 100644 index 0000000..edaf7ae --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-class.h @@ -0,0 +1,62 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-reg-class.h +/// + +#ifndef XED_REG_CLASS_H +# define XED_REG_CLASS_H + +#include "xed-types.h" +#include "xed-reg-enum.h" // a generated file +#include "xed-reg-class-enum.h" // a generated file + +/// Returns the register class of the given input register. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_class_enum_t xed_reg_class(xed_reg_enum_t r); + +/// Returns the specific width GPR reg class (like XED_REG_CLASS_GPR32 or +/// XED_REG_CLASS_GPR64) +/// for a given GPR register. Or XED_REG_INVALID if not a GPR. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_class_enum_t xed_gpr_reg_class(xed_reg_enum_t r); + +/// Returns the largest enclosing register for any kind of register; This +/// is mostly useful for GPRs. (64b mode assumed) +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_enum_t +xed_get_largest_enclosing_register(xed_reg_enum_t r); + +/// Returns the largest enclosing register for any kind of register; This +/// is mostly useful for GPRs in 32b mode. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_reg_enum_t +xed_get_largest_enclosing_register32(xed_reg_enum_t r); + +/// Returns the width, in bits, of the named register. 32b mode +///@ingroup REGINTFC +XED_DLL_EXPORT xed_uint32_t +xed_get_register_width_bits(xed_reg_enum_t r); + +/// Returns the width, in bits, of the named register. 64b mode. +///@ingroup REGINTFC +XED_DLL_EXPORT xed_uint32_t +xed_get_register_width_bits64(xed_reg_enum_t r); + +//////////////////////////////////////////////////////////////////////////// + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-enum.h new file mode 100644 index 0000000..4e22ade --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-reg-enum.h @@ -0,0 +1,726 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-reg-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_REG_ENUM_H) +# define XED_REG_ENUM_H +#include "xed-common-hdrs.h" +#define XED_REG_INVALID_DEFINED 1 +#define XED_REG_BNDCFGU_DEFINED 1 +#define XED_REG_BNDSTATUS_DEFINED 1 +#define XED_REG_BND0_DEFINED 1 +#define XED_REG_BND1_DEFINED 1 +#define XED_REG_BND2_DEFINED 1 +#define XED_REG_BND3_DEFINED 1 +#define XED_REG_CR0_DEFINED 1 +#define XED_REG_CR1_DEFINED 1 +#define XED_REG_CR2_DEFINED 1 +#define XED_REG_CR3_DEFINED 1 +#define XED_REG_CR4_DEFINED 1 +#define XED_REG_CR5_DEFINED 1 +#define XED_REG_CR6_DEFINED 1 +#define XED_REG_CR7_DEFINED 1 +#define XED_REG_CR8_DEFINED 1 +#define XED_REG_CR9_DEFINED 1 +#define XED_REG_CR10_DEFINED 1 +#define XED_REG_CR11_DEFINED 1 +#define XED_REG_CR12_DEFINED 1 +#define XED_REG_CR13_DEFINED 1 +#define XED_REG_CR14_DEFINED 1 +#define XED_REG_CR15_DEFINED 1 +#define XED_REG_DR0_DEFINED 1 +#define XED_REG_DR1_DEFINED 1 +#define XED_REG_DR2_DEFINED 1 +#define XED_REG_DR3_DEFINED 1 +#define XED_REG_DR4_DEFINED 1 +#define XED_REG_DR5_DEFINED 1 +#define XED_REG_DR6_DEFINED 1 +#define XED_REG_DR7_DEFINED 1 +#define XED_REG_FLAGS_DEFINED 1 +#define XED_REG_EFLAGS_DEFINED 1 +#define XED_REG_RFLAGS_DEFINED 1 +#define XED_REG_AX_DEFINED 1 +#define XED_REG_CX_DEFINED 1 +#define XED_REG_DX_DEFINED 1 +#define XED_REG_BX_DEFINED 1 +#define XED_REG_SP_DEFINED 1 +#define XED_REG_BP_DEFINED 1 +#define XED_REG_SI_DEFINED 1 +#define XED_REG_DI_DEFINED 1 +#define XED_REG_R8W_DEFINED 1 +#define XED_REG_R9W_DEFINED 1 +#define XED_REG_R10W_DEFINED 1 +#define XED_REG_R11W_DEFINED 1 +#define XED_REG_R12W_DEFINED 1 +#define XED_REG_R13W_DEFINED 1 +#define XED_REG_R14W_DEFINED 1 +#define XED_REG_R15W_DEFINED 1 +#define XED_REG_EAX_DEFINED 1 +#define XED_REG_ECX_DEFINED 1 +#define XED_REG_EDX_DEFINED 1 +#define XED_REG_EBX_DEFINED 1 +#define XED_REG_ESP_DEFINED 1 +#define XED_REG_EBP_DEFINED 1 +#define XED_REG_ESI_DEFINED 1 +#define XED_REG_EDI_DEFINED 1 +#define XED_REG_R8D_DEFINED 1 +#define XED_REG_R9D_DEFINED 1 +#define XED_REG_R10D_DEFINED 1 +#define XED_REG_R11D_DEFINED 1 +#define XED_REG_R12D_DEFINED 1 +#define XED_REG_R13D_DEFINED 1 +#define XED_REG_R14D_DEFINED 1 +#define XED_REG_R15D_DEFINED 1 +#define XED_REG_RAX_DEFINED 1 +#define XED_REG_RCX_DEFINED 1 +#define XED_REG_RDX_DEFINED 1 +#define XED_REG_RBX_DEFINED 1 +#define XED_REG_RSP_DEFINED 1 +#define XED_REG_RBP_DEFINED 1 +#define XED_REG_RSI_DEFINED 1 +#define XED_REG_RDI_DEFINED 1 +#define XED_REG_R8_DEFINED 1 +#define XED_REG_R9_DEFINED 1 +#define XED_REG_R10_DEFINED 1 +#define XED_REG_R11_DEFINED 1 +#define XED_REG_R12_DEFINED 1 +#define XED_REG_R13_DEFINED 1 +#define XED_REG_R14_DEFINED 1 +#define XED_REG_R15_DEFINED 1 +#define XED_REG_AL_DEFINED 1 +#define XED_REG_CL_DEFINED 1 +#define XED_REG_DL_DEFINED 1 +#define XED_REG_BL_DEFINED 1 +#define XED_REG_SPL_DEFINED 1 +#define XED_REG_BPL_DEFINED 1 +#define XED_REG_SIL_DEFINED 1 +#define XED_REG_DIL_DEFINED 1 +#define XED_REG_R8B_DEFINED 1 +#define XED_REG_R9B_DEFINED 1 +#define XED_REG_R10B_DEFINED 1 +#define XED_REG_R11B_DEFINED 1 +#define XED_REG_R12B_DEFINED 1 +#define XED_REG_R13B_DEFINED 1 +#define XED_REG_R14B_DEFINED 1 +#define XED_REG_R15B_DEFINED 1 +#define XED_REG_AH_DEFINED 1 +#define XED_REG_CH_DEFINED 1 +#define XED_REG_DH_DEFINED 1 +#define XED_REG_BH_DEFINED 1 +#define XED_REG_ERROR_DEFINED 1 +#define XED_REG_RIP_DEFINED 1 +#define XED_REG_EIP_DEFINED 1 +#define XED_REG_IP_DEFINED 1 +#define XED_REG_K0_DEFINED 1 +#define XED_REG_K1_DEFINED 1 +#define XED_REG_K2_DEFINED 1 +#define XED_REG_K3_DEFINED 1 +#define XED_REG_K4_DEFINED 1 +#define XED_REG_K5_DEFINED 1 +#define XED_REG_K6_DEFINED 1 +#define XED_REG_K7_DEFINED 1 +#define XED_REG_MMX0_DEFINED 1 +#define XED_REG_MMX1_DEFINED 1 +#define XED_REG_MMX2_DEFINED 1 +#define XED_REG_MMX3_DEFINED 1 +#define XED_REG_MMX4_DEFINED 1 +#define XED_REG_MMX5_DEFINED 1 +#define XED_REG_MMX6_DEFINED 1 +#define XED_REG_MMX7_DEFINED 1 +#define XED_REG_SSP_DEFINED 1 +#define XED_REG_IA32_U_CET_DEFINED 1 +#define XED_REG_MXCSR_DEFINED 1 +#define XED_REG_STACKPUSH_DEFINED 1 +#define XED_REG_STACKPOP_DEFINED 1 +#define XED_REG_GDTR_DEFINED 1 +#define XED_REG_LDTR_DEFINED 1 +#define XED_REG_IDTR_DEFINED 1 +#define XED_REG_TR_DEFINED 1 +#define XED_REG_TSC_DEFINED 1 +#define XED_REG_TSCAUX_DEFINED 1 +#define XED_REG_MSRS_DEFINED 1 +#define XED_REG_FSBASE_DEFINED 1 +#define XED_REG_GSBASE_DEFINED 1 +#define XED_REG_TILECONFIG_DEFINED 1 +#define XED_REG_X87CONTROL_DEFINED 1 +#define XED_REG_X87STATUS_DEFINED 1 +#define XED_REG_X87TAG_DEFINED 1 +#define XED_REG_X87PUSH_DEFINED 1 +#define XED_REG_X87POP_DEFINED 1 +#define XED_REG_X87POP2_DEFINED 1 +#define XED_REG_X87OPCODE_DEFINED 1 +#define XED_REG_X87LASTCS_DEFINED 1 +#define XED_REG_X87LASTIP_DEFINED 1 +#define XED_REG_X87LASTDS_DEFINED 1 +#define XED_REG_X87LASTDP_DEFINED 1 +#define XED_REG_ES_DEFINED 1 +#define XED_REG_CS_DEFINED 1 +#define XED_REG_SS_DEFINED 1 +#define XED_REG_DS_DEFINED 1 +#define XED_REG_FS_DEFINED 1 +#define XED_REG_GS_DEFINED 1 +#define XED_REG_TMP0_DEFINED 1 +#define XED_REG_TMP1_DEFINED 1 +#define XED_REG_TMP2_DEFINED 1 +#define XED_REG_TMP3_DEFINED 1 +#define XED_REG_TMP4_DEFINED 1 +#define XED_REG_TMP5_DEFINED 1 +#define XED_REG_TMP6_DEFINED 1 +#define XED_REG_TMP7_DEFINED 1 +#define XED_REG_TMP8_DEFINED 1 +#define XED_REG_TMP9_DEFINED 1 +#define XED_REG_TMP10_DEFINED 1 +#define XED_REG_TMP11_DEFINED 1 +#define XED_REG_TMP12_DEFINED 1 +#define XED_REG_TMP13_DEFINED 1 +#define XED_REG_TMP14_DEFINED 1 +#define XED_REG_TMP15_DEFINED 1 +#define XED_REG_TMM0_DEFINED 1 +#define XED_REG_TMM1_DEFINED 1 +#define XED_REG_TMM2_DEFINED 1 +#define XED_REG_TMM3_DEFINED 1 +#define XED_REG_TMM4_DEFINED 1 +#define XED_REG_TMM5_DEFINED 1 +#define XED_REG_TMM6_DEFINED 1 +#define XED_REG_TMM7_DEFINED 1 +#define XED_REG_UIF_DEFINED 1 +#define XED_REG_ST0_DEFINED 1 +#define XED_REG_ST1_DEFINED 1 +#define XED_REG_ST2_DEFINED 1 +#define XED_REG_ST3_DEFINED 1 +#define XED_REG_ST4_DEFINED 1 +#define XED_REG_ST5_DEFINED 1 +#define XED_REG_ST6_DEFINED 1 +#define XED_REG_ST7_DEFINED 1 +#define XED_REG_XCR0_DEFINED 1 +#define XED_REG_XMM0_DEFINED 1 +#define XED_REG_XMM1_DEFINED 1 +#define XED_REG_XMM2_DEFINED 1 +#define XED_REG_XMM3_DEFINED 1 +#define XED_REG_XMM4_DEFINED 1 +#define XED_REG_XMM5_DEFINED 1 +#define XED_REG_XMM6_DEFINED 1 +#define XED_REG_XMM7_DEFINED 1 +#define XED_REG_XMM8_DEFINED 1 +#define XED_REG_XMM9_DEFINED 1 +#define XED_REG_XMM10_DEFINED 1 +#define XED_REG_XMM11_DEFINED 1 +#define XED_REG_XMM12_DEFINED 1 +#define XED_REG_XMM13_DEFINED 1 +#define XED_REG_XMM14_DEFINED 1 +#define XED_REG_XMM15_DEFINED 1 +#define XED_REG_XMM16_DEFINED 1 +#define XED_REG_XMM17_DEFINED 1 +#define XED_REG_XMM18_DEFINED 1 +#define XED_REG_XMM19_DEFINED 1 +#define XED_REG_XMM20_DEFINED 1 +#define XED_REG_XMM21_DEFINED 1 +#define XED_REG_XMM22_DEFINED 1 +#define XED_REG_XMM23_DEFINED 1 +#define XED_REG_XMM24_DEFINED 1 +#define XED_REG_XMM25_DEFINED 1 +#define XED_REG_XMM26_DEFINED 1 +#define XED_REG_XMM27_DEFINED 1 +#define XED_REG_XMM28_DEFINED 1 +#define XED_REG_XMM29_DEFINED 1 +#define XED_REG_XMM30_DEFINED 1 +#define XED_REG_XMM31_DEFINED 1 +#define XED_REG_YMM0_DEFINED 1 +#define XED_REG_YMM1_DEFINED 1 +#define XED_REG_YMM2_DEFINED 1 +#define XED_REG_YMM3_DEFINED 1 +#define XED_REG_YMM4_DEFINED 1 +#define XED_REG_YMM5_DEFINED 1 +#define XED_REG_YMM6_DEFINED 1 +#define XED_REG_YMM7_DEFINED 1 +#define XED_REG_YMM8_DEFINED 1 +#define XED_REG_YMM9_DEFINED 1 +#define XED_REG_YMM10_DEFINED 1 +#define XED_REG_YMM11_DEFINED 1 +#define XED_REG_YMM12_DEFINED 1 +#define XED_REG_YMM13_DEFINED 1 +#define XED_REG_YMM14_DEFINED 1 +#define XED_REG_YMM15_DEFINED 1 +#define XED_REG_YMM16_DEFINED 1 +#define XED_REG_YMM17_DEFINED 1 +#define XED_REG_YMM18_DEFINED 1 +#define XED_REG_YMM19_DEFINED 1 +#define XED_REG_YMM20_DEFINED 1 +#define XED_REG_YMM21_DEFINED 1 +#define XED_REG_YMM22_DEFINED 1 +#define XED_REG_YMM23_DEFINED 1 +#define XED_REG_YMM24_DEFINED 1 +#define XED_REG_YMM25_DEFINED 1 +#define XED_REG_YMM26_DEFINED 1 +#define XED_REG_YMM27_DEFINED 1 +#define XED_REG_YMM28_DEFINED 1 +#define XED_REG_YMM29_DEFINED 1 +#define XED_REG_YMM30_DEFINED 1 +#define XED_REG_YMM31_DEFINED 1 +#define XED_REG_ZMM0_DEFINED 1 +#define XED_REG_ZMM1_DEFINED 1 +#define XED_REG_ZMM2_DEFINED 1 +#define XED_REG_ZMM3_DEFINED 1 +#define XED_REG_ZMM4_DEFINED 1 +#define XED_REG_ZMM5_DEFINED 1 +#define XED_REG_ZMM6_DEFINED 1 +#define XED_REG_ZMM7_DEFINED 1 +#define XED_REG_ZMM8_DEFINED 1 +#define XED_REG_ZMM9_DEFINED 1 +#define XED_REG_ZMM10_DEFINED 1 +#define XED_REG_ZMM11_DEFINED 1 +#define XED_REG_ZMM12_DEFINED 1 +#define XED_REG_ZMM13_DEFINED 1 +#define XED_REG_ZMM14_DEFINED 1 +#define XED_REG_ZMM15_DEFINED 1 +#define XED_REG_ZMM16_DEFINED 1 +#define XED_REG_ZMM17_DEFINED 1 +#define XED_REG_ZMM18_DEFINED 1 +#define XED_REG_ZMM19_DEFINED 1 +#define XED_REG_ZMM20_DEFINED 1 +#define XED_REG_ZMM21_DEFINED 1 +#define XED_REG_ZMM22_DEFINED 1 +#define XED_REG_ZMM23_DEFINED 1 +#define XED_REG_ZMM24_DEFINED 1 +#define XED_REG_ZMM25_DEFINED 1 +#define XED_REG_ZMM26_DEFINED 1 +#define XED_REG_ZMM27_DEFINED 1 +#define XED_REG_ZMM28_DEFINED 1 +#define XED_REG_ZMM29_DEFINED 1 +#define XED_REG_ZMM30_DEFINED 1 +#define XED_REG_ZMM31_DEFINED 1 +#define XED_REG_LAST_DEFINED 1 +#define XED_REG_BNDCFG_FIRST_DEFINED 1 +#define XED_REG_BNDCFG_LAST_DEFINED 1 +#define XED_REG_BNDSTAT_FIRST_DEFINED 1 +#define XED_REG_BNDSTAT_LAST_DEFINED 1 +#define XED_REG_BOUND_FIRST_DEFINED 1 +#define XED_REG_BOUND_LAST_DEFINED 1 +#define XED_REG_CR_FIRST_DEFINED 1 +#define XED_REG_CR_LAST_DEFINED 1 +#define XED_REG_DR_FIRST_DEFINED 1 +#define XED_REG_DR_LAST_DEFINED 1 +#define XED_REG_FLAGS_FIRST_DEFINED 1 +#define XED_REG_FLAGS_LAST_DEFINED 1 +#define XED_REG_GPR16_FIRST_DEFINED 1 +#define XED_REG_GPR16_LAST_DEFINED 1 +#define XED_REG_GPR32_FIRST_DEFINED 1 +#define XED_REG_GPR32_LAST_DEFINED 1 +#define XED_REG_GPR64_FIRST_DEFINED 1 +#define XED_REG_GPR64_LAST_DEFINED 1 +#define XED_REG_GPR8_FIRST_DEFINED 1 +#define XED_REG_GPR8_LAST_DEFINED 1 +#define XED_REG_GPR8h_FIRST_DEFINED 1 +#define XED_REG_GPR8h_LAST_DEFINED 1 +#define XED_REG_INVALID_FIRST_DEFINED 1 +#define XED_REG_INVALID_LAST_DEFINED 1 +#define XED_REG_IP_FIRST_DEFINED 1 +#define XED_REG_IP_LAST_DEFINED 1 +#define XED_REG_MASK_FIRST_DEFINED 1 +#define XED_REG_MASK_LAST_DEFINED 1 +#define XED_REG_MMX_FIRST_DEFINED 1 +#define XED_REG_MMX_LAST_DEFINED 1 +#define XED_REG_MSR_FIRST_DEFINED 1 +#define XED_REG_MSR_LAST_DEFINED 1 +#define XED_REG_MXCSR_FIRST_DEFINED 1 +#define XED_REG_MXCSR_LAST_DEFINED 1 +#define XED_REG_PSEUDO_FIRST_DEFINED 1 +#define XED_REG_PSEUDO_LAST_DEFINED 1 +#define XED_REG_PSEUDOX87_FIRST_DEFINED 1 +#define XED_REG_PSEUDOX87_LAST_DEFINED 1 +#define XED_REG_SR_FIRST_DEFINED 1 +#define XED_REG_SR_LAST_DEFINED 1 +#define XED_REG_TMP_FIRST_DEFINED 1 +#define XED_REG_TMP_LAST_DEFINED 1 +#define XED_REG_TREG_FIRST_DEFINED 1 +#define XED_REG_TREG_LAST_DEFINED 1 +#define XED_REG_UIF_FIRST_DEFINED 1 +#define XED_REG_UIF_LAST_DEFINED 1 +#define XED_REG_X87_FIRST_DEFINED 1 +#define XED_REG_X87_LAST_DEFINED 1 +#define XED_REG_XCR_FIRST_DEFINED 1 +#define XED_REG_XCR_LAST_DEFINED 1 +#define XED_REG_XMM_FIRST_DEFINED 1 +#define XED_REG_XMM_LAST_DEFINED 1 +#define XED_REG_YMM_FIRST_DEFINED 1 +#define XED_REG_YMM_LAST_DEFINED 1 +#define XED_REG_ZMM_FIRST_DEFINED 1 +#define XED_REG_ZMM_LAST_DEFINED 1 +typedef enum { + XED_REG_INVALID, + XED_REG_BNDCFGU, + XED_REG_BNDSTATUS, + XED_REG_BND0, + XED_REG_BND1, + XED_REG_BND2, + XED_REG_BND3, + XED_REG_CR0, + XED_REG_CR1, + XED_REG_CR2, + XED_REG_CR3, + XED_REG_CR4, + XED_REG_CR5, + XED_REG_CR6, + XED_REG_CR7, + XED_REG_CR8, + XED_REG_CR9, + XED_REG_CR10, + XED_REG_CR11, + XED_REG_CR12, + XED_REG_CR13, + XED_REG_CR14, + XED_REG_CR15, + XED_REG_DR0, + XED_REG_DR1, + XED_REG_DR2, + XED_REG_DR3, + XED_REG_DR4, + XED_REG_DR5, + XED_REG_DR6, + XED_REG_DR7, + XED_REG_FLAGS, + XED_REG_EFLAGS, + XED_REG_RFLAGS, + XED_REG_AX, + XED_REG_CX, + XED_REG_DX, + XED_REG_BX, + XED_REG_SP, + XED_REG_BP, + XED_REG_SI, + XED_REG_DI, + XED_REG_R8W, + XED_REG_R9W, + XED_REG_R10W, + XED_REG_R11W, + XED_REG_R12W, + XED_REG_R13W, + XED_REG_R14W, + XED_REG_R15W, + XED_REG_EAX, + XED_REG_ECX, + XED_REG_EDX, + XED_REG_EBX, + XED_REG_ESP, + XED_REG_EBP, + XED_REG_ESI, + XED_REG_EDI, + XED_REG_R8D, + XED_REG_R9D, + XED_REG_R10D, + XED_REG_R11D, + XED_REG_R12D, + XED_REG_R13D, + XED_REG_R14D, + XED_REG_R15D, + XED_REG_RAX, + XED_REG_RCX, + XED_REG_RDX, + XED_REG_RBX, + XED_REG_RSP, + XED_REG_RBP, + XED_REG_RSI, + XED_REG_RDI, + XED_REG_R8, + XED_REG_R9, + XED_REG_R10, + XED_REG_R11, + XED_REG_R12, + XED_REG_R13, + XED_REG_R14, + XED_REG_R15, + XED_REG_AL, + XED_REG_CL, + XED_REG_DL, + XED_REG_BL, + XED_REG_SPL, + XED_REG_BPL, + XED_REG_SIL, + XED_REG_DIL, + XED_REG_R8B, + XED_REG_R9B, + XED_REG_R10B, + XED_REG_R11B, + XED_REG_R12B, + XED_REG_R13B, + XED_REG_R14B, + XED_REG_R15B, + XED_REG_AH, + XED_REG_CH, + XED_REG_DH, + XED_REG_BH, + XED_REG_ERROR, + XED_REG_RIP, + XED_REG_EIP, + XED_REG_IP, + XED_REG_K0, + XED_REG_K1, + XED_REG_K2, + XED_REG_K3, + XED_REG_K4, + XED_REG_K5, + XED_REG_K6, + XED_REG_K7, + XED_REG_MMX0, + XED_REG_MMX1, + XED_REG_MMX2, + XED_REG_MMX3, + XED_REG_MMX4, + XED_REG_MMX5, + XED_REG_MMX6, + XED_REG_MMX7, + XED_REG_SSP, + XED_REG_IA32_U_CET, + XED_REG_MXCSR, + XED_REG_STACKPUSH, + XED_REG_STACKPOP, + XED_REG_GDTR, + XED_REG_LDTR, + XED_REG_IDTR, + XED_REG_TR, + XED_REG_TSC, + XED_REG_TSCAUX, + XED_REG_MSRS, + XED_REG_FSBASE, + XED_REG_GSBASE, + XED_REG_TILECONFIG, + XED_REG_X87CONTROL, + XED_REG_X87STATUS, + XED_REG_X87TAG, + XED_REG_X87PUSH, + XED_REG_X87POP, + XED_REG_X87POP2, + XED_REG_X87OPCODE, + XED_REG_X87LASTCS, + XED_REG_X87LASTIP, + XED_REG_X87LASTDS, + XED_REG_X87LASTDP, + XED_REG_ES, + XED_REG_CS, + XED_REG_SS, + XED_REG_DS, + XED_REG_FS, + XED_REG_GS, + XED_REG_TMP0, + XED_REG_TMP1, + XED_REG_TMP2, + XED_REG_TMP3, + XED_REG_TMP4, + XED_REG_TMP5, + XED_REG_TMP6, + XED_REG_TMP7, + XED_REG_TMP8, + XED_REG_TMP9, + XED_REG_TMP10, + XED_REG_TMP11, + XED_REG_TMP12, + XED_REG_TMP13, + XED_REG_TMP14, + XED_REG_TMP15, + XED_REG_TMM0, + XED_REG_TMM1, + XED_REG_TMM2, + XED_REG_TMM3, + XED_REG_TMM4, + XED_REG_TMM5, + XED_REG_TMM6, + XED_REG_TMM7, + XED_REG_UIF, + XED_REG_ST0, + XED_REG_ST1, + XED_REG_ST2, + XED_REG_ST3, + XED_REG_ST4, + XED_REG_ST5, + XED_REG_ST6, + XED_REG_ST7, + XED_REG_XCR0, + XED_REG_XMM0, + XED_REG_XMM1, + XED_REG_XMM2, + XED_REG_XMM3, + XED_REG_XMM4, + XED_REG_XMM5, + XED_REG_XMM6, + XED_REG_XMM7, + XED_REG_XMM8, + XED_REG_XMM9, + XED_REG_XMM10, + XED_REG_XMM11, + XED_REG_XMM12, + XED_REG_XMM13, + XED_REG_XMM14, + XED_REG_XMM15, + XED_REG_XMM16, + XED_REG_XMM17, + XED_REG_XMM18, + XED_REG_XMM19, + XED_REG_XMM20, + XED_REG_XMM21, + XED_REG_XMM22, + XED_REG_XMM23, + XED_REG_XMM24, + XED_REG_XMM25, + XED_REG_XMM26, + XED_REG_XMM27, + XED_REG_XMM28, + XED_REG_XMM29, + XED_REG_XMM30, + XED_REG_XMM31, + XED_REG_YMM0, + XED_REG_YMM1, + XED_REG_YMM2, + XED_REG_YMM3, + XED_REG_YMM4, + XED_REG_YMM5, + XED_REG_YMM6, + XED_REG_YMM7, + XED_REG_YMM8, + XED_REG_YMM9, + XED_REG_YMM10, + XED_REG_YMM11, + XED_REG_YMM12, + XED_REG_YMM13, + XED_REG_YMM14, + XED_REG_YMM15, + XED_REG_YMM16, + XED_REG_YMM17, + XED_REG_YMM18, + XED_REG_YMM19, + XED_REG_YMM20, + XED_REG_YMM21, + XED_REG_YMM22, + XED_REG_YMM23, + XED_REG_YMM24, + XED_REG_YMM25, + XED_REG_YMM26, + XED_REG_YMM27, + XED_REG_YMM28, + XED_REG_YMM29, + XED_REG_YMM30, + XED_REG_YMM31, + XED_REG_ZMM0, + XED_REG_ZMM1, + XED_REG_ZMM2, + XED_REG_ZMM3, + XED_REG_ZMM4, + XED_REG_ZMM5, + XED_REG_ZMM6, + XED_REG_ZMM7, + XED_REG_ZMM8, + XED_REG_ZMM9, + XED_REG_ZMM10, + XED_REG_ZMM11, + XED_REG_ZMM12, + XED_REG_ZMM13, + XED_REG_ZMM14, + XED_REG_ZMM15, + XED_REG_ZMM16, + XED_REG_ZMM17, + XED_REG_ZMM18, + XED_REG_ZMM19, + XED_REG_ZMM20, + XED_REG_ZMM21, + XED_REG_ZMM22, + XED_REG_ZMM23, + XED_REG_ZMM24, + XED_REG_ZMM25, + XED_REG_ZMM26, + XED_REG_ZMM27, + XED_REG_ZMM28, + XED_REG_ZMM29, + XED_REG_ZMM30, + XED_REG_ZMM31, + XED_REG_LAST, + XED_REG_BNDCFG_FIRST=XED_REG_BNDCFGU, //< PSEUDO + XED_REG_BNDCFG_LAST=XED_REG_BNDCFGU, //mmode=arg_mmode; + p->stack_addr_width=arg_stack_addr_width; + (void) arg_ignored; //pacify compiler unused arg warning +} + +/// Constructor. +/// The mode, and addresses widths are enumerations that specify the number +/// of bits. In 64b mode (#XED_MACHINE_MODE_LONG_64) the address width and +/// stack address widths are 64b (#XED_ADDRESS_WIDTH_64b). In other machine +/// modes, you must specify valid addressing widths. +/// +/// @param p the pointer to the #xed_state_t type +/// @param arg_mmode the machine mode of type #xed_machine_mode_enum_t +/// @param arg_stack_addr_width the stack address width of type #xed_address_width_enum_t (only required if not the mode is not #XED_MACHINE_MODE_LONG_64) +/// @ingroup INIT +static XED_INLINE void xed_state_init2(xed_state_t* p, + xed_machine_mode_enum_t arg_mmode, + xed_address_width_enum_t arg_stack_addr_width) { + p->mmode=arg_mmode; + p->stack_addr_width=arg_stack_addr_width; +} + +/// clear the xed_state_t +/// @ingroup INIT +static XED_INLINE void xed_state_zero(xed_state_t* p) { + p->mmode= XED_MACHINE_MODE_INVALID; + p->stack_addr_width=XED_ADDRESS_WIDTH_INVALID; +} + +//@} + +/// @name Machine mode +//@{ +/// return the machine mode +/// @ingroup INIT +static XED_INLINE xed_machine_mode_enum_t xed_state_get_machine_mode(const xed_state_t* p) { + return p->mmode; +} + + +/// true iff the machine is in LONG_64 mode +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_long64_mode(const xed_state_t* p) { + return xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LONG_64; +} + +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_real_mode(const xed_state_t* p) { + xed_machine_mode_enum_t mmode = xed_state_get_machine_mode(p); + return ( mmode == XED_MACHINE_MODE_REAL_16 || + mmode == XED_MACHINE_MODE_REAL_32 ); +} + +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_mode_width_16(const xed_state_t* p) { + return (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LEGACY_16) || + (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LONG_COMPAT_16); +} + +/// @ingroup INIT +static XED_INLINE xed_bool_t xed_state_mode_width_32(const xed_state_t* p) { + return (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LEGACY_32) || + (xed_state_get_machine_mode(p) == XED_MACHINE_MODE_LONG_COMPAT_32); +} + + +/// Set the machine mode which corresponds to the default data operand size +/// @ingroup INIT +static XED_INLINE void xed_state_set_machine_mode( xed_state_t* p, + xed_machine_mode_enum_t arg_mode) { + p->mmode = arg_mode; +} +//@} + +/// @name Address width +//@{ + +/// return the address width +/// @ingroup INIT +static XED_INLINE xed_address_width_enum_t +xed_state_get_address_width(const xed_state_t* p) +{ + switch(xed_state_get_machine_mode(p)) { + case XED_MACHINE_MODE_LONG_64: + return XED_ADDRESS_WIDTH_64b; + + case XED_MACHINE_MODE_REAL_16: + case XED_MACHINE_MODE_REAL_32: + /* should be 20b... but if you are working w/real mode then you're + going to have to deal with somehow. Could easily make this be + 20b if anyone cares. */ + return XED_ADDRESS_WIDTH_32b; + + case XED_MACHINE_MODE_LEGACY_32: + case XED_MACHINE_MODE_LONG_COMPAT_32: + return XED_ADDRESS_WIDTH_32b; + case XED_MACHINE_MODE_LEGACY_16: + case XED_MACHINE_MODE_LONG_COMPAT_16: + return XED_ADDRESS_WIDTH_16b; + default: + return XED_ADDRESS_WIDTH_INVALID; + } +} + +//@} + +/// @name Stack address width +//@{ +/// set the STACK address width +/// @ingroup INIT +static XED_INLINE void +xed_state_set_stack_address_width(xed_state_t* p, + xed_address_width_enum_t arg_addr_width) +{ + p->stack_addr_width = arg_addr_width; +} + + +/// Return the STACK address width +/// @ingroup INIT +static XED_INLINE xed_address_width_enum_t xed_state_get_stack_address_width(const xed_state_t* p) { + return p->stack_addr_width; +} +//@} + +/// @ingroup INIT +XED_DLL_EXPORT int xed_state_print(const xed_state_t* p, char* buf, int buflen); + +#endif + diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-syntax-enum.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-syntax-enum.h new file mode 100644 index 0000000..42cb930 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-syntax-enum.h @@ -0,0 +1,54 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-syntax-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_SYNTAX_ENUM_H) +# define XED_SYNTAX_ENUM_H +#include "xed-common-hdrs.h" +#define XED_SYNTAX_INVALID_DEFINED 1 +#define XED_SYNTAX_XED_DEFINED 1 +#define XED_SYNTAX_ATT_DEFINED 1 +#define XED_SYNTAX_INTEL_DEFINED 1 +#define XED_SYNTAX_LAST_DEFINED 1 +typedef enum { + XED_SYNTAX_INVALID, + XED_SYNTAX_XED, ///< XED disassembly syntax + XED_SYNTAX_ATT, ///< ATT SYSV disassembly syntax + XED_SYNTAX_INTEL, ///< Intel disassembly syntax + XED_SYNTAX_LAST +} xed_syntax_enum_t; + +/// This converts strings to #xed_syntax_enum_t types. +/// @param s A C-string. +/// @return #xed_syntax_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_syntax_enum_t str2xed_syntax_enum_t(const char* s); +/// This converts strings to #xed_syntax_enum_t types. +/// @param p An enumeration element of type xed_syntax_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_syntax_enum_t2str(const xed_syntax_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_syntax_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_syntax_enum_t xed_syntax_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-types.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-types.h new file mode 100644 index 0000000..46483e4 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-types.h @@ -0,0 +1,131 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-types.h +/// + + +#ifndef XED_TYPES_H +# define XED_TYPES_H + +//////////////////////////////////////////////////////////////////////////// + +#include "xed-common-hdrs.h" + +#if defined(__GNUC__) || defined(__ICC) +# include +# define xed_uint8_t uint8_t +# define xed_uint16_t uint16_t +# define xed_uint32_t uint32_t +# define xed_uint64_t uint64_t +# define xed_int8_t int8_t +# define xed_int16_t int16_t +# define xed_int32_t int32_t +# define xed_int64_t int64_t +#elif defined(_WIN32) +# define xed_uint8_t unsigned __int8 +# define xed_uint16_t unsigned __int16 +# define xed_uint32_t unsigned __int32 +# define xed_uint64_t unsigned __int64 +# define xed_int8_t __int8 +# define xed_int16_t __int16 +# define xed_int32_t __int32 +# define xed_int64_t __int64 +#else +# error "XED types unsupported platform? Need windows, gcc, or icc." +#endif + +typedef unsigned int xed_uint_t; +typedef int xed_int_t; +typedef unsigned int xed_bits_t; +typedef unsigned int xed_bool_t; + +#if defined(__LP64__) || defined (_M_X64) +typedef xed_uint64_t xed_addr_t; +#else +typedef xed_uint32_t xed_addr_t; +#endif + + +typedef union { + xed_uint8_t byte[2]; + xed_int8_t s_byte[2]; + + struct { + xed_uint8_t b0; /*low 8 bits*/ + xed_uint8_t b1; /*high 8 bits*/ + } b; + xed_int16_t i16; + xed_uint16_t u16; +} xed_union16_t ; + +typedef union { + xed_uint8_t byte[4]; + xed_uint16_t word[2]; + xed_int8_t s_byte[4]; + xed_int16_t s_word[2]; + + struct { + xed_uint8_t b0; /*low 8 bits*/ + xed_uint8_t b1; + xed_uint8_t b2; + xed_uint8_t b3; /*high 8 bits*/ + } b; + + struct { + xed_uint16_t w0; /*low 16 bits*/ + xed_uint16_t w1; /*high 16 bits*/ + } w; + xed_int32_t i32; + xed_uint32_t u32; +} xed_union32_t ; + +typedef union { + xed_uint8_t byte[8]; + xed_uint16_t word[4]; + xed_uint32_t dword[2]; + xed_int8_t s_byte[8]; + xed_int16_t s_word[4]; + xed_int32_t s_dword[2]; + + struct { + xed_uint8_t b0; /*low 8 bits*/ + xed_uint8_t b1; + xed_uint8_t b2; + xed_uint8_t b3; + xed_uint8_t b4; + xed_uint8_t b5; + xed_uint8_t b6; + xed_uint8_t b7; /*high 8 bits*/ + } b; + + struct { + xed_uint16_t w0; /*low 16 bits*/ + xed_uint16_t w1; + xed_uint16_t w2; + xed_uint16_t w3; /*high 16 bits*/ + } w; + struct { + xed_uint32_t lo32; + xed_uint32_t hi32; + } s; + xed_uint64_t u64; + xed_int64_t i64; +} xed_union64_t ; + +//////////////////////////////////////////////////////////////////////////// +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-util.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-util.h new file mode 100644 index 0000000..9d36d64 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-util.h @@ -0,0 +1,254 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +/// @file xed-util.h +/// + + + +#ifndef XED_UTIL_H +# define XED_UTIL_H + +#include "xed-common-hdrs.h" +#include "xed-types.h" +#include "xed-portability.h" + + + +extern int xed_verbose; +#if defined(XED_MESSAGES) +# include +extern FILE* xed_log_file; +# define XED_EMIT_MESSAGES (xed_verbose >= 1) +# define XED_INFO_VERBOSE (xed_verbose >= 2) +# define XED_INFO2_VERBOSE (xed_verbose >= 3) +# define XED_VERBOSE (xed_verbose >= 4) +# define XED_MORE_VERBOSE (xed_verbose >= 5) +# define XED_VERY_VERBOSE (xed_verbose >= 6) +#else +# define XED_EMIT_MESSAGES (0) +# define XED_INFO_VERBOSE (0) +# define XED_INFO2_VERBOSE (0) +# define XED_VERBOSE (0) +# define XED_MORE_VERBOSE (0) +# define XED_VERY_VERBOSE (0) +#endif + +#if defined(__GNUC__) +# define XED_FUNCNAME __func__ +#else +# define XED_FUNCNAME "" +#endif + +#if defined(XED_MESSAGES) +#define XED2IMSG(x) \ + do { \ + if (XED_EMIT_MESSAGES) { \ + if (XED_VERY_VERBOSE) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + } \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + } while(0) + +#define XED2TMSG(x) \ + do { \ + if (XED_VERBOSE) { \ + if (XED_VERY_VERBOSE) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + } \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + } while(0) + +#define XED2VMSG(x) \ + do { \ + if (XED_VERY_VERBOSE) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + } while(0) + +// Example usage: +// XED2DIE((xed_log_file,"%s\n", msg)); + +#define XED2DIE(x) \ + do { \ + if (XED_EMIT_MESSAGES) { \ + fprintf(xed_log_file,"%s:%d:%s: ", \ + __FILE__, __LINE__, XED_FUNCNAME); \ + fprintf x; \ + fflush(xed_log_file); \ + } \ + xed_assert(0); \ + } while(0) + + + +#else +# define XED2IMSG(x) +# define XED2TMSG(x) +# define XED2VMSG(x) +# define XED2DIE(x) do { xed_assert(0); } while(0) +#endif + +#if defined(XED_ASSERTS) +# define xed_assert(x) do { if (( x )== 0) xed_internal_assert( #x, __FILE__, __LINE__); } while(0) +#else +# define xed_assert(x) do { } while(0) +#endif +XED_NORETURN XED_NOINLINE XED_DLL_EXPORT void xed_internal_assert(const char* s, const char* file, int line); + +typedef void (*xed_user_abort_function_t)(const char* msg, + const char* file, + int line, + void* other); + +/// @ingroup INIT +/// This is for registering a function to be called during XED's assert +/// processing. If you do not register an abort function, then the system's +/// abort function will be called. If your supplied function returns, then +/// abort() will still be called. +/// +/// @param fn This is a function pointer for a function that should handle the +/// assertion reporting. The function pointer points to a function that +/// takes 4 arguments: +/// (1) msg, the assertion message, +/// (2) file, the file name, +/// (3) line, the line number (as an integer), and +/// (4) other, a void pointer that is supplied as thei +/// 2nd argument to this registration. +/// @param other This is a void* that is passed back to your supplied function fn +/// as its 4th argument. It can be zero if you don't need this +/// feature. You can used this to convey whatever additional context +/// to your assertion handler (like FILE* pointers etc.). +/// +XED_DLL_EXPORT void xed_register_abort_function(xed_user_abort_function_t fn, + void* other); + + +XED_DLL_EXPORT int xed_itoa(char* buf, + xed_uint64_t f, + int buflen); + +/// defaults to lowercase +XED_DLL_EXPORT int xed_itoa_hex_zeros(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + xed_bool_t leading_zeros, + int buflen); + +/// defaults to lowercase +XED_DLL_EXPORT int xed_itoa_hex(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + int buflen); + +XED_DLL_EXPORT int xed_itoa_hex_ul(char* buf, + xed_uint64_t f, + xed_uint_t bits_to_print, + xed_bool_t leading_zeros, + int buflen, + xed_bool_t lowercase); + + +/// Set the FILE* for XED's log msgs. This takes a FILE* as a void* because +/// some software defines their own FILE* types creating conflicts. +XED_DLL_EXPORT void xed_set_log_file(void* o); + + +/// Set the verbosity level for XED +XED_DLL_EXPORT void xed_set_verbosity(int v); + +XED_DLL_EXPORT xed_int64_t xed_sign_extend32_64(xed_int32_t x); +XED_DLL_EXPORT xed_int64_t xed_sign_extend16_64(xed_int16_t x); +XED_DLL_EXPORT xed_int64_t xed_sign_extend8_64(xed_int8_t x); + +XED_DLL_EXPORT xed_int32_t xed_sign_extend16_32(xed_int16_t x); +XED_DLL_EXPORT xed_int32_t xed_sign_extend8_32(xed_int8_t x); + +XED_DLL_EXPORT xed_int16_t xed_sign_extend8_16(xed_int8_t x); + +///arbitrary sign extension from a qty of "bits" length to 32b +XED_DLL_EXPORT xed_int32_t xed_sign_extend_arbitrary_to_32(xed_uint32_t x, unsigned int bits); + +///arbitrary sign extension from a qty of "bits" length to 64b +XED_DLL_EXPORT xed_int64_t xed_sign_extend_arbitrary_to_64(xed_uint64_t x, unsigned int bits); + + +XED_DLL_EXPORT xed_uint64_t xed_zero_extend32_64(xed_uint32_t x); +XED_DLL_EXPORT xed_uint64_t xed_zero_extend16_64(xed_uint16_t x); +XED_DLL_EXPORT xed_uint64_t xed_zero_extend8_64(xed_uint8_t x); + +XED_DLL_EXPORT xed_uint32_t xed_zero_extend16_32(xed_uint16_t x); +XED_DLL_EXPORT xed_uint32_t xed_zero_extend8_32(xed_uint8_t x); + +XED_DLL_EXPORT xed_uint16_t xed_zero_extend8_16(xed_uint8_t x); + +#if defined(XED_LITTLE_ENDIAN_SWAPPING) +XED_DLL_EXPORT xed_int32_t +xed_little_endian_to_int32(xed_uint64_t x, unsigned int len); + +XED_DLL_EXPORT xed_int64_t +xed_little_endian_to_int64(xed_uint64_t x, unsigned int len); +XED_DLL_EXPORT xed_uint64_t +xed_little_endian_to_uint64(xed_uint64_t x, unsigned int len); + +XED_DLL_EXPORT xed_int64_t +xed_little_endian_hilo_to_int64(xed_uint32_t hi_le, xed_uint32_t lo_le, unsigned int len); +XED_DLL_EXPORT xed_uint64_t +xed_little_endian_hilo_to_uint64(xed_uint32_t hi_le, xed_uint32_t lo_le, unsigned int len); +#endif + +XED_DLL_EXPORT xed_uint8_t +xed_get_byte(xed_uint64_t x, unsigned int i, unsigned int len); + +static XED_INLINE xed_uint64_t xed_make_uint64(xed_uint32_t hi, xed_uint32_t lo) { + xed_union64_t y; + y.s.lo32= lo; + y.s.hi32= hi; + return y.u64; +} +static XED_INLINE xed_int64_t xed_make_int64(xed_uint32_t hi, xed_uint32_t lo) { + xed_union64_t y; + y.s.lo32= lo; + y.s.hi32= hi; + return y.i64; +} + +/// returns the number of bytes required to store the UNSIGNED number x +/// given a mask of legal lengths. For the legal_widths argument, bit 0 +/// implies 1 byte is a legal return width, bit 1 implies that 2 bytes is a +/// legal return width, bit 2 implies that 4 bytes is a legal return width. +/// This returns 8 (indicating 8B) if none of the provided legal widths +/// applies. +XED_DLL_EXPORT xed_uint_t xed_shortest_width_unsigned(xed_uint64_t x, xed_uint8_t legal_widths); + +/// returns the number of bytes required to store the SIGNED number x +/// given a mask of legal lengths. For the legal_widths argument, bit 0 implies 1 +/// byte is a legal return width, bit 1 implies that 2 bytes is a legal +/// return width, bit 2 implies that 4 bytes is a legal return width. This +/// returns 8 (indicating 8B) if none of the provided legal widths applies. +XED_DLL_EXPORT xed_uint_t xed_shortest_width_signed(xed_int64_t x, xed_uint8_t legal_widths); + +#endif diff --git a/CodeVirtualizer/build/obj/wkit/include/xed/xed-version.h b/CodeVirtualizer/build/obj/wkit/include/xed/xed-version.h new file mode 100644 index 0000000..25ff315 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/include/xed/xed-version.h @@ -0,0 +1,29 @@ +/* BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ + +#if !defined(XED_VERSION_H) +# define XED_VERSION_H +#include "xed-common-hdrs.h" + +///@ingroup INIT +/// Returns a string representing XED svn commit revision and time stamp. +XED_DLL_EXPORT char const* xed_get_version(void); +///@ingroup INIT +/// Returns a copyright string. +XED_DLL_EXPORT char const* xed_get_copyright(void); +#endif diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/__init__.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/__init__.py new file mode 100644 index 0000000..e52a8df --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/__init__.py @@ -0,0 +1,136 @@ +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +# __init__.py +# Mark Charney +"""This is mbuild: a simple portable dependence-based build-system +written in python. + +mbuild is a python-based build system very similar to scons with some +philosophical features of make. mbuild exposes the scan and build phases +allowing them to be repeated as necessary. Multiple DAGs can be +built, one during each scan phase. + +Conceptually there are 3 major components to mbuild: + - The environment L{env_t} + - The directed acyclic graph L{dag_t} + - The work queue L{work_queue_t} + +Using the environment L{env_t} you customize your build configuration +and construct names for your source files, object files, executables, +etc. The environment contains builder methods that create L{plan_t} +objects. There are builders for C, C++, static and dynamic libraries, +assembly files and linking programs. The environment and builders +support string substitution. + +The L{plan_t} objects are passed to the L{dag_t} which stores the +dependences that order execution. The L{plan_t} objects describe work +that needs to be done. Plans typically contain a command line strings +(with all substitutions done), but can also be python functions that +will be executed during the build. + +Using the L{plan_t} objects, the L{dag_t} creates L{command_t} +objects that are passed to the L{work_queue_t} to ultimately build the +target or targets. + +Your build file can have multiple environments, DAGS and work queues. + + +Using the environment dictionary +================================ + +You can bind or augmenting environment variables from the command +line. For example, one can say C{build_cpu=ia32} on an x86-64 system +to change the default compilation behavior. Similarly, one can say +C{CXXFLAGS+=-g} to add the C{-g} flag to the existing C{CXXFLAGS} +variable. + +Dynamic substitution is also used. Patterns of the form %(I{string})s +will substitute I{string} dynamically before it is used. The +expansion can happen directly from the environment and is +recursive. The expansion can also use dictionaries that are variables +in the environment. A dictionary in the environment is really a tuple +of the key-variable and the dictionary itself. + +For example:: + + env['opt_flag'] = ( 'opt', {'noopt':'', + '0':'%(OPTOPT)s0', + '1':'%(OPTOPT)s1', + '2':'%(OPTOPT)s2', + '3':'%(OPTOPT)s3', + '4':'%(OPTOPT)s4'} ) + + env['OPTOPT'] = ( 'compiler', { 'gnu':'-O', + 'ms':'/O'}) + + + env['CXXFLAGS'] += ' %(opt_flag)s' + +The C{OPTOPT} variable depends on C{env['compiler']}. +If C{env['compiler']='gnu'} then C{env['OPTOPT']} expands to C{-O}. +If C{env['compiler']='ms'} then C{env['OPTOPT']} expands to C{/O}. + +If the C{opt} variable is set "C{opt=3}" on the command line, or equivalently +if C{env['opt']='3'} is +set in the script, +then if the C{env['compiler']='gnu'} in the environment at the time of expansion, +then the flag in the +C{CXXFLAGS} will be C{-O3}. If C{env['compiler']='ms'} at the time of expansion, +then the optimiation +flag would be C{/O3}. If C{opt=noopt} (on the command line) then there will be no +optimization flag in the C{CXXFLAGS}. + + +Introspection +============= + +The L{command_t} that are executed during the build have their output +(stdout/stderr) stored in the L{dag_t}. After a build it is possible +to collect the commands using the L{dag_t.results} function and analyze the +output. This is very handy for test and validation suites. +""" + +from .base import * +from .dag import * +from .work_queue import * +from .env import * +from .util import * +from .plan import * +from .arar import * +from .doxygen import doxygen_run, doxygen_args, doxygen_env +from .header_tag import * + +__all__ = [ 'base', + 'dag', + 'work_queue', + 'env', + 'util', + 'plan', + 'msvs', + 'arar', + 'doxygen', + 'dfs', + 'header_tag' ] + + +import time +def mbuild_exit(): + """mbuild's exit function""" + +import atexit +atexit.register(mbuild_exit) diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/arar.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/arar.py new file mode 100644 index 0000000..8e60091 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/arar.py @@ -0,0 +1,84 @@ +#!/usr/bin/env python +# -*- python -*- +# Repackage a bunch of static libs as one big static library. +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +from __future__ import print_function +import os +import sys +import shutil +import re + +from .base import * +from .util import * + +class arar_error(Exception): + def __init__(self, value): + self.value = value + def _str__(self): + return repr(self.value) + +def repack(files, ar='ar', target='liball.a', verbose=False): + """For linux only. Repackage the list of files using ar as the + archiver program. The input files list can contain .a or .o + files. The output library name is supplied by the target keyword + argument. This will raise an exception arar_error in the event of + a problem, setting the exception value field with an explanation.""" + import glob + pid= os.getpid() + #error=os.system(ar + " --version") + tdir = 'tmp.arar.%d' % (pid) + if os.path.exists(tdir): + raise arar_error('Conflict with existing temporary directory: %s' % \ + (tdir)) + os.mkdir(tdir) + # work in a temporary subdirectory + os.chdir(tdir) + doto = [] + for arg in files: + if re.search(r'[.]o$', arg): + if arg[0] == '/': + doto.append(arg) + else: + doto.append(os.path.join('..',arg)) + continue + if arg[0] == '/': + cmd = "%s x %s" % (ar,arg) + else: + cmd = "%s x ../%s" % (ar,arg) + if verbose: + uprint(u"EXTRACTING %s" % (cmd)) + error= os.system(cmd) + if error: + raise arar_error('Extract failed for command %s' % (cmd)) + files = glob.glob('*.o') + doto + local_target = os.path.basename(target) + cmd = "%s rcv %s %s" % (ar, local_target, " ".join(files)) + if verbose: + uprint(u"RECOMBINING %s" % (cmd)) + error=os.system(cmd) + if error: + raise arar_error('Recombine failed') + + os.chdir('..') + os.rename(os.path.join(tdir,local_target), target) + if verbose: + uprint(u"CREATED %s" % (target)) + shutil.rmtree(tdir) + + diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/base.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/base.py new file mode 100644 index 0000000..36fdfea --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/base.py @@ -0,0 +1,311 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +"""Base functionality: messages, verbosity, python version checking""" + +import os +import sys +import traceback +import locale + +_MBUILD_ENCODING = locale.getpreferredencoding() +def unicode_encoding(): + return _MBUILD_ENCODING + +PY3 = sys.version_info > (3,) +def is_python3(): + global PY3 + return PY3 + +_mbuild_verbose_level = 1 +def verbose(level=0): + """Return True if the configured message level supplied is >= the + level arguement + @param level: int + @param level: the verbosity level at which this function should return True + + @rtype: bool + @return: True iff the level argument is >= current verbosity level + """ + global _mbuild_verbose_level + if _mbuild_verbose_level >= level: + return True + return False +def set_verbosity(v): + """Set the global verbosity level. 0=quiet, 99=very very noisy""" + global _mbuild_verbose_level + _mbuild_verbose_level = v + +def get_verbosity(): + """Return the global verbosity level. 0=quiet, 99=very very noisy""" + global _mbuild_verbose_level + return _mbuild_verbose_level + +def bracket(s,m=''): + """add a bracket around s and append m. + @rtype: string + @return: a bracketed string s and a suffixed message m + """ + n = convert2unicode(m) + return u'[{}] {}'.format(s,n) + +def error_msg(s,t): + """Emit '[s] t' to stderr with a newline""" + sys.stderr.write(u2output(bracket(s,t) + "\n")) + +def msg(s, pad=''): + """Emit s to stdout with a newline""" + # someone could pass unicode as pad... + sys.stdout.write(u2output(pad)) + sys.stdout.write(u2output(s)) + sys.stdout.write("\n") + +def msgn(s, pad=''): + """Emit s to stdout without a newline""" + # someone could pass unicode as pad... + sys.stdout.write(u2output(pad)) + sys.stdout.write(u2output(s)) + +def msgb(s,t='',pad=''): + """a bracketed string s sent to stdout, followed by a string t""" + msg(bracket(s,t), pad=pad) + +def vmsg(v,s,pad=''): + """If verbosity v is sufficient, emit s to stdout with a newline""" + # someone could pass unicode as pad... + if verbose(v): + msg(s,pad=pad) + +def vmsgb(v,s,t='',pad=''): + """If verbosity v is sufficient, emit a bracketed string s sent to + stdout, followed by a string t""" + vmsg(v,bracket(s,t),pad=pad) + +def cond_die(v, cmd, msg): + """Conditionally die, if v is not zero. Print the msg and the cmd. + @type v: int + @param v: we die if v is not 0 + + @type cmd: string + @param cmd: a command to print + + @type msg: string + @param msg: a message to print before the command + """ + if v != 0: + s = msg + "\n [CMD] " + cmd + die(s) + +def die(m,s=''): + """Emit an error message m (and optionally s) and exit with a return + value 1""" + msgb("MBUILD ERROR", "%s %s\n\n" % (m,s) ) + etype, value, tb = sys.exc_info() + if tb is None: + stack = traceback.extract_stack()[:-1] + traceback.print_list(stack, file=sys.stdout) + else: + traceback.print_exception(etype, value, tb, file=sys.stdout) + sys.exit(1) + +def warn(m): + """Emit an warning message""" + msgb("MBUILD WARNING", m) + +def get_python_version(): + """Return the python version as an integer + @rtype: int + @return: major * 100000 + minor + 1000 + fixlevel + """ + tuple = sys.version_info + major = int(tuple[0]) + minor = int(tuple[1]) + fix = int(tuple[2]) + vnum = major *100000 + minor * 1000 + fix + return vnum + +def get_python_version_tuple(): + """Return the python version as a tuple (major,minor,fixlevel) + @rtype: tuple + @return: (major,minor,fixlevel) + """ + + tuple = sys.version_info + major = int(tuple[0]) + minor = int(tuple[1]) + fix = int(tuple[2]) + return (major,minor,fix) + +def check_python_version(maj,minor,fix=0): + """Return true if the current python version at least the one + specified by the arguments. + @rtype: bool + @return: True/False + """ + t = get_python_version_tuple() + if t[0] > maj: + return True + if t[0] == maj and t[1] > minor: + return True + if t[0] == maj and t[1] == minor and t[2] >= fix: + return True + return False + + + +try: + if check_python_version(2,7) == False: + die("MBUILD error: Need Python version 2.7 or later.") +except: + die("MBUILD error: Need Python version 2.7 or later.") + +import platform # requires python 2.3 +_on_mac = False +_on_native_windows = False +_on_windows = False # cygwin or native windows +_on_cygwin = False +_on_linux = False +_on_freebsd = False +_on_netbsd = False +_operating_system_name = platform.system() +if _operating_system_name.find('CYGWIN') != -1: + _on_cygwin = True + _on_windows = True +elif _operating_system_name == 'Microsoft' or _operating_system_name == 'Windows': + _on_native_windows = True + _on_windows = True +elif _operating_system_name == 'Linux': + _on_linux = True +elif _operating_system_name == 'FreeBSD': + _on_freebsd = True +elif _operating_system_name == 'NetBSD': + _on_netbsd = True +elif _operating_system_name == 'Darwin': + _on_mac = True +else: + die("Could not detect operating system type: " + _operating_system_name) + +def on_native_windows(): + """ + @rtype: bool + @return: True iff on native windows win32/win64 + """ + global _on_native_windows + return _on_native_windows + +def on_windows(): + """ + @rtype: bool + @return: True iff on windows cygwin/win32/win64 + """ + global _on_windows + return _on_windows + +def on_mac(): + """ + @rtype: bool + @return: True iff on mac + """ + global _on_mac + return _on_mac + +###### + +# UNICODE SUPPORT FEATURES for PY2/PY3 co-existence + + +# unicode string constructors +if PY3: + ustr = str +else: + ustr = unicode # converts its argument to a unicode object + +# binary data strings constructors +if PY3: + bstr = bytes +else: + bstr = str + +def unicode2bytes(us): + """convert a unicode object (unicode type in python2 or string type in + python3) to bytes suitable for writing to a file.""" + return us.encode(unicode_encoding()) + +def bytes2unicode(bs): + """Convert a bytes object or a python2 string to unicode""" + return bs.decode(unicode_encoding()) + +def ensure_string(x): + # strings in python2 turn up as bytes + # strings in python3 show up as strings and are unicode + if isinstance(x,bytes): + return bytes2unicode(x) + if isinstance(x,list): + o = [] + for y in x: + if isinstance(y,bytes): + o.append( bytes2unicode(y) ) + else: + o.append( y ) + return o + return x + +def uappend(lst,s): + """Make sure s is unicode before adding it to the list lst""" + lst.append(ensure_string(s)) + +def u2output(s): + """encode unicode string for output to stderr/stdout, but leave bytes + strings as is. Python3 can print unicode to stdout/stderr if + the locale (LANG env var, etc.) supports it. """ + # we don't want to call encode for non-unicode (bytes) strings + # because that can generate *decode* errors. In python3 we are set + # since all strings are unicode and thus it is always safe to call + # encode on them. In python2 we must see if the string is unicode + # or bytes. + + # python3 does not allow bytes objects as arguments to + # sys.stdout.write() so we just leave stuff as unicode strings in + # python3. If LANG is not C, that works. If LANG is C, wait for + # python 3.7 in mid June 2018. Or just do not use LANG = C! + global PY3 + if not PY3: + if isinstance(s,unicode): + return unicode2bytes(s) + return s + +def uprint(s): + """encode unicode for output and print""" + t = u2output(s) + print(t) + +def is_stringish(x): + global PY3 + if isinstance(x,bytes) or isinstance(x,str): + return True + # python2 has a type unicode, which does not exist by default in + # python3. + if not PY3: + return isinstance(x,unicode) + return False + +def convert2unicode(x): + """convert an arbitrary x to a unicode string""" + return ustr(x) diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/build_env.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/build_env.py new file mode 100644 index 0000000..3bbc104 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/build_env.py @@ -0,0 +1,502 @@ +#!/usr/bin/env python +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""Setup functions for the ms/gnu compiler environment""" + +import os +import sys +import platform +from .base import * +from .util import * +from .env import * +from . import msvs + + +def set_compiler_env_common(env): + """Set up some common stuff that depends heavily on the compiler setting""" + + # This whole section was really an experiment in how dynamically I + # could do substitutions. + + env['debug_flag'] = ( 'debug', { True: '%(DEBUGFLAG)s', + False:''}) + env['debug_flag_link'] = ( 'debug', { True: '%(DEBUGFLAG_LINK)s', + False:''}) + + win_shared_compile_dict = ( 'compiler', { 'ms': ( 'debug', { True: '/MDd', False: '/MD' }), + 'icl': ( 'debug', { True: '/MDd', False: '/MD' }), + 'otherwise': '', + }) + + shared_compile_dict = ( 'host_os', { 'android': '-fPIC', + 'lin': '-fPIC', + 'win': win_shared_compile_dict, + 'bsd': '-fPIC', + 'otherwise': '', + }) + + win_static_compile_dict = ( 'compiler', { 'ms': ( 'debug', { True: '/MTd', False: '/MT' }), + 'icl': ( 'debug', { True: '/MTd', False: '/MT' }), + 'otherwise': '', + }) + + static_compile_dict = ( 'host_os', { 'android': '', + 'lin': '', + 'win': win_static_compile_dict, + 'bsd': '', + 'otherwise': '', + }) + + env['shared_compile_flag'] = ( 'shared', { True: shared_compile_dict, + False: static_compile_dict + }) + + shared_link_dict = ('compiler', { 'ms':'/dll', + 'icl':'/dll', + 'icc':'-shared', + 'gnu':'-shared'}) + + env['shared_link'] = ( 'shared', { True: shared_link_dict, + False:''}) + + env['OPTOPT'] = ( 'compiler', { 'gnu':'-O', + 'clang':'-O', + 'iclang':'-O', + 'icc':'-O', + 'icl':'/O', + 'ms':'/O'}) + + env['nologo'] = ( 'compiler', { 'gnu':'', + 'clang':'', + 'iclang':'', + 'icc':'', + 'icl':'/nologo', + 'ms':'/nologo'}) + flags = '' + flags += ' %(debug_flag)s' + flags += ' %(nologo)s' + flags += ' %(opt_flag)s' + flags += ' %(shared_compile_flag)s' + env['CCFLAGS'] = flags + env['CXXFLAGS'] = flags + env['LINKFLAGS'] += ' %(debug_flag_link)s' + +def add_gnu_arch_flags(d): + """Accept a dictionary, return a string""" + if d['compiler'] in ['gnu','clang'] and d['gcc_version'] != '2.96': # FIXME: iclang? + if d['host_cpu'] == 'x86-64': + return '-m64' + elif d['host_cpu'] == 'ia32': + return '-m32' + return '' + + +def set_env_gnu(env): + """Example of setting up the GNU GCC environment for compilation""" + set_compiler_env_common(env) + + env['opt_flag'] = ( 'opt', {'noopt':'', + 's':'%(OPTOPT)ss', + '0':'%(OPTOPT)s0', + '1':'%(OPTOPT)s1', + '2':'%(OPTOPT)s2', + '3':'%(OPTOPT)s3', + '4':'%(OPTOPT)s4'} ) + + # lazy toolchain and other env var (f) expansion + mktool = lambda f: "%(toolchain)s%(" + f + ")s" + + if env['CXX_COMPILER'] == '': + env['CXX_COMPILER'] = ( 'compiler', { 'gnu':'g++', + 'icc':'icpc', + 'iclang':'icl++', + 'clang':'clang++'}) + if env['CC_COMPILER'] == '': + env['CC_COMPILER'] = ( 'compiler', { 'gnu':'gcc', + 'icc':'icc', + 'iclang':'icl', + 'clang':'clang' }) + if env['ASSEMBLER'] == '': + env['ASSEMBLER'] = ( 'compiler', { 'gnu':'gcc', + 'icc':'icc', + 'iclang':'icl', + 'clang':'yasm' }) + + if env['LINKER'] == '': + env['LINKER'] = '%(CXX_COMPILER)s' # FIXME C++ or C? + if env['ARCHIVER'] == '': + env['ARCHIVER'] = ( 'compiler', { 'gnu': 'ar', # or GAR?? + 'icc' : 'xiar', + 'iclang' : 'xiar', + 'clang':'ar' }) + if env['RANLIB_CMD'] == '': + env['RANLIB_CMD'] = 'ranlib' + + if env['CC'] == '': + env['CC'] = mktool('CC_COMPILER') + if env['CXX'] == '': + env['CXX'] = mktool('CXX_COMPILER') + if env['AS'] == '': + env['AS'] = mktool('ASSEMBLER') + if env['LINK'] == '': + env['LINK'] = mktool('LINKER') + if env['AR'] == '': + env['AR'] = mktool('ARCHIVER') + if env['RANLIB'] == '': + env['RANLIB'] = mktool('RANLIB_CMD') + + # if using gcc to compile include -c. If using gas, omit the -c + env['ASFLAGS'] = ' -c' + + env['ARFLAGS'] = "rcv" + env['STATIC'] = ( 'static', { True : "-static", + False : "" } ) + env['LINKFLAGS'] += " %(STATIC)s" + + env['GNU64'] = add_gnu_arch_flags # dynamically called function during variable expansion! + s = ' %(GNU64)s' + env['CCFLAGS'] += s + env['CXXFLAGS'] += s + env['LINKFLAGS'] += s + # if using gcc to compile use -m64, otherwise if gas is used, omit the -m64. + env['ASFLAGS'] += s + + env['DEBUGFLAG'] = '-g' + env['DEBUGFLAG_LINK'] = '-g' + env['COPT'] = '-c' + env['DOPT'] = '-D' + env['ASDOPT'] = '-D' + env['IOPT'] = '-I' + env['ISYSOPT'] = '-isystem ' # trailing space required + env['LOPT'] = '-L' + + env['COUT'] = '-o ' + env['ASMOUT'] = '-o ' + env['LIBOUT'] = ' ' # nothing when using gar/ar + env['LINKOUT'] = '-o ' + env['EXEOUT'] = '-o ' + if env.on_mac(): + env['DLLOPT'] = '-shared' # '-dynamiclib' + else: + env['DLLOPT'] = '-shared -Wl,-soname,%(SOLIBNAME)s' + + env['OBJEXT'] = '.o' + if env.on_windows(): + env['EXEEXT'] = '.exe' + env['DLLEXT'] = '.dll' + env['LIBEXT'] = '.lib' + env['PDBEXT'] = '.pdb' + elif env.on_mac(): + env['EXEEXT'] = '' + env['DLLEXT'] = '.dylib' + env['LIBEXT'] = '.a' + env['PDBEXT'] = '' + else: + env['EXEEXT'] = '' + env['DLLEXT'] = '.so' + env['LIBEXT'] = '.a' + env['PDBEXT'] = '' + +def find_ms_toolchain(env): + if env['msvs_version']: + env['setup_msvc']=True + + if env['vc_dir'] == '' and not env['setup_msvc']: + if 'MSVCDir' in os.environ: + vs_dir = os.environ['MSVCDir'] + if os.path.exists(vs_dir): + env['vc_dir'] = vs_dir + elif 'VCINSTALLDIR' in os.environ: + vc_dir = os.environ['VCINSTALLDIR'] + if os.path.exists(vc_dir): + env['vc_dir'] = vc_dir + msvs7 = os.path.join(env['vc_dir'],"Vc7") + if os.path.exists(msvs7): + env['vc_dir'] = msvs7 + elif 'VSINSTALLDIR' in os.environ: + vs_dir = os.environ['VSINSTALLDIR'] + if os.path.exists(vs_dir): + env['vc_dir'] = os.path.join(vs_dir, 'VC') + elif 'MSVCDIR' in os.environ: + vs_dir = os.environ['MSVCDIR'] + if os.path.exists(vs_dir): + env['vc_dir'] = vs_dir + + # Before DEV15, the VCINSTALLDIR was sufficient to find the + # compiler. But with DEV15, they locate the compiler more deeply + # in to the file system and we need more information including the + # build number. The DEV15 installation sets the env var + # VCToolsInstallDir with that information. The headers and + # libraries change location too so relying on VCINTALLDIR is + # insufficient. So if people run with (1) mbuild's setup of DEV15 + # or (2) the MSVS command prompt, they should be fine. But + # anything else is probably questionable. + + incoming_setup = True # presume system setup by user + if env['vc_dir'] == '' or env['setup_msvc']: + incoming_setup = False + env['vc_dir'] = msvs.set_msvs_env(env) + + # toolchain is the bin directory of the compiler with a trailing slash + if env['toolchain'] == '': + if incoming_setup: + # relying on user-setup env (say MSVS cmd.exe or vcvars-equiv bat file) + if os.environ['VisualStudioVersion'] in ['15.0','16.0']: + env['msvs_version'] = str(int(float(os.environ['VisualStudioVersion']))) + msvs.set_msvc_compilers(env, os.environ['VCToolsInstallDir']) + if env['compiler']=='ms': + env['toolchain'] = msvs.pick_compiler(env) + + + +def _check_set_rc(env, sdk): + def _path_check_rc_cmd(env): + if os.path.exists(env.expand('%(RC_CMD)s')): + return True + return False + + if env['host_cpu'] == 'x86-64': + env['RC_CMD'] = os.path.join(sdk,'x64','rc.exe') + else: + env['RC_CMD'] = os.path.join(sdk,'x86','rc.exe') + if not _path_check_rc_cmd(env): + env['RC_CMD'] = os.path.join(sdk,'rc.exe') + return _path_check_rc_cmd(env) + + +def _find_rc_cmd(env): + """Finding the rc executable is a bit of a nightmare. + + In MSVS2005(VC8): + C:/Program Files (x86)/Microsoft Visual Studio 8/VC + bin/rc.exe + or + PlatformSDK/Bin/win64/AMD64/rc.exe + which is $VCINSTALLDIR/bin or + $VCINSTALLDIR/PlatformSDK/bin/win64/AMD64 + We do not bother attempting to find that version of rc. + Put it on your path or set env['RC_CMD'] if you need it. + + In MSVS2008(VC9), MSVS2010 (VC10) and MSVS2012 (VC11): + have rc.exe in the SDK directory, though the location varies + a little for the 32b version. + + With winsdk10 (used by MSVS2017/DEV15), rc.exe moved around from + version to version of the sdk. In the early versions of the SDK, + the rc.exe is located in: + + C:\Program Files (x86)\Windows Kits\10\bin\{x86,x64} + + However, in later versions (starting with 10.0.16299.0), they + placed the rc.exe in the numbered subdirectory: + + C:\Program Files (x86)\Windows Kits\10\bin\10.0.16299.0\{x86,x64} + """ + sdks = [] # list of directories to search + + def _add_bin(s): + return os.path.join(s,'bin') + + if 'rc_winkit_number' in env: # set up by msvs.py for dev14, dev15 + p = "{}/bin/{}".format( env['rc_winkit'], + env['rc_winkit_number']) + sdks.append(p) + + if 'rc_winkit' in env: # set up by msvs.py for dev14, dev15 + sdks.append(_add_bin(env['rc_winkit'])) + pass + + if 'WindowsSdkDir' in env: + sdks.append( _add_bin(env['WindowsSdkDir'])) + elif 'WindowsSdkDir' in os.environ: + sdks.append( _add_bin(os.environ['WindowsSdkDir'])) + + for k in sdks: + if _check_set_rc(env,k): + # found a good one...work with that. + return + + if env['host_cpu'] == 'x86-64': + warn("Could not find 64b RC command in SDK directory; assuming on PATH") + else: + warn("Could not find 32b RC command in SDK directory; assuming on PATH") + # hope the user puts the location of RC on their PATH + env['RC_CMD'] = 'rc' + + + +def set_env_ms(env): + """Example of setting up the MSVS environment for compilation""" + set_compiler_env_common(env) + + # FIXME: allow combinations of options + env['opt_flag'] = ( 'opt', {'noopt':'', + '0':'%(OPTOPT)sd', + '1':'%(OPTOPT)s1', + '2':'%(OPTOPT)s2', + '3':'%(OPTOPT)s2', # map O3 and O4 to O2 + '4':'%(OPTOPT)s2', # map O3 and O4 to O2 + 'b':'%(OPTOPT)sb', + 'i':'%(OPTOPT)si', + 's':'%(OPTOPT)ss', + 'x':'%(OPTOPT)sx', + 'd':'%(OPTOPT)sd', + 'g':'%(OPTOPT)sg'} ) + + env['ASFLAGS'] = '/c /nologo ' + env['LINKFLAGS'] += ' /nologo' + env['ARFLAGS'] = '/nologo' + + env['link_prefix'] = ('use_compiler_to_link', { True:'/link', + False:'' }) + if env['host_cpu'] == 'ia32': + env['LINKFLAGS'] += ' %(link_prefix)s /MACHINE:X86' + env['ARFLAGS'] += ' /MACHINE:X86' + elif env['host_cpu'] == 'x86-64': + env['LINKFLAGS'] += ' %(link_prefix)s /MACHINE:X64' + env['ARFLAGS'] += ' /MACHINE:X64' + + env['favor'] = ( 'compiler', { 'ms' : ' /favor:EM64T', + 'otherwise' : '' }) + env['CXXFLAGS'] += ' %(favor)s' + env['CCFLAGS'] += ' %(favor)s' + + elif env['host_cpu'] == 'ipf': + env['LINKFLAGS'] += ' %(link_prefix)s /MACHINE:IA64' + env['ARFLAGS'] += ' /MACHINE:IA64' + + env['COPT'] = '/c' + env['DOPT'] = '/D' + env['ASDOPT'] = '/D' + + # I use '-I' instead of '/I' because it simplifies use of YASM + # which requires -I for includes. + env['IOPT'] = '-I' # -I or /I works with MSVS8. + env['ISYSOPT'] = '-I' # MSVS has not -isystem so we use -I + env['LOPT'] = '%(link_prefix)s /LIBPATH:' + + + # Some options differ when using the compiler to link programs. + # Note: /Zi has parallel-build synchronization bugs + env['DEBUGFLAG'] = '/Z7' + env['DEBUGFLAG_LINK'] = ('use_compiler_to_link', { True:'/Z7', # of /Zi + False:'/debug'}) + env['COUT'] = '/Fo' + env['ASMOUT'] = '/Fo' + env['LIBOUT'] = '/out:' + env['EXEOUT'] = '/Fe' + env['LINKOUT'] = ('use_compiler_to_link',{ True:'/Fo', + False:'/OUT:'}) + env['DLLOPT'] = '/dll' + env['OBJEXT'] = '.obj' + env['LIBEXT'] = '.lib' + env['DLLEXT'] = '.dll' + env['EXEEXT'] = '.exe' + env['PDBEXT'] = '.pdb' + env['PDBEXT'] = '.pdb' + env['RCEXT'] = '.rc' + env['RESEXT'] = '.res' + + find_ms_toolchain(env) + + if env['ASSEMBLER'] == '': + if env['host_cpu'] == 'ia32': + env['ASSEMBLER'] = 'ml.exe' + elif env['host_cpu'] == 'x86-64': + env['ASSEMBLER'] = 'ml64.exe' + + if env['CXX_COMPILER'] == '': + env['CXX_COMPILER'] = ( 'compiler', { 'ms':'cl.exe', + 'icl':'icl.exe' }) + if env['CC_COMPILER'] == '': + env['CC_COMPILER'] = ( 'compiler', { 'ms':'cl.exe', + 'icl':'icl.exe' }) + if env['LINKER'] == '': + env['LINKER'] = ( 'compiler', { 'ms': 'link.exe', + 'icl' : 'xilink.exe'}) + + # old versions of RC do not accept the /nologo switch + env['rcnologo'] = ( 'msvs_version', { 'otherwise':' /nologo', + '6':'', + '7':'', + '8':'', + '9':'' }) + env['RCFLAGS'] = " %(rcnologo)s" + + + if env['RC_CMD'] == '': + _find_rc_cmd(env) + + if env['RC'] == '': + env['RC'] = quote('%(RC_CMD)s') + + if env['ARCHIVER'] == '': + env['ARCHIVER'] =( 'compiler', { 'ms': 'lib.exe', + 'icl' : 'xilib.exe'}) + # lazy toolchain and other env var (f) expansion + mktool = lambda f: "%(toolchain)s%(" + f + ")s" + + if env['CXX'] == '': + env['CXX'] = quote(mktool('CXX_COMPILER')) + if env['CC'] == '': + env['CC'] = quote(mktool('CC_COMPILER')) + if env['AS'] == '': + env['AS'] = quote(mktool('ASSEMBLER')) + if env['LINK'] == '': + env['LINK'] = quote(mktool('LINKER')) + if env['AR'] == '': + env['AR'] = quote(mktool('ARCHIVER')) + + + +def yasm_support(env): + """Initialize the YASM support based on the env's host_os and host_cpu""" + # FIXME: android??? + yasm_formats={} + yasm_formats['win'] = { 'ia32': 'win32', 'x86-64': 'win64'} + yasm_formats['lin'] = { 'ia32': 'elf32', 'x86-64': 'elf64'} + yasm_formats['bsd'] = { 'ia32': 'elf32', 'x86-64': 'elf64'} + yasm_formats['mac'] = { 'ia32': 'macho32', 'x86-64': 'macho64'} + env['ASDOPT']='-D' + try: + env['ASFLAGS'] = ' -f' + yasm_formats[env['host_os']][env['host_cpu']] + env['ASMOUT'] = '-o ' + env['AS'] = 'yasm' + except: + die("YASM does not know what format to use for build O/S: %s and target CPU: %s" % + (env['host_os'], env['host_cpu'])) + + + +def set_env_clang(env): + set_env_gnu(env) + + +def set_env_icc(env): + """Example of setting up the Intel ICC environment for compilation""" + set_env_gnu(env) + +def set_env_iclang(env): + """Example of setting up the Intel iclang (aka mac icl) environment for compilation""" + set_env_gnu(env) + +def set_env_icl(env): + """Example of setting up the Intel ICL (windows) environment for compilation""" + set_env_ms(env) diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/dag.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/dag.py new file mode 100644 index 0000000..a5b707d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/dag.py @@ -0,0 +1,1131 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""dependence tracking using a directed acyclic graph (DAG)""" + +# Originally, we decided that if we could not find a header then it +# was an error. And there was an ignored file list for headers that +# were conditionally included on some platforms but not others. The +# idea was that you'd list the files that were ignorable on your +# platform and they would not trigger a rebuild. Any other missing +# file would trigger a rebuild though!! That's problematic though as +# users must maintain lists of ignorable files. +# +# Another school of thought is that if the scanner cannot find the +# file and all the include paths were specified properly, then the +# compilation will fail if the header is required. Missing headers +# files in this regime will not trigger downstream rebuilds. +# +# This precludes users from manually specifying -I flags and +# skipping the mbuild's add_include_dir() API. They'll get okay +# build but incomplete dependence checks. So don't bypass +# add_include_dir()! +# +# Even so, there is a problem with ignoring missing files: What about +# dependences on generated header files that have not been generated +# yet? That is THE problem that motivates this design. If we ignore +# missing headers, then the "dependent" file will either be marked as: +# +# (a) "ready to compile" (assuming the other headers are found but one +# or more might have changed) +# or +# (b) "does not need compilation" (if none of the found headers +# have changed). +# +# In the former case (a), the compilation will fail +# nondeterministically depending on whether or not the header file is +# created at the compilation time of the "including" file. Or in the +# latter case (b), we won't rebuild things that need +# rebuilding. Either way, the idea of ignoring missing header files is +# very broken. +# +# A third option is to ignore most header missing files but specify +# that certain generated missing header files cannot be ignored. Since +# there are way fewer generated header files, this is a much more +# convenient option. +# +# NOTE: If there is a cmd in the dag that produces the missing header +# file, we must run it to produce the missing header. +# + +from __future__ import print_function +import os +import sys +import platform +import types +import collections +import atexit +try: + import cPickle as apickle +except: + import pickle as apickle + + +from .base import * +from .work_queue import * +from .env import * +from .util import * +from .plan import * +from . import scanner +from . import dfs +from . import util + +class _mbuild_dep_record_t(object): + """This stores the basic dependence structure for the + build. Creators are listed for files that are generated. The + signature is the last signature we saw for this.""" + def __init__(self, file_name, creator=None): + self.file_name = file_name + + self.old_signature = None + self.signature = None + self.scanned_header = False + + # If this file has a creator, we check the signature of the + # thing that created it to see if it is the same as it was the + # last time we made this target. + self.old_command_signature = None + self.command_signature = None + + # did we do the header scan for this file yet? + self.scanned = False + + # When a changed input reaches this node, it sets needs_to_run + # to True. + self.needs_to_run = False + self.visited = False + self.added = False + + # before building, we mark all the nodes that are required for + # the build to True (by search for ancestors from targets) so + # that we know which commands to enable for execution. + self.required = False + + self.changed = None + + self.creator = creator # command_t + self.files_that_are_inputs = [] + self.files_that_depend_on_this = [] + + self.part_of_loop = False + self.index = 0 + self.lowlink = 0 + + self.hash_file() + + def hash_file(self): + #msgb("HASHING", str(self.file_name)) + if os.path.exists(self.file_name): + self.signature = util.hash_file(self.file_name) + else: + if verbose(99): + msgb("COULD NOT HASH MISSING FILE", self.file_name) + + def hash_if_needed(self): + if self.signature == None: + self.hash_file() + + + def missing(self): + if not os.path.exists(self.file_name): + return True + return False + + + def _check_required(self, required_files): + if self.file_name in required_files: + return True + if os.path.basename(self.file_name) in required_files: + return True + return False + + + def _compute_changed_bit(self, required_files): + """Return True if there is no old signature or the old + signature does not equal the current signature, or the file + does not exist""" + if self.missing(): + # A missing required file during the scan implies either + # the build is going to fail or something upstream better + # create it. And if it is created we are going to have to + # assume it is changing since we don't have one now. + if verbose(10): + msgb("MISSING FILE", self.file_name) + if self._check_required(required_files): + if verbose(10): + msgb("MISSING REQUIRED FILE->CHANGED") + return True + # we let scanned headers slide if they don't exist + if self.scanned_header: + if verbose(10): + msgb("MISSING SCANNED HEADER FILE->UNCHANGED") + return False + if verbose(10): + msgb("MISSING FILE->ASSUME CHANGED") + return True + else: + if self.old_signature: + self.hash_if_needed() + if self.old_signature == self.signature: + return False + elif verbose(10): + msgb("SIG MISMATCH for %s" % self.file_name) + msgb("OLD SIG %s" % str(self.old_signature)) + msgb("NEW SIG %s" % str(self.signature)) + elif verbose(10): + msgb("NO OLD SIG for %s" % self.file_name) + return True + + def change_bit(self, required_files): + """Compute changed bit if it has not been computed yet. Return + the value.""" + if self.changed == None: + self.changed = self._compute_changed_bit(required_files) + if verbose(10): + msgb("COMPUTE CHANGE BIT", "%s for %s" % + ( str(self.changed), self.file_name)) + return self.changed + + + def format_string(self,s): + o = "\n\t".join(s) + return o + + def dump_str(self): + + s = "\tANCESTORS: %s\nTARGET: %s\n\tDESCENDENTS: %s\n" % \ + (self.format_string(self.files_that_are_inputs), + self.file_name, + self.format_string(self.files_that_depend_on_this)) + + if self.creator: + s += "\tCREATOR: %s\n" % self.creator.dump() + if self.visited: + s += "\tVISITED\n" + else: + s += "\tNOT-VISITED\n" + + if self.part_of_loop: + s += "\tIN-LOOP\n" + else: + s += "\tNOT-IN-LOOP\n" + + if self.required: + s += "\tREQUIRED\n" + else: + s += "\tNOT-REQUIRED\n" + + if self.changed: + s += "\tCHANGED\n" + else: + s += "\tNOT-CHANGED\n" + return s + + def dump(self): + """print a string representing this node of the DAG. The + string comes from the __str__ function""" + print(self.dump_str()) + def __str__(self): + return self.dump_str() + +class _mbuild_storage_object_t(object): + def __init__(self, signature): + self.signature = signature + +def _do_terminate(d): + """called by atexit function for dag_t objects""" + d.terminate() + +class dag_t(object): + """ + This object builds a DAG of files an sequences their submission to + the parallel work queue of type L{work_queue_t}. + + This takes L{plan_t} objects representing command + strings or python functions, and creates L{command_t} + objects suitable for use in the L{work_queue_t}. + + As the L{work_queue_t} executes, it queries this DAG for more + ready commands or functions to execute. + """ + + + def __init__(self, name='default', env=None): + self.name = name + self.recs = {} # _mbuild_dep_record_t's + + # dictionary of _mbuild_storage_object_t's by file name. + self.old_signatures = {} + + # if you care about changes to the python functions, then + # include the python sources in the list of inputs. This + # feature _python_commands_changed is deprecated. + self._python_commands_changed = False + + self.signature_file_name = ".mbuild.hash." + self.name + if env: + self.signature_file_name = env.build_dir_join( + self.signature_file_name) + # some users change directories during the build and we do not + # want relative paths to mess us up when we go to write the + # signature file at the end of the build. + self.signature_file_name = os.path.abspath(self.signature_file_name) + + if os.path.exists(self.signature_file_name): + self._read_signatures(self.signature_file_name) + + if env and 'required' in env: + self.required_set = \ + set(self._canonize_if_exists_fn(env['required'])) + else: + self.required_set = set() + + atexit.register(_do_terminate, self) + + def cycle_check(self): + """Check the DAG for illegal cycles in the include structure. + @rtype: bool + @return: True if the DAG contains cycles (and thus is not a DAG). + """ + node_dict = {} + # build the graph for the DFS + for k,v in iter(self.recs.items()): + if k in node_dict: + node = node_dict[k] + else: + node = dfs.node_t(k) + node_dict[k] = node + for p in v.files_that_are_inputs: + if p in node_dict: + pnode = node_dict[p] + else: + pnode = dfs.node_t(p) + node_dict[p] = pnode + node.add_successor(pnode) + # Traverse the graph + cycle = dfs.dfs(node_dict.values()) + if cycle: + msgb("CYCLE DETECTED IN DAG") + return cycle + + def terminate(self): + self.dag_write_signatures() + + def dump(self): + """print a string representing the DAG. """ + print("DAG DUMP") + for v in iter(self.recs.values()): + v.dump() + + def _hash_mixed_list(l): + + if isinstance(l, list): + il = l + else: + il = [l] + s = [] + for i in il: + if i.is_command_line(): + s.append(i.command) + t = " - ".join(s) + h = hash_string(t) + return h + + def dag_write_signatures(self): + """Write a dictionary of _mbuild_storage_object_t's to the + given file name""" + vmsgb(10, "WRITING SIGNATURES", self.signature_file_name) + d = {} + for (k,v) in iter(self.recs.items()): + # get the new hash values for anything that had a command + # execute for it. + if v.creator: + if v.creator.is_command_line() and v.creator.completed: + # store the command line hashes in the same + # dictionary with a prefix + command_hash = v.creator.hash() + full_key = v.creator.dagkey() + d[full_key]= _mbuild_storage_object_t(command_hash) + if verbose(99): + msgb("SIGWRITE", "%s -> %s" % (str(command_hash), + full_key)) + if v.creator.completed and v.creator.exit_status == 0: + v.hash_file() + if v.creator and v.creator.failed(): + if verbose(99): + msgb("NULLIFY SIG", k) + v.signature = None + if not v.signature: + if verbose(99): + msgb("FIXING NULL SIGNATURE", k) + v.hash_file() + + if verbose(99): + msgb("SIGWRITE", "%s -> %s" % (str(v.signature),k)) + d[k] = _mbuild_storage_object_t(v.signature) + + # FIXME: binary protocol 2, binary file write DOES NOT WORK ON + # win32/win64 + f = open(self.signature_file_name,"wb") + apickle.dump(d,f) + f.close() + + def _check_command_signature(self, co): + """Return True if the signature matches the command object.""" + + # if the command is not a list of strings, we just assume that + # is has changed. + if co.has_python_subcommand(): + if self._python_commands_changed: + return False + else: + return True # assume the command has not changed + + full_key = co.dagkey() + try: + old_hash = self.old_signatures[full_key].signature + if verbose(99): + msgb('COMMAND HASH', full_key) + msgb('COMMAND HASH', old_hash) + new_hash = co.hash() + if old_hash == new_hash: + if verbose(99): + msgb('COMMAND HASH','\tMATCH') + + return True + except: + if verbose(99): + msgb('COMMAND HASH','\tNO OLD HASH') + + if verbose(99): + msgb('COMMAND HASH','\tDOES NOT MATCH') + return False + + + def _read_signatures(self, file_name): + """Read a dictionary of _mbuild_storage_object_t's from the + given file name.""" + if verbose(10): + msgb("READING SIGNATURES", file_name) + try: + f = open(file_name,"rb") + self.old_signatures = apickle.load(f) + f.close() + except: + warn("READING SIGNATURES FAILED FOR "+ file_name) + return + if verbose(99): + for k, v in iter(self.old_signatures.items()): + msgb("SIGREAD", "%s -> %s" % (str(v.signature),k)) + + # Add old signatures to any existing files + for k, v in iter(self.recs.items()): + if k in self.old_signatures: + v.old_signature = self.old_signatures[k].signature + + def _check_required_file(self,fn): + if fn in self.required_set: + return True + if os.path.basename(fn) in self.required_set: + return True + return False + + + def _compute_all_parents_visited(self, n): + """Returns (all_parents_visited, some_parents_changed)""" + all_parents_visited = True + some_parents_changed = False + for ancestor_fn in n.files_that_are_inputs: + try: + ancestor_rec = self.recs[ancestor_fn] + if ancestor_rec.visited: + if ancestor_rec.changed: + some_parents_changed = True + else: + all_parents_visited = False + except: + if self._check_required_file(ancestor_fn): + warn("[1] node %s: did not find ancestor node: %s" % + (n.file_name, ancestor_fn)) + + return (all_parents_visited, some_parents_changed) + + def _just_compute_parent_changed(self, n): + """Returns True if some parent changed""" + for ancestor_fn in n.files_that_are_inputs: + try: + ancestor_rec = self.recs[ancestor_fn] + if ancestor_rec.visited: + if ancestor_rec.changed: + return True + except: + if self._check_required_file(ancestor_fn): + warn("[2] node %s: did not find ancestor node: %s" % + (n.file_name, ancestor_fn)) + return False + + + def _just_compute_all_parents_visited(self, n): + """Returns True if all parents were visited or parents are part of a loop""" + for ancestor_fn in n.files_that_are_inputs: + try: + ancestor_rec = self.recs[ancestor_fn] + if not ancestor_rec.visited: + if verbose(10): + msgb("PARENT UNVISITED", "%s <- %s" % + (n.file_name, ancestor_fn)) + if n.part_of_loop: + warn("Circularity involving %s" % (n.file_name)) + return True # FIXME HACK + return False + except: + if self._check_required_file(ancestor_fn): + warn("[3] node %s: did not find ancestor node: %s" % + (n.file_name, ancestor_fn)) + return True + + def _just_compute_all_parents_completed(self, n): + """Returns True if all parents that have to execute have completed""" + for ancestor_fn in n.files_that_are_inputs: + try: + ancestor_rec = self.recs[ancestor_fn] + if ancestor_rec.creator: + if not ancestor_rec.creator.completed: + return False + except: + if self._check_required_file(ancestor_fn): + warn("[4] node %s: did not find ancestor node: %s" % + (n.file_name, ancestor_fn)) + return True + + def _set_ancestors_to_required(self, lof): + """Set all the ancestors of the files in the list of files lof + argument to be required nodes.""" + nodes = collections.deque() # work list + for f in lof: + nodes.append(f) + + while len(nodes) != 0: + f = nodes.popleft() + r = self.recs[f] + if not r.required: + if verbose(10): + msgb("MARKING-ANCESTORS AS REQUIRED", r.file_name) + + r.required = True + for g in r.files_that_are_inputs: + nodes.append(g) + + def _find_required_nodes(self, targets): + """Look at the targets list and mark the ancestors as + required for the build. Internal function""" + if verbose(10): + msgb("INPUT TARGETS", str(targets)) + for v in iter(self.recs.values()): + v.required = False + + target_dictionary = dict.fromkeys(targets, True) + if verbose(10): + msgb("TARGETS", str(target_dictionary)) + for v in iter(self.recs.values()): + if v.creator: + if v.file_name in target_dictionary: + if not v.required: + if verbose(10): + msgb("MARK AS REQUIRED", v.file_name) + v.required = True + self._set_ancestors_to_required(v.files_that_are_inputs) + + def check_for_skipped(self): + """Return a list of things that did not build but were tagged + as required for the build. This list could be nonempty because + (1)there was an error in the build or (2) there is a + circularity in the dependence structure.""" + did_not_build = [] + for v in iter(self.recs.values()): + if v.required and not v.visited: + did_not_build.append(v.file_name) + return did_not_build + + def _find_loops(self, root_nodes): + + def _mark_loop(level,n,stack,all_sccs): + # Tarjan's algorithm for strongly connected components + n.index = level + n.lowlink = level + level = level + 1 + stack.append(n) + + for cfn in n.files_that_depend_on_this: + child = self.recs[cfn] + if child.index == 0: + _mark_loop(level,child,stack,all_sccs) + n.lowlink = min(n.lowlink, child.lowlink) + elif child in stack: + n.lowlink = min(n.lowlink, child.index) + + if n.lowlink == n.index: + # collect each strongly connected component + scc = [] + + while 1: + child = stack.pop() + scc.append(child) + if child == n: + break + all_sccs.append(scc) + + stack = collections.deque() + all_sccs = [] # list of lists of nodes + level = 1 + + for v in root_nodes: + _mark_loop(level,v,stack,all_sccs) + + # mark nodes that are part of include-loops (and print them out) + for scc in all_sccs: + if len(scc) > 1: + msg("===================================") + msg("CYCLE INVOLVING THESE FILES (will assume all ready):") + for n in scc: + msg("\t" + n.file_name) + n.part_of_loop = True + msg("===================================") + + def _leaves_with_changes(self, targets=None): + """Return a list of mbuild_dep_records_t for things with no + ancestors but with associated commands. targets is an optional + list of things to build. (called from work_queue.py) + """ + nodes = collections.deque() # work list + + if targets: + if not isinstance(targets, list): # make it a list + targets = [ targets ] + self._find_required_nodes(targets) + else: + # mark all nodes required since no targets are specified + for v in iter(self.recs.values()): + v.required = True + + self._find_loops(iter(self.recs.values())) + + # build a list of roots -- files that have nothing they depend on. + # store that list in the nodes list + for v in iter(self.recs.values()): + v.visited = False # initialize all to false + v.added = False # initialize all to false + if (v.part_of_loop or len(v.files_that_are_inputs) == 0) and v.required: + v.needs_to_run = v.change_bit(self.required_set) + v.added = True + nodes.append(v) + + if verbose(9): + if v.needs_to_run: + s = ": CHANGED" + else: + s = '' + msgb("ROOTSEARCH", v.file_name + s) + else: + v.needs_to_run = False # clear all the other nodes + + ready = self._ready_scan(nodes) + del nodes + return ready + + def _enable_successors(self,cmd): + """When a command completes, it must notify things that + depend on its stated target files. Return a list of ready + commands (called from work_queue.py) + """ + if verbose(10): + msgb('ENABLE SUCCESSORS', str(cmd)) + nodes = collections.deque() # work list + for tgt in cmd.targets: + rtgt = os.path.realpath(tgt) + if verbose(11): + msgb('SUCCESSOR', tgt + " --> " + rtgt) + n = self.recs[ rtgt ] + self._scan_successors(nodes,n) + ready = self._ready_scan(nodes) + if verbose(10): + msgb("NEW READY VALUES", str(ready)) + del nodes + return ready + + def _scan_successors(self, nodes,n): + """Add ready successors of n to nodes list""" + if verbose(10): + msgb('SCAN SUCCESSORS', n.file_name + " -> " + + str(n.files_that_depend_on_this)) + for successor_fn in n.files_that_depend_on_this: + try: + successor_rec = self.recs[successor_fn] + if successor_rec.required and not successor_rec.needs_to_run: + if self._just_compute_all_parents_visited(successor_rec): + if self._just_compute_all_parents_completed(successor_rec): + if verbose(10): + msgb("LEAFSEARCH", "\tADDING: " + + successor_rec.file_name) + # Make sure we are not scanning things + # multiple times. + if successor_rec.added: + warn("Already added: " + successor_rec.file_name) + else: + successor_rec.added = True + successor_rec.needs_to_run = True + nodes.append(successor_rec) + else: + if verbose(10): + msgb("NOT ALL PARENTS COMPLETED", successor_fn) + else: + if verbose(10): + msgb("NOT ALL PARENTS VISITED", successor_fn) + else: + if verbose(10): + msgb("NOT REQUIRED/NOT NEEDED TO RUN", successor_fn) + + except: + warn("node %s: did not find child node: %s" % + (n.file_name, successor_fn)) + if verbose(10): + msgb('SCAN SUCCESSORS DONE') + + def _cmd_all_outputs_visited_and_unchanged(self, cmd): + """Return True if all the outputs of the command are visited + and unchanged. If any are not visited or any are changed, + return False.""" + if not cmd.targets: + return True + for fn in cmd.targets: + rfn = os.path.realpath(fn) + vmsgb(20,"TESTING CMD TARGET:", rfn, pad = 4*' ') + if rfn in self.recs: + d = self.recs[rfn] + if d.visited == False: + vmsgb(20,"CMD TARGET NOT VISITED YET:", fn, pad=8*' ') + return False + if d.changed: + vmsgb(20,"CMD TARGET CHANGED:", fn, pad=8*' ') + return False + else: + vmsgb(20,"CMD TARGET NOT FOUND IN DAG:", fn, pad=8*' ') + vmsgb(20,"CMD TARGETS ALL VISITED AND UNCHANGED:", fn) + return True + + def _ready_scan(self,nodes): + """Process the nodes list and return a list of ready commands""" + vmsgb(20,'READY SCAN', '%d' % (len(nodes))) + readyd = dict() # ready dictionary for fast searching + vmsgb(20,"READYD0", str(readyd)) + # Pop a node off the nodes list. If that node has a creator, + # put it in the ready list. If the node has no creator put then its + # children on the nodes list. + iters = 0 + while len(nodes) != 0: + n = nodes.popleft() + iters+=1 + # see if all parents have been visited yet + parents_changed = self._just_compute_parent_changed(n) + vmsgb(20,"VISITING", n.file_name) + n.visited = True + if n.change_bit(self.required_set): + vmsgb(20,"LEAFSEARCH", "%d \tthis node %s CHANGED." % + (iters,n.file_name)) + propagate_changed = True + n.needs_to_run = True + elif parents_changed: + vmsgb(20,"LEAFSEARCH", "%d \tsome parent of %s CHANGED." % + (iters,n.file_name)) + n.changed = True # we changed because our parents changed + propagate_changed = True + n.needs_to_run = True + elif n.creator and \ + not self._check_command_signature(n.creator): + vmsgb(20,"LEAFSEARCH", "%d\tthis node's command changed: %s." % + (iters,n.file_name)) + n.changed = True # we changed because our command line changed + propagate_changed = True + n.needs_to_run = True + else: + vmsgb(20,"LEAFSEARCH", "%d\tUNCHANGED: %s." % + (iters,n.file_name)) + propagate_changed = False + + if n.creator: + # if the inputs have not changed and the signtures of + # the outputs match, then do not build the thing. Just + # mark it complete so it won't run. + + # we only mark a creator completed if all the + # command_t targets are visited unchanged. + + if not propagate_changed: + vmsgb(20,"LEAFSEARCH", "\tTESTING CMD SUCCESSORS: " + + n.file_name) + if self._cmd_all_outputs_visited_and_unchanged(n.creator): + n.creator._complete() + vmsgb(20,"LEAFSEARCH", "\tMARK CREATOR CMD COMPLETED: " + + n.file_name) + else: + vmsgb(20,"LEAFSEARCH", "\tCMD OUTPUTS NOT FULLY SCANNED YET: " + + n.file_name) + + else: + if n.creator._ready(): + vmsgb(20,"LEAFSEARCH", "\tCMD READY: " + n.file_name) + if n.file_name not in readyd: + vmsgb(20,"LEAFSEARCH", + "\tADDING CREATOR TO READYD: " + + n.file_name) + readyd[n.file_name] = n + else: + vmsgb(20,"LEAFSEARCH", + "\tCREATOR ALREADY IN READYD: " + + n.file_name) + + self._scan_successors(nodes,n) + vmsgb(20,"READYD", str(readyd)) + ready = readyd.values() + return ready + + def _find_rec_for_missing_file(self, fn, assumed_directory): + vmsgb(20,"LOOKING FOR MISSING FILE", "%s assuming %s" % + (fn, assumed_directory)) + + if fn in self.recs: + vmsgb(20,"FOUND DEP REC FOR MISSING FILE", fn) + return self.recs[fn] + if assumed_directory: + nfn = util.join(assumed_directory, fn) + if nfn in self.recs: + vmsgb(20,"FOUND DEP REC FOR MISSING FILE(2)", nfn) + return self.recs[nfn] + nfn = os.path.realpath(nfn) + if nfn in self.recs: + vmsgb(20,"FOUND DEP REC FOR MISSING FILE(3)", nfn) + return self.recs[nfn] + vmsgb(20,"NO DEP REC FOR MISSING FILE", fn) + return None + + def _make_list(self, x): # private + """Make a list from a single object if the thing is not + already a list. If it is a list, just return the list""" + if isinstance(x,list): + return x + return [ x ] + + def _scan_headers(self, xinput, header_paths, assumed_directory=None): + """Scan xinput for headers. Add those headers to the list of + files that are inputs.""" + to_scan = collections.deque() + to_scan.append(xinput) + #msgb("HDRSCAN1", xinput) + # loop scanning headers of headers... + while len(to_scan) != 0: + fn = to_scan.popleft() + #msgb("HDRSCAN2", "\t" + fn) + # r is the record of the thing we are scanning + r = self._check_add_dep_rec(fn) + + # sometimes we add stuff to the work list twice. Catch the + # dups here + if r.scanned: + continue + #msgb("HDRSCAN3", fn) + # headers is all the files that fn includes directly. One + # level scan + headers = scanner.mbuild_scan(fn, header_paths) + if verbose(4): + for hr in headers: + if hr.system: + sys="System " + else: + sys="NotSystem" + if hr.found: + fnd="Found " + else: + fnd="Missing" + msgb('HDR',"%s| %s| %s" % + ( sys, fnd, hr.file_name) ) + + r.scanned = True + + for hr in headers: + # we ignore system include files and process normal files + + if not hr.system: + scanned_header = True + if not hr.found: + # check if we have a dep record for this + # header. It might be a generated header that + # we are expecting to build. + ah = self._find_rec_for_missing_file(hr.file_name, assumed_directory) + if ah: + if verbose(4): + msgb("FOUND DEP REC FOR MISSING HEADER. WE WILL BUILD IT") + hr.file_name = ah.file_name + scanned_header = False + elif not self._check_required_file(hr.file_name): + if verbose(4): + msgb("MISSING HEADER NOT REQUIRED") + continue + elif assumed_directory: + ofn = hr.file_name + hr.file_name = util.join(assumed_directory, ofn) + if verbose(4): + msgb("ASSUMING", + "%s is in %s" % (ofn, assumed_directory)) + + + # make the hdr file name canonical. + hr.file_name = os.path.realpath(hr.file_name) + + # Make the forward & backwards links. + r.files_that_are_inputs.append(hr.file_name) + hdr_node = self._check_add_dep_rec(hr.file_name) + hdr_node.scanned_header = scanned_header + hdr_node.files_that_depend_on_this.append(fn) + + if not hdr_node.scanned: + to_scan.append(hr.file_name) + + + def _make_dep_record(self, file_name, creator=None): + if verbose(10): + msgb("MKDEP", file_name) + r = _mbuild_dep_record_t(file_name, creator) + if file_name in self.old_signatures: + r.old_signature = self.old_signatures[file_name].signature + return r + + def _check_add_dep_rec(self, fn, creator=None): + """Look to see if the file exists in our list of dependence + records. If not, add it. Return the found or created + record.""" + + rfn = os.path.realpath(fn) + + if rfn not in self.recs: + r = self._make_dep_record(rfn, creator) + self.recs[rfn] = r + else: + r = self.recs[rfn] + return r + + def _add_one_input(self, xinput, consumer_cmd): + r = self._check_add_dep_rec(xinput) + r.files_that_depend_on_this.extend(consumer_cmd.targets) + + def _add_one_output(self, output, creator=None): + r = self._check_add_dep_rec(output) + self.required_set.add(r.file_name) + if creator != None: + if r.creator: + die("Two commands create " + output) + r.creator = creator + r.files_that_are_inputs.extend(creator.inputs) + + def _make_command_object(self,d): + """Produce a command_t to add to the workqueue or for + connecting to other commands by dependence chains""" + if d.env: + # FIXME: assumes args is present + c = command_t( d.command, d.args, d.env ) + elif d.args: + c = command_t( d.command, d.args) + else: + c = command_t( d.command ) + if d.input: + c.inputs = self._make_list( d.input) + if d.output: + c.targets = self._make_list( d.output) + + if hasattr(d,'name'): + c.name = d.name + return c + + def _make_commands_depend_on_each_other(self,c): + """We just added a new command c. Now we must make sure that + the commands that create this command's inputs come before + this command. Also the commands that use this command's output + output files as inputs come after it. Not all the commands may + be known yet, but by working symmetrically here, we'll get + them all eventually.""" + + # Look at the inputs and see if any have commands we can make + # preceded this one. + for xinput in c.inputs: + try: + t = self.recs[xinput] + if t.creator: + if verbose(10): + msgb("CMD IDEP", xinput + " -> " + str(c.targets)) + t.creator.add_after_me(c) + except: + pass + + # Look at the outputs and see if the files that depend on + # these outputs have creator commands that should be after + # this one. + for output in c.targets: + # We just added this so it better be there. + if output not in self.recs: + die("Missing command for target " + output) + t = self.recs[output] + for f in t.files_that_depend_on_this: + if f in self.recs: + u = self.recs[f] + if u.creator: + if verbose(10): + msgb("ODEP", output + ' -> ' + + str(u.creator.targets)) + u.creator.add_before_me(c) + + + def results(self): + """Return a list of L{command_t}'s that were executed for + analysis of the build. If a command was not executed, it is + not returned. + + @rtype: list + @return: A list of L{command_t} objects. + """ + executed_commands = [] + for r in iter(self.recs.values()): + if r.creator: + if r.creator.completed: + executed_commands.append(r.creator) + return executed_commands + + + def add(self,env,d): + """Create a command based on the input dictionary or + L{plan_t} object. It may have inputs and + outputs. Things may have no input or output files. Return the + created L{command_t}. The command object dependence + tracking mechanism will control their execution. + + @type env: L{env_t} + @param env: the environment + @type d: dict or L{plan_t} + @param d: a dictionary or L{plan_t} + from a builder describing the command. + @rtype: L{command_t} + @return: A command object for the dependence DAG + """ + if verbose(12): + msgb("DAG ADDING", str(d)) + if isinstance(d,dict): + q = self._convert_to_dagfood(d) + c = self._add_dagfood(env,q) + elif isinstance(d,plan_t): + c = self._add_dagfood(env,d) + else: + die("Unhandled type: " + str(type(d))) + if verbose(12): + msgb("DAG ADDING", 'DONE') + + return c + + + def _canonize_one_fn(self,fn): + nfn = strip_quotes(fn) + r = os.path.realpath(nfn) + if verbose(12): + msgb("REALPATH", "%s -> %s" %(nfn, r), pad=' ') + return r + + def _canonize_fn(self,x): + x = self._make_list(x) + n = [] + for fn in x: + r = self._canonize_one_fn(fn) + n.append( r ) + return n + + def _canonize_if_exists_fn(self,x): + x = self._make_list(x) + n = [] + for fn in x: + if os.path.exists(fn): + r = self._canonize_one_fn(fn) + n.append( r ) + else: + n.append(fn) + return n + + def _add_dagfood(self,env,d): + # make sure all the command line substition has been done + if d.input: + d.input = env.expand_string(d.input) + if d.output: + d.output = env.expand_string(d.output) + + c = self._make_command_object(d) + + if verbose(12): + msgb("CANONIZE INPUTS", pad=' ') + c.inputs = self._canonize_fn(c.inputs) + if verbose(12): + msgb("CANONIZE TARGETS", pad=' ') + c.targets = self._canonize_fn(c.targets) + + for s in c.inputs: + if verbose(10): + msgb("ADD-INPUT", s, pad=' ') + self._add_one_input(s,c) + + for t in c.targets: + if verbose(10): + msgb("ADD-OUTPUT", t, pad=' ') + self._add_one_output(t,c) + + header_paths = env['CPPPATH'] + for s in c.inputs: + self._scan_headers(s, header_paths, env['gen_dir']) + return c + + def _convert_to_dagfood(self,d): + """Convert a dictionary to a plan_t""" + q = plan_t(d['command']) + try: + q.args = d['args'] + except: + pass + try: + q.input = d['input'] + except: + pass + try: + q.output = d['output'] + except: + pass + try: + q.env = d['env'] + except: + pass + return q + + + + + diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/dfs.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/dfs.py new file mode 100644 index 0000000..7f3282e --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/dfs.py @@ -0,0 +1,161 @@ +#!/usr/bin/env python +# FILE: dfs.py +# AUTHOR: Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""This file provides a node_t type and a dfs() routine that prints out +cycles found in a graph represented as a list of node_t objects. +""" +from __future__ import print_function +_dfs_verbose = False + +class node_t(object): + def __init__(self,name='no-name-for-node'): + self.name = name + self.afters = [] + self.befores = [] + self.zero() + + # The colors are: + # 0 = white (unvisited), + # 1=grey (discovered, visiting), + # 2=black (finalized) + self.color = 0 + + self.discover = 0 + self.finalize = 0 + self.predecessor = None + def zero(self): + self.color = 0 + def add_successor(self, s): + self.afters.append(s) + s.befores.append(self) + def add_ancestor(self, s): + self.befores.append(s) + s.afters.append(self) + def __str__(self): + s = [] + s.append("TARGET: %s\n\t" % self.name) + s.append("discovered %d finalized %d\n\t" % (self.discover, self.finalize)) + s.extend(["\t\n{}".format(x.name) for x in self.afters]) + return ''.join(s) + + + +def _print_cycle(last_visit, grey_loop_closer): + pad = '' + p = last_visit + while 1: + print (pad, p.name) + if p == grey_loop_closer: + break + p = p.predecessor + pad += ' ' + +def _visit(n): + global _dfs_time + n.color = 1 + n.discover = _dfs_time + if _dfs_verbose: + print ("visiting %s" % str(n)) + _dfs_time += 1 + retval = False + for a in n.afters: + if a.color == 0: + a.predecessor = n + retval |= _visit(a) + elif a.color == 1: + # a back-edge + print ("cycle") + _print_cycle(n,a) + retval = True + n.color = 2 + n.finalize = _dfs_time + _dfs_time += 1 + return retval + +def dfs(nodes): + """Depth first search a list of node_t objects. Print out cycles. + @rtype: bool + @return: True if cycles were detected. + """ + global _dfs_time + _dfs_time = 0 + for t in nodes: + t.zero() + cycle = False + for n in nodes: + if n.color == 0: + cycle |= _visit(n) + return cycle + +####################################################### + +# stuff for a strongly connected components algorithm -- currently +# unused. + +def _node_cmp(aa,bb): + return aa.finalize.__cmp__(bb.finalize) + +def _visit_transpose(n): + global _dfs_time + n.color = 1 + if _dfs_verbose: + print ("visiting %s" % str(n)) + for a in n.befores: + if a.color == 0: + _visit_transpose(a) + n.color = 2 + + +def dfs_transpose(nodes): + global _dfs_time + _dfs_time = 0 + for t in nodes: + t.zero() + nodes.sort(cmp=_node_cmp) + for n in nodes: + if n.color == 0: + _visit_transpose(n) + if _dfs_verbose: + print ("====") + +#################################################### + +def _test_dfs(): + node1 = node_t('1') + node2 = node_t('2') + node3 = node_t('3') + node4 = node_t('4') + node1.add_successor(node2) + node1.add_successor(node3) + node3.add_successor(node4) + node4.add_successor(node1) + + nodes = [ node1, node2, node3, node4 ] + cycle = dfs(nodes) + if cycle: + print ("CYCLE DETECTED") + #print ("VISIT TRANSPOSE") + #dfs_transpose(nodes) + + # print ("NODES\n", "\n".join(map(str,nodes))) + +if __name__ == '__main__': + _test_dfs() diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/doxygen.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/doxygen.py new file mode 100644 index 0000000..20afcdb --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/doxygen.py @@ -0,0 +1,360 @@ +#!/usr/bin/env python +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + + +############################################################################ +## START OF IMPORTS SETUP +############################################################################ + +import sys +import os +import re +import copy +import glob +import types + +try: + from . import base + from . import dag + from . import util + from . import plan +except: + s = "\nXED ERROR: mfile.py could not find mbuild." + \ + " Should be a sibling of the xed2 directory.\n\n" + sys.stderr.write(s) + sys.exit(1) + + +########################################################################### +## DOXYGEN SUPPORT +########################################################################### + +def _doxygen_version_okay(s, want_major, want_minor, want_fix): + values = s.split('.') + + maj =int(values[0]) + minor = int(values[1]) + fix = 0 + if len(values) > 2: + # remove everything after the dash for things like: 'Doxygen + # 1.5.1-p1' + values[2] = re.sub(r'-.*$','',values[2]) + try: + fix = int(values[2]) + except ValueError as v: + pass + if (maj > 1) or \ + (maj == want_major and minor > want_minor) or \ + (maj == want_major and minor == want_minor and fix >= want_fix): + return True + return False + +def _find_doxygen(env): + """Find the right version of doxygen. Return a tuple of the + command name and a boolean indicating whether or not the version + checked out.""" + + if env['doxygen_cmd'] == '': + doxygen_cmd_intel = "/usr/intel/bin/doxygen" + doxygen_cmd_cygwin = "C:/cygwin/bin/doxygen" + doxygen_cmd_mac = \ + "/Applications/Doxygen.app/Contents/Resources/doxygen" + doxygen_cmd = "doxygen" + + if env['build_os'] == 'win': + if os.path.exists(doxygen_cmd_cygwin): + doxygen_cmd = doxygen_cmd_cygwin + else: + base.msgb('DOXYGEN',"Could not find cygwin's doxygen," + + "trying doxygen from PATH") + elif env['build_os'] == 'lin': + if base.verbose(2): + base.msgb("CHECKING FOR", doxygen_cmd_intel) + if os.path.exists(doxygen_cmd_intel): + doxygen_cmd = doxygen_cmd_intel + elif env['build_os'] == 'mac': + if base.verbose(2): + base.msgb("CHECKING FOR", doxygen_cmd_mac) + if os.path.exists(doxygen_cmd_mac): + doxygen_cmd = doxygen_cmd_mac + else: + doxygen_cmd = env['doxygen_cmd'] + + doxygen_cmd = env.escape_string(doxygen_cmd) + doxygen_okay = False + if base.verbose(2): + base.msgb('Checking doxygen version','...') + if base.check_python_version(2,4): + try: + (retval, output, error_output) = \ + util.run_command(doxygen_cmd + " --version") + if retval==0: + if len(output) > 0: + first_line = output[0].strip() + if base.verbose(2): + base.msgb("Doxygen version", first_line) + doxygen_okay = _doxygen_version_okay(first_line, 1,4,6) + else: + for o in output: + base.msgb("Doxygen-version-check STDOUT", o) + if error_output: + for line in error_output: + base.msgb("STDERR ",line.rstrip()) + except: + base.die("Doxygen required by the command line options " + + "but no doxygen found") + + return (doxygen_cmd, doxygen_okay) + + +def _replace_match(istring, mtch, newstring, group_name): + """This is a lame way of avoiding regular expression backslashing + issues""" + x1= mtch.start(group_name) + x2= mtch.end(group_name) + ostring = istring[0:x1] + newstring + istring[x2:] + return ostring + + +def _customize_doxygen_file(env, subs): + + """Change the $(*) strings to the proper value in the config file. + Returns True on success""" + + # doxygen wants quotes around paths with spaces + for k,s in iter(subs.items()): + if re.search(' ',s): + if not re.search('^".*"$',s): + base.die("Doxygen requires quotes around strings with spaces: [%s]->[%s]" % + ( k,s)) + return False + + # input and output files + try: + lines = open(env['doxygen_config']).readlines() + except: + base.msgb("Could not open input file: " + env['doxygen_config']) + return False + + env['doxygen_config_customized'] = \ + env.build_dir_join(os.path.basename(env['doxygen_config']) + '.customized') + try: + ofile = open(env['doxygen_config_customized'],'w') + except: + base.msgb("Could not open output file: " + env['doxygen_config_customized']) + return False + + # compile the patterns + rsubs = {} + for k,v in iter(subs.items()): + rsubs[k]=re.compile(r'(?P[$][(]' + k + '[)])') + + olines = [] + for line in lines: + oline = line + for k,p in iter(rsubs.items()): + #print ('searching for', k, 'to replace it with', subs[k]) + m = p.search(oline) + while m: + #print ('replacing', k, 'with', subs[k]) + oline = _replace_match(oline, m, subs[k], 'tag') + m = p.search(oline) + olines.append(oline) + + + try: + for line in olines: + ofile.write(line) + except: + ofile.close() + base.msgb("Could not write output file: " + env['doxygen_config_customized']) + return False + + ofile.close() + return True + +def _build_doxygen_main(args, env): + """Customize the doxygen input file. Run the doxygen command, copy + in any images, and put the output in the right place.""" + + if isinstance(args, list): + if len(args) < 2: + base.die("Need subs dictionary and dummy file arg for the doxygen command " + + "to indicate its processing") + else: + base.die("Need a list for _build_doxygen_main with the subs " + + "dictionary and the dummy file name") + + (subs,dummy_file) = args + + (doxygen_cmd, doxygen_okay) = _find_doxygen(env) + if not doxygen_okay: + msg = 'No good doxygen available on this system; ' + \ + 'Your command line arguments\n\trequire it to be present. ' + \ + 'Consider dropping the "doc" and "doc-build" options\n\t or ' + \ + 'specify a path to doxygen with the --doxygen knob.\n\n\n' + return (1, [msg]) # failure + else: + env['DOXYGEN'] = doxygen_cmd + + try: + okay = _customize_doxygen_file(env, subs) + except: + base.die("CUSTOMIZE DOXYGEN INPUT FILE FAILED") + if not okay: + return (1, ['Doxygen customization failed']) + + cmd = env['DOXYGEN'] + ' ' + \ + env.escape_string(env['doxygen_config_customized']) + if base.verbose(2): + base.msgb("RUN DOXYGEN", cmd) + (retval, output, error_output) = util.run_command(cmd) + + for line in output: + base.msgb("DOX",line.rstrip()) + if error_output: + for line in error_output: + base.msgb("DOX-ERROR",line.rstrip()) + if retval != 0: + base.msgb("DOXYGEN FAILED") + base.die("Doxygen run failed. Retval=", str(retval)) + util.touch(dummy_file) + base.msgb("DOXYGEN","succeeded") + return (0, []) # success + + +########################################################################### +# Doxygen build +########################################################################### +def _empty_dir(d): + """return True if the directory d does not exist or if it contains no + files/subdirectories.""" + if not os.path.exists(d): + return True + for (root, subdirs, subfiles) in os.walk(d): + if len(subfiles) or len(subdirs): + return False + return True + +def _make_doxygen_reference_manual(env, doxygen_inputs, subs, work_queue, + hash_file_name='dox'): + """Install the doxygen reference manual the doyxgen_output_dir + directory. doxygen_inputs is a list of files """ + + dox_dag = dag.dag_t(hash_file_name,env=env) + + # so that the scanner can find them + dirs = {} + for f in doxygen_inputs: + dirs[os.path.dirname(f)]=True + for d in dirs.keys(): + env.add_include_dir(d) + + # make sure the config and top file are in the inptus list + doxygen_inputs.append(env['doxygen_config']) + doxygen_inputs.append(env['doxygen_top_src']) + + dummy = env.build_dir_join('dummy-doxygen-' + hash_file_name) + + # Run it via the builder to make it dependence driven + run_always = False + if _empty_dir(env['doxygen_install']): + run_always = True + + if run_always: + _build_doxygen_main([subs,dummy], env) + else: + c1 = plan.plan_t(command=_build_doxygen_main, + args= [subs,dummy], + env= env, + input= doxygen_inputs, + output= dummy) + dox1 = dox_dag.add(env,c1) + + okay = work_queue.build(dag=dox_dag) + phase = "DOXYGEN" + if not okay: + base.die("[%s] failed. dying..." % phase) + if base.verbose(2): + base.msgb(phase, "build succeeded") + + +############################################################ + +def doxygen_env(env): + """Add the doxygen variables to the environment""" + doxygen_defaults = dict( doxygen_config='', + doxygen_top_src='', + doxygen_install='', + doxygen_cmd='' ) + env.update_dict(doxygen_defaults) + +def doxygen_args(env): + """Add the knobs to the command line knobs parser""" + + env.parser.add_option("--doxygen-install", + dest="doxygen_install", + action="store", + default='', + help="Doxygen installation directory") + + env.parser.add_option("--doxygen-config", + dest="doxygen_config", + action="store", + default='', + help="Doxygen config file") + + env.parser.add_option("--doxygen-top-src", + dest="doxygen_top_src", + action="store", + default='', + help="Doxygen top source file") + + env.parser.add_option("--doxygen-cmd", + dest="doxygen_cmd", + action="store", + default='', + help="Doxygen command name") + + +def doxygen_run(env, inputs, subs, work_queue, hash_file_name='dox'): + """Run doxygen assuming certain values are in the environment env. + + @type env: env_t + @param env: the environment + + @type inputs: list + @param inputs: list of input files to scan for dependences + + @type subs: dictionary + @param subs: replacements in the config file + + @type work_queue: work_queue_t + @param work_queue: a work queue for the build + + @type hash_file_name: string + @param hash_file_name: used for the dummy file and mbuild hash suffix + """ + _make_doxygen_reference_manual(env, inputs, subs, work_queue, hash_file_name) + + + + + diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/env.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/env.py new file mode 100644 index 0000000..acba59a --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/env.py @@ -0,0 +1,2134 @@ +#!/usr/bin/env python +# -*- python -*- +# Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""Environment support""" +from __future__ import print_function +import os +import sys +import re +import platform +import types +import optparse +import time +import copy + +from .base import * +from . import util +from . import build_env +from . import plan +from . import msvs + + +def _remove_libname(args,env): + #lib = env.expand('%(LIBNAME)s') + lib = args[0] + vmsgb(1, "REMOVING", lib) + util.remove_file(lib) + return (0,['REMOVED %s\n' % ( lib )]) + +# 2014-04-02: Intel has 2 compilers for mac: icc and icl. Intel now +# calls their mac llvm-based comiler "icl". This confuses thing with +# the name of the windows intel compiler which is also called "icl". +# In mbuild, we call the Intel llvm-based compiler "iclang" to +# disambiguate the conflict. + +class env_t(object): + """The is the environment for compilation. The environment + includes a dictionary for holding everything custom about this + environment. The default environment includes: + + - command line options. These are also in the environment dictionary. + - build_dir defaultE{:} obj + - src_dir defaultE{:} . or path to the mfile + - gen_dir defaultE{:} None (default path for generated files, if set) + - shared defaultE{:} False (default: no shared libraries) + - static defaultE{:} False (default: not to statically link) + - opt defaultE{:} 'noopt' (could be 'noopt, 0,1,2,3) + - debug defaultE{:} False + - separate_pdb_files defaultE{:} False + - targets defaultE{:} [] targets to build + - verbose defaultE{:} 1 + - compiler defaultE{:} 'gnu', 'ms', 'clang', 'icc', 'icl', 'iclang' + - extra_defines defaultE{:} '' + - extra_flags defaultE{:} '' (for both CXXFLAGS & CCFLAGS) + - extra_cxxflags defaultE{:} '' + - extra_ccflags defaultE{:} '' + - extra_linkflags defaultE{:} '' + - extra_libs defaultE{:} '' + - use_yasm defaultE{:} False + + - CPPPATH defaultE{:} [] The list of include paths + - SYSTEMINCLUDE defaultE{:} [] The list of system include paths (Not + supported by MSVS). + - DEFINES defaultE{:} {} The dictionary of defines + + + - short names for the primary compiler toolsE{:} + - CXX_COMPILER cl or g++ + - CC_COMPILER cl or gcc + - ASSEMBLER ml/ml64 or gcc/gas (gcc is the default for gnu) + - LINKER link or g++/gcc (g++ is the default for gnu) + - ARCHIVER ar + - RANLIB_CMD ranlib + + - toolchain path to the compiler tools (default is ''). If toolchain is + set, it should end with a trailing slash. + - vc_dir path to the compiler VC directory for MSVS (default is '')n + - icc_version 7, 8, 9, 10, ... + - gcc_version 2.96, 3.x.y, 4.x.y, ... + - msvs_version 6 (VC98), 7 (.NET 2003), 8 (Pro 2005), ... + + - primary compilation toolsE{:} + - CC cl or gcc (with toolchain path) + - CXX cl or g++ (with toolchain path) + - AS ml,ml64 or gcc/gas (with toolchain path) + - LINK link or gcc/g++ (with toolchain path) + - AR lib or ar (with toolchain path) + - RANLIB ranlib (with toolchain path) + - flags for primary toolsE{:} + - CCFLAGS + - CXXFLAGS + - ASFLAGS + - ARFLAGS + - LINKFLAGS + - LIBS (libraries for the end of the link statement) + + - preprocessor flags + - DOPT /D or -D + - ASDOPT /D or -D + - IOPT /I or -I + - OPTPOPT /O or -O + - DEBUGOPT /Zi or -g + + - options to control compilation outputE{:} + - COPT /c or -c + - COUT /Fo or -o + - ASMOUT /Fo or -o + - LIBOUT /outE{:} or -o + - LINKOUT /OUTE{:} or -o + - DLLOPT -shared + + - Override-buildersE{:} set these to a function pointer if you want + to replace the default builder function. + + - ASSEMBLE_BUILDER if not set default is to use assemble_default() + - CXX_COMPILE_BUILDER if not set default is to use cxx_default() + - CC_COMPILE_BUILDER if not set default is to use cc_default() + - LINK_BUILDER if not set default is to use link_default() + - STATIC_LIBRARY_BUILDER if not set default is to use static_lib_default() + - DYNAMIC_LIBRARY_BUILDER if not set default is to use dynamic_lib_default() + + - default extensionsE{:} + - OBJEXT .obj or .o + - LIBEXT .lib or .a + - DLLEXT .dll, .so, or .dylib + - EXEEXT .exe or '' + + - System valuesE{:} + - uname standard python tuple of values from uname. + - system standard valuesE{:} 'Linux', 'Windows', 'Darwin', 'Microsoft', 'FreeBSD', 'NetBSD' + - hostname + - build_os standard valuesE{:} 'lin', 'win', 'mac', 'bsd' + - host_os standard valuesE{:} 'lin', 'win', 'mac', 'bsd' + - build_cpu standard valuesE{:} 'ia32', 'x86-64', 'ipf' + - host_cpu standard valuesE{:} 'ia32', 'x86-64', 'ipf' + + """ + + obj_pattern = re.compile(r'.obj$') + objext_pattern = re.compile(r'[%][(]OBJEXT[)]s$') + + mbuild_subs_pattern = re.compile('%[(][^)]+[)]') + #FIXME: no backslashes in patterns! + assignment_pattern = re.compile(r'(?P[-A-Za-z0-9_]+)[=](?P.+)') + supplement_pattern = re.compile(r'(?P[-A-Za-z0-9_]+)[+][=](?P.+)') + + def version(self): + """Emit the version string. + @rtype: string + @return: The version string + """ + # FIXME: could put an Id in each sub-module and look at the + # doc strings for each one. + msgb("VERSION", "$Id: mbuild_env.py 44 2007-03-16 15:54:44Z mjcharne $") + def __setitem__(self,k,value): + """Write a value to the environment dictionary""" + if util.is_stringish(value): + self.env[k] = util.posix_slashes(value) + else: + self.env[k] = value + def __contains__(self,k): + if k in self.env: + return True + return False + + def __getitem__(self,k): + """Read the environment dictionary. Not doing any + substitutions.""" + + try: + return self.env[k] + except: + die("env key not found: %s" % (k)) + + def expand(self, command_string, newenv=None): + """Alias for expand_string()""" + return self.expand_string(command_string, newenv) + + def expand_string(self, command_string, newenv=None): + """Read the environment dictionary, doing recursive + substitutions from the environment. If no environment is + supplied, then the default environment is used. + + @type command_string: string or list of strings + @param command_string: A string with %(...)s variables in it + @type newenv: L{env_t} + @param newenv: An environment within which to do the expansion. If + null, the default environment is used. + @rtype: string + """ + if newenv == None: + newenv = self.env + if util.is_stringish(command_string): + return self._iterative_substitute(command_string, newenv) + if isinstance(command_string, list): + return [ self._iterative_substitute(x, newenv) for x in command_string ] + die("expand_string only handles substitution in strings or lists of strings") + + def expand_key(self,k, newenv=None): + """Read the the value of k from the environment dictionary, + doing recursive substitutions from the environment. If no + environment is supplied, then the default environment is used. + + @type k: string or list of strings + @param k: A string (or strings) containing a single key name(s) + @type newenv: L{env_t} + @param newenv: An environment within which to do the expansion. If + null, the default environment is used. + @rtype: string + """ + if newenv == None: + newenv = self.env + if k not in newenv: + die("Could not find %s in the environment" % k) + + + if isinstance(newenv[k],list): + # We must process each string in the list and do + # substitutions on them. For example, CPPPATH + return [ self._iterative_substitute(x,newenv) for x in newenv[k]] + if util.is_stringish(newenv[k]): + return self._iterative_substitute("%(" + k + ")s", newenv) + # non strings (scalars) + return newenv[k] + + def _mysub(self,input, keyname, newval): + """Replace %(keyname)s in input with newval""" + # only handling %(...)s replacement. Nothing fancy. + s = '%('+keyname+')s' + # simple string replacement, not regexp replacement + output = input.replace(s,newval) + return output + + + def _iterative_substitute(self,s,dct1,debug=False): + """Replace all the %(...)s with values in s from the + dictionary dct1. Note, the dictionary can contain tuples of + the form (key, dict). In this case, this code uses the lookup + result of dct1[key] to query yet the dictionary dict. That + lookup can result in a string or another such tuple.""" + #error_msg("iterative_substitute", str(s)) + subs_pattern = re.compile('%[(](?P[^)]+)[)]s') + t = s + m = subs_pattern.search(t) + while m: + name = m.group('name') + if name not in dct1: + die("Bad substitution for " + name) + v = dct1[name] + # repeatedly expand any tuples that show up. + while not util.is_stringish(v): + if isinstance(v,tuple): + (key, dct) = v + + # look up key in the main dictionary to create a + # subkey for use in the 2nd level dictionary + + try: + subkey = dct1[key] + except: + die("nested dictionary lookup error during iterative string " + + " expansion. key=%s" % (str(key))) + + try: + v = dct[ subkey ] + except: + try: + v = dct['otherwise'] + except: + die("nested dictionary lookup error during iterative string " + + " expansion. key=%s subkey=%s" % (str(key),str(subkey))) + elif isinstance(v,types.FunctionType): + try: + v = v(dct1) + except: + die("Bad function invokation during iterative string expansion") + else: + die("Bad environment value: " + str(v) + + " when searching: " + s) + t = self._mysub(t,name,v) + m = subs_pattern.search(t) + if debug: + uprint(t) + return t + + def _dosub_old(self,s,d): + """Repeatedly substitute values from the dictionary d into the + string s while '%(...)' substrings remain in the thing we want + to return. If the input s is a list, then we recursively + expand each element of that list""" + + if isinstance(s,list): + return [ self.dosub(x,d) for x in s] + + # The common case: Just expanding a simple string. + t = s + while env_t.mbuild_subs_pattern.search(t): + t = t % d + return t + + def __str__(self): + """Print out the environment""" + s = [] + s.append("BUILD_CPU:") + s.append(self.env['build_cpu']) + s.append("HOST_CPU:") + s.append(self.env['host_cpu']) + s.append("\nBUILD_OS: ") + s.append(self.env['build_os']) + s.append("\nHOST_OS: ") + s.append(self.env['host_os']) + s.append("\nUNAME: ") + s.append(str(self.env['uname'])) + s.append("\nHOSTNAME: ") + s.append(self.env['hostname']) + s.append("\nSYSTEM: ") + s.append(self.env['system']) + s.append("\nDICTIONARY:\n") + for k,v in iter(self.env.items()): + s.append("\t") + s.append(k) + s.append("->") + s.append(str(v)) + s.append("\n") + return ''.join(s) + + def verbose_startup(self): + if self._emitted_startup_msg: + return + self._emitted_startup_msg = True + if verbose(2): + msgb("INVOKED", " ".join(sys.argv)) + msgb("START TIME", self.env['start_time_str']) + msgb("CURRENT DIRECTORY", os.getcwd()) + + msgb('UNAME', str(self.env['uname']).replace(':','_')) + msgb('SYSTEM', self.env['system']) + msgb('HOSTNAME', self.env['hostname']) + msgb("BUILD_OS", self.env['build_os']) + msgb("BUILD_CPU", self.env['build_cpu']) + msgb("HOST_OS", self.env['host_os']) + msgb("HOST_CPU", self.env['host_cpu']) + + def _check_registry_environment(self,env_var): + s = 'SYSTEM\\CurrentControlSet\\Control\\Session Manager\\Environment' + is_py2 = sys.version[0] == '2' + try: + if is_py2: + import _winreg as winreg + else: + import winreg + key = winreg.OpenKey(winreg.HKEY_LOCAL_MACHINE, s) + (val, typ) = winreg.QueryValueEx(key, env_var) + return val + except: + die(("Could not read windows registry for variable %s.\n" % \ + (env_var)) + + "Use win32 python and install pywin32") + + def _check_processor_identifier_windows(self): + + return self._check_registry_environment('PROCESSOR_IDENTIFIER') + + + def _check_number_of_processors_windows(self): + return self._check_registry_environment('NUMBER_OF_PROCESSORS') + + + def __init__(self, init_verbose=1, default_knobs=True): + """Build up the environment for compilation. + """ + set_verbosity(int(init_verbose)) + self.env = {} + self.parsed_args = False + self.added_common_knobs=False + self.added_default_knobs=False + self.env['python'] = sys.executable + self.env['CPPPATH'] = [] + self.env['SYSTEMINCLUDE'] = [] + self.env['DEFINES'] = {} + + self.env['LINKPATH'] = [] + self.env['LINKDIRS'] = '' + self.env['LINKFLAGS'] = ' %(LINKDIRS)s ' + + self.env['targets'] = [] + + # defaults for the build dir and src dir + self.env['build_dir'] = 'obj' + self.env['src_dir'] = '' # we set this accordingly + self.env['gen_dir'] = None # location of generated files that do not exist + self.env['shared'] = False + self.env['static'] = False + self.env['debug'] = False + self.env['separate_pdb_files'] = False + self.env['opt'] = 'noopt' + + self.env['LIBS'] = '' # default link libraries + self.env['CXX_COMPILER'] = '' + self.env['CC_COMPILER'] = '' + self.env['ASSEMBLER'] = '' + self.env['LINKER'] = '' + + + # windows rc tool for dll resource files. + self.env['RC'] = '' + self.env['RC_CMD'] = '' + self.env['RCFLAGS'] = '' + + # use_compiler_to_link = True if using the compiler to link. + # use_compiler_to_link = False if using the linker to link + self.env['use_compiler_to_link'] = False + self.env['ARCHIVER'] = '' + self.env['RANLIB_CMD'] = '' + + self.env['CXX'] = '' + self.env['CC'] = '' + self.env['LINK'] = '' + self.env['AR'] = '' + self.env['AS'] = '' + self.env['RANLIB'] = '' + + # python3.9 breaks copy.deepcopy() of platform.uname() return + # values so we make our own. + self.env['uname'] = ( platform.system(), + platform.node(), + platform.release(), + platform.version(), + platform.machine() ) + + self.env['hostname'] = platform.node() + self.env['system'] = platform.system() # sort of like build_os + + # distro is the empty string on mac and windows + distro = '' + distro_ver = '' + if not self.on_mac() and not self.on_windows(): + if util.check_python_version(3,8): + # With python 3.8 one needs to install the python "distro" + # package to obtain the linux distro information. I do not + # want to require users to install a non-default package + # so we'll have to live without the distro information. + # People who require it can "python3 -m pip install distro" + try: + import distro + (distro, distro_ver, distro_id) = distro.linux_distribution() + except: + distro = "linux-unknown" + distro_ver = "unknown" + + elif util.check_python_version(2,6): + (distro, distro_ver, distro_id) = platform.linux_distribution() + + self.env['distro'] = distro.strip() + self.env['distro_version'] = distro_ver + + + if 'HOME' in os.environ: + self.env['home'] = os.environ['HOME'] + elif self.on_windows() and 'USERPROFILE' in os.environ: + self.env['home'] = os.environ['USERPROFILE'] + else: + self.env['home'] = 'unknown' + + # the colons in the time string are replaced by underscores. + # The colons confused xemacs compilation mode error + # parsing. (emacs was fine) + + self.env['start_time_str'] = re.sub(":","_",util.get_time_str()) + self.start_time = util.get_time() + + #Old versions of mbuild used target_cpu erroneously instead of + #host_cpu. We do a little magic later to try to make those old + #uses continue to work. + self.env['target_cpu']=None + + if self.env['system'] in [ 'Linux', 'FreeBSD', 'NetBSD']: + uname = platform.uname() + self.env['build_os'] = self._normalize_os_name(uname[0]) + + self.env['build_cpu'] = \ + self._normalize_cpu_name(uname[4]) + + elif self.env['system'] in [ 'Darwin']: + uname = platform.uname() + self.env['build_os'] = self._normalize_os_name(uname[0]) + x = uname[4] + if self._check_mac_64b(): + x = 'x86_64' + self.env['build_cpu'] = \ + self._normalize_cpu_name(x) + elif self.on_windows(): + self.env['build_os'] = self._normalize_os_name(os.environ['OS']) + if 'PROCESSOR_IDENTIFIER' in os.environ: + p = os.environ['PROCESSOR_IDENTIFIER'] + else: + p = self._check_processor_identifier_windows() + self.env['build_cpu'] = \ + self._normalize_cpu_name(p) + + else: + die("Unknown platform") + + # where the compiled thing runs, not where it is built + # but that is the starting default. + self.env['host_cpu'] = self.env['build_cpu'] + self.env['host_os'] = self.env['build_os'] + + self._add_compilation_support() + + + self._emitted_startup_msg = False + + mbuild_env_defaults = dict( + args = [], + mbuild_version=False, + jobs='4', + build_dir='obj', + src_dir='', + gen_dir=None, + verbose= -1, + arg_host_cpu=None, + arg_host_os=None, + compiler=self.default_compiler(), + debug=False, + shared=False, + static=False, + opt='noopt', + silent=False, + extra_defines=[], + extra_flags=[], + extra_cxxflags=[], + extra_ccflags=[], + extra_linkflags=[], + extra_libs=[], + toolchain='', + ignorable_files=[], # deprecated, unused 2011-10-20 + required_files=[], + vc_dir='', + msvs_version='', + setup_msvc=False, + icc_version='', + gcc_version='', + cc='', + cxx='', + linker='', + ar='', + + use_yasm=False, + cygwin_limit_jobs=True + ) + + # as is a keyword so must set it separately + mbuild_env_defaults['as']='' + + # store the default if we ever need them + self.env_defaults = mbuild_env_defaults + # put them in the initial environment + self.update_dict(mbuild_env_defaults) + + self.parser = optparse.OptionParser() + # set the defaults in the command line option parser + self.parser.set_defaults(**mbuild_env_defaults) + + if default_knobs: + self.add_common_knobs() + self.add_default_knobs() + + + def add_common_knobs(self): + if self.added_common_knobs: + return + self.added_common_knobs=True + self.parser.add_option( + "-j", "--jobs", + dest="jobs", + action="store", + help="Number of concurrent worker threads to use.") + + def add_default_knobs(self): + if self.added_default_knobs: + return + self.added_default_knobs=True + self.parser.add_option( + "--mbuild-version", + dest="mbuild_version", + action="store_true", + help="Emit the version information") + self.parser.add_option( + "--build-dir", + dest="build_dir", + action="store", + help="Build directory, default is 'obj'") + self.parser.add_option( + "--src-dir", + action="store", + dest="src_dir", + help="The directory where the sources are located.") + self.parser.add_option( + "--gen-dir", + action="store", + dest="gen_dir", + help="The directory where generated sources are assumed" + + " to be located.") + self.parser.add_option( + "-v", + "--verbose", + action="store", + dest="verbose", + help="Verbosity level. Defaults to value passed to env_t()") + self.parser.add_option( + "--compiler", + dest="compiler", + action="store", + help="Compiler (ms,gnu,clang,icc,icl,iclang)." + + " Default is gnu on linux and" + + " ms on windows. Default is: %s" % (self.default_compiler())) + self.parser.add_option( + "--debug", + dest="debug", + action="store_true", + help="Debug build") + self.parser.add_option( + "--shared", + dest="shared", + action="store_true", + help="Shared DLL build") + self.parser.add_option( + "--static", + dest="static", + action="store_true", + help="Statically link executables") + self.parser.add_option( + "--opt", + dest="opt", + action="store", + help="Optimization level noopt, 0, 1, 2, 3") + self.parser.add_option( + "-s", + "--silent", + dest="silent", + action="store_true", + help="Silence all but the most important messages") + self.parser.add_option( + "--extra-defines", + dest="extra_defines", + action="append", + help="Extra preprocessor defines") + self.parser.add_option( + "--extra-flags", + dest="extra_flags", + action="append", + help="Extra values for CXXFLAGS and CCFLAGS") + self.parser.add_option( + "--extra-cxxflags", + dest="extra_cxxflags", + action="append", + help="Extra values for CXXFLAGS") + self.parser.add_option( + "--extra-ccflags", + dest="extra_ccflags", + action="append", + help="Extra values for CCFLAGS") + self.parser.add_option( + "--extra-linkflags", + dest="extra_linkflags", + action="append", + help="Extra values for LINKFLAGS") + self.parser.add_option( + "--extra-libs", + dest="extra_libs", + action="append", + help="Extra values for LIBS") + self.parser.add_option( + "--toolchain", + dest="toolchain", + action="store", + help="Compiler toolchain") + self.parser.add_option( + "--vc-dir", + dest="vc_dir", + action="store", + help="MSVS Compiler VC directory. For finding libraries " + + " and setting the toolchain") + self.parser.add_option( + '--msvs-version', + '--msvc-version', + '--msvsversion', + '--msvcversion', + dest='msvs_version', + action='store', + help="MSVS version 6=VC98, 7=VS .Net 2003, 8=VS 2005, " + + "9=VS2008, 10=VS 2010/DEV10, 11=VS2012/DEV11, 12=VS2013, " + + "14=VS2015, 15=VS2017, 16=VS2019. " + + "This sets certain flags and idioms for quirks in some compilers.") + self.parser.add_option( + '--setup-msvc', + '--setup-msvs', + '--msvs-setup', + '--msvc-setup', + dest='setup_msvc', + action='store_true', + help="Use the value of the --msvc-version to initialize" + + " the MSVC configuration.") + self.parser.add_option( + '--icc-version', + '--iccver', + '--icc-ver', + dest='icc_version', + action='store', + help="ICC/ICL version 7, 8, 9, 10, 11") + self.parser.add_option( + '--gcc-version', + '--gccversion', + '--gcc-ver', + dest='gcc_version', + action='store', + help="GCC version, with dots as in 2.96, 3.4.3, 4.2.0, etc. ") + + self.parser.add_option( + "--cc", + dest="cc", + action="store", + help="full path to C compiler") + self.parser.add_option( + "--cxx", + dest="cxx", + action="store", + help="full path to C++ compiler") + self.parser.add_option( + "--linker", + dest="linker", + action="store", + help="full path to linker") + self.parser.add_option( + "--ar", + dest="ar", + action="store", + help="full path to archiver (lib/ar)") + self.parser.add_option( + "--as", + dest="as", + action="store", + help="full path to assembler (gas/as/ml/ml64)") + + self.parser.add_option( + "--yasm", + dest="use_yasm", + action="store_true", + help="Use yasm") + self.parser.add_option( + "--no-cygwin-limit", + dest="cygwin_limit_jobs", + action="store_false", + help="Do not limit cygwin to one job at a time. " + + " Default is to limit cygwin to one job.") + + self.parser.add_option( + "--host-cpu", + dest="arg_host_cpu", + action="store", + help="Host CPU, typically ia32, intel64 or x86-64") + + self.parser.add_option( + "--host-os", + dest="arg_host_os", + action="store", + help="Host OS (where the binary runs)") + + def _implied_compiler(self,dct): + """If one of the icc_version, gcc_version_ or msvs_version + variables are set, deduce the compiler variable setting.""" + + # windows default is ms so no need to set that. + if dct['icc_version'] != '': + if self.on_windows(): + dct['compiler'] = 'icl' + else: + dct['compiler'] = 'icc' + if dct['gcc_version'] != '': + dct['compiler'] = 'gnu' + + def _check_mac_ncpu(self): + """How many CPUs on a mac""" + + cmd = "/usr/sbin/sysctl hw.ncpu" + (retval,output, error_output) = util.run_command(cmd) + if retval == 0 and len(output)>0: + if re.match('hw.ncpu', output[0]): + n = int(re.sub('hw.ncpu: ','',output[0])) + return n + return 0 + + def number_of_cpus(self): + """Return the number of CPUs or 0 if we don't know anything for sure""" + n = 0 + if self.on_mac(): + n = self._check_mac_ncpu() + elif self.on_windows(): + ns = "NUMBER_OF_PROCESSORS" + if ns in os.environ: + nsv = os.environ[ns] + else: + nsv = self._check_number_of_processors_windows() + n = int(nsv) + elif self.on_freebsd(): + getconf = "/usr/bin/getconf" + if os.path.exists(getconf): + cmd = "%s NPROCESSORS_ONLN" % (getconf) # or NPROCESSORS_CONF + (retval, output, error_output) = util.run_command(cmd) + if retval == 0 and len(output)>0: + n = int(output[0]) + elif self.on_netbsd(): + sysctl = "/sbin/sysctl" + if os.path.exists(sysctl): + cmd = "%s -n hw.ncpuonline" % (sysctl) + (retval, output, error_output) = util.run_command(cmd) + if retval == 0 and len(output)>0: + n = int(output[0]) + else: + f = '/proc/cpuinfo' + proc_pat= re.compile(r'proces') + if os.path.exists(f): + for line in open(f,'r'): + if proc_pat.search(line): + n += 1 + return n + + def update_dict(self, dct): + """Update the environment dictionary with another dictionary.""" + self.env.update(dct) + + def copy_settings(self, incoming_env, kwds, replace=False): + + """Update the environment dictionary with elements of kwds + from the dictionary in the incoming_env. Lists are extended with the + incoming elements and other types of elements are assigned directly. + + @type incoming_env: env_t + @param incoming_env: the source environment + + @type kwds: list of strings + @param kwds: elements to copy from the source enviornment + + @type replace: bool + @param replace: if True, replace lists in the source environment + """ + for k in kwds: + if k in incoming_env: + t = incoming_env[k] + if isinstance(t,list) and replace==False: + self.env[k].extend(t) + else: + self.env[k] = t + else: + die("copy_settings() could not read key %s from incoming environment" % k) + + def update(self, targets=None): + """Post process the current environment, setting targets and bindings""" + + # if the dct['args'] exists, supplement the targets list with + # that. This is how non-command-line invocations of mbuild + # pass the "other stuff" + if targets == None: + targets = [] + + if not isinstance(targets,list): + die("The 'targets' environment option must be a list") + + if 'args' in self.env: + args = self.env['args'] + if isinstance(args,list): + targets.extend(args) + else: + die("The 'args' environment option must be a list") + + # split up the targets list so we can extract the command line + # variable bindings + just_targets = [] + bindings = [] + for t in targets: + ap = env_t.assignment_pattern.match(t) + if ap: + msgb("BINDING", "%s --> [%s]" % + (ap.group('name'), ap.group('value'))) + bindings.append( (ap.group('name'), + ap.group('value'), 'equals' )) + continue + sp = env_t.supplement_pattern.match(t) + if ap: + msgb("BINDING", "%s --> [%s]" % + (ap.group('name'), ap.group('value'))) + bindings.append( (ap.group('name'), + ap.group('value'), 'plusequals') ) + continue + just_targets.append(t) + + # add command line variable bindings to the environment + for (var,value, how) in bindings: + if how == 'equals': + self.env[var] = value + + # early versions of mbuild used target_cpu instead of + # host_cpu. This next override compensates for that, + # compatibility with older clients. + if var == 'target_cpu': + self.env['host_cpu'] = value + + elif how == 'plusequals': + self.add_to_var(var,value) + + # give precidence to the knob for --host-cpu and --host-os + # over the default binding. + if self.env['arg_host_cpu']: + self.env['host_cpu'] = self.env['arg_host_cpu'] + if self.env['arg_host_os']: + self.env['host_os'] = self.env['arg_host_os'] + + # make sure we understand what host cpu we are dealing + # with. If someone puts in an Intel64 it'll come out as + # x86-64. + + self.env['host_cpu'] = self._normalize_cpu_name(self.env['host_cpu']) + self.env['host_os'] = self._normalize_os_name(self.env['host_os']) + self.add_to_var('targets',just_targets) + + # old versions of mbuild used target_cpu. To allow them to + # continue to work, we copy target_cpu to host_cpu if + # target_cpu is non null and differs from the setting for the + # host_cpu and the host_cpu is the same as the build_cpu. If + # the host_cpu and build_cpu differ, someone must have set + # host_cpu so leave it alone in that case. + + if self.env['target_cpu']: + if self.env['target_cpu'] != self.env['host_cpu']: + # build_cpu and host_cpu start out the same, so only + # change host_cpu if it has the original value. + if self.env['build_cpu'] == self.env['host_cpu']: + self.env['host_cpu'] = self.env['target_cpu'] + + + def process_user_settings(self): + """Set the initial derived environment settings""" + + self.update() + + if self.env['mbuild_version']: + self.version() + sys.exit(0) + + self._implied_compiler(self.env) + + if self.env['silent']: + set_verbosity(0) + else: + arg_verbosity = int(self.env['verbose']) + if arg_verbosity >= 0: + set_verbosity( arg_verbosity ) + self.verbose_startup() + + # convert several of the lists to strings + for f in ['extra_cxxflags', 'extra_ccflags', 'extra_linkflags', + 'extra_libs', 'extra_flags']: + self._flatten_list_to_string(f,self.env) + # distribute the "extra" flags. + if self.env['extra_flags']: + self.env['extra_cxxflags'] += ' ' + self.env['extra_flags'] + self.env['extra_ccflags'] += ' ' + self.env['extra_flags'] + + # This starts the compilation environment off CLEAN + self.set_compiler_env() + + # if the user did not use --src-dir, then we check the path to + # the mbuild script. If it there is no path, we assume we are + # in the right directory. If there is a path, we assume that + # is where the sources are, and change the option before anyone + # can see it. + if self.env['src_dir'] == '': + (path_to_src, this_file) = os.path.split(sys.argv[0]) + if path_to_src == '': + path_to_src = '.' + self.env['src_dir'] = util.posix_slashes(path_to_src) + + # This works around a longstanding python-specific bug in + # cygwin with running multiple threads. + if self.on_windows(): + try: + import win32api # we don't use it. We just test for it. + except: + if self.env['cygwin_limit_jobs'] and self.on_cygwin(): + msgb('NOTE', + 'Using just one worker thread to avoid' + \ + ' a cygwin threading problem.') + self.env['jobs'] = "1" + + # if 0 jobs were specified, try to use 2x the number of cpus. + if self.env['jobs'] == '0': + n = self.number_of_cpus() + if n: + self.env['jobs'] = str(2*n) + msgb('NOTE', + 'Setting jobs to %d, 2x the detected number of CPUs (%d)' % + (2*n,n)) + else: + self.env['jobs'] = "1" + msgb('NOTE', + 'Setting jobs to 1 because we could not detect' + + ' the number of CPUs') + + if verbose(2): + # print host_cpu here because it may be overridden for + # cross compilations + msgb("HOST_CPU", self.env['host_cpu']) + + + + + def _flatten_list_to_string(self, field, dct): + """See if options has a field named field. If it does and its + value is a list, flatten the list, joining the substrings with + spaces.""" + if field in dct: + v = dct[field] + if isinstance(v,list): + vflat = ' '.join(v) + dct[field]= vflat + + def set_defaults(self, dct): + + """Take the dictionary of defaults and apply to the + environment. Any extra bindings and targets should be listed + in the 'args' list option of the dictionary""" + + self.parser.set_defaults(**dct) + self.update_dict(dct) + + + + def parse_args(self, user_default_options=None): + """Call this to re-initialize the environment from the command + line arguments. This calls update() with the results of + command line processing. + @type user_default_options: dict + @param user_default_options: dictionary of default options + """ + + # make parse_args() runnable only once per environment. + # ("append"-mode arguments get messed up if args parsed + # more than once.) + if self.parsed_args: + return + self.parsed_args=True + + if user_default_options: + # pass a dictionary where keyword args are expected using + # "**" SEE: + # http://docs.python.org/tut/node6.html#SECTION006740000000000000000 + self.parser.set_defaults(**user_default_options) + + (options, args) = self.parser.parse_args() + dct = vars(options) + dct['args'].extend(args) + self.update_dict(dct) + + self.process_user_settings() + + + def on_ipf(self): + """@rtype: bool + @return: True iff on IA64""" + if self.env['build_cpu'] == 'ipf': + return True + return False + + def on_ia32(self): + """@rtype: bool + @return: True iff on IA32""" + if self.env['build_cpu'] == 'ia32': + return True + return False + + def on_intel64(self): + """@rtype: bool + @return: True iff on Intel64""" + if self.env['build_cpu'] == 'x86-64': + return True + return False + + def on_mac(self): + """@rtype: bool + @return: True iff on Mac OSX Darwin""" + if self.env['system'] == 'Darwin': + return True + return False + + def mac_ver(self): + val = [0]*3 + if self.on_mac(): + version_string = platform.mac_ver()[0] + chunks = version_string.split('.') + for i,c in enumerate(chunks): + val[i]=int(c) + return tuple(val) + + def check_mac_ver(self, x,y,z): + """@rtype: bool + @return: True iff on a mac and the version is later than x.y.z""" + if self.on_mac(): + (maj,min,rev) = self.mac_ver() + if x > maj: + return False + if x == maj and y > min: + return False + if x == maj and y == min and z > rev: + return False + return True + return False + + def on_tiger(self): + """@rtype: bool + @return: True iff on Mac running OS X Tiger 10.4.x""" + if self.check_mac_ver(10,4,0): + return True + return False + def on_leopard(self): + """@rtype: bool + @return: True iff on Mac running OS X Leopard 10.5.x""" + if self.check_mac_ver(10,5,0): + return True + return False + + def on_freebsd(self): + """@rtype: bool + @return: True iff on freebsd""" + if self.env['system'] == 'FreeBSD': + return True + return False + + def on_netbsd(self): + """@rtype: bool + @return: True iff on netbsd""" + if self.env['system'] == 'NetBSD': + return True + return False + + def on_linux(self): + """@rtype: bool + @return: True iff on linux""" + if self.env['system'] == 'Linux': + return True + return False + + def on_cygwin(self): + """@rtype: bool + @return: True iff on cygwin""" + if len(self.env['system']) >= 6 and self.env['system'][0:6] == 'CYGWIN': + return True + return False + + def windows_native(self): + """@rtype: bool + @return: True iff on windows native -- not using cygwin""" + if self.env['system'] == 'Windows' or self.env['system'] == 'Microsoft': + return True + return False + + def on_windows(self): + """@rtype: bool + @return: True iff on windows""" + if self.windows_native(): + return True + return self.on_cygwin() + + def supports_avx(self): + """Return True if system supports AVX1. Does not work + on windows""" + if self.on_linux(): + with open('/proc/cpuinfo','r') as fp: + for l in fp: + if 'avx' in l: + return True + elif self.on_mac(): + cmd = "/usr/sbin/sysctl hw.optional.avx1_0" + (retval, output, error_output) = util.run_command(cmd) + if retval == 0 and len(output)>0: + if re.match('hw.optional.avx1_0: 1', output[0]): + return True + + # FIXME: find some way of doing this on windows + return False + + def _check_mac_64b(self): + """Check to see if a mac is 64b""" + + cmd = "/usr/sbin/sysctl hw.optional.x86_64" + (retval,output, error_output) = util.run_command(cmd) + if retval == 0 and len(output)>0: + if re.match('hw.optional.x86_64: 1', ensure_string(output[0])): + return True + return False + + def _normalize_cpu_name(self, name): + """Internal function. Standardize various CPU identifiers""" + if name in ['ia32', 'i386', 'i686','x86']: + return 'ia32' + elif name in ['ia32e', 'x86_64', 'amd64', + 'x86-64', 'Intel64','intel64']: + return 'x86-64' + elif name == 'ia64': + return 'ipf' + elif name[0:5] == 'EM64T': + return 'x86-64' + elif name[0:7] == 'Intel64': + return 'x86-64' + elif name == 'intel64': + return 'x86-64' + elif name[0:5] == 'AMD64': + return 'x86-64' + elif name[0:3] == 'x86': + return 'ia32' + elif name in ['aarch64', 'arm64']: + return 'aarch64' + else: + die("Unknown cpu " + name) + + def _normalize_os_name(self,name): + """Internal function. Standardize various O/S identifiers""" + if name in ['android']: + return 'android' + elif name in ['lin', 'Linux']: + return 'lin' + elif name in ['mac', 'Darwin']: + return 'mac' + elif name in ['bsd', 'FreeBSD', 'NetBSD']: + return 'bsd' + elif name[0:6] == 'CYGWIN': + return 'win' + elif name in ['win', 'Windows_NT']: + return 'win' + else: + die("Unknown os " + name) + + def default_compiler(self): + """Default to ms on windows and gnu everywhere else. + @rtype: string + @returns: "ms" on windows, "clang" on mac, otherwise "gnu" + """ + if self.on_windows(): + return "ms" + if self.on_mac(): + return "clang" + return "gnu" + + def set_compiler_env(self, compiler_family=None): + """Initialize the build environment based on the compiler + environment variable setting. + + Adds in the "extra" flags from the environment. + + @type compiler_family: string + @param compiler_family: an override for the default + compiler family (gnu, ms, clang, icl, icc, iclang) + """ + + + # copy the command line version of the tool overrides to the + # real ones that we use. + + if self.env['cxx'] != '': + self.env['CXX'] = self.env['cxx'] + if self.env['cc'] != '': + self.env['CC'] = self.env['cc'] + if self.env['linker'] != '': + self.env['LINK'] = self.env['linker'] + if self.env['ar'] != '': + self.env['AR'] = self.env['ar'] + if self.env['as'] != '': + self.env['AS'] = self.env['as'] + + if compiler_family == None: + if 'compiler' in self.env: + self.env['compiler'] = self.env['compiler'].lower() + compiler_family = self.env['compiler'] + else: + die("Compiler family not specified in the environment or as an argument") + + if compiler_family == 'gnu': + build_env.set_env_gnu(self) + elif compiler_family == 'clang': + build_env.set_env_clang(self) + elif compiler_family == 'ms': + build_env.set_env_ms(self) + elif compiler_family == 'icc': + build_env.set_env_icc(self) + elif compiler_family == 'iclang': + build_env.set_env_iclang(self) + elif compiler_family == 'icl': + build_env.set_env_icl(self) + else: + die("Compiler family not recognized. Need gnu or ms") + + if self.env['use_yasm']: + if verbose(2): + msgb("USE YASM") + build_env.yasm_support(self) + + self.add_to_var('CXXFLAGS', self.env['extra_cxxflags']) + self.add_to_var('CCFLAGS', self.env['extra_ccflags'] ) + self.add_to_var('LINKFLAGS', self.env['extra_linkflags'] ) + self.add_to_var('LIBS', self.env['extra_libs'] ) + for d in self.env['extra_defines']: + self.add_define(d) + + def resuffix(self, fn, newext): + """Replace the suffix of single fn (or list of files) with + newext. newext should supply its own dot if you want one. + @type fn: string (or list of strings) + @param fn: a filename + @type newext: string + @param newext: a new extension starting with a '.' + @rtype: string + @return: fn with a new suffix specified by newext + """ + if isinstance(fn,list): + return [self.resuffix(x,newext) for x in fn] + else: + (root,ext) = os.path.splitext(fn) + return root + newext + + def osenv_add_to_front(self,evar,newstring,osenv=None): + """Add newstring to front of the environment variable osenv if given + if not given add to os.environ """ + environ = os.environ + if osenv: + environ = osenv + + if self.on_windows(): + sep = ';' + else: + sep = ':' + if evar in environ: + # The environment variable already exists + environ[evar]= newstring + sep + environ[evar] + else: + # Support creation of a new environment variable + environ[evar]= newstring + + def path_search(self,exe): + path = os.environ['PATH'] + if self.on_freebsd() or self.on_linux() or self.on_cygwin() or self.on_netbsd(): + sep = ':' + else: + sep = ';' + for p in path.split(sep): + t = util.prefix_files(p,exe) + if os.path.exists(t): + return t + return None + + + def make_obj(self,flist): + """Take file or list of files and return a file or list of + files with the OBJEXT extension from the environment. + @type flist: string or list of strings + @param flist: a filename (or list of filenames) + @rtype: string + @return: fn with a suffix specified %(OBJEXT)s + """ + return self.resuffix(flist,"%(OBJEXT)s") + + + def build_dir_join(self,files): + """Make the file (or list of files) with the build + directory name. + + @type files: string or list of strings + @param files: filename(s) + + @rtype: string or list of strings + @return: filenames prepended with the current build_dir + """ + + # FIXME: could do this lazily... and just prepend %(build_dir)s + try: + objdir = self.env['build_dir'] + except: + die("build_dir not defined in build_dir_join") + if objdir == '': + return files + return util.prefix_files(objdir, files) + + def src_dir_join(self,files): + """Prefix file (or list of files) with the src directory name. + @type files: string or list of strings + @param files: filename(s) + + @rtype: string or list of strings + @return: filenames prepended with the current src_dir + """ + # FIXME: could do this lazily... and just prepend %(src_dir)s + try: + srcdir = self.env['src_dir'] + except: + die("src_dir not defined in src_dir_join") + if srcdir == '': + return files + return util.prefix_files(srcdir, files) + + def add_define(self,newdef): + """Add a define or list defines to the CXXFLAGS and CCFLAGS + @type newdef: string or list of strings + @param newdef: string to add to the CXXFLAGS and CCFLAGS + environment variables. + """ + self.add_cc_define(newdef) + self.add_cxx_define(newdef) + self.add_as_define(newdef) + + def _collect_defines(self, dlist): + for d in dlist: + if d not in self.env['DEFINES']: + self.env['DEFINES'][d]=True + + def add_as_define(self,newdef): + """Add a define or list defines to the ASFLAGS + @type newdef: string or list of strings + @param newdef: string to add to the ASFLAGS + environment variable. + """ + if isinstance(newdef,list): + deflist = newdef + else: + deflist = [ newdef ] + self._collect_defines(deflist) + for d in deflist: + self.add_to_var('ASFLAGS', "%(ASDOPT)s" + d ) + + def add_cc_define(self,newdef): + """Add a define or list defines to the CCFLAGS + @type newdef: string or list of strings + @param newdef: string to add to the CCFLAGS + environment variable. + """ + if isinstance(newdef,list): + deflist = newdef + else: + deflist = [ newdef ] + self._collect_defines(deflist) + + for d in deflist: + self.add_to_var('CCFLAGS', "%(DOPT)s" + d ) + + def add_cxx_define(self,newdef): + """Add a define or list defines to the CXXFLAGS + @type newdef: string or list of strings + @param newdef: string to add to the CXXFLAGS + environment variable. + """ + if isinstance(newdef,list): + deflist = newdef + else: + deflist = [ newdef ] + self._collect_defines(deflist) + for d in deflist: + self.add_to_var('CXXFLAGS', "%(DOPT)s" + d ) + + + def add_include_dir(self,include_dir): + """Add a directory or list of directories to the CPPPATH. Just + a short cut for adding things to the list of files in the + env['CPPPATH'] + @type include_dir: string or list of strings + @param include_dir: string to add to the CPPPATH environment variable + """ + if isinstance(include_dir,list): + lst = include_dir + else: + lst = [ include_dir ] + for d in lst: + p = util.posix_slashes(d) + if p not in self.env['CPPPATH']: + self.env['CPPPATH'].append(p) + + def add_system_include_dir(self,sys_include_dir): + """Add a directory or list of directories to the SYSTEMINCLUDE. Just + a short cut for adding things to the list of files in the + env['SYSTEMINCLUDE'] + @type sys_include_dir: string or list of strings + @param sys_include_dir: string to add to the SYSTEMINCLUDE environment variable + """ + if isinstance(sys_include_dir,list): + lst = sys_include_dir + else: + lst = [ sys_include_dir ] + for d in lst: + p = util.posix_slashes(d) + if p not in self.env['SYSTEMINCLUDE']: + self.env['SYSTEMINCLUDE'].append(p) + + def add_link_dir(self,link_dir): + """Add a directory or list of directories to the LINKPATH. These + get included in the LINKFLAGS + + @type link_dir: string or list of strings + @param link_dir: string to add to the LINKPATH variable + """ + if isinstance(link_dir,list): + for d in link_dir: + self.env['LINKPATH'].append(util.posix_slashes(d)) + else: + self.env['LINKPATH'].append(util.posix_slashes(link_dir)) + + + def remove_from_var(self, var, value): + """Remove a substring (or list entry) from env[var]. Opposite + of add_to_var(). + + @type var: string + @param var: name of a dictionary key + @type value: string + @param value: the value to remove + """ + if var in self.env: + if isinstance(self.env[var], list): + try: + self.env[var].remove(value) + except: + pass + else: + self.env[var] = re.sub(value,'',self.env[var]) + + + def add_to_var(self, var, value): + """Add or append value to the environment variable var. If the + variable is not in the environment, then it is added as + is. Otherwise if the variable is in the environment and is a + list then value is appended. Otherwise, the value is appended + as a string with a leading space. This will *NOT* do variable + substitution when adding to a variable. + + @type var: string + @param var: name of a dictionary key + @type value: string + @param value: the value to add or append + + """ + if var not in self.env: + self.env[var] = value + elif isinstance(self.env[var],list): + if isinstance(value, list): + self.env[var].extend(value) + else: + self.env[var].append(value) + else: + self.env[var] += ' ' + value # This would do variable expansion when calling __getitem__ + + # These strings should be % env expanded. + + # COUT should be "-o " on linux. Note the trailing space + # COPT should be "-c" on linux + # OBJNAME and SRCNAME should be fully qualified suffix-wise + # OBJNAMES is used for the link and lib statements + # EXENAME is used for link statements + # LIBNAME is used for lib statements + # SOLIBNAME is used for shared objects "soname" embedded names + # LIBOUT, LINKOUT should be set appropriately. Trailing spaces needed on linux + # DLLOPT is needed for dynamic libraries + + # Example: + # a = '%(lang)s has %(c)03d quote types.' % dict(lang='Python', c=2) + + def _add_c_compile(self): + s = "%(CC)s %(CPPINCLUDES)s %(SYSINCLUDES)s %(CCFLAGS)s %(COPT)s %(COUT)s%(OBJNAME)s %(SRCNAME)s" + return s + + def _add_assemble(self): + s = "%(AS)s %(CPPINCLUDES)s %(SYSINCLUDES)s %(ASFLAGS)s %(ASMOUT)s%(OBJNAME)s %(SRCNAME)s" + return s + + def _add_cxx_compile(self): + s = "%(CXX)s %(CPPINCLUDES)s %(SYSINCLUDES)s %(CXXFLAGS)s %(COPT)s %(COUT)s%(OBJNAME)s %(SRCNAME)s" + return s + + def _add_link(self): + s = "%(LINK)s %(LINKFLAGS)s %(LINKOUT)s%(EXENAME)s %(OBJNAMES)s %(LIBS)s" + return s + + def _add_static_lib(self): + s = [ _remove_libname, + "%(AR)s %(ARFLAGS)s %(LIBOUT)s%(LIBNAME)s %(OBJNAMES)s" ] + return s + + def _add_dynamic_lib(self): + s = "%(LINK)s %(LINKFLAGS)s %(DLLOPT)s %(LIBOUT)s%(LIBNAME)s %(OBJNAMES)s %(LIBS)s" + return s + + def _add_cxx_shared_lib(self): + s = "%(CXX)s %(LINKFLAGS)s %(DLLOPT)s %(COUT)s%(LIBNAME)s %(OBJNAMES)s %(LIBS)s" + return s + + def _add_res_file_cmd(self): + s = "%(RC)s %(RCFLAGS)s /fo%(RESNAME)s %(RCNAME)s" + return s + + def _add_default_builders(self): + """Private. Part of initialization for the environment. Sets + the default builders""" + + # Instead use default function if these are not set. + self.env['ASSEMBLE_BUILDER'] = None + self.env['CXX_COMPILE_BUILDER'] = None + self.env['CC_COMPILE_BUILDER'] = None + self.env['LINK_BUILDER'] = None + self.env['STATIC_LIBRARY_BUILDER'] = None + self.env['DYNAMIC_LIBRARY_BUILDER'] = None + self.env['RES_FILE_BUILDER'] = None + + def _add_default_builder_templates(self): + """Private. Part of initialization for the environment. Sets + the default templates used by the default builders""" + self.env['CC_COMPILE_COMMAND'] = self._add_c_compile() + self.env['CXX_COMPILE_COMMAND'] = self._add_cxx_compile() + self.env['ASSEMBLE_COMMAND'] = self._add_assemble() + self.env['LINK_COMMAND'] = self._add_link() + self.env['STATIC_LIB_COMMAND'] = self._add_static_lib() + self.env['DYNAMIC_LIB_COMMAND'] = self._add_dynamic_lib() + self.env['CXX_SHARED_LIB_COMMAND'] = self._add_cxx_shared_lib() + self.env['RES_FILE_COMMAND'] = self._add_res_file_cmd() + + def _add_compilation_support(self): + """Private. Part of initialization for the environment. Sets + the default builders and templates.""" + self._add_default_builders() + self._add_default_builder_templates() + + def escape_string(self,s): + return util.escape_string(s) + + def _escape_list_of_strings(self,sl): + n = [] + for s in sl: + n.append(self.escape_string(s)) + return n + + def _make_cpp_include(self): + s = [] + + iopt = self.env['IOPT'] + + for p in self.env['CPPPATH']: + s.extend([iopt, self.escape_string(p), ' ']) + return ''.join(s) + + def _make_system_include(self): + s = [] + iopt = self.env['ISYSOPT'] + for p in self.env['SYSTEMINCLUDE']: + s.extend([iopt, self.escape_string(p), ' ']) + return ''.join(s) + + def _make_link_dirs(self): + s = [] + lopt = self.env['LOPT'] + for p in self.env['LINKPATH']: + s.extend([lopt, self.escape_string(p), ' ']) + return ''.join(s) + + def _make_cpp_flags(self): + self.env['CPPINCLUDES'] = self._make_cpp_include() + def _make_sys_include_flags(self): + self.env['SYSINCLUDES'] = self._make_system_include() + def _make_link_flags(self): + self.env['LINKDIRS'] = self._make_link_dirs() + + def make_derived_flags(self): + """Put together any derived flags. This is required to be + called by builder functions before they do their expansion. + """ + + self._make_cpp_flags() + self._make_sys_include_flags() + self._make_link_flags() + + + + def assemble(self, source, obj=None): + """Indirection function. Reads builder function from the + environment variable ASSEMBLER_BUILDER. Assemble a source file + to the obj file. If no obj file name is given one will be + created in the build directory. + @type source: string + @param source: filename to assemble + + @type obj: string + @param obj: output filename. + + @rtype: L{plan_t} + @return: an input for the DAG + """ + # FIXME abspath breaks windows compilation under cygwin python + new_source = os.path.abspath(source) + + f= self.env['ASSEMBLE_BUILDER'] + if f: + return f(new_source,obj) + return self._assemble_default(new_source,obj) + + def cxx_compile(self, source, obj=None): + """Indirection function. Reads builder function from the + environment variable CXX_COMPILE_BUILDER. C++-compile a source + file to a file called obj. If no obj file name is given one + will be created in the build directory. + @type source: string + @param source: filename to compile + + @type obj: string + @param obj: output filename. + + @rtype: L{plan_t} + @return: an input for the DAG + """ + # FIXME abspath breaks windows compilation under cygwin python + new_source = os.path.abspath(source) + + f = self.env['CXX_COMPILE_BUILDER'] + if f: + return f(new_source,obj) + return self._cxx_compile_default(new_source,obj) + + def cc_compile(self, source, obj=None): + """Indirection function. Reads builder function from the + environment variable CC_COMPILE_BUILDER. C-compile a source + file to a file named obj. If no obj file name is given one + will be created in the build directory. + @type source: string + @param source: filename to compile + + @type obj: string + @param obj: output filename. + + @rtype: L{plan_t} + @return: an input for the DAG + """ + + # FIXME abspath breaks windows compilation under cygwin python + new_source = os.path.abspath(source) + + f = self.env['CC_COMPILE_BUILDER'] + if f: + return f(new_source,obj) + return self._cc_compile_default(new_source,obj) + + def link(self, objs, exename, relocate=False): + """Indirection function. Reads builder function from the + environment variable LINK_BUILDER. Link an executable from + objs. If relocate is True, then prefix exename with the build + directory name. + @type objs: list of strings + @param objs: filenames to link + + @type exename: string + @param exename: output filename. + + @type relocate: bool + @param relocate: If true, relocate the exename to the build directory. + + @rtype: L{plan_t} + @return: an input for the DAG + + """ + f = self.env['LINK_BUILDER'] + if f: + return f(objs,exename, relocate) + return self._link_default(objs,exename,relocate) + + def static_lib(self, objs, libname, relocate=False): + """Indirection function. Reads builder function from the + environment variable STATIC_LIBRARY_BUILDER. Make a static + library libname from objs. If relocate is True, then prefix + libname with the build directory name + + @type objs: list of strings + @param objs: filenames to link + + @type libname: string + @param libname: output filename. + + @type relocate: bool + @param relocate: If true, relocate the library to the build directory. + + @rtype: L{plan_t} + @return: an input for the DAG + + + """ + f = self.env['STATIC_LIBRARY_BUILDER'] + if f: + return f(objs,libname, relocate) + return self._static_lib_default(objs,libname,relocate) + + def compile_and_static_lib(self, dag, sources, libname): + """Build all the sources by adding them to the dag. Use the + suffixes to figure out how to handle the files. The dag can be + passed to a work queue. See the build function. """ + + # Compile + objs = self.compile(dag, sources) + + # Link the lib + dag.add(self, self.static_lib(objs, libname, relocate=True)) + + def dynamic_lib_name(self, base): + return self.shared_lib_name(base) + + def shared_lib_name(self, base): + if self.on_windows(): + s = '{}%(DLLEXT)s'.format(base) + else: + s = 'lib{}%(DLLEXT)s'.format(base) + return s + def static_lib_name(self, base): + if self.on_windows(): + s = '{}%(LIBEXT)s'.format(base) + else: + s = 'lib{}%(LIBEXT)s'.format(base) + return s + + def dynamic_lib(self, objs, libname, relocate=False): + """Indirection function. Reads builder function from the + environment variable DYNAMIC_LIBRARY_BUILDER. Make a dynamic + library libname from objs. If relocate is True, then prefix + libname with the build directory name + + @type objs: list of strings + @param objs: filenames to link + + @type libname: string + @param libname: output filename. + + @type relocate: bool + @param relocate: If true, relocate the library to the build directory. + + @rtype: L{plan_t} + @return: an input for the DAG + + """ + f = self.env['DYNAMIC_LIBRARY_BUILDER'] + if f: + return f(objs,libname, relocate) + return self._dynamic_lib_default(objs,libname,relocate) + + + def rc_file(self, rc_file, res_file=None): + """Indirection function. For making RES files + from RC files on windows. + + @type rc_file: string + @param rc_file: filename for RC file + + @type res_file: string + @param res_file: filename for RES file + + """ + f = self.env['RES_FILE_BUILDER'] + if f: + return f(rc_file, res_file) + return self._res_file_builder_default(rc_file, res_file) + + def _escape_dict(self, d): + file_name_keys = ['SRCNAME','OBJNAME', 'LIBNAME', + 'SOLIBNAME', 'EXENAME', + 'RCNAME', 'RESNAME' ] + for k in file_name_keys: + if k in d: + d[k] = self.escape_string(d[k]) + + def _assemble_default(self, source, obj=None): + """Assemble a source file to the obj file. If no obj file name + is given one will be created in the build directory.""" + cmd = self.env['ASSEMBLE_COMMAND'] + d = copy.copy(self) + self.make_derived_flags() + d['SRCNAME'] = source + if obj == None: + (filepath,fullfilename) = os.path.split(source) + (filename,ext) = os.path.splitext(fullfilename) + obj = filename + self.env['OBJEXT'] + obj = self.build_dir_join(obj) + d['OBJNAME'] = obj + self._escape_dict(d) + s = self.expand_string(cmd, d) + return plan.plan_t(command=s, output=obj, input=source) + + def _make_pdb_file(self,obj): + """If obj obj file ends in '.obj$' or '%(OBJEXT)s' replace it + so it looks like: '%(PDBEXT)s'""" + + if env_t.obj_pattern.search(obj): + pdbfile = env_t.obj_pattern.sub('%(PDBEXT)s',obj) + elif env_t.objext_pattern.search(obj): + pdbfile = env_t.objext_pattern.sub('%(PDBEXT)s',obj) + else: + die("Could not make PDB file from OBJ file: %s" % obj) + return pdbfile + + def _cxx_compile_default(self, source, obj=None): + """C++-compile a source file to a file called obj. If no obj file + name is given one will be created in the build directory.""" + cmd = self.env['CXX_COMPILE_COMMAND'] + d = copy.copy(self) + self.make_derived_flags() + d['SRCNAME'] = source + if obj == None: + (filepath,fullfilename) = os.path.split(source) + (filename,ext) = os.path.splitext(fullfilename) + obj = filename + self.env['OBJEXT'] + obj = self.build_dir_join(obj) + if d['separate_pdb_files'] and d['compiler'] == 'ms' and d['debug'] == 1: + pdbfile = self._make_pdb_file(obj) + d['CXXFLAGS'] += ' /Fd%s ' % pdbfile + + d['OBJNAME'] = obj + self._escape_dict(d) + s = self.expand_string(cmd, d) + return plan.plan_t(command=s, output=obj, input=source) + + + def _cc_compile_default(self, source, obj=None): + """C-compile a source file to a file named obj. If no obj file + name is given one will be created in the build directory.""" + + cmd = self.env['CC_COMPILE_COMMAND'] + d = copy.copy(self) + self.make_derived_flags() + d['SRCNAME'] = source + if obj == None: + (filepath,fullfilename) = os.path.split(source) + (filename,ext) = os.path.splitext(fullfilename) + obj = filename + self.env['OBJEXT'] + obj = self.build_dir_join(obj) + if d['separate_pdb_files'] and d['compiler'] == 'ms' and d['debug'] == 1: + pdbfile = self._make_pdb_file(obj) + d['CCFLAGS'] += ' /Fd%s ' % pdbfile + + d['OBJNAME'] = obj + self._escape_dict(d) + s = self.expand_string(cmd, d) + return plan.plan_t(command=s, output=obj, input=source) + + def _find_libs(self): + libs = [] + for lib in self.expand_string('%(LIBS)s').split(): + if lib: + # ignore libraries that start with "-" as in -lc -lm. I + # would not know what suffix to put on them anyway + # (LIBEXT,DLLEXT) without trying them all. + if lib[0]=='-': + continue + if os.path.exists(lib): + #msgb("ADDING DEPENDENCE ON LIBRARY", lib) + libs.append(lib) + else: + for dir in self.env['LINKPATH']: + t = util.join(dir,lib) + if os.path.exists(t): + #msgb("ADDING DERIVED DEPENDENCE ON LIBRARY", t) + libs.append(t) + return libs + + + def _link_default(self, objs, exename, relocate=False): + """Link an executable from objs. If relocate is True, + then prefix exename with the build directory name.""" + cmd = self.env['LINK_COMMAND'] + d = copy.copy(self) + self.make_derived_flags() + if relocate: + exename = self.build_dir_join(exename) + d['EXENAME'] = exename + + if not isinstance(objs, list): + objs = [ objs ] + objs = self._escape_list_of_strings(objs) + obj = " ".join(objs) + d['OBJNAMES'] = obj + self._escape_dict(d) + s = self.expand_string(cmd, d) + return plan.plan_t(command=s, output=exename, input=objs + self._find_libs()) + + + def _static_lib_default(self, objs, libname, relocate=False): + """Make a static library libname from objs. If relocate is True, + then prefix libname with the build directory name""" + d = copy.copy(self) + self.make_derived_flags() + if relocate: + libname = self.build_dir_join(libname) + d['LIBNAME'] = libname + if not isinstance(objs,list): + objs = [ objs ] + objs = self._escape_list_of_strings(objs) + obj = " ".join(objs) + + d['OBJNAMES'] = obj + self._escape_dict(d) + n = [] + scmd = self.env['STATIC_LIB_COMMAND'] + if not isinstance(scmd,list): + scmd = [ scmd ] + for cmd in scmd: + if util.is_stringish(cmd): + n.append(self.expand_string(cmd, d)) + else: + n.append(cmd) + # we pass args to the python scripts... Must expand now or + # else suffer concurrency bugs at build time. + args = [ self.expand_string('%(LIBNAME)s') ] + return plan.plan_t(command=n, output=libname, + args=args, + input=objs, env=self) + + + def _dynamic_lib_default(self, objs, libname, relocate=False): + """Make a dynamic library libname from objs. If relocate is True, + then prefix libname with the build directory name""" + if self.env['compiler'] in [ 'gnu','icc','clang','iclang']: + cmd = self.env['CXX_SHARED_LIB_COMMAND'] + else: + cmd = self.env['DYNAMIC_LIB_COMMAND'] + d = copy.copy(self) + self.make_derived_flags() + if relocate: + libname = self.build_dir_join(libname) + d['LIBNAME'] = libname + d['SOLIBNAME'] = os.path.basename(libname) + if not isinstance(objs,list): + objs = [ objs ] + objs = self._escape_list_of_strings(objs) + obj = " ".join(objs) + d['OBJNAMES'] = obj + self._escape_dict(d) + s = self.expand_string(cmd, d) + return plan.plan_t(command=s, output=libname, + input=objs + self._find_libs()) + + + + def _res_file_builder_default(self, rc_file,res_file=None): + """Make a res file from an rc file. Windows only.""" + cmd = self.env['RES_FILE_COMMAND'] + d = copy.copy(self) + if not res_file: + res_file = self.build_dir_join(self.resuffix(rc_file,'%(RESEXT)s')) + d['RESNAME'] = res_file + d['RCNAME'] = rc_file + self._escape_dict(d) + s = self.expand_string(cmd, d) + return plan.plan_t(command=s, + output=res_file, + input=rc_file) + + def compile(self, dag, sources): + """Build all the sources by adding them to the dag. Use the + suffixes to figure out how to handle the files. The dag can be + passed to a work queue. See the build function. """ + + objs = [] + for s in sources: + b = os.path.basename(s) # filename component of path/filename + (base,ext) = os.path.splitext(b) + if ext in ['.rc' ]: + obj = self.build_dir_join(self.resuffix(b,'%(RESEXT)s')) + else: + obj = self.build_dir_join(self.make_obj(b)) + + if ext in ['.asm', '.s' ]: + c = self.assemble( s, obj ) + elif ext in ['.c']: + c = self.cc_compile( s, obj ) + elif ext in ['.cpp', '.C' ]: + c = self.cxx_compile( s, obj ) + elif ext in ['.rc' ]: + c = self.rc_file( s, obj ) # obj is a res file in this case + else: + die("Unsupported file type %s" % (s)) + cmd = dag.add(self,c) + objs.append(self.expand_string(obj)) + return objs + + + def compile_and_link(self, dag, sources, exe, shared_object=False, libs=[]): + """Build all the sources by adding them to the dag. Use the + suffixes to figure out how to handle the files. The dag can be + passed to a work queue. See the build function. """ + + objs = self.compile(dag, sources) + + if shared_object: + cmd2 = dag.add(self, + self.dynamic_lib(objs + libs, exe, relocate=True)) + else: + cmd2 = dag.add(self, + self.link(objs + libs , exe,relocate=True)) + return cmd2 + + + def build(self, work_queue, dag, phase='BUILD',terminate_on_errors=False): + """Build everything in the work queue""" + okay = work_queue.build(dag=dag, die_on_errors=False) + if not okay: + if terminate_on_errors: + die("[%s] failed." % phase) + else: + msgb(phase,"failed.") + return False + msgb(phase, "succeeded") + return True diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/header_tag.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/header_tag.py new file mode 100644 index 0000000..727e7ef --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/header_tag.py @@ -0,0 +1,173 @@ +#!/usr/bin/env python +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +from __future__ import print_function +import sys +import os +import re +from stat import * + + +def _get_mode(fn): + "get the mode of the file named fn, suitable for os.chmod() or open() calls" + mode = os.stat(fn)[ST_MODE] + cmode = S_IMODE(mode) + return cmode + +def _replace_original_with_new_file(file,newfile): + "Replace file with newfile" + # os.system(" mv -f %s %s" % ( newfile, file)) + os.unlink(file) + os.rename(newfile,file) + +def _remove_existing_header(contents,prefix="#"): + "remove existing legal header, if any" + retval = [] + skipping = False + start_pattern = re.compile(r"^(/[*]BEGIN_LEGAL)|(" + prefix + "BEGIN_LEGAL)") + stop_pattern = re.compile(r"^[ ]*(END_LEGAL[ ]?[*]/)|(" + prefix + "[ ]*END_LEGAL)") + for line in contents: + if start_pattern.match(line): + skipping = True + if skipping == False: + retval.append(line) + if stop_pattern.match(line): + skipping = False + return retval + +def _prepend_script_comment(header,prefix="#"): + "Apply script comment marker to each line" + retval = [] + for line in header: + retval.append( prefix + line ) + return retval + +def apply_header_to_source_file(header, file): + "apply header to file using C++ comment style" + f = open(file,"r") + mode = _get_mode(file) + contents = f.readlines() + f.close() + trimmed_contents = _remove_existing_header(contents) + newfile = file + ".new" + o = open(newfile,"w") + o.write("/*BEGIN_LEGAL \n") + o.writelines(header) + o.write("END_LEGAL */\n") + o.writelines(trimmed_contents) + o.close() + os.chmod(newfile,mode) + _replace_original_with_new_file(file,newfile) + +# FIXME: this will flag files that have multiline C-style comments +# with -*- in them even though the splitter will not look for the +# comment properly + +def _shell_script(lines): + """return true if the lines are the start of shell script or + something that needs a mode comment at the top""" + + first = "" + second = "" + if len(lines) > 0: + first = lines[0]; + if len(lines) > 1: + second = lines[1]; + + if re.match("#!",first): + return True + if re.search("-\*-",first) or re.search("-\*-",second): + return True + return False + +def _split_script(lines): + "Return a tuple of (header, body) for shell scripts, based on an input line list" + header = [] + body = [] + + f = lines.pop(0) + while re.match("#",f) or re.search("-\*-",f): + header.append(f) + f = lines.pop(0) + + # tack on the first non matching line from the above loop + body.append(f); + body.extend(lines); + return (header,body) + +def _write_script_header(o,lines,prefix="#"): + "Write the file header for a script" + o.write(prefix+"BEGIN_LEGAL\n") + o.writelines(lines) + o.write(prefix+"END_LEGAL\n") + +def apply_header_to_data_file(header, file, prefix="#"): + "apply header to file using script comment style" + f = open(file,"r") + mode = _get_mode(file) + contents = f.readlines() + f.close() + trimmed_contents = _remove_existing_header(contents, prefix) + newfile = file + ".new" + o = open(newfile,"w") + augmented_header = _prepend_script_comment(header,prefix) + if _shell_script(trimmed_contents): + (script_header, script_body) = _split_script(trimmed_contents) + o.writelines(script_header) + _write_script_header(o, augmented_header, prefix) + o.writelines(script_body) + else: + _write_script_header(o,augmented_header,prefix) + o.writelines(trimmed_contents) + o.close() + os.chmod(newfile,mode) + _replace_original_with_new_file(file,newfile) + +#################################################################### +### MAIN +#################################################################### +if __name__ == '__main__': + if len(sys.argv) < 4: + print ("Usage " + sys.argv[0] + " [-s|-t] legal-header file-name [file-name...]\n") + sys.exit(1) + + type = sys.argv[1] + header_file = sys.argv[2] + if not os.path.exists(header_file): + print ("Could not find header file: [%s]\n" % (header_file)) + sys.exit(1) + + files_to_tag = sys.argv[3:] + f = open(header_file,"r") + header = f.readlines() + f.close() + + sources = files_to_tag + + if type == "-s": + for file in sources: + if re.search(".svn",file) == None and re.search(".new$",file) == None: + apply_header_to_source_file(header, file.strip()) + elif type == "-t": + for file in sources: + if re.search(".svn",file) == None and re.search(".new$",file) == None: + apply_header_to_data_file(header, file.strip()) + else: + print ("2nd argument must be -s or -t\n") + sys.exit(1) diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/msvs.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/msvs.py new file mode 100644 index 0000000..5e72a66 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/msvs.py @@ -0,0 +1,1460 @@ +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +# TESTING MATRIX +# ('e' is for express) +# +# 32 32/64 64 +# 6 ok ? N/A +# 7 ok ok N/A +# 8 ? ok ok +# 8e ? ? ? +# 9 ? ok ok +# 9e ok ? ? +# 10 ? ? ? +# + +"""Environment setup for Microsoft Visual Studio. Set INCLUDE, +LIBPATH, LIB, PATH, VCINSTALLDIR, VS80COMNTOOLS, VSINSTALLDIR, etc. +""" +from __future__ import print_function +import os +import sys +import platform +from .base import * +from .util import * +from .env import * +from .osenv import * + +######################################################################## +def add_env(v,s): + """Add v=v;old_vs to the shell environment. Inserts at front""" + if 0: + if os.path.exists(s): + tag = u"GOOD" + else: + tag = u"BAD" + uprint(u"{} {}".format(tag,s)) + v.insert(0,s) +######################################################################## + +def _find_dir_list(lst): + for dir in lst: + if os.path.exists(dir): + return dir + return None + + +def _set_msvs_dev6(env, x64_host, x64_target): # VC 98 + vc_prefixes = [ "C:/VC98", + "C:/Program Files (x86)/Microsoft Visual Studio", + "C:/Program Files/Microsoft Visual Studio" ] + + msdev_prefixes = [ + "C:/Program Files/Microsoft Visual Studio/Common" ] + vc_prefix = _find_dir_list(vc_prefixes) + msdev_prefix = _find_dir_list(msdev_prefixes) + if not vc_prefix: + die("Could not find VC98") + if not msdev_prefix: + die("Could not find VC98 MSDEV") + + i = [] + add_env(i, vc_prefix + "/VC98/ATL/INCLUDE") + add_env(i, vc_prefix + "/VC98/INCLUDE") + add_env(i, vc_prefix + "/VC98/MFC/INCUDE") + set_env_list("INCLUDE",i) + + lib = [] + add_env(lib, vc_prefix + "/VC98/LIB") + add_env(lib, vc_prefix + "/VC98/MFC/LIB") + set_env_list("LIB",lib) + + path=[] + add_env(path, msdev_prefix + "/msdev98/Bin") + add_env(path, vc_prefix + "/VC98/Bin") + add_env(path, msdev_prefix + "/TOOLS/WINNT") + add_env(path, msdev_prefix + "/TOOLS") + add_to_front_list('PATH', path) + + set_env("MSDevDir", msdev_prefix + "/msdev98") + set_env("MSVCDir", vc_prefix + "/VC98") + + return vc_prefix + "/VC98" + +def _set_msvs_dev7(env, x64_host, x64_target): # .NET 2003 + + prefixes = [ "c:/Program Files/Microsoft Visual Studio .NET 2003", + "c:/Program Files (x86)/Microsoft Visual Studio .NET 2003"] + prefix = _find_dir_list(prefixes) + if not prefix: + die("Could not find MSVS7 .NET 2003") + + inc = [] + add_env(inc, prefix + '/VC7/ATLMFC/INCLUDE') + add_env(inc, prefix + '/VC7/include') + add_env(inc, prefix + '/VC7/PlatformSDK/include/prerelease') + add_env(inc, prefix + '/VC7/PlatformSDK/include') + add_env(inc, prefix + '/SDK/v1.1/include') + add_env(inc, prefix + '/SDK/v1.1/include/') + set_env_list("INCLUDE",inc) + + lib = [] + add_env(lib, prefix + '/VC7/ATLMFC/LIB') + add_env(lib, prefix + '/VC7/LIB') + add_env(lib, prefix + '/VC7/PlatformSDK/lib/prerelease') + add_env(lib, prefix + '/VC7/PlatformSDK/lib') + add_env(lib, prefix + '/SDK/v1.1/lib') + add_env(lib, prefix + '/SDK/v1.1/Lib/') + set_env_list("LIB",lib) + + path = [] + add_env(path, prefix + "/Common7/IDE") + add_env(path, prefix + "/VC7/bin") + add_env(path, prefix + "/Common7/Tools") + add_env(path, prefix + "/Common7/Tools/bin/prerelease") + add_env(path, prefix + "/Common7/Tools/bin") + add_env(path, prefix + "/SDK/v1.1/bin") + add_to_front_list('PATH', path) + + set_env("VCINSTALLDIR", prefix) + set_env("VC71COMNTOOLS", prefix + "/Common7/Tools/") + set_env("VSINSTALLDIR", prefix + '/Common7/IDE') + set_env("MSVCDir", prefix + '/VC7') + set_env("FrameworkVersion","v1.1.4322") + set_env("FrameworkSDKDir", prefix + "/SDK/v1.1") + set_env("FrameworkDir", "C:/WINDOWS/Microsoft.NET/Framework") + # DevEnvDir has a trailing slash + set_env("DevEnvDir", prefix + "/Common7/IDE/") + + return prefix + "/VC7" +def _set_msvs_dev8(env, x64_host, x64_target, regv=None): # VS 2005 + if regv: + prefix = regv + else: + prefixes = ["c:/Program Files (x86)/Microsoft Visual Studio 8", + "c:/Program Files/Microsoft Visual Studio 8"] + prefix = _find_dir_list(prefixes) + if not os.path.exists(prefix): + die("Could not find MSVC8 (2005)") + + set_env('VCINSTALLDIR', prefix + '/VC') + set_env('VS80COMNTOOLS', prefix + "/Common7/Tools") + set_env('VSINSTALLDIR', prefix) + + i =[] + add_env(i, prefix + "/VC/ATLMFC/INCLUDE") + add_env(i, prefix + "/VC/INCLUDE") + add_env(i, prefix + "/VC/PlatformSDK/include") + add_env(i, prefix + "/SDK/v2.0/include") + set_env_list('INCLUDE', i) + + set_env('FrameworkDir','C:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkVersion', 'v2.0.50727') + set_env('FrameworkSDKDir', prefix +'/SDK/v2.0') + + # DevEnvDir has a trailing slash + set_env("DevEnvDir", prefix +'/Common7/IDE/') + + lp = [] + path=[] + lib=[] + if x64_host and x64_target: + add_env(lp, prefix + '/VC/ATLMFC/LIB/amd64') + + add_env(lib, prefix + "/VC/ATLMFC/LIB/amd64") + add_env(lib, prefix + "/VC/LIB/amd64") + add_env(lib, prefix + "/VC/PlatformSDK/lib/amd64") + add_env(lib, prefix + "/SDK/v2.0/LIBAMD64") + + add_env(path, prefix + "/VC/bin/amd64") + add_env(path, prefix + "/VC/PlatformSDK/bin/win64/amd64") + add_env(path, prefix + "/VC/PlatformSDK/bin") + add_env(path, prefix + "/VC/VCPackages") + add_env(path, prefix + "/Common7/IDE") + add_env(path, prefix + "/Common7/Tools") + add_env(path, prefix + "/Common7/Tools/bin") + add_env(path, prefix + "/SDK/v2.0/bin") + add_env(path, prefix + "C:/WINDOWS/Microsoft.NET/Framework64/v2.0.50727") + + elif not x64_target: + + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix + '/Common7/Tools') + add_env(path, prefix + '/Common7/Tools/bin') + add_env(path, prefix + '/VC/PlatformSDK/bin') + add_env(path, prefix + '/SDK/v2.0/bin') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v2.0.50727') + + add_env(lib, prefix + '/VC/ATLMFC/LIB') + add_env(lib, prefix + '/VC/LIB') + add_env(lib, prefix + '/VC/PlatformSDK/lib') + add_env(lib, prefix + '/SDK/v2.0/lib') + + add_env(lp, prefix + '/VC/ATLMFC/LIB') + add_env(lp, 'C:/WINDOWS/Microsoft.NET/Framework/v2.0.50727') + + add_to_front_list('PATH', path) + set_env_list('LIB',lib) + set_env_list('LIBPATH', lp) + + return prefix + "/VC" + +def _set_msvs_dev9(env, x64_host, x64_target, regv=None): # VS 2008 + if regv: + prefix = regv + else: + prefixes = ['C:/Program Files (x86)/Microsoft Visual Studio 9.0', + 'C:/Program Files/Microsoft Visual Studio 9.0'] + prefix = _find_dir_list(prefixes) + + set_env('VSINSTALLDIR', prefix) + set_env('VS90COMNTOOLS', prefix + '/Common7/Tools') + set_env('VCINSTALLDIR', prefix +'/VC') + set_env('FrameworkDir', 'C:/WINDOWS/Microsoft.NET/Framework') + set_env('Framework35Version','v3.5') + set_env('FrameworkVersion','v2.0.50727') + set_env('FrameworkSDKDir', prefix +'/SDK/v3.5') + set_env('WindowsSdkDir','C:/Program Files/Microsoft SDKs/Windows/v6.0A') + + # DevEnvDir has a trailing slash + set_env('DevEnvDir', prefix + '/Common7/IDE/') + inc = [] + add_env(inc, prefix + 'VC/ATLMFC/INCLUDE') + add_env(inc, prefix + '/VC/INCLUDE') + add_env(inc, 'C:/Program Files/Microsoft SDKs/Windows/v6.0A/include') + set_env_list('INCLUDE',inc) + + path = [] + lib = [] + libpath = [] + + if x64_target: # FIXME! 64b!!!! + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix + '/Common7/Tools') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, 'C:/Program Files/Microsoft SDKs/Windows/v6.0A/bin') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v3.5') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v2.0.50727') + + add_env(lib, prefix +'/VC/ATLMFC/LIB/amdt64') + add_env(lib, prefix +'/VC/LIB/amd64') + add_env(lib, 'C:/Program Files/Microsoft SDKs/Windows/v6.0A/lib/x64') + + add_env(libpath, 'C:/WINDOWS/Microsoft.NET/Framework64/v2.0.50727') + add_env(libpath, 'C:/WINDOWS/Microsoft.NET/Framework64/v3.5') + add_env(libpath, 'C:/WINDOWS/Microsoft.NET/Framework64/v2.0.50727') + add_env(libpath, 'C:/WINDOWS/Microsoft.NET/Framework64/v2.0.50727') + add_env(libpath, prefix + '/VC/ATLMFC/LIB/amd64') + add_env(libpath, prefix + '/VC/LIB/amd64') + else: + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix + '/Common7/Tools') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, 'C:/Program Files/Microsoft SDKs/Windows/v6.0A/bin') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v3.5') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v2.0.50727') + + add_env(lib, prefix +'/VC/LIB') + add_env(lib, prefix +'/VC/ATLMFC/LIB') + add_env(lib, 'C:/Program Files/Microsoft SDKs/Windows/v6.0A/lib') + + add_env(libpath, 'C:/WINDOWS/Microsoft.NET/Framework/v3.5') + add_env(libpath, 'C:/WINDOWS/Microsoft.NET/Framework/v2.0.50727') + add_env(libpath, prefix + '/VC/ATLMFC/LIB') + add_env(libpath, prefix + '/VC/LIB') + + set_env_list('LIBPATH',libpath) + set_env_list('LIB',lib) + add_to_front_list('PATH',path) + + return prefix + "/VC" + + +def _set_msvs_dev10(env, x64_host, x64_target, regv=None): # VS 2010 + if regv: + prefix = regv + else: + prefix = 'C:/Program Files (x86)/Microsoft Visual Studio 10.0' + + path = [] + lib = [] + libpath = [] + + inc = [] + add_env(inc, prefix + '/VC/INCLUDE') + add_env(inc, prefix + '/VC/ATLMFC/INCLUDE') + add_env(inc, 'c:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/include') + set_env_list('INCLUDE',inc) + + set_env('Framework35Version','v3.5') + set_env('FrameworkVersion', 'v4.0.20728') + set_env('FrameworkVersion32', 'v4.0.20728') + + set_env('VCINSTALLDIR', prefix + '/VC') + set_env('VS100COMNTOOLS', prefix + '/Common7/Tools') + set_env('VSINSTALLDIR' , prefix) + set_env('WindowsSdkDir', 'c:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A') + + # DevEnvDir has a trailing slash + set_env('DevEnvDir', prefix + '/Common7/IDE/') + + if x64_target: + set_env('FrameworkDir','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkDIR64','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkVersion64', 'v4.0.20728') + + set_env('Platform','X64') + add_env(lib, prefix + '/VC/LIB/amd64') + add_env(lib, prefix + '/VC/ATLMFC/LIB/amd64') + add_env(lib, 'c:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/lib/x64') + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.20728') + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework64/v3.5') + add_env(libpath, prefix + '/VC/LIB/amd64') + add_env(libpath, prefix + '/VC/ATLMFC/LIB/amd64') + + add_env(path, prefix + '/VC/BIN/amd64') + add_env(path, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.20728') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework64/v3.5') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Program Files (x86)/HTML Help Workshop') + add_env(path, 'C:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/' + + 'bin/NETFX 4.0 Tools/x64') + add_env(path, 'C:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/bin/x64') + add_env(path, 'C:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/bin') + else: + set_env('FrameworkDir', 'c:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkDIR32', 'c:/WINDOWS/Microsoft.NET/Framework') + + add_env(lib, prefix + '/VC/LIB') + add_env(lib, prefix + '/VC/ATLMFC/LIB') + add_env(lib, 'c:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/lib') + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework/v4.0.20728') + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework/v3.5') + add_env(libpath, prefix + '/VC/LIB') + add_env(libpath, prefix + '/VC/ATLMFC/LIB') + + add_env(path, prefix + '/Common7/IDE/') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix +'/Common7/Tools') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v4.0.20728') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework/v3.5') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, 'C:/Program Files (x86)/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools') + add_env(path, 'C;/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/' + + 'bin/NETFX 4.0 Tools') + add_env(path, 'C:/Program Files (x86)/Microsoft SDKs/Windows/v7.0A/bin') + + set_env_list('LIBPATH',libpath) + set_env_list('LIB',lib) + add_to_front_list('PATH',path) + + return prefix + "/VC" + + +def _set_msvs_dev11(env, x64_host, x64_target, regv=None): # msvs2012 + progfi = 'C:/Program Files (x86)' + if regv: + prefix = regv + else: + prefix = progfi + '/Microsoft Visual Studio 11.0' + + sdkdir = progfi + '/Microsoft SDKs/Windows/v8.0' + sdk8 = progfi + '/Microsoft SDKs/Windows/v8.0A' + sdk7 = progfi + '/Microsoft SDKs/Windows/v7.0A' + winkit = progfi + '/Windows Kits/8.0' + + path = [] + lib = [] + libpath = [] + + inc = [] + add_env(inc, prefix + '/VC/INCLUDE') + add_env(inc, prefix + '/VC/ATLMFC/INCLUDE') + add_env(inc, winkit + '/include') + add_env(inc, winkit + '/include/um') + add_env(inc, winkit + '/include/shared') + add_env(inc, winkit + '/include/winrt') + set_env_list('INCLUDE',inc) + + set_env('Framework35Version','v3.5') + set_env('FrameworkVersion', 'v4.0.30319') + set_env('FrameworkVersion32', 'v4.0.30319') + + set_env('VCINSTALLDIR', prefix + '/VC/') + set_env('VS110COMNTOOLS', prefix + '/Common7/Tools') + set_env('VSINSTALLDIR' , prefix) + set_env('WindowsSdkDir', winkit) + + + if x64_target: + set_env('FrameworkDir','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkDIR64','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkVersion64', 'v4.0.30319') + + set_env('Platform','X64') + + add_env(lib, prefix + '/VC/LIB/amd64') + add_env(lib, prefix + '/VC/ATLMFC/LIB/amd64') + add_env(lib, winkit + '/lib/win8/um/x64') + + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.30319') + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework64/v3.5') + add_env(libpath, prefix + '/VC/LIB/amd64') + add_env(libpath, prefix + '/VC/ATLMFC/LIB/amd64') + add_env(libpath, winkit + '/References/CommonConfiguration/Neutral') + add_env(libpath, sdkdir + 'ExtensionSDKs/Microsoft.VCLibs/11.0/' + + 'References/CommonConfiguration/neutral') + + add_env(path, prefix + '/VC/BIN/amd64') + add_env(path, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.30319') + add_env(path, 'C:/WINDOWS/Microsoft.NET/Framework64/v3.5') + + add_env(path, prefix + '/Common7/IDE/CommonExtensions/Microsoft/TestWindow') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Program Files (x86)/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools/x64') + add_env(path, prefix + '/Team Tools/Performance Tools') + add_env(path, winkit + '/8.0/bin/x64') + add_env(path, sdk8 + '/bin/NETFX 4.0 Tools/x64') + add_env(path, sdk7 + '/Bin/x64') + add_env(path, sdk8 + '/bin/NETFX 4.0 Tools') + add_env(path, sdk7 + '/Bin') + add_env(path, winkit + '/Windows Performance Toolkit') + add_env(path, 'C:/Program Files/Microsoft SQL Server/110/Tools/Binn') + + else: + set_env('FrameworkDir', 'c:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkDIR32', 'c:/WINDOWS/Microsoft.NET/Framework') + + add_env(lib, prefix + '/VC/LIB') + add_env(lib, prefix + '/VC/ATLMFC/LIB') + add_env(lib, winkit + '/lib/win8/um/x86') + + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework/v4.0.30319') + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework/v3.5') + add_env(libpath, prefix + '/VC/LIB') + add_env(libpath, prefix + '/VC/ATLMFC/LIB') + add_env(libpath, winkit + '/References/CommonConfiguration/Neutral') + add_env(libpath, sdkdir + '/ExtensionSDKs/Microsoft.VCLibs/11.0/' + + 'References/CommonConfiguration/neutral') + + + add_env(path, prefix + '/Common7/IDE/CommonExtensions/Microsoft/TestWindow') + add_env(path, 'C:/Program Files (x86)/Microsoft SDKs/F#/3.0/Framework/v4.0') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Windows/Microsoft.NET/Framework/v4.0.30319') + add_env(path, 'C:/Windows/Microsoft.NET/Framework/v3.5') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, 'C:/Program Files (x86)/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools') + add_env(path, winkit + '/bin/x86') + add_env(path, sdk8 + '/bin/NETFX 4.0 Tools') + add_env(path, sdk7 + '/Bin') + add_env(path, winkit + '/Windows Performance Toolkit') + add_env(path, 'C:/Program Files/Microsoft SQL Server/110/Tools/Binn') + + + + set_env_list('LIBPATH',libpath) + set_env_list('LIB',lib) + add_to_front_list('PATH',path) + + return prefix + "/VC" + + + +def _set_msvs_dev12(env, x64_host, x64_target, regv=None): # msvs2013 + progfi = 'C:/Program Files (x86)' + if regv: + prefix = regv + else: + prefix = progfi + '/Microsoft Visual Studio 12.0' + + sdk81a = progfi + '/Microsoft SDKs/Windows/v8.1A' + sdk81 = progfi + '/Microsoft SDKs/Windows/v8.1' + winkit = progfi + '/Windows Kits/8.1' + + + path = [] + lib = [] + libpath = [] + + inc = [] + add_env(inc, prefix + '/VC/INCLUDE') + add_env(inc, prefix + '/VC/ATLMFC/INCLUDE') + add_env(inc, winkit + '/include') # not used in msvs12 + add_env(inc, winkit + '/include/um') + add_env(inc, winkit + '/include/shared') + add_env(inc, winkit + '/include/winrt') + set_env_list('INCLUDE',inc) + + set_env('Framework40Version','v4.0') + set_env('FrameworkVersion', 'v4.0.30319') + set_env('ExtensionSdkDir', + sdk81 + '/ExtensionSDKs') + + set_env('VCINSTALLDIR', prefix + '/VC/') + set_env('VS120COMNTOOLS', prefix + '/Common7/Tools') + set_env('VSINSTALLDIR' , prefix) + set_env('WindowsSdkDir', winkit) + set_env('VisualStudioVersion','12.0') + + set_env('WindowsSDK_ExecutablePath_x86', + sdk81a + '/bin/NETFX 4.5.1 Tools/') + + if x64_target: + set_env('WindowsSDK_ExecutablePath_x64', + sdk81a +'/bin/NETFX 4.5.1 Tools/x64/') + + set_env('FrameworkDir','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkDIR64','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkVersion64', 'v4.0.30319') + + set_env('Platform','X64') + + add_env(lib, prefix + '/VC/LIB/amd64') + add_env(lib, prefix + '/VC/ATLMFC/LIB/amd64') + add_env(lib, winkit + '/lib/winv6.3/um/x64') + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.30319') + add_env(libpath, prefix + '/VC/LIB/amd64') + add_env(libpath, prefix + '/VC/ATLMFC/LIB/amd64') + add_env(libpath, winkit + '/References/CommonConfiguration/Neutral') + add_env(libpath, sdk81 + '/ExtensionSDKs/Microsoft.VCLibs/12.0/' + + 'References/CommonConfiguration/neutral') + + add_env(path, prefix + '/Common7/IDE/CommonExtensions/Microsoft/TestWindow') + add_env(path, prefix + '/VC/BIN/amd64') + add_env(path, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.30319') + + add_env(path, prefix + '/VC/VCPackages') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Program Files (x86)/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools/x64') + add_env(path, prefix + '/Team Tools/Performance Tools') + add_env(path, winkit + '/8.1/bin/x64') + add_env(path, winkit + '/8.1/bin/x86') + add_env(path, sdk81a + '/bin/NETFX 4.5.1 Tools/x64') + add_env(path, winkit + '/Windows Performance Toolkit') + + + else: + set_env('FrameworkDir', 'c:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkDIR32', 'c:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkVersion32','v4.0.30319') + + add_env(lib, prefix + '/VC/LIB') + add_env(lib, prefix + '/VC/ATLMFC/LIB') + add_env(lib, winkit + '/lib/winv6.3/um/x86') + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework/v4.0.30319') + add_env(libpath, prefix + '/VC/LIB') + add_env(libpath, prefix + '/VC/ATLMFC/LIB') + add_env(libpath, winkit + '/References/CommonConfiguration/Neutral') + add_env(libpath, sdk81 + '/ExtensionSDKs/Microsoft.VCLibs/12.0/' + + 'References/CommonConfiguration/neutral') + + + add_env(path, prefix + '/Common7/IDE/CommonExtensions/Microsoft/TestWindow') + add_env(path, progfi + '/Microsoft SDKs/F#/3.1/Framework/v4.0') + add_env(path, progfi + '/MSBuild/12.0/bin') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Windows/Microsoft.NET/Framework/v4.0.30319') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, progfi + '/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools') + add_env(path, winkit + '/bin/x86') + add_env(path, sdk81a + '/bin/NETFX 4.5.1 Tools') + add_env(path, winkit + '/Windows Performance Toolkit') + + + set_env_list('LIBPATH',libpath) + set_env_list('LIB',lib) + add_to_front_list('PATH',path) + + return prefix + "/VC" + + +def _get_winkit10_version(env, winkit10): + # Find the UCRT Version. Could not locate a registry entry with + # the information. Preview version of msvs2015/dev14 did not set + # the env var. Poke around in the directory system as a last + # resort. Could make this configrable + winkit10version = None + if 'UCRTVersion' in os.environ: + winkit10version = os.environ['UCRTVersion'] + + # Early versions of winkit10 that ship with MSVS2015(dev14) do not + # have the the required stuff so people had to rely on SDK + # 8.1. The early versions only have a ucrt subdirectory and not a + # "shared", "um" or "winrt" directories. We use the "shared" + # directory as our guide. + + if winkit10 and not winkit10version: + # use glob and find youngest named directory. This code had + # used os.path.getctime() but that gave the wrong result if an + # older SDK was installed after a younger SDK was installed. + dlist = glob(winkit10 + '/include/*') + dlist.sort(reverse=True) + for g in dlist: + if (os.path.exists('{}/shared'.format(g)) and + os.path.exists('{}/ucrt'.format(g)) ): + winkit10version = os.path.basename(g) + + if winkit10version: + complete = True + msgb("UCRT Version", winkit10version) + else: + complete = False + warn("Did not find winkit 10 version. RC tool may not be available") + + return (winkit10version,complete) + +def _find_msvc_version_directory(root): + ctime = 0 + msvc_ver = None + for g in glob(root + '/*'): + gtime = os.path.getctime(g) + if gtime > ctime: + msvc_ver = os.path.basename(g) + ctime = gtime + if not msvc_ver: + die("Could not find MSVC version directory.") + return msvc_ver + +def _find_latest_subdir(d): + ctime = 0 + for g in glob(d + '*'): + gtime = os.path.getctime(g) + if gtime > ctime: + ctime = gtime + subdir = g + return subdir +def _ijoin(x,y): + return '{}/{}'.format(x,y) + +def msvc_dir_from_vc_dir(vc_dir): + msvc_tools_root = vc_dir + '/Tools/MSVC' + msvc_ver = _find_msvc_version_directory(msvc_tools_root) + msvc_tools_root = _ijoin(msvc_tools_root,msvc_ver) + #msgb('MSVC version', msvc_tools_root) + return msvc_tools_root, msvc_ver + +def set_msvc_compilers(env,msvc_tools_root): + """set host/target paths for MSVS2017/DEV15. Also called from + build_env.py when using an externally configured shell.""" + x64_to_x64 = '{}/bin/Host{}/{}/'.format(msvc_tools_root,'x64','x64') + x64_to_x86 = '{}/bin/Host{}/{}/'.format(msvc_tools_root,'x64','x86') + x86_to_x64 = '{}/bin/Host{}/{}/'.format(msvc_tools_root,'x86','x64') + x86_to_x86 = '{}/bin/Host{}/{}/'.format(msvc_tools_root,'x86','x86') + env['msvc_compilers'] = {} + env['msvc_compilers']['ia32'] = {} + env['msvc_compilers']['x86-64'] = {} + env['msvc_compilers']['ia32']['ia32'] = x86_to_x64 + env['msvc_compilers']['ia32']['x86-64'] = x86_to_x86 + env['msvc_compilers']['x86-64']['ia32'] = x64_to_x86 + env['msvc_compilers']['x86-64']['x86-64'] = x64_to_x64 + + +def _set_msvs_dev16(env, x64_host, x64_target, regv=None): # msvs 2019 + versions = ['Enterprise', 'Professional', 'Community'] + + progfi = 'C:/Program Files (x86)' + if regv: + prefix = regv + else: + prefix = progfi + '/Microsoft Visual Studio/2019' + + if x64_target: + tgt = 'x64' + else: + tgt = 'x86' + + found = False + for v in versions: + p = _ijoin(prefix,v) + if os.path.exists(p): + found = True + break + if not found: + die('Could not find MSVS 2019 directory') + vprefix = p + winkit10 = progfi + '/Windows Kits/10' + winkit10version, winkit10complete = _get_winkit10_version(env,winkit10) + #msgb('WINKIT10 VERSION', winkit10version) + if winkit10complete == False: + die('need a complete winkit10 for MSVS 2019 (dev 16)') + env['rc_winkit'] = winkit10 + env['rc_winkit_number'] = winkit10version + + msvc_tools_root, msvc_ver = msvc_dir_from_vc_dir(vprefix + '/VC') + + netfx_sdk = progfi + '/Windows Kits/NETFXSDK/4.6.1/' + + path = [] + lib = [] + libpath = [] + inc = [] + + add_env(inc, prefix + '/ATLMFC/include') + add_env(inc, msvc_tools_root + '/include') + add_env(inc, netfx_sdk + 'include/um') + wki = '{}/include/{}'.format(winkit10, winkit10version) + add_env(inc, wki + '/ucrt') + add_env(inc, wki + '/shared') + add_env(inc, wki + '/um') + add_env(inc, wki + '/winrt') + add_env(inc, wki + '/cppwinrt') + + # LIB + wkl = '{}/lib/{}'.format(winkit10, winkit10version) + lib1 = '{}/ATLMFC/lib/{}'.format(msvc_tools_root,tgt) + lib2 = '{}/lib/{}'.format(msvc_tools_root,tgt) + add_env(lib, lib1) + add_env(lib, lib2) + add_env(lib, '{}lib/um/{}'.format(netfx_sdk,tgt)) + add_env(lib, '{}/ucrt/{}'.format(wkl,tgt)) + add_env(lib, '{}/um/{}'.format(wkl,tgt)) + + # LIBPATH + add_env(libpath, lib1) + add_env(libpath, lib2) + add_env(libpath, winkit10 + '/UnionMetadata') + add_env(libpath, winkit10 + '/References') + s = '' + if tgt == 'x64': + s = '64' + fwr = 'C:/windows/Microsoft.NET/Framework{}'.format(s) + fwr64 = 'C:/windows/Microsoft.NET/Framework64' + fwv = 'v4.0.30319' + fwp = '{}/{}'.format(fwr,fwv) + add_env(libpath, fwp) + + # PATH + + # locations for cross compilers changed in this version + set_msvc_compilers(env, msvc_tools_root) + x86_to_x64 = env['msvc_compilers']['ia32']['ia32'] + x86_to_x86 = env['msvc_compilers']['ia32']['x86-64'] + x64_to_x86 = env['msvc_compilers']['x86-64']['ia32'] + x64_to_x64 = env['msvc_compilers']['x86-64']['x86-64'] + + cross = False + if x64_host: + if x64_target: + cl_tgt_bin_dir = x64_to_x64 + else: + cross = True + cl_tgt_bin_dir = x64_to_x86 + cl_host_bin_dir = x64_to_x64 + else: + if x64_target: + cross = True + cl_tgt_bin_dir = x86_to_x64 + cl_host_bin_dir = x64_to_x86 + else: + cl_tgt_bin_dir = x86_to_x86 + + add_env(path, cl_tgt_bin_dir) + # CL TARGET compiler gets DLLs from the HOST bin dir + if cross: + add_env(path, cl_host_bin_dir) + + add_env(path, '{}/Common7/IDE/VC/VCPackages'.format(msvc_tools_root)) + add_env(path, '{}/Common7/IDE/CommonExtensions/Microsoft/TestWindow'.format(msvc_tools_root)) + add_env(path, '{}/Common7/IDE/CommonExtensions/Microsoft/TeamFoundation/Team Explorer'.format(msvc_tools_root)) + add_env(path, '{}/MSBuild/15.0/bin/Roslyn'.format(msvc_tools_root)) + add_env(path, '{}/Team Tools/Performance Tools'.format(msvc_tools_root)) + + add_env(path, progfi + '/Microsoft Visual Studio/Shared/Common/VSPerfCollectionTools') + netfx_tools = progfi + '/Microsoft SDKs/Windows/v10.0A/bin/NETFX 4.6.1 Tools' + add_env(path, netfx_tools) + + add_env(path, '{}/bin/{}'.format(winkit10,tgt)) + add_env(path, '{}/bin/{}/{}'.format(winkit10,winkit10version,tgt)) + add_env(path, '{}/MSBuild/15.0/bin'.format(vprefix)) + add_env(path, fwp) + add_env(path, '{}/Common7/IDE'.format(vprefix)) + add_env(path, '{}/Common7/Tools'.format(vprefix)) + + set_env_list('INCLUDE',inc) + set_env_list('LIB',lib) + set_env_list('LIBPATH',libpath) + add_to_front_list('PATH',path) + if 0: + msgb("INCLUDE", "\n\t".join(inc)) + msgb("LIB", "\n\t".join(lib)) + msgb("LIBPATH", "\n\t".join(libpath)) + msgb("PATH", "\n\t".join(path)) + + # Misc env variables. Not sure which are needed, if any + set_env('NETFXSDKDir',netfx_sdk) + set_env('DevEnvDir', vprefix + '/Common7/IDE/') + set_env('ExtensionSdkDir', progfi + '/Microsoft SDKs/Windows Kits/10/ExtensionSDKs') + set_env('Framework40Version','v4.0') + set_env('FrameworkVersion',fwv) + if x64_host: + set_env('VSCMD_ARG_HOST_ARCH','x64') + else: + set_env('VSCMD_ARG_HOST_ARCH','x86') + + set_env('Platform',tgt) + set_env('VSCMD_ARG_TGT_ARCH',tgt) + + if x64_target: + set_env('FrameworkDir', fwr) + set_env('FrameworkDIR64',fwr) + set_env('FrameworkVersion64',fwv) + else: + set_env('FrameworkDIR32',fwr) + set_env('FrameworkVersion32',fwv) + if x64_host: + set_env('FrameworkDir', fwr64) + set_env('FrameworkDIR64',fwr64) + set_env('FrameworkVersion64',fwv) + else: + set_env('FrameworkDir', fwr) + + set_env('UCRTVersion', winkit10version) + set_env('WindowsSDKLibVersion', winkit10version + '/') + set_env('WindowsSDKVersion', winkit10version + '/') + set_env('WindowsSdkVerBinPath', '{}/bin/{}/'.format(winkit10,winkit10version)) + set_env('WindowsSdkBinPath', winkit10 + '/bin/') + set_env('WindowsSdkDir', winkit10 + '/') + set_env('UniversalCRTSdkDir',winkit10 + '/') + set_env('WindowsLibPath', winkit10 + '/UnionMetadata;' + winkit10 + '/References') + + set_env('VCIDEInstallDir', vprefix + '/Common7/IDE/VC/') + set_env('VCINSTALLDIR', vprefix + '/VC/') + set_env('VCToolsInstallDir', vprefix + '/VC/Tools/MSVC/' + msvc_ver + '/') + set_env('VCToolsRedistDir', vprefix + '/VC/Redist/MSVC/' + msvc_ver + '/') + set_env('VS150COMNTOOLS', vprefix + '/Common7/Tools/') + set_env('VSINSTALLDIR', vprefix + '/') + set_env('VisualStudioVersion', '15.0') + + set_env('WindowsSDK_ExecutablePath_x64', netfx_tools + '/x64/') + set_env('WindowsSDK_ExecutablePath_x86', netfx_tools + '/') + + return vprefix + '/VC' + + +def _set_msvs_dev15(env, x64_host, x64_target, regv=None): # msvs 2017 + versions = ['Enterprise', 'Professional', 'Community'] + + progfi = 'C:/Program Files (x86)' + if regv: + prefix = regv + else: + prefix = progfi + '/Microsoft Visual Studio/2017' + + if x64_target: + tgt = 'x64' + else: + tgt = 'x86' + + found = False + for v in versions: + p = _ijoin(prefix,v) + if os.path.exists(p): + found = True + break + if not found: + die('Could not find MSVS 2017 directory') + vprefix = p + #msgb('VPREFIX', vprefix) + winkit10 = progfi + '/Windows Kits/10' + winkit10version, winkit10complete = _get_winkit10_version(env,winkit10) + #msgb('WINKIT10 VERSION', winkit10version) + if winkit10complete == False: + die('need a complete winkit10 for MSVS 2017 (dev 15)') + env['rc_winkit'] = winkit10 + env['rc_winkit_number'] = winkit10version + + msvc_tools_root, msvc_ver = msvc_dir_from_vc_dir(vprefix + '/VC') + + netfx_sdk = progfi + '/Windows Kits/NETFXSDK/4.6.1/' + + path = [] + lib = [] + libpath = [] + inc = [] + + add_env(inc, prefix + '/ATLMFC/include') + add_env(inc, msvc_tools_root + '/include') + add_env(inc, netfx_sdk + 'include/um') + wki = '{}/include/{}'.format(winkit10, winkit10version) + add_env(inc, wki + '/ucrt') + add_env(inc, wki + '/shared') + add_env(inc, wki + '/um') + add_env(inc, wki + '/winrt') + + # LIB + wkl = '{}/lib/{}'.format(winkit10, winkit10version) + lib1 = '{}/ATLMFC/lib/{}'.format(msvc_tools_root,tgt) + lib2 = '{}/lib/{}'.format(msvc_tools_root,tgt) + add_env(lib, lib1) + add_env(lib, lib2) + add_env(lib, '{}lib/um/{}'.format(netfx_sdk,tgt)) + add_env(lib, '{}/ucrt/{}'.format(wkl,tgt)) + add_env(lib, '{}/um/{}'.format(wkl,tgt)) + + # LIBPATH + add_env(libpath, lib1) + add_env(libpath, lib2) + add_env(libpath, winkit10 + '/UnionMetadata') + add_env(libpath, winkit10 + '/References') + s = '' + if tgt == 'x64': + s = '64' + fwr = 'C:/windows/Microsoft.NET/Framework{}'.format(s) + fwr64 = 'C:/windows/Microsoft.NET/Framework64' + fwv = 'v4.0.30319' + fwp = '{}/{}'.format(fwr,fwv) + add_env(libpath, fwp) + + # PATH + + # locations for cross compilers changed in this version + set_msvc_compilers(env, msvc_tools_root) + x86_to_x64 = env['msvc_compilers']['ia32']['ia32'] + x86_to_x86 = env['msvc_compilers']['ia32']['x86-64'] + x64_to_x86 = env['msvc_compilers']['x86-64']['ia32'] + x64_to_x64 = env['msvc_compilers']['x86-64']['x86-64'] + + cross = False + if x64_host: + if x64_target: + cl_tgt_bin_dir = x64_to_x64 + else: + cross = True + cl_tgt_bin_dir = x64_to_x86 + cl_host_bin_dir = x64_to_x64 + else: + if x64_target: + cross = True + cl_tgt_bin_dir = x86_to_x64 + cl_host_bin_dir = x64_to_x86 + else: + cl_tgt_bin_dir = x86_to_x86 + + add_env(path, cl_tgt_bin_dir) + # CL TARGET compiler gets DLLs from the HOST bin dir + if cross: + add_env(path, cl_host_bin_dir) + + add_env(path, '{}/Common7/IDE/VC/VCPackages'.format(msvc_tools_root)) + add_env(path, '{}/Common7/IDE/CommonExtensions/Microsoft/TestWindow'.format(msvc_tools_root)) + add_env(path, '{}/Common7/IDE/CommonExtensions/Microsoft/TeamFoundation/Team Explorer'.format(msvc_tools_root)) + add_env(path, '{}/MSBuild/15.0/bin/Roslyn'.format(msvc_tools_root)) + add_env(path, '{}/Team Tools/Performance Tools'.format(msvc_tools_root)) + + add_env(path, progfi + '/Microsoft Visual Studio/Shared/Common/VSPerfCollectionTools') + netfx_tools = progfi + '/Microsoft SDKs/Windows/v10.0A/bin/NETFX 4.6.1 Tools' + add_env(path, netfx_tools) + + add_env(path, '{}/bin/{}'.format(winkit10,tgt)) + add_env(path, '{}/bin/{}/{}'.format(winkit10,winkit10version,tgt)) + add_env(path, '{}/MSBuild/15.0/bin'.format(vprefix)) + add_env(path, fwp) + add_env(path, '{}/Common7/IDE'.format(vprefix)) + add_env(path, '{}/Common7/Tools'.format(vprefix)) + + set_env_list('INCLUDE',inc) + set_env_list('LIB',lib) + set_env_list('LIBPATH',libpath) + add_to_front_list('PATH',path) + if 0: + msgb("INCLUDE", "\n\t".join(inc)) + msgb("LIB", "\n\t".join(lib)) + msgb("LIBPATH", "\n\t".join(libpath)) + msgb("PATH", "\n\t".join(path)) + + # Misc env variables. Not sure which are needed, if any + set_env('NETFXSDKDir',netfx_sdk) + set_env('DevEnvDir', vprefix + '/Common7/IDE/') + set_env('ExtensionSdkDir', progfi + '/Microsoft SDKs/Windows Kits/10/ExtensionSDKs') + set_env('Framework40Version','v4.0') + set_env('FrameworkVersion',fwv) + if x64_host: + set_env('VSCMD_ARG_HOST_ARCH','x64') + else: + set_env('VSCMD_ARG_HOST_ARCH','x86') + + set_env('Platform',tgt) + set_env('VSCMD_ARG_TGT_ARCH',tgt) + + if x64_target: + set_env('FrameworkDir', fwr) + set_env('FrameworkDIR64',fwr) + set_env('FrameworkVersion64',fwv) + else: + set_env('FrameworkDIR32',fwr) + set_env('FrameworkVersion32',fwv) + if x64_host: + set_env('FrameworkDir', fwr64) + set_env('FrameworkDIR64',fwr64) + set_env('FrameworkVersion64',fwv) + else: + set_env('FrameworkDir', fwr) + + set_env('UCRTVersion', winkit10version) + set_env('WindowsSDKLibVersion', winkit10version + '/') + set_env('WindowsSDKVersion', winkit10version + '/') + set_env('WindowsSdkVerBinPath', '{}/bin/{}/'.format(winkit10,winkit10version)) + set_env('WindowsSdkBinPath', winkit10 + '/bin/') + set_env('WindowsSdkDir', winkit10 + '/') + set_env('UniversalCRTSdkDir',winkit10 + '/') + set_env('WindowsLibPath', winkit10 + '/UnionMetadata;' + winkit10 + '/References') + + set_env('VCIDEInstallDir', vprefix + '/Common7/IDE/VC/') + set_env('VCINSTALLDIR', vprefix + '/VC/') + set_env('VCToolsInstallDir', vprefix + '/VC/Tools/MSVC/' + msvc_ver + '/') + set_env('VCToolsRedistDir', vprefix + '/VC/Redist/MSVC/' + msvc_ver + '/') + set_env('VS150COMNTOOLS', vprefix + '/Common7/Tools/') + set_env('VSINSTALLDIR', vprefix + '/') + set_env('VisualStudioVersion', '15.0') + + set_env('WindowsSDK_ExecutablePath_x64', netfx_tools + '/x64/') + set_env('WindowsSDK_ExecutablePath_x86', netfx_tools + '/') + + return vprefix + '/VC' + +def _set_msvs_dev14(env, x64_host, x64_target, regv=None): # msvs 2015 + progfi = 'C:/Program Files (x86)' + if regv: + prefix = regv + else: + prefix = progfi + '/Microsoft Visual Studio 14.0' + + sdk81a = progfi + '/Microsoft SDKs/Windows/v8.1A' + sdk81 = progfi + '/Microsoft SDKs/Windows/v8.1' + sdk10a = progfi + '/Microsoft SDKs/Windows/v10.0A' + if os.path.exists(sdk10a): + sdk81a = None + sdk81 = None + else: + sdk10a = None + + winkit8 = progfi + '/Windows Kits/8.1' + winkit10 = progfi + '/Windows Kits/10' + + if os.path.exists(winkit10): + winkit = winkit10 + sdk81 = None + sdk81a = None + else: + winkit = winkit8 + winkit10 = None + + winkit10version, winkit10complete = _get_winkit10_version(env,winkit10) + # if winkit10complete is False, we need to fall back on + # winkit8 for some stuff + + if winkit10complete: + env['rc_winkit'] = winkit10 + env['rc_winkit_number'] = winkit10version + else: + env['rc_winkit'] = winkit8 + + path = [] + lib = [] + libpath = [] + + inc = [] + add_env(inc, prefix + '/VC/INCLUDE') + add_env(inc, prefix + '/VC/ATLMFC/INCLUDE') + + if winkit10version: + t = '{}/include/{}'.format(winkit10,winkit10version) + add_env(inc, t + '/ucrt') + + if winkit10version and winkit10complete: + add_env(inc, t + '/shared') + add_env(inc, t + '/um') + add_env(inc, t + '/winrt') + else: + add_env(inc, winkit8 + '/include') # not used in msvs12 + add_env(inc, winkit8 + '/include/shared') + add_env(inc, winkit8 + '/include/um') + add_env(inc, winkit8 + '/include/winrt') + + set_env_list('INCLUDE',inc) + + set_env('Framework40Version', 'v4.0') + set_env('FrameworkVersion', 'v4.0.30319') + #set_env('ExtensionSdkDir', sdk81 + '/ExtensionSDKs') + + set_env('VCINSTALLDIR', prefix + '/VC/') + set_env('VS140COMNTOOLS', prefix + '/Common7/Tools') + set_env('VSINSTALLDIR' , prefix) + set_env('WindowsSdkDir', winkit + '/') + set_env('VisualStudioVersion','14.0') + + if sdk10a: + set_env('WindowsSDK_ExecutablePath_x86', + sdk10a + '/bin/NETFX 4.6.1 Tools/') + elif sdk81a: + set_env('WindowsSDK_ExecutablePath_x86', + sdk81a + '/bin/NETFX 4.5.1 Tools/') + + if x64_target: + if sdk10a: + set_env('WindowsSDK_ExecutablePath_x64', + sdk10a +'/bin/NETFX 4.6.1 Tools/x64/') + elif sdk81a: + set_env('WindowsSDK_ExecutablePath_x64', + sdk81a +'/bin/NETFX 4.5.1 Tools/x64/') + + set_env('FrameworkDir','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkDIR64','c:/WINDOWS/Microsoft.NET/Framework64') + set_env('FrameworkVersion64', 'v4.0.30319') + + set_env('Platform','X64') + + add_env(lib, prefix + '/VC/LIB/amd64') + add_env(lib, prefix + '/VC/ATLMFC/LIB/amd64') + if winkit10version: + add_env(lib, winkit10 + '/lib/{}/ucrt/x64'.format(winkit10version)) + if winkit10version and winkit10complete: + add_env(lib, winkit10 + '/lib/{}/um/x64'.format(winkit10version)) + else: + add_env(lib, winkit8 + '/lib/winv6.3/um/x64') + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.30319') + add_env(libpath, prefix + '/VC/LIB/amd64') + add_env(libpath, prefix + '/VC/ATLMFC/LIB/amd64') + if not winkit10: + add_env(libpath, winkit + '/References/CommonConfiguration/Neutral') + # next one is usually not present and I am unclear of value/need + #if sdk81: + # add_env(libpath, sdk81 + '/ExtensionSDKs/Microsoft.VCLibs/14.0/' + + # 'References/CommonConfiguration/neutral') + + add_env(path, prefix + '/Common7/IDE/CommonExtensions/Microsoft/TestWindow') + add_env(path, prefix + '/VC/BIN/amd64') + add_env(path, 'c:/WINDOWS/Microsoft.NET/Framework64/v4.0.30319') + + add_env(path, prefix + '/VC/VCPackages') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Program Files (x86)/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools/x64') + add_env(path, prefix + '/Team Tools/Performance Tools') + + if winkit10complete: + t = winkit10 + else: + t = winkit8 + add_env(path, t + '/bin/x64') + add_env(path, t + '/bin/x86') + + if sdk10a: + b = _find_latest_subdir(sdk10a + '/bin/') + add_env(path, b + '/x64') + elif sdk81a: + add_env(path, sdk81a + '/bin/NETFX 4.5.1 Tools/x64') + + else: # 32b + set_env('FrameworkDir', 'c:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkDIR32', 'c:/WINDOWS/Microsoft.NET/Framework') + set_env('FrameworkVersion32','v4.0.30319') + + add_env(lib, prefix + '/VC/LIB') + add_env(lib, prefix + '/VC/ATLMFC/LIB') + if winkit10version: + add_env(lib, winkit10 + '/lib/{}/ucrt/x86'.format(winkit10version)) + if winkit10version and winkit10complete: + add_env(lib, winkit10 + '/lib/{}/um/x86'.format(winkit10version)) + else: + add_env(lib, winkit8 + '/lib/winv6.3/um/x86') + + add_env(libpath, 'c:/WINDOWS/Microsoft.NET/Framework/v4.0.30319') + add_env(libpath, prefix + '/VC/LIB') + add_env(libpath, prefix + '/VC/ATLMFC/LIB') + if not winkit10complete: + add_env(libpath, winkit8 + '/References/CommonConfiguration/Neutral') + # next one is usually not present and I am unclear of value/need + #if sdk81: + # add_env(libpath, sdk81 + '/ExtensionSDKs/Microsoft.VCLibs/14.0/' + + # 'References/CommonConfiguration/neutral') + + add_env(path, prefix + '/Common7/IDE/CommonExtensions/Microsoft/TestWindow') + add_env(path, progfi + '/Microsoft SDKs/F#/3.1/Framework/v4.0') + add_env(path, progfi + '/MSBuild/14.0/bin') + add_env(path, prefix + '/Common7/IDE') + add_env(path, prefix + '/VC/BIN') + add_env(path, prefix + '/Common7/Tools') + add_env(path, 'C:/Windows/Microsoft.NET/Framework/v4.0.30319') + add_env(path, prefix + '/VC/VCPackages') + add_env(path, progfi + '/HTML Help Workshop') + add_env(path, prefix + '/Team Tools/Performance Tools') + + if winkit10complete: + t = winkit10 + else: + t = winkit8 + add_env(path, t + '/bin/x86') + + if sdk10a: + b = _find_latest_subdir(sdk10a + '/bin/') + add_env(path, b + '/x64') + elif sdk81a: + add_env(path, sdk81a + '/bin/NETFX 4.5.1 Tools') + + + set_env_list('LIBPATH',libpath) + set_env_list('LIB',lib) + add_to_front_list('PATH',path) + + return prefix + "/VC" + + +def _figure_out_msvs_version_filesystem(env, specific_version=0): + """If specific_version is set to one of the listed versions, this will + only return success if that version is found. Otherwise it returns + the latest install. """ + + prefixes = [ + (16,'C:/Program Files (x86)/Microsoft Visual Studio/2019'), + + # starting with DEV15, everything is in the "Program Files + # (x86)" directory. + (15,'C:/Program Files (x86)/Microsoft Visual Studio/2017'), + + (14,'C:/Program Files (x86)/Microsoft Visual Studio 14.0'), + (14,'C:/Program Files/Microsoft Visual Studio 14.0'), + + (12,'C:/Program Files (x86)/Microsoft Visual Studio 12.0'), + (12,'C:/Program Files/Microsoft Visual Studio 12.0'), + + (11,'C:/Program Files (x86)/Microsoft Visual Studio 11.0'), + (11,'C:/Program Files/Microsoft Visual Studio 11.0'), + + (10,'C:/Program Files (x86)/Microsoft Visual Studio 10.0'), + (10,'C:/Program Files/Microsoft Visual Studio 10.0'), + + (9,'C:/Program Files (x86)/Microsoft Visual Studio 9.0'), + (9,'C:/Program Files/Microsoft Visual Studio 9.0'), + + (8, "c:/Program Files (x86)/Microsoft Visual Studio 8"), + (8,"c:/Program Files/Microsoft Visual Studio 8"), + + (7, "c:/Program Files/Microsoft Visual Studio .NET 2003"), + (7,"c:/Program Files (x86)/Microsoft Visual Studio .NET 2003") + ] + for v,dir in prefixes: + if os.path.exists(dir): + if specific_version: + if specific_version == v: + return str(v) + else: + return str(v) + return None # we don't know + +_is_py2 = sys.version[0] == '2' + +def _read_registry(root,key,value): + if _is_py2: + import _winreg as winreg + else: + import winreg + try: + hkey = winreg.OpenKey(root, key) + except: + return None + try: + (val, typ) = winreg.QueryValueEx(hkey, value) + except: + winreg.CloseKey(hkey) + return None + winreg.CloseKey(hkey) + return val + +def pick_compiler(env): + if env['msvs_version']: + if int(env['msvs_version']) >= 15: + compilers_dict = env['msvc_compilers'] + return compilers_dict[env['build_cpu']][env['host_cpu']] + return _pick_compiler_until_dev14(env) + +def _pick_compiler_until_dev14(env): + if env['build_cpu'] == 'ia32' and env['host_cpu'] == 'ia32': + toolchain = os.path.join(env['vc_dir'], 'bin', '') + elif env['build_cpu'] == 'ia32' and env['host_cpu'] == 'x86-64': + toolchain = os.path.join(env['vc_dir'], 'bin', 'x86_amd64', '') + elif env['build_cpu'] == 'x86-64' and env['host_cpu'] == 'x86-64': + toolchain = os.path.join(env['vc_dir'], 'bin', 'amd64', '') + elif env['build_cpu'] == 'x86-64' and env['host_cpu'] == 'ia32': + toolchain = os.path.join(env['vc_dir'], 'bin', '') + elif env['compiler'] == 'ms': + die("Unknown build/target combination. build cpu=%s, " + + "host_cpu=%s" % ( env['build_cpu'], env['host_cpu'])) + return toolchain + +def _find_msvc_in_registry(env,version): + if _is_py2: + import _winreg as winreg + else: + import winreg + + vs_ver = str(version) + '.0' + vs_key = 'SOFTWARE\\Microsoft\\VisualStudio\\' + vs_ver + '\\Setup\\VS' + vc_key = 'SOFTWARE\\Microsoft\\VisualStudio\\' + vs_ver + '\\Setup\\VC' + vs_dir = _read_registry(winreg.HKEY_LOCAL_MACHINE, vs_key, 'ProductDir') + vc_dir = _read_registry(winreg.HKEY_LOCAL_MACHINE, vc_key, 'ProductDir') + + # On a 64-bit host, look for a 32-bit installation + + if (not vs_dir or not vc_dir): + vs_key = 'SOFTWARE\\Wow6432Node\\Microsoft\\VisualStudio\\' + \ + vs_ver + '\\Setup\\VS' + vc_key = 'SOFTWARE\\Wow6432Node\\Microsoft\\VisualStudio\\' + \ + vs_ver + '\\Setup\\VC' + vs_dir = _read_registry(winreg.HKEY_LOCAL_MACHINE, + vs_key, 'ProductDir') + vc_dir = _read_registry(winreg.HKEY_LOCAL_MACHINE, + vc_key, 'ProductDir') + return (vs_dir,vc_dir) + +def _figure_out_msvs_version_registry(env): + # starting with DEV15 (MSVS2017) MS stopped using the + # registry to store installation information. + versions = [14,12,11,10,9,8,7,6] + for v in versions: + (vs_dir,vc_dir) = _find_msvc_in_registry(env,v) + if vs_dir and vc_dir: + return (str(v),vs_dir) + return (None,None) + +def _find_specific_msvs_version(env,uv): + """Search for (integer) uv version of MSVS in registry & file system""" + found = False + # 1. look for specific version in registry + if uv < 15: + (vs_dir,vc_dir) = _find_msvc_in_registry(env,uv) + if vs_dir and vc_dir: + env['msvs_version'] = str(uv) + found = True + else: + warn("Could not find specified version of MSVS in registry: {}".format(uv)) + + # 2. look in file system for specific version + if not found: + env['msvs_version'] = _figure_out_msvs_version_filesystem(env, uv) + if env['msvs_version']: + found = True + else: + warn("Could not find specified version of MSVS in file system: {}".format(uv)) + return found + + + +def set_msvs_env(env): + versions = [] + if env['msvs_version'] != '' : + if ',' in env['msvs_version']: # got a list of versions + versions = map(str.strip,env['msvs_version'].split(',')) + else: + versions = [ env['msvs_version'] ] + + found = False + for uv in versions: + iuv = int(uv) + if _find_specific_msvs_version(env,iuv): + found = True + break + if versions and not found: + die("Could not find specified MSVS version(s): [{}]".format(",".join(versions))) + + # 3. Trying to locate newest version in file system. Must do this + # before generic registry search because regitry stopped being + # updated with DEV15/MSVS2017. + if not found: + env['msvs_version'] = _figure_out_msvs_version_filesystem(env) + if env['msvs_version']: + found = True + + # 4. try latest version in registry + if not found: + env['msvs_version'], vs_dir = _figure_out_msvs_version_registry(env) + + if not env['msvs_version']: + die("Did not find MSVS version!") + + + + x64_target=False + if env['host_cpu'] == 'x86-64': + x64_target=True + + x64_host = False + if env['build_cpu'] == 'x86-64': + x64_host=True + + + # "express" compiler is 32b only + vc = None + vs_dir = None + i = int(env['msvs_version']) + if i == 6: # 32b only + vc = _set_msvs_dev6(env,x64_host, x64_target) + elif i == 7: # 32b only + vc = _set_msvs_dev7(env,x64_host, x64_target) + elif i == 8: + vc = _set_msvs_dev8(env, x64_host, x64_target, vs_dir) + elif i == 9: + vc = _set_msvs_dev9(env, x64_host, x64_target, vs_dir) + elif i == 10: + vc = _set_msvs_dev10(env, x64_host, x64_target, vs_dir) + elif i == 11: + vc = _set_msvs_dev11(env, x64_host, x64_target, vs_dir) + elif i == 12: + vc = _set_msvs_dev12(env, x64_host, x64_target, vs_dir) + # And 12 shall be followed by 14. 13? 13 is Right Out! + elif i == 14: + vc = _set_msvs_dev14(env, x64_host, x64_target, vs_dir) + elif i == 15: # vs 2017 + vc = _set_msvs_dev15(env, x64_host, x64_target, vs_dir) + elif i == 16: # vs 2019 + vc = _set_msvs_dev16(env, x64_host, x64_target, vs_dir) + else: + die("Unhandled MSVS version: " + env['msvs_version']) + + msgb("FOUND MS VERSION",env['msvs_version']) + return vc + diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/osenv.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/osenv.py new file mode 100644 index 0000000..6231a8c --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/osenv.py @@ -0,0 +1,77 @@ +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""OS Environment accessors +""" +from __future__ import print_function +import os +import sys +from .base import * + +def _get_osenv_sep(): + if on_native_windows(): + return ';' + return ':' + +def get_env(v): + "return the osenv var v as a string" + if v in os.environ: + return os.environ[v] + return '' + +def get_env_list(v): + "return the osenv var v as a list" + if v in os.environ: + sep = _get_osenv_sep() + return os.environ[v].split(sep) + return [] + +def set_env(v,s): + """Add v=s to the shell environment""" + if v in os.environ: + orig = os.environ[v] + else: + orig = '' + + # We have had issues on windows were we attempt to make the + # environment too long. This catches the error and prints a nice + # error msg. + try: + os.environ[v]=s + except Exception as e: + sys.stderr.write( str(e) + '\n') + sys.stderr.write("Env Variable [%s]\n" % (v)) + sys.stderr.write("Original was [%s]\n" % (orig)) + sys.stderr.write("New value was [%s]\n" % (s)) + sys.exit(1) + +def set_env_list(v,slist): + """Add list to os env var v""" + sep = _get_osenv_sep() + set_env(v,sep.join(slist)) + +def add_to_front(v,s): + """Add v=s+old_v to the shell environment""" + sep = _get_osenv_sep() + set_env(v,s + sep + os.environ[v]) + +def add_to_front_list(v,slist): + "Add slist to front of env, adding os-specific separator" + sep = _get_osenv_sep() + add_to_front(v,sep.join(slist)) diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/plan.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/plan.py new file mode 100644 index 0000000..5664cf8 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/plan.py @@ -0,0 +1,93 @@ +# -*- python -*- +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""Intermediate data structure produced by builders and sent to the +dependence directed acyclic graph (DAG) that sequences execution. + +Users who create their own builders to call python functions should emit +an plan_t object and add it to the DAG. +""" + +class plan_t(object): + """ + An object that the builders create and is passed to the DAG L{dag_t} to + order the tasks. This is used exclusively to create + L{command_t}'s. + """ + def __init__(self, command, args=None, env=None, input=None, output=None, name=None): + """ + Create an input record for the L{dag_t} describing a + command. The command can be a string to execute or a python + function or a list of strings and python functions. The python + function will be passed two arguments: args and env. args is + typically a list, but could be anything. + + The input and output lists of files are used by the L{dag_t} to + order this command relative to other commands. + + When the command is a python function, the python function is + called with two arguments: args and an env of type + L{env_t}. The args can be anything but are typically the + inputs to the python function and any information required to + generate the corresponding outputs. The python functions return + a 2-typle (retcode, stdout). + + The input list: When the command is a python function, the + plan_t's input list contains at least the input files names + passed via args variable. The input list can be a superset + containing more stuff that might trigger the command + execution. + + If the command does not produce a specific output, you can + specify a dummy file name to allow sequencing relative to + other commands. + + @type command: string or python function or a list + @param command: string or python function. + + @type args: list + @param args: (optional) arguments to the command if it is a python function + + @type env: L{env_t} + @param env: (optional) an environment to pass to the python function + + @type input: list + @param input: (optional) files upon which this command depends. + + @type output: list + @param output: (optional) files which depend on this command. + + @type name: string + @param name: (optional) short name to be used to identify the work/task + """ + self.command = command + self.args = args + self.env = env + self.input = input + self.output = output + self.name = name + + def __str__(self): + s = [] + if self.name: + s.append('NAME: ' + str(self.name)) + s.append('CMD: ' + str(self.command)) + s.append('INPUT: ' + str(self.input)) + s.append('OUTPUT: ' + str(self.output)) + return " ".join(s) diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/scanner.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/scanner.py new file mode 100644 index 0000000..b155399 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/scanner.py @@ -0,0 +1,111 @@ +# -*- python -*- +# Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""Function for header include scanning""" +from __future__ import print_function +import re +import os +import sys +from . import base +from . import util + + +class mbuild_header_record_t: + """Stores information about headers that we find""" + def __init__(self, fn, found=True): + self.file_name = fn + self.system = False + self.found = found + def __str__(self): + s = '' + s = self.file_name + if self.system: + s += ' system' + if not self.found: + s += ' not-found' + return s + +def mbuild_compute_path(hname, search_path): + """Return the full path of the header hname, if found and None + otherwise. Search the path in order and see if we find the file""" + for p in search_path: + tname = util.join(p,hname) + tname = os.path.realpath(tname) + #mbuild_base.msgb("TESTING", tname) + if os.path.exists(tname): + return tname + return None + +# FIXME: ignoring system headers for now. +mbuild_include_pattern = re.compile(r'^[ \t]*#[ \t]*include[ \t]+"(?P[^"]+)"') +mbuild_nasm_include_pattern = re.compile(r'^[ \t]*%include[ \t]+"(?P[^"]+)"') + +is_py2 = sys.version[0] == '2' +def _open_errors(fn): + if is_py2: + return open(fn, 'r') + else: + return open(fn, 'r', errors='ignore') + +def mbuild_scan(fn, search_path): + """Given a file name fn, and a list of search paths, scan for + headers in fn and return a list of mbuild_header_record_t's. The + header records indicate if the file is a system include based on + <> symbols or if the file was missing. If the file cannot be + found, we assume it is in the assumed_directory.""" + global mbuild_include_pattern + global mbuild_nasm_include_pattern + + all_names = [] + + if not os.path.exists(fn): + return all_names + + source_path = os.path.dirname(fn) + if source_path == '': + source_path = '.' + aug_search_path = [source_path] + search_path + + with _open_errors(fn) as f: + for line in f: + hgroup = mbuild_include_pattern.match(line) + if not hgroup: + hgroup = mbuild_nasm_include_pattern.match(line) + if hgroup: + hname = hgroup.group('hdr') + full_name = mbuild_compute_path(hname, aug_search_path) + if full_name: + hr = mbuild_header_record_t(full_name) + else: + hr = mbuild_header_record_t(hname, found=False) + all_names.append(hr) + return all_names + + + +def _test_scan(): + paths = ["/home/mjcharne/proj/learn/" ] + all_headers = mbuild_scan("/home/mjcharne/proj/learn/foo.cpp", paths) + for hr in all_headers: + print (hr) + +if __name__ == '__main__': + _test_scan() + diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/util.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/util.py new file mode 100644 index 0000000..8d1c740 --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/util.py @@ -0,0 +1,1185 @@ +# -*- python -*- +# Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""Basic useful utilities: file copying, removal, permissions, +path-name manipulation, and command execution.""" + +import os +import re +import glob +import io # for io.open +import sys +import shutil +import stat +import types +import time +import subprocess +import tempfile +import shlex +import traceback +try: + import cPickle as apickle +except: + import pickle as apickle + +from .base import * + + +def find_python(env): + """return path to NON cygwin""" + pycmd = sys.executable # use whatever the user invoked us with + if env.on_windows() and env.on_cygwin(): + # avoid cygwin python + if pycmd in ['/usr/bin/python', '/bin/python']: + python_commands = [ 'c:/python27/python.exe', + 'c:/python26/python.exe', + 'c:/python25/python.exe' ] + pycmd = None + for p in python_commands: + if os.path.exists(p): + return p + if not pycmd: + die("Could not find win32 python at these locations: %s" % + "\n\t" + "\n\t".join(python_commands)) + + return pycmd +def copy_file(src,tgt): + """Copy src to tgt.""" + if verbose(2): + msgb("COPY", tgt + " <- " + src) + shutil.copy(src,tgt) +def move_file(src,tgt): + """Move/Rename src to tgt.""" + if verbose(2): + msgb("MOVE", src + " -> " + tgt) + shutil.move(src,tgt) +def symlink(env,src,tgt): + """Make a symlink from src to target. Not available on windows.""" + if env.on_windows(): + die("symlink() not available on windows") + if verbose(2): + msgb("SYMLINK", src + " -> " + tgt) + os.symlink(src,tgt) + +def copy_tree(src,tgt, ignore_patterns=None, symlinks=False): + """Copy the tree at src to tgt. This will first remove tgt if it + already exists.""" + if verbose(2): + msgb("COPYTREE", tgt + " <- " + src) + if not os.path.exists(src): + error_msg("SRC TREE DOES NOT EXIST", src) + raise Exception + if os.path.exists(tgt): + if verbose(2): + msgb("Removing existing target tree", tgt) + shutil.rmtree(tgt, ignore_errors=True) + if verbose(2): + msgb("Copying to tree", tgt) + if ignore_patterns: + sp = shutil.ignore_patterns(ignore_patterns) + else: + sp = None + shutil.copytree(src,tgt,ignore=sp, symlinks=symlinks) + if verbose(2): + msgb("Done copying tree", tgt) + +def cmkdir(path_to_dir): + """Make a directory if it does not exist""" + if not os.path.exists(path_to_dir): + if verbose(2): + msgb("MKDIR", path_to_dir) + os.makedirs(path_to_dir) +def list2string(ls): + """Print a list as a string""" + s = " ".join(ls) + return s + +def util_add_to_list(olst, v): + """Add v to olst. v can be a list or a non-list object. If v is a + list, extend olst. If v is not a list, append to olst. """ + if isinstance(v,list): + olst.extend(v) + else: + olst.append(v) + +def remove_file(fn, env=None, quiet=True): + """Remove a file or link if it exists. env parameter is not used.""" + if os.path.exists(fn): + make_writable(fn) + if os.path.exists(fn) or os.path.lexists(fn): + if not quiet: + vmsgb(2, "REMOVING", fn) + os.unlink(fn) + return (0, []) +def remove_tree(dir_name, env=None, dangerous=False): + """Remove a directory if it exists. env parameter is not + used. This will not remove a directory that has a .svn or .git + subdirectory indicating it is a source directory. Warning: It does + not look recursively for .svn/.git subdirectories. + @type dir_name: string + @param dir_name: a directory name + @type env: L{env_t} + @param env: optional. Not currently used. + @type dangerous: bool + @param dangerous: optional. If True,will delete anything including svn trees!! BE CAREFUL! default False. + """ + + def _important_file(dir_name): + for idir in ['.git', '.svn']: + if os.path.exists(os.path.join(dir_name, idir)): + return True + return False + + vmsgb(2, "CHECKING", dir_name) + if os.path.exists(dir_name): + if not dangerous and _important_file(dir_name): + s = 'Did not remove directory {} because of a .svn/.git subdirectory'.format(dir_name) + warn(s) + return (1, [ s ]) + vmsgb(2, "REMOVING", dir_name) + make_writable(dir_name) + shutil.rmtree(dir_name, ignore_errors = True) + return (0, []) +def remove_files(lst, env=None): + """Remove all the files in the list of files, lst. The env + parameter is not used""" + for fn in lst: + remove_file(fn) + return (0, []) + +def remove_files_glob(lst,env=None): + """Remove all files in the list of wild card expressions. The env + parameter is not used""" + for fn_glob in lst: + #msgb("REMOVING", fn_glob) + for file_name in glob(fn_glob): + remove_file(file_name) + return (0, []) + +def remove_files_from_tree(dir, file_patterns): + """Remove files that match the re object compiled pattern provided""" + for (dir, subdirs, subfiles) in os.walk(dir): + for file_name in subfiles: + fn = os.path.join(dir,file_name) + if file_patterns.search(fn): + remove_file(fn) + + +_readable_by_all = stat.S_IRUSR|stat.S_IRGRP|stat.S_IROTH +_readable_by_ug = stat.S_IRUSR|stat.S_IRGRP +_executable_by_all = stat.S_IXUSR|stat.S_IXGRP|stat.S_IXOTH +_executable_by_ug = stat.S_IXUSR|stat.S_IXGRP +_writeable_by_me = stat.S_IWUSR +_rwx_by_me = stat.S_IWUSR| stat.S_IRUSR|stat.S_IXUSR +_writeable_by_ug = stat.S_IWUSR|stat.S_IWGRP + +def make_writable(fn): + """Make the file or directory readable/writable/executable by me""" + global _rwx_by_me + os.chmod(fn, _rwx_by_me) + +def make_executable(fn): + """Make the file or directory readable & executable by user/group, writable by user""" + global _executable_by_ug + global _readable_by_ug + global _writeable_by_me + os.chmod(fn, _readable_by_ug|_writeable_by_me|_executable_by_ug) + +def modify_dir_tree(path, dir_fn=None, file_fn=None): + """Walk the tree rooted at path and apply the function dir_fn to + directories and file_fn to files. This is intended for doing + recursive chmods, etc.""" + if dir_fn: + dir_fn(path) + for (dir, subdirs, subfiles) in os.walk(path): + if dir_fn: + for subdir in subdirs: + dir_fn(os.path.join(dir,subdir)) + if file_fn: + for file_name in subfiles: + file_fn(os.path.join(dir,file_name)) + + +def make_read_only(fn): + """Make the file fn read-only""" + global _readable_by_all + os.chmod(fn, _readable_by_all) + +def make_web_accessible(fn): + """Make the file readable by all and writable by the current owner""" + global _readable_by_all + global _writeable_by_me + if verbose(8): + msgb("make_web_accessible", fn) + os.chmod(fn, _writeable_by_me|_readable_by_all) +def make_web_accessible_dir(dir): + """Make the directory readable and executable by all and writable + by the current owner""" + global _readable_by_all + global _executable_by_all + global _writeable_by_me + if verbose(8): + msgb("make_web_accessible_dir", dir) + os.chmod(dir, _writeable_by_me|_readable_by_all|_executable_by_all) + +def make_documentation_tree_accessible(dir): + """Make the directory teree rooted at dir web-accessible. That is, + the directories are readable and executable by anyone and the + files are readable by anyone.""" + msgb("CHMOD TREE", dir) + modify_dir_tree(dir, make_web_accessible_dir, make_web_accessible) + + + +def prefix_files(dir,input_files): + """Add dir on to the front of the input file or files. Works with + strings or lists of strings. + @type dir: string + @param dir: prefix directory + + @type input_files: string or list of strings + @param input_files: name(s) of files + + @rtype: string or list of strings + @return: input file(s) prefixed with dir sp + """ + if isinstance(input_files,list): + new_files = [join(dir,x) for x in input_files] + return new_files + elif is_stringish(input_files): + new_file = join(dir, input_files) + return new_file + die("Unhandled type in prefix_files: "+ str(type(input_files))) + +def quote(fn): + """Add quotes around the file nameed fn. Return a string""" + return "\"%s\"" % fn + +def qdip(fn): + """Add quotes to a string if there are spaces in the name""" + if re.search(' ',fn): + return '"%s"' % fn + return fn + + +def touch(fn): + """Open a file for append. Write nothing to it""" + vmsgb(1, "TOUCH", fn) + f=open(fn,"a") + f.close() + +############################################################ +if on_native_windows(): + _mysep = "\\" +else: + _mysep = "/" + +def myjoin( *args ): + """join all the args supplied as arguments using _mysep as the + separator. _mysep is a backslash on native windows and a forward + slash everywhere else. + @type args: strings + @param args: path component strings + + @rtype: string + @return: string with _mysep slashes + """ + s = '' + first = True + for a in args: + if first: + first = False + else: + s = s + _mysep + s = s + a + return s + +def strip_quotes(a): + """Conditionally remove leading/trailing quotes from a string + @type a: string + @param a: a string potentially with quotes + + @rtype: string + @return: same string without the leading and trailing quotes + """ + ln = len(a) + if ln >= 2: + strip_quotes = False + if a[0] == '"' and a[-1] == '"': + strip_quotes=True + elif a[0] == "'" and a[-1] == "'": + strip_quotes=True + if strip_quotes: + b = a[1:ln-1] + return b + return a + +def join( *args ): + """join all the args supplied as arguments using a forward slash as + the separator + + @type args: strings + @param args: path component strings + + @rtype: string + @return: string with forward-slashes + """ + s = '' + first = True + for a in args: + ln = len(s) + if first: + first = False + elif ln == 0 or s[-1] != '/': + # if the last character is not a fwd slash already, add a slash + s = s + '/' + a = strip_quotes(a) + s = s + a + return s + + +def flip_slashes(s): + """convert to backslashes to _mysep slashes. _mysep slashes are + defined to be backslashes on native windows and forward slashes + everywhere else. + @type s: string or list of strings + @param s: path name(s) + + @rtype: string or list of strings + @return: string(s) with _mysep slashes + """ + + if on_native_windows(): + return s + if isinstance(s, list): + return list(map(flip_slashes, s)) + t = re.sub(r'\\',_mysep,s,0) # replace all + return t + +def posix_slashes(s): + """convert to posix slashes. Do not flip slashes immediately before spaces + @type s: string or list of strings + @param s: path name(s) + + @rtype: string or list of strings + @return: string(s) with forward slashes + """ + if isinstance(s,list): + return list(map(posix_slashes, s)) + #t = re.sub(r'\\','/',s,0) # replace all + last = len(s)-1 + t=[] + for i,a in enumerate(s): + x=a + if a == '\\': + if i == last: + x = '/' + elif s[i+1] != ' ': + x = '/' + t.append(x) + return ''.join(t) + +def glob(*s): + """If multiple arguments are passed, we run them through mbuild.join() + first. Run the normal glob.glob() on s but make sure all the + slashes are flipped forward afterwards. This is shorthand for + posix_slashes(glob.glob(s)) """ + import glob + if len(s) > 1: + t = join(*s) + else: + t = s[0] + return posix_slashes(glob.glob(t)) + +def cond_add_quotes(s): + """If there are spaces in the input string s, put quotes around the + string and return it... if there are not already quotes in the + string. + + @type s: string + @param s: path name + + @rtype: string + @return: string with quotes, if necessary + """ + if re.search(r'[ ]',s) and not ( re.search(r'["].*["]',s) or + re.search(r"['].*[']",s) ): + return '\"' + s + '\"' + return s + +def escape_string(s): + return cond_add_quotes(s) + +def escape_special_characters(s): + """Add a backslash before characters that have special meanings in + regular expressions. Python does not handle backslashes in regular + expressions or substitution text so they must be escaped before + processing.""" + + special_chars = r'\\' + new_string = '' + for c in s: + if c in special_chars: + new_string += '\\' + new_string += c + return new_string + +############################################################### + +if check_python_version(2,5): + import hashlib + hasher = hashlib.sha1 +else: + import sha + hasher = sha.new + +def hash_list(list_of_strings): + """Compute a sha1 hash of a list of strings and return the hex digest""" + m = hasher() + for l in list_of_strings: + m.update(l.encode(unicode_encoding())) + return m.hexdigest() + + +def hash_file(fn): + if not os.path.exists(fn): + return None + m = hasher() + with open(fn,'rb') as afile: + buf = afile.read() + m.update(buf) + return m.hexdigest() + + + +def write_signatures(fn,d): + """Write a dictionary of d[file]=hash to the specified file""" + # FIXME: binary protocol 2, binary file write DOES NOT WORK ON win32/win64 + f = open(fn,"wb") + apickle.dump(d,f) + f.close() + +def read_signatures(fn): + """Return a dictionary of d[file]=hash from the specified file""" + try: + f = open(fn,"rb") + d = apickle.load(f) + f.close() + return d + except: + return None + + +def hash_string(s): + """Compute a sha1 hash of a string and return the hex digest""" + if check_python_version(2,5): + m = hashlib.sha1() + else: + m = sha.new() + m.update(s) + d = m.hexdigest() + return d + + +def hash_files(list_of_files, fn): + """Hash the files in the list of files and write the hashes to fn""" + d = {} + for f in list_of_files: + d[f] = hash_file(f) + write_signatures(fn,d) + +def file_hashes_are_valid(list_of_files, fn): + """Return true iff the old hashes in the file fn are valid for all + of the specified list of files.""" + if not os.path.exists(fn): + return False + d = read_signatures(fn) + if d == None: + return False + for f in list_of_files: + if os.path.exists(f): + nhash = hash_file(f) + else: + return False + if nhash == None: + return False + if f not in d: + return False + elif d[f] != nhash: + return False; + return True + +############################################################### +# Time functions +def get_time_str(): + """@rtype: string + @returns: current time as string + """ + # include time zone + return time.strftime('%Y-%m-%d %H:%M:%S %Z') + +def get_time(): + """@rtype: float + @returns: current time as float + """ + return time.time() + +def get_elapsed_time(start_time, end_time=None): + """compute the elapsed time in seconds or minutes + @type start_time: float + @param start_time: starting time. + @type end_time: float + @param end_time: ending time. + @rtype: string + """ + if end_time == None: + end_time = get_time() + seconds = end_time - start_time + negative_prefix = '' + if seconds < 0: + negative_prefix = '-' + seconds = -seconds + if seconds < 120: + if int(seconds) == 0: + milli_seconds = seconds * 1000 + timestr = "%d" % int(milli_seconds) + suffix = " msecs" + else: + timestr = "%d" % int(seconds) + suffix = " secs" + else: + minutes = int(seconds/60.0) + remainder_seconds = int(seconds - (minutes*60)) + timestr = "%.d:%02d" % (minutes,remainder_seconds) + suffix = " min:sec" + return "".join([negative_prefix, timestr, suffix]) + +def print_elapsed_time(start_time, end_time=None, prefix=None, current=False): + """print the elapsed time in seconds or minutes. + + @type start_time: float + @param start_time: the starting time + @type end_time: float + @param end_time: the ending time (optional) + @type prefix: string + @param prefix: a string to print at the start of the line (optional) + """ + if end_time == None: + end_time = get_time() + ets = "ELAPSED TIME" + if prefix: + s = "%s %s" % (prefix, ets) + else: + s = ets + + t = get_elapsed_time(start_time, end_time) + if current: + t = t + " / NOW: " + get_time_str() + vmsgb(1,s,t) + + +############################################################### +def _prepare_cmd(cmd): + """Tokenize the cmd string input. Return as list on non-windows + platforms. On windows, it returns the raw command string.""" + + if on_native_windows(): + # the posix=False is required to keep shlex from eating + # backslashed path characters on windows. But + # the nonposix chokes on /Dfoo="xxx yyy" in that it'll + # split '/Dfoo="xxx' and 'yyy"' in to two different args. + # so we cannot use that + #args = shlex.split(cmd,posix=False) + + # using posix mode (default) means that all commands must must + # forward slashes. So that is annoying and we avoid that + #args = shlex.split(cmd) + + # passing the args through works fine. Make sure not to have + # any carriage returns or leading white space in the supplied + # command. + args = cmd + + else: + args = shlex.split(cmd) + return args + +def _cond_open_input_file(directory,input_file_name): + if input_file_name: + if directory and not os.path.isabs(input_file_name): + fn = os.path.join(directory, input_file_name) + else: + fn = input_file_name + input_file_obj = open(fn,"r") + return input_file_obj + return None + +def run_command(cmd, + separate_stderr=False, + shell_executable=None, + directory=None, + osenv=None, + input_file_name=None, + **kwargs): + """ + Run a command string using the subprocess module. + + @type cmd: string + @param cmd: command line to execut with all args. + @type separate_stderr: bool + @param separate_stderr: If True, the return tuple has a list of stderr lines as the 3rd element + @type shell_executable: string + @param shell_executable: the shell executable + @type directory: string + @param directory: a directory to change to before running the command. + @type osenv: dictionary + @param osenv: dict of environment vars to be passed to the new process + @type input_file_name: string + @param input_file_name: file name to read stdin from. Default none + + @rtype: tuple + @return: (return code, list of stdout lines, list of lines of stderr) + """ + use_shell = False + if verbose(99): + msgb("RUN COMMAND", cmd) + msgb("RUN COMMAND repr", repr(cmd)) + stdout = None + stderr = None + cmd_args = _prepare_cmd(cmd) + try: + input_file_obj = _cond_open_input_file(directory, input_file_name) + + if separate_stderr: + sub = subprocess.Popen(cmd_args, + shell=use_shell, + executable=shell_executable, + stdin = input_file_obj, + stdout = subprocess.PIPE, + stderr = subprocess.PIPE, + cwd=directory, + env=osenv, + universal_newlines=True, + **kwargs) + (stdout, stderr ) = sub.communicate() + if not isinstance(stderr,list): + stderr = stderr.splitlines(True) + if not isinstance(stdout,list): + stdout = stdout.splitlines(True) + stdout = ensure_string(stdout) + stderr = ensure_string(stderr) + return (sub.returncode, stdout, stderr) + else: + sub = subprocess.Popen(cmd_args, + shell=use_shell, + executable=shell_executable, + stdin = input_file_obj, + stdout = subprocess.PIPE, + stderr = subprocess.STDOUT, + cwd=directory, + env=osenv, + universal_newlines=True, + **kwargs) + stdout = sub.stdout.readlines() + sub.wait() + if not isinstance(stdout,list): + stdout = stdout.splitlines(True) + stdout = ensure_string(stdout) + return (sub.returncode, stdout, None) + except OSError as e: + s= [u"Execution failed for: %s\n" % (cmd) ] + uappend(s,"Result is %s\n" % (str(e))) + # put the error message in stderr if there is a separate + # stderr, otherwise put it in stdout. + if separate_stderr: + if stderr == None: + stderr = [] + elif not isinstance(stderr,list): + stderr = stderr.splitlines(True) + if stdout == None: + stdout = [] + elif not isinstance(stdout,list): + stdout = stdout.splitlines(True) + stderr = ensure_string(stderr) + stdout = ensure_string(stdout) + if separate_stderr: + stderr.extend(s) + else: + stdout.extend(s) + return (1, stdout, stderr) + + +def run_command_unbufferred(cmd, + prefix_line=None, + shell_executable=None, + directory=None, + osenv=None, + input_file_name=None, + **kwargs): + """ + Run a command string using the subprocess module. + + @type cmd: string + @param cmd: command line to execut with all args. + @type prefix_line: string + @param prefix_line: a string to prefix each output line. Default None + @type shell_executable: string + @param shell_executable: NOT USED BY THIS FUNCTION + @type directory: string + @param directory: a directory to change to before running the command. + @type osenv: dictionary + @param osenv: dict of environment vars to be passed to the new process + @type input_file_name: string + @param input_file_name: file name to read stdin from. Default none + + @rtype: tuple + @return: (return code, list of stdout lines, empty list) + + """ + use_shell = False + if verbose(99): + msgb("RUN COMMAND", cmd) + msgb("RUN COMMAND repr", repr(cmd)) + lines = [] + cmd_args = _prepare_cmd(cmd) + try: + input_file_obj = _cond_open_input_file(directory, input_file_name) + sub = subprocess.Popen(cmd_args, + shell=use_shell, + executable=shell_executable, + stdin = input_file_obj, + stdout = subprocess.PIPE, + stderr = subprocess.STDOUT, + env=osenv, + cwd=directory, + universal_newlines=True, + **kwargs) + while 1: + # FIXME: 2008-12-05 bad for password prompts without newlines. + line = sub.stdout.readline() + if line == '': + break + line = line.rstrip() + if prefix_line: + msgn(prefix_line) + msg(line) + lines.append(ensure_string(line) + u"\n") + + sub.wait() + return (sub.returncode, lines, []) + except OSError as e: + uappend(lines, u"Execution failed for: %s\n" % (cmd)) + uappend(lines, u"Result is %s\n" % (str(e))) + return (1, lines, []) + +def run_command_output_file(cmd, + output_file_name, + shell_executable=None, + directory=None, + osenv=None, + input_file_name=None, + **kwargs): + """ + Run a command string using the subprocess module. + + @type cmd: string + @param cmd: command line to execut with all args. + @type output_file_name: string + @param output_file_name: output file name + @type shell_executable: string + @param shell_executable: the shell executable + @type directory: string + @param directory: a directory to change to before running the command. + @type osenv: dictionary + @param osenv: dict of environment vars to be passed to the new process + @type input_file_name: string + @param input_file_name: file name to read stdin from. Default none + + @rtype: tuple + @return: (return code, list of stdout lines) + """ + use_shell = False + if verbose(99): + msgb("RUN COMMAND", cmd) + lines = [] + cmd_args = _prepare_cmd(cmd) + try: + output = io.open(output_file_name,"wt",encoding=unicode_encoding()) + input_file_obj = _cond_open_input_file(directory, input_file_name) + sub = subprocess.Popen(cmd_args, + shell=use_shell, + executable=shell_executable, + stdin = input_file_obj, + stdout = subprocess.PIPE, + stderr = subprocess.STDOUT, + env=osenv, + cwd=directory, + universal_newlines=True, + **kwargs) + + (stdout, stderr) = sub.communicate() + if not isinstance(stdout,list): + stdout = stdout.splitlines(True) + stdout = ensure_string(stdout) + for line in stdout: + output.write(line) + lines.append(line) + output.close() + return (sub.returncode, lines, []) + except OSError as e: + uappend(lines,"Execution failed for: %s\n" % (cmd)) + uappend(lines,"Result is %s\n" % (str(e))) + return (1, lines, []) + except: + print("Unxpected error:", sys.exc_info()[0]) + raise + +def run_cmd_io(cmd, fn_i, fn_o,shell_executable=None, directory=None): + """ + Run a command string using the subprocess module. Read standard + input from fn_i and write stdout/stderr to fn_o. + + @type cmd: string + @param cmd: command line to execut with all args. + @type fn_i: string + @param fn_i: input file name + @type fn_o: string + @param fn_o: output file name + @type shell_executable: string + @param shell_executable: the shell executable + @type directory: string + @param directory: a directory to change to before running the command. + + @rtype: integer + @return: return code + """ + use_shell = False + cmd_args = _prepare_cmd(cmd) + try: + fin = io.open(fn_i, 'rt', encoding=unicode_encoding()) + fout = io.open(fn_o, 'wt', encoding=unicode_encoding()) + sub = subprocess.Popen(cmd_args, + shell=use_shell, + executable=shell_executable, + stdin=fin, + stdout=fout, + stderr=subprocess.STDOUT, + universal_newlines=True, + cwd=directory) + retval = sub.wait() + fin.close() + fout.close() + return retval + except OSError as e: + die(u"Execution failed for cmd %s\nResult is %s\n" % (cmd,str(e))) + +def find_dir(d): + """Look upwards for a particular filesystem directory d as a + subdirectory of one of the ancestors. Return None on failure""" + dir = os.getcwd() + last = '' + while dir != last: + target_dir = os.path.join(dir,d) + if os.path.exists(target_dir): + return target_dir + last = dir + (dir,tail) = os.path.split(dir) + return None + +def peel_dir(s,n): + """Remove n trailing path components from s by calling + os.path.dirname()""" + t = s + for i in range(0,n): + t = os.path.dirname(t) + return t + +def get_gcc_version(gcc): + """Return the compressed version number of gcc""" + cmd = gcc + " -dumpversion" + try: + (retcode, stdout, stderr) = run_command(cmd) + if retcode == 0: + version = stdout[0] + return version.strip() + except: + return 'unknown' + +def get_clang_version(full_path): + cmd = full_path + " -dM -E - " + try: + (retcode, stdout, stderr) = run_command(cmd, + input_file_name="/dev/null") + if retcode == 0: + major=minor=patchlevel='x' + for line in stdout: + line = line.strip() + chunks = line.split() + if len(chunks) == 3: + if chunks[1] == '__clang_major__': + major = chunks[2] + elif chunks[1] == '__clang_minor__': + minor = chunks[2] + elif chunks[1] == '__clang_patchlevel__': + patchlevel = chunks[2] + version = "{}.{}.{}".format(major,minor,patchlevel) + return version + except: + return 'unknown' + +# unify names for clang/gcc version checkers +def compute_clang_version(full_path): + return get_clang_version(full_path) + +def compute_gcc_version(full_path): + return get_gcc_version(full_path) + +def gcc_version_test(major,minor,rev,gstr): + """Return True if the specified gcc version string (gstr) is at or + after the specified major,minor,revision args""" + + n = gstr.split('.') + if len(n) not in [2,3]: + die("Cannot compute gcc version from input string: [%s]" % (gstr)) + ga = int(n[0]) + gb = int(n[1]) + if len(n) == 2: + gc = 0 + else: + gc = int(n[2]) + + if ga > major: + return True + if ga == major and gb > minor: + return True + if ga == major and gb == minor and gc >= rev: + return True + return False + +import threading +# requires Python2.6 or later +class _timed_command_t(threading.Thread): + """ + Internal function to mbuild util.py. Do not call directly. + + Examples of use + env = os.environ + env['FOOBAR'] = 'hi' + # the command a.out prints out the getenv("FOOBAR") value + rc = _timed_command_t(["./a.out", "5"], seconds=4, env=env) + rc.timed_run() + + rc = _timed_command_t(["/bin/sleep", "5"], seconds=4) + rc.timed_run() + """ + + def __init__(self, cmd, + shell_executable=None, + directory=None, + osenv=None, + seconds=0, + input_file_name=None, + **kwargs): + """The kwargs are for the other parameters to Popen""" + threading.Thread.__init__(self) + self.cmd = cmd + self.kwargs = kwargs + self.seconds = seconds + self.timed_out = False + self.sub = None + self.osenv= osenv + self.input_file_name = input_file_name + self.directory = directory + self.shell_executable = shell_executable + self.exception_type = None + self.exception_object = None + self.exception_trace = None + self.exitcode = 0, + self.output = "", + self.stderr = "", + + def run(self): # executed by calling start() + cmd = self.cmd + #run a python command + if _is_python_cmd(cmd): + kwargs = self.kwargs + xenv = kwargs.get('xenv') + args_lst = kwargs.get('args_lst') + if args_lst == None: + args_lst = [] + if xenv == None: + (self.exitcode,self.output,self.stderr) = cmd(*args_lst) + else: + (self.exitcode,self.output,self.stderr) = cmd(xenv, *args_lst) + return + + #run an executable + use_shell = False + cmd_args = _prepare_cmd(cmd) + input_file_obj = _cond_open_input_file(self.directory, + self.input_file_name) + try: + self.sub = subprocess.Popen(cmd_args, + shell=use_shell, + executable=self.shell_executable, + cwd=self.directory, + env=self.osenv, + stdin = input_file_obj, + universal_newlines=True, + **self.kwargs) + except: + (self.exception_type, + self.exception_object, + self.exception_trace) = sys.exc_info() + else: + self.sub.wait() + + def timed_run(self): + """Returns False if the process times out. Also sets + self.timed_out to True.""" + + self.timed_out=False + self.start() # calls run() + if self.seconds: + self.join(self.seconds) + else: + self.join() + + if self.is_alive(): + try: + if self.sub: + if on_windows(): + # On Windows terminate() does not always kill + # the process So we need specific handling for + # Windows here. + kill_cmd = "taskkill /F /T /PID %i" % (self.sub.pid) + cmd_args = _prepare_cmd(kill_cmd) + subprocess.Popen(cmd_args, shell=True) + else: + self.sub.kill() + except: + pass + + self.join() + self.timed_out=True + return False + return True + + +def _is_python_cmd(cmd): + return isinstance(cmd,types.FunctionType) + + +def run_command_timed( cmd, + shell_executable=None, + directory=None, + osenv=None, + seconds=0, + input_file_name=None, + **kwargs ): + """Run a timed command. kwargs are keyword args for subprocess.Popen. + + @type cmd: string or python function + @param cmd: command to run + + @type shell_executable: string + @param shell_executable: the shell executable + + @type directory: string + @param directory: the directory to run the command in + + @type osenv: dictionary + @param osenv: dict of environment vars to be passed to the new process + + @type seconds: number + @param seconds: maximum execution time in seconds + + @type input_file_name: string + @param input_file_name: input filename when redirecting stdin. + + @type kwargs: keyword args + @param kwargs: keyword args for subprocess.Popen + + @rtype: tuple + return: (return code, list of stdout+stderr lines) + """ + + def _get_exit_code(tc): + exit_code = 399 + if tc.sub: + # if tc.sub does not have a returncode, then something went + # very wrong, usually an exception running the subprocess. + if hasattr(tc.sub, 'returncode'): + exit_code = tc.sub.returncode + return exit_code + + # we use a temporary file to hold the output because killing the + # process disrupts the normal output collection mechanism. + fo = tempfile.SpooledTemporaryFile() # FIXME: PY3 mode='w+'? + fe = tempfile.SpooledTemporaryFile() # FIXME: PY3 mode='w+'? + tc = _timed_command_t(cmd, + shell_executable, + directory, + osenv, + seconds, + input_file_name, + stdout=fo, + stderr=fe, + **kwargs) + + tc.timed_run() + + if _is_python_cmd(tc.cmd): + exit_code = tc.exitcode + output = tc.output + stderr = tc.stderr + else: + fo.seek(0) + output = fo.readlines() + fo.close() + output = ensure_string(output) + + fe.seek(0) + stderr = fe.readlines() + fe.close() + stderr = ensure_string(stderr) + exit_code = _get_exit_code(tc) + + nl = u'\n' + if tc.timed_out: + stderr.extend([ nl, + u'COMMAND TIMEOUT'+nl, + u'KILLING PROCCESS'+nl]) + if tc.exception_type: + stderr.extend([ nl, + u'COMMAND ENCOUNTERD AN EXCEPTION' + nl]) + stderr.extend(traceback.format_exception(tc.exception_type, + tc.exception_object, + tc.exception_trace)) + + return (exit_code, output, stderr) + + +def make_list_of_str(lst): + return [ str(x) for x in lst] +def open_readlines(fn, mode='rt',enc=None): + if enc==None: + enc = unicode_encoding() + return io.open(f,mode,encoding=enc).readlines() diff --git a/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/work_queue.py b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/work_queue.py new file mode 100644 index 0000000..a9c2b2d --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/mbuild/mbuild/work_queue.py @@ -0,0 +1,1020 @@ +# -*- python -*- +# Mark Charney +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL + +"""Command objects and parallel work queue""" +from __future__ import print_function +import os +import sys +import types +is_py2 = sys.version[0] == '2' +if is_py2: + import Queue as queue +else: + import queue as queue +from threading import Thread +from collections import deque + +from .base import * +from .util import * +from .dag import * + + +############################################################################ +class dir_cmd_t(object): + """For holding a directory and a command. When you call + execute(), it changes to the directory an executes the command""" + + def __init__(self, dir, command, output_file=None): + self.dir= dir + self.command= command + self.output_file = output_file + def __str__(self): + return "DIR: %s\nCOMMAND: %s" % (self.dir, self.command) + + def execute(self,args=None, env=None): + """Change to the specified directory and execute the command, + unbufferred""" + orig = os.getcwd() + try: + msgb("CHDIR TO", self.dir) + os.chdir(self.dir) + except: + return (-1, ["no such dir: " + self.dir]) + msgb("EXECUTING", self.command) + if self.output_file: + (retcode, out, err) = \ + run_command_output_file(self.command, self.output_file) + msgb("WROTE", self.output_file) + else: + (retcode, out, err) = run_command_unbufferred(self.command) + os.chdir(orig) + if not err: + err = [] + if not out: + out = [] + if err: + return (retcode, out+err) + else: + return (retcode, out) + +class command_t(object): + """The primary data structure used to track jobs in this script. It + is created when you add L{plan_t} objects to the DAG + L{dag_t}.""" + + _ids = 0 + + def __init__(self, + command=None, + args=None, + xenv=None, + unbufferred=False, + output_file_name=None, + shell_executable=None, + directory=None, + name=None, + show_output=True, + osenv=None, + seconds=0, + input_file_name=None): + """ + This is the unit of work for the L{work_queue_t}. These are + typically created by the L{dag_t} but they can also be created + by hand and added to the L{work_queue_t} to execute arbitrary + commands. + + @type command: string or python function, or a list of both + @param command: command line string to execute or a python function + + @type args: anything + @param args: (optional) typically a list of arguments for the python function. + + @type xenv: L{env_t} + @param xenv: (optional) environment for used by the python + function. Passed as the second argument to the python function. + + @type osenv: dictionary + @param osenv: (optional) the environment that will be set in the new subprocess. + + @type unbufferred: L{bool} + @param unbufferred: (optional) true if the output should be unbufferred. + + @type output_file_name: string + @param output_file_name: (optional) file name for stderr/stdout + + @type show_output: L{bool} + @param show_output: (optional) show output, default True + + @type input_file_name: string + @param input_file_name: (optional) file name for stdin + + """ + self.id = command_t._ids + command_t._ids += 1 + # store the command as a list + if isinstance(command,list): + self.command = command + else: + self.command = [ command ] + self.name = name + self.shell_executable = shell_executable + self.args = args + self.xenv = xenv + self.osenv = osenv + self.exit_status = 0 + self.output = [] + self.stderr = [] + self.unbufferred = unbufferred + self.input_file_name = input_file_name + self.output_file_name = output_file_name + self.start_time = 0 + self.end_time = 0 + self.directory = directory + self.show_output = show_output + self.input_file_name = input_file_name + + # Has this command be submitted to the work queue? + self.submitted = False + + # executed is set to True when this command tries to execute. + self.executed = False + + # all prerequisite commands are ready + self.ready = False + + # completed is set to True when this command exits successfully. + self.completed = False + + # things that depend on this command completing sucessfully + self.after_me = [] + + # things that must complete before this command can run + self.before_me = [] + + # from the file DAG. A list of inputs upon which this command depends + self.inputs = [] + # from the file DAG. A list of things generated by this command + self.targets = [] + + # used for special signals to the worker threads to tell them to + # shut down. + self.terminator = False + self.timeout = seconds + + def failed(self): + """ + Return the exit status. + @rtype: bool + @return: True if the command failed (exit status != 0) + """ + if self.exit_status != 0: + return True + return False + + def _complete(self): + self.completed = True + + def _ready(self): + """Return true if all things that must execute before this node + have completed and false otherwise. Updates self.ready.""" + if self.ready: + return True + + for n in self.before_me: + if not n.completed: + return False + + self.ready=True + return True + + def is_python_command(self, i=0): + """Return true if the command list element is a python function + @rtype: bool + """ + if isinstance(self.command[i],types.FunctionType): + return True + return False + + def is_dir_cmd(self, i=0): + """Return true if the command list element is a python dir_cmd_t object + @rtype: bool + """ + if isinstance(self.command[i],dir_cmd_t): + return True + return False + + def has_python_subcommand(self): + """Return true if the command list has a python function + @rtype: bool + """ + for c in self.command: + if isinstance(c,types.FunctionType): + return True + return False + + def is_command_line(self, i=0): + """Return true if the command list element is normal string command + line. + @rtype: bool + """ + if not isinstance(self.command[i],types.FunctionType) and \ + not isinstance(self.command[i],dir_cmd_t): + return True + return False + + def dagkey(self): + s = [] + for i in self.command: + if not isinstance(i,types.FunctionType): + s.append(i) + t = "MBUILD_COMMAND_KEY " + (" - ".join(s)) + return t + + def hash(self): + s = [] + for i in self.command: + if not isinstance(i,types.FunctionType): + s.append(i) + t = " - ".join(s) + h = hash_string(t.encode(unicode_encoding())) + return h + + def add_before_me(self,n): + """Make the current command execute after command n + @type n: L{command_t} + @param n: another (earlier) command + """ + if isinstance(n,list): + for x in n: + self.before_me.append(x) + x.after_me.append(self) + else: + self.before_me.append(n) + n.after_me.append(self) + + def add_after_me(self,n): + """Make the current command execute before command n. + @type n: L{command_t} + @param n: another (later) command + """ + if isinstance(n, list): + for x in n: + self.after_me.append(x) + x.before_me.append(self) + else: + self.after_me.append(n) + n.before_me.append(self) + + def _check_afters(self): + """Return a list of after nodes that are as-yet not submitted + but now ready""" + ready = [] + for x in self.after_me: + if not x.submitted and x._ready(): + ready.append(x) + return ready + + def elapsed_time(self): + """Return the elapsed time as an number of seconds""" + if self.end_time == None: + self.end_time = get_time() + return self.end_time - self.start_time + + def elapsed(self): + """Return the elapsed time. + @rtype: string + @returns: the elapsed wall clock time of execution. + """ + if self.end_time == None: + self.end_time = get_time() + elapsed = get_elapsed_time(self.start_time, self.end_time) + return elapsed + + def dump_cmd(self): + return self._pretty_cmd_str() + + def stderr_exists(self): + if self.stderr and len(self.stderr) > 0: + if len(self.stderr) == 1 and len(self.stderr[0]) == 0: + return False + return True + return False + + def stdout_exists(self): + if self.output and len(self.output) > 0: + if len(self.output) == 1 and len(self.output[0]) == 0: + return False + return True + return False + + def _pretty_cmd_str(self): + s = [] + for cmd in self.command: + if isinstance(cmd,types.FunctionType): + s.append("PYTHON FN: " + cmd.__name__) + elif is_stringish(cmd): + s.append(cmd) + else: + s.append(str(cmd)) + return " ;;;; ".join(s) + + + def dump(self, tab_output=False, show_output=True): + s = [] + nl = '\n' + if verbose(2): + pass + elif self.failed(): + pass + elif self.targets: + s.append(bracket('TARGET ', " ".join(self.targets))) + s.append(nl) + if self.name: + s.append(bracket('NAME ', self.name)) + s.append(nl) + if self.command: + s.append(bracket('COMMAND ', self._pretty_cmd_str())) + s.append(nl) + else: + s.append( bracket('COMMAND ', 'none') ) + s.append(nl) + if self.args: + args_string = str(self.args) + print_limit = 400 + if len(args_string) > print_limit: + args_string = args_string[:print_limit] + s.append(bracket('ARGS ', args_string)) + s.append(nl) + if self.xenv: + s.append(bracket('ENV ', 'some env')) + s.append(nl) + #if self.submitted: + # s.append(bracket('START_TIME ', self.start_time)) + # s.append(nl) + if self.input_file_name: + s.append(bracket('INPUT_FILE ', self.input_file_name)) + s.append(nl) + + if self.completed or self.failed(): + if self.exit_status != 0: + s.append(bracket('EXIT_STATUS ', str(self.exit_status))) + s.append(nl) + if self.elapsed_time() > 1: + s.append(bracket('ELAPSED_TIME', self.elapsed())) + s.append(nl) + if self.input_file_name: + s.append(bracket('INPUT FILE', self.input_file_name)) + s.append(nl) + if self.output_file_name: + s.append(bracket('OUTPUT FILE', self.output_file_name)) + s.append(nl) + + # stdout and stderr frequently have unicode + s = ensure_string(s) + if self.unbufferred == False and self.output_file_name==None: + if show_output and self.show_output and self.stdout_exists(): + uappend(s,bracket('OUTPUT')) + uappend(s,nl) + for line in self.output: + if tab_output: + uappend(s,'\t') + uappend(s,line) + if show_output and self.show_output and self.stderr_exists(): + uappend(s,bracket('STDERR')) + uappend(s,nl) + + for line in self.stderr: + if tab_output: + uappend(s,'\t') + uappend(s,line) + return u"".join(s) + + def __str__(self): + return self.dump() + + def _extend_output(self, lines): + if lines: + util_add_to_list(self.output,ensure_string(lines)) + + def _extend_stderr(self, lines): + if lines: + util_add_to_list(self.stderr,ensure_string(lines)) + + def _extend_output_stderr(self, output, stderr): + self._extend_output(output) + self._extend_stderr(stderr) + + + def execute(self): + """Execute the command whether it be a python function or a + command string. This is executed by worker threads but is made + available here for potential debugging. Record execution exit/return + status and output. + + Sets the exit_status, output and stderr error fields of the + command object. + """ + self.executed = True + self.start_time = get_time() + self.output = [] + self.stderr = [] + for cmd in self.command: + try: + if isinstance(cmd, dir_cmd_t): + # execute dir_cmd_t objects + (self.exit_status, output) = cmd.execute( self.args, self.xenv ) + self._extend_output(output) + + elif isinstance(cmd,types.FunctionType): + # execute python functions + (self.exit_status, output) = cmd( self.args, self.xenv ) + self._extend_output(output) + + elif is_stringish(cmd): + # execute command strings + if self.output_file_name: + (self.exit_status, output, stderr) = \ + run_command_output_file(cmd, + self.output_file_name, + shell_executable=self.shell_executable, + directory=self.directory, + osenv=self.osenv, + input_file_name=self.input_file_name) + self._extend_output_stderr(output,stderr) + + elif self.unbufferred: + (self.exit_status, output, stderr) = \ + run_command_unbufferred(cmd, + shell_executable= + self.shell_executable, + directory = self.directory, + osenv = self.osenv, + input_file_name=self.input_file_name) + self._extend_output_stderr(output, stderr) + else: + # execute timed_cmd_t objects + (self.exit_status, output, stderr) = \ + run_command_timed(cmd, + shell_executable=self.shell_executable, + directory = self.directory, + osenv = self.osenv, + seconds=self.timeout, + input_file_name = self.input_file_name) + self._extend_output_stderr(output, stderr) + + else: + self.exit_status = 1 + self._extend_output("Unhandled command object: " + self.dump()) + + # stop if something failed + if self.exit_status != 0: + break; + except Exception as e: + self.exit_status = 1 + self._extend_stderr(u"Execution error for: %s\n%s" % (ustr(e), self.dump())) + break + + self.end_time = get_time() + + + +def _worker_one_task(incoming,outgoing): + """A thread. Takes stuff from the incoming queue and puts stuff on + the outgoing queue. calls execute for each command it takes off the + in queue. Return False when we receive a terminator command""" + #msgb("WORKER WAITING") + item = incoming.get() + #msgb("WORKER GOT A TASK") + if item.terminator: + outgoing.put(item) + return False + item.execute() + incoming.task_done() + outgoing.put(item) + return True + +def _worker(incoming,outgoing): + """A thread. Takes stuff from the incoming queue and puts stuff on + the outgoing queue. calls execute for each command it takes off the + in queue. Return when we get a terminator command""" + keep_going = True + while keep_going: + keep_going = _worker_one_task(incoming, outgoing) + +class work_queue_t(object): + """This stores the threads and controls their execution""" + def __init__(self, max_parallelism=4): + """ + @type max_parallelism: int + @param max_parallelism: the number of worker threads to start + """ + max_parallelism = int(max_parallelism) + if max_parallelism <= 0: + die("Bad value for --jobs option: " + str(max_parallelism)) + self.max_parallelism = max_parallelism + self.use_threads = True + self.threads = [] + + # worker threads can add stuff to the new_queue so we + # use an MT-safe queue. + self.new_queue = queue.Queue(0) + self.out_queue = queue.Queue(0) + self.back_queue = queue.Queue(0) + self.pending_commands = deque() + + self.message_delay = 10 + self.min_message_delay = 10 + self.message_delay_delta = 10 + + self.job_num = 0 + self.pending = 0 + self._clean_slate() + + if self.use_threads: + if len(self.threads) == 0: + self._start_daemons() + + def _empty_queue(self, q): + while not q.empty(): + item = q.get_nowait() + + def _cleanup(self): + """After a failed build we want to clean up our any in-progress state + so we can re-use the work queue object""" + + # the new_queue, job_num and pending get updated by add() before we build. + # so we must clean them up after every build. Also good hygene to clean out + # the task queues that we use to talk to the workers. + self.pending_commands = deque() + self._empty_queue(self.new_queue) + self._empty_queue(self.out_queue) + self._empty_queue(self.back_queue) + self.job_num = 0 + self.pending = 0 + + def _clean_slate(self): + self.running_commands = [] + self.all_commands = [] + self.running = 0 + self.sent = 0 + self.finished = 0 + self.errors = 0 + self.dag = None + + # for message limiting in _status() + self.last_time = 0 + self.last_pending = 0 + self.last_finished = 0 + self.last_running = 0 + + self.start_time = get_time() + self.end_time = None + + # we set dying to to True when we are trying to stop because of an error + self.dying = False + + self._empty_queue(self.out_queue) + self._empty_queue(self.back_queue) + + + def clear_commands(self): + """Remove any previously remembered commands""" + self.all_commands = [] + def commands(self): + """Return list of all commands involved in last build""" + return self.all_commands + + def elapsed_time(self): + """Return the elapsed time as an a number""" + if self.end_time == None: + self.end_time = get_time() + return self.end_time - self.start_time + + def elapsed(self): + """Return the elapsed time as a pretty string + @rtype: string + @returns: the elapsed wall clock time of execution. + """ + if self.end_time == None: + self.end_time = get_time() + elapsed = get_elapsed_time(self.start_time, self.end_time) + return elapsed + + def _terminate(self): + """Shut everything down. Kill the worker threads if any were + being used. This is called when the work_queue_t is garbage + collected, but can be called directly.""" + self.dying = True + if self.use_threads: + self._stop_daemons() + self._join_threads() + + def _start_daemons(self): + """Start up a bunch of daemon worker threads to process jobs from + the queue.""" + for i in range(self.max_parallelism): + t = Thread(target=_worker, args=(self.out_queue, self.back_queue)) + t.setDaemon(True) + t.start() + self.threads.append(t) + + def _stop_daemons(self): + """Send terminator objects to all the workers""" + for i in range(self.max_parallelism): + t = command_t() + t.terminator = True + if verbose(4): + msgb("SENT TERMINATOR", str(i)) + self._start_a_job(t) + + def _join_threads(self): + """Use this when not running threads in daemon-mode""" + for t in self.threads: + t.join() + if verbose(4): + msgb("WORKER THREAD TERMINATED") + self.threads = [] + + def _add_one(self,command): + """Add a single command of type L{command_t} to the list + of jobs to run.""" + # FIXME: make this take a string and build a command_t + + if command.completed: + if verbose(5): + msgb("SKIPPING COMPLETED CMD", str(command.command)) + msgb("SKIPPING COMPLETED CMD", str(command.command)) + self.add(command._check_afters()) + return + if command.submitted: + if verbose(5): + msgb("SKIPPING SUBMITTED CMD", str(command.command)) + msgb("SKIPPING SUBMITTED CMD", str(command.command)) + return + command.submitted = True + if verbose(6): + msgb("WQ ADDING", str(command.command)) + self.job_num += 1 + self.new_queue.put( command ) + self.pending += 1 + + def add_sequential(self,command_strings, unbufferred=False): + """ + Add a list of command strings as sequential tasks to the work queue. + + @type command_strings: list of strings + @param command_strings: command strings to add to the L{work_queue_t} + + @rtype: list of L{command_t} + @return: the commands created + """ + last_cmd = None + cmds = [] + for c in command_strings: + co = command_t(c, unbufferred=unbufferred) + cmds.append(co) + self.add(co) + if last_cmd: + last_cmd.add_after_me(co) + last_cmd = co + return cmds + + def add(self,command): + """Add a command or list of commands of type L{command_t} + to the list of jobs to run. + + @type command: L{command_t} + @param command: the command to run + """ + if verbose(5): + msgb("ADD CMD", str(type(command))) + + if command: + if isinstance(command,list): + for c in command: + if verbose(5): + msgb("ADD CMD", str(type(c))) + self._add_one(c) + else: + self._add_one(command) + + def _done(self): + if self.running > 0: + return False + if not self.dying and self.pending > 0: + return False + return True + + def _status(self): + if self.show_progress or verbose(2): + s = ( '[STATUS] RUNNING: %d PENDING: %d COMPLETED: %d ' + + 'ERRORS: %d ELAPSED: %s %s' ) + s = ( 'R: %d P: %d C: %d E: %d / %s %s' ) + cur_time = get_time() + + changed = False + if (self.running != self.last_running or + self.pending != self.last_pending or + self.finished != self.last_finished): + changed = True + + if (changed or + # have we waited sufficiently long? + cur_time >= self.last_time + self.message_delay): + + # speed back up when anything finishes + if self.finished != self.last_finished: + self.message_delay = self.min_message_delay + elif self.last_time != 0: + # only printing because of timeout delay, so + # we increase the time a little bit. + self.message_delay += self.min_message_delay + + # store the other limiters for next time + self.last_time = cur_time + self.last_pending = self.pending + self.last_finished = self.finished + self.last_running = self.running + + vmsg(1, s % (self.running, + self.pending, + self.finished, + self.errors, + get_elapsed_time(self.start_time, get_time()), + self._command_names())) + + def _start_more_jobs(self): + """If there are jobs to start and we didn't hit our parallelism + limit, start more jobs""" + + # copy from new_queue to pending_commands to avoid data + # race on iterating over pending commands. + started = False + while not self.new_queue.empty(): + self.pending_commands.append( self.new_queue.get() ) + + ready = deque() + for cmd in self.pending_commands: + if cmd._ready(): + ready.append(cmd) + + while self.running < self.max_parallelism and ready: + cmd = ready.popleft() + # FIXME: small concern that this could be slow + self.pending_commands.remove(cmd) + if verbose(3): + msgb("LAUNCHING", cmd.dump_cmd()) + self._start_a_job(cmd) + self.pending -= 1 + started = True + return started + + def _start_a_job(self,cmd): + """Private function to kick off a command""" + self.out_queue.put(cmd) + self.running_commands.append(cmd) + if not cmd.terminator: + self.all_commands.append(cmd) + self.sent += 1 + self.running += 1 + + def _command_names(self): + s = [] + anonymous_jobs = 0 + for r in self.running_commands: + if hasattr(r,'name') and r.name: + s.append(r.name) + else: + anonymous_jobs += 1 + if s: + if anonymous_jobs: + s.append('%d-anonymous' % (anonymous_jobs)) + return '[' + ' '.join(s) + ']' + else: + return '' + + def _wait_for_jobs(self): + """Return one command object when it finishes, or None on timeout (or + other non-keyboard-interrupt exceptions).""" + if self.running > 0: + try: + cmd = self.back_queue.get(block=True, timeout=self.join_timeout) + self.running -= 1 + self.finished += 1 + self.running_commands.remove(cmd) + self.back_queue.task_done() + return cmd + except queue.Empty: + return None + except KeyboardInterrupt: + msgb('INTERRUPT') + self._terminate() + self.dying = True + sys.exit(1) + return None # NOT REACHED + except: + return None + return None + + def build(self, + dag=None, + targets=None, + die_on_errors=True, + show_output=True, + error_limit=0, + show_progress=False, + show_errors_only=False, + join_timeout=10.0): + """ + This makes the work queue start building stuff. If no targets + are specified then all the targets are considered and built if + necessary. All commands that get run or generated are stored in + the all_commands attribute. That attribute gets re-initialized + on each call to build. + + @type dag: L{dag_t} + @param dag: the dependence tree object + + @type targets: list + @param targets: specific targets to build + + @type die_on_errors: bool + @param die_on_errors: keep going or die on errors + + @type show_output: bool + @param show_output: show stdout/stderr (or just buffer it in + memory for later processing). Setting this to False is good for + avoiding voluminous screen output. The default is True. + + @type show_progress: bool + @param show_progress: show the running/pending/completed/errors msgs + + @type show_errors_only: bool + @param show_errors_only: normally print the commands as they complete. + If True, only show the commands that fail. + + @type join_timeout: float + @param join_timeout: how long to wait for thread to terminate. default 10s + """ + self._clean_slate() + + self.show_progress = show_progress + self.join_timeout = join_timeout + self.errors = 0 + self.show_errors_only = show_errors_only + self.message_delay = self.min_message_delay + self.last_time = 0 + self.clear_commands() + self.dag = dag + if self.dag: + for x in self.dag._leaves_with_changes(targets): + self.add(x.creator) + okay = self._build_blind(die_on_errors, show_output, error_limit) + if okay and self.dag: + did_not_build = self.dag.check_for_skipped() + if len(did_not_build) > 0: + # some stuff did not build, force an error status return + msgb("ERROR: DID NOT BUILD SOME STUFF", "\n\t".join(did_not_build)) + if self.dag: + uprint(self.dag.dump()) + self.end_time = get_time() + self._cleanup() + return False + # normal exit path + self.end_time = get_time() + if self.dag: + self.dag.dag_write_signatures() + self._cleanup() + return okay + + def _build_blind(self, die_on_errors=True, show_output=True, error_limit=0): + """Start running the commands that are pending and kick off + dependent jobs as those complete. If die_on_errors is True, the + default, we stop running new jobs after one job returns a nonzero + status. Returns True if no errors""" + if self.use_threads: + return self._build_blind_threads(die_on_errors, + show_output, + error_limit) + else: + return self._build_blind_no_threads(die_on_errors, + show_output, + error_limit) + + def _build_blind_threads(self, + die_on_errors=True, + show_output=True, + error_limit=0): + """Start running the commands that are pending and kick off + dependent jobs as those complete. If die_on_errors is True, the + default, we stop running new jobs after one job returns a nonzero + status. Returns True if no errors""" + okay = True + started = False + while 1: + c = None + if started: + c = self._wait_for_jobs() + if c: + if verbose(4): + msgb("JOB COMPLETED") + if c.failed(): + self.errors += 1 + okay = False + if die_on_errors or (error_limit != 0 and + self.errors > error_limit): + warn("Command execution failed. " + + "Waiting for remaining jobs and exiting.") + self.dying = True + + if not self.dying: + started |= self._start_more_jobs() + self._status() + + if c and not self.dying: + c._complete() + # Command objects can depend on each other + # directly. Enable execution of dependent commands. + if verbose(4): + msgb("ADD CMD-AFTERS") + self.add(c._check_afters()) + # Or we might find new commands from the file DAG. + if self.dag: + for x in self.dag._enable_successors(c): + self.add(x.creator) + if c: + if self.show_errors_only==False or c.failed(): + uprint(c.dump(show_output=show_output)) + elif c.targets: + for x in c.targets: + vmsg(1, u'\tBUILT: {}'.format(x)) + if self._done(): + break; + return okay + + def _build_blind_no_threads(self, die_on_errors=True, + show_output=True, error_limit=0): + """Start running the commands that are pending and kick off + dependent jobs as those complete. If die_on_errors is True, the + default, we stop running new jobs after one job returns a nonzero + status. Returns True if no errors""" + okay = True + while 1: + started = False + if not self.dying: + started = self._start_more_jobs() + if started: + self._status() + + # EXECUTE THE TASK OURSELVES + if self.running > 0: + _worker_one_task(self.out_queue, self.back_queue) + c = self._wait_for_jobs() + if c: + if verbose(4): + msgb("JOB COMPLETED") + if c.failed(): + okay = False + self.errors += 1 + if die_on_errors or (error_limit !=0 and + self.errors > error_limit): + warn("Command execution failed. " + + "Waiting for remaining jobs and exiting.") + self.dying = True + if not self.dying: + c._complete() + # Command objects can depende on each other + # directly. Enable execution of dependent commands. + if verbose(4): + msgb("ADD CMD-AFTERS") + self.add(c._check_afters()) + # Or we might find new commands from the file DAG. + if self.dag: + for x in self.dag._enable_successors(c): + self.add(x.creator) + if self.show_errors_only==False or c.failed(): + uprint(c.dump(show_output=show_output)) + self._status() + if self._done(): + break; + return okay + + + diff --git a/CodeVirtualizer/build/obj/wkit/misc/cdata.txt b/CodeVirtualizer/build/obj/wkit/misc/cdata.txt new file mode 100644 index 0000000..5f0970b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/misc/cdata.txt @@ -0,0 +1,849 @@ +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +I86 : + I86 LAHF +I86FP : + I86 LAHF X87 +I186 : + I186 I86 LAHF +I186FP : + I186 I86 LAHF X87 +I286REAL : + I186 I286REAL I86 LAHF + X87 +I286 : + I186 I286PROTECTED I286REAL I86 + LAHF X87 +I2186FP : + I186 I286PROTECTED I286REAL I86 + LAHF X87 +I386REAL : + I186 I286REAL I86 LAHF + X87 +I386 : + I186 I286PROTECTED I286REAL I386 + I86 LAHF X87 +I386FP : + I186 I286PROTECTED I286REAL I386 + I86 LAHF X87 +I486REAL : + I186 I286REAL I486REAL I86 + LAHF X87 +I486 : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + X87 +PENTIUMREAL : + I186 I286REAL I486REAL I86 + LAHF PENTIUMREAL X87 +PENTIUM : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMREAL X87 +QUARK : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMREAL X87 +PENTIUMMMXREAL : + I186 I286REAL I486REAL I86 + LAHF PENTIUMREAL RDPMC X87 +PENTIUMMMX : + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMMMX PENTIUMREAL RDPMC X87 +ALLREAL : + I186 I286REAL I486REAL I86 + LAHF PENTIUMREAL RDPMC X87 +PENTIUMPRO : + CMOV FAT_NOP FCMOV I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF PENTIUMREAL + PPRO PPRO_UD0_SHORT PREFETCH_NOP RDPMC + X87 +PENTIUM2 : + CMOV FAT_NOP FCMOV FXSAVE + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMMMX PENTIUMREAL PPRO PREFETCH_NOP + RDPMC X87 +PENTIUM3 : + CMOV FAT_NOP FCMOV FXSAVE + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + PENTIUMMMX PENTIUMREAL PPRO PREFETCH_NOP + RDPMC SSE SSEMXCSR SSE_PREFETCH + X87 +PENTIUM4 : + CLFSH CMOV FAT_NOP FCMOV + FXSAVE I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF PAUSE PENTIUMMMX PENTIUMREAL + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + SSE SSE2 SSE2MMX SSEMXCSR + SSE_PREFETCH X87 +P4PRESCOTT : + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + MONITOR PAUSE PENTIUMMMX PENTIUMREAL + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSEMXCSR SSE_PREFETCH X87 +P4PRESCOTT_NOLAHF : + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LONGMODE MONITOR + PAUSE PENTIUMMMX PENTIUMREAL PPRO + PPRO_UD0_LONG PREFETCH_NOP RDPMC SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSEMXCSR SSE_PREFETCH X87 +P4PRESCOTT_VTX : + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + MONITOR PAUSE PENTIUMMMX PENTIUMREAL + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSEMXCSR SSE_PREFETCH VTX + X87 +MEROM : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL PPRO PPRO_UD0_LONG PREFETCH_NOP + RDPMC SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +PENRYN : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL PPRO PPRO_UD0_LONG PREFETCH_NOP + RDPMC SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VTX X87 +PENRYN_E : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL PPRO PPRO_UD0_LONG PREFETCH_NOP + RDPMC SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VTX X87 XSAVE +NEHALEM : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PENTIUMMMX + PENTIUMREAL POPCNT PPRO PPRO_UD0_LONG + PREFETCH_NOP RDPMC RDTSCP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +WESTMERE : + 3DNOW_PREFETCH AES CLFSH CMOV + CMPXCHG16B FAT_NOP FCMOV FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE MONITOR PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCH_NOP RDPMC + RDTSCP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX VTX X87 +BONNELL : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR MOVBE PAUSE + PENTIUMMMX PENTIUMREAL PPRO PPRO_UD0_SHORT + PREFETCH_NOP RDPMC SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +SALTWELL : + 3DNOW_PREFETCH CLFSH CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR MOVBE PAUSE + PENTIUMMMX PENTIUMREAL PPRO PPRO_UD0_SHORT + PREFETCH_NOP RDPMC SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 +SILVERMONT : + 3DNOW_PREFETCH AES CLFSH CMOV + CMPXCHG16B FAT_NOP FCMOV FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE MONITOR MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_SHORT PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDTSCP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX X87 +VIA : + VIA_PADLOCK_AES VIA_PADLOCK_MONTMUL VIA_PADLOCK_RNG VIA_PADLOCK_SHA +AMD_K10 : + 3DNOW 3DNOW_PREFETCH AES AMD + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + LZCNT MONITOR PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDTSCP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSE4A SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX SVM VTX + X87 +AMD_BULLDOZER : + 3DNOW_PREFETCH AES AMD AVX + AVXAES CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA4 + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LWP + LZCNT MONITOR PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDTSCP RDWRFSGS SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSE4A SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX SVM + VTX X87 XOP XSAVE + XSAVEOPT +AMD_PILEDRIVER : + 3DNOW_PREFETCH AES AMD AVX + AVXAES CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FMA4 FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + LWP LZCNT MONITOR PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPMC RDTSCP RDWRFSGS SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSE4A + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + SVM TBM VTX X87 + XOP XSAVE XSAVEOPT +AMD_ZEN : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AVX AVX2 AVX2GATHER AVXAES + BMI2 CLFLUSHOPT CLFSH CLZERO + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE LZCNT MONITOR MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSE4A SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX SVM TBM VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +AMD_ZENPLUS : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AVX AVX2 AVX2GATHER AVXAES + BMI2 CLFLUSHOPT CLFSH CLZERO + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE LZCNT MONITOR MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSE4A SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX SVM TBM VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +AMD_ZEN2 : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AVX AVX2 AVX2GATHER AVXAES + BMI2 CLFLUSHOPT CLFSH CLWB + CLZERO CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FMA FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE LZCNT MCOMMIT + MONITOR MONITORX MOVBE PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPID RDPMC RDPRU RDRAND + RDSEED RDTSCP RDWRFSGS SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSE4A SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX SVM TBM + VTX WBNOINVD X87 XSAVE + XSAVEC XSAVEOPT XSAVES +AMD_FUTURE : + 3DNOW_PREFETCH ADOX_ADCX AES AMD + AMD_INVLPGB AVX AVX2 AVX2GATHER + AVXAES BMI2 CLFLUSHOPT CLFSH + CLWB CLZERO CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LZCNT + MCOMMIT MONITOR MONITORX MOVBE + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPID RDPMC RDPRU + RDRAND RDSEED RDTSCP RDWRFSGS + SHA SMAP SMX SNP + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSE4A + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + SVM TBM VTX WBNOINVD + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +GOLDMONT : + 3DNOW_PREFETCH AES CLFLUSHOPT CLFSH + CMOV CMPXCHG16B FAT_NOP FCMOV + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE MONITOR + MOVBE MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_SHORT PREFETCHW PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SHA SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +GOLDMONT_PLUS : + 3DNOW_PREFETCH AES CLFLUSHOPT CLFSH + CMOV CMPXCHG16B FAT_NOP FCMOV + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE MONITOR + MOVBE MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_SHORT PREFETCHW PREFETCH_NOP PTWRITE + RDPID RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SGX SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX VMFUNC VTX X87 + XSAVE XSAVEC XSAVEOPT XSAVES +TREMONT : + 3DNOW_PREFETCH AES CLFLUSHOPT CLFSH + CLWB CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 GFNI + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR MOVBE MPX + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + POPCNT PPRO PPRO_UD0_SHORT PREFETCHW + PREFETCH_NOP PTWRITE RDPID RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SHA SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +SNOW_RIDGE : + 3DNOW_PREFETCH AES CLDEMOTE CLFLUSHOPT + CLFSH CLWB CMOV CMPXCHG16B + FAT_NOP FCMOV FXSAVE FXSAVE64 + GFNI I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + LAHF LONGMODE MONITOR MOVBE + MOVDIR MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_SHORT PREFETCHW PREFETCH_NOP PTWRITE + RDPID RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX WAITPKG X87 + XSAVE XSAVEC XSAVEOPT XSAVES +SANDYBRIDGE : + 3DNOW_PREFETCH AES AVX AVXAES + CLFSH CMOV CMPXCHG16B FAT_NOP + FCMOV FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 LAHF LONGMODE + MONITOR PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL POPCNT PPRO PPRO_UD0_LONG + PREFETCH_NOP RDPMC RDTSCP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VTX + X87 XSAVE XSAVEOPT +IVYBRIDGE : + 3DNOW_PREFETCH AES AVX AVXAES + CLFSH CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 LAHF + LONGMODE MONITOR PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCH_NOP RDPMC RDRAND + RDTSCP RDWRFSGS SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VTX X87 + XSAVE XSAVEOPT +HASWELL : + 3DNOW_PREFETCH AES AVX AVX2 + AVX2GATHER AVXAES BMI1 BMI2 + CLFSH CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FMA FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCH_NOP RDPMC RDRAND + RDTSCP RDWRFSGS RTM SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEOPT +BROADWELL : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES BMI1 + BMI2 CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 INVPCID LAHF LONGMODE + LZCNT MONITOR MOVBE PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPMC RDRAND RDSEED RDTSCP + RDWRFSGS RTM SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEOPT +SKYLAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES BMI1 + BMI2 CLFLUSHOPT CLFSH CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MPX PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL POPCNT PPRO PPRO_UD0_LONG + PREFETCHW PREFETCH_NOP RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SGX SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +COMET_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES BMI1 + BMI2 CLFLUSHOPT CLFSH CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MPX PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL PKU POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + RTM SGX SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEC + XSAVEOPT XSAVES +SKYLAKE_SERVER : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVXAES BMI1 + BMI2 CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 INVPCID + LAHF LONGMODE LZCNT MONITOR + MOVBE MPX PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPMC RDRAND RDSEED RDTSCP + RDWRFSGS RTM SGX SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX X87 XSAVE + XSAVEC XSAVEOPT XSAVES +CASCADE_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_VNNI_128 AVX512_VNNI_256 + AVX512_VNNI_512 AVXAES BMI1 BMI2 + CLFLUSHOPT CLFSH CLWB CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MPX PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL PKU POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + RTM SGX SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VMFUNC + VTX X87 XSAVE XSAVEC + XSAVEOPT XSAVES +COOPER_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BF16_128 AVX512_BF16_256 + AVX512_BF16_512 AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 + AVXAES BMI1 BMI2 CLFLUSHOPT + CLFSH CLWB CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 INVPCID LAHF LONGMODE + LZCNT MONITOR MOVBE MPX + PAUSE PCLMULQDQ PENTIUMMMX PENTIUMREAL + PKU POPCNT PPRO PPRO_UD0_LONG + PREFETCHW PREFETCH_NOP RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SGX SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +KNL : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512CD_512 AVX512ER_512 + AVX512ER_SCALAR AVX512F_128N AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512PF_512 AVXAES BMI1 + BMI2 CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHWT1 PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VTX X87 XSAVE XSAVEOPT +KNM : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512CD_512 AVX512ER_512 + AVX512ER_SCALAR AVX512F_128N AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512PF_512 AVX512_4FMAPS_512 AVX512_4FMAPS_SCALAR + AVX512_4VNNIW_512 AVX512_VPOPCNTDQ_512 AVXAES BMI1 + BMI2 CLFSH CMOV CMPXCHG16B + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PENTIUMMMX PENTIUMREAL POPCNT PPRO + PPRO_UD0_LONG PREFETCHWT1 PREFETCH_NOP RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VMFUNC VTX X87 XSAVE + XSAVEOPT +CANNONLAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_IFMA_128 AVX512_IFMA_256 + AVX512_IFMA_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVXAES BMI1 BMI2 CLFLUSHOPT + CLFSH CMOV CMPXCHG16B F16C + FAT_NOP FCMOV FMA FXSAVE + FXSAVE64 I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID LAHF LONGMODE LZCNT + MONITOR MOVBE MPX PAUSE + PCLMULQDQ PENTIUMMMX PENTIUMREAL PKU + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS RTM SGX + SHA SMAP SMX SSE + SSE2 SSE2MMX SSE3 SSE3X87 + SSE4 SSE42 SSEMXCSR SSE_PREFETCH + SSSE3 SSSE3MMX VMFUNC VTX + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +ICE_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BITALG_128 AVX512_BITALG_256 + AVX512_BITALG_512 AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 + AVX512_IFMA_128 AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 + AVX512_VAES_256 AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 + AVX512_VBMI2_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VPCLMULQDQ_128 + AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 + AVX512_VPOPCNTDQ_512 AVXAES AVX_GFNI BMI1 + BMI2 CLFLUSHOPT CLFSH CMOV + CMPXCHG16B F16C FAT_NOP FCMOV + FMA FXSAVE FXSAVE64 GFNI + I186 I286PROTECTED I286REAL I386 + I486 I486REAL I86 INVPCID + LAHF LONGMODE LZCNT MONITOR + MOVBE PAUSE PCLMULQDQ PENTIUMMMX + PENTIUMREAL PKU POPCNT PPRO + PPRO_UD0_LONG PREFETCHW PREFETCH_NOP RDPID + RDPMC RDRAND RDSEED RDTSCP + RDWRFSGS RTM SGX SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX VAES VMFUNC VPCLMULQDQ + VTX X87 XSAVE XSAVEC + XSAVEOPT XSAVES +ICE_LAKE_SERVER : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BITALG_128 AVX512_BITALG_256 + AVX512_BITALG_512 AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 + AVX512_IFMA_128 AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 + AVX512_VAES_256 AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 + AVX512_VBMI2_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VPCLMULQDQ_128 + AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 + AVX512_VPOPCNTDQ_512 AVXAES AVX_GFNI BMI1 + BMI2 CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + GFNI I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID LAHF LONGMODE LZCNT + MONITOR MOVBE PAUSE PCLMULQDQ + PCONFIG PENTIUMMMX PENTIUMREAL PKU + POPCNT PPRO PPRO_UD0_LONG PREFETCHW + PREFETCH_NOP RDPID RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SGX SGX_ENCLV SHA SMAP + SMX SSE SSE2 SSE2MMX + SSE3 SSE3X87 SSE4 SSE42 + SSEMXCSR SSE_PREFETCH SSSE3 SSSE3MMX + VAES VMFUNC VPCLMULQDQ VTX + WBNOINVD X87 XSAVE XSAVEC + XSAVEOPT XSAVES +TIGER_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVX512BW_128 AVX512BW_128N + AVX512BW_256 AVX512BW_512 AVX512BW_KOP AVX512CD_128 + AVX512CD_256 AVX512CD_512 AVX512DQ_128 AVX512DQ_128N + AVX512DQ_256 AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR + AVX512F_128 AVX512F_128N AVX512F_256 AVX512F_512 + AVX512F_KOP AVX512F_SCALAR AVX512_BITALG_128 AVX512_BITALG_256 + AVX512_BITALG_512 AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 + AVX512_IFMA_128 AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 + AVX512_VAES_256 AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 + AVX512_VBMI2_512 AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 + AVX512_VNNI_128 AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VP2INTERSECT_128 + AVX512_VP2INTERSECT_256 AVX512_VP2INTERSECT_512 AVX512_VPCLMULQDQ_128 AVX512_VPCLMULQDQ_256 + AVX512_VPCLMULQDQ_512 AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 AVX512_VPOPCNTDQ_512 + AVXAES AVX_GFNI BMI1 BMI2 + CET CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + GFNI I186 I286PROTECTED I286REAL + I386 I486 I486REAL I86 + INVPCID KEYLOCKER KEYLOCKER_WIDE LAHF + LONGMODE LZCNT MONITOR MOVBE + MOVDIR PAUSE PCLMULQDQ PCONFIG + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + RDPID RDPMC RDRAND RDSEED + RDTSCP RDWRFSGS RTM SGX + SGX_ENCLV SHA SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VAES + VMFUNC VPCLMULQDQ VTX WBNOINVD + X87 XSAVE XSAVEC XSAVEOPT + XSAVES +ALDER_LAKE : + 3DNOW_PREFETCH ADOX_ADCX AES AVX + AVX2 AVX2GATHER AVXAES AVX_GFNI + AVX_VNNI BMI1 BMI2 CET + CLDEMOTE CLFLUSHOPT CLFSH CLWB + CMOV CMPXCHG16B F16C FAT_NOP + FCMOV FMA FXSAVE FXSAVE64 + GFNI HRESET I186 I286PROTECTED + I286REAL I386 I486 I486REAL + I86 INVPCID KEYLOCKER KEYLOCKER_WIDE + LAHF LONGMODE LZCNT MONITOR + MOVBE MOVDIR PAUSE PCLMULQDQ + PCONFIG PENTIUMMMX PENTIUMREAL PKU + POPCNT PPRO PPRO_UD0_SHORT PREFETCHW + PREFETCH_NOP PTWRITE RDPID RDPMC + RDRAND RDSEED RDTSCP RDWRFSGS + SERIALIZE SHA SMAP SMX + SSE SSE2 SSE2MMX SSE3 + SSE3X87 SSE4 SSE42 SSEMXCSR + SSE_PREFETCH SSSE3 SSSE3MMX VAES + VMFUNC VPCLMULQDQ VTX WAITPKG + WBNOINVD X87 XSAVE XSAVEC + XSAVEOPT XSAVES +SAPPHIRE_RAPIDS : + 3DNOW_PREFETCH ADOX_ADCX AES AMX_BF16 + AMX_INT8 AMX_TILE AVX AVX2 + AVX2GATHER AVX512BW_128 AVX512BW_128N AVX512BW_256 + AVX512BW_512 AVX512BW_KOP AVX512CD_128 AVX512CD_256 + AVX512CD_512 AVX512DQ_128 AVX512DQ_128N AVX512DQ_256 + AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR AVX512F_128 + AVX512F_128N AVX512F_256 AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512_BF16_128 AVX512_BF16_256 AVX512_BF16_512 + AVX512_BITALG_128 AVX512_BITALG_256 AVX512_BITALG_512 AVX512_FP16_128 + AVX512_FP16_128N AVX512_FP16_256 AVX512_FP16_512 AVX512_FP16_SCALAR + AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 AVX512_IFMA_128 + AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 AVX512_VAES_256 + AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 AVX512_VBMI2_512 + AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 AVX512_VNNI_128 + AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VP2INTERSECT_128 AVX512_VP2INTERSECT_256 + AVX512_VP2INTERSECT_512 AVX512_VPCLMULQDQ_128 AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 + AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 AVX512_VPOPCNTDQ_512 AVXAES + AVX_GFNI AVX_VNNI BMI1 BMI2 + CET CLDEMOTE CLFLUSHOPT CLFSH + CLWB CMOV CMPXCHG16B ENQCMD + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 GFNI I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MOVDIR PAUSE PCLMULQDQ PCONFIG + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + PTWRITE RDPID RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SERIALIZE SGX SGX_ENCLV SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX TDX TSX_LDTRK UINTR + VAES VMFUNC VPCLMULQDQ VTX + WAITPKG WBNOINVD X87 XSAVE + XSAVEC XSAVEOPT XSAVES +FUTURE : + 3DNOW_PREFETCH ADOX_ADCX AES AMX_BF16 + AMX_INT8 AMX_TILE AVX AVX2 + AVX2GATHER AVX512BW_128 AVX512BW_128N AVX512BW_256 + AVX512BW_512 AVX512BW_KOP AVX512CD_128 AVX512CD_256 + AVX512CD_512 AVX512DQ_128 AVX512DQ_128N AVX512DQ_256 + AVX512DQ_512 AVX512DQ_KOP AVX512DQ_SCALAR AVX512F_128 + AVX512F_128N AVX512F_256 AVX512F_512 AVX512F_KOP + AVX512F_SCALAR AVX512_BF16_128 AVX512_BF16_256 AVX512_BF16_512 + AVX512_BITALG_128 AVX512_BITALG_256 AVX512_BITALG_512 AVX512_FP16_128 + AVX512_FP16_128N AVX512_FP16_256 AVX512_FP16_512 AVX512_FP16_SCALAR + AVX512_GFNI_128 AVX512_GFNI_256 AVX512_GFNI_512 AVX512_IFMA_128 + AVX512_IFMA_256 AVX512_IFMA_512 AVX512_VAES_128 AVX512_VAES_256 + AVX512_VAES_512 AVX512_VBMI2_128 AVX512_VBMI2_256 AVX512_VBMI2_512 + AVX512_VBMI_128 AVX512_VBMI_256 AVX512_VBMI_512 AVX512_VNNI_128 + AVX512_VNNI_256 AVX512_VNNI_512 AVX512_VP2INTERSECT_128 AVX512_VP2INTERSECT_256 + AVX512_VP2INTERSECT_512 AVX512_VPCLMULQDQ_128 AVX512_VPCLMULQDQ_256 AVX512_VPCLMULQDQ_512 + AVX512_VPOPCNTDQ_128 AVX512_VPOPCNTDQ_256 AVX512_VPOPCNTDQ_512 AVXAES + AVX_GFNI AVX_VNNI BMI1 BMI2 + CET CLDEMOTE CLFLUSHOPT CLFSH + CLWB CMOV CMPXCHG16B ENQCMD + F16C FAT_NOP FCMOV FMA + FXSAVE FXSAVE64 GFNI I186 + I286PROTECTED I286REAL I386 I486 + I486REAL I86 INVPCID LAHF + LONGMODE LZCNT MONITOR MOVBE + MOVDIR PAUSE PCLMULQDQ PCONFIG + PENTIUMMMX PENTIUMREAL PKU POPCNT + PPRO PPRO_UD0_LONG PREFETCHW PREFETCH_NOP + PTWRITE RDPID RDPMC RDRAND + RDSEED RDTSCP RDWRFSGS RTM + SERIALIZE SGX SGX_ENCLV SHA + SMAP SMX SSE SSE2 + SSE2MMX SSE3 SSE3X87 SSE4 + SSE42 SSEMXCSR SSE_PREFETCH SSSE3 + SSSE3MMX TDX TSX_LDTRK UINTR + VAES VMFUNC VPCLMULQDQ VTX + WAITPKG WBNOINVD X87 XSAVE + XSAVEC XSAVEOPT XSAVES diff --git a/CodeVirtualizer/build/obj/wkit/misc/idata.txt b/CodeVirtualizer/build/obj/wkit/misc/idata.txt new file mode 100644 index 0000000..663a00b --- /dev/null +++ b/CodeVirtualizer/build/obj/wkit/misc/idata.txt @@ -0,0 +1,6883 @@ +# BEGIN_LEGAL +# +# Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# END_LEGAL +#iclass extension category iform isa_set attributes +AAA BASE DECIMAL AAA I86 INVALID +AAD BASE DECIMAL AAD_IMMb I86 INVALID +AAM BASE DECIMAL AAM_IMMb I86 INVALID +AAS BASE DECIMAL AAS I86 INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR32d_GPR32d ADOX_ADCX INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR32d_MEMd ADOX_ADCX INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR64q_GPR64q ADOX_ADCX INVALID +ADCX ADOX_ADCX ADOX_ADCX ADCX_GPR64q_MEMq ADOX_ADCX INVALID +ADC BASE BINARY ADC_AL_IMMb I86 BYTEOP +ADC BASE BINARY ADC_GPR8_GPR8_10 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_GPR8_12 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_IMMb_80r2 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_IMMb_82r2 I86 BYTEOP +ADC BASE BINARY ADC_GPR8_MEMb I86 BYTEOP +ADC BASE BINARY ADC_GPRv_GPRv_11 I86 SCALABLE +ADC BASE BINARY ADC_GPRv_GPRv_13 I86 SCALABLE +ADC BASE BINARY ADC_GPRv_IMMb I86 SCALABLE +ADC BASE BINARY ADC_GPRv_IMMz I86 SCALABLE +ADC BASE BINARY ADC_GPRv_MEMv I86 SCALABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMb_IMMb_80r2 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMb_IMMb_82r2 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADC_LOCK BASE BINARY ADC_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADC BASE BINARY ADC_MEMb_GPR8 I86 BYTEOP:LOCKABLE +ADC BASE BINARY ADC_MEMb_IMMb_80r2 I86 BYTEOP:LOCKABLE +ADC BASE BINARY ADC_MEMb_IMMb_82r2 I86 BYTEOP:LOCKABLE +ADC BASE BINARY ADC_MEMv_GPRv I86 LOCKABLE:SCALABLE +ADC BASE BINARY ADC_MEMv_IMMb I86 LOCKABLE:SCALABLE +ADC BASE BINARY ADC_MEMv_IMMz I86 LOCKABLE:SCALABLE +ADC BASE BINARY ADC_OrAX_IMMz I86 SCALABLE +ADDPD SSE2 SSE ADDPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +ADDPD SSE2 SSE ADDPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +ADDPS SSE SSE ADDPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +ADDPS SSE SSE ADDPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +ADDSD SSE2 SSE ADDSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +ADDSD SSE2 SSE ADDSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +ADDSS SSE SSE ADDSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +ADDSS SSE SSE ADDSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +ADDSUBPD SSE3 SSE ADDSUBPD_XMMpd_MEMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +ADDSUBPD SSE3 SSE ADDSUBPD_XMMpd_XMMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +ADDSUBPS SSE3 SSE ADDSUBPS_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT:MXCSR +ADDSUBPS SSE3 SSE ADDSUBPS_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT:MXCSR +ADD BASE BINARY ADD_AL_IMMb I86 BYTEOP +ADD BASE BINARY ADD_GPR8_GPR8_00 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_GPR8_02 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_IMMb_80r0 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_IMMb_82r0 I86 BYTEOP +ADD BASE BINARY ADD_GPR8_MEMb I86 BYTEOP +ADD BASE BINARY ADD_GPRv_GPRv_01 I86 SCALABLE +ADD BASE BINARY ADD_GPRv_GPRv_03 I86 SCALABLE +ADD BASE BINARY ADD_GPRv_IMMb I86 SCALABLE +ADD BASE BINARY ADD_GPRv_IMMz I86 SCALABLE +ADD BASE BINARY ADD_GPRv_MEMv I86 SCALABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMb_IMMb_80r0 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMb_IMMb_82r0 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADD_LOCK BASE BINARY ADD_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +ADD BASE BINARY ADD_MEMb_GPR8 I86 BYTEOP:LOCKABLE +ADD BASE BINARY ADD_MEMb_IMMb_80r0 I86 BYTEOP:LOCKABLE +ADD BASE BINARY ADD_MEMb_IMMb_82r0 I86 BYTEOP:LOCKABLE +ADD BASE BINARY ADD_MEMv_GPRv I86 LOCKABLE:SCALABLE +ADD BASE BINARY ADD_MEMv_IMMb I86 LOCKABLE:SCALABLE +ADD BASE BINARY ADD_MEMv_IMMz I86 LOCKABLE:SCALABLE +ADD BASE BINARY ADD_OrAX_IMMz I86 SCALABLE +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR32d_GPR32d ADOX_ADCX INVALID +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR32d_MEMd ADOX_ADCX INVALID +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR64q_GPR64q ADOX_ADCX INVALID +ADOX ADOX_ADCX ADOX_ADCX ADOX_GPR64q_MEMq ADOX_ADCX INVALID +AESDEC128KL KEYLOCKER KEYLOCKER AESDEC128KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESDEC256KL KEYLOCKER KEYLOCKER AESDEC256KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESDECLAST AES AES AESDECLAST_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESDECLAST AES AES AESDECLAST_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESDECWIDE128KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESDECWIDE128KL_MEMu8 KEYLOCKER_WIDE INVALID +AESDECWIDE256KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESDECWIDE256KL_MEMu8 KEYLOCKER_WIDE INVALID +AESDEC AES AES AESDEC_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESDEC AES AES AESDEC_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESENC128KL KEYLOCKER KEYLOCKER AESENC128KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESENC256KL KEYLOCKER KEYLOCKER AESENC256KL_XMMu8_MEMu8 KEYLOCKER INVALID +AESENCLAST AES AES AESENCLAST_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESENCLAST AES AES AESENCLAST_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESENCWIDE128KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESENCWIDE128KL_MEMu8 KEYLOCKER_WIDE INVALID +AESENCWIDE256KL KEYLOCKER_WIDE KEYLOCKER_WIDE AESENCWIDE256KL_MEMu8 KEYLOCKER_WIDE INVALID +AESENC AES AES AESENC_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESENC AES AES AESENC_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESIMC AES AES AESIMC_XMMdq_MEMdq AES REQUIRES_ALIGNMENT +AESIMC AES AES AESIMC_XMMdq_XMMdq AES REQUIRES_ALIGNMENT +AESKEYGENASSIST AES AES AESKEYGENASSIST_XMMdq_MEMdq_IMMb AES REQUIRES_ALIGNMENT +AESKEYGENASSIST AES AES AESKEYGENASSIST_XMMdq_XMMdq_IMMb AES REQUIRES_ALIGNMENT +ANDNPD SSE2 LOGICAL_FP ANDNPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +ANDNPD SSE2 LOGICAL_FP ANDNPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +ANDNPS SSE LOGICAL_FP ANDNPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +ANDNPS SSE LOGICAL_FP ANDNPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +ANDN BMI1 BMI1 ANDN_VGPR32d_VGPR32d_MEMd BMI1 INVALID +ANDN BMI1 BMI1 ANDN_VGPR32d_VGPR32d_VGPR32d BMI1 INVALID +ANDN BMI1 BMI1 ANDN_VGPR64q_VGPR64q_MEMq BMI1 INVALID +ANDN BMI1 BMI1 ANDN_VGPR64q_VGPR64q_VGPR64q BMI1 INVALID +ANDPD SSE2 LOGICAL_FP ANDPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +ANDPD SSE2 LOGICAL_FP ANDPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +ANDPS SSE LOGICAL_FP ANDPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +ANDPS SSE LOGICAL_FP ANDPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +AND BASE LOGICAL AND_AL_IMMb I86 BYTEOP +AND BASE LOGICAL AND_GPR8_GPR8_20 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_GPR8_22 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_IMMb_80r4 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_IMMb_82r4 I86 BYTEOP +AND BASE LOGICAL AND_GPR8_MEMb I86 BYTEOP +AND BASE LOGICAL AND_GPRv_GPRv_21 I86 SCALABLE +AND BASE LOGICAL AND_GPRv_GPRv_23 I86 SCALABLE +AND BASE LOGICAL AND_GPRv_IMMb I86 SCALABLE +AND BASE LOGICAL AND_GPRv_IMMz I86 SCALABLE +AND BASE LOGICAL AND_GPRv_MEMv I86 SCALABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMb_IMMb_80r4 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMb_IMMb_82r4 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +AND_LOCK BASE LOGICAL AND_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +AND BASE LOGICAL AND_MEMb_GPR8 I86 BYTEOP:LOCKABLE +AND BASE LOGICAL AND_MEMb_IMMb_80r4 I86 BYTEOP:LOCKABLE +AND BASE LOGICAL AND_MEMb_IMMb_82r4 I86 BYTEOP:LOCKABLE +AND BASE LOGICAL AND_MEMv_GPRv I86 LOCKABLE:SCALABLE +AND BASE LOGICAL AND_MEMv_IMMb I86 LOCKABLE:SCALABLE +AND BASE LOGICAL AND_MEMv_IMMz I86 LOCKABLE:SCALABLE +AND BASE LOGICAL AND_OrAX_IMMz I86 SCALABLE +ARPL BASE SYSTEM ARPL_GPR16_GPR16 I286PROTECTED PROTECTED_MODE +ARPL BASE SYSTEM ARPL_MEMw_GPR16 I286PROTECTED PROTECTED_MODE +BEXTR BMI1 BMI1 BEXTR_VGPR32d_MEMd_VGPR32d BMI1 INVALID +BEXTR BMI1 BMI1 BEXTR_VGPR32d_VGPR32d_VGPR32d BMI1 INVALID +BEXTR BMI1 BMI1 BEXTR_VGPR64q_MEMq_VGPR64q BMI1 INVALID +BEXTR BMI1 BMI1 BEXTR_VGPR64q_VGPR64q_VGPR64q BMI1 INVALID +BEXTR_XOP TBM TBM BEXTR_XOP_VGPR32d_MEMd_IMMd TBM AMDONLY +BEXTR_XOP TBM TBM BEXTR_XOP_VGPR32d_VGPR32d_IMMd TBM AMDONLY +BEXTR_XOP TBM TBM BEXTR_XOP_VGPRyy_MEMy_IMMd TBM AMDONLY:SCALABLE +BEXTR_XOP TBM TBM BEXTR_XOP_VGPRyy_VGPRyy_IMMd TBM AMDONLY:SCALABLE +BLCFILL TBM TBM BLCFILL_VGPR32d_MEMd TBM AMDONLY +BLCFILL TBM TBM BLCFILL_VGPR32d_VGPR32d TBM AMDONLY +BLCFILL TBM TBM BLCFILL_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCFILL TBM TBM BLCFILL_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCIC TBM TBM BLCIC_VGPR32d_MEMd TBM AMDONLY +BLCIC TBM TBM BLCIC_VGPR32d_VGPR32d TBM AMDONLY +BLCIC TBM TBM BLCIC_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCIC TBM TBM BLCIC_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCI TBM TBM BLCI_VGPR32d_MEMd TBM AMDONLY +BLCI TBM TBM BLCI_VGPR32d_VGPR32d TBM AMDONLY +BLCI TBM TBM BLCI_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCI TBM TBM BLCI_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCMSK TBM TBM BLCMSK_VGPR32d_MEMd TBM AMDONLY +BLCMSK TBM TBM BLCMSK_VGPR32d_VGPR32d TBM AMDONLY +BLCMSK TBM TBM BLCMSK_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCMSK TBM TBM BLCMSK_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLCS TBM TBM BLCS_VGPR32d_MEMd TBM AMDONLY +BLCS TBM TBM BLCS_VGPR32d_VGPR32d TBM AMDONLY +BLCS TBM TBM BLCS_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLCS TBM TBM BLCS_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLENDPD SSE4 SSE BLENDPD_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDPD SSE4 SSE BLENDPD_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDPS SSE4 SSE BLENDPS_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDPS SSE4 SSE BLENDPS_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT +BLENDVPD SSE4 SSE BLENDVPD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +BLENDVPD SSE4 SSE BLENDVPD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +BLENDVPS SSE4 SSE BLENDVPS_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +BLENDVPS SSE4 SSE BLENDVPS_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +BLSFILL TBM TBM BLSFILL_VGPR32d_MEMd TBM AMDONLY +BLSFILL TBM TBM BLSFILL_VGPR32d_VGPR32d TBM AMDONLY +BLSFILL TBM TBM BLSFILL_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLSFILL TBM TBM BLSFILL_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLSIC TBM TBM BLSIC_VGPR32d_MEMd TBM AMDONLY +BLSIC TBM TBM BLSIC_VGPR32d_VGPR32d TBM AMDONLY +BLSIC TBM TBM BLSIC_VGPRyy_MEMy TBM AMDONLY:SCALABLE +BLSIC TBM TBM BLSIC_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +BLSI BMI1 BMI1 BLSI_VGPR32d_MEMd BMI1 INVALID +BLSI BMI1 BMI1 BLSI_VGPR32d_VGPR32d BMI1 INVALID +BLSI BMI1 BMI1 BLSI_VGPR64q_MEMq BMI1 INVALID +BLSI BMI1 BMI1 BLSI_VGPR64q_VGPR64q BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR32d_MEMd BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR32d_VGPR32d BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR64q_MEMq BMI1 INVALID +BLSMSK BMI1 BMI1 BLSMSK_VGPR64q_VGPR64q BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR32d_MEMd BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR32d_VGPR32d BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR64q_MEMq BMI1 INVALID +BLSR BMI1 BMI1 BLSR_VGPR64q_VGPR64q BMI1 INVALID +BNDCL MPX MPX BNDCL_BND_AGEN MPX EXCEPTION_BR +BNDCL MPX MPX BNDCL_BND_GPR32 MPX EXCEPTION_BR +BNDCL MPX MPX BNDCL_BND_GPR64 MPX EXCEPTION_BR +BNDCN MPX MPX BNDCN_BND_AGEN MPX EXCEPTION_BR +BNDCN MPX MPX BNDCN_BND_GPR32 MPX EXCEPTION_BR +BNDCN MPX MPX BNDCN_BND_GPR64 MPX EXCEPTION_BR +BNDCU MPX MPX BNDCU_BND_AGEN MPX EXCEPTION_BR +BNDCU MPX MPX BNDCU_BND_GPR32 MPX EXCEPTION_BR +BNDCU MPX MPX BNDCU_BND_GPR64 MPX EXCEPTION_BR +BNDLDX MPX MPX BNDLDX_BND_MEMbnd32 MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BNDLDX MPX MPX BNDLDX_BND_MEMbnd64 MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BNDMK MPX MPX BNDMK_BND_AGEN MPX NO_RIP_REL +BNDMOV MPX MPX BNDMOV_BND_BND MPX INVALID +BNDMOV MPX MPX BNDMOV_BND_MEMdq MPX INVALID +BNDMOV MPX MPX BNDMOV_BND_MEMq MPX INVALID +BNDMOV MPX MPX BNDMOV_MEMdq_BND MPX INVALID +BNDMOV MPX MPX BNDMOV_MEMq_BND MPX INVALID +BNDSTX MPX MPX BNDSTX_MEMbnd32_BND MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BNDSTX MPX MPX BNDSTX_MEMbnd64_BND MPX EXCEPTION_BR:SPECIAL_AGEN_REQUIRED:INDEX_REG_IS_POINTER:NO_RIP_REL +BOUND BASE INTERRUPT BOUND_GPRv_MEMa16 I186 EXCEPTION_BR:SCALABLE +BOUND BASE INTERRUPT BOUND_GPRv_MEMa32 I186 EXCEPTION_BR:SCALABLE +BSF BASE BITBYTE BSF_GPRv_GPRv I386 SCALABLE +BSF BASE BITBYTE BSF_GPRv_MEMv I386 SCALABLE +BSR BASE BITBYTE BSR_GPRv_GPRv I386 SCALABLE +BSR BASE BITBYTE BSR_GPRv_MEMv I386 SCALABLE +BSWAP BASE DATAXFER BSWAP_GPRv I486REAL SCALABLE +BTC BASE BITBYTE BTC_GPRv_GPRv I386 SCALABLE +BTC BASE BITBYTE BTC_GPRv_IMMb I386 SCALABLE +BTC_LOCK BASE BITBYTE BTC_LOCK_MEMv_GPRv I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTC_LOCK BASE BITBYTE BTC_LOCK_MEMv_IMMb I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTC BASE BITBYTE BTC_MEMv_GPRv I386 LOCKABLE:SCALABLE +BTC BASE BITBYTE BTC_MEMv_IMMb I386 LOCKABLE:SCALABLE +BTR BASE BITBYTE BTR_GPRv_GPRv I386 SCALABLE +BTR BASE BITBYTE BTR_GPRv_IMMb I386 SCALABLE +BTR_LOCK BASE BITBYTE BTR_LOCK_MEMv_GPRv I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTR_LOCK BASE BITBYTE BTR_LOCK_MEMv_IMMb I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTR BASE BITBYTE BTR_MEMv_GPRv I386 LOCKABLE:SCALABLE +BTR BASE BITBYTE BTR_MEMv_IMMb I386 LOCKABLE:SCALABLE +BTS BASE BITBYTE BTS_GPRv_GPRv I386 SCALABLE +BTS BASE BITBYTE BTS_GPRv_IMMb I386 SCALABLE +BTS_LOCK BASE BITBYTE BTS_LOCK_MEMv_GPRv I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTS_LOCK BASE BITBYTE BTS_LOCK_MEMv_IMMb I386 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +BTS BASE BITBYTE BTS_MEMv_GPRv I386 LOCKABLE:SCALABLE +BTS BASE BITBYTE BTS_MEMv_IMMb I386 LOCKABLE:SCALABLE +BT BASE BITBYTE BT_GPRv_GPRv I386 SCALABLE +BT BASE BITBYTE BT_GPRv_IMMb I386 SCALABLE +BT BASE BITBYTE BT_MEMv_GPRv I386 SCALABLE +BT BASE BITBYTE BT_MEMv_IMMb I386 SCALABLE +BZHI BMI2 BMI2 BZHI_VGPR32d_MEMd_VGPR32d BMI2 INVALID +BZHI BMI2 BMI2 BZHI_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +BZHI BMI2 BMI2 BZHI_VGPR64q_MEMq_VGPR64q BMI2 INVALID +BZHI BMI2 BMI2 BZHI_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +CALL_FAR BASE CALL CALL_FAR_MEMp2 I86 FAR_XFER:NOTSX:INDIRECT_BRANCH:FIXED_BASE1:STACKPUSH1:SCALABLE +CALL_FAR BASE CALL CALL_FAR_PTRp_IMMw I86 FAR_XFER:NOTSX:FIXED_BASE0:STACKPUSH0:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_GPRv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:FIXED_BASE0:STACKPUSH0:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_MEMv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:FIXED_BASE1:STACKPUSH1:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_RELBRd I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPUSH0:SCALABLE +CALL_NEAR BASE CALL CALL_NEAR_RELBRz I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPUSH0:SCALABLE +CBW BASE CONVERT CBW I86 INVALID +CDQ BASE CONVERT CDQ I386 INVALID +CDQE LONGMODE CONVERT CDQE LONGMODE INVALID +CLAC SMAP SMAP CLAC SMAP INVALID +CLC BASE FLAGOP CLC I86 INVALID +CLD BASE FLAGOP CLD I86 NOTSX_COND +CLDEMOTE CLDEMOTE CLDEMOTE CLDEMOTE_MEMu8 CLDEMOTE INVALID +CLFLUSHOPT CLFLUSHOPT CLFLUSHOPT CLFLUSHOPT_MEMmprefetch CLFLUSHOPT PREFETCH +CLFLUSH CLFSH MISC CLFLUSH_MEMmprefetch CLFSH NOTSX +CLGI SVM SYSTEM CLGI SVM PROTECTED_MODE:AMDONLY +CLI BASE FLAGOP CLI I86 NOTSX +CLRSSBSY CET CET CLRSSBSY_MEMu64 CET INVALID +CLTS BASE SYSTEM CLTS I286REAL RING0:NOTSX +CLUI UINTR UINTR CLUI UINTR INVALID +CLWB CLWB CLWB CLWB_MEMmprefetch CLWB PREFETCH +CLZERO CLZERO CLZERO CLZERO CLZERO AMDONLY +CMC BASE FLAGOP CMC I86 INVALID +CMOVBE BASE CMOV CMOVBE_GPRv_GPRv CMOV SCALABLE +CMOVBE BASE CMOV CMOVBE_GPRv_MEMv CMOV SCALABLE +CMOVB BASE CMOV CMOVB_GPRv_GPRv CMOV SCALABLE +CMOVB BASE CMOV CMOVB_GPRv_MEMv CMOV SCALABLE +CMOVLE BASE CMOV CMOVLE_GPRv_GPRv CMOV SCALABLE +CMOVLE BASE CMOV CMOVLE_GPRv_MEMv CMOV SCALABLE +CMOVL BASE CMOV CMOVL_GPRv_GPRv CMOV SCALABLE +CMOVL BASE CMOV CMOVL_GPRv_MEMv CMOV SCALABLE +CMOVNBE BASE CMOV CMOVNBE_GPRv_GPRv CMOV SCALABLE +CMOVNBE BASE CMOV CMOVNBE_GPRv_MEMv CMOV SCALABLE +CMOVNB BASE CMOV CMOVNB_GPRv_GPRv CMOV SCALABLE +CMOVNB BASE CMOV CMOVNB_GPRv_MEMv CMOV SCALABLE +CMOVNLE BASE CMOV CMOVNLE_GPRv_GPRv CMOV SCALABLE +CMOVNLE BASE CMOV CMOVNLE_GPRv_MEMv CMOV SCALABLE +CMOVNL BASE CMOV CMOVNL_GPRv_GPRv CMOV SCALABLE +CMOVNL BASE CMOV CMOVNL_GPRv_MEMv CMOV SCALABLE +CMOVNO BASE CMOV CMOVNO_GPRv_GPRv CMOV SCALABLE +CMOVNO BASE CMOV CMOVNO_GPRv_MEMv CMOV SCALABLE +CMOVNP BASE CMOV CMOVNP_GPRv_GPRv CMOV SCALABLE +CMOVNP BASE CMOV CMOVNP_GPRv_MEMv CMOV SCALABLE +CMOVNS BASE CMOV CMOVNS_GPRv_GPRv CMOV SCALABLE +CMOVNS BASE CMOV CMOVNS_GPRv_MEMv CMOV SCALABLE +CMOVNZ BASE CMOV CMOVNZ_GPRv_GPRv CMOV SCALABLE +CMOVNZ BASE CMOV CMOVNZ_GPRv_MEMv CMOV SCALABLE +CMOVO BASE CMOV CMOVO_GPRv_GPRv CMOV SCALABLE +CMOVO BASE CMOV CMOVO_GPRv_MEMv CMOV SCALABLE +CMOVP BASE CMOV CMOVP_GPRv_GPRv CMOV SCALABLE +CMOVP BASE CMOV CMOVP_GPRv_MEMv CMOV SCALABLE +CMOVS BASE CMOV CMOVS_GPRv_GPRv CMOV SCALABLE +CMOVS BASE CMOV CMOVS_GPRv_MEMv CMOV SCALABLE +CMOVZ BASE CMOV CMOVZ_GPRv_GPRv CMOV SCALABLE +CMOVZ BASE CMOV CMOVZ_GPRv_MEMv CMOV SCALABLE +CMPPD SSE2 SSE CMPPD_XMMpd_MEMpd_IMMb SSE2 REQUIRES_ALIGNMENT:MXCSR +CMPPD SSE2 SSE CMPPD_XMMpd_XMMpd_IMMb SSE2 REQUIRES_ALIGNMENT:MXCSR +CMPPS SSE SSE CMPPS_XMMps_MEMps_IMMb SSE REQUIRES_ALIGNMENT:MXCSR +CMPPS SSE SSE CMPPS_XMMps_XMMps_IMMb SSE REQUIRES_ALIGNMENT:MXCSR +CMPSB BASE STRINGOP CMPSB I86 FIXED_BASE0:FIXED_BASE1:BYTEOP +CMPSD BASE STRINGOP CMPSD I386 FIXED_BASE0:FIXED_BASE1 +CMPSD_XMM SSE2 SSE CMPSD_XMM_XMMsd_MEMsd_IMMb SSE2 SIMD_SCALAR:MXCSR +CMPSD_XMM SSE2 SSE CMPSD_XMM_XMMsd_XMMsd_IMMb SSE2 SIMD_SCALAR:MXCSR +CMPSQ LONGMODE STRINGOP CMPSQ LONGMODE FIXED_BASE0:FIXED_BASE1 +CMPSS SSE SSE CMPSS_XMMss_MEMss_IMMb SSE SIMD_SCALAR:MXCSR +CMPSS SSE SSE CMPSS_XMMss_XMMss_IMMb SSE SIMD_SCALAR:MXCSR +CMPSW BASE STRINGOP CMPSW I86 FIXED_BASE0:FIXED_BASE1 +CMPXCHG16B_LOCK LONGMODE SEMAPHORE CMPXCHG16B_LOCK_MEMdq CMPXCHG16B REQUIRES_ALIGNMENT:LOCKED +CMPXCHG16B LONGMODE SEMAPHORE CMPXCHG16B_MEMdq CMPXCHG16B REQUIRES_ALIGNMENT:LOCKABLE +CMPXCHG8B_LOCK BASE SEMAPHORE CMPXCHG8B_LOCK_MEMq PENTIUMREAL LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +CMPXCHG8B BASE SEMAPHORE CMPXCHG8B_MEMq PENTIUMREAL LOCKABLE +CMPXCHG BASE SEMAPHORE CMPXCHG_GPR8_GPR8 I486REAL BYTEOP +CMPXCHG BASE SEMAPHORE CMPXCHG_GPRv_GPRv I486REAL SCALABLE +CMPXCHG_LOCK BASE SEMAPHORE CMPXCHG_LOCK_MEMb_GPR8 I486REAL BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +CMPXCHG_LOCK BASE SEMAPHORE CMPXCHG_LOCK_MEMv_GPRv I486REAL LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +CMPXCHG BASE SEMAPHORE CMPXCHG_MEMb_GPR8 I486REAL BYTEOP:LOCKABLE +CMPXCHG BASE SEMAPHORE CMPXCHG_MEMv_GPRv I486REAL LOCKABLE:SCALABLE +CMP BASE BINARY CMP_AL_IMMb I86 BYTEOP +CMP BASE BINARY CMP_GPR8_GPR8_38 I86 BYTEOP +CMP BASE BINARY CMP_GPR8_GPR8_3A I86 BYTEOP +CMP BASE BINARY CMP_GPR8_IMMb_80r7 I86 BYTEOP +CMP BASE BINARY CMP_GPR8_IMMb_82r7 I86 BYTEOP +CMP BASE BINARY CMP_GPR8_MEMb I86 BYTEOP +CMP BASE BINARY CMP_GPRv_GPRv_39 I86 SCALABLE +CMP BASE BINARY CMP_GPRv_GPRv_3B I86 SCALABLE +CMP BASE BINARY CMP_GPRv_IMMb I86 SCALABLE +CMP BASE BINARY CMP_GPRv_IMMz I86 SCALABLE +CMP BASE BINARY CMP_GPRv_MEMv I86 SCALABLE +CMP BASE BINARY CMP_MEMb_GPR8 I86 BYTEOP +CMP BASE BINARY CMP_MEMb_IMMb_80r7 I86 BYTEOP +CMP BASE BINARY CMP_MEMb_IMMb_82r7 I86 BYTEOP +CMP BASE BINARY CMP_MEMv_GPRv I86 SCALABLE +CMP BASE BINARY CMP_MEMv_IMMb I86 SCALABLE +CMP BASE BINARY CMP_MEMv_IMMz I86 SCALABLE +CMP BASE BINARY CMP_OrAX_IMMz I86 SCALABLE +COMISD SSE2 SSE COMISD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +COMISD SSE2 SSE COMISD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +COMISS SSE SSE COMISS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +COMISS SSE SSE COMISS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +CPUID BASE MISC CPUID I486REAL NOTSX +CQO LONGMODE CONVERT CQO LONGMODE INVALID +CRC32 SSE4 SSE CRC32_GPRyy_GPR8b SSE42 IGNORES_OSFXSR:SCALABLE +CRC32 SSE4 SSE CRC32_GPRyy_GPRv SSE42 IGNORES_OSFXSR:SCALABLE +CRC32 SSE4 SSE CRC32_GPRyy_MEMb SSE42 IGNORES_OSFXSR:SCALABLE +CRC32 SSE4 SSE CRC32_GPRyy_MEMv SSE42 IGNORES_OSFXSR:SCALABLE +CVTDQ2PD SSE2 CONVERT CVTDQ2PD_XMMpd_MEMq SSE2 INVALID +CVTDQ2PD SSE2 CONVERT CVTDQ2PD_XMMpd_XMMq SSE2 INVALID +CVTDQ2PS SSE2 CONVERT CVTDQ2PS_XMMps_MEMdq SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTDQ2PS SSE2 CONVERT CVTDQ2PS_XMMps_XMMdq SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2DQ SSE2 CONVERT CVTPD2DQ_XMMdq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2DQ SSE2 CONVERT CVTPD2DQ_XMMdq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2PI SSE2 CONVERT CVTPD2PI_MMXq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTPD2PI SSE2 CONVERT CVTPD2PI_MMXq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTPD2PS SSE2 CONVERT CVTPD2PS_XMMps_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPD2PS SSE2 CONVERT CVTPD2PS_XMMps_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPI2PD SSE2 CONVERT CVTPI2PD_XMMpd_MEMq SSE2 MXCSR:MMX_EXCEPT:NOTSX +CVTPI2PD SSE2 CONVERT CVTPI2PD_XMMpd_MMXq SSE2 MXCSR:MMX_EXCEPT:NOTSX +CVTPI2PS SSE CONVERT CVTPI2PS_XMMq_MEMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTPI2PS SSE CONVERT CVTPI2PS_XMMq_MMXq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTPS2DQ SSE2 CONVERT CVTPS2DQ_XMMdq_MEMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPS2DQ SSE2 CONVERT CVTPS2DQ_XMMdq_XMMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTPS2PD SSE2 CONVERT CVTPS2PD_XMMpd_MEMq SSE2 MXCSR +CVTPS2PD SSE2 CONVERT CVTPS2PD_XMMpd_XMMq SSE2 MXCSR +CVTPS2PI SSE CONVERT CVTPS2PI_MMXq_MEMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTPS2PI SSE CONVERT CVTPS2PI_MMXq_XMMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR32d_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR32d_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR64q_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SI SSE2 CONVERT CVTSD2SI_GPR64q_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SS SSE2 CONVERT CVTSD2SS_XMMss_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTSD2SS SSE2 CONVERT CVTSD2SS_XMMss_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_GPR32d SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_GPR64q SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_MEMd SSE2 SIMD_SCALAR:MXCSR +CVTSI2SD SSE2 CONVERT CVTSI2SD_XMMsd_MEMq SSE2 SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_GPR32d SSE SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_GPR64q SSE SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_MEMd SSE SIMD_SCALAR:MXCSR +CVTSI2SS SSE CONVERT CVTSI2SS_XMMss_MEMq SSE SIMD_SCALAR:MXCSR +CVTSS2SD SSE2 CONVERT CVTSS2SD_XMMsd_MEMss SSE2 SIMD_SCALAR:MXCSR +CVTSS2SD SSE2 CONVERT CVTSS2SD_XMMsd_XMMss SSE2 SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR32d_MEMss SSE SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR32d_XMMss SSE SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR64q_MEMss SSE SIMD_SCALAR:MXCSR +CVTSS2SI SSE CONVERT CVTSS2SI_GPR64q_XMMss SSE SIMD_SCALAR:MXCSR +CVTTPD2DQ SSE2 CONVERT CVTTPD2DQ_XMMdq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPD2DQ SSE2 CONVERT CVTTPD2DQ_XMMdq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPD2PI SSE2 CONVERT CVTTPD2PI_MMXq_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTTPD2PI SSE2 CONVERT CVTTPD2PI_MMXq_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MMX_EXCEPT:NOTSX +CVTTPS2DQ SSE2 CONVERT CVTTPS2DQ_XMMdq_MEMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPS2DQ SSE2 CONVERT CVTTPS2DQ_XMMdq_XMMps SSE2 REQUIRES_ALIGNMENT:MXCSR +CVTTPS2PI SSE CONVERT CVTTPS2PI_MMXq_MEMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTTPS2PI SSE CONVERT CVTTPS2PI_MMXq_XMMq SSE MXCSR:MMX_EXCEPT:NOTSX +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR32d_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR32d_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR64q_MEMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSD2SI SSE2 CONVERT CVTTSD2SI_GPR64q_XMMsd SSE2 SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR32d_MEMss SSE SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR32d_XMMss SSE SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR64q_MEMss SSE SIMD_SCALAR:MXCSR +CVTTSS2SI SSE CONVERT CVTTSS2SI_GPR64q_XMMss SSE SIMD_SCALAR:MXCSR +CWD BASE CONVERT CWD I86 INVALID +CWDE BASE CONVERT CWDE I386 INVALID +DAA BASE DECIMAL DAA I86 INVALID +DAS BASE DECIMAL DAS I86 INVALID +DEC BASE BINARY DEC_GPR8 I86 BYTEOP +DEC BASE BINARY DEC_GPRv_48 I86 SCALABLE +DEC BASE BINARY DEC_GPRv_FFr1 I86 SCALABLE +DEC_LOCK BASE BINARY DEC_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +DEC_LOCK BASE BINARY DEC_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +DEC BASE BINARY DEC_MEMb I86 BYTEOP:LOCKABLE +DEC BASE BINARY DEC_MEMv I86 LOCKABLE:SCALABLE +DIVPD SSE2 SSE DIVPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +DIVPD SSE2 SSE DIVPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +DIVPS SSE SSE DIVPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +DIVPS SSE SSE DIVPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +DIVSD SSE2 SSE DIVSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +DIVSD SSE2 SSE DIVSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +DIVSS SSE SSE DIVSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +DIVSS SSE SSE DIVSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +DIV BASE BINARY DIV_GPR8 I86 BYTEOP +DIV BASE BINARY DIV_GPRv I86 SCALABLE +DIV BASE BINARY DIV_MEMb I86 BYTEOP +DIV BASE BINARY DIV_MEMv I86 SCALABLE +DPPD SSE4 SSE DPPD_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +DPPD SSE4 SSE DPPD_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +DPPS SSE4 SSE DPPS_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +DPPS SSE4 SSE DPPS_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +EMMS MMX MMX EMMS PENTIUMMMX X87_MMX_STATE_W:NOTSX +ENCLS SGX SGX ENCLS SGX INVALID +ENCLU SGX SGX ENCLU SGX INVALID +ENCLV SGX_ENCLV SGX ENCLV SGX_ENCLV INVALID +ENCODEKEY128 KEYLOCKER KEYLOCKER ENCODEKEY128_GPR32u8_GPR32u8 KEYLOCKER INVALID +ENCODEKEY256 KEYLOCKER KEYLOCKER ENCODEKEY256_GPR32u8_GPR32u8 KEYLOCKER INVALID +ENDBR32 CET CET ENDBR32 CET INVALID +ENDBR64 CET CET ENDBR64 CET INVALID +ENQCMDS ENQCMD ENQCMD ENQCMDS_GPRa_MEMu32 ENQCMD INVALID +ENQCMD ENQCMD ENQCMD ENQCMD_GPRa_MEMu32 ENQCMD INVALID +ENTER BASE MISC ENTER_IMMw_IMMb I186 ATT_OPERAND_ORDER_EXCEPTION:FIXED_BASE0:STACKPUSH0:SCALABLE +EXTRACTPS SSE4 SSE EXTRACTPS_GPR32d_XMMdq_IMMb SSE4 INVALID +EXTRACTPS SSE4 SSE EXTRACTPS_MEMd_XMMps_IMMb SSE4 INVALID +EXTRQ SSE4a BITBYTE EXTRQ_XMMq_IMMb_IMMb SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +EXTRQ SSE4a BITBYTE EXTRQ_XMMq_XMMdq SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +F2XM1 X87 X87_ALU F2XM1 X87 NOTSX +FABS X87 X87_ALU FABS X87 NOTSX +FADDP X87 X87_ALU FADDP_X87_ST0 X87 NOTSX +FADD X87 X87_ALU FADD_ST0_MEMm64real X87 NOTSX +FADD X87 X87_ALU FADD_ST0_MEMmem32real X87 NOTSX +FADD X87 X87_ALU FADD_ST0_X87 X87 NOTSX +FADD X87 X87_ALU FADD_X87_ST0 X87 NOTSX +FBLD X87 X87_ALU FBLD_ST0_MEMmem80dec X87 NOTSX +FBSTP X87 X87_ALU FBSTP_MEMmem80dec_ST0 X87 NOTSX +FCHS X87 X87_ALU FCHS X87 NOTSX +FCMOVBE X87 FCMOV FCMOVBE_ST0_X87 FCMOV NOTSX +FCMOVB X87 FCMOV FCMOVB_ST0_X87 FCMOV NOTSX +FCMOVE X87 FCMOV FCMOVE_ST0_X87 FCMOV NOTSX +FCMOVNBE X87 FCMOV FCMOVNBE_ST0_X87 FCMOV NOTSX +FCMOVNB X87 FCMOV FCMOVNB_ST0_X87 FCMOV NOTSX +FCMOVNE X87 FCMOV FCMOVNE_ST0_X87 FCMOV NOTSX +FCMOVNU X87 FCMOV FCMOVNU_ST0_X87 FCMOV NOTSX +FCMOVU X87 FCMOV FCMOVU_ST0_X87 FCMOV NOTSX +FCOMIP X87 X87_ALU FCOMIP_ST0_X87 PPRO NOTSX +FCOMI X87 X87_ALU FCOMI_ST0_X87 PPRO NOTSX +FCOMPP X87 X87_ALU FCOMPP X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_MEMm64real X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_MEMmem32real X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_X87 X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_X87_DCD1 X87 NOTSX +FCOMP X87 X87_ALU FCOMP_ST0_X87_DED0 X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_MEMm64real X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_MEMmem32real X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_X87 X87 NOTSX +FCOM X87 X87_ALU FCOM_ST0_X87_DCD0 X87 NOTSX +FCOS X87 X87_ALU FCOS X87 NOTSX +FDECSTP X87 X87_ALU FDECSTP X87 X87_CONTROL:NOTSX +FDISI8087_NOP X87 X87_ALU FDISI8087_NOP X87 NOP:NOTSX +FDIVP X87 X87_ALU FDIVP_X87_ST0 X87 NOTSX +FDIVRP X87 X87_ALU FDIVRP_X87_ST0 X87 NOTSX +FDIVR X87 X87_ALU FDIVR_ST0_MEMm64real X87 NOTSX +FDIVR X87 X87_ALU FDIVR_ST0_MEMmem32real X87 NOTSX +FDIVR X87 X87_ALU FDIVR_ST0_X87 X87 NOTSX +FDIVR X87 X87_ALU FDIVR_X87_ST0 X87 NOTSX +FDIV X87 X87_ALU FDIV_ST0_MEMm64real X87 NOTSX +FDIV X87 X87_ALU FDIV_ST0_MEMmem32real X87 NOTSX +FDIV X87 X87_ALU FDIV_ST0_X87 X87 NOTSX +FDIV X87 X87_ALU FDIV_X87_ST0 X87 NOTSX +FEMMS 3DNOW MMX FEMMS 3DNOW X87_MMX_STATE_W:AMDONLY +FENI8087_NOP X87 X87_ALU FENI8087_NOP X87 NOP:NOTSX +FFREEP X87 X87_ALU FFREEP_X87 X87 X87_CONTROL:NOTSX +FFREE X87 X87_ALU FFREE_X87 X87 X87_CONTROL:NOTSX +FIADD X87 X87_ALU FIADD_ST0_MEMmem16int X87 NOTSX +FIADD X87 X87_ALU FIADD_ST0_MEMmem32int X87 NOTSX +FICOMP X87 X87_ALU FICOMP_ST0_MEMmem16int X87 NOTSX +FICOMP X87 X87_ALU FICOMP_ST0_MEMmem32int X87 NOTSX +FICOM X87 X87_ALU FICOM_ST0_MEMmem16int X87 NOTSX +FICOM X87 X87_ALU FICOM_ST0_MEMmem32int X87 NOTSX +FIDIVR X87 X87_ALU FIDIVR_ST0_MEMmem16int X87 NOTSX +FIDIVR X87 X87_ALU FIDIVR_ST0_MEMmem32int X87 NOTSX +FIDIV X87 X87_ALU FIDIV_ST0_MEMmem16int X87 NOTSX +FIDIV X87 X87_ALU FIDIV_ST0_MEMmem32int X87 NOTSX +FILD X87 X87_ALU FILD_ST0_MEMm64int X87 NOTSX +FILD X87 X87_ALU FILD_ST0_MEMmem16int X87 NOTSX +FILD X87 X87_ALU FILD_ST0_MEMmem32int X87 NOTSX +FIMUL X87 X87_ALU FIMUL_ST0_MEMmem16int X87 NOTSX +FIMUL X87 X87_ALU FIMUL_ST0_MEMmem32int X87 NOTSX +FINCSTP X87 X87_ALU FINCSTP X87 X87_CONTROL:NOTSX +FISTP X87 X87_ALU FISTP_MEMm64int_ST0 X87 NOTSX +FISTP X87 X87_ALU FISTP_MEMmem16int_ST0 X87 NOTSX +FISTP X87 X87_ALU FISTP_MEMmem32int_ST0 X87 NOTSX +FISTTP SSE3 X87_ALU FISTTP_MEMm64int_ST0 SSE3X87 NOTSX +FISTTP SSE3 X87_ALU FISTTP_MEMmem16int_ST0 SSE3X87 NOTSX +FISTTP SSE3 X87_ALU FISTTP_MEMmem32int_ST0 SSE3 NOTSX +FIST X87 X87_ALU FIST_MEMmem16int_ST0 X87 NOTSX +FIST X87 X87_ALU FIST_MEMmem32int_ST0 X87 NOTSX +FISUBR X87 X87_ALU FISUBR_ST0_MEMmem16int X87 NOTSX +FISUBR X87 X87_ALU FISUBR_ST0_MEMmem32int X87 NOTSX +FISUB X87 X87_ALU FISUB_ST0_MEMmem16int X87 NOTSX +FISUB X87 X87_ALU FISUB_ST0_MEMmem32int X87 NOTSX +FLD1 X87 X87_ALU FLD1 X87 NOTSX +FLDCW X87 X87_ALU FLDCW_MEMmem16 X87 X87_CONTROL:NOTSX +FLDENV X87 X87_ALU FLDENV_MEMmem14 X87 X87_CONTROL:NOTSX +FLDENV X87 X87_ALU FLDENV_MEMmem28 X87 X87_CONTROL:NOTSX +FLDL2E X87 X87_ALU FLDL2E X87 NOTSX +FLDL2T X87 X87_ALU FLDL2T X87 NOTSX +FLDLG2 X87 X87_ALU FLDLG2 X87 NOTSX +FLDLN2 X87 X87_ALU FLDLN2 X87 NOTSX +FLDPI X87 X87_ALU FLDPI X87 NOTSX +FLDZ X87 X87_ALU FLDZ X87 NOTSX +FLD X87 X87_ALU FLD_ST0_MEMm64real X87 NOTSX +FLD X87 X87_ALU FLD_ST0_MEMmem32real X87 NOTSX +FLD X87 X87_ALU FLD_ST0_MEMmem80real X87 NOTSX +FLD X87 X87_ALU FLD_ST0_X87 X87 NOTSX +FMULP X87 X87_ALU FMULP_X87_ST0 X87 NOTSX +FMUL X87 X87_ALU FMUL_ST0_MEMm64real X87 NOTSX +FMUL X87 X87_ALU FMUL_ST0_MEMmem32real X87 NOTSX +FMUL X87 X87_ALU FMUL_ST0_X87 X87 NOTSX +FMUL X87 X87_ALU FMUL_X87_ST0 X87 NOTSX +FNCLEX X87 X87_ALU FNCLEX X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNINIT X87 X87_ALU FNINIT X87 X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FNOP X87 X87_ALU FNOP X87 NOP:X87_CONTROL:NOTSX +FNSAVE X87 X87_ALU FNSAVE_MEMmem108 X87 X87_MMX_STATE_R:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FNSAVE X87 X87_ALU FNSAVE_MEMmem94 X87 X87_MMX_STATE_R:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FNSTCW X87 X87_ALU FNSTCW_MEMmem16 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTENV X87 X87_ALU FNSTENV_MEMmem14 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTENV X87 X87_ALU FNSTENV_MEMmem28 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTSW X87 X87_ALU FNSTSW_AX X87 X87_NOWAIT:X87_CONTROL:NOTSX +FNSTSW X87 X87_ALU FNSTSW_MEMmem16 X87 X87_NOWAIT:X87_CONTROL:NOTSX +FPATAN X87 X87_ALU FPATAN X87 NOTSX +FPREM X87 X87_ALU FPREM X87 NOTSX +FPREM1 X87 X87_ALU FPREM1 X87 NOTSX +FPTAN X87 X87_ALU FPTAN X87 NOTSX +FRNDINT X87 X87_ALU FRNDINT X87 NOTSX +FRSTOR X87 X87_ALU FRSTOR_MEMmem108 X87 X87_MMX_STATE_W:X87_CONTROL:NOTSX +FRSTOR X87 X87_ALU FRSTOR_MEMmem94 X87 X87_MMX_STATE_W:X87_CONTROL:NOTSX +FSCALE X87 X87_ALU FSCALE X87 NOTSX +FSETPM287_NOP X87 X87_ALU FSETPM287_NOP X87 NOP:NOTSX +FSIN X87 X87_ALU FSIN X87 NOTSX +FSINCOS X87 X87_ALU FSINCOS X87 NOTSX +FSQRT X87 X87_ALU FSQRT X87 NOTSX +FSTPNCE X87 X87_ALU FSTPNCE_X87_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_MEMm64real_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_MEMmem32real_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_MEMmem80real_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_X87_ST0 X87 NOTSX +FSTP X87 X87_ALU FSTP_X87_ST0_DFD0 X87 NOTSX +FSTP X87 X87_ALU FSTP_X87_ST0_DFD1 X87 NOTSX +FST X87 X87_ALU FST_MEMm64real_ST0 X87 NOTSX +FST X87 X87_ALU FST_MEMmem32real_ST0 X87 NOTSX +FST X87 X87_ALU FST_X87_ST0 X87 NOTSX +FSUBP X87 X87_ALU FSUBP_X87_ST0 X87 NOTSX +FSUBRP X87 X87_ALU FSUBRP_X87_ST0 X87 NOTSX +FSUBR X87 X87_ALU FSUBR_ST0_MEMm64real X87 NOTSX +FSUBR X87 X87_ALU FSUBR_ST0_MEMmem32real X87 NOTSX +FSUBR X87 X87_ALU FSUBR_ST0_X87 X87 NOTSX +FSUBR X87 X87_ALU FSUBR_X87_ST0 X87 NOTSX +FSUB X87 X87_ALU FSUB_ST0_MEMm64real X87 NOTSX +FSUB X87 X87_ALU FSUB_ST0_MEMmem32real X87 NOTSX +FSUB X87 X87_ALU FSUB_ST0_X87 X87 NOTSX +FSUB X87 X87_ALU FSUB_X87_ST0 X87 NOTSX +FTST X87 X87_ALU FTST X87 NOTSX +FUCOMIP X87 X87_ALU FUCOMIP_ST0_X87 PPRO NOTSX +FUCOMI X87 X87_ALU FUCOMI_ST0_X87 PPRO NOTSX +FUCOMPP X87 X87_ALU FUCOMPP X87 NOTSX +FUCOMP X87 X87_ALU FUCOMP_ST0_X87 X87 NOTSX +FUCOM X87 X87_ALU FUCOM_ST0_X87 X87 NOTSX +FWAIT X87 X87_ALU FWAIT X87 X87_CONTROL:NOTSX +FXAM X87 X87_ALU FXAM X87 NOTSX +FXCH X87 X87_ALU FXCH_ST0_X87 X87 NOTSX +FXCH X87 X87_ALU FXCH_ST0_X87_DDC1 X87 NOTSX +FXCH X87 X87_ALU FXCH_ST0_X87_DFC1 X87 NOTSX +FXRSTOR64 SSE SSE FXRSTOR64_MEMmfpxenv FXSAVE64 XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FXRSTOR SSE SSE FXRSTOR_MEMmfpxenv FXSAVE XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:X87_NOWAIT:X87_CONTROL:NOTSX +FXSAVE64 SSE SSE FXSAVE64_MEMmfpxenv FXSAVE64 XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:X87_NOWAIT:X87_CONTROL:NOTSX +FXSAVE SSE SSE FXSAVE_MEMmfpxenv FXSAVE XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:X87_NOWAIT:X87_CONTROL:NOTSX +FXTRACT X87 X87_ALU FXTRACT X87 NOTSX +FYL2X X87 X87_ALU FYL2X X87 NOTSX +FYL2XP1 X87 X87_ALU FYL2XP1 X87 NOTSX +GETSEC SMX SYSTEM GETSEC SMX PROTECTED_MODE:NOTSX +GF2P8AFFINEINVQB GFNI GFNI GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 GFNI REQUIRES_ALIGNMENT +GF2P8AFFINEINVQB GFNI GFNI GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 GFNI INVALID +GF2P8AFFINEQB GFNI GFNI GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 GFNI REQUIRES_ALIGNMENT +GF2P8AFFINEQB GFNI GFNI GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 GFNI INVALID +GF2P8MULB GFNI GFNI GF2P8MULB_XMMu8_MEMu8 GFNI REQUIRES_ALIGNMENT +GF2P8MULB GFNI GFNI GF2P8MULB_XMMu8_XMMu8 GFNI INVALID +HADDPD SSE3 SSE HADDPD_XMMpd_MEMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HADDPD SSE3 SSE HADDPD_XMMpd_XMMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HADDPS SSE3 SSE HADDPS_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT:MXCSR +HADDPS SSE3 SSE HADDPS_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT:MXCSR +HLT BASE SYSTEM HLT I86 RING0:NOTSX +HRESET HRESET HRESET HRESET_IMM8 HRESET INVALID +HSUBPD SSE3 SSE HSUBPD_XMMpd_MEMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HSUBPD SSE3 SSE HSUBPD_XMMpd_XMMpd SSE3 REQUIRES_ALIGNMENT:MXCSR +HSUBPS SSE3 SSE HSUBPS_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT:MXCSR +HSUBPS SSE3 SSE HSUBPS_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT:MXCSR +IDIV BASE BINARY IDIV_GPR8 I86 BYTEOP +IDIV BASE BINARY IDIV_GPRv I86 SCALABLE +IDIV BASE BINARY IDIV_MEMb I86 BYTEOP +IDIV BASE BINARY IDIV_MEMv I86 SCALABLE +IMUL BASE BINARY IMUL_GPR8 I86 BYTEOP +IMUL BASE BINARY IMUL_GPRv I86 SCALABLE +IMUL BASE BINARY IMUL_GPRv_GPRv I86 SCALABLE +IMUL BASE BINARY IMUL_GPRv_GPRv_IMMb I186 SCALABLE +IMUL BASE BINARY IMUL_GPRv_GPRv_IMMz I186 SCALABLE +IMUL BASE BINARY IMUL_GPRv_MEMv I86 SCALABLE +IMUL BASE BINARY IMUL_GPRv_MEMv_IMMb I186 SCALABLE +IMUL BASE BINARY IMUL_GPRv_MEMv_IMMz I186 SCALABLE +IMUL BASE BINARY IMUL_MEMb I86 BYTEOP +IMUL BASE BINARY IMUL_MEMv I86 SCALABLE +INCSSPD CET CET INCSSPD_GPR32u8 CET INVALID +INCSSPQ CET CET INCSSPQ_GPR64u8 CET INVALID +INC BASE BINARY INC_GPR8 I86 BYTEOP +INC BASE BINARY INC_GPRv_40 I86 SCALABLE +INC BASE BINARY INC_GPRv_FFr0 I86 SCALABLE +INC_LOCK BASE BINARY INC_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +INC_LOCK BASE BINARY INC_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +INC BASE BINARY INC_MEMb I86 BYTEOP:LOCKABLE +INC BASE BINARY INC_MEMv I86 LOCKABLE:SCALABLE +INSB BASE IOSTRINGOP INSB I186 FIXED_BASE0:NOTSX:BYTEOP +INSD BASE IOSTRINGOP INSD I386 FIXED_BASE0:NOTSX +INSERTPS SSE4 SSE INSERTPS_XMMps_MEMd_IMMb SSE4 INVALID +INSERTPS SSE4 SSE INSERTPS_XMMps_XMMps_IMMb SSE4 INVALID +INSERTQ SSE4a BITBYTE INSERTQ_XMMq_XMMdq SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +INSERTQ SSE4a BITBYTE INSERTQ_XMMq_XMMq_IMMb_IMMb SSE4a ATT_OPERAND_ORDER_EXCEPTION:AMDONLY +INSW BASE IOSTRINGOP INSW I186 FIXED_BASE0:NOTSX +INT1 BASE INTERRUPT INT1 I86 INVALID +INT3 BASE INTERRUPT INT3 I86 NOTSX +INTO BASE INTERRUPT INTO I86 NOTSX +INT BASE INTERRUPT INT_IMMb I86 NOTSX +INVD BASE SYSTEM INVD I486REAL RING0:NOTSX +INVEPT VTX VTX INVEPT_GPR32_MEMdq VTX RING0:NOTSX +INVEPT VTX VTX INVEPT_GPR64_MEMdq VTX RING0:NOTSX +INVLPGA SVM SYSTEM INVLPGA_ArAX_ECX SVM PROTECTED_MODE:AMDONLY +INVLPGB AMD_INVLPGB SYSTEM INVLPGB_EAX_EDX_ECX AMD_INVLPGB AMDONLY +INVLPGB AMD_INVLPGB SYSTEM INVLPGB_RAX_EDX_ECX AMD_INVLPGB AMDONLY +INVLPG BASE SYSTEM INVLPG_MEMb I486REAL ATT_OPERAND_ORDER_EXCEPTION:BYTEOP:RING0:NOTSX +INVPCID INVPCID MISC INVPCID_GPR32_MEMdq INVPCID RING0:NOTSX +INVPCID INVPCID MISC INVPCID_GPR64_MEMdq INVPCID RING0:NOTSX +INVVPID VTX VTX INVVPID_GPR32_MEMdq VTX RING0:NOTSX +INVVPID VTX VTX INVVPID_GPR64_MEMdq VTX RING0:NOTSX +IN BASE IO IN_AL_DX I86 BYTEOP +IN BASE IO IN_AL_IMMb I86 BYTEOP:NOTSX +IN BASE IO IN_OeAX_DX I86 SCALABLE +IN BASE IO IN_OeAX_IMMb I86 NOTSX:SCALABLE +IRET BASE RET IRET I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +IRETD BASE RET IRETD I386 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +IRETQ LONGMODE RET IRETQ LONGMODE NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +JBE BASE COND_BR JBE_RELBRb I86 MPX_PREFIX_ABLE +JBE BASE COND_BR JBE_RELBRd I86 MPX_PREFIX_ABLE +JBE BASE COND_BR JBE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JB BASE COND_BR JB_RELBRb I86 MPX_PREFIX_ABLE +JB BASE COND_BR JB_RELBRd I86 MPX_PREFIX_ABLE +JB BASE COND_BR JB_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JCXZ BASE COND_BR JCXZ_RELBRb I386 INVALID +JECXZ BASE COND_BR JECXZ_RELBRb I386 INVALID +JLE BASE COND_BR JLE_RELBRb I86 MPX_PREFIX_ABLE +JLE BASE COND_BR JLE_RELBRd I86 MPX_PREFIX_ABLE +JLE BASE COND_BR JLE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JL BASE COND_BR JL_RELBRb I86 MPX_PREFIX_ABLE +JL BASE COND_BR JL_RELBRd I86 MPX_PREFIX_ABLE +JL BASE COND_BR JL_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JMP_FAR BASE UNCOND_BR JMP_FAR_MEMp2 I86 FAR_XFER:NOTSX:INDIRECT_BRANCH:SCALABLE +JMP_FAR BASE UNCOND_BR JMP_FAR_PTRp_IMMw I86 FAR_XFER:NOTSX:SCALABLE +JMP BASE UNCOND_BR JMP_GPRv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:SCALABLE +JMP BASE UNCOND_BR JMP_MEMv I86 MPX_PREFIX_ABLE:INDIRECT_BRANCH:SCALABLE +JMP BASE UNCOND_BR JMP_RELBRb I86 INVALID +JMP BASE UNCOND_BR JMP_RELBRd I86 MPX_PREFIX_ABLE +JMP BASE UNCOND_BR JMP_RELBRz I86 MPX_PREFIX_ABLE:SCALABLE +JNBE BASE COND_BR JNBE_RELBRb I86 MPX_PREFIX_ABLE +JNBE BASE COND_BR JNBE_RELBRd I86 MPX_PREFIX_ABLE +JNBE BASE COND_BR JNBE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNB BASE COND_BR JNB_RELBRb I86 MPX_PREFIX_ABLE +JNB BASE COND_BR JNB_RELBRd I86 MPX_PREFIX_ABLE +JNB BASE COND_BR JNB_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNLE BASE COND_BR JNLE_RELBRb I86 MPX_PREFIX_ABLE +JNLE BASE COND_BR JNLE_RELBRd I86 MPX_PREFIX_ABLE +JNLE BASE COND_BR JNLE_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNL BASE COND_BR JNL_RELBRb I86 MPX_PREFIX_ABLE +JNL BASE COND_BR JNL_RELBRd I86 MPX_PREFIX_ABLE +JNL BASE COND_BR JNL_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNO BASE COND_BR JNO_RELBRb I86 MPX_PREFIX_ABLE +JNO BASE COND_BR JNO_RELBRd I86 MPX_PREFIX_ABLE +JNO BASE COND_BR JNO_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNP BASE COND_BR JNP_RELBRb I86 MPX_PREFIX_ABLE +JNP BASE COND_BR JNP_RELBRd I86 MPX_PREFIX_ABLE +JNP BASE COND_BR JNP_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNS BASE COND_BR JNS_RELBRb I86 MPX_PREFIX_ABLE +JNS BASE COND_BR JNS_RELBRd I86 MPX_PREFIX_ABLE +JNS BASE COND_BR JNS_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JNZ BASE COND_BR JNZ_RELBRb I86 MPX_PREFIX_ABLE +JNZ BASE COND_BR JNZ_RELBRd I86 MPX_PREFIX_ABLE +JNZ BASE COND_BR JNZ_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JO BASE COND_BR JO_RELBRb I86 MPX_PREFIX_ABLE +JO BASE COND_BR JO_RELBRd I86 MPX_PREFIX_ABLE +JO BASE COND_BR JO_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JP BASE COND_BR JP_RELBRb I86 MPX_PREFIX_ABLE +JP BASE COND_BR JP_RELBRd I86 MPX_PREFIX_ABLE +JP BASE COND_BR JP_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JRCXZ BASE COND_BR JRCXZ_RELBRb LONGMODE INVALID +JS BASE COND_BR JS_RELBRb I86 MPX_PREFIX_ABLE +JS BASE COND_BR JS_RELBRd I86 MPX_PREFIX_ABLE +JS BASE COND_BR JS_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +JZ BASE COND_BR JZ_RELBRb I86 MPX_PREFIX_ABLE +JZ BASE COND_BR JZ_RELBRd I86 MPX_PREFIX_ABLE +JZ BASE COND_BR JZ_RELBRz I86 SCALABLE:MPX_PREFIX_ABLE:SCALABLE +KADDB AVX512VEX KMASK KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KADDD AVX512VEX KMASK KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KADDQ AVX512VEX KMASK KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KADDW AVX512VEX KMASK KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KANDB AVX512VEX KMASK KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KANDD AVX512VEX KMASK KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDNB AVX512VEX KMASK KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KANDND AVX512VEX KMASK KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDNQ AVX512VEX KMASK KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDNW AVX512VEX KMASK KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KANDQ AVX512VEX KMASK KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KANDW AVX512VEX KMASK KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_GPR32u32_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MASKmskw_GPR32u32_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MASKmskw_MASKu8_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MASKmskw_MEMu8_AVX512 AVX512DQ_KOP KMASK +KMOVB AVX512VEX KMASK KMOVB_MEMu8_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_GPR32u32_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MASKmskw_GPR32u32_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MASKmskw_MASKu32_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MASKmskw_MEMu32_AVX512 AVX512BW_KOP KMASK +KMOVD AVX512VEX KMASK KMOVD_MEMu32_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_GPR64u64_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MASKmskw_GPR64u64_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MASKmskw_MASKu64_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MASKmskw_MEMu64_AVX512 AVX512BW_KOP KMASK +KMOVQ AVX512VEX KMASK KMOVQ_MEMu64_MASKmskw_AVX512 AVX512BW_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_GPR32u32_MASKmskw_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MASKmskw_GPR32u32_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MASKmskw_MASKu16_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MASKmskw_MEMu16_AVX512 AVX512F_KOP KMASK +KMOVW AVX512VEX KMASK KMOVW_MEMu16_MASKmskw_AVX512 AVX512F_KOP KMASK +KNOTB AVX512VEX KMASK KNOTB_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KNOTD AVX512VEX KMASK KNOTD_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KNOTQ AVX512VEX KMASK KNOTQ_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KNOTW AVX512VEX KMASK KNOTW_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KORB AVX512VEX KMASK KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KORD AVX512VEX KMASK KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORQ AVX512VEX KMASK KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORTESTB AVX512VEX KMASK KORTESTB_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KORTESTD AVX512VEX KMASK KORTESTD_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORTESTQ AVX512VEX KMASK KORTESTQ_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KORTESTW AVX512VEX KMASK KORTESTW_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KORW AVX512VEX KMASK KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KSHIFTLB AVX512VEX KMASK KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 AVX512DQ_KOP KMASK +KSHIFTLD AVX512VEX KMASK KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTLQ AVX512VEX KMASK KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTLW AVX512VEX KMASK KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 AVX512F_KOP KMASK +KSHIFTRB AVX512VEX KMASK KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 AVX512DQ_KOP KMASK +KSHIFTRD AVX512VEX KMASK KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTRQ AVX512VEX KMASK KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 AVX512BW_KOP KMASK +KSHIFTRW AVX512VEX KMASK KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 AVX512F_KOP KMASK +KTESTB AVX512VEX KMASK KTESTB_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KTESTD AVX512VEX KMASK KTESTD_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KTESTQ AVX512VEX KMASK KTESTQ_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KTESTW AVX512VEX KMASK KTESTW_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KUNPCKBW AVX512VEX KMASK KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KUNPCKDQ AVX512VEX KMASK KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KUNPCKWD AVX512VEX KMASK KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXNORB AVX512VEX KMASK KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KXNORD AVX512VEX KMASK KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXNORQ AVX512VEX KMASK KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXNORW AVX512VEX KMASK KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +KXORB AVX512VEX KMASK KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512DQ_KOP KMASK +KXORD AVX512VEX KMASK KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXORQ AVX512VEX KMASK KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512BW_KOP KMASK +KXORW AVX512VEX KMASK KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 AVX512F_KOP KMASK +LAHF BASE FLAGOP LAHF LAHF INVALID +LAR BASE SYSTEM LAR_GPRv_GPRv I286PROTECTED PROTECTED_MODE:SCALABLE +LAR BASE SYSTEM LAR_GPRv_MEMw I286PROTECTED PROTECTED_MODE:SCALABLE +LDDQU SSE3 SSE LDDQU_XMMpd_MEMdq SSE3 INVALID +LDMXCSR SSE SSE LDMXCSR_MEMd SSEMXCSR MXCSR +LDS BASE SEGOP LDS_GPRz_MEMp I86 NOTSX:SCALABLE +LDTILECFG AMX_TILE AMX_TILE LDTILECFG_MEM AMX_TILE NOTSX +LEAVE BASE MISC LEAVE I186 FIXED_BASE0:SCALABLE +LEA BASE MISC LEA_GPRv_AGEN I86 SCALABLE +LES BASE SEGOP LES_GPRz_MEMp I86 NOTSX:SCALABLE +LFENCE SSE2 MISC LFENCE SSE2 IGNORES_OSFXSR +LFS BASE SEGOP LFS_GPRv_MEMp2 I386 NOTSX:SCALABLE +LGDT BASE SYSTEM LGDT_MEMs I286REAL NOTSX:SCALABLE +LGDT BASE SYSTEM LGDT_MEMs64 I286REAL NOTSX +LGS BASE SEGOP LGS_GPRv_MEMp2 I386 NOTSX:SCALABLE +LIDT BASE SYSTEM LIDT_MEMs I286REAL RING0:NOTSX:SCALABLE +LIDT BASE SYSTEM LIDT_MEMs64 I286REAL RING0:NOTSX +LLDT BASE SYSTEM LLDT_GPR16 I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LLDT BASE SYSTEM LLDT_MEMw I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LLWPCB XOP XOP LLWPCB_VGPRyy LWP AMDONLY:SCALABLE +LMSW BASE SYSTEM LMSW_GPR16 I286REAL RING0:NOTSX +LMSW BASE SYSTEM LMSW_MEMw I286REAL RING0:NOTSX +LOADIWKEY KEYLOCKER KEYLOCKER LOADIWKEY_XMMu8_XMMu8 KEYLOCKER INVALID +LODSB BASE STRINGOP LODSB I86 FIXED_BASE0:BYTEOP +LODSD BASE STRINGOP LODSD I386 FIXED_BASE0 +LODSQ LONGMODE STRINGOP LODSQ LONGMODE FIXED_BASE0 +LODSW BASE STRINGOP LODSW I86 FIXED_BASE0 +LOOPE BASE COND_BR LOOPE_RELBRb I86 INVALID +LOOPNE BASE COND_BR LOOPNE_RELBRb I86 INVALID +LOOP BASE COND_BR LOOP_RELBRb I86 INVALID +LSL BASE SYSTEM LSL_GPRv_GPRz I286PROTECTED PROTECTED_MODE:SCALABLE +LSL BASE SYSTEM LSL_GPRv_MEMw I286PROTECTED PROTECTED_MODE:SCALABLE +LSS BASE SEGOP LSS_GPRv_MEMp2 I386 NOTSX:SCALABLE +LTR BASE SYSTEM LTR_GPR16 I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LTR BASE SYSTEM LTR_MEMw I286PROTECTED PROTECTED_MODE:RING0:NOTSX +LWPINS XOP XOP LWPINS_VGPRyy_MEMd_IMMd LWP AMDONLY:SCALABLE +LWPINS XOP XOP LWPINS_VGPRyy_VGPR32y_IMMd LWP AMDONLY:SCALABLE +LWPVAL XOP XOP LWPVAL_VGPRyy_MEMd_IMMd LWP AMDONLY:SCALABLE +LWPVAL XOP XOP LWPVAL_VGPRyy_VGPR32y_IMMd LWP AMDONLY:SCALABLE +LZCNT LZCNT LZCNT LZCNT_GPRv_GPRv LZCNT SCALABLE +LZCNT LZCNT LZCNT LZCNT_GPRv_MEMv LZCNT SCALABLE +MASKMOVDQU SSE2 DATAXFER MASKMOVDQU_XMMdq_XMMdq SSE2 FIXED_BASE0:MASKOP:NOTSX:NONTEMPORAL +MASKMOVQ MMX DATAXFER MASKMOVQ_MMXq_MMXq PENTIUMMMX FIXED_BASE0:MASKOP:NOTSX:NONTEMPORAL +MAXPD SSE2 SSE MAXPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MXCSR +MAXPD SSE2 SSE MAXPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR:MXCSR +MAXPS SSE SSE MAXPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +MAXPS SSE SSE MAXPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +MAXSD SSE2 SSE MAXSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +MAXSD SSE2 SSE MAXSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +MAXSS SSE SSE MAXSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +MAXSS SSE SSE MAXSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +MCOMMIT MCOMMIT MISC MCOMMIT MCOMMIT AMDONLY +MFENCE SSE2 MISC MFENCE SSE2 IGNORES_OSFXSR +MINPD SSE2 SSE MINPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MINPD SSE2 SSE MINPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MINPS SSE SSE MINPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +MINPS SSE SSE MINPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +MINSD SSE2 SSE MINSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +MINSD SSE2 SSE MINSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +MINSS SSE SSE MINSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +MINSS SSE SSE MINSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +MONITOR MONITOR MISC MONITOR MONITOR RING0:NOTSX +MONITORX MONITORX MISC MONITORX MONITORX AMDONLY +MOVAPD SSE2 DATAXFER MOVAPD_MEMpd_XMMpd SSE2 REQUIRES_ALIGNMENT +MOVAPD SSE2 DATAXFER MOVAPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT +MOVAPD SSE2 DATAXFER MOVAPD_XMMpd_XMMpd_0F28 SSE2 REQUIRES_ALIGNMENT +MOVAPD SSE2 DATAXFER MOVAPD_XMMpd_XMMpd_0F29 SSE2 REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_MEMps_XMMps SSE REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_XMMps_XMMps_0F28 SSE REQUIRES_ALIGNMENT +MOVAPS SSE DATAXFER MOVAPS_XMMps_XMMps_0F29 SSE REQUIRES_ALIGNMENT +MOVBE MOVBE DATAXFER MOVBE_GPRv_MEMv MOVBE SCALABLE +MOVBE MOVBE DATAXFER MOVBE_MEMv_GPRv MOVBE SCALABLE +MOVDDUP SSE3 DATAXFER MOVDDUP_XMMdq_MEMq SSE3 INVALID +MOVDDUP SSE3 DATAXFER MOVDDUP_XMMdq_XMMq SSE3 INVALID +MOVDIR64B MOVDIR MOVDIR MOVDIR64B_GPRa_MEM MOVDIR REQUIRES_ALIGNMENT +MOVDIRI MOVDIR MOVDIR MOVDIRI_MEMu32_GPR32u32 MOVDIR INVALID +MOVDIRI MOVDIR MOVDIR MOVDIRI_MEMu64_GPR64u64 MOVDIR INVALID +MOVDQ2Q SSE2 DATAXFER MOVDQ2Q_MMXq_XMMq SSE2 MMX_EXCEPT:NOTSX +MOVDQA SSE2 DATAXFER MOVDQA_MEMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +MOVDQA SSE2 DATAXFER MOVDQA_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +MOVDQA SSE2 DATAXFER MOVDQA_XMMdq_XMMdq_0F6F SSE2 REQUIRES_ALIGNMENT +MOVDQA SSE2 DATAXFER MOVDQA_XMMdq_XMMdq_0F7F SSE2 REQUIRES_ALIGNMENT +MOVDQU SSE2 DATAXFER MOVDQU_MEMdq_XMMdq SSE2 INVALID +MOVDQU SSE2 DATAXFER MOVDQU_XMMdq_MEMdq SSE2 INVALID +MOVDQU SSE2 DATAXFER MOVDQU_XMMdq_XMMdq_0F6F SSE2 INVALID +MOVDQU SSE2 DATAXFER MOVDQU_XMMdq_XMMdq_0F7F SSE2 INVALID +MOVD MMX DATAXFER MOVD_GPR32_MMXd PENTIUMMMX NOTSX +MOVD SSE2 DATAXFER MOVD_GPR32_XMMd SSE2 INVALID +MOVD MMX DATAXFER MOVD_MEMd_MMXd PENTIUMMMX NOTSX +MOVD SSE2 DATAXFER MOVD_MEMd_XMMd SSE2 INVALID +MOVD MMX DATAXFER MOVD_MMXq_GPR32 PENTIUMMMX NOTSX +MOVD MMX DATAXFER MOVD_MMXq_MEMd PENTIUMMMX NOTSX +MOVD SSE2 DATAXFER MOVD_XMMdq_GPR32 SSE2 INVALID +MOVD SSE2 DATAXFER MOVD_XMMdq_MEMd SSE2 INVALID +MOVHLPS SSE DATAXFER MOVHLPS_XMMq_XMMq SSE INVALID +MOVHPD SSE2 DATAXFER MOVHPD_MEMq_XMMsd SSE2 INVALID +MOVHPD SSE2 DATAXFER MOVHPD_XMMsd_MEMq SSE2 INVALID +MOVHPS SSE DATAXFER MOVHPS_MEMq_XMMps SSE INVALID +MOVHPS SSE DATAXFER MOVHPS_XMMq_MEMq SSE INVALID +MOVLHPS SSE DATAXFER MOVLHPS_XMMq_XMMq SSE INVALID +MOVLPD SSE2 DATAXFER MOVLPD_MEMq_XMMsd SSE2 INVALID +MOVLPD SSE2 DATAXFER MOVLPD_XMMsd_MEMq SSE2 INVALID +MOVLPS SSE DATAXFER MOVLPS_MEMq_XMMq SSE INVALID +MOVLPS SSE DATAXFER MOVLPS_XMMq_MEMq SSE INVALID +MOVMSKPD SSE2 DATAXFER MOVMSKPD_GPR32_XMMpd SSE2 INVALID +MOVMSKPS SSE DATAXFER MOVMSKPS_GPR32_XMMps SSE INVALID +MOVNTDQA SSE4 SSE MOVNTDQA_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +MOVNTDQ SSE2 DATAXFER MOVNTDQ_MEMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +MOVNTI SSE2 DATAXFER MOVNTI_MEMd_GPR32 SSE2 IGNORES_OSFXSR:NOTSX:NONTEMPORAL +MOVNTI SSE2 DATAXFER MOVNTI_MEMq_GPR64 SSE2 IGNORES_OSFXSR:NOTSX:NONTEMPORAL +MOVNTPD SSE2 DATAXFER MOVNTPD_MEMdq_XMMpd SSE2 NOTSX:REQUIRES_ALIGNMENT:NONTEMPORAL +MOVNTPS SSE DATAXFER MOVNTPS_MEMdq_XMMps SSE NOTSX:REQUIRES_ALIGNMENT:NONTEMPORAL +MOVNTQ MMX DATAXFER MOVNTQ_MEMq_MMXq PENTIUMMMX NOTSX:NONTEMPORAL +MOVNTSD SSE4a DATAXFER MOVNTSD_MEMq_XMMq SSE4a NONTEMPORAL:AMDONLY +MOVNTSS SSE4a DATAXFER MOVNTSS_MEMd_XMMd SSE4a NONTEMPORAL:AMDONLY +MOVQ2DQ SSE2 DATAXFER MOVQ2DQ_XMMdq_MMXq SSE2 MMX_EXCEPT:NOTSX +MOVQ MMX DATAXFER MOVQ_GPR64_MMXq PENTIUMMMX NOTSX +MOVQ SSE2 DATAXFER MOVQ_GPR64_XMMq SSE2 INVALID +MOVQ MMX DATAXFER MOVQ_MEMq_MMXq_0F7E PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MEMq_MMXq_0F7F PENTIUMMMX NOTSX +MOVQ SSE2 DATAXFER MOVQ_MEMq_XMMq_0F7E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_MEMq_XMMq_0FD6 SSE2 INVALID +MOVQ MMX DATAXFER MOVQ_MMXq_GPR64 PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MEMq_0F6E PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MEMq_0F6F PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MMXq_0F6F PENTIUMMMX NOTSX +MOVQ MMX DATAXFER MOVQ_MMXq_MMXq_0F7F PENTIUMMMX NOTSX +MOVQ SSE2 DATAXFER MOVQ_XMMdq_GPR64 SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_MEMq_0F6E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_MEMq_0F7E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_XMMq_0F7E SSE2 INVALID +MOVQ SSE2 DATAXFER MOVQ_XMMdq_XMMq_0FD6 SSE2 INVALID +MOVSB BASE STRINGOP MOVSB I86 FIXED_BASE0:FIXED_BASE1:BYTEOP +MOVSD BASE STRINGOP MOVSD I386 FIXED_BASE0:FIXED_BASE1 +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_MEMsd_XMMsd SSE2 SIMD_SCALAR +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_XMMdq_MEMsd SSE2 SIMD_SCALAR +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_XMMsd_XMMsd_0F10 SSE2 SIMD_SCALAR +MOVSD_XMM SSE2 DATAXFER MOVSD_XMM_XMMsd_XMMsd_0F11 SSE2 SIMD_SCALAR +MOVSHDUP SSE3 DATAXFER MOVSHDUP_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT +MOVSHDUP SSE3 DATAXFER MOVSHDUP_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT +MOVSLDUP SSE3 DATAXFER MOVSLDUP_XMMps_MEMps SSE3 REQUIRES_ALIGNMENT +MOVSLDUP SSE3 DATAXFER MOVSLDUP_XMMps_XMMps SSE3 REQUIRES_ALIGNMENT +MOVSQ LONGMODE STRINGOP MOVSQ LONGMODE FIXED_BASE0:FIXED_BASE1 +MOVSS SSE DATAXFER MOVSS_MEMss_XMMss SSE SIMD_SCALAR +MOVSS SSE DATAXFER MOVSS_XMMdq_MEMss SSE SIMD_SCALAR +MOVSS SSE DATAXFER MOVSS_XMMss_XMMss_0F10 SSE SIMD_SCALAR +MOVSS SSE DATAXFER MOVSS_XMMss_XMMss_0F11 SSE SIMD_SCALAR +MOVSW BASE STRINGOP MOVSW I86 FIXED_BASE0:FIXED_BASE1 +MOVSXD LONGMODE DATAXFER MOVSXD_GPRv_GPRz LONGMODE SCALABLE +MOVSXD LONGMODE DATAXFER MOVSXD_GPRv_MEMz LONGMODE SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_GPR16 I386 SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_GPR8 I386 SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_MEMb I386 SCALABLE +MOVSX BASE DATAXFER MOVSX_GPRv_MEMw I386 SCALABLE +MOVUPD SSE2 DATAXFER MOVUPD_MEMpd_XMMpd SSE2 INVALID +MOVUPD SSE2 DATAXFER MOVUPD_XMMpd_MEMpd SSE2 INVALID +MOVUPD SSE2 DATAXFER MOVUPD_XMMpd_XMMpd_0F10 SSE2 INVALID +MOVUPD SSE2 DATAXFER MOVUPD_XMMpd_XMMpd_0F11 SSE2 INVALID +MOVUPS SSE DATAXFER MOVUPS_MEMps_XMMps SSE INVALID +MOVUPS SSE DATAXFER MOVUPS_XMMps_MEMps SSE INVALID +MOVUPS SSE DATAXFER MOVUPS_XMMps_XMMps_0F10 SSE INVALID +MOVUPS SSE DATAXFER MOVUPS_XMMps_XMMps_0F11 SSE INVALID +MOVZX BASE DATAXFER MOVZX_GPRv_GPR16 I386 SCALABLE +MOVZX BASE DATAXFER MOVZX_GPRv_GPR8 I386 SCALABLE +MOVZX BASE DATAXFER MOVZX_GPRv_MEMb I386 SCALABLE +MOVZX BASE DATAXFER MOVZX_GPRv_MEMw I386 SCALABLE +MOV BASE DATAXFER MOV_AL_MEMb I86 FIXED_BASE0:BYTEOP +MOV_CR BASE DATAXFER MOV_CR_CR_GPR32 I86 RING0:NOTSX +MOV_CR BASE DATAXFER MOV_CR_CR_GPR64 I86 RING0:NOTSX +MOV_CR BASE DATAXFER MOV_CR_GPR32_CR I86 RING0 +MOV_CR BASE DATAXFER MOV_CR_GPR64_CR I86 RING0 +MOV_DR BASE DATAXFER MOV_DR_DR_GPR32 I86 RING0:NOTSX +MOV_DR BASE DATAXFER MOV_DR_DR_GPR64 I86 RING0:NOTSX +MOV_DR BASE DATAXFER MOV_DR_GPR32_DR I86 RING0 +MOV_DR BASE DATAXFER MOV_DR_GPR64_DR I86 RING0 +MOV BASE DATAXFER MOV_GPR8_GPR8_88 I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_GPR8_8A I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_IMMb_B0 I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_IMMb_C6r0 I86 BYTEOP +MOV BASE DATAXFER MOV_GPR8_MEMb I86 BYTEOP +MOV BASE DATAXFER MOV_GPRv_GPRv_89 I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_GPRv_8B I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_IMMv I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_IMMz I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_MEMv I86 SCALABLE +MOV BASE DATAXFER MOV_GPRv_SEG I86 SCALABLE +MOV BASE DATAXFER MOV_MEMb_AL I86 FIXED_BASE0:BYTEOP +MOV BASE DATAXFER MOV_MEMb_GPR8 I86 BYTEOP:HLE_REL_ABLE +MOV BASE DATAXFER MOV_MEMb_IMMb I86 BYTEOP:HLE_REL_ABLE +MOV BASE DATAXFER MOV_MEMv_GPRv I86 HLE_REL_ABLE:SCALABLE +MOV BASE DATAXFER MOV_MEMv_IMMz I86 HLE_REL_ABLE:SCALABLE +MOV BASE DATAXFER MOV_MEMv_OrAX I86 FIXED_BASE0:SCALABLE +MOV BASE DATAXFER MOV_MEMw_SEG I86 INVALID +MOV BASE DATAXFER MOV_OrAX_MEMv I86 FIXED_BASE0:SCALABLE +MOV BASE DATAXFER MOV_SEG_GPR16 I86 NOTSX +MOV BASE DATAXFER MOV_SEG_MEMw I86 NOTSX +MPSADBW SSE4 SSE MPSADBW_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +MPSADBW SSE4 SSE MPSADBW_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +MULPD SSE2 SSE MULPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MULPD SSE2 SSE MULPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +MULPS SSE SSE MULPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +MULPS SSE SSE MULPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +MULSD SSE2 SSE MULSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +MULSD SSE2 SSE MULSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +MULSS SSE SSE MULSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +MULSS SSE SSE MULSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +MULX BMI2 BMI2 MULX_VGPR32d_VGPR32d_MEMd BMI2 INVALID +MULX BMI2 BMI2 MULX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +MULX BMI2 BMI2 MULX_VGPR64q_VGPR64q_MEMq BMI2 INVALID +MULX BMI2 BMI2 MULX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +MUL BASE BINARY MUL_GPR8 I86 BYTEOP +MUL BASE BINARY MUL_GPRv I86 SCALABLE +MUL BASE BINARY MUL_MEMb I86 BYTEOP +MUL BASE BINARY MUL_MEMv I86 SCALABLE +MWAIT MONITOR MISC MWAIT MONITOR RING0:NOTSX +MWAITX MONITORX MISC MWAITX MONITORX AMDONLY +NEG BASE BINARY NEG_GPR8 I86 BYTEOP +NEG BASE BINARY NEG_GPRv I86 SCALABLE +NEG_LOCK BASE BINARY NEG_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +NEG_LOCK BASE BINARY NEG_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +NEG BASE BINARY NEG_MEMb I86 BYTEOP:LOCKABLE +NEG BASE BINARY NEG_MEMv I86 LOCKABLE:SCALABLE +NOP BASE NOP NOP_90 I86 NOP +NOP BASE WIDENOP NOP_GPRv_0F18r0 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r1 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r2 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r3 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r4 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r5 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r6 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_0F18r7 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F0D PREFETCH_NOP SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F19 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1A PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1B PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1C PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1D FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1E PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_GPRv_0F1F FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_MEM_0F1B PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_GPRv_MEMv_0F1A PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r4 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r5 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r6 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_0F18r7 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F19 FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1C PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1D FAT_NOP NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1E PPRO NOP:SCALABLE +NOP BASE WIDENOP NOP_MEMv_GPRv_0F1F FAT_NOP NOP:SCALABLE +NOT BASE LOGICAL NOT_GPR8 I86 BYTEOP +NOT BASE LOGICAL NOT_GPRv I86 SCALABLE +NOT_LOCK BASE LOGICAL NOT_LOCK_MEMb I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +NOT_LOCK BASE LOGICAL NOT_LOCK_MEMv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +NOT BASE LOGICAL NOT_MEMb I86 BYTEOP:LOCKABLE +NOT BASE LOGICAL NOT_MEMv I86 LOCKABLE:SCALABLE +ORPD SSE2 LOGICAL_FP ORPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +ORPD SSE2 LOGICAL_FP ORPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +ORPS SSE LOGICAL_FP ORPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +ORPS SSE LOGICAL_FP ORPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +OR BASE LOGICAL OR_AL_IMMb I86 BYTEOP +OR BASE LOGICAL OR_GPR8_GPR8_08 I86 BYTEOP +OR BASE LOGICAL OR_GPR8_GPR8_0A I86 BYTEOP +OR BASE LOGICAL OR_GPR8_IMMb_80r1 I86 BYTEOP +OR BASE LOGICAL OR_GPR8_IMMb_82r1 I86 BYTEOP +OR BASE LOGICAL OR_GPR8_MEMb I86 BYTEOP +OR BASE LOGICAL OR_GPRv_GPRv_09 I86 SCALABLE +OR BASE LOGICAL OR_GPRv_GPRv_0B I86 SCALABLE +OR BASE LOGICAL OR_GPRv_IMMb I86 SCALABLE +OR BASE LOGICAL OR_GPRv_IMMz I86 SCALABLE +OR BASE LOGICAL OR_GPRv_MEMv I86 SCALABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMb_IMMb_80r1 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMb_IMMb_82r1 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +OR_LOCK BASE LOGICAL OR_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +OR BASE LOGICAL OR_MEMb_GPR8 I86 BYTEOP:LOCKABLE +OR BASE LOGICAL OR_MEMb_IMMb_80r1 I86 BYTEOP:LOCKABLE +OR BASE LOGICAL OR_MEMb_IMMb_82r1 I86 BYTEOP:LOCKABLE +OR BASE LOGICAL OR_MEMv_GPRv I86 LOCKABLE:SCALABLE +OR BASE LOGICAL OR_MEMv_IMMb I86 LOCKABLE:SCALABLE +OR BASE LOGICAL OR_MEMv_IMMz I86 LOCKABLE:SCALABLE +OR BASE LOGICAL OR_OrAX_IMMz I86 SCALABLE +OUTSB BASE IOSTRINGOP OUTSB I186 FIXED_BASE0:NOTSX:BYTEOP +OUTSD BASE IOSTRINGOP OUTSD I386 FIXED_BASE0:NOTSX +OUTSW BASE IOSTRINGOP OUTSW I186 FIXED_BASE0:NOTSX +OUT BASE IO OUT_DX_AL I86 BYTEOP +OUT BASE IO OUT_DX_OeAX I86 SCALABLE +OUT BASE IO OUT_IMMb_AL I86 NOTSX:BYTEOP +OUT BASE IO OUT_IMMb_OeAX I86 NOTSX:SCALABLE +PABSB SSSE3 MMX PABSB_MMXq_MEMq SSSE3MMX NOTSX +PABSB SSSE3 MMX PABSB_MMXq_MMXq SSSE3MMX NOTSX +PABSB SSSE3 SSE PABSB_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PABSB SSSE3 SSE PABSB_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PABSD SSSE3 MMX PABSD_MMXq_MEMq SSSE3MMX SIMD_SCALAR:NOTSX +PABSD SSSE3 MMX PABSD_MMXq_MMXq SSSE3MMX SIMD_SCALAR:NOTSX +PABSD SSSE3 SSE PABSD_XMMdq_MEMdq SSSE3 SIMD_SCALAR:REQUIRES_ALIGNMENT +PABSD SSSE3 SSE PABSD_XMMdq_XMMdq SSSE3 SIMD_SCALAR +PABSW SSSE3 MMX PABSW_MMXq_MEMq SSSE3MMX NOTSX +PABSW SSSE3 MMX PABSW_MMXq_MMXq SSSE3MMX NOTSX +PABSW SSSE3 SSE PABSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PABSW SSSE3 SSE PABSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PACKSSDW MMX MMX PACKSSDW_MMXq_MEMq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSDW MMX MMX PACKSSDW_MMXq_MMXq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSDW SSE2 SSE PACKSSDW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKSSDW SSE2 SSE PACKSSDW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKSSWB MMX MMX PACKSSWB_MMXq_MEMq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSWB MMX MMX PACKSSWB_MMXq_MMXq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKSSWB SSE2 SSE PACKSSWB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKSSWB SSE2 SSE PACKSSWB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSDW SSE4 SSE PACKUSDW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSDW SSE4 SSE PACKUSDW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSWB MMX MMX PACKUSWB_MMXq_MEMq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKUSWB MMX MMX PACKUSWB_MMXq_MMXq PENTIUMMMX HALF_WIDE_OUTPUT:NOTSX +PACKUSWB SSE2 SSE PACKUSWB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PACKUSWB SSE2 SSE PACKUSWB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT:HALF_WIDE_OUTPUT +PADDB MMX MMX PADDB_MMXq_MEMq PENTIUMMMX NOTSX +PADDB MMX MMX PADDB_MMXq_MMXq PENTIUMMMX NOTSX +PADDB SSE2 SSE PADDB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDB SSE2 SSE PADDB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDD MMX MMX PADDD_MMXq_MEMq PENTIUMMMX NOTSX +PADDD MMX MMX PADDD_MMXq_MMXq PENTIUMMMX NOTSX +PADDD SSE2 SSE PADDD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDD SSE2 SSE PADDD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDQ SSE2 MMX PADDQ_MMXq_MEMq SSE2MMX NOTSX +PADDQ SSE2 MMX PADDQ_MMXq_MMXq SSE2MMX NOTSX +PADDQ SSE2 SSE PADDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDQ SSE2 SSE PADDQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDSB MMX MMX PADDSB_MMXq_MEMq PENTIUMMMX NOTSX +PADDSB MMX MMX PADDSB_MMXq_MMXq PENTIUMMMX NOTSX +PADDSB SSE2 SSE PADDSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDSB SSE2 SSE PADDSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDSW MMX MMX PADDSW_MMXq_MEMq PENTIUMMMX NOTSX +PADDSW MMX MMX PADDSW_MMXq_MMXq PENTIUMMMX NOTSX +PADDSW SSE2 SSE PADDSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDSW SSE2 SSE PADDSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDUSB MMX MMX PADDUSB_MMXq_MEMq PENTIUMMMX NOTSX +PADDUSB MMX MMX PADDUSB_MMXq_MMXq PENTIUMMMX NOTSX +PADDUSB SSE2 SSE PADDUSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDUSB SSE2 SSE PADDUSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDUSW MMX MMX PADDUSW_MMXq_MEMq PENTIUMMMX NOTSX +PADDUSW MMX MMX PADDUSW_MMXq_MMXq PENTIUMMMX NOTSX +PADDUSW SSE2 SSE PADDUSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDUSW SSE2 SSE PADDUSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PADDW MMX MMX PADDW_MMXq_MEMq PENTIUMMMX NOTSX +PADDW MMX MMX PADDW_MMXq_MMXq PENTIUMMMX NOTSX +PADDW SSE2 SSE PADDW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PADDW SSE2 SSE PADDW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PALIGNR SSSE3 MMX PALIGNR_MMXq_MEMq_IMMb SSSE3MMX NOTSX +PALIGNR SSSE3 MMX PALIGNR_MMXq_MMXq_IMMb SSSE3MMX NOTSX +PALIGNR SSSE3 SSE PALIGNR_XMMdq_MEMdq_IMMb SSSE3 REQUIRES_ALIGNMENT +PALIGNR SSSE3 SSE PALIGNR_XMMdq_XMMdq_IMMb SSSE3 REQUIRES_ALIGNMENT +PANDN MMX LOGICAL PANDN_MMXq_MEMq PENTIUMMMX NOTSX +PANDN MMX LOGICAL PANDN_MMXq_MMXq PENTIUMMMX NOTSX +PANDN SSE2 LOGICAL PANDN_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PANDN SSE2 LOGICAL PANDN_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PAND MMX LOGICAL PAND_MMXq_MEMq PENTIUMMMX NOTSX +PAND MMX LOGICAL PAND_MMXq_MMXq PENTIUMMMX NOTSX +PAND SSE2 LOGICAL PAND_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PAND SSE2 LOGICAL PAND_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PAUSE PAUSE MISC PAUSE PAUSE NOTSX +PAVGB MMX MMX PAVGB_MMXq_MEMq PENTIUMMMX NOTSX +PAVGB MMX MMX PAVGB_MMXq_MMXq PENTIUMMMX NOTSX +PAVGB SSE2 SSE PAVGB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PAVGB SSE2 SSE PAVGB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PAVGUSB 3DNOW 3DNOW PAVGUSB_MMXq_MEMq 3DNOW AMDONLY +PAVGUSB 3DNOW 3DNOW PAVGUSB_MMXq_MMXq 3DNOW AMDONLY +PAVGW MMX MMX PAVGW_MMXq_MEMq PENTIUMMMX NOTSX +PAVGW MMX MMX PAVGW_MMXq_MMXq PENTIUMMMX NOTSX +PAVGW SSE2 SSE PAVGW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PAVGW SSE2 SSE PAVGW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PBLENDVB SSE4 SSE PBLENDVB_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PBLENDVB SSE4 SSE PBLENDVB_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PBLENDW SSE4 SSE PBLENDW_XMMdq_MEMdq_IMMb SSE4 REQUIRES_ALIGNMENT +PBLENDW SSE4 SSE PBLENDW_XMMdq_XMMdq_IMMb SSE4 REQUIRES_ALIGNMENT +PCLMULQDQ PCLMULQDQ PCLMULQDQ PCLMULQDQ_XMMdq_MEMdq_IMMb PCLMULQDQ REQUIRES_ALIGNMENT +PCLMULQDQ PCLMULQDQ PCLMULQDQ PCLMULQDQ_XMMdq_XMMdq_IMMb PCLMULQDQ REQUIRES_ALIGNMENT +PCMPEQB MMX MMX PCMPEQB_MMXq_MEMq PENTIUMMMX NOTSX +PCMPEQB MMX MMX PCMPEQB_MMXq_MMXq PENTIUMMMX NOTSX +PCMPEQB SSE2 SSE PCMPEQB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQB SSE2 SSE PCMPEQB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQD MMX MMX PCMPEQD_MMXq_MEMq PENTIUMMMX NOTSX +PCMPEQD MMX MMX PCMPEQD_MMXq_MMXq PENTIUMMMX NOTSX +PCMPEQD SSE2 SSE PCMPEQD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQD SSE2 SSE PCMPEQD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQQ SSE4 SSE PCMPEQQ_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PCMPEQQ SSE4 SSE PCMPEQQ_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PCMPEQW MMX MMX PCMPEQW_MMXq_MEMq PENTIUMMMX NOTSX +PCMPEQW MMX MMX PCMPEQW_MMXq_MMXq PENTIUMMMX NOTSX +PCMPEQW SSE2 SSE PCMPEQW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPEQW SSE2 SSE PCMPEQW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPESTRI64 SSE4 SSE PCMPESTRI64_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRI64 SSE4 SSE PCMPESTRI64_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPESTRI SSE4 SSE PCMPESTRI_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRI SSE4 SSE PCMPESTRI_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPESTRM64 SSE4 SSE PCMPESTRM64_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRM64 SSE4 SSE PCMPESTRM64_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPESTRM SSE4 SSE PCMPESTRM_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPESTRM SSE4 SSE PCMPESTRM_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPGTB MMX MMX PCMPGTB_MMXq_MEMq PENTIUMMMX NOTSX +PCMPGTB MMX MMX PCMPGTB_MMXq_MMXq PENTIUMMMX NOTSX +PCMPGTB SSE2 SSE PCMPGTB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTB SSE2 SSE PCMPGTB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTD MMX MMX PCMPGTD_MMXq_MEMq PENTIUMMMX NOTSX +PCMPGTD MMX MMX PCMPGTD_MMXq_MMXq PENTIUMMMX NOTSX +PCMPGTD SSE2 SSE PCMPGTD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTD SSE2 SSE PCMPGTD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTQ SSE4 SSE PCMPGTQ_XMMdq_MEMdq SSE42 REQUIRES_ALIGNMENT +PCMPGTQ SSE4 SSE PCMPGTQ_XMMdq_XMMdq SSE42 REQUIRES_ALIGNMENT +PCMPGTW MMX MMX PCMPGTW_MMXq_MEMq PENTIUMMMX NOTSX +PCMPGTW MMX MMX PCMPGTW_MMXq_MMXq PENTIUMMMX NOTSX +PCMPGTW SSE2 SSE PCMPGTW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PCMPGTW SSE2 SSE PCMPGTW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PCMPISTRI64 SSE4 SSE PCMPISTRI64_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPISTRI64 SSE4 SSE PCMPISTRI64_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPISTRI SSE4 SSE PCMPISTRI_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPISTRI SSE4 SSE PCMPISTRI_XMMdq_XMMdq_IMMb SSE42 INVALID +PCMPISTRM SSE4 SSE PCMPISTRM_XMMdq_MEMdq_IMMb SSE42 INVALID +PCMPISTRM SSE4 SSE PCMPISTRM_XMMdq_XMMdq_IMMb SSE42 INVALID +PCONFIG PCONFIG PCONFIG PCONFIG PCONFIG INVALID +PCONFIG PCONFIG PCONFIG PCONFIG64 PCONFIG INVALID +PDEP BMI2 BMI2 PDEP_VGPR32d_VGPR32d_MEMd BMI2 INVALID +PDEP BMI2 BMI2 PDEP_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +PDEP BMI2 BMI2 PDEP_VGPR64q_VGPR64q_MEMq BMI2 INVALID +PDEP BMI2 BMI2 PDEP_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +PEXTRB SSE4 SSE PEXTRB_GPR32d_XMMdq_IMMb SSE4 INVALID +PEXTRB SSE4 SSE PEXTRB_MEMb_XMMdq_IMMb SSE4 INVALID +PEXTRD SSE4 SSE PEXTRD_GPR32d_XMMdq_IMMb SSE4 INVALID +PEXTRD SSE4 SSE PEXTRD_MEMd_XMMdq_IMMb SSE4 INVALID +PEXTRQ SSE4 SSE PEXTRQ_GPR64q_XMMdq_IMMb SSE4 INVALID +PEXTRQ SSE4 SSE PEXTRQ_MEMq_XMMdq_IMMb SSE4 INVALID +PEXTRW MMX MMX PEXTRW_GPR32_MMXq_IMMb PENTIUMMMX NOTSX +PEXTRW SSE2 SSE PEXTRW_GPR32_XMMdq_IMMb SSE2 INVALID +PEXTRW_SSE4 SSE4 SSE PEXTRW_SSE4_GPR32_XMMdq_IMMb SSE4 INVALID +PEXTRW_SSE4 SSE4 SSE PEXTRW_SSE4_MEMw_XMMdq_IMMb SSE4 INVALID +PEXT BMI2 BMI2 PEXT_VGPR32d_VGPR32d_MEMd BMI2 INVALID +PEXT BMI2 BMI2 PEXT_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +PEXT BMI2 BMI2 PEXT_VGPR64q_VGPR64q_MEMq BMI2 INVALID +PEXT BMI2 BMI2 PEXT_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +PF2ID 3DNOW 3DNOW PF2ID_MMXq_MEMq 3DNOW AMDONLY +PF2ID 3DNOW 3DNOW PF2ID_MMXq_MMXq 3DNOW AMDONLY +PF2IW 3DNOW 3DNOW PF2IW_MMXq_MEMq 3DNOW AMDONLY +PF2IW 3DNOW 3DNOW PF2IW_MMXq_MMXq 3DNOW AMDONLY +PFACC 3DNOW 3DNOW PFACC_MMXq_MEMq 3DNOW AMDONLY +PFACC 3DNOW 3DNOW PFACC_MMXq_MMXq 3DNOW AMDONLY +PFADD 3DNOW 3DNOW PFADD_MMXq_MEMq 3DNOW AMDONLY +PFADD 3DNOW 3DNOW PFADD_MMXq_MMXq 3DNOW AMDONLY +PFCMPEQ 3DNOW 3DNOW PFCMPEQ_MMXq_MEMq 3DNOW AMDONLY +PFCMPEQ 3DNOW 3DNOW PFCMPEQ_MMXq_MMXq 3DNOW AMDONLY +PFCMPGE 3DNOW 3DNOW PFCMPGE_MMXq_MEMq 3DNOW AMDONLY +PFCMPGE 3DNOW 3DNOW PFCMPGE_MMXq_MMXq 3DNOW AMDONLY +PFCMPGT 3DNOW 3DNOW PFCMPGT_MMXq_MEMq 3DNOW AMDONLY +PFCMPGT 3DNOW 3DNOW PFCMPGT_MMXq_MMXq 3DNOW AMDONLY +PFMAX 3DNOW 3DNOW PFMAX_MMXq_MEMq 3DNOW AMDONLY +PFMAX 3DNOW 3DNOW PFMAX_MMXq_MMXq 3DNOW AMDONLY +PFMIN 3DNOW 3DNOW PFMIN_MMXq_MEMq 3DNOW AMDONLY +PFMIN 3DNOW 3DNOW PFMIN_MMXq_MMXq 3DNOW AMDONLY +PFMUL 3DNOW 3DNOW PFMUL_MMXq_MEMq 3DNOW AMDONLY +PFMUL 3DNOW 3DNOW PFMUL_MMXq_MMXq 3DNOW AMDONLY +PFNACC 3DNOW 3DNOW PFNACC_MMXq_MEMq 3DNOW AMDONLY +PFNACC 3DNOW 3DNOW PFNACC_MMXq_MMXq 3DNOW AMDONLY +PFPNACC 3DNOW 3DNOW PFPNACC_MMXq_MEMq 3DNOW AMDONLY +PFPNACC 3DNOW 3DNOW PFPNACC_MMXq_MMXq 3DNOW AMDONLY +PFRCPIT1 3DNOW 3DNOW PFRCPIT1_MMXq_MEMq 3DNOW AMDONLY +PFRCPIT1 3DNOW 3DNOW PFRCPIT1_MMXq_MMXq 3DNOW AMDONLY +PFRCPIT2 3DNOW 3DNOW PFRCPIT2_MMXq_MEMq 3DNOW AMDONLY +PFRCPIT2 3DNOW 3DNOW PFRCPIT2_MMXq_MMXq 3DNOW AMDONLY +PFRCP 3DNOW 3DNOW PFRCP_MMXq_MEMq 3DNOW AMDONLY +PFRCP 3DNOW 3DNOW PFRCP_MMXq_MMXq 3DNOW AMDONLY +PFRSQIT1 3DNOW 3DNOW PFRSQIT1_MMXq_MEMq 3DNOW AMDONLY +PFRSQIT1 3DNOW 3DNOW PFRSQIT1_MMXq_MMXq 3DNOW AMDONLY +PFRSQRT 3DNOW 3DNOW PFRSQRT_MMXq_MEMq 3DNOW AMDONLY +PFRSQRT 3DNOW 3DNOW PFRSQRT_MMXq_MMXq 3DNOW AMDONLY +PFSUBR 3DNOW 3DNOW PFSUBR_MMXq_MEMq 3DNOW AMDONLY +PFSUBR 3DNOW 3DNOW PFSUBR_MMXq_MMXq 3DNOW AMDONLY +PFSUB 3DNOW 3DNOW PFSUB_MMXq_MEMq 3DNOW AMDONLY +PFSUB 3DNOW 3DNOW PFSUB_MMXq_MMXq 3DNOW AMDONLY +PHADDD SSSE3 MMX PHADDD_MMXq_MEMq SSSE3MMX NOTSX +PHADDD SSSE3 MMX PHADDD_MMXq_MMXq SSSE3MMX NOTSX +PHADDD SSSE3 SSE PHADDD_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHADDD SSSE3 SSE PHADDD_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHADDSW SSSE3 MMX PHADDSW_MMXq_MEMq SSSE3MMX NOTSX +PHADDSW SSSE3 MMX PHADDSW_MMXq_MMXq SSSE3MMX NOTSX +PHADDSW SSSE3 SSE PHADDSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHADDSW SSSE3 SSE PHADDSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHADDW SSSE3 MMX PHADDW_MMXq_MEMq SSSE3MMX NOTSX +PHADDW SSSE3 MMX PHADDW_MMXq_MMXq SSSE3MMX NOTSX +PHADDW SSSE3 SSE PHADDW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHADDW SSSE3 SSE PHADDW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHMINPOSUW SSE4 SSE PHMINPOSUW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PHMINPOSUW SSE4 SSE PHMINPOSUW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PHSUBD SSSE3 MMX PHSUBD_MMXq_MEMq SSSE3MMX NOTSX +PHSUBD SSSE3 MMX PHSUBD_MMXq_MMXq SSSE3MMX NOTSX +PHSUBD SSSE3 SSE PHSUBD_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBD SSSE3 SSE PHSUBD_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBSW SSSE3 MMX PHSUBSW_MMXq_MEMq SSSE3MMX NOTSX +PHSUBSW SSSE3 MMX PHSUBSW_MMXq_MMXq SSSE3MMX NOTSX +PHSUBSW SSSE3 SSE PHSUBSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBSW SSSE3 SSE PHSUBSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBW SSSE3 MMX PHSUBW_MMXq_MEMq SSSE3MMX NOTSX +PHSUBW SSSE3 MMX PHSUBW_MMXq_MMXq SSSE3MMX NOTSX +PHSUBW SSSE3 SSE PHSUBW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PHSUBW SSSE3 SSE PHSUBW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PI2FD 3DNOW 3DNOW PI2FD_MMXq_MEMq 3DNOW AMDONLY +PI2FD 3DNOW 3DNOW PI2FD_MMXq_MMXq 3DNOW AMDONLY +PI2FW 3DNOW 3DNOW PI2FW_MMXq_MEMq 3DNOW AMDONLY +PI2FW 3DNOW 3DNOW PI2FW_MMXq_MMXq 3DNOW AMDONLY +PINSRB SSE4 SSE PINSRB_XMMdq_GPR32d_IMMb SSE4 INVALID +PINSRB SSE4 SSE PINSRB_XMMdq_MEMb_IMMb SSE4 INVALID +PINSRD SSE4 SSE PINSRD_XMMdq_GPR32d_IMMb SSE4 INVALID +PINSRD SSE4 SSE PINSRD_XMMdq_MEMd_IMMb SSE4 INVALID +PINSRQ SSE4 SSE PINSRQ_XMMdq_GPR64q_IMMb SSE4 INVALID +PINSRQ SSE4 SSE PINSRQ_XMMdq_MEMq_IMMb SSE4 INVALID +PINSRW MMX MMX PINSRW_MMXq_GPR32_IMMb PENTIUMMMX NOTSX +PINSRW MMX MMX PINSRW_MMXq_MEMw_IMMb PENTIUMMMX NOTSX +PINSRW SSE2 SSE PINSRW_XMMdq_GPR32_IMMb SSE2 INVALID +PINSRW SSE2 SSE PINSRW_XMMdq_MEMw_IMMb SSE2 INVALID +PMADDUBSW SSSE3 MMX PMADDUBSW_MMXq_MEMq SSSE3MMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDUBSW SSSE3 MMX PMADDUBSW_MMXq_MMXq SSSE3MMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDUBSW SSSE3 SSE PMADDUBSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +PMADDUBSW SSSE3 SSE PMADDUBSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT:DOUBLE_WIDE_OUTPUT +PMADDWD MMX MMX PMADDWD_MMXq_MEMq PENTIUMMMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDWD MMX MMX PMADDWD_MMXq_MMXq PENTIUMMMX DOUBLE_WIDE_OUTPUT:NOTSX +PMADDWD SSE2 SSE PMADDWD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMADDWD SSE2 SSE PMADDWD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMAXSB SSE4 SSE PMAXSB_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXSB SSE4 SSE PMAXSB_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMAXSD SSE4 SSE PMAXSD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXSD SSE4 SSE PMAXSD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMAXSW MMX MMX PMAXSW_MMXq_MEMq PENTIUMMMX NOTSX +PMAXSW MMX MMX PMAXSW_MMXq_MMXq PENTIUMMMX NOTSX +PMAXSW SSE2 SSE PMAXSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMAXSW SSE2 SSE PMAXSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMAXUB MMX MMX PMAXUB_MMXq_MEMq PENTIUMMMX NOTSX +PMAXUB MMX MMX PMAXUB_MMXq_MMXq PENTIUMMMX NOTSX +PMAXUB SSE2 SSE PMAXUB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMAXUB SSE2 SSE PMAXUB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMAXUD SSE4 SSE PMAXUD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXUD SSE4 SSE PMAXUD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMAXUW SSE4 SSE PMAXUW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMAXUW SSE4 SSE PMAXUW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINSB SSE4 SSE PMINSB_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINSB SSE4 SSE PMINSB_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINSD SSE4 SSE PMINSD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINSD SSE4 SSE PMINSD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINSW MMX MMX PMINSW_MMXq_MEMq PENTIUMMMX NOTSX +PMINSW MMX MMX PMINSW_MMXq_MMXq PENTIUMMMX NOTSX +PMINSW SSE2 SSE PMINSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMINSW SSE2 SSE PMINSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMINUB MMX MMX PMINUB_MMXq_MEMq PENTIUMMMX NOTSX +PMINUB MMX MMX PMINUB_MMXq_MMXq PENTIUMMMX NOTSX +PMINUB SSE2 SSE PMINUB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMINUB SSE2 SSE PMINUB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMINUD SSE4 SSE PMINUD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINUD SSE4 SSE PMINUD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMINUW SSE4 SSE PMINUW_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMINUW SSE4 SSE PMINUW_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMOVMSKB MMX MMX PMOVMSKB_GPR32_MMXq SSE NOTSX +PMOVMSKB SSE2 SSE PMOVMSKB_GPR32_XMMdq SSE2 INVALID +PMOVSXBD SSE4 SSE PMOVSXBD_XMMdq_MEMd SSE4 INVALID +PMOVSXBD SSE4 SSE PMOVSXBD_XMMdq_XMMd SSE4 INVALID +PMOVSXBQ SSE4 SSE PMOVSXBQ_XMMdq_MEMw SSE4 INVALID +PMOVSXBQ SSE4 SSE PMOVSXBQ_XMMdq_XMMw SSE4 INVALID +PMOVSXBW SSE4 SSE PMOVSXBW_XMMdq_MEMq SSE4 INVALID +PMOVSXBW SSE4 SSE PMOVSXBW_XMMdq_XMMq SSE4 INVALID +PMOVSXDQ SSE4 SSE PMOVSXDQ_XMMdq_MEMq SSE4 INVALID +PMOVSXDQ SSE4 SSE PMOVSXDQ_XMMdq_XMMq SSE4 INVALID +PMOVSXWD SSE4 SSE PMOVSXWD_XMMdq_MEMq SSE4 INVALID +PMOVSXWD SSE4 SSE PMOVSXWD_XMMdq_XMMq SSE4 INVALID +PMOVSXWQ SSE4 SSE PMOVSXWQ_XMMdq_MEMd SSE4 INVALID +PMOVSXWQ SSE4 SSE PMOVSXWQ_XMMdq_XMMd SSE4 INVALID +PMOVZXBD SSE4 SSE PMOVZXBD_XMMdq_MEMd SSE4 INVALID +PMOVZXBD SSE4 SSE PMOVZXBD_XMMdq_XMMd SSE4 INVALID +PMOVZXBQ SSE4 SSE PMOVZXBQ_XMMdq_MEMw SSE4 INVALID +PMOVZXBQ SSE4 SSE PMOVZXBQ_XMMdq_XMMw SSE4 INVALID +PMOVZXBW SSE4 SSE PMOVZXBW_XMMdq_MEMq SSE4 INVALID +PMOVZXBW SSE4 SSE PMOVZXBW_XMMdq_XMMq SSE4 INVALID +PMOVZXDQ SSE4 SSE PMOVZXDQ_XMMdq_MEMq SSE4 INVALID +PMOVZXDQ SSE4 SSE PMOVZXDQ_XMMdq_XMMq SSE4 INVALID +PMOVZXWD SSE4 SSE PMOVZXWD_XMMdq_MEMq SSE4 INVALID +PMOVZXWD SSE4 SSE PMOVZXWD_XMMdq_XMMq SSE4 INVALID +PMOVZXWQ SSE4 SSE PMOVZXWQ_XMMdq_MEMd SSE4 INVALID +PMOVZXWQ SSE4 SSE PMOVZXWQ_XMMdq_XMMd SSE4 INVALID +PMULDQ SSE4 SSE PMULDQ_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMULDQ SSE4 SSE PMULDQ_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMULHRSW SSSE3 MMX PMULHRSW_MMXq_MEMq SSSE3MMX NOTSX +PMULHRSW SSSE3 MMX PMULHRSW_MMXq_MMXq SSSE3MMX NOTSX +PMULHRSW SSSE3 SSE PMULHRSW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PMULHRSW SSSE3 SSE PMULHRSW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PMULHRW 3DNOW 3DNOW PMULHRW_MMXq_MEMq 3DNOW AMDONLY +PMULHRW 3DNOW 3DNOW PMULHRW_MMXq_MMXq 3DNOW AMDONLY +PMULHUW MMX MMX PMULHUW_MMXq_MEMq PENTIUMMMX NOTSX +PMULHUW MMX MMX PMULHUW_MMXq_MMXq PENTIUMMMX NOTSX +PMULHUW SSE2 SSE PMULHUW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULHUW SSE2 SSE PMULHUW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMULHW MMX MMX PMULHW_MMXq_MEMq PENTIUMMMX NOTSX +PMULHW MMX MMX PMULHW_MMXq_MMXq PENTIUMMMX NOTSX +PMULHW SSE2 SSE PMULHW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULHW SSE2 SSE PMULHW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMULLD SSE4 SSE PMULLD_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PMULLD SSE4 SSE PMULLD_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PMULLW MMX MMX PMULLW_MMXq_MEMq PENTIUMMMX NOTSX +PMULLW MMX MMX PMULLW_MMXq_MMXq PENTIUMMMX NOTSX +PMULLW SSE2 SSE PMULLW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULLW SSE2 SSE PMULLW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PMULUDQ SSE2 MMX PMULUDQ_MMXq_MEMq SSE2MMX NOTSX +PMULUDQ SSE2 MMX PMULUDQ_MMXq_MMXq SSE2MMX NOTSX +PMULUDQ SSE2 SSE PMULUDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PMULUDQ SSE2 SSE PMULUDQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +POPA BASE POP POPA I186 FIXED_BASE0:STACKPOP0:SCALABLE +POPAD BASE POP POPAD I386 FIXED_BASE0:STACKPOP0:SCALABLE +POPCNT SSE4 SSE POPCNT_GPRv_GPRv POPCNT IGNORES_OSFXSR:SCALABLE +POPCNT SSE4 SSE POPCNT_GPRv_MEMv POPCNT IGNORES_OSFXSR:SCALABLE +POPF BASE POP POPF I86 NOTSX:FIXED_BASE0:STACKPOP0 +POPFD BASE POP POPFD I386 NOTSX:FIXED_BASE0:STACKPOP0 +POPFQ LONGMODE POP POPFQ LONGMODE NOTSX:FIXED_BASE0:STACKPOP0 +POP BASE POP POP_DS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_ES I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_FS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_GPRv_58 I86 FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_GPRv_8F I86 FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_GS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POP BASE POP POP_MEMv I86 FIXED_BASE1:STACKPOP1:SCALABLE +POP BASE POP POP_SS I86 NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +POR MMX LOGICAL POR_MMXq_MEMq PENTIUMMMX NOTSX +POR MMX LOGICAL POR_MMXq_MMXq PENTIUMMMX NOTSX +POR SSE2 LOGICAL POR_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +POR SSE2 LOGICAL POR_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PREFETCHNTA SSE PREFETCH PREFETCHNTA_MEMmprefetch SSE_PREFETCH PREFETCH:NONTEMPORAL +PREFETCHT0 SSE PREFETCH PREFETCHT0_MEMmprefetch SSE_PREFETCH PREFETCH +PREFETCHT1 SSE PREFETCH PREFETCHT1_MEMmprefetch SSE_PREFETCH PREFETCH +PREFETCHT2 SSE PREFETCH PREFETCHT2_MEMmprefetch SSE_PREFETCH PREFETCH +PREFETCHWT1 PREFETCHWT1 PREFETCHWT1 PREFETCHWT1_MEMu8 PREFETCHWT1 PREFETCH +PREFETCHW 3DNOW_PREFETCH PREFETCH PREFETCHW_0F0Dr1 PREFETCH_NOP PREFETCH +PREFETCHW 3DNOW_PREFETCH PREFETCH PREFETCHW_0F0Dr3 PREFETCH_NOP PREFETCH +PREFETCH_EXCLUSIVE 3DNOW_PREFETCH PREFETCH PREFETCH_EXCLUSIVE_MEMmprefetch PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr4 PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr5 PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr6 PREFETCH_NOP PREFETCH +PREFETCH_RESERVED 3DNOW_PREFETCH PREFETCH PREFETCH_RESERVED_0F0Dr7 PREFETCH_NOP PREFETCH +PSADBW MMX MMX PSADBW_MMXq_MEMq PENTIUMMMX NOTSX +PSADBW MMX MMX PSADBW_MMXq_MMXq PENTIUMMMX NOTSX +PSADBW SSE2 SSE PSADBW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSADBW SSE2 SSE PSADBW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSHUFB SSSE3 MMX PSHUFB_MMXq_MEMq SSSE3MMX NOTSX +PSHUFB SSSE3 MMX PSHUFB_MMXq_MMXq SSSE3MMX NOTSX +PSHUFB SSSE3 SSE PSHUFB_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSHUFB SSSE3 SSE PSHUFB_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSHUFD SSE2 SSE PSHUFD_XMMdq_MEMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFD SSE2 SSE PSHUFD_XMMdq_XMMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFHW SSE2 SSE PSHUFHW_XMMdq_MEMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFHW SSE2 SSE PSHUFHW_XMMdq_XMMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFLW SSE2 SSE PSHUFLW_XMMdq_MEMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFLW SSE2 SSE PSHUFLW_XMMdq_XMMdq_IMMb SSE2 REQUIRES_ALIGNMENT +PSHUFW MMX MMX PSHUFW_MMXq_MEMq_IMMb PENTIUMMMX NOTSX +PSHUFW MMX MMX PSHUFW_MMXq_MMXq_IMMb PENTIUMMMX NOTSX +PSIGNB SSSE3 MMX PSIGNB_MMXq_MEMq SSSE3MMX NOTSX +PSIGNB SSSE3 MMX PSIGNB_MMXq_MMXq SSSE3MMX NOTSX +PSIGNB SSSE3 SSE PSIGNB_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSIGNB SSSE3 SSE PSIGNB_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSIGND SSSE3 MMX PSIGND_MMXq_MEMq SSSE3MMX NOTSX +PSIGND SSSE3 MMX PSIGND_MMXq_MMXq SSSE3MMX NOTSX +PSIGND SSSE3 SSE PSIGND_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSIGND SSSE3 SSE PSIGND_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSIGNW SSSE3 MMX PSIGNW_MMXq_MEMq SSSE3MMX NOTSX +PSIGNW SSSE3 MMX PSIGNW_MMXq_MMXq SSSE3MMX NOTSX +PSIGNW SSSE3 SSE PSIGNW_XMMdq_MEMdq SSSE3 REQUIRES_ALIGNMENT +PSIGNW SSSE3 SSE PSIGNW_XMMdq_XMMdq SSSE3 REQUIRES_ALIGNMENT +PSLLDQ SSE2 SSE PSLLDQ_XMMdq_IMMb SSE2 INVALID +PSLLD MMX MMX PSLLD_MMXq_IMMb PENTIUMMMX NOTSX +PSLLD MMX MMX PSLLD_MMXq_MEMq PENTIUMMMX NOTSX +PSLLD MMX MMX PSLLD_MMXq_MMXq PENTIUMMMX NOTSX +PSLLD SSE2 SSE PSLLD_XMMdq_IMMb SSE2 INVALID +PSLLD SSE2 SSE PSLLD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSLLD SSE2 SSE PSLLD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSLLQ MMX MMX PSLLQ_MMXq_IMMb PENTIUMMMX NOTSX +PSLLQ MMX MMX PSLLQ_MMXq_MEMq PENTIUMMMX NOTSX +PSLLQ MMX MMX PSLLQ_MMXq_MMXq PENTIUMMMX NOTSX +PSLLQ SSE2 SSE PSLLQ_XMMdq_IMMb SSE2 INVALID +PSLLQ SSE2 SSE PSLLQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSLLQ SSE2 SSE PSLLQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSLLW MMX MMX PSLLW_MMXq_IMMb PENTIUMMMX NOTSX +PSLLW MMX MMX PSLLW_MMXq_MEMq PENTIUMMMX NOTSX +PSLLW MMX MMX PSLLW_MMXq_MMXq PENTIUMMMX NOTSX +PSLLW SSE2 SSE PSLLW_XMMdq_IMMb SSE2 INVALID +PSLLW SSE2 SSE PSLLW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSLLW SSE2 SSE PSLLW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSMASH SNP SYSTEM PSMASH_RAX SNP AMDONLY +PSRAD MMX MMX PSRAD_MMXq_IMMb PENTIUMMMX NOTSX +PSRAD MMX MMX PSRAD_MMXq_MEMq PENTIUMMMX NOTSX +PSRAD MMX MMX PSRAD_MMXq_MMXq PENTIUMMMX NOTSX +PSRAD SSE2 SSE PSRAD_XMMdq_IMMb SSE2 INVALID +PSRAD SSE2 SSE PSRAD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRAD SSE2 SSE PSRAD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRAW MMX MMX PSRAW_MMXq_IMMb PENTIUMMMX NOTSX +PSRAW MMX MMX PSRAW_MMXq_MEMq PENTIUMMMX NOTSX +PSRAW MMX MMX PSRAW_MMXq_MMXq PENTIUMMMX NOTSX +PSRAW SSE2 SSE PSRAW_XMMdq_IMMb SSE2 INVALID +PSRAW SSE2 SSE PSRAW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRAW SSE2 SSE PSRAW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRLDQ SSE2 SSE PSRLDQ_XMMdq_IMMb SSE2 INVALID +PSRLD MMX MMX PSRLD_MMXq_IMMb PENTIUMMMX NOTSX +PSRLD MMX MMX PSRLD_MMXq_MEMq PENTIUMMMX NOTSX +PSRLD MMX MMX PSRLD_MMXq_MMXq PENTIUMMMX NOTSX +PSRLD SSE2 SSE PSRLD_XMMdq_IMMb SSE2 INVALID +PSRLD SSE2 SSE PSRLD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRLD SSE2 SSE PSRLD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRLQ MMX MMX PSRLQ_MMXq_IMMb PENTIUMMMX NOTSX +PSRLQ MMX MMX PSRLQ_MMXq_MEMq PENTIUMMMX NOTSX +PSRLQ MMX MMX PSRLQ_MMXq_MMXq PENTIUMMMX NOTSX +PSRLQ SSE2 SSE PSRLQ_XMMdq_IMMb SSE2 INVALID +PSRLQ SSE2 SSE PSRLQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRLQ SSE2 SSE PSRLQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSRLW MMX MMX PSRLW_MMXq_IMMb PENTIUMMMX NOTSX +PSRLW MMX MMX PSRLW_MMXq_MEMq PENTIUMMMX NOTSX +PSRLW MMX MMX PSRLW_MMXq_MMXq PENTIUMMMX NOTSX +PSRLW SSE2 SSE PSRLW_XMMdq_IMMb SSE2 INVALID +PSRLW SSE2 SSE PSRLW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSRLW SSE2 SSE PSRLW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBB MMX MMX PSUBB_MMXq_MEMq PENTIUMMMX NOTSX +PSUBB MMX MMX PSUBB_MMXq_MMXq PENTIUMMMX NOTSX +PSUBB SSE2 SSE PSUBB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBB SSE2 SSE PSUBB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBD MMX MMX PSUBD_MMXq_MEMq PENTIUMMMX NOTSX +PSUBD MMX MMX PSUBD_MMXq_MMXq PENTIUMMMX NOTSX +PSUBD SSE2 SSE PSUBD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBD SSE2 SSE PSUBD_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBQ SSE2 MMX PSUBQ_MMXq_MEMq SSE2MMX NOTSX +PSUBQ SSE2 MMX PSUBQ_MMXq_MMXq SSE2MMX NOTSX +PSUBQ SSE2 SSE PSUBQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBQ SSE2 SSE PSUBQ_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBSB MMX MMX PSUBSB_MMXq_MEMq PENTIUMMMX NOTSX +PSUBSB MMX MMX PSUBSB_MMXq_MMXq PENTIUMMMX NOTSX +PSUBSB SSE2 SSE PSUBSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBSB SSE2 SSE PSUBSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBSW MMX MMX PSUBSW_MMXq_MEMq PENTIUMMMX NOTSX +PSUBSW MMX MMX PSUBSW_MMXq_MMXq PENTIUMMMX NOTSX +PSUBSW SSE2 SSE PSUBSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBSW SSE2 SSE PSUBSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSB MMX MMX PSUBUSB_MMXq_MEMq PENTIUMMMX NOTSX +PSUBUSB MMX MMX PSUBUSB_MMXq_MMXq PENTIUMMMX NOTSX +PSUBUSB SSE2 SSE PSUBUSB_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSB SSE2 SSE PSUBUSB_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSW MMX MMX PSUBUSW_MMXq_MEMq PENTIUMMMX NOTSX +PSUBUSW MMX MMX PSUBUSW_MMXq_MMXq PENTIUMMMX NOTSX +PSUBUSW SSE2 SSE PSUBUSW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBUSW SSE2 SSE PSUBUSW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSUBW MMX MMX PSUBW_MMXq_MEMq PENTIUMMMX NOTSX +PSUBW MMX MMX PSUBW_MMXq_MMXq PENTIUMMMX NOTSX +PSUBW SSE2 SSE PSUBW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PSUBW SSE2 SSE PSUBW_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +PSWAPD 3DNOW 3DNOW PSWAPD_MMXq_MEMq 3DNOW AMDONLY +PSWAPD 3DNOW 3DNOW PSWAPD_MMXq_MMXq 3DNOW AMDONLY +PTEST SSE4 LOGICAL PTEST_XMMdq_MEMdq SSE4 REQUIRES_ALIGNMENT +PTEST SSE4 LOGICAL PTEST_XMMdq_XMMdq SSE4 REQUIRES_ALIGNMENT +PTWRITE PTWRITE PTWRITE PTWRITE_GPRy PTWRITE SCALABLE +PTWRITE PTWRITE PTWRITE PTWRITE_MEMy PTWRITE SCALABLE +PUNPCKHBW MMX MMX PUNPCKHBW_MMXq_MEMq PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHBW MMX MMX PUNPCKHBW_MMXq_MMXd PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHBW SSE2 SSE PUNPCKHBW_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHBW SSE2 SSE PUNPCKHBW_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHDQ MMX MMX PUNPCKHDQ_MMXq_MEMq PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHDQ MMX MMX PUNPCKHDQ_MMXq_MMXd PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHDQ SSE2 SSE PUNPCKHDQ_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHDQ SSE2 SSE PUNPCKHDQ_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHQDQ SSE2 SSE PUNPCKHQDQ_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHQDQ SSE2 SSE PUNPCKHQDQ_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHWD MMX MMX PUNPCKHWD_MMXq_MEMq PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHWD MMX MMX PUNPCKHWD_MMXq_MMXd PENTIUMMMX SKIPLOW32:NOTSX +PUNPCKHWD SSE2 SSE PUNPCKHWD_XMMdq_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKHWD SSE2 SSE PUNPCKHWD_XMMdq_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +PUNPCKLBW MMX MMX PUNPCKLBW_MMXq_MEMd PENTIUMMMX NOTSX +PUNPCKLBW MMX MMX PUNPCKLBW_MMXq_MMXd PENTIUMMMX NOTSX +PUNPCKLBW SSE2 SSE PUNPCKLBW_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLBW SSE2 SSE PUNPCKLBW_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUNPCKLDQ MMX MMX PUNPCKLDQ_MMXq_MEMd PENTIUMMMX NOTSX +PUNPCKLDQ MMX MMX PUNPCKLDQ_MMXq_MMXd PENTIUMMMX NOTSX +PUNPCKLDQ SSE2 SSE PUNPCKLDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLDQ SSE2 SSE PUNPCKLDQ_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUNPCKLQDQ SSE2 SSE PUNPCKLQDQ_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLQDQ SSE2 SSE PUNPCKLQDQ_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUNPCKLWD MMX MMX PUNPCKLWD_MMXq_MEMd PENTIUMMMX NOTSX +PUNPCKLWD MMX MMX PUNPCKLWD_MMXq_MMXd PENTIUMMMX NOTSX +PUNPCKLWD SSE2 SSE PUNPCKLWD_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PUNPCKLWD SSE2 SSE PUNPCKLWD_XMMdq_XMMq SSE2 REQUIRES_ALIGNMENT +PUSHA BASE PUSH PUSHA I186 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSHAD BASE PUSH PUSHAD I386 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSHF BASE PUSH PUSHF I86 FIXED_BASE0:STACKPUSH0 +PUSHFD BASE PUSH PUSHFD I386 FIXED_BASE0:STACKPUSH0 +PUSHFQ LONGMODE PUSH PUSHFQ LONGMODE FIXED_BASE0:STACKPUSH0 +PUSH BASE PUSH PUSH_CS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_DS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_ES I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_FS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_GPRv_50 I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_GPRv_FFr6 I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_GS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_IMMb I186 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_IMMz I186 FIXED_BASE0:STACKPUSH0:SCALABLE +PUSH BASE PUSH PUSH_MEMv I86 FIXED_BASE1:STACKPUSH1:SCALABLE +PUSH BASE PUSH PUSH_SS I86 FIXED_BASE0:STACKPUSH0:SCALABLE +PVALIDATE SNP SYSTEM PVALIDATE_RAX_ECX_EDX SNP AMDONLY +PXOR MMX LOGICAL PXOR_MMXq_MEMq PENTIUMMMX NOTSX +PXOR MMX LOGICAL PXOR_MMXq_MMXq PENTIUMMMX NOTSX +PXOR SSE2 LOGICAL PXOR_XMMdq_MEMdq SSE2 REQUIRES_ALIGNMENT +PXOR SSE2 LOGICAL PXOR_XMMdq_XMMdq SSE2 REQUIRES_ALIGNMENT +RCL BASE ROTATE RCL_GPR8_CL I86 BYTEOP +RCL BASE ROTATE RCL_GPR8_IMMb I186 BYTEOP +RCL BASE ROTATE RCL_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +RCL BASE ROTATE RCL_GPRv_CL I86 SCALABLE +RCL BASE ROTATE RCL_GPRv_IMMb I186 SCALABLE +RCL BASE ROTATE RCL_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +RCL BASE ROTATE RCL_MEMb_CL I86 BYTEOP +RCL BASE ROTATE RCL_MEMb_IMMb I186 BYTEOP +RCL BASE ROTATE RCL_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +RCL BASE ROTATE RCL_MEMv_CL I86 SCALABLE +RCL BASE ROTATE RCL_MEMv_IMMb I186 SCALABLE +RCL BASE ROTATE RCL_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +RCPPS SSE SSE RCPPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT +RCPPS SSE SSE RCPPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT +RCPSS SSE SSE RCPSS_XMMss_MEMss SSE SIMD_SCALAR +RCPSS SSE SSE RCPSS_XMMss_XMMss SSE SIMD_SCALAR +RCR BASE ROTATE RCR_GPR8_CL I86 BYTEOP +RCR BASE ROTATE RCR_GPR8_IMMb I186 BYTEOP +RCR BASE ROTATE RCR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +RCR BASE ROTATE RCR_GPRv_CL I86 SCALABLE +RCR BASE ROTATE RCR_GPRv_IMMb I186 SCALABLE +RCR BASE ROTATE RCR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +RCR BASE ROTATE RCR_MEMb_CL I86 BYTEOP +RCR BASE ROTATE RCR_MEMb_IMMb I186 BYTEOP +RCR BASE ROTATE RCR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +RCR BASE ROTATE RCR_MEMv_CL I86 SCALABLE +RCR BASE ROTATE RCR_MEMv_IMMb I186 SCALABLE +RCR BASE ROTATE RCR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +RDFSBASE RDWRFSGS RDWRFSGS RDFSBASE_GPRy RDWRFSGS SCALABLE +RDGSBASE RDWRFSGS RDWRFSGS RDGSBASE_GPRy RDWRFSGS SCALABLE +RDMSR BASE SYSTEM RDMSR PENTIUMREAL RING0:NOTSX +RDPID RDPID RDPID RDPID_GPR32u32 RDPID INVALID +RDPID RDPID RDPID RDPID_GPR64u64 RDPID INVALID +RDPKRU PKU PKU RDPKRU PKU INVALID +RDPMC BASE SYSTEM RDPMC RDPMC INVALID +RDPRU RDPRU RDPRU RDPRU RDPRU AMDONLY +RDRAND RDRAND RDRAND RDRAND_GPRv RDRAND SCALABLE +RDSEED RDSEED RDSEED RDSEED_GPRv RDSEED SCALABLE +RDSSPD CET CET RDSSPD_GPR32u32 CET INVALID +RDSSPQ CET CET RDSSPQ_GPR64u64 CET INVALID +RDTSC BASE SYSTEM RDTSC PENTIUMREAL INVALID +RDTSCP RDTSCP SYSTEM RDTSCP RDTSCP INVALID +REPE_CMPSB BASE STRINGOP REPE_CMPSB I86 REP:FIXED_BASE0:FIXED_BASE1:BYTEOP +REPE_CMPSD BASE STRINGOP REPE_CMPSD I386 REP:FIXED_BASE0:FIXED_BASE1 +REPE_CMPSQ LONGMODE STRINGOP REPE_CMPSQ LONGMODE REP:FIXED_BASE0:FIXED_BASE1 +REPE_CMPSW BASE STRINGOP REPE_CMPSW I86 REP:FIXED_BASE0:FIXED_BASE1 +REPE_SCASB BASE STRINGOP REPE_SCASB I86 REP:FIXED_BASE0:BYTEOP +REPE_SCASD BASE STRINGOP REPE_SCASD I386 REP:FIXED_BASE0 +REPE_SCASQ LONGMODE STRINGOP REPE_SCASQ LONGMODE REP:FIXED_BASE0 +REPE_SCASW BASE STRINGOP REPE_SCASW I86 REP:FIXED_BASE0 +REPNE_CMPSB BASE STRINGOP REPNE_CMPSB I86 REP:FIXED_BASE0:FIXED_BASE1:BYTEOP +REPNE_CMPSD BASE STRINGOP REPNE_CMPSD I386 REP:FIXED_BASE0:FIXED_BASE1 +REPNE_CMPSQ LONGMODE STRINGOP REPNE_CMPSQ LONGMODE REP:FIXED_BASE0:FIXED_BASE1 +REPNE_CMPSW BASE STRINGOP REPNE_CMPSW I86 REP:FIXED_BASE0:FIXED_BASE1 +REPNE_SCASB BASE STRINGOP REPNE_SCASB I86 REP:FIXED_BASE0:BYTEOP +REPNE_SCASD BASE STRINGOP REPNE_SCASD I386 REP:FIXED_BASE0 +REPNE_SCASQ LONGMODE STRINGOP REPNE_SCASQ LONGMODE REP:FIXED_BASE0 +REPNE_SCASW BASE STRINGOP REPNE_SCASW I86 REP:FIXED_BASE0 +REP_INSB BASE IOSTRINGOP REP_INSB I186 REP:FIXED_BASE0:NOTSX:BYTEOP +REP_INSD BASE IOSTRINGOP REP_INSD I386 REP:FIXED_BASE0:NOTSX +REP_INSW BASE IOSTRINGOP REP_INSW I186 REP:FIXED_BASE0:NOTSX +REP_LODSB BASE STRINGOP REP_LODSB I86 REP:FIXED_BASE0:BYTEOP +REP_LODSD BASE STRINGOP REP_LODSD I386 REP:FIXED_BASE0 +REP_LODSQ LONGMODE STRINGOP REP_LODSQ LONGMODE REP:FIXED_BASE0 +REP_LODSW BASE STRINGOP REP_LODSW I86 REP:FIXED_BASE0 +REP_MONTMUL VIA_PADLOCK_MONTMUL VIA_PADLOCK REP_MONTMUL VIA_PADLOCK_MONTMUL REP:FIXED_BASE0 +REP_MOVSB BASE STRINGOP REP_MOVSB I86 REP:FIXED_BASE0:FIXED_BASE1:BYTEOP +REP_MOVSD BASE STRINGOP REP_MOVSD I386 REP:FIXED_BASE0:FIXED_BASE1 +REP_MOVSQ LONGMODE STRINGOP REP_MOVSQ LONGMODE REP:FIXED_BASE0:FIXED_BASE1 +REP_MOVSW BASE STRINGOP REP_MOVSW I86 REP:FIXED_BASE0:FIXED_BASE1 +REP_OUTSB BASE IOSTRINGOP REP_OUTSB I186 REP:FIXED_BASE0:NOTSX:BYTEOP +REP_OUTSD BASE IOSTRINGOP REP_OUTSD I386 REP:FIXED_BASE0:NOTSX +REP_OUTSW BASE IOSTRINGOP REP_OUTSW I186 REP:FIXED_BASE0:NOTSX +REP_STOSB BASE STRINGOP REP_STOSB I86 REP:FIXED_BASE0:BYTEOP +REP_STOSD BASE STRINGOP REP_STOSD I386 REP:FIXED_BASE0 +REP_STOSQ LONGMODE STRINGOP REP_STOSQ LONGMODE REP:FIXED_BASE0 +REP_STOSW BASE STRINGOP REP_STOSW I86 REP:FIXED_BASE0 +REP_XCRYPTCBC VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTCBC VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTCFB VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTCFB VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTCTR VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTCTR VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTECB VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTECB VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XCRYPTOFB VIA_PADLOCK_AES VIA_PADLOCK REP_XCRYPTOFB VIA_PADLOCK_AES REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XSHA1 VIA_PADLOCK_SHA VIA_PADLOCK REP_XSHA1 VIA_PADLOCK_SHA REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XSHA256 VIA_PADLOCK_SHA VIA_PADLOCK REP_XSHA256 VIA_PADLOCK_SHA REP:FIXED_BASE0:BYTEOP:SCALABLE +REP_XSTORE VIA_PADLOCK_RNG VIA_PADLOCK REP_XSTORE VIA_PADLOCK_RNG REP:FIXED_BASE0:BYTEOP:SCALABLE +RET_FAR BASE RET RET_FAR I86 FAR_XFER:NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +RET_FAR BASE RET RET_FAR_IMMw I86 FAR_XFER:NOTSX:FIXED_BASE0:STACKPOP0:SCALABLE +RET_NEAR BASE RET RET_NEAR I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPOP0:SCALABLE +RET_NEAR BASE RET RET_NEAR_IMMw I86 MPX_PREFIX_ABLE:FIXED_BASE0:STACKPOP0:SCALABLE +RMPADJUST SNP SYSTEM RMPADJUST_RAX_RCX_RDX SNP AMDONLY +RMPUPDATE SNP SYSTEM RMPUPDATE_RAX_RCX SNP AMDONLY +ROL BASE ROTATE ROL_GPR8_CL I86 BYTEOP +ROL BASE ROTATE ROL_GPR8_IMMb I186 BYTEOP +ROL BASE ROTATE ROL_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +ROL BASE ROTATE ROL_GPRv_CL I86 SCALABLE +ROL BASE ROTATE ROL_GPRv_IMMb I186 SCALABLE +ROL BASE ROTATE ROL_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +ROL BASE ROTATE ROL_MEMb_CL I86 BYTEOP +ROL BASE ROTATE ROL_MEMb_IMMb I186 BYTEOP +ROL BASE ROTATE ROL_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +ROL BASE ROTATE ROL_MEMv_CL I86 SCALABLE +ROL BASE ROTATE ROL_MEMv_IMMb I186 SCALABLE +ROL BASE ROTATE ROL_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +RORX BMI2 BMI2 RORX_VGPR32d_MEMd_IMMb BMI2 INVALID +RORX BMI2 BMI2 RORX_VGPR32d_VGPR32d_IMMb BMI2 INVALID +RORX BMI2 BMI2 RORX_VGPR64q_MEMq_IMMb BMI2 INVALID +RORX BMI2 BMI2 RORX_VGPR64q_VGPR64q_IMMb BMI2 INVALID +ROR BASE ROTATE ROR_GPR8_CL I86 BYTEOP +ROR BASE ROTATE ROR_GPR8_IMMb I186 BYTEOP +ROR BASE ROTATE ROR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +ROR BASE ROTATE ROR_GPRv_CL I86 SCALABLE +ROR BASE ROTATE ROR_GPRv_IMMb I186 SCALABLE +ROR BASE ROTATE ROR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +ROR BASE ROTATE ROR_MEMb_CL I86 BYTEOP +ROR BASE ROTATE ROR_MEMb_IMMb I186 BYTEOP +ROR BASE ROTATE ROR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +ROR BASE ROTATE ROR_MEMv_CL I86 SCALABLE +ROR BASE ROTATE ROR_MEMv_IMMb I186 SCALABLE +ROR BASE ROTATE ROR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +ROUNDPD SSE4 SSE ROUNDPD_XMMpd_MEMpd_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDPD SSE4 SSE ROUNDPD_XMMpd_XMMpd_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDPS SSE4 SSE ROUNDPS_XMMps_MEMps_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDPS SSE4 SSE ROUNDPS_XMMps_XMMps_IMMb SSE4 REQUIRES_ALIGNMENT:MXCSR +ROUNDSD SSE4 SSE ROUNDSD_XMMq_MEMq_IMMb SSE4 SIMD_SCALAR:MXCSR +ROUNDSD SSE4 SSE ROUNDSD_XMMq_XMMq_IMMb SSE4 SIMD_SCALAR:MXCSR +ROUNDSS SSE4 SSE ROUNDSS_XMMd_MEMd_IMMb SSE4 SIMD_SCALAR:MXCSR +ROUNDSS SSE4 SSE ROUNDSS_XMMd_XMMd_IMMb SSE4 SIMD_SCALAR:MXCSR +RSM BASE SYSRET RSM I486 NOTSX +RSQRTPS SSE SSE RSQRTPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT +RSQRTPS SSE SSE RSQRTPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT +RSQRTSS SSE SSE RSQRTSS_XMMss_MEMss SSE SIMD_SCALAR +RSQRTSS SSE SSE RSQRTSS_XMMss_XMMss SSE SIMD_SCALAR +RSTORSSP CET CET RSTORSSP_MEMu64 CET INVALID +SAHF BASE FLAGOP SAHF LAHF INVALID +SALC BASE FLAGOP SALC I86 INVALID +SARX BMI2 BMI2 SARX_VGPR32d_MEMd_VGPR32d BMI2 INVALID +SARX BMI2 BMI2 SARX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +SARX BMI2 BMI2 SARX_VGPR64q_MEMq_VGPR64q BMI2 INVALID +SARX BMI2 BMI2 SARX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +SAR BASE SHIFT SAR_GPR8_CL I86 BYTEOP +SAR BASE SHIFT SAR_GPR8_IMMb I186 BYTEOP +SAR BASE SHIFT SAR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +SAR BASE SHIFT SAR_GPRv_CL I86 SCALABLE +SAR BASE SHIFT SAR_GPRv_IMMb I186 SCALABLE +SAR BASE SHIFT SAR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +SAR BASE SHIFT SAR_MEMb_CL I86 BYTEOP +SAR BASE SHIFT SAR_MEMb_IMMb I186 BYTEOP +SAR BASE SHIFT SAR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +SAR BASE SHIFT SAR_MEMv_CL I86 SCALABLE +SAR BASE SHIFT SAR_MEMv_IMMb I186 SCALABLE +SAR BASE SHIFT SAR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +SAVEPREVSSP CET CET SAVEPREVSSP CET INVALID +SBB BASE BINARY SBB_AL_IMMb I86 BYTEOP +SBB BASE BINARY SBB_GPR8_GPR8_18 I86 BYTEOP +SBB BASE BINARY SBB_GPR8_GPR8_1A I86 BYTEOP +SBB BASE BINARY SBB_GPR8_IMMb_80r3 I86 BYTEOP +SBB BASE BINARY SBB_GPR8_IMMb_82r3 I86 BYTEOP +SBB BASE BINARY SBB_GPR8_MEMb I86 BYTEOP +SBB BASE BINARY SBB_GPRv_GPRv_19 I86 SCALABLE +SBB BASE BINARY SBB_GPRv_GPRv_1B I86 SCALABLE +SBB BASE BINARY SBB_GPRv_IMMb I86 SCALABLE +SBB BASE BINARY SBB_GPRv_IMMz I86 SCALABLE +SBB BASE BINARY SBB_GPRv_MEMv I86 SCALABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMb_IMMb_80r3 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMb_IMMb_82r3 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SBB_LOCK BASE BINARY SBB_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SBB BASE BINARY SBB_MEMb_GPR8 I86 BYTEOP:LOCKABLE +SBB BASE BINARY SBB_MEMb_IMMb_80r3 I86 BYTEOP:LOCKABLE +SBB BASE BINARY SBB_MEMb_IMMb_82r3 I86 BYTEOP:LOCKABLE +SBB BASE BINARY SBB_MEMv_GPRv I86 LOCKABLE:SCALABLE +SBB BASE BINARY SBB_MEMv_IMMb I86 LOCKABLE:SCALABLE +SBB BASE BINARY SBB_MEMv_IMMz I86 LOCKABLE:SCALABLE +SBB BASE BINARY SBB_OrAX_IMMz I86 SCALABLE +SCASB BASE STRINGOP SCASB I86 FIXED_BASE0:BYTEOP +SCASD BASE STRINGOP SCASD I386 FIXED_BASE0 +SCASQ LONGMODE STRINGOP SCASQ LONGMODE FIXED_BASE0 +SCASW BASE STRINGOP SCASW I86 FIXED_BASE0 +SEAMCALL TDX LEGACY SEAMCALL TDX NOTSX +SEAMOPS TDX LEGACY SEAMOPS TDX NOTSX +SEAMRET TDX LEGACY SEAMRET TDX NOTSX +SENDUIPI UINTR UINTR SENDUIPI_GPR32u32 UINTR INVALID +SERIALIZE SERIALIZE SERIALIZE SERIALIZE SERIALIZE INVALID +SETBE BASE SETCC SETBE_GPR8 I386 BYTEOP +SETBE BASE SETCC SETBE_MEMb I386 BYTEOP +SETB BASE SETCC SETB_GPR8 I386 BYTEOP +SETB BASE SETCC SETB_MEMb I386 BYTEOP +SETLE BASE SETCC SETLE_GPR8 I386 BYTEOP +SETLE BASE SETCC SETLE_MEMb I386 BYTEOP +SETL BASE SETCC SETL_GPR8 I386 BYTEOP +SETL BASE SETCC SETL_MEMb I386 BYTEOP +SETNBE BASE SETCC SETNBE_GPR8 I386 BYTEOP +SETNBE BASE SETCC SETNBE_MEMb I386 BYTEOP +SETNB BASE SETCC SETNB_GPR8 I386 BYTEOP +SETNB BASE SETCC SETNB_MEMb I386 BYTEOP +SETNLE BASE SETCC SETNLE_GPR8 I386 BYTEOP +SETNLE BASE SETCC SETNLE_MEMb I386 BYTEOP +SETNL BASE SETCC SETNL_GPR8 I386 BYTEOP +SETNL BASE SETCC SETNL_MEMb I386 BYTEOP +SETNO BASE SETCC SETNO_GPR8 I386 BYTEOP +SETNO BASE SETCC SETNO_MEMb I386 BYTEOP +SETNP BASE SETCC SETNP_GPR8 I386 BYTEOP +SETNP BASE SETCC SETNP_MEMb I386 BYTEOP +SETNS BASE SETCC SETNS_GPR8 I386 BYTEOP +SETNS BASE SETCC SETNS_MEMb I386 BYTEOP +SETNZ BASE SETCC SETNZ_GPR8 I386 BYTEOP +SETNZ BASE SETCC SETNZ_MEMb I386 BYTEOP +SETO BASE SETCC SETO_GPR8 I386 BYTEOP +SETO BASE SETCC SETO_MEMb I386 BYTEOP +SETP BASE SETCC SETP_GPR8 I386 BYTEOP +SETP BASE SETCC SETP_MEMb I386 BYTEOP +SETSSBSY CET CET SETSSBSY CET INVALID +SETS BASE SETCC SETS_GPR8 I386 BYTEOP +SETS BASE SETCC SETS_MEMb I386 BYTEOP +SETZ BASE SETCC SETZ_GPR8 I386 BYTEOP +SETZ BASE SETCC SETZ_MEMb I386 BYTEOP +SFENCE SSE MISC SFENCE SSE IGNORES_OSFXSR +SGDT BASE SYSTEM SGDT_MEMs I286REAL NOTSX:SCALABLE +SGDT BASE SYSTEM SGDT_MEMs64 I286REAL NOTSX +SHA1MSG1 SHA SHA SHA1MSG1_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA1MSG1 SHA SHA SHA1MSG1_XMMi32_XMMi32_SHA SHA INVALID +SHA1MSG2 SHA SHA SHA1MSG2_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA1MSG2 SHA SHA SHA1MSG2_XMMi32_XMMi32_SHA SHA INVALID +SHA1NEXTE SHA SHA SHA1NEXTE_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA1NEXTE SHA SHA SHA1NEXTE_XMMi32_XMMi32_SHA SHA INVALID +SHA1RNDS4 SHA SHA SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA SHA REQUIRES_ALIGNMENT +SHA1RNDS4 SHA SHA SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA SHA INVALID +SHA256MSG1 SHA SHA SHA256MSG1_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA256MSG1 SHA SHA SHA256MSG1_XMMi32_XMMi32_SHA SHA INVALID +SHA256MSG2 SHA SHA SHA256MSG2_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA256MSG2 SHA SHA SHA256MSG2_XMMi32_XMMi32_SHA SHA INVALID +SHA256RNDS2 SHA SHA SHA256RNDS2_XMMi32_MEMi32_SHA SHA REQUIRES_ALIGNMENT +SHA256RNDS2 SHA SHA SHA256RNDS2_XMMi32_XMMi32_SHA SHA INVALID +SHLD BASE SHIFT SHLD_GPRv_GPRv_CL I386 SCALABLE +SHLD BASE SHIFT SHLD_GPRv_GPRv_IMMb I386 SCALABLE +SHLD BASE SHIFT SHLD_MEMv_GPRv_CL I386 SCALABLE +SHLD BASE SHIFT SHLD_MEMv_GPRv_IMMb I386 SCALABLE +SHLX BMI2 BMI2 SHLX_VGPR32d_MEMd_VGPR32d BMI2 INVALID +SHLX BMI2 BMI2 SHLX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +SHLX BMI2 BMI2 SHLX_VGPR64q_MEMq_VGPR64q BMI2 INVALID +SHLX BMI2 BMI2 SHLX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +SHL BASE SHIFT SHL_GPR8_CL_D2r4 I86 BYTEOP +SHL BASE SHIFT SHL_GPR8_CL_D2r6 I86 BYTEOP +SHL BASE SHIFT SHL_GPR8_IMMb_C0r4 I186 BYTEOP +SHL BASE SHIFT SHL_GPR8_IMMb_C0r6 I186 BYTEOP +SHL BASE SHIFT SHL_GPR8_ONE_D0r4 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_GPR8_ONE_D0r6 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_GPRv_CL_D3r4 I86 SCALABLE +SHL BASE SHIFT SHL_GPRv_CL_D3r6 I86 SCALABLE +SHL BASE SHIFT SHL_GPRv_IMMb_C1r4 I186 SCALABLE +SHL BASE SHIFT SHL_GPRv_IMMb_C1r6 I186 SCALABLE +SHL BASE SHIFT SHL_GPRv_ONE_D1r4 I86 IMPLICIT_ONE:SCALABLE +SHL BASE SHIFT SHL_GPRv_ONE_D1r6 I86 IMPLICIT_ONE:SCALABLE +SHL BASE SHIFT SHL_MEMb_CL_D2r4 I86 BYTEOP +SHL BASE SHIFT SHL_MEMb_CL_D2r6 I86 BYTEOP +SHL BASE SHIFT SHL_MEMb_IMMb_C0r4 I186 BYTEOP +SHL BASE SHIFT SHL_MEMb_IMMb_C0r6 I186 BYTEOP +SHL BASE SHIFT SHL_MEMb_ONE_D0r4 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_MEMb_ONE_D0r6 I86 BYTEOP:IMPLICIT_ONE +SHL BASE SHIFT SHL_MEMv_CL_D3r4 I86 SCALABLE +SHL BASE SHIFT SHL_MEMv_CL_D3r6 I86 SCALABLE +SHL BASE SHIFT SHL_MEMv_IMMb_C1r4 I186 SCALABLE +SHL BASE SHIFT SHL_MEMv_IMMb_C1r6 I186 SCALABLE +SHL BASE SHIFT SHL_MEMv_ONE_D1r4 I86 IMPLICIT_ONE:SCALABLE +SHL BASE SHIFT SHL_MEMv_ONE_D1r6 I86 IMPLICIT_ONE:SCALABLE +SHRD BASE SHIFT SHRD_GPRv_GPRv_CL I386 SCALABLE +SHRD BASE SHIFT SHRD_GPRv_GPRv_IMMb I386 SCALABLE +SHRD BASE SHIFT SHRD_MEMv_GPRv_CL I386 SCALABLE +SHRD BASE SHIFT SHRD_MEMv_GPRv_IMMb I386 SCALABLE +SHRX BMI2 BMI2 SHRX_VGPR32d_MEMd_VGPR32d BMI2 INVALID +SHRX BMI2 BMI2 SHRX_VGPR32d_VGPR32d_VGPR32d BMI2 INVALID +SHRX BMI2 BMI2 SHRX_VGPR64q_MEMq_VGPR64q BMI2 INVALID +SHRX BMI2 BMI2 SHRX_VGPR64q_VGPR64q_VGPR64q BMI2 INVALID +SHR BASE SHIFT SHR_GPR8_CL I86 BYTEOP +SHR BASE SHIFT SHR_GPR8_IMMb I186 BYTEOP +SHR BASE SHIFT SHR_GPR8_ONE I86 BYTEOP:IMPLICIT_ONE +SHR BASE SHIFT SHR_GPRv_CL I86 SCALABLE +SHR BASE SHIFT SHR_GPRv_IMMb I186 SCALABLE +SHR BASE SHIFT SHR_GPRv_ONE I86 IMPLICIT_ONE:SCALABLE +SHR BASE SHIFT SHR_MEMb_CL I86 BYTEOP +SHR BASE SHIFT SHR_MEMb_IMMb I186 BYTEOP +SHR BASE SHIFT SHR_MEMb_ONE I86 BYTEOP:IMPLICIT_ONE +SHR BASE SHIFT SHR_MEMv_CL I86 SCALABLE +SHR BASE SHIFT SHR_MEMv_IMMb I186 SCALABLE +SHR BASE SHIFT SHR_MEMv_ONE I86 IMPLICIT_ONE:SCALABLE +SHUFPD SSE2 SSE SHUFPD_XMMpd_MEMpd_IMMb SSE2 REQUIRES_ALIGNMENT +SHUFPD SSE2 SSE SHUFPD_XMMpd_XMMpd_IMMb SSE2 REQUIRES_ALIGNMENT +SHUFPS SSE SSE SHUFPS_XMMps_MEMps_IMMb SSE REQUIRES_ALIGNMENT +SHUFPS SSE SSE SHUFPS_XMMps_XMMps_IMMb SSE REQUIRES_ALIGNMENT +SIDT BASE SYSTEM SIDT_MEMs I286REAL NOTSX:SCALABLE +SIDT BASE SYSTEM SIDT_MEMs64 I286REAL INVALID +SKINIT SVM SYSTEM SKINIT_EAX SVM PROTECTED_MODE:AMDONLY +SLDT BASE SYSTEM SLDT_GPRv I286PROTECTED PROTECTED_MODE:NOTSX:SCALABLE +SLDT BASE SYSTEM SLDT_MEMw I286PROTECTED PROTECTED_MODE:NOTSX +SLWPCB XOP XOP SLWPCB_VGPRyy LWP AMDONLY:SCALABLE +SMSW BASE SYSTEM SMSW_GPRv I286REAL SCALABLE +SMSW BASE SYSTEM SMSW_MEMw I286REAL INVALID +SQRTPD SSE2 SSE SQRTPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SQRTPD SSE2 SSE SQRTPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SQRTPS SSE SSE SQRTPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +SQRTPS SSE SSE SQRTPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +SQRTSD SSE2 SSE SQRTSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +SQRTSD SSE2 SSE SQRTSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +SQRTSS SSE SSE SQRTSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +SQRTSS SSE SSE SQRTSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +STAC SMAP SMAP STAC SMAP INVALID +STC BASE FLAGOP STC I86 INVALID +STD BASE FLAGOP STD I86 NOTSX_COND +STGI SVM SYSTEM STGI SVM PROTECTED_MODE:AMDONLY +STI BASE FLAGOP STI I86 NOTSX +STMXCSR SSE SSE STMXCSR_MEMd SSEMXCSR MXCSR_RD +STOSB BASE STRINGOP STOSB I86 FIXED_BASE0:BYTEOP +STOSD BASE STRINGOP STOSD I386 FIXED_BASE0 +STOSQ LONGMODE STRINGOP STOSQ LONGMODE FIXED_BASE0 +STOSW BASE STRINGOP STOSW I86 FIXED_BASE0 +STR BASE SYSTEM STR_GPRv I286PROTECTED PROTECTED_MODE:NOTSX:SCALABLE +STR BASE SYSTEM STR_MEMw I286PROTECTED PROTECTED_MODE:NOTSX +STTILECFG AMX_TILE AMX_TILE STTILECFG_MEM AMX_TILE NOTSX +STUI UINTR UINTR STUI UINTR INVALID +SUBPD SSE2 SSE SUBPD_XMMpd_MEMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SUBPD SSE2 SSE SUBPD_XMMpd_XMMpd SSE2 REQUIRES_ALIGNMENT:MXCSR +SUBPS SSE SSE SUBPS_XMMps_MEMps SSE REQUIRES_ALIGNMENT:MXCSR +SUBPS SSE SSE SUBPS_XMMps_XMMps SSE REQUIRES_ALIGNMENT:MXCSR +SUBSD SSE2 SSE SUBSD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +SUBSD SSE2 SSE SUBSD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +SUBSS SSE SSE SUBSS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +SUBSS SSE SSE SUBSS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +SUB BASE BINARY SUB_AL_IMMb I86 BYTEOP +SUB BASE BINARY SUB_GPR8_GPR8_28 I86 BYTEOP +SUB BASE BINARY SUB_GPR8_GPR8_2A I86 BYTEOP +SUB BASE BINARY SUB_GPR8_IMMb_80r5 I86 BYTEOP +SUB BASE BINARY SUB_GPR8_IMMb_82r5 I86 BYTEOP +SUB BASE BINARY SUB_GPR8_MEMb I86 BYTEOP +SUB BASE BINARY SUB_GPRv_GPRv_29 I86 SCALABLE +SUB BASE BINARY SUB_GPRv_GPRv_2B I86 SCALABLE +SUB BASE BINARY SUB_GPRv_IMMb I86 SCALABLE +SUB BASE BINARY SUB_GPRv_IMMz I86 SCALABLE +SUB BASE BINARY SUB_GPRv_MEMv I86 SCALABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMb_IMMb_80r5 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMb_IMMb_82r5 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SUB_LOCK BASE BINARY SUB_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +SUB BASE BINARY SUB_MEMb_GPR8 I86 BYTEOP:LOCKABLE +SUB BASE BINARY SUB_MEMb_IMMb_80r5 I86 BYTEOP:LOCKABLE +SUB BASE BINARY SUB_MEMb_IMMb_82r5 I86 BYTEOP:LOCKABLE +SUB BASE BINARY SUB_MEMv_GPRv I86 LOCKABLE:SCALABLE +SUB BASE BINARY SUB_MEMv_IMMb I86 LOCKABLE:SCALABLE +SUB BASE BINARY SUB_MEMv_IMMz I86 LOCKABLE:SCALABLE +SUB BASE BINARY SUB_OrAX_IMMz I86 SCALABLE +SWAPGS LONGMODE SYSTEM SWAPGS LONGMODE RING0:NOTSX +SYSCALL LONGMODE SYSCALL SYSCALL LONGMODE NOTSX +SYSCALL_AMD BASE SYSCALL SYSCALL_AMD AMD AMDONLY +SYSENTER BASE SYSCALL SYSENTER PPRO PROTECTED_MODE:NOTSX +SYSEXIT BASE SYSRET SYSEXIT PPRO PROTECTED_MODE:RING0:NOTSX +SYSRET LONGMODE SYSRET SYSRET LONGMODE PROTECTED_MODE:RING0:NOTSX +SYSRET64 LONGMODE SYSRET SYSRET64 LONGMODE PROTECTED_MODE:RING0:NOTSX +SYSRET_AMD BASE SYSRET SYSRET_AMD AMD PROTECTED_MODE:RING0:AMDONLY +T1MSKC TBM TBM T1MSKC_VGPR32d_MEMd TBM AMDONLY +T1MSKC TBM TBM T1MSKC_VGPR32d_VGPR32d TBM AMDONLY +T1MSKC TBM TBM T1MSKC_VGPRyy_MEMy TBM AMDONLY:SCALABLE +T1MSKC TBM TBM T1MSKC_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +TDCALL TDX LEGACY TDCALL TDX NOTSX +TDPBF16PS AMX_BF16 AMX_TILE TDPBF16PS_TMMf32_TMMu32_TMMu32 AMX_BF16 NOTSX +TDPBSSD AMX_INT8 AMX_TILE TDPBSSD_TMMi32_TMMu32_TMMu32 AMX_INT8 NOTSX +TDPBSUD AMX_INT8 AMX_TILE TDPBSUD_TMMi32_TMMu32_TMMu32 AMX_INT8 NOTSX +TDPBUSD AMX_INT8 AMX_TILE TDPBUSD_TMMi32_TMMu32_TMMu32 AMX_INT8 NOTSX +TDPBUUD AMX_INT8 AMX_TILE TDPBUUD_TMMu32_TMMu32_TMMu32 AMX_INT8 NOTSX +TESTUI UINTR UINTR TESTUI UINTR INVALID +TEST BASE LOGICAL TEST_AL_IMMb I86 BYTEOP +TEST BASE LOGICAL TEST_GPR8_GPR8 I86 BYTEOP +TEST BASE LOGICAL TEST_GPR8_IMMb_F6r0 I86 BYTEOP +TEST BASE LOGICAL TEST_GPR8_IMMb_F6r1 I86 BYTEOP +TEST BASE LOGICAL TEST_GPRv_GPRv I86 SCALABLE +TEST BASE LOGICAL TEST_GPRv_IMMz_F7r0 I86 SCALABLE +TEST BASE LOGICAL TEST_GPRv_IMMz_F7r1 I86 SCALABLE +TEST BASE LOGICAL TEST_MEMb_GPR8 I86 BYTEOP +TEST BASE LOGICAL TEST_MEMb_IMMb_F6r0 I86 BYTEOP +TEST BASE LOGICAL TEST_MEMb_IMMb_F6r1 I86 BYTEOP +TEST BASE LOGICAL TEST_MEMv_GPRv I86 SCALABLE +TEST BASE LOGICAL TEST_MEMv_IMMz_F7r0 I86 SCALABLE +TEST BASE LOGICAL TEST_MEMv_IMMz_F7r1 I86 SCALABLE +TEST BASE LOGICAL TEST_OrAX_IMMz I86 SCALABLE +TILELOADDT1 AMX_TILE AMX_TILE TILELOADDT1_TMMu32_MEMu32 AMX_TILE NOTSX:SPECIAL_AGEN_REQUIRED +TILELOADD AMX_TILE AMX_TILE TILELOADD_TMMu32_MEMu32 AMX_TILE NOTSX:SPECIAL_AGEN_REQUIRED +TILERELEASE AMX_TILE AMX_TILE TILERELEASE AMX_TILE NOTSX +TILESTORED AMX_TILE AMX_TILE TILESTORED_MEMu32_TMMu32 AMX_TILE NOTSX:SPECIAL_AGEN_REQUIRED +TILEZERO AMX_TILE AMX_TILE TILEZERO_TMMu32 AMX_TILE NOTSX +TLBSYNC AMD_INVLPGB SYSTEM TLBSYNC AMD_INVLPGB AMDONLY +TPAUSE WAITPKG WAITPKG TPAUSE_GPR32u32 WAITPKG INVALID +TZCNT BMI1 BMI1 TZCNT_GPRv_GPRv BMI1 SCALABLE +TZCNT BMI1 BMI1 TZCNT_GPRv_MEMv BMI1 SCALABLE +TZMSK TBM TBM TZMSK_VGPR32d_MEMd TBM AMDONLY +TZMSK TBM TBM TZMSK_VGPR32d_VGPR32d TBM AMDONLY +TZMSK TBM TBM TZMSK_VGPRyy_MEMy TBM AMDONLY:SCALABLE +TZMSK TBM TBM TZMSK_VGPRyy_VGPRyy TBM AMDONLY:SCALABLE +UCOMISD SSE2 SSE UCOMISD_XMMsd_MEMsd SSE2 SIMD_SCALAR:MXCSR +UCOMISD SSE2 SSE UCOMISD_XMMsd_XMMsd SSE2 SIMD_SCALAR:MXCSR +UCOMISS SSE SSE UCOMISS_XMMss_MEMss SSE SIMD_SCALAR:MXCSR +UCOMISS SSE SSE UCOMISS_XMMss_XMMss SSE SIMD_SCALAR:MXCSR +UD0 BASE MISC UD0 PPRO_UD0_SHORT NOTSX +UD0 BASE MISC UD0_GPR32_GPR32 PPRO_UD0_LONG NOTSX +UD0 BASE MISC UD0_GPR32_MEMd PPRO_UD0_LONG NOTSX +UD1 BASE MISC UD1_GPR32_GPR32 PPRO NOTSX +UD1 BASE MISC UD1_GPR32_MEMd PPRO NOTSX +UD2 BASE MISC UD2 PPRO NOTSX +UIRET UINTR UINTR UIRET UINTR FIXED_BASE0:STACKPOP0:SCALABLE +UMONITOR WAITPKG WAITPKG UMONITOR_GPRa WAITPKG NOTSX +UMWAIT WAITPKG WAITPKG UMWAIT_GPR32 WAITPKG NOTSX +UNPCKHPD SSE2 SSE UNPCKHPD_XMMpd_MEMdq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKHPD SSE2 SSE UNPCKHPD_XMMpd_XMMq SSE2 SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKHPS SSE SSE UNPCKHPS_XMMps_MEMdq SSE SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKHPS SSE SSE UNPCKHPS_XMMps_XMMdq SSE SKIPLOW64:REQUIRES_ALIGNMENT +UNPCKLPD SSE2 SSE UNPCKLPD_XMMpd_MEMdq SSE2 REQUIRES_ALIGNMENT +UNPCKLPD SSE2 SSE UNPCKLPD_XMMpd_XMMq SSE2 REQUIRES_ALIGNMENT +UNPCKLPS SSE SSE UNPCKLPS_XMMps_MEMdq SSE REQUIRES_ALIGNMENT +UNPCKLPS SSE SSE UNPCKLPS_XMMps_XMMq SSE REQUIRES_ALIGNMENT +V4FMADDPS AVX512EVEX AVX512_4FMAPS V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512_4FMAPS_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MXCSR:MASKOP_EVEX +V4FMADDSS AVX512EVEX AVX512_4FMAPS V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512_4FMAPS_SCALAR DISP8_TUPLE1_4X:MXCSR:MULTISOURCE4:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR +V4FNMADDPS AVX512EVEX AVX512_4FMAPS V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512_4FMAPS_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MXCSR:MASKOP_EVEX +V4FNMADDSS AVX512EVEX AVX512_4FMAPS V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512_4FMAPS_SCALAR DISP8_TUPLE1_4X:MXCSR:MULTISOURCE4:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR +VADDPD AVX AVX VADDPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDPD AVX AVX VADDPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDPD AVX512EVEX AVX512 VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPD AVX512EVEX AVX512 VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VADDPD AVX512EVEX AVX512 VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPD AVX512EVEX AVX512 VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VADDPD AVX AVX VADDPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDPD AVX AVX VADDPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VADDPD AVX512EVEX AVX512 VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPD AVX512EVEX AVX512 VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VADDPH AVX512EVEX FP16 VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VADDPS AVX AVX VADDPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDPS AVX AVX VADDPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDPS AVX512EVEX AVX512 VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPS AVX512EVEX AVX512 VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VADDPS AVX512EVEX AVX512 VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPS AVX512EVEX AVX512 VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VADDPS AVX AVX VADDPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDPS AVX AVX VADDPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VADDPS AVX512EVEX AVX512 VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VADDPS AVX512EVEX AVX512 VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VADDSD AVX AVX VADDSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VADDSD AVX AVX VADDSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VADDSD AVX512EVEX AVX512 VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VADDSD AVX512EVEX AVX512 VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VADDSH AVX512EVEX FP16 VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VADDSH AVX512EVEX FP16 VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VADDSS AVX AVX VADDSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VADDSS AVX AVX VADDSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VADDSS AVX512EVEX AVX512 VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VADDSS AVX512EVEX AVX512 VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VADDSUBPD AVX AVX VADDSUBPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDSUBPD AVX AVX VADDSUBPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDSUBPD AVX AVX VADDSUBPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDSUBPD AVX AVX VADDSUBPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VADDSUBPS AVX AVX VADDSUBPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VAESDECLAST AVXAES AES VAESDECLAST_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESDECLAST AVXAES AES VAESDECLAST_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESDECLAST AVX512EVEX VAES VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESDECLAST VAES VAES VAESDECLAST_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESDECLAST VAES VAES VAESDECLAST_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESDECLAST AVX512EVEX VAES VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESDECLAST AVX512EVEX VAES VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESDEC AVXAES AES VAESDEC_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESDEC AVXAES AES VAESDEC_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESDEC AVX512EVEX VAES VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESDEC AVX512EVEX VAES VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESDEC VAES VAES VAESDEC_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESDEC AVX512EVEX VAES VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESDEC VAES VAES VAESDEC_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESDEC AVX512EVEX VAES VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESDEC AVX512EVEX VAES VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESDEC AVX512EVEX VAES VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESENCLAST AVXAES AES VAESENCLAST_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESENCLAST AVXAES AES VAESENCLAST_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESENCLAST AVX512EVEX VAES VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESENCLAST VAES VAES VAESENCLAST_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESENCLAST VAES VAES VAESENCLAST_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESENCLAST AVX512EVEX VAES VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESENCLAST AVX512EVEX VAES VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESENC AVXAES AES VAESENC_XMMdq_XMMdq_MEMdq AVXAES INVALID +VAESENC AVXAES AES VAESENC_XMMdq_XMMdq_XMMdq AVXAES INVALID +VAESENC AVX512EVEX VAES VAESENC_XMMu128_XMMu128_MEMu128_AVX512 AVX512_VAES_128 DISP8_FULLMEM +VAESENC AVX512EVEX VAES VAESENC_XMMu128_XMMu128_XMMu128_AVX512 AVX512_VAES_128 INVALID +VAESENC VAES VAES VAESENC_YMMu128_YMMu128_MEMu128 VAES INVALID +VAESENC AVX512EVEX VAES VAESENC_YMMu128_YMMu128_MEMu128_AVX512 AVX512_VAES_256 DISP8_FULLMEM +VAESENC VAES VAES VAESENC_YMMu128_YMMu128_YMMu128 VAES INVALID +VAESENC AVX512EVEX VAES VAESENC_YMMu128_YMMu128_YMMu128_AVX512 AVX512_VAES_256 INVALID +VAESENC AVX512EVEX VAES VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 AVX512_VAES_512 DISP8_FULLMEM +VAESENC AVX512EVEX VAES VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 AVX512_VAES_512 INVALID +VAESIMC AVXAES AES VAESIMC_XMMdq_MEMdq AVXAES INVALID +VAESIMC AVXAES AES VAESIMC_XMMdq_XMMdq AVXAES INVALID +VAESKEYGENASSIST AVXAES AES VAESKEYGENASSIST_XMMdq_MEMdq_IMMb AVXAES INVALID +VAESKEYGENASSIST AVXAES AES VAESKEYGENASSIST_XMMdq_XMMdq_IMMb AVXAES INVALID +VALIGND AVX512EVEX AVX512 VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGND AVX512EVEX AVX512 VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VALIGND AVX512EVEX AVX512 VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGND AVX512EVEX AVX512 VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VALIGND AVX512EVEX AVX512 VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGND AVX512EVEX AVX512 VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VALIGNQ AVX512EVEX AVX512 VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGNQ AVX512EVEX AVX512 VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VALIGNQ AVX512EVEX AVX512 VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGNQ AVX512EVEX AVX512 VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VALIGNQ AVX512EVEX AVX512 VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VALIGNQ AVX512EVEX AVX512 VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VANDNPD AVX LOGICAL_FP VANDNPD_XMMdq_XMMdq_MEMdq AVX INVALID +VANDNPD AVX LOGICAL_FP VANDNPD_XMMdq_XMMdq_XMMdq AVX INVALID +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDNPD AVX LOGICAL_FP VANDNPD_YMMqq_YMMqq_MEMqq AVX INVALID +VANDNPD AVX LOGICAL_FP VANDNPD_YMMqq_YMMqq_YMMqq AVX INVALID +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPD AVX512EVEX LOGICAL_FP VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VANDNPS AVX LOGICAL_FP VANDNPS_XMMdq_XMMdq_MEMdq AVX INVALID +VANDNPS AVX LOGICAL_FP VANDNPS_XMMdq_XMMdq_XMMdq AVX INVALID +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDNPS AVX LOGICAL_FP VANDNPS_YMMqq_YMMqq_MEMqq AVX INVALID +VANDNPS AVX LOGICAL_FP VANDNPS_YMMqq_YMMqq_YMMqq AVX INVALID +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDNPS AVX512EVEX LOGICAL_FP VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VANDPD AVX LOGICAL_FP VANDPD_XMMdq_XMMdq_MEMdq AVX INVALID +VANDPD AVX LOGICAL_FP VANDPD_XMMdq_XMMdq_XMMdq AVX INVALID +VANDPD AVX512EVEX LOGICAL_FP VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPD AVX512EVEX LOGICAL_FP VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDPD AVX LOGICAL_FP VANDPD_YMMqq_YMMqq_MEMqq AVX INVALID +VANDPD AVX LOGICAL_FP VANDPD_YMMqq_YMMqq_YMMqq AVX INVALID +VANDPD AVX512EVEX LOGICAL_FP VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPD AVX512EVEX LOGICAL_FP VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDPD AVX512EVEX LOGICAL_FP VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPD AVX512EVEX LOGICAL_FP VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VANDPS AVX LOGICAL_FP VANDPS_XMMdq_XMMdq_MEMdq AVX INVALID +VANDPS AVX LOGICAL_FP VANDPS_XMMdq_XMMdq_XMMdq AVX INVALID +VANDPS AVX512EVEX LOGICAL_FP VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPS AVX512EVEX LOGICAL_FP VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VANDPS AVX LOGICAL_FP VANDPS_YMMqq_YMMqq_MEMqq AVX INVALID +VANDPS AVX LOGICAL_FP VANDPS_YMMqq_YMMqq_YMMqq AVX INVALID +VANDPS AVX512EVEX LOGICAL_FP VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPS AVX512EVEX LOGICAL_FP VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VANDPS AVX512EVEX LOGICAL_FP VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VANDPS AVX512EVEX LOGICAL_FP VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPD AVX512EVEX BLEND VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VBLENDMPS AVX512EVEX BLEND VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VBLENDPD AVX AVX VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VBLENDPD AVX AVX VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VBLENDPD AVX AVX VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VBLENDPD AVX AVX VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VBLENDPS AVX AVX VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq AVX INVALID +VBLENDVPD AVX AVX VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq AVX INVALID +VBLENDVPS AVX AVX VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq AVX INVALID +VBROADCASTF128 AVX BROADCAST VBROADCASTF128_YMMqq_MEMdq AVX INVALID +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF32X2 AVX512EVEX BROADCAST VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX +VBROADCASTF32X4 AVX512EVEX BROADCAST VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTF32X4 AVX512EVEX BROADCAST VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTF32X8 AVX512EVEX BROADCAST VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE8 +VBROADCASTF64X2 AVX512EVEX BROADCAST VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF64X2 AVX512EVEX BROADCAST VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTF64X4 AVX512EVEX BROADCAST VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTI128 AVX2 BROADCAST VBROADCASTI128_YMMqq_MEMdq AVX2 INVALID +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI32X2 AVX512EVEX BROADCAST VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VBROADCASTI32X4 AVX512EVEX BROADCAST VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTI32X4 AVX512EVEX BROADCAST VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTI32X8 AVX512EVEX BROADCAST VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE8 +VBROADCASTI64X2 AVX512EVEX BROADCAST VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI64X2 AVX512EVEX BROADCAST VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE2 +VBROADCASTI64X4 AVX512EVEX BROADCAST VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE4 +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VBROADCASTSD AVX BROADCAST VBROADCASTSD_YMMqq_MEMq AVX INVALID +VBROADCASTSD AVX2 BROADCAST VBROADCASTSD_YMMqq_XMMdq AVX2 INVALID +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSD AVX512EVEX BROADCAST VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VBROADCASTSS AVX BROADCAST VBROADCASTSS_XMMdq_MEMd AVX INVALID +VBROADCASTSS AVX2 BROADCAST VBROADCASTSS_XMMdq_XMMdq AVX2 INVALID +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VBROADCASTSS AVX BROADCAST VBROADCASTSS_YMMqq_MEMd AVX INVALID +VBROADCASTSS AVX2 BROADCAST VBROADCASTSS_YMMqq_XMMdq AVX2 INVALID +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VBROADCASTSS AVX512EVEX BROADCAST VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPD AVX512EVEX AVX512 VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCMPPD AVX AVX VCMPPD_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VCMPPD AVX AVX VCMPPD_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VCMPPD AVX AVX VCMPPD_YMMqq_YMMqq_MEMqq_IMMb AVX MXCSR +VCMPPD AVX AVX VCMPPD_YMMqq_YMMqq_YMMqq_IMMb AVX MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCMPPH AVX512EVEX FP16 VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCMPPS AVX512EVEX AVX512 VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCMPPS AVX AVX VCMPPS_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VCMPPS AVX AVX VCMPPS_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VCMPPS AVX AVX VCMPPS_YMMqq_YMMqq_MEMqq_IMMb AVX MXCSR +VCMPPS AVX AVX VCMPPS_YMMqq_YMMqq_YMMqq_IMMb AVX MXCSR +VCMPSD AVX512EVEX AVX512 VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCMPSD AVX512EVEX AVX512 VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCMPSD AVX AVX VCMPSD_XMMdq_XMMdq_MEMq_IMMb AVX SIMD_SCALAR:MXCSR +VCMPSD AVX AVX VCMPSD_XMMdq_XMMdq_XMMq_IMMb AVX SIMD_SCALAR:MXCSR +VCMPSH AVX512EVEX FP16 VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VCMPSH AVX512EVEX FP16 VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCMPSS AVX512EVEX AVX512 VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCMPSS AVX512EVEX AVX512 VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCMPSS AVX AVX VCMPSS_XMMdq_XMMdq_MEMd_IMMb AVX SIMD_SCALAR:MXCSR +VCMPSS AVX AVX VCMPSS_XMMdq_XMMdq_XMMd_IMMb AVX SIMD_SCALAR:MXCSR +VCOMISD AVX512EVEX AVX512 VCOMISD_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCOMISD AVX512EVEX AVX512 VCOMISD_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCOMISD AVX AVX VCOMISD_XMMq_MEMq AVX SIMD_SCALAR:MXCSR +VCOMISD AVX AVX VCOMISD_XMMq_XMMq AVX SIMD_SCALAR:MXCSR +VCOMISH AVX512EVEX FP16 VCOMISH_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MXCSR:SIMD_SCALAR +VCOMISH AVX512EVEX FP16 VCOMISH_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCOMISS AVX AVX VCOMISS_XMMd_MEMd AVX SIMD_SCALAR:MXCSR +VCOMISS AVX AVX VCOMISS_XMMd_XMMd AVX SIMD_SCALAR:MXCSR +VCOMISS AVX512EVEX AVX512 VCOMISS_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCOMISS AVX512EVEX AVX512 VCOMISS_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VCOMPRESSPD AVX512EVEX COMPRESS VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VCOMPRESSPS AVX512EVEX COMPRESS VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_XMMdq_MEMq AVX INVALID +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_XMMdq_XMMq AVX INVALID +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_YMMqq_MEMdq AVX INVALID +VCVTDQ2PD AVX CONVERT VCVTDQ2PD_YMMqq_XMMdq AVX INVALID +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTDQ2PD AVX512EVEX CONVERT VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTDQ2PH AVX512EVEX CONVERT VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_XMMdq_MEMdq AVX MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_XMMdq_XMMdq AVX MXCSR +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_YMMqq_MEMqq AVX MXCSR +VCVTDQ2PS AVX CONVERT VCVTDQ2PS_YMMqq_YMMqq AVX MXCSR +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTDQ2PS AVX512EVEX CONVERT VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 AVX512_BF16_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 AVX512_BF16_128 MASKOP_EVEX +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 AVX512_BF16_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 AVX512_BF16_256 MASKOP_EVEX +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 AVX512_BF16_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNE2PS2BF16 AVX512EVEX CONVERT VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512_BF16_512 MASKOP_EVEX +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 AVX512_BF16_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 AVX512_BF16_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 AVX512_BF16_128 MASKOP_EVEX +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 AVX512_BF16_256 MASKOP_EVEX +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 AVX512_BF16_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VCVTNEPS2BF16 AVX512EVEX CONVERT VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 AVX512_BF16_512 MASKOP_EVEX +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_MEMdq AVX MXCSR +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_MEMqq AVX MXCSR +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_XMMdq AVX MXCSR +VCVTPD2DQ AVX CONVERT VCVTPD2DQ_XMMdq_YMMqq AVX MXCSR +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2DQ AVX512EVEX CONVERT VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPD2PH AVX512EVEX CONVERT VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_MEMdq AVX MXCSR +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_MEMqq AVX MXCSR +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_XMMdq AVX MXCSR +VCVTPD2PS AVX CONVERT VCVTPD2PS_XMMdq_YMMqq AVX MXCSR +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2PS AVX512EVEX CONVERT VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2QQ AVX512EVEX CONVERT VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UDQ AVX512EVEX CONVERT VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPD2UQQ AVX512EVEX CONVERT VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2DQ AVX512EVEX CONVERT VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PD AVX512EVEX CONVERT VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_FTZ +VCVTPH2PSX AVX512EVEX CONVERT VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_FTZ +VCVTPH2PS F16C CONVERT VCVTPH2PS_XMMdq_MEMq F16C MXCSR +VCVTPH2PS F16C CONVERT VCVTPH2PS_XMMdq_XMMq F16C MXCSR +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPH2PS F16C CONVERT VCVTPH2PS_YMMqq_MEMdq F16C MXCSR +VCVTPH2PS F16C CONVERT VCVTPH2PS_YMMqq_XMMdq F16C MXCSR +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPH2PS AVX512EVEX CONVERT VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2QQ AVX512EVEX CONVERT VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UDQ AVX512EVEX CONVERT VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UQQ AVX512EVEX CONVERT VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2UW AVX512EVEX CONVERT VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTPH2W AVX512EVEX CONVERT VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_XMMdq_MEMdq AVX MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_XMMdq_XMMdq AVX MXCSR +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_YMMqq_MEMqq AVX MXCSR +VCVTPS2DQ AVX CONVERT VCVTPS2DQ_YMMqq_YMMqq AVX MXCSR +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2DQ AVX512EVEX CONVERT VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_XMMdq_MEMq AVX MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_XMMdq_XMMq AVX MXCSR +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_YMMqq_MEMdq AVX MXCSR +VCVTPS2PD AVX CONVERT VCVTPS2PD_YMMqq_XMMdq AVX MXCSR +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2PD AVX512EVEX CONVERT VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:USES_DAZ +VCVTPS2PHX AVX512EVEX CONVERT VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:USES_DAZ +VCVTPS2PH F16C CONVERT VCVTPS2PH_MEMdq_YMMqq_IMMb F16C MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:DISP8_HALFMEM +VCVTPS2PH F16C CONVERT VCVTPS2PH_MEMq_XMMdq_IMMb F16C MXCSR +VCVTPS2PH F16C CONVERT VCVTPS2PH_XMMdq_YMMqq_IMMb F16C MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2PH F16C CONVERT VCVTPS2PH_XMMq_XMMdq_IMMb F16C MXCSR +VCVTPS2PH AVX512EVEX CONVERT VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2QQ AVX512EVEX CONVERT VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTPS2UDQ AVX512EVEX CONVERT VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTPS2UQQ AVX512EVEX CONVERT VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PD AVX512EVEX CONVERT VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTQQ2PH AVX512EVEX CONVERT VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTQQ2PS AVX512EVEX CONVERT VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTSD2SH AVX512EVEX CONVERT VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSD2SH AVX512EVEX CONVERT VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR32d_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR32d_XMMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR32i32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR32i32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR64i64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2SI AVX512EVEX CONVERT VCVTSD2SI_GPR64i64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR64q_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SI AVX CONVERT VCVTSD2SI_GPR64q_XMMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SS AVX CONVERT VCVTSD2SS_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SS AVX CONVERT VCVTSD2SS_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VCVTSD2SS AVX512EVEX CONVERT VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCVTSD2SS AVX512EVEX CONVERT VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR32u32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR32u32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR64u64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTSD2USI AVX512EVEX CONVERT VCVTSD2USI_GPR64u64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2SD AVX512EVEX CONVERT VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2SD AVX512EVEX CONVERT VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR32i32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR32i32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR64i64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2SI AVX512EVEX CONVERT VCVTSH2SI_GPR64i64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2SS AVX512EVEX CONVERT VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2SS AVX512EVEX CONVERT VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_FTZ +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR32u32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR32u32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR64u64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSH2USI AVX512EVEX CONVERT VCVTSH2USI_GPR64u64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_GPR32d AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_GPR64q AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX CONVERT VCVTSI2SD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 AVX512F_SCALAR SIMD_SCALAR +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 AVX512F_SCALAR SIMD_SCALAR:DISP8_GPR_READER +VCVTSI2SD AVX512EVEX CONVERT VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTSI2SH AVX512EVEX CONVERT VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_GPR32d AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_GPR64q AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX CONVERT VCVTSI2SS_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTSI2SS AVX512EVEX CONVERT VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTSS2SD AVX CONVERT VCVTSS2SD_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SD AVX CONVERT VCVTSS2SD_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SD AVX512EVEX CONVERT VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VCVTSS2SD AVX512EVEX CONVERT VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VCVTSS2SH AVX512EVEX CONVERT VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSS2SH AVX512EVEX CONVERT VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR:USES_DAZ +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR32d_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR32d_XMMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR32i32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR32i32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR64i64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2SI AVX512EVEX CONVERT VCVTSS2SI_GPR64i64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR64q_MEMd AVX SIMD_SCALAR:MXCSR +VCVTSS2SI AVX CONVERT VCVTSS2SI_GPR64q_XMMd AVX SIMD_SCALAR:MXCSR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR32u32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR32u32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR64u64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTSS2USI AVX512EVEX CONVERT VCVTSS2USI_GPR64u64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_MEMdq AVX MXCSR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_MEMqq AVX MXCSR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_XMMdq AVX MXCSR +VCVTTPD2DQ AVX CONVERT VCVTTPD2DQ_XMMdq_YMMqq AVX MXCSR +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2DQ AVX512EVEX CONVERT VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2QQ AVX512EVEX CONVERT VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UDQ AVX512EVEX CONVERT VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPD2UQQ AVX512EVEX CONVERT VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2DQ AVX512EVEX CONVERT VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2QQ AVX512EVEX CONVERT VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_HALF:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UDQ AVX512EVEX CONVERT VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_QUARTER:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UQQ AVX512EVEX CONVERT VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2UW AVX512EVEX CONVERT VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTTPH2W AVX512EVEX CONVERT VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_XMMdq_MEMdq AVX MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_XMMdq_XMMdq AVX MXCSR +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_YMMqq_MEMqq AVX MXCSR +VCVTTPS2DQ AVX CONVERT VCVTTPS2DQ_YMMqq_YMMqq AVX MXCSR +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2DQ AVX512EVEX CONVERT VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2QQ AVX512EVEX CONVERT VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTTPS2UDQ AVX512EVEX CONVERT VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:MXCSR:BROADCAST_ENABLED +VCVTTPS2UQQ AVX512EVEX CONVERT VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR32d_MEMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR32d_XMMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR32i32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR32i32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR64i64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2SI AVX512EVEX CONVERT VCVTTSD2SI_GPR64i64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR64q_MEMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2SI AVX CONVERT VCVTTSD2SI_GPR64q_XMMq AVX SIMD_SCALAR:MXCSR +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR32u32_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR32u32_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR64u64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_WRITER_LDOP_Q +VCVTTSD2USI AVX512EVEX CONVERT VCVTTSD2USI_GPR64u64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR32i32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR32i32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR64i64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2SI AVX512EVEX CONVERT VCVTTSH2SI_GPR64i64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR32u32_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR32u32_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR64u64_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSH2USI AVX512EVEX CONVERT VCVTTSH2USI_GPR64u64_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR32d_MEMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR32d_XMMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR32i32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR32i32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR64i64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX512EVEX CONVERT VCVTTSS2SI_GPR64i64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR64q_MEMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2SI AVX CONVERT VCVTTSS2SI_GPR64q_XMMd AVX SIMD_SCALAR:MXCSR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR32u32_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR32u32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR64u64_MEMf32_AVX512 AVX512F_SCALAR DISP8_GPR_WRITER_LDOP_D:MXCSR:SIMD_SCALAR +VCVTTSS2USI AVX512EVEX CONVERT VCVTTSS2USI_GPR64u64_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALF:BROADCAST_ENABLED +VCVTUDQ2PD AVX512EVEX CONVERT VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUDQ2PH AVX512EVEX CONVERT VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUDQ2PS AVX512EVEX CONVERT VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PD AVX512EVEX CONVERT VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTUQQ2PH AVX512EVEX CONVERT VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 AVX512DQ_128 MASKOP_EVEX:MXCSR +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 AVX512DQ_256 MASKOP_EVEX:MXCSR +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VCVTUQQ2PS AVX512EVEX CONVERT VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 AVX512F_SCALAR SIMD_SCALAR +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 AVX512F_SCALAR SIMD_SCALAR:DISP8_GPR_READER +VCVTUSI2SD AVX512EVEX CONVERT VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTUSI2SH AVX512EVEX CONVERT VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 AVX512_FP16_SCALAR DISP8_GPR_READER:MXCSR:SIMD_SCALAR +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTUSI2SS AVX512EVEX CONVERT VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_GPR_READER +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTUW2PH AVX512EVEX CONVERT VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VCVTW2PH AVX512EVEX CONVERT VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VDBPSADBW AVX512EVEX AVX512 VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VDIVPD AVX AVX VDIVPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VDIVPD AVX AVX VDIVPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VDIVPD AVX512EVEX AVX512 VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPD AVX512EVEX AVX512 VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VDIVPD AVX512EVEX AVX512 VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPD AVX512EVEX AVX512 VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VDIVPD AVX AVX VDIVPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VDIVPD AVX AVX VDIVPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VDIVPD AVX512EVEX AVX512 VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPD AVX512EVEX AVX512 VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VDIVPH AVX512EVEX FP16 VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VDIVPS AVX AVX VDIVPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VDIVPS AVX AVX VDIVPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VDIVPS AVX512EVEX AVX512 VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPS AVX512EVEX AVX512 VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VDIVPS AVX512EVEX AVX512 VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPS AVX512EVEX AVX512 VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VDIVPS AVX AVX VDIVPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VDIVPS AVX AVX VDIVPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VDIVPS AVX512EVEX AVX512 VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VDIVPS AVX512EVEX AVX512 VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VDIVSD AVX AVX VDIVSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VDIVSD AVX AVX VDIVSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VDIVSD AVX512EVEX AVX512 VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VDIVSD AVX512EVEX AVX512 VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VDIVSH AVX512EVEX FP16 VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VDIVSH AVX512EVEX FP16 VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VDIVSS AVX AVX VDIVSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VDIVSS AVX AVX VDIVSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VDIVSS AVX512EVEX AVX512 VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VDIVSS AVX512EVEX AVX512 VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_BF16_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_BF16_128 MASKOP_EVEX +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_BF16_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_BF16_256 MASKOP_EVEX +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_BF16_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VDPBF16PS AVX512EVEX AVX512 VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_BF16_512 MASKOP_EVEX +VDPPD AVX AVX VDPPD_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VDPPD AVX AVX VDPPD_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_XMMdq_XMMdq_MEMdq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_XMMdq_XMMdq_XMMdq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_YMMqq_YMMqq_MEMqq_IMMb AVX MXCSR +VDPPS AVX AVX VDPPS_YMMqq_YMMqq_YMMqq_IMMb AVX MXCSR +VERR BASE SYSTEM VERR_GPR16 I286PROTECTED PROTECTED_MODE +VERR BASE SYSTEM VERR_MEMw I286PROTECTED PROTECTED_MODE +VERW BASE SYSTEM VERW_GPR16 I286PROTECTED PROTECTED_MODE +VERW BASE SYSTEM VERW_MEMw I286PROTECTED PROTECTED_MODE +VEXP2PD AVX512EVEX AVX512 VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VEXP2PD AVX512EVEX AVX512 VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VEXP2PS AVX512EVEX AVX512 VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VEXP2PS AVX512EVEX AVX512 VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPD AVX512EVEX EXPAND VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VEXPANDPS AVX512EVEX EXPAND VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTF128 AVX AVX VEXTRACTF128_MEMdq_YMMdq_IMMb AVX INVALID +VEXTRACTF128 AVX AVX VEXTRACTF128_XMMdq_YMMdq_IMMb AVX INVALID +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VEXTRACTF32X4 AVX512EVEX AVX512 VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTF32X8 AVX512EVEX AVX512 VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VEXTRACTF32X8 AVX512EVEX AVX512 VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VEXTRACTF64X2 AVX512EVEX AVX512 VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTF64X4 AVX512EVEX AVX512 VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTF64X4 AVX512EVEX AVX512 VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTI128 AVX2 AVX2 VEXTRACTI128_MEMdq_YMMqq_IMMb AVX2 INVALID +VEXTRACTI128 AVX2 AVX2 VEXTRACTI128_XMMdq_YMMqq_IMMb AVX2 INVALID +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VEXTRACTI32X4 AVX512EVEX AVX512 VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTI32X8 AVX512EVEX AVX512 VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VEXTRACTI32X8 AVX512EVEX AVX512 VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VEXTRACTI64X2 AVX512EVEX AVX512 VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VEXTRACTI64X4 AVX512EVEX AVX512 VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VEXTRACTI64X4 AVX512EVEX AVX512 VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VEXTRACTPS AVX AVX VEXTRACTPS_GPR32_XMMdq_IMMb AVX INVALID +VEXTRACTPS AVX512EVEX AVX512 VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 AVX512F_128N INVALID +VEXTRACTPS AVX AVX VEXTRACTPS_MEMd_XMMdq_IMMb AVX INVALID +VEXTRACTPS AVX512EVEX AVX512 VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 AVX512F_128N DISP8_GPR_WRITER_STORE +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCPH AVX512EVEX FP16 VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMADDCSH AVX512EVEX FP16 VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFCMADDCSH AVX512EVEX FP16 VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFCMULCPH AVX512EVEX FP16 VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFCMULCSH AVX512EVEX FP16 VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFCMULCSH AVX512EVEX FP16 VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPD AVX512EVEX AVX512 VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFIXUPIMMPS AVX512EVEX AVX512 VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFIXUPIMMSD AVX512EVEX AVX512 VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFIXUPIMMSD AVX512EVEX AVX512 VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFIXUPIMMSS AVX512EVEX AVX512 VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFIXUPIMMSS AVX512EVEX AVX512 VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD132PD FMA VFMA VFMADD132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD132PD FMA VFMA VFMADD132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD132PD FMA VFMA VFMADD132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD132PD FMA VFMA VFMADD132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PD AVX512EVEX VFMA VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD132PH AVX512EVEX FP16 VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD132PS FMA VFMA VFMADD132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD132PS AVX512EVEX VFMA VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD132SD FMA VFMA VFMADD132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMADD132SD FMA VFMA VFMADD132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMADD132SD AVX512EVEX VFMA VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD132SD AVX512EVEX VFMA VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD132SH AVX512EVEX FP16 VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMADD132SH AVX512EVEX FP16 VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD132SS FMA VFMA VFMADD132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMADD132SS FMA VFMA VFMADD132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMADD132SS AVX512EVEX VFMA VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD132SS AVX512EVEX VFMA VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD213PD FMA VFMA VFMADD213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD213PD FMA VFMA VFMADD213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD213PD FMA VFMA VFMADD213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD213PD FMA VFMA VFMADD213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PD AVX512EVEX VFMA VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD213PH AVX512EVEX FP16 VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD213PS FMA VFMA VFMADD213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD213PS AVX512EVEX VFMA VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD213SD FMA VFMA VFMADD213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMADD213SD FMA VFMA VFMADD213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMADD213SD AVX512EVEX VFMA VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD213SD AVX512EVEX VFMA VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD213SH AVX512EVEX FP16 VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMADD213SH AVX512EVEX FP16 VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD213SS FMA VFMA VFMADD213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMADD213SS FMA VFMA VFMADD213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMADD213SS AVX512EVEX VFMA VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD213SS AVX512EVEX VFMA VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD231PD FMA VFMA VFMADD231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD231PD FMA VFMA VFMADD231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD231PD FMA VFMA VFMADD231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD231PD FMA VFMA VFMADD231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PD AVX512EVEX VFMA VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADD231PH AVX512EVEX FP16 VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADD231PS FMA VFMA VFMADD231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADD231PS AVX512EVEX VFMA VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADD231SD FMA VFMA VFMADD231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMADD231SD FMA VFMA VFMADD231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMADD231SD AVX512EVEX VFMA VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD231SD AVX512EVEX VFMA VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD231SH AVX512EVEX FP16 VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMADD231SH AVX512EVEX FP16 VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADD231SS FMA VFMA VFMADD231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMADD231SS FMA VFMA VFMADD231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMADD231SS AVX512EVEX VFMA VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMADD231SS AVX512EVEX VFMA VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMADDCPH AVX512EVEX FP16 VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMADDCSH AVX512EVEX FP16 VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFMADDCSH AVX512EVEX FP16 VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFMADDPD FMA4 FMA4 VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDPD FMA4 FMA4 VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDPS FMA4 FMA4 VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSD FMA4 FMA4 VFMADDSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSD FMA4 FMA4 VFMADDSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSD FMA4 FMA4 VFMADDSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSS FMA4 FMA4 VFMADDSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSS FMA4 FMA4 VFMADDSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSS FMA4 FMA4 VFMADDSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB132PD FMA VFMA VFMADDSUB132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PD AVX512EVEX VFMA VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB132PH AVX512EVEX FP16 VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB132PS FMA VFMA VFMADDSUB132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB132PS AVX512EVEX VFMA VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB213PD FMA VFMA VFMADDSUB213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PD AVX512EVEX VFMA VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB213PH AVX512EVEX FP16 VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB213PS FMA VFMA VFMADDSUB213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB213PS AVX512EVEX VFMA VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB231PD FMA VFMA VFMADDSUB231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PD AVX512EVEX VFMA VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMADDSUB231PH AVX512EVEX FP16 VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMADDSUB231PS FMA VFMA VFMADDSUB231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMADDSUB231PS AVX512EVEX VFMA VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPD FMA4 FMA4 VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMADDSUBPS FMA4 FMA4 VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUB132PD FMA VFMA VFMSUB132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB132PD FMA VFMA VFMSUB132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB132PD FMA VFMA VFMSUB132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB132PD FMA VFMA VFMSUB132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PD AVX512EVEX VFMA VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB132PH AVX512EVEX FP16 VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB132PS FMA VFMA VFMSUB132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB132PS AVX512EVEX VFMA VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB132SD FMA VFMA VFMSUB132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMSUB132SD FMA VFMA VFMSUB132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMSUB132SD AVX512EVEX VFMA VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB132SD AVX512EVEX VFMA VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB132SH AVX512EVEX FP16 VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMSUB132SH AVX512EVEX FP16 VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB132SS FMA VFMA VFMSUB132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMSUB132SS FMA VFMA VFMSUB132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMSUB132SS AVX512EVEX VFMA VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB132SS AVX512EVEX VFMA VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB213PD FMA VFMA VFMSUB213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB213PD FMA VFMA VFMSUB213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB213PD FMA VFMA VFMSUB213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB213PD FMA VFMA VFMSUB213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PD AVX512EVEX VFMA VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB213PH AVX512EVEX FP16 VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB213PS FMA VFMA VFMSUB213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB213PS AVX512EVEX VFMA VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB213SD FMA VFMA VFMSUB213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMSUB213SD FMA VFMA VFMSUB213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMSUB213SD AVX512EVEX VFMA VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB213SD AVX512EVEX VFMA VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB213SH AVX512EVEX FP16 VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMSUB213SH AVX512EVEX FP16 VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB213SS FMA VFMA VFMSUB213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMSUB213SS FMA VFMA VFMSUB213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMSUB213SS AVX512EVEX VFMA VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB213SS AVX512EVEX VFMA VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB231PD FMA VFMA VFMSUB231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB231PD FMA VFMA VFMSUB231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB231PD FMA VFMA VFMSUB231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB231PD FMA VFMA VFMSUB231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PD AVX512EVEX VFMA VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUB231PH AVX512EVEX FP16 VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUB231PS FMA VFMA VFMSUB231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUB231PS AVX512EVEX VFMA VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUB231SD FMA VFMA VFMSUB231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFMSUB231SD FMA VFMA VFMSUB231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFMSUB231SD AVX512EVEX VFMA VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB231SD AVX512EVEX VFMA VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB231SH AVX512EVEX FP16 VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFMSUB231SH AVX512EVEX FP16 VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUB231SS FMA VFMA VFMSUB231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFMSUB231SS FMA VFMA VFMSUB231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFMSUB231SS AVX512EVEX VFMA VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFMSUB231SS AVX512EVEX VFMA VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD132PD FMA VFMA VFMSUBADD132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PD AVX512EVEX VFMA VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD132PH AVX512EVEX FP16 VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD132PS FMA VFMA VFMSUBADD132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD132PS AVX512EVEX VFMA VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD213PD FMA VFMA VFMSUBADD213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PD AVX512EVEX VFMA VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD213PH AVX512EVEX FP16 VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD213PS FMA VFMA VFMSUBADD213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD213PS AVX512EVEX VFMA VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD231PD FMA VFMA VFMSUBADD231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PD AVX512EVEX VFMA VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFMSUBADD231PH AVX512EVEX FP16 VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFMSUBADD231PS FMA VFMA VFMSUBADD231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFMSUBADD231PS AVX512EVEX VFMA VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPD FMA4 FMA4 VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBADDPS FMA4 FMA4 VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBPD FMA4 FMA4 VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFMSUBPS FMA4 FMA4 VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFMSUBSD FMA4 FMA4 VFMSUBSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSD FMA4 FMA4 VFMSUBSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSD FMA4 FMA4 VFMSUBSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSS FMA4 FMA4 VFMSUBSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSS FMA4 FMA4 VFMSUBSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMSUBSS FMA4 FMA4 VFMSUBSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFMULCPH AVX512EVEX FP16 VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH +VFMULCPH AVX512EVEX FP16 VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH +VFMULCSH AVX512EVEX FP16 VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFMULCSH AVX512EVEX FP16 VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:NO_SRC_DEST_MATCH:SIMD_SCALAR +VFNMADD132PD FMA VFMA VFNMADD132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD132PD FMA VFMA VFNMADD132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD132PD FMA VFMA VFNMADD132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD132PD FMA VFMA VFNMADD132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PD AVX512EVEX VFMA VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD132PH AVX512EVEX FP16 VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD132PS FMA VFMA VFNMADD132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD132PS AVX512EVEX VFMA VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD132SD FMA VFMA VFNMADD132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMADD132SD FMA VFMA VFNMADD132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMADD132SD AVX512EVEX VFMA VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD132SD AVX512EVEX VFMA VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD132SH AVX512EVEX FP16 VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMADD132SH AVX512EVEX FP16 VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD132SS FMA VFMA VFNMADD132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMADD132SS FMA VFMA VFNMADD132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMADD132SS AVX512EVEX VFMA VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD132SS AVX512EVEX VFMA VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD213PD FMA VFMA VFNMADD213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD213PD FMA VFMA VFNMADD213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD213PD FMA VFMA VFNMADD213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD213PD FMA VFMA VFNMADD213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PD AVX512EVEX VFMA VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD213PH AVX512EVEX FP16 VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD213PS FMA VFMA VFNMADD213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD213PS AVX512EVEX VFMA VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD213SD FMA VFMA VFNMADD213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMADD213SD FMA VFMA VFNMADD213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMADD213SD AVX512EVEX VFMA VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD213SD AVX512EVEX VFMA VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD213SH AVX512EVEX FP16 VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMADD213SH AVX512EVEX FP16 VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD213SS FMA VFMA VFNMADD213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMADD213SS FMA VFMA VFNMADD213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMADD213SS AVX512EVEX VFMA VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD213SS AVX512EVEX VFMA VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD231PD FMA VFMA VFNMADD231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD231PD FMA VFMA VFNMADD231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD231PD FMA VFMA VFNMADD231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD231PD FMA VFMA VFNMADD231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PD AVX512EVEX VFMA VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMADD231PH AVX512EVEX FP16 VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMADD231PS FMA VFMA VFNMADD231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMADD231PS AVX512EVEX VFMA VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMADD231SD FMA VFMA VFNMADD231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMADD231SD FMA VFMA VFNMADD231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMADD231SD AVX512EVEX VFMA VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD231SD AVX512EVEX VFMA VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD231SH AVX512EVEX FP16 VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMADD231SH AVX512EVEX FP16 VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADD231SS FMA VFMA VFNMADD231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMADD231SS FMA VFMA VFNMADD231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMADD231SS AVX512EVEX VFMA VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMADD231SS AVX512EVEX VFMA VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMADDPD FMA4 FMA4 VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMADDPD FMA4 FMA4 VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMADDPS FMA4 FMA4 VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMADDSD FMA4 FMA4 VFNMADDSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSD FMA4 FMA4 VFNMADDSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSD FMA4 FMA4 VFNMADDSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSS FMA4 FMA4 VFNMADDSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSS FMA4 FMA4 VFNMADDSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMADDSS FMA4 FMA4 VFNMADDSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUB132PD FMA VFMA VFNMSUB132PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB132PD FMA VFMA VFNMSUB132PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB132PD FMA VFMA VFNMSUB132PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB132PD FMA VFMA VFNMSUB132PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PD AVX512EVEX VFMA VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB132PH AVX512EVEX FP16 VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB132PS FMA VFMA VFNMSUB132PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB132PS AVX512EVEX VFMA VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB132SD FMA VFMA VFNMSUB132SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMSUB132SD FMA VFMA VFNMSUB132SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMSUB132SD AVX512EVEX VFMA VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB132SD AVX512EVEX VFMA VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB132SH AVX512EVEX FP16 VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMSUB132SH AVX512EVEX FP16 VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB132SS FMA VFMA VFNMSUB132SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMSUB132SS FMA VFMA VFNMSUB132SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMSUB132SS AVX512EVEX VFMA VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB132SS AVX512EVEX VFMA VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB213PD FMA VFMA VFNMSUB213PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PD AVX512EVEX VFMA VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB213PH AVX512EVEX FP16 VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB213PS FMA VFMA VFNMSUB213PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB213PS AVX512EVEX VFMA VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB213SD FMA VFMA VFNMSUB213SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMSUB213SD FMA VFMA VFNMSUB213SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMSUB213SD AVX512EVEX VFMA VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB213SD AVX512EVEX VFMA VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB213SH AVX512EVEX FP16 VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMSUB213SH AVX512EVEX FP16 VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB213SS FMA VFMA VFNMSUB213SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMSUB213SS FMA VFMA VFNMSUB213SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMSUB213SS AVX512EVEX VFMA VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB213SS AVX512EVEX VFMA VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB231PD FMA VFMA VFNMSUB231PD_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PD AVX512EVEX VFMA VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VFNMSUB231PH AVX512EVEX FP16 VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_XMMdq_XMMdq_MEMdq FMA MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_XMMdq_XMMdq_XMMdq FMA MXCSR +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_YMMqq_YMMqq_MEMqq FMA MXCSR +VFNMSUB231PS FMA VFMA VFNMSUB231PS_YMMqq_YMMqq_YMMqq FMA MXCSR +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFNMSUB231PS AVX512EVEX VFMA VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VFNMSUB231SD FMA VFMA VFNMSUB231SD_XMMdq_XMMq_MEMq FMA MXCSR:SIMD_SCALAR +VFNMSUB231SD FMA VFMA VFNMSUB231SD_XMMdq_XMMq_XMMq FMA MXCSR:SIMD_SCALAR +VFNMSUB231SD AVX512EVEX VFMA VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB231SD AVX512EVEX VFMA VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB231SH AVX512EVEX FP16 VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VFNMSUB231SH AVX512EVEX FP16 VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUB231SS FMA VFMA VFNMSUB231SS_XMMdq_XMMd_MEMd FMA MXCSR:SIMD_SCALAR +VFNMSUB231SS FMA VFMA VFNMSUB231SS_XMMdq_XMMd_XMMd FMA MXCSR:SIMD_SCALAR +VFNMSUB231SS AVX512EVEX VFMA VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFNMSUB231SS AVX512EVEX VFMA VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMSUBPD FMA4 FMA4 VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq FMA4 MXCSR:AMDONLY +VFNMSUBPS FMA4 FMA4 VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq FMA4 MXCSR:AMDONLY +VFNMSUBSD FMA4 FMA4 VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSD FMA4 FMA4 VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSD FMA4 FMA4 VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSS FMA4 FMA4 VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSS FMA4 FMA4 VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFNMSUBSS FMA4 FMA4 VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd FMA4 SIMD_SCALAR:MXCSR:AMDONLY +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VFPCLASSPD AVX512EVEX AVX512 VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX +VFPCLASSPH AVX512EVEX FP16 VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VFPCLASSPS AVX512EVEX AVX512 VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VFPCLASSSD AVX512EVEX AVX512 VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFPCLASSSD AVX512EVEX AVX512 VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFPCLASSSH AVX512EVEX FP16 VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VFPCLASSSH AVX512EVEX FP16 VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VFPCLASSSS AVX512EVEX AVX512 VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VFPCLASSSS AVX512EVEX AVX512 VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VFRCZPD XOP XOP VFRCZPD_XMMdq_MEMdq XOP MXCSR:AMDONLY +VFRCZPD XOP XOP VFRCZPD_XMMdq_XMMdq XOP MXCSR:AMDONLY +VFRCZPD XOP XOP VFRCZPD_YMMqq_MEMqq XOP MXCSR:AMDONLY +VFRCZPD XOP XOP VFRCZPD_YMMqq_YMMqq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_XMMdq_MEMdq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_XMMdq_XMMdq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_YMMqq_MEMqq XOP MXCSR:AMDONLY +VFRCZPS XOP XOP VFRCZPS_YMMqq_YMMqq XOP MXCSR:AMDONLY +VFRCZSD XOP XOP VFRCZSD_XMMdq_MEMq XOP SIMD_SCALAR:MXCSR:AMDONLY +VFRCZSD XOP XOP VFRCZSD_XMMdq_XMMq XOP SIMD_SCALAR:MXCSR:AMDONLY +VFRCZSS XOP XOP VFRCZSS_XMMdq_MEMd XOP SIMD_SCALAR:MXCSR:AMDONLY +VFRCZSS XOP XOP VFRCZSS_XMMdq_XMMd XOP SIMD_SCALAR:MXCSR:AMDONLY +VGATHERDPD AVX512EVEX GATHER VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX2GATHER AVX2GATHER VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX512EVEX GATHER VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX2GATHER AVX2GATHER VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERDPD AVX512EVEX GATHER VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX512EVEX GATHER VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX2GATHER AVX2GATHER VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX512EVEX GATHER VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX2GATHER AVX2GATHER VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERDPS AVX512EVEX GATHER VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERPF0DPD AVX512EVEX GATHER VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF0DPS AVX512EVEX GATHER VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF0QPD AVX512EVEX GATHER VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF0QPS AVX512EVEX GATHER VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1DPD AVX512EVEX GATHER VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1DPS AVX512EVEX GATHER VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1QPD AVX512EVEX GATHER VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERPF1QPS AVX512EVEX GATHER VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:GATHER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VGATHERQPD AVX512EVEX GATHER VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX2GATHER AVX2GATHER VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX512EVEX GATHER VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX2GATHER AVX2GATHER VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VGATHERQPD AVX512EVEX GATHER VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX512EVEX GATHER VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX512EVEX GATHER VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX2GATHER AVX2GATHER VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX2GATHER AVX2GATHER VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VGATHERQPS AVX512EVEX GATHER VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPD AVX512EVEX AVX512 VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETEXPPH AVX512EVEX FP16 VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETEXPPS AVX512EVEX AVX512 VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETEXPSD AVX512EVEX AVX512 VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETEXPSD AVX512EVEX AVX512 VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETEXPSH AVX512EVEX FP16 VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VGETEXPSH AVX512EVEX FP16 VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETEXPSS AVX512EVEX AVX512 VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETEXPSS AVX512EVEX AVX512 VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPD AVX512EVEX AVX512 VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VGETMANTPH AVX512EVEX FP16 VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VGETMANTPS AVX512EVEX AVX512 VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VGETMANTSD AVX512EVEX AVX512 VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETMANTSD AVX512EVEX AVX512 VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETMANTSH AVX512EVEX FP16 VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VGETMANTSH AVX512EVEX FP16 VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGETMANTSS AVX512EVEX AVX512 VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VGETMANTSS AVX512EVEX AVX512 VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB GFNI GFNI VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEINVQB AVX512EVEX GFNI VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 AVX512_GFNI_128 MASKOP_EVEX +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 AVX512_GFNI_256 MASKOP_EVEX +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB GFNI GFNI VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 AVX_GFNI INVALID +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VGF2P8AFFINEQB AVX512EVEX GFNI VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 AVX512_GFNI_512 MASKOP_EVEX +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_GFNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_GFNI_128 MASKOP_EVEX +VGF2P8MULB GFNI GFNI VGF2P8MULB_XMMu8_XMMu8_MEMu8 AVX_GFNI INVALID +VGF2P8MULB GFNI GFNI VGF2P8MULB_XMMu8_XMMu8_XMMu8 AVX_GFNI INVALID +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_GFNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_GFNI_256 MASKOP_EVEX +VGF2P8MULB GFNI GFNI VGF2P8MULB_YMMu8_YMMu8_MEMu8 AVX_GFNI INVALID +VGF2P8MULB GFNI GFNI VGF2P8MULB_YMMu8_YMMu8_YMMu8 AVX_GFNI INVALID +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_GFNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VGF2P8MULB AVX512EVEX GFNI VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_GFNI_512 MASKOP_EVEX +VHADDPD AVX AVX VHADDPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VHADDPD AVX AVX VHADDPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VHADDPD AVX AVX VHADDPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VHADDPD AVX AVX VHADDPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VHADDPS AVX AVX VHADDPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VHADDPS AVX AVX VHADDPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VHADDPS AVX AVX VHADDPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VHADDPS AVX AVX VHADDPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VHSUBPD AVX AVX VHSUBPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VHSUBPS AVX AVX VHSUBPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VINSERTF128 AVX AVX VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb AVX INVALID +VINSERTF128 AVX AVX VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb AVX INVALID +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTF32X4 AVX512EVEX AVX512 VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTF32X8 AVX512EVEX AVX512 VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VINSERTF32X8 AVX512EVEX AVX512 VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTF64X2 AVX512EVEX AVX512 VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTF64X4 AVX512EVEX AVX512 VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTF64X4 AVX512EVEX AVX512 VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTI128 AVX2 AVX2 VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb AVX2 INVALID +VINSERTI128 AVX2 AVX2 VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb AVX2 INVALID +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTI32X4 AVX512EVEX AVX512 VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTI32X8 AVX512EVEX AVX512 VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE8 +VINSERTI32X8 AVX512EVEX AVX512 VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:DISP8_TUPLE2 +VINSERTI64X2 AVX512EVEX AVX512 VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX +VINSERTI64X4 AVX512EVEX AVX512 VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_TUPLE4 +VINSERTI64X4 AVX512EVEX AVX512 VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VINSERTPS AVX AVX VINSERTPS_XMMdq_XMMdq_MEMd_IMMb AVX INVALID +VINSERTPS AVX AVX VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VINSERTPS AVX512EVEX AVX512 VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128N DISP8_TUPLE1 +VINSERTPS AVX512EVEX AVX512 VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128N INVALID +VLDDQU AVX AVX VLDDQU_XMMdq_MEMdq AVX INVALID +VLDDQU AVX AVX VLDDQU_YMMqq_MEMqq AVX INVALID +VLDMXCSR AVX AVX VLDMXCSR_MEMd AVX MXCSR +VMASKMOVDQU AVX AVX VMASKMOVDQU_XMMdq_XMMdq AVX MASKOP:FIXED_BASE0:NOTSX:NONTEMPORAL +VMASKMOVPD AVX AVX VMASKMOVPD_MEMdq_XMMdq_XMMdq AVX MASKOP +VMASKMOVPD AVX AVX VMASKMOVPD_MEMqq_YMMqq_YMMqq AVX MASKOP +VMASKMOVPD AVX AVX VMASKMOVPD_XMMdq_XMMdq_MEMdq AVX MASKOP +VMASKMOVPD AVX AVX VMASKMOVPD_YMMqq_YMMqq_MEMqq AVX MASKOP +VMASKMOVPS AVX AVX VMASKMOVPS_MEMdq_XMMdq_XMMdq AVX MASKOP:NONTEMPORAL +VMASKMOVPS AVX AVX VMASKMOVPS_MEMqq_YMMqq_YMMqq AVX MASKOP:NONTEMPORAL +VMASKMOVPS AVX AVX VMASKMOVPS_XMMdq_XMMdq_MEMdq AVX MASKOP:NONTEMPORAL +VMASKMOVPS AVX AVX VMASKMOVPS_YMMqq_YMMqq_MEMqq AVX MASKOP:NONTEMPORAL +VMAXPD AVX AVX VMAXPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VMAXPD AVX AVX VMAXPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VMAXPD AVX512EVEX AVX512 VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPD AVX512EVEX AVX512 VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMAXPD AVX512EVEX AVX512 VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPD AVX512EVEX AVX512 VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMAXPD AVX AVX VMAXPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VMAXPD AVX AVX VMAXPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VMAXPD AVX512EVEX AVX512 VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPD AVX512EVEX AVX512 VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMAXPH AVX512EVEX FP16 VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VMAXPS AVX AVX VMAXPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VMAXPS AVX AVX VMAXPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VMAXPS AVX512EVEX AVX512 VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPS AVX512EVEX AVX512 VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMAXPS AVX512EVEX AVX512 VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPS AVX512EVEX AVX512 VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMAXPS AVX AVX VMAXPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VMAXPS AVX AVX VMAXPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VMAXPS AVX512EVEX AVX512 VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMAXPS AVX512EVEX AVX512 VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMAXSD AVX AVX VMAXSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VMAXSD AVX AVX VMAXSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VMAXSD AVX512EVEX AVX512 VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMAXSD AVX512EVEX AVX512 VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMAXSH AVX512EVEX FP16 VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VMAXSH AVX512EVEX FP16 VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMAXSS AVX AVX VMAXSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VMAXSS AVX AVX VMAXSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VMAXSS AVX512EVEX AVX512 VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMAXSS AVX512EVEX AVX512 VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMCALL VTX VTX VMCALL VTX NOTSX +VMCLEAR VTX VTX VMCLEAR_MEMq VTX NOTSX +VMFUNC VMFUNC VTX VMFUNC VMFUNC INVALID +VMINPD AVX AVX VMINPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VMINPD AVX AVX VMINPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VMINPD AVX512EVEX AVX512 VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPD AVX512EVEX AVX512 VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMINPD AVX512EVEX AVX512 VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPD AVX512EVEX AVX512 VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMINPD AVX AVX VMINPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VMINPD AVX AVX VMINPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VMINPD AVX512EVEX AVX512 VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPD AVX512EVEX AVX512 VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMINPH AVX512EVEX FP16 VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VMINPS AVX AVX VMINPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VMINPS AVX AVX VMINPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VMINPS AVX512EVEX AVX512 VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPS AVX512EVEX AVX512 VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMINPS AVX512EVEX AVX512 VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPS AVX512EVEX AVX512 VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMINPS AVX AVX VMINPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VMINPS AVX AVX VMINPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VMINPS AVX512EVEX AVX512 VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMINPS AVX512EVEX AVX512 VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMINSD AVX AVX VMINSD_XMMdq_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VMINSD AVX AVX VMINSD_XMMdq_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VMINSD AVX512EVEX AVX512 VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMINSD AVX512EVEX AVX512 VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMINSH AVX512EVEX FP16 VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VMINSH AVX512EVEX FP16 VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMINSS AVX AVX VMINSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VMINSS AVX AVX VMINSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VMINSS AVX512EVEX AVX512 VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMINSS AVX512EVEX AVX512 VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMLAUNCH VTX VTX VMLAUNCH VTX NOTSX +VMLOAD SVM SYSTEM VMLOAD_ArAX SVM PROTECTED_MODE:AMDONLY +VMMCALL SVM SYSTEM VMMCALL SVM AMDONLY +VMOVAPD AVX DATAXFER VMOVAPD_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX DATAXFER VMOVAPD_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_XMMdq_XMMdq_28 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_XMMdq_XMMdq_29 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVAPD AVX DATAXFER VMOVAPD_YMMqq_MEMqq AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_YMMqq_YMMqq_28 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX DATAXFER VMOVAPD_YMMqq_YMMqq_29 AVX REQUIRES_ALIGNMENT +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPD AVX512EVEX DATAXFER VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVAPS AVX DATAXFER VMOVAPS_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX DATAXFER VMOVAPS_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_XMMdq_XMMdq_28 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_XMMdq_XMMdq_29 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVAPS AVX DATAXFER VMOVAPS_YMMqq_MEMqq AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_YMMqq_YMMqq_28 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX DATAXFER VMOVAPS_YMMqq_YMMqq_29 AVX REQUIRES_ALIGNMENT +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVAPS AVX512EVEX DATAXFER VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDDUP AVX DATAXFER VMOVDDUP_XMMdq_MEMq AVX INVALID +VMOVDDUP AVX DATAXFER VMOVDDUP_XMMdq_XMMq AVX INVALID +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MOVDDUP +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MOVDDUP +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDDUP AVX DATAXFER VMOVDDUP_YMMqq_MEMqq AVX INVALID +VMOVDDUP AVX DATAXFER VMOVDDUP_YMMqq_YMMqq AVX INVALID +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MOVDDUP +VMOVDDUP AVX512EVEX DATAXFER VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA32 AVX512EVEX DATAXFER VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:REQUIRES_ALIGNMENT:DISP8_FULLMEM +VMOVDQA64 AVX512EVEX DATAXFER VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQA AVX DATAXFER VMOVDQA_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_XMMdq_XMMdq_6F AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_XMMdq_XMMdq_7F AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_YMMqq_MEMqq AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_YMMqq_YMMqq_6F AVX REQUIRES_ALIGNMENT +VMOVDQA AVX DATAXFER VMOVDQA_YMMqq_YMMqq_7F AVX REQUIRES_ALIGNMENT +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU16 AVX512EVEX DATAXFER VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU32 AVX512EVEX DATAXFER VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU64 AVX512EVEX DATAXFER VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVDQU8 AVX512EVEX DATAXFER VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VMOVDQU AVX DATAXFER VMOVDQU_MEMdq_XMMdq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_MEMqq_YMMqq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_XMMdq_MEMdq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_XMMdq_XMMdq_6F AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_XMMdq_XMMdq_7F AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_YMMqq_MEMqq AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_YMMqq_YMMqq_6F AVX INVALID +VMOVDQU AVX DATAXFER VMOVDQU_YMMqq_YMMqq_7F AVX INVALID +VMOVD AVX DATAXFER VMOVD_GPR32d_XMMd AVX INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_GPR32u32_XMMu32_AVX512 AVX512F_128N INVALID +VMOVD AVX DATAXFER VMOVD_MEMd_XMMd AVX INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_MEMu32_XMMu32_AVX512 AVX512F_128N DISP8_GPR_WRITER_STORE +VMOVD AVX DATAXFER VMOVD_XMMdq_GPR32d AVX INVALID +VMOVD AVX DATAXFER VMOVD_XMMdq_MEMd AVX INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_XMMu32_GPR32u32_AVX512 AVX512F_128N INVALID +VMOVD AVX512EVEX DATAXFER VMOVD_XMMu32_MEMu32_AVX512 AVX512F_128N DISP8_GPR_READER +VMOVHLPS AVX DATAXFER VMOVHLPS_XMMdq_XMMdq_XMMdq AVX INVALID +VMOVHLPS AVX512EVEX DATAXFER VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 AVX512F_128N INVALID +VMOVHPD AVX512EVEX DATAXFER VMOVHPD_MEMf64_XMMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVHPD AVX DATAXFER VMOVHPD_MEMq_XMMdq AVX INVALID +VMOVHPD AVX DATAXFER VMOVHPD_XMMdq_XMMq_MEMq AVX INVALID +VMOVHPD AVX512EVEX DATAXFER VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVHPS AVX512EVEX DATAXFER VMOVHPS_MEMf32_XMMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVHPS AVX DATAXFER VMOVHPS_MEMq_XMMdq AVX INVALID +VMOVHPS AVX DATAXFER VMOVHPS_XMMdq_XMMq_MEMq AVX INVALID +VMOVHPS AVX512EVEX DATAXFER VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVLHPS AVX DATAXFER VMOVLHPS_XMMdq_XMMq_XMMq AVX INVALID +VMOVLHPS AVX512EVEX DATAXFER VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 AVX512F_128N INVALID +VMOVLPD AVX512EVEX DATAXFER VMOVLPD_MEMf64_XMMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVLPD AVX DATAXFER VMOVLPD_MEMq_XMMq AVX INVALID +VMOVLPD AVX DATAXFER VMOVLPD_XMMdq_XMMdq_MEMq AVX INVALID +VMOVLPD AVX512EVEX DATAXFER VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVLPS AVX512EVEX DATAXFER VMOVLPS_MEMf32_XMMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVLPS AVX DATAXFER VMOVLPS_MEMq_XMMq AVX INVALID +VMOVLPS AVX DATAXFER VMOVLPS_XMMdq_XMMdq_MEMq AVX INVALID +VMOVLPS AVX512EVEX DATAXFER VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 AVX512F_128N DISP8_TUPLE2 +VMOVMSKPD AVX DATAXFER VMOVMSKPD_GPR32d_XMMdq AVX INVALID +VMOVMSKPD AVX DATAXFER VMOVMSKPD_GPR32d_YMMqq AVX INVALID +VMOVMSKPS AVX DATAXFER VMOVMSKPS_GPR32d_XMMdq AVX INVALID +VMOVMSKPS AVX DATAXFER VMOVMSKPS_GPR32d_YMMqq AVX INVALID +VMOVNTDQA AVX DATAXFER VMOVNTDQA_XMMdq_MEMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQA AVX512EVEX DATAXFER VMOVNTDQA_XMMu32_MEMu32_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQA AVX2 DATAXFER VMOVNTDQA_YMMqq_MEMqq AVX2 REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQA AVX512EVEX DATAXFER VMOVNTDQA_YMMu32_MEMu32_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQA AVX512EVEX DATAXFER VMOVNTDQA_ZMMu32_MEMu32_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQ AVX DATAXFER VMOVNTDQ_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQ AVX DATAXFER VMOVNTDQ_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTDQ AVX512EVEX DATAXFER VMOVNTDQ_MEMu32_XMMu32_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQ AVX512EVEX DATAXFER VMOVNTDQ_MEMu32_YMMu32_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTDQ AVX512EVEX DATAXFER VMOVNTDQ_MEMu32_ZMMu32_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX DATAXFER VMOVNTPD_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTPD AVX512EVEX DATAXFER VMOVNTPD_MEMf64_XMMf64_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX512EVEX DATAXFER VMOVNTPD_MEMf64_YMMf64_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX512EVEX DATAXFER VMOVNTPD_MEMf64_ZMMf64_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPD AVX DATAXFER VMOVNTPD_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTPS AVX DATAXFER VMOVNTPS_MEMdq_XMMdq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVNTPS AVX512EVEX DATAXFER VMOVNTPS_MEMf32_XMMf32_AVX512 AVX512F_128 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPS AVX512EVEX DATAXFER VMOVNTPS_MEMf32_YMMf32_AVX512 AVX512F_256 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPS AVX512EVEX DATAXFER VMOVNTPS_MEMf32_ZMMf32_AVX512 AVX512F_512 NOTSX:REQUIRES_ALIGNMENT:DISP8_FULLMEM:NONTEMPORAL +VMOVNTPS AVX DATAXFER VMOVNTPS_MEMqq_YMMqq AVX REQUIRES_ALIGNMENT:NOTSX:NONTEMPORAL +VMOVQ AVX DATAXFER VMOVQ_GPR64q_XMMq AVX INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_GPR64u64_XMMu64_AVX512 AVX512F_128N INVALID +VMOVQ AVX DATAXFER VMOVQ_MEMq_XMMq_7E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_MEMq_XMMq_D6 AVX INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_MEMu64_XMMu64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVQ AVX DATAXFER VMOVQ_XMMdq_GPR64q AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_MEMq_6E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_MEMq_7E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_XMMq_7E AVX INVALID +VMOVQ AVX DATAXFER VMOVQ_XMMdq_XMMq_D6 AVX INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_XMMu64_GPR64u64_AVX512 AVX512F_128N INVALID +VMOVQ AVX512EVEX DATAXFER VMOVQ_XMMu64_MEMu64_AVX512 AVX512F_128N DISP8_SCALAR +VMOVQ AVX512EVEX DATAXFER VMOVQ_XMMu64_XMMu64_AVX512 AVX512F_128N INVALID +VMOVSD AVX512EVEX DATAXFER VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSD AVX DATAXFER VMOVSD_MEMq_XMMq AVX SIMD_SCALAR +VMOVSD AVX DATAXFER VMOVSD_XMMdq_MEMq AVX SIMD_SCALAR +VMOVSD AVX DATAXFER VMOVSD_XMMdq_XMMdq_XMMq_10 AVX SIMD_SCALAR +VMOVSD AVX DATAXFER VMOVSD_XMMdq_XMMdq_XMMq_11 AVX SIMD_SCALAR +VMOVSD AVX512EVEX DATAXFER VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSD AVX512EVEX DATAXFER VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:SIMD_SCALAR +VMOVSHDUP AVX DATAXFER VMOVSHDUP_XMMdq_MEMdq AVX INVALID +VMOVSHDUP AVX DATAXFER VMOVSHDUP_XMMdq_XMMdq AVX INVALID +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULLMEM +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULLMEM +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVSHDUP AVX DATAXFER VMOVSHDUP_YMMqq_MEMqq AVX INVALID +VMOVSHDUP AVX DATAXFER VMOVSHDUP_YMMqq_YMMqq AVX INVALID +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULLMEM +VMOVSHDUP AVX512EVEX DATAXFER VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVSH AVX512EVEX DATAXFER VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VMOVSH AVX512EVEX DATAXFER VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VMOVSH AVX512EVEX DATAXFER VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VMOVSLDUP AVX DATAXFER VMOVSLDUP_XMMdq_MEMdq AVX INVALID +VMOVSLDUP AVX DATAXFER VMOVSLDUP_XMMdq_XMMdq AVX INVALID +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULLMEM +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULLMEM +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVSLDUP AVX DATAXFER VMOVSLDUP_YMMqq_MEMqq AVX INVALID +VMOVSLDUP AVX DATAXFER VMOVSLDUP_YMMqq_YMMqq AVX INVALID +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULLMEM +VMOVSLDUP AVX512EVEX DATAXFER VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVSS AVX DATAXFER VMOVSS_MEMd_XMMd AVX SIMD_SCALAR +VMOVSS AVX512EVEX DATAXFER VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSS AVX DATAXFER VMOVSS_XMMdq_MEMd AVX SIMD_SCALAR +VMOVSS AVX DATAXFER VMOVSS_XMMdq_XMMdq_XMMd_10 AVX SIMD_SCALAR +VMOVSS AVX DATAXFER VMOVSS_XMMdq_XMMdq_XMMd_11 AVX SIMD_SCALAR +VMOVSS AVX512EVEX DATAXFER VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SIMD_SCALAR:DISP8_SCALAR +VMOVSS AVX512EVEX DATAXFER VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:SIMD_SCALAR +VMOVUPD AVX DATAXFER VMOVUPD_MEMdq_XMMdq AVX INVALID +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX DATAXFER VMOVUPD_MEMqq_YMMqq AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_XMMdq_MEMdq AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_XMMdq_XMMdq_10 AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_XMMdq_XMMdq_11 AVX INVALID +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VMOVUPD AVX DATAXFER VMOVUPD_YMMqq_MEMqq AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_YMMqq_YMMqq_10 AVX INVALID +VMOVUPD AVX DATAXFER VMOVUPD_YMMqq_YMMqq_11 AVX INVALID +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPD AVX512EVEX DATAXFER VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VMOVUPS AVX DATAXFER VMOVUPS_MEMdq_XMMdq AVX INVALID +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX DATAXFER VMOVUPS_MEMqq_YMMqq AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_XMMdq_MEMdq AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_XMMdq_XMMdq_10 AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_XMMdq_XMMdq_11 AVX INVALID +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VMOVUPS AVX DATAXFER VMOVUPS_YMMqq_MEMqq AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_YMMqq_YMMqq_10 AVX INVALID +VMOVUPS AVX DATAXFER VMOVUPS_YMMqq_YMMqq_11 AVX INVALID +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VMOVUPS AVX512EVEX DATAXFER VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VMOVW AVX512EVEX DATAXFER VMOVW_GPR32f16_XMMf16_AVX512 AVX512_FP16_128N INVALID +VMOVW AVX512EVEX DATAXFER VMOVW_MEMf16_XMMf16_AVX512 AVX512_FP16_128N DISP8_GPR_WRITER_STORE +VMOVW AVX512EVEX DATAXFER VMOVW_XMMf16_GPR32f16_AVX512 AVX512_FP16_128N INVALID +VMOVW AVX512EVEX DATAXFER VMOVW_XMMf16_MEMf16_AVX512 AVX512_FP16_128N DISP8_GPR_READER +VMPSADBW AVX AVX VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VMPSADBW AVX AVX VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VMPSADBW AVX2 AVX2 VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VMPSADBW AVX2 AVX2 VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VMPTRLD VTX VTX VMPTRLD_MEMq VTX NOTSX +VMPTRST VTX VTX VMPTRST_MEMq VTX NOTSX +VMREAD VTX VTX VMREAD_GPR32_GPR32 VTX INVALID +VMREAD VTX VTX VMREAD_GPR64_GPR64 VTX INVALID +VMREAD VTX VTX VMREAD_MEMd_GPR32 VTX INVALID +VMREAD VTX VTX VMREAD_MEMq_GPR64 VTX INVALID +VMRESUME VTX VTX VMRESUME VTX NOTSX +VMRUN SVM SYSTEM VMRUN_ArAX SVM PROTECTED_MODE:AMDONLY +VMSAVE SVM SYSTEM VMSAVE SVM PROTECTED_MODE:AMDONLY +VMULPD AVX AVX VMULPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VMULPD AVX AVX VMULPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VMULPD AVX512EVEX AVX512 VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPD AVX512EVEX AVX512 VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMULPD AVX512EVEX AVX512 VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPD AVX512EVEX AVX512 VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMULPD AVX AVX VMULPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VMULPD AVX AVX VMULPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VMULPD AVX512EVEX AVX512 VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPD AVX512EVEX AVX512 VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VMULPH AVX512EVEX FP16 VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VMULPS AVX AVX VMULPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VMULPS AVX AVX VMULPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VMULPS AVX512EVEX AVX512 VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPS AVX512EVEX AVX512 VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VMULPS AVX512EVEX AVX512 VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPS AVX512EVEX AVX512 VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VMULPS AVX AVX VMULPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VMULPS AVX AVX VMULPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VMULPS AVX512EVEX AVX512 VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VMULPS AVX512EVEX AVX512 VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VMULSD AVX AVX VMULSD_XMMdq_XMMdq_MEMq AVX MXCSR:SIMD_SCALAR +VMULSD AVX AVX VMULSD_XMMdq_XMMdq_XMMq AVX MXCSR:SIMD_SCALAR +VMULSD AVX512EVEX AVX512 VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMULSD AVX512EVEX AVX512 VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMULSH AVX512EVEX FP16 VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VMULSH AVX512EVEX FP16 VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMULSS AVX AVX VMULSS_XMMdq_XMMdq_MEMd AVX MXCSR:SIMD_SCALAR +VMULSS AVX AVX VMULSS_XMMdq_XMMdq_XMMd AVX MXCSR:SIMD_SCALAR +VMULSS AVX512EVEX AVX512 VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VMULSS AVX512EVEX AVX512 VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VMWRITE VTX VTX VMWRITE_GPR32_GPR32 VTX INVALID +VMWRITE VTX VTX VMWRITE_GPR32_MEMd VTX INVALID +VMWRITE VTX VTX VMWRITE_GPR64_GPR64 VTX INVALID +VMWRITE VTX VTX VMWRITE_GPR64_MEMq VTX INVALID +VMXOFF VTX VTX VMXOFF VTX NOTSX +VMXON VTX VTX VMXON_MEMq VTX PROTECTED_MODE:NOTSX +VORPD AVX LOGICAL_FP VORPD_XMMdq_XMMdq_MEMdq AVX INVALID +VORPD AVX LOGICAL_FP VORPD_XMMdq_XMMdq_XMMdq AVX INVALID +VORPD AVX512EVEX LOGICAL_FP VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPD AVX512EVEX LOGICAL_FP VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VORPD AVX LOGICAL_FP VORPD_YMMqq_YMMqq_MEMqq AVX INVALID +VORPD AVX LOGICAL_FP VORPD_YMMqq_YMMqq_YMMqq AVX INVALID +VORPD AVX512EVEX LOGICAL_FP VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPD AVX512EVEX LOGICAL_FP VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VORPD AVX512EVEX LOGICAL_FP VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPD AVX512EVEX LOGICAL_FP VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VORPS AVX LOGICAL_FP VORPS_XMMdq_XMMdq_MEMdq AVX INVALID +VORPS AVX LOGICAL_FP VORPS_XMMdq_XMMdq_XMMdq AVX INVALID +VORPS AVX512EVEX LOGICAL_FP VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPS AVX512EVEX LOGICAL_FP VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VORPS AVX LOGICAL_FP VORPS_YMMqq_YMMqq_MEMqq AVX INVALID +VORPS AVX LOGICAL_FP VORPS_YMMqq_YMMqq_YMMqq AVX INVALID +VORPS AVX512EVEX LOGICAL_FP VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPS AVX512EVEX LOGICAL_FP VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VORPS AVX512EVEX LOGICAL_FP VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VORPS AVX512EVEX LOGICAL_FP VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_VP2INTERSECT_128 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_VP2INTERSECT_128 MULTIDEST2 +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_VP2INTERSECT_256 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_VP2INTERSECT_256 MULTIDEST2 +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_VP2INTERSECT_512 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTD AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_VP2INTERSECT_512 MULTIDEST2 +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_VP2INTERSECT_128 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_VP2INTERSECT_128 MULTIDEST2 +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_VP2INTERSECT_256 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_VP2INTERSECT_256 MULTIDEST2 +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_VP2INTERSECT_512 DISP8_FULL:MULTIDEST2:BROADCAST_ENABLED +VP2INTERSECTQ AVX512EVEX AVX512_VP2INTERSECT VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_VP2INTERSECT_512 MULTIDEST2 +VP4DPWSSDS AVX512EVEX AVX512_4VNNIW VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_4VNNIW_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MASKOP_EVEX +VP4DPWSSD AVX512EVEX AVX512_4VNNIW VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_4VNNIW_512 MEMORY_FAULT_SUPPRESSION:MULTISOURCE4:DISP8_TUPLE1_4X:MASKOP_EVEX +VPABSB AVX AVX VPABSB_XMMdq_MEMdq AVX INVALID +VPABSB AVX AVX VPABSB_XMMdq_XMMdq AVX INVALID +VPABSB AVX512EVEX AVX512 VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSB AVX512EVEX AVX512 VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPABSB AVX512EVEX AVX512 VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSB AVX512EVEX AVX512 VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPABSB AVX2 AVX2 VPABSB_YMMqq_MEMqq AVX2 INVALID +VPABSB AVX2 AVX2 VPABSB_YMMqq_YMMqq AVX2 INVALID +VPABSB AVX512EVEX AVX512 VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSB AVX512EVEX AVX512 VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPABSD AVX AVX VPABSD_XMMdq_MEMdq AVX INVALID +VPABSD AVX AVX VPABSD_XMMdq_XMMdq AVX INVALID +VPABSD AVX512EVEX AVX512 VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSD AVX512EVEX AVX512 VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPABSD AVX512EVEX AVX512 VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSD AVX512EVEX AVX512 VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPABSD AVX2 AVX2 VPABSD_YMMqq_MEMqq AVX2 INVALID +VPABSD AVX2 AVX2 VPABSD_YMMqq_YMMqq AVX2 INVALID +VPABSD AVX512EVEX AVX512 VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSD AVX512EVEX AVX512 VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPABSQ AVX512EVEX AVX512 VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSQ AVX512EVEX AVX512 VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPABSQ AVX512EVEX AVX512 VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSQ AVX512EVEX AVX512 VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPABSQ AVX512EVEX AVX512 VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPABSQ AVX512EVEX AVX512 VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPABSW AVX AVX VPABSW_XMMdq_MEMdq AVX INVALID +VPABSW AVX AVX VPABSW_XMMdq_XMMdq AVX INVALID +VPABSW AVX512EVEX AVX512 VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSW AVX512EVEX AVX512 VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPABSW AVX512EVEX AVX512 VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSW AVX512EVEX AVX512 VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPABSW AVX2 AVX2 VPABSW_YMMqq_MEMqq AVX2 INVALID +VPABSW AVX2 AVX2 VPABSW_YMMqq_YMMqq AVX2 INVALID +VPABSW AVX512EVEX AVX512 VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPABSW AVX512EVEX AVX512 VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKSSDW AVX AVX VPACKSSDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKSSDW AVX AVX VPACKSSDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKSSDW AVX2 AVX2 VPACKSSDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKSSDW AVX2 AVX2 VPACKSSDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKSSDW AVX512EVEX AVX512 VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKSSWB AVX AVX VPACKSSWB_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKSSWB AVX AVX VPACKSSWB_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKSSWB AVX2 AVX2 VPACKSSWB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKSSWB AVX2 AVX2 VPACKSSWB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPACKSSWB AVX512EVEX AVX512 VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKUSDW AVX AVX VPACKUSDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKUSDW AVX AVX VPACKUSDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKUSDW AVX2 AVX2 VPACKUSDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKUSDW AVX2 AVX2 VPACKUSDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPACKUSDW AVX512EVEX AVX512 VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512BW_512 MASKOP_EVEX +VPACKUSWB AVX AVX VPACKUSWB_XMMdq_XMMdq_MEMdq AVX INVALID +VPACKUSWB AVX AVX VPACKUSWB_XMMdq_XMMdq_XMMdq AVX INVALID +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPACKUSWB AVX2 AVX2 VPACKUSWB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPACKUSWB AVX2 AVX2 VPACKUSWB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPACKUSWB AVX512EVEX AVX512 VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDB AVX AVX VPADDB_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDB AVX AVX VPADDB_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDB AVX512EVEX AVX512 VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDB AVX512EVEX AVX512 VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDB AVX2 AVX2 VPADDB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDB AVX2 AVX2 VPADDB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDB AVX512EVEX AVX512 VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDB AVX512EVEX AVX512 VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDB AVX512EVEX AVX512 VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDB AVX512EVEX AVX512 VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDD AVX AVX VPADDD_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDD AVX AVX VPADDD_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDD AVX512EVEX AVX512 VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDD AVX512EVEX AVX512 VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPADDD AVX2 AVX2 VPADDD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDD AVX2 AVX2 VPADDD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDD AVX512EVEX AVX512 VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDD AVX512EVEX AVX512 VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPADDD AVX512EVEX AVX512 VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDD AVX512EVEX AVX512 VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPADDQ AVX AVX VPADDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDQ AVX AVX VPADDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDQ AVX512EVEX AVX512 VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDQ AVX512EVEX AVX512 VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPADDQ AVX2 AVX2 VPADDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDQ AVX2 AVX2 VPADDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDQ AVX512EVEX AVX512 VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDQ AVX512EVEX AVX512 VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPADDQ AVX512EVEX AVX512 VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPADDQ AVX512EVEX AVX512 VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPADDSB AVX AVX VPADDSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDSB AVX AVX VPADDSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDSB AVX512EVEX AVX512 VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSB AVX512EVEX AVX512 VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDSB AVX512EVEX AVX512 VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSB AVX512EVEX AVX512 VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDSB AVX2 AVX2 VPADDSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDSB AVX2 AVX2 VPADDSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDSB AVX512EVEX AVX512 VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSB AVX512EVEX AVX512 VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDSW AVX AVX VPADDSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDSW AVX AVX VPADDSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDSW AVX512EVEX AVX512 VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSW AVX512EVEX AVX512 VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDSW AVX512EVEX AVX512 VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSW AVX512EVEX AVX512 VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDSW AVX2 AVX2 VPADDSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDSW AVX2 AVX2 VPADDSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDSW AVX512EVEX AVX512 VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDSW AVX512EVEX AVX512 VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDUSB AVX AVX VPADDUSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDUSB AVX AVX VPADDUSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDUSB AVX512EVEX AVX512 VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSB AVX512EVEX AVX512 VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDUSB AVX2 AVX2 VPADDUSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDUSB AVX2 AVX2 VPADDUSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDUSB AVX512EVEX AVX512 VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSB AVX512EVEX AVX512 VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDUSB AVX512EVEX AVX512 VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSB AVX512EVEX AVX512 VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDUSW AVX AVX VPADDUSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDUSW AVX AVX VPADDUSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDUSW AVX512EVEX AVX512 VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSW AVX512EVEX AVX512 VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDUSW AVX2 AVX2 VPADDUSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDUSW AVX2 AVX2 VPADDUSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDUSW AVX512EVEX AVX512 VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSW AVX512EVEX AVX512 VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDUSW AVX512EVEX AVX512 VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDUSW AVX512EVEX AVX512 VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPADDW AVX AVX VPADDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPADDW AVX AVX VPADDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPADDW AVX512EVEX AVX512 VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDW AVX512EVEX AVX512 VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPADDW AVX2 AVX2 VPADDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPADDW AVX2 AVX2 VPADDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPADDW AVX512EVEX AVX512 VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDW AVX512EVEX AVX512 VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPADDW AVX512EVEX AVX512 VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPADDW AVX512EVEX AVX512 VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPALIGNR AVX AVX VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VPALIGNR AVX AVX VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VPALIGNR AVX512EVEX AVX512 VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPALIGNR AVX512EVEX AVX512 VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPALIGNR AVX2 AVX2 VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPALIGNR AVX2 AVX2 VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPALIGNR AVX512EVEX AVX512 VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPALIGNR AVX512EVEX AVX512 VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPALIGNR AVX512EVEX AVX512 VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPALIGNR AVX512EVEX AVX512 VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPANDD AVX512EVEX LOGICAL VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDD AVX512EVEX LOGICAL VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPANDD AVX512EVEX LOGICAL VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDD AVX512EVEX LOGICAL VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPANDD AVX512EVEX LOGICAL VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDD AVX512EVEX LOGICAL VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPANDND AVX512EVEX LOGICAL VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDND AVX512EVEX LOGICAL VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPANDND AVX512EVEX LOGICAL VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDND AVX512EVEX LOGICAL VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPANDND AVX512EVEX LOGICAL VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDND AVX512EVEX LOGICAL VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDNQ AVX512EVEX LOGICAL VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPANDN AVX LOGICAL VPANDN_XMMdq_XMMdq_MEMdq AVX INVALID +VPANDN AVX LOGICAL VPANDN_XMMdq_XMMdq_XMMdq AVX INVALID +VPANDN AVX2 LOGICAL VPANDN_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPANDN AVX2 LOGICAL VPANDN_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPANDQ AVX512EVEX LOGICAL VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDQ AVX512EVEX LOGICAL VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPANDQ AVX512EVEX LOGICAL VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDQ AVX512EVEX LOGICAL VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPANDQ AVX512EVEX LOGICAL VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPANDQ AVX512EVEX LOGICAL VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPAND AVX LOGICAL VPAND_XMMdq_XMMdq_MEMdq AVX INVALID +VPAND AVX LOGICAL VPAND_XMMdq_XMMdq_XMMdq AVX INVALID +VPAND AVX2 LOGICAL VPAND_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPAND AVX2 LOGICAL VPAND_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPAVGB AVX AVX VPAVGB_XMMdq_XMMdq_MEMdq AVX INVALID +VPAVGB AVX AVX VPAVGB_XMMdq_XMMdq_XMMdq AVX INVALID +VPAVGB AVX512EVEX AVX512 VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGB AVX512EVEX AVX512 VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPAVGB AVX2 AVX2 VPAVGB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPAVGB AVX2 AVX2 VPAVGB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPAVGB AVX512EVEX AVX512 VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGB AVX512EVEX AVX512 VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPAVGB AVX512EVEX AVX512 VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGB AVX512EVEX AVX512 VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPAVGW AVX AVX VPAVGW_XMMdq_XMMdq_MEMdq AVX INVALID +VPAVGW AVX AVX VPAVGW_XMMdq_XMMdq_XMMdq AVX INVALID +VPAVGW AVX512EVEX AVX512 VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGW AVX512EVEX AVX512 VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPAVGW AVX2 AVX2 VPAVGW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPAVGW AVX2 AVX2 VPAVGW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPAVGW AVX512EVEX AVX512 VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGW AVX512EVEX AVX512 VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPAVGW AVX512EVEX AVX512 VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPAVGW AVX512EVEX AVX512 VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPBLENDD AVX2 AVX2 VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb AVX2 INVALID +VPBLENDD AVX2 AVX2 VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb AVX2 INVALID +VPBLENDD AVX2 AVX2 VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPBLENDD AVX2 AVX2 VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMB AVX512EVEX BLEND VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMD AVX512EVEX BLEND VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED:MASK_AS_CONTROL +VPBLENDMQ AVX512EVEX BLEND VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM:MASK_AS_CONTROL +VPBLENDMW AVX512EVEX BLEND VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX:MASK_AS_CONTROL +VPBLENDVB AVX AVX VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq AVX INVALID +VPBLENDVB AVX AVX VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq AVX INVALID +VPBLENDVB AVX2 AVX2 VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq AVX2 INVALID +VPBLENDVB AVX2 AVX2 VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPBLENDW AVX AVX VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VPBLENDW AVX AVX VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VPBLENDW AVX2 AVX2 VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPBLENDW AVX2 AVX2 VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_XMMdq_MEMb AVX2 INVALID +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_XMMdq_XMMb AVX2 INVALID +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_BYTE +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_YMMqq_MEMb AVX2 INVALID +VPBROADCASTB AVX2 BROADCAST VPBROADCASTB_YMMqq_XMMb AVX2 INVALID +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_BYTE +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 AVX512BW_512 MASKOP_EVEX +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_BYTE +VPBROADCASTB AVX512EVEX BROADCAST VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_XMMdq_MEMd AVX2 INVALID +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_XMMdq_XMMd AVX2 INVALID +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_YMMqq_MEMd AVX2 INVALID +VPBROADCASTD AVX2 BROADCAST VPBROADCASTD_YMMqq_XMMd AVX2 INVALID +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTD AVX512EVEX BROADCAST VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTMB2Q AVX512EVEX BROADCAST VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 AVX512CD_128 INVALID +VPBROADCASTMB2Q AVX512EVEX BROADCAST VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 AVX512CD_256 INVALID +VPBROADCASTMB2Q AVX512EVEX BROADCAST VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD AVX512CD_512 INVALID +VPBROADCASTMW2D AVX512EVEX BROADCAST VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 AVX512CD_128 INVALID +VPBROADCASTMW2D AVX512EVEX BROADCAST VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 AVX512CD_256 INVALID +VPBROADCASTMW2D AVX512EVEX BROADCAST VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD AVX512CD_512 INVALID +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_XMMdq_MEMq AVX2 INVALID +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_XMMdq_XMMq AVX2 INVALID +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_YMMqq_MEMq AVX2 INVALID +VPBROADCASTQ AVX2 BROADCAST VPBROADCASTQ_YMMqq_XMMq AVX2 INVALID +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1 +VPBROADCASTQ AVX512EVEX BROADCAST VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_XMMdq_MEMw AVX2 INVALID +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_XMMdq_XMMw AVX2 INVALID +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_WORD +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_YMMqq_MEMw AVX2 INVALID +VPBROADCASTW AVX2 BROADCAST VPBROADCASTW_YMMqq_XMMw AVX2 INVALID +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_WORD +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 AVX512BW_512 MASKOP_EVEX +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_TUPLE1_WORD +VPBROADCASTW AVX512EVEX BROADCAST VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPCLMULQDQ AVX AVX VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VPCLMULQDQ AVX AVX VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_128 DISP8_FULLMEM +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_128 INVALID +VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 VPCLMULQDQ INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_256 DISP8_FULLMEM +VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 VPCLMULQDQ INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_256 INVALID +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_512 DISP8_FULLMEM +VPCLMULQDQ AVX512EVEX VPCLMULQDQ VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 AVX512_VPCLMULQDQ_512 INVALID +VPCMOV XOP XOP VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq XOP AMDONLY +VPCMOV XOP XOP VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq XOP AMDONLY +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPB AVX512EVEX AVX512 VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPD AVX512EVEX AVX512 VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQB AVX512EVEX AVX512 VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPEQB AVX AVX VPCMPEQB_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQB AVX AVX VPCMPEQB_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQB AVX2 AVX2 VPCMPEQB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQB AVX2 AVX2 VPCMPEQB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQD AVX512EVEX AVX512 VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPEQD AVX AVX VPCMPEQD_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQD AVX AVX VPCMPEQD_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQD AVX2 AVX2 VPCMPEQD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQD AVX2 AVX2 VPCMPEQD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPEQQ AVX512EVEX AVX512 VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPEQQ AVX AVX VPCMPEQQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQQ AVX AVX VPCMPEQQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQQ AVX2 AVX2 VPCMPEQQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQQ AVX2 AVX2 VPCMPEQQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPEQW AVX512EVEX AVX512 VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPEQW AVX AVX VPCMPEQW_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPEQW AVX AVX VPCMPEQW_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPEQW AVX2 AVX2 VPCMPEQW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPEQW AVX2 AVX2 VPCMPEQW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPESTRI64 AVX STTNI VPCMPESTRI64_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRI64 AVX STTNI VPCMPESTRI64_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPESTRI AVX STTNI VPCMPESTRI_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRI AVX STTNI VPCMPESTRI_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPESTRM64 AVX STTNI VPCMPESTRM64_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRM64 AVX STTNI VPCMPESTRM64_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPESTRM AVX STTNI VPCMPESTRM_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPESTRM AVX STTNI VPCMPESTRM_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTB AVX512EVEX AVX512 VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPGTB AVX AVX VPCMPGTB_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTB AVX AVX VPCMPGTB_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTB AVX2 AVX2 VPCMPGTB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTB AVX2 AVX2 VPCMPGTB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTD AVX512EVEX AVX512 VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPGTD AVX AVX VPCMPGTD_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTD AVX AVX VPCMPGTD_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTD AVX2 AVX2 VPCMPGTD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTD AVX2 AVX2 VPCMPGTD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPGTQ AVX512EVEX AVX512 VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPGTQ AVX AVX VPCMPGTQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTQ AVX AVX VPCMPGTQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTQ AVX2 AVX2 VPCMPGTQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTQ AVX2 AVX2 VPCMPGTQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPGTW AVX512EVEX AVX512 VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPGTW AVX AVX VPCMPGTW_XMMdq_XMMdq_MEMdq AVX INVALID +VPCMPGTW AVX AVX VPCMPGTW_XMMdq_XMMdq_XMMdq AVX INVALID +VPCMPGTW AVX2 AVX2 VPCMPGTW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPCMPGTW AVX2 AVX2 VPCMPGTW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPCMPISTRI64 AVX STTNI VPCMPISTRI64_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPISTRI64 AVX STTNI VPCMPISTRI64_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPISTRI AVX STTNI VPCMPISTRI_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPISTRI AVX STTNI VPCMPISTRI_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPISTRM AVX STTNI VPCMPISTRM_XMMdq_MEMdq_IMMb AVX INVALID +VPCMPISTRM AVX STTNI VPCMPISTRM_XMMdq_XMMdq_IMMb AVX INVALID +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPQ AVX512EVEX AVX512 VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUB AVX512EVEX AVX512 VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUD AVX512EVEX AVX512 VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCMPUQ AVX512EVEX AVX512 VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPUW AVX512EVEX AVX512 VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPCMPW AVX512EVEX AVX512 VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPCOMB XOP XOP VPCOMB_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMB XOP XOP VPCOMB_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMD XOP XOP VPCOMD_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMD XOP XOP VPCOMD_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPCOMPRESSB AVX512EVEX COMPRESS VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPCOMPRESSD AVX512EVEX COMPRESS VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPCOMPRESSQ AVX512EVEX COMPRESS VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPCOMPRESSW AVX512EVEX COMPRESS VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPCOMQ XOP XOP VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMQ XOP XOP VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUB XOP XOP VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUB XOP XOP VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUD XOP XOP VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUD XOP XOP VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUQ XOP XOP VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUQ XOP XOP VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMUW XOP XOP VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMUW XOP XOP VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCOMW XOP XOP VPCOMW_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPCOMW XOP XOP VPCOMW_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512CD_128 MASKOP_EVEX +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512CD_256 MASKOP_EVEX +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD AVX512CD_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTD AVX512EVEX CONFLICT VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD AVX512CD_512 MASKOP_EVEX +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512CD_128 MASKOP_EVEX +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512CD_256 MASKOP_EVEX +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD AVX512CD_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPCONFLICTQ AVX512EVEX CONFLICT VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD AVX512CD_512 MASKOP_EVEX +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSDS AVX_VNNI VEX VPDPBUSDS_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSDS AVX512EVEX AVX512 VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPBUSD AVX_VNNI VEX VPDPBUSD_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSD AVX_VNNI VEX VPDPBUSD_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPBUSD AVX_VNNI VEX VPDPBUSD_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPBUSD AVX_VNNI VEX VPDPBUSD_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPBUSD AVX512EVEX AVX512 VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSDS AVX_VNNI VEX VPDPWSSDS_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSDS AVX512EVEX AVX512 VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 AVX512_VNNI_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 AVX512_VNNI_128 MASKOP_EVEX +VPDPWSSD AVX_VNNI VEX VPDPWSSD_XMMi32_XMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSD AVX_VNNI VEX VPDPWSSD_XMMi32_XMMu32_XMMu32 AVX_VNNI INVALID +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 AVX512_VNNI_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 AVX512_VNNI_256 MASKOP_EVEX +VPDPWSSD AVX_VNNI VEX VPDPWSSD_YMMi32_YMMu32_MEMu32 AVX_VNNI INVALID +VPDPWSSD AVX_VNNI VEX VPDPWSSD_YMMi32_YMMu32_YMMu32 AVX_VNNI INVALID +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 AVX512_VNNI_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPDPWSSD AVX512EVEX AVX512 VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 AVX512_VNNI_512 MASKOP_EVEX +VPERM2F128 AVX AVX VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VPERM2F128 AVX AVX VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VPERM2I128 AVX2 AVX2 VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb AVX2 INVALID +VPERM2I128 AVX2 AVX2 VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb AVX2 INVALID +VPERMB AVX512EVEX AVX512_VBMI VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMB AVX512EVEX AVX512_VBMI VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPERMB AVX512EVEX AVX512_VBMI VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMB AVX512EVEX AVX512_VBMI VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPERMB AVX512EVEX AVX512_VBMI VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMB AVX512EVEX AVX512_VBMI VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPERMD AVX2 AVX2 VPERMD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPERMD AVX2 AVX2 VPERMD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPERMD AVX512EVEX AVX512 VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMD AVX512EVEX AVX512 VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMD AVX512EVEX AVX512 VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMD AVX512EVEX AVX512 VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2B AVX512EVEX AVX512_VBMI VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPERMI2D AVX512EVEX AVX512 VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2D AVX512EVEX AVX512 VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2D AVX512EVEX AVX512 VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2D AVX512EVEX AVX512 VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2D AVX512EVEX AVX512 VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2D AVX512EVEX AVX512 VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PD AVX512EVEX AVX512 VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2PS AVX512EVEX AVX512 VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMI2Q AVX512EVEX AVX512 VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMI2W AVX512EVEX AVX512 VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2W AVX512EVEX AVX512 VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPERMI2W AVX512EVEX AVX512 VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2W AVX512EVEX AVX512 VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPERMI2W AVX512EVEX AVX512 VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMI2W AVX512EVEX AVX512 VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPERMIL2PD XOP XOP VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb XOP AMDONLY +VPERMIL2PD XOP XOP VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb XOP AMDONLY +VPERMIL2PS XOP XOP VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb XOP AMDONLY +VPERMILPD AVX AVX VPERMILPD_XMMdq_MEMdq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_XMMdq_XMMdq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_XMMdq_XMMdq_MEMdq AVX INVALID +VPERMILPD AVX AVX VPERMILPD_XMMdq_XMMdq_XMMdq AVX INVALID +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPD AVX AVX VPERMILPD_YMMqq_MEMqq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_YMMqq_YMMqq_IMMb AVX INVALID +VPERMILPD AVX AVX VPERMILPD_YMMqq_YMMqq_MEMqq AVX INVALID +VPERMILPD AVX AVX VPERMILPD_YMMqq_YMMqq_YMMqq AVX INVALID +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPD AVX512EVEX AVX512 VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMILPS AVX AVX VPERMILPS_XMMdq_MEMdq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_XMMdq_XMMdq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_XMMdq_XMMdq_MEMdq AVX INVALID +VPERMILPS AVX AVX VPERMILPS_XMMdq_XMMdq_XMMdq AVX INVALID +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMILPS AVX AVX VPERMILPS_YMMqq_MEMqq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_YMMqq_YMMqq_IMMb AVX INVALID +VPERMILPS AVX AVX VPERMILPS_YMMqq_YMMqq_MEMqq AVX INVALID +VPERMILPS AVX AVX VPERMILPS_YMMqq_YMMqq_YMMqq AVX INVALID +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMILPS AVX512EVEX AVX512 VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMPD AVX2 AVX2 VPERMPD_YMMqq_MEMqq_IMMb AVX2 INVALID +VPERMPD AVX2 AVX2 VPERMPD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPD AVX512EVEX AVX512 VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMPS AVX512EVEX AVX512 VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPS AVX512EVEX AVX512 VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMPS AVX2 AVX2 VPERMPS_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPERMPS AVX2 AVX2 VPERMPS_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPERMPS AVX512EVEX AVX512 VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMPS AVX512EVEX AVX512 VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMQ AVX2 AVX2 VPERMQ_YMMqq_MEMqq_IMMb AVX2 INVALID +VPERMQ AVX2 AVX2 VPERMQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMQ AVX512EVEX AVX512 VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2B AVX512EVEX AVX512_VBMI VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPERMT2D AVX512EVEX AVX512 VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2D AVX512EVEX AVX512 VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2D AVX512EVEX AVX512 VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2D AVX512EVEX AVX512 VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2D AVX512EVEX AVX512 VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2D AVX512EVEX AVX512 VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PD AVX512EVEX AVX512 VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2PS AVX512EVEX AVX512 VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPERMT2Q AVX512EVEX AVX512 VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPERMT2W AVX512EVEX AVX512 VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2W AVX512EVEX AVX512 VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPERMT2W AVX512EVEX AVX512 VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2W AVX512EVEX AVX512 VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPERMT2W AVX512EVEX AVX512 VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMT2W AVX512EVEX AVX512 VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPERMW AVX512EVEX AVX512 VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPERMW AVX512EVEX AVX512 VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPERMW AVX512EVEX AVX512 VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPERMW AVX512EVEX AVX512 VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPERMW AVX512EVEX AVX512 VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPERMW AVX512EVEX AVX512 VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDB AVX512EVEX EXPAND VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDD AVX512EVEX EXPAND VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDQ AVX512EVEX EXPAND VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_GSCAT:MASK_VARIABLE_MEMOP +VPEXPANDW AVX512EVEX EXPAND VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPEXTRB AVX AVX VPEXTRB_GPR32d_XMMdq_IMMb AVX INVALID +VPEXTRB AVX512EVEX AVX512 VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 AVX512BW_128N INVALID +VPEXTRB AVX AVX VPEXTRB_MEMb_XMMdq_IMMb AVX INVALID +VPEXTRB AVX512EVEX AVX512 VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 AVX512BW_128N DISP8_GPR_WRITER_STORE_BYTE +VPEXTRD AVX AVX VPEXTRD_GPR32d_XMMdq_IMMb AVX INVALID +VPEXTRD AVX512EVEX AVX512 VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 AVX512DQ_128N INVALID +VPEXTRD AVX AVX VPEXTRD_MEMd_XMMdq_IMMb AVX INVALID +VPEXTRD AVX512EVEX AVX512 VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_WRITER_STORE +VPEXTRQ AVX AVX VPEXTRQ_GPR64q_XMMdq_IMMb AVX INVALID +VPEXTRQ AVX512EVEX AVX512 VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 AVX512DQ_128N INVALID +VPEXTRQ AVX AVX VPEXTRQ_MEMq_XMMdq_IMMb AVX INVALID +VPEXTRQ AVX512EVEX AVX512 VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_WRITER_STORE +VPEXTRW AVX AVX VPEXTRW_GPR32d_XMMdq_IMMb_15 AVX INVALID +VPEXTRW AVX AVX VPEXTRW_GPR32d_XMMdq_IMMb_C5 AVX INVALID +VPEXTRW AVX512EVEX AVX512 VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 AVX512BW_128N INVALID +VPEXTRW_C5 AVX512EVEX AVX512 VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 AVX512BW_128N INVALID +VPEXTRW AVX512EVEX AVX512 VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 AVX512BW_128N DISP8_GPR_WRITER_STORE_WORD +VPEXTRW AVX AVX VPEXTRW_MEMw_XMMdq_IMMb AVX INVALID +VPGATHERDD AVX512EVEX GATHER VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX2GATHER AVX2GATHER VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX512EVEX GATHER VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX2GATHER AVX2GATHER VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERDD AVX512EVEX GATHER VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX512EVEX GATHER VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 AVX512F_128 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX2GATHER AVX2GATHER VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX512EVEX GATHER VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 AVX512F_256 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX2GATHER AVX2GATHER VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 AVX2GATHER GATHER:DWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERDQ AVX512EVEX GATHER VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 AVX512F_512 DWORD_INDICES:GATHER:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX512EVEX GATHER VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX512EVEX GATHER VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX2GATHER AVX2GATHER VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX2GATHER AVX2GATHER VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_D:SPECIAL_AGEN_REQUIRED +VPGATHERQD AVX512EVEX GATHER VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX512EVEX GATHER VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 AVX512F_128 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX2GATHER AVX2GATHER VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX512EVEX GATHER VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 AVX512F_256 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX2GATHER AVX2GATHER VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 AVX2GATHER GATHER:QWORD_INDICES:ELEMENT_SIZE_Q:SPECIAL_AGEN_REQUIRED +VPGATHERQQ AVX512EVEX GATHER VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 AVX512F_512 GATHER:QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED +VPHADDBD XOP XOP VPHADDBD_XMMdq_MEMdq XOP AMDONLY +VPHADDBD XOP XOP VPHADDBD_XMMdq_XMMdq XOP AMDONLY +VPHADDBQ XOP XOP VPHADDBQ_XMMdq_MEMdq XOP AMDONLY +VPHADDBQ XOP XOP VPHADDBQ_XMMdq_XMMdq XOP AMDONLY +VPHADDBW XOP XOP VPHADDBW_XMMdq_MEMdq XOP AMDONLY +VPHADDBW XOP XOP VPHADDBW_XMMdq_XMMdq XOP AMDONLY +VPHADDDQ XOP XOP VPHADDDQ_XMMdq_MEMdq XOP AMDONLY +VPHADDDQ XOP XOP VPHADDDQ_XMMdq_XMMdq XOP AMDONLY +VPHADDD AVX AVX VPHADDD_XMMdq_XMMdq_MEMdq AVX INVALID +VPHADDD AVX AVX VPHADDD_XMMdq_XMMdq_XMMdq AVX INVALID +VPHADDD AVX2 AVX2 VPHADDD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHADDD AVX2 AVX2 VPHADDD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHADDSW AVX AVX VPHADDSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHADDSW AVX AVX VPHADDSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHADDSW AVX2 AVX2 VPHADDSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHADDSW AVX2 AVX2 VPHADDSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHADDUBD XOP XOP VPHADDUBD_XMMdq_MEMdq XOP AMDONLY +VPHADDUBD XOP XOP VPHADDUBD_XMMdq_XMMdq XOP AMDONLY +VPHADDUBQ XOP XOP VPHADDUBQ_XMMdq_MEMdq XOP AMDONLY +VPHADDUBQ XOP XOP VPHADDUBQ_XMMdq_XMMdq XOP AMDONLY +VPHADDUBW XOP XOP VPHADDUBW_XMMdq_MEMdq XOP AMDONLY +VPHADDUBW XOP XOP VPHADDUBW_XMMdq_XMMdq XOP AMDONLY +VPHADDUDQ XOP XOP VPHADDUDQ_XMMdq_MEMdq XOP AMDONLY +VPHADDUDQ XOP XOP VPHADDUDQ_XMMdq_XMMdq XOP AMDONLY +VPHADDUWD XOP XOP VPHADDUWD_XMMdq_MEMdq XOP AMDONLY +VPHADDUWD XOP XOP VPHADDUWD_XMMdq_XMMdq XOP AMDONLY +VPHADDUWQ XOP XOP VPHADDUWQ_XMMdq_MEMdq XOP AMDONLY +VPHADDUWQ XOP XOP VPHADDUWQ_XMMdq_XMMdq XOP AMDONLY +VPHADDWD XOP XOP VPHADDWD_XMMdq_MEMdq XOP AMDONLY +VPHADDWD XOP XOP VPHADDWD_XMMdq_XMMdq XOP AMDONLY +VPHADDWQ XOP XOP VPHADDWQ_XMMdq_MEMdq XOP AMDONLY +VPHADDWQ XOP XOP VPHADDWQ_XMMdq_XMMdq XOP AMDONLY +VPHADDW AVX AVX VPHADDW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHADDW AVX AVX VPHADDW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHADDW AVX2 AVX2 VPHADDW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHADDW AVX2 AVX2 VPHADDW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHMINPOSUW AVX AVX VPHMINPOSUW_XMMdq_MEMdq AVX INVALID +VPHMINPOSUW AVX AVX VPHMINPOSUW_XMMdq_XMMdq AVX INVALID +VPHSUBBW XOP XOP VPHSUBBW_XMMdq_MEMdq XOP AMDONLY +VPHSUBBW XOP XOP VPHSUBBW_XMMdq_XMMdq XOP AMDONLY +VPHSUBDQ XOP XOP VPHSUBDQ_XMMdq_MEMdq XOP AMDONLY +VPHSUBDQ XOP XOP VPHSUBDQ_XMMdq_XMMdq XOP AMDONLY +VPHSUBD AVX AVX VPHSUBD_XMMdq_XMMdq_MEMdq AVX INVALID +VPHSUBD AVX AVX VPHSUBD_XMMdq_XMMdq_XMMdq AVX INVALID +VPHSUBD AVX2 AVX2 VPHSUBD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHSUBD AVX2 AVX2 VPHSUBD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHSUBSW AVX AVX VPHSUBSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHSUBSW AVX AVX VPHSUBSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHSUBSW AVX2 AVX2 VPHSUBSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHSUBSW AVX2 AVX2 VPHSUBSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPHSUBWD XOP XOP VPHSUBWD_XMMdq_MEMdq XOP AMDONLY +VPHSUBWD XOP XOP VPHSUBWD_XMMdq_XMMdq XOP AMDONLY +VPHSUBW AVX AVX VPHSUBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPHSUBW AVX AVX VPHSUBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPHSUBW AVX2 AVX2 VPHSUBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPHSUBW AVX2 AVX2 VPHSUBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPINSRB AVX AVX VPINSRB_XMMdq_XMMdq_GPR32d_IMMb AVX INVALID +VPINSRB AVX AVX VPINSRB_XMMdq_XMMdq_MEMb_IMMb AVX INVALID +VPINSRB AVX512EVEX AVX512 VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 AVX512BW_128N INVALID +VPINSRB AVX512EVEX AVX512 VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128N DISP8_GPR_READER_BYTE +VPINSRD AVX AVX VPINSRD_XMMdq_XMMdq_GPR32d_IMMb AVX INVALID +VPINSRD AVX AVX VPINSRD_XMMdq_XMMdq_MEMd_IMMb AVX INVALID +VPINSRD AVX512EVEX AVX512 VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 AVX512DQ_128N INVALID +VPINSRD AVX512EVEX AVX512 VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_READER +VPINSRQ AVX AVX VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb AVX INVALID +VPINSRQ AVX AVX VPINSRQ_XMMdq_XMMdq_MEMq_IMMb AVX INVALID +VPINSRQ AVX512EVEX AVX512 VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 AVX512DQ_128N INVALID +VPINSRQ AVX512EVEX AVX512 VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 AVX512DQ_128N DISP8_GPR_READER +VPINSRW AVX AVX VPINSRW_XMMdq_XMMdq_GPR32d_IMMb AVX INVALID +VPINSRW AVX AVX VPINSRW_XMMdq_XMMdq_MEMw_IMMb AVX INVALID +VPINSRW AVX512EVEX AVX512 VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 AVX512BW_128N INVALID +VPINSRW AVX512EVEX AVX512 VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 AVX512BW_128N DISP8_GPR_READER_WORD +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512CD_128 MASKOP_EVEX +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512CD_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512CD_256 MASKOP_EVEX +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD AVX512CD_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTD AVX512EVEX CONFLICT VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD AVX512CD_512 MASKOP_EVEX +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512CD_128 MASKOP_EVEX +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512CD_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512CD_256 MASKOP_EVEX +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD AVX512CD_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPLZCNTQ AVX512EVEX CONFLICT VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD AVX512CD_512 MASKOP_EVEX +VPMACSDD XOP XOP VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSDD XOP XOP VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSDQH XOP XOP VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSDQH XOP XOP VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSDQL XOP XOP VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSDQL XOP XOP VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSDD XOP XOP VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSDD XOP XOP VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSDQH XOP XOP VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSDQH XOP XOP VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSDQL XOP XOP VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSDQL XOP XOP VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSWD XOP XOP VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSWD XOP XOP VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSSWW XOP XOP VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSSWW XOP XOP VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSWD XOP XOP VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSWD XOP XOP VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMACSWW XOP XOP VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMACSWW XOP XOP VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMADCSSWD XOP XOP VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMADCSSWD XOP XOP VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMADCSWD XOP XOP VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPMADCSWD XOP XOP VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_IFMA_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_IFMA_128 MASKOP_EVEX +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_IFMA_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_IFMA_256 MASKOP_EVEX +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_IFMA_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52HUQ AVX512EVEX IFMA VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_IFMA_512 MASKOP_EVEX +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_IFMA_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_IFMA_128 MASKOP_EVEX +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_IFMA_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_IFMA_256 MASKOP_EVEX +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_IFMA_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMADD52LUQ AVX512EVEX IFMA VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_IFMA_512 MASKOP_EVEX +VPMADDUBSW AVX AVX VPMADDUBSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMADDUBSW AVX AVX VPMADDUBSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMADDUBSW AVX2 AVX2 VPMADDUBSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMADDUBSW AVX2 AVX2 VPMADDUBSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPMADDUBSW AVX512EVEX AVX512 VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMADDWD AVX AVX VPMADDWD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMADDWD AVX AVX VPMADDWD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMADDWD AVX512EVEX AVX512 VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPMADDWD AVX512EVEX AVX512 VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMADDWD AVX512EVEX AVX512 VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPMADDWD AVX512EVEX AVX512 VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMADDWD AVX2 AVX2 VPMADDWD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMADDWD AVX2 AVX2 VPMADDWD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMADDWD AVX512EVEX AVX512 VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPMADDWD AVX512EVEX AVX512 VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_MEMdq_XMMdq_XMMdq AVX2 MASKOP +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_MEMqq_YMMqq_YMMqq AVX2 MASKOP +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_XMMdq_XMMdq_MEMdq AVX2 MASKOP +VPMASKMOVD AVX2 AVX2 VPMASKMOVD_YMMqq_YMMqq_MEMqq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_MEMdq_XMMdq_XMMdq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_MEMqq_YMMqq_YMMqq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_XMMdq_XMMdq_MEMdq AVX2 MASKOP +VPMASKMOVQ AVX2 AVX2 VPMASKMOVQ_YMMqq_YMMqq_MEMqq AVX2 MASKOP +VPMAXSB AVX AVX VPMAXSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXSB AVX AVX VPMAXSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXSB AVX512EVEX AVX512 VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSB AVX512EVEX AVX512 VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXSB AVX512EVEX AVX512 VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSB AVX512EVEX AVX512 VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXSB AVX2 AVX2 VPMAXSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXSB AVX2 AVX2 VPMAXSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXSB AVX512EVEX AVX512 VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSB AVX512EVEX AVX512 VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMAXSD AVX AVX VPMAXSD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXSD AVX AVX VPMAXSD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXSD AVX512EVEX AVX512 VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSD AVX512EVEX AVX512 VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXSD AVX512EVEX AVX512 VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSD AVX512EVEX AVX512 VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXSD AVX2 AVX2 VPMAXSD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXSD AVX2 AVX2 VPMAXSD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXSD AVX512EVEX AVX512 VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSD AVX512EVEX AVX512 VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXSQ AVX512EVEX AVX512 VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXSW AVX AVX VPMAXSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXSW AVX AVX VPMAXSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXSW AVX512EVEX AVX512 VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSW AVX512EVEX AVX512 VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXSW AVX512EVEX AVX512 VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSW AVX512EVEX AVX512 VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXSW AVX2 AVX2 VPMAXSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXSW AVX2 AVX2 VPMAXSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXSW AVX512EVEX AVX512 VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXSW AVX512EVEX AVX512 VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMAXUB AVX AVX VPMAXUB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXUB AVX AVX VPMAXUB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXUB AVX512EVEX AVX512 VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUB AVX512EVEX AVX512 VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXUB AVX2 AVX2 VPMAXUB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXUB AVX2 AVX2 VPMAXUB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXUB AVX512EVEX AVX512 VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUB AVX512EVEX AVX512 VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXUB AVX512EVEX AVX512 VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUB AVX512EVEX AVX512 VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMAXUD AVX AVX VPMAXUD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXUD AVX AVX VPMAXUD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXUD AVX512EVEX AVX512 VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUD AVX512EVEX AVX512 VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXUD AVX2 AVX2 VPMAXUD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXUD AVX2 AVX2 VPMAXUD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXUD AVX512EVEX AVX512 VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUD AVX512EVEX AVX512 VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXUD AVX512EVEX AVX512 VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUD AVX512EVEX AVX512 VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMAXUQ AVX512EVEX AVX512 VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMAXUW AVX AVX VPMAXUW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMAXUW AVX AVX VPMAXUW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMAXUW AVX512EVEX AVX512 VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUW AVX512EVEX AVX512 VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMAXUW AVX2 AVX2 VPMAXUW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMAXUW AVX2 AVX2 VPMAXUW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMAXUW AVX512EVEX AVX512 VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUW AVX512EVEX AVX512 VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMAXUW AVX512EVEX AVX512 VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMAXUW AVX512EVEX AVX512 VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINSB AVX AVX VPMINSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINSB AVX AVX VPMINSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINSB AVX512EVEX AVX512 VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSB AVX512EVEX AVX512 VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINSB AVX512EVEX AVX512 VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSB AVX512EVEX AVX512 VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINSB AVX2 AVX2 VPMINSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINSB AVX2 AVX2 VPMINSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINSB AVX512EVEX AVX512 VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSB AVX512EVEX AVX512 VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINSD AVX AVX VPMINSD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINSD AVX AVX VPMINSD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINSD AVX512EVEX AVX512 VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSD AVX512EVEX AVX512 VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMINSD AVX512EVEX AVX512 VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSD AVX512EVEX AVX512 VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMINSD AVX2 AVX2 VPMINSD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINSD AVX2 AVX2 VPMINSD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINSD AVX512EVEX AVX512 VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSD AVX512EVEX AVX512 VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMINSQ AVX512EVEX AVX512 VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSQ AVX512EVEX AVX512 VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMINSQ AVX512EVEX AVX512 VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSQ AVX512EVEX AVX512 VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMINSQ AVX512EVEX AVX512 VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINSQ AVX512EVEX AVX512 VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMINSW AVX AVX VPMINSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINSW AVX AVX VPMINSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINSW AVX512EVEX AVX512 VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSW AVX512EVEX AVX512 VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINSW AVX512EVEX AVX512 VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSW AVX512EVEX AVX512 VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINSW AVX2 AVX2 VPMINSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINSW AVX2 AVX2 VPMINSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINSW AVX512EVEX AVX512 VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINSW AVX512EVEX AVX512 VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINUB AVX AVX VPMINUB_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINUB AVX AVX VPMINUB_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINUB AVX512EVEX AVX512 VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUB AVX512EVEX AVX512 VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINUB AVX2 AVX2 VPMINUB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINUB AVX2 AVX2 VPMINUB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINUB AVX512EVEX AVX512 VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUB AVX512EVEX AVX512 VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINUB AVX512EVEX AVX512 VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUB AVX512EVEX AVX512 VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMINUD AVX AVX VPMINUD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINUD AVX AVX VPMINUD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINUD AVX512EVEX AVX512 VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUD AVX512EVEX AVX512 VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMINUD AVX2 AVX2 VPMINUD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINUD AVX2 AVX2 VPMINUD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINUD AVX512EVEX AVX512 VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUD AVX512EVEX AVX512 VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMINUD AVX512EVEX AVX512 VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUD AVX512EVEX AVX512 VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMINUQ AVX512EVEX AVX512 VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUQ AVX512EVEX AVX512 VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMINUQ AVX512EVEX AVX512 VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUQ AVX512EVEX AVX512 VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMINUQ AVX512EVEX AVX512 VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMINUQ AVX512EVEX AVX512 VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMINUW AVX AVX VPMINUW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMINUW AVX AVX VPMINUW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMINUW AVX512EVEX AVX512 VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUW AVX512EVEX AVX512 VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMINUW AVX2 AVX2 VPMINUW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMINUW AVX2 AVX2 VPMINUW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMINUW AVX512EVEX AVX512 VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUW AVX512EVEX AVX512 VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMINUW AVX512EVEX AVX512 VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMINUW AVX512EVEX AVX512 VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVB2M AVX512EVEX DATAXFER VPMOVB2M_MASKmskw_XMMu8_AVX512 AVX512BW_128 INVALID +VPMOVB2M AVX512EVEX DATAXFER VPMOVB2M_MASKmskw_YMMu8_AVX512 AVX512BW_256 INVALID +VPMOVB2M AVX512EVEX DATAXFER VPMOVB2M_MASKmskw_ZMMu8_AVX512 AVX512BW_512 INVALID +VPMOVD2M AVX512EVEX DATAXFER VPMOVD2M_MASKmskw_XMMu32_AVX512 AVX512DQ_128 INVALID +VPMOVD2M AVX512EVEX DATAXFER VPMOVD2M_MASKmskw_YMMu32_AVX512 AVX512DQ_256 INVALID +VPMOVD2M AVX512EVEX DATAXFER VPMOVD2M_MASKmskw_ZMMu32_AVX512 AVX512DQ_512 INVALID +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVDB AVX512EVEX DATAXFER VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVDW AVX512EVEX DATAXFER VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVM2B AVX512EVEX DATAXFER VPMOVM2B_XMMu8_MASKmskw_AVX512 AVX512BW_128 INVALID +VPMOVM2B AVX512EVEX DATAXFER VPMOVM2B_YMMu8_MASKmskw_AVX512 AVX512BW_256 INVALID +VPMOVM2B AVX512EVEX DATAXFER VPMOVM2B_ZMMu8_MASKmskw_AVX512 AVX512BW_512 INVALID +VPMOVM2D AVX512EVEX DATAXFER VPMOVM2D_XMMu32_MASKmskw_AVX512 AVX512DQ_128 INVALID +VPMOVM2D AVX512EVEX DATAXFER VPMOVM2D_YMMu32_MASKmskw_AVX512 AVX512DQ_256 INVALID +VPMOVM2D AVX512EVEX DATAXFER VPMOVM2D_ZMMu32_MASKmskw_AVX512 AVX512DQ_512 INVALID +VPMOVM2Q AVX512EVEX DATAXFER VPMOVM2Q_XMMu64_MASKmskw_AVX512 AVX512DQ_128 INVALID +VPMOVM2Q AVX512EVEX DATAXFER VPMOVM2Q_YMMu64_MASKmskw_AVX512 AVX512DQ_256 INVALID +VPMOVM2Q AVX512EVEX DATAXFER VPMOVM2Q_ZMMu64_MASKmskw_AVX512 AVX512DQ_512 INVALID +VPMOVM2W AVX512EVEX DATAXFER VPMOVM2W_XMMu16_MASKmskw_AVX512 AVX512BW_128 INVALID +VPMOVM2W AVX512EVEX DATAXFER VPMOVM2W_YMMu16_MASKmskw_AVX512 AVX512BW_256 INVALID +VPMOVM2W AVX512EVEX DATAXFER VPMOVM2W_ZMMu16_MASKmskw_AVX512 AVX512BW_512 INVALID +VPMOVMSKB AVX AVX VPMOVMSKB_GPR32d_XMMdq AVX INVALID +VPMOVMSKB AVX2 AVX2 VPMOVMSKB_GPR32d_YMMqq AVX2 INVALID +VPMOVQ2M AVX512EVEX DATAXFER VPMOVQ2M_MASKmskw_XMMu64_AVX512 AVX512DQ_128 INVALID +VPMOVQ2M AVX512EVEX DATAXFER VPMOVQ2M_MASKmskw_YMMu64_AVX512 AVX512DQ_256 INVALID +VPMOVQ2M AVX512EVEX DATAXFER VPMOVQ2M_MASKmskw_ZMMu64_AVX512 AVX512DQ_512 INVALID +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVQB AVX512EVEX DATAXFER VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVQD AVX512EVEX DATAXFER VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVQW AVX512EVEX DATAXFER VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSDB AVX512EVEX DATAXFER VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSDW AVX512EVEX DATAXFER VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSQB AVX512EVEX DATAXFER VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSQD AVX512EVEX DATAXFER VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSQW AVX512EVEX DATAXFER VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVSWB AVX512EVEX DATAXFER VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVSXBD AVX AVX VPMOVSXBD_XMMdq_MEMd AVX INVALID +VPMOVSXBD AVX AVX VPMOVSXBD_XMMdq_XMMd AVX INVALID +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXBD AVX2 AVX2 VPMOVSXBD_YMMqq_MEMq AVX2 INVALID +VPMOVSXBD AVX2 AVX2 VPMOVSXBD_YMMqq_XMMq AVX2 INVALID +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXBD AVX512EVEX DATAXFER VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXBQ AVX AVX VPMOVSXBQ_XMMdq_MEMw AVX INVALID +VPMOVSXBQ AVX AVX VPMOVSXBQ_XMMdq_XMMw AVX INVALID +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXBQ AVX2 AVX2 VPMOVSXBQ_YMMqq_MEMd AVX2 INVALID +VPMOVSXBQ AVX2 AVX2 VPMOVSXBQ_YMMqq_XMMd AVX2 INVALID +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVSXBQ AVX512EVEX DATAXFER VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXBW AVX AVX VPMOVSXBW_XMMdq_MEMq AVX INVALID +VPMOVSXBW AVX AVX VPMOVSXBW_XMMdq_XMMq AVX INVALID +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVSXBW AVX2 AVX2 VPMOVSXBW_YMMqq_MEMdq AVX2 INVALID +VPMOVSXBW AVX2 AVX2 VPMOVSXBW_YMMqq_XMMdq AVX2 INVALID +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXBW AVX512EVEX DATAXFER VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVSXDQ AVX AVX VPMOVSXDQ_XMMdq_MEMq AVX INVALID +VPMOVSXDQ AVX AVX VPMOVSXDQ_XMMdq_XMMq AVX INVALID +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXDQ AVX2 AVX2 VPMOVSXDQ_YMMqq_MEMdq AVX2 INVALID +VPMOVSXDQ AVX2 AVX2 VPMOVSXDQ_YMMqq_XMMdq AVX2 INVALID +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXDQ AVX512EVEX DATAXFER VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXWD AVX AVX VPMOVSXWD_XMMdq_MEMq AVX INVALID +VPMOVSXWD AVX AVX VPMOVSXWD_XMMdq_XMMq AVX INVALID +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXWD AVX2 AVX2 VPMOVSXWD_YMMqq_MEMdq AVX2 INVALID +VPMOVSXWD AVX2 AVX2 VPMOVSXWD_YMMqq_XMMdq AVX2 INVALID +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVSXWD AVX512EVEX DATAXFER VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVSXWQ AVX AVX VPMOVSXWQ_XMMdq_MEMd AVX INVALID +VPMOVSXWQ AVX AVX VPMOVSXWQ_XMMdq_XMMd AVX INVALID +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVSXWQ AVX2 AVX2 VPMOVSXWQ_YMMqq_MEMq AVX2 INVALID +VPMOVSXWQ AVX2 AVX2 VPMOVSXWQ_YMMqq_XMMq AVX2 INVALID +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVSXWQ AVX512EVEX DATAXFER VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSDB AVX512EVEX DATAXFER VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSDW AVX512EVEX DATAXFER VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSQB AVX512EVEX DATAXFER VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSQD AVX512EVEX DATAXFER VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVUSQW AVX512EVEX DATAXFER VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVUSWB AVX512EVEX DATAXFER VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVW2M AVX512EVEX DATAXFER VPMOVW2M_MASKmskw_XMMu16_AVX512 AVX512BW_128 INVALID +VPMOVW2M AVX512EVEX DATAXFER VPMOVW2M_MASKmskw_YMMu16_AVX512 AVX512BW_256 INVALID +VPMOVW2M AVX512EVEX DATAXFER VPMOVW2M_MASKmskw_ZMMu16_AVX512 AVX512BW_512 INVALID +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVWB AVX512EVEX DATAXFER VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVZXBD AVX AVX VPMOVZXBD_XMMdq_MEMd AVX INVALID +VPMOVZXBD AVX AVX VPMOVZXBD_XMMdq_XMMd AVX INVALID +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXBD AVX2 AVX2 VPMOVZXBD_YMMqq_MEMq AVX2 INVALID +VPMOVZXBD AVX2 AVX2 VPMOVZXBD_YMMqq_XMMq AVX2 INVALID +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXBD AVX512EVEX DATAXFER VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXBQ AVX AVX VPMOVZXBQ_XMMdq_MEMw AVX INVALID +VPMOVZXBQ AVX AVX VPMOVZXBQ_XMMdq_XMMw AVX INVALID +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXBQ AVX2 AVX2 VPMOVZXBQ_YMMqq_MEMd AVX2 INVALID +VPMOVZXBQ AVX2 AVX2 VPMOVZXBQ_YMMqq_XMMd AVX2 INVALID +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_EIGHTHMEM +VPMOVZXBQ AVX512EVEX DATAXFER VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXBW AVX AVX VPMOVZXBW_XMMdq_MEMq AVX INVALID +VPMOVZXBW AVX AVX VPMOVZXBW_XMMdq_XMMq AVX INVALID +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPMOVZXBW AVX2 AVX2 VPMOVZXBW_YMMqq_MEMdq AVX2 INVALID +VPMOVZXBW AVX2 AVX2 VPMOVZXBW_YMMqq_XMMdq AVX2 INVALID +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXBW AVX512EVEX DATAXFER VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPMOVZXDQ AVX AVX VPMOVZXDQ_XMMdq_MEMq AVX INVALID +VPMOVZXDQ AVX AVX VPMOVZXDQ_XMMdq_XMMq AVX INVALID +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXDQ AVX2 AVX2 VPMOVZXDQ_YMMqq_MEMdq AVX2 INVALID +VPMOVZXDQ AVX2 AVX2 VPMOVZXDQ_YMMqq_XMMdq AVX2 INVALID +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXDQ AVX512EVEX DATAXFER VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXWD AVX AVX VPMOVZXWD_XMMdq_MEMq AVX INVALID +VPMOVZXWD AVX AVX VPMOVZXWD_XMMdq_XMMq AVX INVALID +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXWD AVX2 AVX2 VPMOVZXWD_YMMqq_MEMdq AVX2 INVALID +VPMOVZXWD AVX2 AVX2 VPMOVZXWD_YMMqq_XMMdq AVX2 INVALID +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_HALFMEM +VPMOVZXWD AVX512EVEX DATAXFER VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMOVZXWQ AVX AVX VPMOVZXWQ_XMMdq_MEMd AVX INVALID +VPMOVZXWQ AVX AVX VPMOVZXWQ_XMMdq_XMMd AVX INVALID +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 AVX512F_128 MASKOP_EVEX +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 AVX512F_256 MASKOP_EVEX +VPMOVZXWQ AVX2 AVX2 VPMOVZXWQ_YMMqq_MEMq AVX2 INVALID +VPMOVZXWQ AVX2 AVX2 VPMOVZXWQ_YMMqq_XMMq AVX2 INVALID +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_QUARTERMEM +VPMOVZXWQ AVX512EVEX DATAXFER VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 AVX512F_512 MASKOP_EVEX +VPMULDQ AVX AVX VPMULDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULDQ AVX AVX VPMULDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULDQ AVX512EVEX AVX512 VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 AVX512F_128 MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 AVX512F_256 MASKOP_EVEX +VPMULDQ AVX2 AVX2 VPMULDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULDQ AVX2 AVX2 VPMULDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULDQ AVX512EVEX AVX512 VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULDQ AVX512EVEX AVX512 VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 AVX512F_512 MASKOP_EVEX +VPMULHRSW AVX AVX VPMULHRSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULHRSW AVX AVX VPMULHRSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULHRSW AVX2 AVX2 VPMULHRSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULHRSW AVX2 AVX2 VPMULHRSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHRSW AVX512EVEX AVX512 VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULHUW AVX AVX VPMULHUW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULHUW AVX AVX VPMULHUW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULHUW AVX512EVEX AVX512 VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHUW AVX512EVEX AVX512 VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULHUW AVX2 AVX2 VPMULHUW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULHUW AVX2 AVX2 VPMULHUW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULHUW AVX512EVEX AVX512 VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHUW AVX512EVEX AVX512 VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULHUW AVX512EVEX AVX512 VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHUW AVX512EVEX AVX512 VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULHW AVX AVX VPMULHW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULHW AVX AVX VPMULHW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULHW AVX512EVEX AVX512 VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHW AVX512EVEX AVX512 VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULHW AVX2 AVX2 VPMULHW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULHW AVX2 AVX2 VPMULHW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULHW AVX512EVEX AVX512 VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHW AVX512EVEX AVX512 VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULHW AVX512EVEX AVX512 VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULHW AVX512EVEX AVX512 VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULLD AVX AVX VPMULLD_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULLD AVX AVX VPMULLD_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULLD AVX512EVEX AVX512 VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLD AVX512EVEX AVX512 VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMULLD AVX2 AVX2 VPMULLD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULLD AVX2 AVX2 VPMULLD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULLD AVX512EVEX AVX512 VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLD AVX512EVEX AVX512 VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMULLD AVX512EVEX AVX512 VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLD AVX512EVEX AVX512 VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPMULLQ AVX512EVEX AVX512 VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLQ AVX512EVEX AVX512 VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VPMULLQ AVX512EVEX AVX512 VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLQ AVX512EVEX AVX512 VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VPMULLQ AVX512EVEX AVX512 VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULLQ AVX512EVEX AVX512 VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VPMULLW AVX AVX VPMULLW_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULLW AVX AVX VPMULLW_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULLW AVX512EVEX AVX512 VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULLW AVX512EVEX AVX512 VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPMULLW AVX2 AVX2 VPMULLW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULLW AVX2 AVX2 VPMULLW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULLW AVX512EVEX AVX512 VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULLW AVX512EVEX AVX512 VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPMULLW AVX512EVEX AVX512 VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPMULLW AVX512EVEX AVX512 VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 AVX512_VBMI_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 AVX512_VBMI_128 MASKOP_EVEX +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 AVX512_VBMI_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 AVX512_VBMI_256 MASKOP_EVEX +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 AVX512_VBMI_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPMULTISHIFTQB AVX512EVEX AVX512_VBMI VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 AVX512_VBMI_512 MASKOP_EVEX +VPMULUDQ AVX AVX VPMULUDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPMULUDQ AVX AVX VPMULUDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPMULUDQ AVX2 AVX2 VPMULUDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPMULUDQ AVX2 AVX2 VPMULUDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:DOUBLE_WIDE_MEMOP:DISP8_FULL:BROADCAST_ENABLED:MASKOP_EVEX +VPMULUDQ AVX512EVEX AVX512 VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 AVX512_BITALG_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 AVX512_BITALG_128 MASKOP_EVEX +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 AVX512_BITALG_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTB AVX512EVEX AVX512 VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 AVX512_BITALG_256 MASKOP_EVEX +VPOPCNTB AVX512EVEX AVX512_BITALG VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 AVX512_BITALG_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTB AVX512EVEX AVX512_BITALG VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 AVX512_BITALG_512 MASKOP_EVEX +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 AVX512_VPOPCNTDQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 AVX512_VPOPCNTDQ_128 MASKOP_EVEX +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 AVX512_VPOPCNTDQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 AVX512_VPOPCNTDQ_256 MASKOP_EVEX +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 AVX512_VPOPCNTDQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTD AVX512EVEX AVX512 VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 AVX512_VPOPCNTDQ_512 MASKOP_EVEX +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 AVX512_VPOPCNTDQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 AVX512_VPOPCNTDQ_128 MASKOP_EVEX +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 AVX512_VPOPCNTDQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 AVX512_VPOPCNTDQ_256 MASKOP_EVEX +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 AVX512_VPOPCNTDQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPOPCNTQ AVX512EVEX AVX512 VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 AVX512_VPOPCNTDQ_512 MASKOP_EVEX +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 AVX512_BITALG_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 AVX512_BITALG_128 MASKOP_EVEX +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 AVX512_BITALG_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTW AVX512EVEX AVX512 VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 AVX512_BITALG_256 MASKOP_EVEX +VPOPCNTW AVX512EVEX AVX512_BITALG VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 AVX512_BITALG_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPOPCNTW AVX512EVEX AVX512_BITALG VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 AVX512_BITALG_512 MASKOP_EVEX +VPORD AVX512EVEX LOGICAL VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORD AVX512EVEX LOGICAL VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPORD AVX512EVEX LOGICAL VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORD AVX512EVEX LOGICAL VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPORD AVX512EVEX LOGICAL VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORD AVX512EVEX LOGICAL VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPORQ AVX512EVEX LOGICAL VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORQ AVX512EVEX LOGICAL VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPORQ AVX512EVEX LOGICAL VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORQ AVX512EVEX LOGICAL VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPORQ AVX512EVEX LOGICAL VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPORQ AVX512EVEX LOGICAL VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPOR AVX LOGICAL VPOR_XMMdq_XMMdq_MEMdq AVX INVALID +VPOR AVX LOGICAL VPOR_XMMdq_XMMdq_XMMdq AVX INVALID +VPOR AVX2 LOGICAL VPOR_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPOR AVX2 LOGICAL VPOR_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPPERM XOP XOP VPPERM_XMMdq_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPPERM XOP XOP VPPERM_XMMdq_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPPERM XOP XOP VPPERM_XMMdq_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROLD AVX512EVEX AVX512 VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLD AVX512EVEX AVX512 VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPROLD AVX512EVEX AVX512 VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLD AVX512EVEX AVX512 VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPROLD AVX512EVEX AVX512 VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLD AVX512EVEX AVX512 VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPROLQ AVX512EVEX AVX512 VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLQ AVX512EVEX AVX512 VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPROLQ AVX512EVEX AVX512 VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLQ AVX512EVEX AVX512 VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPROLQ AVX512EVEX AVX512 VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLQ AVX512EVEX AVX512 VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPROLVD AVX512EVEX AVX512 VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVD AVX512EVEX AVX512 VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPROLVD AVX512EVEX AVX512 VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVD AVX512EVEX AVX512 VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPROLVD AVX512EVEX AVX512 VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVD AVX512EVEX AVX512 VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPROLVQ AVX512EVEX AVX512 VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVQ AVX512EVEX AVX512 VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPROLVQ AVX512EVEX AVX512 VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVQ AVX512EVEX AVX512 VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPROLVQ AVX512EVEX AVX512 VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPROLVQ AVX512EVEX AVX512 VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPRORD AVX512EVEX AVX512 VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORD AVX512EVEX AVX512 VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPRORD AVX512EVEX AVX512 VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORD AVX512EVEX AVX512 VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPRORD AVX512EVEX AVX512 VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORD AVX512EVEX AVX512 VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPRORQ AVX512EVEX AVX512 VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORQ AVX512EVEX AVX512 VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPRORQ AVX512EVEX AVX512 VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORQ AVX512EVEX AVX512 VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPRORQ AVX512EVEX AVX512 VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORQ AVX512EVEX AVX512 VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPRORVD AVX512EVEX AVX512 VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVD AVX512EVEX AVX512 VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPRORVD AVX512EVEX AVX512 VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVD AVX512EVEX AVX512 VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPRORVD AVX512EVEX AVX512 VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVD AVX512EVEX AVX512 VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPRORVQ AVX512EVEX AVX512 VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVQ AVX512EVEX AVX512 VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPRORVQ AVX512EVEX AVX512 VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVQ AVX512EVEX AVX512 VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPRORVQ AVX512EVEX AVX512 VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPRORVQ AVX512EVEX AVX512 VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPROTB XOP XOP VPROTB_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTB XOP XOP VPROTB_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTD XOP XOP VPROTD_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTQ XOP XOP VPROTQ_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_MEMdq_IMMb XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_XMMdq_IMMb XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPROTW XOP XOP VPROTW_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSADBW AVX AVX VPSADBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSADBW AVX AVX VPSADBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSADBW AVX512EVEX AVX512 VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 AVX512BW_128 DISP8_FULLMEM +VPSADBW AVX512EVEX AVX512 VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 AVX512BW_128 INVALID +VPSADBW AVX2 AVX2 VPSADBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSADBW AVX2 AVX2 VPSADBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSADBW AVX512EVEX AVX512 VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 AVX512BW_256 DISP8_FULLMEM +VPSADBW AVX512EVEX AVX512 VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 AVX512BW_256 INVALID +VPSADBW AVX512EVEX AVX512 VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 AVX512BW_512 DISP8_FULLMEM +VPSADBW AVX512EVEX AVX512 VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 AVX512BW_512 INVALID +VPSCATTERDD AVX512EVEX SCATTER VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDD AVX512EVEX SCATTER VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDD AVX512EVEX SCATTER VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDQ AVX512EVEX SCATTER VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDQ AVX512EVEX SCATTER VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERDQ AVX512EVEX SCATTER VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQD AVX512EVEX SCATTER VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQD AVX512EVEX SCATTER VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQD AVX512EVEX SCATTER VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQQ AVX512EVEX SCATTER VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQQ AVX512EVEX SCATTER VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSCATTERQQ AVX512EVEX SCATTER VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VPSHAB XOP XOP VPSHAB_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAB XOP XOP VPSHAB_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAB XOP XOP VPSHAB_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHAD XOP XOP VPSHAD_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAD XOP XOP VPSHAD_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAD XOP XOP VPSHAD_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHAQ XOP XOP VPSHAQ_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAQ XOP XOP VPSHAQ_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAQ XOP XOP VPSHAQ_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHAW XOP XOP VPSHAW_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHAW XOP XOP VPSHAW_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHAW XOP XOP VPSHAW_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLB XOP XOP VPSHLB_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLB XOP XOP VPSHLB_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLB XOP XOP VPSHLB_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDD AVX512EVEX VBMI2 VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDQ AVX512EVEX VBMI2 VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVD AVX512EVEX VBMI2 VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHLDVQ AVX512EVEX VBMI2 VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDVW AVX512EVEX VBMI2 VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHLDW AVX512EVEX VBMI2 VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHLD XOP XOP VPSHLD_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLD XOP XOP VPSHLD_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLD XOP XOP VPSHLD_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLQ XOP XOP VPSHLQ_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLQ XOP XOP VPSHLQ_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLQ XOP XOP VPSHLQ_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHLW XOP XOP VPSHLW_XMMdq_MEMdq_XMMdq XOP AMDONLY +VPSHLW XOP XOP VPSHLW_XMMdq_XMMdq_MEMdq XOP AMDONLY +VPSHLW XOP XOP VPSHLW_XMMdq_XMMdq_XMMdq XOP AMDONLY +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDD AVX512EVEX VBMI2 VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDQ AVX512EVEX VBMI2 VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVD AVX512EVEX VBMI2 VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHRDVQ AVX512EVEX VBMI2 VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDVW AVX512EVEX VBMI2 VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 AVX512_VBMI2_128 MASKOP_EVEX +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 AVX512_VBMI2_256 MASKOP_EVEX +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 AVX512_VBMI2_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHRDW AVX512EVEX VBMI2 VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 AVX512_VBMI2_512 MASKOP_EVEX +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 AVX512_BITALG_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 AVX512_BITALG_128 MASKOP_EVEX +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 AVX512_BITALG_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHUFBITQMB AVX512EVEX AVX512 VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 AVX512_BITALG_256 MASKOP_EVEX +VPSHUFBITQMB AVX512EVEX AVX512_BITALG VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 AVX512_BITALG_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSHUFBITQMB AVX512EVEX AVX512_BITALG VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 AVX512_BITALG_512 MASKOP_EVEX +VPSHUFB AVX AVX VPSHUFB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSHUFB AVX AVX VPSHUFB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSHUFB AVX512EVEX AVX512 VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFB AVX512EVEX AVX512 VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSHUFB AVX2 AVX2 VPSHUFB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSHUFB AVX2 AVX2 VPSHUFB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSHUFB AVX512EVEX AVX512 VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFB AVX512EVEX AVX512 VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSHUFB AVX512EVEX AVX512 VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFB AVX512EVEX AVX512 VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSHUFD AVX AVX VPSHUFD_XMMdq_MEMdq_IMMb AVX INVALID +VPSHUFD AVX AVX VPSHUFD_XMMdq_XMMdq_IMMb AVX INVALID +VPSHUFD AVX512EVEX AVX512 VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHUFD AVX512EVEX AVX512 VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSHUFD AVX2 AVX2 VPSHUFD_YMMqq_MEMqq_IMMb AVX2 INVALID +VPSHUFD AVX2 AVX2 VPSHUFD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSHUFD AVX512EVEX AVX512 VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHUFD AVX512EVEX AVX512 VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSHUFD AVX512EVEX AVX512 VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSHUFD AVX512EVEX AVX512 VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSHUFHW AVX AVX VPSHUFHW_XMMdq_MEMdq_IMMb AVX INVALID +VPSHUFHW AVX AVX VPSHUFHW_XMMdq_XMMdq_IMMb AVX INVALID +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSHUFHW AVX2 AVX2 VPSHUFHW_YMMqq_MEMqq_IMMb AVX2 INVALID +VPSHUFHW AVX2 AVX2 VPSHUFHW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFHW AVX512EVEX AVX512 VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSHUFLW AVX AVX VPSHUFLW_XMMdq_MEMdq_IMMb AVX INVALID +VPSHUFLW AVX AVX VPSHUFLW_XMMdq_XMMdq_IMMb AVX INVALID +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSHUFLW AVX2 AVX2 VPSHUFLW_YMMqq_MEMqq_IMMb AVX2 INVALID +VPSHUFLW AVX2 AVX2 VPSHUFLW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPSHUFLW AVX512EVEX AVX512 VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSIGNB AVX AVX VPSIGNB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSIGNB AVX AVX VPSIGNB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSIGNB AVX2 AVX2 VPSIGNB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSIGNB AVX2 AVX2 VPSIGNB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSIGND AVX AVX VPSIGND_XMMdq_XMMdq_MEMdq AVX INVALID +VPSIGND AVX AVX VPSIGND_XMMdq_XMMdq_XMMdq AVX INVALID +VPSIGND AVX2 AVX2 VPSIGND_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSIGND AVX2 AVX2 VPSIGND_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSIGNW AVX AVX VPSIGNW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSIGNW AVX AVX VPSIGNW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSIGNW AVX2 AVX2 VPSIGNW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSIGNW AVX2 AVX2 VPSIGNW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSLLDQ AVX AVX VPSLLDQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 DISP8_FULLMEM +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 INVALID +VPSLLDQ AVX2 AVX2 VPSLLDQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 DISP8_FULLMEM +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 INVALID +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 DISP8_FULLMEM +VPSLLDQ AVX512EVEX AVX512 VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 INVALID +VPSLLD AVX AVX VPSLLD_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLD AVX AVX VPSLLD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSLLD AVX AVX VPSLLD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSLLD AVX512EVEX AVX512 VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLD AVX2 AVX2 VPSLLD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLD AVX2 AVX2 VPSLLD_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSLLD AVX2 AVX2 VPSLLD_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSLLD AVX512EVEX AVX512 VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSLLD AVX512EVEX AVX512 VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLQ AVX AVX VPSLLQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLQ AVX AVX VPSLLQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPSLLQ AVX AVX VPSLLQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSLLQ AVX512EVEX AVX512 VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLQ AVX2 AVX2 VPSLLQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLQ AVX2 AVX2 VPSLLQ_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSLLQ AVX2 AVX2 VPSLLQ_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSLLQ AVX512EVEX AVX512 VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSLLQ AVX512EVEX AVX512 VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLVD AVX2 AVX2 VPSLLVD_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSLLVD AVX2 AVX2 VPSLLVD_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSLLVD AVX512EVEX AVX512 VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVD AVX512EVEX AVX512 VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLVD AVX2 AVX2 VPSLLVD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSLLVD AVX2 AVX2 VPSLLVD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSLLVD AVX512EVEX AVX512 VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVD AVX512EVEX AVX512 VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLVD AVX512EVEX AVX512 VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVD AVX512EVEX AVX512 VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLVQ AVX2 AVX2 VPSLLVQ_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSLLVQ AVX2 AVX2 VPSLLVQ_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSLLVQ AVX2 AVX2 VPSLLVQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSLLVQ AVX2 AVX2 VPSLLVQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSLLVQ AVX512EVEX AVX512 VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSLLVW AVX512EVEX AVX512 VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLVW AVX512EVEX AVX512 VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSLLVW AVX512EVEX AVX512 VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLVW AVX512EVEX AVX512 VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSLLVW AVX512EVEX AVX512 VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLVW AVX512EVEX AVX512 VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSLLW AVX AVX VPSLLW_XMMdq_XMMdq_IMMb AVX INVALID +VPSLLW AVX AVX VPSLLW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSLLW AVX AVX VPSLLW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_MEM128 +VPSLLW AVX512EVEX AVX512 VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSLLW AVX2 AVX2 VPSLLW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSLLW AVX2 AVX2 VPSLLW_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSLLW AVX2 AVX2 VPSLLW_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_MEM128 +VPSLLW AVX512EVEX AVX512 VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_MEM128 +VPSLLW AVX512EVEX AVX512 VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRAD AVX AVX VPSRAD_XMMdq_XMMdq_IMMb AVX INVALID +VPSRAD AVX AVX VPSRAD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRAD AVX AVX VPSRAD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRAD AVX512EVEX AVX512 VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAD AVX2 AVX2 VPSRAD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRAD AVX2 AVX2 VPSRAD_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRAD AVX2 AVX2 VPSRAD_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRAD AVX512EVEX AVX512 VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRAD AVX512EVEX AVX512 VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRAQ AVX512EVEX AVX512 VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRAQ AVX512EVEX AVX512 VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRAQ AVX512EVEX AVX512 VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAVD AVX2 AVX2 VPSRAVD_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSRAVD AVX2 AVX2 VPSRAVD_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSRAVD AVX512EVEX AVX512 VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVD AVX512EVEX AVX512 VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAVD AVX2 AVX2 VPSRAVD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSRAVD AVX2 AVX2 VPSRAVD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSRAVD AVX512EVEX AVX512 VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVD AVX512EVEX AVX512 VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAVD AVX512EVEX AVX512 VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVD AVX512EVEX AVX512 VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRAVQ AVX512EVEX AVX512 VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRAVW AVX512EVEX AVX512 VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAVW AVX512EVEX AVX512 VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRAVW AVX512EVEX AVX512 VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAVW AVX512EVEX AVX512 VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRAVW AVX512EVEX AVX512 VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAVW AVX512EVEX AVX512 VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRAW AVX AVX VPSRAW_XMMdq_XMMdq_IMMb AVX INVALID +VPSRAW AVX AVX VPSRAW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRAW AVX AVX VPSRAW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_MEM128 +VPSRAW AVX512EVEX AVX512 VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRAW AVX2 AVX2 VPSRAW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRAW AVX2 AVX2 VPSRAW_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRAW AVX2 AVX2 VPSRAW_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_MEM128 +VPSRAW AVX512EVEX AVX512 VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_MEM128 +VPSRAW AVX512EVEX AVX512 VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRLDQ AVX AVX VPSRLDQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 AVX512BW_128 DISP8_FULLMEM +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 AVX512BW_128 INVALID +VPSRLDQ AVX2 AVX2 VPSRLDQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 AVX512BW_256 DISP8_FULLMEM +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 AVX512BW_256 INVALID +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 AVX512BW_512 DISP8_FULLMEM +VPSRLDQ AVX512EVEX AVX512 VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 AVX512BW_512 INVALID +VPSRLD AVX AVX VPSRLD_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLD AVX AVX VPSRLD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRLD AVX AVX VPSRLD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRLD AVX512EVEX AVX512 VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLD AVX2 AVX2 VPSRLD_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLD AVX2 AVX2 VPSRLD_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRLD AVX2 AVX2 VPSRLD_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRLD AVX512EVEX AVX512 VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRLD AVX512EVEX AVX512 VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLQ AVX AVX VPSRLQ_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLQ AVX AVX VPSRLQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRLQ AVX AVX VPSRLQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_MEM128 +VPSRLQ AVX512EVEX AVX512 VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLQ AVX2 AVX2 VPSRLQ_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLQ AVX2 AVX2 VPSRLQ_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRLQ AVX2 AVX2 VPSRLQ_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_MEM128 +VPSRLQ AVX512EVEX AVX512 VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_MEM128 +VPSRLQ AVX512EVEX AVX512 VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLVD AVX2 AVX2 VPSRLVD_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSRLVD AVX2 AVX2 VPSRLVD_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSRLVD AVX512EVEX AVX512 VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVD AVX512EVEX AVX512 VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLVD AVX2 AVX2 VPSRLVD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSRLVD AVX2 AVX2 VPSRLVD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSRLVD AVX512EVEX AVX512 VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVD AVX512EVEX AVX512 VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLVD AVX512EVEX AVX512 VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVD AVX512EVEX AVX512 VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLVQ AVX2 AVX2 VPSRLVQ_XMMdq_XMMdq_MEMdq AVX2 INVALID +VPSRLVQ AVX2 AVX2 VPSRLVQ_XMMdq_XMMdq_XMMdq AVX2 INVALID +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSRLVQ AVX2 AVX2 VPSRLVQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSRLVQ AVX2 AVX2 VPSRLVQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSRLVQ AVX512EVEX AVX512 VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSRLVW AVX512EVEX AVX512 VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLVW AVX512EVEX AVX512 VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRLVW AVX512EVEX AVX512 VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLVW AVX512EVEX AVX512 VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRLVW AVX512EVEX AVX512 VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLVW AVX512EVEX AVX512 VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRLW AVX AVX VPSRLW_XMMdq_XMMdq_IMMb AVX INVALID +VPSRLW AVX AVX VPSRLW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSRLW AVX AVX VPSRLW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_MEM128 +VPSRLW AVX512EVEX AVX512 VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSRLW AVX2 AVX2 VPSRLW_YMMqq_YMMqq_IMMb AVX2 INVALID +VPSRLW AVX2 AVX2 VPSRLW_YMMqq_YMMqq_MEMdq AVX2 INVALID +VPSRLW AVX2 AVX2 VPSRLW_YMMqq_YMMqq_XMMq AVX2 INVALID +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_MEM128 +VPSRLW AVX512EVEX AVX512 VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_MEM128 +VPSRLW AVX512EVEX AVX512 VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBB AVX AVX VPSUBB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBB AVX AVX VPSUBB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBB AVX512EVEX AVX512 VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBB AVX512EVEX AVX512 VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBB AVX2 AVX2 VPSUBB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBB AVX2 AVX2 VPSUBB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBB AVX512EVEX AVX512 VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBB AVX512EVEX AVX512 VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBB AVX512EVEX AVX512 VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBB AVX512EVEX AVX512 VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBD AVX AVX VPSUBD_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBD AVX AVX VPSUBD_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBD AVX512EVEX AVX512 VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBD AVX512EVEX AVX512 VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPSUBD AVX2 AVX2 VPSUBD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBD AVX2 AVX2 VPSUBD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBD AVX512EVEX AVX512 VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBD AVX512EVEX AVX512 VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPSUBD AVX512EVEX AVX512 VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBD AVX512EVEX AVX512 VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPSUBQ AVX AVX VPSUBQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBQ AVX AVX VPSUBQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBQ AVX512EVEX AVX512 VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBQ AVX512EVEX AVX512 VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPSUBQ AVX2 AVX2 VPSUBQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBQ AVX2 AVX2 VPSUBQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBQ AVX512EVEX AVX512 VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBQ AVX512EVEX AVX512 VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPSUBQ AVX512EVEX AVX512 VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPSUBQ AVX512EVEX AVX512 VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPSUBSB AVX AVX VPSUBSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBSB AVX AVX VPSUBSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBSB AVX512EVEX AVX512 VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSB AVX512EVEX AVX512 VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBSB AVX512EVEX AVX512 VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSB AVX512EVEX AVX512 VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBSB AVX2 AVX2 VPSUBSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBSB AVX2 AVX2 VPSUBSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBSB AVX512EVEX AVX512 VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSB AVX512EVEX AVX512 VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBSW AVX AVX VPSUBSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBSW AVX AVX VPSUBSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBSW AVX512EVEX AVX512 VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSW AVX512EVEX AVX512 VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBSW AVX512EVEX AVX512 VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSW AVX512EVEX AVX512 VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBSW AVX2 AVX2 VPSUBSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBSW AVX2 AVX2 VPSUBSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBSW AVX512EVEX AVX512 VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBSW AVX512EVEX AVX512 VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBUSB AVX AVX VPSUBUSB_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBUSB AVX AVX VPSUBUSB_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBUSB AVX2 AVX2 VPSUBUSB_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBUSB AVX2 AVX2 VPSUBUSB_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSB AVX512EVEX AVX512 VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBUSW AVX AVX VPSUBUSW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBUSW AVX AVX VPSUBUSW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBUSW AVX2 AVX2 VPSUBUSW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBUSW AVX2 AVX2 VPSUBUSW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBUSW AVX512EVEX AVX512 VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPSUBW AVX AVX VPSUBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPSUBW AVX AVX VPSUBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPSUBW AVX512EVEX AVX512 VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBW AVX512EVEX AVX512 VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPSUBW AVX2 AVX2 VPSUBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPSUBW AVX2 AVX2 VPSUBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPSUBW AVX512EVEX AVX512 VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBW AVX512EVEX AVX512 VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPSUBW AVX512EVEX AVX512 VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPSUBW AVX512EVEX AVX512 VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGD AVX512EVEX LOGICAL VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTERNLOGQ AVX512EVEX LOGICAL VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMB AVX512EVEX LOGICAL VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMD AVX512EVEX LOGICAL VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTMQ AVX512EVEX LOGICAL VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTMW AVX512EVEX LOGICAL VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMB AVX512EVEX LOGICAL VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMD AVX512EVEX LOGICAL VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPTESTNMQ AVX512EVEX LOGICAL VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULLMEM +VPTESTNMW AVX512EVEX LOGICAL VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPTEST AVX LOGICAL VPTEST_XMMdq_MEMdq AVX INVALID +VPTEST AVX LOGICAL VPTEST_XMMdq_XMMdq AVX INVALID +VPTEST AVX LOGICAL VPTEST_YMMqq_MEMqq AVX INVALID +VPTEST AVX LOGICAL VPTEST_YMMqq_YMMqq AVX INVALID +VPUNPCKHBW AVX AVX VPUNPCKHBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHBW AVX AVX VPUNPCKHBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKHBW AVX2 AVX2 VPUNPCKHBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHBW AVX2 AVX2 VPUNPCKHBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHBW AVX512EVEX AVX512 VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPUNPCKHDQ AVX AVX VPUNPCKHDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHDQ AVX AVX VPUNPCKHDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKHDQ AVX2 AVX2 VPUNPCKHDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHDQ AVX2 AVX2 VPUNPCKHDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHDQ AVX512EVEX AVX512 VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKHQDQ AVX AVX VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHQDQ AVX AVX VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKHQDQ AVX2 AVX2 VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHQDQ AVX2 AVX2 VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKHQDQ AVX512EVEX AVX512 VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKHWD AVX AVX VPUNPCKHWD_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKHWD AVX AVX VPUNPCKHWD_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKHWD AVX2 AVX2 VPUNPCKHWD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKHWD AVX2 AVX2 VPUNPCKHWD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKHWD AVX512EVEX AVX512 VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPUNPCKLBW AVX AVX VPUNPCKLBW_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLBW AVX AVX VPUNPCKLBW_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKLBW AVX2 AVX2 VPUNPCKLBW_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLBW AVX2 AVX2 VPUNPCKLBW_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLBW AVX512EVEX AVX512 VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 AVX512BW_512 MASKOP_EVEX +VPUNPCKLDQ AVX AVX VPUNPCKLDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLDQ AVX AVX VPUNPCKLDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKLDQ AVX2 AVX2 VPUNPCKLDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLDQ AVX2 AVX2 VPUNPCKLDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLDQ AVX512EVEX AVX512 VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKLQDQ AVX AVX VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLQDQ AVX AVX VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPUNPCKLQDQ AVX2 AVX2 VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLQDQ AVX2 AVX2 VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPUNPCKLQDQ AVX512EVEX AVX512 VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPUNPCKLWD AVX AVX VPUNPCKLWD_XMMdq_XMMdq_MEMdq AVX INVALID +VPUNPCKLWD AVX AVX VPUNPCKLWD_XMMdq_XMMdq_XMMdq AVX INVALID +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 AVX512BW_128 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 AVX512BW_128 MASKOP_EVEX +VPUNPCKLWD AVX2 AVX2 VPUNPCKLWD_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPUNPCKLWD AVX2 AVX2 VPUNPCKLWD_YMMqq_YMMqq_YMMqq AVX2 INVALID +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 AVX512BW_256 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 AVX512BW_256 MASKOP_EVEX +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 AVX512BW_512 MASKOP_EVEX:DISP8_FULLMEM +VPUNPCKLWD AVX512EVEX AVX512 VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 AVX512BW_512 MASKOP_EVEX +VPXORD AVX512EVEX LOGICAL VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORD AVX512EVEX LOGICAL VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512F_128 MASKOP_EVEX +VPXORD AVX512EVEX LOGICAL VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORD AVX512EVEX LOGICAL VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512F_256 MASKOP_EVEX +VPXORD AVX512EVEX LOGICAL VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORD AVX512EVEX LOGICAL VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512F_512 MASKOP_EVEX +VPXORQ AVX512EVEX LOGICAL VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORQ AVX512EVEX LOGICAL VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512F_128 MASKOP_EVEX +VPXORQ AVX512EVEX LOGICAL VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORQ AVX512EVEX LOGICAL VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512F_256 MASKOP_EVEX +VPXORQ AVX512EVEX LOGICAL VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VPXORQ AVX512EVEX LOGICAL VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512F_512 MASKOP_EVEX +VPXOR AVX LOGICAL VPXOR_XMMdq_XMMdq_MEMdq AVX INVALID +VPXOR AVX LOGICAL VPXOR_XMMdq_XMMdq_XMMdq AVX INVALID +VPXOR AVX2 LOGICAL VPXOR_YMMqq_YMMqq_MEMqq AVX2 INVALID +VPXOR AVX2 LOGICAL VPXOR_YMMqq_YMMqq_YMMqq AVX2 INVALID +VRANGEPD AVX512EVEX AVX512 VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPD AVX512EVEX AVX512 VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VRANGEPD AVX512EVEX AVX512 VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPD AVX512EVEX AVX512 VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VRANGEPD AVX512EVEX AVX512 VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPD AVX512EVEX AVX512 VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VRANGEPS AVX512EVEX AVX512 VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPS AVX512EVEX AVX512 VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VRANGEPS AVX512EVEX AVX512 VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPS AVX512EVEX AVX512 VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VRANGEPS AVX512EVEX AVX512 VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRANGEPS AVX512EVEX AVX512 VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VRANGESD AVX512EVEX AVX512 VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRANGESD AVX512EVEX AVX512 VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRANGESS AVX512EVEX AVX512 VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRANGESS AVX512EVEX AVX512 VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRCP14PD AVX512EVEX AVX512 VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PD AVX512EVEX AVX512 VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRCP14PD AVX512EVEX AVX512 VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PD AVX512EVEX AVX512 VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRCP14PD AVX512EVEX AVX512 VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PD AVX512EVEX AVX512 VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRCP14PS AVX512EVEX AVX512 VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PS AVX512EVEX AVX512 VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRCP14PS AVX512EVEX AVX512 VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PS AVX512EVEX AVX512 VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRCP14PS AVX512EVEX AVX512 VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRCP14PS AVX512EVEX AVX512 VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRCP14SD AVX512EVEX AVX512 VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRCP14SD AVX512EVEX AVX512 VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRCP14SS AVX512EVEX AVX512 VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRCP14SS AVX512EVEX AVX512 VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRCP28PD AVX512EVEX AVX512 VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRCP28PD AVX512EVEX AVX512 VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRCP28PS AVX512EVEX AVX512 VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRCP28PS AVX512EVEX AVX512 VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRCP28SD AVX512EVEX AVX512 VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRCP28SD AVX512EVEX AVX512 VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRCP28SS AVX512EVEX AVX512 VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRCP28SS AVX512EVEX AVX512 VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRCPPH AVX512EVEX FP16 VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRCPPH AVX512EVEX FP16 VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX +VRCPPH AVX512EVEX FP16 VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRCPPH AVX512EVEX FP16 VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX +VRCPPH AVX512EVEX FP16 VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRCPPH AVX512EVEX FP16 VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX +VRCPPS AVX AVX VRCPPS_XMMdq_MEMdq AVX INVALID +VRCPPS AVX AVX VRCPPS_XMMdq_XMMdq AVX INVALID +VRCPPS AVX AVX VRCPPS_YMMqq_MEMqq AVX INVALID +VRCPPS AVX AVX VRCPPS_YMMqq_YMMqq AVX INVALID +VRCPSH AVX512EVEX FP16 VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VRCPSH AVX512EVEX FP16 VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VRCPSS AVX AVX VRCPSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR +VRCPSS AVX AVX VRCPSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPD AVX512EVEX AVX512 VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VREDUCEPH AVX512EVEX FP16 VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512DQ_128 MASKOP_EVEX:MXCSR +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512DQ_256 MASKOP_EVEX:MXCSR +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VREDUCEPS AVX512EVEX AVX512 VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512DQ_512 MASKOP_EVEX:MXCSR +VREDUCESD AVX512EVEX AVX512 VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VREDUCESD AVX512EVEX AVX512 VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VREDUCESH AVX512EVEX FP16 VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VREDUCESH AVX512EVEX FP16 VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VREDUCESS AVX512EVEX AVX512 VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512DQ_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VREDUCESS AVX512EVEX AVX512 VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512DQ_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPD AVX512EVEX AVX512 VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VRNDSCALEPH AVX512EVEX FP16 VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRNDSCALEPS AVX512EVEX AVX512 VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRNDSCALESD AVX512EVEX AVX512 VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRNDSCALESD AVX512EVEX AVX512 VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRNDSCALESH AVX512EVEX FP16 VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VRNDSCALESH AVX512EVEX FP16 VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRNDSCALESS AVX512EVEX AVX512 VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRNDSCALESS AVX512EVEX AVX512 VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VROUNDPD AVX AVX VROUNDPD_XMMdq_MEMdq_IMMb AVX MXCSR +VROUNDPD AVX AVX VROUNDPD_XMMdq_XMMdq_IMMb AVX MXCSR +VROUNDPD AVX AVX VROUNDPD_YMMqq_MEMqq_IMMb AVX MXCSR +VROUNDPD AVX AVX VROUNDPD_YMMqq_YMMqq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_XMMdq_MEMdq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_XMMdq_XMMdq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_YMMqq_MEMqq_IMMb AVX MXCSR +VROUNDPS AVX AVX VROUNDPS_YMMqq_YMMqq_IMMb AVX MXCSR +VROUNDSD AVX AVX VROUNDSD_XMMdq_XMMdq_MEMq_IMMb AVX MXCSR:SIMD_SCALAR +VROUNDSD AVX AVX VROUNDSD_XMMdq_XMMdq_XMMq_IMMb AVX MXCSR:SIMD_SCALAR +VROUNDSS AVX AVX VROUNDSS_XMMdq_XMMdq_MEMd_IMMb AVX MXCSR:SIMD_SCALAR +VROUNDSS AVX AVX VROUNDSS_XMMdq_XMMdq_XMMd_IMMb AVX MXCSR:SIMD_SCALAR +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PD AVX512EVEX AVX512 VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VRSQRT14PS AVX512EVEX AVX512 VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VRSQRT14SD AVX512EVEX AVX512 VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRSQRT14SD AVX512EVEX AVX512 VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRSQRT14SS AVX512EVEX AVX512 VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VRSQRT14SS AVX512EVEX AVX512 VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VRSQRT28PD AVX512EVEX AVX512 VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRSQRT28PD AVX512EVEX AVX512 VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRSQRT28PS AVX512EVEX AVX512 VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER AVX512ER_512 MXCSR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VRSQRT28PS AVX512EVEX AVX512 VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER AVX512ER_512 MXCSR:MASKOP_EVEX +VRSQRT28SD AVX512EVEX AVX512 VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRSQRT28SD AVX512EVEX AVX512 VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRSQRT28SS AVX512EVEX AVX512 VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_SCALAR +VRSQRT28SS AVX512EVEX AVX512 VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER AVX512ER_SCALAR MXCSR:SIMD_SCALAR:MASKOP_EVEX +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION +VRSQRTPH AVX512EVEX FP16 VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX +VRSQRTPS AVX AVX VRSQRTPS_XMMdq_MEMdq AVX INVALID +VRSQRTPS AVX AVX VRSQRTPS_XMMdq_XMMdq AVX INVALID +VRSQRTPS AVX AVX VRSQRTPS_YMMqq_MEMqq AVX INVALID +VRSQRTPS AVX AVX VRSQRTPS_YMMqq_YMMqq AVX INVALID +VRSQRTSH AVX512EVEX FP16 VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:SIMD_SCALAR +VRSQRTSH AVX512EVEX FP16 VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:SIMD_SCALAR +VRSQRTSS AVX AVX VRSQRTSS_XMMdq_XMMdq_MEMd AVX SIMD_SCALAR +VRSQRTSS AVX AVX VRSQRTSS_XMMdq_XMMdq_XMMd AVX SIMD_SCALAR +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPD AVX512EVEX AVX512 VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSCALEFPH AVX512EVEX FP16 VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSCALEFPS AVX512EVEX AVX512 VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSCALEFSD AVX512EVEX AVX512 VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSCALEFSD AVX512EVEX AVX512 VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSCALEFSH AVX512EVEX FP16 VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VSCALEFSH AVX512EVEX FP16 VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSCALEFSS AVX512EVEX AVX512 VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSCALEFSS AVX512EVEX AVX512 VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSCATTERDPD AVX512EVEX SCATTER VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPD AVX512EVEX SCATTER VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPD AVX512EVEX SCATTER VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPS AVX512EVEX SCATTER VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 AVX512F_128 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPS AVX512EVEX SCATTER VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 AVX512F_256 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERDPS AVX512EVEX SCATTER VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 AVX512F_512 DWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERPF0DPD AVX512EVEX SCATTER VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF0DPS AVX512EVEX SCATTER VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF0QPD AVX512EVEX SCATTER VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF0QPS AVX512EVEX SCATTER VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1DPD AVX512EVEX SCATTER VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1DPS AVX512EVEX SCATTER VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:DWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1QPD AVX512EVEX SCATTER VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERPF1QPS AVX512EVEX SCATTER VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 AVX512PF_512 MEMORY_FAULT_SUPPRESSION:SPECIAL_AGEN_REQUIRED:QWORD_INDICES:SCATTER:PREFETCH:MASKOP_EVEX:DISP8_GSCAT +VSCATTERQPD AVX512EVEX SCATTER VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPD AVX512EVEX SCATTER VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPD AVX512EVEX SCATTER VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPS AVX512EVEX SCATTER VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 AVX512F_128 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPS AVX512EVEX SCATTER VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 AVX512F_256 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSCATTERQPS AVX512EVEX SCATTER VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 AVX512F_512 QWORD_INDICES:DISP8_GSCAT:MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:SPECIAL_AGEN_REQUIRED:SCATTER +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF32X4 AVX512EVEX AVX512 VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFF64X2 AVX512EVEX AVX512 VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI32X4 AVX512EVEX AVX512 VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFI64X2 AVX512EVEX AVX512 VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFPD AVX AVX VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VSHUFPD AVX AVX VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VSHUFPD AVX512EVEX AVX512 VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPD AVX512EVEX AVX512 VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VSHUFPD AVX512EVEX AVX512 VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPD AVX512EVEX AVX512 VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFPD AVX AVX VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VSHUFPD AVX AVX VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VSHUFPD AVX512EVEX AVX512 VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPD AVX512EVEX AVX512 VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSHUFPS AVX AVX VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb AVX INVALID +VSHUFPS AVX AVX VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb AVX INVALID +VSHUFPS AVX512EVEX AVX512 VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPS AVX512EVEX AVX512 VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 AVX512F_128 MASKOP_EVEX +VSHUFPS AVX512EVEX AVX512 VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPS AVX512EVEX AVX512 VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 AVX512F_256 MASKOP_EVEX +VSHUFPS AVX AVX VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb AVX INVALID +VSHUFPS AVX AVX VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb AVX INVALID +VSHUFPS AVX512EVEX AVX512 VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VSHUFPS AVX512EVEX AVX512 VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 AVX512F_512 MASKOP_EVEX +VSQRTPD AVX AVX VSQRTPD_XMMdq_MEMdq AVX MXCSR +VSQRTPD AVX AVX VSQRTPD_XMMdq_XMMdq AVX MXCSR +VSQRTPD AVX512EVEX AVX512 VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPD AVX512EVEX AVX512 VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSQRTPD AVX512EVEX AVX512 VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPD AVX512EVEX AVX512 VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSQRTPD AVX AVX VSQRTPD_YMMqq_MEMqq AVX MXCSR +VSQRTPD AVX AVX VSQRTPD_YMMqq_YMMqq AVX MXCSR +VSQRTPD AVX512EVEX AVX512 VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPD AVX512EVEX AVX512 VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSQRTPH AVX512EVEX FP16 VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VSQRTPS AVX AVX VSQRTPS_XMMdq_MEMdq AVX MXCSR +VSQRTPS AVX AVX VSQRTPS_XMMdq_XMMdq AVX MXCSR +VSQRTPS AVX512EVEX AVX512 VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPS AVX512EVEX AVX512 VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSQRTPS AVX512EVEX AVX512 VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPS AVX512EVEX AVX512 VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSQRTPS AVX AVX VSQRTPS_YMMqq_MEMqq AVX MXCSR +VSQRTPS AVX AVX VSQRTPS_YMMqq_YMMqq AVX MXCSR +VSQRTPS AVX512EVEX AVX512 VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSQRTPS AVX512EVEX AVX512 VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSQRTSD AVX AVX VSQRTSD_XMMdq_XMMdq_MEMq AVX MXCSR:SIMD_SCALAR +VSQRTSD AVX AVX VSQRTSD_XMMdq_XMMdq_XMMq AVX MXCSR:SIMD_SCALAR +VSQRTSD AVX512EVEX AVX512 VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSQRTSD AVX512EVEX AVX512 VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSQRTSH AVX512EVEX FP16 VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VSQRTSH AVX512EVEX FP16 VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSQRTSS AVX AVX VSQRTSS_XMMdq_XMMdq_MEMd AVX MXCSR:SIMD_SCALAR +VSQRTSS AVX AVX VSQRTSS_XMMdq_XMMdq_XMMd AVX MXCSR:SIMD_SCALAR +VSQRTSS AVX512EVEX AVX512 VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSQRTSS AVX512EVEX AVX512 VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSTMXCSR AVX AVX VSTMXCSR_MEMd AVX MXCSR_RD +VSUBPD AVX AVX VSUBPD_XMMdq_XMMdq_MEMdq AVX MXCSR +VSUBPD AVX AVX VSUBPD_XMMdq_XMMdq_XMMdq AVX MXCSR +VSUBPD AVX512EVEX AVX512 VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPD AVX512EVEX AVX512 VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSUBPD AVX512EVEX AVX512 VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPD AVX512EVEX AVX512 VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSUBPD AVX AVX VSUBPD_YMMqq_YMMqq_MEMqq AVX MXCSR +VSUBPD AVX AVX VSUBPD_YMMqq_YMMqq_YMMqq AVX MXCSR +VSUBPD AVX512EVEX AVX512 VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPD AVX512EVEX AVX512 VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_128 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_128 MASKOP_EVEX:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 AVX512_FP16_256 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 AVX512_FP16_256 MASKOP_EVEX:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 AVX512_FP16_512 BROADCAST_ENABLED:DISP8_FULL:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR +VSUBPH AVX512EVEX FP16 VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 AVX512_FP16_512 MASKOP_EVEX:MXCSR +VSUBPS AVX AVX VSUBPS_XMMdq_XMMdq_MEMdq AVX MXCSR +VSUBPS AVX AVX VSUBPS_XMMdq_XMMdq_XMMdq AVX MXCSR +VSUBPS AVX512EVEX AVX512 VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPS AVX512EVEX AVX512 VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX:MXCSR +VSUBPS AVX512EVEX AVX512 VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPS AVX512EVEX AVX512 VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX:MXCSR +VSUBPS AVX AVX VSUBPS_YMMqq_YMMqq_MEMqq AVX MXCSR +VSUBPS AVX AVX VSUBPS_YMMqq_YMMqq_YMMqq AVX MXCSR +VSUBPS AVX512EVEX AVX512 VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:MXCSR:BROADCAST_ENABLED +VSUBPS AVX512EVEX AVX512 VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX:MXCSR +VSUBSD AVX AVX VSUBSD_XMMdq_XMMdq_MEMq AVX MXCSR:SIMD_SCALAR +VSUBSD AVX AVX VSUBSD_XMMdq_XMMdq_XMMq AVX MXCSR:SIMD_SCALAR +VSUBSD AVX512EVEX AVX512 VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSUBSD AVX512EVEX AVX512 VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSUBSH AVX512EVEX FP16 VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MASKOP_EVEX:MEMORY_FAULT_SUPPRESSION:MXCSR:SIMD_SCALAR +VSUBSH AVX512EVEX FP16 VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VSUBSS AVX AVX VSUBSS_XMMdq_XMMdq_MEMd AVX MXCSR:SIMD_SCALAR +VSUBSS AVX AVX VSUBSS_XMMdq_XMMdq_XMMd AVX MXCSR:SIMD_SCALAR +VSUBSS AVX512EVEX AVX512 VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:MXCSR:SIMD_SCALAR:DISP8_SCALAR +VSUBSS AVX512EVEX AVX512 VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MASKOP_EVEX:MXCSR:SIMD_SCALAR +VTESTPD AVX LOGICAL_FP VTESTPD_XMMdq_MEMdq AVX INVALID +VTESTPD AVX LOGICAL_FP VTESTPD_XMMdq_XMMdq AVX INVALID +VTESTPD AVX LOGICAL_FP VTESTPD_YMMqq_MEMqq AVX INVALID +VTESTPD AVX LOGICAL_FP VTESTPD_YMMqq_YMMqq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_XMMdq_MEMdq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_XMMdq_XMMdq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_YMMqq_MEMqq AVX INVALID +VTESTPS AVX LOGICAL_FP VTESTPS_YMMqq_YMMqq AVX INVALID +VUCOMISD AVX AVX VUCOMISD_XMMdq_MEMq AVX SIMD_SCALAR:MXCSR +VUCOMISD AVX AVX VUCOMISD_XMMdq_XMMq AVX SIMD_SCALAR:MXCSR +VUCOMISD AVX512EVEX AVX512 VUCOMISD_XMMf64_MEMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VUCOMISD AVX512EVEX AVX512 VUCOMISD_XMMf64_XMMf64_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VUCOMISH AVX512EVEX FP16 VUCOMISH_XMMf16_MEMf16_AVX512 AVX512_FP16_SCALAR DISP8_SCALAR:MXCSR:SIMD_SCALAR +VUCOMISH AVX512EVEX FP16 VUCOMISH_XMMf16_XMMf16_AVX512 AVX512_FP16_SCALAR MXCSR:SIMD_SCALAR +VUCOMISS AVX AVX VUCOMISS_XMMdq_MEMd AVX SIMD_SCALAR:MXCSR +VUCOMISS AVX AVX VUCOMISS_XMMdq_XMMd AVX SIMD_SCALAR:MXCSR +VUCOMISS AVX512EVEX AVX512 VUCOMISS_XMMf32_MEMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR:DISP8_SCALAR +VUCOMISS AVX512EVEX AVX512 VUCOMISS_XMMf32_XMMf32_AVX512 AVX512F_SCALAR MXCSR:SIMD_SCALAR +VUNPCKHPD AVX AVX VUNPCKHPD_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKHPD AVX AVX VUNPCKHPD_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKHPD AVX AVX VUNPCKHPD_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKHPD AVX AVX VUNPCKHPD_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPD AVX512EVEX AVX512 VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VUNPCKHPS AVX AVX VUNPCKHPS_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKHPS AVX AVX VUNPCKHPS_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKHPS AVX AVX VUNPCKHPS_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKHPS AVX AVX VUNPCKHPS_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKHPS AVX512EVEX AVX512 VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VUNPCKLPD AVX AVX VUNPCKLPD_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKLPD AVX AVX VUNPCKLPD_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKLPD AVX AVX VUNPCKLPD_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKLPD AVX AVX VUNPCKLPD_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPD AVX512EVEX AVX512 VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 AVX512F_512 MASKOP_EVEX +VUNPCKLPS AVX AVX VUNPCKLPS_XMMdq_XMMdq_MEMdq AVX INVALID +VUNPCKLPS AVX AVX VUNPCKLPS_XMMdq_XMMdq_XMMdq AVX INVALID +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 AVX512F_128 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 AVX512F_128 MASKOP_EVEX +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 AVX512F_256 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 AVX512F_256 MASKOP_EVEX +VUNPCKLPS AVX AVX VUNPCKLPS_YMMqq_YMMqq_MEMqq AVX INVALID +VUNPCKLPS AVX AVX VUNPCKLPS_YMMqq_YMMqq_YMMqq AVX INVALID +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 AVX512F_512 MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VUNPCKLPS AVX512EVEX AVX512 VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 AVX512F_512 MASKOP_EVEX +VXORPD AVX LOGICAL_FP VXORPD_XMMdq_XMMdq_MEMdq AVX INVALID +VXORPD AVX LOGICAL_FP VXORPD_XMMdq_XMMdq_XMMdq AVX INVALID +VXORPD AVX512EVEX LOGICAL_FP VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPD AVX512EVEX LOGICAL_FP VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 AVX512DQ_128 MASKOP_EVEX +VXORPD AVX LOGICAL_FP VXORPD_YMMqq_YMMqq_MEMqq AVX INVALID +VXORPD AVX LOGICAL_FP VXORPD_YMMqq_YMMqq_YMMqq AVX INVALID +VXORPD AVX512EVEX LOGICAL_FP VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPD AVX512EVEX LOGICAL_FP VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 AVX512DQ_256 MASKOP_EVEX +VXORPD AVX512EVEX LOGICAL_FP VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPD AVX512EVEX LOGICAL_FP VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 AVX512DQ_512 MASKOP_EVEX +VXORPS AVX LOGICAL_FP VXORPS_XMMdq_XMMdq_MEMdq AVX INVALID +VXORPS AVX LOGICAL_FP VXORPS_XMMdq_XMMdq_XMMdq AVX INVALID +VXORPS AVX512EVEX LOGICAL_FP VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 AVX512DQ_128 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPS AVX512EVEX LOGICAL_FP VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 AVX512DQ_128 MASKOP_EVEX +VXORPS AVX LOGICAL_FP VXORPS_YMMqq_YMMqq_MEMqq AVX INVALID +VXORPS AVX LOGICAL_FP VXORPS_YMMqq_YMMqq_YMMqq AVX INVALID +VXORPS AVX512EVEX LOGICAL_FP VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 AVX512DQ_256 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPS AVX512EVEX LOGICAL_FP VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 AVX512DQ_256 MASKOP_EVEX +VXORPS AVX512EVEX LOGICAL_FP VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 AVX512DQ_512 MEMORY_FAULT_SUPPRESSION:MASKOP_EVEX:DISP8_FULL:BROADCAST_ENABLED +VXORPS AVX512EVEX LOGICAL_FP VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 AVX512DQ_512 MASKOP_EVEX +VZEROALL AVX AVX VZEROALL AVX XMM_STATE_W +VZEROUPPER AVX AVX VZEROUPPER AVX XMM_STATE_W:NOTSX +WBINVD BASE SYSTEM WBINVD I486REAL RING0:NOTSX +WBNOINVD WBNOINVD SYSTEM WBNOINVD WBNOINVD RING0:NOTSX +WRFSBASE RDWRFSGS RDWRFSGS WRFSBASE_GPRy RDWRFSGS NOTSX:SCALABLE +WRGSBASE RDWRFSGS RDWRFSGS WRGSBASE_GPRy RDWRFSGS NOTSX:SCALABLE +WRMSR BASE SYSTEM WRMSR PENTIUMREAL RING0:NOTSX +WRPKRU PKU PKU WRPKRU PKU INVALID +WRSSD CET CET WRSSD_MEMu32_GPR32u32 CET INVALID +WRSSQ CET CET WRSSQ_MEMu64_GPR64u64 CET INVALID +WRUSSD CET CET WRUSSD_MEMu32_GPR32u32 CET INVALID +WRUSSQ CET CET WRUSSQ_MEMu64_GPR64u64 CET INVALID +XABORT RTM UNCOND_BR XABORT_IMMb RTM INVALID +XADD BASE SEMAPHORE XADD_GPR8_GPR8 I486REAL BYTEOP +XADD BASE SEMAPHORE XADD_GPRv_GPRv I486REAL SCALABLE +XADD_LOCK BASE SEMAPHORE XADD_LOCK_MEMb_GPR8 I486REAL BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XADD_LOCK BASE SEMAPHORE XADD_LOCK_MEMv_GPRv I486REAL LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XADD BASE SEMAPHORE XADD_MEMb_GPR8 I486REAL BYTEOP:LOCKABLE +XADD BASE SEMAPHORE XADD_MEMv_GPRv I486REAL LOCKABLE:SCALABLE +XBEGIN RTM COND_BR XBEGIN_RELBRz RTM SCALABLE +XCHG BASE DATAXFER XCHG_GPR8_GPR8 I86 BYTEOP +XCHG BASE DATAXFER XCHG_GPRv_GPRv I86 SCALABLE +XCHG BASE DATAXFER XCHG_GPRv_OrAX I86 SCALABLE +XCHG BASE DATAXFER XCHG_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XCHG BASE DATAXFER XCHG_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XEND RTM COND_BR XEND RTM INVALID +XGETBV XSAVE XSAVE XGETBV XSAVE INVALID +XLAT BASE MISC XLAT I86 FIXED_BASE0 +XORPD SSE2 LOGICAL_FP XORPD_XMMxuq_MEMxuq SSE2 REQUIRES_ALIGNMENT +XORPD SSE2 LOGICAL_FP XORPD_XMMxuq_XMMxuq SSE2 REQUIRES_ALIGNMENT +XORPS SSE LOGICAL_FP XORPS_XMMxud_MEMxud SSE REQUIRES_ALIGNMENT +XORPS SSE LOGICAL_FP XORPS_XMMxud_XMMxud SSE REQUIRES_ALIGNMENT +XOR BASE LOGICAL XOR_AL_IMMb I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_GPR8_30 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_GPR8_32 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_IMMb_80r6 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_IMMb_82r6 I86 BYTEOP +XOR BASE LOGICAL XOR_GPR8_MEMb I86 BYTEOP +XOR BASE LOGICAL XOR_GPRv_GPRv_31 I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_GPRv_33 I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_IMMb I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_IMMz I86 SCALABLE +XOR BASE LOGICAL XOR_GPRv_MEMv I86 SCALABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMb_GPR8 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMb_IMMb_80r6 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMb_IMMb_82r6 I86 BYTEOP:LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMv_GPRv I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMv_IMMb I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XOR_LOCK BASE LOGICAL XOR_LOCK_MEMv_IMMz I86 LOCKED:HLE_ACQ_ABLE:HLE_REL_ABLE:SCALABLE +XOR BASE LOGICAL XOR_MEMb_GPR8 I86 BYTEOP:LOCKABLE +XOR BASE LOGICAL XOR_MEMb_IMMb_80r6 I86 BYTEOP:LOCKABLE +XOR BASE LOGICAL XOR_MEMb_IMMb_82r6 I86 BYTEOP:LOCKABLE +XOR BASE LOGICAL XOR_MEMv_GPRv I86 LOCKABLE:SCALABLE +XOR BASE LOGICAL XOR_MEMv_IMMb I86 LOCKABLE:SCALABLE +XOR BASE LOGICAL XOR_MEMv_IMMz I86 LOCKABLE:SCALABLE +XOR BASE LOGICAL XOR_OrAX_IMMz I86 SCALABLE +XRESLDTRK TSX_LDTRK TSX_LDTRK XRESLDTRK TSX_LDTRK INVALID +XRSTOR64 XSAVE XSAVE XRSTOR64_MEMmxsave XSAVE XMM_STATE_CW:REQUIRES_ALIGNMENT:X87_MMX_STATE_CW:NOTSX:SPECIAL_AGEN_REQUIRED +XRSTORS64 XSAVES XSAVE XRSTORS64_MEMmxsave XSAVES XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:NOTSX:SPECIAL_AGEN_REQUIRED +XRSTORS XSAVES XSAVE XRSTORS_MEMmxsave XSAVES XMM_STATE_W:REQUIRES_ALIGNMENT:X87_MMX_STATE_W:NOTSX:SPECIAL_AGEN_REQUIRED +XRSTOR XSAVE XSAVE XRSTOR_MEMmxsave XSAVE XMM_STATE_CW:REQUIRES_ALIGNMENT:X87_MMX_STATE_CW:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVE64 XSAVE XSAVE XSAVE64_MEMmxsave XSAVE XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVEC64 XSAVEC XSAVE XSAVEC64_MEMmxsave XSAVEC XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVEC XSAVEC XSAVE XSAVEC_MEMmxsave XSAVEC XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVEOPT64 XSAVEOPT XSAVEOPT XSAVEOPT64_MEMmxsave XSAVEOPT XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX +XSAVEOPT XSAVEOPT XSAVEOPT XSAVEOPT_MEMmxsave XSAVEOPT XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX +XSAVES64 XSAVES XSAVE XSAVES64_MEMmxsave XSAVES XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVES XSAVES XSAVE XSAVES_MEMmxsave XSAVES XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSAVE XSAVE XSAVE XSAVE_MEMmxsave XSAVE XMM_STATE_R:REQUIRES_ALIGNMENT:X87_MMX_STATE_R:NOTSX:SPECIAL_AGEN_REQUIRED +XSETBV XSAVE XSAVE XSETBV XSAVE RING0:NOTSX +XSTORE VIA_PADLOCK_RNG VIA_PADLOCK XSTORE VIA_PADLOCK_RNG SCALABLE +XSUSLDTRK TSX_LDTRK TSX_LDTRK XSUSLDTRK TSX_LDTRK INVALID +XTEST RTM LOGICAL XTEST RTM INVALID diff --git a/CodeVirtualizer/build/obj/xed-address-width-enum.c b/CodeVirtualizer/build/obj/xed-address-width-enum.c new file mode 100644 index 0000000..2c35938 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-address-width-enum.c @@ -0,0 +1,69 @@ +/// @file xed-address-width-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-address-width-enum.h" + +typedef struct { + const char* name; + xed_address_width_enum_t value; +} name_table_xed_address_width_enum_t; +static const name_table_xed_address_width_enum_t name_array_xed_address_width_enum_t[] = { +{"INVALID", XED_ADDRESS_WIDTH_INVALID}, +{"16b", XED_ADDRESS_WIDTH_16b}, +{"32b", XED_ADDRESS_WIDTH_32b}, +{"64b", XED_ADDRESS_WIDTH_64b}, +{"LAST", XED_ADDRESS_WIDTH_LAST}, +{0, XED_ADDRESS_WIDTH_LAST}, +}; + + +xed_address_width_enum_t str2xed_address_width_enum_t(const char* s) +{ + const name_table_xed_address_width_enum_t* p = name_array_xed_address_width_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_ADDRESS_WIDTH_INVALID; +} + + +const char* xed_address_width_enum_t2str(const xed_address_width_enum_t p) +{ + const name_table_xed_address_width_enum_t* q = name_array_xed_address_width_enum_t; + while( q->name ) { + if (q->value == p) { + return q->name; + } + q++; + } + return "???"; +} + +xed_address_width_enum_t xed_address_width_enum_t_last(void) { + return XED_ADDRESS_WIDTH_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_ADDRESS_WIDTH_INVALID: + case XED_ADDRESS_WIDTH_16b: + case XED_ADDRESS_WIDTH_32b: + case XED_ADDRESS_WIDTH_64b: + case XED_ADDRESS_WIDTH_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-address-width-enum.h b/CodeVirtualizer/build/obj/xed-address-width-enum.h new file mode 100644 index 0000000..814b30a --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-address-width-enum.h @@ -0,0 +1,37 @@ +/// @file xed-address-width-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ADDRESS_WIDTH_ENUM_H) +# define XED_ADDRESS_WIDTH_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ADDRESS_WIDTH_INVALID_DEFINED 1 +#define XED_ADDRESS_WIDTH_16b_DEFINED 1 +#define XED_ADDRESS_WIDTH_32b_DEFINED 1 +#define XED_ADDRESS_WIDTH_64b_DEFINED 1 +#define XED_ADDRESS_WIDTH_LAST_DEFINED 1 +typedef enum { + XED_ADDRESS_WIDTH_INVALID=0, + XED_ADDRESS_WIDTH_16b=2, ///< 16b addressing + XED_ADDRESS_WIDTH_32b=4, ///< 32b addressing + XED_ADDRESS_WIDTH_64b=8, ///< 64b addressing + XED_ADDRESS_WIDTH_LAST +} xed_address_width_enum_t; + +/// This converts strings to #xed_address_width_enum_t types. +/// @param s A C-string. +/// @return #xed_address_width_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_address_width_enum_t str2xed_address_width_enum_t(const char* s); +/// This converts strings to #xed_address_width_enum_t types. +/// @param p An enumeration element of type xed_address_width_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_address_width_enum_t2str(const xed_address_width_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_address_width_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_address_width_enum_t xed_address_width_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-attribute-enum.c b/CodeVirtualizer/build/obj/xed-attribute-enum.c new file mode 100644 index 0000000..c3be13b --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-attribute-enum.c @@ -0,0 +1,244 @@ +/// @file xed-attribute-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-attribute-enum.h" + +typedef struct { + const char* name; + xed_attribute_enum_t value; +} name_table_xed_attribute_enum_t; +static const name_table_xed_attribute_enum_t name_array_xed_attribute_enum_t[] = { +{"INVALID", XED_ATTRIBUTE_INVALID}, +{"AMDONLY", XED_ATTRIBUTE_AMDONLY}, +{"ATT_OPERAND_ORDER_EXCEPTION", XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION}, +{"BROADCAST_ENABLED", XED_ATTRIBUTE_BROADCAST_ENABLED}, +{"BYTEOP", XED_ATTRIBUTE_BYTEOP}, +{"DISP8_EIGHTHMEM", XED_ATTRIBUTE_DISP8_EIGHTHMEM}, +{"DISP8_FULL", XED_ATTRIBUTE_DISP8_FULL}, +{"DISP8_FULLMEM", XED_ATTRIBUTE_DISP8_FULLMEM}, +{"DISP8_GPR_READER", XED_ATTRIBUTE_DISP8_GPR_READER}, +{"DISP8_GPR_READER_BYTE", XED_ATTRIBUTE_DISP8_GPR_READER_BYTE}, +{"DISP8_GPR_READER_WORD", XED_ATTRIBUTE_DISP8_GPR_READER_WORD}, +{"DISP8_GPR_WRITER_LDOP_D", XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D}, +{"DISP8_GPR_WRITER_LDOP_Q", XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q}, +{"DISP8_GPR_WRITER_STORE", XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE}, +{"DISP8_GPR_WRITER_STORE_BYTE", XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE}, +{"DISP8_GPR_WRITER_STORE_WORD", XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD}, +{"DISP8_GSCAT", XED_ATTRIBUTE_DISP8_GSCAT}, +{"DISP8_HALF", XED_ATTRIBUTE_DISP8_HALF}, +{"DISP8_HALFMEM", XED_ATTRIBUTE_DISP8_HALFMEM}, +{"DISP8_MEM128", XED_ATTRIBUTE_DISP8_MEM128}, +{"DISP8_MOVDDUP", XED_ATTRIBUTE_DISP8_MOVDDUP}, +{"DISP8_QUARTER", XED_ATTRIBUTE_DISP8_QUARTER}, +{"DISP8_QUARTERMEM", XED_ATTRIBUTE_DISP8_QUARTERMEM}, +{"DISP8_SCALAR", XED_ATTRIBUTE_DISP8_SCALAR}, +{"DISP8_TUPLE1", XED_ATTRIBUTE_DISP8_TUPLE1}, +{"DISP8_TUPLE1_4X", XED_ATTRIBUTE_DISP8_TUPLE1_4X}, +{"DISP8_TUPLE1_BYTE", XED_ATTRIBUTE_DISP8_TUPLE1_BYTE}, +{"DISP8_TUPLE1_WORD", XED_ATTRIBUTE_DISP8_TUPLE1_WORD}, +{"DISP8_TUPLE2", XED_ATTRIBUTE_DISP8_TUPLE2}, +{"DISP8_TUPLE4", XED_ATTRIBUTE_DISP8_TUPLE4}, +{"DISP8_TUPLE8", XED_ATTRIBUTE_DISP8_TUPLE8}, +{"DOUBLE_WIDE_MEMOP", XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP}, +{"DOUBLE_WIDE_OUTPUT", XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT}, +{"DWORD_INDICES", XED_ATTRIBUTE_DWORD_INDICES}, +{"ELEMENT_SIZE_D", XED_ATTRIBUTE_ELEMENT_SIZE_D}, +{"ELEMENT_SIZE_Q", XED_ATTRIBUTE_ELEMENT_SIZE_Q}, +{"EXCEPTION_BR", XED_ATTRIBUTE_EXCEPTION_BR}, +{"FAR_XFER", XED_ATTRIBUTE_FAR_XFER}, +{"FIXED_BASE0", XED_ATTRIBUTE_FIXED_BASE0}, +{"FIXED_BASE1", XED_ATTRIBUTE_FIXED_BASE1}, +{"GATHER", XED_ATTRIBUTE_GATHER}, +{"HALF_WIDE_OUTPUT", XED_ATTRIBUTE_HALF_WIDE_OUTPUT}, +{"HLE_ACQ_ABLE", XED_ATTRIBUTE_HLE_ACQ_ABLE}, +{"HLE_REL_ABLE", XED_ATTRIBUTE_HLE_REL_ABLE}, +{"IGNORES_OSFXSR", XED_ATTRIBUTE_IGNORES_OSFXSR}, +{"IMPLICIT_ONE", XED_ATTRIBUTE_IMPLICIT_ONE}, +{"INDEX_REG_IS_POINTER", XED_ATTRIBUTE_INDEX_REG_IS_POINTER}, +{"INDIRECT_BRANCH", XED_ATTRIBUTE_INDIRECT_BRANCH}, +{"KMASK", XED_ATTRIBUTE_KMASK}, +{"LOCKABLE", XED_ATTRIBUTE_LOCKABLE}, +{"LOCKED", XED_ATTRIBUTE_LOCKED}, +{"MASKOP", XED_ATTRIBUTE_MASKOP}, +{"MASKOP_EVEX", XED_ATTRIBUTE_MASKOP_EVEX}, +{"MASK_AS_CONTROL", XED_ATTRIBUTE_MASK_AS_CONTROL}, +{"MASK_VARIABLE_MEMOP", XED_ATTRIBUTE_MASK_VARIABLE_MEMOP}, +{"MEMORY_FAULT_SUPPRESSION", XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION}, +{"MMX_EXCEPT", XED_ATTRIBUTE_MMX_EXCEPT}, +{"MPX_PREFIX_ABLE", XED_ATTRIBUTE_MPX_PREFIX_ABLE}, +{"MULTIDEST2", XED_ATTRIBUTE_MULTIDEST2}, +{"MULTISOURCE4", XED_ATTRIBUTE_MULTISOURCE4}, +{"MXCSR", XED_ATTRIBUTE_MXCSR}, +{"MXCSR_RD", XED_ATTRIBUTE_MXCSR_RD}, +{"NONTEMPORAL", XED_ATTRIBUTE_NONTEMPORAL}, +{"NOP", XED_ATTRIBUTE_NOP}, +{"NOTSX", XED_ATTRIBUTE_NOTSX}, +{"NOTSX_COND", XED_ATTRIBUTE_NOTSX_COND}, +{"NO_RIP_REL", XED_ATTRIBUTE_NO_RIP_REL}, +{"NO_SRC_DEST_MATCH", XED_ATTRIBUTE_NO_SRC_DEST_MATCH}, +{"PREFETCH", XED_ATTRIBUTE_PREFETCH}, +{"PROTECTED_MODE", XED_ATTRIBUTE_PROTECTED_MODE}, +{"QWORD_INDICES", XED_ATTRIBUTE_QWORD_INDICES}, +{"REP", XED_ATTRIBUTE_REP}, +{"REQUIRES_ALIGNMENT", XED_ATTRIBUTE_REQUIRES_ALIGNMENT}, +{"RING0", XED_ATTRIBUTE_RING0}, +{"SCALABLE", XED_ATTRIBUTE_SCALABLE}, +{"SCATTER", XED_ATTRIBUTE_SCATTER}, +{"SIMD_SCALAR", XED_ATTRIBUTE_SIMD_SCALAR}, +{"SKIPLOW32", XED_ATTRIBUTE_SKIPLOW32}, +{"SKIPLOW64", XED_ATTRIBUTE_SKIPLOW64}, +{"SPECIAL_AGEN_REQUIRED", XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED}, +{"STACKPOP0", XED_ATTRIBUTE_STACKPOP0}, +{"STACKPOP1", XED_ATTRIBUTE_STACKPOP1}, +{"STACKPUSH0", XED_ATTRIBUTE_STACKPUSH0}, +{"STACKPUSH1", XED_ATTRIBUTE_STACKPUSH1}, +{"USES_DAZ", XED_ATTRIBUTE_USES_DAZ}, +{"USES_FTZ", XED_ATTRIBUTE_USES_FTZ}, +{"X87_CONTROL", XED_ATTRIBUTE_X87_CONTROL}, +{"X87_MMX_STATE_CW", XED_ATTRIBUTE_X87_MMX_STATE_CW}, +{"X87_MMX_STATE_R", XED_ATTRIBUTE_X87_MMX_STATE_R}, +{"X87_MMX_STATE_W", XED_ATTRIBUTE_X87_MMX_STATE_W}, +{"X87_NOWAIT", XED_ATTRIBUTE_X87_NOWAIT}, +{"XMM_STATE_CW", XED_ATTRIBUTE_XMM_STATE_CW}, +{"XMM_STATE_R", XED_ATTRIBUTE_XMM_STATE_R}, +{"XMM_STATE_W", XED_ATTRIBUTE_XMM_STATE_W}, +{"LAST", XED_ATTRIBUTE_LAST}, +{0, XED_ATTRIBUTE_LAST}, +}; + + +xed_attribute_enum_t str2xed_attribute_enum_t(const char* s) +{ + const name_table_xed_attribute_enum_t* p = name_array_xed_attribute_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_ATTRIBUTE_INVALID; +} + + +const char* xed_attribute_enum_t2str(const xed_attribute_enum_t p) +{ + xed_attribute_enum_t type_idx = p; + if ( p > XED_ATTRIBUTE_LAST) type_idx = XED_ATTRIBUTE_LAST; + return name_array_xed_attribute_enum_t[type_idx].name; +} + +xed_attribute_enum_t xed_attribute_enum_t_last(void) { + return XED_ATTRIBUTE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_ATTRIBUTE_INVALID: + case XED_ATTRIBUTE_AMDONLY: + case XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION: + case XED_ATTRIBUTE_BROADCAST_ENABLED: + case XED_ATTRIBUTE_BYTEOP: + case XED_ATTRIBUTE_DISP8_EIGHTHMEM: + case XED_ATTRIBUTE_DISP8_FULL: + case XED_ATTRIBUTE_DISP8_FULLMEM: + case XED_ATTRIBUTE_DISP8_GPR_READER: + case XED_ATTRIBUTE_DISP8_GPR_READER_BYTE: + case XED_ATTRIBUTE_DISP8_GPR_READER_WORD: + case XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D: + case XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q: + case XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE: + case XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE: + case XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD: + case XED_ATTRIBUTE_DISP8_GSCAT: + case XED_ATTRIBUTE_DISP8_HALF: + case XED_ATTRIBUTE_DISP8_HALFMEM: + case XED_ATTRIBUTE_DISP8_MEM128: + case XED_ATTRIBUTE_DISP8_MOVDDUP: + case XED_ATTRIBUTE_DISP8_QUARTER: + case XED_ATTRIBUTE_DISP8_QUARTERMEM: + case XED_ATTRIBUTE_DISP8_SCALAR: + case XED_ATTRIBUTE_DISP8_TUPLE1: + case XED_ATTRIBUTE_DISP8_TUPLE1_4X: + case XED_ATTRIBUTE_DISP8_TUPLE1_BYTE: + case XED_ATTRIBUTE_DISP8_TUPLE1_WORD: + case XED_ATTRIBUTE_DISP8_TUPLE2: + case XED_ATTRIBUTE_DISP8_TUPLE4: + case XED_ATTRIBUTE_DISP8_TUPLE8: + case XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP: + case XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT: + case XED_ATTRIBUTE_DWORD_INDICES: + case XED_ATTRIBUTE_ELEMENT_SIZE_D: + case XED_ATTRIBUTE_ELEMENT_SIZE_Q: + case XED_ATTRIBUTE_EXCEPTION_BR: + case XED_ATTRIBUTE_FAR_XFER: + case XED_ATTRIBUTE_FIXED_BASE0: + case XED_ATTRIBUTE_FIXED_BASE1: + case XED_ATTRIBUTE_GATHER: + case XED_ATTRIBUTE_HALF_WIDE_OUTPUT: + case XED_ATTRIBUTE_HLE_ACQ_ABLE: + case XED_ATTRIBUTE_HLE_REL_ABLE: + case XED_ATTRIBUTE_IGNORES_OSFXSR: + case XED_ATTRIBUTE_IMPLICIT_ONE: + case XED_ATTRIBUTE_INDEX_REG_IS_POINTER: + case XED_ATTRIBUTE_INDIRECT_BRANCH: + case XED_ATTRIBUTE_KMASK: + case XED_ATTRIBUTE_LOCKABLE: + case XED_ATTRIBUTE_LOCKED: + case XED_ATTRIBUTE_MASKOP: + case XED_ATTRIBUTE_MASKOP_EVEX: + case XED_ATTRIBUTE_MASK_AS_CONTROL: + case XED_ATTRIBUTE_MASK_VARIABLE_MEMOP: + case XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION: + case XED_ATTRIBUTE_MMX_EXCEPT: + case XED_ATTRIBUTE_MPX_PREFIX_ABLE: + case XED_ATTRIBUTE_MULTIDEST2: + case XED_ATTRIBUTE_MULTISOURCE4: + case XED_ATTRIBUTE_MXCSR: + case XED_ATTRIBUTE_MXCSR_RD: + case XED_ATTRIBUTE_NONTEMPORAL: + case XED_ATTRIBUTE_NOP: + case XED_ATTRIBUTE_NOTSX: + case XED_ATTRIBUTE_NOTSX_COND: + case XED_ATTRIBUTE_NO_RIP_REL: + case XED_ATTRIBUTE_NO_SRC_DEST_MATCH: + case XED_ATTRIBUTE_PREFETCH: + case XED_ATTRIBUTE_PROTECTED_MODE: + case XED_ATTRIBUTE_QWORD_INDICES: + case XED_ATTRIBUTE_REP: + case XED_ATTRIBUTE_REQUIRES_ALIGNMENT: + case XED_ATTRIBUTE_RING0: + case XED_ATTRIBUTE_SCALABLE: + case XED_ATTRIBUTE_SCATTER: + case XED_ATTRIBUTE_SIMD_SCALAR: + case XED_ATTRIBUTE_SKIPLOW32: + case XED_ATTRIBUTE_SKIPLOW64: + case XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED: + case XED_ATTRIBUTE_STACKPOP0: + case XED_ATTRIBUTE_STACKPOP1: + case XED_ATTRIBUTE_STACKPUSH0: + case XED_ATTRIBUTE_STACKPUSH1: + case XED_ATTRIBUTE_USES_DAZ: + case XED_ATTRIBUTE_USES_FTZ: + case XED_ATTRIBUTE_X87_CONTROL: + case XED_ATTRIBUTE_X87_MMX_STATE_CW: + case XED_ATTRIBUTE_X87_MMX_STATE_R: + case XED_ATTRIBUTE_X87_MMX_STATE_W: + case XED_ATTRIBUTE_X87_NOWAIT: + case XED_ATTRIBUTE_XMM_STATE_CW: + case XED_ATTRIBUTE_XMM_STATE_R: + case XED_ATTRIBUTE_XMM_STATE_W: + case XED_ATTRIBUTE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-attribute-enum.h b/CodeVirtualizer/build/obj/xed-attribute-enum.h new file mode 100644 index 0000000..5fc8f80 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-attribute-enum.h @@ -0,0 +1,217 @@ +/// @file xed-attribute-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ATTRIBUTE_ENUM_H) +# define XED_ATTRIBUTE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ATTRIBUTE_INVALID_DEFINED 1 +#define XED_ATTRIBUTE_AMDONLY_DEFINED 1 +#define XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION_DEFINED 1 +#define XED_ATTRIBUTE_BROADCAST_ENABLED_DEFINED 1 +#define XED_ATTRIBUTE_BYTEOP_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_EIGHTHMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_FULL_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_FULLMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_READER_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_READER_BYTE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_READER_WORD_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_GSCAT_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_HALF_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_HALFMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_MEM128_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_MOVDDUP_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_QUARTER_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_QUARTERMEM_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_SCALAR_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_4X_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_BYTE_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE1_WORD_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE2_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE4_DEFINED 1 +#define XED_ATTRIBUTE_DISP8_TUPLE8_DEFINED 1 +#define XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP_DEFINED 1 +#define XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT_DEFINED 1 +#define XED_ATTRIBUTE_DWORD_INDICES_DEFINED 1 +#define XED_ATTRIBUTE_ELEMENT_SIZE_D_DEFINED 1 +#define XED_ATTRIBUTE_ELEMENT_SIZE_Q_DEFINED 1 +#define XED_ATTRIBUTE_EXCEPTION_BR_DEFINED 1 +#define XED_ATTRIBUTE_FAR_XFER_DEFINED 1 +#define XED_ATTRIBUTE_FIXED_BASE0_DEFINED 1 +#define XED_ATTRIBUTE_FIXED_BASE1_DEFINED 1 +#define XED_ATTRIBUTE_GATHER_DEFINED 1 +#define XED_ATTRIBUTE_HALF_WIDE_OUTPUT_DEFINED 1 +#define XED_ATTRIBUTE_HLE_ACQ_ABLE_DEFINED 1 +#define XED_ATTRIBUTE_HLE_REL_ABLE_DEFINED 1 +#define XED_ATTRIBUTE_IGNORES_OSFXSR_DEFINED 1 +#define XED_ATTRIBUTE_IMPLICIT_ONE_DEFINED 1 +#define XED_ATTRIBUTE_INDEX_REG_IS_POINTER_DEFINED 1 +#define XED_ATTRIBUTE_INDIRECT_BRANCH_DEFINED 1 +#define XED_ATTRIBUTE_KMASK_DEFINED 1 +#define XED_ATTRIBUTE_LOCKABLE_DEFINED 1 +#define XED_ATTRIBUTE_LOCKED_DEFINED 1 +#define XED_ATTRIBUTE_MASKOP_DEFINED 1 +#define XED_ATTRIBUTE_MASKOP_EVEX_DEFINED 1 +#define XED_ATTRIBUTE_MASK_AS_CONTROL_DEFINED 1 +#define XED_ATTRIBUTE_MASK_VARIABLE_MEMOP_DEFINED 1 +#define XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION_DEFINED 1 +#define XED_ATTRIBUTE_MMX_EXCEPT_DEFINED 1 +#define XED_ATTRIBUTE_MPX_PREFIX_ABLE_DEFINED 1 +#define XED_ATTRIBUTE_MULTIDEST2_DEFINED 1 +#define XED_ATTRIBUTE_MULTISOURCE4_DEFINED 1 +#define XED_ATTRIBUTE_MXCSR_DEFINED 1 +#define XED_ATTRIBUTE_MXCSR_RD_DEFINED 1 +#define XED_ATTRIBUTE_NONTEMPORAL_DEFINED 1 +#define XED_ATTRIBUTE_NOP_DEFINED 1 +#define XED_ATTRIBUTE_NOTSX_DEFINED 1 +#define XED_ATTRIBUTE_NOTSX_COND_DEFINED 1 +#define XED_ATTRIBUTE_NO_RIP_REL_DEFINED 1 +#define XED_ATTRIBUTE_NO_SRC_DEST_MATCH_DEFINED 1 +#define XED_ATTRIBUTE_PREFETCH_DEFINED 1 +#define XED_ATTRIBUTE_PROTECTED_MODE_DEFINED 1 +#define XED_ATTRIBUTE_QWORD_INDICES_DEFINED 1 +#define XED_ATTRIBUTE_REP_DEFINED 1 +#define XED_ATTRIBUTE_REQUIRES_ALIGNMENT_DEFINED 1 +#define XED_ATTRIBUTE_RING0_DEFINED 1 +#define XED_ATTRIBUTE_SCALABLE_DEFINED 1 +#define XED_ATTRIBUTE_SCATTER_DEFINED 1 +#define XED_ATTRIBUTE_SIMD_SCALAR_DEFINED 1 +#define XED_ATTRIBUTE_SKIPLOW32_DEFINED 1 +#define XED_ATTRIBUTE_SKIPLOW64_DEFINED 1 +#define XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED_DEFINED 1 +#define XED_ATTRIBUTE_STACKPOP0_DEFINED 1 +#define XED_ATTRIBUTE_STACKPOP1_DEFINED 1 +#define XED_ATTRIBUTE_STACKPUSH0_DEFINED 1 +#define XED_ATTRIBUTE_STACKPUSH1_DEFINED 1 +#define XED_ATTRIBUTE_USES_DAZ_DEFINED 1 +#define XED_ATTRIBUTE_USES_FTZ_DEFINED 1 +#define XED_ATTRIBUTE_X87_CONTROL_DEFINED 1 +#define XED_ATTRIBUTE_X87_MMX_STATE_CW_DEFINED 1 +#define XED_ATTRIBUTE_X87_MMX_STATE_R_DEFINED 1 +#define XED_ATTRIBUTE_X87_MMX_STATE_W_DEFINED 1 +#define XED_ATTRIBUTE_X87_NOWAIT_DEFINED 1 +#define XED_ATTRIBUTE_XMM_STATE_CW_DEFINED 1 +#define XED_ATTRIBUTE_XMM_STATE_R_DEFINED 1 +#define XED_ATTRIBUTE_XMM_STATE_W_DEFINED 1 +#define XED_ATTRIBUTE_LAST_DEFINED 1 +typedef enum { + XED_ATTRIBUTE_INVALID, + XED_ATTRIBUTE_AMDONLY, + XED_ATTRIBUTE_ATT_OPERAND_ORDER_EXCEPTION, + XED_ATTRIBUTE_BROADCAST_ENABLED, + XED_ATTRIBUTE_BYTEOP, + XED_ATTRIBUTE_DISP8_EIGHTHMEM, + XED_ATTRIBUTE_DISP8_FULL, + XED_ATTRIBUTE_DISP8_FULLMEM, + XED_ATTRIBUTE_DISP8_GPR_READER, + XED_ATTRIBUTE_DISP8_GPR_READER_BYTE, + XED_ATTRIBUTE_DISP8_GPR_READER_WORD, + XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_D, + XED_ATTRIBUTE_DISP8_GPR_WRITER_LDOP_Q, + XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE, + XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_BYTE, + XED_ATTRIBUTE_DISP8_GPR_WRITER_STORE_WORD, + XED_ATTRIBUTE_DISP8_GSCAT, + XED_ATTRIBUTE_DISP8_HALF, + XED_ATTRIBUTE_DISP8_HALFMEM, + XED_ATTRIBUTE_DISP8_MEM128, + XED_ATTRIBUTE_DISP8_MOVDDUP, + XED_ATTRIBUTE_DISP8_QUARTER, + XED_ATTRIBUTE_DISP8_QUARTERMEM, + XED_ATTRIBUTE_DISP8_SCALAR, + XED_ATTRIBUTE_DISP8_TUPLE1, + XED_ATTRIBUTE_DISP8_TUPLE1_4X, + XED_ATTRIBUTE_DISP8_TUPLE1_BYTE, + XED_ATTRIBUTE_DISP8_TUPLE1_WORD, + XED_ATTRIBUTE_DISP8_TUPLE2, + XED_ATTRIBUTE_DISP8_TUPLE4, + XED_ATTRIBUTE_DISP8_TUPLE8, + XED_ATTRIBUTE_DOUBLE_WIDE_MEMOP, + XED_ATTRIBUTE_DOUBLE_WIDE_OUTPUT, + XED_ATTRIBUTE_DWORD_INDICES, + XED_ATTRIBUTE_ELEMENT_SIZE_D, + XED_ATTRIBUTE_ELEMENT_SIZE_Q, + XED_ATTRIBUTE_EXCEPTION_BR, + XED_ATTRIBUTE_FAR_XFER, + XED_ATTRIBUTE_FIXED_BASE0, + XED_ATTRIBUTE_FIXED_BASE1, + XED_ATTRIBUTE_GATHER, + XED_ATTRIBUTE_HALF_WIDE_OUTPUT, + XED_ATTRIBUTE_HLE_ACQ_ABLE, + XED_ATTRIBUTE_HLE_REL_ABLE, + XED_ATTRIBUTE_IGNORES_OSFXSR, + XED_ATTRIBUTE_IMPLICIT_ONE, + XED_ATTRIBUTE_INDEX_REG_IS_POINTER, + XED_ATTRIBUTE_INDIRECT_BRANCH, + XED_ATTRIBUTE_KMASK, + XED_ATTRIBUTE_LOCKABLE, + XED_ATTRIBUTE_LOCKED, + XED_ATTRIBUTE_MASKOP, + XED_ATTRIBUTE_MASKOP_EVEX, + XED_ATTRIBUTE_MASK_AS_CONTROL, + XED_ATTRIBUTE_MASK_VARIABLE_MEMOP, + XED_ATTRIBUTE_MEMORY_FAULT_SUPPRESSION, + XED_ATTRIBUTE_MMX_EXCEPT, + XED_ATTRIBUTE_MPX_PREFIX_ABLE, + XED_ATTRIBUTE_MULTIDEST2, + XED_ATTRIBUTE_MULTISOURCE4, + XED_ATTRIBUTE_MXCSR, + XED_ATTRIBUTE_MXCSR_RD, + XED_ATTRIBUTE_NONTEMPORAL, + XED_ATTRIBUTE_NOP, + XED_ATTRIBUTE_NOTSX, + XED_ATTRIBUTE_NOTSX_COND, + XED_ATTRIBUTE_NO_RIP_REL, + XED_ATTRIBUTE_NO_SRC_DEST_MATCH, + XED_ATTRIBUTE_PREFETCH, + XED_ATTRIBUTE_PROTECTED_MODE, + XED_ATTRIBUTE_QWORD_INDICES, + XED_ATTRIBUTE_REP, + XED_ATTRIBUTE_REQUIRES_ALIGNMENT, + XED_ATTRIBUTE_RING0, + XED_ATTRIBUTE_SCALABLE, + XED_ATTRIBUTE_SCATTER, + XED_ATTRIBUTE_SIMD_SCALAR, + XED_ATTRIBUTE_SKIPLOW32, + XED_ATTRIBUTE_SKIPLOW64, + XED_ATTRIBUTE_SPECIAL_AGEN_REQUIRED, + XED_ATTRIBUTE_STACKPOP0, + XED_ATTRIBUTE_STACKPOP1, + XED_ATTRIBUTE_STACKPUSH0, + XED_ATTRIBUTE_STACKPUSH1, + XED_ATTRIBUTE_USES_DAZ, + XED_ATTRIBUTE_USES_FTZ, + XED_ATTRIBUTE_X87_CONTROL, + XED_ATTRIBUTE_X87_MMX_STATE_CW, + XED_ATTRIBUTE_X87_MMX_STATE_R, + XED_ATTRIBUTE_X87_MMX_STATE_W, + XED_ATTRIBUTE_X87_NOWAIT, + XED_ATTRIBUTE_XMM_STATE_CW, + XED_ATTRIBUTE_XMM_STATE_R, + XED_ATTRIBUTE_XMM_STATE_W, + XED_ATTRIBUTE_LAST +} xed_attribute_enum_t; + +/// This converts strings to #xed_attribute_enum_t types. +/// @param s A C-string. +/// @return #xed_attribute_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_attribute_enum_t str2xed_attribute_enum_t(const char* s); +/// This converts strings to #xed_attribute_enum_t types. +/// @param p An enumeration element of type xed_attribute_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_attribute_enum_t2str(const xed_attribute_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_attribute_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_attribute_enum_t xed_attribute_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-attribute-enum.txt b/CodeVirtualizer/build/obj/xed-attribute-enum.txt new file mode 100644 index 0000000..a055306 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-attribute-enum.txt @@ -0,0 +1,124 @@ +# @file xed-attribute-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-attribute-enum.c +hfn xed-attribute-enum.h +typename xed_attribute_enum_t +prefix XED_ATTRIBUTE_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +AMDONLY +ATT_OPERAND_ORDER_EXCEPTION +BROADCAST_ENABLED +BYTEOP +DISP8_EIGHTHMEM +DISP8_FULL +DISP8_FULLMEM +DISP8_GPR_READER +DISP8_GPR_READER_BYTE +DISP8_GPR_READER_WORD +DISP8_GPR_WRITER_LDOP_D +DISP8_GPR_WRITER_LDOP_Q +DISP8_GPR_WRITER_STORE +DISP8_GPR_WRITER_STORE_BYTE +DISP8_GPR_WRITER_STORE_WORD +DISP8_GSCAT +DISP8_HALF +DISP8_HALFMEM +DISP8_MEM128 +DISP8_MOVDDUP +DISP8_QUARTER +DISP8_QUARTERMEM +DISP8_SCALAR +DISP8_TUPLE1 +DISP8_TUPLE1_4X +DISP8_TUPLE1_BYTE +DISP8_TUPLE1_WORD +DISP8_TUPLE2 +DISP8_TUPLE4 +DISP8_TUPLE8 +DOUBLE_WIDE_MEMOP +DOUBLE_WIDE_OUTPUT +DWORD_INDICES +ELEMENT_SIZE_D +ELEMENT_SIZE_Q +EXCEPTION_BR +FAR_XFER +FIXED_BASE0 +FIXED_BASE1 +GATHER +HALF_WIDE_OUTPUT +HLE_ACQ_ABLE +HLE_REL_ABLE +IGNORES_OSFXSR +IMPLICIT_ONE +INDEX_REG_IS_POINTER +INDIRECT_BRANCH +KMASK +LOCKABLE +LOCKED +MASKOP +MASKOP_EVEX +MASK_AS_CONTROL +MASK_VARIABLE_MEMOP +MEMORY_FAULT_SUPPRESSION +MMX_EXCEPT +MPX_PREFIX_ABLE +MULTIDEST2 +MULTISOURCE4 +MXCSR +MXCSR_RD +NONTEMPORAL +NOP +NOTSX +NOTSX_COND +NO_RIP_REL +NO_SRC_DEST_MATCH +PREFETCH +PROTECTED_MODE +QWORD_INDICES +REP +REQUIRES_ALIGNMENT +RING0 +SCALABLE +SCATTER +SIMD_SCALAR +SKIPLOW32 +SKIPLOW64 +SPECIAL_AGEN_REQUIRED +STACKPOP0 +STACKPOP1 +STACKPUSH0 +STACKPUSH1 +USES_DAZ +USES_FTZ +X87_CONTROL +X87_MMX_STATE_CW +X87_MMX_STATE_R +X87_MMX_STATE_W +X87_NOWAIT +XMM_STATE_CW +XMM_STATE_R +XMM_STATE_W diff --git a/CodeVirtualizer/build/obj/xed-attributes-init.c b/CodeVirtualizer/build/obj/xed-attributes-init.c new file mode 100644 index 0000000..65b7804 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-attributes-init.c @@ -0,0 +1,234 @@ +/// @file xed-attributes-init.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-attributes.h" +#include "xed-gen-table-defs.h" + +const xed_attributes_t xed_attributes[XED_MAX_REQUIRED_ATTRIBUTES] = { +/* 0 */ { 0,0 }, +/* 1 */ { 0,(((xed_uint64_t)1)<<(XED_ATTRIBUTE_NOTSX-64)) }, +/* 2 */ { 0,(((xed_uint64_t)1)<<(XED_ATTRIBUTE_NOTSX-64))|(((xed_uint64_t)1)<<(XED_ATTRIBUTE_X87_CONTROL-64)) }, +/* 3 */ { 0,(((xed_uint64_t)1)<<(XED_ATTRIBUTE_NOTSX-64))|(((xed_uint64_t)1)<<(XED_ATTRIBUTE_X87_CONTROL-64))|(((xed_uint64_t)1)<<(XED_ATTRIBUTE_X87_NOWAIT-64)) }, +/* 4 */ { (((xed_uint64_t)1)< +#include +#include "xed-category-enum.h" + +typedef struct { + const char* name; + xed_category_enum_t value; +} name_table_xed_category_enum_t; +static const name_table_xed_category_enum_t name_array_xed_category_enum_t[] = { +{"INVALID", XED_CATEGORY_INVALID}, +{"3DNOW", XED_CATEGORY_3DNOW}, +{"ADOX_ADCX", XED_CATEGORY_ADOX_ADCX}, +{"AES", XED_CATEGORY_AES}, +{"AMX_TILE", XED_CATEGORY_AMX_TILE}, +{"AVX", XED_CATEGORY_AVX}, +{"AVX2", XED_CATEGORY_AVX2}, +{"AVX2GATHER", XED_CATEGORY_AVX2GATHER}, +{"AVX512", XED_CATEGORY_AVX512}, +{"AVX512_4FMAPS", XED_CATEGORY_AVX512_4FMAPS}, +{"AVX512_4VNNIW", XED_CATEGORY_AVX512_4VNNIW}, +{"AVX512_BITALG", XED_CATEGORY_AVX512_BITALG}, +{"AVX512_VBMI", XED_CATEGORY_AVX512_VBMI}, +{"AVX512_VP2INTERSECT", XED_CATEGORY_AVX512_VP2INTERSECT}, +{"BINARY", XED_CATEGORY_BINARY}, +{"BITBYTE", XED_CATEGORY_BITBYTE}, +{"BLEND", XED_CATEGORY_BLEND}, +{"BMI1", XED_CATEGORY_BMI1}, +{"BMI2", XED_CATEGORY_BMI2}, +{"BROADCAST", XED_CATEGORY_BROADCAST}, +{"CALL", XED_CATEGORY_CALL}, +{"CET", XED_CATEGORY_CET}, +{"CLDEMOTE", XED_CATEGORY_CLDEMOTE}, +{"CLFLUSHOPT", XED_CATEGORY_CLFLUSHOPT}, +{"CLWB", XED_CATEGORY_CLWB}, +{"CLZERO", XED_CATEGORY_CLZERO}, +{"CMOV", XED_CATEGORY_CMOV}, +{"COMPRESS", XED_CATEGORY_COMPRESS}, +{"COND_BR", XED_CATEGORY_COND_BR}, +{"CONFLICT", XED_CATEGORY_CONFLICT}, +{"CONVERT", XED_CATEGORY_CONVERT}, +{"DATAXFER", XED_CATEGORY_DATAXFER}, +{"DECIMAL", XED_CATEGORY_DECIMAL}, +{"ENQCMD", XED_CATEGORY_ENQCMD}, +{"EXPAND", XED_CATEGORY_EXPAND}, +{"FCMOV", XED_CATEGORY_FCMOV}, +{"FLAGOP", XED_CATEGORY_FLAGOP}, +{"FMA4", XED_CATEGORY_FMA4}, +{"FP16", XED_CATEGORY_FP16}, +{"GATHER", XED_CATEGORY_GATHER}, +{"GFNI", XED_CATEGORY_GFNI}, +{"HRESET", XED_CATEGORY_HRESET}, +{"IFMA", XED_CATEGORY_IFMA}, +{"INTERRUPT", XED_CATEGORY_INTERRUPT}, +{"IO", XED_CATEGORY_IO}, +{"IOSTRINGOP", XED_CATEGORY_IOSTRINGOP}, +{"KEYLOCKER", XED_CATEGORY_KEYLOCKER}, +{"KEYLOCKER_WIDE", XED_CATEGORY_KEYLOCKER_WIDE}, +{"KMASK", XED_CATEGORY_KMASK}, +{"LEGACY", XED_CATEGORY_LEGACY}, +{"LOGICAL", XED_CATEGORY_LOGICAL}, +{"LOGICAL_FP", XED_CATEGORY_LOGICAL_FP}, +{"LZCNT", XED_CATEGORY_LZCNT}, +{"MISC", XED_CATEGORY_MISC}, +{"MMX", XED_CATEGORY_MMX}, +{"MOVDIR", XED_CATEGORY_MOVDIR}, +{"MPX", XED_CATEGORY_MPX}, +{"NOP", XED_CATEGORY_NOP}, +{"PCLMULQDQ", XED_CATEGORY_PCLMULQDQ}, +{"PCONFIG", XED_CATEGORY_PCONFIG}, +{"PKU", XED_CATEGORY_PKU}, +{"POP", XED_CATEGORY_POP}, +{"PREFETCH", XED_CATEGORY_PREFETCH}, +{"PREFETCHWT1", XED_CATEGORY_PREFETCHWT1}, +{"PTWRITE", XED_CATEGORY_PTWRITE}, +{"PUSH", XED_CATEGORY_PUSH}, +{"RDPID", XED_CATEGORY_RDPID}, +{"RDPRU", XED_CATEGORY_RDPRU}, +{"RDRAND", XED_CATEGORY_RDRAND}, +{"RDSEED", XED_CATEGORY_RDSEED}, +{"RDWRFSGS", XED_CATEGORY_RDWRFSGS}, +{"RET", XED_CATEGORY_RET}, +{"ROTATE", XED_CATEGORY_ROTATE}, +{"SCATTER", XED_CATEGORY_SCATTER}, +{"SEGOP", XED_CATEGORY_SEGOP}, +{"SEMAPHORE", XED_CATEGORY_SEMAPHORE}, +{"SERIALIZE", XED_CATEGORY_SERIALIZE}, +{"SETCC", XED_CATEGORY_SETCC}, +{"SGX", XED_CATEGORY_SGX}, +{"SHA", XED_CATEGORY_SHA}, +{"SHIFT", XED_CATEGORY_SHIFT}, +{"SMAP", XED_CATEGORY_SMAP}, +{"SSE", XED_CATEGORY_SSE}, +{"STRINGOP", XED_CATEGORY_STRINGOP}, +{"STTNI", XED_CATEGORY_STTNI}, +{"SYSCALL", XED_CATEGORY_SYSCALL}, +{"SYSRET", XED_CATEGORY_SYSRET}, +{"SYSTEM", XED_CATEGORY_SYSTEM}, +{"TBM", XED_CATEGORY_TBM}, +{"TSX_LDTRK", XED_CATEGORY_TSX_LDTRK}, +{"UINTR", XED_CATEGORY_UINTR}, +{"UNCOND_BR", XED_CATEGORY_UNCOND_BR}, +{"VAES", XED_CATEGORY_VAES}, +{"VBMI2", XED_CATEGORY_VBMI2}, +{"VEX", XED_CATEGORY_VEX}, +{"VFMA", XED_CATEGORY_VFMA}, +{"VIA_PADLOCK", XED_CATEGORY_VIA_PADLOCK}, +{"VPCLMULQDQ", XED_CATEGORY_VPCLMULQDQ}, +{"VTX", XED_CATEGORY_VTX}, +{"WAITPKG", XED_CATEGORY_WAITPKG}, +{"WIDENOP", XED_CATEGORY_WIDENOP}, +{"X87_ALU", XED_CATEGORY_X87_ALU}, +{"XOP", XED_CATEGORY_XOP}, +{"XSAVE", XED_CATEGORY_XSAVE}, +{"XSAVEOPT", XED_CATEGORY_XSAVEOPT}, +{"LAST", XED_CATEGORY_LAST}, +{0, XED_CATEGORY_LAST}, +}; + + +xed_category_enum_t str2xed_category_enum_t(const char* s) +{ + const name_table_xed_category_enum_t* p = name_array_xed_category_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_CATEGORY_INVALID; +} + + +const char* xed_category_enum_t2str(const xed_category_enum_t p) +{ + xed_category_enum_t type_idx = p; + if ( p > XED_CATEGORY_LAST) type_idx = XED_CATEGORY_LAST; + return name_array_xed_category_enum_t[type_idx].name; +} + +xed_category_enum_t xed_category_enum_t_last(void) { + return XED_CATEGORY_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_CATEGORY_INVALID: + case XED_CATEGORY_3DNOW: + case XED_CATEGORY_ADOX_ADCX: + case XED_CATEGORY_AES: + case XED_CATEGORY_AMX_TILE: + case XED_CATEGORY_AVX: + case XED_CATEGORY_AVX2: + case XED_CATEGORY_AVX2GATHER: + case XED_CATEGORY_AVX512: + case XED_CATEGORY_AVX512_4FMAPS: + case XED_CATEGORY_AVX512_4VNNIW: + case XED_CATEGORY_AVX512_BITALG: + case XED_CATEGORY_AVX512_VBMI: + case XED_CATEGORY_AVX512_VP2INTERSECT: + case XED_CATEGORY_BINARY: + case XED_CATEGORY_BITBYTE: + case XED_CATEGORY_BLEND: + case XED_CATEGORY_BMI1: + case XED_CATEGORY_BMI2: + case XED_CATEGORY_BROADCAST: + case XED_CATEGORY_CALL: + case XED_CATEGORY_CET: + case XED_CATEGORY_CLDEMOTE: + case XED_CATEGORY_CLFLUSHOPT: + case XED_CATEGORY_CLWB: + case XED_CATEGORY_CLZERO: + case XED_CATEGORY_CMOV: + case XED_CATEGORY_COMPRESS: + case XED_CATEGORY_COND_BR: + case XED_CATEGORY_CONFLICT: + case XED_CATEGORY_CONVERT: + case XED_CATEGORY_DATAXFER: + case XED_CATEGORY_DECIMAL: + case XED_CATEGORY_ENQCMD: + case XED_CATEGORY_EXPAND: + case XED_CATEGORY_FCMOV: + case XED_CATEGORY_FLAGOP: + case XED_CATEGORY_FMA4: + case XED_CATEGORY_FP16: + case XED_CATEGORY_GATHER: + case XED_CATEGORY_GFNI: + case XED_CATEGORY_HRESET: + case XED_CATEGORY_IFMA: + case XED_CATEGORY_INTERRUPT: + case XED_CATEGORY_IO: + case XED_CATEGORY_IOSTRINGOP: + case XED_CATEGORY_KEYLOCKER: + case XED_CATEGORY_KEYLOCKER_WIDE: + case XED_CATEGORY_KMASK: + case XED_CATEGORY_LEGACY: + case XED_CATEGORY_LOGICAL: + case XED_CATEGORY_LOGICAL_FP: + case XED_CATEGORY_LZCNT: + case XED_CATEGORY_MISC: + case XED_CATEGORY_MMX: + case XED_CATEGORY_MOVDIR: + case XED_CATEGORY_MPX: + case XED_CATEGORY_NOP: + case XED_CATEGORY_PCLMULQDQ: + case XED_CATEGORY_PCONFIG: + case XED_CATEGORY_PKU: + case XED_CATEGORY_POP: + case XED_CATEGORY_PREFETCH: + case XED_CATEGORY_PREFETCHWT1: + case XED_CATEGORY_PTWRITE: + case XED_CATEGORY_PUSH: + case XED_CATEGORY_RDPID: + case XED_CATEGORY_RDPRU: + case XED_CATEGORY_RDRAND: + case XED_CATEGORY_RDSEED: + case XED_CATEGORY_RDWRFSGS: + case XED_CATEGORY_RET: + case XED_CATEGORY_ROTATE: + case XED_CATEGORY_SCATTER: + case XED_CATEGORY_SEGOP: + case XED_CATEGORY_SEMAPHORE: + case XED_CATEGORY_SERIALIZE: + case XED_CATEGORY_SETCC: + case XED_CATEGORY_SGX: + case XED_CATEGORY_SHA: + case XED_CATEGORY_SHIFT: + case XED_CATEGORY_SMAP: + case XED_CATEGORY_SSE: + case XED_CATEGORY_STRINGOP: + case XED_CATEGORY_STTNI: + case XED_CATEGORY_SYSCALL: + case XED_CATEGORY_SYSRET: + case XED_CATEGORY_SYSTEM: + case XED_CATEGORY_TBM: + case XED_CATEGORY_TSX_LDTRK: + case XED_CATEGORY_UINTR: + case XED_CATEGORY_UNCOND_BR: + case XED_CATEGORY_VAES: + case XED_CATEGORY_VBMI2: + case XED_CATEGORY_VEX: + case XED_CATEGORY_VFMA: + case XED_CATEGORY_VIA_PADLOCK: + case XED_CATEGORY_VPCLMULQDQ: + case XED_CATEGORY_VTX: + case XED_CATEGORY_WAITPKG: + case XED_CATEGORY_WIDENOP: + case XED_CATEGORY_X87_ALU: + case XED_CATEGORY_XOP: + case XED_CATEGORY_XSAVE: + case XED_CATEGORY_XSAVEOPT: + case XED_CATEGORY_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-category-enum.h b/CodeVirtualizer/build/obj/xed-category-enum.h new file mode 100644 index 0000000..432be72 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-category-enum.h @@ -0,0 +1,239 @@ +/// @file xed-category-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CATEGORY_ENUM_H) +# define XED_CATEGORY_ENUM_H +#include "xed-common-hdrs.h" +#define XED_CATEGORY_INVALID_DEFINED 1 +#define XED_CATEGORY_3DNOW_DEFINED 1 +#define XED_CATEGORY_ADOX_ADCX_DEFINED 1 +#define XED_CATEGORY_AES_DEFINED 1 +#define XED_CATEGORY_AMX_TILE_DEFINED 1 +#define XED_CATEGORY_AVX_DEFINED 1 +#define XED_CATEGORY_AVX2_DEFINED 1 +#define XED_CATEGORY_AVX2GATHER_DEFINED 1 +#define XED_CATEGORY_AVX512_DEFINED 1 +#define XED_CATEGORY_AVX512_4FMAPS_DEFINED 1 +#define XED_CATEGORY_AVX512_4VNNIW_DEFINED 1 +#define XED_CATEGORY_AVX512_BITALG_DEFINED 1 +#define XED_CATEGORY_AVX512_VBMI_DEFINED 1 +#define XED_CATEGORY_AVX512_VP2INTERSECT_DEFINED 1 +#define XED_CATEGORY_BINARY_DEFINED 1 +#define XED_CATEGORY_BITBYTE_DEFINED 1 +#define XED_CATEGORY_BLEND_DEFINED 1 +#define XED_CATEGORY_BMI1_DEFINED 1 +#define XED_CATEGORY_BMI2_DEFINED 1 +#define XED_CATEGORY_BROADCAST_DEFINED 1 +#define XED_CATEGORY_CALL_DEFINED 1 +#define XED_CATEGORY_CET_DEFINED 1 +#define XED_CATEGORY_CLDEMOTE_DEFINED 1 +#define XED_CATEGORY_CLFLUSHOPT_DEFINED 1 +#define XED_CATEGORY_CLWB_DEFINED 1 +#define XED_CATEGORY_CLZERO_DEFINED 1 +#define XED_CATEGORY_CMOV_DEFINED 1 +#define XED_CATEGORY_COMPRESS_DEFINED 1 +#define XED_CATEGORY_COND_BR_DEFINED 1 +#define XED_CATEGORY_CONFLICT_DEFINED 1 +#define XED_CATEGORY_CONVERT_DEFINED 1 +#define XED_CATEGORY_DATAXFER_DEFINED 1 +#define XED_CATEGORY_DECIMAL_DEFINED 1 +#define XED_CATEGORY_ENQCMD_DEFINED 1 +#define XED_CATEGORY_EXPAND_DEFINED 1 +#define XED_CATEGORY_FCMOV_DEFINED 1 +#define XED_CATEGORY_FLAGOP_DEFINED 1 +#define XED_CATEGORY_FMA4_DEFINED 1 +#define XED_CATEGORY_FP16_DEFINED 1 +#define XED_CATEGORY_GATHER_DEFINED 1 +#define XED_CATEGORY_GFNI_DEFINED 1 +#define XED_CATEGORY_HRESET_DEFINED 1 +#define XED_CATEGORY_IFMA_DEFINED 1 +#define XED_CATEGORY_INTERRUPT_DEFINED 1 +#define XED_CATEGORY_IO_DEFINED 1 +#define XED_CATEGORY_IOSTRINGOP_DEFINED 1 +#define XED_CATEGORY_KEYLOCKER_DEFINED 1 +#define XED_CATEGORY_KEYLOCKER_WIDE_DEFINED 1 +#define XED_CATEGORY_KMASK_DEFINED 1 +#define XED_CATEGORY_LEGACY_DEFINED 1 +#define XED_CATEGORY_LOGICAL_DEFINED 1 +#define XED_CATEGORY_LOGICAL_FP_DEFINED 1 +#define XED_CATEGORY_LZCNT_DEFINED 1 +#define XED_CATEGORY_MISC_DEFINED 1 +#define XED_CATEGORY_MMX_DEFINED 1 +#define XED_CATEGORY_MOVDIR_DEFINED 1 +#define XED_CATEGORY_MPX_DEFINED 1 +#define XED_CATEGORY_NOP_DEFINED 1 +#define XED_CATEGORY_PCLMULQDQ_DEFINED 1 +#define XED_CATEGORY_PCONFIG_DEFINED 1 +#define XED_CATEGORY_PKU_DEFINED 1 +#define XED_CATEGORY_POP_DEFINED 1 +#define XED_CATEGORY_PREFETCH_DEFINED 1 +#define XED_CATEGORY_PREFETCHWT1_DEFINED 1 +#define XED_CATEGORY_PTWRITE_DEFINED 1 +#define XED_CATEGORY_PUSH_DEFINED 1 +#define XED_CATEGORY_RDPID_DEFINED 1 +#define XED_CATEGORY_RDPRU_DEFINED 1 +#define XED_CATEGORY_RDRAND_DEFINED 1 +#define XED_CATEGORY_RDSEED_DEFINED 1 +#define XED_CATEGORY_RDWRFSGS_DEFINED 1 +#define XED_CATEGORY_RET_DEFINED 1 +#define XED_CATEGORY_ROTATE_DEFINED 1 +#define XED_CATEGORY_SCATTER_DEFINED 1 +#define XED_CATEGORY_SEGOP_DEFINED 1 +#define XED_CATEGORY_SEMAPHORE_DEFINED 1 +#define XED_CATEGORY_SERIALIZE_DEFINED 1 +#define XED_CATEGORY_SETCC_DEFINED 1 +#define XED_CATEGORY_SGX_DEFINED 1 +#define XED_CATEGORY_SHA_DEFINED 1 +#define XED_CATEGORY_SHIFT_DEFINED 1 +#define XED_CATEGORY_SMAP_DEFINED 1 +#define XED_CATEGORY_SSE_DEFINED 1 +#define XED_CATEGORY_STRINGOP_DEFINED 1 +#define XED_CATEGORY_STTNI_DEFINED 1 +#define XED_CATEGORY_SYSCALL_DEFINED 1 +#define XED_CATEGORY_SYSRET_DEFINED 1 +#define XED_CATEGORY_SYSTEM_DEFINED 1 +#define XED_CATEGORY_TBM_DEFINED 1 +#define XED_CATEGORY_TSX_LDTRK_DEFINED 1 +#define XED_CATEGORY_UINTR_DEFINED 1 +#define XED_CATEGORY_UNCOND_BR_DEFINED 1 +#define XED_CATEGORY_VAES_DEFINED 1 +#define XED_CATEGORY_VBMI2_DEFINED 1 +#define XED_CATEGORY_VEX_DEFINED 1 +#define XED_CATEGORY_VFMA_DEFINED 1 +#define XED_CATEGORY_VIA_PADLOCK_DEFINED 1 +#define XED_CATEGORY_VPCLMULQDQ_DEFINED 1 +#define XED_CATEGORY_VTX_DEFINED 1 +#define XED_CATEGORY_WAITPKG_DEFINED 1 +#define XED_CATEGORY_WIDENOP_DEFINED 1 +#define XED_CATEGORY_X87_ALU_DEFINED 1 +#define XED_CATEGORY_XOP_DEFINED 1 +#define XED_CATEGORY_XSAVE_DEFINED 1 +#define XED_CATEGORY_XSAVEOPT_DEFINED 1 +#define XED_CATEGORY_LAST_DEFINED 1 +typedef enum { + XED_CATEGORY_INVALID, + XED_CATEGORY_3DNOW, + XED_CATEGORY_ADOX_ADCX, + XED_CATEGORY_AES, + XED_CATEGORY_AMX_TILE, + XED_CATEGORY_AVX, + XED_CATEGORY_AVX2, + XED_CATEGORY_AVX2GATHER, + XED_CATEGORY_AVX512, + XED_CATEGORY_AVX512_4FMAPS, + XED_CATEGORY_AVX512_4VNNIW, + XED_CATEGORY_AVX512_BITALG, + XED_CATEGORY_AVX512_VBMI, + XED_CATEGORY_AVX512_VP2INTERSECT, + XED_CATEGORY_BINARY, + XED_CATEGORY_BITBYTE, + XED_CATEGORY_BLEND, + XED_CATEGORY_BMI1, + XED_CATEGORY_BMI2, + XED_CATEGORY_BROADCAST, + XED_CATEGORY_CALL, + XED_CATEGORY_CET, + XED_CATEGORY_CLDEMOTE, + XED_CATEGORY_CLFLUSHOPT, + XED_CATEGORY_CLWB, + XED_CATEGORY_CLZERO, + XED_CATEGORY_CMOV, + XED_CATEGORY_COMPRESS, + XED_CATEGORY_COND_BR, + XED_CATEGORY_CONFLICT, + XED_CATEGORY_CONVERT, + XED_CATEGORY_DATAXFER, + XED_CATEGORY_DECIMAL, + XED_CATEGORY_ENQCMD, + XED_CATEGORY_EXPAND, + XED_CATEGORY_FCMOV, + XED_CATEGORY_FLAGOP, + XED_CATEGORY_FMA4, + XED_CATEGORY_FP16, + XED_CATEGORY_GATHER, + XED_CATEGORY_GFNI, + XED_CATEGORY_HRESET, + XED_CATEGORY_IFMA, + XED_CATEGORY_INTERRUPT, + XED_CATEGORY_IO, + XED_CATEGORY_IOSTRINGOP, + XED_CATEGORY_KEYLOCKER, + XED_CATEGORY_KEYLOCKER_WIDE, + XED_CATEGORY_KMASK, + XED_CATEGORY_LEGACY, + XED_CATEGORY_LOGICAL, + XED_CATEGORY_LOGICAL_FP, + XED_CATEGORY_LZCNT, + XED_CATEGORY_MISC, + XED_CATEGORY_MMX, + XED_CATEGORY_MOVDIR, + XED_CATEGORY_MPX, + XED_CATEGORY_NOP, + XED_CATEGORY_PCLMULQDQ, + XED_CATEGORY_PCONFIG, + XED_CATEGORY_PKU, + XED_CATEGORY_POP, + XED_CATEGORY_PREFETCH, + XED_CATEGORY_PREFETCHWT1, + XED_CATEGORY_PTWRITE, + XED_CATEGORY_PUSH, + XED_CATEGORY_RDPID, + XED_CATEGORY_RDPRU, + XED_CATEGORY_RDRAND, + XED_CATEGORY_RDSEED, + XED_CATEGORY_RDWRFSGS, + XED_CATEGORY_RET, + XED_CATEGORY_ROTATE, + XED_CATEGORY_SCATTER, + XED_CATEGORY_SEGOP, + XED_CATEGORY_SEMAPHORE, + XED_CATEGORY_SERIALIZE, + XED_CATEGORY_SETCC, + XED_CATEGORY_SGX, + XED_CATEGORY_SHA, + XED_CATEGORY_SHIFT, + XED_CATEGORY_SMAP, + XED_CATEGORY_SSE, + XED_CATEGORY_STRINGOP, + XED_CATEGORY_STTNI, + XED_CATEGORY_SYSCALL, + XED_CATEGORY_SYSRET, + XED_CATEGORY_SYSTEM, + XED_CATEGORY_TBM, + XED_CATEGORY_TSX_LDTRK, + XED_CATEGORY_UINTR, + XED_CATEGORY_UNCOND_BR, + XED_CATEGORY_VAES, + XED_CATEGORY_VBMI2, + XED_CATEGORY_VEX, + XED_CATEGORY_VFMA, + XED_CATEGORY_VIA_PADLOCK, + XED_CATEGORY_VPCLMULQDQ, + XED_CATEGORY_VTX, + XED_CATEGORY_WAITPKG, + XED_CATEGORY_WIDENOP, + XED_CATEGORY_X87_ALU, + XED_CATEGORY_XOP, + XED_CATEGORY_XSAVE, + XED_CATEGORY_XSAVEOPT, + XED_CATEGORY_LAST +} xed_category_enum_t; + +/// This converts strings to #xed_category_enum_t types. +/// @param s A C-string. +/// @return #xed_category_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_category_enum_t str2xed_category_enum_t(const char* s); +/// This converts strings to #xed_category_enum_t types. +/// @param p An enumeration element of type xed_category_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_category_enum_t2str(const xed_category_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_category_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_category_enum_t xed_category_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-category-enum.txt b/CodeVirtualizer/build/obj/xed-category-enum.txt new file mode 100644 index 0000000..f3f08f1 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-category-enum.txt @@ -0,0 +1,135 @@ +# @file xed-category-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-category-enum.c +hfn xed-category-enum.h +typename xed_category_enum_t +prefix XED_CATEGORY_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +3DNOW +ADOX_ADCX +AES +AMX_TILE +AVX +AVX2 +AVX2GATHER +AVX512 +AVX512_4FMAPS +AVX512_4VNNIW +AVX512_BITALG +AVX512_VBMI +AVX512_VP2INTERSECT +BINARY +BITBYTE +BLEND +BMI1 +BMI2 +BROADCAST +CALL +CET +CLDEMOTE +CLFLUSHOPT +CLWB +CLZERO +CMOV +COMPRESS +COND_BR +CONFLICT +CONVERT +DATAXFER +DECIMAL +ENQCMD +EXPAND +FCMOV +FLAGOP +FMA4 +FP16 +GATHER +GFNI +HRESET +IFMA +INTERRUPT +IO +IOSTRINGOP +KEYLOCKER +KEYLOCKER_WIDE +KMASK +LEGACY +LOGICAL +LOGICAL_FP +LZCNT +MISC +MMX +MOVDIR +MPX +NOP +PCLMULQDQ +PCONFIG +PKU +POP +PREFETCH +PREFETCHWT1 +PTWRITE +PUSH +RDPID +RDPRU +RDRAND +RDSEED +RDWRFSGS +RET +ROTATE +SCATTER +SEGOP +SEMAPHORE +SERIALIZE +SETCC +SGX +SHA +SHIFT +SMAP +SSE +STRINGOP +STTNI +SYSCALL +SYSRET +SYSTEM +TBM +TSX_LDTRK +UINTR +UNCOND_BR +VAES +VBMI2 +VEX +VFMA +VIA_PADLOCK +VPCLMULQDQ +VTX +WAITPKG +WIDENOP +X87_ALU +XOP +XSAVE +XSAVEOPT diff --git a/CodeVirtualizer/build/obj/xed-chip-enum.c b/CodeVirtualizer/build/obj/xed-chip-enum.c new file mode 100644 index 0000000..3fad89a --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-chip-enum.c @@ -0,0 +1,186 @@ +/// @file xed-chip-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-chip-enum.h" + +typedef struct { + const char* name; + xed_chip_enum_t value; +} name_table_xed_chip_enum_t; +static const name_table_xed_chip_enum_t name_array_xed_chip_enum_t[] = { +{"INVALID", XED_CHIP_INVALID}, +{"I86", XED_CHIP_I86}, +{"I86FP", XED_CHIP_I86FP}, +{"I186", XED_CHIP_I186}, +{"I186FP", XED_CHIP_I186FP}, +{"I286REAL", XED_CHIP_I286REAL}, +{"I286", XED_CHIP_I286}, +{"I2186FP", XED_CHIP_I2186FP}, +{"I386REAL", XED_CHIP_I386REAL}, +{"I386", XED_CHIP_I386}, +{"I386FP", XED_CHIP_I386FP}, +{"I486REAL", XED_CHIP_I486REAL}, +{"I486", XED_CHIP_I486}, +{"PENTIUMREAL", XED_CHIP_PENTIUMREAL}, +{"PENTIUM", XED_CHIP_PENTIUM}, +{"QUARK", XED_CHIP_QUARK}, +{"PENTIUMMMXREAL", XED_CHIP_PENTIUMMMXREAL}, +{"PENTIUMMMX", XED_CHIP_PENTIUMMMX}, +{"ALLREAL", XED_CHIP_ALLREAL}, +{"PENTIUMPRO", XED_CHIP_PENTIUMPRO}, +{"PENTIUM2", XED_CHIP_PENTIUM2}, +{"PENTIUM3", XED_CHIP_PENTIUM3}, +{"PENTIUM4", XED_CHIP_PENTIUM4}, +{"P4PRESCOTT", XED_CHIP_P4PRESCOTT}, +{"P4PRESCOTT_NOLAHF", XED_CHIP_P4PRESCOTT_NOLAHF}, +{"P4PRESCOTT_VTX", XED_CHIP_P4PRESCOTT_VTX}, +{"MEROM", XED_CHIP_MEROM}, +{"PENRYN", XED_CHIP_PENRYN}, +{"PENRYN_E", XED_CHIP_PENRYN_E}, +{"NEHALEM", XED_CHIP_NEHALEM}, +{"WESTMERE", XED_CHIP_WESTMERE}, +{"BONNELL", XED_CHIP_BONNELL}, +{"SALTWELL", XED_CHIP_SALTWELL}, +{"SILVERMONT", XED_CHIP_SILVERMONT}, +{"VIA", XED_CHIP_VIA}, +{"AMD_K10", XED_CHIP_AMD_K10}, +{"AMD_BULLDOZER", XED_CHIP_AMD_BULLDOZER}, +{"AMD_PILEDRIVER", XED_CHIP_AMD_PILEDRIVER}, +{"AMD_ZEN", XED_CHIP_AMD_ZEN}, +{"AMD_ZENPLUS", XED_CHIP_AMD_ZENPLUS}, +{"AMD_ZEN2", XED_CHIP_AMD_ZEN2}, +{"AMD_FUTURE", XED_CHIP_AMD_FUTURE}, +{"GOLDMONT", XED_CHIP_GOLDMONT}, +{"GOLDMONT_PLUS", XED_CHIP_GOLDMONT_PLUS}, +{"TREMONT", XED_CHIP_TREMONT}, +{"SNOW_RIDGE", XED_CHIP_SNOW_RIDGE}, +{"SANDYBRIDGE", XED_CHIP_SANDYBRIDGE}, +{"IVYBRIDGE", XED_CHIP_IVYBRIDGE}, +{"HASWELL", XED_CHIP_HASWELL}, +{"BROADWELL", XED_CHIP_BROADWELL}, +{"SKYLAKE", XED_CHIP_SKYLAKE}, +{"COMET_LAKE", XED_CHIP_COMET_LAKE}, +{"SKYLAKE_SERVER", XED_CHIP_SKYLAKE_SERVER}, +{"CASCADE_LAKE", XED_CHIP_CASCADE_LAKE}, +{"COOPER_LAKE", XED_CHIP_COOPER_LAKE}, +{"KNL", XED_CHIP_KNL}, +{"KNM", XED_CHIP_KNM}, +{"CANNONLAKE", XED_CHIP_CANNONLAKE}, +{"ICE_LAKE", XED_CHIP_ICE_LAKE}, +{"ICE_LAKE_SERVER", XED_CHIP_ICE_LAKE_SERVER}, +{"TIGER_LAKE", XED_CHIP_TIGER_LAKE}, +{"ALDER_LAKE", XED_CHIP_ALDER_LAKE}, +{"SAPPHIRE_RAPIDS", XED_CHIP_SAPPHIRE_RAPIDS}, +{"FUTURE", XED_CHIP_FUTURE}, +{"ALL", XED_CHIP_ALL}, +{"LAST", XED_CHIP_LAST}, +{0, XED_CHIP_LAST}, +}; + + +xed_chip_enum_t str2xed_chip_enum_t(const char* s) +{ + const name_table_xed_chip_enum_t* p = name_array_xed_chip_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_CHIP_INVALID; +} + + +const char* xed_chip_enum_t2str(const xed_chip_enum_t p) +{ + xed_chip_enum_t type_idx = p; + if ( p > XED_CHIP_LAST) type_idx = XED_CHIP_LAST; + return name_array_xed_chip_enum_t[type_idx].name; +} + +xed_chip_enum_t xed_chip_enum_t_last(void) { + return XED_CHIP_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_CHIP_INVALID: + case XED_CHIP_I86: + case XED_CHIP_I86FP: + case XED_CHIP_I186: + case XED_CHIP_I186FP: + case XED_CHIP_I286REAL: + case XED_CHIP_I286: + case XED_CHIP_I2186FP: + case XED_CHIP_I386REAL: + case XED_CHIP_I386: + case XED_CHIP_I386FP: + case XED_CHIP_I486REAL: + case XED_CHIP_I486: + case XED_CHIP_PENTIUMREAL: + case XED_CHIP_PENTIUM: + case XED_CHIP_QUARK: + case XED_CHIP_PENTIUMMMXREAL: + case XED_CHIP_PENTIUMMMX: + case XED_CHIP_ALLREAL: + case XED_CHIP_PENTIUMPRO: + case XED_CHIP_PENTIUM2: + case XED_CHIP_PENTIUM3: + case XED_CHIP_PENTIUM4: + case XED_CHIP_P4PRESCOTT: + case XED_CHIP_P4PRESCOTT_NOLAHF: + case XED_CHIP_P4PRESCOTT_VTX: + case XED_CHIP_MEROM: + case XED_CHIP_PENRYN: + case XED_CHIP_PENRYN_E: + case XED_CHIP_NEHALEM: + case XED_CHIP_WESTMERE: + case XED_CHIP_BONNELL: + case XED_CHIP_SALTWELL: + case XED_CHIP_SILVERMONT: + case XED_CHIP_VIA: + case XED_CHIP_AMD_K10: + case XED_CHIP_AMD_BULLDOZER: + case XED_CHIP_AMD_PILEDRIVER: + case XED_CHIP_AMD_ZEN: + case XED_CHIP_AMD_ZENPLUS: + case XED_CHIP_AMD_ZEN2: + case XED_CHIP_AMD_FUTURE: + case XED_CHIP_GOLDMONT: + case XED_CHIP_GOLDMONT_PLUS: + case XED_CHIP_TREMONT: + case XED_CHIP_SNOW_RIDGE: + case XED_CHIP_SANDYBRIDGE: + case XED_CHIP_IVYBRIDGE: + case XED_CHIP_HASWELL: + case XED_CHIP_BROADWELL: + case XED_CHIP_SKYLAKE: + case XED_CHIP_COMET_LAKE: + case XED_CHIP_SKYLAKE_SERVER: + case XED_CHIP_CASCADE_LAKE: + case XED_CHIP_COOPER_LAKE: + case XED_CHIP_KNL: + case XED_CHIP_KNM: + case XED_CHIP_CANNONLAKE: + case XED_CHIP_ICE_LAKE: + case XED_CHIP_ICE_LAKE_SERVER: + case XED_CHIP_TIGER_LAKE: + case XED_CHIP_ALDER_LAKE: + case XED_CHIP_SAPPHIRE_RAPIDS: + case XED_CHIP_FUTURE: + case XED_CHIP_ALL: + case XED_CHIP_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-chip-enum.h b/CodeVirtualizer/build/obj/xed-chip-enum.h new file mode 100644 index 0000000..91af1e0 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-chip-enum.h @@ -0,0 +1,159 @@ +/// @file xed-chip-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CHIP_ENUM_H) +# define XED_CHIP_ENUM_H +#include "xed-common-hdrs.h" +#define XED_CHIP_INVALID_DEFINED 1 +#define XED_CHIP_I86_DEFINED 1 +#define XED_CHIP_I86FP_DEFINED 1 +#define XED_CHIP_I186_DEFINED 1 +#define XED_CHIP_I186FP_DEFINED 1 +#define XED_CHIP_I286REAL_DEFINED 1 +#define XED_CHIP_I286_DEFINED 1 +#define XED_CHIP_I2186FP_DEFINED 1 +#define XED_CHIP_I386REAL_DEFINED 1 +#define XED_CHIP_I386_DEFINED 1 +#define XED_CHIP_I386FP_DEFINED 1 +#define XED_CHIP_I486REAL_DEFINED 1 +#define XED_CHIP_I486_DEFINED 1 +#define XED_CHIP_PENTIUMREAL_DEFINED 1 +#define XED_CHIP_PENTIUM_DEFINED 1 +#define XED_CHIP_QUARK_DEFINED 1 +#define XED_CHIP_PENTIUMMMXREAL_DEFINED 1 +#define XED_CHIP_PENTIUMMMX_DEFINED 1 +#define XED_CHIP_ALLREAL_DEFINED 1 +#define XED_CHIP_PENTIUMPRO_DEFINED 1 +#define XED_CHIP_PENTIUM2_DEFINED 1 +#define XED_CHIP_PENTIUM3_DEFINED 1 +#define XED_CHIP_PENTIUM4_DEFINED 1 +#define XED_CHIP_P4PRESCOTT_DEFINED 1 +#define XED_CHIP_P4PRESCOTT_NOLAHF_DEFINED 1 +#define XED_CHIP_P4PRESCOTT_VTX_DEFINED 1 +#define XED_CHIP_MEROM_DEFINED 1 +#define XED_CHIP_PENRYN_DEFINED 1 +#define XED_CHIP_PENRYN_E_DEFINED 1 +#define XED_CHIP_NEHALEM_DEFINED 1 +#define XED_CHIP_WESTMERE_DEFINED 1 +#define XED_CHIP_BONNELL_DEFINED 1 +#define XED_CHIP_SALTWELL_DEFINED 1 +#define XED_CHIP_SILVERMONT_DEFINED 1 +#define XED_CHIP_VIA_DEFINED 1 +#define XED_CHIP_AMD_K10_DEFINED 1 +#define XED_CHIP_AMD_BULLDOZER_DEFINED 1 +#define XED_CHIP_AMD_PILEDRIVER_DEFINED 1 +#define XED_CHIP_AMD_ZEN_DEFINED 1 +#define XED_CHIP_AMD_ZENPLUS_DEFINED 1 +#define XED_CHIP_AMD_ZEN2_DEFINED 1 +#define XED_CHIP_AMD_FUTURE_DEFINED 1 +#define XED_CHIP_GOLDMONT_DEFINED 1 +#define XED_CHIP_GOLDMONT_PLUS_DEFINED 1 +#define XED_CHIP_TREMONT_DEFINED 1 +#define XED_CHIP_SNOW_RIDGE_DEFINED 1 +#define XED_CHIP_SANDYBRIDGE_DEFINED 1 +#define XED_CHIP_IVYBRIDGE_DEFINED 1 +#define XED_CHIP_HASWELL_DEFINED 1 +#define XED_CHIP_BROADWELL_DEFINED 1 +#define XED_CHIP_SKYLAKE_DEFINED 1 +#define XED_CHIP_COMET_LAKE_DEFINED 1 +#define XED_CHIP_SKYLAKE_SERVER_DEFINED 1 +#define XED_CHIP_CASCADE_LAKE_DEFINED 1 +#define XED_CHIP_COOPER_LAKE_DEFINED 1 +#define XED_CHIP_KNL_DEFINED 1 +#define XED_CHIP_KNM_DEFINED 1 +#define XED_CHIP_CANNONLAKE_DEFINED 1 +#define XED_CHIP_ICE_LAKE_DEFINED 1 +#define XED_CHIP_ICE_LAKE_SERVER_DEFINED 1 +#define XED_CHIP_TIGER_LAKE_DEFINED 1 +#define XED_CHIP_ALDER_LAKE_DEFINED 1 +#define XED_CHIP_SAPPHIRE_RAPIDS_DEFINED 1 +#define XED_CHIP_FUTURE_DEFINED 1 +#define XED_CHIP_ALL_DEFINED 1 +#define XED_CHIP_LAST_DEFINED 1 +typedef enum { + XED_CHIP_INVALID, + XED_CHIP_I86, + XED_CHIP_I86FP, + XED_CHIP_I186, + XED_CHIP_I186FP, + XED_CHIP_I286REAL, + XED_CHIP_I286, + XED_CHIP_I2186FP, + XED_CHIP_I386REAL, + XED_CHIP_I386, + XED_CHIP_I386FP, + XED_CHIP_I486REAL, + XED_CHIP_I486, + XED_CHIP_PENTIUMREAL, + XED_CHIP_PENTIUM, + XED_CHIP_QUARK, + XED_CHIP_PENTIUMMMXREAL, + XED_CHIP_PENTIUMMMX, + XED_CHIP_ALLREAL, + XED_CHIP_PENTIUMPRO, + XED_CHIP_PENTIUM2, + XED_CHIP_PENTIUM3, + XED_CHIP_PENTIUM4, + XED_CHIP_P4PRESCOTT, + XED_CHIP_P4PRESCOTT_NOLAHF, + XED_CHIP_P4PRESCOTT_VTX, + XED_CHIP_MEROM, + XED_CHIP_PENRYN, + XED_CHIP_PENRYN_E, + XED_CHIP_NEHALEM, + XED_CHIP_WESTMERE, + XED_CHIP_BONNELL, + XED_CHIP_SALTWELL, + XED_CHIP_SILVERMONT, + XED_CHIP_VIA, + XED_CHIP_AMD_K10, + XED_CHIP_AMD_BULLDOZER, + XED_CHIP_AMD_PILEDRIVER, + XED_CHIP_AMD_ZEN, + XED_CHIP_AMD_ZENPLUS, + XED_CHIP_AMD_ZEN2, + XED_CHIP_AMD_FUTURE, + XED_CHIP_GOLDMONT, + XED_CHIP_GOLDMONT_PLUS, + XED_CHIP_TREMONT, + XED_CHIP_SNOW_RIDGE, + XED_CHIP_SANDYBRIDGE, + XED_CHIP_IVYBRIDGE, + XED_CHIP_HASWELL, + XED_CHIP_BROADWELL, + XED_CHIP_SKYLAKE, + XED_CHIP_COMET_LAKE, + XED_CHIP_SKYLAKE_SERVER, + XED_CHIP_CASCADE_LAKE, + XED_CHIP_COOPER_LAKE, + XED_CHIP_KNL, + XED_CHIP_KNM, + XED_CHIP_CANNONLAKE, + XED_CHIP_ICE_LAKE, + XED_CHIP_ICE_LAKE_SERVER, + XED_CHIP_TIGER_LAKE, + XED_CHIP_ALDER_LAKE, + XED_CHIP_SAPPHIRE_RAPIDS, + XED_CHIP_FUTURE, + XED_CHIP_ALL, + XED_CHIP_LAST +} xed_chip_enum_t; + +/// This converts strings to #xed_chip_enum_t types. +/// @param s A C-string. +/// @return #xed_chip_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_chip_enum_t str2xed_chip_enum_t(const char* s); +/// This converts strings to #xed_chip_enum_t types. +/// @param p An enumeration element of type xed_chip_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_chip_enum_t2str(const xed_chip_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_chip_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_chip_enum_t xed_chip_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-chip-enum.txt b/CodeVirtualizer/build/obj/xed-chip-enum.txt new file mode 100644 index 0000000..9f2f88e --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-chip-enum.txt @@ -0,0 +1,95 @@ +# @file xed-chip-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-chip-enum.c +hfn xed-chip-enum.h +typename xed_chip_enum_t +prefix XED_CHIP_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +I86 +I86FP +I186 +I186FP +I286REAL +I286 +I2186FP +I386REAL +I386 +I386FP +I486REAL +I486 +PENTIUMREAL +PENTIUM +QUARK +PENTIUMMMXREAL +PENTIUMMMX +ALLREAL +PENTIUMPRO +PENTIUM2 +PENTIUM3 +PENTIUM4 +P4PRESCOTT +P4PRESCOTT_NOLAHF +P4PRESCOTT_VTX +MEROM +PENRYN +PENRYN_E +NEHALEM +WESTMERE +BONNELL +SALTWELL +SILVERMONT +VIA +AMD_K10 +AMD_BULLDOZER +AMD_PILEDRIVER +AMD_ZEN +AMD_ZENPLUS +AMD_ZEN2 +AMD_FUTURE +GOLDMONT +GOLDMONT_PLUS +TREMONT +SNOW_RIDGE +SANDYBRIDGE +IVYBRIDGE +HASWELL +BROADWELL +SKYLAKE +COMET_LAKE +SKYLAKE_SERVER +CASCADE_LAKE +COOPER_LAKE +KNL +KNM +CANNONLAKE +ICE_LAKE +ICE_LAKE_SERVER +TIGER_LAKE +ALDER_LAKE +SAPPHIRE_RAPIDS +FUTURE +ALL diff --git a/CodeVirtualizer/build/obj/xed-chip-features-table.c b/CodeVirtualizer/build/obj/xed-chip-features-table.c new file mode 100644 index 0000000..ab7aea4 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-chip-features-table.c @@ -0,0 +1,3561 @@ +/// @file xed-chip-features-table.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-isa-set-enum.h" +#include "xed-chip-enum.h" +xed_uint64_t xed_chip_features[XED_CHIP_LAST][5]; +xed_bool_t xed_chip_supports_avx512[XED_CHIP_LAST]; +void xed_init_chip_model_info(void) +{ + const xed_uint64_t one=1; + xed_chip_features[XED_CHIP_I86][0] = 0; + xed_chip_features[XED_CHIP_I86][1] = 0 + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I86][2] = 0; + xed_chip_features[XED_CHIP_I86][3] = 0; + xed_chip_features[XED_CHIP_I86][4] = 0; + xed_chip_features[XED_CHIP_I86FP][0] = 0; + xed_chip_features[XED_CHIP_I86FP][1] = 0 + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I86FP][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I86FP][3] = 0; + xed_chip_features[XED_CHIP_I86FP][4] = 0; + xed_chip_features[XED_CHIP_I186][0] = 0; + xed_chip_features[XED_CHIP_I186][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I186][2] = 0; + xed_chip_features[XED_CHIP_I186][3] = 0; + xed_chip_features[XED_CHIP_I186][4] = 0; + xed_chip_features[XED_CHIP_I186FP][0] = 0; + xed_chip_features[XED_CHIP_I186FP][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I186FP][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I186FP][3] = 0; + xed_chip_features[XED_CHIP_I186FP][4] = 0; + xed_chip_features[XED_CHIP_I286REAL][0] = 0; + xed_chip_features[XED_CHIP_I286REAL][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I286REAL][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I286REAL][3] = 0; + xed_chip_features[XED_CHIP_I286REAL][4] = 0; + xed_chip_features[XED_CHIP_I286][0] = 0; + xed_chip_features[XED_CHIP_I286][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I286][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I286][3] = 0; + xed_chip_features[XED_CHIP_I286][4] = 0; + xed_chip_features[XED_CHIP_I2186FP][0] = 0; + xed_chip_features[XED_CHIP_I2186FP][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I2186FP][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I2186FP][3] = 0; + xed_chip_features[XED_CHIP_I2186FP][4] = 0; + xed_chip_features[XED_CHIP_I386REAL][0] = 0; + xed_chip_features[XED_CHIP_I386REAL][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I386REAL][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I386REAL][3] = 0; + xed_chip_features[XED_CHIP_I386REAL][4] = 0; + xed_chip_features[XED_CHIP_I386][0] = 0; + xed_chip_features[XED_CHIP_I386][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I386][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I386][3] = 0; + xed_chip_features[XED_CHIP_I386][4] = 0; + xed_chip_features[XED_CHIP_I386FP][0] = 0; + xed_chip_features[XED_CHIP_I386FP][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I386FP][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I386FP][3] = 0; + xed_chip_features[XED_CHIP_I386FP][4] = 0; + xed_chip_features[XED_CHIP_I486REAL][0] = 0; + xed_chip_features[XED_CHIP_I486REAL][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I486REAL][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I486REAL][3] = 0; + xed_chip_features[XED_CHIP_I486REAL][4] = 0; + xed_chip_features[XED_CHIP_I486][0] = 0; + xed_chip_features[XED_CHIP_I486][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)); + xed_chip_features[XED_CHIP_I486][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_I486][3] = 0; + xed_chip_features[XED_CHIP_I486][4] = 0; + xed_chip_features[XED_CHIP_PENTIUMREAL][0] = 0; + xed_chip_features[XED_CHIP_PENTIUMREAL][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)); + xed_chip_features[XED_CHIP_PENTIUMREAL][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUMREAL][3] = 0; + xed_chip_features[XED_CHIP_PENTIUMREAL][4] = 0; + xed_chip_features[XED_CHIP_PENTIUM][0] = 0; + xed_chip_features[XED_CHIP_PENTIUM][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)); + xed_chip_features[XED_CHIP_PENTIUM][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUM][3] = 0; + xed_chip_features[XED_CHIP_PENTIUM][4] = 0; + xed_chip_features[XED_CHIP_QUARK][0] = 0; + xed_chip_features[XED_CHIP_QUARK][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)); + xed_chip_features[XED_CHIP_QUARK][2] = 0 + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_QUARK][3] = 0; + xed_chip_features[XED_CHIP_QUARK][4] = 0; + xed_chip_features[XED_CHIP_PENTIUMMMXREAL][0] = 0; + xed_chip_features[XED_CHIP_PENTIUMMMXREAL][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)); + xed_chip_features[XED_CHIP_PENTIUMMMXREAL][2] = 0 + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUMMMXREAL][3] = 0; + xed_chip_features[XED_CHIP_PENTIUMMMXREAL][4] = 0; + xed_chip_features[XED_CHIP_PENTIUMMMX][0] = 0; + xed_chip_features[XED_CHIP_PENTIUMMMX][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)); + xed_chip_features[XED_CHIP_PENTIUMMMX][2] = 0 + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUMMMX][3] = 0; + xed_chip_features[XED_CHIP_PENTIUMMMX][4] = 0; + xed_chip_features[XED_CHIP_ALLREAL][0] = 0; + xed_chip_features[XED_CHIP_ALLREAL][1] = 0 + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)); + xed_chip_features[XED_CHIP_ALLREAL][2] = 0 + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_ALLREAL][3] = 0; + xed_chip_features[XED_CHIP_ALLREAL][4] = 0; + xed_chip_features[XED_CHIP_PENTIUMPRO][0] = 0; + xed_chip_features[XED_CHIP_PENTIUMPRO][1] = 0 + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_PENTIUMPRO][2] = 0 + |(one<<(XED_ISA_SET_PPRO_UD0_SHORT-128)) + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUMPRO][3] = 0; + xed_chip_features[XED_CHIP_PENTIUMPRO][4] = 0; + xed_chip_features[XED_CHIP_PENTIUM2][0] = 0; + xed_chip_features[XED_CHIP_PENTIUM2][1] = 0 + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_FXSAVE-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_PENTIUM2][2] = 0 + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUM2][3] = 0; + xed_chip_features[XED_CHIP_PENTIUM2][4] = 0; + xed_chip_features[XED_CHIP_PENTIUM3][0] = 0; + xed_chip_features[XED_CHIP_PENTIUM3][1] = 0 + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_FXSAVE-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_PENTIUM3][2] = 0 + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_SSE-128)) + |(one<<(XED_ISA_SET_SSEMXCSR-128)) + |(one<<(XED_ISA_SET_SSE_PREFETCH-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUM3][3] = 0; + xed_chip_features[XED_CHIP_PENTIUM3][4] = 0; + xed_chip_features[XED_CHIP_PENTIUM4][0] = 0; + xed_chip_features[XED_CHIP_PENTIUM4][1] = 0 + |(one<<(XED_ISA_SET_CLFSH-64)) + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_FXSAVE-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_PAUSE-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_PENTIUM4][2] = 0 + |(one<<(XED_ISA_SET_PPRO_UD0_LONG-128)) + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_SSE-128)) + |(one<<(XED_ISA_SET_SSE2-128)) + |(one<<(XED_ISA_SET_SSE2MMX-128)) + |(one<<(XED_ISA_SET_SSEMXCSR-128)) + |(one<<(XED_ISA_SET_SSE_PREFETCH-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_PENTIUM4][3] = 0; + xed_chip_features[XED_CHIP_PENTIUM4][4] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT][0] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT][1] = 0 + |(one<<(XED_ISA_SET_CLFSH-64)) + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_CMPXCHG16B-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_FXSAVE-64)) + |(one<<(XED_ISA_SET_FXSAVE64-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_LONGMODE-64)) + |(one<<(XED_ISA_SET_MONITOR-64)) + |(one<<(XED_ISA_SET_PAUSE-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_P4PRESCOTT][2] = 0 + |(one<<(XED_ISA_SET_PPRO_UD0_LONG-128)) + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_SSE-128)) + |(one<<(XED_ISA_SET_SSE2-128)) + |(one<<(XED_ISA_SET_SSE2MMX-128)) + |(one<<(XED_ISA_SET_SSE3-128)) + |(one<<(XED_ISA_SET_SSE3X87-128)) + |(one<<(XED_ISA_SET_SSEMXCSR-128)) + |(one<<(XED_ISA_SET_SSE_PREFETCH-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_P4PRESCOTT][3] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT][4] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT_NOLAHF][0] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT_NOLAHF][1] = 0 + |(one<<(XED_ISA_SET_CLFSH-64)) + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_CMPXCHG16B-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_FXSAVE-64)) + |(one<<(XED_ISA_SET_FXSAVE64-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LONGMODE-64)) + |(one<<(XED_ISA_SET_MONITOR-64)) + |(one<<(XED_ISA_SET_PAUSE-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_P4PRESCOTT_NOLAHF][2] = 0 + |(one<<(XED_ISA_SET_PPRO_UD0_LONG-128)) + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_SSE-128)) + |(one<<(XED_ISA_SET_SSE2-128)) + |(one<<(XED_ISA_SET_SSE2MMX-128)) + |(one<<(XED_ISA_SET_SSE3-128)) + |(one<<(XED_ISA_SET_SSE3X87-128)) + |(one<<(XED_ISA_SET_SSEMXCSR-128)) + |(one<<(XED_ISA_SET_SSE_PREFETCH-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_P4PRESCOTT_NOLAHF][3] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT_NOLAHF][4] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT_VTX][0] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT_VTX][1] = 0 + |(one<<(XED_ISA_SET_CLFSH-64)) + |(one<<(XED_ISA_SET_CMOV-64)) + |(one<<(XED_ISA_SET_CMPXCHG16B-64)) + |(one<<(XED_ISA_SET_FAT_NOP-64)) + |(one<<(XED_ISA_SET_FCMOV-64)) + |(one<<(XED_ISA_SET_FXSAVE-64)) + |(one<<(XED_ISA_SET_FXSAVE64-64)) + |(one<<(XED_ISA_SET_I186-64)) + |(one<<(XED_ISA_SET_I286PROTECTED-64)) + |(one<<(XED_ISA_SET_I286REAL-64)) + |(one<<(XED_ISA_SET_I386-64)) + |(one<<(XED_ISA_SET_I486-64)) + |(one<<(XED_ISA_SET_I486REAL-64)) + |(one<<(XED_ISA_SET_I86-64)) + |(one<<(XED_ISA_SET_LAHF-64)) + |(one<<(XED_ISA_SET_LONGMODE-64)) + |(one<<(XED_ISA_SET_MONITOR-64)) + |(one<<(XED_ISA_SET_PAUSE-64)) + |(one<<(XED_ISA_SET_PENTIUMMMX-64)) + |(one<<(XED_ISA_SET_PENTIUMREAL-64)) + |(one<<(XED_ISA_SET_PPRO-64)); + xed_chip_features[XED_CHIP_P4PRESCOTT_VTX][2] = 0 + |(one<<(XED_ISA_SET_PPRO_UD0_LONG-128)) + |(one<<(XED_ISA_SET_PREFETCH_NOP-128)) + |(one<<(XED_ISA_SET_RDPMC-128)) + |(one<<(XED_ISA_SET_SSE-128)) + |(one<<(XED_ISA_SET_SSE2-128)) + |(one<<(XED_ISA_SET_SSE2MMX-128)) + |(one<<(XED_ISA_SET_SSE3-128)) + |(one<<(XED_ISA_SET_SSE3X87-128)) + |(one<<(XED_ISA_SET_SSEMXCSR-128)) + |(one<<(XED_ISA_SET_SSE_PREFETCH-128)) + |(one<<(XED_ISA_SET_VTX-128)) + |(one<<(XED_ISA_SET_X87-128)); + xed_chip_features[XED_CHIP_P4PRESCOTT_VTX][3] = 0; + xed_chip_features[XED_CHIP_P4PRESCOTT_VTX][4] = 0; + xed_chip_features[XED_CHIP_MEROM][0] = 0 + |(one< +#include +#include "xed-cpuid-bit-enum.h" + +typedef struct { + const char* name; + xed_cpuid_bit_enum_t value; +} name_table_xed_cpuid_bit_enum_t; +static const name_table_xed_cpuid_bit_enum_t name_array_xed_cpuid_bit_enum_t[] = { +{"INVALID", XED_CPUID_BIT_INVALID}, +{"ADOXADCX", XED_CPUID_BIT_ADOXADCX}, +{"AES", XED_CPUID_BIT_AES}, +{"AMX_BF16", XED_CPUID_BIT_AMX_BF16}, +{"AMX_INT8", XED_CPUID_BIT_AMX_INT8}, +{"AMX_TILES", XED_CPUID_BIT_AMX_TILES}, +{"AVX", XED_CPUID_BIT_AVX}, +{"AVX2", XED_CPUID_BIT_AVX2}, +{"AVX512BW", XED_CPUID_BIT_AVX512BW}, +{"AVX512CD", XED_CPUID_BIT_AVX512CD}, +{"AVX512DQ", XED_CPUID_BIT_AVX512DQ}, +{"AVX512ER", XED_CPUID_BIT_AVX512ER}, +{"AVX512F", XED_CPUID_BIT_AVX512F}, +{"AVX512IFMA", XED_CPUID_BIT_AVX512IFMA}, +{"AVX512PF", XED_CPUID_BIT_AVX512PF}, +{"AVX512VBMI", XED_CPUID_BIT_AVX512VBMI}, +{"AVX512VL", XED_CPUID_BIT_AVX512VL}, +{"AVX512_4FMAPS", XED_CPUID_BIT_AVX512_4FMAPS}, +{"AVX512_4VNNIW", XED_CPUID_BIT_AVX512_4VNNIW}, +{"AVX512_BITALG", XED_CPUID_BIT_AVX512_BITALG}, +{"AVX512_FP16", XED_CPUID_BIT_AVX512_FP16}, +{"AVX512_VBMI2", XED_CPUID_BIT_AVX512_VBMI2}, +{"AVX512_VNNI", XED_CPUID_BIT_AVX512_VNNI}, +{"AVX512_VP2INTERSECT", XED_CPUID_BIT_AVX512_VP2INTERSECT}, +{"AVX512_VPOPCNTDQ", XED_CPUID_BIT_AVX512_VPOPCNTDQ}, +{"AVX_VNNI", XED_CPUID_BIT_AVX_VNNI}, +{"BF16", XED_CPUID_BIT_BF16}, +{"BMI1", XED_CPUID_BIT_BMI1}, +{"BMI2", XED_CPUID_BIT_BMI2}, +{"CET", XED_CPUID_BIT_CET}, +{"CLDEMOTE", XED_CPUID_BIT_CLDEMOTE}, +{"CLFLUSH", XED_CPUID_BIT_CLFLUSH}, +{"CLFLUSHOPT", XED_CPUID_BIT_CLFLUSHOPT}, +{"CLWB", XED_CPUID_BIT_CLWB}, +{"CMPXCHG16B", XED_CPUID_BIT_CMPXCHG16B}, +{"ENQCMD", XED_CPUID_BIT_ENQCMD}, +{"F16C", XED_CPUID_BIT_F16C}, +{"FMA", XED_CPUID_BIT_FMA}, +{"FXSAVE", XED_CPUID_BIT_FXSAVE}, +{"GFNI", XED_CPUID_BIT_GFNI}, +{"HRESET", XED_CPUID_BIT_HRESET}, +{"INTEL64", XED_CPUID_BIT_INTEL64}, +{"INTELPT", XED_CPUID_BIT_INTELPT}, +{"INVPCID", XED_CPUID_BIT_INVPCID}, +{"KLENABLED", XED_CPUID_BIT_KLENABLED}, +{"KLSUPPORTED", XED_CPUID_BIT_KLSUPPORTED}, +{"KLWIDE", XED_CPUID_BIT_KLWIDE}, +{"LAHF", XED_CPUID_BIT_LAHF}, +{"LZCNT", XED_CPUID_BIT_LZCNT}, +{"MCOMMIT", XED_CPUID_BIT_MCOMMIT}, +{"MONITOR", XED_CPUID_BIT_MONITOR}, +{"MONITORX", XED_CPUID_BIT_MONITORX}, +{"MOVDIR64B", XED_CPUID_BIT_MOVDIR64B}, +{"MOVDIRI", XED_CPUID_BIT_MOVDIRI}, +{"MOVEBE", XED_CPUID_BIT_MOVEBE}, +{"MPX", XED_CPUID_BIT_MPX}, +{"OSPKU", XED_CPUID_BIT_OSPKU}, +{"OSXSAVE", XED_CPUID_BIT_OSXSAVE}, +{"PCLMULQDQ", XED_CPUID_BIT_PCLMULQDQ}, +{"PCONFIG", XED_CPUID_BIT_PCONFIG}, +{"PKU", XED_CPUID_BIT_PKU}, +{"POPCNT", XED_CPUID_BIT_POPCNT}, +{"PREFETCHW", XED_CPUID_BIT_PREFETCHW}, +{"PREFETCHWT1", XED_CPUID_BIT_PREFETCHWT1}, +{"PTWRITE", XED_CPUID_BIT_PTWRITE}, +{"RDP", XED_CPUID_BIT_RDP}, +{"RDPRU", XED_CPUID_BIT_RDPRU}, +{"RDRAND", XED_CPUID_BIT_RDRAND}, +{"RDSEED", XED_CPUID_BIT_RDSEED}, +{"RDTSCP", XED_CPUID_BIT_RDTSCP}, +{"RDWRFSGS", XED_CPUID_BIT_RDWRFSGS}, +{"RTM", XED_CPUID_BIT_RTM}, +{"SERIALIZE", XED_CPUID_BIT_SERIALIZE}, +{"SGX", XED_CPUID_BIT_SGX}, +{"SHA", XED_CPUID_BIT_SHA}, +{"SMAP", XED_CPUID_BIT_SMAP}, +{"SMX", XED_CPUID_BIT_SMX}, +{"SNP", XED_CPUID_BIT_SNP}, +{"SSE", XED_CPUID_BIT_SSE}, +{"SSE2", XED_CPUID_BIT_SSE2}, +{"SSE3", XED_CPUID_BIT_SSE3}, +{"SSE4", XED_CPUID_BIT_SSE4}, +{"SSE42", XED_CPUID_BIT_SSE42}, +{"SSE4A", XED_CPUID_BIT_SSE4A}, +{"SSSE3", XED_CPUID_BIT_SSSE3}, +{"TSX_LDTRK", XED_CPUID_BIT_TSX_LDTRK}, +{"UINTR", XED_CPUID_BIT_UINTR}, +{"VAES", XED_CPUID_BIT_VAES}, +{"VIA_PADLOCK_AES", XED_CPUID_BIT_VIA_PADLOCK_AES}, +{"VIA_PADLOCK_AES_EN", XED_CPUID_BIT_VIA_PADLOCK_AES_EN}, +{"VIA_PADLOCK_PMM", XED_CPUID_BIT_VIA_PADLOCK_PMM}, +{"VIA_PADLOCK_PMM_EN", XED_CPUID_BIT_VIA_PADLOCK_PMM_EN}, +{"VIA_PADLOCK_RNG", XED_CPUID_BIT_VIA_PADLOCK_RNG}, +{"VIA_PADLOCK_RNG_EN", XED_CPUID_BIT_VIA_PADLOCK_RNG_EN}, +{"VIA_PADLOCK_SHA", XED_CPUID_BIT_VIA_PADLOCK_SHA}, +{"VIA_PADLOCK_SHA_EN", XED_CPUID_BIT_VIA_PADLOCK_SHA_EN}, +{"VMX", XED_CPUID_BIT_VMX}, +{"VPCLMULQDQ", XED_CPUID_BIT_VPCLMULQDQ}, +{"WAITPKG", XED_CPUID_BIT_WAITPKG}, +{"WBNOINVD", XED_CPUID_BIT_WBNOINVD}, +{"XSAVE", XED_CPUID_BIT_XSAVE}, +{"XSAVEC", XED_CPUID_BIT_XSAVEC}, +{"XSAVEOPT", XED_CPUID_BIT_XSAVEOPT}, +{"XSAVES", XED_CPUID_BIT_XSAVES}, +{"LAST", XED_CPUID_BIT_LAST}, +{0, XED_CPUID_BIT_LAST}, +}; + + +xed_cpuid_bit_enum_t str2xed_cpuid_bit_enum_t(const char* s) +{ + const name_table_xed_cpuid_bit_enum_t* p = name_array_xed_cpuid_bit_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_CPUID_BIT_INVALID; +} + + +const char* xed_cpuid_bit_enum_t2str(const xed_cpuid_bit_enum_t p) +{ + xed_cpuid_bit_enum_t type_idx = p; + if ( p > XED_CPUID_BIT_LAST) type_idx = XED_CPUID_BIT_LAST; + return name_array_xed_cpuid_bit_enum_t[type_idx].name; +} + +xed_cpuid_bit_enum_t xed_cpuid_bit_enum_t_last(void) { + return XED_CPUID_BIT_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_CPUID_BIT_INVALID: + case XED_CPUID_BIT_ADOXADCX: + case XED_CPUID_BIT_AES: + case XED_CPUID_BIT_AMX_BF16: + case XED_CPUID_BIT_AMX_INT8: + case XED_CPUID_BIT_AMX_TILES: + case XED_CPUID_BIT_AVX: + case XED_CPUID_BIT_AVX2: + case XED_CPUID_BIT_AVX512BW: + case XED_CPUID_BIT_AVX512CD: + case XED_CPUID_BIT_AVX512DQ: + case XED_CPUID_BIT_AVX512ER: + case XED_CPUID_BIT_AVX512F: + case XED_CPUID_BIT_AVX512IFMA: + case XED_CPUID_BIT_AVX512PF: + case XED_CPUID_BIT_AVX512VBMI: + case XED_CPUID_BIT_AVX512VL: + case XED_CPUID_BIT_AVX512_4FMAPS: + case XED_CPUID_BIT_AVX512_4VNNIW: + case XED_CPUID_BIT_AVX512_BITALG: + case XED_CPUID_BIT_AVX512_FP16: + case XED_CPUID_BIT_AVX512_VBMI2: + case XED_CPUID_BIT_AVX512_VNNI: + case XED_CPUID_BIT_AVX512_VP2INTERSECT: + case XED_CPUID_BIT_AVX512_VPOPCNTDQ: + case XED_CPUID_BIT_AVX_VNNI: + case XED_CPUID_BIT_BF16: + case XED_CPUID_BIT_BMI1: + case XED_CPUID_BIT_BMI2: + case XED_CPUID_BIT_CET: + case XED_CPUID_BIT_CLDEMOTE: + case XED_CPUID_BIT_CLFLUSH: + case XED_CPUID_BIT_CLFLUSHOPT: + case XED_CPUID_BIT_CLWB: + case XED_CPUID_BIT_CMPXCHG16B: + case XED_CPUID_BIT_ENQCMD: + case XED_CPUID_BIT_F16C: + case XED_CPUID_BIT_FMA: + case XED_CPUID_BIT_FXSAVE: + case XED_CPUID_BIT_GFNI: + case XED_CPUID_BIT_HRESET: + case XED_CPUID_BIT_INTEL64: + case XED_CPUID_BIT_INTELPT: + case XED_CPUID_BIT_INVPCID: + case XED_CPUID_BIT_KLENABLED: + case XED_CPUID_BIT_KLSUPPORTED: + case XED_CPUID_BIT_KLWIDE: + case XED_CPUID_BIT_LAHF: + case XED_CPUID_BIT_LZCNT: + case XED_CPUID_BIT_MCOMMIT: + case XED_CPUID_BIT_MONITOR: + case XED_CPUID_BIT_MONITORX: + case XED_CPUID_BIT_MOVDIR64B: + case XED_CPUID_BIT_MOVDIRI: + case XED_CPUID_BIT_MOVEBE: + case XED_CPUID_BIT_MPX: + case XED_CPUID_BIT_OSPKU: + case XED_CPUID_BIT_OSXSAVE: + case XED_CPUID_BIT_PCLMULQDQ: + case XED_CPUID_BIT_PCONFIG: + case XED_CPUID_BIT_PKU: + case XED_CPUID_BIT_POPCNT: + case XED_CPUID_BIT_PREFETCHW: + case XED_CPUID_BIT_PREFETCHWT1: + case XED_CPUID_BIT_PTWRITE: + case XED_CPUID_BIT_RDP: + case XED_CPUID_BIT_RDPRU: + case XED_CPUID_BIT_RDRAND: + case XED_CPUID_BIT_RDSEED: + case XED_CPUID_BIT_RDTSCP: + case XED_CPUID_BIT_RDWRFSGS: + case XED_CPUID_BIT_RTM: + case XED_CPUID_BIT_SERIALIZE: + case XED_CPUID_BIT_SGX: + case XED_CPUID_BIT_SHA: + case XED_CPUID_BIT_SMAP: + case XED_CPUID_BIT_SMX: + case XED_CPUID_BIT_SNP: + case XED_CPUID_BIT_SSE: + case XED_CPUID_BIT_SSE2: + case XED_CPUID_BIT_SSE3: + case XED_CPUID_BIT_SSE4: + case XED_CPUID_BIT_SSE42: + case XED_CPUID_BIT_SSE4A: + case XED_CPUID_BIT_SSSE3: + case XED_CPUID_BIT_TSX_LDTRK: + case XED_CPUID_BIT_UINTR: + case XED_CPUID_BIT_VAES: + case XED_CPUID_BIT_VIA_PADLOCK_AES: + case XED_CPUID_BIT_VIA_PADLOCK_AES_EN: + case XED_CPUID_BIT_VIA_PADLOCK_PMM: + case XED_CPUID_BIT_VIA_PADLOCK_PMM_EN: + case XED_CPUID_BIT_VIA_PADLOCK_RNG: + case XED_CPUID_BIT_VIA_PADLOCK_RNG_EN: + case XED_CPUID_BIT_VIA_PADLOCK_SHA: + case XED_CPUID_BIT_VIA_PADLOCK_SHA_EN: + case XED_CPUID_BIT_VMX: + case XED_CPUID_BIT_VPCLMULQDQ: + case XED_CPUID_BIT_WAITPKG: + case XED_CPUID_BIT_WBNOINVD: + case XED_CPUID_BIT_XSAVE: + case XED_CPUID_BIT_XSAVEC: + case XED_CPUID_BIT_XSAVEOPT: + case XED_CPUID_BIT_XSAVES: + case XED_CPUID_BIT_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-cpuid-bit-enum.h b/CodeVirtualizer/build/obj/xed-cpuid-bit-enum.h new file mode 100644 index 0000000..3c0f01c --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-cpuid-bit-enum.h @@ -0,0 +1,237 @@ +/// @file xed-cpuid-bit-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_CPUID_BIT_ENUM_H) +# define XED_CPUID_BIT_ENUM_H +#include "xed-common-hdrs.h" +#define XED_CPUID_BIT_INVALID_DEFINED 1 +#define XED_CPUID_BIT_ADOXADCX_DEFINED 1 +#define XED_CPUID_BIT_AES_DEFINED 1 +#define XED_CPUID_BIT_AMX_BF16_DEFINED 1 +#define XED_CPUID_BIT_AMX_INT8_DEFINED 1 +#define XED_CPUID_BIT_AMX_TILES_DEFINED 1 +#define XED_CPUID_BIT_AVX_DEFINED 1 +#define XED_CPUID_BIT_AVX2_DEFINED 1 +#define XED_CPUID_BIT_AVX512BW_DEFINED 1 +#define XED_CPUID_BIT_AVX512CD_DEFINED 1 +#define XED_CPUID_BIT_AVX512DQ_DEFINED 1 +#define XED_CPUID_BIT_AVX512ER_DEFINED 1 +#define XED_CPUID_BIT_AVX512F_DEFINED 1 +#define XED_CPUID_BIT_AVX512IFMA_DEFINED 1 +#define XED_CPUID_BIT_AVX512PF_DEFINED 1 +#define XED_CPUID_BIT_AVX512VBMI_DEFINED 1 +#define XED_CPUID_BIT_AVX512VL_DEFINED 1 +#define XED_CPUID_BIT_AVX512_4FMAPS_DEFINED 1 +#define XED_CPUID_BIT_AVX512_4VNNIW_DEFINED 1 +#define XED_CPUID_BIT_AVX512_BITALG_DEFINED 1 +#define XED_CPUID_BIT_AVX512_FP16_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VBMI2_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VNNI_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VP2INTERSECT_DEFINED 1 +#define XED_CPUID_BIT_AVX512_VPOPCNTDQ_DEFINED 1 +#define XED_CPUID_BIT_AVX_VNNI_DEFINED 1 +#define XED_CPUID_BIT_BF16_DEFINED 1 +#define XED_CPUID_BIT_BMI1_DEFINED 1 +#define XED_CPUID_BIT_BMI2_DEFINED 1 +#define XED_CPUID_BIT_CET_DEFINED 1 +#define XED_CPUID_BIT_CLDEMOTE_DEFINED 1 +#define XED_CPUID_BIT_CLFLUSH_DEFINED 1 +#define XED_CPUID_BIT_CLFLUSHOPT_DEFINED 1 +#define XED_CPUID_BIT_CLWB_DEFINED 1 +#define XED_CPUID_BIT_CMPXCHG16B_DEFINED 1 +#define XED_CPUID_BIT_ENQCMD_DEFINED 1 +#define XED_CPUID_BIT_F16C_DEFINED 1 +#define XED_CPUID_BIT_FMA_DEFINED 1 +#define XED_CPUID_BIT_FXSAVE_DEFINED 1 +#define XED_CPUID_BIT_GFNI_DEFINED 1 +#define XED_CPUID_BIT_HRESET_DEFINED 1 +#define XED_CPUID_BIT_INTEL64_DEFINED 1 +#define XED_CPUID_BIT_INTELPT_DEFINED 1 +#define XED_CPUID_BIT_INVPCID_DEFINED 1 +#define XED_CPUID_BIT_KLENABLED_DEFINED 1 +#define XED_CPUID_BIT_KLSUPPORTED_DEFINED 1 +#define XED_CPUID_BIT_KLWIDE_DEFINED 1 +#define XED_CPUID_BIT_LAHF_DEFINED 1 +#define XED_CPUID_BIT_LZCNT_DEFINED 1 +#define XED_CPUID_BIT_MCOMMIT_DEFINED 1 +#define XED_CPUID_BIT_MONITOR_DEFINED 1 +#define XED_CPUID_BIT_MONITORX_DEFINED 1 +#define XED_CPUID_BIT_MOVDIR64B_DEFINED 1 +#define XED_CPUID_BIT_MOVDIRI_DEFINED 1 +#define XED_CPUID_BIT_MOVEBE_DEFINED 1 +#define XED_CPUID_BIT_MPX_DEFINED 1 +#define XED_CPUID_BIT_OSPKU_DEFINED 1 +#define XED_CPUID_BIT_OSXSAVE_DEFINED 1 +#define XED_CPUID_BIT_PCLMULQDQ_DEFINED 1 +#define XED_CPUID_BIT_PCONFIG_DEFINED 1 +#define XED_CPUID_BIT_PKU_DEFINED 1 +#define XED_CPUID_BIT_POPCNT_DEFINED 1 +#define XED_CPUID_BIT_PREFETCHW_DEFINED 1 +#define XED_CPUID_BIT_PREFETCHWT1_DEFINED 1 +#define XED_CPUID_BIT_PTWRITE_DEFINED 1 +#define XED_CPUID_BIT_RDP_DEFINED 1 +#define XED_CPUID_BIT_RDPRU_DEFINED 1 +#define XED_CPUID_BIT_RDRAND_DEFINED 1 +#define XED_CPUID_BIT_RDSEED_DEFINED 1 +#define XED_CPUID_BIT_RDTSCP_DEFINED 1 +#define XED_CPUID_BIT_RDWRFSGS_DEFINED 1 +#define XED_CPUID_BIT_RTM_DEFINED 1 +#define XED_CPUID_BIT_SERIALIZE_DEFINED 1 +#define XED_CPUID_BIT_SGX_DEFINED 1 +#define XED_CPUID_BIT_SHA_DEFINED 1 +#define XED_CPUID_BIT_SMAP_DEFINED 1 +#define XED_CPUID_BIT_SMX_DEFINED 1 +#define XED_CPUID_BIT_SNP_DEFINED 1 +#define XED_CPUID_BIT_SSE_DEFINED 1 +#define XED_CPUID_BIT_SSE2_DEFINED 1 +#define XED_CPUID_BIT_SSE3_DEFINED 1 +#define XED_CPUID_BIT_SSE4_DEFINED 1 +#define XED_CPUID_BIT_SSE42_DEFINED 1 +#define XED_CPUID_BIT_SSE4A_DEFINED 1 +#define XED_CPUID_BIT_SSSE3_DEFINED 1 +#define XED_CPUID_BIT_TSX_LDTRK_DEFINED 1 +#define XED_CPUID_BIT_UINTR_DEFINED 1 +#define XED_CPUID_BIT_VAES_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_AES_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_AES_EN_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_PMM_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_PMM_EN_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_RNG_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_RNG_EN_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_SHA_DEFINED 1 +#define XED_CPUID_BIT_VIA_PADLOCK_SHA_EN_DEFINED 1 +#define XED_CPUID_BIT_VMX_DEFINED 1 +#define XED_CPUID_BIT_VPCLMULQDQ_DEFINED 1 +#define XED_CPUID_BIT_WAITPKG_DEFINED 1 +#define XED_CPUID_BIT_WBNOINVD_DEFINED 1 +#define XED_CPUID_BIT_XSAVE_DEFINED 1 +#define XED_CPUID_BIT_XSAVEC_DEFINED 1 +#define XED_CPUID_BIT_XSAVEOPT_DEFINED 1 +#define XED_CPUID_BIT_XSAVES_DEFINED 1 +#define XED_CPUID_BIT_LAST_DEFINED 1 +typedef enum { + XED_CPUID_BIT_INVALID, + XED_CPUID_BIT_ADOXADCX, + XED_CPUID_BIT_AES, + XED_CPUID_BIT_AMX_BF16, + XED_CPUID_BIT_AMX_INT8, + XED_CPUID_BIT_AMX_TILES, + XED_CPUID_BIT_AVX, + XED_CPUID_BIT_AVX2, + XED_CPUID_BIT_AVX512BW, + XED_CPUID_BIT_AVX512CD, + XED_CPUID_BIT_AVX512DQ, + XED_CPUID_BIT_AVX512ER, + XED_CPUID_BIT_AVX512F, + XED_CPUID_BIT_AVX512IFMA, + XED_CPUID_BIT_AVX512PF, + XED_CPUID_BIT_AVX512VBMI, + XED_CPUID_BIT_AVX512VL, + XED_CPUID_BIT_AVX512_4FMAPS, + XED_CPUID_BIT_AVX512_4VNNIW, + XED_CPUID_BIT_AVX512_BITALG, + XED_CPUID_BIT_AVX512_FP16, + XED_CPUID_BIT_AVX512_VBMI2, + XED_CPUID_BIT_AVX512_VNNI, + XED_CPUID_BIT_AVX512_VP2INTERSECT, + XED_CPUID_BIT_AVX512_VPOPCNTDQ, + XED_CPUID_BIT_AVX_VNNI, + XED_CPUID_BIT_BF16, + XED_CPUID_BIT_BMI1, + XED_CPUID_BIT_BMI2, + XED_CPUID_BIT_CET, + XED_CPUID_BIT_CLDEMOTE, + XED_CPUID_BIT_CLFLUSH, + XED_CPUID_BIT_CLFLUSHOPT, + XED_CPUID_BIT_CLWB, + XED_CPUID_BIT_CMPXCHG16B, + XED_CPUID_BIT_ENQCMD, + XED_CPUID_BIT_F16C, + XED_CPUID_BIT_FMA, + XED_CPUID_BIT_FXSAVE, + XED_CPUID_BIT_GFNI, + XED_CPUID_BIT_HRESET, + XED_CPUID_BIT_INTEL64, + XED_CPUID_BIT_INTELPT, + XED_CPUID_BIT_INVPCID, + XED_CPUID_BIT_KLENABLED, + XED_CPUID_BIT_KLSUPPORTED, + XED_CPUID_BIT_KLWIDE, + XED_CPUID_BIT_LAHF, + XED_CPUID_BIT_LZCNT, + XED_CPUID_BIT_MCOMMIT, + XED_CPUID_BIT_MONITOR, + XED_CPUID_BIT_MONITORX, + XED_CPUID_BIT_MOVDIR64B, + XED_CPUID_BIT_MOVDIRI, + XED_CPUID_BIT_MOVEBE, + XED_CPUID_BIT_MPX, + XED_CPUID_BIT_OSPKU, + XED_CPUID_BIT_OSXSAVE, + XED_CPUID_BIT_PCLMULQDQ, + XED_CPUID_BIT_PCONFIG, + XED_CPUID_BIT_PKU, + XED_CPUID_BIT_POPCNT, + XED_CPUID_BIT_PREFETCHW, + XED_CPUID_BIT_PREFETCHWT1, + XED_CPUID_BIT_PTWRITE, + XED_CPUID_BIT_RDP, + XED_CPUID_BIT_RDPRU, + XED_CPUID_BIT_RDRAND, + XED_CPUID_BIT_RDSEED, + XED_CPUID_BIT_RDTSCP, + XED_CPUID_BIT_RDWRFSGS, + XED_CPUID_BIT_RTM, + XED_CPUID_BIT_SERIALIZE, + XED_CPUID_BIT_SGX, + XED_CPUID_BIT_SHA, + XED_CPUID_BIT_SMAP, + XED_CPUID_BIT_SMX, + XED_CPUID_BIT_SNP, + XED_CPUID_BIT_SSE, + XED_CPUID_BIT_SSE2, + XED_CPUID_BIT_SSE3, + XED_CPUID_BIT_SSE4, + XED_CPUID_BIT_SSE42, + XED_CPUID_BIT_SSE4A, + XED_CPUID_BIT_SSSE3, + XED_CPUID_BIT_TSX_LDTRK, + XED_CPUID_BIT_UINTR, + XED_CPUID_BIT_VAES, + XED_CPUID_BIT_VIA_PADLOCK_AES, + XED_CPUID_BIT_VIA_PADLOCK_AES_EN, + XED_CPUID_BIT_VIA_PADLOCK_PMM, + XED_CPUID_BIT_VIA_PADLOCK_PMM_EN, + XED_CPUID_BIT_VIA_PADLOCK_RNG, + XED_CPUID_BIT_VIA_PADLOCK_RNG_EN, + XED_CPUID_BIT_VIA_PADLOCK_SHA, + XED_CPUID_BIT_VIA_PADLOCK_SHA_EN, + XED_CPUID_BIT_VMX, + XED_CPUID_BIT_VPCLMULQDQ, + XED_CPUID_BIT_WAITPKG, + XED_CPUID_BIT_WBNOINVD, + XED_CPUID_BIT_XSAVE, + XED_CPUID_BIT_XSAVEC, + XED_CPUID_BIT_XSAVEOPT, + XED_CPUID_BIT_XSAVES, + XED_CPUID_BIT_LAST +} xed_cpuid_bit_enum_t; + +/// This converts strings to #xed_cpuid_bit_enum_t types. +/// @param s A C-string. +/// @return #xed_cpuid_bit_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_cpuid_bit_enum_t str2xed_cpuid_bit_enum_t(const char* s); +/// This converts strings to #xed_cpuid_bit_enum_t types. +/// @param p An enumeration element of type xed_cpuid_bit_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_cpuid_bit_enum_t2str(const xed_cpuid_bit_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_cpuid_bit_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_cpuid_bit_enum_t xed_cpuid_bit_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-cpuid-bit-enum.txt b/CodeVirtualizer/build/obj/xed-cpuid-bit-enum.txt new file mode 100644 index 0000000..c87531c --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-cpuid-bit-enum.txt @@ -0,0 +1,134 @@ +# @file xed-cpuid-bit-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-cpuid-bit-enum.c +hfn xed-cpuid-bit-enum.h +typename xed_cpuid_bit_enum_t +prefix XED_CPUID_BIT_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +ADOXADCX +AES +AMX_BF16 +AMX_INT8 +AMX_TILES +AVX +AVX2 +AVX512BW +AVX512CD +AVX512DQ +AVX512ER +AVX512F +AVX512IFMA +AVX512PF +AVX512VBMI +AVX512VL +AVX512_4FMAPS +AVX512_4VNNIW +AVX512_BITALG +AVX512_FP16 +AVX512_VBMI2 +AVX512_VNNI +AVX512_VP2INTERSECT +AVX512_VPOPCNTDQ +AVX_VNNI +BF16 +BMI1 +BMI2 +CET +CLDEMOTE +CLFLUSH +CLFLUSHOPT +CLWB +CMPXCHG16B +ENQCMD +F16C +FMA +FXSAVE +GFNI +HRESET +INTEL64 +INTELPT +INVPCID +KLENABLED +KLSUPPORTED +KLWIDE +LAHF +LZCNT +MCOMMIT +MONITOR +MONITORX +MOVDIR64B +MOVDIRI +MOVEBE +MPX +OSPKU +OSXSAVE +PCLMULQDQ +PCONFIG +PKU +POPCNT +PREFETCHW +PREFETCHWT1 +PTWRITE +RDP +RDPRU +RDRAND +RDSEED +RDTSCP +RDWRFSGS +RTM +SERIALIZE +SGX +SHA +SMAP +SMX +SNP +SSE +SSE2 +SSE3 +SSE4 +SSE42 +SSE4A +SSSE3 +TSX_LDTRK +UINTR +VAES +VIA_PADLOCK_AES +VIA_PADLOCK_AES_EN +VIA_PADLOCK_PMM +VIA_PADLOCK_PMM_EN +VIA_PADLOCK_RNG +VIA_PADLOCK_RNG_EN +VIA_PADLOCK_SHA +VIA_PADLOCK_SHA_EN +VMX +VPCLMULQDQ +WAITPKG +WBNOINVD +XSAVE +XSAVEC +XSAVEOPT +XSAVES diff --git a/CodeVirtualizer/build/obj/xed-cpuid-tables.c b/CodeVirtualizer/build/obj/xed-cpuid-tables.c new file mode 100644 index 0000000..68f6f13 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-cpuid-tables.c @@ -0,0 +1,313 @@ +/// @file xed-cpuid-tables.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +const xed_cpuid_rec_t xed_cpuid_info[] = { +/* INVALID */ { 0x0, 0, 0, XED_REG_INVALID }, +/* ADOXADCX */ { 0x7, 0, 19, XED_REG_EBX }, +/* AES */ { 0x1, 0, 25, XED_REG_ECX }, +/* AMX_BF16 */ { 0x7, 0, 22, XED_REG_EDX }, +/* AMX_INT8 */ { 0x7, 0, 25, XED_REG_EDX }, +/* AMX_TILES */ { 0x7, 0, 24, XED_REG_EDX }, +/* AVX */ { 0x1, 0, 28, XED_REG_ECX }, +/* AVX2 */ { 0x7, 0, 5, XED_REG_EBX }, +/* AVX512BW */ { 0x7, 0, 30, XED_REG_EBX }, +/* AVX512CD */ { 0x7, 0, 28, XED_REG_EBX }, +/* AVX512DQ */ { 0x7, 0, 17, XED_REG_EBX }, +/* AVX512ER */ { 0x7, 0, 27, XED_REG_EBX }, +/* AVX512F */ { 0x7, 0, 16, XED_REG_EBX }, +/* AVX512IFMA */ { 0x7, 0, 21, XED_REG_EBX }, +/* AVX512PF */ { 0x7, 0, 26, XED_REG_EBX }, +/* AVX512VBMI */ { 0x7, 0, 1, XED_REG_ECX }, +/* AVX512VL */ { 0x7, 0, 31, XED_REG_EBX }, +/* AVX512_4FMAPS */ { 0x7, 0, 3, XED_REG_EDX }, +/* AVX512_4VNNIW */ { 0x7, 0, 2, XED_REG_EDX }, +/* AVX512_BITALG */ { 0x7, 0, 12, XED_REG_ECX }, +/* AVX512_FP16 */ { 0x7, 0, 23, XED_REG_EDX }, +/* AVX512_VBMI2 */ { 0x7, 0, 6, XED_REG_ECX }, +/* AVX512_VNNI */ { 0x7, 0, 11, XED_REG_ECX }, +/* AVX512_VP2INTERSECT */ { 0x7, 0, 8, XED_REG_EDX }, +/* AVX512_VPOPCNTDQ */ { 0x7, 0, 14, XED_REG_ECX }, +/* AVX_VNNI */ { 0x7, 1, 4, XED_REG_EAX }, +/* BF16 */ { 0x7, 1, 5, XED_REG_EAX }, +/* BMI1 */ { 0x7, 0, 3, XED_REG_EBX }, +/* BMI2 */ { 0x7, 0, 8, XED_REG_EBX }, +/* CET */ { 0x7, 0, 7, XED_REG_ECX }, +/* CLDEMOTE */ { 0x7, 0, 25, XED_REG_ECX }, +/* CLFLUSH */ { 0x1, 0, 19, XED_REG_EDX }, +/* CLFLUSHOPT */ { 0x7, 0, 23, XED_REG_EBX }, +/* CLWB */ { 0x7, 0, 24, XED_REG_EBX }, +/* CMPXCHG16B */ { 0x1, 0, 13, XED_REG_ECX }, +/* ENQCMD */ { 0x7, 0, 29, XED_REG_ECX }, +/* F16C */ { 0x1, 0, 29, XED_REG_ECX }, +/* FMA */ { 0x1, 0, 12, XED_REG_ECX }, +/* FXSAVE */ { 0x1, 0, 24, XED_REG_EDX }, +/* GFNI */ { 0x7, 0, 8, XED_REG_ECX }, +/* HRESET */ { 0x7, 1, 22, XED_REG_EAX }, +/* INTEL64 */ { 0x80000001, 0, 29, XED_REG_EDX }, +/* INTELPT */ { 0x7, 0, 25, XED_REG_EBX }, +/* INVPCID */ { 0x7, 0, 10, XED_REG_EBX }, +/* KLENABLED */ { 0x19, 0, 0, XED_REG_EBX }, +/* KLSUPPORTED */ { 0x7, 0, 23, XED_REG_ECX }, +/* KLWIDE */ { 0x19, 0, 2, XED_REG_EBX }, +/* LAHF */ { 0x80000001, 0, 0, XED_REG_ECX }, +/* LZCNT */ { 0x80000001, 0, 5, XED_REG_ECX }, +/* MCOMMIT */ { 0x80000008, 0, 8, XED_REG_EBX }, +/* MONITOR */ { 0x1, 0, 3, XED_REG_ECX }, +/* MONITORX */ { 0x80000001, 0, 29, XED_REG_ECX }, +/* MOVDIR64B */ { 0x7, 0, 28, XED_REG_ECX }, +/* MOVDIRI */ { 0x7, 0, 27, XED_REG_ECX }, +/* MOVEBE */ { 0x1, 0, 22, XED_REG_ECX }, +/* MPX */ { 0x7, 0, 14, XED_REG_EBX }, +/* OSPKU */ { 0x7, 0, 4, XED_REG_ECX }, +/* OSXSAVE */ { 0x1, 0, 27, XED_REG_ECX }, +/* PCLMULQDQ */ { 0x1, 0, 1, XED_REG_ECX }, +/* PCONFIG */ { 0x7, 0, 18, XED_REG_EDX }, +/* PKU */ { 0x7, 0, 3, XED_REG_ECX }, +/* POPCNT */ { 0x1, 0, 23, XED_REG_ECX }, +/* PREFETCHW */ { 0x80000001, 0, 8, XED_REG_ECX }, +/* PREFETCHWT1 */ { 0x7, 0, 0, XED_REG_ECX }, +/* PTWRITE */ { 0x14, 0, 4, XED_REG_EBX }, +/* RDP */ { 0x7, 0, 22, XED_REG_ECX }, +/* RDPRU */ { 0x80000008, 0, 4, XED_REG_EBX }, +/* RDRAND */ { 0x1, 0, 30, XED_REG_ECX }, +/* RDSEED */ { 0x7, 0, 18, XED_REG_EBX }, +/* RDTSCP */ { 0x80000001, 0, 27, XED_REG_EDX }, +/* RDWRFSGS */ { 0x7, 0, 0, XED_REG_EBX }, +/* RTM */ { 0x7, 0, 11, XED_REG_EBX }, +/* SERIALIZE */ { 0x7, 0, 14, XED_REG_EDX }, +/* SGX */ { 0x7, 0, 2, XED_REG_EBX }, +/* SHA */ { 0x7, 0, 29, XED_REG_EBX }, +/* SMAP */ { 0x7, 0, 20, XED_REG_EBX }, +/* SMX */ { 0x1, 0, 6, XED_REG_ECX }, +/* SNP */ { 0x8000001F, 0, 4, XED_REG_EAX }, +/* SSE */ { 0x1, 0, 25, XED_REG_EDX }, +/* SSE2 */ { 0x1, 0, 26, XED_REG_EDX }, +/* SSE3 */ { 0x1, 0, 0, XED_REG_ECX }, +/* SSE4 */ { 0x1, 0, 19, XED_REG_ECX }, +/* SSE42 */ { 0x1, 0, 20, XED_REG_ECX }, +/* SSE4A */ { 0x80000001, 0, 6, XED_REG_ECX }, +/* SSSE3 */ { 0x1, 0, 9, XED_REG_ECX }, +/* TSX_LDTRK */ { 0x7, 0, 16, XED_REG_EDX }, +/* UINTR */ { 0x7, 0, 5, XED_REG_EDX }, +/* VAES */ { 0x7, 0, 9, XED_REG_ECX }, +/* VIA_PADLOCK_AES */ { 0xC0000001, 0, 6, XED_REG_EDX }, +/* VIA_PADLOCK_AES_EN */ { 0xC0000001, 0, 7, XED_REG_EDX }, +/* VIA_PADLOCK_PMM */ { 0xC0000001, 0, 12, XED_REG_EDX }, +/* VIA_PADLOCK_PMM_EN */ { 0xC0000001, 0, 13, XED_REG_EDX }, +/* VIA_PADLOCK_RNG */ { 0xC0000001, 0, 2, XED_REG_EDX }, +/* VIA_PADLOCK_RNG_EN */ { 0xC0000001, 0, 3, XED_REG_EDX }, +/* VIA_PADLOCK_SHA */ { 0xC0000001, 0, 10, XED_REG_EDX }, +/* VIA_PADLOCK_SHA_EN */ { 0xC0000001, 0, 11, XED_REG_EDX }, +/* VMX */ { 0x1, 0, 5, XED_REG_ECX }, +/* VPCLMULQDQ */ { 0x7, 0, 10, XED_REG_ECX }, +/* WAITPKG */ { 0x7, 0, 5, XED_REG_ECX }, +/* WBNOINVD */ { 0x80000008, 0, 9, XED_REG_EBX }, +/* XSAVE */ { 0x1, 0, 26, XED_REG_ECX }, +/* XSAVEC */ { 0xD, 1, 1, XED_REG_EAX }, +/* XSAVEOPT */ { 0xD, 1, 0, XED_REG_EAX }, +/* XSAVES */ { 0xD, 1, 3, XED_REG_EAX }, +}; +const xed_cpuid_bit_enum_t xed_isa_set_to_cpuid_mapping[][XED_MAX_CPUID_BITS_PER_ISA_SET] = { +/* INVALID */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* 3DNOW */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* 3DNOW_PREFETCH */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* ADOX_ADCX */ { XED_CPUID_BIT_ADOXADCX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AES */ { XED_CPUID_BIT_AES, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AMD */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AMD_INVLPGB */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AMX_BF16 */ { XED_CPUID_BIT_AMX_TILES, XED_CPUID_BIT_AMX_BF16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AMX_INT8 */ { XED_CPUID_BIT_AMX_TILES, XED_CPUID_BIT_AMX_INT8, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AMX_TILE */ { XED_CPUID_BIT_AMX_TILES, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX */ { XED_CPUID_BIT_AVX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX2 */ { XED_CPUID_BIT_AVX2, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX2GATHER */ { XED_CPUID_BIT_AVX2, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512BW_128 */ { XED_CPUID_BIT_AVX512BW, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512BW_128N */ { XED_CPUID_BIT_AVX512BW, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512BW_256 */ { XED_CPUID_BIT_AVX512BW, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512BW_512 */ { XED_CPUID_BIT_AVX512BW, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512BW_KOP */ { XED_CPUID_BIT_AVX512BW, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512CD_128 */ { XED_CPUID_BIT_AVX512CD, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512CD_256 */ { XED_CPUID_BIT_AVX512CD, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512CD_512 */ { XED_CPUID_BIT_AVX512CD, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512DQ_128 */ { XED_CPUID_BIT_AVX512DQ, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512DQ_128N */ { XED_CPUID_BIT_AVX512DQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512DQ_256 */ { XED_CPUID_BIT_AVX512DQ, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512DQ_512 */ { XED_CPUID_BIT_AVX512DQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512DQ_KOP */ { XED_CPUID_BIT_AVX512DQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512DQ_SCALAR */ { XED_CPUID_BIT_AVX512DQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512ER_512 */ { XED_CPUID_BIT_AVX512ER, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512ER_SCALAR */ { XED_CPUID_BIT_AVX512ER, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512F_128 */ { XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512F_128N */ { XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512F_256 */ { XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512F_512 */ { XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512F_KOP */ { XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512F_SCALAR */ { XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512PF_512 */ { XED_CPUID_BIT_AVX512PF, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_4FMAPS_512 */ { XED_CPUID_BIT_AVX512_4FMAPS, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_4FMAPS_SCALAR */ { XED_CPUID_BIT_AVX512_4FMAPS, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_4VNNIW_512 */ { XED_CPUID_BIT_AVX512_4VNNIW, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_BF16_128 */ { XED_CPUID_BIT_BF16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_BF16_256 */ { XED_CPUID_BIT_BF16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_BF16_512 */ { XED_CPUID_BIT_BF16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_BITALG_128 */ { XED_CPUID_BIT_AVX512_BITALG, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_BITALG_256 */ { XED_CPUID_BIT_AVX512_BITALG, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_BITALG_512 */ { XED_CPUID_BIT_AVX512_BITALG, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_FP16_128 */ { XED_CPUID_BIT_AVX512_FP16, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_FP16_128N */ { XED_CPUID_BIT_AVX512_FP16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_FP16_256 */ { XED_CPUID_BIT_AVX512_FP16, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_FP16_512 */ { XED_CPUID_BIT_AVX512_FP16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_FP16_SCALAR */ { XED_CPUID_BIT_AVX512_FP16, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_GFNI_128 */ { XED_CPUID_BIT_GFNI, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID } , +/* AVX512_GFNI_256 */ { XED_CPUID_BIT_GFNI, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID } , +/* AVX512_GFNI_512 */ { XED_CPUID_BIT_GFNI, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_IFMA_128 */ { XED_CPUID_BIT_AVX512IFMA, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_IFMA_256 */ { XED_CPUID_BIT_AVX512IFMA, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_IFMA_512 */ { XED_CPUID_BIT_AVX512IFMA, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VAES_128 */ { XED_CPUID_BIT_VAES, XED_CPUID_BIT_AES, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL } , +/* AVX512_VAES_256 */ { XED_CPUID_BIT_VAES, XED_CPUID_BIT_AES, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL } , +/* AVX512_VAES_512 */ { XED_CPUID_BIT_VAES, XED_CPUID_BIT_AES, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID } , +/* AVX512_VBMI2_128 */ { XED_CPUID_BIT_AVX512_VBMI2, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VBMI2_256 */ { XED_CPUID_BIT_AVX512_VBMI2, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VBMI2_512 */ { XED_CPUID_BIT_AVX512_VBMI2, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VBMI_128 */ { XED_CPUID_BIT_AVX512VBMI, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VBMI_256 */ { XED_CPUID_BIT_AVX512VBMI, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VBMI_512 */ { XED_CPUID_BIT_AVX512VBMI, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VNNI_128 */ { XED_CPUID_BIT_AVX512_VNNI, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VNNI_256 */ { XED_CPUID_BIT_AVX512_VNNI, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VNNI_512 */ { XED_CPUID_BIT_AVX512_VNNI, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VP2INTERSECT_128 */ { XED_CPUID_BIT_AVX512_VP2INTERSECT, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VP2INTERSECT_256 */ { XED_CPUID_BIT_AVX512_VP2INTERSECT, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VP2INTERSECT_512 */ { XED_CPUID_BIT_AVX512_VP2INTERSECT, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VPCLMULQDQ_128 */ { XED_CPUID_BIT_VPCLMULQDQ, XED_CPUID_BIT_PCLMULQDQ, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL } , +/* AVX512_VPCLMULQDQ_256 */ { XED_CPUID_BIT_VPCLMULQDQ, XED_CPUID_BIT_PCLMULQDQ, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_AVX512VL } , +/* AVX512_VPCLMULQDQ_512 */ { XED_CPUID_BIT_VPCLMULQDQ, XED_CPUID_BIT_PCLMULQDQ, XED_CPUID_BIT_AVX512F, XED_CPUID_BIT_INVALID } , +/* AVX512_VPOPCNTDQ_128 */ { XED_CPUID_BIT_AVX512_VPOPCNTDQ, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VPOPCNTDQ_256 */ { XED_CPUID_BIT_AVX512_VPOPCNTDQ, XED_CPUID_BIT_AVX512VL, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX512_VPOPCNTDQ_512 */ { XED_CPUID_BIT_AVX512_VPOPCNTDQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVXAES */ { XED_CPUID_BIT_AES, XED_CPUID_BIT_AVX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX_GFNI */ { XED_CPUID_BIT_GFNI, XED_CPUID_BIT_AVX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* AVX_VNNI */ { XED_CPUID_BIT_AVX_VNNI, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* BMI1 */ { XED_CPUID_BIT_BMI1, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* BMI2 */ { XED_CPUID_BIT_BMI2, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CET */ { XED_CPUID_BIT_CET, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CLDEMOTE */ { XED_CPUID_BIT_CLDEMOTE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CLFLUSHOPT */ { XED_CPUID_BIT_CLFLUSHOPT, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CLFSH */ { XED_CPUID_BIT_CLFLUSH, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CLWB */ { XED_CPUID_BIT_CLWB, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CLZERO */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CMOV */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* CMPXCHG16B */ { XED_CPUID_BIT_CMPXCHG16B, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* ENQCMD */ { XED_CPUID_BIT_ENQCMD, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* F16C */ { XED_CPUID_BIT_F16C, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* FAT_NOP */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* FCMOV */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* FMA */ { XED_CPUID_BIT_FMA, XED_CPUID_BIT_AVX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* FMA4 */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* FXSAVE */ { XED_CPUID_BIT_FXSAVE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* FXSAVE64 */ { XED_CPUID_BIT_FXSAVE, XED_CPUID_BIT_INTEL64, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* GFNI */ { XED_CPUID_BIT_GFNI, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* HRESET */ { XED_CPUID_BIT_HRESET, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I186 */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I286PROTECTED */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I286REAL */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I386 */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I486 */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I486REAL */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* I86 */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* INVPCID */ { XED_CPUID_BIT_INVPCID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* KEYLOCKER */ { XED_CPUID_BIT_KLSUPPORTED, XED_CPUID_BIT_KLENABLED, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* KEYLOCKER_WIDE */ { XED_CPUID_BIT_KLSUPPORTED, XED_CPUID_BIT_KLWIDE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* LAHF */ { XED_CPUID_BIT_LAHF, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* LONGMODE */ { XED_CPUID_BIT_INTEL64, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* LWP */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* LZCNT */ { XED_CPUID_BIT_LZCNT, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* MCOMMIT */ { XED_CPUID_BIT_MCOMMIT, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* MONITOR */ { XED_CPUID_BIT_MONITOR, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* MONITORX */ { XED_CPUID_BIT_MONITORX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* MOVBE */ { XED_CPUID_BIT_MOVEBE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* MOVDIR */ { XED_CPUID_BIT_MOVDIRI, XED_CPUID_BIT_MOVDIR64B, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* MPX */ { XED_CPUID_BIT_MPX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PAUSE */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PCLMULQDQ */ { XED_CPUID_BIT_PCLMULQDQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PCONFIG */ { XED_CPUID_BIT_PCONFIG, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PENTIUMMMX */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PENTIUMREAL */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PKU */ { XED_CPUID_BIT_PKU, XED_CPUID_BIT_OSPKU, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* POPCNT */ { XED_CPUID_BIT_POPCNT, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PPRO */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PPRO_UD0_LONG */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PPRO_UD0_SHORT */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PREFETCHW */ { XED_CPUID_BIT_PREFETCHW, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PREFETCHWT1 */ { XED_CPUID_BIT_PREFETCHWT1, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PREFETCH_NOP */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* PTWRITE */ { XED_CPUID_BIT_INTELPT, XED_CPUID_BIT_PTWRITE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDPID */ { XED_CPUID_BIT_RDP, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDPMC */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDPRU */ { XED_CPUID_BIT_RDPRU, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDRAND */ { XED_CPUID_BIT_RDRAND, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDSEED */ { XED_CPUID_BIT_RDSEED, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDTSCP */ { XED_CPUID_BIT_RDTSCP, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RDWRFSGS */ { XED_CPUID_BIT_RDWRFSGS, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* RTM */ { XED_CPUID_BIT_RTM, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SERIALIZE */ { XED_CPUID_BIT_SERIALIZE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SGX */ { XED_CPUID_BIT_SGX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SGX_ENCLV */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SHA */ { XED_CPUID_BIT_SHA, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SMAP */ { XED_CPUID_BIT_SMAP, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SMX */ { XED_CPUID_BIT_SMX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SNP */ { XED_CPUID_BIT_SNP, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE */ { XED_CPUID_BIT_SSE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE2 */ { XED_CPUID_BIT_SSE2, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE2MMX */ { XED_CPUID_BIT_SSE2, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE3 */ { XED_CPUID_BIT_SSE3, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE3X87 */ { XED_CPUID_BIT_SSE3, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE4 */ { XED_CPUID_BIT_SSE4, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE42 */ { XED_CPUID_BIT_SSE42, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE4A */ { XED_CPUID_BIT_SSE4A, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSEMXCSR */ { XED_CPUID_BIT_SSE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSE_PREFETCH */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSSE3 */ { XED_CPUID_BIT_SSSE3, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SSSE3MMX */ { XED_CPUID_BIT_SSSE3, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* SVM */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* TBM */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* TDX */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* TSX_LDTRK */ { XED_CPUID_BIT_TSX_LDTRK, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* UINTR */ { XED_CPUID_BIT_UINTR, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VAES */ { XED_CPUID_BIT_VAES, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VIA_PADLOCK_AES */ { XED_CPUID_BIT_VIA_PADLOCK_AES, XED_CPUID_BIT_VIA_PADLOCK_AES_EN, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VIA_PADLOCK_MONTMUL */ { XED_CPUID_BIT_VIA_PADLOCK_PMM, XED_CPUID_BIT_VIA_PADLOCK_PMM_EN, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VIA_PADLOCK_RNG */ { XED_CPUID_BIT_VIA_PADLOCK_RNG, XED_CPUID_BIT_VIA_PADLOCK_RNG_EN, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VIA_PADLOCK_SHA */ { XED_CPUID_BIT_VIA_PADLOCK_SHA, XED_CPUID_BIT_VIA_PADLOCK_SHA_EN, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VMFUNC */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VPCLMULQDQ */ { XED_CPUID_BIT_VPCLMULQDQ, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* VTX */ { XED_CPUID_BIT_VMX, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* WAITPKG */ { XED_CPUID_BIT_WAITPKG, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* WBNOINVD */ { XED_CPUID_BIT_WBNOINVD, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* X87 */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* XOP */ { XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* XSAVE */ { XED_CPUID_BIT_XSAVE, XED_CPUID_BIT_OSXSAVE, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* XSAVEC */ { XED_CPUID_BIT_XSAVEC, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* XSAVEOPT */ { XED_CPUID_BIT_XSAVEOPT, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +/* XSAVES */ { XED_CPUID_BIT_XSAVES, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID, XED_CPUID_BIT_INVALID } , +}; diff --git a/CodeVirtualizer/build/obj/xed-enc-groups.c b/CodeVirtualizer/build/obj/xed-enc-groups.c new file mode 100644 index 0000000..5979e33 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-enc-groups.c @@ -0,0 +1,61075 @@ +/// @file xed-enc-groups.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encode-private.h" +#include "xed-enc-operand-lu.h" +#include "xed-operand-accessors.h" +#include "xed-encoder.h" +xed_bool_t xed_encode_group_0(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][4] = { + /*FADD */ { 3, 1, 2, 0}, + /*FDIV */ { 24, 22, 23, 21}, + /*FDIVR */ { 28, 26, 27, 25}, + /*FMUL */ { 7, 5, 6, 4}, + /*FSUB */ { 16, 14, 15, 13}, + /*FSUBR */ { 20, 18, 19, 17}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64REAL); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32REAL); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_1(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*FCOMP */ { 9, 10, 11, 12, 8}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_2(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*FCOM */ { 31, 32, 30, 29}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_3(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*FLD */ { 34, 36, 33, 35}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM80REAL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_4(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*FST */ { 39, 38, 37}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64REAL) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32REAL) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_5(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*FSTP */ { 43, 44, 45, 42, 40, 41}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64REAL) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32REAL) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM80REAL) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_6(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[7][1] = { + /*FADDP */ { 156}, + /*FDIVP */ { 162}, + /*FDIVRP */ { 161}, + /*FMULP */ { 157}, + /*FSTPNCE */ { 46}, + /*FSUBP */ { 160}, + /*FSUBRP */ { 159}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_7(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*FLDENV */ { 47, 50, 48, 51, 49, 52, 53}, + /*FNSTENV */ { 55, 58, 56, 59, 57, 60, 61}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM14); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM28); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM14); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM28); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM14); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM28); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM28); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_8(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*FLDCW */ { 54}, + /*FNSTCW */ { 62}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM16); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_9(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*FXCH */ { 63, 64, 65}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_10(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[121][1] = { + /*CLAC */ {2481}, + /*CLC */ {1112}, + /*CLD */ {1116}, + /*CLGI */ {2044}, + /*CLI */ {1114}, + /*CLTS */ {1123}, + /*CLZERO */ {2057}, + /*CMC */ {1111}, + /*CPUID */ {1295}, + /*EMMS */ {1272}, + /*ENCLS */ {2484}, + /*ENCLU */ {2483}, + /*ENCLV */ {2497}, + /*ENDBR32 */ {2439}, + /*ENDBR64 */ {2440}, + /*F2XM1 */ { 78}, + /*FABS */ { 68}, + /*FCHS */ { 67}, + /*FCOMPP */ { 158}, + /*FCOS */ { 93}, + /*FDECSTP */ { 84}, + /*FDISI8087_NOP */ { 134}, + /*FEMMS */ {1988}, + /*FENI8087_NOP */ { 133}, + /*FINCSTP */ { 85}, + /*FLD1 */ { 71}, + /*FLDL2E */ { 73}, + /*FLDL2T */ { 72}, + /*FLDLG2 */ { 75}, + /*FLDLN2 */ { 76}, + /*FLDPI */ { 74}, + /*FLDZ */ { 77}, + /*FNCLEX */ { 130}, + /*FNINIT */ { 131}, + /*FNOP */ { 66}, + /*FPATAN */ { 81}, + /*FPREM */ { 86}, + /*FPREM1 */ { 83}, + /*FPTAN */ { 80}, + /*FRNDINT */ { 90}, + /*FSCALE */ { 91}, + /*FSETPM287_NOP */ { 132}, + /*FSIN */ { 92}, + /*FSINCOS */ { 89}, + /*FSQRT */ { 88}, + /*FTST */ { 69}, + /*FUCOMPP */ { 114}, + /*FWAIT */ { 929}, + /*FXAM */ { 70}, + /*FXTRACT */ { 82}, + /*FYL2X */ { 79}, + /*FYL2XP1 */ { 87}, + /*GETSEC */ {1942}, + /*HLT */ {1110}, + /*INSB */ { 793}, + /*INT1 */ {1109}, + /*INT3 */ {1074}, + /*INVD */ {1391}, + /*LAHF */ { 945}, + /*LFENCE */ { 763}, + /*MCOMMIT */ {2063}, + /*MFENCE */ { 764}, + /*MWAIT */ { 755}, + /*MWAITX */ {2062}, + /*NOP2 */ {1969}, + /*NOP3 */ {1970}, + /*NOP4 */ {1971}, + /*NOP5 */ {1972}, + /*NOP6 */ {1973}, + /*NOP7 */ {1974}, + /*NOP8 */ {1975}, + /*NOP9 */ {1976}, + /*PAUSE */ { 912}, + /*RDMSR */ {1170}, + /*RDPKRU */ {5458}, + /*RDPMC */ {1171}, + /*RDPRU */ {2064}, + /*RDTSC */ {1169}, + /*RDTSCP */ { 760}, + /*REPE_SCASB */ {1042}, + /*REPNE_SCASB */ {1043}, + /*REP_XCRYPTCBC */ {1980}, + /*REP_XCRYPTCFB */ {1982}, + /*REP_XCRYPTCTR */ {1981}, + /*REP_XCRYPTECB */ {1979}, + /*REP_XCRYPTOFB */ {1983}, + /*REP_XSHA1 */ {1984}, + /*REP_XSHA256 */ {1985}, + /*REP_XSTORE */ {1978}, + /*RSM */ {1625}, + /*SAHF */ { 944}, + /*SAVEPREVSSP */ {2446}, + /*SCASB */ {1044}, + /*SERIALIZE */ {7043}, + /*SETSSBSY */ {2447}, + /*SFENCE */ { 761}, + /*STAC */ {2482}, + /*STC */ {1113}, + /*STD */ {1117}, + /*STGI */ {2043}, + /*STI */ {1115}, + /*STOSB */ { 996}, + /*TLBSYNC */ {2071}, + /*UD2 */ {1400}, + /*VMCALL */ { 743}, + /*VMFUNC */ {5443}, + /*VMLAUNCH */ { 744}, + /*VMMCALL */ {2040}, + /*VMRESUME */ { 745}, + /*VMSAVE */ {2042}, + /*VMXOFF */ { 746}, + /*WBNOINVD */ {6845}, + /*WRMSR */ {1168}, + /*WRPKRU */ {5459}, + /*XEND */ {5447}, + /*XGETBV */ {1934}, + /*XRESLDTRK */ {7041}, + /*XSETBV */ {1935}, + /*XSTORE */ {1977}, + /*XSUSLDTRK */ {7042}, + /*XTEST */ {5449}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'VTX', 'VTX', 'VTX', 'VTX', 'MONITOR', 'RDTSCP', 'SSE', 'SSE2', 'SSE2', 'I186', 'PAUSE', 'X87', 'LAHF', 'LAHF', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I286REAL', 'PENTIUMREAL', 'PENTIUMREAL', 'PENTIUMREAL', 'RDPMC', 'PENTIUMMMX', 'I486REAL', 'I486REAL', 'PPRO', 'I486', 'XSAVE', 'XSAVE', 'SMX', 'I86', 'FAT_NOP', 'FAT_NOP', 'FAT_NOP', 'FAT_NOP', 'FAT_NOP', 'FAT_NOP', 'FAT_NOP', 'VIA_PADLOCK_RNG', 'VIA_PADLOCK_RNG', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_AES', 'VIA_PADLOCK_SHA', 'VIA_PADLOCK_SHA', '3DNOW', 'SVM', 'SVM', 'SVM', 'SVM', 'CLZERO', 'MONITORX', 'MCOMMIT', 'RDPRU', 'AMD_INVLPGB', 'CET', 'CET', 'CET', 'CET', 'SMAP', 'SMAP', 'SGX', 'SGX', 'SGX_ENCLV', 'VMFUNC', 'RTM', 'RTM', 'PKU', 'PKU', 'WBNOINVD', 'TSX_LDTRK', 'TSX_LDTRK', 'SERIALIZE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_11(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][2] = { + /*FIADD */ { 95, 94}, + /*FICOM */ { 99, 98}, + /*FICOMP */ { 101, 100}, + /*FIDIV */ { 107, 106}, + /*FIDIVR */ { 109, 108}, + /*FIMUL */ { 97, 96}, + /*FISUB */ { 103, 102}, + /*FISUBR */ { 105, 104}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM16INT); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32INT); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_12(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[14][1] = { + /*FCMOVB */ { 110}, + /*FCMOVBE */ { 112}, + /*FCMOVE */ { 111}, + /*FCMOVNB */ { 126}, + /*FCMOVNBE */ { 128}, + /*FCMOVNE */ { 127}, + /*FCMOVNU */ { 129}, + /*FCMOVU */ { 113}, + /*FCOMI */ { 136}, + /*FCOMIP */ { 167}, + /*FUCOM */ { 154}, + /*FUCOMI */ { 135}, + /*FUCOMIP */ { 166}, + /*FUCOMP */ { 155}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + xed_encode_ntluf_X87(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FCMOV', 'FCMOV', 'FCMOV', 'FCMOV', 'FCMOV', 'FCMOV', 'FCMOV', 'FCMOV', 'PPRO', 'PPRO', 'X87', 'X87', 'PPRO', 'PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_13(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*FILD */ { 117, 116, 115}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64INT); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM16INT); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32INT); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_14(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*FISTP */ { 125, 124, 123}, + /*FISTTP */ { 119, 120, 118}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M64INT) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE3X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM16INT) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE3X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32INT) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE3', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_15(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*FIST */ { 122, 121}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM16INT) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM32INT) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_16(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*FNSAVE */ { 147, 144, 148, 145, 149, 150, 146}, + /*FRSTOR */ { 140, 137, 141, 138, 142, 143, 139}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM108); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM94); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM108); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM94); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM108); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM108); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM94); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_17(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*FNSTSW */ { 152, 151}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM16); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_18(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*FFREE */ { 153}, + /*FFREEP */ { 165}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_X87(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['X87', 'X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_19(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*FBLD */ { 163}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_ST0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM80DEC); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_20(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*FBSTP */ { 164}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MEM80DEC) && + (xed3_operand_get_reg0(xes) == XED_REG_ST0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['X87'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_21(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][6] = { + /*ADC_LOCK */ { 220, 221, 216, 219, 217, 218}, + /*ADD_LOCK */ { 172, 173, 168, 171, 169, 170}, + /*OR_LOCK */ { 196, 197, 192, 195, 193, 194}, + /*SBB_LOCK */ { 244, 245, 240, 243, 241, 242}, + /*SUB_LOCK */ { 292, 293, 288, 291, 289, 290}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_22(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][18] = { + /*ADC */ { 239, 238, 231, 235, 233, 237, 230, 232, 227, 223, 234, 229, 225, 236, 222, 228, 224, 226}, + /*ADD */ { 191, 190, 183, 187, 185, 189, 182, 184, 179, 175, 186, 181, 177, 188, 174, 180, 176, 178}, + /*CMP */ { 353, 352, 345, 349, 347, 351, 344, 346, 341, 337, 348, 343, 339, 350, 336, 342, 338, 340}, + /*SBB */ { 263, 262, 255, 258, 257, 260, 254, 256, 251, 247, 259, 253, 249, 261, 246, 252, 248, 250}, + /*SUB */ { 311, 310, 303, 306, 305, 308, 302, 304, 299, 295, 307, 301, 297, 309, 294, 300, 296, 298}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_23(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][18] = { + /*OR */ { 215, 214, 207, 211, 209, 213, 206, 208, 203, 199, 210, 205, 201, 212, 198, 204, 200, 202}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_24(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*AND_LOCK */ { 268, 269, 264, 267, 265, 266}, + /*XOR_LOCK */ { 316, 317, 312, 315, 313, 314}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_25(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][18] = { + /*AND */ { 287, 286, 279, 282, 281, 284, 278, 280, 275, 271, 283, 277, 273, 285, 270, 276, 272, 274}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_26(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][18] = { + /*XOR */ { 335, 334, 327, 330, 329, 332, 326, 328, 323, 319, 331, 325, 321, 333, 318, 324, 320, 322}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_27(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*POP */ { 358, 356, 357, 359, 360, 361, 355, 354}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_DS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_ES); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_SS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_FS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_GS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_28(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][12] = { + /*RCL */ { 395, 397, 394, 396, 391, 387, 393, 389, 390, 386, 392, 388}, + /*RCR */ { 407, 409, 406, 408, 403, 399, 405, 401, 402, 398, 404, 400}, + /*ROL */ { 371, 373, 370, 372, 367, 363, 369, 365, 366, 362, 368, 364}, + /*ROR */ { 383, 385, 382, 384, 379, 375, 381, 376, 378, 374, 380, 377}, + /*SAR */ { 455, 457, 454, 456, 451, 447, 453, 449, 450, 446, 452, 448}, + /*SHR */ { 443, 445, 442, 444, 439, 435, 441, 437, 438, 434, 440, 436}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_reg0(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_reg0(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I186', 'I186', 'I186', 'I186', 'I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I186', 'I186', 'I186', 'I186', 'I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I186', 'I186', 'I186', 'I186', 'I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I186', 'I186', 'I186', 'I186', 'I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_29(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][24] = { + /*SHL */ { 427, 429, 431, 433, 426, 428, 430, 432, 419, 421, 411, 413, 423, 425, 415, 417, 418, 420, 410, 412, 422, 424, 414, 416}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_reg0(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_reg0(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_reg0(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_reg0(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][20]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][21]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ONE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][22]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][23]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_30(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][14] = { + /*TEST */ { 471, 470, 467, 469, 466, 468, 460, 461, 464, 465, 458, 459, 462, 463}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_31(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][2] = { + /*DEC_LOCK */ { 513, 514}, + /*INC_LOCK */ { 506, 507}, + /*NEG_LOCK */ { 478, 479}, + /*NOT_LOCK */ { 472, 473}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_32(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][4] = { + /*DIV */ { 499, 501, 498, 500}, + /*IDIV */ { 503, 505, 502, 504}, + /*MUL */ { 485, 487, 484, 486}, + /*NEG */ { 481, 483, 480, 482}, + /*NOT */ { 475, 477, 474, 476}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_33(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*IMUL */ { 489, 491, 488, 490, 497, 495, 493, 496, 494, 492}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_34(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*DEC */ { 519, 516, 518, 515, 517}, + /*INC */ { 512, 509, 511, 508, 510}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_35(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*CALL_NEAR */ { 522, 523, 521, 520}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISPz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP32_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CET_NO_TRACK_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CET_NO_TRACK_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_36(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*JMP */ { 528, 526, 527, 529, 525, 524}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISPz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CET_NO_TRACK_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CET_NO_TRACK_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_37(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CALL_FAR */ { 928, 927}, + /*JMP_FAR */ { 531, 530}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_PTR && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_ptr(xes) == 1) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISPz_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM16_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_P2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_38(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*PUSH */ { 535, 537, 534, 536, 540, 539, 538, 541, 542, 533, 532}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_CS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_DS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_ES); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_reg0(xes) == XED_REG_SS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_FS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_GS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_39(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*SLDT */ { 544, 543}, + /*SMSW */ { 558, 557}, + /*STR */ { 546, 545}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I286PROTECTED', 'I286PROTECTED', 'I286REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I286PROTECTED', 'I286PROTECTED', 'I286REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_40(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][2] = { + /*LLDT */ { 548, 547}, + /*LMSW */ { 560, 559}, + /*LTR */ { 550, 549}, + /*VERR */ { 552, 551}, + /*VERW */ { 554, 553}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR16_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I286PROTECTED', 'I286PROTECTED', 'I286PROTECTED', 'I286PROTECTED', 'I286REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['I286PROTECTED', 'I286PROTECTED', 'I286PROTECTED', 'I286PROTECTED', 'I286REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_41(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][2] = { + /*LGDT */ { 556, 555}, + /*LIDT */ { 750, 749}, + /*SGDT */ { 748, 747}, + /*SIDT */ { 756, 757}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_S); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I286REAL', 'I286REAL', 'I286REAL', 'I286REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_S64); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I286REAL', 'I286REAL', 'I286REAL', 'I286REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_42(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][4] = { + /*BT */ { 564, 563, 562, 561}, + /*BTC */ { 582, 581, 580, 579}, + /*BTR */ { 576, 575, 574, 573}, + /*BTS */ { 570, 569, 568, 567}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I386', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I386', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I386', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['I386', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_43(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*BTC_LOCK */ { 578, 577}, + /*BTR_LOCK */ { 572, 571}, + /*BTS_LOCK */ { 566, 565}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_44(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*VMCLEAR */ { 583}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_45(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*CLRSSBSY */ {2438}, + /*RSTORSSP */ {2445}, + /*VMPTRLD */ { 584}, + /*VMPTRST */ { 585}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['VTX', 'VTX', 'CET', 'CET'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_46(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*VMXON */ { 586}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_47(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CMPXCHG8B */ { 589, 590}, + /*CMPXCHG8B_LOCK*/ { 587, 588}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['PENTIUMREAL', 'PENTIUMREAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['PENTIUMREAL', 'PENTIUMREAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_48(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*CMPXCHG16B */ { 592}, + /*CMPXCHG16B_LOCK*/ { 591}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['CMPXCHG16B', 'CMPXCHG16B'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_49(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][22] = { + /*MOV */ { 611, 612, 613, 614, 610, 609, 597, 602, 600, 606, 604, 608, 598, 599, 605, 593, 601, 595, 603, 607, 594, 596}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID) && + (xed3_operand_get_index(xes) == XED_REG_INVALID); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MEMDISPv_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID) && + (xed3_operand_get_index(xes) == XED_REG_INVALID); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MEMDISPv_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_SB(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMMv_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID) && + (xed3_operand_get_index(xes) == XED_REG_INVALID); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MEMDISPv_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID) && + (xed3_operand_get_index(xes) == XED_REG_INVALID); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MEMDISPv_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_SEG(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_SEG_MOV(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR16_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + xed_encode_ntluf_SEG(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_SEG_MOV(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][20]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][21]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SIMMz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_50(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][6] = { + /*PSLLD */ { 648, 645, 647, 650, 646, 649}, + /*PSLLQ */ { 660, 657, 659, 662, 658, 661}, + /*PSLLW */ { 630, 627, 629, 632, 628, 631}, + /*PSRAD */ { 642, 639, 641, 644, 640, 643}, + /*PSRAW */ { 624, 621, 623, 626, 622, 625}, + /*PSRLD */ { 636, 633, 635, 638, 634, 637}, + /*PSRLQ */ { 654, 651, 653, 656, 652, 655}, + /*PSRLW */ { 618, 615, 617, 620, 616, 619}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_51(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*PSLLDQ */ { 664}, + /*PSRLDQ */ { 663}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_52(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*FXRSTOR */ { 666}, + /*FXRSTOR64 */ { 668}, + /*FXSAVE */ { 665}, + /*FXSAVE64 */ { 667}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MFPXENV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FXSAVE', 'FXSAVE', 'FXSAVE64', 'FXSAVE64'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_53(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*LDMXCSR */ { 669}, + /*STMXCSR */ { 670}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSEMXCSR', 'SSEMXCSR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_54(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][1] = { + /*CLFLUSH */ { 762}, + /*PREFETCHNTA */ { 671}, + /*PREFETCHT0 */ { 672}, + /*PREFETCHT1 */ { 673}, + /*PREFETCHT2 */ { 674}, + /*PREFETCH_EXCLUSIVE*/ {1961}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['SSE_PREFETCH', 'SSE_PREFETCH', 'SSE_PREFETCH', 'SSE_PREFETCH', 'CLFSH', 'PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_55(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][60] = { + /*NOP */ { 700, 699, 701, 702, 730, 707, 708, 704, 705, 706, 675, 676, 677, 678, 680, 682, 683, 684, 688, 696, 703, 712, 713, 714, 715, 716, 717, 718, 719, 720, 721, 722, 723, 724, 725, 726, 727, 728, 729, 741, 679, 681, 685, 686, 687, 695, 711, 731, 732, 733, 734, 735, 736, 737, 738, 739, 740, 742, 709, 710}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 0) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 0) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][20]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][21]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][22]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][23]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][24]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][25]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][26]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][27]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][28]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][29]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][30]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][31]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][32]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][33]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][34]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][35]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][36]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][37]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][38]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][39]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][40]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][41]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][42]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][43]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][44]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['FAT_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][45]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][46]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][47]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][48]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][49]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][50]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][51]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][52]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][53]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][54]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][55]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][56]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][57]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 0) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][58]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 0) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][59]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_56(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*MONITOR */ { 752, 751, 754, 753}, + /*MONITORX */ {2059,2058,2061,2060}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_easz(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['MONITOR', 'MONITORX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_easz(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['MONITOR', 'MONITORX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_easz(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['MONITOR', 'MONITORX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_easz(xes) == 3); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['MONITOR', 'MONITORX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_57(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][1] = { + /*CLDEMOTE */ {2496}, + /*INVLPG */ { 758}, + /*PREFETCHWT1 */ {5565}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I486REAL', 'CLDEMOTE', 'PREFETCHWT1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_58(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[17][1] = { + /*CDQE */ { 916}, + /*CLUI */ {7022}, + /*CQO */ { 923}, + /*IRETQ */ {1083}, + /*REPE_SCASQ */ {1063}, + /*REPNE_SCASQ */ {1064}, + /*SCASQ */ {1065}, + /*SEAMCALL */ {7044}, + /*SEAMOPS */ {7045}, + /*SEAMRET */ {7046}, + /*STOSQ */ {1017}, + /*STUI */ {7024}, + /*SWAPGS */ { 759}, + /*SYSRET */ {1124}, + /*SYSRET64 */ {1125}, + /*TESTUI */ {7025}, + /*UIRET */ {7026}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE', 'UINTR', 'UINTR', 'UINTR', 'UINTR', 'TDX', 'TDX', 'TDX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_59(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][1] = { + /*LOADIWKEY */ {7020}, + /*MOVHLPS */ { 765}, + /*MOVLHPS */ { 768}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE', 'SSE', 'KEYLOCKER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_60(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*MOVHPS */ { 770, 769}, + /*MOVLPS */ { 767, 766}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_61(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[7][1] = { + /*AAA */ { 773}, + /*AAS */ { 774}, + /*DAA */ { 771}, + /*DAS */ { 772}, + /*INTO */ {1076}, + /*SALC */ {1086}, + /*SYSRET_AMD */ {2038}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'AMD'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_62(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][2] = { + /*POPA */ { 779, 780}, + /*POPAD */ { 781, 782}, + /*POPFD */ { 940, 941}, + /*PUSHA */ { 775, 776}, + /*PUSHAD */ { 777, 778}, + /*PUSHFD */ { 934, 933}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I386', 'I186', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I386', 'I186', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_63(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*BOUND */ { 783, 785, 784, 786}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_A16); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_A32); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_A16); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_A32); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_64(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*ARPL */ { 788, 787}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR16_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR16_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I286PROTECTED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + xed_encode_ntluf_GPR16_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I286PROTECTED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_65(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*MOVSXD */ { 790, 789}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRz_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Z); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_66(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*REP_INSB */ { 791, 792}, + /*REP_STOSB */ { 994, 995}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I186', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I186', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_67(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*REP_INSW */ { 794, 797, 795, 798, 796, 799}, + /*REP_STOSD */ {1006,1009,1007,1010,1008,1011}, + /*REP_STOSW */ { 997,1000, 998,1001, 999,1002}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_68(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[17][3] = { + /*CBW */ { 913, 914, 915}, + /*CDQ */ { 924, 925, 926}, + /*CWD */ { 920, 921, 922}, + /*CWDE */ { 917, 918, 919}, + /*INSW */ { 800, 801, 802}, + /*IRET */ {1077,1078,1079}, + /*IRETD */ {1080,1081,1082}, + /*POPF */ { 937, 938, 939}, + /*PUSHF */ { 930, 931, 932}, + /*REPE_SCASD */ {1054,1055,1056}, + /*REPE_SCASW */ {1045,1046,1047}, + /*REPNE_SCASD */ {1057,1058,1059}, + /*REPNE_SCASW */ {1048,1049,1050}, + /*SCASD */ {1060,1061,1062}, + /*SCASW */ {1051,1052,1053}, + /*STOSD */ {1012,1013,1014}, + /*STOSW */ {1003,1004,1005}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I186', 'I86', 'I386', 'I86', 'I386', 'I86', 'I86', 'I86', 'I386', 'I86', 'I86', 'I86', 'I386', 'I386', 'I386', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I186', 'I86', 'I386', 'I86', 'I386', 'I86', 'I86', 'I86', 'I386', 'I86', 'I86', 'I86', 'I386', 'I386', 'I386', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I186', 'I86', 'I386', 'I86', 'I386', 'I86', 'I86', 'I86', 'I386', 'I86', 'I86', 'I86', 'I386', 'I386', 'I386', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_69(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*REP_INSD */ { 803, 807, 804, 808, 805, 806, 809, 810}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_70(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*INSD */ { 811, 812, 813, 814}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_71(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*REP_LODSB */ {1018,1019}, + /*REP_OUTSB */ { 815, 816}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I186', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I186', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_72(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][1] = { + /*CMPSB */ { 972}, + /*LODSB */ {1020}, + /*OUTSB */ { 817}, + /*REPE_CMPSB */ { 970}, + /*REPNE_CMPSB */ { 971}, + /*XLAT */ {1087}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['I186', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_73(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*REP_LODSD */ {1030,1033,1031,1034,1032,1035}, + /*REP_LODSW */ {1021,1024,1022,1025,1023,1026}, + /*REP_OUTSW */ { 818, 821, 819, 822, 820, 823}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I186', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_74(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[9][3] = { + /*CMPSD */ { 988, 989, 990}, + /*CMPSW */ { 979, 980, 981}, + /*LODSD */ {1036,1037,1038}, + /*LODSW */ {1027,1028,1029}, + /*OUTSW */ { 824, 825, 826}, + /*REPE_CMPSD */ { 982, 983, 984}, + /*REPE_CMPSW */ { 973, 974, 975}, + /*REPNE_CMPSD */ { 985, 986, 987}, + /*REPNE_CMPSW */ { 976, 977, 978}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['I186', 'I86', 'I86', 'I86', 'I386', 'I386', 'I386', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['I186', 'I86', 'I86', 'I86', 'I386', 'I386', 'I386', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['I186', 'I86', 'I86', 'I86', 'I386', 'I386', 'I386', 'I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_75(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*REP_OUTSD */ { 827, 831, 828, 832, 829, 830, 833, 834}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_76(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*OUTSD */ { 835, 836, 837, 838}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_77(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[16][4] = { + /*JB */ { 848, 849, 847, 850}, + /*JBE */ { 864, 865, 863, 866}, + /*JL */ { 888, 889, 887, 890}, + /*JLE */ { 896, 897, 895, 898}, + /*JNB */ { 852, 853, 851, 854}, + /*JNBE */ { 868, 869, 867, 870}, + /*JNL */ { 892, 893, 891, 894}, + /*JNLE */ { 900, 901, 899, 902}, + /*JNO */ { 844, 845, 843, 846}, + /*JNP */ { 884, 885, 883, 886}, + /*JNS */ { 876, 877, 875, 878}, + /*JNZ */ { 860, 861, 859, 862}, + /*JO */ { 840, 842, 839, 841}, + /*JP */ { 880, 881, 879, 882}, + /*JS */ { 872, 873, 871, 874}, + /*JZ */ { 856, 857, 855, 858}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRANCH_HINT_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRANCH_HINT_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISPz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRANCH_HINT_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRANCH_HINT_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_78(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*XCHG */ { 909, 910, 905, 908, 903, 904, 906, 907}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_OrAX(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_79(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*LEA */ { 911}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_AGEN) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_agen(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REMOVE_SEGMENT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_80(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*POPFQ */ { 942, 943}, + /*PUSHFQ */ { 935, 936}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['LONGMODE', 'LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['LONGMODE', 'LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_81(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*REP_MOVSB */ { 946, 947}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_82(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVSB */ { 948}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_83(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*REP_MOVSD */ { 958, 961, 959, 962, 960, 963}, + /*REP_MOVSW */ { 949, 952, 950, 953, 951, 954}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_84(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*MOVSD */ { 964, 965, 966}, + /*MOVSW */ { 955, 956, 957}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_85(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*REP_MOVSQ */ { 967, 968}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_86(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVSQ */ { 969}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_87(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*CMPSQ */ { 993}, + /*LODSQ */ {1041}, + /*REPE_CMPSQ */ { 991}, + /*REPNE_CMPSQ */ { 992}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['LONGMODE', 'LONGMODE', 'LONGMODE', 'LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_88(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*REP_STOSQ */ {1015,1016}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_89(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*REP_LODSQ */ {1039,1040}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_90(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*RET_NEAR */ {1067,1066}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM16_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_91(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*LDS */ {1069}, + /*LES */ {1068}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPRz_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_P); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_92(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*ENTER */ {1070}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_IMM0 && xes->_operand_order[1] == XED_OPERAND_IMM1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1) && + (xed3_operand_get_imm1(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM16_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_93(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*LEAVE */ {1071}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I186'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_94(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*RET_FAR */ {1073,1072}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM16_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_95(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][1] = { + /*HRESET */ {7021}, + /*INT */ {1075}, + /*XABORT */ {5448}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I86', 'RTM', 'HRESET'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_96(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*AAD */ {1085}, + /*AAM */ {1084}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_97(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*LOOPE */ {1094,1092,1093,1095}, + /*LOOPNE */ {1090,1088,1089,1091}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_modep5(xes) == 0) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_modep5(xes) == 1) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_modep5(xes) == 1) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_modep5(xes) == 1) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I86', 'I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_98(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*LOOP */ {1096}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_DF64_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_99(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*JCXZ */ {1097}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 1) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_100(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*JECXZ */ {1098,1099}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_101(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*JRCXZ */ {1100}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISP8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_102(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*IN */ {1103,1104,1101,1102}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_reg1(xes) == XED_REG_DX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OeAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_DX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE_REXW_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_AL) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_IMM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_OeAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE_REXW_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_103(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*OUT */ {1107,1105,1108,1106}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_DX) && + (xed3_operand_get_reg1(xes) == XED_REG_AL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_IMM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1) && + (xed3_operand_get_reg0(xes) == XED_REG_AL); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_DX) && + xed_encode_ntluf_OeAX(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE_REXW_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_IMM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_imm0(xes) == 1) && + xed_encode_ntluf_OeAX(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE_REXW_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_104(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*LAR */ {1119,1118}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I286PROTECTED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I286PROTECTED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_105(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*LSL */ {1121,1120}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRz_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I286PROTECTED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I286PROTECTED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_106(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*SYSCALL */ {1122}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LONGMODE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FORCE64_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_107(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*MOVAPS */ {1404,1402,1403,1401}, + /*MOVUPS */ {1129,1127,1128,1126}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_108(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[10][2] = { + /*CVTDQ2PS */ {1478,1477}, + /*GF2P8MULB */ {6966,6967}, + /*SHA1MSG1 */ {2453,2454}, + /*SHA1MSG2 */ {2455,2456}, + /*SHA1NEXTE */ {2457,2458}, + /*SHA256MSG1 */ {2461,2462}, + /*SHA256MSG2 */ {2463,2464}, + /*SHA256RNDS2 */ {2465,2466}, + /*UNPCKHPS */ {1133,1132}, + /*UNPCKLPS */ {1131,1130}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True] isa_set ['SSE', 'SSE', 'SSE2', 'SHA', 'SHA', 'SHA', 'SHA', 'SHA', 'SHA', 'GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True] isa_set ['SSE', 'SSE', 'SSE2', 'SHA', 'SHA', 'SHA', 'SHA', 'SHA', 'SHA', 'GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_109(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*MOVSS */ {1137,1135,1136,1134}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_110(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][2] = { + /*ADDSUBPS */ {1350,1349}, + /*CVTTPS2DQ */ {1494,1493}, + /*HADDPS */ {1606,1605}, + /*HSUBPS */ {1608,1607}, + /*MOVSHDUP */ {1141,1140}, + /*MOVSLDUP */ {1139,1138}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['SSE3', 'SSE3', 'SSE3', 'SSE2', 'SSE3', 'SSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['SSE3', 'SSE3', 'SSE3', 'SSE2', 'SSE3', 'SSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_111(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*MOVAPD */ {1431,1429,1430,1428}, + /*MOVUPD */ {1145,1143,1144,1142}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PD) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_112(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*MOVHPD */ {1153,1152}, + /*MOVLPD */ {1147,1146}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_113(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[27][2] = { + /*AESDEC */ {1949,1950}, + /*AESDECLAST */ {1951,1952}, + /*AESENC */ {1945,1946}, + /*AESENCLAST */ {1947,1948}, + /*AESIMC */ {1953,1954}, + /*BLENDVPD */ {1822,1821}, + /*BLENDVPS */ {1824,1823}, + /*PACKUSDW */ {1839,1838}, + /*PBLENDVB */ {1843,1842}, + /*PCMPEQQ */ {1826,1825}, + /*PCMPGTQ */ {1812,1811}, + /*PHMINPOSUW */ {1869,1868}, + /*PMAXSB */ {1871,1870}, + /*PMAXSD */ {1873,1872}, + /*PMAXUD */ {1875,1874}, + /*PMAXUW */ {1877,1876}, + /*PMINSB */ {1879,1878}, + /*PMINSD */ {1881,1880}, + /*PMINUD */ {1883,1882}, + /*PMINUW */ {1885,1884}, + /*PMULDQ */ {1889,1888}, + /*PMULLD */ {1887,1886}, + /*PTEST */ {1867,1866}, + /*PUNPCKHQDQ */ {1584,1583}, + /*PUNPCKLQDQ */ {1582,1581}, + /*UNPCKHPD */ {1151,1150}, + /*UNPCKLPD */ {1149,1148}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE42', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'AES', 'AES', 'AES', 'AES', 'AES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE42', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'AES', 'AES', 'AES', 'AES', 'AES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_114(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*MOVSD_XMM */ {1157,1155,1156,1154}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_115(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CVTDQ2PD */ {1373,1372}, + /*MOVDDUP */ {1159,1158}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE3', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE3', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_116(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*MOV_CR */ {1160,1162,1161,1163}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_CR_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_CR_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_CR_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_CR_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_117(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*MOV_DR */ {1164,1166,1165,1167}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_DR_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_DR_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_DR_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_DR_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I86'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_118(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][2] = { + /*PCONFIG */ {6846,6847}, + /*SYSENTER */ {1172,1173}, + /*SYSEXIT */ {1174,1175}, + /*TDCALL */ {7048,7047}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['PPRO', 'PPRO', 'PCONFIG', 'TDX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['PPRO', 'PPRO', 'PCONFIG', 'TDX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_119(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[18][2] = { + /*CMOVB */ {1181,1180}, + /*CMOVBE */ {1189,1188}, + /*CMOVL */ {1464,1463}, + /*CMOVLE */ {1468,1467}, + /*CMOVNB */ {1183,1182}, + /*CMOVNBE */ {1191,1190}, + /*CMOVNL */ {1466,1465}, + /*CMOVNLE */ {1470,1469}, + /*CMOVNO */ {1179,1178}, + /*CMOVNP */ {1462,1461}, + /*CMOVNS */ {1458,1457}, + /*CMOVNZ */ {1187,1186}, + /*CMOVO */ {1177,1176}, + /*CMOVP */ {1460,1459}, + /*CMOVS */ {1456,1455}, + /*CMOVZ */ {1185,1184}, + /*POPCNT */ {1810,1809}, + /*TZCNT */ {5442,5441}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'POPCNT', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'CMOV', 'POPCNT', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_120(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVMSKPS */ {1192}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_121(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[9][2] = { + /*ADDPS */ {1472,1471}, + /*DIVPS */ {1484,1483}, + /*MAXPS */ {1486,1485}, + /*MINPS */ {1482,1481}, + /*MULPS */ {1474,1473}, + /*RCPPS */ {1198,1197}, + /*RSQRTPS */ {1196,1195}, + /*SQRTPS */ {1194,1193}, + /*SUBPS */ {1480,1479}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_122(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][2] = { + /*ANDNPS */ {1202,1201}, + /*ANDPS */ {1200,1199}, + /*ORPS */ {1204,1203}, + /*XORPS */ {1206,1205}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['SSE', 'SSE', 'SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_XUD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['SSE', 'SSE', 'SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_123(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[10][2] = { + /*ADDSS */ {1488,1487}, + /*CVTSS2SD */ {1492,1491}, + /*DIVSS */ {1500,1499}, + /*MAXSS */ {1502,1501}, + /*MINSS */ {1498,1497}, + /*MULSS */ {1490,1489}, + /*RCPSS */ {1212,1211}, + /*RSQRTSS */ {1210,1209}, + /*SQRTSS */ {1208,1207}, + /*SUBSS */ {1496,1495}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True] isa_set ['SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE2', 'SSE', 'SSE', 'SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True] isa_set ['SSE', 'SSE', 'SSE', 'SSE', 'SSE', 'SSE2', 'SSE', 'SSE', 'SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_124(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVMSKPD */ {1213}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_125(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[12][2] = { + /*ADDPD */ {1504,1503}, + /*ADDSUBPD */ {1347,1346}, + /*CVTPD2PS */ {1508,1507}, + /*CVTTPD2DQ */ {1370,1369}, + /*DIVPD */ {1516,1515}, + /*HADDPD */ {1598,1597}, + /*HSUBPD */ {1600,1599}, + /*MAXPD */ {1518,1517}, + /*MINPD */ {1514,1513}, + /*MULPD */ {1506,1505}, + /*SQRTPD */ {1215,1214}, + /*SUBPD */ {1512,1511}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE3', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE3', 'SSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE3', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE3', 'SSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_126(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][2] = { + /*ANDNPD */ {1219,1218}, + /*ANDPD */ {1217,1216}, + /*ORPD */ {1221,1220}, + /*XORPD */ {1223,1222}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_XUQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_127(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][2] = { + /*ADDSD */ {1520,1519}, + /*CVTSD2SS */ {1524,1523}, + /*DIVSD */ {1530,1529}, + /*MAXSD */ {1532,1531}, + /*MINSD */ {1528,1527}, + /*MULSD */ {1522,1521}, + /*SQRTSD */ {1225,1224}, + /*SUBSD */ {1526,1525}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_128(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][4] = { + /*PUNPCKLBW */ {1227,1226,1229,1228}, + /*PUNPCKLDQ */ {1235,1234,1237,1236}, + /*PUNPCKLWD */ {1231,1230,1233,1232}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_129(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[59][4] = { + /*PABSB */ {1798,1797,1800,1799}, + /*PABSD */ {1806,1805,1808,1807}, + /*PABSW */ {1802,1801,1804,1803}, + /*PACKSSDW */ {1546,1545,1548,1547}, + /*PACKSSWB */ {1239,1238,1241,1240}, + /*PACKUSWB */ {1255,1254,1257,1256}, + /*PADDB */ {1734,1733,1736,1735}, + /*PADDD */ {1742,1741,1744,1743}, + /*PADDQ */ {1337,1336,1339,1338}, + /*PADDSB */ {1702,1701,1704,1703}, + /*PADDSW */ {1706,1705,1708,1707}, + /*PADDUSB */ {1670,1669,1672,1671}, + /*PADDUSW */ {1674,1673,1676,1675}, + /*PADDW */ {1738,1737,1740,1739}, + /*PAND */ {1666,1665,1668,1667}, + /*PANDN */ {1682,1681,1684,1683}, + /*PAVGB */ {1353,1352,1355,1354}, + /*PAVGW */ {1357,1356,1359,1358}, + /*PCMPEQB */ {1261,1260,1263,1262}, + /*PCMPEQD */ {1269,1268,1271,1270}, + /*PCMPEQW */ {1265,1264,1267,1266}, + /*PCMPGTB */ {1243,1242,1245,1244}, + /*PCMPGTD */ {1251,1250,1253,1252}, + /*PCMPGTW */ {1247,1246,1249,1248}, + /*PHADDD */ {1750,1749,1752,1751}, + /*PHADDSW */ {1754,1753,1756,1755}, + /*PHADDW */ {1746,1745,1748,1747}, + /*PHSUBD */ {1762,1761,1764,1763}, + /*PHSUBSW */ {1766,1765,1768,1767}, + /*PHSUBW */ {1758,1757,1760,1759}, + /*PMADDUBSW */ {1770,1769,1772,1771}, + /*PMADDWD */ {1381,1380,1383,1382}, + /*PMAXSW */ {1710,1709,1712,1711}, + /*PMAXUB */ {1678,1677,1680,1679}, + /*PMINSW */ {1694,1693,1696,1695}, + /*PMINUB */ {1662,1661,1664,1663}, + /*PMULHRSW */ {1774,1773,1776,1775}, + /*PMULHUW */ {1361,1360,1363,1362}, + /*PMULHW */ {1365,1364,1367,1366}, + /*PMULLW */ {1341,1340,1343,1342}, + /*PMULUDQ */ {1377,1376,1379,1378}, + /*POR */ {1698,1697,1700,1699}, + /*PSADBW */ {1385,1384,1387,1386}, + /*PSHUFB */ {1778,1777,1780,1779}, + /*PSIGNB */ {1782,1781,1784,1783}, + /*PSIGND */ {1790,1789,1792,1791}, + /*PSIGNW */ {1786,1785,1788,1787}, + /*PSUBB */ {1718,1717,1720,1719}, + /*PSUBD */ {1726,1725,1728,1727}, + /*PSUBQ */ {1730,1729,1732,1731}, + /*PSUBSB */ {1686,1685,1688,1687}, + /*PSUBSW */ {1690,1689,1692,1691}, + /*PSUBUSB */ {1654,1653,1656,1655}, + /*PSUBUSW */ {1658,1657,1660,1659}, + /*PSUBW */ {1722,1721,1724,1723}, + /*PUNPCKHBW */ {1534,1533,1536,1535}, + /*PUNPCKHDQ */ {1542,1541,1544,1543}, + /*PUNPCKHWD */ {1538,1537,1540,1539}, + /*PXOR */ {1714,1713,1716,1715}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSE2MMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSE2MMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSE2MMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSE2MMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSE2MMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSE2MMX', 'PENTIUMMMX', 'PENTIUMMMX', 'PENTIUMMMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX', 'SSSE3MMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSE2', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3', 'SSSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_130(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PSHUFW */ {1259,1258}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_131(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[9][2] = { + /*AESKEYGENASSIST*/ {1943,1944}, + /*BLENDPD */ {1818,1817}, + /*BLENDPS */ {1820,1819}, + /*DPPD */ {1828,1827}, + /*DPPS */ {1830,1829}, + /*MPSADBW */ {1837,1836}, + /*PBLENDW */ {1841,1840}, + /*PCLMULQDQ */ {1955,1956}, + /*PSHUFD */ {1274,1273}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'AES', 'PCLMULQDQ'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['SSE2', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'AES', 'PCLMULQDQ'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_132(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*PSHUFHW */ {1278,1277}, + /*PSHUFLW */ {1276,1275}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_133(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[16][2] = { + /*SETB */ {1284,1283}, + /*SETBE */ {1292,1291}, + /*SETL */ {1618,1617}, + /*SETLE */ {1622,1621}, + /*SETNB */ {1286,1285}, + /*SETNBE */ {1294,1293}, + /*SETNL */ {1620,1619}, + /*SETNLE */ {1624,1623}, + /*SETNO */ {1282,1281}, + /*SETNP */ {1616,1615}, + /*SETNS */ {1612,1611}, + /*SETNZ */ {1290,1289}, + /*SETO */ {1280,1279}, + /*SETP */ {1614,1613}, + /*SETS */ {1610,1609}, + /*SETZ */ {1288,1287}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_134(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CMPXCHG_LOCK */ {1296,1297}, + /*XADD_LOCK */ {1309,1310}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I486REAL', 'I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I486REAL', 'I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_135(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*CMPXCHG */ {1299,1301,1298,1300}, + /*XADD */ {1312,1314,1311,1313}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I486REAL', 'I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I486REAL', 'I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_GPR8_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I486REAL', 'I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I486REAL', 'I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_136(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][1] = { + /*LFS */ {1303}, + /*LGS */ {1304}, + /*LSS */ {1302}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_P2); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['I386', 'I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_137(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*MOVSX */ {1651,1649,1648,1650}, + /*MOVZX */ {1308,1306,1305,1307}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR16_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_138(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CMPPS */ {1316,1315}, + /*SHUFPS */ {1327,1326}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_139(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*MOVNTI */ {1317,1318,1319}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_140(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*PINSRW */ {1321,1320,1323,1322}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_141(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PEXTRW */ {1324,1325}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_142(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CMPSS */ {1329,1328}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_143(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*CMPPD */ {1331,1330}, + /*ROUNDPD */ {1859,1858}, + /*SHUFPD */ {1333,1332}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE2', 'SSE2', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE2', 'SSE2', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_144(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CMPSD_XMM */ {1335,1334}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_145(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PMOVMSKB */ {1344,1345}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_146(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVQ2DQ */ {1348}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_147(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVDQ2Q */ {1351}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_148(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVNTQ */ {1368}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_149(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*MOVNTDQ */ {1371}, + /*MOVNTPD */ {1434}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_150(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CVTPD2DQ */ {1375,1374}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_151(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MASKMOVQ */ {1388}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_152(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MASKMOVDQU */ {1389}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_153(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*LDDQU */ {1390}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_154(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*WBINVD */ {1392,1393,1394}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = 1; + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_155(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*UD0 */ {1395,1397,1396}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode_short_ud0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO_UD0_SHORT'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode_short_ud0(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO_UD0_LONG'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode_short_ud0(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO_UD0_LONG'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_156(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*UD1 */ {1399,1398}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PPRO'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_157(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CVTPI2PS */ {1406,1405}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_158(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVNTPS */ {1407}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_159(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CVTPS2PI */ {1411,1410}, + /*CVTTPS2PI */ {1409,1408}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_160(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*COMISS */ {1415,1414}, + /*UCOMISS */ {1413,1412}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_161(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*CVTSI2SD */ {1444,1446,1443,1445}, + /*CVTSI2SS */ {1417,1419,1416,1418}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_162(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*CVTSS2SI */ {1425,1427,1424,1426}, + /*CVTTSS2SI */ {1421,1423,1420,1422}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SS); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE', 'SSE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_163(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CVTPI2PD */ {1433,1432}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_164(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*CVTPD2PI */ {1438,1437}, + /*CVTTPD2PI */ {1436,1435}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_165(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*COMISD */ {1442,1441}, + /*UCOMISD */ {1440,1439}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_166(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*CVTSD2SI */ {1452,1454,1451,1453}, + /*CVTTSD2SI */ {1448,1450,1447,1449}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_SD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE2', 'SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_167(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CVTPS2PD */ {1476,1475}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_168(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*CVTPS2DQ */ {1510,1509}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_169(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][16] = { + /*MOVD */ {1564,1560,1562,1558,1563,1556,1559,1552,1561,1554,1557,1550,1555,1551,1553,1549}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_170(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][16] = { + /*MOVQ */ {1576,1574,1580,1578,1579,1575,1568,1573,1566,1577,1570,1572,1569,1567,1565,1571}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PENTIUMMMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_171(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*MOVDQU */ {1588,1586,1587,1585}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_172(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VMREAD */ {1592,1590,1591,1589}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_173(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VMWRITE */ {1596,1594,1595,1593}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VTX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_174(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*MOVDQA */ {1602,1604,1601,1603}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_175(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*SHLD */ {1633,1632,1631,1630}, + /*SHRD */ {1629,1628,1627,1626}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_reg2(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_CL); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['I386', 'I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_176(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*BSF */ {1635,1637,1639,1634,1636,1638}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_177(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*BSR */ {1641,1643,1645,1647,1640,1642,1644,1646}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I386'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_178(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*BSWAP */ {1652}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_SB(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['I486REAL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_179(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*PALIGNR */ {1794,1793,1796,1795}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSSE3MMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSSE3MMX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSSE3'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_180(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*CRC32 */ {1814,1816,1813,1815}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRy_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR8_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRy_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRy_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRy_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_181(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVNTDQA */ {1831}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_182(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*EXTRACTPS */ {1833,1832}, + /*PEXTRD */ {1851,1850}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_183(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*INSERTPS */ {1835,1834}, + /*ROUNDSS */ {1865,1864}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_184(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PEXTRB */ {1845,1844}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_185(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PEXTRW_SSE4 */ {1847,1846}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_186(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PEXTRQ */ {1849,1848}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_187(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PINSRB */ {1853,1852}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_188(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PINSRD */ {1855,1854}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_189(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PINSRQ */ {1857,1856}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_190(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*ROUNDPS */ {1861,1860}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PS) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_191(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*ROUNDSD */ {1863,1862}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_192(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][2] = { + /*PMOVSXBW */ {1891,1890}, + /*PMOVSXDQ */ {1901,1900}, + /*PMOVSXWD */ {1897,1896}, + /*PMOVZXBW */ {1903,1902}, + /*PMOVZXDQ */ {1913,1912}, + /*PMOVZXWD */ {1909,1908}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_193(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][2] = { + /*PMOVSXBD */ {1893,1892}, + /*PMOVSXWQ */ {1899,1898}, + /*PMOVZXBD */ {1905,1904}, + /*PMOVZXWQ */ {1911,1910}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['SSE4', 'SSE4', 'SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['SSE4', 'SSE4', 'SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_194(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*PMOVSXBQ */ {1895,1894}, + /*PMOVZXBQ */ {1907,1906}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SSE4', 'SSE4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_195(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][4] = { + /*PCMPESTRI */ {1915,1917,1914,1916}, + /*PCMPESTRM */ {1927,1929,1926,1928}, + /*PCMPISTRI */ {1921,1923,1920,1922}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE42', 'SSE42', 'SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE42', 'SSE42', 'SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE42', 'SSE42', 'SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE42', 'SSE42', 'SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_196(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*PCMPESTRI64 */ {1919,1918}, + /*PCMPESTRM64 */ {1931,1930}, + /*PCMPISTRI64 */ {1925,1924}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE42', 'SSE42', 'SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SSE42', 'SSE42', 'SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_197(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PCMPISTRM */ {1933,1932}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE42'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_198(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[12][1] = { + /*XRSTOR */ {1937}, + /*XRSTOR64 */ {1939}, + /*XRSTORS */ {2471}, + /*XRSTORS64 */ {2472}, + /*XSAVE */ {1936}, + /*XSAVE64 */ {1938}, + /*XSAVEC */ {2473}, + /*XSAVEC64 */ {2474}, + /*XSAVEOPT */ {2467}, + /*XSAVEOPT64 */ {2468}, + /*XSAVES */ {2469}, + /*XSAVES64 */ {2470}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MXSAVE); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['XSAVE', 'XSAVE', 'XSAVE', 'XSAVE', 'XSAVEOPT', 'XSAVEOPT', 'XSAVES', 'XSAVES', 'XSAVES', 'XSAVES', 'XSAVEC', 'XSAVEC'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_199(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*MOVBE */ {1941,1940}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V) && + xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MOVBE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MOVBE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_200(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*INVEPT */ {1958,1957}, + /*INVPCID */ {5445,5444}, + /*INVVPID */ {1960,1959}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['VTX', 'VTX', 'INVPCID'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['VTX', 'VTX', 'INVPCID'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_CR_WIDTH_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_201(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PREFETCHW */ {1962,1963}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_202(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*PREFETCH_RESERVED*/ {1964,1965,1966,1967,1968}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PREFETCH_NOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_203(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*REP_MONTMUL */ {1986,1987}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VIA_PADLOCK_MONTMUL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VIA_PADLOCK_MONTMUL'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_204(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[24][2] = { + /*PAVGUSB */ {2036,2035}, + /*PF2ID */ {1996,1995}, + /*PF2IW */ {1994,1993}, + /*PFACC */ {2024,2023}, + /*PFADD */ {2012,2011}, + /*PFCMPEQ */ {2026,2025}, + /*PFCMPGE */ {2002,2001}, + /*PFCMPGT */ {2014,2013}, + /*PFMAX */ {2016,2015}, + /*PFMIN */ {2004,2003}, + /*PFMUL */ {2028,2027}, + /*PFNACC */ {1998,1997}, + /*PFPNACC */ {2000,1999}, + /*PFRCP */ {2006,2005}, + /*PFRCPIT1 */ {2018,2017}, + /*PFRCPIT2 */ {2030,2029}, + /*PFRSQIT1 */ {2020,2019}, + /*PFRSQRT */ {2008,2007}, + /*PFSUB */ {2010,2009}, + /*PFSUBR */ {2022,2021}, + /*PI2FD */ {1992,1991}, + /*PI2FW */ {1990,1989}, + /*PMULHRW */ {2032,2031}, + /*PSWAPD */ {2034,2033}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MMX_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MMX_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW', '3DNOW'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_205(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*SYSCALL_AMD */ {2037}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMD'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IGNORE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_206(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*VMLOAD */ {2041}, + /*VMRUN */ {2039}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_ArAX(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['SVM', 'SVM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_207(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*SKINIT */ {2045}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_EAX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SVM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_208(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*INVLPGA */ {2046}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_ArAX(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_reg1(xes) == XED_REG_ECX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SVM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_209(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*EXTRQ */ {2048,2047}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4a'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[19], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1) && + (xed3_operand_get_imm1(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4a'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_210(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*INSERTQ */ {2050,2049}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4a'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[20], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1) && + (xed3_operand_get_imm1(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4a'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_211(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVNTSD */ {2051}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4a'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_212(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*MOVNTSS */ {2052}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SSE4a'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_213(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*LZCNT */ {2054,2056,2053,2055}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMD'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LZCNT'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMD'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_V); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['LZCNT'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_214(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*PSMASH */ {2065}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_reg0(xes) == XED_REG_RAX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SNP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_215(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*PVALIDATE */ {2066}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_reg0(xes) == XED_REG_RAX) && + (xed3_operand_get_reg1(xes) == XED_REG_ECX) && + (xed3_operand_get_reg2(xes) == XED_REG_EDX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SNP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_216(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*RMPADJUST */ {2067}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_reg0(xes) == XED_REG_RAX) && + (xed3_operand_get_reg1(xes) == XED_REG_RCX) && + (xed3_operand_get_reg2(xes) == XED_REG_RDX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SNP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_217(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*RMPUPDATE */ {2068}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_reg0(xes) == XED_REG_RAX) && + (xed3_operand_get_reg1(xes) == XED_REG_RCX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['SNP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_218(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*INVLPGB */ {2069,2070}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_reg0(xes) == XED_REG_EAX) && + (xed3_operand_get_reg1(xes) == XED_REG_EDX) && + (xed3_operand_get_reg2(xes) == XED_REG_ECX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMD_INVLPGB'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_reg0(xes) == XED_REG_RAX) && + (xed3_operand_get_reg1(xes) == XED_REG_EDX) && + (xed3_operand_get_reg2(xes) == XED_REG_ECX); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMD_INVLPGB'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_219(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[12][2] = { + /*VPMACSDD */ {2129,2128}, + /*VPMACSDQH */ {2131,2130}, + /*VPMACSDQL */ {2083,2082}, + /*VPMACSSDD */ {2125,2124}, + /*VPMACSSDQH */ {2127,2126}, + /*VPMACSSDQL */ {2077,2076}, + /*VPMACSSWD */ {2075,2074}, + /*VPMACSSWW */ {2073,2072}, + /*VPMACSWD */ {2081,2080}, + /*VPMACSWW */ {2079,2078}, + /*VPMADCSSWD */ {2097,2096}, + /*VPMADCSWD */ {2099,2098}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_220(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*VPCMOV */ {2085,2087,2089,2091,2084,2086,2088,2090}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_221(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VPPERM */ {2093,2095,2092,2094}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_222(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][6] = { + /*VPROTB */ {2103,2105,2102,2101,2104,2100}, + /*VPROTD */ {2115,2117,2114,2113,2116,2112}, + /*VPROTQ */ {2121,2123,2120,2119,2122,2118}, + /*VPROTW */ {2109,2111,2108,2107,2110,2106}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_223(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][2] = { + /*VPCOMB */ {2133,2132}, + /*VPCOMD */ {2137,2136}, + /*VPCOMQ */ {2139,2138}, + /*VPCOMUB */ {2141,2140}, + /*VPCOMUD */ {2145,2144}, + /*VPCOMUQ */ {2147,2146}, + /*VPCOMUW */ {2143,2142}, + /*VPCOMW */ {2135,2134}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_224(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VFRCZPD */ {2153,2155,2152,2154}, + /*VFRCZPS */ {2149,2151,2148,2150}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_225(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VFRCZSS */ {2157,2156}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_226(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VFRCZSD */ {2159,2158}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_227(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][4] = { + /*VPSHAB */ {2203,2205,2202,2204}, + /*VPSHAD */ {2211,2213,2210,2212}, + /*VPSHAQ */ {2215,2217,2214,2216}, + /*VPSHAW */ {2207,2209,2206,2208}, + /*VPSHLB */ {2161,2163,2160,2162}, + /*VPSHLD */ {2169,2171,2168,2170}, + /*VPSHLQ */ {2173,2175,2172,2174}, + /*VPSHLW */ {2165,2167,2164,2166}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_228(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[15][2] = { + /*VPHADDBD */ {2179,2178}, + /*VPHADDBQ */ {2181,2180}, + /*VPHADDBW */ {2177,2176}, + /*VPHADDDQ */ {2219,2218}, + /*VPHADDUBD */ {2189,2188}, + /*VPHADDUBQ */ {2191,2190}, + /*VPHADDUBW */ {2187,2186}, + /*VPHADDUDQ */ {2221,2220}, + /*VPHADDUWD */ {2193,2192}, + /*VPHADDUWQ */ {2195,2194}, + /*VPHADDWD */ {2183,2182}, + /*VPHADDWQ */ {2185,2184}, + /*VPHSUBBW */ {2197,2196}, + /*VPHSUBDQ */ {2201,2200}, + /*VPHSUBWD */ {2199,2198}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_229(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*BEXTR_XOP */ {2224,2225,2222,2223}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPRy_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Y) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_230(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[9][4] = { + /*BLCFILL */ {2228,2229,2226,2227}, + /*BLCI */ {2260,2261,2258,2259}, + /*BLCIC */ {2244,2245,2242,2243}, + /*BLCMSK */ {2256,2257,2254,2255}, + /*BLCS */ {2236,2237,2234,2235}, + /*BLSFILL */ {2232,2233,2230,2231}, + /*BLSIC */ {2248,2249,2246,2247}, + /*T1MSKC */ {2252,2253,2250,2251}, + /*TZMSK */ {2240,2241,2238,2239}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPRy_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_N(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Y); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM', 'TBM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_231(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*LLWPCB */ {2262}, + /*SLWPCB */ {2263}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['LWP', 'LWP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_232(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*LWPINS */ {2265,2264}, + /*LWPVAL */ {2267,2266}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['LWP', 'LWP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_VGPRy_N(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['LWP', 'LWP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM32_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_233(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[12][8] = { + /*VFMADDPD */ {2309,2311,2313,2315,2308,2310,2312,2314}, + /*VFMADDPS */ {2301,2303,2305,2307,2300,2302,2304,2306}, + /*VFMADDSUBPD */ {2277,2279,2281,2283,2276,2278,2280,2282}, + /*VFMADDSUBPS */ {2269,2271,2273,2275,2268,2270,2272,2274}, + /*VFMSUBADDPD */ {2293,2295,2297,2299,2292,2294,2296,2298}, + /*VFMSUBADDPS */ {2285,2287,2289,2291,2284,2286,2288,2290}, + /*VFMSUBPD */ {2333,2335,2337,2339,2332,2334,2336,2338}, + /*VFMSUBPS */ {2325,2327,2329,2331,2324,2326,2328,2330}, + /*VFNMADDPD */ {2357,2359,2361,2363,2356,2358,2360,2362}, + /*VFNMADDPS */ {2349,2351,2353,2355,2348,2350,2352,2354}, + /*VFNMSUBPD */ {2381,2383,2385,2387,2380,2382,2384,2386}, + /*VFNMSUBPS */ {2373,2375,2377,2379,2372,2374,2376,2378}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_234(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][4] = { + /*VFMADDSS */ {2317,2319,2316,2318}, + /*VFMSUBSS */ {2341,2343,2340,2342}, + /*VFNMADDSS */ {2365,2367,2364,2366}, + /*VFNMSUBSS */ {2389,2391,2388,2390}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_235(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][4] = { + /*VFMADDSD */ {2321,2323,2320,2322}, + /*VFMSUBSD */ {2345,2347,2344,2346}, + /*VFNMADDSD */ {2369,2371,2368,2370}, + /*VFNMSUBSD */ {2393,2395,2392,2394}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['FMA4', 'FMA4', 'FMA4', 'FMA4'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_236(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][8] = { + /*VPERMIL2PD */ {2405,2409,2407,2411,2404,2408,2406,2410}, + /*VPERMIL2PS */ {2397,2401,2399,2403,2396,2400,2398,2402}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[28], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[28], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['XOP', 'XOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_237(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*BNDMK */ {2412}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_AGEN) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_agen(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_238(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][3] = { + /*BNDCL */ {2415,2414,2413}, + /*BNDCN */ {2421,2420,2419}, + /*BNDCU */ {2418,2417,2416}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['MPX', 'MPX', 'MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['MPX', 'MPX', 'MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_AGEN) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_agen(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['MPX', 'MPX', 'MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_239(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*BNDMOV */ {2426,2422,2427,2423,2428,2424,2429,2425}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_BND_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_BND_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_easz(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_easz(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_240(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*BNDLDX */ {2430,2431,2432,2433}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_easz(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND32); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND64); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND64); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND64); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_241(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*BNDSTX */ {2434,2435,2436,2437}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND32) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND64) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND64) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mpxmode(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_BND64) && + xed_encode_ntluf_BND_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MPX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_242(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*INCSSPD */ {2441}, + /*RDSSPD */ {2443}, + /*TPAUSE */ {2493}, + /*UMWAIT */ {2495}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['CET', 'CET', 'WAITPKG', 'WAITPKG'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_243(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*INCSSPQ */ {2442}, + /*RDSSPQ */ {2444}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['CET', 'CET'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_244(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*WRSSD */ {2448}, + /*WRUSSD */ {2450}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['CET', 'CET'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_245(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*WRSSQ */ {2449}, + /*WRUSSQ */ {2451}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['CET', 'CET'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_246(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*RDRAND */ {2452}, + /*RDSEED */ {2476}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRv_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['RDRAND', 'RDSEED'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_247(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*GF2P8AFFINEINVQB*/ {6962,6963}, + /*GF2P8AFFINEQB */ {6964,6965}, + /*SHA1RNDS4 */ {2459,2460}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SHA', 'GFNI', 'GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['SHA', 'GFNI', 'GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_248(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*CLFLUSHOPT */ {2475}, + /*CLWB */ {5460}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_MPREFETCH); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['CLFLUSHOPT', 'CLWB'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_REFINING66_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_249(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*RDFSBASE */ {2477}, + /*RDGSBASE */ {2478}, + /*WRFSBASE */ {2479}, + /*WRGSBASE */ {2480}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPRy_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['RDWRFSGS', 'RDWRFSGS', 'RDWRFSGS', 'RDWRFSGS'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_250(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*RDPID */ {2485,2486}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['RDPID'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['RDPID'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_251(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*PTWRITE */ {2487,2488}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPRy_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PTWRITE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Y); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['PTWRITE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_252(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*MOVDIR64B */ {2489,2490}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_A_GPR_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MOVDIR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_A_GPR_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MOVDIR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_253(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*MOVDIRI */ {2491,2492}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MOVDIR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['MOVDIR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_254(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*UMONITOR */ {2494}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_A_GPR_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['WAITPKG'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_255(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[22][11] = { + /*VADDPD */ {2503,2499,2501,2498,2500,2505,2507,2502,2506,2508,2504}, + /*VDIVPD */ {2819,2815,2817,2814,2816,2821,2823,2818,2822,2824,2820}, + /*VFMADD132PD */ {4656,4652,4654,4651,4653,4658,4660,4655,4659,4661,4657}, + /*VFMADD213PD */ {4688,4684,4686,4683,4685,4690,4692,4687,4691,4693,4689}, + /*VFMADD231PD */ {4720,4716,4718,4715,4717,4722,4724,4719,4723,4725,4721}, + /*VFMADDSUB132PD*/ {4752,4748,4750,4747,4749,4754,4756,4751,4755,4757,4753}, + /*VFMADDSUB213PD*/ {4763,4759,4761,4758,4760,4765,4767,4762,4766,4768,4764}, + /*VFMADDSUB231PD*/ {4774,4770,4772,4769,4771,4776,4778,4773,4777,4779,4775}, + /*VFMSUB132PD */ {4884,4880,4882,4879,4881,4886,4888,4883,4887,4889,4885}, + /*VFMSUB213PD */ {4916,4912,4914,4911,4913,4918,4920,4915,4919,4921,4917}, + /*VFMSUB231PD */ {4948,4944,4946,4943,4945,4950,4952,4947,4951,4953,4949}, + /*VFMSUBADD132PD*/ {4818,4814,4816,4813,4815,4820,4822,4817,4821,4823,4819}, + /*VFMSUBADD213PD*/ {4829,4825,4827,4824,4826,4831,4833,4828,4832,4834,4830}, + /*VFMSUBADD231PD*/ {4840,4836,4838,4835,4837,4842,4844,4839,4843,4845,4841}, + /*VFNMADD132PD */ {4980,4976,4978,4975,4977,4982,4984,4979,4983,4985,4981}, + /*VFNMADD213PD */ {5012,5008,5010,5007,5009,5014,5016,5011,5015,5017,5013}, + /*VFNMADD231PD */ {5044,5040,5042,5039,5041,5046,5048,5043,5047,5049,5045}, + /*VFNMSUB132PD */ {5076,5072,5074,5071,5073,5078,5080,5075,5079,5081,5077}, + /*VFNMSUB213PD */ {5108,5104,5106,5103,5105,5110,5112,5107,5111,5113,5109}, + /*VFNMSUB231PD */ {5140,5136,5138,5135,5137,5142,5144,5139,5143,5145,5141}, + /*VMULPD */ {4040,4036,4038,4035,4037,4042,4044,4039,4043,4045,4041}, + /*VSUBPD */ {4008,4004,4006,4003,4005,4010,4012,4007,4011,4013,4009}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_256(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[22][11] = { + /*VADDPS */ {2514,2510,2512,2509,2511,2516,2518,2513,2517,2519,2515}, + /*VDIVPS */ {2830,2826,2828,2825,2827,2832,2834,2829,2833,2835,2831}, + /*VFMADD132PS */ {4667,4663,4665,4662,4664,4669,4671,4666,4670,4672,4668}, + /*VFMADD213PS */ {4699,4695,4697,4694,4696,4701,4703,4698,4702,4704,4700}, + /*VFMADD231PS */ {4731,4727,4729,4726,4728,4733,4735,4730,4734,4736,4732}, + /*VFMADDSUB132PS*/ {4785,4781,4783,4780,4782,4787,4789,4784,4788,4790,4786}, + /*VFMADDSUB213PS*/ {4796,4792,4794,4791,4793,4798,4800,4795,4799,4801,4797}, + /*VFMADDSUB231PS*/ {4807,4803,4805,4802,4804,4809,4811,4806,4810,4812,4808}, + /*VFMSUB132PS */ {4895,4891,4893,4890,4892,4897,4899,4894,4898,4900,4896}, + /*VFMSUB213PS */ {4927,4923,4925,4922,4924,4929,4931,4926,4930,4932,4928}, + /*VFMSUB231PS */ {4959,4955,4957,4954,4956,4961,4963,4958,4962,4964,4960}, + /*VFMSUBADD132PS*/ {4851,4847,4849,4846,4848,4853,4855,4850,4854,4856,4852}, + /*VFMSUBADD213PS*/ {4862,4858,4860,4857,4859,4864,4866,4861,4865,4867,4863}, + /*VFMSUBADD231PS*/ {4873,4869,4871,4868,4870,4875,4877,4872,4876,4878,4874}, + /*VFNMADD132PS */ {4991,4987,4989,4986,4988,4993,4995,4990,4994,4996,4992}, + /*VFNMADD213PS */ {5023,5019,5021,5018,5020,5025,5027,5022,5026,5028,5024}, + /*VFNMADD231PS */ {5055,5051,5053,5050,5052,5057,5059,5054,5058,5060,5056}, + /*VFNMSUB132PS */ {5087,5083,5085,5082,5084,5089,5091,5086,5090,5092,5088}, + /*VFNMSUB213PS */ {5119,5115,5117,5114,5116,5121,5123,5118,5122,5124,5120}, + /*VFNMSUB231PS */ {5151,5147,5149,5146,5148,5153,5155,5150,5154,5156,5152}, + /*VMULPS */ {4051,4047,4049,4046,4048,4053,4055,4050,4054,4056,4052}, + /*VSUBPS */ {4019,4015,4017,4014,4016,4021,4023,4018,4022,4024,4020}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_257(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[18][5] = { + /*VADDSD */ {2523,2521,2520,2522,2524}, + /*VCVTSD2SS */ {2779,2777,2776,2778,2780}, + /*VDIVSD */ {2839,2837,2836,2838,2840}, + /*VFMADD132SD */ {4676,4674,4673,4675,4677}, + /*VFMADD213SD */ {4708,4706,4705,4707,4709}, + /*VFMADD231SD */ {4740,4738,4737,4739,4741}, + /*VFMSUB132SD */ {4904,4902,4901,4903,4905}, + /*VFMSUB213SD */ {4936,4934,4933,4935,4937}, + /*VFMSUB231SD */ {4968,4966,4965,4967,4969}, + /*VFNMADD132SD */ {5000,4998,4997,4999,5001}, + /*VFNMADD213SD */ {5032,5030,5029,5031,5033}, + /*VFNMADD231SD */ {5064,5062,5061,5063,5065}, + /*VFNMSUB132SD */ {5096,5094,5093,5095,5097}, + /*VFNMSUB213SD */ {5128,5126,5125,5127,5129}, + /*VFNMSUB231SD */ {5160,5158,5157,5159,5161}, + /*VMULSD */ {4060,4058,4057,4059,4061}, + /*VSQRTSD */ {3976,3974,3973,3975,3977}, + /*VSUBSD */ {4028,4026,4025,4027,4029}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_258(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[17][5] = { + /*VADDSS */ {2528,2526,2525,2527,2529}, + /*VDIVSS */ {2844,2842,2841,2843,2845}, + /*VFMADD132SS */ {4681,4679,4678,4680,4682}, + /*VFMADD213SS */ {4713,4711,4710,4712,4714}, + /*VFMADD231SS */ {4745,4743,4742,4744,4746}, + /*VFMSUB132SS */ {4909,4907,4906,4908,4910}, + /*VFMSUB213SS */ {4941,4939,4938,4940,4942}, + /*VFMSUB231SS */ {4973,4971,4970,4972,4974}, + /*VFNMADD132SS */ {5005,5003,5002,5004,5006}, + /*VFNMADD213SS */ {5037,5035,5034,5036,5038}, + /*VFNMADD231SS */ {5069,5067,5066,5068,5070}, + /*VFNMSUB132SS */ {5101,5099,5098,5100,5102}, + /*VFNMSUB213SS */ {5133,5131,5130,5132,5134}, + /*VFNMSUB231SS */ {5165,5163,5162,5164,5166}, + /*VMULSS */ {4065,4063,4062,4064,4066}, + /*VSQRTSS */ {3981,3979,3978,3980,3982}, + /*VSUBSS */ {4033,4031,4030,4032,4034}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA', 'FMA'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_259(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[19][4] = { + /*VADDSUBPD */ {2531,2533,2530,2532}, + /*VADDSUBPS */ {2535,2537,2534,2536}, + /*VHADDPD */ {2861,2863,2860,2862}, + /*VHADDPS */ {2865,2867,2864,2866}, + /*VHSUBPD */ {2869,2871,2868,2870}, + /*VHSUBPS */ {2873,2875,2872,2874}, + /*VPAND */ {3150,3152,3149,3151}, + /*VPANDN */ {3154,3156,3153,3155}, + /*VPHADDD */ {3592,3594,3591,3593}, + /*VPHADDSW */ {3596,3598,3595,3597}, + /*VPHADDW */ {3588,3590,3587,3589}, + /*VPHSUBD */ {3604,3606,3603,3605}, + /*VPHSUBSW */ {3608,3610,3607,3609}, + /*VPHSUBW */ {3600,3602,3599,3601}, + /*VPOR */ {3146,3148,3145,3147}, + /*VPSIGNB */ {3702,3704,3701,3703}, + /*VPSIGND */ {3710,3712,3709,3711}, + /*VPSIGNW */ {3706,3708,3705,3707}, + /*VPXOR */ {3158,3160,3157,3159}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_260(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[14][10] = { + /*VANDNPD */ {2559,2561,2558,2560,2562,2564,2566,2563,2565,2567}, + /*VANDPD */ {2539,2541,2538,2540,2542,2544,2546,2543,2545,2547}, + /*VORPD */ {4068,4070,4067,4069,4071,4073,4075,4072,4074,4076}, + /*VPADDQ */ {3438,3440,3437,3439,3443,3445,3441,3444,3446,3442}, + /*VPMULDQ */ {3672,3674,3671,3673,3677,3679,3675,3678,3680,3676}, + /*VPMULUDQ */ {3662,3664,3661,3663,3667,3669,3665,3668,3670,3666}, + /*VPSLLVQ */ {5324,5326,5323,5325,5329,5331,5327,5330,5332,5328}, + /*VPSRLVQ */ {5344,5346,5343,5345,5349,5351,5347,5350,5352,5348}, + /*VPSUBQ */ {3784,3786,3783,3785,3789,3791,3787,3790,3792,3788}, + /*VPUNPCKHQDQ */ {3824,3826,3823,3825,3829,3831,3827,3830,3832,3828}, + /*VPUNPCKLQDQ */ {3864,3866,3863,3865,3869,3871,3867,3870,3872,3868}, + /*VUNPCKHPD */ {3984,3986,3983,3985,3989,3991,3987,3990,3992,3988}, + /*VUNPCKLPD */ {4242,4244,4241,4243,4247,4249,4245,4248,4250,4246}, + /*VXORPD */ {4262,4264,4261,4263,4265,4267,4269,4266,4268,4270}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_261(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[24][10] = { + /*VANDNPS */ {2569,2571,2568,2570,2572,2574,2576,2573,2575,2577}, + /*VANDPS */ {2549,2551,2548,2550,2552,2554,2556,2553,2555,2557}, + /*VORPS */ {4078,4080,4077,4079,4081,4083,4085,4082,4084,4086}, + /*VPACKSSDW */ {3234,3236,3233,3235,3237,3239,3241,3238,3240,3242}, + /*VPACKUSDW */ {3254,3256,3253,3255,3257,3259,3261,3258,3260,3262}, + /*VPADDD */ {3428,3430,3427,3429,3433,3435,3431,3434,3436,3432}, + /*VPDPBUSD */ {5467,5469,5468,5470,5461,5463,5465,5462,5464,5466}, + /*VPDPBUSDS */ {5477,5479,5478,5480,5471,5473,5475,5472,5474,5476}, + /*VPDPWSSD */ {5487,5489,5488,5490,5481,5483,5485,5482,5484,5486}, + /*VPDPWSSDS */ {5497,5499,5498,5500,5491,5493,5495,5492,5494,5496}, + /*VPMAXSD */ {4108,4110,4107,4109,4113,4115,4111,4114,4116,4112}, + /*VPMAXUD */ {4138,4140,4137,4139,4143,4145,4141,4144,4146,4142}, + /*VPMINSD */ {4168,4170,4167,4169,4173,4175,4171,4174,4176,4172}, + /*VPMINUD */ {4198,4200,4197,4199,4203,4205,4201,4204,4206,4202}, + /*VPMULLD */ {3652,3654,3651,3653,3657,3659,3655,3658,3660,3656}, + /*VPSLLVD */ {5314,5316,5313,5315,5319,5321,5317,5320,5322,5318}, + /*VPSRAVD */ {5354,5356,5353,5355,5359,5361,5357,5360,5362,5358}, + /*VPSRLVD */ {5334,5336,5333,5335,5339,5341,5337,5340,5342,5338}, + /*VPSUBD */ {3774,3776,3773,3775,3779,3781,3777,3780,3782,3778}, + /*VPUNPCKHDQ */ {3814,3816,3813,3815,3819,3821,3817,3820,3822,3818}, + /*VPUNPCKLDQ */ {3854,3856,3853,3855,3859,3861,3857,3860,3862,3858}, + /*VUNPCKHPS */ {3994,3996,3993,3995,3999,4001,3997,4000,4002,3998}, + /*VUNPCKLPS */ {4252,4254,4251,4253,4257,4259,4255,4258,4260,4256}, + /*VXORPS */ {4272,4274,4271,4273,4275,4277,4279,4276,4278,4280}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI', 'AVX_VNNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512_VNNI_128', 'AVX512_VNNI_128', 'AVX512_VNNI_128', 'AVX512_VNNI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512_VNNI_256', 'AVX512_VNNI_256', 'AVX512_VNNI_256', 'AVX512_VNNI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512_VNNI_512', 'AVX512_VNNI_512', 'AVX512_VNNI_512', 'AVX512_VNNI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512_VNNI_128', 'AVX512_VNNI_128', 'AVX512_VNNI_128', 'AVX512_VNNI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512_VNNI_256', 'AVX512_VNNI_256', 'AVX512_VNNI_256', 'AVX512_VNNI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512_VNNI_512', 'AVX512_VNNI_512', 'AVX512_VNNI_512', 'AVX512_VNNI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_262(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][4] = { + /*VBLENDPD */ {2579,2581,2578,2580}, + /*VBLENDPS */ {2583,2585,2582,2584}, + /*VDPPS */ {2851,2853,2850,2852}, + /*VMPSADBW */ {4228,4230,4227,4229}, + /*VPBLENDD */ {5254,5256,5253,5255}, + /*VPBLENDW */ {3904,3906,3903,3905}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_263(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCMPPD */ {2591,2587,2589,2586,2588,2593,2595,2590,2594,2596,2592}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_264(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCMPPS */ {2602,2598,2600,2597,2599,2604,2606,2601,2605,2607,2603}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_265(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*VCMPSD */ {2611,2609,2608,2610,2612}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_266(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*VCMPSS */ {2616,2614,2613,2615,2617}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_267(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VCOMISD */ {2621,2619,2618,2620,2622}, + /*VUCOMISD */ {4234,4232,4231,4233,4235}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_268(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VCOMISS */ {2626,2624,2623,2625,2627}, + /*VUCOMISS */ {4239,4237,4236,4238,4240}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_269(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCVTDQ2PD */ {2633,2629,2631,2628,2630,2635,2637,2632,2636,2638,2634}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_270(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][11] = { + /*VCVTDQ2PS */ {2644,2640,2642,2639,2641,2646,2648,2643,2647,2649,2645}, + /*VCVTPS2DQ */ {2688,2684,2686,2683,2685,2690,2692,2687,2691,2693,2689}, + /*VSQRTPS */ {3967,3963,3965,3962,3964,3969,3971,3966,3970,3972,3968}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_271(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][11] = { + /*VCVTPD2DQ */ {2655,2651,2653,2650,2652,2657,2659,2654,2658,2660,2656}, + /*VCVTPD2PS */ {2677,2673,2675,2672,2674,2679,2681,2676,2680,2682,2678}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_272(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCVTTPD2DQ */ {2666,2662,2664,2661,2663,2668,2670,2665,2669,2671,2667}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_273(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCVTTPS2DQ */ {2699,2695,2697,2694,2696,2701,2703,2698,2702,2704,2700}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_274(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCVTPS2PD */ {2710,2706,2708,2705,2707,2712,2714,2709,2713,2715,2711}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_275(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][15] = { + /*VCVTSD2SI */ {2724,2725,2729,2717,2719,2721,2716,2718,2720,2722,2723,2728,2726,2727,2730}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_276(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][15] = { + /*VCVTTSD2SI */ {2739,2740,2744,2732,2734,2736,2731,2733,2735,2737,2738,2743,2741,2742,2745}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_277(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][15] = { + /*VCVTSS2SI */ {2754,2755,2759,2747,2749,2751,2746,2748,2750,2752,2753,2758,2756,2757,2760}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_278(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][15] = { + /*VCVTTSS2SI */ {2769,2770,2774,2762,2764,2766,2761,2763,2765,2767,2768,2773,2771,2772,2775}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_279(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][13] = { + /*VCVTSI2SD */ {2792,2782,2784,2786,2781,2783,2785,2787,2788,2791,2789,2790,2793}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_280(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][15] = { + /*VCVTSI2SS */ {2802,2803,2807,2795,2797,2799,2794,2796,2798,2800,2801,2806,2804,2805,2808}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_281(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][5] = { + /*VCVTSS2SD */ {2812,2810,2809,2811,2813}, + /*VMAXSS */ {2993,2991,2990,2992,2994}, + /*VMINSS */ {3025,3023,3022,3024,3026}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_282(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VEXTRACTF128 */ {2847,2846}, + /*VEXTRACTI128 */ {5210,5209}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_283(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VDPPD */ {2849,2848}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_284(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VEXTRACTPS */ {2855,2854,2856,2857}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_285(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*VZEROALL */ {2858}, + /*VZEROUPPER */ {2859}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_286(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][20] = { + /*VPERMILPD */ {2877,2879,2881,2876,2883,2878,2880,2882,2890,2894,2886,2888,2892,2884,2891,2895,2887,2889,2893,2885}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_287(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][20] = { + /*VPERMILPS */ {2897,2899,2901,2896,2903,2898,2900,2902,2910,2914,2906,2908,2912,2904,2911,2915,2907,2909,2913,2905}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_288(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VPERM2F128 */ {2917,2916}, + /*VPERM2I128 */ {5220,5219}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_289(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VBROADCASTSS */ {2920,2921,2918,2919,2925,2927,2923,2924,2926,2922}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_290(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VBROADCASTSD */ {2929,2928,2933,2931,2932,2930}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_291(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*VBROADCASTF128*/ {2934}, + /*VBROADCASTI128*/ {5312}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_292(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VINSERTF128 */ {2936,2935}, + /*VINSERTI128 */ {5208,5207}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_293(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VINSERTPS */ {2938,2937,2939,2940}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_294(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VLDDQU */ {2941,2942}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_295(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][4] = { + /*VMASKMOVPD */ {2949,2947,2950,2948}, + /*VMASKMOVPS */ {2945,2943,2946,2944}, + /*VPMASKMOVD */ {5213,5211,5214,5212}, + /*VPMASKMOVQ */ {5217,5215,5218,5216}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX', 'AVX', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_296(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][4] = { + /*VPTEST */ {2952,2954,2951,2953}, + /*VRCPPS */ {3940,3942,3939,3941}, + /*VRSQRTPS */ {3946,3948,3945,3947}, + /*VTESTPD */ {2960,2962,2959,2961}, + /*VTESTPS */ {2956,2958,2955,2957}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_297(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][11] = { + /*VMAXPD */ {2968,2964,2966,2963,2965,2970,2972,2967,2971,2973,2969}, + /*VMINPD */ {3000,2996,2998,2995,2997,3002,3004,2999,3003,3005,3001}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_298(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][11] = { + /*VMAXPS */ {2979,2975,2977,2974,2976,2981,2983,2978,2982,2984,2980}, + /*VMINPS */ {3011,3007,3009,3006,3008,3013,3015,3010,3014,3016,3012}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_299(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VMAXSD */ {2988,2986,2985,2987,2989}, + /*VMINSD */ {3020,3018,3017,3019,3021}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_300(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][20] = { + /*VMOVAPD */ {3030,3028,3034,3032,3029,3027,3033,3031,3041,3039,3045,3043,3037,3035,3042,3040,3046,3044,3038,3036}, + /*VMOVUPD */ {4300,4298,4304,4302,4299,4297,4303,4301,4311,4309,4315,4313,4307,4305,4312,4310,4316,4314,4308,4306}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_301(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][20] = { + /*VMOVAPS */ {3050,3048,3054,3052,3049,3047,3053,3051,3061,3059,3065,3063,3057,3055,3062,3060,3066,3064,3058,3056}, + /*VMOVUPS */ {4320,4318,4324,4322,4319,4317,4323,4321,4331,4329,4335,4333,4327,4325,4332,4330,4336,4334,4328,4326}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][18]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][19]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_302(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][16] = { + /*VMOVD */ {3070,3068,3074,3072,3069,3067,3073,3071,3079,3075,3080,3076,3081,3077,3082,3078}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_303(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][16] = { + /*VMOVQ */ {3086,3084,3090,3088,3085,3083,3089,3087,3093,3091,3097,3095,3098,3094,3092,3096}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_304(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VMOVDDUP */ {3100,3102,3099,3101,3105,3107,3103,3106,3108,3104}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MOVDDUP_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MOVDDUP_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MOVDDUP_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_305(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][8] = { + /*VMOVDQA */ {3112,3110,3116,3114,3111,3109,3115,3113}, + /*VMOVDQU */ {3122,3118,3124,3120,3121,3117,3123,3119}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_306(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VMOVSHDUP */ {3126,3128,3125,3127,3131,3133,3129,3132,3134,3130}, + /*VMOVSLDUP */ {3136,3138,3135,3137,3141,3143,3139,3142,3144,3140}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_307(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPABSB */ {3162,3164,3161,3163,3165,3167,3169,3166,3168,3170}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_308(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPABSW */ {3172,3174,3171,3173,3175,3177,3179,3176,3178,3180}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_309(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPABSD */ {3182,3184,3181,3183,3187,3189,3185,3188,3190,3186}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_310(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VAESIMC */ {4617,4618}, + /*VPHMINPOSUW */ {3192,3191}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVXAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVXAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_311(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPSHUFD */ {3194,3196,3193,3195,3199,3201,3197,3200,3202,3198}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_312(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPSHUFHW */ {3204,3206,3203,3205,3207,3209,3211,3208,3210,3212}, + /*VPSHUFLW */ {3214,3216,3213,3215,3217,3219,3221,3218,3220,3222}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_313(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[21][10] = { + /*VPACKSSWB */ {3224,3226,3223,3225,3227,3229,3231,3228,3230,3232}, + /*VPACKUSWB */ {3244,3246,3243,3245,3247,3249,3251,3248,3250,3252}, + /*VPADDSW */ {3458,3460,3457,3459,3461,3463,3465,3462,3464,3466}, + /*VPADDUSW */ {3478,3480,3477,3479,3481,3483,3485,3482,3484,3486}, + /*VPADDW */ {3418,3420,3417,3419,3421,3423,3425,3422,3424,3426}, + /*VPAVGW */ {3498,3500,3497,3499,3501,3503,3505,3502,3504,3506}, + /*VPMADDUBSW */ {4218,4220,4217,4219,4221,4223,4225,4222,4224,4226}, + /*VPMADDWD */ {4208,4210,4207,4209,4211,4213,4215,4212,4214,4216}, + /*VPMAXSW */ {4098,4100,4097,4099,4101,4103,4105,4102,4104,4106}, + /*VPMAXUW */ {4128,4130,4127,4129,4131,4133,4135,4132,4134,4136}, + /*VPMINSW */ {4158,4160,4157,4159,4161,4163,4165,4162,4164,4166}, + /*VPMINUW */ {4188,4190,4187,4189,4191,4193,4195,4192,4194,4196}, + /*VPMULHRSW */ {3622,3624,3621,3623,3625,3627,3629,3626,3628,3630}, + /*VPMULHUW */ {3612,3614,3611,3613,3615,3617,3619,3616,3618,3620}, + /*VPMULHW */ {3632,3634,3631,3633,3635,3637,3639,3636,3638,3640}, + /*VPMULLW */ {3642,3644,3641,3643,3645,3647,3649,3646,3648,3650}, + /*VPSUBSW */ {3724,3726,3723,3725,3727,3729,3731,3728,3730,3732}, + /*VPSUBUSW */ {3744,3746,3743,3745,3747,3749,3751,3748,3750,3752}, + /*VPSUBW */ {3764,3766,3763,3765,3767,3769,3771,3768,3770,3772}, + /*VPUNPCKHWD */ {3804,3806,3803,3805,3807,3809,3811,3808,3810,3812}, + /*VPUNPCKLWD */ {3844,3846,3843,3845,3847,3849,3851,3848,3850,3852}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_314(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][18] = { + /*VPSLLW */ {3264,3267,3265,3263,3268,3266,3269,3273,3277,3271,3275,3279,3270,3274,3278,3272,3276,3280}, + /*VPSRAW */ {3372,3375,3373,3371,3376,3374,3377,3381,3385,3379,3383,3387,3378,3382,3386,3380,3384,3388}, + /*VPSRLW */ {3318,3321,3319,3317,3322,3320,3323,3327,3331,3325,3329,3333,3324,3328,3332,3326,3330,3334}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_315(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][18] = { + /*VPSLLD */ {3282,3285,3283,3281,3286,3284,3291,3295,3287,3293,3297,3289,3292,3296,3288,3294,3298,3290}, + /*VPSRAD */ {3390,3393,3391,3389,3394,3392,3399,3403,3395,3401,3405,3397,3400,3404,3396,3402,3406,3398}, + /*VPSRLD */ {3336,3339,3337,3335,3340,3338,3345,3349,3341,3347,3351,3343,3346,3350,3342,3348,3352,3344}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_316(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][18] = { + /*VPSLLQ */ {3300,3303,3301,3299,3304,3302,3309,3313,3305,3311,3315,3307,3310,3314,3306,3312,3316,3308}, + /*VPSRLQ */ {3354,3357,3355,3353,3358,3356,3363,3367,3359,3365,3369,3361,3364,3368,3360,3366,3370,3362}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][16]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][17]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_317(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[15][10] = { + /*VGF2P8MULB */ {6994,6996,6995,6997,6988,6990,6992,6989,6991,6993}, + /*VPADDB */ {3408,3410,3407,3409,3411,3413,3415,3412,3414,3416}, + /*VPADDSB */ {3448,3450,3447,3449,3451,3453,3455,3452,3454,3456}, + /*VPADDUSB */ {3468,3470,3467,3469,3471,3473,3475,3472,3474,3476}, + /*VPAVGB */ {3488,3490,3487,3489,3491,3493,3495,3492,3494,3496}, + /*VPMAXSB */ {4088,4090,4087,4089,4091,4093,4095,4092,4094,4096}, + /*VPMAXUB */ {4118,4120,4117,4119,4121,4123,4125,4122,4124,4126}, + /*VPMINSB */ {4148,4150,4147,4149,4151,4153,4155,4152,4154,4156}, + /*VPMINUB */ {4178,4180,4177,4179,4181,4183,4185,4182,4184,4186}, + /*VPSHUFB */ {3692,3694,3691,3693,3695,3697,3699,3696,3698,3700}, + /*VPSUBB */ {3754,3756,3753,3755,3757,3759,3761,3758,3760,3762}, + /*VPSUBSB */ {3714,3716,3713,3715,3717,3719,3721,3718,3720,3722}, + /*VPSUBUSB */ {3734,3736,3733,3735,3737,3739,3741,3738,3740,3742}, + /*VPUNPCKHBW */ {3794,3796,3793,3795,3797,3799,3801,3798,3800,3802}, + /*VPUNPCKLBW */ {3834,3836,3833,3835,3837,3839,3841,3838,3840,3842}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX2', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512_GFNI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512_GFNI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512_GFNI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512_GFNI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512_GFNI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512_GFNI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_318(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPCMPEQB */ {3508,3510,3507,3509,3511,3513,3515,3512,3514,3516}, + /*VPCMPGTB */ {3548,3550,3547,3549,3551,3553,3555,3552,3554,3556}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_319(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPCMPEQW */ {3518,3520,3517,3519,3521,3523,3525,3522,3524,3526}, + /*VPCMPGTW */ {3558,3560,3557,3559,3561,3563,3565,3562,3564,3566}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_320(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPCMPEQD */ {3528,3530,3527,3529,3533,3535,3531,3534,3536,3532}, + /*VPCMPGTD */ {3568,3570,3567,3569,3573,3575,3571,3574,3576,3572}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_321(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPCMPEQQ */ {3538,3540,3537,3539,3543,3545,3541,3544,3546,3542}, + /*VPCMPGTQ */ {3578,3580,3577,3579,3583,3585,3581,3584,3586,3582}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_322(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPSADBW */ {3682,3684,3681,3683,3685,3687,3689,3686,3688,3690}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_323(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][8] = { + /*VPSLLDQ */ {3881,3882,3883,3885,3887,3884,3886,3888}, + /*VPSRLDQ */ {3873,3874,3875,3877,3879,3876,3878,3880}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_324(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VMOVHLPS */ {3891,3892}, + /*VMOVLHPS */ {3889,3890}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128N', 'AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_325(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPALIGNR */ {3894,3896,3893,3895,3897,3899,3901,3898,3900,3902}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_326(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VROUNDPD */ {3908,3910,3907,3909}, + /*VROUNDPS */ {3912,3914,3911,3913}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_327(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VROUNDSD */ {3916,3915}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_328(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VROUNDSS */ {3918,3917}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_329(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][10] = { + /*VGF2P8AFFINEINVQB*/ {6974,6976,6975,6977,6968,6970,6972,6969,6971,6973}, + /*VGF2P8AFFINEQB*/ {6984,6986,6985,6987,6978,6980,6982,6979,6981,6983}, + /*VSHUFPD */ {3920,3922,3919,3921,3925,3927,3923,3926,3928,3924}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX_GFNI', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX_GFNI', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX_GFNI', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX_GFNI', 'AVX_GFNI'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512_GFNI_128', 'AVX512_GFNI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512_GFNI_256', 'AVX512_GFNI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512_GFNI_512', 'AVX512_GFNI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512_GFNI_128', 'AVX512_GFNI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512_GFNI_256', 'AVX512_GFNI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512_GFNI_512', 'AVX512_GFNI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_330(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VSHUFPS */ {3930,3932,3929,3931,3935,3937,3933,3936,3938,3934}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_331(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VRCPSS */ {3944,3943}, + /*VRSQRTSS */ {3950,3949}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_332(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VSQRTPD */ {3956,3952,3954,3951,3953,3958,3960,3955,3959,3961,3957}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_333(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*VMOVSS */ {4284,4282,4283,4281,4288,4287,4286,4285}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_334(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*VMOVSD */ {4292,4290,4291,4289,4296,4295,4294,4293}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_335(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VMOVHPD */ {4346,4345,4348,4347}, + /*VMOVLPD */ {4338,4337,4340,4339}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128N', 'AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128N', 'AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_336(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VMOVHPS */ {4350,4349,4352,4351}, + /*VMOVLPS */ {4342,4341,4344,4343}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128N', 'AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128N', 'AVX512F_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_337(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*VMOVMSKPD */ {4353,4354}, + /*VMOVMSKPS */ {4355,4356}, + /*VPMOVMSKB */ {4357,4358}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_338(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPMOVSXBW */ {4359,4361,4360,4362,4363,4365,4367,4364,4366,4368}, + /*VPMOVZXBW */ {4419,4421,4420,4422,4423,4425,4427,4424,4426,4428}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_339(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPMOVSXBD */ {4369,4371,4370,4372,4375,4377,4373,4376,4378,4374}, + /*VPMOVZXBD */ {4429,4431,4430,4432,4435,4437,4433,4436,4438,4434}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_340(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPMOVSXBQ */ {4379,4381,4380,4382,4385,4387,4383,4386,4388,4384}, + /*VPMOVZXBQ */ {4439,4441,4440,4442,4445,4447,4443,4446,4448,4444}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_341(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPMOVSXWD */ {4389,4391,4390,4392,4395,4397,4393,4396,4398,4394}, + /*VPMOVZXWD */ {4449,4451,4450,4452,4455,4457,4453,4456,4458,4454}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_342(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPMOVSXWQ */ {4399,4401,4400,4402,4405,4407,4403,4406,4408,4404}, + /*VPMOVZXWQ */ {4459,4461,4460,4462,4465,4467,4463,4466,4468,4464}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_343(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPMOVSXDQ */ {4409,4411,4410,4412,4415,4417,4413,4416,4418,4414}, + /*VPMOVZXDQ */ {4469,4471,4470,4472,4475,4477,4473,4476,4478,4474}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_344(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VPEXTRB */ {4480,4479,4481,4482}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BYTE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_345(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*VPEXTRW */ {4484,4485,4483,4486,4487}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_WORD_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_346(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VPEXTRQ */ {4489,4488,4490,4491}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_347(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*VPEXTRD */ {4495,4493,4494,4492,4496,4497,4498,4499}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_348(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VPINSRB */ {4501,4500,4502,4503}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BYTE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_349(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VPINSRW */ {4505,4504,4506,4507}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_WORD_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_350(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][8] = { + /*VPINSRD */ {4511,4509,4510,4508,4512,4513,4514,4515}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_351(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VPINSRQ */ {4517,4516,4518,4519}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_352(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][4] = { + /*VPCMPESTRI */ {4521,4523,4520,4522}, + /*VPCMPESTRM */ {4533,4535,4532,4534}, + /*VPCMPISTRI */ {4527,4529,4526,4528}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_353(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][2] = { + /*VPCMPESTRI64 */ {4525,4524}, + /*VPCMPESTRM64 */ {4537,4536}, + /*VPCMPISTRI64 */ {4531,4530}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_354(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VAESKEYGENASSIST*/ {4575,4576}, + /*VPCMPISTRM */ {4539,4538}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVXAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVXAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_355(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*VMASKMOVDQU */ {4540}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_356(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*VLDMXCSR */ {4541}, + /*VSTMXCSR */ {4542}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_357(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][4] = { + /*VBLENDVPD */ {4548,4550,4547,4549}, + /*VBLENDVPS */ {4552,4554,4551,4553}, + /*VPBLENDVB */ {4544,4546,4543,4545}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[21], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_SE(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX2', 'AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SE_IMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_358(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*VMOVNTDQA */ {4555,4556,4558,4559,4557}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_359(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VMOVNTDQ */ {4560,4561,4563,4564,4562}, + /*VMOVNTPS */ {4570,4571,4573,4574,4572}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX', 'AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_360(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*VMOVNTPD */ {4565,4566,4568,4569,4567}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_361(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][10] = { + /*VAESDEC */ {4597,4605,4598,4606,4599,4601,4603,4600,4602,4604}, + /*VAESDECLAST */ {4607,4615,4608,4616,4609,4611,4613,4610,4612,4614}, + /*VAESENC */ {4577,4585,4578,4586,4579,4581,4583,4580,4582,4584}, + /*VAESENCLAST */ {4587,4595,4588,4596,4589,4591,4593,4590,4592,4594}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVXAES', 'AVXAES', 'AVXAES', 'AVXAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['VAES', 'VAES', 'VAES', 'VAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVXAES', 'AVXAES', 'AVXAES', 'AVXAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['VAES', 'VAES', 'VAES', 'VAES'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_VAES_128', 'AVX512_VAES_128', 'AVX512_VAES_128', 'AVX512_VAES_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_VAES_256', 'AVX512_VAES_256', 'AVX512_VAES_256', 'AVX512_VAES_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_VAES_512', 'AVX512_VAES_512', 'AVX512_VAES_512', 'AVX512_VAES_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_VAES_128', 'AVX512_VAES_128', 'AVX512_VAES_128', 'AVX512_VAES_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_128_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_VAES_256', 'AVX512_VAES_256', 'AVX512_VAES_256', 'AVX512_VAES_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_128_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_VAES_512', 'AVX512_VAES_512', 'AVX512_VAES_512', 'AVX512_VAES_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_128_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_362(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][10] = { + /*VPCLMULQDQ */ {4619,4627,4620,4628,4621,4623,4625,4622,4624,4626}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VPCLMULQDQ'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['VPCLMULQDQ'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VPCLMULQDQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VPCLMULQDQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VPCLMULQDQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VPCLMULQDQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VPCLMULQDQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VPCLMULQDQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_363(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCVTPH2PS */ {4634,4630,4632,4629,4631,4636,4638,4633,4637,4639,4635}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_364(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][11] = { + /*VCVTPS2PH */ {4645,4641,4643,4640,4642,4647,4649,4644,4648,4650,4646}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[16], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['F16C'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_365(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VGATHERDPD */ {5168,5167,5170,5171,5169}, + /*VPGATHERDQ */ {5188,5187,5190,5191,5189}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_XMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_XMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_366(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VGATHERDPS */ {5173,5172,5175,5176,5174}, + /*VPGATHERDD */ {5193,5192,5195,5196,5194}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_XMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_YMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_367(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VGATHERQPD */ {5178,5177,5180,5181,5179}, + /*VPGATHERQQ */ {5198,5197,5200,5201,5199}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_XMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_YMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_368(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][5] = { + /*VGATHERQPS */ {5183,5182,5185,5186,5184}, + /*VPGATHERQD */ {5203,5202,5205,5206,5204}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_XMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_XMM_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2GATHER', 'AVX2GATHER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_VMODRM_YMM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_369(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][10] = { + /*VPERMPD */ {5232,5231,5239,5235,5237,5233,5240,5236,5238,5234}, + /*VPERMQ */ {5222,5221,5229,5225,5227,5223,5230,5226,5228,5224}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_370(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPERMD */ {5242,5241,5245,5243,5246,5244}, + /*VPERMPS */ {5248,5247,5251,5249,5252,5250}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX2', 'AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_371(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][13] = { + /*VPBROADCASTB */ {5258,5260,5257,5259,5263,5261,5266,5264,5269,5267,5262,5265,5268}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BYTE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BYTE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BYTE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_372(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][13] = { + /*VPBROADCASTW */ {5271,5273,5270,5272,5276,5274,5279,5277,5282,5280,5275,5278,5281}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_W); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_WORD_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_WORD_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_WORD_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_373(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][16] = { + /*VPBROADCASTD */ {5284,5286,5283,5285,5293,5294,5292,5297,5298,5296,5289,5290,5288,5291,5295,5287}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][13]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][14]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][15]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_374(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][13] = { + /*VPBROADCASTQ */ {5300,5302,5299,5301,5308,5307,5311,5310,5305,5304,5306,5309,5303}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_YMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][12]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_375(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][6] = { + /*ANDN */ {5377,5378,5380,5375,5376,5379}, + /*MULX */ {5429,5430,5433,5431,5432,5434}, + /*PDEP */ {5365,5366,5368,5363,5364,5367}, + /*PEXT */ {5371,5372,5374,5369,5370,5373}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['BMI2', 'BMI2', 'BMI1', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['BMI2', 'BMI2', 'BMI1', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR64_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_VGPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['BMI2', 'BMI2', 'BMI1', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['BMI2', 'BMI2', 'BMI1', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['BMI2', 'BMI2', 'BMI1', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR64_N(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['BMI2', 'BMI2', 'BMI1', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_376(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*BLSI */ {5395,5396,5398,5393,5394,5397}, + /*BLSMSK */ {5389,5390,5392,5387,5388,5391}, + /*BLSR */ {5383,5384,5386,5381,5382,5385}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['BMI1', 'BMI1', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['BMI1', 'BMI1', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_N(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['BMI1', 'BMI1', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['BMI1', 'BMI1', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['BMI1', 'BMI1', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_N(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['BMI1', 'BMI1', 'BMI1'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_377(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][6] = { + /*BEXTR */ {5407,5408,5410,5405,5406,5409}, + /*BZHI */ {5401,5402,5404,5399,5400,5403}, + /*SARX */ {5419,5420,5422,5417,5418,5421}, + /*SHLX */ {5413,5414,5416,5411,5412,5415}, + /*SHRX */ {5425,5426,5428,5423,5424,5427}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['BMI2', 'BMI1', 'BMI2', 'BMI2', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['BMI2', 'BMI1', 'BMI2', 'BMI2', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR64_B(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_VGPR64_N(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['BMI2', 'BMI1', 'BMI2', 'BMI2', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['BMI2', 'BMI1', 'BMI2', 'BMI2', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_VGPR32_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['BMI2', 'BMI1', 'BMI2', 'BMI2', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[24], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_VGPR64_N(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['BMI2', 'BMI1', 'BMI2', 'BMI2', 'BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_378(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*RORX */ {5435,5436,5439,5437,5438,5440}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR32_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_VGPR64_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[8], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_VGPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['BMI2'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_379(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*XBEGIN */ {5446}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_RELBR) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_relbr(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['RTM'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_BRDISPz_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_380(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*ADCX */ {5452,5450,5453,5451}, + /*ADOX */ {5456,5454,5457,5455}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['ADOX_ADCX', 'ADOX_ADCX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['ADOX_ADCX', 'ADOX_ADCX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['ADOX_ADCX', 'ADOX_ADCX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['ADOX_ADCX', 'ADOX_ADCX'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_IMMUNE66_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_381(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[16][6] = { + /*VBLENDMPS */ {5604,5606,5602,5605,5607,5603}, + /*VCVTNE2PS2BF16*/ {5501,5503,5505,5502,5504,5506}, + /*VDPBF16PS */ {5513,5515,5517,5514,5516,5518}, + /*VPANDD */ {5872,5874,5870,5873,5875,5871}, + /*VPANDND */ {5878,5880,5876,5879,5881,5877}, + /*VPBLENDMD */ {5896,5898,5894,5897,5899,5895}, + /*VPERMI2D */ {5944,5946,5942,5945,5947,5943}, + /*VPERMI2PS */ {5956,5958,5954,5957,5959,5955}, + /*VPERMT2D */ {5968,5970,5966,5969,5971,5967}, + /*VPERMT2PS */ {5980,5982,5978,5981,5983,5979}, + /*VPORD */ {6118,6120,6116,6119,6121,6117}, + /*VPROLVD */ {6142,6144,6140,6143,6145,6141}, + /*VPRORVD */ {6166,6168,6164,6167,6169,6165}, + /*VPSHLDVD */ {6902,6904,6906,6903,6905,6907}, + /*VPSHRDVD */ {6938,6940,6942,6939,6941,6943}, + /*VPXORD */ {6244,6246,6242,6245,6247,6243}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_BF16_128', 'AVX512_BF16_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_BF16_256', 'AVX512_BF16_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_BF16_512', 'AVX512_BF16_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_BF16_128', 'AVX512_BF16_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_BF16_256', 'AVX512_BF16_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_BF16_512', 'AVX512_BF16_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_382(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VCVTNEPS2BF16 */ {5507,5509,5511,5508,5510,5512}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BF16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BF16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BF16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BF16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BF16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BF16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_383(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][3] = { + /*VEXP2PD */ {5520,5519,5521}, + /*VRCP28PD */ {5534,5533,5535}, + /*VRSQRT28PD */ {5546,5545,5547}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_512', 'AVX512ER_512', 'AVX512ER_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_512', 'AVX512ER_512', 'AVX512ER_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_512', 'AVX512ER_512', 'AVX512ER_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_384(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][3] = { + /*VEXP2PS */ {5523,5522,5524}, + /*VRCP28PS */ {5537,5536,5538}, + /*VRSQRT28PS */ {5549,5548,5550}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_512', 'AVX512ER_512', 'AVX512ER_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_512', 'AVX512ER_512', 'AVX512ER_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_512', 'AVX512ER_512', 'AVX512ER_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_385(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*VGATHERPF0DPD */ {5525}, + /*VGATHERPF1DPD */ {5529}, + /*VSCATTERPF0DPD*/ {5557}, + /*VSCATTERPF1DPD*/ {5561}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_386(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][1] = { + /*VGATHERPF0DPS */ {5526}, + /*VGATHERPF0QPS */ {5528}, + /*VGATHERPF1DPS */ {5530}, + /*VGATHERPF1QPS */ {5532}, + /*VSCATTERPF0DPS*/ {5558}, + /*VSCATTERPF0QPS*/ {5560}, + /*VSCATTERPF1DPS*/ {5562}, + /*VSCATTERPF1QPS*/ {5564}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_387(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*VGATHERPF0QPD */ {5527}, + /*VGATHERPF1QPD */ {5531}, + /*VSCATTERPF0QPD*/ {5559}, + /*VSCATTERPF1QPD*/ {5563}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512', 'AVX512PF_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_388(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][3] = { + /*VGETEXPSD */ {5779,5778,5780}, + /*VRCP28SD */ {5540,5539,5541}, + /*VRSQRT28SD */ {5552,5551,5553}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_SCALAR', 'AVX512ER_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_SCALAR', 'AVX512ER_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_SCALAR', 'AVX512ER_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_389(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][3] = { + /*VGETEXPSS */ {5782,5781,5783}, + /*VRCP28SS */ {5543,5542,5544}, + /*VRSQRT28SS */ {5555,5554,5556}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_SCALAR', 'AVX512ER_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_SCALAR', 'AVX512ER_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512ER_SCALAR', 'AVX512ER_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_390(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][1] = { + /*V4FMADDPS */ {5566}, + /*V4FNMADDPS */ {5568}, + /*VP4DPWSSD */ {5570}, + /*VP4DPWSSDS */ {5571}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512_4FMAPS_512', 'AVX512_4FMAPS_512', 'AVX512_4VNNIW_512', 'AVX512_4VNNIW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_4X_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_391(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*V4FMADDSS */ {5567}, + /*V4FNMADDSS */ {5569}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_4FMAPS_SCALAR', 'AVX512_4FMAPS_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE1_4X_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_392(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][6] = { + /*VPCONFLICTD */ {6377,6379,6375,6378,6380,6376}, + /*VPLZCNTD */ {6389,6391,6387,6390,6392,6388}, + /*VPOPCNTD */ {5574,5576,5572,5575,5577,5573}, + /*VRCP14PS */ {6262,6264,6260,6263,6265,6261}, + /*VRSQRT14PS */ {6298,6300,6296,6299,6301,6297}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512CD_128', 'AVX512CD_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512CD_256', 'AVX512CD_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512CD_512', 'AVX512CD_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512CD_128', 'AVX512CD_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512CD_256', 'AVX512CD_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512CD_512', 'AVX512CD_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_393(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][6] = { + /*VPABSQ */ {5866,5868,5864,5867,5869,5865}, + /*VPCONFLICTQ */ {6383,6385,6381,6384,6386,6382}, + /*VPLZCNTQ */ {6395,6397,6393,6396,6398,6394}, + /*VPOPCNTQ */ {5580,5582,5578,5581,5583,5579}, + /*VRCP14PD */ {6256,6258,6254,6257,6259,6255}, + /*VRSQRT14PD */ {6292,6294,6290,6293,6295,6291}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512CD_128', 'AVX512CD_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512CD_256', 'AVX512CD_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512CD_512', 'AVX512CD_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512CD_128', 'AVX512CD_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512CD_256', 'AVX512CD_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512_VPOPCNTDQ_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512CD_512', 'AVX512CD_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_394(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][6] = { + /*VALIGND */ {5586,5588,5584,5587,5589,5585}, + /*VPSHLDD */ {6890,6892,6894,6891,6893,6895}, + /*VPSHRDD */ {6926,6928,6930,6927,6929,6931}, + /*VPTERNLOGD */ {6208,6210,6206,6209,6211,6207}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_395(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][6] = { + /*VALIGNQ */ {5592,5594,5590,5593,5595,5591}, + /*VPSHLDQ */ {6896,6898,6900,6897,6899,6901}, + /*VPSHRDQ */ {6932,6934,6936,6933,6935,6937}, + /*VPTERNLOGQ */ {6214,6216,6212,6215,6217,6213}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_396(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[23][6] = { + /*VBLENDMPD */ {5598,5600,5596,5599,5601,5597}, + /*VPANDNQ */ {5884,5886,5882,5885,5887,5883}, + /*VPANDQ */ {5890,5892,5888,5891,5893,5889}, + /*VPBLENDMQ */ {5902,5904,5900,5903,5905,5901}, + /*VPERMI2PD */ {5950,5952,5948,5951,5953,5949}, + /*VPERMI2Q */ {5962,5964,5960,5963,5965,5961}, + /*VPERMT2PD */ {5974,5976,5972,5975,5977,5973}, + /*VPERMT2Q */ {5986,5988,5984,5987,5989,5985}, + /*VPMADD52HUQ */ {6809,6811,6813,6810,6812,6814}, + /*VPMADD52LUQ */ {6815,6817,6819,6816,6818,6820}, + /*VPMAXSQ */ {6004,6006,6002,6005,6007,6003}, + /*VPMAXUQ */ {6010,6012,6008,6011,6013,6009}, + /*VPMINSQ */ {6016,6018,6014,6017,6019,6015}, + /*VPMINUQ */ {6022,6024,6020,6023,6025,6021}, + /*VPMULLQ */ {6667,6669,6671,6668,6670,6672}, + /*VPMULTISHIFTQB*/ {6839,6841,6843,6840,6842,6844}, + /*VPORQ */ {6124,6126,6122,6125,6127,6123}, + /*VPROLVQ */ {6148,6150,6146,6149,6151,6147}, + /*VPRORVQ */ {6172,6174,6170,6173,6175,6171}, + /*VPSHLDVQ */ {6908,6910,6912,6909,6911,6913}, + /*VPSHRDVQ */ {6944,6946,6948,6945,6947,6949}, + /*VPSRAVQ */ {6202,6204,6200,6203,6205,6201}, + /*VPXORQ */ {6250,6252,6248,6251,6253,6249}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512_IFMA_128', 'AVX512_IFMA_128', 'AVX512_VBMI_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512_IFMA_256', 'AVX512_IFMA_256', 'AVX512_VBMI_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512_IFMA_512', 'AVX512_IFMA_512', 'AVX512_VBMI_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512F_128', 'AVX512DQ_128', 'AVX512_IFMA_128', 'AVX512_IFMA_128', 'AVX512_VBMI_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512F_256', 'AVX512DQ_256', 'AVX512_IFMA_256', 'AVX512_IFMA_256', 'AVX512_VBMI_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512F_512', 'AVX512DQ_512', 'AVX512_IFMA_512', 'AVX512_IFMA_512', 'AVX512_VBMI_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_397(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VBROADCASTF32X4*/ {5609,5608}, + /*VBROADCASTI32X4*/ {5612,5611}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_398(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*VBROADCASTF64X4*/ {5610}, + /*VBROADCASTI64X4*/ {5613}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_399(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VCOMPRESSPD */ {5617,5619,5615,5616,5618,5614}, + /*VPCOMPRESSQ */ {5939,5941,5937,5938,5940,5936}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_400(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VCOMPRESSPS */ {5623,5625,5621,5622,5624,5620}, + /*VPCOMPRESSD */ {5933,5935,5931,5932,5934,5930}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_401(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTPD2UDQ */ {5627,5629,5631,5626,5630,5632,5628}, + /*VCVTQQ2PS */ {6455,6450,6452,6454,6451,6453,6456}, + /*VCVTUQQ2PS */ {6497,6492,6494,6496,6493,6495,6498}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_402(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VCVTPS2UDQ */ {5634,5636,5638,5633,5637,5639,5635}, + /*VCVTUDQ2PS */ {5698,5700,5702,5697,5701,5703,5699}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_403(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][9] = { + /*VCVTSD2USI */ {5642,5643,5647,5640,5641,5646,5644,5645,5648}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_404(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][9] = { + /*VCVTSS2USI */ {5651,5652,5656,5649,5650,5655,5653,5654,5657}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_405(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][7] = { + /*VCVTTPD2UDQ */ {5659,5661,5663,5658,5662,5664,5660}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_406(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VCVTTPS2UDQ */ {5666,5668,5670,5665,5669,5671,5667}, + /*VGETEXPPS */ {5772,5774,5776,5771,5775,5777,5773}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_407(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][9] = { + /*VCVTTSD2USI */ {5674,5675,5679,5672,5673,5678,5676,5677,5680}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_408(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][9] = { + /*VCVTTSS2USI */ {5683,5684,5688,5681,5682,5687,5685,5686,5689}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_409(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][7] = { + /*VCVTUDQ2PD */ {5691,5693,5695,5690,5694,5696,5692}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_410(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][7] = { + /*VCVTUSI2SD */ {5709,5704,5705,5708,5706,5707,5710}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_411(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][9] = { + /*VCVTUSI2SS */ {5713,5714,5718,5711,5712,5717,5715,5716,5719}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_412(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VEXPANDPD */ {5723,5725,5721,5722,5724,5720}, + /*VPEXPANDQ */ {5999,6001,5997,5998,6000,5996}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_413(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VEXPANDPS */ {5729,5731,5727,5728,5730,5726}, + /*VPEXPANDD */ {5993,5995,5991,5992,5994,5990}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_414(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VEXTRACTF32X4 */ {5734,5732,5735,5733}, + /*VEXTRACTI32X4 */ {5740,5738,5741,5739}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_415(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VEXTRACTF64X4 */ {5736,5737}, + /*VEXTRACTI64X4 */ {5742,5743}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_416(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VFIXUPIMMPD */ {5745,5747,5749,5744,5748,5750,5746}, + /*VRANGEPD */ {6720,6715,6717,6719,6716,6718,6721}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_417(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VFIXUPIMMPS */ {5752,5754,5756,5751,5755,5757,5753}, + /*VRANGEPS */ {6727,6722,6724,6726,6723,6725,6728}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_418(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][3] = { + /*VFIXUPIMMSD */ {5759,5758,5760}, + /*VGETMANTSD */ {5799,5798,5800}, + /*VRANGESD */ {6730,6729,6731}, + /*VREDUCESD */ {6750,6749,6751}, + /*VRNDSCALESD */ {6285,6284,6286}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512DQ_SCALAR', 'AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512DQ_SCALAR', 'AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512DQ_SCALAR', 'AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_419(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][3] = { + /*VFIXUPIMMSS */ {5762,5761,5763}, + /*VGETMANTSS */ {5802,5801,5803}, + /*VRANGESS */ {6733,6732,6734}, + /*VREDUCESS */ {6753,6752,6754}, + /*VRNDSCALESS */ {6288,6287,6289}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512DQ_SCALAR', 'AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512DQ_SCALAR', 'AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512F_SCALAR', 'AVX512DQ_SCALAR', 'AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_420(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTTPD2QQ */ {6462,6457,6459,6461,6458,6460,6463}, + /*VCVTTPD2UQQ */ {6469,6464,6466,6468,6465,6467,6470}, + /*VGETEXPPD */ {5765,5767,5769,5764,5768,5770,5766}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_421(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VGETMANTPD */ {5785,5787,5789,5784,5788,5790,5786}, + /*VREDUCEPD */ {6740,6735,6737,6739,6736,6738,6741}, + /*VRNDSCALEPD */ {6271,6273,6275,6270,6274,6276,6272}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_422(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VGETMANTPS */ {5792,5794,5796,5791,5795,5797,5793}, + /*VREDUCEPS */ {6747,6742,6744,6746,6743,6745,6748}, + /*VRNDSCALEPS */ {6278,6280,6282,6277,6281,6283,6279}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_423(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VINSERTF32X4 */ {5806,5804,5807,5805}, + /*VINSERTI32X4 */ {5812,5810,5813,5811}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_424(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VINSERTF64X4 */ {5808,5809}, + /*VINSERTI64X4 */ {5814,5815}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE4_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_425(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][12] = { + /*VMOVDQA32 */ {5822,5820,5826,5824,5818,5816,5823,5821,5827,5825,5819,5817}, + /*VMOVDQU32 */ {5846,5844,5850,5848,5842,5840,5847,5845,5851,5849,5843,5841}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_426(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][12] = { + /*VMOVDQA64 */ {5834,5832,5838,5836,5830,5828,5835,5833,5839,5837,5831,5829}, + /*VMOVDQU64 */ {5858,5856,5862,5860,5854,5852,5859,5857,5863,5861,5855,5853}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_427(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPCMPD */ {5908,5910,5906,5909,5911,5907}, + /*VPCMPUD */ {5920,5922,5918,5921,5923,5919}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_428(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPCMPQ */ {5914,5916,5912,5915,5917,5913}, + /*VPCMPUQ */ {5926,5928,5924,5927,5929,5925}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_429(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPMOVDB */ {6028,6030,6026,6029,6031,6027}, + /*VPMOVSDB */ {6058,6060,6056,6059,6061,6057}, + /*VPMOVUSDB */ {6088,6090,6086,6089,6091,6087}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_430(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPMOVDW */ {6034,6036,6032,6035,6037,6033}, + /*VPMOVSDW */ {6064,6066,6062,6065,6067,6063}, + /*VPMOVUSDW */ {6094,6096,6092,6095,6097,6093}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_431(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPMOVQB */ {6040,6042,6038,6041,6043,6039}, + /*VPMOVSQB */ {6070,6072,6068,6071,6073,6069}, + /*VPMOVUSQB */ {6100,6102,6098,6101,6103,6099}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_432(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPMOVQD */ {6046,6048,6044,6047,6049,6045}, + /*VPMOVSQD */ {6076,6078,6074,6077,6079,6075}, + /*VPMOVUSQD */ {6106,6108,6104,6107,6109,6105}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_433(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPMOVQW */ {6052,6054,6050,6053,6055,6051}, + /*VPMOVSQW */ {6082,6084,6080,6083,6085,6081}, + /*VPMOVUSQW */ {6112,6114,6110,6113,6115,6111}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_128', 'AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_256', 'AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512F_512', 'AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_434(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPROLD */ {6130,6132,6128,6131,6133,6129}, + /*VPRORD */ {6154,6156,6152,6155,6157,6153}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_435(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPROLQ */ {6136,6138,6134,6137,6139,6135}, + /*VPRORQ */ {6160,6162,6158,6161,6163,6159}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_436(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*VPSCATTERDD */ {6177,6178,6176}, + /*VSCATTERDPS */ {6330,6331,6329}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_437(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*VPSCATTERDQ */ {6180,6181,6179}, + /*VSCATTERDPD */ {6327,6328,6326}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_438(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*VPSCATTERQD */ {6183,6184,6182}, + /*VSCATTERQPS */ {6336,6337,6335}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_439(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*VPSCATTERQQ */ {6186,6187,6185}, + /*VSCATTERQPD */ {6333,6334,6332}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASKNOT0(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_440(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][12] = { + /*VPSRAQ */ {6192,6196,6188,6194,6198,6190,6193,6197,6189,6195,6199,6191}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_MEM128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_441(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPTESTMD */ {6220,6222,6218,6221,6223,6219}, + /*VPTESTNMD */ {6232,6234,6230,6233,6235,6231}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_442(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPTESTMQ */ {6226,6228,6224,6227,6229,6225}, + /*VPTESTNMQ */ {6238,6240,6236,6239,6241,6237}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_128', 'AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_443(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VRCP14SD */ {6266,6267}, + /*VRSQRT14SD */ {6302,6303}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_444(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VRCP14SS */ {6268,6269}, + /*VRSQRT14SS */ {6304,6305}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_SCALAR', 'AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_445(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][7] = { + /*VSCALEFPD */ {6307,6309,6311,6306,6310,6312,6308}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_446(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][7] = { + /*VFCMADDCPH */ {7307,7302,7304,7306,7303,7305,7308}, + /*VFCMULCPH */ {7317,7312,7314,7316,7313,7315,7318}, + /*VFMADDCPH */ {7357,7352,7354,7356,7353,7355,7358}, + /*VFMULCPH */ {7439,7434,7436,7438,7435,7437,7440}, + /*VSCALEFPS */ {6314,6316,6318,6313,6317,6319,6315}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512F_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_447(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*VSCALEFSD */ {6321,6320,6322}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_448(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*VSCALEFSS */ {6324,6323,6325}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_449(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VSHUFF32X4 */ {6340,6338,6341,6339}, + /*VSHUFI32X4 */ {6348,6346,6349,6347}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_450(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VSHUFF64X2 */ {6344,6342,6345,6343}, + /*VSHUFI64X2 */ {6352,6350,6353,6351}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_256', 'AVX512F_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512F_512', 'AVX512F_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_451(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[27][1] = { + /*KADDB */ {6755}, + /*KADDD */ {6756}, + /*KADDQ */ {6757}, + /*KADDW */ {6758}, + /*KANDB */ {6759}, + /*KANDD */ {6760}, + /*KANDNB */ {6761}, + /*KANDND */ {6762}, + /*KANDNQ */ {6763}, + /*KANDNW */ {6354}, + /*KANDQ */ {6764}, + /*KANDW */ {6355}, + /*KORB */ {6785}, + /*KORD */ {6786}, + /*KORQ */ {6787}, + /*KORW */ {6363}, + /*KUNPCKBW */ {6366}, + /*KUNPCKDQ */ {6801}, + /*KUNPCKWD */ {6802}, + /*KXNORB */ {6803}, + /*KXNORD */ {6804}, + /*KXNORQ */ {6805}, + /*KXNORW */ {6367}, + /*KXORB */ {6806}, + /*KXORD */ {6807}, + /*KXORQ */ {6808}, + /*KXORW */ {6368}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_N(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_KOP', 'AVX512F_KOP', 'AVX512F_KOP', 'AVX512F_KOP', 'AVX512F_KOP', 'AVX512F_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_452(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*KMOVW */ {6360,6359,6356,6358,6357}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512F_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_453(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[12][1] = { + /*KNOTB */ {6782}, + /*KNOTD */ {6783}, + /*KNOTQ */ {6784}, + /*KNOTW */ {6361}, + /*KORTESTB */ {6788}, + /*KORTESTD */ {6789}, + /*KORTESTQ */ {6790}, + /*KORTESTW */ {6362}, + /*KTESTB */ {6797}, + /*KTESTD */ {6798}, + /*KTESTQ */ {6799}, + /*KTESTW */ {6800}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512F_KOP', 'AVX512F_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_454(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[8][1] = { + /*KSHIFTLB */ {6791}, + /*KSHIFTLD */ {6792}, + /*KSHIFTLQ */ {6793}, + /*KSHIFTLW */ {6364}, + /*KSHIFTRB */ {6794}, + /*KSHIFTRD */ {6795}, + /*KSHIFTRQ */ {6796}, + /*KSHIFTRW */ {6365}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True] isa_set ['AVX512F_KOP', 'AVX512F_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP', 'AVX512DQ_KOP', 'AVX512BW_KOP', 'AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_455(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[6][3] = { + /*VPBROADCASTMB2Q*/ {6370,6371,6369}, + /*VPBROADCASTMW2D*/ {6373,6374,6372}, + /*VPMOVM2B */ {6631,6632,6633}, + /*VPMOVM2D */ {6634,6635,6636}, + /*VPMOVM2Q */ {6637,6638,6639}, + /*VPMOVM2W */ {6640,6641,6642}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512CD_128', 'AVX512CD_128', 'AVX512BW_128', 'AVX512DQ_128', 'AVX512DQ_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512CD_256', 'AVX512CD_256', 'AVX512BW_256', 'AVX512DQ_256', 'AVX512DQ_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True] isa_set ['AVX512CD_512', 'AVX512CD_512', 'AVX512BW_512', 'AVX512DQ_512', 'AVX512DQ_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_456(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VBROADCASTF32X2*/ {6399,6401,6400,6402}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_457(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*VBROADCASTF32X8*/ {6403}, + /*VBROADCASTI32X8*/ {6412}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_458(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VBROADCASTF64X2*/ {6404,6405}, + /*VBROADCASTI64X2*/ {6413,6414}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_459(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VBROADCASTI32X2*/ {6406,6408,6410,6407,6409,6411}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_460(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][7] = { + /*VCVTPD2QQ */ {6420,6415,6417,6419,6416,6418,6421}, + /*VCVTPD2UQQ */ {6427,6422,6424,6426,6423,6425,6428}, + /*VCVTQQ2PD */ {6448,6443,6445,6447,6444,6446,6449}, + /*VCVTUQQ2PD */ {6490,6485,6487,6489,6486,6488,6491}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128', 'AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256', 'AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128', 'AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256', 'AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512', 'AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_461(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VCVTPS2QQ */ {6434,6429,6431,6433,6430,6432,6435}, + /*VCVTPS2UQQ */ {6441,6436,6438,6440,6437,6439,6442}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_462(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VCVTTPS2QQ */ {6476,6471,6473,6475,6472,6474,6477}, + /*VCVTTPS2UQQ */ {6483,6478,6480,6482,6479,6481,6484}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_128', 'AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_463(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VDBPSADBW */ {6499,6501,6503,6500,6502,6504}, + /*VPSHLDW */ {6920,6922,6924,6921,6923,6925}, + /*VPSHRDW */ {6956,6958,6960,6957,6959,6961}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_464(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VEXTRACTF32X8 */ {6505,6506}, + /*VEXTRACTI32X8 */ {6511,6512}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_465(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VEXTRACTF64X2 */ {6507,6509,6508,6510}, + /*VEXTRACTI64X2 */ {6513,6515,6514,6516}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[31], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_466(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VFPCLASSPD */ {6517,6519,6521,6518,6520,6522}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_467(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VFPCLASSPS */ {6523,6525,6527,6524,6526,6528}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_468(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VFPCLASSSD */ {6529,6530}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_469(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VFPCLASSSS */ {6531,6532}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_470(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VINSERTF32X8 */ {6533,6534}, + /*VINSERTI32X8 */ {6539,6540}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_471(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][4] = { + /*VINSERTF64X2 */ {6535,6537,6536,6538}, + /*VINSERTI64X2 */ {6541,6543,6542,6544}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_256', 'AVX512DQ_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512DQ_512', 'AVX512DQ_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_TUPLE2_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_472(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][12] = { + /*VMOVDQU16 */ {6547,6545,6551,6549,6555,6553,6548,6546,6552,6550,6556,6554}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_473(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][12] = { + /*VMOVDQU8 */ {6559,6557,6563,6561,6567,6565,6560,6558,6564,6562,6568,6566}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][9]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][10]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][11]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_474(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][6] = { + /*VPBLENDMB */ {6569,6571,6573,6570,6572,6574}, + /*VPERMB */ {6821,6823,6825,6822,6824,6826}, + /*VPERMI2B */ {6827,6829,6831,6828,6830,6832}, + /*VPERMT2B */ {6833,6835,6837,6834,6836,6838}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_128', 'AVX512_VBMI_128', 'AVX512_VBMI_128', 'AVX512_VBMI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_256', 'AVX512_VBMI_256', 'AVX512_VBMI_256', 'AVX512_VBMI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_512', 'AVX512_VBMI_512', 'AVX512_VBMI_512', 'AVX512_VBMI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_128', 'AVX512_VBMI_128', 'AVX512_VBMI_128', 'AVX512_VBMI_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_256', 'AVX512_VBMI_256', 'AVX512_VBMI_256', 'AVX512_VBMI_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_512', 'AVX512_VBMI_512', 'AVX512_VBMI_512', 'AVX512_VBMI_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_475(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[9][6] = { + /*VPBLENDMW */ {6575,6577,6579,6576,6578,6580}, + /*VPERMI2W */ {6605,6607,6609,6606,6608,6610}, + /*VPERMT2W */ {6611,6613,6615,6612,6614,6616}, + /*VPERMW */ {6617,6619,6621,6618,6620,6622}, + /*VPSHLDVW */ {6914,6916,6918,6915,6917,6919}, + /*VPSHRDVW */ {6950,6952,6954,6951,6953,6955}, + /*VPSLLVW */ {6673,6675,6677,6674,6676,6678}, + /*VPSRAVW */ {6679,6681,6683,6680,6682,6684}, + /*VPSRLVW */ {6685,6687,6689,6686,6688,6690}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128', 'AVX512_VBMI2_128', 'AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256', 'AVX512_VBMI2_256', 'AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512', 'AVX512_VBMI2_512', 'AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_476(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPCMPB */ {6581,6583,6585,6582,6584,6586}, + /*VPCMPUB */ {6587,6589,6591,6588,6590,6592}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_477(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPCMPUW */ {6593,6595,6597,6594,6596,6598}, + /*VPCMPW */ {6599,6601,6603,6600,6602,6604}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_478(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VPEXTRW_C5 */ {6623,6624}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[9], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_479(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[4][3] = { + /*VPMOVB2M */ {6625,6626,6627}, + /*VPMOVD2M */ {6628,6629,6630}, + /*VPMOVQ2M */ {6643,6644,6645}, + /*VPMOVW2M */ {6658,6659,6660}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_128', 'AVX512DQ_128', 'AVX512DQ_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_256', 'AVX512DQ_256', 'AVX512DQ_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True] isa_set ['AVX512BW_512', 'AVX512DQ_512', 'AVX512DQ_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_480(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPMOVSWB */ {6646,6648,6650,6647,6649,6651}, + /*VPMOVUSWB */ {6652,6654,6656,6653,6655,6657}, + /*VPMOVWB */ {6661,6663,6665,6662,6664,6666}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALFMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_481(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][6] = { + /*VPSHUFBITQMB */ {6860,6862,6864,6861,6863,6865}, + /*VPTESTMB */ {6691,6693,6695,6692,6694,6696}, + /*VPTESTNMB */ {6703,6705,6707,6704,6706,6708}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512_BITALG_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512_BITALG_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512_BITALG_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_128', 'AVX512BW_128', 'AVX512_BITALG_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_256', 'AVX512BW_256', 'AVX512_BITALG_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512BW_512', 'AVX512BW_512', 'AVX512_BITALG_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_482(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VPTESTMW */ {6697,6699,6701,6698,6700,6702}, + /*VPTESTNMW */ {6709,6711,6713,6710,6712,6714}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_128', 'AVX512BW_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_256', 'AVX512BW_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512BW_512', 'AVX512BW_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_483(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*KMOVB */ {6769,6768,6765,6767,6766}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_B); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512DQ_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_484(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][7] = { + /*KMOVD */ {6776,6774,6775,6773,6770,6772,6771}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_485(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][5] = { + /*KMOVQ */ {6781,6780,6777,6779,6778}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512BW_KOP'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_486(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VPOPCNTB */ {6848,6850,6852,6849,6851,6853}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_487(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VPOPCNTW */ {6854,6856,6858,6855,6857,6859}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_BITALG_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULLMEM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_488(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VPCOMPRESSB */ {6867,6869,6871,6866,6868,6870}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_489(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VPCOMPRESSW */ {6873,6875,6877,6872,6874,6876}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_490(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VPEXPANDB */ {6879,6881,6883,6878,6880,6882}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_8_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_491(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VPEXPANDW */ {6885,6887,6889,6884,6886,6888}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_DQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_QQ); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VBMI2_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GSCAT_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_492(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VP2INTERSECTD */ {6998,7000,7002,6999,7001,7003}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_493(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VP2INTERSECTQ */ {7004,7006,7008,7005,7007,7009}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_VP2INTERSECT_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_494(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*AESDEC128KL */ {7010}, + /*AESENC128KL */ {7014}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M384); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['KEYLOCKER', 'KEYLOCKER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_495(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*AESDEC256KL */ {7011}, + /*AESENC256KL */ {7015}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['KEYLOCKER', 'KEYLOCKER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_496(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*AESDECWIDE128KL*/ {7012}, + /*AESENCWIDE128KL*/ {7016}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_M384); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['KEYLOCKER_WIDE', 'KEYLOCKER_WIDE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_497(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*AESDECWIDE256KL*/ {7013}, + /*AESENCWIDE256KL*/ {7017}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['KEYLOCKER_WIDE', 'KEYLOCKER_WIDE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_498(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*ENCODEKEY128 */ {7018}, + /*ENCODEKEY256 */ {7019}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['KEYLOCKER', 'KEYLOCKER'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_499(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*SENDUIPI */ {7023}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['UINTR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_500(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*LDTILECFG */ {7027}, + /*STTILECFG */ {7028}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AMX_TILE', 'AMX_TILE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_501(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][1] = { + /*TDPBF16PS */ {7029}, + /*TDPBSSD */ {7030}, + /*TDPBSUD */ {7031}, + /*TDPBUSD */ {7032}, + /*TDPBUUD */ {7033}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_TMM_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_TMM_B(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_TMM_N(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AMX_BF16', 'AMX_INT8', 'AMX_INT8', 'AMX_INT8', 'AMX_INT8'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_502(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*TILELOADD */ {7034}, + /*TILELOADDT1 */ {7035}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_TMM_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PTR); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AMX_TILE', 'AMX_TILE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_503(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*TILERELEASE */ {7036}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMX_TILE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_504(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*TILESTORED */ {7037}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_PTR) && + xed_encode_ntluf_TMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMX_TILE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_505(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][1] = { + /*TILEZERO */ {7038}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 1 && xes->_operand_order[0] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_must_use_evex(xes) == 0) && + xed_encode_ntluf_TMM_R(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AMX_TILE'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_506(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][1] = { + /*ENQCMD */ {7039}, + /*ENQCMDS */ {7040}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_A_GPR_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_ZD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['ENQCMD', 'ENQCMD'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_507(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[23][7] = { + /*VADDPH */ {7054,7049,7051,7053,7050,7052,7055}, + /*VDIVPH */ {7297,7292,7294,7296,7293,7295,7298}, + /*VFMADD132PH */ {7327,7322,7324,7326,7323,7325,7328}, + /*VFMADD213PH */ {7337,7332,7334,7336,7333,7335,7338}, + /*VFMADD231PH */ {7347,7342,7344,7346,7343,7345,7348}, + /*VFMADDSUB132PH*/ {7367,7362,7364,7366,7363,7365,7368}, + /*VFMADDSUB213PH*/ {7374,7369,7371,7373,7370,7372,7375}, + /*VFMADDSUB231PH*/ {7381,7376,7378,7380,7377,7379,7382}, + /*VFMSUB132PH */ {7388,7383,7385,7387,7384,7386,7389}, + /*VFMSUB213PH */ {7398,7393,7395,7397,7394,7396,7399}, + /*VFMSUB231PH */ {7408,7403,7405,7407,7404,7406,7409}, + /*VFMSUBADD132PH*/ {7418,7413,7415,7417,7414,7416,7419}, + /*VFMSUBADD213PH*/ {7425,7420,7422,7424,7421,7423,7426}, + /*VFMSUBADD231PH*/ {7432,7427,7429,7431,7428,7430,7433}, + /*VFNMADD132PH */ {7449,7444,7446,7448,7445,7447,7450}, + /*VFNMADD213PH */ {7459,7454,7456,7458,7455,7457,7460}, + /*VFNMADD231PH */ {7469,7464,7466,7468,7465,7467,7470}, + /*VFNMSUB132PH */ {7479,7474,7476,7478,7475,7477,7480}, + /*VFNMSUB213PH */ {7489,7484,7486,7488,7485,7487,7490}, + /*VFNMSUB231PH */ {7499,7494,7496,7498,7495,7497,7500}, + /*VMULPH */ {7565,7560,7562,7564,7561,7563,7566}, + /*VSCALEFPH */ {7611,7606,7608,7610,7607,7609,7612}, + /*VSUBPH */ {7631,7626,7628,7630,7627,7629,7632}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_508(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[18][3] = { + /*VADDSH */ {7057,7056,7058}, + /*VDIVSH */ {7300,7299,7301}, + /*VFMADD132SH */ {7330,7329,7331}, + /*VFMADD213SH */ {7340,7339,7341}, + /*VFMADD231SH */ {7350,7349,7351}, + /*VFMSUB132SH */ {7391,7390,7392}, + /*VFMSUB213SH */ {7401,7400,7402}, + /*VFMSUB231SH */ {7411,7410,7412}, + /*VFNMADD132SH */ {7452,7451,7453}, + /*VFNMADD213SH */ {7462,7461,7463}, + /*VFNMADD231SH */ {7472,7471,7473}, + /*VFNMSUB132SH */ {7482,7481,7483}, + /*VFNMSUB213SH */ {7492,7491,7493}, + /*VFNMSUB231SH */ {7502,7501,7503}, + /*VMULSH */ {7568,7567,7569}, + /*VSCALEFSH */ {7614,7613,7615}, + /*VSQRTSH */ {7624,7623,7625}, + /*VSUBSH */ {7634,7633,7635}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_509(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][7] = { + /*VCMPPH */ {7064,7059,7061,7063,7060,7062,7065}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_510(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*VCMPSH */ {7067,7066,7068}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_511(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][3] = { + /*VCOMISH */ {7070,7069,7071}, + /*VUCOMISH */ {7637,7636,7638}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_512(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTDQ2PH */ {7077,7072,7074,7076,7073,7075,7078}, + /*VCVTPS2PHX */ {7147,7142,7144,7146,7143,7145,7148}, + /*VCVTUDQ2PH */ {7260,7255,7257,7259,7256,7258,7261}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_513(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTPD2PH */ {7084,7079,7081,7083,7080,7082,7085}, + /*VCVTQQ2PH */ {7154,7149,7151,7153,7150,7152,7155}, + /*VCVTUQQ2PH */ {7267,7262,7264,7266,7263,7265,7268}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_514(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VCVTPH2DQ */ {7091,7086,7088,7090,7087,7089,7092}, + /*VCVTPH2UDQ */ {7119,7114,7116,7118,7115,7117,7120}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_515(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTPH2PD */ {7098,7093,7095,7097,7094,7096,7099}, + /*VCVTTPH2QQ */ {7207,7202,7204,7206,7203,7205,7208}, + /*VCVTTPH2UQQ */ {7221,7216,7218,7220,7217,7219,7222}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_516(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTPH2PSX */ {7105,7100,7102,7104,7101,7103,7106}, + /*VCVTTPH2DQ */ {7200,7195,7197,7199,7196,7198,7201}, + /*VCVTTPH2UDQ */ {7214,7209,7211,7213,7210,7212,7215}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_HALF_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_517(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VCVTPH2QQ */ {7112,7107,7109,7111,7108,7110,7113}, + /*VCVTPH2UQQ */ {7126,7121,7123,7125,7122,7124,7127}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_QUARTER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_518(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][7] = { + /*VCVTPH2UW */ {7133,7128,7130,7132,7129,7131,7134}, + /*VCVTPH2W */ {7140,7135,7137,7139,7136,7138,7141}, + /*VCVTUW2PH */ {7283,7278,7280,7282,7279,7281,7284}, + /*VCVTW2PH */ {7290,7285,7287,7289,7286,7288,7291}, + /*VSQRTPH */ {7621,7616,7618,7620,7617,7619,7622}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_519(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][3] = { + /*VCVTSD2SH */ {7157,7156,7158}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_520(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][3] = { + /*VCVTSH2SD */ {7160,7159,7161}, + /*VCVTSH2SS */ {7172,7171,7173}, + /*VGETEXPSH */ {7520,7519,7521}, + /*VMAXSH */ {7540,7539,7541}, + /*VMINSH */ {7550,7549,7551}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_521(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][9] = { + /*VCVTSH2SI */ {7166,7163,7169,7165,7162,7168,7167,7164,7170}, + /*VCVTSH2USI */ {7178,7175,7181,7177,7174,7180,7179,7176,7182}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_522(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][9] = { + /*VCVTSI2SH */ {7187,7184,7190,7186,7183,7189,7188,7185,7191}, + /*VCVTUSI2SH */ {7273,7270,7276,7272,7269,7275,7274,7271,7277}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_GPR64_B(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_Q); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_64_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_523(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[5][3] = { + /*VCVTSS2SH */ {7193,7192,7194}, + /*VFCMADDCSH */ {7310,7309,7311}, + /*VFCMULCSH */ {7320,7319,7321}, + /*VFMADDCSH */ {7360,7359,7361}, + /*VFMULCSH */ {7442,7441,7443}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_roundc(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_AVX512_ROUND_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_D); + if (conditions_satisfied) { + // real_opcode [True, True, True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_32_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_524(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VCVTTPH2UW */ {7228,7223,7225,7227,7224,7226,7229}, + /*VCVTTPH2W */ {7235,7230,7232,7234,7231,7233,7236}, + /*VGETEXPPH */ {7517,7512,7514,7516,7513,7515,7518}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_525(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][9] = { + /*VCVTTSH2SI */ {7241,7238,7244,7240,7237,7243,7242,7239,7245}, + /*VCVTTSH2USI */ {7250,7247,7253,7249,7246,7252,7251,7248,7254}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR32_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][7]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + xed_encode_ntluf_GPR64_R(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][8]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_526(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][6] = { + /*VFPCLASSPH */ {7504,7506,7508,7505,7507,7509}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_527(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][2] = { + /*VFPCLASSSH */ {7510,7511}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_MASK_R(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_528(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][7] = { + /*VGETMANTPH */ {7527,7522,7524,7526,7523,7525,7528}, + /*VREDUCEPH */ {7583,7578,7580,7582,7579,7581,7584}, + /*VRNDSCALEPH */ {7593,7588,7590,7592,7589,7591,7594}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[27], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[26], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_529(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[3][3] = { + /*VGETMANTSH */ {7530,7529,7531}, + /*VREDUCESH */ {7586,7585,7587}, + /*VRNDSCALESH */ {7596,7595,7597}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[29], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 5 && memcmp(xed_encode_order[30], xes->_operand_order, sizeof(xed_uint8_t)*5)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + (xed3_operand_get_imm0(xes) == 1); + if (conditions_satisfied) { + // real_opcode [True, True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_UIMM8_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_530(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][7] = { + /*VMAXPH */ {7537,7532,7534,7536,7533,7535,7538}, + /*VMINPH */ {7547,7542,7544,7546,7543,7545,7548}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_sae(xes) != 0) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_SAE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][6]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_531(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VMOVSH */ {7555,7554,7553,7552}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[17], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_532(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[1][4] = { + /*VMOVW */ {7558,7556,7559,7557}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_REG1) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_GPR32_B(xes,xed3_operand_get_reg1(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_MEM0 && xes->_operand_order[1] == XED_OPERAND_REG0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 2 && xes->_operand_order[0] == XED_OPERAND_REG0 && xes->_operand_order[1] == XED_OPERAND_MEM0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True] isa_set ['AVX512_FP16_128N'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_GPR_READER_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_533(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][6] = { + /*VRCPPH */ {7570,7572,7574,7571,7573,7575}, + /*VRSQRTPH */ {7598,7600,7602,7599,7601,7603}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_YMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[18], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_ZMM_B3(xes,xed3_operand_get_reg2(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][2]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 0) && + xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_128', 'AVX512_FP16_128'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][3]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 1) && + xed_encode_ntluf_YMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_256', 'AVX512_FP16_256'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][4]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 3 && memcmp(xed_encode_order[25], xes->_operand_order, sizeof(xed_uint8_t)*3)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = (xed3_operand_get_vl(xes) == 2) && + xed_encode_ntluf_ZMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_VV); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_512', 'AVX512_FP16_512'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][5]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_FULL_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} +xed_bool_t xed_encode_group_534(xed_encoder_request_t* xes) +{ + xed_bool_t okay=1; + xed_ptrn_func_ptr_t fb_ptrn_function; + static const xed_uint16_t iform_ids[2][2] = { + /*VRCPSH */ {7576,7577}, + /*VRSQRTSH */ {7604,7605}, + }; + xed_uint8_t iclass_index = xed_encoder_get_iclasses_index_in_group(xes); + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[22], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + xed_encode_ntluf_XMM_B3(xes,xed3_operand_get_reg3(xes)); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][0]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + if (1) { // ALL ONES + if (xes->_n_operand_order == 4 && memcmp(xed_encode_order[23], xes->_operand_order, sizeof(xed_uint8_t)*4)==0) { + xed_bool_t conditions_satisfied=0; + conditions_satisfied = xed_encode_ntluf_XMM_R3(xes,xed3_operand_get_reg0(xes)) && + xed_encode_ntluf_MASK1(xes,xed3_operand_get_reg1(xes)) && + xed_encode_ntluf_XMM_N3(xes,xed3_operand_get_reg2(xes)) && + (xed3_operand_get_mem0(xes) == 1) && + xed_encoder_request__memop_compatible(xes,XED_OPERAND_WIDTH_WRD); + if (conditions_satisfied) { + // real_opcode [True, True] isa_set ['AVX512_FP16_SCALAR', 'AVX512_FP16_SCALAR'] + okay=1; + xed_encoder_request_set_iform_index(xes,iform_ids[iclass_index][1]); + fb_ptrn_function = xed_encoder_get_fb_ptrn(xes); + (*fb_ptrn_function)(xes); + if (okay) + okay = xed_encode_nonterminal_MODRM_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_ESIZE_16_BITS_BIND(xes); + if (okay) + okay = xed_encode_nonterminal_NELEM_SCALAR_BIND(xes); + if (okay) return 1; + } + } // initial conditions + } // xed_enc_chip_check + return 0; + (void) okay; + (void) xes; +} diff --git a/CodeVirtualizer/build/obj/xed-enc-operand-lu.c b/CodeVirtualizer/build/obj/xed-enc-operand-lu.c new file mode 100644 index 0000000..11f0714 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-enc-operand-lu.c @@ -0,0 +1,377 @@ +/// @file xed-enc-operand-lu.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encode.h" +#include "xed-operand-accessors.h" +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_EASZ(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_base0(xes)) << ((0)); + key += (xed3_operand_get_easz(xes)) << ((9)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_DEFAULT_SEG_SEG0(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_default_seg(xes)) << ((0)); + key += (xed3_operand_get_seg0(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_NEED_SIB(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_need_sib(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_INDEX(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_easz(xes)) << ((0)); + key += (xed3_operand_get_index(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_NEED_SIB_SCALE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_need_sib(xes)) << ((0)); + key += (xed3_operand_get_scale(xes)) << ((1)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_DISP_WIDTH_EASZ(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_disp_width(xes)) << ((0)); + key += (xed3_operand_get_easz(xes)) << ((7)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_INDEX(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_base0(xes)) << ((0)); + key += (xed3_operand_get_index(xes)) << ((9)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_MODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_base0(xes)) << ((0)); + key += (xed3_operand_get_mode(xes)) << ((9)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0_EASZ_MODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_base0(xes)) << ((0)); + key += (xed3_operand_get_easz(xes)) << ((9)); + key += (xed3_operand_get_mode(xes)) << ((11)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BASE0(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_base0(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_NEED_SIB(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_easz(xes)) << ((0)); + key += (xed3_operand_get_need_sib(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_DISP_WIDTH(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_disp_width(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ_MODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_eosz(xes)) << ((0)); + key += (xed3_operand_get_mode(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_MODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_easz(xes)) << ((0)); + key += (xed3_operand_get_mode(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_SMODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_smode(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_AGEN(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_agen(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_SEG0(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_seg0(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_SEG1(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_seg1(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_DF32_DF64_EOSZ_MODE_VEXVALID(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_df32(xes)) << ((0)); + key += (xed3_operand_get_df64(xes)) << ((1)); + key += (xed3_operand_get_eosz(xes)) << ((2)); + key += (xed3_operand_get_mode(xes)) << ((4)); + key += (xed3_operand_get_vexvalid(xes)) << ((6)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_VEXVALID(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_vexvalid(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MAP(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_map(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXB_REXX(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_rexb(xes)) << ((2)); + key += (xed3_operand_get_rexx(xes)) << ((3)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_REG_REXR(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_reg(xes)) << ((0)); + key += (xed3_operand_get_rexr(xes)) << ((3)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_REXB_RM(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_rexb(xes)) << ((0)); + key += (xed3_operand_get_rm(xes)) << ((1)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXR(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_rexr(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXB_REXX_VEX_C4(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_rexb(xes)) << ((2)); + key += (xed3_operand_get_rexx(xes)) << ((3)); + key += (xed3_operand_get_vex_c4(xes)) << ((4)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MAP_VEX_C4(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_map(xes)) << ((0)); + key += (xed3_operand_get_vex_c4(xes)) << ((4)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_VEX_PREFIX_VL(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_vex_prefix(xes)) << ((0)); + key += (xed3_operand_get_vl(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_DUMMY(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_dummy(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_SCALE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_scale(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_INDEX(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_index(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXX(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_rexx(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXB(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_rexb(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_REXRR(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_rexrr(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_VEX_PREFIX(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_vex_prefix(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_ROUNDC_SAE_VL(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_roundc(xes)) << ((0)); + key += (xed3_operand_get_sae(xes)) << ((3)); + key += (xed3_operand_get_vl(xes)) << ((4)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_VEXDEST4(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_vexdest4(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_ROUNDC(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_roundc(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_SAE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_sae(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BCAST(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_bcast(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_IMM_WIDTH_MODE_UIMM0_1(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_imm_width(xes)) << ((0)); + key += (xed3_operand_get_mode(xes)) << ((7)); + key += (xed3_operand_get_uimm0_1(xes)) << ((9)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ_IMM_WIDTH(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_eosz(xes)) << ((0)); + key += (xed3_operand_get_imm_width(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_IMM_WIDTH(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_imm_width(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BRDISP_WIDTH(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_brdisp_width(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_BRDISP_WIDTH_EOSZ(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_brdisp_width(xes)) << ((0)); + key += (xed3_operand_get_eosz(xes)) << ((6)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_OUTREG(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_outreg(xes)) << ((0)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_MODE_OUTREG(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_mode(xes)) << ((0)); + key += (xed3_operand_get_outreg(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EASZ_OUTREG(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_easz(xes)) << ((0)); + key += (xed3_operand_get_outreg(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_OUTREG_SMODE(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_outreg(xes)) << ((0)); + key += (xed3_operand_get_smode(xes)) << ((9)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ_OUTREG(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_eosz(xes)) << ((0)); + key += (xed3_operand_get_outreg(xes)) << ((2)); + return key; +} +XED_NOINLINE xed_uint64_t xed_enc_lu_EOSZ(xed_encoder_request_t* xes) +{ + xed_uint64_t key = 0; + key += (xed3_operand_get_eosz(xes)) << ((0)); + return key; +} diff --git a/CodeVirtualizer/build/obj/xed-enc-patterns.c b/CodeVirtualizer/build/obj/xed-enc-patterns.c new file mode 100644 index 0000000..ee8b6eb --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-enc-patterns.c @@ -0,0 +1,3117 @@ +/// @file xed-enc-patterns.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encode.h" +#include "xed-encoder.h" +#include "xed-operand-accessors.h" +void xed_encode_instruction_fb_pattern_0(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_reg(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_1(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_2(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_3(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_4(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_reg(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_5(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rm(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_6(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_lock(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_7(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_lock(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_8(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_9(xed_encoder_request_t* xes) +{ + (void)xes; +} +void xed_encode_instruction_fb_pattern_10(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_11(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_reg(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_12(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_lock(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_13(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_osz(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rep(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_14(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_15(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_osz(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_16(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_17(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rexb(xes,*(val+0)); + xed3_operand_set_srm(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_18(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_p4(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); + xed3_operand_set_srm(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_19(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_20(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_21(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); + xed3_operand_set_rm(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_22(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_cet(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rep(xes,*(val+3)); + xed3_operand_set_rm(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_23(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_cet(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rep(xes,*(val+3)); + xed3_operand_set_rexw(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_24(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_cldemote(xes,*(val+0)); + xed3_operand_set_osz(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rep(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_25(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_osz(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rep(xes,*(val+3)); + xed3_operand_set_rm(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_26(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_27(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rep(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_28(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_29(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rep(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_30(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rexb(xes,*(val+0)); + xed3_operand_set_srm(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_31(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_osz(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_32(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rexw(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_33(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_wbnoinvd(xes,*(val+0)); +} +void xed_encode_instruction_fb_pattern_34(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_35(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_osz(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_36(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rep(xes,*(val+0)); + xed3_operand_set_tzcnt(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_37(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); + xed3_operand_set_tzcnt(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_38(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_lzcnt(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_39(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_lzcnt(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_40(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_41(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_42(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_43(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_44(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_vex_prefix(xes,*(val+1)); + xed3_operand_set_vexdest210(xes,*(val+2)); + xed3_operand_set_vexdest3(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_45(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_46(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_47(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_48(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_49(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_rep(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_50(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_osz(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_51(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_mod(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rep(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_52(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_vex_prefix(xes,*(val+1)); + xed3_operand_set_vexvalid(xes,*(val+2)); +} +void xed_encode_instruction_fb_pattern_53(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_54(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_55(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_56(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_zeroing(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_57(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); + xed3_operand_set_zeroing(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_58(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_zeroing(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_59(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_rexw(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexdest210(xes,*(val+6)); + xed3_operand_set_vexdest3(xes,*(val+7)); + xed3_operand_set_vexdest4(xes,*(val+8)); + xed3_operand_set_vexvalid(xes,*(val+9)); + xed3_operand_set_zeroing(xes,*(val+10)); +} +void xed_encode_instruction_fb_pattern_60(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); + xed3_operand_set_zeroing(xes,*(val+9)); +} +void xed_encode_instruction_fb_pattern_61(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_62(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexdest4(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_63(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); + xed3_operand_set_zeroing(xes,*(val+9)); +} +void xed_encode_instruction_fb_pattern_64(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_rexrr(xes,*(val+4)); + xed3_operand_set_rexw(xes,*(val+5)); + xed3_operand_set_vex_prefix(xes,*(val+6)); + xed3_operand_set_vexdest210(xes,*(val+7)); + xed3_operand_set_vexdest3(xes,*(val+8)); + xed3_operand_set_vexdest4(xes,*(val+9)); + xed3_operand_set_vexvalid(xes,*(val+10)); + xed3_operand_set_zeroing(xes,*(val+11)); +} +void xed_encode_instruction_fb_pattern_65(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexdest4(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); + xed3_operand_set_zeroing(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_66(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_rexrr(xes,*(val+3)); + xed3_operand_set_rexw(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexdest210(xes,*(val+6)); + xed3_operand_set_vexdest3(xes,*(val+7)); + xed3_operand_set_vexdest4(xes,*(val+8)); + xed3_operand_set_vexvalid(xes,*(val+9)); + xed3_operand_set_zeroing(xes,*(val+10)); +} +void xed_encode_instruction_fb_pattern_67(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mask(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_zeroing(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_68(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mask(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_zeroing(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_69(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_zeroing(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_70(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_zeroing(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_71(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_rexw(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); + xed3_operand_set_zeroing(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_72(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_zeroing(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_73(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_vex_prefix(xes,*(val+1)); + xed3_operand_set_vexdest210(xes,*(val+2)); + xed3_operand_set_vexdest3(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_vl(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_74(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_75(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_76(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_bcrc(xes,*(val+1)); + xed3_operand_set_map(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_77(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_bcrc(xes,*(val+1)); + xed3_operand_set_map(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_rexw(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexdest210(xes,*(val+6)); + xed3_operand_set_vexdest3(xes,*(val+7)); + xed3_operand_set_vexdest4(xes,*(val+8)); + xed3_operand_set_vexvalid(xes,*(val+9)); +} +void xed_encode_instruction_fb_pattern_78(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_79(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_80(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexdest4(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_81(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexdest4(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); + xed3_operand_set_zeroing(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_82(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexdest4(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_83(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexdest4(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_84(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_85(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_86(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_reg(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_87(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_88(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_reg(xes,*(val+3)); + xed3_operand_set_rexw(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_89(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_90(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_zeroing(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_91(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); + xed3_operand_set_zeroing(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_92(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_reg(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); + xed3_operand_set_zeroing(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_93(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_reg(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_zeroing(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_94(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_vl(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_95(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_rm(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_96(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_rm(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); + xed3_operand_set_zeroing(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_97(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_bcrc(xes,*(val+1)); + xed3_operand_set_map(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_98(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_vex_prefix(xes,*(val+1)); + xed3_operand_set_vexvalid(xes,*(val+2)); + xed3_operand_set_vl(xes,*(val+3)); +} +void xed_encode_instruction_fb_pattern_99(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); + xed3_operand_set_vl(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_100(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); + xed3_operand_set_vl(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_101(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_vl(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_102(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexvalid(xes,*(val+3)); + xed3_operand_set_vl(xes,*(val+4)); +} +void xed_encode_instruction_fb_pattern_103(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_vl(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_104(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_vl(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_105(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_vl(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_106(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_vl(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_107(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); + xed3_operand_set_vl(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_108(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexvalid(xes,*(val+5)); + xed3_operand_set_vl(xes,*(val+6)); +} +void xed_encode_instruction_fb_pattern_109(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_rm(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexdest210(xes,*(val+6)); + xed3_operand_set_vexdest3(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); + xed3_operand_set_vl(xes,*(val+9)); + xed3_operand_set_zeroing(xes,*(val+10)); +} +void xed_encode_instruction_fb_pattern_110(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcast(xes,*(val+0)); + xed3_operand_set_bcrc(xes,*(val+1)); + xed3_operand_set_map(xes,*(val+2)); + xed3_operand_set_mask(xes,*(val+3)); + xed3_operand_set_mod(xes,*(val+4)); + xed3_operand_set_rexw(xes,*(val+5)); + xed3_operand_set_vex_prefix(xes,*(val+6)); + xed3_operand_set_vexdest210(xes,*(val+7)); + xed3_operand_set_vexdest3(xes,*(val+8)); + xed3_operand_set_vexdest4(xes,*(val+9)); + xed3_operand_set_vexvalid(xes,*(val+10)); + xed3_operand_set_zeroing(xes,*(val+11)); +} +void xed_encode_instruction_fb_pattern_111(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mod(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); + xed3_operand_set_zeroing(xes,*(val+9)); +} +void xed_encode_instruction_fb_pattern_112(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_vex_prefix(xes,*(val+2)); + xed3_operand_set_vexdest210(xes,*(val+3)); + xed3_operand_set_vexdest3(xes,*(val+4)); + xed3_operand_set_vexdest4(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); + xed3_operand_set_zeroing(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_113(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_mod(xes,*(val+3)); + xed3_operand_set_rexrr(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexdest210(xes,*(val+6)); + xed3_operand_set_vexdest3(xes,*(val+7)); + xed3_operand_set_vexdest4(xes,*(val+8)); + xed3_operand_set_vexvalid(xes,*(val+9)); + xed3_operand_set_zeroing(xes,*(val+10)); +} +void xed_encode_instruction_fb_pattern_114(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_rep(xes,*(val+0)); + xed3_operand_set_wbnoinvd(xes,*(val+1)); +} +void xed_encode_instruction_fb_pattern_115(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mask(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexvalid(xes,*(val+4)); + xed3_operand_set_zeroing(xes,*(val+5)); +} +void xed_encode_instruction_fb_pattern_116(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_reg(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); + xed3_operand_set_vl(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_117(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_rexw(xes,*(val+1)); + xed3_operand_set_rm(xes,*(val+2)); + xed3_operand_set_vex_prefix(xes,*(val+3)); + xed3_operand_set_vexdest210(xes,*(val+4)); + xed3_operand_set_vexdest3(xes,*(val+5)); + xed3_operand_set_vexvalid(xes,*(val+6)); + xed3_operand_set_vl(xes,*(val+7)); +} +void xed_encode_instruction_fb_pattern_118(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_reg(xes,*(val+2)); + xed3_operand_set_rexw(xes,*(val+3)); + xed3_operand_set_rm(xes,*(val+4)); + xed3_operand_set_vex_prefix(xes,*(val+5)); + xed3_operand_set_vexdest210(xes,*(val+6)); + xed3_operand_set_vexdest3(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); + xed3_operand_set_vl(xes,*(val+9)); +} +void xed_encode_instruction_fb_pattern_119(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_map(xes,*(val+0)); + xed3_operand_set_mod(xes,*(val+1)); + xed3_operand_set_rexw(xes,*(val+2)); + xed3_operand_set_rm(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexvalid(xes,*(val+7)); + xed3_operand_set_vl(xes,*(val+8)); +} +void xed_encode_instruction_fb_pattern_120(xed_encoder_request_t* xes) +{ + const xed_uint8_t* val; + val = xed_encoder_get_start_field_value(xes); + xed3_operand_set_bcrc(xes,*(val+0)); + xed3_operand_set_map(xes,*(val+1)); + xed3_operand_set_mask(xes,*(val+2)); + xed3_operand_set_rexrr(xes,*(val+3)); + xed3_operand_set_vex_prefix(xes,*(val+4)); + xed3_operand_set_vexdest210(xes,*(val+5)); + xed3_operand_set_vexdest3(xes,*(val+6)); + xed3_operand_set_vexdest4(xes,*(val+7)); + xed3_operand_set_vexvalid(xes,*(val+8)); + xed3_operand_set_zeroing(xes,*(val+9)); +} +void xed_encode_instruction_emit_pattern_0(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_1(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); +} +void xed_encode_instruction_emit_pattern_2(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_SIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_3(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_SIMMz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_4(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_SIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_5(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_SIMMz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_6(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_SIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_7(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_SIMMz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_8(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_9(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_10(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_11(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_12(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_13(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); +} +void xed_encode_instruction_emit_pattern_14(xed_encoder_request_t* xes) +{ + xed_encoder_request_encode_emit(xes,5,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_srm(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_15(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_16(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ONE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_17(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_ONE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_18(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_19(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); +} +void xed_encode_instruction_emit_pattern_20(xed_encoder_request_t* xes) +{ + xed_encoder_request_encode_emit(xes,5,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_srm(xes)); +} +void xed_encode_instruction_emit_pattern_21(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_CET_NO_TRACK_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_22(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xes); + xed_encode_nonterminal_CET_NO_TRACK_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_23(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRDISPz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_24(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRDISP32_EMIT(xes); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_FORCE64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_25(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_FORCE64_EMIT(xes); + xed_encode_nonterminal_BRDISP32_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_26(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRDISP8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_27(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_FORCE64_EMIT(xes); + xed_encode_nonterminal_BRDISP8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_28(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRDISPz_EMIT(xes); + xed_encode_nonterminal_UIMM16_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_29(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_SIMMz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_30(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_SIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_31(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FORCE64_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_32(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_33(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_34(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_35(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_IGNORE66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_36(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_IMMUNE66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_37(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_MEMDISPv_EMIT(xes); + xed_encode_nonterminal_OVERRIDE_SEG0_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_38(xed_encoder_request_t* xes) +{ + xed_encoder_request_encode_emit(xes,5,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_srm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_39(xed_encoder_request_t* xes) +{ + xed_encoder_request_encode_emit(xes,5,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_srm(xes)); + xed_encode_nonterminal_UIMMv_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_40(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_41(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_42(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_OVERRIDE_SEG0_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_43(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_FORCE64_EMIT(xes); + xed_encode_nonterminal_BRANCH_HINT_EMIT(xes); + xed_encode_nonterminal_BRDISP8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_44(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRANCH_HINT_EMIT(xes); + xed_encode_nonterminal_BRDISP8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_45(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_FORCE64_EMIT(xes); + xed_encode_nonterminal_BRANCH_HINT_EMIT(xes); + xed_encode_nonterminal_BRDISP32_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_46(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRANCH_HINT_EMIT(xes); + xed_encode_nonterminal_BRDISPz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_47(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_REMOVE_SEGMENT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_48(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_49(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_OVERRIDE_SEG1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_50(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_UIMM16_EMIT(xes); + xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_51(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_52(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_UIMM16_EMIT(xes); + xed_encode_nonterminal_UIMM8_1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_53(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_UIMM16_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_54(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_DF64_EMIT(xes); + xed_encode_nonterminal_BRDISP8_EMIT(xes); + xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_55(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_BRDISP8_EMIT(xes); + xed_encode_nonterminal_FORCE64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_56(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_IMMUNE_REXW_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_57(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_IMMUNE_REXW_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_58(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_FORCE64_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_59(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); +} +void xed_encode_instruction_emit_pattern_60(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_IGNORE66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_61(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_CR_WIDTH_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_62(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_63(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_IGNORE66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_64(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_IGNORE66_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_65(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_OVERRIDE_SEG0_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_66(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_OVERRIDE_SEG0_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_67(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_68(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_CR_WIDTH_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_69(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_encode_emit(xes,5,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_srm(xes)); +} +void xed_encode_instruction_emit_pattern_70(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_71(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); +} +void xed_encode_instruction_emit_pattern_72(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_73(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_74(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_75(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_76(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_77(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_78(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_79(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_80(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_81(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); +} +void xed_encode_instruction_emit_pattern_82(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_IMMUNE66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_83(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x3a); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_IMMUNE66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_84(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_CR_WIDTH_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_85(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 8, 0x0); +} +void xed_encode_instruction_emit_pattern_86(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 8, 0x40); + xed_encoder_request_encode_emit(xes, 8, 0x0); +} +void xed_encode_instruction_emit_pattern_87(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 8, 0x44); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); +} +void xed_encode_instruction_emit_pattern_88(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 8, 0x80); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); +} +void xed_encode_instruction_emit_pattern_89(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 8, 0x84); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); + xed_encoder_request_encode_emit(xes, 8, 0x0); +} +void xed_encode_instruction_emit_pattern_90(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); +} +void xed_encode_instruction_emit_pattern_91(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); +} +void xed_encode_instruction_emit_pattern_92(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_IGNORE66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_93(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_UIMM8_1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_94(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encode_nonterminal_REFINING66_EMIT(xes); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); +} +void xed_encode_instruction_emit_pattern_95(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_UIMM8_1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_96(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_SE_IMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_97(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_SE_IMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_98(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM32_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_99(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UIMM32_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_100(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_REFINING66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_101(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN512_EMIT(xes); + xed_encode_nonterminal_AVX512_ROUND_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_102(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULL_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_103(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULL_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_104(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_AVX512_ROUND_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_105(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_106(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_107(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN512_EMIT(xes); + xed_encode_nonterminal_SAE_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_108(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULL_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_109(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULL_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_110(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_SAE_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_111(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_112(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_113(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_114(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_SAE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_115(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_116(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_117(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN512_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_118(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_HALF_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_119(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN512_EMIT(xes); + xed_encode_nonterminal_SAE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_120(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_121(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_122(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_123(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_124(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_125(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_126(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_127(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE1_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_128(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_129(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_130(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_131(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_132(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_133(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_134(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_MOVDDUP_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_135(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_136(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_137(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_138(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_MEM128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_139(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_MEM128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_140(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_MEM128_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_141(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_142(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_143(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE2_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_144(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_HALFMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_145(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_QUARTERMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_146(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_EIGHTHMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_147(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_HALFMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_148(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_QUARTERMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_149(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_HALFMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_150(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BYTE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_151(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_WORD_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_152(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_153(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_BYTE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_154(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_WORD_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_155(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_156(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_157(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_128_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_158(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_HALFMEM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_159(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_VMODRM_XMM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_160(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UISA_VMODRM_YMM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_161(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UISA_VMODRM_XMM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_162(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_VMODRM_YMM_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_163(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UISA_VMODRM_ZMM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_164(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UISA_VMODRM_XMM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_165(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UISA_VMODRM_YMM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_166(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_UISA_VMODRM_ZMM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_167(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE1_BYTE_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_168(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE1_WORD_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_169(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_BRDISPz_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_170(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_IMMUNE66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_171(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,0x0f); + xed_encoder_request_emit_bytes(xes,8,0x38); + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_IMMUNE66_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_172(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE1_4X_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_173(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE4_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_174(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE4_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_175(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_176(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_177(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE4_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_178(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE4_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_179(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_180(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE2_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_181(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_182(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_TUPLE2_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_183(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_184(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GSCAT_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_185(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULL_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_186(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_187(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_FULL_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_188(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_189(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_UIMM8_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_190(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_HALF_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_191(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_QUARTER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_192(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_193(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_194(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_195(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_196(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xes); + xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_SCALAR_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_197(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xes); +} +void xed_encode_instruction_emit_pattern_198(xed_encoder_request_t* xes) +{ + xed_encoder_request_emit_bytes(xes,8,xed_encoder_get_nominal_opcode(xes)); + xed_encoder_request_encode_emit(xes, 2, xed3_operand_get_mod(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_reg(xes)); + xed_encoder_request_encode_emit(xes, 3, xed3_operand_get_rm(xes)); + xed_encode_nonterminal_MODRM_EMIT(xes); + xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xes); + xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xes); +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-0.c b/CodeVirtualizer/build/obj/xed-encoder-0.c new file mode 100644 index 0000000..907be10 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-0.c @@ -0,0 +1,2985 @@ +/// @file xed-encoder-0.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encoder.h" +#include "xed-encode-private.h" +#include "xed-enc-operand-lu.h" +#include "xed-operand-accessors.h" +xed_bool_t xed_encode_nonterminal_MODRM_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_SIB_REQUIRED_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SIBSCALE_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SIBINDEX_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SIBBASE_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_MODRM_RM_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_MODRM_MOD_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SIB_NT_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_MODRM_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_SIB_NT_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_ISA_ENCODE(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_ISA_BINDINGS(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_ISA_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_ISA_BINDINGS(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_FIXUP_EOSZ_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_FIXUP_EASZ_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_ASZ_NONTERM_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_INSTRUCTIONS_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_OSZ_NONTERM_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_PREFIX_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEXED_REX_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_ISA_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_PREFIX_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEXED_REX_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_INSTRUCTIONS_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_XOP_ENC_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_XOP_TYPE_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXR_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_XOP_REXXB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_XOP_MAP_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REG_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_ESCVL_ENC_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_XOP_ENC_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_XOP_TYPE_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXR_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_XOP_REXXB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_XOP_MAP_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REG_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_ESCVL_ENC_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_NEWVEX_ENC_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VEX_TYPE_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXR_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXXB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_MAP_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REG_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_ESCVL_ENC_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_NEWVEX_ENC_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VEX_TYPE_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXR_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXXB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_MAP_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REG_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_ESCVL_ENC_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_VMODRM_XMM_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_INDEX_XMM_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_VMODRM_YMM_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_INDEX_YMM_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_VMODRM_XMM_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VSIB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_VMODRM_YMM_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VSIB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_EVEX_ENC_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_EVEX_62_REXR_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXX_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXRR_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_MAP_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXW_VVVV_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_UPP_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_LL_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_AVX512_EVEX_BYTE3_ENC_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_EVEX_ENC_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_EVEX_62_REXR_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXX_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXRR_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_MAP_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_REXW_VVVV_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_UPP_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_EVEX_LL_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_AVX512_EVEX_BYTE3_ENC_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_NEWVEX3_ENC_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VEX_TYPE_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXR_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXXB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_MAP_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REG_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_ESCVL_ENC_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_NEWVEX3_ENC_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VEX_TYPE_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXR_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REXXB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_MAP_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_REG_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VEX_ESCVL_ENC_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_ZMM_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_UISA_ENC_INDEX_ZMM_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_YMM_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_UISA_ENC_INDEX_YMM_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_XMM_BIND(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_UISA_ENC_INDEX_XMM_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_VSIB_ENC_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_BIND(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_ZMM_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VSIB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_YMM_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VSIB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_bool_t xed_encode_nonterminal_UISA_VMODRM_XMM_EMIT(xed_encoder_request_t* xes) +{ +xed_bool_t okay; +okay = xed_encode_nonterminal_VSIB_ENC_EMIT(xes); +if (!okay) return 0; +okay = xed_encode_nonterminal_DISP_NT_EMIT(xes); +if (!okay) return 0; +return 1; +} +xed_uint32_t xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t default_seg;} lu_entry_t; +static const lu_entry_t lu_table[108] = { +/*h(0)=0 BASE0=@ -> FB DEFAULT_SEG=0 value=0x0*/ {0, 0}, +/*empty slot1 */ {0,0}, +/*h(1078)=2 BASE0=XED_REG_ESP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1*/ {1078, 1}, +/*h(1617)=3 BASE0=XED_REG_R15 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1617, 0}, +/*h(1083)=4 BASE0=XED_REG_R9D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1083, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1602)=7 BASE0=XED_REG_RAX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1602, 0}, +/*empty slot1 */ {0,0}, +/*h(1607)=9 BASE0=XED_REG_RBP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1*/ {1607, 1}, +/*h(547)=10 BASE0=XED_REG_CX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {547, 0}, +/*h(1086)=11 BASE0=XED_REG_R12D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1086, 0}, +/*h(552)=12 BASE0=XED_REG_SI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {552, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1610)=16 BASE0=XED_REG_R8 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1610, 0}, +/*h(1076)=17 BASE0=XED_REG_EDX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1076, 0}, +/*h(1615)=18 BASE0=XED_REG_R13 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1615, 0}, +/*h(555)=19 BASE0=XED_REG_R9W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {555, 0}, +/*empty slot1 */ {0,0}, +/*h(560)=21 BASE0=XED_REG_R14W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {560, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1079)=24 BASE0=XED_REG_EBP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1*/ {1079, 1}, +/*empty slot1 */ {0,0}, +/*h(1084)=26 BASE0=XED_REG_R10D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1084, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1603)=29 BASE0=XED_REG_RCX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1603, 0}, +/*empty slot1 */ {0,0}, +/*h(1608)=31 BASE0=XED_REG_RSI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1608, 0}, +/*h(548)=32 BASE0=XED_REG_DX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {548, 0}, +/*h(1087)=33 BASE0=XED_REG_R13D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1087, 0}, +/*h(553)=34 BASE0=XED_REG_DI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {553, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1611)=38 BASE0=XED_REG_R9 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1611, 0}, +/*h(1077)=39 BASE0=XED_REG_EBX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1077, 0}, +/*h(1616)=40 BASE0=XED_REG_R14 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1616, 0}, +/*h(556)=41 BASE0=XED_REG_R10W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {556, 0}, +/*h(1024)=42 BASE0=@ -> FB DEFAULT_SEG=0 value=0x0*/ {1024, 0}, +/*h(561)=43 BASE0=XED_REG_R15W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {561, 0}, +/*empty slot1 */ {0,0}, +/*h(1639)=45 BASE0=XED_REG_RIP EASZ=3 -> nothing*/ {1639, -1}, +/*h(1080)=46 BASE0=XED_REG_ESI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1080, 0}, +/*h(546)=47 BASE0=XED_REG_AX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {546, 0}, +/*h(1085)=48 BASE0=XED_REG_R11D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1085, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1604)=51 BASE0=XED_REG_RDX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1604, 0}, +/*empty slot1 */ {0,0}, +/*h(1609)=53 BASE0=XED_REG_RDI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1609, 0}, +/*h(549)=54 BASE0=XED_REG_BX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {549, 0}, +/*h(1088)=55 BASE0=XED_REG_R14D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1088, 0}, +/*h(554)=56 BASE0=XED_REG_R8W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {554, 0}, +/*empty slot1 */ {0,0}, +/*h(1536)=58 BASE0=@ -> FB DEFAULT_SEG=0 value=0x0*/ {1536, 0}, +/*empty slot1 */ {0,0}, +/*h(1612)=60 BASE0=XED_REG_R10 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1612, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(557)=63 BASE0=XED_REG_R11W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {557, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1081)=68 BASE0=XED_REG_EDI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1081, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1605)=73 BASE0=XED_REG_RBX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1605, 0}, +/*empty slot1 */ {0,0}, +/*h(512)=75 BASE0=@ -> FB DEFAULT_SEG=0 value=0x0*/ {512, 0}, +/*h(550)=76 BASE0=XED_REG_SP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1*/ {550, 1}, +/*h(1089)=77 BASE0=XED_REG_R15D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1089, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1074)=81 BASE0=XED_REG_EAX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1074, 0}, +/*h(1613)=82 BASE0=XED_REG_R11 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1613, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(558)=85 BASE0=XED_REG_R12W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {558, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1082)=90 BASE0=XED_REG_R8D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1082, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1606)=95 BASE0=XED_REG_RSP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1*/ {1606, 1}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(551)=98 BASE0=XED_REG_BP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1*/ {551, 1}, +/*empty slot1 */ {0,0}, +/*h(1128)=100 BASE0=XED_REG_EIP EASZ=2 -> nothing*/ {1128, -1}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1075)=103 BASE0=XED_REG_ECX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0*/ {1075, 0}, +/*h(1614)=104 BASE0=XED_REG_R12 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0*/ {1614, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(559)=107 BASE0=XED_REG_R13W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0*/ {559, 0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0_EASZ(xes); +hidx = ((22*key % 167) % 108); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].default_seg >= 0) xed3_operand_set_default_seg(xes,lu_table[hidx].default_seg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_SEGMENT_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t seg_ovd;} lu_entry_t; +static const lu_entry_t lu_table[28] = { +/*h(0)=0 DEFAULT_SEG=0 SEG0=@ -> FB SEG_OVD=0 value=0x0*/ {0, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(612)=6 DEFAULT_SEG=0 SEG0=XED_REG_GS -> FB SEG_OVD=5 value=0x5*/ {612, 5}, +/*empty slot1 */ {0,0}, +/*h(604)=8 DEFAULT_SEG=0 SEG0=XED_REG_DS -> FB SEG_OVD=0 value=0x0*/ {604, 0}, +/*h(596)=9 DEFAULT_SEG=0 SEG0=XED_REG_CS -> FB SEG_OVD=1 value=0x1*/ {596, 1}, +/*h(609)=10 DEFAULT_SEG=1 SEG0=XED_REG_FS -> FB SEG_OVD=4 value=0x4*/ {609, 4}, +/*empty slot1 */ {0,0}, +/*h(601)=12 DEFAULT_SEG=1 SEG0=XED_REG_SS -> FB SEG_OVD=0 value=0x0*/ {601, 0}, +/*h(593)=13 DEFAULT_SEG=1 SEG0=XED_REG_ES -> FB SEG_OVD=3 value=0x3*/ {593, 3}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=17 DEFAULT_SEG=1 SEG0=@ -> FB SEG_OVD=0 value=0x0*/ {1, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(608)=21 DEFAULT_SEG=0 SEG0=XED_REG_FS -> FB SEG_OVD=4 value=0x4*/ {608, 4}, +/*h(600)=22 DEFAULT_SEG=0 SEG0=XED_REG_SS -> FB SEG_OVD=6 value=0x6*/ {600, 6}, +/*h(613)=23 DEFAULT_SEG=1 SEG0=XED_REG_GS -> FB SEG_OVD=5 value=0x5*/ {613, 5}, +/*h(592)=24 DEFAULT_SEG=0 SEG0=XED_REG_ES -> FB SEG_OVD=3 value=0x3*/ {592, 3}, +/*h(605)=25 DEFAULT_SEG=1 SEG0=XED_REG_DS -> FB SEG_OVD=2 value=0x2*/ {605, 2}, +/*empty slot1 */ {0,0}, +/*h(597)=27 DEFAULT_SEG=1 SEG0=XED_REG_CS -> FB SEG_OVD=1 value=0x1*/ {597, 1} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DEFAULT_SEG_SEG0(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 28ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + return 1; +} +else{ + xed3_operand_set_seg_ovd(xes,0); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_SIBBASE_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 NEED_SIB=0 -> nothing*/ {0}, +/*h(1)=1 NEED_SIB=1 -> nt NT[SIBBASE_ENCODE_SIB1]*/ {xed_encode_nonterminal_SIBBASE_ENCODE_SIB1_BIND} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_NEED_SIB(xes); +hidx = key - 0; +if(hidx <= 1) { + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_SIBBASE_ENCODE=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_SIBBASE_ENCODE_SIB1_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t sibbase ;xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[104] = { +/*h(0)=0 BASE0=@ -> nt NT[DISP_WIDTH_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {0, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(548)=3 BASE0=XED_REG_DX EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0*/ {548, 0,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(549)=7 BASE0=XED_REG_BX EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0*/ {549, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(550)=11 BASE0=XED_REG_SP EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0*/ {550, 0,4,0}, +/*h(1024)=12 BASE0=@ -> nt NT[DISP_WIDTH_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {1024, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(1074)=13 BASE0=XED_REG_EAX EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0*/ {1074, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(551)=15 BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {551, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1075)=17 BASE0=XED_REG_ECX EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0*/ {1075, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(552)=19 BASE0=XED_REG_SI EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0*/ {552, 0,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1076)=21 BASE0=XED_REG_EDX EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0*/ {1076, 0,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(553)=23 BASE0=XED_REG_DI EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0*/ {553, 0,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1077)=25 BASE0=XED_REG_EBX EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0*/ {1077, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(554)=27 BASE0=XED_REG_R8W EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1*/ {554, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1078)=29 BASE0=XED_REG_ESP EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0*/ {1078, 0,4,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(555)=31 BASE0=XED_REG_R9W EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1*/ {555, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1079)=33 BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {1079, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(556)=35 BASE0=XED_REG_R10W EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1*/ {556, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1080)=37 BASE0=XED_REG_ESI EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0*/ {1080, 0,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(557)=39 BASE0=XED_REG_R11W EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1*/ {557, 1,3,0}, +/*h(1602)=40 BASE0=XED_REG_RAX EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0*/ {1602, 0,0,0}, +/*h(1081)=41 BASE0=XED_REG_EDI EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0*/ {1081, 0,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(558)=43 BASE0=XED_REG_R12W EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1*/ {558, 1,4,0}, +/*h(1603)=44 BASE0=XED_REG_RCX EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0*/ {1603, 0,1,0}, +/*h(1082)=45 BASE0=XED_REG_R8D EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1*/ {1082, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(559)=47 BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1*/ {559, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*h(1604)=48 BASE0=XED_REG_RDX EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0*/ {1604, 0,2,0}, +/*h(1083)=49 BASE0=XED_REG_R9D EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1*/ {1083, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(560)=51 BASE0=XED_REG_R14W EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1*/ {560, 1,6,0}, +/*h(1605)=52 BASE0=XED_REG_RBX EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0*/ {1605, 0,3,0}, +/*h(1084)=53 BASE0=XED_REG_R10D EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1*/ {1084, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(561)=55 BASE0=XED_REG_R15W EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1*/ {561, 1,7,0}, +/*h(1606)=56 BASE0=XED_REG_RSP EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0*/ {1606, 0,4,0}, +/*h(1085)=57 BASE0=XED_REG_R11D EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1*/ {1085, 1,3,0}, +/*h(512)=58 BASE0=@ -> nt NT[DISP_WIDTH_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {512, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1607)=60 BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {1607, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*h(1086)=61 BASE0=XED_REG_R12D EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1*/ {1086, 1,4,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1608)=64 BASE0=XED_REG_RSI EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0*/ {1608, 0,6,0}, +/*h(1087)=65 BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1*/ {1087, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1609)=68 BASE0=XED_REG_RDI EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0*/ {1609, 0,7,0}, +/*h(1088)=69 BASE0=XED_REG_R14D EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1*/ {1088, 1,6,0}, +/*h(1536)=70 BASE0=@ -> nt NT[DISP_WIDTH_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0*/ {1536, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1610)=72 BASE0=XED_REG_R8 EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1*/ {1610, 1,0,0}, +/*h(1089)=73 BASE0=XED_REG_R15D EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1*/ {1089, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1611)=76 BASE0=XED_REG_R9 EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1*/ {1611, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1612)=80 BASE0=XED_REG_R10 EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1*/ {1612, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1613)=84 BASE0=XED_REG_R11 EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1*/ {1613, 1,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1614)=88 BASE0=XED_REG_R12 EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1*/ {1614, 1,4,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(546)=90 BASE0=XED_REG_AX EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0*/ {546, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1615)=92 BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1*/ {1615, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(547)=94 BASE0=XED_REG_CX EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0*/ {547, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1616)=96 BASE0=XED_REG_R14 EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1*/ {1616, 1,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1617)=100 BASE0=XED_REG_R15 EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1*/ {1617, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_BASE0_EASZ(xes); +hidx = ((4*key % 199) % 104); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_sibbase(xes,lu_table[hidx].sibbase); + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_SIBBASE_ENCODE_SIB1=hidx+1; + return res; + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_SIBINDEX_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 NEED_SIB=0 -> nothing*/ {0}, +/*h(1)=1 NEED_SIB=1 -> nt NT[SIBINDEX_ENCODE_SIB1]*/ {xed_encode_nonterminal_SIBINDEX_ENCODE_SIB1_BIND} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_NEED_SIB(xes); +hidx = key - 0; +if(hidx <= 1) { + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_SIBINDEX_ENCODE=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_SIBINDEX_ENCODE_SIB1_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexx ;xed_int8_t sibindex;} lu_entry_t; +static const lu_entry_t lu_table[98] = { +/*h(0)=0 INDEX=@ -> FB SIBINDEX=4 value=0x4 FB REXX=0 value=0x0*/ {0, 0,4}, +/*h(319)=1 INDEX=XED_REG_R13 EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1*/ {319, 1,5}, +/*h(291)=2 INDEX=XED_REG_RSI EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0*/ {291, 0,6}, +/*h(197)=3 INDEX=XED_REG_R15W EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1*/ {197, 1,7}, +/*h(169)=4 INDEX=XED_REG_R8W EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1*/ {169, 1,0}, +/*h(141)=5 INDEX=XED_REG_CX EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0*/ {141, 0,1}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(189)=8 INDEX=XED_REG_R13W EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1*/ {189, 1,5}, +/*h(161)=9 INDEX=XED_REG_SI EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0*/ {161, 0,6}, +/*h(1)=10 INDEX=@ -> FB SIBINDEX=4 value=0x4 FB REXX=0 value=0x0*/ {1, 0,4}, +/*h(254)=11 INDEX=XED_REG_R13D EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1*/ {254, 1,5}, +/*h(226)=12 INDEX=XED_REG_ESI EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0*/ {226, 0,6}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(246)=16 INDEX=XED_REG_R11D EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1*/ {246, 1,3}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(311)=19 INDEX=XED_REG_R11 EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1*/ {311, 1,3}, +/*h(2)=20 INDEX=@ -> FB SIBINDEX=4 value=0x4 FB REXX=0 value=0x0*/ {2, 0,4}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(303)=24 INDEX=XED_REG_R9 EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1*/ {303, 1,1}, +/*h(275)=25 INDEX=XED_REG_RDX EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0*/ {275, 0,2}, +/*h(181)=26 INDEX=XED_REG_R11W EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1*/ {181, 1,3}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(3)=30 INDEX=@ -> FB SIBINDEX=4 value=0x4 FB REXX=0 value=0x0*/ {3, 0,4}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(238)=34 INDEX=XED_REG_R9D EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1*/ {238, 1,1}, +/*h(210)=35 INDEX=XED_REG_EDX EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0*/ {210, 0,2}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(323)=41 INDEX=XED_REG_R14 EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1*/ {323, 1,6}, +/*h(295)=42 INDEX=XED_REG_RDI EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0*/ {295, 0,7}, +/*h(267)=43 INDEX=XED_REG_RAX EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0*/ {267, 0,0}, +/*h(173)=44 INDEX=XED_REG_R9W EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1*/ {173, 1,1}, +/*h(145)=45 INDEX=XED_REG_DX EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0*/ {145, 0,2}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(193)=48 INDEX=XED_REG_R14W EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1*/ {193, 1,6}, +/*h(165)=49 INDEX=XED_REG_DI EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0*/ {165, 0,7}, +/*h(137)=50 INDEX=XED_REG_AX EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0*/ {137, 0,0}, +/*h(258)=51 INDEX=XED_REG_R14D EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1*/ {258, 1,6}, +/*h(230)=52 INDEX=XED_REG_EDI EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0*/ {230, 0,7}, +/*h(202)=53 INDEX=XED_REG_EAX EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0*/ {202, 0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(250)=56 INDEX=XED_REG_R12D EASZ=2 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1*/ {250, 1,4}, +/*h(222)=57 INDEX=XED_REG_EBP EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0*/ {222, 0,5}, +/*empty slot1 */ {0,0,0}, +/*h(315)=59 INDEX=XED_REG_R12 EASZ=3 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1*/ {315, 1,4}, +/*h(287)=60 INDEX=XED_REG_RBP EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0*/ {287, 0,5}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(307)=64 INDEX=XED_REG_R10 EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1*/ {307, 1,2}, +/*h(279)=65 INDEX=XED_REG_RBX EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0*/ {279, 0,3}, +/*h(185)=66 INDEX=XED_REG_R12W EASZ=1 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1*/ {185, 1,4}, +/*h(157)=67 INDEX=XED_REG_BP EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0*/ {157, 0,5}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(242)=74 INDEX=XED_REG_R10D EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1*/ {242, 1,2}, +/*h(214)=75 INDEX=XED_REG_EBX EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0*/ {214, 0,3}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(327)=81 INDEX=XED_REG_R15 EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1*/ {327, 1,7}, +/*h(299)=82 INDEX=XED_REG_R8 EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1*/ {299, 1,0}, +/*h(271)=83 INDEX=XED_REG_RCX EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0*/ {271, 0,1}, +/*h(177)=84 INDEX=XED_REG_R10W EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1*/ {177, 1,2}, +/*h(149)=85 INDEX=XED_REG_BX EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0*/ {149, 0,3}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(262)=91 INDEX=XED_REG_R15D EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1*/ {262, 1,7}, +/*h(234)=92 INDEX=XED_REG_R8D EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1*/ {234, 1,0}, +/*h(206)=93 INDEX=XED_REG_ECX EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0*/ {206, 0,1}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_EASZ_INDEX(xes); +hidx = ((10*key % 281) % 98); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_SIBSCALE_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t sibscale;} lu_entry_t; +static const lu_entry_t lu_table[34] = { +/*h(0)=0 NEED_SIB=0 -> nothing*/ {0, -1}, +/*empty slot1 */ {0,0}, +/*h(26)=2 NEED_SIB=0 -> nothing*/ {26, -1}, +/*h(5)=3 NEED_SIB=1 SCALE=2 -> FB SIBSCALE=1 value=0x1*/ {5, 1}, +/*h(18)=4 NEED_SIB=0 -> nothing*/ {18, -1}, +/*empty slot1 */ {0,0}, +/*h(10)=6 NEED_SIB=0 -> nothing*/ {10, -1}, +/*empty slot1 */ {0,0}, +/*h(2)=8 NEED_SIB=0 -> nothing*/ {2, -1}, +/*empty slot1 */ {0,0}, +/*h(28)=10 NEED_SIB=0 -> nothing*/ {28, -1}, +/*empty slot1 */ {0,0}, +/*h(20)=12 NEED_SIB=0 -> nothing*/ {20, -1}, +/*empty slot1 */ {0,0}, +/*h(12)=14 NEED_SIB=0 -> nothing*/ {12, -1}, +/*empty slot1 */ {0,0}, +/*h(4)=16 NEED_SIB=0 -> nothing*/ {4, -1}, +/*h(17)=17 NEED_SIB=1 SCALE=8 -> FB SIBSCALE=3 value=0x3*/ {17, 3}, +/*h(30)=18 NEED_SIB=0 -> nothing*/ {30, -1}, +/*h(9)=19 NEED_SIB=1 SCALE=4 -> FB SIBSCALE=2 value=0x2*/ {9, 2}, +/*h(22)=20 NEED_SIB=0 -> nothing*/ {22, -1}, +/*h(1)=21 NEED_SIB=1 SCALE=0 -> FB SIBSCALE=0 value=0x0*/ {1, 0}, +/*h(14)=22 NEED_SIB=0 -> nothing*/ {14, -1}, +/*empty slot1 */ {0,0}, +/*h(6)=24 NEED_SIB=0 -> nothing*/ {6, -1}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(24)=28 NEED_SIB=0 -> nothing*/ {24, -1}, +/*h(3)=29 NEED_SIB=1 SCALE=1 -> FB SIBSCALE=0 value=0x0*/ {3, 0}, +/*h(16)=30 NEED_SIB=0 -> nothing*/ {16, -1}, +/*empty slot1 */ {0,0}, +/*h(8)=32 NEED_SIB=0 -> nothing*/ {8, -1}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_NEED_SIB_SCALE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 34ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].sibscale >= 0) xed3_operand_set_sibscale(xes,lu_table[hidx].sibscale); + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(264)=0 EASZ=2 DISP_WIDTH=8 -> nt NT[MODRM_MOD_EA32_DISP8]*/ {264, xed_encode_nonterminal_MODRM_MOD_EA32_DISP8_BIND}, +/*h(416)=1 EASZ=3 DISP_WIDTH=32 -> nt NT[MODRM_MOD_EA64_DISP32]*/ {416, xed_encode_nonterminal_MODRM_MOD_EA64_DISP32_BIND}, +/*h(144)=2 EASZ=1 DISP_WIDTH=16 -> nt NT[MODRM_MOD_EA16_DISP16]*/ {144, xed_encode_nonterminal_MODRM_MOD_EA16_DISP16_BIND}, +/*h(256)=3 EASZ=2 DISP_WIDTH=0 -> nt NT[MODRM_MOD_EA32_DISP0]*/ {256, xed_encode_nonterminal_MODRM_MOD_EA32_DISP0_BIND}, +/*h(448)=4 EASZ=3 DISP_WIDTH=64 -> nt NT[ERROR]*/ {448, xed_encode_nonterminal_ERROR_BIND}, +/*h(136)=5 EASZ=1 DISP_WIDTH=8 -> nt NT[MODRM_MOD_EA16_DISP8]*/ {136, xed_encode_nonterminal_MODRM_MOD_EA16_DISP8_BIND}, +/*h(288)=6 EASZ=2 DISP_WIDTH=32 -> nt NT[MODRM_MOD_EA32_DISP32]*/ {288, xed_encode_nonterminal_MODRM_MOD_EA32_DISP32_BIND}, +/*h(400)=7 EASZ=3 DISP_WIDTH=16 -> nt NT[ERROR]*/ {400, xed_encode_nonterminal_ERROR_BIND}, +/*h(128)=8 EASZ=1 DISP_WIDTH=0 -> nt NT[MODRM_MOD_EA16_DISP0]*/ {128, xed_encode_nonterminal_MODRM_MOD_EA16_DISP0_BIND}, +/*h(320)=9 EASZ=2 DISP_WIDTH=64 -> nt NT[ERROR]*/ {320, xed_encode_nonterminal_ERROR_BIND}, +/*h(392)=10 EASZ=3 DISP_WIDTH=8 -> nt NT[MODRM_MOD_EA64_DISP8]*/ {392, xed_encode_nonterminal_MODRM_MOD_EA64_DISP8_BIND}, +/*h(160)=11 EASZ=1 DISP_WIDTH=32 -> nt NT[ERROR]*/ {160, xed_encode_nonterminal_ERROR_BIND}, +/*h(272)=12 EASZ=2 DISP_WIDTH=16 -> nt NT[ERROR]*/ {272, xed_encode_nonterminal_ERROR_BIND}, +/*h(384)=13 EASZ=3 DISP_WIDTH=0 -> nt NT[MODRM_MOD_EA64_DISP0]*/ {384, xed_encode_nonterminal_MODRM_MOD_EA64_DISP0_BIND}, +/*h(192)=14 EASZ=1 DISP_WIDTH=64 -> nt NT[ERROR]*/ {192, xed_encode_nonterminal_ERROR_BIND} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_DISP_WIDTH_EASZ(xes); +hidx = ((5*key % 43) % 15); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_MODRM_MOD_ENCODE=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t disp ;xed_int8_t disp_width ;xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(37)=0 BASE0=XED_REG_BX INDEX=@ -> FB MOD=0 value=0x0*/ {37, -1,-1,0}, +/*h(21029)=1 BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB MOD=0 value=0x0*/ {21029, -1,-1,0}, +/*h(20517)=2 BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB MOD=0 value=0x0*/ {20517, -1,-1,0}, +/*h(39)=3 BASE0=XED_REG_BP INDEX=@ -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0*/ {39, 0,8,1}, +/*h(21031)=4 BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB MOD=0 value=0x0*/ {21031, -1,-1,0}, +/*h(20519)=5 BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB MOD=0 value=0x0*/ {20519, -1,-1,0}, +/*h(41)=6 BASE0=XED_REG_DI INDEX=@ -> FB MOD=0 value=0x0*/ {41, -1,-1,0}, +/*h(40)=7 BASE0=XED_REG_SI INDEX=@ -> FB MOD=0 value=0x0*/ {40, -1,-1,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0_INDEX(xes); +hidx = ((20*key % 37) % 8); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].disp >= 0) xed3_operand_set_disp(xes,lu_table[hidx].disp); + if(lu_table[hidx].disp_width >= 0) xed3_operand_set_disp_width(xes,lu_table[hidx].disp_width); + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP8_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(37)=0 BASE0=XED_REG_BX INDEX=@ -> FB MOD=1 value=0x1*/ {37, 1}, +/*h(21029)=1 BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB MOD=1 value=0x1*/ {21029, 1}, +/*h(20517)=2 BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB MOD=1 value=0x1*/ {20517, 1}, +/*h(39)=3 BASE0=XED_REG_BP INDEX=@ -> FB MOD=1 value=0x1*/ {39, 1}, +/*h(21031)=4 BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB MOD=1 value=0x1*/ {21031, 1}, +/*h(20519)=5 BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB MOD=1 value=0x1*/ {20519, 1}, +/*h(41)=6 BASE0=XED_REG_DI INDEX=@ -> FB MOD=1 value=0x1*/ {41, 1}, +/*h(40)=7 BASE0=XED_REG_SI INDEX=@ -> FB MOD=1 value=0x1*/ {40, 1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0_INDEX(xes); +hidx = ((20*key % 37) % 8); +if(lu_table[hidx].key == key) { + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP16_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(0)=0 BASE0=@ INDEX=@ -> FB MOD=0 value=0x0*/ {0, 0}, +/*h(39)=1 BASE0=XED_REG_BP INDEX=@ -> FB MOD=2 value=0x2*/ {39, 2}, +/*h(40)=2 BASE0=XED_REG_SI INDEX=@ -> FB MOD=2 value=0x2*/ {40, 2}, +/*h(41)=3 BASE0=XED_REG_DI INDEX=@ -> FB MOD=2 value=0x2*/ {41, 2}, +/*h(21029)=4 BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB MOD=2 value=0x2*/ {21029, 2}, +/*h(20517)=5 BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB MOD=2 value=0x2*/ {20517, 2}, +/*h(21031)=6 BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB MOD=2 value=0x2*/ {21031, 2}, +/*h(20519)=7 BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB MOD=2 value=0x2*/ {20519, 2}, +/*h(37)=8 BASE0=XED_REG_BX INDEX=@ -> FB MOD=2 value=0x2*/ {37, 2} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0_INDEX(xes); +hidx = ((30*key % 29) % 9); +if(lu_table[hidx].key == key) { + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t disp ;xed_int8_t disp_width ;xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[24] = { +/*h(566)=0 BASE0=XED_REG_ESP MODE=1 -> FB MOD=0 value=0x0*/ {566, -1,-1,0}, +/*h(1075)=1 BASE0=XED_REG_ECX MODE=2 -> FB MOD=0 value=0x0*/ {1075, -1,-1,0}, +/*h(1080)=2 BASE0=XED_REG_ESI MODE=2 -> FB MOD=0 value=0x0*/ {1080, -1,-1,0}, +/*h(1085)=3 BASE0=XED_REG_R11D MODE=2 -> FB MOD=0 value=0x0*/ {1085, -1,-1,0}, +/*h(562)=4 BASE0=XED_REG_EAX MODE=1 -> FB MOD=0 value=0x0*/ {562, -1,-1,0}, +/*h(567)=5 BASE0=XED_REG_EBP MODE=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0*/ {567, 0,8,1}, +/*h(1076)=6 BASE0=XED_REG_EDX MODE=2 -> FB MOD=0 value=0x0*/ {1076, -1,-1,0}, +/*h(1081)=7 BASE0=XED_REG_EDI MODE=2 -> FB MOD=0 value=0x0*/ {1081, -1,-1,0}, +/*h(1086)=8 BASE0=XED_REG_R12D MODE=2 -> FB MOD=0 value=0x0*/ {1086, -1,-1,0}, +/*h(563)=9 BASE0=XED_REG_ECX MODE=1 -> FB MOD=0 value=0x0*/ {563, -1,-1,0}, +/*h(568)=10 BASE0=XED_REG_ESI MODE=1 -> FB MOD=0 value=0x0*/ {568, -1,-1,0}, +/*h(1077)=11 BASE0=XED_REG_EBX MODE=2 -> FB MOD=0 value=0x0*/ {1077, -1,-1,0}, +/*h(1082)=12 BASE0=XED_REG_R8D MODE=2 -> FB MOD=0 value=0x0*/ {1082, -1,-1,0}, +/*h(1087)=13 BASE0=XED_REG_R13D MODE=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0*/ {1087, 0,8,1}, +/*h(564)=14 BASE0=XED_REG_EDX MODE=1 -> FB MOD=0 value=0x0*/ {564, -1,-1,0}, +/*h(569)=15 BASE0=XED_REG_EDI MODE=1 -> FB MOD=0 value=0x0*/ {569, -1,-1,0}, +/*h(1078)=16 BASE0=XED_REG_ESP MODE=2 -> FB MOD=0 value=0x0*/ {1078, -1,-1,0}, +/*h(1083)=17 BASE0=XED_REG_R9D MODE=2 -> FB MOD=0 value=0x0*/ {1083, -1,-1,0}, +/*h(1088)=18 BASE0=XED_REG_R14D MODE=2 -> FB MOD=0 value=0x0*/ {1088, -1,-1,0}, +/*h(565)=19 BASE0=XED_REG_EBX MODE=1 -> FB MOD=0 value=0x0*/ {565, -1,-1,0}, +/*h(1074)=20 BASE0=XED_REG_EAX MODE=2 -> FB MOD=0 value=0x0*/ {1074, -1,-1,0}, +/*h(1079)=21 BASE0=XED_REG_EBP MODE=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0*/ {1079, 0,8,1}, +/*h(1084)=22 BASE0=XED_REG_R10D MODE=2 -> FB MOD=0 value=0x0*/ {1084, -1,-1,0}, +/*h(1089)=23 BASE0=XED_REG_R15D MODE=2 -> FB MOD=0 value=0x0*/ {1089, -1,-1,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0_MODE(xes); +hidx = ((5*key % 107) % 24); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].disp >= 0) xed3_operand_set_disp(xes,lu_table[hidx].disp); + if(lu_table[hidx].disp_width >= 0) xed3_operand_set_disp_width(xes,lu_table[hidx].disp_width); + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP8_BIND(xed_encoder_request_t* xes) +{ +xed3_operand_set_mod(xes,1); +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP32_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[228] = { +/*h(0)=0 BASE0=@ -> FB MOD=0 value=0x0*/ {0, 0}, +/*empty slot1 */ {0,0}, +/*h(7680)=2 BASE0=@ -> FB MOD=0 value=0x0*/ {7680, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(7168)=11 BASE0=@ -> FB MOD=0 value=0x0*/ {7168, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(6656)=20 BASE0=@ -> FB MOD=0 value=0x0*/ {6656, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(6144)=29 BASE0=@ -> FB MOD=0 value=0x0*/ {6144, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5632)=38 BASE0=@ -> FB MOD=0 value=0x0*/ {5632, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5735)=41 MODE=2 BASE0=XED_REG_RIP EASZ=3 -> FB MOD=0 value=0x0*/ {5735, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5120)=47 BASE0=@ -> FB MOD=0 value=0x0*/ {5120, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(4608)=56 BASE0=@ -> FB MOD=0 value=0x0*/ {4608, 0}, +/*empty slot1 */ {0,0}, +/*h(5224)=58 MODE=2 BASE0=XED_REG_EIP EASZ=2 -> FB MOD=0 value=0x0*/ {5224, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(4096)=65 BASE0=@ -> FB MOD=0 value=0x0*/ {4096, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5682)=73 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {5682, 2}, +/*h(3584)=74 BASE0=@ -> FB MOD=0 value=0x0*/ {3584, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5683)=81 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {5683, 2}, +/*h(5170)=82 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {5170, 2}, +/*h(3072)=83 BASE0=@ -> FB MOD=0 value=0x0*/ {3072, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5684)=89 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {5684, 2}, +/*h(5171)=90 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {5171, 2}, +/*h(4658)=91 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {4658, 2}, +/*h(2560)=92 BASE0=@ -> FB MOD=0 value=0x0*/ {2560, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5685)=97 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {5685, 2}, +/*h(5172)=98 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {5172, 2}, +/*h(4659)=99 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {4659, 2}, +/*h(4146)=100 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {4146, 2}, +/*h(2048)=101 BASE0=@ -> FB MOD=0 value=0x0*/ {2048, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5686)=105 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {5686, 2}, +/*h(5173)=106 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {5173, 2}, +/*h(4660)=107 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {4660, 2}, +/*h(4147)=108 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {4147, 2}, +/*h(3634)=109 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {3634, 2}, +/*h(1536)=110 BASE0=@ -> FB MOD=0 value=0x0*/ {1536, 0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5687)=113 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {5687, 2}, +/*h(5174)=114 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {5174, 2}, +/*h(4661)=115 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {4661, 2}, +/*h(4148)=116 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {4148, 2}, +/*h(3635)=117 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {3635, 2}, +/*h(3122)=118 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {3122, 2}, +/*h(1024)=119 BASE0=@ -> FB MOD=0 value=0x0*/ {1024, 0}, +/*empty slot1 */ {0,0}, +/*h(5688)=121 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {5688, 2}, +/*h(5175)=122 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {5175, 2}, +/*h(4662)=123 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {4662, 2}, +/*h(4149)=124 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {4149, 2}, +/*h(3636)=125 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {3636, 2}, +/*h(3123)=126 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {3123, 2}, +/*h(2610)=127 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {2610, 2}, +/*h(512)=128 BASE0=@ -> FB MOD=0 value=0x0*/ {512, 0}, +/*h(5689)=129 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {5689, 2}, +/*h(5176)=130 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {5176, 2}, +/*h(4663)=131 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {4663, 2}, +/*h(4150)=132 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {4150, 2}, +/*h(3637)=133 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {3637, 2}, +/*h(3124)=134 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {3124, 2}, +/*h(2611)=135 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {2611, 2}, +/*h(2098)=136 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2*/ {2098, 2}, +/*h(5690)=137 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2*/ {5690, 2}, +/*h(5177)=138 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {5177, 2}, +/*h(4664)=139 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {4664, 2}, +/*h(4151)=140 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {4151, 2}, +/*h(3638)=141 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {3638, 2}, +/*h(3125)=142 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {3125, 2}, +/*h(2612)=143 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {2612, 2}, +/*h(2099)=144 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2*/ {2099, 2}, +/*h(5691)=145 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2*/ {5691, 2}, +/*h(5178)=146 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2*/ {5178, 2}, +/*h(4665)=147 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {4665, 2}, +/*h(4152)=148 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {4152, 2}, +/*h(3639)=149 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {3639, 2}, +/*h(3126)=150 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {3126, 2}, +/*h(2613)=151 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {2613, 2}, +/*h(2100)=152 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2*/ {2100, 2}, +/*h(5692)=153 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2*/ {5692, 2}, +/*h(5179)=154 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2*/ {5179, 2}, +/*h(4666)=155 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2*/ {4666, 2}, +/*h(4153)=156 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {4153, 2}, +/*h(3640)=157 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {3640, 2}, +/*h(3127)=158 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {3127, 2}, +/*h(2614)=159 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {2614, 2}, +/*h(2101)=160 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2*/ {2101, 2}, +/*h(5693)=161 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2*/ {5693, 2}, +/*h(5180)=162 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2*/ {5180, 2}, +/*h(4667)=163 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2*/ {4667, 2}, +/*h(4154)=164 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2*/ {4154, 2}, +/*h(3641)=165 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {3641, 2}, +/*h(3128)=166 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {3128, 2}, +/*h(2615)=167 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {2615, 2}, +/*h(2102)=168 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2*/ {2102, 2}, +/*h(5694)=169 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2*/ {5694, 2}, +/*h(5181)=170 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2*/ {5181, 2}, +/*h(4668)=171 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2*/ {4668, 2}, +/*h(4155)=172 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2*/ {4155, 2}, +/*empty slot1 */ {0,0}, +/*h(3129)=174 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {3129, 2}, +/*h(2616)=175 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {2616, 2}, +/*h(2103)=176 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2*/ {2103, 2}, +/*h(5695)=177 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2*/ {5695, 2}, +/*h(5182)=178 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2*/ {5182, 2}, +/*h(4669)=179 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2*/ {4669, 2}, +/*h(4156)=180 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2*/ {4156, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2617)=183 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {2617, 2}, +/*h(2104)=184 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2*/ {2104, 2}, +/*h(5696)=185 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2*/ {5696, 2}, +/*h(5183)=186 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2*/ {5183, 2}, +/*h(4670)=187 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2*/ {4670, 2}, +/*h(4157)=188 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2*/ {4157, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(2105)=192 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2*/ {2105, 2}, +/*h(5697)=193 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2*/ {5697, 2}, +/*h(5184)=194 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2*/ {5184, 2}, +/*h(4671)=195 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2*/ {4671, 2}, +/*h(4158)=196 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2*/ {4158, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(5185)=202 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2*/ {5185, 2}, +/*h(4672)=203 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2*/ {4672, 2}, +/*h(4159)=204 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2*/ {4159, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(4673)=211 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2*/ {4673, 2}, +/*h(4160)=212 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2*/ {4160, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(4161)=220 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2*/ {4161, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0_EASZ_MODE(xes); +hidx = ((8*key % 821) % 228); +if(lu_table[hidx].key == key) { + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t disp ;xed_int8_t disp_width ;xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[26] = { +/*h(68)=0 BASE0=XED_REG_RDX -> FB MOD=0 value=0x0*/ {68, -1,-1,0}, +/*h(81)=1 BASE0=XED_REG_R15 -> FB MOD=0 value=0x0*/ {81, -1,-1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(73)=3 BASE0=XED_REG_RDI -> FB MOD=0 value=0x0*/ {73, -1,-1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(78)=5 BASE0=XED_REG_R12 -> FB MOD=0 value=0x0*/ {78, -1,-1,0}, +/*h(70)=6 BASE0=XED_REG_RSP -> FB MOD=0 value=0x0*/ {70, -1,-1,0}, +/*h(104)=7 BASE0=XED_REG_EIP -> FB MOD=0 value=0x0 FB DISP_WIDTH=32 value=0x20 FB DISP=0 value=0x0*/ {104, 0,32,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(75)=9 BASE0=XED_REG_R9 -> FB MOD=0 value=0x0*/ {75, -1,-1,0}, +/*h(67)=10 BASE0=XED_REG_RCX -> FB MOD=0 value=0x0*/ {67, -1,-1,0}, +/*h(80)=11 BASE0=XED_REG_R14 -> FB MOD=0 value=0x0*/ {80, -1,-1,0}, +/*h(72)=12 BASE0=XED_REG_RSI -> FB MOD=0 value=0x0*/ {72, -1,-1,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(77)=15 BASE0=XED_REG_R11 -> FB MOD=0 value=0x0*/ {77, -1,-1,0}, +/*h(69)=16 BASE0=XED_REG_RBX -> FB MOD=0 value=0x0*/ {69, -1,-1,0}, +/*h(103)=17 BASE0=XED_REG_RIP -> FB MOD=0 value=0x0 FB DISP_WIDTH=32 value=0x20 FB DISP=0 value=0x0*/ {103, 0,32,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(74)=19 BASE0=XED_REG_R8 -> FB MOD=0 value=0x0*/ {74, -1,-1,0}, +/*h(66)=20 BASE0=XED_REG_RAX -> FB MOD=0 value=0x0*/ {66, -1,-1,0}, +/*h(79)=21 BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0*/ {79, 0,8,1}, +/*h(71)=22 BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0*/ {71, 0,8,1}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(76)=25 BASE0=XED_REG_R10 -> FB MOD=0 value=0x0*/ {76, -1,-1,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 26ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].disp >= 0) xed3_operand_set_disp(xes,lu_table[hidx].disp); + if(lu_table[hidx].disp_width >= 0) xed3_operand_set_disp_width(xes,lu_table[hidx].disp_width); + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP8_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 BASE0=XED_REG_RAX -> FB MOD=1 value=0x1*/ {1}, +/*h(67)=1 BASE0=XED_REG_RCX -> FB MOD=1 value=0x1*/ {1}, +/*h(68)=2 BASE0=XED_REG_RDX -> FB MOD=1 value=0x1*/ {1}, +/*h(69)=3 BASE0=XED_REG_RBX -> FB MOD=1 value=0x1*/ {1}, +/*h(70)=4 BASE0=XED_REG_RSP -> FB MOD=1 value=0x1*/ {1}, +/*h(71)=5 BASE0=XED_REG_RBP -> FB MOD=1 value=0x1*/ {1}, +/*h(72)=6 BASE0=XED_REG_RSI -> FB MOD=1 value=0x1*/ {1}, +/*h(73)=7 BASE0=XED_REG_RDI -> FB MOD=1 value=0x1*/ {1}, +/*h(74)=8 BASE0=XED_REG_R8 -> FB MOD=1 value=0x1*/ {1}, +/*h(75)=9 BASE0=XED_REG_R9 -> FB MOD=1 value=0x1*/ {1}, +/*h(76)=10 BASE0=XED_REG_R10 -> FB MOD=1 value=0x1*/ {1}, +/*h(77)=11 BASE0=XED_REG_R11 -> FB MOD=1 value=0x1*/ {1}, +/*h(78)=12 BASE0=XED_REG_R12 -> FB MOD=1 value=0x1*/ {1}, +/*h(79)=13 BASE0=XED_REG_R13 -> FB MOD=1 value=0x1*/ {1}, +/*h(80)=14 BASE0=XED_REG_R14 -> FB MOD=1 value=0x1*/ {1}, +/*h(81)=15 BASE0=XED_REG_R15 -> FB MOD=1 value=0x1*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP32_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t mod;} lu_entry_t; +static const lu_entry_t lu_table[19] = { +/*h(0)=0 BASE0=@ -> FB MOD=0 value=0x0*/ {0, 0}, +/*h(104)=1 BASE0=XED_REG_EIP -> FB MOD=0 value=0x0*/ {104, 0}, +/*h(71)=2 BASE0=XED_REG_RBP -> FB MOD=2 value=0x2*/ {71, 2}, +/*h(73)=3 BASE0=XED_REG_RDI -> FB MOD=2 value=0x2*/ {73, 2}, +/*h(75)=4 BASE0=XED_REG_R9 -> FB MOD=2 value=0x2*/ {75, 2}, +/*h(77)=5 BASE0=XED_REG_R11 -> FB MOD=2 value=0x2*/ {77, 2}, +/*h(79)=6 BASE0=XED_REG_R13 -> FB MOD=2 value=0x2*/ {79, 2}, +/*h(81)=7 BASE0=XED_REG_R15 -> FB MOD=2 value=0x2*/ {81, 2}, +/*h(67)=8 BASE0=XED_REG_RCX -> FB MOD=2 value=0x2*/ {67, 2}, +/*h(69)=9 BASE0=XED_REG_RBX -> FB MOD=2 value=0x2*/ {69, 2}, +/*h(103)=10 BASE0=XED_REG_RIP -> FB MOD=0 value=0x0*/ {103, 0}, +/*h(70)=11 BASE0=XED_REG_RSP -> FB MOD=2 value=0x2*/ {70, 2}, +/*h(72)=12 BASE0=XED_REG_RSI -> FB MOD=2 value=0x2*/ {72, 2}, +/*h(74)=13 BASE0=XED_REG_R8 -> FB MOD=2 value=0x2*/ {74, 2}, +/*h(76)=14 BASE0=XED_REG_R10 -> FB MOD=2 value=0x2*/ {76, 2}, +/*h(78)=15 BASE0=XED_REG_R12 -> FB MOD=2 value=0x2*/ {78, 2}, +/*h(80)=16 BASE0=XED_REG_R14 -> FB MOD=2 value=0x2*/ {80, 2}, +/*h(66)=17 BASE0=XED_REG_RAX -> FB MOD=2 value=0x2*/ {66, 2}, +/*h(68)=18 BASE0=XED_REG_RDX -> FB MOD=2 value=0x2*/ {68, 2} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BASE0(xes); +hidx = ((29*key % 673) % 19); +if(lu_table[hidx].key == key) { + xed3_operand_set_mod(xes,lu_table[hidx].mod); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*empty slot1 */ {0,0}, +/*h(2)=1 EASZ=2 NEED_SIB=0 -> nt NT[MODRM_RM_ENCODE_EA32_SIB0]*/ {2, xed_encode_nonterminal_MODRM_RM_ENCODE_EA32_SIB0_BIND}, +/*h(7)=2 EASZ!=1 NEED_SIB=1 -> nt NT[MODRM_RM_ENCODE_EANOT16_SIB1]*/ {7, xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_BIND}, +/*h(4)=3 EASZ!=1 NEED_SIB=1 -> nt NT[MODRM_RM_ENCODE_EANOT16_SIB1]*/ {4, xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_BIND}, +/*h(1)=4 EASZ=1 NEED_SIB=0 -> nt NT[MODRM_RM_ENCODE_EA16_SIB0]*/ {1, xed_encode_nonterminal_MODRM_RM_ENCODE_EA16_SIB0_BIND}, +/*h(6)=5 EASZ!=1 NEED_SIB=1 -> nt NT[MODRM_RM_ENCODE_EANOT16_SIB1]*/ {6, xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_BIND}, +/*h(3)=6 EASZ=3 NEED_SIB=0 -> nt NT[MODRM_RM_ENCODE_EA64_SIB0]*/ {3, xed_encode_nonterminal_MODRM_RM_ENCODE_EA64_SIB0_BIND}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_EASZ_NEED_SIB(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-3)); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA16_SIB0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t rm ;xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(0)=0 BASE0=@ INDEX=@ -> nt NT[DISP_WIDTH_16] FB RM=6 value=0x6*/ {0, 6,xed_encode_nonterminal_DISP_WIDTH_16_BIND}, +/*h(39)=1 BASE0=XED_REG_BP INDEX=@ -> nt NT[DISP_WIDTH_0_8_16] FB RM=6 value=0x6*/ {39, 6,xed_encode_nonterminal_DISP_WIDTH_0_8_16_BIND}, +/*h(40)=2 BASE0=XED_REG_SI INDEX=@ -> FB RM=4 value=0x4*/ {40, 4,0}, +/*h(41)=3 BASE0=XED_REG_DI INDEX=@ -> FB RM=5 value=0x5*/ {41, 5,0}, +/*h(21029)=4 BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB RM=1 value=0x1*/ {21029, 1,0}, +/*h(20517)=5 BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB RM=0 value=0x0*/ {20517, 0,0}, +/*h(21031)=6 BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB RM=3 value=0x3*/ {21031, 3,0}, +/*h(20519)=7 BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB RM=2 value=0x2*/ {20519, 2,0}, +/*h(37)=8 BASE0=XED_REG_BX INDEX=@ -> FB RM=7 value=0x7*/ {37, 7,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_BASE0_INDEX(xes); +hidx = ((30*key % 29) % 9); +if(lu_table[hidx].key == key) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE_EA16_SIB0=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA64_SIB0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t rm ;xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[17] = { +/*h(0)=0 BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5*/ {0, -1,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(73)=1 BASE0=XED_REG_RDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0*/ {73, 0,7,0}, +/*h(68)=2 BASE0=XED_REG_RDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0*/ {68, 0,2,0}, +/*h(80)=3 BASE0=XED_REG_R14 -> FB RM=6 value=0x6 FB REXB=1 value=0x1*/ {80, 1,6,0}, +/*h(75)=4 BASE0=XED_REG_R9 -> FB RM=1 value=0x1 FB REXB=1 value=0x1*/ {75, 1,1,0}, +/*h(81)=5 BASE0=XED_REG_R15 -> FB RM=7 value=0x7 FB REXB=1 value=0x1*/ {81, 1,7,0}, +/*h(104)=6 BASE0=XED_REG_EIP -> FB RM=5 value=0x5*/ {104, -1,5,0}, +/*h(77)=7 BASE0=XED_REG_R11 -> FB RM=3 value=0x3 FB REXB=1 value=0x1*/ {77, 1,3,0}, +/*h(72)=8 BASE0=XED_REG_RSI -> FB RM=6 value=0x6 FB REXB=0 value=0x0*/ {72, 0,6,0}, +/*h(67)=9 BASE0=XED_REG_RCX -> FB RM=1 value=0x1 FB REXB=0 value=0x0*/ {67, 0,1,0}, +/*h(79)=10 BASE0=XED_REG_R13 -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1*/ {79, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*h(74)=11 BASE0=XED_REG_R8 -> FB RM=0 value=0x0 FB REXB=1 value=0x1*/ {74, 1,0,0}, +/*h(69)=12 BASE0=XED_REG_RBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0*/ {69, 0,3,0}, +/*h(103)=13 BASE0=XED_REG_RIP -> FB RM=5 value=0x5*/ {103, -1,5,0}, +/*h(76)=14 BASE0=XED_REG_R10 -> FB RM=2 value=0x2 FB REXB=1 value=0x1*/ {76, 1,2,0}, +/*h(71)=15 BASE0=XED_REG_RBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0*/ {71, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*h(66)=16 BASE0=XED_REG_RAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0*/ {66, 0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_BASE0(xes); +hidx = ((27*key % 433) % 17); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].rexb >= 0) xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE_EA64_SIB0=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA32_SIB0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t rm ;xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[124] = { +/*h(0)=0 BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5*/ {0, -1,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(1089)=1 BASE0=XED_REG_R15D -> FB RM=7 value=0x7 FB REXB=1 value=0x1*/ {1089, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(577)=3 BASE0=XED_REG_R15D -> FB RM=7 value=0x7 FB REXB=1 value=0x1*/ {577, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(65)=5 BASE0=XED_REG_R15D -> FB RM=7 value=0x7 FB REXB=1 value=0x1*/ {65, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1586)=18 BASE0=XED_REG_EAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0*/ {1586, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1074)=20 BASE0=XED_REG_EAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0*/ {1074, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(562)=22 BASE0=XED_REG_EAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0*/ {562, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(50)=24 BASE0=XED_REG_EAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0*/ {50, 0,0,0}, +/*h(1587)=25 BASE0=XED_REG_ECX -> FB RM=1 value=0x1 FB REXB=0 value=0x0*/ {1587, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1075)=27 BASE0=XED_REG_ECX -> FB RM=1 value=0x1 FB REXB=0 value=0x0*/ {1075, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(563)=29 BASE0=XED_REG_ECX -> FB RM=1 value=0x1 FB REXB=0 value=0x0*/ {563, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(51)=31 BASE0=XED_REG_ECX -> FB RM=1 value=0x1 FB REXB=0 value=0x0*/ {51, 0,1,0}, +/*h(1588)=32 BASE0=XED_REG_EDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0*/ {1588, 0,2,0}, +/*h(1536)=33 BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5*/ {1536, -1,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(1076)=34 BASE0=XED_REG_EDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0*/ {1076, 0,2,0}, +/*h(1024)=35 BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5*/ {1024, -1,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(564)=36 BASE0=XED_REG_EDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0*/ {564, 0,2,0}, +/*h(512)=37 BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5*/ {512, -1,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(52)=38 BASE0=XED_REG_EDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0*/ {52, 0,2,0}, +/*h(1589)=39 BASE0=XED_REG_EBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0*/ {1589, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1077)=41 BASE0=XED_REG_EBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0*/ {1077, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(565)=43 BASE0=XED_REG_EBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0*/ {565, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(53)=45 BASE0=XED_REG_EBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0*/ {53, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1591)=53 BASE0=XED_REG_EBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0*/ {1591, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1079)=55 BASE0=XED_REG_EBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0*/ {1079, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(567)=57 BASE0=XED_REG_EBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0*/ {567, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(55)=59 BASE0=XED_REG_EBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0*/ {55, 0,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*h(1592)=60 BASE0=XED_REG_ESI -> FB RM=6 value=0x6 FB REXB=0 value=0x0*/ {1592, 0,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1080)=62 BASE0=XED_REG_ESI -> FB RM=6 value=0x6 FB REXB=0 value=0x0*/ {1080, 0,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(568)=64 BASE0=XED_REG_ESI -> FB RM=6 value=0x6 FB REXB=0 value=0x0*/ {568, 0,6,0}, +/*h(1127)=65 BASE0=XED_REG_RIP MODE=2 -> FB RM=5 value=0x5*/ {1127, -1,5,0}, +/*h(56)=66 BASE0=XED_REG_ESI -> FB RM=6 value=0x6 FB REXB=0 value=0x0*/ {56, 0,6,0}, +/*h(1593)=67 BASE0=XED_REG_EDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0*/ {1593, 0,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1081)=69 BASE0=XED_REG_EDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0*/ {1081, 0,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(569)=71 BASE0=XED_REG_EDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0*/ {569, 0,7,0}, +/*h(1128)=72 BASE0=XED_REG_EIP MODE=2 -> FB RM=5 value=0x5*/ {1128, -1,5,0}, +/*h(57)=73 BASE0=XED_REG_EDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0*/ {57, 0,7,0}, +/*h(1594)=74 BASE0=XED_REG_R8D -> FB RM=0 value=0x0 FB REXB=1 value=0x1*/ {1594, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1082)=76 BASE0=XED_REG_R8D -> FB RM=0 value=0x0 FB REXB=1 value=0x1*/ {1082, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(570)=78 BASE0=XED_REG_R8D -> FB RM=0 value=0x0 FB REXB=1 value=0x1*/ {570, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(58)=80 BASE0=XED_REG_R8D -> FB RM=0 value=0x0 FB REXB=1 value=0x1*/ {58, 1,0,0}, +/*h(1595)=81 BASE0=XED_REG_R9D -> FB RM=1 value=0x1 FB REXB=1 value=0x1*/ {1595, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1083)=83 BASE0=XED_REG_R9D -> FB RM=1 value=0x1 FB REXB=1 value=0x1*/ {1083, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(571)=85 BASE0=XED_REG_R9D -> FB RM=1 value=0x1 FB REXB=1 value=0x1*/ {571, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(59)=87 BASE0=XED_REG_R9D -> FB RM=1 value=0x1 FB REXB=1 value=0x1*/ {59, 1,1,0}, +/*h(1596)=88 BASE0=XED_REG_R10D -> FB RM=2 value=0x2 FB REXB=1 value=0x1*/ {1596, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1084)=90 BASE0=XED_REG_R10D -> FB RM=2 value=0x2 FB REXB=1 value=0x1*/ {1084, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(572)=92 BASE0=XED_REG_R10D -> FB RM=2 value=0x2 FB REXB=1 value=0x1*/ {572, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(60)=94 BASE0=XED_REG_R10D -> FB RM=2 value=0x2 FB REXB=1 value=0x1*/ {60, 1,2,0}, +/*h(1597)=95 BASE0=XED_REG_R11D -> FB RM=3 value=0x3 FB REXB=1 value=0x1*/ {1597, 1,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1085)=97 BASE0=XED_REG_R11D -> FB RM=3 value=0x3 FB REXB=1 value=0x1*/ {1085, 1,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(573)=99 BASE0=XED_REG_R11D -> FB RM=3 value=0x3 FB REXB=1 value=0x1*/ {573, 1,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(61)=101 BASE0=XED_REG_R11D -> FB RM=3 value=0x3 FB REXB=1 value=0x1*/ {61, 1,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1599)=109 BASE0=XED_REG_R13D -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1*/ {1599, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1087)=111 BASE0=XED_REG_R13D -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1*/ {1087, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(575)=113 BASE0=XED_REG_R13D -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1*/ {575, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(63)=115 BASE0=XED_REG_R13D -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1*/ {63, 1,5,xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND}, +/*h(1600)=116 BASE0=XED_REG_R14D -> FB RM=6 value=0x6 FB REXB=1 value=0x1*/ {1600, 1,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1088)=118 BASE0=XED_REG_R14D -> FB RM=6 value=0x6 FB REXB=1 value=0x1*/ {1088, 1,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(576)=120 BASE0=XED_REG_R14D -> FB RM=6 value=0x6 FB REXB=1 value=0x1*/ {576, 1,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(64)=122 BASE0=XED_REG_R14D -> FB RM=6 value=0x6 FB REXB=1 value=0x1*/ {64, 1,6,0}, +/*h(1601)=123 BASE0=XED_REG_R15D -> FB RM=7 value=0x7 FB REXB=1 value=0x1*/ {1601, 1,7,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_BASE0_MODE(xes); +hidx = ((7*key % 163) % 124); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].rexb >= 0) xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE_EA32_SIB0=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_BIND(xed_encoder_request_t* xes) +{ +xed3_operand_set_rm(xes,4); +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_SIB_NT_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 NEED_SIB=0 -> nothing*/ {0}, +/*h(1)=1 NEED_SIB=1 SIBBASE[bbb]=* SIBSCALE[ss]=* SIBINDEX[iii]=* -> emit ss_iii_bbb emit_type=letters nbits=8*/ {2} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_NEED_SIB(xes); +hidx = key - 0; +if(hidx <= 1) { + xed_encoder_request_iforms(xes)->x_SIB_NT=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_NT_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(8)=0 DISP_WIDTH=8 DISP[dddddddd]=* -> emit dddddddd emit_type=letters nbits=8*/ {8, 1}, +/*h(32)=1 DISP_WIDTH=32 DISP[dddddddddddddddddddddddddddddddd]=* -> emit dddddddddddddddddddddddddddddddd emit_type=letters nbits=32*/ {32, 2}, +/*h(64)=2 DISP_WIDTH=64 DISP[dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd]=* -> emit dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd emit_type=letters nbits=64*/ {64, 3}, +/*h(16)=3 DISP_WIDTH=16 DISP[dddddddddddddddd]=* -> emit dddddddddddddddd emit_type=letters nbits=16*/ {16, 4} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = ((3*key % 5) % 4); +if(lu_table[hidx].key == key) { + xed_encoder_request_iforms(xes)->x_DISP_NT=lu_table[hidx].emit; + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_ERROR_BIND(xed_encoder_request_t* xes) +{ +xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_0_BIND(xed_encoder_request_t* xes) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 0; +if(hidx == 0) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_8_BIND(xed_encoder_request_t* xes) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 8; +if(hidx == 0) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_16_BIND(xed_encoder_request_t* xes) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 16; +if(hidx == 0) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_32_BIND(xed_encoder_request_t* xes) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 32; +if(hidx == 0) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_0_8_16_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 DISP_WIDTH=0 -> nothing*/ {0, }, +/*h(16)=1 DISP_WIDTH=16 -> nothing*/ {16, }, +/*h(8)=2 DISP_WIDTH=8 -> nothing*/ {8, } +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_0_8_32_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 DISP_WIDTH=0 -> nothing*/ {0, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(32)=3 DISP_WIDTH=32 -> nothing*/ {32, }, +/*h(8)=4 DISP_WIDTH=8 -> nothing*/ {8, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_FIXUP_EOSZ_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t eosz;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 EOSZ=0 -> FB EOSZ=1 value=0x1*/ {0, 1}, +/*h(4)=1 MODE=1 EOSZ=0 -> FB EOSZ=2 value=0x2*/ {4, 2}, +/*h(8)=2 MODE=2 EOSZ=0 -> FB EOSZ=2 value=0x2*/ {8, 2} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_EOSZ_MODE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_eosz(xes,lu_table[hidx].eosz); + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_FIXUP_EASZ_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t easz;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 EASZ=0 -> FB EASZ=1 value=0x1*/ {0, 1}, +/*h(4)=1 MODE=1 EASZ=0 -> FB EASZ=2 value=0x2*/ {4, 2}, +/*h(8)=2 MODE=2 EASZ=0 -> FB EASZ=3 value=0x3*/ {8, 3} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_EASZ_MODE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_easz(xes,lu_table[hidx].easz); + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_FIXUP_SMODE_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error ;xed_int8_t smode;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(2)=0 MODE=2 SMODE=0 -> FB SMODE=2 value=0x2*/ {2, -1,2}, +/*h(6)=1 MODE=2 SMODE=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {6, XED_ERROR_GENERAL_ERROR,-1} +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_SMODE(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-1)); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + if(lu_table[hidx].smode >= 0) xed3_operand_set_smode(xes,lu_table[hidx].smode); + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_REMOVE_SEGMENT_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 AGEN=0 -> nothing*/ {0}, +/*h(1)=1 AGEN=1 -> nt NT[REMOVE_SEGMENT_AGEN1]*/ {xed_encode_nonterminal_REMOVE_SEGMENT_AGEN1_BIND} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_AGEN(xes); +hidx = key - 0; +if(hidx <= 1) { + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_REMOVE_SEGMENT=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_REMOVE_SEGMENT_AGEN1_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 SEG0=@ -> nothing*/ {0, -1}, +/*h(149)=1 SEG0=XED_REG_CS -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {149, XED_ERROR_GENERAL_ERROR}, +/*empty slot1 */ {0,0}, +/*h(151)=3 SEG0=XED_REG_DS -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {151, XED_ERROR_GENERAL_ERROR}, +/*empty slot1 */ {0,0}, +/*h(148)=5 SEG0=XED_REG_ES -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {148, XED_ERROR_GENERAL_ERROR}, +/*h(153)=6 SEG0=XED_REG_GS -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {153, XED_ERROR_GENERAL_ERROR}, +/*empty slot1 */ {0,0}, +/*h(150)=8 SEG0=XED_REG_SS -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {150, XED_ERROR_GENERAL_ERROR}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=11 SEG0=XED_REG_FS -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {152, XED_ERROR_GENERAL_ERROR} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_SEG0(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_OVERRIDE_SEG0_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t seg_ovd;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 SEG0=@ -> FB SEG_OVD=0 value=0x0*/ {0, 0}, +/*h(149)=1 SEG0=XED_REG_CS -> FB SEG_OVD=1 value=0x1*/ {149, 1}, +/*empty slot1 */ {0,0}, +/*h(151)=3 SEG0=XED_REG_DS -> FB SEG_OVD=0 value=0x0*/ {151, 0}, +/*empty slot1 */ {0,0}, +/*h(148)=5 SEG0=XED_REG_ES -> FB SEG_OVD=3 value=0x3*/ {148, 3}, +/*h(153)=6 SEG0=XED_REG_GS -> FB SEG_OVD=5 value=0x5*/ {153, 5}, +/*empty slot1 */ {0,0}, +/*h(150)=8 SEG0=XED_REG_SS -> FB SEG_OVD=6 value=0x6*/ {150, 6}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=11 SEG0=XED_REG_FS -> FB SEG_OVD=4 value=0x4*/ {152, 4} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_SEG0(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_OVERRIDE_SEG1_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t seg_ovd;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(0)=0 SEG1=@ -> FB SEG_OVD=0 value=0x0*/ {0, 0}, +/*h(149)=1 SEG1=XED_REG_CS -> FB SEG_OVD=1 value=0x1*/ {149, 1}, +/*empty slot1 */ {0,0}, +/*h(151)=3 SEG1=XED_REG_DS -> FB SEG_OVD=0 value=0x0*/ {151, 0}, +/*empty slot1 */ {0,0}, +/*h(148)=5 SEG1=XED_REG_ES -> FB SEG_OVD=3 value=0x3*/ {148, 3}, +/*h(153)=6 SEG1=XED_REG_GS -> FB SEG_OVD=5 value=0x5*/ {153, 5}, +/*empty slot1 */ {0,0}, +/*h(150)=8 SEG1=XED_REG_SS -> FB SEG_OVD=6 value=0x6*/ {150, 6}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=11 SEG1=XED_REG_FS -> FB SEG_OVD=4 value=0x4*/ {152, 4} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_SEG1(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DF64_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t df64;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> nothing*/ {-1}, +/*h(1)=1 MODE=1 -> nothing*/ {-1}, +/*h(2)=2 MODE=2 -> FB DF64=1 value=0x1*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].df64 >= 0) xed3_operand_set_df64(xes,lu_table[hidx].df64); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_OSZ_NONTERM_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error ;xed_int8_t osz ;xed_int8_t rexw;} lu_entry_t; +static const lu_entry_t lu_table[47] = { +/*h(47)=0 VEXVALID=0 MODE=2 EOSZ=3 DF64=1 -> nothing*/ {47, -1,-1,-1}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(4)=12 VEXVALID=0 MODE=0 EOSZ=1 -> nothing*/ {4, -1,-1,-1}, +/*h(20)=13 VEXVALID=0 MODE=1 EOSZ=1 -> FB OSZ=1 value=0x1*/ {20, -1,1,-1}, +/*h(36)=14 VEXVALID=0 MODE=2 EOSZ=1 -> FB OSZ=1 value=0x1*/ {36, -1,1,-1}, +/*h(5)=15 VEXVALID=0 MODE=0 EOSZ=1 -> nothing*/ {5, -1,-1,-1}, +/*h(21)=16 VEXVALID=0 MODE=1 EOSZ=1 -> FB OSZ=1 value=0x1*/ {21, -1,1,-1}, +/*h(37)=17 VEXVALID=0 MODE=2 EOSZ=1 -> FB OSZ=1 value=0x1*/ {37, -1,1,-1}, +/*h(6)=18 VEXVALID=0 MODE=0 EOSZ=1 -> nothing*/ {6, -1,-1,-1}, +/*h(22)=19 VEXVALID=0 MODE=1 EOSZ=1 -> FB OSZ=1 value=0x1*/ {22, -1,1,-1}, +/*h(38)=20 VEXVALID=0 MODE=2 EOSZ=1 -> FB OSZ=1 value=0x1*/ {38, -1,1,-1}, +/*h(7)=21 VEXVALID=0 MODE=0 EOSZ=1 -> nothing*/ {7, -1,-1,-1}, +/*h(23)=22 VEXVALID=0 MODE=1 EOSZ=1 -> FB OSZ=1 value=0x1*/ {23, -1,1,-1}, +/*h(39)=23 VEXVALID=0 MODE=2 EOSZ=1 -> FB OSZ=1 value=0x1*/ {39, -1,1,-1}, +/*h(8)=24 VEXVALID=0 MODE=0 EOSZ=2 DF32=0 -> FB OSZ=1 value=0x1*/ {8, -1,1,-1}, +/*h(24)=25 VEXVALID=0 MODE=1 EOSZ=2 -> nothing*/ {24, -1,-1,-1}, +/*h(40)=26 VEXVALID=0 MODE=2 EOSZ=2 DF64=0 -> nothing*/ {40, -1,-1,-1}, +/*h(9)=27 VEXVALID=0 MODE=0 EOSZ=2 DF32=1 -> nothing*/ {9, -1,-1,-1}, +/*h(25)=28 VEXVALID=0 MODE=1 EOSZ=2 -> nothing*/ {25, -1,-1,-1}, +/*h(41)=29 VEXVALID=0 MODE=2 EOSZ=2 DF64=0 -> nothing*/ {41, -1,-1,-1}, +/*h(10)=30 VEXVALID=0 MODE=0 EOSZ=2 DF32=0 -> FB OSZ=1 value=0x1*/ {10, -1,1,-1}, +/*h(26)=31 VEXVALID=0 MODE=1 EOSZ=2 -> nothing*/ {26, -1,-1,-1}, +/*h(42)=32 VEXVALID=0 MODE=2 EOSZ=2 DF64=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {42, XED_ERROR_GENERAL_ERROR,-1,-1}, +/*h(11)=33 VEXVALID=0 MODE=0 EOSZ=2 DF32=1 -> nothing*/ {11, -1,-1,-1}, +/*h(27)=34 VEXVALID=0 MODE=1 EOSZ=2 -> nothing*/ {27, -1,-1,-1}, +/*h(43)=35 VEXVALID=0 MODE=2 EOSZ=2 DF64=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {43, XED_ERROR_GENERAL_ERROR,-1,-1}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(44)=38 VEXVALID=0 MODE=2 EOSZ=3 DF64=0 -> FB REXW=1 value=0x1*/ {44, -1,-1,1}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(45)=41 VEXVALID=0 MODE=2 EOSZ=3 DF64=0 -> FB REXW=1 value=0x1*/ {45, -1,-1,1}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(46)=44 VEXVALID=0 MODE=2 EOSZ=3 DF64=1 -> nothing*/ {46, -1,-1,-1}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DF32_DF64_EOSZ_MODE_VEXVALID(xes); +hidx = (3*key % 47); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + if(lu_table[hidx].osz >= 0) xed3_operand_set_osz(xes,lu_table[hidx].osz); + if(lu_table[hidx].rexw >= 0) xed3_operand_set_rexw(xes,lu_table[hidx].rexw); + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_REFINING66_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_IGNORE66_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_IMMUNE66_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t df32 ;xed_int8_t eosz;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 MODE=0 -> FB EOSZ=2 value=0x2 FB DF32=1 value=0x1*/ {1,2} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx == 0) { + xed3_operand_set_df32(xes,lu_table[hidx].df32); + xed3_operand_set_eosz(xes,lu_table[hidx].eosz); + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_IMMUNE66_LOOP64_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_IMMUNE_REXW_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_CR_WIDTH_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t df32 ;xed_int8_t df64 ;xed_int8_t eosz;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> FB DF32=1 value=0x1 FB EOSZ=2 value=0x2*/ {1,-1,2}, +/*h(1)=1 MODE=1 -> nothing*/ {-1,-1,-1}, +/*h(2)=2 MODE=2 -> FB DF64=1 value=0x1 FB EOSZ=3 value=0x3*/ {-1,1,3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].df32 >= 0) xed3_operand_set_df32(xes,lu_table[hidx].df32); + if(lu_table[hidx].df64 >= 0) xed3_operand_set_df64(xes,lu_table[hidx].df64); + if(lu_table[hidx].eosz >= 0) xed3_operand_set_eosz(xes,lu_table[hidx].eosz); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_FORCE64_BIND(xed_encoder_request_t* xes) +{ +xed3_operand_set_df64(xes,1); +xed3_operand_set_eosz(xes,3); +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_BRANCH_HINT_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_CET_NO_TRACK_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_VEXED_REX_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 VEXVALID=0 -> nt NT[REX_PREFIX_ENC]*/ {xed_encode_nonterminal_REX_PREFIX_ENC_BIND}, +/*h(1)=1 VEXVALID=1 -> nt NT[NEWVEX_ENC]*/ {xed_encode_nonterminal_NEWVEX_ENC_BIND}, +/*h(2)=2 VEXVALID=2 -> nt NT[EVEX_ENC]*/ {xed_encode_nonterminal_EVEX_ENC_BIND}, +/*h(3)=3 VEXVALID=3 -> nt NT[XOP_ENC]*/ {xed_encode_nonterminal_XOP_ENC_BIND} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_VEXVALID(xes); +hidx = key - 0; +if(hidx <= 3) { + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_VEXED_REX=hidx+1; + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_XOP_TYPE_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8)=0 MAP=8 -> emit 0x8F emit_type=numeric value=0x8f nbits=8*/ {1}, +/*h(9)=1 MAP=9 -> emit 0x8F emit_type=numeric value=0x8f nbits=8*/ {2}, +/*h(10)=2 MAP=10 -> emit 0x8F emit_type=numeric value=0x8f nbits=8*/ {3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MAP(xes); +hidx = key - 8; +if(hidx <= 2) { + xed_encoder_request_iforms(xes)->x_XOP_TYPE_ENC=lu_table[hidx].emit; + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_XOP_MAP_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(8)=0 MAP=8 REXW[w]=* -> emit 0b0_1000 emit_type=numeric value=0x8 nbits=5 emit w emit_type=letters nbits=1*/ {1}, +/*h(9)=1 MAP=9 REXW[w]=* -> emit 0b0_1001 emit_type=numeric value=0x9 nbits=5 emit w emit_type=letters nbits=1*/ {2}, +/*h(10)=2 MAP=10 REXW[w]=* -> emit 0b0_1010 emit_type=numeric value=0xa nbits=5 emit w emit_type=letters nbits=1*/ {3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MAP(xes); +hidx = key - 8; +if(hidx <= 2) { + xed_encoder_request_iforms(xes)->x_XOP_MAP_ENC=lu_table[hidx].emit; + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_XOP_REXXB_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 MODE!=2 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,4}, +/*h(1)=1 MODE!=2 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,4}, +/*h(2)=2 MODE=2 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,3}, +/*h(3)=3 MODE!=2 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,4}, +/*h(4)=4 MODE!=2 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(5)=5 MODE!=2 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(6)=6 MODE=2 REXX=0 REXB=1 -> emit 0b10 emit_type=numeric value=0x2 nbits=2*/ {-1,7}, +/*h(7)=7 MODE!=2 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(8)=8 MODE!=2 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(9)=9 MODE!=2 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(10)=10 MODE=2 REXX=1 REXB=0 -> emit 0b01 emit_type=numeric value=0x1 nbits=2*/ {-1,11}, +/*h(11)=11 MODE!=2 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(12)=12 MODE!=2 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(13)=13 MODE!=2 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(14)=14 MODE=2 REXX=1 REXB=1 -> emit 0b00 emit_type=numeric value=0x0 nbits=2*/ {-1,15}, +/*h(15)=15 MODE!=2 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXB_REXX(xes); +hidx = key - 0; +if(hidx <= 15) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_XOP_REXXB_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_BND_R_CHECK_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 REXR=0 REG=0x0 -> nothing*/ {-1}, +/*h(1)=1 REXR=0 REG=0x1 -> nothing*/ {-1}, +/*h(2)=2 REXR=0 REG=0x2 -> nothing*/ {-1}, +/*h(3)=3 REXR=0 REG=0x3 -> nothing*/ {-1}, +/*h(4)=4 REXR=0 REG=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(5)=5 REXR=0 REG=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(6)=6 REXR=0 REG=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(7)=7 REXR=0 REG=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(8)=8 REXR=1 REG=0x0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(9)=9 REXR=1 REG=0x1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(10)=10 REXR=1 REG=0x2 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(11)=11 REXR=1 REG=0x3 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(12)=12 REXR=1 REG=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(13)=13 REXR=1 REG=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(14)=14 REXR=1 REG=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(15)=15 REXR=1 REG=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_REG_REXR(xes); +hidx = key - 0; +if(hidx <= 15) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_BND_B_CHECK_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 REXB=0 RM=0x0 -> nothing*/ {-1}, +/*h(1)=1 REXB=1 RM=0x0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(2)=2 REXB=0 RM=0x1 -> nothing*/ {-1}, +/*h(3)=3 REXB=1 RM=0x1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(4)=4 REXB=0 RM=0x2 -> nothing*/ {-1}, +/*h(5)=5 REXB=1 RM=0x2 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(6)=6 REXB=0 RM=0x3 -> nothing*/ {-1}, +/*h(7)=7 REXB=1 RM=0x3 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(8)=8 REXB=0 RM=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(9)=9 REXB=1 RM=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(10)=10 REXB=0 RM=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(11)=11 REXB=1 RM=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(12)=12 REXB=0 RM=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(13)=13 REXB=1 RM=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(14)=14 REXB=0 RM=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(15)=15 REXB=1 RM=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_REXB_RM(xes); +hidx = key - 0; +if(hidx <= 15) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_VEX_REXR_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 MODE!=2 REXR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {-1,4}, +/*h(1)=1 MODE!=2 REXR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {-1,4}, +/*h(2)=2 MODE=2 REXR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {-1,3}, +/*h(3)=3 MODE!=2 REXR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {-1,4}, +/*h(4)=4 MODE!=2 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(5)=5 MODE!=2 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(6)=6 MODE=2 REXR=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1*/ {-1,7}, +/*h(7)=7 MODE!=2 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXR(xes); +hidx = key - 0; +if(hidx <= 7) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_VEX_REXR_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_VEX_REXXB_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(16)=0 MODE!=2 VEX_C4=1 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,4}, +/*h(17)=1 MODE!=2 VEX_C4=1 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,4}, +/*h(18)=2 MODE=2 VEX_C4=1 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,3}, +/*h(19)=3 MODE!=2 VEX_C4=1 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2*/ {-1,4}, +/*h(20)=4 MODE!=2 VEX_C4=1 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(21)=5 MODE!=2 VEX_C4=1 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(22)=6 MODE=2 VEX_C4=1 REXX=0 REXB=1 -> emit 0b10 emit_type=numeric value=0x2 nbits=2*/ {-1,7}, +/*h(23)=7 MODE!=2 VEX_C4=1 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(24)=8 MODE!=2 VEX_C4=1 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(25)=9 MODE!=2 VEX_C4=1 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(26)=10 MODE=2 VEX_C4=1 REXX=1 REXB=0 -> emit 0b01 emit_type=numeric value=0x1 nbits=2*/ {-1,11}, +/*h(27)=11 MODE!=2 VEX_C4=1 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(28)=12 MODE!=2 VEX_C4=1 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(29)=13 MODE!=2 VEX_C4=1 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(30)=14 MODE=2 VEX_C4=1 REXX=1 REXB=1 -> emit 0b00 emit_type=numeric value=0x0 nbits=2*/ {-1,15}, +/*h(31)=15 MODE!=2 VEX_C4=1 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXB_REXX_VEX_C4(xes); +hidx = key - 16; +if(hidx <= 15) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_VEX_REXXB_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_VEX_MAP_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(16)=0 VEX_C4=1 MAP=0 REXW[w]=* -> emit 0b0_0000 emit_type=numeric value=0x0 nbits=5 emit w emit_type=letters nbits=1*/ {1}, +/*h(17)=1 VEX_C4=1 MAP=1 REXW[w]=* -> emit 0b0_0001 emit_type=numeric value=0x1 nbits=5 emit w emit_type=letters nbits=1*/ {2}, +/*h(18)=2 VEX_C4=1 MAP=2 REXW[w]=* -> emit 0b0_0010 emit_type=numeric value=0x2 nbits=5 emit w emit_type=letters nbits=1*/ {3}, +/*h(19)=3 VEX_C4=1 MAP=3 REXW[w]=* -> emit 0b0_0011 emit_type=numeric value=0x3 nbits=5 emit w emit_type=letters nbits=1*/ {4} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MAP_VEX_C4(xes); +hidx = key - 16; +if(hidx <= 3) { + xed_encoder_request_iforms(xes)->x_VEX_MAP_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_VEX_REG_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 MODE!=2 VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit 1_ddd emit_type=letters nbits=4*/ {4}, +/*h(1)=1 MODE!=2 VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit 1_ddd emit_type=letters nbits=4*/ {4}, +/*h(2)=2 MODE=2 VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit u_ddd emit_type=letters nbits=4*/ {3}, +/*h(3)=3 MODE!=2 VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit 1_ddd emit_type=letters nbits=4*/ {4} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 3) { + xed_encoder_request_iforms(xes)->x_VEX_REG_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_VEX_ESCVL_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(0)=0 VL=0 VEX_PREFIX=0 -> emit 0b000 emit_type=numeric value=0x0 nbits=3*/ {1}, +/*h(1)=1 VL=0 VEX_PREFIX=1 -> emit 0b001 emit_type=numeric value=0x1 nbits=3*/ {2}, +/*h(2)=2 VL=0 VEX_PREFIX=2 -> emit 0b011 emit_type=numeric value=0x3 nbits=3*/ {3}, +/*h(3)=3 VL=0 VEX_PREFIX=3 -> emit 0b010 emit_type=numeric value=0x2 nbits=3*/ {4}, +/*h(4)=4 VL=1 VEX_PREFIX=0 -> emit 0b100 emit_type=numeric value=0x4 nbits=3*/ {5}, +/*h(5)=5 VL=1 VEX_PREFIX=1 -> emit 0b101 emit_type=numeric value=0x5 nbits=3*/ {6}, +/*h(6)=6 VL=1 VEX_PREFIX=2 -> emit 0b111 emit_type=numeric value=0x7 nbits=3*/ {7}, +/*h(7)=7 VL=1 VEX_PREFIX=3 -> emit 0b110 emit_type=numeric value=0x6 nbits=3*/ {8} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_VEX_PREFIX_VL(xes); +hidx = key - 0; +if(hidx <= 7) { + xed_encoder_request_iforms(xes)->x_VEX_ESCVL_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_SE_IMM8_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 DUMMY=0 ESRC[ssss]=* UIMM0[dddd]=* -> emit ssss_dddd emit_type=letters nbits=8*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DUMMY(xes); +hidx = key - 0; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_SE_IMM8=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_BASE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t sibbase ;xed_nt_func_ptr_t ntptr0;} lu_entry_t; +static const lu_entry_t lu_table[104] = { +/*h(0)=0 BASE0=@ -> nt NT[DISP_WIDTH_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {0, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(548)=3 BASE0=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2*/ {548, 0,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(549)=7 BASE0=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3*/ {549, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(550)=11 BASE0=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4*/ {550, 0,4,0}, +/*h(1024)=12 BASE0=@ -> nt NT[DISP_WIDTH_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {1024, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*h(1074)=13 BASE0=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0*/ {1074, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(551)=15 BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {551, 0,5,xed_encode_nonterminal_DISP_WIDTH_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1075)=17 BASE0=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1*/ {1075, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(552)=19 BASE0=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6*/ {552, 0,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1076)=21 BASE0=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2*/ {1076, 0,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(553)=23 BASE0=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7*/ {553, 0,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1077)=25 BASE0=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3*/ {1077, 0,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(554)=27 BASE0=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0*/ {554, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1078)=29 BASE0=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4*/ {1078, 0,4,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(555)=31 BASE0=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1*/ {555, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1079)=33 BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {1079, 0,5,xed_encode_nonterminal_DISP_WIDTH_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(556)=35 BASE0=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2*/ {556, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1080)=37 BASE0=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6*/ {1080, 0,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(557)=39 BASE0=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3*/ {557, 1,3,0}, +/*h(1602)=40 BASE0=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0*/ {1602, 0,0,0}, +/*h(1081)=41 BASE0=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7*/ {1081, 0,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(558)=43 BASE0=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4*/ {558, 1,4,0}, +/*h(1603)=44 BASE0=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1*/ {1603, 0,1,0}, +/*h(1082)=45 BASE0=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0*/ {1082, 1,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(559)=47 BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5*/ {559, 1,5,xed_encode_nonterminal_DISP_WIDTH_8_32_BIND}, +/*h(1604)=48 BASE0=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2*/ {1604, 0,2,0}, +/*h(1083)=49 BASE0=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1*/ {1083, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(560)=51 BASE0=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6*/ {560, 1,6,0}, +/*h(1605)=52 BASE0=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3*/ {1605, 0,3,0}, +/*h(1084)=53 BASE0=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2*/ {1084, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(561)=55 BASE0=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7*/ {561, 1,7,0}, +/*h(1606)=56 BASE0=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4*/ {1606, 0,4,0}, +/*h(1085)=57 BASE0=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3*/ {1085, 1,3,0}, +/*h(512)=58 BASE0=@ -> nt NT[DISP_WIDTH_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {512, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1607)=60 BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {1607, 0,5,xed_encode_nonterminal_DISP_WIDTH_8_32_BIND}, +/*h(1086)=61 BASE0=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4*/ {1086, 1,4,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1608)=64 BASE0=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6*/ {1608, 0,6,0}, +/*h(1087)=65 BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5*/ {1087, 1,5,xed_encode_nonterminal_DISP_WIDTH_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1609)=68 BASE0=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7*/ {1609, 0,7,0}, +/*h(1088)=69 BASE0=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6*/ {1088, 1,6,0}, +/*h(1536)=70 BASE0=@ -> nt NT[DISP_WIDTH_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5*/ {1536, 0,5,xed_encode_nonterminal_DISP_WIDTH_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(1610)=72 BASE0=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0*/ {1610, 1,0,0}, +/*h(1089)=73 BASE0=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7*/ {1089, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1611)=76 BASE0=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1*/ {1611, 1,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1612)=80 BASE0=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2*/ {1612, 1,2,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1613)=84 BASE0=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3*/ {1613, 1,3,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1614)=88 BASE0=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4*/ {1614, 1,4,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(546)=90 BASE0=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0*/ {546, 0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1615)=92 BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5*/ {1615, 1,5,xed_encode_nonterminal_DISP_WIDTH_8_32_BIND}, +/*empty slot1 */ {0,0,0,0}, +/*h(547)=94 BASE0=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1*/ {547, 0,1,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1616)=96 BASE0=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6*/ {1616, 1,6,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*h(1617)=100 BASE0=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7*/ {1617, 1,7,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0}, +/*empty slot1 */ {0,0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +key = xed_enc_lu_BASE0_EASZ(xes); +hidx = ((4*key % 199) % 104); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_sibbase(xes,lu_table[hidx].sibbase); + if(lu_table[hidx].ntptr0 != 0) res=(*lu_table[hidx].ntptr0)(xes); + xed_encoder_request_iforms(xes)->x_VSIB_ENC_BASE=hidx+1; + return res; + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_SCALE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t sibscale;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(0)=0 SCALE=0 -> FB SIBSCALE=0 value=0x0*/ {0, 0}, +/*h(2)=1 SCALE=2 -> FB SIBSCALE=1 value=0x1*/ {2, 1}, +/*h(4)=2 SCALE=4 -> FB SIBSCALE=2 value=0x2*/ {4, 2}, +/*h(1)=3 SCALE=1 -> FB SIBSCALE=0 value=0x0*/ {1, 0}, +/*h(8)=4 SCALE=8 -> FB SIBSCALE=3 value=0x3*/ {8, 3} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_SCALE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_sibscale(xes,lu_table[hidx].sibscale); + return 1; +} +else{ + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 DUMMY=0 SIBBASE[bbb]=* SIBINDEX[iii]=* SIBSCALE[ss]=* -> emit ss_iii_bbb emit_type=letters nbits=8*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DUMMY(xes); +hidx = key - 0; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_VSIB_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_INDEX_XMM_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t rexx ;xed_int8_t sibindex;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(188)=0 INDEX=XED_REG_XMM0 -> FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0}, +/*h(189)=1 INDEX=XED_REG_XMM1 -> FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1}, +/*h(190)=2 INDEX=XED_REG_XMM2 -> FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2}, +/*h(191)=3 INDEX=XED_REG_XMM3 -> FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3}, +/*h(192)=4 INDEX=XED_REG_XMM4 -> FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4}, +/*h(193)=5 INDEX=XED_REG_XMM5 -> FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5}, +/*h(194)=6 INDEX=XED_REG_XMM6 -> FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6}, +/*h(195)=7 INDEX=XED_REG_XMM7 -> FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7}, +/*h(196)=8 INDEX=XED_REG_XMM8 -> FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0}, +/*h(197)=9 INDEX=XED_REG_XMM9 -> FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1}, +/*h(198)=10 INDEX=XED_REG_XMM10 -> FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2}, +/*h(199)=11 INDEX=XED_REG_XMM11 -> FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3}, +/*h(200)=12 INDEX=XED_REG_XMM12 -> FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4}, +/*h(201)=13 INDEX=XED_REG_XMM13 -> FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5}, +/*h(202)=14 INDEX=XED_REG_XMM14 -> FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6}, +/*h(203)=15 INDEX=XED_REG_XMM15 -> FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_INDEX(xes); +hidx = key - 188; +if(hidx <= 15) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_VSIB_ENC_INDEX_YMM_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t rexx ;xed_int8_t sibindex;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(220)=0 INDEX=XED_REG_YMM0 -> FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0}, +/*h(221)=1 INDEX=XED_REG_YMM1 -> FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1}, +/*h(222)=2 INDEX=XED_REG_YMM2 -> FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2}, +/*h(223)=3 INDEX=XED_REG_YMM3 -> FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3}, +/*h(224)=4 INDEX=XED_REG_YMM4 -> FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4}, +/*h(225)=5 INDEX=XED_REG_YMM5 -> FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5}, +/*h(226)=6 INDEX=XED_REG_YMM6 -> FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6}, +/*h(227)=7 INDEX=XED_REG_YMM7 -> FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7}, +/*h(228)=8 INDEX=XED_REG_YMM8 -> FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0}, +/*h(229)=9 INDEX=XED_REG_YMM9 -> FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1}, +/*h(230)=10 INDEX=XED_REG_YMM10 -> FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2}, +/*h(231)=11 INDEX=XED_REG_YMM11 -> FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3}, +/*h(232)=12 INDEX=XED_REG_YMM12 -> FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4}, +/*h(233)=13 INDEX=XED_REG_YMM13 -> FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5}, +/*h(234)=14 INDEX=XED_REG_YMM14 -> FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6}, +/*h(235)=15 INDEX=XED_REG_YMM15 -> FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_INDEX(xes); +hidx = key - 220; +if(hidx <= 15) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_DISP_WIDTH_8_32_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(8)=0 DISP_WIDTH=8 -> nothing*/ {8, }, +/*h(32)=1 DISP_WIDTH=32 -> nothing*/ {32, } +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = ((3*key % 5) % 2); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_4X_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_EVEX_62_REXR_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(5)=0 MODE=1 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {5, XED_ERROR_GENERAL_ERROR,0}, +/*h(2)=1 MODE=2 REXR=0 -> emit 0x62 emit_type=numeric value=0x62 nbits=8 emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {2, -1,2}, +/*empty slot1 */ {0,0,0}, +/*h(1)=3 MODE=1 REXR=0 -> emit 0x62 emit_type=numeric value=0x62 nbits=8 emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {1, -1,4}, +/*h(6)=4 MODE=2 REXR=1 -> emit 0x62 emit_type=numeric value=0x62 nbits=8 emit 0b0 emit_type=numeric value=0x0 nbits=1*/ {6, -1,5}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXR(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_EVEX_62_REXR_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_REXX_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(5)=0 MODE=1 REXX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {5, XED_ERROR_GENERAL_ERROR,0}, +/*h(2)=1 MODE=2 REXX=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {2, -1,2}, +/*empty slot1 */ {0,0,0}, +/*h(1)=3 MODE=1 REXX=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {1, -1,4}, +/*h(6)=4 MODE=2 REXX=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1*/ {6, -1,5}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXX(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_EVEX_REXX_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_REXB_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(5)=0 MODE=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {5, XED_ERROR_GENERAL_ERROR,0}, +/*h(2)=1 MODE=2 REXB=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {2, -1,2}, +/*empty slot1 */ {0,0,0}, +/*h(1)=3 MODE=1 REXB=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {1, -1,4}, +/*h(6)=4 MODE=2 REXB=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1*/ {6, -1,5}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXB(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_EVEX_REXB_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_REXRR_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(5)=0 MODE=1 REXRR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {5, XED_ERROR_GENERAL_ERROR,0}, +/*h(2)=1 MODE=2 REXRR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {2, -1,2}, +/*empty slot1 */ {0,0,0}, +/*h(1)=3 MODE=1 REXRR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1*/ {1, -1,4}, +/*h(6)=4 MODE=2 REXRR=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1*/ {6, -1,5}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MODE_REXRR(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_EVEX_REXRR_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_MAP_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[7] = { +/*h(0)=0 MAP=0 -> emit 0b0000 emit_type=numeric value=0x0 nbits=4*/ {-1,1}, +/*h(1)=1 MAP=1 -> emit 0b0001 emit_type=numeric value=0x1 nbits=4*/ {-1,2}, +/*h(2)=2 MAP=2 -> emit 0b0010 emit_type=numeric value=0x2 nbits=4*/ {-1,3}, +/*h(3)=3 MAP=3 -> emit 0b0011 emit_type=numeric value=0x3 nbits=4*/ {-1,4}, +/*h(4)=4 MAP=4 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR,0}, +/*h(5)=5 MAP=5 -> emit 0b0101 emit_type=numeric value=0x5 nbits=4*/ {-1,6}, +/*h(6)=6 MAP=6 -> emit 0b0110 emit_type=numeric value=0x6 nbits=4*/ {-1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_MAP(xes); +hidx = key - 0; +if(hidx <= 6) { + if(lu_table[hidx].error >= 0) xed3_operand_set_error(xes,lu_table[hidx].error); + xed_encoder_request_iforms(xes)->x_EVEX_MAP_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_REXW_VVVV_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 DUMMY=0 REXW[w]=* VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit w emit_type=letters nbits=1 emit u_ddd emit_type=letters nbits=4*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DUMMY(xes); +hidx = key - 0; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_EVEX_REXW_VVVV_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_UPP_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 VEX_PREFIX=0 -> emit 0b100 emit_type=numeric value=0x4 nbits=3*/ {1}, +/*h(1)=1 VEX_PREFIX=1 -> emit 0b101 emit_type=numeric value=0x5 nbits=3*/ {2}, +/*h(2)=2 VEX_PREFIX=2 -> emit 0b111 emit_type=numeric value=0x7 nbits=3*/ {3}, +/*h(3)=3 VEX_PREFIX=3 -> emit 0b110 emit_type=numeric value=0x6 nbits=3*/ {4} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_VEX_PREFIX(xes); +hidx = key - 0; +if(hidx <= 3) { + xed_encoder_request_iforms(xes)->x_EVEX_UPP_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_EVEX_LL_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t bcrc ;xed_int8_t llrc;} lu_entry_t; +static const lu_entry_t lu_table[19] = { +/*h(0)=0 ROUNDC=0 SAE=0 VL=0 -> FB LLRC=0 value=0x0*/ {0, -1,0}, +/*h(32)=1 ROUNDC=0 SAE=0 VL=2 -> FB LLRC=2 value=0x2*/ {32, -1,2}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(8)=5 ROUNDC=0 SAE=1 VL=0 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1*/ {8, 1,0}, +/*h(40)=6 ROUNDC=0 SAE=1 VL=2 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1*/ {40, 1,0}, +/*empty slot1 */ {0,0,0}, +/*h(9)=8 ROUNDC=1 SAE=1 VL=0 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1*/ {9, 1,0}, +/*h(41)=9 ROUNDC=1 SAE=1 VL=2 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1*/ {41, 1,0}, +/*h(16)=10 ROUNDC=0 SAE=0 VL=1 -> FB LLRC=1 value=0x1*/ {16, -1,1}, +/*h(10)=11 ROUNDC=2 SAE=1 VL=0 -> FB LLRC=1 value=0x1 FB BCRC=1 value=0x1*/ {10, 1,1}, +/*h(42)=12 ROUNDC=2 SAE=1 VL=2 -> FB LLRC=1 value=0x1 FB BCRC=1 value=0x1*/ {42, 1,1}, +/*empty slot1 */ {0,0,0}, +/*h(11)=14 ROUNDC=3 SAE=1 VL=0 -> FB LLRC=2 value=0x2 FB BCRC=1 value=0x1*/ {11, 1,2}, +/*h(43)=15 ROUNDC=3 SAE=1 VL=2 -> FB LLRC=2 value=0x2 FB BCRC=1 value=0x1*/ {43, 1,2}, +/*empty slot1 */ {0,0,0}, +/*h(12)=17 ROUNDC=4 SAE=1 VL=0 -> FB LLRC=3 value=0x3 FB BCRC=1 value=0x1*/ {12, 1,3}, +/*h(44)=18 ROUNDC=4 SAE=1 VL=2 -> FB LLRC=3 value=0x3 FB BCRC=1 value=0x1*/ {44, 1,3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_ROUNDC_SAE_VL(xes); +hidx = (3*key % 19); +if(lu_table[hidx].key == key) { + if(lu_table[hidx].bcrc >= 0) xed3_operand_set_bcrc(xes,lu_table[hidx].bcrc); + xed3_operand_set_llrc(xes,lu_table[hidx].llrc); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_AVX512_EVEX_BYTE3_ENC_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 ZEROING[z]=* LLRC[nn]=* BCRC[b]=* VEXDEST4=0 MASK[aaa]=* -> emit z_nn_b emit_type=letters nbits=4 emit 0b1 emit_type=numeric value=0x1 nbits=1 emit aaa emit_type=letters nbits=3*/ {1}, +/*h(1)=1 ZEROING[z]=* LLRC[nn]=* BCRC[b]=* VEXDEST4=1 MASK[aaa]=* -> emit z_nn_b emit_type=letters nbits=4 emit 0b0 emit_type=numeric value=0x0 nbits=1 emit aaa emit_type=letters nbits=3*/ {2} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_VEXDEST4(xes); +hidx = key - 0; +if(hidx <= 1) { + xed_encoder_request_iforms(xes)->x_AVX512_EVEX_BYTE3_ENC=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_AVX512_ROUND_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t bcrc ;xed_int8_t llrc;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(1)=0 ROUNDC=1 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1*/ {1,0}, +/*h(2)=1 ROUNDC=2 -> FB LLRC=1 value=0x1 FB BCRC=1 value=0x1*/ {1,1}, +/*h(3)=2 ROUNDC=3 -> FB LLRC=2 value=0x2 FB BCRC=1 value=0x1*/ {1,2}, +/*h(4)=3 ROUNDC=4 -> FB LLRC=3 value=0x3 FB BCRC=1 value=0x1*/ {1,3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_ROUNDC(xes); +hidx = key - 1; +if(hidx <= 3) { + xed3_operand_set_bcrc(xes,lu_table[hidx].bcrc); + xed3_operand_set_llrc(xes,lu_table[hidx].llrc); + return 1; +} +else{ + return 0; +} +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-1.c b/CodeVirtualizer/build/obj/xed-encoder-1.c new file mode 100644 index 0000000..b3e95c0 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-1.c @@ -0,0 +1,2990 @@ +/// @file xed-encoder-1.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encoder.h" +#include "xed-encode-private.h" +#include "xed-enc-operand-lu.h" +#include "xed-operand-accessors.h" +xed_uint32_t xed_encode_nonterminal_SAE_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t bcrc;} lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(0)=0 SAE=0 -> FB BCRC=0 value=0x0*/ {0}, +/*h(1)=1 SAE=1 -> FB BCRC=1 value=0x1*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_SAE(xes); +hidx = key - 0; +if(hidx <= 1) { + xed3_operand_set_bcrc(xes,lu_table[hidx].bcrc); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_ESIZE_128_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_64_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_32_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_16_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_8_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_4_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_2_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ESIZE_1_BITS_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_MOVDDUP_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_FULLMEM_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_HALFMEM_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_QUARTERMEM_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_EIGHTHMEM_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_BYTE_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_WORD_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BYTE_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_WORD_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_BYTE_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_WORD_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_SCALAR_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_SUBDWORD_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_READER_SUBDWORD_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_SUBDWORD_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_MEM128_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t error;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*h(1)=0 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(2)=1 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(3)=2 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(4)=3 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(5)=4 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(6)=5 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(7)=6 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(8)=7 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(9)=8 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(10)=9 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(11)=10 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(12)=11 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(13)=12 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(14)=13 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(15)=14 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(16)=15 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(17)=16 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(18)=17 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(19)=18 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(20)=19 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(21)=20 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(22)=21 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(23)=22 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(24)=23 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(25)=24 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(26)=25 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(27)=26 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(28)=27 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(29)=28 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(30)=29 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR}, +/*h(31)=30 BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR*/ {XED_ERROR_GENERAL_ERROR} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BCAST(xes); +hidx = key - 1; +if(hidx <= 30) { + xed3_operand_set_error(xes,lu_table[hidx].error); + return 1; +} +else{ + xed3_operand_set_bcrc(xes,0); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE1_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_GSCAT_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE2_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE4_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_TUPLE8_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_NELEM_FULL_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t bcrc;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*h(1)=0 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(2)=1 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(3)=2 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(4)=3 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(5)=4 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(6)=5 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(7)=6 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(8)=7 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(9)=8 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(10)=9 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(11)=10 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(12)=11 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(13)=12 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(14)=13 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(15)=14 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(16)=15 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(17)=16 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(18)=17 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(19)=18 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(20)=19 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(21)=20 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(22)=21 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(23)=22 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(24)=23 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(25)=24 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(26)=25 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(27)=26 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(28)=27 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(29)=28 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(30)=29 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(31)=30 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BCAST(xes); +hidx = key - 1; +if(hidx <= 30) { + xed3_operand_set_bcrc(xes,lu_table[hidx].bcrc); + return 1; +} +else{ + xed3_operand_set_bcrc(xes,0); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_NELEM_HALF_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t bcrc;} lu_entry_t; +static const lu_entry_t lu_table[31] = { +/*h(1)=0 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(2)=1 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(3)=2 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(4)=3 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(5)=4 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(6)=5 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(7)=6 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(8)=7 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(9)=8 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(10)=9 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(11)=10 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(12)=11 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(13)=12 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(14)=13 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(15)=14 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(16)=15 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(17)=16 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(18)=17 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(19)=18 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(20)=19 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(21)=20 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(22)=21 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(23)=22 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(24)=23 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(25)=24 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(26)=25 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(27)=26 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(28)=27 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(29)=28 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(30)=29 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1}, +/*h(31)=30 BCAST!=0 -> FB BCRC=1 value=0x1*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BCAST(xes); +hidx = key - 1; +if(hidx <= 30) { + xed3_operand_set_bcrc(xes,lu_table[hidx].bcrc); + return 1; +} +else{ + xed3_operand_set_bcrc(xes,0); + return 1; +} +} +xed_uint32_t xed_encode_nonterminal_FIX_ROUND_LEN512_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_FIX_ROUND_LEN128_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_UISA_ENC_INDEX_ZMM_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t rexx ;xed_int8_t sibindex ;xed_int8_t vexdest4;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(252)=0 INDEX=XED_REG_ZMM0 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0,0}, +/*h(253)=1 INDEX=XED_REG_ZMM1 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1,0}, +/*h(254)=2 INDEX=XED_REG_ZMM2 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2,0}, +/*h(255)=3 INDEX=XED_REG_ZMM3 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3,0}, +/*h(256)=4 INDEX=XED_REG_ZMM4 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4,0}, +/*h(257)=5 INDEX=XED_REG_ZMM5 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5,0}, +/*h(258)=6 INDEX=XED_REG_ZMM6 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6,0}, +/*h(259)=7 INDEX=XED_REG_ZMM7 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7,0}, +/*h(260)=8 INDEX=XED_REG_ZMM8 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0,0}, +/*h(261)=9 INDEX=XED_REG_ZMM9 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1,0}, +/*h(262)=10 INDEX=XED_REG_ZMM10 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2,0}, +/*h(263)=11 INDEX=XED_REG_ZMM11 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3,0}, +/*h(264)=12 INDEX=XED_REG_ZMM12 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4,0}, +/*h(265)=13 INDEX=XED_REG_ZMM13 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5,0}, +/*h(266)=14 INDEX=XED_REG_ZMM14 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6,0}, +/*h(267)=15 INDEX=XED_REG_ZMM15 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7,0}, +/*h(268)=16 INDEX=XED_REG_ZMM16 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0,1}, +/*h(269)=17 INDEX=XED_REG_ZMM17 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1,1}, +/*h(270)=18 INDEX=XED_REG_ZMM18 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2,1}, +/*h(271)=19 INDEX=XED_REG_ZMM19 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3,1}, +/*h(272)=20 INDEX=XED_REG_ZMM20 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4,1}, +/*h(273)=21 INDEX=XED_REG_ZMM21 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5,1}, +/*h(274)=22 INDEX=XED_REG_ZMM22 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6,1}, +/*h(275)=23 INDEX=XED_REG_ZMM23 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7,1}, +/*h(276)=24 INDEX=XED_REG_ZMM24 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0,1}, +/*h(277)=25 INDEX=XED_REG_ZMM25 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1,1}, +/*h(278)=26 INDEX=XED_REG_ZMM26 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2,1}, +/*h(279)=27 INDEX=XED_REG_ZMM27 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3,1}, +/*h(280)=28 INDEX=XED_REG_ZMM28 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4,1}, +/*h(281)=29 INDEX=XED_REG_ZMM29 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5,1}, +/*h(282)=30 INDEX=XED_REG_ZMM30 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6,1}, +/*h(283)=31 INDEX=XED_REG_ZMM31 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_INDEX(xes); +hidx = key - 252; +if(hidx <= 31) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + xed3_operand_set_vexdest4(xes,lu_table[hidx].vexdest4); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UISA_ENC_INDEX_YMM_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t rexx ;xed_int8_t sibindex ;xed_int8_t vexdest4;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(220)=0 INDEX=XED_REG_YMM0 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0,0}, +/*h(221)=1 INDEX=XED_REG_YMM1 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1,0}, +/*h(222)=2 INDEX=XED_REG_YMM2 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2,0}, +/*h(223)=3 INDEX=XED_REG_YMM3 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3,0}, +/*h(224)=4 INDEX=XED_REG_YMM4 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4,0}, +/*h(225)=5 INDEX=XED_REG_YMM5 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5,0}, +/*h(226)=6 INDEX=XED_REG_YMM6 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6,0}, +/*h(227)=7 INDEX=XED_REG_YMM7 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7,0}, +/*h(228)=8 INDEX=XED_REG_YMM8 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0,0}, +/*h(229)=9 INDEX=XED_REG_YMM9 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1,0}, +/*h(230)=10 INDEX=XED_REG_YMM10 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2,0}, +/*h(231)=11 INDEX=XED_REG_YMM11 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3,0}, +/*h(232)=12 INDEX=XED_REG_YMM12 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4,0}, +/*h(233)=13 INDEX=XED_REG_YMM13 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5,0}, +/*h(234)=14 INDEX=XED_REG_YMM14 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6,0}, +/*h(235)=15 INDEX=XED_REG_YMM15 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7,0}, +/*h(236)=16 INDEX=XED_REG_YMM16 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0,1}, +/*h(237)=17 INDEX=XED_REG_YMM17 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1,1}, +/*h(238)=18 INDEX=XED_REG_YMM18 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2,1}, +/*h(239)=19 INDEX=XED_REG_YMM19 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3,1}, +/*h(240)=20 INDEX=XED_REG_YMM20 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4,1}, +/*h(241)=21 INDEX=XED_REG_YMM21 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5,1}, +/*h(242)=22 INDEX=XED_REG_YMM22 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6,1}, +/*h(243)=23 INDEX=XED_REG_YMM23 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7,1}, +/*h(244)=24 INDEX=XED_REG_YMM24 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0,1}, +/*h(245)=25 INDEX=XED_REG_YMM25 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1,1}, +/*h(246)=26 INDEX=XED_REG_YMM26 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2,1}, +/*h(247)=27 INDEX=XED_REG_YMM27 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3,1}, +/*h(248)=28 INDEX=XED_REG_YMM28 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4,1}, +/*h(249)=29 INDEX=XED_REG_YMM29 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5,1}, +/*h(250)=30 INDEX=XED_REG_YMM30 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6,1}, +/*h(251)=31 INDEX=XED_REG_YMM31 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_INDEX(xes); +hidx = key - 220; +if(hidx <= 31) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + xed3_operand_set_vexdest4(xes,lu_table[hidx].vexdest4); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UISA_ENC_INDEX_XMM_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t rexx ;xed_int8_t sibindex ;xed_int8_t vexdest4;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(188)=0 INDEX=XED_REG_XMM0 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0,0}, +/*h(189)=1 INDEX=XED_REG_XMM1 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1,0}, +/*h(190)=2 INDEX=XED_REG_XMM2 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2,0}, +/*h(191)=3 INDEX=XED_REG_XMM3 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3,0}, +/*h(192)=4 INDEX=XED_REG_XMM4 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4,0}, +/*h(193)=5 INDEX=XED_REG_XMM5 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5,0}, +/*h(194)=6 INDEX=XED_REG_XMM6 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6,0}, +/*h(195)=7 INDEX=XED_REG_XMM7 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7,0}, +/*h(196)=8 INDEX=XED_REG_XMM8 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0,0}, +/*h(197)=9 INDEX=XED_REG_XMM9 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1,0}, +/*h(198)=10 INDEX=XED_REG_XMM10 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2,0}, +/*h(199)=11 INDEX=XED_REG_XMM11 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3,0}, +/*h(200)=12 INDEX=XED_REG_XMM12 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4,0}, +/*h(201)=13 INDEX=XED_REG_XMM13 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5,0}, +/*h(202)=14 INDEX=XED_REG_XMM14 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6,0}, +/*h(203)=15 INDEX=XED_REG_XMM15 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7,0}, +/*h(204)=16 INDEX=XED_REG_XMM16 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {0,0,1}, +/*h(205)=17 INDEX=XED_REG_XMM17 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {0,1,1}, +/*h(206)=18 INDEX=XED_REG_XMM18 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {0,2,1}, +/*h(207)=19 INDEX=XED_REG_XMM19 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {0,3,1}, +/*h(208)=20 INDEX=XED_REG_XMM20 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0,4,1}, +/*h(209)=21 INDEX=XED_REG_XMM21 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {0,5,1}, +/*h(210)=22 INDEX=XED_REG_XMM22 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {0,6,1}, +/*h(211)=23 INDEX=XED_REG_XMM23 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {0,7,1}, +/*h(212)=24 INDEX=XED_REG_XMM24 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {1,0,1}, +/*h(213)=25 INDEX=XED_REG_XMM25 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {1,1,1}, +/*h(214)=26 INDEX=XED_REG_XMM26 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {1,2,1}, +/*h(215)=27 INDEX=XED_REG_XMM27 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {1,3,1}, +/*h(216)=28 INDEX=XED_REG_XMM28 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {1,4,1}, +/*h(217)=29 INDEX=XED_REG_XMM29 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {1,5,1}, +/*h(218)=30 INDEX=XED_REG_XMM30 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {1,6,1}, +/*h(219)=31 INDEX=XED_REG_XMM31 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {1,7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_INDEX(xes); +hidx = key - 188; +if(hidx <= 31) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + xed3_operand_set_vexdest4(xes,lu_table[hidx].vexdest4); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_NELEM_QUARTER_BIND(xed_encoder_request_t* xes) +{ +return 1; +(void)xes; +return 1; +} +xed_uint32_t xed_encode_nonterminal_ASZ_NONTERM_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t asz;} lu_entry_t; +static const lu_entry_t lu_table[9] = { +/*h(5)=0 EASZ=1 MODE=1 -> FB ASZ=1 value=0x1*/ {5, 1}, +/*h(10)=1 EASZ=2 MODE=2 -> FB ASZ=1 value=0x1*/ {10, 1}, +/*h(2)=2 EASZ=2 MODE=0 -> FB ASZ=1 value=0x1*/ {2, 1}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(1)=5 EASZ=1 MODE=0 -> FB ASZ=0 value=0x0*/ {1, 0}, +/*h(6)=6 EASZ=2 MODE=1 -> FB ASZ=0 value=0x0*/ {6, 0}, +/*h(11)=7 EASZ=3 MODE=2 -> FB ASZ=0 value=0x0*/ {11, 0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_EASZ_MODE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 9ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_asz(xes,lu_table[hidx].asz); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_ONE_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(648)=0 IMM_WIDTH=8 UIMM0=1 MODE=1 -> nothing*/ {648, }, +/*h(520)=1 IMM_WIDTH=8 UIMM0=1 MODE=0 -> nothing*/ {520, }, +/*h(776)=2 IMM_WIDTH=8 UIMM0=1 MODE=2 -> nothing*/ {776, } +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_IMM_WIDTH_MODE_UIMM0_1(xes); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UIMMv_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(259)=0 IMM_WIDTH=64 EOSZ=3 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=64*/ {259, 1}, +/*h(65)=1 IMM_WIDTH=16 EOSZ=1 UIMM0[iiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiii emit_type=letters nbits=16*/ {65, 2}, +/*h(130)=2 IMM_WIDTH=32 EOSZ=2 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32*/ {130, 3}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_EOSZ_IMM_WIDTH(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed_encoder_request_iforms(xes)->x_UIMMv=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_SIMMz_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t imm0signed ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(65)=0 IMM_WIDTH=16 EOSZ=1 UIMM0[iiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiii emit_type=letters nbits=16 FB IMM0SIGNED=1 value=0x1*/ {65, 1,1}, +/*h(130)=1 IMM_WIDTH=32 EOSZ=2 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32 FB IMM0SIGNED=1 value=0x1*/ {130, 1,2}, +/*h(131)=2 IMM_WIDTH=32 EOSZ=3 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32 FB IMM0SIGNED=1 value=0x1*/ {131, 1,3} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_EOSZ_IMM_WIDTH(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_imm0signed(xes,lu_table[hidx].imm0signed); + xed_encoder_request_iforms(xes)->x_SIMMz=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_SIMM8_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_int8_t imm0signed ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8)=0 IMM_WIDTH=8 UIMM0[iiiiiiii]=* -> emit uimm0=iiiiiiii emit_type=letters nbits=8 FB IMM0SIGNED=1 value=0x1*/ {1,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_IMM_WIDTH(xes); +hidx = key - 8; +if(hidx == 0) { + xed3_operand_set_imm0signed(xes,lu_table[hidx].imm0signed); + xed_encoder_request_iforms(xes)->x_SIMM8=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UIMM8_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8)=0 IMM_WIDTH=8 UIMM0[iiiiiiii]=* -> emit uimm0=iiiiiiii emit_type=letters nbits=8*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_IMM_WIDTH(xes); +hidx = key - 8; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_UIMM8=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UIMM8_1_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(0)=0 DUMMY=0 UIMM1[iiiiiiii]=* -> emit uimm1=iiiiiiii emit_type=letters nbits=8*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DUMMY(xes); +hidx = key - 0; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_UIMM8_1=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UIMM16_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16)=0 IMM_WIDTH=16 UIMM0[iiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiii emit_type=letters nbits=16*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_IMM_WIDTH(xes); +hidx = key - 16; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_UIMM16=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_UIMM32_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(32)=0 IMM_WIDTH=32 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_IMM_WIDTH(xes); +hidx = key - 32; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_UIMM32=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_BRDISP8_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8)=0 BRDISP_WIDTH=8 DISP[dddddddd]=* -> emit disp=dddddddd emit_type=letters nbits=8*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BRDISP_WIDTH(xes); +hidx = key - 8; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_BRDISP8=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_BRDISP32_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(32)=0 BRDISP_WIDTH=32 DISP[dddddddddddddddddddddddddddddddd]=* -> emit disp=dddddddddddddddddddddddddddddddd emit_type=letters nbits=32*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BRDISP_WIDTH(xes); +hidx = key - 32; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_BRDISP32=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_BRDISPz_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(224)=0 BRDISP_WIDTH=32 EOSZ=3 DISP[dddddddddddddddddddddddddddddddd]=* -> emit disp=dddddddddddddddddddddddddddddddd emit_type=letters nbits=32*/ {224, 1}, +/*h(160)=1 BRDISP_WIDTH=32 EOSZ=2 DISP[dddddddddddddddddddddddddddddddd]=* -> emit disp=dddddddddddddddddddddddddddddddd emit_type=letters nbits=32*/ {160, 2}, +/*h(80)=2 BRDISP_WIDTH=16 EOSZ=1 DISP[dddddddddddddddd]=* -> emit disp=dddddddddddddddd emit_type=letters nbits=16*/ {80, 3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_BRDISP_WIDTH_EOSZ(xes); +hidx = ((3*key % 7) % 3); +if(lu_table[hidx].key == key) { + xed_encoder_request_iforms(xes)->x_BRDISPz=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MEMDISPv_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(448)=0 DISP_WIDTH=64 EASZ=3 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=64*/ {448, 1}, +/*h(288)=1 DISP_WIDTH=32 EASZ=2 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=32*/ {288, 2}, +/*h(144)=2 DISP_WIDTH=16 EASZ=1 DISP[aaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaa emit_type=letters nbits=16*/ {144, 3} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH_EASZ(xes); +hidx = ((4*key % 7) % 3); +if(lu_table[hidx].key == key) { + xed_encoder_request_iforms(xes)->x_MEMDISPv=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MEMDISP32_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(32)=0 DISP_WIDTH=32 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=32*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 32; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_MEMDISP32=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MEMDISP16_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(16)=0 DISP_WIDTH=16 DISP[aaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaa emit_type=letters nbits=16*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 16; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_MEMDISP16=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MEMDISP8_BIND(xed_encoder_request_t* xes) +{ +typedef struct { xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[1] = { +/*h(8)=0 DISP_WIDTH=8 DISP[aaaaaaaa]=* -> emit disp=aaaaaaaa emit_type=letters nbits=8*/ {1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = key - 8; +if(hidx == 0) { + xed_encoder_request_iforms(xes)->x_MEMDISP8=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_nonterminal_MEMDISP_BIND(xed_encoder_request_t* xes) +{ +typedef struct {xed_uint32_t key; xed_int8_t need_memdisp ;xed_uint32_t emit;} lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(0)=0 DISP_WIDTH=0 -> FB NEED_MEMDISP=0 value=0x0*/ {0, 0,0}, +/*h(16)=1 DISP_WIDTH=16 DISP[aaaaaaaaaaaaaaaa]=* -> FB NEED_MEMDISP=16 value=0x10 emit disp=aaaaaaaaaaaaaaaa emit_type=letters nbits=16*/ {16, 16,2}, +/*h(32)=2 DISP_WIDTH=32 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> FB NEED_MEMDISP=32 value=0x20 emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=32*/ {32, 32,3}, +/*h(8)=3 DISP_WIDTH=8 DISP[aaaaaaaa]=* -> FB NEED_MEMDISP=8 value=0x8 emit disp=aaaaaaaa emit_type=letters nbits=8*/ {8, 8,4} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +key = xed_enc_lu_DISP_WIDTH(xes); +hidx = ((6*key % 5) % 4); +if(lu_table[hidx].key == key) { + xed3_operand_set_need_memdisp(xes,lu_table[hidx].need_memdisp); + xed_encoder_request_iforms(xes)->x_MEMDISP=lu_table[hidx].emit; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR8_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t needrex ;xed_int8_t norex ;xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[20] = { +/*h(82)=0 OUTREG=XED_REG_AL -> FB REG=0 value=0x0*/ {-1,-1,0,-1}, +/*h(83)=1 OUTREG=XED_REG_CL -> FB REG=1 value=0x1*/ {-1,-1,1,-1}, +/*h(84)=2 OUTREG=XED_REG_DL -> FB REG=2 value=0x2*/ {-1,-1,2,-1}, +/*h(85)=3 OUTREG=XED_REG_BL -> FB REG=3 value=0x3*/ {-1,-1,3,-1}, +/*h(86)=4 OUTREG=XED_REG_SPL -> FB REG=4 value=0x4 FB NEEDREX=1 value=0x1*/ {1,-1,4,-1}, +/*h(87)=5 OUTREG=XED_REG_BPL -> FB REG=5 value=0x5 FB NEEDREX=1 value=0x1*/ {1,-1,5,-1}, +/*h(88)=6 OUTREG=XED_REG_SIL -> FB REG=6 value=0x6 FB NEEDREX=1 value=0x1*/ {1,-1,6,-1}, +/*h(89)=7 OUTREG=XED_REG_DIL -> FB REG=7 value=0x7 FB NEEDREX=1 value=0x1*/ {1,-1,7,-1}, +/*h(90)=8 OUTREG=XED_REG_R8B -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {-1,-1,0,1}, +/*h(91)=9 OUTREG=XED_REG_R9B -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {-1,-1,1,1}, +/*h(92)=10 OUTREG=XED_REG_R10B -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {-1,-1,2,1}, +/*h(93)=11 OUTREG=XED_REG_R11B -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {-1,-1,3,1}, +/*h(94)=12 OUTREG=XED_REG_R12B -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {-1,-1,4,1}, +/*h(95)=13 OUTREG=XED_REG_R13B -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {-1,-1,5,1}, +/*h(96)=14 OUTREG=XED_REG_R14B -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {-1,-1,6,1}, +/*h(97)=15 OUTREG=XED_REG_R15B -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {-1,-1,7,1}, +/*h(98)=16 OUTREG=XED_REG_AH -> FB REG=4 value=0x4 FB NOREX=1 value=0x1*/ {-1,1,4,-1}, +/*h(99)=17 OUTREG=XED_REG_CH -> FB REG=5 value=0x5 FB NOREX=1 value=0x1*/ {-1,1,5,-1}, +/*h(100)=18 OUTREG=XED_REG_DH -> FB REG=6 value=0x6 FB NOREX=1 value=0x1*/ {-1,1,6,-1}, +/*h(101)=19 OUTREG=XED_REG_BH -> FB REG=7 value=0x7 FB NOREX=1 value=0x1*/ {-1,1,7,-1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 82; +if(hidx <= 19) { + if(lu_table[hidx].needrex >= 0) xed3_operand_set_needrex(xes,lu_table[hidx].needrex); + if(lu_table[hidx].norex >= 0) xed3_operand_set_norex(xes,lu_table[hidx].norex); + xed3_operand_set_reg(xes,lu_table[hidx].reg); + if(lu_table[hidx].rexr >= 0) xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR8_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t needrex ;xed_int8_t norex ;xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[20] = { +/*h(82)=0 OUTREG=XED_REG_AL -> FB RM=0 value=0x0*/ {-1,-1,-1,0}, +/*h(83)=1 OUTREG=XED_REG_CL -> FB RM=1 value=0x1*/ {-1,-1,-1,1}, +/*h(84)=2 OUTREG=XED_REG_DL -> FB RM=2 value=0x2*/ {-1,-1,-1,2}, +/*h(85)=3 OUTREG=XED_REG_BL -> FB RM=3 value=0x3*/ {-1,-1,-1,3}, +/*h(86)=4 OUTREG=XED_REG_SPL -> FB RM=4 value=0x4 FB NEEDREX=1 value=0x1*/ {1,-1,-1,4}, +/*h(87)=5 OUTREG=XED_REG_BPL -> FB RM=5 value=0x5 FB NEEDREX=1 value=0x1*/ {1,-1,-1,5}, +/*h(88)=6 OUTREG=XED_REG_SIL -> FB RM=6 value=0x6 FB NEEDREX=1 value=0x1*/ {1,-1,-1,6}, +/*h(89)=7 OUTREG=XED_REG_DIL -> FB RM=7 value=0x7 FB NEEDREX=1 value=0x1*/ {1,-1,-1,7}, +/*h(90)=8 OUTREG=XED_REG_R8B -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {-1,-1,1,0}, +/*h(91)=9 OUTREG=XED_REG_R9B -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {-1,-1,1,1}, +/*h(92)=10 OUTREG=XED_REG_R10B -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {-1,-1,1,2}, +/*h(93)=11 OUTREG=XED_REG_R11B -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {-1,-1,1,3}, +/*h(94)=12 OUTREG=XED_REG_R12B -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {-1,-1,1,4}, +/*h(95)=13 OUTREG=XED_REG_R13B -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {-1,-1,1,5}, +/*h(96)=14 OUTREG=XED_REG_R14B -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {-1,-1,1,6}, +/*h(97)=15 OUTREG=XED_REG_R15B -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {-1,-1,1,7}, +/*h(98)=16 OUTREG=XED_REG_AH -> FB RM=4 value=0x4 FB NOREX=1 value=0x1*/ {-1,1,-1,4}, +/*h(99)=17 OUTREG=XED_REG_CH -> FB RM=5 value=0x5 FB NOREX=1 value=0x1*/ {-1,1,-1,5}, +/*h(100)=18 OUTREG=XED_REG_DH -> FB RM=6 value=0x6 FB NOREX=1 value=0x1*/ {-1,1,-1,6}, +/*h(101)=19 OUTREG=XED_REG_BH -> FB RM=7 value=0x7 FB NOREX=1 value=0x1*/ {-1,1,-1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 82; +if(hidx <= 19) { + if(lu_table[hidx].needrex >= 0) xed3_operand_set_needrex(xes,lu_table[hidx].needrex); + if(lu_table[hidx].norex >= 0) xed3_operand_set_norex(xes,lu_table[hidx].norex); + if(lu_table[hidx].rexb >= 0) xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR8_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t needrex ;xed_int8_t norex ;xed_int8_t rexb ;xed_int8_t srm;} lu_entry_t; +static const lu_entry_t lu_table[20] = { +/*h(82)=0 OUTREG=XED_REG_AL -> FB SRM=0 value=0x0*/ {-1,-1,-1,0}, +/*h(83)=1 OUTREG=XED_REG_CL -> FB SRM=1 value=0x1*/ {-1,-1,-1,1}, +/*h(84)=2 OUTREG=XED_REG_DL -> FB SRM=2 value=0x2*/ {-1,-1,-1,2}, +/*h(85)=3 OUTREG=XED_REG_BL -> FB SRM=3 value=0x3*/ {-1,-1,-1,3}, +/*h(86)=4 OUTREG=XED_REG_SPL -> FB SRM=4 value=0x4 FB NEEDREX=1 value=0x1*/ {1,-1,-1,4}, +/*h(87)=5 OUTREG=XED_REG_BPL -> FB SRM=5 value=0x5 FB NEEDREX=1 value=0x1*/ {1,-1,-1,5}, +/*h(88)=6 OUTREG=XED_REG_SIL -> FB SRM=6 value=0x6 FB NEEDREX=1 value=0x1*/ {1,-1,-1,6}, +/*h(89)=7 OUTREG=XED_REG_DIL -> FB SRM=7 value=0x7 FB NEEDREX=1 value=0x1*/ {1,-1,-1,7}, +/*h(90)=8 OUTREG=XED_REG_R8B -> FB REXB=1 value=0x1 FB SRM=0 value=0x0*/ {-1,-1,1,0}, +/*h(91)=9 OUTREG=XED_REG_R9B -> FB REXB=1 value=0x1 FB SRM=1 value=0x1*/ {-1,-1,1,1}, +/*h(92)=10 OUTREG=XED_REG_R10B -> FB REXB=1 value=0x1 FB SRM=2 value=0x2*/ {-1,-1,1,2}, +/*h(93)=11 OUTREG=XED_REG_R11B -> FB REXB=1 value=0x1 FB SRM=3 value=0x3*/ {-1,-1,1,3}, +/*h(94)=12 OUTREG=XED_REG_R12B -> FB REXB=1 value=0x1 FB SRM=4 value=0x4*/ {-1,-1,1,4}, +/*h(95)=13 OUTREG=XED_REG_R13B -> FB REXB=1 value=0x1 FB SRM=5 value=0x5*/ {-1,-1,1,5}, +/*h(96)=14 OUTREG=XED_REG_R14B -> FB REXB=1 value=0x1 FB SRM=6 value=0x6*/ {-1,-1,1,6}, +/*h(97)=15 OUTREG=XED_REG_R15B -> FB REXB=1 value=0x1 FB SRM=7 value=0x7*/ {-1,-1,1,7}, +/*h(98)=16 OUTREG=XED_REG_AH -> FB SRM=4 value=0x4 FB NOREX=1 value=0x1*/ {-1,1,-1,4}, +/*h(99)=17 OUTREG=XED_REG_CH -> FB SRM=5 value=0x5 FB NOREX=1 value=0x1*/ {-1,1,-1,5}, +/*h(100)=18 OUTREG=XED_REG_DH -> FB SRM=6 value=0x6 FB NOREX=1 value=0x1*/ {-1,1,-1,6}, +/*h(101)=19 OUTREG=XED_REG_BH -> FB SRM=7 value=0x7 FB NOREX=1 value=0x1*/ {-1,1,-1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 82; +if(hidx <= 19) { + if(lu_table[hidx].needrex >= 0) xed3_operand_set_needrex(xes,lu_table[hidx].needrex); + if(lu_table[hidx].norex >= 0) xed3_operand_set_norex(xes,lu_table[hidx].norex); + if(lu_table[hidx].rexb >= 0) xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_srm(xes,lu_table[hidx].srm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_SEGe(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 148; +if(hidx <= 5) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR16e(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 34; +if(hidx <= 7) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32e(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[36] = { +/*empty slot1 */ {0}, +/*h(246)=1 MODE=2 OUTREG=XED_REG_R11D -> nothing*/ {246, }, +/*h(225)=2 MODE=1 OUTREG=XED_REG_ESI -> nothing*/ {225, }, +/*h(238)=3 MODE=2 OUTREG=XED_REG_R9D -> nothing*/ {238, }, +/*h(217)=4 MODE=1 OUTREG=XED_REG_ESP -> nothing*/ {217, }, +/*h(230)=5 MODE=2 OUTREG=XED_REG_EDI -> nothing*/ {230, }, +/*h(209)=6 MODE=1 OUTREG=XED_REG_EDX -> nothing*/ {209, }, +/*h(222)=7 MODE=2 OUTREG=XED_REG_EBP -> nothing*/ {222, }, +/*h(201)=8 MODE=1 OUTREG=XED_REG_EAX -> nothing*/ {201, }, +/*h(214)=9 MODE=2 OUTREG=XED_REG_EBX -> nothing*/ {214, }, +/*empty slot1 */ {0}, +/*h(206)=11 MODE=2 OUTREG=XED_REG_ECX -> nothing*/ {206, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(258)=16 MODE=2 OUTREG=XED_REG_R14D -> nothing*/ {258, }, +/*empty slot1 */ {0}, +/*h(250)=18 MODE=2 OUTREG=XED_REG_R12D -> nothing*/ {250, }, +/*h(229)=19 MODE=1 OUTREG=XED_REG_EDI -> nothing*/ {229, }, +/*h(242)=20 MODE=2 OUTREG=XED_REG_R10D -> nothing*/ {242, }, +/*h(221)=21 MODE=1 OUTREG=XED_REG_EBP -> nothing*/ {221, }, +/*h(234)=22 MODE=2 OUTREG=XED_REG_R8D -> nothing*/ {234, }, +/*h(213)=23 MODE=1 OUTREG=XED_REG_EBX -> nothing*/ {213, }, +/*h(226)=24 MODE=2 OUTREG=XED_REG_ESI -> nothing*/ {226, }, +/*h(205)=25 MODE=1 OUTREG=XED_REG_ECX -> nothing*/ {205, }, +/*h(218)=26 MODE=2 OUTREG=XED_REG_ESP -> nothing*/ {218, }, +/*empty slot1 */ {0}, +/*h(210)=28 MODE=2 OUTREG=XED_REG_EDX -> nothing*/ {210, }, +/*empty slot1 */ {0}, +/*h(202)=30 MODE=2 OUTREG=XED_REG_EAX -> nothing*/ {202, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(262)=33 MODE=2 OUTREG=XED_REG_R15D -> nothing*/ {262, }, +/*empty slot1 */ {0}, +/*h(254)=35 MODE=2 OUTREG=XED_REG_R13D -> nothing*/ {254, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 36ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32e_m32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 7) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32e_m64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR64e(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArAX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(267)=0 OUTREG=XED_REG_RAX EASZ=3 -> nothing*/ {267, }, +/*empty slot1 */ {0}, +/*h(137)=2 OUTREG=XED_REG_AX EASZ=1 -> nothing*/ {137, }, +/*h(202)=3 OUTREG=XED_REG_EAX EASZ=2 -> nothing*/ {202, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArBX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(149)=0 OUTREG=XED_REG_BX EASZ=1 -> nothing*/ {149, }, +/*h(214)=1 OUTREG=XED_REG_EBX EASZ=2 -> nothing*/ {214, }, +/*h(279)=2 OUTREG=XED_REG_RBX EASZ=3 -> nothing*/ {279, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArCX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(141)=0 OUTREG=XED_REG_CX EASZ=1 -> nothing*/ {141, }, +/*h(206)=1 OUTREG=XED_REG_ECX EASZ=2 -> nothing*/ {206, }, +/*h(271)=2 OUTREG=XED_REG_RCX EASZ=3 -> nothing*/ {271, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArDX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(145)=3 OUTREG=XED_REG_DX EASZ=1 -> nothing*/ {145, }, +/*h(210)=4 OUTREG=XED_REG_EDX EASZ=2 -> nothing*/ {210, }, +/*h(275)=5 OUTREG=XED_REG_RDX EASZ=3 -> nothing*/ {275, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArSI(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(161)=2 OUTREG=XED_REG_SI EASZ=1 -> nothing*/ {161, }, +/*h(226)=3 OUTREG=XED_REG_ESI EASZ=2 -> nothing*/ {226, }, +/*h(291)=4 OUTREG=XED_REG_RSI EASZ=3 -> nothing*/ {291, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArDI(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(230)=0 OUTREG=XED_REG_EDI EASZ=2 -> nothing*/ {230, }, +/*h(295)=1 OUTREG=XED_REG_RDI EASZ=3 -> nothing*/ {295, }, +/*empty slot1 */ {0}, +/*h(165)=3 OUTREG=XED_REG_DI EASZ=1 -> nothing*/ {165, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArSP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(153)=2 OUTREG=XED_REG_SP EASZ=1 -> nothing*/ {153, }, +/*h(218)=3 OUTREG=XED_REG_ESP EASZ=2 -> nothing*/ {218, }, +/*h(283)=4 OUTREG=XED_REG_RSP EASZ=3 -> nothing*/ {283, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ArBP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(157)=0 OUTREG=XED_REG_BP EASZ=1 -> nothing*/ {157, }, +/*h(222)=1 OUTREG=XED_REG_EBP EASZ=2 -> nothing*/ {222, }, +/*h(287)=2 OUTREG=XED_REG_RBP EASZ=3 -> nothing*/ {287, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_SrSP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1094)=0 OUTREG=XED_REG_RSP SMODE=2 -> nothing*/ {1094, }, +/*h(38)=1 OUTREG=XED_REG_SP SMODE=0 -> nothing*/ {38, }, +/*h(566)=2 OUTREG=XED_REG_ESP SMODE=1 -> nothing*/ {566, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG_SMODE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_SrBP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(39)=0 OUTREG=XED_REG_BP SMODE=0 -> nothing*/ {39, }, +/*h(567)=1 OUTREG=XED_REG_EBP SMODE=1 -> nothing*/ {567, }, +/*h(1095)=2 OUTREG=XED_REG_RBP SMODE=2 -> nothing*/ {1095, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG_SMODE(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar8(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*empty slot1 */ {0}, +/*h(169)=1 OUTREG=XED_REG_R8W EASZ=1 -> nothing*/ {169, }, +/*h(234)=2 OUTREG=XED_REG_R8D EASZ=2 -> nothing*/ {234, }, +/*h(299)=3 OUTREG=XED_REG_R8 EASZ=3 -> nothing*/ {299, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar9(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(238)=0 OUTREG=XED_REG_R9D EASZ=2 -> nothing*/ {238, }, +/*h(303)=1 OUTREG=XED_REG_R9 EASZ=3 -> nothing*/ {303, }, +/*empty slot1 */ {0}, +/*h(173)=3 OUTREG=XED_REG_R9W EASZ=1 -> nothing*/ {173, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar10(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0}, +/*h(177)=1 OUTREG=XED_REG_R10W EASZ=1 -> nothing*/ {177, }, +/*h(242)=2 OUTREG=XED_REG_R10D EASZ=2 -> nothing*/ {242, }, +/*h(307)=3 OUTREG=XED_REG_R10 EASZ=3 -> nothing*/ {307, }, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar11(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(246)=0 OUTREG=XED_REG_R11D EASZ=2 -> nothing*/ {246, }, +/*h(311)=1 OUTREG=XED_REG_R11 EASZ=3 -> nothing*/ {311, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(181)=4 OUTREG=XED_REG_R11W EASZ=1 -> nothing*/ {181, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar12(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0}, +/*h(185)=1 OUTREG=XED_REG_R12W EASZ=1 -> nothing*/ {185, }, +/*h(250)=2 OUTREG=XED_REG_R12D EASZ=2 -> nothing*/ {250, }, +/*h(315)=3 OUTREG=XED_REG_R12 EASZ=3 -> nothing*/ {315, }, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar13(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(319)=0 OUTREG=XED_REG_R13 EASZ=3 -> nothing*/ {319, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(189)=4 OUTREG=XED_REG_R13W EASZ=1 -> nothing*/ {189, }, +/*h(254)=5 OUTREG=XED_REG_R13D EASZ=2 -> nothing*/ {254, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar14(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0}, +/*h(193)=1 OUTREG=XED_REG_R14W EASZ=1 -> nothing*/ {193, }, +/*h(258)=2 OUTREG=XED_REG_R14D EASZ=2 -> nothing*/ {258, }, +/*h(323)=3 OUTREG=XED_REG_R14 EASZ=3 -> nothing*/ {323, }, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_Ar15(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(327)=0 OUTREG=XED_REG_R15 EASZ=3 -> nothing*/ {327, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(197)=3 OUTREG=XED_REG_R15W EASZ=1 -> nothing*/ {197, }, +/*h(262)=4 OUTREG=XED_REG_R15D EASZ=2 -> nothing*/ {262, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_rIP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(416)=0 OUTREG=XED_REG_EIP MODE=0 -> nothing*/ {416, }, +/*empty slot1 */ {0}, +/*h(417)=2 OUTREG=XED_REG_EIP MODE=1 -> nothing*/ {417, }, +/*h(414)=3 OUTREG=XED_REG_RIP MODE=2 -> nothing*/ {414, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_rIPa(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[2] = { +/*h(418)=0 OUTREG=XED_REG_EIP EASZ=2 -> nothing*/ {418, }, +/*h(415)=1 OUTREG=XED_REG_RIP EASZ=3 -> nothing*/ {415, } +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = (3*key % 2); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OeAX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*empty slot1 */ {0}, +/*h(203)=1 OUTREG=XED_REG_EAX EOSZ=3 -> nothing*/ {203, }, +/*h(137)=2 OUTREG=XED_REG_AX EOSZ=1 -> nothing*/ {137, }, +/*h(202)=3 OUTREG=XED_REG_EAX EOSZ=2 -> nothing*/ {202, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OrAX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[4] = { +/*h(267)=0 OUTREG=XED_REG_RAX EOSZ=3 -> nothing*/ {267, }, +/*empty slot1 */ {0}, +/*h(137)=2 OUTREG=XED_REG_AX EOSZ=1 -> nothing*/ {137, }, +/*h(202)=3 OUTREG=XED_REG_EAX EOSZ=2 -> nothing*/ {202, } +}; +xed_union64_t t; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, t.s.lo32 >> (32-2)); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OrDX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(145)=3 OUTREG=XED_REG_DX EOSZ=1 -> nothing*/ {145, }, +/*h(210)=4 OUTREG=XED_REG_EDX EOSZ=2 -> nothing*/ {210, }, +/*h(275)=5 OUTREG=XED_REG_RDX EOSZ=3 -> nothing*/ {275, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OrCX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(141)=0 OUTREG=XED_REG_CX EOSZ=1 -> nothing*/ {141, }, +/*h(206)=1 OUTREG=XED_REG_ECX EOSZ=2 -> nothing*/ {206, }, +/*h(271)=2 OUTREG=XED_REG_RCX EOSZ=3 -> nothing*/ {271, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OrBX(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(149)=0 OUTREG=XED_REG_BX EOSZ=1 -> nothing*/ {149, }, +/*h(214)=1 OUTREG=XED_REG_EBX EOSZ=2 -> nothing*/ {214, }, +/*h(279)=2 OUTREG=XED_REG_RBX EOSZ=3 -> nothing*/ {279, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OrSP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*h(153)=2 OUTREG=XED_REG_SP EOSZ=1 -> nothing*/ {153, }, +/*h(218)=3 OUTREG=XED_REG_ESP EOSZ=2 -> nothing*/ {218, }, +/*h(283)=4 OUTREG=XED_REG_RSP EOSZ=3 -> nothing*/ {283, } +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 5ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_OrBP(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(157)=0 OUTREG=XED_REG_BP EOSZ=1 -> nothing*/ {157, }, +/*h(222)=1 OUTREG=XED_REG_EBP EOSZ=2 -> nothing*/ {222, }, +/*h(287)=2 OUTREG=XED_REG_RBP EOSZ=3 -> nothing*/ {287, }, +/*empty slot1 */ {0}, +/*empty slot1 */ {0}, +/*empty slot1 */ {0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_rFLAGS(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; } lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(129)=0 OUTREG=XED_REG_EFLAGS MODE=1 -> nothing*/ {129, }, +/*h(124)=1 OUTREG=XED_REG_FLAGS MODE=0 -> nothing*/ {124, }, +/*h(134)=2 OUTREG=XED_REG_RFLAGS MODE=2 -> nothing*/ {134, } +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (4*key % 3); +if(lu_table[hidx].key == key) { + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MMX_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(114)=0 OUTREG=XED_REG_MMX0 -> FB REG=0 value=0x0*/ {0}, +/*h(115)=1 OUTREG=XED_REG_MMX1 -> FB REG=1 value=0x1*/ {1}, +/*h(116)=2 OUTREG=XED_REG_MMX2 -> FB REG=2 value=0x2*/ {2}, +/*h(117)=3 OUTREG=XED_REG_MMX3 -> FB REG=3 value=0x3*/ {3}, +/*h(118)=4 OUTREG=XED_REG_MMX4 -> FB REG=4 value=0x4*/ {4}, +/*h(119)=5 OUTREG=XED_REG_MMX5 -> FB REG=5 value=0x5*/ {5}, +/*h(120)=6 OUTREG=XED_REG_MMX6 -> FB REG=6 value=0x6*/ {6}, +/*h(121)=7 OUTREG=XED_REG_MMX7 -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 114; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MMX_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(114)=0 OUTREG=XED_REG_MMX0 -> FB RM=0 value=0x0*/ {0}, +/*h(115)=1 OUTREG=XED_REG_MMX1 -> FB RM=1 value=0x1*/ {1}, +/*h(116)=2 OUTREG=XED_REG_MMX2 -> FB RM=2 value=0x2*/ {2}, +/*h(117)=3 OUTREG=XED_REG_MMX3 -> FB RM=3 value=0x3*/ {3}, +/*h(118)=4 OUTREG=XED_REG_MMX4 -> FB RM=4 value=0x4*/ {4}, +/*h(119)=5 OUTREG=XED_REG_MMX5 -> FB RM=5 value=0x5*/ {5}, +/*h(120)=6 OUTREG=XED_REG_MMX6 -> FB RM=6 value=0x6*/ {6}, +/*h(121)=7 OUTREG=XED_REG_MMX7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 114; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRv_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR16_R}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_R}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR64_R} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRv_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR16_SB}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_SB}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR64_SB} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRz_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR16_R}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_R}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR32_R} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRv_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR16_B}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_B}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR64_B} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRz_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR16_B}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_B}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR32_B} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRy_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR32_B}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_B}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR64_B} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPRy_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_GPR32_R}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_GPR32_R}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_GPR64_R} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR64_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 OUTREG=XED_REG_RAX -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(67)=1 OUTREG=XED_REG_RCX -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(68)=2 OUTREG=XED_REG_RDX -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(69)=3 OUTREG=XED_REG_RBX -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(70)=4 OUTREG=XED_REG_RSP -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(71)=5 OUTREG=XED_REG_RBP -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(73)=7 OUTREG=XED_REG_RDI -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(74)=8 OUTREG=XED_REG_R8 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(75)=9 OUTREG=XED_REG_R9 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(76)=10 OUTREG=XED_REG_R10 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(77)=11 OUTREG=XED_REG_R11 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(78)=12 OUTREG=XED_REG_R12 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(79)=13 OUTREG=XED_REG_R13 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(81)=15 OUTREG=XED_REG_R15 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR64_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 OUTREG=XED_REG_RAX -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(67)=1 OUTREG=XED_REG_RCX -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(68)=2 OUTREG=XED_REG_RDX -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(69)=3 OUTREG=XED_REG_RBX -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(70)=4 OUTREG=XED_REG_RSP -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(71)=5 OUTREG=XED_REG_RBP -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(73)=7 OUTREG=XED_REG_RDI -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(74)=8 OUTREG=XED_REG_R8 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(75)=9 OUTREG=XED_REG_R9 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(76)=10 OUTREG=XED_REG_R10 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(77)=11 OUTREG=XED_REG_R11 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(78)=12 OUTREG=XED_REG_R12 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(79)=13 OUTREG=XED_REG_R13 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(81)=15 OUTREG=XED_REG_R15 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR64_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t srm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 OUTREG=XED_REG_RAX -> FB REXB=0 value=0x0 FB SRM=0 value=0x0*/ {0,0}, +/*h(67)=1 OUTREG=XED_REG_RCX -> FB REXB=0 value=0x0 FB SRM=1 value=0x1*/ {0,1}, +/*h(68)=2 OUTREG=XED_REG_RDX -> FB REXB=0 value=0x0 FB SRM=2 value=0x2*/ {0,2}, +/*h(69)=3 OUTREG=XED_REG_RBX -> FB REXB=0 value=0x0 FB SRM=3 value=0x3*/ {0,3}, +/*h(70)=4 OUTREG=XED_REG_RSP -> FB REXB=0 value=0x0 FB SRM=4 value=0x4*/ {0,4}, +/*h(71)=5 OUTREG=XED_REG_RBP -> FB REXB=0 value=0x0 FB SRM=5 value=0x5*/ {0,5}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB REXB=0 value=0x0 FB SRM=6 value=0x6*/ {0,6}, +/*h(73)=7 OUTREG=XED_REG_RDI -> FB REXB=0 value=0x0 FB SRM=7 value=0x7*/ {0,7}, +/*h(74)=8 OUTREG=XED_REG_R8 -> FB REXB=1 value=0x1 FB SRM=0 value=0x0*/ {1,0}, +/*h(75)=9 OUTREG=XED_REG_R9 -> FB REXB=1 value=0x1 FB SRM=1 value=0x1*/ {1,1}, +/*h(76)=10 OUTREG=XED_REG_R10 -> FB REXB=1 value=0x1 FB SRM=2 value=0x2*/ {1,2}, +/*h(77)=11 OUTREG=XED_REG_R11 -> FB REXB=1 value=0x1 FB SRM=3 value=0x3*/ {1,3}, +/*h(78)=12 OUTREG=XED_REG_R12 -> FB REXB=1 value=0x1 FB SRM=4 value=0x4*/ {1,4}, +/*h(79)=13 OUTREG=XED_REG_R13 -> FB REXB=1 value=0x1 FB SRM=5 value=0x5*/ {1,5}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB REXB=1 value=0x1 FB SRM=6 value=0x6*/ {1,6}, +/*h(81)=15 OUTREG=XED_REG_R15 -> FB REXB=1 value=0x1 FB SRM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_srm(xes,lu_table[hidx].srm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR64_X(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexx ;xed_int8_t sibindex;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(0)=0 OUTREG=XED_REG_INVALID -> FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0, 0,4}, +/*h(81)=1 OUTREG=XED_REG_R15 -> FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {81, 1,7}, +/*h(76)=2 OUTREG=XED_REG_R10 -> FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {76, 1,2}, +/*h(71)=3 OUTREG=XED_REG_RBP -> FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {71, 0,5}, +/*h(66)=4 OUTREG=XED_REG_RAX -> FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {66, 0,0}, +/*h(77)=5 OUTREG=XED_REG_R11 -> FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {77, 1,3}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {72, 0,6}, +/*h(67)=7 OUTREG=XED_REG_RCX -> FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {67, 0,1}, +/*h(78)=8 OUTREG=XED_REG_R12 -> FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {78, 1,4}, +/*h(73)=9 OUTREG=XED_REG_RDI -> FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {73, 0,7}, +/*h(68)=10 OUTREG=XED_REG_RDX -> FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {68, 0,2}, +/*h(79)=11 OUTREG=XED_REG_R13 -> FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {79, 1,5}, +/*h(74)=12 OUTREG=XED_REG_R8 -> FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {74, 1,0}, +/*h(69)=13 OUTREG=XED_REG_RBX -> FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {69, 0,3}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {80, 1,6}, +/*h(75)=15 OUTREG=XED_REG_R9 -> FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {75, 1,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = ((3*key % 89) % 16); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(58)=8 OUTREG=XED_REG_R8D -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(60)=10 OUTREG=XED_REG_R10D -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(61)=11 OUTREG=XED_REG_R11D -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(62)=12 OUTREG=XED_REG_R12D -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(63)=13 OUTREG=XED_REG_R13D -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(64)=14 OUTREG=XED_REG_R14D -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(65)=15 OUTREG=XED_REG_R15D -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(58)=8 OUTREG=XED_REG_R8D -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(60)=10 OUTREG=XED_REG_R10D -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(61)=11 OUTREG=XED_REG_R11D -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(62)=12 OUTREG=XED_REG_R12D -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(63)=13 OUTREG=XED_REG_R13D -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(64)=14 OUTREG=XED_REG_R14D -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(65)=15 OUTREG=XED_REG_R15D -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t srm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB REXB=0 value=0x0 FB SRM=0 value=0x0*/ {0,0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB REXB=0 value=0x0 FB SRM=1 value=0x1*/ {0,1}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REXB=0 value=0x0 FB SRM=2 value=0x2*/ {0,2}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB REXB=0 value=0x0 FB SRM=3 value=0x3*/ {0,3}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB REXB=0 value=0x0 FB SRM=4 value=0x4*/ {0,4}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB REXB=0 value=0x0 FB SRM=5 value=0x5*/ {0,5}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB REXB=0 value=0x0 FB SRM=6 value=0x6*/ {0,6}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB REXB=0 value=0x0 FB SRM=7 value=0x7*/ {0,7}, +/*h(58)=8 OUTREG=XED_REG_R8D -> FB REXB=1 value=0x1 FB SRM=0 value=0x0*/ {1,0}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB REXB=1 value=0x1 FB SRM=1 value=0x1*/ {1,1}, +/*h(60)=10 OUTREG=XED_REG_R10D -> FB REXB=1 value=0x1 FB SRM=2 value=0x2*/ {1,2}, +/*h(61)=11 OUTREG=XED_REG_R11D -> FB REXB=1 value=0x1 FB SRM=3 value=0x3*/ {1,3}, +/*h(62)=12 OUTREG=XED_REG_R12D -> FB REXB=1 value=0x1 FB SRM=4 value=0x4*/ {1,4}, +/*h(63)=13 OUTREG=XED_REG_R13D -> FB REXB=1 value=0x1 FB SRM=5 value=0x5*/ {1,5}, +/*h(64)=14 OUTREG=XED_REG_R14D -> FB REXB=1 value=0x1 FB SRM=6 value=0x6*/ {1,6}, +/*h(65)=15 OUTREG=XED_REG_R15D -> FB REXB=1 value=0x1 FB SRM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_srm(xes,lu_table[hidx].srm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR32_X(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexx ;xed_int8_t sibindex;} lu_entry_t; +static const lu_entry_t lu_table[21] = { +/*h(0)=0 OUTREG=XED_REG_INVALID -> FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4*/ {0, 0,4}, +/*h(60)=1 OUTREG=XED_REG_R10D -> FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2*/ {60, 1,2}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2*/ {52, 0,2}, +/*h(65)=3 OUTREG=XED_REG_R15D -> FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7*/ {65, 1,7}, +/*h(57)=4 OUTREG=XED_REG_EDI -> FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7*/ {57, 0,7}, +/*empty slot1 */ {0,0,0}, +/*h(62)=6 OUTREG=XED_REG_R12D -> FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4*/ {62, 1,4}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1*/ {59, 1,1}, +/*h(51)=10 OUTREG=XED_REG_ECX -> FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1*/ {51, 0,1}, +/*h(64)=11 OUTREG=XED_REG_R14D -> FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6*/ {64, 1,6}, +/*h(56)=12 OUTREG=XED_REG_ESI -> FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6*/ {56, 0,6}, +/*empty slot1 */ {0,0,0}, +/*h(61)=14 OUTREG=XED_REG_R11D -> FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3*/ {61, 1,3}, +/*h(53)=15 OUTREG=XED_REG_EBX -> FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3*/ {53, 0,3}, +/*empty slot1 */ {0,0,0}, +/*h(58)=17 OUTREG=XED_REG_R8D -> FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0*/ {58, 1,0}, +/*h(50)=18 OUTREG=XED_REG_EAX -> FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0*/ {50, 0,0}, +/*h(63)=19 OUTREG=XED_REG_R13D -> FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5*/ {63, 1,5}, +/*h(55)=20 OUTREG=XED_REG_EBP -> FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5*/ {55, 0,5} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 21ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_sibindex(xes,lu_table[hidx].sibindex); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR16_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(34)=0 OUTREG=XED_REG_AX -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(35)=1 OUTREG=XED_REG_CX -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(36)=2 OUTREG=XED_REG_DX -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(37)=3 OUTREG=XED_REG_BX -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(38)=4 OUTREG=XED_REG_SP -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(39)=5 OUTREG=XED_REG_BP -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(40)=6 OUTREG=XED_REG_SI -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(41)=7 OUTREG=XED_REG_DI -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(42)=8 OUTREG=XED_REG_R8W -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(43)=9 OUTREG=XED_REG_R9W -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(44)=10 OUTREG=XED_REG_R10W -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(45)=11 OUTREG=XED_REG_R11W -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(46)=12 OUTREG=XED_REG_R12W -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(47)=13 OUTREG=XED_REG_R13W -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(48)=14 OUTREG=XED_REG_R14W -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(49)=15 OUTREG=XED_REG_R15W -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 34; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR16_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(34)=0 OUTREG=XED_REG_AX -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(35)=1 OUTREG=XED_REG_CX -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(36)=2 OUTREG=XED_REG_DX -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(37)=3 OUTREG=XED_REG_BX -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(38)=4 OUTREG=XED_REG_SP -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(39)=5 OUTREG=XED_REG_BP -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(40)=6 OUTREG=XED_REG_SI -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(41)=7 OUTREG=XED_REG_DI -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(42)=8 OUTREG=XED_REG_R8W -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(43)=9 OUTREG=XED_REG_R9W -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(44)=10 OUTREG=XED_REG_R10W -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(45)=11 OUTREG=XED_REG_R11W -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(46)=12 OUTREG=XED_REG_R12W -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(47)=13 OUTREG=XED_REG_R13W -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(48)=14 OUTREG=XED_REG_R14W -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(49)=15 OUTREG=XED_REG_R15W -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 34; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_GPR16_SB(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t srm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(34)=0 OUTREG=XED_REG_AX -> FB REXB=0 value=0x0 FB SRM=0 value=0x0*/ {0,0}, +/*h(35)=1 OUTREG=XED_REG_CX -> FB REXB=0 value=0x0 FB SRM=1 value=0x1*/ {0,1}, +/*h(36)=2 OUTREG=XED_REG_DX -> FB REXB=0 value=0x0 FB SRM=2 value=0x2*/ {0,2}, +/*h(37)=3 OUTREG=XED_REG_BX -> FB REXB=0 value=0x0 FB SRM=3 value=0x3*/ {0,3}, +/*h(38)=4 OUTREG=XED_REG_SP -> FB REXB=0 value=0x0 FB SRM=4 value=0x4*/ {0,4}, +/*h(39)=5 OUTREG=XED_REG_BP -> FB REXB=0 value=0x0 FB SRM=5 value=0x5*/ {0,5}, +/*h(40)=6 OUTREG=XED_REG_SI -> FB REXB=0 value=0x0 FB SRM=6 value=0x6*/ {0,6}, +/*h(41)=7 OUTREG=XED_REG_DI -> FB REXB=0 value=0x0 FB SRM=7 value=0x7*/ {0,7}, +/*h(42)=8 OUTREG=XED_REG_R8W -> FB REXB=1 value=0x1 FB SRM=0 value=0x0*/ {1,0}, +/*h(43)=9 OUTREG=XED_REG_R9W -> FB REXB=1 value=0x1 FB SRM=1 value=0x1*/ {1,1}, +/*h(44)=10 OUTREG=XED_REG_R10W -> FB REXB=1 value=0x1 FB SRM=2 value=0x2*/ {1,2}, +/*h(45)=11 OUTREG=XED_REG_R11W -> FB REXB=1 value=0x1 FB SRM=3 value=0x3*/ {1,3}, +/*h(46)=12 OUTREG=XED_REG_R12W -> FB REXB=1 value=0x1 FB SRM=4 value=0x4*/ {1,4}, +/*h(47)=13 OUTREG=XED_REG_R13W -> FB REXB=1 value=0x1 FB SRM=5 value=0x5*/ {1,5}, +/*h(48)=14 OUTREG=XED_REG_R14W -> FB REXB=1 value=0x1 FB SRM=6 value=0x6*/ {1,6}, +/*h(49)=15 OUTREG=XED_REG_R15W -> FB REXB=1 value=0x1 FB SRM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 34; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_srm(xes,lu_table[hidx].srm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_CR_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(102)=0 OUTREG=XED_REG_ERROR -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {102, 1,0}, +/*h(10)=1 OUTREG=XED_REG_CR3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {10, 3,0}, +/*h(15)=2 OUTREG=XED_REG_CR8 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {15, 0,1}, +/*h(7)=3 OUTREG=XED_REG_CR0 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {7, 0,0}, +/*empty slot1 */ {0,0,0}, +/*h(9)=5 OUTREG=XED_REG_CR2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {9, 2,0}, +/*empty slot1 */ {0,0,0}, +/*h(11)=7 OUTREG=XED_REG_CR4 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {11, 4,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_CR_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(102)=0 OUTREG=XED_REG_ERROR -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {102, 0,1}, +/*h(10)=1 OUTREG=XED_REG_CR3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {10, 0,3}, +/*h(15)=2 OUTREG=XED_REG_CR8 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {15, 1,0}, +/*h(7)=3 OUTREG=XED_REG_CR0 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {7, 0,0}, +/*empty slot1 */ {0,0,0}, +/*h(9)=5 OUTREG=XED_REG_CR2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {9, 0,2}, +/*empty slot1 */ {0,0,0}, +/*h(11)=7 OUTREG=XED_REG_CR4 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {11, 0,4}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_DR_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[15] = { +/*h(102)=0 OUTREG=XED_REG_ERROR -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {102, 0,1}, +/*h(26)=1 OUTREG=XED_REG_DR3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {26, 3,0}, +/*empty slot1 */ {0,0,0}, +/*h(23)=3 OUTREG=XED_REG_DR0 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {23, 0,0}, +/*h(28)=4 OUTREG=XED_REG_DR5 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {28, 5,0}, +/*empty slot1 */ {0,0,0}, +/*h(25)=6 OUTREG=XED_REG_DR2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {25, 2,0}, +/*empty slot1 */ {0,0,0}, +/*h(30)=8 OUTREG=XED_REG_DR7 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {30, 7,0}, +/*empty slot1 */ {0,0,0}, +/*h(27)=10 OUTREG=XED_REG_DR4 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {27, 4,0}, +/*empty slot1 */ {0,0,0}, +/*h(24)=12 OUTREG=XED_REG_DR1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {24, 1,0}, +/*h(29)=13 OUTREG=XED_REG_DR6 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {29, 6,0}, +/*empty slot1 */ {0,0,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 15ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_X87(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(179)=0 OUTREG=XED_REG_ST0 -> FB RM=0 value=0x0*/ {0}, +/*h(180)=1 OUTREG=XED_REG_ST1 -> FB RM=1 value=0x1*/ {1}, +/*h(181)=2 OUTREG=XED_REG_ST2 -> FB RM=2 value=0x2*/ {2}, +/*h(182)=3 OUTREG=XED_REG_ST3 -> FB RM=3 value=0x3*/ {3}, +/*h(183)=4 OUTREG=XED_REG_ST4 -> FB RM=4 value=0x4*/ {4}, +/*h(184)=5 OUTREG=XED_REG_ST5 -> FB RM=5 value=0x5*/ {5}, +/*h(185)=6 OUTREG=XED_REG_ST6 -> FB RM=6 value=0x6*/ {6}, +/*h(186)=7 OUTREG=XED_REG_ST7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 179; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_SEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[12] = { +/*h(102)=0 OUTREG=XED_REG_ERROR -> FB REG=6 value=0x6*/ {102, 6}, +/*h(149)=1 OUTREG=XED_REG_CS -> FB REG=1 value=0x1*/ {149, 1}, +/*empty slot1 */ {0,0}, +/*h(151)=3 OUTREG=XED_REG_DS -> FB REG=3 value=0x3*/ {151, 3}, +/*empty slot1 */ {0,0}, +/*h(148)=5 OUTREG=XED_REG_ES -> FB REG=0 value=0x0*/ {148, 0}, +/*h(153)=6 OUTREG=XED_REG_GS -> FB REG=5 value=0x5*/ {153, 5}, +/*empty slot1 */ {0,0}, +/*h(150)=8 OUTREG=XED_REG_SS -> FB REG=2 value=0x2*/ {150, 2}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(152)=11 OUTREG=XED_REG_FS -> FB REG=4 value=0x4*/ {152, 4} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 12ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_SEG_MOV(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(102)=0 OUTREG=XED_REG_ERROR -> FB REG=6 value=0x6*/ {102, 6}, +/*h(151)=1 OUTREG=XED_REG_DS -> FB REG=3 value=0x3*/ {151, 3}, +/*h(148)=2 OUTREG=XED_REG_ES -> FB REG=0 value=0x0*/ {148, 0}, +/*h(153)=3 OUTREG=XED_REG_GS -> FB REG=5 value=0x5*/ {153, 5}, +/*h(150)=4 OUTREG=XED_REG_SS -> FB REG=2 value=0x2*/ {150, 2}, +/*h(152)=5 OUTREG=XED_REG_FS -> FB REG=4 value=0x4*/ {152, 4} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 6ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_DSEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_FINAL_DSEG_NOT64}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_FINAL_DSEG_NOT64}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_FINAL_DSEG_MODE64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_DSEG_NOT64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t seg_ovd ;xed_int8_t using_default_segment0;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(148)=0 OUTREG=XED_REG_ES -> FB SEG_OVD=3 value=0x3 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {3,0}, +/*h(149)=1 OUTREG=XED_REG_CS -> FB SEG_OVD=1 value=0x1 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {1,0}, +/*h(150)=2 OUTREG=XED_REG_SS -> FB SEG_OVD=6 value=0x6 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {6,0}, +/*h(151)=3 OUTREG=XED_REG_DS -> FB SEG_OVD=0 value=0x0 FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {0,1}, +/*h(152)=4 OUTREG=XED_REG_FS -> FB SEG_OVD=4 value=0x4 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {4,0}, +/*h(153)=5 OUTREG=XED_REG_GS -> FB SEG_OVD=5 value=0x5 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {5,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 148; +if(hidx <= 5) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + xed3_operand_set_using_default_segment0(xes,lu_table[hidx].using_default_segment0); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_DSEG_MODE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t seg_ovd ;xed_int8_t using_default_segment0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 OUTREG=XED_REG_INVALID -> FB SEG_OVD=0 value=0x0 FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {0, 0,1}, +/*h(153)=1 OUTREG=XED_REG_GS -> FB SEG_OVD=5 value=0x5 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {153, 5,0}, +/*h(152)=2 OUTREG=XED_REG_FS -> FB SEG_OVD=4 value=0x4 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {152, 4,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + xed3_operand_set_using_default_segment0(xes,lu_table[hidx].using_default_segment0); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_DSEG1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_FINAL_DSEG1_NOT64}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_FINAL_DSEG1_NOT64}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_FINAL_DSEG1_MODE64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_DSEG1_NOT64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t seg_ovd ;xed_int8_t using_default_segment1;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(148)=0 OUTREG=XED_REG_ES -> FB SEG_OVD=3 value=0x3 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {3,0}, +/*h(149)=1 OUTREG=XED_REG_CS -> FB SEG_OVD=1 value=0x1 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {1,0}, +/*h(150)=2 OUTREG=XED_REG_SS -> FB SEG_OVD=6 value=0x6 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {6,0}, +/*h(151)=3 OUTREG=XED_REG_DS -> FB SEG_OVD=0 value=0x0 FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {0,1}, +/*h(152)=4 OUTREG=XED_REG_FS -> FB SEG_OVD=4 value=0x4 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {4,0}, +/*h(153)=5 OUTREG=XED_REG_GS -> FB SEG_OVD=5 value=0x5 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {5,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 148; +if(hidx <= 5) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + xed3_operand_set_using_default_segment1(xes,lu_table[hidx].using_default_segment1); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_DSEG1_MODE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t seg_ovd ;xed_int8_t using_default_segment1;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 OUTREG=XED_REG_INVALID -> FB SEG_OVD=0 value=0x0 FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {0, 0,1}, +/*h(153)=1 OUTREG=XED_REG_GS -> FB SEG_OVD=5 value=0x5 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {153, 5,0}, +/*h(152)=2 OUTREG=XED_REG_FS -> FB SEG_OVD=4 value=0x4 FB USING_DEFAULT_SEGMENT1=0 value=0x0*/ {152, 4,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + xed3_operand_set_using_default_segment1(xes,lu_table[hidx].using_default_segment1); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_ESEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t using_default_segment0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2)=0 OUTREG=XED_REG_INVALID MODE=2 -> FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {2, 1}, +/*h(593)=1 OUTREG=XED_REG_ES MODE=1 -> FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {593, 1}, +/*h(592)=2 OUTREG=XED_REG_ES MODE=0 -> FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {592, 1} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_using_default_segment0(xes,lu_table[hidx].using_default_segment0); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_ESEG1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t using_default_segment1;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2)=0 OUTREG=XED_REG_INVALID MODE=2 -> FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {2, 1}, +/*h(593)=1 OUTREG=XED_REG_ES MODE=1 -> FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {593, 1}, +/*h(592)=2 OUTREG=XED_REG_ES MODE=0 -> FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {592, 1} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_using_default_segment1(xes,lu_table[hidx].using_default_segment1); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_SSEG1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t using_default_segment1;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2)=0 OUTREG=XED_REG_INVALID MODE=2 -> FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {2, 1}, +/*h(601)=1 OUTREG=XED_REG_SS MODE=1 -> FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {601, 1}, +/*h(600)=2 OUTREG=XED_REG_SS MODE=0 -> FB USING_DEFAULT_SEGMENT1=1 value=0x1*/ {600, 1} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_using_default_segment1(xes,lu_table[hidx].using_default_segment1); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_SSEG0(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t using_default_segment0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(2)=0 OUTREG=XED_REG_INVALID MODE=2 -> FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {2, 1}, +/*h(601)=1 OUTREG=XED_REG_SS MODE=1 -> FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {601, 1}, +/*h(600)=2 OUTREG=XED_REG_SS MODE=0 -> FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {600, 1} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_using_default_segment0(xes,lu_table[hidx].using_default_segment0); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_SSEG(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_FINAL_SSEG_NOT64}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_FINAL_SSEG_NOT64}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_FINAL_SSEG_MODE64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_SSEG_NOT64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t seg_ovd ;xed_int8_t using_default_segment0;} lu_entry_t; +static const lu_entry_t lu_table[6] = { +/*h(148)=0 OUTREG=XED_REG_ES -> FB SEG_OVD=3 value=0x3 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {3,0}, +/*h(149)=1 OUTREG=XED_REG_CS -> FB SEG_OVD=1 value=0x1 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {1,0}, +/*h(150)=2 OUTREG=XED_REG_SS -> FB SEG_OVD=0 value=0x0 FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {0,1}, +/*h(151)=3 OUTREG=XED_REG_DS -> FB SEG_OVD=2 value=0x2 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {2,0}, +/*h(152)=4 OUTREG=XED_REG_FS -> FB SEG_OVD=4 value=0x4 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {4,0}, +/*h(153)=5 OUTREG=XED_REG_GS -> FB SEG_OVD=5 value=0x5 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {5,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 148; +if(hidx <= 5) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + xed3_operand_set_using_default_segment0(xes,lu_table[hidx].using_default_segment0); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_FINAL_SSEG_MODE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t seg_ovd ;xed_int8_t using_default_segment0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 OUTREG=XED_REG_INVALID -> FB SEG_OVD=0 value=0x0 FB USING_DEFAULT_SEGMENT0=1 value=0x1*/ {0, 0,1}, +/*h(153)=1 OUTREG=XED_REG_GS -> FB SEG_OVD=5 value=0x5 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {153, 5,0}, +/*h(152)=2 OUTREG=XED_REG_FS -> FB SEG_OVD=4 value=0x4 FB USING_DEFAULT_SEGMENT0=0 value=0x0*/ {152, 4,0} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 3ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_seg_ovd(xes,lu_table[hidx].seg_ovd); + xed3_operand_set_using_default_segment0(xes,lu_table[hidx].using_default_segment0); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_R_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_R_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_R_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_R_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB REG=0 value=0x0*/ {0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB REG=1 value=0x1*/ {1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB REG=2 value=0x2*/ {2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB REG=3 value=0x3*/ {3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB REG=4 value=0x4*/ {4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB REG=5 value=0x5*/ {5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB REG=6 value=0x6*/ {6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_R_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_B_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_B_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_B_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_B_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB RM=0 value=0x0*/ {0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB RM=1 value=0x1*/ {1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB RM=2 value=0x2*/ {2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB RM=3 value=0x3*/ {3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB RM=4 value=0x4*/ {4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB RM=5 value=0x5*/ {5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB RM=6 value=0x6*/ {6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-2.c b/CodeVirtualizer/build/obj/xed-encoder-2.c new file mode 100644 index 0000000..7e90b65 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-2.c @@ -0,0 +1,3061 @@ +/// @file xed-encoder-2.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encoder.h" +#include "xed-encode-private.h" +#include "xed-enc-operand-lu.h" +#include "xed-operand-accessors.h" +xed_uint32_t xed_encode_ntluf_XMM_B_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_BND_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 OUTREG=XED_REG_BND2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {5, 2,0}, +/*h(102)=1 OUTREG=XED_REG_ERROR -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {102, 4,0}, +/*h(4)=2 OUTREG=XED_REG_BND1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {4, 1,0}, +/*h(6)=3 OUTREG=XED_REG_BND3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {6, 3,0}, +/*h(3)=4 OUTREG=XED_REG_BND0 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {3, 0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (3*key % 5); +if(lu_table[hidx].key == key) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_BND_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[5] = { +/*h(5)=0 OUTREG=XED_REG_BND2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {5, 0,2}, +/*h(102)=1 OUTREG=XED_REG_ERROR -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {102, 0,4}, +/*h(4)=2 OUTREG=XED_REG_BND1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {4, 0,1}, +/*h(6)=3 OUTREG=XED_REG_BND3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {6, 0,3}, +/*h(3)=4 OUTREG=XED_REG_BND0 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {3, 0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (3*key % 5); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_A_GPR_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[96] = { +/*h(206)=0 OUTREG=XED_REG_ECX EASZ=2 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {206, 1,0}, +/*empty slot1 */ {0,0,0}, +/*h(149)=2 OUTREG=XED_REG_BX EASZ=1 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {149, 3,0}, +/*h(275)=3 OUTREG=XED_REG_RDX EASZ=3 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {275, 2,0}, +/*h(137)=4 OUTREG=XED_REG_AX EASZ=1 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {137, 0,0}, +/*h(218)=5 OUTREG=XED_REG_ESP EASZ=2 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {218, 4,0}, +/*empty slot1 */ {0,0,0}, +/*h(161)=7 OUTREG=XED_REG_SI EASZ=1 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {161, 6,0}, +/*h(287)=8 OUTREG=XED_REG_RBP EASZ=3 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {287, 5,0}, +/*empty slot1 */ {0,0,0}, +/*h(230)=10 OUTREG=XED_REG_EDI EASZ=2 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {230, 7,0}, +/*empty slot1 */ {0,0,0}, +/*h(173)=12 OUTREG=XED_REG_R9W EASZ=1 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {173, 1,1}, +/*h(299)=13 OUTREG=XED_REG_R8 EASZ=3 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {299, 0,1}, +/*empty slot1 */ {0,0,0}, +/*h(242)=15 OUTREG=XED_REG_R10D EASZ=2 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {242, 2,1}, +/*empty slot1 */ {0,0,0}, +/*h(185)=17 OUTREG=XED_REG_R12W EASZ=1 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {185, 4,1}, +/*h(311)=18 OUTREG=XED_REG_R11 EASZ=3 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {311, 3,1}, +/*empty slot1 */ {0,0,0}, +/*h(254)=20 OUTREG=XED_REG_R13D EASZ=2 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {254, 5,1}, +/*empty slot1 */ {0,0,0}, +/*h(197)=22 OUTREG=XED_REG_R15W EASZ=1 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {197, 7,1}, +/*h(323)=23 OUTREG=XED_REG_R14 EASZ=3 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {323, 6,1}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(141)=33 OUTREG=XED_REG_CX EASZ=1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {141, 1,0}, +/*h(267)=34 OUTREG=XED_REG_RAX EASZ=3 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {267, 0,0}, +/*empty slot1 */ {0,0,0}, +/*h(210)=36 OUTREG=XED_REG_EDX EASZ=2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {210, 2,0}, +/*empty slot1 */ {0,0,0}, +/*h(153)=38 OUTREG=XED_REG_SP EASZ=1 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {153, 4,0}, +/*h(279)=39 OUTREG=XED_REG_RBX EASZ=3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {279, 3,0}, +/*empty slot1 */ {0,0,0}, +/*h(222)=41 OUTREG=XED_REG_EBP EASZ=2 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {222, 5,0}, +/*empty slot1 */ {0,0,0}, +/*h(165)=43 OUTREG=XED_REG_DI EASZ=1 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {165, 7,0}, +/*h(291)=44 OUTREG=XED_REG_RSI EASZ=3 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {291, 6,0}, +/*empty slot1 */ {0,0,0}, +/*h(234)=46 OUTREG=XED_REG_R8D EASZ=2 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {234, 0,1}, +/*empty slot1 */ {0,0,0}, +/*h(177)=48 OUTREG=XED_REG_R10W EASZ=1 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {177, 2,1}, +/*h(303)=49 OUTREG=XED_REG_R9 EASZ=3 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {303, 1,1}, +/*empty slot1 */ {0,0,0}, +/*h(246)=51 OUTREG=XED_REG_R11D EASZ=2 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {246, 3,1}, +/*empty slot1 */ {0,0,0}, +/*h(189)=53 OUTREG=XED_REG_R13W EASZ=1 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {189, 5,1}, +/*h(315)=54 OUTREG=XED_REG_R12 EASZ=3 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {315, 4,1}, +/*empty slot1 */ {0,0,0}, +/*h(258)=56 OUTREG=XED_REG_R14D EASZ=2 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {258, 6,1}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(327)=59 OUTREG=XED_REG_R15 EASZ=3 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {327, 7,1}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(202)=67 OUTREG=XED_REG_EAX EASZ=2 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {202, 0,0}, +/*empty slot1 */ {0,0,0}, +/*h(145)=69 OUTREG=XED_REG_DX EASZ=1 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {145, 2,0}, +/*h(271)=70 OUTREG=XED_REG_RCX EASZ=3 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {271, 1,0}, +/*empty slot1 */ {0,0,0}, +/*h(214)=72 OUTREG=XED_REG_EBX EASZ=2 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {214, 3,0}, +/*empty slot1 */ {0,0,0}, +/*h(157)=74 OUTREG=XED_REG_BP EASZ=1 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {157, 5,0}, +/*h(283)=75 OUTREG=XED_REG_RSP EASZ=3 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {283, 4,0}, +/*empty slot1 */ {0,0,0}, +/*h(226)=77 OUTREG=XED_REG_ESI EASZ=2 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {226, 6,0}, +/*empty slot1 */ {0,0,0}, +/*h(169)=79 OUTREG=XED_REG_R8W EASZ=1 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {169, 0,1}, +/*h(295)=80 OUTREG=XED_REG_RDI EASZ=3 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {295, 7,0}, +/*empty slot1 */ {0,0,0}, +/*h(238)=82 OUTREG=XED_REG_R9D EASZ=2 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {238, 1,1}, +/*empty slot1 */ {0,0,0}, +/*h(181)=84 OUTREG=XED_REG_R11W EASZ=1 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {181, 3,1}, +/*h(307)=85 OUTREG=XED_REG_R10 EASZ=3 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {307, 2,1}, +/*empty slot1 */ {0,0,0}, +/*h(250)=87 OUTREG=XED_REG_R12D EASZ=2 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {250, 4,1}, +/*empty slot1 */ {0,0,0}, +/*h(193)=89 OUTREG=XED_REG_R14W EASZ=1 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {193, 6,1}, +/*h(319)=90 OUTREG=XED_REG_R13 EASZ=3 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {319, 5,1}, +/*empty slot1 */ {0,0,0}, +/*h(262)=92 OUTREG=XED_REG_R15D EASZ=2 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {262, 7,1}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = ((9*key % 103) % 96); +if(lu_table[hidx].key == key) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_A_GPR_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[96] = { +/*h(206)=0 OUTREG=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {206, 0,1}, +/*empty slot1 */ {0,0,0}, +/*h(149)=2 OUTREG=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {149, 0,3}, +/*h(275)=3 OUTREG=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {275, 0,2}, +/*h(137)=4 OUTREG=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {137, 0,0}, +/*h(218)=5 OUTREG=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {218, 0,4}, +/*empty slot1 */ {0,0,0}, +/*h(161)=7 OUTREG=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {161, 0,6}, +/*h(287)=8 OUTREG=XED_REG_RBP EASZ=3 -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {287, 0,5}, +/*empty slot1 */ {0,0,0}, +/*h(230)=10 OUTREG=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {230, 0,7}, +/*empty slot1 */ {0,0,0}, +/*h(173)=12 OUTREG=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {173, 1,1}, +/*h(299)=13 OUTREG=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {299, 1,0}, +/*empty slot1 */ {0,0,0}, +/*h(242)=15 OUTREG=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {242, 1,2}, +/*empty slot1 */ {0,0,0}, +/*h(185)=17 OUTREG=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {185, 1,4}, +/*h(311)=18 OUTREG=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {311, 1,3}, +/*empty slot1 */ {0,0,0}, +/*h(254)=20 OUTREG=XED_REG_R13D EASZ=2 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {254, 1,5}, +/*empty slot1 */ {0,0,0}, +/*h(197)=22 OUTREG=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {197, 1,7}, +/*h(323)=23 OUTREG=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {323, 1,6}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(141)=33 OUTREG=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {141, 0,1}, +/*h(267)=34 OUTREG=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {267, 0,0}, +/*empty slot1 */ {0,0,0}, +/*h(210)=36 OUTREG=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {210, 0,2}, +/*empty slot1 */ {0,0,0}, +/*h(153)=38 OUTREG=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {153, 0,4}, +/*h(279)=39 OUTREG=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {279, 0,3}, +/*empty slot1 */ {0,0,0}, +/*h(222)=41 OUTREG=XED_REG_EBP EASZ=2 -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {222, 0,5}, +/*empty slot1 */ {0,0,0}, +/*h(165)=43 OUTREG=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {165, 0,7}, +/*h(291)=44 OUTREG=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {291, 0,6}, +/*empty slot1 */ {0,0,0}, +/*h(234)=46 OUTREG=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {234, 1,0}, +/*empty slot1 */ {0,0,0}, +/*h(177)=48 OUTREG=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {177, 1,2}, +/*h(303)=49 OUTREG=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {303, 1,1}, +/*empty slot1 */ {0,0,0}, +/*h(246)=51 OUTREG=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {246, 1,3}, +/*empty slot1 */ {0,0,0}, +/*h(189)=53 OUTREG=XED_REG_R13W EASZ=1 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {189, 1,5}, +/*h(315)=54 OUTREG=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {315, 1,4}, +/*empty slot1 */ {0,0,0}, +/*h(258)=56 OUTREG=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {258, 1,6}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(327)=59 OUTREG=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {327, 1,7}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*h(202)=67 OUTREG=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {202, 0,0}, +/*empty slot1 */ {0,0,0}, +/*h(145)=69 OUTREG=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {145, 0,2}, +/*h(271)=70 OUTREG=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {271, 0,1}, +/*empty slot1 */ {0,0,0}, +/*h(214)=72 OUTREG=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {214, 0,3}, +/*empty slot1 */ {0,0,0}, +/*h(157)=74 OUTREG=XED_REG_BP EASZ=1 -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {157, 0,5}, +/*h(283)=75 OUTREG=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {283, 0,4}, +/*empty slot1 */ {0,0,0}, +/*h(226)=77 OUTREG=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {226, 0,6}, +/*empty slot1 */ {0,0,0}, +/*h(169)=79 OUTREG=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {169, 1,0}, +/*h(295)=80 OUTREG=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {295, 0,7}, +/*empty slot1 */ {0,0,0}, +/*h(238)=82 OUTREG=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {238, 1,1}, +/*empty slot1 */ {0,0,0}, +/*h(181)=84 OUTREG=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {181, 1,3}, +/*h(307)=85 OUTREG=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {307, 1,2}, +/*empty slot1 */ {0,0,0}, +/*h(250)=87 OUTREG=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {250, 1,4}, +/*empty slot1 */ {0,0,0}, +/*h(193)=89 OUTREG=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {193, 1,6}, +/*h(319)=90 OUTREG=XED_REG_R13 EASZ=3 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {319, 1,5}, +/*empty slot1 */ {0,0,0}, +/*h(262)=92 OUTREG=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {262, 1,7}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0}, +/*empty slot1 */ {0,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EASZ_OUTREG(xes); +hidx = ((9*key % 103) % 96); +if(lu_table[hidx].key == key) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_SE(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_SE32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_SE32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_SE64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_SE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t esrc;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB ESRC=0 value=0x0*/ {0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB ESRC=1 value=0x1*/ {1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB ESRC=2 value=0x2*/ {2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB ESRC=3 value=0x3*/ {3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB ESRC=4 value=0x4*/ {4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB ESRC=5 value=0x5*/ {5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB ESRC=6 value=0x6*/ {6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB ESRC=7 value=0x7*/ {7}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB ESRC=8 value=0x8*/ {8}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB ESRC=9 value=0x9*/ {9}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB ESRC=10 value=0xa*/ {10}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB ESRC=11 value=0xb*/ {11}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB ESRC=12 value=0xc*/ {12}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB ESRC=13 value=0xd*/ {13}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB ESRC=14 value=0xe*/ {14}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB ESRC=15 value=0xf*/ {15} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 15) { + xed3_operand_set_esrc(xes,lu_table[hidx].esrc); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_SE32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t esrc;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB ESRC=0 value=0x0*/ {0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB ESRC=1 value=0x1*/ {1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB ESRC=2 value=0x2*/ {2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB ESRC=3 value=0x3*/ {3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB ESRC=4 value=0x4*/ {4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB ESRC=5 value=0x5*/ {5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB ESRC=6 value=0x6*/ {6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB ESRC=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_esrc(xes,lu_table[hidx].esrc); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_SE(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_SE32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_SE32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_SE64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_SE64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t esrc;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB ESRC=0 value=0x0*/ {0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB ESRC=1 value=0x1*/ {1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB ESRC=2 value=0x2*/ {2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB ESRC=3 value=0x3*/ {3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB ESRC=4 value=0x4*/ {4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB ESRC=5 value=0x5*/ {5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB ESRC=6 value=0x6*/ {6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB ESRC=7 value=0x7*/ {7}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB ESRC=8 value=0x8*/ {8}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB ESRC=9 value=0x9*/ {9}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB ESRC=10 value=0xa*/ {10}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB ESRC=11 value=0xb*/ {11}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB ESRC=12 value=0xc*/ {12}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB ESRC=13 value=0xd*/ {13}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB ESRC=14 value=0xe*/ {14}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB ESRC=15 value=0xf*/ {15} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 15) { + xed3_operand_set_esrc(xes,lu_table[hidx].esrc); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_SE32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t esrc;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB ESRC=0 value=0x0*/ {0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB ESRC=1 value=0x1*/ {1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB ESRC=2 value=0x2*/ {2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB ESRC=3 value=0x3*/ {3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB ESRC=4 value=0x4*/ {4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB ESRC=5 value=0x5*/ {5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB ESRC=6 value=0x6*/ {6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB ESRC=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_esrc(xes,lu_table[hidx].esrc); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_N_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_N_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_N_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_N_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_N_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 15) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_N_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_N_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_N_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_N_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_N_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 15) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_R_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_R_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_R_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_R_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB REG=0 value=0x0*/ {0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB REG=1 value=0x1*/ {1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB REG=2 value=0x2*/ {2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB REG=3 value=0x3*/ {3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB REG=4 value=0x4*/ {4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB REG=5 value=0x5*/ {5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB REG=6 value=0x6*/ {6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_R_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_B_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_B_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_B_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_B_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB RM=0 value=0x0*/ {0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB RM=1 value=0x1*/ {1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB RM=2 value=0x2*/ {2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB RM=3 value=0x3*/ {3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB RM=4 value=0x4*/ {4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB RM=5 value=0x5*/ {5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB RM=6 value=0x6*/ {6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_B_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPRy_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_VGPR32_R}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_VGPR32_R}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_VGPR64_R} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPRy_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_VGPR32_B}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_VGPR32_B}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_VGPR64_B} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPRy_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(1)=0 EOSZ=1 -> ntluf*/ {xed_encode_ntluf_VGPR32_N}, +/*h(2)=1 EOSZ=2 -> ntluf*/ {xed_encode_ntluf_VGPR32_N}, +/*h(3)=2 EOSZ=3 -> ntluf*/ {xed_encode_ntluf_VGPR64_N} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_EOSZ(xes); +hidx = key - 1; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_VGPR32_N_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_VGPR32_N_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_VGPR32_N_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_VGPR32_B_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_VGPR32_B_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_VGPR32_B_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_VGPR32_R_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_VGPR32_R_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_VGPR32_R_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_N_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_N_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1}, +/*h(58)=8 OUTREG=XED_REG_R8D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0}, +/*h(60)=10 OUTREG=XED_REG_R10D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0}, +/*h(61)=11 OUTREG=XED_REG_R11D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0}, +/*h(62)=12 OUTREG=XED_REG_R12D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0}, +/*h(63)=13 OUTREG=XED_REG_R13D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0}, +/*h(64)=14 OUTREG=XED_REG_R14D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0}, +/*h(65)=15 OUTREG=XED_REG_R15D -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR64_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 OUTREG=XED_REG_RAX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1}, +/*h(67)=1 OUTREG=XED_REG_RCX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1}, +/*h(68)=2 OUTREG=XED_REG_RDX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1}, +/*h(69)=3 OUTREG=XED_REG_RBX -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1}, +/*h(70)=4 OUTREG=XED_REG_RSP -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1}, +/*h(71)=5 OUTREG=XED_REG_RBP -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1}, +/*h(73)=7 OUTREG=XED_REG_RDI -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1}, +/*h(74)=8 OUTREG=XED_REG_R8 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0}, +/*h(75)=9 OUTREG=XED_REG_R9 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0}, +/*h(76)=10 OUTREG=XED_REG_R10 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0}, +/*h(77)=11 OUTREG=XED_REG_R11 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0}, +/*h(78)=12 OUTREG=XED_REG_R12 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0}, +/*h(79)=13 OUTREG=XED_REG_R13 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0}, +/*h(81)=15 OUTREG=XED_REG_R15 -> FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_R_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB REG=0 value=0x0*/ {0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB REG=1 value=0x1*/ {1}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REG=2 value=0x2*/ {2}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB REG=3 value=0x3*/ {3}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB REG=4 value=0x4*/ {4}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB REG=5 value=0x5*/ {5}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB REG=6 value=0x6*/ {6}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_R_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(58)=8 OUTREG=XED_REG_R8D -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(60)=10 OUTREG=XED_REG_R10D -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(61)=11 OUTREG=XED_REG_R11D -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(62)=12 OUTREG=XED_REG_R12D -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(63)=13 OUTREG=XED_REG_R13D -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(64)=14 OUTREG=XED_REG_R14D -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(65)=15 OUTREG=XED_REG_R15D -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR64_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 OUTREG=XED_REG_RAX -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(67)=1 OUTREG=XED_REG_RCX -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(68)=2 OUTREG=XED_REG_RDX -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(69)=3 OUTREG=XED_REG_RBX -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(70)=4 OUTREG=XED_REG_RSP -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(71)=5 OUTREG=XED_REG_RBP -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(73)=7 OUTREG=XED_REG_RDI -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0}, +/*h(74)=8 OUTREG=XED_REG_R8 -> FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1}, +/*h(75)=9 OUTREG=XED_REG_R9 -> FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1}, +/*h(76)=10 OUTREG=XED_REG_R10 -> FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1}, +/*h(77)=11 OUTREG=XED_REG_R11 -> FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1}, +/*h(78)=12 OUTREG=XED_REG_R12 -> FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1}, +/*h(79)=13 OUTREG=XED_REG_R13 -> FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1}, +/*h(81)=15 OUTREG=XED_REG_R15 -> FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_B_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB RM=0 value=0x0*/ {0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB RM=1 value=0x1*/ {1}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB RM=2 value=0x2*/ {2}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB RM=3 value=0x3*/ {3}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB RM=4 value=0x4*/ {4}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB RM=5 value=0x5*/ {5}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB RM=6 value=0x6*/ {6}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR32_B_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(50)=0 OUTREG=XED_REG_EAX -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(51)=1 OUTREG=XED_REG_ECX -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(52)=2 OUTREG=XED_REG_EDX -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(53)=3 OUTREG=XED_REG_EBX -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(54)=4 OUTREG=XED_REG_ESP -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(55)=5 OUTREG=XED_REG_EBP -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(56)=6 OUTREG=XED_REG_ESI -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(57)=7 OUTREG=XED_REG_EDI -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(58)=8 OUTREG=XED_REG_R8D -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(59)=9 OUTREG=XED_REG_R9D -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(60)=10 OUTREG=XED_REG_R10D -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(61)=11 OUTREG=XED_REG_R11D -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(62)=12 OUTREG=XED_REG_R12D -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(63)=13 OUTREG=XED_REG_R13D -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(64)=14 OUTREG=XED_REG_R14D -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(65)=15 OUTREG=XED_REG_R15D -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 50; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_VGPR64_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[16] = { +/*h(66)=0 OUTREG=XED_REG_RAX -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(67)=1 OUTREG=XED_REG_RCX -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(68)=2 OUTREG=XED_REG_RDX -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(69)=3 OUTREG=XED_REG_RBX -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(70)=4 OUTREG=XED_REG_RSP -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(71)=5 OUTREG=XED_REG_RBP -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(72)=6 OUTREG=XED_REG_RSI -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(73)=7 OUTREG=XED_REG_RDI -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7}, +/*h(74)=8 OUTREG=XED_REG_R8 -> FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0}, +/*h(75)=9 OUTREG=XED_REG_R9 -> FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1}, +/*h(76)=10 OUTREG=XED_REG_R10 -> FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,2}, +/*h(77)=11 OUTREG=XED_REG_R11 -> FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,3}, +/*h(78)=12 OUTREG=XED_REG_R12 -> FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,4}, +/*h(79)=13 OUTREG=XED_REG_R13 -> FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,5}, +/*h(80)=14 OUTREG=XED_REG_R14 -> FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,6}, +/*h(81)=15 OUTREG=XED_REG_R15 -> FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 66; +if(hidx <= 15) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASK1(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t mask;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(106)=0 OUTREG=XED_REG_K0 -> FB MASK=0 value=0x0*/ {0}, +/*h(107)=1 OUTREG=XED_REG_K1 -> FB MASK=1 value=0x1*/ {1}, +/*h(108)=2 OUTREG=XED_REG_K2 -> FB MASK=2 value=0x2*/ {2}, +/*h(109)=3 OUTREG=XED_REG_K3 -> FB MASK=3 value=0x3*/ {3}, +/*h(110)=4 OUTREG=XED_REG_K4 -> FB MASK=4 value=0x4*/ {4}, +/*h(111)=5 OUTREG=XED_REG_K5 -> FB MASK=5 value=0x5*/ {5}, +/*h(112)=6 OUTREG=XED_REG_K6 -> FB MASK=6 value=0x6*/ {6}, +/*h(113)=7 OUTREG=XED_REG_K7 -> FB MASK=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 106; +if(hidx <= 7) { + xed3_operand_set_mask(xes,lu_table[hidx].mask); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASKNOT0(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct {xed_uint32_t key; xed_int8_t mask;} lu_entry_t; +static const lu_entry_t lu_table[10] = { +/*h(102)=0 OUTREG=XED_REG_ERROR -> FB MASK=0 value=0x0*/ {102, 0}, +/*h(107)=1 OUTREG=XED_REG_K1 -> FB MASK=1 value=0x1*/ {107, 1}, +/*h(112)=2 OUTREG=XED_REG_K6 -> FB MASK=6 value=0x6*/ {112, 6}, +/*h(109)=3 OUTREG=XED_REG_K3 -> FB MASK=3 value=0x3*/ {109, 3}, +/*empty slot1 */ {0,0}, +/*empty slot1 */ {0,0}, +/*h(111)=6 OUTREG=XED_REG_K5 -> FB MASK=5 value=0x5*/ {111, 5}, +/*h(108)=7 OUTREG=XED_REG_K2 -> FB MASK=2 value=0x2*/ {108, 2}, +/*h(113)=8 OUTREG=XED_REG_K7 -> FB MASK=7 value=0x7*/ {113, 7}, +/*h(110)=9 OUTREG=XED_REG_K4 -> FB MASK=4 value=0x4*/ {110, 4} +}; +xed_union64_t t, u; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = (t.u64 = 2654435769 * key, u.u64 = t.s.lo32 * 10ULL, u.s.hi32); +if(lu_table[hidx].key == key) { + xed3_operand_set_mask(xes,lu_table[hidx].mask); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASK_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr ;xed_int8_t rexrr;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(106)=0 OUTREG=XED_REG_K0 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,0}, +/*h(107)=1 OUTREG=XED_REG_K1 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,0}, +/*h(108)=2 OUTREG=XED_REG_K2 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,0}, +/*h(109)=3 OUTREG=XED_REG_K3 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,0}, +/*h(110)=4 OUTREG=XED_REG_K4 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,0}, +/*h(111)=5 OUTREG=XED_REG_K5 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,0}, +/*h(112)=6 OUTREG=XED_REG_K6 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,0}, +/*h(113)=7 OUTREG=XED_REG_K7 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 106; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + xed3_operand_set_rexrr(xes,lu_table[hidx].rexrr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASK_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(106)=0 OUTREG=XED_REG_K0 -> FB RM=0 value=0x0*/ {0}, +/*h(107)=1 OUTREG=XED_REG_K1 -> FB RM=1 value=0x1*/ {1}, +/*h(108)=2 OUTREG=XED_REG_K2 -> FB RM=2 value=0x2*/ {2}, +/*h(109)=3 OUTREG=XED_REG_K3 -> FB RM=3 value=0x3*/ {3}, +/*h(110)=4 OUTREG=XED_REG_K4 -> FB RM=4 value=0x4*/ {4}, +/*h(111)=5 OUTREG=XED_REG_K5 -> FB RM=5 value=0x5*/ {5}, +/*h(112)=6 OUTREG=XED_REG_K6 -> FB RM=6 value=0x6*/ {6}, +/*h(113)=7 OUTREG=XED_REG_K7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 106; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASK_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_MASK_N32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_MASK_N32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_MASK_N64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASK_N64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(106)=0 OUTREG=XED_REG_K0 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1}, +/*h(107)=1 OUTREG=XED_REG_K1 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1}, +/*h(108)=2 OUTREG=XED_REG_K2 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1}, +/*h(109)=3 OUTREG=XED_REG_K3 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1}, +/*h(110)=4 OUTREG=XED_REG_K4 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1}, +/*h(111)=5 OUTREG=XED_REG_K5 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1}, +/*h(112)=6 OUTREG=XED_REG_K6 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1}, +/*h(113)=7 OUTREG=XED_REG_K7 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 106; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_MASK_N32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(106)=0 OUTREG=XED_REG_K0 -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(107)=1 OUTREG=XED_REG_K1 -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(108)=2 OUTREG=XED_REG_K2 -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(109)=3 OUTREG=XED_REG_K3 -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(110)=4 OUTREG=XED_REG_K4 -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(111)=5 OUTREG=XED_REG_K5 -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(112)=6 OUTREG=XED_REG_K6 -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(113)=7 OUTREG=XED_REG_K7 -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 106; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_R3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_R3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_R3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_R3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_R3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB REG=0 value=0x0*/ {0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB REG=1 value=0x1*/ {1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB REG=2 value=0x2*/ {2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB REG=3 value=0x3*/ {3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB REG=4 value=0x4*/ {4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB REG=5 value=0x5*/ {5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB REG=6 value=0x6*/ {6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_R3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr ;xed_int8_t rexrr;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,0}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,0}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,0}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,0}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,0}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,0}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,0}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1,0}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1,0}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1,0}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1,0}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1,0}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1,0}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1,0}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1,0}, +/*h(204)=16 OUTREG=XED_REG_XMM16 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,1}, +/*h(205)=17 OUTREG=XED_REG_XMM17 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,1}, +/*h(206)=18 OUTREG=XED_REG_XMM18 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,1}, +/*h(207)=19 OUTREG=XED_REG_XMM19 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,1}, +/*h(208)=20 OUTREG=XED_REG_XMM20 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,1}, +/*h(209)=21 OUTREG=XED_REG_XMM21 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,1}, +/*h(210)=22 OUTREG=XED_REG_XMM22 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,1}, +/*h(211)=23 OUTREG=XED_REG_XMM23 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,1}, +/*h(212)=24 OUTREG=XED_REG_XMM24 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1,1}, +/*h(213)=25 OUTREG=XED_REG_XMM25 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1,1}, +/*h(214)=26 OUTREG=XED_REG_XMM26 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1,1}, +/*h(215)=27 OUTREG=XED_REG_XMM27 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1,1}, +/*h(216)=28 OUTREG=XED_REG_XMM28 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1,1}, +/*h(217)=29 OUTREG=XED_REG_XMM29 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1,1}, +/*h(218)=30 OUTREG=XED_REG_XMM30 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1,1}, +/*h(219)=31 OUTREG=XED_REG_XMM31 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 31) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + xed3_operand_set_rexrr(xes,lu_table[hidx].rexrr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_R3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_R3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_R3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_R3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_R3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB REG=0 value=0x0*/ {0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB REG=1 value=0x1*/ {1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB REG=2 value=0x2*/ {2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB REG=3 value=0x3*/ {3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB REG=4 value=0x4*/ {4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB REG=5 value=0x5*/ {5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB REG=6 value=0x6*/ {6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_R3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr ;xed_int8_t rexrr;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,0}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,0}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,0}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,0}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,0}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,0}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,0}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1,0}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1,0}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1,0}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1,0}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1,0}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1,0}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1,0}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1,0}, +/*h(236)=16 OUTREG=XED_REG_YMM16 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,1}, +/*h(237)=17 OUTREG=XED_REG_YMM17 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,1}, +/*h(238)=18 OUTREG=XED_REG_YMM18 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,1}, +/*h(239)=19 OUTREG=XED_REG_YMM19 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,1}, +/*h(240)=20 OUTREG=XED_REG_YMM20 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,1}, +/*h(241)=21 OUTREG=XED_REG_YMM21 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,1}, +/*h(242)=22 OUTREG=XED_REG_YMM22 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,1}, +/*h(243)=23 OUTREG=XED_REG_YMM23 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,1}, +/*h(244)=24 OUTREG=XED_REG_YMM24 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1,1}, +/*h(245)=25 OUTREG=XED_REG_YMM25 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1,1}, +/*h(246)=26 OUTREG=XED_REG_YMM26 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1,1}, +/*h(247)=27 OUTREG=XED_REG_YMM27 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1,1}, +/*h(248)=28 OUTREG=XED_REG_YMM28 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1,1}, +/*h(249)=29 OUTREG=XED_REG_YMM29 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1,1}, +/*h(250)=30 OUTREG=XED_REG_YMM30 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1,1}, +/*h(251)=31 OUTREG=XED_REG_YMM31 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 31) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + xed3_operand_set_rexrr(xes,lu_table[hidx].rexrr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_R3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_ZMM_R3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_ZMM_R3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_ZMM_R3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_R3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(252)=0 OUTREG=XED_REG_ZMM0 -> FB REG=0 value=0x0*/ {0}, +/*h(253)=1 OUTREG=XED_REG_ZMM1 -> FB REG=1 value=0x1*/ {1}, +/*h(254)=2 OUTREG=XED_REG_ZMM2 -> FB REG=2 value=0x2*/ {2}, +/*h(255)=3 OUTREG=XED_REG_ZMM3 -> FB REG=3 value=0x3*/ {3}, +/*h(256)=4 OUTREG=XED_REG_ZMM4 -> FB REG=4 value=0x4*/ {4}, +/*h(257)=5 OUTREG=XED_REG_ZMM5 -> FB REG=5 value=0x5*/ {5}, +/*h(258)=6 OUTREG=XED_REG_ZMM6 -> FB REG=6 value=0x6*/ {6}, +/*h(259)=7 OUTREG=XED_REG_ZMM7 -> FB REG=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 252; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_R3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr ;xed_int8_t rexrr;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(252)=0 OUTREG=XED_REG_ZMM0 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,0}, +/*h(253)=1 OUTREG=XED_REG_ZMM1 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,0}, +/*h(254)=2 OUTREG=XED_REG_ZMM2 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,0}, +/*h(255)=3 OUTREG=XED_REG_ZMM3 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,0}, +/*h(256)=4 OUTREG=XED_REG_ZMM4 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,0}, +/*h(257)=5 OUTREG=XED_REG_ZMM5 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,0}, +/*h(258)=6 OUTREG=XED_REG_ZMM6 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,0}, +/*h(259)=7 OUTREG=XED_REG_ZMM7 -> FB REXRR=0 value=0x0 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,0}, +/*h(260)=8 OUTREG=XED_REG_ZMM8 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1,0}, +/*h(261)=9 OUTREG=XED_REG_ZMM9 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1,0}, +/*h(262)=10 OUTREG=XED_REG_ZMM10 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1,0}, +/*h(263)=11 OUTREG=XED_REG_ZMM11 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1,0}, +/*h(264)=12 OUTREG=XED_REG_ZMM12 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1,0}, +/*h(265)=13 OUTREG=XED_REG_ZMM13 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1,0}, +/*h(266)=14 OUTREG=XED_REG_ZMM14 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1,0}, +/*h(267)=15 OUTREG=XED_REG_ZMM15 -> FB REXRR=0 value=0x0 FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1,0}, +/*h(268)=16 OUTREG=XED_REG_ZMM16 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0,1}, +/*h(269)=17 OUTREG=XED_REG_ZMM17 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0,1}, +/*h(270)=18 OUTREG=XED_REG_ZMM18 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0,1}, +/*h(271)=19 OUTREG=XED_REG_ZMM19 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0,1}, +/*h(272)=20 OUTREG=XED_REG_ZMM20 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0,1}, +/*h(273)=21 OUTREG=XED_REG_ZMM21 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0,1}, +/*h(274)=22 OUTREG=XED_REG_ZMM22 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0,1}, +/*h(275)=23 OUTREG=XED_REG_ZMM23 -> FB REXRR=1 value=0x1 FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0,1}, +/*h(276)=24 OUTREG=XED_REG_ZMM24 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=0 value=0x0*/ {0,1,1}, +/*h(277)=25 OUTREG=XED_REG_ZMM25 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=1 value=0x1*/ {1,1,1}, +/*h(278)=26 OUTREG=XED_REG_ZMM26 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=2 value=0x2*/ {2,1,1}, +/*h(279)=27 OUTREG=XED_REG_ZMM27 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=3 value=0x3*/ {3,1,1}, +/*h(280)=28 OUTREG=XED_REG_ZMM28 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=4 value=0x4*/ {4,1,1}, +/*h(281)=29 OUTREG=XED_REG_ZMM29 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=5 value=0x5*/ {5,1,1}, +/*h(282)=30 OUTREG=XED_REG_ZMM30 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=6 value=0x6*/ {6,1,1}, +/*h(283)=31 OUTREG=XED_REG_ZMM31 -> FB REXRR=1 value=0x1 FB REXR=1 value=0x1 FB REG=7 value=0x7*/ {7,1,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 252; +if(hidx <= 31) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + xed3_operand_set_rexrr(xes,lu_table[hidx].rexrr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_B3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_B3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_B3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_B3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_B3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB RM=0 value=0x0*/ {0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB RM=1 value=0x1*/ {1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB RM=2 value=0x2*/ {2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB RM=3 value=0x3*/ {3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB RM=4 value=0x4*/ {4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB RM=5 value=0x5*/ {5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB RM=6 value=0x6*/ {6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_B3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rexx ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0,0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,0,1}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,0,2}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,0,3}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,0,4}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,0,5}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,0,6}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,0,7}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0,0}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,0,1}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,0,2}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,0,3}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,0,4}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,0,5}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,0,6}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,0,7}, +/*h(204)=16 OUTREG=XED_REG_XMM16 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,1,0}, +/*h(205)=17 OUTREG=XED_REG_XMM17 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1,1}, +/*h(206)=18 OUTREG=XED_REG_XMM18 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,1,2}, +/*h(207)=19 OUTREG=XED_REG_XMM19 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,1,3}, +/*h(208)=20 OUTREG=XED_REG_XMM20 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,1,4}, +/*h(209)=21 OUTREG=XED_REG_XMM21 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,1,5}, +/*h(210)=22 OUTREG=XED_REG_XMM22 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,1,6}, +/*h(211)=23 OUTREG=XED_REG_XMM23 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,1,7}, +/*h(212)=24 OUTREG=XED_REG_XMM24 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,1,0}, +/*h(213)=25 OUTREG=XED_REG_XMM25 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1,1}, +/*h(214)=26 OUTREG=XED_REG_XMM26 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,1,2}, +/*h(215)=27 OUTREG=XED_REG_XMM27 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,1,3}, +/*h(216)=28 OUTREG=XED_REG_XMM28 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,1,4}, +/*h(217)=29 OUTREG=XED_REG_XMM29 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,1,5}, +/*h(218)=30 OUTREG=XED_REG_XMM30 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,1,6}, +/*h(219)=31 OUTREG=XED_REG_XMM31 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 31) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_B3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_B3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_B3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_B3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_B3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB RM=0 value=0x0*/ {0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB RM=1 value=0x1*/ {1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB RM=2 value=0x2*/ {2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB RM=3 value=0x3*/ {3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB RM=4 value=0x4*/ {4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB RM=5 value=0x5*/ {5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB RM=6 value=0x6*/ {6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_B3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rexx ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0,0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,0,1}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,0,2}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,0,3}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,0,4}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,0,5}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,0,6}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,0,7}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0,0}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,0,1}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,0,2}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,0,3}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,0,4}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,0,5}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,0,6}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,0,7}, +/*h(236)=16 OUTREG=XED_REG_YMM16 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,1,0}, +/*h(237)=17 OUTREG=XED_REG_YMM17 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1,1}, +/*h(238)=18 OUTREG=XED_REG_YMM18 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,1,2}, +/*h(239)=19 OUTREG=XED_REG_YMM19 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,1,3}, +/*h(240)=20 OUTREG=XED_REG_YMM20 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,1,4}, +/*h(241)=21 OUTREG=XED_REG_YMM21 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,1,5}, +/*h(242)=22 OUTREG=XED_REG_YMM22 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,1,6}, +/*h(243)=23 OUTREG=XED_REG_YMM23 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,1,7}, +/*h(244)=24 OUTREG=XED_REG_YMM24 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,1,0}, +/*h(245)=25 OUTREG=XED_REG_YMM25 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1,1}, +/*h(246)=26 OUTREG=XED_REG_YMM26 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,1,2}, +/*h(247)=27 OUTREG=XED_REG_YMM27 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,1,3}, +/*h(248)=28 OUTREG=XED_REG_YMM28 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,1,4}, +/*h(249)=29 OUTREG=XED_REG_YMM29 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,1,5}, +/*h(250)=30 OUTREG=XED_REG_YMM30 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,1,6}, +/*h(251)=31 OUTREG=XED_REG_YMM31 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 31) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_B3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_ZMM_B3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_ZMM_B3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_ZMM_B3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_B3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(252)=0 OUTREG=XED_REG_ZMM0 -> FB RM=0 value=0x0*/ {0}, +/*h(253)=1 OUTREG=XED_REG_ZMM1 -> FB RM=1 value=0x1*/ {1}, +/*h(254)=2 OUTREG=XED_REG_ZMM2 -> FB RM=2 value=0x2*/ {2}, +/*h(255)=3 OUTREG=XED_REG_ZMM3 -> FB RM=3 value=0x3*/ {3}, +/*h(256)=4 OUTREG=XED_REG_ZMM4 -> FB RM=4 value=0x4*/ {4}, +/*h(257)=5 OUTREG=XED_REG_ZMM5 -> FB RM=5 value=0x5*/ {5}, +/*h(258)=6 OUTREG=XED_REG_ZMM6 -> FB RM=6 value=0x6*/ {6}, +/*h(259)=7 OUTREG=XED_REG_ZMM7 -> FB RM=7 value=0x7*/ {7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 252; +if(hidx <= 7) { + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_B3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rexx ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(252)=0 OUTREG=XED_REG_ZMM0 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0,0}, +/*h(253)=1 OUTREG=XED_REG_ZMM1 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,0,1}, +/*h(254)=2 OUTREG=XED_REG_ZMM2 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,0,2}, +/*h(255)=3 OUTREG=XED_REG_ZMM3 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,0,3}, +/*h(256)=4 OUTREG=XED_REG_ZMM4 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,0,4}, +/*h(257)=5 OUTREG=XED_REG_ZMM5 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,0,5}, +/*h(258)=6 OUTREG=XED_REG_ZMM6 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,0,6}, +/*h(259)=7 OUTREG=XED_REG_ZMM7 -> FB REXX=0 value=0x0 FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,0,7}, +/*h(260)=8 OUTREG=XED_REG_ZMM8 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,0,0}, +/*h(261)=9 OUTREG=XED_REG_ZMM9 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,0,1}, +/*h(262)=10 OUTREG=XED_REG_ZMM10 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,0,2}, +/*h(263)=11 OUTREG=XED_REG_ZMM11 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,0,3}, +/*h(264)=12 OUTREG=XED_REG_ZMM12 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,0,4}, +/*h(265)=13 OUTREG=XED_REG_ZMM13 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,0,5}, +/*h(266)=14 OUTREG=XED_REG_ZMM14 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,0,6}, +/*h(267)=15 OUTREG=XED_REG_ZMM15 -> FB REXX=0 value=0x0 FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,0,7}, +/*h(268)=16 OUTREG=XED_REG_ZMM16 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,1,0}, +/*h(269)=17 OUTREG=XED_REG_ZMM17 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1,1}, +/*h(270)=18 OUTREG=XED_REG_ZMM18 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,1,2}, +/*h(271)=19 OUTREG=XED_REG_ZMM19 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,1,3}, +/*h(272)=20 OUTREG=XED_REG_ZMM20 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,1,4}, +/*h(273)=21 OUTREG=XED_REG_ZMM21 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,1,5}, +/*h(274)=22 OUTREG=XED_REG_ZMM22 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,1,6}, +/*h(275)=23 OUTREG=XED_REG_ZMM23 -> FB REXX=1 value=0x1 FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,1,7}, +/*h(276)=24 OUTREG=XED_REG_ZMM24 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=0 value=0x0*/ {1,1,0}, +/*h(277)=25 OUTREG=XED_REG_ZMM25 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=1 value=0x1*/ {1,1,1}, +/*h(278)=26 OUTREG=XED_REG_ZMM26 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=2 value=0x2*/ {1,1,2}, +/*h(279)=27 OUTREG=XED_REG_ZMM27 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=3 value=0x3*/ {1,1,3}, +/*h(280)=28 OUTREG=XED_REG_ZMM28 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=4 value=0x4*/ {1,1,4}, +/*h(281)=29 OUTREG=XED_REG_ZMM29 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=5 value=0x5*/ {1,1,5}, +/*h(282)=30 OUTREG=XED_REG_ZMM30 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=6 value=0x6*/ {1,1,6}, +/*h(283)=31 OUTREG=XED_REG_ZMM31 -> FB REXX=1 value=0x1 FB REXB=1 value=0x1 FB RM=7 value=0x7*/ {1,1,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 252; +if(hidx <= 31) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rexx(xes,lu_table[hidx].rexx); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_N3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_XMM_N3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_XMM_N3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_XMM_N3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_N3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_XMM_N3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3 ;xed_int8_t vexdest4;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(188)=0 OUTREG=XED_REG_XMM0 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1,0}, +/*h(189)=1 OUTREG=XED_REG_XMM1 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1,0}, +/*h(190)=2 OUTREG=XED_REG_XMM2 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1,0}, +/*h(191)=3 OUTREG=XED_REG_XMM3 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1,0}, +/*h(192)=4 OUTREG=XED_REG_XMM4 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1,0}, +/*h(193)=5 OUTREG=XED_REG_XMM5 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1,0}, +/*h(194)=6 OUTREG=XED_REG_XMM6 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1,0}, +/*h(195)=7 OUTREG=XED_REG_XMM7 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1,0}, +/*h(196)=8 OUTREG=XED_REG_XMM8 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0,0}, +/*h(197)=9 OUTREG=XED_REG_XMM9 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0,0}, +/*h(198)=10 OUTREG=XED_REG_XMM10 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0,0}, +/*h(199)=11 OUTREG=XED_REG_XMM11 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0,0}, +/*h(200)=12 OUTREG=XED_REG_XMM12 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0,0}, +/*h(201)=13 OUTREG=XED_REG_XMM13 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0,0}, +/*h(202)=14 OUTREG=XED_REG_XMM14 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0,0}, +/*h(203)=15 OUTREG=XED_REG_XMM15 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0,0}, +/*h(204)=16 OUTREG=XED_REG_XMM16 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1,1}, +/*h(205)=17 OUTREG=XED_REG_XMM17 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1,1}, +/*h(206)=18 OUTREG=XED_REG_XMM18 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1,1}, +/*h(207)=19 OUTREG=XED_REG_XMM19 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1,1}, +/*h(208)=20 OUTREG=XED_REG_XMM20 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1,1}, +/*h(209)=21 OUTREG=XED_REG_XMM21 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1,1}, +/*h(210)=22 OUTREG=XED_REG_XMM22 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1,1}, +/*h(211)=23 OUTREG=XED_REG_XMM23 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1,1}, +/*h(212)=24 OUTREG=XED_REG_XMM24 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0,1}, +/*h(213)=25 OUTREG=XED_REG_XMM25 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0,1}, +/*h(214)=26 OUTREG=XED_REG_XMM26 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0,1}, +/*h(215)=27 OUTREG=XED_REG_XMM27 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0,1}, +/*h(216)=28 OUTREG=XED_REG_XMM28 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0,1}, +/*h(217)=29 OUTREG=XED_REG_XMM29 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0,1}, +/*h(218)=30 OUTREG=XED_REG_XMM30 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0,1}, +/*h(219)=31 OUTREG=XED_REG_XMM31 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 188; +if(hidx <= 31) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + xed3_operand_set_vexdest4(xes,lu_table[hidx].vexdest4); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_N3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_YMM_N3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_YMM_N3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_YMM_N3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_N3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_YMM_N3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3 ;xed_int8_t vexdest4;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(220)=0 OUTREG=XED_REG_YMM0 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1,0}, +/*h(221)=1 OUTREG=XED_REG_YMM1 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1,0}, +/*h(222)=2 OUTREG=XED_REG_YMM2 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1,0}, +/*h(223)=3 OUTREG=XED_REG_YMM3 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1,0}, +/*h(224)=4 OUTREG=XED_REG_YMM4 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1,0}, +/*h(225)=5 OUTREG=XED_REG_YMM5 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1,0}, +/*h(226)=6 OUTREG=XED_REG_YMM6 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1,0}, +/*h(227)=7 OUTREG=XED_REG_YMM7 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1,0}, +/*h(228)=8 OUTREG=XED_REG_YMM8 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0,0}, +/*h(229)=9 OUTREG=XED_REG_YMM9 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0,0}, +/*h(230)=10 OUTREG=XED_REG_YMM10 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0,0}, +/*h(231)=11 OUTREG=XED_REG_YMM11 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0,0}, +/*h(232)=12 OUTREG=XED_REG_YMM12 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0,0}, +/*h(233)=13 OUTREG=XED_REG_YMM13 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0,0}, +/*h(234)=14 OUTREG=XED_REG_YMM14 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0,0}, +/*h(235)=15 OUTREG=XED_REG_YMM15 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0,0}, +/*h(236)=16 OUTREG=XED_REG_YMM16 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1,1}, +/*h(237)=17 OUTREG=XED_REG_YMM17 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1,1}, +/*h(238)=18 OUTREG=XED_REG_YMM18 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1,1}, +/*h(239)=19 OUTREG=XED_REG_YMM19 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1,1}, +/*h(240)=20 OUTREG=XED_REG_YMM20 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1,1}, +/*h(241)=21 OUTREG=XED_REG_YMM21 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1,1}, +/*h(242)=22 OUTREG=XED_REG_YMM22 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1,1}, +/*h(243)=23 OUTREG=XED_REG_YMM23 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1,1}, +/*h(244)=24 OUTREG=XED_REG_YMM24 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0,1}, +/*h(245)=25 OUTREG=XED_REG_YMM25 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0,1}, +/*h(246)=26 OUTREG=XED_REG_YMM26 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0,1}, +/*h(247)=27 OUTREG=XED_REG_YMM27 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0,1}, +/*h(248)=28 OUTREG=XED_REG_YMM28 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0,1}, +/*h(249)=29 OUTREG=XED_REG_YMM29 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0,1}, +/*h(250)=30 OUTREG=XED_REG_YMM30 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0,1}, +/*h(251)=31 OUTREG=XED_REG_YMM31 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 220; +if(hidx <= 31) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + xed3_operand_set_vexdest4(xes,lu_table[hidx].vexdest4); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_N3(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_ntluf_func_ptr_t ntlufptr0;} lu_entry_t; +static const lu_entry_t lu_table[3] = { +/*h(0)=0 MODE=0 -> ntluf*/ {xed_encode_ntluf_ZMM_N3_32}, +/*h(1)=1 MODE=1 -> ntluf*/ {xed_encode_ntluf_ZMM_N3_32}, +/*h(2)=2 MODE=2 -> ntluf*/ {xed_encode_ntluf_ZMM_N3_64} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed_uint64_t res = 1; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_MODE(xes); +hidx = key - 0; +if(hidx <= 2) { + if(lu_table[hidx].ntlufptr0 != 0) res=(*lu_table[hidx].ntlufptr0)(xes,arg_reg); + return res; + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_N3_32(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(252)=0 OUTREG=XED_REG_ZMM0 -> FB VEXDEST210=7 value=0x7*/ {7}, +/*h(253)=1 OUTREG=XED_REG_ZMM1 -> FB VEXDEST210=6 value=0x6*/ {6}, +/*h(254)=2 OUTREG=XED_REG_ZMM2 -> FB VEXDEST210=5 value=0x5*/ {5}, +/*h(255)=3 OUTREG=XED_REG_ZMM3 -> FB VEXDEST210=4 value=0x4*/ {4}, +/*h(256)=4 OUTREG=XED_REG_ZMM4 -> FB VEXDEST210=3 value=0x3*/ {3}, +/*h(257)=5 OUTREG=XED_REG_ZMM5 -> FB VEXDEST210=2 value=0x2*/ {2}, +/*h(258)=6 OUTREG=XED_REG_ZMM6 -> FB VEXDEST210=1 value=0x1*/ {1}, +/*h(259)=7 OUTREG=XED_REG_ZMM7 -> FB VEXDEST210=0 value=0x0*/ {0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 252; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_ZMM_N3_64(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3 ;xed_int8_t vexdest4;} lu_entry_t; +static const lu_entry_t lu_table[32] = { +/*h(252)=0 OUTREG=XED_REG_ZMM0 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1,0}, +/*h(253)=1 OUTREG=XED_REG_ZMM1 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1,0}, +/*h(254)=2 OUTREG=XED_REG_ZMM2 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1,0}, +/*h(255)=3 OUTREG=XED_REG_ZMM3 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1,0}, +/*h(256)=4 OUTREG=XED_REG_ZMM4 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1,0}, +/*h(257)=5 OUTREG=XED_REG_ZMM5 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1,0}, +/*h(258)=6 OUTREG=XED_REG_ZMM6 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1,0}, +/*h(259)=7 OUTREG=XED_REG_ZMM7 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1,0}, +/*h(260)=8 OUTREG=XED_REG_ZMM8 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0,0}, +/*h(261)=9 OUTREG=XED_REG_ZMM9 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0,0}, +/*h(262)=10 OUTREG=XED_REG_ZMM10 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0,0}, +/*h(263)=11 OUTREG=XED_REG_ZMM11 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0,0}, +/*h(264)=12 OUTREG=XED_REG_ZMM12 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0,0}, +/*h(265)=13 OUTREG=XED_REG_ZMM13 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0,0}, +/*h(266)=14 OUTREG=XED_REG_ZMM14 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0,0}, +/*h(267)=15 OUTREG=XED_REG_ZMM15 -> FB VEXDEST4=0 value=0x0 FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0,0}, +/*h(268)=16 OUTREG=XED_REG_ZMM16 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1,1}, +/*h(269)=17 OUTREG=XED_REG_ZMM17 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1,1}, +/*h(270)=18 OUTREG=XED_REG_ZMM18 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1,1}, +/*h(271)=19 OUTREG=XED_REG_ZMM19 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1,1}, +/*h(272)=20 OUTREG=XED_REG_ZMM20 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1,1}, +/*h(273)=21 OUTREG=XED_REG_ZMM21 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1,1}, +/*h(274)=22 OUTREG=XED_REG_ZMM22 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1,1}, +/*h(275)=23 OUTREG=XED_REG_ZMM23 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1,1}, +/*h(276)=24 OUTREG=XED_REG_ZMM24 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=7 value=0x7*/ {7,0,1}, +/*h(277)=25 OUTREG=XED_REG_ZMM25 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=6 value=0x6*/ {6,0,1}, +/*h(278)=26 OUTREG=XED_REG_ZMM26 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=5 value=0x5*/ {5,0,1}, +/*h(279)=27 OUTREG=XED_REG_ZMM27 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=4 value=0x4*/ {4,0,1}, +/*h(280)=28 OUTREG=XED_REG_ZMM28 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=3 value=0x3*/ {3,0,1}, +/*h(281)=29 OUTREG=XED_REG_ZMM29 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=2 value=0x2*/ {2,0,1}, +/*h(282)=30 OUTREG=XED_REG_ZMM30 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=1 value=0x1*/ {1,0,1}, +/*h(283)=31 OUTREG=XED_REG_ZMM31 -> FB VEXDEST4=1 value=0x1 FB VEXDEST3=0 value=0x0 FB VEXDEST210=0 value=0x0*/ {0,0,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 252; +if(hidx <= 31) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + xed3_operand_set_vexdest4(xes,lu_table[hidx].vexdest4); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_TMM_R(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t reg ;xed_int8_t rexr;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(170)=0 OUTREG=XED_REG_TMM0 -> FB REXR=0 value=0x0 FB REG=0 value=0x0*/ {0,0}, +/*h(171)=1 OUTREG=XED_REG_TMM1 -> FB REXR=0 value=0x0 FB REG=1 value=0x1*/ {1,0}, +/*h(172)=2 OUTREG=XED_REG_TMM2 -> FB REXR=0 value=0x0 FB REG=2 value=0x2*/ {2,0}, +/*h(173)=3 OUTREG=XED_REG_TMM3 -> FB REXR=0 value=0x0 FB REG=3 value=0x3*/ {3,0}, +/*h(174)=4 OUTREG=XED_REG_TMM4 -> FB REXR=0 value=0x0 FB REG=4 value=0x4*/ {4,0}, +/*h(175)=5 OUTREG=XED_REG_TMM5 -> FB REXR=0 value=0x0 FB REG=5 value=0x5*/ {5,0}, +/*h(176)=6 OUTREG=XED_REG_TMM6 -> FB REXR=0 value=0x0 FB REG=6 value=0x6*/ {6,0}, +/*h(177)=7 OUTREG=XED_REG_TMM7 -> FB REXR=0 value=0x0 FB REG=7 value=0x7*/ {7,0} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 170; +if(hidx <= 7) { + xed3_operand_set_reg(xes,lu_table[hidx].reg); + xed3_operand_set_rexr(xes,lu_table[hidx].rexr); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_TMM_B(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t rexb ;xed_int8_t rm;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(170)=0 OUTREG=XED_REG_TMM0 -> FB REXB=0 value=0x0 FB RM=0 value=0x0*/ {0,0}, +/*h(171)=1 OUTREG=XED_REG_TMM1 -> FB REXB=0 value=0x0 FB RM=1 value=0x1*/ {0,1}, +/*h(172)=2 OUTREG=XED_REG_TMM2 -> FB REXB=0 value=0x0 FB RM=2 value=0x2*/ {0,2}, +/*h(173)=3 OUTREG=XED_REG_TMM3 -> FB REXB=0 value=0x0 FB RM=3 value=0x3*/ {0,3}, +/*h(174)=4 OUTREG=XED_REG_TMM4 -> FB REXB=0 value=0x0 FB RM=4 value=0x4*/ {0,4}, +/*h(175)=5 OUTREG=XED_REG_TMM5 -> FB REXB=0 value=0x0 FB RM=5 value=0x5*/ {0,5}, +/*h(176)=6 OUTREG=XED_REG_TMM6 -> FB REXB=0 value=0x0 FB RM=6 value=0x6*/ {0,6}, +/*h(177)=7 OUTREG=XED_REG_TMM7 -> FB REXB=0 value=0x0 FB RM=7 value=0x7*/ {0,7} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 170; +if(hidx <= 7) { + xed3_operand_set_rexb(xes,lu_table[hidx].rexb); + xed3_operand_set_rm(xes,lu_table[hidx].rm); + return 1; +} +else{ + return 0; +} +} +xed_uint32_t xed_encode_ntluf_TMM_N(xed_encoder_request_t* xes, xed_reg_enum_t arg_reg) +{ +typedef struct { xed_int8_t vexdest210 ;xed_int8_t vexdest3;} lu_entry_t; +static const lu_entry_t lu_table[8] = { +/*h(170)=0 OUTREG=XED_REG_TMM0 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=7 value=0x7*/ {7,1}, +/*h(171)=1 OUTREG=XED_REG_TMM1 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=6 value=0x6*/ {6,1}, +/*h(172)=2 OUTREG=XED_REG_TMM2 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=5 value=0x5*/ {5,1}, +/*h(173)=3 OUTREG=XED_REG_TMM3 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=4 value=0x4*/ {4,1}, +/*h(174)=4 OUTREG=XED_REG_TMM4 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=3 value=0x3*/ {3,1}, +/*h(175)=5 OUTREG=XED_REG_TMM5 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=2 value=0x2*/ {2,1}, +/*h(176)=6 OUTREG=XED_REG_TMM6 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=1 value=0x1*/ {1,1}, +/*h(177)=7 OUTREG=XED_REG_TMM7 -> FB VEXDEST3=1 value=0x1 FB VEXDEST210=0 value=0x0*/ {0,1} +}; +xed_uint64_t key = 0; +xed_uint64_t hidx = 0; +xed3_operand_set_outreg(xes,arg_reg); +key = xed_enc_lu_OUTREG(xes); +hidx = key - 170; +if(hidx <= 7) { + xed3_operand_set_vexdest210(xes,lu_table[hidx].vexdest210); + xed3_operand_set_vexdest3(xes,lu_table[hidx].vexdest3); + return 1; +} +else{ + return 0; +} +} +xed_uint_t xed_encode_nonterminal_SEGMENT_DEFAULT_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* SEGMENT_DEFAULT_ENCODE():: + BASE0=@ -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_SP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1 + BASE0=XED_REG_ESP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1 + BASE0=XED_REG_RSP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1 + BASE0=XED_REG_BP EASZ=1 -> FB DEFAULT_SEG=1 value=0x1 + BASE0=XED_REG_EBP EASZ=2 -> FB DEFAULT_SEG=1 value=0x1 + BASE0=XED_REG_RBP EASZ=3 -> FB DEFAULT_SEG=1 value=0x1 + BASE0=XED_REG_AX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_EAX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_RAX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_CX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_ECX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_RCX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_DX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_EDX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_RDX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_BX EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_EBX EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_RBX EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_SI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_ESI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_RSI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_DI EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_EDI EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_RDI EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R8W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R8D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R8 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R9W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R9D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R9 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R10W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R10D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R10 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R11W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R11D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R11 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R12W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R12D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R12 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R13W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R13D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R13 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R14W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R14D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R14 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R15W EASZ=1 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R15D EASZ=2 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_R15 EASZ=3 -> FB DEFAULT_SEG=0 value=0x0 + BASE0=XED_REG_EIP EASZ=2 -> nothing + BASE0=XED_REG_RIP EASZ=3 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_SEGMENT_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* SEGMENT_ENCODE():: + DEFAULT_SEG=1 SEG0=@ -> FB SEG_OVD=0 value=0x0 + DEFAULT_SEG=1 SEG0=XED_REG_CS -> FB SEG_OVD=1 value=0x1 + DEFAULT_SEG=1 SEG0=XED_REG_DS -> FB SEG_OVD=2 value=0x2 + DEFAULT_SEG=1 SEG0=XED_REG_SS -> FB SEG_OVD=0 value=0x0 + DEFAULT_SEG=1 SEG0=XED_REG_ES -> FB SEG_OVD=3 value=0x3 + DEFAULT_SEG=1 SEG0=XED_REG_FS -> FB SEG_OVD=4 value=0x4 + DEFAULT_SEG=1 SEG0=XED_REG_GS -> FB SEG_OVD=5 value=0x5 + DEFAULT_SEG=0 SEG0=@ -> FB SEG_OVD=0 value=0x0 + DEFAULT_SEG=0 SEG0=XED_REG_CS -> FB SEG_OVD=1 value=0x1 + DEFAULT_SEG=0 SEG0=XED_REG_DS -> FB SEG_OVD=0 value=0x0 + DEFAULT_SEG=0 SEG0=XED_REG_SS -> FB SEG_OVD=6 value=0x6 + DEFAULT_SEG=0 SEG0=XED_REG_ES -> FB SEG_OVD=3 value=0x3 + DEFAULT_SEG=0 SEG0=XED_REG_FS -> FB SEG_OVD=4 value=0x4 + DEFAULT_SEG=0 SEG0=XED_REG_GS -> FB SEG_OVD=5 value=0x5 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_SIB_REQUIRED_ENCODE_BIND(xed_encoder_request_t* xes) +{ +/* SIB_REQUIRED_ENCODE():: + EASZ=3 BASE0=@ DISP_WIDTH=32 -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 BASE0=@ DISP_WIDTH=32 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RAX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RBX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RCX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RDX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RSP -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RBP -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RSI -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RDI -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R8 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R9 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R10 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R11 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R12 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R13 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R14 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R15 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_SP EASZ=1 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_ESP EASZ=2 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_RSP EASZ=3 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_R12W EASZ=1 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_R12D EASZ=2 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_R12 EASZ=3 -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R8D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R9D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R10D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R11D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R12D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R13D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R14D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R15D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=0 -> nothing + EASZ=2 MODE=1 -> nothing + */ +xed_uint_t okay=1; +xed_uint_t conditions_satisfied=0; +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID) && + (xed3_operand_get_disp_width(xes) == 32); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID) && + (xed3_operand_get_disp_width(xes) == 32); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RAX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RBX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RCX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RDX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RSP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RBP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RSI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_RDI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R8); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R9); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R10); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R11); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R12); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R13); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R14); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_index(xes) == XED_REG_R15); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_base0(xes) == XED_REG_SP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_base0(xes) == XED_REG_ESP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_base0(xes) == XED_REG_RSP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_base0(xes) == XED_REG_R12W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_base0(xes) == XED_REG_R12D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) != 1) && + (xed3_operand_get_base0(xes) == XED_REG_R12) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_EAX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_EBX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_ECX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_EDX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_ESP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_EBP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_ESI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_index(xes) == XED_REG_EDI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_EAX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_EBX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_ECX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_EDX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_ESP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_EBP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_ESI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_EDI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R8D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R9D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R10D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R11D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R12D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R13D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R14D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_index(xes) == XED_REG_R15D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_need_sib(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 0); +if (conditions_satisfied) { + okay=1; + return 1; /* nothing */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_mode(xes) == 1); +if (conditions_satisfied) { + okay=1; + return 1; /* nothing */ + if (okay) return 1; +} +conditions_satisfied = 1; +if (conditions_satisfied) { + okay=1; +/* FIXME action code not done yet for return 1*/ + if (okay) return 1; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) conditions_satisfied; +} +xed_uint_t xed_encode_nonterminal_SIB_REQUIRED_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* SIB_REQUIRED_ENCODE():: + EASZ=3 BASE0=@ DISP_WIDTH=32 -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 BASE0=@ DISP_WIDTH=32 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RAX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RBX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RCX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RDX -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RSP -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RBP -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RSI -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_RDI -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R8 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R9 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R10 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R11 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R12 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R13 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R14 -> FB NEED_SIB=1 value=0x1 + EASZ=3 INDEX=XED_REG_R15 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_SP EASZ=1 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_ESP EASZ=2 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_RSP EASZ=3 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_R12W EASZ=1 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_R12D EASZ=2 -> FB NEED_SIB=1 value=0x1 + EASZ!=1 BASE0=XED_REG_R12 EASZ=3 -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=1 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EAX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EBX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_ECX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EDX -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_ESP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EBP -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_ESI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_EDI -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R8D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R9D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R10D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R11D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R12D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R13D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R14D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=2 INDEX=XED_REG_R15D -> FB NEED_SIB=1 value=0x1 + EASZ=2 MODE=0 -> nothing + EASZ=2 MODE=1 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_SIBBASE_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* SIBBASE_ENCODE():: + NEED_SIB=1 -> nt NT[SIBBASE_ENCODE_SIB1] + NEED_SIB=0 -> nothing + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SIBBASE_ENCODE; +/* 2 */ if (iform==2) { + xed_encode_nonterminal_SIBBASE_ENCODE_SIB1_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (1) { /* nothing */ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-3.c b/CodeVirtualizer/build/obj/xed-encoder-3.c new file mode 100644 index 0000000..1233bb1 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-3.c @@ -0,0 +1,4525 @@ +/// @file xed-encoder-3.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encoder.h" +#include "xed-encode-private.h" +#include "xed-enc-operand-lu.h" +#include "xed-operand-accessors.h" +xed_uint_t xed_encode_nonterminal_SIBBASE_ENCODE_SIB1_EMIT(xed_encoder_request_t* xes) +{ +/* SIBBASE_ENCODE_SIB1():: + BASE0=XED_REG_AX EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 + BASE0=XED_REG_EAX EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 + BASE0=XED_REG_RAX EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=0 value=0x0 + BASE0=XED_REG_R8W EASZ=1 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 + BASE0=XED_REG_R8D EASZ=2 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 + BASE0=XED_REG_R8 EASZ=3 -> FB SIBBASE=0 value=0x0 FB REXB=1 value=0x1 + BASE0=XED_REG_CX EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 + BASE0=XED_REG_ECX EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 + BASE0=XED_REG_RCX EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=0 value=0x0 + BASE0=XED_REG_R9W EASZ=1 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 + BASE0=XED_REG_R9D EASZ=2 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 + BASE0=XED_REG_R9 EASZ=3 -> FB SIBBASE=1 value=0x1 FB REXB=1 value=0x1 + BASE0=XED_REG_DX EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 + BASE0=XED_REG_EDX EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 + BASE0=XED_REG_RDX EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=0 value=0x0 + BASE0=XED_REG_R10W EASZ=1 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 + BASE0=XED_REG_R10D EASZ=2 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 + BASE0=XED_REG_R10 EASZ=3 -> FB SIBBASE=2 value=0x2 FB REXB=1 value=0x1 + BASE0=XED_REG_BX EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 + BASE0=XED_REG_EBX EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 + BASE0=XED_REG_RBX EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=0 value=0x0 + BASE0=XED_REG_R11W EASZ=1 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 + BASE0=XED_REG_R11D EASZ=2 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 + BASE0=XED_REG_R11 EASZ=3 -> FB SIBBASE=3 value=0x3 FB REXB=1 value=0x1 + BASE0=XED_REG_SP EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 + BASE0=XED_REG_ESP EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 + BASE0=XED_REG_RSP EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=0 value=0x0 + BASE0=XED_REG_R12W EASZ=1 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 + BASE0=XED_REG_R12D EASZ=2 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 + BASE0=XED_REG_R12 EASZ=3 -> FB SIBBASE=4 value=0x4 FB REXB=1 value=0x1 + BASE0=XED_REG_SI EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 + BASE0=XED_REG_ESI EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 + BASE0=XED_REG_RSI EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=0 value=0x0 + BASE0=XED_REG_R14W EASZ=1 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 + BASE0=XED_REG_R14D EASZ=2 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 + BASE0=XED_REG_R14 EASZ=3 -> FB SIBBASE=6 value=0x6 FB REXB=1 value=0x1 + BASE0=XED_REG_DI EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 + BASE0=XED_REG_EDI EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 + BASE0=XED_REG_RDI EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=0 value=0x0 + BASE0=XED_REG_R15W EASZ=1 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 + BASE0=XED_REG_R15D EASZ=2 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 + BASE0=XED_REG_R15 EASZ=3 -> FB SIBBASE=7 value=0x7 FB REXB=1 value=0x1 + BASE0=@ -> nt NT[DISP_WIDTH_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 + BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 + BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 + BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=0 value=0x0 + BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 + BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 + BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_0_8_32] FB SIBBASE=5 value=0x5 FB REXB=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SIBBASE_ENCODE_SIB1; +/* 91 */ if (iform==91) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 14 */ if (iform==14) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 41 */ if (iform==41) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 28 */ if (iform==28) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 46 */ if (iform==46) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 73 */ if (iform==73) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 95 */ if (iform==95) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 18 */ if (iform==18) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 45 */ if (iform==45) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 32 */ if (iform==32) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 50 */ if (iform==50) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 77 */ if (iform==77) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 22 */ if (iform==22) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 49 */ if (iform==49) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 36 */ if (iform==36) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 54 */ if (iform==54) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 81 */ if (iform==81) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 8 */ if (iform==8) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 26 */ if (iform==26) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 53 */ if (iform==53) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 40 */ if (iform==40) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 58 */ if (iform==58) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 85 */ if (iform==85) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 12 */ if (iform==12) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 30 */ if (iform==30) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 57 */ if (iform==57) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 44 */ if (iform==44) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 62 */ if (iform==62) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 89 */ if (iform==89) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 20 */ if (iform==20) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 38 */ if (iform==38) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 65 */ if (iform==65) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 52 */ if (iform==52) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 70 */ if (iform==70) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 97 */ if (iform==97) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 24 */ if (iform==24) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 42 */ if (iform==42) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 69 */ if (iform==69) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 56 */ if (iform==56) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 74 */ if (iform==74) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 101 */ if (iform==101) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 71 */ if (iform==71) { + xed_encode_nonterminal_DISP_WIDTH_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 16 */ if (iform==16) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 34 */ if (iform==34) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 61 */ if (iform==61) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 48 */ if (iform==48) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 66 */ if (iform==66) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 93 */ if (iform==93) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_SIBINDEX_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* SIBINDEX_ENCODE():: + NEED_SIB=1 -> nt NT[SIBINDEX_ENCODE_SIB1] + NEED_SIB=0 -> nothing + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SIBINDEX_ENCODE; +/* 2 */ if (iform==2) { + xed_encode_nonterminal_SIBINDEX_ENCODE_SIB1_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (1) { /* nothing */ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_SIBINDEX_ENCODE_SIB1_EMIT(xed_encoder_request_t* xes) +{ +/* SIBINDEX_ENCODE_SIB1():: + INDEX=@ -> FB SIBINDEX=4 value=0x4 FB REXX=0 value=0x0 + INDEX=XED_REG_AX EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 + INDEX=XED_REG_EAX EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 + INDEX=XED_REG_RAX EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=0 value=0x0 + INDEX=XED_REG_R8W EASZ=1 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 + INDEX=XED_REG_R8D EASZ=2 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 + INDEX=XED_REG_R8 EASZ=3 -> FB SIBINDEX=0 value=0x0 FB REXX=1 value=0x1 + INDEX=XED_REG_CX EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 + INDEX=XED_REG_ECX EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 + INDEX=XED_REG_RCX EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=0 value=0x0 + INDEX=XED_REG_R9W EASZ=1 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 + INDEX=XED_REG_R9D EASZ=2 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 + INDEX=XED_REG_R9 EASZ=3 -> FB SIBINDEX=1 value=0x1 FB REXX=1 value=0x1 + INDEX=XED_REG_DX EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 + INDEX=XED_REG_EDX EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 + INDEX=XED_REG_RDX EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=0 value=0x0 + INDEX=XED_REG_R10W EASZ=1 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 + INDEX=XED_REG_R10D EASZ=2 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 + INDEX=XED_REG_R10 EASZ=3 -> FB SIBINDEX=2 value=0x2 FB REXX=1 value=0x1 + INDEX=XED_REG_BX EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 + INDEX=XED_REG_EBX EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 + INDEX=XED_REG_RBX EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=0 value=0x0 + INDEX=XED_REG_R11W EASZ=1 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 + INDEX=XED_REG_R11D EASZ=2 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 + INDEX=XED_REG_R11 EASZ=3 -> FB SIBINDEX=3 value=0x3 FB REXX=1 value=0x1 + INDEX=XED_REG_R12W EASZ=1 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 + INDEX=XED_REG_R12D EASZ=2 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 + INDEX=XED_REG_R12 EASZ=3 -> FB SIBINDEX=4 value=0x4 FB REXX=1 value=0x1 + INDEX=XED_REG_BP EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 + INDEX=XED_REG_EBP EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 + INDEX=XED_REG_RBP EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=0 value=0x0 + INDEX=XED_REG_R13W EASZ=1 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 + INDEX=XED_REG_R13D EASZ=2 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 + INDEX=XED_REG_R13 EASZ=3 -> FB SIBINDEX=5 value=0x5 FB REXX=1 value=0x1 + INDEX=XED_REG_SI EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 + INDEX=XED_REG_ESI EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 + INDEX=XED_REG_RSI EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=0 value=0x0 + INDEX=XED_REG_R14W EASZ=1 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 + INDEX=XED_REG_R14D EASZ=2 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 + INDEX=XED_REG_R14 EASZ=3 -> FB SIBINDEX=6 value=0x6 FB REXX=1 value=0x1 + INDEX=XED_REG_DI EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 + INDEX=XED_REG_EDI EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 + INDEX=XED_REG_RDI EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=0 value=0x0 + INDEX=XED_REG_R15W EASZ=1 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 + INDEX=XED_REG_R15D EASZ=2 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 + INDEX=XED_REG_R15 EASZ=3 -> FB SIBINDEX=7 value=0x7 FB REXX=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_SIBSCALE_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* SIBSCALE_ENCODE():: + NEED_SIB=1 SCALE=0 -> FB SIBSCALE=0 value=0x0 + NEED_SIB=1 SCALE=1 -> FB SIBSCALE=0 value=0x0 + NEED_SIB=1 SCALE=2 -> FB SIBSCALE=1 value=0x1 + NEED_SIB=1 SCALE=4 -> FB SIBSCALE=2 value=0x2 + NEED_SIB=1 SCALE=8 -> FB SIBSCALE=3 value=0x3 + NEED_SIB=0 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_ENCODE():: + EASZ=1 DISP_WIDTH=0 -> nt NT[MODRM_MOD_EA16_DISP0] + EASZ=1 DISP_WIDTH=8 -> nt NT[MODRM_MOD_EA16_DISP8] + EASZ=1 DISP_WIDTH=16 -> nt NT[MODRM_MOD_EA16_DISP16] + EASZ=1 DISP_WIDTH=32 -> nt NT[ERROR] + EASZ=1 DISP_WIDTH=64 -> nt NT[ERROR] + EASZ=2 DISP_WIDTH=0 -> nt NT[MODRM_MOD_EA32_DISP0] + EASZ=2 DISP_WIDTH=8 -> nt NT[MODRM_MOD_EA32_DISP8] + EASZ=2 DISP_WIDTH=16 -> nt NT[ERROR] + EASZ=2 DISP_WIDTH=32 -> nt NT[MODRM_MOD_EA32_DISP32] + EASZ=2 DISP_WIDTH=64 -> nt NT[ERROR] + EASZ=3 DISP_WIDTH=0 -> nt NT[MODRM_MOD_EA64_DISP0] + EASZ=3 DISP_WIDTH=8 -> nt NT[MODRM_MOD_EA64_DISP8] + EASZ=3 DISP_WIDTH=16 -> nt NT[ERROR] + EASZ=3 DISP_WIDTH=32 -> nt NT[MODRM_MOD_EA64_DISP32] + EASZ=3 DISP_WIDTH=64 -> nt NT[ERROR] + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MODRM_MOD_ENCODE; +/* 9 */ if (iform==9) { + xed_encode_nonterminal_MODRM_MOD_EA16_DISP0_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 6 */ if (iform==6) { + xed_encode_nonterminal_MODRM_MOD_EA16_DISP8_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encode_nonterminal_MODRM_MOD_EA16_DISP16_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 12 */ if (iform==12) { + xed_encode_nonterminal_ERROR_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 15 */ if (iform==15) { + xed_encode_nonterminal_ERROR_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encode_nonterminal_MODRM_MOD_EA32_DISP0_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encode_nonterminal_MODRM_MOD_EA32_DISP8_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 13 */ if (iform==13) { + xed_encode_nonterminal_ERROR_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + xed_encode_nonterminal_MODRM_MOD_EA32_DISP32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 10 */ if (iform==10) { + xed_encode_nonterminal_ERROR_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 14 */ if (iform==14) { + xed_encode_nonterminal_MODRM_MOD_EA64_DISP0_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 11 */ if (iform==11) { + xed_encode_nonterminal_MODRM_MOD_EA64_DISP8_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 8 */ if (iform==8) { + xed_encode_nonterminal_ERROR_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encode_nonterminal_MODRM_MOD_EA64_DISP32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 5 */ if (iform==5) { + xed_encode_nonterminal_ERROR_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP0_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA16_DISP0():: + BASE0=XED_REG_BX INDEX=@ -> FB MOD=0 value=0x0 + BASE0=XED_REG_SI INDEX=@ -> FB MOD=0 value=0x0 + BASE0=XED_REG_DI INDEX=@ -> FB MOD=0 value=0x0 + BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB MOD=0 value=0x0 + BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB MOD=0 value=0x0 + BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB MOD=0 value=0x0 + BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB MOD=0 value=0x0 + BASE0=XED_REG_BP INDEX=@ -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP8_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA16_DISP8():: + BASE0=XED_REG_BX INDEX=@ -> FB MOD=1 value=0x1 + BASE0=XED_REG_SI INDEX=@ -> FB MOD=1 value=0x1 + BASE0=XED_REG_DI INDEX=@ -> FB MOD=1 value=0x1 + BASE0=XED_REG_BP INDEX=@ -> FB MOD=1 value=0x1 + BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB MOD=1 value=0x1 + BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB MOD=1 value=0x1 + BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB MOD=1 value=0x1 + BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB MOD=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA16_DISP16_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA16_DISP16():: + BASE0=@ INDEX=@ -> FB MOD=0 value=0x0 + BASE0=XED_REG_BX INDEX=@ -> FB MOD=2 value=0x2 + BASE0=XED_REG_SI INDEX=@ -> FB MOD=2 value=0x2 + BASE0=XED_REG_DI INDEX=@ -> FB MOD=2 value=0x2 + BASE0=XED_REG_BP INDEX=@ -> FB MOD=2 value=0x2 + BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB MOD=2 value=0x2 + BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB MOD=2 value=0x2 + BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB MOD=2 value=0x2 + BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB MOD=2 value=0x2 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP0_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA32_DISP0():: + BASE0=XED_REG_EAX MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EBX MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_ECX MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EDX MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_ESI MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EDI MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_ESP MODE=1 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EAX MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EBX MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_ECX MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EDX MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_ESI MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EDI MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_ESP MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R8D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R9D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R10D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R11D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R12D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R14D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R15D MODE=2 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EBP MODE=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + BASE0=XED_REG_EBP MODE=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + BASE0=XED_REG_R13D MODE=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP8_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA32_DISP8():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA32_DISP32_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA32_DISP32():: + BASE0=@ -> FB MOD=0 value=0x0 + MODE=2 BASE0=XED_REG_EIP EASZ=2 -> FB MOD=0 value=0x0 + MODE=2 BASE0=XED_REG_RIP EASZ=3 -> FB MOD=0 value=0x0 + MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 + MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2 + MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP0_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA64_DISP0():: + BASE0=XED_REG_RAX -> FB MOD=0 value=0x0 + BASE0=XED_REG_RBX -> FB MOD=0 value=0x0 + BASE0=XED_REG_RCX -> FB MOD=0 value=0x0 + BASE0=XED_REG_RDX -> FB MOD=0 value=0x0 + BASE0=XED_REG_RSI -> FB MOD=0 value=0x0 + BASE0=XED_REG_RDI -> FB MOD=0 value=0x0 + BASE0=XED_REG_RSP -> FB MOD=0 value=0x0 + BASE0=XED_REG_R8 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R9 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R10 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R11 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R12 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R14 -> FB MOD=0 value=0x0 + BASE0=XED_REG_R15 -> FB MOD=0 value=0x0 + BASE0=XED_REG_EIP -> FB MOD=0 value=0x0 FB DISP_WIDTH=32 value=0x20 FB DISP=0 value=0x0 + BASE0=XED_REG_RIP -> FB MOD=0 value=0x0 FB DISP_WIDTH=32 value=0x20 FB DISP=0 value=0x0 + BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP8_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA64_DISP8():: + BASE0=XED_REG_RAX -> FB MOD=1 value=0x1 + BASE0=XED_REG_RBX -> FB MOD=1 value=0x1 + BASE0=XED_REG_RCX -> FB MOD=1 value=0x1 + BASE0=XED_REG_RDX -> FB MOD=1 value=0x1 + BASE0=XED_REG_RSP -> FB MOD=1 value=0x1 + BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 + BASE0=XED_REG_RSI -> FB MOD=1 value=0x1 + BASE0=XED_REG_RDI -> FB MOD=1 value=0x1 + BASE0=XED_REG_R8 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R9 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R10 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R11 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R12 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R14 -> FB MOD=1 value=0x1 + BASE0=XED_REG_R15 -> FB MOD=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_MOD_EA64_DISP32_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_MOD_EA64_DISP32():: + BASE0=@ -> FB MOD=0 value=0x0 + BASE0=XED_REG_EIP -> FB MOD=0 value=0x0 + BASE0=XED_REG_RIP -> FB MOD=0 value=0x0 + BASE0=XED_REG_RAX -> FB MOD=2 value=0x2 + BASE0=XED_REG_RBX -> FB MOD=2 value=0x2 + BASE0=XED_REG_RCX -> FB MOD=2 value=0x2 + BASE0=XED_REG_RDX -> FB MOD=2 value=0x2 + BASE0=XED_REG_RSI -> FB MOD=2 value=0x2 + BASE0=XED_REG_RDI -> FB MOD=2 value=0x2 + BASE0=XED_REG_RSP -> FB MOD=2 value=0x2 + BASE0=XED_REG_RBP -> FB MOD=2 value=0x2 + BASE0=XED_REG_R8 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R9 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R10 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R11 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R12 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R13 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R14 -> FB MOD=2 value=0x2 + BASE0=XED_REG_R15 -> FB MOD=2 value=0x2 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_RM_ENCODE():: + EASZ=1 NEED_SIB=0 -> nt NT[MODRM_RM_ENCODE_EA16_SIB0] + EASZ=2 NEED_SIB=0 -> nt NT[MODRM_RM_ENCODE_EA32_SIB0] + EASZ=3 NEED_SIB=0 -> nt NT[MODRM_RM_ENCODE_EA64_SIB0] + EASZ!=1 NEED_SIB=1 -> nt NT[MODRM_RM_ENCODE_EANOT16_SIB1] + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE; +/* 5 */ if (iform==5) { + xed_encode_nonterminal_MODRM_RM_ENCODE_EA16_SIB0_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encode_nonterminal_MODRM_RM_ENCODE_EA32_SIB0_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + xed_encode_nonterminal_MODRM_RM_ENCODE_EA64_SIB0_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA16_SIB0_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_RM_ENCODE_EA16_SIB0():: + BASE0=XED_REG_BX INDEX=XED_REG_SI -> FB RM=0 value=0x0 + BASE0=XED_REG_BX INDEX=XED_REG_DI -> FB RM=1 value=0x1 + BASE0=XED_REG_BP INDEX=XED_REG_SI -> FB RM=2 value=0x2 + BASE0=XED_REG_BP INDEX=XED_REG_DI -> FB RM=3 value=0x3 + BASE0=XED_REG_SI INDEX=@ -> FB RM=4 value=0x4 + BASE0=XED_REG_DI INDEX=@ -> FB RM=5 value=0x5 + BASE0=XED_REG_BX INDEX=@ -> FB RM=7 value=0x7 + BASE0=@ INDEX=@ -> nt NT[DISP_WIDTH_16] FB RM=6 value=0x6 + BASE0=XED_REG_BP INDEX=@ -> nt NT[DISP_WIDTH_0_8_16] FB RM=6 value=0x6 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE_EA16_SIB0; +/* 6 */ if (iform==6) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 5 */ if (iform==5) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 8 */ if (iform==8) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 9 */ if (iform==9) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encode_nonterminal_DISP_WIDTH_16_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encode_nonterminal_DISP_WIDTH_0_8_16_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA64_SIB0_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_RM_ENCODE_EA64_SIB0():: + BASE0=XED_REG_RIP -> FB RM=5 value=0x5 + BASE0=XED_REG_EIP -> FB RM=5 value=0x5 + BASE0=XED_REG_RAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0 + BASE0=XED_REG_R8 -> FB RM=0 value=0x0 FB REXB=1 value=0x1 + BASE0=XED_REG_RCX -> FB RM=1 value=0x1 FB REXB=0 value=0x0 + BASE0=XED_REG_R9 -> FB RM=1 value=0x1 FB REXB=1 value=0x1 + BASE0=XED_REG_RDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0 + BASE0=XED_REG_R10 -> FB RM=2 value=0x2 FB REXB=1 value=0x1 + BASE0=XED_REG_RBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0 + BASE0=XED_REG_R11 -> FB RM=3 value=0x3 FB REXB=1 value=0x1 + BASE0=XED_REG_RSI -> FB RM=6 value=0x6 FB REXB=0 value=0x0 + BASE0=XED_REG_R14 -> FB RM=6 value=0x6 FB REXB=1 value=0x1 + BASE0=XED_REG_RDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0 + BASE0=XED_REG_R15 -> FB RM=7 value=0x7 FB REXB=1 value=0x1 + BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5 + BASE0=XED_REG_RBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0 + BASE0=XED_REG_R13 -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE_EA64_SIB0; +/* 14 */ if (iform==14) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 17 */ if (iform==17) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 12 */ if (iform==12) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 10 */ if (iform==10) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 5 */ if (iform==5) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 15 */ if (iform==15) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 13 */ if (iform==13) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 8 */ if (iform==8) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 9 */ if (iform==9) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 6 */ if (iform==6) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encode_nonterminal_DISP_WIDTH_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 16 */ if (iform==16) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 11 */ if (iform==11) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EA32_SIB0_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_RM_ENCODE_EA32_SIB0():: + BASE0=XED_REG_RIP MODE=2 -> FB RM=5 value=0x5 + BASE0=XED_REG_EIP MODE=2 -> FB RM=5 value=0x5 + BASE0=XED_REG_EAX -> FB RM=0 value=0x0 FB REXB=0 value=0x0 + BASE0=XED_REG_R8D -> FB RM=0 value=0x0 FB REXB=1 value=0x1 + BASE0=XED_REG_ECX -> FB RM=1 value=0x1 FB REXB=0 value=0x0 + BASE0=XED_REG_R9D -> FB RM=1 value=0x1 FB REXB=1 value=0x1 + BASE0=XED_REG_EDX -> FB RM=2 value=0x2 FB REXB=0 value=0x0 + BASE0=XED_REG_R10D -> FB RM=2 value=0x2 FB REXB=1 value=0x1 + BASE0=XED_REG_EBX -> FB RM=3 value=0x3 FB REXB=0 value=0x0 + BASE0=XED_REG_R11D -> FB RM=3 value=0x3 FB REXB=1 value=0x1 + BASE0=XED_REG_ESI -> FB RM=6 value=0x6 FB REXB=0 value=0x0 + BASE0=XED_REG_R14D -> FB RM=6 value=0x6 FB REXB=1 value=0x1 + BASE0=XED_REG_EDI -> FB RM=7 value=0x7 FB REXB=0 value=0x0 + BASE0=XED_REG_R15D -> FB RM=7 value=0x7 FB REXB=1 value=0x1 + BASE0=@ -> nt NT[DISP_WIDTH_32] FB RM=5 value=0x5 + BASE0=XED_REG_EBP -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=0 value=0x0 + BASE0=XED_REG_R13D -> nt NT[DISP_WIDTH_0_8_32] FB RM=5 value=0x5 FB REXB=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MODRM_RM_ENCODE_EA32_SIB0; +/* 66 */ if (iform==66) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 73 */ if (iform==73) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 19 */ if (iform==19) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 75 */ if (iform==75) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 26 */ if (iform==26) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 82 */ if (iform==82) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 33 */ if (iform==33) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 89 */ if (iform==89) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 40 */ if (iform==40) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 96 */ if (iform==96) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 61 */ if (iform==61) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 117 */ if (iform==117) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 68 */ if (iform==68) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 124 */ if (iform==124) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 34 */ if (iform==34) { + xed_encode_nonterminal_DISP_WIDTH_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 54 */ if (iform==54) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 110 */ if (iform==110) { + xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MODRM_RM_ENCODE_EANOT16_SIB1_EMIT(xed_encoder_request_t* xes) +{ +/* MODRM_RM_ENCODE_EANOT16_SIB1():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_SIB_NT_EMIT(xed_encoder_request_t* xes) +{ +/* SIB_NT():: + NEED_SIB=1 SIBBASE[bbb]=* SIBSCALE[ss]=* SIBINDEX[iii]=* -> emit ss_iii_bbb emit_type=letters nbits=8 + NEED_SIB=0 -> nothing + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SIB_NT; +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_sibscale(xes)<< 6)|(xed3_operand_get_sibindex(xes)<< 3)|(xed3_operand_get_sibbase(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (1) { /* nothing */ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_DISP_NT_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_NT():: + DISP_WIDTH=8 DISP[dddddddd]=* -> emit dddddddd emit_type=letters nbits=8 + DISP_WIDTH=16 DISP[dddddddddddddddd]=* -> emit dddddddddddddddd emit_type=letters nbits=16 + DISP_WIDTH=32 DISP[dddddddddddddddddddddddddddddddd]=* -> emit dddddddddddddddddddddddddddddddd emit_type=letters nbits=32 + DISP_WIDTH=64 DISP[dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd]=* -> emit dddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd emit_type=letters nbits=64 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_DISP_NT; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,64,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_ERROR_EMIT(xed_encoder_request_t* xes) +{ +/* ERROR():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_0_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_0():: + DISP_WIDTH=0 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_8_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_8():: + DISP_WIDTH=8 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_16_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_16():: + DISP_WIDTH=16 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_32_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_32():: + DISP_WIDTH=32 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_0_8_16_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_0_8_16():: + DISP_WIDTH=0 -> nothing + DISP_WIDTH=8 -> nothing + DISP_WIDTH=16 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_0_8_32_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_0_8_32():: + DISP_WIDTH=0 -> nothing + DISP_WIDTH=8 -> nothing + DISP_WIDTH=32 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_FIXUP_EOSZ_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* FIXUP_EOSZ_ENC():: + MODE=0 EOSZ=0 -> FB EOSZ=1 value=0x1 + MODE=1 EOSZ=0 -> FB EOSZ=2 value=0x2 + MODE=2 EOSZ=0 -> FB EOSZ=2 value=0x2 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_FIXUP_EASZ_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* FIXUP_EASZ_ENC():: + MODE=0 EASZ=0 -> FB EASZ=1 value=0x1 + MODE=1 EASZ=0 -> FB EASZ=2 value=0x2 + MODE=2 EASZ=0 -> FB EASZ=3 value=0x3 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_FIXUP_SMODE_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* FIXUP_SMODE_ENC():: + MODE=2 SMODE=0 -> FB SMODE=2 value=0x2 + MODE=2 SMODE=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_REMOVE_SEGMENT_EMIT(xed_encoder_request_t* xes) +{ +/* REMOVE_SEGMENT():: + AGEN=1 -> nt NT[REMOVE_SEGMENT_AGEN1] + AGEN=0 -> nothing + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_REMOVE_SEGMENT; +/* 2 */ if (iform==2) { + xed_encode_nonterminal_REMOVE_SEGMENT_AGEN1_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (1) { /* nothing */ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_REMOVE_SEGMENT_AGEN1_EMIT(xed_encoder_request_t* xes) +{ +/* REMOVE_SEGMENT_AGEN1():: + SEG0=@ -> nothing + SEG0=XED_REG_DS -> FB ERROR=XED_ERROR_GENERAL_ERROR + SEG0=XED_REG_CS -> FB ERROR=XED_ERROR_GENERAL_ERROR + SEG0=XED_REG_ES -> FB ERROR=XED_ERROR_GENERAL_ERROR + SEG0=XED_REG_FS -> FB ERROR=XED_ERROR_GENERAL_ERROR + SEG0=XED_REG_GS -> FB ERROR=XED_ERROR_GENERAL_ERROR + SEG0=XED_REG_SS -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_OVERRIDE_SEG0_EMIT(xed_encoder_request_t* xes) +{ +/* OVERRIDE_SEG0():: + SEG0=@ -> FB SEG_OVD=0 value=0x0 + SEG0=XED_REG_DS -> FB SEG_OVD=0 value=0x0 + SEG0=XED_REG_CS -> FB SEG_OVD=1 value=0x1 + SEG0=XED_REG_ES -> FB SEG_OVD=3 value=0x3 + SEG0=XED_REG_FS -> FB SEG_OVD=4 value=0x4 + SEG0=XED_REG_GS -> FB SEG_OVD=5 value=0x5 + SEG0=XED_REG_SS -> FB SEG_OVD=6 value=0x6 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_OVERRIDE_SEG1_EMIT(xed_encoder_request_t* xes) +{ +/* OVERRIDE_SEG1():: + SEG1=@ -> FB SEG_OVD=0 value=0x0 + SEG1=XED_REG_DS -> FB SEG_OVD=0 value=0x0 + SEG1=XED_REG_CS -> FB SEG_OVD=1 value=0x1 + SEG1=XED_REG_ES -> FB SEG_OVD=3 value=0x3 + SEG1=XED_REG_FS -> FB SEG_OVD=4 value=0x4 + SEG1=XED_REG_GS -> FB SEG_OVD=5 value=0x5 + SEG1=XED_REG_SS -> FB SEG_OVD=6 value=0x6 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_REX_PREFIX_ENC_BIND(xed_encoder_request_t* xes) +{ +/* REX_PREFIX_ENC():: + MODE=2 NOREX=0 NEEDREX=1 REXW[w]=* REXB[b]=* REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REX=1 REXW[w]=* REXB[b]=* REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=1 REXB[b]=* REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=* REXB[b]=1 REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=* REXB[b]=* REXX[x]=1 REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=* REXB[b]=* REXX[x]=* REXR[r]=1 -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NEEDREX=0 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + MODE=1 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + MODE=0 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + MODE=2 NOREX=1 NEEDREX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXW=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +xed_uint_t conditions_satisfied=0; +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 0) && + (xed3_operand_get_needrex(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC=1; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 0) && + (xed3_operand_get_rex(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC=2; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 0) && + (xed3_operand_get_rexw(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC=3; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 0) && + (xed3_operand_get_rexb(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC=4; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 0) && + (xed3_operand_get_rexx(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC=5; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 0) && + (xed3_operand_get_rexr(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC=6; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_needrex(xes) == 0) && + (xed3_operand_get_rex(xes) == 0) && + (xed3_operand_get_rexw(xes) == 0) && + (xed3_operand_get_rexb(xes) == 0) && + (xed3_operand_get_rexx(xes) == 0) && + (xed3_operand_get_rexr(xes) == 0); +if (conditions_satisfied) { + okay=1; + return 1; /* nothing */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_rex(xes) == 0) && + (xed3_operand_get_rexw(xes) == 0) && + (xed3_operand_get_rexb(xes) == 0) && + (xed3_operand_get_rexx(xes) == 0) && + (xed3_operand_get_rexr(xes) == 0); +if (conditions_satisfied) { + okay=1; + return 1; /* nothing */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 0) && + (xed3_operand_get_rex(xes) == 0) && + (xed3_operand_get_rexw(xes) == 0) && + (xed3_operand_get_rexb(xes) == 0) && + (xed3_operand_get_rexx(xes) == 0) && + (xed3_operand_get_rexr(xes) == 0); +if (conditions_satisfied) { + okay=1; + return 1; /* nothing */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 1) && + (xed3_operand_get_needrex(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 1) && + (xed3_operand_get_rex(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 1) && + (xed3_operand_get_rexw(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 1) && + (xed3_operand_get_rexb(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 1) && + (xed3_operand_get_rexx(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_norex(xes) == 1) && + (xed3_operand_get_rexr(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ + if (okay) return 1; +} +conditions_satisfied = 1; +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ +/* FIXME action code not done yet for return 1*/ + if (okay) return 1; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) conditions_satisfied; +} +xed_uint_t xed_encode_nonterminal_REX_PREFIX_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* REX_PREFIX_ENC():: + MODE=2 NOREX=0 NEEDREX=1 REXW[w]=* REXB[b]=* REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REX=1 REXW[w]=* REXB[b]=* REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=1 REXB[b]=* REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=* REXB[b]=1 REXX[x]=* REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=* REXB[b]=* REXX[x]=1 REXR[r]=* -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NOREX=0 REXW[w]=* REXB[b]=* REXX[x]=* REXR[r]=1 -> emit 0b0100 emit_type=numeric value=0x4 nbits=4 emit wrxb emit_type=letters nbits=4 + MODE=2 NEEDREX=0 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + MODE=1 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + MODE=0 REX=0 REXW=0 REXB=0 REXX=0 REXR=0 -> nothing + MODE=2 NOREX=1 NEEDREX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXW=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE=2 NOREX=1 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_REX_PREFIX_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,4,0x4); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_rexw(xes)<< 3)|(xed3_operand_get_rexr(xes)<< 2)|(xed3_operand_get_rexx(xes)<< 1)|(xed3_operand_get_rexb(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,4,0x4); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_rexw(xes)<< 3)|(xed3_operand_get_rexr(xes)<< 2)|(xed3_operand_get_rexx(xes)<< 1)|(xed3_operand_get_rexb(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,4,0x4); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_rexw(xes)<< 3)|(xed3_operand_get_rexr(xes)<< 2)|(xed3_operand_get_rexx(xes)<< 1)|(xed3_operand_get_rexb(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,4,0x4); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_rexw(xes)<< 3)|(xed3_operand_get_rexr(xes)<< 2)|(xed3_operand_get_rexx(xes)<< 1)|(xed3_operand_get_rexb(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,4,0x4); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_rexw(xes)<< 3)|(xed3_operand_get_rexr(xes)<< 2)|(xed3_operand_get_rexx(xes)<< 1)|(xed3_operand_get_rexb(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 6 */ if (iform==6) { + xed_encoder_request_encode_emit(xes,4,0x4); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_rexw(xes)<< 3)|(xed3_operand_get_rexr(xes)<< 2)|(xed3_operand_get_rexx(xes)<< 1)|(xed3_operand_get_rexb(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (1) { /* nothing */ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_PREFIX_ENC_BIND(xed_encoder_request_t* xes) +{ +/* PREFIX_ENC():: + REP=2 -> emit 0xf2 emit_type=numeric value=0xf2 nbits=8 FB NO_RETURN=1 value=0x1 + REP=3 -> emit 0xf3 emit_type=numeric value=0xf3 nbits=8 FB NO_RETURN=1 value=0x1 + OSZ=1 -> emit 0x66 emit_type=numeric value=0x66 nbits=8 FB NO_RETURN=1 value=0x1 + ASZ=1 -> emit 0x67 emit_type=numeric value=0x67 nbits=8 FB NO_RETURN=1 value=0x1 + LOCK=1 -> emit 0xf0 emit_type=numeric value=0xf0 nbits=8 FB NO_RETURN=1 value=0x1 + SEG_OVD=4 -> emit 0x64 emit_type=numeric value=0x64 nbits=8 FB NO_RETURN=1 value=0x1 + SEG_OVD=5 -> emit 0x65 emit_type=numeric value=0x65 nbits=8 FB NO_RETURN=1 value=0x1 + MODE=2 HINT=3 -> emit 0x2e emit_type=numeric value=0x2e nbits=8 FB NO_RETURN=1 value=0x1 + MODE=2 HINT=4 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE=2 HINT=5 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=1 -> emit 0x2e emit_type=numeric value=0x2e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 HINT=3 -> emit 0x2e emit_type=numeric value=0x2e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=2 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 HINT=4 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 HINT=5 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=3 -> emit 0x26 emit_type=numeric value=0x26 nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=6 -> emit 0x36 emit_type=numeric value=0x36 nbits=8 FB NO_RETURN=1 value=0x1 + */ +xed_uint_t okay=1; +xed_uint_t conditions_satisfied=0; +xed_encoder_request_iforms(xes)->x_PREFIX_ENC=0; +conditions_satisfied = (xed3_operand_get_rep(xes) == 2); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<1); +} +conditions_satisfied = (xed3_operand_get_rep(xes) == 3); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<2); +} +conditions_satisfied = (xed3_operand_get_osz(xes) == 1); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<3); +} +conditions_satisfied = (xed3_operand_get_asz(xes) == 1); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<4); +} +conditions_satisfied = (xed3_operand_get_lock(xes) == 1); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<5); +} +conditions_satisfied = (xed3_operand_get_seg_ovd(xes) == 4); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<6); +} +conditions_satisfied = (xed3_operand_get_seg_ovd(xes) == 5); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<7); +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_hint(xes) == 3); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<8); +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_hint(xes) == 4); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<9); +} +conditions_satisfied = (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_hint(xes) == 5); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<10); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_seg_ovd(xes) == 1); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<11); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_hint(xes) == 3); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<12); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_seg_ovd(xes) == 2); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<13); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_hint(xes) == 4); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<14); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_hint(xes) == 5); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<15); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_seg_ovd(xes) == 3); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<16); +} +conditions_satisfied = (xed3_operand_get_mode(xes) != 2) && + (xed3_operand_get_seg_ovd(xes) == 6); +if (conditions_satisfied) { + okay=1; +/* no code required for NO_RETURN binding */ + xed_encoder_request_iforms(xes)->x_PREFIX_ENC |=(1<<17); +} +conditions_satisfied = 1; +if (conditions_satisfied) { + okay=1; +/* FIXME action code not done yet for return 1*/ + if (okay) return 1; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) conditions_satisfied; +} +xed_uint_t xed_encode_nonterminal_PREFIX_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* PREFIX_ENC():: + REP=2 -> emit 0xf2 emit_type=numeric value=0xf2 nbits=8 FB NO_RETURN=1 value=0x1 + REP=3 -> emit 0xf3 emit_type=numeric value=0xf3 nbits=8 FB NO_RETURN=1 value=0x1 + OSZ=1 -> emit 0x66 emit_type=numeric value=0x66 nbits=8 FB NO_RETURN=1 value=0x1 + ASZ=1 -> emit 0x67 emit_type=numeric value=0x67 nbits=8 FB NO_RETURN=1 value=0x1 + LOCK=1 -> emit 0xf0 emit_type=numeric value=0xf0 nbits=8 FB NO_RETURN=1 value=0x1 + SEG_OVD=4 -> emit 0x64 emit_type=numeric value=0x64 nbits=8 FB NO_RETURN=1 value=0x1 + SEG_OVD=5 -> emit 0x65 emit_type=numeric value=0x65 nbits=8 FB NO_RETURN=1 value=0x1 + MODE=2 HINT=3 -> emit 0x2e emit_type=numeric value=0x2e nbits=8 FB NO_RETURN=1 value=0x1 + MODE=2 HINT=4 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE=2 HINT=5 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=1 -> emit 0x2e emit_type=numeric value=0x2e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 HINT=3 -> emit 0x2e emit_type=numeric value=0x2e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=2 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 HINT=4 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 HINT=5 -> emit 0x3e emit_type=numeric value=0x3e nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=3 -> emit 0x26 emit_type=numeric value=0x26 nbits=8 FB NO_RETURN=1 value=0x1 + MODE!=2 SEG_OVD=6 -> emit 0x36 emit_type=numeric value=0x36 nbits=8 FB NO_RETURN=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_PREFIX_ENC; +/* no return */ if (iform&(1<<1)) { + xed_encoder_request_encode_emit(xes,8,0xf2); +} +/* no return */ if (iform&(1<<2)) { + xed_encoder_request_encode_emit(xes,8,0xf3); +} +/* no return */ if (iform&(1<<3)) { + xed_encoder_request_encode_emit(xes,8,0x66); +} +/* no return */ if (iform&(1<<4)) { + xed_encoder_request_encode_emit(xes,8,0x67); +} +/* no return */ if (iform&(1<<5)) { + xed_encoder_request_encode_emit(xes,8,0xf0); +} +/* no return */ if (iform&(1<<6)) { + xed_encoder_request_encode_emit(xes,8,0x64); +} +/* no return */ if (iform&(1<<7)) { + xed_encoder_request_encode_emit(xes,8,0x65); +} +/* no return */ if (iform&(1<<8)) { + xed_encoder_request_encode_emit(xes,8,0x2e); +} +/* no return */ if (iform&(1<<9)) { + xed_encoder_request_encode_emit(xes,8,0x3e); +} +/* no return */ if (iform&(1<<10)) { + xed_encoder_request_encode_emit(xes,8,0x3e); +} +/* no return */ if (iform&(1<<11)) { + xed_encoder_request_encode_emit(xes,8,0x2e); +} +/* no return */ if (iform&(1<<12)) { + xed_encoder_request_encode_emit(xes,8,0x2e); +} +/* no return */ if (iform&(1<<13)) { + xed_encoder_request_encode_emit(xes,8,0x3e); +} +/* no return */ if (iform&(1<<14)) { + xed_encoder_request_encode_emit(xes,8,0x3e); +} +/* no return */ if (iform&(1<<15)) { + xed_encoder_request_encode_emit(xes,8,0x3e); +} +/* no return */ if (iform&(1<<16)) { + xed_encoder_request_encode_emit(xes,8,0x26); +} +/* no return */ if (iform&(1<<17)) { + xed_encoder_request_encode_emit(xes,8,0x36); +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_DF64_EMIT(xed_encoder_request_t* xes) +{ +/* DF64():: + MODE=2 -> FB DF64=1 value=0x1 + MODE=0 -> nothing + MODE=1 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_OSZ_NONTERM_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* OSZ_NONTERM_ENC():: + VEXVALID=0 MODE=0 EOSZ=2 DF32=0 -> FB OSZ=1 value=0x1 + VEXVALID=0 MODE=1 EOSZ=1 -> FB OSZ=1 value=0x1 + VEXVALID=0 MODE=2 EOSZ=1 -> FB OSZ=1 value=0x1 + VEXVALID=0 MODE=2 EOSZ=3 DF64=0 -> FB REXW=1 value=0x1 + VEXVALID=0 MODE=0 EOSZ=1 -> nothing + VEXVALID=0 MODE=0 EOSZ=2 DF32=1 -> nothing + VEXVALID=0 MODE=1 EOSZ=2 -> nothing + VEXVALID=0 MODE=2 EOSZ=2 DF64=0 -> nothing + VEXVALID=0 MODE=2 EOSZ=3 DF64=1 -> nothing + VEXVALID=0 MODE=2 EOSZ=2 DF64=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_REFINING66_EMIT(xed_encoder_request_t* xes) +{ +/* REFINING66():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_IGNORE66_EMIT(xed_encoder_request_t* xes) +{ +/* IGNORE66():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_IMMUNE66_EMIT(xed_encoder_request_t* xes) +{ +/* IMMUNE66():: + MODE=0 -> FB EOSZ=2 value=0x2 FB DF32=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_IMMUNE66_LOOP64_EMIT(xed_encoder_request_t* xes) +{ +/* IMMUNE66_LOOP64():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_IMMUNE_REXW_EMIT(xed_encoder_request_t* xes) +{ +/* IMMUNE_REXW():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_CR_WIDTH_EMIT(xed_encoder_request_t* xes) +{ +/* CR_WIDTH():: + MODE=0 -> FB DF32=1 value=0x1 FB EOSZ=2 value=0x2 + MODE=2 -> FB DF64=1 value=0x1 FB EOSZ=3 value=0x3 + MODE=1 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_FORCE64_EMIT(xed_encoder_request_t* xes) +{ +/* FORCE64():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_BRANCH_HINT_EMIT(xed_encoder_request_t* xes) +{ +/* BRANCH_HINT():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_CET_NO_TRACK_EMIT(xed_encoder_request_t* xes) +{ +/* CET_NO_TRACK():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_VEXED_REX_EMIT(xed_encoder_request_t* xes) +{ +/* VEXED_REX():: + VEXVALID=3 -> nt NT[XOP_ENC] + VEXVALID=0 -> nt NT[REX_PREFIX_ENC] + VEXVALID=1 -> nt NT[NEWVEX_ENC] + VEXVALID=2 -> nt NT[EVEX_ENC] + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEXED_REX; +/* 4 */ if (iform==4) { + xed_encode_nonterminal_XOP_ENC_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encode_nonterminal_REX_PREFIX_ENC_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encode_nonterminal_NEWVEX_ENC_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encode_nonterminal_EVEX_ENC_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_XOP_TYPE_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* XOP_TYPE_ENC():: + MAP=8 -> emit 0x8F emit_type=numeric value=0x8f nbits=8 + MAP=9 -> emit 0x8F emit_type=numeric value=0x8f nbits=8 + MAP=10 -> emit 0x8F emit_type=numeric value=0x8f nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_XOP_TYPE_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,0x8f); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,8,0x8f); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,8,0x8f); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_XOP_MAP_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* XOP_MAP_ENC():: + MAP=8 REXW[w]=* -> emit 0b0_1000 emit_type=numeric value=0x8 nbits=5 emit w emit_type=letters nbits=1 + MAP=9 REXW[w]=* -> emit 0b0_1001 emit_type=numeric value=0x9 nbits=5 emit w emit_type=letters nbits=1 + MAP=10 REXW[w]=* -> emit 0b0_1010 emit_type=numeric value=0xa nbits=5 emit w emit_type=letters nbits=1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_XOP_MAP_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,5,0x8); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,5,0x9); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,5,0xa); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_XOP_REXXB_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* XOP_REXXB_ENC():: + MODE=2 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2 + MODE=2 REXX=1 REXB=0 -> emit 0b01 emit_type=numeric value=0x1 nbits=2 + MODE=2 REXX=0 REXB=1 -> emit 0b10 emit_type=numeric value=0x2 nbits=2 + MODE=2 REXX=1 REXB=1 -> emit 0b00 emit_type=numeric value=0x0 nbits=2 + MODE!=2 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2 + MODE!=2 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE!=2 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE!=2 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_XOP_REXXB_ENC; +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,2,0x3); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 11 */ if (iform==11) { + xed_encoder_request_encode_emit(xes,2,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + xed_encoder_request_encode_emit(xes,2,0x2); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 15 */ if (iform==15) { + xed_encoder_request_encode_emit(xes,2,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,2,0x3); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_BND_R_CHECK_EMIT(xed_encoder_request_t* xes) +{ +/* BND_R_CHECK():: + REXR=0 REG=0x0 -> nothing + REXR=0 REG=0x1 -> nothing + REXR=0 REG=0x2 -> nothing + REXR=0 REG=0x3 -> nothing + REXR=0 REG=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=0 REG=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=0 REG=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=0 REG=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x0 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x2 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x3 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXR=1 REG=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_BND_B_CHECK_EMIT(xed_encoder_request_t* xes) +{ +/* BND_B_CHECK():: + REXB=0 RM=0x0 -> nothing + REXB=0 RM=0x1 -> nothing + REXB=0 RM=0x2 -> nothing + REXB=0 RM=0x3 -> nothing + REXB=0 RM=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=0 RM=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=0 RM=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=0 RM=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x0 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x2 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x3 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x4 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x5 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x6 -> FB ERROR=XED_ERROR_GENERAL_ERROR + REXB=1 RM=0x7 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_VEX_TYPE_ENC_BIND(xed_encoder_request_t* xes) +{ +/* VEX_TYPE_ENC():: + REXX=1 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + REXB=1 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + MAP=0 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + MAP=2 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + MAP=3 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + REXW=1 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + */ +xed_uint_t okay=1; +xed_uint_t conditions_satisfied=0; +conditions_satisfied = (xed3_operand_get_rexx(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,1); + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=1; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_rexb(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,1); + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=2; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_map(xes) == 0); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,1); + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=3; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_map(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,1); + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=4; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_map(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,1); + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=5; + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_rexw(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,1); + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=6; + if (okay) return 1; +} +conditions_satisfied = 1; +if (conditions_satisfied) { + okay=1; + xed3_operand_set_vex_c4(xes,0); +/* FIXME action code not done yet for return 1*/ + xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC=0; + if (okay) return 1; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) conditions_satisfied; +} +xed_uint_t xed_encode_nonterminal_VEX_TYPE_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VEX_TYPE_ENC():: + REXX=1 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + REXB=1 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + MAP=0 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + MAP=2 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + MAP=3 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + REXW=1 -> emit 0xC4 emit_type=numeric value=0xc4 nbits=8 FB VEX_C4=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEX_TYPE_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,0xc4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,8,0xc4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,8,0xc4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,8,0xc4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,8,0xc4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 6 */ if (iform==6) { + xed_encoder_request_encode_emit(xes,8,0xc4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + xed_encoder_request_encode_emit(xes,8,0xc5); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VEX_REXR_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VEX_REXR_ENC():: + MODE=2 REXR=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1 + MODE=2 REXR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE!=2 REXR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE!=2 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEX_REXR_ENC; +/* 7 */ if (iform==7) { + xed_encoder_request_encode_emit(xes,1,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VEX_REXXB_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VEX_REXXB_ENC():: + MODE=2 VEX_C4=1 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2 + MODE=2 VEX_C4=1 REXX=1 REXB=0 -> emit 0b01 emit_type=numeric value=0x1 nbits=2 + MODE=2 VEX_C4=1 REXX=0 REXB=1 -> emit 0b10 emit_type=numeric value=0x2 nbits=2 + MODE=2 VEX_C4=1 REXX=1 REXB=1 -> emit 0b00 emit_type=numeric value=0x0 nbits=2 + MODE!=2 VEX_C4=1 REXX=0 REXB=0 -> emit 0b11 emit_type=numeric value=0x3 nbits=2 + MODE!=2 VEX_C4=1 REXX=1 REXB=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE!=2 VEX_C4=1 REXX=0 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + MODE!=2 VEX_C4=1 REXX=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEX_REXXB_ENC; +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,2,0x3); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 11 */ if (iform==11) { + xed_encoder_request_encode_emit(xes,2,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + xed_encoder_request_encode_emit(xes,2,0x2); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 15 */ if (iform==15) { + xed_encoder_request_encode_emit(xes,2,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,2,0x3); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VEX_MAP_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VEX_MAP_ENC():: + VEX_C4=1 MAP=0 REXW[w]=* -> emit 0b0_0000 emit_type=numeric value=0x0 nbits=5 emit w emit_type=letters nbits=1 + VEX_C4=1 MAP=1 REXW[w]=* -> emit 0b0_0001 emit_type=numeric value=0x1 nbits=5 emit w emit_type=letters nbits=1 + VEX_C4=1 MAP=2 REXW[w]=* -> emit 0b0_0010 emit_type=numeric value=0x2 nbits=5 emit w emit_type=letters nbits=1 + VEX_C4=1 MAP=3 REXW[w]=* -> emit 0b0_0011 emit_type=numeric value=0x3 nbits=5 emit w emit_type=letters nbits=1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEX_MAP_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,5,0x0); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,5,0x1); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,5,0x2); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,5,0x3); + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VEX_REG_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VEX_REG_ENC():: + MODE=2 VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit u_ddd emit_type=letters nbits=4 + MODE!=2 VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit 1_ddd emit_type=letters nbits=4 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEX_REG_ENC; +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_vexdest3(xes)<< 3)|(xed3_operand_get_vexdest210(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,4, (1 << 3)| (((xed3_operand_get_vexdest210(xes) >> 2) & 1) << 2)| (((xed3_operand_get_vexdest210(xes) >> 1) & 1) << 1)| (xed3_operand_get_vexdest210(xes) & 1) ); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VEX_ESCVL_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VEX_ESCVL_ENC():: + VL=0 VEX_PREFIX=0 -> emit 0b000 emit_type=numeric value=0x0 nbits=3 + VL=0 VEX_PREFIX=1 -> emit 0b001 emit_type=numeric value=0x1 nbits=3 + VL=0 VEX_PREFIX=3 -> emit 0b010 emit_type=numeric value=0x2 nbits=3 + VL=0 VEX_PREFIX=2 -> emit 0b011 emit_type=numeric value=0x3 nbits=3 + VL=1 VEX_PREFIX=0 -> emit 0b100 emit_type=numeric value=0x4 nbits=3 + VL=1 VEX_PREFIX=1 -> emit 0b101 emit_type=numeric value=0x5 nbits=3 + VL=1 VEX_PREFIX=3 -> emit 0b110 emit_type=numeric value=0x6 nbits=3 + VL=1 VEX_PREFIX=2 -> emit 0b111 emit_type=numeric value=0x7 nbits=3 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VEX_ESCVL_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,3,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,3,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,3,0x2); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,3,0x3); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,3,0x4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 6 */ if (iform==6) { + xed_encoder_request_encode_emit(xes,3,0x5); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 8 */ if (iform==8) { + xed_encoder_request_encode_emit(xes,3,0x6); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + xed_encoder_request_encode_emit(xes,3,0x7); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_SE_IMM8_EMIT(xed_encoder_request_t* xes) +{ +/* SE_IMM8():: + DUMMY=0 ESRC[ssss]=* UIMM0[dddd]=* -> emit ssss_dddd emit_type=letters nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SE_IMM8; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_esrc(xes)<< 4)|(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VMODRM_MOD_ENCODE_BIND(xed_encoder_request_t* xes) +{ +/* VMODRM_MOD_ENCODE():: + EASZ=2 DISP_WIDTH=8 -> FB MOD=1 value=0x1 + EASZ=2 DISP_WIDTH=32 BASE0=@ -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=32 BASE0=@ -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RAX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RCX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSP -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSI -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDI -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R8 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R9 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R10 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R11 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R12 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R14 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R15 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_AX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_CX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SI EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DI EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SP EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BP EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + */ +xed_uint_t okay=1; +xed_uint_t conditions_satisfied=0; +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 8); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_INVALID); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_AX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EAX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RAX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_BX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EBX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RBX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_CX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_ECX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RCX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_DX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EDX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RDX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_SI) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_ESI) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RSI) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_DI) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EDI) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RDI) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_SP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_ESP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RSP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R8W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R8D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R8) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R9W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R9D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R9) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R10W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R10D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R10) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R11W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R11D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R11) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R12W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R12D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R12) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R14W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R14D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R14) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R15W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R15D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R15) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_AX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EAX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RAX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_BX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EBX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RBX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_CX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_ECX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RCX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_DX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EDX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RDX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_SI) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_ESI) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RSI) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_DI) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EDI) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RDI) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_SP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_ESP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RSP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R8W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R8D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R8) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R9W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R9D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R9) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R10W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R10D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R10) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R11W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R11D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R11) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R12W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R12D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R12) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R14W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R14D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R14) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R15W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R15D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R15) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RAX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RBX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RCX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RDX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RSP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RBP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RSI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_RDI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R8); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R9); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R10); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R11); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R12); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R13); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R14); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 8) && + (xed3_operand_get_base0(xes) == XED_REG_R15); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_AX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_EAX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RAX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_BX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_EBX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RBX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_CX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_ECX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RCX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_DX) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_EDX) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RDX) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_SI) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_ESI) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RSI) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_DI) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_EDI) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RDI) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_SP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_ESP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RSP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_BP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_EBP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_RBP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R8W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R8D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R8) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R9W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R9D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R9) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R10W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R10D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R10) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R11W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R11D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R11) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R12W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R12D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R12) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R13W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R13D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R13) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R14W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R14D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R14) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R15W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R15D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_base0(xes) == XED_REG_R15) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_EAX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_EBX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_ECX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_EDX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_ESP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_EBP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_ESI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 1) && + (xed3_operand_get_base0(xes) == XED_REG_EDI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_EAX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_EBX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_ECX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_EDX); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_ESP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_EBP); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_ESI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_EDI); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R8D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R9D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R10D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R11D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R12D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R13D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R14D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 32) && + (xed3_operand_get_mode(xes) == 2) && + (xed3_operand_get_base0(xes) == XED_REG_R15D); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,2); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_BP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EBP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RBP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R13W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R13D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 2) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R13) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_BP) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_EBP) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_RBP) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R13W) && + (xed3_operand_get_easz(xes) == 1); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R13D) && + (xed3_operand_get_easz(xes) == 2); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = (xed3_operand_get_easz(xes) == 3) && + (xed3_operand_get_disp_width(xes) == 0) && + (xed3_operand_get_base0(xes) == XED_REG_R13) && + (xed3_operand_get_easz(xes) == 3); +if (conditions_satisfied) { + okay=1; + xed3_operand_set_mod(xes,1); + xed3_operand_set_disp_width(xes,8); + xed3_operand_set_disp(xes,0); + if (okay) return 1; +} +conditions_satisfied = 1; +if (conditions_satisfied) { + okay=1; + xed3_operand_set_error(xes,XED_ERROR_GENERAL_ERROR); + return 0; /* error */ +/* FIXME action code not done yet for return 1*/ + if (okay) return 1; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) conditions_satisfied; +} +xed_uint_t xed_encode_nonterminal_VMODRM_MOD_ENCODE_EMIT(xed_encoder_request_t* xes) +{ +/* VMODRM_MOD_ENCODE():: + EASZ=2 DISP_WIDTH=8 -> FB MOD=1 value=0x1 + EASZ=2 DISP_WIDTH=32 BASE0=@ -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=32 BASE0=@ -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=2 DISP_WIDTH=0 MODE=2 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_AX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_CX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DX EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_DI EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_SP EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=0 value=0x0 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RAX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RCX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDX -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSP -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RBP -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RSI -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_RDI -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R8 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R9 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R10 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R11 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R12 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R13 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R14 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=8 BASE0=XED_REG_R15 -> FB MOD=1 value=0x1 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_AX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EAX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RAX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_CX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ECX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RCX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DX EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDX EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDX EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SI EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESI EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSI EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_DI EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EDI EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RDI EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_SP EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_ESP EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RSP EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_BP EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R8 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R9 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R10 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R11 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R12 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R14 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15W EASZ=1 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15D EASZ=2 -> FB MOD=2 value=0x2 + EASZ=3 DISP_WIDTH=32 BASE0=XED_REG_R15 EASZ=3 -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=1 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EAX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ECX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDX -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EBP -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_ESI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_EDI -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R8D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R9D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R10D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R11D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R12D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R13D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R14D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=32 MODE=2 BASE0=XED_REG_R15D -> FB MOD=2 value=0x2 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=2 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_BP EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_EBP EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_RBP EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13W EASZ=1 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13D EASZ=2 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + EASZ=3 DISP_WIDTH=0 BASE0=XED_REG_R13 EASZ=3 -> FB MOD=1 value=0x1 FB DISP_WIDTH=8 value=0x8 FB DISP=0 value=0x0 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-4.c b/CodeVirtualizer/build/obj/xed-encoder-4.c new file mode 100644 index 0000000..534bd04 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-4.c @@ -0,0 +1,1612 @@ +/// @file xed-encoder-4.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encoder.h" +#include "xed-encode-private.h" +#include "xed-enc-operand-lu.h" +#include "xed-operand-accessors.h" +xed_uint_t xed_encode_nonterminal_VSIB_ENC_BASE_EMIT(xed_encoder_request_t* xes) +{ +/* VSIB_ENC_BASE():: + BASE0=XED_REG_AX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 + BASE0=XED_REG_EAX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 + BASE0=XED_REG_RAX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=0 value=0x0 + BASE0=XED_REG_CX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 + BASE0=XED_REG_ECX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 + BASE0=XED_REG_RCX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=1 value=0x1 + BASE0=XED_REG_DX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 + BASE0=XED_REG_EDX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 + BASE0=XED_REG_RDX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=2 value=0x2 + BASE0=XED_REG_BX EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 + BASE0=XED_REG_EBX EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 + BASE0=XED_REG_RBX EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=3 value=0x3 + BASE0=XED_REG_SP EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 + BASE0=XED_REG_ESP EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 + BASE0=XED_REG_RSP EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=4 value=0x4 + BASE0=XED_REG_SI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 + BASE0=XED_REG_ESI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 + BASE0=XED_REG_RSI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=6 value=0x6 + BASE0=XED_REG_DI EASZ=1 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 + BASE0=XED_REG_EDI EASZ=2 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 + BASE0=XED_REG_RDI EASZ=3 -> FB REXB=0 value=0x0 FB SIBBASE=7 value=0x7 + BASE0=XED_REG_R8W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 + BASE0=XED_REG_R8D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 + BASE0=XED_REG_R8 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=0 value=0x0 + BASE0=XED_REG_R9W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 + BASE0=XED_REG_R9D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 + BASE0=XED_REG_R9 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=1 value=0x1 + BASE0=XED_REG_R10W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 + BASE0=XED_REG_R10D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 + BASE0=XED_REG_R10 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=2 value=0x2 + BASE0=XED_REG_R11W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 + BASE0=XED_REG_R11D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 + BASE0=XED_REG_R11 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=3 value=0x3 + BASE0=XED_REG_R12W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 + BASE0=XED_REG_R12D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 + BASE0=XED_REG_R12 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=4 value=0x4 + BASE0=XED_REG_R14W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 + BASE0=XED_REG_R14D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 + BASE0=XED_REG_R14 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=6 value=0x6 + BASE0=XED_REG_R15W EASZ=1 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 + BASE0=XED_REG_R15D EASZ=2 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 + BASE0=XED_REG_R15 EASZ=3 -> FB REXB=1 value=0x1 FB SIBBASE=7 value=0x7 + BASE0=@ -> nt NT[DISP_WIDTH_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 + BASE0=XED_REG_BP EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 + BASE0=XED_REG_EBP EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 + BASE0=XED_REG_RBP EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=0 value=0x0 FB SIBBASE=5 value=0x5 + BASE0=XED_REG_R13W EASZ=1 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 + BASE0=XED_REG_R13D EASZ=2 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 + BASE0=XED_REG_R13 EASZ=3 -> nt NT[DISP_WIDTH_8_32] FB REXB=1 value=0x1 FB SIBBASE=5 value=0x5 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VSIB_ENC_BASE; +/* 91 */ if (iform==91) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 14 */ if (iform==14) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 41 */ if (iform==41) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 95 */ if (iform==95) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 18 */ if (iform==18) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 45 */ if (iform==45) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 22 */ if (iform==22) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 49 */ if (iform==49) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 8 */ if (iform==8) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 26 */ if (iform==26) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 53 */ if (iform==53) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 12 */ if (iform==12) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 30 */ if (iform==30) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 57 */ if (iform==57) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 20 */ if (iform==20) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 38 */ if (iform==38) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 65 */ if (iform==65) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 24 */ if (iform==24) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 42 */ if (iform==42) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 69 */ if (iform==69) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 28 */ if (iform==28) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 46 */ if (iform==46) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 73 */ if (iform==73) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 32 */ if (iform==32) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 50 */ if (iform==50) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 77 */ if (iform==77) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 36 */ if (iform==36) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 54 */ if (iform==54) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 81 */ if (iform==81) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 40 */ if (iform==40) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 58 */ if (iform==58) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 85 */ if (iform==85) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 44 */ if (iform==44) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 62 */ if (iform==62) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 89 */ if (iform==89) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 52 */ if (iform==52) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 70 */ if (iform==70) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 97 */ if (iform==97) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 56 */ if (iform==56) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 74 */ if (iform==74) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 101 */ if (iform==101) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 71 */ if (iform==71) { + xed_encode_nonterminal_DISP_WIDTH_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 16 */ if (iform==16) { + xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 34 */ if (iform==34) { + xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 61 */ if (iform==61) { + xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 48 */ if (iform==48) { + xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 66 */ if (iform==66) { + xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 93 */ if (iform==93) { + xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xes); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VSIB_ENC_SCALE_EMIT(xed_encoder_request_t* xes) +{ +/* VSIB_ENC_SCALE():: + SCALE=0 -> FB SIBSCALE=0 value=0x0 + SCALE=1 -> FB SIBSCALE=0 value=0x0 + SCALE=2 -> FB SIBSCALE=1 value=0x1 + SCALE=4 -> FB SIBSCALE=2 value=0x2 + SCALE=8 -> FB SIBSCALE=3 value=0x3 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_VSIB_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* VSIB_ENC():: + DUMMY=0 SIBBASE[bbb]=* SIBINDEX[iii]=* SIBSCALE[ss]=* -> emit ss_iii_bbb emit_type=letters nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_VSIB_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_sibscale(xes)<< 6)|(xed3_operand_get_sibindex(xes)<< 3)|(xed3_operand_get_sibbase(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_VSIB_ENC_INDEX_XMM_EMIT(xed_encoder_request_t* xes) +{ +/* VSIB_ENC_INDEX_XMM():: + INDEX=XED_REG_XMM0 -> FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_XMM1 -> FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_XMM2 -> FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_XMM3 -> FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_XMM4 -> FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_XMM5 -> FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_XMM6 -> FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_XMM7 -> FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_XMM8 -> FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_XMM9 -> FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_XMM10 -> FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_XMM11 -> FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_XMM12 -> FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_XMM13 -> FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_XMM14 -> FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_XMM15 -> FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_VSIB_ENC_INDEX_YMM_EMIT(xed_encoder_request_t* xes) +{ +/* VSIB_ENC_INDEX_YMM():: + INDEX=XED_REG_YMM0 -> FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_YMM1 -> FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_YMM2 -> FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_YMM3 -> FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_YMM4 -> FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_YMM5 -> FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_YMM6 -> FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_YMM7 -> FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_YMM8 -> FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_YMM9 -> FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_YMM10 -> FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_YMM11 -> FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_YMM12 -> FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_YMM13 -> FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_YMM14 -> FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_YMM15 -> FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_DISP_WIDTH_8_32_EMIT(xed_encoder_request_t* xes) +{ +/* DISP_WIDTH_8_32():: + DISP_WIDTH=8 -> nothing + DISP_WIDTH=32 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_4X_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE1_4X():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_EVEX_62_REXR_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_62_REXR_ENC():: + MODE=2 REXR=1 -> emit 0x62 emit_type=numeric value=0x62 nbits=8 emit 0b0 emit_type=numeric value=0x0 nbits=1 + MODE=2 REXR=0 -> emit 0x62 emit_type=numeric value=0x62 nbits=8 emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXR=0 -> emit 0x62 emit_type=numeric value=0x62 nbits=8 emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_62_REXR_ENC; +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,8,0x62); + xed_encoder_request_encode_emit(xes,1,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,8,0x62); + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,8,0x62); + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_REXX_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_REXX_ENC():: + MODE=2 REXX=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1 + MODE=2 REXX=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXX=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXX=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_REXX_ENC; +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,1,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_REXB_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_REXB_ENC():: + MODE=2 REXB=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1 + MODE=2 REXB=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXB=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXB=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_REXB_ENC; +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,1,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_REXRR_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_REXRR_ENC():: + MODE=2 REXRR=1 -> emit 0b0 emit_type=numeric value=0x0 nbits=1 + MODE=2 REXRR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXRR=0 -> emit 0b1 emit_type=numeric value=0x1 nbits=1 + MODE=1 REXRR=1 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_REXRR_ENC; +/* 5 */ if (iform==5) { + xed_encoder_request_encode_emit(xes,1,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,1,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_MAP_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_MAP_ENC():: + MAP=0 -> emit 0b0000 emit_type=numeric value=0x0 nbits=4 + MAP=1 -> emit 0b0001 emit_type=numeric value=0x1 nbits=4 + MAP=2 -> emit 0b0010 emit_type=numeric value=0x2 nbits=4 + MAP=3 -> emit 0b0011 emit_type=numeric value=0x3 nbits=4 + MAP=5 -> emit 0b0101 emit_type=numeric value=0x5 nbits=4 + MAP=6 -> emit 0b0110 emit_type=numeric value=0x6 nbits=4 + MAP=4 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_MAP_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,4,0x0); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,4,0x1); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,4,0x2); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,4,0x3); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 6 */ if (iform==6) { + xed_encoder_request_encode_emit(xes,4,0x5); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 7 */ if (iform==7) { + xed_encoder_request_encode_emit(xes,4,0x6); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_REXW_VVVV_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_REXW_VVVV_ENC():: + DUMMY=0 REXW[w]=* VEXDEST3[u]=* VEXDEST210[ddd]=* -> emit w emit_type=letters nbits=1 emit u_ddd emit_type=letters nbits=4 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_REXW_VVVV_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,1,(xed3_operand_get_rexw(xes))); + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_vexdest3(xes)<< 3)|(xed3_operand_get_vexdest210(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_UPP_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_UPP_ENC():: + VEX_PREFIX=0 -> emit 0b100 emit_type=numeric value=0x4 nbits=3 + VEX_PREFIX=1 -> emit 0b101 emit_type=numeric value=0x5 nbits=3 + VEX_PREFIX=3 -> emit 0b110 emit_type=numeric value=0x6 nbits=3 + VEX_PREFIX=2 -> emit 0b111 emit_type=numeric value=0x7 nbits=3 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_EVEX_UPP_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,3,0x4); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,3,0x5); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,3,0x6); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,3,0x7); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_EVEX_LL_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* EVEX_LL_ENC():: + ROUNDC=0 SAE=0 VL=0 -> FB LLRC=0 value=0x0 + ROUNDC=0 SAE=0 VL=1 -> FB LLRC=1 value=0x1 + ROUNDC=0 SAE=0 VL=2 -> FB LLRC=2 value=0x2 + ROUNDC=0 SAE=1 VL=0 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1 + ROUNDC=1 SAE=1 VL=0 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1 + ROUNDC=2 SAE=1 VL=0 -> FB LLRC=1 value=0x1 FB BCRC=1 value=0x1 + ROUNDC=3 SAE=1 VL=0 -> FB LLRC=2 value=0x2 FB BCRC=1 value=0x1 + ROUNDC=4 SAE=1 VL=0 -> FB LLRC=3 value=0x3 FB BCRC=1 value=0x1 + ROUNDC=0 SAE=1 VL=2 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1 + ROUNDC=1 SAE=1 VL=2 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1 + ROUNDC=2 SAE=1 VL=2 -> FB LLRC=1 value=0x1 FB BCRC=1 value=0x1 + ROUNDC=3 SAE=1 VL=2 -> FB LLRC=2 value=0x2 FB BCRC=1 value=0x1 + ROUNDC=4 SAE=1 VL=2 -> FB LLRC=3 value=0x3 FB BCRC=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_AVX512_EVEX_BYTE3_ENC_EMIT(xed_encoder_request_t* xes) +{ +/* AVX512_EVEX_BYTE3_ENC():: + ZEROING[z]=* LLRC[nn]=* BCRC[b]=* VEXDEST4=0 MASK[aaa]=* -> emit z_nn_b emit_type=letters nbits=4 emit 0b1 emit_type=numeric value=0x1 nbits=1 emit aaa emit_type=letters nbits=3 + ZEROING[z]=* LLRC[nn]=* BCRC[b]=* VEXDEST4=1 MASK[aaa]=* -> emit z_nn_b emit_type=letters nbits=4 emit 0b0 emit_type=numeric value=0x0 nbits=1 emit aaa emit_type=letters nbits=3 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_AVX512_EVEX_BYTE3_ENC; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_zeroing(xes)<< 3)|(xed3_operand_get_llrc(xes)<< 1)|(xed3_operand_get_bcrc(xes))); + xed_encoder_request_encode_emit(xes,1,0x1); + xed_encoder_request_encode_emit(xes,3,(xed3_operand_get_mask(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,4,(xed3_operand_get_zeroing(xes)<< 3)|(xed3_operand_get_llrc(xes)<< 1)|(xed3_operand_get_bcrc(xes))); + xed_encoder_request_encode_emit(xes,1,0x0); + xed_encoder_request_encode_emit(xes,3,(xed3_operand_get_mask(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_AVX512_ROUND_EMIT(xed_encoder_request_t* xes) +{ +/* AVX512_ROUND():: + ROUNDC=1 -> FB LLRC=0 value=0x0 FB BCRC=1 value=0x1 + ROUNDC=2 -> FB LLRC=1 value=0x1 FB BCRC=1 value=0x1 + ROUNDC=3 -> FB LLRC=2 value=0x2 FB BCRC=1 value=0x1 + ROUNDC=4 -> FB LLRC=3 value=0x3 FB BCRC=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_SAE_EMIT(xed_encoder_request_t* xes) +{ +/* SAE():: + SAE=1 -> FB BCRC=1 value=0x1 + SAE=0 -> FB BCRC=0 value=0x0 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_128_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_128_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_64_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_64_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_32_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_32_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_16_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_16_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_8_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_8_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_4_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_4_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_2_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_2_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ESIZE_1_BITS_EMIT(xed_encoder_request_t* xes) +{ +/* ESIZE_1_BITS():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_MOVDDUP_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_MOVDDUP():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_FULLMEM_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_FULLMEM():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_HALFMEM_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_HALFMEM():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_QUARTERMEM_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_QUARTERMEM():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_EIGHTHMEM_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_EIGHTHMEM():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_BYTE_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_READER_BYTE():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_WORD_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_READER_WORD():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_D_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_LDOP_D():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_Q_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_LDOP_Q():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_BYTE_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_STORE_BYTE():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_WORD_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_STORE_WORD():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_BYTE_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE1_BYTE():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_WORD_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE1_WORD():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_SCALAR_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_SCALAR():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_SUBDWORD_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE1_SUBDWORD():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_READER():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_READER_SUBDWORD_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_READER_SUBDWORD():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_LDOP_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_LDOP():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_STORE():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GPR_WRITER_STORE_SUBDWORD_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GPR_WRITER_STORE_SUBDWORD():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_MEM128_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_MEM128():: + BCAST!=0 -> FB ERROR=XED_ERROR_GENERAL_ERROR + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE1_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE1():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_GSCAT_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_GSCAT():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE2_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE2():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE4_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE4():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_TUPLE8_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_TUPLE8():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_FULL_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_FULL():: + BCAST!=0 -> FB BCRC=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_HALF_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_HALF():: + BCAST!=0 -> FB BCRC=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_FIX_ROUND_LEN512_EMIT(xed_encoder_request_t* xes) +{ +/* FIX_ROUND_LEN512():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_FIX_ROUND_LEN128_EMIT(xed_encoder_request_t* xes) +{ +/* FIX_ROUND_LEN128():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_UISA_ENC_INDEX_ZMM_EMIT(xed_encoder_request_t* xes) +{ +/* UISA_ENC_INDEX_ZMM():: + INDEX=XED_REG_ZMM0 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_ZMM1 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_ZMM2 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_ZMM3 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_ZMM4 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_ZMM5 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_ZMM6 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_ZMM7 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_ZMM8 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_ZMM9 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_ZMM10 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_ZMM11 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_ZMM12 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_ZMM13 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_ZMM14 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_ZMM15 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_ZMM16 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_ZMM17 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_ZMM18 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_ZMM19 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_ZMM20 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_ZMM21 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_ZMM22 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_ZMM23 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_ZMM24 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_ZMM25 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_ZMM26 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_ZMM27 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_ZMM28 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_ZMM29 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_ZMM30 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_ZMM31 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_UISA_ENC_INDEX_YMM_EMIT(xed_encoder_request_t* xes) +{ +/* UISA_ENC_INDEX_YMM():: + INDEX=XED_REG_YMM0 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_YMM1 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_YMM2 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_YMM3 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_YMM4 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_YMM5 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_YMM6 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_YMM7 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_YMM8 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_YMM9 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_YMM10 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_YMM11 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_YMM12 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_YMM13 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_YMM14 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_YMM15 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_YMM16 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_YMM17 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_YMM18 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_YMM19 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_YMM20 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_YMM21 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_YMM22 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_YMM23 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_YMM24 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_YMM25 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_YMM26 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_YMM27 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_YMM28 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_YMM29 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_YMM30 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_YMM31 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_UISA_ENC_INDEX_XMM_EMIT(xed_encoder_request_t* xes) +{ +/* UISA_ENC_INDEX_XMM():: + INDEX=XED_REG_XMM0 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_XMM1 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_XMM2 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_XMM3 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_XMM4 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_XMM5 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_XMM6 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_XMM7 -> FB VEXDEST4=0 value=0x0 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_XMM8 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_XMM9 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_XMM10 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_XMM11 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_XMM12 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_XMM13 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_XMM14 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_XMM15 -> FB VEXDEST4=0 value=0x0 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_XMM16 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_XMM17 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_XMM18 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_XMM19 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_XMM20 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_XMM21 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_XMM22 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_XMM23 -> FB VEXDEST4=1 value=0x1 FB REXX=0 value=0x0 FB SIBINDEX=7 value=0x7 + INDEX=XED_REG_XMM24 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=0 value=0x0 + INDEX=XED_REG_XMM25 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=1 value=0x1 + INDEX=XED_REG_XMM26 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=2 value=0x2 + INDEX=XED_REG_XMM27 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=3 value=0x3 + INDEX=XED_REG_XMM28 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=4 value=0x4 + INDEX=XED_REG_XMM29 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=5 value=0x5 + INDEX=XED_REG_XMM30 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=6 value=0x6 + INDEX=XED_REG_XMM31 -> FB VEXDEST4=1 value=0x1 FB REXX=1 value=0x1 FB SIBINDEX=7 value=0x7 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_NELEM_QUARTER_EMIT(xed_encoder_request_t* xes) +{ +/* NELEM_QUARTER():: + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ASZ_NONTERM_EMIT(xed_encoder_request_t* xes) +{ +/* ASZ_NONTERM():: + EASZ=1 MODE=0 -> FB ASZ=0 value=0x0 + EASZ=2 MODE=0 -> FB ASZ=1 value=0x1 + EASZ=2 MODE=1 -> FB ASZ=0 value=0x0 + EASZ=1 MODE=1 -> FB ASZ=1 value=0x1 + EASZ=3 MODE=2 -> FB ASZ=0 value=0x0 + EASZ=2 MODE=2 -> FB ASZ=1 value=0x1 + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_ONE_EMIT(xed_encoder_request_t* xes) +{ +/* ONE():: + IMM_WIDTH=8 UIMM0=1 MODE=0 -> nothing + IMM_WIDTH=8 UIMM0=1 MODE=1 -> nothing + IMM_WIDTH=8 UIMM0=1 MODE=2 -> nothing + */ +xed_uint_t okay=1; +return 1; +(void) okay; +(void) xes; +} +xed_uint_t xed_encode_nonterminal_UIMMv_EMIT(xed_encoder_request_t* xes) +{ +/* UIMMv():: + IMM_WIDTH=16 EOSZ=1 UIMM0[iiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiii emit_type=letters nbits=16 + IMM_WIDTH=32 EOSZ=2 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32 + IMM_WIDTH=64 EOSZ=3 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=64 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_UIMMv; +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,64,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_SIMMz_EMIT(xed_encoder_request_t* xes) +{ +/* SIMMz():: + IMM_WIDTH=16 EOSZ=1 UIMM0[iiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiii emit_type=letters nbits=16 FB IMM0SIGNED=1 value=0x1 + IMM_WIDTH=32 EOSZ=2 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32 FB IMM0SIGNED=1 value=0x1 + IMM_WIDTH=32 EOSZ=3 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32 FB IMM0SIGNED=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SIMMz; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_SIMM8_EMIT(xed_encoder_request_t* xes) +{ +/* SIMM8():: + IMM_WIDTH=8 UIMM0[iiiiiiii]=* -> emit uimm0=iiiiiiii emit_type=letters nbits=8 FB IMM0SIGNED=1 value=0x1 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_SIMM8; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_UIMM8_EMIT(xed_encoder_request_t* xes) +{ +/* UIMM8():: + IMM_WIDTH=8 UIMM0[iiiiiiii]=* -> emit uimm0=iiiiiiii emit_type=letters nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_UIMM8; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_UIMM8_1_EMIT(xed_encoder_request_t* xes) +{ +/* UIMM8_1():: + DUMMY=0 UIMM1[iiiiiiii]=* -> emit uimm1=iiiiiiii emit_type=letters nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_UIMM8_1; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_uimm1(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_UIMM16_EMIT(xed_encoder_request_t* xes) +{ +/* UIMM16():: + IMM_WIDTH=16 UIMM0[iiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiii emit_type=letters nbits=16 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_UIMM16; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_UIMM32_EMIT(xed_encoder_request_t* xes) +{ +/* UIMM32():: + IMM_WIDTH=32 UIMM0[iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii]=* -> emit uimm0=iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii emit_type=letters nbits=32 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_UIMM32; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_uimm0(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_BRDISP8_EMIT(xed_encoder_request_t* xes) +{ +/* BRDISP8():: + BRDISP_WIDTH=8 DISP[dddddddd]=* -> emit disp=dddddddd emit_type=letters nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_BRDISP8; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_BRDISP32_EMIT(xed_encoder_request_t* xes) +{ +/* BRDISP32():: + BRDISP_WIDTH=32 DISP[dddddddddddddddddddddddddddddddd]=* -> emit disp=dddddddddddddddddddddddddddddddd emit_type=letters nbits=32 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_BRDISP32; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_BRDISPz_EMIT(xed_encoder_request_t* xes) +{ +/* BRDISPz():: + BRDISP_WIDTH=16 EOSZ=1 DISP[dddddddddddddddd]=* -> emit disp=dddddddddddddddd emit_type=letters nbits=16 + BRDISP_WIDTH=32 EOSZ=2 DISP[dddddddddddddddddddddddddddddddd]=* -> emit disp=dddddddddddddddddddddddddddddddd emit_type=letters nbits=32 + BRDISP_WIDTH=32 EOSZ=3 DISP[dddddddddddddddddddddddddddddddd]=* -> emit disp=dddddddddddddddddddddddddddddddd emit_type=letters nbits=32 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_BRDISPz; +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MEMDISPv_EMIT(xed_encoder_request_t* xes) +{ +/* MEMDISPv():: + DISP_WIDTH=16 EASZ=1 DISP[aaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaa emit_type=letters nbits=16 + DISP_WIDTH=32 EASZ=2 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=32 + DISP_WIDTH=64 EASZ=3 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=64 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MEMDISPv; +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,64,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MEMDISP32_EMIT(xed_encoder_request_t* xes) +{ +/* MEMDISP32():: + DISP_WIDTH=32 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=32 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MEMDISP32; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MEMDISP16_EMIT(xed_encoder_request_t* xes) +{ +/* MEMDISP16():: + DISP_WIDTH=16 DISP[aaaaaaaaaaaaaaaa]=* -> emit disp=aaaaaaaaaaaaaaaa emit_type=letters nbits=16 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MEMDISP16; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MEMDISP8_EMIT(xed_encoder_request_t* xes) +{ +/* MEMDISP8():: + DISP_WIDTH=8 DISP[aaaaaaaa]=* -> emit disp=aaaaaaaa emit_type=letters nbits=8 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MEMDISP8; +/* 1 */ if (iform==1) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} +xed_uint_t xed_encode_nonterminal_MEMDISP_EMIT(xed_encoder_request_t* xes) +{ +/* MEMDISP():: + DISP_WIDTH=0 -> FB NEED_MEMDISP=0 value=0x0 + DISP_WIDTH=8 DISP[aaaaaaaa]=* -> FB NEED_MEMDISP=8 value=0x8 emit disp=aaaaaaaa emit_type=letters nbits=8 + DISP_WIDTH=16 DISP[aaaaaaaaaaaaaaaa]=* -> FB NEED_MEMDISP=16 value=0x10 emit disp=aaaaaaaaaaaaaaaa emit_type=letters nbits=16 + DISP_WIDTH=32 DISP[aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa]=* -> FB NEED_MEMDISP=32 value=0x20 emit disp=aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa emit_type=letters nbits=32 + */ +xed_uint_t okay=1; +unsigned int iform = xed_encoder_request_iforms(xes)->x_MEMDISP; +/* 1 */ if (iform==1) { + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 4 */ if (iform==4) { + xed_encoder_request_encode_emit(xes,8,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 2 */ if (iform==2) { + xed_encoder_request_encode_emit(xes,16,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +/* 3 */ if (iform==3) { + xed_encoder_request_encode_emit(xes,32,(xed3_operand_get_disp(xes))); + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +if (1) { /*otherwise*/ + if (xed3_operand_get_error(xes) != XED_ERROR_NONE) okay=0; + return okay; +} +return 0; /*pacify the compiler*/ +(void) okay; +(void) xes; +(void) iform; +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-gen-defs.h b/CodeVirtualizer/build/obj/xed-encoder-gen-defs.h new file mode 100644 index 0000000..4d63790 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-gen-defs.h @@ -0,0 +1,32 @@ +/// @file xed-encoder-gen-defs.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENCODER_GEN_DEFS_H) +# define XED_ENCODER_GEN_DEFS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#define XED_ENCODE_ORDER_MAX_ENTRIES 32 +#define XED_ENCODE_ORDER_MAX_OPERANDS 5 +#define XED_ENCODE_MAX_FB_PATTERNS 121 +#define XED_ENCODE_MAX_EMIT_PATTERNS 199 +#define XED_ENCODE_FB_VALUES_TABLE_SIZE 3880 +#define XED_ENCODE_MAX_IFORMS 7639 +#define XED_ENC_GROUPS 535 +#endif diff --git a/CodeVirtualizer/build/obj/xed-encoder-iforms-init.c b/CodeVirtualizer/build/obj/xed-encoder-iforms-init.c new file mode 100644 index 0000000..c6f3d4d --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-iforms-init.c @@ -0,0 +1,7666 @@ +/// @file xed-encoder-iforms-init.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-ild.h" +#include "xed-ild-enum.h" +const xed_encoder_iform_t xed_encode_iform_db[XED_ENCODE_MAX_IFORMS] = { + /*( 0) FADD*/ { 0, 0, 0xd8, 0}, + /*( 1) FADD*/ { 1, 1, 0xd8, 1}, + /*( 2) FADD*/ { 0, 0, 0xdc, 0}, + /*( 3) FADD*/ { 1, 1, 0xdc, 1}, + /*( 4) FMUL*/ { 0, 0, 0xd8, 3}, + /*( 5) FMUL*/ { 1, 1, 0xd8, 4}, + /*( 6) FMUL*/ { 0, 0, 0xdc, 3}, + /*( 7) FMUL*/ { 1, 1, 0xdc, 4}, + /*( 8) FCOMP*/ { 0, 0, 0xd8, 1}, + /*( 9) FCOMP*/ { 1, 1, 0xd8, 6}, + /*( 10) FCOMP*/ { 1, 1, 0xdc, 6}, + /*( 11) FCOMP*/ { 1, 1, 0xde, 8}, + /*( 12) FCOMP*/ { 0, 0, 0xdc, 1}, + /*( 13) FSUB*/ { 0, 0, 0xd8, 10}, + /*( 14) FSUB*/ { 1, 1, 0xd8, 11}, + /*( 15) FSUB*/ { 0, 0, 0xdc, 10}, + /*( 16) FSUB*/ { 1, 1, 0xdc, 13}, + /*( 17) FSUBR*/ { 0, 0, 0xd8, 14}, + /*( 18) FSUBR*/ { 1, 1, 0xd8, 13}, + /*( 19) FSUBR*/ { 0, 0, 0xdc, 14}, + /*( 20) FSUBR*/ { 1, 1, 0xdc, 11}, + /*( 21) FDIV*/ { 0, 0, 0xd8, 15}, + /*( 22) FDIV*/ { 1, 1, 0xd8, 16}, + /*( 23) FDIV*/ { 0, 0, 0xdc, 15}, + /*( 24) FDIV*/ { 1, 1, 0xdc, 18}, + /*( 25) FDIVR*/ { 0, 0, 0xd8, 19}, + /*( 26) FDIVR*/ { 1, 1, 0xd8, 18}, + /*( 27) FDIVR*/ { 0, 0, 0xdc, 19}, + /*( 28) FDIVR*/ { 1, 1, 0xdc, 16}, + /*( 29) FCOM*/ { 0, 0, 0xd8, 9}, + /*( 30) FCOM*/ { 0, 0, 0xdc, 9}, + /*( 31) FCOM*/ { 1, 1, 0xd8, 8}, + /*( 32) FCOM*/ { 1, 1, 0xdc, 8}, + /*( 33) FLD*/ { 0, 0, 0xd9, 0}, + /*( 34) FLD*/ { 1, 1, 0xd9, 1}, + /*( 35) FLD*/ { 0, 0, 0xdb, 14}, + /*( 36) FLD*/ { 0, 0, 0xdd, 0}, + /*( 37) FST*/ { 0, 0, 0xd9, 9}, + /*( 38) FST*/ { 0, 0, 0xdd, 9}, + /*( 39) FST*/ { 1, 1, 0xdd, 8}, + /*( 40) FSTP*/ { 0, 0, 0xd9, 1}, + /*( 41) FSTP*/ { 0, 0, 0xdb, 19}, + /*( 42) FSTP*/ { 0, 0, 0xdd, 1}, + /*( 43) FSTP*/ { 1, 1, 0xdd, 6}, + /*( 44) FSTP*/ { 1, 1, 0xdf, 8}, + /*( 45) FSTP*/ { 1, 1, 0xdf, 6}, + /*( 46) FSTPNCE*/ { 1, 1, 0xd9, 6}, + /*( 47) FLDENV*/ { 2, 0, 0xd9, 20}, + /*( 48) FLDENV*/ { 2, 0, 0xd9, 22}, + /*( 49) FLDENV*/ { 3, 0, 0xd9, 24}, + /*( 50) FLDENV*/ { 2, 0, 0xd9, 22}, + /*( 51) FLDENV*/ { 2, 0, 0xd9, 20}, + /*( 52) FLDENV*/ { 4, 0, 0xd9, 21}, + /*( 53) FLDENV*/ { 3, 0, 0xd9, 27}, + /*( 54) FLDCW*/ { 0, 0, 0xd9, 14}, + /*( 55) FNSTENV*/ { 2, 0, 0xd9, 30}, + /*( 56) FNSTENV*/ { 2, 0, 0xd9, 32}, + /*( 57) FNSTENV*/ { 3, 0, 0xd9, 34}, + /*( 58) FNSTENV*/ { 2, 0, 0xd9, 32}, + /*( 59) FNSTENV*/ { 2, 0, 0xd9, 30}, + /*( 60) FNSTENV*/ { 4, 0, 0xd9, 31}, + /*( 61) FNSTENV*/ { 3, 0, 0xd9, 37}, + /*( 62) FNSTCW*/ { 0, 0, 0xd9, 19}, + /*( 63) FXCH*/ { 1, 1, 0xd9, 4}, + /*( 64) FXCH*/ { 1, 1, 0xdf, 4}, + /*( 65) FXCH*/ { 1, 1, 0xdd, 4}, + /*( 66) FNOP*/ { 5, 1, 0xd9, 40}, + /*( 67) FCHS*/ { 5, 1, 0xd9, 43}, + /*( 68) FABS*/ { 5, 1, 0xd9, 46}, + /*( 69) FTST*/ { 5, 1, 0xd9, 49}, + /*( 70) FXAM*/ { 5, 1, 0xd9, 52}, + /*( 71) FLD1*/ { 5, 1, 0xd9, 55}, + /*( 72) FLDL2T*/ { 5, 1, 0xd9, 58}, + /*( 73) FLDL2E*/ { 5, 1, 0xd9, 61}, + /*( 74) FLDPI*/ { 5, 1, 0xd9, 64}, + /*( 75) FLDLG2*/ { 5, 1, 0xd9, 67}, + /*( 76) FLDLN2*/ { 5, 1, 0xd9, 70}, + /*( 77) FLDZ*/ { 5, 1, 0xd9, 13}, + /*( 78) F2XM1*/ { 5, 1, 0xd9, 73}, + /*( 79) FYL2X*/ { 5, 1, 0xd9, 76}, + /*( 80) FPTAN*/ { 5, 1, 0xd9, 79}, + /*( 81) FPATAN*/ { 5, 1, 0xd9, 16}, + /*( 82) FXTRACT*/ { 5, 1, 0xd9, 82}, + /*( 83) FPREM1*/ { 5, 1, 0xd9, 85}, + /*( 84) FDECSTP*/ { 5, 1, 0xd9, 88}, + /*( 85) FINCSTP*/ { 5, 1, 0xd9, 91}, + /*( 86) FPREM*/ { 5, 1, 0xd9, 18}, + /*( 87) FYL2XP1*/ { 5, 1, 0xd9, 94}, + /*( 88) FSQRT*/ { 5, 1, 0xd9, 97}, + /*( 89) FSINCOS*/ { 5, 1, 0xd9, 100}, + /*( 90) FRNDINT*/ { 5, 1, 0xd9, 103}, + /*( 91) FSCALE*/ { 5, 1, 0xd9, 106}, + /*( 92) FSIN*/ { 5, 1, 0xd9, 109}, + /*( 93) FCOS*/ { 5, 1, 0xd9, 112}, + /*( 94) FIADD*/ { 0, 0, 0xda, 0}, + /*( 95) FIADD*/ { 0, 0, 0xde, 0}, + /*( 96) FIMUL*/ { 0, 0, 0xda, 3}, + /*( 97) FIMUL*/ { 0, 0, 0xde, 3}, + /*( 98) FICOM*/ { 0, 0, 0xda, 9}, + /*( 99) FICOM*/ { 0, 0, 0xde, 9}, + /*( 100) FICOMP*/ { 0, 0, 0xda, 1}, + /*( 101) FICOMP*/ { 0, 0, 0xde, 1}, + /*( 102) FISUB*/ { 0, 0, 0xda, 10}, + /*( 103) FISUB*/ { 0, 0, 0xde, 10}, + /*( 104) FISUBR*/ { 0, 0, 0xda, 14}, + /*( 105) FISUBR*/ { 0, 0, 0xde, 14}, + /*( 106) FIDIV*/ { 0, 0, 0xda, 15}, + /*( 107) FIDIV*/ { 0, 0, 0xde, 15}, + /*( 108) FIDIVR*/ { 0, 0, 0xda, 19}, + /*( 109) FIDIVR*/ { 0, 0, 0xde, 19}, + /*( 110) FCMOVB*/ { 1, 1, 0xda, 1}, + /*( 111) FCMOVE*/ { 1, 1, 0xda, 4}, + /*( 112) FCMOVBE*/ { 1, 1, 0xda, 8}, + /*( 113) FCMOVU*/ { 1, 1, 0xda, 6}, + /*( 114) FUCOMPP*/ { 5, 1, 0xda, 58}, + /*( 115) FILD*/ { 0, 0, 0xdb, 0}, + /*( 116) FILD*/ { 0, 0, 0xdf, 0}, + /*( 117) FILD*/ { 0, 0, 0xdf, 14}, + /*( 118) FISTTP*/ { 0, 0, 0xdb, 3}, + /*( 119) FISTTP*/ { 0, 0, 0xdd, 3}, + /*( 120) FISTTP*/ { 0, 0, 0xdf, 3}, + /*( 121) FIST*/ { 0, 0, 0xdb, 9}, + /*( 122) FIST*/ { 0, 0, 0xdf, 9}, + /*( 123) FISTP*/ { 0, 0, 0xdb, 1}, + /*( 124) FISTP*/ { 0, 0, 0xdf, 1}, + /*( 125) FISTP*/ { 0, 0, 0xdf, 19}, + /*( 126) FCMOVNB*/ { 1, 1, 0xdb, 1}, + /*( 127) FCMOVNE*/ { 1, 1, 0xdb, 4}, + /*( 128) FCMOVNBE*/ { 1, 1, 0xdb, 8}, + /*( 129) FCMOVNU*/ { 1, 1, 0xdb, 6}, + /*( 130) FNCLEX*/ { 5, 1, 0xdb, 115}, + /*( 131) FNINIT*/ { 5, 1, 0xdb, 11}, + /*( 132) FSETPM287_NOP*/ { 5, 1, 0xdb, 49}, + /*( 133) FENI8087_NOP*/ { 5, 1, 0xdb, 43}, + /*( 134) FDISI8087_NOP*/ { 5, 1, 0xdb, 46}, + /*( 135) FUCOMI*/ { 1, 1, 0xdb, 13}, + /*( 136) FCOMI*/ { 1, 1, 0xdb, 16}, + /*( 137) FRSTOR*/ { 2, 0, 0xdd, 20}, + /*( 138) FRSTOR*/ { 2, 0, 0xdd, 22}, + /*( 139) FRSTOR*/ { 3, 0, 0xdd, 24}, + /*( 140) FRSTOR*/ { 2, 0, 0xdd, 22}, + /*( 141) FRSTOR*/ { 2, 0, 0xdd, 20}, + /*( 142) FRSTOR*/ { 4, 0, 0xdd, 21}, + /*( 143) FRSTOR*/ { 3, 0, 0xdd, 27}, + /*( 144) FNSAVE*/ { 2, 0, 0xdd, 30}, + /*( 145) FNSAVE*/ { 2, 0, 0xdd, 32}, + /*( 146) FNSAVE*/ { 3, 0, 0xdd, 34}, + /*( 147) FNSAVE*/ { 2, 0, 0xdd, 32}, + /*( 148) FNSAVE*/ { 2, 0, 0xdd, 30}, + /*( 149) FNSAVE*/ { 4, 0, 0xdd, 31}, + /*( 150) FNSAVE*/ { 3, 0, 0xdd, 37}, + /*( 151) FNSTSW*/ { 0, 0, 0xdd, 19}, + /*( 152) FNSTSW*/ { 5, 1, 0xdf, 43}, + /*( 153) FFREE*/ { 1, 1, 0xdd, 1}, + /*( 154) FUCOM*/ { 1, 1, 0xdd, 11}, + /*( 155) FUCOMP*/ { 1, 1, 0xdd, 13}, + /*( 156) FADDP*/ { 1, 1, 0xde, 1}, + /*( 157) FMULP*/ { 1, 1, 0xde, 4}, + /*( 158) FCOMPP*/ { 5, 1, 0xde, 118}, + /*( 159) FSUBRP*/ { 1, 1, 0xde, 11}, + /*( 160) FSUBP*/ { 1, 1, 0xde, 13}, + /*( 161) FDIVRP*/ { 1, 1, 0xde, 16}, + /*( 162) FDIVP*/ { 1, 1, 0xde, 18}, + /*( 163) FBLD*/ { 0, 0, 0xdf, 10}, + /*( 164) FBSTP*/ { 0, 0, 0xdf, 15}, + /*( 165) FFREEP*/ { 1, 1, 0xdf, 1}, + /*( 166) FUCOMIP*/ { 1, 1, 0xdf, 13}, + /*( 167) FCOMIP*/ { 1, 1, 0xdf, 16}, + /*( 168) ADD_LOCK*/ { 6, 2, 0x80, 121}, + /*( 169) ADD_LOCK*/ { 6, 3, 0x81, 121}, + /*( 170) ADD_LOCK*/ { 6, 2, 0x82, 121}, + /*( 171) ADD_LOCK*/ { 6, 2, 0x83, 121}, + /*( 172) ADD_LOCK*/ { 7, 0, 0x0, 3}, + /*( 173) ADD_LOCK*/ { 7, 0, 0x1, 3}, + /*( 174) ADD*/ { 6, 2, 0x80, 26}, + /*( 175) ADD*/ { 1, 4, 0x80, 1}, + /*( 176) ADD*/ { 6, 3, 0x81, 26}, + /*( 177) ADD*/ { 1, 5, 0x81, 1}, + /*( 178) ADD*/ { 6, 2, 0x82, 26}, + /*( 179) ADD*/ { 1, 4, 0x82, 1}, + /*( 180) ADD*/ { 6, 2, 0x83, 26}, + /*( 181) ADD*/ { 1, 4, 0x83, 1}, + /*( 182) ADD*/ { 7, 0, 0x0, 0}, + /*( 183) ADD*/ { 8, 1, 0x0, 1}, + /*( 184) ADD*/ { 7, 0, 0x1, 0}, + /*( 185) ADD*/ { 8, 1, 0x1, 1}, + /*( 186) ADD*/ { 9, 0, 0x2, 0}, + /*( 187) ADD*/ { 8, 1, 0x2, 1}, + /*( 188) ADD*/ { 9, 0, 0x3, 0}, + /*( 189) ADD*/ { 8, 1, 0x3, 1}, + /*( 190) ADD*/ { 9, 6, 0x4, 0}, + /*( 191) ADD*/ { 9, 7, 0x5, 0}, + /*( 192) OR_LOCK*/ { 6, 2, 0x80, 120}, + /*( 193) OR_LOCK*/ { 6, 3, 0x81, 120}, + /*( 194) OR_LOCK*/ { 6, 2, 0x82, 120}, + /*( 195) OR_LOCK*/ { 6, 2, 0x83, 120}, + /*( 196) OR_LOCK*/ { 7, 0, 0x8, 3}, + /*( 197) OR_LOCK*/ { 7, 0, 0x9, 3}, + /*( 198) OR*/ { 6, 2, 0x80, 2}, + /*( 199) OR*/ { 1, 4, 0x80, 4}, + /*( 200) OR*/ { 6, 3, 0x81, 2}, + /*( 201) OR*/ { 1, 5, 0x81, 4}, + /*( 202) OR*/ { 6, 2, 0x82, 2}, + /*( 203) OR*/ { 1, 4, 0x82, 4}, + /*( 204) OR*/ { 6, 2, 0x83, 2}, + /*( 205) OR*/ { 1, 4, 0x83, 4}, + /*( 206) OR*/ { 7, 0, 0x8, 0}, + /*( 207) OR*/ { 8, 1, 0x8, 1}, + /*( 208) OR*/ { 7, 0, 0x9, 0}, + /*( 209) OR*/ { 8, 1, 0x9, 1}, + /*( 210) OR*/ { 9, 0, 0xa, 0}, + /*( 211) OR*/ { 8, 1, 0xa, 1}, + /*( 212) OR*/ { 9, 0, 0xb, 0}, + /*( 213) OR*/ { 8, 1, 0xb, 1}, + /*( 214) OR*/ { 9, 8, 0xc, 0}, + /*( 215) OR*/ { 9, 7, 0xd, 0}, + /*( 216) ADC_LOCK*/ { 6, 2, 0x80, 123}, + /*( 217) ADC_LOCK*/ { 6, 3, 0x81, 123}, + /*( 218) ADC_LOCK*/ { 6, 2, 0x82, 123}, + /*( 219) ADC_LOCK*/ { 6, 2, 0x83, 123}, + /*( 220) ADC_LOCK*/ { 7, 0, 0x10, 3}, + /*( 221) ADC_LOCK*/ { 7, 0, 0x11, 3}, + /*( 222) ADC*/ { 6, 2, 0x80, 125}, + /*( 223) ADC*/ { 1, 4, 0x80, 8}, + /*( 224) ADC*/ { 6, 3, 0x81, 125}, + /*( 225) ADC*/ { 1, 5, 0x81, 8}, + /*( 226) ADC*/ { 6, 2, 0x82, 125}, + /*( 227) ADC*/ { 1, 4, 0x82, 8}, + /*( 228) ADC*/ { 6, 2, 0x83, 125}, + /*( 229) ADC*/ { 1, 4, 0x83, 8}, + /*( 230) ADC*/ { 7, 0, 0x10, 0}, + /*( 231) ADC*/ { 8, 1, 0x10, 1}, + /*( 232) ADC*/ { 7, 0, 0x11, 0}, + /*( 233) ADC*/ { 8, 1, 0x11, 1}, + /*( 234) ADC*/ { 9, 0, 0x12, 0}, + /*( 235) ADC*/ { 8, 1, 0x12, 1}, + /*( 236) ADC*/ { 9, 0, 0x13, 0}, + /*( 237) ADC*/ { 8, 1, 0x13, 1}, + /*( 238) ADC*/ { 9, 6, 0x14, 0}, + /*( 239) ADC*/ { 9, 7, 0x15, 0}, + /*( 240) SBB_LOCK*/ { 6, 2, 0x80, 3}, + /*( 241) SBB_LOCK*/ { 6, 3, 0x81, 3}, + /*( 242) SBB_LOCK*/ { 6, 2, 0x82, 3}, + /*( 243) SBB_LOCK*/ { 6, 2, 0x83, 3}, + /*( 244) SBB_LOCK*/ { 7, 0, 0x18, 3}, + /*( 245) SBB_LOCK*/ { 7, 0, 0x19, 3}, + /*( 246) SBB*/ { 6, 2, 0x80, 0}, + /*( 247) SBB*/ { 1, 4, 0x80, 6}, + /*( 248) SBB*/ { 6, 3, 0x81, 0}, + /*( 249) SBB*/ { 1, 5, 0x81, 6}, + /*( 250) SBB*/ { 6, 2, 0x82, 0}, + /*( 251) SBB*/ { 1, 4, 0x82, 6}, + /*( 252) SBB*/ { 6, 2, 0x83, 0}, + /*( 253) SBB*/ { 1, 4, 0x83, 6}, + /*( 254) SBB*/ { 7, 0, 0x18, 0}, + /*( 255) SBB*/ { 8, 1, 0x18, 1}, + /*( 256) SBB*/ { 7, 0, 0x19, 0}, + /*( 257) SBB*/ { 8, 1, 0x19, 1}, + /*( 258) SBB*/ { 8, 1, 0x1a, 1}, + /*( 259) SBB*/ { 9, 0, 0x1a, 0}, + /*( 260) SBB*/ { 8, 1, 0x1b, 1}, + /*( 261) SBB*/ { 9, 0, 0x1b, 0}, + /*( 262) SBB*/ { 9, 6, 0x1c, 0}, + /*( 263) SBB*/ { 9, 7, 0x1d, 0}, + /*( 264) AND_LOCK*/ { 6, 9, 0x80, 22}, + /*( 265) AND_LOCK*/ { 6, 3, 0x81, 22}, + /*( 266) AND_LOCK*/ { 6, 9, 0x82, 22}, + /*( 267) AND_LOCK*/ { 6, 2, 0x83, 22}, + /*( 268) AND_LOCK*/ { 7, 0, 0x20, 3}, + /*( 269) AND_LOCK*/ { 7, 0, 0x21, 3}, + /*( 270) AND*/ { 6, 9, 0x80, 20}, + /*( 271) AND*/ { 1, 10, 0x80, 11}, + /*( 272) AND*/ { 6, 3, 0x81, 20}, + /*( 273) AND*/ { 1, 5, 0x81, 11}, + /*( 274) AND*/ { 6, 9, 0x82, 20}, + /*( 275) AND*/ { 1, 10, 0x82, 11}, + /*( 276) AND*/ { 6, 2, 0x83, 20}, + /*( 277) AND*/ { 1, 4, 0x83, 11}, + /*( 278) AND*/ { 7, 0, 0x20, 0}, + /*( 279) AND*/ { 8, 1, 0x20, 1}, + /*( 280) AND*/ { 7, 0, 0x21, 0}, + /*( 281) AND*/ { 8, 1, 0x21, 1}, + /*( 282) AND*/ { 8, 1, 0x22, 1}, + /*( 283) AND*/ { 9, 0, 0x22, 0}, + /*( 284) AND*/ { 8, 1, 0x23, 1}, + /*( 285) AND*/ { 9, 0, 0x23, 0}, + /*( 286) AND*/ { 9, 6, 0x24, 0}, + /*( 287) AND*/ { 9, 7, 0x25, 0}, + /*( 288) SUB_LOCK*/ { 6, 2, 0x80, 127}, + /*( 289) SUB_LOCK*/ { 6, 3, 0x81, 127}, + /*( 290) SUB_LOCK*/ { 6, 2, 0x82, 127}, + /*( 291) SUB_LOCK*/ { 6, 2, 0x83, 127}, + /*( 292) SUB_LOCK*/ { 7, 0, 0x28, 3}, + /*( 293) SUB_LOCK*/ { 7, 0, 0x29, 3}, + /*( 294) SUB*/ { 6, 2, 0x80, 129}, + /*( 295) SUB*/ { 1, 4, 0x80, 13}, + /*( 296) SUB*/ { 6, 3, 0x81, 129}, + /*( 297) SUB*/ { 1, 5, 0x81, 13}, + /*( 298) SUB*/ { 6, 2, 0x82, 129}, + /*( 299) SUB*/ { 1, 4, 0x82, 13}, + /*( 300) SUB*/ { 6, 2, 0x83, 129}, + /*( 301) SUB*/ { 1, 4, 0x83, 13}, + /*( 302) SUB*/ { 7, 0, 0x28, 0}, + /*( 303) SUB*/ { 8, 1, 0x28, 1}, + /*( 304) SUB*/ { 7, 0, 0x29, 0}, + /*( 305) SUB*/ { 8, 1, 0x29, 1}, + /*( 306) SUB*/ { 8, 1, 0x2a, 1}, + /*( 307) SUB*/ { 9, 0, 0x2a, 0}, + /*( 308) SUB*/ { 8, 1, 0x2b, 1}, + /*( 309) SUB*/ { 9, 0, 0x2b, 0}, + /*( 310) SUB*/ { 9, 6, 0x2c, 0}, + /*( 311) SUB*/ { 9, 7, 0x2d, 0}, + /*( 312) XOR_LOCK*/ { 6, 9, 0x80, 32}, + /*( 313) XOR_LOCK*/ { 6, 3, 0x81, 32}, + /*( 314) XOR_LOCK*/ { 6, 9, 0x82, 32}, + /*( 315) XOR_LOCK*/ { 6, 2, 0x83, 32}, + /*( 316) XOR_LOCK*/ { 7, 0, 0x30, 3}, + /*( 317) XOR_LOCK*/ { 7, 0, 0x31, 3}, + /*( 318) XOR*/ { 6, 9, 0x80, 30}, + /*( 319) XOR*/ { 1, 10, 0x80, 16}, + /*( 320) XOR*/ { 6, 3, 0x81, 30}, + /*( 321) XOR*/ { 1, 5, 0x81, 16}, + /*( 322) XOR*/ { 6, 9, 0x82, 30}, + /*( 323) XOR*/ { 1, 10, 0x82, 16}, + /*( 324) XOR*/ { 6, 2, 0x83, 30}, + /*( 325) XOR*/ { 1, 4, 0x83, 16}, + /*( 326) XOR*/ { 7, 0, 0x30, 0}, + /*( 327) XOR*/ { 8, 1, 0x30, 1}, + /*( 328) XOR*/ { 7, 0, 0x31, 0}, + /*( 329) XOR*/ { 8, 1, 0x31, 1}, + /*( 330) XOR*/ { 8, 1, 0x32, 1}, + /*( 331) XOR*/ { 9, 0, 0x32, 0}, + /*( 332) XOR*/ { 8, 1, 0x33, 1}, + /*( 333) XOR*/ { 9, 0, 0x33, 0}, + /*( 334) XOR*/ { 9, 8, 0x34, 0}, + /*( 335) XOR*/ { 9, 7, 0x35, 0}, + /*( 336) CMP*/ { 0, 2, 0x80, 19}, + /*( 337) CMP*/ { 1, 4, 0x80, 18}, + /*( 338) CMP*/ { 0, 3, 0x81, 19}, + /*( 339) CMP*/ { 1, 5, 0x81, 18}, + /*( 340) CMP*/ { 0, 2, 0x82, 19}, + /*( 341) CMP*/ { 1, 4, 0x82, 18}, + /*( 342) CMP*/ { 0, 2, 0x83, 19}, + /*( 343) CMP*/ { 1, 4, 0x83, 18}, + /*( 344) CMP*/ { 9, 0, 0x38, 0}, + /*( 345) CMP*/ { 8, 1, 0x38, 1}, + /*( 346) CMP*/ { 9, 0, 0x39, 0}, + /*( 347) CMP*/ { 8, 1, 0x39, 1}, + /*( 348) CMP*/ { 9, 0, 0x3a, 0}, + /*( 349) CMP*/ { 8, 1, 0x3a, 1}, + /*( 350) CMP*/ { 9, 0, 0x3b, 0}, + /*( 351) CMP*/ { 8, 1, 0x3b, 1}, + /*( 352) CMP*/ { 9, 6, 0x3c, 0}, + /*( 353) CMP*/ { 9, 7, 0x3d, 0}, + /*( 354) POP*/ { 0, 11, 0x8f, 0}, + /*( 355) POP*/ { 1, 12, 0x8f, 1}, + /*( 356) POP*/ { 9, 13, 0x7, 0}, + /*( 357) POP*/ { 9, 13, 0x17, 0}, + /*( 358) POP*/ { 9, 13, 0x1f, 0}, + /*( 359) POP*/ { 9, 14, 0xb, 0}, + /*( 360) POP*/ { 9, 15, 0xa1, 0}, + /*( 361) POP*/ { 9, 15, 0xa9, 0}, + /*( 362) ROL*/ { 0, 9, 0xc0, 0}, + /*( 363) ROL*/ { 1, 10, 0xc0, 1}, + /*( 364) ROL*/ { 0, 9, 0xc1, 0}, + /*( 365) ROL*/ { 1, 10, 0xc1, 1}, + /*( 366) ROL*/ { 0, 16, 0xd0, 0}, + /*( 367) ROL*/ { 1, 17, 0xd0, 1}, + /*( 368) ROL*/ { 0, 16, 0xd1, 0}, + /*( 369) ROL*/ { 1, 17, 0xd1, 1}, + /*( 370) ROL*/ { 0, 0, 0xd2, 0}, + /*( 371) ROL*/ { 1, 1, 0xd2, 1}, + /*( 372) ROL*/ { 0, 0, 0xd3, 0}, + /*( 373) ROL*/ { 1, 1, 0xd3, 1}, + /*( 374) ROR*/ { 0, 9, 0xc0, 3}, + /*( 375) ROR*/ { 1, 10, 0xc0, 4}, + /*( 376) ROR*/ { 1, 10, 0xc1, 4}, + /*( 377) ROR*/ { 0, 9, 0xc1, 3}, + /*( 378) ROR*/ { 0, 16, 0xd0, 3}, + /*( 379) ROR*/ { 1, 17, 0xd0, 4}, + /*( 380) ROR*/ { 0, 16, 0xd1, 3}, + /*( 381) ROR*/ { 1, 17, 0xd1, 4}, + /*( 382) ROR*/ { 0, 0, 0xd2, 3}, + /*( 383) ROR*/ { 1, 1, 0xd2, 4}, + /*( 384) ROR*/ { 0, 0, 0xd3, 3}, + /*( 385) ROR*/ { 1, 1, 0xd3, 4}, + /*( 386) RCL*/ { 0, 9, 0xc0, 9}, + /*( 387) RCL*/ { 1, 10, 0xc0, 8}, + /*( 388) RCL*/ { 0, 9, 0xc1, 9}, + /*( 389) RCL*/ { 1, 10, 0xc1, 8}, + /*( 390) RCL*/ { 0, 16, 0xd0, 9}, + /*( 391) RCL*/ { 1, 17, 0xd0, 8}, + /*( 392) RCL*/ { 0, 16, 0xd1, 9}, + /*( 393) RCL*/ { 1, 17, 0xd1, 8}, + /*( 394) RCL*/ { 0, 0, 0xd2, 9}, + /*( 395) RCL*/ { 1, 1, 0xd2, 8}, + /*( 396) RCL*/ { 0, 0, 0xd3, 9}, + /*( 397) RCL*/ { 1, 1, 0xd3, 8}, + /*( 398) RCR*/ { 0, 9, 0xc0, 1}, + /*( 399) RCR*/ { 1, 10, 0xc0, 6}, + /*( 400) RCR*/ { 0, 9, 0xc1, 1}, + /*( 401) RCR*/ { 1, 10, 0xc1, 6}, + /*( 402) RCR*/ { 0, 16, 0xd0, 1}, + /*( 403) RCR*/ { 1, 17, 0xd0, 6}, + /*( 404) RCR*/ { 0, 16, 0xd1, 1}, + /*( 405) RCR*/ { 1, 17, 0xd1, 6}, + /*( 406) RCR*/ { 0, 0, 0xd2, 1}, + /*( 407) RCR*/ { 1, 1, 0xd2, 6}, + /*( 408) RCR*/ { 0, 0, 0xd3, 1}, + /*( 409) RCR*/ { 1, 1, 0xd3, 6}, + /*( 410) SHL*/ { 0, 9, 0xc0, 10}, + /*( 411) SHL*/ { 1, 10, 0xc0, 11}, + /*( 412) SHL*/ { 0, 9, 0xc0, 15}, + /*( 413) SHL*/ { 1, 10, 0xc0, 16}, + /*( 414) SHL*/ { 0, 9, 0xc1, 10}, + /*( 415) SHL*/ { 1, 10, 0xc1, 11}, + /*( 416) SHL*/ { 0, 9, 0xc1, 15}, + /*( 417) SHL*/ { 1, 10, 0xc1, 16}, + /*( 418) SHL*/ { 0, 16, 0xd0, 10}, + /*( 419) SHL*/ { 1, 17, 0xd0, 11}, + /*( 420) SHL*/ { 0, 16, 0xd0, 15}, + /*( 421) SHL*/ { 1, 17, 0xd0, 16}, + /*( 422) SHL*/ { 0, 16, 0xd1, 15}, + /*( 423) SHL*/ { 1, 17, 0xd1, 16}, + /*( 424) SHL*/ { 0, 16, 0xd1, 10}, + /*( 425) SHL*/ { 1, 17, 0xd1, 11}, + /*( 426) SHL*/ { 0, 0, 0xd2, 10}, + /*( 427) SHL*/ { 1, 1, 0xd2, 11}, + /*( 428) SHL*/ { 0, 0, 0xd2, 15}, + /*( 429) SHL*/ { 1, 1, 0xd2, 16}, + /*( 430) SHL*/ { 0, 0, 0xd3, 10}, + /*( 431) SHL*/ { 1, 1, 0xd3, 11}, + /*( 432) SHL*/ { 0, 0, 0xd3, 15}, + /*( 433) SHL*/ { 1, 1, 0xd3, 16}, + /*( 434) SHR*/ { 0, 9, 0xc0, 14}, + /*( 435) SHR*/ { 1, 10, 0xc0, 13}, + /*( 436) SHR*/ { 0, 9, 0xc1, 14}, + /*( 437) SHR*/ { 1, 10, 0xc1, 13}, + /*( 438) SHR*/ { 0, 16, 0xd0, 14}, + /*( 439) SHR*/ { 1, 17, 0xd0, 13}, + /*( 440) SHR*/ { 0, 16, 0xd1, 14}, + /*( 441) SHR*/ { 1, 17, 0xd1, 13}, + /*( 442) SHR*/ { 0, 0, 0xd2, 14}, + /*( 443) SHR*/ { 1, 1, 0xd2, 13}, + /*( 444) SHR*/ { 0, 0, 0xd3, 14}, + /*( 445) SHR*/ { 1, 1, 0xd3, 13}, + /*( 446) SAR*/ { 0, 9, 0xc0, 19}, + /*( 447) SAR*/ { 1, 10, 0xc0, 18}, + /*( 448) SAR*/ { 0, 9, 0xc1, 19}, + /*( 449) SAR*/ { 1, 10, 0xc1, 18}, + /*( 450) SAR*/ { 0, 16, 0xd0, 19}, + /*( 451) SAR*/ { 1, 17, 0xd0, 18}, + /*( 452) SAR*/ { 0, 16, 0xd1, 19}, + /*( 453) SAR*/ { 1, 17, 0xd1, 18}, + /*( 454) SAR*/ { 0, 0, 0xd2, 19}, + /*( 455) SAR*/ { 1, 1, 0xd2, 18}, + /*( 456) SAR*/ { 0, 0, 0xd3, 19}, + /*( 457) SAR*/ { 1, 1, 0xd3, 18}, + /*( 458) TEST*/ { 0, 2, 0xf6, 0}, + /*( 459) TEST*/ { 0, 2, 0xf6, 3}, + /*( 460) TEST*/ { 1, 4, 0xf6, 1}, + /*( 461) TEST*/ { 1, 4, 0xf6, 4}, + /*( 462) TEST*/ { 0, 3, 0xf7, 0}, + /*( 463) TEST*/ { 0, 3, 0xf7, 3}, + /*( 464) TEST*/ { 1, 5, 0xf7, 1}, + /*( 465) TEST*/ { 1, 5, 0xf7, 4}, + /*( 466) TEST*/ { 9, 0, 0x84, 0}, + /*( 467) TEST*/ { 8, 1, 0x84, 1}, + /*( 468) TEST*/ { 9, 0, 0x85, 0}, + /*( 469) TEST*/ { 8, 1, 0x85, 1}, + /*( 470) TEST*/ { 9, 6, 0xa8, 0}, + /*( 471) TEST*/ { 9, 7, 0xa9, 0}, + /*( 472) NOT_LOCK*/ { 6, 0, 0xf6, 123}, + /*( 473) NOT_LOCK*/ { 6, 0, 0xf7, 123}, + /*( 474) NOT*/ { 6, 0, 0xf6, 125}, + /*( 475) NOT*/ { 1, 1, 0xf6, 8}, + /*( 476) NOT*/ { 6, 0, 0xf7, 125}, + /*( 477) NOT*/ { 1, 1, 0xf7, 8}, + /*( 478) NEG_LOCK*/ { 6, 0, 0xf6, 3}, + /*( 479) NEG_LOCK*/ { 6, 0, 0xf7, 3}, + /*( 480) NEG*/ { 6, 0, 0xf6, 0}, + /*( 481) NEG*/ { 1, 1, 0xf6, 6}, + /*( 482) NEG*/ { 6, 0, 0xf7, 0}, + /*( 483) NEG*/ { 1, 1, 0xf7, 6}, + /*( 484) MUL*/ { 0, 0, 0xf6, 10}, + /*( 485) MUL*/ { 1, 1, 0xf6, 11}, + /*( 486) MUL*/ { 0, 0, 0xf7, 10}, + /*( 487) MUL*/ { 1, 1, 0xf7, 11}, + /*( 488) IMUL*/ { 0, 0, 0xf6, 14}, + /*( 489) IMUL*/ { 1, 1, 0xf6, 13}, + /*( 490) IMUL*/ { 0, 0, 0xf7, 14}, + /*( 491) IMUL*/ { 1, 1, 0xf7, 13}, + /*( 492) IMUL*/ { 9, 3, 0x69, 0}, + /*( 493) IMUL*/ { 8, 5, 0x69, 1}, + /*( 494) IMUL*/ { 9, 2, 0x6b, 0}, + /*( 495) IMUL*/ { 8, 4, 0x6b, 1}, + /*( 496) IMUL*/ { 9, 18, 0xaf, 0}, + /*( 497) IMUL*/ { 8, 19, 0xaf, 1}, + /*( 498) DIV*/ { 0, 0, 0xf6, 15}, + /*( 499) DIV*/ { 1, 1, 0xf6, 16}, + /*( 500) DIV*/ { 0, 0, 0xf7, 15}, + /*( 501) DIV*/ { 1, 1, 0xf7, 16}, + /*( 502) IDIV*/ { 0, 0, 0xf6, 19}, + /*( 503) IDIV*/ { 1, 1, 0xf6, 18}, + /*( 504) IDIV*/ { 0, 0, 0xf7, 19}, + /*( 505) IDIV*/ { 1, 1, 0xf7, 18}, + /*( 506) INC_LOCK*/ { 6, 0, 0xfe, 121}, + /*( 507) INC_LOCK*/ { 6, 0, 0xff, 121}, + /*( 508) INC*/ { 6, 0, 0xfe, 26}, + /*( 509) INC*/ { 1, 1, 0xfe, 1}, + /*( 510) INC*/ { 6, 0, 0xff, 26}, + /*( 511) INC*/ { 1, 1, 0xff, 1}, + /*( 512) INC*/ { 9, 20, 0x8, 0}, + /*( 513) DEC_LOCK*/ { 6, 0, 0xfe, 120}, + /*( 514) DEC_LOCK*/ { 6, 0, 0xff, 120}, + /*( 515) DEC*/ { 6, 0, 0xfe, 2}, + /*( 516) DEC*/ { 1, 1, 0xfe, 4}, + /*( 517) DEC*/ { 6, 0, 0xff, 2}, + /*( 518) DEC*/ { 1, 1, 0xff, 4}, + /*( 519) DEC*/ { 9, 20, 0x9, 0}, + /*( 520) CALL_NEAR*/ { 0, 21, 0xff, 9}, + /*( 521) CALL_NEAR*/ { 1, 22, 0xff, 8}, + /*( 522) CALL_NEAR*/ { 9, 23, 0xe8, 0}, + /*( 523) CALL_NEAR*/ { 9, 24, 0xe8, 0}, + /*( 524) JMP*/ { 0, 21, 0xff, 10}, + /*( 525) JMP*/ { 1, 22, 0xff, 11}, + /*( 526) JMP*/ { 9, 23, 0xe9, 0}, + /*( 527) JMP*/ { 9, 25, 0xe9, 0}, + /*( 528) JMP*/ { 9, 26, 0xeb, 0}, + /*( 529) JMP*/ { 9, 27, 0xeb, 0}, + /*( 530) JMP_FAR*/ { 0, 0, 0xff, 14}, + /*( 531) JMP_FAR*/ { 9, 28, 0xea, 0}, + /*( 532) PUSH*/ { 0, 11, 0xff, 15}, + /*( 533) PUSH*/ { 1, 12, 0xff, 16}, + /*( 534) PUSH*/ { 9, 13, 0x6, 0}, + /*( 535) PUSH*/ { 9, 13, 0xe, 0}, + /*( 536) PUSH*/ { 9, 13, 0x16, 0}, + /*( 537) PUSH*/ { 9, 13, 0x1e, 0}, + /*( 538) PUSH*/ { 9, 14, 0xa, 0}, + /*( 539) PUSH*/ { 9, 29, 0x68, 0}, + /*( 540) PUSH*/ { 9, 30, 0x6a, 0}, + /*( 541) PUSH*/ { 9, 15, 0xa0, 0}, + /*( 542) PUSH*/ { 9, 15, 0xa8, 0}, + /*( 543) SLDT*/ { 0, 18, 0x0, 0}, + /*( 544) SLDT*/ { 1, 19, 0x0, 1}, + /*( 545) STR*/ { 0, 18, 0x0, 3}, + /*( 546) STR*/ { 1, 19, 0x0, 4}, + /*( 547) LLDT*/ { 0, 18, 0x0, 9}, + /*( 548) LLDT*/ { 1, 19, 0x0, 8}, + /*( 549) LTR*/ { 0, 18, 0x0, 1}, + /*( 550) LTR*/ { 1, 19, 0x0, 6}, + /*( 551) VERR*/ { 0, 18, 0x0, 10}, + /*( 552) VERR*/ { 1, 19, 0x0, 11}, + /*( 553) VERW*/ { 0, 18, 0x0, 14}, + /*( 554) VERW*/ { 1, 19, 0x0, 13}, + /*( 555) LGDT*/ { 0, 31, 0x1, 9}, + /*( 556) LGDT*/ { 0, 18, 0x1, 9}, + /*( 557) SMSW*/ { 0, 18, 0x1, 10}, + /*( 558) SMSW*/ { 1, 19, 0x1, 11}, + /*( 559) LMSW*/ { 0, 18, 0x1, 15}, + /*( 560) LMSW*/ { 1, 19, 0x1, 16}, + /*( 561) BT*/ { 0, 32, 0xba, 10}, + /*( 562) BT*/ { 1, 33, 0xba, 11}, + /*( 563) BT*/ { 9, 18, 0xa3, 0}, + /*( 564) BT*/ { 8, 19, 0xa3, 1}, + /*( 565) BTS_LOCK*/ { 6, 32, 0xba, 127}, + /*( 566) BTS_LOCK*/ { 7, 18, 0xab, 3}, + /*( 567) BTS*/ { 6, 32, 0xba, 129}, + /*( 568) BTS*/ { 1, 33, 0xba, 13}, + /*( 569) BTS*/ { 7, 18, 0xab, 0}, + /*( 570) BTS*/ { 8, 19, 0xab, 1}, + /*( 571) BTR_LOCK*/ { 6, 32, 0xba, 32}, + /*( 572) BTR_LOCK*/ { 7, 18, 0xb3, 3}, + /*( 573) BTR*/ { 6, 32, 0xba, 30}, + /*( 574) BTR*/ { 1, 33, 0xba, 16}, + /*( 575) BTR*/ { 7, 18, 0xb3, 0}, + /*( 576) BTR*/ { 8, 19, 0xb3, 1}, + /*( 577) BTC_LOCK*/ { 6, 32, 0xba, 131}, + /*( 578) BTC_LOCK*/ { 7, 18, 0xbb, 3}, + /*( 579) BTC*/ { 6, 32, 0xba, 133}, + /*( 580) BTC*/ { 1, 33, 0xba, 18}, + /*( 581) BTC*/ { 7, 18, 0xbb, 0}, + /*( 582) BTC*/ { 8, 19, 0xbb, 1}, + /*( 583) VMCLEAR*/ { 10, 34, 0xc7, 34}, + /*( 584) VMPTRLD*/ { 10, 18, 0xc7, 37}, + /*( 585) VMPTRST*/ { 10, 18, 0xc7, 135}, + /*( 586) VMXON*/ { 11, 35, 0xc7, 15}, + /*( 587) CMPXCHG8B_LOCK*/ { 6, 36, 0xc7, 120}, + /*( 588) CMPXCHG8B_LOCK*/ { 12, 36, 0xc7, 120}, + /*( 589) CMPXCHG8B*/ { 6, 36, 0xc7, 2}, + /*( 590) CMPXCHG8B*/ { 12, 36, 0xc7, 138}, + /*( 591) CMPXCHG16B_LOCK*/ { 12, 36, 0xc7, 141}, + /*( 592) CMPXCHG16B*/ { 12, 36, 0xc7, 140}, + /*( 593) MOV*/ { 1, 10, 0xc6, 1}, + /*( 594) MOV*/ { 0, 9, 0xc6, 0}, + /*( 595) MOV*/ { 1, 5, 0xc7, 1}, + /*( 596) MOV*/ { 0, 3, 0xc7, 0}, + /*( 597) MOV*/ { 8, 1, 0x88, 1}, + /*( 598) MOV*/ { 9, 0, 0x88, 0}, + /*( 599) MOV*/ { 9, 0, 0x89, 0}, + /*( 600) MOV*/ { 8, 1, 0x89, 1}, + /*( 601) MOV*/ { 9, 0, 0x8a, 0}, + /*( 602) MOV*/ { 8, 1, 0x8a, 1}, + /*( 603) MOV*/ { 9, 0, 0x8b, 0}, + /*( 604) MOV*/ { 8, 1, 0x8b, 1}, + /*( 605) MOV*/ { 9, 0, 0x8c, 0}, + /*( 606) MOV*/ { 8, 1, 0x8c, 1}, + /*( 607) MOV*/ { 9, 0, 0x8e, 0}, + /*( 608) MOV*/ { 8, 1, 0x8e, 1}, + /*( 609) MOV*/ { 9, 37, 0xa0, 0}, + /*( 610) MOV*/ { 9, 37, 0xa1, 0}, + /*( 611) MOV*/ { 9, 37, 0xa2, 0}, + /*( 612) MOV*/ { 9, 37, 0xa3, 0}, + /*( 613) MOV*/ { 9, 38, 0x16, 0}, + /*( 614) MOV*/ { 9, 39, 0x17, 0}, + /*( 615) PSRLW*/ { 13, 33, 0x71, 144}, + /*( 616) PSRLW*/ { 13, 40, 0x71, 148}, + /*( 617) PSRLW*/ { 14, 18, 0xd1, 26}, + /*( 618) PSRLW*/ { 15, 19, 0xd1, 152}, + /*( 619) PSRLW*/ { 14, 34, 0xd1, 121}, + /*( 620) PSRLW*/ { 15, 41, 0xd1, 155}, + /*( 621) PSRAW*/ { 13, 33, 0x71, 158}, + /*( 622) PSRAW*/ { 13, 40, 0x71, 162}, + /*( 623) PSRAW*/ { 14, 18, 0xe1, 26}, + /*( 624) PSRAW*/ { 15, 19, 0xe1, 152}, + /*( 625) PSRAW*/ { 14, 34, 0xe1, 121}, + /*( 626) PSRAW*/ { 15, 41, 0xe1, 155}, + /*( 627) PSLLW*/ { 13, 33, 0x71, 166}, + /*( 628) PSLLW*/ { 13, 40, 0x71, 170}, + /*( 629) PSLLW*/ { 14, 18, 0xf1, 26}, + /*( 630) PSLLW*/ { 15, 19, 0xf1, 152}, + /*( 631) PSLLW*/ { 14, 34, 0xf1, 121}, + /*( 632) PSLLW*/ { 15, 41, 0xf1, 155}, + /*( 633) PSRLD*/ { 13, 33, 0x72, 144}, + /*( 634) PSRLD*/ { 13, 40, 0x72, 148}, + /*( 635) PSRLD*/ { 14, 18, 0xd2, 26}, + /*( 636) PSRLD*/ { 15, 19, 0xd2, 152}, + /*( 637) PSRLD*/ { 14, 34, 0xd2, 121}, + /*( 638) PSRLD*/ { 15, 41, 0xd2, 155}, + /*( 639) PSRAD*/ { 13, 33, 0x72, 158}, + /*( 640) PSRAD*/ { 13, 40, 0x72, 162}, + /*( 641) PSRAD*/ { 14, 18, 0xe2, 26}, + /*( 642) PSRAD*/ { 15, 19, 0xe2, 152}, + /*( 643) PSRAD*/ { 14, 34, 0xe2, 121}, + /*( 644) PSRAD*/ { 15, 41, 0xe2, 155}, + /*( 645) PSLLD*/ { 13, 33, 0x72, 166}, + /*( 646) PSLLD*/ { 13, 40, 0x72, 170}, + /*( 647) PSLLD*/ { 14, 18, 0xf2, 26}, + /*( 648) PSLLD*/ { 15, 19, 0xf2, 152}, + /*( 649) PSLLD*/ { 14, 34, 0xf2, 121}, + /*( 650) PSLLD*/ { 15, 41, 0xf2, 155}, + /*( 651) PSRLQ*/ { 13, 33, 0x73, 144}, + /*( 652) PSRLQ*/ { 13, 40, 0x73, 148}, + /*( 653) PSRLQ*/ { 14, 18, 0xd3, 26}, + /*( 654) PSRLQ*/ { 15, 19, 0xd3, 152}, + /*( 655) PSRLQ*/ { 14, 34, 0xd3, 121}, + /*( 656) PSRLQ*/ { 15, 41, 0xd3, 155}, + /*( 657) PSLLQ*/ { 13, 33, 0x73, 166}, + /*( 658) PSLLQ*/ { 13, 40, 0x73, 170}, + /*( 659) PSLLQ*/ { 14, 18, 0xf3, 26}, + /*( 660) PSLLQ*/ { 15, 19, 0xf3, 152}, + /*( 661) PSLLQ*/ { 14, 34, 0xf3, 121}, + /*( 662) PSLLQ*/ { 15, 41, 0xf3, 155}, + /*( 663) PSRLDQ*/ { 13, 40, 0x73, 174}, + /*( 664) PSLLDQ*/ { 13, 40, 0x73, 178}, + /*( 665) FXSAVE*/ { 16, 18, 0xae, 182}, + /*( 666) FXRSTOR*/ { 16, 18, 0xae, 186}, + /*( 667) FXSAVE64*/ { 16, 18, 0xae, 184}, + /*( 668) FXRSTOR64*/ { 16, 18, 0xae, 138}, + /*( 669) LDMXCSR*/ { 10, 18, 0xae, 145}, + /*( 670) STMXCSR*/ { 10, 18, 0xae, 0}, + /*( 671) PREFETCHNTA*/ { 0, 18, 0x18, 0}, + /*( 672) PREFETCHT0*/ { 0, 18, 0x18, 3}, + /*( 673) PREFETCHT1*/ { 0, 18, 0x18, 9}, + /*( 674) PREFETCHT2*/ { 0, 18, 0x18, 1}, + /*( 675) NOP*/ { 1, 19, 0x18, 1}, + /*( 676) NOP*/ { 1, 19, 0x18, 4}, + /*( 677) NOP*/ { 1, 19, 0x18, 8}, + /*( 678) NOP*/ { 1, 19, 0x18, 6}, + /*( 679) NOP*/ { 0, 18, 0x18, 10}, + /*( 680) NOP*/ { 1, 19, 0x18, 11}, + /*( 681) NOP*/ { 0, 18, 0x18, 14}, + /*( 682) NOP*/ { 1, 19, 0x18, 13}, + /*( 683) NOP*/ { 1, 19, 0x18, 16}, + /*( 684) NOP*/ { 1, 19, 0x18, 18}, + /*( 685) NOP*/ { 0, 18, 0x18, 15}, + /*( 686) NOP*/ { 0, 18, 0x18, 19}, + /*( 687) NOP*/ { 9, 18, 0x19, 0}, + /*( 688) NOP*/ { 8, 19, 0x19, 1}, + /*( 689) NOP*/ { 9, 18, 0x1a, 0}, + /*( 690) NOP*/ { 8, 19, 0x1a, 1}, + /*( 691) NOP*/ { 9, 18, 0x1b, 0}, + /*( 692) NOP*/ { 8, 19, 0x1b, 1}, + /*( 693) NOP*/ { 9, 18, 0x1c, 0}, + /*( 694) NOP*/ { 8, 19, 0x1c, 1}, + /*( 695) NOP*/ { 9, 18, 0x1d, 0}, + /*( 696) NOP*/ { 8, 19, 0x1d, 1}, + /*( 697) NOP*/ { 9, 18, 0x1e, 0}, + /*( 698) NOP*/ { 8, 19, 0x1e, 1}, + /*( 699) NOP*/ { 9, 18, 0x1f, 0}, + /*( 700) NOP*/ { 8, 19, 0x1f, 1}, + /*( 701) NOP*/ { 17, 20, 0x12, 26}, + /*( 702) NOP*/ { 18, 20, 0x12, 0}, + /*( 703) NOP*/ { 8, 19, 0xd, 1}, + /*( 704) NOP*/ { 15, 19, 0x1a, 152}, + /*( 705) NOP*/ { 15, 19, 0x1b, 152}, + /*( 706) NOP*/ { 19, 19, 0x1b, 6}, + /*( 707) NOP*/ { 8, 19, 0x1a, 1}, + /*( 708) NOP*/ { 8, 19, 0x1b, 1}, + /*( 709) NOP*/ { 9, 18, 0x1a, 0}, + /*( 710) NOP*/ { 9, 18, 0x1b, 0}, + /*( 711) NOP*/ { 9, 18, 0x1e, 0}, + /*( 712) NOP*/ { 15, 19, 0x1e, 152}, + /*( 713) NOP*/ { 19, 19, 0x1e, 8}, + /*( 714) NOP*/ { 15, 19, 0x1e, 155}, + /*( 715) NOP*/ { 20, 19, 0x1e, 176}, + /*( 716) NOP*/ { 20, 19, 0x1e, 190}, + /*( 717) NOP*/ { 20, 19, 0x1e, 6}, + /*( 718) NOP*/ { 20, 19, 0x1e, 11}, + /*( 719) NOP*/ { 20, 19, 0x1e, 64}, + /*( 720) NOP*/ { 20, 19, 0x1e, 16}, + /*( 721) NOP*/ { 21, 19, 0x1e, 193}, + /*( 722) NOP*/ { 21, 19, 0x1e, 197}, + /*( 723) NOP*/ { 21, 19, 0x1e, 201}, + /*( 724) NOP*/ { 21, 19, 0x1e, 205}, + /*( 725) NOP*/ { 21, 19, 0x1e, 209}, + /*( 726) NOP*/ { 21, 19, 0x1e, 213}, + /*( 727) NOP*/ { 22, 19, 0x1e, 217}, + /*( 728) NOP*/ { 22, 19, 0x1e, 222}, + /*( 729) NOP*/ { 23, 19, 0x1e, 173}, + /*( 730) NOP*/ { 23, 19, 0x1e, 227}, + /*( 731) NOP*/ { 11, 18, 0x1c, 125}, + /*( 732) NOP*/ { 11, 18, 0x1c, 0}, + /*( 733) NOP*/ { 10, 18, 0x1c, 187}, + /*( 734) NOP*/ { 0, 18, 0x1c, 3}, + /*( 735) NOP*/ { 0, 18, 0x1c, 9}, + /*( 736) NOP*/ { 0, 18, 0x1c, 1}, + /*( 737) NOP*/ { 0, 18, 0x1c, 10}, + /*( 738) NOP*/ { 0, 18, 0x1c, 14}, + /*( 739) NOP*/ { 0, 18, 0x1c, 15}, + /*( 740) NOP*/ { 0, 18, 0x1c, 19}, + /*( 741) NOP*/ { 8, 19, 0x1c, 1}, + /*( 742) NOP*/ { 24, 18, 0x1c, 181}, + /*( 743) VMCALL*/ { 25, 19, 0x1, 232}, + /*( 744) VMLAUNCH*/ { 25, 19, 0x1, 237}, + /*( 745) VMRESUME*/ { 25, 19, 0x1, 242}, + /*( 746) VMXOFF*/ { 25, 19, 0x1, 247}, + /*( 747) SGDT*/ { 0, 31, 0x1, 0}, + /*( 748) SGDT*/ { 0, 18, 0x1, 0}, + /*( 749) LIDT*/ { 0, 31, 0x1, 1}, + /*( 750) LIDT*/ { 0, 18, 0x1, 1}, + /*( 751) MONITOR*/ { 25, 19, 0x1, 252}, + /*( 752) MONITOR*/ { 25, 19, 0x1, 252}, + /*( 753) MONITOR*/ { 25, 19, 0x1, 252}, + /*( 754) MONITOR*/ { 25, 19, 0x1, 252}, + /*( 755) MWAIT*/ { 25, 19, 0x1, 257}, + /*( 756) SIDT*/ { 0, 18, 0x1, 3}, + /*( 757) SIDT*/ { 0, 31, 0x1, 3}, + /*( 758) INVLPG*/ { 0, 18, 0x1, 19}, + /*( 759) SWAPGS*/ { 5, 19, 0x1, 18}, + /*( 760) RDTSCP*/ { 5, 19, 0x1, 94}, + /*( 761) SFENCE*/ { 13, 19, 0xae, 262}, + /*( 762) CLFLUSH*/ { 10, 18, 0xae, 133}, + /*( 763) LFENCE*/ { 13, 19, 0xae, 266}, + /*( 764) MFENCE*/ { 13, 19, 0xae, 166}, + /*( 765) MOVHLPS*/ { 15, 19, 0x12, 152}, + /*( 766) MOVLPS*/ { 14, 18, 0x12, 26}, + /*( 767) MOVLPS*/ { 14, 18, 0x13, 26}, + /*( 768) MOVLHPS*/ { 15, 19, 0x16, 152}, + /*( 769) MOVHPS*/ { 14, 18, 0x16, 26}, + /*( 770) MOVHPS*/ { 14, 18, 0x17, 26}, + /*( 771) DAA*/ { 9, 13, 0x27, 0}, + /*( 772) DAS*/ { 9, 13, 0x2f, 0}, + /*( 773) AAA*/ { 9, 13, 0x37, 0}, + /*( 774) AAS*/ { 9, 13, 0x3f, 0}, + /*( 775) PUSHA*/ { 26, 13, 0x60, 0}, + /*( 776) PUSHA*/ { 26, 13, 0x60, 3}, + /*( 777) PUSHAD*/ { 26, 13, 0x60, 3}, + /*( 778) PUSHAD*/ { 26, 13, 0x60, 0}, + /*( 779) POPA*/ { 26, 13, 0x61, 0}, + /*( 780) POPA*/ { 26, 13, 0x61, 3}, + /*( 781) POPAD*/ { 26, 13, 0x61, 3}, + /*( 782) POPAD*/ { 26, 13, 0x61, 0}, + /*( 783) BOUND*/ { 26, 0, 0x62, 0}, + /*( 784) BOUND*/ { 26, 0, 0x62, 3}, + /*( 785) BOUND*/ { 26, 0, 0x62, 3}, + /*( 786) BOUND*/ { 26, 0, 0x62, 0}, + /*( 787) ARPL*/ { 9, 0, 0x63, 0}, + /*( 788) ARPL*/ { 8, 1, 0x63, 1}, + /*( 789) MOVSXD*/ { 9, 0, 0x63, 0}, + /*( 790) MOVSXD*/ { 8, 1, 0x63, 1}, + /*( 791) REP_INSB*/ { 27, 13, 0x6c, 1}, + /*( 792) REP_INSB*/ { 27, 13, 0x6c, 9}, + /*( 793) INSB*/ { 27, 13, 0x6c, 0}, + /*( 794) REP_INSW*/ { 14, 13, 0x6d, 0}, + /*( 795) REP_INSW*/ { 14, 13, 0x6d, 3}, + /*( 796) REP_INSW*/ { 28, 13, 0x6d, 143}, + /*( 797) REP_INSW*/ { 14, 13, 0x6d, 125}, + /*( 798) REP_INSW*/ { 14, 13, 0x6d, 123}, + /*( 799) REP_INSW*/ { 28, 13, 0x6d, 123}, + /*( 800) INSW*/ { 14, 13, 0x6d, 26}, + /*( 801) INSW*/ { 14, 13, 0x6d, 121}, + /*( 802) INSW*/ { 28, 13, 0x6d, 187}, + /*( 803) REP_INSD*/ { 14, 13, 0x6d, 3}, + /*( 804) REP_INSD*/ { 14, 13, 0x6d, 0}, + /*( 805) REP_INSD*/ { 28, 13, 0x6d, 0}, + /*( 806) REP_INSD*/ { 29, 13, 0x6d, 4}, + /*( 807) REP_INSD*/ { 14, 13, 0x6d, 123}, + /*( 808) REP_INSD*/ { 14, 13, 0x6d, 125}, + /*( 809) REP_INSD*/ { 28, 13, 0x6d, 145}, + /*( 810) REP_INSD*/ { 29, 13, 0x6d, 126}, + /*( 811) INSD*/ { 14, 13, 0x6d, 121}, + /*( 812) INSD*/ { 14, 13, 0x6d, 26}, + /*( 813) INSD*/ { 28, 13, 0x6d, 181}, + /*( 814) INSD*/ { 29, 13, 0x6d, 2}, + /*( 815) REP_OUTSB*/ { 27, 42, 0x6e, 1}, + /*( 816) REP_OUTSB*/ { 27, 42, 0x6e, 9}, + /*( 817) OUTSB*/ { 27, 42, 0x6e, 0}, + /*( 818) REP_OUTSW*/ { 14, 42, 0x6f, 0}, + /*( 819) REP_OUTSW*/ { 14, 42, 0x6f, 3}, + /*( 820) REP_OUTSW*/ { 28, 42, 0x6f, 143}, + /*( 821) REP_OUTSW*/ { 14, 42, 0x6f, 125}, + /*( 822) REP_OUTSW*/ { 14, 42, 0x6f, 123}, + /*( 823) REP_OUTSW*/ { 28, 42, 0x6f, 123}, + /*( 824) OUTSW*/ { 14, 42, 0x6f, 26}, + /*( 825) OUTSW*/ { 14, 42, 0x6f, 121}, + /*( 826) OUTSW*/ { 28, 42, 0x6f, 187}, + /*( 827) REP_OUTSD*/ { 14, 42, 0x6f, 3}, + /*( 828) REP_OUTSD*/ { 14, 42, 0x6f, 0}, + /*( 829) REP_OUTSD*/ { 28, 42, 0x6f, 0}, + /*( 830) REP_OUTSD*/ { 29, 42, 0x6f, 4}, + /*( 831) REP_OUTSD*/ { 14, 42, 0x6f, 123}, + /*( 832) REP_OUTSD*/ { 14, 42, 0x6f, 125}, + /*( 833) REP_OUTSD*/ { 28, 42, 0x6f, 145}, + /*( 834) REP_OUTSD*/ { 29, 42, 0x6f, 126}, + /*( 835) OUTSD*/ { 14, 42, 0x6f, 121}, + /*( 836) OUTSD*/ { 14, 42, 0x6f, 26}, + /*( 837) OUTSD*/ { 28, 42, 0x6f, 181}, + /*( 838) OUTSD*/ { 29, 42, 0x6f, 2}, + /*( 839) JO*/ { 9, 43, 0x70, 0}, + /*( 840) JO*/ { 9, 44, 0x70, 0}, + /*( 841) JO*/ { 9, 45, 0x80, 0}, + /*( 842) JO*/ { 9, 46, 0x80, 0}, + /*( 843) JNO*/ { 9, 43, 0x71, 0}, + /*( 844) JNO*/ { 9, 44, 0x71, 0}, + /*( 845) JNO*/ { 9, 46, 0x81, 0}, + /*( 846) JNO*/ { 9, 45, 0x81, 0}, + /*( 847) JB*/ { 9, 43, 0x72, 0}, + /*( 848) JB*/ { 9, 44, 0x72, 0}, + /*( 849) JB*/ { 9, 46, 0x82, 0}, + /*( 850) JB*/ { 9, 45, 0x82, 0}, + /*( 851) JNB*/ { 9, 43, 0x73, 0}, + /*( 852) JNB*/ { 9, 44, 0x73, 0}, + /*( 853) JNB*/ { 9, 46, 0x83, 0}, + /*( 854) JNB*/ { 9, 45, 0x83, 0}, + /*( 855) JZ*/ { 9, 43, 0x74, 0}, + /*( 856) JZ*/ { 9, 44, 0x74, 0}, + /*( 857) JZ*/ { 9, 46, 0x84, 0}, + /*( 858) JZ*/ { 9, 45, 0x84, 0}, + /*( 859) JNZ*/ { 9, 43, 0x75, 0}, + /*( 860) JNZ*/ { 9, 44, 0x75, 0}, + /*( 861) JNZ*/ { 9, 46, 0x85, 0}, + /*( 862) JNZ*/ { 9, 45, 0x85, 0}, + /*( 863) JBE*/ { 9, 43, 0x76, 0}, + /*( 864) JBE*/ { 9, 44, 0x76, 0}, + /*( 865) JBE*/ { 9, 46, 0x86, 0}, + /*( 866) JBE*/ { 9, 45, 0x86, 0}, + /*( 867) JNBE*/ { 9, 43, 0x77, 0}, + /*( 868) JNBE*/ { 9, 44, 0x77, 0}, + /*( 869) JNBE*/ { 9, 46, 0x87, 0}, + /*( 870) JNBE*/ { 9, 45, 0x87, 0}, + /*( 871) JS*/ { 9, 43, 0x78, 0}, + /*( 872) JS*/ { 9, 44, 0x78, 0}, + /*( 873) JS*/ { 9, 46, 0x88, 0}, + /*( 874) JS*/ { 9, 45, 0x88, 0}, + /*( 875) JNS*/ { 9, 43, 0x79, 0}, + /*( 876) JNS*/ { 9, 44, 0x79, 0}, + /*( 877) JNS*/ { 9, 46, 0x89, 0}, + /*( 878) JNS*/ { 9, 45, 0x89, 0}, + /*( 879) JP*/ { 9, 43, 0x7a, 0}, + /*( 880) JP*/ { 9, 44, 0x7a, 0}, + /*( 881) JP*/ { 9, 46, 0x8a, 0}, + /*( 882) JP*/ { 9, 45, 0x8a, 0}, + /*( 883) JNP*/ { 9, 43, 0x7b, 0}, + /*( 884) JNP*/ { 9, 44, 0x7b, 0}, + /*( 885) JNP*/ { 9, 46, 0x8b, 0}, + /*( 886) JNP*/ { 9, 45, 0x8b, 0}, + /*( 887) JL*/ { 9, 43, 0x7c, 0}, + /*( 888) JL*/ { 9, 44, 0x7c, 0}, + /*( 889) JL*/ { 9, 46, 0x8c, 0}, + /*( 890) JL*/ { 9, 45, 0x8c, 0}, + /*( 891) JNL*/ { 9, 43, 0x7d, 0}, + /*( 892) JNL*/ { 9, 44, 0x7d, 0}, + /*( 893) JNL*/ { 9, 46, 0x8d, 0}, + /*( 894) JNL*/ { 9, 45, 0x8d, 0}, + /*( 895) JLE*/ { 9, 43, 0x7e, 0}, + /*( 896) JLE*/ { 9, 44, 0x7e, 0}, + /*( 897) JLE*/ { 9, 46, 0x8e, 0}, + /*( 898) JLE*/ { 9, 45, 0x8e, 0}, + /*( 899) JNLE*/ { 9, 43, 0x7f, 0}, + /*( 900) JNLE*/ { 9, 44, 0x7f, 0}, + /*( 901) JNLE*/ { 9, 46, 0x8f, 0}, + /*( 902) JNLE*/ { 9, 45, 0x8f, 0}, + /*( 903) XCHG*/ { 7, 0, 0x86, 3}, + /*( 904) XCHG*/ { 7, 0, 0x86, 0}, + /*( 905) XCHG*/ { 8, 1, 0x86, 1}, + /*( 906) XCHG*/ { 7, 0, 0x87, 3}, + /*( 907) XCHG*/ { 7, 0, 0x87, 0}, + /*( 908) XCHG*/ { 8, 1, 0x87, 1}, + /*( 909) XCHG*/ { 9, 20, 0x12, 0}, + /*( 910) XCHG*/ { 30, 20, 0x12, 121}, + /*( 911) LEA*/ { 9, 47, 0x8d, 0}, + /*( 912) PAUSE*/ { 18, 20, 0x12, 143}, + /*( 913) CBW*/ { 26, 13, 0x98, 0}, + /*( 914) CBW*/ { 26, 13, 0x98, 3}, + /*( 915) CBW*/ { 31, 13, 0x98, 121}, + /*( 916) CDQE*/ { 32, 13, 0x98, 3}, + /*( 917) CWDE*/ { 26, 13, 0x98, 3}, + /*( 918) CWDE*/ { 26, 13, 0x98, 0}, + /*( 919) CWDE*/ { 31, 13, 0x98, 26}, + /*( 920) CWD*/ { 26, 13, 0x99, 0}, + /*( 921) CWD*/ { 26, 13, 0x99, 3}, + /*( 922) CWD*/ { 31, 13, 0x99, 121}, + /*( 923) CQO*/ { 32, 13, 0x99, 3}, + /*( 924) CDQ*/ { 26, 13, 0x99, 3}, + /*( 925) CDQ*/ { 26, 13, 0x99, 0}, + /*( 926) CDQ*/ { 31, 13, 0x99, 26}, + /*( 927) CALL_FAR*/ { 0, 0, 0xff, 1}, + /*( 928) CALL_FAR*/ { 9, 28, 0x9a, 0}, + /*( 929) FWAIT*/ { 9, 13, 0x9b, 0}, + /*( 930) PUSHF*/ { 26, 13, 0x9c, 0}, + /*( 931) PUSHF*/ { 26, 13, 0x9c, 3}, + /*( 932) PUSHF*/ { 31, 13, 0x9c, 121}, + /*( 933) PUSHFD*/ { 26, 13, 0x9c, 0}, + /*( 934) PUSHFD*/ { 26, 13, 0x9c, 3}, + /*( 935) PUSHFQ*/ { 31, 48, 0x9c, 26}, + /*( 936) PUSHFQ*/ { 32, 48, 0x9c, 3}, + /*( 937) POPF*/ { 26, 13, 0x9d, 0}, + /*( 938) POPF*/ { 26, 13, 0x9d, 3}, + /*( 939) POPF*/ { 31, 13, 0x9d, 121}, + /*( 940) POPFD*/ { 26, 13, 0x9d, 3}, + /*( 941) POPFD*/ { 26, 13, 0x9d, 0}, + /*( 942) POPFQ*/ { 31, 48, 0x9d, 26}, + /*( 943) POPFQ*/ { 32, 48, 0x9d, 3}, + /*( 944) SAHF*/ { 9, 13, 0x9e, 0}, + /*( 945) LAHF*/ { 9, 13, 0x9f, 0}, + /*( 946) REP_MOVSB*/ { 27, 49, 0xa4, 1}, + /*( 947) REP_MOVSB*/ { 27, 49, 0xa4, 9}, + /*( 948) MOVSB*/ { 27, 49, 0xa4, 0}, + /*( 949) REP_MOVSW*/ { 14, 49, 0xa5, 0}, + /*( 950) REP_MOVSW*/ { 14, 49, 0xa5, 3}, + /*( 951) REP_MOVSW*/ { 28, 49, 0xa5, 143}, + /*( 952) REP_MOVSW*/ { 14, 49, 0xa5, 125}, + /*( 953) REP_MOVSW*/ { 14, 49, 0xa5, 123}, + /*( 954) REP_MOVSW*/ { 28, 49, 0xa5, 123}, + /*( 955) MOVSW*/ { 14, 49, 0xa5, 26}, + /*( 956) MOVSW*/ { 14, 49, 0xa5, 121}, + /*( 957) MOVSW*/ { 28, 49, 0xa5, 187}, + /*( 958) REP_MOVSD*/ { 14, 49, 0xa5, 3}, + /*( 959) REP_MOVSD*/ { 14, 49, 0xa5, 0}, + /*( 960) REP_MOVSD*/ { 28, 49, 0xa5, 0}, + /*( 961) REP_MOVSD*/ { 14, 49, 0xa5, 123}, + /*( 962) REP_MOVSD*/ { 14, 49, 0xa5, 125}, + /*( 963) REP_MOVSD*/ { 28, 49, 0xa5, 145}, + /*( 964) MOVSD*/ { 14, 49, 0xa5, 121}, + /*( 965) MOVSD*/ { 14, 49, 0xa5, 26}, + /*( 966) MOVSD*/ { 28, 49, 0xa5, 181}, + /*( 967) REP_MOVSQ*/ { 29, 49, 0xa5, 4}, + /*( 968) REP_MOVSQ*/ { 29, 49, 0xa5, 126}, + /*( 969) MOVSQ*/ { 29, 49, 0xa5, 2}, + /*( 970) REPE_CMPSB*/ { 27, 42, 0xa6, 1}, + /*( 971) REPNE_CMPSB*/ { 27, 42, 0xa6, 9}, + /*( 972) CMPSB*/ { 27, 42, 0xa6, 0}, + /*( 973) REPE_CMPSW*/ { 14, 42, 0xa7, 0}, + /*( 974) REPE_CMPSW*/ { 14, 42, 0xa7, 3}, + /*( 975) REPE_CMPSW*/ { 28, 42, 0xa7, 143}, + /*( 976) REPNE_CMPSW*/ { 14, 42, 0xa7, 125}, + /*( 977) REPNE_CMPSW*/ { 14, 42, 0xa7, 123}, + /*( 978) REPNE_CMPSW*/ { 28, 42, 0xa7, 123}, + /*( 979) CMPSW*/ { 14, 42, 0xa7, 26}, + /*( 980) CMPSW*/ { 14, 42, 0xa7, 121}, + /*( 981) CMPSW*/ { 28, 42, 0xa7, 187}, + /*( 982) REPE_CMPSD*/ { 14, 42, 0xa7, 3}, + /*( 983) REPE_CMPSD*/ { 14, 42, 0xa7, 0}, + /*( 984) REPE_CMPSD*/ { 28, 42, 0xa7, 0}, + /*( 985) REPNE_CMPSD*/ { 14, 42, 0xa7, 123}, + /*( 986) REPNE_CMPSD*/ { 14, 42, 0xa7, 125}, + /*( 987) REPNE_CMPSD*/ { 28, 42, 0xa7, 145}, + /*( 988) CMPSD*/ { 14, 42, 0xa7, 121}, + /*( 989) CMPSD*/ { 14, 42, 0xa7, 26}, + /*( 990) CMPSD*/ { 28, 42, 0xa7, 181}, + /*( 991) REPE_CMPSQ*/ { 29, 42, 0xa7, 4}, + /*( 992) REPNE_CMPSQ*/ { 29, 42, 0xa7, 126}, + /*( 993) CMPSQ*/ { 29, 42, 0xa7, 2}, + /*( 994) REP_STOSB*/ { 27, 13, 0xaa, 1}, + /*( 995) REP_STOSB*/ { 27, 13, 0xaa, 9}, + /*( 996) STOSB*/ { 27, 13, 0xaa, 0}, + /*( 997) REP_STOSW*/ { 14, 13, 0xab, 0}, + /*( 998) REP_STOSW*/ { 14, 13, 0xab, 3}, + /*( 999) REP_STOSW*/ { 28, 13, 0xab, 143}, + /*(1000) REP_STOSW*/ { 14, 13, 0xab, 125}, + /*(1001) REP_STOSW*/ { 14, 13, 0xab, 123}, + /*(1002) REP_STOSW*/ { 28, 13, 0xab, 123}, + /*(1003) STOSW*/ { 14, 13, 0xab, 26}, + /*(1004) STOSW*/ { 14, 13, 0xab, 121}, + /*(1005) STOSW*/ { 28, 13, 0xab, 187}, + /*(1006) REP_STOSD*/ { 14, 13, 0xab, 3}, + /*(1007) REP_STOSD*/ { 14, 13, 0xab, 0}, + /*(1008) REP_STOSD*/ { 28, 13, 0xab, 0}, + /*(1009) REP_STOSD*/ { 14, 13, 0xab, 123}, + /*(1010) REP_STOSD*/ { 14, 13, 0xab, 125}, + /*(1011) REP_STOSD*/ { 28, 13, 0xab, 145}, + /*(1012) STOSD*/ { 14, 13, 0xab, 121}, + /*(1013) STOSD*/ { 14, 13, 0xab, 26}, + /*(1014) STOSD*/ { 28, 13, 0xab, 181}, + /*(1015) REP_STOSQ*/ { 29, 13, 0xab, 4}, + /*(1016) REP_STOSQ*/ { 29, 13, 0xab, 126}, + /*(1017) STOSQ*/ { 29, 13, 0xab, 2}, + /*(1018) REP_LODSB*/ { 27, 42, 0xac, 1}, + /*(1019) REP_LODSB*/ { 27, 42, 0xac, 9}, + /*(1020) LODSB*/ { 27, 42, 0xac, 0}, + /*(1021) REP_LODSW*/ { 14, 42, 0xad, 0}, + /*(1022) REP_LODSW*/ { 14, 42, 0xad, 3}, + /*(1023) REP_LODSW*/ { 28, 42, 0xad, 143}, + /*(1024) REP_LODSW*/ { 14, 42, 0xad, 125}, + /*(1025) REP_LODSW*/ { 14, 42, 0xad, 123}, + /*(1026) REP_LODSW*/ { 28, 42, 0xad, 123}, + /*(1027) LODSW*/ { 14, 42, 0xad, 26}, + /*(1028) LODSW*/ { 14, 42, 0xad, 121}, + /*(1029) LODSW*/ { 28, 42, 0xad, 187}, + /*(1030) REP_LODSD*/ { 14, 42, 0xad, 3}, + /*(1031) REP_LODSD*/ { 14, 42, 0xad, 0}, + /*(1032) REP_LODSD*/ { 28, 42, 0xad, 0}, + /*(1033) REP_LODSD*/ { 14, 42, 0xad, 123}, + /*(1034) REP_LODSD*/ { 14, 42, 0xad, 125}, + /*(1035) REP_LODSD*/ { 28, 42, 0xad, 145}, + /*(1036) LODSD*/ { 14, 42, 0xad, 121}, + /*(1037) LODSD*/ { 14, 42, 0xad, 26}, + /*(1038) LODSD*/ { 28, 42, 0xad, 181}, + /*(1039) REP_LODSQ*/ { 29, 42, 0xad, 4}, + /*(1040) REP_LODSQ*/ { 29, 42, 0xad, 126}, + /*(1041) LODSQ*/ { 29, 42, 0xad, 2}, + /*(1042) REPE_SCASB*/ { 27, 13, 0xae, 1}, + /*(1043) REPNE_SCASB*/ { 27, 13, 0xae, 9}, + /*(1044) SCASB*/ { 27, 13, 0xae, 0}, + /*(1045) REPE_SCASW*/ { 14, 13, 0xaf, 0}, + /*(1046) REPE_SCASW*/ { 14, 13, 0xaf, 3}, + /*(1047) REPE_SCASW*/ { 28, 13, 0xaf, 143}, + /*(1048) REPNE_SCASW*/ { 14, 13, 0xaf, 125}, + /*(1049) REPNE_SCASW*/ { 14, 13, 0xaf, 123}, + /*(1050) REPNE_SCASW*/ { 28, 13, 0xaf, 123}, + /*(1051) SCASW*/ { 14, 13, 0xaf, 26}, + /*(1052) SCASW*/ { 14, 13, 0xaf, 121}, + /*(1053) SCASW*/ { 28, 13, 0xaf, 187}, + /*(1054) REPE_SCASD*/ { 14, 13, 0xaf, 3}, + /*(1055) REPE_SCASD*/ { 14, 13, 0xaf, 0}, + /*(1056) REPE_SCASD*/ { 28, 13, 0xaf, 0}, + /*(1057) REPNE_SCASD*/ { 14, 13, 0xaf, 123}, + /*(1058) REPNE_SCASD*/ { 14, 13, 0xaf, 125}, + /*(1059) REPNE_SCASD*/ { 28, 13, 0xaf, 145}, + /*(1060) SCASD*/ { 14, 13, 0xaf, 121}, + /*(1061) SCASD*/ { 14, 13, 0xaf, 26}, + /*(1062) SCASD*/ { 28, 13, 0xaf, 181}, + /*(1063) REPE_SCASQ*/ { 29, 13, 0xaf, 4}, + /*(1064) REPNE_SCASQ*/ { 29, 13, 0xaf, 126}, + /*(1065) SCASQ*/ { 29, 13, 0xaf, 2}, + /*(1066) RET_NEAR*/ { 9, 50, 0xc2, 0}, + /*(1067) RET_NEAR*/ { 9, 51, 0xc3, 0}, + /*(1068) LES*/ { 9, 0, 0xc4, 0}, + /*(1069) LDS*/ { 9, 0, 0xc5, 0}, + /*(1070) ENTER*/ { 9, 52, 0xc8, 0}, + /*(1071) LEAVE*/ { 9, 48, 0xc9, 0}, + /*(1072) RET_FAR*/ { 9, 53, 0xca, 0}, + /*(1073) RET_FAR*/ { 9, 13, 0xcb, 0}, + /*(1074) INT3*/ { 9, 13, 0xcc, 0}, + /*(1075) INT*/ { 9, 8, 0xcd, 0}, + /*(1076) INTO*/ { 9, 13, 0xce, 0}, + /*(1077) IRET*/ { 26, 13, 0xcf, 0}, + /*(1078) IRET*/ { 26, 13, 0xcf, 3}, + /*(1079) IRET*/ { 31, 13, 0xcf, 121}, + /*(1080) IRETD*/ { 26, 13, 0xcf, 3}, + /*(1081) IRETD*/ { 26, 13, 0xcf, 0}, + /*(1082) IRETD*/ { 31, 13, 0xcf, 26}, + /*(1083) IRETQ*/ { 32, 13, 0xcf, 3}, + /*(1084) AAM*/ { 9, 8, 0xd4, 0}, + /*(1085) AAD*/ { 9, 8, 0xd5, 0}, + /*(1086) SALC*/ { 9, 13, 0xd6, 0}, + /*(1087) XLAT*/ { 9, 42, 0xd7, 0}, + /*(1088) LOOPNE*/ { 27, 54, 0xe0, 0}, + /*(1089) LOOPNE*/ { 27, 54, 0xe0, 9}, + /*(1090) LOOPNE*/ { 9, 54, 0xe0, 0}, + /*(1091) LOOPNE*/ { 27, 54, 0xe1, 9}, + /*(1092) LOOPE*/ { 27, 54, 0xe1, 0}, + /*(1093) LOOPE*/ { 27, 54, 0xe1, 1}, + /*(1094) LOOPE*/ { 9, 54, 0xe1, 0}, + /*(1095) LOOPE*/ { 27, 54, 0xe0, 1}, + /*(1096) LOOP*/ { 9, 54, 0xe2, 0}, + /*(1097) JCXZ*/ { 9, 26, 0xe3, 0}, + /*(1098) JECXZ*/ { 9, 26, 0xe3, 0}, + /*(1099) JECXZ*/ { 9, 55, 0xe3, 0}, + /*(1100) JRCXZ*/ { 9, 55, 0xe3, 0}, + /*(1101) IN*/ { 9, 8, 0xe4, 0}, + /*(1102) IN*/ { 9, 56, 0xe5, 0}, + /*(1103) IN*/ { 9, 13, 0xec, 0}, + /*(1104) IN*/ { 9, 57, 0xed, 0}, + /*(1105) OUT*/ { 9, 8, 0xe6, 0}, + /*(1106) OUT*/ { 9, 56, 0xe7, 0}, + /*(1107) OUT*/ { 9, 13, 0xee, 0}, + /*(1108) OUT*/ { 9, 57, 0xef, 0}, + /*(1109) INT1*/ { 9, 13, 0xf1, 0}, + /*(1110) HLT*/ { 9, 13, 0xf4, 0}, + /*(1111) CMC*/ { 9, 13, 0xf5, 0}, + /*(1112) CLC*/ { 9, 13, 0xf8, 0}, + /*(1113) STC*/ { 9, 13, 0xf9, 0}, + /*(1114) CLI*/ { 9, 13, 0xfa, 0}, + /*(1115) STI*/ { 9, 13, 0xfb, 0}, + /*(1116) CLD*/ { 9, 13, 0xfc, 0}, + /*(1117) STD*/ { 9, 13, 0xfd, 0}, + /*(1118) LAR*/ { 9, 18, 0x2, 0}, + /*(1119) LAR*/ { 8, 19, 0x2, 1}, + /*(1120) LSL*/ { 9, 18, 0x3, 0}, + /*(1121) LSL*/ { 8, 19, 0x3, 1}, + /*(1122) SYSCALL*/ { 9, 58, 0x5, 0}, + /*(1123) CLTS*/ { 9, 59, 0x6, 0}, + /*(1124) SYSRET*/ { 32, 59, 0x7, 0}, + /*(1125) SYSRET64*/ { 32, 59, 0x7, 3}, + /*(1126) MOVUPS*/ { 14, 18, 0x10, 26}, + /*(1127) MOVUPS*/ { 15, 19, 0x10, 152}, + /*(1128) MOVUPS*/ { 14, 18, 0x11, 26}, + /*(1129) MOVUPS*/ { 15, 19, 0x11, 152}, + /*(1130) UNPCKLPS*/ { 14, 18, 0x14, 26}, + /*(1131) UNPCKLPS*/ { 15, 19, 0x14, 152}, + /*(1132) UNPCKHPS*/ { 14, 18, 0x15, 26}, + /*(1133) UNPCKHPS*/ { 15, 19, 0x15, 152}, + /*(1134) MOVSS*/ { 27, 35, 0x10, 1}, + /*(1135) MOVSS*/ { 19, 60, 0x10, 6}, + /*(1136) MOVSS*/ { 27, 35, 0x11, 1}, + /*(1137) MOVSS*/ { 19, 60, 0x11, 6}, + /*(1138) MOVSLDUP*/ { 27, 35, 0x12, 1}, + /*(1139) MOVSLDUP*/ { 19, 60, 0x12, 6}, + /*(1140) MOVSHDUP*/ { 27, 35, 0x16, 1}, + /*(1141) MOVSHDUP*/ { 19, 60, 0x16, 6}, + /*(1142) MOVUPD*/ { 14, 34, 0x10, 121}, + /*(1143) MOVUPD*/ { 15, 41, 0x10, 155}, + /*(1144) MOVUPD*/ { 14, 34, 0x11, 121}, + /*(1145) MOVUPD*/ { 15, 41, 0x11, 155}, + /*(1146) MOVLPD*/ { 14, 34, 0x12, 121}, + /*(1147) MOVLPD*/ { 14, 34, 0x13, 121}, + /*(1148) UNPCKLPD*/ { 14, 34, 0x14, 121}, + /*(1149) UNPCKLPD*/ { 15, 41, 0x14, 155}, + /*(1150) UNPCKHPD*/ { 14, 34, 0x15, 121}, + /*(1151) UNPCKHPD*/ { 15, 41, 0x15, 155}, + /*(1152) MOVHPD*/ { 14, 34, 0x16, 121}, + /*(1153) MOVHPD*/ { 14, 34, 0x17, 121}, + /*(1154) MOVSD_XMM*/ { 27, 35, 0x10, 9}, + /*(1155) MOVSD_XMM*/ { 19, 60, 0x10, 8}, + /*(1156) MOVSD_XMM*/ { 27, 35, 0x11, 9}, + /*(1157) MOVSD_XMM*/ { 19, 60, 0x11, 8}, + /*(1158) MOVDDUP*/ { 27, 35, 0x12, 9}, + /*(1159) MOVDDUP*/ { 19, 60, 0x12, 8}, + /*(1160) MOV_CR*/ { 9, 61, 0x22, 0}, + /*(1161) MOV_CR*/ { 9, 61, 0x22, 0}, + /*(1162) MOV_CR*/ { 9, 61, 0x20, 0}, + /*(1163) MOV_CR*/ { 9, 61, 0x20, 0}, + /*(1164) MOV_DR*/ { 9, 61, 0x23, 0}, + /*(1165) MOV_DR*/ { 9, 61, 0x23, 0}, + /*(1166) MOV_DR*/ { 9, 61, 0x21, 0}, + /*(1167) MOV_DR*/ { 9, 61, 0x21, 0}, + /*(1168) WRMSR*/ { 9, 59, 0x30, 0}, + /*(1169) RDTSC*/ { 9, 59, 0x31, 0}, + /*(1170) RDMSR*/ { 9, 59, 0x32, 0}, + /*(1171) RDPMC*/ { 9, 59, 0x33, 0}, + /*(1172) SYSENTER*/ { 9, 59, 0x34, 0}, + /*(1173) SYSENTER*/ { 9, 59, 0x34, 0}, + /*(1174) SYSEXIT*/ { 9, 59, 0x35, 0}, + /*(1175) SYSEXIT*/ { 9, 59, 0x35, 0}, + /*(1176) CMOVO*/ { 9, 18, 0x40, 0}, + /*(1177) CMOVO*/ { 8, 19, 0x40, 1}, + /*(1178) CMOVNO*/ { 9, 18, 0x41, 0}, + /*(1179) CMOVNO*/ { 8, 19, 0x41, 1}, + /*(1180) CMOVB*/ { 9, 18, 0x42, 0}, + /*(1181) CMOVB*/ { 8, 19, 0x42, 1}, + /*(1182) CMOVNB*/ { 9, 18, 0x43, 0}, + /*(1183) CMOVNB*/ { 8, 19, 0x43, 1}, + /*(1184) CMOVZ*/ { 9, 18, 0x44, 0}, + /*(1185) CMOVZ*/ { 8, 19, 0x44, 1}, + /*(1186) CMOVNZ*/ { 9, 18, 0x45, 0}, + /*(1187) CMOVNZ*/ { 8, 19, 0x45, 1}, + /*(1188) CMOVBE*/ { 9, 18, 0x46, 0}, + /*(1189) CMOVBE*/ { 8, 19, 0x46, 1}, + /*(1190) CMOVNBE*/ { 9, 18, 0x47, 0}, + /*(1191) CMOVNBE*/ { 8, 19, 0x47, 1}, + /*(1192) MOVMSKPS*/ { 15, 19, 0x50, 152}, + /*(1193) SQRTPS*/ { 14, 18, 0x51, 26}, + /*(1194) SQRTPS*/ { 15, 19, 0x51, 152}, + /*(1195) RSQRTPS*/ { 14, 18, 0x52, 26}, + /*(1196) RSQRTPS*/ { 15, 19, 0x52, 152}, + /*(1197) RCPPS*/ { 14, 18, 0x53, 26}, + /*(1198) RCPPS*/ { 15, 19, 0x53, 152}, + /*(1199) ANDPS*/ { 14, 18, 0x54, 26}, + /*(1200) ANDPS*/ { 15, 19, 0x54, 152}, + /*(1201) ANDNPS*/ { 14, 18, 0x55, 26}, + /*(1202) ANDNPS*/ { 15, 19, 0x55, 152}, + /*(1203) ORPS*/ { 14, 18, 0x56, 26}, + /*(1204) ORPS*/ { 15, 19, 0x56, 152}, + /*(1205) XORPS*/ { 14, 18, 0x57, 26}, + /*(1206) XORPS*/ { 15, 19, 0x57, 152}, + /*(1207) SQRTSS*/ { 27, 35, 0x51, 1}, + /*(1208) SQRTSS*/ { 19, 60, 0x51, 6}, + /*(1209) RSQRTSS*/ { 27, 35, 0x52, 1}, + /*(1210) RSQRTSS*/ { 19, 60, 0x52, 6}, + /*(1211) RCPSS*/ { 27, 35, 0x53, 1}, + /*(1212) RCPSS*/ { 19, 60, 0x53, 6}, + /*(1213) MOVMSKPD*/ { 15, 41, 0x50, 155}, + /*(1214) SQRTPD*/ { 14, 34, 0x51, 121}, + /*(1215) SQRTPD*/ { 15, 41, 0x51, 155}, + /*(1216) ANDPD*/ { 14, 34, 0x54, 121}, + /*(1217) ANDPD*/ { 15, 41, 0x54, 155}, + /*(1218) ANDNPD*/ { 14, 34, 0x55, 121}, + /*(1219) ANDNPD*/ { 15, 41, 0x55, 155}, + /*(1220) ORPD*/ { 14, 34, 0x56, 121}, + /*(1221) ORPD*/ { 15, 41, 0x56, 155}, + /*(1222) XORPD*/ { 14, 34, 0x57, 121}, + /*(1223) XORPD*/ { 15, 41, 0x57, 155}, + /*(1224) SQRTSD*/ { 27, 35, 0x51, 9}, + /*(1225) SQRTSD*/ { 19, 60, 0x51, 8}, + /*(1226) PUNPCKLBW*/ { 14, 18, 0x60, 26}, + /*(1227) PUNPCKLBW*/ { 15, 19, 0x60, 152}, + /*(1228) PUNPCKLBW*/ { 14, 34, 0x60, 121}, + /*(1229) PUNPCKLBW*/ { 15, 41, 0x60, 155}, + /*(1230) PUNPCKLWD*/ { 14, 18, 0x61, 26}, + /*(1231) PUNPCKLWD*/ { 15, 19, 0x61, 152}, + /*(1232) PUNPCKLWD*/ { 14, 34, 0x61, 121}, + /*(1233) PUNPCKLWD*/ { 15, 41, 0x61, 155}, + /*(1234) PUNPCKLDQ*/ { 14, 18, 0x62, 26}, + /*(1235) PUNPCKLDQ*/ { 15, 19, 0x62, 152}, + /*(1236) PUNPCKLDQ*/ { 14, 34, 0x62, 121}, + /*(1237) PUNPCKLDQ*/ { 15, 41, 0x62, 155}, + /*(1238) PACKSSWB*/ { 14, 18, 0x63, 26}, + /*(1239) PACKSSWB*/ { 15, 19, 0x63, 152}, + /*(1240) PACKSSWB*/ { 14, 34, 0x63, 121}, + /*(1241) PACKSSWB*/ { 15, 41, 0x63, 155}, + /*(1242) PCMPGTB*/ { 14, 18, 0x64, 26}, + /*(1243) PCMPGTB*/ { 15, 19, 0x64, 152}, + /*(1244) PCMPGTB*/ { 14, 34, 0x64, 121}, + /*(1245) PCMPGTB*/ { 15, 41, 0x64, 155}, + /*(1246) PCMPGTW*/ { 14, 18, 0x65, 26}, + /*(1247) PCMPGTW*/ { 15, 19, 0x65, 152}, + /*(1248) PCMPGTW*/ { 14, 34, 0x65, 121}, + /*(1249) PCMPGTW*/ { 15, 41, 0x65, 155}, + /*(1250) PCMPGTD*/ { 14, 18, 0x66, 26}, + /*(1251) PCMPGTD*/ { 15, 19, 0x66, 152}, + /*(1252) PCMPGTD*/ { 14, 34, 0x66, 121}, + /*(1253) PCMPGTD*/ { 15, 41, 0x66, 155}, + /*(1254) PACKUSWB*/ { 14, 18, 0x67, 26}, + /*(1255) PACKUSWB*/ { 15, 19, 0x67, 152}, + /*(1256) PACKUSWB*/ { 14, 34, 0x67, 121}, + /*(1257) PACKUSWB*/ { 15, 41, 0x67, 155}, + /*(1258) PSHUFW*/ { 14, 32, 0x70, 26}, + /*(1259) PSHUFW*/ { 15, 33, 0x70, 152}, + /*(1260) PCMPEQB*/ { 14, 18, 0x74, 26}, + /*(1261) PCMPEQB*/ { 15, 19, 0x74, 152}, + /*(1262) PCMPEQB*/ { 14, 34, 0x74, 121}, + /*(1263) PCMPEQB*/ { 15, 41, 0x74, 155}, + /*(1264) PCMPEQW*/ { 14, 18, 0x75, 26}, + /*(1265) PCMPEQW*/ { 15, 19, 0x75, 152}, + /*(1266) PCMPEQW*/ { 14, 34, 0x75, 121}, + /*(1267) PCMPEQW*/ { 15, 41, 0x75, 155}, + /*(1268) PCMPEQD*/ { 14, 18, 0x76, 26}, + /*(1269) PCMPEQD*/ { 15, 19, 0x76, 152}, + /*(1270) PCMPEQD*/ { 14, 34, 0x76, 121}, + /*(1271) PCMPEQD*/ { 15, 41, 0x76, 155}, + /*(1272) EMMS*/ { 14, 59, 0x77, 26}, + /*(1273) PSHUFD*/ { 14, 62, 0x70, 121}, + /*(1274) PSHUFD*/ { 15, 40, 0x70, 155}, + /*(1275) PSHUFLW*/ { 27, 63, 0x70, 9}, + /*(1276) PSHUFLW*/ { 19, 64, 0x70, 8}, + /*(1277) PSHUFHW*/ { 27, 63, 0x70, 1}, + /*(1278) PSHUFHW*/ { 19, 64, 0x70, 6}, + /*(1279) SETO*/ { 9, 18, 0x90, 0}, + /*(1280) SETO*/ { 8, 19, 0x90, 1}, + /*(1281) SETNO*/ { 9, 18, 0x91, 0}, + /*(1282) SETNO*/ { 8, 19, 0x91, 1}, + /*(1283) SETB*/ { 9, 18, 0x92, 0}, + /*(1284) SETB*/ { 8, 19, 0x92, 1}, + /*(1285) SETNB*/ { 9, 18, 0x93, 0}, + /*(1286) SETNB*/ { 8, 19, 0x93, 1}, + /*(1287) SETZ*/ { 9, 18, 0x94, 0}, + /*(1288) SETZ*/ { 8, 19, 0x94, 1}, + /*(1289) SETNZ*/ { 9, 18, 0x95, 0}, + /*(1290) SETNZ*/ { 8, 19, 0x95, 1}, + /*(1291) SETBE*/ { 9, 18, 0x96, 0}, + /*(1292) SETBE*/ { 8, 19, 0x96, 1}, + /*(1293) SETNBE*/ { 9, 18, 0x97, 0}, + /*(1294) SETNBE*/ { 8, 19, 0x97, 1}, + /*(1295) CPUID*/ { 9, 59, 0xa2, 0}, + /*(1296) CMPXCHG_LOCK*/ { 7, 18, 0xb0, 3}, + /*(1297) CMPXCHG_LOCK*/ { 7, 18, 0xb1, 3}, + /*(1298) CMPXCHG*/ { 7, 18, 0xb0, 0}, + /*(1299) CMPXCHG*/ { 8, 19, 0xb0, 1}, + /*(1300) CMPXCHG*/ { 7, 18, 0xb1, 0}, + /*(1301) CMPXCHG*/ { 8, 19, 0xb1, 1}, + /*(1302) LSS*/ { 9, 18, 0xb2, 0}, + /*(1303) LFS*/ { 9, 18, 0xb4, 0}, + /*(1304) LGS*/ { 9, 18, 0xb5, 0}, + /*(1305) MOVZX*/ { 9, 18, 0xb6, 0}, + /*(1306) MOVZX*/ { 8, 19, 0xb6, 1}, + /*(1307) MOVZX*/ { 9, 18, 0xb7, 0}, + /*(1308) MOVZX*/ { 8, 19, 0xb7, 1}, + /*(1309) XADD_LOCK*/ { 7, 18, 0xc0, 3}, + /*(1310) XADD_LOCK*/ { 7, 18, 0xc1, 3}, + /*(1311) XADD*/ { 7, 18, 0xc0, 0}, + /*(1312) XADD*/ { 8, 19, 0xc0, 1}, + /*(1313) XADD*/ { 7, 18, 0xc1, 0}, + /*(1314) XADD*/ { 8, 19, 0xc1, 1}, + /*(1315) CMPPS*/ { 14, 32, 0xc2, 26}, + /*(1316) CMPPS*/ { 15, 33, 0xc2, 152}, + /*(1317) MOVNTI*/ { 14, 18, 0xc3, 26}, + /*(1318) MOVNTI*/ { 28, 18, 0xc3, 181}, + /*(1319) MOVNTI*/ { 28, 18, 0xc3, 137}, + /*(1320) PINSRW*/ { 14, 32, 0xc4, 26}, + /*(1321) PINSRW*/ { 15, 33, 0xc4, 152}, + /*(1322) PINSRW*/ { 14, 62, 0xc4, 121}, + /*(1323) PINSRW*/ { 15, 40, 0xc4, 155}, + /*(1324) PEXTRW*/ { 15, 33, 0xc5, 152}, + /*(1325) PEXTRW*/ { 15, 40, 0xc5, 155}, + /*(1326) SHUFPS*/ { 14, 32, 0xc6, 26}, + /*(1327) SHUFPS*/ { 15, 33, 0xc6, 152}, + /*(1328) CMPSS*/ { 27, 63, 0xc2, 1}, + /*(1329) CMPSS*/ { 19, 64, 0xc2, 6}, + /*(1330) CMPPD*/ { 14, 62, 0xc2, 121}, + /*(1331) CMPPD*/ { 15, 40, 0xc2, 155}, + /*(1332) SHUFPD*/ { 14, 62, 0xc6, 121}, + /*(1333) SHUFPD*/ { 15, 40, 0xc6, 155}, + /*(1334) CMPSD_XMM*/ { 27, 63, 0xc2, 9}, + /*(1335) CMPSD_XMM*/ { 19, 64, 0xc2, 8}, + /*(1336) PADDQ*/ { 14, 18, 0xd4, 26}, + /*(1337) PADDQ*/ { 15, 19, 0xd4, 152}, + /*(1338) PADDQ*/ { 14, 34, 0xd4, 121}, + /*(1339) PADDQ*/ { 15, 41, 0xd4, 155}, + /*(1340) PMULLW*/ { 14, 18, 0xd5, 26}, + /*(1341) PMULLW*/ { 15, 19, 0xd5, 152}, + /*(1342) PMULLW*/ { 14, 34, 0xd5, 121}, + /*(1343) PMULLW*/ { 15, 41, 0xd5, 155}, + /*(1344) PMOVMSKB*/ { 15, 19, 0xd7, 152}, + /*(1345) PMOVMSKB*/ { 15, 41, 0xd7, 155}, + /*(1346) ADDSUBPD*/ { 14, 34, 0xd0, 121}, + /*(1347) ADDSUBPD*/ { 15, 41, 0xd0, 155}, + /*(1348) MOVQ2DQ*/ { 19, 60, 0xd6, 6}, + /*(1349) ADDSUBPS*/ { 27, 35, 0xd0, 9}, + /*(1350) ADDSUBPS*/ { 19, 60, 0xd0, 8}, + /*(1351) MOVDQ2Q*/ { 19, 60, 0xd6, 8}, + /*(1352) PAVGB*/ { 14, 18, 0xe0, 26}, + /*(1353) PAVGB*/ { 15, 19, 0xe0, 152}, + /*(1354) PAVGB*/ { 14, 34, 0xe0, 121}, + /*(1355) PAVGB*/ { 15, 41, 0xe0, 155}, + /*(1356) PAVGW*/ { 14, 18, 0xe3, 26}, + /*(1357) PAVGW*/ { 15, 19, 0xe3, 152}, + /*(1358) PAVGW*/ { 14, 34, 0xe3, 121}, + /*(1359) PAVGW*/ { 15, 41, 0xe3, 155}, + /*(1360) PMULHUW*/ { 14, 18, 0xe4, 26}, + /*(1361) PMULHUW*/ { 15, 19, 0xe4, 152}, + /*(1362) PMULHUW*/ { 14, 34, 0xe4, 121}, + /*(1363) PMULHUW*/ { 15, 41, 0xe4, 155}, + /*(1364) PMULHW*/ { 14, 18, 0xe5, 26}, + /*(1365) PMULHW*/ { 15, 19, 0xe5, 152}, + /*(1366) PMULHW*/ { 14, 34, 0xe5, 121}, + /*(1367) PMULHW*/ { 15, 41, 0xe5, 155}, + /*(1368) MOVNTQ*/ { 14, 18, 0xe7, 26}, + /*(1369) CVTTPD2DQ*/ { 14, 34, 0xe6, 121}, + /*(1370) CVTTPD2DQ*/ { 15, 41, 0xe6, 155}, + /*(1371) MOVNTDQ*/ { 14, 34, 0xe7, 121}, + /*(1372) CVTDQ2PD*/ { 27, 35, 0xe6, 1}, + /*(1373) CVTDQ2PD*/ { 19, 60, 0xe6, 6}, + /*(1374) CVTPD2DQ*/ { 27, 35, 0xe6, 9}, + /*(1375) CVTPD2DQ*/ { 19, 60, 0xe6, 8}, + /*(1376) PMULUDQ*/ { 14, 18, 0xf4, 26}, + /*(1377) PMULUDQ*/ { 15, 19, 0xf4, 152}, + /*(1378) PMULUDQ*/ { 14, 34, 0xf4, 121}, + /*(1379) PMULUDQ*/ { 15, 41, 0xf4, 155}, + /*(1380) PMADDWD*/ { 14, 18, 0xf5, 26}, + /*(1381) PMADDWD*/ { 15, 19, 0xf5, 152}, + /*(1382) PMADDWD*/ { 14, 34, 0xf5, 121}, + /*(1383) PMADDWD*/ { 15, 41, 0xf5, 155}, + /*(1384) PSADBW*/ { 14, 18, 0xf6, 26}, + /*(1385) PSADBW*/ { 15, 19, 0xf6, 152}, + /*(1386) PSADBW*/ { 14, 34, 0xf6, 121}, + /*(1387) PSADBW*/ { 15, 41, 0xf6, 155}, + /*(1388) MASKMOVQ*/ { 15, 65, 0xf7, 152}, + /*(1389) MASKMOVDQU*/ { 15, 66, 0xf7, 155}, + /*(1390) LDDQU*/ { 27, 35, 0xf0, 9}, + /*(1391) INVD*/ { 9, 59, 0x8, 0}, + /*(1392) WBINVD*/ { 9, 59, 0x9, 0}, + /*(1393) WBINVD*/ { 33, 59, 0x9, 0}, + /*(1394) WBINVD*/ { 33, 59, 0x9, 3}, + /*(1395) UD0*/ { 9, 59, 0xff, 0}, + /*(1396) UD0*/ { 9, 18, 0xff, 0}, + /*(1397) UD0*/ { 8, 19, 0xff, 1}, + /*(1398) UD1*/ { 9, 18, 0xb9, 0}, + /*(1399) UD1*/ { 8, 19, 0xb9, 1}, + /*(1400) UD2*/ { 9, 59, 0xb, 0}, + /*(1401) MOVAPS*/ { 14, 18, 0x28, 26}, + /*(1402) MOVAPS*/ { 15, 19, 0x28, 152}, + /*(1403) MOVAPS*/ { 14, 18, 0x29, 26}, + /*(1404) MOVAPS*/ { 15, 19, 0x29, 152}, + /*(1405) CVTPI2PS*/ { 14, 18, 0x2a, 26}, + /*(1406) CVTPI2PS*/ { 15, 19, 0x2a, 152}, + /*(1407) MOVNTPS*/ { 14, 18, 0x2b, 26}, + /*(1408) CVTTPS2PI*/ { 14, 18, 0x2c, 26}, + /*(1409) CVTTPS2PI*/ { 15, 19, 0x2c, 152}, + /*(1410) CVTPS2PI*/ { 14, 18, 0x2d, 26}, + /*(1411) CVTPS2PI*/ { 15, 19, 0x2d, 152}, + /*(1412) UCOMISS*/ { 14, 18, 0x2e, 26}, + /*(1413) UCOMISS*/ { 15, 19, 0x2e, 152}, + /*(1414) COMISS*/ { 14, 18, 0x2f, 26}, + /*(1415) COMISS*/ { 15, 19, 0x2f, 152}, + /*(1416) CVTSI2SS*/ { 29, 35, 0x2a, 1}, + /*(1417) CVTSI2SS*/ { 34, 60, 0x2a, 225}, + /*(1418) CVTSI2SS*/ { 29, 35, 0x2a, 4}, + /*(1419) CVTSI2SS*/ { 34, 60, 0x2a, 118}, + /*(1420) CVTTSS2SI*/ { 29, 35, 0x2c, 1}, + /*(1421) CVTTSS2SI*/ { 34, 60, 0x2c, 225}, + /*(1422) CVTTSS2SI*/ { 29, 35, 0x2c, 4}, + /*(1423) CVTTSS2SI*/ { 34, 60, 0x2c, 118}, + /*(1424) CVTSS2SI*/ { 29, 35, 0x2d, 1}, + /*(1425) CVTSS2SI*/ { 34, 60, 0x2d, 225}, + /*(1426) CVTSS2SI*/ { 29, 35, 0x2d, 4}, + /*(1427) CVTSS2SI*/ { 34, 60, 0x2d, 118}, + /*(1428) MOVAPD*/ { 14, 34, 0x28, 121}, + /*(1429) MOVAPD*/ { 15, 41, 0x28, 155}, + /*(1430) MOVAPD*/ { 14, 34, 0x29, 121}, + /*(1431) MOVAPD*/ { 15, 41, 0x29, 155}, + /*(1432) CVTPI2PD*/ { 14, 34, 0x2a, 121}, + /*(1433) CVTPI2PD*/ { 15, 41, 0x2a, 155}, + /*(1434) MOVNTPD*/ { 14, 67, 0x2b, 121}, + /*(1435) CVTTPD2PI*/ { 14, 34, 0x2c, 121}, + /*(1436) CVTTPD2PI*/ { 15, 41, 0x2c, 155}, + /*(1437) CVTPD2PI*/ { 14, 34, 0x2d, 121}, + /*(1438) CVTPD2PI*/ { 15, 41, 0x2d, 155}, + /*(1439) UCOMISD*/ { 14, 34, 0x2e, 121}, + /*(1440) UCOMISD*/ { 15, 41, 0x2e, 155}, + /*(1441) COMISD*/ { 14, 34, 0x2f, 121}, + /*(1442) COMISD*/ { 15, 41, 0x2f, 155}, + /*(1443) CVTSI2SD*/ { 29, 35, 0x2a, 41}, + /*(1444) CVTSI2SD*/ { 34, 60, 0x2a, 40}, + /*(1445) CVTSI2SD*/ { 29, 35, 0x2a, 126}, + /*(1446) CVTSI2SD*/ { 34, 60, 0x2a, 270}, + /*(1447) CVTTSD2SI*/ { 29, 35, 0x2c, 41}, + /*(1448) CVTTSD2SI*/ { 34, 60, 0x2c, 40}, + /*(1449) CVTTSD2SI*/ { 29, 35, 0x2c, 126}, + /*(1450) CVTTSD2SI*/ { 34, 60, 0x2c, 270}, + /*(1451) CVTSD2SI*/ { 29, 35, 0x2d, 41}, + /*(1452) CVTSD2SI*/ { 34, 60, 0x2d, 40}, + /*(1453) CVTSD2SI*/ { 29, 35, 0x2d, 126}, + /*(1454) CVTSD2SI*/ { 34, 60, 0x2d, 270}, + /*(1455) CMOVS*/ { 9, 18, 0x48, 0}, + /*(1456) CMOVS*/ { 8, 19, 0x48, 1}, + /*(1457) CMOVNS*/ { 9, 18, 0x49, 0}, + /*(1458) CMOVNS*/ { 8, 19, 0x49, 1}, + /*(1459) CMOVP*/ { 9, 18, 0x4a, 0}, + /*(1460) CMOVP*/ { 8, 19, 0x4a, 1}, + /*(1461) CMOVNP*/ { 9, 18, 0x4b, 0}, + /*(1462) CMOVNP*/ { 8, 19, 0x4b, 1}, + /*(1463) CMOVL*/ { 9, 18, 0x4c, 0}, + /*(1464) CMOVL*/ { 8, 19, 0x4c, 1}, + /*(1465) CMOVNL*/ { 9, 18, 0x4d, 0}, + /*(1466) CMOVNL*/ { 8, 19, 0x4d, 1}, + /*(1467) CMOVLE*/ { 9, 18, 0x4e, 0}, + /*(1468) CMOVLE*/ { 8, 19, 0x4e, 1}, + /*(1469) CMOVNLE*/ { 9, 18, 0x4f, 0}, + /*(1470) CMOVNLE*/ { 8, 19, 0x4f, 1}, + /*(1471) ADDPS*/ { 14, 18, 0x58, 26}, + /*(1472) ADDPS*/ { 15, 19, 0x58, 152}, + /*(1473) MULPS*/ { 14, 18, 0x59, 26}, + /*(1474) MULPS*/ { 15, 19, 0x59, 152}, + /*(1475) CVTPS2PD*/ { 14, 18, 0x5a, 26}, + /*(1476) CVTPS2PD*/ { 15, 19, 0x5a, 152}, + /*(1477) CVTDQ2PS*/ { 14, 18, 0x5b, 26}, + /*(1478) CVTDQ2PS*/ { 15, 19, 0x5b, 152}, + /*(1479) SUBPS*/ { 14, 18, 0x5c, 26}, + /*(1480) SUBPS*/ { 15, 19, 0x5c, 152}, + /*(1481) MINPS*/ { 14, 18, 0x5d, 26}, + /*(1482) MINPS*/ { 15, 19, 0x5d, 152}, + /*(1483) DIVPS*/ { 14, 18, 0x5e, 26}, + /*(1484) DIVPS*/ { 15, 19, 0x5e, 152}, + /*(1485) MAXPS*/ { 14, 18, 0x5f, 26}, + /*(1486) MAXPS*/ { 15, 19, 0x5f, 152}, + /*(1487) ADDSS*/ { 27, 35, 0x58, 1}, + /*(1488) ADDSS*/ { 19, 60, 0x58, 6}, + /*(1489) MULSS*/ { 27, 35, 0x59, 1}, + /*(1490) MULSS*/ { 19, 60, 0x59, 6}, + /*(1491) CVTSS2SD*/ { 27, 35, 0x5a, 1}, + /*(1492) CVTSS2SD*/ { 19, 60, 0x5a, 6}, + /*(1493) CVTTPS2DQ*/ { 27, 35, 0x5b, 1}, + /*(1494) CVTTPS2DQ*/ { 19, 60, 0x5b, 6}, + /*(1495) SUBSS*/ { 27, 35, 0x5c, 1}, + /*(1496) SUBSS*/ { 19, 60, 0x5c, 6}, + /*(1497) MINSS*/ { 27, 35, 0x5d, 1}, + /*(1498) MINSS*/ { 19, 60, 0x5d, 6}, + /*(1499) DIVSS*/ { 27, 35, 0x5e, 1}, + /*(1500) DIVSS*/ { 19, 60, 0x5e, 6}, + /*(1501) MAXSS*/ { 27, 35, 0x5f, 1}, + /*(1502) MAXSS*/ { 19, 60, 0x5f, 6}, + /*(1503) ADDPD*/ { 14, 34, 0x58, 121}, + /*(1504) ADDPD*/ { 15, 41, 0x58, 155}, + /*(1505) MULPD*/ { 14, 34, 0x59, 121}, + /*(1506) MULPD*/ { 15, 41, 0x59, 155}, + /*(1507) CVTPD2PS*/ { 14, 34, 0x5a, 121}, + /*(1508) CVTPD2PS*/ { 15, 41, 0x5a, 155}, + /*(1509) CVTPS2DQ*/ { 14, 34, 0x5b, 121}, + /*(1510) CVTPS2DQ*/ { 15, 41, 0x5b, 155}, + /*(1511) SUBPD*/ { 14, 34, 0x5c, 121}, + /*(1512) SUBPD*/ { 15, 41, 0x5c, 155}, + /*(1513) MINPD*/ { 14, 34, 0x5d, 121}, + /*(1514) MINPD*/ { 15, 41, 0x5d, 155}, + /*(1515) DIVPD*/ { 14, 34, 0x5e, 121}, + /*(1516) DIVPD*/ { 15, 41, 0x5e, 155}, + /*(1517) MAXPD*/ { 14, 34, 0x5f, 121}, + /*(1518) MAXPD*/ { 15, 41, 0x5f, 155}, + /*(1519) ADDSD*/ { 27, 35, 0x58, 9}, + /*(1520) ADDSD*/ { 19, 60, 0x58, 8}, + /*(1521) MULSD*/ { 27, 35, 0x59, 9}, + /*(1522) MULSD*/ { 19, 60, 0x59, 8}, + /*(1523) CVTSD2SS*/ { 27, 35, 0x5a, 9}, + /*(1524) CVTSD2SS*/ { 19, 60, 0x5a, 8}, + /*(1525) SUBSD*/ { 27, 35, 0x5c, 9}, + /*(1526) SUBSD*/ { 19, 60, 0x5c, 8}, + /*(1527) MINSD*/ { 27, 35, 0x5d, 9}, + /*(1528) MINSD*/ { 19, 60, 0x5d, 8}, + /*(1529) DIVSD*/ { 27, 35, 0x5e, 9}, + /*(1530) DIVSD*/ { 19, 60, 0x5e, 8}, + /*(1531) MAXSD*/ { 27, 35, 0x5f, 9}, + /*(1532) MAXSD*/ { 19, 60, 0x5f, 8}, + /*(1533) PUNPCKHBW*/ { 14, 18, 0x68, 26}, + /*(1534) PUNPCKHBW*/ { 15, 19, 0x68, 152}, + /*(1535) PUNPCKHBW*/ { 14, 34, 0x68, 121}, + /*(1536) PUNPCKHBW*/ { 15, 41, 0x68, 155}, + /*(1537) PUNPCKHWD*/ { 14, 18, 0x69, 26}, + /*(1538) PUNPCKHWD*/ { 15, 19, 0x69, 152}, + /*(1539) PUNPCKHWD*/ { 14, 34, 0x69, 121}, + /*(1540) PUNPCKHWD*/ { 15, 41, 0x69, 155}, + /*(1541) PUNPCKHDQ*/ { 14, 18, 0x6a, 26}, + /*(1542) PUNPCKHDQ*/ { 15, 19, 0x6a, 152}, + /*(1543) PUNPCKHDQ*/ { 14, 34, 0x6a, 121}, + /*(1544) PUNPCKHDQ*/ { 15, 41, 0x6a, 155}, + /*(1545) PACKSSDW*/ { 14, 18, 0x6b, 26}, + /*(1546) PACKSSDW*/ { 15, 19, 0x6b, 152}, + /*(1547) PACKSSDW*/ { 14, 34, 0x6b, 121}, + /*(1548) PACKSSDW*/ { 15, 41, 0x6b, 155}, + /*(1549) MOVD*/ { 28, 34, 0x6e, 187}, + /*(1550) MOVD*/ { 35, 41, 0x6e, 273}, + /*(1551) MOVD*/ { 14, 34, 0x6e, 121}, + /*(1552) MOVD*/ { 15, 41, 0x6e, 155}, + /*(1553) MOVD*/ { 28, 34, 0x7e, 187}, + /*(1554) MOVD*/ { 35, 41, 0x7e, 273}, + /*(1555) MOVD*/ { 14, 34, 0x7e, 121}, + /*(1556) MOVD*/ { 15, 41, 0x7e, 155}, + /*(1557) MOVD*/ { 28, 18, 0x6e, 181}, + /*(1558) MOVD*/ { 35, 19, 0x6e, 232}, + /*(1559) MOVD*/ { 14, 18, 0x6e, 26}, + /*(1560) MOVD*/ { 15, 19, 0x6e, 152}, + /*(1561) MOVD*/ { 28, 18, 0x7e, 181}, + /*(1562) MOVD*/ { 35, 19, 0x7e, 232}, + /*(1563) MOVD*/ { 14, 18, 0x7e, 26}, + /*(1564) MOVD*/ { 15, 19, 0x7e, 152}, + /*(1565) MOVQ*/ { 28, 34, 0x6e, 121}, + /*(1566) MOVQ*/ { 35, 41, 0x6e, 277}, + /*(1567) MOVQ*/ { 28, 34, 0x7e, 121}, + /*(1568) MOVQ*/ { 35, 41, 0x7e, 277}, + /*(1569) MOVQ*/ { 14, 34, 0xd6, 121}, + /*(1570) MOVQ*/ { 15, 41, 0xd6, 155}, + /*(1571) MOVQ*/ { 27, 35, 0x7e, 1}, + /*(1572) MOVQ*/ { 19, 60, 0x7e, 6}, + /*(1573) MOVQ*/ { 28, 18, 0x6e, 137}, + /*(1574) MOVQ*/ { 35, 19, 0x6e, 281}, + /*(1575) MOVQ*/ { 28, 18, 0x7e, 137}, + /*(1576) MOVQ*/ { 35, 19, 0x7e, 281}, + /*(1577) MOVQ*/ { 14, 18, 0x6f, 26}, + /*(1578) MOVQ*/ { 15, 19, 0x6f, 152}, + /*(1579) MOVQ*/ { 14, 18, 0x7f, 26}, + /*(1580) MOVQ*/ { 15, 19, 0x7f, 152}, + /*(1581) PUNPCKLQDQ*/ { 14, 34, 0x6c, 121}, + /*(1582) PUNPCKLQDQ*/ { 15, 41, 0x6c, 155}, + /*(1583) PUNPCKHQDQ*/ { 14, 34, 0x6d, 121}, + /*(1584) PUNPCKHQDQ*/ { 15, 41, 0x6d, 155}, + /*(1585) MOVDQU*/ { 27, 35, 0x6f, 1}, + /*(1586) MOVDQU*/ { 19, 60, 0x6f, 6}, + /*(1587) MOVDQU*/ { 27, 35, 0x7f, 1}, + /*(1588) MOVDQU*/ { 19, 60, 0x7f, 6}, + /*(1589) VMREAD*/ { 14, 68, 0x78, 26}, + /*(1590) VMREAD*/ { 15, 61, 0x78, 152}, + /*(1591) VMREAD*/ { 14, 68, 0x78, 26}, + /*(1592) VMREAD*/ { 15, 61, 0x78, 152}, + /*(1593) VMWRITE*/ { 14, 68, 0x79, 26}, + /*(1594) VMWRITE*/ { 15, 61, 0x79, 152}, + /*(1595) VMWRITE*/ { 14, 68, 0x79, 26}, + /*(1596) VMWRITE*/ { 15, 61, 0x79, 152}, + /*(1597) HADDPD*/ { 14, 34, 0x7c, 121}, + /*(1598) HADDPD*/ { 15, 41, 0x7c, 155}, + /*(1599) HSUBPD*/ { 14, 34, 0x7d, 121}, + /*(1600) HSUBPD*/ { 15, 41, 0x7d, 155}, + /*(1601) MOVDQA*/ { 14, 34, 0x7f, 121}, + /*(1602) MOVDQA*/ { 15, 41, 0x7f, 155}, + /*(1603) MOVDQA*/ { 14, 34, 0x6f, 121}, + /*(1604) MOVDQA*/ { 15, 41, 0x6f, 155}, + /*(1605) HADDPS*/ { 27, 35, 0x7c, 9}, + /*(1606) HADDPS*/ { 19, 60, 0x7c, 8}, + /*(1607) HSUBPS*/ { 27, 35, 0x7d, 9}, + /*(1608) HSUBPS*/ { 19, 60, 0x7d, 8}, + /*(1609) SETS*/ { 9, 18, 0x98, 0}, + /*(1610) SETS*/ { 8, 19, 0x98, 1}, + /*(1611) SETNS*/ { 9, 18, 0x99, 0}, + /*(1612) SETNS*/ { 8, 19, 0x99, 1}, + /*(1613) SETP*/ { 9, 18, 0x9a, 0}, + /*(1614) SETP*/ { 8, 19, 0x9a, 1}, + /*(1615) SETNP*/ { 9, 18, 0x9b, 0}, + /*(1616) SETNP*/ { 8, 19, 0x9b, 1}, + /*(1617) SETL*/ { 9, 18, 0x9c, 0}, + /*(1618) SETL*/ { 8, 19, 0x9c, 1}, + /*(1619) SETNL*/ { 9, 18, 0x9d, 0}, + /*(1620) SETNL*/ { 8, 19, 0x9d, 1}, + /*(1621) SETLE*/ { 9, 18, 0x9e, 0}, + /*(1622) SETLE*/ { 8, 19, 0x9e, 1}, + /*(1623) SETNLE*/ { 9, 18, 0x9f, 0}, + /*(1624) SETNLE*/ { 8, 19, 0x9f, 1}, + /*(1625) RSM*/ { 9, 59, 0xaa, 0}, + /*(1626) SHRD*/ { 9, 32, 0xac, 0}, + /*(1627) SHRD*/ { 8, 33, 0xac, 1}, + /*(1628) SHRD*/ { 9, 18, 0xad, 0}, + /*(1629) SHRD*/ { 8, 19, 0xad, 1}, + /*(1630) SHLD*/ { 9, 32, 0xa4, 0}, + /*(1631) SHLD*/ { 8, 33, 0xa4, 1}, + /*(1632) SHLD*/ { 9, 18, 0xa5, 0}, + /*(1633) SHLD*/ { 8, 19, 0xa5, 1}, + /*(1634) BSF*/ { 9, 18, 0xbc, 0}, + /*(1635) BSF*/ { 8, 19, 0xbc, 1}, + /*(1636) BSF*/ { 9, 18, 0xbc, 0}, + /*(1637) BSF*/ { 8, 19, 0xbc, 1}, + /*(1638) BSF*/ { 36, 18, 0xbc, 1}, + /*(1639) BSF*/ { 37, 19, 0xbc, 225}, + /*(1640) BSR*/ { 9, 18, 0xbd, 0}, + /*(1641) BSR*/ { 8, 19, 0xbd, 1}, + /*(1642) BSR*/ { 9, 18, 0xbd, 0}, + /*(1643) BSR*/ { 8, 19, 0xbd, 1}, + /*(1644) BSR*/ { 9, 18, 0xbd, 0}, + /*(1645) BSR*/ { 8, 19, 0xbd, 1}, + /*(1646) BSR*/ { 38, 18, 0xbd, 0}, + /*(1647) BSR*/ { 39, 19, 0xbd, 245}, + /*(1648) MOVSX*/ { 9, 18, 0xbe, 0}, + /*(1649) MOVSX*/ { 8, 19, 0xbe, 1}, + /*(1650) MOVSX*/ { 9, 18, 0xbf, 0}, + /*(1651) MOVSX*/ { 8, 19, 0xbf, 1}, + /*(1652) BSWAP*/ { 9, 69, 0x19, 0}, + /*(1653) PSUBUSB*/ { 14, 18, 0xd8, 26}, + /*(1654) PSUBUSB*/ { 15, 19, 0xd8, 152}, + /*(1655) PSUBUSB*/ { 14, 34, 0xd8, 121}, + /*(1656) PSUBUSB*/ { 15, 41, 0xd8, 155}, + /*(1657) PSUBUSW*/ { 14, 18, 0xd9, 26}, + /*(1658) PSUBUSW*/ { 15, 19, 0xd9, 152}, + /*(1659) PSUBUSW*/ { 14, 34, 0xd9, 121}, + /*(1660) PSUBUSW*/ { 15, 41, 0xd9, 155}, + /*(1661) PMINUB*/ { 14, 18, 0xda, 26}, + /*(1662) PMINUB*/ { 15, 19, 0xda, 152}, + /*(1663) PMINUB*/ { 14, 34, 0xda, 121}, + /*(1664) PMINUB*/ { 15, 41, 0xda, 155}, + /*(1665) PAND*/ { 14, 18, 0xdb, 26}, + /*(1666) PAND*/ { 15, 19, 0xdb, 152}, + /*(1667) PAND*/ { 14, 34, 0xdb, 121}, + /*(1668) PAND*/ { 15, 41, 0xdb, 155}, + /*(1669) PADDUSB*/ { 14, 18, 0xdc, 26}, + /*(1670) PADDUSB*/ { 15, 19, 0xdc, 152}, + /*(1671) PADDUSB*/ { 14, 34, 0xdc, 121}, + /*(1672) PADDUSB*/ { 15, 41, 0xdc, 155}, + /*(1673) PADDUSW*/ { 14, 18, 0xdd, 26}, + /*(1674) PADDUSW*/ { 15, 19, 0xdd, 152}, + /*(1675) PADDUSW*/ { 14, 34, 0xdd, 121}, + /*(1676) PADDUSW*/ { 15, 41, 0xdd, 155}, + /*(1677) PMAXUB*/ { 14, 18, 0xde, 26}, + /*(1678) PMAXUB*/ { 15, 19, 0xde, 152}, + /*(1679) PMAXUB*/ { 14, 34, 0xde, 121}, + /*(1680) PMAXUB*/ { 15, 41, 0xde, 155}, + /*(1681) PANDN*/ { 14, 18, 0xdf, 26}, + /*(1682) PANDN*/ { 15, 19, 0xdf, 152}, + /*(1683) PANDN*/ { 14, 34, 0xdf, 121}, + /*(1684) PANDN*/ { 15, 41, 0xdf, 155}, + /*(1685) PSUBSB*/ { 14, 18, 0xe8, 26}, + /*(1686) PSUBSB*/ { 15, 19, 0xe8, 152}, + /*(1687) PSUBSB*/ { 14, 34, 0xe8, 121}, + /*(1688) PSUBSB*/ { 15, 41, 0xe8, 155}, + /*(1689) PSUBSW*/ { 14, 18, 0xe9, 26}, + /*(1690) PSUBSW*/ { 15, 19, 0xe9, 152}, + /*(1691) PSUBSW*/ { 14, 34, 0xe9, 121}, + /*(1692) PSUBSW*/ { 15, 41, 0xe9, 155}, + /*(1693) PMINSW*/ { 14, 18, 0xea, 26}, + /*(1694) PMINSW*/ { 15, 19, 0xea, 152}, + /*(1695) PMINSW*/ { 14, 34, 0xea, 121}, + /*(1696) PMINSW*/ { 15, 41, 0xea, 155}, + /*(1697) POR*/ { 14, 18, 0xeb, 26}, + /*(1698) POR*/ { 15, 19, 0xeb, 152}, + /*(1699) POR*/ { 14, 34, 0xeb, 121}, + /*(1700) POR*/ { 15, 41, 0xeb, 155}, + /*(1701) PADDSB*/ { 14, 18, 0xec, 26}, + /*(1702) PADDSB*/ { 15, 19, 0xec, 152}, + /*(1703) PADDSB*/ { 14, 34, 0xec, 121}, + /*(1704) PADDSB*/ { 15, 41, 0xec, 155}, + /*(1705) PADDSW*/ { 14, 18, 0xed, 26}, + /*(1706) PADDSW*/ { 15, 19, 0xed, 152}, + /*(1707) PADDSW*/ { 14, 34, 0xed, 121}, + /*(1708) PADDSW*/ { 15, 41, 0xed, 155}, + /*(1709) PMAXSW*/ { 14, 18, 0xee, 26}, + /*(1710) PMAXSW*/ { 15, 19, 0xee, 152}, + /*(1711) PMAXSW*/ { 14, 34, 0xee, 121}, + /*(1712) PMAXSW*/ { 15, 41, 0xee, 155}, + /*(1713) PXOR*/ { 14, 18, 0xef, 26}, + /*(1714) PXOR*/ { 15, 19, 0xef, 152}, + /*(1715) PXOR*/ { 14, 34, 0xef, 121}, + /*(1716) PXOR*/ { 15, 41, 0xef, 155}, + /*(1717) PSUBB*/ { 14, 18, 0xf8, 26}, + /*(1718) PSUBB*/ { 15, 19, 0xf8, 152}, + /*(1719) PSUBB*/ { 14, 34, 0xf8, 121}, + /*(1720) PSUBB*/ { 15, 41, 0xf8, 155}, + /*(1721) PSUBW*/ { 14, 18, 0xf9, 26}, + /*(1722) PSUBW*/ { 15, 19, 0xf9, 152}, + /*(1723) PSUBW*/ { 14, 34, 0xf9, 121}, + /*(1724) PSUBW*/ { 15, 41, 0xf9, 155}, + /*(1725) PSUBD*/ { 14, 18, 0xfa, 26}, + /*(1726) PSUBD*/ { 15, 19, 0xfa, 152}, + /*(1727) PSUBD*/ { 14, 34, 0xfa, 121}, + /*(1728) PSUBD*/ { 15, 41, 0xfa, 155}, + /*(1729) PSUBQ*/ { 14, 18, 0xfb, 26}, + /*(1730) PSUBQ*/ { 15, 19, 0xfb, 152}, + /*(1731) PSUBQ*/ { 14, 34, 0xfb, 121}, + /*(1732) PSUBQ*/ { 15, 41, 0xfb, 155}, + /*(1733) PADDB*/ { 14, 18, 0xfc, 26}, + /*(1734) PADDB*/ { 15, 19, 0xfc, 152}, + /*(1735) PADDB*/ { 14, 34, 0xfc, 121}, + /*(1736) PADDB*/ { 15, 41, 0xfc, 155}, + /*(1737) PADDW*/ { 14, 18, 0xfd, 26}, + /*(1738) PADDW*/ { 15, 19, 0xfd, 152}, + /*(1739) PADDW*/ { 14, 34, 0xfd, 121}, + /*(1740) PADDW*/ { 15, 41, 0xfd, 155}, + /*(1741) PADDD*/ { 14, 18, 0xfe, 26}, + /*(1742) PADDD*/ { 15, 19, 0xfe, 152}, + /*(1743) PADDD*/ { 14, 34, 0xfe, 121}, + /*(1744) PADDD*/ { 15, 41, 0xfe, 155}, + /*(1745) PHADDW*/ { 14, 70, 0x1, 26}, + /*(1746) PHADDW*/ { 15, 71, 0x1, 152}, + /*(1747) PHADDW*/ { 14, 72, 0x1, 121}, + /*(1748) PHADDW*/ { 15, 73, 0x1, 155}, + /*(1749) PHADDD*/ { 14, 70, 0x2, 26}, + /*(1750) PHADDD*/ { 15, 71, 0x2, 152}, + /*(1751) PHADDD*/ { 14, 72, 0x2, 121}, + /*(1752) PHADDD*/ { 15, 73, 0x2, 155}, + /*(1753) PHADDSW*/ { 14, 70, 0x3, 26}, + /*(1754) PHADDSW*/ { 15, 71, 0x3, 152}, + /*(1755) PHADDSW*/ { 14, 72, 0x3, 121}, + /*(1756) PHADDSW*/ { 15, 73, 0x3, 155}, + /*(1757) PHSUBW*/ { 14, 70, 0x5, 26}, + /*(1758) PHSUBW*/ { 15, 71, 0x5, 152}, + /*(1759) PHSUBW*/ { 14, 72, 0x5, 121}, + /*(1760) PHSUBW*/ { 15, 73, 0x5, 155}, + /*(1761) PHSUBD*/ { 14, 70, 0x6, 26}, + /*(1762) PHSUBD*/ { 15, 71, 0x6, 152}, + /*(1763) PHSUBD*/ { 14, 72, 0x6, 121}, + /*(1764) PHSUBD*/ { 15, 73, 0x6, 155}, + /*(1765) PHSUBSW*/ { 14, 70, 0x7, 26}, + /*(1766) PHSUBSW*/ { 15, 71, 0x7, 152}, + /*(1767) PHSUBSW*/ { 14, 72, 0x7, 121}, + /*(1768) PHSUBSW*/ { 15, 73, 0x7, 155}, + /*(1769) PMADDUBSW*/ { 14, 70, 0x4, 26}, + /*(1770) PMADDUBSW*/ { 15, 71, 0x4, 152}, + /*(1771) PMADDUBSW*/ { 14, 72, 0x4, 121}, + /*(1772) PMADDUBSW*/ { 15, 73, 0x4, 155}, + /*(1773) PMULHRSW*/ { 14, 70, 0xb, 26}, + /*(1774) PMULHRSW*/ { 15, 71, 0xb, 152}, + /*(1775) PMULHRSW*/ { 14, 72, 0xb, 121}, + /*(1776) PMULHRSW*/ { 15, 73, 0xb, 155}, + /*(1777) PSHUFB*/ { 14, 70, 0x0, 26}, + /*(1778) PSHUFB*/ { 15, 71, 0x0, 152}, + /*(1779) PSHUFB*/ { 14, 72, 0x0, 121}, + /*(1780) PSHUFB*/ { 15, 73, 0x0, 155}, + /*(1781) PSIGNB*/ { 14, 70, 0x8, 26}, + /*(1782) PSIGNB*/ { 15, 71, 0x8, 152}, + /*(1783) PSIGNB*/ { 14, 72, 0x8, 121}, + /*(1784) PSIGNB*/ { 15, 73, 0x8, 155}, + /*(1785) PSIGNW*/ { 14, 70, 0x9, 26}, + /*(1786) PSIGNW*/ { 15, 71, 0x9, 152}, + /*(1787) PSIGNW*/ { 14, 72, 0x9, 121}, + /*(1788) PSIGNW*/ { 15, 73, 0x9, 155}, + /*(1789) PSIGND*/ { 14, 70, 0xa, 26}, + /*(1790) PSIGND*/ { 15, 71, 0xa, 152}, + /*(1791) PSIGND*/ { 14, 72, 0xa, 121}, + /*(1792) PSIGND*/ { 15, 73, 0xa, 155}, + /*(1793) PALIGNR*/ { 14, 74, 0xf, 26}, + /*(1794) PALIGNR*/ { 15, 75, 0xf, 152}, + /*(1795) PALIGNR*/ { 14, 76, 0xf, 121}, + /*(1796) PALIGNR*/ { 15, 77, 0xf, 155}, + /*(1797) PABSB*/ { 14, 70, 0x1c, 26}, + /*(1798) PABSB*/ { 15, 71, 0x1c, 152}, + /*(1799) PABSB*/ { 14, 72, 0x1c, 121}, + /*(1800) PABSB*/ { 15, 73, 0x1c, 155}, + /*(1801) PABSW*/ { 14, 70, 0x1d, 26}, + /*(1802) PABSW*/ { 15, 71, 0x1d, 152}, + /*(1803) PABSW*/ { 14, 72, 0x1d, 121}, + /*(1804) PABSW*/ { 15, 73, 0x1d, 155}, + /*(1805) PABSD*/ { 14, 70, 0x1e, 26}, + /*(1806) PABSD*/ { 15, 71, 0x1e, 152}, + /*(1807) PABSD*/ { 14, 72, 0x1e, 121}, + /*(1808) PABSD*/ { 15, 73, 0x1e, 155}, + /*(1809) POPCNT*/ { 27, 18, 0xb8, 1}, + /*(1810) POPCNT*/ { 19, 19, 0xb8, 6}, + /*(1811) PCMPGTQ*/ { 14, 72, 0x37, 121}, + /*(1812) PCMPGTQ*/ { 15, 73, 0x37, 155}, + /*(1813) CRC32*/ { 27, 70, 0xf0, 9}, + /*(1814) CRC32*/ { 19, 71, 0xf0, 8}, + /*(1815) CRC32*/ { 27, 70, 0xf1, 9}, + /*(1816) CRC32*/ { 19, 71, 0xf1, 8}, + /*(1817) BLENDPD*/ { 14, 78, 0xd, 121}, + /*(1818) BLENDPD*/ { 15, 79, 0xd, 155}, + /*(1819) BLENDPS*/ { 14, 78, 0xc, 121}, + /*(1820) BLENDPS*/ { 15, 79, 0xc, 155}, + /*(1821) BLENDVPD*/ { 14, 80, 0x15, 121}, + /*(1822) BLENDVPD*/ { 15, 81, 0x15, 155}, + /*(1823) BLENDVPS*/ { 14, 80, 0x14, 121}, + /*(1824) BLENDVPS*/ { 15, 81, 0x14, 155}, + /*(1825) PCMPEQQ*/ { 14, 80, 0x29, 121}, + /*(1826) PCMPEQQ*/ { 15, 81, 0x29, 155}, + /*(1827) DPPD*/ { 14, 78, 0x41, 121}, + /*(1828) DPPD*/ { 15, 79, 0x41, 155}, + /*(1829) DPPS*/ { 14, 78, 0x40, 121}, + /*(1830) DPPS*/ { 15, 79, 0x40, 155}, + /*(1831) MOVNTDQA*/ { 14, 80, 0x2a, 121}, + /*(1832) EXTRACTPS*/ { 14, 78, 0x17, 121}, + /*(1833) EXTRACTPS*/ { 15, 79, 0x17, 155}, + /*(1834) INSERTPS*/ { 14, 78, 0x21, 121}, + /*(1835) INSERTPS*/ { 15, 79, 0x21, 155}, + /*(1836) MPSADBW*/ { 14, 78, 0x42, 121}, + /*(1837) MPSADBW*/ { 15, 79, 0x42, 155}, + /*(1838) PACKUSDW*/ { 14, 80, 0x2b, 121}, + /*(1839) PACKUSDW*/ { 15, 81, 0x2b, 155}, + /*(1840) PBLENDW*/ { 14, 78, 0xe, 121}, + /*(1841) PBLENDW*/ { 15, 79, 0xe, 155}, + /*(1842) PBLENDVB*/ { 14, 80, 0x10, 121}, + /*(1843) PBLENDVB*/ { 15, 81, 0x10, 155}, + /*(1844) PEXTRB*/ { 14, 78, 0x14, 121}, + /*(1845) PEXTRB*/ { 15, 79, 0x14, 155}, + /*(1846) PEXTRW_SSE4*/ { 14, 78, 0x15, 121}, + /*(1847) PEXTRW_SSE4*/ { 15, 79, 0x15, 155}, + /*(1848) PEXTRQ*/ { 28, 78, 0x16, 121}, + /*(1849) PEXTRQ*/ { 35, 79, 0x16, 277}, + /*(1850) PEXTRD*/ { 28, 78, 0x16, 187}, + /*(1851) PEXTRD*/ { 35, 79, 0x16, 273}, + /*(1852) PINSRB*/ { 14, 78, 0x20, 121}, + /*(1853) PINSRB*/ { 15, 79, 0x20, 155}, + /*(1854) PINSRD*/ { 28, 78, 0x22, 187}, + /*(1855) PINSRD*/ { 35, 79, 0x22, 273}, + /*(1856) PINSRQ*/ { 28, 78, 0x22, 121}, + /*(1857) PINSRQ*/ { 35, 79, 0x22, 277}, + /*(1858) ROUNDPD*/ { 14, 78, 0x9, 121}, + /*(1859) ROUNDPD*/ { 15, 79, 0x9, 155}, + /*(1860) ROUNDPS*/ { 14, 78, 0x8, 121}, + /*(1861) ROUNDPS*/ { 15, 79, 0x8, 155}, + /*(1862) ROUNDSD*/ { 14, 78, 0xb, 121}, + /*(1863) ROUNDSD*/ { 15, 79, 0xb, 155}, + /*(1864) ROUNDSS*/ { 14, 78, 0xa, 121}, + /*(1865) ROUNDSS*/ { 15, 79, 0xa, 155}, + /*(1866) PTEST*/ { 14, 80, 0x17, 121}, + /*(1867) PTEST*/ { 15, 81, 0x17, 155}, + /*(1868) PHMINPOSUW*/ { 14, 80, 0x41, 121}, + /*(1869) PHMINPOSUW*/ { 15, 81, 0x41, 155}, + /*(1870) PMAXSB*/ { 14, 80, 0x3c, 121}, + /*(1871) PMAXSB*/ { 15, 81, 0x3c, 155}, + /*(1872) PMAXSD*/ { 14, 80, 0x3d, 121}, + /*(1873) PMAXSD*/ { 15, 81, 0x3d, 155}, + /*(1874) PMAXUD*/ { 14, 80, 0x3f, 121}, + /*(1875) PMAXUD*/ { 15, 81, 0x3f, 155}, + /*(1876) PMAXUW*/ { 14, 80, 0x3e, 121}, + /*(1877) PMAXUW*/ { 15, 81, 0x3e, 155}, + /*(1878) PMINSB*/ { 14, 80, 0x38, 121}, + /*(1879) PMINSB*/ { 15, 81, 0x38, 155}, + /*(1880) PMINSD*/ { 14, 80, 0x39, 121}, + /*(1881) PMINSD*/ { 15, 81, 0x39, 155}, + /*(1882) PMINUD*/ { 14, 80, 0x3b, 121}, + /*(1883) PMINUD*/ { 15, 81, 0x3b, 155}, + /*(1884) PMINUW*/ { 14, 80, 0x3a, 121}, + /*(1885) PMINUW*/ { 15, 81, 0x3a, 155}, + /*(1886) PMULLD*/ { 14, 80, 0x40, 121}, + /*(1887) PMULLD*/ { 15, 81, 0x40, 155}, + /*(1888) PMULDQ*/ { 14, 80, 0x28, 121}, + /*(1889) PMULDQ*/ { 15, 81, 0x28, 155}, + /*(1890) PMOVSXBW*/ { 14, 80, 0x20, 121}, + /*(1891) PMOVSXBW*/ { 15, 81, 0x20, 155}, + /*(1892) PMOVSXBD*/ { 14, 80, 0x21, 121}, + /*(1893) PMOVSXBD*/ { 15, 81, 0x21, 155}, + /*(1894) PMOVSXBQ*/ { 14, 80, 0x22, 121}, + /*(1895) PMOVSXBQ*/ { 15, 81, 0x22, 155}, + /*(1896) PMOVSXWD*/ { 14, 80, 0x23, 121}, + /*(1897) PMOVSXWD*/ { 15, 81, 0x23, 155}, + /*(1898) PMOVSXWQ*/ { 14, 80, 0x24, 121}, + /*(1899) PMOVSXWQ*/ { 15, 81, 0x24, 155}, + /*(1900) PMOVSXDQ*/ { 14, 80, 0x25, 121}, + /*(1901) PMOVSXDQ*/ { 15, 81, 0x25, 155}, + /*(1902) PMOVZXBW*/ { 14, 80, 0x30, 121}, + /*(1903) PMOVZXBW*/ { 15, 81, 0x30, 155}, + /*(1904) PMOVZXBD*/ { 14, 80, 0x31, 121}, + /*(1905) PMOVZXBD*/ { 15, 81, 0x31, 155}, + /*(1906) PMOVZXBQ*/ { 14, 80, 0x32, 121}, + /*(1907) PMOVZXBQ*/ { 15, 81, 0x32, 155}, + /*(1908) PMOVZXWD*/ { 14, 80, 0x33, 121}, + /*(1909) PMOVZXWD*/ { 15, 81, 0x33, 155}, + /*(1910) PMOVZXWQ*/ { 14, 80, 0x34, 121}, + /*(1911) PMOVZXWQ*/ { 15, 81, 0x34, 155}, + /*(1912) PMOVZXDQ*/ { 14, 80, 0x35, 121}, + /*(1913) PMOVZXDQ*/ { 15, 81, 0x35, 155}, + /*(1914) PCMPESTRI*/ { 14, 82, 0x61, 121}, + /*(1915) PCMPESTRI*/ { 15, 83, 0x61, 155}, + /*(1916) PCMPESTRI*/ { 28, 82, 0x61, 187}, + /*(1917) PCMPESTRI*/ { 35, 83, 0x61, 273}, + /*(1918) PCMPESTRI64*/ { 28, 82, 0x61, 121}, + /*(1919) PCMPESTRI64*/ { 35, 83, 0x61, 277}, + /*(1920) PCMPISTRI*/ { 14, 82, 0x63, 121}, + /*(1921) PCMPISTRI*/ { 15, 83, 0x63, 155}, + /*(1922) PCMPISTRI*/ { 28, 82, 0x63, 187}, + /*(1923) PCMPISTRI*/ { 35, 83, 0x63, 273}, + /*(1924) PCMPISTRI64*/ { 28, 82, 0x63, 121}, + /*(1925) PCMPISTRI64*/ { 35, 83, 0x63, 277}, + /*(1926) PCMPESTRM*/ { 14, 82, 0x60, 121}, + /*(1927) PCMPESTRM*/ { 15, 83, 0x60, 155}, + /*(1928) PCMPESTRM*/ { 28, 82, 0x60, 187}, + /*(1929) PCMPESTRM*/ { 35, 83, 0x60, 273}, + /*(1930) PCMPESTRM64*/ { 28, 82, 0x60, 121}, + /*(1931) PCMPESTRM64*/ { 35, 83, 0x60, 277}, + /*(1932) PCMPISTRM*/ { 14, 82, 0x62, 121}, + /*(1933) PCMPISTRM*/ { 15, 83, 0x62, 155}, + /*(1934) XGETBV*/ { 25, 19, 0x1, 285}, + /*(1935) XSETBV*/ { 25, 19, 0x1, 290}, + /*(1936) XSAVE*/ { 16, 18, 0xae, 27}, + /*(1937) XRSTOR*/ { 16, 18, 0xae, 295}, + /*(1938) XSAVE64*/ { 16, 18, 0xae, 299}, + /*(1939) XRSTOR64*/ { 16, 18, 0xae, 303}, + /*(1940) MOVBE*/ { 27, 70, 0xf0, 0}, + /*(1941) MOVBE*/ { 27, 70, 0xf1, 0}, + /*(1942) GETSEC*/ { 14, 59, 0x37, 26}, + /*(1943) AESKEYGENASSIST*/ { 15, 77, 0xdf, 155}, + /*(1944) AESKEYGENASSIST*/ { 14, 76, 0xdf, 121}, + /*(1945) AESENC*/ { 15, 73, 0xdc, 155}, + /*(1946) AESENC*/ { 14, 72, 0xdc, 121}, + /*(1947) AESENCLAST*/ { 15, 73, 0xdd, 155}, + /*(1948) AESENCLAST*/ { 14, 72, 0xdd, 121}, + /*(1949) AESDEC*/ { 15, 73, 0xde, 155}, + /*(1950) AESDEC*/ { 14, 72, 0xde, 121}, + /*(1951) AESDECLAST*/ { 15, 73, 0xdf, 155}, + /*(1952) AESDECLAST*/ { 14, 72, 0xdf, 121}, + /*(1953) AESIMC*/ { 15, 73, 0xdb, 155}, + /*(1954) AESIMC*/ { 14, 72, 0xdb, 121}, + /*(1955) PCLMULQDQ*/ { 15, 77, 0x44, 155}, + /*(1956) PCLMULQDQ*/ { 14, 76, 0x44, 121}, + /*(1957) INVEPT*/ { 14, 84, 0x80, 121}, + /*(1958) INVEPT*/ { 14, 84, 0x80, 121}, + /*(1959) INVVPID*/ { 14, 84, 0x81, 121}, + /*(1960) INVVPID*/ { 14, 84, 0x81, 121}, + /*(1961) PREFETCH_EXCLUSIVE*/ { 0, 18, 0xd, 0}, + /*(1962) PREFETCHW*/ { 0, 18, 0xd, 3}, + /*(1963) PREFETCHW*/ { 0, 18, 0xd, 1}, + /*(1964) PREFETCH_RESERVED*/ { 0, 18, 0xd, 9}, + /*(1965) PREFETCH_RESERVED*/ { 0, 18, 0xd, 10}, + /*(1966) PREFETCH_RESERVED*/ { 0, 18, 0xd, 14}, + /*(1967) PREFETCH_RESERVED*/ { 0, 18, 0xd, 15}, + /*(1968) PREFETCH_RESERVED*/ { 0, 18, 0xd, 19}, + /*(1969) NOP2*/ { 26, 13, 0x90, 3}, + /*(1970) NOP3*/ { 9, 85, 0x1f, 0}, + /*(1971) NOP4*/ { 9, 86, 0x1f, 0}, + /*(1972) NOP5*/ { 9, 87, 0x1f, 0}, + /*(1973) NOP6*/ { 26, 87, 0x1f, 3}, + /*(1974) NOP7*/ { 9, 88, 0x1f, 0}, + /*(1975) NOP8*/ { 9, 89, 0x1f, 0}, + /*(1976) NOP9*/ { 26, 89, 0x1f, 3}, + /*(1977) XSTORE*/ { 21, 19, 0xa7, 232}, + /*(1978) REP_XSTORE*/ { 21, 19, 0xa7, 307}, + /*(1979) REP_XCRYPTECB*/ { 21, 19, 0xa7, 174}, + /*(1980) REP_XCRYPTCBC*/ { 21, 19, 0xa7, 311}, + /*(1981) REP_XCRYPTCTR*/ { 21, 19, 0xa7, 315}, + /*(1982) REP_XCRYPTCFB*/ { 21, 19, 0xa7, 319}, + /*(1983) REP_XCRYPTOFB*/ { 21, 19, 0xa7, 323}, + /*(1984) REP_XSHA1*/ { 21, 19, 0xa6, 174}, + /*(1985) REP_XSHA256*/ { 21, 19, 0xa6, 311}, + /*(1986) REP_MONTMUL*/ { 21, 19, 0xa6, 307}, + /*(1987) REP_MONTMUL*/ { 21, 19, 0xa6, 307}, + /*(1988) FEMMS*/ { 9, 59, 0xe, 0}, + /*(1989) PI2FW*/ { 9, 90, 0xc, 0}, + /*(1990) PI2FW*/ { 8, 91, 0xc, 1}, + /*(1991) PI2FD*/ { 9, 90, 0xd, 0}, + /*(1992) PI2FD*/ { 8, 91, 0xd, 1}, + /*(1993) PF2IW*/ { 9, 90, 0x1c, 0}, + /*(1994) PF2IW*/ { 8, 91, 0x1c, 1}, + /*(1995) PF2ID*/ { 9, 90, 0x1d, 0}, + /*(1996) PF2ID*/ { 8, 91, 0x1d, 1}, + /*(1997) PFNACC*/ { 9, 90, 0x8a, 0}, + /*(1998) PFNACC*/ { 8, 91, 0x8a, 1}, + /*(1999) PFPNACC*/ { 9, 90, 0x8e, 0}, + /*(2000) PFPNACC*/ { 8, 91, 0x8e, 1}, + /*(2001) PFCMPGE*/ { 9, 90, 0x90, 0}, + /*(2002) PFCMPGE*/ { 8, 91, 0x90, 1}, + /*(2003) PFMIN*/ { 9, 90, 0x94, 0}, + /*(2004) PFMIN*/ { 8, 91, 0x94, 1}, + /*(2005) PFRCP*/ { 9, 90, 0x96, 0}, + /*(2006) PFRCP*/ { 8, 91, 0x96, 1}, + /*(2007) PFRSQRT*/ { 9, 90, 0x97, 0}, + /*(2008) PFRSQRT*/ { 8, 91, 0x97, 1}, + /*(2009) PFSUB*/ { 9, 90, 0x9a, 0}, + /*(2010) PFSUB*/ { 8, 91, 0x9a, 1}, + /*(2011) PFADD*/ { 9, 90, 0x9e, 0}, + /*(2012) PFADD*/ { 8, 91, 0x9e, 1}, + /*(2013) PFCMPGT*/ { 9, 90, 0xa0, 0}, + /*(2014) PFCMPGT*/ { 8, 91, 0xa0, 1}, + /*(2015) PFMAX*/ { 9, 90, 0xa4, 0}, + /*(2016) PFMAX*/ { 8, 91, 0xa4, 1}, + /*(2017) PFRCPIT1*/ { 9, 90, 0xa6, 0}, + /*(2018) PFRCPIT1*/ { 8, 91, 0xa6, 1}, + /*(2019) PFRSQIT1*/ { 9, 90, 0xa7, 0}, + /*(2020) PFRSQIT1*/ { 8, 91, 0xa7, 1}, + /*(2021) PFSUBR*/ { 9, 90, 0xaa, 0}, + /*(2022) PFSUBR*/ { 8, 91, 0xaa, 1}, + /*(2023) PFACC*/ { 9, 90, 0xae, 0}, + /*(2024) PFACC*/ { 8, 91, 0xae, 1}, + /*(2025) PFCMPEQ*/ { 9, 90, 0xb0, 0}, + /*(2026) PFCMPEQ*/ { 8, 91, 0xb0, 1}, + /*(2027) PFMUL*/ { 9, 90, 0xb4, 0}, + /*(2028) PFMUL*/ { 8, 91, 0xb4, 1}, + /*(2029) PFRCPIT2*/ { 9, 90, 0xb6, 0}, + /*(2030) PFRCPIT2*/ { 8, 91, 0xb6, 1}, + /*(2031) PMULHRW*/ { 9, 90, 0xb7, 0}, + /*(2032) PMULHRW*/ { 8, 91, 0xb7, 1}, + /*(2033) PSWAPD*/ { 9, 90, 0xbb, 0}, + /*(2034) PSWAPD*/ { 8, 91, 0xbb, 1}, + /*(2035) PAVGUSB*/ { 9, 90, 0xbf, 0}, + /*(2036) PAVGUSB*/ { 8, 91, 0xbf, 1}, + /*(2037) SYSCALL_AMD*/ { 9, 92, 0x5, 0}, + /*(2038) SYSRET_AMD*/ { 9, 59, 0x7, 0}, + /*(2039) VMRUN*/ { 5, 19, 0x1, 225}, + /*(2040) VMMCALL*/ { 5, 19, 0x1, 118}, + /*(2041) VMLOAD*/ { 5, 19, 0x1, 7}, + /*(2042) VMSAVE*/ { 5, 19, 0x1, 6}, + /*(2043) STGI*/ { 5, 19, 0x1, 327}, + /*(2044) CLGI*/ { 5, 19, 0x1, 66}, + /*(2045) SKINIT*/ { 5, 19, 0x1, 330}, + /*(2046) INVLPGA*/ { 5, 19, 0x1, 102}, + /*(2047) EXTRQ*/ { 13, 93, 0x78, 273}, + /*(2048) EXTRQ*/ { 15, 94, 0x79, 155}, + /*(2049) INSERTQ*/ { 19, 95, 0x78, 8}, + /*(2050) INSERTQ*/ { 19, 19, 0x79, 8}, + /*(2051) MOVNTSD*/ { 27, 18, 0x2b, 9}, + /*(2052) MOVNTSS*/ { 27, 18, 0x2b, 1}, + /*(2053) LZCNT*/ { 27, 18, 0xbd, 1}, + /*(2054) LZCNT*/ { 19, 19, 0xbd, 6}, + /*(2055) LZCNT*/ { 38, 18, 0xbd, 3}, + /*(2056) LZCNT*/ { 39, 19, 0xbd, 5}, + /*(2057) CLZERO*/ { 5, 19, 0x1, 103}, + /*(2058) MONITORX*/ { 25, 19, 0x1, 333}, + /*(2059) MONITORX*/ { 25, 19, 0x1, 333}, + /*(2060) MONITORX*/ { 25, 19, 0x1, 333}, + /*(2061) MONITORX*/ { 25, 19, 0x1, 333}, + /*(2062) MWAITX*/ { 25, 19, 0x1, 262}, + /*(2063) MCOMMIT*/ { 21, 19, 0x1, 218}, + /*(2064) RDPRU*/ { 5, 19, 0x1, 106}, + /*(2065) PSMASH*/ { 21, 19, 0x1, 213}, + /*(2066) PVALIDATE*/ { 21, 19, 0x1, 338}, + /*(2067) RMPADJUST*/ { 21, 19, 0x1, 209}, + /*(2068) RMPUPDATE*/ { 21, 19, 0x1, 342}, + /*(2069) INVLPGB*/ { 25, 19, 0x1, 346}, + /*(2070) INVLPGB*/ { 25, 19, 0x1, 346}, + /*(2071) TLBSYNC*/ { 25, 19, 0x1, 351}, + /*(2072) VPMACSSWW*/ { 40, 96, 0x85, 356}, + /*(2073) VPMACSSWW*/ { 41, 97, 0x85, 360}, + /*(2074) VPMACSSWD*/ { 40, 96, 0x86, 356}, + /*(2075) VPMACSSWD*/ { 41, 97, 0x86, 360}, + /*(2076) VPMACSSDQL*/ { 40, 96, 0x87, 356}, + /*(2077) VPMACSSDQL*/ { 41, 97, 0x87, 360}, + /*(2078) VPMACSWW*/ { 40, 96, 0x95, 356}, + /*(2079) VPMACSWW*/ { 41, 97, 0x95, 360}, + /*(2080) VPMACSWD*/ { 40, 96, 0x96, 356}, + /*(2081) VPMACSWD*/ { 41, 97, 0x96, 360}, + /*(2082) VPMACSDQL*/ { 40, 96, 0x97, 356}, + /*(2083) VPMACSDQL*/ { 41, 97, 0x97, 360}, + /*(2084) VPCMOV*/ { 40, 96, 0xa2, 356}, + /*(2085) VPCMOV*/ { 41, 97, 0xa2, 360}, + /*(2086) VPCMOV*/ { 40, 96, 0xa2, 365}, + /*(2087) VPCMOV*/ { 41, 97, 0xa2, 369}, + /*(2088) VPCMOV*/ { 40, 96, 0xa2, 356}, + /*(2089) VPCMOV*/ { 41, 97, 0xa2, 360}, + /*(2090) VPCMOV*/ { 40, 96, 0xa2, 365}, + /*(2091) VPCMOV*/ { 41, 97, 0xa2, 369}, + /*(2092) VPPERM*/ { 40, 96, 0xa3, 356}, + /*(2093) VPPERM*/ { 41, 97, 0xa3, 360}, + /*(2094) VPPERM*/ { 40, 96, 0xa3, 365}, + /*(2095) VPPERM*/ { 41, 97, 0xa3, 369}, + /*(2096) VPMADCSSWD*/ { 40, 96, 0xa6, 356}, + /*(2097) VPMADCSSWD*/ { 41, 97, 0xa6, 360}, + /*(2098) VPMADCSWD*/ { 40, 96, 0xb6, 356}, + /*(2099) VPMADCSWD*/ { 41, 97, 0xb6, 360}, + /*(2100) VPROTB*/ { 42, 9, 0xc0, 374}, + /*(2101) VPROTB*/ { 43, 10, 0xc0, 380}, + /*(2102) VPROTB*/ { 40, 0, 0x90, 387}, + /*(2103) VPROTB*/ { 41, 1, 0x90, 391}, + /*(2104) VPROTB*/ { 40, 0, 0x90, 396}, + /*(2105) VPROTB*/ { 41, 1, 0x90, 400}, + /*(2106) VPROTW*/ { 42, 9, 0xc1, 374}, + /*(2107) VPROTW*/ { 43, 10, 0xc1, 380}, + /*(2108) VPROTW*/ { 40, 0, 0x91, 387}, + /*(2109) VPROTW*/ { 41, 1, 0x91, 391}, + /*(2110) VPROTW*/ { 40, 0, 0x91, 396}, + /*(2111) VPROTW*/ { 41, 1, 0x91, 400}, + /*(2112) VPROTD*/ { 42, 9, 0xc2, 374}, + /*(2113) VPROTD*/ { 43, 10, 0xc2, 380}, + /*(2114) VPROTD*/ { 40, 0, 0x92, 387}, + /*(2115) VPROTD*/ { 41, 1, 0x92, 391}, + /*(2116) VPROTD*/ { 40, 0, 0x92, 396}, + /*(2117) VPROTD*/ { 41, 1, 0x92, 400}, + /*(2118) VPROTQ*/ { 42, 9, 0xc3, 374}, + /*(2119) VPROTQ*/ { 43, 10, 0xc3, 380}, + /*(2120) VPROTQ*/ { 40, 0, 0x93, 387}, + /*(2121) VPROTQ*/ { 41, 1, 0x93, 391}, + /*(2122) VPROTQ*/ { 40, 0, 0x93, 396}, + /*(2123) VPROTQ*/ { 41, 1, 0x93, 400}, + /*(2124) VPMACSSDD*/ { 40, 96, 0x8e, 356}, + /*(2125) VPMACSSDD*/ { 41, 97, 0x8e, 360}, + /*(2126) VPMACSSDQH*/ { 40, 96, 0x8f, 356}, + /*(2127) VPMACSSDQH*/ { 41, 97, 0x8f, 360}, + /*(2128) VPMACSDD*/ { 40, 96, 0x9e, 356}, + /*(2129) VPMACSDD*/ { 41, 97, 0x9e, 360}, + /*(2130) VPMACSDQH*/ { 40, 96, 0x9f, 356}, + /*(2131) VPMACSDQH*/ { 41, 97, 0x9f, 360}, + /*(2132) VPCOMB*/ { 40, 9, 0xcc, 356}, + /*(2133) VPCOMB*/ { 41, 10, 0xcc, 360}, + /*(2134) VPCOMW*/ { 40, 9, 0xcd, 356}, + /*(2135) VPCOMW*/ { 41, 10, 0xcd, 360}, + /*(2136) VPCOMD*/ { 40, 9, 0xce, 356}, + /*(2137) VPCOMD*/ { 41, 10, 0xce, 360}, + /*(2138) VPCOMQ*/ { 40, 9, 0xcf, 356}, + /*(2139) VPCOMQ*/ { 41, 10, 0xcf, 360}, + /*(2140) VPCOMUB*/ { 40, 9, 0xec, 356}, + /*(2141) VPCOMUB*/ { 41, 10, 0xec, 360}, + /*(2142) VPCOMUW*/ { 40, 9, 0xed, 356}, + /*(2143) VPCOMUW*/ { 41, 10, 0xed, 360}, + /*(2144) VPCOMUD*/ { 40, 9, 0xee, 356}, + /*(2145) VPCOMUD*/ { 41, 10, 0xee, 360}, + /*(2146) VPCOMUQ*/ { 40, 9, 0xef, 356}, + /*(2147) VPCOMUQ*/ { 41, 10, 0xef, 360}, + /*(2148) VFRCZPS*/ { 42, 0, 0x80, 405}, + /*(2149) VFRCZPS*/ { 43, 1, 0x80, 411}, + /*(2150) VFRCZPS*/ { 42, 0, 0x80, 405}, + /*(2151) VFRCZPS*/ { 43, 1, 0x80, 411}, + /*(2152) VFRCZPD*/ { 42, 0, 0x81, 405}, + /*(2153) VFRCZPD*/ { 43, 1, 0x81, 411}, + /*(2154) VFRCZPD*/ { 42, 0, 0x81, 405}, + /*(2155) VFRCZPD*/ { 43, 1, 0x81, 411}, + /*(2156) VFRCZSS*/ { 42, 0, 0x82, 405}, + /*(2157) VFRCZSS*/ { 43, 1, 0x82, 411}, + /*(2158) VFRCZSD*/ { 42, 0, 0x83, 405}, + /*(2159) VFRCZSD*/ { 43, 1, 0x83, 411}, + /*(2160) VPSHLB*/ { 40, 0, 0x94, 387}, + /*(2161) VPSHLB*/ { 41, 1, 0x94, 391}, + /*(2162) VPSHLB*/ { 40, 0, 0x94, 396}, + /*(2163) VPSHLB*/ { 41, 1, 0x94, 400}, + /*(2164) VPSHLW*/ { 40, 0, 0x95, 387}, + /*(2165) VPSHLW*/ { 41, 1, 0x95, 391}, + /*(2166) VPSHLW*/ { 40, 0, 0x95, 396}, + /*(2167) VPSHLW*/ { 41, 1, 0x95, 400}, + /*(2168) VPSHLD*/ { 40, 0, 0x96, 387}, + /*(2169) VPSHLD*/ { 41, 1, 0x96, 391}, + /*(2170) VPSHLD*/ { 40, 0, 0x96, 396}, + /*(2171) VPSHLD*/ { 41, 1, 0x96, 400}, + /*(2172) VPSHLQ*/ { 40, 0, 0x97, 387}, + /*(2173) VPSHLQ*/ { 41, 1, 0x97, 391}, + /*(2174) VPSHLQ*/ { 40, 0, 0x97, 396}, + /*(2175) VPSHLQ*/ { 41, 1, 0x97, 400}, + /*(2176) VPHADDBW*/ { 42, 0, 0xc1, 405}, + /*(2177) VPHADDBW*/ { 43, 1, 0xc1, 411}, + /*(2178) VPHADDBD*/ { 42, 0, 0xc2, 405}, + /*(2179) VPHADDBD*/ { 43, 1, 0xc2, 411}, + /*(2180) VPHADDBQ*/ { 42, 0, 0xc3, 405}, + /*(2181) VPHADDBQ*/ { 43, 1, 0xc3, 411}, + /*(2182) VPHADDWD*/ { 42, 0, 0xc6, 405}, + /*(2183) VPHADDWD*/ { 43, 1, 0xc6, 411}, + /*(2184) VPHADDWQ*/ { 42, 0, 0xc7, 405}, + /*(2185) VPHADDWQ*/ { 43, 1, 0xc7, 411}, + /*(2186) VPHADDUBW*/ { 42, 0, 0xd1, 405}, + /*(2187) VPHADDUBW*/ { 43, 1, 0xd1, 411}, + /*(2188) VPHADDUBD*/ { 42, 0, 0xd2, 405}, + /*(2189) VPHADDUBD*/ { 43, 1, 0xd2, 411}, + /*(2190) VPHADDUBQ*/ { 42, 0, 0xd3, 405}, + /*(2191) VPHADDUBQ*/ { 43, 1, 0xd3, 411}, + /*(2192) VPHADDUWD*/ { 42, 0, 0xd6, 405}, + /*(2193) VPHADDUWD*/ { 43, 1, 0xd6, 411}, + /*(2194) VPHADDUWQ*/ { 42, 0, 0xd7, 405}, + /*(2195) VPHADDUWQ*/ { 43, 1, 0xd7, 411}, + /*(2196) VPHSUBBW*/ { 42, 0, 0xe1, 405}, + /*(2197) VPHSUBBW*/ { 43, 1, 0xe1, 411}, + /*(2198) VPHSUBWD*/ { 42, 0, 0xe2, 405}, + /*(2199) VPHSUBWD*/ { 43, 1, 0xe2, 411}, + /*(2200) VPHSUBDQ*/ { 42, 0, 0xe3, 405}, + /*(2201) VPHSUBDQ*/ { 43, 1, 0xe3, 411}, + /*(2202) VPSHAB*/ { 40, 0, 0x98, 387}, + /*(2203) VPSHAB*/ { 41, 1, 0x98, 391}, + /*(2204) VPSHAB*/ { 40, 0, 0x98, 396}, + /*(2205) VPSHAB*/ { 41, 1, 0x98, 400}, + /*(2206) VPSHAW*/ { 40, 0, 0x99, 387}, + /*(2207) VPSHAW*/ { 41, 1, 0x99, 391}, + /*(2208) VPSHAW*/ { 40, 0, 0x99, 396}, + /*(2209) VPSHAW*/ { 41, 1, 0x99, 400}, + /*(2210) VPSHAD*/ { 40, 0, 0x9a, 387}, + /*(2211) VPSHAD*/ { 41, 1, 0x9a, 391}, + /*(2212) VPSHAD*/ { 40, 0, 0x9a, 396}, + /*(2213) VPSHAD*/ { 41, 1, 0x9a, 400}, + /*(2214) VPSHAQ*/ { 40, 0, 0x9b, 387}, + /*(2215) VPSHAQ*/ { 41, 1, 0x9b, 391}, + /*(2216) VPSHAQ*/ { 40, 0, 0x9b, 396}, + /*(2217) VPSHAQ*/ { 41, 1, 0x9b, 400}, + /*(2218) VPHADDDQ*/ { 42, 0, 0xcb, 405}, + /*(2219) VPHADDDQ*/ { 43, 1, 0xcb, 411}, + /*(2220) VPHADDUDQ*/ { 42, 0, 0xdb, 405}, + /*(2221) VPHADDUDQ*/ { 43, 1, 0xdb, 411}, + /*(2222) BEXTR_XOP*/ { 44, 98, 0x10, 418}, + /*(2223) BEXTR_XOP*/ { 44, 98, 0x10, 418}, + /*(2224) BEXTR_XOP*/ { 45, 99, 0x10, 423}, + /*(2225) BEXTR_XOP*/ { 45, 99, 0x10, 423}, + /*(2226) BLCFILL*/ { 46, 0, 0x1, 396}, + /*(2227) BLCFILL*/ { 46, 0, 0x1, 396}, + /*(2228) BLCFILL*/ { 47, 1, 0x1, 400}, + /*(2229) BLCFILL*/ { 47, 1, 0x1, 400}, + /*(2230) BLSFILL*/ { 46, 0, 0x1, 429}, + /*(2231) BLSFILL*/ { 46, 0, 0x1, 429}, + /*(2232) BLSFILL*/ { 47, 1, 0x1, 433}, + /*(2233) BLSFILL*/ { 47, 1, 0x1, 433}, + /*(2234) BLCS*/ { 46, 0, 0x1, 438}, + /*(2235) BLCS*/ { 46, 0, 0x1, 438}, + /*(2236) BLCS*/ { 47, 1, 0x1, 442}, + /*(2237) BLCS*/ { 47, 1, 0x1, 442}, + /*(2238) TZMSK*/ { 46, 0, 0x1, 447}, + /*(2239) TZMSK*/ { 46, 0, 0x1, 447}, + /*(2240) TZMSK*/ { 47, 1, 0x1, 451}, + /*(2241) TZMSK*/ { 47, 1, 0x1, 451}, + /*(2242) BLCIC*/ { 46, 0, 0x1, 456}, + /*(2243) BLCIC*/ { 46, 0, 0x1, 456}, + /*(2244) BLCIC*/ { 47, 1, 0x1, 460}, + /*(2245) BLCIC*/ { 47, 1, 0x1, 460}, + /*(2246) BLSIC*/ { 46, 0, 0x1, 465}, + /*(2247) BLSIC*/ { 46, 0, 0x1, 465}, + /*(2248) BLSIC*/ { 47, 1, 0x1, 469}, + /*(2249) BLSIC*/ { 47, 1, 0x1, 469}, + /*(2250) T1MSKC*/ { 46, 0, 0x1, 474}, + /*(2251) T1MSKC*/ { 46, 0, 0x1, 474}, + /*(2252) T1MSKC*/ { 47, 1, 0x1, 478}, + /*(2253) T1MSKC*/ { 47, 1, 0x1, 478}, + /*(2254) BLCMSK*/ { 46, 0, 0x2, 396}, + /*(2255) BLCMSK*/ { 46, 0, 0x2, 396}, + /*(2256) BLCMSK*/ { 47, 1, 0x2, 400}, + /*(2257) BLCMSK*/ { 47, 1, 0x2, 400}, + /*(2258) BLCI*/ { 46, 0, 0x2, 465}, + /*(2259) BLCI*/ { 46, 0, 0x2, 465}, + /*(2260) BLCI*/ { 47, 1, 0x2, 469}, + /*(2261) BLCI*/ { 47, 1, 0x2, 469}, + /*(2262) LLWPCB*/ { 48, 1, 0x12, 411}, + /*(2263) SLWPCB*/ { 48, 1, 0x12, 483}, + /*(2264) LWPINS*/ { 46, 98, 0x12, 490}, + /*(2265) LWPINS*/ { 47, 99, 0x12, 494}, + /*(2266) LWPVAL*/ { 46, 98, 0x12, 499}, + /*(2267) LWPVAL*/ { 47, 99, 0x12, 503}, + /*(2268) VFMADDSUBPS*/ { 40, 96, 0x5c, 508}, + /*(2269) VFMADDSUBPS*/ { 41, 97, 0x5c, 507}, + /*(2270) VFMADDSUBPS*/ { 40, 96, 0x5c, 512}, + /*(2271) VFMADDSUBPS*/ { 41, 97, 0x5c, 516}, + /*(2272) VFMADDSUBPS*/ { 40, 96, 0x5c, 508}, + /*(2273) VFMADDSUBPS*/ { 41, 97, 0x5c, 507}, + /*(2274) VFMADDSUBPS*/ { 40, 96, 0x5c, 512}, + /*(2275) VFMADDSUBPS*/ { 41, 97, 0x5c, 516}, + /*(2276) VFMADDSUBPD*/ { 40, 96, 0x5d, 508}, + /*(2277) VFMADDSUBPD*/ { 41, 97, 0x5d, 507}, + /*(2278) VFMADDSUBPD*/ { 40, 96, 0x5d, 512}, + /*(2279) VFMADDSUBPD*/ { 41, 97, 0x5d, 516}, + /*(2280) VFMADDSUBPD*/ { 40, 96, 0x5d, 508}, + /*(2281) VFMADDSUBPD*/ { 41, 97, 0x5d, 507}, + /*(2282) VFMADDSUBPD*/ { 40, 96, 0x5d, 512}, + /*(2283) VFMADDSUBPD*/ { 41, 97, 0x5d, 516}, + /*(2284) VFMSUBADDPS*/ { 40, 96, 0x5e, 508}, + /*(2285) VFMSUBADDPS*/ { 41, 97, 0x5e, 507}, + /*(2286) VFMSUBADDPS*/ { 40, 96, 0x5e, 512}, + /*(2287) VFMSUBADDPS*/ { 41, 97, 0x5e, 516}, + /*(2288) VFMSUBADDPS*/ { 40, 96, 0x5e, 508}, + /*(2289) VFMSUBADDPS*/ { 41, 97, 0x5e, 507}, + /*(2290) VFMSUBADDPS*/ { 40, 96, 0x5e, 512}, + /*(2291) VFMSUBADDPS*/ { 41, 97, 0x5e, 516}, + /*(2292) VFMSUBADDPD*/ { 40, 96, 0x5f, 508}, + /*(2293) VFMSUBADDPD*/ { 41, 97, 0x5f, 507}, + /*(2294) VFMSUBADDPD*/ { 40, 96, 0x5f, 512}, + /*(2295) VFMSUBADDPD*/ { 41, 97, 0x5f, 516}, + /*(2296) VFMSUBADDPD*/ { 40, 96, 0x5f, 508}, + /*(2297) VFMSUBADDPD*/ { 41, 97, 0x5f, 507}, + /*(2298) VFMSUBADDPD*/ { 40, 96, 0x5f, 512}, + /*(2299) VFMSUBADDPD*/ { 41, 97, 0x5f, 516}, + /*(2300) VFMADDPS*/ { 40, 96, 0x68, 508}, + /*(2301) VFMADDPS*/ { 41, 97, 0x68, 507}, + /*(2302) VFMADDPS*/ { 40, 96, 0x68, 512}, + /*(2303) VFMADDPS*/ { 41, 97, 0x68, 516}, + /*(2304) VFMADDPS*/ { 40, 96, 0x68, 508}, + /*(2305) VFMADDPS*/ { 41, 97, 0x68, 507}, + /*(2306) VFMADDPS*/ { 40, 96, 0x68, 512}, + /*(2307) VFMADDPS*/ { 41, 97, 0x68, 516}, + /*(2308) VFMADDPD*/ { 40, 96, 0x69, 508}, + /*(2309) VFMADDPD*/ { 41, 97, 0x69, 507}, + /*(2310) VFMADDPD*/ { 40, 96, 0x69, 512}, + /*(2311) VFMADDPD*/ { 41, 97, 0x69, 516}, + /*(2312) VFMADDPD*/ { 40, 96, 0x69, 508}, + /*(2313) VFMADDPD*/ { 41, 97, 0x69, 507}, + /*(2314) VFMADDPD*/ { 40, 96, 0x69, 512}, + /*(2315) VFMADDPD*/ { 41, 97, 0x69, 516}, + /*(2316) VFMADDSS*/ { 40, 96, 0x6a, 508}, + /*(2317) VFMADDSS*/ { 41, 97, 0x6a, 507}, + /*(2318) VFMADDSS*/ { 40, 96, 0x6a, 512}, + /*(2319) VFMADDSS*/ { 41, 97, 0x6a, 516}, + /*(2320) VFMADDSD*/ { 40, 96, 0x6b, 508}, + /*(2321) VFMADDSD*/ { 41, 97, 0x6b, 507}, + /*(2322) VFMADDSD*/ { 40, 96, 0x6b, 512}, + /*(2323) VFMADDSD*/ { 41, 97, 0x6b, 516}, + /*(2324) VFMSUBPS*/ { 40, 96, 0x6c, 508}, + /*(2325) VFMSUBPS*/ { 41, 97, 0x6c, 507}, + /*(2326) VFMSUBPS*/ { 40, 96, 0x6c, 512}, + /*(2327) VFMSUBPS*/ { 41, 97, 0x6c, 516}, + /*(2328) VFMSUBPS*/ { 40, 96, 0x6c, 508}, + /*(2329) VFMSUBPS*/ { 41, 97, 0x6c, 507}, + /*(2330) VFMSUBPS*/ { 40, 96, 0x6c, 512}, + /*(2331) VFMSUBPS*/ { 41, 97, 0x6c, 516}, + /*(2332) VFMSUBPD*/ { 40, 96, 0x6d, 508}, + /*(2333) VFMSUBPD*/ { 41, 97, 0x6d, 507}, + /*(2334) VFMSUBPD*/ { 40, 96, 0x6d, 512}, + /*(2335) VFMSUBPD*/ { 41, 97, 0x6d, 516}, + /*(2336) VFMSUBPD*/ { 40, 96, 0x6d, 508}, + /*(2337) VFMSUBPD*/ { 41, 97, 0x6d, 507}, + /*(2338) VFMSUBPD*/ { 40, 96, 0x6d, 512}, + /*(2339) VFMSUBPD*/ { 41, 97, 0x6d, 516}, + /*(2340) VFMSUBSS*/ { 40, 96, 0x6e, 508}, + /*(2341) VFMSUBSS*/ { 41, 97, 0x6e, 507}, + /*(2342) VFMSUBSS*/ { 40, 96, 0x6e, 512}, + /*(2343) VFMSUBSS*/ { 41, 97, 0x6e, 516}, + /*(2344) VFMSUBSD*/ { 40, 96, 0x6f, 508}, + /*(2345) VFMSUBSD*/ { 41, 97, 0x6f, 507}, + /*(2346) VFMSUBSD*/ { 40, 96, 0x6f, 512}, + /*(2347) VFMSUBSD*/ { 41, 97, 0x6f, 516}, + /*(2348) VFNMADDPS*/ { 40, 96, 0x78, 508}, + /*(2349) VFNMADDPS*/ { 41, 97, 0x78, 507}, + /*(2350) VFNMADDPS*/ { 40, 96, 0x78, 512}, + /*(2351) VFNMADDPS*/ { 41, 97, 0x78, 516}, + /*(2352) VFNMADDPS*/ { 40, 96, 0x78, 508}, + /*(2353) VFNMADDPS*/ { 41, 97, 0x78, 507}, + /*(2354) VFNMADDPS*/ { 40, 96, 0x78, 512}, + /*(2355) VFNMADDPS*/ { 41, 97, 0x78, 516}, + /*(2356) VFNMADDPD*/ { 40, 96, 0x79, 508}, + /*(2357) VFNMADDPD*/ { 41, 97, 0x79, 507}, + /*(2358) VFNMADDPD*/ { 40, 96, 0x79, 512}, + /*(2359) VFNMADDPD*/ { 41, 97, 0x79, 516}, + /*(2360) VFNMADDPD*/ { 40, 96, 0x79, 508}, + /*(2361) VFNMADDPD*/ { 41, 97, 0x79, 507}, + /*(2362) VFNMADDPD*/ { 40, 96, 0x79, 512}, + /*(2363) VFNMADDPD*/ { 41, 97, 0x79, 516}, + /*(2364) VFNMADDSS*/ { 40, 96, 0x7a, 508}, + /*(2365) VFNMADDSS*/ { 41, 97, 0x7a, 507}, + /*(2366) VFNMADDSS*/ { 40, 96, 0x7a, 512}, + /*(2367) VFNMADDSS*/ { 41, 97, 0x7a, 516}, + /*(2368) VFNMADDSD*/ { 40, 96, 0x7b, 508}, + /*(2369) VFNMADDSD*/ { 41, 97, 0x7b, 507}, + /*(2370) VFNMADDSD*/ { 40, 96, 0x7b, 512}, + /*(2371) VFNMADDSD*/ { 41, 97, 0x7b, 516}, + /*(2372) VFNMSUBPS*/ { 40, 96, 0x7c, 508}, + /*(2373) VFNMSUBPS*/ { 41, 97, 0x7c, 507}, + /*(2374) VFNMSUBPS*/ { 40, 96, 0x7c, 512}, + /*(2375) VFNMSUBPS*/ { 41, 97, 0x7c, 516}, + /*(2376) VFNMSUBPS*/ { 40, 96, 0x7c, 508}, + /*(2377) VFNMSUBPS*/ { 41, 97, 0x7c, 507}, + /*(2378) VFNMSUBPS*/ { 40, 96, 0x7c, 512}, + /*(2379) VFNMSUBPS*/ { 41, 97, 0x7c, 516}, + /*(2380) VFNMSUBPD*/ { 40, 96, 0x7d, 508}, + /*(2381) VFNMSUBPD*/ { 41, 97, 0x7d, 507}, + /*(2382) VFNMSUBPD*/ { 40, 96, 0x7d, 512}, + /*(2383) VFNMSUBPD*/ { 41, 97, 0x7d, 516}, + /*(2384) VFNMSUBPD*/ { 40, 96, 0x7d, 508}, + /*(2385) VFNMSUBPD*/ { 41, 97, 0x7d, 507}, + /*(2386) VFNMSUBPD*/ { 40, 96, 0x7d, 512}, + /*(2387) VFNMSUBPD*/ { 41, 97, 0x7d, 516}, + /*(2388) VFNMSUBSS*/ { 40, 96, 0x7e, 508}, + /*(2389) VFNMSUBSS*/ { 41, 97, 0x7e, 507}, + /*(2390) VFNMSUBSS*/ { 40, 96, 0x7e, 512}, + /*(2391) VFNMSUBSS*/ { 41, 97, 0x7e, 516}, + /*(2392) VFNMSUBSD*/ { 40, 96, 0x7f, 508}, + /*(2393) VFNMSUBSD*/ { 41, 97, 0x7f, 507}, + /*(2394) VFNMSUBSD*/ { 40, 96, 0x7f, 512}, + /*(2395) VFNMSUBSD*/ { 41, 97, 0x7f, 516}, + /*(2396) VPERMIL2PS*/ { 40, 96, 0x48, 508}, + /*(2397) VPERMIL2PS*/ { 41, 97, 0x48, 507}, + /*(2398) VPERMIL2PS*/ { 40, 96, 0x48, 508}, + /*(2399) VPERMIL2PS*/ { 41, 97, 0x48, 507}, + /*(2400) VPERMIL2PS*/ { 40, 96, 0x48, 512}, + /*(2401) VPERMIL2PS*/ { 41, 97, 0x48, 516}, + /*(2402) VPERMIL2PS*/ { 40, 96, 0x48, 512}, + /*(2403) VPERMIL2PS*/ { 41, 97, 0x48, 516}, + /*(2404) VPERMIL2PD*/ { 40, 96, 0x49, 508}, + /*(2405) VPERMIL2PD*/ { 41, 97, 0x49, 507}, + /*(2406) VPERMIL2PD*/ { 40, 96, 0x49, 508}, + /*(2407) VPERMIL2PD*/ { 41, 97, 0x49, 507}, + /*(2408) VPERMIL2PD*/ { 40, 96, 0x49, 512}, + /*(2409) VPERMIL2PD*/ { 41, 97, 0x49, 516}, + /*(2410) VPERMIL2PD*/ { 40, 96, 0x49, 512}, + /*(2411) VPERMIL2PD*/ { 41, 97, 0x49, 516}, + /*(2412) BNDMK*/ { 27, 18, 0x1b, 1}, + /*(2413) BNDCL*/ { 27, 18, 0x1a, 1}, + /*(2414) BNDCL*/ { 49, 19, 0x1a, 6}, + /*(2415) BNDCL*/ { 49, 19, 0x1a, 6}, + /*(2416) BNDCU*/ { 27, 18, 0x1a, 9}, + /*(2417) BNDCU*/ { 49, 19, 0x1a, 8}, + /*(2418) BNDCU*/ { 49, 19, 0x1a, 8}, + /*(2419) BNDCN*/ { 27, 18, 0x1b, 9}, + /*(2420) BNDCN*/ { 49, 19, 0x1b, 8}, + /*(2421) BNDCN*/ { 49, 19, 0x1b, 8}, + /*(2422) BNDMOV*/ { 15, 41, 0x1a, 155}, + /*(2423) BNDMOV*/ { 14, 100, 0x1a, 121}, + /*(2424) BNDMOV*/ { 14, 100, 0x1a, 121}, + /*(2425) BNDMOV*/ { 14, 100, 0x1a, 121}, + /*(2426) BNDMOV*/ { 15, 41, 0x1b, 155}, + /*(2427) BNDMOV*/ { 14, 100, 0x1b, 121}, + /*(2428) BNDMOV*/ { 14, 100, 0x1b, 121}, + /*(2429) BNDMOV*/ { 14, 100, 0x1b, 121}, + /*(2430) BNDLDX*/ { 14, 18, 0x1a, 26}, + /*(2431) BNDLDX*/ { 50, 18, 0x1a, 181}, + /*(2432) BNDLDX*/ { 50, 18, 0x1a, 187}, + /*(2433) BNDLDX*/ { 50, 18, 0x1a, 287}, + /*(2434) BNDSTX*/ { 14, 18, 0x1b, 26}, + /*(2435) BNDSTX*/ { 50, 18, 0x1b, 181}, + /*(2436) BNDSTX*/ { 50, 18, 0x1b, 187}, + /*(2437) BNDSTX*/ { 50, 18, 0x1b, 287}, + /*(2438) CLRSSBSY*/ { 11, 18, 0xae, 15}, + /*(2439) ENDBR32*/ { 22, 19, 0x1e, 521}, + /*(2440) ENDBR64*/ { 22, 19, 0x1e, 526}, + /*(2441) INCSSPD*/ { 51, 19, 0xae, 323}, + /*(2442) INCSSPQ*/ { 51, 19, 0xae, 531}, + /*(2443) RDSSPD*/ { 23, 19, 0x1e, 229}, + /*(2444) RDSSPQ*/ { 23, 19, 0x1e, 535}, + /*(2445) RSTORSSP*/ { 11, 18, 0x1, 54}, + /*(2446) SAVEPREVSSP*/ { 21, 19, 0x1, 540}, + /*(2447) SETSSBSY*/ { 21, 19, 0x1, 323}, + /*(2448) WRSSD*/ { 28, 70, 0xf6, 181}, + /*(2449) WRSSQ*/ { 28, 70, 0xf6, 137}, + /*(2450) WRUSSD*/ { 28, 70, 0xf5, 187}, + /*(2451) WRUSSQ*/ { 28, 70, 0xf5, 121}, + /*(2452) RDRAND*/ { 20, 19, 0xc7, 73}, + /*(2453) SHA1MSG1*/ { 15, 71, 0xc9, 152}, + /*(2454) SHA1MSG1*/ { 14, 70, 0xc9, 26}, + /*(2455) SHA1MSG2*/ { 15, 71, 0xca, 152}, + /*(2456) SHA1MSG2*/ { 14, 70, 0xca, 26}, + /*(2457) SHA1NEXTE*/ { 15, 71, 0xc8, 152}, + /*(2458) SHA1NEXTE*/ { 14, 70, 0xc8, 26}, + /*(2459) SHA1RNDS4*/ { 15, 75, 0xcc, 152}, + /*(2460) SHA1RNDS4*/ { 14, 74, 0xcc, 26}, + /*(2461) SHA256MSG1*/ { 15, 71, 0xcc, 152}, + /*(2462) SHA256MSG1*/ { 14, 70, 0xcc, 26}, + /*(2463) SHA256MSG2*/ { 15, 71, 0xcd, 152}, + /*(2464) SHA256MSG2*/ { 14, 70, 0xcd, 26}, + /*(2465) SHA256RNDS2*/ { 15, 71, 0xcb, 152}, + /*(2466) SHA256RNDS2*/ { 14, 70, 0xcb, 26}, + /*(2467) XSAVEOPT*/ { 16, 18, 0xae, 544}, + /*(2468) XSAVEOPT64*/ { 16, 18, 0xae, 548}, + /*(2469) XSAVES*/ { 16, 18, 0xc7, 295}, + /*(2470) XSAVES64*/ { 16, 18, 0xc7, 303}, + /*(2471) XRSTORS*/ { 16, 18, 0xc7, 151}, + /*(2472) XRSTORS64*/ { 16, 18, 0xc7, 0}, + /*(2473) XSAVEC*/ { 16, 18, 0xc7, 27}, + /*(2474) XSAVEC64*/ { 16, 18, 0xc7, 299}, + /*(2475) CLFLUSHOPT*/ { 10, 34, 0xae, 131}, + /*(2476) RDSEED*/ { 20, 19, 0xc7, 18}, + /*(2477) RDFSBASE*/ { 20, 19, 0xae, 176}, + /*(2478) RDGSBASE*/ { 20, 19, 0xae, 4}, + /*(2479) WRFSBASE*/ { 20, 19, 0xae, 190}, + /*(2480) WRGSBASE*/ { 20, 19, 0xae, 6}, + /*(2481) CLAC*/ { 25, 19, 0x1, 552}, + /*(2482) STAC*/ { 25, 19, 0x1, 557}, + /*(2483) ENCLU*/ { 25, 19, 0x1, 562}, + /*(2484) ENCLS*/ { 25, 19, 0x1, 567}, + /*(2485) RDPID*/ { 20, 19, 0xc7, 100}, + /*(2486) RDPID*/ { 20, 19, 0xc7, 100}, + /*(2487) PTWRITE*/ { 13, 19, 0xae, 572}, + /*(2488) PTWRITE*/ { 10, 18, 0xae, 250}, + /*(2489) MOVDIR64B*/ { 14, 70, 0xf8, 121}, + /*(2490) MOVDIR64B*/ { 14, 70, 0xf8, 121}, + /*(2491) MOVDIRI*/ { 28, 70, 0xf9, 181}, + /*(2492) MOVDIRI*/ { 28, 70, 0xf9, 137}, + /*(2493) TPAUSE*/ { 13, 19, 0xae, 170}, + /*(2494) UMONITOR*/ { 20, 19, 0xae, 16}, + /*(2495) UMWAIT*/ { 20, 19, 0xae, 79}, + /*(2496) CLDEMOTE*/ { 24, 18, 0x1c, 576}, + /*(2497) ENCLV*/ { 25, 19, 0x1, 580}, + /*(2498) VADDPD*/ { 52, 0, 0x58, 141}, + /*(2499) VADDPD*/ { 53, 1, 0x58, 511}, + /*(2500) VADDPD*/ { 52, 0, 0x58, 141}, + /*(2501) VADDPD*/ { 53, 1, 0x58, 511}, + /*(2502) VADDPD*/ { 54, 1, 0x58, 585}, + /*(2503) VADDPD*/ { 54, 101, 0x58, 591}, + /*(2504) VADDPD*/ { 40, 102, 0x58, 597}, + /*(2505) VADDPD*/ { 54, 1, 0x58, 585}, + /*(2506) VADDPD*/ { 40, 102, 0x58, 597}, + /*(2507) VADDPD*/ { 54, 1, 0x58, 585}, + /*(2508) VADDPD*/ { 40, 102, 0x58, 597}, + /*(2509) VADDPS*/ { 52, 0, 0x58, 121}, + /*(2510) VADDPS*/ { 53, 1, 0x58, 551}, + /*(2511) VADDPS*/ { 52, 0, 0x58, 121}, + /*(2512) VADDPS*/ { 53, 1, 0x58, 551}, + /*(2513) VADDPS*/ { 54, 1, 0x58, 601}, + /*(2514) VADDPS*/ { 54, 101, 0x58, 607}, + /*(2515) VADDPS*/ { 40, 103, 0x58, 613}, + /*(2516) VADDPS*/ { 54, 1, 0x58, 601}, + /*(2517) VADDPS*/ { 40, 103, 0x58, 613}, + /*(2518) VADDPS*/ { 54, 1, 0x58, 601}, + /*(2519) VADDPS*/ { 40, 103, 0x58, 613}, + /*(2520) VADDSD*/ { 52, 0, 0x58, 589}, + /*(2521) VADDSD*/ { 53, 1, 0x58, 617}, + /*(2522) VADDSD*/ { 54, 1, 0x58, 621}, + /*(2523) VADDSD*/ { 54, 104, 0x58, 627}, + /*(2524) VADDSD*/ { 55, 105, 0x58, 633}, + /*(2525) VADDSS*/ { 52, 0, 0x58, 3}, + /*(2526) VADDSS*/ { 53, 1, 0x58, 515}, + /*(2527) VADDSS*/ { 54, 1, 0x58, 638}, + /*(2528) VADDSS*/ { 54, 104, 0x58, 644}, + /*(2529) VADDSS*/ { 55, 106, 0x58, 650}, + /*(2530) VADDSUBPD*/ { 52, 0, 0xd0, 141}, + /*(2531) VADDSUBPD*/ { 53, 1, 0xd0, 511}, + /*(2532) VADDSUBPD*/ { 52, 0, 0xd0, 141}, + /*(2533) VADDSUBPD*/ { 53, 1, 0xd0, 511}, + /*(2534) VADDSUBPS*/ { 52, 0, 0xd0, 589}, + /*(2535) VADDSUBPS*/ { 53, 1, 0xd0, 617}, + /*(2536) VADDSUBPS*/ { 52, 0, 0xd0, 589}, + /*(2537) VADDSUBPS*/ { 53, 1, 0xd0, 617}, + /*(2538) VANDPD*/ { 52, 0, 0x54, 141}, + /*(2539) VANDPD*/ { 53, 1, 0x54, 511}, + /*(2540) VANDPD*/ { 52, 0, 0x54, 141}, + /*(2541) VANDPD*/ { 53, 1, 0x54, 511}, + /*(2542) VANDPD*/ { 54, 1, 0x54, 585}, + /*(2543) VANDPD*/ { 40, 102, 0x54, 597}, + /*(2544) VANDPD*/ { 54, 1, 0x54, 585}, + /*(2545) VANDPD*/ { 40, 102, 0x54, 597}, + /*(2546) VANDPD*/ { 54, 1, 0x54, 585}, + /*(2547) VANDPD*/ { 40, 102, 0x54, 597}, + /*(2548) VANDPS*/ { 52, 0, 0x54, 121}, + /*(2549) VANDPS*/ { 53, 1, 0x54, 551}, + /*(2550) VANDPS*/ { 52, 0, 0x54, 121}, + /*(2551) VANDPS*/ { 53, 1, 0x54, 551}, + /*(2552) VANDPS*/ { 54, 1, 0x54, 601}, + /*(2553) VANDPS*/ { 40, 103, 0x54, 613}, + /*(2554) VANDPS*/ { 54, 1, 0x54, 601}, + /*(2555) VANDPS*/ { 40, 103, 0x54, 613}, + /*(2556) VANDPS*/ { 54, 1, 0x54, 601}, + /*(2557) VANDPS*/ { 40, 103, 0x54, 613}, + /*(2558) VANDNPD*/ { 52, 0, 0x55, 141}, + /*(2559) VANDNPD*/ { 53, 1, 0x55, 511}, + /*(2560) VANDNPD*/ { 52, 0, 0x55, 141}, + /*(2561) VANDNPD*/ { 53, 1, 0x55, 511}, + /*(2562) VANDNPD*/ { 54, 1, 0x55, 585}, + /*(2563) VANDNPD*/ { 40, 102, 0x55, 597}, + /*(2564) VANDNPD*/ { 54, 1, 0x55, 585}, + /*(2565) VANDNPD*/ { 40, 102, 0x55, 597}, + /*(2566) VANDNPD*/ { 54, 1, 0x55, 585}, + /*(2567) VANDNPD*/ { 40, 102, 0x55, 597}, + /*(2568) VANDNPS*/ { 52, 0, 0x55, 121}, + /*(2569) VANDNPS*/ { 53, 1, 0x55, 551}, + /*(2570) VANDNPS*/ { 52, 0, 0x55, 121}, + /*(2571) VANDNPS*/ { 53, 1, 0x55, 551}, + /*(2572) VANDNPS*/ { 54, 1, 0x55, 601}, + /*(2573) VANDNPS*/ { 40, 103, 0x55, 613}, + /*(2574) VANDNPS*/ { 54, 1, 0x55, 601}, + /*(2575) VANDNPS*/ { 40, 103, 0x55, 613}, + /*(2576) VANDNPS*/ { 54, 1, 0x55, 601}, + /*(2577) VANDNPS*/ { 40, 103, 0x55, 613}, + /*(2578) VBLENDPD*/ { 52, 9, 0xd, 119}, + /*(2579) VBLENDPD*/ { 53, 10, 0xd, 118}, + /*(2580) VBLENDPD*/ { 52, 9, 0xd, 119}, + /*(2581) VBLENDPD*/ { 53, 10, 0xd, 118}, + /*(2582) VBLENDPS*/ { 52, 9, 0xc, 119}, + /*(2583) VBLENDPS*/ { 53, 10, 0xc, 118}, + /*(2584) VBLENDPS*/ { 52, 9, 0xc, 119}, + /*(2585) VBLENDPS*/ { 53, 10, 0xc, 118}, + /*(2586) VCMPPD*/ { 52, 9, 0xc2, 141}, + /*(2587) VCMPPD*/ { 53, 10, 0xc2, 511}, + /*(2588) VCMPPD*/ { 52, 9, 0xc2, 141}, + /*(2589) VCMPPD*/ { 53, 10, 0xc2, 511}, + /*(2590) VCMPPD*/ { 56, 10, 0xc2, 655}, + /*(2591) VCMPPD*/ { 56, 107, 0xc2, 662}, + /*(2592) VCMPPD*/ { 57, 108, 0xc2, 597}, + /*(2593) VCMPPD*/ { 56, 10, 0xc2, 655}, + /*(2594) VCMPPD*/ { 57, 108, 0xc2, 597}, + /*(2595) VCMPPD*/ { 56, 10, 0xc2, 655}, + /*(2596) VCMPPD*/ { 57, 108, 0xc2, 597}, + /*(2597) VCMPPS*/ { 52, 9, 0xc2, 121}, + /*(2598) VCMPPS*/ { 53, 10, 0xc2, 551}, + /*(2599) VCMPPS*/ { 52, 9, 0xc2, 121}, + /*(2600) VCMPPS*/ { 53, 10, 0xc2, 551}, + /*(2601) VCMPPS*/ { 56, 10, 0xc2, 669}, + /*(2602) VCMPPS*/ { 56, 107, 0xc2, 676}, + /*(2603) VCMPPS*/ { 57, 109, 0xc2, 683}, + /*(2604) VCMPPS*/ { 56, 10, 0xc2, 669}, + /*(2605) VCMPPS*/ { 57, 109, 0xc2, 683}, + /*(2606) VCMPPS*/ { 56, 10, 0xc2, 669}, + /*(2607) VCMPPS*/ { 57, 109, 0xc2, 683}, + /*(2608) VCMPSD*/ { 52, 9, 0xc2, 589}, + /*(2609) VCMPSD*/ { 53, 10, 0xc2, 617}, + /*(2610) VCMPSD*/ { 56, 10, 0xc2, 688}, + /*(2611) VCMPSD*/ { 56, 110, 0xc2, 627}, + /*(2612) VCMPSD*/ { 58, 111, 0xc2, 633}, + /*(2613) VCMPSS*/ { 52, 9, 0xc2, 3}, + /*(2614) VCMPSS*/ { 53, 10, 0xc2, 515}, + /*(2615) VCMPSS*/ { 56, 10, 0xc2, 695}, + /*(2616) VCMPSS*/ { 56, 110, 0xc2, 644}, + /*(2617) VCMPSS*/ { 58, 112, 0xc2, 650}, + /*(2618) VCOMISD*/ { 44, 0, 0x2f, 702}, + /*(2619) VCOMISD*/ { 45, 1, 0x2f, 707}, + /*(2620) VCOMISD*/ { 59, 113, 0x2f, 713}, + /*(2621) VCOMISD*/ { 59, 114, 0x2f, 724}, + /*(2622) VCOMISD*/ { 60, 115, 0x2f, 735}, + /*(2623) VCOMISS*/ { 44, 0, 0x2f, 745}, + /*(2624) VCOMISS*/ { 45, 1, 0x2f, 750}, + /*(2625) VCOMISS*/ { 59, 113, 0x2f, 756}, + /*(2626) VCOMISS*/ { 59, 114, 0x2f, 767}, + /*(2627) VCOMISS*/ { 60, 116, 0x2f, 778}, + /*(2628) VCVTDQ2PD*/ { 44, 0, 0xe6, 788}, + /*(2629) VCVTDQ2PD*/ { 45, 1, 0xe6, 793}, + /*(2630) VCVTDQ2PD*/ { 44, 0, 0xe6, 788}, + /*(2631) VCVTDQ2PD*/ { 45, 1, 0xe6, 793}, + /*(2632) VCVTDQ2PD*/ { 61, 1, 0xe6, 799}, + /*(2633) VCVTDQ2PD*/ { 61, 117, 0xe6, 808}, + /*(2634) VCVTDQ2PD*/ { 62, 118, 0xe6, 817}, + /*(2635) VCVTDQ2PD*/ { 61, 1, 0xe6, 799}, + /*(2636) VCVTDQ2PD*/ { 62, 118, 0xe6, 817}, + /*(2637) VCVTDQ2PD*/ { 61, 1, 0xe6, 799}, + /*(2638) VCVTDQ2PD*/ { 62, 118, 0xe6, 817}, + /*(2639) VCVTDQ2PS*/ { 44, 0, 0x5b, 745}, + /*(2640) VCVTDQ2PS*/ { 45, 1, 0x5b, 750}, + /*(2641) VCVTDQ2PS*/ { 44, 0, 0x5b, 745}, + /*(2642) VCVTDQ2PS*/ { 45, 1, 0x5b, 750}, + /*(2643) VCVTDQ2PS*/ { 61, 1, 0x5b, 824}, + /*(2644) VCVTDQ2PS*/ { 61, 101, 0x5b, 833}, + /*(2645) VCVTDQ2PS*/ { 62, 103, 0x5b, 842}, + /*(2646) VCVTDQ2PS*/ { 61, 1, 0x5b, 824}, + /*(2647) VCVTDQ2PS*/ { 62, 103, 0x5b, 842}, + /*(2648) VCVTDQ2PS*/ { 61, 1, 0x5b, 824}, + /*(2649) VCVTDQ2PS*/ { 62, 103, 0x5b, 842}, + /*(2650) VCVTPD2DQ*/ { 44, 0, 0xe6, 849}, + /*(2651) VCVTPD2DQ*/ { 45, 1, 0xe6, 854}, + /*(2652) VCVTPD2DQ*/ { 44, 0, 0xe6, 849}, + /*(2653) VCVTPD2DQ*/ { 45, 1, 0xe6, 854}, + /*(2654) VCVTPD2DQ*/ { 61, 1, 0xe6, 860}, + /*(2655) VCVTPD2DQ*/ { 61, 101, 0xe6, 869}, + /*(2656) VCVTPD2DQ*/ { 62, 102, 0xe6, 878}, + /*(2657) VCVTPD2DQ*/ { 61, 1, 0xe6, 860}, + /*(2658) VCVTPD2DQ*/ { 62, 102, 0xe6, 878}, + /*(2659) VCVTPD2DQ*/ { 61, 1, 0xe6, 860}, + /*(2660) VCVTPD2DQ*/ { 62, 102, 0xe6, 878}, + /*(2661) VCVTTPD2DQ*/ { 44, 0, 0xe6, 702}, + /*(2662) VCVTTPD2DQ*/ { 45, 1, 0xe6, 707}, + /*(2663) VCVTTPD2DQ*/ { 44, 0, 0xe6, 702}, + /*(2664) VCVTTPD2DQ*/ { 45, 1, 0xe6, 707}, + /*(2665) VCVTTPD2DQ*/ { 61, 1, 0xe6, 885}, + /*(2666) VCVTTPD2DQ*/ { 61, 119, 0xe6, 894}, + /*(2667) VCVTTPD2DQ*/ { 62, 102, 0xe6, 903}, + /*(2668) VCVTTPD2DQ*/ { 61, 1, 0xe6, 885}, + /*(2669) VCVTTPD2DQ*/ { 62, 102, 0xe6, 903}, + /*(2670) VCVTTPD2DQ*/ { 61, 1, 0xe6, 885}, + /*(2671) VCVTTPD2DQ*/ { 62, 102, 0xe6, 903}, + /*(2672) VCVTPD2PS*/ { 44, 0, 0x5a, 702}, + /*(2673) VCVTPD2PS*/ { 45, 1, 0x5a, 707}, + /*(2674) VCVTPD2PS*/ { 44, 0, 0x5a, 702}, + /*(2675) VCVTPD2PS*/ { 45, 1, 0x5a, 707}, + /*(2676) VCVTPD2PS*/ { 61, 1, 0x5a, 885}, + /*(2677) VCVTPD2PS*/ { 61, 101, 0x5a, 894}, + /*(2678) VCVTPD2PS*/ { 62, 102, 0x5a, 903}, + /*(2679) VCVTPD2PS*/ { 61, 1, 0x5a, 885}, + /*(2680) VCVTPD2PS*/ { 62, 102, 0x5a, 903}, + /*(2681) VCVTPD2PS*/ { 61, 1, 0x5a, 885}, + /*(2682) VCVTPD2PS*/ { 62, 102, 0x5a, 903}, + /*(2683) VCVTPS2DQ*/ { 44, 0, 0x5b, 702}, + /*(2684) VCVTPS2DQ*/ { 45, 1, 0x5b, 707}, + /*(2685) VCVTPS2DQ*/ { 44, 0, 0x5b, 702}, + /*(2686) VCVTPS2DQ*/ { 45, 1, 0x5b, 707}, + /*(2687) VCVTPS2DQ*/ { 61, 1, 0x5b, 910}, + /*(2688) VCVTPS2DQ*/ { 61, 101, 0x5b, 919}, + /*(2689) VCVTPS2DQ*/ { 62, 103, 0x5b, 928}, + /*(2690) VCVTPS2DQ*/ { 61, 1, 0x5b, 910}, + /*(2691) VCVTPS2DQ*/ { 62, 103, 0x5b, 928}, + /*(2692) VCVTPS2DQ*/ { 61, 1, 0x5b, 910}, + /*(2693) VCVTPS2DQ*/ { 62, 103, 0x5b, 928}, + /*(2694) VCVTTPS2DQ*/ { 44, 0, 0x5b, 788}, + /*(2695) VCVTTPS2DQ*/ { 45, 1, 0x5b, 793}, + /*(2696) VCVTTPS2DQ*/ { 44, 0, 0x5b, 788}, + /*(2697) VCVTTPS2DQ*/ { 45, 1, 0x5b, 793}, + /*(2698) VCVTTPS2DQ*/ { 61, 1, 0x5b, 799}, + /*(2699) VCVTTPS2DQ*/ { 61, 119, 0x5b, 808}, + /*(2700) VCVTTPS2DQ*/ { 62, 103, 0x5b, 817}, + /*(2701) VCVTTPS2DQ*/ { 61, 1, 0x5b, 799}, + /*(2702) VCVTTPS2DQ*/ { 62, 103, 0x5b, 817}, + /*(2703) VCVTTPS2DQ*/ { 61, 1, 0x5b, 799}, + /*(2704) VCVTTPS2DQ*/ { 62, 103, 0x5b, 817}, + /*(2705) VCVTPS2PD*/ { 44, 0, 0x5a, 745}, + /*(2706) VCVTPS2PD*/ { 45, 1, 0x5a, 750}, + /*(2707) VCVTPS2PD*/ { 44, 0, 0x5a, 745}, + /*(2708) VCVTPS2PD*/ { 45, 1, 0x5a, 750}, + /*(2709) VCVTPS2PD*/ { 61, 1, 0x5a, 824}, + /*(2710) VCVTPS2PD*/ { 61, 119, 0x5a, 833}, + /*(2711) VCVTPS2PD*/ { 62, 118, 0x5a, 842}, + /*(2712) VCVTPS2PD*/ { 61, 1, 0x5a, 824}, + /*(2713) VCVTPS2PD*/ { 62, 118, 0x5a, 842}, + /*(2714) VCVTPS2PD*/ { 61, 1, 0x5a, 824}, + /*(2715) VCVTPS2PD*/ { 62, 118, 0x5a, 842}, + /*(2716) VCVTSD2SI*/ { 44, 0, 0x2d, 849}, + /*(2717) VCVTSD2SI*/ { 45, 1, 0x2d, 854}, + /*(2718) VCVTSD2SI*/ { 42, 0, 0x2d, 935}, + /*(2719) VCVTSD2SI*/ { 43, 1, 0x2d, 941}, + /*(2720) VCVTSD2SI*/ { 42, 0, 0x2d, 948}, + /*(2721) VCVTSD2SI*/ { 43, 1, 0x2d, 954}, + /*(2722) VCVTSD2SI*/ { 63, 113, 0x2d, 961}, + /*(2723) VCVTSD2SI*/ { 64, 113, 0x2d, 971}, + /*(2724) VCVTSD2SI*/ { 63, 104, 0x2d, 983}, + /*(2725) VCVTSD2SI*/ { 64, 104, 0x2d, 993}, + /*(2726) VCVTSD2SI*/ { 65, 120, 0x2d, 1005}, + /*(2727) VCVTSD2SI*/ { 66, 120, 0x2d, 1014}, + /*(2728) VCVTSD2SI*/ { 64, 113, 0x2d, 1025}, + /*(2729) VCVTSD2SI*/ { 64, 104, 0x2d, 1037}, + /*(2730) VCVTSD2SI*/ { 66, 120, 0x2d, 1049}, + /*(2731) VCVTTSD2SI*/ { 44, 0, 0x2c, 849}, + /*(2732) VCVTTSD2SI*/ { 45, 1, 0x2c, 854}, + /*(2733) VCVTTSD2SI*/ { 42, 0, 0x2c, 935}, + /*(2734) VCVTTSD2SI*/ { 43, 1, 0x2c, 941}, + /*(2735) VCVTTSD2SI*/ { 42, 0, 0x2c, 948}, + /*(2736) VCVTTSD2SI*/ { 43, 1, 0x2c, 954}, + /*(2737) VCVTTSD2SI*/ { 63, 113, 0x2c, 961}, + /*(2738) VCVTTSD2SI*/ { 64, 113, 0x2c, 971}, + /*(2739) VCVTTSD2SI*/ { 63, 114, 0x2c, 983}, + /*(2740) VCVTTSD2SI*/ { 64, 114, 0x2c, 993}, + /*(2741) VCVTTSD2SI*/ { 65, 120, 0x2c, 1005}, + /*(2742) VCVTTSD2SI*/ { 66, 120, 0x2c, 1014}, + /*(2743) VCVTTSD2SI*/ { 64, 113, 0x2c, 1025}, + /*(2744) VCVTTSD2SI*/ { 64, 114, 0x2c, 1037}, + /*(2745) VCVTTSD2SI*/ { 66, 120, 0x2c, 1049}, + /*(2746) VCVTSS2SI*/ { 44, 0, 0x2d, 788}, + /*(2747) VCVTSS2SI*/ { 45, 1, 0x2d, 793}, + /*(2748) VCVTSS2SI*/ { 42, 0, 0x2d, 1060}, + /*(2749) VCVTSS2SI*/ { 43, 1, 0x2d, 1066}, + /*(2750) VCVTSS2SI*/ { 42, 0, 0x2d, 1073}, + /*(2751) VCVTSS2SI*/ { 43, 1, 0x2d, 1079}, + /*(2752) VCVTSS2SI*/ { 63, 113, 0x2d, 1086}, + /*(2753) VCVTSS2SI*/ { 64, 113, 0x2d, 1096}, + /*(2754) VCVTSS2SI*/ { 63, 104, 0x2d, 1108}, + /*(2755) VCVTSS2SI*/ { 64, 104, 0x2d, 1118}, + /*(2756) VCVTSS2SI*/ { 65, 121, 0x2d, 1130}, + /*(2757) VCVTSS2SI*/ { 66, 121, 0x2d, 1139}, + /*(2758) VCVTSS2SI*/ { 64, 113, 0x2d, 1150}, + /*(2759) VCVTSS2SI*/ { 64, 104, 0x2d, 1162}, + /*(2760) VCVTSS2SI*/ { 66, 121, 0x2d, 1174}, + /*(2761) VCVTTSS2SI*/ { 44, 0, 0x2c, 788}, + /*(2762) VCVTTSS2SI*/ { 45, 1, 0x2c, 793}, + /*(2763) VCVTTSS2SI*/ { 42, 0, 0x2c, 1060}, + /*(2764) VCVTTSS2SI*/ { 43, 1, 0x2c, 1066}, + /*(2765) VCVTTSS2SI*/ { 42, 0, 0x2c, 1073}, + /*(2766) VCVTTSS2SI*/ { 43, 1, 0x2c, 1079}, + /*(2767) VCVTTSS2SI*/ { 63, 113, 0x2c, 1086}, + /*(2768) VCVTTSS2SI*/ { 64, 113, 0x2c, 1096}, + /*(2769) VCVTTSS2SI*/ { 63, 114, 0x2c, 1108}, + /*(2770) VCVTTSS2SI*/ { 64, 114, 0x2c, 1118}, + /*(2771) VCVTTSS2SI*/ { 65, 121, 0x2c, 1130}, + /*(2772) VCVTTSS2SI*/ { 66, 121, 0x2c, 1139}, + /*(2773) VCVTTSS2SI*/ { 64, 113, 0x2c, 1150}, + /*(2774) VCVTTSS2SI*/ { 64, 114, 0x2c, 1162}, + /*(2775) VCVTTSS2SI*/ { 66, 121, 0x2c, 1174}, + /*(2776) VCVTSD2SS*/ { 52, 0, 0x5a, 589}, + /*(2777) VCVTSD2SS*/ { 53, 1, 0x5a, 617}, + /*(2778) VCVTSD2SS*/ { 54, 1, 0x5a, 621}, + /*(2779) VCVTSD2SS*/ { 54, 104, 0x5a, 627}, + /*(2780) VCVTSD2SS*/ { 55, 105, 0x5a, 633}, + /*(2781) VCVTSI2SD*/ { 52, 0, 0x2a, 589}, + /*(2782) VCVTSI2SD*/ { 53, 1, 0x2a, 617}, + /*(2783) VCVTSI2SD*/ { 40, 0, 0x2a, 805}, + /*(2784) VCVTSI2SD*/ { 41, 1, 0x2a, 1185}, + /*(2785) VCVTSI2SD*/ { 40, 0, 0x2a, 588}, + /*(2786) VCVTSI2SD*/ { 41, 1, 0x2a, 1190}, + /*(2787) VCVTSI2SD*/ { 67, 113, 0x2a, 1195}, + /*(2788) VCVTSI2SD*/ { 68, 113, 0x2a, 1201}, + /*(2789) VCVTSI2SD*/ { 69, 122, 0x2a, 1208}, + /*(2790) VCVTSI2SD*/ { 70, 122, 0x2a, 1214}, + /*(2791) VCVTSI2SD*/ { 71, 113, 0x2a, 1221}, + /*(2792) VCVTSI2SD*/ { 71, 104, 0x2a, 1229}, + /*(2793) VCVTSI2SD*/ { 70, 123, 0x2a, 1237}, + /*(2794) VCVTSI2SS*/ { 52, 0, 0x2a, 3}, + /*(2795) VCVTSI2SS*/ { 53, 1, 0x2a, 515}, + /*(2796) VCVTSI2SS*/ { 40, 0, 0x2a, 714}, + /*(2797) VCVTSI2SS*/ { 41, 1, 0x2a, 175}, + /*(2798) VCVTSI2SS*/ { 40, 0, 0x2a, 510}, + /*(2799) VCVTSI2SS*/ { 41, 1, 0x2a, 535}, + /*(2800) VCVTSI2SS*/ { 72, 113, 0x2a, 1244}, + /*(2801) VCVTSI2SS*/ { 71, 113, 0x2a, 1251}, + /*(2802) VCVTSI2SS*/ { 72, 104, 0x2a, 1259}, + /*(2803) VCVTSI2SS*/ { 71, 104, 0x2a, 1266}, + /*(2804) VCVTSI2SS*/ { 69, 122, 0x2a, 650}, + /*(2805) VCVTSI2SS*/ { 70, 122, 0x2a, 1274}, + /*(2806) VCVTSI2SS*/ { 71, 113, 0x2a, 1281}, + /*(2807) VCVTSI2SS*/ { 71, 104, 0x2a, 1289}, + /*(2808) VCVTSI2SS*/ { 70, 123, 0x2a, 1297}, + /*(2809) VCVTSS2SD*/ { 52, 0, 0x5a, 3}, + /*(2810) VCVTSS2SD*/ { 53, 1, 0x5a, 515}, + /*(2811) VCVTSS2SD*/ { 54, 1, 0x5a, 638}, + /*(2812) VCVTSS2SD*/ { 54, 114, 0x5a, 644}, + /*(2813) VCVTSS2SD*/ { 55, 106, 0x5a, 650}, + /*(2814) VDIVPD*/ { 52, 0, 0x5e, 141}, + /*(2815) VDIVPD*/ { 53, 1, 0x5e, 511}, + /*(2816) VDIVPD*/ { 52, 0, 0x5e, 141}, + /*(2817) VDIVPD*/ { 53, 1, 0x5e, 511}, + /*(2818) VDIVPD*/ { 54, 1, 0x5e, 585}, + /*(2819) VDIVPD*/ { 54, 101, 0x5e, 591}, + /*(2820) VDIVPD*/ { 40, 102, 0x5e, 597}, + /*(2821) VDIVPD*/ { 54, 1, 0x5e, 585}, + /*(2822) VDIVPD*/ { 40, 102, 0x5e, 597}, + /*(2823) VDIVPD*/ { 54, 1, 0x5e, 585}, + /*(2824) VDIVPD*/ { 40, 102, 0x5e, 597}, + /*(2825) VDIVPS*/ { 52, 0, 0x5e, 121}, + /*(2826) VDIVPS*/ { 53, 1, 0x5e, 551}, + /*(2827) VDIVPS*/ { 52, 0, 0x5e, 121}, + /*(2828) VDIVPS*/ { 53, 1, 0x5e, 551}, + /*(2829) VDIVPS*/ { 54, 1, 0x5e, 601}, + /*(2830) VDIVPS*/ { 54, 101, 0x5e, 607}, + /*(2831) VDIVPS*/ { 40, 103, 0x5e, 613}, + /*(2832) VDIVPS*/ { 54, 1, 0x5e, 601}, + /*(2833) VDIVPS*/ { 40, 103, 0x5e, 613}, + /*(2834) VDIVPS*/ { 54, 1, 0x5e, 601}, + /*(2835) VDIVPS*/ { 40, 103, 0x5e, 613}, + /*(2836) VDIVSD*/ { 52, 0, 0x5e, 589}, + /*(2837) VDIVSD*/ { 53, 1, 0x5e, 617}, + /*(2838) VDIVSD*/ { 54, 1, 0x5e, 621}, + /*(2839) VDIVSD*/ { 54, 104, 0x5e, 627}, + /*(2840) VDIVSD*/ { 55, 105, 0x5e, 633}, + /*(2841) VDIVSS*/ { 52, 0, 0x5e, 3}, + /*(2842) VDIVSS*/ { 53, 1, 0x5e, 515}, + /*(2843) VDIVSS*/ { 54, 1, 0x5e, 638}, + /*(2844) VDIVSS*/ { 54, 104, 0x5e, 644}, + /*(2845) VDIVSS*/ { 55, 106, 0x5e, 650}, + /*(2846) VEXTRACTF128*/ { 42, 9, 0x19, 1304}, + /*(2847) VEXTRACTF128*/ { 43, 10, 0x19, 1310}, + /*(2848) VDPPD*/ { 52, 9, 0x41, 119}, + /*(2849) VDPPD*/ { 53, 10, 0x41, 118}, + /*(2850) VDPPS*/ { 52, 9, 0x40, 119}, + /*(2851) VDPPS*/ { 53, 10, 0x40, 118}, + /*(2852) VDPPS*/ { 52, 9, 0x40, 119}, + /*(2853) VDPPS*/ { 53, 10, 0x40, 118}, + /*(2854) VEXTRACTPS*/ { 44, 9, 0x17, 708}, + /*(2855) VEXTRACTPS*/ { 45, 10, 0x17, 1317}, + /*(2856) VEXTRACTPS*/ { 63, 10, 0x17, 1323}, + /*(2857) VEXTRACTPS*/ { 65, 124, 0x17, 1333}, + /*(2858) VZEROALL*/ { 73, 13, 0x77, 745}, + /*(2859) VZEROUPPER*/ { 73, 13, 0x77, 1342}, + /*(2860) VHADDPD*/ { 52, 0, 0x7c, 141}, + /*(2861) VHADDPD*/ { 53, 1, 0x7c, 511}, + /*(2862) VHADDPD*/ { 52, 0, 0x7c, 141}, + /*(2863) VHADDPD*/ { 53, 1, 0x7c, 511}, + /*(2864) VHADDPS*/ { 52, 0, 0x7c, 589}, + /*(2865) VHADDPS*/ { 53, 1, 0x7c, 617}, + /*(2866) VHADDPS*/ { 52, 0, 0x7c, 589}, + /*(2867) VHADDPS*/ { 53, 1, 0x7c, 617}, + /*(2868) VHSUBPD*/ { 52, 0, 0x7d, 141}, + /*(2869) VHSUBPD*/ { 53, 1, 0x7d, 511}, + /*(2870) VHSUBPD*/ { 52, 0, 0x7d, 141}, + /*(2871) VHSUBPD*/ { 53, 1, 0x7d, 511}, + /*(2872) VHSUBPS*/ { 52, 0, 0x7d, 589}, + /*(2873) VHSUBPS*/ { 53, 1, 0x7d, 617}, + /*(2874) VHSUBPS*/ { 52, 0, 0x7d, 589}, + /*(2875) VHSUBPS*/ { 53, 1, 0x7d, 617}, + /*(2876) VPERMILPD*/ { 40, 0, 0xd, 632}, + /*(2877) VPERMILPD*/ { 41, 1, 0xd, 1348}, + /*(2878) VPERMILPD*/ { 40, 0, 0xd, 632}, + /*(2879) VPERMILPD*/ { 41, 1, 0xd, 1348}, + /*(2880) VPERMILPD*/ { 42, 9, 0x5, 1304}, + /*(2881) VPERMILPD*/ { 43, 10, 0x5, 1310}, + /*(2882) VPERMILPD*/ { 42, 9, 0x5, 1304}, + /*(2883) VPERMILPD*/ { 43, 10, 0x5, 1310}, + /*(2884) VPERMILPD*/ { 61, 10, 0x5, 1353}, + /*(2885) VPERMILPD*/ { 62, 108, 0x5, 716}, + /*(2886) VPERMILPD*/ { 54, 1, 0xd, 1362}, + /*(2887) VPERMILPD*/ { 40, 102, 0xd, 877}, + /*(2888) VPERMILPD*/ { 61, 10, 0x5, 1353}, + /*(2889) VPERMILPD*/ { 62, 108, 0x5, 716}, + /*(2890) VPERMILPD*/ { 54, 1, 0xd, 1362}, + /*(2891) VPERMILPD*/ { 40, 102, 0xd, 877}, + /*(2892) VPERMILPD*/ { 61, 10, 0x5, 1353}, + /*(2893) VPERMILPD*/ { 62, 108, 0x5, 716}, + /*(2894) VPERMILPD*/ { 54, 1, 0xd, 1362}, + /*(2895) VPERMILPD*/ { 40, 102, 0xd, 877}, + /*(2896) VPERMILPS*/ { 40, 0, 0xc, 632}, + /*(2897) VPERMILPS*/ { 41, 1, 0xc, 1348}, + /*(2898) VPERMILPS*/ { 40, 0, 0xc, 632}, + /*(2899) VPERMILPS*/ { 41, 1, 0xc, 1348}, + /*(2900) VPERMILPS*/ { 42, 9, 0x4, 1304}, + /*(2901) VPERMILPS*/ { 43, 10, 0x4, 1310}, + /*(2902) VPERMILPS*/ { 42, 9, 0x4, 1304}, + /*(2903) VPERMILPS*/ { 43, 10, 0x4, 1310}, + /*(2904) VPERMILPS*/ { 61, 10, 0x4, 1368}, + /*(2905) VPERMILPS*/ { 62, 109, 0x4, 912}, + /*(2906) VPERMILPS*/ { 54, 1, 0xc, 1377}, + /*(2907) VPERMILPS*/ { 40, 103, 0xc, 1383}, + /*(2908) VPERMILPS*/ { 61, 10, 0x4, 1368}, + /*(2909) VPERMILPS*/ { 62, 109, 0x4, 912}, + /*(2910) VPERMILPS*/ { 54, 1, 0xc, 1377}, + /*(2911) VPERMILPS*/ { 40, 103, 0xc, 1383}, + /*(2912) VPERMILPS*/ { 61, 10, 0x4, 1368}, + /*(2913) VPERMILPS*/ { 62, 109, 0x4, 912}, + /*(2914) VPERMILPS*/ { 54, 1, 0xc, 1377}, + /*(2915) VPERMILPS*/ { 40, 103, 0xc, 1383}, + /*(2916) VPERM2F128*/ { 40, 9, 0x6, 508}, + /*(2917) VPERM2F128*/ { 41, 10, 0x6, 507}, + /*(2918) VBROADCASTSS*/ { 74, 0, 0x18, 1387}, + /*(2919) VBROADCASTSS*/ { 74, 0, 0x18, 1394}, + /*(2920) VBROADCASTSS*/ { 75, 1, 0x18, 1401}, + /*(2921) VBROADCASTSS*/ { 75, 1, 0x18, 1409}, + /*(2922) VBROADCASTSS*/ { 76, 125, 0x18, 1417}, + /*(2923) VBROADCASTSS*/ { 77, 1, 0x18, 1426}, + /*(2924) VBROADCASTSS*/ { 76, 125, 0x18, 1436}, + /*(2925) VBROADCASTSS*/ { 77, 1, 0x18, 1445}, + /*(2926) VBROADCASTSS*/ { 76, 125, 0x18, 1455}, + /*(2927) VBROADCASTSS*/ { 77, 1, 0x18, 1464}, + /*(2928) VBROADCASTSD*/ { 74, 0, 0x19, 1474}, + /*(2929) VBROADCASTSD*/ { 75, 1, 0x19, 1481}, + /*(2930) VBROADCASTSD*/ { 76, 126, 0x19, 1489}, + /*(2931) VBROADCASTSD*/ { 77, 1, 0x19, 1498}, + /*(2932) VBROADCASTSD*/ { 76, 126, 0x19, 1508}, + /*(2933) VBROADCASTSD*/ { 77, 1, 0x19, 1517}, + /*(2934) VBROADCASTF128*/ { 74, 0, 0x1a, 1527}, + /*(2935) VINSERTF128*/ { 78, 9, 0x18, 1534}, + /*(2936) VINSERTF128*/ { 79, 10, 0x18, 1539}, + /*(2937) VINSERTPS*/ { 52, 9, 0x21, 119}, + /*(2938) VINSERTPS*/ { 53, 10, 0x21, 118}, + /*(2939) VINSERTPS*/ { 71, 10, 0x21, 1545}, + /*(2940) VINSERTPS*/ { 70, 127, 0x21, 1553}, + /*(2941) VLDDQU*/ { 44, 0, 0xf0, 849}, + /*(2942) VLDDQU*/ { 44, 0, 0xf0, 849}, + /*(2943) VMASKMOVPS*/ { 40, 0, 0x2c, 632}, + /*(2944) VMASKMOVPS*/ { 40, 0, 0x2c, 632}, + /*(2945) VMASKMOVPS*/ { 40, 0, 0x2e, 632}, + /*(2946) VMASKMOVPS*/ { 40, 0, 0x2e, 632}, + /*(2947) VMASKMOVPD*/ { 40, 0, 0x2d, 632}, + /*(2948) VMASKMOVPD*/ { 40, 0, 0x2d, 632}, + /*(2949) VMASKMOVPD*/ { 40, 0, 0x2f, 632}, + /*(2950) VMASKMOVPD*/ { 40, 0, 0x2f, 632}, + /*(2951) VPTEST*/ { 44, 0, 0x17, 1560}, + /*(2952) VPTEST*/ { 45, 1, 0x17, 1565}, + /*(2953) VPTEST*/ { 44, 0, 0x17, 1560}, + /*(2954) VPTEST*/ { 45, 1, 0x17, 1565}, + /*(2955) VTESTPS*/ { 42, 0, 0xe, 1388}, + /*(2956) VTESTPS*/ { 43, 1, 0xe, 1402}, + /*(2957) VTESTPS*/ { 42, 0, 0xe, 1388}, + /*(2958) VTESTPS*/ { 43, 1, 0xe, 1402}, + /*(2959) VTESTPD*/ { 42, 0, 0xf, 1388}, + /*(2960) VTESTPD*/ { 43, 1, 0xf, 1402}, + /*(2961) VTESTPD*/ { 42, 0, 0xf, 1388}, + /*(2962) VTESTPD*/ { 43, 1, 0xf, 1402}, + /*(2963) VMAXPD*/ { 52, 0, 0x5f, 141}, + /*(2964) VMAXPD*/ { 53, 1, 0x5f, 511}, + /*(2965) VMAXPD*/ { 52, 0, 0x5f, 141}, + /*(2966) VMAXPD*/ { 53, 1, 0x5f, 511}, + /*(2967) VMAXPD*/ { 54, 1, 0x5f, 585}, + /*(2968) VMAXPD*/ { 54, 119, 0x5f, 591}, + /*(2969) VMAXPD*/ { 40, 102, 0x5f, 597}, + /*(2970) VMAXPD*/ { 54, 1, 0x5f, 585}, + /*(2971) VMAXPD*/ { 40, 102, 0x5f, 597}, + /*(2972) VMAXPD*/ { 54, 1, 0x5f, 585}, + /*(2973) VMAXPD*/ { 40, 102, 0x5f, 597}, + /*(2974) VMAXPS*/ { 52, 0, 0x5f, 121}, + /*(2975) VMAXPS*/ { 53, 1, 0x5f, 551}, + /*(2976) VMAXPS*/ { 52, 0, 0x5f, 121}, + /*(2977) VMAXPS*/ { 53, 1, 0x5f, 551}, + /*(2978) VMAXPS*/ { 54, 1, 0x5f, 601}, + /*(2979) VMAXPS*/ { 54, 119, 0x5f, 607}, + /*(2980) VMAXPS*/ { 40, 103, 0x5f, 613}, + /*(2981) VMAXPS*/ { 54, 1, 0x5f, 601}, + /*(2982) VMAXPS*/ { 40, 103, 0x5f, 613}, + /*(2983) VMAXPS*/ { 54, 1, 0x5f, 601}, + /*(2984) VMAXPS*/ { 40, 103, 0x5f, 613}, + /*(2985) VMAXSD*/ { 52, 0, 0x5f, 589}, + /*(2986) VMAXSD*/ { 53, 1, 0x5f, 617}, + /*(2987) VMAXSD*/ { 54, 1, 0x5f, 621}, + /*(2988) VMAXSD*/ { 54, 114, 0x5f, 627}, + /*(2989) VMAXSD*/ { 55, 105, 0x5f, 633}, + /*(2990) VMAXSS*/ { 52, 0, 0x5f, 3}, + /*(2991) VMAXSS*/ { 53, 1, 0x5f, 515}, + /*(2992) VMAXSS*/ { 54, 1, 0x5f, 638}, + /*(2993) VMAXSS*/ { 54, 114, 0x5f, 644}, + /*(2994) VMAXSS*/ { 55, 106, 0x5f, 650}, + /*(2995) VMINPD*/ { 52, 0, 0x5d, 141}, + /*(2996) VMINPD*/ { 53, 1, 0x5d, 511}, + /*(2997) VMINPD*/ { 52, 0, 0x5d, 141}, + /*(2998) VMINPD*/ { 53, 1, 0x5d, 511}, + /*(2999) VMINPD*/ { 54, 1, 0x5d, 585}, + /*(3000) VMINPD*/ { 54, 119, 0x5d, 591}, + /*(3001) VMINPD*/ { 40, 102, 0x5d, 597}, + /*(3002) VMINPD*/ { 54, 1, 0x5d, 585}, + /*(3003) VMINPD*/ { 40, 102, 0x5d, 597}, + /*(3004) VMINPD*/ { 54, 1, 0x5d, 585}, + /*(3005) VMINPD*/ { 40, 102, 0x5d, 597}, + /*(3006) VMINPS*/ { 52, 0, 0x5d, 121}, + /*(3007) VMINPS*/ { 53, 1, 0x5d, 551}, + /*(3008) VMINPS*/ { 52, 0, 0x5d, 121}, + /*(3009) VMINPS*/ { 53, 1, 0x5d, 551}, + /*(3010) VMINPS*/ { 54, 1, 0x5d, 601}, + /*(3011) VMINPS*/ { 54, 119, 0x5d, 607}, + /*(3012) VMINPS*/ { 40, 103, 0x5d, 613}, + /*(3013) VMINPS*/ { 54, 1, 0x5d, 601}, + /*(3014) VMINPS*/ { 40, 103, 0x5d, 613}, + /*(3015) VMINPS*/ { 54, 1, 0x5d, 601}, + /*(3016) VMINPS*/ { 40, 103, 0x5d, 613}, + /*(3017) VMINSD*/ { 52, 0, 0x5d, 589}, + /*(3018) VMINSD*/ { 53, 1, 0x5d, 617}, + /*(3019) VMINSD*/ { 54, 1, 0x5d, 621}, + /*(3020) VMINSD*/ { 54, 114, 0x5d, 627}, + /*(3021) VMINSD*/ { 55, 105, 0x5d, 633}, + /*(3022) VMINSS*/ { 52, 0, 0x5d, 3}, + /*(3023) VMINSS*/ { 53, 1, 0x5d, 515}, + /*(3024) VMINSS*/ { 54, 1, 0x5d, 638}, + /*(3025) VMINSS*/ { 54, 114, 0x5d, 644}, + /*(3026) VMINSS*/ { 55, 106, 0x5d, 650}, + /*(3027) VMOVAPD*/ { 44, 0, 0x28, 702}, + /*(3028) VMOVAPD*/ { 45, 1, 0x28, 707}, + /*(3029) VMOVAPD*/ { 44, 0, 0x29, 702}, + /*(3030) VMOVAPD*/ { 45, 1, 0x29, 707}, + /*(3031) VMOVAPD*/ { 44, 0, 0x28, 702}, + /*(3032) VMOVAPD*/ { 45, 1, 0x28, 707}, + /*(3033) VMOVAPD*/ { 44, 0, 0x29, 702}, + /*(3034) VMOVAPD*/ { 45, 1, 0x29, 707}, + /*(3035) VMOVAPD*/ { 61, 1, 0x28, 885}, + /*(3036) VMOVAPD*/ { 80, 128, 0x28, 1571}, + /*(3037) VMOVAPD*/ { 61, 1, 0x29, 885}, + /*(3038) VMOVAPD*/ { 81, 128, 0x29, 1579}, + /*(3039) VMOVAPD*/ { 61, 1, 0x28, 885}, + /*(3040) VMOVAPD*/ { 80, 128, 0x28, 1571}, + /*(3041) VMOVAPD*/ { 61, 1, 0x29, 885}, + /*(3042) VMOVAPD*/ { 81, 128, 0x29, 1571}, + /*(3043) VMOVAPD*/ { 61, 1, 0x28, 885}, + /*(3044) VMOVAPD*/ { 80, 128, 0x28, 1571}, + /*(3045) VMOVAPD*/ { 61, 1, 0x29, 885}, + /*(3046) VMOVAPD*/ { 81, 128, 0x29, 1571}, + /*(3047) VMOVAPS*/ { 44, 0, 0x28, 745}, + /*(3048) VMOVAPS*/ { 45, 1, 0x28, 750}, + /*(3049) VMOVAPS*/ { 44, 0, 0x29, 745}, + /*(3050) VMOVAPS*/ { 45, 1, 0x29, 750}, + /*(3051) VMOVAPS*/ { 44, 0, 0x28, 745}, + /*(3052) VMOVAPS*/ { 45, 1, 0x28, 750}, + /*(3053) VMOVAPS*/ { 44, 0, 0x29, 745}, + /*(3054) VMOVAPS*/ { 45, 1, 0x29, 750}, + /*(3055) VMOVAPS*/ { 61, 1, 0x28, 824}, + /*(3056) VMOVAPS*/ { 80, 129, 0x28, 1588}, + /*(3057) VMOVAPS*/ { 61, 1, 0x29, 824}, + /*(3058) VMOVAPS*/ { 81, 129, 0x29, 1596}, + /*(3059) VMOVAPS*/ { 61, 1, 0x28, 824}, + /*(3060) VMOVAPS*/ { 80, 129, 0x28, 1588}, + /*(3061) VMOVAPS*/ { 61, 1, 0x29, 824}, + /*(3062) VMOVAPS*/ { 81, 129, 0x29, 1588}, + /*(3063) VMOVAPS*/ { 61, 1, 0x28, 824}, + /*(3064) VMOVAPS*/ { 80, 129, 0x28, 1588}, + /*(3065) VMOVAPS*/ { 61, 1, 0x29, 824}, + /*(3066) VMOVAPS*/ { 81, 129, 0x29, 1588}, + /*(3067) VMOVD*/ { 44, 0, 0x6e, 702}, + /*(3068) VMOVD*/ { 45, 1, 0x6e, 707}, + /*(3069) VMOVD*/ { 44, 0, 0x7e, 702}, + /*(3070) VMOVD*/ { 45, 1, 0x7e, 707}, + /*(3071) VMOVD*/ { 42, 0, 0x6e, 1605}, + /*(3072) VMOVD*/ { 43, 1, 0x6e, 1611}, + /*(3073) VMOVD*/ { 42, 0, 0x7e, 1605}, + /*(3074) VMOVD*/ { 43, 1, 0x7e, 1611}, + /*(3075) VMOVD*/ { 63, 1, 0x6e, 1618}, + /*(3076) VMOVD*/ { 59, 1, 0x6e, 1628}, + /*(3077) VMOVD*/ { 65, 130, 0x6e, 1639}, + /*(3078) VMOVD*/ { 60, 130, 0x6e, 1648}, + /*(3079) VMOVD*/ { 63, 1, 0x7e, 1618}, + /*(3080) VMOVD*/ { 59, 1, 0x7e, 1628}, + /*(3081) VMOVD*/ { 65, 131, 0x7e, 1639}, + /*(3082) VMOVD*/ { 60, 131, 0x7e, 1648}, + /*(3083) VMOVQ*/ { 42, 0, 0x6e, 1658}, + /*(3084) VMOVQ*/ { 43, 1, 0x6e, 1664}, + /*(3085) VMOVQ*/ { 42, 0, 0x7e, 1658}, + /*(3086) VMOVQ*/ { 43, 1, 0x7e, 1664}, + /*(3087) VMOVQ*/ { 44, 0, 0x7e, 788}, + /*(3088) VMOVQ*/ { 45, 1, 0x7e, 793}, + /*(3089) VMOVQ*/ { 44, 0, 0xd6, 702}, + /*(3090) VMOVQ*/ { 45, 1, 0xd6, 707}, + /*(3091) VMOVQ*/ { 59, 1, 0x6e, 713}, + /*(3092) VMOVQ*/ { 60, 132, 0x6e, 735}, + /*(3093) VMOVQ*/ { 59, 1, 0x7e, 713}, + /*(3094) VMOVQ*/ { 60, 133, 0x7e, 735}, + /*(3095) VMOVQ*/ { 59, 1, 0x7e, 1671}, + /*(3096) VMOVQ*/ { 60, 105, 0x7e, 1682}, + /*(3097) VMOVQ*/ { 59, 1, 0xd6, 713}, + /*(3098) VMOVQ*/ { 60, 105, 0xd6, 735}, + /*(3099) VMOVDDUP*/ { 44, 0, 0x12, 849}, + /*(3100) VMOVDDUP*/ { 45, 1, 0x12, 854}, + /*(3101) VMOVDDUP*/ { 44, 0, 0x12, 849}, + /*(3102) VMOVDDUP*/ { 45, 1, 0x12, 854}, + /*(3103) VMOVDDUP*/ { 61, 1, 0x12, 860}, + /*(3104) VMOVDDUP*/ { 80, 134, 0x12, 1692}, + /*(3105) VMOVDDUP*/ { 61, 1, 0x12, 860}, + /*(3106) VMOVDDUP*/ { 80, 134, 0x12, 1692}, + /*(3107) VMOVDDUP*/ { 61, 1, 0x12, 860}, + /*(3108) VMOVDDUP*/ { 80, 134, 0x12, 1692}, + /*(3109) VMOVDQA*/ { 44, 0, 0x6f, 702}, + /*(3110) VMOVDQA*/ { 45, 1, 0x6f, 707}, + /*(3111) VMOVDQA*/ { 44, 0, 0x7f, 702}, + /*(3112) VMOVDQA*/ { 45, 1, 0x7f, 707}, + /*(3113) VMOVDQA*/ { 44, 0, 0x6f, 702}, + /*(3114) VMOVDQA*/ { 45, 1, 0x6f, 707}, + /*(3115) VMOVDQA*/ { 44, 0, 0x7f, 702}, + /*(3116) VMOVDQA*/ { 45, 1, 0x7f, 707}, + /*(3117) VMOVDQU*/ { 44, 0, 0x6f, 788}, + /*(3118) VMOVDQU*/ { 45, 1, 0x6f, 793}, + /*(3119) VMOVDQU*/ { 44, 0, 0x6f, 788}, + /*(3120) VMOVDQU*/ { 45, 1, 0x6f, 793}, + /*(3121) VMOVDQU*/ { 44, 0, 0x7f, 788}, + /*(3122) VMOVDQU*/ { 45, 1, 0x7f, 793}, + /*(3123) VMOVDQU*/ { 44, 0, 0x7f, 788}, + /*(3124) VMOVDQU*/ { 45, 1, 0x7f, 793}, + /*(3125) VMOVSHDUP*/ { 44, 0, 0x16, 788}, + /*(3126) VMOVSHDUP*/ { 45, 1, 0x16, 793}, + /*(3127) VMOVSHDUP*/ { 44, 0, 0x16, 788}, + /*(3128) VMOVSHDUP*/ { 45, 1, 0x16, 793}, + /*(3129) VMOVSHDUP*/ { 61, 1, 0x16, 799}, + /*(3130) VMOVSHDUP*/ { 80, 129, 0x16, 1130}, + /*(3131) VMOVSHDUP*/ { 61, 1, 0x16, 799}, + /*(3132) VMOVSHDUP*/ { 80, 129, 0x16, 1130}, + /*(3133) VMOVSHDUP*/ { 61, 1, 0x16, 799}, + /*(3134) VMOVSHDUP*/ { 80, 129, 0x16, 1130}, + /*(3135) VMOVSLDUP*/ { 44, 0, 0x12, 788}, + /*(3136) VMOVSLDUP*/ { 45, 1, 0x12, 793}, + /*(3137) VMOVSLDUP*/ { 44, 0, 0x12, 788}, + /*(3138) VMOVSLDUP*/ { 45, 1, 0x12, 793}, + /*(3139) VMOVSLDUP*/ { 61, 1, 0x12, 799}, + /*(3140) VMOVSLDUP*/ { 80, 129, 0x12, 1130}, + /*(3141) VMOVSLDUP*/ { 61, 1, 0x12, 799}, + /*(3142) VMOVSLDUP*/ { 80, 129, 0x12, 1130}, + /*(3143) VMOVSLDUP*/ { 61, 1, 0x12, 799}, + /*(3144) VMOVSLDUP*/ { 80, 129, 0x12, 1130}, + /*(3145) VPOR*/ { 52, 0, 0xeb, 141}, + /*(3146) VPOR*/ { 53, 1, 0xeb, 511}, + /*(3147) VPOR*/ { 52, 0, 0xeb, 141}, + /*(3148) VPOR*/ { 53, 1, 0xeb, 511}, + /*(3149) VPAND*/ { 52, 0, 0xdb, 141}, + /*(3150) VPAND*/ { 53, 1, 0xdb, 511}, + /*(3151) VPAND*/ { 52, 0, 0xdb, 141}, + /*(3152) VPAND*/ { 53, 1, 0xdb, 511}, + /*(3153) VPANDN*/ { 52, 0, 0xdf, 141}, + /*(3154) VPANDN*/ { 53, 1, 0xdf, 511}, + /*(3155) VPANDN*/ { 52, 0, 0xdf, 141}, + /*(3156) VPANDN*/ { 53, 1, 0xdf, 511}, + /*(3157) VPXOR*/ { 52, 0, 0xef, 141}, + /*(3158) VPXOR*/ { 53, 1, 0xef, 511}, + /*(3159) VPXOR*/ { 52, 0, 0xef, 141}, + /*(3160) VPXOR*/ { 53, 1, 0xef, 511}, + /*(3161) VPABSB*/ { 44, 0, 0x1c, 1560}, + /*(3162) VPABSB*/ { 45, 1, 0x1c, 1565}, + /*(3163) VPABSB*/ { 44, 0, 0x1c, 1560}, + /*(3164) VPABSB*/ { 45, 1, 0x1c, 1565}, + /*(3165) VPABSB*/ { 82, 1, 0x1c, 1700}, + /*(3166) VPABSB*/ { 83, 135, 0x1c, 1708}, + /*(3167) VPABSB*/ { 82, 1, 0x1c, 1700}, + /*(3168) VPABSB*/ { 83, 135, 0x1c, 1708}, + /*(3169) VPABSB*/ { 82, 1, 0x1c, 1700}, + /*(3170) VPABSB*/ { 83, 135, 0x1c, 1708}, + /*(3171) VPABSW*/ { 44, 0, 0x1d, 1560}, + /*(3172) VPABSW*/ { 45, 1, 0x1d, 1565}, + /*(3173) VPABSW*/ { 44, 0, 0x1d, 1560}, + /*(3174) VPABSW*/ { 45, 1, 0x1d, 1565}, + /*(3175) VPABSW*/ { 82, 1, 0x1d, 1700}, + /*(3176) VPABSW*/ { 83, 136, 0x1d, 1708}, + /*(3177) VPABSW*/ { 82, 1, 0x1d, 1700}, + /*(3178) VPABSW*/ { 83, 136, 0x1d, 1708}, + /*(3179) VPABSW*/ { 82, 1, 0x1d, 1700}, + /*(3180) VPABSW*/ { 83, 136, 0x1d, 1708}, + /*(3181) VPABSD*/ { 44, 0, 0x1e, 1560}, + /*(3182) VPABSD*/ { 45, 1, 0x1e, 1565}, + /*(3183) VPABSD*/ { 44, 0, 0x1e, 1560}, + /*(3184) VPABSD*/ { 45, 1, 0x1e, 1565}, + /*(3185) VPABSD*/ { 61, 1, 0x1e, 1427}, + /*(3186) VPABSD*/ { 62, 103, 0x1e, 1419}, + /*(3187) VPABSD*/ { 61, 1, 0x1e, 1427}, + /*(3188) VPABSD*/ { 62, 103, 0x1e, 1419}, + /*(3189) VPABSD*/ { 61, 1, 0x1e, 1427}, + /*(3190) VPABSD*/ { 62, 103, 0x1e, 1419}, + /*(3191) VPHMINPOSUW*/ { 44, 0, 0x41, 1560}, + /*(3192) VPHMINPOSUW*/ { 45, 1, 0x41, 1565}, + /*(3193) VPSHUFD*/ { 44, 9, 0x70, 702}, + /*(3194) VPSHUFD*/ { 45, 10, 0x70, 707}, + /*(3195) VPSHUFD*/ { 44, 9, 0x70, 702}, + /*(3196) VPSHUFD*/ { 45, 10, 0x70, 707}, + /*(3197) VPSHUFD*/ { 61, 10, 0x70, 910}, + /*(3198) VPSHUFD*/ { 62, 109, 0x70, 928}, + /*(3199) VPSHUFD*/ { 61, 10, 0x70, 910}, + /*(3200) VPSHUFD*/ { 62, 109, 0x70, 928}, + /*(3201) VPSHUFD*/ { 61, 10, 0x70, 910}, + /*(3202) VPSHUFD*/ { 62, 109, 0x70, 928}, + /*(3203) VPSHUFHW*/ { 44, 9, 0x70, 788}, + /*(3204) VPSHUFHW*/ { 45, 10, 0x70, 793}, + /*(3205) VPSHUFHW*/ { 44, 9, 0x70, 788}, + /*(3206) VPSHUFHW*/ { 45, 10, 0x70, 793}, + /*(3207) VPSHUFHW*/ { 82, 10, 0x70, 1715}, + /*(3208) VPSHUFHW*/ { 83, 137, 0x70, 1154}, + /*(3209) VPSHUFHW*/ { 82, 10, 0x70, 1715}, + /*(3210) VPSHUFHW*/ { 83, 137, 0x70, 1154}, + /*(3211) VPSHUFHW*/ { 82, 10, 0x70, 1715}, + /*(3212) VPSHUFHW*/ { 83, 137, 0x70, 1154}, + /*(3213) VPSHUFLW*/ { 44, 9, 0x70, 849}, + /*(3214) VPSHUFLW*/ { 45, 10, 0x70, 854}, + /*(3215) VPSHUFLW*/ { 44, 9, 0x70, 849}, + /*(3216) VPSHUFLW*/ { 45, 10, 0x70, 854}, + /*(3217) VPSHUFLW*/ { 82, 10, 0x70, 1723}, + /*(3218) VPSHUFLW*/ { 83, 137, 0x70, 1029}, + /*(3219) VPSHUFLW*/ { 82, 10, 0x70, 1723}, + /*(3220) VPSHUFLW*/ { 83, 137, 0x70, 1029}, + /*(3221) VPSHUFLW*/ { 82, 10, 0x70, 1723}, + /*(3222) VPSHUFLW*/ { 83, 137, 0x70, 1029}, + /*(3223) VPACKSSWB*/ { 52, 0, 0x63, 141}, + /*(3224) VPACKSSWB*/ { 53, 1, 0x63, 511}, + /*(3225) VPACKSSWB*/ { 52, 0, 0x63, 141}, + /*(3226) VPACKSSWB*/ { 53, 1, 0x63, 511}, + /*(3227) VPACKSSWB*/ { 84, 1, 0x63, 621}, + /*(3228) VPACKSSWB*/ { 85, 136, 0x63, 633}, + /*(3229) VPACKSSWB*/ { 84, 1, 0x63, 621}, + /*(3230) VPACKSSWB*/ { 85, 136, 0x63, 633}, + /*(3231) VPACKSSWB*/ { 84, 1, 0x63, 621}, + /*(3232) VPACKSSWB*/ { 85, 136, 0x63, 633}, + /*(3233) VPACKSSDW*/ { 52, 0, 0x6b, 141}, + /*(3234) VPACKSSDW*/ { 53, 1, 0x6b, 511}, + /*(3235) VPACKSSDW*/ { 52, 0, 0x6b, 141}, + /*(3236) VPACKSSDW*/ { 53, 1, 0x6b, 511}, + /*(3237) VPACKSSDW*/ { 54, 1, 0x6b, 1731}, + /*(3238) VPACKSSDW*/ { 40, 103, 0x6b, 121}, + /*(3239) VPACKSSDW*/ { 54, 1, 0x6b, 1731}, + /*(3240) VPACKSSDW*/ { 40, 103, 0x6b, 121}, + /*(3241) VPACKSSDW*/ { 54, 1, 0x6b, 1731}, + /*(3242) VPACKSSDW*/ { 40, 103, 0x6b, 121}, + /*(3243) VPACKUSWB*/ { 52, 0, 0x67, 141}, + /*(3244) VPACKUSWB*/ { 53, 1, 0x67, 511}, + /*(3245) VPACKUSWB*/ { 52, 0, 0x67, 141}, + /*(3246) VPACKUSWB*/ { 53, 1, 0x67, 511}, + /*(3247) VPACKUSWB*/ { 84, 1, 0x67, 621}, + /*(3248) VPACKUSWB*/ { 85, 136, 0x67, 633}, + /*(3249) VPACKUSWB*/ { 84, 1, 0x67, 621}, + /*(3250) VPACKUSWB*/ { 85, 136, 0x67, 633}, + /*(3251) VPACKUSWB*/ { 84, 1, 0x67, 621}, + /*(3252) VPACKUSWB*/ { 85, 136, 0x67, 633}, + /*(3253) VPACKUSDW*/ { 52, 0, 0x2b, 590}, + /*(3254) VPACKUSDW*/ { 53, 1, 0x2b, 1363}, + /*(3255) VPACKUSDW*/ { 52, 0, 0x2b, 590}, + /*(3256) VPACKUSDW*/ { 53, 1, 0x2b, 1363}, + /*(3257) VPACKUSDW*/ { 54, 1, 0x2b, 1377}, + /*(3258) VPACKUSDW*/ { 40, 103, 0x2b, 1383}, + /*(3259) VPACKUSDW*/ { 54, 1, 0x2b, 1377}, + /*(3260) VPACKUSDW*/ { 40, 103, 0x2b, 1383}, + /*(3261) VPACKUSDW*/ { 54, 1, 0x2b, 1377}, + /*(3262) VPACKUSDW*/ { 40, 103, 0x2b, 1383}, + /*(3263) VPSLLW*/ { 52, 0, 0xf1, 141}, + /*(3264) VPSLLW*/ { 53, 1, 0xf1, 511}, + /*(3265) VPSLLW*/ { 47, 10, 0x71, 1737}, + /*(3266) VPSLLW*/ { 52, 0, 0xf1, 141}, + /*(3267) VPSLLW*/ { 53, 1, 0xf1, 511}, + /*(3268) VPSLLW*/ { 47, 10, 0x71, 1737}, + /*(3269) VPSLLW*/ { 84, 1, 0xf1, 621}, + /*(3270) VPSLLW*/ { 85, 138, 0xf1, 633}, + /*(3271) VPSLLW*/ { 86, 10, 0x71, 1742}, + /*(3272) VPSLLW*/ { 87, 137, 0x71, 1748}, + /*(3273) VPSLLW*/ { 84, 1, 0xf1, 621}, + /*(3274) VPSLLW*/ { 85, 138, 0xf1, 633}, + /*(3275) VPSLLW*/ { 86, 10, 0x71, 1742}, + /*(3276) VPSLLW*/ { 87, 137, 0x71, 1748}, + /*(3277) VPSLLW*/ { 84, 1, 0xf1, 621}, + /*(3278) VPSLLW*/ { 85, 138, 0xf1, 633}, + /*(3279) VPSLLW*/ { 86, 10, 0x71, 1742}, + /*(3280) VPSLLW*/ { 87, 137, 0x71, 1748}, + /*(3281) VPSLLD*/ { 52, 0, 0xf2, 141}, + /*(3282) VPSLLD*/ { 53, 1, 0xf2, 511}, + /*(3283) VPSLLD*/ { 47, 10, 0x72, 1737}, + /*(3284) VPSLLD*/ { 52, 0, 0xf2, 141}, + /*(3285) VPSLLD*/ { 53, 1, 0xf2, 511}, + /*(3286) VPSLLD*/ { 47, 10, 0x72, 1737}, + /*(3287) VPSLLD*/ { 54, 1, 0xf2, 1731}, + /*(3288) VPSLLD*/ { 55, 139, 0xf2, 1237}, + /*(3289) VPSLLD*/ { 88, 10, 0x72, 1753}, + /*(3290) VPSLLD*/ { 89, 109, 0x72, 1760}, + /*(3291) VPSLLD*/ { 54, 1, 0xf2, 1731}, + /*(3292) VPSLLD*/ { 55, 139, 0xf2, 1237}, + /*(3293) VPSLLD*/ { 88, 10, 0x72, 1753}, + /*(3294) VPSLLD*/ { 89, 109, 0x72, 1760}, + /*(3295) VPSLLD*/ { 54, 1, 0xf2, 1731}, + /*(3296) VPSLLD*/ { 55, 139, 0xf2, 1237}, + /*(3297) VPSLLD*/ { 88, 10, 0x72, 1753}, + /*(3298) VPSLLD*/ { 89, 109, 0x72, 1760}, + /*(3299) VPSLLQ*/ { 52, 0, 0xf3, 141}, + /*(3300) VPSLLQ*/ { 53, 1, 0xf3, 511}, + /*(3301) VPSLLQ*/ { 47, 10, 0x73, 1737}, + /*(3302) VPSLLQ*/ { 52, 0, 0xf3, 141}, + /*(3303) VPSLLQ*/ { 53, 1, 0xf3, 511}, + /*(3304) VPSLLQ*/ { 47, 10, 0x73, 1737}, + /*(3305) VPSLLQ*/ { 54, 1, 0xf3, 585}, + /*(3306) VPSLLQ*/ { 55, 140, 0xf3, 1765}, + /*(3307) VPSLLQ*/ { 88, 10, 0x73, 1770}, + /*(3308) VPSLLQ*/ { 89, 108, 0x73, 1777}, + /*(3309) VPSLLQ*/ { 54, 1, 0xf3, 585}, + /*(3310) VPSLLQ*/ { 55, 140, 0xf3, 1765}, + /*(3311) VPSLLQ*/ { 88, 10, 0x73, 1770}, + /*(3312) VPSLLQ*/ { 89, 108, 0x73, 1777}, + /*(3313) VPSLLQ*/ { 54, 1, 0xf3, 585}, + /*(3314) VPSLLQ*/ { 55, 140, 0xf3, 1765}, + /*(3315) VPSLLQ*/ { 88, 10, 0x73, 1770}, + /*(3316) VPSLLQ*/ { 89, 108, 0x73, 1777}, + /*(3317) VPSRLW*/ { 52, 0, 0xd1, 141}, + /*(3318) VPSRLW*/ { 53, 1, 0xd1, 511}, + /*(3319) VPSRLW*/ { 47, 10, 0x71, 1782}, + /*(3320) VPSRLW*/ { 52, 0, 0xd1, 141}, + /*(3321) VPSRLW*/ { 53, 1, 0xd1, 511}, + /*(3322) VPSRLW*/ { 47, 10, 0x71, 1782}, + /*(3323) VPSRLW*/ { 84, 1, 0xd1, 621}, + /*(3324) VPSRLW*/ { 85, 138, 0xd1, 633}, + /*(3325) VPSRLW*/ { 86, 10, 0x71, 1787}, + /*(3326) VPSRLW*/ { 87, 137, 0x71, 1793}, + /*(3327) VPSRLW*/ { 84, 1, 0xd1, 621}, + /*(3328) VPSRLW*/ { 85, 138, 0xd1, 633}, + /*(3329) VPSRLW*/ { 86, 10, 0x71, 1787}, + /*(3330) VPSRLW*/ { 87, 137, 0x71, 1793}, + /*(3331) VPSRLW*/ { 84, 1, 0xd1, 621}, + /*(3332) VPSRLW*/ { 85, 138, 0xd1, 633}, + /*(3333) VPSRLW*/ { 86, 10, 0x71, 1787}, + /*(3334) VPSRLW*/ { 87, 137, 0x71, 1793}, + /*(3335) VPSRLD*/ { 52, 0, 0xd2, 141}, + /*(3336) VPSRLD*/ { 53, 1, 0xd2, 511}, + /*(3337) VPSRLD*/ { 47, 10, 0x72, 1782}, + /*(3338) VPSRLD*/ { 52, 0, 0xd2, 141}, + /*(3339) VPSRLD*/ { 53, 1, 0xd2, 511}, + /*(3340) VPSRLD*/ { 47, 10, 0x72, 1782}, + /*(3341) VPSRLD*/ { 54, 1, 0xd2, 1731}, + /*(3342) VPSRLD*/ { 55, 139, 0xd2, 1237}, + /*(3343) VPSRLD*/ { 88, 10, 0x72, 1798}, + /*(3344) VPSRLD*/ { 89, 109, 0x72, 1791}, + /*(3345) VPSRLD*/ { 54, 1, 0xd2, 1731}, + /*(3346) VPSRLD*/ { 55, 139, 0xd2, 1237}, + /*(3347) VPSRLD*/ { 88, 10, 0x72, 1798}, + /*(3348) VPSRLD*/ { 89, 109, 0x72, 1791}, + /*(3349) VPSRLD*/ { 54, 1, 0xd2, 1731}, + /*(3350) VPSRLD*/ { 55, 139, 0xd2, 1237}, + /*(3351) VPSRLD*/ { 88, 10, 0x72, 1798}, + /*(3352) VPSRLD*/ { 89, 109, 0x72, 1791}, + /*(3353) VPSRLQ*/ { 52, 0, 0xd3, 141}, + /*(3354) VPSRLQ*/ { 53, 1, 0xd3, 511}, + /*(3355) VPSRLQ*/ { 47, 10, 0x73, 1782}, + /*(3356) VPSRLQ*/ { 52, 0, 0xd3, 141}, + /*(3357) VPSRLQ*/ { 53, 1, 0xd3, 511}, + /*(3358) VPSRLQ*/ { 47, 10, 0x73, 1782}, + /*(3359) VPSRLQ*/ { 54, 1, 0xd3, 585}, + /*(3360) VPSRLQ*/ { 55, 140, 0xd3, 1765}, + /*(3361) VPSRLQ*/ { 88, 10, 0x73, 1805}, + /*(3362) VPSRLQ*/ { 89, 108, 0x73, 1812}, + /*(3363) VPSRLQ*/ { 54, 1, 0xd3, 585}, + /*(3364) VPSRLQ*/ { 55, 140, 0xd3, 1765}, + /*(3365) VPSRLQ*/ { 88, 10, 0x73, 1805}, + /*(3366) VPSRLQ*/ { 89, 108, 0x73, 1812}, + /*(3367) VPSRLQ*/ { 54, 1, 0xd3, 585}, + /*(3368) VPSRLQ*/ { 55, 140, 0xd3, 1765}, + /*(3369) VPSRLQ*/ { 88, 10, 0x73, 1805}, + /*(3370) VPSRLQ*/ { 89, 108, 0x73, 1812}, + /*(3371) VPSRAW*/ { 52, 0, 0xe1, 141}, + /*(3372) VPSRAW*/ { 53, 1, 0xe1, 511}, + /*(3373) VPSRAW*/ { 47, 10, 0x71, 1817}, + /*(3374) VPSRAW*/ { 52, 0, 0xe1, 141}, + /*(3375) VPSRAW*/ { 53, 1, 0xe1, 511}, + /*(3376) VPSRAW*/ { 47, 10, 0x71, 1817}, + /*(3377) VPSRAW*/ { 84, 1, 0xe1, 621}, + /*(3378) VPSRAW*/ { 85, 138, 0xe1, 633}, + /*(3379) VPSRAW*/ { 86, 10, 0x71, 1822}, + /*(3380) VPSRAW*/ { 87, 137, 0x71, 1828}, + /*(3381) VPSRAW*/ { 84, 1, 0xe1, 621}, + /*(3382) VPSRAW*/ { 85, 138, 0xe1, 633}, + /*(3383) VPSRAW*/ { 86, 10, 0x71, 1822}, + /*(3384) VPSRAW*/ { 87, 137, 0x71, 1828}, + /*(3385) VPSRAW*/ { 84, 1, 0xe1, 621}, + /*(3386) VPSRAW*/ { 85, 138, 0xe1, 633}, + /*(3387) VPSRAW*/ { 86, 10, 0x71, 1822}, + /*(3388) VPSRAW*/ { 87, 137, 0x71, 1828}, + /*(3389) VPSRAD*/ { 52, 0, 0xe2, 141}, + /*(3390) VPSRAD*/ { 53, 1, 0xe2, 511}, + /*(3391) VPSRAD*/ { 47, 10, 0x72, 1817}, + /*(3392) VPSRAD*/ { 52, 0, 0xe2, 141}, + /*(3393) VPSRAD*/ { 53, 1, 0xe2, 511}, + /*(3394) VPSRAD*/ { 47, 10, 0x72, 1817}, + /*(3395) VPSRAD*/ { 54, 1, 0xe2, 1731}, + /*(3396) VPSRAD*/ { 55, 139, 0xe2, 1237}, + /*(3397) VPSRAD*/ { 88, 10, 0x72, 1833}, + /*(3398) VPSRAD*/ { 89, 109, 0x72, 1840}, + /*(3399) VPSRAD*/ { 54, 1, 0xe2, 1731}, + /*(3400) VPSRAD*/ { 55, 139, 0xe2, 1237}, + /*(3401) VPSRAD*/ { 88, 10, 0x72, 1833}, + /*(3402) VPSRAD*/ { 89, 109, 0x72, 1840}, + /*(3403) VPSRAD*/ { 54, 1, 0xe2, 1731}, + /*(3404) VPSRAD*/ { 55, 139, 0xe2, 1237}, + /*(3405) VPSRAD*/ { 88, 10, 0x72, 1833}, + /*(3406) VPSRAD*/ { 89, 109, 0x72, 1840}, + /*(3407) VPADDB*/ { 52, 0, 0xfc, 141}, + /*(3408) VPADDB*/ { 53, 1, 0xfc, 511}, + /*(3409) VPADDB*/ { 52, 0, 0xfc, 141}, + /*(3410) VPADDB*/ { 53, 1, 0xfc, 511}, + /*(3411) VPADDB*/ { 84, 1, 0xfc, 621}, + /*(3412) VPADDB*/ { 85, 135, 0xfc, 633}, + /*(3413) VPADDB*/ { 84, 1, 0xfc, 621}, + /*(3414) VPADDB*/ { 85, 135, 0xfc, 633}, + /*(3415) VPADDB*/ { 84, 1, 0xfc, 621}, + /*(3416) VPADDB*/ { 85, 135, 0xfc, 633}, + /*(3417) VPADDW*/ { 52, 0, 0xfd, 141}, + /*(3418) VPADDW*/ { 53, 1, 0xfd, 511}, + /*(3419) VPADDW*/ { 52, 0, 0xfd, 141}, + /*(3420) VPADDW*/ { 53, 1, 0xfd, 511}, + /*(3421) VPADDW*/ { 84, 1, 0xfd, 621}, + /*(3422) VPADDW*/ { 85, 136, 0xfd, 633}, + /*(3423) VPADDW*/ { 84, 1, 0xfd, 621}, + /*(3424) VPADDW*/ { 85, 136, 0xfd, 633}, + /*(3425) VPADDW*/ { 84, 1, 0xfd, 621}, + /*(3426) VPADDW*/ { 85, 136, 0xfd, 633}, + /*(3427) VPADDD*/ { 52, 0, 0xfe, 141}, + /*(3428) VPADDD*/ { 53, 1, 0xfe, 511}, + /*(3429) VPADDD*/ { 52, 0, 0xfe, 141}, + /*(3430) VPADDD*/ { 53, 1, 0xfe, 511}, + /*(3431) VPADDD*/ { 54, 1, 0xfe, 1731}, + /*(3432) VPADDD*/ { 40, 103, 0xfe, 121}, + /*(3433) VPADDD*/ { 54, 1, 0xfe, 1731}, + /*(3434) VPADDD*/ { 40, 103, 0xfe, 121}, + /*(3435) VPADDD*/ { 54, 1, 0xfe, 1731}, + /*(3436) VPADDD*/ { 40, 103, 0xfe, 121}, + /*(3437) VPADDQ*/ { 52, 0, 0xd4, 141}, + /*(3438) VPADDQ*/ { 53, 1, 0xd4, 511}, + /*(3439) VPADDQ*/ { 52, 0, 0xd4, 141}, + /*(3440) VPADDQ*/ { 53, 1, 0xd4, 511}, + /*(3441) VPADDQ*/ { 54, 1, 0xd4, 585}, + /*(3442) VPADDQ*/ { 40, 102, 0xd4, 597}, + /*(3443) VPADDQ*/ { 54, 1, 0xd4, 585}, + /*(3444) VPADDQ*/ { 40, 102, 0xd4, 597}, + /*(3445) VPADDQ*/ { 54, 1, 0xd4, 585}, + /*(3446) VPADDQ*/ { 40, 102, 0xd4, 597}, + /*(3447) VPADDSB*/ { 52, 0, 0xec, 141}, + /*(3448) VPADDSB*/ { 53, 1, 0xec, 511}, + /*(3449) VPADDSB*/ { 52, 0, 0xec, 141}, + /*(3450) VPADDSB*/ { 53, 1, 0xec, 511}, + /*(3451) VPADDSB*/ { 84, 1, 0xec, 621}, + /*(3452) VPADDSB*/ { 85, 135, 0xec, 633}, + /*(3453) VPADDSB*/ { 84, 1, 0xec, 621}, + /*(3454) VPADDSB*/ { 85, 135, 0xec, 633}, + /*(3455) VPADDSB*/ { 84, 1, 0xec, 621}, + /*(3456) VPADDSB*/ { 85, 135, 0xec, 633}, + /*(3457) VPADDSW*/ { 52, 0, 0xed, 141}, + /*(3458) VPADDSW*/ { 53, 1, 0xed, 511}, + /*(3459) VPADDSW*/ { 52, 0, 0xed, 141}, + /*(3460) VPADDSW*/ { 53, 1, 0xed, 511}, + /*(3461) VPADDSW*/ { 84, 1, 0xed, 621}, + /*(3462) VPADDSW*/ { 85, 136, 0xed, 633}, + /*(3463) VPADDSW*/ { 84, 1, 0xed, 621}, + /*(3464) VPADDSW*/ { 85, 136, 0xed, 633}, + /*(3465) VPADDSW*/ { 84, 1, 0xed, 621}, + /*(3466) VPADDSW*/ { 85, 136, 0xed, 633}, + /*(3467) VPADDUSB*/ { 52, 0, 0xdc, 141}, + /*(3468) VPADDUSB*/ { 53, 1, 0xdc, 511}, + /*(3469) VPADDUSB*/ { 52, 0, 0xdc, 141}, + /*(3470) VPADDUSB*/ { 53, 1, 0xdc, 511}, + /*(3471) VPADDUSB*/ { 84, 1, 0xdc, 621}, + /*(3472) VPADDUSB*/ { 85, 135, 0xdc, 633}, + /*(3473) VPADDUSB*/ { 84, 1, 0xdc, 621}, + /*(3474) VPADDUSB*/ { 85, 135, 0xdc, 633}, + /*(3475) VPADDUSB*/ { 84, 1, 0xdc, 621}, + /*(3476) VPADDUSB*/ { 85, 135, 0xdc, 633}, + /*(3477) VPADDUSW*/ { 52, 0, 0xdd, 141}, + /*(3478) VPADDUSW*/ { 53, 1, 0xdd, 511}, + /*(3479) VPADDUSW*/ { 52, 0, 0xdd, 141}, + /*(3480) VPADDUSW*/ { 53, 1, 0xdd, 511}, + /*(3481) VPADDUSW*/ { 84, 1, 0xdd, 621}, + /*(3482) VPADDUSW*/ { 85, 136, 0xdd, 633}, + /*(3483) VPADDUSW*/ { 84, 1, 0xdd, 621}, + /*(3484) VPADDUSW*/ { 85, 136, 0xdd, 633}, + /*(3485) VPADDUSW*/ { 84, 1, 0xdd, 621}, + /*(3486) VPADDUSW*/ { 85, 136, 0xdd, 633}, + /*(3487) VPAVGB*/ { 52, 0, 0xe0, 141}, + /*(3488) VPAVGB*/ { 53, 1, 0xe0, 511}, + /*(3489) VPAVGB*/ { 52, 0, 0xe0, 141}, + /*(3490) VPAVGB*/ { 53, 1, 0xe0, 511}, + /*(3491) VPAVGB*/ { 84, 1, 0xe0, 621}, + /*(3492) VPAVGB*/ { 85, 135, 0xe0, 633}, + /*(3493) VPAVGB*/ { 84, 1, 0xe0, 621}, + /*(3494) VPAVGB*/ { 85, 135, 0xe0, 633}, + /*(3495) VPAVGB*/ { 84, 1, 0xe0, 621}, + /*(3496) VPAVGB*/ { 85, 135, 0xe0, 633}, + /*(3497) VPAVGW*/ { 52, 0, 0xe3, 141}, + /*(3498) VPAVGW*/ { 53, 1, 0xe3, 511}, + /*(3499) VPAVGW*/ { 52, 0, 0xe3, 141}, + /*(3500) VPAVGW*/ { 53, 1, 0xe3, 511}, + /*(3501) VPAVGW*/ { 84, 1, 0xe3, 621}, + /*(3502) VPAVGW*/ { 85, 136, 0xe3, 633}, + /*(3503) VPAVGW*/ { 84, 1, 0xe3, 621}, + /*(3504) VPAVGW*/ { 85, 136, 0xe3, 633}, + /*(3505) VPAVGW*/ { 84, 1, 0xe3, 621}, + /*(3506) VPAVGW*/ { 85, 136, 0xe3, 633}, + /*(3507) VPCMPEQB*/ { 52, 0, 0x74, 141}, + /*(3508) VPCMPEQB*/ { 53, 1, 0x74, 511}, + /*(3509) VPCMPEQB*/ { 52, 0, 0x74, 141}, + /*(3510) VPCMPEQB*/ { 53, 1, 0x74, 511}, + /*(3511) VPCMPEQB*/ { 90, 1, 0x74, 1845}, + /*(3512) VPCMPEQB*/ { 91, 135, 0x74, 1851}, + /*(3513) VPCMPEQB*/ { 90, 1, 0x74, 1845}, + /*(3514) VPCMPEQB*/ { 91, 135, 0x74, 1851}, + /*(3515) VPCMPEQB*/ { 90, 1, 0x74, 1845}, + /*(3516) VPCMPEQB*/ { 91, 135, 0x74, 1851}, + /*(3517) VPCMPEQW*/ { 52, 0, 0x75, 141}, + /*(3518) VPCMPEQW*/ { 53, 1, 0x75, 511}, + /*(3519) VPCMPEQW*/ { 52, 0, 0x75, 141}, + /*(3520) VPCMPEQW*/ { 53, 1, 0x75, 511}, + /*(3521) VPCMPEQW*/ { 90, 1, 0x75, 1845}, + /*(3522) VPCMPEQW*/ { 91, 136, 0x75, 1851}, + /*(3523) VPCMPEQW*/ { 90, 1, 0x75, 1845}, + /*(3524) VPCMPEQW*/ { 91, 136, 0x75, 1851}, + /*(3525) VPCMPEQW*/ { 90, 1, 0x75, 1845}, + /*(3526) VPCMPEQW*/ { 91, 136, 0x75, 1851}, + /*(3527) VPCMPEQD*/ { 52, 0, 0x76, 141}, + /*(3528) VPCMPEQD*/ { 53, 1, 0x76, 511}, + /*(3529) VPCMPEQD*/ { 52, 0, 0x76, 141}, + /*(3530) VPCMPEQD*/ { 53, 1, 0x76, 511}, + /*(3531) VPCMPEQD*/ { 56, 1, 0x76, 1856}, + /*(3532) VPCMPEQD*/ { 57, 103, 0x76, 121}, + /*(3533) VPCMPEQD*/ { 56, 1, 0x76, 1856}, + /*(3534) VPCMPEQD*/ { 57, 103, 0x76, 121}, + /*(3535) VPCMPEQD*/ { 56, 1, 0x76, 1856}, + /*(3536) VPCMPEQD*/ { 57, 103, 0x76, 121}, + /*(3537) VPCMPEQQ*/ { 52, 0, 0x29, 590}, + /*(3538) VPCMPEQQ*/ { 53, 1, 0x29, 1363}, + /*(3539) VPCMPEQQ*/ { 52, 0, 0x29, 590}, + /*(3540) VPCMPEQQ*/ { 53, 1, 0x29, 1363}, + /*(3541) VPCMPEQQ*/ { 56, 1, 0x29, 1362}, + /*(3542) VPCMPEQQ*/ { 57, 102, 0x29, 1863}, + /*(3543) VPCMPEQQ*/ { 56, 1, 0x29, 1362}, + /*(3544) VPCMPEQQ*/ { 57, 102, 0x29, 1863}, + /*(3545) VPCMPEQQ*/ { 56, 1, 0x29, 1362}, + /*(3546) VPCMPEQQ*/ { 57, 102, 0x29, 1863}, + /*(3547) VPCMPGTB*/ { 52, 0, 0x64, 141}, + /*(3548) VPCMPGTB*/ { 53, 1, 0x64, 511}, + /*(3549) VPCMPGTB*/ { 52, 0, 0x64, 141}, + /*(3550) VPCMPGTB*/ { 53, 1, 0x64, 511}, + /*(3551) VPCMPGTB*/ { 90, 1, 0x64, 1845}, + /*(3552) VPCMPGTB*/ { 91, 135, 0x64, 1851}, + /*(3553) VPCMPGTB*/ { 90, 1, 0x64, 1845}, + /*(3554) VPCMPGTB*/ { 91, 135, 0x64, 1851}, + /*(3555) VPCMPGTB*/ { 90, 1, 0x64, 1845}, + /*(3556) VPCMPGTB*/ { 91, 135, 0x64, 1851}, + /*(3557) VPCMPGTW*/ { 52, 0, 0x65, 141}, + /*(3558) VPCMPGTW*/ { 53, 1, 0x65, 511}, + /*(3559) VPCMPGTW*/ { 52, 0, 0x65, 141}, + /*(3560) VPCMPGTW*/ { 53, 1, 0x65, 511}, + /*(3561) VPCMPGTW*/ { 90, 1, 0x65, 1845}, + /*(3562) VPCMPGTW*/ { 91, 136, 0x65, 1851}, + /*(3563) VPCMPGTW*/ { 90, 1, 0x65, 1845}, + /*(3564) VPCMPGTW*/ { 91, 136, 0x65, 1851}, + /*(3565) VPCMPGTW*/ { 90, 1, 0x65, 1845}, + /*(3566) VPCMPGTW*/ { 91, 136, 0x65, 1851}, + /*(3567) VPCMPGTD*/ { 52, 0, 0x66, 141}, + /*(3568) VPCMPGTD*/ { 53, 1, 0x66, 511}, + /*(3569) VPCMPGTD*/ { 52, 0, 0x66, 141}, + /*(3570) VPCMPGTD*/ { 53, 1, 0x66, 511}, + /*(3571) VPCMPGTD*/ { 56, 1, 0x66, 1856}, + /*(3572) VPCMPGTD*/ { 57, 103, 0x66, 121}, + /*(3573) VPCMPGTD*/ { 56, 1, 0x66, 1856}, + /*(3574) VPCMPGTD*/ { 57, 103, 0x66, 121}, + /*(3575) VPCMPGTD*/ { 56, 1, 0x66, 1856}, + /*(3576) VPCMPGTD*/ { 57, 103, 0x66, 121}, + /*(3577) VPCMPGTQ*/ { 52, 0, 0x37, 590}, + /*(3578) VPCMPGTQ*/ { 53, 1, 0x37, 1363}, + /*(3579) VPCMPGTQ*/ { 52, 0, 0x37, 590}, + /*(3580) VPCMPGTQ*/ { 53, 1, 0x37, 1363}, + /*(3581) VPCMPGTQ*/ { 56, 1, 0x37, 1362}, + /*(3582) VPCMPGTQ*/ { 57, 102, 0x37, 1863}, + /*(3583) VPCMPGTQ*/ { 56, 1, 0x37, 1362}, + /*(3584) VPCMPGTQ*/ { 57, 102, 0x37, 1863}, + /*(3585) VPCMPGTQ*/ { 56, 1, 0x37, 1362}, + /*(3586) VPCMPGTQ*/ { 57, 102, 0x37, 1863}, + /*(3587) VPHADDW*/ { 52, 0, 0x1, 590}, + /*(3588) VPHADDW*/ { 53, 1, 0x1, 1363}, + /*(3589) VPHADDW*/ { 52, 0, 0x1, 590}, + /*(3590) VPHADDW*/ { 53, 1, 0x1, 1363}, + /*(3591) VPHADDD*/ { 52, 0, 0x2, 590}, + /*(3592) VPHADDD*/ { 53, 1, 0x2, 1363}, + /*(3593) VPHADDD*/ { 52, 0, 0x2, 590}, + /*(3594) VPHADDD*/ { 53, 1, 0x2, 1363}, + /*(3595) VPHADDSW*/ { 52, 0, 0x3, 590}, + /*(3596) VPHADDSW*/ { 53, 1, 0x3, 1363}, + /*(3597) VPHADDSW*/ { 52, 0, 0x3, 590}, + /*(3598) VPHADDSW*/ { 53, 1, 0x3, 1363}, + /*(3599) VPHSUBW*/ { 52, 0, 0x5, 590}, + /*(3600) VPHSUBW*/ { 53, 1, 0x5, 1363}, + /*(3601) VPHSUBW*/ { 52, 0, 0x5, 590}, + /*(3602) VPHSUBW*/ { 53, 1, 0x5, 1363}, + /*(3603) VPHSUBD*/ { 52, 0, 0x6, 590}, + /*(3604) VPHSUBD*/ { 53, 1, 0x6, 1363}, + /*(3605) VPHSUBD*/ { 52, 0, 0x6, 590}, + /*(3606) VPHSUBD*/ { 53, 1, 0x6, 1363}, + /*(3607) VPHSUBSW*/ { 52, 0, 0x7, 590}, + /*(3608) VPHSUBSW*/ { 53, 1, 0x7, 1363}, + /*(3609) VPHSUBSW*/ { 52, 0, 0x7, 590}, + /*(3610) VPHSUBSW*/ { 53, 1, 0x7, 1363}, + /*(3611) VPMULHUW*/ { 52, 0, 0xe4, 141}, + /*(3612) VPMULHUW*/ { 53, 1, 0xe4, 511}, + /*(3613) VPMULHUW*/ { 52, 0, 0xe4, 141}, + /*(3614) VPMULHUW*/ { 53, 1, 0xe4, 511}, + /*(3615) VPMULHUW*/ { 84, 1, 0xe4, 621}, + /*(3616) VPMULHUW*/ { 85, 136, 0xe4, 633}, + /*(3617) VPMULHUW*/ { 84, 1, 0xe4, 621}, + /*(3618) VPMULHUW*/ { 85, 136, 0xe4, 633}, + /*(3619) VPMULHUW*/ { 84, 1, 0xe4, 621}, + /*(3620) VPMULHUW*/ { 85, 136, 0xe4, 633}, + /*(3621) VPMULHRSW*/ { 52, 0, 0xb, 590}, + /*(3622) VPMULHRSW*/ { 53, 1, 0xb, 1363}, + /*(3623) VPMULHRSW*/ { 52, 0, 0xb, 590}, + /*(3624) VPMULHRSW*/ { 53, 1, 0xb, 1363}, + /*(3625) VPMULHRSW*/ { 84, 1, 0xb, 1868}, + /*(3626) VPMULHRSW*/ { 85, 136, 0xb, 847}, + /*(3627) VPMULHRSW*/ { 84, 1, 0xb, 1868}, + /*(3628) VPMULHRSW*/ { 85, 136, 0xb, 847}, + /*(3629) VPMULHRSW*/ { 84, 1, 0xb, 1868}, + /*(3630) VPMULHRSW*/ { 85, 136, 0xb, 847}, + /*(3631) VPMULHW*/ { 52, 0, 0xe5, 141}, + /*(3632) VPMULHW*/ { 53, 1, 0xe5, 511}, + /*(3633) VPMULHW*/ { 52, 0, 0xe5, 141}, + /*(3634) VPMULHW*/ { 53, 1, 0xe5, 511}, + /*(3635) VPMULHW*/ { 84, 1, 0xe5, 621}, + /*(3636) VPMULHW*/ { 85, 136, 0xe5, 633}, + /*(3637) VPMULHW*/ { 84, 1, 0xe5, 621}, + /*(3638) VPMULHW*/ { 85, 136, 0xe5, 633}, + /*(3639) VPMULHW*/ { 84, 1, 0xe5, 621}, + /*(3640) VPMULHW*/ { 85, 136, 0xe5, 633}, + /*(3641) VPMULLW*/ { 52, 0, 0xd5, 141}, + /*(3642) VPMULLW*/ { 53, 1, 0xd5, 511}, + /*(3643) VPMULLW*/ { 52, 0, 0xd5, 141}, + /*(3644) VPMULLW*/ { 53, 1, 0xd5, 511}, + /*(3645) VPMULLW*/ { 84, 1, 0xd5, 621}, + /*(3646) VPMULLW*/ { 85, 136, 0xd5, 633}, + /*(3647) VPMULLW*/ { 84, 1, 0xd5, 621}, + /*(3648) VPMULLW*/ { 85, 136, 0xd5, 633}, + /*(3649) VPMULLW*/ { 84, 1, 0xd5, 621}, + /*(3650) VPMULLW*/ { 85, 136, 0xd5, 633}, + /*(3651) VPMULLD*/ { 52, 0, 0x40, 590}, + /*(3652) VPMULLD*/ { 53, 1, 0x40, 1363}, + /*(3653) VPMULLD*/ { 52, 0, 0x40, 590}, + /*(3654) VPMULLD*/ { 53, 1, 0x40, 1363}, + /*(3655) VPMULLD*/ { 54, 1, 0x40, 1377}, + /*(3656) VPMULLD*/ { 40, 103, 0x40, 1383}, + /*(3657) VPMULLD*/ { 54, 1, 0x40, 1377}, + /*(3658) VPMULLD*/ { 40, 103, 0x40, 1383}, + /*(3659) VPMULLD*/ { 54, 1, 0x40, 1377}, + /*(3660) VPMULLD*/ { 40, 103, 0x40, 1383}, + /*(3661) VPMULUDQ*/ { 52, 0, 0xf4, 141}, + /*(3662) VPMULUDQ*/ { 53, 1, 0xf4, 511}, + /*(3663) VPMULUDQ*/ { 52, 0, 0xf4, 141}, + /*(3664) VPMULUDQ*/ { 53, 1, 0xf4, 511}, + /*(3665) VPMULUDQ*/ { 54, 1, 0xf4, 585}, + /*(3666) VPMULUDQ*/ { 40, 102, 0xf4, 597}, + /*(3667) VPMULUDQ*/ { 54, 1, 0xf4, 585}, + /*(3668) VPMULUDQ*/ { 40, 102, 0xf4, 597}, + /*(3669) VPMULUDQ*/ { 54, 1, 0xf4, 585}, + /*(3670) VPMULUDQ*/ { 40, 102, 0xf4, 597}, + /*(3671) VPMULDQ*/ { 52, 0, 0x28, 590}, + /*(3672) VPMULDQ*/ { 53, 1, 0x28, 1363}, + /*(3673) VPMULDQ*/ { 52, 0, 0x28, 590}, + /*(3674) VPMULDQ*/ { 53, 1, 0x28, 1363}, + /*(3675) VPMULDQ*/ { 54, 1, 0x28, 1362}, + /*(3676) VPMULDQ*/ { 40, 102, 0x28, 877}, + /*(3677) VPMULDQ*/ { 54, 1, 0x28, 1362}, + /*(3678) VPMULDQ*/ { 40, 102, 0x28, 877}, + /*(3679) VPMULDQ*/ { 54, 1, 0x28, 1362}, + /*(3680) VPMULDQ*/ { 40, 102, 0x28, 877}, + /*(3681) VPSADBW*/ { 52, 0, 0xf6, 141}, + /*(3682) VPSADBW*/ { 53, 1, 0xf6, 511}, + /*(3683) VPSADBW*/ { 52, 0, 0xf6, 141}, + /*(3684) VPSADBW*/ { 53, 1, 0xf6, 511}, + /*(3685) VPSADBW*/ { 72, 1, 0xf6, 1873}, + /*(3686) VPSADBW*/ { 69, 135, 0xf6, 1880}, + /*(3687) VPSADBW*/ { 72, 1, 0xf6, 1873}, + /*(3688) VPSADBW*/ { 69, 135, 0xf6, 1880}, + /*(3689) VPSADBW*/ { 72, 1, 0xf6, 1873}, + /*(3690) VPSADBW*/ { 69, 135, 0xf6, 1880}, + /*(3691) VPSHUFB*/ { 52, 0, 0x0, 590}, + /*(3692) VPSHUFB*/ { 53, 1, 0x0, 1363}, + /*(3693) VPSHUFB*/ { 52, 0, 0x0, 590}, + /*(3694) VPSHUFB*/ { 53, 1, 0x0, 1363}, + /*(3695) VPSHUFB*/ { 84, 1, 0x0, 1868}, + /*(3696) VPSHUFB*/ { 85, 135, 0x0, 847}, + /*(3697) VPSHUFB*/ { 84, 1, 0x0, 1868}, + /*(3698) VPSHUFB*/ { 85, 135, 0x0, 847}, + /*(3699) VPSHUFB*/ { 84, 1, 0x0, 1868}, + /*(3700) VPSHUFB*/ { 85, 135, 0x0, 847}, + /*(3701) VPSIGNB*/ { 52, 0, 0x8, 590}, + /*(3702) VPSIGNB*/ { 53, 1, 0x8, 1363}, + /*(3703) VPSIGNB*/ { 52, 0, 0x8, 590}, + /*(3704) VPSIGNB*/ { 53, 1, 0x8, 1363}, + /*(3705) VPSIGNW*/ { 52, 0, 0x9, 590}, + /*(3706) VPSIGNW*/ { 53, 1, 0x9, 1363}, + /*(3707) VPSIGNW*/ { 52, 0, 0x9, 590}, + /*(3708) VPSIGNW*/ { 53, 1, 0x9, 1363}, + /*(3709) VPSIGND*/ { 52, 0, 0xa, 590}, + /*(3710) VPSIGND*/ { 53, 1, 0xa, 1363}, + /*(3711) VPSIGND*/ { 52, 0, 0xa, 590}, + /*(3712) VPSIGND*/ { 53, 1, 0xa, 1363}, + /*(3713) VPSUBSB*/ { 52, 0, 0xe8, 141}, + /*(3714) VPSUBSB*/ { 53, 1, 0xe8, 511}, + /*(3715) VPSUBSB*/ { 52, 0, 0xe8, 141}, + /*(3716) VPSUBSB*/ { 53, 1, 0xe8, 511}, + /*(3717) VPSUBSB*/ { 84, 1, 0xe8, 621}, + /*(3718) VPSUBSB*/ { 85, 135, 0xe8, 633}, + /*(3719) VPSUBSB*/ { 84, 1, 0xe8, 621}, + /*(3720) VPSUBSB*/ { 85, 135, 0xe8, 633}, + /*(3721) VPSUBSB*/ { 84, 1, 0xe8, 621}, + /*(3722) VPSUBSB*/ { 85, 135, 0xe8, 633}, + /*(3723) VPSUBSW*/ { 52, 0, 0xe9, 141}, + /*(3724) VPSUBSW*/ { 53, 1, 0xe9, 511}, + /*(3725) VPSUBSW*/ { 52, 0, 0xe9, 141}, + /*(3726) VPSUBSW*/ { 53, 1, 0xe9, 511}, + /*(3727) VPSUBSW*/ { 84, 1, 0xe9, 621}, + /*(3728) VPSUBSW*/ { 85, 136, 0xe9, 633}, + /*(3729) VPSUBSW*/ { 84, 1, 0xe9, 621}, + /*(3730) VPSUBSW*/ { 85, 136, 0xe9, 633}, + /*(3731) VPSUBSW*/ { 84, 1, 0xe9, 621}, + /*(3732) VPSUBSW*/ { 85, 136, 0xe9, 633}, + /*(3733) VPSUBUSB*/ { 52, 0, 0xd8, 141}, + /*(3734) VPSUBUSB*/ { 53, 1, 0xd8, 511}, + /*(3735) VPSUBUSB*/ { 52, 0, 0xd8, 141}, + /*(3736) VPSUBUSB*/ { 53, 1, 0xd8, 511}, + /*(3737) VPSUBUSB*/ { 84, 1, 0xd8, 621}, + /*(3738) VPSUBUSB*/ { 85, 135, 0xd8, 633}, + /*(3739) VPSUBUSB*/ { 84, 1, 0xd8, 621}, + /*(3740) VPSUBUSB*/ { 85, 135, 0xd8, 633}, + /*(3741) VPSUBUSB*/ { 84, 1, 0xd8, 621}, + /*(3742) VPSUBUSB*/ { 85, 135, 0xd8, 633}, + /*(3743) VPSUBUSW*/ { 52, 0, 0xd9, 141}, + /*(3744) VPSUBUSW*/ { 53, 1, 0xd9, 511}, + /*(3745) VPSUBUSW*/ { 52, 0, 0xd9, 141}, + /*(3746) VPSUBUSW*/ { 53, 1, 0xd9, 511}, + /*(3747) VPSUBUSW*/ { 84, 1, 0xd9, 621}, + /*(3748) VPSUBUSW*/ { 85, 136, 0xd9, 633}, + /*(3749) VPSUBUSW*/ { 84, 1, 0xd9, 621}, + /*(3750) VPSUBUSW*/ { 85, 136, 0xd9, 633}, + /*(3751) VPSUBUSW*/ { 84, 1, 0xd9, 621}, + /*(3752) VPSUBUSW*/ { 85, 136, 0xd9, 633}, + /*(3753) VPSUBB*/ { 52, 0, 0xf8, 141}, + /*(3754) VPSUBB*/ { 53, 1, 0xf8, 511}, + /*(3755) VPSUBB*/ { 52, 0, 0xf8, 141}, + /*(3756) VPSUBB*/ { 53, 1, 0xf8, 511}, + /*(3757) VPSUBB*/ { 84, 1, 0xf8, 621}, + /*(3758) VPSUBB*/ { 85, 135, 0xf8, 633}, + /*(3759) VPSUBB*/ { 84, 1, 0xf8, 621}, + /*(3760) VPSUBB*/ { 85, 135, 0xf8, 633}, + /*(3761) VPSUBB*/ { 84, 1, 0xf8, 621}, + /*(3762) VPSUBB*/ { 85, 135, 0xf8, 633}, + /*(3763) VPSUBW*/ { 52, 0, 0xf9, 141}, + /*(3764) VPSUBW*/ { 53, 1, 0xf9, 511}, + /*(3765) VPSUBW*/ { 52, 0, 0xf9, 141}, + /*(3766) VPSUBW*/ { 53, 1, 0xf9, 511}, + /*(3767) VPSUBW*/ { 84, 1, 0xf9, 621}, + /*(3768) VPSUBW*/ { 85, 136, 0xf9, 633}, + /*(3769) VPSUBW*/ { 84, 1, 0xf9, 621}, + /*(3770) VPSUBW*/ { 85, 136, 0xf9, 633}, + /*(3771) VPSUBW*/ { 84, 1, 0xf9, 621}, + /*(3772) VPSUBW*/ { 85, 136, 0xf9, 633}, + /*(3773) VPSUBD*/ { 52, 0, 0xfa, 141}, + /*(3774) VPSUBD*/ { 53, 1, 0xfa, 511}, + /*(3775) VPSUBD*/ { 52, 0, 0xfa, 141}, + /*(3776) VPSUBD*/ { 53, 1, 0xfa, 511}, + /*(3777) VPSUBD*/ { 54, 1, 0xfa, 1731}, + /*(3778) VPSUBD*/ { 40, 103, 0xfa, 121}, + /*(3779) VPSUBD*/ { 54, 1, 0xfa, 1731}, + /*(3780) VPSUBD*/ { 40, 103, 0xfa, 121}, + /*(3781) VPSUBD*/ { 54, 1, 0xfa, 1731}, + /*(3782) VPSUBD*/ { 40, 103, 0xfa, 121}, + /*(3783) VPSUBQ*/ { 52, 0, 0xfb, 141}, + /*(3784) VPSUBQ*/ { 53, 1, 0xfb, 511}, + /*(3785) VPSUBQ*/ { 52, 0, 0xfb, 141}, + /*(3786) VPSUBQ*/ { 53, 1, 0xfb, 511}, + /*(3787) VPSUBQ*/ { 54, 1, 0xfb, 585}, + /*(3788) VPSUBQ*/ { 40, 102, 0xfb, 597}, + /*(3789) VPSUBQ*/ { 54, 1, 0xfb, 585}, + /*(3790) VPSUBQ*/ { 40, 102, 0xfb, 597}, + /*(3791) VPSUBQ*/ { 54, 1, 0xfb, 585}, + /*(3792) VPSUBQ*/ { 40, 102, 0xfb, 597}, + /*(3793) VPUNPCKHBW*/ { 52, 0, 0x68, 141}, + /*(3794) VPUNPCKHBW*/ { 53, 1, 0x68, 511}, + /*(3795) VPUNPCKHBW*/ { 52, 0, 0x68, 141}, + /*(3796) VPUNPCKHBW*/ { 53, 1, 0x68, 511}, + /*(3797) VPUNPCKHBW*/ { 84, 1, 0x68, 621}, + /*(3798) VPUNPCKHBW*/ { 85, 135, 0x68, 633}, + /*(3799) VPUNPCKHBW*/ { 84, 1, 0x68, 621}, + /*(3800) VPUNPCKHBW*/ { 85, 135, 0x68, 633}, + /*(3801) VPUNPCKHBW*/ { 84, 1, 0x68, 621}, + /*(3802) VPUNPCKHBW*/ { 85, 135, 0x68, 633}, + /*(3803) VPUNPCKHWD*/ { 52, 0, 0x69, 141}, + /*(3804) VPUNPCKHWD*/ { 53, 1, 0x69, 511}, + /*(3805) VPUNPCKHWD*/ { 52, 0, 0x69, 141}, + /*(3806) VPUNPCKHWD*/ { 53, 1, 0x69, 511}, + /*(3807) VPUNPCKHWD*/ { 84, 1, 0x69, 621}, + /*(3808) VPUNPCKHWD*/ { 85, 136, 0x69, 633}, + /*(3809) VPUNPCKHWD*/ { 84, 1, 0x69, 621}, + /*(3810) VPUNPCKHWD*/ { 85, 136, 0x69, 633}, + /*(3811) VPUNPCKHWD*/ { 84, 1, 0x69, 621}, + /*(3812) VPUNPCKHWD*/ { 85, 136, 0x69, 633}, + /*(3813) VPUNPCKHDQ*/ { 52, 0, 0x6a, 141}, + /*(3814) VPUNPCKHDQ*/ { 53, 1, 0x6a, 511}, + /*(3815) VPUNPCKHDQ*/ { 52, 0, 0x6a, 141}, + /*(3816) VPUNPCKHDQ*/ { 53, 1, 0x6a, 511}, + /*(3817) VPUNPCKHDQ*/ { 54, 1, 0x6a, 1731}, + /*(3818) VPUNPCKHDQ*/ { 40, 103, 0x6a, 121}, + /*(3819) VPUNPCKHDQ*/ { 54, 1, 0x6a, 1731}, + /*(3820) VPUNPCKHDQ*/ { 40, 103, 0x6a, 121}, + /*(3821) VPUNPCKHDQ*/ { 54, 1, 0x6a, 1731}, + /*(3822) VPUNPCKHDQ*/ { 40, 103, 0x6a, 121}, + /*(3823) VPUNPCKHQDQ*/ { 52, 0, 0x6d, 141}, + /*(3824) VPUNPCKHQDQ*/ { 53, 1, 0x6d, 511}, + /*(3825) VPUNPCKHQDQ*/ { 52, 0, 0x6d, 141}, + /*(3826) VPUNPCKHQDQ*/ { 53, 1, 0x6d, 511}, + /*(3827) VPUNPCKHQDQ*/ { 54, 1, 0x6d, 585}, + /*(3828) VPUNPCKHQDQ*/ { 40, 102, 0x6d, 597}, + /*(3829) VPUNPCKHQDQ*/ { 54, 1, 0x6d, 585}, + /*(3830) VPUNPCKHQDQ*/ { 40, 102, 0x6d, 597}, + /*(3831) VPUNPCKHQDQ*/ { 54, 1, 0x6d, 585}, + /*(3832) VPUNPCKHQDQ*/ { 40, 102, 0x6d, 597}, + /*(3833) VPUNPCKLBW*/ { 52, 0, 0x60, 141}, + /*(3834) VPUNPCKLBW*/ { 53, 1, 0x60, 511}, + /*(3835) VPUNPCKLBW*/ { 52, 0, 0x60, 141}, + /*(3836) VPUNPCKLBW*/ { 53, 1, 0x60, 511}, + /*(3837) VPUNPCKLBW*/ { 84, 1, 0x60, 621}, + /*(3838) VPUNPCKLBW*/ { 85, 135, 0x60, 633}, + /*(3839) VPUNPCKLBW*/ { 84, 1, 0x60, 621}, + /*(3840) VPUNPCKLBW*/ { 85, 135, 0x60, 633}, + /*(3841) VPUNPCKLBW*/ { 84, 1, 0x60, 621}, + /*(3842) VPUNPCKLBW*/ { 85, 135, 0x60, 633}, + /*(3843) VPUNPCKLWD*/ { 52, 0, 0x61, 141}, + /*(3844) VPUNPCKLWD*/ { 53, 1, 0x61, 511}, + /*(3845) VPUNPCKLWD*/ { 52, 0, 0x61, 141}, + /*(3846) VPUNPCKLWD*/ { 53, 1, 0x61, 511}, + /*(3847) VPUNPCKLWD*/ { 84, 1, 0x61, 621}, + /*(3848) VPUNPCKLWD*/ { 85, 136, 0x61, 633}, + /*(3849) VPUNPCKLWD*/ { 84, 1, 0x61, 621}, + /*(3850) VPUNPCKLWD*/ { 85, 136, 0x61, 633}, + /*(3851) VPUNPCKLWD*/ { 84, 1, 0x61, 621}, + /*(3852) VPUNPCKLWD*/ { 85, 136, 0x61, 633}, + /*(3853) VPUNPCKLDQ*/ { 52, 0, 0x62, 141}, + /*(3854) VPUNPCKLDQ*/ { 53, 1, 0x62, 511}, + /*(3855) VPUNPCKLDQ*/ { 52, 0, 0x62, 141}, + /*(3856) VPUNPCKLDQ*/ { 53, 1, 0x62, 511}, + /*(3857) VPUNPCKLDQ*/ { 54, 1, 0x62, 1731}, + /*(3858) VPUNPCKLDQ*/ { 40, 103, 0x62, 121}, + /*(3859) VPUNPCKLDQ*/ { 54, 1, 0x62, 1731}, + /*(3860) VPUNPCKLDQ*/ { 40, 103, 0x62, 121}, + /*(3861) VPUNPCKLDQ*/ { 54, 1, 0x62, 1731}, + /*(3862) VPUNPCKLDQ*/ { 40, 103, 0x62, 121}, + /*(3863) VPUNPCKLQDQ*/ { 52, 0, 0x6c, 141}, + /*(3864) VPUNPCKLQDQ*/ { 53, 1, 0x6c, 511}, + /*(3865) VPUNPCKLQDQ*/ { 52, 0, 0x6c, 141}, + /*(3866) VPUNPCKLQDQ*/ { 53, 1, 0x6c, 511}, + /*(3867) VPUNPCKLQDQ*/ { 54, 1, 0x6c, 585}, + /*(3868) VPUNPCKLQDQ*/ { 40, 102, 0x6c, 597}, + /*(3869) VPUNPCKLQDQ*/ { 54, 1, 0x6c, 585}, + /*(3870) VPUNPCKLQDQ*/ { 40, 102, 0x6c, 597}, + /*(3871) VPUNPCKLQDQ*/ { 54, 1, 0x6c, 585}, + /*(3872) VPUNPCKLQDQ*/ { 40, 102, 0x6c, 597}, + /*(3873) VPSRLDQ*/ { 47, 10, 0x73, 515}, + /*(3874) VPSRLDQ*/ { 47, 10, 0x73, 515}, + /*(3875) VPSRLDQ*/ { 92, 10, 0x73, 1886}, + /*(3876) VPSRLDQ*/ { 93, 141, 0x73, 1873}, + /*(3877) VPSRLDQ*/ { 92, 10, 0x73, 1886}, + /*(3878) VPSRLDQ*/ { 93, 141, 0x73, 1873}, + /*(3879) VPSRLDQ*/ { 92, 10, 0x73, 1886}, + /*(3880) VPSRLDQ*/ { 93, 141, 0x73, 1873}, + /*(3881) VPSLLDQ*/ { 47, 10, 0x73, 788}, + /*(3882) VPSLLDQ*/ { 47, 10, 0x73, 788}, + /*(3883) VPSLLDQ*/ { 92, 10, 0x73, 1894}, + /*(3884) VPSLLDQ*/ { 93, 141, 0x73, 1902}, + /*(3885) VPSLLDQ*/ { 92, 10, 0x73, 1894}, + /*(3886) VPSLLDQ*/ { 93, 141, 0x73, 1902}, + /*(3887) VPSLLDQ*/ { 92, 10, 0x73, 1894}, + /*(3888) VPSLLDQ*/ { 93, 141, 0x73, 1902}, + /*(3889) VMOVLHPS*/ { 53, 1, 0x16, 551}, + /*(3890) VMOVLHPS*/ { 71, 1, 0x16, 1909}, + /*(3891) VMOVHLPS*/ { 53, 1, 0x12, 551}, + /*(3892) VMOVHLPS*/ { 71, 1, 0x12, 1909}, + /*(3893) VPALIGNR*/ { 52, 9, 0xf, 119}, + /*(3894) VPALIGNR*/ { 53, 10, 0xf, 118}, + /*(3895) VPALIGNR*/ { 52, 9, 0xf, 119}, + /*(3896) VPALIGNR*/ { 53, 10, 0xf, 118}, + /*(3897) VPALIGNR*/ { 84, 10, 0xf, 1888}, + /*(3898) VPALIGNR*/ { 85, 142, 0xf, 147}, + /*(3899) VPALIGNR*/ { 84, 10, 0xf, 1888}, + /*(3900) VPALIGNR*/ { 85, 142, 0xf, 147}, + /*(3901) VPALIGNR*/ { 84, 10, 0xf, 1888}, + /*(3902) VPALIGNR*/ { 85, 142, 0xf, 147}, + /*(3903) VPBLENDW*/ { 52, 9, 0xe, 119}, + /*(3904) VPBLENDW*/ { 53, 10, 0xe, 118}, + /*(3905) VPBLENDW*/ { 52, 9, 0xe, 119}, + /*(3906) VPBLENDW*/ { 53, 10, 0xe, 118}, + /*(3907) VROUNDPD*/ { 44, 9, 0x9, 708}, + /*(3908) VROUNDPD*/ { 45, 10, 0x9, 1317}, + /*(3909) VROUNDPD*/ { 44, 9, 0x9, 708}, + /*(3910) VROUNDPD*/ { 45, 10, 0x9, 1317}, + /*(3911) VROUNDPS*/ { 44, 9, 0x8, 708}, + /*(3912) VROUNDPS*/ { 45, 10, 0x8, 1317}, + /*(3913) VROUNDPS*/ { 44, 9, 0x8, 708}, + /*(3914) VROUNDPS*/ { 45, 10, 0x8, 1317}, + /*(3915) VROUNDSD*/ { 52, 9, 0xb, 119}, + /*(3916) VROUNDSD*/ { 53, 10, 0xb, 118}, + /*(3917) VROUNDSS*/ { 52, 9, 0xa, 119}, + /*(3918) VROUNDSS*/ { 53, 10, 0xa, 118}, + /*(3919) VSHUFPD*/ { 52, 9, 0xc6, 141}, + /*(3920) VSHUFPD*/ { 53, 10, 0xc6, 511}, + /*(3921) VSHUFPD*/ { 52, 9, 0xc6, 141}, + /*(3922) VSHUFPD*/ { 53, 10, 0xc6, 511}, + /*(3923) VSHUFPD*/ { 54, 10, 0xc6, 585}, + /*(3924) VSHUFPD*/ { 40, 108, 0xc6, 597}, + /*(3925) VSHUFPD*/ { 54, 10, 0xc6, 585}, + /*(3926) VSHUFPD*/ { 40, 108, 0xc6, 597}, + /*(3927) VSHUFPD*/ { 54, 10, 0xc6, 585}, + /*(3928) VSHUFPD*/ { 40, 108, 0xc6, 597}, + /*(3929) VSHUFPS*/ { 52, 9, 0xc6, 121}, + /*(3930) VSHUFPS*/ { 53, 10, 0xc6, 551}, + /*(3931) VSHUFPS*/ { 52, 9, 0xc6, 121}, + /*(3932) VSHUFPS*/ { 53, 10, 0xc6, 551}, + /*(3933) VSHUFPS*/ { 54, 10, 0xc6, 601}, + /*(3934) VSHUFPS*/ { 40, 109, 0xc6, 613}, + /*(3935) VSHUFPS*/ { 54, 10, 0xc6, 601}, + /*(3936) VSHUFPS*/ { 40, 109, 0xc6, 613}, + /*(3937) VSHUFPS*/ { 54, 10, 0xc6, 601}, + /*(3938) VSHUFPS*/ { 40, 109, 0xc6, 613}, + /*(3939) VRCPPS*/ { 44, 0, 0x53, 745}, + /*(3940) VRCPPS*/ { 45, 1, 0x53, 750}, + /*(3941) VRCPPS*/ { 44, 0, 0x53, 745}, + /*(3942) VRCPPS*/ { 45, 1, 0x53, 750}, + /*(3943) VRCPSS*/ { 52, 0, 0x53, 3}, + /*(3944) VRCPSS*/ { 53, 1, 0x53, 515}, + /*(3945) VRSQRTPS*/ { 44, 0, 0x52, 745}, + /*(3946) VRSQRTPS*/ { 45, 1, 0x52, 750}, + /*(3947) VRSQRTPS*/ { 44, 0, 0x52, 745}, + /*(3948) VRSQRTPS*/ { 45, 1, 0x52, 750}, + /*(3949) VRSQRTSS*/ { 52, 0, 0x52, 3}, + /*(3950) VRSQRTSS*/ { 53, 1, 0x52, 515}, + /*(3951) VSQRTPD*/ { 44, 0, 0x51, 702}, + /*(3952) VSQRTPD*/ { 45, 1, 0x51, 707}, + /*(3953) VSQRTPD*/ { 44, 0, 0x51, 702}, + /*(3954) VSQRTPD*/ { 45, 1, 0x51, 707}, + /*(3955) VSQRTPD*/ { 61, 1, 0x51, 885}, + /*(3956) VSQRTPD*/ { 61, 101, 0x51, 894}, + /*(3957) VSQRTPD*/ { 62, 102, 0x51, 903}, + /*(3958) VSQRTPD*/ { 61, 1, 0x51, 885}, + /*(3959) VSQRTPD*/ { 62, 102, 0x51, 903}, + /*(3960) VSQRTPD*/ { 61, 1, 0x51, 885}, + /*(3961) VSQRTPD*/ { 62, 102, 0x51, 903}, + /*(3962) VSQRTPS*/ { 44, 0, 0x51, 745}, + /*(3963) VSQRTPS*/ { 45, 1, 0x51, 750}, + /*(3964) VSQRTPS*/ { 44, 0, 0x51, 745}, + /*(3965) VSQRTPS*/ { 45, 1, 0x51, 750}, + /*(3966) VSQRTPS*/ { 61, 1, 0x51, 824}, + /*(3967) VSQRTPS*/ { 61, 101, 0x51, 833}, + /*(3968) VSQRTPS*/ { 62, 103, 0x51, 842}, + /*(3969) VSQRTPS*/ { 61, 1, 0x51, 824}, + /*(3970) VSQRTPS*/ { 62, 103, 0x51, 842}, + /*(3971) VSQRTPS*/ { 61, 1, 0x51, 824}, + /*(3972) VSQRTPS*/ { 62, 103, 0x51, 842}, + /*(3973) VSQRTSD*/ { 52, 0, 0x51, 589}, + /*(3974) VSQRTSD*/ { 53, 1, 0x51, 617}, + /*(3975) VSQRTSD*/ { 54, 1, 0x51, 621}, + /*(3976) VSQRTSD*/ { 54, 104, 0x51, 627}, + /*(3977) VSQRTSD*/ { 55, 105, 0x51, 633}, + /*(3978) VSQRTSS*/ { 52, 0, 0x51, 3}, + /*(3979) VSQRTSS*/ { 53, 1, 0x51, 515}, + /*(3980) VSQRTSS*/ { 54, 1, 0x51, 638}, + /*(3981) VSQRTSS*/ { 54, 104, 0x51, 644}, + /*(3982) VSQRTSS*/ { 55, 106, 0x51, 650}, + /*(3983) VUNPCKHPD*/ { 52, 0, 0x15, 141}, + /*(3984) VUNPCKHPD*/ { 53, 1, 0x15, 511}, + /*(3985) VUNPCKHPD*/ { 52, 0, 0x15, 141}, + /*(3986) VUNPCKHPD*/ { 53, 1, 0x15, 511}, + /*(3987) VUNPCKHPD*/ { 54, 1, 0x15, 585}, + /*(3988) VUNPCKHPD*/ { 40, 102, 0x15, 597}, + /*(3989) VUNPCKHPD*/ { 54, 1, 0x15, 585}, + /*(3990) VUNPCKHPD*/ { 40, 102, 0x15, 597}, + /*(3991) VUNPCKHPD*/ { 54, 1, 0x15, 585}, + /*(3992) VUNPCKHPD*/ { 40, 102, 0x15, 597}, + /*(3993) VUNPCKHPS*/ { 52, 0, 0x15, 121}, + /*(3994) VUNPCKHPS*/ { 53, 1, 0x15, 551}, + /*(3995) VUNPCKHPS*/ { 52, 0, 0x15, 121}, + /*(3996) VUNPCKHPS*/ { 53, 1, 0x15, 551}, + /*(3997) VUNPCKHPS*/ { 54, 1, 0x15, 601}, + /*(3998) VUNPCKHPS*/ { 40, 103, 0x15, 613}, + /*(3999) VUNPCKHPS*/ { 54, 1, 0x15, 601}, + /*(4000) VUNPCKHPS*/ { 40, 103, 0x15, 613}, + /*(4001) VUNPCKHPS*/ { 54, 1, 0x15, 601}, + /*(4002) VUNPCKHPS*/ { 40, 103, 0x15, 613}, + /*(4003) VSUBPD*/ { 52, 0, 0x5c, 141}, + /*(4004) VSUBPD*/ { 53, 1, 0x5c, 511}, + /*(4005) VSUBPD*/ { 52, 0, 0x5c, 141}, + /*(4006) VSUBPD*/ { 53, 1, 0x5c, 511}, + /*(4007) VSUBPD*/ { 54, 1, 0x5c, 585}, + /*(4008) VSUBPD*/ { 54, 101, 0x5c, 591}, + /*(4009) VSUBPD*/ { 40, 102, 0x5c, 597}, + /*(4010) VSUBPD*/ { 54, 1, 0x5c, 585}, + /*(4011) VSUBPD*/ { 40, 102, 0x5c, 597}, + /*(4012) VSUBPD*/ { 54, 1, 0x5c, 585}, + /*(4013) VSUBPD*/ { 40, 102, 0x5c, 597}, + /*(4014) VSUBPS*/ { 52, 0, 0x5c, 121}, + /*(4015) VSUBPS*/ { 53, 1, 0x5c, 551}, + /*(4016) VSUBPS*/ { 52, 0, 0x5c, 121}, + /*(4017) VSUBPS*/ { 53, 1, 0x5c, 551}, + /*(4018) VSUBPS*/ { 54, 1, 0x5c, 601}, + /*(4019) VSUBPS*/ { 54, 101, 0x5c, 607}, + /*(4020) VSUBPS*/ { 40, 103, 0x5c, 613}, + /*(4021) VSUBPS*/ { 54, 1, 0x5c, 601}, + /*(4022) VSUBPS*/ { 40, 103, 0x5c, 613}, + /*(4023) VSUBPS*/ { 54, 1, 0x5c, 601}, + /*(4024) VSUBPS*/ { 40, 103, 0x5c, 613}, + /*(4025) VSUBSD*/ { 52, 0, 0x5c, 589}, + /*(4026) VSUBSD*/ { 53, 1, 0x5c, 617}, + /*(4027) VSUBSD*/ { 54, 1, 0x5c, 621}, + /*(4028) VSUBSD*/ { 54, 104, 0x5c, 627}, + /*(4029) VSUBSD*/ { 55, 105, 0x5c, 633}, + /*(4030) VSUBSS*/ { 52, 0, 0x5c, 3}, + /*(4031) VSUBSS*/ { 53, 1, 0x5c, 515}, + /*(4032) VSUBSS*/ { 54, 1, 0x5c, 638}, + /*(4033) VSUBSS*/ { 54, 104, 0x5c, 644}, + /*(4034) VSUBSS*/ { 55, 106, 0x5c, 650}, + /*(4035) VMULPD*/ { 52, 0, 0x59, 141}, + /*(4036) VMULPD*/ { 53, 1, 0x59, 511}, + /*(4037) VMULPD*/ { 52, 0, 0x59, 141}, + /*(4038) VMULPD*/ { 53, 1, 0x59, 511}, + /*(4039) VMULPD*/ { 54, 1, 0x59, 585}, + /*(4040) VMULPD*/ { 54, 101, 0x59, 591}, + /*(4041) VMULPD*/ { 40, 102, 0x59, 597}, + /*(4042) VMULPD*/ { 54, 1, 0x59, 585}, + /*(4043) VMULPD*/ { 40, 102, 0x59, 597}, + /*(4044) VMULPD*/ { 54, 1, 0x59, 585}, + /*(4045) VMULPD*/ { 40, 102, 0x59, 597}, + /*(4046) VMULPS*/ { 52, 0, 0x59, 121}, + /*(4047) VMULPS*/ { 53, 1, 0x59, 551}, + /*(4048) VMULPS*/ { 52, 0, 0x59, 121}, + /*(4049) VMULPS*/ { 53, 1, 0x59, 551}, + /*(4050) VMULPS*/ { 54, 1, 0x59, 601}, + /*(4051) VMULPS*/ { 54, 101, 0x59, 607}, + /*(4052) VMULPS*/ { 40, 103, 0x59, 613}, + /*(4053) VMULPS*/ { 54, 1, 0x59, 601}, + /*(4054) VMULPS*/ { 40, 103, 0x59, 613}, + /*(4055) VMULPS*/ { 54, 1, 0x59, 601}, + /*(4056) VMULPS*/ { 40, 103, 0x59, 613}, + /*(4057) VMULSD*/ { 52, 0, 0x59, 589}, + /*(4058) VMULSD*/ { 53, 1, 0x59, 617}, + /*(4059) VMULSD*/ { 54, 1, 0x59, 621}, + /*(4060) VMULSD*/ { 54, 104, 0x59, 627}, + /*(4061) VMULSD*/ { 55, 105, 0x59, 633}, + /*(4062) VMULSS*/ { 52, 0, 0x59, 3}, + /*(4063) VMULSS*/ { 53, 1, 0x59, 515}, + /*(4064) VMULSS*/ { 54, 1, 0x59, 638}, + /*(4065) VMULSS*/ { 54, 104, 0x59, 644}, + /*(4066) VMULSS*/ { 55, 106, 0x59, 650}, + /*(4067) VORPD*/ { 52, 0, 0x56, 141}, + /*(4068) VORPD*/ { 53, 1, 0x56, 511}, + /*(4069) VORPD*/ { 52, 0, 0x56, 141}, + /*(4070) VORPD*/ { 53, 1, 0x56, 511}, + /*(4071) VORPD*/ { 54, 1, 0x56, 585}, + /*(4072) VORPD*/ { 40, 102, 0x56, 597}, + /*(4073) VORPD*/ { 54, 1, 0x56, 585}, + /*(4074) VORPD*/ { 40, 102, 0x56, 597}, + /*(4075) VORPD*/ { 54, 1, 0x56, 585}, + /*(4076) VORPD*/ { 40, 102, 0x56, 597}, + /*(4077) VORPS*/ { 52, 0, 0x56, 121}, + /*(4078) VORPS*/ { 53, 1, 0x56, 551}, + /*(4079) VORPS*/ { 52, 0, 0x56, 121}, + /*(4080) VORPS*/ { 53, 1, 0x56, 551}, + /*(4081) VORPS*/ { 54, 1, 0x56, 601}, + /*(4082) VORPS*/ { 40, 103, 0x56, 613}, + /*(4083) VORPS*/ { 54, 1, 0x56, 601}, + /*(4084) VORPS*/ { 40, 103, 0x56, 613}, + /*(4085) VORPS*/ { 54, 1, 0x56, 601}, + /*(4086) VORPS*/ { 40, 103, 0x56, 613}, + /*(4087) VPMAXSB*/ { 52, 0, 0x3c, 590}, + /*(4088) VPMAXSB*/ { 53, 1, 0x3c, 1363}, + /*(4089) VPMAXSB*/ { 52, 0, 0x3c, 590}, + /*(4090) VPMAXSB*/ { 53, 1, 0x3c, 1363}, + /*(4091) VPMAXSB*/ { 84, 1, 0x3c, 1868}, + /*(4092) VPMAXSB*/ { 85, 135, 0x3c, 847}, + /*(4093) VPMAXSB*/ { 84, 1, 0x3c, 1868}, + /*(4094) VPMAXSB*/ { 85, 135, 0x3c, 847}, + /*(4095) VPMAXSB*/ { 84, 1, 0x3c, 1868}, + /*(4096) VPMAXSB*/ { 85, 135, 0x3c, 847}, + /*(4097) VPMAXSW*/ { 52, 0, 0xee, 141}, + /*(4098) VPMAXSW*/ { 53, 1, 0xee, 511}, + /*(4099) VPMAXSW*/ { 52, 0, 0xee, 141}, + /*(4100) VPMAXSW*/ { 53, 1, 0xee, 511}, + /*(4101) VPMAXSW*/ { 84, 1, 0xee, 621}, + /*(4102) VPMAXSW*/ { 85, 136, 0xee, 633}, + /*(4103) VPMAXSW*/ { 84, 1, 0xee, 621}, + /*(4104) VPMAXSW*/ { 85, 136, 0xee, 633}, + /*(4105) VPMAXSW*/ { 84, 1, 0xee, 621}, + /*(4106) VPMAXSW*/ { 85, 136, 0xee, 633}, + /*(4107) VPMAXSD*/ { 52, 0, 0x3d, 590}, + /*(4108) VPMAXSD*/ { 53, 1, 0x3d, 1363}, + /*(4109) VPMAXSD*/ { 52, 0, 0x3d, 590}, + /*(4110) VPMAXSD*/ { 53, 1, 0x3d, 1363}, + /*(4111) VPMAXSD*/ { 54, 1, 0x3d, 1377}, + /*(4112) VPMAXSD*/ { 40, 103, 0x3d, 1383}, + /*(4113) VPMAXSD*/ { 54, 1, 0x3d, 1377}, + /*(4114) VPMAXSD*/ { 40, 103, 0x3d, 1383}, + /*(4115) VPMAXSD*/ { 54, 1, 0x3d, 1377}, + /*(4116) VPMAXSD*/ { 40, 103, 0x3d, 1383}, + /*(4117) VPMAXUB*/ { 52, 0, 0xde, 141}, + /*(4118) VPMAXUB*/ { 53, 1, 0xde, 511}, + /*(4119) VPMAXUB*/ { 52, 0, 0xde, 141}, + /*(4120) VPMAXUB*/ { 53, 1, 0xde, 511}, + /*(4121) VPMAXUB*/ { 84, 1, 0xde, 621}, + /*(4122) VPMAXUB*/ { 85, 135, 0xde, 633}, + /*(4123) VPMAXUB*/ { 84, 1, 0xde, 621}, + /*(4124) VPMAXUB*/ { 85, 135, 0xde, 633}, + /*(4125) VPMAXUB*/ { 84, 1, 0xde, 621}, + /*(4126) VPMAXUB*/ { 85, 135, 0xde, 633}, + /*(4127) VPMAXUW*/ { 52, 0, 0x3e, 590}, + /*(4128) VPMAXUW*/ { 53, 1, 0x3e, 1363}, + /*(4129) VPMAXUW*/ { 52, 0, 0x3e, 590}, + /*(4130) VPMAXUW*/ { 53, 1, 0x3e, 1363}, + /*(4131) VPMAXUW*/ { 84, 1, 0x3e, 1868}, + /*(4132) VPMAXUW*/ { 85, 136, 0x3e, 847}, + /*(4133) VPMAXUW*/ { 84, 1, 0x3e, 1868}, + /*(4134) VPMAXUW*/ { 85, 136, 0x3e, 847}, + /*(4135) VPMAXUW*/ { 84, 1, 0x3e, 1868}, + /*(4136) VPMAXUW*/ { 85, 136, 0x3e, 847}, + /*(4137) VPMAXUD*/ { 52, 0, 0x3f, 590}, + /*(4138) VPMAXUD*/ { 53, 1, 0x3f, 1363}, + /*(4139) VPMAXUD*/ { 52, 0, 0x3f, 590}, + /*(4140) VPMAXUD*/ { 53, 1, 0x3f, 1363}, + /*(4141) VPMAXUD*/ { 54, 1, 0x3f, 1377}, + /*(4142) VPMAXUD*/ { 40, 103, 0x3f, 1383}, + /*(4143) VPMAXUD*/ { 54, 1, 0x3f, 1377}, + /*(4144) VPMAXUD*/ { 40, 103, 0x3f, 1383}, + /*(4145) VPMAXUD*/ { 54, 1, 0x3f, 1377}, + /*(4146) VPMAXUD*/ { 40, 103, 0x3f, 1383}, + /*(4147) VPMINSB*/ { 52, 0, 0x38, 590}, + /*(4148) VPMINSB*/ { 53, 1, 0x38, 1363}, + /*(4149) VPMINSB*/ { 52, 0, 0x38, 590}, + /*(4150) VPMINSB*/ { 53, 1, 0x38, 1363}, + /*(4151) VPMINSB*/ { 84, 1, 0x38, 1868}, + /*(4152) VPMINSB*/ { 85, 135, 0x38, 847}, + /*(4153) VPMINSB*/ { 84, 1, 0x38, 1868}, + /*(4154) VPMINSB*/ { 85, 135, 0x38, 847}, + /*(4155) VPMINSB*/ { 84, 1, 0x38, 1868}, + /*(4156) VPMINSB*/ { 85, 135, 0x38, 847}, + /*(4157) VPMINSW*/ { 52, 0, 0xea, 141}, + /*(4158) VPMINSW*/ { 53, 1, 0xea, 511}, + /*(4159) VPMINSW*/ { 52, 0, 0xea, 141}, + /*(4160) VPMINSW*/ { 53, 1, 0xea, 511}, + /*(4161) VPMINSW*/ { 84, 1, 0xea, 621}, + /*(4162) VPMINSW*/ { 85, 136, 0xea, 633}, + /*(4163) VPMINSW*/ { 84, 1, 0xea, 621}, + /*(4164) VPMINSW*/ { 85, 136, 0xea, 633}, + /*(4165) VPMINSW*/ { 84, 1, 0xea, 621}, + /*(4166) VPMINSW*/ { 85, 136, 0xea, 633}, + /*(4167) VPMINSD*/ { 52, 0, 0x39, 590}, + /*(4168) VPMINSD*/ { 53, 1, 0x39, 1363}, + /*(4169) VPMINSD*/ { 52, 0, 0x39, 590}, + /*(4170) VPMINSD*/ { 53, 1, 0x39, 1363}, + /*(4171) VPMINSD*/ { 54, 1, 0x39, 1377}, + /*(4172) VPMINSD*/ { 40, 103, 0x39, 1383}, + /*(4173) VPMINSD*/ { 54, 1, 0x39, 1377}, + /*(4174) VPMINSD*/ { 40, 103, 0x39, 1383}, + /*(4175) VPMINSD*/ { 54, 1, 0x39, 1377}, + /*(4176) VPMINSD*/ { 40, 103, 0x39, 1383}, + /*(4177) VPMINUB*/ { 52, 0, 0xda, 141}, + /*(4178) VPMINUB*/ { 53, 1, 0xda, 511}, + /*(4179) VPMINUB*/ { 52, 0, 0xda, 141}, + /*(4180) VPMINUB*/ { 53, 1, 0xda, 511}, + /*(4181) VPMINUB*/ { 84, 1, 0xda, 621}, + /*(4182) VPMINUB*/ { 85, 135, 0xda, 633}, + /*(4183) VPMINUB*/ { 84, 1, 0xda, 621}, + /*(4184) VPMINUB*/ { 85, 135, 0xda, 633}, + /*(4185) VPMINUB*/ { 84, 1, 0xda, 621}, + /*(4186) VPMINUB*/ { 85, 135, 0xda, 633}, + /*(4187) VPMINUW*/ { 52, 0, 0x3a, 590}, + /*(4188) VPMINUW*/ { 53, 1, 0x3a, 1363}, + /*(4189) VPMINUW*/ { 52, 0, 0x3a, 590}, + /*(4190) VPMINUW*/ { 53, 1, 0x3a, 1363}, + /*(4191) VPMINUW*/ { 84, 1, 0x3a, 1868}, + /*(4192) VPMINUW*/ { 85, 136, 0x3a, 847}, + /*(4193) VPMINUW*/ { 84, 1, 0x3a, 1868}, + /*(4194) VPMINUW*/ { 85, 136, 0x3a, 847}, + /*(4195) VPMINUW*/ { 84, 1, 0x3a, 1868}, + /*(4196) VPMINUW*/ { 85, 136, 0x3a, 847}, + /*(4197) VPMINUD*/ { 52, 0, 0x3b, 590}, + /*(4198) VPMINUD*/ { 53, 1, 0x3b, 1363}, + /*(4199) VPMINUD*/ { 52, 0, 0x3b, 590}, + /*(4200) VPMINUD*/ { 53, 1, 0x3b, 1363}, + /*(4201) VPMINUD*/ { 54, 1, 0x3b, 1377}, + /*(4202) VPMINUD*/ { 40, 103, 0x3b, 1383}, + /*(4203) VPMINUD*/ { 54, 1, 0x3b, 1377}, + /*(4204) VPMINUD*/ { 40, 103, 0x3b, 1383}, + /*(4205) VPMINUD*/ { 54, 1, 0x3b, 1377}, + /*(4206) VPMINUD*/ { 40, 103, 0x3b, 1383}, + /*(4207) VPMADDWD*/ { 52, 0, 0xf5, 141}, + /*(4208) VPMADDWD*/ { 53, 1, 0xf5, 511}, + /*(4209) VPMADDWD*/ { 52, 0, 0xf5, 141}, + /*(4210) VPMADDWD*/ { 53, 1, 0xf5, 511}, + /*(4211) VPMADDWD*/ { 84, 1, 0xf5, 621}, + /*(4212) VPMADDWD*/ { 85, 136, 0xf5, 633}, + /*(4213) VPMADDWD*/ { 84, 1, 0xf5, 621}, + /*(4214) VPMADDWD*/ { 85, 136, 0xf5, 633}, + /*(4215) VPMADDWD*/ { 84, 1, 0xf5, 621}, + /*(4216) VPMADDWD*/ { 85, 136, 0xf5, 633}, + /*(4217) VPMADDUBSW*/ { 52, 0, 0x4, 590}, + /*(4218) VPMADDUBSW*/ { 53, 1, 0x4, 1363}, + /*(4219) VPMADDUBSW*/ { 52, 0, 0x4, 590}, + /*(4220) VPMADDUBSW*/ { 53, 1, 0x4, 1363}, + /*(4221) VPMADDUBSW*/ { 84, 1, 0x4, 1868}, + /*(4222) VPMADDUBSW*/ { 85, 136, 0x4, 847}, + /*(4223) VPMADDUBSW*/ { 84, 1, 0x4, 1868}, + /*(4224) VPMADDUBSW*/ { 85, 136, 0x4, 847}, + /*(4225) VPMADDUBSW*/ { 84, 1, 0x4, 1868}, + /*(4226) VPMADDUBSW*/ { 85, 136, 0x4, 847}, + /*(4227) VMPSADBW*/ { 52, 9, 0x42, 119}, + /*(4228) VMPSADBW*/ { 53, 10, 0x42, 118}, + /*(4229) VMPSADBW*/ { 52, 9, 0x42, 119}, + /*(4230) VMPSADBW*/ { 53, 10, 0x42, 118}, + /*(4231) VUCOMISD*/ { 44, 0, 0x2e, 702}, + /*(4232) VUCOMISD*/ { 45, 1, 0x2e, 707}, + /*(4233) VUCOMISD*/ { 59, 113, 0x2e, 713}, + /*(4234) VUCOMISD*/ { 59, 114, 0x2e, 724}, + /*(4235) VUCOMISD*/ { 60, 115, 0x2e, 735}, + /*(4236) VUCOMISS*/ { 44, 0, 0x2e, 745}, + /*(4237) VUCOMISS*/ { 45, 1, 0x2e, 750}, + /*(4238) VUCOMISS*/ { 59, 113, 0x2e, 756}, + /*(4239) VUCOMISS*/ { 59, 114, 0x2e, 767}, + /*(4240) VUCOMISS*/ { 60, 116, 0x2e, 778}, + /*(4241) VUNPCKLPD*/ { 52, 0, 0x14, 141}, + /*(4242) VUNPCKLPD*/ { 53, 1, 0x14, 511}, + /*(4243) VUNPCKLPD*/ { 52, 0, 0x14, 141}, + /*(4244) VUNPCKLPD*/ { 53, 1, 0x14, 511}, + /*(4245) VUNPCKLPD*/ { 54, 1, 0x14, 585}, + /*(4246) VUNPCKLPD*/ { 40, 102, 0x14, 597}, + /*(4247) VUNPCKLPD*/ { 54, 1, 0x14, 585}, + /*(4248) VUNPCKLPD*/ { 40, 102, 0x14, 597}, + /*(4249) VUNPCKLPD*/ { 54, 1, 0x14, 585}, + /*(4250) VUNPCKLPD*/ { 40, 102, 0x14, 597}, + /*(4251) VUNPCKLPS*/ { 52, 0, 0x14, 121}, + /*(4252) VUNPCKLPS*/ { 53, 1, 0x14, 551}, + /*(4253) VUNPCKLPS*/ { 52, 0, 0x14, 121}, + /*(4254) VUNPCKLPS*/ { 53, 1, 0x14, 551}, + /*(4255) VUNPCKLPS*/ { 54, 1, 0x14, 601}, + /*(4256) VUNPCKLPS*/ { 40, 103, 0x14, 613}, + /*(4257) VUNPCKLPS*/ { 54, 1, 0x14, 601}, + /*(4258) VUNPCKLPS*/ { 40, 103, 0x14, 613}, + /*(4259) VUNPCKLPS*/ { 54, 1, 0x14, 601}, + /*(4260) VUNPCKLPS*/ { 40, 103, 0x14, 613}, + /*(4261) VXORPD*/ { 52, 0, 0x57, 141}, + /*(4262) VXORPD*/ { 53, 1, 0x57, 511}, + /*(4263) VXORPD*/ { 52, 0, 0x57, 141}, + /*(4264) VXORPD*/ { 53, 1, 0x57, 511}, + /*(4265) VXORPD*/ { 54, 1, 0x57, 585}, + /*(4266) VXORPD*/ { 40, 102, 0x57, 597}, + /*(4267) VXORPD*/ { 54, 1, 0x57, 585}, + /*(4268) VXORPD*/ { 40, 102, 0x57, 597}, + /*(4269) VXORPD*/ { 54, 1, 0x57, 585}, + /*(4270) VXORPD*/ { 40, 102, 0x57, 597}, + /*(4271) VXORPS*/ { 52, 0, 0x57, 121}, + /*(4272) VXORPS*/ { 53, 1, 0x57, 551}, + /*(4273) VXORPS*/ { 52, 0, 0x57, 121}, + /*(4274) VXORPS*/ { 53, 1, 0x57, 551}, + /*(4275) VXORPS*/ { 54, 1, 0x57, 601}, + /*(4276) VXORPS*/ { 40, 103, 0x57, 613}, + /*(4277) VXORPS*/ { 54, 1, 0x57, 601}, + /*(4278) VXORPS*/ { 40, 103, 0x57, 613}, + /*(4279) VXORPS*/ { 54, 1, 0x57, 601}, + /*(4280) VXORPS*/ { 40, 103, 0x57, 613}, + /*(4281) VMOVSS*/ { 44, 0, 0x10, 788}, + /*(4282) VMOVSS*/ { 53, 1, 0x10, 515}, + /*(4283) VMOVSS*/ { 44, 0, 0x11, 788}, + /*(4284) VMOVSS*/ { 53, 1, 0x11, 515}, + /*(4285) VMOVSS*/ { 80, 106, 0x10, 1130}, + /*(4286) VMOVSS*/ { 81, 106, 0x11, 1130}, + /*(4287) VMOVSS*/ { 54, 1, 0x10, 638}, + /*(4288) VMOVSS*/ { 54, 1, 0x11, 638}, + /*(4289) VMOVSD*/ { 44, 0, 0x10, 849}, + /*(4290) VMOVSD*/ { 53, 1, 0x10, 617}, + /*(4291) VMOVSD*/ { 44, 0, 0x11, 849}, + /*(4292) VMOVSD*/ { 53, 1, 0x11, 617}, + /*(4293) VMOVSD*/ { 80, 105, 0x10, 1692}, + /*(4294) VMOVSD*/ { 81, 105, 0x11, 1692}, + /*(4295) VMOVSD*/ { 54, 1, 0x10, 621}, + /*(4296) VMOVSD*/ { 54, 1, 0x11, 621}, + /*(4297) VMOVUPD*/ { 44, 0, 0x10, 702}, + /*(4298) VMOVUPD*/ { 45, 1, 0x10, 707}, + /*(4299) VMOVUPD*/ { 44, 0, 0x11, 702}, + /*(4300) VMOVUPD*/ { 45, 1, 0x11, 707}, + /*(4301) VMOVUPD*/ { 44, 0, 0x10, 702}, + /*(4302) VMOVUPD*/ { 45, 1, 0x10, 707}, + /*(4303) VMOVUPD*/ { 44, 0, 0x11, 702}, + /*(4304) VMOVUPD*/ { 45, 1, 0x11, 707}, + /*(4305) VMOVUPD*/ { 61, 1, 0x10, 885}, + /*(4306) VMOVUPD*/ { 80, 128, 0x10, 1571}, + /*(4307) VMOVUPD*/ { 61, 1, 0x11, 885}, + /*(4308) VMOVUPD*/ { 81, 128, 0x11, 1571}, + /*(4309) VMOVUPD*/ { 61, 1, 0x10, 885}, + /*(4310) VMOVUPD*/ { 80, 128, 0x10, 1571}, + /*(4311) VMOVUPD*/ { 61, 1, 0x11, 885}, + /*(4312) VMOVUPD*/ { 81, 128, 0x11, 1571}, + /*(4313) VMOVUPD*/ { 61, 1, 0x10, 885}, + /*(4314) VMOVUPD*/ { 80, 128, 0x10, 1571}, + /*(4315) VMOVUPD*/ { 61, 1, 0x11, 885}, + /*(4316) VMOVUPD*/ { 81, 128, 0x11, 1571}, + /*(4317) VMOVUPS*/ { 44, 0, 0x10, 745}, + /*(4318) VMOVUPS*/ { 45, 1, 0x10, 750}, + /*(4319) VMOVUPS*/ { 44, 0, 0x11, 745}, + /*(4320) VMOVUPS*/ { 45, 1, 0x11, 750}, + /*(4321) VMOVUPS*/ { 44, 0, 0x10, 745}, + /*(4322) VMOVUPS*/ { 45, 1, 0x10, 750}, + /*(4323) VMOVUPS*/ { 44, 0, 0x11, 745}, + /*(4324) VMOVUPS*/ { 45, 1, 0x11, 750}, + /*(4325) VMOVUPS*/ { 61, 1, 0x10, 824}, + /*(4326) VMOVUPS*/ { 80, 129, 0x10, 1588}, + /*(4327) VMOVUPS*/ { 61, 1, 0x11, 824}, + /*(4328) VMOVUPS*/ { 81, 129, 0x11, 1588}, + /*(4329) VMOVUPS*/ { 61, 1, 0x10, 824}, + /*(4330) VMOVUPS*/ { 80, 129, 0x10, 1588}, + /*(4331) VMOVUPS*/ { 61, 1, 0x11, 824}, + /*(4332) VMOVUPS*/ { 81, 129, 0x11, 1588}, + /*(4333) VMOVUPS*/ { 61, 1, 0x10, 824}, + /*(4334) VMOVUPS*/ { 80, 129, 0x10, 1588}, + /*(4335) VMOVUPS*/ { 61, 1, 0x11, 824}, + /*(4336) VMOVUPS*/ { 81, 129, 0x11, 1588}, + /*(4337) VMOVLPD*/ { 52, 0, 0x12, 141}, + /*(4338) VMOVLPD*/ { 44, 0, 0x13, 702}, + /*(4339) VMOVLPD*/ { 70, 105, 0x12, 1917}, + /*(4340) VMOVLPD*/ { 60, 105, 0x13, 735}, + /*(4341) VMOVLPS*/ { 52, 0, 0x12, 121}, + /*(4342) VMOVLPS*/ { 44, 0, 0x13, 745}, + /*(4343) VMOVLPS*/ { 70, 143, 0x12, 1924}, + /*(4344) VMOVLPS*/ { 60, 143, 0x13, 778}, + /*(4345) VMOVHPD*/ { 52, 0, 0x16, 141}, + /*(4346) VMOVHPD*/ { 44, 0, 0x17, 702}, + /*(4347) VMOVHPD*/ { 70, 105, 0x16, 1917}, + /*(4348) VMOVHPD*/ { 60, 105, 0x17, 735}, + /*(4349) VMOVHPS*/ { 52, 0, 0x16, 121}, + /*(4350) VMOVHPS*/ { 44, 0, 0x17, 745}, + /*(4351) VMOVHPS*/ { 70, 143, 0x16, 1924}, + /*(4352) VMOVHPS*/ { 60, 143, 0x17, 778}, + /*(4353) VMOVMSKPD*/ { 45, 1, 0x50, 707}, + /*(4354) VMOVMSKPD*/ { 45, 1, 0x50, 707}, + /*(4355) VMOVMSKPS*/ { 45, 1, 0x50, 750}, + /*(4356) VMOVMSKPS*/ { 45, 1, 0x50, 750}, + /*(4357) VPMOVMSKB*/ { 45, 1, 0xd7, 707}, + /*(4358) VPMOVMSKB*/ { 45, 1, 0xd7, 707}, + /*(4359) VPMOVSXBW*/ { 45, 1, 0x20, 1565}, + /*(4360) VPMOVSXBW*/ { 44, 0, 0x20, 1560}, + /*(4361) VPMOVSXBW*/ { 45, 1, 0x20, 1565}, + /*(4362) VPMOVSXBW*/ { 44, 0, 0x20, 1560}, + /*(4363) VPMOVSXBW*/ { 82, 1, 0x20, 1700}, + /*(4364) VPMOVSXBW*/ { 83, 144, 0x20, 1708}, + /*(4365) VPMOVSXBW*/ { 82, 1, 0x20, 1700}, + /*(4366) VPMOVSXBW*/ { 83, 144, 0x20, 1708}, + /*(4367) VPMOVSXBW*/ { 82, 1, 0x20, 1700}, + /*(4368) VPMOVSXBW*/ { 83, 144, 0x20, 1708}, + /*(4369) VPMOVSXBD*/ { 45, 1, 0x21, 1565}, + /*(4370) VPMOVSXBD*/ { 44, 0, 0x21, 1560}, + /*(4371) VPMOVSXBD*/ { 45, 1, 0x21, 1565}, + /*(4372) VPMOVSXBD*/ { 44, 0, 0x21, 1560}, + /*(4373) VPMOVSXBD*/ { 82, 1, 0x21, 1700}, + /*(4374) VPMOVSXBD*/ { 83, 145, 0x21, 1708}, + /*(4375) VPMOVSXBD*/ { 82, 1, 0x21, 1700}, + /*(4376) VPMOVSXBD*/ { 83, 145, 0x21, 1708}, + /*(4377) VPMOVSXBD*/ { 82, 1, 0x21, 1700}, + /*(4378) VPMOVSXBD*/ { 83, 145, 0x21, 1708}, + /*(4379) VPMOVSXBQ*/ { 45, 1, 0x22, 1565}, + /*(4380) VPMOVSXBQ*/ { 44, 0, 0x22, 1560}, + /*(4381) VPMOVSXBQ*/ { 45, 1, 0x22, 1565}, + /*(4382) VPMOVSXBQ*/ { 44, 0, 0x22, 1560}, + /*(4383) VPMOVSXBQ*/ { 82, 1, 0x22, 1700}, + /*(4384) VPMOVSXBQ*/ { 83, 146, 0x22, 1708}, + /*(4385) VPMOVSXBQ*/ { 82, 1, 0x22, 1700}, + /*(4386) VPMOVSXBQ*/ { 83, 146, 0x22, 1708}, + /*(4387) VPMOVSXBQ*/ { 82, 1, 0x22, 1700}, + /*(4388) VPMOVSXBQ*/ { 83, 146, 0x22, 1708}, + /*(4389) VPMOVSXWD*/ { 45, 1, 0x23, 1565}, + /*(4390) VPMOVSXWD*/ { 44, 0, 0x23, 1560}, + /*(4391) VPMOVSXWD*/ { 45, 1, 0x23, 1565}, + /*(4392) VPMOVSXWD*/ { 44, 0, 0x23, 1560}, + /*(4393) VPMOVSXWD*/ { 82, 1, 0x23, 1700}, + /*(4394) VPMOVSXWD*/ { 83, 147, 0x23, 1708}, + /*(4395) VPMOVSXWD*/ { 82, 1, 0x23, 1700}, + /*(4396) VPMOVSXWD*/ { 83, 147, 0x23, 1708}, + /*(4397) VPMOVSXWD*/ { 82, 1, 0x23, 1700}, + /*(4398) VPMOVSXWD*/ { 83, 147, 0x23, 1708}, + /*(4399) VPMOVSXWQ*/ { 45, 1, 0x24, 1565}, + /*(4400) VPMOVSXWQ*/ { 44, 0, 0x24, 1560}, + /*(4401) VPMOVSXWQ*/ { 45, 1, 0x24, 1565}, + /*(4402) VPMOVSXWQ*/ { 44, 0, 0x24, 1560}, + /*(4403) VPMOVSXWQ*/ { 82, 1, 0x24, 1700}, + /*(4404) VPMOVSXWQ*/ { 83, 148, 0x24, 1708}, + /*(4405) VPMOVSXWQ*/ { 82, 1, 0x24, 1700}, + /*(4406) VPMOVSXWQ*/ { 83, 148, 0x24, 1708}, + /*(4407) VPMOVSXWQ*/ { 82, 1, 0x24, 1700}, + /*(4408) VPMOVSXWQ*/ { 83, 148, 0x24, 1708}, + /*(4409) VPMOVSXDQ*/ { 45, 1, 0x25, 1565}, + /*(4410) VPMOVSXDQ*/ { 44, 0, 0x25, 1560}, + /*(4411) VPMOVSXDQ*/ { 45, 1, 0x25, 1565}, + /*(4412) VPMOVSXDQ*/ { 44, 0, 0x25, 1560}, + /*(4413) VPMOVSXDQ*/ { 61, 1, 0x25, 1427}, + /*(4414) VPMOVSXDQ*/ { 80, 149, 0x25, 1418}, + /*(4415) VPMOVSXDQ*/ { 61, 1, 0x25, 1427}, + /*(4416) VPMOVSXDQ*/ { 80, 149, 0x25, 1418}, + /*(4417) VPMOVSXDQ*/ { 61, 1, 0x25, 1427}, + /*(4418) VPMOVSXDQ*/ { 80, 149, 0x25, 1418}, + /*(4419) VPMOVZXBW*/ { 45, 1, 0x30, 1565}, + /*(4420) VPMOVZXBW*/ { 44, 0, 0x30, 1560}, + /*(4421) VPMOVZXBW*/ { 45, 1, 0x30, 1565}, + /*(4422) VPMOVZXBW*/ { 44, 0, 0x30, 1560}, + /*(4423) VPMOVZXBW*/ { 82, 1, 0x30, 1700}, + /*(4424) VPMOVZXBW*/ { 83, 144, 0x30, 1708}, + /*(4425) VPMOVZXBW*/ { 82, 1, 0x30, 1700}, + /*(4426) VPMOVZXBW*/ { 83, 144, 0x30, 1708}, + /*(4427) VPMOVZXBW*/ { 82, 1, 0x30, 1700}, + /*(4428) VPMOVZXBW*/ { 83, 144, 0x30, 1708}, + /*(4429) VPMOVZXBD*/ { 45, 1, 0x31, 1565}, + /*(4430) VPMOVZXBD*/ { 44, 0, 0x31, 1560}, + /*(4431) VPMOVZXBD*/ { 45, 1, 0x31, 1565}, + /*(4432) VPMOVZXBD*/ { 44, 0, 0x31, 1560}, + /*(4433) VPMOVZXBD*/ { 82, 1, 0x31, 1700}, + /*(4434) VPMOVZXBD*/ { 83, 145, 0x31, 1708}, + /*(4435) VPMOVZXBD*/ { 82, 1, 0x31, 1700}, + /*(4436) VPMOVZXBD*/ { 83, 145, 0x31, 1708}, + /*(4437) VPMOVZXBD*/ { 82, 1, 0x31, 1700}, + /*(4438) VPMOVZXBD*/ { 83, 145, 0x31, 1708}, + /*(4439) VPMOVZXBQ*/ { 45, 1, 0x32, 1565}, + /*(4440) VPMOVZXBQ*/ { 44, 0, 0x32, 1560}, + /*(4441) VPMOVZXBQ*/ { 45, 1, 0x32, 1565}, + /*(4442) VPMOVZXBQ*/ { 44, 0, 0x32, 1560}, + /*(4443) VPMOVZXBQ*/ { 82, 1, 0x32, 1700}, + /*(4444) VPMOVZXBQ*/ { 83, 146, 0x32, 1708}, + /*(4445) VPMOVZXBQ*/ { 82, 1, 0x32, 1700}, + /*(4446) VPMOVZXBQ*/ { 83, 146, 0x32, 1708}, + /*(4447) VPMOVZXBQ*/ { 82, 1, 0x32, 1700}, + /*(4448) VPMOVZXBQ*/ { 83, 146, 0x32, 1708}, + /*(4449) VPMOVZXWD*/ { 45, 1, 0x33, 1565}, + /*(4450) VPMOVZXWD*/ { 44, 0, 0x33, 1560}, + /*(4451) VPMOVZXWD*/ { 45, 1, 0x33, 1565}, + /*(4452) VPMOVZXWD*/ { 44, 0, 0x33, 1560}, + /*(4453) VPMOVZXWD*/ { 82, 1, 0x33, 1700}, + /*(4454) VPMOVZXWD*/ { 83, 147, 0x33, 1708}, + /*(4455) VPMOVZXWD*/ { 82, 1, 0x33, 1700}, + /*(4456) VPMOVZXWD*/ { 83, 147, 0x33, 1708}, + /*(4457) VPMOVZXWD*/ { 82, 1, 0x33, 1700}, + /*(4458) VPMOVZXWD*/ { 83, 147, 0x33, 1708}, + /*(4459) VPMOVZXWQ*/ { 45, 1, 0x34, 1565}, + /*(4460) VPMOVZXWQ*/ { 44, 0, 0x34, 1560}, + /*(4461) VPMOVZXWQ*/ { 45, 1, 0x34, 1565}, + /*(4462) VPMOVZXWQ*/ { 44, 0, 0x34, 1560}, + /*(4463) VPMOVZXWQ*/ { 82, 1, 0x34, 1700}, + /*(4464) VPMOVZXWQ*/ { 83, 148, 0x34, 1708}, + /*(4465) VPMOVZXWQ*/ { 82, 1, 0x34, 1700}, + /*(4466) VPMOVZXWQ*/ { 83, 148, 0x34, 1708}, + /*(4467) VPMOVZXWQ*/ { 82, 1, 0x34, 1700}, + /*(4468) VPMOVZXWQ*/ { 83, 148, 0x34, 1708}, + /*(4469) VPMOVZXDQ*/ { 45, 1, 0x35, 1565}, + /*(4470) VPMOVZXDQ*/ { 44, 0, 0x35, 1560}, + /*(4471) VPMOVZXDQ*/ { 45, 1, 0x35, 1565}, + /*(4472) VPMOVZXDQ*/ { 44, 0, 0x35, 1560}, + /*(4473) VPMOVZXDQ*/ { 61, 1, 0x35, 1427}, + /*(4474) VPMOVZXDQ*/ { 80, 149, 0x35, 1418}, + /*(4475) VPMOVZXDQ*/ { 61, 1, 0x35, 1427}, + /*(4476) VPMOVZXDQ*/ { 80, 149, 0x35, 1418}, + /*(4477) VPMOVZXDQ*/ { 61, 1, 0x35, 1427}, + /*(4478) VPMOVZXDQ*/ { 80, 149, 0x35, 1418}, + /*(4479) VPEXTRB*/ { 44, 9, 0x14, 708}, + /*(4480) VPEXTRB*/ { 45, 10, 0x14, 1317}, + /*(4481) VPEXTRB*/ { 63, 10, 0x14, 1323}, + /*(4482) VPEXTRB*/ { 65, 150, 0x14, 1333}, + /*(4483) VPEXTRW*/ { 44, 9, 0x15, 708}, + /*(4484) VPEXTRW*/ { 45, 10, 0x15, 1317}, + /*(4485) VPEXTRW*/ { 45, 10, 0xc5, 707}, + /*(4486) VPEXTRW*/ { 63, 10, 0x15, 1323}, + /*(4487) VPEXTRW*/ { 65, 151, 0x15, 1333}, + /*(4488) VPEXTRQ*/ { 42, 9, 0x16, 1665}, + /*(4489) VPEXTRQ*/ { 43, 10, 0x16, 1931}, + /*(4490) VPEXTRQ*/ { 59, 10, 0x16, 1938}, + /*(4491) VPEXTRQ*/ { 60, 152, 0x16, 1949}, + /*(4492) VPEXTRD*/ { 42, 9, 0x16, 1304}, + /*(4493) VPEXTRD*/ { 43, 10, 0x16, 1310}, + /*(4494) VPEXTRD*/ { 44, 9, 0x16, 708}, + /*(4495) VPEXTRD*/ { 45, 10, 0x16, 1317}, + /*(4496) VPEXTRD*/ { 63, 10, 0x16, 1323}, + /*(4497) VPEXTRD*/ { 59, 10, 0x16, 1959}, + /*(4498) VPEXTRD*/ { 65, 124, 0x16, 1333}, + /*(4499) VPEXTRD*/ { 60, 124, 0x16, 1970}, + /*(4500) VPINSRB*/ { 52, 9, 0x20, 119}, + /*(4501) VPINSRB*/ { 53, 10, 0x20, 118}, + /*(4502) VPINSRB*/ { 72, 10, 0x20, 1980}, + /*(4503) VPINSRB*/ { 69, 153, 0x20, 1547}, + /*(4504) VPINSRW*/ { 52, 9, 0xc4, 141}, + /*(4505) VPINSRW*/ { 53, 10, 0xc4, 511}, + /*(4506) VPINSRW*/ { 72, 10, 0xc4, 1873}, + /*(4507) VPINSRW*/ { 69, 154, 0xc4, 1880}, + /*(4508) VPINSRD*/ { 40, 9, 0x22, 508}, + /*(4509) VPINSRD*/ { 41, 10, 0x22, 507}, + /*(4510) VPINSRD*/ { 52, 9, 0x22, 119}, + /*(4511) VPINSRD*/ { 53, 10, 0x22, 118}, + /*(4512) VPINSRD*/ { 72, 10, 0x22, 1980}, + /*(4513) VPINSRD*/ { 71, 10, 0x22, 1545}, + /*(4514) VPINSRD*/ { 69, 155, 0x22, 1547}, + /*(4515) VPINSRD*/ { 70, 155, 0x22, 1553}, + /*(4516) VPINSRQ*/ { 40, 9, 0x22, 512}, + /*(4517) VPINSRQ*/ { 41, 10, 0x22, 516}, + /*(4518) VPINSRQ*/ { 71, 10, 0x22, 1987}, + /*(4519) VPINSRQ*/ { 70, 156, 0x22, 1995}, + /*(4520) VPCMPESTRI*/ { 44, 9, 0x61, 708}, + /*(4521) VPCMPESTRI*/ { 45, 10, 0x61, 1317}, + /*(4522) VPCMPESTRI*/ { 42, 9, 0x61, 1304}, + /*(4523) VPCMPESTRI*/ { 43, 10, 0x61, 1310}, + /*(4524) VPCMPESTRI64*/ { 42, 9, 0x61, 1665}, + /*(4525) VPCMPESTRI64*/ { 43, 10, 0x61, 1931}, + /*(4526) VPCMPISTRI*/ { 44, 9, 0x63, 708}, + /*(4527) VPCMPISTRI*/ { 45, 10, 0x63, 1317}, + /*(4528) VPCMPISTRI*/ { 42, 9, 0x63, 1304}, + /*(4529) VPCMPISTRI*/ { 43, 10, 0x63, 1310}, + /*(4530) VPCMPISTRI64*/ { 42, 9, 0x63, 1665}, + /*(4531) VPCMPISTRI64*/ { 43, 10, 0x63, 1931}, + /*(4532) VPCMPESTRM*/ { 44, 9, 0x60, 708}, + /*(4533) VPCMPESTRM*/ { 45, 10, 0x60, 1317}, + /*(4534) VPCMPESTRM*/ { 42, 9, 0x60, 1304}, + /*(4535) VPCMPESTRM*/ { 43, 10, 0x60, 1310}, + /*(4536) VPCMPESTRM64*/ { 42, 9, 0x60, 1665}, + /*(4537) VPCMPESTRM64*/ { 43, 10, 0x60, 1931}, + /*(4538) VPCMPISTRM*/ { 44, 9, 0x62, 708}, + /*(4539) VPCMPISTRM*/ { 45, 10, 0x62, 1317}, + /*(4540) VMASKMOVDQU*/ { 45, 1, 0xf7, 707}, + /*(4541) VLDMXCSR*/ { 94, 0, 0xae, 2002}, + /*(4542) VSTMXCSR*/ { 94, 0, 0xae, 750}, + /*(4543) VPBLENDVB*/ { 40, 96, 0x4c, 508}, + /*(4544) VPBLENDVB*/ { 41, 97, 0x4c, 507}, + /*(4545) VPBLENDVB*/ { 40, 96, 0x4c, 508}, + /*(4546) VPBLENDVB*/ { 41, 97, 0x4c, 507}, + /*(4547) VBLENDVPD*/ { 40, 96, 0x4b, 508}, + /*(4548) VBLENDVPD*/ { 41, 97, 0x4b, 507}, + /*(4549) VBLENDVPD*/ { 40, 96, 0x4b, 508}, + /*(4550) VBLENDVPD*/ { 41, 97, 0x4b, 507}, + /*(4551) VBLENDVPS*/ { 40, 96, 0x4a, 508}, + /*(4552) VBLENDVPS*/ { 41, 97, 0x4a, 507}, + /*(4553) VBLENDVPS*/ { 40, 96, 0x4a, 508}, + /*(4554) VBLENDVPS*/ { 41, 97, 0x4a, 507}, + /*(4555) VMOVNTDQA*/ { 44, 0, 0x2a, 1560}, + /*(4556) VMOVNTDQA*/ { 44, 0, 0x2a, 1560}, + /*(4557) VMOVNTDQA*/ { 60, 129, 0x2a, 2009}, + /*(4558) VMOVNTDQA*/ { 60, 129, 0x2a, 2009}, + /*(4559) VMOVNTDQA*/ { 60, 129, 0x2a, 2009}, + /*(4560) VMOVNTDQ*/ { 44, 0, 0xe7, 702}, + /*(4561) VMOVNTDQ*/ { 44, 0, 0xe7, 702}, + /*(4562) VMOVNTDQ*/ { 60, 129, 0xe7, 1648}, + /*(4563) VMOVNTDQ*/ { 60, 129, 0xe7, 1648}, + /*(4564) VMOVNTDQ*/ { 60, 129, 0xe7, 1648}, + /*(4565) VMOVNTPD*/ { 44, 0, 0x2b, 702}, + /*(4566) VMOVNTPD*/ { 44, 0, 0x2b, 702}, + /*(4567) VMOVNTPD*/ { 60, 128, 0x2b, 735}, + /*(4568) VMOVNTPD*/ { 60, 128, 0x2b, 735}, + /*(4569) VMOVNTPD*/ { 60, 128, 0x2b, 735}, + /*(4570) VMOVNTPS*/ { 44, 0, 0x2b, 745}, + /*(4571) VMOVNTPS*/ { 44, 0, 0x2b, 745}, + /*(4572) VMOVNTPS*/ { 60, 129, 0x2b, 778}, + /*(4573) VMOVNTPS*/ { 60, 129, 0x2b, 778}, + /*(4574) VMOVNTPS*/ { 60, 129, 0x2b, 778}, + /*(4575) VAESKEYGENASSIST*/ { 45, 10, 0xdf, 1317}, + /*(4576) VAESKEYGENASSIST*/ { 44, 9, 0xdf, 708}, + /*(4577) VAESENC*/ { 53, 1, 0xdc, 1363}, + /*(4578) VAESENC*/ { 52, 0, 0xdc, 590}, + /*(4579) VAESENC*/ { 72, 1, 0xdc, 145}, + /*(4580) VAESENC*/ { 69, 157, 0xdc, 2019}, + /*(4581) VAESENC*/ { 72, 1, 0xdc, 145}, + /*(4582) VAESENC*/ { 69, 157, 0xdc, 2019}, + /*(4583) VAESENC*/ { 72, 1, 0xdc, 145}, + /*(4584) VAESENC*/ { 69, 157, 0xdc, 2019}, + /*(4585) VAESENC*/ { 53, 1, 0xdc, 1363}, + /*(4586) VAESENC*/ { 52, 0, 0xdc, 590}, + /*(4587) VAESENCLAST*/ { 53, 1, 0xdd, 1363}, + /*(4588) VAESENCLAST*/ { 52, 0, 0xdd, 590}, + /*(4589) VAESENCLAST*/ { 72, 1, 0xdd, 145}, + /*(4590) VAESENCLAST*/ { 69, 157, 0xdd, 2019}, + /*(4591) VAESENCLAST*/ { 72, 1, 0xdd, 145}, + /*(4592) VAESENCLAST*/ { 69, 157, 0xdd, 2019}, + /*(4593) VAESENCLAST*/ { 72, 1, 0xdd, 145}, + /*(4594) VAESENCLAST*/ { 69, 157, 0xdd, 2019}, + /*(4595) VAESENCLAST*/ { 53, 1, 0xdd, 1363}, + /*(4596) VAESENCLAST*/ { 52, 0, 0xdd, 590}, + /*(4597) VAESDEC*/ { 53, 1, 0xde, 1363}, + /*(4598) VAESDEC*/ { 52, 0, 0xde, 590}, + /*(4599) VAESDEC*/ { 72, 1, 0xde, 145}, + /*(4600) VAESDEC*/ { 69, 157, 0xde, 2019}, + /*(4601) VAESDEC*/ { 72, 1, 0xde, 145}, + /*(4602) VAESDEC*/ { 69, 157, 0xde, 2019}, + /*(4603) VAESDEC*/ { 72, 1, 0xde, 145}, + /*(4604) VAESDEC*/ { 69, 157, 0xde, 2019}, + /*(4605) VAESDEC*/ { 53, 1, 0xde, 1363}, + /*(4606) VAESDEC*/ { 52, 0, 0xde, 590}, + /*(4607) VAESDECLAST*/ { 53, 1, 0xdf, 1363}, + /*(4608) VAESDECLAST*/ { 52, 0, 0xdf, 590}, + /*(4609) VAESDECLAST*/ { 72, 1, 0xdf, 145}, + /*(4610) VAESDECLAST*/ { 69, 157, 0xdf, 2019}, + /*(4611) VAESDECLAST*/ { 72, 1, 0xdf, 145}, + /*(4612) VAESDECLAST*/ { 69, 157, 0xdf, 2019}, + /*(4613) VAESDECLAST*/ { 72, 1, 0xdf, 145}, + /*(4614) VAESDECLAST*/ { 69, 157, 0xdf, 2019}, + /*(4615) VAESDECLAST*/ { 53, 1, 0xdf, 1363}, + /*(4616) VAESDECLAST*/ { 52, 0, 0xdf, 590}, + /*(4617) VAESIMC*/ { 45, 1, 0xdb, 1565}, + /*(4618) VAESIMC*/ { 44, 0, 0xdb, 1560}, + /*(4619) VPCLMULQDQ*/ { 53, 10, 0x44, 118}, + /*(4620) VPCLMULQDQ*/ { 52, 9, 0x44, 119}, + /*(4621) VPCLMULQDQ*/ { 72, 10, 0x44, 1980}, + /*(4622) VPCLMULQDQ*/ { 69, 142, 0x44, 1547}, + /*(4623) VPCLMULQDQ*/ { 72, 10, 0x44, 1980}, + /*(4624) VPCLMULQDQ*/ { 69, 142, 0x44, 1547}, + /*(4625) VPCLMULQDQ*/ { 72, 10, 0x44, 1980}, + /*(4626) VPCLMULQDQ*/ { 69, 142, 0x44, 1547}, + /*(4627) VPCLMULQDQ*/ { 53, 10, 0x44, 118}, + /*(4628) VPCLMULQDQ*/ { 52, 9, 0x44, 119}, + /*(4629) VCVTPH2PS*/ { 42, 0, 0x13, 1388}, + /*(4630) VCVTPH2PS*/ { 43, 1, 0x13, 1402}, + /*(4631) VCVTPH2PS*/ { 42, 0, 0x13, 1388}, + /*(4632) VCVTPH2PS*/ { 43, 1, 0x13, 1402}, + /*(4633) VCVTPH2PS*/ { 61, 1, 0x13, 1427}, + /*(4634) VCVTPH2PS*/ { 61, 119, 0x13, 2025}, + /*(4635) VCVTPH2PS*/ { 80, 147, 0x13, 1418}, + /*(4636) VCVTPH2PS*/ { 61, 1, 0x13, 1427}, + /*(4637) VCVTPH2PS*/ { 80, 147, 0x13, 1418}, + /*(4638) VCVTPH2PS*/ { 61, 1, 0x13, 1427}, + /*(4639) VCVTPH2PS*/ { 80, 147, 0x13, 1418}, + /*(4640) VCVTPS2PH*/ { 42, 9, 0x1d, 1304}, + /*(4641) VCVTPS2PH*/ { 43, 10, 0x1d, 1310}, + /*(4642) VCVTPS2PH*/ { 42, 9, 0x1d, 1304}, + /*(4643) VCVTPS2PH*/ { 43, 10, 0x1d, 1310}, + /*(4644) VCVTPS2PH*/ { 61, 10, 0x1d, 1368}, + /*(4645) VCVTPS2PH*/ { 61, 107, 0x1d, 2034}, + /*(4646) VCVTPS2PH*/ { 81, 158, 0x1d, 1333}, + /*(4647) VCVTPS2PH*/ { 61, 10, 0x1d, 1368}, + /*(4648) VCVTPS2PH*/ { 81, 158, 0x1d, 1333}, + /*(4649) VCVTPS2PH*/ { 61, 10, 0x1d, 1368}, + /*(4650) VCVTPS2PH*/ { 81, 158, 0x1d, 1333}, + /*(4651) VFMADD132PD*/ { 40, 0, 0x98, 596}, + /*(4652) VFMADD132PD*/ { 41, 1, 0x98, 2043}, + /*(4653) VFMADD132PD*/ { 40, 0, 0x98, 596}, + /*(4654) VFMADD132PD*/ { 41, 1, 0x98, 2043}, + /*(4655) VFMADD132PD*/ { 54, 1, 0x98, 1362}, + /*(4656) VFMADD132PD*/ { 54, 101, 0x98, 2048}, + /*(4657) VFMADD132PD*/ { 40, 102, 0x98, 877}, + /*(4658) VFMADD132PD*/ { 54, 1, 0x98, 1362}, + /*(4659) VFMADD132PD*/ { 40, 102, 0x98, 877}, + /*(4660) VFMADD132PD*/ { 54, 1, 0x98, 1362}, + /*(4661) VFMADD132PD*/ { 40, 102, 0x98, 877}, + /*(4662) VFMADD132PS*/ { 40, 0, 0x98, 632}, + /*(4663) VFMADD132PS*/ { 41, 1, 0x98, 1348}, + /*(4664) VFMADD132PS*/ { 40, 0, 0x98, 632}, + /*(4665) VFMADD132PS*/ { 41, 1, 0x98, 1348}, + /*(4666) VFMADD132PS*/ { 54, 1, 0x98, 1377}, + /*(4667) VFMADD132PS*/ { 54, 101, 0x98, 2054}, + /*(4668) VFMADD132PS*/ { 40, 103, 0x98, 1383}, + /*(4669) VFMADD132PS*/ { 54, 1, 0x98, 1377}, + /*(4670) VFMADD132PS*/ { 40, 103, 0x98, 1383}, + /*(4671) VFMADD132PS*/ { 54, 1, 0x98, 1377}, + /*(4672) VFMADD132PS*/ { 40, 103, 0x98, 1383}, + /*(4673) VFMADD132SD*/ { 40, 0, 0x99, 596}, + /*(4674) VFMADD132SD*/ { 41, 1, 0x99, 2043}, + /*(4675) VFMADD132SD*/ { 54, 1, 0x99, 1362}, + /*(4676) VFMADD132SD*/ { 54, 104, 0x99, 2048}, + /*(4677) VFMADD132SD*/ { 55, 105, 0x99, 876}, + /*(4678) VFMADD132SS*/ { 40, 0, 0x99, 632}, + /*(4679) VFMADD132SS*/ { 41, 1, 0x99, 1348}, + /*(4680) VFMADD132SS*/ { 54, 1, 0x99, 1377}, + /*(4681) VFMADD132SS*/ { 54, 104, 0x99, 2054}, + /*(4682) VFMADD132SS*/ { 55, 106, 0x99, 2019}, + /*(4683) VFMADD213PD*/ { 40, 0, 0xa8, 596}, + /*(4684) VFMADD213PD*/ { 41, 1, 0xa8, 2043}, + /*(4685) VFMADD213PD*/ { 40, 0, 0xa8, 596}, + /*(4686) VFMADD213PD*/ { 41, 1, 0xa8, 2043}, + /*(4687) VFMADD213PD*/ { 54, 1, 0xa8, 1362}, + /*(4688) VFMADD213PD*/ { 54, 101, 0xa8, 2048}, + /*(4689) VFMADD213PD*/ { 40, 102, 0xa8, 877}, + /*(4690) VFMADD213PD*/ { 54, 1, 0xa8, 1362}, + /*(4691) VFMADD213PD*/ { 40, 102, 0xa8, 877}, + /*(4692) VFMADD213PD*/ { 54, 1, 0xa8, 1362}, + /*(4693) VFMADD213PD*/ { 40, 102, 0xa8, 877}, + /*(4694) VFMADD213PS*/ { 40, 0, 0xa8, 632}, + /*(4695) VFMADD213PS*/ { 41, 1, 0xa8, 1348}, + /*(4696) VFMADD213PS*/ { 40, 0, 0xa8, 632}, + /*(4697) VFMADD213PS*/ { 41, 1, 0xa8, 1348}, + /*(4698) VFMADD213PS*/ { 54, 1, 0xa8, 1377}, + /*(4699) VFMADD213PS*/ { 54, 101, 0xa8, 2054}, + /*(4700) VFMADD213PS*/ { 40, 103, 0xa8, 1383}, + /*(4701) VFMADD213PS*/ { 54, 1, 0xa8, 1377}, + /*(4702) VFMADD213PS*/ { 40, 103, 0xa8, 1383}, + /*(4703) VFMADD213PS*/ { 54, 1, 0xa8, 1377}, + /*(4704) VFMADD213PS*/ { 40, 103, 0xa8, 1383}, + /*(4705) VFMADD213SD*/ { 40, 0, 0xa9, 596}, + /*(4706) VFMADD213SD*/ { 41, 1, 0xa9, 2043}, + /*(4707) VFMADD213SD*/ { 54, 1, 0xa9, 1362}, + /*(4708) VFMADD213SD*/ { 54, 104, 0xa9, 2048}, + /*(4709) VFMADD213SD*/ { 55, 105, 0xa9, 876}, + /*(4710) VFMADD213SS*/ { 40, 0, 0xa9, 632}, + /*(4711) VFMADD213SS*/ { 41, 1, 0xa9, 1348}, + /*(4712) VFMADD213SS*/ { 54, 1, 0xa9, 1377}, + /*(4713) VFMADD213SS*/ { 54, 104, 0xa9, 2054}, + /*(4714) VFMADD213SS*/ { 55, 106, 0xa9, 2019}, + /*(4715) VFMADD231PD*/ { 40, 0, 0xb8, 596}, + /*(4716) VFMADD231PD*/ { 41, 1, 0xb8, 2043}, + /*(4717) VFMADD231PD*/ { 40, 0, 0xb8, 596}, + /*(4718) VFMADD231PD*/ { 41, 1, 0xb8, 2043}, + /*(4719) VFMADD231PD*/ { 54, 1, 0xb8, 1362}, + /*(4720) VFMADD231PD*/ { 54, 101, 0xb8, 2048}, + /*(4721) VFMADD231PD*/ { 40, 102, 0xb8, 877}, + /*(4722) VFMADD231PD*/ { 54, 1, 0xb8, 1362}, + /*(4723) VFMADD231PD*/ { 40, 102, 0xb8, 877}, + /*(4724) VFMADD231PD*/ { 54, 1, 0xb8, 1362}, + /*(4725) VFMADD231PD*/ { 40, 102, 0xb8, 877}, + /*(4726) VFMADD231PS*/ { 40, 0, 0xb8, 632}, + /*(4727) VFMADD231PS*/ { 41, 1, 0xb8, 1348}, + /*(4728) VFMADD231PS*/ { 40, 0, 0xb8, 632}, + /*(4729) VFMADD231PS*/ { 41, 1, 0xb8, 1348}, + /*(4730) VFMADD231PS*/ { 54, 1, 0xb8, 1377}, + /*(4731) VFMADD231PS*/ { 54, 101, 0xb8, 2054}, + /*(4732) VFMADD231PS*/ { 40, 103, 0xb8, 1383}, + /*(4733) VFMADD231PS*/ { 54, 1, 0xb8, 1377}, + /*(4734) VFMADD231PS*/ { 40, 103, 0xb8, 1383}, + /*(4735) VFMADD231PS*/ { 54, 1, 0xb8, 1377}, + /*(4736) VFMADD231PS*/ { 40, 103, 0xb8, 1383}, + /*(4737) VFMADD231SD*/ { 40, 0, 0xb9, 596}, + /*(4738) VFMADD231SD*/ { 41, 1, 0xb9, 2043}, + /*(4739) VFMADD231SD*/ { 54, 1, 0xb9, 1362}, + /*(4740) VFMADD231SD*/ { 54, 104, 0xb9, 2048}, + /*(4741) VFMADD231SD*/ { 55, 105, 0xb9, 876}, + /*(4742) VFMADD231SS*/ { 40, 0, 0xb9, 632}, + /*(4743) VFMADD231SS*/ { 41, 1, 0xb9, 1348}, + /*(4744) VFMADD231SS*/ { 54, 1, 0xb9, 1377}, + /*(4745) VFMADD231SS*/ { 54, 104, 0xb9, 2054}, + /*(4746) VFMADD231SS*/ { 55, 106, 0xb9, 2019}, + /*(4747) VFMADDSUB132PD*/ { 40, 0, 0x96, 596}, + /*(4748) VFMADDSUB132PD*/ { 41, 1, 0x96, 2043}, + /*(4749) VFMADDSUB132PD*/ { 40, 0, 0x96, 596}, + /*(4750) VFMADDSUB132PD*/ { 41, 1, 0x96, 2043}, + /*(4751) VFMADDSUB132PD*/ { 54, 1, 0x96, 1362}, + /*(4752) VFMADDSUB132PD*/ { 54, 101, 0x96, 2048}, + /*(4753) VFMADDSUB132PD*/ { 40, 102, 0x96, 877}, + /*(4754) VFMADDSUB132PD*/ { 54, 1, 0x96, 1362}, + /*(4755) VFMADDSUB132PD*/ { 40, 102, 0x96, 877}, + /*(4756) VFMADDSUB132PD*/ { 54, 1, 0x96, 1362}, + /*(4757) VFMADDSUB132PD*/ { 40, 102, 0x96, 877}, + /*(4758) VFMADDSUB213PD*/ { 40, 0, 0xa6, 596}, + /*(4759) VFMADDSUB213PD*/ { 41, 1, 0xa6, 2043}, + /*(4760) VFMADDSUB213PD*/ { 40, 0, 0xa6, 596}, + /*(4761) VFMADDSUB213PD*/ { 41, 1, 0xa6, 2043}, + /*(4762) VFMADDSUB213PD*/ { 54, 1, 0xa6, 1362}, + /*(4763) VFMADDSUB213PD*/ { 54, 101, 0xa6, 2048}, + /*(4764) VFMADDSUB213PD*/ { 40, 102, 0xa6, 877}, + /*(4765) VFMADDSUB213PD*/ { 54, 1, 0xa6, 1362}, + /*(4766) VFMADDSUB213PD*/ { 40, 102, 0xa6, 877}, + /*(4767) VFMADDSUB213PD*/ { 54, 1, 0xa6, 1362}, + /*(4768) VFMADDSUB213PD*/ { 40, 102, 0xa6, 877}, + /*(4769) VFMADDSUB231PD*/ { 40, 0, 0xb6, 596}, + /*(4770) VFMADDSUB231PD*/ { 41, 1, 0xb6, 2043}, + /*(4771) VFMADDSUB231PD*/ { 40, 0, 0xb6, 596}, + /*(4772) VFMADDSUB231PD*/ { 41, 1, 0xb6, 2043}, + /*(4773) VFMADDSUB231PD*/ { 54, 1, 0xb6, 1362}, + /*(4774) VFMADDSUB231PD*/ { 54, 101, 0xb6, 2048}, + /*(4775) VFMADDSUB231PD*/ { 40, 102, 0xb6, 877}, + /*(4776) VFMADDSUB231PD*/ { 54, 1, 0xb6, 1362}, + /*(4777) VFMADDSUB231PD*/ { 40, 102, 0xb6, 877}, + /*(4778) VFMADDSUB231PD*/ { 54, 1, 0xb6, 1362}, + /*(4779) VFMADDSUB231PD*/ { 40, 102, 0xb6, 877}, + /*(4780) VFMADDSUB132PS*/ { 40, 0, 0x96, 632}, + /*(4781) VFMADDSUB132PS*/ { 41, 1, 0x96, 1348}, + /*(4782) VFMADDSUB132PS*/ { 40, 0, 0x96, 632}, + /*(4783) VFMADDSUB132PS*/ { 41, 1, 0x96, 1348}, + /*(4784) VFMADDSUB132PS*/ { 54, 1, 0x96, 1377}, + /*(4785) VFMADDSUB132PS*/ { 54, 101, 0x96, 2054}, + /*(4786) VFMADDSUB132PS*/ { 40, 103, 0x96, 1383}, + /*(4787) VFMADDSUB132PS*/ { 54, 1, 0x96, 1377}, + /*(4788) VFMADDSUB132PS*/ { 40, 103, 0x96, 1383}, + /*(4789) VFMADDSUB132PS*/ { 54, 1, 0x96, 1377}, + /*(4790) VFMADDSUB132PS*/ { 40, 103, 0x96, 1383}, + /*(4791) VFMADDSUB213PS*/ { 40, 0, 0xa6, 632}, + /*(4792) VFMADDSUB213PS*/ { 41, 1, 0xa6, 1348}, + /*(4793) VFMADDSUB213PS*/ { 40, 0, 0xa6, 632}, + /*(4794) VFMADDSUB213PS*/ { 41, 1, 0xa6, 1348}, + /*(4795) VFMADDSUB213PS*/ { 54, 1, 0xa6, 1377}, + /*(4796) VFMADDSUB213PS*/ { 54, 101, 0xa6, 2054}, + /*(4797) VFMADDSUB213PS*/ { 40, 103, 0xa6, 1383}, + /*(4798) VFMADDSUB213PS*/ { 54, 1, 0xa6, 1377}, + /*(4799) VFMADDSUB213PS*/ { 40, 103, 0xa6, 1383}, + /*(4800) VFMADDSUB213PS*/ { 54, 1, 0xa6, 1377}, + /*(4801) VFMADDSUB213PS*/ { 40, 103, 0xa6, 1383}, + /*(4802) VFMADDSUB231PS*/ { 40, 0, 0xb6, 632}, + /*(4803) VFMADDSUB231PS*/ { 41, 1, 0xb6, 1348}, + /*(4804) VFMADDSUB231PS*/ { 40, 0, 0xb6, 632}, + /*(4805) VFMADDSUB231PS*/ { 41, 1, 0xb6, 1348}, + /*(4806) VFMADDSUB231PS*/ { 54, 1, 0xb6, 1377}, + /*(4807) VFMADDSUB231PS*/ { 54, 101, 0xb6, 2054}, + /*(4808) VFMADDSUB231PS*/ { 40, 103, 0xb6, 1383}, + /*(4809) VFMADDSUB231PS*/ { 54, 1, 0xb6, 1377}, + /*(4810) VFMADDSUB231PS*/ { 40, 103, 0xb6, 1383}, + /*(4811) VFMADDSUB231PS*/ { 54, 1, 0xb6, 1377}, + /*(4812) VFMADDSUB231PS*/ { 40, 103, 0xb6, 1383}, + /*(4813) VFMSUBADD132PD*/ { 40, 0, 0x97, 596}, + /*(4814) VFMSUBADD132PD*/ { 41, 1, 0x97, 2043}, + /*(4815) VFMSUBADD132PD*/ { 40, 0, 0x97, 596}, + /*(4816) VFMSUBADD132PD*/ { 41, 1, 0x97, 2043}, + /*(4817) VFMSUBADD132PD*/ { 54, 1, 0x97, 1362}, + /*(4818) VFMSUBADD132PD*/ { 54, 101, 0x97, 2048}, + /*(4819) VFMSUBADD132PD*/ { 40, 102, 0x97, 877}, + /*(4820) VFMSUBADD132PD*/ { 54, 1, 0x97, 1362}, + /*(4821) VFMSUBADD132PD*/ { 40, 102, 0x97, 877}, + /*(4822) VFMSUBADD132PD*/ { 54, 1, 0x97, 1362}, + /*(4823) VFMSUBADD132PD*/ { 40, 102, 0x97, 877}, + /*(4824) VFMSUBADD213PD*/ { 40, 0, 0xa7, 596}, + /*(4825) VFMSUBADD213PD*/ { 41, 1, 0xa7, 2043}, + /*(4826) VFMSUBADD213PD*/ { 40, 0, 0xa7, 596}, + /*(4827) VFMSUBADD213PD*/ { 41, 1, 0xa7, 2043}, + /*(4828) VFMSUBADD213PD*/ { 54, 1, 0xa7, 1362}, + /*(4829) VFMSUBADD213PD*/ { 54, 101, 0xa7, 2048}, + /*(4830) VFMSUBADD213PD*/ { 40, 102, 0xa7, 877}, + /*(4831) VFMSUBADD213PD*/ { 54, 1, 0xa7, 1362}, + /*(4832) VFMSUBADD213PD*/ { 40, 102, 0xa7, 877}, + /*(4833) VFMSUBADD213PD*/ { 54, 1, 0xa7, 1362}, + /*(4834) VFMSUBADD213PD*/ { 40, 102, 0xa7, 877}, + /*(4835) VFMSUBADD231PD*/ { 40, 0, 0xb7, 596}, + /*(4836) VFMSUBADD231PD*/ { 41, 1, 0xb7, 2043}, + /*(4837) VFMSUBADD231PD*/ { 40, 0, 0xb7, 596}, + /*(4838) VFMSUBADD231PD*/ { 41, 1, 0xb7, 2043}, + /*(4839) VFMSUBADD231PD*/ { 54, 1, 0xb7, 1362}, + /*(4840) VFMSUBADD231PD*/ { 54, 101, 0xb7, 2048}, + /*(4841) VFMSUBADD231PD*/ { 40, 102, 0xb7, 877}, + /*(4842) VFMSUBADD231PD*/ { 54, 1, 0xb7, 1362}, + /*(4843) VFMSUBADD231PD*/ { 40, 102, 0xb7, 877}, + /*(4844) VFMSUBADD231PD*/ { 54, 1, 0xb7, 1362}, + /*(4845) VFMSUBADD231PD*/ { 40, 102, 0xb7, 877}, + /*(4846) VFMSUBADD132PS*/ { 40, 0, 0x97, 632}, + /*(4847) VFMSUBADD132PS*/ { 41, 1, 0x97, 1348}, + /*(4848) VFMSUBADD132PS*/ { 40, 0, 0x97, 632}, + /*(4849) VFMSUBADD132PS*/ { 41, 1, 0x97, 1348}, + /*(4850) VFMSUBADD132PS*/ { 54, 1, 0x97, 1377}, + /*(4851) VFMSUBADD132PS*/ { 54, 101, 0x97, 2054}, + /*(4852) VFMSUBADD132PS*/ { 40, 103, 0x97, 1383}, + /*(4853) VFMSUBADD132PS*/ { 54, 1, 0x97, 1377}, + /*(4854) VFMSUBADD132PS*/ { 40, 103, 0x97, 1383}, + /*(4855) VFMSUBADD132PS*/ { 54, 1, 0x97, 1377}, + /*(4856) VFMSUBADD132PS*/ { 40, 103, 0x97, 1383}, + /*(4857) VFMSUBADD213PS*/ { 40, 0, 0xa7, 632}, + /*(4858) VFMSUBADD213PS*/ { 41, 1, 0xa7, 1348}, + /*(4859) VFMSUBADD213PS*/ { 40, 0, 0xa7, 632}, + /*(4860) VFMSUBADD213PS*/ { 41, 1, 0xa7, 1348}, + /*(4861) VFMSUBADD213PS*/ { 54, 1, 0xa7, 1377}, + /*(4862) VFMSUBADD213PS*/ { 54, 101, 0xa7, 2054}, + /*(4863) VFMSUBADD213PS*/ { 40, 103, 0xa7, 1383}, + /*(4864) VFMSUBADD213PS*/ { 54, 1, 0xa7, 1377}, + /*(4865) VFMSUBADD213PS*/ { 40, 103, 0xa7, 1383}, + /*(4866) VFMSUBADD213PS*/ { 54, 1, 0xa7, 1377}, + /*(4867) VFMSUBADD213PS*/ { 40, 103, 0xa7, 1383}, + /*(4868) VFMSUBADD231PS*/ { 40, 0, 0xb7, 632}, + /*(4869) VFMSUBADD231PS*/ { 41, 1, 0xb7, 1348}, + /*(4870) VFMSUBADD231PS*/ { 40, 0, 0xb7, 632}, + /*(4871) VFMSUBADD231PS*/ { 41, 1, 0xb7, 1348}, + /*(4872) VFMSUBADD231PS*/ { 54, 1, 0xb7, 1377}, + /*(4873) VFMSUBADD231PS*/ { 54, 101, 0xb7, 2054}, + /*(4874) VFMSUBADD231PS*/ { 40, 103, 0xb7, 1383}, + /*(4875) VFMSUBADD231PS*/ { 54, 1, 0xb7, 1377}, + /*(4876) VFMSUBADD231PS*/ { 40, 103, 0xb7, 1383}, + /*(4877) VFMSUBADD231PS*/ { 54, 1, 0xb7, 1377}, + /*(4878) VFMSUBADD231PS*/ { 40, 103, 0xb7, 1383}, + /*(4879) VFMSUB132PD*/ { 40, 0, 0x9a, 596}, + /*(4880) VFMSUB132PD*/ { 41, 1, 0x9a, 2043}, + /*(4881) VFMSUB132PD*/ { 40, 0, 0x9a, 596}, + /*(4882) VFMSUB132PD*/ { 41, 1, 0x9a, 2043}, + /*(4883) VFMSUB132PD*/ { 54, 1, 0x9a, 1362}, + /*(4884) VFMSUB132PD*/ { 54, 101, 0x9a, 2048}, + /*(4885) VFMSUB132PD*/ { 40, 102, 0x9a, 877}, + /*(4886) VFMSUB132PD*/ { 54, 1, 0x9a, 1362}, + /*(4887) VFMSUB132PD*/ { 40, 102, 0x9a, 877}, + /*(4888) VFMSUB132PD*/ { 54, 1, 0x9a, 1362}, + /*(4889) VFMSUB132PD*/ { 40, 102, 0x9a, 877}, + /*(4890) VFMSUB132PS*/ { 40, 0, 0x9a, 632}, + /*(4891) VFMSUB132PS*/ { 41, 1, 0x9a, 1348}, + /*(4892) VFMSUB132PS*/ { 40, 0, 0x9a, 632}, + /*(4893) VFMSUB132PS*/ { 41, 1, 0x9a, 1348}, + /*(4894) VFMSUB132PS*/ { 54, 1, 0x9a, 1377}, + /*(4895) VFMSUB132PS*/ { 54, 101, 0x9a, 2054}, + /*(4896) VFMSUB132PS*/ { 40, 103, 0x9a, 1383}, + /*(4897) VFMSUB132PS*/ { 54, 1, 0x9a, 1377}, + /*(4898) VFMSUB132PS*/ { 40, 103, 0x9a, 1383}, + /*(4899) VFMSUB132PS*/ { 54, 1, 0x9a, 1377}, + /*(4900) VFMSUB132PS*/ { 40, 103, 0x9a, 1383}, + /*(4901) VFMSUB132SD*/ { 40, 0, 0x9b, 596}, + /*(4902) VFMSUB132SD*/ { 41, 1, 0x9b, 2043}, + /*(4903) VFMSUB132SD*/ { 54, 1, 0x9b, 1362}, + /*(4904) VFMSUB132SD*/ { 54, 104, 0x9b, 2048}, + /*(4905) VFMSUB132SD*/ { 55, 105, 0x9b, 876}, + /*(4906) VFMSUB132SS*/ { 40, 0, 0x9b, 632}, + /*(4907) VFMSUB132SS*/ { 41, 1, 0x9b, 1348}, + /*(4908) VFMSUB132SS*/ { 54, 1, 0x9b, 1377}, + /*(4909) VFMSUB132SS*/ { 54, 104, 0x9b, 2054}, + /*(4910) VFMSUB132SS*/ { 55, 106, 0x9b, 2019}, + /*(4911) VFMSUB213PD*/ { 40, 0, 0xaa, 596}, + /*(4912) VFMSUB213PD*/ { 41, 1, 0xaa, 2043}, + /*(4913) VFMSUB213PD*/ { 40, 0, 0xaa, 596}, + /*(4914) VFMSUB213PD*/ { 41, 1, 0xaa, 2043}, + /*(4915) VFMSUB213PD*/ { 54, 1, 0xaa, 1362}, + /*(4916) VFMSUB213PD*/ { 54, 101, 0xaa, 2048}, + /*(4917) VFMSUB213PD*/ { 40, 102, 0xaa, 877}, + /*(4918) VFMSUB213PD*/ { 54, 1, 0xaa, 1362}, + /*(4919) VFMSUB213PD*/ { 40, 102, 0xaa, 877}, + /*(4920) VFMSUB213PD*/ { 54, 1, 0xaa, 1362}, + /*(4921) VFMSUB213PD*/ { 40, 102, 0xaa, 877}, + /*(4922) VFMSUB213PS*/ { 40, 0, 0xaa, 632}, + /*(4923) VFMSUB213PS*/ { 41, 1, 0xaa, 1348}, + /*(4924) VFMSUB213PS*/ { 40, 0, 0xaa, 632}, + /*(4925) VFMSUB213PS*/ { 41, 1, 0xaa, 1348}, + /*(4926) VFMSUB213PS*/ { 54, 1, 0xaa, 1377}, + /*(4927) VFMSUB213PS*/ { 54, 101, 0xaa, 2054}, + /*(4928) VFMSUB213PS*/ { 40, 103, 0xaa, 1383}, + /*(4929) VFMSUB213PS*/ { 54, 1, 0xaa, 1377}, + /*(4930) VFMSUB213PS*/ { 40, 103, 0xaa, 1383}, + /*(4931) VFMSUB213PS*/ { 54, 1, 0xaa, 1377}, + /*(4932) VFMSUB213PS*/ { 40, 103, 0xaa, 1383}, + /*(4933) VFMSUB213SD*/ { 40, 0, 0xab, 596}, + /*(4934) VFMSUB213SD*/ { 41, 1, 0xab, 2043}, + /*(4935) VFMSUB213SD*/ { 54, 1, 0xab, 1362}, + /*(4936) VFMSUB213SD*/ { 54, 104, 0xab, 2048}, + /*(4937) VFMSUB213SD*/ { 55, 105, 0xab, 876}, + /*(4938) VFMSUB213SS*/ { 40, 0, 0xab, 632}, + /*(4939) VFMSUB213SS*/ { 41, 1, 0xab, 1348}, + /*(4940) VFMSUB213SS*/ { 54, 1, 0xab, 1377}, + /*(4941) VFMSUB213SS*/ { 54, 104, 0xab, 2054}, + /*(4942) VFMSUB213SS*/ { 55, 106, 0xab, 2019}, + /*(4943) VFMSUB231PD*/ { 40, 0, 0xba, 596}, + /*(4944) VFMSUB231PD*/ { 41, 1, 0xba, 2043}, + /*(4945) VFMSUB231PD*/ { 40, 0, 0xba, 596}, + /*(4946) VFMSUB231PD*/ { 41, 1, 0xba, 2043}, + /*(4947) VFMSUB231PD*/ { 54, 1, 0xba, 1362}, + /*(4948) VFMSUB231PD*/ { 54, 101, 0xba, 2048}, + /*(4949) VFMSUB231PD*/ { 40, 102, 0xba, 877}, + /*(4950) VFMSUB231PD*/ { 54, 1, 0xba, 1362}, + /*(4951) VFMSUB231PD*/ { 40, 102, 0xba, 877}, + /*(4952) VFMSUB231PD*/ { 54, 1, 0xba, 1362}, + /*(4953) VFMSUB231PD*/ { 40, 102, 0xba, 877}, + /*(4954) VFMSUB231PS*/ { 40, 0, 0xba, 632}, + /*(4955) VFMSUB231PS*/ { 41, 1, 0xba, 1348}, + /*(4956) VFMSUB231PS*/ { 40, 0, 0xba, 632}, + /*(4957) VFMSUB231PS*/ { 41, 1, 0xba, 1348}, + /*(4958) VFMSUB231PS*/ { 54, 1, 0xba, 1377}, + /*(4959) VFMSUB231PS*/ { 54, 101, 0xba, 2054}, + /*(4960) VFMSUB231PS*/ { 40, 103, 0xba, 1383}, + /*(4961) VFMSUB231PS*/ { 54, 1, 0xba, 1377}, + /*(4962) VFMSUB231PS*/ { 40, 103, 0xba, 1383}, + /*(4963) VFMSUB231PS*/ { 54, 1, 0xba, 1377}, + /*(4964) VFMSUB231PS*/ { 40, 103, 0xba, 1383}, + /*(4965) VFMSUB231SD*/ { 40, 0, 0xbb, 596}, + /*(4966) VFMSUB231SD*/ { 41, 1, 0xbb, 2043}, + /*(4967) VFMSUB231SD*/ { 54, 1, 0xbb, 1362}, + /*(4968) VFMSUB231SD*/ { 54, 104, 0xbb, 2048}, + /*(4969) VFMSUB231SD*/ { 55, 105, 0xbb, 876}, + /*(4970) VFMSUB231SS*/ { 40, 0, 0xbb, 632}, + /*(4971) VFMSUB231SS*/ { 41, 1, 0xbb, 1348}, + /*(4972) VFMSUB231SS*/ { 54, 1, 0xbb, 1377}, + /*(4973) VFMSUB231SS*/ { 54, 104, 0xbb, 2054}, + /*(4974) VFMSUB231SS*/ { 55, 106, 0xbb, 2019}, + /*(4975) VFNMADD132PD*/ { 40, 0, 0x9c, 596}, + /*(4976) VFNMADD132PD*/ { 41, 1, 0x9c, 2043}, + /*(4977) VFNMADD132PD*/ { 40, 0, 0x9c, 596}, + /*(4978) VFNMADD132PD*/ { 41, 1, 0x9c, 2043}, + /*(4979) VFNMADD132PD*/ { 54, 1, 0x9c, 1362}, + /*(4980) VFNMADD132PD*/ { 54, 101, 0x9c, 2048}, + /*(4981) VFNMADD132PD*/ { 40, 102, 0x9c, 877}, + /*(4982) VFNMADD132PD*/ { 54, 1, 0x9c, 1362}, + /*(4983) VFNMADD132PD*/ { 40, 102, 0x9c, 877}, + /*(4984) VFNMADD132PD*/ { 54, 1, 0x9c, 1362}, + /*(4985) VFNMADD132PD*/ { 40, 102, 0x9c, 877}, + /*(4986) VFNMADD132PS*/ { 40, 0, 0x9c, 632}, + /*(4987) VFNMADD132PS*/ { 41, 1, 0x9c, 1348}, + /*(4988) VFNMADD132PS*/ { 40, 0, 0x9c, 632}, + /*(4989) VFNMADD132PS*/ { 41, 1, 0x9c, 1348}, + /*(4990) VFNMADD132PS*/ { 54, 1, 0x9c, 1377}, + /*(4991) VFNMADD132PS*/ { 54, 101, 0x9c, 2054}, + /*(4992) VFNMADD132PS*/ { 40, 103, 0x9c, 1383}, + /*(4993) VFNMADD132PS*/ { 54, 1, 0x9c, 1377}, + /*(4994) VFNMADD132PS*/ { 40, 103, 0x9c, 1383}, + /*(4995) VFNMADD132PS*/ { 54, 1, 0x9c, 1377}, + /*(4996) VFNMADD132PS*/ { 40, 103, 0x9c, 1383}, + /*(4997) VFNMADD132SD*/ { 40, 0, 0x9d, 596}, + /*(4998) VFNMADD132SD*/ { 41, 1, 0x9d, 2043}, + /*(4999) VFNMADD132SD*/ { 54, 1, 0x9d, 1362}, + /*(5000) VFNMADD132SD*/ { 54, 104, 0x9d, 2048}, + /*(5001) VFNMADD132SD*/ { 55, 105, 0x9d, 876}, + /*(5002) VFNMADD132SS*/ { 40, 0, 0x9d, 632}, + /*(5003) VFNMADD132SS*/ { 41, 1, 0x9d, 1348}, + /*(5004) VFNMADD132SS*/ { 54, 1, 0x9d, 1377}, + /*(5005) VFNMADD132SS*/ { 54, 104, 0x9d, 2054}, + /*(5006) VFNMADD132SS*/ { 55, 106, 0x9d, 2019}, + /*(5007) VFNMADD213PD*/ { 40, 0, 0xac, 596}, + /*(5008) VFNMADD213PD*/ { 41, 1, 0xac, 2043}, + /*(5009) VFNMADD213PD*/ { 40, 0, 0xac, 596}, + /*(5010) VFNMADD213PD*/ { 41, 1, 0xac, 2043}, + /*(5011) VFNMADD213PD*/ { 54, 1, 0xac, 1362}, + /*(5012) VFNMADD213PD*/ { 54, 101, 0xac, 2048}, + /*(5013) VFNMADD213PD*/ { 40, 102, 0xac, 877}, + /*(5014) VFNMADD213PD*/ { 54, 1, 0xac, 1362}, + /*(5015) VFNMADD213PD*/ { 40, 102, 0xac, 877}, + /*(5016) VFNMADD213PD*/ { 54, 1, 0xac, 1362}, + /*(5017) VFNMADD213PD*/ { 40, 102, 0xac, 877}, + /*(5018) VFNMADD213PS*/ { 40, 0, 0xac, 632}, + /*(5019) VFNMADD213PS*/ { 41, 1, 0xac, 1348}, + /*(5020) VFNMADD213PS*/ { 40, 0, 0xac, 632}, + /*(5021) VFNMADD213PS*/ { 41, 1, 0xac, 1348}, + /*(5022) VFNMADD213PS*/ { 54, 1, 0xac, 1377}, + /*(5023) VFNMADD213PS*/ { 54, 101, 0xac, 2054}, + /*(5024) VFNMADD213PS*/ { 40, 103, 0xac, 1383}, + /*(5025) VFNMADD213PS*/ { 54, 1, 0xac, 1377}, + /*(5026) VFNMADD213PS*/ { 40, 103, 0xac, 1383}, + /*(5027) VFNMADD213PS*/ { 54, 1, 0xac, 1377}, + /*(5028) VFNMADD213PS*/ { 40, 103, 0xac, 1383}, + /*(5029) VFNMADD213SD*/ { 40, 0, 0xad, 596}, + /*(5030) VFNMADD213SD*/ { 41, 1, 0xad, 2043}, + /*(5031) VFNMADD213SD*/ { 54, 1, 0xad, 1362}, + /*(5032) VFNMADD213SD*/ { 54, 104, 0xad, 2048}, + /*(5033) VFNMADD213SD*/ { 55, 105, 0xad, 876}, + /*(5034) VFNMADD213SS*/ { 40, 0, 0xad, 632}, + /*(5035) VFNMADD213SS*/ { 41, 1, 0xad, 1348}, + /*(5036) VFNMADD213SS*/ { 54, 1, 0xad, 1377}, + /*(5037) VFNMADD213SS*/ { 54, 104, 0xad, 2054}, + /*(5038) VFNMADD213SS*/ { 55, 106, 0xad, 2019}, + /*(5039) VFNMADD231PD*/ { 40, 0, 0xbc, 596}, + /*(5040) VFNMADD231PD*/ { 41, 1, 0xbc, 2043}, + /*(5041) VFNMADD231PD*/ { 40, 0, 0xbc, 596}, + /*(5042) VFNMADD231PD*/ { 41, 1, 0xbc, 2043}, + /*(5043) VFNMADD231PD*/ { 54, 1, 0xbc, 1362}, + /*(5044) VFNMADD231PD*/ { 54, 101, 0xbc, 2048}, + /*(5045) VFNMADD231PD*/ { 40, 102, 0xbc, 877}, + /*(5046) VFNMADD231PD*/ { 54, 1, 0xbc, 1362}, + /*(5047) VFNMADD231PD*/ { 40, 102, 0xbc, 877}, + /*(5048) VFNMADD231PD*/ { 54, 1, 0xbc, 1362}, + /*(5049) VFNMADD231PD*/ { 40, 102, 0xbc, 877}, + /*(5050) VFNMADD231PS*/ { 40, 0, 0xbc, 632}, + /*(5051) VFNMADD231PS*/ { 41, 1, 0xbc, 1348}, + /*(5052) VFNMADD231PS*/ { 40, 0, 0xbc, 632}, + /*(5053) VFNMADD231PS*/ { 41, 1, 0xbc, 1348}, + /*(5054) VFNMADD231PS*/ { 54, 1, 0xbc, 1377}, + /*(5055) VFNMADD231PS*/ { 54, 101, 0xbc, 2054}, + /*(5056) VFNMADD231PS*/ { 40, 103, 0xbc, 1383}, + /*(5057) VFNMADD231PS*/ { 54, 1, 0xbc, 1377}, + /*(5058) VFNMADD231PS*/ { 40, 103, 0xbc, 1383}, + /*(5059) VFNMADD231PS*/ { 54, 1, 0xbc, 1377}, + /*(5060) VFNMADD231PS*/ { 40, 103, 0xbc, 1383}, + /*(5061) VFNMADD231SD*/ { 40, 0, 0xbd, 596}, + /*(5062) VFNMADD231SD*/ { 41, 1, 0xbd, 2043}, + /*(5063) VFNMADD231SD*/ { 54, 1, 0xbd, 1362}, + /*(5064) VFNMADD231SD*/ { 54, 104, 0xbd, 2048}, + /*(5065) VFNMADD231SD*/ { 55, 105, 0xbd, 876}, + /*(5066) VFNMADD231SS*/ { 40, 0, 0xbd, 632}, + /*(5067) VFNMADD231SS*/ { 41, 1, 0xbd, 1348}, + /*(5068) VFNMADD231SS*/ { 54, 1, 0xbd, 1377}, + /*(5069) VFNMADD231SS*/ { 54, 104, 0xbd, 2054}, + /*(5070) VFNMADD231SS*/ { 55, 106, 0xbd, 2019}, + /*(5071) VFNMSUB132PD*/ { 40, 0, 0x9e, 596}, + /*(5072) VFNMSUB132PD*/ { 41, 1, 0x9e, 2043}, + /*(5073) VFNMSUB132PD*/ { 40, 0, 0x9e, 596}, + /*(5074) VFNMSUB132PD*/ { 41, 1, 0x9e, 2043}, + /*(5075) VFNMSUB132PD*/ { 54, 1, 0x9e, 1362}, + /*(5076) VFNMSUB132PD*/ { 54, 101, 0x9e, 2048}, + /*(5077) VFNMSUB132PD*/ { 40, 102, 0x9e, 877}, + /*(5078) VFNMSUB132PD*/ { 54, 1, 0x9e, 1362}, + /*(5079) VFNMSUB132PD*/ { 40, 102, 0x9e, 877}, + /*(5080) VFNMSUB132PD*/ { 54, 1, 0x9e, 1362}, + /*(5081) VFNMSUB132PD*/ { 40, 102, 0x9e, 877}, + /*(5082) VFNMSUB132PS*/ { 40, 0, 0x9e, 632}, + /*(5083) VFNMSUB132PS*/ { 41, 1, 0x9e, 1348}, + /*(5084) VFNMSUB132PS*/ { 40, 0, 0x9e, 632}, + /*(5085) VFNMSUB132PS*/ { 41, 1, 0x9e, 1348}, + /*(5086) VFNMSUB132PS*/ { 54, 1, 0x9e, 1377}, + /*(5087) VFNMSUB132PS*/ { 54, 101, 0x9e, 2054}, + /*(5088) VFNMSUB132PS*/ { 40, 103, 0x9e, 1383}, + /*(5089) VFNMSUB132PS*/ { 54, 1, 0x9e, 1377}, + /*(5090) VFNMSUB132PS*/ { 40, 103, 0x9e, 1383}, + /*(5091) VFNMSUB132PS*/ { 54, 1, 0x9e, 1377}, + /*(5092) VFNMSUB132PS*/ { 40, 103, 0x9e, 1383}, + /*(5093) VFNMSUB132SD*/ { 40, 0, 0x9f, 596}, + /*(5094) VFNMSUB132SD*/ { 41, 1, 0x9f, 2043}, + /*(5095) VFNMSUB132SD*/ { 54, 1, 0x9f, 1362}, + /*(5096) VFNMSUB132SD*/ { 54, 104, 0x9f, 2048}, + /*(5097) VFNMSUB132SD*/ { 55, 105, 0x9f, 876}, + /*(5098) VFNMSUB132SS*/ { 40, 0, 0x9f, 632}, + /*(5099) VFNMSUB132SS*/ { 41, 1, 0x9f, 1348}, + /*(5100) VFNMSUB132SS*/ { 54, 1, 0x9f, 1377}, + /*(5101) VFNMSUB132SS*/ { 54, 104, 0x9f, 2054}, + /*(5102) VFNMSUB132SS*/ { 55, 106, 0x9f, 2019}, + /*(5103) VFNMSUB213PD*/ { 40, 0, 0xae, 596}, + /*(5104) VFNMSUB213PD*/ { 41, 1, 0xae, 2043}, + /*(5105) VFNMSUB213PD*/ { 40, 0, 0xae, 596}, + /*(5106) VFNMSUB213PD*/ { 41, 1, 0xae, 2043}, + /*(5107) VFNMSUB213PD*/ { 54, 1, 0xae, 1362}, + /*(5108) VFNMSUB213PD*/ { 54, 101, 0xae, 2048}, + /*(5109) VFNMSUB213PD*/ { 40, 102, 0xae, 877}, + /*(5110) VFNMSUB213PD*/ { 54, 1, 0xae, 1362}, + /*(5111) VFNMSUB213PD*/ { 40, 102, 0xae, 877}, + /*(5112) VFNMSUB213PD*/ { 54, 1, 0xae, 1362}, + /*(5113) VFNMSUB213PD*/ { 40, 102, 0xae, 877}, + /*(5114) VFNMSUB213PS*/ { 40, 0, 0xae, 632}, + /*(5115) VFNMSUB213PS*/ { 41, 1, 0xae, 1348}, + /*(5116) VFNMSUB213PS*/ { 40, 0, 0xae, 632}, + /*(5117) VFNMSUB213PS*/ { 41, 1, 0xae, 1348}, + /*(5118) VFNMSUB213PS*/ { 54, 1, 0xae, 1377}, + /*(5119) VFNMSUB213PS*/ { 54, 101, 0xae, 2054}, + /*(5120) VFNMSUB213PS*/ { 40, 103, 0xae, 1383}, + /*(5121) VFNMSUB213PS*/ { 54, 1, 0xae, 1377}, + /*(5122) VFNMSUB213PS*/ { 40, 103, 0xae, 1383}, + /*(5123) VFNMSUB213PS*/ { 54, 1, 0xae, 1377}, + /*(5124) VFNMSUB213PS*/ { 40, 103, 0xae, 1383}, + /*(5125) VFNMSUB213SD*/ { 40, 0, 0xaf, 596}, + /*(5126) VFNMSUB213SD*/ { 41, 1, 0xaf, 2043}, + /*(5127) VFNMSUB213SD*/ { 54, 1, 0xaf, 1362}, + /*(5128) VFNMSUB213SD*/ { 54, 104, 0xaf, 2048}, + /*(5129) VFNMSUB213SD*/ { 55, 105, 0xaf, 876}, + /*(5130) VFNMSUB213SS*/ { 40, 0, 0xaf, 632}, + /*(5131) VFNMSUB213SS*/ { 41, 1, 0xaf, 1348}, + /*(5132) VFNMSUB213SS*/ { 54, 1, 0xaf, 1377}, + /*(5133) VFNMSUB213SS*/ { 54, 104, 0xaf, 2054}, + /*(5134) VFNMSUB213SS*/ { 55, 106, 0xaf, 2019}, + /*(5135) VFNMSUB231PD*/ { 40, 0, 0xbe, 596}, + /*(5136) VFNMSUB231PD*/ { 41, 1, 0xbe, 2043}, + /*(5137) VFNMSUB231PD*/ { 40, 0, 0xbe, 596}, + /*(5138) VFNMSUB231PD*/ { 41, 1, 0xbe, 2043}, + /*(5139) VFNMSUB231PD*/ { 54, 1, 0xbe, 1362}, + /*(5140) VFNMSUB231PD*/ { 54, 101, 0xbe, 2048}, + /*(5141) VFNMSUB231PD*/ { 40, 102, 0xbe, 877}, + /*(5142) VFNMSUB231PD*/ { 54, 1, 0xbe, 1362}, + /*(5143) VFNMSUB231PD*/ { 40, 102, 0xbe, 877}, + /*(5144) VFNMSUB231PD*/ { 54, 1, 0xbe, 1362}, + /*(5145) VFNMSUB231PD*/ { 40, 102, 0xbe, 877}, + /*(5146) VFNMSUB231PS*/ { 40, 0, 0xbe, 632}, + /*(5147) VFNMSUB231PS*/ { 41, 1, 0xbe, 1348}, + /*(5148) VFNMSUB231PS*/ { 40, 0, 0xbe, 632}, + /*(5149) VFNMSUB231PS*/ { 41, 1, 0xbe, 1348}, + /*(5150) VFNMSUB231PS*/ { 54, 1, 0xbe, 1377}, + /*(5151) VFNMSUB231PS*/ { 54, 101, 0xbe, 2054}, + /*(5152) VFNMSUB231PS*/ { 40, 103, 0xbe, 1383}, + /*(5153) VFNMSUB231PS*/ { 54, 1, 0xbe, 1377}, + /*(5154) VFNMSUB231PS*/ { 40, 103, 0xbe, 1383}, + /*(5155) VFNMSUB231PS*/ { 54, 1, 0xbe, 1377}, + /*(5156) VFNMSUB231PS*/ { 40, 103, 0xbe, 1383}, + /*(5157) VFNMSUB231SD*/ { 40, 0, 0xbf, 596}, + /*(5158) VFNMSUB231SD*/ { 41, 1, 0xbf, 2043}, + /*(5159) VFNMSUB231SD*/ { 54, 1, 0xbf, 1362}, + /*(5160) VFNMSUB231SD*/ { 54, 104, 0xbf, 2048}, + /*(5161) VFNMSUB231SD*/ { 55, 105, 0xbf, 876}, + /*(5162) VFNMSUB231SS*/ { 40, 0, 0xbf, 632}, + /*(5163) VFNMSUB231SS*/ { 41, 1, 0xbf, 1348}, + /*(5164) VFNMSUB231SS*/ { 54, 1, 0xbf, 1377}, + /*(5165) VFNMSUB231SS*/ { 54, 104, 0xbf, 2054}, + /*(5166) VFNMSUB231SS*/ { 55, 106, 0xbf, 2019}, + /*(5167) VGATHERDPD*/ { 95, 159, 0x92, 2060}, + /*(5168) VGATHERDPD*/ { 95, 159, 0x92, 2060}, + /*(5169) VGATHERDPD*/ { 96, 160, 0x92, 2065}, + /*(5170) VGATHERDPD*/ { 96, 161, 0x92, 2065}, + /*(5171) VGATHERDPD*/ { 96, 161, 0x92, 2065}, + /*(5172) VGATHERDPS*/ { 95, 162, 0x92, 2074}, + /*(5173) VGATHERDPS*/ { 95, 159, 0x92, 2074}, + /*(5174) VGATHERDPS*/ { 96, 163, 0x92, 2079}, + /*(5175) VGATHERDPS*/ { 96, 164, 0x92, 2079}, + /*(5176) VGATHERDPS*/ { 96, 165, 0x92, 2079}, + /*(5177) VGATHERQPD*/ { 95, 162, 0x93, 2060}, + /*(5178) VGATHERQPD*/ { 95, 159, 0x93, 2060}, + /*(5179) VGATHERQPD*/ { 96, 166, 0x93, 2065}, + /*(5180) VGATHERQPD*/ { 96, 161, 0x93, 2065}, + /*(5181) VGATHERQPD*/ { 96, 160, 0x93, 2065}, + /*(5182) VGATHERQPS*/ { 95, 162, 0x93, 2074}, + /*(5183) VGATHERQPS*/ { 95, 159, 0x93, 2074}, + /*(5184) VGATHERQPS*/ { 96, 163, 0x93, 2079}, + /*(5185) VGATHERQPS*/ { 96, 164, 0x93, 2079}, + /*(5186) VGATHERQPS*/ { 96, 165, 0x93, 2079}, + /*(5187) VPGATHERDQ*/ { 95, 159, 0x90, 2060}, + /*(5188) VPGATHERDQ*/ { 95, 159, 0x90, 2060}, + /*(5189) VPGATHERDQ*/ { 96, 160, 0x90, 2065}, + /*(5190) VPGATHERDQ*/ { 96, 161, 0x90, 2065}, + /*(5191) VPGATHERDQ*/ { 96, 161, 0x90, 2065}, + /*(5192) VPGATHERDD*/ { 95, 162, 0x90, 2074}, + /*(5193) VPGATHERDD*/ { 95, 159, 0x90, 2074}, + /*(5194) VPGATHERDD*/ { 96, 163, 0x90, 2079}, + /*(5195) VPGATHERDD*/ { 96, 164, 0x90, 2079}, + /*(5196) VPGATHERDD*/ { 96, 165, 0x90, 2079}, + /*(5197) VPGATHERQQ*/ { 95, 162, 0x91, 2060}, + /*(5198) VPGATHERQQ*/ { 95, 159, 0x91, 2060}, + /*(5199) VPGATHERQQ*/ { 96, 166, 0x91, 2065}, + /*(5200) VPGATHERQQ*/ { 96, 161, 0x91, 2065}, + /*(5201) VPGATHERQQ*/ { 96, 160, 0x91, 2065}, + /*(5202) VPGATHERQD*/ { 95, 162, 0x91, 2074}, + /*(5203) VPGATHERQD*/ { 95, 159, 0x91, 2074}, + /*(5204) VPGATHERQD*/ { 96, 163, 0x91, 2079}, + /*(5205) VPGATHERQD*/ { 96, 164, 0x91, 2079}, + /*(5206) VPGATHERQD*/ { 96, 165, 0x91, 2079}, + /*(5207) VINSERTI128*/ { 40, 9, 0x38, 508}, + /*(5208) VINSERTI128*/ { 41, 10, 0x38, 507}, + /*(5209) VEXTRACTI128*/ { 42, 9, 0x39, 1304}, + /*(5210) VEXTRACTI128*/ { 43, 10, 0x39, 1310}, + /*(5211) VPMASKMOVD*/ { 40, 0, 0x8c, 632}, + /*(5212) VPMASKMOVD*/ { 40, 0, 0x8c, 632}, + /*(5213) VPMASKMOVD*/ { 40, 0, 0x8e, 632}, + /*(5214) VPMASKMOVD*/ { 40, 0, 0x8e, 632}, + /*(5215) VPMASKMOVQ*/ { 40, 0, 0x8c, 596}, + /*(5216) VPMASKMOVQ*/ { 40, 0, 0x8c, 596}, + /*(5217) VPMASKMOVQ*/ { 40, 0, 0x8e, 596}, + /*(5218) VPMASKMOVQ*/ { 40, 0, 0x8e, 596}, + /*(5219) VPERM2I128*/ { 40, 9, 0x46, 508}, + /*(5220) VPERM2I128*/ { 41, 10, 0x46, 507}, + /*(5221) VPERMQ*/ { 42, 9, 0x0, 1665}, + /*(5222) VPERMQ*/ { 43, 10, 0x0, 1931}, + /*(5223) VPERMQ*/ { 61, 10, 0x0, 1353}, + /*(5224) VPERMQ*/ { 62, 108, 0x0, 716}, + /*(5225) VPERMQ*/ { 54, 1, 0x36, 1362}, + /*(5226) VPERMQ*/ { 40, 102, 0x36, 877}, + /*(5227) VPERMQ*/ { 61, 10, 0x0, 1353}, + /*(5228) VPERMQ*/ { 62, 108, 0x0, 716}, + /*(5229) VPERMQ*/ { 54, 1, 0x36, 1362}, + /*(5230) VPERMQ*/ { 40, 102, 0x36, 877}, + /*(5231) VPERMPD*/ { 42, 9, 0x1, 1665}, + /*(5232) VPERMPD*/ { 43, 10, 0x1, 1931}, + /*(5233) VPERMPD*/ { 61, 10, 0x1, 1353}, + /*(5234) VPERMPD*/ { 62, 108, 0x1, 716}, + /*(5235) VPERMPD*/ { 54, 1, 0x16, 1362}, + /*(5236) VPERMPD*/ { 40, 102, 0x16, 877}, + /*(5237) VPERMPD*/ { 61, 10, 0x1, 1353}, + /*(5238) VPERMPD*/ { 62, 108, 0x1, 716}, + /*(5239) VPERMPD*/ { 54, 1, 0x16, 1362}, + /*(5240) VPERMPD*/ { 40, 102, 0x16, 877}, + /*(5241) VPERMD*/ { 40, 0, 0x36, 632}, + /*(5242) VPERMD*/ { 41, 1, 0x36, 1348}, + /*(5243) VPERMD*/ { 54, 1, 0x36, 1377}, + /*(5244) VPERMD*/ { 40, 103, 0x36, 1383}, + /*(5245) VPERMD*/ { 54, 1, 0x36, 1377}, + /*(5246) VPERMD*/ { 40, 103, 0x36, 1383}, + /*(5247) VPERMPS*/ { 40, 0, 0x16, 632}, + /*(5248) VPERMPS*/ { 41, 1, 0x16, 1348}, + /*(5249) VPERMPS*/ { 54, 1, 0x16, 1377}, + /*(5250) VPERMPS*/ { 40, 103, 0x16, 1383}, + /*(5251) VPERMPS*/ { 54, 1, 0x16, 1377}, + /*(5252) VPERMPS*/ { 40, 103, 0x16, 1383}, + /*(5253) VPBLENDD*/ { 40, 9, 0x2, 508}, + /*(5254) VPBLENDD*/ { 41, 10, 0x2, 507}, + /*(5255) VPBLENDD*/ { 40, 9, 0x2, 508}, + /*(5256) VPBLENDD*/ { 41, 10, 0x2, 507}, + /*(5257) VPBROADCASTB*/ { 74, 0, 0x78, 2088}, + /*(5258) VPBROADCASTB*/ { 75, 1, 0x78, 2095}, + /*(5259) VPBROADCASTB*/ { 74, 0, 0x78, 2103}, + /*(5260) VPBROADCASTB*/ { 75, 1, 0x78, 2110}, + /*(5261) VPBROADCASTB*/ { 77, 1, 0x78, 2118}, + /*(5262) VPBROADCASTB*/ { 76, 167, 0x78, 2128}, + /*(5263) VPBROADCASTB*/ { 77, 1, 0x7a, 2118}, + /*(5264) VPBROADCASTB*/ { 77, 1, 0x78, 2137}, + /*(5265) VPBROADCASTB*/ { 76, 167, 0x78, 2147}, + /*(5266) VPBROADCASTB*/ { 77, 1, 0x7a, 2137}, + /*(5267) VPBROADCASTB*/ { 77, 1, 0x78, 2156}, + /*(5268) VPBROADCASTB*/ { 76, 167, 0x78, 2166}, + /*(5269) VPBROADCASTB*/ { 77, 1, 0x7a, 2156}, + /*(5270) VPBROADCASTW*/ { 74, 0, 0x79, 2175}, + /*(5271) VPBROADCASTW*/ { 75, 1, 0x79, 2182}, + /*(5272) VPBROADCASTW*/ { 74, 0, 0x79, 2190}, + /*(5273) VPBROADCASTW*/ { 75, 1, 0x79, 2197}, + /*(5274) VPBROADCASTW*/ { 77, 1, 0x79, 2205}, + /*(5275) VPBROADCASTW*/ { 76, 168, 0x79, 2215}, + /*(5276) VPBROADCASTW*/ { 77, 1, 0x7b, 2205}, + /*(5277) VPBROADCASTW*/ { 77, 1, 0x79, 2224}, + /*(5278) VPBROADCASTW*/ { 76, 168, 0x79, 2234}, + /*(5279) VPBROADCASTW*/ { 77, 1, 0x7b, 2224}, + /*(5280) VPBROADCASTW*/ { 77, 1, 0x79, 2243}, + /*(5281) VPBROADCASTW*/ { 76, 168, 0x79, 2253}, + /*(5282) VPBROADCASTW*/ { 77, 1, 0x7b, 2243}, + /*(5283) VPBROADCASTD*/ { 74, 0, 0x58, 1387}, + /*(5284) VPBROADCASTD*/ { 75, 1, 0x58, 1401}, + /*(5285) VPBROADCASTD*/ { 74, 0, 0x58, 1394}, + /*(5286) VPBROADCASTD*/ { 75, 1, 0x58, 1409}, + /*(5287) VPBROADCASTD*/ { 76, 125, 0x58, 1417}, + /*(5288) VPBROADCASTD*/ { 77, 1, 0x58, 1426}, + /*(5289) VPBROADCASTD*/ { 97, 1, 0x7c, 2262}, + /*(5290) VPBROADCASTD*/ { 77, 1, 0x7c, 1426}, + /*(5291) VPBROADCASTD*/ { 76, 125, 0x58, 1436}, + /*(5292) VPBROADCASTD*/ { 77, 1, 0x58, 1445}, + /*(5293) VPBROADCASTD*/ { 97, 1, 0x7c, 2271}, + /*(5294) VPBROADCASTD*/ { 77, 1, 0x7c, 1445}, + /*(5295) VPBROADCASTD*/ { 76, 125, 0x58, 1455}, + /*(5296) VPBROADCASTD*/ { 77, 1, 0x58, 1464}, + /*(5297) VPBROADCASTD*/ { 97, 1, 0x7c, 2280}, + /*(5298) VPBROADCASTD*/ { 77, 1, 0x7c, 1464}, + /*(5299) VPBROADCASTQ*/ { 74, 0, 0x59, 2289}, + /*(5300) VPBROADCASTQ*/ { 75, 1, 0x59, 2296}, + /*(5301) VPBROADCASTQ*/ { 74, 0, 0x59, 1474}, + /*(5302) VPBROADCASTQ*/ { 75, 1, 0x59, 1481}, + /*(5303) VPBROADCASTQ*/ { 76, 126, 0x59, 1489}, + /*(5304) VPBROADCASTQ*/ { 77, 1, 0x59, 1498}, + /*(5305) VPBROADCASTQ*/ { 77, 1, 0x7c, 1498}, + /*(5306) VPBROADCASTQ*/ { 76, 126, 0x59, 2304}, + /*(5307) VPBROADCASTQ*/ { 77, 1, 0x59, 2313}, + /*(5308) VPBROADCASTQ*/ { 77, 1, 0x7c, 2313}, + /*(5309) VPBROADCASTQ*/ { 76, 126, 0x59, 1508}, + /*(5310) VPBROADCASTQ*/ { 77, 1, 0x59, 1517}, + /*(5311) VPBROADCASTQ*/ { 77, 1, 0x7c, 1517}, + /*(5312) VBROADCASTI128*/ { 74, 0, 0x5a, 1527}, + /*(5313) VPSLLVD*/ { 40, 0, 0x47, 632}, + /*(5314) VPSLLVD*/ { 41, 1, 0x47, 1348}, + /*(5315) VPSLLVD*/ { 40, 0, 0x47, 632}, + /*(5316) VPSLLVD*/ { 41, 1, 0x47, 1348}, + /*(5317) VPSLLVD*/ { 54, 1, 0x47, 1377}, + /*(5318) VPSLLVD*/ { 40, 103, 0x47, 1383}, + /*(5319) VPSLLVD*/ { 54, 1, 0x47, 1377}, + /*(5320) VPSLLVD*/ { 40, 103, 0x47, 1383}, + /*(5321) VPSLLVD*/ { 54, 1, 0x47, 1377}, + /*(5322) VPSLLVD*/ { 40, 103, 0x47, 1383}, + /*(5323) VPSLLVQ*/ { 40, 0, 0x47, 596}, + /*(5324) VPSLLVQ*/ { 41, 1, 0x47, 2043}, + /*(5325) VPSLLVQ*/ { 40, 0, 0x47, 596}, + /*(5326) VPSLLVQ*/ { 41, 1, 0x47, 2043}, + /*(5327) VPSLLVQ*/ { 54, 1, 0x47, 1362}, + /*(5328) VPSLLVQ*/ { 40, 102, 0x47, 877}, + /*(5329) VPSLLVQ*/ { 54, 1, 0x47, 1362}, + /*(5330) VPSLLVQ*/ { 40, 102, 0x47, 877}, + /*(5331) VPSLLVQ*/ { 54, 1, 0x47, 1362}, + /*(5332) VPSLLVQ*/ { 40, 102, 0x47, 877}, + /*(5333) VPSRLVD*/ { 40, 0, 0x45, 632}, + /*(5334) VPSRLVD*/ { 41, 1, 0x45, 1348}, + /*(5335) VPSRLVD*/ { 40, 0, 0x45, 632}, + /*(5336) VPSRLVD*/ { 41, 1, 0x45, 1348}, + /*(5337) VPSRLVD*/ { 54, 1, 0x45, 1377}, + /*(5338) VPSRLVD*/ { 40, 103, 0x45, 1383}, + /*(5339) VPSRLVD*/ { 54, 1, 0x45, 1377}, + /*(5340) VPSRLVD*/ { 40, 103, 0x45, 1383}, + /*(5341) VPSRLVD*/ { 54, 1, 0x45, 1377}, + /*(5342) VPSRLVD*/ { 40, 103, 0x45, 1383}, + /*(5343) VPSRLVQ*/ { 40, 0, 0x45, 596}, + /*(5344) VPSRLVQ*/ { 41, 1, 0x45, 2043}, + /*(5345) VPSRLVQ*/ { 40, 0, 0x45, 596}, + /*(5346) VPSRLVQ*/ { 41, 1, 0x45, 2043}, + /*(5347) VPSRLVQ*/ { 54, 1, 0x45, 1362}, + /*(5348) VPSRLVQ*/ { 40, 102, 0x45, 877}, + /*(5349) VPSRLVQ*/ { 54, 1, 0x45, 1362}, + /*(5350) VPSRLVQ*/ { 40, 102, 0x45, 877}, + /*(5351) VPSRLVQ*/ { 54, 1, 0x45, 1362}, + /*(5352) VPSRLVQ*/ { 40, 102, 0x45, 877}, + /*(5353) VPSRAVD*/ { 40, 0, 0x46, 632}, + /*(5354) VPSRAVD*/ { 41, 1, 0x46, 1348}, + /*(5355) VPSRAVD*/ { 40, 0, 0x46, 632}, + /*(5356) VPSRAVD*/ { 41, 1, 0x46, 1348}, + /*(5357) VPSRAVD*/ { 54, 1, 0x46, 1377}, + /*(5358) VPSRAVD*/ { 40, 103, 0x46, 1383}, + /*(5359) VPSRAVD*/ { 54, 1, 0x46, 1377}, + /*(5360) VPSRAVD*/ { 40, 103, 0x46, 1383}, + /*(5361) VPSRAVD*/ { 54, 1, 0x46, 1377}, + /*(5362) VPSRAVD*/ { 40, 103, 0x46, 1383}, + /*(5363) PDEP*/ { 98, 0, 0xf5, 2323}, + /*(5364) PDEP*/ { 99, 0, 0xf5, 2327}, + /*(5365) PDEP*/ { 100, 1, 0xf5, 2332}, + /*(5366) PDEP*/ { 101, 1, 0xf5, 2337}, + /*(5367) PDEP*/ { 99, 0, 0xf5, 2343}, + /*(5368) PDEP*/ { 101, 1, 0xf5, 2348}, + /*(5369) PEXT*/ { 98, 0, 0xf5, 2354}, + /*(5370) PEXT*/ { 99, 0, 0xf5, 2358}, + /*(5371) PEXT*/ { 100, 1, 0xf5, 2363}, + /*(5372) PEXT*/ { 101, 1, 0xf5, 2368}, + /*(5373) PEXT*/ { 99, 0, 0xf5, 271}, + /*(5374) PEXT*/ { 101, 1, 0xf5, 2374}, + /*(5375) ANDN*/ { 98, 0, 0xf2, 292}, + /*(5376) ANDN*/ { 99, 0, 0xf2, 733}, + /*(5377) ANDN*/ { 100, 1, 0xf2, 556}, + /*(5378) ANDN*/ { 101, 1, 0xf2, 2380}, + /*(5379) ANDN*/ { 99, 0, 0xf2, 2386}, + /*(5380) ANDN*/ { 101, 1, 0xf2, 2391}, + /*(5381) BLSR*/ { 102, 0, 0xf3, 2386}, + /*(5382) BLSR*/ { 103, 0, 0xf3, 2397}, + /*(5383) BLSR*/ { 104, 1, 0xf3, 2391}, + /*(5384) BLSR*/ { 105, 1, 0xf3, 2403}, + /*(5385) BLSR*/ { 103, 0, 0xf3, 2410}, + /*(5386) BLSR*/ { 105, 1, 0xf3, 2416}, + /*(5387) BLSMSK*/ { 102, 0, 0xf3, 1198}, + /*(5388) BLSMSK*/ { 103, 0, 0xf3, 1205}, + /*(5389) BLSMSK*/ { 104, 1, 0xf3, 2423}, + /*(5390) BLSMSK*/ { 105, 1, 0xf3, 2429}, + /*(5391) BLSMSK*/ { 103, 0, 0xf3, 2436}, + /*(5392) BLSMSK*/ { 105, 1, 0xf3, 2442}, + /*(5393) BLSI*/ { 102, 0, 0xf3, 556}, + /*(5394) BLSI*/ { 103, 0, 0xf3, 2380}, + /*(5395) BLSI*/ { 104, 1, 0xf3, 2449}, + /*(5396) BLSI*/ { 105, 1, 0xf3, 2455}, + /*(5397) BLSI*/ { 103, 0, 0xf3, 2391}, + /*(5398) BLSI*/ { 105, 1, 0xf3, 2462}, + /*(5399) BZHI*/ { 98, 0, 0xf5, 292}, + /*(5400) BZHI*/ { 99, 0, 0xf5, 733}, + /*(5401) BZHI*/ { 100, 1, 0xf5, 556}, + /*(5402) BZHI*/ { 101, 1, 0xf5, 2380}, + /*(5403) BZHI*/ { 99, 0, 0xf5, 2386}, + /*(5404) BZHI*/ { 101, 1, 0xf5, 2391}, + /*(5405) BEXTR*/ { 98, 0, 0xf7, 292}, + /*(5406) BEXTR*/ { 99, 0, 0xf7, 733}, + /*(5407) BEXTR*/ { 100, 1, 0xf7, 556}, + /*(5408) BEXTR*/ { 101, 1, 0xf7, 2380}, + /*(5409) BEXTR*/ { 99, 0, 0xf7, 2386}, + /*(5410) BEXTR*/ { 101, 1, 0xf7, 2391}, + /*(5411) SHLX*/ { 98, 0, 0xf7, 1193}, + /*(5412) SHLX*/ { 99, 0, 0xf7, 722}, + /*(5413) SHLX*/ { 100, 1, 0xf7, 2416}, + /*(5414) SHLX*/ { 101, 1, 0xf7, 1348}, + /*(5415) SHLX*/ { 99, 0, 0xf7, 2469}, + /*(5416) SHLX*/ { 101, 1, 0xf7, 2474}, + /*(5417) SARX*/ { 98, 0, 0xf7, 2354}, + /*(5418) SARX*/ { 99, 0, 0xf7, 2358}, + /*(5419) SARX*/ { 100, 1, 0xf7, 2363}, + /*(5420) SARX*/ { 101, 1, 0xf7, 2368}, + /*(5421) SARX*/ { 99, 0, 0xf7, 271}, + /*(5422) SARX*/ { 101, 1, 0xf7, 2374}, + /*(5423) SHRX*/ { 98, 0, 0xf7, 2323}, + /*(5424) SHRX*/ { 99, 0, 0xf7, 2327}, + /*(5425) SHRX*/ { 100, 1, 0xf7, 2332}, + /*(5426) SHRX*/ { 101, 1, 0xf7, 2337}, + /*(5427) SHRX*/ { 99, 0, 0xf7, 2343}, + /*(5428) SHRX*/ { 101, 1, 0xf7, 2348}, + /*(5429) MULX*/ { 100, 1, 0xf6, 2332}, + /*(5430) MULX*/ { 101, 1, 0xf6, 2337}, + /*(5431) MULX*/ { 98, 0, 0xf6, 2323}, + /*(5432) MULX*/ { 99, 0, 0xf6, 2327}, + /*(5433) MULX*/ { 101, 1, 0xf6, 2348}, + /*(5434) MULX*/ { 99, 0, 0xf6, 2343}, + /*(5435) RORX*/ { 106, 10, 0xf0, 2480}, + /*(5436) RORX*/ { 107, 10, 0xf0, 2487}, + /*(5437) RORX*/ { 73, 9, 0xf0, 855}, + /*(5438) RORX*/ { 108, 9, 0xf0, 2488}, + /*(5439) RORX*/ { 107, 10, 0xf0, 2495}, + /*(5440) RORX*/ { 108, 9, 0xf0, 955}, + /*(5441) TZCNT*/ { 36, 18, 0xbc, 4}, + /*(5442) TZCNT*/ { 37, 19, 0xbc, 118}, + /*(5443) VMFUNC*/ { 25, 19, 0x1, 2503}, + /*(5444) INVPCID*/ { 14, 84, 0x82, 121}, + /*(5445) INVPCID*/ { 14, 84, 0x82, 121}, + /*(5446) XBEGIN*/ { 5, 169, 0xc7, 18}, + /*(5447) XEND*/ { 25, 19, 0x1, 2508}, + /*(5448) XABORT*/ { 5, 10, 0xc6, 18}, + /*(5449) XTEST*/ { 25, 19, 0x1, 2513}, + /*(5450) ADCX*/ { 35, 170, 0xf6, 273}, + /*(5451) ADCX*/ { 28, 171, 0xf6, 187}, + /*(5452) ADCX*/ { 35, 170, 0xf6, 277}, + /*(5453) ADCX*/ { 28, 171, 0xf6, 121}, + /*(5454) ADOX*/ { 34, 170, 0xf6, 225}, + /*(5455) ADOX*/ { 29, 171, 0xf6, 1}, + /*(5456) ADOX*/ { 34, 170, 0xf6, 118}, + /*(5457) ADOX*/ { 29, 171, 0xf6, 4}, + /*(5458) RDPKRU*/ { 25, 19, 0x1, 2518}, + /*(5459) WRPKRU*/ { 25, 19, 0x1, 2523}, + /*(5460) CLWB*/ { 10, 34, 0xae, 34}, + /*(5461) VPDPBUSD*/ { 54, 1, 0x50, 1377}, + /*(5462) VPDPBUSD*/ { 40, 103, 0x50, 1383}, + /*(5463) VPDPBUSD*/ { 54, 1, 0x50, 1377}, + /*(5464) VPDPBUSD*/ { 40, 103, 0x50, 1383}, + /*(5465) VPDPBUSD*/ { 54, 1, 0x50, 1377}, + /*(5466) VPDPBUSD*/ { 40, 103, 0x50, 1383}, + /*(5467) VPDPBUSD*/ { 41, 1, 0x50, 1348}, + /*(5468) VPDPBUSD*/ { 40, 0, 0x50, 632}, + /*(5469) VPDPBUSD*/ { 41, 1, 0x50, 1348}, + /*(5470) VPDPBUSD*/ { 40, 0, 0x50, 632}, + /*(5471) VPDPBUSDS*/ { 54, 1, 0x51, 1377}, + /*(5472) VPDPBUSDS*/ { 40, 103, 0x51, 1383}, + /*(5473) VPDPBUSDS*/ { 54, 1, 0x51, 1377}, + /*(5474) VPDPBUSDS*/ { 40, 103, 0x51, 1383}, + /*(5475) VPDPBUSDS*/ { 54, 1, 0x51, 1377}, + /*(5476) VPDPBUSDS*/ { 40, 103, 0x51, 1383}, + /*(5477) VPDPBUSDS*/ { 41, 1, 0x51, 1348}, + /*(5478) VPDPBUSDS*/ { 40, 0, 0x51, 632}, + /*(5479) VPDPBUSDS*/ { 41, 1, 0x51, 1348}, + /*(5480) VPDPBUSDS*/ { 40, 0, 0x51, 632}, + /*(5481) VPDPWSSD*/ { 54, 1, 0x52, 1377}, + /*(5482) VPDPWSSD*/ { 40, 103, 0x52, 1383}, + /*(5483) VPDPWSSD*/ { 54, 1, 0x52, 1377}, + /*(5484) VPDPWSSD*/ { 40, 103, 0x52, 1383}, + /*(5485) VPDPWSSD*/ { 54, 1, 0x52, 1377}, + /*(5486) VPDPWSSD*/ { 40, 103, 0x52, 1383}, + /*(5487) VPDPWSSD*/ { 41, 1, 0x52, 1348}, + /*(5488) VPDPWSSD*/ { 40, 0, 0x52, 632}, + /*(5489) VPDPWSSD*/ { 41, 1, 0x52, 1348}, + /*(5490) VPDPWSSD*/ { 40, 0, 0x52, 632}, + /*(5491) VPDPWSSDS*/ { 54, 1, 0x53, 1377}, + /*(5492) VPDPWSSDS*/ { 40, 103, 0x53, 1383}, + /*(5493) VPDPWSSDS*/ { 54, 1, 0x53, 1377}, + /*(5494) VPDPWSSDS*/ { 40, 103, 0x53, 1383}, + /*(5495) VPDPWSSDS*/ { 54, 1, 0x53, 1377}, + /*(5496) VPDPWSSDS*/ { 40, 103, 0x53, 1383}, + /*(5497) VPDPWSSDS*/ { 41, 1, 0x53, 1348}, + /*(5498) VPDPWSSDS*/ { 40, 0, 0x53, 632}, + /*(5499) VPDPWSSDS*/ { 41, 1, 0x53, 1348}, + /*(5500) VPDPWSSDS*/ { 40, 0, 0x53, 632}, + /*(5501) VCVTNE2PS2BF16*/ { 54, 1, 0x72, 2528}, + /*(5502) VCVTNE2PS2BF16*/ { 40, 103, 0x72, 2534}, + /*(5503) VCVTNE2PS2BF16*/ { 54, 1, 0x72, 2528}, + /*(5504) VCVTNE2PS2BF16*/ { 40, 103, 0x72, 2534}, + /*(5505) VCVTNE2PS2BF16*/ { 54, 1, 0x72, 2528}, + /*(5506) VCVTNE2PS2BF16*/ { 40, 103, 0x72, 2534}, + /*(5507) VCVTNEPS2BF16*/ { 61, 1, 0x72, 2538}, + /*(5508) VCVTNEPS2BF16*/ { 62, 103, 0x72, 2547}, + /*(5509) VCVTNEPS2BF16*/ { 61, 1, 0x72, 2538}, + /*(5510) VCVTNEPS2BF16*/ { 62, 103, 0x72, 2547}, + /*(5511) VCVTNEPS2BF16*/ { 61, 1, 0x72, 2538}, + /*(5512) VCVTNEPS2BF16*/ { 62, 103, 0x72, 2547}, + /*(5513) VDPBF16PS*/ { 54, 1, 0x52, 2554}, + /*(5514) VDPBF16PS*/ { 40, 103, 0x52, 2560}, + /*(5515) VDPBF16PS*/ { 54, 1, 0x52, 2554}, + /*(5516) VDPBF16PS*/ { 40, 103, 0x52, 2560}, + /*(5517) VDPBF16PS*/ { 54, 1, 0x52, 2554}, + /*(5518) VDPBF16PS*/ { 40, 103, 0x52, 2560}, + /*(5519) VEXP2PD*/ { 61, 1, 0xc8, 1499}, + /*(5520) VEXP2PD*/ { 61, 119, 0xc8, 2564}, + /*(5521) VEXP2PD*/ { 62, 102, 0xc8, 1491}, + /*(5522) VEXP2PS*/ { 61, 1, 0xc8, 1427}, + /*(5523) VEXP2PS*/ { 61, 119, 0xc8, 2025}, + /*(5524) VEXP2PS*/ { 62, 103, 0xc8, 1419}, + /*(5525) VGATHERPF0DPD*/ { 109, 160, 0xc6, 2573}, + /*(5526) VGATHERPF0DPS*/ { 109, 163, 0xc6, 2584}, + /*(5527) VGATHERPF0QPD*/ { 109, 166, 0xc7, 2573}, + /*(5528) VGATHERPF0QPS*/ { 109, 163, 0xc7, 2584}, + /*(5529) VGATHERPF1DPD*/ { 109, 160, 0xc6, 2595}, + /*(5530) VGATHERPF1DPS*/ { 109, 163, 0xc6, 2606}, + /*(5531) VGATHERPF1QPD*/ { 109, 166, 0xc7, 2595}, + /*(5532) VGATHERPF1QPS*/ { 109, 163, 0xc7, 2606}, + /*(5533) VRCP28PD*/ { 61, 1, 0xca, 1499}, + /*(5534) VRCP28PD*/ { 61, 119, 0xca, 2564}, + /*(5535) VRCP28PD*/ { 62, 102, 0xca, 1491}, + /*(5536) VRCP28PS*/ { 61, 1, 0xca, 1427}, + /*(5537) VRCP28PS*/ { 61, 119, 0xca, 2025}, + /*(5538) VRCP28PS*/ { 62, 103, 0xca, 1419}, + /*(5539) VRCP28SD*/ { 54, 1, 0xcb, 1362}, + /*(5540) VRCP28SD*/ { 54, 114, 0xcb, 2048}, + /*(5541) VRCP28SD*/ { 55, 105, 0xcb, 876}, + /*(5542) VRCP28SS*/ { 54, 1, 0xcb, 1377}, + /*(5543) VRCP28SS*/ { 54, 114, 0xcb, 2054}, + /*(5544) VRCP28SS*/ { 55, 106, 0xcb, 2019}, + /*(5545) VRSQRT28PD*/ { 61, 1, 0xcc, 1499}, + /*(5546) VRSQRT28PD*/ { 61, 119, 0xcc, 2564}, + /*(5547) VRSQRT28PD*/ { 62, 102, 0xcc, 1491}, + /*(5548) VRSQRT28PS*/ { 61, 1, 0xcc, 1427}, + /*(5549) VRSQRT28PS*/ { 61, 119, 0xcc, 2025}, + /*(5550) VRSQRT28PS*/ { 62, 103, 0xcc, 1419}, + /*(5551) VRSQRT28SD*/ { 54, 1, 0xcd, 1362}, + /*(5552) VRSQRT28SD*/ { 54, 114, 0xcd, 2048}, + /*(5553) VRSQRT28SD*/ { 55, 105, 0xcd, 876}, + /*(5554) VRSQRT28SS*/ { 54, 1, 0xcd, 1377}, + /*(5555) VRSQRT28SS*/ { 54, 114, 0xcd, 2054}, + /*(5556) VRSQRT28SS*/ { 55, 106, 0xcd, 2019}, + /*(5557) VSCATTERPF0DPD*/ { 109, 160, 0xc6, 2617}, + /*(5558) VSCATTERPF0DPS*/ { 109, 163, 0xc6, 2628}, + /*(5559) VSCATTERPF0QPD*/ { 109, 166, 0xc7, 2617}, + /*(5560) VSCATTERPF0QPS*/ { 109, 163, 0xc7, 2628}, + /*(5561) VSCATTERPF1DPD*/ { 109, 160, 0xc6, 2639}, + /*(5562) VSCATTERPF1DPS*/ { 109, 163, 0xc6, 2650}, + /*(5563) VSCATTERPF1QPD*/ { 109, 166, 0xc7, 2639}, + /*(5564) VSCATTERPF1QPS*/ { 109, 163, 0xc7, 2650}, + /*(5565) PREFETCHWT1*/ { 0, 18, 0xd, 9}, + /*(5566) V4FMADDPS*/ { 55, 172, 0x9a, 2661}, + /*(5567) V4FMADDSS*/ { 55, 172, 0x9b, 2661}, + /*(5568) V4FNMADDPS*/ { 55, 172, 0xaa, 2661}, + /*(5569) V4FNMADDSS*/ { 55, 172, 0xab, 2661}, + /*(5570) VP4DPWSSD*/ { 55, 172, 0x52, 2661}, + /*(5571) VP4DPWSSDS*/ { 55, 172, 0x53, 2661}, + /*(5572) VPOPCNTD*/ { 61, 1, 0x55, 1427}, + /*(5573) VPOPCNTD*/ { 62, 103, 0x55, 1419}, + /*(5574) VPOPCNTD*/ { 61, 1, 0x55, 1427}, + /*(5575) VPOPCNTD*/ { 62, 103, 0x55, 1419}, + /*(5576) VPOPCNTD*/ { 61, 1, 0x55, 1427}, + /*(5577) VPOPCNTD*/ { 62, 103, 0x55, 1419}, + /*(5578) VPOPCNTQ*/ { 61, 1, 0x55, 1499}, + /*(5579) VPOPCNTQ*/ { 62, 102, 0x55, 1491}, + /*(5580) VPOPCNTQ*/ { 61, 1, 0x55, 1499}, + /*(5581) VPOPCNTQ*/ { 62, 102, 0x55, 1491}, + /*(5582) VPOPCNTQ*/ { 61, 1, 0x55, 1499}, + /*(5583) VPOPCNTQ*/ { 62, 102, 0x55, 1491}, + /*(5584) VALIGND*/ { 54, 10, 0x3, 2666}, + /*(5585) VALIGND*/ { 40, 109, 0x3, 1028}, + /*(5586) VALIGND*/ { 54, 10, 0x3, 2666}, + /*(5587) VALIGND*/ { 40, 109, 0x3, 1028}, + /*(5588) VALIGND*/ { 54, 10, 0x3, 2666}, + /*(5589) VALIGND*/ { 40, 109, 0x3, 1028}, + /*(5590) VALIGNQ*/ { 54, 10, 0x3, 2672}, + /*(5591) VALIGNQ*/ { 40, 108, 0x3, 587}, + /*(5592) VALIGNQ*/ { 54, 10, 0x3, 2672}, + /*(5593) VALIGNQ*/ { 40, 108, 0x3, 587}, + /*(5594) VALIGNQ*/ { 54, 10, 0x3, 2672}, + /*(5595) VALIGNQ*/ { 40, 108, 0x3, 587}, + /*(5596) VBLENDMPD*/ { 54, 1, 0x65, 1362}, + /*(5597) VBLENDMPD*/ { 40, 102, 0x65, 877}, + /*(5598) VBLENDMPD*/ { 54, 1, 0x65, 1362}, + /*(5599) VBLENDMPD*/ { 40, 102, 0x65, 877}, + /*(5600) VBLENDMPD*/ { 54, 1, 0x65, 1362}, + /*(5601) VBLENDMPD*/ { 40, 102, 0x65, 877}, + /*(5602) VBLENDMPS*/ { 54, 1, 0x65, 1377}, + /*(5603) VBLENDMPS*/ { 40, 103, 0x65, 1383}, + /*(5604) VBLENDMPS*/ { 54, 1, 0x65, 1377}, + /*(5605) VBLENDMPS*/ { 40, 103, 0x65, 1383}, + /*(5606) VBLENDMPS*/ { 54, 1, 0x65, 1377}, + /*(5607) VBLENDMPS*/ { 40, 103, 0x65, 1383}, + /*(5608) VBROADCASTF32X4*/ { 76, 173, 0x1a, 2678}, + /*(5609) VBROADCASTF32X4*/ { 76, 173, 0x1a, 2687}, + /*(5610) VBROADCASTF64X4*/ { 76, 174, 0x1b, 2696}, + /*(5611) VBROADCASTI32X4*/ { 76, 173, 0x5a, 2678}, + /*(5612) VBROADCASTI32X4*/ { 76, 173, 0x5a, 2687}, + /*(5613) VBROADCASTI64X4*/ { 76, 174, 0x5b, 2696}, + /*(5614) VCOMPRESSPD*/ { 81, 175, 0x8a, 2705}, + /*(5615) VCOMPRESSPD*/ { 61, 1, 0x8a, 1499}, + /*(5616) VCOMPRESSPD*/ { 81, 175, 0x8a, 2697}, + /*(5617) VCOMPRESSPD*/ { 61, 1, 0x8a, 1499}, + /*(5618) VCOMPRESSPD*/ { 81, 175, 0x8a, 2697}, + /*(5619) VCOMPRESSPD*/ { 61, 1, 0x8a, 1499}, + /*(5620) VCOMPRESSPS*/ { 81, 176, 0x8a, 2714}, + /*(5621) VCOMPRESSPS*/ { 61, 1, 0x8a, 1427}, + /*(5622) VCOMPRESSPS*/ { 81, 176, 0x8a, 2714}, + /*(5623) VCOMPRESSPS*/ { 61, 1, 0x8a, 1427}, + /*(5624) VCOMPRESSPS*/ { 81, 176, 0x8a, 2714}, + /*(5625) VCOMPRESSPS*/ { 61, 1, 0x8a, 1427}, + /*(5626) VCVTPD2UDQ*/ { 61, 1, 0x79, 2723}, + /*(5627) VCVTPD2UDQ*/ { 61, 101, 0x79, 2732}, + /*(5628) VCVTPD2UDQ*/ { 62, 102, 0x79, 2741}, + /*(5629) VCVTPD2UDQ*/ { 61, 1, 0x79, 2723}, + /*(5630) VCVTPD2UDQ*/ { 62, 102, 0x79, 2741}, + /*(5631) VCVTPD2UDQ*/ { 61, 1, 0x79, 2723}, + /*(5632) VCVTPD2UDQ*/ { 62, 102, 0x79, 2741}, + /*(5633) VCVTPS2UDQ*/ { 61, 1, 0x79, 824}, + /*(5634) VCVTPS2UDQ*/ { 61, 101, 0x79, 833}, + /*(5635) VCVTPS2UDQ*/ { 62, 103, 0x79, 842}, + /*(5636) VCVTPS2UDQ*/ { 61, 1, 0x79, 824}, + /*(5637) VCVTPS2UDQ*/ { 62, 103, 0x79, 842}, + /*(5638) VCVTPS2UDQ*/ { 61, 1, 0x79, 824}, + /*(5639) VCVTPS2UDQ*/ { 62, 103, 0x79, 842}, + /*(5640) VCVTSD2USI*/ { 63, 113, 0x79, 961}, + /*(5641) VCVTSD2USI*/ { 64, 113, 0x79, 971}, + /*(5642) VCVTSD2USI*/ { 63, 104, 0x79, 983}, + /*(5643) VCVTSD2USI*/ { 64, 104, 0x79, 993}, + /*(5644) VCVTSD2USI*/ { 65, 120, 0x79, 1005}, + /*(5645) VCVTSD2USI*/ { 66, 120, 0x79, 1014}, + /*(5646) VCVTSD2USI*/ { 64, 113, 0x79, 1025}, + /*(5647) VCVTSD2USI*/ { 64, 104, 0x79, 1037}, + /*(5648) VCVTSD2USI*/ { 66, 120, 0x79, 1049}, + /*(5649) VCVTSS2USI*/ { 63, 113, 0x79, 1086}, + /*(5650) VCVTSS2USI*/ { 64, 113, 0x79, 1096}, + /*(5651) VCVTSS2USI*/ { 63, 104, 0x79, 1108}, + /*(5652) VCVTSS2USI*/ { 64, 104, 0x79, 1118}, + /*(5653) VCVTSS2USI*/ { 65, 121, 0x79, 1130}, + /*(5654) VCVTSS2USI*/ { 66, 121, 0x79, 1139}, + /*(5655) VCVTSS2USI*/ { 64, 113, 0x79, 1150}, + /*(5656) VCVTSS2USI*/ { 64, 104, 0x79, 1162}, + /*(5657) VCVTSS2USI*/ { 66, 121, 0x79, 1174}, + /*(5658) VCVTTPD2UDQ*/ { 61, 1, 0x78, 2723}, + /*(5659) VCVTTPD2UDQ*/ { 61, 119, 0x78, 2732}, + /*(5660) VCVTTPD2UDQ*/ { 62, 102, 0x78, 2741}, + /*(5661) VCVTTPD2UDQ*/ { 61, 1, 0x78, 2723}, + /*(5662) VCVTTPD2UDQ*/ { 62, 102, 0x78, 2741}, + /*(5663) VCVTTPD2UDQ*/ { 61, 1, 0x78, 2723}, + /*(5664) VCVTTPD2UDQ*/ { 62, 102, 0x78, 2741}, + /*(5665) VCVTTPS2UDQ*/ { 61, 1, 0x78, 824}, + /*(5666) VCVTTPS2UDQ*/ { 61, 119, 0x78, 833}, + /*(5667) VCVTTPS2UDQ*/ { 62, 103, 0x78, 842}, + /*(5668) VCVTTPS2UDQ*/ { 61, 1, 0x78, 824}, + /*(5669) VCVTTPS2UDQ*/ { 62, 103, 0x78, 842}, + /*(5670) VCVTTPS2UDQ*/ { 61, 1, 0x78, 824}, + /*(5671) VCVTTPS2UDQ*/ { 62, 103, 0x78, 842}, + /*(5672) VCVTTSD2USI*/ { 63, 113, 0x78, 961}, + /*(5673) VCVTTSD2USI*/ { 64, 113, 0x78, 971}, + /*(5674) VCVTTSD2USI*/ { 63, 114, 0x78, 983}, + /*(5675) VCVTTSD2USI*/ { 64, 114, 0x78, 993}, + /*(5676) VCVTTSD2USI*/ { 65, 120, 0x78, 1005}, + /*(5677) VCVTTSD2USI*/ { 66, 120, 0x78, 1014}, + /*(5678) VCVTTSD2USI*/ { 64, 113, 0x78, 1025}, + /*(5679) VCVTTSD2USI*/ { 64, 114, 0x78, 1037}, + /*(5680) VCVTTSD2USI*/ { 66, 120, 0x78, 1049}, + /*(5681) VCVTTSS2USI*/ { 63, 113, 0x78, 1086}, + /*(5682) VCVTTSS2USI*/ { 64, 113, 0x78, 1096}, + /*(5683) VCVTTSS2USI*/ { 63, 114, 0x78, 1108}, + /*(5684) VCVTTSS2USI*/ { 64, 114, 0x78, 1118}, + /*(5685) VCVTTSS2USI*/ { 65, 121, 0x78, 1130}, + /*(5686) VCVTTSS2USI*/ { 66, 121, 0x78, 1139}, + /*(5687) VCVTTSS2USI*/ { 64, 113, 0x78, 1150}, + /*(5688) VCVTTSS2USI*/ { 64, 114, 0x78, 1162}, + /*(5689) VCVTTSS2USI*/ { 66, 121, 0x78, 1174}, + /*(5690) VCVTUDQ2PD*/ { 61, 1, 0x7a, 799}, + /*(5691) VCVTUDQ2PD*/ { 61, 117, 0x7a, 808}, + /*(5692) VCVTUDQ2PD*/ { 62, 118, 0x7a, 817}, + /*(5693) VCVTUDQ2PD*/ { 61, 1, 0x7a, 799}, + /*(5694) VCVTUDQ2PD*/ { 62, 118, 0x7a, 817}, + /*(5695) VCVTUDQ2PD*/ { 61, 1, 0x7a, 799}, + /*(5696) VCVTUDQ2PD*/ { 62, 118, 0x7a, 817}, + /*(5697) VCVTUDQ2PS*/ { 61, 1, 0x7a, 2748}, + /*(5698) VCVTUDQ2PS*/ { 61, 101, 0x7a, 2757}, + /*(5699) VCVTUDQ2PS*/ { 62, 103, 0x7a, 1006}, + /*(5700) VCVTUDQ2PS*/ { 61, 1, 0x7a, 2748}, + /*(5701) VCVTUDQ2PS*/ { 62, 103, 0x7a, 1006}, + /*(5702) VCVTUDQ2PS*/ { 61, 1, 0x7a, 2748}, + /*(5703) VCVTUDQ2PS*/ { 62, 103, 0x7a, 1006}, + /*(5704) VCVTUSI2SD*/ { 67, 113, 0x7b, 1195}, + /*(5705) VCVTUSI2SD*/ { 68, 113, 0x7b, 1201}, + /*(5706) VCVTUSI2SD*/ { 69, 122, 0x7b, 1208}, + /*(5707) VCVTUSI2SD*/ { 70, 122, 0x7b, 1214}, + /*(5708) VCVTUSI2SD*/ { 71, 113, 0x7b, 1221}, + /*(5709) VCVTUSI2SD*/ { 71, 104, 0x7b, 1229}, + /*(5710) VCVTUSI2SD*/ { 70, 123, 0x7b, 1237}, + /*(5711) VCVTUSI2SS*/ { 72, 113, 0x7b, 1244}, + /*(5712) VCVTUSI2SS*/ { 71, 113, 0x7b, 1251}, + /*(5713) VCVTUSI2SS*/ { 72, 104, 0x7b, 1259}, + /*(5714) VCVTUSI2SS*/ { 71, 104, 0x7b, 1266}, + /*(5715) VCVTUSI2SS*/ { 69, 122, 0x7b, 650}, + /*(5716) VCVTUSI2SS*/ { 70, 122, 0x7b, 1274}, + /*(5717) VCVTUSI2SS*/ { 71, 113, 0x7b, 1281}, + /*(5718) VCVTUSI2SS*/ { 71, 104, 0x7b, 1289}, + /*(5719) VCVTUSI2SS*/ { 70, 123, 0x7b, 1297}, + /*(5720) VEXPANDPD*/ { 80, 175, 0x88, 1490}, + /*(5721) VEXPANDPD*/ { 61, 1, 0x88, 1499}, + /*(5722) VEXPANDPD*/ { 80, 175, 0x88, 1490}, + /*(5723) VEXPANDPD*/ { 61, 1, 0x88, 1499}, + /*(5724) VEXPANDPD*/ { 80, 175, 0x88, 1490}, + /*(5725) VEXPANDPD*/ { 61, 1, 0x88, 1499}, + /*(5726) VEXPANDPS*/ { 80, 176, 0x88, 1418}, + /*(5727) VEXPANDPS*/ { 61, 1, 0x88, 1427}, + /*(5728) VEXPANDPS*/ { 80, 176, 0x88, 1418}, + /*(5729) VEXPANDPS*/ { 61, 1, 0x88, 1427}, + /*(5730) VEXPANDPS*/ { 80, 176, 0x88, 1418}, + /*(5731) VEXPANDPS*/ { 61, 1, 0x88, 1427}, + /*(5732) VEXTRACTF32X4*/ { 61, 10, 0x19, 1368}, + /*(5733) VEXTRACTF32X4*/ { 81, 177, 0x19, 1333}, + /*(5734) VEXTRACTF32X4*/ { 61, 10, 0x19, 1368}, + /*(5735) VEXTRACTF32X4*/ { 81, 177, 0x19, 1333}, + /*(5736) VEXTRACTF64X4*/ { 61, 10, 0x1b, 1353}, + /*(5737) VEXTRACTF64X4*/ { 81, 178, 0x1b, 715}, + /*(5738) VEXTRACTI32X4*/ { 61, 10, 0x39, 1368}, + /*(5739) VEXTRACTI32X4*/ { 81, 177, 0x39, 1333}, + /*(5740) VEXTRACTI32X4*/ { 61, 10, 0x39, 1368}, + /*(5741) VEXTRACTI32X4*/ { 81, 177, 0x39, 1333}, + /*(5742) VEXTRACTI64X4*/ { 61, 10, 0x3b, 1353}, + /*(5743) VEXTRACTI64X4*/ { 81, 178, 0x3b, 715}, + /*(5744) VFIXUPIMMPD*/ { 54, 10, 0x54, 2672}, + /*(5745) VFIXUPIMMPD*/ { 54, 107, 0x54, 2766}, + /*(5746) VFIXUPIMMPD*/ { 40, 108, 0x54, 587}, + /*(5747) VFIXUPIMMPD*/ { 54, 10, 0x54, 2672}, + /*(5748) VFIXUPIMMPD*/ { 40, 108, 0x54, 587}, + /*(5749) VFIXUPIMMPD*/ { 54, 10, 0x54, 2672}, + /*(5750) VFIXUPIMMPD*/ { 40, 108, 0x54, 587}, + /*(5751) VFIXUPIMMPS*/ { 54, 10, 0x54, 2666}, + /*(5752) VFIXUPIMMPS*/ { 54, 107, 0x54, 2772}, + /*(5753) VFIXUPIMMPS*/ { 40, 109, 0x54, 1028}, + /*(5754) VFIXUPIMMPS*/ { 54, 10, 0x54, 2666}, + /*(5755) VFIXUPIMMPS*/ { 40, 109, 0x54, 1028}, + /*(5756) VFIXUPIMMPS*/ { 54, 10, 0x54, 2666}, + /*(5757) VFIXUPIMMPS*/ { 40, 109, 0x54, 1028}, + /*(5758) VFIXUPIMMSD*/ { 54, 10, 0x55, 2672}, + /*(5759) VFIXUPIMMSD*/ { 54, 110, 0x55, 2766}, + /*(5760) VFIXUPIMMSD*/ { 55, 111, 0x55, 1989}, + /*(5761) VFIXUPIMMSS*/ { 54, 10, 0x55, 2666}, + /*(5762) VFIXUPIMMSS*/ { 54, 110, 0x55, 2772}, + /*(5763) VFIXUPIMMSS*/ { 55, 112, 0x55, 1027}, + /*(5764) VGETEXPPD*/ { 61, 1, 0x42, 1499}, + /*(5765) VGETEXPPD*/ { 61, 119, 0x42, 2564}, + /*(5766) VGETEXPPD*/ { 62, 102, 0x42, 1491}, + /*(5767) VGETEXPPD*/ { 61, 1, 0x42, 1499}, + /*(5768) VGETEXPPD*/ { 62, 102, 0x42, 1491}, + /*(5769) VGETEXPPD*/ { 61, 1, 0x42, 1499}, + /*(5770) VGETEXPPD*/ { 62, 102, 0x42, 1491}, + /*(5771) VGETEXPPS*/ { 61, 1, 0x42, 1427}, + /*(5772) VGETEXPPS*/ { 61, 119, 0x42, 2025}, + /*(5773) VGETEXPPS*/ { 62, 103, 0x42, 1419}, + /*(5774) VGETEXPPS*/ { 61, 1, 0x42, 1427}, + /*(5775) VGETEXPPS*/ { 62, 103, 0x42, 1419}, + /*(5776) VGETEXPPS*/ { 61, 1, 0x42, 1427}, + /*(5777) VGETEXPPS*/ { 62, 103, 0x42, 1419}, + /*(5778) VGETEXPSD*/ { 54, 1, 0x43, 1362}, + /*(5779) VGETEXPSD*/ { 54, 114, 0x43, 2048}, + /*(5780) VGETEXPSD*/ { 55, 105, 0x43, 876}, + /*(5781) VGETEXPSS*/ { 54, 1, 0x43, 1377}, + /*(5782) VGETEXPSS*/ { 54, 114, 0x43, 2054}, + /*(5783) VGETEXPSS*/ { 55, 106, 0x43, 2019}, + /*(5784) VGETMANTPD*/ { 61, 10, 0x26, 1353}, + /*(5785) VGETMANTPD*/ { 61, 107, 0x26, 2778}, + /*(5786) VGETMANTPD*/ { 62, 108, 0x26, 716}, + /*(5787) VGETMANTPD*/ { 61, 10, 0x26, 1353}, + /*(5788) VGETMANTPD*/ { 62, 108, 0x26, 716}, + /*(5789) VGETMANTPD*/ { 61, 10, 0x26, 1353}, + /*(5790) VGETMANTPD*/ { 62, 108, 0x26, 716}, + /*(5791) VGETMANTPS*/ { 61, 10, 0x26, 1368}, + /*(5792) VGETMANTPS*/ { 61, 107, 0x26, 2034}, + /*(5793) VGETMANTPS*/ { 62, 109, 0x26, 912}, + /*(5794) VGETMANTPS*/ { 61, 10, 0x26, 1368}, + /*(5795) VGETMANTPS*/ { 62, 109, 0x26, 912}, + /*(5796) VGETMANTPS*/ { 61, 10, 0x26, 1368}, + /*(5797) VGETMANTPS*/ { 62, 109, 0x26, 912}, + /*(5798) VGETMANTSD*/ { 54, 10, 0x27, 2672}, + /*(5799) VGETMANTSD*/ { 54, 110, 0x27, 2766}, + /*(5800) VGETMANTSD*/ { 55, 111, 0x27, 1989}, + /*(5801) VGETMANTSS*/ { 54, 10, 0x27, 2666}, + /*(5802) VGETMANTSS*/ { 54, 110, 0x27, 2772}, + /*(5803) VGETMANTSS*/ { 55, 112, 0x27, 1027}, + /*(5804) VINSERTF32X4*/ { 54, 10, 0x18, 2666}, + /*(5805) VINSERTF32X4*/ { 55, 177, 0x18, 1027}, + /*(5806) VINSERTF32X4*/ { 54, 10, 0x18, 2666}, + /*(5807) VINSERTF32X4*/ { 55, 177, 0x18, 1027}, + /*(5808) VINSERTF64X4*/ { 54, 10, 0x1a, 2672}, + /*(5809) VINSERTF64X4*/ { 55, 178, 0x1a, 1989}, + /*(5810) VINSERTI32X4*/ { 54, 10, 0x38, 2666}, + /*(5811) VINSERTI32X4*/ { 55, 177, 0x38, 1027}, + /*(5812) VINSERTI32X4*/ { 54, 10, 0x38, 2666}, + /*(5813) VINSERTI32X4*/ { 55, 177, 0x38, 1027}, + /*(5814) VINSERTI64X4*/ { 54, 10, 0x3a, 2672}, + /*(5815) VINSERTI64X4*/ { 55, 178, 0x3a, 1989}, + /*(5816) VMOVDQA32*/ { 61, 1, 0x6f, 910}, + /*(5817) VMOVDQA32*/ { 80, 129, 0x6f, 1639}, + /*(5818) VMOVDQA32*/ { 61, 1, 0x7f, 910}, + /*(5819) VMOVDQA32*/ { 81, 129, 0x7f, 1639}, + /*(5820) VMOVDQA32*/ { 61, 1, 0x6f, 910}, + /*(5821) VMOVDQA32*/ { 80, 129, 0x6f, 1639}, + /*(5822) VMOVDQA32*/ { 61, 1, 0x7f, 910}, + /*(5823) VMOVDQA32*/ { 81, 129, 0x7f, 1639}, + /*(5824) VMOVDQA32*/ { 61, 1, 0x6f, 910}, + /*(5825) VMOVDQA32*/ { 80, 129, 0x6f, 1639}, + /*(5826) VMOVDQA32*/ { 61, 1, 0x7f, 910}, + /*(5827) VMOVDQA32*/ { 81, 129, 0x7f, 1639}, + /*(5828) VMOVDQA64*/ { 61, 1, 0x6f, 885}, + /*(5829) VMOVDQA64*/ { 80, 128, 0x6f, 1571}, + /*(5830) VMOVDQA64*/ { 61, 1, 0x7f, 885}, + /*(5831) VMOVDQA64*/ { 81, 128, 0x7f, 1571}, + /*(5832) VMOVDQA64*/ { 61, 1, 0x6f, 885}, + /*(5833) VMOVDQA64*/ { 80, 128, 0x6f, 1571}, + /*(5834) VMOVDQA64*/ { 61, 1, 0x7f, 885}, + /*(5835) VMOVDQA64*/ { 81, 128, 0x7f, 1571}, + /*(5836) VMOVDQA64*/ { 61, 1, 0x6f, 885}, + /*(5837) VMOVDQA64*/ { 80, 128, 0x6f, 1571}, + /*(5838) VMOVDQA64*/ { 61, 1, 0x7f, 885}, + /*(5839) VMOVDQA64*/ { 81, 128, 0x7f, 1571}, + /*(5840) VMOVDQU32*/ { 61, 1, 0x6f, 799}, + /*(5841) VMOVDQU32*/ { 80, 129, 0x6f, 1130}, + /*(5842) VMOVDQU32*/ { 61, 1, 0x7f, 799}, + /*(5843) VMOVDQU32*/ { 81, 129, 0x7f, 1130}, + /*(5844) VMOVDQU32*/ { 61, 1, 0x6f, 799}, + /*(5845) VMOVDQU32*/ { 80, 129, 0x6f, 1130}, + /*(5846) VMOVDQU32*/ { 61, 1, 0x7f, 799}, + /*(5847) VMOVDQU32*/ { 81, 129, 0x7f, 1130}, + /*(5848) VMOVDQU32*/ { 61, 1, 0x6f, 799}, + /*(5849) VMOVDQU32*/ { 80, 129, 0x6f, 1130}, + /*(5850) VMOVDQU32*/ { 61, 1, 0x7f, 799}, + /*(5851) VMOVDQU32*/ { 81, 129, 0x7f, 1130}, + /*(5852) VMOVDQU64*/ { 61, 1, 0x6f, 2787}, + /*(5853) VMOVDQU64*/ { 80, 128, 0x6f, 2796}, + /*(5854) VMOVDQU64*/ { 61, 1, 0x7f, 2787}, + /*(5855) VMOVDQU64*/ { 81, 128, 0x7f, 2804}, + /*(5856) VMOVDQU64*/ { 61, 1, 0x6f, 2787}, + /*(5857) VMOVDQU64*/ { 80, 128, 0x6f, 2796}, + /*(5858) VMOVDQU64*/ { 61, 1, 0x7f, 2787}, + /*(5859) VMOVDQU64*/ { 81, 128, 0x7f, 2796}, + /*(5860) VMOVDQU64*/ { 61, 1, 0x6f, 2787}, + /*(5861) VMOVDQU64*/ { 80, 128, 0x6f, 2796}, + /*(5862) VMOVDQU64*/ { 61, 1, 0x7f, 2787}, + /*(5863) VMOVDQU64*/ { 81, 128, 0x7f, 2796}, + /*(5864) VPABSQ*/ { 61, 1, 0x1f, 1499}, + /*(5865) VPABSQ*/ { 62, 102, 0x1f, 1491}, + /*(5866) VPABSQ*/ { 61, 1, 0x1f, 1499}, + /*(5867) VPABSQ*/ { 62, 102, 0x1f, 1491}, + /*(5868) VPABSQ*/ { 61, 1, 0x1f, 1499}, + /*(5869) VPABSQ*/ { 62, 102, 0x1f, 1491}, + /*(5870) VPANDD*/ { 54, 1, 0xdb, 1731}, + /*(5871) VPANDD*/ { 40, 103, 0xdb, 121}, + /*(5872) VPANDD*/ { 54, 1, 0xdb, 1731}, + /*(5873) VPANDD*/ { 40, 103, 0xdb, 121}, + /*(5874) VPANDD*/ { 54, 1, 0xdb, 1731}, + /*(5875) VPANDD*/ { 40, 103, 0xdb, 121}, + /*(5876) VPANDND*/ { 54, 1, 0xdf, 1731}, + /*(5877) VPANDND*/ { 40, 103, 0xdf, 121}, + /*(5878) VPANDND*/ { 54, 1, 0xdf, 1731}, + /*(5879) VPANDND*/ { 40, 103, 0xdf, 121}, + /*(5880) VPANDND*/ { 54, 1, 0xdf, 1731}, + /*(5881) VPANDND*/ { 40, 103, 0xdf, 121}, + /*(5882) VPANDNQ*/ { 54, 1, 0xdf, 585}, + /*(5883) VPANDNQ*/ { 40, 102, 0xdf, 597}, + /*(5884) VPANDNQ*/ { 54, 1, 0xdf, 585}, + /*(5885) VPANDNQ*/ { 40, 102, 0xdf, 597}, + /*(5886) VPANDNQ*/ { 54, 1, 0xdf, 585}, + /*(5887) VPANDNQ*/ { 40, 102, 0xdf, 597}, + /*(5888) VPANDQ*/ { 54, 1, 0xdb, 585}, + /*(5889) VPANDQ*/ { 40, 102, 0xdb, 597}, + /*(5890) VPANDQ*/ { 54, 1, 0xdb, 585}, + /*(5891) VPANDQ*/ { 40, 102, 0xdb, 597}, + /*(5892) VPANDQ*/ { 54, 1, 0xdb, 585}, + /*(5893) VPANDQ*/ { 40, 102, 0xdb, 597}, + /*(5894) VPBLENDMD*/ { 54, 1, 0x64, 1377}, + /*(5895) VPBLENDMD*/ { 40, 103, 0x64, 1383}, + /*(5896) VPBLENDMD*/ { 54, 1, 0x64, 1377}, + /*(5897) VPBLENDMD*/ { 40, 103, 0x64, 1383}, + /*(5898) VPBLENDMD*/ { 54, 1, 0x64, 1377}, + /*(5899) VPBLENDMD*/ { 40, 103, 0x64, 1383}, + /*(5900) VPBLENDMQ*/ { 54, 1, 0x64, 1362}, + /*(5901) VPBLENDMQ*/ { 40, 102, 0x64, 877}, + /*(5902) VPBLENDMQ*/ { 54, 1, 0x64, 1362}, + /*(5903) VPBLENDMQ*/ { 40, 102, 0x64, 877}, + /*(5904) VPBLENDMQ*/ { 54, 1, 0x64, 1362}, + /*(5905) VPBLENDMQ*/ { 40, 102, 0x64, 877}, + /*(5906) VPCMPD*/ { 56, 10, 0x1f, 2666}, + /*(5907) VPCMPD*/ { 57, 109, 0x1f, 1548}, + /*(5908) VPCMPD*/ { 56, 10, 0x1f, 2666}, + /*(5909) VPCMPD*/ { 57, 109, 0x1f, 1548}, + /*(5910) VPCMPD*/ { 56, 10, 0x1f, 2666}, + /*(5911) VPCMPD*/ { 57, 109, 0x1f, 1548}, + /*(5912) VPCMPQ*/ { 56, 10, 0x1f, 2813}, + /*(5913) VPCMPQ*/ { 57, 108, 0x1f, 657}, + /*(5914) VPCMPQ*/ { 56, 10, 0x1f, 2813}, + /*(5915) VPCMPQ*/ { 57, 108, 0x1f, 657}, + /*(5916) VPCMPQ*/ { 56, 10, 0x1f, 2813}, + /*(5917) VPCMPQ*/ { 57, 108, 0x1f, 657}, + /*(5918) VPCMPUD*/ { 56, 10, 0x1e, 2666}, + /*(5919) VPCMPUD*/ { 57, 109, 0x1e, 1548}, + /*(5920) VPCMPUD*/ { 56, 10, 0x1e, 2666}, + /*(5921) VPCMPUD*/ { 57, 109, 0x1e, 1548}, + /*(5922) VPCMPUD*/ { 56, 10, 0x1e, 2666}, + /*(5923) VPCMPUD*/ { 57, 109, 0x1e, 1548}, + /*(5924) VPCMPUQ*/ { 56, 10, 0x1e, 2813}, + /*(5925) VPCMPUQ*/ { 57, 108, 0x1e, 657}, + /*(5926) VPCMPUQ*/ { 56, 10, 0x1e, 2813}, + /*(5927) VPCMPUQ*/ { 57, 108, 0x1e, 657}, + /*(5928) VPCMPUQ*/ { 56, 10, 0x1e, 2813}, + /*(5929) VPCMPUQ*/ { 57, 108, 0x1e, 657}, + /*(5930) VPCOMPRESSD*/ { 81, 176, 0x8b, 2714}, + /*(5931) VPCOMPRESSD*/ { 61, 1, 0x8b, 1427}, + /*(5932) VPCOMPRESSD*/ { 81, 176, 0x8b, 2714}, + /*(5933) VPCOMPRESSD*/ { 61, 1, 0x8b, 1427}, + /*(5934) VPCOMPRESSD*/ { 81, 176, 0x8b, 2714}, + /*(5935) VPCOMPRESSD*/ { 61, 1, 0x8b, 1427}, + /*(5936) VPCOMPRESSQ*/ { 81, 175, 0x8b, 2697}, + /*(5937) VPCOMPRESSQ*/ { 61, 1, 0x8b, 1499}, + /*(5938) VPCOMPRESSQ*/ { 81, 175, 0x8b, 2697}, + /*(5939) VPCOMPRESSQ*/ { 61, 1, 0x8b, 1499}, + /*(5940) VPCOMPRESSQ*/ { 81, 175, 0x8b, 2697}, + /*(5941) VPCOMPRESSQ*/ { 61, 1, 0x8b, 1499}, + /*(5942) VPERMI2D*/ { 54, 1, 0x76, 1377}, + /*(5943) VPERMI2D*/ { 40, 103, 0x76, 1383}, + /*(5944) VPERMI2D*/ { 54, 1, 0x76, 1377}, + /*(5945) VPERMI2D*/ { 40, 103, 0x76, 1383}, + /*(5946) VPERMI2D*/ { 54, 1, 0x76, 1377}, + /*(5947) VPERMI2D*/ { 40, 103, 0x76, 1383}, + /*(5948) VPERMI2PD*/ { 54, 1, 0x77, 1362}, + /*(5949) VPERMI2PD*/ { 40, 102, 0x77, 877}, + /*(5950) VPERMI2PD*/ { 54, 1, 0x77, 1362}, + /*(5951) VPERMI2PD*/ { 40, 102, 0x77, 877}, + /*(5952) VPERMI2PD*/ { 54, 1, 0x77, 1362}, + /*(5953) VPERMI2PD*/ { 40, 102, 0x77, 877}, + /*(5954) VPERMI2PS*/ { 54, 1, 0x77, 1377}, + /*(5955) VPERMI2PS*/ { 40, 103, 0x77, 1383}, + /*(5956) VPERMI2PS*/ { 54, 1, 0x77, 1377}, + /*(5957) VPERMI2PS*/ { 40, 103, 0x77, 1383}, + /*(5958) VPERMI2PS*/ { 54, 1, 0x77, 1377}, + /*(5959) VPERMI2PS*/ { 40, 103, 0x77, 1383}, + /*(5960) VPERMI2Q*/ { 54, 1, 0x76, 1362}, + /*(5961) VPERMI2Q*/ { 40, 102, 0x76, 877}, + /*(5962) VPERMI2Q*/ { 54, 1, 0x76, 1362}, + /*(5963) VPERMI2Q*/ { 40, 102, 0x76, 877}, + /*(5964) VPERMI2Q*/ { 54, 1, 0x76, 1362}, + /*(5965) VPERMI2Q*/ { 40, 102, 0x76, 877}, + /*(5966) VPERMT2D*/ { 54, 1, 0x7e, 1377}, + /*(5967) VPERMT2D*/ { 40, 103, 0x7e, 1383}, + /*(5968) VPERMT2D*/ { 54, 1, 0x7e, 1377}, + /*(5969) VPERMT2D*/ { 40, 103, 0x7e, 1383}, + /*(5970) VPERMT2D*/ { 54, 1, 0x7e, 1377}, + /*(5971) VPERMT2D*/ { 40, 103, 0x7e, 1383}, + /*(5972) VPERMT2PD*/ { 54, 1, 0x7f, 1362}, + /*(5973) VPERMT2PD*/ { 40, 102, 0x7f, 877}, + /*(5974) VPERMT2PD*/ { 54, 1, 0x7f, 1362}, + /*(5975) VPERMT2PD*/ { 40, 102, 0x7f, 877}, + /*(5976) VPERMT2PD*/ { 54, 1, 0x7f, 1362}, + /*(5977) VPERMT2PD*/ { 40, 102, 0x7f, 877}, + /*(5978) VPERMT2PS*/ { 54, 1, 0x7f, 1377}, + /*(5979) VPERMT2PS*/ { 40, 103, 0x7f, 1383}, + /*(5980) VPERMT2PS*/ { 54, 1, 0x7f, 1377}, + /*(5981) VPERMT2PS*/ { 40, 103, 0x7f, 1383}, + /*(5982) VPERMT2PS*/ { 54, 1, 0x7f, 1377}, + /*(5983) VPERMT2PS*/ { 40, 103, 0x7f, 1383}, + /*(5984) VPERMT2Q*/ { 54, 1, 0x7e, 1362}, + /*(5985) VPERMT2Q*/ { 40, 102, 0x7e, 877}, + /*(5986) VPERMT2Q*/ { 54, 1, 0x7e, 1362}, + /*(5987) VPERMT2Q*/ { 40, 102, 0x7e, 877}, + /*(5988) VPERMT2Q*/ { 54, 1, 0x7e, 1362}, + /*(5989) VPERMT2Q*/ { 40, 102, 0x7e, 877}, + /*(5990) VPEXPANDD*/ { 80, 176, 0x89, 1418}, + /*(5991) VPEXPANDD*/ { 61, 1, 0x89, 1427}, + /*(5992) VPEXPANDD*/ { 80, 176, 0x89, 1418}, + /*(5993) VPEXPANDD*/ { 61, 1, 0x89, 1427}, + /*(5994) VPEXPANDD*/ { 80, 176, 0x89, 1418}, + /*(5995) VPEXPANDD*/ { 61, 1, 0x89, 1427}, + /*(5996) VPEXPANDQ*/ { 80, 175, 0x89, 1490}, + /*(5997) VPEXPANDQ*/ { 61, 1, 0x89, 1499}, + /*(5998) VPEXPANDQ*/ { 80, 175, 0x89, 1490}, + /*(5999) VPEXPANDQ*/ { 61, 1, 0x89, 1499}, + /*(6000) VPEXPANDQ*/ { 80, 175, 0x89, 1490}, + /*(6001) VPEXPANDQ*/ { 61, 1, 0x89, 1499}, + /*(6002) VPMAXSQ*/ { 54, 1, 0x3d, 1362}, + /*(6003) VPMAXSQ*/ { 40, 102, 0x3d, 877}, + /*(6004) VPMAXSQ*/ { 54, 1, 0x3d, 1362}, + /*(6005) VPMAXSQ*/ { 40, 102, 0x3d, 877}, + /*(6006) VPMAXSQ*/ { 54, 1, 0x3d, 1362}, + /*(6007) VPMAXSQ*/ { 40, 102, 0x3d, 877}, + /*(6008) VPMAXUQ*/ { 54, 1, 0x3f, 1362}, + /*(6009) VPMAXUQ*/ { 40, 102, 0x3f, 877}, + /*(6010) VPMAXUQ*/ { 54, 1, 0x3f, 1362}, + /*(6011) VPMAXUQ*/ { 40, 102, 0x3f, 877}, + /*(6012) VPMAXUQ*/ { 54, 1, 0x3f, 1362}, + /*(6013) VPMAXUQ*/ { 40, 102, 0x3f, 877}, + /*(6014) VPMINSQ*/ { 54, 1, 0x39, 1362}, + /*(6015) VPMINSQ*/ { 40, 102, 0x39, 877}, + /*(6016) VPMINSQ*/ { 54, 1, 0x39, 1362}, + /*(6017) VPMINSQ*/ { 40, 102, 0x39, 877}, + /*(6018) VPMINSQ*/ { 54, 1, 0x39, 1362}, + /*(6019) VPMINSQ*/ { 40, 102, 0x39, 877}, + /*(6020) VPMINUQ*/ { 54, 1, 0x3b, 1362}, + /*(6021) VPMINUQ*/ { 40, 102, 0x3b, 877}, + /*(6022) VPMINUQ*/ { 54, 1, 0x3b, 1362}, + /*(6023) VPMINUQ*/ { 40, 102, 0x3b, 877}, + /*(6024) VPMINUQ*/ { 54, 1, 0x3b, 1362}, + /*(6025) VPMINUQ*/ { 40, 102, 0x3b, 877}, + /*(6026) VPMOVDB*/ { 61, 1, 0x31, 2538}, + /*(6027) VPMOVDB*/ { 81, 145, 0x31, 2820}, + /*(6028) VPMOVDB*/ { 61, 1, 0x31, 2538}, + /*(6029) VPMOVDB*/ { 81, 145, 0x31, 2820}, + /*(6030) VPMOVDB*/ { 61, 1, 0x31, 2538}, + /*(6031) VPMOVDB*/ { 81, 145, 0x31, 2820}, + /*(6032) VPMOVDW*/ { 61, 1, 0x33, 2538}, + /*(6033) VPMOVDW*/ { 81, 147, 0x33, 2820}, + /*(6034) VPMOVDW*/ { 61, 1, 0x33, 2538}, + /*(6035) VPMOVDW*/ { 81, 147, 0x33, 2820}, + /*(6036) VPMOVDW*/ { 61, 1, 0x33, 2538}, + /*(6037) VPMOVDW*/ { 81, 147, 0x33, 2820}, + /*(6038) VPMOVQB*/ { 61, 1, 0x32, 2538}, + /*(6039) VPMOVQB*/ { 81, 146, 0x32, 2820}, + /*(6040) VPMOVQB*/ { 61, 1, 0x32, 2538}, + /*(6041) VPMOVQB*/ { 81, 146, 0x32, 2820}, + /*(6042) VPMOVQB*/ { 61, 1, 0x32, 2538}, + /*(6043) VPMOVQB*/ { 81, 146, 0x32, 2820}, + /*(6044) VPMOVQD*/ { 61, 1, 0x35, 2538}, + /*(6045) VPMOVQD*/ { 81, 149, 0x35, 2820}, + /*(6046) VPMOVQD*/ { 61, 1, 0x35, 2538}, + /*(6047) VPMOVQD*/ { 81, 149, 0x35, 2820}, + /*(6048) VPMOVQD*/ { 61, 1, 0x35, 2538}, + /*(6049) VPMOVQD*/ { 81, 149, 0x35, 2820}, + /*(6050) VPMOVQW*/ { 61, 1, 0x34, 2538}, + /*(6051) VPMOVQW*/ { 81, 148, 0x34, 2820}, + /*(6052) VPMOVQW*/ { 61, 1, 0x34, 2538}, + /*(6053) VPMOVQW*/ { 81, 148, 0x34, 2820}, + /*(6054) VPMOVQW*/ { 61, 1, 0x34, 2538}, + /*(6055) VPMOVQW*/ { 81, 148, 0x34, 2820}, + /*(6056) VPMOVSDB*/ { 61, 1, 0x21, 2538}, + /*(6057) VPMOVSDB*/ { 81, 145, 0x21, 2820}, + /*(6058) VPMOVSDB*/ { 61, 1, 0x21, 2538}, + /*(6059) VPMOVSDB*/ { 81, 145, 0x21, 2820}, + /*(6060) VPMOVSDB*/ { 61, 1, 0x21, 2538}, + /*(6061) VPMOVSDB*/ { 81, 145, 0x21, 2820}, + /*(6062) VPMOVSDW*/ { 61, 1, 0x23, 2538}, + /*(6063) VPMOVSDW*/ { 81, 147, 0x23, 2820}, + /*(6064) VPMOVSDW*/ { 61, 1, 0x23, 2538}, + /*(6065) VPMOVSDW*/ { 81, 147, 0x23, 2820}, + /*(6066) VPMOVSDW*/ { 61, 1, 0x23, 2538}, + /*(6067) VPMOVSDW*/ { 81, 147, 0x23, 2820}, + /*(6068) VPMOVSQB*/ { 61, 1, 0x22, 2538}, + /*(6069) VPMOVSQB*/ { 81, 146, 0x22, 2820}, + /*(6070) VPMOVSQB*/ { 61, 1, 0x22, 2538}, + /*(6071) VPMOVSQB*/ { 81, 146, 0x22, 2820}, + /*(6072) VPMOVSQB*/ { 61, 1, 0x22, 2538}, + /*(6073) VPMOVSQB*/ { 81, 146, 0x22, 2820}, + /*(6074) VPMOVSQD*/ { 61, 1, 0x25, 2538}, + /*(6075) VPMOVSQD*/ { 81, 149, 0x25, 2820}, + /*(6076) VPMOVSQD*/ { 61, 1, 0x25, 2538}, + /*(6077) VPMOVSQD*/ { 81, 149, 0x25, 2820}, + /*(6078) VPMOVSQD*/ { 61, 1, 0x25, 2538}, + /*(6079) VPMOVSQD*/ { 81, 149, 0x25, 2820}, + /*(6080) VPMOVSQW*/ { 61, 1, 0x24, 2538}, + /*(6081) VPMOVSQW*/ { 81, 148, 0x24, 2820}, + /*(6082) VPMOVSQW*/ { 61, 1, 0x24, 2538}, + /*(6083) VPMOVSQW*/ { 81, 148, 0x24, 2820}, + /*(6084) VPMOVSQW*/ { 61, 1, 0x24, 2538}, + /*(6085) VPMOVSQW*/ { 81, 148, 0x24, 2820}, + /*(6086) VPMOVUSDB*/ { 61, 1, 0x11, 2538}, + /*(6087) VPMOVUSDB*/ { 81, 145, 0x11, 2820}, + /*(6088) VPMOVUSDB*/ { 61, 1, 0x11, 2538}, + /*(6089) VPMOVUSDB*/ { 81, 145, 0x11, 2820}, + /*(6090) VPMOVUSDB*/ { 61, 1, 0x11, 2538}, + /*(6091) VPMOVUSDB*/ { 81, 145, 0x11, 2820}, + /*(6092) VPMOVUSDW*/ { 61, 1, 0x13, 2538}, + /*(6093) VPMOVUSDW*/ { 81, 147, 0x13, 2820}, + /*(6094) VPMOVUSDW*/ { 61, 1, 0x13, 2538}, + /*(6095) VPMOVUSDW*/ { 81, 147, 0x13, 2820}, + /*(6096) VPMOVUSDW*/ { 61, 1, 0x13, 2538}, + /*(6097) VPMOVUSDW*/ { 81, 147, 0x13, 2820}, + /*(6098) VPMOVUSQB*/ { 61, 1, 0x12, 2538}, + /*(6099) VPMOVUSQB*/ { 81, 146, 0x12, 2820}, + /*(6100) VPMOVUSQB*/ { 61, 1, 0x12, 2538}, + /*(6101) VPMOVUSQB*/ { 81, 146, 0x12, 2820}, + /*(6102) VPMOVUSQB*/ { 61, 1, 0x12, 2538}, + /*(6103) VPMOVUSQB*/ { 81, 146, 0x12, 2820}, + /*(6104) VPMOVUSQD*/ { 61, 1, 0x15, 2538}, + /*(6105) VPMOVUSQD*/ { 81, 149, 0x15, 2820}, + /*(6106) VPMOVUSQD*/ { 61, 1, 0x15, 2538}, + /*(6107) VPMOVUSQD*/ { 81, 149, 0x15, 2820}, + /*(6108) VPMOVUSQD*/ { 61, 1, 0x15, 2538}, + /*(6109) VPMOVUSQD*/ { 81, 149, 0x15, 2820}, + /*(6110) VPMOVUSQW*/ { 61, 1, 0x14, 2538}, + /*(6111) VPMOVUSQW*/ { 81, 148, 0x14, 2820}, + /*(6112) VPMOVUSQW*/ { 61, 1, 0x14, 2538}, + /*(6113) VPMOVUSQW*/ { 81, 148, 0x14, 2820}, + /*(6114) VPMOVUSQW*/ { 61, 1, 0x14, 2538}, + /*(6115) VPMOVUSQW*/ { 81, 148, 0x14, 2820}, + /*(6116) VPORD*/ { 54, 1, 0xeb, 1731}, + /*(6117) VPORD*/ { 40, 103, 0xeb, 121}, + /*(6118) VPORD*/ { 54, 1, 0xeb, 1731}, + /*(6119) VPORD*/ { 40, 103, 0xeb, 121}, + /*(6120) VPORD*/ { 54, 1, 0xeb, 1731}, + /*(6121) VPORD*/ { 40, 103, 0xeb, 121}, + /*(6122) VPORQ*/ { 54, 1, 0xeb, 585}, + /*(6123) VPORQ*/ { 40, 102, 0xeb, 597}, + /*(6124) VPORQ*/ { 54, 1, 0xeb, 585}, + /*(6125) VPORQ*/ { 40, 102, 0xeb, 597}, + /*(6126) VPORQ*/ { 54, 1, 0xeb, 585}, + /*(6127) VPORQ*/ { 40, 102, 0xeb, 597}, + /*(6128) VPROLD*/ { 88, 10, 0x72, 2829}, + /*(6129) VPROLD*/ { 89, 109, 0x72, 120}, + /*(6130) VPROLD*/ { 88, 10, 0x72, 2829}, + /*(6131) VPROLD*/ { 89, 109, 0x72, 120}, + /*(6132) VPROLD*/ { 88, 10, 0x72, 2829}, + /*(6133) VPROLD*/ { 89, 109, 0x72, 120}, + /*(6134) VPROLQ*/ { 88, 10, 0x72, 2836}, + /*(6135) VPROLQ*/ { 89, 108, 0x72, 946}, + /*(6136) VPROLQ*/ { 88, 10, 0x72, 2836}, + /*(6137) VPROLQ*/ { 89, 108, 0x72, 946}, + /*(6138) VPROLQ*/ { 88, 10, 0x72, 2836}, + /*(6139) VPROLQ*/ { 89, 108, 0x72, 946}, + /*(6140) VPROLVD*/ { 54, 1, 0x15, 1377}, + /*(6141) VPROLVD*/ { 40, 103, 0x15, 1383}, + /*(6142) VPROLVD*/ { 54, 1, 0x15, 1377}, + /*(6143) VPROLVD*/ { 40, 103, 0x15, 1383}, + /*(6144) VPROLVD*/ { 54, 1, 0x15, 1377}, + /*(6145) VPROLVD*/ { 40, 103, 0x15, 1383}, + /*(6146) VPROLVQ*/ { 54, 1, 0x15, 1362}, + /*(6147) VPROLVQ*/ { 40, 102, 0x15, 877}, + /*(6148) VPROLVQ*/ { 54, 1, 0x15, 1362}, + /*(6149) VPROLVQ*/ { 40, 102, 0x15, 877}, + /*(6150) VPROLVQ*/ { 54, 1, 0x15, 1362}, + /*(6151) VPROLVQ*/ { 40, 102, 0x15, 877}, + /*(6152) VPRORD*/ { 88, 10, 0x72, 2843}, + /*(6153) VPRORD*/ { 89, 109, 0x72, 1050}, + /*(6154) VPRORD*/ { 88, 10, 0x72, 2843}, + /*(6155) VPRORD*/ { 89, 109, 0x72, 1050}, + /*(6156) VPRORD*/ { 88, 10, 0x72, 2843}, + /*(6157) VPRORD*/ { 89, 109, 0x72, 1050}, + /*(6158) VPRORQ*/ { 88, 10, 0x72, 2850}, + /*(6159) VPRORQ*/ { 89, 108, 0x72, 1918}, + /*(6160) VPRORQ*/ { 88, 10, 0x72, 2850}, + /*(6161) VPRORQ*/ { 89, 108, 0x72, 1918}, + /*(6162) VPRORQ*/ { 88, 10, 0x72, 2850}, + /*(6163) VPRORQ*/ { 89, 108, 0x72, 1918}, + /*(6164) VPRORVD*/ { 54, 1, 0x14, 1377}, + /*(6165) VPRORVD*/ { 40, 103, 0x14, 1383}, + /*(6166) VPRORVD*/ { 54, 1, 0x14, 1377}, + /*(6167) VPRORVD*/ { 40, 103, 0x14, 1383}, + /*(6168) VPRORVD*/ { 54, 1, 0x14, 1377}, + /*(6169) VPRORVD*/ { 40, 103, 0x14, 1383}, + /*(6170) VPRORVQ*/ { 54, 1, 0x14, 1362}, + /*(6171) VPRORVQ*/ { 40, 102, 0x14, 877}, + /*(6172) VPRORVQ*/ { 54, 1, 0x14, 1362}, + /*(6173) VPRORVQ*/ { 40, 102, 0x14, 877}, + /*(6174) VPRORVQ*/ { 54, 1, 0x14, 1362}, + /*(6175) VPRORVQ*/ { 40, 102, 0x14, 877}, + /*(6176) VPSCATTERDD*/ { 96, 163, 0xa0, 2079}, + /*(6177) VPSCATTERDD*/ { 96, 164, 0xa0, 2079}, + /*(6178) VPSCATTERDD*/ { 96, 165, 0xa0, 2079}, + /*(6179) VPSCATTERDQ*/ { 96, 160, 0xa0, 2065}, + /*(6180) VPSCATTERDQ*/ { 96, 161, 0xa0, 2065}, + /*(6181) VPSCATTERDQ*/ { 96, 161, 0xa0, 2065}, + /*(6182) VPSCATTERQD*/ { 96, 163, 0xa1, 2079}, + /*(6183) VPSCATTERQD*/ { 96, 164, 0xa1, 2079}, + /*(6184) VPSCATTERQD*/ { 96, 165, 0xa1, 2079}, + /*(6185) VPSCATTERQQ*/ { 96, 166, 0xa1, 2065}, + /*(6186) VPSCATTERQQ*/ { 96, 161, 0xa1, 2065}, + /*(6187) VPSCATTERQQ*/ { 96, 160, 0xa1, 2065}, + /*(6188) VPSRAQ*/ { 54, 1, 0xe2, 585}, + /*(6189) VPSRAQ*/ { 55, 140, 0xe2, 1765}, + /*(6190) VPSRAQ*/ { 88, 10, 0x72, 2857}, + /*(6191) VPSRAQ*/ { 89, 108, 0x72, 2864}, + /*(6192) VPSRAQ*/ { 54, 1, 0xe2, 585}, + /*(6193) VPSRAQ*/ { 55, 140, 0xe2, 1765}, + /*(6194) VPSRAQ*/ { 88, 10, 0x72, 2857}, + /*(6195) VPSRAQ*/ { 89, 108, 0x72, 2864}, + /*(6196) VPSRAQ*/ { 54, 1, 0xe2, 585}, + /*(6197) VPSRAQ*/ { 55, 140, 0xe2, 1765}, + /*(6198) VPSRAQ*/ { 88, 10, 0x72, 2857}, + /*(6199) VPSRAQ*/ { 89, 108, 0x72, 2864}, + /*(6200) VPSRAVQ*/ { 54, 1, 0x46, 1362}, + /*(6201) VPSRAVQ*/ { 40, 102, 0x46, 877}, + /*(6202) VPSRAVQ*/ { 54, 1, 0x46, 1362}, + /*(6203) VPSRAVQ*/ { 40, 102, 0x46, 877}, + /*(6204) VPSRAVQ*/ { 54, 1, 0x46, 1362}, + /*(6205) VPSRAVQ*/ { 40, 102, 0x46, 877}, + /*(6206) VPTERNLOGD*/ { 54, 10, 0x25, 2666}, + /*(6207) VPTERNLOGD*/ { 40, 109, 0x25, 1028}, + /*(6208) VPTERNLOGD*/ { 54, 10, 0x25, 2666}, + /*(6209) VPTERNLOGD*/ { 40, 109, 0x25, 1028}, + /*(6210) VPTERNLOGD*/ { 54, 10, 0x25, 2666}, + /*(6211) VPTERNLOGD*/ { 40, 109, 0x25, 1028}, + /*(6212) VPTERNLOGQ*/ { 54, 10, 0x25, 2672}, + /*(6213) VPTERNLOGQ*/ { 40, 108, 0x25, 587}, + /*(6214) VPTERNLOGQ*/ { 54, 10, 0x25, 2672}, + /*(6215) VPTERNLOGQ*/ { 40, 108, 0x25, 587}, + /*(6216) VPTERNLOGQ*/ { 54, 10, 0x25, 2672}, + /*(6217) VPTERNLOGQ*/ { 40, 108, 0x25, 587}, + /*(6218) VPTESTMD*/ { 56, 1, 0x27, 2869}, + /*(6219) VPTESTMD*/ { 57, 103, 0x27, 1801}, + /*(6220) VPTESTMD*/ { 56, 1, 0x27, 2869}, + /*(6221) VPTESTMD*/ { 57, 103, 0x27, 1801}, + /*(6222) VPTESTMD*/ { 56, 1, 0x27, 2869}, + /*(6223) VPTESTMD*/ { 57, 103, 0x27, 1801}, + /*(6224) VPTESTMQ*/ { 56, 1, 0x27, 1362}, + /*(6225) VPTESTMQ*/ { 57, 102, 0x27, 1863}, + /*(6226) VPTESTMQ*/ { 56, 1, 0x27, 1362}, + /*(6227) VPTESTMQ*/ { 57, 102, 0x27, 1863}, + /*(6228) VPTESTMQ*/ { 56, 1, 0x27, 1362}, + /*(6229) VPTESTMQ*/ { 57, 102, 0x27, 1863}, + /*(6230) VPTESTNMD*/ { 56, 1, 0x27, 2876}, + /*(6231) VPTESTNMD*/ { 57, 103, 0x27, 2883}, + /*(6232) VPTESTNMD*/ { 56, 1, 0x27, 2876}, + /*(6233) VPTESTNMD*/ { 57, 103, 0x27, 2883}, + /*(6234) VPTESTNMD*/ { 56, 1, 0x27, 2876}, + /*(6235) VPTESTNMD*/ { 57, 103, 0x27, 2883}, + /*(6236) VPTESTNMQ*/ { 56, 1, 0x27, 2888}, + /*(6237) VPTESTNMQ*/ { 57, 102, 0x27, 2895}, + /*(6238) VPTESTNMQ*/ { 56, 1, 0x27, 2888}, + /*(6239) VPTESTNMQ*/ { 57, 102, 0x27, 2895}, + /*(6240) VPTESTNMQ*/ { 56, 1, 0x27, 2888}, + /*(6241) VPTESTNMQ*/ { 57, 102, 0x27, 2895}, + /*(6242) VPXORD*/ { 54, 1, 0xef, 1731}, + /*(6243) VPXORD*/ { 40, 103, 0xef, 121}, + /*(6244) VPXORD*/ { 54, 1, 0xef, 1731}, + /*(6245) VPXORD*/ { 40, 103, 0xef, 121}, + /*(6246) VPXORD*/ { 54, 1, 0xef, 1731}, + /*(6247) VPXORD*/ { 40, 103, 0xef, 121}, + /*(6248) VPXORQ*/ { 54, 1, 0xef, 585}, + /*(6249) VPXORQ*/ { 40, 102, 0xef, 597}, + /*(6250) VPXORQ*/ { 54, 1, 0xef, 585}, + /*(6251) VPXORQ*/ { 40, 102, 0xef, 597}, + /*(6252) VPXORQ*/ { 54, 1, 0xef, 585}, + /*(6253) VPXORQ*/ { 40, 102, 0xef, 597}, + /*(6254) VRCP14PD*/ { 61, 1, 0x4c, 1499}, + /*(6255) VRCP14PD*/ { 62, 102, 0x4c, 1491}, + /*(6256) VRCP14PD*/ { 61, 1, 0x4c, 1499}, + /*(6257) VRCP14PD*/ { 62, 102, 0x4c, 1491}, + /*(6258) VRCP14PD*/ { 61, 1, 0x4c, 1499}, + /*(6259) VRCP14PD*/ { 62, 102, 0x4c, 1491}, + /*(6260) VRCP14PS*/ { 61, 1, 0x4c, 1427}, + /*(6261) VRCP14PS*/ { 62, 103, 0x4c, 1419}, + /*(6262) VRCP14PS*/ { 61, 1, 0x4c, 1427}, + /*(6263) VRCP14PS*/ { 62, 103, 0x4c, 1419}, + /*(6264) VRCP14PS*/ { 61, 1, 0x4c, 1427}, + /*(6265) VRCP14PS*/ { 62, 103, 0x4c, 1419}, + /*(6266) VRCP14SD*/ { 54, 1, 0x4d, 1362}, + /*(6267) VRCP14SD*/ { 55, 105, 0x4d, 876}, + /*(6268) VRCP14SS*/ { 54, 1, 0x4d, 1377}, + /*(6269) VRCP14SS*/ { 55, 106, 0x4d, 2019}, + /*(6270) VRNDSCALEPD*/ { 61, 10, 0x9, 1353}, + /*(6271) VRNDSCALEPD*/ { 61, 107, 0x9, 2778}, + /*(6272) VRNDSCALEPD*/ { 62, 108, 0x9, 716}, + /*(6273) VRNDSCALEPD*/ { 61, 10, 0x9, 1353}, + /*(6274) VRNDSCALEPD*/ { 62, 108, 0x9, 716}, + /*(6275) VRNDSCALEPD*/ { 61, 10, 0x9, 1353}, + /*(6276) VRNDSCALEPD*/ { 62, 108, 0x9, 716}, + /*(6277) VRNDSCALEPS*/ { 61, 10, 0x8, 1368}, + /*(6278) VRNDSCALEPS*/ { 61, 107, 0x8, 2034}, + /*(6279) VRNDSCALEPS*/ { 62, 109, 0x8, 912}, + /*(6280) VRNDSCALEPS*/ { 61, 10, 0x8, 1368}, + /*(6281) VRNDSCALEPS*/ { 62, 109, 0x8, 912}, + /*(6282) VRNDSCALEPS*/ { 61, 10, 0x8, 1368}, + /*(6283) VRNDSCALEPS*/ { 62, 109, 0x8, 912}, + /*(6284) VRNDSCALESD*/ { 54, 10, 0xb, 2672}, + /*(6285) VRNDSCALESD*/ { 54, 110, 0xb, 2766}, + /*(6286) VRNDSCALESD*/ { 55, 111, 0xb, 1989}, + /*(6287) VRNDSCALESS*/ { 54, 10, 0xa, 2666}, + /*(6288) VRNDSCALESS*/ { 54, 110, 0xa, 2772}, + /*(6289) VRNDSCALESS*/ { 55, 112, 0xa, 1027}, + /*(6290) VRSQRT14PD*/ { 61, 1, 0x4e, 1499}, + /*(6291) VRSQRT14PD*/ { 62, 102, 0x4e, 1491}, + /*(6292) VRSQRT14PD*/ { 61, 1, 0x4e, 1499}, + /*(6293) VRSQRT14PD*/ { 62, 102, 0x4e, 1491}, + /*(6294) VRSQRT14PD*/ { 61, 1, 0x4e, 1499}, + /*(6295) VRSQRT14PD*/ { 62, 102, 0x4e, 1491}, + /*(6296) VRSQRT14PS*/ { 61, 1, 0x4e, 1427}, + /*(6297) VRSQRT14PS*/ { 62, 103, 0x4e, 1419}, + /*(6298) VRSQRT14PS*/ { 61, 1, 0x4e, 1427}, + /*(6299) VRSQRT14PS*/ { 62, 103, 0x4e, 1419}, + /*(6300) VRSQRT14PS*/ { 61, 1, 0x4e, 1427}, + /*(6301) VRSQRT14PS*/ { 62, 103, 0x4e, 1419}, + /*(6302) VRSQRT14SD*/ { 54, 1, 0x4f, 1362}, + /*(6303) VRSQRT14SD*/ { 55, 105, 0x4f, 876}, + /*(6304) VRSQRT14SS*/ { 54, 1, 0x4f, 1377}, + /*(6305) VRSQRT14SS*/ { 55, 106, 0x4f, 2019}, + /*(6306) VSCALEFPD*/ { 54, 1, 0x2c, 1362}, + /*(6307) VSCALEFPD*/ { 54, 101, 0x2c, 2048}, + /*(6308) VSCALEFPD*/ { 40, 102, 0x2c, 877}, + /*(6309) VSCALEFPD*/ { 54, 1, 0x2c, 1362}, + /*(6310) VSCALEFPD*/ { 40, 102, 0x2c, 877}, + /*(6311) VSCALEFPD*/ { 54, 1, 0x2c, 1362}, + /*(6312) VSCALEFPD*/ { 40, 102, 0x2c, 877}, + /*(6313) VSCALEFPS*/ { 54, 1, 0x2c, 1377}, + /*(6314) VSCALEFPS*/ { 54, 101, 0x2c, 2054}, + /*(6315) VSCALEFPS*/ { 40, 103, 0x2c, 1383}, + /*(6316) VSCALEFPS*/ { 54, 1, 0x2c, 1377}, + /*(6317) VSCALEFPS*/ { 40, 103, 0x2c, 1383}, + /*(6318) VSCALEFPS*/ { 54, 1, 0x2c, 1377}, + /*(6319) VSCALEFPS*/ { 40, 103, 0x2c, 1383}, + /*(6320) VSCALEFSD*/ { 54, 1, 0x2d, 1362}, + /*(6321) VSCALEFSD*/ { 54, 104, 0x2d, 2048}, + /*(6322) VSCALEFSD*/ { 55, 105, 0x2d, 876}, + /*(6323) VSCALEFSS*/ { 54, 1, 0x2d, 1377}, + /*(6324) VSCALEFSS*/ { 54, 104, 0x2d, 2054}, + /*(6325) VSCALEFSS*/ { 55, 106, 0x2d, 2019}, + /*(6326) VSCATTERDPD*/ { 96, 160, 0xa2, 2065}, + /*(6327) VSCATTERDPD*/ { 96, 161, 0xa2, 2065}, + /*(6328) VSCATTERDPD*/ { 96, 161, 0xa2, 2065}, + /*(6329) VSCATTERDPS*/ { 96, 163, 0xa2, 2079}, + /*(6330) VSCATTERDPS*/ { 96, 164, 0xa2, 2079}, + /*(6331) VSCATTERDPS*/ { 96, 165, 0xa2, 2079}, + /*(6332) VSCATTERQPD*/ { 96, 166, 0xa3, 2065}, + /*(6333) VSCATTERQPD*/ { 96, 161, 0xa3, 2065}, + /*(6334) VSCATTERQPD*/ { 96, 160, 0xa3, 2065}, + /*(6335) VSCATTERQPS*/ { 96, 163, 0xa3, 2079}, + /*(6336) VSCATTERQPS*/ { 96, 164, 0xa3, 2079}, + /*(6337) VSCATTERQPS*/ { 96, 165, 0xa3, 2079}, + /*(6338) VSHUFF32X4*/ { 54, 10, 0x23, 2666}, + /*(6339) VSHUFF32X4*/ { 40, 109, 0x23, 1028}, + /*(6340) VSHUFF32X4*/ { 54, 10, 0x23, 2666}, + /*(6341) VSHUFF32X4*/ { 40, 109, 0x23, 1028}, + /*(6342) VSHUFF64X2*/ { 54, 10, 0x23, 2672}, + /*(6343) VSHUFF64X2*/ { 40, 108, 0x23, 587}, + /*(6344) VSHUFF64X2*/ { 54, 10, 0x23, 2672}, + /*(6345) VSHUFF64X2*/ { 40, 108, 0x23, 587}, + /*(6346) VSHUFI32X4*/ { 54, 10, 0x43, 2666}, + /*(6347) VSHUFI32X4*/ { 40, 109, 0x43, 1028}, + /*(6348) VSHUFI32X4*/ { 54, 10, 0x43, 2666}, + /*(6349) VSHUFI32X4*/ { 40, 109, 0x43, 1028}, + /*(6350) VSHUFI64X2*/ { 54, 10, 0x43, 2672}, + /*(6351) VSHUFI64X2*/ { 40, 108, 0x43, 587}, + /*(6352) VSHUFI64X2*/ { 54, 10, 0x43, 2672}, + /*(6353) VSHUFI64X2*/ { 40, 108, 0x43, 587}, + /*(6354) KANDNW*/ { 101, 1, 0x42, 2900}, + /*(6355) KANDW*/ { 101, 1, 0x41, 2900}, + /*(6356) KMOVW*/ { 107, 1, 0x90, 2906}, + /*(6357) KMOVW*/ { 108, 0, 0x90, 2914}, + /*(6358) KMOVW*/ { 108, 0, 0x91, 2914}, + /*(6359) KMOVW*/ { 107, 1, 0x92, 2906}, + /*(6360) KMOVW*/ { 107, 1, 0x93, 2906}, + /*(6361) KNOTW*/ { 107, 1, 0x44, 2906}, + /*(6362) KORTESTW*/ { 107, 1, 0x98, 2906}, + /*(6363) KORW*/ { 101, 1, 0x45, 2900}, + /*(6364) KSHIFTLW*/ { 107, 10, 0x32, 1931}, + /*(6365) KSHIFTRW*/ { 107, 10, 0x30, 1931}, + /*(6366) KUNPCKBW*/ { 101, 1, 0x4b, 2921}, + /*(6367) KXNORW*/ { 101, 1, 0x46, 2900}, + /*(6368) KXORW*/ { 101, 1, 0x47, 2900}, + /*(6369) VPBROADCASTMB2Q*/ { 110, 1, 0x2a, 2927}, + /*(6370) VPBROADCASTMB2Q*/ { 110, 1, 0x2a, 2939}, + /*(6371) VPBROADCASTMB2Q*/ { 110, 1, 0x2a, 2951}, + /*(6372) VPBROADCASTMW2D*/ { 110, 1, 0x3a, 2963}, + /*(6373) VPBROADCASTMW2D*/ { 110, 1, 0x3a, 2975}, + /*(6374) VPBROADCASTMW2D*/ { 110, 1, 0x3a, 2987}, + /*(6375) VPCONFLICTD*/ { 61, 1, 0xc4, 1427}, + /*(6376) VPCONFLICTD*/ { 62, 103, 0xc4, 1419}, + /*(6377) VPCONFLICTD*/ { 61, 1, 0xc4, 1427}, + /*(6378) VPCONFLICTD*/ { 62, 103, 0xc4, 1419}, + /*(6379) VPCONFLICTD*/ { 61, 1, 0xc4, 1427}, + /*(6380) VPCONFLICTD*/ { 62, 103, 0xc4, 1419}, + /*(6381) VPCONFLICTQ*/ { 61, 1, 0xc4, 1499}, + /*(6382) VPCONFLICTQ*/ { 62, 102, 0xc4, 1491}, + /*(6383) VPCONFLICTQ*/ { 61, 1, 0xc4, 1499}, + /*(6384) VPCONFLICTQ*/ { 62, 102, 0xc4, 1491}, + /*(6385) VPCONFLICTQ*/ { 61, 1, 0xc4, 1499}, + /*(6386) VPCONFLICTQ*/ { 62, 102, 0xc4, 1491}, + /*(6387) VPLZCNTD*/ { 61, 1, 0x44, 1427}, + /*(6388) VPLZCNTD*/ { 62, 103, 0x44, 1419}, + /*(6389) VPLZCNTD*/ { 61, 1, 0x44, 1427}, + /*(6390) VPLZCNTD*/ { 62, 103, 0x44, 1419}, + /*(6391) VPLZCNTD*/ { 61, 1, 0x44, 1427}, + /*(6392) VPLZCNTD*/ { 62, 103, 0x44, 1419}, + /*(6393) VPLZCNTQ*/ { 61, 1, 0x44, 1499}, + /*(6394) VPLZCNTQ*/ { 62, 102, 0x44, 1491}, + /*(6395) VPLZCNTQ*/ { 61, 1, 0x44, 1499}, + /*(6396) VPLZCNTQ*/ { 62, 102, 0x44, 1491}, + /*(6397) VPLZCNTQ*/ { 61, 1, 0x44, 1499}, + /*(6398) VPLZCNTQ*/ { 62, 102, 0x44, 1491}, + /*(6399) VBROADCASTF32X2*/ { 77, 1, 0x19, 2999}, + /*(6400) VBROADCASTF32X2*/ { 76, 143, 0x19, 3009}, + /*(6401) VBROADCASTF32X2*/ { 77, 1, 0x19, 3018}, + /*(6402) VBROADCASTF32X2*/ { 76, 143, 0x19, 3028}, + /*(6403) VBROADCASTF32X8*/ { 76, 179, 0x1b, 3037}, + /*(6404) VBROADCASTF64X2*/ { 76, 180, 0x1a, 3046}, + /*(6405) VBROADCASTF64X2*/ { 76, 180, 0x1a, 3055}, + /*(6406) VBROADCASTI32X2*/ { 77, 1, 0x59, 3064}, + /*(6407) VBROADCASTI32X2*/ { 76, 143, 0x59, 3074}, + /*(6408) VBROADCASTI32X2*/ { 77, 1, 0x59, 2999}, + /*(6409) VBROADCASTI32X2*/ { 76, 143, 0x59, 3009}, + /*(6410) VBROADCASTI32X2*/ { 77, 1, 0x59, 3018}, + /*(6411) VBROADCASTI32X2*/ { 76, 143, 0x59, 3028}, + /*(6412) VBROADCASTI32X8*/ { 76, 179, 0x5b, 3037}, + /*(6413) VBROADCASTI64X2*/ { 76, 180, 0x5a, 3046}, + /*(6414) VBROADCASTI64X2*/ { 76, 180, 0x5a, 3055}, + /*(6415) VCVTPD2QQ*/ { 61, 1, 0x7b, 885}, + /*(6416) VCVTPD2QQ*/ { 62, 102, 0x7b, 903}, + /*(6417) VCVTPD2QQ*/ { 61, 1, 0x7b, 885}, + /*(6418) VCVTPD2QQ*/ { 62, 102, 0x7b, 903}, + /*(6419) VCVTPD2QQ*/ { 61, 1, 0x7b, 885}, + /*(6420) VCVTPD2QQ*/ { 61, 101, 0x7b, 894}, + /*(6421) VCVTPD2QQ*/ { 62, 102, 0x7b, 903}, + /*(6422) VCVTPD2UQQ*/ { 61, 1, 0x79, 885}, + /*(6423) VCVTPD2UQQ*/ { 62, 102, 0x79, 903}, + /*(6424) VCVTPD2UQQ*/ { 61, 1, 0x79, 885}, + /*(6425) VCVTPD2UQQ*/ { 62, 102, 0x79, 903}, + /*(6426) VCVTPD2UQQ*/ { 61, 1, 0x79, 885}, + /*(6427) VCVTPD2UQQ*/ { 61, 101, 0x79, 894}, + /*(6428) VCVTPD2UQQ*/ { 62, 102, 0x79, 903}, + /*(6429) VCVTPS2QQ*/ { 61, 1, 0x7b, 910}, + /*(6430) VCVTPS2QQ*/ { 62, 118, 0x7b, 928}, + /*(6431) VCVTPS2QQ*/ { 61, 1, 0x7b, 910}, + /*(6432) VCVTPS2QQ*/ { 62, 118, 0x7b, 928}, + /*(6433) VCVTPS2QQ*/ { 61, 1, 0x7b, 910}, + /*(6434) VCVTPS2QQ*/ { 61, 101, 0x7b, 919}, + /*(6435) VCVTPS2QQ*/ { 62, 118, 0x7b, 928}, + /*(6436) VCVTPS2UQQ*/ { 61, 1, 0x79, 910}, + /*(6437) VCVTPS2UQQ*/ { 62, 118, 0x79, 928}, + /*(6438) VCVTPS2UQQ*/ { 61, 1, 0x79, 910}, + /*(6439) VCVTPS2UQQ*/ { 62, 118, 0x79, 928}, + /*(6440) VCVTPS2UQQ*/ { 61, 1, 0x79, 910}, + /*(6441) VCVTPS2UQQ*/ { 61, 101, 0x79, 919}, + /*(6442) VCVTPS2UQQ*/ { 62, 118, 0x79, 928}, + /*(6443) VCVTQQ2PD*/ { 61, 1, 0xe6, 2787}, + /*(6444) VCVTQQ2PD*/ { 62, 102, 0xe6, 2797}, + /*(6445) VCVTQQ2PD*/ { 61, 1, 0xe6, 2787}, + /*(6446) VCVTQQ2PD*/ { 62, 102, 0xe6, 2797}, + /*(6447) VCVTQQ2PD*/ { 61, 1, 0xe6, 2787}, + /*(6448) VCVTQQ2PD*/ { 61, 101, 0xe6, 3083}, + /*(6449) VCVTQQ2PD*/ { 62, 102, 0xe6, 2797}, + /*(6450) VCVTQQ2PS*/ { 61, 1, 0x5b, 2723}, + /*(6451) VCVTQQ2PS*/ { 62, 102, 0x5b, 2741}, + /*(6452) VCVTQQ2PS*/ { 61, 1, 0x5b, 2723}, + /*(6453) VCVTQQ2PS*/ { 62, 102, 0x5b, 2741}, + /*(6454) VCVTQQ2PS*/ { 61, 1, 0x5b, 2723}, + /*(6455) VCVTQQ2PS*/ { 61, 101, 0x5b, 2732}, + /*(6456) VCVTQQ2PS*/ { 62, 102, 0x5b, 2741}, + /*(6457) VCVTTPD2QQ*/ { 61, 1, 0x7a, 885}, + /*(6458) VCVTTPD2QQ*/ { 62, 102, 0x7a, 903}, + /*(6459) VCVTTPD2QQ*/ { 61, 1, 0x7a, 885}, + /*(6460) VCVTTPD2QQ*/ { 62, 102, 0x7a, 903}, + /*(6461) VCVTTPD2QQ*/ { 61, 1, 0x7a, 885}, + /*(6462) VCVTTPD2QQ*/ { 61, 119, 0x7a, 894}, + /*(6463) VCVTTPD2QQ*/ { 62, 102, 0x7a, 903}, + /*(6464) VCVTTPD2UQQ*/ { 61, 1, 0x78, 885}, + /*(6465) VCVTTPD2UQQ*/ { 62, 102, 0x78, 903}, + /*(6466) VCVTTPD2UQQ*/ { 61, 1, 0x78, 885}, + /*(6467) VCVTTPD2UQQ*/ { 62, 102, 0x78, 903}, + /*(6468) VCVTTPD2UQQ*/ { 61, 1, 0x78, 885}, + /*(6469) VCVTTPD2UQQ*/ { 61, 119, 0x78, 894}, + /*(6470) VCVTTPD2UQQ*/ { 62, 102, 0x78, 903}, + /*(6471) VCVTTPS2QQ*/ { 61, 1, 0x7a, 910}, + /*(6472) VCVTTPS2QQ*/ { 62, 118, 0x7a, 928}, + /*(6473) VCVTTPS2QQ*/ { 61, 1, 0x7a, 910}, + /*(6474) VCVTTPS2QQ*/ { 62, 118, 0x7a, 928}, + /*(6475) VCVTTPS2QQ*/ { 61, 1, 0x7a, 910}, + /*(6476) VCVTTPS2QQ*/ { 61, 119, 0x7a, 919}, + /*(6477) VCVTTPS2QQ*/ { 62, 118, 0x7a, 928}, + /*(6478) VCVTTPS2UQQ*/ { 61, 1, 0x78, 910}, + /*(6479) VCVTTPS2UQQ*/ { 62, 118, 0x78, 928}, + /*(6480) VCVTTPS2UQQ*/ { 61, 1, 0x78, 910}, + /*(6481) VCVTTPS2UQQ*/ { 62, 118, 0x78, 928}, + /*(6482) VCVTTPS2UQQ*/ { 61, 1, 0x78, 910}, + /*(6483) VCVTTPS2UQQ*/ { 61, 119, 0x78, 919}, + /*(6484) VCVTTPS2UQQ*/ { 62, 118, 0x78, 928}, + /*(6485) VCVTUQQ2PD*/ { 61, 1, 0x7a, 2787}, + /*(6486) VCVTUQQ2PD*/ { 62, 102, 0x7a, 2797}, + /*(6487) VCVTUQQ2PD*/ { 61, 1, 0x7a, 2787}, + /*(6488) VCVTUQQ2PD*/ { 62, 102, 0x7a, 2797}, + /*(6489) VCVTUQQ2PD*/ { 61, 1, 0x7a, 2787}, + /*(6490) VCVTUQQ2PD*/ { 61, 101, 0x7a, 3083}, + /*(6491) VCVTUQQ2PD*/ { 62, 102, 0x7a, 2797}, + /*(6492) VCVTUQQ2PS*/ { 61, 1, 0x7a, 860}, + /*(6493) VCVTUQQ2PS*/ { 62, 102, 0x7a, 878}, + /*(6494) VCVTUQQ2PS*/ { 61, 1, 0x7a, 860}, + /*(6495) VCVTUQQ2PS*/ { 62, 102, 0x7a, 878}, + /*(6496) VCVTUQQ2PS*/ { 61, 1, 0x7a, 860}, + /*(6497) VCVTUQQ2PS*/ { 61, 101, 0x7a, 869}, + /*(6498) VCVTUQQ2PS*/ { 62, 102, 0x7a, 878}, + /*(6499) VDBPSADBW*/ { 54, 10, 0x42, 2666}, + /*(6500) VDBPSADBW*/ { 55, 137, 0x42, 1027}, + /*(6501) VDBPSADBW*/ { 54, 10, 0x42, 2666}, + /*(6502) VDBPSADBW*/ { 55, 137, 0x42, 1027}, + /*(6503) VDBPSADBW*/ { 54, 10, 0x42, 2666}, + /*(6504) VDBPSADBW*/ { 55, 137, 0x42, 1027}, + /*(6505) VEXTRACTF32X8*/ { 61, 10, 0x1b, 1368}, + /*(6506) VEXTRACTF32X8*/ { 81, 181, 0x1b, 1333}, + /*(6507) VEXTRACTF64X2*/ { 61, 10, 0x19, 1353}, + /*(6508) VEXTRACTF64X2*/ { 81, 182, 0x19, 715}, + /*(6509) VEXTRACTF64X2*/ { 61, 10, 0x19, 1353}, + /*(6510) VEXTRACTF64X2*/ { 81, 182, 0x19, 715}, + /*(6511) VEXTRACTI32X8*/ { 61, 10, 0x3b, 1368}, + /*(6512) VEXTRACTI32X8*/ { 81, 181, 0x3b, 1333}, + /*(6513) VEXTRACTI64X2*/ { 61, 10, 0x39, 1353}, + /*(6514) VEXTRACTI64X2*/ { 81, 182, 0x39, 715}, + /*(6515) VEXTRACTI64X2*/ { 61, 10, 0x39, 1353}, + /*(6516) VEXTRACTI64X2*/ { 81, 182, 0x39, 715}, + /*(6517) VFPCLASSPD*/ { 111, 10, 0x66, 1353}, + /*(6518) VFPCLASSPD*/ { 112, 108, 0x66, 716}, + /*(6519) VFPCLASSPD*/ { 111, 10, 0x66, 1353}, + /*(6520) VFPCLASSPD*/ { 112, 108, 0x66, 716}, + /*(6521) VFPCLASSPD*/ { 111, 10, 0x66, 1353}, + /*(6522) VFPCLASSPD*/ { 112, 108, 0x66, 716}, + /*(6523) VFPCLASSPS*/ { 111, 10, 0x66, 1368}, + /*(6524) VFPCLASSPS*/ { 112, 109, 0x66, 1334}, + /*(6525) VFPCLASSPS*/ { 111, 10, 0x66, 1368}, + /*(6526) VFPCLASSPS*/ { 112, 109, 0x66, 1334}, + /*(6527) VFPCLASSPS*/ { 111, 10, 0x66, 1368}, + /*(6528) VFPCLASSPS*/ { 112, 109, 0x66, 1334}, + /*(6529) VFPCLASSSD*/ { 111, 10, 0x67, 1353}, + /*(6530) VFPCLASSSD*/ { 81, 111, 0x67, 715}, + /*(6531) VFPCLASSSS*/ { 111, 10, 0x67, 1368}, + /*(6532) VFPCLASSSS*/ { 81, 112, 0x67, 1333}, + /*(6533) VINSERTF32X8*/ { 54, 10, 0x1a, 2666}, + /*(6534) VINSERTF32X8*/ { 55, 181, 0x1a, 1027}, + /*(6535) VINSERTF64X2*/ { 54, 10, 0x18, 2672}, + /*(6536) VINSERTF64X2*/ { 55, 182, 0x18, 1989}, + /*(6537) VINSERTF64X2*/ { 54, 10, 0x18, 2672}, + /*(6538) VINSERTF64X2*/ { 55, 182, 0x18, 1989}, + /*(6539) VINSERTI32X8*/ { 54, 10, 0x3a, 2666}, + /*(6540) VINSERTI32X8*/ { 55, 181, 0x3a, 1027}, + /*(6541) VINSERTI64X2*/ { 54, 10, 0x38, 2672}, + /*(6542) VINSERTI64X2*/ { 55, 182, 0x38, 1989}, + /*(6543) VINSERTI64X2*/ { 54, 10, 0x38, 2672}, + /*(6544) VINSERTI64X2*/ { 55, 182, 0x38, 1989}, + /*(6545) VMOVDQU16*/ { 61, 1, 0x6f, 860}, + /*(6546) VMOVDQU16*/ { 80, 136, 0x6f, 1692}, + /*(6547) VMOVDQU16*/ { 61, 1, 0x7f, 860}, + /*(6548) VMOVDQU16*/ { 81, 136, 0x7f, 1692}, + /*(6549) VMOVDQU16*/ { 61, 1, 0x6f, 860}, + /*(6550) VMOVDQU16*/ { 80, 136, 0x6f, 1692}, + /*(6551) VMOVDQU16*/ { 61, 1, 0x7f, 860}, + /*(6552) VMOVDQU16*/ { 81, 136, 0x7f, 1692}, + /*(6553) VMOVDQU16*/ { 61, 1, 0x6f, 860}, + /*(6554) VMOVDQU16*/ { 80, 136, 0x6f, 1692}, + /*(6555) VMOVDQU16*/ { 61, 1, 0x7f, 860}, + /*(6556) VMOVDQU16*/ { 81, 136, 0x7f, 1692}, + /*(6557) VMOVDQU8*/ { 61, 1, 0x6f, 2748}, + /*(6558) VMOVDQU8*/ { 80, 135, 0x6f, 1005}, + /*(6559) VMOVDQU8*/ { 61, 1, 0x7f, 2748}, + /*(6560) VMOVDQU8*/ { 81, 135, 0x7f, 1005}, + /*(6561) VMOVDQU8*/ { 61, 1, 0x6f, 2748}, + /*(6562) VMOVDQU8*/ { 80, 135, 0x6f, 1005}, + /*(6563) VMOVDQU8*/ { 61, 1, 0x7f, 2748}, + /*(6564) VMOVDQU8*/ { 81, 135, 0x7f, 1005}, + /*(6565) VMOVDQU8*/ { 61, 1, 0x6f, 2748}, + /*(6566) VMOVDQU8*/ { 80, 135, 0x6f, 1005}, + /*(6567) VMOVDQU8*/ { 61, 1, 0x7f, 2748}, + /*(6568) VMOVDQU8*/ { 81, 135, 0x7f, 1005}, + /*(6569) VPBLENDMB*/ { 54, 1, 0x66, 1377}, + /*(6570) VPBLENDMB*/ { 55, 135, 0x66, 2019}, + /*(6571) VPBLENDMB*/ { 54, 1, 0x66, 1377}, + /*(6572) VPBLENDMB*/ { 55, 135, 0x66, 2019}, + /*(6573) VPBLENDMB*/ { 54, 1, 0x66, 1377}, + /*(6574) VPBLENDMB*/ { 55, 135, 0x66, 2019}, + /*(6575) VPBLENDMW*/ { 54, 1, 0x66, 1362}, + /*(6576) VPBLENDMW*/ { 55, 136, 0x66, 876}, + /*(6577) VPBLENDMW*/ { 54, 1, 0x66, 1362}, + /*(6578) VPBLENDMW*/ { 55, 136, 0x66, 876}, + /*(6579) VPBLENDMW*/ { 54, 1, 0x66, 1362}, + /*(6580) VPBLENDMW*/ { 55, 136, 0x66, 876}, + /*(6581) VPCMPB*/ { 56, 10, 0x3f, 2666}, + /*(6582) VPCMPB*/ { 58, 141, 0x3f, 1547}, + /*(6583) VPCMPB*/ { 56, 10, 0x3f, 2666}, + /*(6584) VPCMPB*/ { 58, 141, 0x3f, 1547}, + /*(6585) VPCMPB*/ { 56, 10, 0x3f, 2666}, + /*(6586) VPCMPB*/ { 58, 141, 0x3f, 1547}, + /*(6587) VPCMPUB*/ { 56, 10, 0x3e, 2666}, + /*(6588) VPCMPUB*/ { 58, 141, 0x3e, 1547}, + /*(6589) VPCMPUB*/ { 56, 10, 0x3e, 2666}, + /*(6590) VPCMPUB*/ { 58, 141, 0x3e, 1547}, + /*(6591) VPCMPUB*/ { 56, 10, 0x3e, 2666}, + /*(6592) VPCMPUB*/ { 58, 141, 0x3e, 1547}, + /*(6593) VPCMPUW*/ { 56, 10, 0x3e, 2813}, + /*(6594) VPCMPUW*/ { 58, 137, 0x3e, 1989}, + /*(6595) VPCMPUW*/ { 56, 10, 0x3e, 2813}, + /*(6596) VPCMPUW*/ { 58, 137, 0x3e, 1989}, + /*(6597) VPCMPUW*/ { 56, 10, 0x3e, 2813}, + /*(6598) VPCMPUW*/ { 58, 137, 0x3e, 1989}, + /*(6599) VPCMPW*/ { 56, 10, 0x3f, 2813}, + /*(6600) VPCMPW*/ { 58, 137, 0x3f, 1989}, + /*(6601) VPCMPW*/ { 56, 10, 0x3f, 2813}, + /*(6602) VPCMPW*/ { 58, 137, 0x3f, 1989}, + /*(6603) VPCMPW*/ { 56, 10, 0x3f, 2813}, + /*(6604) VPCMPW*/ { 58, 137, 0x3f, 1989}, + /*(6605) VPERMI2W*/ { 54, 1, 0x75, 1362}, + /*(6606) VPERMI2W*/ { 55, 136, 0x75, 876}, + /*(6607) VPERMI2W*/ { 54, 1, 0x75, 1362}, + /*(6608) VPERMI2W*/ { 55, 136, 0x75, 876}, + /*(6609) VPERMI2W*/ { 54, 1, 0x75, 1362}, + /*(6610) VPERMI2W*/ { 55, 136, 0x75, 876}, + /*(6611) VPERMT2W*/ { 54, 1, 0x7d, 1362}, + /*(6612) VPERMT2W*/ { 55, 136, 0x7d, 876}, + /*(6613) VPERMT2W*/ { 54, 1, 0x7d, 1362}, + /*(6614) VPERMT2W*/ { 55, 136, 0x7d, 876}, + /*(6615) VPERMT2W*/ { 54, 1, 0x7d, 1362}, + /*(6616) VPERMT2W*/ { 55, 136, 0x7d, 876}, + /*(6617) VPERMW*/ { 54, 1, 0x8d, 1362}, + /*(6618) VPERMW*/ { 55, 136, 0x8d, 876}, + /*(6619) VPERMW*/ { 54, 1, 0x8d, 1362}, + /*(6620) VPERMW*/ { 55, 136, 0x8d, 876}, + /*(6621) VPERMW*/ { 54, 1, 0x8d, 1362}, + /*(6622) VPERMW*/ { 55, 136, 0x8d, 876}, + /*(6623) VPEXTRW_C5*/ { 63, 10, 0xc5, 1618}, + /*(6624) VPEXTRW_C5*/ { 113, 10, 0xc5, 1628}, + /*(6625) VPMOVB2M*/ { 59, 1, 0x29, 2964}, + /*(6626) VPMOVB2M*/ { 59, 1, 0x29, 2964}, + /*(6627) VPMOVB2M*/ { 59, 1, 0x29, 2964}, + /*(6628) VPMOVD2M*/ { 59, 1, 0x39, 2964}, + /*(6629) VPMOVD2M*/ { 59, 1, 0x39, 2964}, + /*(6630) VPMOVD2M*/ { 59, 1, 0x39, 2964}, + /*(6631) VPMOVM2B*/ { 59, 1, 0x28, 2964}, + /*(6632) VPMOVM2B*/ { 59, 1, 0x28, 2964}, + /*(6633) VPMOVM2B*/ { 59, 1, 0x28, 2964}, + /*(6634) VPMOVM2D*/ { 59, 1, 0x38, 2964}, + /*(6635) VPMOVM2D*/ { 59, 1, 0x38, 2964}, + /*(6636) VPMOVM2D*/ { 59, 1, 0x38, 2964}, + /*(6637) VPMOVM2Q*/ { 59, 1, 0x38, 2928}, + /*(6638) VPMOVM2Q*/ { 59, 1, 0x38, 2928}, + /*(6639) VPMOVM2Q*/ { 59, 1, 0x38, 2928}, + /*(6640) VPMOVM2W*/ { 59, 1, 0x28, 2928}, + /*(6641) VPMOVM2W*/ { 59, 1, 0x28, 2928}, + /*(6642) VPMOVM2W*/ { 59, 1, 0x28, 2928}, + /*(6643) VPMOVQ2M*/ { 59, 1, 0x39, 2928}, + /*(6644) VPMOVQ2M*/ { 59, 1, 0x39, 2928}, + /*(6645) VPMOVQ2M*/ { 59, 1, 0x39, 2928}, + /*(6646) VPMOVSWB*/ { 61, 1, 0x20, 2538}, + /*(6647) VPMOVSWB*/ { 81, 144, 0x20, 2820}, + /*(6648) VPMOVSWB*/ { 61, 1, 0x20, 2538}, + /*(6649) VPMOVSWB*/ { 81, 144, 0x20, 2820}, + /*(6650) VPMOVSWB*/ { 61, 1, 0x20, 2538}, + /*(6651) VPMOVSWB*/ { 81, 144, 0x20, 2820}, + /*(6652) VPMOVUSWB*/ { 61, 1, 0x10, 2538}, + /*(6653) VPMOVUSWB*/ { 81, 144, 0x10, 2820}, + /*(6654) VPMOVUSWB*/ { 61, 1, 0x10, 2538}, + /*(6655) VPMOVUSWB*/ { 81, 144, 0x10, 2820}, + /*(6656) VPMOVUSWB*/ { 61, 1, 0x10, 2538}, + /*(6657) VPMOVUSWB*/ { 81, 144, 0x10, 2820}, + /*(6658) VPMOVW2M*/ { 59, 1, 0x29, 2928}, + /*(6659) VPMOVW2M*/ { 59, 1, 0x29, 2928}, + /*(6660) VPMOVW2M*/ { 59, 1, 0x29, 2928}, + /*(6661) VPMOVWB*/ { 61, 1, 0x30, 2538}, + /*(6662) VPMOVWB*/ { 81, 144, 0x30, 2820}, + /*(6663) VPMOVWB*/ { 61, 1, 0x30, 2538}, + /*(6664) VPMOVWB*/ { 81, 144, 0x30, 2820}, + /*(6665) VPMOVWB*/ { 61, 1, 0x30, 2538}, + /*(6666) VPMOVWB*/ { 81, 144, 0x30, 2820}, + /*(6667) VPMULLQ*/ { 54, 1, 0x40, 1362}, + /*(6668) VPMULLQ*/ { 40, 102, 0x40, 877}, + /*(6669) VPMULLQ*/ { 54, 1, 0x40, 1362}, + /*(6670) VPMULLQ*/ { 40, 102, 0x40, 877}, + /*(6671) VPMULLQ*/ { 54, 1, 0x40, 1362}, + /*(6672) VPMULLQ*/ { 40, 102, 0x40, 877}, + /*(6673) VPSLLVW*/ { 54, 1, 0x12, 1362}, + /*(6674) VPSLLVW*/ { 55, 136, 0x12, 876}, + /*(6675) VPSLLVW*/ { 54, 1, 0x12, 1362}, + /*(6676) VPSLLVW*/ { 55, 136, 0x12, 876}, + /*(6677) VPSLLVW*/ { 54, 1, 0x12, 1362}, + /*(6678) VPSLLVW*/ { 55, 136, 0x12, 876}, + /*(6679) VPSRAVW*/ { 54, 1, 0x11, 1362}, + /*(6680) VPSRAVW*/ { 55, 136, 0x11, 876}, + /*(6681) VPSRAVW*/ { 54, 1, 0x11, 1362}, + /*(6682) VPSRAVW*/ { 55, 136, 0x11, 876}, + /*(6683) VPSRAVW*/ { 54, 1, 0x11, 1362}, + /*(6684) VPSRAVW*/ { 55, 136, 0x11, 876}, + /*(6685) VPSRLVW*/ { 54, 1, 0x10, 1362}, + /*(6686) VPSRLVW*/ { 55, 136, 0x10, 876}, + /*(6687) VPSRLVW*/ { 54, 1, 0x10, 1362}, + /*(6688) VPSRLVW*/ { 55, 136, 0x10, 876}, + /*(6689) VPSRLVW*/ { 54, 1, 0x10, 1362}, + /*(6690) VPSRLVW*/ { 55, 136, 0x10, 876}, + /*(6691) VPTESTMB*/ { 56, 1, 0x26, 2869}, + /*(6692) VPTESTMB*/ { 58, 135, 0x26, 2019}, + /*(6693) VPTESTMB*/ { 56, 1, 0x26, 2869}, + /*(6694) VPTESTMB*/ { 58, 135, 0x26, 2019}, + /*(6695) VPTESTMB*/ { 56, 1, 0x26, 2869}, + /*(6696) VPTESTMB*/ { 58, 135, 0x26, 2019}, + /*(6697) VPTESTMW*/ { 56, 1, 0x26, 1362}, + /*(6698) VPTESTMW*/ { 58, 136, 0x26, 1862}, + /*(6699) VPTESTMW*/ { 56, 1, 0x26, 1362}, + /*(6700) VPTESTMW*/ { 58, 136, 0x26, 1862}, + /*(6701) VPTESTMW*/ { 56, 1, 0x26, 1362}, + /*(6702) VPTESTMW*/ { 58, 136, 0x26, 1862}, + /*(6703) VPTESTNMB*/ { 56, 1, 0x26, 2876}, + /*(6704) VPTESTNMB*/ { 58, 135, 0x26, 2882}, + /*(6705) VPTESTNMB*/ { 56, 1, 0x26, 2876}, + /*(6706) VPTESTNMB*/ { 58, 135, 0x26, 2882}, + /*(6707) VPTESTNMB*/ { 56, 1, 0x26, 2876}, + /*(6708) VPTESTNMB*/ { 58, 135, 0x26, 2882}, + /*(6709) VPTESTNMW*/ { 56, 1, 0x26, 2888}, + /*(6710) VPTESTNMW*/ { 58, 136, 0x26, 2894}, + /*(6711) VPTESTNMW*/ { 56, 1, 0x26, 2888}, + /*(6712) VPTESTNMW*/ { 58, 136, 0x26, 2894}, + /*(6713) VPTESTNMW*/ { 56, 1, 0x26, 2888}, + /*(6714) VPTESTNMW*/ { 58, 136, 0x26, 2894}, + /*(6715) VRANGEPD*/ { 54, 10, 0x50, 2672}, + /*(6716) VRANGEPD*/ { 40, 108, 0x50, 587}, + /*(6717) VRANGEPD*/ { 54, 10, 0x50, 2672}, + /*(6718) VRANGEPD*/ { 40, 108, 0x50, 587}, + /*(6719) VRANGEPD*/ { 54, 10, 0x50, 2672}, + /*(6720) VRANGEPD*/ { 54, 107, 0x50, 2766}, + /*(6721) VRANGEPD*/ { 40, 108, 0x50, 587}, + /*(6722) VRANGEPS*/ { 54, 10, 0x50, 2666}, + /*(6723) VRANGEPS*/ { 40, 109, 0x50, 1028}, + /*(6724) VRANGEPS*/ { 54, 10, 0x50, 2666}, + /*(6725) VRANGEPS*/ { 40, 109, 0x50, 1028}, + /*(6726) VRANGEPS*/ { 54, 10, 0x50, 2666}, + /*(6727) VRANGEPS*/ { 54, 107, 0x50, 2772}, + /*(6728) VRANGEPS*/ { 40, 109, 0x50, 1028}, + /*(6729) VRANGESD*/ { 54, 10, 0x51, 2672}, + /*(6730) VRANGESD*/ { 54, 110, 0x51, 2766}, + /*(6731) VRANGESD*/ { 55, 111, 0x51, 1989}, + /*(6732) VRANGESS*/ { 54, 10, 0x51, 2666}, + /*(6733) VRANGESS*/ { 54, 110, 0x51, 2772}, + /*(6734) VRANGESS*/ { 55, 112, 0x51, 1027}, + /*(6735) VREDUCEPD*/ { 61, 10, 0x56, 1353}, + /*(6736) VREDUCEPD*/ { 62, 108, 0x56, 716}, + /*(6737) VREDUCEPD*/ { 61, 10, 0x56, 1353}, + /*(6738) VREDUCEPD*/ { 62, 108, 0x56, 716}, + /*(6739) VREDUCEPD*/ { 61, 10, 0x56, 1353}, + /*(6740) VREDUCEPD*/ { 61, 107, 0x56, 2778}, + /*(6741) VREDUCEPD*/ { 62, 108, 0x56, 716}, + /*(6742) VREDUCEPS*/ { 61, 10, 0x56, 1368}, + /*(6743) VREDUCEPS*/ { 62, 109, 0x56, 912}, + /*(6744) VREDUCEPS*/ { 61, 10, 0x56, 1368}, + /*(6745) VREDUCEPS*/ { 62, 109, 0x56, 912}, + /*(6746) VREDUCEPS*/ { 61, 10, 0x56, 1368}, + /*(6747) VREDUCEPS*/ { 61, 107, 0x56, 2034}, + /*(6748) VREDUCEPS*/ { 62, 109, 0x56, 912}, + /*(6749) VREDUCESD*/ { 54, 10, 0x57, 2672}, + /*(6750) VREDUCESD*/ { 54, 110, 0x57, 2766}, + /*(6751) VREDUCESD*/ { 55, 111, 0x57, 1989}, + /*(6752) VREDUCESS*/ { 54, 10, 0x57, 2666}, + /*(6753) VREDUCESS*/ { 54, 110, 0x57, 2772}, + /*(6754) VREDUCESS*/ { 55, 112, 0x57, 1027}, + /*(6755) KADDB*/ { 101, 1, 0x4a, 2921}, + /*(6756) KADDD*/ { 101, 1, 0x4a, 3092}, + /*(6757) KADDQ*/ { 101, 1, 0x4a, 3098}, + /*(6758) KADDW*/ { 101, 1, 0x4a, 2900}, + /*(6759) KANDB*/ { 101, 1, 0x41, 2921}, + /*(6760) KANDD*/ { 101, 1, 0x41, 3092}, + /*(6761) KANDNB*/ { 101, 1, 0x42, 2921}, + /*(6762) KANDND*/ { 101, 1, 0x42, 3092}, + /*(6763) KANDNQ*/ { 101, 1, 0x42, 3098}, + /*(6764) KANDQ*/ { 101, 1, 0x41, 3098}, + /*(6765) KMOVB*/ { 107, 1, 0x90, 1611}, + /*(6766) KMOVB*/ { 108, 0, 0x90, 3104}, + /*(6767) KMOVB*/ { 108, 0, 0x91, 3104}, + /*(6768) KMOVB*/ { 107, 1, 0x92, 1611}, + /*(6769) KMOVB*/ { 107, 1, 0x93, 1611}, + /*(6770) KMOVD*/ { 107, 1, 0x90, 1664}, + /*(6771) KMOVD*/ { 108, 0, 0x90, 3111}, + /*(6772) KMOVD*/ { 108, 0, 0x91, 3111}, + /*(6773) KMOVD*/ { 107, 1, 0x92, 3118}, + /*(6774) KMOVD*/ { 106, 1, 0x92, 854}, + /*(6775) KMOVD*/ { 107, 1, 0x93, 3118}, + /*(6776) KMOVD*/ { 106, 1, 0x93, 854}, + /*(6777) KMOVQ*/ { 107, 1, 0x90, 3126}, + /*(6778) KMOVQ*/ { 108, 0, 0x90, 3134}, + /*(6779) KMOVQ*/ { 108, 0, 0x91, 3134}, + /*(6780) KMOVQ*/ { 107, 1, 0x92, 954}, + /*(6781) KMOVQ*/ { 107, 1, 0x93, 954}, + /*(6782) KNOTB*/ { 107, 1, 0x44, 1611}, + /*(6783) KNOTD*/ { 107, 1, 0x44, 1664}, + /*(6784) KNOTQ*/ { 107, 1, 0x44, 3126}, + /*(6785) KORB*/ { 101, 1, 0x45, 2921}, + /*(6786) KORD*/ { 101, 1, 0x45, 3092}, + /*(6787) KORQ*/ { 101, 1, 0x45, 3098}, + /*(6788) KORTESTB*/ { 107, 1, 0x98, 1611}, + /*(6789) KORTESTD*/ { 107, 1, 0x98, 1664}, + /*(6790) KORTESTQ*/ { 107, 1, 0x98, 3126}, + /*(6791) KSHIFTLB*/ { 107, 10, 0x32, 3141}, + /*(6792) KSHIFTLD*/ { 107, 10, 0x33, 3141}, + /*(6793) KSHIFTLQ*/ { 107, 10, 0x33, 1931}, + /*(6794) KSHIFTRB*/ { 107, 10, 0x30, 3141}, + /*(6795) KSHIFTRD*/ { 107, 10, 0x31, 3141}, + /*(6796) KSHIFTRQ*/ { 107, 10, 0x31, 1931}, + /*(6797) KTESTB*/ { 107, 1, 0x99, 1611}, + /*(6798) KTESTD*/ { 107, 1, 0x99, 1664}, + /*(6799) KTESTQ*/ { 107, 1, 0x99, 3126}, + /*(6800) KTESTW*/ { 107, 1, 0x99, 2906}, + /*(6801) KUNPCKDQ*/ { 101, 1, 0x4b, 3098}, + /*(6802) KUNPCKWD*/ { 101, 1, 0x4b, 2900}, + /*(6803) KXNORB*/ { 101, 1, 0x46, 2921}, + /*(6804) KXNORD*/ { 101, 1, 0x46, 3092}, + /*(6805) KXNORQ*/ { 101, 1, 0x46, 3098}, + /*(6806) KXORB*/ { 101, 1, 0x47, 2921}, + /*(6807) KXORD*/ { 101, 1, 0x47, 3092}, + /*(6808) KXORQ*/ { 101, 1, 0x47, 3098}, + /*(6809) VPMADD52HUQ*/ { 54, 1, 0xb5, 1362}, + /*(6810) VPMADD52HUQ*/ { 40, 102, 0xb5, 877}, + /*(6811) VPMADD52HUQ*/ { 54, 1, 0xb5, 1362}, + /*(6812) VPMADD52HUQ*/ { 40, 102, 0xb5, 877}, + /*(6813) VPMADD52HUQ*/ { 54, 1, 0xb5, 1362}, + /*(6814) VPMADD52HUQ*/ { 40, 102, 0xb5, 877}, + /*(6815) VPMADD52LUQ*/ { 54, 1, 0xb4, 1362}, + /*(6816) VPMADD52LUQ*/ { 40, 102, 0xb4, 877}, + /*(6817) VPMADD52LUQ*/ { 54, 1, 0xb4, 1362}, + /*(6818) VPMADD52LUQ*/ { 40, 102, 0xb4, 877}, + /*(6819) VPMADD52LUQ*/ { 54, 1, 0xb4, 1362}, + /*(6820) VPMADD52LUQ*/ { 40, 102, 0xb4, 877}, + /*(6821) VPERMB*/ { 54, 1, 0x8d, 1377}, + /*(6822) VPERMB*/ { 55, 135, 0x8d, 2019}, + /*(6823) VPERMB*/ { 54, 1, 0x8d, 1377}, + /*(6824) VPERMB*/ { 55, 135, 0x8d, 2019}, + /*(6825) VPERMB*/ { 54, 1, 0x8d, 1377}, + /*(6826) VPERMB*/ { 55, 135, 0x8d, 2019}, + /*(6827) VPERMI2B*/ { 54, 1, 0x75, 1377}, + /*(6828) VPERMI2B*/ { 55, 135, 0x75, 2019}, + /*(6829) VPERMI2B*/ { 54, 1, 0x75, 1377}, + /*(6830) VPERMI2B*/ { 55, 135, 0x75, 2019}, + /*(6831) VPERMI2B*/ { 54, 1, 0x75, 1377}, + /*(6832) VPERMI2B*/ { 55, 135, 0x75, 2019}, + /*(6833) VPERMT2B*/ { 54, 1, 0x7d, 1377}, + /*(6834) VPERMT2B*/ { 55, 135, 0x7d, 2019}, + /*(6835) VPERMT2B*/ { 54, 1, 0x7d, 1377}, + /*(6836) VPERMT2B*/ { 55, 135, 0x7d, 2019}, + /*(6837) VPERMT2B*/ { 54, 1, 0x7d, 1377}, + /*(6838) VPERMT2B*/ { 55, 135, 0x7d, 2019}, + /*(6839) VPMULTISHIFTQB*/ { 54, 1, 0x83, 1362}, + /*(6840) VPMULTISHIFTQB*/ { 40, 102, 0x83, 877}, + /*(6841) VPMULTISHIFTQB*/ { 54, 1, 0x83, 1362}, + /*(6842) VPMULTISHIFTQB*/ { 40, 102, 0x83, 877}, + /*(6843) VPMULTISHIFTQB*/ { 54, 1, 0x83, 1362}, + /*(6844) VPMULTISHIFTQB*/ { 40, 102, 0x83, 877}, + /*(6845) WBNOINVD*/ { 114, 59, 0x9, 4}, + /*(6846) PCONFIG*/ { 25, 19, 0x1, 3149}, + /*(6847) PCONFIG*/ { 25, 19, 0x1, 3149}, + /*(6848) VPOPCNTB*/ { 61, 1, 0x54, 1427}, + /*(6849) VPOPCNTB*/ { 80, 135, 0x54, 1418}, + /*(6850) VPOPCNTB*/ { 61, 1, 0x54, 1427}, + /*(6851) VPOPCNTB*/ { 80, 135, 0x54, 1418}, + /*(6852) VPOPCNTB*/ { 61, 1, 0x54, 1427}, + /*(6853) VPOPCNTB*/ { 80, 135, 0x54, 1418}, + /*(6854) VPOPCNTW*/ { 61, 1, 0x54, 1499}, + /*(6855) VPOPCNTW*/ { 80, 136, 0x54, 1490}, + /*(6856) VPOPCNTW*/ { 61, 1, 0x54, 1499}, + /*(6857) VPOPCNTW*/ { 80, 136, 0x54, 1490}, + /*(6858) VPOPCNTW*/ { 61, 1, 0x54, 1499}, + /*(6859) VPOPCNTW*/ { 80, 136, 0x54, 1490}, + /*(6860) VPSHUFBITQMB*/ { 56, 1, 0x8f, 2869}, + /*(6861) VPSHUFBITQMB*/ { 58, 135, 0x8f, 2019}, + /*(6862) VPSHUFBITQMB*/ { 56, 1, 0x8f, 2869}, + /*(6863) VPSHUFBITQMB*/ { 58, 135, 0x8f, 2019}, + /*(6864) VPSHUFBITQMB*/ { 56, 1, 0x8f, 2869}, + /*(6865) VPSHUFBITQMB*/ { 58, 135, 0x8f, 2019}, + /*(6866) VPCOMPRESSB*/ { 81, 183, 0x63, 2714}, + /*(6867) VPCOMPRESSB*/ { 61, 1, 0x63, 1427}, + /*(6868) VPCOMPRESSB*/ { 81, 183, 0x63, 2714}, + /*(6869) VPCOMPRESSB*/ { 61, 1, 0x63, 1427}, + /*(6870) VPCOMPRESSB*/ { 81, 183, 0x63, 2714}, + /*(6871) VPCOMPRESSB*/ { 61, 1, 0x63, 1427}, + /*(6872) VPCOMPRESSW*/ { 81, 184, 0x63, 2697}, + /*(6873) VPCOMPRESSW*/ { 61, 1, 0x63, 1499}, + /*(6874) VPCOMPRESSW*/ { 81, 184, 0x63, 2697}, + /*(6875) VPCOMPRESSW*/ { 61, 1, 0x63, 1499}, + /*(6876) VPCOMPRESSW*/ { 81, 184, 0x63, 2697}, + /*(6877) VPCOMPRESSW*/ { 61, 1, 0x63, 1499}, + /*(6878) VPEXPANDB*/ { 80, 183, 0x62, 1418}, + /*(6879) VPEXPANDB*/ { 61, 1, 0x62, 1427}, + /*(6880) VPEXPANDB*/ { 80, 183, 0x62, 1418}, + /*(6881) VPEXPANDB*/ { 61, 1, 0x62, 1427}, + /*(6882) VPEXPANDB*/ { 80, 183, 0x62, 1418}, + /*(6883) VPEXPANDB*/ { 61, 1, 0x62, 1427}, + /*(6884) VPEXPANDW*/ { 80, 184, 0x62, 1490}, + /*(6885) VPEXPANDW*/ { 61, 1, 0x62, 1499}, + /*(6886) VPEXPANDW*/ { 80, 184, 0x62, 1490}, + /*(6887) VPEXPANDW*/ { 61, 1, 0x62, 1499}, + /*(6888) VPEXPANDW*/ { 80, 184, 0x62, 1490}, + /*(6889) VPEXPANDW*/ { 61, 1, 0x62, 1499}, + /*(6890) VPSHLDD*/ { 54, 10, 0x71, 2666}, + /*(6891) VPSHLDD*/ { 40, 109, 0x71, 1028}, + /*(6892) VPSHLDD*/ { 54, 10, 0x71, 2666}, + /*(6893) VPSHLDD*/ { 40, 109, 0x71, 1028}, + /*(6894) VPSHLDD*/ { 54, 10, 0x71, 2666}, + /*(6895) VPSHLDD*/ { 40, 109, 0x71, 1028}, + /*(6896) VPSHLDQ*/ { 54, 10, 0x71, 2672}, + /*(6897) VPSHLDQ*/ { 40, 108, 0x71, 587}, + /*(6898) VPSHLDQ*/ { 54, 10, 0x71, 2672}, + /*(6899) VPSHLDQ*/ { 40, 108, 0x71, 587}, + /*(6900) VPSHLDQ*/ { 54, 10, 0x71, 2672}, + /*(6901) VPSHLDQ*/ { 40, 108, 0x71, 587}, + /*(6902) VPSHLDVD*/ { 54, 1, 0x71, 1377}, + /*(6903) VPSHLDVD*/ { 40, 103, 0x71, 1383}, + /*(6904) VPSHLDVD*/ { 54, 1, 0x71, 1377}, + /*(6905) VPSHLDVD*/ { 40, 103, 0x71, 1383}, + /*(6906) VPSHLDVD*/ { 54, 1, 0x71, 1377}, + /*(6907) VPSHLDVD*/ { 40, 103, 0x71, 1383}, + /*(6908) VPSHLDVQ*/ { 54, 1, 0x71, 1362}, + /*(6909) VPSHLDVQ*/ { 40, 102, 0x71, 877}, + /*(6910) VPSHLDVQ*/ { 54, 1, 0x71, 1362}, + /*(6911) VPSHLDVQ*/ { 40, 102, 0x71, 877}, + /*(6912) VPSHLDVQ*/ { 54, 1, 0x71, 1362}, + /*(6913) VPSHLDVQ*/ { 40, 102, 0x71, 877}, + /*(6914) VPSHLDVW*/ { 54, 1, 0x70, 1362}, + /*(6915) VPSHLDVW*/ { 55, 136, 0x70, 876}, + /*(6916) VPSHLDVW*/ { 54, 1, 0x70, 1362}, + /*(6917) VPSHLDVW*/ { 55, 136, 0x70, 876}, + /*(6918) VPSHLDVW*/ { 54, 1, 0x70, 1362}, + /*(6919) VPSHLDVW*/ { 55, 136, 0x70, 876}, + /*(6920) VPSHLDW*/ { 54, 10, 0x70, 2672}, + /*(6921) VPSHLDW*/ { 55, 137, 0x70, 1989}, + /*(6922) VPSHLDW*/ { 54, 10, 0x70, 2672}, + /*(6923) VPSHLDW*/ { 55, 137, 0x70, 1989}, + /*(6924) VPSHLDW*/ { 54, 10, 0x70, 2672}, + /*(6925) VPSHLDW*/ { 55, 137, 0x70, 1989}, + /*(6926) VPSHRDD*/ { 54, 10, 0x73, 2666}, + /*(6927) VPSHRDD*/ { 40, 109, 0x73, 1028}, + /*(6928) VPSHRDD*/ { 54, 10, 0x73, 2666}, + /*(6929) VPSHRDD*/ { 40, 109, 0x73, 1028}, + /*(6930) VPSHRDD*/ { 54, 10, 0x73, 2666}, + /*(6931) VPSHRDD*/ { 40, 109, 0x73, 1028}, + /*(6932) VPSHRDQ*/ { 54, 10, 0x73, 2672}, + /*(6933) VPSHRDQ*/ { 40, 108, 0x73, 587}, + /*(6934) VPSHRDQ*/ { 54, 10, 0x73, 2672}, + /*(6935) VPSHRDQ*/ { 40, 108, 0x73, 587}, + /*(6936) VPSHRDQ*/ { 54, 10, 0x73, 2672}, + /*(6937) VPSHRDQ*/ { 40, 108, 0x73, 587}, + /*(6938) VPSHRDVD*/ { 54, 1, 0x73, 1377}, + /*(6939) VPSHRDVD*/ { 40, 103, 0x73, 1383}, + /*(6940) VPSHRDVD*/ { 54, 1, 0x73, 1377}, + /*(6941) VPSHRDVD*/ { 40, 103, 0x73, 1383}, + /*(6942) VPSHRDVD*/ { 54, 1, 0x73, 1377}, + /*(6943) VPSHRDVD*/ { 40, 103, 0x73, 1383}, + /*(6944) VPSHRDVQ*/ { 54, 1, 0x73, 1362}, + /*(6945) VPSHRDVQ*/ { 40, 102, 0x73, 877}, + /*(6946) VPSHRDVQ*/ { 54, 1, 0x73, 1362}, + /*(6947) VPSHRDVQ*/ { 40, 102, 0x73, 877}, + /*(6948) VPSHRDVQ*/ { 54, 1, 0x73, 1362}, + /*(6949) VPSHRDVQ*/ { 40, 102, 0x73, 877}, + /*(6950) VPSHRDVW*/ { 54, 1, 0x72, 1362}, + /*(6951) VPSHRDVW*/ { 55, 136, 0x72, 876}, + /*(6952) VPSHRDVW*/ { 54, 1, 0x72, 1362}, + /*(6953) VPSHRDVW*/ { 55, 136, 0x72, 876}, + /*(6954) VPSHRDVW*/ { 54, 1, 0x72, 1362}, + /*(6955) VPSHRDVW*/ { 55, 136, 0x72, 876}, + /*(6956) VPSHRDW*/ { 54, 10, 0x72, 2672}, + /*(6957) VPSHRDW*/ { 55, 137, 0x72, 1989}, + /*(6958) VPSHRDW*/ { 54, 10, 0x72, 2672}, + /*(6959) VPSHRDW*/ { 55, 137, 0x72, 1989}, + /*(6960) VPSHRDW*/ { 54, 10, 0x72, 2672}, + /*(6961) VPSHRDW*/ { 55, 137, 0x72, 1989}, + /*(6962) GF2P8AFFINEINVQB*/ { 15, 75, 0xcf, 155}, + /*(6963) GF2P8AFFINEINVQB*/ { 14, 74, 0xcf, 121}, + /*(6964) GF2P8AFFINEQB*/ { 15, 75, 0xce, 155}, + /*(6965) GF2P8AFFINEQB*/ { 14, 74, 0xce, 121}, + /*(6966) GF2P8MULB*/ { 15, 71, 0xcf, 155}, + /*(6967) GF2P8MULB*/ { 14, 70, 0xcf, 121}, + /*(6968) VGF2P8AFFINEINVQB*/ { 54, 10, 0xcf, 2672}, + /*(6969) VGF2P8AFFINEINVQB*/ { 40, 108, 0xcf, 587}, + /*(6970) VGF2P8AFFINEINVQB*/ { 54, 10, 0xcf, 2672}, + /*(6971) VGF2P8AFFINEINVQB*/ { 40, 108, 0xcf, 587}, + /*(6972) VGF2P8AFFINEINVQB*/ { 54, 10, 0xcf, 2672}, + /*(6973) VGF2P8AFFINEINVQB*/ { 40, 108, 0xcf, 587}, + /*(6974) VGF2P8AFFINEINVQB*/ { 41, 10, 0xcf, 516}, + /*(6975) VGF2P8AFFINEINVQB*/ { 40, 9, 0xcf, 512}, + /*(6976) VGF2P8AFFINEINVQB*/ { 41, 10, 0xcf, 516}, + /*(6977) VGF2P8AFFINEINVQB*/ { 40, 9, 0xcf, 512}, + /*(6978) VGF2P8AFFINEQB*/ { 54, 10, 0xce, 2672}, + /*(6979) VGF2P8AFFINEQB*/ { 40, 108, 0xce, 587}, + /*(6980) VGF2P8AFFINEQB*/ { 54, 10, 0xce, 2672}, + /*(6981) VGF2P8AFFINEQB*/ { 40, 108, 0xce, 587}, + /*(6982) VGF2P8AFFINEQB*/ { 54, 10, 0xce, 2672}, + /*(6983) VGF2P8AFFINEQB*/ { 40, 108, 0xce, 587}, + /*(6984) VGF2P8AFFINEQB*/ { 41, 10, 0xce, 516}, + /*(6985) VGF2P8AFFINEQB*/ { 40, 9, 0xce, 512}, + /*(6986) VGF2P8AFFINEQB*/ { 41, 10, 0xce, 516}, + /*(6987) VGF2P8AFFINEQB*/ { 40, 9, 0xce, 512}, + /*(6988) VGF2P8MULB*/ { 54, 1, 0xcf, 1377}, + /*(6989) VGF2P8MULB*/ { 55, 135, 0xcf, 2019}, + /*(6990) VGF2P8MULB*/ { 54, 1, 0xcf, 1377}, + /*(6991) VGF2P8MULB*/ { 55, 135, 0xcf, 2019}, + /*(6992) VGF2P8MULB*/ { 54, 1, 0xcf, 1377}, + /*(6993) VGF2P8MULB*/ { 55, 135, 0xcf, 2019}, + /*(6994) VGF2P8MULB*/ { 41, 1, 0xcf, 1348}, + /*(6995) VGF2P8MULB*/ { 40, 0, 0xcf, 632}, + /*(6996) VGF2P8MULB*/ { 41, 1, 0xcf, 1348}, + /*(6997) VGF2P8MULB*/ { 40, 0, 0xcf, 632}, + /*(6998) VP2INTERSECTD*/ { 71, 1, 0x68, 3154}, + /*(6999) VP2INTERSECTD*/ { 115, 103, 0x68, 2604}, + /*(7000) VP2INTERSECTD*/ { 71, 1, 0x68, 3154}, + /*(7001) VP2INTERSECTD*/ { 115, 103, 0x68, 2604}, + /*(7002) VP2INTERSECTD*/ { 71, 1, 0x68, 3154}, + /*(7003) VP2INTERSECTD*/ { 115, 103, 0x68, 2604}, + /*(7004) VP2INTERSECTQ*/ { 71, 1, 0x68, 3162}, + /*(7005) VP2INTERSECTQ*/ { 115, 102, 0x68, 3170}, + /*(7006) VP2INTERSECTQ*/ { 71, 1, 0x68, 3162}, + /*(7007) VP2INTERSECTQ*/ { 115, 102, 0x68, 3170}, + /*(7008) VP2INTERSECTQ*/ { 71, 1, 0x68, 3162}, + /*(7009) VP2INTERSECTQ*/ { 115, 102, 0x68, 3170}, + /*(7010) AESDEC128KL*/ { 27, 70, 0xdd, 1}, + /*(7011) AESDEC256KL*/ { 27, 70, 0xdf, 1}, + /*(7012) AESDECWIDE128KL*/ { 11, 70, 0xd8, 3}, + /*(7013) AESDECWIDE256KL*/ { 11, 70, 0xd8, 6}, + /*(7014) AESENC128KL*/ { 27, 70, 0xdc, 1}, + /*(7015) AESENC256KL*/ { 27, 70, 0xde, 1}, + /*(7016) AESENCWIDE128KL*/ { 11, 70, 0xd8, 0}, + /*(7017) AESENCWIDE256KL*/ { 11, 70, 0xd8, 63}, + /*(7018) ENCODEKEY128*/ { 19, 71, 0xfa, 6}, + /*(7019) ENCODEKEY256*/ { 19, 71, 0xfb, 6}, + /*(7020) LOADIWKEY*/ { 19, 71, 0xdc, 6}, + /*(7021) HRESET*/ { 21, 75, 0xf0, 307}, + /*(7022) CLUI*/ { 21, 19, 0x1, 3176}, + /*(7023) SENDUIPI*/ { 20, 19, 0xc7, 16}, + /*(7024) STUI*/ { 21, 19, 0x1, 207}, + /*(7025) TESTUI*/ { 21, 19, 0x1, 3180}, + /*(7026) UIRET*/ { 21, 19, 0x1, 3184}, + /*(7027) LDTILECFG*/ { 116, 0, 0x49, 3188}, + /*(7028) STTILECFG*/ { 116, 0, 0x49, 3196}, + /*(7029) TDPBF16PS*/ { 101, 1, 0x5c, 2368}, + /*(7030) TDPBSSD*/ { 101, 1, 0x5e, 2337}, + /*(7031) TDPBSUD*/ { 101, 1, 0x5e, 2368}, + /*(7032) TDPBUSD*/ { 101, 1, 0x5e, 1348}, + /*(7033) TDPBUUD*/ { 101, 1, 0x5e, 2380}, + /*(7034) TILELOADD*/ { 117, 0, 0x4b, 3204}, + /*(7035) TILELOADDT1*/ { 117, 0, 0x4b, 3212}, + /*(7036) TILERELEASE*/ { 118, 1, 0x49, 3220}, + /*(7037) TILESTORED*/ { 117, 0, 0x4b, 3230}, + /*(7038) TILEZERO*/ { 119, 1, 0x49, 3238}, + /*(7039) ENQCMD*/ { 27, 70, 0xf8, 9}, + /*(7040) ENQCMDS*/ { 27, 70, 0xf8, 1}, + /*(7041) XRESLDTRK*/ { 21, 19, 0x1, 3247}, + /*(7042) XSUSLDTRK*/ { 21, 19, 0x1, 3251}, + /*(7043) SERIALIZE*/ { 25, 19, 0x1, 3255}, + /*(7044) SEAMCALL*/ { 25, 19, 0x1, 3260}, + /*(7045) SEAMOPS*/ { 25, 19, 0x1, 3265}, + /*(7046) SEAMRET*/ { 25, 19, 0x1, 3270}, + /*(7047) TDCALL*/ { 25, 19, 0x1, 3275}, + /*(7048) TDCALL*/ { 25, 19, 0x1, 3275}, + /*(7049) VADDPH*/ { 54, 1, 0x58, 3280}, + /*(7050) VADDPH*/ { 40, 185, 0x58, 3286}, + /*(7051) VADDPH*/ { 54, 1, 0x58, 3280}, + /*(7052) VADDPH*/ { 40, 185, 0x58, 3286}, + /*(7053) VADDPH*/ { 54, 1, 0x58, 3280}, + /*(7054) VADDPH*/ { 54, 101, 0x58, 3290}, + /*(7055) VADDPH*/ { 40, 185, 0x58, 3286}, + /*(7056) VADDSH*/ { 54, 113, 0x58, 3296}, + /*(7057) VADDSH*/ { 54, 104, 0x58, 3302}, + /*(7058) VADDSH*/ { 55, 186, 0x58, 267}, + /*(7059) VCMPPH*/ { 56, 10, 0xc2, 3308}, + /*(7060) VCMPPH*/ { 57, 187, 0xc2, 671}, + /*(7061) VCMPPH*/ { 56, 10, 0xc2, 3308}, + /*(7062) VCMPPH*/ { 57, 187, 0xc2, 671}, + /*(7063) VCMPPH*/ { 56, 10, 0xc2, 3308}, + /*(7064) VCMPPH*/ { 56, 107, 0xc2, 3315}, + /*(7065) VCMPPH*/ { 57, 187, 0xc2, 671}, + /*(7066) VCMPSH*/ { 56, 188, 0xc2, 3322}, + /*(7067) VCMPSH*/ { 56, 110, 0xc2, 3329}, + /*(7068) VCMPSH*/ { 58, 189, 0xc2, 1253}, + /*(7069) VCOMISH*/ { 59, 113, 0x2f, 3336}, + /*(7070) VCOMISH*/ { 59, 114, 0x2f, 3347}, + /*(7071) VCOMISH*/ { 60, 186, 0x2f, 3358}, + /*(7072) VCVTDQ2PH*/ { 61, 1, 0x5b, 3368}, + /*(7073) VCVTDQ2PH*/ { 62, 103, 0x5b, 3377}, + /*(7074) VCVTDQ2PH*/ { 61, 1, 0x5b, 3368}, + /*(7075) VCVTDQ2PH*/ { 62, 103, 0x5b, 3377}, + /*(7076) VCVTDQ2PH*/ { 61, 1, 0x5b, 3368}, + /*(7077) VCVTDQ2PH*/ { 61, 101, 0x5b, 3384}, + /*(7078) VCVTDQ2PH*/ { 62, 103, 0x5b, 3377}, + /*(7079) VCVTPD2PH*/ { 61, 1, 0x5a, 3393}, + /*(7080) VCVTPD2PH*/ { 62, 102, 0x5a, 3402}, + /*(7081) VCVTPD2PH*/ { 61, 1, 0x5a, 3393}, + /*(7082) VCVTPD2PH*/ { 62, 102, 0x5a, 3402}, + /*(7083) VCVTPD2PH*/ { 61, 1, 0x5a, 3393}, + /*(7084) VCVTPD2PH*/ { 61, 101, 0x5a, 3409}, + /*(7085) VCVTPD2PH*/ { 62, 102, 0x5a, 3402}, + /*(7086) VCVTPH2DQ*/ { 61, 1, 0x5b, 3418}, + /*(7087) VCVTPH2DQ*/ { 62, 190, 0x5b, 3427}, + /*(7088) VCVTPH2DQ*/ { 61, 1, 0x5b, 3418}, + /*(7089) VCVTPH2DQ*/ { 62, 190, 0x5b, 3427}, + /*(7090) VCVTPH2DQ*/ { 61, 1, 0x5b, 3418}, + /*(7091) VCVTPH2DQ*/ { 61, 101, 0x5b, 3434}, + /*(7092) VCVTPH2DQ*/ { 62, 190, 0x5b, 3427}, + /*(7093) VCVTPH2PD*/ { 61, 1, 0x5a, 3368}, + /*(7094) VCVTPH2PD*/ { 62, 191, 0x5a, 3377}, + /*(7095) VCVTPH2PD*/ { 61, 1, 0x5a, 3368}, + /*(7096) VCVTPH2PD*/ { 62, 191, 0x5a, 3377}, + /*(7097) VCVTPH2PD*/ { 61, 1, 0x5a, 3368}, + /*(7098) VCVTPH2PD*/ { 61, 119, 0x5a, 3384}, + /*(7099) VCVTPH2PD*/ { 62, 191, 0x5a, 3377}, + /*(7100) VCVTPH2PSX*/ { 61, 1, 0x13, 3443}, + /*(7101) VCVTPH2PSX*/ { 62, 190, 0x13, 3452}, + /*(7102) VCVTPH2PSX*/ { 61, 1, 0x13, 3443}, + /*(7103) VCVTPH2PSX*/ { 62, 190, 0x13, 3452}, + /*(7104) VCVTPH2PSX*/ { 61, 1, 0x13, 3443}, + /*(7105) VCVTPH2PSX*/ { 61, 119, 0x13, 3459}, + /*(7106) VCVTPH2PSX*/ { 62, 190, 0x13, 3452}, + /*(7107) VCVTPH2QQ*/ { 61, 1, 0x7b, 3418}, + /*(7108) VCVTPH2QQ*/ { 62, 191, 0x7b, 3427}, + /*(7109) VCVTPH2QQ*/ { 61, 1, 0x7b, 3418}, + /*(7110) VCVTPH2QQ*/ { 62, 191, 0x7b, 3427}, + /*(7111) VCVTPH2QQ*/ { 61, 1, 0x7b, 3418}, + /*(7112) VCVTPH2QQ*/ { 61, 101, 0x7b, 3434}, + /*(7113) VCVTPH2QQ*/ { 62, 191, 0x7b, 3427}, + /*(7114) VCVTPH2UDQ*/ { 61, 1, 0x79, 3368}, + /*(7115) VCVTPH2UDQ*/ { 62, 190, 0x79, 3377}, + /*(7116) VCVTPH2UDQ*/ { 61, 1, 0x79, 3368}, + /*(7117) VCVTPH2UDQ*/ { 62, 190, 0x79, 3377}, + /*(7118) VCVTPH2UDQ*/ { 61, 1, 0x79, 3368}, + /*(7119) VCVTPH2UDQ*/ { 61, 101, 0x79, 3384}, + /*(7120) VCVTPH2UDQ*/ { 62, 190, 0x79, 3377}, + /*(7121) VCVTPH2UQQ*/ { 61, 1, 0x79, 3418}, + /*(7122) VCVTPH2UQQ*/ { 62, 191, 0x79, 3427}, + /*(7123) VCVTPH2UQQ*/ { 61, 1, 0x79, 3418}, + /*(7124) VCVTPH2UQQ*/ { 62, 191, 0x79, 3427}, + /*(7125) VCVTPH2UQQ*/ { 61, 1, 0x79, 3418}, + /*(7126) VCVTPH2UQQ*/ { 61, 101, 0x79, 3434}, + /*(7127) VCVTPH2UQQ*/ { 62, 191, 0x79, 3427}, + /*(7128) VCVTPH2UW*/ { 61, 1, 0x7d, 3368}, + /*(7129) VCVTPH2UW*/ { 62, 185, 0x7d, 3377}, + /*(7130) VCVTPH2UW*/ { 61, 1, 0x7d, 3368}, + /*(7131) VCVTPH2UW*/ { 62, 185, 0x7d, 3377}, + /*(7132) VCVTPH2UW*/ { 61, 1, 0x7d, 3368}, + /*(7133) VCVTPH2UW*/ { 61, 101, 0x7d, 3384}, + /*(7134) VCVTPH2UW*/ { 62, 185, 0x7d, 3377}, + /*(7135) VCVTPH2W*/ { 61, 1, 0x7d, 3418}, + /*(7136) VCVTPH2W*/ { 62, 185, 0x7d, 3427}, + /*(7137) VCVTPH2W*/ { 61, 1, 0x7d, 3418}, + /*(7138) VCVTPH2W*/ { 62, 185, 0x7d, 3427}, + /*(7139) VCVTPH2W*/ { 61, 1, 0x7d, 3418}, + /*(7140) VCVTPH2W*/ { 61, 101, 0x7d, 3434}, + /*(7141) VCVTPH2W*/ { 62, 185, 0x7d, 3427}, + /*(7142) VCVTPS2PHX*/ { 61, 1, 0x1d, 3418}, + /*(7143) VCVTPS2PHX*/ { 62, 103, 0x1d, 3427}, + /*(7144) VCVTPS2PHX*/ { 61, 1, 0x1d, 3418}, + /*(7145) VCVTPS2PHX*/ { 62, 103, 0x1d, 3427}, + /*(7146) VCVTPS2PHX*/ { 61, 1, 0x1d, 3418}, + /*(7147) VCVTPS2PHX*/ { 61, 101, 0x1d, 3434}, + /*(7148) VCVTPS2PHX*/ { 62, 103, 0x1d, 3427}, + /*(7149) VCVTQQ2PH*/ { 61, 1, 0x5b, 3468}, + /*(7150) VCVTQQ2PH*/ { 62, 102, 0x5b, 3477}, + /*(7151) VCVTQQ2PH*/ { 61, 1, 0x5b, 3468}, + /*(7152) VCVTQQ2PH*/ { 62, 102, 0x5b, 3477}, + /*(7153) VCVTQQ2PH*/ { 61, 1, 0x5b, 3468}, + /*(7154) VCVTQQ2PH*/ { 61, 101, 0x5b, 3484}, + /*(7155) VCVTQQ2PH*/ { 62, 102, 0x5b, 3477}, + /*(7156) VCVTSD2SH*/ { 54, 113, 0x5a, 3493}, + /*(7157) VCVTSD2SH*/ { 54, 104, 0x5a, 3499}, + /*(7158) VCVTSD2SH*/ { 55, 192, 0x5a, 3505}, + /*(7159) VCVTSH2SD*/ { 54, 113, 0x5a, 3296}, + /*(7160) VCVTSH2SD*/ { 54, 114, 0x5a, 3302}, + /*(7161) VCVTSH2SD*/ { 55, 186, 0x5a, 267}, + /*(7162) VCVTSH2SI*/ { 64, 113, 0x2d, 3510}, + /*(7163) VCVTSH2SI*/ { 64, 104, 0x2d, 3522}, + /*(7164) VCVTSH2SI*/ { 66, 193, 0x2d, 3534}, + /*(7165) VCVTSH2SI*/ { 113, 113, 0x2d, 3545}, + /*(7166) VCVTSH2SI*/ { 113, 104, 0x2d, 3556}, + /*(7167) VCVTSH2SI*/ { 120, 193, 0x2d, 3567}, + /*(7168) VCVTSH2SI*/ { 64, 113, 0x2d, 3577}, + /*(7169) VCVTSH2SI*/ { 64, 104, 0x2d, 3589}, + /*(7170) VCVTSH2SI*/ { 66, 193, 0x2d, 3601}, + /*(7171) VCVTSH2SS*/ { 54, 113, 0x13, 3612}, + /*(7172) VCVTSH2SS*/ { 54, 114, 0x13, 3618}, + /*(7173) VCVTSH2SS*/ { 55, 186, 0x13, 3624}, + /*(7174) VCVTSH2USI*/ { 64, 113, 0x79, 3510}, + /*(7175) VCVTSH2USI*/ { 64, 104, 0x79, 3522}, + /*(7176) VCVTSH2USI*/ { 66, 193, 0x79, 3534}, + /*(7177) VCVTSH2USI*/ { 113, 113, 0x79, 3545}, + /*(7178) VCVTSH2USI*/ { 113, 104, 0x79, 3556}, + /*(7179) VCVTSH2USI*/ { 120, 193, 0x79, 3567}, + /*(7180) VCVTSH2USI*/ { 64, 113, 0x79, 3577}, + /*(7181) VCVTSH2USI*/ { 64, 104, 0x79, 3589}, + /*(7182) VCVTSH2USI*/ { 66, 193, 0x79, 3601}, + /*(7183) VCVTSI2SH*/ { 71, 113, 0x2a, 3629}, + /*(7184) VCVTSI2SH*/ { 71, 104, 0x2a, 3637}, + /*(7185) VCVTSI2SH*/ { 70, 194, 0x2a, 3645}, + /*(7186) VCVTSI2SH*/ { 72, 113, 0x2a, 3652}, + /*(7187) VCVTSI2SH*/ { 72, 104, 0x2a, 3659}, + /*(7188) VCVTSI2SH*/ { 69, 194, 0x2a, 3666}, + /*(7189) VCVTSI2SH*/ { 71, 113, 0x2a, 3672}, + /*(7190) VCVTSI2SH*/ { 71, 104, 0x2a, 3680}, + /*(7191) VCVTSI2SH*/ { 70, 195, 0x2a, 3688}, + /*(7192) VCVTSS2SH*/ { 54, 113, 0x1d, 3280}, + /*(7193) VCVTSS2SH*/ { 54, 104, 0x1d, 3290}, + /*(7194) VCVTSS2SH*/ { 55, 196, 0x1d, 3695}, + /*(7195) VCVTTPH2DQ*/ { 61, 1, 0x5b, 3700}, + /*(7196) VCVTTPH2DQ*/ { 62, 190, 0x5b, 3709}, + /*(7197) VCVTTPH2DQ*/ { 61, 1, 0x5b, 3700}, + /*(7198) VCVTTPH2DQ*/ { 62, 190, 0x5b, 3709}, + /*(7199) VCVTTPH2DQ*/ { 61, 1, 0x5b, 3700}, + /*(7200) VCVTTPH2DQ*/ { 61, 119, 0x5b, 3716}, + /*(7201) VCVTTPH2DQ*/ { 62, 190, 0x5b, 3709}, + /*(7202) VCVTTPH2QQ*/ { 61, 1, 0x7a, 3418}, + /*(7203) VCVTTPH2QQ*/ { 62, 191, 0x7a, 3427}, + /*(7204) VCVTTPH2QQ*/ { 61, 1, 0x7a, 3418}, + /*(7205) VCVTTPH2QQ*/ { 62, 191, 0x7a, 3427}, + /*(7206) VCVTTPH2QQ*/ { 61, 1, 0x7a, 3418}, + /*(7207) VCVTTPH2QQ*/ { 61, 119, 0x7a, 3434}, + /*(7208) VCVTTPH2QQ*/ { 62, 191, 0x7a, 3427}, + /*(7209) VCVTTPH2UDQ*/ { 61, 1, 0x78, 3368}, + /*(7210) VCVTTPH2UDQ*/ { 62, 190, 0x78, 3377}, + /*(7211) VCVTTPH2UDQ*/ { 61, 1, 0x78, 3368}, + /*(7212) VCVTTPH2UDQ*/ { 62, 190, 0x78, 3377}, + /*(7213) VCVTTPH2UDQ*/ { 61, 1, 0x78, 3368}, + /*(7214) VCVTTPH2UDQ*/ { 61, 119, 0x78, 3384}, + /*(7215) VCVTTPH2UDQ*/ { 62, 190, 0x78, 3377}, + /*(7216) VCVTTPH2UQQ*/ { 61, 1, 0x78, 3418}, + /*(7217) VCVTTPH2UQQ*/ { 62, 191, 0x78, 3427}, + /*(7218) VCVTTPH2UQQ*/ { 61, 1, 0x78, 3418}, + /*(7219) VCVTTPH2UQQ*/ { 62, 191, 0x78, 3427}, + /*(7220) VCVTTPH2UQQ*/ { 61, 1, 0x78, 3418}, + /*(7221) VCVTTPH2UQQ*/ { 61, 119, 0x78, 3434}, + /*(7222) VCVTTPH2UQQ*/ { 62, 191, 0x78, 3427}, + /*(7223) VCVTTPH2UW*/ { 61, 1, 0x7c, 3368}, + /*(7224) VCVTTPH2UW*/ { 62, 185, 0x7c, 3377}, + /*(7225) VCVTTPH2UW*/ { 61, 1, 0x7c, 3368}, + /*(7226) VCVTTPH2UW*/ { 62, 185, 0x7c, 3377}, + /*(7227) VCVTTPH2UW*/ { 61, 1, 0x7c, 3368}, + /*(7228) VCVTTPH2UW*/ { 61, 119, 0x7c, 3384}, + /*(7229) VCVTTPH2UW*/ { 62, 185, 0x7c, 3377}, + /*(7230) VCVTTPH2W*/ { 61, 1, 0x7c, 3418}, + /*(7231) VCVTTPH2W*/ { 62, 185, 0x7c, 3427}, + /*(7232) VCVTTPH2W*/ { 61, 1, 0x7c, 3418}, + /*(7233) VCVTTPH2W*/ { 62, 185, 0x7c, 3427}, + /*(7234) VCVTTPH2W*/ { 61, 1, 0x7c, 3418}, + /*(7235) VCVTTPH2W*/ { 61, 119, 0x7c, 3434}, + /*(7236) VCVTTPH2W*/ { 62, 185, 0x7c, 3427}, + /*(7237) VCVTTSH2SI*/ { 64, 113, 0x2c, 3510}, + /*(7238) VCVTTSH2SI*/ { 64, 114, 0x2c, 3522}, + /*(7239) VCVTTSH2SI*/ { 66, 193, 0x2c, 3534}, + /*(7240) VCVTTSH2SI*/ { 113, 113, 0x2c, 3545}, + /*(7241) VCVTTSH2SI*/ { 113, 114, 0x2c, 3556}, + /*(7242) VCVTTSH2SI*/ { 120, 193, 0x2c, 3567}, + /*(7243) VCVTTSH2SI*/ { 64, 113, 0x2c, 3577}, + /*(7244) VCVTTSH2SI*/ { 64, 114, 0x2c, 3589}, + /*(7245) VCVTTSH2SI*/ { 66, 193, 0x2c, 3601}, + /*(7246) VCVTTSH2USI*/ { 64, 113, 0x78, 3510}, + /*(7247) VCVTTSH2USI*/ { 64, 114, 0x78, 3522}, + /*(7248) VCVTTSH2USI*/ { 66, 193, 0x78, 3534}, + /*(7249) VCVTTSH2USI*/ { 113, 113, 0x78, 3545}, + /*(7250) VCVTTSH2USI*/ { 113, 114, 0x78, 3556}, + /*(7251) VCVTTSH2USI*/ { 120, 193, 0x78, 3567}, + /*(7252) VCVTTSH2USI*/ { 64, 113, 0x78, 3577}, + /*(7253) VCVTTSH2USI*/ { 64, 114, 0x78, 3589}, + /*(7254) VCVTTSH2USI*/ { 66, 193, 0x78, 3601}, + /*(7255) VCVTUDQ2PH*/ { 61, 1, 0x7a, 3725}, + /*(7256) VCVTUDQ2PH*/ { 62, 103, 0x7a, 3734}, + /*(7257) VCVTUDQ2PH*/ { 61, 1, 0x7a, 3725}, + /*(7258) VCVTUDQ2PH*/ { 62, 103, 0x7a, 3734}, + /*(7259) VCVTUDQ2PH*/ { 61, 1, 0x7a, 3725}, + /*(7260) VCVTUDQ2PH*/ { 61, 101, 0x7a, 3741}, + /*(7261) VCVTUDQ2PH*/ { 62, 103, 0x7a, 3734}, + /*(7262) VCVTUQQ2PH*/ { 61, 1, 0x7a, 3750}, + /*(7263) VCVTUQQ2PH*/ { 62, 102, 0x7a, 3759}, + /*(7264) VCVTUQQ2PH*/ { 61, 1, 0x7a, 3750}, + /*(7265) VCVTUQQ2PH*/ { 62, 102, 0x7a, 3759}, + /*(7266) VCVTUQQ2PH*/ { 61, 1, 0x7a, 3750}, + /*(7267) VCVTUQQ2PH*/ { 61, 101, 0x7a, 3766}, + /*(7268) VCVTUQQ2PH*/ { 62, 102, 0x7a, 3759}, + /*(7269) VCVTUSI2SH*/ { 71, 113, 0x7b, 3629}, + /*(7270) VCVTUSI2SH*/ { 71, 104, 0x7b, 3637}, + /*(7271) VCVTUSI2SH*/ { 70, 194, 0x7b, 3645}, + /*(7272) VCVTUSI2SH*/ { 72, 113, 0x7b, 3652}, + /*(7273) VCVTUSI2SH*/ { 72, 104, 0x7b, 3659}, + /*(7274) VCVTUSI2SH*/ { 69, 194, 0x7b, 3666}, + /*(7275) VCVTUSI2SH*/ { 71, 113, 0x7b, 3672}, + /*(7276) VCVTUSI2SH*/ { 71, 104, 0x7b, 3680}, + /*(7277) VCVTUSI2SH*/ { 70, 195, 0x7b, 3688}, + /*(7278) VCVTUW2PH*/ { 61, 1, 0x7d, 3725}, + /*(7279) VCVTUW2PH*/ { 62, 185, 0x7d, 3734}, + /*(7280) VCVTUW2PH*/ { 61, 1, 0x7d, 3725}, + /*(7281) VCVTUW2PH*/ { 62, 185, 0x7d, 3734}, + /*(7282) VCVTUW2PH*/ { 61, 1, 0x7d, 3725}, + /*(7283) VCVTUW2PH*/ { 61, 101, 0x7d, 3741}, + /*(7284) VCVTUW2PH*/ { 62, 185, 0x7d, 3734}, + /*(7285) VCVTW2PH*/ { 61, 1, 0x7d, 3700}, + /*(7286) VCVTW2PH*/ { 62, 185, 0x7d, 3709}, + /*(7287) VCVTW2PH*/ { 61, 1, 0x7d, 3700}, + /*(7288) VCVTW2PH*/ { 62, 185, 0x7d, 3709}, + /*(7289) VCVTW2PH*/ { 61, 1, 0x7d, 3700}, + /*(7290) VCVTW2PH*/ { 61, 101, 0x7d, 3716}, + /*(7291) VCVTW2PH*/ { 62, 185, 0x7d, 3709}, + /*(7292) VDIVPH*/ { 54, 1, 0x5e, 3280}, + /*(7293) VDIVPH*/ { 40, 185, 0x5e, 3286}, + /*(7294) VDIVPH*/ { 54, 1, 0x5e, 3280}, + /*(7295) VDIVPH*/ { 40, 185, 0x5e, 3286}, + /*(7296) VDIVPH*/ { 54, 1, 0x5e, 3280}, + /*(7297) VDIVPH*/ { 54, 101, 0x5e, 3290}, + /*(7298) VDIVPH*/ { 40, 185, 0x5e, 3286}, + /*(7299) VDIVSH*/ { 54, 113, 0x5e, 3296}, + /*(7300) VDIVSH*/ { 54, 104, 0x5e, 3302}, + /*(7301) VDIVSH*/ { 55, 186, 0x5e, 267}, + /*(7302) VFCMADDCPH*/ { 54, 1, 0x56, 3775}, + /*(7303) VFCMADDCPH*/ { 40, 103, 0x56, 3781}, + /*(7304) VFCMADDCPH*/ { 54, 1, 0x56, 3775}, + /*(7305) VFCMADDCPH*/ { 40, 103, 0x56, 3781}, + /*(7306) VFCMADDCPH*/ { 54, 1, 0x56, 3775}, + /*(7307) VFCMADDCPH*/ { 54, 101, 0x56, 3785}, + /*(7308) VFCMADDCPH*/ { 40, 103, 0x56, 3781}, + /*(7309) VFCMADDCSH*/ { 54, 113, 0x57, 3775}, + /*(7310) VFCMADDCSH*/ { 54, 104, 0x57, 3785}, + /*(7311) VFCMADDCSH*/ { 55, 196, 0x57, 3791}, + /*(7312) VFCMULCPH*/ { 54, 1, 0xd6, 3775}, + /*(7313) VFCMULCPH*/ { 40, 103, 0xd6, 3781}, + /*(7314) VFCMULCPH*/ { 54, 1, 0xd6, 3775}, + /*(7315) VFCMULCPH*/ { 40, 103, 0xd6, 3781}, + /*(7316) VFCMULCPH*/ { 54, 1, 0xd6, 3775}, + /*(7317) VFCMULCPH*/ { 54, 101, 0xd6, 3785}, + /*(7318) VFCMULCPH*/ { 40, 103, 0xd6, 3781}, + /*(7319) VFCMULCSH*/ { 54, 113, 0xd7, 3775}, + /*(7320) VFCMULCSH*/ { 54, 104, 0xd7, 3785}, + /*(7321) VFCMULCSH*/ { 55, 196, 0xd7, 3791}, + /*(7322) VFMADD132PH*/ { 54, 1, 0x98, 3796}, + /*(7323) VFMADD132PH*/ { 40, 185, 0x98, 1756}, + /*(7324) VFMADD132PH*/ { 54, 1, 0x98, 3796}, + /*(7325) VFMADD132PH*/ { 40, 185, 0x98, 1756}, + /*(7326) VFMADD132PH*/ { 54, 1, 0x98, 3796}, + /*(7327) VFMADD132PH*/ { 54, 101, 0x98, 3802}, + /*(7328) VFMADD132PH*/ { 40, 185, 0x98, 1756}, + /*(7329) VFMADD132SH*/ { 54, 113, 0x99, 3796}, + /*(7330) VFMADD132SH*/ { 54, 104, 0x99, 3802}, + /*(7331) VFMADD132SH*/ { 55, 186, 0x99, 3808}, + /*(7332) VFMADD213PH*/ { 54, 1, 0xa8, 3796}, + /*(7333) VFMADD213PH*/ { 40, 185, 0xa8, 1756}, + /*(7334) VFMADD213PH*/ { 54, 1, 0xa8, 3796}, + /*(7335) VFMADD213PH*/ { 40, 185, 0xa8, 1756}, + /*(7336) VFMADD213PH*/ { 54, 1, 0xa8, 3796}, + /*(7337) VFMADD213PH*/ { 54, 101, 0xa8, 3802}, + /*(7338) VFMADD213PH*/ { 40, 185, 0xa8, 1756}, + /*(7339) VFMADD213SH*/ { 54, 113, 0xa9, 3796}, + /*(7340) VFMADD213SH*/ { 54, 104, 0xa9, 3802}, + /*(7341) VFMADD213SH*/ { 55, 186, 0xa9, 3808}, + /*(7342) VFMADD231PH*/ { 54, 1, 0xb8, 3796}, + /*(7343) VFMADD231PH*/ { 40, 185, 0xb8, 1756}, + /*(7344) VFMADD231PH*/ { 54, 1, 0xb8, 3796}, + /*(7345) VFMADD231PH*/ { 40, 185, 0xb8, 1756}, + /*(7346) VFMADD231PH*/ { 54, 1, 0xb8, 3796}, + /*(7347) VFMADD231PH*/ { 54, 101, 0xb8, 3802}, + /*(7348) VFMADD231PH*/ { 40, 185, 0xb8, 1756}, + /*(7349) VFMADD231SH*/ { 54, 113, 0xb9, 3796}, + /*(7350) VFMADD231SH*/ { 54, 104, 0xb9, 3802}, + /*(7351) VFMADD231SH*/ { 55, 186, 0xb9, 3808}, + /*(7352) VFMADDCPH*/ { 54, 1, 0x56, 3813}, + /*(7353) VFMADDCPH*/ { 40, 103, 0x56, 38}, + /*(7354) VFMADDCPH*/ { 54, 1, 0x56, 3813}, + /*(7355) VFMADDCPH*/ { 40, 103, 0x56, 38}, + /*(7356) VFMADDCPH*/ { 54, 1, 0x56, 3813}, + /*(7357) VFMADDCPH*/ { 54, 101, 0x56, 3819}, + /*(7358) VFMADDCPH*/ { 40, 103, 0x56, 38}, + /*(7359) VFMADDCSH*/ { 54, 113, 0x57, 3813}, + /*(7360) VFMADDCSH*/ { 54, 104, 0x57, 3819}, + /*(7361) VFMADDCSH*/ { 55, 196, 0x57, 37}, + /*(7362) VFMADDSUB132PH*/ { 54, 1, 0x96, 3796}, + /*(7363) VFMADDSUB132PH*/ { 40, 185, 0x96, 1756}, + /*(7364) VFMADDSUB132PH*/ { 54, 1, 0x96, 3796}, + /*(7365) VFMADDSUB132PH*/ { 40, 185, 0x96, 1756}, + /*(7366) VFMADDSUB132PH*/ { 54, 1, 0x96, 3796}, + /*(7367) VFMADDSUB132PH*/ { 54, 101, 0x96, 3802}, + /*(7368) VFMADDSUB132PH*/ { 40, 185, 0x96, 1756}, + /*(7369) VFMADDSUB213PH*/ { 54, 1, 0xa6, 3796}, + /*(7370) VFMADDSUB213PH*/ { 40, 185, 0xa6, 1756}, + /*(7371) VFMADDSUB213PH*/ { 54, 1, 0xa6, 3796}, + /*(7372) VFMADDSUB213PH*/ { 40, 185, 0xa6, 1756}, + /*(7373) VFMADDSUB213PH*/ { 54, 1, 0xa6, 3796}, + /*(7374) VFMADDSUB213PH*/ { 54, 101, 0xa6, 3802}, + /*(7375) VFMADDSUB213PH*/ { 40, 185, 0xa6, 1756}, + /*(7376) VFMADDSUB231PH*/ { 54, 1, 0xb6, 3796}, + /*(7377) VFMADDSUB231PH*/ { 40, 185, 0xb6, 1756}, + /*(7378) VFMADDSUB231PH*/ { 54, 1, 0xb6, 3796}, + /*(7379) VFMADDSUB231PH*/ { 40, 185, 0xb6, 1756}, + /*(7380) VFMADDSUB231PH*/ { 54, 1, 0xb6, 3796}, + /*(7381) VFMADDSUB231PH*/ { 54, 101, 0xb6, 3802}, + /*(7382) VFMADDSUB231PH*/ { 40, 185, 0xb6, 1756}, + /*(7383) VFMSUB132PH*/ { 54, 1, 0x9a, 3796}, + /*(7384) VFMSUB132PH*/ { 40, 185, 0x9a, 1756}, + /*(7385) VFMSUB132PH*/ { 54, 1, 0x9a, 3796}, + /*(7386) VFMSUB132PH*/ { 40, 185, 0x9a, 1756}, + /*(7387) VFMSUB132PH*/ { 54, 1, 0x9a, 3796}, + /*(7388) VFMSUB132PH*/ { 54, 101, 0x9a, 3802}, + /*(7389) VFMSUB132PH*/ { 40, 185, 0x9a, 1756}, + /*(7390) VFMSUB132SH*/ { 54, 113, 0x9b, 3796}, + /*(7391) VFMSUB132SH*/ { 54, 104, 0x9b, 3802}, + /*(7392) VFMSUB132SH*/ { 55, 186, 0x9b, 3808}, + /*(7393) VFMSUB213PH*/ { 54, 1, 0xaa, 3796}, + /*(7394) VFMSUB213PH*/ { 40, 185, 0xaa, 1756}, + /*(7395) VFMSUB213PH*/ { 54, 1, 0xaa, 3796}, + /*(7396) VFMSUB213PH*/ { 40, 185, 0xaa, 1756}, + /*(7397) VFMSUB213PH*/ { 54, 1, 0xaa, 3796}, + /*(7398) VFMSUB213PH*/ { 54, 101, 0xaa, 3802}, + /*(7399) VFMSUB213PH*/ { 40, 185, 0xaa, 1756}, + /*(7400) VFMSUB213SH*/ { 54, 113, 0xab, 3796}, + /*(7401) VFMSUB213SH*/ { 54, 104, 0xab, 3802}, + /*(7402) VFMSUB213SH*/ { 55, 186, 0xab, 3808}, + /*(7403) VFMSUB231PH*/ { 54, 1, 0xba, 3796}, + /*(7404) VFMSUB231PH*/ { 40, 185, 0xba, 1756}, + /*(7405) VFMSUB231PH*/ { 54, 1, 0xba, 3796}, + /*(7406) VFMSUB231PH*/ { 40, 185, 0xba, 1756}, + /*(7407) VFMSUB231PH*/ { 54, 1, 0xba, 3796}, + /*(7408) VFMSUB231PH*/ { 54, 101, 0xba, 3802}, + /*(7409) VFMSUB231PH*/ { 40, 185, 0xba, 1756}, + /*(7410) VFMSUB231SH*/ { 54, 113, 0xbb, 3796}, + /*(7411) VFMSUB231SH*/ { 54, 104, 0xbb, 3802}, + /*(7412) VFMSUB231SH*/ { 55, 186, 0xbb, 3808}, + /*(7413) VFMSUBADD132PH*/ { 54, 1, 0x97, 3796}, + /*(7414) VFMSUBADD132PH*/ { 40, 185, 0x97, 1756}, + /*(7415) VFMSUBADD132PH*/ { 54, 1, 0x97, 3796}, + /*(7416) VFMSUBADD132PH*/ { 40, 185, 0x97, 1756}, + /*(7417) VFMSUBADD132PH*/ { 54, 1, 0x97, 3796}, + /*(7418) VFMSUBADD132PH*/ { 54, 101, 0x97, 3802}, + /*(7419) VFMSUBADD132PH*/ { 40, 185, 0x97, 1756}, + /*(7420) VFMSUBADD213PH*/ { 54, 1, 0xa7, 3796}, + /*(7421) VFMSUBADD213PH*/ { 40, 185, 0xa7, 1756}, + /*(7422) VFMSUBADD213PH*/ { 54, 1, 0xa7, 3796}, + /*(7423) VFMSUBADD213PH*/ { 40, 185, 0xa7, 1756}, + /*(7424) VFMSUBADD213PH*/ { 54, 1, 0xa7, 3796}, + /*(7425) VFMSUBADD213PH*/ { 54, 101, 0xa7, 3802}, + /*(7426) VFMSUBADD213PH*/ { 40, 185, 0xa7, 1756}, + /*(7427) VFMSUBADD231PH*/ { 54, 1, 0xb7, 3796}, + /*(7428) VFMSUBADD231PH*/ { 40, 185, 0xb7, 1756}, + /*(7429) VFMSUBADD231PH*/ { 54, 1, 0xb7, 3796}, + /*(7430) VFMSUBADD231PH*/ { 40, 185, 0xb7, 1756}, + /*(7431) VFMSUBADD231PH*/ { 54, 1, 0xb7, 3796}, + /*(7432) VFMSUBADD231PH*/ { 54, 101, 0xb7, 3802}, + /*(7433) VFMSUBADD231PH*/ { 40, 185, 0xb7, 1756}, + /*(7434) VFMULCPH*/ { 54, 1, 0xd6, 3813}, + /*(7435) VFMULCPH*/ { 40, 103, 0xd6, 38}, + /*(7436) VFMULCPH*/ { 54, 1, 0xd6, 3813}, + /*(7437) VFMULCPH*/ { 40, 103, 0xd6, 38}, + /*(7438) VFMULCPH*/ { 54, 1, 0xd6, 3813}, + /*(7439) VFMULCPH*/ { 54, 101, 0xd6, 3819}, + /*(7440) VFMULCPH*/ { 40, 103, 0xd6, 38}, + /*(7441) VFMULCSH*/ { 54, 113, 0xd7, 3813}, + /*(7442) VFMULCSH*/ { 54, 104, 0xd7, 3819}, + /*(7443) VFMULCSH*/ { 55, 196, 0xd7, 37}, + /*(7444) VFNMADD132PH*/ { 54, 1, 0x9c, 3796}, + /*(7445) VFNMADD132PH*/ { 40, 185, 0x9c, 1756}, + /*(7446) VFNMADD132PH*/ { 54, 1, 0x9c, 3796}, + /*(7447) VFNMADD132PH*/ { 40, 185, 0x9c, 1756}, + /*(7448) VFNMADD132PH*/ { 54, 1, 0x9c, 3796}, + /*(7449) VFNMADD132PH*/ { 54, 101, 0x9c, 3802}, + /*(7450) VFNMADD132PH*/ { 40, 185, 0x9c, 1756}, + /*(7451) VFNMADD132SH*/ { 54, 113, 0x9d, 3796}, + /*(7452) VFNMADD132SH*/ { 54, 104, 0x9d, 3802}, + /*(7453) VFNMADD132SH*/ { 55, 186, 0x9d, 3808}, + /*(7454) VFNMADD213PH*/ { 54, 1, 0xac, 3796}, + /*(7455) VFNMADD213PH*/ { 40, 185, 0xac, 1756}, + /*(7456) VFNMADD213PH*/ { 54, 1, 0xac, 3796}, + /*(7457) VFNMADD213PH*/ { 40, 185, 0xac, 1756}, + /*(7458) VFNMADD213PH*/ { 54, 1, 0xac, 3796}, + /*(7459) VFNMADD213PH*/ { 54, 101, 0xac, 3802}, + /*(7460) VFNMADD213PH*/ { 40, 185, 0xac, 1756}, + /*(7461) VFNMADD213SH*/ { 54, 113, 0xad, 3796}, + /*(7462) VFNMADD213SH*/ { 54, 104, 0xad, 3802}, + /*(7463) VFNMADD213SH*/ { 55, 186, 0xad, 3808}, + /*(7464) VFNMADD231PH*/ { 54, 1, 0xbc, 3796}, + /*(7465) VFNMADD231PH*/ { 40, 185, 0xbc, 1756}, + /*(7466) VFNMADD231PH*/ { 54, 1, 0xbc, 3796}, + /*(7467) VFNMADD231PH*/ { 40, 185, 0xbc, 1756}, + /*(7468) VFNMADD231PH*/ { 54, 1, 0xbc, 3796}, + /*(7469) VFNMADD231PH*/ { 54, 101, 0xbc, 3802}, + /*(7470) VFNMADD231PH*/ { 40, 185, 0xbc, 1756}, + /*(7471) VFNMADD231SH*/ { 54, 113, 0xbd, 3796}, + /*(7472) VFNMADD231SH*/ { 54, 104, 0xbd, 3802}, + /*(7473) VFNMADD231SH*/ { 55, 186, 0xbd, 3808}, + /*(7474) VFNMSUB132PH*/ { 54, 1, 0x9e, 3796}, + /*(7475) VFNMSUB132PH*/ { 40, 185, 0x9e, 1756}, + /*(7476) VFNMSUB132PH*/ { 54, 1, 0x9e, 3796}, + /*(7477) VFNMSUB132PH*/ { 40, 185, 0x9e, 1756}, + /*(7478) VFNMSUB132PH*/ { 54, 1, 0x9e, 3796}, + /*(7479) VFNMSUB132PH*/ { 54, 101, 0x9e, 3802}, + /*(7480) VFNMSUB132PH*/ { 40, 185, 0x9e, 1756}, + /*(7481) VFNMSUB132SH*/ { 54, 113, 0x9f, 3796}, + /*(7482) VFNMSUB132SH*/ { 54, 104, 0x9f, 3802}, + /*(7483) VFNMSUB132SH*/ { 55, 186, 0x9f, 3808}, + /*(7484) VFNMSUB213PH*/ { 54, 1, 0xae, 3796}, + /*(7485) VFNMSUB213PH*/ { 40, 185, 0xae, 1756}, + /*(7486) VFNMSUB213PH*/ { 54, 1, 0xae, 3796}, + /*(7487) VFNMSUB213PH*/ { 40, 185, 0xae, 1756}, + /*(7488) VFNMSUB213PH*/ { 54, 1, 0xae, 3796}, + /*(7489) VFNMSUB213PH*/ { 54, 101, 0xae, 3802}, + /*(7490) VFNMSUB213PH*/ { 40, 185, 0xae, 1756}, + /*(7491) VFNMSUB213SH*/ { 54, 113, 0xaf, 3796}, + /*(7492) VFNMSUB213SH*/ { 54, 104, 0xaf, 3802}, + /*(7493) VFNMSUB213SH*/ { 55, 186, 0xaf, 3808}, + /*(7494) VFNMSUB231PH*/ { 54, 1, 0xbe, 3796}, + /*(7495) VFNMSUB231PH*/ { 40, 185, 0xbe, 1756}, + /*(7496) VFNMSUB231PH*/ { 54, 1, 0xbe, 3796}, + /*(7497) VFNMSUB231PH*/ { 40, 185, 0xbe, 1756}, + /*(7498) VFNMSUB231PH*/ { 54, 1, 0xbe, 3796}, + /*(7499) VFNMSUB231PH*/ { 54, 101, 0xbe, 3802}, + /*(7500) VFNMSUB231PH*/ { 40, 185, 0xbe, 1756}, + /*(7501) VFNMSUB231SH*/ { 54, 113, 0xbf, 3796}, + /*(7502) VFNMSUB231SH*/ { 54, 104, 0xbf, 3802}, + /*(7503) VFNMSUB231SH*/ { 55, 186, 0xbf, 3808}, + /*(7504) VFPCLASSPH*/ { 111, 10, 0x66, 3825}, + /*(7505) VFPCLASSPH*/ { 112, 187, 0x66, 759}, + /*(7506) VFPCLASSPH*/ { 111, 10, 0x66, 3825}, + /*(7507) VFPCLASSPH*/ { 112, 187, 0x66, 759}, + /*(7508) VFPCLASSPH*/ { 111, 10, 0x66, 3825}, + /*(7509) VFPCLASSPH*/ { 112, 187, 0x66, 759}, + /*(7510) VFPCLASSSH*/ { 111, 188, 0x67, 3825}, + /*(7511) VFPCLASSSH*/ { 81, 189, 0x67, 758}, + /*(7512) VGETEXPPH*/ { 61, 1, 0x42, 3443}, + /*(7513) VGETEXPPH*/ { 62, 185, 0x42, 3452}, + /*(7514) VGETEXPPH*/ { 61, 1, 0x42, 3443}, + /*(7515) VGETEXPPH*/ { 62, 185, 0x42, 3452}, + /*(7516) VGETEXPPH*/ { 61, 1, 0x42, 3443}, + /*(7517) VGETEXPPH*/ { 61, 119, 0x42, 3459}, + /*(7518) VGETEXPPH*/ { 62, 185, 0x42, 3452}, + /*(7519) VGETEXPSH*/ { 54, 113, 0x43, 3796}, + /*(7520) VGETEXPSH*/ { 54, 114, 0x43, 3802}, + /*(7521) VGETEXPSH*/ { 55, 186, 0x43, 3808}, + /*(7522) VGETMANTPH*/ { 61, 10, 0x26, 3825}, + /*(7523) VGETMANTPH*/ { 62, 187, 0x26, 759}, + /*(7524) VGETMANTPH*/ { 61, 10, 0x26, 3825}, + /*(7525) VGETMANTPH*/ { 62, 187, 0x26, 759}, + /*(7526) VGETMANTPH*/ { 61, 10, 0x26, 3825}, + /*(7527) VGETMANTPH*/ { 61, 107, 0x26, 3835}, + /*(7528) VGETMANTPH*/ { 62, 187, 0x26, 759}, + /*(7529) VGETMANTSH*/ { 54, 188, 0x27, 3308}, + /*(7530) VGETMANTSH*/ { 54, 110, 0x27, 3315}, + /*(7531) VGETMANTSH*/ { 55, 189, 0x27, 973}, + /*(7532) VMAXPH*/ { 54, 1, 0x5f, 3280}, + /*(7533) VMAXPH*/ { 40, 185, 0x5f, 3286}, + /*(7534) VMAXPH*/ { 54, 1, 0x5f, 3280}, + /*(7535) VMAXPH*/ { 40, 185, 0x5f, 3286}, + /*(7536) VMAXPH*/ { 54, 1, 0x5f, 3280}, + /*(7537) VMAXPH*/ { 54, 119, 0x5f, 3290}, + /*(7538) VMAXPH*/ { 40, 185, 0x5f, 3286}, + /*(7539) VMAXSH*/ { 54, 113, 0x5f, 3296}, + /*(7540) VMAXSH*/ { 54, 114, 0x5f, 3302}, + /*(7541) VMAXSH*/ { 55, 186, 0x5f, 267}, + /*(7542) VMINPH*/ { 54, 1, 0x5d, 3280}, + /*(7543) VMINPH*/ { 40, 185, 0x5d, 3286}, + /*(7544) VMINPH*/ { 54, 1, 0x5d, 3280}, + /*(7545) VMINPH*/ { 40, 185, 0x5d, 3286}, + /*(7546) VMINPH*/ { 54, 1, 0x5d, 3280}, + /*(7547) VMINPH*/ { 54, 119, 0x5d, 3290}, + /*(7548) VMINPH*/ { 40, 185, 0x5d, 3286}, + /*(7549) VMINSH*/ { 54, 113, 0x5d, 3296}, + /*(7550) VMINSH*/ { 54, 114, 0x5d, 3302}, + /*(7551) VMINSH*/ { 55, 186, 0x5d, 267}, + /*(7552) VMOVSH*/ { 80, 186, 0x10, 3844}, + /*(7553) VMOVSH*/ { 81, 186, 0x11, 3852}, + /*(7554) VMOVSH*/ { 54, 113, 0x10, 3296}, + /*(7555) VMOVSH*/ { 54, 113, 0x11, 3296}, + /*(7556) VMOVW*/ { 63, 1, 0x6e, 3861}, + /*(7557) VMOVW*/ { 65, 197, 0x6e, 3871}, + /*(7558) VMOVW*/ { 63, 1, 0x7e, 3861}, + /*(7559) VMOVW*/ { 65, 198, 0x7e, 3871}, + /*(7560) VMULPH*/ { 54, 1, 0x59, 3280}, + /*(7561) VMULPH*/ { 40, 185, 0x59, 3286}, + /*(7562) VMULPH*/ { 54, 1, 0x59, 3280}, + /*(7563) VMULPH*/ { 40, 185, 0x59, 3286}, + /*(7564) VMULPH*/ { 54, 1, 0x59, 3280}, + /*(7565) VMULPH*/ { 54, 101, 0x59, 3290}, + /*(7566) VMULPH*/ { 40, 185, 0x59, 3286}, + /*(7567) VMULSH*/ { 54, 113, 0x59, 3296}, + /*(7568) VMULSH*/ { 54, 104, 0x59, 3302}, + /*(7569) VMULSH*/ { 55, 186, 0x59, 267}, + /*(7570) VRCPPH*/ { 61, 1, 0x4c, 3443}, + /*(7571) VRCPPH*/ { 62, 185, 0x4c, 3452}, + /*(7572) VRCPPH*/ { 61, 1, 0x4c, 3443}, + /*(7573) VRCPPH*/ { 62, 185, 0x4c, 3452}, + /*(7574) VRCPPH*/ { 61, 1, 0x4c, 3443}, + /*(7575) VRCPPH*/ { 62, 185, 0x4c, 3452}, + /*(7576) VRCPSH*/ { 54, 113, 0x4d, 3796}, + /*(7577) VRCPSH*/ { 55, 186, 0x4d, 3808}, + /*(7578) VREDUCEPH*/ { 61, 10, 0x56, 3825}, + /*(7579) VREDUCEPH*/ { 62, 187, 0x56, 759}, + /*(7580) VREDUCEPH*/ { 61, 10, 0x56, 3825}, + /*(7581) VREDUCEPH*/ { 62, 187, 0x56, 759}, + /*(7582) VREDUCEPH*/ { 61, 10, 0x56, 3825}, + /*(7583) VREDUCEPH*/ { 61, 107, 0x56, 3835}, + /*(7584) VREDUCEPH*/ { 62, 187, 0x56, 759}, + /*(7585) VREDUCESH*/ { 54, 188, 0x57, 3308}, + /*(7586) VREDUCESH*/ { 54, 110, 0x57, 3315}, + /*(7587) VREDUCESH*/ { 55, 189, 0x57, 973}, + /*(7588) VRNDSCALEPH*/ { 61, 10, 0x8, 3825}, + /*(7589) VRNDSCALEPH*/ { 62, 187, 0x8, 759}, + /*(7590) VRNDSCALEPH*/ { 61, 10, 0x8, 3825}, + /*(7591) VRNDSCALEPH*/ { 62, 187, 0x8, 759}, + /*(7592) VRNDSCALEPH*/ { 61, 10, 0x8, 3825}, + /*(7593) VRNDSCALEPH*/ { 61, 107, 0x8, 3835}, + /*(7594) VRNDSCALEPH*/ { 62, 187, 0x8, 759}, + /*(7595) VRNDSCALESH*/ { 54, 188, 0xa, 3308}, + /*(7596) VRNDSCALESH*/ { 54, 110, 0xa, 3315}, + /*(7597) VRNDSCALESH*/ { 55, 189, 0xa, 973}, + /*(7598) VRSQRTPH*/ { 61, 1, 0x4e, 3443}, + /*(7599) VRSQRTPH*/ { 62, 185, 0x4e, 3452}, + /*(7600) VRSQRTPH*/ { 61, 1, 0x4e, 3443}, + /*(7601) VRSQRTPH*/ { 62, 185, 0x4e, 3452}, + /*(7602) VRSQRTPH*/ { 61, 1, 0x4e, 3443}, + /*(7603) VRSQRTPH*/ { 62, 185, 0x4e, 3452}, + /*(7604) VRSQRTSH*/ { 54, 113, 0x4f, 3796}, + /*(7605) VRSQRTSH*/ { 55, 186, 0x4f, 3808}, + /*(7606) VSCALEFPH*/ { 54, 1, 0x2c, 3796}, + /*(7607) VSCALEFPH*/ { 40, 185, 0x2c, 1756}, + /*(7608) VSCALEFPH*/ { 54, 1, 0x2c, 3796}, + /*(7609) VSCALEFPH*/ { 40, 185, 0x2c, 1756}, + /*(7610) VSCALEFPH*/ { 54, 1, 0x2c, 3796}, + /*(7611) VSCALEFPH*/ { 54, 101, 0x2c, 3802}, + /*(7612) VSCALEFPH*/ { 40, 185, 0x2c, 1756}, + /*(7613) VSCALEFSH*/ { 54, 113, 0x2d, 3796}, + /*(7614) VSCALEFSH*/ { 54, 104, 0x2d, 3802}, + /*(7615) VSCALEFSH*/ { 55, 186, 0x2d, 3808}, + /*(7616) VSQRTPH*/ { 61, 1, 0x51, 3368}, + /*(7617) VSQRTPH*/ { 62, 185, 0x51, 3377}, + /*(7618) VSQRTPH*/ { 61, 1, 0x51, 3368}, + /*(7619) VSQRTPH*/ { 62, 185, 0x51, 3377}, + /*(7620) VSQRTPH*/ { 61, 1, 0x51, 3368}, + /*(7621) VSQRTPH*/ { 61, 101, 0x51, 3384}, + /*(7622) VSQRTPH*/ { 62, 185, 0x51, 3377}, + /*(7623) VSQRTSH*/ { 54, 113, 0x51, 3296}, + /*(7624) VSQRTSH*/ { 54, 104, 0x51, 3302}, + /*(7625) VSQRTSH*/ { 55, 186, 0x51, 267}, + /*(7626) VSUBPH*/ { 54, 1, 0x5c, 3280}, + /*(7627) VSUBPH*/ { 40, 185, 0x5c, 3286}, + /*(7628) VSUBPH*/ { 54, 1, 0x5c, 3280}, + /*(7629) VSUBPH*/ { 40, 185, 0x5c, 3286}, + /*(7630) VSUBPH*/ { 54, 1, 0x5c, 3280}, + /*(7631) VSUBPH*/ { 54, 101, 0x5c, 3290}, + /*(7632) VSUBPH*/ { 40, 185, 0x5c, 3286}, + /*(7633) VSUBSH*/ { 54, 113, 0x5c, 3296}, + /*(7634) VSUBSH*/ { 54, 104, 0x5c, 3302}, + /*(7635) VSUBSH*/ { 55, 186, 0x5c, 267}, + /*(7636) VUCOMISH*/ { 59, 113, 0x2e, 3336}, + /*(7637) VUCOMISH*/ { 59, 114, 0x2e, 3347}, + /*(7638) VUCOMISH*/ { 60, 186, 0x2e, 3358}, +}; diff --git a/CodeVirtualizer/build/obj/xed-encoder-iforms.h b/CodeVirtualizer/build/obj/xed-encoder-iforms.h new file mode 100644 index 0000000..18afee6 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-iforms.h @@ -0,0 +1,77 @@ +/// @file xed-encoder-iforms.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ENCODER_IFORMS_H) +# define XED_ENCODER_IFORMS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-types.h" +typedef struct xed_encoder_iforms_s { + xed_uint32_t x_SIBBASE_ENCODE; + xed_uint32_t x_SIBBASE_ENCODE_SIB1; + xed_uint32_t x_SIBINDEX_ENCODE; + xed_uint32_t x_MODRM_MOD_ENCODE; + xed_uint32_t x_MODRM_RM_ENCODE; + xed_uint32_t x_MODRM_RM_ENCODE_EA16_SIB0; + xed_uint32_t x_MODRM_RM_ENCODE_EA64_SIB0; + xed_uint32_t x_MODRM_RM_ENCODE_EA32_SIB0; + xed_uint32_t x_SIB_NT; + xed_uint32_t x_DISP_NT; + xed_uint32_t x_REMOVE_SEGMENT; + xed_uint32_t x_REX_PREFIX_ENC; + xed_uint32_t x_PREFIX_ENC; + xed_uint32_t x_VEXED_REX; + xed_uint32_t x_XOP_TYPE_ENC; + xed_uint32_t x_XOP_MAP_ENC; + xed_uint32_t x_XOP_REXXB_ENC; + xed_uint32_t x_VEX_TYPE_ENC; + xed_uint32_t x_VEX_REXR_ENC; + xed_uint32_t x_VEX_REXXB_ENC; + xed_uint32_t x_VEX_MAP_ENC; + xed_uint32_t x_VEX_REG_ENC; + xed_uint32_t x_VEX_ESCVL_ENC; + xed_uint32_t x_SE_IMM8; + xed_uint32_t x_VSIB_ENC_BASE; + xed_uint32_t x_VSIB_ENC; + xed_uint32_t x_EVEX_62_REXR_ENC; + xed_uint32_t x_EVEX_REXX_ENC; + xed_uint32_t x_EVEX_REXB_ENC; + xed_uint32_t x_EVEX_REXRR_ENC; + xed_uint32_t x_EVEX_MAP_ENC; + xed_uint32_t x_EVEX_REXW_VVVV_ENC; + xed_uint32_t x_EVEX_UPP_ENC; + xed_uint32_t x_AVX512_EVEX_BYTE3_ENC; + xed_uint32_t x_UIMMv; + xed_uint32_t x_SIMMz; + xed_uint32_t x_SIMM8; + xed_uint32_t x_UIMM8; + xed_uint32_t x_UIMM8_1; + xed_uint32_t x_UIMM16; + xed_uint32_t x_UIMM32; + xed_uint32_t x_BRDISP8; + xed_uint32_t x_BRDISP32; + xed_uint32_t x_BRDISPz; + xed_uint32_t x_MEMDISPv; + xed_uint32_t x_MEMDISP32; + xed_uint32_t x_MEMDISP16; + xed_uint32_t x_MEMDISP8; + xed_uint32_t x_MEMDISP; +} xed_encoder_iforms_t; +#endif diff --git a/CodeVirtualizer/build/obj/xed-encoder-init.c b/CodeVirtualizer/build/obj/xed-encoder-init.c new file mode 100644 index 0000000..0c4b346 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-init.c @@ -0,0 +1,3513 @@ +/// @file xed-encoder-init.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-encoder.h" +void xed_init_encode_table(void) +{ + xed_enc_iclass2group[XED_ICLASS_FADD] = 0; + xed_enc_iclass2group[XED_ICLASS_FMUL] = 0; + xed_enc_iclass2group[XED_ICLASS_FSUB] = 0; + xed_enc_iclass2group[XED_ICLASS_FSUBR] = 0; + xed_enc_iclass2group[XED_ICLASS_FDIV] = 0; + xed_enc_iclass2group[XED_ICLASS_FDIVR] = 0; + xed_enc_iclass2group[XED_ICLASS_FCOMP] = 1; + xed_enc_iclass2group[XED_ICLASS_FCOM] = 2; + xed_enc_iclass2group[XED_ICLASS_FLD] = 3; + xed_enc_iclass2group[XED_ICLASS_FST] = 4; + xed_enc_iclass2group[XED_ICLASS_FSTP] = 5; + xed_enc_iclass2group[XED_ICLASS_FSTPNCE] = 6; + xed_enc_iclass2group[XED_ICLASS_FADDP] = 6; + xed_enc_iclass2group[XED_ICLASS_FMULP] = 6; + xed_enc_iclass2group[XED_ICLASS_FSUBRP] = 6; + xed_enc_iclass2group[XED_ICLASS_FSUBP] = 6; + xed_enc_iclass2group[XED_ICLASS_FDIVRP] = 6; + xed_enc_iclass2group[XED_ICLASS_FDIVP] = 6; + xed_enc_iclass2group[XED_ICLASS_FLDENV] = 7; + xed_enc_iclass2group[XED_ICLASS_FNSTENV] = 7; + xed_enc_iclass2group[XED_ICLASS_FLDCW] = 8; + xed_enc_iclass2group[XED_ICLASS_FNSTCW] = 8; + xed_enc_iclass2group[XED_ICLASS_FXCH] = 9; + xed_enc_iclass2group[XED_ICLASS_FNOP] = 10; + xed_enc_iclass2group[XED_ICLASS_FCHS] = 10; + xed_enc_iclass2group[XED_ICLASS_FABS] = 10; + xed_enc_iclass2group[XED_ICLASS_FTST] = 10; + xed_enc_iclass2group[XED_ICLASS_FXAM] = 10; + xed_enc_iclass2group[XED_ICLASS_FLD1] = 10; + xed_enc_iclass2group[XED_ICLASS_FLDL2T] = 10; + xed_enc_iclass2group[XED_ICLASS_FLDL2E] = 10; + xed_enc_iclass2group[XED_ICLASS_FLDPI] = 10; + xed_enc_iclass2group[XED_ICLASS_FLDLG2] = 10; + xed_enc_iclass2group[XED_ICLASS_FLDLN2] = 10; + xed_enc_iclass2group[XED_ICLASS_FLDZ] = 10; + xed_enc_iclass2group[XED_ICLASS_F2XM1] = 10; + xed_enc_iclass2group[XED_ICLASS_FYL2X] = 10; + xed_enc_iclass2group[XED_ICLASS_FPTAN] = 10; + xed_enc_iclass2group[XED_ICLASS_FPATAN] = 10; + xed_enc_iclass2group[XED_ICLASS_FXTRACT] = 10; + xed_enc_iclass2group[XED_ICLASS_FPREM1] = 10; + xed_enc_iclass2group[XED_ICLASS_FDECSTP] = 10; + xed_enc_iclass2group[XED_ICLASS_FINCSTP] = 10; + xed_enc_iclass2group[XED_ICLASS_FPREM] = 10; + xed_enc_iclass2group[XED_ICLASS_FYL2XP1] = 10; + xed_enc_iclass2group[XED_ICLASS_FSQRT] = 10; + xed_enc_iclass2group[XED_ICLASS_FSINCOS] = 10; + xed_enc_iclass2group[XED_ICLASS_FRNDINT] = 10; + xed_enc_iclass2group[XED_ICLASS_FSCALE] = 10; + xed_enc_iclass2group[XED_ICLASS_FSIN] = 10; + xed_enc_iclass2group[XED_ICLASS_FCOS] = 10; + xed_enc_iclass2group[XED_ICLASS_FUCOMPP] = 10; + xed_enc_iclass2group[XED_ICLASS_FNCLEX] = 10; + xed_enc_iclass2group[XED_ICLASS_FNINIT] = 10; + xed_enc_iclass2group[XED_ICLASS_FSETPM287_NOP] = 10; + xed_enc_iclass2group[XED_ICLASS_FENI8087_NOP] = 10; + xed_enc_iclass2group[XED_ICLASS_FDISI8087_NOP] = 10; + xed_enc_iclass2group[XED_ICLASS_FCOMPP] = 10; + xed_enc_iclass2group[XED_ICLASS_VMCALL] = 10; + xed_enc_iclass2group[XED_ICLASS_VMLAUNCH] = 10; + xed_enc_iclass2group[XED_ICLASS_VMRESUME] = 10; + xed_enc_iclass2group[XED_ICLASS_VMXOFF] = 10; + xed_enc_iclass2group[XED_ICLASS_MWAIT] = 10; + xed_enc_iclass2group[XED_ICLASS_RDTSCP] = 10; + xed_enc_iclass2group[XED_ICLASS_SFENCE] = 10; + xed_enc_iclass2group[XED_ICLASS_LFENCE] = 10; + xed_enc_iclass2group[XED_ICLASS_MFENCE] = 10; + xed_enc_iclass2group[XED_ICLASS_INSB] = 10; + xed_enc_iclass2group[XED_ICLASS_PAUSE] = 10; + xed_enc_iclass2group[XED_ICLASS_FWAIT] = 10; + xed_enc_iclass2group[XED_ICLASS_SAHF] = 10; + xed_enc_iclass2group[XED_ICLASS_LAHF] = 10; + xed_enc_iclass2group[XED_ICLASS_STOSB] = 10; + xed_enc_iclass2group[XED_ICLASS_REPE_SCASB] = 10; + xed_enc_iclass2group[XED_ICLASS_REPNE_SCASB] = 10; + xed_enc_iclass2group[XED_ICLASS_SCASB] = 10; + xed_enc_iclass2group[XED_ICLASS_INT3] = 10; + xed_enc_iclass2group[XED_ICLASS_INT1] = 10; + xed_enc_iclass2group[XED_ICLASS_HLT] = 10; + xed_enc_iclass2group[XED_ICLASS_CMC] = 10; + xed_enc_iclass2group[XED_ICLASS_CLC] = 10; + xed_enc_iclass2group[XED_ICLASS_STC] = 10; + xed_enc_iclass2group[XED_ICLASS_CLI] = 10; + xed_enc_iclass2group[XED_ICLASS_STI] = 10; + xed_enc_iclass2group[XED_ICLASS_CLD] = 10; + xed_enc_iclass2group[XED_ICLASS_STD] = 10; + xed_enc_iclass2group[XED_ICLASS_CLTS] = 10; + xed_enc_iclass2group[XED_ICLASS_WRMSR] = 10; + xed_enc_iclass2group[XED_ICLASS_RDTSC] = 10; + xed_enc_iclass2group[XED_ICLASS_RDMSR] = 10; + xed_enc_iclass2group[XED_ICLASS_RDPMC] = 10; + xed_enc_iclass2group[XED_ICLASS_EMMS] = 10; + xed_enc_iclass2group[XED_ICLASS_CPUID] = 10; + xed_enc_iclass2group[XED_ICLASS_INVD] = 10; + xed_enc_iclass2group[XED_ICLASS_UD2] = 10; + xed_enc_iclass2group[XED_ICLASS_RSM] = 10; + xed_enc_iclass2group[XED_ICLASS_XGETBV] = 10; + xed_enc_iclass2group[XED_ICLASS_XSETBV] = 10; + xed_enc_iclass2group[XED_ICLASS_GETSEC] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP2] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP3] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP4] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP5] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP6] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP7] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP8] = 10; + xed_enc_iclass2group[XED_ICLASS_NOP9] = 10; + xed_enc_iclass2group[XED_ICLASS_XSTORE] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XSTORE] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XCRYPTECB] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XCRYPTCBC] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XCRYPTCTR] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XCRYPTCFB] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XCRYPTOFB] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XSHA1] = 10; + xed_enc_iclass2group[XED_ICLASS_REP_XSHA256] = 10; + xed_enc_iclass2group[XED_ICLASS_FEMMS] = 10; + xed_enc_iclass2group[XED_ICLASS_VMMCALL] = 10; + xed_enc_iclass2group[XED_ICLASS_VMSAVE] = 10; + xed_enc_iclass2group[XED_ICLASS_STGI] = 10; + xed_enc_iclass2group[XED_ICLASS_CLGI] = 10; + xed_enc_iclass2group[XED_ICLASS_CLZERO] = 10; + xed_enc_iclass2group[XED_ICLASS_MWAITX] = 10; + xed_enc_iclass2group[XED_ICLASS_MCOMMIT] = 10; + xed_enc_iclass2group[XED_ICLASS_RDPRU] = 10; + xed_enc_iclass2group[XED_ICLASS_TLBSYNC] = 10; + xed_enc_iclass2group[XED_ICLASS_ENDBR32] = 10; + xed_enc_iclass2group[XED_ICLASS_ENDBR64] = 10; + xed_enc_iclass2group[XED_ICLASS_SAVEPREVSSP] = 10; + xed_enc_iclass2group[XED_ICLASS_SETSSBSY] = 10; + xed_enc_iclass2group[XED_ICLASS_CLAC] = 10; + xed_enc_iclass2group[XED_ICLASS_STAC] = 10; + xed_enc_iclass2group[XED_ICLASS_ENCLU] = 10; + xed_enc_iclass2group[XED_ICLASS_ENCLS] = 10; + xed_enc_iclass2group[XED_ICLASS_ENCLV] = 10; + xed_enc_iclass2group[XED_ICLASS_VMFUNC] = 10; + xed_enc_iclass2group[XED_ICLASS_XEND] = 10; + xed_enc_iclass2group[XED_ICLASS_XTEST] = 10; + xed_enc_iclass2group[XED_ICLASS_RDPKRU] = 10; + xed_enc_iclass2group[XED_ICLASS_WRPKRU] = 10; + xed_enc_iclass2group[XED_ICLASS_WBNOINVD] = 10; + xed_enc_iclass2group[XED_ICLASS_XRESLDTRK] = 10; + xed_enc_iclass2group[XED_ICLASS_XSUSLDTRK] = 10; + xed_enc_iclass2group[XED_ICLASS_SERIALIZE] = 10; + xed_enc_iclass2group[XED_ICLASS_FIADD] = 11; + xed_enc_iclass2group[XED_ICLASS_FIMUL] = 11; + xed_enc_iclass2group[XED_ICLASS_FICOM] = 11; + xed_enc_iclass2group[XED_ICLASS_FICOMP] = 11; + xed_enc_iclass2group[XED_ICLASS_FISUB] = 11; + xed_enc_iclass2group[XED_ICLASS_FISUBR] = 11; + xed_enc_iclass2group[XED_ICLASS_FIDIV] = 11; + xed_enc_iclass2group[XED_ICLASS_FIDIVR] = 11; + xed_enc_iclass2group[XED_ICLASS_FCMOVB] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVE] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVBE] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVU] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVNB] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVNE] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVNBE] = 12; + xed_enc_iclass2group[XED_ICLASS_FCMOVNU] = 12; + xed_enc_iclass2group[XED_ICLASS_FUCOMI] = 12; + xed_enc_iclass2group[XED_ICLASS_FCOMI] = 12; + xed_enc_iclass2group[XED_ICLASS_FUCOM] = 12; + xed_enc_iclass2group[XED_ICLASS_FUCOMP] = 12; + xed_enc_iclass2group[XED_ICLASS_FUCOMIP] = 12; + xed_enc_iclass2group[XED_ICLASS_FCOMIP] = 12; + xed_enc_iclass2group[XED_ICLASS_FILD] = 13; + xed_enc_iclass2group[XED_ICLASS_FISTTP] = 14; + xed_enc_iclass2group[XED_ICLASS_FISTP] = 14; + xed_enc_iclass2group[XED_ICLASS_FIST] = 15; + xed_enc_iclass2group[XED_ICLASS_FRSTOR] = 16; + xed_enc_iclass2group[XED_ICLASS_FNSAVE] = 16; + xed_enc_iclass2group[XED_ICLASS_FNSTSW] = 17; + xed_enc_iclass2group[XED_ICLASS_FFREE] = 18; + xed_enc_iclass2group[XED_ICLASS_FFREEP] = 18; + xed_enc_iclass2group[XED_ICLASS_FBLD] = 19; + xed_enc_iclass2group[XED_ICLASS_FBSTP] = 20; + xed_enc_iclass2group[XED_ICLASS_ADD_LOCK] = 21; + xed_enc_iclass2group[XED_ICLASS_OR_LOCK] = 21; + xed_enc_iclass2group[XED_ICLASS_ADC_LOCK] = 21; + xed_enc_iclass2group[XED_ICLASS_SBB_LOCK] = 21; + xed_enc_iclass2group[XED_ICLASS_SUB_LOCK] = 21; + xed_enc_iclass2group[XED_ICLASS_ADD] = 22; + xed_enc_iclass2group[XED_ICLASS_ADC] = 22; + xed_enc_iclass2group[XED_ICLASS_SBB] = 22; + xed_enc_iclass2group[XED_ICLASS_SUB] = 22; + xed_enc_iclass2group[XED_ICLASS_CMP] = 22; + xed_enc_iclass2group[XED_ICLASS_OR] = 23; + xed_enc_iclass2group[XED_ICLASS_AND_LOCK] = 24; + xed_enc_iclass2group[XED_ICLASS_XOR_LOCK] = 24; + xed_enc_iclass2group[XED_ICLASS_AND] = 25; + xed_enc_iclass2group[XED_ICLASS_XOR] = 26; + xed_enc_iclass2group[XED_ICLASS_POP] = 27; + xed_enc_iclass2group[XED_ICLASS_ROL] = 28; + xed_enc_iclass2group[XED_ICLASS_ROR] = 28; + xed_enc_iclass2group[XED_ICLASS_RCL] = 28; + xed_enc_iclass2group[XED_ICLASS_RCR] = 28; + xed_enc_iclass2group[XED_ICLASS_SHR] = 28; + xed_enc_iclass2group[XED_ICLASS_SAR] = 28; + xed_enc_iclass2group[XED_ICLASS_SHL] = 29; + xed_enc_iclass2group[XED_ICLASS_TEST] = 30; + xed_enc_iclass2group[XED_ICLASS_NOT_LOCK] = 31; + xed_enc_iclass2group[XED_ICLASS_NEG_LOCK] = 31; + xed_enc_iclass2group[XED_ICLASS_INC_LOCK] = 31; + xed_enc_iclass2group[XED_ICLASS_DEC_LOCK] = 31; + xed_enc_iclass2group[XED_ICLASS_NOT] = 32; + xed_enc_iclass2group[XED_ICLASS_NEG] = 32; + xed_enc_iclass2group[XED_ICLASS_MUL] = 32; + xed_enc_iclass2group[XED_ICLASS_DIV] = 32; + xed_enc_iclass2group[XED_ICLASS_IDIV] = 32; + xed_enc_iclass2group[XED_ICLASS_IMUL] = 33; + xed_enc_iclass2group[XED_ICLASS_INC] = 34; + xed_enc_iclass2group[XED_ICLASS_DEC] = 34; + xed_enc_iclass2group[XED_ICLASS_CALL_NEAR] = 35; + xed_enc_iclass2group[XED_ICLASS_JMP] = 36; + xed_enc_iclass2group[XED_ICLASS_JMP_FAR] = 37; + xed_enc_iclass2group[XED_ICLASS_CALL_FAR] = 37; + xed_enc_iclass2group[XED_ICLASS_PUSH] = 38; + xed_enc_iclass2group[XED_ICLASS_SLDT] = 39; + xed_enc_iclass2group[XED_ICLASS_STR] = 39; + xed_enc_iclass2group[XED_ICLASS_SMSW] = 39; + xed_enc_iclass2group[XED_ICLASS_LLDT] = 40; + xed_enc_iclass2group[XED_ICLASS_LTR] = 40; + xed_enc_iclass2group[XED_ICLASS_VERR] = 40; + xed_enc_iclass2group[XED_ICLASS_VERW] = 40; + xed_enc_iclass2group[XED_ICLASS_LMSW] = 40; + xed_enc_iclass2group[XED_ICLASS_LGDT] = 41; + xed_enc_iclass2group[XED_ICLASS_SGDT] = 41; + xed_enc_iclass2group[XED_ICLASS_LIDT] = 41; + xed_enc_iclass2group[XED_ICLASS_SIDT] = 41; + xed_enc_iclass2group[XED_ICLASS_BT] = 42; + xed_enc_iclass2group[XED_ICLASS_BTS] = 42; + xed_enc_iclass2group[XED_ICLASS_BTR] = 42; + xed_enc_iclass2group[XED_ICLASS_BTC] = 42; + xed_enc_iclass2group[XED_ICLASS_BTS_LOCK] = 43; + xed_enc_iclass2group[XED_ICLASS_BTR_LOCK] = 43; + xed_enc_iclass2group[XED_ICLASS_BTC_LOCK] = 43; + xed_enc_iclass2group[XED_ICLASS_VMCLEAR] = 44; + xed_enc_iclass2group[XED_ICLASS_VMPTRLD] = 45; + xed_enc_iclass2group[XED_ICLASS_VMPTRST] = 45; + xed_enc_iclass2group[XED_ICLASS_CLRSSBSY] = 45; + xed_enc_iclass2group[XED_ICLASS_RSTORSSP] = 45; + xed_enc_iclass2group[XED_ICLASS_VMXON] = 46; + xed_enc_iclass2group[XED_ICLASS_CMPXCHG8B_LOCK] = 47; + xed_enc_iclass2group[XED_ICLASS_CMPXCHG8B] = 47; + xed_enc_iclass2group[XED_ICLASS_CMPXCHG16B_LOCK] = 48; + xed_enc_iclass2group[XED_ICLASS_CMPXCHG16B] = 48; + xed_enc_iclass2group[XED_ICLASS_MOV] = 49; + xed_enc_iclass2group[XED_ICLASS_PSRLW] = 50; + xed_enc_iclass2group[XED_ICLASS_PSRAW] = 50; + xed_enc_iclass2group[XED_ICLASS_PSLLW] = 50; + xed_enc_iclass2group[XED_ICLASS_PSRLD] = 50; + xed_enc_iclass2group[XED_ICLASS_PSRAD] = 50; + xed_enc_iclass2group[XED_ICLASS_PSLLD] = 50; + xed_enc_iclass2group[XED_ICLASS_PSRLQ] = 50; + xed_enc_iclass2group[XED_ICLASS_PSLLQ] = 50; + xed_enc_iclass2group[XED_ICLASS_PSRLDQ] = 51; + xed_enc_iclass2group[XED_ICLASS_PSLLDQ] = 51; + xed_enc_iclass2group[XED_ICLASS_FXSAVE] = 52; + xed_enc_iclass2group[XED_ICLASS_FXRSTOR] = 52; + xed_enc_iclass2group[XED_ICLASS_FXSAVE64] = 52; + xed_enc_iclass2group[XED_ICLASS_FXRSTOR64] = 52; + xed_enc_iclass2group[XED_ICLASS_LDMXCSR] = 53; + xed_enc_iclass2group[XED_ICLASS_STMXCSR] = 53; + xed_enc_iclass2group[XED_ICLASS_PREFETCHNTA] = 54; + xed_enc_iclass2group[XED_ICLASS_PREFETCHT0] = 54; + xed_enc_iclass2group[XED_ICLASS_PREFETCHT1] = 54; + xed_enc_iclass2group[XED_ICLASS_PREFETCHT2] = 54; + xed_enc_iclass2group[XED_ICLASS_CLFLUSH] = 54; + xed_enc_iclass2group[XED_ICLASS_PREFETCH_EXCLUSIVE] = 54; + xed_enc_iclass2group[XED_ICLASS_NOP] = 55; + xed_enc_iclass2group[XED_ICLASS_MONITOR] = 56; + xed_enc_iclass2group[XED_ICLASS_MONITORX] = 56; + xed_enc_iclass2group[XED_ICLASS_INVLPG] = 57; + xed_enc_iclass2group[XED_ICLASS_CLDEMOTE] = 57; + xed_enc_iclass2group[XED_ICLASS_PREFETCHWT1] = 57; + xed_enc_iclass2group[XED_ICLASS_SWAPGS] = 58; + xed_enc_iclass2group[XED_ICLASS_CDQE] = 58; + xed_enc_iclass2group[XED_ICLASS_CQO] = 58; + xed_enc_iclass2group[XED_ICLASS_STOSQ] = 58; + xed_enc_iclass2group[XED_ICLASS_REPE_SCASQ] = 58; + xed_enc_iclass2group[XED_ICLASS_REPNE_SCASQ] = 58; + xed_enc_iclass2group[XED_ICLASS_SCASQ] = 58; + xed_enc_iclass2group[XED_ICLASS_IRETQ] = 58; + xed_enc_iclass2group[XED_ICLASS_SYSRET] = 58; + xed_enc_iclass2group[XED_ICLASS_SYSRET64] = 58; + xed_enc_iclass2group[XED_ICLASS_CLUI] = 58; + xed_enc_iclass2group[XED_ICLASS_STUI] = 58; + xed_enc_iclass2group[XED_ICLASS_TESTUI] = 58; + xed_enc_iclass2group[XED_ICLASS_UIRET] = 58; + xed_enc_iclass2group[XED_ICLASS_SEAMCALL] = 58; + xed_enc_iclass2group[XED_ICLASS_SEAMOPS] = 58; + xed_enc_iclass2group[XED_ICLASS_SEAMRET] = 58; + xed_enc_iclass2group[XED_ICLASS_MOVHLPS] = 59; + xed_enc_iclass2group[XED_ICLASS_MOVLHPS] = 59; + xed_enc_iclass2group[XED_ICLASS_LOADIWKEY] = 59; + xed_enc_iclass2group[XED_ICLASS_MOVLPS] = 60; + xed_enc_iclass2group[XED_ICLASS_MOVHPS] = 60; + xed_enc_iclass2group[XED_ICLASS_DAA] = 61; + xed_enc_iclass2group[XED_ICLASS_DAS] = 61; + xed_enc_iclass2group[XED_ICLASS_AAA] = 61; + xed_enc_iclass2group[XED_ICLASS_AAS] = 61; + xed_enc_iclass2group[XED_ICLASS_INTO] = 61; + xed_enc_iclass2group[XED_ICLASS_SALC] = 61; + xed_enc_iclass2group[XED_ICLASS_SYSRET_AMD] = 61; + xed_enc_iclass2group[XED_ICLASS_PUSHA] = 62; + xed_enc_iclass2group[XED_ICLASS_PUSHAD] = 62; + xed_enc_iclass2group[XED_ICLASS_POPA] = 62; + xed_enc_iclass2group[XED_ICLASS_POPAD] = 62; + xed_enc_iclass2group[XED_ICLASS_PUSHFD] = 62; + xed_enc_iclass2group[XED_ICLASS_POPFD] = 62; + xed_enc_iclass2group[XED_ICLASS_BOUND] = 63; + xed_enc_iclass2group[XED_ICLASS_ARPL] = 64; + xed_enc_iclass2group[XED_ICLASS_MOVSXD] = 65; + xed_enc_iclass2group[XED_ICLASS_REP_INSB] = 66; + xed_enc_iclass2group[XED_ICLASS_REP_STOSB] = 66; + xed_enc_iclass2group[XED_ICLASS_REP_INSW] = 67; + xed_enc_iclass2group[XED_ICLASS_REP_STOSW] = 67; + xed_enc_iclass2group[XED_ICLASS_REP_STOSD] = 67; + xed_enc_iclass2group[XED_ICLASS_INSW] = 68; + xed_enc_iclass2group[XED_ICLASS_CBW] = 68; + xed_enc_iclass2group[XED_ICLASS_CWDE] = 68; + xed_enc_iclass2group[XED_ICLASS_CWD] = 68; + xed_enc_iclass2group[XED_ICLASS_CDQ] = 68; + xed_enc_iclass2group[XED_ICLASS_PUSHF] = 68; + xed_enc_iclass2group[XED_ICLASS_POPF] = 68; + xed_enc_iclass2group[XED_ICLASS_STOSW] = 68; + xed_enc_iclass2group[XED_ICLASS_STOSD] = 68; + xed_enc_iclass2group[XED_ICLASS_REPE_SCASW] = 68; + xed_enc_iclass2group[XED_ICLASS_REPNE_SCASW] = 68; + xed_enc_iclass2group[XED_ICLASS_SCASW] = 68; + xed_enc_iclass2group[XED_ICLASS_REPE_SCASD] = 68; + xed_enc_iclass2group[XED_ICLASS_REPNE_SCASD] = 68; + xed_enc_iclass2group[XED_ICLASS_SCASD] = 68; + xed_enc_iclass2group[XED_ICLASS_IRET] = 68; + xed_enc_iclass2group[XED_ICLASS_IRETD] = 68; + xed_enc_iclass2group[XED_ICLASS_REP_INSD] = 69; + xed_enc_iclass2group[XED_ICLASS_INSD] = 70; + xed_enc_iclass2group[XED_ICLASS_REP_OUTSB] = 71; + xed_enc_iclass2group[XED_ICLASS_REP_LODSB] = 71; + xed_enc_iclass2group[XED_ICLASS_OUTSB] = 72; + xed_enc_iclass2group[XED_ICLASS_REPE_CMPSB] = 72; + xed_enc_iclass2group[XED_ICLASS_REPNE_CMPSB] = 72; + xed_enc_iclass2group[XED_ICLASS_CMPSB] = 72; + xed_enc_iclass2group[XED_ICLASS_LODSB] = 72; + xed_enc_iclass2group[XED_ICLASS_XLAT] = 72; + xed_enc_iclass2group[XED_ICLASS_REP_OUTSW] = 73; + xed_enc_iclass2group[XED_ICLASS_REP_LODSW] = 73; + xed_enc_iclass2group[XED_ICLASS_REP_LODSD] = 73; + xed_enc_iclass2group[XED_ICLASS_OUTSW] = 74; + xed_enc_iclass2group[XED_ICLASS_REPE_CMPSW] = 74; + xed_enc_iclass2group[XED_ICLASS_REPNE_CMPSW] = 74; + xed_enc_iclass2group[XED_ICLASS_CMPSW] = 74; + xed_enc_iclass2group[XED_ICLASS_REPE_CMPSD] = 74; + xed_enc_iclass2group[XED_ICLASS_REPNE_CMPSD] = 74; + xed_enc_iclass2group[XED_ICLASS_CMPSD] = 74; + xed_enc_iclass2group[XED_ICLASS_LODSW] = 74; + xed_enc_iclass2group[XED_ICLASS_LODSD] = 74; + xed_enc_iclass2group[XED_ICLASS_REP_OUTSD] = 75; + xed_enc_iclass2group[XED_ICLASS_OUTSD] = 76; + xed_enc_iclass2group[XED_ICLASS_JO] = 77; + xed_enc_iclass2group[XED_ICLASS_JNO] = 77; + xed_enc_iclass2group[XED_ICLASS_JB] = 77; + xed_enc_iclass2group[XED_ICLASS_JNB] = 77; + xed_enc_iclass2group[XED_ICLASS_JZ] = 77; + xed_enc_iclass2group[XED_ICLASS_JNZ] = 77; + xed_enc_iclass2group[XED_ICLASS_JBE] = 77; + xed_enc_iclass2group[XED_ICLASS_JNBE] = 77; + xed_enc_iclass2group[XED_ICLASS_JS] = 77; + xed_enc_iclass2group[XED_ICLASS_JNS] = 77; + xed_enc_iclass2group[XED_ICLASS_JP] = 77; + xed_enc_iclass2group[XED_ICLASS_JNP] = 77; + xed_enc_iclass2group[XED_ICLASS_JL] = 77; + xed_enc_iclass2group[XED_ICLASS_JNL] = 77; + xed_enc_iclass2group[XED_ICLASS_JLE] = 77; + xed_enc_iclass2group[XED_ICLASS_JNLE] = 77; + xed_enc_iclass2group[XED_ICLASS_XCHG] = 78; + xed_enc_iclass2group[XED_ICLASS_LEA] = 79; + xed_enc_iclass2group[XED_ICLASS_PUSHFQ] = 80; + xed_enc_iclass2group[XED_ICLASS_POPFQ] = 80; + xed_enc_iclass2group[XED_ICLASS_REP_MOVSB] = 81; + xed_enc_iclass2group[XED_ICLASS_MOVSB] = 82; + xed_enc_iclass2group[XED_ICLASS_REP_MOVSW] = 83; + xed_enc_iclass2group[XED_ICLASS_REP_MOVSD] = 83; + xed_enc_iclass2group[XED_ICLASS_MOVSW] = 84; + xed_enc_iclass2group[XED_ICLASS_MOVSD] = 84; + xed_enc_iclass2group[XED_ICLASS_REP_MOVSQ] = 85; + xed_enc_iclass2group[XED_ICLASS_MOVSQ] = 86; + xed_enc_iclass2group[XED_ICLASS_REPE_CMPSQ] = 87; + xed_enc_iclass2group[XED_ICLASS_REPNE_CMPSQ] = 87; + xed_enc_iclass2group[XED_ICLASS_CMPSQ] = 87; + xed_enc_iclass2group[XED_ICLASS_LODSQ] = 87; + xed_enc_iclass2group[XED_ICLASS_REP_STOSQ] = 88; + xed_enc_iclass2group[XED_ICLASS_REP_LODSQ] = 89; + xed_enc_iclass2group[XED_ICLASS_RET_NEAR] = 90; + xed_enc_iclass2group[XED_ICLASS_LES] = 91; + xed_enc_iclass2group[XED_ICLASS_LDS] = 91; + xed_enc_iclass2group[XED_ICLASS_ENTER] = 92; + xed_enc_iclass2group[XED_ICLASS_LEAVE] = 93; + xed_enc_iclass2group[XED_ICLASS_RET_FAR] = 94; + xed_enc_iclass2group[XED_ICLASS_INT] = 95; + xed_enc_iclass2group[XED_ICLASS_XABORT] = 95; + xed_enc_iclass2group[XED_ICLASS_HRESET] = 95; + xed_enc_iclass2group[XED_ICLASS_AAM] = 96; + xed_enc_iclass2group[XED_ICLASS_AAD] = 96; + xed_enc_iclass2group[XED_ICLASS_LOOPNE] = 97; + xed_enc_iclass2group[XED_ICLASS_LOOPE] = 97; + xed_enc_iclass2group[XED_ICLASS_LOOP] = 98; + xed_enc_iclass2group[XED_ICLASS_JCXZ] = 99; + xed_enc_iclass2group[XED_ICLASS_JECXZ] = 100; + xed_enc_iclass2group[XED_ICLASS_JRCXZ] = 101; + xed_enc_iclass2group[XED_ICLASS_IN] = 102; + xed_enc_iclass2group[XED_ICLASS_OUT] = 103; + xed_enc_iclass2group[XED_ICLASS_LAR] = 104; + xed_enc_iclass2group[XED_ICLASS_LSL] = 105; + xed_enc_iclass2group[XED_ICLASS_SYSCALL] = 106; + xed_enc_iclass2group[XED_ICLASS_MOVUPS] = 107; + xed_enc_iclass2group[XED_ICLASS_MOVAPS] = 107; + xed_enc_iclass2group[XED_ICLASS_UNPCKLPS] = 108; + xed_enc_iclass2group[XED_ICLASS_UNPCKHPS] = 108; + xed_enc_iclass2group[XED_ICLASS_CVTDQ2PS] = 108; + xed_enc_iclass2group[XED_ICLASS_SHA1MSG1] = 108; + xed_enc_iclass2group[XED_ICLASS_SHA1MSG2] = 108; + xed_enc_iclass2group[XED_ICLASS_SHA1NEXTE] = 108; + xed_enc_iclass2group[XED_ICLASS_SHA256MSG1] = 108; + xed_enc_iclass2group[XED_ICLASS_SHA256MSG2] = 108; + xed_enc_iclass2group[XED_ICLASS_SHA256RNDS2] = 108; + xed_enc_iclass2group[XED_ICLASS_GF2P8MULB] = 108; + xed_enc_iclass2group[XED_ICLASS_MOVSS] = 109; + xed_enc_iclass2group[XED_ICLASS_MOVSLDUP] = 110; + xed_enc_iclass2group[XED_ICLASS_MOVSHDUP] = 110; + xed_enc_iclass2group[XED_ICLASS_ADDSUBPS] = 110; + xed_enc_iclass2group[XED_ICLASS_CVTTPS2DQ] = 110; + xed_enc_iclass2group[XED_ICLASS_HADDPS] = 110; + xed_enc_iclass2group[XED_ICLASS_HSUBPS] = 110; + xed_enc_iclass2group[XED_ICLASS_MOVUPD] = 111; + xed_enc_iclass2group[XED_ICLASS_MOVAPD] = 111; + xed_enc_iclass2group[XED_ICLASS_MOVLPD] = 112; + xed_enc_iclass2group[XED_ICLASS_MOVHPD] = 112; + xed_enc_iclass2group[XED_ICLASS_UNPCKLPD] = 113; + xed_enc_iclass2group[XED_ICLASS_UNPCKHPD] = 113; + xed_enc_iclass2group[XED_ICLASS_PUNPCKLQDQ] = 113; + xed_enc_iclass2group[XED_ICLASS_PUNPCKHQDQ] = 113; + xed_enc_iclass2group[XED_ICLASS_PCMPGTQ] = 113; + xed_enc_iclass2group[XED_ICLASS_BLENDVPD] = 113; + xed_enc_iclass2group[XED_ICLASS_BLENDVPS] = 113; + xed_enc_iclass2group[XED_ICLASS_PCMPEQQ] = 113; + xed_enc_iclass2group[XED_ICLASS_PACKUSDW] = 113; + xed_enc_iclass2group[XED_ICLASS_PBLENDVB] = 113; + xed_enc_iclass2group[XED_ICLASS_PTEST] = 113; + xed_enc_iclass2group[XED_ICLASS_PHMINPOSUW] = 113; + xed_enc_iclass2group[XED_ICLASS_PMAXSB] = 113; + xed_enc_iclass2group[XED_ICLASS_PMAXSD] = 113; + xed_enc_iclass2group[XED_ICLASS_PMAXUD] = 113; + xed_enc_iclass2group[XED_ICLASS_PMAXUW] = 113; + xed_enc_iclass2group[XED_ICLASS_PMINSB] = 113; + xed_enc_iclass2group[XED_ICLASS_PMINSD] = 113; + xed_enc_iclass2group[XED_ICLASS_PMINUD] = 113; + xed_enc_iclass2group[XED_ICLASS_PMINUW] = 113; + xed_enc_iclass2group[XED_ICLASS_PMULLD] = 113; + xed_enc_iclass2group[XED_ICLASS_PMULDQ] = 113; + xed_enc_iclass2group[XED_ICLASS_AESENC] = 113; + xed_enc_iclass2group[XED_ICLASS_AESENCLAST] = 113; + xed_enc_iclass2group[XED_ICLASS_AESDEC] = 113; + xed_enc_iclass2group[XED_ICLASS_AESDECLAST] = 113; + xed_enc_iclass2group[XED_ICLASS_AESIMC] = 113; + xed_enc_iclass2group[XED_ICLASS_MOVSD_XMM] = 114; + xed_enc_iclass2group[XED_ICLASS_MOVDDUP] = 115; + xed_enc_iclass2group[XED_ICLASS_CVTDQ2PD] = 115; + xed_enc_iclass2group[XED_ICLASS_MOV_CR] = 116; + xed_enc_iclass2group[XED_ICLASS_MOV_DR] = 117; + xed_enc_iclass2group[XED_ICLASS_SYSENTER] = 118; + xed_enc_iclass2group[XED_ICLASS_SYSEXIT] = 118; + xed_enc_iclass2group[XED_ICLASS_PCONFIG] = 118; + xed_enc_iclass2group[XED_ICLASS_TDCALL] = 118; + xed_enc_iclass2group[XED_ICLASS_CMOVO] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNO] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVB] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNB] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVZ] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNZ] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVBE] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNBE] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVS] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNS] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVP] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNP] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVL] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNL] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVLE] = 119; + xed_enc_iclass2group[XED_ICLASS_CMOVNLE] = 119; + xed_enc_iclass2group[XED_ICLASS_POPCNT] = 119; + xed_enc_iclass2group[XED_ICLASS_TZCNT] = 119; + xed_enc_iclass2group[XED_ICLASS_MOVMSKPS] = 120; + xed_enc_iclass2group[XED_ICLASS_SQRTPS] = 121; + xed_enc_iclass2group[XED_ICLASS_RSQRTPS] = 121; + xed_enc_iclass2group[XED_ICLASS_RCPPS] = 121; + xed_enc_iclass2group[XED_ICLASS_ADDPS] = 121; + xed_enc_iclass2group[XED_ICLASS_MULPS] = 121; + xed_enc_iclass2group[XED_ICLASS_SUBPS] = 121; + xed_enc_iclass2group[XED_ICLASS_MINPS] = 121; + xed_enc_iclass2group[XED_ICLASS_DIVPS] = 121; + xed_enc_iclass2group[XED_ICLASS_MAXPS] = 121; + xed_enc_iclass2group[XED_ICLASS_ANDPS] = 122; + xed_enc_iclass2group[XED_ICLASS_ANDNPS] = 122; + xed_enc_iclass2group[XED_ICLASS_ORPS] = 122; + xed_enc_iclass2group[XED_ICLASS_XORPS] = 122; + xed_enc_iclass2group[XED_ICLASS_SQRTSS] = 123; + xed_enc_iclass2group[XED_ICLASS_RSQRTSS] = 123; + xed_enc_iclass2group[XED_ICLASS_RCPSS] = 123; + xed_enc_iclass2group[XED_ICLASS_ADDSS] = 123; + xed_enc_iclass2group[XED_ICLASS_MULSS] = 123; + xed_enc_iclass2group[XED_ICLASS_CVTSS2SD] = 123; + xed_enc_iclass2group[XED_ICLASS_SUBSS] = 123; + xed_enc_iclass2group[XED_ICLASS_MINSS] = 123; + xed_enc_iclass2group[XED_ICLASS_DIVSS] = 123; + xed_enc_iclass2group[XED_ICLASS_MAXSS] = 123; + xed_enc_iclass2group[XED_ICLASS_MOVMSKPD] = 124; + xed_enc_iclass2group[XED_ICLASS_SQRTPD] = 125; + xed_enc_iclass2group[XED_ICLASS_ADDSUBPD] = 125; + xed_enc_iclass2group[XED_ICLASS_CVTTPD2DQ] = 125; + xed_enc_iclass2group[XED_ICLASS_ADDPD] = 125; + xed_enc_iclass2group[XED_ICLASS_MULPD] = 125; + xed_enc_iclass2group[XED_ICLASS_CVTPD2PS] = 125; + xed_enc_iclass2group[XED_ICLASS_SUBPD] = 125; + xed_enc_iclass2group[XED_ICLASS_MINPD] = 125; + xed_enc_iclass2group[XED_ICLASS_DIVPD] = 125; + xed_enc_iclass2group[XED_ICLASS_MAXPD] = 125; + xed_enc_iclass2group[XED_ICLASS_HADDPD] = 125; + xed_enc_iclass2group[XED_ICLASS_HSUBPD] = 125; + xed_enc_iclass2group[XED_ICLASS_ANDPD] = 126; + xed_enc_iclass2group[XED_ICLASS_ANDNPD] = 126; + xed_enc_iclass2group[XED_ICLASS_ORPD] = 126; + xed_enc_iclass2group[XED_ICLASS_XORPD] = 126; + xed_enc_iclass2group[XED_ICLASS_SQRTSD] = 127; + xed_enc_iclass2group[XED_ICLASS_ADDSD] = 127; + xed_enc_iclass2group[XED_ICLASS_MULSD] = 127; + xed_enc_iclass2group[XED_ICLASS_CVTSD2SS] = 127; + xed_enc_iclass2group[XED_ICLASS_SUBSD] = 127; + xed_enc_iclass2group[XED_ICLASS_MINSD] = 127; + xed_enc_iclass2group[XED_ICLASS_DIVSD] = 127; + xed_enc_iclass2group[XED_ICLASS_MAXSD] = 127; + xed_enc_iclass2group[XED_ICLASS_PUNPCKLBW] = 128; + xed_enc_iclass2group[XED_ICLASS_PUNPCKLWD] = 128; + xed_enc_iclass2group[XED_ICLASS_PUNPCKLDQ] = 128; + xed_enc_iclass2group[XED_ICLASS_PACKSSWB] = 129; + xed_enc_iclass2group[XED_ICLASS_PCMPGTB] = 129; + xed_enc_iclass2group[XED_ICLASS_PCMPGTW] = 129; + xed_enc_iclass2group[XED_ICLASS_PCMPGTD] = 129; + xed_enc_iclass2group[XED_ICLASS_PACKUSWB] = 129; + xed_enc_iclass2group[XED_ICLASS_PCMPEQB] = 129; + xed_enc_iclass2group[XED_ICLASS_PCMPEQW] = 129; + xed_enc_iclass2group[XED_ICLASS_PCMPEQD] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDQ] = 129; + xed_enc_iclass2group[XED_ICLASS_PMULLW] = 129; + xed_enc_iclass2group[XED_ICLASS_PAVGB] = 129; + xed_enc_iclass2group[XED_ICLASS_PAVGW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMULHUW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMULHW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMULUDQ] = 129; + xed_enc_iclass2group[XED_ICLASS_PMADDWD] = 129; + xed_enc_iclass2group[XED_ICLASS_PSADBW] = 129; + xed_enc_iclass2group[XED_ICLASS_PUNPCKHBW] = 129; + xed_enc_iclass2group[XED_ICLASS_PUNPCKHWD] = 129; + xed_enc_iclass2group[XED_ICLASS_PUNPCKHDQ] = 129; + xed_enc_iclass2group[XED_ICLASS_PACKSSDW] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBUSB] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBUSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMINUB] = 129; + xed_enc_iclass2group[XED_ICLASS_PAND] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDUSB] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDUSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMAXUB] = 129; + xed_enc_iclass2group[XED_ICLASS_PANDN] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBSB] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMINSW] = 129; + xed_enc_iclass2group[XED_ICLASS_POR] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDSB] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMAXSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PXOR] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBB] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBW] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBD] = 129; + xed_enc_iclass2group[XED_ICLASS_PSUBQ] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDB] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDW] = 129; + xed_enc_iclass2group[XED_ICLASS_PADDD] = 129; + xed_enc_iclass2group[XED_ICLASS_PHADDW] = 129; + xed_enc_iclass2group[XED_ICLASS_PHADDD] = 129; + xed_enc_iclass2group[XED_ICLASS_PHADDSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PHSUBW] = 129; + xed_enc_iclass2group[XED_ICLASS_PHSUBD] = 129; + xed_enc_iclass2group[XED_ICLASS_PHSUBSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMADDUBSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PMULHRSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PSHUFB] = 129; + xed_enc_iclass2group[XED_ICLASS_PSIGNB] = 129; + xed_enc_iclass2group[XED_ICLASS_PSIGNW] = 129; + xed_enc_iclass2group[XED_ICLASS_PSIGND] = 129; + xed_enc_iclass2group[XED_ICLASS_PABSB] = 129; + xed_enc_iclass2group[XED_ICLASS_PABSW] = 129; + xed_enc_iclass2group[XED_ICLASS_PABSD] = 129; + xed_enc_iclass2group[XED_ICLASS_PSHUFW] = 130; + xed_enc_iclass2group[XED_ICLASS_PSHUFD] = 131; + xed_enc_iclass2group[XED_ICLASS_BLENDPD] = 131; + xed_enc_iclass2group[XED_ICLASS_BLENDPS] = 131; + xed_enc_iclass2group[XED_ICLASS_DPPD] = 131; + xed_enc_iclass2group[XED_ICLASS_DPPS] = 131; + xed_enc_iclass2group[XED_ICLASS_MPSADBW] = 131; + xed_enc_iclass2group[XED_ICLASS_PBLENDW] = 131; + xed_enc_iclass2group[XED_ICLASS_AESKEYGENASSIST] = 131; + xed_enc_iclass2group[XED_ICLASS_PCLMULQDQ] = 131; + xed_enc_iclass2group[XED_ICLASS_PSHUFLW] = 132; + xed_enc_iclass2group[XED_ICLASS_PSHUFHW] = 132; + xed_enc_iclass2group[XED_ICLASS_SETO] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNO] = 133; + xed_enc_iclass2group[XED_ICLASS_SETB] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNB] = 133; + xed_enc_iclass2group[XED_ICLASS_SETZ] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNZ] = 133; + xed_enc_iclass2group[XED_ICLASS_SETBE] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNBE] = 133; + xed_enc_iclass2group[XED_ICLASS_SETS] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNS] = 133; + xed_enc_iclass2group[XED_ICLASS_SETP] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNP] = 133; + xed_enc_iclass2group[XED_ICLASS_SETL] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNL] = 133; + xed_enc_iclass2group[XED_ICLASS_SETLE] = 133; + xed_enc_iclass2group[XED_ICLASS_SETNLE] = 133; + xed_enc_iclass2group[XED_ICLASS_CMPXCHG_LOCK] = 134; + xed_enc_iclass2group[XED_ICLASS_XADD_LOCK] = 134; + xed_enc_iclass2group[XED_ICLASS_CMPXCHG] = 135; + xed_enc_iclass2group[XED_ICLASS_XADD] = 135; + xed_enc_iclass2group[XED_ICLASS_LSS] = 136; + xed_enc_iclass2group[XED_ICLASS_LFS] = 136; + xed_enc_iclass2group[XED_ICLASS_LGS] = 136; + xed_enc_iclass2group[XED_ICLASS_MOVZX] = 137; + xed_enc_iclass2group[XED_ICLASS_MOVSX] = 137; + xed_enc_iclass2group[XED_ICLASS_CMPPS] = 138; + xed_enc_iclass2group[XED_ICLASS_SHUFPS] = 138; + xed_enc_iclass2group[XED_ICLASS_MOVNTI] = 139; + xed_enc_iclass2group[XED_ICLASS_PINSRW] = 140; + xed_enc_iclass2group[XED_ICLASS_PEXTRW] = 141; + xed_enc_iclass2group[XED_ICLASS_CMPSS] = 142; + xed_enc_iclass2group[XED_ICLASS_CMPPD] = 143; + xed_enc_iclass2group[XED_ICLASS_SHUFPD] = 143; + xed_enc_iclass2group[XED_ICLASS_ROUNDPD] = 143; + xed_enc_iclass2group[XED_ICLASS_CMPSD_XMM] = 144; + xed_enc_iclass2group[XED_ICLASS_PMOVMSKB] = 145; + xed_enc_iclass2group[XED_ICLASS_MOVQ2DQ] = 146; + xed_enc_iclass2group[XED_ICLASS_MOVDQ2Q] = 147; + xed_enc_iclass2group[XED_ICLASS_MOVNTQ] = 148; + xed_enc_iclass2group[XED_ICLASS_MOVNTDQ] = 149; + xed_enc_iclass2group[XED_ICLASS_MOVNTPD] = 149; + xed_enc_iclass2group[XED_ICLASS_CVTPD2DQ] = 150; + xed_enc_iclass2group[XED_ICLASS_MASKMOVQ] = 151; + xed_enc_iclass2group[XED_ICLASS_MASKMOVDQU] = 152; + xed_enc_iclass2group[XED_ICLASS_LDDQU] = 153; + xed_enc_iclass2group[XED_ICLASS_WBINVD] = 154; + xed_enc_iclass2group[XED_ICLASS_UD0] = 155; + xed_enc_iclass2group[XED_ICLASS_UD1] = 156; + xed_enc_iclass2group[XED_ICLASS_CVTPI2PS] = 157; + xed_enc_iclass2group[XED_ICLASS_MOVNTPS] = 158; + xed_enc_iclass2group[XED_ICLASS_CVTTPS2PI] = 159; + xed_enc_iclass2group[XED_ICLASS_CVTPS2PI] = 159; + xed_enc_iclass2group[XED_ICLASS_UCOMISS] = 160; + xed_enc_iclass2group[XED_ICLASS_COMISS] = 160; + xed_enc_iclass2group[XED_ICLASS_CVTSI2SS] = 161; + xed_enc_iclass2group[XED_ICLASS_CVTSI2SD] = 161; + xed_enc_iclass2group[XED_ICLASS_CVTTSS2SI] = 162; + xed_enc_iclass2group[XED_ICLASS_CVTSS2SI] = 162; + xed_enc_iclass2group[XED_ICLASS_CVTPI2PD] = 163; + xed_enc_iclass2group[XED_ICLASS_CVTTPD2PI] = 164; + xed_enc_iclass2group[XED_ICLASS_CVTPD2PI] = 164; + xed_enc_iclass2group[XED_ICLASS_UCOMISD] = 165; + xed_enc_iclass2group[XED_ICLASS_COMISD] = 165; + xed_enc_iclass2group[XED_ICLASS_CVTTSD2SI] = 166; + xed_enc_iclass2group[XED_ICLASS_CVTSD2SI] = 166; + xed_enc_iclass2group[XED_ICLASS_CVTPS2PD] = 167; + xed_enc_iclass2group[XED_ICLASS_CVTPS2DQ] = 168; + xed_enc_iclass2group[XED_ICLASS_MOVD] = 169; + xed_enc_iclass2group[XED_ICLASS_MOVQ] = 170; + xed_enc_iclass2group[XED_ICLASS_MOVDQU] = 171; + xed_enc_iclass2group[XED_ICLASS_VMREAD] = 172; + xed_enc_iclass2group[XED_ICLASS_VMWRITE] = 173; + xed_enc_iclass2group[XED_ICLASS_MOVDQA] = 174; + xed_enc_iclass2group[XED_ICLASS_SHRD] = 175; + xed_enc_iclass2group[XED_ICLASS_SHLD] = 175; + xed_enc_iclass2group[XED_ICLASS_BSF] = 176; + xed_enc_iclass2group[XED_ICLASS_BSR] = 177; + xed_enc_iclass2group[XED_ICLASS_BSWAP] = 178; + xed_enc_iclass2group[XED_ICLASS_PALIGNR] = 179; + xed_enc_iclass2group[XED_ICLASS_CRC32] = 180; + xed_enc_iclass2group[XED_ICLASS_MOVNTDQA] = 181; + xed_enc_iclass2group[XED_ICLASS_EXTRACTPS] = 182; + xed_enc_iclass2group[XED_ICLASS_PEXTRD] = 182; + xed_enc_iclass2group[XED_ICLASS_INSERTPS] = 183; + xed_enc_iclass2group[XED_ICLASS_ROUNDSS] = 183; + xed_enc_iclass2group[XED_ICLASS_PEXTRB] = 184; + xed_enc_iclass2group[XED_ICLASS_PEXTRW_SSE4] = 185; + xed_enc_iclass2group[XED_ICLASS_PEXTRQ] = 186; + xed_enc_iclass2group[XED_ICLASS_PINSRB] = 187; + xed_enc_iclass2group[XED_ICLASS_PINSRD] = 188; + xed_enc_iclass2group[XED_ICLASS_PINSRQ] = 189; + xed_enc_iclass2group[XED_ICLASS_ROUNDPS] = 190; + xed_enc_iclass2group[XED_ICLASS_ROUNDSD] = 191; + xed_enc_iclass2group[XED_ICLASS_PMOVSXBW] = 192; + xed_enc_iclass2group[XED_ICLASS_PMOVSXWD] = 192; + xed_enc_iclass2group[XED_ICLASS_PMOVSXDQ] = 192; + xed_enc_iclass2group[XED_ICLASS_PMOVZXBW] = 192; + xed_enc_iclass2group[XED_ICLASS_PMOVZXWD] = 192; + xed_enc_iclass2group[XED_ICLASS_PMOVZXDQ] = 192; + xed_enc_iclass2group[XED_ICLASS_PMOVSXBD] = 193; + xed_enc_iclass2group[XED_ICLASS_PMOVSXWQ] = 193; + xed_enc_iclass2group[XED_ICLASS_PMOVZXBD] = 193; + xed_enc_iclass2group[XED_ICLASS_PMOVZXWQ] = 193; + xed_enc_iclass2group[XED_ICLASS_PMOVSXBQ] = 194; + xed_enc_iclass2group[XED_ICLASS_PMOVZXBQ] = 194; + xed_enc_iclass2group[XED_ICLASS_PCMPESTRI] = 195; + xed_enc_iclass2group[XED_ICLASS_PCMPISTRI] = 195; + xed_enc_iclass2group[XED_ICLASS_PCMPESTRM] = 195; + xed_enc_iclass2group[XED_ICLASS_PCMPESTRI64] = 196; + xed_enc_iclass2group[XED_ICLASS_PCMPISTRI64] = 196; + xed_enc_iclass2group[XED_ICLASS_PCMPESTRM64] = 196; + xed_enc_iclass2group[XED_ICLASS_PCMPISTRM] = 197; + xed_enc_iclass2group[XED_ICLASS_XSAVE] = 198; + xed_enc_iclass2group[XED_ICLASS_XRSTOR] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVE64] = 198; + xed_enc_iclass2group[XED_ICLASS_XRSTOR64] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVEOPT] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVEOPT64] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVES] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVES64] = 198; + xed_enc_iclass2group[XED_ICLASS_XRSTORS] = 198; + xed_enc_iclass2group[XED_ICLASS_XRSTORS64] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVEC] = 198; + xed_enc_iclass2group[XED_ICLASS_XSAVEC64] = 198; + xed_enc_iclass2group[XED_ICLASS_MOVBE] = 199; + xed_enc_iclass2group[XED_ICLASS_INVEPT] = 200; + xed_enc_iclass2group[XED_ICLASS_INVVPID] = 200; + xed_enc_iclass2group[XED_ICLASS_INVPCID] = 200; + xed_enc_iclass2group[XED_ICLASS_PREFETCHW] = 201; + xed_enc_iclass2group[XED_ICLASS_PREFETCH_RESERVED] = 202; + xed_enc_iclass2group[XED_ICLASS_REP_MONTMUL] = 203; + xed_enc_iclass2group[XED_ICLASS_PI2FW] = 204; + xed_enc_iclass2group[XED_ICLASS_PI2FD] = 204; + xed_enc_iclass2group[XED_ICLASS_PF2IW] = 204; + xed_enc_iclass2group[XED_ICLASS_PF2ID] = 204; + xed_enc_iclass2group[XED_ICLASS_PFNACC] = 204; + xed_enc_iclass2group[XED_ICLASS_PFPNACC] = 204; + xed_enc_iclass2group[XED_ICLASS_PFCMPGE] = 204; + xed_enc_iclass2group[XED_ICLASS_PFMIN] = 204; + xed_enc_iclass2group[XED_ICLASS_PFRCP] = 204; + xed_enc_iclass2group[XED_ICLASS_PFRSQRT] = 204; + xed_enc_iclass2group[XED_ICLASS_PFSUB] = 204; + xed_enc_iclass2group[XED_ICLASS_PFADD] = 204; + xed_enc_iclass2group[XED_ICLASS_PFCMPGT] = 204; + xed_enc_iclass2group[XED_ICLASS_PFMAX] = 204; + xed_enc_iclass2group[XED_ICLASS_PFRCPIT1] = 204; + xed_enc_iclass2group[XED_ICLASS_PFRSQIT1] = 204; + xed_enc_iclass2group[XED_ICLASS_PFSUBR] = 204; + xed_enc_iclass2group[XED_ICLASS_PFACC] = 204; + xed_enc_iclass2group[XED_ICLASS_PFCMPEQ] = 204; + xed_enc_iclass2group[XED_ICLASS_PFMUL] = 204; + xed_enc_iclass2group[XED_ICLASS_PFRCPIT2] = 204; + xed_enc_iclass2group[XED_ICLASS_PMULHRW] = 204; + xed_enc_iclass2group[XED_ICLASS_PSWAPD] = 204; + xed_enc_iclass2group[XED_ICLASS_PAVGUSB] = 204; + xed_enc_iclass2group[XED_ICLASS_SYSCALL_AMD] = 205; + xed_enc_iclass2group[XED_ICLASS_VMRUN] = 206; + xed_enc_iclass2group[XED_ICLASS_VMLOAD] = 206; + xed_enc_iclass2group[XED_ICLASS_SKINIT] = 207; + xed_enc_iclass2group[XED_ICLASS_INVLPGA] = 208; + xed_enc_iclass2group[XED_ICLASS_EXTRQ] = 209; + xed_enc_iclass2group[XED_ICLASS_INSERTQ] = 210; + xed_enc_iclass2group[XED_ICLASS_MOVNTSD] = 211; + xed_enc_iclass2group[XED_ICLASS_MOVNTSS] = 212; + xed_enc_iclass2group[XED_ICLASS_LZCNT] = 213; + xed_enc_iclass2group[XED_ICLASS_PSMASH] = 214; + xed_enc_iclass2group[XED_ICLASS_PVALIDATE] = 215; + xed_enc_iclass2group[XED_ICLASS_RMPADJUST] = 216; + xed_enc_iclass2group[XED_ICLASS_RMPUPDATE] = 217; + xed_enc_iclass2group[XED_ICLASS_INVLPGB] = 218; + xed_enc_iclass2group[XED_ICLASS_VPMACSSWW] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSSWD] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSSDQL] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSWW] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSWD] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSDQL] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMADCSSWD] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMADCSWD] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSSDD] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSSDQH] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSDD] = 219; + xed_enc_iclass2group[XED_ICLASS_VPMACSDQH] = 219; + xed_enc_iclass2group[XED_ICLASS_VPCMOV] = 220; + xed_enc_iclass2group[XED_ICLASS_VPPERM] = 221; + xed_enc_iclass2group[XED_ICLASS_VPROTB] = 222; + xed_enc_iclass2group[XED_ICLASS_VPROTW] = 222; + xed_enc_iclass2group[XED_ICLASS_VPROTD] = 222; + xed_enc_iclass2group[XED_ICLASS_VPROTQ] = 222; + xed_enc_iclass2group[XED_ICLASS_VPCOMB] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMW] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMD] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMQ] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMUB] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMUW] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMUD] = 223; + xed_enc_iclass2group[XED_ICLASS_VPCOMUQ] = 223; + xed_enc_iclass2group[XED_ICLASS_VFRCZPS] = 224; + xed_enc_iclass2group[XED_ICLASS_VFRCZPD] = 224; + xed_enc_iclass2group[XED_ICLASS_VFRCZSS] = 225; + xed_enc_iclass2group[XED_ICLASS_VFRCZSD] = 226; + xed_enc_iclass2group[XED_ICLASS_VPSHLB] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHLW] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHLD] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHLQ] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHAB] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHAW] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHAD] = 227; + xed_enc_iclass2group[XED_ICLASS_VPSHAQ] = 227; + xed_enc_iclass2group[XED_ICLASS_VPHADDBW] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDBD] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDBQ] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDWD] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDWQ] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDUBW] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDUBD] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDUBQ] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDUWD] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDUWQ] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHSUBBW] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHSUBWD] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHSUBDQ] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDDQ] = 228; + xed_enc_iclass2group[XED_ICLASS_VPHADDUDQ] = 228; + xed_enc_iclass2group[XED_ICLASS_BEXTR_XOP] = 229; + xed_enc_iclass2group[XED_ICLASS_BLCFILL] = 230; + xed_enc_iclass2group[XED_ICLASS_BLSFILL] = 230; + xed_enc_iclass2group[XED_ICLASS_BLCS] = 230; + xed_enc_iclass2group[XED_ICLASS_TZMSK] = 230; + xed_enc_iclass2group[XED_ICLASS_BLCIC] = 230; + xed_enc_iclass2group[XED_ICLASS_BLSIC] = 230; + xed_enc_iclass2group[XED_ICLASS_T1MSKC] = 230; + xed_enc_iclass2group[XED_ICLASS_BLCMSK] = 230; + xed_enc_iclass2group[XED_ICLASS_BLCI] = 230; + xed_enc_iclass2group[XED_ICLASS_LLWPCB] = 231; + xed_enc_iclass2group[XED_ICLASS_SLWPCB] = 231; + xed_enc_iclass2group[XED_ICLASS_LWPINS] = 232; + xed_enc_iclass2group[XED_ICLASS_LWPVAL] = 232; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUBPS] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUBPD] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADDPS] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADDPD] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMADDPS] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMADDPD] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMSUBPS] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMSUBPD] = 233; + xed_enc_iclass2group[XED_ICLASS_VFNMADDPS] = 233; + xed_enc_iclass2group[XED_ICLASS_VFNMADDPD] = 233; + xed_enc_iclass2group[XED_ICLASS_VFNMSUBPS] = 233; + xed_enc_iclass2group[XED_ICLASS_VFNMSUBPD] = 233; + xed_enc_iclass2group[XED_ICLASS_VFMADDSS] = 234; + xed_enc_iclass2group[XED_ICLASS_VFMSUBSS] = 234; + xed_enc_iclass2group[XED_ICLASS_VFNMADDSS] = 234; + xed_enc_iclass2group[XED_ICLASS_VFNMSUBSS] = 234; + xed_enc_iclass2group[XED_ICLASS_VFMADDSD] = 235; + xed_enc_iclass2group[XED_ICLASS_VFMSUBSD] = 235; + xed_enc_iclass2group[XED_ICLASS_VFNMADDSD] = 235; + xed_enc_iclass2group[XED_ICLASS_VFNMSUBSD] = 235; + xed_enc_iclass2group[XED_ICLASS_VPERMIL2PS] = 236; + xed_enc_iclass2group[XED_ICLASS_VPERMIL2PD] = 236; + xed_enc_iclass2group[XED_ICLASS_BNDMK] = 237; + xed_enc_iclass2group[XED_ICLASS_BNDCL] = 238; + xed_enc_iclass2group[XED_ICLASS_BNDCU] = 238; + xed_enc_iclass2group[XED_ICLASS_BNDCN] = 238; + xed_enc_iclass2group[XED_ICLASS_BNDMOV] = 239; + xed_enc_iclass2group[XED_ICLASS_BNDLDX] = 240; + xed_enc_iclass2group[XED_ICLASS_BNDSTX] = 241; + xed_enc_iclass2group[XED_ICLASS_INCSSPD] = 242; + xed_enc_iclass2group[XED_ICLASS_RDSSPD] = 242; + xed_enc_iclass2group[XED_ICLASS_TPAUSE] = 242; + xed_enc_iclass2group[XED_ICLASS_UMWAIT] = 242; + xed_enc_iclass2group[XED_ICLASS_INCSSPQ] = 243; + xed_enc_iclass2group[XED_ICLASS_RDSSPQ] = 243; + xed_enc_iclass2group[XED_ICLASS_WRSSD] = 244; + xed_enc_iclass2group[XED_ICLASS_WRUSSD] = 244; + xed_enc_iclass2group[XED_ICLASS_WRSSQ] = 245; + xed_enc_iclass2group[XED_ICLASS_WRUSSQ] = 245; + xed_enc_iclass2group[XED_ICLASS_RDRAND] = 246; + xed_enc_iclass2group[XED_ICLASS_RDSEED] = 246; + xed_enc_iclass2group[XED_ICLASS_SHA1RNDS4] = 247; + xed_enc_iclass2group[XED_ICLASS_GF2P8AFFINEINVQB] = 247; + xed_enc_iclass2group[XED_ICLASS_GF2P8AFFINEQB] = 247; + xed_enc_iclass2group[XED_ICLASS_CLFLUSHOPT] = 248; + xed_enc_iclass2group[XED_ICLASS_CLWB] = 248; + xed_enc_iclass2group[XED_ICLASS_RDFSBASE] = 249; + xed_enc_iclass2group[XED_ICLASS_RDGSBASE] = 249; + xed_enc_iclass2group[XED_ICLASS_WRFSBASE] = 249; + xed_enc_iclass2group[XED_ICLASS_WRGSBASE] = 249; + xed_enc_iclass2group[XED_ICLASS_RDPID] = 250; + xed_enc_iclass2group[XED_ICLASS_PTWRITE] = 251; + xed_enc_iclass2group[XED_ICLASS_MOVDIR64B] = 252; + xed_enc_iclass2group[XED_ICLASS_MOVDIRI] = 253; + xed_enc_iclass2group[XED_ICLASS_UMONITOR] = 254; + xed_enc_iclass2group[XED_ICLASS_VADDPD] = 255; + xed_enc_iclass2group[XED_ICLASS_VDIVPD] = 255; + xed_enc_iclass2group[XED_ICLASS_VSUBPD] = 255; + xed_enc_iclass2group[XED_ICLASS_VMULPD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMADD132PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMADD213PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMADD231PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB132PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB213PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB231PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD132PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD213PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD231PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMSUB132PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMSUB213PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFMSUB231PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFNMADD132PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFNMADD213PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFNMADD231PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB132PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB213PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB231PD] = 255; + xed_enc_iclass2group[XED_ICLASS_VADDPS] = 256; + xed_enc_iclass2group[XED_ICLASS_VDIVPS] = 256; + xed_enc_iclass2group[XED_ICLASS_VSUBPS] = 256; + xed_enc_iclass2group[XED_ICLASS_VMULPS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMADD132PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMADD213PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMADD231PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB132PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB213PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB231PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD132PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD213PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD231PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMSUB132PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMSUB213PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFMSUB231PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFNMADD132PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFNMADD213PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFNMADD231PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB132PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB213PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB231PS] = 256; + xed_enc_iclass2group[XED_ICLASS_VADDSD] = 257; + xed_enc_iclass2group[XED_ICLASS_VCVTSD2SS] = 257; + xed_enc_iclass2group[XED_ICLASS_VDIVSD] = 257; + xed_enc_iclass2group[XED_ICLASS_VSQRTSD] = 257; + xed_enc_iclass2group[XED_ICLASS_VSUBSD] = 257; + xed_enc_iclass2group[XED_ICLASS_VMULSD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFMADD132SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFMADD213SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFMADD231SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFMSUB132SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFMSUB213SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFMSUB231SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFNMADD132SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFNMADD213SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFNMADD231SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB132SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB213SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB231SD] = 257; + xed_enc_iclass2group[XED_ICLASS_VADDSS] = 258; + xed_enc_iclass2group[XED_ICLASS_VDIVSS] = 258; + xed_enc_iclass2group[XED_ICLASS_VSQRTSS] = 258; + xed_enc_iclass2group[XED_ICLASS_VSUBSS] = 258; + xed_enc_iclass2group[XED_ICLASS_VMULSS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFMADD132SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFMADD213SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFMADD231SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFMSUB132SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFMSUB213SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFMSUB231SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFNMADD132SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFNMADD213SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFNMADD231SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB132SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB213SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB231SS] = 258; + xed_enc_iclass2group[XED_ICLASS_VADDSUBPD] = 259; + xed_enc_iclass2group[XED_ICLASS_VADDSUBPS] = 259; + xed_enc_iclass2group[XED_ICLASS_VHADDPD] = 259; + xed_enc_iclass2group[XED_ICLASS_VHADDPS] = 259; + xed_enc_iclass2group[XED_ICLASS_VHSUBPD] = 259; + xed_enc_iclass2group[XED_ICLASS_VHSUBPS] = 259; + xed_enc_iclass2group[XED_ICLASS_VPOR] = 259; + xed_enc_iclass2group[XED_ICLASS_VPAND] = 259; + xed_enc_iclass2group[XED_ICLASS_VPANDN] = 259; + xed_enc_iclass2group[XED_ICLASS_VPXOR] = 259; + xed_enc_iclass2group[XED_ICLASS_VPHADDW] = 259; + xed_enc_iclass2group[XED_ICLASS_VPHADDD] = 259; + xed_enc_iclass2group[XED_ICLASS_VPHADDSW] = 259; + xed_enc_iclass2group[XED_ICLASS_VPHSUBW] = 259; + xed_enc_iclass2group[XED_ICLASS_VPHSUBD] = 259; + xed_enc_iclass2group[XED_ICLASS_VPHSUBSW] = 259; + xed_enc_iclass2group[XED_ICLASS_VPSIGNB] = 259; + xed_enc_iclass2group[XED_ICLASS_VPSIGNW] = 259; + xed_enc_iclass2group[XED_ICLASS_VPSIGND] = 259; + xed_enc_iclass2group[XED_ICLASS_VANDPD] = 260; + xed_enc_iclass2group[XED_ICLASS_VANDNPD] = 260; + xed_enc_iclass2group[XED_ICLASS_VPADDQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VPMULUDQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VPMULDQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VPSUBQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKHQDQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKLQDQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VUNPCKHPD] = 260; + xed_enc_iclass2group[XED_ICLASS_VORPD] = 260; + xed_enc_iclass2group[XED_ICLASS_VUNPCKLPD] = 260; + xed_enc_iclass2group[XED_ICLASS_VXORPD] = 260; + xed_enc_iclass2group[XED_ICLASS_VPSLLVQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VPSRLVQ] = 260; + xed_enc_iclass2group[XED_ICLASS_VANDPS] = 261; + xed_enc_iclass2group[XED_ICLASS_VANDNPS] = 261; + xed_enc_iclass2group[XED_ICLASS_VPACKSSDW] = 261; + xed_enc_iclass2group[XED_ICLASS_VPACKUSDW] = 261; + xed_enc_iclass2group[XED_ICLASS_VPADDD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPMULLD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPSUBD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKHDQ] = 261; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKLDQ] = 261; + xed_enc_iclass2group[XED_ICLASS_VUNPCKHPS] = 261; + xed_enc_iclass2group[XED_ICLASS_VORPS] = 261; + xed_enc_iclass2group[XED_ICLASS_VPMAXSD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPMAXUD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPMINSD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPMINUD] = 261; + xed_enc_iclass2group[XED_ICLASS_VUNPCKLPS] = 261; + xed_enc_iclass2group[XED_ICLASS_VXORPS] = 261; + xed_enc_iclass2group[XED_ICLASS_VPSLLVD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPSRLVD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPSRAVD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPDPBUSD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPDPBUSDS] = 261; + xed_enc_iclass2group[XED_ICLASS_VPDPWSSD] = 261; + xed_enc_iclass2group[XED_ICLASS_VPDPWSSDS] = 261; + xed_enc_iclass2group[XED_ICLASS_VBLENDPD] = 262; + xed_enc_iclass2group[XED_ICLASS_VBLENDPS] = 262; + xed_enc_iclass2group[XED_ICLASS_VDPPS] = 262; + xed_enc_iclass2group[XED_ICLASS_VPBLENDW] = 262; + xed_enc_iclass2group[XED_ICLASS_VMPSADBW] = 262; + xed_enc_iclass2group[XED_ICLASS_VPBLENDD] = 262; + xed_enc_iclass2group[XED_ICLASS_VCMPPD] = 263; + xed_enc_iclass2group[XED_ICLASS_VCMPPS] = 264; + xed_enc_iclass2group[XED_ICLASS_VCMPSD] = 265; + xed_enc_iclass2group[XED_ICLASS_VCMPSS] = 266; + xed_enc_iclass2group[XED_ICLASS_VCOMISD] = 267; + xed_enc_iclass2group[XED_ICLASS_VUCOMISD] = 267; + xed_enc_iclass2group[XED_ICLASS_VCOMISS] = 268; + xed_enc_iclass2group[XED_ICLASS_VUCOMISS] = 268; + xed_enc_iclass2group[XED_ICLASS_VCVTDQ2PD] = 269; + xed_enc_iclass2group[XED_ICLASS_VCVTDQ2PS] = 270; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2DQ] = 270; + xed_enc_iclass2group[XED_ICLASS_VSQRTPS] = 270; + xed_enc_iclass2group[XED_ICLASS_VCVTPD2DQ] = 271; + xed_enc_iclass2group[XED_ICLASS_VCVTPD2PS] = 271; + xed_enc_iclass2group[XED_ICLASS_VCVTTPD2DQ] = 272; + xed_enc_iclass2group[XED_ICLASS_VCVTTPS2DQ] = 273; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2PD] = 274; + xed_enc_iclass2group[XED_ICLASS_VCVTSD2SI] = 275; + xed_enc_iclass2group[XED_ICLASS_VCVTTSD2SI] = 276; + xed_enc_iclass2group[XED_ICLASS_VCVTSS2SI] = 277; + xed_enc_iclass2group[XED_ICLASS_VCVTTSS2SI] = 278; + xed_enc_iclass2group[XED_ICLASS_VCVTSI2SD] = 279; + xed_enc_iclass2group[XED_ICLASS_VCVTSI2SS] = 280; + xed_enc_iclass2group[XED_ICLASS_VCVTSS2SD] = 281; + xed_enc_iclass2group[XED_ICLASS_VMAXSS] = 281; + xed_enc_iclass2group[XED_ICLASS_VMINSS] = 281; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTF128] = 282; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTI128] = 282; + xed_enc_iclass2group[XED_ICLASS_VDPPD] = 283; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTPS] = 284; + xed_enc_iclass2group[XED_ICLASS_VZEROALL] = 285; + xed_enc_iclass2group[XED_ICLASS_VZEROUPPER] = 285; + xed_enc_iclass2group[XED_ICLASS_VPERMILPD] = 286; + xed_enc_iclass2group[XED_ICLASS_VPERMILPS] = 287; + xed_enc_iclass2group[XED_ICLASS_VPERM2F128] = 288; + xed_enc_iclass2group[XED_ICLASS_VPERM2I128] = 288; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTSS] = 289; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTSD] = 290; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTF128] = 291; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTI128] = 291; + xed_enc_iclass2group[XED_ICLASS_VINSERTF128] = 292; + xed_enc_iclass2group[XED_ICLASS_VINSERTI128] = 292; + xed_enc_iclass2group[XED_ICLASS_VINSERTPS] = 293; + xed_enc_iclass2group[XED_ICLASS_VLDDQU] = 294; + xed_enc_iclass2group[XED_ICLASS_VMASKMOVPS] = 295; + xed_enc_iclass2group[XED_ICLASS_VMASKMOVPD] = 295; + xed_enc_iclass2group[XED_ICLASS_VPMASKMOVD] = 295; + xed_enc_iclass2group[XED_ICLASS_VPMASKMOVQ] = 295; + xed_enc_iclass2group[XED_ICLASS_VPTEST] = 296; + xed_enc_iclass2group[XED_ICLASS_VTESTPS] = 296; + xed_enc_iclass2group[XED_ICLASS_VTESTPD] = 296; + xed_enc_iclass2group[XED_ICLASS_VRCPPS] = 296; + xed_enc_iclass2group[XED_ICLASS_VRSQRTPS] = 296; + xed_enc_iclass2group[XED_ICLASS_VMAXPD] = 297; + xed_enc_iclass2group[XED_ICLASS_VMINPD] = 297; + xed_enc_iclass2group[XED_ICLASS_VMAXPS] = 298; + xed_enc_iclass2group[XED_ICLASS_VMINPS] = 298; + xed_enc_iclass2group[XED_ICLASS_VMAXSD] = 299; + xed_enc_iclass2group[XED_ICLASS_VMINSD] = 299; + xed_enc_iclass2group[XED_ICLASS_VMOVAPD] = 300; + xed_enc_iclass2group[XED_ICLASS_VMOVUPD] = 300; + xed_enc_iclass2group[XED_ICLASS_VMOVAPS] = 301; + xed_enc_iclass2group[XED_ICLASS_VMOVUPS] = 301; + xed_enc_iclass2group[XED_ICLASS_VMOVD] = 302; + xed_enc_iclass2group[XED_ICLASS_VMOVQ] = 303; + xed_enc_iclass2group[XED_ICLASS_VMOVDDUP] = 304; + xed_enc_iclass2group[XED_ICLASS_VMOVDQA] = 305; + xed_enc_iclass2group[XED_ICLASS_VMOVDQU] = 305; + xed_enc_iclass2group[XED_ICLASS_VMOVSHDUP] = 306; + xed_enc_iclass2group[XED_ICLASS_VMOVSLDUP] = 306; + xed_enc_iclass2group[XED_ICLASS_VPABSB] = 307; + xed_enc_iclass2group[XED_ICLASS_VPABSW] = 308; + xed_enc_iclass2group[XED_ICLASS_VPABSD] = 309; + xed_enc_iclass2group[XED_ICLASS_VPHMINPOSUW] = 310; + xed_enc_iclass2group[XED_ICLASS_VAESIMC] = 310; + xed_enc_iclass2group[XED_ICLASS_VPSHUFD] = 311; + xed_enc_iclass2group[XED_ICLASS_VPSHUFHW] = 312; + xed_enc_iclass2group[XED_ICLASS_VPSHUFLW] = 312; + xed_enc_iclass2group[XED_ICLASS_VPACKSSWB] = 313; + xed_enc_iclass2group[XED_ICLASS_VPACKUSWB] = 313; + xed_enc_iclass2group[XED_ICLASS_VPADDW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPADDSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPADDUSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPAVGW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMULHUW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMULHRSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMULHW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMULLW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPSUBSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPSUBUSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPSUBW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKHWD] = 313; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKLWD] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMAXSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMAXUW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMINSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMINUW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMADDWD] = 313; + xed_enc_iclass2group[XED_ICLASS_VPMADDUBSW] = 313; + xed_enc_iclass2group[XED_ICLASS_VPSLLW] = 314; + xed_enc_iclass2group[XED_ICLASS_VPSRLW] = 314; + xed_enc_iclass2group[XED_ICLASS_VPSRAW] = 314; + xed_enc_iclass2group[XED_ICLASS_VPSLLD] = 315; + xed_enc_iclass2group[XED_ICLASS_VPSRLD] = 315; + xed_enc_iclass2group[XED_ICLASS_VPSRAD] = 315; + xed_enc_iclass2group[XED_ICLASS_VPSLLQ] = 316; + xed_enc_iclass2group[XED_ICLASS_VPSRLQ] = 316; + xed_enc_iclass2group[XED_ICLASS_VPADDB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPADDSB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPADDUSB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPAVGB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPSHUFB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPSUBSB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPSUBUSB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPSUBB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKHBW] = 317; + xed_enc_iclass2group[XED_ICLASS_VPUNPCKLBW] = 317; + xed_enc_iclass2group[XED_ICLASS_VPMAXSB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPMAXUB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPMINSB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPMINUB] = 317; + xed_enc_iclass2group[XED_ICLASS_VGF2P8MULB] = 317; + xed_enc_iclass2group[XED_ICLASS_VPCMPEQB] = 318; + xed_enc_iclass2group[XED_ICLASS_VPCMPGTB] = 318; + xed_enc_iclass2group[XED_ICLASS_VPCMPEQW] = 319; + xed_enc_iclass2group[XED_ICLASS_VPCMPGTW] = 319; + xed_enc_iclass2group[XED_ICLASS_VPCMPEQD] = 320; + xed_enc_iclass2group[XED_ICLASS_VPCMPGTD] = 320; + xed_enc_iclass2group[XED_ICLASS_VPCMPEQQ] = 321; + xed_enc_iclass2group[XED_ICLASS_VPCMPGTQ] = 321; + xed_enc_iclass2group[XED_ICLASS_VPSADBW] = 322; + xed_enc_iclass2group[XED_ICLASS_VPSRLDQ] = 323; + xed_enc_iclass2group[XED_ICLASS_VPSLLDQ] = 323; + xed_enc_iclass2group[XED_ICLASS_VMOVLHPS] = 324; + xed_enc_iclass2group[XED_ICLASS_VMOVHLPS] = 324; + xed_enc_iclass2group[XED_ICLASS_VPALIGNR] = 325; + xed_enc_iclass2group[XED_ICLASS_VROUNDPD] = 326; + xed_enc_iclass2group[XED_ICLASS_VROUNDPS] = 326; + xed_enc_iclass2group[XED_ICLASS_VROUNDSD] = 327; + xed_enc_iclass2group[XED_ICLASS_VROUNDSS] = 328; + xed_enc_iclass2group[XED_ICLASS_VSHUFPD] = 329; + xed_enc_iclass2group[XED_ICLASS_VGF2P8AFFINEINVQB] = 329; + xed_enc_iclass2group[XED_ICLASS_VGF2P8AFFINEQB] = 329; + xed_enc_iclass2group[XED_ICLASS_VSHUFPS] = 330; + xed_enc_iclass2group[XED_ICLASS_VRCPSS] = 331; + xed_enc_iclass2group[XED_ICLASS_VRSQRTSS] = 331; + xed_enc_iclass2group[XED_ICLASS_VSQRTPD] = 332; + xed_enc_iclass2group[XED_ICLASS_VMOVSS] = 333; + xed_enc_iclass2group[XED_ICLASS_VMOVSD] = 334; + xed_enc_iclass2group[XED_ICLASS_VMOVLPD] = 335; + xed_enc_iclass2group[XED_ICLASS_VMOVHPD] = 335; + xed_enc_iclass2group[XED_ICLASS_VMOVLPS] = 336; + xed_enc_iclass2group[XED_ICLASS_VMOVHPS] = 336; + xed_enc_iclass2group[XED_ICLASS_VMOVMSKPD] = 337; + xed_enc_iclass2group[XED_ICLASS_VMOVMSKPS] = 337; + xed_enc_iclass2group[XED_ICLASS_VPMOVMSKB] = 337; + xed_enc_iclass2group[XED_ICLASS_VPMOVSXBW] = 338; + xed_enc_iclass2group[XED_ICLASS_VPMOVZXBW] = 338; + xed_enc_iclass2group[XED_ICLASS_VPMOVSXBD] = 339; + xed_enc_iclass2group[XED_ICLASS_VPMOVZXBD] = 339; + xed_enc_iclass2group[XED_ICLASS_VPMOVSXBQ] = 340; + xed_enc_iclass2group[XED_ICLASS_VPMOVZXBQ] = 340; + xed_enc_iclass2group[XED_ICLASS_VPMOVSXWD] = 341; + xed_enc_iclass2group[XED_ICLASS_VPMOVZXWD] = 341; + xed_enc_iclass2group[XED_ICLASS_VPMOVSXWQ] = 342; + xed_enc_iclass2group[XED_ICLASS_VPMOVZXWQ] = 342; + xed_enc_iclass2group[XED_ICLASS_VPMOVSXDQ] = 343; + xed_enc_iclass2group[XED_ICLASS_VPMOVZXDQ] = 343; + xed_enc_iclass2group[XED_ICLASS_VPEXTRB] = 344; + xed_enc_iclass2group[XED_ICLASS_VPEXTRW] = 345; + xed_enc_iclass2group[XED_ICLASS_VPEXTRQ] = 346; + xed_enc_iclass2group[XED_ICLASS_VPEXTRD] = 347; + xed_enc_iclass2group[XED_ICLASS_VPINSRB] = 348; + xed_enc_iclass2group[XED_ICLASS_VPINSRW] = 349; + xed_enc_iclass2group[XED_ICLASS_VPINSRD] = 350; + xed_enc_iclass2group[XED_ICLASS_VPINSRQ] = 351; + xed_enc_iclass2group[XED_ICLASS_VPCMPESTRI] = 352; + xed_enc_iclass2group[XED_ICLASS_VPCMPISTRI] = 352; + xed_enc_iclass2group[XED_ICLASS_VPCMPESTRM] = 352; + xed_enc_iclass2group[XED_ICLASS_VPCMPESTRI64] = 353; + xed_enc_iclass2group[XED_ICLASS_VPCMPISTRI64] = 353; + xed_enc_iclass2group[XED_ICLASS_VPCMPESTRM64] = 353; + xed_enc_iclass2group[XED_ICLASS_VPCMPISTRM] = 354; + xed_enc_iclass2group[XED_ICLASS_VAESKEYGENASSIST] = 354; + xed_enc_iclass2group[XED_ICLASS_VMASKMOVDQU] = 355; + xed_enc_iclass2group[XED_ICLASS_VLDMXCSR] = 356; + xed_enc_iclass2group[XED_ICLASS_VSTMXCSR] = 356; + xed_enc_iclass2group[XED_ICLASS_VPBLENDVB] = 357; + xed_enc_iclass2group[XED_ICLASS_VBLENDVPD] = 357; + xed_enc_iclass2group[XED_ICLASS_VBLENDVPS] = 357; + xed_enc_iclass2group[XED_ICLASS_VMOVNTDQA] = 358; + xed_enc_iclass2group[XED_ICLASS_VMOVNTDQ] = 359; + xed_enc_iclass2group[XED_ICLASS_VMOVNTPS] = 359; + xed_enc_iclass2group[XED_ICLASS_VMOVNTPD] = 360; + xed_enc_iclass2group[XED_ICLASS_VAESENC] = 361; + xed_enc_iclass2group[XED_ICLASS_VAESENCLAST] = 361; + xed_enc_iclass2group[XED_ICLASS_VAESDEC] = 361; + xed_enc_iclass2group[XED_ICLASS_VAESDECLAST] = 361; + xed_enc_iclass2group[XED_ICLASS_VPCLMULQDQ] = 362; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2PS] = 363; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2PH] = 364; + xed_enc_iclass2group[XED_ICLASS_VGATHERDPD] = 365; + xed_enc_iclass2group[XED_ICLASS_VPGATHERDQ] = 365; + xed_enc_iclass2group[XED_ICLASS_VGATHERDPS] = 366; + xed_enc_iclass2group[XED_ICLASS_VPGATHERDD] = 366; + xed_enc_iclass2group[XED_ICLASS_VGATHERQPD] = 367; + xed_enc_iclass2group[XED_ICLASS_VPGATHERQQ] = 367; + xed_enc_iclass2group[XED_ICLASS_VGATHERQPS] = 368; + xed_enc_iclass2group[XED_ICLASS_VPGATHERQD] = 368; + xed_enc_iclass2group[XED_ICLASS_VPERMQ] = 369; + xed_enc_iclass2group[XED_ICLASS_VPERMPD] = 369; + xed_enc_iclass2group[XED_ICLASS_VPERMD] = 370; + xed_enc_iclass2group[XED_ICLASS_VPERMPS] = 370; + xed_enc_iclass2group[XED_ICLASS_VPBROADCASTB] = 371; + xed_enc_iclass2group[XED_ICLASS_VPBROADCASTW] = 372; + xed_enc_iclass2group[XED_ICLASS_VPBROADCASTD] = 373; + xed_enc_iclass2group[XED_ICLASS_VPBROADCASTQ] = 374; + xed_enc_iclass2group[XED_ICLASS_PDEP] = 375; + xed_enc_iclass2group[XED_ICLASS_PEXT] = 375; + xed_enc_iclass2group[XED_ICLASS_ANDN] = 375; + xed_enc_iclass2group[XED_ICLASS_MULX] = 375; + xed_enc_iclass2group[XED_ICLASS_BLSR] = 376; + xed_enc_iclass2group[XED_ICLASS_BLSMSK] = 376; + xed_enc_iclass2group[XED_ICLASS_BLSI] = 376; + xed_enc_iclass2group[XED_ICLASS_BZHI] = 377; + xed_enc_iclass2group[XED_ICLASS_BEXTR] = 377; + xed_enc_iclass2group[XED_ICLASS_SHLX] = 377; + xed_enc_iclass2group[XED_ICLASS_SARX] = 377; + xed_enc_iclass2group[XED_ICLASS_SHRX] = 377; + xed_enc_iclass2group[XED_ICLASS_RORX] = 378; + xed_enc_iclass2group[XED_ICLASS_XBEGIN] = 379; + xed_enc_iclass2group[XED_ICLASS_ADCX] = 380; + xed_enc_iclass2group[XED_ICLASS_ADOX] = 380; + xed_enc_iclass2group[XED_ICLASS_VCVTNE2PS2BF16] = 381; + xed_enc_iclass2group[XED_ICLASS_VDPBF16PS] = 381; + xed_enc_iclass2group[XED_ICLASS_VBLENDMPS] = 381; + xed_enc_iclass2group[XED_ICLASS_VPANDD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPANDND] = 381; + xed_enc_iclass2group[XED_ICLASS_VPBLENDMD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPERMI2D] = 381; + xed_enc_iclass2group[XED_ICLASS_VPERMI2PS] = 381; + xed_enc_iclass2group[XED_ICLASS_VPERMT2D] = 381; + xed_enc_iclass2group[XED_ICLASS_VPERMT2PS] = 381; + xed_enc_iclass2group[XED_ICLASS_VPORD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPROLVD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPRORVD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPXORD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPSHLDVD] = 381; + xed_enc_iclass2group[XED_ICLASS_VPSHRDVD] = 381; + xed_enc_iclass2group[XED_ICLASS_VCVTNEPS2BF16] = 382; + xed_enc_iclass2group[XED_ICLASS_VEXP2PD] = 383; + xed_enc_iclass2group[XED_ICLASS_VRCP28PD] = 383; + xed_enc_iclass2group[XED_ICLASS_VRSQRT28PD] = 383; + xed_enc_iclass2group[XED_ICLASS_VEXP2PS] = 384; + xed_enc_iclass2group[XED_ICLASS_VRCP28PS] = 384; + xed_enc_iclass2group[XED_ICLASS_VRSQRT28PS] = 384; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF0DPD] = 385; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF1DPD] = 385; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF0DPD] = 385; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF1DPD] = 385; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF0DPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF0QPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF1DPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF1QPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF0DPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF0QPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF1DPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF1QPS] = 386; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF0QPD] = 387; + xed_enc_iclass2group[XED_ICLASS_VGATHERPF1QPD] = 387; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF0QPD] = 387; + xed_enc_iclass2group[XED_ICLASS_VSCATTERPF1QPD] = 387; + xed_enc_iclass2group[XED_ICLASS_VRCP28SD] = 388; + xed_enc_iclass2group[XED_ICLASS_VRSQRT28SD] = 388; + xed_enc_iclass2group[XED_ICLASS_VGETEXPSD] = 388; + xed_enc_iclass2group[XED_ICLASS_VRCP28SS] = 389; + xed_enc_iclass2group[XED_ICLASS_VRSQRT28SS] = 389; + xed_enc_iclass2group[XED_ICLASS_VGETEXPSS] = 389; + xed_enc_iclass2group[XED_ICLASS_V4FMADDPS] = 390; + xed_enc_iclass2group[XED_ICLASS_V4FNMADDPS] = 390; + xed_enc_iclass2group[XED_ICLASS_VP4DPWSSD] = 390; + xed_enc_iclass2group[XED_ICLASS_VP4DPWSSDS] = 390; + xed_enc_iclass2group[XED_ICLASS_V4FMADDSS] = 391; + xed_enc_iclass2group[XED_ICLASS_V4FNMADDSS] = 391; + xed_enc_iclass2group[XED_ICLASS_VPOPCNTD] = 392; + xed_enc_iclass2group[XED_ICLASS_VRCP14PS] = 392; + xed_enc_iclass2group[XED_ICLASS_VRSQRT14PS] = 392; + xed_enc_iclass2group[XED_ICLASS_VPCONFLICTD] = 392; + xed_enc_iclass2group[XED_ICLASS_VPLZCNTD] = 392; + xed_enc_iclass2group[XED_ICLASS_VPOPCNTQ] = 393; + xed_enc_iclass2group[XED_ICLASS_VPABSQ] = 393; + xed_enc_iclass2group[XED_ICLASS_VRCP14PD] = 393; + xed_enc_iclass2group[XED_ICLASS_VRSQRT14PD] = 393; + xed_enc_iclass2group[XED_ICLASS_VPCONFLICTQ] = 393; + xed_enc_iclass2group[XED_ICLASS_VPLZCNTQ] = 393; + xed_enc_iclass2group[XED_ICLASS_VALIGND] = 394; + xed_enc_iclass2group[XED_ICLASS_VPTERNLOGD] = 394; + xed_enc_iclass2group[XED_ICLASS_VPSHLDD] = 394; + xed_enc_iclass2group[XED_ICLASS_VPSHRDD] = 394; + xed_enc_iclass2group[XED_ICLASS_VALIGNQ] = 395; + xed_enc_iclass2group[XED_ICLASS_VPTERNLOGQ] = 395; + xed_enc_iclass2group[XED_ICLASS_VPSHLDQ] = 395; + xed_enc_iclass2group[XED_ICLASS_VPSHRDQ] = 395; + xed_enc_iclass2group[XED_ICLASS_VBLENDMPD] = 396; + xed_enc_iclass2group[XED_ICLASS_VPANDNQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPANDQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPBLENDMQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPERMI2PD] = 396; + xed_enc_iclass2group[XED_ICLASS_VPERMI2Q] = 396; + xed_enc_iclass2group[XED_ICLASS_VPERMT2PD] = 396; + xed_enc_iclass2group[XED_ICLASS_VPERMT2Q] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMAXSQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMAXUQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMINSQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMINUQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPORQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPROLVQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPRORVQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPSRAVQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPXORQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMULLQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMADD52HUQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMADD52LUQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPMULTISHIFTQB] = 396; + xed_enc_iclass2group[XED_ICLASS_VPSHLDVQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VPSHRDVQ] = 396; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTF32X4] = 397; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTI32X4] = 397; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTF64X4] = 398; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTI64X4] = 398; + xed_enc_iclass2group[XED_ICLASS_VCOMPRESSPD] = 399; + xed_enc_iclass2group[XED_ICLASS_VPCOMPRESSQ] = 399; + xed_enc_iclass2group[XED_ICLASS_VCOMPRESSPS] = 400; + xed_enc_iclass2group[XED_ICLASS_VPCOMPRESSD] = 400; + xed_enc_iclass2group[XED_ICLASS_VCVTPD2UDQ] = 401; + xed_enc_iclass2group[XED_ICLASS_VCVTQQ2PS] = 401; + xed_enc_iclass2group[XED_ICLASS_VCVTUQQ2PS] = 401; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2UDQ] = 402; + xed_enc_iclass2group[XED_ICLASS_VCVTUDQ2PS] = 402; + xed_enc_iclass2group[XED_ICLASS_VCVTSD2USI] = 403; + xed_enc_iclass2group[XED_ICLASS_VCVTSS2USI] = 404; + xed_enc_iclass2group[XED_ICLASS_VCVTTPD2UDQ] = 405; + xed_enc_iclass2group[XED_ICLASS_VCVTTPS2UDQ] = 406; + xed_enc_iclass2group[XED_ICLASS_VGETEXPPS] = 406; + xed_enc_iclass2group[XED_ICLASS_VCVTTSD2USI] = 407; + xed_enc_iclass2group[XED_ICLASS_VCVTTSS2USI] = 408; + xed_enc_iclass2group[XED_ICLASS_VCVTUDQ2PD] = 409; + xed_enc_iclass2group[XED_ICLASS_VCVTUSI2SD] = 410; + xed_enc_iclass2group[XED_ICLASS_VCVTUSI2SS] = 411; + xed_enc_iclass2group[XED_ICLASS_VEXPANDPD] = 412; + xed_enc_iclass2group[XED_ICLASS_VPEXPANDQ] = 412; + xed_enc_iclass2group[XED_ICLASS_VEXPANDPS] = 413; + xed_enc_iclass2group[XED_ICLASS_VPEXPANDD] = 413; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTF32X4] = 414; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTI32X4] = 414; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTF64X4] = 415; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTI64X4] = 415; + xed_enc_iclass2group[XED_ICLASS_VFIXUPIMMPD] = 416; + xed_enc_iclass2group[XED_ICLASS_VRANGEPD] = 416; + xed_enc_iclass2group[XED_ICLASS_VFIXUPIMMPS] = 417; + xed_enc_iclass2group[XED_ICLASS_VRANGEPS] = 417; + xed_enc_iclass2group[XED_ICLASS_VFIXUPIMMSD] = 418; + xed_enc_iclass2group[XED_ICLASS_VGETMANTSD] = 418; + xed_enc_iclass2group[XED_ICLASS_VRNDSCALESD] = 418; + xed_enc_iclass2group[XED_ICLASS_VRANGESD] = 418; + xed_enc_iclass2group[XED_ICLASS_VREDUCESD] = 418; + xed_enc_iclass2group[XED_ICLASS_VFIXUPIMMSS] = 419; + xed_enc_iclass2group[XED_ICLASS_VGETMANTSS] = 419; + xed_enc_iclass2group[XED_ICLASS_VRNDSCALESS] = 419; + xed_enc_iclass2group[XED_ICLASS_VRANGESS] = 419; + xed_enc_iclass2group[XED_ICLASS_VREDUCESS] = 419; + xed_enc_iclass2group[XED_ICLASS_VGETEXPPD] = 420; + xed_enc_iclass2group[XED_ICLASS_VCVTTPD2QQ] = 420; + xed_enc_iclass2group[XED_ICLASS_VCVTTPD2UQQ] = 420; + xed_enc_iclass2group[XED_ICLASS_VGETMANTPD] = 421; + xed_enc_iclass2group[XED_ICLASS_VRNDSCALEPD] = 421; + xed_enc_iclass2group[XED_ICLASS_VREDUCEPD] = 421; + xed_enc_iclass2group[XED_ICLASS_VGETMANTPS] = 422; + xed_enc_iclass2group[XED_ICLASS_VRNDSCALEPS] = 422; + xed_enc_iclass2group[XED_ICLASS_VREDUCEPS] = 422; + xed_enc_iclass2group[XED_ICLASS_VINSERTF32X4] = 423; + xed_enc_iclass2group[XED_ICLASS_VINSERTI32X4] = 423; + xed_enc_iclass2group[XED_ICLASS_VINSERTF64X4] = 424; + xed_enc_iclass2group[XED_ICLASS_VINSERTI64X4] = 424; + xed_enc_iclass2group[XED_ICLASS_VMOVDQA32] = 425; + xed_enc_iclass2group[XED_ICLASS_VMOVDQU32] = 425; + xed_enc_iclass2group[XED_ICLASS_VMOVDQA64] = 426; + xed_enc_iclass2group[XED_ICLASS_VMOVDQU64] = 426; + xed_enc_iclass2group[XED_ICLASS_VPCMPD] = 427; + xed_enc_iclass2group[XED_ICLASS_VPCMPUD] = 427; + xed_enc_iclass2group[XED_ICLASS_VPCMPQ] = 428; + xed_enc_iclass2group[XED_ICLASS_VPCMPUQ] = 428; + xed_enc_iclass2group[XED_ICLASS_VPMOVDB] = 429; + xed_enc_iclass2group[XED_ICLASS_VPMOVSDB] = 429; + xed_enc_iclass2group[XED_ICLASS_VPMOVUSDB] = 429; + xed_enc_iclass2group[XED_ICLASS_VPMOVDW] = 430; + xed_enc_iclass2group[XED_ICLASS_VPMOVSDW] = 430; + xed_enc_iclass2group[XED_ICLASS_VPMOVUSDW] = 430; + xed_enc_iclass2group[XED_ICLASS_VPMOVQB] = 431; + xed_enc_iclass2group[XED_ICLASS_VPMOVSQB] = 431; + xed_enc_iclass2group[XED_ICLASS_VPMOVUSQB] = 431; + xed_enc_iclass2group[XED_ICLASS_VPMOVQD] = 432; + xed_enc_iclass2group[XED_ICLASS_VPMOVSQD] = 432; + xed_enc_iclass2group[XED_ICLASS_VPMOVUSQD] = 432; + xed_enc_iclass2group[XED_ICLASS_VPMOVQW] = 433; + xed_enc_iclass2group[XED_ICLASS_VPMOVSQW] = 433; + xed_enc_iclass2group[XED_ICLASS_VPMOVUSQW] = 433; + xed_enc_iclass2group[XED_ICLASS_VPROLD] = 434; + xed_enc_iclass2group[XED_ICLASS_VPRORD] = 434; + xed_enc_iclass2group[XED_ICLASS_VPROLQ] = 435; + xed_enc_iclass2group[XED_ICLASS_VPRORQ] = 435; + xed_enc_iclass2group[XED_ICLASS_VPSCATTERDD] = 436; + xed_enc_iclass2group[XED_ICLASS_VSCATTERDPS] = 436; + xed_enc_iclass2group[XED_ICLASS_VPSCATTERDQ] = 437; + xed_enc_iclass2group[XED_ICLASS_VSCATTERDPD] = 437; + xed_enc_iclass2group[XED_ICLASS_VPSCATTERQD] = 438; + xed_enc_iclass2group[XED_ICLASS_VSCATTERQPS] = 438; + xed_enc_iclass2group[XED_ICLASS_VPSCATTERQQ] = 439; + xed_enc_iclass2group[XED_ICLASS_VSCATTERQPD] = 439; + xed_enc_iclass2group[XED_ICLASS_VPSRAQ] = 440; + xed_enc_iclass2group[XED_ICLASS_VPTESTMD] = 441; + xed_enc_iclass2group[XED_ICLASS_VPTESTNMD] = 441; + xed_enc_iclass2group[XED_ICLASS_VPTESTMQ] = 442; + xed_enc_iclass2group[XED_ICLASS_VPTESTNMQ] = 442; + xed_enc_iclass2group[XED_ICLASS_VRCP14SD] = 443; + xed_enc_iclass2group[XED_ICLASS_VRSQRT14SD] = 443; + xed_enc_iclass2group[XED_ICLASS_VRCP14SS] = 444; + xed_enc_iclass2group[XED_ICLASS_VRSQRT14SS] = 444; + xed_enc_iclass2group[XED_ICLASS_VSCALEFPD] = 445; + xed_enc_iclass2group[XED_ICLASS_VSCALEFPS] = 446; + xed_enc_iclass2group[XED_ICLASS_VFCMADDCPH] = 446; + xed_enc_iclass2group[XED_ICLASS_VFCMULCPH] = 446; + xed_enc_iclass2group[XED_ICLASS_VFMADDCPH] = 446; + xed_enc_iclass2group[XED_ICLASS_VFMULCPH] = 446; + xed_enc_iclass2group[XED_ICLASS_VSCALEFSD] = 447; + xed_enc_iclass2group[XED_ICLASS_VSCALEFSS] = 448; + xed_enc_iclass2group[XED_ICLASS_VSHUFF32X4] = 449; + xed_enc_iclass2group[XED_ICLASS_VSHUFI32X4] = 449; + xed_enc_iclass2group[XED_ICLASS_VSHUFF64X2] = 450; + xed_enc_iclass2group[XED_ICLASS_VSHUFI64X2] = 450; + xed_enc_iclass2group[XED_ICLASS_KANDNW] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDW] = 451; + xed_enc_iclass2group[XED_ICLASS_KORW] = 451; + xed_enc_iclass2group[XED_ICLASS_KUNPCKBW] = 451; + xed_enc_iclass2group[XED_ICLASS_KXNORW] = 451; + xed_enc_iclass2group[XED_ICLASS_KXORW] = 451; + xed_enc_iclass2group[XED_ICLASS_KADDB] = 451; + xed_enc_iclass2group[XED_ICLASS_KADDD] = 451; + xed_enc_iclass2group[XED_ICLASS_KADDQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KADDW] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDB] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDD] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDNB] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDND] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDNQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KANDQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KORB] = 451; + xed_enc_iclass2group[XED_ICLASS_KORD] = 451; + xed_enc_iclass2group[XED_ICLASS_KORQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KUNPCKDQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KUNPCKWD] = 451; + xed_enc_iclass2group[XED_ICLASS_KXNORB] = 451; + xed_enc_iclass2group[XED_ICLASS_KXNORD] = 451; + xed_enc_iclass2group[XED_ICLASS_KXNORQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KXORB] = 451; + xed_enc_iclass2group[XED_ICLASS_KXORD] = 451; + xed_enc_iclass2group[XED_ICLASS_KXORQ] = 451; + xed_enc_iclass2group[XED_ICLASS_KMOVW] = 452; + xed_enc_iclass2group[XED_ICLASS_KNOTW] = 453; + xed_enc_iclass2group[XED_ICLASS_KORTESTW] = 453; + xed_enc_iclass2group[XED_ICLASS_KNOTB] = 453; + xed_enc_iclass2group[XED_ICLASS_KNOTD] = 453; + xed_enc_iclass2group[XED_ICLASS_KNOTQ] = 453; + xed_enc_iclass2group[XED_ICLASS_KORTESTB] = 453; + xed_enc_iclass2group[XED_ICLASS_KORTESTD] = 453; + xed_enc_iclass2group[XED_ICLASS_KORTESTQ] = 453; + xed_enc_iclass2group[XED_ICLASS_KTESTB] = 453; + xed_enc_iclass2group[XED_ICLASS_KTESTD] = 453; + xed_enc_iclass2group[XED_ICLASS_KTESTQ] = 453; + xed_enc_iclass2group[XED_ICLASS_KTESTW] = 453; + xed_enc_iclass2group[XED_ICLASS_KSHIFTLW] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTRW] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTLB] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTLD] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTLQ] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTRB] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTRD] = 454; + xed_enc_iclass2group[XED_ICLASS_KSHIFTRQ] = 454; + xed_enc_iclass2group[XED_ICLASS_VPBROADCASTMB2Q] = 455; + xed_enc_iclass2group[XED_ICLASS_VPBROADCASTMW2D] = 455; + xed_enc_iclass2group[XED_ICLASS_VPMOVM2B] = 455; + xed_enc_iclass2group[XED_ICLASS_VPMOVM2D] = 455; + xed_enc_iclass2group[XED_ICLASS_VPMOVM2Q] = 455; + xed_enc_iclass2group[XED_ICLASS_VPMOVM2W] = 455; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTF32X2] = 456; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTF32X8] = 457; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTI32X8] = 457; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTF64X2] = 458; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTI64X2] = 458; + xed_enc_iclass2group[XED_ICLASS_VBROADCASTI32X2] = 459; + xed_enc_iclass2group[XED_ICLASS_VCVTPD2QQ] = 460; + xed_enc_iclass2group[XED_ICLASS_VCVTPD2UQQ] = 460; + xed_enc_iclass2group[XED_ICLASS_VCVTQQ2PD] = 460; + xed_enc_iclass2group[XED_ICLASS_VCVTUQQ2PD] = 460; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2QQ] = 461; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2UQQ] = 461; + xed_enc_iclass2group[XED_ICLASS_VCVTTPS2QQ] = 462; + xed_enc_iclass2group[XED_ICLASS_VCVTTPS2UQQ] = 462; + xed_enc_iclass2group[XED_ICLASS_VDBPSADBW] = 463; + xed_enc_iclass2group[XED_ICLASS_VPSHLDW] = 463; + xed_enc_iclass2group[XED_ICLASS_VPSHRDW] = 463; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTF32X8] = 464; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTI32X8] = 464; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTF64X2] = 465; + xed_enc_iclass2group[XED_ICLASS_VEXTRACTI64X2] = 465; + xed_enc_iclass2group[XED_ICLASS_VFPCLASSPD] = 466; + xed_enc_iclass2group[XED_ICLASS_VFPCLASSPS] = 467; + xed_enc_iclass2group[XED_ICLASS_VFPCLASSSD] = 468; + xed_enc_iclass2group[XED_ICLASS_VFPCLASSSS] = 469; + xed_enc_iclass2group[XED_ICLASS_VINSERTF32X8] = 470; + xed_enc_iclass2group[XED_ICLASS_VINSERTI32X8] = 470; + xed_enc_iclass2group[XED_ICLASS_VINSERTF64X2] = 471; + xed_enc_iclass2group[XED_ICLASS_VINSERTI64X2] = 471; + xed_enc_iclass2group[XED_ICLASS_VMOVDQU16] = 472; + xed_enc_iclass2group[XED_ICLASS_VMOVDQU8] = 473; + xed_enc_iclass2group[XED_ICLASS_VPBLENDMB] = 474; + xed_enc_iclass2group[XED_ICLASS_VPERMB] = 474; + xed_enc_iclass2group[XED_ICLASS_VPERMI2B] = 474; + xed_enc_iclass2group[XED_ICLASS_VPERMT2B] = 474; + xed_enc_iclass2group[XED_ICLASS_VPBLENDMW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPERMI2W] = 475; + xed_enc_iclass2group[XED_ICLASS_VPERMT2W] = 475; + xed_enc_iclass2group[XED_ICLASS_VPERMW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPSLLVW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPSRAVW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPSRLVW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPSHLDVW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPSHRDVW] = 475; + xed_enc_iclass2group[XED_ICLASS_VPCMPB] = 476; + xed_enc_iclass2group[XED_ICLASS_VPCMPUB] = 476; + xed_enc_iclass2group[XED_ICLASS_VPCMPUW] = 477; + xed_enc_iclass2group[XED_ICLASS_VPCMPW] = 477; + xed_enc_iclass2group[XED_ICLASS_VPEXTRW_C5] = 478; + xed_enc_iclass2group[XED_ICLASS_VPMOVB2M] = 479; + xed_enc_iclass2group[XED_ICLASS_VPMOVD2M] = 479; + xed_enc_iclass2group[XED_ICLASS_VPMOVQ2M] = 479; + xed_enc_iclass2group[XED_ICLASS_VPMOVW2M] = 479; + xed_enc_iclass2group[XED_ICLASS_VPMOVSWB] = 480; + xed_enc_iclass2group[XED_ICLASS_VPMOVUSWB] = 480; + xed_enc_iclass2group[XED_ICLASS_VPMOVWB] = 480; + xed_enc_iclass2group[XED_ICLASS_VPTESTMB] = 481; + xed_enc_iclass2group[XED_ICLASS_VPTESTNMB] = 481; + xed_enc_iclass2group[XED_ICLASS_VPSHUFBITQMB] = 481; + xed_enc_iclass2group[XED_ICLASS_VPTESTMW] = 482; + xed_enc_iclass2group[XED_ICLASS_VPTESTNMW] = 482; + xed_enc_iclass2group[XED_ICLASS_KMOVB] = 483; + xed_enc_iclass2group[XED_ICLASS_KMOVD] = 484; + xed_enc_iclass2group[XED_ICLASS_KMOVQ] = 485; + xed_enc_iclass2group[XED_ICLASS_VPOPCNTB] = 486; + xed_enc_iclass2group[XED_ICLASS_VPOPCNTW] = 487; + xed_enc_iclass2group[XED_ICLASS_VPCOMPRESSB] = 488; + xed_enc_iclass2group[XED_ICLASS_VPCOMPRESSW] = 489; + xed_enc_iclass2group[XED_ICLASS_VPEXPANDB] = 490; + xed_enc_iclass2group[XED_ICLASS_VPEXPANDW] = 491; + xed_enc_iclass2group[XED_ICLASS_VP2INTERSECTD] = 492; + xed_enc_iclass2group[XED_ICLASS_VP2INTERSECTQ] = 493; + xed_enc_iclass2group[XED_ICLASS_AESDEC128KL] = 494; + xed_enc_iclass2group[XED_ICLASS_AESENC128KL] = 494; + xed_enc_iclass2group[XED_ICLASS_AESDEC256KL] = 495; + xed_enc_iclass2group[XED_ICLASS_AESENC256KL] = 495; + xed_enc_iclass2group[XED_ICLASS_AESDECWIDE128KL] = 496; + xed_enc_iclass2group[XED_ICLASS_AESENCWIDE128KL] = 496; + xed_enc_iclass2group[XED_ICLASS_AESDECWIDE256KL] = 497; + xed_enc_iclass2group[XED_ICLASS_AESENCWIDE256KL] = 497; + xed_enc_iclass2group[XED_ICLASS_ENCODEKEY128] = 498; + xed_enc_iclass2group[XED_ICLASS_ENCODEKEY256] = 498; + xed_enc_iclass2group[XED_ICLASS_SENDUIPI] = 499; + xed_enc_iclass2group[XED_ICLASS_LDTILECFG] = 500; + xed_enc_iclass2group[XED_ICLASS_STTILECFG] = 500; + xed_enc_iclass2group[XED_ICLASS_TDPBF16PS] = 501; + xed_enc_iclass2group[XED_ICLASS_TDPBSSD] = 501; + xed_enc_iclass2group[XED_ICLASS_TDPBSUD] = 501; + xed_enc_iclass2group[XED_ICLASS_TDPBUSD] = 501; + xed_enc_iclass2group[XED_ICLASS_TDPBUUD] = 501; + xed_enc_iclass2group[XED_ICLASS_TILELOADD] = 502; + xed_enc_iclass2group[XED_ICLASS_TILELOADDT1] = 502; + xed_enc_iclass2group[XED_ICLASS_TILERELEASE] = 503; + xed_enc_iclass2group[XED_ICLASS_TILESTORED] = 504; + xed_enc_iclass2group[XED_ICLASS_TILEZERO] = 505; + xed_enc_iclass2group[XED_ICLASS_ENQCMD] = 506; + xed_enc_iclass2group[XED_ICLASS_ENQCMDS] = 506; + xed_enc_iclass2group[XED_ICLASS_VADDPH] = 507; + xed_enc_iclass2group[XED_ICLASS_VDIVPH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMADD132PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMADD213PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMADD231PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB132PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB213PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMADDSUB231PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMSUB132PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMSUB213PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMSUB231PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD132PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD213PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFMSUBADD231PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFNMADD132PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFNMADD213PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFNMADD231PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB132PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB213PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB231PH] = 507; + xed_enc_iclass2group[XED_ICLASS_VMULPH] = 507; + xed_enc_iclass2group[XED_ICLASS_VSCALEFPH] = 507; + xed_enc_iclass2group[XED_ICLASS_VSUBPH] = 507; + xed_enc_iclass2group[XED_ICLASS_VADDSH] = 508; + xed_enc_iclass2group[XED_ICLASS_VDIVSH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFMADD132SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFMADD213SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFMADD231SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFMSUB132SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFMSUB213SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFMSUB231SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFNMADD132SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFNMADD213SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFNMADD231SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB132SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB213SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VFNMSUB231SH] = 508; + xed_enc_iclass2group[XED_ICLASS_VMULSH] = 508; + xed_enc_iclass2group[XED_ICLASS_VSCALEFSH] = 508; + xed_enc_iclass2group[XED_ICLASS_VSQRTSH] = 508; + xed_enc_iclass2group[XED_ICLASS_VSUBSH] = 508; + xed_enc_iclass2group[XED_ICLASS_VCMPPH] = 509; + xed_enc_iclass2group[XED_ICLASS_VCMPSH] = 510; + xed_enc_iclass2group[XED_ICLASS_VCOMISH] = 511; + xed_enc_iclass2group[XED_ICLASS_VUCOMISH] = 511; + xed_enc_iclass2group[XED_ICLASS_VCVTDQ2PH] = 512; + xed_enc_iclass2group[XED_ICLASS_VCVTPS2PHX] = 512; + xed_enc_iclass2group[XED_ICLASS_VCVTUDQ2PH] = 512; + xed_enc_iclass2group[XED_ICLASS_VCVTPD2PH] = 513; + xed_enc_iclass2group[XED_ICLASS_VCVTQQ2PH] = 513; + xed_enc_iclass2group[XED_ICLASS_VCVTUQQ2PH] = 513; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2DQ] = 514; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2UDQ] = 514; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2PD] = 515; + xed_enc_iclass2group[XED_ICLASS_VCVTTPH2QQ] = 515; + xed_enc_iclass2group[XED_ICLASS_VCVTTPH2UQQ] = 515; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2PSX] = 516; + xed_enc_iclass2group[XED_ICLASS_VCVTTPH2DQ] = 516; + xed_enc_iclass2group[XED_ICLASS_VCVTTPH2UDQ] = 516; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2QQ] = 517; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2UQQ] = 517; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2UW] = 518; + xed_enc_iclass2group[XED_ICLASS_VCVTPH2W] = 518; + xed_enc_iclass2group[XED_ICLASS_VCVTUW2PH] = 518; + xed_enc_iclass2group[XED_ICLASS_VCVTW2PH] = 518; + xed_enc_iclass2group[XED_ICLASS_VSQRTPH] = 518; + xed_enc_iclass2group[XED_ICLASS_VCVTSD2SH] = 519; + xed_enc_iclass2group[XED_ICLASS_VCVTSH2SD] = 520; + xed_enc_iclass2group[XED_ICLASS_VCVTSH2SS] = 520; + xed_enc_iclass2group[XED_ICLASS_VGETEXPSH] = 520; + xed_enc_iclass2group[XED_ICLASS_VMAXSH] = 520; + xed_enc_iclass2group[XED_ICLASS_VMINSH] = 520; + xed_enc_iclass2group[XED_ICLASS_VCVTSH2SI] = 521; + xed_enc_iclass2group[XED_ICLASS_VCVTSH2USI] = 521; + xed_enc_iclass2group[XED_ICLASS_VCVTSI2SH] = 522; + xed_enc_iclass2group[XED_ICLASS_VCVTUSI2SH] = 522; + xed_enc_iclass2group[XED_ICLASS_VCVTSS2SH] = 523; + xed_enc_iclass2group[XED_ICLASS_VFCMADDCSH] = 523; + xed_enc_iclass2group[XED_ICLASS_VFCMULCSH] = 523; + xed_enc_iclass2group[XED_ICLASS_VFMADDCSH] = 523; + xed_enc_iclass2group[XED_ICLASS_VFMULCSH] = 523; + xed_enc_iclass2group[XED_ICLASS_VCVTTPH2UW] = 524; + xed_enc_iclass2group[XED_ICLASS_VCVTTPH2W] = 524; + xed_enc_iclass2group[XED_ICLASS_VGETEXPPH] = 524; + xed_enc_iclass2group[XED_ICLASS_VCVTTSH2SI] = 525; + xed_enc_iclass2group[XED_ICLASS_VCVTTSH2USI] = 525; + xed_enc_iclass2group[XED_ICLASS_VFPCLASSPH] = 526; + xed_enc_iclass2group[XED_ICLASS_VFPCLASSSH] = 527; + xed_enc_iclass2group[XED_ICLASS_VGETMANTPH] = 528; + xed_enc_iclass2group[XED_ICLASS_VREDUCEPH] = 528; + xed_enc_iclass2group[XED_ICLASS_VRNDSCALEPH] = 528; + xed_enc_iclass2group[XED_ICLASS_VGETMANTSH] = 529; + xed_enc_iclass2group[XED_ICLASS_VREDUCESH] = 529; + xed_enc_iclass2group[XED_ICLASS_VRNDSCALESH] = 529; + xed_enc_iclass2group[XED_ICLASS_VMAXPH] = 530; + xed_enc_iclass2group[XED_ICLASS_VMINPH] = 530; + xed_enc_iclass2group[XED_ICLASS_VMOVSH] = 531; + xed_enc_iclass2group[XED_ICLASS_VMOVW] = 532; + xed_enc_iclass2group[XED_ICLASS_VRCPPH] = 533; + xed_enc_iclass2group[XED_ICLASS_VRSQRTPH] = 533; + xed_enc_iclass2group[XED_ICLASS_VRCPSH] = 534; + xed_enc_iclass2group[XED_ICLASS_VRSQRTSH] = 534; + xed_enc_iclass2index_in_group[XED_ICLASS_FADD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FDIV] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FDIVR] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_FMUL] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_FSUB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_FSUBR] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_FCOMP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FCOM] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FLD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FSTP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FADDP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FDIVP] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FDIVRP] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_FMULP] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_FSTPNCE] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_FSUBP] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_FSUBRP] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDENV] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FNSTENV] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDCW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FNSTCW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FXCH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CLAC] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CLC] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CLD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CLGI] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_CLI] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_CLTS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_CLZERO] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_CMC] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_CPUID] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_EMMS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_ENCLS] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_ENCLU] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_ENCLV] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_ENDBR32] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_ENDBR64] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_F2XM1] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_FABS] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_FCHS] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_FCOMPP] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_FCOS] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_FDECSTP] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_FDISI8087_NOP] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_FEMMS] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_FENI8087_NOP] = 23; + xed_enc_iclass2index_in_group[XED_ICLASS_FINCSTP] = 24; + xed_enc_iclass2index_in_group[XED_ICLASS_FLD1] = 25; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDL2E] = 26; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDL2T] = 27; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDLG2] = 28; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDLN2] = 29; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDPI] = 30; + xed_enc_iclass2index_in_group[XED_ICLASS_FLDZ] = 31; + xed_enc_iclass2index_in_group[XED_ICLASS_FNCLEX] = 32; + xed_enc_iclass2index_in_group[XED_ICLASS_FNINIT] = 33; + xed_enc_iclass2index_in_group[XED_ICLASS_FNOP] = 34; + xed_enc_iclass2index_in_group[XED_ICLASS_FPATAN] = 35; + xed_enc_iclass2index_in_group[XED_ICLASS_FPREM] = 36; + xed_enc_iclass2index_in_group[XED_ICLASS_FPREM1] = 37; + xed_enc_iclass2index_in_group[XED_ICLASS_FPTAN] = 38; + xed_enc_iclass2index_in_group[XED_ICLASS_FRNDINT] = 39; + xed_enc_iclass2index_in_group[XED_ICLASS_FSCALE] = 40; + xed_enc_iclass2index_in_group[XED_ICLASS_FSETPM287_NOP] = 41; + xed_enc_iclass2index_in_group[XED_ICLASS_FSIN] = 42; + xed_enc_iclass2index_in_group[XED_ICLASS_FSINCOS] = 43; + xed_enc_iclass2index_in_group[XED_ICLASS_FSQRT] = 44; + xed_enc_iclass2index_in_group[XED_ICLASS_FTST] = 45; + xed_enc_iclass2index_in_group[XED_ICLASS_FUCOMPP] = 46; + xed_enc_iclass2index_in_group[XED_ICLASS_FWAIT] = 47; + xed_enc_iclass2index_in_group[XED_ICLASS_FXAM] = 48; + xed_enc_iclass2index_in_group[XED_ICLASS_FXTRACT] = 49; + xed_enc_iclass2index_in_group[XED_ICLASS_FYL2X] = 50; + xed_enc_iclass2index_in_group[XED_ICLASS_FYL2XP1] = 51; + xed_enc_iclass2index_in_group[XED_ICLASS_GETSEC] = 52; + xed_enc_iclass2index_in_group[XED_ICLASS_HLT] = 53; + xed_enc_iclass2index_in_group[XED_ICLASS_INSB] = 54; + xed_enc_iclass2index_in_group[XED_ICLASS_INT1] = 55; + xed_enc_iclass2index_in_group[XED_ICLASS_INT3] = 56; + xed_enc_iclass2index_in_group[XED_ICLASS_INVD] = 57; + xed_enc_iclass2index_in_group[XED_ICLASS_LAHF] = 58; + xed_enc_iclass2index_in_group[XED_ICLASS_LFENCE] = 59; + xed_enc_iclass2index_in_group[XED_ICLASS_MCOMMIT] = 60; + xed_enc_iclass2index_in_group[XED_ICLASS_MFENCE] = 61; + xed_enc_iclass2index_in_group[XED_ICLASS_MWAIT] = 62; + xed_enc_iclass2index_in_group[XED_ICLASS_MWAITX] = 63; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP2] = 64; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP3] = 65; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP4] = 66; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP5] = 67; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP6] = 68; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP7] = 69; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP8] = 70; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP9] = 71; + xed_enc_iclass2index_in_group[XED_ICLASS_PAUSE] = 72; + xed_enc_iclass2index_in_group[XED_ICLASS_RDMSR] = 73; + xed_enc_iclass2index_in_group[XED_ICLASS_RDPKRU] = 74; + xed_enc_iclass2index_in_group[XED_ICLASS_RDPMC] = 75; + xed_enc_iclass2index_in_group[XED_ICLASS_RDPRU] = 76; + xed_enc_iclass2index_in_group[XED_ICLASS_RDTSC] = 77; + xed_enc_iclass2index_in_group[XED_ICLASS_RDTSCP] = 78; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_SCASB] = 79; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_SCASB] = 80; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XCRYPTCBC] = 81; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XCRYPTCFB] = 82; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XCRYPTCTR] = 83; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XCRYPTECB] = 84; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XCRYPTOFB] = 85; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XSHA1] = 86; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XSHA256] = 87; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_XSTORE] = 88; + xed_enc_iclass2index_in_group[XED_ICLASS_RSM] = 89; + xed_enc_iclass2index_in_group[XED_ICLASS_SAHF] = 90; + xed_enc_iclass2index_in_group[XED_ICLASS_SAVEPREVSSP] = 91; + xed_enc_iclass2index_in_group[XED_ICLASS_SCASB] = 92; + xed_enc_iclass2index_in_group[XED_ICLASS_SERIALIZE] = 93; + xed_enc_iclass2index_in_group[XED_ICLASS_SETSSBSY] = 94; + xed_enc_iclass2index_in_group[XED_ICLASS_SFENCE] = 95; + xed_enc_iclass2index_in_group[XED_ICLASS_STAC] = 96; + xed_enc_iclass2index_in_group[XED_ICLASS_STC] = 97; + xed_enc_iclass2index_in_group[XED_ICLASS_STD] = 98; + xed_enc_iclass2index_in_group[XED_ICLASS_STGI] = 99; + xed_enc_iclass2index_in_group[XED_ICLASS_STI] = 100; + xed_enc_iclass2index_in_group[XED_ICLASS_STOSB] = 101; + xed_enc_iclass2index_in_group[XED_ICLASS_TLBSYNC] = 102; + xed_enc_iclass2index_in_group[XED_ICLASS_UD2] = 103; + xed_enc_iclass2index_in_group[XED_ICLASS_VMCALL] = 104; + xed_enc_iclass2index_in_group[XED_ICLASS_VMFUNC] = 105; + xed_enc_iclass2index_in_group[XED_ICLASS_VMLAUNCH] = 106; + xed_enc_iclass2index_in_group[XED_ICLASS_VMMCALL] = 107; + xed_enc_iclass2index_in_group[XED_ICLASS_VMRESUME] = 108; + xed_enc_iclass2index_in_group[XED_ICLASS_VMSAVE] = 109; + xed_enc_iclass2index_in_group[XED_ICLASS_VMXOFF] = 110; + xed_enc_iclass2index_in_group[XED_ICLASS_WBNOINVD] = 111; + xed_enc_iclass2index_in_group[XED_ICLASS_WRMSR] = 112; + xed_enc_iclass2index_in_group[XED_ICLASS_WRPKRU] = 113; + xed_enc_iclass2index_in_group[XED_ICLASS_XEND] = 114; + xed_enc_iclass2index_in_group[XED_ICLASS_XGETBV] = 115; + xed_enc_iclass2index_in_group[XED_ICLASS_XRESLDTRK] = 116; + xed_enc_iclass2index_in_group[XED_ICLASS_XSETBV] = 117; + xed_enc_iclass2index_in_group[XED_ICLASS_XSTORE] = 118; + xed_enc_iclass2index_in_group[XED_ICLASS_XSUSLDTRK] = 119; + xed_enc_iclass2index_in_group[XED_ICLASS_XTEST] = 120; + xed_enc_iclass2index_in_group[XED_ICLASS_FIADD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FICOM] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FICOMP] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_FIDIV] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_FIDIVR] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_FIMUL] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_FISUB] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_FISUBR] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVBE] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVE] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVNB] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVNBE] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVNE] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVNU] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_FCMOVU] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_FCOMI] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_FCOMIP] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_FUCOM] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_FUCOMI] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_FUCOMIP] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_FUCOMP] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_FILD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FISTP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FISTTP] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FIST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FNSAVE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FRSTOR] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FNSTSW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FFREE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FFREEP] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FBLD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FBSTP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADC_LOCK] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADD_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_OR_LOCK] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_SBB_LOCK] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_SUB_LOCK] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_ADC] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CMP] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_SBB] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_SUB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_OR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AND_LOCK] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XOR_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AND] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XOR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_POP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RCL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RCR] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_ROL] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_ROR] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_SAR] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_SHR] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_SHL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_TEST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_DEC_LOCK] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INC_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_NEG_LOCK] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_NOT_LOCK] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_DIV] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_IDIV] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MUL] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_NEG] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_NOT] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_IMUL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_DEC] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INC] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CALL_NEAR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JMP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CALL_FAR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JMP_FAR] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PUSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SLDT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SMSW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_STR] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_LLDT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LMSW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LTR] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VERR] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VERW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_LGDT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LIDT] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SGDT] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_SIDT] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_BT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BTC] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BTR] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_BTS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_BTC_LOCK] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BTR_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BTS_LOCK] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VMCLEAR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CLRSSBSY] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RSTORSSP] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMPTRLD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VMPTRST] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VMXON] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPXCHG8B] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPXCHG8B_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPXCHG16B] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPXCHG16B_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MOV] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PSLLD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PSLLQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PSLLW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PSRAD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PSRAW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_PSRLD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_PSRLQ] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_PSRLW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PSLLDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PSRLDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FXRSTOR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_FXRSTOR64] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_FXSAVE] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_FXSAVE64] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_LDMXCSR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_STMXCSR] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CLFLUSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCHNTA] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCHT0] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCHT1] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCHT2] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCH_EXCLUSIVE] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_NOP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MONITOR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MONITORX] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CLDEMOTE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INVLPG] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCHWT1] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CDQE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CLUI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CQO] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_IRETQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_SCASQ] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_SCASQ] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_SCASQ] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_SEAMCALL] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_SEAMOPS] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_SEAMRET] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_STOSQ] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_STUI] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_SWAPGS] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSRET] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSRET64] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_TESTUI] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_UIRET] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_LOADIWKEY] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVHLPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVLHPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVHPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVLPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AAA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AAS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_DAA] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_DAS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_INTO] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_SALC] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSRET_AMD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_POPA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_POPAD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_POPFD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PUSHA] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PUSHAD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_PUSHFD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_BOUND] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ARPL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSXD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_INSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_STOSB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_INSW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_STOSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_STOSW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CBW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CWD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CWDE] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_INSW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_IRET] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_IRETD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_POPF] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PUSHF] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_SCASD] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_SCASW] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_SCASD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_SCASW] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_SCASD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_SCASW] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_STOSD] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_STOSW] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_INSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_LODSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_OUTSB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LODSB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_OUTSB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_CMPSB] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_CMPSB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_XLAT] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_LODSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_LODSW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_OUTSW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPSW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LODSD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_LODSW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_OUTSW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_CMPSD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_CMPSW] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_CMPSD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_CMPSW] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_OUTSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_OUTSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JBE] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_JL] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_JLE] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_JNB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_JNBE] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_JNL] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_JNLE] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_JNO] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_JNP] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_JNS] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_JNZ] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_JO] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_JP] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_JS] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_JZ] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_XCHG] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LEA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_POPFQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PUSHFQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_MOVSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_MOVSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_MOVSW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_MOVSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LODSQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_REPE_CMPSQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_REPNE_CMPSQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_STOSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_LODSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RET_NEAR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LDS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LES] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_ENTER] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LEAVE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RET_FAR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_HRESET] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INT] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_XABORT] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_AAD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AAM] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LOOPE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LOOPNE] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LOOP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JCXZ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JECXZ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_JRCXZ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_IN] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_OUT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LAR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LSL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSCALL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVAPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVUPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTDQ2PS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_GF2P8MULB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA1MSG1] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA1MSG2] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA1NEXTE] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA256MSG1] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA256MSG2] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA256RNDS2] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_UNPCKHPS] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_UNPCKLPS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADDSUBPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTTPS2DQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_HADDPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_HSUBPS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSHDUP] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSLDUP] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVAPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVUPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVHPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVLPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AESDEC] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESDECLAST] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AESENC] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_AESENCLAST] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_AESIMC] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_BLENDVPD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_BLENDVPS] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_PACKUSDW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PBLENDVB] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPEQQ] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPGTQ] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_PHMINPOSUW] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_PMAXSB] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_PMAXSD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_PMAXUD] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_PMAXUW] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_PMINSB] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_PMINSD] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_PMINUD] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_PMINUW] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULDQ] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULLD] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_PTEST] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKHQDQ] = 23; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKLQDQ] = 24; + xed_enc_iclass2index_in_group[XED_ICLASS_UNPCKHPD] = 25; + xed_enc_iclass2index_in_group[XED_ICLASS_UNPCKLPD] = 26; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSD_XMM] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTDQ2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVDDUP] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MOV_CR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOV_DR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PCONFIG] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSENTER] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSEXIT] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_TDCALL] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVBE] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVL] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVLE] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNBE] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNL] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNLE] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNO] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNP] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNS] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVNZ] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVO] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVP] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVS] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_CMOVZ] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_POPCNT] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_TZCNT] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVMSKPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADDPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_DIVPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MAXPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_MINPS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_MULPS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_RCPPS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_RSQRTPS] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_SQRTPS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_SUBPS] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_ANDNPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ANDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_ORPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_XORPS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_ADDSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTSS2SD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_DIVSS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_MAXSS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_MINSS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_MULSS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_RCPSS] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_RSQRTSS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_SQRTSS] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_SUBSS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVMSKPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADDSUBPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPD2PS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTTPD2DQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_DIVPD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_HADDPD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_HSUBPD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_MAXPD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_MINPD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_MULPD] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_SQRTPD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_SUBPD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_ANDNPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ANDPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_ORPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_XORPD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_ADDSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTSD2SS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_DIVSD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_MAXSD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_MINSD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_MULSD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_SQRTSD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_SUBSD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKLBW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKLDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKLWD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PABSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PABSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PABSW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PACKSSDW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PACKSSWB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_PACKUSWB] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDB] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDQ] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDSB] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDSW] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDUSB] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDUSW] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_PADDW] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_PAND] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_PANDN] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_PAVGB] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_PAVGW] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPEQB] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPEQD] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPEQW] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPGTB] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPGTD] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPGTW] = 23; + xed_enc_iclass2index_in_group[XED_ICLASS_PHADDD] = 24; + xed_enc_iclass2index_in_group[XED_ICLASS_PHADDSW] = 25; + xed_enc_iclass2index_in_group[XED_ICLASS_PHADDW] = 26; + xed_enc_iclass2index_in_group[XED_ICLASS_PHSUBD] = 27; + xed_enc_iclass2index_in_group[XED_ICLASS_PHSUBSW] = 28; + xed_enc_iclass2index_in_group[XED_ICLASS_PHSUBW] = 29; + xed_enc_iclass2index_in_group[XED_ICLASS_PMADDUBSW] = 30; + xed_enc_iclass2index_in_group[XED_ICLASS_PMADDWD] = 31; + xed_enc_iclass2index_in_group[XED_ICLASS_PMAXSW] = 32; + xed_enc_iclass2index_in_group[XED_ICLASS_PMAXUB] = 33; + xed_enc_iclass2index_in_group[XED_ICLASS_PMINSW] = 34; + xed_enc_iclass2index_in_group[XED_ICLASS_PMINUB] = 35; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULHRSW] = 36; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULHUW] = 37; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULHW] = 38; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULLW] = 39; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULUDQ] = 40; + xed_enc_iclass2index_in_group[XED_ICLASS_POR] = 41; + xed_enc_iclass2index_in_group[XED_ICLASS_PSADBW] = 42; + xed_enc_iclass2index_in_group[XED_ICLASS_PSHUFB] = 43; + xed_enc_iclass2index_in_group[XED_ICLASS_PSIGNB] = 44; + xed_enc_iclass2index_in_group[XED_ICLASS_PSIGND] = 45; + xed_enc_iclass2index_in_group[XED_ICLASS_PSIGNW] = 46; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBB] = 47; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBD] = 48; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBQ] = 49; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBSB] = 50; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBSW] = 51; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBUSB] = 52; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBUSW] = 53; + xed_enc_iclass2index_in_group[XED_ICLASS_PSUBW] = 54; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKHBW] = 55; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKHDQ] = 56; + xed_enc_iclass2index_in_group[XED_ICLASS_PUNPCKHWD] = 57; + xed_enc_iclass2index_in_group[XED_ICLASS_PXOR] = 58; + xed_enc_iclass2index_in_group[XED_ICLASS_PSHUFW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESKEYGENASSIST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BLENDPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BLENDPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_DPPD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_DPPS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_MPSADBW] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_PBLENDW] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_PCLMULQDQ] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PSHUFD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_PSHUFHW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PSHUFLW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SETB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SETBE] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SETL] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_SETLE] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNBE] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNL] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNLE] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNO] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNP] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNS] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_SETNZ] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_SETO] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_SETP] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_SETS] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_SETZ] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPXCHG_LOCK] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XADD_LOCK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPXCHG] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XADD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LFS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LGS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LSS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVSX] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVZX] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SHUFPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PINSRW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PEXTRW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ROUNDPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SHUFPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CMPSD_XMM] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVMSKB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVQ2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVDQ2Q] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPD2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MASKMOVQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MASKMOVDQU] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LDDQU] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_WBINVD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_UD0] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_UD1] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPI2PS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPS2PI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTTPS2PI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_COMISS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_UCOMISS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTSI2SD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTSI2SS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTSS2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTTSS2SI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPI2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPD2PI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTTPD2PI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_COMISD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_UCOMISD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTSD2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTTSD2SI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPS2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CVTPS2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVDQU] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMREAD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMWRITE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVDQA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SHLD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SHRD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BSF] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BSR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BSWAP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PALIGNR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CRC32] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTDQA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_EXTRACTPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PEXTRD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_INSERTPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ROUNDSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PEXTRB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PEXTRW_SSE4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PEXTRQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PINSRB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PINSRD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PINSRQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ROUNDPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ROUNDSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVSXBW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVSXDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVSXWD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVZXBW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVZXDQ] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVZXWD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVSXBD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVSXWQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVZXBD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVZXWQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVSXBQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PMOVZXBQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPESTRI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPESTRM] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPISTRI] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPESTRI64] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPESTRM64] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPISTRI64] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PCMPISTRM] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XRSTOR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XRSTOR64] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_XRSTORS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_XRSTORS64] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVE] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVE64] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVEC] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVEC64] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVEOPT] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVEOPT64] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVES] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_XSAVES64] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVBE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INVEPT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INVPCID] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_INVVPID] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCHW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PREFETCH_RESERVED] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_REP_MONTMUL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PAVGUSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PF2ID] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PF2IW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PFACC] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_PFADD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_PFCMPEQ] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_PFCMPGE] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_PFCMPGT] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_PFMAX] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_PFMIN] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_PFMUL] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_PFNACC] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_PFPNACC] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_PFRCP] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_PFRCPIT1] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_PFRCPIT2] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_PFRSQIT1] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_PFRSQRT] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_PFSUB] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_PFSUBR] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_PI2FD] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_PI2FW] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_PMULHRW] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_PSWAPD] = 23; + xed_enc_iclass2index_in_group[XED_ICLASS_SYSCALL_AMD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMLOAD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMRUN] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SKINIT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INVLPGA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_EXTRQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INSERTQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVNTSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LZCNT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PSMASH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PVALIDATE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RMPADJUST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RMPUPDATE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INVLPGB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSDD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSDQH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSDQL] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSSDD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSSDQH] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSSDQL] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSSWD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSSWW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSWD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMACSWW] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMADCSSWD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMADCSWD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMOV] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPPERM] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROTB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROTD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROTQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROTW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMUB] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMUD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMUQ] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMUW] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFRCZPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFRCZPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFRCZSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFRCZSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHAB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHAD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHAQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHAW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLQ] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDBD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDBQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDBW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDDQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDUBD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDUBQ] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDUBW] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDUDQ] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDUWD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDUWQ] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDWD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDWQ] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHSUBBW] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHSUBDQ] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHSUBWD] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_BEXTR_XOP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BLCFILL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BLCI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BLCIC] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_BLCMSK] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_BLCS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_BLSFILL] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_BLSIC] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_T1MSKC] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_TZMSK] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_LLWPCB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_SLWPCB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_LWPINS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LWPVAL] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUBPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUBPS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADDPD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADDPS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBPD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBPS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADDPD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADDPS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUBPD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUBPS] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADDSS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUBSS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADDSD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUBSD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMIL2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMIL2PS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDMK] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDCL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDCN] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDCU] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDMOV] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDLDX] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BNDSTX] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_INCSSPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RDSSPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_TPAUSE] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_UMWAIT] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_INCSSPQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RDSSPQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_WRSSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_WRUSSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_WRSSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_WRUSSQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_RDRAND] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RDSEED] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_GF2P8AFFINEINVQB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_GF2P8AFFINEQB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SHA1RNDS4] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_CLFLUSHOPT] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_CLWB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_RDFSBASE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_RDGSBASE] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_WRFSBASE] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_WRGSBASE] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_RDPID] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_PTWRITE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVDIR64B] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MOVDIRI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_UMONITOR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VDIVPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD132PD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD213PD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD231PD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB132PD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB213PD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB231PD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB132PD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB213PD] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB231PD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD132PD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD213PD] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD231PD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD132PD] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD213PD] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD231PD] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB132PD] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB213PD] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB231PD] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_VMULPD] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_VSUBPD] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VDIVPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD132PS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD213PS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD231PS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB132PS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB213PS] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB231PS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB132PS] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB213PS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB231PS] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD132PS] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD213PS] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD231PS] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD132PS] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD213PS] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD231PS] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB132PS] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB213PS] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB231PS] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_VMULPS] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_VSUBPS] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSD2SS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VDIVSD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD132SD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD213SD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD231SD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB132SD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB213SD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB231SD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD132SD] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD213SD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD231SD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB132SD] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB213SD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB231SD] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VMULSD] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VSQRTSD] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VSUBSD] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VDIVSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD132SS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD213SS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD231SS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB132SS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB213SS] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB231SS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD132SS] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD213SS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD231SS] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB132SS] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB213SS] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB231SS] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VMULSS] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VSQRTSS] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VSUBSS] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDSUBPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDSUBPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VHADDPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VHADDPS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VHSUBPD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VHSUBPS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPAND] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPANDN] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDSW] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHADDW] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHSUBD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHSUBSW] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHSUBW] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPOR] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSIGNB] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSIGND] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSIGNW] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VPXOR] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VANDNPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VANDPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VORPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULDQ] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULUDQ] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLVQ] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLVQ] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBQ] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKHQDQ] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKLQDQ] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VUNPCKHPD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VUNPCKLPD] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VXORPD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VANDNPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VANDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VORPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPACKSSDW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPACKUSDW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPDPBUSD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPDPBUSDS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPDPWSSD] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPDPWSSDS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXSD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXUD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINSD] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINUD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULLD] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLVD] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRAVD] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLVD] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBD] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKHDQ] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKLDQ] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_VUNPCKHPS] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_VUNPCKLPS] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_VXORPS] = 23; + xed_enc_iclass2index_in_group[XED_ICLASS_VBLENDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBLENDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VDPPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VMPSADBW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDW] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VCMPPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCMPPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCMPSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCMPSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCOMISD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VUCOMISD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCOMISS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VUCOMISS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTDQ2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTDQ2PS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2DQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSQRTPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPD2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPD2PS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPD2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPS2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSD2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTSD2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSS2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTSS2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSI2SD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSI2SS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSS2SD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMAXSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMINSS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTF128] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTI128] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VDPPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VZEROALL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VZEROUPPER] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMILPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMILPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERM2F128] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERM2I128] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTF128] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTI128] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTF128] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTI128] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VLDDQU] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMASKMOVPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMASKMOVPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMASKMOVD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMASKMOVQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTEST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCPPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRTPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VTESTPD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VTESTPS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VMAXPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMINPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMAXPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMINPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMAXSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMINSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVAPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVUPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVAPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVUPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDDUP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQU] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVSHDUP] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVSLDUP] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPABSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPABSW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPABSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VAESIMC] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPHMINPOSUW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHUFD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHUFHW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHUFLW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPACKSSWB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPACKUSWB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDSW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDUSW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPAVGW] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMADDUBSW] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMADDWD] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXSW] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXUW] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINSW] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINUW] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULHRSW] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULHUW] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULHW] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULLW] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBSW] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBUSW] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBW] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKHWD] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKLWD] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRAW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRAD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGF2P8MULB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDSB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPADDUSB] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPAVGB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXSB] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXUB] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINSB] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINUB] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHUFB] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBB] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBSB] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSUBUSB] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKHBW] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPUNPCKLBW] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPEQB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPGTB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPEQW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPGTW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPEQD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPGTD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPEQQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPGTQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSADBW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVHLPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVLHPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPALIGNR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VROUNDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VROUNDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VROUNDSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VROUNDSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGF2P8AFFINEINVQB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGF2P8AFFINEQB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSHUFPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VSHUFPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCPSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRTSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSQRTPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVHPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVLPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVHPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVLPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVMSKPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVMSKPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVMSKB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSXBW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVZXBW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSXBD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVZXBD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSXBQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVZXBQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSXWD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVZXWD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSXWQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVZXWQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSXDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVZXDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXTRB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXTRW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXTRQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXTRD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPINSRB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPINSRW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPINSRD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPINSRQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPESTRI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPESTRM] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPISTRI] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPESTRI64] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPESTRM64] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPISTRI64] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VAESKEYGENASSIST] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPISTRM] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMASKMOVDQU] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VLDMXCSR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSTMXCSR] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VBLENDVPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBLENDVPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDVB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVNTDQA] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVNTDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVNTPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVNTPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VAESDEC] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VAESDECLAST] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VAESENC] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VAESENCLAST] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCLMULQDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2PS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2PH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPGATHERDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERDPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPGATHERDD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERQPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPGATHERQQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERQPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPGATHERQD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBROADCASTB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBROADCASTW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBROADCASTD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBROADCASTQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ANDN] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_MULX] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_PDEP] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_PEXT] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_BLSI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BLSMSK] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_BLSR] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_BEXTR] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_BZHI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SARX] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_SHLX] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_SHRX] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_RORX] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_XBEGIN] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADCX] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ADOX] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VBLENDMPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTNE2PS2BF16] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VDPBF16PS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPANDD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPANDND] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDMD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMI2D] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMI2PS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMT2D] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMT2PS] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPORD] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROLVD] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPRORVD] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLDVD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHRDVD] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VPXORD] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTNEPS2BF16] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXP2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP28PD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT28PD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXP2PS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP28PS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT28PS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF0DPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF1DPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF0DPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF1DPD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF0DPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF0QPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF1DPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF1QPS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF0DPS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF0QPS] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF1DPS] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF1QPS] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF0QPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGATHERPF1QPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF0QPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERPF1QPD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETEXPSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP28SD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT28SD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETEXPSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP28SS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT28SS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_V4FMADDPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_V4FNMADDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VP4DPWSSD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VP4DPWSSDS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_V4FMADDSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_V4FNMADDSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCONFLICTD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPLZCNTD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPOPCNTD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP14PS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT14PS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPABSQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCONFLICTQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPLZCNTQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPOPCNTQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP14PD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT14PD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VALIGND] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLDD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHRDD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTERNLOGD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VALIGNQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHRDQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTERNLOGQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VBLENDMPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPANDNQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPANDQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDMQ] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMI2PD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMI2Q] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMT2PD] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMT2Q] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMADD52HUQ] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMADD52LUQ] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXSQ] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMAXUQ] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINSQ] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMINUQ] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULLQ] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMULTISHIFTQB] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VPORQ] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROLVQ] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VPRORVQ] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLDVQ] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHRDVQ] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRAVQ] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_VPXORQ] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTF32X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTI32X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTF64X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTI64X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCOMPRESSPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMPRESSQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCOMPRESSPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMPRESSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPD2UDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTQQ2PS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUQQ2PS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2UDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUDQ2PS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSD2USI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSS2USI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPD2UDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPS2UDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETEXPPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTSD2USI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTSS2USI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUDQ2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUSI2SD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUSI2SS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXPANDPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXPANDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXPANDPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXPANDD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTF32X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTI32X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTF64X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTI64X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFIXUPIMMPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRANGEPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFIXUPIMMPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRANGEPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFIXUPIMMSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETMANTSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRANGESD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VREDUCESD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VRNDSCALESD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFIXUPIMMSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETMANTSS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRANGESS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VREDUCESS] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VRNDSCALESS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPD2QQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPD2UQQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETEXPPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETMANTPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VREDUCEPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRNDSCALEPD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETMANTPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VREDUCEPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRNDSCALEPS] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTF32X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTI32X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTF64X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTI64X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQA32] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQU32] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQA64] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQU64] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPUD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPUQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVDB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSDB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVUSDB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVDW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSDW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVUSDW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVQB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSQB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVUSQB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVQD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSQD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVUSQD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVQW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSQW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVUSQW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROLD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPRORD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPROLQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPRORQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSCATTERDD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERDPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSCATTERDQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERDPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSCATTERQD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERQPS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSCATTERQQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCATTERQPD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRAQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTMD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTNMD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTMQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTNMQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP14SD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT14SD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCP14SS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRT14SS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCALEFPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFCMADDCPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFCMULCPH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDCPH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMULCPH] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCALEFPS] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCALEFSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCALEFSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSHUFF32X4] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSHUFI32X4] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VSHUFF64X2] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VSHUFI64X2] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_KADDB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_KADDD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_KADDQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_KADDW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDNB] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDND] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDNQ] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDNW] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDQ] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_KANDW] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_KORB] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_KORD] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_KORQ] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_KORW] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_KUNPCKBW] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_KUNPCKDQ] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_KUNPCKWD] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_KXNORB] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_KXNORD] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_KXNORQ] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_KXNORW] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_KXORB] = 23; + xed_enc_iclass2index_in_group[XED_ICLASS_KXORD] = 24; + xed_enc_iclass2index_in_group[XED_ICLASS_KXORQ] = 25; + xed_enc_iclass2index_in_group[XED_ICLASS_KXORW] = 26; + xed_enc_iclass2index_in_group[XED_ICLASS_KMOVW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_KNOTB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_KNOTD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_KNOTQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_KNOTW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_KORTESTB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_KORTESTD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_KORTESTQ] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_KORTESTW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_KTESTB] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_KTESTD] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_KTESTQ] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_KTESTW] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTLB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTLD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTLQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTLW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTRB] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTRD] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTRQ] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_KSHIFTRW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBROADCASTMB2Q] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBROADCASTMW2D] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVM2B] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVM2D] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVM2Q] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVM2W] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTF32X2] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTF32X8] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTI32X8] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTF64X2] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTI64X2] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VBROADCASTI32X2] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPD2QQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPD2UQQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTQQ2PD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUQQ2PD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2QQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2UQQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPS2QQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPS2UQQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VDBPSADBW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLDW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHRDW] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTF32X8] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTI32X8] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTF64X2] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VEXTRACTI64X2] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFPCLASSPD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFPCLASSPS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFPCLASSSD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFPCLASSSS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTF32X8] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTI32X8] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTF64X2] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VINSERTI64X2] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQU16] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVDQU8] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDMB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMI2B] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMT2B] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPBLENDMW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMI2W] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMT2W] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPERMW] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHLDVW] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHRDVW] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSLLVW] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRAVW] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSRLVW] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPUB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPUW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCMPW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXTRW_C5] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVB2M] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVD2M] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVQ2M] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVW2M] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVSWB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVUSWB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPMOVWB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPSHUFBITQMB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTMB] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTNMB] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTMW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPTESTNMW] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_KMOVB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_KMOVD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_KMOVQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPOPCNTB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPOPCNTW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMPRESSB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPCOMPRESSW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXPANDB] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VPEXPANDW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VP2INTERSECTD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VP2INTERSECTQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESDEC128KL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESENC128KL] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AESDEC256KL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESENC256KL] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AESDECWIDE128KL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESENCWIDE128KL] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_AESDECWIDE256KL] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_AESENCWIDE256KL] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_ENCODEKEY128] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ENCODEKEY256] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_SENDUIPI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_LDTILECFG] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_STTILECFG] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_TDPBF16PS] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_TDPBSSD] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_TDPBSUD] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_TDPBUSD] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_TDPBUUD] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_TILELOADD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_TILELOADDT1] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_TILERELEASE] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_TILESTORED] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_TILEZERO] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ENQCMD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_ENQCMDS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VDIVPH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD132PH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD213PH] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD231PH] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB132PH] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB213PH] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDSUB231PH] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB132PH] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB213PH] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB231PH] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD132PH] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD213PH] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUBADD231PH] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD132PH] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD213PH] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD231PH] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB132PH] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB213PH] = 18; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB231PH] = 19; + xed_enc_iclass2index_in_group[XED_ICLASS_VMULPH] = 20; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCALEFPH] = 21; + xed_enc_iclass2index_in_group[XED_ICLASS_VSUBPH] = 22; + xed_enc_iclass2index_in_group[XED_ICLASS_VADDSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VDIVSH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD132SH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD213SH] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADD231SH] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB132SH] = 5; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB213SH] = 6; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMSUB231SH] = 7; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD132SH] = 8; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD213SH] = 9; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMADD231SH] = 10; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB132SH] = 11; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB213SH] = 12; + xed_enc_iclass2index_in_group[XED_ICLASS_VFNMSUB231SH] = 13; + xed_enc_iclass2index_in_group[XED_ICLASS_VMULSH] = 14; + xed_enc_iclass2index_in_group[XED_ICLASS_VSCALEFSH] = 15; + xed_enc_iclass2index_in_group[XED_ICLASS_VSQRTSH] = 16; + xed_enc_iclass2index_in_group[XED_ICLASS_VSUBSH] = 17; + xed_enc_iclass2index_in_group[XED_ICLASS_VCMPPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCMPSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCOMISH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VUCOMISH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTDQ2PH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPS2PHX] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUDQ2PH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPD2PH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTQQ2PH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUQQ2PH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2DQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2UDQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2PD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPH2QQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPH2UQQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2PSX] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPH2DQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPH2UDQ] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2QQ] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2UQQ] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2UW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTPH2W] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUW2PH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTW2PH] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VSQRTPH] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSD2SH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSH2SD] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSH2SS] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETEXPSH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VMAXSH] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VMINSH] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSH2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSH2USI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSI2SH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTUSI2SH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTSS2SH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFCMADDCSH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFCMULCSH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMADDCSH] = 3; + xed_enc_iclass2index_in_group[XED_ICLASS_VFMULCSH] = 4; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPH2UW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTPH2W] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETEXPPH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTSH2SI] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VCVTTSH2USI] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VFPCLASSPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VFPCLASSSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETMANTPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VREDUCEPH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRNDSCALEPH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VGETMANTSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VREDUCESH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRNDSCALESH] = 2; + xed_enc_iclass2index_in_group[XED_ICLASS_VMAXPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMINPH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VMOVW] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCPPH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRTPH] = 1; + xed_enc_iclass2index_in_group[XED_ICLASS_VRCPSH] = 0; + xed_enc_iclass2index_in_group[XED_ICLASS_VRSQRTSH] = 1; +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-order-init.c b/CodeVirtualizer/build/obj/xed-encoder-order-init.c new file mode 100644 index 0000000..7618de1 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-order-init.c @@ -0,0 +1,147 @@ +/// @file xed-encoder-order-init.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_init_encoder_order(void) +{ +xed_encode_order[0][0]=XED_OPERAND_REG0; +xed_encode_order[0][1]=XED_OPERAND_MEM0; +xed_encode_order_limit[0]=2; +xed_encode_order[1][0]=XED_OPERAND_REG0; +xed_encode_order[1][1]=XED_OPERAND_REG1; +xed_encode_order_limit[1]=2; +xed_encode_order[2][0]=XED_OPERAND_MEM0; +xed_encode_order[2][1]=XED_OPERAND_REG0; +xed_encode_order_limit[2]=2; +xed_encode_order[3][0]=XED_OPERAND_MEM0; +xed_encode_order_limit[3]=1; +xed_encode_order_limit[4]=0; +xed_encode_order[5][0]=XED_OPERAND_REG0; +xed_encode_order_limit[5]=1; +xed_encode_order[6][0]=XED_OPERAND_MEM0; +xed_encode_order[6][1]=XED_OPERAND_IMM0; +xed_encode_order_limit[6]=2; +xed_encode_order[7][0]=XED_OPERAND_REG0; +xed_encode_order[7][1]=XED_OPERAND_IMM0; +xed_encode_order_limit[7]=2; +xed_encode_order[8][0]=XED_OPERAND_REG0; +xed_encode_order[8][1]=XED_OPERAND_MEM0; +xed_encode_order[8][2]=XED_OPERAND_IMM0; +xed_encode_order_limit[8]=3; +xed_encode_order[9][0]=XED_OPERAND_REG0; +xed_encode_order[9][1]=XED_OPERAND_REG1; +xed_encode_order[9][2]=XED_OPERAND_IMM0; +xed_encode_order_limit[9]=3; +xed_encode_order[10][0]=XED_OPERAND_RELBR; +xed_encode_order_limit[10]=1; +xed_encode_order[11][0]=XED_OPERAND_PTR; +xed_encode_order[11][1]=XED_OPERAND_IMM0; +xed_encode_order_limit[11]=2; +xed_encode_order[12][0]=XED_OPERAND_IMM0; +xed_encode_order_limit[12]=1; +xed_encode_order[13][0]=XED_OPERAND_REG0; +xed_encode_order[13][1]=XED_OPERAND_AGEN; +xed_encode_order_limit[13]=2; +xed_encode_order[14][0]=XED_OPERAND_IMM0; +xed_encode_order[14][1]=XED_OPERAND_IMM1; +xed_encode_order_limit[14]=2; +xed_encode_order[15][0]=XED_OPERAND_IMM0; +xed_encode_order[15][1]=XED_OPERAND_REG0; +xed_encode_order_limit[15]=2; +xed_encode_order[16][0]=XED_OPERAND_MEM0; +xed_encode_order[16][1]=XED_OPERAND_REG0; +xed_encode_order[16][2]=XED_OPERAND_IMM0; +xed_encode_order_limit[16]=3; +xed_encode_order[17][0]=XED_OPERAND_MEM0; +xed_encode_order[17][1]=XED_OPERAND_REG0; +xed_encode_order[17][2]=XED_OPERAND_REG1; +xed_encode_order_limit[17]=3; +xed_encode_order[18][0]=XED_OPERAND_REG0; +xed_encode_order[18][1]=XED_OPERAND_REG1; +xed_encode_order[18][2]=XED_OPERAND_REG2; +xed_encode_order_limit[18]=3; +xed_encode_order[19][0]=XED_OPERAND_REG0; +xed_encode_order[19][1]=XED_OPERAND_IMM0; +xed_encode_order[19][2]=XED_OPERAND_IMM1; +xed_encode_order_limit[19]=3; +xed_encode_order[20][0]=XED_OPERAND_REG0; +xed_encode_order[20][1]=XED_OPERAND_REG1; +xed_encode_order[20][2]=XED_OPERAND_IMM0; +xed_encode_order[20][3]=XED_OPERAND_IMM1; +xed_encode_order_limit[20]=4; +xed_encode_order[21][0]=XED_OPERAND_REG0; +xed_encode_order[21][1]=XED_OPERAND_REG1; +xed_encode_order[21][2]=XED_OPERAND_MEM0; +xed_encode_order[21][3]=XED_OPERAND_REG2; +xed_encode_order_limit[21]=4; +xed_encode_order[22][0]=XED_OPERAND_REG0; +xed_encode_order[22][1]=XED_OPERAND_REG1; +xed_encode_order[22][2]=XED_OPERAND_REG2; +xed_encode_order[22][3]=XED_OPERAND_REG3; +xed_encode_order_limit[22]=4; +xed_encode_order[23][0]=XED_OPERAND_REG0; +xed_encode_order[23][1]=XED_OPERAND_REG1; +xed_encode_order[23][2]=XED_OPERAND_REG2; +xed_encode_order[23][3]=XED_OPERAND_MEM0; +xed_encode_order_limit[23]=4; +xed_encode_order[24][0]=XED_OPERAND_REG0; +xed_encode_order[24][1]=XED_OPERAND_MEM0; +xed_encode_order[24][2]=XED_OPERAND_REG1; +xed_encode_order_limit[24]=3; +xed_encode_order[25][0]=XED_OPERAND_REG0; +xed_encode_order[25][1]=XED_OPERAND_REG1; +xed_encode_order[25][2]=XED_OPERAND_MEM0; +xed_encode_order_limit[25]=3; +xed_encode_order[26][0]=XED_OPERAND_REG0; +xed_encode_order[26][1]=XED_OPERAND_REG1; +xed_encode_order[26][2]=XED_OPERAND_MEM0; +xed_encode_order[26][3]=XED_OPERAND_IMM0; +xed_encode_order_limit[26]=4; +xed_encode_order[27][0]=XED_OPERAND_REG0; +xed_encode_order[27][1]=XED_OPERAND_REG1; +xed_encode_order[27][2]=XED_OPERAND_REG2; +xed_encode_order[27][3]=XED_OPERAND_IMM0; +xed_encode_order_limit[27]=4; +xed_encode_order[28][0]=XED_OPERAND_REG0; +xed_encode_order[28][1]=XED_OPERAND_REG1; +xed_encode_order[28][2]=XED_OPERAND_MEM0; +xed_encode_order[28][3]=XED_OPERAND_REG2; +xed_encode_order[28][4]=XED_OPERAND_IMM0; +xed_encode_order_limit[28]=5; +xed_encode_order[29][0]=XED_OPERAND_REG0; +xed_encode_order[29][1]=XED_OPERAND_REG1; +xed_encode_order[29][2]=XED_OPERAND_REG2; +xed_encode_order[29][3]=XED_OPERAND_REG3; +xed_encode_order[29][4]=XED_OPERAND_IMM0; +xed_encode_order_limit[29]=5; +xed_encode_order[30][0]=XED_OPERAND_REG0; +xed_encode_order[30][1]=XED_OPERAND_REG1; +xed_encode_order[30][2]=XED_OPERAND_REG2; +xed_encode_order[30][3]=XED_OPERAND_MEM0; +xed_encode_order[30][4]=XED_OPERAND_IMM0; +xed_encode_order_limit[30]=5; +xed_encode_order[31][0]=XED_OPERAND_MEM0; +xed_encode_order[31][1]=XED_OPERAND_REG0; +xed_encode_order[31][2]=XED_OPERAND_REG1; +xed_encode_order[31][3]=XED_OPERAND_IMM0; +xed_encode_order_limit[31]=4; +} diff --git a/CodeVirtualizer/build/obj/xed-encoder-pattern-lu.c b/CodeVirtualizer/build/obj/xed-encoder-pattern-lu.c new file mode 100644 index 0000000..cb322bd --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-encoder-pattern-lu.c @@ -0,0 +1,1093 @@ +/// @file xed-encoder-pattern-lu.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-enc-patterns.h" +#include "xed-encoder-gen-defs.h" +#include "xed-encoder.h" +#include "xed-enc-groups.h" +const xed_ptrn_func_ptr_t xed_encode_fb_lu_table[XED_ENCODE_MAX_FB_PATTERNS] = { + xed_encode_instruction_fb_pattern_0, + xed_encode_instruction_fb_pattern_1, + xed_encode_instruction_fb_pattern_2, + xed_encode_instruction_fb_pattern_3, + xed_encode_instruction_fb_pattern_4, + xed_encode_instruction_fb_pattern_5, + xed_encode_instruction_fb_pattern_6, + xed_encode_instruction_fb_pattern_7, + xed_encode_instruction_fb_pattern_8, + xed_encode_instruction_fb_pattern_9, + xed_encode_instruction_fb_pattern_10, + xed_encode_instruction_fb_pattern_11, + xed_encode_instruction_fb_pattern_12, + xed_encode_instruction_fb_pattern_13, + xed_encode_instruction_fb_pattern_14, + xed_encode_instruction_fb_pattern_15, + xed_encode_instruction_fb_pattern_16, + xed_encode_instruction_fb_pattern_17, + xed_encode_instruction_fb_pattern_18, + xed_encode_instruction_fb_pattern_19, + xed_encode_instruction_fb_pattern_20, + xed_encode_instruction_fb_pattern_21, + xed_encode_instruction_fb_pattern_22, + xed_encode_instruction_fb_pattern_23, + xed_encode_instruction_fb_pattern_24, + xed_encode_instruction_fb_pattern_25, + xed_encode_instruction_fb_pattern_26, + xed_encode_instruction_fb_pattern_27, + xed_encode_instruction_fb_pattern_28, + xed_encode_instruction_fb_pattern_29, + xed_encode_instruction_fb_pattern_30, + xed_encode_instruction_fb_pattern_31, + xed_encode_instruction_fb_pattern_32, + xed_encode_instruction_fb_pattern_33, + xed_encode_instruction_fb_pattern_34, + xed_encode_instruction_fb_pattern_35, + xed_encode_instruction_fb_pattern_36, + xed_encode_instruction_fb_pattern_37, + xed_encode_instruction_fb_pattern_38, + xed_encode_instruction_fb_pattern_39, + xed_encode_instruction_fb_pattern_40, + xed_encode_instruction_fb_pattern_41, + xed_encode_instruction_fb_pattern_42, + xed_encode_instruction_fb_pattern_43, + xed_encode_instruction_fb_pattern_44, + xed_encode_instruction_fb_pattern_45, + xed_encode_instruction_fb_pattern_46, + xed_encode_instruction_fb_pattern_47, + xed_encode_instruction_fb_pattern_48, + xed_encode_instruction_fb_pattern_49, + xed_encode_instruction_fb_pattern_50, + xed_encode_instruction_fb_pattern_51, + xed_encode_instruction_fb_pattern_52, + xed_encode_instruction_fb_pattern_53, + xed_encode_instruction_fb_pattern_54, + xed_encode_instruction_fb_pattern_55, + xed_encode_instruction_fb_pattern_56, + xed_encode_instruction_fb_pattern_57, + xed_encode_instruction_fb_pattern_58, + xed_encode_instruction_fb_pattern_59, + xed_encode_instruction_fb_pattern_60, + xed_encode_instruction_fb_pattern_61, + xed_encode_instruction_fb_pattern_62, + xed_encode_instruction_fb_pattern_63, + xed_encode_instruction_fb_pattern_64, + xed_encode_instruction_fb_pattern_65, + xed_encode_instruction_fb_pattern_66, + xed_encode_instruction_fb_pattern_67, + xed_encode_instruction_fb_pattern_68, + xed_encode_instruction_fb_pattern_69, + xed_encode_instruction_fb_pattern_70, + xed_encode_instruction_fb_pattern_71, + xed_encode_instruction_fb_pattern_72, + xed_encode_instruction_fb_pattern_73, + xed_encode_instruction_fb_pattern_74, + xed_encode_instruction_fb_pattern_75, + xed_encode_instruction_fb_pattern_76, + xed_encode_instruction_fb_pattern_77, + xed_encode_instruction_fb_pattern_78, + xed_encode_instruction_fb_pattern_79, + xed_encode_instruction_fb_pattern_80, + xed_encode_instruction_fb_pattern_81, + xed_encode_instruction_fb_pattern_82, + xed_encode_instruction_fb_pattern_83, + xed_encode_instruction_fb_pattern_84, + xed_encode_instruction_fb_pattern_85, + xed_encode_instruction_fb_pattern_86, + xed_encode_instruction_fb_pattern_87, + xed_encode_instruction_fb_pattern_88, + xed_encode_instruction_fb_pattern_89, + xed_encode_instruction_fb_pattern_90, + xed_encode_instruction_fb_pattern_91, + xed_encode_instruction_fb_pattern_92, + xed_encode_instruction_fb_pattern_93, + xed_encode_instruction_fb_pattern_94, + xed_encode_instruction_fb_pattern_95, + xed_encode_instruction_fb_pattern_96, + xed_encode_instruction_fb_pattern_97, + xed_encode_instruction_fb_pattern_98, + xed_encode_instruction_fb_pattern_99, + xed_encode_instruction_fb_pattern_100, + xed_encode_instruction_fb_pattern_101, + xed_encode_instruction_fb_pattern_102, + xed_encode_instruction_fb_pattern_103, + xed_encode_instruction_fb_pattern_104, + xed_encode_instruction_fb_pattern_105, + xed_encode_instruction_fb_pattern_106, + xed_encode_instruction_fb_pattern_107, + xed_encode_instruction_fb_pattern_108, + xed_encode_instruction_fb_pattern_109, + xed_encode_instruction_fb_pattern_110, + xed_encode_instruction_fb_pattern_111, + xed_encode_instruction_fb_pattern_112, + xed_encode_instruction_fb_pattern_113, + xed_encode_instruction_fb_pattern_114, + xed_encode_instruction_fb_pattern_115, + xed_encode_instruction_fb_pattern_116, + xed_encode_instruction_fb_pattern_117, + xed_encode_instruction_fb_pattern_118, + xed_encode_instruction_fb_pattern_119, + xed_encode_instruction_fb_pattern_120, +}; + + + +const xed_ptrn_func_ptr_t xed_encode_emit_lu_table[XED_ENCODE_MAX_EMIT_PATTERNS] = { + xed_encode_instruction_emit_pattern_0, + xed_encode_instruction_emit_pattern_1, + xed_encode_instruction_emit_pattern_2, + xed_encode_instruction_emit_pattern_3, + xed_encode_instruction_emit_pattern_4, + xed_encode_instruction_emit_pattern_5, + xed_encode_instruction_emit_pattern_6, + xed_encode_instruction_emit_pattern_7, + xed_encode_instruction_emit_pattern_8, + xed_encode_instruction_emit_pattern_9, + xed_encode_instruction_emit_pattern_10, + xed_encode_instruction_emit_pattern_11, + xed_encode_instruction_emit_pattern_12, + xed_encode_instruction_emit_pattern_13, + xed_encode_instruction_emit_pattern_14, + xed_encode_instruction_emit_pattern_15, + xed_encode_instruction_emit_pattern_16, + xed_encode_instruction_emit_pattern_17, + xed_encode_instruction_emit_pattern_18, + xed_encode_instruction_emit_pattern_19, + xed_encode_instruction_emit_pattern_20, + xed_encode_instruction_emit_pattern_21, + xed_encode_instruction_emit_pattern_22, + xed_encode_instruction_emit_pattern_23, + xed_encode_instruction_emit_pattern_24, + xed_encode_instruction_emit_pattern_25, + xed_encode_instruction_emit_pattern_26, + xed_encode_instruction_emit_pattern_27, + xed_encode_instruction_emit_pattern_28, + xed_encode_instruction_emit_pattern_29, + xed_encode_instruction_emit_pattern_30, + xed_encode_instruction_emit_pattern_31, + xed_encode_instruction_emit_pattern_32, + xed_encode_instruction_emit_pattern_33, + xed_encode_instruction_emit_pattern_34, + xed_encode_instruction_emit_pattern_35, + xed_encode_instruction_emit_pattern_36, + xed_encode_instruction_emit_pattern_37, + xed_encode_instruction_emit_pattern_38, + xed_encode_instruction_emit_pattern_39, + xed_encode_instruction_emit_pattern_40, + xed_encode_instruction_emit_pattern_41, + xed_encode_instruction_emit_pattern_42, + xed_encode_instruction_emit_pattern_43, + xed_encode_instruction_emit_pattern_44, + xed_encode_instruction_emit_pattern_45, + xed_encode_instruction_emit_pattern_46, + xed_encode_instruction_emit_pattern_47, + xed_encode_instruction_emit_pattern_48, + xed_encode_instruction_emit_pattern_49, + xed_encode_instruction_emit_pattern_50, + xed_encode_instruction_emit_pattern_51, + xed_encode_instruction_emit_pattern_52, + xed_encode_instruction_emit_pattern_53, + xed_encode_instruction_emit_pattern_54, + xed_encode_instruction_emit_pattern_55, + xed_encode_instruction_emit_pattern_56, + xed_encode_instruction_emit_pattern_57, + xed_encode_instruction_emit_pattern_58, + xed_encode_instruction_emit_pattern_59, + xed_encode_instruction_emit_pattern_60, + xed_encode_instruction_emit_pattern_61, + xed_encode_instruction_emit_pattern_62, + xed_encode_instruction_emit_pattern_63, + xed_encode_instruction_emit_pattern_64, + xed_encode_instruction_emit_pattern_65, + xed_encode_instruction_emit_pattern_66, + xed_encode_instruction_emit_pattern_67, + xed_encode_instruction_emit_pattern_68, + xed_encode_instruction_emit_pattern_69, + xed_encode_instruction_emit_pattern_70, + xed_encode_instruction_emit_pattern_71, + xed_encode_instruction_emit_pattern_72, + xed_encode_instruction_emit_pattern_73, + xed_encode_instruction_emit_pattern_74, + xed_encode_instruction_emit_pattern_75, + xed_encode_instruction_emit_pattern_76, + xed_encode_instruction_emit_pattern_77, + xed_encode_instruction_emit_pattern_78, + xed_encode_instruction_emit_pattern_79, + xed_encode_instruction_emit_pattern_80, + xed_encode_instruction_emit_pattern_81, + xed_encode_instruction_emit_pattern_82, + xed_encode_instruction_emit_pattern_83, + xed_encode_instruction_emit_pattern_84, + xed_encode_instruction_emit_pattern_85, + xed_encode_instruction_emit_pattern_86, + xed_encode_instruction_emit_pattern_87, + xed_encode_instruction_emit_pattern_88, + xed_encode_instruction_emit_pattern_89, + xed_encode_instruction_emit_pattern_90, + xed_encode_instruction_emit_pattern_91, + xed_encode_instruction_emit_pattern_92, + xed_encode_instruction_emit_pattern_93, + xed_encode_instruction_emit_pattern_94, + xed_encode_instruction_emit_pattern_95, + xed_encode_instruction_emit_pattern_96, + xed_encode_instruction_emit_pattern_97, + xed_encode_instruction_emit_pattern_98, + xed_encode_instruction_emit_pattern_99, + xed_encode_instruction_emit_pattern_100, + xed_encode_instruction_emit_pattern_101, + xed_encode_instruction_emit_pattern_102, + xed_encode_instruction_emit_pattern_103, + xed_encode_instruction_emit_pattern_104, + xed_encode_instruction_emit_pattern_105, + xed_encode_instruction_emit_pattern_106, + xed_encode_instruction_emit_pattern_107, + xed_encode_instruction_emit_pattern_108, + xed_encode_instruction_emit_pattern_109, + xed_encode_instruction_emit_pattern_110, + xed_encode_instruction_emit_pattern_111, + xed_encode_instruction_emit_pattern_112, + xed_encode_instruction_emit_pattern_113, + xed_encode_instruction_emit_pattern_114, + xed_encode_instruction_emit_pattern_115, + xed_encode_instruction_emit_pattern_116, + xed_encode_instruction_emit_pattern_117, + xed_encode_instruction_emit_pattern_118, + xed_encode_instruction_emit_pattern_119, + xed_encode_instruction_emit_pattern_120, + xed_encode_instruction_emit_pattern_121, + xed_encode_instruction_emit_pattern_122, + xed_encode_instruction_emit_pattern_123, + xed_encode_instruction_emit_pattern_124, + xed_encode_instruction_emit_pattern_125, + xed_encode_instruction_emit_pattern_126, + xed_encode_instruction_emit_pattern_127, + xed_encode_instruction_emit_pattern_128, + xed_encode_instruction_emit_pattern_129, + xed_encode_instruction_emit_pattern_130, + xed_encode_instruction_emit_pattern_131, + xed_encode_instruction_emit_pattern_132, + xed_encode_instruction_emit_pattern_133, + xed_encode_instruction_emit_pattern_134, + xed_encode_instruction_emit_pattern_135, + xed_encode_instruction_emit_pattern_136, + xed_encode_instruction_emit_pattern_137, + xed_encode_instruction_emit_pattern_138, + xed_encode_instruction_emit_pattern_139, + xed_encode_instruction_emit_pattern_140, + xed_encode_instruction_emit_pattern_141, + xed_encode_instruction_emit_pattern_142, + xed_encode_instruction_emit_pattern_143, + xed_encode_instruction_emit_pattern_144, + xed_encode_instruction_emit_pattern_145, + xed_encode_instruction_emit_pattern_146, + xed_encode_instruction_emit_pattern_147, + xed_encode_instruction_emit_pattern_148, + xed_encode_instruction_emit_pattern_149, + xed_encode_instruction_emit_pattern_150, + xed_encode_instruction_emit_pattern_151, + xed_encode_instruction_emit_pattern_152, + xed_encode_instruction_emit_pattern_153, + xed_encode_instruction_emit_pattern_154, + xed_encode_instruction_emit_pattern_155, + xed_encode_instruction_emit_pattern_156, + xed_encode_instruction_emit_pattern_157, + xed_encode_instruction_emit_pattern_158, + xed_encode_instruction_emit_pattern_159, + xed_encode_instruction_emit_pattern_160, + xed_encode_instruction_emit_pattern_161, + xed_encode_instruction_emit_pattern_162, + xed_encode_instruction_emit_pattern_163, + xed_encode_instruction_emit_pattern_164, + xed_encode_instruction_emit_pattern_165, + xed_encode_instruction_emit_pattern_166, + xed_encode_instruction_emit_pattern_167, + xed_encode_instruction_emit_pattern_168, + xed_encode_instruction_emit_pattern_169, + xed_encode_instruction_emit_pattern_170, + xed_encode_instruction_emit_pattern_171, + xed_encode_instruction_emit_pattern_172, + xed_encode_instruction_emit_pattern_173, + xed_encode_instruction_emit_pattern_174, + xed_encode_instruction_emit_pattern_175, + xed_encode_instruction_emit_pattern_176, + xed_encode_instruction_emit_pattern_177, + xed_encode_instruction_emit_pattern_178, + xed_encode_instruction_emit_pattern_179, + xed_encode_instruction_emit_pattern_180, + xed_encode_instruction_emit_pattern_181, + xed_encode_instruction_emit_pattern_182, + xed_encode_instruction_emit_pattern_183, + xed_encode_instruction_emit_pattern_184, + xed_encode_instruction_emit_pattern_185, + xed_encode_instruction_emit_pattern_186, + xed_encode_instruction_emit_pattern_187, + xed_encode_instruction_emit_pattern_188, + xed_encode_instruction_emit_pattern_189, + xed_encode_instruction_emit_pattern_190, + xed_encode_instruction_emit_pattern_191, + xed_encode_instruction_emit_pattern_192, + xed_encode_instruction_emit_pattern_193, + xed_encode_instruction_emit_pattern_194, + xed_encode_instruction_emit_pattern_195, + xed_encode_instruction_emit_pattern_196, + xed_encode_instruction_emit_pattern_197, + xed_encode_instruction_emit_pattern_198, +}; + + + +const xed_uint8_t xed_encode_fb_values_table[XED_ENCODE_FB_VALUES_TABLE_SIZE] = { + 0,3,0,1,3,1,3,3,3,2,4,3,4,3,5,6,3,6,3,7, + 0,4,1,4,1,4,0,0,4,0,0,6,1,6,1,6,0,0,6,0, + 3,2,0,3,4,0,3,4,1,3,4,4,3,4,5,3,5,0,3,5, + 1,3,5,2,3,5,3,3,5,4,3,5,5,3,6,0,3,6,1,3, + 6,2,3,6,4,3,6,5,3,6,6,3,6,7,3,7,1,3,7,2, + 3,7,3,3,7,4,3,7,5,3,7,6,3,7,7,3,4,2,3,3, + 1,1,0,1,2,0,2,1,5,0,5,1,7,0,7,0,7,0,0,1, + 0,1,1,1,3,0,2,0,3,1,2,0,3,0,0,3,1,0,3,0, + 4,0,3,1,4,0,3,0,6,0,3,1,6,0,3,1,3,0,3,1, + 7,0,0,0,0,0,0,1,0,0,3,2,3,3,7,3,0,3,7,3, + 1,3,7,3,4,3,7,3,5,3,7,3,6,3,7,3,7,0,3,7, + 3,2,0,3,7,3,3,0,3,1,3,1,3,0,0,0,1,3,0,0, + 0,2,3,0,0,0,3,3,0,0,0,4,3,0,1,0,0,3,0,1, + 0,1,3,0,7,0,3,0,5,0,3,2,1,3,1,0,0,3,1,0, + 1,3,0,0,1,3,0,2,0,0,3,0,2,0,1,0,5,0,0,0, + 4,0,1,0,5,0,1,3,0,3,0,3,2,3,0,3,3,3,0,3, + 4,3,0,3,5,3,0,3,3,4,3,3,6,3,0,7,0,2,3,7, + 2,7,3,7,2,6,3,0,7,0,6,3,0,7,0,7,8,0,0,3, + 8,3,0,0,3,8,1,0,3,8,3,1,0,3,8,0,0,7,1,3, + 8,3,0,0,7,1,3,9,0,0,3,9,3,0,0,3,9,1,0,3, + 9,3,1,0,3,9,0,0,7,1,3,9,3,0,0,7,1,3,10,0, + 7,1,3,10,3,0,7,1,3,9,2,0,3,9,3,2,0,3,9,3, + 0,3,9,3,3,0,3,9,4,0,3,9,3,4,0,3,9,5,0,3, + 9,3,5,0,3,9,6,0,3,9,3,6,0,3,9,7,0,3,9,3, + 7,0,3,9,3,1,0,7,1,3,10,0,0,3,10,3,0,0,3,10, + 1,0,3,10,3,1,0,3,3,0,1,1,3,1,1,1,3,3,1,1, + 1,1,3,7,3,3,1,3,7,3,2,3,5,3,1,1,3,1,3,1, + 3,5,3,2,0,6,0,0,0,6,0,1,3,0,1,0,2,3,0,1, + 0,3,3,0,2,0,7,3,0,1,0,7,3,0,4,3,1,0,0,0, + 3,0,0,0,0,0,1,3,1,1,2,1,1,3,1,1,2,1,1,1, + 2,0,1,3,0,0,2,1,1,3,0,0,2,1,0,0,2,1,3,2, + 1,0,1,3,1,2,2,1,1,3,1,2,2,0,1,1,2,2,0,1, + 3,0,3,2,1,1,3,0,3,2,0,1,0,3,2,0,1,3,1,1, + 2,0,1,1,3,1,1,2,0,0,1,3,0,0,2,0,1,1,3,0, + 0,2,0,1,0,0,2,0,0,1,3,1,2,2,0,0,1,3,0,3, + 2,0,1,1,7,1,1,1,3,1,7,1,1,0,1,0,3,1,1,7, + 1,0,2,0,1,1,0,3,1,1,7,1,0,2,0,0,1,0,1,1, + 7,1,0,2,0,1,0,7,1,1,1,3,0,7,1,1,0,1,0,3, + 0,0,7,1,0,2,0,1,1,0,3,0,0,7,1,0,2,0,0,1, + 0,0,0,7,1,0,2,0,1,3,7,1,1,1,3,3,7,1,1,0, + 1,3,0,3,7,1,0,2,1,1,3,0,3,7,1,0,2,1,0,3, + 7,1,0,2,0,1,3,0,0,7,1,0,2,1,1,3,0,0,7,1, + 0,2,1,0,0,7,1,0,2,1,2,7,1,1,1,3,2,7,1,1, + 0,1,3,1,2,7,1,0,2,1,1,3,1,2,7,1,0,2,1,1, + 2,7,1,0,2,0,1,3,1,1,7,1,0,2,1,1,3,1,1,7, + 1,0,2,1,1,1,7,1,0,2,0,1,3,0,1,7,1,0,2,1, + 1,3,0,1,7,1,0,2,1,0,1,7,1,0,2,1,0,2,7,1, + 1,1,3,0,2,7,1,1,1,1,2,7,1,1,1,3,1,2,7,1, + 1,0,1,0,3,2,7,1,0,2,0,0,1,0,3,0,0,2,7,1, + 0,2,0,1,1,0,3,2,7,1,0,2,0,1,1,0,3,0,0,2, + 7,1,0,2,0,0,1,0,2,7,1,0,2,0,0,1,0,0,0,2, + 7,1,0,2,0,0,1,0,3,0,1,2,7,1,0,2,0,1,1,0, + 3,0,1,2,7,1,0,2,0,0,1,0,0,1,2,7,1,0,2,0, + 1,0,3,7,1,1,1,3,0,3,7,1,1,1,1,3,7,1,1,1, + 3,1,3,7,1,1,0,1,0,3,3,7,1,0,2,0,0,1,0,3, + 0,0,3,7,1,0,2,0,1,1,0,3,3,7,1,0,2,0,1,1, + 0,3,0,0,3,7,1,0,2,0,0,1,0,3,7,1,0,2,0,0, + 1,0,0,0,3,7,1,0,2,0,0,1,0,3,0,1,3,7,1,0, + 2,0,1,1,0,3,0,1,3,7,1,0,2,0,0,1,0,0,1,3, + 7,1,0,2,0,1,3,0,2,1,1,3,1,2,1,1,0,3,2,2, + 0,1,0,3,0,2,2,0,0,1,0,2,2,0,0,1,0,0,2,2, + 0,0,1,0,3,1,2,2,0,1,1,0,3,1,2,2,0,0,1,0, + 1,2,2,0,0,1,0,3,3,2,0,0,1,0,3,0,3,2,0,1, + 1,0,3,3,2,0,1,1,0,3,0,3,2,0,0,1,0,0,3,2, + 0,0,1,0,3,1,3,2,0,1,1,0,3,1,3,2,0,0,1,0, + 1,3,2,0,3,0,1,7,1,1,3,3,0,1,7,1,1,3,3,1, + 7,1,1,0,3,0,3,1,7,1,0,2,0,0,3,0,1,7,1,0, + 2,0,1,0,7,1,1,0,2,3,0,1,1,0,3,3,1,1,7,1, + 0,2,0,2,3,1,1,2,0,3,3,0,1,7,1,0,2,0,2,3, + 0,1,2,2,0,1,2,10,2,0,1,7,1,1,3,2,0,1,7,1, + 1,10,2,3,0,1,7,1,1,3,2,3,0,1,7,1,1,1,0,2, + 0,1,7,1,0,2,1,0,2,3,0,1,7,1,0,2,10,0,2,0, + 1,7,1,0,2,10,0,2,3,0,1,7,1,0,2,3,0,2,0,1, + 7,1,0,2,3,0,2,3,0,1,7,1,0,2,13,2,0,1,7,1, + 1,13,2,3,0,1,7,1,1,5,0,2,1,1,7,1,0,2,5,0, + 2,3,1,1,7,1,0,2,13,0,2,1,1,7,1,0,2,13,0,2, + 3,1,1,7,1,0,2,20,2,0,1,7,1,1,20,3,0,1,1,20, + 3,3,0,1,1,0,3,0,3,0,1,2,0,0,3,0,0,1,2,0, + 2,1,7,1,1,2,3,1,7,1,1,0,1,1,1,7,1,0,2,0, + 1,1,1,7,1,0,2,0,0,1,0,0,7,1,0,2,0,1,0,0, + 7,1,0,2,0,1,0,1,7,1,1,1,3,0,1,7,1,1,0,1, + 0,3,1,7,1,0,2,0,0,1,0,3,0,1,7,1,0,2,0,0, + 1,0,1,7,1,0,2,0,0,1,0,0,1,7,1,0,2,0,1,1, + 1,7,1,1,1,3,1,1,7,1,1,0,1,0,3,1,3,7,1,0, + 2,0,0,1,0,1,3,7,1,0,2,0,0,1,1,2,7,1,0,2, + 0,2,3,1,7,1,0,2,0,2,1,7,1,0,2,0,1,3,3,7, + 1,0,2,0,1,3,2,7,1,0,2,0,1,3,0,1,2,1,3,6, + 1,1,0,1,3,6,1,2,0,1,6,1,2,0,1,3,6,0,1,2, + 1,6,0,1,2,0,1,1,1,2,0,1,3,6,1,1,2,1,6,1, + 1,2,1,3,2,1,1,0,1,3,2,1,2,0,1,2,1,2,0,1, + 3,2,0,1,2,0,1,3,2,1,1,2,1,2,1,1,2,1,3,4, + 1,1,0,1,3,4,1,2,0,1,4,1,2,0,1,3,4,0,1,2, + 1,4,0,1,2,0,1,3,1,2,0,0,1,1,2,0,0,1,3,0, + 1,2,0,2,1,1,2,0,0,2,3,1,2,0,1,0,3,1,2,0, + 0,1,0,1,2,0,0,1,0,3,3,1,2,0,0,1,0,3,7,1, + 2,0,0,1,0,7,1,2,0,0,1,0,3,0,0,2,0,0,1,0, + 1,1,2,0,0,1,0,0,0,2,0,3,3,1,1,7,1,1,0,3, + 0,3,1,1,7,1,0,2,0,0,3,0,1,1,7,1,0,2,0,0, + 3,0,3,0,1,7,1,0,2,0,0,3,0,0,1,7,1,0,2,0, + 0,3,0,3,1,2,0,0,3,0,3,1,1,2,0,0,3,0,1,1, + 2,0,1,2,0,7,1,1,0,0,2,0,0,1,7,1,0,2,0,0, + 2,0,1,2,0,1,2,3,0,1,7,1,0,2,1,3,3,0,1,7, + 1,0,2,2,3,1,1,1,1,2,3,1,1,2,1,2,3,0,1,2, + 2,1,4,1,1,0,2,1,4,1,7,1,2,0,2,0,4,1,1,0, + 2,0,4,1,7,1,2,0,17,2,0,1,7,1,1,17,2,3,0,1, + 7,1,1,18,2,0,1,7,1,1,18,2,3,0,1,7,1,1,17,0, + 2,3,0,1,7,1,0,2,17,0,2,0,1,7,1,0,2,18,0,2, + 3,0,1,7,1,0,2,18,0,2,0,1,7,1,0,2,19,0,2,3, + 0,1,7,1,0,2,19,0,2,0,1,7,1,0,2,14,2,0,1,7, + 1,1,14,2,3,0,1,7,1,1,15,2,0,1,7,1,1,15,2,3, + 0,1,7,1,1,14,0,2,3,0,1,7,1,0,2,14,0,2,0,1, + 7,1,0,2,15,0,2,3,0,1,7,1,0,2,15,0,2,0,1,7, + 1,0,2,16,0,2,3,0,1,7,1,0,2,16,0,2,0,1,7,1, + 0,2,1,0,2,3,1,7,1,0,2,10,0,2,3,1,7,1,0,2, + 3,0,2,3,1,7,1,0,2,11,2,0,1,7,1,1,11,2,3,0, + 1,7,1,1,11,0,2,1,1,7,1,0,2,11,0,2,3,1,1,7, + 1,0,2,2,2,1,0,2,0,2,1,0,2,3,2,1,0,2,3,0, + 2,1,0,2,1,2,1,0,2,3,1,2,1,0,2,3,1,0,2,0, + 3,1,0,2,3,3,1,0,2,3,0,3,1,0,2,3,1,3,1,0, + 2,3,0,0,1,0,2,1,0,1,0,2,3,1,0,1,0,2,1,0, + 0,1,0,2,3,1,0,0,1,0,2,1,1,0,1,0,2,3,1,1, + 0,1,0,2,3,2,0,1,0,2,3,2,0,0,1,0,2,2,1,0, + 1,0,2,3,2,1,0,1,0,2,3,3,0,1,0,2,3,3,0,0, + 1,0,2,3,3,1,0,1,0,2,1,1,1,0,2,3,1,1,1,0, + 3,3,2,7,1,1,0,3,3,0,2,7,1,1,0,3,3,1,2,7, + 1,1,0,3,0,2,0,4,3,0,2,0,5,3,0,2,0,6,3,0, + 5,0,6,3,0,5,0,7,0,2,3,0,2,2,2,0,2,2,0,2, + 3,0,3,7,1,0,2,2,0,3,7,1,0,2,0,2,3,0,3,2, + 2,0,3,2,1,2,3,1,1,7,1,0,2,0,2,1,1,4,1,7, + 1,2,2,0,0,2,1,0,4,1,7,1,2,2,0,0,2,2,1,4, + 1,7,1,2,2,0,0,2,2,0,4,1,7,1,2,2,0,0,2,5, + 1,4,1,7,1,2,2,0,0,2,5,0,4,1,7,1,2,2,0,0, + 2,6,1,4,1,7,1,2,2,0,0,2,6,0,4,1,7,1,2,2, + 0,0,2,0,2,2,0,3,3,0,1,2,0,3,3,1,1,2,2,0, + 2,0,1,7,1,0,2,4,0,2,0,1,7,1,0,2,6,0,2,1, + 1,7,1,0,2,0,2,1,1,7,1,0,2,0,0,2,0,1,7,1, + 0,2,0,0,1,3,1,0,7,1,0,2,1,1,3,1,0,7,1,0, + 2,1,1,0,7,1,0,2,0,1,3,0,2,7,1,0,2,1,1,3, + 0,2,7,1,0,2,1,3,3,1,1,2,1,3,3,0,1,2,1,3, + 3,1,1,7,1,0,2,0,1,3,1,3,7,1,0,2,0,1,1,3, + 7,1,0,2,0,1,1,3,7,1,0,2,0,0,3,3,1,1,2,0, + 0,2,0,3,7,1,0,2,0,0,1,3,1,0,1,2,0,1,3,1, + 1,1,2,0,1,3,0,0,1,2,0,1,3,0,1,1,2,0,1,3, + 4,1,1,2,1,4,1,1,2,0,2,3,0,1,2,0,0,2,3,0, + 3,2,0,2,0,3,2,0,0,2,3,1,3,2,0,2,1,3,2,0, + 1,3,0,0,1,1,1,3,0,0,7,1,1,0,1,0,0,7,1,1, + 0,1,3,0,1,1,1,25,0,2,0,3,1,3,7,1,0,2,0,23, + 0,2,0,3,1,3,7,1,0,2,0,24,0,2,0,3,1,3,7,1, + 0,2,0,15,0,2,0,3,0,3,7,1,0,2,0,27,0,2,0,3, + 0,3,7,1,0,2,0,14,0,2,0,3,0,3,7,1,0,2,0,21, + 0,2,3,0,1,7,1,0,2,21,0,2,0,1,7,1,0,2,7,0, + 2,3,0,1,7,1,0,2,7,0,2,0,1,7,1,0,2,9,0,2, + 0,1,7,1,0,2,20,0,2,1,1,7,1,0,2,8,0,2,1,1, + 7,1,0,2,12,0,2,3,0,1,7,1,0,2,12,0,2,0,1,7, + 1,0,2,1,1,3,1,3,7,1,0,2,1,3,1,1,1,1,1,3, + 1,0,1,1,1,0,1,7,1,1,0,1,1,1,7,1,1,0,1,3, + 0,2,7,1,1,0,1,3,1,0,7,1,1,0,1,1,0,7,1,1, + 0,3,3,0,1,7,1,1,0,3,0,0,0,5,0,2,0,3,0,2, + 2,0,0,2,0,3,1,2,2,0,2,0,1,2,2,0,3,5,3,6, + 3,5,3,5,3,5,3,4,2,0,0,0,7,1,1,0,2,0,0,1, + 7,1,1,0,2,0,4,2,7,1,1,0,2,0,4,1,7,1,1,0, + 2,3,0,0,0,0,7,1,1,0,2,0,4,3,7,1,1,0,2,3, + 0,0,2,7,1,1,0,3,5,2,1,3,5,2,0,3,0,5,0,0, + 3,1,1,0,7,3,1,1,0,6,3,1,1,0,5,3,1,1,0,4, + 0,5,3,0,0,2,5,0,0,2,1,5,3,0,0,2,0,5,3,0, + 3,2,1,5,3,0,3,2,0,3,3,0,0,2,0,1,3,3,0,0, + 2,0,0,3,3,0,3,2,0,1,3,3,0,3,2,0,0,5,0,3, + 0,0,7,1,0,2,0,1,5,0,3,0,0,7,1,0,2,0,0,5, + 0,0,0,7,1,0,2,0,0,5,3,0,0,7,1,0,2,5,0,0, + 7,1,0,2,1,5,3,0,0,7,1,0,2,0,5,3,1,1,7,1, + 0,2,5,1,1,7,1,0,2,1,5,3,1,1,7,1,0,2,0,5, + 3,0,1,7,1,0,2,5,0,1,7,1,0,2,1,5,3,0,1,7, + 1,0,2,0,6,3,0,1,7,1,0,2,6,0,1,7,1,0,2,1, + 6,3,0,1,7,1,0,2,0,5,3,1,0,7,1,0,2,5,1,0, + 7,1,0,2,1,5,3,1,0,7,1,0,2,0,5,3,1,2,2,1, + 5,3,1,2,2,0,5,1,2,2,0,5,0,3,0,0,3,7,1,0, + 2,0,1,5,0,3,0,0,3,7,1,0,2,0,0,5,0,0,0,3, + 7,1,0,2,0,0,5,0,3,0,3,7,1,0,2,0,1,5,0,3, + 0,3,7,1,0,2,0,0,5,0,0,3,7,1,0,2,0,0,5,0, + 3,0,1,3,7,1,0,2,0,1,5,0,3,0,1,3,7,1,0,2, + 0,0,5,0,0,1,3,7,1,0,2,0,0,6,3,0,0,2,1,6, + 3,0,0,2,0,6,0,0,2,0,5,0,3,0,3,2,0,1,5,0, + 3,0,3,2,0,0,5,0,0,3,2,0,0,5,0,3,3,2,0,1, + 5,0,3,3,2,0,0,5,0,3,2,0,0,5,0,3,1,3,2,0, + 1,5,0,3,1,3,2,0,0,5,0,1,3,2,0,0,5,0,0,2, + 0,5,3,0,3,7,1,0,2,5,0,3,7,1,0,2,1,5,3,0, + 3,7,1,0,2,0,5,3,0,2,7,1,0,2,5,0,2,7,1,0, + 2,1,5,3,0,2,7,1,0,2,0,5,3,1,2,7,1,0,2,5, + 1,2,7,1,0,2,1,5,3,1,2,7,1,0,2,0,6,3,0,2, + 2,6,0,2,2,1,6,3,0,2,2,0,6,0,2,2,0,6,3,0, + 1,2,1,6,3,0,1,2,0,6,0,1,2,0,6,3,0,3,2,1, + 6,3,0,3,2,0,3,3,0,0,7,1,0,2,0,1,3,3,0,0, + 7,1,0,2,0,5,0,3,7,1,0,2,0,5,0,3,7,1,0,2, + 0,0,5,0,3,1,7,1,0,2,0,0,5,0,1,7,1,0,2,0, +}; + + + +const xed_encode_function_pointer_t xed_encode_groups[XED_ENC_GROUPS] = { + xed_encode_group_0, + xed_encode_group_1, + xed_encode_group_2, + xed_encode_group_3, + xed_encode_group_4, + xed_encode_group_5, + xed_encode_group_6, + xed_encode_group_7, + xed_encode_group_8, + xed_encode_group_9, + xed_encode_group_10, + xed_encode_group_11, + xed_encode_group_12, + xed_encode_group_13, + xed_encode_group_14, + xed_encode_group_15, + xed_encode_group_16, + xed_encode_group_17, + xed_encode_group_18, + xed_encode_group_19, + xed_encode_group_20, + xed_encode_group_21, + xed_encode_group_22, + xed_encode_group_23, + xed_encode_group_24, + xed_encode_group_25, + xed_encode_group_26, + xed_encode_group_27, + xed_encode_group_28, + xed_encode_group_29, + xed_encode_group_30, + xed_encode_group_31, + xed_encode_group_32, + xed_encode_group_33, + xed_encode_group_34, + xed_encode_group_35, + xed_encode_group_36, + xed_encode_group_37, + xed_encode_group_38, + xed_encode_group_39, + xed_encode_group_40, + xed_encode_group_41, + xed_encode_group_42, + xed_encode_group_43, + xed_encode_group_44, + xed_encode_group_45, + xed_encode_group_46, + xed_encode_group_47, + xed_encode_group_48, + xed_encode_group_49, + xed_encode_group_50, + xed_encode_group_51, + xed_encode_group_52, + xed_encode_group_53, + xed_encode_group_54, + xed_encode_group_55, + xed_encode_group_56, + xed_encode_group_57, + xed_encode_group_58, + xed_encode_group_59, + xed_encode_group_60, + xed_encode_group_61, + xed_encode_group_62, + xed_encode_group_63, + xed_encode_group_64, + xed_encode_group_65, + xed_encode_group_66, + xed_encode_group_67, + xed_encode_group_68, + xed_encode_group_69, + xed_encode_group_70, + xed_encode_group_71, + xed_encode_group_72, + xed_encode_group_73, + xed_encode_group_74, + xed_encode_group_75, + xed_encode_group_76, + xed_encode_group_77, + xed_encode_group_78, + xed_encode_group_79, + xed_encode_group_80, + xed_encode_group_81, + xed_encode_group_82, + xed_encode_group_83, + xed_encode_group_84, + xed_encode_group_85, + xed_encode_group_86, + xed_encode_group_87, + xed_encode_group_88, + xed_encode_group_89, + xed_encode_group_90, + xed_encode_group_91, + xed_encode_group_92, + xed_encode_group_93, + xed_encode_group_94, + xed_encode_group_95, + xed_encode_group_96, + xed_encode_group_97, + xed_encode_group_98, + xed_encode_group_99, + xed_encode_group_100, + xed_encode_group_101, + xed_encode_group_102, + xed_encode_group_103, + xed_encode_group_104, + xed_encode_group_105, + xed_encode_group_106, + xed_encode_group_107, + xed_encode_group_108, + xed_encode_group_109, + xed_encode_group_110, + xed_encode_group_111, + xed_encode_group_112, + xed_encode_group_113, + xed_encode_group_114, + xed_encode_group_115, + xed_encode_group_116, + xed_encode_group_117, + xed_encode_group_118, + xed_encode_group_119, + xed_encode_group_120, + xed_encode_group_121, + xed_encode_group_122, + xed_encode_group_123, + xed_encode_group_124, + xed_encode_group_125, + xed_encode_group_126, + xed_encode_group_127, + xed_encode_group_128, + xed_encode_group_129, + xed_encode_group_130, + xed_encode_group_131, + xed_encode_group_132, + xed_encode_group_133, + xed_encode_group_134, + xed_encode_group_135, + xed_encode_group_136, + xed_encode_group_137, + xed_encode_group_138, + xed_encode_group_139, + xed_encode_group_140, + xed_encode_group_141, + xed_encode_group_142, + xed_encode_group_143, + xed_encode_group_144, + xed_encode_group_145, + xed_encode_group_146, + xed_encode_group_147, + xed_encode_group_148, + xed_encode_group_149, + xed_encode_group_150, + xed_encode_group_151, + xed_encode_group_152, + xed_encode_group_153, + xed_encode_group_154, + xed_encode_group_155, + xed_encode_group_156, + xed_encode_group_157, + xed_encode_group_158, + xed_encode_group_159, + xed_encode_group_160, + xed_encode_group_161, + xed_encode_group_162, + xed_encode_group_163, + xed_encode_group_164, + xed_encode_group_165, + xed_encode_group_166, + xed_encode_group_167, + xed_encode_group_168, + xed_encode_group_169, + xed_encode_group_170, + xed_encode_group_171, + xed_encode_group_172, + xed_encode_group_173, + xed_encode_group_174, + xed_encode_group_175, + xed_encode_group_176, + xed_encode_group_177, + xed_encode_group_178, + xed_encode_group_179, + xed_encode_group_180, + xed_encode_group_181, + xed_encode_group_182, + xed_encode_group_183, + xed_encode_group_184, + xed_encode_group_185, + xed_encode_group_186, + xed_encode_group_187, + xed_encode_group_188, + xed_encode_group_189, + xed_encode_group_190, + xed_encode_group_191, + xed_encode_group_192, + xed_encode_group_193, + xed_encode_group_194, + xed_encode_group_195, + xed_encode_group_196, + xed_encode_group_197, + xed_encode_group_198, + xed_encode_group_199, + xed_encode_group_200, + xed_encode_group_201, + xed_encode_group_202, + xed_encode_group_203, + xed_encode_group_204, + xed_encode_group_205, + xed_encode_group_206, + xed_encode_group_207, + xed_encode_group_208, + xed_encode_group_209, + xed_encode_group_210, + xed_encode_group_211, + xed_encode_group_212, + xed_encode_group_213, + xed_encode_group_214, + xed_encode_group_215, + xed_encode_group_216, + xed_encode_group_217, + xed_encode_group_218, + xed_encode_group_219, + xed_encode_group_220, + xed_encode_group_221, + xed_encode_group_222, + xed_encode_group_223, + xed_encode_group_224, + xed_encode_group_225, + xed_encode_group_226, + xed_encode_group_227, + xed_encode_group_228, + xed_encode_group_229, + xed_encode_group_230, + xed_encode_group_231, + xed_encode_group_232, + xed_encode_group_233, + xed_encode_group_234, + xed_encode_group_235, + xed_encode_group_236, + xed_encode_group_237, + xed_encode_group_238, + xed_encode_group_239, + xed_encode_group_240, + xed_encode_group_241, + xed_encode_group_242, + xed_encode_group_243, + xed_encode_group_244, + xed_encode_group_245, + xed_encode_group_246, + xed_encode_group_247, + xed_encode_group_248, + xed_encode_group_249, + xed_encode_group_250, + xed_encode_group_251, + xed_encode_group_252, + xed_encode_group_253, + xed_encode_group_254, + xed_encode_group_255, + xed_encode_group_256, + xed_encode_group_257, + xed_encode_group_258, + xed_encode_group_259, + xed_encode_group_260, + xed_encode_group_261, + xed_encode_group_262, + xed_encode_group_263, + xed_encode_group_264, + xed_encode_group_265, + xed_encode_group_266, + xed_encode_group_267, + xed_encode_group_268, + xed_encode_group_269, + xed_encode_group_270, + xed_encode_group_271, + xed_encode_group_272, + xed_encode_group_273, + xed_encode_group_274, + xed_encode_group_275, + xed_encode_group_276, + xed_encode_group_277, + xed_encode_group_278, + xed_encode_group_279, + xed_encode_group_280, + xed_encode_group_281, + xed_encode_group_282, + xed_encode_group_283, + xed_encode_group_284, + xed_encode_group_285, + xed_encode_group_286, + xed_encode_group_287, + xed_encode_group_288, + xed_encode_group_289, + xed_encode_group_290, + xed_encode_group_291, + xed_encode_group_292, + xed_encode_group_293, + xed_encode_group_294, + xed_encode_group_295, + xed_encode_group_296, + xed_encode_group_297, + xed_encode_group_298, + xed_encode_group_299, + xed_encode_group_300, + xed_encode_group_301, + xed_encode_group_302, + xed_encode_group_303, + xed_encode_group_304, + xed_encode_group_305, + xed_encode_group_306, + xed_encode_group_307, + xed_encode_group_308, + xed_encode_group_309, + xed_encode_group_310, + xed_encode_group_311, + xed_encode_group_312, + xed_encode_group_313, + xed_encode_group_314, + xed_encode_group_315, + xed_encode_group_316, + xed_encode_group_317, + xed_encode_group_318, + xed_encode_group_319, + xed_encode_group_320, + xed_encode_group_321, + xed_encode_group_322, + xed_encode_group_323, + xed_encode_group_324, + xed_encode_group_325, + xed_encode_group_326, + xed_encode_group_327, + xed_encode_group_328, + xed_encode_group_329, + xed_encode_group_330, + xed_encode_group_331, + xed_encode_group_332, + xed_encode_group_333, + xed_encode_group_334, + xed_encode_group_335, + xed_encode_group_336, + xed_encode_group_337, + xed_encode_group_338, + xed_encode_group_339, + xed_encode_group_340, + xed_encode_group_341, + xed_encode_group_342, + xed_encode_group_343, + xed_encode_group_344, + xed_encode_group_345, + xed_encode_group_346, + xed_encode_group_347, + xed_encode_group_348, + xed_encode_group_349, + xed_encode_group_350, + xed_encode_group_351, + xed_encode_group_352, + xed_encode_group_353, + xed_encode_group_354, + xed_encode_group_355, + xed_encode_group_356, + xed_encode_group_357, + xed_encode_group_358, + xed_encode_group_359, + xed_encode_group_360, + xed_encode_group_361, + xed_encode_group_362, + xed_encode_group_363, + xed_encode_group_364, + xed_encode_group_365, + xed_encode_group_366, + xed_encode_group_367, + xed_encode_group_368, + xed_encode_group_369, + xed_encode_group_370, + xed_encode_group_371, + xed_encode_group_372, + xed_encode_group_373, + xed_encode_group_374, + xed_encode_group_375, + xed_encode_group_376, + xed_encode_group_377, + xed_encode_group_378, + xed_encode_group_379, + xed_encode_group_380, + xed_encode_group_381, + xed_encode_group_382, + xed_encode_group_383, + xed_encode_group_384, + xed_encode_group_385, + xed_encode_group_386, + xed_encode_group_387, + xed_encode_group_388, + xed_encode_group_389, + xed_encode_group_390, + xed_encode_group_391, + xed_encode_group_392, + xed_encode_group_393, + xed_encode_group_394, + xed_encode_group_395, + xed_encode_group_396, + xed_encode_group_397, + xed_encode_group_398, + xed_encode_group_399, + xed_encode_group_400, + xed_encode_group_401, + xed_encode_group_402, + xed_encode_group_403, + xed_encode_group_404, + xed_encode_group_405, + xed_encode_group_406, + xed_encode_group_407, + xed_encode_group_408, + xed_encode_group_409, + xed_encode_group_410, + xed_encode_group_411, + xed_encode_group_412, + xed_encode_group_413, + xed_encode_group_414, + xed_encode_group_415, + xed_encode_group_416, + xed_encode_group_417, + xed_encode_group_418, + xed_encode_group_419, + xed_encode_group_420, + xed_encode_group_421, + xed_encode_group_422, + xed_encode_group_423, + xed_encode_group_424, + xed_encode_group_425, + xed_encode_group_426, + xed_encode_group_427, + xed_encode_group_428, + xed_encode_group_429, + xed_encode_group_430, + xed_encode_group_431, + xed_encode_group_432, + xed_encode_group_433, + xed_encode_group_434, + xed_encode_group_435, + xed_encode_group_436, + xed_encode_group_437, + xed_encode_group_438, + xed_encode_group_439, + xed_encode_group_440, + xed_encode_group_441, + xed_encode_group_442, + xed_encode_group_443, + xed_encode_group_444, + xed_encode_group_445, + xed_encode_group_446, + xed_encode_group_447, + xed_encode_group_448, + xed_encode_group_449, + xed_encode_group_450, + xed_encode_group_451, + xed_encode_group_452, + xed_encode_group_453, + xed_encode_group_454, + xed_encode_group_455, + xed_encode_group_456, + xed_encode_group_457, + xed_encode_group_458, + xed_encode_group_459, + xed_encode_group_460, + xed_encode_group_461, + xed_encode_group_462, + xed_encode_group_463, + xed_encode_group_464, + xed_encode_group_465, + xed_encode_group_466, + xed_encode_group_467, + xed_encode_group_468, + xed_encode_group_469, + xed_encode_group_470, + xed_encode_group_471, + xed_encode_group_472, + xed_encode_group_473, + xed_encode_group_474, + xed_encode_group_475, + xed_encode_group_476, + xed_encode_group_477, + xed_encode_group_478, + xed_encode_group_479, + xed_encode_group_480, + xed_encode_group_481, + xed_encode_group_482, + xed_encode_group_483, + xed_encode_group_484, + xed_encode_group_485, + xed_encode_group_486, + xed_encode_group_487, + xed_encode_group_488, + xed_encode_group_489, + xed_encode_group_490, + xed_encode_group_491, + xed_encode_group_492, + xed_encode_group_493, + xed_encode_group_494, + xed_encode_group_495, + xed_encode_group_496, + xed_encode_group_497, + xed_encode_group_498, + xed_encode_group_499, + xed_encode_group_500, + xed_encode_group_501, + xed_encode_group_502, + xed_encode_group_503, + xed_encode_group_504, + xed_encode_group_505, + xed_encode_group_506, + xed_encode_group_507, + xed_encode_group_508, + xed_encode_group_509, + xed_encode_group_510, + xed_encode_group_511, + xed_encode_group_512, + xed_encode_group_513, + xed_encode_group_514, + xed_encode_group_515, + xed_encode_group_516, + xed_encode_group_517, + xed_encode_group_518, + xed_encode_group_519, + xed_encode_group_520, + xed_encode_group_521, + xed_encode_group_522, + xed_encode_group_523, + xed_encode_group_524, + xed_encode_group_525, + xed_encode_group_526, + xed_encode_group_527, + xed_encode_group_528, + xed_encode_group_529, + xed_encode_group_530, + xed_encode_group_531, + xed_encode_group_532, + xed_encode_group_533, + xed_encode_group_534, +}; diff --git a/CodeVirtualizer/build/obj/xed-error-enum.c b/CodeVirtualizer/build/obj/xed-error-enum.c new file mode 100644 index 0000000..a38348b --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-error-enum.c @@ -0,0 +1,100 @@ +/// @file xed-error-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-error-enum.h" + +typedef struct { + const char* name; + xed_error_enum_t value; +} name_table_xed_error_enum_t; +static const name_table_xed_error_enum_t name_array_xed_error_enum_t[] = { +{"NONE", XED_ERROR_NONE}, +{"BUFFER_TOO_SHORT", XED_ERROR_BUFFER_TOO_SHORT}, +{"GENERAL_ERROR", XED_ERROR_GENERAL_ERROR}, +{"INVALID_FOR_CHIP", XED_ERROR_INVALID_FOR_CHIP}, +{"BAD_REGISTER", XED_ERROR_BAD_REGISTER}, +{"BAD_LOCK_PREFIX", XED_ERROR_BAD_LOCK_PREFIX}, +{"BAD_REP_PREFIX", XED_ERROR_BAD_REP_PREFIX}, +{"BAD_LEGACY_PREFIX", XED_ERROR_BAD_LEGACY_PREFIX}, +{"BAD_REX_PREFIX", XED_ERROR_BAD_REX_PREFIX}, +{"BAD_EVEX_UBIT", XED_ERROR_BAD_EVEX_UBIT}, +{"BAD_MAP", XED_ERROR_BAD_MAP}, +{"BAD_EVEX_V_PRIME", XED_ERROR_BAD_EVEX_V_PRIME}, +{"BAD_EVEX_Z_NO_MASKING", XED_ERROR_BAD_EVEX_Z_NO_MASKING}, +{"NO_OUTPUT_POINTER", XED_ERROR_NO_OUTPUT_POINTER}, +{"NO_AGEN_CALL_BACK_REGISTERED", XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED}, +{"BAD_MEMOP_INDEX", XED_ERROR_BAD_MEMOP_INDEX}, +{"CALLBACK_PROBLEM", XED_ERROR_CALLBACK_PROBLEM}, +{"GATHER_REGS", XED_ERROR_GATHER_REGS}, +{"INSTR_TOO_LONG", XED_ERROR_INSTR_TOO_LONG}, +{"INVALID_MODE", XED_ERROR_INVALID_MODE}, +{"BAD_EVEX_LL", XED_ERROR_BAD_EVEX_LL}, +{"BAD_REG_MATCH", XED_ERROR_BAD_REG_MATCH}, +{"LAST", XED_ERROR_LAST}, +{0, XED_ERROR_LAST}, +}; + + +xed_error_enum_t str2xed_error_enum_t(const char* s) +{ + const name_table_xed_error_enum_t* p = name_array_xed_error_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_ERROR_LAST; +} + + +const char* xed_error_enum_t2str(const xed_error_enum_t p) +{ + xed_error_enum_t type_idx = p; + if ( p > XED_ERROR_LAST) type_idx = XED_ERROR_LAST; + return name_array_xed_error_enum_t[type_idx].name; +} + +xed_error_enum_t xed_error_enum_t_last(void) { + return XED_ERROR_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_ERROR_NONE: + case XED_ERROR_BUFFER_TOO_SHORT: + case XED_ERROR_GENERAL_ERROR: + case XED_ERROR_INVALID_FOR_CHIP: + case XED_ERROR_BAD_REGISTER: + case XED_ERROR_BAD_LOCK_PREFIX: + case XED_ERROR_BAD_REP_PREFIX: + case XED_ERROR_BAD_LEGACY_PREFIX: + case XED_ERROR_BAD_REX_PREFIX: + case XED_ERROR_BAD_EVEX_UBIT: + case XED_ERROR_BAD_MAP: + case XED_ERROR_BAD_EVEX_V_PRIME: + case XED_ERROR_BAD_EVEX_Z_NO_MASKING: + case XED_ERROR_NO_OUTPUT_POINTER: + case XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED: + case XED_ERROR_BAD_MEMOP_INDEX: + case XED_ERROR_CALLBACK_PROBLEM: + case XED_ERROR_GATHER_REGS: + case XED_ERROR_INSTR_TOO_LONG: + case XED_ERROR_INVALID_MODE: + case XED_ERROR_BAD_EVEX_LL: + case XED_ERROR_BAD_REG_MATCH: + case XED_ERROR_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-error-enum.h b/CodeVirtualizer/build/obj/xed-error-enum.h new file mode 100644 index 0000000..8d33d19 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-error-enum.h @@ -0,0 +1,73 @@ +/// @file xed-error-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ERROR_ENUM_H) +# define XED_ERROR_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ERROR_NONE_DEFINED 1 +#define XED_ERROR_BUFFER_TOO_SHORT_DEFINED 1 +#define XED_ERROR_GENERAL_ERROR_DEFINED 1 +#define XED_ERROR_INVALID_FOR_CHIP_DEFINED 1 +#define XED_ERROR_BAD_REGISTER_DEFINED 1 +#define XED_ERROR_BAD_LOCK_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_REP_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_LEGACY_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_REX_PREFIX_DEFINED 1 +#define XED_ERROR_BAD_EVEX_UBIT_DEFINED 1 +#define XED_ERROR_BAD_MAP_DEFINED 1 +#define XED_ERROR_BAD_EVEX_V_PRIME_DEFINED 1 +#define XED_ERROR_BAD_EVEX_Z_NO_MASKING_DEFINED 1 +#define XED_ERROR_NO_OUTPUT_POINTER_DEFINED 1 +#define XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED_DEFINED 1 +#define XED_ERROR_BAD_MEMOP_INDEX_DEFINED 1 +#define XED_ERROR_CALLBACK_PROBLEM_DEFINED 1 +#define XED_ERROR_GATHER_REGS_DEFINED 1 +#define XED_ERROR_INSTR_TOO_LONG_DEFINED 1 +#define XED_ERROR_INVALID_MODE_DEFINED 1 +#define XED_ERROR_BAD_EVEX_LL_DEFINED 1 +#define XED_ERROR_BAD_REG_MATCH_DEFINED 1 +#define XED_ERROR_LAST_DEFINED 1 +typedef enum { + XED_ERROR_NONE, ///< There was no error + XED_ERROR_BUFFER_TOO_SHORT, ///< There were not enough bytes in the given buffer + XED_ERROR_GENERAL_ERROR, ///< XED could not decode the given instruction + XED_ERROR_INVALID_FOR_CHIP, ///< The instruciton is not valid for the specified chip + XED_ERROR_BAD_REGISTER, ///< XED could not decode the given instruction because an invalid register encoding was used. + XED_ERROR_BAD_LOCK_PREFIX, ///< A lock prefix was found where none is allowed. + XED_ERROR_BAD_REP_PREFIX, ///< An F2 or F3 prefix was found where none is allowed. + XED_ERROR_BAD_LEGACY_PREFIX, ///< A 66, F2 or F3 prefix was found where none is allowed. + XED_ERROR_BAD_REX_PREFIX, ///< A REX prefix was found where none is allowed. + XED_ERROR_BAD_EVEX_UBIT, ///< An illegal value for the EVEX.U bit was present in the instruction. + XED_ERROR_BAD_MAP, ///< An illegal value for the MAP field was detected in the instruction. + XED_ERROR_BAD_EVEX_V_PRIME, ///< EVEX.V'=0 was detected in a non-64b mode instruction. + XED_ERROR_BAD_EVEX_Z_NO_MASKING, ///< EVEX.Z!=0 when EVEX.aaa==0 + XED_ERROR_NO_OUTPUT_POINTER, ///< The output pointer for xed_agen was zero + XED_ERROR_NO_AGEN_CALL_BACK_REGISTERED, ///< One or both of the callbacks for xed_agen were missing. + XED_ERROR_BAD_MEMOP_INDEX, ///< Memop indices must be 0 or 1. + XED_ERROR_CALLBACK_PROBLEM, ///< The register or segment callback for xed_agen experienced a problem + XED_ERROR_GATHER_REGS, ///< The index, dest and mask regs for AVX2 gathers must be different. + XED_ERROR_INSTR_TOO_LONG, ///< Full decode of instruction would exeed 15B. + XED_ERROR_INVALID_MODE, ///< The instruction was not valid for the specified mode + XED_ERROR_BAD_EVEX_LL, ///< EVEX.LL must not ==3 unless using embedded rounding + XED_ERROR_BAD_REG_MATCH, ///< Source registers must not match the destination register for this instruction. + XED_ERROR_LAST +} xed_error_enum_t; + +/// This converts strings to #xed_error_enum_t types. +/// @param s A C-string. +/// @return #xed_error_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_error_enum_t str2xed_error_enum_t(const char* s); +/// This converts strings to #xed_error_enum_t types. +/// @param p An enumeration element of type xed_error_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_error_enum_t2str(const xed_error_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_error_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_error_enum_t xed_error_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-exception-enum.c b/CodeVirtualizer/build/obj/xed-exception-enum.c new file mode 100644 index 0000000..cd0f20d --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-exception-enum.c @@ -0,0 +1,166 @@ +/// @file xed-exception-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-exception-enum.h" + +typedef struct { + const char* name; + xed_exception_enum_t value; +} name_table_xed_exception_enum_t; +static const name_table_xed_exception_enum_t name_array_xed_exception_enum_t[] = { +{"INVALID", XED_EXCEPTION_INVALID}, +{"AMX_E1", XED_EXCEPTION_AMX_E1}, +{"AMX_E2", XED_EXCEPTION_AMX_E2}, +{"AMX_E3", XED_EXCEPTION_AMX_E3}, +{"AMX_E4", XED_EXCEPTION_AMX_E4}, +{"AMX_E5", XED_EXCEPTION_AMX_E5}, +{"AMX_E6", XED_EXCEPTION_AMX_E6}, +{"AVX512_E1", XED_EXCEPTION_AVX512_E1}, +{"AVX512_E10", XED_EXCEPTION_AVX512_E10}, +{"AVX512_E10NF", XED_EXCEPTION_AVX512_E10NF}, +{"AVX512_E11", XED_EXCEPTION_AVX512_E11}, +{"AVX512_E12", XED_EXCEPTION_AVX512_E12}, +{"AVX512_E12NP", XED_EXCEPTION_AVX512_E12NP}, +{"AVX512_E1NF", XED_EXCEPTION_AVX512_E1NF}, +{"AVX512_E2", XED_EXCEPTION_AVX512_E2}, +{"AVX512_E3", XED_EXCEPTION_AVX512_E3}, +{"AVX512_E3NF", XED_EXCEPTION_AVX512_E3NF}, +{"AVX512_E4", XED_EXCEPTION_AVX512_E4}, +{"AVX512_E4NF", XED_EXCEPTION_AVX512_E4NF}, +{"AVX512_E5", XED_EXCEPTION_AVX512_E5}, +{"AVX512_E5NF", XED_EXCEPTION_AVX512_E5NF}, +{"AVX512_E6", XED_EXCEPTION_AVX512_E6}, +{"AVX512_E6NF", XED_EXCEPTION_AVX512_E6NF}, +{"AVX512_E7NM", XED_EXCEPTION_AVX512_E7NM}, +{"AVX512_E7NM128", XED_EXCEPTION_AVX512_E7NM128}, +{"AVX512_E9NF", XED_EXCEPTION_AVX512_E9NF}, +{"AVX512_K20", XED_EXCEPTION_AVX512_K20}, +{"AVX512_K21", XED_EXCEPTION_AVX512_K21}, +{"AVX_TYPE_1", XED_EXCEPTION_AVX_TYPE_1}, +{"AVX_TYPE_11", XED_EXCEPTION_AVX_TYPE_11}, +{"AVX_TYPE_12", XED_EXCEPTION_AVX_TYPE_12}, +{"AVX_TYPE_2", XED_EXCEPTION_AVX_TYPE_2}, +{"AVX_TYPE_2D", XED_EXCEPTION_AVX_TYPE_2D}, +{"AVX_TYPE_3", XED_EXCEPTION_AVX_TYPE_3}, +{"AVX_TYPE_4", XED_EXCEPTION_AVX_TYPE_4}, +{"AVX_TYPE_4M", XED_EXCEPTION_AVX_TYPE_4M}, +{"AVX_TYPE_5", XED_EXCEPTION_AVX_TYPE_5}, +{"AVX_TYPE_5L", XED_EXCEPTION_AVX_TYPE_5L}, +{"AVX_TYPE_6", XED_EXCEPTION_AVX_TYPE_6}, +{"AVX_TYPE_7", XED_EXCEPTION_AVX_TYPE_7}, +{"AVX_TYPE_8", XED_EXCEPTION_AVX_TYPE_8}, +{"MMX_FP", XED_EXCEPTION_MMX_FP}, +{"MMX_FP_16ALIGN", XED_EXCEPTION_MMX_FP_16ALIGN}, +{"MMX_MEM", XED_EXCEPTION_MMX_MEM}, +{"MMX_NOFP", XED_EXCEPTION_MMX_NOFP}, +{"MMX_NOFP2", XED_EXCEPTION_MMX_NOFP2}, +{"MMX_NOMEM", XED_EXCEPTION_MMX_NOMEM}, +{"SSE_TYPE_1", XED_EXCEPTION_SSE_TYPE_1}, +{"SSE_TYPE_2", XED_EXCEPTION_SSE_TYPE_2}, +{"SSE_TYPE_2D", XED_EXCEPTION_SSE_TYPE_2D}, +{"SSE_TYPE_3", XED_EXCEPTION_SSE_TYPE_3}, +{"SSE_TYPE_4", XED_EXCEPTION_SSE_TYPE_4}, +{"SSE_TYPE_4M", XED_EXCEPTION_SSE_TYPE_4M}, +{"SSE_TYPE_5", XED_EXCEPTION_SSE_TYPE_5}, +{"SSE_TYPE_7", XED_EXCEPTION_SSE_TYPE_7}, +{"LAST", XED_EXCEPTION_LAST}, +{0, XED_EXCEPTION_LAST}, +}; + + +xed_exception_enum_t str2xed_exception_enum_t(const char* s) +{ + const name_table_xed_exception_enum_t* p = name_array_xed_exception_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_EXCEPTION_INVALID; +} + + +const char* xed_exception_enum_t2str(const xed_exception_enum_t p) +{ + xed_exception_enum_t type_idx = p; + if ( p > XED_EXCEPTION_LAST) type_idx = XED_EXCEPTION_LAST; + return name_array_xed_exception_enum_t[type_idx].name; +} + +xed_exception_enum_t xed_exception_enum_t_last(void) { + return XED_EXCEPTION_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_EXCEPTION_INVALID: + case XED_EXCEPTION_AMX_E1: + case XED_EXCEPTION_AMX_E2: + case XED_EXCEPTION_AMX_E3: + case XED_EXCEPTION_AMX_E4: + case XED_EXCEPTION_AMX_E5: + case XED_EXCEPTION_AMX_E6: + case XED_EXCEPTION_AVX512_E1: + case XED_EXCEPTION_AVX512_E10: + case XED_EXCEPTION_AVX512_E10NF: + case XED_EXCEPTION_AVX512_E11: + case XED_EXCEPTION_AVX512_E12: + case XED_EXCEPTION_AVX512_E12NP: + case XED_EXCEPTION_AVX512_E1NF: + case XED_EXCEPTION_AVX512_E2: + case XED_EXCEPTION_AVX512_E3: + case XED_EXCEPTION_AVX512_E3NF: + case XED_EXCEPTION_AVX512_E4: + case XED_EXCEPTION_AVX512_E4NF: + case XED_EXCEPTION_AVX512_E5: + case XED_EXCEPTION_AVX512_E5NF: + case XED_EXCEPTION_AVX512_E6: + case XED_EXCEPTION_AVX512_E6NF: + case XED_EXCEPTION_AVX512_E7NM: + case XED_EXCEPTION_AVX512_E7NM128: + case XED_EXCEPTION_AVX512_E9NF: + case XED_EXCEPTION_AVX512_K20: + case XED_EXCEPTION_AVX512_K21: + case XED_EXCEPTION_AVX_TYPE_1: + case XED_EXCEPTION_AVX_TYPE_11: + case XED_EXCEPTION_AVX_TYPE_12: + case XED_EXCEPTION_AVX_TYPE_2: + case XED_EXCEPTION_AVX_TYPE_2D: + case XED_EXCEPTION_AVX_TYPE_3: + case XED_EXCEPTION_AVX_TYPE_4: + case XED_EXCEPTION_AVX_TYPE_4M: + case XED_EXCEPTION_AVX_TYPE_5: + case XED_EXCEPTION_AVX_TYPE_5L: + case XED_EXCEPTION_AVX_TYPE_6: + case XED_EXCEPTION_AVX_TYPE_7: + case XED_EXCEPTION_AVX_TYPE_8: + case XED_EXCEPTION_MMX_FP: + case XED_EXCEPTION_MMX_FP_16ALIGN: + case XED_EXCEPTION_MMX_MEM: + case XED_EXCEPTION_MMX_NOFP: + case XED_EXCEPTION_MMX_NOFP2: + case XED_EXCEPTION_MMX_NOMEM: + case XED_EXCEPTION_SSE_TYPE_1: + case XED_EXCEPTION_SSE_TYPE_2: + case XED_EXCEPTION_SSE_TYPE_2D: + case XED_EXCEPTION_SSE_TYPE_3: + case XED_EXCEPTION_SSE_TYPE_4: + case XED_EXCEPTION_SSE_TYPE_4M: + case XED_EXCEPTION_SSE_TYPE_5: + case XED_EXCEPTION_SSE_TYPE_7: + case XED_EXCEPTION_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-exception-enum.h b/CodeVirtualizer/build/obj/xed-exception-enum.h new file mode 100644 index 0000000..c8eacc9 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-exception-enum.h @@ -0,0 +1,139 @@ +/// @file xed-exception-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_EXCEPTION_ENUM_H) +# define XED_EXCEPTION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_EXCEPTION_INVALID_DEFINED 1 +#define XED_EXCEPTION_AMX_E1_DEFINED 1 +#define XED_EXCEPTION_AMX_E2_DEFINED 1 +#define XED_EXCEPTION_AMX_E3_DEFINED 1 +#define XED_EXCEPTION_AMX_E4_DEFINED 1 +#define XED_EXCEPTION_AMX_E5_DEFINED 1 +#define XED_EXCEPTION_AMX_E6_DEFINED 1 +#define XED_EXCEPTION_AVX512_E1_DEFINED 1 +#define XED_EXCEPTION_AVX512_E10_DEFINED 1 +#define XED_EXCEPTION_AVX512_E10NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E11_DEFINED 1 +#define XED_EXCEPTION_AVX512_E12_DEFINED 1 +#define XED_EXCEPTION_AVX512_E12NP_DEFINED 1 +#define XED_EXCEPTION_AVX512_E1NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E2_DEFINED 1 +#define XED_EXCEPTION_AVX512_E3_DEFINED 1 +#define XED_EXCEPTION_AVX512_E3NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E4_DEFINED 1 +#define XED_EXCEPTION_AVX512_E4NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E5_DEFINED 1 +#define XED_EXCEPTION_AVX512_E5NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E6_DEFINED 1 +#define XED_EXCEPTION_AVX512_E6NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_E7NM_DEFINED 1 +#define XED_EXCEPTION_AVX512_E7NM128_DEFINED 1 +#define XED_EXCEPTION_AVX512_E9NF_DEFINED 1 +#define XED_EXCEPTION_AVX512_K20_DEFINED 1 +#define XED_EXCEPTION_AVX512_K21_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_1_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_11_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_12_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_2_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_2D_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_3_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_4_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_4M_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_5_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_5L_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_6_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_7_DEFINED 1 +#define XED_EXCEPTION_AVX_TYPE_8_DEFINED 1 +#define XED_EXCEPTION_MMX_FP_DEFINED 1 +#define XED_EXCEPTION_MMX_FP_16ALIGN_DEFINED 1 +#define XED_EXCEPTION_MMX_MEM_DEFINED 1 +#define XED_EXCEPTION_MMX_NOFP_DEFINED 1 +#define XED_EXCEPTION_MMX_NOFP2_DEFINED 1 +#define XED_EXCEPTION_MMX_NOMEM_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_1_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_2_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_2D_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_3_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_4_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_4M_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_5_DEFINED 1 +#define XED_EXCEPTION_SSE_TYPE_7_DEFINED 1 +#define XED_EXCEPTION_LAST_DEFINED 1 +typedef enum { + XED_EXCEPTION_INVALID, + XED_EXCEPTION_AMX_E1, + XED_EXCEPTION_AMX_E2, + XED_EXCEPTION_AMX_E3, + XED_EXCEPTION_AMX_E4, + XED_EXCEPTION_AMX_E5, + XED_EXCEPTION_AMX_E6, + XED_EXCEPTION_AVX512_E1, + XED_EXCEPTION_AVX512_E10, + XED_EXCEPTION_AVX512_E10NF, + XED_EXCEPTION_AVX512_E11, + XED_EXCEPTION_AVX512_E12, + XED_EXCEPTION_AVX512_E12NP, + XED_EXCEPTION_AVX512_E1NF, + XED_EXCEPTION_AVX512_E2, + XED_EXCEPTION_AVX512_E3, + XED_EXCEPTION_AVX512_E3NF, + XED_EXCEPTION_AVX512_E4, + XED_EXCEPTION_AVX512_E4NF, + XED_EXCEPTION_AVX512_E5, + XED_EXCEPTION_AVX512_E5NF, + XED_EXCEPTION_AVX512_E6, + XED_EXCEPTION_AVX512_E6NF, + XED_EXCEPTION_AVX512_E7NM, + XED_EXCEPTION_AVX512_E7NM128, + XED_EXCEPTION_AVX512_E9NF, + XED_EXCEPTION_AVX512_K20, + XED_EXCEPTION_AVX512_K21, + XED_EXCEPTION_AVX_TYPE_1, + XED_EXCEPTION_AVX_TYPE_11, + XED_EXCEPTION_AVX_TYPE_12, + XED_EXCEPTION_AVX_TYPE_2, + XED_EXCEPTION_AVX_TYPE_2D, + XED_EXCEPTION_AVX_TYPE_3, + XED_EXCEPTION_AVX_TYPE_4, + XED_EXCEPTION_AVX_TYPE_4M, + XED_EXCEPTION_AVX_TYPE_5, + XED_EXCEPTION_AVX_TYPE_5L, + XED_EXCEPTION_AVX_TYPE_6, + XED_EXCEPTION_AVX_TYPE_7, + XED_EXCEPTION_AVX_TYPE_8, + XED_EXCEPTION_MMX_FP, + XED_EXCEPTION_MMX_FP_16ALIGN, + XED_EXCEPTION_MMX_MEM, + XED_EXCEPTION_MMX_NOFP, + XED_EXCEPTION_MMX_NOFP2, + XED_EXCEPTION_MMX_NOMEM, + XED_EXCEPTION_SSE_TYPE_1, + XED_EXCEPTION_SSE_TYPE_2, + XED_EXCEPTION_SSE_TYPE_2D, + XED_EXCEPTION_SSE_TYPE_3, + XED_EXCEPTION_SSE_TYPE_4, + XED_EXCEPTION_SSE_TYPE_4M, + XED_EXCEPTION_SSE_TYPE_5, + XED_EXCEPTION_SSE_TYPE_7, + XED_EXCEPTION_LAST +} xed_exception_enum_t; + +/// This converts strings to #xed_exception_enum_t types. +/// @param s A C-string. +/// @return #xed_exception_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_exception_enum_t str2xed_exception_enum_t(const char* s); +/// This converts strings to #xed_exception_enum_t types. +/// @param p An enumeration element of type xed_exception_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_exception_enum_t2str(const xed_exception_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_exception_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_exception_enum_t xed_exception_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-exception-enum.txt b/CodeVirtualizer/build/obj/xed-exception-enum.txt new file mode 100644 index 0000000..4144f4f --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-exception-enum.txt @@ -0,0 +1,85 @@ +# @file xed-exception-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-exception-enum.c +hfn xed-exception-enum.h +typename xed_exception_enum_t +prefix XED_EXCEPTION_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +AMX_E1 +AMX_E2 +AMX_E3 +AMX_E4 +AMX_E5 +AMX_E6 +AVX512_E1 +AVX512_E10 +AVX512_E10NF +AVX512_E11 +AVX512_E12 +AVX512_E12NP +AVX512_E1NF +AVX512_E2 +AVX512_E3 +AVX512_E3NF +AVX512_E4 +AVX512_E4NF +AVX512_E5 +AVX512_E5NF +AVX512_E6 +AVX512_E6NF +AVX512_E7NM +AVX512_E7NM128 +AVX512_E9NF +AVX512_K20 +AVX512_K21 +AVX_TYPE_1 +AVX_TYPE_11 +AVX_TYPE_12 +AVX_TYPE_2 +AVX_TYPE_2D +AVX_TYPE_3 +AVX_TYPE_4 +AVX_TYPE_4M +AVX_TYPE_5 +AVX_TYPE_5L +AVX_TYPE_6 +AVX_TYPE_7 +AVX_TYPE_8 +MMX_FP +MMX_FP_16ALIGN +MMX_MEM +MMX_NOFP +MMX_NOFP2 +MMX_NOMEM +SSE_TYPE_1 +SSE_TYPE_2 +SSE_TYPE_2D +SSE_TYPE_3 +SSE_TYPE_4 +SSE_TYPE_4M +SSE_TYPE_5 +SSE_TYPE_7 diff --git a/CodeVirtualizer/build/obj/xed-extension-enum.c b/CodeVirtualizer/build/obj/xed-extension-enum.c new file mode 100644 index 0000000..07b1bc7 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-extension-enum.c @@ -0,0 +1,236 @@ +/// @file xed-extension-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-extension-enum.h" + +typedef struct { + const char* name; + xed_extension_enum_t value; +} name_table_xed_extension_enum_t; +static const name_table_xed_extension_enum_t name_array_xed_extension_enum_t[] = { +{"INVALID", XED_EXTENSION_INVALID}, +{"3DNOW", XED_EXTENSION_3DNOW}, +{"3DNOW_PREFETCH", XED_EXTENSION_3DNOW_PREFETCH}, +{"ADOX_ADCX", XED_EXTENSION_ADOX_ADCX}, +{"AES", XED_EXTENSION_AES}, +{"AMD_INVLPGB", XED_EXTENSION_AMD_INVLPGB}, +{"AMX_BF16", XED_EXTENSION_AMX_BF16}, +{"AMX_INT8", XED_EXTENSION_AMX_INT8}, +{"AMX_TILE", XED_EXTENSION_AMX_TILE}, +{"AVX", XED_EXTENSION_AVX}, +{"AVX2", XED_EXTENSION_AVX2}, +{"AVX2GATHER", XED_EXTENSION_AVX2GATHER}, +{"AVX512EVEX", XED_EXTENSION_AVX512EVEX}, +{"AVX512VEX", XED_EXTENSION_AVX512VEX}, +{"AVXAES", XED_EXTENSION_AVXAES}, +{"AVX_VNNI", XED_EXTENSION_AVX_VNNI}, +{"BASE", XED_EXTENSION_BASE}, +{"BMI1", XED_EXTENSION_BMI1}, +{"BMI2", XED_EXTENSION_BMI2}, +{"CET", XED_EXTENSION_CET}, +{"CLDEMOTE", XED_EXTENSION_CLDEMOTE}, +{"CLFLUSHOPT", XED_EXTENSION_CLFLUSHOPT}, +{"CLFSH", XED_EXTENSION_CLFSH}, +{"CLWB", XED_EXTENSION_CLWB}, +{"CLZERO", XED_EXTENSION_CLZERO}, +{"ENQCMD", XED_EXTENSION_ENQCMD}, +{"F16C", XED_EXTENSION_F16C}, +{"FMA", XED_EXTENSION_FMA}, +{"FMA4", XED_EXTENSION_FMA4}, +{"GFNI", XED_EXTENSION_GFNI}, +{"HRESET", XED_EXTENSION_HRESET}, +{"INVPCID", XED_EXTENSION_INVPCID}, +{"KEYLOCKER", XED_EXTENSION_KEYLOCKER}, +{"KEYLOCKER_WIDE", XED_EXTENSION_KEYLOCKER_WIDE}, +{"LONGMODE", XED_EXTENSION_LONGMODE}, +{"LZCNT", XED_EXTENSION_LZCNT}, +{"MCOMMIT", XED_EXTENSION_MCOMMIT}, +{"MMX", XED_EXTENSION_MMX}, +{"MONITOR", XED_EXTENSION_MONITOR}, +{"MONITORX", XED_EXTENSION_MONITORX}, +{"MOVBE", XED_EXTENSION_MOVBE}, +{"MOVDIR", XED_EXTENSION_MOVDIR}, +{"MPX", XED_EXTENSION_MPX}, +{"PAUSE", XED_EXTENSION_PAUSE}, +{"PCLMULQDQ", XED_EXTENSION_PCLMULQDQ}, +{"PCONFIG", XED_EXTENSION_PCONFIG}, +{"PKU", XED_EXTENSION_PKU}, +{"PREFETCHWT1", XED_EXTENSION_PREFETCHWT1}, +{"PTWRITE", XED_EXTENSION_PTWRITE}, +{"RDPID", XED_EXTENSION_RDPID}, +{"RDPRU", XED_EXTENSION_RDPRU}, +{"RDRAND", XED_EXTENSION_RDRAND}, +{"RDSEED", XED_EXTENSION_RDSEED}, +{"RDTSCP", XED_EXTENSION_RDTSCP}, +{"RDWRFSGS", XED_EXTENSION_RDWRFSGS}, +{"RTM", XED_EXTENSION_RTM}, +{"SERIALIZE", XED_EXTENSION_SERIALIZE}, +{"SGX", XED_EXTENSION_SGX}, +{"SGX_ENCLV", XED_EXTENSION_SGX_ENCLV}, +{"SHA", XED_EXTENSION_SHA}, +{"SMAP", XED_EXTENSION_SMAP}, +{"SMX", XED_EXTENSION_SMX}, +{"SNP", XED_EXTENSION_SNP}, +{"SSE", XED_EXTENSION_SSE}, +{"SSE2", XED_EXTENSION_SSE2}, +{"SSE3", XED_EXTENSION_SSE3}, +{"SSE4", XED_EXTENSION_SSE4}, +{"SSE4A", XED_EXTENSION_SSE4A}, +{"SSSE3", XED_EXTENSION_SSSE3}, +{"SVM", XED_EXTENSION_SVM}, +{"TBM", XED_EXTENSION_TBM}, +{"TDX", XED_EXTENSION_TDX}, +{"TSX_LDTRK", XED_EXTENSION_TSX_LDTRK}, +{"UINTR", XED_EXTENSION_UINTR}, +{"VAES", XED_EXTENSION_VAES}, +{"VIA_PADLOCK_AES", XED_EXTENSION_VIA_PADLOCK_AES}, +{"VIA_PADLOCK_MONTMUL", XED_EXTENSION_VIA_PADLOCK_MONTMUL}, +{"VIA_PADLOCK_RNG", XED_EXTENSION_VIA_PADLOCK_RNG}, +{"VIA_PADLOCK_SHA", XED_EXTENSION_VIA_PADLOCK_SHA}, +{"VMFUNC", XED_EXTENSION_VMFUNC}, +{"VPCLMULQDQ", XED_EXTENSION_VPCLMULQDQ}, +{"VTX", XED_EXTENSION_VTX}, +{"WAITPKG", XED_EXTENSION_WAITPKG}, +{"WBNOINVD", XED_EXTENSION_WBNOINVD}, +{"X87", XED_EXTENSION_X87}, +{"XOP", XED_EXTENSION_XOP}, +{"XSAVE", XED_EXTENSION_XSAVE}, +{"XSAVEC", XED_EXTENSION_XSAVEC}, +{"XSAVEOPT", XED_EXTENSION_XSAVEOPT}, +{"XSAVES", XED_EXTENSION_XSAVES}, +{"LAST", XED_EXTENSION_LAST}, +{0, XED_EXTENSION_LAST}, +}; + + +xed_extension_enum_t str2xed_extension_enum_t(const char* s) +{ + const name_table_xed_extension_enum_t* p = name_array_xed_extension_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_EXTENSION_INVALID; +} + + +const char* xed_extension_enum_t2str(const xed_extension_enum_t p) +{ + xed_extension_enum_t type_idx = p; + if ( p > XED_EXTENSION_LAST) type_idx = XED_EXTENSION_LAST; + return name_array_xed_extension_enum_t[type_idx].name; +} + +xed_extension_enum_t xed_extension_enum_t_last(void) { + return XED_EXTENSION_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_EXTENSION_INVALID: + case XED_EXTENSION_3DNOW: + case XED_EXTENSION_3DNOW_PREFETCH: + case XED_EXTENSION_ADOX_ADCX: + case XED_EXTENSION_AES: + case XED_EXTENSION_AMD_INVLPGB: + case XED_EXTENSION_AMX_BF16: + case XED_EXTENSION_AMX_INT8: + case XED_EXTENSION_AMX_TILE: + case XED_EXTENSION_AVX: + case XED_EXTENSION_AVX2: + case XED_EXTENSION_AVX2GATHER: + case XED_EXTENSION_AVX512EVEX: + case XED_EXTENSION_AVX512VEX: + case XED_EXTENSION_AVXAES: + case XED_EXTENSION_AVX_VNNI: + case XED_EXTENSION_BASE: + case XED_EXTENSION_BMI1: + case XED_EXTENSION_BMI2: + case XED_EXTENSION_CET: + case XED_EXTENSION_CLDEMOTE: + case XED_EXTENSION_CLFLUSHOPT: + case XED_EXTENSION_CLFSH: + case XED_EXTENSION_CLWB: + case XED_EXTENSION_CLZERO: + case XED_EXTENSION_ENQCMD: + case XED_EXTENSION_F16C: + case XED_EXTENSION_FMA: + case XED_EXTENSION_FMA4: + case XED_EXTENSION_GFNI: + case XED_EXTENSION_HRESET: + case XED_EXTENSION_INVPCID: + case XED_EXTENSION_KEYLOCKER: + case XED_EXTENSION_KEYLOCKER_WIDE: + case XED_EXTENSION_LONGMODE: + case XED_EXTENSION_LZCNT: + case XED_EXTENSION_MCOMMIT: + case XED_EXTENSION_MMX: + case XED_EXTENSION_MONITOR: + case XED_EXTENSION_MONITORX: + case XED_EXTENSION_MOVBE: + case XED_EXTENSION_MOVDIR: + case XED_EXTENSION_MPX: + case XED_EXTENSION_PAUSE: + case XED_EXTENSION_PCLMULQDQ: + case XED_EXTENSION_PCONFIG: + case XED_EXTENSION_PKU: + case XED_EXTENSION_PREFETCHWT1: + case XED_EXTENSION_PTWRITE: + case XED_EXTENSION_RDPID: + case XED_EXTENSION_RDPRU: + case XED_EXTENSION_RDRAND: + case XED_EXTENSION_RDSEED: + case XED_EXTENSION_RDTSCP: + case XED_EXTENSION_RDWRFSGS: + case XED_EXTENSION_RTM: + case XED_EXTENSION_SERIALIZE: + case XED_EXTENSION_SGX: + case XED_EXTENSION_SGX_ENCLV: + case XED_EXTENSION_SHA: + case XED_EXTENSION_SMAP: + case XED_EXTENSION_SMX: + case XED_EXTENSION_SNP: + case XED_EXTENSION_SSE: + case XED_EXTENSION_SSE2: + case XED_EXTENSION_SSE3: + case XED_EXTENSION_SSE4: + case XED_EXTENSION_SSE4A: + case XED_EXTENSION_SSSE3: + case XED_EXTENSION_SVM: + case XED_EXTENSION_TBM: + case XED_EXTENSION_TDX: + case XED_EXTENSION_TSX_LDTRK: + case XED_EXTENSION_UINTR: + case XED_EXTENSION_VAES: + case XED_EXTENSION_VIA_PADLOCK_AES: + case XED_EXTENSION_VIA_PADLOCK_MONTMUL: + case XED_EXTENSION_VIA_PADLOCK_RNG: + case XED_EXTENSION_VIA_PADLOCK_SHA: + case XED_EXTENSION_VMFUNC: + case XED_EXTENSION_VPCLMULQDQ: + case XED_EXTENSION_VTX: + case XED_EXTENSION_WAITPKG: + case XED_EXTENSION_WBNOINVD: + case XED_EXTENSION_X87: + case XED_EXTENSION_XOP: + case XED_EXTENSION_XSAVE: + case XED_EXTENSION_XSAVEC: + case XED_EXTENSION_XSAVEOPT: + case XED_EXTENSION_XSAVES: + case XED_EXTENSION_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-extension-enum.h b/CodeVirtualizer/build/obj/xed-extension-enum.h new file mode 100644 index 0000000..4839704 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-extension-enum.h @@ -0,0 +1,209 @@ +/// @file xed-extension-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_EXTENSION_ENUM_H) +# define XED_EXTENSION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_EXTENSION_INVALID_DEFINED 1 +#define XED_EXTENSION_3DNOW_DEFINED 1 +#define XED_EXTENSION_3DNOW_PREFETCH_DEFINED 1 +#define XED_EXTENSION_ADOX_ADCX_DEFINED 1 +#define XED_EXTENSION_AES_DEFINED 1 +#define XED_EXTENSION_AMD_INVLPGB_DEFINED 1 +#define XED_EXTENSION_AMX_BF16_DEFINED 1 +#define XED_EXTENSION_AMX_INT8_DEFINED 1 +#define XED_EXTENSION_AMX_TILE_DEFINED 1 +#define XED_EXTENSION_AVX_DEFINED 1 +#define XED_EXTENSION_AVX2_DEFINED 1 +#define XED_EXTENSION_AVX2GATHER_DEFINED 1 +#define XED_EXTENSION_AVX512EVEX_DEFINED 1 +#define XED_EXTENSION_AVX512VEX_DEFINED 1 +#define XED_EXTENSION_AVXAES_DEFINED 1 +#define XED_EXTENSION_AVX_VNNI_DEFINED 1 +#define XED_EXTENSION_BASE_DEFINED 1 +#define XED_EXTENSION_BMI1_DEFINED 1 +#define XED_EXTENSION_BMI2_DEFINED 1 +#define XED_EXTENSION_CET_DEFINED 1 +#define XED_EXTENSION_CLDEMOTE_DEFINED 1 +#define XED_EXTENSION_CLFLUSHOPT_DEFINED 1 +#define XED_EXTENSION_CLFSH_DEFINED 1 +#define XED_EXTENSION_CLWB_DEFINED 1 +#define XED_EXTENSION_CLZERO_DEFINED 1 +#define XED_EXTENSION_ENQCMD_DEFINED 1 +#define XED_EXTENSION_F16C_DEFINED 1 +#define XED_EXTENSION_FMA_DEFINED 1 +#define XED_EXTENSION_FMA4_DEFINED 1 +#define XED_EXTENSION_GFNI_DEFINED 1 +#define XED_EXTENSION_HRESET_DEFINED 1 +#define XED_EXTENSION_INVPCID_DEFINED 1 +#define XED_EXTENSION_KEYLOCKER_DEFINED 1 +#define XED_EXTENSION_KEYLOCKER_WIDE_DEFINED 1 +#define XED_EXTENSION_LONGMODE_DEFINED 1 +#define XED_EXTENSION_LZCNT_DEFINED 1 +#define XED_EXTENSION_MCOMMIT_DEFINED 1 +#define XED_EXTENSION_MMX_DEFINED 1 +#define XED_EXTENSION_MONITOR_DEFINED 1 +#define XED_EXTENSION_MONITORX_DEFINED 1 +#define XED_EXTENSION_MOVBE_DEFINED 1 +#define XED_EXTENSION_MOVDIR_DEFINED 1 +#define XED_EXTENSION_MPX_DEFINED 1 +#define XED_EXTENSION_PAUSE_DEFINED 1 +#define XED_EXTENSION_PCLMULQDQ_DEFINED 1 +#define XED_EXTENSION_PCONFIG_DEFINED 1 +#define XED_EXTENSION_PKU_DEFINED 1 +#define XED_EXTENSION_PREFETCHWT1_DEFINED 1 +#define XED_EXTENSION_PTWRITE_DEFINED 1 +#define XED_EXTENSION_RDPID_DEFINED 1 +#define XED_EXTENSION_RDPRU_DEFINED 1 +#define XED_EXTENSION_RDRAND_DEFINED 1 +#define XED_EXTENSION_RDSEED_DEFINED 1 +#define XED_EXTENSION_RDTSCP_DEFINED 1 +#define XED_EXTENSION_RDWRFSGS_DEFINED 1 +#define XED_EXTENSION_RTM_DEFINED 1 +#define XED_EXTENSION_SERIALIZE_DEFINED 1 +#define XED_EXTENSION_SGX_DEFINED 1 +#define XED_EXTENSION_SGX_ENCLV_DEFINED 1 +#define XED_EXTENSION_SHA_DEFINED 1 +#define XED_EXTENSION_SMAP_DEFINED 1 +#define XED_EXTENSION_SMX_DEFINED 1 +#define XED_EXTENSION_SNP_DEFINED 1 +#define XED_EXTENSION_SSE_DEFINED 1 +#define XED_EXTENSION_SSE2_DEFINED 1 +#define XED_EXTENSION_SSE3_DEFINED 1 +#define XED_EXTENSION_SSE4_DEFINED 1 +#define XED_EXTENSION_SSE4A_DEFINED 1 +#define XED_EXTENSION_SSSE3_DEFINED 1 +#define XED_EXTENSION_SVM_DEFINED 1 +#define XED_EXTENSION_TBM_DEFINED 1 +#define XED_EXTENSION_TDX_DEFINED 1 +#define XED_EXTENSION_TSX_LDTRK_DEFINED 1 +#define XED_EXTENSION_UINTR_DEFINED 1 +#define XED_EXTENSION_VAES_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_AES_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_MONTMUL_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_RNG_DEFINED 1 +#define XED_EXTENSION_VIA_PADLOCK_SHA_DEFINED 1 +#define XED_EXTENSION_VMFUNC_DEFINED 1 +#define XED_EXTENSION_VPCLMULQDQ_DEFINED 1 +#define XED_EXTENSION_VTX_DEFINED 1 +#define XED_EXTENSION_WAITPKG_DEFINED 1 +#define XED_EXTENSION_WBNOINVD_DEFINED 1 +#define XED_EXTENSION_X87_DEFINED 1 +#define XED_EXTENSION_XOP_DEFINED 1 +#define XED_EXTENSION_XSAVE_DEFINED 1 +#define XED_EXTENSION_XSAVEC_DEFINED 1 +#define XED_EXTENSION_XSAVEOPT_DEFINED 1 +#define XED_EXTENSION_XSAVES_DEFINED 1 +#define XED_EXTENSION_LAST_DEFINED 1 +typedef enum { + XED_EXTENSION_INVALID, + XED_EXTENSION_3DNOW, + XED_EXTENSION_3DNOW_PREFETCH, + XED_EXTENSION_ADOX_ADCX, + XED_EXTENSION_AES, + XED_EXTENSION_AMD_INVLPGB, + XED_EXTENSION_AMX_BF16, + XED_EXTENSION_AMX_INT8, + XED_EXTENSION_AMX_TILE, + XED_EXTENSION_AVX, + XED_EXTENSION_AVX2, + XED_EXTENSION_AVX2GATHER, + XED_EXTENSION_AVX512EVEX, + XED_EXTENSION_AVX512VEX, + XED_EXTENSION_AVXAES, + XED_EXTENSION_AVX_VNNI, + XED_EXTENSION_BASE, + XED_EXTENSION_BMI1, + XED_EXTENSION_BMI2, + XED_EXTENSION_CET, + XED_EXTENSION_CLDEMOTE, + XED_EXTENSION_CLFLUSHOPT, + XED_EXTENSION_CLFSH, + XED_EXTENSION_CLWB, + XED_EXTENSION_CLZERO, + XED_EXTENSION_ENQCMD, + XED_EXTENSION_F16C, + XED_EXTENSION_FMA, + XED_EXTENSION_FMA4, + XED_EXTENSION_GFNI, + XED_EXTENSION_HRESET, + XED_EXTENSION_INVPCID, + XED_EXTENSION_KEYLOCKER, + XED_EXTENSION_KEYLOCKER_WIDE, + XED_EXTENSION_LONGMODE, + XED_EXTENSION_LZCNT, + XED_EXTENSION_MCOMMIT, + XED_EXTENSION_MMX, + XED_EXTENSION_MONITOR, + XED_EXTENSION_MONITORX, + XED_EXTENSION_MOVBE, + XED_EXTENSION_MOVDIR, + XED_EXTENSION_MPX, + XED_EXTENSION_PAUSE, + XED_EXTENSION_PCLMULQDQ, + XED_EXTENSION_PCONFIG, + XED_EXTENSION_PKU, + XED_EXTENSION_PREFETCHWT1, + XED_EXTENSION_PTWRITE, + XED_EXTENSION_RDPID, + XED_EXTENSION_RDPRU, + XED_EXTENSION_RDRAND, + XED_EXTENSION_RDSEED, + XED_EXTENSION_RDTSCP, + XED_EXTENSION_RDWRFSGS, + XED_EXTENSION_RTM, + XED_EXTENSION_SERIALIZE, + XED_EXTENSION_SGX, + XED_EXTENSION_SGX_ENCLV, + XED_EXTENSION_SHA, + XED_EXTENSION_SMAP, + XED_EXTENSION_SMX, + XED_EXTENSION_SNP, + XED_EXTENSION_SSE, + XED_EXTENSION_SSE2, + XED_EXTENSION_SSE3, + XED_EXTENSION_SSE4, + XED_EXTENSION_SSE4A, + XED_EXTENSION_SSSE3, + XED_EXTENSION_SVM, + XED_EXTENSION_TBM, + XED_EXTENSION_TDX, + XED_EXTENSION_TSX_LDTRK, + XED_EXTENSION_UINTR, + XED_EXTENSION_VAES, + XED_EXTENSION_VIA_PADLOCK_AES, + XED_EXTENSION_VIA_PADLOCK_MONTMUL, + XED_EXTENSION_VIA_PADLOCK_RNG, + XED_EXTENSION_VIA_PADLOCK_SHA, + XED_EXTENSION_VMFUNC, + XED_EXTENSION_VPCLMULQDQ, + XED_EXTENSION_VTX, + XED_EXTENSION_WAITPKG, + XED_EXTENSION_WBNOINVD, + XED_EXTENSION_X87, + XED_EXTENSION_XOP, + XED_EXTENSION_XSAVE, + XED_EXTENSION_XSAVEC, + XED_EXTENSION_XSAVEOPT, + XED_EXTENSION_XSAVES, + XED_EXTENSION_LAST +} xed_extension_enum_t; + +/// This converts strings to #xed_extension_enum_t types. +/// @param s A C-string. +/// @return #xed_extension_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_extension_enum_t str2xed_extension_enum_t(const char* s); +/// This converts strings to #xed_extension_enum_t types. +/// @param p An enumeration element of type xed_extension_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_extension_enum_t2str(const xed_extension_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_extension_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_extension_enum_t xed_extension_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-extension-enum.txt b/CodeVirtualizer/build/obj/xed-extension-enum.txt new file mode 100644 index 0000000..b2350c7 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-extension-enum.txt @@ -0,0 +1,120 @@ +# @file xed-extension-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-extension-enum.c +hfn xed-extension-enum.h +typename xed_extension_enum_t +prefix XED_EXTENSION_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +3DNOW +3DNOW_PREFETCH +ADOX_ADCX +AES +AMD_INVLPGB +AMX_BF16 +AMX_INT8 +AMX_TILE +AVX +AVX2 +AVX2GATHER +AVX512EVEX +AVX512VEX +AVXAES +AVX_VNNI +BASE +BMI1 +BMI2 +CET +CLDEMOTE +CLFLUSHOPT +CLFSH +CLWB +CLZERO +ENQCMD +F16C +FMA +FMA4 +GFNI +HRESET +INVPCID +KEYLOCKER +KEYLOCKER_WIDE +LONGMODE +LZCNT +MCOMMIT +MMX +MONITOR +MONITORX +MOVBE +MOVDIR +MPX +PAUSE +PCLMULQDQ +PCONFIG +PKU +PREFETCHWT1 +PTWRITE +RDPID +RDPRU +RDRAND +RDSEED +RDTSCP +RDWRFSGS +RTM +SERIALIZE +SGX +SGX_ENCLV +SHA +SMAP +SMX +SNP +SSE +SSE2 +SSE3 +SSE4 +SSE4A +SSSE3 +SVM +TBM +TDX +TSX_LDTRK +UINTR +VAES +VIA_PADLOCK_AES +VIA_PADLOCK_MONTMUL +VIA_PADLOCK_RNG +VIA_PADLOCK_SHA +VMFUNC +VPCLMULQDQ +VTX +WAITPKG +WBNOINVD +X87 +XOP +XSAVE +XSAVEC +XSAVEOPT +XSAVES diff --git a/CodeVirtualizer/build/obj/xed-flag-action-enum.c b/CodeVirtualizer/build/obj/xed-flag-action-enum.c new file mode 100644 index 0000000..b63ed60 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flag-action-enum.c @@ -0,0 +1,72 @@ +/// @file xed-flag-action-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-flag-action-enum.h" + +typedef struct { + const char* name; + xed_flag_action_enum_t value; +} name_table_xed_flag_action_enum_t; +static const name_table_xed_flag_action_enum_t name_array_xed_flag_action_enum_t[] = { +{"INVALID", XED_FLAG_ACTION_INVALID}, +{"u", XED_FLAG_ACTION_u}, +{"tst", XED_FLAG_ACTION_tst}, +{"mod", XED_FLAG_ACTION_mod}, +{"0", XED_FLAG_ACTION_0}, +{"pop", XED_FLAG_ACTION_pop}, +{"ah", XED_FLAG_ACTION_ah}, +{"1", XED_FLAG_ACTION_1}, +{"LAST", XED_FLAG_ACTION_LAST}, +{0, XED_FLAG_ACTION_LAST}, +}; + + +xed_flag_action_enum_t str2xed_flag_action_enum_t(const char* s) +{ + const name_table_xed_flag_action_enum_t* p = name_array_xed_flag_action_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_FLAG_ACTION_INVALID; +} + + +const char* xed_flag_action_enum_t2str(const xed_flag_action_enum_t p) +{ + xed_flag_action_enum_t type_idx = p; + if ( p > XED_FLAG_ACTION_LAST) type_idx = XED_FLAG_ACTION_LAST; + return name_array_xed_flag_action_enum_t[type_idx].name; +} + +xed_flag_action_enum_t xed_flag_action_enum_t_last(void) { + return XED_FLAG_ACTION_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_FLAG_ACTION_INVALID: + case XED_FLAG_ACTION_u: + case XED_FLAG_ACTION_tst: + case XED_FLAG_ACTION_mod: + case XED_FLAG_ACTION_0: + case XED_FLAG_ACTION_pop: + case XED_FLAG_ACTION_ah: + case XED_FLAG_ACTION_1: + case XED_FLAG_ACTION_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-flag-action-enum.h b/CodeVirtualizer/build/obj/xed-flag-action-enum.h new file mode 100644 index 0000000..627e5fb --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flag-action-enum.h @@ -0,0 +1,45 @@ +/// @file xed-flag-action-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_FLAG_ACTION_ENUM_H) +# define XED_FLAG_ACTION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_FLAG_ACTION_INVALID_DEFINED 1 +#define XED_FLAG_ACTION_u_DEFINED 1 +#define XED_FLAG_ACTION_tst_DEFINED 1 +#define XED_FLAG_ACTION_mod_DEFINED 1 +#define XED_FLAG_ACTION_0_DEFINED 1 +#define XED_FLAG_ACTION_pop_DEFINED 1 +#define XED_FLAG_ACTION_ah_DEFINED 1 +#define XED_FLAG_ACTION_1_DEFINED 1 +#define XED_FLAG_ACTION_LAST_DEFINED 1 +typedef enum { + XED_FLAG_ACTION_INVALID, + XED_FLAG_ACTION_u, ///< undefined (treated as a write) + XED_FLAG_ACTION_tst, ///< test (read) + XED_FLAG_ACTION_mod, ///< modification (write) + XED_FLAG_ACTION_0, ///< value will be zero (write) + XED_FLAG_ACTION_pop, ///< value comes from the stack (write) + XED_FLAG_ACTION_ah, ///< value comes from AH (write) + XED_FLAG_ACTION_1, ///< value will be 1 (write) + XED_FLAG_ACTION_LAST +} xed_flag_action_enum_t; + +/// This converts strings to #xed_flag_action_enum_t types. +/// @param s A C-string. +/// @return #xed_flag_action_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_action_enum_t str2xed_flag_action_enum_t(const char* s); +/// This converts strings to #xed_flag_action_enum_t types. +/// @param p An enumeration element of type xed_flag_action_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_flag_action_enum_t2str(const xed_flag_action_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_flag_action_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_action_enum_t xed_flag_action_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-flag-enum.c b/CodeVirtualizer/build/obj/xed-flag-enum.c new file mode 100644 index 0000000..fe93861 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flag-enum.c @@ -0,0 +1,100 @@ +/// @file xed-flag-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-flag-enum.h" + +typedef struct { + const char* name; + xed_flag_enum_t value; +} name_table_xed_flag_enum_t; +static const name_table_xed_flag_enum_t name_array_xed_flag_enum_t[] = { +{"INVALID", XED_FLAG_INVALID}, +{"of", XED_FLAG_of}, +{"sf", XED_FLAG_sf}, +{"zf", XED_FLAG_zf}, +{"af", XED_FLAG_af}, +{"pf", XED_FLAG_pf}, +{"cf", XED_FLAG_cf}, +{"df", XED_FLAG_df}, +{"vif", XED_FLAG_vif}, +{"iopl", XED_FLAG_iopl}, +{"if", XED_FLAG_if}, +{"ac", XED_FLAG_ac}, +{"vm", XED_FLAG_vm}, +{"rf", XED_FLAG_rf}, +{"nt", XED_FLAG_nt}, +{"tf", XED_FLAG_tf}, +{"id", XED_FLAG_id}, +{"vip", XED_FLAG_vip}, +{"fc0", XED_FLAG_fc0}, +{"fc1", XED_FLAG_fc1}, +{"fc2", XED_FLAG_fc2}, +{"fc3", XED_FLAG_fc3}, +{"LAST", XED_FLAG_LAST}, +{0, XED_FLAG_LAST}, +}; + + +xed_flag_enum_t str2xed_flag_enum_t(const char* s) +{ + const name_table_xed_flag_enum_t* p = name_array_xed_flag_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_FLAG_INVALID; +} + + +const char* xed_flag_enum_t2str(const xed_flag_enum_t p) +{ + xed_flag_enum_t type_idx = p; + if ( p > XED_FLAG_LAST) type_idx = XED_FLAG_LAST; + return name_array_xed_flag_enum_t[type_idx].name; +} + +xed_flag_enum_t xed_flag_enum_t_last(void) { + return XED_FLAG_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_FLAG_INVALID: + case XED_FLAG_of: + case XED_FLAG_sf: + case XED_FLAG_zf: + case XED_FLAG_af: + case XED_FLAG_pf: + case XED_FLAG_cf: + case XED_FLAG_df: + case XED_FLAG_vif: + case XED_FLAG_iopl: + case XED_FLAG_if: + case XED_FLAG_ac: + case XED_FLAG_vm: + case XED_FLAG_rf: + case XED_FLAG_nt: + case XED_FLAG_tf: + case XED_FLAG_id: + case XED_FLAG_vip: + case XED_FLAG_fc0: + case XED_FLAG_fc1: + case XED_FLAG_fc2: + case XED_FLAG_fc3: + case XED_FLAG_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-flag-enum.h b/CodeVirtualizer/build/obj/xed-flag-enum.h new file mode 100644 index 0000000..4e767e0 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flag-enum.h @@ -0,0 +1,73 @@ +/// @file xed-flag-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_FLAG_ENUM_H) +# define XED_FLAG_ENUM_H +#include "xed-common-hdrs.h" +#define XED_FLAG_INVALID_DEFINED 1 +#define XED_FLAG_of_DEFINED 1 +#define XED_FLAG_sf_DEFINED 1 +#define XED_FLAG_zf_DEFINED 1 +#define XED_FLAG_af_DEFINED 1 +#define XED_FLAG_pf_DEFINED 1 +#define XED_FLAG_cf_DEFINED 1 +#define XED_FLAG_df_DEFINED 1 +#define XED_FLAG_vif_DEFINED 1 +#define XED_FLAG_iopl_DEFINED 1 +#define XED_FLAG_if_DEFINED 1 +#define XED_FLAG_ac_DEFINED 1 +#define XED_FLAG_vm_DEFINED 1 +#define XED_FLAG_rf_DEFINED 1 +#define XED_FLAG_nt_DEFINED 1 +#define XED_FLAG_tf_DEFINED 1 +#define XED_FLAG_id_DEFINED 1 +#define XED_FLAG_vip_DEFINED 1 +#define XED_FLAG_fc0_DEFINED 1 +#define XED_FLAG_fc1_DEFINED 1 +#define XED_FLAG_fc2_DEFINED 1 +#define XED_FLAG_fc3_DEFINED 1 +#define XED_FLAG_LAST_DEFINED 1 +typedef enum { + XED_FLAG_INVALID, + XED_FLAG_of, ///<< overflow flag + XED_FLAG_sf, ///< sign flag + XED_FLAG_zf, ///< zero flag + XED_FLAG_af, ///< auxiliary flag + XED_FLAG_pf, ///< parity flag + XED_FLAG_cf, ///< carry flag + XED_FLAG_df, ///< direction flag + XED_FLAG_vif, ///< virtual interrupt flag + XED_FLAG_iopl, ///< I/O privilege level + XED_FLAG_if, ///< interrupt flag + XED_FLAG_ac, ///< alignment check + XED_FLAG_vm, ///< virtual-8086 mode + XED_FLAG_rf, ///< resume flag + XED_FLAG_nt, ///< nested task + XED_FLAG_tf, ///< traf flag + XED_FLAG_id, ///< ID flag + XED_FLAG_vip, ///< virtual interrupt pending + XED_FLAG_fc0, ///< x87 FC0 flag + XED_FLAG_fc1, ///< x87 FC1 flag + XED_FLAG_fc2, ///< x87 FC2 flag + XED_FLAG_fc3, ///< x87 FC3 flag + XED_FLAG_LAST +} xed_flag_enum_t; + +/// This converts strings to #xed_flag_enum_t types. +/// @param s A C-string. +/// @return #xed_flag_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_enum_t str2xed_flag_enum_t(const char* s); +/// This converts strings to #xed_flag_enum_t types. +/// @param p An enumeration element of type xed_flag_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_flag_enum_t2str(const xed_flag_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_flag_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_flag_enum_t xed_flag_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-flags-actions.c b/CodeVirtualizer/build/obj/xed-flags-actions.c new file mode 100644 index 0000000..153a177 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flags-actions.c @@ -0,0 +1,498 @@ +/// @file xed-flags-actions.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-flags.h" +const xed_flag_action_t xed_flag_action_table[] = { +/* 0 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 1 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 2 */ { XED_FLAG_fc2,XED_FLAG_ACTION_u }, +/* 3 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 4 */ { XED_FLAG_fc0,XED_FLAG_ACTION_mod }, +/* 5 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 6 */ { XED_FLAG_fc2,XED_FLAG_ACTION_mod }, +/* 7 */ { XED_FLAG_fc3,XED_FLAG_ACTION_mod }, +/* 8 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 9 */ { XED_FLAG_fc1,XED_FLAG_ACTION_u }, +/* 10 */ { XED_FLAG_fc2,XED_FLAG_ACTION_u }, +/* 11 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 12 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 13 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 14 */ { XED_FLAG_fc2,XED_FLAG_ACTION_mod }, +/* 15 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 16 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 17 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 18 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 19 */ { XED_FLAG_fc2,XED_FLAG_ACTION_u }, +/* 20 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 21 */ { XED_FLAG_zf,XED_FLAG_ACTION_tst }, +/* 22 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 23 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 24 */ { XED_FLAG_fc2,XED_FLAG_ACTION_u }, +/* 25 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 26 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 27 */ { XED_FLAG_zf,XED_FLAG_ACTION_tst }, +/* 28 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 29 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 30 */ { XED_FLAG_fc2,XED_FLAG_ACTION_u }, +/* 31 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 32 */ { XED_FLAG_pf,XED_FLAG_ACTION_tst }, +/* 33 */ { XED_FLAG_fc0,XED_FLAG_ACTION_u }, +/* 34 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 35 */ { XED_FLAG_fc2,XED_FLAG_ACTION_u }, +/* 36 */ { XED_FLAG_fc3,XED_FLAG_ACTION_u }, +/* 37 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 38 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 39 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 40 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 41 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 42 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 43 */ { XED_FLAG_fc1,XED_FLAG_ACTION_mod }, +/* 44 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 45 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 46 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 47 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 48 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 49 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 50 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 51 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 52 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 53 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 54 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 55 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 56 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 57 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 58 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 59 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 60 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 61 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 62 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 63 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 64 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 65 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 66 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 67 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 68 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 69 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 70 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 71 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 72 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 73 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 74 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 75 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 76 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 77 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 78 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 79 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 80 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 81 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 82 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 83 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 84 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 85 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 86 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 87 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 88 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 89 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 90 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 91 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 92 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 93 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 94 */ { XED_FLAG_zf,XED_FLAG_ACTION_u }, +/* 95 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 96 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 97 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 98 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 99 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 100 */ { XED_FLAG_zf,XED_FLAG_ACTION_u }, +/* 101 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 102 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 103 */ { XED_FLAG_cf,XED_FLAG_ACTION_u }, +/* 104 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 105 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 106 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 107 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 108 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 109 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 110 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 111 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 112 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 113 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 114 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 115 */ { XED_FLAG_id,XED_FLAG_ACTION_mod }, +/* 116 */ { XED_FLAG_vip,XED_FLAG_ACTION_mod }, +/* 117 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 118 */ { XED_FLAG_ac,XED_FLAG_ACTION_mod }, +/* 119 */ { XED_FLAG_vm,XED_FLAG_ACTION_tst }, +/* 120 */ { XED_FLAG_rf,XED_FLAG_ACTION_mod }, +/* 121 */ { XED_FLAG_nt,XED_FLAG_ACTION_mod }, +/* 122 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 123 */ { XED_FLAG_iopl,XED_FLAG_ACTION_mod }, +/* 124 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 125 */ { XED_FLAG_df,XED_FLAG_ACTION_mod }, +/* 126 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 127 */ { XED_FLAG_tf,XED_FLAG_ACTION_mod }, +/* 128 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 129 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 130 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 131 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 132 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 133 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 134 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 135 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 136 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 137 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 138 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 139 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 140 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 141 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 142 */ { XED_FLAG_af,XED_FLAG_ACTION_tst }, +/* 143 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 144 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 145 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 146 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 147 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 148 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 149 */ { XED_FLAG_zf,XED_FLAG_ACTION_u }, +/* 150 */ { XED_FLAG_af,XED_FLAG_ACTION_tst }, +/* 151 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 152 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 153 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 154 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 155 */ { XED_FLAG_df,XED_FLAG_ACTION_tst }, +/* 156 */ { XED_FLAG_of,XED_FLAG_ACTION_tst }, +/* 157 */ { XED_FLAG_sf,XED_FLAG_ACTION_tst }, +/* 158 */ { XED_FLAG_sf,XED_FLAG_ACTION_tst }, +/* 159 */ { XED_FLAG_of,XED_FLAG_ACTION_tst }, +/* 160 */ { XED_FLAG_sf,XED_FLAG_ACTION_tst }, +/* 161 */ { XED_FLAG_of,XED_FLAG_ACTION_tst }, +/* 162 */ { XED_FLAG_zf,XED_FLAG_ACTION_tst }, +/* 163 */ { XED_FLAG_id,XED_FLAG_ACTION_tst }, +/* 164 */ { XED_FLAG_vip,XED_FLAG_ACTION_tst }, +/* 165 */ { XED_FLAG_vif,XED_FLAG_ACTION_tst }, +/* 166 */ { XED_FLAG_ac,XED_FLAG_ACTION_tst }, +/* 167 */ { XED_FLAG_vm,XED_FLAG_ACTION_tst }, +/* 168 */ { XED_FLAG_rf,XED_FLAG_ACTION_tst }, +/* 169 */ { XED_FLAG_nt,XED_FLAG_ACTION_tst }, +/* 170 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 171 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 172 */ { XED_FLAG_of,XED_FLAG_ACTION_tst }, +/* 173 */ { XED_FLAG_df,XED_FLAG_ACTION_tst }, +/* 174 */ { XED_FLAG_if,XED_FLAG_ACTION_tst }, +/* 175 */ { XED_FLAG_tf,XED_FLAG_ACTION_tst }, +/* 176 */ { XED_FLAG_sf,XED_FLAG_ACTION_tst }, +/* 177 */ { XED_FLAG_zf,XED_FLAG_ACTION_tst }, +/* 178 */ { XED_FLAG_af,XED_FLAG_ACTION_tst }, +/* 179 */ { XED_FLAG_pf,XED_FLAG_ACTION_tst }, +/* 180 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 181 */ { XED_FLAG_id,XED_FLAG_ACTION_pop }, +/* 182 */ { XED_FLAG_vip,XED_FLAG_ACTION_tst }, +/* 183 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 184 */ { XED_FLAG_ac,XED_FLAG_ACTION_pop }, +/* 185 */ { XED_FLAG_vm,XED_FLAG_ACTION_tst }, +/* 186 */ { XED_FLAG_rf,XED_FLAG_ACTION_0 }, +/* 187 */ { XED_FLAG_nt,XED_FLAG_ACTION_pop }, +/* 188 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 189 */ { XED_FLAG_iopl,XED_FLAG_ACTION_pop }, +/* 190 */ { XED_FLAG_of,XED_FLAG_ACTION_pop }, +/* 191 */ { XED_FLAG_df,XED_FLAG_ACTION_pop }, +/* 192 */ { XED_FLAG_if,XED_FLAG_ACTION_pop }, +/* 193 */ { XED_FLAG_tf,XED_FLAG_ACTION_pop }, +/* 194 */ { XED_FLAG_sf,XED_FLAG_ACTION_pop }, +/* 195 */ { XED_FLAG_zf,XED_FLAG_ACTION_pop }, +/* 196 */ { XED_FLAG_af,XED_FLAG_ACTION_pop }, +/* 197 */ { XED_FLAG_pf,XED_FLAG_ACTION_pop }, +/* 198 */ { XED_FLAG_cf,XED_FLAG_ACTION_pop }, +/* 199 */ { XED_FLAG_sf,XED_FLAG_ACTION_ah }, +/* 200 */ { XED_FLAG_zf,XED_FLAG_ACTION_ah }, +/* 201 */ { XED_FLAG_af,XED_FLAG_ACTION_ah }, +/* 202 */ { XED_FLAG_pf,XED_FLAG_ACTION_ah }, +/* 203 */ { XED_FLAG_cf,XED_FLAG_ACTION_ah }, +/* 204 */ { XED_FLAG_sf,XED_FLAG_ACTION_tst }, +/* 205 */ { XED_FLAG_zf,XED_FLAG_ACTION_tst }, +/* 206 */ { XED_FLAG_af,XED_FLAG_ACTION_tst }, +/* 207 */ { XED_FLAG_pf,XED_FLAG_ACTION_tst }, +/* 208 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 209 */ { XED_FLAG_df,XED_FLAG_ACTION_tst }, +/* 210 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 211 */ { XED_FLAG_df,XED_FLAG_ACTION_tst }, +/* 212 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 213 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 214 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 215 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 216 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 217 */ { XED_FLAG_zf,XED_FLAG_ACTION_tst }, +/* 218 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 219 */ { XED_FLAG_ac,XED_FLAG_ACTION_mod }, +/* 220 */ { XED_FLAG_vm,XED_FLAG_ACTION_tst }, +/* 221 */ { XED_FLAG_vm,XED_FLAG_ACTION_mod }, +/* 222 */ { XED_FLAG_rf,XED_FLAG_ACTION_0 }, +/* 223 */ { XED_FLAG_nt,XED_FLAG_ACTION_mod }, +/* 224 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 225 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 226 */ { XED_FLAG_tf,XED_FLAG_ACTION_0 }, +/* 227 */ { XED_FLAG_ac,XED_FLAG_ACTION_mod }, +/* 228 */ { XED_FLAG_vm,XED_FLAG_ACTION_tst }, +/* 229 */ { XED_FLAG_vm,XED_FLAG_ACTION_mod }, +/* 230 */ { XED_FLAG_rf,XED_FLAG_ACTION_0 }, +/* 231 */ { XED_FLAG_nt,XED_FLAG_ACTION_mod }, +/* 232 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 233 */ { XED_FLAG_of,XED_FLAG_ACTION_tst }, +/* 234 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 235 */ { XED_FLAG_tf,XED_FLAG_ACTION_mod }, +/* 236 */ { XED_FLAG_id,XED_FLAG_ACTION_pop }, +/* 237 */ { XED_FLAG_vip,XED_FLAG_ACTION_pop }, +/* 238 */ { XED_FLAG_vif,XED_FLAG_ACTION_pop }, +/* 239 */ { XED_FLAG_ac,XED_FLAG_ACTION_pop }, +/* 240 */ { XED_FLAG_vm,XED_FLAG_ACTION_tst }, +/* 241 */ { XED_FLAG_vm,XED_FLAG_ACTION_pop }, +/* 242 */ { XED_FLAG_rf,XED_FLAG_ACTION_pop }, +/* 243 */ { XED_FLAG_nt,XED_FLAG_ACTION_tst }, +/* 244 */ { XED_FLAG_nt,XED_FLAG_ACTION_pop }, +/* 245 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 246 */ { XED_FLAG_iopl,XED_FLAG_ACTION_pop }, +/* 247 */ { XED_FLAG_of,XED_FLAG_ACTION_pop }, +/* 248 */ { XED_FLAG_df,XED_FLAG_ACTION_pop }, +/* 249 */ { XED_FLAG_if,XED_FLAG_ACTION_pop }, +/* 250 */ { XED_FLAG_tf,XED_FLAG_ACTION_pop }, +/* 251 */ { XED_FLAG_sf,XED_FLAG_ACTION_pop }, +/* 252 */ { XED_FLAG_zf,XED_FLAG_ACTION_pop }, +/* 253 */ { XED_FLAG_af,XED_FLAG_ACTION_pop }, +/* 254 */ { XED_FLAG_pf,XED_FLAG_ACTION_pop }, +/* 255 */ { XED_FLAG_cf,XED_FLAG_ACTION_pop }, +/* 256 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 257 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 258 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 259 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 260 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 261 */ { XED_FLAG_cf,XED_FLAG_ACTION_u }, +/* 262 */ { XED_FLAG_cf,XED_FLAG_ACTION_tst }, +/* 263 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 264 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 265 */ { XED_FLAG_cf,XED_FLAG_ACTION_1 }, +/* 266 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 267 */ { XED_FLAG_iopl,XED_FLAG_ACTION_tst }, +/* 268 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 269 */ { XED_FLAG_df,XED_FLAG_ACTION_0 }, +/* 270 */ { XED_FLAG_df,XED_FLAG_ACTION_1 }, +/* 271 */ { XED_FLAG_id,XED_FLAG_ACTION_mod }, +/* 272 */ { XED_FLAG_vip,XED_FLAG_ACTION_mod }, +/* 273 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 274 */ { XED_FLAG_ac,XED_FLAG_ACTION_mod }, +/* 275 */ { XED_FLAG_vm,XED_FLAG_ACTION_0 }, +/* 276 */ { XED_FLAG_rf,XED_FLAG_ACTION_0 }, +/* 277 */ { XED_FLAG_nt,XED_FLAG_ACTION_mod }, +/* 278 */ { XED_FLAG_iopl,XED_FLAG_ACTION_mod }, +/* 279 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 280 */ { XED_FLAG_df,XED_FLAG_ACTION_mod }, +/* 281 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 282 */ { XED_FLAG_tf,XED_FLAG_ACTION_mod }, +/* 283 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 284 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 285 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 286 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 287 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 288 */ { XED_FLAG_id,XED_FLAG_ACTION_mod }, +/* 289 */ { XED_FLAG_vip,XED_FLAG_ACTION_mod }, +/* 290 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 291 */ { XED_FLAG_ac,XED_FLAG_ACTION_mod }, +/* 292 */ { XED_FLAG_rf,XED_FLAG_ACTION_0 }, +/* 293 */ { XED_FLAG_nt,XED_FLAG_ACTION_mod }, +/* 294 */ { XED_FLAG_iopl,XED_FLAG_ACTION_mod }, +/* 295 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 296 */ { XED_FLAG_df,XED_FLAG_ACTION_mod }, +/* 297 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 298 */ { XED_FLAG_tf,XED_FLAG_ACTION_mod }, +/* 299 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 300 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 301 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 302 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 303 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 304 */ { XED_FLAG_vm,XED_FLAG_ACTION_0 }, +/* 305 */ { XED_FLAG_rf,XED_FLAG_ACTION_0 }, +/* 306 */ { XED_FLAG_if,XED_FLAG_ACTION_0 }, +/* 307 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 308 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 309 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 310 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 311 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 312 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 313 */ { XED_FLAG_id,XED_FLAG_ACTION_mod }, +/* 314 */ { XED_FLAG_vip,XED_FLAG_ACTION_mod }, +/* 315 */ { XED_FLAG_vif,XED_FLAG_ACTION_mod }, +/* 316 */ { XED_FLAG_ac,XED_FLAG_ACTION_mod }, +/* 317 */ { XED_FLAG_vm,XED_FLAG_ACTION_mod }, +/* 318 */ { XED_FLAG_rf,XED_FLAG_ACTION_mod }, +/* 319 */ { XED_FLAG_nt,XED_FLAG_ACTION_mod }, +/* 320 */ { XED_FLAG_iopl,XED_FLAG_ACTION_mod }, +/* 321 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 322 */ { XED_FLAG_df,XED_FLAG_ACTION_mod }, +/* 323 */ { XED_FLAG_if,XED_FLAG_ACTION_mod }, +/* 324 */ { XED_FLAG_tf,XED_FLAG_ACTION_mod }, +/* 325 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 326 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 327 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 328 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 329 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 330 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 331 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 332 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 333 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 334 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 335 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 336 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 337 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 338 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 339 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 340 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 341 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 342 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 343 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 344 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 345 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 346 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 347 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 348 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 349 */ { XED_FLAG_zf,XED_FLAG_ACTION_0 }, +/* 350 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 351 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 352 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 353 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 354 */ { XED_FLAG_ac,XED_FLAG_ACTION_0 }, +/* 355 */ { XED_FLAG_ac,XED_FLAG_ACTION_1 }, +/* 356 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 357 */ { XED_FLAG_zf,XED_FLAG_ACTION_0 }, +/* 358 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 359 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 360 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 361 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 362 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 363 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 364 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 365 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 366 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 367 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 368 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 369 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 370 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 371 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 372 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 373 */ { XED_FLAG_cf,XED_FLAG_ACTION_u }, +/* 374 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 375 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 376 */ { XED_FLAG_of,XED_FLAG_ACTION_u }, +/* 377 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 378 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 379 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 380 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 381 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 382 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 383 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 384 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 385 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 386 */ { XED_FLAG_of,XED_FLAG_ACTION_tst }, +/* 387 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 388 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 389 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 390 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 391 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 392 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 393 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 394 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 395 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 396 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 397 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 398 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 399 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 400 */ { XED_FLAG_zf,XED_FLAG_ACTION_0 }, +/* 401 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 402 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 403 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 404 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 405 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 406 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 407 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 408 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 409 */ { XED_FLAG_of,XED_FLAG_ACTION_mod }, +/* 410 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 411 */ { XED_FLAG_af,XED_FLAG_ACTION_mod }, +/* 412 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 413 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 414 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 415 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 416 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 417 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 418 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 419 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 420 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 421 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 422 */ { XED_FLAG_sf,XED_FLAG_ACTION_u }, +/* 423 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 424 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 425 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 426 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 427 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 428 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 429 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 430 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 431 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 432 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 433 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 434 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 435 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 436 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 437 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 438 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 439 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 440 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 441 */ { XED_FLAG_cf,XED_FLAG_ACTION_0 }, +/* 442 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 443 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 444 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 445 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 446 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 447 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 448 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 449 */ { XED_FLAG_sf,XED_FLAG_ACTION_mod }, +/* 450 */ { XED_FLAG_zf,XED_FLAG_ACTION_0 }, +/* 451 */ { XED_FLAG_af,XED_FLAG_ACTION_u }, +/* 452 */ { XED_FLAG_pf,XED_FLAG_ACTION_u }, +/* 453 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 454 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 455 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 456 */ { XED_FLAG_pf,XED_FLAG_ACTION_0 }, +/* 457 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 458 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 459 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 460 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 461 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 462 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 463 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 464 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +/* 465 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 466 */ { XED_FLAG_zf,XED_FLAG_ACTION_mod }, +/* 467 */ { XED_FLAG_pf,XED_FLAG_ACTION_mod }, +/* 468 */ { XED_FLAG_cf,XED_FLAG_ACTION_mod }, +/* 469 */ { XED_FLAG_of,XED_FLAG_ACTION_0 }, +/* 470 */ { XED_FLAG_sf,XED_FLAG_ACTION_0 }, +/* 471 */ { XED_FLAG_af,XED_FLAG_ACTION_0 }, +}; diff --git a/CodeVirtualizer/build/obj/xed-flags-complex.c b/CodeVirtualizer/build/obj/xed-flags-complex.c new file mode 100644 index 0000000..53bf7df --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flags-complex.c @@ -0,0 +1,64 @@ +/// @file xed-flags-complex.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-flags.h" +#include "xed-flags-private.h" +const xed_complex_flag_t xed_flags_complex_table[] = { +/* 0 */ {0,0,{0,0,0,0,0},}, /* invalid */ +/* 1 */ {0,1,{0,14,15,0,0},}, +/* 2 */ {0,1,{0,14,15,0,0},}, +/* 3 */ {0,1,{0,14,15,0,0},}, +/* 4 */ {0,1,{0,14,15,0,0},}, +/* 5 */ {0,1,{0,14,15,0,0},}, +/* 6 */ {0,1,{0,14,15,0,0},}, +/* 7 */ {0,1,{0,14,15,0,0},}, +/* 8 */ {0,1,{0,14,15,0,0},}, +/* 9 */ {0,1,{0,17,18,0,0},}, +/* 10 */ {0,1,{0,17,18,0,0},}, +/* 11 */ {0,1,{0,17,18,0,0},}, +/* 12 */ {0,1,{0,17,18,0,0},}, +/* 13 */ {0,1,{0,17,18,0,0},}, +/* 14 */ {0,1,{0,17,18,0,0},}, +/* 15 */ {0,1,{0,17,18,0,0},}, +/* 16 */ {0,1,{0,17,18,0,0},}, +/* 17 */ {0,1,{0,20,21,0,0},}, +/* 18 */ {0,1,{0,20,21,0,0},}, +/* 19 */ {0,1,{0,20,21,0,0},}, +/* 20 */ {0,1,{0,20,21,0,0},}, +/* 21 */ {0,1,{0,20,21,0,0},}, +/* 22 */ {0,1,{0,20,21,0,0},}, +/* 23 */ {0,1,{0,20,21,0,0},}, +/* 24 */ {0,1,{0,20,21,0,0},}, +/* 25 */ {0,1,{0,20,21,0,0},}, +/* 26 */ {0,1,{0,20,21,0,0},}, +/* 27 */ {0,1,{0,20,21,0,0},}, +/* 28 */ {0,1,{0,20,21,0,0},}, +/* 29 */ {0,1,{0,20,21,0,0},}, +/* 30 */ {0,1,{0,20,21,0,0},}, +/* 31 */ {0,1,{0,20,21,0,0},}, +/* 32 */ {0,1,{0,20,21,0,0},}, +/* 33 */ {0,1,{0,20,21,0,0},}, +/* 34 */ {0,1,{0,20,21,0,0},}, +/* 35 */ {0,1,{0,20,21,0,0},}, +/* 36 */ {0,1,{0,20,21,0,0},}, +}; diff --git a/CodeVirtualizer/build/obj/xed-flags-simple.c b/CodeVirtualizer/build/obj/xed-flags-simple.c new file mode 100644 index 0000000..2b6238c --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-flags-simple.c @@ -0,0 +1,125 @@ +/// @file xed-flags-simple.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-flags.h" +const xed_simple_flag_t xed_flags_simple_table[] = { +/* 0 */ {0,0,0,{0},{0},{0},0}, /* invalid */ +/* 1 */ {4,0,1,{0x0},{0xf0000000},{0xd0000000},0}, +/* 2 */ {4,0,1,{0x0},{0xf0000000},{0x0},4}, +/* 3 */ {4,0,1,{0x0},{0xf0000000},{0xf0000000},8}, +/* 4 */ {4,0,1,{0x0},{0xf0000000},{0x90000000},12}, +/* 5 */ {5,0,1,{0x1},{0xf0000000},{0xd0000000},16}, +/* 6 */ {5,0,1,{0x40},{0xf0000000},{0xd0000000},21}, +/* 7 */ {6,0,1,{0x41},{0xf0000000},{0xd0000000},26}, +/* 8 */ {5,0,1,{0x4},{0xf0000000},{0xd0000000},32}, +/* 9 */ {7,0,1,{0x0},{0x200008d5},{0x0},37}, +/* 10 */ {6,0,1,{0x0},{0x8d5},{0x0},44}, +/* 11 */ {6,0,1,{0x0},{0x8d5},{0x10},50}, +/* 12 */ {7,0,1,{0x1},{0x8d5},{0x0},56}, +/* 13 */ {7,0,1,{0x1},{0x8d5},{0x10},63}, +/* 14 */ {2,0,1,{0x0},{0x801},{0x0},70}, +/* 15 */ {2,0,1,{0x0},{0x801},{0x800},72}, +/* 16 */ {2,1,0,{0x0},{0x801},{0x800},72}, +/* 17 */ {3,0,1,{0x1},{0x801},{0x0},74}, +/* 18 */ {3,0,1,{0x1},{0x801},{0x800},77}, +/* 19 */ {3,1,0,{0x1},{0x801},{0x800},77}, +/* 20 */ {6,0,1,{0x0},{0x8d5},{0x10},80}, +/* 21 */ {6,0,1,{0x0},{0x8d5},{0x810},86}, +/* 22 */ {6,1,0,{0x0},{0x8d5},{0x810},86}, +/* 23 */ {6,0,1,{0x0},{0x8d5},{0xd4},92}, +/* 24 */ {6,0,1,{0x0},{0x8d5},{0x8d5},98}, +/* 25 */ {5,0,1,{0x0},{0x8d4},{0x0},56}, +/* 26 */ {1,0,1,{0x0},{0x40},{0x0},37}, +/* 27 */ {5,0,1,{0x0},{0x895},{0x894},104}, +/* 28 */ {6,0,1,{0x0},{0x8d5},{0x0},109}, +/* 29 */ {18,1,0,{0x23000},{0x3d7fd5},{0x0},115}, +/* 30 */ {6,0,1,{0x0},{0x8d5},{0x0},133}, +/* 31 */ {8,0,1,{0x11},{0x8d5},{0x800},139}, +/* 32 */ {7,0,1,{0x10},{0x8d5},{0x8c4},147}, +/* 33 */ {2,0,0,{0x3400},{0x0},{0x0},154}, +/* 34 */ {1,0,0,{0x800},{0x0},{0x0},156}, +/* 35 */ {1,0,0,{0x1},{0x0},{0x0},26}, +/* 36 */ {1,0,0,{0x40},{0x0},{0x0},21}, +/* 37 */ {2,0,0,{0x41},{0x0},{0x0},26}, +/* 38 */ {1,0,0,{0x80},{0x0},{0x0},157}, +/* 39 */ {1,0,0,{0x4},{0x0},{0x0},32}, +/* 40 */ {2,0,0,{0x880},{0x0},{0x0},158}, +/* 41 */ {3,0,0,{0x8c0},{0x0},{0x0},160}, +/* 42 */ {18,0,1,{0x3f7fd5},{0x0},{0x0},163}, +/* 43 */ {18,0,1,{0x123000},{0x2d7fd5},{0x0},181}, +/* 44 */ {5,0,1,{0x0},{0xd5},{0x0},199}, +/* 45 */ {5,0,1,{0xd5},{0x0},{0x0},204}, +/* 46 */ {1,0,0,{0x400},{0x0},{0x0},209}, +/* 47 */ {8,1,0,{0x440},{0x8d5},{0x0},210}, +/* 48 */ {7,0,1,{0x400},{0x8d5},{0x0},210}, +/* 49 */ {9,0,1,{0x23000},{0xf4300},{0x0},218}, +/* 50 */ {9,0,1,{0x23800},{0x74300},{0x0},227}, +/* 51 */ {20,0,1,{0x27000},{0x3f7fd5},{0x0},236}, +/* 52 */ {6,0,1,{0x0},{0x8d5},{0x811},256}, +/* 53 */ {1,0,1,{0x1},{0x0},{0x0},26}, +/* 54 */ {1,0,0,{0x3000},{0x0},{0x0},154}, +/* 55 */ {2,0,1,{0x1},{0x1},{0x0},262}, +/* 56 */ {1,0,1,{0x0},{0x1},{0x0},264}, +/* 57 */ {1,0,1,{0x0},{0x1},{0x0},265}, +/* 58 */ {3,0,1,{0x3000},{0x80200},{0x0},266}, +/* 59 */ {1,0,1,{0x0},{0x400},{0x0},269}, +/* 60 */ {1,0,1,{0x0},{0x400},{0x0},270}, +/* 61 */ {17,0,1,{0x0},{0x3f7fd5},{0x0},271}, +/* 62 */ {16,0,1,{0x0},{0x3d7fd5},{0x0},288}, +/* 63 */ {3,0,1,{0x0},{0x30200},{0x0},304}, +/* 64 */ {1,0,0,{0x1},{0x0},{0x0},262}, +/* 65 */ {6,0,1,{0x0},{0x8d5},{0x0},307}, +/* 66 */ {1,0,0,{0x80},{0x0},{0x0},204}, +/* 67 */ {2,0,0,{0x880},{0x0},{0x0},160}, +/* 68 */ {17,0,1,{0x0},{0x3f7fd5},{0x0},313}, +/* 69 */ {6,0,1,{0x0},{0x8d5},{0x0},330}, +/* 70 */ {6,0,1,{0x0},{0x8d5},{0x0},336}, +/* 71 */ {6,0,1,{0x0},{0x8d5},{0x0},342}, +/* 72 */ {1,0,1,{0x0},{0x1},{0x0},342}, +/* 73 */ {6,0,1,{0x0},{0x8d5},{0x0},348}, +/* 74 */ {1,0,1,{0x0},{0x40000},{0x0},354}, +/* 75 */ {1,0,1,{0x0},{0x40000},{0x0},355}, +/* 76 */ {6,0,1,{0x0},{0x8d5},{0x0},356}, +/* 77 */ {6,0,1,{0x0},{0x8d5},{0x894},362}, +/* 78 */ {6,0,1,{0x0},{0x8d5},{0x895},368}, +/* 79 */ {6,0,1,{0x0},{0x8d5},{0x894},374}, +/* 80 */ {6,0,1,{0x0},{0x8d5},{0x0},380}, +/* 81 */ {2,0,1,{0x800},{0x800},{0x0},386}, +/* 82 */ {6,0,1,{0x0},{0x8d5},{0x0},388}, +/* 83 */ {6,0,1,{0x0},{0x8d5},{0x0},394}, +/* 84 */ {6,0,1,{0x0},{0x8d5},{0x0},400}, +/* 85 */ {1,0,1,{0x0},{0x1},{0x0},374}, +/* 86 */ {6,0,1,{0x0},{0x8d5},{0x0},406}, +/* 87 */ {6,0,1,{0x0},{0x8d5},{0x0},412}, +/* 88 */ {6,0,1,{0x0},{0x8d5},{0x94},418}, +/* 89 */ {6,0,1,{0x0},{0x8d5},{0x14},424}, +/* 90 */ {1,0,1,{0x0},{0x1},{0x0},424}, +/* 91 */ {6,0,1,{0x0},{0x8d5},{0x0},430}, +/* 92 */ {2,0,1,{0x0},{0x41},{0x0},412}, +/* 93 */ {6,0,1,{0x0},{0x8d5},{0x14},436}, +/* 94 */ {6,0,1,{0x0},{0x8d5},{0x14},442}, +/* 95 */ {6,0,1,{0x0},{0x8d5},{0x14},448}, +/* 96 */ {6,0,1,{0x0},{0x8d5},{0x0},454}, +/* 97 */ {6,0,1,{0x0},{0x8d5},{0x0},460}, +/* 98 */ {6,0,1,{0x0},{0x8d5},{0x0},466}, +}; diff --git a/CodeVirtualizer/build/obj/xed-gen-table-defs.h b/CodeVirtualizer/build/obj/xed-gen-table-defs.h new file mode 100644 index 0000000..c0df29e --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-gen-table-defs.h @@ -0,0 +1,39 @@ +/// @file xed-gen-table-defs.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_GEN_TABLE_DEFS_H) +# define XED_GEN_TABLE_DEFS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#define XED_ICLASS_NAME_STR_MAX 142 +#define XED_MAX_ATTRIBUTE_COUNT 93 +#define XED_MAX_INST_TABLE_NODES 7614 +#define XED_MAX_OPERAND_TABLE_NODES 1502 +#define XED_MAX_OPERAND_SEQUENCES 8974 +#define XED_MAX_REQUIRED_SIMPLE_FLAGS_ENTRIES 99 +#define XED_MAX_REQUIRED_COMPLEX_FLAGS_ENTRIES 37 +#define XED_MAX_GLOBAL_FLAG_ACTIONS 472 +#define XED_MAX_IFORMS_PER_ICLASS 28 +#define XED_MAX_REQUIRED_ATTRIBUTES 205 +#define XED_MAX_CONVERT_PATTERNS 5 +#define XED_MAX_DECORATIONS_PER_OPERAND 3 +#define XED_MAX_MAP_VEX 3 +#define XED_MAX_MAP_EVEX 6 +#endif diff --git a/CodeVirtualizer/build/obj/xed-iclass-enum.c b/CodeVirtualizer/build/obj/xed-iclass-enum.c new file mode 100644 index 0000000..a3a6f8b --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iclass-enum.c @@ -0,0 +1,3544 @@ +/// @file xed-iclass-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-iclass-enum.h" + +typedef struct { + const char* name; + xed_iclass_enum_t value; +} name_table_xed_iclass_enum_t; +static const name_table_xed_iclass_enum_t name_array_xed_iclass_enum_t[] = { +{"INVALID", XED_ICLASS_INVALID}, +{"AAA", XED_ICLASS_AAA}, +{"AAD", XED_ICLASS_AAD}, +{"AAM", XED_ICLASS_AAM}, +{"AAS", XED_ICLASS_AAS}, +{"ADC", XED_ICLASS_ADC}, +{"ADCX", XED_ICLASS_ADCX}, +{"ADC_LOCK", XED_ICLASS_ADC_LOCK}, +{"ADD", XED_ICLASS_ADD}, +{"ADDPD", XED_ICLASS_ADDPD}, +{"ADDPS", XED_ICLASS_ADDPS}, +{"ADDSD", XED_ICLASS_ADDSD}, +{"ADDSS", XED_ICLASS_ADDSS}, +{"ADDSUBPD", XED_ICLASS_ADDSUBPD}, +{"ADDSUBPS", XED_ICLASS_ADDSUBPS}, +{"ADD_LOCK", XED_ICLASS_ADD_LOCK}, +{"ADOX", XED_ICLASS_ADOX}, +{"AESDEC", XED_ICLASS_AESDEC}, +{"AESDEC128KL", XED_ICLASS_AESDEC128KL}, +{"AESDEC256KL", XED_ICLASS_AESDEC256KL}, +{"AESDECLAST", XED_ICLASS_AESDECLAST}, +{"AESDECWIDE128KL", XED_ICLASS_AESDECWIDE128KL}, +{"AESDECWIDE256KL", XED_ICLASS_AESDECWIDE256KL}, +{"AESENC", XED_ICLASS_AESENC}, +{"AESENC128KL", XED_ICLASS_AESENC128KL}, +{"AESENC256KL", XED_ICLASS_AESENC256KL}, +{"AESENCLAST", XED_ICLASS_AESENCLAST}, +{"AESENCWIDE128KL", XED_ICLASS_AESENCWIDE128KL}, +{"AESENCWIDE256KL", XED_ICLASS_AESENCWIDE256KL}, +{"AESIMC", XED_ICLASS_AESIMC}, +{"AESKEYGENASSIST", XED_ICLASS_AESKEYGENASSIST}, +{"AND", XED_ICLASS_AND}, +{"ANDN", XED_ICLASS_ANDN}, +{"ANDNPD", XED_ICLASS_ANDNPD}, +{"ANDNPS", XED_ICLASS_ANDNPS}, +{"ANDPD", XED_ICLASS_ANDPD}, +{"ANDPS", XED_ICLASS_ANDPS}, +{"AND_LOCK", XED_ICLASS_AND_LOCK}, +{"ARPL", XED_ICLASS_ARPL}, +{"BEXTR", XED_ICLASS_BEXTR}, +{"BEXTR_XOP", XED_ICLASS_BEXTR_XOP}, +{"BLCFILL", XED_ICLASS_BLCFILL}, +{"BLCI", XED_ICLASS_BLCI}, +{"BLCIC", XED_ICLASS_BLCIC}, +{"BLCMSK", XED_ICLASS_BLCMSK}, +{"BLCS", XED_ICLASS_BLCS}, +{"BLENDPD", XED_ICLASS_BLENDPD}, +{"BLENDPS", XED_ICLASS_BLENDPS}, +{"BLENDVPD", XED_ICLASS_BLENDVPD}, +{"BLENDVPS", XED_ICLASS_BLENDVPS}, +{"BLSFILL", XED_ICLASS_BLSFILL}, +{"BLSI", XED_ICLASS_BLSI}, +{"BLSIC", XED_ICLASS_BLSIC}, +{"BLSMSK", XED_ICLASS_BLSMSK}, +{"BLSR", XED_ICLASS_BLSR}, +{"BNDCL", XED_ICLASS_BNDCL}, +{"BNDCN", XED_ICLASS_BNDCN}, +{"BNDCU", XED_ICLASS_BNDCU}, +{"BNDLDX", XED_ICLASS_BNDLDX}, +{"BNDMK", XED_ICLASS_BNDMK}, +{"BNDMOV", XED_ICLASS_BNDMOV}, +{"BNDSTX", XED_ICLASS_BNDSTX}, +{"BOUND", XED_ICLASS_BOUND}, +{"BSF", XED_ICLASS_BSF}, +{"BSR", XED_ICLASS_BSR}, +{"BSWAP", XED_ICLASS_BSWAP}, +{"BT", XED_ICLASS_BT}, +{"BTC", XED_ICLASS_BTC}, +{"BTC_LOCK", XED_ICLASS_BTC_LOCK}, +{"BTR", XED_ICLASS_BTR}, +{"BTR_LOCK", XED_ICLASS_BTR_LOCK}, +{"BTS", XED_ICLASS_BTS}, +{"BTS_LOCK", XED_ICLASS_BTS_LOCK}, +{"BZHI", XED_ICLASS_BZHI}, +{"CALL_FAR", XED_ICLASS_CALL_FAR}, +{"CALL_NEAR", XED_ICLASS_CALL_NEAR}, +{"CBW", XED_ICLASS_CBW}, +{"CDQ", XED_ICLASS_CDQ}, +{"CDQE", XED_ICLASS_CDQE}, +{"CLAC", XED_ICLASS_CLAC}, +{"CLC", XED_ICLASS_CLC}, +{"CLD", XED_ICLASS_CLD}, +{"CLDEMOTE", XED_ICLASS_CLDEMOTE}, +{"CLFLUSH", XED_ICLASS_CLFLUSH}, +{"CLFLUSHOPT", XED_ICLASS_CLFLUSHOPT}, +{"CLGI", XED_ICLASS_CLGI}, +{"CLI", XED_ICLASS_CLI}, +{"CLRSSBSY", XED_ICLASS_CLRSSBSY}, +{"CLTS", XED_ICLASS_CLTS}, +{"CLUI", XED_ICLASS_CLUI}, +{"CLWB", XED_ICLASS_CLWB}, +{"CLZERO", XED_ICLASS_CLZERO}, +{"CMC", XED_ICLASS_CMC}, +{"CMOVB", XED_ICLASS_CMOVB}, +{"CMOVBE", XED_ICLASS_CMOVBE}, +{"CMOVL", XED_ICLASS_CMOVL}, +{"CMOVLE", XED_ICLASS_CMOVLE}, +{"CMOVNB", XED_ICLASS_CMOVNB}, +{"CMOVNBE", XED_ICLASS_CMOVNBE}, +{"CMOVNL", XED_ICLASS_CMOVNL}, +{"CMOVNLE", XED_ICLASS_CMOVNLE}, +{"CMOVNO", XED_ICLASS_CMOVNO}, +{"CMOVNP", XED_ICLASS_CMOVNP}, +{"CMOVNS", XED_ICLASS_CMOVNS}, +{"CMOVNZ", XED_ICLASS_CMOVNZ}, +{"CMOVO", XED_ICLASS_CMOVO}, +{"CMOVP", XED_ICLASS_CMOVP}, +{"CMOVS", XED_ICLASS_CMOVS}, +{"CMOVZ", XED_ICLASS_CMOVZ}, +{"CMP", XED_ICLASS_CMP}, +{"CMPPD", XED_ICLASS_CMPPD}, +{"CMPPS", XED_ICLASS_CMPPS}, +{"CMPSB", XED_ICLASS_CMPSB}, +{"CMPSD", XED_ICLASS_CMPSD}, +{"CMPSD_XMM", XED_ICLASS_CMPSD_XMM}, +{"CMPSQ", XED_ICLASS_CMPSQ}, +{"CMPSS", XED_ICLASS_CMPSS}, +{"CMPSW", XED_ICLASS_CMPSW}, +{"CMPXCHG", XED_ICLASS_CMPXCHG}, +{"CMPXCHG16B", XED_ICLASS_CMPXCHG16B}, +{"CMPXCHG16B_LOCK", XED_ICLASS_CMPXCHG16B_LOCK}, +{"CMPXCHG8B", XED_ICLASS_CMPXCHG8B}, +{"CMPXCHG8B_LOCK", XED_ICLASS_CMPXCHG8B_LOCK}, +{"CMPXCHG_LOCK", XED_ICLASS_CMPXCHG_LOCK}, +{"COMISD", XED_ICLASS_COMISD}, +{"COMISS", XED_ICLASS_COMISS}, +{"CPUID", XED_ICLASS_CPUID}, +{"CQO", XED_ICLASS_CQO}, +{"CRC32", XED_ICLASS_CRC32}, +{"CVTDQ2PD", XED_ICLASS_CVTDQ2PD}, +{"CVTDQ2PS", XED_ICLASS_CVTDQ2PS}, +{"CVTPD2DQ", XED_ICLASS_CVTPD2DQ}, +{"CVTPD2PI", XED_ICLASS_CVTPD2PI}, +{"CVTPD2PS", XED_ICLASS_CVTPD2PS}, +{"CVTPI2PD", XED_ICLASS_CVTPI2PD}, +{"CVTPI2PS", XED_ICLASS_CVTPI2PS}, +{"CVTPS2DQ", XED_ICLASS_CVTPS2DQ}, +{"CVTPS2PD", XED_ICLASS_CVTPS2PD}, +{"CVTPS2PI", XED_ICLASS_CVTPS2PI}, +{"CVTSD2SI", XED_ICLASS_CVTSD2SI}, +{"CVTSD2SS", XED_ICLASS_CVTSD2SS}, +{"CVTSI2SD", XED_ICLASS_CVTSI2SD}, +{"CVTSI2SS", XED_ICLASS_CVTSI2SS}, +{"CVTSS2SD", XED_ICLASS_CVTSS2SD}, +{"CVTSS2SI", XED_ICLASS_CVTSS2SI}, +{"CVTTPD2DQ", XED_ICLASS_CVTTPD2DQ}, +{"CVTTPD2PI", XED_ICLASS_CVTTPD2PI}, +{"CVTTPS2DQ", XED_ICLASS_CVTTPS2DQ}, +{"CVTTPS2PI", XED_ICLASS_CVTTPS2PI}, +{"CVTTSD2SI", XED_ICLASS_CVTTSD2SI}, +{"CVTTSS2SI", XED_ICLASS_CVTTSS2SI}, +{"CWD", XED_ICLASS_CWD}, +{"CWDE", XED_ICLASS_CWDE}, +{"DAA", XED_ICLASS_DAA}, +{"DAS", XED_ICLASS_DAS}, +{"DEC", XED_ICLASS_DEC}, +{"DEC_LOCK", XED_ICLASS_DEC_LOCK}, +{"DIV", XED_ICLASS_DIV}, +{"DIVPD", XED_ICLASS_DIVPD}, +{"DIVPS", XED_ICLASS_DIVPS}, +{"DIVSD", XED_ICLASS_DIVSD}, +{"DIVSS", XED_ICLASS_DIVSS}, +{"DPPD", XED_ICLASS_DPPD}, +{"DPPS", XED_ICLASS_DPPS}, +{"EMMS", XED_ICLASS_EMMS}, +{"ENCLS", XED_ICLASS_ENCLS}, +{"ENCLU", XED_ICLASS_ENCLU}, +{"ENCLV", XED_ICLASS_ENCLV}, +{"ENCODEKEY128", XED_ICLASS_ENCODEKEY128}, +{"ENCODEKEY256", XED_ICLASS_ENCODEKEY256}, +{"ENDBR32", XED_ICLASS_ENDBR32}, +{"ENDBR64", XED_ICLASS_ENDBR64}, +{"ENQCMD", XED_ICLASS_ENQCMD}, +{"ENQCMDS", XED_ICLASS_ENQCMDS}, +{"ENTER", XED_ICLASS_ENTER}, +{"EXTRACTPS", XED_ICLASS_EXTRACTPS}, +{"EXTRQ", XED_ICLASS_EXTRQ}, +{"F2XM1", XED_ICLASS_F2XM1}, +{"FABS", XED_ICLASS_FABS}, +{"FADD", XED_ICLASS_FADD}, +{"FADDP", XED_ICLASS_FADDP}, +{"FBLD", XED_ICLASS_FBLD}, +{"FBSTP", XED_ICLASS_FBSTP}, +{"FCHS", XED_ICLASS_FCHS}, +{"FCMOVB", XED_ICLASS_FCMOVB}, +{"FCMOVBE", XED_ICLASS_FCMOVBE}, +{"FCMOVE", XED_ICLASS_FCMOVE}, +{"FCMOVNB", XED_ICLASS_FCMOVNB}, +{"FCMOVNBE", XED_ICLASS_FCMOVNBE}, +{"FCMOVNE", XED_ICLASS_FCMOVNE}, +{"FCMOVNU", XED_ICLASS_FCMOVNU}, +{"FCMOVU", XED_ICLASS_FCMOVU}, +{"FCOM", XED_ICLASS_FCOM}, +{"FCOMI", XED_ICLASS_FCOMI}, +{"FCOMIP", XED_ICLASS_FCOMIP}, +{"FCOMP", XED_ICLASS_FCOMP}, +{"FCOMPP", XED_ICLASS_FCOMPP}, +{"FCOS", XED_ICLASS_FCOS}, +{"FDECSTP", XED_ICLASS_FDECSTP}, +{"FDISI8087_NOP", XED_ICLASS_FDISI8087_NOP}, +{"FDIV", XED_ICLASS_FDIV}, +{"FDIVP", XED_ICLASS_FDIVP}, +{"FDIVR", XED_ICLASS_FDIVR}, +{"FDIVRP", XED_ICLASS_FDIVRP}, +{"FEMMS", XED_ICLASS_FEMMS}, +{"FENI8087_NOP", XED_ICLASS_FENI8087_NOP}, +{"FFREE", XED_ICLASS_FFREE}, +{"FFREEP", XED_ICLASS_FFREEP}, +{"FIADD", XED_ICLASS_FIADD}, +{"FICOM", XED_ICLASS_FICOM}, +{"FICOMP", XED_ICLASS_FICOMP}, +{"FIDIV", XED_ICLASS_FIDIV}, +{"FIDIVR", XED_ICLASS_FIDIVR}, +{"FILD", XED_ICLASS_FILD}, +{"FIMUL", XED_ICLASS_FIMUL}, +{"FINCSTP", XED_ICLASS_FINCSTP}, +{"FIST", XED_ICLASS_FIST}, +{"FISTP", XED_ICLASS_FISTP}, +{"FISTTP", XED_ICLASS_FISTTP}, +{"FISUB", XED_ICLASS_FISUB}, +{"FISUBR", XED_ICLASS_FISUBR}, +{"FLD", XED_ICLASS_FLD}, +{"FLD1", XED_ICLASS_FLD1}, +{"FLDCW", XED_ICLASS_FLDCW}, +{"FLDENV", XED_ICLASS_FLDENV}, +{"FLDL2E", XED_ICLASS_FLDL2E}, +{"FLDL2T", XED_ICLASS_FLDL2T}, +{"FLDLG2", XED_ICLASS_FLDLG2}, +{"FLDLN2", XED_ICLASS_FLDLN2}, +{"FLDPI", XED_ICLASS_FLDPI}, +{"FLDZ", XED_ICLASS_FLDZ}, +{"FMUL", XED_ICLASS_FMUL}, +{"FMULP", XED_ICLASS_FMULP}, +{"FNCLEX", XED_ICLASS_FNCLEX}, +{"FNINIT", XED_ICLASS_FNINIT}, +{"FNOP", XED_ICLASS_FNOP}, +{"FNSAVE", XED_ICLASS_FNSAVE}, +{"FNSTCW", XED_ICLASS_FNSTCW}, +{"FNSTENV", XED_ICLASS_FNSTENV}, +{"FNSTSW", XED_ICLASS_FNSTSW}, +{"FPATAN", XED_ICLASS_FPATAN}, +{"FPREM", XED_ICLASS_FPREM}, +{"FPREM1", XED_ICLASS_FPREM1}, +{"FPTAN", XED_ICLASS_FPTAN}, +{"FRNDINT", XED_ICLASS_FRNDINT}, +{"FRSTOR", XED_ICLASS_FRSTOR}, +{"FSCALE", XED_ICLASS_FSCALE}, +{"FSETPM287_NOP", XED_ICLASS_FSETPM287_NOP}, +{"FSIN", XED_ICLASS_FSIN}, +{"FSINCOS", XED_ICLASS_FSINCOS}, +{"FSQRT", XED_ICLASS_FSQRT}, +{"FST", XED_ICLASS_FST}, +{"FSTP", XED_ICLASS_FSTP}, +{"FSTPNCE", XED_ICLASS_FSTPNCE}, +{"FSUB", XED_ICLASS_FSUB}, +{"FSUBP", XED_ICLASS_FSUBP}, +{"FSUBR", XED_ICLASS_FSUBR}, +{"FSUBRP", XED_ICLASS_FSUBRP}, +{"FTST", XED_ICLASS_FTST}, +{"FUCOM", XED_ICLASS_FUCOM}, +{"FUCOMI", XED_ICLASS_FUCOMI}, +{"FUCOMIP", XED_ICLASS_FUCOMIP}, +{"FUCOMP", XED_ICLASS_FUCOMP}, +{"FUCOMPP", XED_ICLASS_FUCOMPP}, +{"FWAIT", XED_ICLASS_FWAIT}, +{"FXAM", XED_ICLASS_FXAM}, +{"FXCH", XED_ICLASS_FXCH}, +{"FXRSTOR", XED_ICLASS_FXRSTOR}, +{"FXRSTOR64", XED_ICLASS_FXRSTOR64}, +{"FXSAVE", XED_ICLASS_FXSAVE}, +{"FXSAVE64", XED_ICLASS_FXSAVE64}, +{"FXTRACT", XED_ICLASS_FXTRACT}, +{"FYL2X", XED_ICLASS_FYL2X}, +{"FYL2XP1", XED_ICLASS_FYL2XP1}, +{"GETSEC", XED_ICLASS_GETSEC}, +{"GF2P8AFFINEINVQB", XED_ICLASS_GF2P8AFFINEINVQB}, +{"GF2P8AFFINEQB", XED_ICLASS_GF2P8AFFINEQB}, +{"GF2P8MULB", XED_ICLASS_GF2P8MULB}, +{"HADDPD", XED_ICLASS_HADDPD}, +{"HADDPS", XED_ICLASS_HADDPS}, +{"HLT", XED_ICLASS_HLT}, +{"HRESET", XED_ICLASS_HRESET}, +{"HSUBPD", XED_ICLASS_HSUBPD}, +{"HSUBPS", XED_ICLASS_HSUBPS}, +{"IDIV", XED_ICLASS_IDIV}, +{"IMUL", XED_ICLASS_IMUL}, +{"IN", XED_ICLASS_IN}, +{"INC", XED_ICLASS_INC}, +{"INCSSPD", XED_ICLASS_INCSSPD}, +{"INCSSPQ", XED_ICLASS_INCSSPQ}, +{"INC_LOCK", XED_ICLASS_INC_LOCK}, +{"INSB", XED_ICLASS_INSB}, +{"INSD", XED_ICLASS_INSD}, +{"INSERTPS", XED_ICLASS_INSERTPS}, +{"INSERTQ", XED_ICLASS_INSERTQ}, +{"INSW", XED_ICLASS_INSW}, +{"INT", XED_ICLASS_INT}, +{"INT1", XED_ICLASS_INT1}, +{"INT3", XED_ICLASS_INT3}, +{"INTO", XED_ICLASS_INTO}, +{"INVD", XED_ICLASS_INVD}, +{"INVEPT", XED_ICLASS_INVEPT}, +{"INVLPG", XED_ICLASS_INVLPG}, +{"INVLPGA", XED_ICLASS_INVLPGA}, +{"INVLPGB", XED_ICLASS_INVLPGB}, +{"INVPCID", XED_ICLASS_INVPCID}, +{"INVVPID", XED_ICLASS_INVVPID}, +{"IRET", XED_ICLASS_IRET}, +{"IRETD", XED_ICLASS_IRETD}, +{"IRETQ", XED_ICLASS_IRETQ}, +{"JB", XED_ICLASS_JB}, +{"JBE", XED_ICLASS_JBE}, +{"JCXZ", XED_ICLASS_JCXZ}, +{"JECXZ", XED_ICLASS_JECXZ}, +{"JL", XED_ICLASS_JL}, +{"JLE", XED_ICLASS_JLE}, +{"JMP", XED_ICLASS_JMP}, +{"JMP_FAR", XED_ICLASS_JMP_FAR}, +{"JNB", XED_ICLASS_JNB}, +{"JNBE", XED_ICLASS_JNBE}, +{"JNL", XED_ICLASS_JNL}, +{"JNLE", XED_ICLASS_JNLE}, +{"JNO", XED_ICLASS_JNO}, +{"JNP", XED_ICLASS_JNP}, +{"JNS", XED_ICLASS_JNS}, +{"JNZ", XED_ICLASS_JNZ}, +{"JO", XED_ICLASS_JO}, +{"JP", XED_ICLASS_JP}, +{"JRCXZ", XED_ICLASS_JRCXZ}, +{"JS", XED_ICLASS_JS}, +{"JZ", XED_ICLASS_JZ}, +{"KADDB", XED_ICLASS_KADDB}, +{"KADDD", XED_ICLASS_KADDD}, +{"KADDQ", XED_ICLASS_KADDQ}, +{"KADDW", XED_ICLASS_KADDW}, +{"KANDB", XED_ICLASS_KANDB}, +{"KANDD", XED_ICLASS_KANDD}, +{"KANDNB", XED_ICLASS_KANDNB}, +{"KANDND", XED_ICLASS_KANDND}, +{"KANDNQ", XED_ICLASS_KANDNQ}, +{"KANDNW", XED_ICLASS_KANDNW}, +{"KANDQ", XED_ICLASS_KANDQ}, +{"KANDW", XED_ICLASS_KANDW}, +{"KMOVB", XED_ICLASS_KMOVB}, +{"KMOVD", XED_ICLASS_KMOVD}, +{"KMOVQ", XED_ICLASS_KMOVQ}, +{"KMOVW", XED_ICLASS_KMOVW}, +{"KNOTB", XED_ICLASS_KNOTB}, +{"KNOTD", XED_ICLASS_KNOTD}, +{"KNOTQ", XED_ICLASS_KNOTQ}, +{"KNOTW", XED_ICLASS_KNOTW}, +{"KORB", XED_ICLASS_KORB}, +{"KORD", XED_ICLASS_KORD}, +{"KORQ", XED_ICLASS_KORQ}, +{"KORTESTB", XED_ICLASS_KORTESTB}, +{"KORTESTD", XED_ICLASS_KORTESTD}, +{"KORTESTQ", XED_ICLASS_KORTESTQ}, +{"KORTESTW", XED_ICLASS_KORTESTW}, +{"KORW", XED_ICLASS_KORW}, +{"KSHIFTLB", XED_ICLASS_KSHIFTLB}, +{"KSHIFTLD", XED_ICLASS_KSHIFTLD}, +{"KSHIFTLQ", XED_ICLASS_KSHIFTLQ}, +{"KSHIFTLW", XED_ICLASS_KSHIFTLW}, +{"KSHIFTRB", XED_ICLASS_KSHIFTRB}, +{"KSHIFTRD", XED_ICLASS_KSHIFTRD}, +{"KSHIFTRQ", XED_ICLASS_KSHIFTRQ}, +{"KSHIFTRW", XED_ICLASS_KSHIFTRW}, +{"KTESTB", XED_ICLASS_KTESTB}, +{"KTESTD", XED_ICLASS_KTESTD}, +{"KTESTQ", XED_ICLASS_KTESTQ}, +{"KTESTW", XED_ICLASS_KTESTW}, +{"KUNPCKBW", XED_ICLASS_KUNPCKBW}, +{"KUNPCKDQ", XED_ICLASS_KUNPCKDQ}, +{"KUNPCKWD", XED_ICLASS_KUNPCKWD}, +{"KXNORB", XED_ICLASS_KXNORB}, +{"KXNORD", XED_ICLASS_KXNORD}, +{"KXNORQ", XED_ICLASS_KXNORQ}, +{"KXNORW", XED_ICLASS_KXNORW}, +{"KXORB", XED_ICLASS_KXORB}, +{"KXORD", XED_ICLASS_KXORD}, +{"KXORQ", XED_ICLASS_KXORQ}, +{"KXORW", XED_ICLASS_KXORW}, +{"LAHF", XED_ICLASS_LAHF}, +{"LAR", XED_ICLASS_LAR}, +{"LDDQU", XED_ICLASS_LDDQU}, +{"LDMXCSR", XED_ICLASS_LDMXCSR}, +{"LDS", XED_ICLASS_LDS}, +{"LDTILECFG", XED_ICLASS_LDTILECFG}, +{"LEA", XED_ICLASS_LEA}, +{"LEAVE", XED_ICLASS_LEAVE}, +{"LES", XED_ICLASS_LES}, +{"LFENCE", XED_ICLASS_LFENCE}, +{"LFS", XED_ICLASS_LFS}, +{"LGDT", XED_ICLASS_LGDT}, +{"LGS", XED_ICLASS_LGS}, +{"LIDT", XED_ICLASS_LIDT}, +{"LLDT", XED_ICLASS_LLDT}, +{"LLWPCB", XED_ICLASS_LLWPCB}, +{"LMSW", XED_ICLASS_LMSW}, +{"LOADIWKEY", XED_ICLASS_LOADIWKEY}, +{"LODSB", XED_ICLASS_LODSB}, +{"LODSD", XED_ICLASS_LODSD}, +{"LODSQ", XED_ICLASS_LODSQ}, +{"LODSW", XED_ICLASS_LODSW}, +{"LOOP", XED_ICLASS_LOOP}, +{"LOOPE", XED_ICLASS_LOOPE}, +{"LOOPNE", XED_ICLASS_LOOPNE}, +{"LSL", XED_ICLASS_LSL}, +{"LSS", XED_ICLASS_LSS}, +{"LTR", XED_ICLASS_LTR}, +{"LWPINS", XED_ICLASS_LWPINS}, +{"LWPVAL", XED_ICLASS_LWPVAL}, +{"LZCNT", XED_ICLASS_LZCNT}, +{"MASKMOVDQU", XED_ICLASS_MASKMOVDQU}, +{"MASKMOVQ", XED_ICLASS_MASKMOVQ}, +{"MAXPD", XED_ICLASS_MAXPD}, +{"MAXPS", XED_ICLASS_MAXPS}, +{"MAXSD", XED_ICLASS_MAXSD}, +{"MAXSS", XED_ICLASS_MAXSS}, +{"MCOMMIT", XED_ICLASS_MCOMMIT}, +{"MFENCE", XED_ICLASS_MFENCE}, +{"MINPD", XED_ICLASS_MINPD}, +{"MINPS", XED_ICLASS_MINPS}, +{"MINSD", XED_ICLASS_MINSD}, +{"MINSS", XED_ICLASS_MINSS}, +{"MONITOR", XED_ICLASS_MONITOR}, +{"MONITORX", XED_ICLASS_MONITORX}, +{"MOV", XED_ICLASS_MOV}, +{"MOVAPD", XED_ICLASS_MOVAPD}, +{"MOVAPS", XED_ICLASS_MOVAPS}, +{"MOVBE", XED_ICLASS_MOVBE}, +{"MOVD", XED_ICLASS_MOVD}, +{"MOVDDUP", XED_ICLASS_MOVDDUP}, +{"MOVDIR64B", XED_ICLASS_MOVDIR64B}, +{"MOVDIRI", XED_ICLASS_MOVDIRI}, +{"MOVDQ2Q", XED_ICLASS_MOVDQ2Q}, +{"MOVDQA", XED_ICLASS_MOVDQA}, +{"MOVDQU", XED_ICLASS_MOVDQU}, +{"MOVHLPS", XED_ICLASS_MOVHLPS}, +{"MOVHPD", XED_ICLASS_MOVHPD}, +{"MOVHPS", XED_ICLASS_MOVHPS}, +{"MOVLHPS", XED_ICLASS_MOVLHPS}, +{"MOVLPD", XED_ICLASS_MOVLPD}, +{"MOVLPS", XED_ICLASS_MOVLPS}, +{"MOVMSKPD", XED_ICLASS_MOVMSKPD}, +{"MOVMSKPS", XED_ICLASS_MOVMSKPS}, +{"MOVNTDQ", XED_ICLASS_MOVNTDQ}, +{"MOVNTDQA", XED_ICLASS_MOVNTDQA}, +{"MOVNTI", XED_ICLASS_MOVNTI}, +{"MOVNTPD", XED_ICLASS_MOVNTPD}, +{"MOVNTPS", XED_ICLASS_MOVNTPS}, +{"MOVNTQ", XED_ICLASS_MOVNTQ}, +{"MOVNTSD", XED_ICLASS_MOVNTSD}, +{"MOVNTSS", XED_ICLASS_MOVNTSS}, +{"MOVQ", XED_ICLASS_MOVQ}, +{"MOVQ2DQ", XED_ICLASS_MOVQ2DQ}, +{"MOVSB", XED_ICLASS_MOVSB}, +{"MOVSD", XED_ICLASS_MOVSD}, +{"MOVSD_XMM", XED_ICLASS_MOVSD_XMM}, +{"MOVSHDUP", XED_ICLASS_MOVSHDUP}, +{"MOVSLDUP", XED_ICLASS_MOVSLDUP}, +{"MOVSQ", XED_ICLASS_MOVSQ}, +{"MOVSS", XED_ICLASS_MOVSS}, +{"MOVSW", XED_ICLASS_MOVSW}, +{"MOVSX", XED_ICLASS_MOVSX}, +{"MOVSXD", XED_ICLASS_MOVSXD}, +{"MOVUPD", XED_ICLASS_MOVUPD}, +{"MOVUPS", XED_ICLASS_MOVUPS}, +{"MOVZX", XED_ICLASS_MOVZX}, +{"MOV_CR", XED_ICLASS_MOV_CR}, +{"MOV_DR", XED_ICLASS_MOV_DR}, +{"MPSADBW", XED_ICLASS_MPSADBW}, +{"MUL", XED_ICLASS_MUL}, +{"MULPD", XED_ICLASS_MULPD}, +{"MULPS", XED_ICLASS_MULPS}, +{"MULSD", XED_ICLASS_MULSD}, +{"MULSS", XED_ICLASS_MULSS}, +{"MULX", XED_ICLASS_MULX}, +{"MWAIT", XED_ICLASS_MWAIT}, +{"MWAITX", XED_ICLASS_MWAITX}, +{"NEG", XED_ICLASS_NEG}, +{"NEG_LOCK", XED_ICLASS_NEG_LOCK}, +{"NOP", XED_ICLASS_NOP}, +{"NOP2", XED_ICLASS_NOP2}, +{"NOP3", XED_ICLASS_NOP3}, +{"NOP4", XED_ICLASS_NOP4}, +{"NOP5", XED_ICLASS_NOP5}, +{"NOP6", XED_ICLASS_NOP6}, +{"NOP7", XED_ICLASS_NOP7}, +{"NOP8", XED_ICLASS_NOP8}, +{"NOP9", XED_ICLASS_NOP9}, +{"NOT", XED_ICLASS_NOT}, +{"NOT_LOCK", XED_ICLASS_NOT_LOCK}, +{"OR", XED_ICLASS_OR}, +{"ORPD", XED_ICLASS_ORPD}, +{"ORPS", XED_ICLASS_ORPS}, +{"OR_LOCK", XED_ICLASS_OR_LOCK}, +{"OUT", XED_ICLASS_OUT}, +{"OUTSB", XED_ICLASS_OUTSB}, +{"OUTSD", XED_ICLASS_OUTSD}, +{"OUTSW", XED_ICLASS_OUTSW}, +{"PABSB", XED_ICLASS_PABSB}, +{"PABSD", XED_ICLASS_PABSD}, +{"PABSW", XED_ICLASS_PABSW}, +{"PACKSSDW", XED_ICLASS_PACKSSDW}, +{"PACKSSWB", XED_ICLASS_PACKSSWB}, +{"PACKUSDW", XED_ICLASS_PACKUSDW}, +{"PACKUSWB", XED_ICLASS_PACKUSWB}, +{"PADDB", XED_ICLASS_PADDB}, +{"PADDD", XED_ICLASS_PADDD}, +{"PADDQ", XED_ICLASS_PADDQ}, +{"PADDSB", XED_ICLASS_PADDSB}, +{"PADDSW", XED_ICLASS_PADDSW}, +{"PADDUSB", XED_ICLASS_PADDUSB}, +{"PADDUSW", XED_ICLASS_PADDUSW}, +{"PADDW", XED_ICLASS_PADDW}, +{"PALIGNR", XED_ICLASS_PALIGNR}, +{"PAND", XED_ICLASS_PAND}, +{"PANDN", XED_ICLASS_PANDN}, +{"PAUSE", XED_ICLASS_PAUSE}, +{"PAVGB", XED_ICLASS_PAVGB}, +{"PAVGUSB", XED_ICLASS_PAVGUSB}, +{"PAVGW", XED_ICLASS_PAVGW}, +{"PBLENDVB", XED_ICLASS_PBLENDVB}, +{"PBLENDW", XED_ICLASS_PBLENDW}, +{"PCLMULQDQ", XED_ICLASS_PCLMULQDQ}, +{"PCMPEQB", XED_ICLASS_PCMPEQB}, +{"PCMPEQD", XED_ICLASS_PCMPEQD}, +{"PCMPEQQ", XED_ICLASS_PCMPEQQ}, +{"PCMPEQW", XED_ICLASS_PCMPEQW}, +{"PCMPESTRI", XED_ICLASS_PCMPESTRI}, +{"PCMPESTRI64", XED_ICLASS_PCMPESTRI64}, +{"PCMPESTRM", XED_ICLASS_PCMPESTRM}, +{"PCMPESTRM64", XED_ICLASS_PCMPESTRM64}, +{"PCMPGTB", XED_ICLASS_PCMPGTB}, +{"PCMPGTD", XED_ICLASS_PCMPGTD}, +{"PCMPGTQ", XED_ICLASS_PCMPGTQ}, +{"PCMPGTW", XED_ICLASS_PCMPGTW}, +{"PCMPISTRI", XED_ICLASS_PCMPISTRI}, +{"PCMPISTRI64", XED_ICLASS_PCMPISTRI64}, +{"PCMPISTRM", XED_ICLASS_PCMPISTRM}, +{"PCONFIG", XED_ICLASS_PCONFIG}, +{"PDEP", XED_ICLASS_PDEP}, +{"PEXT", XED_ICLASS_PEXT}, +{"PEXTRB", XED_ICLASS_PEXTRB}, +{"PEXTRD", XED_ICLASS_PEXTRD}, +{"PEXTRQ", XED_ICLASS_PEXTRQ}, +{"PEXTRW", XED_ICLASS_PEXTRW}, +{"PEXTRW_SSE4", XED_ICLASS_PEXTRW_SSE4}, +{"PF2ID", XED_ICLASS_PF2ID}, +{"PF2IW", XED_ICLASS_PF2IW}, +{"PFACC", XED_ICLASS_PFACC}, +{"PFADD", XED_ICLASS_PFADD}, +{"PFCMPEQ", XED_ICLASS_PFCMPEQ}, +{"PFCMPGE", XED_ICLASS_PFCMPGE}, +{"PFCMPGT", XED_ICLASS_PFCMPGT}, +{"PFMAX", XED_ICLASS_PFMAX}, +{"PFMIN", XED_ICLASS_PFMIN}, +{"PFMUL", XED_ICLASS_PFMUL}, +{"PFNACC", XED_ICLASS_PFNACC}, +{"PFPNACC", XED_ICLASS_PFPNACC}, +{"PFRCP", XED_ICLASS_PFRCP}, +{"PFRCPIT1", XED_ICLASS_PFRCPIT1}, +{"PFRCPIT2", XED_ICLASS_PFRCPIT2}, +{"PFRSQIT1", XED_ICLASS_PFRSQIT1}, +{"PFRSQRT", XED_ICLASS_PFRSQRT}, +{"PFSUB", XED_ICLASS_PFSUB}, +{"PFSUBR", XED_ICLASS_PFSUBR}, +{"PHADDD", XED_ICLASS_PHADDD}, +{"PHADDSW", XED_ICLASS_PHADDSW}, +{"PHADDW", XED_ICLASS_PHADDW}, +{"PHMINPOSUW", XED_ICLASS_PHMINPOSUW}, +{"PHSUBD", XED_ICLASS_PHSUBD}, +{"PHSUBSW", XED_ICLASS_PHSUBSW}, +{"PHSUBW", XED_ICLASS_PHSUBW}, +{"PI2FD", XED_ICLASS_PI2FD}, +{"PI2FW", XED_ICLASS_PI2FW}, +{"PINSRB", XED_ICLASS_PINSRB}, +{"PINSRD", XED_ICLASS_PINSRD}, +{"PINSRQ", XED_ICLASS_PINSRQ}, +{"PINSRW", XED_ICLASS_PINSRW}, +{"PMADDUBSW", XED_ICLASS_PMADDUBSW}, +{"PMADDWD", XED_ICLASS_PMADDWD}, +{"PMAXSB", XED_ICLASS_PMAXSB}, +{"PMAXSD", XED_ICLASS_PMAXSD}, +{"PMAXSW", XED_ICLASS_PMAXSW}, +{"PMAXUB", XED_ICLASS_PMAXUB}, +{"PMAXUD", XED_ICLASS_PMAXUD}, +{"PMAXUW", XED_ICLASS_PMAXUW}, +{"PMINSB", XED_ICLASS_PMINSB}, +{"PMINSD", XED_ICLASS_PMINSD}, +{"PMINSW", XED_ICLASS_PMINSW}, +{"PMINUB", XED_ICLASS_PMINUB}, +{"PMINUD", XED_ICLASS_PMINUD}, +{"PMINUW", XED_ICLASS_PMINUW}, +{"PMOVMSKB", XED_ICLASS_PMOVMSKB}, +{"PMOVSXBD", XED_ICLASS_PMOVSXBD}, +{"PMOVSXBQ", XED_ICLASS_PMOVSXBQ}, +{"PMOVSXBW", XED_ICLASS_PMOVSXBW}, +{"PMOVSXDQ", XED_ICLASS_PMOVSXDQ}, +{"PMOVSXWD", XED_ICLASS_PMOVSXWD}, +{"PMOVSXWQ", XED_ICLASS_PMOVSXWQ}, +{"PMOVZXBD", XED_ICLASS_PMOVZXBD}, +{"PMOVZXBQ", XED_ICLASS_PMOVZXBQ}, +{"PMOVZXBW", XED_ICLASS_PMOVZXBW}, +{"PMOVZXDQ", XED_ICLASS_PMOVZXDQ}, +{"PMOVZXWD", XED_ICLASS_PMOVZXWD}, +{"PMOVZXWQ", XED_ICLASS_PMOVZXWQ}, +{"PMULDQ", XED_ICLASS_PMULDQ}, +{"PMULHRSW", XED_ICLASS_PMULHRSW}, +{"PMULHRW", XED_ICLASS_PMULHRW}, +{"PMULHUW", XED_ICLASS_PMULHUW}, +{"PMULHW", XED_ICLASS_PMULHW}, +{"PMULLD", XED_ICLASS_PMULLD}, +{"PMULLW", XED_ICLASS_PMULLW}, +{"PMULUDQ", XED_ICLASS_PMULUDQ}, +{"POP", XED_ICLASS_POP}, +{"POPA", XED_ICLASS_POPA}, +{"POPAD", XED_ICLASS_POPAD}, +{"POPCNT", XED_ICLASS_POPCNT}, +{"POPF", XED_ICLASS_POPF}, +{"POPFD", XED_ICLASS_POPFD}, +{"POPFQ", XED_ICLASS_POPFQ}, +{"POR", XED_ICLASS_POR}, +{"PREFETCHNTA", XED_ICLASS_PREFETCHNTA}, +{"PREFETCHT0", XED_ICLASS_PREFETCHT0}, +{"PREFETCHT1", XED_ICLASS_PREFETCHT1}, +{"PREFETCHT2", XED_ICLASS_PREFETCHT2}, +{"PREFETCHW", XED_ICLASS_PREFETCHW}, +{"PREFETCHWT1", XED_ICLASS_PREFETCHWT1}, +{"PREFETCH_EXCLUSIVE", XED_ICLASS_PREFETCH_EXCLUSIVE}, +{"PREFETCH_RESERVED", XED_ICLASS_PREFETCH_RESERVED}, +{"PSADBW", XED_ICLASS_PSADBW}, +{"PSHUFB", XED_ICLASS_PSHUFB}, +{"PSHUFD", XED_ICLASS_PSHUFD}, +{"PSHUFHW", XED_ICLASS_PSHUFHW}, +{"PSHUFLW", XED_ICLASS_PSHUFLW}, +{"PSHUFW", XED_ICLASS_PSHUFW}, +{"PSIGNB", XED_ICLASS_PSIGNB}, +{"PSIGND", XED_ICLASS_PSIGND}, +{"PSIGNW", XED_ICLASS_PSIGNW}, +{"PSLLD", XED_ICLASS_PSLLD}, +{"PSLLDQ", XED_ICLASS_PSLLDQ}, +{"PSLLQ", XED_ICLASS_PSLLQ}, +{"PSLLW", XED_ICLASS_PSLLW}, +{"PSMASH", XED_ICLASS_PSMASH}, +{"PSRAD", XED_ICLASS_PSRAD}, +{"PSRAW", XED_ICLASS_PSRAW}, +{"PSRLD", XED_ICLASS_PSRLD}, +{"PSRLDQ", XED_ICLASS_PSRLDQ}, +{"PSRLQ", XED_ICLASS_PSRLQ}, +{"PSRLW", XED_ICLASS_PSRLW}, +{"PSUBB", XED_ICLASS_PSUBB}, +{"PSUBD", XED_ICLASS_PSUBD}, +{"PSUBQ", XED_ICLASS_PSUBQ}, +{"PSUBSB", XED_ICLASS_PSUBSB}, +{"PSUBSW", XED_ICLASS_PSUBSW}, +{"PSUBUSB", XED_ICLASS_PSUBUSB}, +{"PSUBUSW", XED_ICLASS_PSUBUSW}, +{"PSUBW", XED_ICLASS_PSUBW}, +{"PSWAPD", XED_ICLASS_PSWAPD}, +{"PTEST", XED_ICLASS_PTEST}, +{"PTWRITE", XED_ICLASS_PTWRITE}, +{"PUNPCKHBW", XED_ICLASS_PUNPCKHBW}, +{"PUNPCKHDQ", XED_ICLASS_PUNPCKHDQ}, +{"PUNPCKHQDQ", XED_ICLASS_PUNPCKHQDQ}, +{"PUNPCKHWD", XED_ICLASS_PUNPCKHWD}, +{"PUNPCKLBW", XED_ICLASS_PUNPCKLBW}, +{"PUNPCKLDQ", XED_ICLASS_PUNPCKLDQ}, +{"PUNPCKLQDQ", XED_ICLASS_PUNPCKLQDQ}, +{"PUNPCKLWD", XED_ICLASS_PUNPCKLWD}, +{"PUSH", XED_ICLASS_PUSH}, +{"PUSHA", XED_ICLASS_PUSHA}, +{"PUSHAD", XED_ICLASS_PUSHAD}, +{"PUSHF", XED_ICLASS_PUSHF}, +{"PUSHFD", XED_ICLASS_PUSHFD}, +{"PUSHFQ", XED_ICLASS_PUSHFQ}, +{"PVALIDATE", XED_ICLASS_PVALIDATE}, +{"PXOR", XED_ICLASS_PXOR}, +{"RCL", XED_ICLASS_RCL}, +{"RCPPS", XED_ICLASS_RCPPS}, +{"RCPSS", XED_ICLASS_RCPSS}, +{"RCR", XED_ICLASS_RCR}, +{"RDFSBASE", XED_ICLASS_RDFSBASE}, +{"RDGSBASE", XED_ICLASS_RDGSBASE}, +{"RDMSR", XED_ICLASS_RDMSR}, +{"RDPID", XED_ICLASS_RDPID}, +{"RDPKRU", XED_ICLASS_RDPKRU}, +{"RDPMC", XED_ICLASS_RDPMC}, +{"RDPRU", XED_ICLASS_RDPRU}, +{"RDRAND", XED_ICLASS_RDRAND}, +{"RDSEED", XED_ICLASS_RDSEED}, +{"RDSSPD", XED_ICLASS_RDSSPD}, +{"RDSSPQ", XED_ICLASS_RDSSPQ}, +{"RDTSC", XED_ICLASS_RDTSC}, +{"RDTSCP", XED_ICLASS_RDTSCP}, +{"REPE_CMPSB", XED_ICLASS_REPE_CMPSB}, +{"REPE_CMPSD", XED_ICLASS_REPE_CMPSD}, +{"REPE_CMPSQ", XED_ICLASS_REPE_CMPSQ}, +{"REPE_CMPSW", XED_ICLASS_REPE_CMPSW}, +{"REPE_SCASB", XED_ICLASS_REPE_SCASB}, +{"REPE_SCASD", XED_ICLASS_REPE_SCASD}, +{"REPE_SCASQ", XED_ICLASS_REPE_SCASQ}, +{"REPE_SCASW", XED_ICLASS_REPE_SCASW}, +{"REPNE_CMPSB", XED_ICLASS_REPNE_CMPSB}, +{"REPNE_CMPSD", XED_ICLASS_REPNE_CMPSD}, +{"REPNE_CMPSQ", XED_ICLASS_REPNE_CMPSQ}, +{"REPNE_CMPSW", XED_ICLASS_REPNE_CMPSW}, +{"REPNE_SCASB", XED_ICLASS_REPNE_SCASB}, +{"REPNE_SCASD", XED_ICLASS_REPNE_SCASD}, +{"REPNE_SCASQ", XED_ICLASS_REPNE_SCASQ}, +{"REPNE_SCASW", XED_ICLASS_REPNE_SCASW}, +{"REP_INSB", XED_ICLASS_REP_INSB}, +{"REP_INSD", XED_ICLASS_REP_INSD}, +{"REP_INSW", XED_ICLASS_REP_INSW}, +{"REP_LODSB", XED_ICLASS_REP_LODSB}, +{"REP_LODSD", XED_ICLASS_REP_LODSD}, +{"REP_LODSQ", XED_ICLASS_REP_LODSQ}, +{"REP_LODSW", XED_ICLASS_REP_LODSW}, +{"REP_MONTMUL", XED_ICLASS_REP_MONTMUL}, +{"REP_MOVSB", XED_ICLASS_REP_MOVSB}, +{"REP_MOVSD", XED_ICLASS_REP_MOVSD}, +{"REP_MOVSQ", XED_ICLASS_REP_MOVSQ}, +{"REP_MOVSW", XED_ICLASS_REP_MOVSW}, +{"REP_OUTSB", XED_ICLASS_REP_OUTSB}, +{"REP_OUTSD", XED_ICLASS_REP_OUTSD}, +{"REP_OUTSW", XED_ICLASS_REP_OUTSW}, +{"REP_STOSB", XED_ICLASS_REP_STOSB}, +{"REP_STOSD", XED_ICLASS_REP_STOSD}, +{"REP_STOSQ", XED_ICLASS_REP_STOSQ}, +{"REP_STOSW", XED_ICLASS_REP_STOSW}, +{"REP_XCRYPTCBC", XED_ICLASS_REP_XCRYPTCBC}, +{"REP_XCRYPTCFB", XED_ICLASS_REP_XCRYPTCFB}, +{"REP_XCRYPTCTR", XED_ICLASS_REP_XCRYPTCTR}, +{"REP_XCRYPTECB", XED_ICLASS_REP_XCRYPTECB}, +{"REP_XCRYPTOFB", XED_ICLASS_REP_XCRYPTOFB}, +{"REP_XSHA1", XED_ICLASS_REP_XSHA1}, +{"REP_XSHA256", XED_ICLASS_REP_XSHA256}, +{"REP_XSTORE", XED_ICLASS_REP_XSTORE}, +{"RET_FAR", XED_ICLASS_RET_FAR}, +{"RET_NEAR", XED_ICLASS_RET_NEAR}, +{"RMPADJUST", XED_ICLASS_RMPADJUST}, +{"RMPUPDATE", XED_ICLASS_RMPUPDATE}, +{"ROL", XED_ICLASS_ROL}, +{"ROR", XED_ICLASS_ROR}, +{"RORX", XED_ICLASS_RORX}, +{"ROUNDPD", XED_ICLASS_ROUNDPD}, +{"ROUNDPS", XED_ICLASS_ROUNDPS}, +{"ROUNDSD", XED_ICLASS_ROUNDSD}, +{"ROUNDSS", XED_ICLASS_ROUNDSS}, +{"RSM", XED_ICLASS_RSM}, +{"RSQRTPS", XED_ICLASS_RSQRTPS}, +{"RSQRTSS", XED_ICLASS_RSQRTSS}, +{"RSTORSSP", XED_ICLASS_RSTORSSP}, +{"SAHF", XED_ICLASS_SAHF}, +{"SALC", XED_ICLASS_SALC}, +{"SAR", XED_ICLASS_SAR}, +{"SARX", XED_ICLASS_SARX}, +{"SAVEPREVSSP", XED_ICLASS_SAVEPREVSSP}, +{"SBB", XED_ICLASS_SBB}, +{"SBB_LOCK", XED_ICLASS_SBB_LOCK}, +{"SCASB", XED_ICLASS_SCASB}, +{"SCASD", XED_ICLASS_SCASD}, +{"SCASQ", XED_ICLASS_SCASQ}, +{"SCASW", XED_ICLASS_SCASW}, +{"SEAMCALL", XED_ICLASS_SEAMCALL}, +{"SEAMOPS", XED_ICLASS_SEAMOPS}, +{"SEAMRET", XED_ICLASS_SEAMRET}, +{"SENDUIPI", XED_ICLASS_SENDUIPI}, +{"SERIALIZE", XED_ICLASS_SERIALIZE}, +{"SETB", XED_ICLASS_SETB}, +{"SETBE", XED_ICLASS_SETBE}, +{"SETL", XED_ICLASS_SETL}, +{"SETLE", XED_ICLASS_SETLE}, +{"SETNB", XED_ICLASS_SETNB}, +{"SETNBE", XED_ICLASS_SETNBE}, +{"SETNL", XED_ICLASS_SETNL}, +{"SETNLE", XED_ICLASS_SETNLE}, +{"SETNO", XED_ICLASS_SETNO}, +{"SETNP", XED_ICLASS_SETNP}, +{"SETNS", XED_ICLASS_SETNS}, +{"SETNZ", XED_ICLASS_SETNZ}, +{"SETO", XED_ICLASS_SETO}, +{"SETP", XED_ICLASS_SETP}, +{"SETS", XED_ICLASS_SETS}, +{"SETSSBSY", XED_ICLASS_SETSSBSY}, +{"SETZ", XED_ICLASS_SETZ}, +{"SFENCE", XED_ICLASS_SFENCE}, +{"SGDT", XED_ICLASS_SGDT}, +{"SHA1MSG1", XED_ICLASS_SHA1MSG1}, +{"SHA1MSG2", XED_ICLASS_SHA1MSG2}, +{"SHA1NEXTE", XED_ICLASS_SHA1NEXTE}, +{"SHA1RNDS4", XED_ICLASS_SHA1RNDS4}, +{"SHA256MSG1", XED_ICLASS_SHA256MSG1}, +{"SHA256MSG2", XED_ICLASS_SHA256MSG2}, +{"SHA256RNDS2", XED_ICLASS_SHA256RNDS2}, +{"SHL", XED_ICLASS_SHL}, +{"SHLD", XED_ICLASS_SHLD}, +{"SHLX", XED_ICLASS_SHLX}, +{"SHR", XED_ICLASS_SHR}, +{"SHRD", XED_ICLASS_SHRD}, +{"SHRX", XED_ICLASS_SHRX}, +{"SHUFPD", XED_ICLASS_SHUFPD}, +{"SHUFPS", XED_ICLASS_SHUFPS}, +{"SIDT", XED_ICLASS_SIDT}, +{"SKINIT", XED_ICLASS_SKINIT}, +{"SLDT", XED_ICLASS_SLDT}, +{"SLWPCB", XED_ICLASS_SLWPCB}, +{"SMSW", XED_ICLASS_SMSW}, +{"SQRTPD", XED_ICLASS_SQRTPD}, +{"SQRTPS", XED_ICLASS_SQRTPS}, +{"SQRTSD", XED_ICLASS_SQRTSD}, +{"SQRTSS", XED_ICLASS_SQRTSS}, +{"STAC", XED_ICLASS_STAC}, +{"STC", XED_ICLASS_STC}, +{"STD", XED_ICLASS_STD}, +{"STGI", XED_ICLASS_STGI}, +{"STI", XED_ICLASS_STI}, +{"STMXCSR", XED_ICLASS_STMXCSR}, +{"STOSB", XED_ICLASS_STOSB}, +{"STOSD", XED_ICLASS_STOSD}, +{"STOSQ", XED_ICLASS_STOSQ}, +{"STOSW", XED_ICLASS_STOSW}, +{"STR", XED_ICLASS_STR}, +{"STTILECFG", XED_ICLASS_STTILECFG}, +{"STUI", XED_ICLASS_STUI}, +{"SUB", XED_ICLASS_SUB}, +{"SUBPD", XED_ICLASS_SUBPD}, +{"SUBPS", XED_ICLASS_SUBPS}, +{"SUBSD", XED_ICLASS_SUBSD}, +{"SUBSS", XED_ICLASS_SUBSS}, +{"SUB_LOCK", XED_ICLASS_SUB_LOCK}, +{"SWAPGS", XED_ICLASS_SWAPGS}, +{"SYSCALL", XED_ICLASS_SYSCALL}, +{"SYSCALL_AMD", XED_ICLASS_SYSCALL_AMD}, +{"SYSENTER", XED_ICLASS_SYSENTER}, +{"SYSEXIT", XED_ICLASS_SYSEXIT}, +{"SYSRET", XED_ICLASS_SYSRET}, +{"SYSRET64", XED_ICLASS_SYSRET64}, +{"SYSRET_AMD", XED_ICLASS_SYSRET_AMD}, +{"T1MSKC", XED_ICLASS_T1MSKC}, +{"TDCALL", XED_ICLASS_TDCALL}, +{"TDPBF16PS", XED_ICLASS_TDPBF16PS}, +{"TDPBSSD", XED_ICLASS_TDPBSSD}, +{"TDPBSUD", XED_ICLASS_TDPBSUD}, +{"TDPBUSD", XED_ICLASS_TDPBUSD}, +{"TDPBUUD", XED_ICLASS_TDPBUUD}, +{"TEST", XED_ICLASS_TEST}, +{"TESTUI", XED_ICLASS_TESTUI}, +{"TILELOADD", XED_ICLASS_TILELOADD}, +{"TILELOADDT1", XED_ICLASS_TILELOADDT1}, +{"TILERELEASE", XED_ICLASS_TILERELEASE}, +{"TILESTORED", XED_ICLASS_TILESTORED}, +{"TILEZERO", XED_ICLASS_TILEZERO}, +{"TLBSYNC", XED_ICLASS_TLBSYNC}, +{"TPAUSE", XED_ICLASS_TPAUSE}, +{"TZCNT", XED_ICLASS_TZCNT}, +{"TZMSK", XED_ICLASS_TZMSK}, +{"UCOMISD", XED_ICLASS_UCOMISD}, +{"UCOMISS", XED_ICLASS_UCOMISS}, +{"UD0", XED_ICLASS_UD0}, +{"UD1", XED_ICLASS_UD1}, +{"UD2", XED_ICLASS_UD2}, +{"UIRET", XED_ICLASS_UIRET}, +{"UMONITOR", XED_ICLASS_UMONITOR}, +{"UMWAIT", XED_ICLASS_UMWAIT}, +{"UNPCKHPD", XED_ICLASS_UNPCKHPD}, +{"UNPCKHPS", XED_ICLASS_UNPCKHPS}, +{"UNPCKLPD", XED_ICLASS_UNPCKLPD}, +{"UNPCKLPS", XED_ICLASS_UNPCKLPS}, +{"V4FMADDPS", XED_ICLASS_V4FMADDPS}, +{"V4FMADDSS", XED_ICLASS_V4FMADDSS}, +{"V4FNMADDPS", XED_ICLASS_V4FNMADDPS}, +{"V4FNMADDSS", XED_ICLASS_V4FNMADDSS}, +{"VADDPD", XED_ICLASS_VADDPD}, +{"VADDPH", XED_ICLASS_VADDPH}, +{"VADDPS", XED_ICLASS_VADDPS}, +{"VADDSD", XED_ICLASS_VADDSD}, +{"VADDSH", XED_ICLASS_VADDSH}, +{"VADDSS", XED_ICLASS_VADDSS}, +{"VADDSUBPD", XED_ICLASS_VADDSUBPD}, +{"VADDSUBPS", XED_ICLASS_VADDSUBPS}, +{"VAESDEC", XED_ICLASS_VAESDEC}, +{"VAESDECLAST", XED_ICLASS_VAESDECLAST}, +{"VAESENC", XED_ICLASS_VAESENC}, +{"VAESENCLAST", XED_ICLASS_VAESENCLAST}, +{"VAESIMC", XED_ICLASS_VAESIMC}, +{"VAESKEYGENASSIST", XED_ICLASS_VAESKEYGENASSIST}, +{"VALIGND", XED_ICLASS_VALIGND}, +{"VALIGNQ", XED_ICLASS_VALIGNQ}, +{"VANDNPD", XED_ICLASS_VANDNPD}, +{"VANDNPS", XED_ICLASS_VANDNPS}, +{"VANDPD", XED_ICLASS_VANDPD}, +{"VANDPS", XED_ICLASS_VANDPS}, +{"VBLENDMPD", XED_ICLASS_VBLENDMPD}, +{"VBLENDMPS", XED_ICLASS_VBLENDMPS}, +{"VBLENDPD", XED_ICLASS_VBLENDPD}, +{"VBLENDPS", XED_ICLASS_VBLENDPS}, +{"VBLENDVPD", XED_ICLASS_VBLENDVPD}, +{"VBLENDVPS", XED_ICLASS_VBLENDVPS}, +{"VBROADCASTF128", XED_ICLASS_VBROADCASTF128}, +{"VBROADCASTF32X2", XED_ICLASS_VBROADCASTF32X2}, +{"VBROADCASTF32X4", XED_ICLASS_VBROADCASTF32X4}, +{"VBROADCASTF32X8", XED_ICLASS_VBROADCASTF32X8}, +{"VBROADCASTF64X2", XED_ICLASS_VBROADCASTF64X2}, +{"VBROADCASTF64X4", XED_ICLASS_VBROADCASTF64X4}, +{"VBROADCASTI128", XED_ICLASS_VBROADCASTI128}, +{"VBROADCASTI32X2", XED_ICLASS_VBROADCASTI32X2}, +{"VBROADCASTI32X4", XED_ICLASS_VBROADCASTI32X4}, +{"VBROADCASTI32X8", XED_ICLASS_VBROADCASTI32X8}, +{"VBROADCASTI64X2", XED_ICLASS_VBROADCASTI64X2}, +{"VBROADCASTI64X4", XED_ICLASS_VBROADCASTI64X4}, +{"VBROADCASTSD", XED_ICLASS_VBROADCASTSD}, +{"VBROADCASTSS", XED_ICLASS_VBROADCASTSS}, +{"VCMPPD", XED_ICLASS_VCMPPD}, +{"VCMPPH", XED_ICLASS_VCMPPH}, +{"VCMPPS", XED_ICLASS_VCMPPS}, +{"VCMPSD", XED_ICLASS_VCMPSD}, +{"VCMPSH", XED_ICLASS_VCMPSH}, +{"VCMPSS", XED_ICLASS_VCMPSS}, +{"VCOMISD", XED_ICLASS_VCOMISD}, +{"VCOMISH", XED_ICLASS_VCOMISH}, +{"VCOMISS", XED_ICLASS_VCOMISS}, +{"VCOMPRESSPD", XED_ICLASS_VCOMPRESSPD}, +{"VCOMPRESSPS", XED_ICLASS_VCOMPRESSPS}, +{"VCVTDQ2PD", XED_ICLASS_VCVTDQ2PD}, +{"VCVTDQ2PH", XED_ICLASS_VCVTDQ2PH}, +{"VCVTDQ2PS", XED_ICLASS_VCVTDQ2PS}, +{"VCVTNE2PS2BF16", XED_ICLASS_VCVTNE2PS2BF16}, +{"VCVTNEPS2BF16", XED_ICLASS_VCVTNEPS2BF16}, +{"VCVTPD2DQ", XED_ICLASS_VCVTPD2DQ}, +{"VCVTPD2PH", XED_ICLASS_VCVTPD2PH}, +{"VCVTPD2PS", XED_ICLASS_VCVTPD2PS}, +{"VCVTPD2QQ", XED_ICLASS_VCVTPD2QQ}, +{"VCVTPD2UDQ", XED_ICLASS_VCVTPD2UDQ}, +{"VCVTPD2UQQ", XED_ICLASS_VCVTPD2UQQ}, +{"VCVTPH2DQ", XED_ICLASS_VCVTPH2DQ}, +{"VCVTPH2PD", XED_ICLASS_VCVTPH2PD}, +{"VCVTPH2PS", XED_ICLASS_VCVTPH2PS}, +{"VCVTPH2PSX", XED_ICLASS_VCVTPH2PSX}, +{"VCVTPH2QQ", XED_ICLASS_VCVTPH2QQ}, +{"VCVTPH2UDQ", XED_ICLASS_VCVTPH2UDQ}, +{"VCVTPH2UQQ", XED_ICLASS_VCVTPH2UQQ}, +{"VCVTPH2UW", XED_ICLASS_VCVTPH2UW}, +{"VCVTPH2W", XED_ICLASS_VCVTPH2W}, +{"VCVTPS2DQ", XED_ICLASS_VCVTPS2DQ}, +{"VCVTPS2PD", XED_ICLASS_VCVTPS2PD}, +{"VCVTPS2PH", XED_ICLASS_VCVTPS2PH}, +{"VCVTPS2PHX", XED_ICLASS_VCVTPS2PHX}, +{"VCVTPS2QQ", XED_ICLASS_VCVTPS2QQ}, +{"VCVTPS2UDQ", XED_ICLASS_VCVTPS2UDQ}, +{"VCVTPS2UQQ", XED_ICLASS_VCVTPS2UQQ}, +{"VCVTQQ2PD", XED_ICLASS_VCVTQQ2PD}, +{"VCVTQQ2PH", XED_ICLASS_VCVTQQ2PH}, +{"VCVTQQ2PS", XED_ICLASS_VCVTQQ2PS}, +{"VCVTSD2SH", XED_ICLASS_VCVTSD2SH}, +{"VCVTSD2SI", XED_ICLASS_VCVTSD2SI}, +{"VCVTSD2SS", XED_ICLASS_VCVTSD2SS}, +{"VCVTSD2USI", XED_ICLASS_VCVTSD2USI}, +{"VCVTSH2SD", XED_ICLASS_VCVTSH2SD}, +{"VCVTSH2SI", XED_ICLASS_VCVTSH2SI}, +{"VCVTSH2SS", XED_ICLASS_VCVTSH2SS}, +{"VCVTSH2USI", XED_ICLASS_VCVTSH2USI}, +{"VCVTSI2SD", XED_ICLASS_VCVTSI2SD}, +{"VCVTSI2SH", XED_ICLASS_VCVTSI2SH}, +{"VCVTSI2SS", XED_ICLASS_VCVTSI2SS}, +{"VCVTSS2SD", XED_ICLASS_VCVTSS2SD}, +{"VCVTSS2SH", XED_ICLASS_VCVTSS2SH}, +{"VCVTSS2SI", XED_ICLASS_VCVTSS2SI}, +{"VCVTSS2USI", XED_ICLASS_VCVTSS2USI}, +{"VCVTTPD2DQ", XED_ICLASS_VCVTTPD2DQ}, +{"VCVTTPD2QQ", XED_ICLASS_VCVTTPD2QQ}, +{"VCVTTPD2UDQ", XED_ICLASS_VCVTTPD2UDQ}, +{"VCVTTPD2UQQ", XED_ICLASS_VCVTTPD2UQQ}, +{"VCVTTPH2DQ", XED_ICLASS_VCVTTPH2DQ}, +{"VCVTTPH2QQ", XED_ICLASS_VCVTTPH2QQ}, +{"VCVTTPH2UDQ", XED_ICLASS_VCVTTPH2UDQ}, +{"VCVTTPH2UQQ", XED_ICLASS_VCVTTPH2UQQ}, +{"VCVTTPH2UW", XED_ICLASS_VCVTTPH2UW}, +{"VCVTTPH2W", XED_ICLASS_VCVTTPH2W}, +{"VCVTTPS2DQ", XED_ICLASS_VCVTTPS2DQ}, +{"VCVTTPS2QQ", XED_ICLASS_VCVTTPS2QQ}, +{"VCVTTPS2UDQ", XED_ICLASS_VCVTTPS2UDQ}, +{"VCVTTPS2UQQ", XED_ICLASS_VCVTTPS2UQQ}, +{"VCVTTSD2SI", XED_ICLASS_VCVTTSD2SI}, +{"VCVTTSD2USI", XED_ICLASS_VCVTTSD2USI}, +{"VCVTTSH2SI", XED_ICLASS_VCVTTSH2SI}, +{"VCVTTSH2USI", XED_ICLASS_VCVTTSH2USI}, +{"VCVTTSS2SI", XED_ICLASS_VCVTTSS2SI}, +{"VCVTTSS2USI", XED_ICLASS_VCVTTSS2USI}, +{"VCVTUDQ2PD", XED_ICLASS_VCVTUDQ2PD}, +{"VCVTUDQ2PH", XED_ICLASS_VCVTUDQ2PH}, +{"VCVTUDQ2PS", XED_ICLASS_VCVTUDQ2PS}, +{"VCVTUQQ2PD", XED_ICLASS_VCVTUQQ2PD}, +{"VCVTUQQ2PH", XED_ICLASS_VCVTUQQ2PH}, +{"VCVTUQQ2PS", XED_ICLASS_VCVTUQQ2PS}, +{"VCVTUSI2SD", XED_ICLASS_VCVTUSI2SD}, +{"VCVTUSI2SH", XED_ICLASS_VCVTUSI2SH}, +{"VCVTUSI2SS", XED_ICLASS_VCVTUSI2SS}, +{"VCVTUW2PH", XED_ICLASS_VCVTUW2PH}, +{"VCVTW2PH", XED_ICLASS_VCVTW2PH}, +{"VDBPSADBW", XED_ICLASS_VDBPSADBW}, +{"VDIVPD", XED_ICLASS_VDIVPD}, +{"VDIVPH", XED_ICLASS_VDIVPH}, +{"VDIVPS", XED_ICLASS_VDIVPS}, +{"VDIVSD", XED_ICLASS_VDIVSD}, +{"VDIVSH", XED_ICLASS_VDIVSH}, +{"VDIVSS", XED_ICLASS_VDIVSS}, +{"VDPBF16PS", XED_ICLASS_VDPBF16PS}, +{"VDPPD", XED_ICLASS_VDPPD}, +{"VDPPS", XED_ICLASS_VDPPS}, +{"VERR", XED_ICLASS_VERR}, +{"VERW", XED_ICLASS_VERW}, +{"VEXP2PD", XED_ICLASS_VEXP2PD}, +{"VEXP2PS", XED_ICLASS_VEXP2PS}, +{"VEXPANDPD", XED_ICLASS_VEXPANDPD}, +{"VEXPANDPS", XED_ICLASS_VEXPANDPS}, +{"VEXTRACTF128", XED_ICLASS_VEXTRACTF128}, +{"VEXTRACTF32X4", XED_ICLASS_VEXTRACTF32X4}, +{"VEXTRACTF32X8", XED_ICLASS_VEXTRACTF32X8}, +{"VEXTRACTF64X2", XED_ICLASS_VEXTRACTF64X2}, +{"VEXTRACTF64X4", XED_ICLASS_VEXTRACTF64X4}, +{"VEXTRACTI128", XED_ICLASS_VEXTRACTI128}, +{"VEXTRACTI32X4", XED_ICLASS_VEXTRACTI32X4}, +{"VEXTRACTI32X8", XED_ICLASS_VEXTRACTI32X8}, +{"VEXTRACTI64X2", XED_ICLASS_VEXTRACTI64X2}, +{"VEXTRACTI64X4", XED_ICLASS_VEXTRACTI64X4}, +{"VEXTRACTPS", XED_ICLASS_VEXTRACTPS}, +{"VFCMADDCPH", XED_ICLASS_VFCMADDCPH}, +{"VFCMADDCSH", XED_ICLASS_VFCMADDCSH}, +{"VFCMULCPH", XED_ICLASS_VFCMULCPH}, +{"VFCMULCSH", XED_ICLASS_VFCMULCSH}, +{"VFIXUPIMMPD", XED_ICLASS_VFIXUPIMMPD}, +{"VFIXUPIMMPS", XED_ICLASS_VFIXUPIMMPS}, +{"VFIXUPIMMSD", XED_ICLASS_VFIXUPIMMSD}, +{"VFIXUPIMMSS", XED_ICLASS_VFIXUPIMMSS}, +{"VFMADD132PD", XED_ICLASS_VFMADD132PD}, +{"VFMADD132PH", XED_ICLASS_VFMADD132PH}, +{"VFMADD132PS", XED_ICLASS_VFMADD132PS}, +{"VFMADD132SD", XED_ICLASS_VFMADD132SD}, +{"VFMADD132SH", XED_ICLASS_VFMADD132SH}, +{"VFMADD132SS", XED_ICLASS_VFMADD132SS}, +{"VFMADD213PD", XED_ICLASS_VFMADD213PD}, +{"VFMADD213PH", XED_ICLASS_VFMADD213PH}, +{"VFMADD213PS", XED_ICLASS_VFMADD213PS}, +{"VFMADD213SD", XED_ICLASS_VFMADD213SD}, +{"VFMADD213SH", XED_ICLASS_VFMADD213SH}, +{"VFMADD213SS", XED_ICLASS_VFMADD213SS}, +{"VFMADD231PD", XED_ICLASS_VFMADD231PD}, +{"VFMADD231PH", XED_ICLASS_VFMADD231PH}, +{"VFMADD231PS", XED_ICLASS_VFMADD231PS}, +{"VFMADD231SD", XED_ICLASS_VFMADD231SD}, +{"VFMADD231SH", XED_ICLASS_VFMADD231SH}, +{"VFMADD231SS", XED_ICLASS_VFMADD231SS}, +{"VFMADDCPH", XED_ICLASS_VFMADDCPH}, +{"VFMADDCSH", XED_ICLASS_VFMADDCSH}, +{"VFMADDPD", XED_ICLASS_VFMADDPD}, +{"VFMADDPS", XED_ICLASS_VFMADDPS}, +{"VFMADDSD", XED_ICLASS_VFMADDSD}, +{"VFMADDSS", XED_ICLASS_VFMADDSS}, +{"VFMADDSUB132PD", XED_ICLASS_VFMADDSUB132PD}, +{"VFMADDSUB132PH", XED_ICLASS_VFMADDSUB132PH}, +{"VFMADDSUB132PS", XED_ICLASS_VFMADDSUB132PS}, +{"VFMADDSUB213PD", XED_ICLASS_VFMADDSUB213PD}, +{"VFMADDSUB213PH", XED_ICLASS_VFMADDSUB213PH}, +{"VFMADDSUB213PS", XED_ICLASS_VFMADDSUB213PS}, +{"VFMADDSUB231PD", XED_ICLASS_VFMADDSUB231PD}, +{"VFMADDSUB231PH", XED_ICLASS_VFMADDSUB231PH}, +{"VFMADDSUB231PS", XED_ICLASS_VFMADDSUB231PS}, +{"VFMADDSUBPD", XED_ICLASS_VFMADDSUBPD}, +{"VFMADDSUBPS", XED_ICLASS_VFMADDSUBPS}, +{"VFMSUB132PD", XED_ICLASS_VFMSUB132PD}, +{"VFMSUB132PH", XED_ICLASS_VFMSUB132PH}, +{"VFMSUB132PS", XED_ICLASS_VFMSUB132PS}, +{"VFMSUB132SD", XED_ICLASS_VFMSUB132SD}, +{"VFMSUB132SH", XED_ICLASS_VFMSUB132SH}, +{"VFMSUB132SS", XED_ICLASS_VFMSUB132SS}, +{"VFMSUB213PD", XED_ICLASS_VFMSUB213PD}, +{"VFMSUB213PH", XED_ICLASS_VFMSUB213PH}, +{"VFMSUB213PS", XED_ICLASS_VFMSUB213PS}, +{"VFMSUB213SD", XED_ICLASS_VFMSUB213SD}, +{"VFMSUB213SH", XED_ICLASS_VFMSUB213SH}, +{"VFMSUB213SS", XED_ICLASS_VFMSUB213SS}, +{"VFMSUB231PD", XED_ICLASS_VFMSUB231PD}, +{"VFMSUB231PH", XED_ICLASS_VFMSUB231PH}, +{"VFMSUB231PS", XED_ICLASS_VFMSUB231PS}, +{"VFMSUB231SD", XED_ICLASS_VFMSUB231SD}, +{"VFMSUB231SH", XED_ICLASS_VFMSUB231SH}, +{"VFMSUB231SS", XED_ICLASS_VFMSUB231SS}, +{"VFMSUBADD132PD", XED_ICLASS_VFMSUBADD132PD}, +{"VFMSUBADD132PH", XED_ICLASS_VFMSUBADD132PH}, +{"VFMSUBADD132PS", XED_ICLASS_VFMSUBADD132PS}, +{"VFMSUBADD213PD", XED_ICLASS_VFMSUBADD213PD}, +{"VFMSUBADD213PH", XED_ICLASS_VFMSUBADD213PH}, +{"VFMSUBADD213PS", XED_ICLASS_VFMSUBADD213PS}, +{"VFMSUBADD231PD", XED_ICLASS_VFMSUBADD231PD}, +{"VFMSUBADD231PH", XED_ICLASS_VFMSUBADD231PH}, +{"VFMSUBADD231PS", XED_ICLASS_VFMSUBADD231PS}, +{"VFMSUBADDPD", XED_ICLASS_VFMSUBADDPD}, +{"VFMSUBADDPS", XED_ICLASS_VFMSUBADDPS}, +{"VFMSUBPD", XED_ICLASS_VFMSUBPD}, +{"VFMSUBPS", XED_ICLASS_VFMSUBPS}, +{"VFMSUBSD", XED_ICLASS_VFMSUBSD}, +{"VFMSUBSS", XED_ICLASS_VFMSUBSS}, +{"VFMULCPH", XED_ICLASS_VFMULCPH}, +{"VFMULCSH", XED_ICLASS_VFMULCSH}, +{"VFNMADD132PD", XED_ICLASS_VFNMADD132PD}, +{"VFNMADD132PH", XED_ICLASS_VFNMADD132PH}, +{"VFNMADD132PS", XED_ICLASS_VFNMADD132PS}, +{"VFNMADD132SD", XED_ICLASS_VFNMADD132SD}, +{"VFNMADD132SH", XED_ICLASS_VFNMADD132SH}, +{"VFNMADD132SS", XED_ICLASS_VFNMADD132SS}, +{"VFNMADD213PD", XED_ICLASS_VFNMADD213PD}, +{"VFNMADD213PH", XED_ICLASS_VFNMADD213PH}, +{"VFNMADD213PS", XED_ICLASS_VFNMADD213PS}, +{"VFNMADD213SD", XED_ICLASS_VFNMADD213SD}, +{"VFNMADD213SH", XED_ICLASS_VFNMADD213SH}, +{"VFNMADD213SS", XED_ICLASS_VFNMADD213SS}, +{"VFNMADD231PD", XED_ICLASS_VFNMADD231PD}, +{"VFNMADD231PH", XED_ICLASS_VFNMADD231PH}, +{"VFNMADD231PS", XED_ICLASS_VFNMADD231PS}, +{"VFNMADD231SD", XED_ICLASS_VFNMADD231SD}, +{"VFNMADD231SH", XED_ICLASS_VFNMADD231SH}, +{"VFNMADD231SS", XED_ICLASS_VFNMADD231SS}, +{"VFNMADDPD", XED_ICLASS_VFNMADDPD}, +{"VFNMADDPS", XED_ICLASS_VFNMADDPS}, +{"VFNMADDSD", XED_ICLASS_VFNMADDSD}, +{"VFNMADDSS", XED_ICLASS_VFNMADDSS}, +{"VFNMSUB132PD", XED_ICLASS_VFNMSUB132PD}, +{"VFNMSUB132PH", XED_ICLASS_VFNMSUB132PH}, +{"VFNMSUB132PS", XED_ICLASS_VFNMSUB132PS}, +{"VFNMSUB132SD", XED_ICLASS_VFNMSUB132SD}, +{"VFNMSUB132SH", XED_ICLASS_VFNMSUB132SH}, +{"VFNMSUB132SS", XED_ICLASS_VFNMSUB132SS}, +{"VFNMSUB213PD", XED_ICLASS_VFNMSUB213PD}, +{"VFNMSUB213PH", XED_ICLASS_VFNMSUB213PH}, +{"VFNMSUB213PS", XED_ICLASS_VFNMSUB213PS}, +{"VFNMSUB213SD", XED_ICLASS_VFNMSUB213SD}, +{"VFNMSUB213SH", XED_ICLASS_VFNMSUB213SH}, +{"VFNMSUB213SS", XED_ICLASS_VFNMSUB213SS}, +{"VFNMSUB231PD", XED_ICLASS_VFNMSUB231PD}, +{"VFNMSUB231PH", XED_ICLASS_VFNMSUB231PH}, +{"VFNMSUB231PS", XED_ICLASS_VFNMSUB231PS}, +{"VFNMSUB231SD", XED_ICLASS_VFNMSUB231SD}, +{"VFNMSUB231SH", XED_ICLASS_VFNMSUB231SH}, +{"VFNMSUB231SS", XED_ICLASS_VFNMSUB231SS}, +{"VFNMSUBPD", XED_ICLASS_VFNMSUBPD}, +{"VFNMSUBPS", XED_ICLASS_VFNMSUBPS}, +{"VFNMSUBSD", XED_ICLASS_VFNMSUBSD}, +{"VFNMSUBSS", XED_ICLASS_VFNMSUBSS}, +{"VFPCLASSPD", XED_ICLASS_VFPCLASSPD}, +{"VFPCLASSPH", XED_ICLASS_VFPCLASSPH}, +{"VFPCLASSPS", XED_ICLASS_VFPCLASSPS}, +{"VFPCLASSSD", XED_ICLASS_VFPCLASSSD}, +{"VFPCLASSSH", XED_ICLASS_VFPCLASSSH}, +{"VFPCLASSSS", XED_ICLASS_VFPCLASSSS}, +{"VFRCZPD", XED_ICLASS_VFRCZPD}, +{"VFRCZPS", XED_ICLASS_VFRCZPS}, +{"VFRCZSD", XED_ICLASS_VFRCZSD}, +{"VFRCZSS", XED_ICLASS_VFRCZSS}, +{"VGATHERDPD", XED_ICLASS_VGATHERDPD}, +{"VGATHERDPS", XED_ICLASS_VGATHERDPS}, +{"VGATHERPF0DPD", XED_ICLASS_VGATHERPF0DPD}, +{"VGATHERPF0DPS", XED_ICLASS_VGATHERPF0DPS}, +{"VGATHERPF0QPD", XED_ICLASS_VGATHERPF0QPD}, +{"VGATHERPF0QPS", XED_ICLASS_VGATHERPF0QPS}, +{"VGATHERPF1DPD", XED_ICLASS_VGATHERPF1DPD}, +{"VGATHERPF1DPS", XED_ICLASS_VGATHERPF1DPS}, +{"VGATHERPF1QPD", XED_ICLASS_VGATHERPF1QPD}, +{"VGATHERPF1QPS", XED_ICLASS_VGATHERPF1QPS}, +{"VGATHERQPD", XED_ICLASS_VGATHERQPD}, +{"VGATHERQPS", XED_ICLASS_VGATHERQPS}, +{"VGETEXPPD", XED_ICLASS_VGETEXPPD}, +{"VGETEXPPH", XED_ICLASS_VGETEXPPH}, +{"VGETEXPPS", XED_ICLASS_VGETEXPPS}, +{"VGETEXPSD", XED_ICLASS_VGETEXPSD}, +{"VGETEXPSH", XED_ICLASS_VGETEXPSH}, +{"VGETEXPSS", XED_ICLASS_VGETEXPSS}, +{"VGETMANTPD", XED_ICLASS_VGETMANTPD}, +{"VGETMANTPH", XED_ICLASS_VGETMANTPH}, +{"VGETMANTPS", XED_ICLASS_VGETMANTPS}, +{"VGETMANTSD", XED_ICLASS_VGETMANTSD}, +{"VGETMANTSH", XED_ICLASS_VGETMANTSH}, +{"VGETMANTSS", XED_ICLASS_VGETMANTSS}, +{"VGF2P8AFFINEINVQB", XED_ICLASS_VGF2P8AFFINEINVQB}, +{"VGF2P8AFFINEQB", XED_ICLASS_VGF2P8AFFINEQB}, +{"VGF2P8MULB", XED_ICLASS_VGF2P8MULB}, +{"VHADDPD", XED_ICLASS_VHADDPD}, +{"VHADDPS", XED_ICLASS_VHADDPS}, +{"VHSUBPD", XED_ICLASS_VHSUBPD}, +{"VHSUBPS", XED_ICLASS_VHSUBPS}, +{"VINSERTF128", XED_ICLASS_VINSERTF128}, +{"VINSERTF32X4", XED_ICLASS_VINSERTF32X4}, +{"VINSERTF32X8", XED_ICLASS_VINSERTF32X8}, +{"VINSERTF64X2", XED_ICLASS_VINSERTF64X2}, +{"VINSERTF64X4", XED_ICLASS_VINSERTF64X4}, +{"VINSERTI128", XED_ICLASS_VINSERTI128}, +{"VINSERTI32X4", XED_ICLASS_VINSERTI32X4}, +{"VINSERTI32X8", XED_ICLASS_VINSERTI32X8}, +{"VINSERTI64X2", XED_ICLASS_VINSERTI64X2}, +{"VINSERTI64X4", XED_ICLASS_VINSERTI64X4}, +{"VINSERTPS", XED_ICLASS_VINSERTPS}, +{"VLDDQU", XED_ICLASS_VLDDQU}, +{"VLDMXCSR", XED_ICLASS_VLDMXCSR}, +{"VMASKMOVDQU", XED_ICLASS_VMASKMOVDQU}, +{"VMASKMOVPD", XED_ICLASS_VMASKMOVPD}, +{"VMASKMOVPS", XED_ICLASS_VMASKMOVPS}, +{"VMAXPD", XED_ICLASS_VMAXPD}, +{"VMAXPH", XED_ICLASS_VMAXPH}, +{"VMAXPS", XED_ICLASS_VMAXPS}, +{"VMAXSD", XED_ICLASS_VMAXSD}, +{"VMAXSH", XED_ICLASS_VMAXSH}, +{"VMAXSS", XED_ICLASS_VMAXSS}, +{"VMCALL", XED_ICLASS_VMCALL}, +{"VMCLEAR", XED_ICLASS_VMCLEAR}, +{"VMFUNC", XED_ICLASS_VMFUNC}, +{"VMINPD", XED_ICLASS_VMINPD}, +{"VMINPH", XED_ICLASS_VMINPH}, +{"VMINPS", XED_ICLASS_VMINPS}, +{"VMINSD", XED_ICLASS_VMINSD}, +{"VMINSH", XED_ICLASS_VMINSH}, +{"VMINSS", XED_ICLASS_VMINSS}, +{"VMLAUNCH", XED_ICLASS_VMLAUNCH}, +{"VMLOAD", XED_ICLASS_VMLOAD}, +{"VMMCALL", XED_ICLASS_VMMCALL}, +{"VMOVAPD", XED_ICLASS_VMOVAPD}, +{"VMOVAPS", XED_ICLASS_VMOVAPS}, +{"VMOVD", XED_ICLASS_VMOVD}, +{"VMOVDDUP", XED_ICLASS_VMOVDDUP}, +{"VMOVDQA", XED_ICLASS_VMOVDQA}, +{"VMOVDQA32", XED_ICLASS_VMOVDQA32}, +{"VMOVDQA64", XED_ICLASS_VMOVDQA64}, +{"VMOVDQU", XED_ICLASS_VMOVDQU}, +{"VMOVDQU16", XED_ICLASS_VMOVDQU16}, +{"VMOVDQU32", XED_ICLASS_VMOVDQU32}, +{"VMOVDQU64", XED_ICLASS_VMOVDQU64}, +{"VMOVDQU8", XED_ICLASS_VMOVDQU8}, +{"VMOVHLPS", XED_ICLASS_VMOVHLPS}, +{"VMOVHPD", XED_ICLASS_VMOVHPD}, +{"VMOVHPS", XED_ICLASS_VMOVHPS}, +{"VMOVLHPS", XED_ICLASS_VMOVLHPS}, +{"VMOVLPD", XED_ICLASS_VMOVLPD}, +{"VMOVLPS", XED_ICLASS_VMOVLPS}, +{"VMOVMSKPD", XED_ICLASS_VMOVMSKPD}, +{"VMOVMSKPS", XED_ICLASS_VMOVMSKPS}, +{"VMOVNTDQ", XED_ICLASS_VMOVNTDQ}, +{"VMOVNTDQA", XED_ICLASS_VMOVNTDQA}, +{"VMOVNTPD", XED_ICLASS_VMOVNTPD}, +{"VMOVNTPS", XED_ICLASS_VMOVNTPS}, +{"VMOVQ", XED_ICLASS_VMOVQ}, +{"VMOVSD", XED_ICLASS_VMOVSD}, +{"VMOVSH", XED_ICLASS_VMOVSH}, +{"VMOVSHDUP", XED_ICLASS_VMOVSHDUP}, +{"VMOVSLDUP", XED_ICLASS_VMOVSLDUP}, +{"VMOVSS", XED_ICLASS_VMOVSS}, +{"VMOVUPD", XED_ICLASS_VMOVUPD}, +{"VMOVUPS", XED_ICLASS_VMOVUPS}, +{"VMOVW", XED_ICLASS_VMOVW}, +{"VMPSADBW", XED_ICLASS_VMPSADBW}, +{"VMPTRLD", XED_ICLASS_VMPTRLD}, +{"VMPTRST", XED_ICLASS_VMPTRST}, +{"VMREAD", XED_ICLASS_VMREAD}, +{"VMRESUME", XED_ICLASS_VMRESUME}, +{"VMRUN", XED_ICLASS_VMRUN}, +{"VMSAVE", XED_ICLASS_VMSAVE}, +{"VMULPD", XED_ICLASS_VMULPD}, +{"VMULPH", XED_ICLASS_VMULPH}, +{"VMULPS", XED_ICLASS_VMULPS}, +{"VMULSD", XED_ICLASS_VMULSD}, +{"VMULSH", XED_ICLASS_VMULSH}, +{"VMULSS", XED_ICLASS_VMULSS}, +{"VMWRITE", XED_ICLASS_VMWRITE}, +{"VMXOFF", XED_ICLASS_VMXOFF}, +{"VMXON", XED_ICLASS_VMXON}, +{"VORPD", XED_ICLASS_VORPD}, +{"VORPS", XED_ICLASS_VORPS}, +{"VP2INTERSECTD", XED_ICLASS_VP2INTERSECTD}, +{"VP2INTERSECTQ", XED_ICLASS_VP2INTERSECTQ}, +{"VP4DPWSSD", XED_ICLASS_VP4DPWSSD}, +{"VP4DPWSSDS", XED_ICLASS_VP4DPWSSDS}, +{"VPABSB", XED_ICLASS_VPABSB}, +{"VPABSD", XED_ICLASS_VPABSD}, +{"VPABSQ", XED_ICLASS_VPABSQ}, +{"VPABSW", XED_ICLASS_VPABSW}, +{"VPACKSSDW", XED_ICLASS_VPACKSSDW}, +{"VPACKSSWB", XED_ICLASS_VPACKSSWB}, +{"VPACKUSDW", XED_ICLASS_VPACKUSDW}, +{"VPACKUSWB", XED_ICLASS_VPACKUSWB}, +{"VPADDB", XED_ICLASS_VPADDB}, +{"VPADDD", XED_ICLASS_VPADDD}, +{"VPADDQ", XED_ICLASS_VPADDQ}, +{"VPADDSB", XED_ICLASS_VPADDSB}, +{"VPADDSW", XED_ICLASS_VPADDSW}, +{"VPADDUSB", XED_ICLASS_VPADDUSB}, +{"VPADDUSW", XED_ICLASS_VPADDUSW}, +{"VPADDW", XED_ICLASS_VPADDW}, +{"VPALIGNR", XED_ICLASS_VPALIGNR}, +{"VPAND", XED_ICLASS_VPAND}, +{"VPANDD", XED_ICLASS_VPANDD}, +{"VPANDN", XED_ICLASS_VPANDN}, +{"VPANDND", XED_ICLASS_VPANDND}, +{"VPANDNQ", XED_ICLASS_VPANDNQ}, +{"VPANDQ", XED_ICLASS_VPANDQ}, +{"VPAVGB", XED_ICLASS_VPAVGB}, +{"VPAVGW", XED_ICLASS_VPAVGW}, +{"VPBLENDD", XED_ICLASS_VPBLENDD}, +{"VPBLENDMB", XED_ICLASS_VPBLENDMB}, +{"VPBLENDMD", XED_ICLASS_VPBLENDMD}, +{"VPBLENDMQ", XED_ICLASS_VPBLENDMQ}, +{"VPBLENDMW", XED_ICLASS_VPBLENDMW}, +{"VPBLENDVB", XED_ICLASS_VPBLENDVB}, +{"VPBLENDW", XED_ICLASS_VPBLENDW}, +{"VPBROADCASTB", XED_ICLASS_VPBROADCASTB}, +{"VPBROADCASTD", XED_ICLASS_VPBROADCASTD}, +{"VPBROADCASTMB2Q", XED_ICLASS_VPBROADCASTMB2Q}, +{"VPBROADCASTMW2D", XED_ICLASS_VPBROADCASTMW2D}, +{"VPBROADCASTQ", XED_ICLASS_VPBROADCASTQ}, +{"VPBROADCASTW", XED_ICLASS_VPBROADCASTW}, +{"VPCLMULQDQ", XED_ICLASS_VPCLMULQDQ}, +{"VPCMOV", XED_ICLASS_VPCMOV}, +{"VPCMPB", XED_ICLASS_VPCMPB}, +{"VPCMPD", XED_ICLASS_VPCMPD}, +{"VPCMPEQB", XED_ICLASS_VPCMPEQB}, +{"VPCMPEQD", XED_ICLASS_VPCMPEQD}, +{"VPCMPEQQ", XED_ICLASS_VPCMPEQQ}, +{"VPCMPEQW", XED_ICLASS_VPCMPEQW}, +{"VPCMPESTRI", XED_ICLASS_VPCMPESTRI}, +{"VPCMPESTRI64", XED_ICLASS_VPCMPESTRI64}, +{"VPCMPESTRM", XED_ICLASS_VPCMPESTRM}, +{"VPCMPESTRM64", XED_ICLASS_VPCMPESTRM64}, +{"VPCMPGTB", XED_ICLASS_VPCMPGTB}, +{"VPCMPGTD", XED_ICLASS_VPCMPGTD}, +{"VPCMPGTQ", XED_ICLASS_VPCMPGTQ}, +{"VPCMPGTW", XED_ICLASS_VPCMPGTW}, +{"VPCMPISTRI", XED_ICLASS_VPCMPISTRI}, +{"VPCMPISTRI64", XED_ICLASS_VPCMPISTRI64}, +{"VPCMPISTRM", XED_ICLASS_VPCMPISTRM}, +{"VPCMPQ", XED_ICLASS_VPCMPQ}, +{"VPCMPUB", XED_ICLASS_VPCMPUB}, +{"VPCMPUD", XED_ICLASS_VPCMPUD}, +{"VPCMPUQ", XED_ICLASS_VPCMPUQ}, +{"VPCMPUW", XED_ICLASS_VPCMPUW}, +{"VPCMPW", XED_ICLASS_VPCMPW}, +{"VPCOMB", XED_ICLASS_VPCOMB}, +{"VPCOMD", XED_ICLASS_VPCOMD}, +{"VPCOMPRESSB", XED_ICLASS_VPCOMPRESSB}, +{"VPCOMPRESSD", XED_ICLASS_VPCOMPRESSD}, +{"VPCOMPRESSQ", XED_ICLASS_VPCOMPRESSQ}, +{"VPCOMPRESSW", XED_ICLASS_VPCOMPRESSW}, +{"VPCOMQ", XED_ICLASS_VPCOMQ}, +{"VPCOMUB", XED_ICLASS_VPCOMUB}, +{"VPCOMUD", XED_ICLASS_VPCOMUD}, +{"VPCOMUQ", XED_ICLASS_VPCOMUQ}, +{"VPCOMUW", XED_ICLASS_VPCOMUW}, +{"VPCOMW", XED_ICLASS_VPCOMW}, +{"VPCONFLICTD", XED_ICLASS_VPCONFLICTD}, +{"VPCONFLICTQ", XED_ICLASS_VPCONFLICTQ}, +{"VPDPBUSD", XED_ICLASS_VPDPBUSD}, +{"VPDPBUSDS", XED_ICLASS_VPDPBUSDS}, +{"VPDPWSSD", XED_ICLASS_VPDPWSSD}, +{"VPDPWSSDS", XED_ICLASS_VPDPWSSDS}, +{"VPERM2F128", XED_ICLASS_VPERM2F128}, +{"VPERM2I128", XED_ICLASS_VPERM2I128}, +{"VPERMB", XED_ICLASS_VPERMB}, +{"VPERMD", XED_ICLASS_VPERMD}, +{"VPERMI2B", XED_ICLASS_VPERMI2B}, +{"VPERMI2D", XED_ICLASS_VPERMI2D}, +{"VPERMI2PD", XED_ICLASS_VPERMI2PD}, +{"VPERMI2PS", XED_ICLASS_VPERMI2PS}, +{"VPERMI2Q", XED_ICLASS_VPERMI2Q}, +{"VPERMI2W", XED_ICLASS_VPERMI2W}, +{"VPERMIL2PD", XED_ICLASS_VPERMIL2PD}, +{"VPERMIL2PS", XED_ICLASS_VPERMIL2PS}, +{"VPERMILPD", XED_ICLASS_VPERMILPD}, +{"VPERMILPS", XED_ICLASS_VPERMILPS}, +{"VPERMPD", XED_ICLASS_VPERMPD}, +{"VPERMPS", XED_ICLASS_VPERMPS}, +{"VPERMQ", XED_ICLASS_VPERMQ}, +{"VPERMT2B", XED_ICLASS_VPERMT2B}, +{"VPERMT2D", XED_ICLASS_VPERMT2D}, +{"VPERMT2PD", XED_ICLASS_VPERMT2PD}, +{"VPERMT2PS", XED_ICLASS_VPERMT2PS}, +{"VPERMT2Q", XED_ICLASS_VPERMT2Q}, +{"VPERMT2W", XED_ICLASS_VPERMT2W}, +{"VPERMW", XED_ICLASS_VPERMW}, +{"VPEXPANDB", XED_ICLASS_VPEXPANDB}, +{"VPEXPANDD", XED_ICLASS_VPEXPANDD}, +{"VPEXPANDQ", XED_ICLASS_VPEXPANDQ}, +{"VPEXPANDW", XED_ICLASS_VPEXPANDW}, +{"VPEXTRB", XED_ICLASS_VPEXTRB}, +{"VPEXTRD", XED_ICLASS_VPEXTRD}, +{"VPEXTRQ", XED_ICLASS_VPEXTRQ}, +{"VPEXTRW", XED_ICLASS_VPEXTRW}, +{"VPEXTRW_C5", XED_ICLASS_VPEXTRW_C5}, +{"VPGATHERDD", XED_ICLASS_VPGATHERDD}, +{"VPGATHERDQ", XED_ICLASS_VPGATHERDQ}, +{"VPGATHERQD", XED_ICLASS_VPGATHERQD}, +{"VPGATHERQQ", XED_ICLASS_VPGATHERQQ}, +{"VPHADDBD", XED_ICLASS_VPHADDBD}, +{"VPHADDBQ", XED_ICLASS_VPHADDBQ}, +{"VPHADDBW", XED_ICLASS_VPHADDBW}, +{"VPHADDD", XED_ICLASS_VPHADDD}, +{"VPHADDDQ", XED_ICLASS_VPHADDDQ}, +{"VPHADDSW", XED_ICLASS_VPHADDSW}, +{"VPHADDUBD", XED_ICLASS_VPHADDUBD}, +{"VPHADDUBQ", XED_ICLASS_VPHADDUBQ}, +{"VPHADDUBW", XED_ICLASS_VPHADDUBW}, +{"VPHADDUDQ", XED_ICLASS_VPHADDUDQ}, +{"VPHADDUWD", XED_ICLASS_VPHADDUWD}, +{"VPHADDUWQ", XED_ICLASS_VPHADDUWQ}, +{"VPHADDW", XED_ICLASS_VPHADDW}, +{"VPHADDWD", XED_ICLASS_VPHADDWD}, +{"VPHADDWQ", XED_ICLASS_VPHADDWQ}, +{"VPHMINPOSUW", XED_ICLASS_VPHMINPOSUW}, +{"VPHSUBBW", XED_ICLASS_VPHSUBBW}, +{"VPHSUBD", XED_ICLASS_VPHSUBD}, +{"VPHSUBDQ", XED_ICLASS_VPHSUBDQ}, +{"VPHSUBSW", XED_ICLASS_VPHSUBSW}, +{"VPHSUBW", XED_ICLASS_VPHSUBW}, +{"VPHSUBWD", XED_ICLASS_VPHSUBWD}, +{"VPINSRB", XED_ICLASS_VPINSRB}, +{"VPINSRD", XED_ICLASS_VPINSRD}, +{"VPINSRQ", XED_ICLASS_VPINSRQ}, +{"VPINSRW", XED_ICLASS_VPINSRW}, +{"VPLZCNTD", XED_ICLASS_VPLZCNTD}, +{"VPLZCNTQ", XED_ICLASS_VPLZCNTQ}, +{"VPMACSDD", XED_ICLASS_VPMACSDD}, +{"VPMACSDQH", XED_ICLASS_VPMACSDQH}, +{"VPMACSDQL", XED_ICLASS_VPMACSDQL}, +{"VPMACSSDD", XED_ICLASS_VPMACSSDD}, +{"VPMACSSDQH", XED_ICLASS_VPMACSSDQH}, +{"VPMACSSDQL", XED_ICLASS_VPMACSSDQL}, +{"VPMACSSWD", XED_ICLASS_VPMACSSWD}, +{"VPMACSSWW", XED_ICLASS_VPMACSSWW}, +{"VPMACSWD", XED_ICLASS_VPMACSWD}, +{"VPMACSWW", XED_ICLASS_VPMACSWW}, +{"VPMADCSSWD", XED_ICLASS_VPMADCSSWD}, +{"VPMADCSWD", XED_ICLASS_VPMADCSWD}, +{"VPMADD52HUQ", XED_ICLASS_VPMADD52HUQ}, +{"VPMADD52LUQ", XED_ICLASS_VPMADD52LUQ}, +{"VPMADDUBSW", XED_ICLASS_VPMADDUBSW}, +{"VPMADDWD", XED_ICLASS_VPMADDWD}, +{"VPMASKMOVD", XED_ICLASS_VPMASKMOVD}, +{"VPMASKMOVQ", XED_ICLASS_VPMASKMOVQ}, +{"VPMAXSB", XED_ICLASS_VPMAXSB}, +{"VPMAXSD", XED_ICLASS_VPMAXSD}, +{"VPMAXSQ", XED_ICLASS_VPMAXSQ}, +{"VPMAXSW", XED_ICLASS_VPMAXSW}, +{"VPMAXUB", XED_ICLASS_VPMAXUB}, +{"VPMAXUD", XED_ICLASS_VPMAXUD}, +{"VPMAXUQ", XED_ICLASS_VPMAXUQ}, +{"VPMAXUW", XED_ICLASS_VPMAXUW}, +{"VPMINSB", XED_ICLASS_VPMINSB}, +{"VPMINSD", XED_ICLASS_VPMINSD}, +{"VPMINSQ", XED_ICLASS_VPMINSQ}, +{"VPMINSW", XED_ICLASS_VPMINSW}, +{"VPMINUB", XED_ICLASS_VPMINUB}, +{"VPMINUD", XED_ICLASS_VPMINUD}, +{"VPMINUQ", XED_ICLASS_VPMINUQ}, +{"VPMINUW", XED_ICLASS_VPMINUW}, +{"VPMOVB2M", XED_ICLASS_VPMOVB2M}, +{"VPMOVD2M", XED_ICLASS_VPMOVD2M}, +{"VPMOVDB", XED_ICLASS_VPMOVDB}, +{"VPMOVDW", XED_ICLASS_VPMOVDW}, +{"VPMOVM2B", XED_ICLASS_VPMOVM2B}, +{"VPMOVM2D", XED_ICLASS_VPMOVM2D}, +{"VPMOVM2Q", XED_ICLASS_VPMOVM2Q}, +{"VPMOVM2W", XED_ICLASS_VPMOVM2W}, +{"VPMOVMSKB", XED_ICLASS_VPMOVMSKB}, +{"VPMOVQ2M", XED_ICLASS_VPMOVQ2M}, +{"VPMOVQB", XED_ICLASS_VPMOVQB}, +{"VPMOVQD", XED_ICLASS_VPMOVQD}, +{"VPMOVQW", XED_ICLASS_VPMOVQW}, +{"VPMOVSDB", XED_ICLASS_VPMOVSDB}, +{"VPMOVSDW", XED_ICLASS_VPMOVSDW}, +{"VPMOVSQB", XED_ICLASS_VPMOVSQB}, +{"VPMOVSQD", XED_ICLASS_VPMOVSQD}, +{"VPMOVSQW", XED_ICLASS_VPMOVSQW}, +{"VPMOVSWB", XED_ICLASS_VPMOVSWB}, +{"VPMOVSXBD", XED_ICLASS_VPMOVSXBD}, +{"VPMOVSXBQ", XED_ICLASS_VPMOVSXBQ}, +{"VPMOVSXBW", XED_ICLASS_VPMOVSXBW}, +{"VPMOVSXDQ", XED_ICLASS_VPMOVSXDQ}, +{"VPMOVSXWD", XED_ICLASS_VPMOVSXWD}, +{"VPMOVSXWQ", XED_ICLASS_VPMOVSXWQ}, +{"VPMOVUSDB", XED_ICLASS_VPMOVUSDB}, +{"VPMOVUSDW", XED_ICLASS_VPMOVUSDW}, +{"VPMOVUSQB", XED_ICLASS_VPMOVUSQB}, +{"VPMOVUSQD", XED_ICLASS_VPMOVUSQD}, +{"VPMOVUSQW", XED_ICLASS_VPMOVUSQW}, +{"VPMOVUSWB", XED_ICLASS_VPMOVUSWB}, +{"VPMOVW2M", XED_ICLASS_VPMOVW2M}, +{"VPMOVWB", XED_ICLASS_VPMOVWB}, +{"VPMOVZXBD", XED_ICLASS_VPMOVZXBD}, +{"VPMOVZXBQ", XED_ICLASS_VPMOVZXBQ}, +{"VPMOVZXBW", XED_ICLASS_VPMOVZXBW}, +{"VPMOVZXDQ", XED_ICLASS_VPMOVZXDQ}, +{"VPMOVZXWD", XED_ICLASS_VPMOVZXWD}, +{"VPMOVZXWQ", XED_ICLASS_VPMOVZXWQ}, +{"VPMULDQ", XED_ICLASS_VPMULDQ}, +{"VPMULHRSW", XED_ICLASS_VPMULHRSW}, +{"VPMULHUW", XED_ICLASS_VPMULHUW}, +{"VPMULHW", XED_ICLASS_VPMULHW}, +{"VPMULLD", XED_ICLASS_VPMULLD}, +{"VPMULLQ", XED_ICLASS_VPMULLQ}, +{"VPMULLW", XED_ICLASS_VPMULLW}, +{"VPMULTISHIFTQB", XED_ICLASS_VPMULTISHIFTQB}, +{"VPMULUDQ", XED_ICLASS_VPMULUDQ}, +{"VPOPCNTB", XED_ICLASS_VPOPCNTB}, +{"VPOPCNTD", XED_ICLASS_VPOPCNTD}, +{"VPOPCNTQ", XED_ICLASS_VPOPCNTQ}, +{"VPOPCNTW", XED_ICLASS_VPOPCNTW}, +{"VPOR", XED_ICLASS_VPOR}, +{"VPORD", XED_ICLASS_VPORD}, +{"VPORQ", XED_ICLASS_VPORQ}, +{"VPPERM", XED_ICLASS_VPPERM}, +{"VPROLD", XED_ICLASS_VPROLD}, +{"VPROLQ", XED_ICLASS_VPROLQ}, +{"VPROLVD", XED_ICLASS_VPROLVD}, +{"VPROLVQ", XED_ICLASS_VPROLVQ}, +{"VPRORD", XED_ICLASS_VPRORD}, +{"VPRORQ", XED_ICLASS_VPRORQ}, +{"VPRORVD", XED_ICLASS_VPRORVD}, +{"VPRORVQ", XED_ICLASS_VPRORVQ}, +{"VPROTB", XED_ICLASS_VPROTB}, +{"VPROTD", XED_ICLASS_VPROTD}, +{"VPROTQ", XED_ICLASS_VPROTQ}, +{"VPROTW", XED_ICLASS_VPROTW}, +{"VPSADBW", XED_ICLASS_VPSADBW}, +{"VPSCATTERDD", XED_ICLASS_VPSCATTERDD}, +{"VPSCATTERDQ", XED_ICLASS_VPSCATTERDQ}, +{"VPSCATTERQD", XED_ICLASS_VPSCATTERQD}, +{"VPSCATTERQQ", XED_ICLASS_VPSCATTERQQ}, +{"VPSHAB", XED_ICLASS_VPSHAB}, +{"VPSHAD", XED_ICLASS_VPSHAD}, +{"VPSHAQ", XED_ICLASS_VPSHAQ}, +{"VPSHAW", XED_ICLASS_VPSHAW}, +{"VPSHLB", XED_ICLASS_VPSHLB}, +{"VPSHLD", XED_ICLASS_VPSHLD}, +{"VPSHLDD", XED_ICLASS_VPSHLDD}, +{"VPSHLDQ", XED_ICLASS_VPSHLDQ}, +{"VPSHLDVD", XED_ICLASS_VPSHLDVD}, +{"VPSHLDVQ", XED_ICLASS_VPSHLDVQ}, +{"VPSHLDVW", XED_ICLASS_VPSHLDVW}, +{"VPSHLDW", XED_ICLASS_VPSHLDW}, +{"VPSHLQ", XED_ICLASS_VPSHLQ}, +{"VPSHLW", XED_ICLASS_VPSHLW}, +{"VPSHRDD", XED_ICLASS_VPSHRDD}, +{"VPSHRDQ", XED_ICLASS_VPSHRDQ}, +{"VPSHRDVD", XED_ICLASS_VPSHRDVD}, +{"VPSHRDVQ", XED_ICLASS_VPSHRDVQ}, +{"VPSHRDVW", XED_ICLASS_VPSHRDVW}, +{"VPSHRDW", XED_ICLASS_VPSHRDW}, +{"VPSHUFB", XED_ICLASS_VPSHUFB}, +{"VPSHUFBITQMB", XED_ICLASS_VPSHUFBITQMB}, +{"VPSHUFD", XED_ICLASS_VPSHUFD}, +{"VPSHUFHW", XED_ICLASS_VPSHUFHW}, +{"VPSHUFLW", XED_ICLASS_VPSHUFLW}, +{"VPSIGNB", XED_ICLASS_VPSIGNB}, +{"VPSIGND", XED_ICLASS_VPSIGND}, +{"VPSIGNW", XED_ICLASS_VPSIGNW}, +{"VPSLLD", XED_ICLASS_VPSLLD}, +{"VPSLLDQ", XED_ICLASS_VPSLLDQ}, +{"VPSLLQ", XED_ICLASS_VPSLLQ}, +{"VPSLLVD", XED_ICLASS_VPSLLVD}, +{"VPSLLVQ", XED_ICLASS_VPSLLVQ}, +{"VPSLLVW", XED_ICLASS_VPSLLVW}, +{"VPSLLW", XED_ICLASS_VPSLLW}, +{"VPSRAD", XED_ICLASS_VPSRAD}, +{"VPSRAQ", XED_ICLASS_VPSRAQ}, +{"VPSRAVD", XED_ICLASS_VPSRAVD}, +{"VPSRAVQ", XED_ICLASS_VPSRAVQ}, +{"VPSRAVW", XED_ICLASS_VPSRAVW}, +{"VPSRAW", XED_ICLASS_VPSRAW}, +{"VPSRLD", XED_ICLASS_VPSRLD}, +{"VPSRLDQ", XED_ICLASS_VPSRLDQ}, +{"VPSRLQ", XED_ICLASS_VPSRLQ}, +{"VPSRLVD", XED_ICLASS_VPSRLVD}, +{"VPSRLVQ", XED_ICLASS_VPSRLVQ}, +{"VPSRLVW", XED_ICLASS_VPSRLVW}, +{"VPSRLW", XED_ICLASS_VPSRLW}, +{"VPSUBB", XED_ICLASS_VPSUBB}, +{"VPSUBD", XED_ICLASS_VPSUBD}, +{"VPSUBQ", XED_ICLASS_VPSUBQ}, +{"VPSUBSB", XED_ICLASS_VPSUBSB}, +{"VPSUBSW", XED_ICLASS_VPSUBSW}, +{"VPSUBUSB", XED_ICLASS_VPSUBUSB}, +{"VPSUBUSW", XED_ICLASS_VPSUBUSW}, +{"VPSUBW", XED_ICLASS_VPSUBW}, +{"VPTERNLOGD", XED_ICLASS_VPTERNLOGD}, +{"VPTERNLOGQ", XED_ICLASS_VPTERNLOGQ}, +{"VPTEST", XED_ICLASS_VPTEST}, +{"VPTESTMB", XED_ICLASS_VPTESTMB}, +{"VPTESTMD", XED_ICLASS_VPTESTMD}, +{"VPTESTMQ", XED_ICLASS_VPTESTMQ}, +{"VPTESTMW", XED_ICLASS_VPTESTMW}, +{"VPTESTNMB", XED_ICLASS_VPTESTNMB}, +{"VPTESTNMD", XED_ICLASS_VPTESTNMD}, +{"VPTESTNMQ", XED_ICLASS_VPTESTNMQ}, +{"VPTESTNMW", XED_ICLASS_VPTESTNMW}, +{"VPUNPCKHBW", XED_ICLASS_VPUNPCKHBW}, +{"VPUNPCKHDQ", XED_ICLASS_VPUNPCKHDQ}, +{"VPUNPCKHQDQ", XED_ICLASS_VPUNPCKHQDQ}, +{"VPUNPCKHWD", XED_ICLASS_VPUNPCKHWD}, +{"VPUNPCKLBW", XED_ICLASS_VPUNPCKLBW}, +{"VPUNPCKLDQ", XED_ICLASS_VPUNPCKLDQ}, +{"VPUNPCKLQDQ", XED_ICLASS_VPUNPCKLQDQ}, +{"VPUNPCKLWD", XED_ICLASS_VPUNPCKLWD}, +{"VPXOR", XED_ICLASS_VPXOR}, +{"VPXORD", XED_ICLASS_VPXORD}, +{"VPXORQ", XED_ICLASS_VPXORQ}, +{"VRANGEPD", XED_ICLASS_VRANGEPD}, +{"VRANGEPS", XED_ICLASS_VRANGEPS}, +{"VRANGESD", XED_ICLASS_VRANGESD}, +{"VRANGESS", XED_ICLASS_VRANGESS}, +{"VRCP14PD", XED_ICLASS_VRCP14PD}, +{"VRCP14PS", XED_ICLASS_VRCP14PS}, +{"VRCP14SD", XED_ICLASS_VRCP14SD}, +{"VRCP14SS", XED_ICLASS_VRCP14SS}, +{"VRCP28PD", XED_ICLASS_VRCP28PD}, +{"VRCP28PS", XED_ICLASS_VRCP28PS}, +{"VRCP28SD", XED_ICLASS_VRCP28SD}, +{"VRCP28SS", XED_ICLASS_VRCP28SS}, +{"VRCPPH", XED_ICLASS_VRCPPH}, +{"VRCPPS", XED_ICLASS_VRCPPS}, +{"VRCPSH", XED_ICLASS_VRCPSH}, +{"VRCPSS", XED_ICLASS_VRCPSS}, +{"VREDUCEPD", XED_ICLASS_VREDUCEPD}, +{"VREDUCEPH", XED_ICLASS_VREDUCEPH}, +{"VREDUCEPS", XED_ICLASS_VREDUCEPS}, +{"VREDUCESD", XED_ICLASS_VREDUCESD}, +{"VREDUCESH", XED_ICLASS_VREDUCESH}, +{"VREDUCESS", XED_ICLASS_VREDUCESS}, +{"VRNDSCALEPD", XED_ICLASS_VRNDSCALEPD}, +{"VRNDSCALEPH", XED_ICLASS_VRNDSCALEPH}, +{"VRNDSCALEPS", XED_ICLASS_VRNDSCALEPS}, +{"VRNDSCALESD", XED_ICLASS_VRNDSCALESD}, +{"VRNDSCALESH", XED_ICLASS_VRNDSCALESH}, +{"VRNDSCALESS", XED_ICLASS_VRNDSCALESS}, +{"VROUNDPD", XED_ICLASS_VROUNDPD}, +{"VROUNDPS", XED_ICLASS_VROUNDPS}, +{"VROUNDSD", XED_ICLASS_VROUNDSD}, +{"VROUNDSS", XED_ICLASS_VROUNDSS}, +{"VRSQRT14PD", XED_ICLASS_VRSQRT14PD}, +{"VRSQRT14PS", XED_ICLASS_VRSQRT14PS}, +{"VRSQRT14SD", XED_ICLASS_VRSQRT14SD}, +{"VRSQRT14SS", XED_ICLASS_VRSQRT14SS}, +{"VRSQRT28PD", XED_ICLASS_VRSQRT28PD}, +{"VRSQRT28PS", XED_ICLASS_VRSQRT28PS}, +{"VRSQRT28SD", XED_ICLASS_VRSQRT28SD}, +{"VRSQRT28SS", XED_ICLASS_VRSQRT28SS}, +{"VRSQRTPH", XED_ICLASS_VRSQRTPH}, +{"VRSQRTPS", XED_ICLASS_VRSQRTPS}, +{"VRSQRTSH", XED_ICLASS_VRSQRTSH}, +{"VRSQRTSS", XED_ICLASS_VRSQRTSS}, +{"VSCALEFPD", XED_ICLASS_VSCALEFPD}, +{"VSCALEFPH", XED_ICLASS_VSCALEFPH}, +{"VSCALEFPS", XED_ICLASS_VSCALEFPS}, +{"VSCALEFSD", XED_ICLASS_VSCALEFSD}, +{"VSCALEFSH", XED_ICLASS_VSCALEFSH}, +{"VSCALEFSS", XED_ICLASS_VSCALEFSS}, +{"VSCATTERDPD", XED_ICLASS_VSCATTERDPD}, +{"VSCATTERDPS", XED_ICLASS_VSCATTERDPS}, +{"VSCATTERPF0DPD", XED_ICLASS_VSCATTERPF0DPD}, +{"VSCATTERPF0DPS", XED_ICLASS_VSCATTERPF0DPS}, +{"VSCATTERPF0QPD", XED_ICLASS_VSCATTERPF0QPD}, +{"VSCATTERPF0QPS", XED_ICLASS_VSCATTERPF0QPS}, +{"VSCATTERPF1DPD", XED_ICLASS_VSCATTERPF1DPD}, +{"VSCATTERPF1DPS", XED_ICLASS_VSCATTERPF1DPS}, +{"VSCATTERPF1QPD", XED_ICLASS_VSCATTERPF1QPD}, +{"VSCATTERPF1QPS", XED_ICLASS_VSCATTERPF1QPS}, +{"VSCATTERQPD", XED_ICLASS_VSCATTERQPD}, +{"VSCATTERQPS", XED_ICLASS_VSCATTERQPS}, +{"VSHUFF32X4", XED_ICLASS_VSHUFF32X4}, +{"VSHUFF64X2", XED_ICLASS_VSHUFF64X2}, +{"VSHUFI32X4", XED_ICLASS_VSHUFI32X4}, +{"VSHUFI64X2", XED_ICLASS_VSHUFI64X2}, +{"VSHUFPD", XED_ICLASS_VSHUFPD}, +{"VSHUFPS", XED_ICLASS_VSHUFPS}, +{"VSQRTPD", XED_ICLASS_VSQRTPD}, +{"VSQRTPH", XED_ICLASS_VSQRTPH}, +{"VSQRTPS", XED_ICLASS_VSQRTPS}, +{"VSQRTSD", XED_ICLASS_VSQRTSD}, +{"VSQRTSH", XED_ICLASS_VSQRTSH}, +{"VSQRTSS", XED_ICLASS_VSQRTSS}, +{"VSTMXCSR", XED_ICLASS_VSTMXCSR}, +{"VSUBPD", XED_ICLASS_VSUBPD}, +{"VSUBPH", XED_ICLASS_VSUBPH}, +{"VSUBPS", XED_ICLASS_VSUBPS}, +{"VSUBSD", XED_ICLASS_VSUBSD}, +{"VSUBSH", XED_ICLASS_VSUBSH}, +{"VSUBSS", XED_ICLASS_VSUBSS}, +{"VTESTPD", XED_ICLASS_VTESTPD}, +{"VTESTPS", XED_ICLASS_VTESTPS}, +{"VUCOMISD", XED_ICLASS_VUCOMISD}, +{"VUCOMISH", XED_ICLASS_VUCOMISH}, +{"VUCOMISS", XED_ICLASS_VUCOMISS}, +{"VUNPCKHPD", XED_ICLASS_VUNPCKHPD}, +{"VUNPCKHPS", XED_ICLASS_VUNPCKHPS}, +{"VUNPCKLPD", XED_ICLASS_VUNPCKLPD}, +{"VUNPCKLPS", XED_ICLASS_VUNPCKLPS}, +{"VXORPD", XED_ICLASS_VXORPD}, +{"VXORPS", XED_ICLASS_VXORPS}, +{"VZEROALL", XED_ICLASS_VZEROALL}, +{"VZEROUPPER", XED_ICLASS_VZEROUPPER}, +{"WBINVD", XED_ICLASS_WBINVD}, +{"WBNOINVD", XED_ICLASS_WBNOINVD}, +{"WRFSBASE", XED_ICLASS_WRFSBASE}, +{"WRGSBASE", XED_ICLASS_WRGSBASE}, +{"WRMSR", XED_ICLASS_WRMSR}, +{"WRPKRU", XED_ICLASS_WRPKRU}, +{"WRSSD", XED_ICLASS_WRSSD}, +{"WRSSQ", XED_ICLASS_WRSSQ}, +{"WRUSSD", XED_ICLASS_WRUSSD}, +{"WRUSSQ", XED_ICLASS_WRUSSQ}, +{"XABORT", XED_ICLASS_XABORT}, +{"XADD", XED_ICLASS_XADD}, +{"XADD_LOCK", XED_ICLASS_XADD_LOCK}, +{"XBEGIN", XED_ICLASS_XBEGIN}, +{"XCHG", XED_ICLASS_XCHG}, +{"XEND", XED_ICLASS_XEND}, +{"XGETBV", XED_ICLASS_XGETBV}, +{"XLAT", XED_ICLASS_XLAT}, +{"XOR", XED_ICLASS_XOR}, +{"XORPD", XED_ICLASS_XORPD}, +{"XORPS", XED_ICLASS_XORPS}, +{"XOR_LOCK", XED_ICLASS_XOR_LOCK}, +{"XRESLDTRK", XED_ICLASS_XRESLDTRK}, +{"XRSTOR", XED_ICLASS_XRSTOR}, +{"XRSTOR64", XED_ICLASS_XRSTOR64}, +{"XRSTORS", XED_ICLASS_XRSTORS}, +{"XRSTORS64", XED_ICLASS_XRSTORS64}, +{"XSAVE", XED_ICLASS_XSAVE}, +{"XSAVE64", XED_ICLASS_XSAVE64}, +{"XSAVEC", XED_ICLASS_XSAVEC}, +{"XSAVEC64", XED_ICLASS_XSAVEC64}, +{"XSAVEOPT", XED_ICLASS_XSAVEOPT}, +{"XSAVEOPT64", XED_ICLASS_XSAVEOPT64}, +{"XSAVES", XED_ICLASS_XSAVES}, +{"XSAVES64", XED_ICLASS_XSAVES64}, +{"XSETBV", XED_ICLASS_XSETBV}, +{"XSTORE", XED_ICLASS_XSTORE}, +{"XSUSLDTRK", XED_ICLASS_XSUSLDTRK}, +{"XTEST", XED_ICLASS_XTEST}, +{"LAST", XED_ICLASS_LAST}, +{0, XED_ICLASS_LAST}, +}; + + +xed_iclass_enum_t str2xed_iclass_enum_t(const char* s) +{ + const name_table_xed_iclass_enum_t* p = name_array_xed_iclass_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_ICLASS_INVALID; +} + + +const char* xed_iclass_enum_t2str(const xed_iclass_enum_t p) +{ + xed_iclass_enum_t type_idx = p; + if ( p > XED_ICLASS_LAST) type_idx = XED_ICLASS_LAST; + return name_array_xed_iclass_enum_t[type_idx].name; +} + +xed_iclass_enum_t xed_iclass_enum_t_last(void) { + return XED_ICLASS_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_ICLASS_INVALID: + case XED_ICLASS_AAA: + case XED_ICLASS_AAD: + case XED_ICLASS_AAM: + case XED_ICLASS_AAS: + case XED_ICLASS_ADC: + case XED_ICLASS_ADCX: + case XED_ICLASS_ADC_LOCK: + case XED_ICLASS_ADD: + case XED_ICLASS_ADDPD: + case XED_ICLASS_ADDPS: + case XED_ICLASS_ADDSD: + case XED_ICLASS_ADDSS: + case XED_ICLASS_ADDSUBPD: + case XED_ICLASS_ADDSUBPS: + case XED_ICLASS_ADD_LOCK: + case XED_ICLASS_ADOX: + case XED_ICLASS_AESDEC: + case XED_ICLASS_AESDEC128KL: + case XED_ICLASS_AESDEC256KL: + case XED_ICLASS_AESDECLAST: + case XED_ICLASS_AESDECWIDE128KL: + case XED_ICLASS_AESDECWIDE256KL: + case XED_ICLASS_AESENC: + case XED_ICLASS_AESENC128KL: + case XED_ICLASS_AESENC256KL: + case XED_ICLASS_AESENCLAST: + case XED_ICLASS_AESENCWIDE128KL: + case XED_ICLASS_AESENCWIDE256KL: + case XED_ICLASS_AESIMC: + case XED_ICLASS_AESKEYGENASSIST: + case XED_ICLASS_AND: + case XED_ICLASS_ANDN: + case XED_ICLASS_ANDNPD: + case XED_ICLASS_ANDNPS: + case XED_ICLASS_ANDPD: + case XED_ICLASS_ANDPS: + case XED_ICLASS_AND_LOCK: + case XED_ICLASS_ARPL: + case XED_ICLASS_BEXTR: + case XED_ICLASS_BEXTR_XOP: + case XED_ICLASS_BLCFILL: + case XED_ICLASS_BLCI: + case XED_ICLASS_BLCIC: + case XED_ICLASS_BLCMSK: + case XED_ICLASS_BLCS: + case XED_ICLASS_BLENDPD: + case XED_ICLASS_BLENDPS: + case XED_ICLASS_BLENDVPD: + case XED_ICLASS_BLENDVPS: + case XED_ICLASS_BLSFILL: + case XED_ICLASS_BLSI: + case XED_ICLASS_BLSIC: + case XED_ICLASS_BLSMSK: + case XED_ICLASS_BLSR: + case XED_ICLASS_BNDCL: + case XED_ICLASS_BNDCN: + case XED_ICLASS_BNDCU: + case XED_ICLASS_BNDLDX: + case XED_ICLASS_BNDMK: + case XED_ICLASS_BNDMOV: + case XED_ICLASS_BNDSTX: + case XED_ICLASS_BOUND: + case XED_ICLASS_BSF: + case XED_ICLASS_BSR: + case XED_ICLASS_BSWAP: + case XED_ICLASS_BT: + case XED_ICLASS_BTC: + case XED_ICLASS_BTC_LOCK: + case XED_ICLASS_BTR: + case XED_ICLASS_BTR_LOCK: + case XED_ICLASS_BTS: + case XED_ICLASS_BTS_LOCK: + case XED_ICLASS_BZHI: + case XED_ICLASS_CALL_FAR: + case XED_ICLASS_CALL_NEAR: + case XED_ICLASS_CBW: + case XED_ICLASS_CDQ: + case XED_ICLASS_CDQE: + case XED_ICLASS_CLAC: + case XED_ICLASS_CLC: + case XED_ICLASS_CLD: + case XED_ICLASS_CLDEMOTE: + case XED_ICLASS_CLFLUSH: + case XED_ICLASS_CLFLUSHOPT: + case XED_ICLASS_CLGI: + case XED_ICLASS_CLI: + case XED_ICLASS_CLRSSBSY: + case XED_ICLASS_CLTS: + case XED_ICLASS_CLUI: + case XED_ICLASS_CLWB: + case XED_ICLASS_CLZERO: + case XED_ICLASS_CMC: + case XED_ICLASS_CMOVB: + case XED_ICLASS_CMOVBE: + case XED_ICLASS_CMOVL: + case XED_ICLASS_CMOVLE: + case XED_ICLASS_CMOVNB: + case XED_ICLASS_CMOVNBE: + case XED_ICLASS_CMOVNL: + case XED_ICLASS_CMOVNLE: + case XED_ICLASS_CMOVNO: + case XED_ICLASS_CMOVNP: + case XED_ICLASS_CMOVNS: + case XED_ICLASS_CMOVNZ: + case XED_ICLASS_CMOVO: + case XED_ICLASS_CMOVP: + case XED_ICLASS_CMOVS: + case XED_ICLASS_CMOVZ: + case XED_ICLASS_CMP: + case XED_ICLASS_CMPPD: + case XED_ICLASS_CMPPS: + case XED_ICLASS_CMPSB: + case XED_ICLASS_CMPSD: + case XED_ICLASS_CMPSD_XMM: + case XED_ICLASS_CMPSQ: + case XED_ICLASS_CMPSS: + case XED_ICLASS_CMPSW: + case XED_ICLASS_CMPXCHG: + case XED_ICLASS_CMPXCHG16B: + case XED_ICLASS_CMPXCHG16B_LOCK: + case XED_ICLASS_CMPXCHG8B: + case XED_ICLASS_CMPXCHG8B_LOCK: + case XED_ICLASS_CMPXCHG_LOCK: + case XED_ICLASS_COMISD: + case XED_ICLASS_COMISS: + case XED_ICLASS_CPUID: + case XED_ICLASS_CQO: + case XED_ICLASS_CRC32: + case XED_ICLASS_CVTDQ2PD: + case XED_ICLASS_CVTDQ2PS: + case XED_ICLASS_CVTPD2DQ: + case XED_ICLASS_CVTPD2PI: + case XED_ICLASS_CVTPD2PS: + case XED_ICLASS_CVTPI2PD: + case XED_ICLASS_CVTPI2PS: + case XED_ICLASS_CVTPS2DQ: + case XED_ICLASS_CVTPS2PD: + case XED_ICLASS_CVTPS2PI: + case XED_ICLASS_CVTSD2SI: + case XED_ICLASS_CVTSD2SS: + case XED_ICLASS_CVTSI2SD: + case XED_ICLASS_CVTSI2SS: + case XED_ICLASS_CVTSS2SD: + case XED_ICLASS_CVTSS2SI: + case XED_ICLASS_CVTTPD2DQ: + case XED_ICLASS_CVTTPD2PI: + case XED_ICLASS_CVTTPS2DQ: + case XED_ICLASS_CVTTPS2PI: + case XED_ICLASS_CVTTSD2SI: + case XED_ICLASS_CVTTSS2SI: + case XED_ICLASS_CWD: + case XED_ICLASS_CWDE: + case XED_ICLASS_DAA: + case XED_ICLASS_DAS: + case XED_ICLASS_DEC: + case XED_ICLASS_DEC_LOCK: + case XED_ICLASS_DIV: + case XED_ICLASS_DIVPD: + case XED_ICLASS_DIVPS: + case XED_ICLASS_DIVSD: + case XED_ICLASS_DIVSS: + case XED_ICLASS_DPPD: + case XED_ICLASS_DPPS: + case XED_ICLASS_EMMS: + case XED_ICLASS_ENCLS: + case XED_ICLASS_ENCLU: + case XED_ICLASS_ENCLV: + case XED_ICLASS_ENCODEKEY128: + case XED_ICLASS_ENCODEKEY256: + case XED_ICLASS_ENDBR32: + case XED_ICLASS_ENDBR64: + case XED_ICLASS_ENQCMD: + case XED_ICLASS_ENQCMDS: + case XED_ICLASS_ENTER: + case XED_ICLASS_EXTRACTPS: + case XED_ICLASS_EXTRQ: + case XED_ICLASS_F2XM1: + case XED_ICLASS_FABS: + case XED_ICLASS_FADD: + case XED_ICLASS_FADDP: + case XED_ICLASS_FBLD: + case XED_ICLASS_FBSTP: + case XED_ICLASS_FCHS: + case XED_ICLASS_FCMOVB: + case XED_ICLASS_FCMOVBE: + case XED_ICLASS_FCMOVE: + case XED_ICLASS_FCMOVNB: + case XED_ICLASS_FCMOVNBE: + case XED_ICLASS_FCMOVNE: + case XED_ICLASS_FCMOVNU: + case XED_ICLASS_FCMOVU: + case XED_ICLASS_FCOM: + case XED_ICLASS_FCOMI: + case XED_ICLASS_FCOMIP: + case XED_ICLASS_FCOMP: + case XED_ICLASS_FCOMPP: + case XED_ICLASS_FCOS: + case XED_ICLASS_FDECSTP: + case XED_ICLASS_FDISI8087_NOP: + case XED_ICLASS_FDIV: + case XED_ICLASS_FDIVP: + case XED_ICLASS_FDIVR: + case XED_ICLASS_FDIVRP: + case XED_ICLASS_FEMMS: + case XED_ICLASS_FENI8087_NOP: + case XED_ICLASS_FFREE: + case XED_ICLASS_FFREEP: + case XED_ICLASS_FIADD: + case XED_ICLASS_FICOM: + case XED_ICLASS_FICOMP: + case XED_ICLASS_FIDIV: + case XED_ICLASS_FIDIVR: + case XED_ICLASS_FILD: + case XED_ICLASS_FIMUL: + case XED_ICLASS_FINCSTP: + case XED_ICLASS_FIST: + case XED_ICLASS_FISTP: + case XED_ICLASS_FISTTP: + case XED_ICLASS_FISUB: + case XED_ICLASS_FISUBR: + case XED_ICLASS_FLD: + case XED_ICLASS_FLD1: + case XED_ICLASS_FLDCW: + case XED_ICLASS_FLDENV: + case XED_ICLASS_FLDL2E: + case XED_ICLASS_FLDL2T: + case XED_ICLASS_FLDLG2: + case XED_ICLASS_FLDLN2: + case XED_ICLASS_FLDPI: + case XED_ICLASS_FLDZ: + case XED_ICLASS_FMUL: + case XED_ICLASS_FMULP: + case XED_ICLASS_FNCLEX: + case XED_ICLASS_FNINIT: + case XED_ICLASS_FNOP: + case XED_ICLASS_FNSAVE: + case XED_ICLASS_FNSTCW: + case XED_ICLASS_FNSTENV: + case XED_ICLASS_FNSTSW: + case XED_ICLASS_FPATAN: + case XED_ICLASS_FPREM: + case XED_ICLASS_FPREM1: + case XED_ICLASS_FPTAN: + case XED_ICLASS_FRNDINT: + case XED_ICLASS_FRSTOR: + case XED_ICLASS_FSCALE: + case XED_ICLASS_FSETPM287_NOP: + case XED_ICLASS_FSIN: + case XED_ICLASS_FSINCOS: + case XED_ICLASS_FSQRT: + case XED_ICLASS_FST: + case XED_ICLASS_FSTP: + case XED_ICLASS_FSTPNCE: + case XED_ICLASS_FSUB: + case XED_ICLASS_FSUBP: + case XED_ICLASS_FSUBR: + case XED_ICLASS_FSUBRP: + case XED_ICLASS_FTST: + case XED_ICLASS_FUCOM: + case XED_ICLASS_FUCOMI: + case XED_ICLASS_FUCOMIP: + case XED_ICLASS_FUCOMP: + case XED_ICLASS_FUCOMPP: + case XED_ICLASS_FWAIT: + case XED_ICLASS_FXAM: + case XED_ICLASS_FXCH: + case XED_ICLASS_FXRSTOR: + case XED_ICLASS_FXRSTOR64: + case XED_ICLASS_FXSAVE: + case XED_ICLASS_FXSAVE64: + case XED_ICLASS_FXTRACT: + case XED_ICLASS_FYL2X: + case XED_ICLASS_FYL2XP1: + case XED_ICLASS_GETSEC: + case XED_ICLASS_GF2P8AFFINEINVQB: + case XED_ICLASS_GF2P8AFFINEQB: + case XED_ICLASS_GF2P8MULB: + case XED_ICLASS_HADDPD: + case XED_ICLASS_HADDPS: + case XED_ICLASS_HLT: + case XED_ICLASS_HRESET: + case XED_ICLASS_HSUBPD: + case XED_ICLASS_HSUBPS: + case XED_ICLASS_IDIV: + case XED_ICLASS_IMUL: + case XED_ICLASS_IN: + case XED_ICLASS_INC: + case XED_ICLASS_INCSSPD: + case XED_ICLASS_INCSSPQ: + case XED_ICLASS_INC_LOCK: + case XED_ICLASS_INSB: + case XED_ICLASS_INSD: + case XED_ICLASS_INSERTPS: + case XED_ICLASS_INSERTQ: + case XED_ICLASS_INSW: + case XED_ICLASS_INT: + case XED_ICLASS_INT1: + case XED_ICLASS_INT3: + case XED_ICLASS_INTO: + case XED_ICLASS_INVD: + case XED_ICLASS_INVEPT: + case XED_ICLASS_INVLPG: + case XED_ICLASS_INVLPGA: + case XED_ICLASS_INVLPGB: + case XED_ICLASS_INVPCID: + case XED_ICLASS_INVVPID: + case XED_ICLASS_IRET: + case XED_ICLASS_IRETD: + case XED_ICLASS_IRETQ: + case XED_ICLASS_JB: + case XED_ICLASS_JBE: + case XED_ICLASS_JCXZ: + case XED_ICLASS_JECXZ: + case XED_ICLASS_JL: + case XED_ICLASS_JLE: + case XED_ICLASS_JMP: + case XED_ICLASS_JMP_FAR: + case XED_ICLASS_JNB: + case XED_ICLASS_JNBE: + case XED_ICLASS_JNL: + case XED_ICLASS_JNLE: + case XED_ICLASS_JNO: + case XED_ICLASS_JNP: + case XED_ICLASS_JNS: + case XED_ICLASS_JNZ: + case XED_ICLASS_JO: + case XED_ICLASS_JP: + case XED_ICLASS_JRCXZ: + case XED_ICLASS_JS: + case XED_ICLASS_JZ: + case XED_ICLASS_KADDB: + case XED_ICLASS_KADDD: + case XED_ICLASS_KADDQ: + case XED_ICLASS_KADDW: + case XED_ICLASS_KANDB: + case XED_ICLASS_KANDD: + case XED_ICLASS_KANDNB: + case XED_ICLASS_KANDND: + case XED_ICLASS_KANDNQ: + case XED_ICLASS_KANDNW: + case XED_ICLASS_KANDQ: + case XED_ICLASS_KANDW: + case XED_ICLASS_KMOVB: + case XED_ICLASS_KMOVD: + case XED_ICLASS_KMOVQ: + case XED_ICLASS_KMOVW: + case XED_ICLASS_KNOTB: + case XED_ICLASS_KNOTD: + case XED_ICLASS_KNOTQ: + case XED_ICLASS_KNOTW: + case XED_ICLASS_KORB: + case XED_ICLASS_KORD: + case XED_ICLASS_KORQ: + case XED_ICLASS_KORTESTB: + case XED_ICLASS_KORTESTD: + case XED_ICLASS_KORTESTQ: + case XED_ICLASS_KORTESTW: + case XED_ICLASS_KORW: + case XED_ICLASS_KSHIFTLB: + case XED_ICLASS_KSHIFTLD: + case XED_ICLASS_KSHIFTLQ: + case XED_ICLASS_KSHIFTLW: + case XED_ICLASS_KSHIFTRB: + case XED_ICLASS_KSHIFTRD: + case XED_ICLASS_KSHIFTRQ: + case XED_ICLASS_KSHIFTRW: + case XED_ICLASS_KTESTB: + case XED_ICLASS_KTESTD: + case XED_ICLASS_KTESTQ: + case XED_ICLASS_KTESTW: + case XED_ICLASS_KUNPCKBW: + case XED_ICLASS_KUNPCKDQ: + case XED_ICLASS_KUNPCKWD: + case XED_ICLASS_KXNORB: + case XED_ICLASS_KXNORD: + case XED_ICLASS_KXNORQ: + case XED_ICLASS_KXNORW: + case XED_ICLASS_KXORB: + case XED_ICLASS_KXORD: + case XED_ICLASS_KXORQ: + case XED_ICLASS_KXORW: + case XED_ICLASS_LAHF: + case XED_ICLASS_LAR: + case XED_ICLASS_LDDQU: + case XED_ICLASS_LDMXCSR: + case XED_ICLASS_LDS: + case XED_ICLASS_LDTILECFG: + case XED_ICLASS_LEA: + case XED_ICLASS_LEAVE: + case XED_ICLASS_LES: + case XED_ICLASS_LFENCE: + case XED_ICLASS_LFS: + case XED_ICLASS_LGDT: + case XED_ICLASS_LGS: + case XED_ICLASS_LIDT: + case XED_ICLASS_LLDT: + case XED_ICLASS_LLWPCB: + case XED_ICLASS_LMSW: + case XED_ICLASS_LOADIWKEY: + case XED_ICLASS_LODSB: + case XED_ICLASS_LODSD: + case XED_ICLASS_LODSQ: + case XED_ICLASS_LODSW: + case XED_ICLASS_LOOP: + case XED_ICLASS_LOOPE: + case XED_ICLASS_LOOPNE: + case XED_ICLASS_LSL: + case XED_ICLASS_LSS: + case XED_ICLASS_LTR: + case XED_ICLASS_LWPINS: + case XED_ICLASS_LWPVAL: + case XED_ICLASS_LZCNT: + case XED_ICLASS_MASKMOVDQU: + case XED_ICLASS_MASKMOVQ: + case XED_ICLASS_MAXPD: + case XED_ICLASS_MAXPS: + case XED_ICLASS_MAXSD: + case XED_ICLASS_MAXSS: + case XED_ICLASS_MCOMMIT: + case XED_ICLASS_MFENCE: + case XED_ICLASS_MINPD: + case XED_ICLASS_MINPS: + case XED_ICLASS_MINSD: + case XED_ICLASS_MINSS: + case XED_ICLASS_MONITOR: + case XED_ICLASS_MONITORX: + case XED_ICLASS_MOV: + case XED_ICLASS_MOVAPD: + case XED_ICLASS_MOVAPS: + case XED_ICLASS_MOVBE: + case XED_ICLASS_MOVD: + case XED_ICLASS_MOVDDUP: + case XED_ICLASS_MOVDIR64B: + case XED_ICLASS_MOVDIRI: + case XED_ICLASS_MOVDQ2Q: + case XED_ICLASS_MOVDQA: + case XED_ICLASS_MOVDQU: + case XED_ICLASS_MOVHLPS: + case XED_ICLASS_MOVHPD: + case XED_ICLASS_MOVHPS: + case XED_ICLASS_MOVLHPS: + case XED_ICLASS_MOVLPD: + case XED_ICLASS_MOVLPS: + case XED_ICLASS_MOVMSKPD: + case XED_ICLASS_MOVMSKPS: + case XED_ICLASS_MOVNTDQ: + case XED_ICLASS_MOVNTDQA: + case XED_ICLASS_MOVNTI: + case XED_ICLASS_MOVNTPD: + case XED_ICLASS_MOVNTPS: + case XED_ICLASS_MOVNTQ: + case XED_ICLASS_MOVNTSD: + case XED_ICLASS_MOVNTSS: + case XED_ICLASS_MOVQ: + case XED_ICLASS_MOVQ2DQ: + case XED_ICLASS_MOVSB: + case XED_ICLASS_MOVSD: + case XED_ICLASS_MOVSD_XMM: + case XED_ICLASS_MOVSHDUP: + case XED_ICLASS_MOVSLDUP: + case XED_ICLASS_MOVSQ: + case XED_ICLASS_MOVSS: + case XED_ICLASS_MOVSW: + case XED_ICLASS_MOVSX: + case XED_ICLASS_MOVSXD: + case XED_ICLASS_MOVUPD: + case XED_ICLASS_MOVUPS: + case XED_ICLASS_MOVZX: + case XED_ICLASS_MOV_CR: + case XED_ICLASS_MOV_DR: + case XED_ICLASS_MPSADBW: + case XED_ICLASS_MUL: + case XED_ICLASS_MULPD: + case XED_ICLASS_MULPS: + case XED_ICLASS_MULSD: + case XED_ICLASS_MULSS: + case XED_ICLASS_MULX: + case XED_ICLASS_MWAIT: + case XED_ICLASS_MWAITX: + case XED_ICLASS_NEG: + case XED_ICLASS_NEG_LOCK: + case XED_ICLASS_NOP: + case XED_ICLASS_NOP2: + case XED_ICLASS_NOP3: + case XED_ICLASS_NOP4: + case XED_ICLASS_NOP5: + case XED_ICLASS_NOP6: + case XED_ICLASS_NOP7: + case XED_ICLASS_NOP8: + case XED_ICLASS_NOP9: + case XED_ICLASS_NOT: + case XED_ICLASS_NOT_LOCK: + case XED_ICLASS_OR: + case XED_ICLASS_ORPD: + case XED_ICLASS_ORPS: + case XED_ICLASS_OR_LOCK: + case XED_ICLASS_OUT: + case XED_ICLASS_OUTSB: + case XED_ICLASS_OUTSD: + case XED_ICLASS_OUTSW: + case XED_ICLASS_PABSB: + case XED_ICLASS_PABSD: + case XED_ICLASS_PABSW: + case XED_ICLASS_PACKSSDW: + case XED_ICLASS_PACKSSWB: + case XED_ICLASS_PACKUSDW: + case XED_ICLASS_PACKUSWB: + case XED_ICLASS_PADDB: + case XED_ICLASS_PADDD: + case XED_ICLASS_PADDQ: + case XED_ICLASS_PADDSB: + case XED_ICLASS_PADDSW: + case XED_ICLASS_PADDUSB: + case XED_ICLASS_PADDUSW: + case XED_ICLASS_PADDW: + case XED_ICLASS_PALIGNR: + case XED_ICLASS_PAND: + case XED_ICLASS_PANDN: + case XED_ICLASS_PAUSE: + case XED_ICLASS_PAVGB: + case XED_ICLASS_PAVGUSB: + case XED_ICLASS_PAVGW: + case XED_ICLASS_PBLENDVB: + case XED_ICLASS_PBLENDW: + case XED_ICLASS_PCLMULQDQ: + case XED_ICLASS_PCMPEQB: + case XED_ICLASS_PCMPEQD: + case XED_ICLASS_PCMPEQQ: + case XED_ICLASS_PCMPEQW: + case XED_ICLASS_PCMPESTRI: + case XED_ICLASS_PCMPESTRI64: + case XED_ICLASS_PCMPESTRM: + case XED_ICLASS_PCMPESTRM64: + case XED_ICLASS_PCMPGTB: + case XED_ICLASS_PCMPGTD: + case XED_ICLASS_PCMPGTQ: + case XED_ICLASS_PCMPGTW: + case XED_ICLASS_PCMPISTRI: + case XED_ICLASS_PCMPISTRI64: + case XED_ICLASS_PCMPISTRM: + case XED_ICLASS_PCONFIG: + case XED_ICLASS_PDEP: + case XED_ICLASS_PEXT: + case XED_ICLASS_PEXTRB: + case XED_ICLASS_PEXTRD: + case XED_ICLASS_PEXTRQ: + case XED_ICLASS_PEXTRW: + case XED_ICLASS_PEXTRW_SSE4: + case XED_ICLASS_PF2ID: + case XED_ICLASS_PF2IW: + case XED_ICLASS_PFACC: + case XED_ICLASS_PFADD: + case XED_ICLASS_PFCMPEQ: + case XED_ICLASS_PFCMPGE: + case XED_ICLASS_PFCMPGT: + case XED_ICLASS_PFMAX: + case XED_ICLASS_PFMIN: + case XED_ICLASS_PFMUL: + case XED_ICLASS_PFNACC: + case XED_ICLASS_PFPNACC: + case XED_ICLASS_PFRCP: + case XED_ICLASS_PFRCPIT1: + case XED_ICLASS_PFRCPIT2: + case XED_ICLASS_PFRSQIT1: + case XED_ICLASS_PFRSQRT: + case XED_ICLASS_PFSUB: + case XED_ICLASS_PFSUBR: + case XED_ICLASS_PHADDD: + case XED_ICLASS_PHADDSW: + case XED_ICLASS_PHADDW: + case XED_ICLASS_PHMINPOSUW: + case XED_ICLASS_PHSUBD: + case XED_ICLASS_PHSUBSW: + case XED_ICLASS_PHSUBW: + case XED_ICLASS_PI2FD: + case XED_ICLASS_PI2FW: + case XED_ICLASS_PINSRB: + case XED_ICLASS_PINSRD: + case XED_ICLASS_PINSRQ: + case XED_ICLASS_PINSRW: + case XED_ICLASS_PMADDUBSW: + case XED_ICLASS_PMADDWD: + case XED_ICLASS_PMAXSB: + case XED_ICLASS_PMAXSD: + case XED_ICLASS_PMAXSW: + case XED_ICLASS_PMAXUB: + case XED_ICLASS_PMAXUD: + case XED_ICLASS_PMAXUW: + case XED_ICLASS_PMINSB: + case XED_ICLASS_PMINSD: + case XED_ICLASS_PMINSW: + case XED_ICLASS_PMINUB: + case XED_ICLASS_PMINUD: + case XED_ICLASS_PMINUW: + case XED_ICLASS_PMOVMSKB: + case XED_ICLASS_PMOVSXBD: + case XED_ICLASS_PMOVSXBQ: + case XED_ICLASS_PMOVSXBW: + case XED_ICLASS_PMOVSXDQ: + case XED_ICLASS_PMOVSXWD: + case XED_ICLASS_PMOVSXWQ: + case XED_ICLASS_PMOVZXBD: + case XED_ICLASS_PMOVZXBQ: + case XED_ICLASS_PMOVZXBW: + case XED_ICLASS_PMOVZXDQ: + case XED_ICLASS_PMOVZXWD: + case XED_ICLASS_PMOVZXWQ: + case XED_ICLASS_PMULDQ: + case XED_ICLASS_PMULHRSW: + case XED_ICLASS_PMULHRW: + case XED_ICLASS_PMULHUW: + case XED_ICLASS_PMULHW: + case XED_ICLASS_PMULLD: + case XED_ICLASS_PMULLW: + case XED_ICLASS_PMULUDQ: + case XED_ICLASS_POP: + case XED_ICLASS_POPA: + case XED_ICLASS_POPAD: + case XED_ICLASS_POPCNT: + case XED_ICLASS_POPF: + case XED_ICLASS_POPFD: + case XED_ICLASS_POPFQ: + case XED_ICLASS_POR: + case XED_ICLASS_PREFETCHNTA: + case XED_ICLASS_PREFETCHT0: + case XED_ICLASS_PREFETCHT1: + case XED_ICLASS_PREFETCHT2: + case XED_ICLASS_PREFETCHW: + case XED_ICLASS_PREFETCHWT1: + case XED_ICLASS_PREFETCH_EXCLUSIVE: + case XED_ICLASS_PREFETCH_RESERVED: + case XED_ICLASS_PSADBW: + case XED_ICLASS_PSHUFB: + case XED_ICLASS_PSHUFD: + case XED_ICLASS_PSHUFHW: + case XED_ICLASS_PSHUFLW: + case XED_ICLASS_PSHUFW: + case XED_ICLASS_PSIGNB: + case XED_ICLASS_PSIGND: + case XED_ICLASS_PSIGNW: + case XED_ICLASS_PSLLD: + case XED_ICLASS_PSLLDQ: + case XED_ICLASS_PSLLQ: + case XED_ICLASS_PSLLW: + case XED_ICLASS_PSMASH: + case XED_ICLASS_PSRAD: + case XED_ICLASS_PSRAW: + case XED_ICLASS_PSRLD: + case XED_ICLASS_PSRLDQ: + case XED_ICLASS_PSRLQ: + case XED_ICLASS_PSRLW: + case XED_ICLASS_PSUBB: + case XED_ICLASS_PSUBD: + case XED_ICLASS_PSUBQ: + case XED_ICLASS_PSUBSB: + case XED_ICLASS_PSUBSW: + case XED_ICLASS_PSUBUSB: + case XED_ICLASS_PSUBUSW: + case XED_ICLASS_PSUBW: + case XED_ICLASS_PSWAPD: + case XED_ICLASS_PTEST: + case XED_ICLASS_PTWRITE: + case XED_ICLASS_PUNPCKHBW: + case XED_ICLASS_PUNPCKHDQ: + case XED_ICLASS_PUNPCKHQDQ: + case XED_ICLASS_PUNPCKHWD: + case XED_ICLASS_PUNPCKLBW: + case XED_ICLASS_PUNPCKLDQ: + case XED_ICLASS_PUNPCKLQDQ: + case XED_ICLASS_PUNPCKLWD: + case XED_ICLASS_PUSH: + case XED_ICLASS_PUSHA: + case XED_ICLASS_PUSHAD: + case XED_ICLASS_PUSHF: + case XED_ICLASS_PUSHFD: + case XED_ICLASS_PUSHFQ: + case XED_ICLASS_PVALIDATE: + case XED_ICLASS_PXOR: + case XED_ICLASS_RCL: + case XED_ICLASS_RCPPS: + case XED_ICLASS_RCPSS: + case XED_ICLASS_RCR: + case XED_ICLASS_RDFSBASE: + case XED_ICLASS_RDGSBASE: + case XED_ICLASS_RDMSR: + case XED_ICLASS_RDPID: + case XED_ICLASS_RDPKRU: + case XED_ICLASS_RDPMC: + case XED_ICLASS_RDPRU: + case XED_ICLASS_RDRAND: + case XED_ICLASS_RDSEED: + case XED_ICLASS_RDSSPD: + case XED_ICLASS_RDSSPQ: + case XED_ICLASS_RDTSC: + case XED_ICLASS_RDTSCP: + case XED_ICLASS_REPE_CMPSB: + case XED_ICLASS_REPE_CMPSD: + case XED_ICLASS_REPE_CMPSQ: + case XED_ICLASS_REPE_CMPSW: + case XED_ICLASS_REPE_SCASB: + case XED_ICLASS_REPE_SCASD: + case XED_ICLASS_REPE_SCASQ: + case XED_ICLASS_REPE_SCASW: + case XED_ICLASS_REPNE_CMPSB: + case XED_ICLASS_REPNE_CMPSD: + case XED_ICLASS_REPNE_CMPSQ: + case XED_ICLASS_REPNE_CMPSW: + case XED_ICLASS_REPNE_SCASB: + case XED_ICLASS_REPNE_SCASD: + case XED_ICLASS_REPNE_SCASQ: + case XED_ICLASS_REPNE_SCASW: + case XED_ICLASS_REP_INSB: + case XED_ICLASS_REP_INSD: + case XED_ICLASS_REP_INSW: + case XED_ICLASS_REP_LODSB: + case XED_ICLASS_REP_LODSD: + case XED_ICLASS_REP_LODSQ: + case XED_ICLASS_REP_LODSW: + case XED_ICLASS_REP_MONTMUL: + case XED_ICLASS_REP_MOVSB: + case XED_ICLASS_REP_MOVSD: + case XED_ICLASS_REP_MOVSQ: + case XED_ICLASS_REP_MOVSW: + case XED_ICLASS_REP_OUTSB: + case XED_ICLASS_REP_OUTSD: + case XED_ICLASS_REP_OUTSW: + case XED_ICLASS_REP_STOSB: + case XED_ICLASS_REP_STOSD: + case XED_ICLASS_REP_STOSQ: + case XED_ICLASS_REP_STOSW: + case XED_ICLASS_REP_XCRYPTCBC: + case XED_ICLASS_REP_XCRYPTCFB: + case XED_ICLASS_REP_XCRYPTCTR: + case XED_ICLASS_REP_XCRYPTECB: + case XED_ICLASS_REP_XCRYPTOFB: + case XED_ICLASS_REP_XSHA1: + case XED_ICLASS_REP_XSHA256: + case XED_ICLASS_REP_XSTORE: + case XED_ICLASS_RET_FAR: + case XED_ICLASS_RET_NEAR: + case XED_ICLASS_RMPADJUST: + case XED_ICLASS_RMPUPDATE: + case XED_ICLASS_ROL: + case XED_ICLASS_ROR: + case XED_ICLASS_RORX: + case XED_ICLASS_ROUNDPD: + case XED_ICLASS_ROUNDPS: + case XED_ICLASS_ROUNDSD: + case XED_ICLASS_ROUNDSS: + case XED_ICLASS_RSM: + case XED_ICLASS_RSQRTPS: + case XED_ICLASS_RSQRTSS: + case XED_ICLASS_RSTORSSP: + case XED_ICLASS_SAHF: + case XED_ICLASS_SALC: + case XED_ICLASS_SAR: + case XED_ICLASS_SARX: + case XED_ICLASS_SAVEPREVSSP: + case XED_ICLASS_SBB: + case XED_ICLASS_SBB_LOCK: + case XED_ICLASS_SCASB: + case XED_ICLASS_SCASD: + case XED_ICLASS_SCASQ: + case XED_ICLASS_SCASW: + case XED_ICLASS_SEAMCALL: + case XED_ICLASS_SEAMOPS: + case XED_ICLASS_SEAMRET: + case XED_ICLASS_SENDUIPI: + case XED_ICLASS_SERIALIZE: + case XED_ICLASS_SETB: + case XED_ICLASS_SETBE: + case XED_ICLASS_SETL: + case XED_ICLASS_SETLE: + case XED_ICLASS_SETNB: + case XED_ICLASS_SETNBE: + case XED_ICLASS_SETNL: + case XED_ICLASS_SETNLE: + case XED_ICLASS_SETNO: + case XED_ICLASS_SETNP: + case XED_ICLASS_SETNS: + case XED_ICLASS_SETNZ: + case XED_ICLASS_SETO: + case XED_ICLASS_SETP: + case XED_ICLASS_SETS: + case XED_ICLASS_SETSSBSY: + case XED_ICLASS_SETZ: + case XED_ICLASS_SFENCE: + case XED_ICLASS_SGDT: + case XED_ICLASS_SHA1MSG1: + case XED_ICLASS_SHA1MSG2: + case XED_ICLASS_SHA1NEXTE: + case XED_ICLASS_SHA1RNDS4: + case XED_ICLASS_SHA256MSG1: + case XED_ICLASS_SHA256MSG2: + case XED_ICLASS_SHA256RNDS2: + case XED_ICLASS_SHL: + case XED_ICLASS_SHLD: + case XED_ICLASS_SHLX: + case XED_ICLASS_SHR: + case XED_ICLASS_SHRD: + case XED_ICLASS_SHRX: + case XED_ICLASS_SHUFPD: + case XED_ICLASS_SHUFPS: + case XED_ICLASS_SIDT: + case XED_ICLASS_SKINIT: + case XED_ICLASS_SLDT: + case XED_ICLASS_SLWPCB: + case XED_ICLASS_SMSW: + case XED_ICLASS_SQRTPD: + case XED_ICLASS_SQRTPS: + case XED_ICLASS_SQRTSD: + case XED_ICLASS_SQRTSS: + case XED_ICLASS_STAC: + case XED_ICLASS_STC: + case XED_ICLASS_STD: + case XED_ICLASS_STGI: + case XED_ICLASS_STI: + case XED_ICLASS_STMXCSR: + case XED_ICLASS_STOSB: + case XED_ICLASS_STOSD: + case XED_ICLASS_STOSQ: + case XED_ICLASS_STOSW: + case XED_ICLASS_STR: + case XED_ICLASS_STTILECFG: + case XED_ICLASS_STUI: + case XED_ICLASS_SUB: + case XED_ICLASS_SUBPD: + case XED_ICLASS_SUBPS: + case XED_ICLASS_SUBSD: + case XED_ICLASS_SUBSS: + case XED_ICLASS_SUB_LOCK: + case XED_ICLASS_SWAPGS: + case XED_ICLASS_SYSCALL: + case XED_ICLASS_SYSCALL_AMD: + case XED_ICLASS_SYSENTER: + case XED_ICLASS_SYSEXIT: + case XED_ICLASS_SYSRET: + case XED_ICLASS_SYSRET64: + case XED_ICLASS_SYSRET_AMD: + case XED_ICLASS_T1MSKC: + case XED_ICLASS_TDCALL: + case XED_ICLASS_TDPBF16PS: + case XED_ICLASS_TDPBSSD: + case XED_ICLASS_TDPBSUD: + case XED_ICLASS_TDPBUSD: + case XED_ICLASS_TDPBUUD: + case XED_ICLASS_TEST: + case XED_ICLASS_TESTUI: + case XED_ICLASS_TILELOADD: + case XED_ICLASS_TILELOADDT1: + case XED_ICLASS_TILERELEASE: + case XED_ICLASS_TILESTORED: + case XED_ICLASS_TILEZERO: + case XED_ICLASS_TLBSYNC: + case XED_ICLASS_TPAUSE: + case XED_ICLASS_TZCNT: + case XED_ICLASS_TZMSK: + case XED_ICLASS_UCOMISD: + case XED_ICLASS_UCOMISS: + case XED_ICLASS_UD0: + case XED_ICLASS_UD1: + case XED_ICLASS_UD2: + case XED_ICLASS_UIRET: + case XED_ICLASS_UMONITOR: + case XED_ICLASS_UMWAIT: + case XED_ICLASS_UNPCKHPD: + case XED_ICLASS_UNPCKHPS: + case XED_ICLASS_UNPCKLPD: + case XED_ICLASS_UNPCKLPS: + case XED_ICLASS_V4FMADDPS: + case XED_ICLASS_V4FMADDSS: + case XED_ICLASS_V4FNMADDPS: + case XED_ICLASS_V4FNMADDSS: + case XED_ICLASS_VADDPD: + case XED_ICLASS_VADDPH: + case XED_ICLASS_VADDPS: + case XED_ICLASS_VADDSD: + case XED_ICLASS_VADDSH: + case XED_ICLASS_VADDSS: + case XED_ICLASS_VADDSUBPD: + case XED_ICLASS_VADDSUBPS: + case XED_ICLASS_VAESDEC: + case XED_ICLASS_VAESDECLAST: + case XED_ICLASS_VAESENC: + case XED_ICLASS_VAESENCLAST: + case XED_ICLASS_VAESIMC: + case XED_ICLASS_VAESKEYGENASSIST: + case XED_ICLASS_VALIGND: + case XED_ICLASS_VALIGNQ: + case XED_ICLASS_VANDNPD: + case XED_ICLASS_VANDNPS: + case XED_ICLASS_VANDPD: + case XED_ICLASS_VANDPS: + case XED_ICLASS_VBLENDMPD: + case XED_ICLASS_VBLENDMPS: + case XED_ICLASS_VBLENDPD: + case XED_ICLASS_VBLENDPS: + case XED_ICLASS_VBLENDVPD: + case XED_ICLASS_VBLENDVPS: + case XED_ICLASS_VBROADCASTF128: + case XED_ICLASS_VBROADCASTF32X2: + case XED_ICLASS_VBROADCASTF32X4: + case XED_ICLASS_VBROADCASTF32X8: + case XED_ICLASS_VBROADCASTF64X2: + case XED_ICLASS_VBROADCASTF64X4: + case XED_ICLASS_VBROADCASTI128: + case XED_ICLASS_VBROADCASTI32X2: + case XED_ICLASS_VBROADCASTI32X4: + case XED_ICLASS_VBROADCASTI32X8: + case XED_ICLASS_VBROADCASTI64X2: + case XED_ICLASS_VBROADCASTI64X4: + case XED_ICLASS_VBROADCASTSD: + case XED_ICLASS_VBROADCASTSS: + case XED_ICLASS_VCMPPD: + case XED_ICLASS_VCMPPH: + case XED_ICLASS_VCMPPS: + case XED_ICLASS_VCMPSD: + case XED_ICLASS_VCMPSH: + case XED_ICLASS_VCMPSS: + case XED_ICLASS_VCOMISD: + case XED_ICLASS_VCOMISH: + case XED_ICLASS_VCOMISS: + case XED_ICLASS_VCOMPRESSPD: + case XED_ICLASS_VCOMPRESSPS: + case XED_ICLASS_VCVTDQ2PD: + case XED_ICLASS_VCVTDQ2PH: + case XED_ICLASS_VCVTDQ2PS: + case XED_ICLASS_VCVTNE2PS2BF16: + case XED_ICLASS_VCVTNEPS2BF16: + case XED_ICLASS_VCVTPD2DQ: + case XED_ICLASS_VCVTPD2PH: + case XED_ICLASS_VCVTPD2PS: + case XED_ICLASS_VCVTPD2QQ: + case XED_ICLASS_VCVTPD2UDQ: + case XED_ICLASS_VCVTPD2UQQ: + case XED_ICLASS_VCVTPH2DQ: + case XED_ICLASS_VCVTPH2PD: + case XED_ICLASS_VCVTPH2PS: + case XED_ICLASS_VCVTPH2PSX: + case XED_ICLASS_VCVTPH2QQ: + case XED_ICLASS_VCVTPH2UDQ: + case XED_ICLASS_VCVTPH2UQQ: + case XED_ICLASS_VCVTPH2UW: + case XED_ICLASS_VCVTPH2W: + case XED_ICLASS_VCVTPS2DQ: + case XED_ICLASS_VCVTPS2PD: + case XED_ICLASS_VCVTPS2PH: + case XED_ICLASS_VCVTPS2PHX: + case XED_ICLASS_VCVTPS2QQ: + case XED_ICLASS_VCVTPS2UDQ: + case XED_ICLASS_VCVTPS2UQQ: + case XED_ICLASS_VCVTQQ2PD: + case XED_ICLASS_VCVTQQ2PH: + case XED_ICLASS_VCVTQQ2PS: + case XED_ICLASS_VCVTSD2SH: + case XED_ICLASS_VCVTSD2SI: + case XED_ICLASS_VCVTSD2SS: + case XED_ICLASS_VCVTSD2USI: + case XED_ICLASS_VCVTSH2SD: + case XED_ICLASS_VCVTSH2SI: + case XED_ICLASS_VCVTSH2SS: + case XED_ICLASS_VCVTSH2USI: + case XED_ICLASS_VCVTSI2SD: + case XED_ICLASS_VCVTSI2SH: + case XED_ICLASS_VCVTSI2SS: + case XED_ICLASS_VCVTSS2SD: + case XED_ICLASS_VCVTSS2SH: + case XED_ICLASS_VCVTSS2SI: + case XED_ICLASS_VCVTSS2USI: + case XED_ICLASS_VCVTTPD2DQ: + case XED_ICLASS_VCVTTPD2QQ: + case XED_ICLASS_VCVTTPD2UDQ: + case XED_ICLASS_VCVTTPD2UQQ: + case XED_ICLASS_VCVTTPH2DQ: + case XED_ICLASS_VCVTTPH2QQ: + case XED_ICLASS_VCVTTPH2UDQ: + case XED_ICLASS_VCVTTPH2UQQ: + case XED_ICLASS_VCVTTPH2UW: + case XED_ICLASS_VCVTTPH2W: + case XED_ICLASS_VCVTTPS2DQ: + case XED_ICLASS_VCVTTPS2QQ: + case XED_ICLASS_VCVTTPS2UDQ: + case XED_ICLASS_VCVTTPS2UQQ: + case XED_ICLASS_VCVTTSD2SI: + case XED_ICLASS_VCVTTSD2USI: + case XED_ICLASS_VCVTTSH2SI: + case XED_ICLASS_VCVTTSH2USI: + case XED_ICLASS_VCVTTSS2SI: + case XED_ICLASS_VCVTTSS2USI: + case XED_ICLASS_VCVTUDQ2PD: + case XED_ICLASS_VCVTUDQ2PH: + case XED_ICLASS_VCVTUDQ2PS: + case XED_ICLASS_VCVTUQQ2PD: + case XED_ICLASS_VCVTUQQ2PH: + case XED_ICLASS_VCVTUQQ2PS: + case XED_ICLASS_VCVTUSI2SD: + case XED_ICLASS_VCVTUSI2SH: + case XED_ICLASS_VCVTUSI2SS: + case XED_ICLASS_VCVTUW2PH: + case XED_ICLASS_VCVTW2PH: + case XED_ICLASS_VDBPSADBW: + case XED_ICLASS_VDIVPD: + case XED_ICLASS_VDIVPH: + case XED_ICLASS_VDIVPS: + case XED_ICLASS_VDIVSD: + case XED_ICLASS_VDIVSH: + case XED_ICLASS_VDIVSS: + case XED_ICLASS_VDPBF16PS: + case XED_ICLASS_VDPPD: + case XED_ICLASS_VDPPS: + case XED_ICLASS_VERR: + case XED_ICLASS_VERW: + case XED_ICLASS_VEXP2PD: + case XED_ICLASS_VEXP2PS: + case XED_ICLASS_VEXPANDPD: + case XED_ICLASS_VEXPANDPS: + case XED_ICLASS_VEXTRACTF128: + case XED_ICLASS_VEXTRACTF32X4: + case XED_ICLASS_VEXTRACTF32X8: + case XED_ICLASS_VEXTRACTF64X2: + case XED_ICLASS_VEXTRACTF64X4: + case XED_ICLASS_VEXTRACTI128: + case XED_ICLASS_VEXTRACTI32X4: + case XED_ICLASS_VEXTRACTI32X8: + case XED_ICLASS_VEXTRACTI64X2: + case XED_ICLASS_VEXTRACTI64X4: + case XED_ICLASS_VEXTRACTPS: + case XED_ICLASS_VFCMADDCPH: + case XED_ICLASS_VFCMADDCSH: + case XED_ICLASS_VFCMULCPH: + case XED_ICLASS_VFCMULCSH: + case XED_ICLASS_VFIXUPIMMPD: + case XED_ICLASS_VFIXUPIMMPS: + case XED_ICLASS_VFIXUPIMMSD: + case XED_ICLASS_VFIXUPIMMSS: + case XED_ICLASS_VFMADD132PD: + case XED_ICLASS_VFMADD132PH: + case XED_ICLASS_VFMADD132PS: + case XED_ICLASS_VFMADD132SD: + case XED_ICLASS_VFMADD132SH: + case XED_ICLASS_VFMADD132SS: + case XED_ICLASS_VFMADD213PD: + case XED_ICLASS_VFMADD213PH: + case XED_ICLASS_VFMADD213PS: + case XED_ICLASS_VFMADD213SD: + case XED_ICLASS_VFMADD213SH: + case XED_ICLASS_VFMADD213SS: + case XED_ICLASS_VFMADD231PD: + case XED_ICLASS_VFMADD231PH: + case XED_ICLASS_VFMADD231PS: + case XED_ICLASS_VFMADD231SD: + case XED_ICLASS_VFMADD231SH: + case XED_ICLASS_VFMADD231SS: + case XED_ICLASS_VFMADDCPH: + case XED_ICLASS_VFMADDCSH: + case XED_ICLASS_VFMADDPD: + case XED_ICLASS_VFMADDPS: + case XED_ICLASS_VFMADDSD: + case XED_ICLASS_VFMADDSS: + case XED_ICLASS_VFMADDSUB132PD: + case XED_ICLASS_VFMADDSUB132PH: + case XED_ICLASS_VFMADDSUB132PS: + case XED_ICLASS_VFMADDSUB213PD: + case XED_ICLASS_VFMADDSUB213PH: + case XED_ICLASS_VFMADDSUB213PS: + case XED_ICLASS_VFMADDSUB231PD: + case XED_ICLASS_VFMADDSUB231PH: + case XED_ICLASS_VFMADDSUB231PS: + case XED_ICLASS_VFMADDSUBPD: + case XED_ICLASS_VFMADDSUBPS: + case XED_ICLASS_VFMSUB132PD: + case XED_ICLASS_VFMSUB132PH: + case XED_ICLASS_VFMSUB132PS: + case XED_ICLASS_VFMSUB132SD: + case XED_ICLASS_VFMSUB132SH: + case XED_ICLASS_VFMSUB132SS: + case XED_ICLASS_VFMSUB213PD: + case XED_ICLASS_VFMSUB213PH: + case XED_ICLASS_VFMSUB213PS: + case XED_ICLASS_VFMSUB213SD: + case XED_ICLASS_VFMSUB213SH: + case XED_ICLASS_VFMSUB213SS: + case XED_ICLASS_VFMSUB231PD: + case XED_ICLASS_VFMSUB231PH: + case XED_ICLASS_VFMSUB231PS: + case XED_ICLASS_VFMSUB231SD: + case XED_ICLASS_VFMSUB231SH: + case XED_ICLASS_VFMSUB231SS: + case XED_ICLASS_VFMSUBADD132PD: + case XED_ICLASS_VFMSUBADD132PH: + case XED_ICLASS_VFMSUBADD132PS: + case XED_ICLASS_VFMSUBADD213PD: + case XED_ICLASS_VFMSUBADD213PH: + case XED_ICLASS_VFMSUBADD213PS: + case XED_ICLASS_VFMSUBADD231PD: + case XED_ICLASS_VFMSUBADD231PH: + case XED_ICLASS_VFMSUBADD231PS: + case XED_ICLASS_VFMSUBADDPD: + case XED_ICLASS_VFMSUBADDPS: + case XED_ICLASS_VFMSUBPD: + case XED_ICLASS_VFMSUBPS: + case XED_ICLASS_VFMSUBSD: + case XED_ICLASS_VFMSUBSS: + case XED_ICLASS_VFMULCPH: + case XED_ICLASS_VFMULCSH: + case XED_ICLASS_VFNMADD132PD: + case XED_ICLASS_VFNMADD132PH: + case XED_ICLASS_VFNMADD132PS: + case XED_ICLASS_VFNMADD132SD: + case XED_ICLASS_VFNMADD132SH: + case XED_ICLASS_VFNMADD132SS: + case XED_ICLASS_VFNMADD213PD: + case XED_ICLASS_VFNMADD213PH: + case XED_ICLASS_VFNMADD213PS: + case XED_ICLASS_VFNMADD213SD: + case XED_ICLASS_VFNMADD213SH: + case XED_ICLASS_VFNMADD213SS: + case XED_ICLASS_VFNMADD231PD: + case XED_ICLASS_VFNMADD231PH: + case XED_ICLASS_VFNMADD231PS: + case XED_ICLASS_VFNMADD231SD: + case XED_ICLASS_VFNMADD231SH: + case XED_ICLASS_VFNMADD231SS: + case XED_ICLASS_VFNMADDPD: + case XED_ICLASS_VFNMADDPS: + case XED_ICLASS_VFNMADDSD: + case XED_ICLASS_VFNMADDSS: + case XED_ICLASS_VFNMSUB132PD: + case XED_ICLASS_VFNMSUB132PH: + case XED_ICLASS_VFNMSUB132PS: + case XED_ICLASS_VFNMSUB132SD: + case XED_ICLASS_VFNMSUB132SH: + case XED_ICLASS_VFNMSUB132SS: + case XED_ICLASS_VFNMSUB213PD: + case XED_ICLASS_VFNMSUB213PH: + case XED_ICLASS_VFNMSUB213PS: + case XED_ICLASS_VFNMSUB213SD: + case XED_ICLASS_VFNMSUB213SH: + case XED_ICLASS_VFNMSUB213SS: + case XED_ICLASS_VFNMSUB231PD: + case XED_ICLASS_VFNMSUB231PH: + case XED_ICLASS_VFNMSUB231PS: + case XED_ICLASS_VFNMSUB231SD: + case XED_ICLASS_VFNMSUB231SH: + case XED_ICLASS_VFNMSUB231SS: + case XED_ICLASS_VFNMSUBPD: + case XED_ICLASS_VFNMSUBPS: + case XED_ICLASS_VFNMSUBSD: + case XED_ICLASS_VFNMSUBSS: + case XED_ICLASS_VFPCLASSPD: + case XED_ICLASS_VFPCLASSPH: + case XED_ICLASS_VFPCLASSPS: + case XED_ICLASS_VFPCLASSSD: + case XED_ICLASS_VFPCLASSSH: + case XED_ICLASS_VFPCLASSSS: + case XED_ICLASS_VFRCZPD: + case XED_ICLASS_VFRCZPS: + case XED_ICLASS_VFRCZSD: + case XED_ICLASS_VFRCZSS: + case XED_ICLASS_VGATHERDPD: + case XED_ICLASS_VGATHERDPS: + case XED_ICLASS_VGATHERPF0DPD: + case XED_ICLASS_VGATHERPF0DPS: + case XED_ICLASS_VGATHERPF0QPD: + case XED_ICLASS_VGATHERPF0QPS: + case XED_ICLASS_VGATHERPF1DPD: + case XED_ICLASS_VGATHERPF1DPS: + case XED_ICLASS_VGATHERPF1QPD: + case XED_ICLASS_VGATHERPF1QPS: + case XED_ICLASS_VGATHERQPD: + case XED_ICLASS_VGATHERQPS: + case XED_ICLASS_VGETEXPPD: + case XED_ICLASS_VGETEXPPH: + case XED_ICLASS_VGETEXPPS: + case XED_ICLASS_VGETEXPSD: + case XED_ICLASS_VGETEXPSH: + case XED_ICLASS_VGETEXPSS: + case XED_ICLASS_VGETMANTPD: + case XED_ICLASS_VGETMANTPH: + case XED_ICLASS_VGETMANTPS: + case XED_ICLASS_VGETMANTSD: + case XED_ICLASS_VGETMANTSH: + case XED_ICLASS_VGETMANTSS: + case XED_ICLASS_VGF2P8AFFINEINVQB: + case XED_ICLASS_VGF2P8AFFINEQB: + case XED_ICLASS_VGF2P8MULB: + case XED_ICLASS_VHADDPD: + case XED_ICLASS_VHADDPS: + case XED_ICLASS_VHSUBPD: + case XED_ICLASS_VHSUBPS: + case XED_ICLASS_VINSERTF128: + case XED_ICLASS_VINSERTF32X4: + case XED_ICLASS_VINSERTF32X8: + case XED_ICLASS_VINSERTF64X2: + case XED_ICLASS_VINSERTF64X4: + case XED_ICLASS_VINSERTI128: + case XED_ICLASS_VINSERTI32X4: + case XED_ICLASS_VINSERTI32X8: + case XED_ICLASS_VINSERTI64X2: + case XED_ICLASS_VINSERTI64X4: + case XED_ICLASS_VINSERTPS: + case XED_ICLASS_VLDDQU: + case XED_ICLASS_VLDMXCSR: + case XED_ICLASS_VMASKMOVDQU: + case XED_ICLASS_VMASKMOVPD: + case XED_ICLASS_VMASKMOVPS: + case XED_ICLASS_VMAXPD: + case XED_ICLASS_VMAXPH: + case XED_ICLASS_VMAXPS: + case XED_ICLASS_VMAXSD: + case XED_ICLASS_VMAXSH: + case XED_ICLASS_VMAXSS: + case XED_ICLASS_VMCALL: + case XED_ICLASS_VMCLEAR: + case XED_ICLASS_VMFUNC: + case XED_ICLASS_VMINPD: + case XED_ICLASS_VMINPH: + case XED_ICLASS_VMINPS: + case XED_ICLASS_VMINSD: + case XED_ICLASS_VMINSH: + case XED_ICLASS_VMINSS: + case XED_ICLASS_VMLAUNCH: + case XED_ICLASS_VMLOAD: + case XED_ICLASS_VMMCALL: + case XED_ICLASS_VMOVAPD: + case XED_ICLASS_VMOVAPS: + case XED_ICLASS_VMOVD: + case XED_ICLASS_VMOVDDUP: + case XED_ICLASS_VMOVDQA: + case XED_ICLASS_VMOVDQA32: + case XED_ICLASS_VMOVDQA64: + case XED_ICLASS_VMOVDQU: + case XED_ICLASS_VMOVDQU16: + case XED_ICLASS_VMOVDQU32: + case XED_ICLASS_VMOVDQU64: + case XED_ICLASS_VMOVDQU8: + case XED_ICLASS_VMOVHLPS: + case XED_ICLASS_VMOVHPD: + case XED_ICLASS_VMOVHPS: + case XED_ICLASS_VMOVLHPS: + case XED_ICLASS_VMOVLPD: + case XED_ICLASS_VMOVLPS: + case XED_ICLASS_VMOVMSKPD: + case XED_ICLASS_VMOVMSKPS: + case XED_ICLASS_VMOVNTDQ: + case XED_ICLASS_VMOVNTDQA: + case XED_ICLASS_VMOVNTPD: + case XED_ICLASS_VMOVNTPS: + case XED_ICLASS_VMOVQ: + case XED_ICLASS_VMOVSD: + case XED_ICLASS_VMOVSH: + case XED_ICLASS_VMOVSHDUP: + case XED_ICLASS_VMOVSLDUP: + case XED_ICLASS_VMOVSS: + case XED_ICLASS_VMOVUPD: + case XED_ICLASS_VMOVUPS: + case XED_ICLASS_VMOVW: + case XED_ICLASS_VMPSADBW: + case XED_ICLASS_VMPTRLD: + case XED_ICLASS_VMPTRST: + case XED_ICLASS_VMREAD: + case XED_ICLASS_VMRESUME: + case XED_ICLASS_VMRUN: + case XED_ICLASS_VMSAVE: + case XED_ICLASS_VMULPD: + case XED_ICLASS_VMULPH: + case XED_ICLASS_VMULPS: + case XED_ICLASS_VMULSD: + case XED_ICLASS_VMULSH: + case XED_ICLASS_VMULSS: + case XED_ICLASS_VMWRITE: + case XED_ICLASS_VMXOFF: + case XED_ICLASS_VMXON: + case XED_ICLASS_VORPD: + case XED_ICLASS_VORPS: + case XED_ICLASS_VP2INTERSECTD: + case XED_ICLASS_VP2INTERSECTQ: + case XED_ICLASS_VP4DPWSSD: + case XED_ICLASS_VP4DPWSSDS: + case XED_ICLASS_VPABSB: + case XED_ICLASS_VPABSD: + case XED_ICLASS_VPABSQ: + case XED_ICLASS_VPABSW: + case XED_ICLASS_VPACKSSDW: + case XED_ICLASS_VPACKSSWB: + case XED_ICLASS_VPACKUSDW: + case XED_ICLASS_VPACKUSWB: + case XED_ICLASS_VPADDB: + case XED_ICLASS_VPADDD: + case XED_ICLASS_VPADDQ: + case XED_ICLASS_VPADDSB: + case XED_ICLASS_VPADDSW: + case XED_ICLASS_VPADDUSB: + case XED_ICLASS_VPADDUSW: + case XED_ICLASS_VPADDW: + case XED_ICLASS_VPALIGNR: + case XED_ICLASS_VPAND: + case XED_ICLASS_VPANDD: + case XED_ICLASS_VPANDN: + case XED_ICLASS_VPANDND: + case XED_ICLASS_VPANDNQ: + case XED_ICLASS_VPANDQ: + case XED_ICLASS_VPAVGB: + case XED_ICLASS_VPAVGW: + case XED_ICLASS_VPBLENDD: + case XED_ICLASS_VPBLENDMB: + case XED_ICLASS_VPBLENDMD: + case XED_ICLASS_VPBLENDMQ: + case XED_ICLASS_VPBLENDMW: + case XED_ICLASS_VPBLENDVB: + case XED_ICLASS_VPBLENDW: + case XED_ICLASS_VPBROADCASTB: + case XED_ICLASS_VPBROADCASTD: + case XED_ICLASS_VPBROADCASTMB2Q: + case XED_ICLASS_VPBROADCASTMW2D: + case XED_ICLASS_VPBROADCASTQ: + case XED_ICLASS_VPBROADCASTW: + case XED_ICLASS_VPCLMULQDQ: + case XED_ICLASS_VPCMOV: + case XED_ICLASS_VPCMPB: + case XED_ICLASS_VPCMPD: + case XED_ICLASS_VPCMPEQB: + case XED_ICLASS_VPCMPEQD: + case XED_ICLASS_VPCMPEQQ: + case XED_ICLASS_VPCMPEQW: + case XED_ICLASS_VPCMPESTRI: + case XED_ICLASS_VPCMPESTRI64: + case XED_ICLASS_VPCMPESTRM: + case XED_ICLASS_VPCMPESTRM64: + case XED_ICLASS_VPCMPGTB: + case XED_ICLASS_VPCMPGTD: + case XED_ICLASS_VPCMPGTQ: + case XED_ICLASS_VPCMPGTW: + case XED_ICLASS_VPCMPISTRI: + case XED_ICLASS_VPCMPISTRI64: + case XED_ICLASS_VPCMPISTRM: + case XED_ICLASS_VPCMPQ: + case XED_ICLASS_VPCMPUB: + case XED_ICLASS_VPCMPUD: + case XED_ICLASS_VPCMPUQ: + case XED_ICLASS_VPCMPUW: + case XED_ICLASS_VPCMPW: + case XED_ICLASS_VPCOMB: + case XED_ICLASS_VPCOMD: + case XED_ICLASS_VPCOMPRESSB: + case XED_ICLASS_VPCOMPRESSD: + case XED_ICLASS_VPCOMPRESSQ: + case XED_ICLASS_VPCOMPRESSW: + case XED_ICLASS_VPCOMQ: + case XED_ICLASS_VPCOMUB: + case XED_ICLASS_VPCOMUD: + case XED_ICLASS_VPCOMUQ: + case XED_ICLASS_VPCOMUW: + case XED_ICLASS_VPCOMW: + case XED_ICLASS_VPCONFLICTD: + case XED_ICLASS_VPCONFLICTQ: + case XED_ICLASS_VPDPBUSD: + case XED_ICLASS_VPDPBUSDS: + case XED_ICLASS_VPDPWSSD: + case XED_ICLASS_VPDPWSSDS: + case XED_ICLASS_VPERM2F128: + case XED_ICLASS_VPERM2I128: + case XED_ICLASS_VPERMB: + case XED_ICLASS_VPERMD: + case XED_ICLASS_VPERMI2B: + case XED_ICLASS_VPERMI2D: + case XED_ICLASS_VPERMI2PD: + case XED_ICLASS_VPERMI2PS: + case XED_ICLASS_VPERMI2Q: + case XED_ICLASS_VPERMI2W: + case XED_ICLASS_VPERMIL2PD: + case XED_ICLASS_VPERMIL2PS: + case XED_ICLASS_VPERMILPD: + case XED_ICLASS_VPERMILPS: + case XED_ICLASS_VPERMPD: + case XED_ICLASS_VPERMPS: + case XED_ICLASS_VPERMQ: + case XED_ICLASS_VPERMT2B: + case XED_ICLASS_VPERMT2D: + case XED_ICLASS_VPERMT2PD: + case XED_ICLASS_VPERMT2PS: + case XED_ICLASS_VPERMT2Q: + case XED_ICLASS_VPERMT2W: + case XED_ICLASS_VPERMW: + case XED_ICLASS_VPEXPANDB: + case XED_ICLASS_VPEXPANDD: + case XED_ICLASS_VPEXPANDQ: + case XED_ICLASS_VPEXPANDW: + case XED_ICLASS_VPEXTRB: + case XED_ICLASS_VPEXTRD: + case XED_ICLASS_VPEXTRQ: + case XED_ICLASS_VPEXTRW: + case XED_ICLASS_VPEXTRW_C5: + case XED_ICLASS_VPGATHERDD: + case XED_ICLASS_VPGATHERDQ: + case XED_ICLASS_VPGATHERQD: + case XED_ICLASS_VPGATHERQQ: + case XED_ICLASS_VPHADDBD: + case XED_ICLASS_VPHADDBQ: + case XED_ICLASS_VPHADDBW: + case XED_ICLASS_VPHADDD: + case XED_ICLASS_VPHADDDQ: + case XED_ICLASS_VPHADDSW: + case XED_ICLASS_VPHADDUBD: + case XED_ICLASS_VPHADDUBQ: + case XED_ICLASS_VPHADDUBW: + case XED_ICLASS_VPHADDUDQ: + case XED_ICLASS_VPHADDUWD: + case XED_ICLASS_VPHADDUWQ: + case XED_ICLASS_VPHADDW: + case XED_ICLASS_VPHADDWD: + case XED_ICLASS_VPHADDWQ: + case XED_ICLASS_VPHMINPOSUW: + case XED_ICLASS_VPHSUBBW: + case XED_ICLASS_VPHSUBD: + case XED_ICLASS_VPHSUBDQ: + case XED_ICLASS_VPHSUBSW: + case XED_ICLASS_VPHSUBW: + case XED_ICLASS_VPHSUBWD: + case XED_ICLASS_VPINSRB: + case XED_ICLASS_VPINSRD: + case XED_ICLASS_VPINSRQ: + case XED_ICLASS_VPINSRW: + case XED_ICLASS_VPLZCNTD: + case XED_ICLASS_VPLZCNTQ: + case XED_ICLASS_VPMACSDD: + case XED_ICLASS_VPMACSDQH: + case XED_ICLASS_VPMACSDQL: + case XED_ICLASS_VPMACSSDD: + case XED_ICLASS_VPMACSSDQH: + case XED_ICLASS_VPMACSSDQL: + case XED_ICLASS_VPMACSSWD: + case XED_ICLASS_VPMACSSWW: + case XED_ICLASS_VPMACSWD: + case XED_ICLASS_VPMACSWW: + case XED_ICLASS_VPMADCSSWD: + case XED_ICLASS_VPMADCSWD: + case XED_ICLASS_VPMADD52HUQ: + case XED_ICLASS_VPMADD52LUQ: + case XED_ICLASS_VPMADDUBSW: + case XED_ICLASS_VPMADDWD: + case XED_ICLASS_VPMASKMOVD: + case XED_ICLASS_VPMASKMOVQ: + case XED_ICLASS_VPMAXSB: + case XED_ICLASS_VPMAXSD: + case XED_ICLASS_VPMAXSQ: + case XED_ICLASS_VPMAXSW: + case XED_ICLASS_VPMAXUB: + case XED_ICLASS_VPMAXUD: + case XED_ICLASS_VPMAXUQ: + case XED_ICLASS_VPMAXUW: + case XED_ICLASS_VPMINSB: + case XED_ICLASS_VPMINSD: + case XED_ICLASS_VPMINSQ: + case XED_ICLASS_VPMINSW: + case XED_ICLASS_VPMINUB: + case XED_ICLASS_VPMINUD: + case XED_ICLASS_VPMINUQ: + case XED_ICLASS_VPMINUW: + case XED_ICLASS_VPMOVB2M: + case XED_ICLASS_VPMOVD2M: + case XED_ICLASS_VPMOVDB: + case XED_ICLASS_VPMOVDW: + case XED_ICLASS_VPMOVM2B: + case XED_ICLASS_VPMOVM2D: + case XED_ICLASS_VPMOVM2Q: + case XED_ICLASS_VPMOVM2W: + case XED_ICLASS_VPMOVMSKB: + case XED_ICLASS_VPMOVQ2M: + case XED_ICLASS_VPMOVQB: + case XED_ICLASS_VPMOVQD: + case XED_ICLASS_VPMOVQW: + case XED_ICLASS_VPMOVSDB: + case XED_ICLASS_VPMOVSDW: + case XED_ICLASS_VPMOVSQB: + case XED_ICLASS_VPMOVSQD: + case XED_ICLASS_VPMOVSQW: + case XED_ICLASS_VPMOVSWB: + case XED_ICLASS_VPMOVSXBD: + case XED_ICLASS_VPMOVSXBQ: + case XED_ICLASS_VPMOVSXBW: + case XED_ICLASS_VPMOVSXDQ: + case XED_ICLASS_VPMOVSXWD: + case XED_ICLASS_VPMOVSXWQ: + case XED_ICLASS_VPMOVUSDB: + case XED_ICLASS_VPMOVUSDW: + case XED_ICLASS_VPMOVUSQB: + case XED_ICLASS_VPMOVUSQD: + case XED_ICLASS_VPMOVUSQW: + case XED_ICLASS_VPMOVUSWB: + case XED_ICLASS_VPMOVW2M: + case XED_ICLASS_VPMOVWB: + case XED_ICLASS_VPMOVZXBD: + case XED_ICLASS_VPMOVZXBQ: + case XED_ICLASS_VPMOVZXBW: + case XED_ICLASS_VPMOVZXDQ: + case XED_ICLASS_VPMOVZXWD: + case XED_ICLASS_VPMOVZXWQ: + case XED_ICLASS_VPMULDQ: + case XED_ICLASS_VPMULHRSW: + case XED_ICLASS_VPMULHUW: + case XED_ICLASS_VPMULHW: + case XED_ICLASS_VPMULLD: + case XED_ICLASS_VPMULLQ: + case XED_ICLASS_VPMULLW: + case XED_ICLASS_VPMULTISHIFTQB: + case XED_ICLASS_VPMULUDQ: + case XED_ICLASS_VPOPCNTB: + case XED_ICLASS_VPOPCNTD: + case XED_ICLASS_VPOPCNTQ: + case XED_ICLASS_VPOPCNTW: + case XED_ICLASS_VPOR: + case XED_ICLASS_VPORD: + case XED_ICLASS_VPORQ: + case XED_ICLASS_VPPERM: + case XED_ICLASS_VPROLD: + case XED_ICLASS_VPROLQ: + case XED_ICLASS_VPROLVD: + case XED_ICLASS_VPROLVQ: + case XED_ICLASS_VPRORD: + case XED_ICLASS_VPRORQ: + case XED_ICLASS_VPRORVD: + case XED_ICLASS_VPRORVQ: + case XED_ICLASS_VPROTB: + case XED_ICLASS_VPROTD: + case XED_ICLASS_VPROTQ: + case XED_ICLASS_VPROTW: + case XED_ICLASS_VPSADBW: + case XED_ICLASS_VPSCATTERDD: + case XED_ICLASS_VPSCATTERDQ: + case XED_ICLASS_VPSCATTERQD: + case XED_ICLASS_VPSCATTERQQ: + case XED_ICLASS_VPSHAB: + case XED_ICLASS_VPSHAD: + case XED_ICLASS_VPSHAQ: + case XED_ICLASS_VPSHAW: + case XED_ICLASS_VPSHLB: + case XED_ICLASS_VPSHLD: + case XED_ICLASS_VPSHLDD: + case XED_ICLASS_VPSHLDQ: + case XED_ICLASS_VPSHLDVD: + case XED_ICLASS_VPSHLDVQ: + case XED_ICLASS_VPSHLDVW: + case XED_ICLASS_VPSHLDW: + case XED_ICLASS_VPSHLQ: + case XED_ICLASS_VPSHLW: + case XED_ICLASS_VPSHRDD: + case XED_ICLASS_VPSHRDQ: + case XED_ICLASS_VPSHRDVD: + case XED_ICLASS_VPSHRDVQ: + case XED_ICLASS_VPSHRDVW: + case XED_ICLASS_VPSHRDW: + case XED_ICLASS_VPSHUFB: + case XED_ICLASS_VPSHUFBITQMB: + case XED_ICLASS_VPSHUFD: + case XED_ICLASS_VPSHUFHW: + case XED_ICLASS_VPSHUFLW: + case XED_ICLASS_VPSIGNB: + case XED_ICLASS_VPSIGND: + case XED_ICLASS_VPSIGNW: + case XED_ICLASS_VPSLLD: + case XED_ICLASS_VPSLLDQ: + case XED_ICLASS_VPSLLQ: + case XED_ICLASS_VPSLLVD: + case XED_ICLASS_VPSLLVQ: + case XED_ICLASS_VPSLLVW: + case XED_ICLASS_VPSLLW: + case XED_ICLASS_VPSRAD: + case XED_ICLASS_VPSRAQ: + case XED_ICLASS_VPSRAVD: + case XED_ICLASS_VPSRAVQ: + case XED_ICLASS_VPSRAVW: + case XED_ICLASS_VPSRAW: + case XED_ICLASS_VPSRLD: + case XED_ICLASS_VPSRLDQ: + case XED_ICLASS_VPSRLQ: + case XED_ICLASS_VPSRLVD: + case XED_ICLASS_VPSRLVQ: + case XED_ICLASS_VPSRLVW: + case XED_ICLASS_VPSRLW: + case XED_ICLASS_VPSUBB: + case XED_ICLASS_VPSUBD: + case XED_ICLASS_VPSUBQ: + case XED_ICLASS_VPSUBSB: + case XED_ICLASS_VPSUBSW: + case XED_ICLASS_VPSUBUSB: + case XED_ICLASS_VPSUBUSW: + case XED_ICLASS_VPSUBW: + case XED_ICLASS_VPTERNLOGD: + case XED_ICLASS_VPTERNLOGQ: + case XED_ICLASS_VPTEST: + case XED_ICLASS_VPTESTMB: + case XED_ICLASS_VPTESTMD: + case XED_ICLASS_VPTESTMQ: + case XED_ICLASS_VPTESTMW: + case XED_ICLASS_VPTESTNMB: + case XED_ICLASS_VPTESTNMD: + case XED_ICLASS_VPTESTNMQ: + case XED_ICLASS_VPTESTNMW: + case XED_ICLASS_VPUNPCKHBW: + case XED_ICLASS_VPUNPCKHDQ: + case XED_ICLASS_VPUNPCKHQDQ: + case XED_ICLASS_VPUNPCKHWD: + case XED_ICLASS_VPUNPCKLBW: + case XED_ICLASS_VPUNPCKLDQ: + case XED_ICLASS_VPUNPCKLQDQ: + case XED_ICLASS_VPUNPCKLWD: + case XED_ICLASS_VPXOR: + case XED_ICLASS_VPXORD: + case XED_ICLASS_VPXORQ: + case XED_ICLASS_VRANGEPD: + case XED_ICLASS_VRANGEPS: + case XED_ICLASS_VRANGESD: + case XED_ICLASS_VRANGESS: + case XED_ICLASS_VRCP14PD: + case XED_ICLASS_VRCP14PS: + case XED_ICLASS_VRCP14SD: + case XED_ICLASS_VRCP14SS: + case XED_ICLASS_VRCP28PD: + case XED_ICLASS_VRCP28PS: + case XED_ICLASS_VRCP28SD: + case XED_ICLASS_VRCP28SS: + case XED_ICLASS_VRCPPH: + case XED_ICLASS_VRCPPS: + case XED_ICLASS_VRCPSH: + case XED_ICLASS_VRCPSS: + case XED_ICLASS_VREDUCEPD: + case XED_ICLASS_VREDUCEPH: + case XED_ICLASS_VREDUCEPS: + case XED_ICLASS_VREDUCESD: + case XED_ICLASS_VREDUCESH: + case XED_ICLASS_VREDUCESS: + case XED_ICLASS_VRNDSCALEPD: + case XED_ICLASS_VRNDSCALEPH: + case XED_ICLASS_VRNDSCALEPS: + case XED_ICLASS_VRNDSCALESD: + case XED_ICLASS_VRNDSCALESH: + case XED_ICLASS_VRNDSCALESS: + case XED_ICLASS_VROUNDPD: + case XED_ICLASS_VROUNDPS: + case XED_ICLASS_VROUNDSD: + case XED_ICLASS_VROUNDSS: + case XED_ICLASS_VRSQRT14PD: + case XED_ICLASS_VRSQRT14PS: + case XED_ICLASS_VRSQRT14SD: + case XED_ICLASS_VRSQRT14SS: + case XED_ICLASS_VRSQRT28PD: + case XED_ICLASS_VRSQRT28PS: + case XED_ICLASS_VRSQRT28SD: + case XED_ICLASS_VRSQRT28SS: + case XED_ICLASS_VRSQRTPH: + case XED_ICLASS_VRSQRTPS: + case XED_ICLASS_VRSQRTSH: + case XED_ICLASS_VRSQRTSS: + case XED_ICLASS_VSCALEFPD: + case XED_ICLASS_VSCALEFPH: + case XED_ICLASS_VSCALEFPS: + case XED_ICLASS_VSCALEFSD: + case XED_ICLASS_VSCALEFSH: + case XED_ICLASS_VSCALEFSS: + case XED_ICLASS_VSCATTERDPD: + case XED_ICLASS_VSCATTERDPS: + case XED_ICLASS_VSCATTERPF0DPD: + case XED_ICLASS_VSCATTERPF0DPS: + case XED_ICLASS_VSCATTERPF0QPD: + case XED_ICLASS_VSCATTERPF0QPS: + case XED_ICLASS_VSCATTERPF1DPD: + case XED_ICLASS_VSCATTERPF1DPS: + case XED_ICLASS_VSCATTERPF1QPD: + case XED_ICLASS_VSCATTERPF1QPS: + case XED_ICLASS_VSCATTERQPD: + case XED_ICLASS_VSCATTERQPS: + case XED_ICLASS_VSHUFF32X4: + case XED_ICLASS_VSHUFF64X2: + case XED_ICLASS_VSHUFI32X4: + case XED_ICLASS_VSHUFI64X2: + case XED_ICLASS_VSHUFPD: + case XED_ICLASS_VSHUFPS: + case XED_ICLASS_VSQRTPD: + case XED_ICLASS_VSQRTPH: + case XED_ICLASS_VSQRTPS: + case XED_ICLASS_VSQRTSD: + case XED_ICLASS_VSQRTSH: + case XED_ICLASS_VSQRTSS: + case XED_ICLASS_VSTMXCSR: + case XED_ICLASS_VSUBPD: + case XED_ICLASS_VSUBPH: + case XED_ICLASS_VSUBPS: + case XED_ICLASS_VSUBSD: + case XED_ICLASS_VSUBSH: + case XED_ICLASS_VSUBSS: + case XED_ICLASS_VTESTPD: + case XED_ICLASS_VTESTPS: + case XED_ICLASS_VUCOMISD: + case XED_ICLASS_VUCOMISH: + case XED_ICLASS_VUCOMISS: + case XED_ICLASS_VUNPCKHPD: + case XED_ICLASS_VUNPCKHPS: + case XED_ICLASS_VUNPCKLPD: + case XED_ICLASS_VUNPCKLPS: + case XED_ICLASS_VXORPD: + case XED_ICLASS_VXORPS: + case XED_ICLASS_VZEROALL: + case XED_ICLASS_VZEROUPPER: + case XED_ICLASS_WBINVD: + case XED_ICLASS_WBNOINVD: + case XED_ICLASS_WRFSBASE: + case XED_ICLASS_WRGSBASE: + case XED_ICLASS_WRMSR: + case XED_ICLASS_WRPKRU: + case XED_ICLASS_WRSSD: + case XED_ICLASS_WRSSQ: + case XED_ICLASS_WRUSSD: + case XED_ICLASS_WRUSSQ: + case XED_ICLASS_XABORT: + case XED_ICLASS_XADD: + case XED_ICLASS_XADD_LOCK: + case XED_ICLASS_XBEGIN: + case XED_ICLASS_XCHG: + case XED_ICLASS_XEND: + case XED_ICLASS_XGETBV: + case XED_ICLASS_XLAT: + case XED_ICLASS_XOR: + case XED_ICLASS_XORPD: + case XED_ICLASS_XORPS: + case XED_ICLASS_XOR_LOCK: + case XED_ICLASS_XRESLDTRK: + case XED_ICLASS_XRSTOR: + case XED_ICLASS_XRSTOR64: + case XED_ICLASS_XRSTORS: + case XED_ICLASS_XRSTORS64: + case XED_ICLASS_XSAVE: + case XED_ICLASS_XSAVE64: + case XED_ICLASS_XSAVEC: + case XED_ICLASS_XSAVEC64: + case XED_ICLASS_XSAVEOPT: + case XED_ICLASS_XSAVEOPT64: + case XED_ICLASS_XSAVES: + case XED_ICLASS_XSAVES64: + case XED_ICLASS_XSETBV: + case XED_ICLASS_XSTORE: + case XED_ICLASS_XSUSLDTRK: + case XED_ICLASS_XTEST: + case XED_ICLASS_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-iclass-enum.h b/CodeVirtualizer/build/obj/xed-iclass-enum.h new file mode 100644 index 0000000..f250429 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iclass-enum.h @@ -0,0 +1,3517 @@ +/// @file xed-iclass-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ICLASS_ENUM_H) +# define XED_ICLASS_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ICLASS_INVALID_DEFINED 1 +#define XED_ICLASS_AAA_DEFINED 1 +#define XED_ICLASS_AAD_DEFINED 1 +#define XED_ICLASS_AAM_DEFINED 1 +#define XED_ICLASS_AAS_DEFINED 1 +#define XED_ICLASS_ADC_DEFINED 1 +#define XED_ICLASS_ADCX_DEFINED 1 +#define XED_ICLASS_ADC_LOCK_DEFINED 1 +#define XED_ICLASS_ADD_DEFINED 1 +#define XED_ICLASS_ADDPD_DEFINED 1 +#define XED_ICLASS_ADDPS_DEFINED 1 +#define XED_ICLASS_ADDSD_DEFINED 1 +#define XED_ICLASS_ADDSS_DEFINED 1 +#define XED_ICLASS_ADDSUBPD_DEFINED 1 +#define XED_ICLASS_ADDSUBPS_DEFINED 1 +#define XED_ICLASS_ADD_LOCK_DEFINED 1 +#define XED_ICLASS_ADOX_DEFINED 1 +#define XED_ICLASS_AESDEC_DEFINED 1 +#define XED_ICLASS_AESDEC128KL_DEFINED 1 +#define XED_ICLASS_AESDEC256KL_DEFINED 1 +#define XED_ICLASS_AESDECLAST_DEFINED 1 +#define XED_ICLASS_AESDECWIDE128KL_DEFINED 1 +#define XED_ICLASS_AESDECWIDE256KL_DEFINED 1 +#define XED_ICLASS_AESENC_DEFINED 1 +#define XED_ICLASS_AESENC128KL_DEFINED 1 +#define XED_ICLASS_AESENC256KL_DEFINED 1 +#define XED_ICLASS_AESENCLAST_DEFINED 1 +#define XED_ICLASS_AESENCWIDE128KL_DEFINED 1 +#define XED_ICLASS_AESENCWIDE256KL_DEFINED 1 +#define XED_ICLASS_AESIMC_DEFINED 1 +#define XED_ICLASS_AESKEYGENASSIST_DEFINED 1 +#define XED_ICLASS_AND_DEFINED 1 +#define XED_ICLASS_ANDN_DEFINED 1 +#define XED_ICLASS_ANDNPD_DEFINED 1 +#define XED_ICLASS_ANDNPS_DEFINED 1 +#define XED_ICLASS_ANDPD_DEFINED 1 +#define XED_ICLASS_ANDPS_DEFINED 1 +#define XED_ICLASS_AND_LOCK_DEFINED 1 +#define XED_ICLASS_ARPL_DEFINED 1 +#define XED_ICLASS_BEXTR_DEFINED 1 +#define XED_ICLASS_BEXTR_XOP_DEFINED 1 +#define XED_ICLASS_BLCFILL_DEFINED 1 +#define XED_ICLASS_BLCI_DEFINED 1 +#define XED_ICLASS_BLCIC_DEFINED 1 +#define XED_ICLASS_BLCMSK_DEFINED 1 +#define XED_ICLASS_BLCS_DEFINED 1 +#define XED_ICLASS_BLENDPD_DEFINED 1 +#define XED_ICLASS_BLENDPS_DEFINED 1 +#define XED_ICLASS_BLENDVPD_DEFINED 1 +#define XED_ICLASS_BLENDVPS_DEFINED 1 +#define XED_ICLASS_BLSFILL_DEFINED 1 +#define XED_ICLASS_BLSI_DEFINED 1 +#define XED_ICLASS_BLSIC_DEFINED 1 +#define XED_ICLASS_BLSMSK_DEFINED 1 +#define XED_ICLASS_BLSR_DEFINED 1 +#define XED_ICLASS_BNDCL_DEFINED 1 +#define XED_ICLASS_BNDCN_DEFINED 1 +#define XED_ICLASS_BNDCU_DEFINED 1 +#define XED_ICLASS_BNDLDX_DEFINED 1 +#define XED_ICLASS_BNDMK_DEFINED 1 +#define XED_ICLASS_BNDMOV_DEFINED 1 +#define XED_ICLASS_BNDSTX_DEFINED 1 +#define XED_ICLASS_BOUND_DEFINED 1 +#define XED_ICLASS_BSF_DEFINED 1 +#define XED_ICLASS_BSR_DEFINED 1 +#define XED_ICLASS_BSWAP_DEFINED 1 +#define XED_ICLASS_BT_DEFINED 1 +#define XED_ICLASS_BTC_DEFINED 1 +#define XED_ICLASS_BTC_LOCK_DEFINED 1 +#define XED_ICLASS_BTR_DEFINED 1 +#define XED_ICLASS_BTR_LOCK_DEFINED 1 +#define XED_ICLASS_BTS_DEFINED 1 +#define XED_ICLASS_BTS_LOCK_DEFINED 1 +#define XED_ICLASS_BZHI_DEFINED 1 +#define XED_ICLASS_CALL_FAR_DEFINED 1 +#define XED_ICLASS_CALL_NEAR_DEFINED 1 +#define XED_ICLASS_CBW_DEFINED 1 +#define XED_ICLASS_CDQ_DEFINED 1 +#define XED_ICLASS_CDQE_DEFINED 1 +#define XED_ICLASS_CLAC_DEFINED 1 +#define XED_ICLASS_CLC_DEFINED 1 +#define XED_ICLASS_CLD_DEFINED 1 +#define XED_ICLASS_CLDEMOTE_DEFINED 1 +#define XED_ICLASS_CLFLUSH_DEFINED 1 +#define XED_ICLASS_CLFLUSHOPT_DEFINED 1 +#define XED_ICLASS_CLGI_DEFINED 1 +#define XED_ICLASS_CLI_DEFINED 1 +#define XED_ICLASS_CLRSSBSY_DEFINED 1 +#define XED_ICLASS_CLTS_DEFINED 1 +#define XED_ICLASS_CLUI_DEFINED 1 +#define XED_ICLASS_CLWB_DEFINED 1 +#define XED_ICLASS_CLZERO_DEFINED 1 +#define XED_ICLASS_CMC_DEFINED 1 +#define XED_ICLASS_CMOVB_DEFINED 1 +#define XED_ICLASS_CMOVBE_DEFINED 1 +#define XED_ICLASS_CMOVL_DEFINED 1 +#define XED_ICLASS_CMOVLE_DEFINED 1 +#define XED_ICLASS_CMOVNB_DEFINED 1 +#define XED_ICLASS_CMOVNBE_DEFINED 1 +#define XED_ICLASS_CMOVNL_DEFINED 1 +#define XED_ICLASS_CMOVNLE_DEFINED 1 +#define XED_ICLASS_CMOVNO_DEFINED 1 +#define XED_ICLASS_CMOVNP_DEFINED 1 +#define XED_ICLASS_CMOVNS_DEFINED 1 +#define XED_ICLASS_CMOVNZ_DEFINED 1 +#define XED_ICLASS_CMOVO_DEFINED 1 +#define XED_ICLASS_CMOVP_DEFINED 1 +#define XED_ICLASS_CMOVS_DEFINED 1 +#define XED_ICLASS_CMOVZ_DEFINED 1 +#define XED_ICLASS_CMP_DEFINED 1 +#define XED_ICLASS_CMPPD_DEFINED 1 +#define XED_ICLASS_CMPPS_DEFINED 1 +#define XED_ICLASS_CMPSB_DEFINED 1 +#define XED_ICLASS_CMPSD_DEFINED 1 +#define XED_ICLASS_CMPSD_XMM_DEFINED 1 +#define XED_ICLASS_CMPSQ_DEFINED 1 +#define XED_ICLASS_CMPSS_DEFINED 1 +#define XED_ICLASS_CMPSW_DEFINED 1 +#define XED_ICLASS_CMPXCHG_DEFINED 1 +#define XED_ICLASS_CMPXCHG16B_DEFINED 1 +#define XED_ICLASS_CMPXCHG16B_LOCK_DEFINED 1 +#define XED_ICLASS_CMPXCHG8B_DEFINED 1 +#define XED_ICLASS_CMPXCHG8B_LOCK_DEFINED 1 +#define XED_ICLASS_CMPXCHG_LOCK_DEFINED 1 +#define XED_ICLASS_COMISD_DEFINED 1 +#define XED_ICLASS_COMISS_DEFINED 1 +#define XED_ICLASS_CPUID_DEFINED 1 +#define XED_ICLASS_CQO_DEFINED 1 +#define XED_ICLASS_CRC32_DEFINED 1 +#define XED_ICLASS_CVTDQ2PD_DEFINED 1 +#define XED_ICLASS_CVTDQ2PS_DEFINED 1 +#define XED_ICLASS_CVTPD2DQ_DEFINED 1 +#define XED_ICLASS_CVTPD2PI_DEFINED 1 +#define XED_ICLASS_CVTPD2PS_DEFINED 1 +#define XED_ICLASS_CVTPI2PD_DEFINED 1 +#define XED_ICLASS_CVTPI2PS_DEFINED 1 +#define XED_ICLASS_CVTPS2DQ_DEFINED 1 +#define XED_ICLASS_CVTPS2PD_DEFINED 1 +#define XED_ICLASS_CVTPS2PI_DEFINED 1 +#define XED_ICLASS_CVTSD2SI_DEFINED 1 +#define XED_ICLASS_CVTSD2SS_DEFINED 1 +#define XED_ICLASS_CVTSI2SD_DEFINED 1 +#define XED_ICLASS_CVTSI2SS_DEFINED 1 +#define XED_ICLASS_CVTSS2SD_DEFINED 1 +#define XED_ICLASS_CVTSS2SI_DEFINED 1 +#define XED_ICLASS_CVTTPD2DQ_DEFINED 1 +#define XED_ICLASS_CVTTPD2PI_DEFINED 1 +#define XED_ICLASS_CVTTPS2DQ_DEFINED 1 +#define XED_ICLASS_CVTTPS2PI_DEFINED 1 +#define XED_ICLASS_CVTTSD2SI_DEFINED 1 +#define XED_ICLASS_CVTTSS2SI_DEFINED 1 +#define XED_ICLASS_CWD_DEFINED 1 +#define XED_ICLASS_CWDE_DEFINED 1 +#define XED_ICLASS_DAA_DEFINED 1 +#define XED_ICLASS_DAS_DEFINED 1 +#define XED_ICLASS_DEC_DEFINED 1 +#define XED_ICLASS_DEC_LOCK_DEFINED 1 +#define XED_ICLASS_DIV_DEFINED 1 +#define XED_ICLASS_DIVPD_DEFINED 1 +#define XED_ICLASS_DIVPS_DEFINED 1 +#define XED_ICLASS_DIVSD_DEFINED 1 +#define XED_ICLASS_DIVSS_DEFINED 1 +#define XED_ICLASS_DPPD_DEFINED 1 +#define XED_ICLASS_DPPS_DEFINED 1 +#define XED_ICLASS_EMMS_DEFINED 1 +#define XED_ICLASS_ENCLS_DEFINED 1 +#define XED_ICLASS_ENCLU_DEFINED 1 +#define XED_ICLASS_ENCLV_DEFINED 1 +#define XED_ICLASS_ENCODEKEY128_DEFINED 1 +#define XED_ICLASS_ENCODEKEY256_DEFINED 1 +#define XED_ICLASS_ENDBR32_DEFINED 1 +#define XED_ICLASS_ENDBR64_DEFINED 1 +#define XED_ICLASS_ENQCMD_DEFINED 1 +#define XED_ICLASS_ENQCMDS_DEFINED 1 +#define XED_ICLASS_ENTER_DEFINED 1 +#define XED_ICLASS_EXTRACTPS_DEFINED 1 +#define XED_ICLASS_EXTRQ_DEFINED 1 +#define XED_ICLASS_F2XM1_DEFINED 1 +#define XED_ICLASS_FABS_DEFINED 1 +#define XED_ICLASS_FADD_DEFINED 1 +#define XED_ICLASS_FADDP_DEFINED 1 +#define XED_ICLASS_FBLD_DEFINED 1 +#define XED_ICLASS_FBSTP_DEFINED 1 +#define XED_ICLASS_FCHS_DEFINED 1 +#define XED_ICLASS_FCMOVB_DEFINED 1 +#define XED_ICLASS_FCMOVBE_DEFINED 1 +#define XED_ICLASS_FCMOVE_DEFINED 1 +#define XED_ICLASS_FCMOVNB_DEFINED 1 +#define XED_ICLASS_FCMOVNBE_DEFINED 1 +#define XED_ICLASS_FCMOVNE_DEFINED 1 +#define XED_ICLASS_FCMOVNU_DEFINED 1 +#define XED_ICLASS_FCMOVU_DEFINED 1 +#define XED_ICLASS_FCOM_DEFINED 1 +#define XED_ICLASS_FCOMI_DEFINED 1 +#define XED_ICLASS_FCOMIP_DEFINED 1 +#define XED_ICLASS_FCOMP_DEFINED 1 +#define XED_ICLASS_FCOMPP_DEFINED 1 +#define XED_ICLASS_FCOS_DEFINED 1 +#define XED_ICLASS_FDECSTP_DEFINED 1 +#define XED_ICLASS_FDISI8087_NOP_DEFINED 1 +#define XED_ICLASS_FDIV_DEFINED 1 +#define XED_ICLASS_FDIVP_DEFINED 1 +#define XED_ICLASS_FDIVR_DEFINED 1 +#define XED_ICLASS_FDIVRP_DEFINED 1 +#define XED_ICLASS_FEMMS_DEFINED 1 +#define XED_ICLASS_FENI8087_NOP_DEFINED 1 +#define XED_ICLASS_FFREE_DEFINED 1 +#define XED_ICLASS_FFREEP_DEFINED 1 +#define XED_ICLASS_FIADD_DEFINED 1 +#define XED_ICLASS_FICOM_DEFINED 1 +#define XED_ICLASS_FICOMP_DEFINED 1 +#define XED_ICLASS_FIDIV_DEFINED 1 +#define XED_ICLASS_FIDIVR_DEFINED 1 +#define XED_ICLASS_FILD_DEFINED 1 +#define XED_ICLASS_FIMUL_DEFINED 1 +#define XED_ICLASS_FINCSTP_DEFINED 1 +#define XED_ICLASS_FIST_DEFINED 1 +#define XED_ICLASS_FISTP_DEFINED 1 +#define XED_ICLASS_FISTTP_DEFINED 1 +#define XED_ICLASS_FISUB_DEFINED 1 +#define XED_ICLASS_FISUBR_DEFINED 1 +#define XED_ICLASS_FLD_DEFINED 1 +#define XED_ICLASS_FLD1_DEFINED 1 +#define XED_ICLASS_FLDCW_DEFINED 1 +#define XED_ICLASS_FLDENV_DEFINED 1 +#define XED_ICLASS_FLDL2E_DEFINED 1 +#define XED_ICLASS_FLDL2T_DEFINED 1 +#define XED_ICLASS_FLDLG2_DEFINED 1 +#define XED_ICLASS_FLDLN2_DEFINED 1 +#define XED_ICLASS_FLDPI_DEFINED 1 +#define XED_ICLASS_FLDZ_DEFINED 1 +#define XED_ICLASS_FMUL_DEFINED 1 +#define XED_ICLASS_FMULP_DEFINED 1 +#define XED_ICLASS_FNCLEX_DEFINED 1 +#define XED_ICLASS_FNINIT_DEFINED 1 +#define XED_ICLASS_FNOP_DEFINED 1 +#define XED_ICLASS_FNSAVE_DEFINED 1 +#define XED_ICLASS_FNSTCW_DEFINED 1 +#define XED_ICLASS_FNSTENV_DEFINED 1 +#define XED_ICLASS_FNSTSW_DEFINED 1 +#define XED_ICLASS_FPATAN_DEFINED 1 +#define XED_ICLASS_FPREM_DEFINED 1 +#define XED_ICLASS_FPREM1_DEFINED 1 +#define XED_ICLASS_FPTAN_DEFINED 1 +#define XED_ICLASS_FRNDINT_DEFINED 1 +#define XED_ICLASS_FRSTOR_DEFINED 1 +#define XED_ICLASS_FSCALE_DEFINED 1 +#define XED_ICLASS_FSETPM287_NOP_DEFINED 1 +#define XED_ICLASS_FSIN_DEFINED 1 +#define XED_ICLASS_FSINCOS_DEFINED 1 +#define XED_ICLASS_FSQRT_DEFINED 1 +#define XED_ICLASS_FST_DEFINED 1 +#define XED_ICLASS_FSTP_DEFINED 1 +#define XED_ICLASS_FSTPNCE_DEFINED 1 +#define XED_ICLASS_FSUB_DEFINED 1 +#define XED_ICLASS_FSUBP_DEFINED 1 +#define XED_ICLASS_FSUBR_DEFINED 1 +#define XED_ICLASS_FSUBRP_DEFINED 1 +#define XED_ICLASS_FTST_DEFINED 1 +#define XED_ICLASS_FUCOM_DEFINED 1 +#define XED_ICLASS_FUCOMI_DEFINED 1 +#define XED_ICLASS_FUCOMIP_DEFINED 1 +#define XED_ICLASS_FUCOMP_DEFINED 1 +#define XED_ICLASS_FUCOMPP_DEFINED 1 +#define XED_ICLASS_FWAIT_DEFINED 1 +#define XED_ICLASS_FXAM_DEFINED 1 +#define XED_ICLASS_FXCH_DEFINED 1 +#define XED_ICLASS_FXRSTOR_DEFINED 1 +#define XED_ICLASS_FXRSTOR64_DEFINED 1 +#define XED_ICLASS_FXSAVE_DEFINED 1 +#define XED_ICLASS_FXSAVE64_DEFINED 1 +#define XED_ICLASS_FXTRACT_DEFINED 1 +#define XED_ICLASS_FYL2X_DEFINED 1 +#define XED_ICLASS_FYL2XP1_DEFINED 1 +#define XED_ICLASS_GETSEC_DEFINED 1 +#define XED_ICLASS_GF2P8AFFINEINVQB_DEFINED 1 +#define XED_ICLASS_GF2P8AFFINEQB_DEFINED 1 +#define XED_ICLASS_GF2P8MULB_DEFINED 1 +#define XED_ICLASS_HADDPD_DEFINED 1 +#define XED_ICLASS_HADDPS_DEFINED 1 +#define XED_ICLASS_HLT_DEFINED 1 +#define XED_ICLASS_HRESET_DEFINED 1 +#define XED_ICLASS_HSUBPD_DEFINED 1 +#define XED_ICLASS_HSUBPS_DEFINED 1 +#define XED_ICLASS_IDIV_DEFINED 1 +#define XED_ICLASS_IMUL_DEFINED 1 +#define XED_ICLASS_IN_DEFINED 1 +#define XED_ICLASS_INC_DEFINED 1 +#define XED_ICLASS_INCSSPD_DEFINED 1 +#define XED_ICLASS_INCSSPQ_DEFINED 1 +#define XED_ICLASS_INC_LOCK_DEFINED 1 +#define XED_ICLASS_INSB_DEFINED 1 +#define XED_ICLASS_INSD_DEFINED 1 +#define XED_ICLASS_INSERTPS_DEFINED 1 +#define XED_ICLASS_INSERTQ_DEFINED 1 +#define XED_ICLASS_INSW_DEFINED 1 +#define XED_ICLASS_INT_DEFINED 1 +#define XED_ICLASS_INT1_DEFINED 1 +#define XED_ICLASS_INT3_DEFINED 1 +#define XED_ICLASS_INTO_DEFINED 1 +#define XED_ICLASS_INVD_DEFINED 1 +#define XED_ICLASS_INVEPT_DEFINED 1 +#define XED_ICLASS_INVLPG_DEFINED 1 +#define XED_ICLASS_INVLPGA_DEFINED 1 +#define XED_ICLASS_INVLPGB_DEFINED 1 +#define XED_ICLASS_INVPCID_DEFINED 1 +#define XED_ICLASS_INVVPID_DEFINED 1 +#define XED_ICLASS_IRET_DEFINED 1 +#define XED_ICLASS_IRETD_DEFINED 1 +#define XED_ICLASS_IRETQ_DEFINED 1 +#define XED_ICLASS_JB_DEFINED 1 +#define XED_ICLASS_JBE_DEFINED 1 +#define XED_ICLASS_JCXZ_DEFINED 1 +#define XED_ICLASS_JECXZ_DEFINED 1 +#define XED_ICLASS_JL_DEFINED 1 +#define XED_ICLASS_JLE_DEFINED 1 +#define XED_ICLASS_JMP_DEFINED 1 +#define XED_ICLASS_JMP_FAR_DEFINED 1 +#define XED_ICLASS_JNB_DEFINED 1 +#define XED_ICLASS_JNBE_DEFINED 1 +#define XED_ICLASS_JNL_DEFINED 1 +#define XED_ICLASS_JNLE_DEFINED 1 +#define XED_ICLASS_JNO_DEFINED 1 +#define XED_ICLASS_JNP_DEFINED 1 +#define XED_ICLASS_JNS_DEFINED 1 +#define XED_ICLASS_JNZ_DEFINED 1 +#define XED_ICLASS_JO_DEFINED 1 +#define XED_ICLASS_JP_DEFINED 1 +#define XED_ICLASS_JRCXZ_DEFINED 1 +#define XED_ICLASS_JS_DEFINED 1 +#define XED_ICLASS_JZ_DEFINED 1 +#define XED_ICLASS_KADDB_DEFINED 1 +#define XED_ICLASS_KADDD_DEFINED 1 +#define XED_ICLASS_KADDQ_DEFINED 1 +#define XED_ICLASS_KADDW_DEFINED 1 +#define XED_ICLASS_KANDB_DEFINED 1 +#define XED_ICLASS_KANDD_DEFINED 1 +#define XED_ICLASS_KANDNB_DEFINED 1 +#define XED_ICLASS_KANDND_DEFINED 1 +#define XED_ICLASS_KANDNQ_DEFINED 1 +#define XED_ICLASS_KANDNW_DEFINED 1 +#define XED_ICLASS_KANDQ_DEFINED 1 +#define XED_ICLASS_KANDW_DEFINED 1 +#define XED_ICLASS_KMOVB_DEFINED 1 +#define XED_ICLASS_KMOVD_DEFINED 1 +#define XED_ICLASS_KMOVQ_DEFINED 1 +#define XED_ICLASS_KMOVW_DEFINED 1 +#define XED_ICLASS_KNOTB_DEFINED 1 +#define XED_ICLASS_KNOTD_DEFINED 1 +#define XED_ICLASS_KNOTQ_DEFINED 1 +#define XED_ICLASS_KNOTW_DEFINED 1 +#define XED_ICLASS_KORB_DEFINED 1 +#define XED_ICLASS_KORD_DEFINED 1 +#define XED_ICLASS_KORQ_DEFINED 1 +#define XED_ICLASS_KORTESTB_DEFINED 1 +#define XED_ICLASS_KORTESTD_DEFINED 1 +#define XED_ICLASS_KORTESTQ_DEFINED 1 +#define XED_ICLASS_KORTESTW_DEFINED 1 +#define XED_ICLASS_KORW_DEFINED 1 +#define XED_ICLASS_KSHIFTLB_DEFINED 1 +#define XED_ICLASS_KSHIFTLD_DEFINED 1 +#define XED_ICLASS_KSHIFTLQ_DEFINED 1 +#define XED_ICLASS_KSHIFTLW_DEFINED 1 +#define XED_ICLASS_KSHIFTRB_DEFINED 1 +#define XED_ICLASS_KSHIFTRD_DEFINED 1 +#define XED_ICLASS_KSHIFTRQ_DEFINED 1 +#define XED_ICLASS_KSHIFTRW_DEFINED 1 +#define XED_ICLASS_KTESTB_DEFINED 1 +#define XED_ICLASS_KTESTD_DEFINED 1 +#define XED_ICLASS_KTESTQ_DEFINED 1 +#define XED_ICLASS_KTESTW_DEFINED 1 +#define XED_ICLASS_KUNPCKBW_DEFINED 1 +#define XED_ICLASS_KUNPCKDQ_DEFINED 1 +#define XED_ICLASS_KUNPCKWD_DEFINED 1 +#define XED_ICLASS_KXNORB_DEFINED 1 +#define XED_ICLASS_KXNORD_DEFINED 1 +#define XED_ICLASS_KXNORQ_DEFINED 1 +#define XED_ICLASS_KXNORW_DEFINED 1 +#define XED_ICLASS_KXORB_DEFINED 1 +#define XED_ICLASS_KXORD_DEFINED 1 +#define XED_ICLASS_KXORQ_DEFINED 1 +#define XED_ICLASS_KXORW_DEFINED 1 +#define XED_ICLASS_LAHF_DEFINED 1 +#define XED_ICLASS_LAR_DEFINED 1 +#define XED_ICLASS_LDDQU_DEFINED 1 +#define XED_ICLASS_LDMXCSR_DEFINED 1 +#define XED_ICLASS_LDS_DEFINED 1 +#define XED_ICLASS_LDTILECFG_DEFINED 1 +#define XED_ICLASS_LEA_DEFINED 1 +#define XED_ICLASS_LEAVE_DEFINED 1 +#define XED_ICLASS_LES_DEFINED 1 +#define XED_ICLASS_LFENCE_DEFINED 1 +#define XED_ICLASS_LFS_DEFINED 1 +#define XED_ICLASS_LGDT_DEFINED 1 +#define XED_ICLASS_LGS_DEFINED 1 +#define XED_ICLASS_LIDT_DEFINED 1 +#define XED_ICLASS_LLDT_DEFINED 1 +#define XED_ICLASS_LLWPCB_DEFINED 1 +#define XED_ICLASS_LMSW_DEFINED 1 +#define XED_ICLASS_LOADIWKEY_DEFINED 1 +#define XED_ICLASS_LODSB_DEFINED 1 +#define XED_ICLASS_LODSD_DEFINED 1 +#define XED_ICLASS_LODSQ_DEFINED 1 +#define XED_ICLASS_LODSW_DEFINED 1 +#define XED_ICLASS_LOOP_DEFINED 1 +#define XED_ICLASS_LOOPE_DEFINED 1 +#define XED_ICLASS_LOOPNE_DEFINED 1 +#define XED_ICLASS_LSL_DEFINED 1 +#define XED_ICLASS_LSS_DEFINED 1 +#define XED_ICLASS_LTR_DEFINED 1 +#define XED_ICLASS_LWPINS_DEFINED 1 +#define XED_ICLASS_LWPVAL_DEFINED 1 +#define XED_ICLASS_LZCNT_DEFINED 1 +#define XED_ICLASS_MASKMOVDQU_DEFINED 1 +#define XED_ICLASS_MASKMOVQ_DEFINED 1 +#define XED_ICLASS_MAXPD_DEFINED 1 +#define XED_ICLASS_MAXPS_DEFINED 1 +#define XED_ICLASS_MAXSD_DEFINED 1 +#define XED_ICLASS_MAXSS_DEFINED 1 +#define XED_ICLASS_MCOMMIT_DEFINED 1 +#define XED_ICLASS_MFENCE_DEFINED 1 +#define XED_ICLASS_MINPD_DEFINED 1 +#define XED_ICLASS_MINPS_DEFINED 1 +#define XED_ICLASS_MINSD_DEFINED 1 +#define XED_ICLASS_MINSS_DEFINED 1 +#define XED_ICLASS_MONITOR_DEFINED 1 +#define XED_ICLASS_MONITORX_DEFINED 1 +#define XED_ICLASS_MOV_DEFINED 1 +#define XED_ICLASS_MOVAPD_DEFINED 1 +#define XED_ICLASS_MOVAPS_DEFINED 1 +#define XED_ICLASS_MOVBE_DEFINED 1 +#define XED_ICLASS_MOVD_DEFINED 1 +#define XED_ICLASS_MOVDDUP_DEFINED 1 +#define XED_ICLASS_MOVDIR64B_DEFINED 1 +#define XED_ICLASS_MOVDIRI_DEFINED 1 +#define XED_ICLASS_MOVDQ2Q_DEFINED 1 +#define XED_ICLASS_MOVDQA_DEFINED 1 +#define XED_ICLASS_MOVDQU_DEFINED 1 +#define XED_ICLASS_MOVHLPS_DEFINED 1 +#define XED_ICLASS_MOVHPD_DEFINED 1 +#define XED_ICLASS_MOVHPS_DEFINED 1 +#define XED_ICLASS_MOVLHPS_DEFINED 1 +#define XED_ICLASS_MOVLPD_DEFINED 1 +#define XED_ICLASS_MOVLPS_DEFINED 1 +#define XED_ICLASS_MOVMSKPD_DEFINED 1 +#define XED_ICLASS_MOVMSKPS_DEFINED 1 +#define XED_ICLASS_MOVNTDQ_DEFINED 1 +#define XED_ICLASS_MOVNTDQA_DEFINED 1 +#define XED_ICLASS_MOVNTI_DEFINED 1 +#define XED_ICLASS_MOVNTPD_DEFINED 1 +#define XED_ICLASS_MOVNTPS_DEFINED 1 +#define XED_ICLASS_MOVNTQ_DEFINED 1 +#define XED_ICLASS_MOVNTSD_DEFINED 1 +#define XED_ICLASS_MOVNTSS_DEFINED 1 +#define XED_ICLASS_MOVQ_DEFINED 1 +#define XED_ICLASS_MOVQ2DQ_DEFINED 1 +#define XED_ICLASS_MOVSB_DEFINED 1 +#define XED_ICLASS_MOVSD_DEFINED 1 +#define XED_ICLASS_MOVSD_XMM_DEFINED 1 +#define XED_ICLASS_MOVSHDUP_DEFINED 1 +#define XED_ICLASS_MOVSLDUP_DEFINED 1 +#define XED_ICLASS_MOVSQ_DEFINED 1 +#define XED_ICLASS_MOVSS_DEFINED 1 +#define XED_ICLASS_MOVSW_DEFINED 1 +#define XED_ICLASS_MOVSX_DEFINED 1 +#define XED_ICLASS_MOVSXD_DEFINED 1 +#define XED_ICLASS_MOVUPD_DEFINED 1 +#define XED_ICLASS_MOVUPS_DEFINED 1 +#define XED_ICLASS_MOVZX_DEFINED 1 +#define XED_ICLASS_MOV_CR_DEFINED 1 +#define XED_ICLASS_MOV_DR_DEFINED 1 +#define XED_ICLASS_MPSADBW_DEFINED 1 +#define XED_ICLASS_MUL_DEFINED 1 +#define XED_ICLASS_MULPD_DEFINED 1 +#define XED_ICLASS_MULPS_DEFINED 1 +#define XED_ICLASS_MULSD_DEFINED 1 +#define XED_ICLASS_MULSS_DEFINED 1 +#define XED_ICLASS_MULX_DEFINED 1 +#define XED_ICLASS_MWAIT_DEFINED 1 +#define XED_ICLASS_MWAITX_DEFINED 1 +#define XED_ICLASS_NEG_DEFINED 1 +#define XED_ICLASS_NEG_LOCK_DEFINED 1 +#define XED_ICLASS_NOP_DEFINED 1 +#define XED_ICLASS_NOP2_DEFINED 1 +#define XED_ICLASS_NOP3_DEFINED 1 +#define XED_ICLASS_NOP4_DEFINED 1 +#define XED_ICLASS_NOP5_DEFINED 1 +#define XED_ICLASS_NOP6_DEFINED 1 +#define XED_ICLASS_NOP7_DEFINED 1 +#define XED_ICLASS_NOP8_DEFINED 1 +#define XED_ICLASS_NOP9_DEFINED 1 +#define XED_ICLASS_NOT_DEFINED 1 +#define XED_ICLASS_NOT_LOCK_DEFINED 1 +#define XED_ICLASS_OR_DEFINED 1 +#define XED_ICLASS_ORPD_DEFINED 1 +#define XED_ICLASS_ORPS_DEFINED 1 +#define XED_ICLASS_OR_LOCK_DEFINED 1 +#define XED_ICLASS_OUT_DEFINED 1 +#define XED_ICLASS_OUTSB_DEFINED 1 +#define XED_ICLASS_OUTSD_DEFINED 1 +#define XED_ICLASS_OUTSW_DEFINED 1 +#define XED_ICLASS_PABSB_DEFINED 1 +#define XED_ICLASS_PABSD_DEFINED 1 +#define XED_ICLASS_PABSW_DEFINED 1 +#define XED_ICLASS_PACKSSDW_DEFINED 1 +#define XED_ICLASS_PACKSSWB_DEFINED 1 +#define XED_ICLASS_PACKUSDW_DEFINED 1 +#define XED_ICLASS_PACKUSWB_DEFINED 1 +#define XED_ICLASS_PADDB_DEFINED 1 +#define XED_ICLASS_PADDD_DEFINED 1 +#define XED_ICLASS_PADDQ_DEFINED 1 +#define XED_ICLASS_PADDSB_DEFINED 1 +#define XED_ICLASS_PADDSW_DEFINED 1 +#define XED_ICLASS_PADDUSB_DEFINED 1 +#define XED_ICLASS_PADDUSW_DEFINED 1 +#define XED_ICLASS_PADDW_DEFINED 1 +#define XED_ICLASS_PALIGNR_DEFINED 1 +#define XED_ICLASS_PAND_DEFINED 1 +#define XED_ICLASS_PANDN_DEFINED 1 +#define XED_ICLASS_PAUSE_DEFINED 1 +#define XED_ICLASS_PAVGB_DEFINED 1 +#define XED_ICLASS_PAVGUSB_DEFINED 1 +#define XED_ICLASS_PAVGW_DEFINED 1 +#define XED_ICLASS_PBLENDVB_DEFINED 1 +#define XED_ICLASS_PBLENDW_DEFINED 1 +#define XED_ICLASS_PCLMULQDQ_DEFINED 1 +#define XED_ICLASS_PCMPEQB_DEFINED 1 +#define XED_ICLASS_PCMPEQD_DEFINED 1 +#define XED_ICLASS_PCMPEQQ_DEFINED 1 +#define XED_ICLASS_PCMPEQW_DEFINED 1 +#define XED_ICLASS_PCMPESTRI_DEFINED 1 +#define XED_ICLASS_PCMPESTRI64_DEFINED 1 +#define XED_ICLASS_PCMPESTRM_DEFINED 1 +#define XED_ICLASS_PCMPESTRM64_DEFINED 1 +#define XED_ICLASS_PCMPGTB_DEFINED 1 +#define XED_ICLASS_PCMPGTD_DEFINED 1 +#define XED_ICLASS_PCMPGTQ_DEFINED 1 +#define XED_ICLASS_PCMPGTW_DEFINED 1 +#define XED_ICLASS_PCMPISTRI_DEFINED 1 +#define XED_ICLASS_PCMPISTRI64_DEFINED 1 +#define XED_ICLASS_PCMPISTRM_DEFINED 1 +#define XED_ICLASS_PCONFIG_DEFINED 1 +#define XED_ICLASS_PDEP_DEFINED 1 +#define XED_ICLASS_PEXT_DEFINED 1 +#define XED_ICLASS_PEXTRB_DEFINED 1 +#define XED_ICLASS_PEXTRD_DEFINED 1 +#define XED_ICLASS_PEXTRQ_DEFINED 1 +#define XED_ICLASS_PEXTRW_DEFINED 1 +#define XED_ICLASS_PEXTRW_SSE4_DEFINED 1 +#define XED_ICLASS_PF2ID_DEFINED 1 +#define XED_ICLASS_PF2IW_DEFINED 1 +#define XED_ICLASS_PFACC_DEFINED 1 +#define XED_ICLASS_PFADD_DEFINED 1 +#define XED_ICLASS_PFCMPEQ_DEFINED 1 +#define XED_ICLASS_PFCMPGE_DEFINED 1 +#define XED_ICLASS_PFCMPGT_DEFINED 1 +#define XED_ICLASS_PFMAX_DEFINED 1 +#define XED_ICLASS_PFMIN_DEFINED 1 +#define XED_ICLASS_PFMUL_DEFINED 1 +#define XED_ICLASS_PFNACC_DEFINED 1 +#define XED_ICLASS_PFPNACC_DEFINED 1 +#define XED_ICLASS_PFRCP_DEFINED 1 +#define XED_ICLASS_PFRCPIT1_DEFINED 1 +#define XED_ICLASS_PFRCPIT2_DEFINED 1 +#define XED_ICLASS_PFRSQIT1_DEFINED 1 +#define XED_ICLASS_PFRSQRT_DEFINED 1 +#define XED_ICLASS_PFSUB_DEFINED 1 +#define XED_ICLASS_PFSUBR_DEFINED 1 +#define XED_ICLASS_PHADDD_DEFINED 1 +#define XED_ICLASS_PHADDSW_DEFINED 1 +#define XED_ICLASS_PHADDW_DEFINED 1 +#define XED_ICLASS_PHMINPOSUW_DEFINED 1 +#define XED_ICLASS_PHSUBD_DEFINED 1 +#define XED_ICLASS_PHSUBSW_DEFINED 1 +#define XED_ICLASS_PHSUBW_DEFINED 1 +#define XED_ICLASS_PI2FD_DEFINED 1 +#define XED_ICLASS_PI2FW_DEFINED 1 +#define XED_ICLASS_PINSRB_DEFINED 1 +#define XED_ICLASS_PINSRD_DEFINED 1 +#define XED_ICLASS_PINSRQ_DEFINED 1 +#define XED_ICLASS_PINSRW_DEFINED 1 +#define XED_ICLASS_PMADDUBSW_DEFINED 1 +#define XED_ICLASS_PMADDWD_DEFINED 1 +#define XED_ICLASS_PMAXSB_DEFINED 1 +#define XED_ICLASS_PMAXSD_DEFINED 1 +#define XED_ICLASS_PMAXSW_DEFINED 1 +#define XED_ICLASS_PMAXUB_DEFINED 1 +#define XED_ICLASS_PMAXUD_DEFINED 1 +#define XED_ICLASS_PMAXUW_DEFINED 1 +#define XED_ICLASS_PMINSB_DEFINED 1 +#define XED_ICLASS_PMINSD_DEFINED 1 +#define XED_ICLASS_PMINSW_DEFINED 1 +#define XED_ICLASS_PMINUB_DEFINED 1 +#define XED_ICLASS_PMINUD_DEFINED 1 +#define XED_ICLASS_PMINUW_DEFINED 1 +#define XED_ICLASS_PMOVMSKB_DEFINED 1 +#define XED_ICLASS_PMOVSXBD_DEFINED 1 +#define XED_ICLASS_PMOVSXBQ_DEFINED 1 +#define XED_ICLASS_PMOVSXBW_DEFINED 1 +#define XED_ICLASS_PMOVSXDQ_DEFINED 1 +#define XED_ICLASS_PMOVSXWD_DEFINED 1 +#define XED_ICLASS_PMOVSXWQ_DEFINED 1 +#define XED_ICLASS_PMOVZXBD_DEFINED 1 +#define XED_ICLASS_PMOVZXBQ_DEFINED 1 +#define XED_ICLASS_PMOVZXBW_DEFINED 1 +#define XED_ICLASS_PMOVZXDQ_DEFINED 1 +#define XED_ICLASS_PMOVZXWD_DEFINED 1 +#define XED_ICLASS_PMOVZXWQ_DEFINED 1 +#define XED_ICLASS_PMULDQ_DEFINED 1 +#define XED_ICLASS_PMULHRSW_DEFINED 1 +#define XED_ICLASS_PMULHRW_DEFINED 1 +#define XED_ICLASS_PMULHUW_DEFINED 1 +#define XED_ICLASS_PMULHW_DEFINED 1 +#define XED_ICLASS_PMULLD_DEFINED 1 +#define XED_ICLASS_PMULLW_DEFINED 1 +#define XED_ICLASS_PMULUDQ_DEFINED 1 +#define XED_ICLASS_POP_DEFINED 1 +#define XED_ICLASS_POPA_DEFINED 1 +#define XED_ICLASS_POPAD_DEFINED 1 +#define XED_ICLASS_POPCNT_DEFINED 1 +#define XED_ICLASS_POPF_DEFINED 1 +#define XED_ICLASS_POPFD_DEFINED 1 +#define XED_ICLASS_POPFQ_DEFINED 1 +#define XED_ICLASS_POR_DEFINED 1 +#define XED_ICLASS_PREFETCHNTA_DEFINED 1 +#define XED_ICLASS_PREFETCHT0_DEFINED 1 +#define XED_ICLASS_PREFETCHT1_DEFINED 1 +#define XED_ICLASS_PREFETCHT2_DEFINED 1 +#define XED_ICLASS_PREFETCHW_DEFINED 1 +#define XED_ICLASS_PREFETCHWT1_DEFINED 1 +#define XED_ICLASS_PREFETCH_EXCLUSIVE_DEFINED 1 +#define XED_ICLASS_PREFETCH_RESERVED_DEFINED 1 +#define XED_ICLASS_PSADBW_DEFINED 1 +#define XED_ICLASS_PSHUFB_DEFINED 1 +#define XED_ICLASS_PSHUFD_DEFINED 1 +#define XED_ICLASS_PSHUFHW_DEFINED 1 +#define XED_ICLASS_PSHUFLW_DEFINED 1 +#define XED_ICLASS_PSHUFW_DEFINED 1 +#define XED_ICLASS_PSIGNB_DEFINED 1 +#define XED_ICLASS_PSIGND_DEFINED 1 +#define XED_ICLASS_PSIGNW_DEFINED 1 +#define XED_ICLASS_PSLLD_DEFINED 1 +#define XED_ICLASS_PSLLDQ_DEFINED 1 +#define XED_ICLASS_PSLLQ_DEFINED 1 +#define XED_ICLASS_PSLLW_DEFINED 1 +#define XED_ICLASS_PSMASH_DEFINED 1 +#define XED_ICLASS_PSRAD_DEFINED 1 +#define XED_ICLASS_PSRAW_DEFINED 1 +#define XED_ICLASS_PSRLD_DEFINED 1 +#define XED_ICLASS_PSRLDQ_DEFINED 1 +#define XED_ICLASS_PSRLQ_DEFINED 1 +#define XED_ICLASS_PSRLW_DEFINED 1 +#define XED_ICLASS_PSUBB_DEFINED 1 +#define XED_ICLASS_PSUBD_DEFINED 1 +#define XED_ICLASS_PSUBQ_DEFINED 1 +#define XED_ICLASS_PSUBSB_DEFINED 1 +#define XED_ICLASS_PSUBSW_DEFINED 1 +#define XED_ICLASS_PSUBUSB_DEFINED 1 +#define XED_ICLASS_PSUBUSW_DEFINED 1 +#define XED_ICLASS_PSUBW_DEFINED 1 +#define XED_ICLASS_PSWAPD_DEFINED 1 +#define XED_ICLASS_PTEST_DEFINED 1 +#define XED_ICLASS_PTWRITE_DEFINED 1 +#define XED_ICLASS_PUNPCKHBW_DEFINED 1 +#define XED_ICLASS_PUNPCKHDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKHQDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKHWD_DEFINED 1 +#define XED_ICLASS_PUNPCKLBW_DEFINED 1 +#define XED_ICLASS_PUNPCKLDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKLQDQ_DEFINED 1 +#define XED_ICLASS_PUNPCKLWD_DEFINED 1 +#define XED_ICLASS_PUSH_DEFINED 1 +#define XED_ICLASS_PUSHA_DEFINED 1 +#define XED_ICLASS_PUSHAD_DEFINED 1 +#define XED_ICLASS_PUSHF_DEFINED 1 +#define XED_ICLASS_PUSHFD_DEFINED 1 +#define XED_ICLASS_PUSHFQ_DEFINED 1 +#define XED_ICLASS_PVALIDATE_DEFINED 1 +#define XED_ICLASS_PXOR_DEFINED 1 +#define XED_ICLASS_RCL_DEFINED 1 +#define XED_ICLASS_RCPPS_DEFINED 1 +#define XED_ICLASS_RCPSS_DEFINED 1 +#define XED_ICLASS_RCR_DEFINED 1 +#define XED_ICLASS_RDFSBASE_DEFINED 1 +#define XED_ICLASS_RDGSBASE_DEFINED 1 +#define XED_ICLASS_RDMSR_DEFINED 1 +#define XED_ICLASS_RDPID_DEFINED 1 +#define XED_ICLASS_RDPKRU_DEFINED 1 +#define XED_ICLASS_RDPMC_DEFINED 1 +#define XED_ICLASS_RDPRU_DEFINED 1 +#define XED_ICLASS_RDRAND_DEFINED 1 +#define XED_ICLASS_RDSEED_DEFINED 1 +#define XED_ICLASS_RDSSPD_DEFINED 1 +#define XED_ICLASS_RDSSPQ_DEFINED 1 +#define XED_ICLASS_RDTSC_DEFINED 1 +#define XED_ICLASS_RDTSCP_DEFINED 1 +#define XED_ICLASS_REPE_CMPSB_DEFINED 1 +#define XED_ICLASS_REPE_CMPSD_DEFINED 1 +#define XED_ICLASS_REPE_CMPSQ_DEFINED 1 +#define XED_ICLASS_REPE_CMPSW_DEFINED 1 +#define XED_ICLASS_REPE_SCASB_DEFINED 1 +#define XED_ICLASS_REPE_SCASD_DEFINED 1 +#define XED_ICLASS_REPE_SCASQ_DEFINED 1 +#define XED_ICLASS_REPE_SCASW_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSB_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSD_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSQ_DEFINED 1 +#define XED_ICLASS_REPNE_CMPSW_DEFINED 1 +#define XED_ICLASS_REPNE_SCASB_DEFINED 1 +#define XED_ICLASS_REPNE_SCASD_DEFINED 1 +#define XED_ICLASS_REPNE_SCASQ_DEFINED 1 +#define XED_ICLASS_REPNE_SCASW_DEFINED 1 +#define XED_ICLASS_REP_INSB_DEFINED 1 +#define XED_ICLASS_REP_INSD_DEFINED 1 +#define XED_ICLASS_REP_INSW_DEFINED 1 +#define XED_ICLASS_REP_LODSB_DEFINED 1 +#define XED_ICLASS_REP_LODSD_DEFINED 1 +#define XED_ICLASS_REP_LODSQ_DEFINED 1 +#define XED_ICLASS_REP_LODSW_DEFINED 1 +#define XED_ICLASS_REP_MONTMUL_DEFINED 1 +#define XED_ICLASS_REP_MOVSB_DEFINED 1 +#define XED_ICLASS_REP_MOVSD_DEFINED 1 +#define XED_ICLASS_REP_MOVSQ_DEFINED 1 +#define XED_ICLASS_REP_MOVSW_DEFINED 1 +#define XED_ICLASS_REP_OUTSB_DEFINED 1 +#define XED_ICLASS_REP_OUTSD_DEFINED 1 +#define XED_ICLASS_REP_OUTSW_DEFINED 1 +#define XED_ICLASS_REP_STOSB_DEFINED 1 +#define XED_ICLASS_REP_STOSD_DEFINED 1 +#define XED_ICLASS_REP_STOSQ_DEFINED 1 +#define XED_ICLASS_REP_STOSW_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTCBC_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTCFB_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTCTR_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTECB_DEFINED 1 +#define XED_ICLASS_REP_XCRYPTOFB_DEFINED 1 +#define XED_ICLASS_REP_XSHA1_DEFINED 1 +#define XED_ICLASS_REP_XSHA256_DEFINED 1 +#define XED_ICLASS_REP_XSTORE_DEFINED 1 +#define XED_ICLASS_RET_FAR_DEFINED 1 +#define XED_ICLASS_RET_NEAR_DEFINED 1 +#define XED_ICLASS_RMPADJUST_DEFINED 1 +#define XED_ICLASS_RMPUPDATE_DEFINED 1 +#define XED_ICLASS_ROL_DEFINED 1 +#define XED_ICLASS_ROR_DEFINED 1 +#define XED_ICLASS_RORX_DEFINED 1 +#define XED_ICLASS_ROUNDPD_DEFINED 1 +#define XED_ICLASS_ROUNDPS_DEFINED 1 +#define XED_ICLASS_ROUNDSD_DEFINED 1 +#define XED_ICLASS_ROUNDSS_DEFINED 1 +#define XED_ICLASS_RSM_DEFINED 1 +#define XED_ICLASS_RSQRTPS_DEFINED 1 +#define XED_ICLASS_RSQRTSS_DEFINED 1 +#define XED_ICLASS_RSTORSSP_DEFINED 1 +#define XED_ICLASS_SAHF_DEFINED 1 +#define XED_ICLASS_SALC_DEFINED 1 +#define XED_ICLASS_SAR_DEFINED 1 +#define XED_ICLASS_SARX_DEFINED 1 +#define XED_ICLASS_SAVEPREVSSP_DEFINED 1 +#define XED_ICLASS_SBB_DEFINED 1 +#define XED_ICLASS_SBB_LOCK_DEFINED 1 +#define XED_ICLASS_SCASB_DEFINED 1 +#define XED_ICLASS_SCASD_DEFINED 1 +#define XED_ICLASS_SCASQ_DEFINED 1 +#define XED_ICLASS_SCASW_DEFINED 1 +#define XED_ICLASS_SEAMCALL_DEFINED 1 +#define XED_ICLASS_SEAMOPS_DEFINED 1 +#define XED_ICLASS_SEAMRET_DEFINED 1 +#define XED_ICLASS_SENDUIPI_DEFINED 1 +#define XED_ICLASS_SERIALIZE_DEFINED 1 +#define XED_ICLASS_SETB_DEFINED 1 +#define XED_ICLASS_SETBE_DEFINED 1 +#define XED_ICLASS_SETL_DEFINED 1 +#define XED_ICLASS_SETLE_DEFINED 1 +#define XED_ICLASS_SETNB_DEFINED 1 +#define XED_ICLASS_SETNBE_DEFINED 1 +#define XED_ICLASS_SETNL_DEFINED 1 +#define XED_ICLASS_SETNLE_DEFINED 1 +#define XED_ICLASS_SETNO_DEFINED 1 +#define XED_ICLASS_SETNP_DEFINED 1 +#define XED_ICLASS_SETNS_DEFINED 1 +#define XED_ICLASS_SETNZ_DEFINED 1 +#define XED_ICLASS_SETO_DEFINED 1 +#define XED_ICLASS_SETP_DEFINED 1 +#define XED_ICLASS_SETS_DEFINED 1 +#define XED_ICLASS_SETSSBSY_DEFINED 1 +#define XED_ICLASS_SETZ_DEFINED 1 +#define XED_ICLASS_SFENCE_DEFINED 1 +#define XED_ICLASS_SGDT_DEFINED 1 +#define XED_ICLASS_SHA1MSG1_DEFINED 1 +#define XED_ICLASS_SHA1MSG2_DEFINED 1 +#define XED_ICLASS_SHA1NEXTE_DEFINED 1 +#define XED_ICLASS_SHA1RNDS4_DEFINED 1 +#define XED_ICLASS_SHA256MSG1_DEFINED 1 +#define XED_ICLASS_SHA256MSG2_DEFINED 1 +#define XED_ICLASS_SHA256RNDS2_DEFINED 1 +#define XED_ICLASS_SHL_DEFINED 1 +#define XED_ICLASS_SHLD_DEFINED 1 +#define XED_ICLASS_SHLX_DEFINED 1 +#define XED_ICLASS_SHR_DEFINED 1 +#define XED_ICLASS_SHRD_DEFINED 1 +#define XED_ICLASS_SHRX_DEFINED 1 +#define XED_ICLASS_SHUFPD_DEFINED 1 +#define XED_ICLASS_SHUFPS_DEFINED 1 +#define XED_ICLASS_SIDT_DEFINED 1 +#define XED_ICLASS_SKINIT_DEFINED 1 +#define XED_ICLASS_SLDT_DEFINED 1 +#define XED_ICLASS_SLWPCB_DEFINED 1 +#define XED_ICLASS_SMSW_DEFINED 1 +#define XED_ICLASS_SQRTPD_DEFINED 1 +#define XED_ICLASS_SQRTPS_DEFINED 1 +#define XED_ICLASS_SQRTSD_DEFINED 1 +#define XED_ICLASS_SQRTSS_DEFINED 1 +#define XED_ICLASS_STAC_DEFINED 1 +#define XED_ICLASS_STC_DEFINED 1 +#define XED_ICLASS_STD_DEFINED 1 +#define XED_ICLASS_STGI_DEFINED 1 +#define XED_ICLASS_STI_DEFINED 1 +#define XED_ICLASS_STMXCSR_DEFINED 1 +#define XED_ICLASS_STOSB_DEFINED 1 +#define XED_ICLASS_STOSD_DEFINED 1 +#define XED_ICLASS_STOSQ_DEFINED 1 +#define XED_ICLASS_STOSW_DEFINED 1 +#define XED_ICLASS_STR_DEFINED 1 +#define XED_ICLASS_STTILECFG_DEFINED 1 +#define XED_ICLASS_STUI_DEFINED 1 +#define XED_ICLASS_SUB_DEFINED 1 +#define XED_ICLASS_SUBPD_DEFINED 1 +#define XED_ICLASS_SUBPS_DEFINED 1 +#define XED_ICLASS_SUBSD_DEFINED 1 +#define XED_ICLASS_SUBSS_DEFINED 1 +#define XED_ICLASS_SUB_LOCK_DEFINED 1 +#define XED_ICLASS_SWAPGS_DEFINED 1 +#define XED_ICLASS_SYSCALL_DEFINED 1 +#define XED_ICLASS_SYSCALL_AMD_DEFINED 1 +#define XED_ICLASS_SYSENTER_DEFINED 1 +#define XED_ICLASS_SYSEXIT_DEFINED 1 +#define XED_ICLASS_SYSRET_DEFINED 1 +#define XED_ICLASS_SYSRET64_DEFINED 1 +#define XED_ICLASS_SYSRET_AMD_DEFINED 1 +#define XED_ICLASS_T1MSKC_DEFINED 1 +#define XED_ICLASS_TDCALL_DEFINED 1 +#define XED_ICLASS_TDPBF16PS_DEFINED 1 +#define XED_ICLASS_TDPBSSD_DEFINED 1 +#define XED_ICLASS_TDPBSUD_DEFINED 1 +#define XED_ICLASS_TDPBUSD_DEFINED 1 +#define XED_ICLASS_TDPBUUD_DEFINED 1 +#define XED_ICLASS_TEST_DEFINED 1 +#define XED_ICLASS_TESTUI_DEFINED 1 +#define XED_ICLASS_TILELOADD_DEFINED 1 +#define XED_ICLASS_TILELOADDT1_DEFINED 1 +#define XED_ICLASS_TILERELEASE_DEFINED 1 +#define XED_ICLASS_TILESTORED_DEFINED 1 +#define XED_ICLASS_TILEZERO_DEFINED 1 +#define XED_ICLASS_TLBSYNC_DEFINED 1 +#define XED_ICLASS_TPAUSE_DEFINED 1 +#define XED_ICLASS_TZCNT_DEFINED 1 +#define XED_ICLASS_TZMSK_DEFINED 1 +#define XED_ICLASS_UCOMISD_DEFINED 1 +#define XED_ICLASS_UCOMISS_DEFINED 1 +#define XED_ICLASS_UD0_DEFINED 1 +#define XED_ICLASS_UD1_DEFINED 1 +#define XED_ICLASS_UD2_DEFINED 1 +#define XED_ICLASS_UIRET_DEFINED 1 +#define XED_ICLASS_UMONITOR_DEFINED 1 +#define XED_ICLASS_UMWAIT_DEFINED 1 +#define XED_ICLASS_UNPCKHPD_DEFINED 1 +#define XED_ICLASS_UNPCKHPS_DEFINED 1 +#define XED_ICLASS_UNPCKLPD_DEFINED 1 +#define XED_ICLASS_UNPCKLPS_DEFINED 1 +#define XED_ICLASS_V4FMADDPS_DEFINED 1 +#define XED_ICLASS_V4FMADDSS_DEFINED 1 +#define XED_ICLASS_V4FNMADDPS_DEFINED 1 +#define XED_ICLASS_V4FNMADDSS_DEFINED 1 +#define XED_ICLASS_VADDPD_DEFINED 1 +#define XED_ICLASS_VADDPH_DEFINED 1 +#define XED_ICLASS_VADDPS_DEFINED 1 +#define XED_ICLASS_VADDSD_DEFINED 1 +#define XED_ICLASS_VADDSH_DEFINED 1 +#define XED_ICLASS_VADDSS_DEFINED 1 +#define XED_ICLASS_VADDSUBPD_DEFINED 1 +#define XED_ICLASS_VADDSUBPS_DEFINED 1 +#define XED_ICLASS_VAESDEC_DEFINED 1 +#define XED_ICLASS_VAESDECLAST_DEFINED 1 +#define XED_ICLASS_VAESENC_DEFINED 1 +#define XED_ICLASS_VAESENCLAST_DEFINED 1 +#define XED_ICLASS_VAESIMC_DEFINED 1 +#define XED_ICLASS_VAESKEYGENASSIST_DEFINED 1 +#define XED_ICLASS_VALIGND_DEFINED 1 +#define XED_ICLASS_VALIGNQ_DEFINED 1 +#define XED_ICLASS_VANDNPD_DEFINED 1 +#define XED_ICLASS_VANDNPS_DEFINED 1 +#define XED_ICLASS_VANDPD_DEFINED 1 +#define XED_ICLASS_VANDPS_DEFINED 1 +#define XED_ICLASS_VBLENDMPD_DEFINED 1 +#define XED_ICLASS_VBLENDMPS_DEFINED 1 +#define XED_ICLASS_VBLENDPD_DEFINED 1 +#define XED_ICLASS_VBLENDPS_DEFINED 1 +#define XED_ICLASS_VBLENDVPD_DEFINED 1 +#define XED_ICLASS_VBLENDVPS_DEFINED 1 +#define XED_ICLASS_VBROADCASTF128_DEFINED 1 +#define XED_ICLASS_VBROADCASTF32X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTF32X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTF32X8_DEFINED 1 +#define XED_ICLASS_VBROADCASTF64X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTF64X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTI128_DEFINED 1 +#define XED_ICLASS_VBROADCASTI32X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTI32X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTI32X8_DEFINED 1 +#define XED_ICLASS_VBROADCASTI64X2_DEFINED 1 +#define XED_ICLASS_VBROADCASTI64X4_DEFINED 1 +#define XED_ICLASS_VBROADCASTSD_DEFINED 1 +#define XED_ICLASS_VBROADCASTSS_DEFINED 1 +#define XED_ICLASS_VCMPPD_DEFINED 1 +#define XED_ICLASS_VCMPPH_DEFINED 1 +#define XED_ICLASS_VCMPPS_DEFINED 1 +#define XED_ICLASS_VCMPSD_DEFINED 1 +#define XED_ICLASS_VCMPSH_DEFINED 1 +#define XED_ICLASS_VCMPSS_DEFINED 1 +#define XED_ICLASS_VCOMISD_DEFINED 1 +#define XED_ICLASS_VCOMISH_DEFINED 1 +#define XED_ICLASS_VCOMISS_DEFINED 1 +#define XED_ICLASS_VCOMPRESSPD_DEFINED 1 +#define XED_ICLASS_VCOMPRESSPS_DEFINED 1 +#define XED_ICLASS_VCVTDQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTDQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTDQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTNE2PS2BF16_DEFINED 1 +#define XED_ICLASS_VCVTNEPS2BF16_DEFINED 1 +#define XED_ICLASS_VCVTPD2DQ_DEFINED 1 +#define XED_ICLASS_VCVTPD2PH_DEFINED 1 +#define XED_ICLASS_VCVTPD2PS_DEFINED 1 +#define XED_ICLASS_VCVTPD2QQ_DEFINED 1 +#define XED_ICLASS_VCVTPD2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTPD2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2DQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2PD_DEFINED 1 +#define XED_ICLASS_VCVTPH2PS_DEFINED 1 +#define XED_ICLASS_VCVTPH2PSX_DEFINED 1 +#define XED_ICLASS_VCVTPH2QQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTPH2UW_DEFINED 1 +#define XED_ICLASS_VCVTPH2W_DEFINED 1 +#define XED_ICLASS_VCVTPS2DQ_DEFINED 1 +#define XED_ICLASS_VCVTPS2PD_DEFINED 1 +#define XED_ICLASS_VCVTPS2PH_DEFINED 1 +#define XED_ICLASS_VCVTPS2PHX_DEFINED 1 +#define XED_ICLASS_VCVTPS2QQ_DEFINED 1 +#define XED_ICLASS_VCVTPS2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTPS2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTQQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTQQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTQQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTSD2SH_DEFINED 1 +#define XED_ICLASS_VCVTSD2SI_DEFINED 1 +#define XED_ICLASS_VCVTSD2SS_DEFINED 1 +#define XED_ICLASS_VCVTSD2USI_DEFINED 1 +#define XED_ICLASS_VCVTSH2SD_DEFINED 1 +#define XED_ICLASS_VCVTSH2SI_DEFINED 1 +#define XED_ICLASS_VCVTSH2SS_DEFINED 1 +#define XED_ICLASS_VCVTSH2USI_DEFINED 1 +#define XED_ICLASS_VCVTSI2SD_DEFINED 1 +#define XED_ICLASS_VCVTSI2SH_DEFINED 1 +#define XED_ICLASS_VCVTSI2SS_DEFINED 1 +#define XED_ICLASS_VCVTSS2SD_DEFINED 1 +#define XED_ICLASS_VCVTSS2SH_DEFINED 1 +#define XED_ICLASS_VCVTSS2SI_DEFINED 1 +#define XED_ICLASS_VCVTSS2USI_DEFINED 1 +#define XED_ICLASS_VCVTTPD2DQ_DEFINED 1 +#define XED_ICLASS_VCVTTPD2QQ_DEFINED 1 +#define XED_ICLASS_VCVTTPD2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTTPD2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2DQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2QQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTTPH2UW_DEFINED 1 +#define XED_ICLASS_VCVTTPH2W_DEFINED 1 +#define XED_ICLASS_VCVTTPS2DQ_DEFINED 1 +#define XED_ICLASS_VCVTTPS2QQ_DEFINED 1 +#define XED_ICLASS_VCVTTPS2UDQ_DEFINED 1 +#define XED_ICLASS_VCVTTPS2UQQ_DEFINED 1 +#define XED_ICLASS_VCVTTSD2SI_DEFINED 1 +#define XED_ICLASS_VCVTTSD2USI_DEFINED 1 +#define XED_ICLASS_VCVTTSH2SI_DEFINED 1 +#define XED_ICLASS_VCVTTSH2USI_DEFINED 1 +#define XED_ICLASS_VCVTTSS2SI_DEFINED 1 +#define XED_ICLASS_VCVTTSS2USI_DEFINED 1 +#define XED_ICLASS_VCVTUDQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTUDQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTUDQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTUQQ2PD_DEFINED 1 +#define XED_ICLASS_VCVTUQQ2PH_DEFINED 1 +#define XED_ICLASS_VCVTUQQ2PS_DEFINED 1 +#define XED_ICLASS_VCVTUSI2SD_DEFINED 1 +#define XED_ICLASS_VCVTUSI2SH_DEFINED 1 +#define XED_ICLASS_VCVTUSI2SS_DEFINED 1 +#define XED_ICLASS_VCVTUW2PH_DEFINED 1 +#define XED_ICLASS_VCVTW2PH_DEFINED 1 +#define XED_ICLASS_VDBPSADBW_DEFINED 1 +#define XED_ICLASS_VDIVPD_DEFINED 1 +#define XED_ICLASS_VDIVPH_DEFINED 1 +#define XED_ICLASS_VDIVPS_DEFINED 1 +#define XED_ICLASS_VDIVSD_DEFINED 1 +#define XED_ICLASS_VDIVSH_DEFINED 1 +#define XED_ICLASS_VDIVSS_DEFINED 1 +#define XED_ICLASS_VDPBF16PS_DEFINED 1 +#define XED_ICLASS_VDPPD_DEFINED 1 +#define XED_ICLASS_VDPPS_DEFINED 1 +#define XED_ICLASS_VERR_DEFINED 1 +#define XED_ICLASS_VERW_DEFINED 1 +#define XED_ICLASS_VEXP2PD_DEFINED 1 +#define XED_ICLASS_VEXP2PS_DEFINED 1 +#define XED_ICLASS_VEXPANDPD_DEFINED 1 +#define XED_ICLASS_VEXPANDPS_DEFINED 1 +#define XED_ICLASS_VEXTRACTF128_DEFINED 1 +#define XED_ICLASS_VEXTRACTF32X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTF32X8_DEFINED 1 +#define XED_ICLASS_VEXTRACTF64X2_DEFINED 1 +#define XED_ICLASS_VEXTRACTF64X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTI128_DEFINED 1 +#define XED_ICLASS_VEXTRACTI32X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTI32X8_DEFINED 1 +#define XED_ICLASS_VEXTRACTI64X2_DEFINED 1 +#define XED_ICLASS_VEXTRACTI64X4_DEFINED 1 +#define XED_ICLASS_VEXTRACTPS_DEFINED 1 +#define XED_ICLASS_VFCMADDCPH_DEFINED 1 +#define XED_ICLASS_VFCMADDCSH_DEFINED 1 +#define XED_ICLASS_VFCMULCPH_DEFINED 1 +#define XED_ICLASS_VFCMULCSH_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMPD_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMPS_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMSD_DEFINED 1 +#define XED_ICLASS_VFIXUPIMMSS_DEFINED 1 +#define XED_ICLASS_VFMADD132PD_DEFINED 1 +#define XED_ICLASS_VFMADD132PH_DEFINED 1 +#define XED_ICLASS_VFMADD132PS_DEFINED 1 +#define XED_ICLASS_VFMADD132SD_DEFINED 1 +#define XED_ICLASS_VFMADD132SH_DEFINED 1 +#define XED_ICLASS_VFMADD132SS_DEFINED 1 +#define XED_ICLASS_VFMADD213PD_DEFINED 1 +#define XED_ICLASS_VFMADD213PH_DEFINED 1 +#define XED_ICLASS_VFMADD213PS_DEFINED 1 +#define XED_ICLASS_VFMADD213SD_DEFINED 1 +#define XED_ICLASS_VFMADD213SH_DEFINED 1 +#define XED_ICLASS_VFMADD213SS_DEFINED 1 +#define XED_ICLASS_VFMADD231PD_DEFINED 1 +#define XED_ICLASS_VFMADD231PH_DEFINED 1 +#define XED_ICLASS_VFMADD231PS_DEFINED 1 +#define XED_ICLASS_VFMADD231SD_DEFINED 1 +#define XED_ICLASS_VFMADD231SH_DEFINED 1 +#define XED_ICLASS_VFMADD231SS_DEFINED 1 +#define XED_ICLASS_VFMADDCPH_DEFINED 1 +#define XED_ICLASS_VFMADDCSH_DEFINED 1 +#define XED_ICLASS_VFMADDPD_DEFINED 1 +#define XED_ICLASS_VFMADDPS_DEFINED 1 +#define XED_ICLASS_VFMADDSD_DEFINED 1 +#define XED_ICLASS_VFMADDSS_DEFINED 1 +#define XED_ICLASS_VFMADDSUB132PD_DEFINED 1 +#define XED_ICLASS_VFMADDSUB132PH_DEFINED 1 +#define XED_ICLASS_VFMADDSUB132PS_DEFINED 1 +#define XED_ICLASS_VFMADDSUB213PD_DEFINED 1 +#define XED_ICLASS_VFMADDSUB213PH_DEFINED 1 +#define XED_ICLASS_VFMADDSUB213PS_DEFINED 1 +#define XED_ICLASS_VFMADDSUB231PD_DEFINED 1 +#define XED_ICLASS_VFMADDSUB231PH_DEFINED 1 +#define XED_ICLASS_VFMADDSUB231PS_DEFINED 1 +#define XED_ICLASS_VFMADDSUBPD_DEFINED 1 +#define XED_ICLASS_VFMADDSUBPS_DEFINED 1 +#define XED_ICLASS_VFMSUB132PD_DEFINED 1 +#define XED_ICLASS_VFMSUB132PH_DEFINED 1 +#define XED_ICLASS_VFMSUB132PS_DEFINED 1 +#define XED_ICLASS_VFMSUB132SD_DEFINED 1 +#define XED_ICLASS_VFMSUB132SH_DEFINED 1 +#define XED_ICLASS_VFMSUB132SS_DEFINED 1 +#define XED_ICLASS_VFMSUB213PD_DEFINED 1 +#define XED_ICLASS_VFMSUB213PH_DEFINED 1 +#define XED_ICLASS_VFMSUB213PS_DEFINED 1 +#define XED_ICLASS_VFMSUB213SD_DEFINED 1 +#define XED_ICLASS_VFMSUB213SH_DEFINED 1 +#define XED_ICLASS_VFMSUB213SS_DEFINED 1 +#define XED_ICLASS_VFMSUB231PD_DEFINED 1 +#define XED_ICLASS_VFMSUB231PH_DEFINED 1 +#define XED_ICLASS_VFMSUB231PS_DEFINED 1 +#define XED_ICLASS_VFMSUB231SD_DEFINED 1 +#define XED_ICLASS_VFMSUB231SH_DEFINED 1 +#define XED_ICLASS_VFMSUB231SS_DEFINED 1 +#define XED_ICLASS_VFMSUBADD132PD_DEFINED 1 +#define XED_ICLASS_VFMSUBADD132PH_DEFINED 1 +#define XED_ICLASS_VFMSUBADD132PS_DEFINED 1 +#define XED_ICLASS_VFMSUBADD213PD_DEFINED 1 +#define XED_ICLASS_VFMSUBADD213PH_DEFINED 1 +#define XED_ICLASS_VFMSUBADD213PS_DEFINED 1 +#define XED_ICLASS_VFMSUBADD231PD_DEFINED 1 +#define XED_ICLASS_VFMSUBADD231PH_DEFINED 1 +#define XED_ICLASS_VFMSUBADD231PS_DEFINED 1 +#define XED_ICLASS_VFMSUBADDPD_DEFINED 1 +#define XED_ICLASS_VFMSUBADDPS_DEFINED 1 +#define XED_ICLASS_VFMSUBPD_DEFINED 1 +#define XED_ICLASS_VFMSUBPS_DEFINED 1 +#define XED_ICLASS_VFMSUBSD_DEFINED 1 +#define XED_ICLASS_VFMSUBSS_DEFINED 1 +#define XED_ICLASS_VFMULCPH_DEFINED 1 +#define XED_ICLASS_VFMULCSH_DEFINED 1 +#define XED_ICLASS_VFNMADD132PD_DEFINED 1 +#define XED_ICLASS_VFNMADD132PH_DEFINED 1 +#define XED_ICLASS_VFNMADD132PS_DEFINED 1 +#define XED_ICLASS_VFNMADD132SD_DEFINED 1 +#define XED_ICLASS_VFNMADD132SH_DEFINED 1 +#define XED_ICLASS_VFNMADD132SS_DEFINED 1 +#define XED_ICLASS_VFNMADD213PD_DEFINED 1 +#define XED_ICLASS_VFNMADD213PH_DEFINED 1 +#define XED_ICLASS_VFNMADD213PS_DEFINED 1 +#define XED_ICLASS_VFNMADD213SD_DEFINED 1 +#define XED_ICLASS_VFNMADD213SH_DEFINED 1 +#define XED_ICLASS_VFNMADD213SS_DEFINED 1 +#define XED_ICLASS_VFNMADD231PD_DEFINED 1 +#define XED_ICLASS_VFNMADD231PH_DEFINED 1 +#define XED_ICLASS_VFNMADD231PS_DEFINED 1 +#define XED_ICLASS_VFNMADD231SD_DEFINED 1 +#define XED_ICLASS_VFNMADD231SH_DEFINED 1 +#define XED_ICLASS_VFNMADD231SS_DEFINED 1 +#define XED_ICLASS_VFNMADDPD_DEFINED 1 +#define XED_ICLASS_VFNMADDPS_DEFINED 1 +#define XED_ICLASS_VFNMADDSD_DEFINED 1 +#define XED_ICLASS_VFNMADDSS_DEFINED 1 +#define XED_ICLASS_VFNMSUB132PD_DEFINED 1 +#define XED_ICLASS_VFNMSUB132PH_DEFINED 1 +#define XED_ICLASS_VFNMSUB132PS_DEFINED 1 +#define XED_ICLASS_VFNMSUB132SD_DEFINED 1 +#define XED_ICLASS_VFNMSUB132SH_DEFINED 1 +#define XED_ICLASS_VFNMSUB132SS_DEFINED 1 +#define XED_ICLASS_VFNMSUB213PD_DEFINED 1 +#define XED_ICLASS_VFNMSUB213PH_DEFINED 1 +#define XED_ICLASS_VFNMSUB213PS_DEFINED 1 +#define XED_ICLASS_VFNMSUB213SD_DEFINED 1 +#define XED_ICLASS_VFNMSUB213SH_DEFINED 1 +#define XED_ICLASS_VFNMSUB213SS_DEFINED 1 +#define XED_ICLASS_VFNMSUB231PD_DEFINED 1 +#define XED_ICLASS_VFNMSUB231PH_DEFINED 1 +#define XED_ICLASS_VFNMSUB231PS_DEFINED 1 +#define XED_ICLASS_VFNMSUB231SD_DEFINED 1 +#define XED_ICLASS_VFNMSUB231SH_DEFINED 1 +#define XED_ICLASS_VFNMSUB231SS_DEFINED 1 +#define XED_ICLASS_VFNMSUBPD_DEFINED 1 +#define XED_ICLASS_VFNMSUBPS_DEFINED 1 +#define XED_ICLASS_VFNMSUBSD_DEFINED 1 +#define XED_ICLASS_VFNMSUBSS_DEFINED 1 +#define XED_ICLASS_VFPCLASSPD_DEFINED 1 +#define XED_ICLASS_VFPCLASSPH_DEFINED 1 +#define XED_ICLASS_VFPCLASSPS_DEFINED 1 +#define XED_ICLASS_VFPCLASSSD_DEFINED 1 +#define XED_ICLASS_VFPCLASSSH_DEFINED 1 +#define XED_ICLASS_VFPCLASSSS_DEFINED 1 +#define XED_ICLASS_VFRCZPD_DEFINED 1 +#define XED_ICLASS_VFRCZPS_DEFINED 1 +#define XED_ICLASS_VFRCZSD_DEFINED 1 +#define XED_ICLASS_VFRCZSS_DEFINED 1 +#define XED_ICLASS_VGATHERDPD_DEFINED 1 +#define XED_ICLASS_VGATHERDPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF0DPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF0DPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF0QPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF0QPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF1DPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF1DPS_DEFINED 1 +#define XED_ICLASS_VGATHERPF1QPD_DEFINED 1 +#define XED_ICLASS_VGATHERPF1QPS_DEFINED 1 +#define XED_ICLASS_VGATHERQPD_DEFINED 1 +#define XED_ICLASS_VGATHERQPS_DEFINED 1 +#define XED_ICLASS_VGETEXPPD_DEFINED 1 +#define XED_ICLASS_VGETEXPPH_DEFINED 1 +#define XED_ICLASS_VGETEXPPS_DEFINED 1 +#define XED_ICLASS_VGETEXPSD_DEFINED 1 +#define XED_ICLASS_VGETEXPSH_DEFINED 1 +#define XED_ICLASS_VGETEXPSS_DEFINED 1 +#define XED_ICLASS_VGETMANTPD_DEFINED 1 +#define XED_ICLASS_VGETMANTPH_DEFINED 1 +#define XED_ICLASS_VGETMANTPS_DEFINED 1 +#define XED_ICLASS_VGETMANTSD_DEFINED 1 +#define XED_ICLASS_VGETMANTSH_DEFINED 1 +#define XED_ICLASS_VGETMANTSS_DEFINED 1 +#define XED_ICLASS_VGF2P8AFFINEINVQB_DEFINED 1 +#define XED_ICLASS_VGF2P8AFFINEQB_DEFINED 1 +#define XED_ICLASS_VGF2P8MULB_DEFINED 1 +#define XED_ICLASS_VHADDPD_DEFINED 1 +#define XED_ICLASS_VHADDPS_DEFINED 1 +#define XED_ICLASS_VHSUBPD_DEFINED 1 +#define XED_ICLASS_VHSUBPS_DEFINED 1 +#define XED_ICLASS_VINSERTF128_DEFINED 1 +#define XED_ICLASS_VINSERTF32X4_DEFINED 1 +#define XED_ICLASS_VINSERTF32X8_DEFINED 1 +#define XED_ICLASS_VINSERTF64X2_DEFINED 1 +#define XED_ICLASS_VINSERTF64X4_DEFINED 1 +#define XED_ICLASS_VINSERTI128_DEFINED 1 +#define XED_ICLASS_VINSERTI32X4_DEFINED 1 +#define XED_ICLASS_VINSERTI32X8_DEFINED 1 +#define XED_ICLASS_VINSERTI64X2_DEFINED 1 +#define XED_ICLASS_VINSERTI64X4_DEFINED 1 +#define XED_ICLASS_VINSERTPS_DEFINED 1 +#define XED_ICLASS_VLDDQU_DEFINED 1 +#define XED_ICLASS_VLDMXCSR_DEFINED 1 +#define XED_ICLASS_VMASKMOVDQU_DEFINED 1 +#define XED_ICLASS_VMASKMOVPD_DEFINED 1 +#define XED_ICLASS_VMASKMOVPS_DEFINED 1 +#define XED_ICLASS_VMAXPD_DEFINED 1 +#define XED_ICLASS_VMAXPH_DEFINED 1 +#define XED_ICLASS_VMAXPS_DEFINED 1 +#define XED_ICLASS_VMAXSD_DEFINED 1 +#define XED_ICLASS_VMAXSH_DEFINED 1 +#define XED_ICLASS_VMAXSS_DEFINED 1 +#define XED_ICLASS_VMCALL_DEFINED 1 +#define XED_ICLASS_VMCLEAR_DEFINED 1 +#define XED_ICLASS_VMFUNC_DEFINED 1 +#define XED_ICLASS_VMINPD_DEFINED 1 +#define XED_ICLASS_VMINPH_DEFINED 1 +#define XED_ICLASS_VMINPS_DEFINED 1 +#define XED_ICLASS_VMINSD_DEFINED 1 +#define XED_ICLASS_VMINSH_DEFINED 1 +#define XED_ICLASS_VMINSS_DEFINED 1 +#define XED_ICLASS_VMLAUNCH_DEFINED 1 +#define XED_ICLASS_VMLOAD_DEFINED 1 +#define XED_ICLASS_VMMCALL_DEFINED 1 +#define XED_ICLASS_VMOVAPD_DEFINED 1 +#define XED_ICLASS_VMOVAPS_DEFINED 1 +#define XED_ICLASS_VMOVD_DEFINED 1 +#define XED_ICLASS_VMOVDDUP_DEFINED 1 +#define XED_ICLASS_VMOVDQA_DEFINED 1 +#define XED_ICLASS_VMOVDQA32_DEFINED 1 +#define XED_ICLASS_VMOVDQA64_DEFINED 1 +#define XED_ICLASS_VMOVDQU_DEFINED 1 +#define XED_ICLASS_VMOVDQU16_DEFINED 1 +#define XED_ICLASS_VMOVDQU32_DEFINED 1 +#define XED_ICLASS_VMOVDQU64_DEFINED 1 +#define XED_ICLASS_VMOVDQU8_DEFINED 1 +#define XED_ICLASS_VMOVHLPS_DEFINED 1 +#define XED_ICLASS_VMOVHPD_DEFINED 1 +#define XED_ICLASS_VMOVHPS_DEFINED 1 +#define XED_ICLASS_VMOVLHPS_DEFINED 1 +#define XED_ICLASS_VMOVLPD_DEFINED 1 +#define XED_ICLASS_VMOVLPS_DEFINED 1 +#define XED_ICLASS_VMOVMSKPD_DEFINED 1 +#define XED_ICLASS_VMOVMSKPS_DEFINED 1 +#define XED_ICLASS_VMOVNTDQ_DEFINED 1 +#define XED_ICLASS_VMOVNTDQA_DEFINED 1 +#define XED_ICLASS_VMOVNTPD_DEFINED 1 +#define XED_ICLASS_VMOVNTPS_DEFINED 1 +#define XED_ICLASS_VMOVQ_DEFINED 1 +#define XED_ICLASS_VMOVSD_DEFINED 1 +#define XED_ICLASS_VMOVSH_DEFINED 1 +#define XED_ICLASS_VMOVSHDUP_DEFINED 1 +#define XED_ICLASS_VMOVSLDUP_DEFINED 1 +#define XED_ICLASS_VMOVSS_DEFINED 1 +#define XED_ICLASS_VMOVUPD_DEFINED 1 +#define XED_ICLASS_VMOVUPS_DEFINED 1 +#define XED_ICLASS_VMOVW_DEFINED 1 +#define XED_ICLASS_VMPSADBW_DEFINED 1 +#define XED_ICLASS_VMPTRLD_DEFINED 1 +#define XED_ICLASS_VMPTRST_DEFINED 1 +#define XED_ICLASS_VMREAD_DEFINED 1 +#define XED_ICLASS_VMRESUME_DEFINED 1 +#define XED_ICLASS_VMRUN_DEFINED 1 +#define XED_ICLASS_VMSAVE_DEFINED 1 +#define XED_ICLASS_VMULPD_DEFINED 1 +#define XED_ICLASS_VMULPH_DEFINED 1 +#define XED_ICLASS_VMULPS_DEFINED 1 +#define XED_ICLASS_VMULSD_DEFINED 1 +#define XED_ICLASS_VMULSH_DEFINED 1 +#define XED_ICLASS_VMULSS_DEFINED 1 +#define XED_ICLASS_VMWRITE_DEFINED 1 +#define XED_ICLASS_VMXOFF_DEFINED 1 +#define XED_ICLASS_VMXON_DEFINED 1 +#define XED_ICLASS_VORPD_DEFINED 1 +#define XED_ICLASS_VORPS_DEFINED 1 +#define XED_ICLASS_VP2INTERSECTD_DEFINED 1 +#define XED_ICLASS_VP2INTERSECTQ_DEFINED 1 +#define XED_ICLASS_VP4DPWSSD_DEFINED 1 +#define XED_ICLASS_VP4DPWSSDS_DEFINED 1 +#define XED_ICLASS_VPABSB_DEFINED 1 +#define XED_ICLASS_VPABSD_DEFINED 1 +#define XED_ICLASS_VPABSQ_DEFINED 1 +#define XED_ICLASS_VPABSW_DEFINED 1 +#define XED_ICLASS_VPACKSSDW_DEFINED 1 +#define XED_ICLASS_VPACKSSWB_DEFINED 1 +#define XED_ICLASS_VPACKUSDW_DEFINED 1 +#define XED_ICLASS_VPACKUSWB_DEFINED 1 +#define XED_ICLASS_VPADDB_DEFINED 1 +#define XED_ICLASS_VPADDD_DEFINED 1 +#define XED_ICLASS_VPADDQ_DEFINED 1 +#define XED_ICLASS_VPADDSB_DEFINED 1 +#define XED_ICLASS_VPADDSW_DEFINED 1 +#define XED_ICLASS_VPADDUSB_DEFINED 1 +#define XED_ICLASS_VPADDUSW_DEFINED 1 +#define XED_ICLASS_VPADDW_DEFINED 1 +#define XED_ICLASS_VPALIGNR_DEFINED 1 +#define XED_ICLASS_VPAND_DEFINED 1 +#define XED_ICLASS_VPANDD_DEFINED 1 +#define XED_ICLASS_VPANDN_DEFINED 1 +#define XED_ICLASS_VPANDND_DEFINED 1 +#define XED_ICLASS_VPANDNQ_DEFINED 1 +#define XED_ICLASS_VPANDQ_DEFINED 1 +#define XED_ICLASS_VPAVGB_DEFINED 1 +#define XED_ICLASS_VPAVGW_DEFINED 1 +#define XED_ICLASS_VPBLENDD_DEFINED 1 +#define XED_ICLASS_VPBLENDMB_DEFINED 1 +#define XED_ICLASS_VPBLENDMD_DEFINED 1 +#define XED_ICLASS_VPBLENDMQ_DEFINED 1 +#define XED_ICLASS_VPBLENDMW_DEFINED 1 +#define XED_ICLASS_VPBLENDVB_DEFINED 1 +#define XED_ICLASS_VPBLENDW_DEFINED 1 +#define XED_ICLASS_VPBROADCASTB_DEFINED 1 +#define XED_ICLASS_VPBROADCASTD_DEFINED 1 +#define XED_ICLASS_VPBROADCASTMB2Q_DEFINED 1 +#define XED_ICLASS_VPBROADCASTMW2D_DEFINED 1 +#define XED_ICLASS_VPBROADCASTQ_DEFINED 1 +#define XED_ICLASS_VPBROADCASTW_DEFINED 1 +#define XED_ICLASS_VPCLMULQDQ_DEFINED 1 +#define XED_ICLASS_VPCMOV_DEFINED 1 +#define XED_ICLASS_VPCMPB_DEFINED 1 +#define XED_ICLASS_VPCMPD_DEFINED 1 +#define XED_ICLASS_VPCMPEQB_DEFINED 1 +#define XED_ICLASS_VPCMPEQD_DEFINED 1 +#define XED_ICLASS_VPCMPEQQ_DEFINED 1 +#define XED_ICLASS_VPCMPEQW_DEFINED 1 +#define XED_ICLASS_VPCMPESTRI_DEFINED 1 +#define XED_ICLASS_VPCMPESTRI64_DEFINED 1 +#define XED_ICLASS_VPCMPESTRM_DEFINED 1 +#define XED_ICLASS_VPCMPESTRM64_DEFINED 1 +#define XED_ICLASS_VPCMPGTB_DEFINED 1 +#define XED_ICLASS_VPCMPGTD_DEFINED 1 +#define XED_ICLASS_VPCMPGTQ_DEFINED 1 +#define XED_ICLASS_VPCMPGTW_DEFINED 1 +#define XED_ICLASS_VPCMPISTRI_DEFINED 1 +#define XED_ICLASS_VPCMPISTRI64_DEFINED 1 +#define XED_ICLASS_VPCMPISTRM_DEFINED 1 +#define XED_ICLASS_VPCMPQ_DEFINED 1 +#define XED_ICLASS_VPCMPUB_DEFINED 1 +#define XED_ICLASS_VPCMPUD_DEFINED 1 +#define XED_ICLASS_VPCMPUQ_DEFINED 1 +#define XED_ICLASS_VPCMPUW_DEFINED 1 +#define XED_ICLASS_VPCMPW_DEFINED 1 +#define XED_ICLASS_VPCOMB_DEFINED 1 +#define XED_ICLASS_VPCOMD_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSB_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSD_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSQ_DEFINED 1 +#define XED_ICLASS_VPCOMPRESSW_DEFINED 1 +#define XED_ICLASS_VPCOMQ_DEFINED 1 +#define XED_ICLASS_VPCOMUB_DEFINED 1 +#define XED_ICLASS_VPCOMUD_DEFINED 1 +#define XED_ICLASS_VPCOMUQ_DEFINED 1 +#define XED_ICLASS_VPCOMUW_DEFINED 1 +#define XED_ICLASS_VPCOMW_DEFINED 1 +#define XED_ICLASS_VPCONFLICTD_DEFINED 1 +#define XED_ICLASS_VPCONFLICTQ_DEFINED 1 +#define XED_ICLASS_VPDPBUSD_DEFINED 1 +#define XED_ICLASS_VPDPBUSDS_DEFINED 1 +#define XED_ICLASS_VPDPWSSD_DEFINED 1 +#define XED_ICLASS_VPDPWSSDS_DEFINED 1 +#define XED_ICLASS_VPERM2F128_DEFINED 1 +#define XED_ICLASS_VPERM2I128_DEFINED 1 +#define XED_ICLASS_VPERMB_DEFINED 1 +#define XED_ICLASS_VPERMD_DEFINED 1 +#define XED_ICLASS_VPERMI2B_DEFINED 1 +#define XED_ICLASS_VPERMI2D_DEFINED 1 +#define XED_ICLASS_VPERMI2PD_DEFINED 1 +#define XED_ICLASS_VPERMI2PS_DEFINED 1 +#define XED_ICLASS_VPERMI2Q_DEFINED 1 +#define XED_ICLASS_VPERMI2W_DEFINED 1 +#define XED_ICLASS_VPERMIL2PD_DEFINED 1 +#define XED_ICLASS_VPERMIL2PS_DEFINED 1 +#define XED_ICLASS_VPERMILPD_DEFINED 1 +#define XED_ICLASS_VPERMILPS_DEFINED 1 +#define XED_ICLASS_VPERMPD_DEFINED 1 +#define XED_ICLASS_VPERMPS_DEFINED 1 +#define XED_ICLASS_VPERMQ_DEFINED 1 +#define XED_ICLASS_VPERMT2B_DEFINED 1 +#define XED_ICLASS_VPERMT2D_DEFINED 1 +#define XED_ICLASS_VPERMT2PD_DEFINED 1 +#define XED_ICLASS_VPERMT2PS_DEFINED 1 +#define XED_ICLASS_VPERMT2Q_DEFINED 1 +#define XED_ICLASS_VPERMT2W_DEFINED 1 +#define XED_ICLASS_VPERMW_DEFINED 1 +#define XED_ICLASS_VPEXPANDB_DEFINED 1 +#define XED_ICLASS_VPEXPANDD_DEFINED 1 +#define XED_ICLASS_VPEXPANDQ_DEFINED 1 +#define XED_ICLASS_VPEXPANDW_DEFINED 1 +#define XED_ICLASS_VPEXTRB_DEFINED 1 +#define XED_ICLASS_VPEXTRD_DEFINED 1 +#define XED_ICLASS_VPEXTRQ_DEFINED 1 +#define XED_ICLASS_VPEXTRW_DEFINED 1 +#define XED_ICLASS_VPEXTRW_C5_DEFINED 1 +#define XED_ICLASS_VPGATHERDD_DEFINED 1 +#define XED_ICLASS_VPGATHERDQ_DEFINED 1 +#define XED_ICLASS_VPGATHERQD_DEFINED 1 +#define XED_ICLASS_VPGATHERQQ_DEFINED 1 +#define XED_ICLASS_VPHADDBD_DEFINED 1 +#define XED_ICLASS_VPHADDBQ_DEFINED 1 +#define XED_ICLASS_VPHADDBW_DEFINED 1 +#define XED_ICLASS_VPHADDD_DEFINED 1 +#define XED_ICLASS_VPHADDDQ_DEFINED 1 +#define XED_ICLASS_VPHADDSW_DEFINED 1 +#define XED_ICLASS_VPHADDUBD_DEFINED 1 +#define XED_ICLASS_VPHADDUBQ_DEFINED 1 +#define XED_ICLASS_VPHADDUBW_DEFINED 1 +#define XED_ICLASS_VPHADDUDQ_DEFINED 1 +#define XED_ICLASS_VPHADDUWD_DEFINED 1 +#define XED_ICLASS_VPHADDUWQ_DEFINED 1 +#define XED_ICLASS_VPHADDW_DEFINED 1 +#define XED_ICLASS_VPHADDWD_DEFINED 1 +#define XED_ICLASS_VPHADDWQ_DEFINED 1 +#define XED_ICLASS_VPHMINPOSUW_DEFINED 1 +#define XED_ICLASS_VPHSUBBW_DEFINED 1 +#define XED_ICLASS_VPHSUBD_DEFINED 1 +#define XED_ICLASS_VPHSUBDQ_DEFINED 1 +#define XED_ICLASS_VPHSUBSW_DEFINED 1 +#define XED_ICLASS_VPHSUBW_DEFINED 1 +#define XED_ICLASS_VPHSUBWD_DEFINED 1 +#define XED_ICLASS_VPINSRB_DEFINED 1 +#define XED_ICLASS_VPINSRD_DEFINED 1 +#define XED_ICLASS_VPINSRQ_DEFINED 1 +#define XED_ICLASS_VPINSRW_DEFINED 1 +#define XED_ICLASS_VPLZCNTD_DEFINED 1 +#define XED_ICLASS_VPLZCNTQ_DEFINED 1 +#define XED_ICLASS_VPMACSDD_DEFINED 1 +#define XED_ICLASS_VPMACSDQH_DEFINED 1 +#define XED_ICLASS_VPMACSDQL_DEFINED 1 +#define XED_ICLASS_VPMACSSDD_DEFINED 1 +#define XED_ICLASS_VPMACSSDQH_DEFINED 1 +#define XED_ICLASS_VPMACSSDQL_DEFINED 1 +#define XED_ICLASS_VPMACSSWD_DEFINED 1 +#define XED_ICLASS_VPMACSSWW_DEFINED 1 +#define XED_ICLASS_VPMACSWD_DEFINED 1 +#define XED_ICLASS_VPMACSWW_DEFINED 1 +#define XED_ICLASS_VPMADCSSWD_DEFINED 1 +#define XED_ICLASS_VPMADCSWD_DEFINED 1 +#define XED_ICLASS_VPMADD52HUQ_DEFINED 1 +#define XED_ICLASS_VPMADD52LUQ_DEFINED 1 +#define XED_ICLASS_VPMADDUBSW_DEFINED 1 +#define XED_ICLASS_VPMADDWD_DEFINED 1 +#define XED_ICLASS_VPMASKMOVD_DEFINED 1 +#define XED_ICLASS_VPMASKMOVQ_DEFINED 1 +#define XED_ICLASS_VPMAXSB_DEFINED 1 +#define XED_ICLASS_VPMAXSD_DEFINED 1 +#define XED_ICLASS_VPMAXSQ_DEFINED 1 +#define XED_ICLASS_VPMAXSW_DEFINED 1 +#define XED_ICLASS_VPMAXUB_DEFINED 1 +#define XED_ICLASS_VPMAXUD_DEFINED 1 +#define XED_ICLASS_VPMAXUQ_DEFINED 1 +#define XED_ICLASS_VPMAXUW_DEFINED 1 +#define XED_ICLASS_VPMINSB_DEFINED 1 +#define XED_ICLASS_VPMINSD_DEFINED 1 +#define XED_ICLASS_VPMINSQ_DEFINED 1 +#define XED_ICLASS_VPMINSW_DEFINED 1 +#define XED_ICLASS_VPMINUB_DEFINED 1 +#define XED_ICLASS_VPMINUD_DEFINED 1 +#define XED_ICLASS_VPMINUQ_DEFINED 1 +#define XED_ICLASS_VPMINUW_DEFINED 1 +#define XED_ICLASS_VPMOVB2M_DEFINED 1 +#define XED_ICLASS_VPMOVD2M_DEFINED 1 +#define XED_ICLASS_VPMOVDB_DEFINED 1 +#define XED_ICLASS_VPMOVDW_DEFINED 1 +#define XED_ICLASS_VPMOVM2B_DEFINED 1 +#define XED_ICLASS_VPMOVM2D_DEFINED 1 +#define XED_ICLASS_VPMOVM2Q_DEFINED 1 +#define XED_ICLASS_VPMOVM2W_DEFINED 1 +#define XED_ICLASS_VPMOVMSKB_DEFINED 1 +#define XED_ICLASS_VPMOVQ2M_DEFINED 1 +#define XED_ICLASS_VPMOVQB_DEFINED 1 +#define XED_ICLASS_VPMOVQD_DEFINED 1 +#define XED_ICLASS_VPMOVQW_DEFINED 1 +#define XED_ICLASS_VPMOVSDB_DEFINED 1 +#define XED_ICLASS_VPMOVSDW_DEFINED 1 +#define XED_ICLASS_VPMOVSQB_DEFINED 1 +#define XED_ICLASS_VPMOVSQD_DEFINED 1 +#define XED_ICLASS_VPMOVSQW_DEFINED 1 +#define XED_ICLASS_VPMOVSWB_DEFINED 1 +#define XED_ICLASS_VPMOVSXBD_DEFINED 1 +#define XED_ICLASS_VPMOVSXBQ_DEFINED 1 +#define XED_ICLASS_VPMOVSXBW_DEFINED 1 +#define XED_ICLASS_VPMOVSXDQ_DEFINED 1 +#define XED_ICLASS_VPMOVSXWD_DEFINED 1 +#define XED_ICLASS_VPMOVSXWQ_DEFINED 1 +#define XED_ICLASS_VPMOVUSDB_DEFINED 1 +#define XED_ICLASS_VPMOVUSDW_DEFINED 1 +#define XED_ICLASS_VPMOVUSQB_DEFINED 1 +#define XED_ICLASS_VPMOVUSQD_DEFINED 1 +#define XED_ICLASS_VPMOVUSQW_DEFINED 1 +#define XED_ICLASS_VPMOVUSWB_DEFINED 1 +#define XED_ICLASS_VPMOVW2M_DEFINED 1 +#define XED_ICLASS_VPMOVWB_DEFINED 1 +#define XED_ICLASS_VPMOVZXBD_DEFINED 1 +#define XED_ICLASS_VPMOVZXBQ_DEFINED 1 +#define XED_ICLASS_VPMOVZXBW_DEFINED 1 +#define XED_ICLASS_VPMOVZXDQ_DEFINED 1 +#define XED_ICLASS_VPMOVZXWD_DEFINED 1 +#define XED_ICLASS_VPMOVZXWQ_DEFINED 1 +#define XED_ICLASS_VPMULDQ_DEFINED 1 +#define XED_ICLASS_VPMULHRSW_DEFINED 1 +#define XED_ICLASS_VPMULHUW_DEFINED 1 +#define XED_ICLASS_VPMULHW_DEFINED 1 +#define XED_ICLASS_VPMULLD_DEFINED 1 +#define XED_ICLASS_VPMULLQ_DEFINED 1 +#define XED_ICLASS_VPMULLW_DEFINED 1 +#define XED_ICLASS_VPMULTISHIFTQB_DEFINED 1 +#define XED_ICLASS_VPMULUDQ_DEFINED 1 +#define XED_ICLASS_VPOPCNTB_DEFINED 1 +#define XED_ICLASS_VPOPCNTD_DEFINED 1 +#define XED_ICLASS_VPOPCNTQ_DEFINED 1 +#define XED_ICLASS_VPOPCNTW_DEFINED 1 +#define XED_ICLASS_VPOR_DEFINED 1 +#define XED_ICLASS_VPORD_DEFINED 1 +#define XED_ICLASS_VPORQ_DEFINED 1 +#define XED_ICLASS_VPPERM_DEFINED 1 +#define XED_ICLASS_VPROLD_DEFINED 1 +#define XED_ICLASS_VPROLQ_DEFINED 1 +#define XED_ICLASS_VPROLVD_DEFINED 1 +#define XED_ICLASS_VPROLVQ_DEFINED 1 +#define XED_ICLASS_VPRORD_DEFINED 1 +#define XED_ICLASS_VPRORQ_DEFINED 1 +#define XED_ICLASS_VPRORVD_DEFINED 1 +#define XED_ICLASS_VPRORVQ_DEFINED 1 +#define XED_ICLASS_VPROTB_DEFINED 1 +#define XED_ICLASS_VPROTD_DEFINED 1 +#define XED_ICLASS_VPROTQ_DEFINED 1 +#define XED_ICLASS_VPROTW_DEFINED 1 +#define XED_ICLASS_VPSADBW_DEFINED 1 +#define XED_ICLASS_VPSCATTERDD_DEFINED 1 +#define XED_ICLASS_VPSCATTERDQ_DEFINED 1 +#define XED_ICLASS_VPSCATTERQD_DEFINED 1 +#define XED_ICLASS_VPSCATTERQQ_DEFINED 1 +#define XED_ICLASS_VPSHAB_DEFINED 1 +#define XED_ICLASS_VPSHAD_DEFINED 1 +#define XED_ICLASS_VPSHAQ_DEFINED 1 +#define XED_ICLASS_VPSHAW_DEFINED 1 +#define XED_ICLASS_VPSHLB_DEFINED 1 +#define XED_ICLASS_VPSHLD_DEFINED 1 +#define XED_ICLASS_VPSHLDD_DEFINED 1 +#define XED_ICLASS_VPSHLDQ_DEFINED 1 +#define XED_ICLASS_VPSHLDVD_DEFINED 1 +#define XED_ICLASS_VPSHLDVQ_DEFINED 1 +#define XED_ICLASS_VPSHLDVW_DEFINED 1 +#define XED_ICLASS_VPSHLDW_DEFINED 1 +#define XED_ICLASS_VPSHLQ_DEFINED 1 +#define XED_ICLASS_VPSHLW_DEFINED 1 +#define XED_ICLASS_VPSHRDD_DEFINED 1 +#define XED_ICLASS_VPSHRDQ_DEFINED 1 +#define XED_ICLASS_VPSHRDVD_DEFINED 1 +#define XED_ICLASS_VPSHRDVQ_DEFINED 1 +#define XED_ICLASS_VPSHRDVW_DEFINED 1 +#define XED_ICLASS_VPSHRDW_DEFINED 1 +#define XED_ICLASS_VPSHUFB_DEFINED 1 +#define XED_ICLASS_VPSHUFBITQMB_DEFINED 1 +#define XED_ICLASS_VPSHUFD_DEFINED 1 +#define XED_ICLASS_VPSHUFHW_DEFINED 1 +#define XED_ICLASS_VPSHUFLW_DEFINED 1 +#define XED_ICLASS_VPSIGNB_DEFINED 1 +#define XED_ICLASS_VPSIGND_DEFINED 1 +#define XED_ICLASS_VPSIGNW_DEFINED 1 +#define XED_ICLASS_VPSLLD_DEFINED 1 +#define XED_ICLASS_VPSLLDQ_DEFINED 1 +#define XED_ICLASS_VPSLLQ_DEFINED 1 +#define XED_ICLASS_VPSLLVD_DEFINED 1 +#define XED_ICLASS_VPSLLVQ_DEFINED 1 +#define XED_ICLASS_VPSLLVW_DEFINED 1 +#define XED_ICLASS_VPSLLW_DEFINED 1 +#define XED_ICLASS_VPSRAD_DEFINED 1 +#define XED_ICLASS_VPSRAQ_DEFINED 1 +#define XED_ICLASS_VPSRAVD_DEFINED 1 +#define XED_ICLASS_VPSRAVQ_DEFINED 1 +#define XED_ICLASS_VPSRAVW_DEFINED 1 +#define XED_ICLASS_VPSRAW_DEFINED 1 +#define XED_ICLASS_VPSRLD_DEFINED 1 +#define XED_ICLASS_VPSRLDQ_DEFINED 1 +#define XED_ICLASS_VPSRLQ_DEFINED 1 +#define XED_ICLASS_VPSRLVD_DEFINED 1 +#define XED_ICLASS_VPSRLVQ_DEFINED 1 +#define XED_ICLASS_VPSRLVW_DEFINED 1 +#define XED_ICLASS_VPSRLW_DEFINED 1 +#define XED_ICLASS_VPSUBB_DEFINED 1 +#define XED_ICLASS_VPSUBD_DEFINED 1 +#define XED_ICLASS_VPSUBQ_DEFINED 1 +#define XED_ICLASS_VPSUBSB_DEFINED 1 +#define XED_ICLASS_VPSUBSW_DEFINED 1 +#define XED_ICLASS_VPSUBUSB_DEFINED 1 +#define XED_ICLASS_VPSUBUSW_DEFINED 1 +#define XED_ICLASS_VPSUBW_DEFINED 1 +#define XED_ICLASS_VPTERNLOGD_DEFINED 1 +#define XED_ICLASS_VPTERNLOGQ_DEFINED 1 +#define XED_ICLASS_VPTEST_DEFINED 1 +#define XED_ICLASS_VPTESTMB_DEFINED 1 +#define XED_ICLASS_VPTESTMD_DEFINED 1 +#define XED_ICLASS_VPTESTMQ_DEFINED 1 +#define XED_ICLASS_VPTESTMW_DEFINED 1 +#define XED_ICLASS_VPTESTNMB_DEFINED 1 +#define XED_ICLASS_VPTESTNMD_DEFINED 1 +#define XED_ICLASS_VPTESTNMQ_DEFINED 1 +#define XED_ICLASS_VPTESTNMW_DEFINED 1 +#define XED_ICLASS_VPUNPCKHBW_DEFINED 1 +#define XED_ICLASS_VPUNPCKHDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKHQDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKHWD_DEFINED 1 +#define XED_ICLASS_VPUNPCKLBW_DEFINED 1 +#define XED_ICLASS_VPUNPCKLDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKLQDQ_DEFINED 1 +#define XED_ICLASS_VPUNPCKLWD_DEFINED 1 +#define XED_ICLASS_VPXOR_DEFINED 1 +#define XED_ICLASS_VPXORD_DEFINED 1 +#define XED_ICLASS_VPXORQ_DEFINED 1 +#define XED_ICLASS_VRANGEPD_DEFINED 1 +#define XED_ICLASS_VRANGEPS_DEFINED 1 +#define XED_ICLASS_VRANGESD_DEFINED 1 +#define XED_ICLASS_VRANGESS_DEFINED 1 +#define XED_ICLASS_VRCP14PD_DEFINED 1 +#define XED_ICLASS_VRCP14PS_DEFINED 1 +#define XED_ICLASS_VRCP14SD_DEFINED 1 +#define XED_ICLASS_VRCP14SS_DEFINED 1 +#define XED_ICLASS_VRCP28PD_DEFINED 1 +#define XED_ICLASS_VRCP28PS_DEFINED 1 +#define XED_ICLASS_VRCP28SD_DEFINED 1 +#define XED_ICLASS_VRCP28SS_DEFINED 1 +#define XED_ICLASS_VRCPPH_DEFINED 1 +#define XED_ICLASS_VRCPPS_DEFINED 1 +#define XED_ICLASS_VRCPSH_DEFINED 1 +#define XED_ICLASS_VRCPSS_DEFINED 1 +#define XED_ICLASS_VREDUCEPD_DEFINED 1 +#define XED_ICLASS_VREDUCEPH_DEFINED 1 +#define XED_ICLASS_VREDUCEPS_DEFINED 1 +#define XED_ICLASS_VREDUCESD_DEFINED 1 +#define XED_ICLASS_VREDUCESH_DEFINED 1 +#define XED_ICLASS_VREDUCESS_DEFINED 1 +#define XED_ICLASS_VRNDSCALEPD_DEFINED 1 +#define XED_ICLASS_VRNDSCALEPH_DEFINED 1 +#define XED_ICLASS_VRNDSCALEPS_DEFINED 1 +#define XED_ICLASS_VRNDSCALESD_DEFINED 1 +#define XED_ICLASS_VRNDSCALESH_DEFINED 1 +#define XED_ICLASS_VRNDSCALESS_DEFINED 1 +#define XED_ICLASS_VROUNDPD_DEFINED 1 +#define XED_ICLASS_VROUNDPS_DEFINED 1 +#define XED_ICLASS_VROUNDSD_DEFINED 1 +#define XED_ICLASS_VROUNDSS_DEFINED 1 +#define XED_ICLASS_VRSQRT14PD_DEFINED 1 +#define XED_ICLASS_VRSQRT14PS_DEFINED 1 +#define XED_ICLASS_VRSQRT14SD_DEFINED 1 +#define XED_ICLASS_VRSQRT14SS_DEFINED 1 +#define XED_ICLASS_VRSQRT28PD_DEFINED 1 +#define XED_ICLASS_VRSQRT28PS_DEFINED 1 +#define XED_ICLASS_VRSQRT28SD_DEFINED 1 +#define XED_ICLASS_VRSQRT28SS_DEFINED 1 +#define XED_ICLASS_VRSQRTPH_DEFINED 1 +#define XED_ICLASS_VRSQRTPS_DEFINED 1 +#define XED_ICLASS_VRSQRTSH_DEFINED 1 +#define XED_ICLASS_VRSQRTSS_DEFINED 1 +#define XED_ICLASS_VSCALEFPD_DEFINED 1 +#define XED_ICLASS_VSCALEFPH_DEFINED 1 +#define XED_ICLASS_VSCALEFPS_DEFINED 1 +#define XED_ICLASS_VSCALEFSD_DEFINED 1 +#define XED_ICLASS_VSCALEFSH_DEFINED 1 +#define XED_ICLASS_VSCALEFSS_DEFINED 1 +#define XED_ICLASS_VSCATTERDPD_DEFINED 1 +#define XED_ICLASS_VSCATTERDPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0DPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0DPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0QPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF0QPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1DPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1DPS_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1QPD_DEFINED 1 +#define XED_ICLASS_VSCATTERPF1QPS_DEFINED 1 +#define XED_ICLASS_VSCATTERQPD_DEFINED 1 +#define XED_ICLASS_VSCATTERQPS_DEFINED 1 +#define XED_ICLASS_VSHUFF32X4_DEFINED 1 +#define XED_ICLASS_VSHUFF64X2_DEFINED 1 +#define XED_ICLASS_VSHUFI32X4_DEFINED 1 +#define XED_ICLASS_VSHUFI64X2_DEFINED 1 +#define XED_ICLASS_VSHUFPD_DEFINED 1 +#define XED_ICLASS_VSHUFPS_DEFINED 1 +#define XED_ICLASS_VSQRTPD_DEFINED 1 +#define XED_ICLASS_VSQRTPH_DEFINED 1 +#define XED_ICLASS_VSQRTPS_DEFINED 1 +#define XED_ICLASS_VSQRTSD_DEFINED 1 +#define XED_ICLASS_VSQRTSH_DEFINED 1 +#define XED_ICLASS_VSQRTSS_DEFINED 1 +#define XED_ICLASS_VSTMXCSR_DEFINED 1 +#define XED_ICLASS_VSUBPD_DEFINED 1 +#define XED_ICLASS_VSUBPH_DEFINED 1 +#define XED_ICLASS_VSUBPS_DEFINED 1 +#define XED_ICLASS_VSUBSD_DEFINED 1 +#define XED_ICLASS_VSUBSH_DEFINED 1 +#define XED_ICLASS_VSUBSS_DEFINED 1 +#define XED_ICLASS_VTESTPD_DEFINED 1 +#define XED_ICLASS_VTESTPS_DEFINED 1 +#define XED_ICLASS_VUCOMISD_DEFINED 1 +#define XED_ICLASS_VUCOMISH_DEFINED 1 +#define XED_ICLASS_VUCOMISS_DEFINED 1 +#define XED_ICLASS_VUNPCKHPD_DEFINED 1 +#define XED_ICLASS_VUNPCKHPS_DEFINED 1 +#define XED_ICLASS_VUNPCKLPD_DEFINED 1 +#define XED_ICLASS_VUNPCKLPS_DEFINED 1 +#define XED_ICLASS_VXORPD_DEFINED 1 +#define XED_ICLASS_VXORPS_DEFINED 1 +#define XED_ICLASS_VZEROALL_DEFINED 1 +#define XED_ICLASS_VZEROUPPER_DEFINED 1 +#define XED_ICLASS_WBINVD_DEFINED 1 +#define XED_ICLASS_WBNOINVD_DEFINED 1 +#define XED_ICLASS_WRFSBASE_DEFINED 1 +#define XED_ICLASS_WRGSBASE_DEFINED 1 +#define XED_ICLASS_WRMSR_DEFINED 1 +#define XED_ICLASS_WRPKRU_DEFINED 1 +#define XED_ICLASS_WRSSD_DEFINED 1 +#define XED_ICLASS_WRSSQ_DEFINED 1 +#define XED_ICLASS_WRUSSD_DEFINED 1 +#define XED_ICLASS_WRUSSQ_DEFINED 1 +#define XED_ICLASS_XABORT_DEFINED 1 +#define XED_ICLASS_XADD_DEFINED 1 +#define XED_ICLASS_XADD_LOCK_DEFINED 1 +#define XED_ICLASS_XBEGIN_DEFINED 1 +#define XED_ICLASS_XCHG_DEFINED 1 +#define XED_ICLASS_XEND_DEFINED 1 +#define XED_ICLASS_XGETBV_DEFINED 1 +#define XED_ICLASS_XLAT_DEFINED 1 +#define XED_ICLASS_XOR_DEFINED 1 +#define XED_ICLASS_XORPD_DEFINED 1 +#define XED_ICLASS_XORPS_DEFINED 1 +#define XED_ICLASS_XOR_LOCK_DEFINED 1 +#define XED_ICLASS_XRESLDTRK_DEFINED 1 +#define XED_ICLASS_XRSTOR_DEFINED 1 +#define XED_ICLASS_XRSTOR64_DEFINED 1 +#define XED_ICLASS_XRSTORS_DEFINED 1 +#define XED_ICLASS_XRSTORS64_DEFINED 1 +#define XED_ICLASS_XSAVE_DEFINED 1 +#define XED_ICLASS_XSAVE64_DEFINED 1 +#define XED_ICLASS_XSAVEC_DEFINED 1 +#define XED_ICLASS_XSAVEC64_DEFINED 1 +#define XED_ICLASS_XSAVEOPT_DEFINED 1 +#define XED_ICLASS_XSAVEOPT64_DEFINED 1 +#define XED_ICLASS_XSAVES_DEFINED 1 +#define XED_ICLASS_XSAVES64_DEFINED 1 +#define XED_ICLASS_XSETBV_DEFINED 1 +#define XED_ICLASS_XSTORE_DEFINED 1 +#define XED_ICLASS_XSUSLDTRK_DEFINED 1 +#define XED_ICLASS_XTEST_DEFINED 1 +#define XED_ICLASS_LAST_DEFINED 1 +typedef enum { + XED_ICLASS_INVALID, + XED_ICLASS_AAA, + XED_ICLASS_AAD, + XED_ICLASS_AAM, + XED_ICLASS_AAS, + XED_ICLASS_ADC, + XED_ICLASS_ADCX, + XED_ICLASS_ADC_LOCK, + XED_ICLASS_ADD, + XED_ICLASS_ADDPD, + XED_ICLASS_ADDPS, + XED_ICLASS_ADDSD, + XED_ICLASS_ADDSS, + XED_ICLASS_ADDSUBPD, + XED_ICLASS_ADDSUBPS, + XED_ICLASS_ADD_LOCK, + XED_ICLASS_ADOX, + XED_ICLASS_AESDEC, + XED_ICLASS_AESDEC128KL, + XED_ICLASS_AESDEC256KL, + XED_ICLASS_AESDECLAST, + XED_ICLASS_AESDECWIDE128KL, + XED_ICLASS_AESDECWIDE256KL, + XED_ICLASS_AESENC, + XED_ICLASS_AESENC128KL, + XED_ICLASS_AESENC256KL, + XED_ICLASS_AESENCLAST, + XED_ICLASS_AESENCWIDE128KL, + XED_ICLASS_AESENCWIDE256KL, + XED_ICLASS_AESIMC, + XED_ICLASS_AESKEYGENASSIST, + XED_ICLASS_AND, + XED_ICLASS_ANDN, + XED_ICLASS_ANDNPD, + XED_ICLASS_ANDNPS, + XED_ICLASS_ANDPD, + XED_ICLASS_ANDPS, + XED_ICLASS_AND_LOCK, + XED_ICLASS_ARPL, + XED_ICLASS_BEXTR, + XED_ICLASS_BEXTR_XOP, + XED_ICLASS_BLCFILL, + XED_ICLASS_BLCI, + XED_ICLASS_BLCIC, + XED_ICLASS_BLCMSK, + XED_ICLASS_BLCS, + XED_ICLASS_BLENDPD, + XED_ICLASS_BLENDPS, + XED_ICLASS_BLENDVPD, + XED_ICLASS_BLENDVPS, + XED_ICLASS_BLSFILL, + XED_ICLASS_BLSI, + XED_ICLASS_BLSIC, + XED_ICLASS_BLSMSK, + XED_ICLASS_BLSR, + XED_ICLASS_BNDCL, + XED_ICLASS_BNDCN, + XED_ICLASS_BNDCU, + XED_ICLASS_BNDLDX, + XED_ICLASS_BNDMK, + XED_ICLASS_BNDMOV, + XED_ICLASS_BNDSTX, + XED_ICLASS_BOUND, + XED_ICLASS_BSF, + XED_ICLASS_BSR, + XED_ICLASS_BSWAP, + XED_ICLASS_BT, + XED_ICLASS_BTC, + XED_ICLASS_BTC_LOCK, + XED_ICLASS_BTR, + XED_ICLASS_BTR_LOCK, + XED_ICLASS_BTS, + XED_ICLASS_BTS_LOCK, + XED_ICLASS_BZHI, + XED_ICLASS_CALL_FAR, + XED_ICLASS_CALL_NEAR, + XED_ICLASS_CBW, + XED_ICLASS_CDQ, + XED_ICLASS_CDQE, + XED_ICLASS_CLAC, + XED_ICLASS_CLC, + XED_ICLASS_CLD, + XED_ICLASS_CLDEMOTE, + XED_ICLASS_CLFLUSH, + XED_ICLASS_CLFLUSHOPT, + XED_ICLASS_CLGI, + XED_ICLASS_CLI, + XED_ICLASS_CLRSSBSY, + XED_ICLASS_CLTS, + XED_ICLASS_CLUI, + XED_ICLASS_CLWB, + XED_ICLASS_CLZERO, + XED_ICLASS_CMC, + XED_ICLASS_CMOVB, + XED_ICLASS_CMOVBE, + XED_ICLASS_CMOVL, + XED_ICLASS_CMOVLE, + XED_ICLASS_CMOVNB, + XED_ICLASS_CMOVNBE, + XED_ICLASS_CMOVNL, + XED_ICLASS_CMOVNLE, + XED_ICLASS_CMOVNO, + XED_ICLASS_CMOVNP, + XED_ICLASS_CMOVNS, + XED_ICLASS_CMOVNZ, + XED_ICLASS_CMOVO, + XED_ICLASS_CMOVP, + XED_ICLASS_CMOVS, + XED_ICLASS_CMOVZ, + XED_ICLASS_CMP, + XED_ICLASS_CMPPD, + XED_ICLASS_CMPPS, + XED_ICLASS_CMPSB, + XED_ICLASS_CMPSD, + XED_ICLASS_CMPSD_XMM, + XED_ICLASS_CMPSQ, + XED_ICLASS_CMPSS, + XED_ICLASS_CMPSW, + XED_ICLASS_CMPXCHG, + XED_ICLASS_CMPXCHG16B, + XED_ICLASS_CMPXCHG16B_LOCK, + XED_ICLASS_CMPXCHG8B, + XED_ICLASS_CMPXCHG8B_LOCK, + XED_ICLASS_CMPXCHG_LOCK, + XED_ICLASS_COMISD, + XED_ICLASS_COMISS, + XED_ICLASS_CPUID, + XED_ICLASS_CQO, + XED_ICLASS_CRC32, + XED_ICLASS_CVTDQ2PD, + XED_ICLASS_CVTDQ2PS, + XED_ICLASS_CVTPD2DQ, + XED_ICLASS_CVTPD2PI, + XED_ICLASS_CVTPD2PS, + XED_ICLASS_CVTPI2PD, + XED_ICLASS_CVTPI2PS, + XED_ICLASS_CVTPS2DQ, + XED_ICLASS_CVTPS2PD, + XED_ICLASS_CVTPS2PI, + XED_ICLASS_CVTSD2SI, + XED_ICLASS_CVTSD2SS, + XED_ICLASS_CVTSI2SD, + XED_ICLASS_CVTSI2SS, + XED_ICLASS_CVTSS2SD, + XED_ICLASS_CVTSS2SI, + XED_ICLASS_CVTTPD2DQ, + XED_ICLASS_CVTTPD2PI, + XED_ICLASS_CVTTPS2DQ, + XED_ICLASS_CVTTPS2PI, + XED_ICLASS_CVTTSD2SI, + XED_ICLASS_CVTTSS2SI, + XED_ICLASS_CWD, + XED_ICLASS_CWDE, + XED_ICLASS_DAA, + XED_ICLASS_DAS, + XED_ICLASS_DEC, + XED_ICLASS_DEC_LOCK, + XED_ICLASS_DIV, + XED_ICLASS_DIVPD, + XED_ICLASS_DIVPS, + XED_ICLASS_DIVSD, + XED_ICLASS_DIVSS, + XED_ICLASS_DPPD, + XED_ICLASS_DPPS, + XED_ICLASS_EMMS, + XED_ICLASS_ENCLS, + XED_ICLASS_ENCLU, + XED_ICLASS_ENCLV, + XED_ICLASS_ENCODEKEY128, + XED_ICLASS_ENCODEKEY256, + XED_ICLASS_ENDBR32, + XED_ICLASS_ENDBR64, + XED_ICLASS_ENQCMD, + XED_ICLASS_ENQCMDS, + XED_ICLASS_ENTER, + XED_ICLASS_EXTRACTPS, + XED_ICLASS_EXTRQ, + XED_ICLASS_F2XM1, + XED_ICLASS_FABS, + XED_ICLASS_FADD, + XED_ICLASS_FADDP, + XED_ICLASS_FBLD, + XED_ICLASS_FBSTP, + XED_ICLASS_FCHS, + XED_ICLASS_FCMOVB, + XED_ICLASS_FCMOVBE, + XED_ICLASS_FCMOVE, + XED_ICLASS_FCMOVNB, + XED_ICLASS_FCMOVNBE, + XED_ICLASS_FCMOVNE, + XED_ICLASS_FCMOVNU, + XED_ICLASS_FCMOVU, + XED_ICLASS_FCOM, + XED_ICLASS_FCOMI, + XED_ICLASS_FCOMIP, + XED_ICLASS_FCOMP, + XED_ICLASS_FCOMPP, + XED_ICLASS_FCOS, + XED_ICLASS_FDECSTP, + XED_ICLASS_FDISI8087_NOP, + XED_ICLASS_FDIV, + XED_ICLASS_FDIVP, + XED_ICLASS_FDIVR, + XED_ICLASS_FDIVRP, + XED_ICLASS_FEMMS, + XED_ICLASS_FENI8087_NOP, + XED_ICLASS_FFREE, + XED_ICLASS_FFREEP, + XED_ICLASS_FIADD, + XED_ICLASS_FICOM, + XED_ICLASS_FICOMP, + XED_ICLASS_FIDIV, + XED_ICLASS_FIDIVR, + XED_ICLASS_FILD, + XED_ICLASS_FIMUL, + XED_ICLASS_FINCSTP, + XED_ICLASS_FIST, + XED_ICLASS_FISTP, + XED_ICLASS_FISTTP, + XED_ICLASS_FISUB, + XED_ICLASS_FISUBR, + XED_ICLASS_FLD, + XED_ICLASS_FLD1, + XED_ICLASS_FLDCW, + XED_ICLASS_FLDENV, + XED_ICLASS_FLDL2E, + XED_ICLASS_FLDL2T, + XED_ICLASS_FLDLG2, + XED_ICLASS_FLDLN2, + XED_ICLASS_FLDPI, + XED_ICLASS_FLDZ, + XED_ICLASS_FMUL, + XED_ICLASS_FMULP, + XED_ICLASS_FNCLEX, + XED_ICLASS_FNINIT, + XED_ICLASS_FNOP, + XED_ICLASS_FNSAVE, + XED_ICLASS_FNSTCW, + XED_ICLASS_FNSTENV, + XED_ICLASS_FNSTSW, + XED_ICLASS_FPATAN, + XED_ICLASS_FPREM, + XED_ICLASS_FPREM1, + XED_ICLASS_FPTAN, + XED_ICLASS_FRNDINT, + XED_ICLASS_FRSTOR, + XED_ICLASS_FSCALE, + XED_ICLASS_FSETPM287_NOP, + XED_ICLASS_FSIN, + XED_ICLASS_FSINCOS, + XED_ICLASS_FSQRT, + XED_ICLASS_FST, + XED_ICLASS_FSTP, + XED_ICLASS_FSTPNCE, + XED_ICLASS_FSUB, + XED_ICLASS_FSUBP, + XED_ICLASS_FSUBR, + XED_ICLASS_FSUBRP, + XED_ICLASS_FTST, + XED_ICLASS_FUCOM, + XED_ICLASS_FUCOMI, + XED_ICLASS_FUCOMIP, + XED_ICLASS_FUCOMP, + XED_ICLASS_FUCOMPP, + XED_ICLASS_FWAIT, + XED_ICLASS_FXAM, + XED_ICLASS_FXCH, + XED_ICLASS_FXRSTOR, + XED_ICLASS_FXRSTOR64, + XED_ICLASS_FXSAVE, + XED_ICLASS_FXSAVE64, + XED_ICLASS_FXTRACT, + XED_ICLASS_FYL2X, + XED_ICLASS_FYL2XP1, + XED_ICLASS_GETSEC, + XED_ICLASS_GF2P8AFFINEINVQB, + XED_ICLASS_GF2P8AFFINEQB, + XED_ICLASS_GF2P8MULB, + XED_ICLASS_HADDPD, + XED_ICLASS_HADDPS, + XED_ICLASS_HLT, + XED_ICLASS_HRESET, + XED_ICLASS_HSUBPD, + XED_ICLASS_HSUBPS, + XED_ICLASS_IDIV, + XED_ICLASS_IMUL, + XED_ICLASS_IN, + XED_ICLASS_INC, + XED_ICLASS_INCSSPD, + XED_ICLASS_INCSSPQ, + XED_ICLASS_INC_LOCK, + XED_ICLASS_INSB, + XED_ICLASS_INSD, + XED_ICLASS_INSERTPS, + XED_ICLASS_INSERTQ, + XED_ICLASS_INSW, + XED_ICLASS_INT, + XED_ICLASS_INT1, + XED_ICLASS_INT3, + XED_ICLASS_INTO, + XED_ICLASS_INVD, + XED_ICLASS_INVEPT, + XED_ICLASS_INVLPG, + XED_ICLASS_INVLPGA, + XED_ICLASS_INVLPGB, + XED_ICLASS_INVPCID, + XED_ICLASS_INVVPID, + XED_ICLASS_IRET, + XED_ICLASS_IRETD, + XED_ICLASS_IRETQ, + XED_ICLASS_JB, + XED_ICLASS_JBE, + XED_ICLASS_JCXZ, + XED_ICLASS_JECXZ, + XED_ICLASS_JL, + XED_ICLASS_JLE, + XED_ICLASS_JMP, + XED_ICLASS_JMP_FAR, + XED_ICLASS_JNB, + XED_ICLASS_JNBE, + XED_ICLASS_JNL, + XED_ICLASS_JNLE, + XED_ICLASS_JNO, + XED_ICLASS_JNP, + XED_ICLASS_JNS, + XED_ICLASS_JNZ, + XED_ICLASS_JO, + XED_ICLASS_JP, + XED_ICLASS_JRCXZ, + XED_ICLASS_JS, + XED_ICLASS_JZ, + XED_ICLASS_KADDB, + XED_ICLASS_KADDD, + XED_ICLASS_KADDQ, + XED_ICLASS_KADDW, + XED_ICLASS_KANDB, + XED_ICLASS_KANDD, + XED_ICLASS_KANDNB, + XED_ICLASS_KANDND, + XED_ICLASS_KANDNQ, + XED_ICLASS_KANDNW, + XED_ICLASS_KANDQ, + XED_ICLASS_KANDW, + XED_ICLASS_KMOVB, + XED_ICLASS_KMOVD, + XED_ICLASS_KMOVQ, + XED_ICLASS_KMOVW, + XED_ICLASS_KNOTB, + XED_ICLASS_KNOTD, + XED_ICLASS_KNOTQ, + XED_ICLASS_KNOTW, + XED_ICLASS_KORB, + XED_ICLASS_KORD, + XED_ICLASS_KORQ, + XED_ICLASS_KORTESTB, + XED_ICLASS_KORTESTD, + XED_ICLASS_KORTESTQ, + XED_ICLASS_KORTESTW, + XED_ICLASS_KORW, + XED_ICLASS_KSHIFTLB, + XED_ICLASS_KSHIFTLD, + XED_ICLASS_KSHIFTLQ, + XED_ICLASS_KSHIFTLW, + XED_ICLASS_KSHIFTRB, + XED_ICLASS_KSHIFTRD, + XED_ICLASS_KSHIFTRQ, + XED_ICLASS_KSHIFTRW, + XED_ICLASS_KTESTB, + XED_ICLASS_KTESTD, + XED_ICLASS_KTESTQ, + XED_ICLASS_KTESTW, + XED_ICLASS_KUNPCKBW, + XED_ICLASS_KUNPCKDQ, + XED_ICLASS_KUNPCKWD, + XED_ICLASS_KXNORB, + XED_ICLASS_KXNORD, + XED_ICLASS_KXNORQ, + XED_ICLASS_KXNORW, + XED_ICLASS_KXORB, + XED_ICLASS_KXORD, + XED_ICLASS_KXORQ, + XED_ICLASS_KXORW, + XED_ICLASS_LAHF, + XED_ICLASS_LAR, + XED_ICLASS_LDDQU, + XED_ICLASS_LDMXCSR, + XED_ICLASS_LDS, + XED_ICLASS_LDTILECFG, + XED_ICLASS_LEA, + XED_ICLASS_LEAVE, + XED_ICLASS_LES, + XED_ICLASS_LFENCE, + XED_ICLASS_LFS, + XED_ICLASS_LGDT, + XED_ICLASS_LGS, + XED_ICLASS_LIDT, + XED_ICLASS_LLDT, + XED_ICLASS_LLWPCB, + XED_ICLASS_LMSW, + XED_ICLASS_LOADIWKEY, + XED_ICLASS_LODSB, + XED_ICLASS_LODSD, + XED_ICLASS_LODSQ, + XED_ICLASS_LODSW, + XED_ICLASS_LOOP, + XED_ICLASS_LOOPE, + XED_ICLASS_LOOPNE, + XED_ICLASS_LSL, + XED_ICLASS_LSS, + XED_ICLASS_LTR, + XED_ICLASS_LWPINS, + XED_ICLASS_LWPVAL, + XED_ICLASS_LZCNT, + XED_ICLASS_MASKMOVDQU, + XED_ICLASS_MASKMOVQ, + XED_ICLASS_MAXPD, + XED_ICLASS_MAXPS, + XED_ICLASS_MAXSD, + XED_ICLASS_MAXSS, + XED_ICLASS_MCOMMIT, + XED_ICLASS_MFENCE, + XED_ICLASS_MINPD, + XED_ICLASS_MINPS, + XED_ICLASS_MINSD, + XED_ICLASS_MINSS, + XED_ICLASS_MONITOR, + XED_ICLASS_MONITORX, + XED_ICLASS_MOV, + XED_ICLASS_MOVAPD, + XED_ICLASS_MOVAPS, + XED_ICLASS_MOVBE, + XED_ICLASS_MOVD, + XED_ICLASS_MOVDDUP, + XED_ICLASS_MOVDIR64B, + XED_ICLASS_MOVDIRI, + XED_ICLASS_MOVDQ2Q, + XED_ICLASS_MOVDQA, + XED_ICLASS_MOVDQU, + XED_ICLASS_MOVHLPS, + XED_ICLASS_MOVHPD, + XED_ICLASS_MOVHPS, + XED_ICLASS_MOVLHPS, + XED_ICLASS_MOVLPD, + XED_ICLASS_MOVLPS, + XED_ICLASS_MOVMSKPD, + XED_ICLASS_MOVMSKPS, + XED_ICLASS_MOVNTDQ, + XED_ICLASS_MOVNTDQA, + XED_ICLASS_MOVNTI, + XED_ICLASS_MOVNTPD, + XED_ICLASS_MOVNTPS, + XED_ICLASS_MOVNTQ, + XED_ICLASS_MOVNTSD, + XED_ICLASS_MOVNTSS, + XED_ICLASS_MOVQ, + XED_ICLASS_MOVQ2DQ, + XED_ICLASS_MOVSB, + XED_ICLASS_MOVSD, + XED_ICLASS_MOVSD_XMM, + XED_ICLASS_MOVSHDUP, + XED_ICLASS_MOVSLDUP, + XED_ICLASS_MOVSQ, + XED_ICLASS_MOVSS, + XED_ICLASS_MOVSW, + XED_ICLASS_MOVSX, + XED_ICLASS_MOVSXD, + XED_ICLASS_MOVUPD, + XED_ICLASS_MOVUPS, + XED_ICLASS_MOVZX, + XED_ICLASS_MOV_CR, + XED_ICLASS_MOV_DR, + XED_ICLASS_MPSADBW, + XED_ICLASS_MUL, + XED_ICLASS_MULPD, + XED_ICLASS_MULPS, + XED_ICLASS_MULSD, + XED_ICLASS_MULSS, + XED_ICLASS_MULX, + XED_ICLASS_MWAIT, + XED_ICLASS_MWAITX, + XED_ICLASS_NEG, + XED_ICLASS_NEG_LOCK, + XED_ICLASS_NOP, + XED_ICLASS_NOP2, + XED_ICLASS_NOP3, + XED_ICLASS_NOP4, + XED_ICLASS_NOP5, + XED_ICLASS_NOP6, + XED_ICLASS_NOP7, + XED_ICLASS_NOP8, + XED_ICLASS_NOP9, + XED_ICLASS_NOT, + XED_ICLASS_NOT_LOCK, + XED_ICLASS_OR, + XED_ICLASS_ORPD, + XED_ICLASS_ORPS, + XED_ICLASS_OR_LOCK, + XED_ICLASS_OUT, + XED_ICLASS_OUTSB, + XED_ICLASS_OUTSD, + XED_ICLASS_OUTSW, + XED_ICLASS_PABSB, + XED_ICLASS_PABSD, + XED_ICLASS_PABSW, + XED_ICLASS_PACKSSDW, + XED_ICLASS_PACKSSWB, + XED_ICLASS_PACKUSDW, + XED_ICLASS_PACKUSWB, + XED_ICLASS_PADDB, + XED_ICLASS_PADDD, + XED_ICLASS_PADDQ, + XED_ICLASS_PADDSB, + XED_ICLASS_PADDSW, + XED_ICLASS_PADDUSB, + XED_ICLASS_PADDUSW, + XED_ICLASS_PADDW, + XED_ICLASS_PALIGNR, + XED_ICLASS_PAND, + XED_ICLASS_PANDN, + XED_ICLASS_PAUSE, + XED_ICLASS_PAVGB, + XED_ICLASS_PAVGUSB, + XED_ICLASS_PAVGW, + XED_ICLASS_PBLENDVB, + XED_ICLASS_PBLENDW, + XED_ICLASS_PCLMULQDQ, + XED_ICLASS_PCMPEQB, + XED_ICLASS_PCMPEQD, + XED_ICLASS_PCMPEQQ, + XED_ICLASS_PCMPEQW, + XED_ICLASS_PCMPESTRI, + XED_ICLASS_PCMPESTRI64, + XED_ICLASS_PCMPESTRM, + XED_ICLASS_PCMPESTRM64, + XED_ICLASS_PCMPGTB, + XED_ICLASS_PCMPGTD, + XED_ICLASS_PCMPGTQ, + XED_ICLASS_PCMPGTW, + XED_ICLASS_PCMPISTRI, + XED_ICLASS_PCMPISTRI64, + XED_ICLASS_PCMPISTRM, + XED_ICLASS_PCONFIG, + XED_ICLASS_PDEP, + XED_ICLASS_PEXT, + XED_ICLASS_PEXTRB, + XED_ICLASS_PEXTRD, + XED_ICLASS_PEXTRQ, + XED_ICLASS_PEXTRW, + XED_ICLASS_PEXTRW_SSE4, + XED_ICLASS_PF2ID, + XED_ICLASS_PF2IW, + XED_ICLASS_PFACC, + XED_ICLASS_PFADD, + XED_ICLASS_PFCMPEQ, + XED_ICLASS_PFCMPGE, + XED_ICLASS_PFCMPGT, + XED_ICLASS_PFMAX, + XED_ICLASS_PFMIN, + XED_ICLASS_PFMUL, + XED_ICLASS_PFNACC, + XED_ICLASS_PFPNACC, + XED_ICLASS_PFRCP, + XED_ICLASS_PFRCPIT1, + XED_ICLASS_PFRCPIT2, + XED_ICLASS_PFRSQIT1, + XED_ICLASS_PFRSQRT, + XED_ICLASS_PFSUB, + XED_ICLASS_PFSUBR, + XED_ICLASS_PHADDD, + XED_ICLASS_PHADDSW, + XED_ICLASS_PHADDW, + XED_ICLASS_PHMINPOSUW, + XED_ICLASS_PHSUBD, + XED_ICLASS_PHSUBSW, + XED_ICLASS_PHSUBW, + XED_ICLASS_PI2FD, + XED_ICLASS_PI2FW, + XED_ICLASS_PINSRB, + XED_ICLASS_PINSRD, + XED_ICLASS_PINSRQ, + XED_ICLASS_PINSRW, + XED_ICLASS_PMADDUBSW, + XED_ICLASS_PMADDWD, + XED_ICLASS_PMAXSB, + XED_ICLASS_PMAXSD, + XED_ICLASS_PMAXSW, + XED_ICLASS_PMAXUB, + XED_ICLASS_PMAXUD, + XED_ICLASS_PMAXUW, + XED_ICLASS_PMINSB, + XED_ICLASS_PMINSD, + XED_ICLASS_PMINSW, + XED_ICLASS_PMINUB, + XED_ICLASS_PMINUD, + XED_ICLASS_PMINUW, + XED_ICLASS_PMOVMSKB, + XED_ICLASS_PMOVSXBD, + XED_ICLASS_PMOVSXBQ, + XED_ICLASS_PMOVSXBW, + XED_ICLASS_PMOVSXDQ, + XED_ICLASS_PMOVSXWD, + XED_ICLASS_PMOVSXWQ, + XED_ICLASS_PMOVZXBD, + XED_ICLASS_PMOVZXBQ, + XED_ICLASS_PMOVZXBW, + XED_ICLASS_PMOVZXDQ, + XED_ICLASS_PMOVZXWD, + XED_ICLASS_PMOVZXWQ, + XED_ICLASS_PMULDQ, + XED_ICLASS_PMULHRSW, + XED_ICLASS_PMULHRW, + XED_ICLASS_PMULHUW, + XED_ICLASS_PMULHW, + XED_ICLASS_PMULLD, + XED_ICLASS_PMULLW, + XED_ICLASS_PMULUDQ, + XED_ICLASS_POP, + XED_ICLASS_POPA, + XED_ICLASS_POPAD, + XED_ICLASS_POPCNT, + XED_ICLASS_POPF, + XED_ICLASS_POPFD, + XED_ICLASS_POPFQ, + XED_ICLASS_POR, + XED_ICLASS_PREFETCHNTA, + XED_ICLASS_PREFETCHT0, + XED_ICLASS_PREFETCHT1, + XED_ICLASS_PREFETCHT2, + XED_ICLASS_PREFETCHW, + XED_ICLASS_PREFETCHWT1, + XED_ICLASS_PREFETCH_EXCLUSIVE, + XED_ICLASS_PREFETCH_RESERVED, + XED_ICLASS_PSADBW, + XED_ICLASS_PSHUFB, + XED_ICLASS_PSHUFD, + XED_ICLASS_PSHUFHW, + XED_ICLASS_PSHUFLW, + XED_ICLASS_PSHUFW, + XED_ICLASS_PSIGNB, + XED_ICLASS_PSIGND, + XED_ICLASS_PSIGNW, + XED_ICLASS_PSLLD, + XED_ICLASS_PSLLDQ, + XED_ICLASS_PSLLQ, + XED_ICLASS_PSLLW, + XED_ICLASS_PSMASH, + XED_ICLASS_PSRAD, + XED_ICLASS_PSRAW, + XED_ICLASS_PSRLD, + XED_ICLASS_PSRLDQ, + XED_ICLASS_PSRLQ, + XED_ICLASS_PSRLW, + XED_ICLASS_PSUBB, + XED_ICLASS_PSUBD, + XED_ICLASS_PSUBQ, + XED_ICLASS_PSUBSB, + XED_ICLASS_PSUBSW, + XED_ICLASS_PSUBUSB, + XED_ICLASS_PSUBUSW, + XED_ICLASS_PSUBW, + XED_ICLASS_PSWAPD, + XED_ICLASS_PTEST, + XED_ICLASS_PTWRITE, + XED_ICLASS_PUNPCKHBW, + XED_ICLASS_PUNPCKHDQ, + XED_ICLASS_PUNPCKHQDQ, + XED_ICLASS_PUNPCKHWD, + XED_ICLASS_PUNPCKLBW, + XED_ICLASS_PUNPCKLDQ, + XED_ICLASS_PUNPCKLQDQ, + XED_ICLASS_PUNPCKLWD, + XED_ICLASS_PUSH, + XED_ICLASS_PUSHA, + XED_ICLASS_PUSHAD, + XED_ICLASS_PUSHF, + XED_ICLASS_PUSHFD, + XED_ICLASS_PUSHFQ, + XED_ICLASS_PVALIDATE, + XED_ICLASS_PXOR, + XED_ICLASS_RCL, + XED_ICLASS_RCPPS, + XED_ICLASS_RCPSS, + XED_ICLASS_RCR, + XED_ICLASS_RDFSBASE, + XED_ICLASS_RDGSBASE, + XED_ICLASS_RDMSR, + XED_ICLASS_RDPID, + XED_ICLASS_RDPKRU, + XED_ICLASS_RDPMC, + XED_ICLASS_RDPRU, + XED_ICLASS_RDRAND, + XED_ICLASS_RDSEED, + XED_ICLASS_RDSSPD, + XED_ICLASS_RDSSPQ, + XED_ICLASS_RDTSC, + XED_ICLASS_RDTSCP, + XED_ICLASS_REPE_CMPSB, + XED_ICLASS_REPE_CMPSD, + XED_ICLASS_REPE_CMPSQ, + XED_ICLASS_REPE_CMPSW, + XED_ICLASS_REPE_SCASB, + XED_ICLASS_REPE_SCASD, + XED_ICLASS_REPE_SCASQ, + XED_ICLASS_REPE_SCASW, + XED_ICLASS_REPNE_CMPSB, + XED_ICLASS_REPNE_CMPSD, + XED_ICLASS_REPNE_CMPSQ, + XED_ICLASS_REPNE_CMPSW, + XED_ICLASS_REPNE_SCASB, + XED_ICLASS_REPNE_SCASD, + XED_ICLASS_REPNE_SCASQ, + XED_ICLASS_REPNE_SCASW, + XED_ICLASS_REP_INSB, + XED_ICLASS_REP_INSD, + XED_ICLASS_REP_INSW, + XED_ICLASS_REP_LODSB, + XED_ICLASS_REP_LODSD, + XED_ICLASS_REP_LODSQ, + XED_ICLASS_REP_LODSW, + XED_ICLASS_REP_MONTMUL, + XED_ICLASS_REP_MOVSB, + XED_ICLASS_REP_MOVSD, + XED_ICLASS_REP_MOVSQ, + XED_ICLASS_REP_MOVSW, + XED_ICLASS_REP_OUTSB, + XED_ICLASS_REP_OUTSD, + XED_ICLASS_REP_OUTSW, + XED_ICLASS_REP_STOSB, + XED_ICLASS_REP_STOSD, + XED_ICLASS_REP_STOSQ, + XED_ICLASS_REP_STOSW, + XED_ICLASS_REP_XCRYPTCBC, + XED_ICLASS_REP_XCRYPTCFB, + XED_ICLASS_REP_XCRYPTCTR, + XED_ICLASS_REP_XCRYPTECB, + XED_ICLASS_REP_XCRYPTOFB, + XED_ICLASS_REP_XSHA1, + XED_ICLASS_REP_XSHA256, + XED_ICLASS_REP_XSTORE, + XED_ICLASS_RET_FAR, + XED_ICLASS_RET_NEAR, + XED_ICLASS_RMPADJUST, + XED_ICLASS_RMPUPDATE, + XED_ICLASS_ROL, + XED_ICLASS_ROR, + XED_ICLASS_RORX, + XED_ICLASS_ROUNDPD, + XED_ICLASS_ROUNDPS, + XED_ICLASS_ROUNDSD, + XED_ICLASS_ROUNDSS, + XED_ICLASS_RSM, + XED_ICLASS_RSQRTPS, + XED_ICLASS_RSQRTSS, + XED_ICLASS_RSTORSSP, + XED_ICLASS_SAHF, + XED_ICLASS_SALC, + XED_ICLASS_SAR, + XED_ICLASS_SARX, + XED_ICLASS_SAVEPREVSSP, + XED_ICLASS_SBB, + XED_ICLASS_SBB_LOCK, + XED_ICLASS_SCASB, + XED_ICLASS_SCASD, + XED_ICLASS_SCASQ, + XED_ICLASS_SCASW, + XED_ICLASS_SEAMCALL, + XED_ICLASS_SEAMOPS, + XED_ICLASS_SEAMRET, + XED_ICLASS_SENDUIPI, + XED_ICLASS_SERIALIZE, + XED_ICLASS_SETB, + XED_ICLASS_SETBE, + XED_ICLASS_SETL, + XED_ICLASS_SETLE, + XED_ICLASS_SETNB, + XED_ICLASS_SETNBE, + XED_ICLASS_SETNL, + XED_ICLASS_SETNLE, + XED_ICLASS_SETNO, + XED_ICLASS_SETNP, + XED_ICLASS_SETNS, + XED_ICLASS_SETNZ, + XED_ICLASS_SETO, + XED_ICLASS_SETP, + XED_ICLASS_SETS, + XED_ICLASS_SETSSBSY, + XED_ICLASS_SETZ, + XED_ICLASS_SFENCE, + XED_ICLASS_SGDT, + XED_ICLASS_SHA1MSG1, + XED_ICLASS_SHA1MSG2, + XED_ICLASS_SHA1NEXTE, + XED_ICLASS_SHA1RNDS4, + XED_ICLASS_SHA256MSG1, + XED_ICLASS_SHA256MSG2, + XED_ICLASS_SHA256RNDS2, + XED_ICLASS_SHL, + XED_ICLASS_SHLD, + XED_ICLASS_SHLX, + XED_ICLASS_SHR, + XED_ICLASS_SHRD, + XED_ICLASS_SHRX, + XED_ICLASS_SHUFPD, + XED_ICLASS_SHUFPS, + XED_ICLASS_SIDT, + XED_ICLASS_SKINIT, + XED_ICLASS_SLDT, + XED_ICLASS_SLWPCB, + XED_ICLASS_SMSW, + XED_ICLASS_SQRTPD, + XED_ICLASS_SQRTPS, + XED_ICLASS_SQRTSD, + XED_ICLASS_SQRTSS, + XED_ICLASS_STAC, + XED_ICLASS_STC, + XED_ICLASS_STD, + XED_ICLASS_STGI, + XED_ICLASS_STI, + XED_ICLASS_STMXCSR, + XED_ICLASS_STOSB, + XED_ICLASS_STOSD, + XED_ICLASS_STOSQ, + XED_ICLASS_STOSW, + XED_ICLASS_STR, + XED_ICLASS_STTILECFG, + XED_ICLASS_STUI, + XED_ICLASS_SUB, + XED_ICLASS_SUBPD, + XED_ICLASS_SUBPS, + XED_ICLASS_SUBSD, + XED_ICLASS_SUBSS, + XED_ICLASS_SUB_LOCK, + XED_ICLASS_SWAPGS, + XED_ICLASS_SYSCALL, + XED_ICLASS_SYSCALL_AMD, + XED_ICLASS_SYSENTER, + XED_ICLASS_SYSEXIT, + XED_ICLASS_SYSRET, + XED_ICLASS_SYSRET64, + XED_ICLASS_SYSRET_AMD, + XED_ICLASS_T1MSKC, + XED_ICLASS_TDCALL, + XED_ICLASS_TDPBF16PS, + XED_ICLASS_TDPBSSD, + XED_ICLASS_TDPBSUD, + XED_ICLASS_TDPBUSD, + XED_ICLASS_TDPBUUD, + XED_ICLASS_TEST, + XED_ICLASS_TESTUI, + XED_ICLASS_TILELOADD, + XED_ICLASS_TILELOADDT1, + XED_ICLASS_TILERELEASE, + XED_ICLASS_TILESTORED, + XED_ICLASS_TILEZERO, + XED_ICLASS_TLBSYNC, + XED_ICLASS_TPAUSE, + XED_ICLASS_TZCNT, + XED_ICLASS_TZMSK, + XED_ICLASS_UCOMISD, + XED_ICLASS_UCOMISS, + XED_ICLASS_UD0, + XED_ICLASS_UD1, + XED_ICLASS_UD2, + XED_ICLASS_UIRET, + XED_ICLASS_UMONITOR, + XED_ICLASS_UMWAIT, + XED_ICLASS_UNPCKHPD, + XED_ICLASS_UNPCKHPS, + XED_ICLASS_UNPCKLPD, + XED_ICLASS_UNPCKLPS, + XED_ICLASS_V4FMADDPS, + XED_ICLASS_V4FMADDSS, + XED_ICLASS_V4FNMADDPS, + XED_ICLASS_V4FNMADDSS, + XED_ICLASS_VADDPD, + XED_ICLASS_VADDPH, + XED_ICLASS_VADDPS, + XED_ICLASS_VADDSD, + XED_ICLASS_VADDSH, + XED_ICLASS_VADDSS, + XED_ICLASS_VADDSUBPD, + XED_ICLASS_VADDSUBPS, + XED_ICLASS_VAESDEC, + XED_ICLASS_VAESDECLAST, + XED_ICLASS_VAESENC, + XED_ICLASS_VAESENCLAST, + XED_ICLASS_VAESIMC, + XED_ICLASS_VAESKEYGENASSIST, + XED_ICLASS_VALIGND, + XED_ICLASS_VALIGNQ, + XED_ICLASS_VANDNPD, + XED_ICLASS_VANDNPS, + XED_ICLASS_VANDPD, + XED_ICLASS_VANDPS, + XED_ICLASS_VBLENDMPD, + XED_ICLASS_VBLENDMPS, + XED_ICLASS_VBLENDPD, + XED_ICLASS_VBLENDPS, + XED_ICLASS_VBLENDVPD, + XED_ICLASS_VBLENDVPS, + XED_ICLASS_VBROADCASTF128, + XED_ICLASS_VBROADCASTF32X2, + XED_ICLASS_VBROADCASTF32X4, + XED_ICLASS_VBROADCASTF32X8, + XED_ICLASS_VBROADCASTF64X2, + XED_ICLASS_VBROADCASTF64X4, + XED_ICLASS_VBROADCASTI128, + XED_ICLASS_VBROADCASTI32X2, + XED_ICLASS_VBROADCASTI32X4, + XED_ICLASS_VBROADCASTI32X8, + XED_ICLASS_VBROADCASTI64X2, + XED_ICLASS_VBROADCASTI64X4, + XED_ICLASS_VBROADCASTSD, + XED_ICLASS_VBROADCASTSS, + XED_ICLASS_VCMPPD, + XED_ICLASS_VCMPPH, + XED_ICLASS_VCMPPS, + XED_ICLASS_VCMPSD, + XED_ICLASS_VCMPSH, + XED_ICLASS_VCMPSS, + XED_ICLASS_VCOMISD, + XED_ICLASS_VCOMISH, + XED_ICLASS_VCOMISS, + XED_ICLASS_VCOMPRESSPD, + XED_ICLASS_VCOMPRESSPS, + XED_ICLASS_VCVTDQ2PD, + XED_ICLASS_VCVTDQ2PH, + XED_ICLASS_VCVTDQ2PS, + XED_ICLASS_VCVTNE2PS2BF16, + XED_ICLASS_VCVTNEPS2BF16, + XED_ICLASS_VCVTPD2DQ, + XED_ICLASS_VCVTPD2PH, + XED_ICLASS_VCVTPD2PS, + XED_ICLASS_VCVTPD2QQ, + XED_ICLASS_VCVTPD2UDQ, + XED_ICLASS_VCVTPD2UQQ, + XED_ICLASS_VCVTPH2DQ, + XED_ICLASS_VCVTPH2PD, + XED_ICLASS_VCVTPH2PS, + XED_ICLASS_VCVTPH2PSX, + XED_ICLASS_VCVTPH2QQ, + XED_ICLASS_VCVTPH2UDQ, + XED_ICLASS_VCVTPH2UQQ, + XED_ICLASS_VCVTPH2UW, + XED_ICLASS_VCVTPH2W, + XED_ICLASS_VCVTPS2DQ, + XED_ICLASS_VCVTPS2PD, + XED_ICLASS_VCVTPS2PH, + XED_ICLASS_VCVTPS2PHX, + XED_ICLASS_VCVTPS2QQ, + XED_ICLASS_VCVTPS2UDQ, + XED_ICLASS_VCVTPS2UQQ, + XED_ICLASS_VCVTQQ2PD, + XED_ICLASS_VCVTQQ2PH, + XED_ICLASS_VCVTQQ2PS, + XED_ICLASS_VCVTSD2SH, + XED_ICLASS_VCVTSD2SI, + XED_ICLASS_VCVTSD2SS, + XED_ICLASS_VCVTSD2USI, + XED_ICLASS_VCVTSH2SD, + XED_ICLASS_VCVTSH2SI, + XED_ICLASS_VCVTSH2SS, + XED_ICLASS_VCVTSH2USI, + XED_ICLASS_VCVTSI2SD, + XED_ICLASS_VCVTSI2SH, + XED_ICLASS_VCVTSI2SS, + XED_ICLASS_VCVTSS2SD, + XED_ICLASS_VCVTSS2SH, + XED_ICLASS_VCVTSS2SI, + XED_ICLASS_VCVTSS2USI, + XED_ICLASS_VCVTTPD2DQ, + XED_ICLASS_VCVTTPD2QQ, + XED_ICLASS_VCVTTPD2UDQ, + XED_ICLASS_VCVTTPD2UQQ, + XED_ICLASS_VCVTTPH2DQ, + XED_ICLASS_VCVTTPH2QQ, + XED_ICLASS_VCVTTPH2UDQ, + XED_ICLASS_VCVTTPH2UQQ, + XED_ICLASS_VCVTTPH2UW, + XED_ICLASS_VCVTTPH2W, + XED_ICLASS_VCVTTPS2DQ, + XED_ICLASS_VCVTTPS2QQ, + XED_ICLASS_VCVTTPS2UDQ, + XED_ICLASS_VCVTTPS2UQQ, + XED_ICLASS_VCVTTSD2SI, + XED_ICLASS_VCVTTSD2USI, + XED_ICLASS_VCVTTSH2SI, + XED_ICLASS_VCVTTSH2USI, + XED_ICLASS_VCVTTSS2SI, + XED_ICLASS_VCVTTSS2USI, + XED_ICLASS_VCVTUDQ2PD, + XED_ICLASS_VCVTUDQ2PH, + XED_ICLASS_VCVTUDQ2PS, + XED_ICLASS_VCVTUQQ2PD, + XED_ICLASS_VCVTUQQ2PH, + XED_ICLASS_VCVTUQQ2PS, + XED_ICLASS_VCVTUSI2SD, + XED_ICLASS_VCVTUSI2SH, + XED_ICLASS_VCVTUSI2SS, + XED_ICLASS_VCVTUW2PH, + XED_ICLASS_VCVTW2PH, + XED_ICLASS_VDBPSADBW, + XED_ICLASS_VDIVPD, + XED_ICLASS_VDIVPH, + XED_ICLASS_VDIVPS, + XED_ICLASS_VDIVSD, + XED_ICLASS_VDIVSH, + XED_ICLASS_VDIVSS, + XED_ICLASS_VDPBF16PS, + XED_ICLASS_VDPPD, + XED_ICLASS_VDPPS, + XED_ICLASS_VERR, + XED_ICLASS_VERW, + XED_ICLASS_VEXP2PD, + XED_ICLASS_VEXP2PS, + XED_ICLASS_VEXPANDPD, + XED_ICLASS_VEXPANDPS, + XED_ICLASS_VEXTRACTF128, + XED_ICLASS_VEXTRACTF32X4, + XED_ICLASS_VEXTRACTF32X8, + XED_ICLASS_VEXTRACTF64X2, + XED_ICLASS_VEXTRACTF64X4, + XED_ICLASS_VEXTRACTI128, + XED_ICLASS_VEXTRACTI32X4, + XED_ICLASS_VEXTRACTI32X8, + XED_ICLASS_VEXTRACTI64X2, + XED_ICLASS_VEXTRACTI64X4, + XED_ICLASS_VEXTRACTPS, + XED_ICLASS_VFCMADDCPH, + XED_ICLASS_VFCMADDCSH, + XED_ICLASS_VFCMULCPH, + XED_ICLASS_VFCMULCSH, + XED_ICLASS_VFIXUPIMMPD, + XED_ICLASS_VFIXUPIMMPS, + XED_ICLASS_VFIXUPIMMSD, + XED_ICLASS_VFIXUPIMMSS, + XED_ICLASS_VFMADD132PD, + XED_ICLASS_VFMADD132PH, + XED_ICLASS_VFMADD132PS, + XED_ICLASS_VFMADD132SD, + XED_ICLASS_VFMADD132SH, + XED_ICLASS_VFMADD132SS, + XED_ICLASS_VFMADD213PD, + XED_ICLASS_VFMADD213PH, + XED_ICLASS_VFMADD213PS, + XED_ICLASS_VFMADD213SD, + XED_ICLASS_VFMADD213SH, + XED_ICLASS_VFMADD213SS, + XED_ICLASS_VFMADD231PD, + XED_ICLASS_VFMADD231PH, + XED_ICLASS_VFMADD231PS, + XED_ICLASS_VFMADD231SD, + XED_ICLASS_VFMADD231SH, + XED_ICLASS_VFMADD231SS, + XED_ICLASS_VFMADDCPH, + XED_ICLASS_VFMADDCSH, + XED_ICLASS_VFMADDPD, + XED_ICLASS_VFMADDPS, + XED_ICLASS_VFMADDSD, + XED_ICLASS_VFMADDSS, + XED_ICLASS_VFMADDSUB132PD, + XED_ICLASS_VFMADDSUB132PH, + XED_ICLASS_VFMADDSUB132PS, + XED_ICLASS_VFMADDSUB213PD, + XED_ICLASS_VFMADDSUB213PH, + XED_ICLASS_VFMADDSUB213PS, + XED_ICLASS_VFMADDSUB231PD, + XED_ICLASS_VFMADDSUB231PH, + XED_ICLASS_VFMADDSUB231PS, + XED_ICLASS_VFMADDSUBPD, + XED_ICLASS_VFMADDSUBPS, + XED_ICLASS_VFMSUB132PD, + XED_ICLASS_VFMSUB132PH, + XED_ICLASS_VFMSUB132PS, + XED_ICLASS_VFMSUB132SD, + XED_ICLASS_VFMSUB132SH, + XED_ICLASS_VFMSUB132SS, + XED_ICLASS_VFMSUB213PD, + XED_ICLASS_VFMSUB213PH, + XED_ICLASS_VFMSUB213PS, + XED_ICLASS_VFMSUB213SD, + XED_ICLASS_VFMSUB213SH, + XED_ICLASS_VFMSUB213SS, + XED_ICLASS_VFMSUB231PD, + XED_ICLASS_VFMSUB231PH, + XED_ICLASS_VFMSUB231PS, + XED_ICLASS_VFMSUB231SD, + XED_ICLASS_VFMSUB231SH, + XED_ICLASS_VFMSUB231SS, + XED_ICLASS_VFMSUBADD132PD, + XED_ICLASS_VFMSUBADD132PH, + XED_ICLASS_VFMSUBADD132PS, + XED_ICLASS_VFMSUBADD213PD, + XED_ICLASS_VFMSUBADD213PH, + XED_ICLASS_VFMSUBADD213PS, + XED_ICLASS_VFMSUBADD231PD, + XED_ICLASS_VFMSUBADD231PH, + XED_ICLASS_VFMSUBADD231PS, + XED_ICLASS_VFMSUBADDPD, + XED_ICLASS_VFMSUBADDPS, + XED_ICLASS_VFMSUBPD, + XED_ICLASS_VFMSUBPS, + XED_ICLASS_VFMSUBSD, + XED_ICLASS_VFMSUBSS, + XED_ICLASS_VFMULCPH, + XED_ICLASS_VFMULCSH, + XED_ICLASS_VFNMADD132PD, + XED_ICLASS_VFNMADD132PH, + XED_ICLASS_VFNMADD132PS, + XED_ICLASS_VFNMADD132SD, + XED_ICLASS_VFNMADD132SH, + XED_ICLASS_VFNMADD132SS, + XED_ICLASS_VFNMADD213PD, + XED_ICLASS_VFNMADD213PH, + XED_ICLASS_VFNMADD213PS, + XED_ICLASS_VFNMADD213SD, + XED_ICLASS_VFNMADD213SH, + XED_ICLASS_VFNMADD213SS, + XED_ICLASS_VFNMADD231PD, + XED_ICLASS_VFNMADD231PH, + XED_ICLASS_VFNMADD231PS, + XED_ICLASS_VFNMADD231SD, + XED_ICLASS_VFNMADD231SH, + XED_ICLASS_VFNMADD231SS, + XED_ICLASS_VFNMADDPD, + XED_ICLASS_VFNMADDPS, + XED_ICLASS_VFNMADDSD, + XED_ICLASS_VFNMADDSS, + XED_ICLASS_VFNMSUB132PD, + XED_ICLASS_VFNMSUB132PH, + XED_ICLASS_VFNMSUB132PS, + XED_ICLASS_VFNMSUB132SD, + XED_ICLASS_VFNMSUB132SH, + XED_ICLASS_VFNMSUB132SS, + XED_ICLASS_VFNMSUB213PD, + XED_ICLASS_VFNMSUB213PH, + XED_ICLASS_VFNMSUB213PS, + XED_ICLASS_VFNMSUB213SD, + XED_ICLASS_VFNMSUB213SH, + XED_ICLASS_VFNMSUB213SS, + XED_ICLASS_VFNMSUB231PD, + XED_ICLASS_VFNMSUB231PH, + XED_ICLASS_VFNMSUB231PS, + XED_ICLASS_VFNMSUB231SD, + XED_ICLASS_VFNMSUB231SH, + XED_ICLASS_VFNMSUB231SS, + XED_ICLASS_VFNMSUBPD, + XED_ICLASS_VFNMSUBPS, + XED_ICLASS_VFNMSUBSD, + XED_ICLASS_VFNMSUBSS, + XED_ICLASS_VFPCLASSPD, + XED_ICLASS_VFPCLASSPH, + XED_ICLASS_VFPCLASSPS, + XED_ICLASS_VFPCLASSSD, + XED_ICLASS_VFPCLASSSH, + XED_ICLASS_VFPCLASSSS, + XED_ICLASS_VFRCZPD, + XED_ICLASS_VFRCZPS, + XED_ICLASS_VFRCZSD, + XED_ICLASS_VFRCZSS, + XED_ICLASS_VGATHERDPD, + XED_ICLASS_VGATHERDPS, + XED_ICLASS_VGATHERPF0DPD, + XED_ICLASS_VGATHERPF0DPS, + XED_ICLASS_VGATHERPF0QPD, + XED_ICLASS_VGATHERPF0QPS, + XED_ICLASS_VGATHERPF1DPD, + XED_ICLASS_VGATHERPF1DPS, + XED_ICLASS_VGATHERPF1QPD, + XED_ICLASS_VGATHERPF1QPS, + XED_ICLASS_VGATHERQPD, + XED_ICLASS_VGATHERQPS, + XED_ICLASS_VGETEXPPD, + XED_ICLASS_VGETEXPPH, + XED_ICLASS_VGETEXPPS, + XED_ICLASS_VGETEXPSD, + XED_ICLASS_VGETEXPSH, + XED_ICLASS_VGETEXPSS, + XED_ICLASS_VGETMANTPD, + XED_ICLASS_VGETMANTPH, + XED_ICLASS_VGETMANTPS, + XED_ICLASS_VGETMANTSD, + XED_ICLASS_VGETMANTSH, + XED_ICLASS_VGETMANTSS, + XED_ICLASS_VGF2P8AFFINEINVQB, + XED_ICLASS_VGF2P8AFFINEQB, + XED_ICLASS_VGF2P8MULB, + XED_ICLASS_VHADDPD, + XED_ICLASS_VHADDPS, + XED_ICLASS_VHSUBPD, + XED_ICLASS_VHSUBPS, + XED_ICLASS_VINSERTF128, + XED_ICLASS_VINSERTF32X4, + XED_ICLASS_VINSERTF32X8, + XED_ICLASS_VINSERTF64X2, + XED_ICLASS_VINSERTF64X4, + XED_ICLASS_VINSERTI128, + XED_ICLASS_VINSERTI32X4, + XED_ICLASS_VINSERTI32X8, + XED_ICLASS_VINSERTI64X2, + XED_ICLASS_VINSERTI64X4, + XED_ICLASS_VINSERTPS, + XED_ICLASS_VLDDQU, + XED_ICLASS_VLDMXCSR, + XED_ICLASS_VMASKMOVDQU, + XED_ICLASS_VMASKMOVPD, + XED_ICLASS_VMASKMOVPS, + XED_ICLASS_VMAXPD, + XED_ICLASS_VMAXPH, + XED_ICLASS_VMAXPS, + XED_ICLASS_VMAXSD, + XED_ICLASS_VMAXSH, + XED_ICLASS_VMAXSS, + XED_ICLASS_VMCALL, + XED_ICLASS_VMCLEAR, + XED_ICLASS_VMFUNC, + XED_ICLASS_VMINPD, + XED_ICLASS_VMINPH, + XED_ICLASS_VMINPS, + XED_ICLASS_VMINSD, + XED_ICLASS_VMINSH, + XED_ICLASS_VMINSS, + XED_ICLASS_VMLAUNCH, + XED_ICLASS_VMLOAD, + XED_ICLASS_VMMCALL, + XED_ICLASS_VMOVAPD, + XED_ICLASS_VMOVAPS, + XED_ICLASS_VMOVD, + XED_ICLASS_VMOVDDUP, + XED_ICLASS_VMOVDQA, + XED_ICLASS_VMOVDQA32, + XED_ICLASS_VMOVDQA64, + XED_ICLASS_VMOVDQU, + XED_ICLASS_VMOVDQU16, + XED_ICLASS_VMOVDQU32, + XED_ICLASS_VMOVDQU64, + XED_ICLASS_VMOVDQU8, + XED_ICLASS_VMOVHLPS, + XED_ICLASS_VMOVHPD, + XED_ICLASS_VMOVHPS, + XED_ICLASS_VMOVLHPS, + XED_ICLASS_VMOVLPD, + XED_ICLASS_VMOVLPS, + XED_ICLASS_VMOVMSKPD, + XED_ICLASS_VMOVMSKPS, + XED_ICLASS_VMOVNTDQ, + XED_ICLASS_VMOVNTDQA, + XED_ICLASS_VMOVNTPD, + XED_ICLASS_VMOVNTPS, + XED_ICLASS_VMOVQ, + XED_ICLASS_VMOVSD, + XED_ICLASS_VMOVSH, + XED_ICLASS_VMOVSHDUP, + XED_ICLASS_VMOVSLDUP, + XED_ICLASS_VMOVSS, + XED_ICLASS_VMOVUPD, + XED_ICLASS_VMOVUPS, + XED_ICLASS_VMOVW, + XED_ICLASS_VMPSADBW, + XED_ICLASS_VMPTRLD, + XED_ICLASS_VMPTRST, + XED_ICLASS_VMREAD, + XED_ICLASS_VMRESUME, + XED_ICLASS_VMRUN, + XED_ICLASS_VMSAVE, + XED_ICLASS_VMULPD, + XED_ICLASS_VMULPH, + XED_ICLASS_VMULPS, + XED_ICLASS_VMULSD, + XED_ICLASS_VMULSH, + XED_ICLASS_VMULSS, + XED_ICLASS_VMWRITE, + XED_ICLASS_VMXOFF, + XED_ICLASS_VMXON, + XED_ICLASS_VORPD, + XED_ICLASS_VORPS, + XED_ICLASS_VP2INTERSECTD, + XED_ICLASS_VP2INTERSECTQ, + XED_ICLASS_VP4DPWSSD, + XED_ICLASS_VP4DPWSSDS, + XED_ICLASS_VPABSB, + XED_ICLASS_VPABSD, + XED_ICLASS_VPABSQ, + XED_ICLASS_VPABSW, + XED_ICLASS_VPACKSSDW, + XED_ICLASS_VPACKSSWB, + XED_ICLASS_VPACKUSDW, + XED_ICLASS_VPACKUSWB, + XED_ICLASS_VPADDB, + XED_ICLASS_VPADDD, + XED_ICLASS_VPADDQ, + XED_ICLASS_VPADDSB, + XED_ICLASS_VPADDSW, + XED_ICLASS_VPADDUSB, + XED_ICLASS_VPADDUSW, + XED_ICLASS_VPADDW, + XED_ICLASS_VPALIGNR, + XED_ICLASS_VPAND, + XED_ICLASS_VPANDD, + XED_ICLASS_VPANDN, + XED_ICLASS_VPANDND, + XED_ICLASS_VPANDNQ, + XED_ICLASS_VPANDQ, + XED_ICLASS_VPAVGB, + XED_ICLASS_VPAVGW, + XED_ICLASS_VPBLENDD, + XED_ICLASS_VPBLENDMB, + XED_ICLASS_VPBLENDMD, + XED_ICLASS_VPBLENDMQ, + XED_ICLASS_VPBLENDMW, + XED_ICLASS_VPBLENDVB, + XED_ICLASS_VPBLENDW, + XED_ICLASS_VPBROADCASTB, + XED_ICLASS_VPBROADCASTD, + XED_ICLASS_VPBROADCASTMB2Q, + XED_ICLASS_VPBROADCASTMW2D, + XED_ICLASS_VPBROADCASTQ, + XED_ICLASS_VPBROADCASTW, + XED_ICLASS_VPCLMULQDQ, + XED_ICLASS_VPCMOV, + XED_ICLASS_VPCMPB, + XED_ICLASS_VPCMPD, + XED_ICLASS_VPCMPEQB, + XED_ICLASS_VPCMPEQD, + XED_ICLASS_VPCMPEQQ, + XED_ICLASS_VPCMPEQW, + XED_ICLASS_VPCMPESTRI, + XED_ICLASS_VPCMPESTRI64, + XED_ICLASS_VPCMPESTRM, + XED_ICLASS_VPCMPESTRM64, + XED_ICLASS_VPCMPGTB, + XED_ICLASS_VPCMPGTD, + XED_ICLASS_VPCMPGTQ, + XED_ICLASS_VPCMPGTW, + XED_ICLASS_VPCMPISTRI, + XED_ICLASS_VPCMPISTRI64, + XED_ICLASS_VPCMPISTRM, + XED_ICLASS_VPCMPQ, + XED_ICLASS_VPCMPUB, + XED_ICLASS_VPCMPUD, + XED_ICLASS_VPCMPUQ, + XED_ICLASS_VPCMPUW, + XED_ICLASS_VPCMPW, + XED_ICLASS_VPCOMB, + XED_ICLASS_VPCOMD, + XED_ICLASS_VPCOMPRESSB, + XED_ICLASS_VPCOMPRESSD, + XED_ICLASS_VPCOMPRESSQ, + XED_ICLASS_VPCOMPRESSW, + XED_ICLASS_VPCOMQ, + XED_ICLASS_VPCOMUB, + XED_ICLASS_VPCOMUD, + XED_ICLASS_VPCOMUQ, + XED_ICLASS_VPCOMUW, + XED_ICLASS_VPCOMW, + XED_ICLASS_VPCONFLICTD, + XED_ICLASS_VPCONFLICTQ, + XED_ICLASS_VPDPBUSD, + XED_ICLASS_VPDPBUSDS, + XED_ICLASS_VPDPWSSD, + XED_ICLASS_VPDPWSSDS, + XED_ICLASS_VPERM2F128, + XED_ICLASS_VPERM2I128, + XED_ICLASS_VPERMB, + XED_ICLASS_VPERMD, + XED_ICLASS_VPERMI2B, + XED_ICLASS_VPERMI2D, + XED_ICLASS_VPERMI2PD, + XED_ICLASS_VPERMI2PS, + XED_ICLASS_VPERMI2Q, + XED_ICLASS_VPERMI2W, + XED_ICLASS_VPERMIL2PD, + XED_ICLASS_VPERMIL2PS, + XED_ICLASS_VPERMILPD, + XED_ICLASS_VPERMILPS, + XED_ICLASS_VPERMPD, + XED_ICLASS_VPERMPS, + XED_ICLASS_VPERMQ, + XED_ICLASS_VPERMT2B, + XED_ICLASS_VPERMT2D, + XED_ICLASS_VPERMT2PD, + XED_ICLASS_VPERMT2PS, + XED_ICLASS_VPERMT2Q, + XED_ICLASS_VPERMT2W, + XED_ICLASS_VPERMW, + XED_ICLASS_VPEXPANDB, + XED_ICLASS_VPEXPANDD, + XED_ICLASS_VPEXPANDQ, + XED_ICLASS_VPEXPANDW, + XED_ICLASS_VPEXTRB, + XED_ICLASS_VPEXTRD, + XED_ICLASS_VPEXTRQ, + XED_ICLASS_VPEXTRW, + XED_ICLASS_VPEXTRW_C5, + XED_ICLASS_VPGATHERDD, + XED_ICLASS_VPGATHERDQ, + XED_ICLASS_VPGATHERQD, + XED_ICLASS_VPGATHERQQ, + XED_ICLASS_VPHADDBD, + XED_ICLASS_VPHADDBQ, + XED_ICLASS_VPHADDBW, + XED_ICLASS_VPHADDD, + XED_ICLASS_VPHADDDQ, + XED_ICLASS_VPHADDSW, + XED_ICLASS_VPHADDUBD, + XED_ICLASS_VPHADDUBQ, + XED_ICLASS_VPHADDUBW, + XED_ICLASS_VPHADDUDQ, + XED_ICLASS_VPHADDUWD, + XED_ICLASS_VPHADDUWQ, + XED_ICLASS_VPHADDW, + XED_ICLASS_VPHADDWD, + XED_ICLASS_VPHADDWQ, + XED_ICLASS_VPHMINPOSUW, + XED_ICLASS_VPHSUBBW, + XED_ICLASS_VPHSUBD, + XED_ICLASS_VPHSUBDQ, + XED_ICLASS_VPHSUBSW, + XED_ICLASS_VPHSUBW, + XED_ICLASS_VPHSUBWD, + XED_ICLASS_VPINSRB, + XED_ICLASS_VPINSRD, + XED_ICLASS_VPINSRQ, + XED_ICLASS_VPINSRW, + XED_ICLASS_VPLZCNTD, + XED_ICLASS_VPLZCNTQ, + XED_ICLASS_VPMACSDD, + XED_ICLASS_VPMACSDQH, + XED_ICLASS_VPMACSDQL, + XED_ICLASS_VPMACSSDD, + XED_ICLASS_VPMACSSDQH, + XED_ICLASS_VPMACSSDQL, + XED_ICLASS_VPMACSSWD, + XED_ICLASS_VPMACSSWW, + XED_ICLASS_VPMACSWD, + XED_ICLASS_VPMACSWW, + XED_ICLASS_VPMADCSSWD, + XED_ICLASS_VPMADCSWD, + XED_ICLASS_VPMADD52HUQ, + XED_ICLASS_VPMADD52LUQ, + XED_ICLASS_VPMADDUBSW, + XED_ICLASS_VPMADDWD, + XED_ICLASS_VPMASKMOVD, + XED_ICLASS_VPMASKMOVQ, + XED_ICLASS_VPMAXSB, + XED_ICLASS_VPMAXSD, + XED_ICLASS_VPMAXSQ, + XED_ICLASS_VPMAXSW, + XED_ICLASS_VPMAXUB, + XED_ICLASS_VPMAXUD, + XED_ICLASS_VPMAXUQ, + XED_ICLASS_VPMAXUW, + XED_ICLASS_VPMINSB, + XED_ICLASS_VPMINSD, + XED_ICLASS_VPMINSQ, + XED_ICLASS_VPMINSW, + XED_ICLASS_VPMINUB, + XED_ICLASS_VPMINUD, + XED_ICLASS_VPMINUQ, + XED_ICLASS_VPMINUW, + XED_ICLASS_VPMOVB2M, + XED_ICLASS_VPMOVD2M, + XED_ICLASS_VPMOVDB, + XED_ICLASS_VPMOVDW, + XED_ICLASS_VPMOVM2B, + XED_ICLASS_VPMOVM2D, + XED_ICLASS_VPMOVM2Q, + XED_ICLASS_VPMOVM2W, + XED_ICLASS_VPMOVMSKB, + XED_ICLASS_VPMOVQ2M, + XED_ICLASS_VPMOVQB, + XED_ICLASS_VPMOVQD, + XED_ICLASS_VPMOVQW, + XED_ICLASS_VPMOVSDB, + XED_ICLASS_VPMOVSDW, + XED_ICLASS_VPMOVSQB, + XED_ICLASS_VPMOVSQD, + XED_ICLASS_VPMOVSQW, + XED_ICLASS_VPMOVSWB, + XED_ICLASS_VPMOVSXBD, + XED_ICLASS_VPMOVSXBQ, + XED_ICLASS_VPMOVSXBW, + XED_ICLASS_VPMOVSXDQ, + XED_ICLASS_VPMOVSXWD, + XED_ICLASS_VPMOVSXWQ, + XED_ICLASS_VPMOVUSDB, + XED_ICLASS_VPMOVUSDW, + XED_ICLASS_VPMOVUSQB, + XED_ICLASS_VPMOVUSQD, + XED_ICLASS_VPMOVUSQW, + XED_ICLASS_VPMOVUSWB, + XED_ICLASS_VPMOVW2M, + XED_ICLASS_VPMOVWB, + XED_ICLASS_VPMOVZXBD, + XED_ICLASS_VPMOVZXBQ, + XED_ICLASS_VPMOVZXBW, + XED_ICLASS_VPMOVZXDQ, + XED_ICLASS_VPMOVZXWD, + XED_ICLASS_VPMOVZXWQ, + XED_ICLASS_VPMULDQ, + XED_ICLASS_VPMULHRSW, + XED_ICLASS_VPMULHUW, + XED_ICLASS_VPMULHW, + XED_ICLASS_VPMULLD, + XED_ICLASS_VPMULLQ, + XED_ICLASS_VPMULLW, + XED_ICLASS_VPMULTISHIFTQB, + XED_ICLASS_VPMULUDQ, + XED_ICLASS_VPOPCNTB, + XED_ICLASS_VPOPCNTD, + XED_ICLASS_VPOPCNTQ, + XED_ICLASS_VPOPCNTW, + XED_ICLASS_VPOR, + XED_ICLASS_VPORD, + XED_ICLASS_VPORQ, + XED_ICLASS_VPPERM, + XED_ICLASS_VPROLD, + XED_ICLASS_VPROLQ, + XED_ICLASS_VPROLVD, + XED_ICLASS_VPROLVQ, + XED_ICLASS_VPRORD, + XED_ICLASS_VPRORQ, + XED_ICLASS_VPRORVD, + XED_ICLASS_VPRORVQ, + XED_ICLASS_VPROTB, + XED_ICLASS_VPROTD, + XED_ICLASS_VPROTQ, + XED_ICLASS_VPROTW, + XED_ICLASS_VPSADBW, + XED_ICLASS_VPSCATTERDD, + XED_ICLASS_VPSCATTERDQ, + XED_ICLASS_VPSCATTERQD, + XED_ICLASS_VPSCATTERQQ, + XED_ICLASS_VPSHAB, + XED_ICLASS_VPSHAD, + XED_ICLASS_VPSHAQ, + XED_ICLASS_VPSHAW, + XED_ICLASS_VPSHLB, + XED_ICLASS_VPSHLD, + XED_ICLASS_VPSHLDD, + XED_ICLASS_VPSHLDQ, + XED_ICLASS_VPSHLDVD, + XED_ICLASS_VPSHLDVQ, + XED_ICLASS_VPSHLDVW, + XED_ICLASS_VPSHLDW, + XED_ICLASS_VPSHLQ, + XED_ICLASS_VPSHLW, + XED_ICLASS_VPSHRDD, + XED_ICLASS_VPSHRDQ, + XED_ICLASS_VPSHRDVD, + XED_ICLASS_VPSHRDVQ, + XED_ICLASS_VPSHRDVW, + XED_ICLASS_VPSHRDW, + XED_ICLASS_VPSHUFB, + XED_ICLASS_VPSHUFBITQMB, + XED_ICLASS_VPSHUFD, + XED_ICLASS_VPSHUFHW, + XED_ICLASS_VPSHUFLW, + XED_ICLASS_VPSIGNB, + XED_ICLASS_VPSIGND, + XED_ICLASS_VPSIGNW, + XED_ICLASS_VPSLLD, + XED_ICLASS_VPSLLDQ, + XED_ICLASS_VPSLLQ, + XED_ICLASS_VPSLLVD, + XED_ICLASS_VPSLLVQ, + XED_ICLASS_VPSLLVW, + XED_ICLASS_VPSLLW, + XED_ICLASS_VPSRAD, + XED_ICLASS_VPSRAQ, + XED_ICLASS_VPSRAVD, + XED_ICLASS_VPSRAVQ, + XED_ICLASS_VPSRAVW, + XED_ICLASS_VPSRAW, + XED_ICLASS_VPSRLD, + XED_ICLASS_VPSRLDQ, + XED_ICLASS_VPSRLQ, + XED_ICLASS_VPSRLVD, + XED_ICLASS_VPSRLVQ, + XED_ICLASS_VPSRLVW, + XED_ICLASS_VPSRLW, + XED_ICLASS_VPSUBB, + XED_ICLASS_VPSUBD, + XED_ICLASS_VPSUBQ, + XED_ICLASS_VPSUBSB, + XED_ICLASS_VPSUBSW, + XED_ICLASS_VPSUBUSB, + XED_ICLASS_VPSUBUSW, + XED_ICLASS_VPSUBW, + XED_ICLASS_VPTERNLOGD, + XED_ICLASS_VPTERNLOGQ, + XED_ICLASS_VPTEST, + XED_ICLASS_VPTESTMB, + XED_ICLASS_VPTESTMD, + XED_ICLASS_VPTESTMQ, + XED_ICLASS_VPTESTMW, + XED_ICLASS_VPTESTNMB, + XED_ICLASS_VPTESTNMD, + XED_ICLASS_VPTESTNMQ, + XED_ICLASS_VPTESTNMW, + XED_ICLASS_VPUNPCKHBW, + XED_ICLASS_VPUNPCKHDQ, + XED_ICLASS_VPUNPCKHQDQ, + XED_ICLASS_VPUNPCKHWD, + XED_ICLASS_VPUNPCKLBW, + XED_ICLASS_VPUNPCKLDQ, + XED_ICLASS_VPUNPCKLQDQ, + XED_ICLASS_VPUNPCKLWD, + XED_ICLASS_VPXOR, + XED_ICLASS_VPXORD, + XED_ICLASS_VPXORQ, + XED_ICLASS_VRANGEPD, + XED_ICLASS_VRANGEPS, + XED_ICLASS_VRANGESD, + XED_ICLASS_VRANGESS, + XED_ICLASS_VRCP14PD, + XED_ICLASS_VRCP14PS, + XED_ICLASS_VRCP14SD, + XED_ICLASS_VRCP14SS, + XED_ICLASS_VRCP28PD, + XED_ICLASS_VRCP28PS, + XED_ICLASS_VRCP28SD, + XED_ICLASS_VRCP28SS, + XED_ICLASS_VRCPPH, + XED_ICLASS_VRCPPS, + XED_ICLASS_VRCPSH, + XED_ICLASS_VRCPSS, + XED_ICLASS_VREDUCEPD, + XED_ICLASS_VREDUCEPH, + XED_ICLASS_VREDUCEPS, + XED_ICLASS_VREDUCESD, + XED_ICLASS_VREDUCESH, + XED_ICLASS_VREDUCESS, + XED_ICLASS_VRNDSCALEPD, + XED_ICLASS_VRNDSCALEPH, + XED_ICLASS_VRNDSCALEPS, + XED_ICLASS_VRNDSCALESD, + XED_ICLASS_VRNDSCALESH, + XED_ICLASS_VRNDSCALESS, + XED_ICLASS_VROUNDPD, + XED_ICLASS_VROUNDPS, + XED_ICLASS_VROUNDSD, + XED_ICLASS_VROUNDSS, + XED_ICLASS_VRSQRT14PD, + XED_ICLASS_VRSQRT14PS, + XED_ICLASS_VRSQRT14SD, + XED_ICLASS_VRSQRT14SS, + XED_ICLASS_VRSQRT28PD, + XED_ICLASS_VRSQRT28PS, + XED_ICLASS_VRSQRT28SD, + XED_ICLASS_VRSQRT28SS, + XED_ICLASS_VRSQRTPH, + XED_ICLASS_VRSQRTPS, + XED_ICLASS_VRSQRTSH, + XED_ICLASS_VRSQRTSS, + XED_ICLASS_VSCALEFPD, + XED_ICLASS_VSCALEFPH, + XED_ICLASS_VSCALEFPS, + XED_ICLASS_VSCALEFSD, + XED_ICLASS_VSCALEFSH, + XED_ICLASS_VSCALEFSS, + XED_ICLASS_VSCATTERDPD, + XED_ICLASS_VSCATTERDPS, + XED_ICLASS_VSCATTERPF0DPD, + XED_ICLASS_VSCATTERPF0DPS, + XED_ICLASS_VSCATTERPF0QPD, + XED_ICLASS_VSCATTERPF0QPS, + XED_ICLASS_VSCATTERPF1DPD, + XED_ICLASS_VSCATTERPF1DPS, + XED_ICLASS_VSCATTERPF1QPD, + XED_ICLASS_VSCATTERPF1QPS, + XED_ICLASS_VSCATTERQPD, + XED_ICLASS_VSCATTERQPS, + XED_ICLASS_VSHUFF32X4, + XED_ICLASS_VSHUFF64X2, + XED_ICLASS_VSHUFI32X4, + XED_ICLASS_VSHUFI64X2, + XED_ICLASS_VSHUFPD, + XED_ICLASS_VSHUFPS, + XED_ICLASS_VSQRTPD, + XED_ICLASS_VSQRTPH, + XED_ICLASS_VSQRTPS, + XED_ICLASS_VSQRTSD, + XED_ICLASS_VSQRTSH, + XED_ICLASS_VSQRTSS, + XED_ICLASS_VSTMXCSR, + XED_ICLASS_VSUBPD, + XED_ICLASS_VSUBPH, + XED_ICLASS_VSUBPS, + XED_ICLASS_VSUBSD, + XED_ICLASS_VSUBSH, + XED_ICLASS_VSUBSS, + XED_ICLASS_VTESTPD, + XED_ICLASS_VTESTPS, + XED_ICLASS_VUCOMISD, + XED_ICLASS_VUCOMISH, + XED_ICLASS_VUCOMISS, + XED_ICLASS_VUNPCKHPD, + XED_ICLASS_VUNPCKHPS, + XED_ICLASS_VUNPCKLPD, + XED_ICLASS_VUNPCKLPS, + XED_ICLASS_VXORPD, + XED_ICLASS_VXORPS, + XED_ICLASS_VZEROALL, + XED_ICLASS_VZEROUPPER, + XED_ICLASS_WBINVD, + XED_ICLASS_WBNOINVD, + XED_ICLASS_WRFSBASE, + XED_ICLASS_WRGSBASE, + XED_ICLASS_WRMSR, + XED_ICLASS_WRPKRU, + XED_ICLASS_WRSSD, + XED_ICLASS_WRSSQ, + XED_ICLASS_WRUSSD, + XED_ICLASS_WRUSSQ, + XED_ICLASS_XABORT, + XED_ICLASS_XADD, + XED_ICLASS_XADD_LOCK, + XED_ICLASS_XBEGIN, + XED_ICLASS_XCHG, + XED_ICLASS_XEND, + XED_ICLASS_XGETBV, + XED_ICLASS_XLAT, + XED_ICLASS_XOR, + XED_ICLASS_XORPD, + XED_ICLASS_XORPS, + XED_ICLASS_XOR_LOCK, + XED_ICLASS_XRESLDTRK, + XED_ICLASS_XRSTOR, + XED_ICLASS_XRSTOR64, + XED_ICLASS_XRSTORS, + XED_ICLASS_XRSTORS64, + XED_ICLASS_XSAVE, + XED_ICLASS_XSAVE64, + XED_ICLASS_XSAVEC, + XED_ICLASS_XSAVEC64, + XED_ICLASS_XSAVEOPT, + XED_ICLASS_XSAVEOPT64, + XED_ICLASS_XSAVES, + XED_ICLASS_XSAVES64, + XED_ICLASS_XSETBV, + XED_ICLASS_XSTORE, + XED_ICLASS_XSUSLDTRK, + XED_ICLASS_XTEST, + XED_ICLASS_LAST +} xed_iclass_enum_t; + +/// This converts strings to #xed_iclass_enum_t types. +/// @param s A C-string. +/// @return #xed_iclass_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_iclass_enum_t str2xed_iclass_enum_t(const char* s); +/// This converts strings to #xed_iclass_enum_t types. +/// @param p An enumeration element of type xed_iclass_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_iclass_enum_t2str(const xed_iclass_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_iclass_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_iclass_enum_t xed_iclass_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-iclass-enum.txt b/CodeVirtualizer/build/obj/xed-iclass-enum.txt new file mode 100644 index 0000000..f2aa48f --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iclass-enum.txt @@ -0,0 +1,1774 @@ +# @file xed-iclass-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-iclass-enum.c +hfn xed-iclass-enum.h +typename xed_iclass_enum_t +prefix XED_ICLASS_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +AAA +AAD +AAM +AAS +ADC +ADCX +ADC_LOCK +ADD +ADDPD +ADDPS +ADDSD +ADDSS +ADDSUBPD +ADDSUBPS +ADD_LOCK +ADOX +AESDEC +AESDEC128KL +AESDEC256KL +AESDECLAST +AESDECWIDE128KL +AESDECWIDE256KL +AESENC +AESENC128KL +AESENC256KL +AESENCLAST +AESENCWIDE128KL +AESENCWIDE256KL +AESIMC +AESKEYGENASSIST +AND +ANDN +ANDNPD +ANDNPS +ANDPD +ANDPS +AND_LOCK +ARPL +BEXTR +BEXTR_XOP +BLCFILL +BLCI +BLCIC +BLCMSK +BLCS +BLENDPD +BLENDPS +BLENDVPD +BLENDVPS +BLSFILL +BLSI +BLSIC +BLSMSK +BLSR +BNDCL +BNDCN +BNDCU +BNDLDX +BNDMK +BNDMOV +BNDSTX +BOUND +BSF +BSR +BSWAP +BT +BTC +BTC_LOCK +BTR +BTR_LOCK +BTS +BTS_LOCK +BZHI +CALL_FAR +CALL_NEAR +CBW +CDQ +CDQE +CLAC +CLC +CLD +CLDEMOTE +CLFLUSH +CLFLUSHOPT +CLGI +CLI +CLRSSBSY +CLTS +CLUI +CLWB +CLZERO +CMC +CMOVB +CMOVBE +CMOVL +CMOVLE +CMOVNB +CMOVNBE +CMOVNL +CMOVNLE +CMOVNO +CMOVNP +CMOVNS +CMOVNZ +CMOVO +CMOVP +CMOVS +CMOVZ +CMP +CMPPD +CMPPS +CMPSB +CMPSD +CMPSD_XMM +CMPSQ +CMPSS +CMPSW +CMPXCHG +CMPXCHG16B +CMPXCHG16B_LOCK +CMPXCHG8B +CMPXCHG8B_LOCK +CMPXCHG_LOCK +COMISD +COMISS +CPUID +CQO +CRC32 +CVTDQ2PD +CVTDQ2PS +CVTPD2DQ +CVTPD2PI +CVTPD2PS +CVTPI2PD +CVTPI2PS +CVTPS2DQ +CVTPS2PD +CVTPS2PI +CVTSD2SI +CVTSD2SS +CVTSI2SD +CVTSI2SS +CVTSS2SD +CVTSS2SI +CVTTPD2DQ +CVTTPD2PI +CVTTPS2DQ +CVTTPS2PI +CVTTSD2SI +CVTTSS2SI +CWD +CWDE +DAA +DAS +DEC +DEC_LOCK +DIV +DIVPD +DIVPS +DIVSD +DIVSS +DPPD +DPPS +EMMS +ENCLS +ENCLU +ENCLV +ENCODEKEY128 +ENCODEKEY256 +ENDBR32 +ENDBR64 +ENQCMD +ENQCMDS +ENTER +EXTRACTPS +EXTRQ +F2XM1 +FABS +FADD +FADDP +FBLD +FBSTP +FCHS +FCMOVB +FCMOVBE +FCMOVE +FCMOVNB +FCMOVNBE +FCMOVNE +FCMOVNU +FCMOVU +FCOM +FCOMI +FCOMIP +FCOMP +FCOMPP +FCOS +FDECSTP +FDISI8087_NOP +FDIV +FDIVP +FDIVR +FDIVRP +FEMMS +FENI8087_NOP +FFREE +FFREEP +FIADD +FICOM +FICOMP +FIDIV +FIDIVR +FILD +FIMUL +FINCSTP +FIST +FISTP +FISTTP +FISUB +FISUBR +FLD +FLD1 +FLDCW +FLDENV +FLDL2E +FLDL2T +FLDLG2 +FLDLN2 +FLDPI +FLDZ +FMUL +FMULP +FNCLEX +FNINIT +FNOP +FNSAVE +FNSTCW +FNSTENV +FNSTSW +FPATAN +FPREM +FPREM1 +FPTAN +FRNDINT +FRSTOR +FSCALE +FSETPM287_NOP +FSIN +FSINCOS +FSQRT +FST +FSTP +FSTPNCE +FSUB +FSUBP +FSUBR +FSUBRP +FTST +FUCOM +FUCOMI +FUCOMIP +FUCOMP +FUCOMPP +FWAIT +FXAM +FXCH +FXRSTOR +FXRSTOR64 +FXSAVE +FXSAVE64 +FXTRACT +FYL2X +FYL2XP1 +GETSEC +GF2P8AFFINEINVQB +GF2P8AFFINEQB +GF2P8MULB +HADDPD +HADDPS +HLT +HRESET +HSUBPD +HSUBPS +IDIV +IMUL +IN +INC +INCSSPD +INCSSPQ +INC_LOCK +INSB +INSD +INSERTPS +INSERTQ +INSW +INT +INT1 +INT3 +INTO +INVD +INVEPT +INVLPG +INVLPGA +INVLPGB +INVPCID +INVVPID +IRET +IRETD +IRETQ +JB +JBE +JCXZ +JECXZ +JL +JLE +JMP +JMP_FAR +JNB +JNBE +JNL +JNLE +JNO +JNP +JNS +JNZ +JO +JP +JRCXZ +JS +JZ +KADDB +KADDD +KADDQ +KADDW +KANDB +KANDD +KANDNB +KANDND +KANDNQ +KANDNW +KANDQ +KANDW +KMOVB +KMOVD +KMOVQ +KMOVW +KNOTB +KNOTD +KNOTQ +KNOTW +KORB +KORD +KORQ +KORTESTB +KORTESTD +KORTESTQ +KORTESTW +KORW +KSHIFTLB +KSHIFTLD +KSHIFTLQ +KSHIFTLW +KSHIFTRB +KSHIFTRD +KSHIFTRQ +KSHIFTRW +KTESTB +KTESTD +KTESTQ +KTESTW +KUNPCKBW +KUNPCKDQ +KUNPCKWD +KXNORB +KXNORD +KXNORQ +KXNORW +KXORB +KXORD +KXORQ +KXORW +LAHF +LAR +LDDQU +LDMXCSR +LDS +LDTILECFG +LEA +LEAVE +LES +LFENCE +LFS +LGDT +LGS +LIDT +LLDT +LLWPCB +LMSW +LOADIWKEY +LODSB +LODSD +LODSQ +LODSW +LOOP +LOOPE +LOOPNE +LSL +LSS +LTR +LWPINS +LWPVAL +LZCNT +MASKMOVDQU +MASKMOVQ +MAXPD +MAXPS +MAXSD +MAXSS +MCOMMIT +MFENCE +MINPD +MINPS +MINSD +MINSS +MONITOR +MONITORX +MOV +MOVAPD +MOVAPS +MOVBE +MOVD +MOVDDUP +MOVDIR64B +MOVDIRI +MOVDQ2Q +MOVDQA +MOVDQU +MOVHLPS +MOVHPD +MOVHPS +MOVLHPS +MOVLPD +MOVLPS +MOVMSKPD +MOVMSKPS +MOVNTDQ +MOVNTDQA +MOVNTI +MOVNTPD +MOVNTPS +MOVNTQ +MOVNTSD +MOVNTSS +MOVQ +MOVQ2DQ +MOVSB +MOVSD +MOVSD_XMM +MOVSHDUP +MOVSLDUP +MOVSQ +MOVSS +MOVSW +MOVSX +MOVSXD +MOVUPD +MOVUPS +MOVZX +MOV_CR +MOV_DR +MPSADBW +MUL +MULPD +MULPS +MULSD +MULSS +MULX +MWAIT +MWAITX +NEG +NEG_LOCK +NOP +NOP2 +NOP3 +NOP4 +NOP5 +NOP6 +NOP7 +NOP8 +NOP9 +NOT +NOT_LOCK +OR +ORPD +ORPS +OR_LOCK +OUT +OUTSB +OUTSD +OUTSW +PABSB +PABSD +PABSW +PACKSSDW +PACKSSWB +PACKUSDW +PACKUSWB +PADDB +PADDD +PADDQ +PADDSB +PADDSW +PADDUSB +PADDUSW +PADDW +PALIGNR +PAND +PANDN +PAUSE +PAVGB +PAVGUSB +PAVGW +PBLENDVB +PBLENDW +PCLMULQDQ +PCMPEQB +PCMPEQD +PCMPEQQ +PCMPEQW +PCMPESTRI +PCMPESTRI64 +PCMPESTRM +PCMPESTRM64 +PCMPGTB +PCMPGTD +PCMPGTQ +PCMPGTW +PCMPISTRI +PCMPISTRI64 +PCMPISTRM +PCONFIG +PDEP +PEXT +PEXTRB +PEXTRD +PEXTRQ +PEXTRW +PEXTRW_SSE4 +PF2ID +PF2IW +PFACC +PFADD +PFCMPEQ +PFCMPGE +PFCMPGT +PFMAX +PFMIN +PFMUL +PFNACC +PFPNACC +PFRCP +PFRCPIT1 +PFRCPIT2 +PFRSQIT1 +PFRSQRT +PFSUB +PFSUBR +PHADDD +PHADDSW +PHADDW +PHMINPOSUW +PHSUBD +PHSUBSW +PHSUBW +PI2FD +PI2FW +PINSRB +PINSRD +PINSRQ +PINSRW +PMADDUBSW +PMADDWD +PMAXSB +PMAXSD +PMAXSW +PMAXUB +PMAXUD +PMAXUW +PMINSB +PMINSD +PMINSW +PMINUB +PMINUD +PMINUW +PMOVMSKB +PMOVSXBD +PMOVSXBQ +PMOVSXBW +PMOVSXDQ +PMOVSXWD +PMOVSXWQ +PMOVZXBD +PMOVZXBQ +PMOVZXBW +PMOVZXDQ +PMOVZXWD +PMOVZXWQ +PMULDQ +PMULHRSW +PMULHRW +PMULHUW +PMULHW +PMULLD +PMULLW +PMULUDQ +POP +POPA +POPAD +POPCNT +POPF +POPFD +POPFQ +POR +PREFETCHNTA +PREFETCHT0 +PREFETCHT1 +PREFETCHT2 +PREFETCHW +PREFETCHWT1 +PREFETCH_EXCLUSIVE +PREFETCH_RESERVED +PSADBW +PSHUFB +PSHUFD +PSHUFHW +PSHUFLW +PSHUFW +PSIGNB +PSIGND +PSIGNW +PSLLD +PSLLDQ +PSLLQ +PSLLW +PSMASH +PSRAD +PSRAW +PSRLD +PSRLDQ +PSRLQ +PSRLW +PSUBB +PSUBD +PSUBQ +PSUBSB +PSUBSW +PSUBUSB +PSUBUSW +PSUBW +PSWAPD +PTEST +PTWRITE +PUNPCKHBW +PUNPCKHDQ +PUNPCKHQDQ +PUNPCKHWD +PUNPCKLBW +PUNPCKLDQ +PUNPCKLQDQ +PUNPCKLWD +PUSH +PUSHA +PUSHAD +PUSHF +PUSHFD +PUSHFQ +PVALIDATE +PXOR +RCL +RCPPS +RCPSS +RCR +RDFSBASE +RDGSBASE +RDMSR +RDPID +RDPKRU +RDPMC +RDPRU +RDRAND +RDSEED +RDSSPD +RDSSPQ +RDTSC +RDTSCP +REPE_CMPSB +REPE_CMPSD +REPE_CMPSQ +REPE_CMPSW +REPE_SCASB +REPE_SCASD +REPE_SCASQ +REPE_SCASW +REPNE_CMPSB +REPNE_CMPSD +REPNE_CMPSQ +REPNE_CMPSW +REPNE_SCASB +REPNE_SCASD +REPNE_SCASQ +REPNE_SCASW +REP_INSB +REP_INSD +REP_INSW +REP_LODSB +REP_LODSD +REP_LODSQ +REP_LODSW +REP_MONTMUL +REP_MOVSB +REP_MOVSD +REP_MOVSQ +REP_MOVSW +REP_OUTSB +REP_OUTSD +REP_OUTSW +REP_STOSB +REP_STOSD +REP_STOSQ +REP_STOSW +REP_XCRYPTCBC +REP_XCRYPTCFB +REP_XCRYPTCTR +REP_XCRYPTECB +REP_XCRYPTOFB +REP_XSHA1 +REP_XSHA256 +REP_XSTORE +RET_FAR +RET_NEAR +RMPADJUST +RMPUPDATE +ROL +ROR +RORX +ROUNDPD +ROUNDPS +ROUNDSD +ROUNDSS +RSM +RSQRTPS +RSQRTSS +RSTORSSP +SAHF +SALC +SAR +SARX +SAVEPREVSSP +SBB +SBB_LOCK +SCASB +SCASD +SCASQ +SCASW +SEAMCALL +SEAMOPS +SEAMRET +SENDUIPI +SERIALIZE +SETB +SETBE +SETL +SETLE +SETNB +SETNBE +SETNL +SETNLE +SETNO +SETNP +SETNS +SETNZ +SETO +SETP +SETS +SETSSBSY +SETZ +SFENCE +SGDT +SHA1MSG1 +SHA1MSG2 +SHA1NEXTE +SHA1RNDS4 +SHA256MSG1 +SHA256MSG2 +SHA256RNDS2 +SHL +SHLD +SHLX +SHR +SHRD +SHRX +SHUFPD +SHUFPS +SIDT +SKINIT +SLDT +SLWPCB +SMSW +SQRTPD +SQRTPS +SQRTSD +SQRTSS +STAC +STC +STD +STGI +STI +STMXCSR +STOSB +STOSD +STOSQ +STOSW +STR +STTILECFG +STUI +SUB +SUBPD +SUBPS +SUBSD +SUBSS +SUB_LOCK +SWAPGS +SYSCALL +SYSCALL_AMD +SYSENTER +SYSEXIT +SYSRET +SYSRET64 +SYSRET_AMD +T1MSKC +TDCALL +TDPBF16PS +TDPBSSD +TDPBSUD +TDPBUSD +TDPBUUD +TEST +TESTUI +TILELOADD +TILELOADDT1 +TILERELEASE +TILESTORED +TILEZERO +TLBSYNC +TPAUSE +TZCNT +TZMSK +UCOMISD +UCOMISS +UD0 +UD1 +UD2 +UIRET +UMONITOR +UMWAIT +UNPCKHPD +UNPCKHPS +UNPCKLPD +UNPCKLPS +V4FMADDPS +V4FMADDSS +V4FNMADDPS +V4FNMADDSS +VADDPD +VADDPH +VADDPS +VADDSD +VADDSH +VADDSS +VADDSUBPD +VADDSUBPS +VAESDEC +VAESDECLAST +VAESENC +VAESENCLAST +VAESIMC +VAESKEYGENASSIST +VALIGND +VALIGNQ +VANDNPD +VANDNPS +VANDPD +VANDPS +VBLENDMPD +VBLENDMPS +VBLENDPD +VBLENDPS +VBLENDVPD +VBLENDVPS +VBROADCASTF128 +VBROADCASTF32X2 +VBROADCASTF32X4 +VBROADCASTF32X8 +VBROADCASTF64X2 +VBROADCASTF64X4 +VBROADCASTI128 +VBROADCASTI32X2 +VBROADCASTI32X4 +VBROADCASTI32X8 +VBROADCASTI64X2 +VBROADCASTI64X4 +VBROADCASTSD +VBROADCASTSS +VCMPPD +VCMPPH +VCMPPS +VCMPSD +VCMPSH +VCMPSS +VCOMISD +VCOMISH +VCOMISS +VCOMPRESSPD +VCOMPRESSPS +VCVTDQ2PD +VCVTDQ2PH +VCVTDQ2PS +VCVTNE2PS2BF16 +VCVTNEPS2BF16 +VCVTPD2DQ +VCVTPD2PH +VCVTPD2PS +VCVTPD2QQ +VCVTPD2UDQ +VCVTPD2UQQ +VCVTPH2DQ +VCVTPH2PD +VCVTPH2PS +VCVTPH2PSX +VCVTPH2QQ +VCVTPH2UDQ +VCVTPH2UQQ +VCVTPH2UW +VCVTPH2W +VCVTPS2DQ +VCVTPS2PD +VCVTPS2PH +VCVTPS2PHX +VCVTPS2QQ +VCVTPS2UDQ +VCVTPS2UQQ +VCVTQQ2PD +VCVTQQ2PH +VCVTQQ2PS +VCVTSD2SH +VCVTSD2SI +VCVTSD2SS +VCVTSD2USI +VCVTSH2SD +VCVTSH2SI +VCVTSH2SS +VCVTSH2USI +VCVTSI2SD +VCVTSI2SH +VCVTSI2SS +VCVTSS2SD +VCVTSS2SH +VCVTSS2SI +VCVTSS2USI +VCVTTPD2DQ +VCVTTPD2QQ +VCVTTPD2UDQ +VCVTTPD2UQQ +VCVTTPH2DQ +VCVTTPH2QQ +VCVTTPH2UDQ +VCVTTPH2UQQ +VCVTTPH2UW +VCVTTPH2W +VCVTTPS2DQ +VCVTTPS2QQ +VCVTTPS2UDQ +VCVTTPS2UQQ +VCVTTSD2SI +VCVTTSD2USI +VCVTTSH2SI +VCVTTSH2USI +VCVTTSS2SI +VCVTTSS2USI +VCVTUDQ2PD +VCVTUDQ2PH +VCVTUDQ2PS +VCVTUQQ2PD +VCVTUQQ2PH +VCVTUQQ2PS +VCVTUSI2SD +VCVTUSI2SH +VCVTUSI2SS +VCVTUW2PH +VCVTW2PH +VDBPSADBW +VDIVPD +VDIVPH +VDIVPS +VDIVSD +VDIVSH +VDIVSS +VDPBF16PS +VDPPD +VDPPS +VERR +VERW +VEXP2PD +VEXP2PS +VEXPANDPD +VEXPANDPS +VEXTRACTF128 +VEXTRACTF32X4 +VEXTRACTF32X8 +VEXTRACTF64X2 +VEXTRACTF64X4 +VEXTRACTI128 +VEXTRACTI32X4 +VEXTRACTI32X8 +VEXTRACTI64X2 +VEXTRACTI64X4 +VEXTRACTPS +VFCMADDCPH +VFCMADDCSH +VFCMULCPH +VFCMULCSH +VFIXUPIMMPD +VFIXUPIMMPS +VFIXUPIMMSD +VFIXUPIMMSS +VFMADD132PD +VFMADD132PH +VFMADD132PS +VFMADD132SD +VFMADD132SH +VFMADD132SS +VFMADD213PD +VFMADD213PH +VFMADD213PS +VFMADD213SD +VFMADD213SH +VFMADD213SS +VFMADD231PD +VFMADD231PH +VFMADD231PS +VFMADD231SD +VFMADD231SH +VFMADD231SS +VFMADDCPH +VFMADDCSH +VFMADDPD +VFMADDPS +VFMADDSD +VFMADDSS +VFMADDSUB132PD +VFMADDSUB132PH +VFMADDSUB132PS +VFMADDSUB213PD +VFMADDSUB213PH +VFMADDSUB213PS +VFMADDSUB231PD +VFMADDSUB231PH +VFMADDSUB231PS +VFMADDSUBPD +VFMADDSUBPS +VFMSUB132PD +VFMSUB132PH +VFMSUB132PS +VFMSUB132SD +VFMSUB132SH +VFMSUB132SS +VFMSUB213PD +VFMSUB213PH +VFMSUB213PS +VFMSUB213SD +VFMSUB213SH +VFMSUB213SS +VFMSUB231PD +VFMSUB231PH +VFMSUB231PS +VFMSUB231SD +VFMSUB231SH +VFMSUB231SS +VFMSUBADD132PD +VFMSUBADD132PH +VFMSUBADD132PS +VFMSUBADD213PD +VFMSUBADD213PH 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+VGATHERQPD +VGATHERQPS +VGETEXPPD +VGETEXPPH +VGETEXPPS +VGETEXPSD +VGETEXPSH +VGETEXPSS +VGETMANTPD +VGETMANTPH +VGETMANTPS +VGETMANTSD +VGETMANTSH +VGETMANTSS +VGF2P8AFFINEINVQB +VGF2P8AFFINEQB +VGF2P8MULB +VHADDPD +VHADDPS +VHSUBPD +VHSUBPS +VINSERTF128 +VINSERTF32X4 +VINSERTF32X8 +VINSERTF64X2 +VINSERTF64X4 +VINSERTI128 +VINSERTI32X4 +VINSERTI32X8 +VINSERTI64X2 +VINSERTI64X4 +VINSERTPS +VLDDQU +VLDMXCSR +VMASKMOVDQU +VMASKMOVPD +VMASKMOVPS +VMAXPD +VMAXPH +VMAXPS +VMAXSD +VMAXSH +VMAXSS +VMCALL +VMCLEAR +VMFUNC +VMINPD +VMINPH +VMINPS +VMINSD +VMINSH +VMINSS +VMLAUNCH +VMLOAD +VMMCALL +VMOVAPD +VMOVAPS +VMOVD +VMOVDDUP +VMOVDQA +VMOVDQA32 +VMOVDQA64 +VMOVDQU +VMOVDQU16 +VMOVDQU32 +VMOVDQU64 +VMOVDQU8 +VMOVHLPS +VMOVHPD +VMOVHPS +VMOVLHPS +VMOVLPD +VMOVLPS +VMOVMSKPD +VMOVMSKPS +VMOVNTDQ +VMOVNTDQA +VMOVNTPD +VMOVNTPS +VMOVQ +VMOVSD +VMOVSH +VMOVSHDUP +VMOVSLDUP +VMOVSS +VMOVUPD +VMOVUPS +VMOVW +VMPSADBW +VMPTRLD +VMPTRST +VMREAD +VMRESUME +VMRUN +VMSAVE +VMULPD +VMULPH +VMULPS +VMULSD +VMULSH +VMULSS +VMWRITE +VMXOFF +VMXON +VORPD +VORPS +VP2INTERSECTD +VP2INTERSECTQ +VP4DPWSSD +VP4DPWSSDS +VPABSB +VPABSD +VPABSQ +VPABSW +VPACKSSDW +VPACKSSWB +VPACKUSDW +VPACKUSWB +VPADDB +VPADDD +VPADDQ +VPADDSB +VPADDSW +VPADDUSB +VPADDUSW +VPADDW +VPALIGNR +VPAND +VPANDD +VPANDN +VPANDND +VPANDNQ +VPANDQ +VPAVGB +VPAVGW +VPBLENDD +VPBLENDMB +VPBLENDMD +VPBLENDMQ +VPBLENDMW +VPBLENDVB +VPBLENDW +VPBROADCASTB +VPBROADCASTD +VPBROADCASTMB2Q +VPBROADCASTMW2D +VPBROADCASTQ +VPBROADCASTW +VPCLMULQDQ +VPCMOV +VPCMPB +VPCMPD +VPCMPEQB +VPCMPEQD +VPCMPEQQ +VPCMPEQW +VPCMPESTRI +VPCMPESTRI64 +VPCMPESTRM +VPCMPESTRM64 +VPCMPGTB +VPCMPGTD +VPCMPGTQ +VPCMPGTW +VPCMPISTRI +VPCMPISTRI64 +VPCMPISTRM +VPCMPQ +VPCMPUB +VPCMPUD +VPCMPUQ +VPCMPUW +VPCMPW +VPCOMB +VPCOMD +VPCOMPRESSB +VPCOMPRESSD +VPCOMPRESSQ +VPCOMPRESSW +VPCOMQ +VPCOMUB +VPCOMUD +VPCOMUQ +VPCOMUW +VPCOMW +VPCONFLICTD +VPCONFLICTQ +VPDPBUSD +VPDPBUSDS +VPDPWSSD +VPDPWSSDS +VPERM2F128 +VPERM2I128 +VPERMB +VPERMD +VPERMI2B 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+VPSLLW +VPSRAD +VPSRAQ +VPSRAVD +VPSRAVQ +VPSRAVW +VPSRAW +VPSRLD +VPSRLDQ +VPSRLQ +VPSRLVD +VPSRLVQ +VPSRLVW +VPSRLW +VPSUBB +VPSUBD +VPSUBQ +VPSUBSB +VPSUBSW +VPSUBUSB +VPSUBUSW +VPSUBW +VPTERNLOGD +VPTERNLOGQ +VPTEST +VPTESTMB +VPTESTMD +VPTESTMQ +VPTESTMW +VPTESTNMB +VPTESTNMD +VPTESTNMQ +VPTESTNMW +VPUNPCKHBW +VPUNPCKHDQ +VPUNPCKHQDQ +VPUNPCKHWD +VPUNPCKLBW +VPUNPCKLDQ +VPUNPCKLQDQ +VPUNPCKLWD +VPXOR +VPXORD +VPXORQ +VRANGEPD +VRANGEPS +VRANGESD +VRANGESS +VRCP14PD +VRCP14PS +VRCP14SD +VRCP14SS +VRCP28PD +VRCP28PS +VRCP28SD +VRCP28SS +VRCPPH +VRCPPS +VRCPSH +VRCPSS +VREDUCEPD +VREDUCEPH +VREDUCEPS +VREDUCESD +VREDUCESH +VREDUCESS +VRNDSCALEPD +VRNDSCALEPH +VRNDSCALEPS +VRNDSCALESD +VRNDSCALESH +VRNDSCALESS +VROUNDPD +VROUNDPS +VROUNDSD +VROUNDSS +VRSQRT14PD +VRSQRT14PS +VRSQRT14SD +VRSQRT14SS +VRSQRT28PD +VRSQRT28PS +VRSQRT28SD +VRSQRT28SS +VRSQRTPH +VRSQRTPS +VRSQRTSH +VRSQRTSS +VSCALEFPD +VSCALEFPH +VSCALEFPS +VSCALEFSD +VSCALEFSH +VSCALEFSS +VSCATTERDPD +VSCATTERDPS +VSCATTERPF0DPD +VSCATTERPF0DPS +VSCATTERPF0QPD +VSCATTERPF0QPS +VSCATTERPF1DPD +VSCATTERPF1DPS +VSCATTERPF1QPD +VSCATTERPF1QPS +VSCATTERQPD +VSCATTERQPS +VSHUFF32X4 +VSHUFF64X2 +VSHUFI32X4 +VSHUFI64X2 +VSHUFPD +VSHUFPS +VSQRTPD +VSQRTPH +VSQRTPS +VSQRTSD +VSQRTSH +VSQRTSS +VSTMXCSR +VSUBPD +VSUBPH +VSUBPS +VSUBSD +VSUBSH +VSUBSS +VTESTPD +VTESTPS +VUCOMISD +VUCOMISH +VUCOMISS +VUNPCKHPD +VUNPCKHPS +VUNPCKLPD +VUNPCKLPS +VXORPD +VXORPS +VZEROALL +VZEROUPPER +WBINVD +WBNOINVD +WRFSBASE +WRGSBASE +WRMSR +WRPKRU +WRSSD +WRSSQ +WRUSSD +WRUSSQ +XABORT +XADD +XADD_LOCK +XBEGIN +XCHG +XEND +XGETBV +XLAT +XOR +XORPD +XORPS +XOR_LOCK +XRESLDTRK +XRSTOR +XRSTOR64 +XRSTORS +XRSTORS64 +XSAVE +XSAVE64 +XSAVEC +XSAVEC64 +XSAVEOPT +XSAVEOPT64 +XSAVES +XSAVES64 +XSETBV +XSTORE +XSUSLDTRK +XTEST diff --git a/CodeVirtualizer/build/obj/xed-iclass-string.c b/CodeVirtualizer/build/obj/xed-iclass-string.c new file mode 100644 index 0000000..59b4895 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iclass-string.c @@ -0,0 +1,169 @@ +/// @file xed-iclass-string.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-gen-table-defs.h" +#include "xed-tables-extern.h" +char const* const xed_iclass_string[XED_ICLASS_NAME_STR_MAX] = { +"invalid", +"invalid", +"add", +"add", +"or", +"or", +"adc", +"adc", +"sbb", +"sbb", +"and", +"and", +"sub", +"sub", +"xor", +"xor", +"not", +"not", +"neg", +"neg", +"inc", +"inc", +"dec", +"dec", +"call", +"call", +"jmp far", +"ljmp", +"bts", +"bts", +"btr", +"btr", +"btc", +"btc", +"cmpxchg8b", +"cmpxchg8b", +"cmpxchg16b", +"cmpxchg16b", +"insb", +"insb", +"insw", +"insw", +"insd", +"insd", +"outsb", +"outsb", +"outsw", +"outsw", +"outsd", +"outsd", +"call far", +"lcall", +"movsb", +"movsb", +"movsw", +"movsw", +"movsd", +"movsd", +"movsq", +"movsq", +"cmpsb", +"cmpsb", +"cmpsw", +"cmpsw", +"cmpsd", +"cmpsd", +"cmpsq", +"cmpsq", +"stosb", +"stosb", +"stosw", +"stosw", +"stosd", +"stosd", +"stosq", +"stosq", +"lodsb", +"lodsb", +"lodsw", +"lodsw", +"lodsd", +"lodsd", +"lodsq", +"lodsq", +"scasb", +"scasb", +"scasw", +"scasw", +"scasd", +"scasd", +"scasq", +"scasq", +"ret", +"ret", +"ret far", +"lcall", +"sysret", +"sysret", +"mov", +"mov", +"cmpxchg", +"cmpxchg", +"xadd", +"xadd", +"pextrw", +"pextrw", +"pcmpestri", +"pcmpestri", +"pcmpistri", +"pcmpistri", +"pcmpestrm", +"pcmpestrm", +"xstore", +"xstore", +"xcryptecb", +"xcryptecb", +"xcryptcbc", +"xcryptcbc", +"xcryptctr", +"xcryptctr", +"xcryptcfb", +"xcryptcfb", +"xcryptofb", +"xcryptofb", +"xsha1", +"xsha1", +"xsha256", +"xsha256", +"montmul", +"montmul", +"syscall", +"syscall", +"bextr", +"bextr", +"vpcmpestri", +"vpcmpestri", +"vpcmpistri", +"vpcmpistri", +"vpcmpestrm", +"vpcmpestrm", +"vpextrw", +"vpextrw", +}; diff --git a/CodeVirtualizer/build/obj/xed-iform-enum.c b/CodeVirtualizer/build/obj/xed-iform-enum.c new file mode 100644 index 0000000..5927603 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iform-enum.c @@ -0,0 +1,13788 @@ +/// @file xed-iform-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-iform-enum.h" + +typedef struct { + const char* name; + xed_iform_enum_t value; +} name_table_xed_iform_enum_t; +static const name_table_xed_iform_enum_t name_array_xed_iform_enum_t[] = { +{"INVALID", XED_IFORM_INVALID}, +{"AAA", XED_IFORM_AAA}, +{"AAD_IMMb", XED_IFORM_AAD_IMMb}, +{"AAM_IMMb", XED_IFORM_AAM_IMMb}, +{"AAS", XED_IFORM_AAS}, +{"ADC_AL_IMMb", XED_IFORM_ADC_AL_IMMb}, +{"ADC_GPR8_GPR8_10", XED_IFORM_ADC_GPR8_GPR8_10}, +{"ADC_GPR8_GPR8_12", XED_IFORM_ADC_GPR8_GPR8_12}, +{"ADC_GPR8_IMMb_80r2", XED_IFORM_ADC_GPR8_IMMb_80r2}, +{"ADC_GPR8_IMMb_82r2", XED_IFORM_ADC_GPR8_IMMb_82r2}, +{"ADC_GPR8_MEMb", XED_IFORM_ADC_GPR8_MEMb}, +{"ADC_GPRv_GPRv_11", XED_IFORM_ADC_GPRv_GPRv_11}, +{"ADC_GPRv_GPRv_13", XED_IFORM_ADC_GPRv_GPRv_13}, +{"ADC_GPRv_IMMb", XED_IFORM_ADC_GPRv_IMMb}, +{"ADC_GPRv_IMMz", XED_IFORM_ADC_GPRv_IMMz}, +{"ADC_GPRv_MEMv", XED_IFORM_ADC_GPRv_MEMv}, +{"ADC_MEMb_GPR8", XED_IFORM_ADC_MEMb_GPR8}, +{"ADC_MEMb_IMMb_80r2", XED_IFORM_ADC_MEMb_IMMb_80r2}, +{"ADC_MEMb_IMMb_82r2", XED_IFORM_ADC_MEMb_IMMb_82r2}, +{"ADC_MEMv_GPRv", XED_IFORM_ADC_MEMv_GPRv}, +{"ADC_MEMv_IMMb", XED_IFORM_ADC_MEMv_IMMb}, +{"ADC_MEMv_IMMz", XED_IFORM_ADC_MEMv_IMMz}, +{"ADC_OrAX_IMMz", XED_IFORM_ADC_OrAX_IMMz}, +{"ADCX_GPR32d_GPR32d", XED_IFORM_ADCX_GPR32d_GPR32d}, +{"ADCX_GPR32d_MEMd", XED_IFORM_ADCX_GPR32d_MEMd}, +{"ADCX_GPR64q_GPR64q", XED_IFORM_ADCX_GPR64q_GPR64q}, +{"ADCX_GPR64q_MEMq", XED_IFORM_ADCX_GPR64q_MEMq}, +{"ADC_LOCK_MEMb_GPR8", XED_IFORM_ADC_LOCK_MEMb_GPR8}, +{"ADC_LOCK_MEMb_IMMb_80r2", XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2}, +{"ADC_LOCK_MEMb_IMMb_82r2", XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2}, +{"ADC_LOCK_MEMv_GPRv", XED_IFORM_ADC_LOCK_MEMv_GPRv}, +{"ADC_LOCK_MEMv_IMMb", XED_IFORM_ADC_LOCK_MEMv_IMMb}, +{"ADC_LOCK_MEMv_IMMz", XED_IFORM_ADC_LOCK_MEMv_IMMz}, +{"ADD_AL_IMMb", XED_IFORM_ADD_AL_IMMb}, +{"ADD_GPR8_GPR8_00", XED_IFORM_ADD_GPR8_GPR8_00}, +{"ADD_GPR8_GPR8_02", XED_IFORM_ADD_GPR8_GPR8_02}, +{"ADD_GPR8_IMMb_80r0", XED_IFORM_ADD_GPR8_IMMb_80r0}, +{"ADD_GPR8_IMMb_82r0", XED_IFORM_ADD_GPR8_IMMb_82r0}, +{"ADD_GPR8_MEMb", XED_IFORM_ADD_GPR8_MEMb}, +{"ADD_GPRv_GPRv_01", XED_IFORM_ADD_GPRv_GPRv_01}, +{"ADD_GPRv_GPRv_03", XED_IFORM_ADD_GPRv_GPRv_03}, +{"ADD_GPRv_IMMb", XED_IFORM_ADD_GPRv_IMMb}, +{"ADD_GPRv_IMMz", XED_IFORM_ADD_GPRv_IMMz}, +{"ADD_GPRv_MEMv", XED_IFORM_ADD_GPRv_MEMv}, +{"ADD_MEMb_GPR8", XED_IFORM_ADD_MEMb_GPR8}, +{"ADD_MEMb_IMMb_80r0", XED_IFORM_ADD_MEMb_IMMb_80r0}, +{"ADD_MEMb_IMMb_82r0", XED_IFORM_ADD_MEMb_IMMb_82r0}, +{"ADD_MEMv_GPRv", XED_IFORM_ADD_MEMv_GPRv}, +{"ADD_MEMv_IMMb", XED_IFORM_ADD_MEMv_IMMb}, +{"ADD_MEMv_IMMz", XED_IFORM_ADD_MEMv_IMMz}, +{"ADD_OrAX_IMMz", XED_IFORM_ADD_OrAX_IMMz}, +{"ADDPD_XMMpd_MEMpd", XED_IFORM_ADDPD_XMMpd_MEMpd}, +{"ADDPD_XMMpd_XMMpd", XED_IFORM_ADDPD_XMMpd_XMMpd}, +{"ADDPS_XMMps_MEMps", XED_IFORM_ADDPS_XMMps_MEMps}, +{"ADDPS_XMMps_XMMps", XED_IFORM_ADDPS_XMMps_XMMps}, +{"ADDSD_XMMsd_MEMsd", XED_IFORM_ADDSD_XMMsd_MEMsd}, +{"ADDSD_XMMsd_XMMsd", XED_IFORM_ADDSD_XMMsd_XMMsd}, +{"ADDSS_XMMss_MEMss", XED_IFORM_ADDSS_XMMss_MEMss}, +{"ADDSS_XMMss_XMMss", XED_IFORM_ADDSS_XMMss_XMMss}, +{"ADDSUBPD_XMMpd_MEMpd", XED_IFORM_ADDSUBPD_XMMpd_MEMpd}, +{"ADDSUBPD_XMMpd_XMMpd", XED_IFORM_ADDSUBPD_XMMpd_XMMpd}, +{"ADDSUBPS_XMMps_MEMps", XED_IFORM_ADDSUBPS_XMMps_MEMps}, +{"ADDSUBPS_XMMps_XMMps", XED_IFORM_ADDSUBPS_XMMps_XMMps}, +{"ADD_LOCK_MEMb_GPR8", XED_IFORM_ADD_LOCK_MEMb_GPR8}, +{"ADD_LOCK_MEMb_IMMb_80r0", XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0}, +{"ADD_LOCK_MEMb_IMMb_82r0", XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0}, +{"ADD_LOCK_MEMv_GPRv", XED_IFORM_ADD_LOCK_MEMv_GPRv}, +{"ADD_LOCK_MEMv_IMMb", XED_IFORM_ADD_LOCK_MEMv_IMMb}, +{"ADD_LOCK_MEMv_IMMz", XED_IFORM_ADD_LOCK_MEMv_IMMz}, +{"ADOX_GPR32d_GPR32d", XED_IFORM_ADOX_GPR32d_GPR32d}, +{"ADOX_GPR32d_MEMd", XED_IFORM_ADOX_GPR32d_MEMd}, +{"ADOX_GPR64q_GPR64q", XED_IFORM_ADOX_GPR64q_GPR64q}, +{"ADOX_GPR64q_MEMq", XED_IFORM_ADOX_GPR64q_MEMq}, +{"AESDEC_XMMdq_MEMdq", XED_IFORM_AESDEC_XMMdq_MEMdq}, +{"AESDEC_XMMdq_XMMdq", XED_IFORM_AESDEC_XMMdq_XMMdq}, +{"AESDEC128KL_XMMu8_MEMu8", XED_IFORM_AESDEC128KL_XMMu8_MEMu8}, +{"AESDEC256KL_XMMu8_MEMu8", XED_IFORM_AESDEC256KL_XMMu8_MEMu8}, +{"AESDECLAST_XMMdq_MEMdq", XED_IFORM_AESDECLAST_XMMdq_MEMdq}, +{"AESDECLAST_XMMdq_XMMdq", XED_IFORM_AESDECLAST_XMMdq_XMMdq}, +{"AESDECWIDE128KL_MEMu8", XED_IFORM_AESDECWIDE128KL_MEMu8}, +{"AESDECWIDE256KL_MEMu8", XED_IFORM_AESDECWIDE256KL_MEMu8}, +{"AESENC_XMMdq_MEMdq", XED_IFORM_AESENC_XMMdq_MEMdq}, +{"AESENC_XMMdq_XMMdq", XED_IFORM_AESENC_XMMdq_XMMdq}, +{"AESENC128KL_XMMu8_MEMu8", XED_IFORM_AESENC128KL_XMMu8_MEMu8}, +{"AESENC256KL_XMMu8_MEMu8", XED_IFORM_AESENC256KL_XMMu8_MEMu8}, +{"AESENCLAST_XMMdq_MEMdq", XED_IFORM_AESENCLAST_XMMdq_MEMdq}, +{"AESENCLAST_XMMdq_XMMdq", XED_IFORM_AESENCLAST_XMMdq_XMMdq}, +{"AESENCWIDE128KL_MEMu8", XED_IFORM_AESENCWIDE128KL_MEMu8}, +{"AESENCWIDE256KL_MEMu8", XED_IFORM_AESENCWIDE256KL_MEMu8}, +{"AESIMC_XMMdq_MEMdq", XED_IFORM_AESIMC_XMMdq_MEMdq}, +{"AESIMC_XMMdq_XMMdq", XED_IFORM_AESIMC_XMMdq_XMMdq}, +{"AESKEYGENASSIST_XMMdq_MEMdq_IMMb", XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb}, +{"AESKEYGENASSIST_XMMdq_XMMdq_IMMb", XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb}, +{"AND_AL_IMMb", XED_IFORM_AND_AL_IMMb}, +{"AND_GPR8_GPR8_20", XED_IFORM_AND_GPR8_GPR8_20}, +{"AND_GPR8_GPR8_22", XED_IFORM_AND_GPR8_GPR8_22}, +{"AND_GPR8_IMMb_80r4", XED_IFORM_AND_GPR8_IMMb_80r4}, +{"AND_GPR8_IMMb_82r4", XED_IFORM_AND_GPR8_IMMb_82r4}, +{"AND_GPR8_MEMb", XED_IFORM_AND_GPR8_MEMb}, +{"AND_GPRv_GPRv_21", XED_IFORM_AND_GPRv_GPRv_21}, +{"AND_GPRv_GPRv_23", XED_IFORM_AND_GPRv_GPRv_23}, +{"AND_GPRv_IMMb", XED_IFORM_AND_GPRv_IMMb}, +{"AND_GPRv_IMMz", XED_IFORM_AND_GPRv_IMMz}, +{"AND_GPRv_MEMv", XED_IFORM_AND_GPRv_MEMv}, +{"AND_MEMb_GPR8", XED_IFORM_AND_MEMb_GPR8}, +{"AND_MEMb_IMMb_80r4", XED_IFORM_AND_MEMb_IMMb_80r4}, +{"AND_MEMb_IMMb_82r4", XED_IFORM_AND_MEMb_IMMb_82r4}, +{"AND_MEMv_GPRv", XED_IFORM_AND_MEMv_GPRv}, +{"AND_MEMv_IMMb", XED_IFORM_AND_MEMv_IMMb}, +{"AND_MEMv_IMMz", XED_IFORM_AND_MEMv_IMMz}, +{"AND_OrAX_IMMz", XED_IFORM_AND_OrAX_IMMz}, +{"ANDN_VGPR32d_VGPR32d_MEMd", XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd}, +{"ANDN_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d}, +{"ANDN_VGPR64q_VGPR64q_MEMq", XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq}, +{"ANDN_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q}, +{"ANDNPD_XMMxuq_MEMxuq", XED_IFORM_ANDNPD_XMMxuq_MEMxuq}, +{"ANDNPD_XMMxuq_XMMxuq", XED_IFORM_ANDNPD_XMMxuq_XMMxuq}, +{"ANDNPS_XMMxud_MEMxud", XED_IFORM_ANDNPS_XMMxud_MEMxud}, +{"ANDNPS_XMMxud_XMMxud", XED_IFORM_ANDNPS_XMMxud_XMMxud}, +{"ANDPD_XMMxuq_MEMxuq", XED_IFORM_ANDPD_XMMxuq_MEMxuq}, +{"ANDPD_XMMxuq_XMMxuq", XED_IFORM_ANDPD_XMMxuq_XMMxuq}, +{"ANDPS_XMMxud_MEMxud", XED_IFORM_ANDPS_XMMxud_MEMxud}, +{"ANDPS_XMMxud_XMMxud", XED_IFORM_ANDPS_XMMxud_XMMxud}, +{"AND_LOCK_MEMb_GPR8", XED_IFORM_AND_LOCK_MEMb_GPR8}, +{"AND_LOCK_MEMb_IMMb_80r4", XED_IFORM_AND_LOCK_MEMb_IMMb_80r4}, +{"AND_LOCK_MEMb_IMMb_82r4", XED_IFORM_AND_LOCK_MEMb_IMMb_82r4}, +{"AND_LOCK_MEMv_GPRv", XED_IFORM_AND_LOCK_MEMv_GPRv}, +{"AND_LOCK_MEMv_IMMb", XED_IFORM_AND_LOCK_MEMv_IMMb}, +{"AND_LOCK_MEMv_IMMz", XED_IFORM_AND_LOCK_MEMv_IMMz}, +{"ARPL_GPR16_GPR16", XED_IFORM_ARPL_GPR16_GPR16}, +{"ARPL_MEMw_GPR16", XED_IFORM_ARPL_MEMw_GPR16}, +{"BEXTR_VGPR32d_MEMd_VGPR32d", XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d}, +{"BEXTR_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d}, +{"BEXTR_VGPR64q_MEMq_VGPR64q", XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q}, +{"BEXTR_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q}, +{"BEXTR_XOP_VGPR32d_MEMd_IMMd", XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd}, +{"BEXTR_XOP_VGPR32d_VGPR32d_IMMd", XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd}, +{"BEXTR_XOP_VGPRyy_MEMy_IMMd", XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd}, +{"BEXTR_XOP_VGPRyy_VGPRyy_IMMd", XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd}, +{"BLCFILL_VGPR32d_MEMd", XED_IFORM_BLCFILL_VGPR32d_MEMd}, +{"BLCFILL_VGPR32d_VGPR32d", XED_IFORM_BLCFILL_VGPR32d_VGPR32d}, +{"BLCFILL_VGPRyy_MEMy", XED_IFORM_BLCFILL_VGPRyy_MEMy}, +{"BLCFILL_VGPRyy_VGPRyy", XED_IFORM_BLCFILL_VGPRyy_VGPRyy}, +{"BLCI_VGPR32d_MEMd", XED_IFORM_BLCI_VGPR32d_MEMd}, +{"BLCI_VGPR32d_VGPR32d", XED_IFORM_BLCI_VGPR32d_VGPR32d}, +{"BLCI_VGPRyy_MEMy", XED_IFORM_BLCI_VGPRyy_MEMy}, +{"BLCI_VGPRyy_VGPRyy", XED_IFORM_BLCI_VGPRyy_VGPRyy}, +{"BLCIC_VGPR32d_MEMd", XED_IFORM_BLCIC_VGPR32d_MEMd}, +{"BLCIC_VGPR32d_VGPR32d", XED_IFORM_BLCIC_VGPR32d_VGPR32d}, +{"BLCIC_VGPRyy_MEMy", XED_IFORM_BLCIC_VGPRyy_MEMy}, +{"BLCIC_VGPRyy_VGPRyy", XED_IFORM_BLCIC_VGPRyy_VGPRyy}, +{"BLCMSK_VGPR32d_MEMd", XED_IFORM_BLCMSK_VGPR32d_MEMd}, +{"BLCMSK_VGPR32d_VGPR32d", XED_IFORM_BLCMSK_VGPR32d_VGPR32d}, +{"BLCMSK_VGPRyy_MEMy", XED_IFORM_BLCMSK_VGPRyy_MEMy}, +{"BLCMSK_VGPRyy_VGPRyy", XED_IFORM_BLCMSK_VGPRyy_VGPRyy}, +{"BLCS_VGPR32d_MEMd", XED_IFORM_BLCS_VGPR32d_MEMd}, +{"BLCS_VGPR32d_VGPR32d", XED_IFORM_BLCS_VGPR32d_VGPR32d}, +{"BLCS_VGPRyy_MEMy", XED_IFORM_BLCS_VGPRyy_MEMy}, +{"BLCS_VGPRyy_VGPRyy", XED_IFORM_BLCS_VGPRyy_VGPRyy}, +{"BLENDPD_XMMdq_MEMdq_IMMb", XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb}, +{"BLENDPD_XMMdq_XMMdq_IMMb", XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb}, +{"BLENDPS_XMMdq_MEMdq_IMMb", XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb}, +{"BLENDPS_XMMdq_XMMdq_IMMb", XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb}, +{"BLENDVPD_XMMdq_MEMdq", XED_IFORM_BLENDVPD_XMMdq_MEMdq}, +{"BLENDVPD_XMMdq_XMMdq", XED_IFORM_BLENDVPD_XMMdq_XMMdq}, +{"BLENDVPS_XMMdq_MEMdq", XED_IFORM_BLENDVPS_XMMdq_MEMdq}, +{"BLENDVPS_XMMdq_XMMdq", XED_IFORM_BLENDVPS_XMMdq_XMMdq}, +{"BLSFILL_VGPR32d_MEMd", XED_IFORM_BLSFILL_VGPR32d_MEMd}, +{"BLSFILL_VGPR32d_VGPR32d", XED_IFORM_BLSFILL_VGPR32d_VGPR32d}, +{"BLSFILL_VGPRyy_MEMy", XED_IFORM_BLSFILL_VGPRyy_MEMy}, +{"BLSFILL_VGPRyy_VGPRyy", XED_IFORM_BLSFILL_VGPRyy_VGPRyy}, +{"BLSI_VGPR32d_MEMd", XED_IFORM_BLSI_VGPR32d_MEMd}, +{"BLSI_VGPR32d_VGPR32d", XED_IFORM_BLSI_VGPR32d_VGPR32d}, +{"BLSI_VGPR64q_MEMq", XED_IFORM_BLSI_VGPR64q_MEMq}, +{"BLSI_VGPR64q_VGPR64q", XED_IFORM_BLSI_VGPR64q_VGPR64q}, +{"BLSIC_VGPR32d_MEMd", XED_IFORM_BLSIC_VGPR32d_MEMd}, +{"BLSIC_VGPR32d_VGPR32d", XED_IFORM_BLSIC_VGPR32d_VGPR32d}, +{"BLSIC_VGPRyy_MEMy", XED_IFORM_BLSIC_VGPRyy_MEMy}, +{"BLSIC_VGPRyy_VGPRyy", XED_IFORM_BLSIC_VGPRyy_VGPRyy}, +{"BLSMSK_VGPR32d_MEMd", XED_IFORM_BLSMSK_VGPR32d_MEMd}, +{"BLSMSK_VGPR32d_VGPR32d", XED_IFORM_BLSMSK_VGPR32d_VGPR32d}, +{"BLSMSK_VGPR64q_MEMq", XED_IFORM_BLSMSK_VGPR64q_MEMq}, +{"BLSMSK_VGPR64q_VGPR64q", XED_IFORM_BLSMSK_VGPR64q_VGPR64q}, +{"BLSR_VGPR32d_MEMd", XED_IFORM_BLSR_VGPR32d_MEMd}, +{"BLSR_VGPR32d_VGPR32d", XED_IFORM_BLSR_VGPR32d_VGPR32d}, +{"BLSR_VGPR64q_MEMq", XED_IFORM_BLSR_VGPR64q_MEMq}, +{"BLSR_VGPR64q_VGPR64q", XED_IFORM_BLSR_VGPR64q_VGPR64q}, +{"BNDCL_BND_AGEN", XED_IFORM_BNDCL_BND_AGEN}, +{"BNDCL_BND_GPR32", XED_IFORM_BNDCL_BND_GPR32}, +{"BNDCL_BND_GPR64", XED_IFORM_BNDCL_BND_GPR64}, +{"BNDCN_BND_AGEN", XED_IFORM_BNDCN_BND_AGEN}, +{"BNDCN_BND_GPR32", XED_IFORM_BNDCN_BND_GPR32}, +{"BNDCN_BND_GPR64", XED_IFORM_BNDCN_BND_GPR64}, +{"BNDCU_BND_AGEN", XED_IFORM_BNDCU_BND_AGEN}, +{"BNDCU_BND_GPR32", XED_IFORM_BNDCU_BND_GPR32}, +{"BNDCU_BND_GPR64", XED_IFORM_BNDCU_BND_GPR64}, +{"BNDLDX_BND_MEMbnd32", XED_IFORM_BNDLDX_BND_MEMbnd32}, +{"BNDLDX_BND_MEMbnd64", XED_IFORM_BNDLDX_BND_MEMbnd64}, +{"BNDMK_BND_AGEN", XED_IFORM_BNDMK_BND_AGEN}, +{"BNDMOV_BND_BND", XED_IFORM_BNDMOV_BND_BND}, +{"BNDMOV_BND_MEMdq", XED_IFORM_BNDMOV_BND_MEMdq}, +{"BNDMOV_BND_MEMq", XED_IFORM_BNDMOV_BND_MEMq}, +{"BNDMOV_MEMdq_BND", XED_IFORM_BNDMOV_MEMdq_BND}, +{"BNDMOV_MEMq_BND", XED_IFORM_BNDMOV_MEMq_BND}, +{"BNDSTX_MEMbnd32_BND", XED_IFORM_BNDSTX_MEMbnd32_BND}, +{"BNDSTX_MEMbnd64_BND", XED_IFORM_BNDSTX_MEMbnd64_BND}, +{"BOUND_GPRv_MEMa16", XED_IFORM_BOUND_GPRv_MEMa16}, +{"BOUND_GPRv_MEMa32", XED_IFORM_BOUND_GPRv_MEMa32}, +{"BSF_GPRv_GPRv", XED_IFORM_BSF_GPRv_GPRv}, +{"BSF_GPRv_MEMv", XED_IFORM_BSF_GPRv_MEMv}, +{"BSR_GPRv_GPRv", XED_IFORM_BSR_GPRv_GPRv}, +{"BSR_GPRv_MEMv", XED_IFORM_BSR_GPRv_MEMv}, +{"BSWAP_GPRv", XED_IFORM_BSWAP_GPRv}, +{"BT_GPRv_GPRv", XED_IFORM_BT_GPRv_GPRv}, +{"BT_GPRv_IMMb", XED_IFORM_BT_GPRv_IMMb}, +{"BT_MEMv_GPRv", XED_IFORM_BT_MEMv_GPRv}, +{"BT_MEMv_IMMb", XED_IFORM_BT_MEMv_IMMb}, +{"BTC_GPRv_GPRv", XED_IFORM_BTC_GPRv_GPRv}, +{"BTC_GPRv_IMMb", XED_IFORM_BTC_GPRv_IMMb}, +{"BTC_MEMv_GPRv", XED_IFORM_BTC_MEMv_GPRv}, +{"BTC_MEMv_IMMb", XED_IFORM_BTC_MEMv_IMMb}, +{"BTC_LOCK_MEMv_GPRv", XED_IFORM_BTC_LOCK_MEMv_GPRv}, +{"BTC_LOCK_MEMv_IMMb", XED_IFORM_BTC_LOCK_MEMv_IMMb}, +{"BTR_GPRv_GPRv", XED_IFORM_BTR_GPRv_GPRv}, +{"BTR_GPRv_IMMb", XED_IFORM_BTR_GPRv_IMMb}, +{"BTR_MEMv_GPRv", XED_IFORM_BTR_MEMv_GPRv}, +{"BTR_MEMv_IMMb", XED_IFORM_BTR_MEMv_IMMb}, +{"BTR_LOCK_MEMv_GPRv", XED_IFORM_BTR_LOCK_MEMv_GPRv}, +{"BTR_LOCK_MEMv_IMMb", XED_IFORM_BTR_LOCK_MEMv_IMMb}, +{"BTS_GPRv_GPRv", XED_IFORM_BTS_GPRv_GPRv}, +{"BTS_GPRv_IMMb", XED_IFORM_BTS_GPRv_IMMb}, +{"BTS_MEMv_GPRv", XED_IFORM_BTS_MEMv_GPRv}, +{"BTS_MEMv_IMMb", XED_IFORM_BTS_MEMv_IMMb}, +{"BTS_LOCK_MEMv_GPRv", XED_IFORM_BTS_LOCK_MEMv_GPRv}, +{"BTS_LOCK_MEMv_IMMb", XED_IFORM_BTS_LOCK_MEMv_IMMb}, +{"BZHI_VGPR32d_MEMd_VGPR32d", XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d}, +{"BZHI_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d}, +{"BZHI_VGPR64q_MEMq_VGPR64q", XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q}, +{"BZHI_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q}, +{"CALL_FAR_MEMp2", XED_IFORM_CALL_FAR_MEMp2}, +{"CALL_FAR_PTRp_IMMw", XED_IFORM_CALL_FAR_PTRp_IMMw}, +{"CALL_NEAR_GPRv", XED_IFORM_CALL_NEAR_GPRv}, +{"CALL_NEAR_MEMv", XED_IFORM_CALL_NEAR_MEMv}, +{"CALL_NEAR_RELBRd", XED_IFORM_CALL_NEAR_RELBRd}, +{"CALL_NEAR_RELBRz", XED_IFORM_CALL_NEAR_RELBRz}, +{"CBW", XED_IFORM_CBW}, +{"CDQ", XED_IFORM_CDQ}, +{"CDQE", XED_IFORM_CDQE}, +{"CLAC", XED_IFORM_CLAC}, +{"CLC", XED_IFORM_CLC}, +{"CLD", XED_IFORM_CLD}, +{"CLDEMOTE_MEMu8", XED_IFORM_CLDEMOTE_MEMu8}, +{"CLFLUSH_MEMmprefetch", XED_IFORM_CLFLUSH_MEMmprefetch}, +{"CLFLUSHOPT_MEMmprefetch", XED_IFORM_CLFLUSHOPT_MEMmprefetch}, +{"CLGI", XED_IFORM_CLGI}, +{"CLI", XED_IFORM_CLI}, +{"CLRSSBSY_MEMu64", XED_IFORM_CLRSSBSY_MEMu64}, +{"CLTS", XED_IFORM_CLTS}, +{"CLUI", XED_IFORM_CLUI}, +{"CLWB_MEMmprefetch", XED_IFORM_CLWB_MEMmprefetch}, +{"CLZERO", XED_IFORM_CLZERO}, +{"CMC", XED_IFORM_CMC}, +{"CMOVB_GPRv_GPRv", XED_IFORM_CMOVB_GPRv_GPRv}, +{"CMOVB_GPRv_MEMv", XED_IFORM_CMOVB_GPRv_MEMv}, +{"CMOVBE_GPRv_GPRv", XED_IFORM_CMOVBE_GPRv_GPRv}, +{"CMOVBE_GPRv_MEMv", XED_IFORM_CMOVBE_GPRv_MEMv}, +{"CMOVL_GPRv_GPRv", XED_IFORM_CMOVL_GPRv_GPRv}, +{"CMOVL_GPRv_MEMv", XED_IFORM_CMOVL_GPRv_MEMv}, +{"CMOVLE_GPRv_GPRv", XED_IFORM_CMOVLE_GPRv_GPRv}, +{"CMOVLE_GPRv_MEMv", XED_IFORM_CMOVLE_GPRv_MEMv}, +{"CMOVNB_GPRv_GPRv", XED_IFORM_CMOVNB_GPRv_GPRv}, +{"CMOVNB_GPRv_MEMv", XED_IFORM_CMOVNB_GPRv_MEMv}, +{"CMOVNBE_GPRv_GPRv", XED_IFORM_CMOVNBE_GPRv_GPRv}, +{"CMOVNBE_GPRv_MEMv", XED_IFORM_CMOVNBE_GPRv_MEMv}, +{"CMOVNL_GPRv_GPRv", XED_IFORM_CMOVNL_GPRv_GPRv}, +{"CMOVNL_GPRv_MEMv", XED_IFORM_CMOVNL_GPRv_MEMv}, +{"CMOVNLE_GPRv_GPRv", XED_IFORM_CMOVNLE_GPRv_GPRv}, +{"CMOVNLE_GPRv_MEMv", XED_IFORM_CMOVNLE_GPRv_MEMv}, +{"CMOVNO_GPRv_GPRv", XED_IFORM_CMOVNO_GPRv_GPRv}, +{"CMOVNO_GPRv_MEMv", XED_IFORM_CMOVNO_GPRv_MEMv}, +{"CMOVNP_GPRv_GPRv", XED_IFORM_CMOVNP_GPRv_GPRv}, +{"CMOVNP_GPRv_MEMv", XED_IFORM_CMOVNP_GPRv_MEMv}, +{"CMOVNS_GPRv_GPRv", XED_IFORM_CMOVNS_GPRv_GPRv}, +{"CMOVNS_GPRv_MEMv", XED_IFORM_CMOVNS_GPRv_MEMv}, +{"CMOVNZ_GPRv_GPRv", XED_IFORM_CMOVNZ_GPRv_GPRv}, +{"CMOVNZ_GPRv_MEMv", XED_IFORM_CMOVNZ_GPRv_MEMv}, +{"CMOVO_GPRv_GPRv", XED_IFORM_CMOVO_GPRv_GPRv}, +{"CMOVO_GPRv_MEMv", XED_IFORM_CMOVO_GPRv_MEMv}, +{"CMOVP_GPRv_GPRv", XED_IFORM_CMOVP_GPRv_GPRv}, +{"CMOVP_GPRv_MEMv", XED_IFORM_CMOVP_GPRv_MEMv}, +{"CMOVS_GPRv_GPRv", XED_IFORM_CMOVS_GPRv_GPRv}, +{"CMOVS_GPRv_MEMv", XED_IFORM_CMOVS_GPRv_MEMv}, +{"CMOVZ_GPRv_GPRv", XED_IFORM_CMOVZ_GPRv_GPRv}, +{"CMOVZ_GPRv_MEMv", XED_IFORM_CMOVZ_GPRv_MEMv}, +{"CMP_AL_IMMb", XED_IFORM_CMP_AL_IMMb}, +{"CMP_GPR8_GPR8_38", XED_IFORM_CMP_GPR8_GPR8_38}, +{"CMP_GPR8_GPR8_3A", XED_IFORM_CMP_GPR8_GPR8_3A}, +{"CMP_GPR8_IMMb_80r7", XED_IFORM_CMP_GPR8_IMMb_80r7}, +{"CMP_GPR8_IMMb_82r7", XED_IFORM_CMP_GPR8_IMMb_82r7}, +{"CMP_GPR8_MEMb", XED_IFORM_CMP_GPR8_MEMb}, +{"CMP_GPRv_GPRv_39", XED_IFORM_CMP_GPRv_GPRv_39}, +{"CMP_GPRv_GPRv_3B", XED_IFORM_CMP_GPRv_GPRv_3B}, +{"CMP_GPRv_IMMb", XED_IFORM_CMP_GPRv_IMMb}, +{"CMP_GPRv_IMMz", XED_IFORM_CMP_GPRv_IMMz}, +{"CMP_GPRv_MEMv", XED_IFORM_CMP_GPRv_MEMv}, +{"CMP_MEMb_GPR8", XED_IFORM_CMP_MEMb_GPR8}, +{"CMP_MEMb_IMMb_80r7", XED_IFORM_CMP_MEMb_IMMb_80r7}, +{"CMP_MEMb_IMMb_82r7", XED_IFORM_CMP_MEMb_IMMb_82r7}, +{"CMP_MEMv_GPRv", XED_IFORM_CMP_MEMv_GPRv}, +{"CMP_MEMv_IMMb", XED_IFORM_CMP_MEMv_IMMb}, +{"CMP_MEMv_IMMz", XED_IFORM_CMP_MEMv_IMMz}, +{"CMP_OrAX_IMMz", XED_IFORM_CMP_OrAX_IMMz}, +{"CMPPD_XMMpd_MEMpd_IMMb", XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb}, +{"CMPPD_XMMpd_XMMpd_IMMb", XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb}, +{"CMPPS_XMMps_MEMps_IMMb", XED_IFORM_CMPPS_XMMps_MEMps_IMMb}, +{"CMPPS_XMMps_XMMps_IMMb", XED_IFORM_CMPPS_XMMps_XMMps_IMMb}, +{"CMPSB", XED_IFORM_CMPSB}, +{"CMPSD", XED_IFORM_CMPSD}, +{"CMPSD_XMM_XMMsd_MEMsd_IMMb", XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb}, +{"CMPSD_XMM_XMMsd_XMMsd_IMMb", XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb}, +{"CMPSQ", XED_IFORM_CMPSQ}, +{"CMPSS_XMMss_MEMss_IMMb", XED_IFORM_CMPSS_XMMss_MEMss_IMMb}, +{"CMPSS_XMMss_XMMss_IMMb", XED_IFORM_CMPSS_XMMss_XMMss_IMMb}, +{"CMPSW", XED_IFORM_CMPSW}, +{"CMPXCHG_GPR8_GPR8", XED_IFORM_CMPXCHG_GPR8_GPR8}, +{"CMPXCHG_GPRv_GPRv", XED_IFORM_CMPXCHG_GPRv_GPRv}, +{"CMPXCHG_MEMb_GPR8", XED_IFORM_CMPXCHG_MEMb_GPR8}, +{"CMPXCHG_MEMv_GPRv", XED_IFORM_CMPXCHG_MEMv_GPRv}, +{"CMPXCHG16B_MEMdq", XED_IFORM_CMPXCHG16B_MEMdq}, +{"CMPXCHG16B_LOCK_MEMdq", XED_IFORM_CMPXCHG16B_LOCK_MEMdq}, +{"CMPXCHG8B_MEMq", XED_IFORM_CMPXCHG8B_MEMq}, +{"CMPXCHG8B_LOCK_MEMq", XED_IFORM_CMPXCHG8B_LOCK_MEMq}, +{"CMPXCHG_LOCK_MEMb_GPR8", XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8}, +{"CMPXCHG_LOCK_MEMv_GPRv", XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv}, +{"COMISD_XMMsd_MEMsd", XED_IFORM_COMISD_XMMsd_MEMsd}, +{"COMISD_XMMsd_XMMsd", XED_IFORM_COMISD_XMMsd_XMMsd}, +{"COMISS_XMMss_MEMss", XED_IFORM_COMISS_XMMss_MEMss}, +{"COMISS_XMMss_XMMss", XED_IFORM_COMISS_XMMss_XMMss}, +{"CPUID", XED_IFORM_CPUID}, +{"CQO", XED_IFORM_CQO}, +{"CRC32_GPRyy_GPR8b", XED_IFORM_CRC32_GPRyy_GPR8b}, +{"CRC32_GPRyy_GPRv", XED_IFORM_CRC32_GPRyy_GPRv}, +{"CRC32_GPRyy_MEMb", XED_IFORM_CRC32_GPRyy_MEMb}, +{"CRC32_GPRyy_MEMv", XED_IFORM_CRC32_GPRyy_MEMv}, +{"CVTDQ2PD_XMMpd_MEMq", XED_IFORM_CVTDQ2PD_XMMpd_MEMq}, +{"CVTDQ2PD_XMMpd_XMMq", XED_IFORM_CVTDQ2PD_XMMpd_XMMq}, +{"CVTDQ2PS_XMMps_MEMdq", XED_IFORM_CVTDQ2PS_XMMps_MEMdq}, +{"CVTDQ2PS_XMMps_XMMdq", XED_IFORM_CVTDQ2PS_XMMps_XMMdq}, +{"CVTPD2DQ_XMMdq_MEMpd", XED_IFORM_CVTPD2DQ_XMMdq_MEMpd}, +{"CVTPD2DQ_XMMdq_XMMpd", XED_IFORM_CVTPD2DQ_XMMdq_XMMpd}, +{"CVTPD2PI_MMXq_MEMpd", XED_IFORM_CVTPD2PI_MMXq_MEMpd}, +{"CVTPD2PI_MMXq_XMMpd", XED_IFORM_CVTPD2PI_MMXq_XMMpd}, +{"CVTPD2PS_XMMps_MEMpd", XED_IFORM_CVTPD2PS_XMMps_MEMpd}, +{"CVTPD2PS_XMMps_XMMpd", XED_IFORM_CVTPD2PS_XMMps_XMMpd}, +{"CVTPI2PD_XMMpd_MEMq", XED_IFORM_CVTPI2PD_XMMpd_MEMq}, +{"CVTPI2PD_XMMpd_MMXq", XED_IFORM_CVTPI2PD_XMMpd_MMXq}, +{"CVTPI2PS_XMMq_MEMq", XED_IFORM_CVTPI2PS_XMMq_MEMq}, +{"CVTPI2PS_XMMq_MMXq", XED_IFORM_CVTPI2PS_XMMq_MMXq}, +{"CVTPS2DQ_XMMdq_MEMps", XED_IFORM_CVTPS2DQ_XMMdq_MEMps}, +{"CVTPS2DQ_XMMdq_XMMps", XED_IFORM_CVTPS2DQ_XMMdq_XMMps}, +{"CVTPS2PD_XMMpd_MEMq", XED_IFORM_CVTPS2PD_XMMpd_MEMq}, +{"CVTPS2PD_XMMpd_XMMq", XED_IFORM_CVTPS2PD_XMMpd_XMMq}, +{"CVTPS2PI_MMXq_MEMq", XED_IFORM_CVTPS2PI_MMXq_MEMq}, +{"CVTPS2PI_MMXq_XMMq", XED_IFORM_CVTPS2PI_MMXq_XMMq}, +{"CVTSD2SI_GPR32d_MEMsd", XED_IFORM_CVTSD2SI_GPR32d_MEMsd}, +{"CVTSD2SI_GPR32d_XMMsd", XED_IFORM_CVTSD2SI_GPR32d_XMMsd}, +{"CVTSD2SI_GPR64q_MEMsd", XED_IFORM_CVTSD2SI_GPR64q_MEMsd}, +{"CVTSD2SI_GPR64q_XMMsd", XED_IFORM_CVTSD2SI_GPR64q_XMMsd}, +{"CVTSD2SS_XMMss_MEMsd", XED_IFORM_CVTSD2SS_XMMss_MEMsd}, +{"CVTSD2SS_XMMss_XMMsd", XED_IFORM_CVTSD2SS_XMMss_XMMsd}, +{"CVTSI2SD_XMMsd_GPR32d", XED_IFORM_CVTSI2SD_XMMsd_GPR32d}, +{"CVTSI2SD_XMMsd_GPR64q", XED_IFORM_CVTSI2SD_XMMsd_GPR64q}, +{"CVTSI2SD_XMMsd_MEMd", XED_IFORM_CVTSI2SD_XMMsd_MEMd}, +{"CVTSI2SD_XMMsd_MEMq", XED_IFORM_CVTSI2SD_XMMsd_MEMq}, +{"CVTSI2SS_XMMss_GPR32d", XED_IFORM_CVTSI2SS_XMMss_GPR32d}, +{"CVTSI2SS_XMMss_GPR64q", XED_IFORM_CVTSI2SS_XMMss_GPR64q}, +{"CVTSI2SS_XMMss_MEMd", XED_IFORM_CVTSI2SS_XMMss_MEMd}, +{"CVTSI2SS_XMMss_MEMq", XED_IFORM_CVTSI2SS_XMMss_MEMq}, +{"CVTSS2SD_XMMsd_MEMss", XED_IFORM_CVTSS2SD_XMMsd_MEMss}, +{"CVTSS2SD_XMMsd_XMMss", XED_IFORM_CVTSS2SD_XMMsd_XMMss}, +{"CVTSS2SI_GPR32d_MEMss", XED_IFORM_CVTSS2SI_GPR32d_MEMss}, +{"CVTSS2SI_GPR32d_XMMss", XED_IFORM_CVTSS2SI_GPR32d_XMMss}, +{"CVTSS2SI_GPR64q_MEMss", XED_IFORM_CVTSS2SI_GPR64q_MEMss}, +{"CVTSS2SI_GPR64q_XMMss", XED_IFORM_CVTSS2SI_GPR64q_XMMss}, +{"CVTTPD2DQ_XMMdq_MEMpd", XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd}, +{"CVTTPD2DQ_XMMdq_XMMpd", XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd}, +{"CVTTPD2PI_MMXq_MEMpd", XED_IFORM_CVTTPD2PI_MMXq_MEMpd}, +{"CVTTPD2PI_MMXq_XMMpd", XED_IFORM_CVTTPD2PI_MMXq_XMMpd}, +{"CVTTPS2DQ_XMMdq_MEMps", XED_IFORM_CVTTPS2DQ_XMMdq_MEMps}, +{"CVTTPS2DQ_XMMdq_XMMps", XED_IFORM_CVTTPS2DQ_XMMdq_XMMps}, +{"CVTTPS2PI_MMXq_MEMq", XED_IFORM_CVTTPS2PI_MMXq_MEMq}, +{"CVTTPS2PI_MMXq_XMMq", XED_IFORM_CVTTPS2PI_MMXq_XMMq}, +{"CVTTSD2SI_GPR32d_MEMsd", XED_IFORM_CVTTSD2SI_GPR32d_MEMsd}, +{"CVTTSD2SI_GPR32d_XMMsd", XED_IFORM_CVTTSD2SI_GPR32d_XMMsd}, +{"CVTTSD2SI_GPR64q_MEMsd", XED_IFORM_CVTTSD2SI_GPR64q_MEMsd}, +{"CVTTSD2SI_GPR64q_XMMsd", XED_IFORM_CVTTSD2SI_GPR64q_XMMsd}, +{"CVTTSS2SI_GPR32d_MEMss", XED_IFORM_CVTTSS2SI_GPR32d_MEMss}, +{"CVTTSS2SI_GPR32d_XMMss", XED_IFORM_CVTTSS2SI_GPR32d_XMMss}, +{"CVTTSS2SI_GPR64q_MEMss", XED_IFORM_CVTTSS2SI_GPR64q_MEMss}, +{"CVTTSS2SI_GPR64q_XMMss", XED_IFORM_CVTTSS2SI_GPR64q_XMMss}, +{"CWD", XED_IFORM_CWD}, +{"CWDE", XED_IFORM_CWDE}, +{"DAA", XED_IFORM_DAA}, +{"DAS", XED_IFORM_DAS}, +{"DEC_GPR8", XED_IFORM_DEC_GPR8}, +{"DEC_GPRv_48", XED_IFORM_DEC_GPRv_48}, +{"DEC_GPRv_FFr1", XED_IFORM_DEC_GPRv_FFr1}, +{"DEC_MEMb", XED_IFORM_DEC_MEMb}, +{"DEC_MEMv", XED_IFORM_DEC_MEMv}, +{"DEC_LOCK_MEMb", XED_IFORM_DEC_LOCK_MEMb}, +{"DEC_LOCK_MEMv", XED_IFORM_DEC_LOCK_MEMv}, +{"DIV_GPR8", XED_IFORM_DIV_GPR8}, +{"DIV_GPRv", XED_IFORM_DIV_GPRv}, +{"DIV_MEMb", XED_IFORM_DIV_MEMb}, +{"DIV_MEMv", XED_IFORM_DIV_MEMv}, +{"DIVPD_XMMpd_MEMpd", XED_IFORM_DIVPD_XMMpd_MEMpd}, +{"DIVPD_XMMpd_XMMpd", XED_IFORM_DIVPD_XMMpd_XMMpd}, +{"DIVPS_XMMps_MEMps", XED_IFORM_DIVPS_XMMps_MEMps}, +{"DIVPS_XMMps_XMMps", XED_IFORM_DIVPS_XMMps_XMMps}, +{"DIVSD_XMMsd_MEMsd", XED_IFORM_DIVSD_XMMsd_MEMsd}, +{"DIVSD_XMMsd_XMMsd", XED_IFORM_DIVSD_XMMsd_XMMsd}, +{"DIVSS_XMMss_MEMss", XED_IFORM_DIVSS_XMMss_MEMss}, +{"DIVSS_XMMss_XMMss", XED_IFORM_DIVSS_XMMss_XMMss}, +{"DPPD_XMMdq_MEMdq_IMMb", XED_IFORM_DPPD_XMMdq_MEMdq_IMMb}, +{"DPPD_XMMdq_XMMdq_IMMb", XED_IFORM_DPPD_XMMdq_XMMdq_IMMb}, +{"DPPS_XMMdq_MEMdq_IMMb", XED_IFORM_DPPS_XMMdq_MEMdq_IMMb}, +{"DPPS_XMMdq_XMMdq_IMMb", XED_IFORM_DPPS_XMMdq_XMMdq_IMMb}, +{"EMMS", XED_IFORM_EMMS}, +{"ENCLS", XED_IFORM_ENCLS}, +{"ENCLU", XED_IFORM_ENCLU}, +{"ENCLV", XED_IFORM_ENCLV}, +{"ENCODEKEY128_GPR32u8_GPR32u8", XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8}, +{"ENCODEKEY256_GPR32u8_GPR32u8", XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8}, +{"ENDBR32", XED_IFORM_ENDBR32}, +{"ENDBR64", XED_IFORM_ENDBR64}, +{"ENQCMD_GPRa_MEMu32", XED_IFORM_ENQCMD_GPRa_MEMu32}, +{"ENQCMDS_GPRa_MEMu32", XED_IFORM_ENQCMDS_GPRa_MEMu32}, +{"ENTER_IMMw_IMMb", XED_IFORM_ENTER_IMMw_IMMb}, +{"EXTRACTPS_GPR32d_XMMdq_IMMb", XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb}, +{"EXTRACTPS_MEMd_XMMps_IMMb", XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb}, +{"EXTRQ_XMMq_IMMb_IMMb", XED_IFORM_EXTRQ_XMMq_IMMb_IMMb}, +{"EXTRQ_XMMq_XMMdq", XED_IFORM_EXTRQ_XMMq_XMMdq}, +{"F2XM1", XED_IFORM_F2XM1}, +{"FABS", XED_IFORM_FABS}, +{"FADD_ST0_MEMm64real", XED_IFORM_FADD_ST0_MEMm64real}, +{"FADD_ST0_MEMmem32real", XED_IFORM_FADD_ST0_MEMmem32real}, +{"FADD_ST0_X87", XED_IFORM_FADD_ST0_X87}, +{"FADD_X87_ST0", XED_IFORM_FADD_X87_ST0}, +{"FADDP_X87_ST0", XED_IFORM_FADDP_X87_ST0}, +{"FBLD_ST0_MEMmem80dec", XED_IFORM_FBLD_ST0_MEMmem80dec}, +{"FBSTP_MEMmem80dec_ST0", XED_IFORM_FBSTP_MEMmem80dec_ST0}, +{"FCHS", XED_IFORM_FCHS}, +{"FCMOVB_ST0_X87", XED_IFORM_FCMOVB_ST0_X87}, +{"FCMOVBE_ST0_X87", XED_IFORM_FCMOVBE_ST0_X87}, +{"FCMOVE_ST0_X87", XED_IFORM_FCMOVE_ST0_X87}, +{"FCMOVNB_ST0_X87", XED_IFORM_FCMOVNB_ST0_X87}, +{"FCMOVNBE_ST0_X87", XED_IFORM_FCMOVNBE_ST0_X87}, +{"FCMOVNE_ST0_X87", XED_IFORM_FCMOVNE_ST0_X87}, +{"FCMOVNU_ST0_X87", XED_IFORM_FCMOVNU_ST0_X87}, +{"FCMOVU_ST0_X87", XED_IFORM_FCMOVU_ST0_X87}, +{"FCOM_ST0_MEMm64real", XED_IFORM_FCOM_ST0_MEMm64real}, +{"FCOM_ST0_MEMmem32real", XED_IFORM_FCOM_ST0_MEMmem32real}, +{"FCOM_ST0_X87", XED_IFORM_FCOM_ST0_X87}, +{"FCOM_ST0_X87_DCD0", XED_IFORM_FCOM_ST0_X87_DCD0}, +{"FCOMI_ST0_X87", XED_IFORM_FCOMI_ST0_X87}, +{"FCOMIP_ST0_X87", XED_IFORM_FCOMIP_ST0_X87}, +{"FCOMP_ST0_MEMm64real", XED_IFORM_FCOMP_ST0_MEMm64real}, +{"FCOMP_ST0_MEMmem32real", XED_IFORM_FCOMP_ST0_MEMmem32real}, +{"FCOMP_ST0_X87", XED_IFORM_FCOMP_ST0_X87}, +{"FCOMP_ST0_X87_DCD1", XED_IFORM_FCOMP_ST0_X87_DCD1}, +{"FCOMP_ST0_X87_DED0", XED_IFORM_FCOMP_ST0_X87_DED0}, +{"FCOMPP", XED_IFORM_FCOMPP}, +{"FCOS", XED_IFORM_FCOS}, +{"FDECSTP", XED_IFORM_FDECSTP}, +{"FDISI8087_NOP", XED_IFORM_FDISI8087_NOP}, +{"FDIV_ST0_MEMm64real", XED_IFORM_FDIV_ST0_MEMm64real}, +{"FDIV_ST0_MEMmem32real", XED_IFORM_FDIV_ST0_MEMmem32real}, +{"FDIV_ST0_X87", XED_IFORM_FDIV_ST0_X87}, +{"FDIV_X87_ST0", XED_IFORM_FDIV_X87_ST0}, +{"FDIVP_X87_ST0", XED_IFORM_FDIVP_X87_ST0}, +{"FDIVR_ST0_MEMm64real", XED_IFORM_FDIVR_ST0_MEMm64real}, +{"FDIVR_ST0_MEMmem32real", XED_IFORM_FDIVR_ST0_MEMmem32real}, +{"FDIVR_ST0_X87", XED_IFORM_FDIVR_ST0_X87}, +{"FDIVR_X87_ST0", XED_IFORM_FDIVR_X87_ST0}, +{"FDIVRP_X87_ST0", XED_IFORM_FDIVRP_X87_ST0}, +{"FEMMS", XED_IFORM_FEMMS}, +{"FENI8087_NOP", XED_IFORM_FENI8087_NOP}, +{"FFREE_X87", XED_IFORM_FFREE_X87}, +{"FFREEP_X87", XED_IFORM_FFREEP_X87}, +{"FIADD_ST0_MEMmem16int", XED_IFORM_FIADD_ST0_MEMmem16int}, +{"FIADD_ST0_MEMmem32int", XED_IFORM_FIADD_ST0_MEMmem32int}, +{"FICOM_ST0_MEMmem16int", XED_IFORM_FICOM_ST0_MEMmem16int}, +{"FICOM_ST0_MEMmem32int", XED_IFORM_FICOM_ST0_MEMmem32int}, +{"FICOMP_ST0_MEMmem16int", XED_IFORM_FICOMP_ST0_MEMmem16int}, +{"FICOMP_ST0_MEMmem32int", XED_IFORM_FICOMP_ST0_MEMmem32int}, +{"FIDIV_ST0_MEMmem16int", XED_IFORM_FIDIV_ST0_MEMmem16int}, +{"FIDIV_ST0_MEMmem32int", XED_IFORM_FIDIV_ST0_MEMmem32int}, +{"FIDIVR_ST0_MEMmem16int", XED_IFORM_FIDIVR_ST0_MEMmem16int}, +{"FIDIVR_ST0_MEMmem32int", XED_IFORM_FIDIVR_ST0_MEMmem32int}, +{"FILD_ST0_MEMm64int", XED_IFORM_FILD_ST0_MEMm64int}, +{"FILD_ST0_MEMmem16int", XED_IFORM_FILD_ST0_MEMmem16int}, +{"FILD_ST0_MEMmem32int", XED_IFORM_FILD_ST0_MEMmem32int}, +{"FIMUL_ST0_MEMmem16int", XED_IFORM_FIMUL_ST0_MEMmem16int}, +{"FIMUL_ST0_MEMmem32int", XED_IFORM_FIMUL_ST0_MEMmem32int}, +{"FINCSTP", XED_IFORM_FINCSTP}, +{"FIST_MEMmem16int_ST0", XED_IFORM_FIST_MEMmem16int_ST0}, +{"FIST_MEMmem32int_ST0", XED_IFORM_FIST_MEMmem32int_ST0}, +{"FISTP_MEMm64int_ST0", XED_IFORM_FISTP_MEMm64int_ST0}, +{"FISTP_MEMmem16int_ST0", XED_IFORM_FISTP_MEMmem16int_ST0}, +{"FISTP_MEMmem32int_ST0", XED_IFORM_FISTP_MEMmem32int_ST0}, +{"FISTTP_MEMm64int_ST0", XED_IFORM_FISTTP_MEMm64int_ST0}, +{"FISTTP_MEMmem16int_ST0", XED_IFORM_FISTTP_MEMmem16int_ST0}, +{"FISTTP_MEMmem32int_ST0", XED_IFORM_FISTTP_MEMmem32int_ST0}, +{"FISUB_ST0_MEMmem16int", XED_IFORM_FISUB_ST0_MEMmem16int}, +{"FISUB_ST0_MEMmem32int", XED_IFORM_FISUB_ST0_MEMmem32int}, +{"FISUBR_ST0_MEMmem16int", XED_IFORM_FISUBR_ST0_MEMmem16int}, +{"FISUBR_ST0_MEMmem32int", XED_IFORM_FISUBR_ST0_MEMmem32int}, +{"FLD_ST0_MEMm64real", XED_IFORM_FLD_ST0_MEMm64real}, +{"FLD_ST0_MEMmem32real", XED_IFORM_FLD_ST0_MEMmem32real}, +{"FLD_ST0_MEMmem80real", XED_IFORM_FLD_ST0_MEMmem80real}, +{"FLD_ST0_X87", XED_IFORM_FLD_ST0_X87}, +{"FLD1", XED_IFORM_FLD1}, +{"FLDCW_MEMmem16", XED_IFORM_FLDCW_MEMmem16}, +{"FLDENV_MEMmem14", XED_IFORM_FLDENV_MEMmem14}, +{"FLDENV_MEMmem28", XED_IFORM_FLDENV_MEMmem28}, +{"FLDL2E", XED_IFORM_FLDL2E}, +{"FLDL2T", XED_IFORM_FLDL2T}, +{"FLDLG2", XED_IFORM_FLDLG2}, +{"FLDLN2", XED_IFORM_FLDLN2}, +{"FLDPI", XED_IFORM_FLDPI}, +{"FLDZ", XED_IFORM_FLDZ}, +{"FMUL_ST0_MEMm64real", XED_IFORM_FMUL_ST0_MEMm64real}, +{"FMUL_ST0_MEMmem32real", XED_IFORM_FMUL_ST0_MEMmem32real}, +{"FMUL_ST0_X87", XED_IFORM_FMUL_ST0_X87}, +{"FMUL_X87_ST0", XED_IFORM_FMUL_X87_ST0}, +{"FMULP_X87_ST0", XED_IFORM_FMULP_X87_ST0}, +{"FNCLEX", XED_IFORM_FNCLEX}, +{"FNINIT", XED_IFORM_FNINIT}, +{"FNOP", XED_IFORM_FNOP}, +{"FNSAVE_MEMmem108", XED_IFORM_FNSAVE_MEMmem108}, +{"FNSAVE_MEMmem94", XED_IFORM_FNSAVE_MEMmem94}, +{"FNSTCW_MEMmem16", XED_IFORM_FNSTCW_MEMmem16}, +{"FNSTENV_MEMmem14", XED_IFORM_FNSTENV_MEMmem14}, +{"FNSTENV_MEMmem28", XED_IFORM_FNSTENV_MEMmem28}, +{"FNSTSW_AX", XED_IFORM_FNSTSW_AX}, +{"FNSTSW_MEMmem16", XED_IFORM_FNSTSW_MEMmem16}, +{"FPATAN", XED_IFORM_FPATAN}, +{"FPREM", XED_IFORM_FPREM}, +{"FPREM1", XED_IFORM_FPREM1}, +{"FPTAN", XED_IFORM_FPTAN}, +{"FRNDINT", XED_IFORM_FRNDINT}, +{"FRSTOR_MEMmem108", XED_IFORM_FRSTOR_MEMmem108}, +{"FRSTOR_MEMmem94", XED_IFORM_FRSTOR_MEMmem94}, +{"FSCALE", XED_IFORM_FSCALE}, +{"FSETPM287_NOP", XED_IFORM_FSETPM287_NOP}, +{"FSIN", XED_IFORM_FSIN}, +{"FSINCOS", XED_IFORM_FSINCOS}, +{"FSQRT", XED_IFORM_FSQRT}, +{"FST_MEMm64real_ST0", XED_IFORM_FST_MEMm64real_ST0}, +{"FST_MEMmem32real_ST0", XED_IFORM_FST_MEMmem32real_ST0}, +{"FST_X87_ST0", XED_IFORM_FST_X87_ST0}, +{"FSTP_MEMm64real_ST0", XED_IFORM_FSTP_MEMm64real_ST0}, +{"FSTP_MEMmem32real_ST0", XED_IFORM_FSTP_MEMmem32real_ST0}, +{"FSTP_MEMmem80real_ST0", XED_IFORM_FSTP_MEMmem80real_ST0}, +{"FSTP_X87_ST0", XED_IFORM_FSTP_X87_ST0}, +{"FSTP_X87_ST0_DFD0", XED_IFORM_FSTP_X87_ST0_DFD0}, +{"FSTP_X87_ST0_DFD1", XED_IFORM_FSTP_X87_ST0_DFD1}, +{"FSTPNCE_X87_ST0", XED_IFORM_FSTPNCE_X87_ST0}, +{"FSUB_ST0_MEMm64real", XED_IFORM_FSUB_ST0_MEMm64real}, +{"FSUB_ST0_MEMmem32real", XED_IFORM_FSUB_ST0_MEMmem32real}, +{"FSUB_ST0_X87", XED_IFORM_FSUB_ST0_X87}, +{"FSUB_X87_ST0", XED_IFORM_FSUB_X87_ST0}, +{"FSUBP_X87_ST0", XED_IFORM_FSUBP_X87_ST0}, +{"FSUBR_ST0_MEMm64real", XED_IFORM_FSUBR_ST0_MEMm64real}, +{"FSUBR_ST0_MEMmem32real", XED_IFORM_FSUBR_ST0_MEMmem32real}, +{"FSUBR_ST0_X87", XED_IFORM_FSUBR_ST0_X87}, +{"FSUBR_X87_ST0", XED_IFORM_FSUBR_X87_ST0}, +{"FSUBRP_X87_ST0", XED_IFORM_FSUBRP_X87_ST0}, +{"FTST", XED_IFORM_FTST}, +{"FUCOM_ST0_X87", XED_IFORM_FUCOM_ST0_X87}, +{"FUCOMI_ST0_X87", XED_IFORM_FUCOMI_ST0_X87}, +{"FUCOMIP_ST0_X87", XED_IFORM_FUCOMIP_ST0_X87}, +{"FUCOMP_ST0_X87", XED_IFORM_FUCOMP_ST0_X87}, +{"FUCOMPP", XED_IFORM_FUCOMPP}, +{"FWAIT", XED_IFORM_FWAIT}, +{"FXAM", XED_IFORM_FXAM}, +{"FXCH_ST0_X87", XED_IFORM_FXCH_ST0_X87}, +{"FXCH_ST0_X87_DDC1", XED_IFORM_FXCH_ST0_X87_DDC1}, +{"FXCH_ST0_X87_DFC1", XED_IFORM_FXCH_ST0_X87_DFC1}, +{"FXRSTOR_MEMmfpxenv", XED_IFORM_FXRSTOR_MEMmfpxenv}, +{"FXRSTOR64_MEMmfpxenv", XED_IFORM_FXRSTOR64_MEMmfpxenv}, +{"FXSAVE_MEMmfpxenv", XED_IFORM_FXSAVE_MEMmfpxenv}, +{"FXSAVE64_MEMmfpxenv", XED_IFORM_FXSAVE64_MEMmfpxenv}, +{"FXTRACT", XED_IFORM_FXTRACT}, +{"FYL2X", XED_IFORM_FYL2X}, +{"FYL2XP1", XED_IFORM_FYL2XP1}, +{"GETSEC", XED_IFORM_GETSEC}, +{"GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8", XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8}, +{"GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8", XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8}, +{"GF2P8AFFINEQB_XMMu8_MEMu64_IMM8", XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8}, +{"GF2P8AFFINEQB_XMMu8_XMMu64_IMM8", XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8}, +{"GF2P8MULB_XMMu8_MEMu8", XED_IFORM_GF2P8MULB_XMMu8_MEMu8}, +{"GF2P8MULB_XMMu8_XMMu8", XED_IFORM_GF2P8MULB_XMMu8_XMMu8}, +{"HADDPD_XMMpd_MEMpd", XED_IFORM_HADDPD_XMMpd_MEMpd}, +{"HADDPD_XMMpd_XMMpd", XED_IFORM_HADDPD_XMMpd_XMMpd}, +{"HADDPS_XMMps_MEMps", XED_IFORM_HADDPS_XMMps_MEMps}, +{"HADDPS_XMMps_XMMps", XED_IFORM_HADDPS_XMMps_XMMps}, +{"HLT", XED_IFORM_HLT}, +{"HRESET_IMM8", XED_IFORM_HRESET_IMM8}, +{"HSUBPD_XMMpd_MEMpd", XED_IFORM_HSUBPD_XMMpd_MEMpd}, +{"HSUBPD_XMMpd_XMMpd", XED_IFORM_HSUBPD_XMMpd_XMMpd}, +{"HSUBPS_XMMps_MEMps", XED_IFORM_HSUBPS_XMMps_MEMps}, +{"HSUBPS_XMMps_XMMps", XED_IFORM_HSUBPS_XMMps_XMMps}, +{"IDIV_GPR8", XED_IFORM_IDIV_GPR8}, +{"IDIV_GPRv", XED_IFORM_IDIV_GPRv}, +{"IDIV_MEMb", XED_IFORM_IDIV_MEMb}, +{"IDIV_MEMv", XED_IFORM_IDIV_MEMv}, +{"IMUL_GPR8", XED_IFORM_IMUL_GPR8}, +{"IMUL_GPRv", XED_IFORM_IMUL_GPRv}, +{"IMUL_GPRv_GPRv", XED_IFORM_IMUL_GPRv_GPRv}, +{"IMUL_GPRv_GPRv_IMMb", XED_IFORM_IMUL_GPRv_GPRv_IMMb}, +{"IMUL_GPRv_GPRv_IMMz", XED_IFORM_IMUL_GPRv_GPRv_IMMz}, +{"IMUL_GPRv_MEMv", XED_IFORM_IMUL_GPRv_MEMv}, +{"IMUL_GPRv_MEMv_IMMb", XED_IFORM_IMUL_GPRv_MEMv_IMMb}, +{"IMUL_GPRv_MEMv_IMMz", XED_IFORM_IMUL_GPRv_MEMv_IMMz}, +{"IMUL_MEMb", XED_IFORM_IMUL_MEMb}, +{"IMUL_MEMv", XED_IFORM_IMUL_MEMv}, +{"IN_AL_DX", XED_IFORM_IN_AL_DX}, +{"IN_AL_IMMb", XED_IFORM_IN_AL_IMMb}, +{"IN_OeAX_DX", XED_IFORM_IN_OeAX_DX}, +{"IN_OeAX_IMMb", XED_IFORM_IN_OeAX_IMMb}, +{"INC_GPR8", XED_IFORM_INC_GPR8}, +{"INC_GPRv_40", XED_IFORM_INC_GPRv_40}, +{"INC_GPRv_FFr0", XED_IFORM_INC_GPRv_FFr0}, +{"INC_MEMb", XED_IFORM_INC_MEMb}, +{"INC_MEMv", XED_IFORM_INC_MEMv}, +{"INCSSPD_GPR32u8", XED_IFORM_INCSSPD_GPR32u8}, +{"INCSSPQ_GPR64u8", XED_IFORM_INCSSPQ_GPR64u8}, +{"INC_LOCK_MEMb", XED_IFORM_INC_LOCK_MEMb}, +{"INC_LOCK_MEMv", XED_IFORM_INC_LOCK_MEMv}, +{"INSB", XED_IFORM_INSB}, +{"INSD", XED_IFORM_INSD}, +{"INSERTPS_XMMps_MEMd_IMMb", XED_IFORM_INSERTPS_XMMps_MEMd_IMMb}, +{"INSERTPS_XMMps_XMMps_IMMb", XED_IFORM_INSERTPS_XMMps_XMMps_IMMb}, +{"INSERTQ_XMMq_XMMdq", XED_IFORM_INSERTQ_XMMq_XMMdq}, +{"INSERTQ_XMMq_XMMq_IMMb_IMMb", XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb}, +{"INSW", XED_IFORM_INSW}, +{"INT_IMMb", XED_IFORM_INT_IMMb}, +{"INT1", XED_IFORM_INT1}, +{"INT3", XED_IFORM_INT3}, +{"INTO", XED_IFORM_INTO}, +{"INVD", XED_IFORM_INVD}, +{"INVEPT_GPR32_MEMdq", XED_IFORM_INVEPT_GPR32_MEMdq}, +{"INVEPT_GPR64_MEMdq", XED_IFORM_INVEPT_GPR64_MEMdq}, +{"INVLPG_MEMb", XED_IFORM_INVLPG_MEMb}, +{"INVLPGA_ArAX_ECX", XED_IFORM_INVLPGA_ArAX_ECX}, +{"INVLPGB_EAX_EDX_ECX", XED_IFORM_INVLPGB_EAX_EDX_ECX}, +{"INVLPGB_RAX_EDX_ECX", XED_IFORM_INVLPGB_RAX_EDX_ECX}, +{"INVPCID_GPR32_MEMdq", XED_IFORM_INVPCID_GPR32_MEMdq}, +{"INVPCID_GPR64_MEMdq", XED_IFORM_INVPCID_GPR64_MEMdq}, +{"INVVPID_GPR32_MEMdq", XED_IFORM_INVVPID_GPR32_MEMdq}, +{"INVVPID_GPR64_MEMdq", XED_IFORM_INVVPID_GPR64_MEMdq}, +{"IRET", XED_IFORM_IRET}, +{"IRETD", XED_IFORM_IRETD}, +{"IRETQ", XED_IFORM_IRETQ}, +{"JB_RELBRb", XED_IFORM_JB_RELBRb}, +{"JB_RELBRd", XED_IFORM_JB_RELBRd}, +{"JB_RELBRz", XED_IFORM_JB_RELBRz}, +{"JBE_RELBRb", XED_IFORM_JBE_RELBRb}, +{"JBE_RELBRd", XED_IFORM_JBE_RELBRd}, +{"JBE_RELBRz", XED_IFORM_JBE_RELBRz}, +{"JCXZ_RELBRb", XED_IFORM_JCXZ_RELBRb}, +{"JECXZ_RELBRb", XED_IFORM_JECXZ_RELBRb}, +{"JL_RELBRb", XED_IFORM_JL_RELBRb}, +{"JL_RELBRd", XED_IFORM_JL_RELBRd}, +{"JL_RELBRz", XED_IFORM_JL_RELBRz}, +{"JLE_RELBRb", XED_IFORM_JLE_RELBRb}, +{"JLE_RELBRd", XED_IFORM_JLE_RELBRd}, +{"JLE_RELBRz", XED_IFORM_JLE_RELBRz}, +{"JMP_GPRv", XED_IFORM_JMP_GPRv}, +{"JMP_MEMv", XED_IFORM_JMP_MEMv}, +{"JMP_RELBRb", XED_IFORM_JMP_RELBRb}, +{"JMP_RELBRd", XED_IFORM_JMP_RELBRd}, +{"JMP_RELBRz", XED_IFORM_JMP_RELBRz}, +{"JMP_FAR_MEMp2", XED_IFORM_JMP_FAR_MEMp2}, +{"JMP_FAR_PTRp_IMMw", XED_IFORM_JMP_FAR_PTRp_IMMw}, +{"JNB_RELBRb", XED_IFORM_JNB_RELBRb}, +{"JNB_RELBRd", XED_IFORM_JNB_RELBRd}, +{"JNB_RELBRz", XED_IFORM_JNB_RELBRz}, +{"JNBE_RELBRb", XED_IFORM_JNBE_RELBRb}, +{"JNBE_RELBRd", XED_IFORM_JNBE_RELBRd}, +{"JNBE_RELBRz", XED_IFORM_JNBE_RELBRz}, +{"JNL_RELBRb", XED_IFORM_JNL_RELBRb}, +{"JNL_RELBRd", XED_IFORM_JNL_RELBRd}, +{"JNL_RELBRz", XED_IFORM_JNL_RELBRz}, +{"JNLE_RELBRb", XED_IFORM_JNLE_RELBRb}, +{"JNLE_RELBRd", XED_IFORM_JNLE_RELBRd}, +{"JNLE_RELBRz", XED_IFORM_JNLE_RELBRz}, +{"JNO_RELBRb", XED_IFORM_JNO_RELBRb}, +{"JNO_RELBRd", XED_IFORM_JNO_RELBRd}, +{"JNO_RELBRz", XED_IFORM_JNO_RELBRz}, +{"JNP_RELBRb", XED_IFORM_JNP_RELBRb}, +{"JNP_RELBRd", XED_IFORM_JNP_RELBRd}, +{"JNP_RELBRz", XED_IFORM_JNP_RELBRz}, +{"JNS_RELBRb", XED_IFORM_JNS_RELBRb}, +{"JNS_RELBRd", XED_IFORM_JNS_RELBRd}, +{"JNS_RELBRz", XED_IFORM_JNS_RELBRz}, +{"JNZ_RELBRb", XED_IFORM_JNZ_RELBRb}, +{"JNZ_RELBRd", XED_IFORM_JNZ_RELBRd}, +{"JNZ_RELBRz", XED_IFORM_JNZ_RELBRz}, +{"JO_RELBRb", XED_IFORM_JO_RELBRb}, +{"JO_RELBRd", XED_IFORM_JO_RELBRd}, +{"JO_RELBRz", XED_IFORM_JO_RELBRz}, +{"JP_RELBRb", XED_IFORM_JP_RELBRb}, +{"JP_RELBRd", XED_IFORM_JP_RELBRd}, +{"JP_RELBRz", XED_IFORM_JP_RELBRz}, +{"JRCXZ_RELBRb", XED_IFORM_JRCXZ_RELBRb}, +{"JS_RELBRb", XED_IFORM_JS_RELBRb}, +{"JS_RELBRd", XED_IFORM_JS_RELBRd}, +{"JS_RELBRz", XED_IFORM_JS_RELBRz}, +{"JZ_RELBRb", XED_IFORM_JZ_RELBRb}, +{"JZ_RELBRd", XED_IFORM_JZ_RELBRd}, +{"JZ_RELBRz", XED_IFORM_JZ_RELBRz}, +{"KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KMOVB_GPR32u32_MASKmskw_AVX512", XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512}, +{"KMOVB_MASKmskw_GPR32u32_AVX512", XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512}, +{"KMOVB_MASKmskw_MASKu8_AVX512", XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512}, +{"KMOVB_MASKmskw_MEMu8_AVX512", XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512}, +{"KMOVB_MEMu8_MASKmskw_AVX512", XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512}, +{"KMOVD_GPR32u32_MASKmskw_AVX512", XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512}, +{"KMOVD_MASKmskw_GPR32u32_AVX512", XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512}, +{"KMOVD_MASKmskw_MASKu32_AVX512", XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512}, +{"KMOVD_MASKmskw_MEMu32_AVX512", XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512}, +{"KMOVD_MEMu32_MASKmskw_AVX512", XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512}, +{"KMOVQ_GPR64u64_MASKmskw_AVX512", XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512}, +{"KMOVQ_MASKmskw_GPR64u64_AVX512", XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512}, +{"KMOVQ_MASKmskw_MASKu64_AVX512", XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512}, +{"KMOVQ_MASKmskw_MEMu64_AVX512", XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512}, +{"KMOVQ_MEMu64_MASKmskw_AVX512", XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512}, +{"KMOVW_GPR32u32_MASKmskw_AVX512", XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512}, +{"KMOVW_MASKmskw_GPR32u32_AVX512", XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512}, +{"KMOVW_MASKmskw_MASKu16_AVX512", XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512}, +{"KMOVW_MASKmskw_MEMu16_AVX512", XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512}, +{"KMOVW_MEMu16_MASKmskw_AVX512", XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512}, +{"KNOTB_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512}, +{"KNOTD_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512}, +{"KNOTQ_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512}, +{"KNOTW_MASKmskw_MASKmskw_AVX512", XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512}, +{"KORB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KORD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KORTESTB_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512}, +{"KORTESTD_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512}, +{"KORTESTQ_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512}, +{"KORTESTW_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512}, +{"KORW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512", XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512}, +{"KTESTB_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512}, +{"KTESTD_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512}, +{"KTESTQ_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512}, +{"KTESTW_MASKmskw_MASKmskw_AVX512", XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512}, +{"KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512", XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512}, +{"LAHF", XED_IFORM_LAHF}, +{"LAR_GPRv_GPRv", XED_IFORM_LAR_GPRv_GPRv}, +{"LAR_GPRv_MEMw", XED_IFORM_LAR_GPRv_MEMw}, +{"LDDQU_XMMpd_MEMdq", XED_IFORM_LDDQU_XMMpd_MEMdq}, +{"LDMXCSR_MEMd", XED_IFORM_LDMXCSR_MEMd}, +{"LDS_GPRz_MEMp", XED_IFORM_LDS_GPRz_MEMp}, +{"LDTILECFG_MEM", XED_IFORM_LDTILECFG_MEM}, +{"LEA_GPRv_AGEN", XED_IFORM_LEA_GPRv_AGEN}, +{"LEAVE", XED_IFORM_LEAVE}, +{"LES_GPRz_MEMp", XED_IFORM_LES_GPRz_MEMp}, +{"LFENCE", XED_IFORM_LFENCE}, +{"LFS_GPRv_MEMp2", XED_IFORM_LFS_GPRv_MEMp2}, +{"LGDT_MEMs", XED_IFORM_LGDT_MEMs}, +{"LGDT_MEMs64", XED_IFORM_LGDT_MEMs64}, +{"LGS_GPRv_MEMp2", XED_IFORM_LGS_GPRv_MEMp2}, +{"LIDT_MEMs", XED_IFORM_LIDT_MEMs}, +{"LIDT_MEMs64", XED_IFORM_LIDT_MEMs64}, +{"LLDT_GPR16", XED_IFORM_LLDT_GPR16}, +{"LLDT_MEMw", XED_IFORM_LLDT_MEMw}, +{"LLWPCB_VGPRyy", XED_IFORM_LLWPCB_VGPRyy}, +{"LMSW_GPR16", XED_IFORM_LMSW_GPR16}, +{"LMSW_MEMw", XED_IFORM_LMSW_MEMw}, +{"LOADIWKEY_XMMu8_XMMu8", XED_IFORM_LOADIWKEY_XMMu8_XMMu8}, +{"LODSB", XED_IFORM_LODSB}, +{"LODSD", XED_IFORM_LODSD}, +{"LODSQ", XED_IFORM_LODSQ}, +{"LODSW", XED_IFORM_LODSW}, +{"LOOP_RELBRb", XED_IFORM_LOOP_RELBRb}, +{"LOOPE_RELBRb", XED_IFORM_LOOPE_RELBRb}, +{"LOOPNE_RELBRb", XED_IFORM_LOOPNE_RELBRb}, +{"LSL_GPRv_GPRz", XED_IFORM_LSL_GPRv_GPRz}, +{"LSL_GPRv_MEMw", XED_IFORM_LSL_GPRv_MEMw}, +{"LSS_GPRv_MEMp2", XED_IFORM_LSS_GPRv_MEMp2}, +{"LTR_GPR16", XED_IFORM_LTR_GPR16}, +{"LTR_MEMw", XED_IFORM_LTR_MEMw}, +{"LWPINS_VGPRyy_MEMd_IMMd", XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd}, +{"LWPINS_VGPRyy_VGPR32y_IMMd", XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd}, +{"LWPVAL_VGPRyy_MEMd_IMMd", XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd}, +{"LWPVAL_VGPRyy_VGPR32y_IMMd", XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd}, +{"LZCNT_GPRv_GPRv", XED_IFORM_LZCNT_GPRv_GPRv}, +{"LZCNT_GPRv_MEMv", XED_IFORM_LZCNT_GPRv_MEMv}, +{"MASKMOVDQU_XMMdq_XMMdq", XED_IFORM_MASKMOVDQU_XMMdq_XMMdq}, +{"MASKMOVQ_MMXq_MMXq", XED_IFORM_MASKMOVQ_MMXq_MMXq}, +{"MAXPD_XMMpd_MEMpd", XED_IFORM_MAXPD_XMMpd_MEMpd}, +{"MAXPD_XMMpd_XMMpd", XED_IFORM_MAXPD_XMMpd_XMMpd}, +{"MAXPS_XMMps_MEMps", XED_IFORM_MAXPS_XMMps_MEMps}, +{"MAXPS_XMMps_XMMps", XED_IFORM_MAXPS_XMMps_XMMps}, +{"MAXSD_XMMsd_MEMsd", XED_IFORM_MAXSD_XMMsd_MEMsd}, +{"MAXSD_XMMsd_XMMsd", XED_IFORM_MAXSD_XMMsd_XMMsd}, +{"MAXSS_XMMss_MEMss", XED_IFORM_MAXSS_XMMss_MEMss}, +{"MAXSS_XMMss_XMMss", XED_IFORM_MAXSS_XMMss_XMMss}, +{"MCOMMIT", XED_IFORM_MCOMMIT}, +{"MFENCE", XED_IFORM_MFENCE}, +{"MINPD_XMMpd_MEMpd", XED_IFORM_MINPD_XMMpd_MEMpd}, +{"MINPD_XMMpd_XMMpd", XED_IFORM_MINPD_XMMpd_XMMpd}, +{"MINPS_XMMps_MEMps", XED_IFORM_MINPS_XMMps_MEMps}, +{"MINPS_XMMps_XMMps", XED_IFORM_MINPS_XMMps_XMMps}, +{"MINSD_XMMsd_MEMsd", XED_IFORM_MINSD_XMMsd_MEMsd}, +{"MINSD_XMMsd_XMMsd", XED_IFORM_MINSD_XMMsd_XMMsd}, +{"MINSS_XMMss_MEMss", XED_IFORM_MINSS_XMMss_MEMss}, +{"MINSS_XMMss_XMMss", XED_IFORM_MINSS_XMMss_XMMss}, +{"MONITOR", XED_IFORM_MONITOR}, +{"MONITORX", XED_IFORM_MONITORX}, +{"MOV_AL_MEMb", XED_IFORM_MOV_AL_MEMb}, +{"MOV_GPR8_GPR8_88", XED_IFORM_MOV_GPR8_GPR8_88}, +{"MOV_GPR8_GPR8_8A", XED_IFORM_MOV_GPR8_GPR8_8A}, +{"MOV_GPR8_IMMb_B0", XED_IFORM_MOV_GPR8_IMMb_B0}, +{"MOV_GPR8_IMMb_C6r0", XED_IFORM_MOV_GPR8_IMMb_C6r0}, +{"MOV_GPR8_MEMb", XED_IFORM_MOV_GPR8_MEMb}, +{"MOV_GPRv_GPRv_89", XED_IFORM_MOV_GPRv_GPRv_89}, +{"MOV_GPRv_GPRv_8B", XED_IFORM_MOV_GPRv_GPRv_8B}, +{"MOV_GPRv_IMMv", XED_IFORM_MOV_GPRv_IMMv}, +{"MOV_GPRv_IMMz", XED_IFORM_MOV_GPRv_IMMz}, +{"MOV_GPRv_MEMv", XED_IFORM_MOV_GPRv_MEMv}, +{"MOV_GPRv_SEG", XED_IFORM_MOV_GPRv_SEG}, +{"MOV_MEMb_AL", XED_IFORM_MOV_MEMb_AL}, +{"MOV_MEMb_GPR8", XED_IFORM_MOV_MEMb_GPR8}, +{"MOV_MEMb_IMMb", XED_IFORM_MOV_MEMb_IMMb}, +{"MOV_MEMv_GPRv", XED_IFORM_MOV_MEMv_GPRv}, +{"MOV_MEMv_IMMz", XED_IFORM_MOV_MEMv_IMMz}, +{"MOV_MEMv_OrAX", XED_IFORM_MOV_MEMv_OrAX}, +{"MOV_MEMw_SEG", XED_IFORM_MOV_MEMw_SEG}, +{"MOV_OrAX_MEMv", XED_IFORM_MOV_OrAX_MEMv}, +{"MOV_SEG_GPR16", XED_IFORM_MOV_SEG_GPR16}, +{"MOV_SEG_MEMw", XED_IFORM_MOV_SEG_MEMw}, +{"MOVAPD_MEMpd_XMMpd", XED_IFORM_MOVAPD_MEMpd_XMMpd}, +{"MOVAPD_XMMpd_MEMpd", XED_IFORM_MOVAPD_XMMpd_MEMpd}, +{"MOVAPD_XMMpd_XMMpd_0F28", XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28}, +{"MOVAPD_XMMpd_XMMpd_0F29", XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29}, +{"MOVAPS_MEMps_XMMps", XED_IFORM_MOVAPS_MEMps_XMMps}, +{"MOVAPS_XMMps_MEMps", XED_IFORM_MOVAPS_XMMps_MEMps}, +{"MOVAPS_XMMps_XMMps_0F28", XED_IFORM_MOVAPS_XMMps_XMMps_0F28}, +{"MOVAPS_XMMps_XMMps_0F29", XED_IFORM_MOVAPS_XMMps_XMMps_0F29}, +{"MOVBE_GPRv_MEMv", XED_IFORM_MOVBE_GPRv_MEMv}, +{"MOVBE_MEMv_GPRv", XED_IFORM_MOVBE_MEMv_GPRv}, +{"MOVD_GPR32_MMXd", XED_IFORM_MOVD_GPR32_MMXd}, +{"MOVD_GPR32_XMMd", XED_IFORM_MOVD_GPR32_XMMd}, +{"MOVD_MEMd_MMXd", XED_IFORM_MOVD_MEMd_MMXd}, +{"MOVD_MEMd_XMMd", XED_IFORM_MOVD_MEMd_XMMd}, +{"MOVD_MMXq_GPR32", XED_IFORM_MOVD_MMXq_GPR32}, +{"MOVD_MMXq_MEMd", XED_IFORM_MOVD_MMXq_MEMd}, +{"MOVD_XMMdq_GPR32", XED_IFORM_MOVD_XMMdq_GPR32}, +{"MOVD_XMMdq_MEMd", XED_IFORM_MOVD_XMMdq_MEMd}, +{"MOVDDUP_XMMdq_MEMq", XED_IFORM_MOVDDUP_XMMdq_MEMq}, +{"MOVDDUP_XMMdq_XMMq", XED_IFORM_MOVDDUP_XMMdq_XMMq}, +{"MOVDIR64B_GPRa_MEM", XED_IFORM_MOVDIR64B_GPRa_MEM}, +{"MOVDIRI_MEMu32_GPR32u32", XED_IFORM_MOVDIRI_MEMu32_GPR32u32}, +{"MOVDIRI_MEMu64_GPR64u64", XED_IFORM_MOVDIRI_MEMu64_GPR64u64}, +{"MOVDQ2Q_MMXq_XMMq", XED_IFORM_MOVDQ2Q_MMXq_XMMq}, +{"MOVDQA_MEMdq_XMMdq", XED_IFORM_MOVDQA_MEMdq_XMMdq}, +{"MOVDQA_XMMdq_MEMdq", XED_IFORM_MOVDQA_XMMdq_MEMdq}, +{"MOVDQA_XMMdq_XMMdq_0F6F", XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F}, +{"MOVDQA_XMMdq_XMMdq_0F7F", XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F}, +{"MOVDQU_MEMdq_XMMdq", XED_IFORM_MOVDQU_MEMdq_XMMdq}, +{"MOVDQU_XMMdq_MEMdq", XED_IFORM_MOVDQU_XMMdq_MEMdq}, +{"MOVDQU_XMMdq_XMMdq_0F6F", XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F}, +{"MOVDQU_XMMdq_XMMdq_0F7F", XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F}, +{"MOVHLPS_XMMq_XMMq", XED_IFORM_MOVHLPS_XMMq_XMMq}, +{"MOVHPD_MEMq_XMMsd", XED_IFORM_MOVHPD_MEMq_XMMsd}, +{"MOVHPD_XMMsd_MEMq", XED_IFORM_MOVHPD_XMMsd_MEMq}, +{"MOVHPS_MEMq_XMMps", XED_IFORM_MOVHPS_MEMq_XMMps}, +{"MOVHPS_XMMq_MEMq", XED_IFORM_MOVHPS_XMMq_MEMq}, +{"MOVLHPS_XMMq_XMMq", XED_IFORM_MOVLHPS_XMMq_XMMq}, +{"MOVLPD_MEMq_XMMsd", XED_IFORM_MOVLPD_MEMq_XMMsd}, +{"MOVLPD_XMMsd_MEMq", XED_IFORM_MOVLPD_XMMsd_MEMq}, +{"MOVLPS_MEMq_XMMq", XED_IFORM_MOVLPS_MEMq_XMMq}, +{"MOVLPS_XMMq_MEMq", XED_IFORM_MOVLPS_XMMq_MEMq}, +{"MOVMSKPD_GPR32_XMMpd", XED_IFORM_MOVMSKPD_GPR32_XMMpd}, +{"MOVMSKPS_GPR32_XMMps", XED_IFORM_MOVMSKPS_GPR32_XMMps}, +{"MOVNTDQ_MEMdq_XMMdq", XED_IFORM_MOVNTDQ_MEMdq_XMMdq}, +{"MOVNTDQA_XMMdq_MEMdq", XED_IFORM_MOVNTDQA_XMMdq_MEMdq}, +{"MOVNTI_MEMd_GPR32", XED_IFORM_MOVNTI_MEMd_GPR32}, +{"MOVNTI_MEMq_GPR64", XED_IFORM_MOVNTI_MEMq_GPR64}, +{"MOVNTPD_MEMdq_XMMpd", XED_IFORM_MOVNTPD_MEMdq_XMMpd}, +{"MOVNTPS_MEMdq_XMMps", XED_IFORM_MOVNTPS_MEMdq_XMMps}, +{"MOVNTQ_MEMq_MMXq", XED_IFORM_MOVNTQ_MEMq_MMXq}, +{"MOVNTSD_MEMq_XMMq", XED_IFORM_MOVNTSD_MEMq_XMMq}, +{"MOVNTSS_MEMd_XMMd", XED_IFORM_MOVNTSS_MEMd_XMMd}, +{"MOVQ_GPR64_MMXq", XED_IFORM_MOVQ_GPR64_MMXq}, +{"MOVQ_GPR64_XMMq", XED_IFORM_MOVQ_GPR64_XMMq}, +{"MOVQ_MEMq_MMXq_0F7E", XED_IFORM_MOVQ_MEMq_MMXq_0F7E}, +{"MOVQ_MEMq_MMXq_0F7F", XED_IFORM_MOVQ_MEMq_MMXq_0F7F}, +{"MOVQ_MEMq_XMMq_0F7E", XED_IFORM_MOVQ_MEMq_XMMq_0F7E}, +{"MOVQ_MEMq_XMMq_0FD6", XED_IFORM_MOVQ_MEMq_XMMq_0FD6}, +{"MOVQ_MMXq_GPR64", XED_IFORM_MOVQ_MMXq_GPR64}, +{"MOVQ_MMXq_MEMq_0F6E", XED_IFORM_MOVQ_MMXq_MEMq_0F6E}, +{"MOVQ_MMXq_MEMq_0F6F", XED_IFORM_MOVQ_MMXq_MEMq_0F6F}, +{"MOVQ_MMXq_MMXq_0F6F", XED_IFORM_MOVQ_MMXq_MMXq_0F6F}, +{"MOVQ_MMXq_MMXq_0F7F", XED_IFORM_MOVQ_MMXq_MMXq_0F7F}, +{"MOVQ_XMMdq_GPR64", XED_IFORM_MOVQ_XMMdq_GPR64}, +{"MOVQ_XMMdq_MEMq_0F6E", XED_IFORM_MOVQ_XMMdq_MEMq_0F6E}, +{"MOVQ_XMMdq_MEMq_0F7E", XED_IFORM_MOVQ_XMMdq_MEMq_0F7E}, +{"MOVQ_XMMdq_XMMq_0F7E", XED_IFORM_MOVQ_XMMdq_XMMq_0F7E}, +{"MOVQ_XMMdq_XMMq_0FD6", XED_IFORM_MOVQ_XMMdq_XMMq_0FD6}, +{"MOVQ2DQ_XMMdq_MMXq", XED_IFORM_MOVQ2DQ_XMMdq_MMXq}, +{"MOVSB", XED_IFORM_MOVSB}, +{"MOVSD", XED_IFORM_MOVSD}, +{"MOVSD_XMM_MEMsd_XMMsd", XED_IFORM_MOVSD_XMM_MEMsd_XMMsd}, +{"MOVSD_XMM_XMMdq_MEMsd", XED_IFORM_MOVSD_XMM_XMMdq_MEMsd}, +{"MOVSD_XMM_XMMsd_XMMsd_0F10", XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10}, +{"MOVSD_XMM_XMMsd_XMMsd_0F11", XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11}, +{"MOVSHDUP_XMMps_MEMps", XED_IFORM_MOVSHDUP_XMMps_MEMps}, +{"MOVSHDUP_XMMps_XMMps", XED_IFORM_MOVSHDUP_XMMps_XMMps}, +{"MOVSLDUP_XMMps_MEMps", XED_IFORM_MOVSLDUP_XMMps_MEMps}, +{"MOVSLDUP_XMMps_XMMps", XED_IFORM_MOVSLDUP_XMMps_XMMps}, +{"MOVSQ", XED_IFORM_MOVSQ}, +{"MOVSS_MEMss_XMMss", XED_IFORM_MOVSS_MEMss_XMMss}, +{"MOVSS_XMMdq_MEMss", XED_IFORM_MOVSS_XMMdq_MEMss}, +{"MOVSS_XMMss_XMMss_0F10", XED_IFORM_MOVSS_XMMss_XMMss_0F10}, +{"MOVSS_XMMss_XMMss_0F11", XED_IFORM_MOVSS_XMMss_XMMss_0F11}, +{"MOVSW", XED_IFORM_MOVSW}, +{"MOVSX_GPRv_GPR16", XED_IFORM_MOVSX_GPRv_GPR16}, +{"MOVSX_GPRv_GPR8", XED_IFORM_MOVSX_GPRv_GPR8}, +{"MOVSX_GPRv_MEMb", XED_IFORM_MOVSX_GPRv_MEMb}, +{"MOVSX_GPRv_MEMw", XED_IFORM_MOVSX_GPRv_MEMw}, +{"MOVSXD_GPRv_GPRz", XED_IFORM_MOVSXD_GPRv_GPRz}, +{"MOVSXD_GPRv_MEMz", XED_IFORM_MOVSXD_GPRv_MEMz}, +{"MOVUPD_MEMpd_XMMpd", XED_IFORM_MOVUPD_MEMpd_XMMpd}, +{"MOVUPD_XMMpd_MEMpd", XED_IFORM_MOVUPD_XMMpd_MEMpd}, +{"MOVUPD_XMMpd_XMMpd_0F10", XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10}, +{"MOVUPD_XMMpd_XMMpd_0F11", XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11}, +{"MOVUPS_MEMps_XMMps", XED_IFORM_MOVUPS_MEMps_XMMps}, +{"MOVUPS_XMMps_MEMps", XED_IFORM_MOVUPS_XMMps_MEMps}, +{"MOVUPS_XMMps_XMMps_0F10", XED_IFORM_MOVUPS_XMMps_XMMps_0F10}, +{"MOVUPS_XMMps_XMMps_0F11", XED_IFORM_MOVUPS_XMMps_XMMps_0F11}, +{"MOVZX_GPRv_GPR16", XED_IFORM_MOVZX_GPRv_GPR16}, +{"MOVZX_GPRv_GPR8", XED_IFORM_MOVZX_GPRv_GPR8}, +{"MOVZX_GPRv_MEMb", XED_IFORM_MOVZX_GPRv_MEMb}, +{"MOVZX_GPRv_MEMw", XED_IFORM_MOVZX_GPRv_MEMw}, +{"MOV_CR_CR_GPR32", XED_IFORM_MOV_CR_CR_GPR32}, +{"MOV_CR_CR_GPR64", XED_IFORM_MOV_CR_CR_GPR64}, +{"MOV_CR_GPR32_CR", XED_IFORM_MOV_CR_GPR32_CR}, +{"MOV_CR_GPR64_CR", XED_IFORM_MOV_CR_GPR64_CR}, +{"MOV_DR_DR_GPR32", XED_IFORM_MOV_DR_DR_GPR32}, +{"MOV_DR_DR_GPR64", XED_IFORM_MOV_DR_DR_GPR64}, +{"MOV_DR_GPR32_DR", XED_IFORM_MOV_DR_GPR32_DR}, +{"MOV_DR_GPR64_DR", XED_IFORM_MOV_DR_GPR64_DR}, +{"MPSADBW_XMMdq_MEMdq_IMMb", XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb}, +{"MPSADBW_XMMdq_XMMdq_IMMb", XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb}, +{"MUL_GPR8", XED_IFORM_MUL_GPR8}, +{"MUL_GPRv", XED_IFORM_MUL_GPRv}, +{"MUL_MEMb", XED_IFORM_MUL_MEMb}, +{"MUL_MEMv", XED_IFORM_MUL_MEMv}, +{"MULPD_XMMpd_MEMpd", XED_IFORM_MULPD_XMMpd_MEMpd}, +{"MULPD_XMMpd_XMMpd", XED_IFORM_MULPD_XMMpd_XMMpd}, +{"MULPS_XMMps_MEMps", XED_IFORM_MULPS_XMMps_MEMps}, +{"MULPS_XMMps_XMMps", XED_IFORM_MULPS_XMMps_XMMps}, +{"MULSD_XMMsd_MEMsd", XED_IFORM_MULSD_XMMsd_MEMsd}, +{"MULSD_XMMsd_XMMsd", XED_IFORM_MULSD_XMMsd_XMMsd}, +{"MULSS_XMMss_MEMss", XED_IFORM_MULSS_XMMss_MEMss}, +{"MULSS_XMMss_XMMss", XED_IFORM_MULSS_XMMss_XMMss}, +{"MULX_VGPR32d_VGPR32d_MEMd", XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd}, +{"MULX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d}, +{"MULX_VGPR64q_VGPR64q_MEMq", XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq}, +{"MULX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q}, +{"MWAIT", XED_IFORM_MWAIT}, +{"MWAITX", XED_IFORM_MWAITX}, +{"NEG_GPR8", XED_IFORM_NEG_GPR8}, +{"NEG_GPRv", XED_IFORM_NEG_GPRv}, +{"NEG_MEMb", XED_IFORM_NEG_MEMb}, +{"NEG_MEMv", XED_IFORM_NEG_MEMv}, +{"NEG_LOCK_MEMb", XED_IFORM_NEG_LOCK_MEMb}, +{"NEG_LOCK_MEMv", XED_IFORM_NEG_LOCK_MEMv}, +{"NOP_90", XED_IFORM_NOP_90}, +{"NOP_GPRv_0F18r0", XED_IFORM_NOP_GPRv_0F18r0}, +{"NOP_GPRv_0F18r1", XED_IFORM_NOP_GPRv_0F18r1}, +{"NOP_GPRv_0F18r2", XED_IFORM_NOP_GPRv_0F18r2}, +{"NOP_GPRv_0F18r3", XED_IFORM_NOP_GPRv_0F18r3}, +{"NOP_GPRv_0F18r4", XED_IFORM_NOP_GPRv_0F18r4}, +{"NOP_GPRv_0F18r5", XED_IFORM_NOP_GPRv_0F18r5}, +{"NOP_GPRv_0F18r6", XED_IFORM_NOP_GPRv_0F18r6}, +{"NOP_GPRv_0F18r7", XED_IFORM_NOP_GPRv_0F18r7}, +{"NOP_GPRv_GPRv_0F0D", XED_IFORM_NOP_GPRv_GPRv_0F0D}, +{"NOP_GPRv_GPRv_0F19", XED_IFORM_NOP_GPRv_GPRv_0F19}, +{"NOP_GPRv_GPRv_0F1A", XED_IFORM_NOP_GPRv_GPRv_0F1A}, +{"NOP_GPRv_GPRv_0F1B", XED_IFORM_NOP_GPRv_GPRv_0F1B}, +{"NOP_GPRv_GPRv_0F1C", XED_IFORM_NOP_GPRv_GPRv_0F1C}, +{"NOP_GPRv_GPRv_0F1D", XED_IFORM_NOP_GPRv_GPRv_0F1D}, +{"NOP_GPRv_GPRv_0F1E", XED_IFORM_NOP_GPRv_GPRv_0F1E}, +{"NOP_GPRv_GPRv_0F1F", XED_IFORM_NOP_GPRv_GPRv_0F1F}, +{"NOP_GPRv_MEM_0F1B", XED_IFORM_NOP_GPRv_MEM_0F1B}, +{"NOP_GPRv_MEMv_0F1A", XED_IFORM_NOP_GPRv_MEMv_0F1A}, +{"NOP_MEMv_0F18r4", XED_IFORM_NOP_MEMv_0F18r4}, +{"NOP_MEMv_0F18r5", XED_IFORM_NOP_MEMv_0F18r5}, +{"NOP_MEMv_0F18r6", XED_IFORM_NOP_MEMv_0F18r6}, +{"NOP_MEMv_0F18r7", XED_IFORM_NOP_MEMv_0F18r7}, +{"NOP_MEMv_GPRv_0F19", XED_IFORM_NOP_MEMv_GPRv_0F19}, +{"NOP_MEMv_GPRv_0F1C", XED_IFORM_NOP_MEMv_GPRv_0F1C}, +{"NOP_MEMv_GPRv_0F1D", XED_IFORM_NOP_MEMv_GPRv_0F1D}, +{"NOP_MEMv_GPRv_0F1E", XED_IFORM_NOP_MEMv_GPRv_0F1E}, +{"NOP_MEMv_GPRv_0F1F", XED_IFORM_NOP_MEMv_GPRv_0F1F}, +{"NOT_GPR8", XED_IFORM_NOT_GPR8}, +{"NOT_GPRv", XED_IFORM_NOT_GPRv}, +{"NOT_MEMb", XED_IFORM_NOT_MEMb}, +{"NOT_MEMv", XED_IFORM_NOT_MEMv}, +{"NOT_LOCK_MEMb", XED_IFORM_NOT_LOCK_MEMb}, +{"NOT_LOCK_MEMv", XED_IFORM_NOT_LOCK_MEMv}, +{"OR_AL_IMMb", XED_IFORM_OR_AL_IMMb}, +{"OR_GPR8_GPR8_08", XED_IFORM_OR_GPR8_GPR8_08}, +{"OR_GPR8_GPR8_0A", XED_IFORM_OR_GPR8_GPR8_0A}, +{"OR_GPR8_IMMb_80r1", XED_IFORM_OR_GPR8_IMMb_80r1}, +{"OR_GPR8_IMMb_82r1", XED_IFORM_OR_GPR8_IMMb_82r1}, +{"OR_GPR8_MEMb", XED_IFORM_OR_GPR8_MEMb}, +{"OR_GPRv_GPRv_09", XED_IFORM_OR_GPRv_GPRv_09}, +{"OR_GPRv_GPRv_0B", XED_IFORM_OR_GPRv_GPRv_0B}, +{"OR_GPRv_IMMb", XED_IFORM_OR_GPRv_IMMb}, +{"OR_GPRv_IMMz", XED_IFORM_OR_GPRv_IMMz}, +{"OR_GPRv_MEMv", XED_IFORM_OR_GPRv_MEMv}, +{"OR_MEMb_GPR8", XED_IFORM_OR_MEMb_GPR8}, +{"OR_MEMb_IMMb_80r1", XED_IFORM_OR_MEMb_IMMb_80r1}, +{"OR_MEMb_IMMb_82r1", XED_IFORM_OR_MEMb_IMMb_82r1}, +{"OR_MEMv_GPRv", XED_IFORM_OR_MEMv_GPRv}, +{"OR_MEMv_IMMb", XED_IFORM_OR_MEMv_IMMb}, +{"OR_MEMv_IMMz", XED_IFORM_OR_MEMv_IMMz}, +{"OR_OrAX_IMMz", XED_IFORM_OR_OrAX_IMMz}, +{"ORPD_XMMxuq_MEMxuq", XED_IFORM_ORPD_XMMxuq_MEMxuq}, +{"ORPD_XMMxuq_XMMxuq", XED_IFORM_ORPD_XMMxuq_XMMxuq}, +{"ORPS_XMMxud_MEMxud", XED_IFORM_ORPS_XMMxud_MEMxud}, +{"ORPS_XMMxud_XMMxud", XED_IFORM_ORPS_XMMxud_XMMxud}, +{"OR_LOCK_MEMb_GPR8", XED_IFORM_OR_LOCK_MEMb_GPR8}, +{"OR_LOCK_MEMb_IMMb_80r1", XED_IFORM_OR_LOCK_MEMb_IMMb_80r1}, +{"OR_LOCK_MEMb_IMMb_82r1", XED_IFORM_OR_LOCK_MEMb_IMMb_82r1}, +{"OR_LOCK_MEMv_GPRv", XED_IFORM_OR_LOCK_MEMv_GPRv}, +{"OR_LOCK_MEMv_IMMb", XED_IFORM_OR_LOCK_MEMv_IMMb}, +{"OR_LOCK_MEMv_IMMz", XED_IFORM_OR_LOCK_MEMv_IMMz}, +{"OUT_DX_AL", XED_IFORM_OUT_DX_AL}, +{"OUT_DX_OeAX", XED_IFORM_OUT_DX_OeAX}, +{"OUT_IMMb_AL", XED_IFORM_OUT_IMMb_AL}, +{"OUT_IMMb_OeAX", XED_IFORM_OUT_IMMb_OeAX}, +{"OUTSB", XED_IFORM_OUTSB}, +{"OUTSD", XED_IFORM_OUTSD}, +{"OUTSW", XED_IFORM_OUTSW}, +{"PABSB_MMXq_MEMq", XED_IFORM_PABSB_MMXq_MEMq}, +{"PABSB_MMXq_MMXq", XED_IFORM_PABSB_MMXq_MMXq}, +{"PABSB_XMMdq_MEMdq", XED_IFORM_PABSB_XMMdq_MEMdq}, +{"PABSB_XMMdq_XMMdq", XED_IFORM_PABSB_XMMdq_XMMdq}, +{"PABSD_MMXq_MEMq", XED_IFORM_PABSD_MMXq_MEMq}, +{"PABSD_MMXq_MMXq", XED_IFORM_PABSD_MMXq_MMXq}, +{"PABSD_XMMdq_MEMdq", XED_IFORM_PABSD_XMMdq_MEMdq}, +{"PABSD_XMMdq_XMMdq", XED_IFORM_PABSD_XMMdq_XMMdq}, +{"PABSW_MMXq_MEMq", XED_IFORM_PABSW_MMXq_MEMq}, +{"PABSW_MMXq_MMXq", XED_IFORM_PABSW_MMXq_MMXq}, +{"PABSW_XMMdq_MEMdq", XED_IFORM_PABSW_XMMdq_MEMdq}, +{"PABSW_XMMdq_XMMdq", XED_IFORM_PABSW_XMMdq_XMMdq}, +{"PACKSSDW_MMXq_MEMq", XED_IFORM_PACKSSDW_MMXq_MEMq}, +{"PACKSSDW_MMXq_MMXq", XED_IFORM_PACKSSDW_MMXq_MMXq}, +{"PACKSSDW_XMMdq_MEMdq", XED_IFORM_PACKSSDW_XMMdq_MEMdq}, +{"PACKSSDW_XMMdq_XMMdq", XED_IFORM_PACKSSDW_XMMdq_XMMdq}, +{"PACKSSWB_MMXq_MEMq", XED_IFORM_PACKSSWB_MMXq_MEMq}, +{"PACKSSWB_MMXq_MMXq", XED_IFORM_PACKSSWB_MMXq_MMXq}, +{"PACKSSWB_XMMdq_MEMdq", XED_IFORM_PACKSSWB_XMMdq_MEMdq}, +{"PACKSSWB_XMMdq_XMMdq", XED_IFORM_PACKSSWB_XMMdq_XMMdq}, +{"PACKUSDW_XMMdq_MEMdq", XED_IFORM_PACKUSDW_XMMdq_MEMdq}, +{"PACKUSDW_XMMdq_XMMdq", XED_IFORM_PACKUSDW_XMMdq_XMMdq}, +{"PACKUSWB_MMXq_MEMq", XED_IFORM_PACKUSWB_MMXq_MEMq}, +{"PACKUSWB_MMXq_MMXq", XED_IFORM_PACKUSWB_MMXq_MMXq}, +{"PACKUSWB_XMMdq_MEMdq", XED_IFORM_PACKUSWB_XMMdq_MEMdq}, +{"PACKUSWB_XMMdq_XMMdq", XED_IFORM_PACKUSWB_XMMdq_XMMdq}, +{"PADDB_MMXq_MEMq", XED_IFORM_PADDB_MMXq_MEMq}, +{"PADDB_MMXq_MMXq", XED_IFORM_PADDB_MMXq_MMXq}, +{"PADDB_XMMdq_MEMdq", XED_IFORM_PADDB_XMMdq_MEMdq}, +{"PADDB_XMMdq_XMMdq", XED_IFORM_PADDB_XMMdq_XMMdq}, +{"PADDD_MMXq_MEMq", XED_IFORM_PADDD_MMXq_MEMq}, +{"PADDD_MMXq_MMXq", XED_IFORM_PADDD_MMXq_MMXq}, +{"PADDD_XMMdq_MEMdq", XED_IFORM_PADDD_XMMdq_MEMdq}, +{"PADDD_XMMdq_XMMdq", XED_IFORM_PADDD_XMMdq_XMMdq}, +{"PADDQ_MMXq_MEMq", XED_IFORM_PADDQ_MMXq_MEMq}, +{"PADDQ_MMXq_MMXq", XED_IFORM_PADDQ_MMXq_MMXq}, +{"PADDQ_XMMdq_MEMdq", XED_IFORM_PADDQ_XMMdq_MEMdq}, +{"PADDQ_XMMdq_XMMdq", XED_IFORM_PADDQ_XMMdq_XMMdq}, +{"PADDSB_MMXq_MEMq", XED_IFORM_PADDSB_MMXq_MEMq}, +{"PADDSB_MMXq_MMXq", XED_IFORM_PADDSB_MMXq_MMXq}, +{"PADDSB_XMMdq_MEMdq", XED_IFORM_PADDSB_XMMdq_MEMdq}, +{"PADDSB_XMMdq_XMMdq", XED_IFORM_PADDSB_XMMdq_XMMdq}, +{"PADDSW_MMXq_MEMq", XED_IFORM_PADDSW_MMXq_MEMq}, +{"PADDSW_MMXq_MMXq", XED_IFORM_PADDSW_MMXq_MMXq}, +{"PADDSW_XMMdq_MEMdq", XED_IFORM_PADDSW_XMMdq_MEMdq}, +{"PADDSW_XMMdq_XMMdq", XED_IFORM_PADDSW_XMMdq_XMMdq}, +{"PADDUSB_MMXq_MEMq", XED_IFORM_PADDUSB_MMXq_MEMq}, +{"PADDUSB_MMXq_MMXq", XED_IFORM_PADDUSB_MMXq_MMXq}, +{"PADDUSB_XMMdq_MEMdq", XED_IFORM_PADDUSB_XMMdq_MEMdq}, +{"PADDUSB_XMMdq_XMMdq", XED_IFORM_PADDUSB_XMMdq_XMMdq}, +{"PADDUSW_MMXq_MEMq", XED_IFORM_PADDUSW_MMXq_MEMq}, +{"PADDUSW_MMXq_MMXq", XED_IFORM_PADDUSW_MMXq_MMXq}, +{"PADDUSW_XMMdq_MEMdq", XED_IFORM_PADDUSW_XMMdq_MEMdq}, +{"PADDUSW_XMMdq_XMMdq", XED_IFORM_PADDUSW_XMMdq_XMMdq}, +{"PADDW_MMXq_MEMq", XED_IFORM_PADDW_MMXq_MEMq}, +{"PADDW_MMXq_MMXq", XED_IFORM_PADDW_MMXq_MMXq}, +{"PADDW_XMMdq_MEMdq", XED_IFORM_PADDW_XMMdq_MEMdq}, +{"PADDW_XMMdq_XMMdq", XED_IFORM_PADDW_XMMdq_XMMdq}, +{"PALIGNR_MMXq_MEMq_IMMb", XED_IFORM_PALIGNR_MMXq_MEMq_IMMb}, +{"PALIGNR_MMXq_MMXq_IMMb", XED_IFORM_PALIGNR_MMXq_MMXq_IMMb}, +{"PALIGNR_XMMdq_MEMdq_IMMb", XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb}, +{"PALIGNR_XMMdq_XMMdq_IMMb", XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb}, +{"PAND_MMXq_MEMq", XED_IFORM_PAND_MMXq_MEMq}, +{"PAND_MMXq_MMXq", XED_IFORM_PAND_MMXq_MMXq}, +{"PAND_XMMdq_MEMdq", XED_IFORM_PAND_XMMdq_MEMdq}, +{"PAND_XMMdq_XMMdq", XED_IFORM_PAND_XMMdq_XMMdq}, +{"PANDN_MMXq_MEMq", XED_IFORM_PANDN_MMXq_MEMq}, +{"PANDN_MMXq_MMXq", XED_IFORM_PANDN_MMXq_MMXq}, +{"PANDN_XMMdq_MEMdq", XED_IFORM_PANDN_XMMdq_MEMdq}, +{"PANDN_XMMdq_XMMdq", XED_IFORM_PANDN_XMMdq_XMMdq}, +{"PAUSE", XED_IFORM_PAUSE}, +{"PAVGB_MMXq_MEMq", XED_IFORM_PAVGB_MMXq_MEMq}, +{"PAVGB_MMXq_MMXq", XED_IFORM_PAVGB_MMXq_MMXq}, +{"PAVGB_XMMdq_MEMdq", XED_IFORM_PAVGB_XMMdq_MEMdq}, +{"PAVGB_XMMdq_XMMdq", XED_IFORM_PAVGB_XMMdq_XMMdq}, +{"PAVGUSB_MMXq_MEMq", XED_IFORM_PAVGUSB_MMXq_MEMq}, +{"PAVGUSB_MMXq_MMXq", XED_IFORM_PAVGUSB_MMXq_MMXq}, +{"PAVGW_MMXq_MEMq", XED_IFORM_PAVGW_MMXq_MEMq}, +{"PAVGW_MMXq_MMXq", XED_IFORM_PAVGW_MMXq_MMXq}, +{"PAVGW_XMMdq_MEMdq", XED_IFORM_PAVGW_XMMdq_MEMdq}, +{"PAVGW_XMMdq_XMMdq", XED_IFORM_PAVGW_XMMdq_XMMdq}, +{"PBLENDVB_XMMdq_MEMdq", XED_IFORM_PBLENDVB_XMMdq_MEMdq}, +{"PBLENDVB_XMMdq_XMMdq", XED_IFORM_PBLENDVB_XMMdq_XMMdq}, +{"PBLENDW_XMMdq_MEMdq_IMMb", XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb}, +{"PBLENDW_XMMdq_XMMdq_IMMb", XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb}, +{"PCLMULQDQ_XMMdq_MEMdq_IMMb", XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb}, +{"PCLMULQDQ_XMMdq_XMMdq_IMMb", XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb}, +{"PCMPEQB_MMXq_MEMq", XED_IFORM_PCMPEQB_MMXq_MEMq}, +{"PCMPEQB_MMXq_MMXq", XED_IFORM_PCMPEQB_MMXq_MMXq}, +{"PCMPEQB_XMMdq_MEMdq", XED_IFORM_PCMPEQB_XMMdq_MEMdq}, +{"PCMPEQB_XMMdq_XMMdq", XED_IFORM_PCMPEQB_XMMdq_XMMdq}, +{"PCMPEQD_MMXq_MEMq", XED_IFORM_PCMPEQD_MMXq_MEMq}, +{"PCMPEQD_MMXq_MMXq", XED_IFORM_PCMPEQD_MMXq_MMXq}, +{"PCMPEQD_XMMdq_MEMdq", XED_IFORM_PCMPEQD_XMMdq_MEMdq}, +{"PCMPEQD_XMMdq_XMMdq", XED_IFORM_PCMPEQD_XMMdq_XMMdq}, +{"PCMPEQQ_XMMdq_MEMdq", XED_IFORM_PCMPEQQ_XMMdq_MEMdq}, +{"PCMPEQQ_XMMdq_XMMdq", XED_IFORM_PCMPEQQ_XMMdq_XMMdq}, +{"PCMPEQW_MMXq_MEMq", XED_IFORM_PCMPEQW_MMXq_MEMq}, +{"PCMPEQW_MMXq_MMXq", XED_IFORM_PCMPEQW_MMXq_MMXq}, +{"PCMPEQW_XMMdq_MEMdq", XED_IFORM_PCMPEQW_XMMdq_MEMdq}, +{"PCMPEQW_XMMdq_XMMdq", XED_IFORM_PCMPEQW_XMMdq_XMMdq}, +{"PCMPESTRI_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb}, +{"PCMPESTRI_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb}, +{"PCMPESTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb}, +{"PCMPESTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb}, +{"PCMPESTRM_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb}, +{"PCMPESTRM_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb}, +{"PCMPESTRM64_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb}, +{"PCMPESTRM64_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb}, +{"PCMPGTB_MMXq_MEMq", XED_IFORM_PCMPGTB_MMXq_MEMq}, +{"PCMPGTB_MMXq_MMXq", XED_IFORM_PCMPGTB_MMXq_MMXq}, +{"PCMPGTB_XMMdq_MEMdq", XED_IFORM_PCMPGTB_XMMdq_MEMdq}, +{"PCMPGTB_XMMdq_XMMdq", XED_IFORM_PCMPGTB_XMMdq_XMMdq}, +{"PCMPGTD_MMXq_MEMq", XED_IFORM_PCMPGTD_MMXq_MEMq}, +{"PCMPGTD_MMXq_MMXq", XED_IFORM_PCMPGTD_MMXq_MMXq}, +{"PCMPGTD_XMMdq_MEMdq", XED_IFORM_PCMPGTD_XMMdq_MEMdq}, +{"PCMPGTD_XMMdq_XMMdq", XED_IFORM_PCMPGTD_XMMdq_XMMdq}, +{"PCMPGTQ_XMMdq_MEMdq", XED_IFORM_PCMPGTQ_XMMdq_MEMdq}, +{"PCMPGTQ_XMMdq_XMMdq", XED_IFORM_PCMPGTQ_XMMdq_XMMdq}, +{"PCMPGTW_MMXq_MEMq", XED_IFORM_PCMPGTW_MMXq_MEMq}, +{"PCMPGTW_MMXq_MMXq", XED_IFORM_PCMPGTW_MMXq_MMXq}, +{"PCMPGTW_XMMdq_MEMdq", XED_IFORM_PCMPGTW_XMMdq_MEMdq}, +{"PCMPGTW_XMMdq_XMMdq", XED_IFORM_PCMPGTW_XMMdq_XMMdq}, +{"PCMPISTRI_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb}, +{"PCMPISTRI_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb}, +{"PCMPISTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb}, +{"PCMPISTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb}, +{"PCMPISTRM_XMMdq_MEMdq_IMMb", XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb}, +{"PCMPISTRM_XMMdq_XMMdq_IMMb", XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb}, +{"PCONFIG", XED_IFORM_PCONFIG}, +{"PCONFIG64", XED_IFORM_PCONFIG64}, +{"PDEP_VGPR32d_VGPR32d_MEMd", XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd}, +{"PDEP_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d}, +{"PDEP_VGPR64q_VGPR64q_MEMq", XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq}, +{"PDEP_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q}, +{"PEXT_VGPR32d_VGPR32d_MEMd", XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd}, +{"PEXT_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d}, +{"PEXT_VGPR64q_VGPR64q_MEMq", XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq}, +{"PEXT_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q}, +{"PEXTRB_GPR32d_XMMdq_IMMb", XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb}, +{"PEXTRB_MEMb_XMMdq_IMMb", XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb}, +{"PEXTRD_GPR32d_XMMdq_IMMb", XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb}, +{"PEXTRD_MEMd_XMMdq_IMMb", XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb}, +{"PEXTRQ_GPR64q_XMMdq_IMMb", XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb}, +{"PEXTRQ_MEMq_XMMdq_IMMb", XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb}, +{"PEXTRW_GPR32_MMXq_IMMb", XED_IFORM_PEXTRW_GPR32_MMXq_IMMb}, +{"PEXTRW_GPR32_XMMdq_IMMb", XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb}, +{"PEXTRW_SSE4_GPR32_XMMdq_IMMb", XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb}, +{"PEXTRW_SSE4_MEMw_XMMdq_IMMb", XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb}, +{"PF2ID_MMXq_MEMq", XED_IFORM_PF2ID_MMXq_MEMq}, +{"PF2ID_MMXq_MMXq", XED_IFORM_PF2ID_MMXq_MMXq}, +{"PF2IW_MMXq_MEMq", XED_IFORM_PF2IW_MMXq_MEMq}, +{"PF2IW_MMXq_MMXq", XED_IFORM_PF2IW_MMXq_MMXq}, +{"PFACC_MMXq_MEMq", XED_IFORM_PFACC_MMXq_MEMq}, +{"PFACC_MMXq_MMXq", XED_IFORM_PFACC_MMXq_MMXq}, +{"PFADD_MMXq_MEMq", XED_IFORM_PFADD_MMXq_MEMq}, +{"PFADD_MMXq_MMXq", XED_IFORM_PFADD_MMXq_MMXq}, +{"PFCMPEQ_MMXq_MEMq", XED_IFORM_PFCMPEQ_MMXq_MEMq}, +{"PFCMPEQ_MMXq_MMXq", XED_IFORM_PFCMPEQ_MMXq_MMXq}, +{"PFCMPGE_MMXq_MEMq", XED_IFORM_PFCMPGE_MMXq_MEMq}, +{"PFCMPGE_MMXq_MMXq", XED_IFORM_PFCMPGE_MMXq_MMXq}, +{"PFCMPGT_MMXq_MEMq", XED_IFORM_PFCMPGT_MMXq_MEMq}, +{"PFCMPGT_MMXq_MMXq", XED_IFORM_PFCMPGT_MMXq_MMXq}, +{"PFMAX_MMXq_MEMq", XED_IFORM_PFMAX_MMXq_MEMq}, +{"PFMAX_MMXq_MMXq", XED_IFORM_PFMAX_MMXq_MMXq}, +{"PFMIN_MMXq_MEMq", XED_IFORM_PFMIN_MMXq_MEMq}, +{"PFMIN_MMXq_MMXq", XED_IFORM_PFMIN_MMXq_MMXq}, +{"PFMUL_MMXq_MEMq", XED_IFORM_PFMUL_MMXq_MEMq}, +{"PFMUL_MMXq_MMXq", XED_IFORM_PFMUL_MMXq_MMXq}, +{"PFNACC_MMXq_MEMq", XED_IFORM_PFNACC_MMXq_MEMq}, +{"PFNACC_MMXq_MMXq", XED_IFORM_PFNACC_MMXq_MMXq}, +{"PFPNACC_MMXq_MEMq", XED_IFORM_PFPNACC_MMXq_MEMq}, +{"PFPNACC_MMXq_MMXq", XED_IFORM_PFPNACC_MMXq_MMXq}, +{"PFRCP_MMXq_MEMq", XED_IFORM_PFRCP_MMXq_MEMq}, +{"PFRCP_MMXq_MMXq", XED_IFORM_PFRCP_MMXq_MMXq}, +{"PFRCPIT1_MMXq_MEMq", XED_IFORM_PFRCPIT1_MMXq_MEMq}, +{"PFRCPIT1_MMXq_MMXq", XED_IFORM_PFRCPIT1_MMXq_MMXq}, +{"PFRCPIT2_MMXq_MEMq", XED_IFORM_PFRCPIT2_MMXq_MEMq}, +{"PFRCPIT2_MMXq_MMXq", XED_IFORM_PFRCPIT2_MMXq_MMXq}, +{"PFRSQIT1_MMXq_MEMq", XED_IFORM_PFRSQIT1_MMXq_MEMq}, +{"PFRSQIT1_MMXq_MMXq", XED_IFORM_PFRSQIT1_MMXq_MMXq}, +{"PFRSQRT_MMXq_MEMq", XED_IFORM_PFRSQRT_MMXq_MEMq}, +{"PFRSQRT_MMXq_MMXq", XED_IFORM_PFRSQRT_MMXq_MMXq}, +{"PFSUB_MMXq_MEMq", XED_IFORM_PFSUB_MMXq_MEMq}, +{"PFSUB_MMXq_MMXq", XED_IFORM_PFSUB_MMXq_MMXq}, +{"PFSUBR_MMXq_MEMq", XED_IFORM_PFSUBR_MMXq_MEMq}, +{"PFSUBR_MMXq_MMXq", XED_IFORM_PFSUBR_MMXq_MMXq}, +{"PHADDD_MMXq_MEMq", XED_IFORM_PHADDD_MMXq_MEMq}, +{"PHADDD_MMXq_MMXq", XED_IFORM_PHADDD_MMXq_MMXq}, +{"PHADDD_XMMdq_MEMdq", XED_IFORM_PHADDD_XMMdq_MEMdq}, +{"PHADDD_XMMdq_XMMdq", XED_IFORM_PHADDD_XMMdq_XMMdq}, +{"PHADDSW_MMXq_MEMq", XED_IFORM_PHADDSW_MMXq_MEMq}, +{"PHADDSW_MMXq_MMXq", XED_IFORM_PHADDSW_MMXq_MMXq}, +{"PHADDSW_XMMdq_MEMdq", XED_IFORM_PHADDSW_XMMdq_MEMdq}, +{"PHADDSW_XMMdq_XMMdq", XED_IFORM_PHADDSW_XMMdq_XMMdq}, +{"PHADDW_MMXq_MEMq", XED_IFORM_PHADDW_MMXq_MEMq}, +{"PHADDW_MMXq_MMXq", XED_IFORM_PHADDW_MMXq_MMXq}, +{"PHADDW_XMMdq_MEMdq", XED_IFORM_PHADDW_XMMdq_MEMdq}, +{"PHADDW_XMMdq_XMMdq", XED_IFORM_PHADDW_XMMdq_XMMdq}, +{"PHMINPOSUW_XMMdq_MEMdq", XED_IFORM_PHMINPOSUW_XMMdq_MEMdq}, +{"PHMINPOSUW_XMMdq_XMMdq", XED_IFORM_PHMINPOSUW_XMMdq_XMMdq}, +{"PHSUBD_MMXq_MEMq", XED_IFORM_PHSUBD_MMXq_MEMq}, +{"PHSUBD_MMXq_MMXq", XED_IFORM_PHSUBD_MMXq_MMXq}, +{"PHSUBD_XMMdq_MEMdq", XED_IFORM_PHSUBD_XMMdq_MEMdq}, +{"PHSUBD_XMMdq_XMMdq", XED_IFORM_PHSUBD_XMMdq_XMMdq}, +{"PHSUBSW_MMXq_MEMq", XED_IFORM_PHSUBSW_MMXq_MEMq}, +{"PHSUBSW_MMXq_MMXq", XED_IFORM_PHSUBSW_MMXq_MMXq}, +{"PHSUBSW_XMMdq_MEMdq", XED_IFORM_PHSUBSW_XMMdq_MEMdq}, +{"PHSUBSW_XMMdq_XMMdq", XED_IFORM_PHSUBSW_XMMdq_XMMdq}, +{"PHSUBW_MMXq_MEMq", XED_IFORM_PHSUBW_MMXq_MEMq}, +{"PHSUBW_MMXq_MMXq", XED_IFORM_PHSUBW_MMXq_MMXq}, +{"PHSUBW_XMMdq_MEMdq", XED_IFORM_PHSUBW_XMMdq_MEMdq}, +{"PHSUBW_XMMdq_XMMdq", XED_IFORM_PHSUBW_XMMdq_XMMdq}, +{"PI2FD_MMXq_MEMq", XED_IFORM_PI2FD_MMXq_MEMq}, +{"PI2FD_MMXq_MMXq", XED_IFORM_PI2FD_MMXq_MMXq}, +{"PI2FW_MMXq_MEMq", XED_IFORM_PI2FW_MMXq_MEMq}, +{"PI2FW_MMXq_MMXq", XED_IFORM_PI2FW_MMXq_MMXq}, +{"PINSRB_XMMdq_GPR32d_IMMb", XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb}, +{"PINSRB_XMMdq_MEMb_IMMb", XED_IFORM_PINSRB_XMMdq_MEMb_IMMb}, +{"PINSRD_XMMdq_GPR32d_IMMb", XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb}, +{"PINSRD_XMMdq_MEMd_IMMb", XED_IFORM_PINSRD_XMMdq_MEMd_IMMb}, +{"PINSRQ_XMMdq_GPR64q_IMMb", XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb}, +{"PINSRQ_XMMdq_MEMq_IMMb", XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb}, +{"PINSRW_MMXq_GPR32_IMMb", XED_IFORM_PINSRW_MMXq_GPR32_IMMb}, +{"PINSRW_MMXq_MEMw_IMMb", XED_IFORM_PINSRW_MMXq_MEMw_IMMb}, +{"PINSRW_XMMdq_GPR32_IMMb", XED_IFORM_PINSRW_XMMdq_GPR32_IMMb}, +{"PINSRW_XMMdq_MEMw_IMMb", XED_IFORM_PINSRW_XMMdq_MEMw_IMMb}, +{"PMADDUBSW_MMXq_MEMq", XED_IFORM_PMADDUBSW_MMXq_MEMq}, +{"PMADDUBSW_MMXq_MMXq", XED_IFORM_PMADDUBSW_MMXq_MMXq}, +{"PMADDUBSW_XMMdq_MEMdq", XED_IFORM_PMADDUBSW_XMMdq_MEMdq}, +{"PMADDUBSW_XMMdq_XMMdq", XED_IFORM_PMADDUBSW_XMMdq_XMMdq}, +{"PMADDWD_MMXq_MEMq", XED_IFORM_PMADDWD_MMXq_MEMq}, +{"PMADDWD_MMXq_MMXq", XED_IFORM_PMADDWD_MMXq_MMXq}, +{"PMADDWD_XMMdq_MEMdq", XED_IFORM_PMADDWD_XMMdq_MEMdq}, +{"PMADDWD_XMMdq_XMMdq", XED_IFORM_PMADDWD_XMMdq_XMMdq}, +{"PMAXSB_XMMdq_MEMdq", XED_IFORM_PMAXSB_XMMdq_MEMdq}, +{"PMAXSB_XMMdq_XMMdq", XED_IFORM_PMAXSB_XMMdq_XMMdq}, +{"PMAXSD_XMMdq_MEMdq", XED_IFORM_PMAXSD_XMMdq_MEMdq}, +{"PMAXSD_XMMdq_XMMdq", XED_IFORM_PMAXSD_XMMdq_XMMdq}, +{"PMAXSW_MMXq_MEMq", XED_IFORM_PMAXSW_MMXq_MEMq}, +{"PMAXSW_MMXq_MMXq", XED_IFORM_PMAXSW_MMXq_MMXq}, +{"PMAXSW_XMMdq_MEMdq", XED_IFORM_PMAXSW_XMMdq_MEMdq}, +{"PMAXSW_XMMdq_XMMdq", XED_IFORM_PMAXSW_XMMdq_XMMdq}, +{"PMAXUB_MMXq_MEMq", XED_IFORM_PMAXUB_MMXq_MEMq}, +{"PMAXUB_MMXq_MMXq", XED_IFORM_PMAXUB_MMXq_MMXq}, +{"PMAXUB_XMMdq_MEMdq", XED_IFORM_PMAXUB_XMMdq_MEMdq}, +{"PMAXUB_XMMdq_XMMdq", XED_IFORM_PMAXUB_XMMdq_XMMdq}, +{"PMAXUD_XMMdq_MEMdq", XED_IFORM_PMAXUD_XMMdq_MEMdq}, +{"PMAXUD_XMMdq_XMMdq", XED_IFORM_PMAXUD_XMMdq_XMMdq}, +{"PMAXUW_XMMdq_MEMdq", XED_IFORM_PMAXUW_XMMdq_MEMdq}, +{"PMAXUW_XMMdq_XMMdq", XED_IFORM_PMAXUW_XMMdq_XMMdq}, +{"PMINSB_XMMdq_MEMdq", XED_IFORM_PMINSB_XMMdq_MEMdq}, +{"PMINSB_XMMdq_XMMdq", XED_IFORM_PMINSB_XMMdq_XMMdq}, +{"PMINSD_XMMdq_MEMdq", XED_IFORM_PMINSD_XMMdq_MEMdq}, +{"PMINSD_XMMdq_XMMdq", XED_IFORM_PMINSD_XMMdq_XMMdq}, +{"PMINSW_MMXq_MEMq", XED_IFORM_PMINSW_MMXq_MEMq}, +{"PMINSW_MMXq_MMXq", XED_IFORM_PMINSW_MMXq_MMXq}, +{"PMINSW_XMMdq_MEMdq", XED_IFORM_PMINSW_XMMdq_MEMdq}, +{"PMINSW_XMMdq_XMMdq", XED_IFORM_PMINSW_XMMdq_XMMdq}, +{"PMINUB_MMXq_MEMq", XED_IFORM_PMINUB_MMXq_MEMq}, +{"PMINUB_MMXq_MMXq", XED_IFORM_PMINUB_MMXq_MMXq}, +{"PMINUB_XMMdq_MEMdq", XED_IFORM_PMINUB_XMMdq_MEMdq}, +{"PMINUB_XMMdq_XMMdq", XED_IFORM_PMINUB_XMMdq_XMMdq}, +{"PMINUD_XMMdq_MEMdq", XED_IFORM_PMINUD_XMMdq_MEMdq}, +{"PMINUD_XMMdq_XMMdq", XED_IFORM_PMINUD_XMMdq_XMMdq}, +{"PMINUW_XMMdq_MEMdq", XED_IFORM_PMINUW_XMMdq_MEMdq}, +{"PMINUW_XMMdq_XMMdq", XED_IFORM_PMINUW_XMMdq_XMMdq}, +{"PMOVMSKB_GPR32_MMXq", XED_IFORM_PMOVMSKB_GPR32_MMXq}, +{"PMOVMSKB_GPR32_XMMdq", XED_IFORM_PMOVMSKB_GPR32_XMMdq}, +{"PMOVSXBD_XMMdq_MEMd", XED_IFORM_PMOVSXBD_XMMdq_MEMd}, +{"PMOVSXBD_XMMdq_XMMd", XED_IFORM_PMOVSXBD_XMMdq_XMMd}, +{"PMOVSXBQ_XMMdq_MEMw", XED_IFORM_PMOVSXBQ_XMMdq_MEMw}, +{"PMOVSXBQ_XMMdq_XMMw", XED_IFORM_PMOVSXBQ_XMMdq_XMMw}, +{"PMOVSXBW_XMMdq_MEMq", XED_IFORM_PMOVSXBW_XMMdq_MEMq}, +{"PMOVSXBW_XMMdq_XMMq", XED_IFORM_PMOVSXBW_XMMdq_XMMq}, +{"PMOVSXDQ_XMMdq_MEMq", XED_IFORM_PMOVSXDQ_XMMdq_MEMq}, +{"PMOVSXDQ_XMMdq_XMMq", XED_IFORM_PMOVSXDQ_XMMdq_XMMq}, +{"PMOVSXWD_XMMdq_MEMq", XED_IFORM_PMOVSXWD_XMMdq_MEMq}, +{"PMOVSXWD_XMMdq_XMMq", XED_IFORM_PMOVSXWD_XMMdq_XMMq}, +{"PMOVSXWQ_XMMdq_MEMd", XED_IFORM_PMOVSXWQ_XMMdq_MEMd}, +{"PMOVSXWQ_XMMdq_XMMd", XED_IFORM_PMOVSXWQ_XMMdq_XMMd}, +{"PMOVZXBD_XMMdq_MEMd", XED_IFORM_PMOVZXBD_XMMdq_MEMd}, +{"PMOVZXBD_XMMdq_XMMd", XED_IFORM_PMOVZXBD_XMMdq_XMMd}, +{"PMOVZXBQ_XMMdq_MEMw", XED_IFORM_PMOVZXBQ_XMMdq_MEMw}, +{"PMOVZXBQ_XMMdq_XMMw", XED_IFORM_PMOVZXBQ_XMMdq_XMMw}, +{"PMOVZXBW_XMMdq_MEMq", XED_IFORM_PMOVZXBW_XMMdq_MEMq}, +{"PMOVZXBW_XMMdq_XMMq", XED_IFORM_PMOVZXBW_XMMdq_XMMq}, +{"PMOVZXDQ_XMMdq_MEMq", XED_IFORM_PMOVZXDQ_XMMdq_MEMq}, +{"PMOVZXDQ_XMMdq_XMMq", XED_IFORM_PMOVZXDQ_XMMdq_XMMq}, +{"PMOVZXWD_XMMdq_MEMq", XED_IFORM_PMOVZXWD_XMMdq_MEMq}, +{"PMOVZXWD_XMMdq_XMMq", XED_IFORM_PMOVZXWD_XMMdq_XMMq}, +{"PMOVZXWQ_XMMdq_MEMd", XED_IFORM_PMOVZXWQ_XMMdq_MEMd}, +{"PMOVZXWQ_XMMdq_XMMd", XED_IFORM_PMOVZXWQ_XMMdq_XMMd}, +{"PMULDQ_XMMdq_MEMdq", XED_IFORM_PMULDQ_XMMdq_MEMdq}, +{"PMULDQ_XMMdq_XMMdq", XED_IFORM_PMULDQ_XMMdq_XMMdq}, +{"PMULHRSW_MMXq_MEMq", XED_IFORM_PMULHRSW_MMXq_MEMq}, +{"PMULHRSW_MMXq_MMXq", XED_IFORM_PMULHRSW_MMXq_MMXq}, +{"PMULHRSW_XMMdq_MEMdq", XED_IFORM_PMULHRSW_XMMdq_MEMdq}, +{"PMULHRSW_XMMdq_XMMdq", XED_IFORM_PMULHRSW_XMMdq_XMMdq}, +{"PMULHRW_MMXq_MEMq", XED_IFORM_PMULHRW_MMXq_MEMq}, +{"PMULHRW_MMXq_MMXq", XED_IFORM_PMULHRW_MMXq_MMXq}, +{"PMULHUW_MMXq_MEMq", XED_IFORM_PMULHUW_MMXq_MEMq}, +{"PMULHUW_MMXq_MMXq", XED_IFORM_PMULHUW_MMXq_MMXq}, +{"PMULHUW_XMMdq_MEMdq", XED_IFORM_PMULHUW_XMMdq_MEMdq}, +{"PMULHUW_XMMdq_XMMdq", XED_IFORM_PMULHUW_XMMdq_XMMdq}, +{"PMULHW_MMXq_MEMq", XED_IFORM_PMULHW_MMXq_MEMq}, +{"PMULHW_MMXq_MMXq", XED_IFORM_PMULHW_MMXq_MMXq}, +{"PMULHW_XMMdq_MEMdq", XED_IFORM_PMULHW_XMMdq_MEMdq}, +{"PMULHW_XMMdq_XMMdq", XED_IFORM_PMULHW_XMMdq_XMMdq}, +{"PMULLD_XMMdq_MEMdq", XED_IFORM_PMULLD_XMMdq_MEMdq}, +{"PMULLD_XMMdq_XMMdq", XED_IFORM_PMULLD_XMMdq_XMMdq}, +{"PMULLW_MMXq_MEMq", XED_IFORM_PMULLW_MMXq_MEMq}, +{"PMULLW_MMXq_MMXq", XED_IFORM_PMULLW_MMXq_MMXq}, +{"PMULLW_XMMdq_MEMdq", XED_IFORM_PMULLW_XMMdq_MEMdq}, +{"PMULLW_XMMdq_XMMdq", XED_IFORM_PMULLW_XMMdq_XMMdq}, +{"PMULUDQ_MMXq_MEMq", XED_IFORM_PMULUDQ_MMXq_MEMq}, +{"PMULUDQ_MMXq_MMXq", XED_IFORM_PMULUDQ_MMXq_MMXq}, +{"PMULUDQ_XMMdq_MEMdq", XED_IFORM_PMULUDQ_XMMdq_MEMdq}, +{"PMULUDQ_XMMdq_XMMdq", XED_IFORM_PMULUDQ_XMMdq_XMMdq}, +{"POP_DS", XED_IFORM_POP_DS}, +{"POP_ES", XED_IFORM_POP_ES}, +{"POP_FS", XED_IFORM_POP_FS}, +{"POP_GPRv_58", XED_IFORM_POP_GPRv_58}, +{"POP_GPRv_8F", XED_IFORM_POP_GPRv_8F}, +{"POP_GS", XED_IFORM_POP_GS}, +{"POP_MEMv", XED_IFORM_POP_MEMv}, +{"POP_SS", XED_IFORM_POP_SS}, +{"POPA", XED_IFORM_POPA}, +{"POPAD", XED_IFORM_POPAD}, +{"POPCNT_GPRv_GPRv", XED_IFORM_POPCNT_GPRv_GPRv}, +{"POPCNT_GPRv_MEMv", XED_IFORM_POPCNT_GPRv_MEMv}, +{"POPF", XED_IFORM_POPF}, +{"POPFD", XED_IFORM_POPFD}, +{"POPFQ", XED_IFORM_POPFQ}, +{"POR_MMXq_MEMq", XED_IFORM_POR_MMXq_MEMq}, +{"POR_MMXq_MMXq", XED_IFORM_POR_MMXq_MMXq}, +{"POR_XMMdq_MEMdq", XED_IFORM_POR_XMMdq_MEMdq}, +{"POR_XMMdq_XMMdq", XED_IFORM_POR_XMMdq_XMMdq}, +{"PREFETCHNTA_MEMmprefetch", XED_IFORM_PREFETCHNTA_MEMmprefetch}, +{"PREFETCHT0_MEMmprefetch", XED_IFORM_PREFETCHT0_MEMmprefetch}, +{"PREFETCHT1_MEMmprefetch", XED_IFORM_PREFETCHT1_MEMmprefetch}, +{"PREFETCHT2_MEMmprefetch", XED_IFORM_PREFETCHT2_MEMmprefetch}, +{"PREFETCHW_0F0Dr1", XED_IFORM_PREFETCHW_0F0Dr1}, +{"PREFETCHW_0F0Dr3", XED_IFORM_PREFETCHW_0F0Dr3}, +{"PREFETCHWT1_MEMu8", XED_IFORM_PREFETCHWT1_MEMu8}, +{"PREFETCH_EXCLUSIVE_MEMmprefetch", XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch}, +{"PREFETCH_RESERVED_0F0Dr4", XED_IFORM_PREFETCH_RESERVED_0F0Dr4}, +{"PREFETCH_RESERVED_0F0Dr5", XED_IFORM_PREFETCH_RESERVED_0F0Dr5}, +{"PREFETCH_RESERVED_0F0Dr6", XED_IFORM_PREFETCH_RESERVED_0F0Dr6}, +{"PREFETCH_RESERVED_0F0Dr7", XED_IFORM_PREFETCH_RESERVED_0F0Dr7}, +{"PSADBW_MMXq_MEMq", XED_IFORM_PSADBW_MMXq_MEMq}, +{"PSADBW_MMXq_MMXq", XED_IFORM_PSADBW_MMXq_MMXq}, +{"PSADBW_XMMdq_MEMdq", XED_IFORM_PSADBW_XMMdq_MEMdq}, +{"PSADBW_XMMdq_XMMdq", XED_IFORM_PSADBW_XMMdq_XMMdq}, +{"PSHUFB_MMXq_MEMq", XED_IFORM_PSHUFB_MMXq_MEMq}, +{"PSHUFB_MMXq_MMXq", XED_IFORM_PSHUFB_MMXq_MMXq}, +{"PSHUFB_XMMdq_MEMdq", XED_IFORM_PSHUFB_XMMdq_MEMdq}, +{"PSHUFB_XMMdq_XMMdq", XED_IFORM_PSHUFB_XMMdq_XMMdq}, +{"PSHUFD_XMMdq_MEMdq_IMMb", XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb}, +{"PSHUFD_XMMdq_XMMdq_IMMb", XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb}, +{"PSHUFHW_XMMdq_MEMdq_IMMb", XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb}, +{"PSHUFHW_XMMdq_XMMdq_IMMb", XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb}, +{"PSHUFLW_XMMdq_MEMdq_IMMb", XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb}, +{"PSHUFLW_XMMdq_XMMdq_IMMb", XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb}, +{"PSHUFW_MMXq_MEMq_IMMb", XED_IFORM_PSHUFW_MMXq_MEMq_IMMb}, +{"PSHUFW_MMXq_MMXq_IMMb", XED_IFORM_PSHUFW_MMXq_MMXq_IMMb}, +{"PSIGNB_MMXq_MEMq", XED_IFORM_PSIGNB_MMXq_MEMq}, +{"PSIGNB_MMXq_MMXq", XED_IFORM_PSIGNB_MMXq_MMXq}, +{"PSIGNB_XMMdq_MEMdq", XED_IFORM_PSIGNB_XMMdq_MEMdq}, +{"PSIGNB_XMMdq_XMMdq", XED_IFORM_PSIGNB_XMMdq_XMMdq}, +{"PSIGND_MMXq_MEMq", XED_IFORM_PSIGND_MMXq_MEMq}, +{"PSIGND_MMXq_MMXq", XED_IFORM_PSIGND_MMXq_MMXq}, +{"PSIGND_XMMdq_MEMdq", XED_IFORM_PSIGND_XMMdq_MEMdq}, +{"PSIGND_XMMdq_XMMdq", XED_IFORM_PSIGND_XMMdq_XMMdq}, +{"PSIGNW_MMXq_MEMq", XED_IFORM_PSIGNW_MMXq_MEMq}, +{"PSIGNW_MMXq_MMXq", XED_IFORM_PSIGNW_MMXq_MMXq}, +{"PSIGNW_XMMdq_MEMdq", XED_IFORM_PSIGNW_XMMdq_MEMdq}, +{"PSIGNW_XMMdq_XMMdq", XED_IFORM_PSIGNW_XMMdq_XMMdq}, +{"PSLLD_MMXq_IMMb", XED_IFORM_PSLLD_MMXq_IMMb}, +{"PSLLD_MMXq_MEMq", XED_IFORM_PSLLD_MMXq_MEMq}, +{"PSLLD_MMXq_MMXq", XED_IFORM_PSLLD_MMXq_MMXq}, +{"PSLLD_XMMdq_IMMb", XED_IFORM_PSLLD_XMMdq_IMMb}, +{"PSLLD_XMMdq_MEMdq", XED_IFORM_PSLLD_XMMdq_MEMdq}, +{"PSLLD_XMMdq_XMMdq", XED_IFORM_PSLLD_XMMdq_XMMdq}, +{"PSLLDQ_XMMdq_IMMb", XED_IFORM_PSLLDQ_XMMdq_IMMb}, +{"PSLLQ_MMXq_IMMb", XED_IFORM_PSLLQ_MMXq_IMMb}, +{"PSLLQ_MMXq_MEMq", XED_IFORM_PSLLQ_MMXq_MEMq}, +{"PSLLQ_MMXq_MMXq", XED_IFORM_PSLLQ_MMXq_MMXq}, +{"PSLLQ_XMMdq_IMMb", XED_IFORM_PSLLQ_XMMdq_IMMb}, +{"PSLLQ_XMMdq_MEMdq", XED_IFORM_PSLLQ_XMMdq_MEMdq}, +{"PSLLQ_XMMdq_XMMdq", XED_IFORM_PSLLQ_XMMdq_XMMdq}, +{"PSLLW_MMXq_IMMb", XED_IFORM_PSLLW_MMXq_IMMb}, +{"PSLLW_MMXq_MEMq", XED_IFORM_PSLLW_MMXq_MEMq}, +{"PSLLW_MMXq_MMXq", XED_IFORM_PSLLW_MMXq_MMXq}, +{"PSLLW_XMMdq_IMMb", XED_IFORM_PSLLW_XMMdq_IMMb}, +{"PSLLW_XMMdq_MEMdq", XED_IFORM_PSLLW_XMMdq_MEMdq}, +{"PSLLW_XMMdq_XMMdq", XED_IFORM_PSLLW_XMMdq_XMMdq}, +{"PSMASH_RAX", XED_IFORM_PSMASH_RAX}, +{"PSRAD_MMXq_IMMb", XED_IFORM_PSRAD_MMXq_IMMb}, +{"PSRAD_MMXq_MEMq", XED_IFORM_PSRAD_MMXq_MEMq}, +{"PSRAD_MMXq_MMXq", XED_IFORM_PSRAD_MMXq_MMXq}, +{"PSRAD_XMMdq_IMMb", XED_IFORM_PSRAD_XMMdq_IMMb}, +{"PSRAD_XMMdq_MEMdq", XED_IFORM_PSRAD_XMMdq_MEMdq}, +{"PSRAD_XMMdq_XMMdq", XED_IFORM_PSRAD_XMMdq_XMMdq}, +{"PSRAW_MMXq_IMMb", XED_IFORM_PSRAW_MMXq_IMMb}, +{"PSRAW_MMXq_MEMq", XED_IFORM_PSRAW_MMXq_MEMq}, +{"PSRAW_MMXq_MMXq", XED_IFORM_PSRAW_MMXq_MMXq}, +{"PSRAW_XMMdq_IMMb", XED_IFORM_PSRAW_XMMdq_IMMb}, +{"PSRAW_XMMdq_MEMdq", XED_IFORM_PSRAW_XMMdq_MEMdq}, +{"PSRAW_XMMdq_XMMdq", XED_IFORM_PSRAW_XMMdq_XMMdq}, +{"PSRLD_MMXq_IMMb", XED_IFORM_PSRLD_MMXq_IMMb}, +{"PSRLD_MMXq_MEMq", XED_IFORM_PSRLD_MMXq_MEMq}, +{"PSRLD_MMXq_MMXq", XED_IFORM_PSRLD_MMXq_MMXq}, +{"PSRLD_XMMdq_IMMb", XED_IFORM_PSRLD_XMMdq_IMMb}, +{"PSRLD_XMMdq_MEMdq", XED_IFORM_PSRLD_XMMdq_MEMdq}, +{"PSRLD_XMMdq_XMMdq", XED_IFORM_PSRLD_XMMdq_XMMdq}, +{"PSRLDQ_XMMdq_IMMb", XED_IFORM_PSRLDQ_XMMdq_IMMb}, +{"PSRLQ_MMXq_IMMb", XED_IFORM_PSRLQ_MMXq_IMMb}, +{"PSRLQ_MMXq_MEMq", XED_IFORM_PSRLQ_MMXq_MEMq}, +{"PSRLQ_MMXq_MMXq", XED_IFORM_PSRLQ_MMXq_MMXq}, +{"PSRLQ_XMMdq_IMMb", XED_IFORM_PSRLQ_XMMdq_IMMb}, +{"PSRLQ_XMMdq_MEMdq", XED_IFORM_PSRLQ_XMMdq_MEMdq}, +{"PSRLQ_XMMdq_XMMdq", XED_IFORM_PSRLQ_XMMdq_XMMdq}, +{"PSRLW_MMXq_IMMb", XED_IFORM_PSRLW_MMXq_IMMb}, +{"PSRLW_MMXq_MEMq", XED_IFORM_PSRLW_MMXq_MEMq}, +{"PSRLW_MMXq_MMXq", XED_IFORM_PSRLW_MMXq_MMXq}, +{"PSRLW_XMMdq_IMMb", XED_IFORM_PSRLW_XMMdq_IMMb}, +{"PSRLW_XMMdq_MEMdq", XED_IFORM_PSRLW_XMMdq_MEMdq}, +{"PSRLW_XMMdq_XMMdq", XED_IFORM_PSRLW_XMMdq_XMMdq}, +{"PSUBB_MMXq_MEMq", XED_IFORM_PSUBB_MMXq_MEMq}, +{"PSUBB_MMXq_MMXq", XED_IFORM_PSUBB_MMXq_MMXq}, +{"PSUBB_XMMdq_MEMdq", XED_IFORM_PSUBB_XMMdq_MEMdq}, +{"PSUBB_XMMdq_XMMdq", XED_IFORM_PSUBB_XMMdq_XMMdq}, +{"PSUBD_MMXq_MEMq", XED_IFORM_PSUBD_MMXq_MEMq}, +{"PSUBD_MMXq_MMXq", XED_IFORM_PSUBD_MMXq_MMXq}, +{"PSUBD_XMMdq_MEMdq", XED_IFORM_PSUBD_XMMdq_MEMdq}, +{"PSUBD_XMMdq_XMMdq", XED_IFORM_PSUBD_XMMdq_XMMdq}, +{"PSUBQ_MMXq_MEMq", XED_IFORM_PSUBQ_MMXq_MEMq}, +{"PSUBQ_MMXq_MMXq", XED_IFORM_PSUBQ_MMXq_MMXq}, +{"PSUBQ_XMMdq_MEMdq", XED_IFORM_PSUBQ_XMMdq_MEMdq}, +{"PSUBQ_XMMdq_XMMdq", XED_IFORM_PSUBQ_XMMdq_XMMdq}, +{"PSUBSB_MMXq_MEMq", XED_IFORM_PSUBSB_MMXq_MEMq}, +{"PSUBSB_MMXq_MMXq", XED_IFORM_PSUBSB_MMXq_MMXq}, +{"PSUBSB_XMMdq_MEMdq", XED_IFORM_PSUBSB_XMMdq_MEMdq}, +{"PSUBSB_XMMdq_XMMdq", XED_IFORM_PSUBSB_XMMdq_XMMdq}, +{"PSUBSW_MMXq_MEMq", XED_IFORM_PSUBSW_MMXq_MEMq}, +{"PSUBSW_MMXq_MMXq", XED_IFORM_PSUBSW_MMXq_MMXq}, +{"PSUBSW_XMMdq_MEMdq", XED_IFORM_PSUBSW_XMMdq_MEMdq}, +{"PSUBSW_XMMdq_XMMdq", XED_IFORM_PSUBSW_XMMdq_XMMdq}, +{"PSUBUSB_MMXq_MEMq", XED_IFORM_PSUBUSB_MMXq_MEMq}, +{"PSUBUSB_MMXq_MMXq", XED_IFORM_PSUBUSB_MMXq_MMXq}, +{"PSUBUSB_XMMdq_MEMdq", XED_IFORM_PSUBUSB_XMMdq_MEMdq}, +{"PSUBUSB_XMMdq_XMMdq", XED_IFORM_PSUBUSB_XMMdq_XMMdq}, +{"PSUBUSW_MMXq_MEMq", XED_IFORM_PSUBUSW_MMXq_MEMq}, +{"PSUBUSW_MMXq_MMXq", XED_IFORM_PSUBUSW_MMXq_MMXq}, +{"PSUBUSW_XMMdq_MEMdq", XED_IFORM_PSUBUSW_XMMdq_MEMdq}, +{"PSUBUSW_XMMdq_XMMdq", XED_IFORM_PSUBUSW_XMMdq_XMMdq}, +{"PSUBW_MMXq_MEMq", XED_IFORM_PSUBW_MMXq_MEMq}, +{"PSUBW_MMXq_MMXq", XED_IFORM_PSUBW_MMXq_MMXq}, +{"PSUBW_XMMdq_MEMdq", XED_IFORM_PSUBW_XMMdq_MEMdq}, +{"PSUBW_XMMdq_XMMdq", XED_IFORM_PSUBW_XMMdq_XMMdq}, +{"PSWAPD_MMXq_MEMq", XED_IFORM_PSWAPD_MMXq_MEMq}, +{"PSWAPD_MMXq_MMXq", XED_IFORM_PSWAPD_MMXq_MMXq}, +{"PTEST_XMMdq_MEMdq", XED_IFORM_PTEST_XMMdq_MEMdq}, +{"PTEST_XMMdq_XMMdq", XED_IFORM_PTEST_XMMdq_XMMdq}, +{"PTWRITE_GPRy", XED_IFORM_PTWRITE_GPRy}, +{"PTWRITE_MEMy", XED_IFORM_PTWRITE_MEMy}, +{"PUNPCKHBW_MMXq_MEMq", XED_IFORM_PUNPCKHBW_MMXq_MEMq}, +{"PUNPCKHBW_MMXq_MMXd", XED_IFORM_PUNPCKHBW_MMXq_MMXd}, +{"PUNPCKHBW_XMMdq_MEMdq", XED_IFORM_PUNPCKHBW_XMMdq_MEMdq}, +{"PUNPCKHBW_XMMdq_XMMq", XED_IFORM_PUNPCKHBW_XMMdq_XMMq}, +{"PUNPCKHDQ_MMXq_MEMq", XED_IFORM_PUNPCKHDQ_MMXq_MEMq}, +{"PUNPCKHDQ_MMXq_MMXd", XED_IFORM_PUNPCKHDQ_MMXq_MMXd}, +{"PUNPCKHDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq}, +{"PUNPCKHDQ_XMMdq_XMMq", XED_IFORM_PUNPCKHDQ_XMMdq_XMMq}, +{"PUNPCKHQDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq}, +{"PUNPCKHQDQ_XMMdq_XMMq", XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq}, +{"PUNPCKHWD_MMXq_MEMq", XED_IFORM_PUNPCKHWD_MMXq_MEMq}, +{"PUNPCKHWD_MMXq_MMXd", XED_IFORM_PUNPCKHWD_MMXq_MMXd}, +{"PUNPCKHWD_XMMdq_MEMdq", XED_IFORM_PUNPCKHWD_XMMdq_MEMdq}, +{"PUNPCKHWD_XMMdq_XMMq", XED_IFORM_PUNPCKHWD_XMMdq_XMMq}, +{"PUNPCKLBW_MMXq_MEMd", XED_IFORM_PUNPCKLBW_MMXq_MEMd}, +{"PUNPCKLBW_MMXq_MMXd", XED_IFORM_PUNPCKLBW_MMXq_MMXd}, +{"PUNPCKLBW_XMMdq_MEMdq", XED_IFORM_PUNPCKLBW_XMMdq_MEMdq}, +{"PUNPCKLBW_XMMdq_XMMq", XED_IFORM_PUNPCKLBW_XMMdq_XMMq}, +{"PUNPCKLDQ_MMXq_MEMd", XED_IFORM_PUNPCKLDQ_MMXq_MEMd}, +{"PUNPCKLDQ_MMXq_MMXd", XED_IFORM_PUNPCKLDQ_MMXq_MMXd}, +{"PUNPCKLDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq}, +{"PUNPCKLDQ_XMMdq_XMMq", XED_IFORM_PUNPCKLDQ_XMMdq_XMMq}, +{"PUNPCKLQDQ_XMMdq_MEMdq", XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq}, +{"PUNPCKLQDQ_XMMdq_XMMq", XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq}, +{"PUNPCKLWD_MMXq_MEMd", XED_IFORM_PUNPCKLWD_MMXq_MEMd}, +{"PUNPCKLWD_MMXq_MMXd", XED_IFORM_PUNPCKLWD_MMXq_MMXd}, +{"PUNPCKLWD_XMMdq_MEMdq", XED_IFORM_PUNPCKLWD_XMMdq_MEMdq}, +{"PUNPCKLWD_XMMdq_XMMq", XED_IFORM_PUNPCKLWD_XMMdq_XMMq}, +{"PUSH_CS", XED_IFORM_PUSH_CS}, +{"PUSH_DS", XED_IFORM_PUSH_DS}, +{"PUSH_ES", XED_IFORM_PUSH_ES}, +{"PUSH_FS", XED_IFORM_PUSH_FS}, +{"PUSH_GPRv_50", XED_IFORM_PUSH_GPRv_50}, +{"PUSH_GPRv_FFr6", XED_IFORM_PUSH_GPRv_FFr6}, +{"PUSH_GS", XED_IFORM_PUSH_GS}, +{"PUSH_IMMb", XED_IFORM_PUSH_IMMb}, +{"PUSH_IMMz", XED_IFORM_PUSH_IMMz}, +{"PUSH_MEMv", XED_IFORM_PUSH_MEMv}, +{"PUSH_SS", XED_IFORM_PUSH_SS}, +{"PUSHA", XED_IFORM_PUSHA}, +{"PUSHAD", XED_IFORM_PUSHAD}, +{"PUSHF", XED_IFORM_PUSHF}, +{"PUSHFD", XED_IFORM_PUSHFD}, +{"PUSHFQ", XED_IFORM_PUSHFQ}, +{"PVALIDATE_RAX_ECX_EDX", XED_IFORM_PVALIDATE_RAX_ECX_EDX}, +{"PXOR_MMXq_MEMq", XED_IFORM_PXOR_MMXq_MEMq}, +{"PXOR_MMXq_MMXq", XED_IFORM_PXOR_MMXq_MMXq}, +{"PXOR_XMMdq_MEMdq", XED_IFORM_PXOR_XMMdq_MEMdq}, +{"PXOR_XMMdq_XMMdq", XED_IFORM_PXOR_XMMdq_XMMdq}, +{"RCL_GPR8_CL", XED_IFORM_RCL_GPR8_CL}, +{"RCL_GPR8_IMMb", XED_IFORM_RCL_GPR8_IMMb}, +{"RCL_GPR8_ONE", XED_IFORM_RCL_GPR8_ONE}, +{"RCL_GPRv_CL", XED_IFORM_RCL_GPRv_CL}, +{"RCL_GPRv_IMMb", XED_IFORM_RCL_GPRv_IMMb}, +{"RCL_GPRv_ONE", XED_IFORM_RCL_GPRv_ONE}, +{"RCL_MEMb_CL", XED_IFORM_RCL_MEMb_CL}, +{"RCL_MEMb_IMMb", XED_IFORM_RCL_MEMb_IMMb}, +{"RCL_MEMb_ONE", XED_IFORM_RCL_MEMb_ONE}, +{"RCL_MEMv_CL", XED_IFORM_RCL_MEMv_CL}, +{"RCL_MEMv_IMMb", XED_IFORM_RCL_MEMv_IMMb}, +{"RCL_MEMv_ONE", XED_IFORM_RCL_MEMv_ONE}, +{"RCPPS_XMMps_MEMps", XED_IFORM_RCPPS_XMMps_MEMps}, +{"RCPPS_XMMps_XMMps", XED_IFORM_RCPPS_XMMps_XMMps}, +{"RCPSS_XMMss_MEMss", XED_IFORM_RCPSS_XMMss_MEMss}, +{"RCPSS_XMMss_XMMss", XED_IFORM_RCPSS_XMMss_XMMss}, +{"RCR_GPR8_CL", XED_IFORM_RCR_GPR8_CL}, +{"RCR_GPR8_IMMb", XED_IFORM_RCR_GPR8_IMMb}, +{"RCR_GPR8_ONE", XED_IFORM_RCR_GPR8_ONE}, +{"RCR_GPRv_CL", XED_IFORM_RCR_GPRv_CL}, +{"RCR_GPRv_IMMb", XED_IFORM_RCR_GPRv_IMMb}, +{"RCR_GPRv_ONE", XED_IFORM_RCR_GPRv_ONE}, +{"RCR_MEMb_CL", XED_IFORM_RCR_MEMb_CL}, +{"RCR_MEMb_IMMb", XED_IFORM_RCR_MEMb_IMMb}, +{"RCR_MEMb_ONE", XED_IFORM_RCR_MEMb_ONE}, +{"RCR_MEMv_CL", XED_IFORM_RCR_MEMv_CL}, +{"RCR_MEMv_IMMb", XED_IFORM_RCR_MEMv_IMMb}, +{"RCR_MEMv_ONE", XED_IFORM_RCR_MEMv_ONE}, +{"RDFSBASE_GPRy", XED_IFORM_RDFSBASE_GPRy}, +{"RDGSBASE_GPRy", XED_IFORM_RDGSBASE_GPRy}, +{"RDMSR", XED_IFORM_RDMSR}, +{"RDPID_GPR32u32", XED_IFORM_RDPID_GPR32u32}, +{"RDPID_GPR64u64", XED_IFORM_RDPID_GPR64u64}, +{"RDPKRU", XED_IFORM_RDPKRU}, +{"RDPMC", XED_IFORM_RDPMC}, +{"RDPRU", XED_IFORM_RDPRU}, +{"RDRAND_GPRv", XED_IFORM_RDRAND_GPRv}, +{"RDSEED_GPRv", XED_IFORM_RDSEED_GPRv}, +{"RDSSPD_GPR32u32", XED_IFORM_RDSSPD_GPR32u32}, +{"RDSSPQ_GPR64u64", XED_IFORM_RDSSPQ_GPR64u64}, +{"RDTSC", XED_IFORM_RDTSC}, +{"RDTSCP", XED_IFORM_RDTSCP}, +{"REPE_CMPSB", XED_IFORM_REPE_CMPSB}, +{"REPE_CMPSD", XED_IFORM_REPE_CMPSD}, +{"REPE_CMPSQ", XED_IFORM_REPE_CMPSQ}, +{"REPE_CMPSW", XED_IFORM_REPE_CMPSW}, +{"REPE_SCASB", XED_IFORM_REPE_SCASB}, +{"REPE_SCASD", XED_IFORM_REPE_SCASD}, +{"REPE_SCASQ", XED_IFORM_REPE_SCASQ}, +{"REPE_SCASW", XED_IFORM_REPE_SCASW}, +{"REPNE_CMPSB", XED_IFORM_REPNE_CMPSB}, +{"REPNE_CMPSD", XED_IFORM_REPNE_CMPSD}, +{"REPNE_CMPSQ", XED_IFORM_REPNE_CMPSQ}, +{"REPNE_CMPSW", XED_IFORM_REPNE_CMPSW}, +{"REPNE_SCASB", XED_IFORM_REPNE_SCASB}, +{"REPNE_SCASD", XED_IFORM_REPNE_SCASD}, +{"REPNE_SCASQ", XED_IFORM_REPNE_SCASQ}, +{"REPNE_SCASW", XED_IFORM_REPNE_SCASW}, +{"REP_INSB", XED_IFORM_REP_INSB}, +{"REP_INSD", XED_IFORM_REP_INSD}, +{"REP_INSW", XED_IFORM_REP_INSW}, +{"REP_LODSB", XED_IFORM_REP_LODSB}, +{"REP_LODSD", XED_IFORM_REP_LODSD}, +{"REP_LODSQ", XED_IFORM_REP_LODSQ}, +{"REP_LODSW", XED_IFORM_REP_LODSW}, +{"REP_MONTMUL", XED_IFORM_REP_MONTMUL}, +{"REP_MOVSB", XED_IFORM_REP_MOVSB}, +{"REP_MOVSD", XED_IFORM_REP_MOVSD}, +{"REP_MOVSQ", XED_IFORM_REP_MOVSQ}, +{"REP_MOVSW", XED_IFORM_REP_MOVSW}, +{"REP_OUTSB", XED_IFORM_REP_OUTSB}, +{"REP_OUTSD", XED_IFORM_REP_OUTSD}, +{"REP_OUTSW", XED_IFORM_REP_OUTSW}, +{"REP_STOSB", XED_IFORM_REP_STOSB}, +{"REP_STOSD", XED_IFORM_REP_STOSD}, +{"REP_STOSQ", XED_IFORM_REP_STOSQ}, +{"REP_STOSW", XED_IFORM_REP_STOSW}, +{"REP_XCRYPTCBC", XED_IFORM_REP_XCRYPTCBC}, +{"REP_XCRYPTCFB", XED_IFORM_REP_XCRYPTCFB}, +{"REP_XCRYPTCTR", XED_IFORM_REP_XCRYPTCTR}, +{"REP_XCRYPTECB", XED_IFORM_REP_XCRYPTECB}, +{"REP_XCRYPTOFB", XED_IFORM_REP_XCRYPTOFB}, +{"REP_XSHA1", XED_IFORM_REP_XSHA1}, +{"REP_XSHA256", XED_IFORM_REP_XSHA256}, +{"REP_XSTORE", XED_IFORM_REP_XSTORE}, +{"RET_FAR", XED_IFORM_RET_FAR}, +{"RET_FAR_IMMw", XED_IFORM_RET_FAR_IMMw}, +{"RET_NEAR", XED_IFORM_RET_NEAR}, +{"RET_NEAR_IMMw", XED_IFORM_RET_NEAR_IMMw}, +{"RMPADJUST_RAX_RCX_RDX", XED_IFORM_RMPADJUST_RAX_RCX_RDX}, +{"RMPUPDATE_RAX_RCX", XED_IFORM_RMPUPDATE_RAX_RCX}, +{"ROL_GPR8_CL", XED_IFORM_ROL_GPR8_CL}, +{"ROL_GPR8_IMMb", XED_IFORM_ROL_GPR8_IMMb}, +{"ROL_GPR8_ONE", XED_IFORM_ROL_GPR8_ONE}, +{"ROL_GPRv_CL", XED_IFORM_ROL_GPRv_CL}, +{"ROL_GPRv_IMMb", XED_IFORM_ROL_GPRv_IMMb}, +{"ROL_GPRv_ONE", XED_IFORM_ROL_GPRv_ONE}, +{"ROL_MEMb_CL", XED_IFORM_ROL_MEMb_CL}, +{"ROL_MEMb_IMMb", XED_IFORM_ROL_MEMb_IMMb}, +{"ROL_MEMb_ONE", XED_IFORM_ROL_MEMb_ONE}, +{"ROL_MEMv_CL", XED_IFORM_ROL_MEMv_CL}, +{"ROL_MEMv_IMMb", XED_IFORM_ROL_MEMv_IMMb}, +{"ROL_MEMv_ONE", XED_IFORM_ROL_MEMv_ONE}, +{"ROR_GPR8_CL", XED_IFORM_ROR_GPR8_CL}, +{"ROR_GPR8_IMMb", XED_IFORM_ROR_GPR8_IMMb}, +{"ROR_GPR8_ONE", XED_IFORM_ROR_GPR8_ONE}, +{"ROR_GPRv_CL", XED_IFORM_ROR_GPRv_CL}, +{"ROR_GPRv_IMMb", XED_IFORM_ROR_GPRv_IMMb}, +{"ROR_GPRv_ONE", XED_IFORM_ROR_GPRv_ONE}, +{"ROR_MEMb_CL", XED_IFORM_ROR_MEMb_CL}, +{"ROR_MEMb_IMMb", XED_IFORM_ROR_MEMb_IMMb}, +{"ROR_MEMb_ONE", XED_IFORM_ROR_MEMb_ONE}, +{"ROR_MEMv_CL", XED_IFORM_ROR_MEMv_CL}, +{"ROR_MEMv_IMMb", XED_IFORM_ROR_MEMv_IMMb}, +{"ROR_MEMv_ONE", XED_IFORM_ROR_MEMv_ONE}, +{"RORX_VGPR32d_MEMd_IMMb", XED_IFORM_RORX_VGPR32d_MEMd_IMMb}, +{"RORX_VGPR32d_VGPR32d_IMMb", XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb}, +{"RORX_VGPR64q_MEMq_IMMb", XED_IFORM_RORX_VGPR64q_MEMq_IMMb}, +{"RORX_VGPR64q_VGPR64q_IMMb", XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb}, +{"ROUNDPD_XMMpd_MEMpd_IMMb", XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb}, +{"ROUNDPD_XMMpd_XMMpd_IMMb", XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb}, +{"ROUNDPS_XMMps_MEMps_IMMb", XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb}, +{"ROUNDPS_XMMps_XMMps_IMMb", XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb}, +{"ROUNDSD_XMMq_MEMq_IMMb", XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb}, +{"ROUNDSD_XMMq_XMMq_IMMb", XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb}, +{"ROUNDSS_XMMd_MEMd_IMMb", XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb}, +{"ROUNDSS_XMMd_XMMd_IMMb", XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb}, +{"RSM", XED_IFORM_RSM}, +{"RSQRTPS_XMMps_MEMps", XED_IFORM_RSQRTPS_XMMps_MEMps}, +{"RSQRTPS_XMMps_XMMps", XED_IFORM_RSQRTPS_XMMps_XMMps}, +{"RSQRTSS_XMMss_MEMss", XED_IFORM_RSQRTSS_XMMss_MEMss}, +{"RSQRTSS_XMMss_XMMss", XED_IFORM_RSQRTSS_XMMss_XMMss}, +{"RSTORSSP_MEMu64", XED_IFORM_RSTORSSP_MEMu64}, +{"SAHF", XED_IFORM_SAHF}, +{"SALC", XED_IFORM_SALC}, +{"SAR_GPR8_CL", XED_IFORM_SAR_GPR8_CL}, +{"SAR_GPR8_IMMb", XED_IFORM_SAR_GPR8_IMMb}, +{"SAR_GPR8_ONE", XED_IFORM_SAR_GPR8_ONE}, +{"SAR_GPRv_CL", XED_IFORM_SAR_GPRv_CL}, +{"SAR_GPRv_IMMb", XED_IFORM_SAR_GPRv_IMMb}, +{"SAR_GPRv_ONE", XED_IFORM_SAR_GPRv_ONE}, +{"SAR_MEMb_CL", XED_IFORM_SAR_MEMb_CL}, +{"SAR_MEMb_IMMb", XED_IFORM_SAR_MEMb_IMMb}, +{"SAR_MEMb_ONE", XED_IFORM_SAR_MEMb_ONE}, +{"SAR_MEMv_CL", XED_IFORM_SAR_MEMv_CL}, +{"SAR_MEMv_IMMb", XED_IFORM_SAR_MEMv_IMMb}, +{"SAR_MEMv_ONE", XED_IFORM_SAR_MEMv_ONE}, +{"SARX_VGPR32d_MEMd_VGPR32d", XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d}, +{"SARX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d}, +{"SARX_VGPR64q_MEMq_VGPR64q", XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q}, +{"SARX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q}, +{"SAVEPREVSSP", XED_IFORM_SAVEPREVSSP}, +{"SBB_AL_IMMb", XED_IFORM_SBB_AL_IMMb}, +{"SBB_GPR8_GPR8_18", XED_IFORM_SBB_GPR8_GPR8_18}, +{"SBB_GPR8_GPR8_1A", XED_IFORM_SBB_GPR8_GPR8_1A}, +{"SBB_GPR8_IMMb_80r3", XED_IFORM_SBB_GPR8_IMMb_80r3}, +{"SBB_GPR8_IMMb_82r3", XED_IFORM_SBB_GPR8_IMMb_82r3}, +{"SBB_GPR8_MEMb", XED_IFORM_SBB_GPR8_MEMb}, +{"SBB_GPRv_GPRv_19", XED_IFORM_SBB_GPRv_GPRv_19}, +{"SBB_GPRv_GPRv_1B", XED_IFORM_SBB_GPRv_GPRv_1B}, +{"SBB_GPRv_IMMb", XED_IFORM_SBB_GPRv_IMMb}, +{"SBB_GPRv_IMMz", XED_IFORM_SBB_GPRv_IMMz}, +{"SBB_GPRv_MEMv", XED_IFORM_SBB_GPRv_MEMv}, +{"SBB_MEMb_GPR8", XED_IFORM_SBB_MEMb_GPR8}, +{"SBB_MEMb_IMMb_80r3", XED_IFORM_SBB_MEMb_IMMb_80r3}, +{"SBB_MEMb_IMMb_82r3", XED_IFORM_SBB_MEMb_IMMb_82r3}, +{"SBB_MEMv_GPRv", XED_IFORM_SBB_MEMv_GPRv}, +{"SBB_MEMv_IMMb", XED_IFORM_SBB_MEMv_IMMb}, +{"SBB_MEMv_IMMz", XED_IFORM_SBB_MEMv_IMMz}, +{"SBB_OrAX_IMMz", XED_IFORM_SBB_OrAX_IMMz}, +{"SBB_LOCK_MEMb_GPR8", XED_IFORM_SBB_LOCK_MEMb_GPR8}, +{"SBB_LOCK_MEMb_IMMb_80r3", XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3}, +{"SBB_LOCK_MEMb_IMMb_82r3", XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3}, +{"SBB_LOCK_MEMv_GPRv", XED_IFORM_SBB_LOCK_MEMv_GPRv}, +{"SBB_LOCK_MEMv_IMMb", XED_IFORM_SBB_LOCK_MEMv_IMMb}, +{"SBB_LOCK_MEMv_IMMz", XED_IFORM_SBB_LOCK_MEMv_IMMz}, +{"SCASB", XED_IFORM_SCASB}, +{"SCASD", XED_IFORM_SCASD}, +{"SCASQ", XED_IFORM_SCASQ}, +{"SCASW", XED_IFORM_SCASW}, +{"SEAMCALL", XED_IFORM_SEAMCALL}, +{"SEAMOPS", XED_IFORM_SEAMOPS}, +{"SEAMRET", XED_IFORM_SEAMRET}, +{"SENDUIPI_GPR32u32", XED_IFORM_SENDUIPI_GPR32u32}, +{"SERIALIZE", XED_IFORM_SERIALIZE}, +{"SETB_GPR8", XED_IFORM_SETB_GPR8}, +{"SETB_MEMb", XED_IFORM_SETB_MEMb}, +{"SETBE_GPR8", XED_IFORM_SETBE_GPR8}, +{"SETBE_MEMb", XED_IFORM_SETBE_MEMb}, +{"SETL_GPR8", XED_IFORM_SETL_GPR8}, +{"SETL_MEMb", XED_IFORM_SETL_MEMb}, +{"SETLE_GPR8", XED_IFORM_SETLE_GPR8}, +{"SETLE_MEMb", XED_IFORM_SETLE_MEMb}, +{"SETNB_GPR8", XED_IFORM_SETNB_GPR8}, +{"SETNB_MEMb", XED_IFORM_SETNB_MEMb}, +{"SETNBE_GPR8", XED_IFORM_SETNBE_GPR8}, +{"SETNBE_MEMb", XED_IFORM_SETNBE_MEMb}, +{"SETNL_GPR8", XED_IFORM_SETNL_GPR8}, +{"SETNL_MEMb", XED_IFORM_SETNL_MEMb}, +{"SETNLE_GPR8", XED_IFORM_SETNLE_GPR8}, +{"SETNLE_MEMb", XED_IFORM_SETNLE_MEMb}, +{"SETNO_GPR8", XED_IFORM_SETNO_GPR8}, +{"SETNO_MEMb", XED_IFORM_SETNO_MEMb}, +{"SETNP_GPR8", XED_IFORM_SETNP_GPR8}, +{"SETNP_MEMb", XED_IFORM_SETNP_MEMb}, +{"SETNS_GPR8", XED_IFORM_SETNS_GPR8}, +{"SETNS_MEMb", XED_IFORM_SETNS_MEMb}, +{"SETNZ_GPR8", XED_IFORM_SETNZ_GPR8}, +{"SETNZ_MEMb", XED_IFORM_SETNZ_MEMb}, +{"SETO_GPR8", XED_IFORM_SETO_GPR8}, +{"SETO_MEMb", XED_IFORM_SETO_MEMb}, +{"SETP_GPR8", XED_IFORM_SETP_GPR8}, +{"SETP_MEMb", XED_IFORM_SETP_MEMb}, +{"SETS_GPR8", XED_IFORM_SETS_GPR8}, +{"SETS_MEMb", XED_IFORM_SETS_MEMb}, +{"SETSSBSY", XED_IFORM_SETSSBSY}, +{"SETZ_GPR8", XED_IFORM_SETZ_GPR8}, +{"SETZ_MEMb", XED_IFORM_SETZ_MEMb}, +{"SFENCE", XED_IFORM_SFENCE}, +{"SGDT_MEMs", XED_IFORM_SGDT_MEMs}, +{"SGDT_MEMs64", XED_IFORM_SGDT_MEMs64}, +{"SHA1MSG1_XMMi32_MEMi32_SHA", XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA}, +{"SHA1MSG1_XMMi32_XMMi32_SHA", XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA}, +{"SHA1MSG2_XMMi32_MEMi32_SHA", XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA}, +{"SHA1MSG2_XMMi32_XMMi32_SHA", XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA}, +{"SHA1NEXTE_XMMi32_MEMi32_SHA", XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA}, +{"SHA1NEXTE_XMMi32_XMMi32_SHA", XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA}, +{"SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA", XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA}, +{"SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA", XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA}, +{"SHA256MSG1_XMMi32_MEMi32_SHA", XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA}, +{"SHA256MSG1_XMMi32_XMMi32_SHA", XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA}, +{"SHA256MSG2_XMMi32_MEMi32_SHA", XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA}, +{"SHA256MSG2_XMMi32_XMMi32_SHA", XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA}, +{"SHA256RNDS2_XMMi32_MEMi32_SHA", XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA}, +{"SHA256RNDS2_XMMi32_XMMi32_SHA", XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA}, +{"SHL_GPR8_CL_D2r4", XED_IFORM_SHL_GPR8_CL_D2r4}, +{"SHL_GPR8_CL_D2r6", XED_IFORM_SHL_GPR8_CL_D2r6}, +{"SHL_GPR8_IMMb_C0r4", XED_IFORM_SHL_GPR8_IMMb_C0r4}, +{"SHL_GPR8_IMMb_C0r6", XED_IFORM_SHL_GPR8_IMMb_C0r6}, +{"SHL_GPR8_ONE_D0r4", XED_IFORM_SHL_GPR8_ONE_D0r4}, +{"SHL_GPR8_ONE_D0r6", XED_IFORM_SHL_GPR8_ONE_D0r6}, +{"SHL_GPRv_CL_D3r4", XED_IFORM_SHL_GPRv_CL_D3r4}, +{"SHL_GPRv_CL_D3r6", XED_IFORM_SHL_GPRv_CL_D3r6}, +{"SHL_GPRv_IMMb_C1r4", XED_IFORM_SHL_GPRv_IMMb_C1r4}, +{"SHL_GPRv_IMMb_C1r6", XED_IFORM_SHL_GPRv_IMMb_C1r6}, +{"SHL_GPRv_ONE_D1r4", XED_IFORM_SHL_GPRv_ONE_D1r4}, +{"SHL_GPRv_ONE_D1r6", XED_IFORM_SHL_GPRv_ONE_D1r6}, +{"SHL_MEMb_CL_D2r4", XED_IFORM_SHL_MEMb_CL_D2r4}, +{"SHL_MEMb_CL_D2r6", XED_IFORM_SHL_MEMb_CL_D2r6}, +{"SHL_MEMb_IMMb_C0r4", XED_IFORM_SHL_MEMb_IMMb_C0r4}, +{"SHL_MEMb_IMMb_C0r6", XED_IFORM_SHL_MEMb_IMMb_C0r6}, +{"SHL_MEMb_ONE_D0r4", XED_IFORM_SHL_MEMb_ONE_D0r4}, +{"SHL_MEMb_ONE_D0r6", XED_IFORM_SHL_MEMb_ONE_D0r6}, +{"SHL_MEMv_CL_D3r4", XED_IFORM_SHL_MEMv_CL_D3r4}, +{"SHL_MEMv_CL_D3r6", XED_IFORM_SHL_MEMv_CL_D3r6}, +{"SHL_MEMv_IMMb_C1r4", XED_IFORM_SHL_MEMv_IMMb_C1r4}, +{"SHL_MEMv_IMMb_C1r6", XED_IFORM_SHL_MEMv_IMMb_C1r6}, +{"SHL_MEMv_ONE_D1r4", XED_IFORM_SHL_MEMv_ONE_D1r4}, +{"SHL_MEMv_ONE_D1r6", XED_IFORM_SHL_MEMv_ONE_D1r6}, +{"SHLD_GPRv_GPRv_CL", XED_IFORM_SHLD_GPRv_GPRv_CL}, +{"SHLD_GPRv_GPRv_IMMb", XED_IFORM_SHLD_GPRv_GPRv_IMMb}, +{"SHLD_MEMv_GPRv_CL", XED_IFORM_SHLD_MEMv_GPRv_CL}, +{"SHLD_MEMv_GPRv_IMMb", XED_IFORM_SHLD_MEMv_GPRv_IMMb}, +{"SHLX_VGPR32d_MEMd_VGPR32d", XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d}, +{"SHLX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d}, +{"SHLX_VGPR64q_MEMq_VGPR64q", XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q}, +{"SHLX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q}, +{"SHR_GPR8_CL", XED_IFORM_SHR_GPR8_CL}, +{"SHR_GPR8_IMMb", XED_IFORM_SHR_GPR8_IMMb}, +{"SHR_GPR8_ONE", XED_IFORM_SHR_GPR8_ONE}, +{"SHR_GPRv_CL", XED_IFORM_SHR_GPRv_CL}, +{"SHR_GPRv_IMMb", XED_IFORM_SHR_GPRv_IMMb}, +{"SHR_GPRv_ONE", XED_IFORM_SHR_GPRv_ONE}, +{"SHR_MEMb_CL", XED_IFORM_SHR_MEMb_CL}, +{"SHR_MEMb_IMMb", XED_IFORM_SHR_MEMb_IMMb}, +{"SHR_MEMb_ONE", XED_IFORM_SHR_MEMb_ONE}, +{"SHR_MEMv_CL", XED_IFORM_SHR_MEMv_CL}, +{"SHR_MEMv_IMMb", XED_IFORM_SHR_MEMv_IMMb}, +{"SHR_MEMv_ONE", XED_IFORM_SHR_MEMv_ONE}, +{"SHRD_GPRv_GPRv_CL", XED_IFORM_SHRD_GPRv_GPRv_CL}, +{"SHRD_GPRv_GPRv_IMMb", XED_IFORM_SHRD_GPRv_GPRv_IMMb}, +{"SHRD_MEMv_GPRv_CL", XED_IFORM_SHRD_MEMv_GPRv_CL}, +{"SHRD_MEMv_GPRv_IMMb", XED_IFORM_SHRD_MEMv_GPRv_IMMb}, +{"SHRX_VGPR32d_MEMd_VGPR32d", XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d}, +{"SHRX_VGPR32d_VGPR32d_VGPR32d", XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d}, +{"SHRX_VGPR64q_MEMq_VGPR64q", XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q}, +{"SHRX_VGPR64q_VGPR64q_VGPR64q", XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q}, +{"SHUFPD_XMMpd_MEMpd_IMMb", XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb}, +{"SHUFPD_XMMpd_XMMpd_IMMb", XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb}, +{"SHUFPS_XMMps_MEMps_IMMb", XED_IFORM_SHUFPS_XMMps_MEMps_IMMb}, +{"SHUFPS_XMMps_XMMps_IMMb", XED_IFORM_SHUFPS_XMMps_XMMps_IMMb}, +{"SIDT_MEMs", XED_IFORM_SIDT_MEMs}, +{"SIDT_MEMs64", XED_IFORM_SIDT_MEMs64}, +{"SKINIT_EAX", XED_IFORM_SKINIT_EAX}, +{"SLDT_GPRv", XED_IFORM_SLDT_GPRv}, +{"SLDT_MEMw", XED_IFORM_SLDT_MEMw}, +{"SLWPCB_VGPRyy", XED_IFORM_SLWPCB_VGPRyy}, +{"SMSW_GPRv", XED_IFORM_SMSW_GPRv}, +{"SMSW_MEMw", XED_IFORM_SMSW_MEMw}, +{"SQRTPD_XMMpd_MEMpd", XED_IFORM_SQRTPD_XMMpd_MEMpd}, +{"SQRTPD_XMMpd_XMMpd", XED_IFORM_SQRTPD_XMMpd_XMMpd}, +{"SQRTPS_XMMps_MEMps", XED_IFORM_SQRTPS_XMMps_MEMps}, +{"SQRTPS_XMMps_XMMps", XED_IFORM_SQRTPS_XMMps_XMMps}, +{"SQRTSD_XMMsd_MEMsd", XED_IFORM_SQRTSD_XMMsd_MEMsd}, +{"SQRTSD_XMMsd_XMMsd", XED_IFORM_SQRTSD_XMMsd_XMMsd}, +{"SQRTSS_XMMss_MEMss", XED_IFORM_SQRTSS_XMMss_MEMss}, +{"SQRTSS_XMMss_XMMss", XED_IFORM_SQRTSS_XMMss_XMMss}, +{"STAC", XED_IFORM_STAC}, +{"STC", XED_IFORM_STC}, +{"STD", XED_IFORM_STD}, +{"STGI", XED_IFORM_STGI}, +{"STI", XED_IFORM_STI}, +{"STMXCSR_MEMd", XED_IFORM_STMXCSR_MEMd}, +{"STOSB", XED_IFORM_STOSB}, +{"STOSD", XED_IFORM_STOSD}, +{"STOSQ", XED_IFORM_STOSQ}, +{"STOSW", XED_IFORM_STOSW}, +{"STR_GPRv", XED_IFORM_STR_GPRv}, +{"STR_MEMw", XED_IFORM_STR_MEMw}, +{"STTILECFG_MEM", XED_IFORM_STTILECFG_MEM}, +{"STUI", XED_IFORM_STUI}, +{"SUB_AL_IMMb", XED_IFORM_SUB_AL_IMMb}, +{"SUB_GPR8_GPR8_28", XED_IFORM_SUB_GPR8_GPR8_28}, +{"SUB_GPR8_GPR8_2A", XED_IFORM_SUB_GPR8_GPR8_2A}, +{"SUB_GPR8_IMMb_80r5", XED_IFORM_SUB_GPR8_IMMb_80r5}, +{"SUB_GPR8_IMMb_82r5", XED_IFORM_SUB_GPR8_IMMb_82r5}, +{"SUB_GPR8_MEMb", XED_IFORM_SUB_GPR8_MEMb}, +{"SUB_GPRv_GPRv_29", XED_IFORM_SUB_GPRv_GPRv_29}, +{"SUB_GPRv_GPRv_2B", XED_IFORM_SUB_GPRv_GPRv_2B}, +{"SUB_GPRv_IMMb", XED_IFORM_SUB_GPRv_IMMb}, +{"SUB_GPRv_IMMz", XED_IFORM_SUB_GPRv_IMMz}, +{"SUB_GPRv_MEMv", XED_IFORM_SUB_GPRv_MEMv}, +{"SUB_MEMb_GPR8", XED_IFORM_SUB_MEMb_GPR8}, +{"SUB_MEMb_IMMb_80r5", XED_IFORM_SUB_MEMb_IMMb_80r5}, +{"SUB_MEMb_IMMb_82r5", XED_IFORM_SUB_MEMb_IMMb_82r5}, +{"SUB_MEMv_GPRv", XED_IFORM_SUB_MEMv_GPRv}, +{"SUB_MEMv_IMMb", XED_IFORM_SUB_MEMv_IMMb}, +{"SUB_MEMv_IMMz", XED_IFORM_SUB_MEMv_IMMz}, +{"SUB_OrAX_IMMz", XED_IFORM_SUB_OrAX_IMMz}, +{"SUBPD_XMMpd_MEMpd", XED_IFORM_SUBPD_XMMpd_MEMpd}, +{"SUBPD_XMMpd_XMMpd", XED_IFORM_SUBPD_XMMpd_XMMpd}, +{"SUBPS_XMMps_MEMps", XED_IFORM_SUBPS_XMMps_MEMps}, +{"SUBPS_XMMps_XMMps", XED_IFORM_SUBPS_XMMps_XMMps}, +{"SUBSD_XMMsd_MEMsd", XED_IFORM_SUBSD_XMMsd_MEMsd}, +{"SUBSD_XMMsd_XMMsd", XED_IFORM_SUBSD_XMMsd_XMMsd}, +{"SUBSS_XMMss_MEMss", XED_IFORM_SUBSS_XMMss_MEMss}, +{"SUBSS_XMMss_XMMss", XED_IFORM_SUBSS_XMMss_XMMss}, +{"SUB_LOCK_MEMb_GPR8", XED_IFORM_SUB_LOCK_MEMb_GPR8}, +{"SUB_LOCK_MEMb_IMMb_80r5", XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5}, +{"SUB_LOCK_MEMb_IMMb_82r5", XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5}, +{"SUB_LOCK_MEMv_GPRv", XED_IFORM_SUB_LOCK_MEMv_GPRv}, +{"SUB_LOCK_MEMv_IMMb", XED_IFORM_SUB_LOCK_MEMv_IMMb}, +{"SUB_LOCK_MEMv_IMMz", XED_IFORM_SUB_LOCK_MEMv_IMMz}, +{"SWAPGS", XED_IFORM_SWAPGS}, +{"SYSCALL", XED_IFORM_SYSCALL}, +{"SYSCALL_AMD", XED_IFORM_SYSCALL_AMD}, +{"SYSENTER", XED_IFORM_SYSENTER}, +{"SYSEXIT", XED_IFORM_SYSEXIT}, +{"SYSRET", XED_IFORM_SYSRET}, +{"SYSRET64", XED_IFORM_SYSRET64}, +{"SYSRET_AMD", XED_IFORM_SYSRET_AMD}, +{"T1MSKC_VGPR32d_MEMd", XED_IFORM_T1MSKC_VGPR32d_MEMd}, +{"T1MSKC_VGPR32d_VGPR32d", XED_IFORM_T1MSKC_VGPR32d_VGPR32d}, +{"T1MSKC_VGPRyy_MEMy", XED_IFORM_T1MSKC_VGPRyy_MEMy}, +{"T1MSKC_VGPRyy_VGPRyy", XED_IFORM_T1MSKC_VGPRyy_VGPRyy}, +{"TDCALL", XED_IFORM_TDCALL}, +{"TDPBF16PS_TMMf32_TMMu32_TMMu32", XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32}, +{"TDPBSSD_TMMi32_TMMu32_TMMu32", XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32}, +{"TDPBSUD_TMMi32_TMMu32_TMMu32", XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32}, +{"TDPBUSD_TMMi32_TMMu32_TMMu32", XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32}, +{"TDPBUUD_TMMu32_TMMu32_TMMu32", XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32}, +{"TEST_AL_IMMb", XED_IFORM_TEST_AL_IMMb}, +{"TEST_GPR8_GPR8", XED_IFORM_TEST_GPR8_GPR8}, +{"TEST_GPR8_IMMb_F6r0", XED_IFORM_TEST_GPR8_IMMb_F6r0}, +{"TEST_GPR8_IMMb_F6r1", XED_IFORM_TEST_GPR8_IMMb_F6r1}, +{"TEST_GPRv_GPRv", XED_IFORM_TEST_GPRv_GPRv}, +{"TEST_GPRv_IMMz_F7r0", XED_IFORM_TEST_GPRv_IMMz_F7r0}, +{"TEST_GPRv_IMMz_F7r1", XED_IFORM_TEST_GPRv_IMMz_F7r1}, +{"TEST_MEMb_GPR8", XED_IFORM_TEST_MEMb_GPR8}, +{"TEST_MEMb_IMMb_F6r0", XED_IFORM_TEST_MEMb_IMMb_F6r0}, +{"TEST_MEMb_IMMb_F6r1", XED_IFORM_TEST_MEMb_IMMb_F6r1}, +{"TEST_MEMv_GPRv", XED_IFORM_TEST_MEMv_GPRv}, +{"TEST_MEMv_IMMz_F7r0", XED_IFORM_TEST_MEMv_IMMz_F7r0}, +{"TEST_MEMv_IMMz_F7r1", XED_IFORM_TEST_MEMv_IMMz_F7r1}, +{"TEST_OrAX_IMMz", XED_IFORM_TEST_OrAX_IMMz}, +{"TESTUI", XED_IFORM_TESTUI}, +{"TILELOADD_TMMu32_MEMu32", XED_IFORM_TILELOADD_TMMu32_MEMu32}, +{"TILELOADDT1_TMMu32_MEMu32", XED_IFORM_TILELOADDT1_TMMu32_MEMu32}, +{"TILERELEASE", XED_IFORM_TILERELEASE}, +{"TILESTORED_MEMu32_TMMu32", XED_IFORM_TILESTORED_MEMu32_TMMu32}, +{"TILEZERO_TMMu32", XED_IFORM_TILEZERO_TMMu32}, +{"TLBSYNC", XED_IFORM_TLBSYNC}, +{"TPAUSE_GPR32u32", XED_IFORM_TPAUSE_GPR32u32}, +{"TZCNT_GPRv_GPRv", XED_IFORM_TZCNT_GPRv_GPRv}, +{"TZCNT_GPRv_MEMv", XED_IFORM_TZCNT_GPRv_MEMv}, +{"TZMSK_VGPR32d_MEMd", XED_IFORM_TZMSK_VGPR32d_MEMd}, +{"TZMSK_VGPR32d_VGPR32d", XED_IFORM_TZMSK_VGPR32d_VGPR32d}, +{"TZMSK_VGPRyy_MEMy", XED_IFORM_TZMSK_VGPRyy_MEMy}, +{"TZMSK_VGPRyy_VGPRyy", XED_IFORM_TZMSK_VGPRyy_VGPRyy}, +{"UCOMISD_XMMsd_MEMsd", XED_IFORM_UCOMISD_XMMsd_MEMsd}, +{"UCOMISD_XMMsd_XMMsd", XED_IFORM_UCOMISD_XMMsd_XMMsd}, +{"UCOMISS_XMMss_MEMss", XED_IFORM_UCOMISS_XMMss_MEMss}, +{"UCOMISS_XMMss_XMMss", XED_IFORM_UCOMISS_XMMss_XMMss}, +{"UD0", XED_IFORM_UD0}, +{"UD0_GPR32_GPR32", XED_IFORM_UD0_GPR32_GPR32}, +{"UD0_GPR32_MEMd", XED_IFORM_UD0_GPR32_MEMd}, +{"UD1_GPR32_GPR32", XED_IFORM_UD1_GPR32_GPR32}, +{"UD1_GPR32_MEMd", XED_IFORM_UD1_GPR32_MEMd}, +{"UD2", XED_IFORM_UD2}, +{"UIRET", XED_IFORM_UIRET}, +{"UMONITOR_GPRa", XED_IFORM_UMONITOR_GPRa}, +{"UMWAIT_GPR32", XED_IFORM_UMWAIT_GPR32}, +{"UNPCKHPD_XMMpd_MEMdq", XED_IFORM_UNPCKHPD_XMMpd_MEMdq}, +{"UNPCKHPD_XMMpd_XMMq", XED_IFORM_UNPCKHPD_XMMpd_XMMq}, +{"UNPCKHPS_XMMps_MEMdq", XED_IFORM_UNPCKHPS_XMMps_MEMdq}, +{"UNPCKHPS_XMMps_XMMdq", XED_IFORM_UNPCKHPS_XMMps_XMMdq}, +{"UNPCKLPD_XMMpd_MEMdq", XED_IFORM_UNPCKLPD_XMMpd_MEMdq}, +{"UNPCKLPD_XMMpd_XMMq", XED_IFORM_UNPCKLPD_XMMpd_XMMq}, +{"UNPCKLPS_XMMps_MEMdq", XED_IFORM_UNPCKLPS_XMMps_MEMdq}, +{"UNPCKLPS_XMMps_XMMq", XED_IFORM_UNPCKLPS_XMMps_XMMq}, +{"V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VADDPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq}, +{"VADDPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq}, +{"VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VADDPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq}, +{"VADDPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq}, +{"VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VADDPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq}, +{"VADDPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq}, +{"VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VADDPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq}, +{"VADDPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq}, +{"VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VADDSD_XMMdq_XMMdq_MEMq", XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq}, +{"VADDSD_XMMdq_XMMdq_XMMq", XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq}, +{"VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VADDSS_XMMdq_XMMdq_MEMd", XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd}, +{"VADDSS_XMMdq_XMMdq_XMMd", XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd}, +{"VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VADDSUBPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq}, +{"VADDSUBPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq}, +{"VADDSUBPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq}, +{"VADDSUBPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq}, +{"VADDSUBPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq}, +{"VADDSUBPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq}, +{"VADDSUBPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq}, +{"VADDSUBPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq}, +{"VAESDEC_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq}, +{"VAESDEC_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq}, +{"VAESDEC_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512}, +{"VAESDEC_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512}, +{"VAESDEC_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128}, +{"VAESDEC_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512}, +{"VAESDEC_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128}, +{"VAESDEC_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512}, +{"VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512}, +{"VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512}, +{"VAESDECLAST_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq}, +{"VAESDECLAST_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq}, +{"VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512}, +{"VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512}, +{"VAESDECLAST_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128}, +{"VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512}, +{"VAESDECLAST_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128}, +{"VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512}, +{"VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512}, +{"VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512}, +{"VAESENC_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq}, +{"VAESENC_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq}, +{"VAESENC_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512}, +{"VAESENC_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512}, +{"VAESENC_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128}, +{"VAESENC_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512}, +{"VAESENC_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128}, +{"VAESENC_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512}, +{"VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512}, +{"VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512}, +{"VAESENCLAST_XMMdq_XMMdq_MEMdq", XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq}, +{"VAESENCLAST_XMMdq_XMMdq_XMMdq", XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq}, +{"VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512", XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512}, +{"VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512", XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512}, +{"VAESENCLAST_YMMu128_YMMu128_MEMu128", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128}, +{"VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512}, +{"VAESENCLAST_YMMu128_YMMu128_YMMu128", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128}, +{"VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512", XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512}, +{"VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512", XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512}, +{"VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512", XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512}, +{"VAESIMC_XMMdq_MEMdq", XED_IFORM_VAESIMC_XMMdq_MEMdq}, +{"VAESIMC_XMMdq_XMMdq", XED_IFORM_VAESIMC_XMMdq_XMMdq}, +{"VAESKEYGENASSIST_XMMdq_MEMdq_IMMb", XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb}, +{"VAESKEYGENASSIST_XMMdq_XMMdq_IMMb", XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb}, +{"VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512}, +{"VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512}, +{"VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512}, +{"VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512}, +{"VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512}, +{"VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512}, +{"VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512}, +{"VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VANDNPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq}, +{"VANDNPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq}, +{"VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VANDNPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq}, +{"VANDNPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq}, +{"VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VANDNPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq}, +{"VANDNPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq}, +{"VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VANDNPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq}, +{"VANDNPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq}, +{"VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VANDPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq}, +{"VANDPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq}, +{"VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VANDPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq}, +{"VANDPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq}, +{"VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VANDPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq}, +{"VANDPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq}, +{"VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VANDPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq}, +{"VANDPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq}, +{"VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb}, +{"VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb}, +{"VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb}, +{"VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb}, +{"VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb}, +{"VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb}, +{"VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VBROADCASTF128_YMMqq_MEMdq", XED_IFORM_VBROADCASTF128_YMMqq_MEMdq}, +{"VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512}, +{"VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512}, +{"VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VBROADCASTI128_YMMqq_MEMdq", XED_IFORM_VBROADCASTI128_YMMqq_MEMdq}, +{"VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512}, +{"VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512}, +{"VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512}, +{"VBROADCASTSD_YMMqq_MEMq", XED_IFORM_VBROADCASTSD_YMMqq_MEMq}, +{"VBROADCASTSD_YMMqq_XMMdq", XED_IFORM_VBROADCASTSD_YMMqq_XMMdq}, +{"VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512}, +{"VBROADCASTSS_XMMdq_MEMd", XED_IFORM_VBROADCASTSS_XMMdq_MEMd}, +{"VBROADCASTSS_XMMdq_XMMdq", XED_IFORM_VBROADCASTSS_XMMdq_XMMdq}, +{"VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512}, +{"VBROADCASTSS_YMMqq_MEMd", XED_IFORM_VBROADCASTSS_YMMqq_MEMd}, +{"VBROADCASTSS_YMMqq_XMMdq", XED_IFORM_VBROADCASTSS_YMMqq_XMMdq}, +{"VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512}, +{"VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512}, +{"VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512}, +{"VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512}, +{"VCMPPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VCMPPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VCMPPD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb}, +{"VCMPPD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb}, +{"VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512}, +{"VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512}, +{"VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512}, +{"VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512}, +{"VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512}, +{"VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512", XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512}, +{"VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512}, +{"VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512}, +{"VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512}, +{"VCMPPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb}, +{"VCMPPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb}, +{"VCMPPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb}, +{"VCMPPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb}, +{"VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VCMPSD_XMMdq_XMMdq_MEMq_IMMb", XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb}, +{"VCMPSD_XMMdq_XMMdq_XMMq_IMMb", XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb}, +{"VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512}, +{"VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512}, +{"VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VCMPSS_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb}, +{"VCMPSS_XMMdq_XMMdq_XMMd_IMMb", XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb}, +{"VCOMISD_XMMf64_MEMf64_AVX512", XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512}, +{"VCOMISD_XMMf64_XMMf64_AVX512", XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512}, +{"VCOMISD_XMMq_MEMq", XED_IFORM_VCOMISD_XMMq_MEMq}, +{"VCOMISD_XMMq_XMMq", XED_IFORM_VCOMISD_XMMq_XMMq}, +{"VCOMISH_XMMf16_MEMf16_AVX512", XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512}, +{"VCOMISH_XMMf16_XMMf16_AVX512", XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512}, +{"VCOMISS_XMMd_MEMd", XED_IFORM_VCOMISS_XMMd_MEMd}, +{"VCOMISS_XMMd_XMMd", XED_IFORM_VCOMISS_XMMd_XMMd}, +{"VCOMISS_XMMf32_MEMf32_AVX512", XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512}, +{"VCOMISS_XMMf32_XMMf32_AVX512", XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512}, +{"VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512}, +{"VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512}, +{"VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512}, +{"VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512}, +{"VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512}, +{"VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512}, +{"VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VCVTDQ2PD_XMMdq_MEMq", XED_IFORM_VCVTDQ2PD_XMMdq_MEMq}, +{"VCVTDQ2PD_XMMdq_XMMq", XED_IFORM_VCVTDQ2PD_XMMdq_XMMq}, +{"VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512}, +{"VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512}, +{"VCVTDQ2PD_YMMqq_MEMdq", XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq}, +{"VCVTDQ2PD_YMMqq_XMMdq", XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq}, +{"VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512", XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512}, +{"VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128}, +{"VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256}, +{"VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512}, +{"VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512", XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512}, +{"VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512", XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512}, +{"VCVTDQ2PS_XMMdq_MEMdq", XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq}, +{"VCVTDQ2PS_XMMdq_XMMdq", XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq}, +{"VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512", XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512}, +{"VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512", XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512}, +{"VCVTDQ2PS_YMMqq_MEMqq", XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq}, +{"VCVTDQ2PS_YMMqq_YMMqq", XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq}, +{"VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512", XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512}, +{"VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512", XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512}, +{"VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128", XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128}, +{"VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256", XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256}, +{"VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512", XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512}, +{"VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128}, +{"VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256}, +{"VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512}, +{"VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512}, +{"VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512}, +{"VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512}, +{"VCVTPD2DQ_XMMdq_MEMdq", XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq}, +{"VCVTPD2DQ_XMMdq_MEMqq", XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq}, +{"VCVTPD2DQ_XMMdq_XMMdq", XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq}, +{"VCVTPD2DQ_XMMdq_YMMqq", XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq}, +{"VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128}, +{"VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256}, +{"VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128}, +{"VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256}, +{"VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512}, +{"VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512}, +{"VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128}, +{"VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256}, +{"VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512}, +{"VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512}, +{"VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512}, +{"VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512}, +{"VCVTPD2PS_XMMdq_MEMdq", XED_IFORM_VCVTPD2PS_XMMdq_MEMdq}, +{"VCVTPD2PS_XMMdq_MEMqq", XED_IFORM_VCVTPD2PS_XMMdq_MEMqq}, +{"VCVTPD2PS_XMMdq_XMMdq", XED_IFORM_VCVTPD2PS_XMMdq_XMMdq}, +{"VCVTPD2PS_XMMdq_YMMqq", XED_IFORM_VCVTPD2PS_XMMdq_YMMqq}, +{"VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128}, +{"VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256}, +{"VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128}, +{"VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256}, +{"VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512}, +{"VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512}, +{"VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512}, +{"VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512}, +{"VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512}, +{"VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128}, +{"VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256}, +{"VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128}, +{"VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256}, +{"VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512}, +{"VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512}, +{"VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512}, +{"VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512}, +{"VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512}, +{"VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512}, +{"VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512}, +{"VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512}, +{"VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512}, +{"VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PS_XMMdq_MEMq", XED_IFORM_VCVTPH2PS_XMMdq_MEMq}, +{"VCVTPH2PS_XMMdq_XMMq", XED_IFORM_VCVTPH2PS_XMMdq_XMMq}, +{"VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PS_YMMqq_MEMdq", XED_IFORM_VCVTPH2PS_YMMqq_MEMdq}, +{"VCVTPH2PS_YMMqq_XMMdq", XED_IFORM_VCVTPH2PS_YMMqq_XMMdq}, +{"VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512}, +{"VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512}, +{"VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512}, +{"VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512}, +{"VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512}, +{"VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512}, +{"VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512}, +{"VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512}, +{"VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512}, +{"VCVTPS2DQ_XMMdq_MEMdq", XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq}, +{"VCVTPS2DQ_XMMdq_XMMdq", XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq}, +{"VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512}, +{"VCVTPS2DQ_YMMqq_MEMqq", XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq}, +{"VCVTPS2DQ_YMMqq_YMMqq", XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq}, +{"VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512}, +{"VCVTPS2PD_XMMdq_MEMq", XED_IFORM_VCVTPS2PD_XMMdq_MEMq}, +{"VCVTPS2PD_XMMdq_XMMq", XED_IFORM_VCVTPS2PD_XMMdq_XMMq}, +{"VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2PD_YMMqq_MEMdq", XED_IFORM_VCVTPS2PD_YMMqq_MEMdq}, +{"VCVTPS2PD_YMMqq_XMMdq", XED_IFORM_VCVTPS2PD_YMMqq_XMMdq}, +{"VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512}, +{"VCVTPS2PH_MEMdq_YMMqq_IMMb", XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb}, +{"VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512}, +{"VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512}, +{"VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VCVTPS2PH_MEMq_XMMdq_IMMb", XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb}, +{"VCVTPS2PH_XMMdq_YMMqq_IMMb", XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb}, +{"VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512}, +{"VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512}, +{"VCVTPS2PH_XMMq_XMMdq_IMMb", XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb}, +{"VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128}, +{"VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256}, +{"VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512}, +{"VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512}, +{"VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512}, +{"VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512}, +{"VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512}, +{"VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512}, +{"VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512}, +{"VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512}, +{"VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512}, +{"VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512}, +{"VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512}, +{"VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512}, +{"VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128}, +{"VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256}, +{"VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512}, +{"VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512}, +{"VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512}, +{"VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512}, +{"VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128}, +{"VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256}, +{"VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128}, +{"VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256}, +{"VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512}, +{"VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512}, +{"VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VCVTSD2SI_GPR32d_MEMq", XED_IFORM_VCVTSD2SI_GPR32d_MEMq}, +{"VCVTSD2SI_GPR32d_XMMq", XED_IFORM_VCVTSD2SI_GPR32d_XMMq}, +{"VCVTSD2SI_GPR32i32_MEMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512}, +{"VCVTSD2SI_GPR32i32_XMMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512}, +{"VCVTSD2SI_GPR64i64_MEMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512}, +{"VCVTSD2SI_GPR64i64_XMMf64_AVX512", XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512}, +{"VCVTSD2SI_GPR64q_MEMq", XED_IFORM_VCVTSD2SI_GPR64q_MEMq}, +{"VCVTSD2SI_GPR64q_XMMq", XED_IFORM_VCVTSD2SI_GPR64q_XMMq}, +{"VCVTSD2SS_XMMdq_XMMdq_MEMq", XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq}, +{"VCVTSD2SS_XMMdq_XMMdq_XMMq", XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq}, +{"VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VCVTSD2USI_GPR32u32_MEMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512}, +{"VCVTSD2USI_GPR32u32_XMMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512}, +{"VCVTSD2USI_GPR64u64_MEMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512}, +{"VCVTSD2USI_GPR64u64_XMMf64_AVX512", XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512}, +{"VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512", XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512}, +{"VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512", XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512}, +{"VCVTSH2SI_GPR32i32_MEMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512}, +{"VCVTSH2SI_GPR32i32_XMMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512}, +{"VCVTSH2SI_GPR64i64_MEMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512}, +{"VCVTSH2SI_GPR64i64_XMMf16_AVX512", XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512}, +{"VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512", XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512}, +{"VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512", XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512}, +{"VCVTSH2USI_GPR32u32_MEMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512}, +{"VCVTSH2USI_GPR32u32_XMMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512}, +{"VCVTSH2USI_GPR64u64_MEMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512}, +{"VCVTSH2USI_GPR64u64_XMMf16_AVX512", XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512}, +{"VCVTSI2SD_XMMdq_XMMdq_GPR32d", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d}, +{"VCVTSI2SD_XMMdq_XMMdq_GPR64q", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q}, +{"VCVTSI2SD_XMMdq_XMMdq_MEMd", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd}, +{"VCVTSI2SD_XMMdq_XMMdq_MEMq", XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq}, +{"VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512}, +{"VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512}, +{"VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512}, +{"VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512", XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512}, +{"VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512}, +{"VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512}, +{"VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512}, +{"VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512", XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512}, +{"VCVTSI2SS_XMMdq_XMMdq_GPR32d", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d}, +{"VCVTSI2SS_XMMdq_XMMdq_GPR64q", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q}, +{"VCVTSI2SS_XMMdq_XMMdq_MEMd", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd}, +{"VCVTSI2SS_XMMdq_XMMdq_MEMq", XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq}, +{"VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512}, +{"VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512}, +{"VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512}, +{"VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512", XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512}, +{"VCVTSS2SD_XMMdq_XMMdq_MEMd", XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd}, +{"VCVTSS2SD_XMMdq_XMMdq_XMMd", XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd}, +{"VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512", XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512}, +{"VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512", XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512}, +{"VCVTSS2SI_GPR32d_MEMd", XED_IFORM_VCVTSS2SI_GPR32d_MEMd}, +{"VCVTSS2SI_GPR32d_XMMd", XED_IFORM_VCVTSS2SI_GPR32d_XMMd}, +{"VCVTSS2SI_GPR32i32_MEMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512}, +{"VCVTSS2SI_GPR32i32_XMMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512}, +{"VCVTSS2SI_GPR64i64_MEMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512}, +{"VCVTSS2SI_GPR64i64_XMMf32_AVX512", XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512}, +{"VCVTSS2SI_GPR64q_MEMd", XED_IFORM_VCVTSS2SI_GPR64q_MEMd}, +{"VCVTSS2SI_GPR64q_XMMd", XED_IFORM_VCVTSS2SI_GPR64q_XMMd}, +{"VCVTSS2USI_GPR32u32_MEMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512}, +{"VCVTSS2USI_GPR32u32_XMMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512}, +{"VCVTSS2USI_GPR64u64_MEMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512}, +{"VCVTSS2USI_GPR64u64_XMMf32_AVX512", XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512}, +{"VCVTTPD2DQ_XMMdq_MEMdq", XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq}, +{"VCVTTPD2DQ_XMMdq_MEMqq", XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq}, +{"VCVTTPD2DQ_XMMdq_XMMdq", XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq}, +{"VCVTTPD2DQ_XMMdq_YMMqq", XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq}, +{"VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128}, +{"VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256}, +{"VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128}, +{"VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256}, +{"VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512}, +{"VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512}, +{"VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512}, +{"VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512}, +{"VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512}, +{"VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512}, +{"VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128}, +{"VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256}, +{"VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128}, +{"VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256}, +{"VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512}, +{"VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512}, +{"VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512}, +{"VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512}, +{"VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512}, +{"VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512}, +{"VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512}, +{"VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512}, +{"VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512}, +{"VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512}, +{"VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512}, +{"VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512}, +{"VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512", XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512}, +{"VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512", XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512}, +{"VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512", XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512}, +{"VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512}, +{"VCVTTPS2DQ_XMMdq_MEMdq", XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq}, +{"VCVTTPS2DQ_XMMdq_XMMdq", XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq}, +{"VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512}, +{"VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512}, +{"VCVTTPS2DQ_YMMqq_MEMqq", XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq}, +{"VCVTTPS2DQ_YMMqq_YMMqq", XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq}, +{"VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512}, +{"VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512}, +{"VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512}, +{"VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512}, +{"VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512}, +{"VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512}, +{"VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512}, +{"VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512}, +{"VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512}, +{"VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512}, +{"VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512", XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512}, +{"VCVTTSD2SI_GPR32d_MEMq", XED_IFORM_VCVTTSD2SI_GPR32d_MEMq}, +{"VCVTTSD2SI_GPR32d_XMMq", XED_IFORM_VCVTTSD2SI_GPR32d_XMMq}, +{"VCVTTSD2SI_GPR32i32_MEMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512}, +{"VCVTTSD2SI_GPR32i32_XMMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512}, +{"VCVTTSD2SI_GPR64i64_MEMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512}, +{"VCVTTSD2SI_GPR64i64_XMMf64_AVX512", XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512}, +{"VCVTTSD2SI_GPR64q_MEMq", XED_IFORM_VCVTTSD2SI_GPR64q_MEMq}, +{"VCVTTSD2SI_GPR64q_XMMq", XED_IFORM_VCVTTSD2SI_GPR64q_XMMq}, +{"VCVTTSD2USI_GPR32u32_MEMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512}, +{"VCVTTSD2USI_GPR32u32_XMMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512}, +{"VCVTTSD2USI_GPR64u64_MEMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512}, +{"VCVTTSD2USI_GPR64u64_XMMf64_AVX512", XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512}, +{"VCVTTSH2SI_GPR32i32_MEMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512}, +{"VCVTTSH2SI_GPR32i32_XMMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512}, +{"VCVTTSH2SI_GPR64i64_MEMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512}, +{"VCVTTSH2SI_GPR64i64_XMMf16_AVX512", XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512}, +{"VCVTTSH2USI_GPR32u32_MEMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512}, +{"VCVTTSH2USI_GPR32u32_XMMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512}, +{"VCVTTSH2USI_GPR64u64_MEMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512}, +{"VCVTTSH2USI_GPR64u64_XMMf16_AVX512", XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512}, +{"VCVTTSS2SI_GPR32d_MEMd", XED_IFORM_VCVTTSS2SI_GPR32d_MEMd}, +{"VCVTTSS2SI_GPR32d_XMMd", XED_IFORM_VCVTTSS2SI_GPR32d_XMMd}, +{"VCVTTSS2SI_GPR32i32_MEMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512}, +{"VCVTTSS2SI_GPR32i32_XMMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512}, +{"VCVTTSS2SI_GPR64i64_MEMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512}, +{"VCVTTSS2SI_GPR64i64_XMMf32_AVX512", XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512}, +{"VCVTTSS2SI_GPR64q_MEMd", XED_IFORM_VCVTTSS2SI_GPR64q_MEMd}, +{"VCVTTSS2SI_GPR64q_XMMd", XED_IFORM_VCVTTSS2SI_GPR64q_XMMd}, +{"VCVTTSS2USI_GPR32u32_MEMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512}, +{"VCVTTSS2USI_GPR32u32_XMMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512}, +{"VCVTTSS2USI_GPR64u64_MEMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512}, +{"VCVTTSS2USI_GPR64u64_XMMf32_AVX512", XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512}, +{"VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512}, +{"VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512}, +{"VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512", XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512}, +{"VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128}, +{"VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256}, +{"VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512}, +{"VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512", XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512}, +{"VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512}, +{"VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512", XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512}, +{"VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512", XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512}, +{"VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512", XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512}, +{"VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512}, +{"VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512", XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512}, +{"VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512", XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512}, +{"VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512", XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512}, +{"VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512", XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512}, +{"VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512", XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512}, +{"VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512}, +{"VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128}, +{"VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256}, +{"VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512}, +{"VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512}, +{"VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512}, +{"VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512}, +{"VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128}, +{"VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256}, +{"VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128}, +{"VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256}, +{"VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512}, +{"VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512}, +{"VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512}, +{"VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512}, +{"VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512}, +{"VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512", XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512}, +{"VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512}, +{"VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512}, +{"VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512}, +{"VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512", XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512}, +{"VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512}, +{"VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512}, +{"VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512}, +{"VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512", XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512}, +{"VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512", XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512}, +{"VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512", XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512}, +{"VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512", XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512}, +{"VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512", XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512}, +{"VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512", XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512}, +{"VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512}, +{"VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512", XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512}, +{"VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512", XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512}, +{"VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512", XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512}, +{"VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512", XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512}, +{"VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512", XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512}, +{"VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512", XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512}, +{"VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512}, +{"VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512}, +{"VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512}, +{"VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512}, +{"VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512}, +{"VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512}, +{"VDIVPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq}, +{"VDIVPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq}, +{"VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VDIVPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq}, +{"VDIVPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq}, +{"VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VDIVPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq}, +{"VDIVPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq}, +{"VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VDIVPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq}, +{"VDIVPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq}, +{"VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VDIVSD_XMMdq_XMMdq_MEMq", XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq}, +{"VDIVSD_XMMdq_XMMdq_XMMq", XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq}, +{"VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VDIVSS_XMMdq_XMMdq_MEMd", XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd}, +{"VDIVSS_XMMdq_XMMdq_XMMd", XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd}, +{"VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VDPPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VDPPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VDPPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb}, +{"VDPPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb}, +{"VDPPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb}, +{"VDPPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb}, +{"VERR_GPR16", XED_IFORM_VERR_GPR16}, +{"VERR_MEMw", XED_IFORM_VERR_MEMw}, +{"VERW_GPR16", XED_IFORM_VERW_GPR16}, +{"VERW_MEMw", XED_IFORM_VERW_MEMw}, +{"VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER", XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER}, +{"VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER", XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER}, +{"VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER", XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER}, +{"VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER", XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER}, +{"VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VEXTRACTF128_MEMdq_YMMdq_IMMb", XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb}, +{"VEXTRACTF128_XMMdq_YMMdq_IMMb", XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb}, +{"VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512}, +{"VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512}, +{"VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VEXTRACTI128_MEMdq_YMMqq_IMMb", XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb}, +{"VEXTRACTI128_XMMdq_YMMqq_IMMb", XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb}, +{"VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VEXTRACTPS_GPR32_XMMdq_IMMb", XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb}, +{"VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512}, +{"VEXTRACTPS_MEMd_XMMdq_IMMb", XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb}, +{"VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512", XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512}, +{"VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512}, +{"VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512}, +{"VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512}, +{"VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512}, +{"VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512}, +{"VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512}, +{"VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512}, +{"VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512}, +{"VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512}, +{"VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512}, +{"VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512}, +{"VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512}, +{"VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512}, +{"VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512}, +{"VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VFMADD132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq}, +{"VFMADD132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq}, +{"VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMADD132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq}, +{"VFMADD132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq}, +{"VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMADD132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq}, +{"VFMADD132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq}, +{"VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMADD132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq}, +{"VFMADD132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq}, +{"VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMADD132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq}, +{"VFMADD132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq}, +{"VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADD132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd}, +{"VFMADD132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd}, +{"VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADD213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq}, +{"VFMADD213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq}, +{"VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMADD213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq}, +{"VFMADD213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq}, +{"VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMADD213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq}, +{"VFMADD213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq}, +{"VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMADD213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq}, +{"VFMADD213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq}, +{"VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMADD213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq}, +{"VFMADD213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq}, +{"VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADD213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd}, +{"VFMADD213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd}, +{"VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADD231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq}, +{"VFMADD231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq}, +{"VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMADD231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq}, +{"VFMADD231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq}, +{"VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMADD231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq}, +{"VFMADD231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq}, +{"VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMADD231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq}, +{"VFMADD231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq}, +{"VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMADD231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq}, +{"VFMADD231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq}, +{"VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADD231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd}, +{"VFMADD231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd}, +{"VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512}, +{"VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512}, +{"VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512}, +{"VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512}, +{"VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMADDSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq}, +{"VFMADDSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq}, +{"VFMADDSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq}, +{"VFMADDSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd}, +{"VFMADDSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd}, +{"VFMADDSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd}, +{"VFMADDSUB132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUB132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMADDSUB132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUB132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMADDSUB132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUB132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMADDSUB132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUB132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMADDSUB213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUB213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMADDSUB213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUB213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMADDSUB213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUB213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMADDSUB213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUB213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMADDSUB231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUB231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMADDSUB231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUB231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMADDSUB231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUB231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMADDSUB231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUB231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMSUB132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq}, +{"VFMSUB132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq}, +{"VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMSUB132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq}, +{"VFMSUB132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq}, +{"VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMSUB132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq}, +{"VFMSUB132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq}, +{"VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMSUB132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq}, +{"VFMSUB132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq}, +{"VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMSUB132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq}, +{"VFMSUB132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq}, +{"VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUB132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd}, +{"VFMSUB132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd}, +{"VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUB213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq}, +{"VFMSUB213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq}, +{"VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMSUB213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq}, +{"VFMSUB213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq}, +{"VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMSUB213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq}, +{"VFMSUB213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq}, +{"VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMSUB213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq}, +{"VFMSUB213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq}, +{"VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMSUB213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq}, +{"VFMSUB213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq}, +{"VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUB213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd}, +{"VFMSUB213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd}, +{"VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUB231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq}, +{"VFMSUB231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq}, +{"VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMSUB231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq}, +{"VFMSUB231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq}, +{"VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMSUB231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq}, +{"VFMSUB231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq}, +{"VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMSUB231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq}, +{"VFMSUB231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq}, +{"VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMSUB231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq}, +{"VFMSUB231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq}, +{"VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUB231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd}, +{"VFMSUB231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd}, +{"VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUBADD132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADD132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMSUBADD132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADD132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMSUBADD132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADD132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMSUBADD132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADD132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMSUBADD213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADD213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMSUBADD213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADD213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMSUBADD213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADD213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMSUBADD213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADD213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMSUBADD231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADD231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFMSUBADD231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADD231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFMSUBADD231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADD231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFMSUBADD231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADD231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFMSUBSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq}, +{"VFMSUBSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq}, +{"VFMSUBSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq}, +{"VFMSUBSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd}, +{"VFMSUBSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd}, +{"VFMSUBSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd}, +{"VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512}, +{"VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512", XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512}, +{"VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512}, +{"VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512", XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512}, +{"VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512", XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512}, +{"VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512", XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512}, +{"VFNMADD132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq}, +{"VFNMADD132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq}, +{"VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFNMADD132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq}, +{"VFNMADD132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq}, +{"VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFNMADD132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq}, +{"VFNMADD132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq}, +{"VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFNMADD132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq}, +{"VFNMADD132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq}, +{"VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFNMADD132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq}, +{"VFNMADD132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq}, +{"VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMADD132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd}, +{"VFNMADD132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd}, +{"VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMADD213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq}, +{"VFNMADD213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq}, +{"VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFNMADD213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq}, +{"VFNMADD213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq}, +{"VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFNMADD213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq}, +{"VFNMADD213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq}, +{"VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFNMADD213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq}, +{"VFNMADD213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq}, +{"VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFNMADD213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq}, +{"VFNMADD213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq}, +{"VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMADD213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd}, +{"VFNMADD213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd}, +{"VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMADD231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq}, +{"VFNMADD231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq}, +{"VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFNMADD231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq}, +{"VFNMADD231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq}, +{"VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFNMADD231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq}, +{"VFNMADD231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq}, +{"VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFNMADD231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq}, +{"VFNMADD231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq}, +{"VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFNMADD231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq}, +{"VFNMADD231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq}, +{"VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMADD231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd}, +{"VFNMADD231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd}, +{"VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFNMADDSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq}, +{"VFNMADDSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq}, +{"VFNMADDSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq}, +{"VFNMADDSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd}, +{"VFNMADDSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd}, +{"VFNMADDSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd}, +{"VFNMSUB132PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq}, +{"VFNMSUB132PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq}, +{"VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFNMSUB132PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq}, +{"VFNMSUB132PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq}, +{"VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFNMSUB132PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq}, +{"VFNMSUB132PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq}, +{"VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFNMSUB132PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq}, +{"VFNMSUB132PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq}, +{"VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFNMSUB132SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq}, +{"VFNMSUB132SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq}, +{"VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMSUB132SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd}, +{"VFNMSUB132SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd}, +{"VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMSUB213PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq}, +{"VFNMSUB213PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq}, +{"VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFNMSUB213PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq}, +{"VFNMSUB213PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq}, +{"VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFNMSUB213PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq}, +{"VFNMSUB213PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq}, +{"VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFNMSUB213PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq}, +{"VFNMSUB213PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq}, +{"VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFNMSUB213SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq}, +{"VFNMSUB213SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq}, +{"VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMSUB213SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd}, +{"VFNMSUB213SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd}, +{"VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMSUB231PD_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq}, +{"VFNMSUB231PD_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq}, +{"VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VFNMSUB231PD_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq}, +{"VFNMSUB231PD_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq}, +{"VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VFNMSUB231PS_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq}, +{"VFNMSUB231PS_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq}, +{"VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VFNMSUB231PS_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq}, +{"VFNMSUB231PS_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq}, +{"VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VFNMSUB231SD_XMMdq_XMMq_MEMq", XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq}, +{"VFNMSUB231SD_XMMdq_XMMq_XMMq", XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq}, +{"VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VFNMSUB231SS_XMMdq_XMMd_MEMd", XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd}, +{"VFNMSUB231SS_XMMdq_XMMd_XMMd", XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd}, +{"VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq", XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq}, +{"VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq", XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq}, +{"VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq", XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq}, +{"VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd", XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd}, +{"VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd", XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd}, +{"VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd", XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd}, +{"VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128}, +{"VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256}, +{"VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512}, +{"VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512}, +{"VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512}, +{"VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128}, +{"VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256}, +{"VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512}, +{"VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512}, +{"VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512}, +{"VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512}, +{"VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128}, +{"VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256}, +{"VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512}, +{"VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512}, +{"VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512}, +{"VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512}, +{"VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512}, +{"VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512}, +{"VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512}, +{"VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512}, +{"VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512}, +{"VFRCZPD_XMMdq_MEMdq", XED_IFORM_VFRCZPD_XMMdq_MEMdq}, +{"VFRCZPD_XMMdq_XMMdq", XED_IFORM_VFRCZPD_XMMdq_XMMdq}, +{"VFRCZPD_YMMqq_MEMqq", XED_IFORM_VFRCZPD_YMMqq_MEMqq}, +{"VFRCZPD_YMMqq_YMMqq", XED_IFORM_VFRCZPD_YMMqq_YMMqq}, +{"VFRCZPS_XMMdq_MEMdq", XED_IFORM_VFRCZPS_XMMdq_MEMdq}, +{"VFRCZPS_XMMdq_XMMdq", XED_IFORM_VFRCZPS_XMMdq_XMMdq}, +{"VFRCZPS_YMMqq_MEMqq", XED_IFORM_VFRCZPS_YMMqq_MEMqq}, +{"VFRCZPS_YMMqq_YMMqq", XED_IFORM_VFRCZPS_YMMqq_YMMqq}, +{"VFRCZSD_XMMdq_MEMq", XED_IFORM_VFRCZSD_XMMdq_MEMq}, +{"VFRCZSD_XMMdq_XMMq", XED_IFORM_VFRCZSD_XMMdq_XMMq}, +{"VFRCZSS_XMMdq_MEMd", XED_IFORM_VFRCZSS_XMMdq_MEMd}, +{"VFRCZSS_XMMdq_XMMd", XED_IFORM_VFRCZSS_XMMdq_XMMd}, +{"VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128}, +{"VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128", XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128}, +{"VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256}, +{"VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256", XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256}, +{"VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512}, +{"VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128}, +{"VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128", XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128}, +{"VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256}, +{"VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256", XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256}, +{"VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512}, +{"VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128", XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128}, +{"VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128", XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128}, +{"VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256", XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256}, +{"VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256", XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256}, +{"VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512", XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512}, +{"VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128", XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128}, +{"VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256", XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256}, +{"VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128", XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128}, +{"VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256", XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256}, +{"VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512", XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512}, +{"VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512}, +{"VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512}, +{"VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512}, +{"VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512}, +{"VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512}, +{"VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512}, +{"VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512}, +{"VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512}, +{"VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512}, +{"VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512}, +{"VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512}, +{"VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512}, +{"VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512}, +{"VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512}, +{"VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512}, +{"VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512}, +{"VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8}, +{"VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8}, +{"VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512}, +{"VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512}, +{"VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8}, +{"VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8", XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8}, +{"VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512}, +{"VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512}, +{"VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512}, +{"VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512}, +{"VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8}, +{"VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8}, +{"VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512}, +{"VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512}, +{"VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8}, +{"VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8", XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8}, +{"VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512}, +{"VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512", XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512}, +{"VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VGF2P8MULB_XMMu8_XMMu8_MEMu8", XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8}, +{"VGF2P8MULB_XMMu8_XMMu8_XMMu8", XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8}, +{"VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VGF2P8MULB_YMMu8_YMMu8_MEMu8", XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8}, +{"VGF2P8MULB_YMMu8_YMMu8_YMMu8", XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8}, +{"VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VHADDPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq}, +{"VHADDPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq}, +{"VHADDPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq}, +{"VHADDPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq}, +{"VHADDPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq}, +{"VHADDPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq}, +{"VHADDPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq}, +{"VHADDPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq}, +{"VHSUBPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq}, +{"VHSUBPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq}, +{"VHSUBPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq}, +{"VHSUBPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq}, +{"VHSUBPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq}, +{"VHSUBPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq}, +{"VHSUBPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq}, +{"VHSUBPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq}, +{"VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb", XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb}, +{"VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb", XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb}, +{"VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512}, +{"VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512}, +{"VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512}, +{"VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512}, +{"VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512}, +{"VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512}, +{"VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512}, +{"VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512}, +{"VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb", XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb}, +{"VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb", XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb}, +{"VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512}, +{"VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512}, +{"VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512}, +{"VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512}, +{"VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512}, +{"VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512}, +{"VINSERTPS_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb}, +{"VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb}, +{"VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512}, +{"VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512}, +{"VLDDQU_XMMdq_MEMdq", XED_IFORM_VLDDQU_XMMdq_MEMdq}, +{"VLDDQU_YMMqq_MEMqq", XED_IFORM_VLDDQU_YMMqq_MEMqq}, +{"VLDMXCSR_MEMd", XED_IFORM_VLDMXCSR_MEMd}, +{"VMASKMOVDQU_XMMdq_XMMdq", XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq}, +{"VMASKMOVPD_MEMdq_XMMdq_XMMdq", XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq}, +{"VMASKMOVPD_MEMqq_YMMqq_YMMqq", XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq}, +{"VMASKMOVPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq}, +{"VMASKMOVPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq}, +{"VMASKMOVPS_MEMdq_XMMdq_XMMdq", XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq}, +{"VMASKMOVPS_MEMqq_YMMqq_YMMqq", XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq}, +{"VMASKMOVPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq}, +{"VMASKMOVPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq}, +{"VMAXPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq}, +{"VMAXPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq}, +{"VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VMAXPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq}, +{"VMAXPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq}, +{"VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VMAXPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq}, +{"VMAXPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq}, +{"VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VMAXPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq}, +{"VMAXPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq}, +{"VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VMAXSD_XMMdq_XMMdq_MEMq", XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq}, +{"VMAXSD_XMMdq_XMMdq_XMMq", XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq}, +{"VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMAXSS_XMMdq_XMMdq_MEMd", XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd}, +{"VMAXSS_XMMdq_XMMdq_XMMd", XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd}, +{"VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMCALL", XED_IFORM_VMCALL}, +{"VMCLEAR_MEMq", XED_IFORM_VMCLEAR_MEMq}, +{"VMFUNC", XED_IFORM_VMFUNC}, +{"VMINPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq}, +{"VMINPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq}, +{"VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VMINPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq}, +{"VMINPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq}, +{"VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VMINPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq}, +{"VMINPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq}, +{"VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VMINPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq}, +{"VMINPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq}, +{"VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VMINSD_XMMdq_XMMdq_MEMq", XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq}, +{"VMINSD_XMMdq_XMMdq_XMMq", XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq}, +{"VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMINSS_XMMdq_XMMdq_MEMd", XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd}, +{"VMINSS_XMMdq_XMMdq_XMMd", XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd}, +{"VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMLAUNCH", XED_IFORM_VMLAUNCH}, +{"VMLOAD_ArAX", XED_IFORM_VMLOAD_ArAX}, +{"VMMCALL", XED_IFORM_VMMCALL}, +{"VMOVAPD_MEMdq_XMMdq", XED_IFORM_VMOVAPD_MEMdq_XMMdq}, +{"VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512}, +{"VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512}, +{"VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512}, +{"VMOVAPD_MEMqq_YMMqq", XED_IFORM_VMOVAPD_MEMqq_YMMqq}, +{"VMOVAPD_XMMdq_MEMdq", XED_IFORM_VMOVAPD_XMMdq_MEMdq}, +{"VMOVAPD_XMMdq_XMMdq_28", XED_IFORM_VMOVAPD_XMMdq_XMMdq_28}, +{"VMOVAPD_XMMdq_XMMdq_29", XED_IFORM_VMOVAPD_XMMdq_XMMdq_29}, +{"VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VMOVAPD_YMMqq_MEMqq", XED_IFORM_VMOVAPD_YMMqq_MEMqq}, +{"VMOVAPD_YMMqq_YMMqq_28", XED_IFORM_VMOVAPD_YMMqq_YMMqq_28}, +{"VMOVAPD_YMMqq_YMMqq_29", XED_IFORM_VMOVAPD_YMMqq_YMMqq_29}, +{"VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VMOVAPS_MEMdq_XMMdq", XED_IFORM_VMOVAPS_MEMdq_XMMdq}, +{"VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512}, +{"VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512}, +{"VMOVAPS_MEMqq_YMMqq", XED_IFORM_VMOVAPS_MEMqq_YMMqq}, +{"VMOVAPS_XMMdq_MEMdq", XED_IFORM_VMOVAPS_XMMdq_MEMdq}, +{"VMOVAPS_XMMdq_XMMdq_28", XED_IFORM_VMOVAPS_XMMdq_XMMdq_28}, +{"VMOVAPS_XMMdq_XMMdq_29", XED_IFORM_VMOVAPS_XMMdq_XMMdq_29}, +{"VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VMOVAPS_YMMqq_MEMqq", XED_IFORM_VMOVAPS_YMMqq_MEMqq}, +{"VMOVAPS_YMMqq_YMMqq_28", XED_IFORM_VMOVAPS_YMMqq_YMMqq_28}, +{"VMOVAPS_YMMqq_YMMqq_29", XED_IFORM_VMOVAPS_YMMqq_YMMqq_29}, +{"VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VMOVD_GPR32d_XMMd", XED_IFORM_VMOVD_GPR32d_XMMd}, +{"VMOVD_GPR32u32_XMMu32_AVX512", XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512}, +{"VMOVD_MEMd_XMMd", XED_IFORM_VMOVD_MEMd_XMMd}, +{"VMOVD_MEMu32_XMMu32_AVX512", XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512}, +{"VMOVD_XMMdq_GPR32d", XED_IFORM_VMOVD_XMMdq_GPR32d}, +{"VMOVD_XMMdq_MEMd", XED_IFORM_VMOVD_XMMdq_MEMd}, +{"VMOVD_XMMu32_GPR32u32_AVX512", XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512}, +{"VMOVD_XMMu32_MEMu32_AVX512", XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512}, +{"VMOVDDUP_XMMdq_MEMq", XED_IFORM_VMOVDDUP_XMMdq_MEMq}, +{"VMOVDDUP_XMMdq_XMMq", XED_IFORM_VMOVDDUP_XMMdq_XMMq}, +{"VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VMOVDDUP_YMMqq_MEMqq", XED_IFORM_VMOVDDUP_YMMqq_MEMqq}, +{"VMOVDDUP_YMMqq_YMMqq", XED_IFORM_VMOVDDUP_YMMqq_YMMqq}, +{"VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VMOVDQA_MEMdq_XMMdq", XED_IFORM_VMOVDQA_MEMdq_XMMdq}, +{"VMOVDQA_MEMqq_YMMqq", XED_IFORM_VMOVDQA_MEMqq_YMMqq}, +{"VMOVDQA_XMMdq_MEMdq", XED_IFORM_VMOVDQA_XMMdq_MEMdq}, +{"VMOVDQA_XMMdq_XMMdq_6F", XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F}, +{"VMOVDQA_XMMdq_XMMdq_7F", XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F}, +{"VMOVDQA_YMMqq_MEMqq", XED_IFORM_VMOVDQA_YMMqq_MEMqq}, +{"VMOVDQA_YMMqq_YMMqq_6F", XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F}, +{"VMOVDQA_YMMqq_YMMqq_7F", XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F}, +{"VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512}, +{"VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512}, +{"VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512}, +{"VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512}, +{"VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512}, +{"VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512}, +{"VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512}, +{"VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512}, +{"VMOVDQU_MEMdq_XMMdq", XED_IFORM_VMOVDQU_MEMdq_XMMdq}, +{"VMOVDQU_MEMqq_YMMqq", XED_IFORM_VMOVDQU_MEMqq_YMMqq}, +{"VMOVDQU_XMMdq_MEMdq", XED_IFORM_VMOVDQU_XMMdq_MEMdq}, +{"VMOVDQU_XMMdq_XMMdq_6F", XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F}, +{"VMOVDQU_XMMdq_XMMdq_7F", XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F}, +{"VMOVDQU_YMMqq_MEMqq", XED_IFORM_VMOVDQU_YMMqq_MEMqq}, +{"VMOVDQU_YMMqq_YMMqq_6F", XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F}, +{"VMOVDQU_YMMqq_YMMqq_7F", XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F}, +{"VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512}, +{"VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512}, +{"VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512}, +{"VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512}, +{"VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512}, +{"VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512}, +{"VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512}, +{"VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512}, +{"VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512}, +{"VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512}, +{"VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512}, +{"VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512}, +{"VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512}, +{"VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512}, +{"VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512}, +{"VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512}, +{"VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512}, +{"VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512}, +{"VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512}, +{"VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512}, +{"VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512}, +{"VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512}, +{"VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512}, +{"VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512}, +{"VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512}, +{"VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512}, +{"VMOVHLPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq}, +{"VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512", XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512}, +{"VMOVHPD_MEMf64_XMMf64_AVX512", XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512}, +{"VMOVHPD_MEMq_XMMdq", XED_IFORM_VMOVHPD_MEMq_XMMdq}, +{"VMOVHPD_XMMdq_XMMq_MEMq", XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq}, +{"VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512", XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512}, +{"VMOVHPS_MEMf32_XMMf32_AVX512", XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512}, +{"VMOVHPS_MEMq_XMMdq", XED_IFORM_VMOVHPS_MEMq_XMMdq}, +{"VMOVHPS_XMMdq_XMMq_MEMq", XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq}, +{"VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512", XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512}, +{"VMOVLHPS_XMMdq_XMMq_XMMq", XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq}, +{"VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512", XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512}, +{"VMOVLPD_MEMf64_XMMf64_AVX512", XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512}, +{"VMOVLPD_MEMq_XMMq", XED_IFORM_VMOVLPD_MEMq_XMMq}, +{"VMOVLPD_XMMdq_XMMdq_MEMq", XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq}, +{"VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512", XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512}, +{"VMOVLPS_MEMf32_XMMf32_AVX512", XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512}, +{"VMOVLPS_MEMq_XMMq", XED_IFORM_VMOVLPS_MEMq_XMMq}, +{"VMOVLPS_XMMdq_XMMdq_MEMq", XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq}, +{"VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512", XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512}, +{"VMOVMSKPD_GPR32d_XMMdq", XED_IFORM_VMOVMSKPD_GPR32d_XMMdq}, +{"VMOVMSKPD_GPR32d_YMMqq", XED_IFORM_VMOVMSKPD_GPR32d_YMMqq}, +{"VMOVMSKPS_GPR32d_XMMdq", XED_IFORM_VMOVMSKPS_GPR32d_XMMdq}, +{"VMOVMSKPS_GPR32d_YMMqq", XED_IFORM_VMOVMSKPS_GPR32d_YMMqq}, +{"VMOVNTDQ_MEMdq_XMMdq", XED_IFORM_VMOVNTDQ_MEMdq_XMMdq}, +{"VMOVNTDQ_MEMqq_YMMqq", XED_IFORM_VMOVNTDQ_MEMqq_YMMqq}, +{"VMOVNTDQ_MEMu32_XMMu32_AVX512", XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512}, +{"VMOVNTDQ_MEMu32_YMMu32_AVX512", XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512}, +{"VMOVNTDQ_MEMu32_ZMMu32_AVX512", XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512}, +{"VMOVNTDQA_XMMdq_MEMdq", XED_IFORM_VMOVNTDQA_XMMdq_MEMdq}, +{"VMOVNTDQA_XMMu32_MEMu32_AVX512", XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512}, +{"VMOVNTDQA_YMMqq_MEMqq", XED_IFORM_VMOVNTDQA_YMMqq_MEMqq}, +{"VMOVNTDQA_YMMu32_MEMu32_AVX512", XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512}, +{"VMOVNTDQA_ZMMu32_MEMu32_AVX512", XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512}, +{"VMOVNTPD_MEMdq_XMMdq", XED_IFORM_VMOVNTPD_MEMdq_XMMdq}, +{"VMOVNTPD_MEMf64_XMMf64_AVX512", XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512}, +{"VMOVNTPD_MEMf64_YMMf64_AVX512", XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512}, +{"VMOVNTPD_MEMf64_ZMMf64_AVX512", XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512}, +{"VMOVNTPD_MEMqq_YMMqq", XED_IFORM_VMOVNTPD_MEMqq_YMMqq}, +{"VMOVNTPS_MEMdq_XMMdq", XED_IFORM_VMOVNTPS_MEMdq_XMMdq}, +{"VMOVNTPS_MEMf32_XMMf32_AVX512", XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512}, +{"VMOVNTPS_MEMf32_YMMf32_AVX512", XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512}, +{"VMOVNTPS_MEMf32_ZMMf32_AVX512", XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512}, +{"VMOVNTPS_MEMqq_YMMqq", XED_IFORM_VMOVNTPS_MEMqq_YMMqq}, +{"VMOVQ_GPR64q_XMMq", XED_IFORM_VMOVQ_GPR64q_XMMq}, +{"VMOVQ_GPR64u64_XMMu64_AVX512", XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512}, +{"VMOVQ_MEMq_XMMq_7E", XED_IFORM_VMOVQ_MEMq_XMMq_7E}, +{"VMOVQ_MEMq_XMMq_D6", XED_IFORM_VMOVQ_MEMq_XMMq_D6}, +{"VMOVQ_MEMu64_XMMu64_AVX512", XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512}, +{"VMOVQ_XMMdq_GPR64q", XED_IFORM_VMOVQ_XMMdq_GPR64q}, +{"VMOVQ_XMMdq_MEMq_6E", XED_IFORM_VMOVQ_XMMdq_MEMq_6E}, +{"VMOVQ_XMMdq_MEMq_7E", XED_IFORM_VMOVQ_XMMdq_MEMq_7E}, +{"VMOVQ_XMMdq_XMMq_7E", XED_IFORM_VMOVQ_XMMdq_XMMq_7E}, +{"VMOVQ_XMMdq_XMMq_D6", XED_IFORM_VMOVQ_XMMdq_XMMq_D6}, +{"VMOVQ_XMMu64_GPR64u64_AVX512", XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512}, +{"VMOVQ_XMMu64_MEMu64_AVX512", XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512}, +{"VMOVQ_XMMu64_XMMu64_AVX512", XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512}, +{"VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512}, +{"VMOVSD_MEMq_XMMq", XED_IFORM_VMOVSD_MEMq_XMMq}, +{"VMOVSD_XMMdq_MEMq", XED_IFORM_VMOVSD_XMMdq_MEMq}, +{"VMOVSD_XMMdq_XMMdq_XMMq_10", XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10}, +{"VMOVSD_XMMdq_XMMdq_XMMq_11", XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11}, +{"VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512}, +{"VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512}, +{"VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMOVSHDUP_XMMdq_MEMdq", XED_IFORM_VMOVSHDUP_XMMdq_MEMdq}, +{"VMOVSHDUP_XMMdq_XMMdq", XED_IFORM_VMOVSHDUP_XMMdq_XMMdq}, +{"VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VMOVSHDUP_YMMqq_MEMqq", XED_IFORM_VMOVSHDUP_YMMqq_MEMqq}, +{"VMOVSHDUP_YMMqq_YMMqq", XED_IFORM_VMOVSHDUP_YMMqq_YMMqq}, +{"VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VMOVSLDUP_XMMdq_MEMdq", XED_IFORM_VMOVSLDUP_XMMdq_MEMdq}, +{"VMOVSLDUP_XMMdq_XMMdq", XED_IFORM_VMOVSLDUP_XMMdq_XMMdq}, +{"VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VMOVSLDUP_YMMqq_MEMqq", XED_IFORM_VMOVSLDUP_YMMqq_MEMqq}, +{"VMOVSLDUP_YMMqq_YMMqq", XED_IFORM_VMOVSLDUP_YMMqq_YMMqq}, +{"VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VMOVSS_MEMd_XMMd", XED_IFORM_VMOVSS_MEMd_XMMd}, +{"VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVSS_XMMdq_MEMd", XED_IFORM_VMOVSS_XMMdq_MEMd}, +{"VMOVSS_XMMdq_XMMdq_XMMd_10", XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10}, +{"VMOVSS_XMMdq_XMMdq_XMMd_11", XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11}, +{"VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMOVUPD_MEMdq_XMMdq", XED_IFORM_VMOVUPD_MEMdq_XMMdq}, +{"VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512}, +{"VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512}, +{"VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512}, +{"VMOVUPD_MEMqq_YMMqq", XED_IFORM_VMOVUPD_MEMqq_YMMqq}, +{"VMOVUPD_XMMdq_MEMdq", XED_IFORM_VMOVUPD_XMMdq_MEMdq}, +{"VMOVUPD_XMMdq_XMMdq_10", XED_IFORM_VMOVUPD_XMMdq_XMMdq_10}, +{"VMOVUPD_XMMdq_XMMdq_11", XED_IFORM_VMOVUPD_XMMdq_XMMdq_11}, +{"VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VMOVUPD_YMMqq_MEMqq", XED_IFORM_VMOVUPD_YMMqq_MEMqq}, +{"VMOVUPD_YMMqq_YMMqq_10", XED_IFORM_VMOVUPD_YMMqq_YMMqq_10}, +{"VMOVUPD_YMMqq_YMMqq_11", XED_IFORM_VMOVUPD_YMMqq_YMMqq_11}, +{"VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VMOVUPS_MEMdq_XMMdq", XED_IFORM_VMOVUPS_MEMdq_XMMdq}, +{"VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512}, +{"VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512}, +{"VMOVUPS_MEMqq_YMMqq", XED_IFORM_VMOVUPS_MEMqq_YMMqq}, +{"VMOVUPS_XMMdq_MEMdq", XED_IFORM_VMOVUPS_XMMdq_MEMdq}, +{"VMOVUPS_XMMdq_XMMdq_10", XED_IFORM_VMOVUPS_XMMdq_XMMdq_10}, +{"VMOVUPS_XMMdq_XMMdq_11", XED_IFORM_VMOVUPS_XMMdq_XMMdq_11}, +{"VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VMOVUPS_YMMqq_MEMqq", XED_IFORM_VMOVUPS_YMMqq_MEMqq}, +{"VMOVUPS_YMMqq_YMMqq_10", XED_IFORM_VMOVUPS_YMMqq_YMMqq_10}, +{"VMOVUPS_YMMqq_YMMqq_11", XED_IFORM_VMOVUPS_YMMqq_YMMqq_11}, +{"VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VMOVW_GPR32f16_XMMf16_AVX512", XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512}, +{"VMOVW_MEMf16_XMMf16_AVX512", XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512}, +{"VMOVW_XMMf16_GPR32f16_AVX512", XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512}, +{"VMOVW_XMMf16_MEMf16_AVX512", XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512}, +{"VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb}, +{"VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb}, +{"VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb}, +{"VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb}, +{"VMPTRLD_MEMq", XED_IFORM_VMPTRLD_MEMq}, +{"VMPTRST_MEMq", XED_IFORM_VMPTRST_MEMq}, +{"VMREAD_GPR32_GPR32", XED_IFORM_VMREAD_GPR32_GPR32}, +{"VMREAD_GPR64_GPR64", XED_IFORM_VMREAD_GPR64_GPR64}, +{"VMREAD_MEMd_GPR32", XED_IFORM_VMREAD_MEMd_GPR32}, +{"VMREAD_MEMq_GPR64", XED_IFORM_VMREAD_MEMq_GPR64}, +{"VMRESUME", XED_IFORM_VMRESUME}, +{"VMRUN_ArAX", XED_IFORM_VMRUN_ArAX}, +{"VMSAVE", XED_IFORM_VMSAVE}, +{"VMULPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq}, +{"VMULPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq}, +{"VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VMULPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq}, +{"VMULPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq}, +{"VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VMULPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq}, +{"VMULPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq}, +{"VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VMULPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq}, +{"VMULPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq}, +{"VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VMULSD_XMMdq_XMMdq_MEMq", XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq}, +{"VMULSD_XMMdq_XMMdq_XMMq", XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq}, +{"VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VMULSS_XMMdq_XMMdq_MEMd", XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd}, +{"VMULSS_XMMdq_XMMdq_XMMd", XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd}, +{"VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VMWRITE_GPR32_GPR32", XED_IFORM_VMWRITE_GPR32_GPR32}, +{"VMWRITE_GPR32_MEMd", XED_IFORM_VMWRITE_GPR32_MEMd}, +{"VMWRITE_GPR64_GPR64", XED_IFORM_VMWRITE_GPR64_GPR64}, +{"VMWRITE_GPR64_MEMq", XED_IFORM_VMWRITE_GPR64_MEMq}, +{"VMXOFF", XED_IFORM_VMXOFF}, +{"VMXON_MEMq", XED_IFORM_VMXON_MEMq}, +{"VORPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq}, +{"VORPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq}, +{"VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VORPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq}, +{"VORPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq}, +{"VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VORPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq}, +{"VORPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq}, +{"VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VORPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq}, +{"VORPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq}, +{"VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512}, +{"VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512}, +{"VPABSB_XMMdq_MEMdq", XED_IFORM_VPABSB_XMMdq_MEMdq}, +{"VPABSB_XMMdq_XMMdq", XED_IFORM_VPABSB_XMMdq_XMMdq}, +{"VPABSB_XMMi8_MASKmskw_MEMi8_AVX512", XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512}, +{"VPABSB_XMMi8_MASKmskw_XMMi8_AVX512", XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512}, +{"VPABSB_YMMi8_MASKmskw_MEMi8_AVX512", XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512}, +{"VPABSB_YMMi8_MASKmskw_YMMi8_AVX512", XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512}, +{"VPABSB_YMMqq_MEMqq", XED_IFORM_VPABSB_YMMqq_MEMqq}, +{"VPABSB_YMMqq_YMMqq", XED_IFORM_VPABSB_YMMqq_YMMqq}, +{"VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512", XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512}, +{"VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512", XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512}, +{"VPABSD_XMMdq_MEMdq", XED_IFORM_VPABSD_XMMdq_MEMdq}, +{"VPABSD_XMMdq_XMMdq", XED_IFORM_VPABSD_XMMdq_XMMdq}, +{"VPABSD_XMMi32_MASKmskw_MEMi32_AVX512", XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512}, +{"VPABSD_XMMi32_MASKmskw_XMMi32_AVX512", XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512}, +{"VPABSD_YMMi32_MASKmskw_MEMi32_AVX512", XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512}, +{"VPABSD_YMMi32_MASKmskw_YMMi32_AVX512", XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512}, +{"VPABSD_YMMqq_MEMqq", XED_IFORM_VPABSD_YMMqq_MEMqq}, +{"VPABSD_YMMqq_YMMqq", XED_IFORM_VPABSD_YMMqq_YMMqq}, +{"VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512", XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512}, +{"VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512}, +{"VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512", XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512}, +{"VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512", XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512}, +{"VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512", XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512}, +{"VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512", XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512}, +{"VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512", XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512}, +{"VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512}, +{"VPABSW_XMMdq_MEMdq", XED_IFORM_VPABSW_XMMdq_MEMdq}, +{"VPABSW_XMMdq_XMMdq", XED_IFORM_VPABSW_XMMdq_XMMdq}, +{"VPABSW_XMMi16_MASKmskw_MEMi16_AVX512", XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512}, +{"VPABSW_XMMi16_MASKmskw_XMMi16_AVX512", XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512}, +{"VPABSW_YMMi16_MASKmskw_MEMi16_AVX512", XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512}, +{"VPABSW_YMMi16_MASKmskw_YMMi16_AVX512", XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512}, +{"VPABSW_YMMqq_MEMqq", XED_IFORM_VPABSW_YMMqq_MEMqq}, +{"VPABSW_YMMqq_YMMqq", XED_IFORM_VPABSW_YMMqq_YMMqq}, +{"VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512", XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512}, +{"VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512", XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512}, +{"VPACKSSDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq}, +{"VPACKSSDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq}, +{"VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512}, +{"VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512}, +{"VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512}, +{"VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512}, +{"VPACKSSDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq}, +{"VPACKSSDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq}, +{"VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512}, +{"VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512}, +{"VPACKSSWB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq}, +{"VPACKSSWB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq}, +{"VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPACKSSWB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq}, +{"VPACKSSWB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq}, +{"VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPACKUSDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq}, +{"VPACKUSDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq}, +{"VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPACKUSDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq}, +{"VPACKUSDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq}, +{"VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPACKUSWB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq}, +{"VPACKUSWB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq}, +{"VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPACKUSWB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq}, +{"VPACKUSWB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq}, +{"VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPADDB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq}, +{"VPADDB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq}, +{"VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPADDB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq}, +{"VPADDB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq}, +{"VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPADDD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq}, +{"VPADDD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq}, +{"VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPADDD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq}, +{"VPADDD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq}, +{"VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPADDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq}, +{"VPADDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq}, +{"VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPADDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq}, +{"VPADDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq}, +{"VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPADDSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq}, +{"VPADDSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq}, +{"VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512}, +{"VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512}, +{"VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512}, +{"VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512}, +{"VPADDSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq}, +{"VPADDSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq}, +{"VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512}, +{"VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512}, +{"VPADDSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq}, +{"VPADDSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq}, +{"VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPADDSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq}, +{"VPADDSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq}, +{"VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPADDUSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq}, +{"VPADDUSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq}, +{"VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPADDUSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq}, +{"VPADDUSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq}, +{"VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPADDUSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq}, +{"VPADDUSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq}, +{"VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPADDUSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq}, +{"VPADDUSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq}, +{"VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPADDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq}, +{"VPADDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq}, +{"VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPADDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq}, +{"VPADDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq}, +{"VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512}, +{"VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512}, +{"VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512}, +{"VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512}, +{"VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512}, +{"VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512}, +{"VPAND_XMMdq_XMMdq_MEMdq", XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq}, +{"VPAND_XMMdq_XMMdq_XMMdq", XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq}, +{"VPAND_YMMqq_YMMqq_MEMqq", XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq}, +{"VPAND_YMMqq_YMMqq_YMMqq", XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq}, +{"VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPANDN_XMMdq_XMMdq_MEMdq", XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq}, +{"VPANDN_XMMdq_XMMdq_XMMdq", XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq}, +{"VPANDN_YMMqq_YMMqq_MEMqq", XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq}, +{"VPANDN_YMMqq_YMMqq_YMMqq", XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq}, +{"VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPAVGB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq}, +{"VPAVGB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq}, +{"VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPAVGB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq}, +{"VPAVGB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq}, +{"VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPAVGW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq}, +{"VPAVGW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq}, +{"VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPAVGW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq}, +{"VPAVGW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq}, +{"VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPBROADCASTB_XMMdq_MEMb", XED_IFORM_VPBROADCASTB_XMMdq_MEMb}, +{"VPBROADCASTB_XMMdq_XMMb", XED_IFORM_VPBROADCASTB_XMMdq_XMMb}, +{"VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512", XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512}, +{"VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512}, +{"VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512}, +{"VPBROADCASTB_YMMqq_MEMb", XED_IFORM_VPBROADCASTB_YMMqq_MEMb}, +{"VPBROADCASTB_YMMqq_XMMb", XED_IFORM_VPBROADCASTB_YMMqq_XMMb}, +{"VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512", XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512}, +{"VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512}, +{"VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512}, +{"VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512", XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512}, +{"VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512}, +{"VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512}, +{"VPBROADCASTD_XMMdq_MEMd", XED_IFORM_VPBROADCASTD_XMMdq_MEMd}, +{"VPBROADCASTD_XMMdq_XMMd", XED_IFORM_VPBROADCASTD_XMMdq_XMMd}, +{"VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512", XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512}, +{"VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VPBROADCASTD_YMMqq_MEMd", XED_IFORM_VPBROADCASTD_YMMqq_MEMd}, +{"VPBROADCASTD_YMMqq_XMMd", XED_IFORM_VPBROADCASTD_YMMqq_XMMd}, +{"VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512", XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512}, +{"VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512}, +{"VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512", XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512}, +{"VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512}, +{"VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512", XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512}, +{"VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512", XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512}, +{"VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD", XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD}, +{"VPBROADCASTMW2D_XMMu32_MASKu32_AVX512", XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512}, +{"VPBROADCASTMW2D_YMMu32_MASKu32_AVX512", XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512}, +{"VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD", XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD}, +{"VPBROADCASTQ_XMMdq_MEMq", XED_IFORM_VPBROADCASTQ_XMMdq_MEMq}, +{"VPBROADCASTQ_XMMdq_XMMq", XED_IFORM_VPBROADCASTQ_XMMdq_XMMq}, +{"VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512", XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512}, +{"VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VPBROADCASTQ_YMMqq_MEMq", XED_IFORM_VPBROADCASTQ_YMMqq_MEMq}, +{"VPBROADCASTQ_YMMqq_XMMq", XED_IFORM_VPBROADCASTQ_YMMqq_XMMq}, +{"VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512", XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512}, +{"VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512}, +{"VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512", XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512}, +{"VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512}, +{"VPBROADCASTW_XMMdq_MEMw", XED_IFORM_VPBROADCASTW_XMMdq_MEMw}, +{"VPBROADCASTW_XMMdq_XMMw", XED_IFORM_VPBROADCASTW_XMMdq_XMMw}, +{"VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512", XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512}, +{"VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512}, +{"VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512}, +{"VPBROADCASTW_YMMqq_MEMw", XED_IFORM_VPBROADCASTW_YMMqq_MEMw}, +{"VPBROADCASTW_YMMqq_XMMw", XED_IFORM_VPBROADCASTW_YMMqq_XMMw}, +{"VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512", XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512}, +{"VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512}, +{"VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512}, +{"VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512", XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512}, +{"VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512}, +{"VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512}, +{"VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512}, +{"VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512}, +{"VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8}, +{"VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512}, +{"VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8}, +{"VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512}, +{"VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512}, +{"VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq", XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq}, +{"VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq}, +{"VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq}, +{"VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512}, +{"VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512}, +{"VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512}, +{"VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512}, +{"VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512}, +{"VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512", XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512}, +{"VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512}, +{"VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512}, +{"VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512}, +{"VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512}, +{"VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512}, +{"VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512", XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512}, +{"VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPCMPEQB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq}, +{"VPCMPEQB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq}, +{"VPCMPEQB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq}, +{"VPCMPEQB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq}, +{"VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPCMPEQD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq}, +{"VPCMPEQD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq}, +{"VPCMPEQD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq}, +{"VPCMPEQD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq}, +{"VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPCMPEQQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq}, +{"VPCMPEQQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq}, +{"VPCMPEQQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq}, +{"VPCMPEQQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq}, +{"VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPCMPEQW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq}, +{"VPCMPEQW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq}, +{"VPCMPEQW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq}, +{"VPCMPEQW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq}, +{"VPCMPESTRI_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb}, +{"VPCMPESTRI_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb}, +{"VPCMPESTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb}, +{"VPCMPESTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb}, +{"VPCMPESTRM_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb}, +{"VPCMPESTRM_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb}, +{"VPCMPESTRM64_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb}, +{"VPCMPESTRM64_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb}, +{"VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPCMPGTB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq}, +{"VPCMPGTB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq}, +{"VPCMPGTB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq}, +{"VPCMPGTB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq}, +{"VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512}, +{"VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512}, +{"VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512}, +{"VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512}, +{"VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512}, +{"VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512}, +{"VPCMPGTD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq}, +{"VPCMPGTD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq}, +{"VPCMPGTD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq}, +{"VPCMPGTD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq}, +{"VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512}, +{"VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512}, +{"VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512}, +{"VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512}, +{"VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512}, +{"VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512", XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512}, +{"VPCMPGTQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq}, +{"VPCMPGTQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq}, +{"VPCMPGTQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq}, +{"VPCMPGTQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq}, +{"VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPCMPGTW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq}, +{"VPCMPGTW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq}, +{"VPCMPGTW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq}, +{"VPCMPGTW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq}, +{"VPCMPISTRI_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb}, +{"VPCMPISTRI_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb}, +{"VPCMPISTRI64_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb}, +{"VPCMPISTRI64_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb}, +{"VPCMPISTRM_XMMdq_MEMdq_IMMb", XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb}, +{"VPCMPISTRM_XMMdq_XMMdq_IMMb", XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb}, +{"VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512}, +{"VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512}, +{"VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512}, +{"VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512}, +{"VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512}, +{"VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512", XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512}, +{"VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512}, +{"VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512}, +{"VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512}, +{"VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512}, +{"VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512}, +{"VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512}, +{"VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512}, +{"VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512}, +{"VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512}, +{"VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512}, +{"VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512}, +{"VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512}, +{"VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512}, +{"VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512}, +{"VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512}, +{"VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512}, +{"VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512}, +{"VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512}, +{"VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512", XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512}, +{"VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512}, +{"VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512}, +{"VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512}, +{"VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512}, +{"VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512}, +{"VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512", XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512}, +{"VPCOMB_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMB_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512}, +{"VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512}, +{"VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512}, +{"VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512}, +{"VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512}, +{"VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512}, +{"VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512}, +{"VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512}, +{"VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512}, +{"VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512}, +{"VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512}, +{"VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512}, +{"VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512}, +{"VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512}, +{"VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512}, +{"VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512}, +{"VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512}, +{"VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512}, +{"VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512}, +{"VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512}, +{"VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCOMW_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPCOMW_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD", XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD}, +{"VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD", XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD}, +{"VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD", XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD}, +{"VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD", XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD}, +{"VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512}, +{"VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512", XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512}, +{"VPDPBUSD_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32}, +{"VPDPBUSD_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32}, +{"VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512}, +{"VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512", XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512}, +{"VPDPBUSD_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32}, +{"VPDPBUSD_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32}, +{"VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512}, +{"VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512", XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512}, +{"VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512}, +{"VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512", XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512}, +{"VPDPBUSDS_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32}, +{"VPDPBUSDS_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32}, +{"VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512}, +{"VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512", XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512}, +{"VPDPBUSDS_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32}, +{"VPDPBUSDS_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32}, +{"VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512", XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512}, +{"VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512", XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512}, +{"VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512}, +{"VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512", XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512}, +{"VPDPWSSD_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32}, +{"VPDPWSSD_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32}, +{"VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512}, +{"VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512", XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512}, +{"VPDPWSSD_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32}, +{"VPDPWSSD_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32}, +{"VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512}, +{"VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512", XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512}, +{"VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512}, +{"VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512", XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512}, +{"VPDPWSSDS_XMMi32_XMMu32_MEMu32", XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32}, +{"VPDPWSSDS_XMMi32_XMMu32_XMMu32", XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32}, +{"VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512}, +{"VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512", XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512}, +{"VPDPWSSDS_YMMi32_YMMu32_MEMu32", XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32}, +{"VPDPWSSDS_YMMi32_YMMu32_YMMu32", XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32}, +{"VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512", XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512}, +{"VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512", XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512}, +{"VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPERMD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq}, +{"VPERMD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq}, +{"VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb}, +{"VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb}, +{"VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb}, +{"VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb}, +{"VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb}, +{"VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb}, +{"VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb}, +{"VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb}, +{"VPERMILPD_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb}, +{"VPERMILPD_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb}, +{"VPERMILPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq}, +{"VPERMILPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq}, +{"VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512}, +{"VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VPERMILPD_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb}, +{"VPERMILPD_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb}, +{"VPERMILPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq}, +{"VPERMILPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq}, +{"VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VPERMILPS_XMMdq_MEMdq_IMMb", XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb}, +{"VPERMILPS_XMMdq_XMMdq_IMMb", XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb}, +{"VPERMILPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq}, +{"VPERMILPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq}, +{"VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512}, +{"VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512}, +{"VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VPERMILPS_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb}, +{"VPERMILPS_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb}, +{"VPERMILPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq}, +{"VPERMILPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq}, +{"VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VPERMPD_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb}, +{"VPERMPD_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb}, +{"VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VPERMPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq}, +{"VPERMPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq}, +{"VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VPERMQ_YMMqq_MEMqq_IMMb", XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb}, +{"VPERMQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb}, +{"VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512}, +{"VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512}, +{"VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512}, +{"VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512}, +{"VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512}, +{"VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512}, +{"VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512}, +{"VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512}, +{"VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512}, +{"VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512}, +{"VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512}, +{"VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512}, +{"VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512}, +{"VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512}, +{"VPEXTRB_GPR32d_XMMdq_IMMb", XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb}, +{"VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512", XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512}, +{"VPEXTRB_MEMb_XMMdq_IMMb", XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb}, +{"VPEXTRB_MEMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512}, +{"VPEXTRD_GPR32d_XMMdq_IMMb", XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb}, +{"VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512", XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512}, +{"VPEXTRD_MEMd_XMMdq_IMMb", XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb}, +{"VPEXTRD_MEMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512}, +{"VPEXTRQ_GPR64q_XMMdq_IMMb", XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb}, +{"VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512", XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512}, +{"VPEXTRQ_MEMq_XMMdq_IMMb", XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb}, +{"VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512}, +{"VPEXTRW_GPR32d_XMMdq_IMMb_15", XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15}, +{"VPEXTRW_GPR32d_XMMdq_IMMb_C5", XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5}, +{"VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512", XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512}, +{"VPEXTRW_MEMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512}, +{"VPEXTRW_MEMw_XMMdq_IMMb", XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb}, +{"VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5", XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5}, +{"VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128", XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128}, +{"VPGATHERDD_XMMu32_MEMd_XMMi32_VL128", XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128}, +{"VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256", XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256}, +{"VPGATHERDD_YMMu32_MEMd_YMMi32_VL256", XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256}, +{"VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512", XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512}, +{"VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128}, +{"VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128", XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128}, +{"VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256}, +{"VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256", XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256}, +{"VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512}, +{"VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128", XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128}, +{"VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256", XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256}, +{"VPGATHERQD_XMMu32_MEMd_XMMi32_VL128", XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128}, +{"VPGATHERQD_XMMu32_MEMd_XMMi32_VL256", XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256}, +{"VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512", XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512}, +{"VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128", XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128}, +{"VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128", XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128}, +{"VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256", XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256}, +{"VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256", XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256}, +{"VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512", XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512}, +{"VPHADDBD_XMMdq_MEMdq", XED_IFORM_VPHADDBD_XMMdq_MEMdq}, +{"VPHADDBD_XMMdq_XMMdq", XED_IFORM_VPHADDBD_XMMdq_XMMdq}, +{"VPHADDBQ_XMMdq_MEMdq", XED_IFORM_VPHADDBQ_XMMdq_MEMdq}, +{"VPHADDBQ_XMMdq_XMMdq", XED_IFORM_VPHADDBQ_XMMdq_XMMdq}, +{"VPHADDBW_XMMdq_MEMdq", XED_IFORM_VPHADDBW_XMMdq_MEMdq}, +{"VPHADDBW_XMMdq_XMMdq", XED_IFORM_VPHADDBW_XMMdq_XMMdq}, +{"VPHADDD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq}, +{"VPHADDD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq}, +{"VPHADDD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq}, +{"VPHADDD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq}, +{"VPHADDDQ_XMMdq_MEMdq", XED_IFORM_VPHADDDQ_XMMdq_MEMdq}, +{"VPHADDDQ_XMMdq_XMMdq", XED_IFORM_VPHADDDQ_XMMdq_XMMdq}, +{"VPHADDSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq}, +{"VPHADDSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq}, +{"VPHADDSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq}, +{"VPHADDSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq}, +{"VPHADDUBD_XMMdq_MEMdq", XED_IFORM_VPHADDUBD_XMMdq_MEMdq}, +{"VPHADDUBD_XMMdq_XMMdq", XED_IFORM_VPHADDUBD_XMMdq_XMMdq}, +{"VPHADDUBQ_XMMdq_MEMdq", XED_IFORM_VPHADDUBQ_XMMdq_MEMdq}, +{"VPHADDUBQ_XMMdq_XMMdq", XED_IFORM_VPHADDUBQ_XMMdq_XMMdq}, +{"VPHADDUBW_XMMdq_MEMdq", XED_IFORM_VPHADDUBW_XMMdq_MEMdq}, +{"VPHADDUBW_XMMdq_XMMdq", XED_IFORM_VPHADDUBW_XMMdq_XMMdq}, +{"VPHADDUDQ_XMMdq_MEMdq", XED_IFORM_VPHADDUDQ_XMMdq_MEMdq}, +{"VPHADDUDQ_XMMdq_XMMdq", XED_IFORM_VPHADDUDQ_XMMdq_XMMdq}, +{"VPHADDUWD_XMMdq_MEMdq", XED_IFORM_VPHADDUWD_XMMdq_MEMdq}, +{"VPHADDUWD_XMMdq_XMMdq", XED_IFORM_VPHADDUWD_XMMdq_XMMdq}, +{"VPHADDUWQ_XMMdq_MEMdq", XED_IFORM_VPHADDUWQ_XMMdq_MEMdq}, +{"VPHADDUWQ_XMMdq_XMMdq", XED_IFORM_VPHADDUWQ_XMMdq_XMMdq}, +{"VPHADDW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq}, +{"VPHADDW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq}, +{"VPHADDW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq}, +{"VPHADDW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq}, +{"VPHADDWD_XMMdq_MEMdq", XED_IFORM_VPHADDWD_XMMdq_MEMdq}, +{"VPHADDWD_XMMdq_XMMdq", XED_IFORM_VPHADDWD_XMMdq_XMMdq}, +{"VPHADDWQ_XMMdq_MEMdq", XED_IFORM_VPHADDWQ_XMMdq_MEMdq}, +{"VPHADDWQ_XMMdq_XMMdq", XED_IFORM_VPHADDWQ_XMMdq_XMMdq}, +{"VPHMINPOSUW_XMMdq_MEMdq", XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq}, +{"VPHMINPOSUW_XMMdq_XMMdq", XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq}, +{"VPHSUBBW_XMMdq_MEMdq", XED_IFORM_VPHSUBBW_XMMdq_MEMdq}, +{"VPHSUBBW_XMMdq_XMMdq", XED_IFORM_VPHSUBBW_XMMdq_XMMdq}, +{"VPHSUBD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq}, +{"VPHSUBD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq}, +{"VPHSUBD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq}, +{"VPHSUBD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq}, +{"VPHSUBDQ_XMMdq_MEMdq", XED_IFORM_VPHSUBDQ_XMMdq_MEMdq}, +{"VPHSUBDQ_XMMdq_XMMdq", XED_IFORM_VPHSUBDQ_XMMdq_XMMdq}, +{"VPHSUBSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq}, +{"VPHSUBSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq}, +{"VPHSUBSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq}, +{"VPHSUBSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq}, +{"VPHSUBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq}, +{"VPHSUBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq}, +{"VPHSUBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq}, +{"VPHSUBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq}, +{"VPHSUBWD_XMMdq_MEMdq", XED_IFORM_VPHSUBWD_XMMdq_MEMdq}, +{"VPHSUBWD_XMMdq_XMMdq", XED_IFORM_VPHSUBWD_XMMdq_XMMdq}, +{"VPINSRB_XMMdq_XMMdq_GPR32d_IMMb", XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb}, +{"VPINSRB_XMMdq_XMMdq_MEMb_IMMb", XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb}, +{"VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512", XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512}, +{"VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512}, +{"VPINSRD_XMMdq_XMMdq_GPR32d_IMMb", XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb}, +{"VPINSRD_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb}, +{"VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512", XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512}, +{"VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512}, +{"VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb", XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb}, +{"VPINSRQ_XMMdq_XMMdq_MEMq_IMMb", XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb}, +{"VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512", XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512}, +{"VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512}, +{"VPINSRW_XMMdq_XMMdq_GPR32d_IMMb", XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb}, +{"VPINSRW_XMMdq_XMMdq_MEMw_IMMb", XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb}, +{"VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512", XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512}, +{"VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512}, +{"VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD", XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD}, +{"VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD", XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD}, +{"VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD", XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD}, +{"VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD", XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD}, +{"VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPMADDUBSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq}, +{"VPMADDUBSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq}, +{"VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPMADDUBSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq}, +{"VPMADDUBSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq}, +{"VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPMADDWD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq}, +{"VPMADDWD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq}, +{"VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPMADDWD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq}, +{"VPMADDWD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq}, +{"VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPMASKMOVD_MEMdq_XMMdq_XMMdq", XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq}, +{"VPMASKMOVD_MEMqq_YMMqq_YMMqq", XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq}, +{"VPMASKMOVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq}, +{"VPMASKMOVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq}, +{"VPMASKMOVQ_MEMdq_XMMdq_XMMdq", XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq}, +{"VPMASKMOVQ_MEMqq_YMMqq_YMMqq", XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq}, +{"VPMASKMOVQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq}, +{"VPMASKMOVQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq}, +{"VPMAXSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq}, +{"VPMAXSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq}, +{"VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512}, +{"VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512}, +{"VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512}, +{"VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512}, +{"VPMAXSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq}, +{"VPMAXSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq}, +{"VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512}, +{"VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512}, +{"VPMAXSD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq}, +{"VPMAXSD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq}, +{"VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512}, +{"VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512}, +{"VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512}, +{"VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512}, +{"VPMAXSD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq}, +{"VPMAXSD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq}, +{"VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512}, +{"VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512}, +{"VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512", XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512}, +{"VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512", XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512}, +{"VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512", XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512}, +{"VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512", XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512}, +{"VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512", XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512}, +{"VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512", XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512}, +{"VPMAXSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq}, +{"VPMAXSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq}, +{"VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPMAXSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq}, +{"VPMAXSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq}, +{"VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPMAXUB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq}, +{"VPMAXUB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq}, +{"VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPMAXUB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq}, +{"VPMAXUB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq}, +{"VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPMAXUD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq}, +{"VPMAXUD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq}, +{"VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPMAXUD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq}, +{"VPMAXUD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq}, +{"VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPMAXUW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq}, +{"VPMAXUW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq}, +{"VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPMAXUW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq}, +{"VPMAXUW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq}, +{"VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPMINSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq}, +{"VPMINSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq}, +{"VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512}, +{"VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512}, +{"VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512}, +{"VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512}, +{"VPMINSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq}, +{"VPMINSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq}, +{"VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512}, +{"VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512}, +{"VPMINSD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq}, +{"VPMINSD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq}, +{"VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512}, +{"VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512}, +{"VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512}, +{"VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512}, +{"VPMINSD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq}, +{"VPMINSD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq}, +{"VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512}, +{"VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512}, +{"VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512", XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512}, +{"VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512", XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512}, +{"VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512", XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512}, +{"VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512", XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512}, +{"VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512", XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512}, +{"VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512", XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512}, +{"VPMINSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq}, +{"VPMINSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq}, +{"VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPMINSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq}, +{"VPMINSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq}, +{"VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPMINUB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq}, +{"VPMINUB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq}, +{"VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPMINUB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq}, +{"VPMINUB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq}, +{"VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPMINUD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq}, +{"VPMINUD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq}, +{"VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPMINUD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq}, +{"VPMINUD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq}, +{"VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPMINUW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq}, +{"VPMINUW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq}, +{"VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPMINUW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq}, +{"VPMINUW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq}, +{"VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPMOVB2M_MASKmskw_XMMu8_AVX512", XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512}, +{"VPMOVB2M_MASKmskw_YMMu8_AVX512", XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512}, +{"VPMOVB2M_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512}, +{"VPMOVD2M_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512}, +{"VPMOVD2M_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512}, +{"VPMOVD2M_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512}, +{"VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512}, +{"VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512}, +{"VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512}, +{"VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512}, +{"VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512}, +{"VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512}, +{"VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512}, +{"VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512}, +{"VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512}, +{"VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512}, +{"VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512}, +{"VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512}, +{"VPMOVM2B_XMMu8_MASKmskw_AVX512", XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512}, +{"VPMOVM2B_YMMu8_MASKmskw_AVX512", XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512}, +{"VPMOVM2B_ZMMu8_MASKmskw_AVX512", XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512}, +{"VPMOVM2D_XMMu32_MASKmskw_AVX512", XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512}, +{"VPMOVM2D_YMMu32_MASKmskw_AVX512", XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512}, +{"VPMOVM2D_ZMMu32_MASKmskw_AVX512", XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512}, +{"VPMOVM2Q_XMMu64_MASKmskw_AVX512", XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512}, +{"VPMOVM2Q_YMMu64_MASKmskw_AVX512", XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512}, +{"VPMOVM2Q_ZMMu64_MASKmskw_AVX512", XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512}, +{"VPMOVM2W_XMMu16_MASKmskw_AVX512", XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512}, +{"VPMOVM2W_YMMu16_MASKmskw_AVX512", XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512}, +{"VPMOVM2W_ZMMu16_MASKmskw_AVX512", XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512}, +{"VPMOVMSKB_GPR32d_XMMdq", XED_IFORM_VPMOVMSKB_GPR32d_XMMdq}, +{"VPMOVMSKB_GPR32d_YMMqq", XED_IFORM_VPMOVMSKB_GPR32d_YMMqq}, +{"VPMOVQ2M_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512}, +{"VPMOVQ2M_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512}, +{"VPMOVQ2M_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512}, +{"VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512}, +{"VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512}, +{"VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512}, +{"VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512}, +{"VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512}, +{"VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512}, +{"VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512}, +{"VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512}, +{"VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512}, +{"VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512}, +{"VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512}, +{"VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512}, +{"VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512}, +{"VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512}, +{"VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512}, +{"VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512}, +{"VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512}, +{"VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512}, +{"VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512}, +{"VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512}, +{"VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512}, +{"VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512}, +{"VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512}, +{"VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512}, +{"VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512}, +{"VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512}, +{"VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512}, +{"VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512}, +{"VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512}, +{"VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512", XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512}, +{"VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512}, +{"VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512}, +{"VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512}, +{"VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512}, +{"VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512}, +{"VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512}, +{"VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512}, +{"VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512}, +{"VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512}, +{"VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512}, +{"VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512}, +{"VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512}, +{"VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512}, +{"VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512}, +{"VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512}, +{"VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512", XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512}, +{"VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512", XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512}, +{"VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512", XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512}, +{"VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512}, +{"VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512}, +{"VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512", XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512}, +{"VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512}, +{"VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512}, +{"VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512", XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512}, +{"VPMOVSXBD_XMMdq_MEMd", XED_IFORM_VPMOVSXBD_XMMdq_MEMd}, +{"VPMOVSXBD_XMMdq_XMMd", XED_IFORM_VPMOVSXBD_XMMdq_XMMd}, +{"VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBD_YMMqq_MEMq", XED_IFORM_VPMOVSXBD_YMMqq_MEMq}, +{"VPMOVSXBD_YMMqq_XMMq", XED_IFORM_VPMOVSXBD_YMMqq_XMMq}, +{"VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBQ_XMMdq_MEMw", XED_IFORM_VPMOVSXBQ_XMMdq_MEMw}, +{"VPMOVSXBQ_XMMdq_XMMw", XED_IFORM_VPMOVSXBQ_XMMdq_XMMw}, +{"VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBQ_YMMqq_MEMd", XED_IFORM_VPMOVSXBQ_YMMqq_MEMd}, +{"VPMOVSXBQ_YMMqq_XMMd", XED_IFORM_VPMOVSXBQ_YMMqq_XMMd}, +{"VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBW_XMMdq_MEMq", XED_IFORM_VPMOVSXBW_XMMdq_MEMq}, +{"VPMOVSXBW_XMMdq_XMMq", XED_IFORM_VPMOVSXBW_XMMdq_XMMq}, +{"VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512}, +{"VPMOVSXBW_YMMqq_MEMdq", XED_IFORM_VPMOVSXBW_YMMqq_MEMdq}, +{"VPMOVSXBW_YMMqq_XMMdq", XED_IFORM_VPMOVSXBW_YMMqq_XMMdq}, +{"VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512}, +{"VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512", XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512}, +{"VPMOVSXDQ_XMMdq_MEMq", XED_IFORM_VPMOVSXDQ_XMMdq_MEMq}, +{"VPMOVSXDQ_XMMdq_XMMq", XED_IFORM_VPMOVSXDQ_XMMdq_XMMq}, +{"VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512}, +{"VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512}, +{"VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512}, +{"VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512}, +{"VPMOVSXDQ_YMMqq_MEMdq", XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq}, +{"VPMOVSXDQ_YMMqq_XMMdq", XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq}, +{"VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512}, +{"VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512}, +{"VPMOVSXWD_XMMdq_MEMq", XED_IFORM_VPMOVSXWD_XMMdq_MEMq}, +{"VPMOVSXWD_XMMdq_XMMq", XED_IFORM_VPMOVSXWD_XMMdq_XMMq}, +{"VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512}, +{"VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512}, +{"VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512}, +{"VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512}, +{"VPMOVSXWD_YMMqq_MEMdq", XED_IFORM_VPMOVSXWD_YMMqq_MEMdq}, +{"VPMOVSXWD_YMMqq_XMMdq", XED_IFORM_VPMOVSXWD_YMMqq_XMMdq}, +{"VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512}, +{"VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512}, +{"VPMOVSXWQ_XMMdq_MEMd", XED_IFORM_VPMOVSXWQ_XMMdq_MEMd}, +{"VPMOVSXWQ_XMMdq_XMMd", XED_IFORM_VPMOVSXWQ_XMMdq_XMMd}, +{"VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512}, +{"VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512}, +{"VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512}, +{"VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512}, +{"VPMOVSXWQ_YMMqq_MEMq", XED_IFORM_VPMOVSXWQ_YMMqq_MEMq}, +{"VPMOVSXWQ_YMMqq_XMMq", XED_IFORM_VPMOVSXWQ_YMMqq_XMMq}, +{"VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512}, +{"VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512}, +{"VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512}, +{"VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512}, +{"VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512}, +{"VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512}, +{"VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512}, +{"VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512}, +{"VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512}, +{"VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512}, +{"VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512}, +{"VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512", XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512}, +{"VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512", XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512}, +{"VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512}, +{"VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512}, +{"VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512}, +{"VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512}, +{"VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512}, +{"VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512}, +{"VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512}, +{"VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512}, +{"VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512}, +{"VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512}, +{"VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512}, +{"VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512}, +{"VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512}, +{"VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512}, +{"VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512}, +{"VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512}, +{"VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512", XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512}, +{"VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512", XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512}, +{"VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512}, +{"VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512}, +{"VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512}, +{"VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512}, +{"VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512}, +{"VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512}, +{"VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512}, +{"VPMOVW2M_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512}, +{"VPMOVW2M_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512}, +{"VPMOVW2M_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512}, +{"VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512}, +{"VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512}, +{"VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512}, +{"VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512", XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512}, +{"VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512", XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512}, +{"VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512}, +{"VPMOVZXBD_XMMdq_MEMd", XED_IFORM_VPMOVZXBD_XMMdq_MEMd}, +{"VPMOVZXBD_XMMdq_XMMd", XED_IFORM_VPMOVZXBD_XMMdq_XMMd}, +{"VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBD_YMMqq_MEMq", XED_IFORM_VPMOVZXBD_YMMqq_MEMq}, +{"VPMOVZXBD_YMMqq_XMMq", XED_IFORM_VPMOVZXBD_YMMqq_XMMq}, +{"VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBQ_XMMdq_MEMw", XED_IFORM_VPMOVZXBQ_XMMdq_MEMw}, +{"VPMOVZXBQ_XMMdq_XMMw", XED_IFORM_VPMOVZXBQ_XMMdq_XMMw}, +{"VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBQ_YMMqq_MEMd", XED_IFORM_VPMOVZXBQ_YMMqq_MEMd}, +{"VPMOVZXBQ_YMMqq_XMMd", XED_IFORM_VPMOVZXBQ_YMMqq_XMMd}, +{"VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBW_XMMdq_MEMq", XED_IFORM_VPMOVZXBW_XMMdq_MEMq}, +{"VPMOVZXBW_XMMdq_XMMq", XED_IFORM_VPMOVZXBW_XMMdq_XMMq}, +{"VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512", XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512}, +{"VPMOVZXBW_YMMqq_MEMdq", XED_IFORM_VPMOVZXBW_YMMqq_MEMdq}, +{"VPMOVZXBW_YMMqq_XMMdq", XED_IFORM_VPMOVZXBW_YMMqq_XMMdq}, +{"VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512", XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512}, +{"VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512", XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512}, +{"VPMOVZXDQ_XMMdq_MEMq", XED_IFORM_VPMOVZXDQ_XMMdq_MEMq}, +{"VPMOVZXDQ_XMMdq_XMMq", XED_IFORM_VPMOVZXDQ_XMMdq_XMMq}, +{"VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512}, +{"VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512}, +{"VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512}, +{"VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512", XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512}, +{"VPMOVZXDQ_YMMqq_MEMdq", XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq}, +{"VPMOVZXDQ_YMMqq_XMMdq", XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq}, +{"VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512", XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512}, +{"VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512", XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512}, +{"VPMOVZXWD_XMMdq_MEMq", XED_IFORM_VPMOVZXWD_XMMdq_MEMq}, +{"VPMOVZXWD_XMMdq_XMMq", XED_IFORM_VPMOVZXWD_XMMdq_XMMq}, +{"VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512}, +{"VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512}, +{"VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512}, +{"VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512}, +{"VPMOVZXWD_YMMqq_MEMdq", XED_IFORM_VPMOVZXWD_YMMqq_MEMdq}, +{"VPMOVZXWD_YMMqq_XMMdq", XED_IFORM_VPMOVZXWD_YMMqq_XMMdq}, +{"VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512}, +{"VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512", XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512}, +{"VPMOVZXWQ_XMMdq_MEMd", XED_IFORM_VPMOVZXWQ_XMMdq_MEMd}, +{"VPMOVZXWQ_XMMdq_XMMd", XED_IFORM_VPMOVZXWQ_XMMdq_XMMd}, +{"VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512}, +{"VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512}, +{"VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512}, +{"VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512}, +{"VPMOVZXWQ_YMMqq_MEMq", XED_IFORM_VPMOVZXWQ_YMMqq_MEMq}, +{"VPMOVZXWQ_YMMqq_XMMq", XED_IFORM_VPMOVZXWQ_YMMqq_XMMq}, +{"VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512", XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512}, +{"VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512", XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512}, +{"VPMULDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq}, +{"VPMULDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq}, +{"VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512", XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512}, +{"VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512", XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512}, +{"VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512", XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512}, +{"VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512", XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512}, +{"VPMULDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq}, +{"VPMULDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq}, +{"VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512", XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512}, +{"VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512", XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512}, +{"VPMULHRSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq}, +{"VPMULHRSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq}, +{"VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPMULHRSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq}, +{"VPMULHRSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq}, +{"VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPMULHUW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq}, +{"VPMULHUW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq}, +{"VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPMULHUW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq}, +{"VPMULHUW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq}, +{"VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPMULHW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq}, +{"VPMULHW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq}, +{"VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPMULHW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq}, +{"VPMULHW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq}, +{"VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPMULLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq}, +{"VPMULLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq}, +{"VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPMULLD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq}, +{"VPMULLD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq}, +{"VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPMULLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq}, +{"VPMULLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq}, +{"VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPMULLW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq}, +{"VPMULLW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq}, +{"VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512}, +{"VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512}, +{"VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512}, +{"VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512}, +{"VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512}, +{"VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512", XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512}, +{"VPMULUDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq}, +{"VPMULUDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq}, +{"VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPMULUDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq}, +{"VPMULUDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq}, +{"VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512}, +{"VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512", XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512}, +{"VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512}, +{"VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512", XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512}, +{"VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512", XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512}, +{"VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512", XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512}, +{"VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512}, +{"VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512", XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512}, +{"VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512}, +{"VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512", XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512}, +{"VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512", XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512}, +{"VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512", XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512}, +{"VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512}, +{"VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512", XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512}, +{"VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512}, +{"VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512", XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512}, +{"VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512", XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512}, +{"VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512", XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512}, +{"VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512}, +{"VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512", XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512}, +{"VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512}, +{"VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512", XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512}, +{"VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512", XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512}, +{"VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512", XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512}, +{"VPOR_XMMdq_XMMdq_MEMdq", XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq}, +{"VPOR_XMMdq_XMMdq_XMMdq", XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq}, +{"VPOR_YMMqq_YMMqq_MEMqq", XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq}, +{"VPOR_YMMqq_YMMqq_YMMqq", XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq}, +{"VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPPERM_XMMdq_XMMdq_MEMdq_XMMdq", XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq}, +{"VPPERM_XMMdq_XMMdq_XMMdq_MEMdq", XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq}, +{"VPPERM_XMMdq_XMMdq_XMMdq_XMMdq", XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq}, +{"VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512}, +{"VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512}, +{"VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512}, +{"VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512}, +{"VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPROTB_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb}, +{"VPROTB_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq}, +{"VPROTB_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb}, +{"VPROTB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq}, +{"VPROTB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq}, +{"VPROTD_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb}, +{"VPROTD_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq}, +{"VPROTD_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb}, +{"VPROTD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq}, +{"VPROTD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq}, +{"VPROTQ_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb}, +{"VPROTQ_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq}, +{"VPROTQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb}, +{"VPROTQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq}, +{"VPROTQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq}, +{"VPROTW_XMMdq_MEMdq_IMMb", XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb}, +{"VPROTW_XMMdq_MEMdq_XMMdq", XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq}, +{"VPROTW_XMMdq_XMMdq_IMMb", XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb}, +{"VPROTW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq}, +{"VPROTW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq}, +{"VPSADBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq}, +{"VPSADBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq}, +{"VPSADBW_XMMu16_XMMu8_MEMu8_AVX512", XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512}, +{"VPSADBW_XMMu16_XMMu8_XMMu8_AVX512", XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512}, +{"VPSADBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq}, +{"VPSADBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq}, +{"VPSADBW_YMMu16_YMMu8_MEMu8_AVX512", XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512}, +{"VPSADBW_YMMu16_YMMu8_YMMu8_AVX512", XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512}, +{"VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512}, +{"VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512}, +{"VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128", XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128}, +{"VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256", XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256}, +{"VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512", XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512}, +{"VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128}, +{"VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256}, +{"VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512}, +{"VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128", XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128}, +{"VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256", XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256}, +{"VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512", XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512}, +{"VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128", XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128}, +{"VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256", XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256}, +{"VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512", XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512}, +{"VPSHAB_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq}, +{"VPSHAB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq}, +{"VPSHAB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq}, +{"VPSHAD_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq}, +{"VPSHAD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq}, +{"VPSHAD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq}, +{"VPSHAQ_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq}, +{"VPSHAQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq}, +{"VPSHAQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq}, +{"VPSHAW_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq}, +{"VPSHAW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq}, +{"VPSHAW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq}, +{"VPSHLB_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq}, +{"VPSHLB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq}, +{"VPSHLB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq}, +{"VPSHLD_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq}, +{"VPSHLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq}, +{"VPSHLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq}, +{"VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512}, +{"VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512}, +{"VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512}, +{"VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512}, +{"VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512}, +{"VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512}, +{"VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512}, +{"VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512}, +{"VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512}, +{"VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512}, +{"VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512}, +{"VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512}, +{"VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512}, +{"VPSHLQ_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq}, +{"VPSHLQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq}, +{"VPSHLQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq}, +{"VPSHLW_XMMdq_MEMdq_XMMdq", XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq}, +{"VPSHLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq}, +{"VPSHLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq}, +{"VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512}, +{"VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512}, +{"VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512}, +{"VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512}, +{"VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512}, +{"VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512}, +{"VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512}, +{"VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512}, +{"VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512}, +{"VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512}, +{"VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512}, +{"VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512}, +{"VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512}, +{"VPSHUFB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq}, +{"VPSHUFB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq}, +{"VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPSHUFB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq}, +{"VPSHUFB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq}, +{"VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512}, +{"VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512}, +{"VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512}, +{"VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512}, +{"VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512}, +{"VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512", XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512}, +{"VPSHUFD_XMMdq_MEMdq_IMMb", XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb}, +{"VPSHUFD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb}, +{"VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512}, +{"VPSHUFD_YMMqq_MEMqq_IMMb", XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb}, +{"VPSHUFD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb}, +{"VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VPSHUFHW_XMMdq_MEMdq_IMMb", XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb}, +{"VPSHUFHW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb}, +{"VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512}, +{"VPSHUFHW_YMMqq_MEMqq_IMMb", XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb}, +{"VPSHUFHW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb}, +{"VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512}, +{"VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512}, +{"VPSHUFLW_XMMdq_MEMdq_IMMb", XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb}, +{"VPSHUFLW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb}, +{"VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512}, +{"VPSHUFLW_YMMqq_MEMqq_IMMb", XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb}, +{"VPSHUFLW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb}, +{"VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512}, +{"VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512}, +{"VPSIGNB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq}, +{"VPSIGNB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq}, +{"VPSIGNB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq}, +{"VPSIGNB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq}, +{"VPSIGND_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq}, +{"VPSIGND_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq}, +{"VPSIGND_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq}, +{"VPSIGND_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq}, +{"VPSIGNW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq}, +{"VPSIGNW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq}, +{"VPSIGNW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq}, +{"VPSIGNW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq}, +{"VPSLLD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb}, +{"VPSLLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq}, +{"VPSLLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq}, +{"VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512}, +{"VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSLLD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb}, +{"VPSLLD_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq}, +{"VPSLLD_YMMqq_YMMqq_XMMq", XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq}, +{"VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512", XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512}, +{"VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512", XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512}, +{"VPSLLDQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb}, +{"VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512}, +{"VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512}, +{"VPSLLDQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb}, +{"VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512}, +{"VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512}, +{"VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512}, +{"VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512}, +{"VPSLLQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb}, +{"VPSLLQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq}, +{"VPSLLQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq}, +{"VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512}, +{"VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSLLQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb}, +{"VPSLLQ_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq}, +{"VPSLLQ_YMMqq_YMMqq_XMMq", XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq}, +{"VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512", XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512}, +{"VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512", XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512}, +{"VPSLLVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq}, +{"VPSLLVD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq}, +{"VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSLLVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq}, +{"VPSLLVD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq}, +{"VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPSLLVQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq}, +{"VPSLLVQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq}, +{"VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSLLVQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq}, +{"VPSLLVQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq}, +{"VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPSLLW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb}, +{"VPSLLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq}, +{"VPSLLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq}, +{"VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512}, +{"VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSLLW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb}, +{"VPSLLW_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq}, +{"VPSLLW_YMMqq_YMMqq_XMMq", XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq}, +{"VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512}, +{"VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512", XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512}, +{"VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512}, +{"VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512", XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512}, +{"VPSRAD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb}, +{"VPSRAD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq}, +{"VPSRAD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq}, +{"VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512}, +{"VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSRAD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb}, +{"VPSRAD_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq}, +{"VPSRAD_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq}, +{"VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512", XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512}, +{"VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512", XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512}, +{"VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512}, +{"VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512", XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512}, +{"VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512", XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512}, +{"VPSRAVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq}, +{"VPSRAVD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq}, +{"VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSRAVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq}, +{"VPSRAVD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq}, +{"VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPSRAW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb}, +{"VPSRAW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq}, +{"VPSRAW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq}, +{"VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512}, +{"VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSRAW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb}, +{"VPSRAW_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq}, +{"VPSRAW_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq}, +{"VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512}, +{"VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512", XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512}, +{"VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512}, +{"VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512", XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512}, +{"VPSRLD_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb}, +{"VPSRLD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq}, +{"VPSRLD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq}, +{"VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512}, +{"VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSRLD_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb}, +{"VPSRLD_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq}, +{"VPSRLD_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq}, +{"VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512}, +{"VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512", XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512}, +{"VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512}, +{"VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512}, +{"VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512", XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512}, +{"VPSRLDQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb}, +{"VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512}, +{"VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512}, +{"VPSRLDQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb}, +{"VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512}, +{"VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512}, +{"VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512}, +{"VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512", XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512}, +{"VPSRLQ_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb}, +{"VPSRLQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq}, +{"VPSRLQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq}, +{"VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512}, +{"VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSRLQ_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb}, +{"VPSRLQ_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq}, +{"VPSRLQ_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq}, +{"VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512}, +{"VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512", XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512}, +{"VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512}, +{"VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512}, +{"VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512", XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512}, +{"VPSRLVD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq}, +{"VPSRLVD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq}, +{"VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSRLVD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq}, +{"VPSRLVD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq}, +{"VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPSRLVQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq}, +{"VPSRLVQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq}, +{"VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSRLVQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq}, +{"VPSRLVQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq}, +{"VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPSRLW_XMMdq_XMMdq_IMMb", XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb}, +{"VPSRLW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq}, +{"VPSRLW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq}, +{"VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512}, +{"VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSRLW_YMMqq_YMMqq_IMMb", XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb}, +{"VPSRLW_YMMqq_YMMqq_MEMdq", XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq}, +{"VPSRLW_YMMqq_YMMqq_XMMq", XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq}, +{"VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512}, +{"VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512", XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512}, +{"VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512}, +{"VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512}, +{"VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512", XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512}, +{"VPSUBB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq}, +{"VPSUBB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq}, +{"VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPSUBB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq}, +{"VPSUBB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq}, +{"VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPSUBD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq}, +{"VPSUBD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq}, +{"VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPSUBD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq}, +{"VPSUBD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq}, +{"VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPSUBQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq}, +{"VPSUBQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq}, +{"VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPSUBQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq}, +{"VPSUBQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq}, +{"VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPSUBSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq}, +{"VPSUBSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq}, +{"VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512", XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512}, +{"VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512", XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512}, +{"VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512", XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512}, +{"VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512", XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512}, +{"VPSUBSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq}, +{"VPSUBSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq}, +{"VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512", XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512}, +{"VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512", XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512}, +{"VPSUBSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq}, +{"VPSUBSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq}, +{"VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512", XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512}, +{"VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512", XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512}, +{"VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512", XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512}, +{"VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512", XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512}, +{"VPSUBSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq}, +{"VPSUBSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq}, +{"VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512", XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512}, +{"VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512", XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512}, +{"VPSUBUSB_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq}, +{"VPSUBUSB_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq}, +{"VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPSUBUSB_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq}, +{"VPSUBUSB_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq}, +{"VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPSUBUSW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq}, +{"VPSUBUSW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq}, +{"VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSUBUSW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq}, +{"VPSUBUSW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq}, +{"VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPSUBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq}, +{"VPSUBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq}, +{"VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPSUBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq}, +{"VPSUBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq}, +{"VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512}, +{"VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512}, +{"VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512}, +{"VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512}, +{"VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512}, +{"VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512}, +{"VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512}, +{"VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VPTEST_XMMdq_MEMdq", XED_IFORM_VPTEST_XMMdq_MEMdq}, +{"VPTEST_XMMdq_XMMdq", XED_IFORM_VPTEST_XMMdq_XMMdq}, +{"VPTEST_YMMqq_MEMqq", XED_IFORM_VPTEST_YMMqq_MEMqq}, +{"VPTEST_YMMqq_YMMqq", XED_IFORM_VPTEST_YMMqq_YMMqq}, +{"VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPUNPCKHBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKHBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPUNPCKHBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKHBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPUNPCKHDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKHDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPUNPCKHDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKHDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPUNPCKHWD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKHWD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPUNPCKHWD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKHWD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPUNPCKLBW_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKLBW_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512}, +{"VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512", XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512}, +{"VPUNPCKLBW_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKLBW_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512}, +{"VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512", XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512}, +{"VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512", XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512}, +{"VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512", XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512}, +{"VPUNPCKLDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKLDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPUNPCKLDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKLDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VPUNPCKLWD_XMMdq_XMMdq_MEMdq", XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq}, +{"VPUNPCKLWD_XMMdq_XMMdq_XMMdq", XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq}, +{"VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512}, +{"VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512", XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512}, +{"VPUNPCKLWD_YMMqq_YMMqq_MEMqq", XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq}, +{"VPUNPCKLWD_YMMqq_YMMqq_YMMqq", XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq}, +{"VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512}, +{"VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512", XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512}, +{"VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512", XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512}, +{"VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512", XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512}, +{"VPXOR_XMMdq_XMMdq_MEMdq", XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq}, +{"VPXOR_XMMdq_XMMdq_XMMdq", XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq}, +{"VPXOR_YMMqq_YMMqq_MEMqq", XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq}, +{"VPXOR_YMMqq_YMMqq_YMMqq", XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq}, +{"VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512}, +{"VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512}, +{"VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512}, +{"VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512}, +{"VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512}, +{"VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512}, +{"VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER", XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER}, +{"VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER", XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER}, +{"VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER", XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER}, +{"VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER", XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER}, +{"VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER", XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER}, +{"VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER", XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER}, +{"VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER", XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER}, +{"VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER", XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER}, +{"VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512}, +{"VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512}, +{"VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512}, +{"VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512}, +{"VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512}, +{"VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512}, +{"VRCPPS_XMMdq_MEMdq", XED_IFORM_VRCPPS_XMMdq_MEMdq}, +{"VRCPPS_XMMdq_XMMdq", XED_IFORM_VRCPPS_XMMdq_XMMdq}, +{"VRCPPS_YMMqq_MEMqq", XED_IFORM_VRCPPS_YMMqq_MEMqq}, +{"VRCPPS_YMMqq_YMMqq", XED_IFORM_VRCPPS_YMMqq_YMMqq}, +{"VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VRCPSS_XMMdq_XMMdq_MEMd", XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd}, +{"VRCPSS_XMMdq_XMMdq_XMMd", XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd}, +{"VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512}, +{"VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512}, +{"VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512}, +{"VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512}, +{"VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512}, +{"VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512}, +{"VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512}, +{"VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512}, +{"VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512}, +{"VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512}, +{"VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512}, +{"VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512}, +{"VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512}, +{"VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512}, +{"VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512}, +{"VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512}, +{"VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512}, +{"VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512}, +{"VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512}, +{"VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512}, +{"VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512", XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512}, +{"VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512", XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512}, +{"VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VROUNDPD_XMMdq_MEMdq_IMMb", XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb}, +{"VROUNDPD_XMMdq_XMMdq_IMMb", XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb}, +{"VROUNDPD_YMMqq_MEMqq_IMMb", XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb}, +{"VROUNDPD_YMMqq_YMMqq_IMMb", XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb}, +{"VROUNDPS_XMMdq_MEMdq_IMMb", XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb}, +{"VROUNDPS_XMMdq_XMMdq_IMMb", XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb}, +{"VROUNDPS_YMMqq_MEMqq_IMMb", XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb}, +{"VROUNDPS_YMMqq_YMMqq_IMMb", XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb}, +{"VROUNDSD_XMMdq_XMMdq_MEMq_IMMb", XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb}, +{"VROUNDSD_XMMdq_XMMdq_XMMq_IMMb", XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb}, +{"VROUNDSS_XMMdq_XMMdq_MEMd_IMMb", XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb}, +{"VROUNDSS_XMMdq_XMMdq_XMMd_IMMb", XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb}, +{"VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER", XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER}, +{"VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER", XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER}, +{"VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER", XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER}, +{"VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER", XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER}, +{"VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER", XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER}, +{"VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER", XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER}, +{"VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER", XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER}, +{"VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER", XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER}, +{"VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512}, +{"VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512}, +{"VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512}, +{"VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512}, +{"VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512}, +{"VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512}, +{"VRSQRTPS_XMMdq_MEMdq", XED_IFORM_VRSQRTPS_XMMdq_MEMdq}, +{"VRSQRTPS_XMMdq_XMMdq", XED_IFORM_VRSQRTPS_XMMdq_XMMdq}, +{"VRSQRTPS_YMMqq_MEMqq", XED_IFORM_VRSQRTPS_YMMqq_MEMqq}, +{"VRSQRTPS_YMMqq_YMMqq", XED_IFORM_VRSQRTPS_YMMqq_YMMqq}, +{"VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VRSQRTSS_XMMdq_XMMdq_MEMd", XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd}, +{"VRSQRTSS_XMMdq_XMMdq_XMMd", XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd}, +{"VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128}, +{"VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256}, +{"VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512}, +{"VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128", XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128}, +{"VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256", XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256}, +{"VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512", XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512}, +{"VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512}, +{"VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512", XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512}, +{"VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128", XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128}, +{"VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256", XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256}, +{"VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512", XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512}, +{"VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128", XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128}, +{"VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256", XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256}, +{"VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512", XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512}, +{"VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512}, +{"VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512}, +{"VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512}, +{"VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512}, +{"VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512}, +{"VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512}, +{"VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512}, +{"VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512}, +{"VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512}, +{"VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512", XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512}, +{"VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512}, +{"VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512}, +{"VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512}, +{"VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512", XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512}, +{"VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb}, +{"VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb}, +{"VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512}, +{"VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512}, +{"VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512}, +{"VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512}, +{"VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb}, +{"VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb}, +{"VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512}, +{"VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512", XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512}, +{"VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb", XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb}, +{"VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb", XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb}, +{"VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512}, +{"VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512}, +{"VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512}, +{"VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512}, +{"VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb", XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb}, +{"VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb", XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb}, +{"VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512}, +{"VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512", XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512}, +{"VSQRTPD_XMMdq_MEMdq", XED_IFORM_VSQRTPD_XMMdq_MEMdq}, +{"VSQRTPD_XMMdq_XMMdq", XED_IFORM_VSQRTPD_XMMdq_XMMdq}, +{"VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512}, +{"VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512", XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512}, +{"VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512}, +{"VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512", XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512}, +{"VSQRTPD_YMMqq_MEMqq", XED_IFORM_VSQRTPD_YMMqq_MEMqq}, +{"VSQRTPD_YMMqq_YMMqq", XED_IFORM_VSQRTPD_YMMqq_YMMqq}, +{"VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512", XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512}, +{"VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512", XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512}, +{"VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512}, +{"VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512", XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512}, +{"VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512}, +{"VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512", XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512}, +{"VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512", XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512}, +{"VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512", XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512}, +{"VSQRTPS_XMMdq_MEMdq", XED_IFORM_VSQRTPS_XMMdq_MEMdq}, +{"VSQRTPS_XMMdq_XMMdq", XED_IFORM_VSQRTPS_XMMdq_XMMdq}, +{"VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512}, +{"VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512", XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512}, +{"VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512}, +{"VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512", XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512}, +{"VSQRTPS_YMMqq_MEMqq", XED_IFORM_VSQRTPS_YMMqq_MEMqq}, +{"VSQRTPS_YMMqq_YMMqq", XED_IFORM_VSQRTPS_YMMqq_YMMqq}, +{"VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512", XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512}, +{"VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512", XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512}, +{"VSQRTSD_XMMdq_XMMdq_MEMq", XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq}, +{"VSQRTSD_XMMdq_XMMdq_XMMq", XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq}, +{"VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VSQRTSS_XMMdq_XMMdq_MEMd", XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd}, +{"VSQRTSS_XMMdq_XMMdq_XMMd", XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd}, +{"VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VSTMXCSR_MEMd", XED_IFORM_VSTMXCSR_MEMd}, +{"VSUBPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq}, +{"VSUBPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq}, +{"VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VSUBPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq}, +{"VSUBPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq}, +{"VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512", XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512}, +{"VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512", XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512}, +{"VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512", XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512}, +{"VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512", XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512}, +{"VSUBPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq}, +{"VSUBPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq}, +{"VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VSUBPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq}, +{"VSUBPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq}, +{"VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VSUBSD_XMMdq_XMMdq_MEMq", XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq}, +{"VSUBSD_XMMdq_XMMdq_XMMq", XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq}, +{"VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512", XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512}, +{"VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512", XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512}, +{"VSUBSS_XMMdq_XMMdq_MEMd", XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd}, +{"VSUBSS_XMMdq_XMMdq_XMMd", XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd}, +{"VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VTESTPD_XMMdq_MEMdq", XED_IFORM_VTESTPD_XMMdq_MEMdq}, +{"VTESTPD_XMMdq_XMMdq", XED_IFORM_VTESTPD_XMMdq_XMMdq}, +{"VTESTPD_YMMqq_MEMqq", XED_IFORM_VTESTPD_YMMqq_MEMqq}, +{"VTESTPD_YMMqq_YMMqq", XED_IFORM_VTESTPD_YMMqq_YMMqq}, +{"VTESTPS_XMMdq_MEMdq", XED_IFORM_VTESTPS_XMMdq_MEMdq}, +{"VTESTPS_XMMdq_XMMdq", XED_IFORM_VTESTPS_XMMdq_XMMdq}, +{"VTESTPS_YMMqq_MEMqq", XED_IFORM_VTESTPS_YMMqq_MEMqq}, +{"VTESTPS_YMMqq_YMMqq", XED_IFORM_VTESTPS_YMMqq_YMMqq}, +{"VUCOMISD_XMMdq_MEMq", XED_IFORM_VUCOMISD_XMMdq_MEMq}, +{"VUCOMISD_XMMdq_XMMq", XED_IFORM_VUCOMISD_XMMdq_XMMq}, +{"VUCOMISD_XMMf64_MEMf64_AVX512", XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512}, +{"VUCOMISD_XMMf64_XMMf64_AVX512", XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512}, +{"VUCOMISH_XMMf16_MEMf16_AVX512", XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512}, +{"VUCOMISH_XMMf16_XMMf16_AVX512", XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512}, +{"VUCOMISS_XMMdq_MEMd", XED_IFORM_VUCOMISS_XMMdq_MEMd}, +{"VUCOMISS_XMMdq_XMMd", XED_IFORM_VUCOMISS_XMMdq_XMMd}, +{"VUCOMISS_XMMf32_MEMf32_AVX512", XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512}, +{"VUCOMISS_XMMf32_XMMf32_AVX512", XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512}, +{"VUNPCKHPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq}, +{"VUNPCKHPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq}, +{"VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VUNPCKHPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq}, +{"VUNPCKHPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq}, +{"VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VUNPCKHPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq}, +{"VUNPCKHPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq}, +{"VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VUNPCKHPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq}, +{"VUNPCKHPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq}, +{"VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VUNPCKLPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq}, +{"VUNPCKLPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq}, +{"VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512}, +{"VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512", XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512}, +{"VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512}, +{"VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512", XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512}, +{"VUNPCKLPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq}, +{"VUNPCKLPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq}, +{"VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512", XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512}, +{"VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512", XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512}, +{"VUNPCKLPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq}, +{"VUNPCKLPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq}, +{"VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512}, +{"VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512", XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512}, +{"VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512}, +{"VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512", XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512}, +{"VUNPCKLPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq}, +{"VUNPCKLPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq}, +{"VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512", XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512}, +{"VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512", XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512}, +{"VXORPD_XMMdq_XMMdq_MEMdq", XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq}, +{"VXORPD_XMMdq_XMMdq_XMMdq", XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq}, +{"VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512", XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512}, +{"VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512", XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512}, +{"VXORPD_YMMqq_YMMqq_MEMqq", XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq}, +{"VXORPD_YMMqq_YMMqq_YMMqq", XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq}, +{"VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512", XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512}, +{"VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512", XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512}, +{"VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512", XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512}, +{"VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512", XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512}, +{"VXORPS_XMMdq_XMMdq_MEMdq", XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq}, +{"VXORPS_XMMdq_XMMdq_XMMdq", XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq}, +{"VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512", XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512}, +{"VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512", XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512}, +{"VXORPS_YMMqq_YMMqq_MEMqq", XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq}, +{"VXORPS_YMMqq_YMMqq_YMMqq", XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq}, +{"VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512", XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512}, +{"VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512", XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512}, +{"VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512", XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512}, +{"VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512", XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512}, +{"VZEROALL", XED_IFORM_VZEROALL}, +{"VZEROUPPER", XED_IFORM_VZEROUPPER}, +{"WBINVD", XED_IFORM_WBINVD}, +{"WBNOINVD", XED_IFORM_WBNOINVD}, +{"WRFSBASE_GPRy", XED_IFORM_WRFSBASE_GPRy}, +{"WRGSBASE_GPRy", XED_IFORM_WRGSBASE_GPRy}, +{"WRMSR", XED_IFORM_WRMSR}, +{"WRPKRU", XED_IFORM_WRPKRU}, +{"WRSSD_MEMu32_GPR32u32", XED_IFORM_WRSSD_MEMu32_GPR32u32}, +{"WRSSQ_MEMu64_GPR64u64", XED_IFORM_WRSSQ_MEMu64_GPR64u64}, +{"WRUSSD_MEMu32_GPR32u32", XED_IFORM_WRUSSD_MEMu32_GPR32u32}, +{"WRUSSQ_MEMu64_GPR64u64", XED_IFORM_WRUSSQ_MEMu64_GPR64u64}, +{"XABORT_IMMb", XED_IFORM_XABORT_IMMb}, +{"XADD_GPR8_GPR8", XED_IFORM_XADD_GPR8_GPR8}, +{"XADD_GPRv_GPRv", XED_IFORM_XADD_GPRv_GPRv}, +{"XADD_MEMb_GPR8", XED_IFORM_XADD_MEMb_GPR8}, +{"XADD_MEMv_GPRv", XED_IFORM_XADD_MEMv_GPRv}, +{"XADD_LOCK_MEMb_GPR8", XED_IFORM_XADD_LOCK_MEMb_GPR8}, +{"XADD_LOCK_MEMv_GPRv", XED_IFORM_XADD_LOCK_MEMv_GPRv}, +{"XBEGIN_RELBRz", XED_IFORM_XBEGIN_RELBRz}, +{"XCHG_GPR8_GPR8", XED_IFORM_XCHG_GPR8_GPR8}, +{"XCHG_GPRv_GPRv", XED_IFORM_XCHG_GPRv_GPRv}, +{"XCHG_GPRv_OrAX", XED_IFORM_XCHG_GPRv_OrAX}, +{"XCHG_MEMb_GPR8", XED_IFORM_XCHG_MEMb_GPR8}, +{"XCHG_MEMv_GPRv", XED_IFORM_XCHG_MEMv_GPRv}, +{"XEND", XED_IFORM_XEND}, +{"XGETBV", XED_IFORM_XGETBV}, +{"XLAT", XED_IFORM_XLAT}, +{"XOR_AL_IMMb", XED_IFORM_XOR_AL_IMMb}, +{"XOR_GPR8_GPR8_30", XED_IFORM_XOR_GPR8_GPR8_30}, +{"XOR_GPR8_GPR8_32", XED_IFORM_XOR_GPR8_GPR8_32}, +{"XOR_GPR8_IMMb_80r6", XED_IFORM_XOR_GPR8_IMMb_80r6}, +{"XOR_GPR8_IMMb_82r6", XED_IFORM_XOR_GPR8_IMMb_82r6}, +{"XOR_GPR8_MEMb", XED_IFORM_XOR_GPR8_MEMb}, +{"XOR_GPRv_GPRv_31", XED_IFORM_XOR_GPRv_GPRv_31}, +{"XOR_GPRv_GPRv_33", XED_IFORM_XOR_GPRv_GPRv_33}, +{"XOR_GPRv_IMMb", XED_IFORM_XOR_GPRv_IMMb}, +{"XOR_GPRv_IMMz", XED_IFORM_XOR_GPRv_IMMz}, +{"XOR_GPRv_MEMv", XED_IFORM_XOR_GPRv_MEMv}, +{"XOR_MEMb_GPR8", XED_IFORM_XOR_MEMb_GPR8}, +{"XOR_MEMb_IMMb_80r6", XED_IFORM_XOR_MEMb_IMMb_80r6}, +{"XOR_MEMb_IMMb_82r6", XED_IFORM_XOR_MEMb_IMMb_82r6}, +{"XOR_MEMv_GPRv", XED_IFORM_XOR_MEMv_GPRv}, +{"XOR_MEMv_IMMb", XED_IFORM_XOR_MEMv_IMMb}, +{"XOR_MEMv_IMMz", XED_IFORM_XOR_MEMv_IMMz}, +{"XOR_OrAX_IMMz", XED_IFORM_XOR_OrAX_IMMz}, +{"XORPD_XMMxuq_MEMxuq", XED_IFORM_XORPD_XMMxuq_MEMxuq}, +{"XORPD_XMMxuq_XMMxuq", XED_IFORM_XORPD_XMMxuq_XMMxuq}, +{"XORPS_XMMxud_MEMxud", XED_IFORM_XORPS_XMMxud_MEMxud}, +{"XORPS_XMMxud_XMMxud", XED_IFORM_XORPS_XMMxud_XMMxud}, +{"XOR_LOCK_MEMb_GPR8", XED_IFORM_XOR_LOCK_MEMb_GPR8}, +{"XOR_LOCK_MEMb_IMMb_80r6", XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6}, +{"XOR_LOCK_MEMb_IMMb_82r6", XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6}, +{"XOR_LOCK_MEMv_GPRv", XED_IFORM_XOR_LOCK_MEMv_GPRv}, +{"XOR_LOCK_MEMv_IMMb", XED_IFORM_XOR_LOCK_MEMv_IMMb}, +{"XOR_LOCK_MEMv_IMMz", XED_IFORM_XOR_LOCK_MEMv_IMMz}, +{"XRESLDTRK", XED_IFORM_XRESLDTRK}, +{"XRSTOR_MEMmxsave", XED_IFORM_XRSTOR_MEMmxsave}, +{"XRSTOR64_MEMmxsave", XED_IFORM_XRSTOR64_MEMmxsave}, +{"XRSTORS_MEMmxsave", XED_IFORM_XRSTORS_MEMmxsave}, +{"XRSTORS64_MEMmxsave", XED_IFORM_XRSTORS64_MEMmxsave}, +{"XSAVE_MEMmxsave", XED_IFORM_XSAVE_MEMmxsave}, +{"XSAVE64_MEMmxsave", XED_IFORM_XSAVE64_MEMmxsave}, +{"XSAVEC_MEMmxsave", XED_IFORM_XSAVEC_MEMmxsave}, +{"XSAVEC64_MEMmxsave", XED_IFORM_XSAVEC64_MEMmxsave}, +{"XSAVEOPT_MEMmxsave", XED_IFORM_XSAVEOPT_MEMmxsave}, +{"XSAVEOPT64_MEMmxsave", XED_IFORM_XSAVEOPT64_MEMmxsave}, +{"XSAVES_MEMmxsave", XED_IFORM_XSAVES_MEMmxsave}, +{"XSAVES64_MEMmxsave", XED_IFORM_XSAVES64_MEMmxsave}, +{"XSETBV", XED_IFORM_XSETBV}, +{"XSTORE", XED_IFORM_XSTORE}, +{"XSUSLDTRK", XED_IFORM_XSUSLDTRK}, +{"XTEST", XED_IFORM_XTEST}, +{"LAST", XED_IFORM_LAST}, +{0, XED_IFORM_LAST}, +}; + + +xed_iform_enum_t str2xed_iform_enum_t(const char* s) +{ + const name_table_xed_iform_enum_t* p = name_array_xed_iform_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_IFORM_INVALID; +} + + +const char* xed_iform_enum_t2str(const xed_iform_enum_t p) +{ + xed_iform_enum_t type_idx = p; + if ( p > XED_IFORM_LAST) type_idx = XED_IFORM_LAST; + return name_array_xed_iform_enum_t[type_idx].name; +} + +xed_iform_enum_t xed_iform_enum_t_last(void) { + return XED_IFORM_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_IFORM_INVALID: + case XED_IFORM_AAA: + case XED_IFORM_AAD_IMMb: + case XED_IFORM_AAM_IMMb: + case XED_IFORM_AAS: + case XED_IFORM_ADC_AL_IMMb: + case XED_IFORM_ADC_GPR8_GPR8_10: + case XED_IFORM_ADC_GPR8_GPR8_12: + case XED_IFORM_ADC_GPR8_IMMb_80r2: + case XED_IFORM_ADC_GPR8_IMMb_82r2: + case XED_IFORM_ADC_GPR8_MEMb: + case XED_IFORM_ADC_GPRv_GPRv_11: + case XED_IFORM_ADC_GPRv_GPRv_13: + case XED_IFORM_ADC_GPRv_IMMb: + case XED_IFORM_ADC_GPRv_IMMz: + case XED_IFORM_ADC_GPRv_MEMv: + case XED_IFORM_ADC_MEMb_GPR8: + case XED_IFORM_ADC_MEMb_IMMb_80r2: + case XED_IFORM_ADC_MEMb_IMMb_82r2: + case XED_IFORM_ADC_MEMv_GPRv: + case XED_IFORM_ADC_MEMv_IMMb: + case XED_IFORM_ADC_MEMv_IMMz: + case XED_IFORM_ADC_OrAX_IMMz: + case XED_IFORM_ADCX_GPR32d_GPR32d: + case XED_IFORM_ADCX_GPR32d_MEMd: + case XED_IFORM_ADCX_GPR64q_GPR64q: + case XED_IFORM_ADCX_GPR64q_MEMq: + case XED_IFORM_ADC_LOCK_MEMb_GPR8: + case XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2: + case XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2: + case XED_IFORM_ADC_LOCK_MEMv_GPRv: + case XED_IFORM_ADC_LOCK_MEMv_IMMb: + case XED_IFORM_ADC_LOCK_MEMv_IMMz: + case XED_IFORM_ADD_AL_IMMb: + case XED_IFORM_ADD_GPR8_GPR8_00: + case XED_IFORM_ADD_GPR8_GPR8_02: + case XED_IFORM_ADD_GPR8_IMMb_80r0: + case XED_IFORM_ADD_GPR8_IMMb_82r0: + case XED_IFORM_ADD_GPR8_MEMb: + case XED_IFORM_ADD_GPRv_GPRv_01: + case XED_IFORM_ADD_GPRv_GPRv_03: + case XED_IFORM_ADD_GPRv_IMMb: + case XED_IFORM_ADD_GPRv_IMMz: + case XED_IFORM_ADD_GPRv_MEMv: + case XED_IFORM_ADD_MEMb_GPR8: + case XED_IFORM_ADD_MEMb_IMMb_80r0: + case XED_IFORM_ADD_MEMb_IMMb_82r0: + case XED_IFORM_ADD_MEMv_GPRv: + case XED_IFORM_ADD_MEMv_IMMb: + case XED_IFORM_ADD_MEMv_IMMz: + case XED_IFORM_ADD_OrAX_IMMz: + case XED_IFORM_ADDPD_XMMpd_MEMpd: + case XED_IFORM_ADDPD_XMMpd_XMMpd: + case XED_IFORM_ADDPS_XMMps_MEMps: + case XED_IFORM_ADDPS_XMMps_XMMps: + case XED_IFORM_ADDSD_XMMsd_MEMsd: + case XED_IFORM_ADDSD_XMMsd_XMMsd: + case XED_IFORM_ADDSS_XMMss_MEMss: + case XED_IFORM_ADDSS_XMMss_XMMss: + case XED_IFORM_ADDSUBPD_XMMpd_MEMpd: + case XED_IFORM_ADDSUBPD_XMMpd_XMMpd: + case XED_IFORM_ADDSUBPS_XMMps_MEMps: + case XED_IFORM_ADDSUBPS_XMMps_XMMps: + case XED_IFORM_ADD_LOCK_MEMb_GPR8: + case XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0: + case XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0: + case XED_IFORM_ADD_LOCK_MEMv_GPRv: + case XED_IFORM_ADD_LOCK_MEMv_IMMb: + case XED_IFORM_ADD_LOCK_MEMv_IMMz: + case XED_IFORM_ADOX_GPR32d_GPR32d: + case XED_IFORM_ADOX_GPR32d_MEMd: + case XED_IFORM_ADOX_GPR64q_GPR64q: + case XED_IFORM_ADOX_GPR64q_MEMq: + case XED_IFORM_AESDEC_XMMdq_MEMdq: + case XED_IFORM_AESDEC_XMMdq_XMMdq: + case XED_IFORM_AESDEC128KL_XMMu8_MEMu8: + case XED_IFORM_AESDEC256KL_XMMu8_MEMu8: + case XED_IFORM_AESDECLAST_XMMdq_MEMdq: + case XED_IFORM_AESDECLAST_XMMdq_XMMdq: + case XED_IFORM_AESDECWIDE128KL_MEMu8: + case XED_IFORM_AESDECWIDE256KL_MEMu8: + case XED_IFORM_AESENC_XMMdq_MEMdq: + case XED_IFORM_AESENC_XMMdq_XMMdq: + case XED_IFORM_AESENC128KL_XMMu8_MEMu8: + case XED_IFORM_AESENC256KL_XMMu8_MEMu8: + case XED_IFORM_AESENCLAST_XMMdq_MEMdq: + case XED_IFORM_AESENCLAST_XMMdq_XMMdq: + case XED_IFORM_AESENCWIDE128KL_MEMu8: + case XED_IFORM_AESENCWIDE256KL_MEMu8: + case XED_IFORM_AESIMC_XMMdq_MEMdq: + case XED_IFORM_AESIMC_XMMdq_XMMdq: + case XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb: + case XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb: + case XED_IFORM_AND_AL_IMMb: + case XED_IFORM_AND_GPR8_GPR8_20: + case XED_IFORM_AND_GPR8_GPR8_22: + case XED_IFORM_AND_GPR8_IMMb_80r4: + case XED_IFORM_AND_GPR8_IMMb_82r4: + case XED_IFORM_AND_GPR8_MEMb: + case XED_IFORM_AND_GPRv_GPRv_21: + case XED_IFORM_AND_GPRv_GPRv_23: + case XED_IFORM_AND_GPRv_IMMb: + case XED_IFORM_AND_GPRv_IMMz: + case XED_IFORM_AND_GPRv_MEMv: + case XED_IFORM_AND_MEMb_GPR8: + case XED_IFORM_AND_MEMb_IMMb_80r4: + case XED_IFORM_AND_MEMb_IMMb_82r4: + case XED_IFORM_AND_MEMv_GPRv: + case XED_IFORM_AND_MEMv_IMMb: + case XED_IFORM_AND_MEMv_IMMz: + case XED_IFORM_AND_OrAX_IMMz: + case XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd: + case XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq: + case XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_ANDNPD_XMMxuq_MEMxuq: + case XED_IFORM_ANDNPD_XMMxuq_XMMxuq: + case XED_IFORM_ANDNPS_XMMxud_MEMxud: + case XED_IFORM_ANDNPS_XMMxud_XMMxud: + case XED_IFORM_ANDPD_XMMxuq_MEMxuq: + case XED_IFORM_ANDPD_XMMxuq_XMMxuq: + case XED_IFORM_ANDPS_XMMxud_MEMxud: + case XED_IFORM_ANDPS_XMMxud_XMMxud: + case XED_IFORM_AND_LOCK_MEMb_GPR8: + case XED_IFORM_AND_LOCK_MEMb_IMMb_80r4: + case XED_IFORM_AND_LOCK_MEMb_IMMb_82r4: + case XED_IFORM_AND_LOCK_MEMv_GPRv: + case XED_IFORM_AND_LOCK_MEMv_IMMb: + case XED_IFORM_AND_LOCK_MEMv_IMMz: + case XED_IFORM_ARPL_GPR16_GPR16: + case XED_IFORM_ARPL_MEMw_GPR16: + case XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d: + case XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q: + case XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd: + case XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd: + case XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd: + case XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd: + case XED_IFORM_BLCFILL_VGPR32d_MEMd: + case XED_IFORM_BLCFILL_VGPR32d_VGPR32d: + case XED_IFORM_BLCFILL_VGPRyy_MEMy: + case XED_IFORM_BLCFILL_VGPRyy_VGPRyy: + case XED_IFORM_BLCI_VGPR32d_MEMd: + case XED_IFORM_BLCI_VGPR32d_VGPR32d: + case XED_IFORM_BLCI_VGPRyy_MEMy: + case XED_IFORM_BLCI_VGPRyy_VGPRyy: + case XED_IFORM_BLCIC_VGPR32d_MEMd: + case XED_IFORM_BLCIC_VGPR32d_VGPR32d: + case XED_IFORM_BLCIC_VGPRyy_MEMy: + case XED_IFORM_BLCIC_VGPRyy_VGPRyy: + case XED_IFORM_BLCMSK_VGPR32d_MEMd: + case XED_IFORM_BLCMSK_VGPR32d_VGPR32d: + case XED_IFORM_BLCMSK_VGPRyy_MEMy: + case XED_IFORM_BLCMSK_VGPRyy_VGPRyy: + case XED_IFORM_BLCS_VGPR32d_MEMd: + case XED_IFORM_BLCS_VGPR32d_VGPR32d: + case XED_IFORM_BLCS_VGPRyy_MEMy: + case XED_IFORM_BLCS_VGPRyy_VGPRyy: + case XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb: + case XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb: + case XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb: + case XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb: + case XED_IFORM_BLENDVPD_XMMdq_MEMdq: + case XED_IFORM_BLENDVPD_XMMdq_XMMdq: + case XED_IFORM_BLENDVPS_XMMdq_MEMdq: + case XED_IFORM_BLENDVPS_XMMdq_XMMdq: + case XED_IFORM_BLSFILL_VGPR32d_MEMd: + case XED_IFORM_BLSFILL_VGPR32d_VGPR32d: + case XED_IFORM_BLSFILL_VGPRyy_MEMy: + case XED_IFORM_BLSFILL_VGPRyy_VGPRyy: + case XED_IFORM_BLSI_VGPR32d_MEMd: + case XED_IFORM_BLSI_VGPR32d_VGPR32d: + case XED_IFORM_BLSI_VGPR64q_MEMq: + case XED_IFORM_BLSI_VGPR64q_VGPR64q: + case XED_IFORM_BLSIC_VGPR32d_MEMd: + case XED_IFORM_BLSIC_VGPR32d_VGPR32d: + case XED_IFORM_BLSIC_VGPRyy_MEMy: + case XED_IFORM_BLSIC_VGPRyy_VGPRyy: + case XED_IFORM_BLSMSK_VGPR32d_MEMd: + case XED_IFORM_BLSMSK_VGPR32d_VGPR32d: + case XED_IFORM_BLSMSK_VGPR64q_MEMq: + case XED_IFORM_BLSMSK_VGPR64q_VGPR64q: + case XED_IFORM_BLSR_VGPR32d_MEMd: + case XED_IFORM_BLSR_VGPR32d_VGPR32d: + case XED_IFORM_BLSR_VGPR64q_MEMq: + case XED_IFORM_BLSR_VGPR64q_VGPR64q: + case XED_IFORM_BNDCL_BND_AGEN: + case XED_IFORM_BNDCL_BND_GPR32: + case XED_IFORM_BNDCL_BND_GPR64: + case XED_IFORM_BNDCN_BND_AGEN: + case XED_IFORM_BNDCN_BND_GPR32: + case XED_IFORM_BNDCN_BND_GPR64: + case XED_IFORM_BNDCU_BND_AGEN: + case XED_IFORM_BNDCU_BND_GPR32: + case XED_IFORM_BNDCU_BND_GPR64: + case XED_IFORM_BNDLDX_BND_MEMbnd32: + case XED_IFORM_BNDLDX_BND_MEMbnd64: + case XED_IFORM_BNDMK_BND_AGEN: + case XED_IFORM_BNDMOV_BND_BND: + case XED_IFORM_BNDMOV_BND_MEMdq: + case XED_IFORM_BNDMOV_BND_MEMq: + case XED_IFORM_BNDMOV_MEMdq_BND: + case XED_IFORM_BNDMOV_MEMq_BND: + case XED_IFORM_BNDSTX_MEMbnd32_BND: + case XED_IFORM_BNDSTX_MEMbnd64_BND: + case XED_IFORM_BOUND_GPRv_MEMa16: + case XED_IFORM_BOUND_GPRv_MEMa32: + case XED_IFORM_BSF_GPRv_GPRv: + case XED_IFORM_BSF_GPRv_MEMv: + case XED_IFORM_BSR_GPRv_GPRv: + case XED_IFORM_BSR_GPRv_MEMv: + case XED_IFORM_BSWAP_GPRv: + case XED_IFORM_BT_GPRv_GPRv: + case XED_IFORM_BT_GPRv_IMMb: + case XED_IFORM_BT_MEMv_GPRv: + case XED_IFORM_BT_MEMv_IMMb: + case XED_IFORM_BTC_GPRv_GPRv: + case XED_IFORM_BTC_GPRv_IMMb: + case XED_IFORM_BTC_MEMv_GPRv: + case XED_IFORM_BTC_MEMv_IMMb: + case XED_IFORM_BTC_LOCK_MEMv_GPRv: + case XED_IFORM_BTC_LOCK_MEMv_IMMb: + case XED_IFORM_BTR_GPRv_GPRv: + case XED_IFORM_BTR_GPRv_IMMb: + case XED_IFORM_BTR_MEMv_GPRv: + case XED_IFORM_BTR_MEMv_IMMb: + case XED_IFORM_BTR_LOCK_MEMv_GPRv: + case XED_IFORM_BTR_LOCK_MEMv_IMMb: + case XED_IFORM_BTS_GPRv_GPRv: + case XED_IFORM_BTS_GPRv_IMMb: + case XED_IFORM_BTS_MEMv_GPRv: + case XED_IFORM_BTS_MEMv_IMMb: + case XED_IFORM_BTS_LOCK_MEMv_GPRv: + case XED_IFORM_BTS_LOCK_MEMv_IMMb: + case XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d: + case XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q: + case XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_CALL_FAR_MEMp2: + case XED_IFORM_CALL_FAR_PTRp_IMMw: + case XED_IFORM_CALL_NEAR_GPRv: + case XED_IFORM_CALL_NEAR_MEMv: + case XED_IFORM_CALL_NEAR_RELBRd: + case XED_IFORM_CALL_NEAR_RELBRz: + case XED_IFORM_CBW: + case XED_IFORM_CDQ: + case XED_IFORM_CDQE: + case XED_IFORM_CLAC: + case XED_IFORM_CLC: + case XED_IFORM_CLD: + case XED_IFORM_CLDEMOTE_MEMu8: + case XED_IFORM_CLFLUSH_MEMmprefetch: + case XED_IFORM_CLFLUSHOPT_MEMmprefetch: + case XED_IFORM_CLGI: + case XED_IFORM_CLI: + case XED_IFORM_CLRSSBSY_MEMu64: + case XED_IFORM_CLTS: + case XED_IFORM_CLUI: + case XED_IFORM_CLWB_MEMmprefetch: + case XED_IFORM_CLZERO: + case XED_IFORM_CMC: + case XED_IFORM_CMOVB_GPRv_GPRv: + case XED_IFORM_CMOVB_GPRv_MEMv: + case XED_IFORM_CMOVBE_GPRv_GPRv: + case XED_IFORM_CMOVBE_GPRv_MEMv: + case XED_IFORM_CMOVL_GPRv_GPRv: + case XED_IFORM_CMOVL_GPRv_MEMv: + case XED_IFORM_CMOVLE_GPRv_GPRv: + case XED_IFORM_CMOVLE_GPRv_MEMv: + case XED_IFORM_CMOVNB_GPRv_GPRv: + case XED_IFORM_CMOVNB_GPRv_MEMv: + case XED_IFORM_CMOVNBE_GPRv_GPRv: + case XED_IFORM_CMOVNBE_GPRv_MEMv: + case XED_IFORM_CMOVNL_GPRv_GPRv: + case XED_IFORM_CMOVNL_GPRv_MEMv: + case XED_IFORM_CMOVNLE_GPRv_GPRv: + case XED_IFORM_CMOVNLE_GPRv_MEMv: + case XED_IFORM_CMOVNO_GPRv_GPRv: + case XED_IFORM_CMOVNO_GPRv_MEMv: + case XED_IFORM_CMOVNP_GPRv_GPRv: + case XED_IFORM_CMOVNP_GPRv_MEMv: + case XED_IFORM_CMOVNS_GPRv_GPRv: + case XED_IFORM_CMOVNS_GPRv_MEMv: + case XED_IFORM_CMOVNZ_GPRv_GPRv: + case XED_IFORM_CMOVNZ_GPRv_MEMv: + case XED_IFORM_CMOVO_GPRv_GPRv: + case XED_IFORM_CMOVO_GPRv_MEMv: + case XED_IFORM_CMOVP_GPRv_GPRv: + case XED_IFORM_CMOVP_GPRv_MEMv: + case XED_IFORM_CMOVS_GPRv_GPRv: + case XED_IFORM_CMOVS_GPRv_MEMv: + case XED_IFORM_CMOVZ_GPRv_GPRv: + case XED_IFORM_CMOVZ_GPRv_MEMv: + case XED_IFORM_CMP_AL_IMMb: + case XED_IFORM_CMP_GPR8_GPR8_38: + case XED_IFORM_CMP_GPR8_GPR8_3A: + case XED_IFORM_CMP_GPR8_IMMb_80r7: + case XED_IFORM_CMP_GPR8_IMMb_82r7: + case XED_IFORM_CMP_GPR8_MEMb: + case XED_IFORM_CMP_GPRv_GPRv_39: + case XED_IFORM_CMP_GPRv_GPRv_3B: + case XED_IFORM_CMP_GPRv_IMMb: + case XED_IFORM_CMP_GPRv_IMMz: + case XED_IFORM_CMP_GPRv_MEMv: + case XED_IFORM_CMP_MEMb_GPR8: + case XED_IFORM_CMP_MEMb_IMMb_80r7: + case XED_IFORM_CMP_MEMb_IMMb_82r7: + case XED_IFORM_CMP_MEMv_GPRv: + case XED_IFORM_CMP_MEMv_IMMb: + case XED_IFORM_CMP_MEMv_IMMz: + case XED_IFORM_CMP_OrAX_IMMz: + case XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb: + case XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb: + case XED_IFORM_CMPPS_XMMps_MEMps_IMMb: + case XED_IFORM_CMPPS_XMMps_XMMps_IMMb: + case XED_IFORM_CMPSB: + case XED_IFORM_CMPSD: + case XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb: + case XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb: + case XED_IFORM_CMPSQ: + case XED_IFORM_CMPSS_XMMss_MEMss_IMMb: + case XED_IFORM_CMPSS_XMMss_XMMss_IMMb: + case XED_IFORM_CMPSW: + case XED_IFORM_CMPXCHG_GPR8_GPR8: + case XED_IFORM_CMPXCHG_GPRv_GPRv: + case XED_IFORM_CMPXCHG_MEMb_GPR8: + case XED_IFORM_CMPXCHG_MEMv_GPRv: + case XED_IFORM_CMPXCHG16B_MEMdq: + case XED_IFORM_CMPXCHG16B_LOCK_MEMdq: + case XED_IFORM_CMPXCHG8B_MEMq: + case XED_IFORM_CMPXCHG8B_LOCK_MEMq: + case XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8: + case XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv: + case XED_IFORM_COMISD_XMMsd_MEMsd: + case XED_IFORM_COMISD_XMMsd_XMMsd: + case XED_IFORM_COMISS_XMMss_MEMss: + case XED_IFORM_COMISS_XMMss_XMMss: + case XED_IFORM_CPUID: + case XED_IFORM_CQO: + case XED_IFORM_CRC32_GPRyy_GPR8b: + case XED_IFORM_CRC32_GPRyy_GPRv: + case XED_IFORM_CRC32_GPRyy_MEMb: + case XED_IFORM_CRC32_GPRyy_MEMv: + case XED_IFORM_CVTDQ2PD_XMMpd_MEMq: + case XED_IFORM_CVTDQ2PD_XMMpd_XMMq: + case XED_IFORM_CVTDQ2PS_XMMps_MEMdq: + case XED_IFORM_CVTDQ2PS_XMMps_XMMdq: + case XED_IFORM_CVTPD2DQ_XMMdq_MEMpd: + case XED_IFORM_CVTPD2DQ_XMMdq_XMMpd: + case XED_IFORM_CVTPD2PI_MMXq_MEMpd: + case XED_IFORM_CVTPD2PI_MMXq_XMMpd: + case XED_IFORM_CVTPD2PS_XMMps_MEMpd: + case XED_IFORM_CVTPD2PS_XMMps_XMMpd: + case XED_IFORM_CVTPI2PD_XMMpd_MEMq: + case XED_IFORM_CVTPI2PD_XMMpd_MMXq: + case XED_IFORM_CVTPI2PS_XMMq_MEMq: + case XED_IFORM_CVTPI2PS_XMMq_MMXq: + case XED_IFORM_CVTPS2DQ_XMMdq_MEMps: + case XED_IFORM_CVTPS2DQ_XMMdq_XMMps: + case XED_IFORM_CVTPS2PD_XMMpd_MEMq: + case XED_IFORM_CVTPS2PD_XMMpd_XMMq: + case XED_IFORM_CVTPS2PI_MMXq_MEMq: + case XED_IFORM_CVTPS2PI_MMXq_XMMq: + case XED_IFORM_CVTSD2SI_GPR32d_MEMsd: + case XED_IFORM_CVTSD2SI_GPR32d_XMMsd: + case XED_IFORM_CVTSD2SI_GPR64q_MEMsd: + case XED_IFORM_CVTSD2SI_GPR64q_XMMsd: + case XED_IFORM_CVTSD2SS_XMMss_MEMsd: + case XED_IFORM_CVTSD2SS_XMMss_XMMsd: + case XED_IFORM_CVTSI2SD_XMMsd_GPR32d: + case XED_IFORM_CVTSI2SD_XMMsd_GPR64q: + case XED_IFORM_CVTSI2SD_XMMsd_MEMd: + case XED_IFORM_CVTSI2SD_XMMsd_MEMq: + case XED_IFORM_CVTSI2SS_XMMss_GPR32d: + case XED_IFORM_CVTSI2SS_XMMss_GPR64q: + case XED_IFORM_CVTSI2SS_XMMss_MEMd: + case XED_IFORM_CVTSI2SS_XMMss_MEMq: + case XED_IFORM_CVTSS2SD_XMMsd_MEMss: + case XED_IFORM_CVTSS2SD_XMMsd_XMMss: + case XED_IFORM_CVTSS2SI_GPR32d_MEMss: + case XED_IFORM_CVTSS2SI_GPR32d_XMMss: + case XED_IFORM_CVTSS2SI_GPR64q_MEMss: + case XED_IFORM_CVTSS2SI_GPR64q_XMMss: + case XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd: + case XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd: + case XED_IFORM_CVTTPD2PI_MMXq_MEMpd: + case XED_IFORM_CVTTPD2PI_MMXq_XMMpd: + case XED_IFORM_CVTTPS2DQ_XMMdq_MEMps: + case XED_IFORM_CVTTPS2DQ_XMMdq_XMMps: + case XED_IFORM_CVTTPS2PI_MMXq_MEMq: + case XED_IFORM_CVTTPS2PI_MMXq_XMMq: + case XED_IFORM_CVTTSD2SI_GPR32d_MEMsd: + case XED_IFORM_CVTTSD2SI_GPR32d_XMMsd: + case XED_IFORM_CVTTSD2SI_GPR64q_MEMsd: + case XED_IFORM_CVTTSD2SI_GPR64q_XMMsd: + case XED_IFORM_CVTTSS2SI_GPR32d_MEMss: + case XED_IFORM_CVTTSS2SI_GPR32d_XMMss: + case XED_IFORM_CVTTSS2SI_GPR64q_MEMss: + case XED_IFORM_CVTTSS2SI_GPR64q_XMMss: + case XED_IFORM_CWD: + case XED_IFORM_CWDE: + case XED_IFORM_DAA: + case XED_IFORM_DAS: + case XED_IFORM_DEC_GPR8: + case XED_IFORM_DEC_GPRv_48: + case XED_IFORM_DEC_GPRv_FFr1: + case XED_IFORM_DEC_MEMb: + case XED_IFORM_DEC_MEMv: + case XED_IFORM_DEC_LOCK_MEMb: + case XED_IFORM_DEC_LOCK_MEMv: + case XED_IFORM_DIV_GPR8: + case XED_IFORM_DIV_GPRv: + case XED_IFORM_DIV_MEMb: + case XED_IFORM_DIV_MEMv: + case XED_IFORM_DIVPD_XMMpd_MEMpd: + case XED_IFORM_DIVPD_XMMpd_XMMpd: + case XED_IFORM_DIVPS_XMMps_MEMps: + case XED_IFORM_DIVPS_XMMps_XMMps: + case XED_IFORM_DIVSD_XMMsd_MEMsd: + case XED_IFORM_DIVSD_XMMsd_XMMsd: + case XED_IFORM_DIVSS_XMMss_MEMss: + case XED_IFORM_DIVSS_XMMss_XMMss: + case XED_IFORM_DPPD_XMMdq_MEMdq_IMMb: + case XED_IFORM_DPPD_XMMdq_XMMdq_IMMb: + case XED_IFORM_DPPS_XMMdq_MEMdq_IMMb: + case XED_IFORM_DPPS_XMMdq_XMMdq_IMMb: + case XED_IFORM_EMMS: + case XED_IFORM_ENCLS: + case XED_IFORM_ENCLU: + case XED_IFORM_ENCLV: + case XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8: + case XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8: + case XED_IFORM_ENDBR32: + case XED_IFORM_ENDBR64: + case XED_IFORM_ENQCMD_GPRa_MEMu32: + case XED_IFORM_ENQCMDS_GPRa_MEMu32: + case XED_IFORM_ENTER_IMMw_IMMb: + case XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb: + case XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb: + case XED_IFORM_EXTRQ_XMMq_IMMb_IMMb: + case XED_IFORM_EXTRQ_XMMq_XMMdq: + case XED_IFORM_F2XM1: + case XED_IFORM_FABS: + case XED_IFORM_FADD_ST0_MEMm64real: + case XED_IFORM_FADD_ST0_MEMmem32real: + case XED_IFORM_FADD_ST0_X87: + case XED_IFORM_FADD_X87_ST0: + case XED_IFORM_FADDP_X87_ST0: + case XED_IFORM_FBLD_ST0_MEMmem80dec: + case XED_IFORM_FBSTP_MEMmem80dec_ST0: + case XED_IFORM_FCHS: + case XED_IFORM_FCMOVB_ST0_X87: + case XED_IFORM_FCMOVBE_ST0_X87: + case XED_IFORM_FCMOVE_ST0_X87: + case XED_IFORM_FCMOVNB_ST0_X87: + case XED_IFORM_FCMOVNBE_ST0_X87: + case XED_IFORM_FCMOVNE_ST0_X87: + case XED_IFORM_FCMOVNU_ST0_X87: + case XED_IFORM_FCMOVU_ST0_X87: + case XED_IFORM_FCOM_ST0_MEMm64real: + case XED_IFORM_FCOM_ST0_MEMmem32real: + case XED_IFORM_FCOM_ST0_X87: + case XED_IFORM_FCOM_ST0_X87_DCD0: + case XED_IFORM_FCOMI_ST0_X87: + case XED_IFORM_FCOMIP_ST0_X87: + case XED_IFORM_FCOMP_ST0_MEMm64real: + case XED_IFORM_FCOMP_ST0_MEMmem32real: + case XED_IFORM_FCOMP_ST0_X87: + case XED_IFORM_FCOMP_ST0_X87_DCD1: + case XED_IFORM_FCOMP_ST0_X87_DED0: + case XED_IFORM_FCOMPP: + case XED_IFORM_FCOS: + case XED_IFORM_FDECSTP: + case XED_IFORM_FDISI8087_NOP: + case XED_IFORM_FDIV_ST0_MEMm64real: + case XED_IFORM_FDIV_ST0_MEMmem32real: + case XED_IFORM_FDIV_ST0_X87: + case XED_IFORM_FDIV_X87_ST0: + case XED_IFORM_FDIVP_X87_ST0: + case XED_IFORM_FDIVR_ST0_MEMm64real: + case XED_IFORM_FDIVR_ST0_MEMmem32real: + case XED_IFORM_FDIVR_ST0_X87: + case XED_IFORM_FDIVR_X87_ST0: + case XED_IFORM_FDIVRP_X87_ST0: + case XED_IFORM_FEMMS: + case XED_IFORM_FENI8087_NOP: + case XED_IFORM_FFREE_X87: + case XED_IFORM_FFREEP_X87: + case XED_IFORM_FIADD_ST0_MEMmem16int: + case XED_IFORM_FIADD_ST0_MEMmem32int: + case XED_IFORM_FICOM_ST0_MEMmem16int: + case XED_IFORM_FICOM_ST0_MEMmem32int: + case XED_IFORM_FICOMP_ST0_MEMmem16int: + case XED_IFORM_FICOMP_ST0_MEMmem32int: + case XED_IFORM_FIDIV_ST0_MEMmem16int: + case XED_IFORM_FIDIV_ST0_MEMmem32int: + case XED_IFORM_FIDIVR_ST0_MEMmem16int: + case XED_IFORM_FIDIVR_ST0_MEMmem32int: + case XED_IFORM_FILD_ST0_MEMm64int: + case XED_IFORM_FILD_ST0_MEMmem16int: + case XED_IFORM_FILD_ST0_MEMmem32int: + case XED_IFORM_FIMUL_ST0_MEMmem16int: + case XED_IFORM_FIMUL_ST0_MEMmem32int: + case XED_IFORM_FINCSTP: + case XED_IFORM_FIST_MEMmem16int_ST0: + case XED_IFORM_FIST_MEMmem32int_ST0: + case XED_IFORM_FISTP_MEMm64int_ST0: + case XED_IFORM_FISTP_MEMmem16int_ST0: + case XED_IFORM_FISTP_MEMmem32int_ST0: + case XED_IFORM_FISTTP_MEMm64int_ST0: + case XED_IFORM_FISTTP_MEMmem16int_ST0: + case XED_IFORM_FISTTP_MEMmem32int_ST0: + case XED_IFORM_FISUB_ST0_MEMmem16int: + case XED_IFORM_FISUB_ST0_MEMmem32int: + case XED_IFORM_FISUBR_ST0_MEMmem16int: + case XED_IFORM_FISUBR_ST0_MEMmem32int: + case XED_IFORM_FLD_ST0_MEMm64real: + case XED_IFORM_FLD_ST0_MEMmem32real: + case XED_IFORM_FLD_ST0_MEMmem80real: + case XED_IFORM_FLD_ST0_X87: + case XED_IFORM_FLD1: + case XED_IFORM_FLDCW_MEMmem16: + case XED_IFORM_FLDENV_MEMmem14: + case XED_IFORM_FLDENV_MEMmem28: + case XED_IFORM_FLDL2E: + case XED_IFORM_FLDL2T: + case XED_IFORM_FLDLG2: + case XED_IFORM_FLDLN2: + case XED_IFORM_FLDPI: + case XED_IFORM_FLDZ: + case XED_IFORM_FMUL_ST0_MEMm64real: + case XED_IFORM_FMUL_ST0_MEMmem32real: + case XED_IFORM_FMUL_ST0_X87: + case XED_IFORM_FMUL_X87_ST0: + case XED_IFORM_FMULP_X87_ST0: + case XED_IFORM_FNCLEX: + case XED_IFORM_FNINIT: + case XED_IFORM_FNOP: + case XED_IFORM_FNSAVE_MEMmem108: + case XED_IFORM_FNSAVE_MEMmem94: + case XED_IFORM_FNSTCW_MEMmem16: + case XED_IFORM_FNSTENV_MEMmem14: + case XED_IFORM_FNSTENV_MEMmem28: + case XED_IFORM_FNSTSW_AX: + case XED_IFORM_FNSTSW_MEMmem16: + case XED_IFORM_FPATAN: + case XED_IFORM_FPREM: + case XED_IFORM_FPREM1: + case XED_IFORM_FPTAN: + case XED_IFORM_FRNDINT: + case XED_IFORM_FRSTOR_MEMmem108: + case XED_IFORM_FRSTOR_MEMmem94: + case XED_IFORM_FSCALE: + case XED_IFORM_FSETPM287_NOP: + case XED_IFORM_FSIN: + case XED_IFORM_FSINCOS: + case XED_IFORM_FSQRT: + case XED_IFORM_FST_MEMm64real_ST0: + case XED_IFORM_FST_MEMmem32real_ST0: + case XED_IFORM_FST_X87_ST0: + case XED_IFORM_FSTP_MEMm64real_ST0: + case XED_IFORM_FSTP_MEMmem32real_ST0: + case XED_IFORM_FSTP_MEMmem80real_ST0: + case XED_IFORM_FSTP_X87_ST0: + case XED_IFORM_FSTP_X87_ST0_DFD0: + case XED_IFORM_FSTP_X87_ST0_DFD1: + case XED_IFORM_FSTPNCE_X87_ST0: + case XED_IFORM_FSUB_ST0_MEMm64real: + case XED_IFORM_FSUB_ST0_MEMmem32real: + case XED_IFORM_FSUB_ST0_X87: + case XED_IFORM_FSUB_X87_ST0: + case XED_IFORM_FSUBP_X87_ST0: + case XED_IFORM_FSUBR_ST0_MEMm64real: + case XED_IFORM_FSUBR_ST0_MEMmem32real: + case XED_IFORM_FSUBR_ST0_X87: + case XED_IFORM_FSUBR_X87_ST0: + case XED_IFORM_FSUBRP_X87_ST0: + case XED_IFORM_FTST: + case XED_IFORM_FUCOM_ST0_X87: + case XED_IFORM_FUCOMI_ST0_X87: + case XED_IFORM_FUCOMIP_ST0_X87: + case XED_IFORM_FUCOMP_ST0_X87: + case XED_IFORM_FUCOMPP: + case XED_IFORM_FWAIT: + case XED_IFORM_FXAM: + case XED_IFORM_FXCH_ST0_X87: + case XED_IFORM_FXCH_ST0_X87_DDC1: + case XED_IFORM_FXCH_ST0_X87_DFC1: + case XED_IFORM_FXRSTOR_MEMmfpxenv: + case XED_IFORM_FXRSTOR64_MEMmfpxenv: + case XED_IFORM_FXSAVE_MEMmfpxenv: + case XED_IFORM_FXSAVE64_MEMmfpxenv: + case XED_IFORM_FXTRACT: + case XED_IFORM_FYL2X: + case XED_IFORM_FYL2XP1: + case XED_IFORM_GETSEC: + case XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8: + case XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8: + case XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8: + case XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8: + case XED_IFORM_GF2P8MULB_XMMu8_MEMu8: + case XED_IFORM_GF2P8MULB_XMMu8_XMMu8: + case XED_IFORM_HADDPD_XMMpd_MEMpd: + case XED_IFORM_HADDPD_XMMpd_XMMpd: + case XED_IFORM_HADDPS_XMMps_MEMps: + case XED_IFORM_HADDPS_XMMps_XMMps: + case XED_IFORM_HLT: + case XED_IFORM_HRESET_IMM8: + case XED_IFORM_HSUBPD_XMMpd_MEMpd: + case XED_IFORM_HSUBPD_XMMpd_XMMpd: + case XED_IFORM_HSUBPS_XMMps_MEMps: + case XED_IFORM_HSUBPS_XMMps_XMMps: + case XED_IFORM_IDIV_GPR8: + case XED_IFORM_IDIV_GPRv: + case XED_IFORM_IDIV_MEMb: + case XED_IFORM_IDIV_MEMv: + case XED_IFORM_IMUL_GPR8: + case XED_IFORM_IMUL_GPRv: + case XED_IFORM_IMUL_GPRv_GPRv: + case XED_IFORM_IMUL_GPRv_GPRv_IMMb: + case XED_IFORM_IMUL_GPRv_GPRv_IMMz: + case XED_IFORM_IMUL_GPRv_MEMv: + case XED_IFORM_IMUL_GPRv_MEMv_IMMb: + case XED_IFORM_IMUL_GPRv_MEMv_IMMz: + case XED_IFORM_IMUL_MEMb: + case XED_IFORM_IMUL_MEMv: + case XED_IFORM_IN_AL_DX: + case XED_IFORM_IN_AL_IMMb: + case XED_IFORM_IN_OeAX_DX: + case XED_IFORM_IN_OeAX_IMMb: + case XED_IFORM_INC_GPR8: + case XED_IFORM_INC_GPRv_40: + case XED_IFORM_INC_GPRv_FFr0: + case XED_IFORM_INC_MEMb: + case XED_IFORM_INC_MEMv: + case XED_IFORM_INCSSPD_GPR32u8: + case XED_IFORM_INCSSPQ_GPR64u8: + case XED_IFORM_INC_LOCK_MEMb: + case XED_IFORM_INC_LOCK_MEMv: + case XED_IFORM_INSB: + case XED_IFORM_INSD: + case XED_IFORM_INSERTPS_XMMps_MEMd_IMMb: + case XED_IFORM_INSERTPS_XMMps_XMMps_IMMb: + case XED_IFORM_INSERTQ_XMMq_XMMdq: + case XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb: + case XED_IFORM_INSW: + case XED_IFORM_INT_IMMb: + case XED_IFORM_INT1: + case XED_IFORM_INT3: + case XED_IFORM_INTO: + case XED_IFORM_INVD: + case XED_IFORM_INVEPT_GPR32_MEMdq: + case XED_IFORM_INVEPT_GPR64_MEMdq: + case XED_IFORM_INVLPG_MEMb: + case XED_IFORM_INVLPGA_ArAX_ECX: + case XED_IFORM_INVLPGB_EAX_EDX_ECX: + case XED_IFORM_INVLPGB_RAX_EDX_ECX: + case XED_IFORM_INVPCID_GPR32_MEMdq: + case XED_IFORM_INVPCID_GPR64_MEMdq: + case XED_IFORM_INVVPID_GPR32_MEMdq: + case XED_IFORM_INVVPID_GPR64_MEMdq: + case XED_IFORM_IRET: + case XED_IFORM_IRETD: + case XED_IFORM_IRETQ: + case XED_IFORM_JB_RELBRb: + case XED_IFORM_JB_RELBRd: + case XED_IFORM_JB_RELBRz: + case XED_IFORM_JBE_RELBRb: + case XED_IFORM_JBE_RELBRd: + case XED_IFORM_JBE_RELBRz: + case XED_IFORM_JCXZ_RELBRb: + case XED_IFORM_JECXZ_RELBRb: + case XED_IFORM_JL_RELBRb: + case XED_IFORM_JL_RELBRd: + case XED_IFORM_JL_RELBRz: + case XED_IFORM_JLE_RELBRb: + case XED_IFORM_JLE_RELBRd: + case XED_IFORM_JLE_RELBRz: + case XED_IFORM_JMP_GPRv: + case XED_IFORM_JMP_MEMv: + case XED_IFORM_JMP_RELBRb: + case XED_IFORM_JMP_RELBRd: + case XED_IFORM_JMP_RELBRz: + case XED_IFORM_JMP_FAR_MEMp2: + case XED_IFORM_JMP_FAR_PTRp_IMMw: + case XED_IFORM_JNB_RELBRb: + case XED_IFORM_JNB_RELBRd: + case XED_IFORM_JNB_RELBRz: + case XED_IFORM_JNBE_RELBRb: + case XED_IFORM_JNBE_RELBRd: + case XED_IFORM_JNBE_RELBRz: + case XED_IFORM_JNL_RELBRb: + case XED_IFORM_JNL_RELBRd: + case XED_IFORM_JNL_RELBRz: + case XED_IFORM_JNLE_RELBRb: + case XED_IFORM_JNLE_RELBRd: + case XED_IFORM_JNLE_RELBRz: + case XED_IFORM_JNO_RELBRb: + case XED_IFORM_JNO_RELBRd: + case XED_IFORM_JNO_RELBRz: + case XED_IFORM_JNP_RELBRb: + case XED_IFORM_JNP_RELBRd: + case XED_IFORM_JNP_RELBRz: + case XED_IFORM_JNS_RELBRb: + case XED_IFORM_JNS_RELBRd: + case XED_IFORM_JNS_RELBRz: + case XED_IFORM_JNZ_RELBRb: + case XED_IFORM_JNZ_RELBRd: + case XED_IFORM_JNZ_RELBRz: + case XED_IFORM_JO_RELBRb: + case XED_IFORM_JO_RELBRd: + case XED_IFORM_JO_RELBRz: + case XED_IFORM_JP_RELBRb: + case XED_IFORM_JP_RELBRd: + case XED_IFORM_JP_RELBRz: + case XED_IFORM_JRCXZ_RELBRb: + case XED_IFORM_JS_RELBRb: + case XED_IFORM_JS_RELBRd: + case XED_IFORM_JS_RELBRz: + case XED_IFORM_JZ_RELBRb: + case XED_IFORM_JZ_RELBRd: + case XED_IFORM_JZ_RELBRz: + case XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512: + case XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512: + case XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512: + case XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512: + case XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512: + case XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512: + case XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512: + case XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512: + case XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512: + case XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512: + case XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512: + case XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512: + case XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512: + case XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512: + case XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512: + case XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512: + case XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512: + case XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512: + case XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512: + case XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512: + case XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512: + case XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512: + case XED_IFORM_LAHF: + case XED_IFORM_LAR_GPRv_GPRv: + case XED_IFORM_LAR_GPRv_MEMw: + case XED_IFORM_LDDQU_XMMpd_MEMdq: + case XED_IFORM_LDMXCSR_MEMd: + case XED_IFORM_LDS_GPRz_MEMp: + case XED_IFORM_LDTILECFG_MEM: + case XED_IFORM_LEA_GPRv_AGEN: + case XED_IFORM_LEAVE: + case XED_IFORM_LES_GPRz_MEMp: + case XED_IFORM_LFENCE: + case XED_IFORM_LFS_GPRv_MEMp2: + case XED_IFORM_LGDT_MEMs: + case XED_IFORM_LGDT_MEMs64: + case XED_IFORM_LGS_GPRv_MEMp2: + case XED_IFORM_LIDT_MEMs: + case XED_IFORM_LIDT_MEMs64: + case XED_IFORM_LLDT_GPR16: + case XED_IFORM_LLDT_MEMw: + case XED_IFORM_LLWPCB_VGPRyy: + case XED_IFORM_LMSW_GPR16: + case XED_IFORM_LMSW_MEMw: + case XED_IFORM_LOADIWKEY_XMMu8_XMMu8: + case XED_IFORM_LODSB: + case XED_IFORM_LODSD: + case XED_IFORM_LODSQ: + case XED_IFORM_LODSW: + case XED_IFORM_LOOP_RELBRb: + case XED_IFORM_LOOPE_RELBRb: + case XED_IFORM_LOOPNE_RELBRb: + case XED_IFORM_LSL_GPRv_GPRz: + case XED_IFORM_LSL_GPRv_MEMw: + case XED_IFORM_LSS_GPRv_MEMp2: + case XED_IFORM_LTR_GPR16: + case XED_IFORM_LTR_MEMw: + case XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd: + case XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd: + case XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd: + case XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd: + case XED_IFORM_LZCNT_GPRv_GPRv: + case XED_IFORM_LZCNT_GPRv_MEMv: + case XED_IFORM_MASKMOVDQU_XMMdq_XMMdq: + case XED_IFORM_MASKMOVQ_MMXq_MMXq: + case XED_IFORM_MAXPD_XMMpd_MEMpd: + case XED_IFORM_MAXPD_XMMpd_XMMpd: + case XED_IFORM_MAXPS_XMMps_MEMps: + case XED_IFORM_MAXPS_XMMps_XMMps: + case XED_IFORM_MAXSD_XMMsd_MEMsd: + case XED_IFORM_MAXSD_XMMsd_XMMsd: + case XED_IFORM_MAXSS_XMMss_MEMss: + case XED_IFORM_MAXSS_XMMss_XMMss: + case XED_IFORM_MCOMMIT: + case XED_IFORM_MFENCE: + case XED_IFORM_MINPD_XMMpd_MEMpd: + case XED_IFORM_MINPD_XMMpd_XMMpd: + case XED_IFORM_MINPS_XMMps_MEMps: + case XED_IFORM_MINPS_XMMps_XMMps: + case XED_IFORM_MINSD_XMMsd_MEMsd: + case XED_IFORM_MINSD_XMMsd_XMMsd: + case XED_IFORM_MINSS_XMMss_MEMss: + case XED_IFORM_MINSS_XMMss_XMMss: + case XED_IFORM_MONITOR: + case XED_IFORM_MONITORX: + case XED_IFORM_MOV_AL_MEMb: + case XED_IFORM_MOV_GPR8_GPR8_88: + case XED_IFORM_MOV_GPR8_GPR8_8A: + case XED_IFORM_MOV_GPR8_IMMb_B0: + case XED_IFORM_MOV_GPR8_IMMb_C6r0: + case XED_IFORM_MOV_GPR8_MEMb: + case XED_IFORM_MOV_GPRv_GPRv_89: + case XED_IFORM_MOV_GPRv_GPRv_8B: + case XED_IFORM_MOV_GPRv_IMMv: + case XED_IFORM_MOV_GPRv_IMMz: + case XED_IFORM_MOV_GPRv_MEMv: + case XED_IFORM_MOV_GPRv_SEG: + case XED_IFORM_MOV_MEMb_AL: + case XED_IFORM_MOV_MEMb_GPR8: + case XED_IFORM_MOV_MEMb_IMMb: + case XED_IFORM_MOV_MEMv_GPRv: + case XED_IFORM_MOV_MEMv_IMMz: + case XED_IFORM_MOV_MEMv_OrAX: + case XED_IFORM_MOV_MEMw_SEG: + case XED_IFORM_MOV_OrAX_MEMv: + case XED_IFORM_MOV_SEG_GPR16: + case XED_IFORM_MOV_SEG_MEMw: + case XED_IFORM_MOVAPD_MEMpd_XMMpd: + case XED_IFORM_MOVAPD_XMMpd_MEMpd: + case XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28: + case XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29: + case XED_IFORM_MOVAPS_MEMps_XMMps: + case XED_IFORM_MOVAPS_XMMps_MEMps: + case XED_IFORM_MOVAPS_XMMps_XMMps_0F28: + case XED_IFORM_MOVAPS_XMMps_XMMps_0F29: + case XED_IFORM_MOVBE_GPRv_MEMv: + case XED_IFORM_MOVBE_MEMv_GPRv: + case XED_IFORM_MOVD_GPR32_MMXd: + case XED_IFORM_MOVD_GPR32_XMMd: + case XED_IFORM_MOVD_MEMd_MMXd: + case XED_IFORM_MOVD_MEMd_XMMd: + case XED_IFORM_MOVD_MMXq_GPR32: + case XED_IFORM_MOVD_MMXq_MEMd: + case XED_IFORM_MOVD_XMMdq_GPR32: + case XED_IFORM_MOVD_XMMdq_MEMd: + case XED_IFORM_MOVDDUP_XMMdq_MEMq: + case XED_IFORM_MOVDDUP_XMMdq_XMMq: + case XED_IFORM_MOVDIR64B_GPRa_MEM: + case XED_IFORM_MOVDIRI_MEMu32_GPR32u32: + case XED_IFORM_MOVDIRI_MEMu64_GPR64u64: + case XED_IFORM_MOVDQ2Q_MMXq_XMMq: + case XED_IFORM_MOVDQA_MEMdq_XMMdq: + case XED_IFORM_MOVDQA_XMMdq_MEMdq: + case XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F: + case XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F: + case XED_IFORM_MOVDQU_MEMdq_XMMdq: + case XED_IFORM_MOVDQU_XMMdq_MEMdq: + case XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F: + case XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F: + case XED_IFORM_MOVHLPS_XMMq_XMMq: + case XED_IFORM_MOVHPD_MEMq_XMMsd: + case XED_IFORM_MOVHPD_XMMsd_MEMq: + case XED_IFORM_MOVHPS_MEMq_XMMps: + case XED_IFORM_MOVHPS_XMMq_MEMq: + case XED_IFORM_MOVLHPS_XMMq_XMMq: + case XED_IFORM_MOVLPD_MEMq_XMMsd: + case XED_IFORM_MOVLPD_XMMsd_MEMq: + case XED_IFORM_MOVLPS_MEMq_XMMq: + case XED_IFORM_MOVLPS_XMMq_MEMq: + case XED_IFORM_MOVMSKPD_GPR32_XMMpd: + case XED_IFORM_MOVMSKPS_GPR32_XMMps: + case XED_IFORM_MOVNTDQ_MEMdq_XMMdq: + case XED_IFORM_MOVNTDQA_XMMdq_MEMdq: + case XED_IFORM_MOVNTI_MEMd_GPR32: + case XED_IFORM_MOVNTI_MEMq_GPR64: + case XED_IFORM_MOVNTPD_MEMdq_XMMpd: + case XED_IFORM_MOVNTPS_MEMdq_XMMps: + case XED_IFORM_MOVNTQ_MEMq_MMXq: + case XED_IFORM_MOVNTSD_MEMq_XMMq: + case XED_IFORM_MOVNTSS_MEMd_XMMd: + case XED_IFORM_MOVQ_GPR64_MMXq: + case XED_IFORM_MOVQ_GPR64_XMMq: + case XED_IFORM_MOVQ_MEMq_MMXq_0F7E: + case XED_IFORM_MOVQ_MEMq_MMXq_0F7F: + case XED_IFORM_MOVQ_MEMq_XMMq_0F7E: + case XED_IFORM_MOVQ_MEMq_XMMq_0FD6: + case XED_IFORM_MOVQ_MMXq_GPR64: + case XED_IFORM_MOVQ_MMXq_MEMq_0F6E: + case XED_IFORM_MOVQ_MMXq_MEMq_0F6F: + case XED_IFORM_MOVQ_MMXq_MMXq_0F6F: + case XED_IFORM_MOVQ_MMXq_MMXq_0F7F: + case XED_IFORM_MOVQ_XMMdq_GPR64: + case XED_IFORM_MOVQ_XMMdq_MEMq_0F6E: + case XED_IFORM_MOVQ_XMMdq_MEMq_0F7E: + case XED_IFORM_MOVQ_XMMdq_XMMq_0F7E: + case XED_IFORM_MOVQ_XMMdq_XMMq_0FD6: + case XED_IFORM_MOVQ2DQ_XMMdq_MMXq: + case XED_IFORM_MOVSB: + case XED_IFORM_MOVSD: + case XED_IFORM_MOVSD_XMM_MEMsd_XMMsd: + case XED_IFORM_MOVSD_XMM_XMMdq_MEMsd: + case XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10: + case XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11: + case XED_IFORM_MOVSHDUP_XMMps_MEMps: + case XED_IFORM_MOVSHDUP_XMMps_XMMps: + case XED_IFORM_MOVSLDUP_XMMps_MEMps: + case XED_IFORM_MOVSLDUP_XMMps_XMMps: + case XED_IFORM_MOVSQ: + case XED_IFORM_MOVSS_MEMss_XMMss: + case XED_IFORM_MOVSS_XMMdq_MEMss: + case XED_IFORM_MOVSS_XMMss_XMMss_0F10: + case XED_IFORM_MOVSS_XMMss_XMMss_0F11: + case XED_IFORM_MOVSW: + case XED_IFORM_MOVSX_GPRv_GPR16: + case XED_IFORM_MOVSX_GPRv_GPR8: + case XED_IFORM_MOVSX_GPRv_MEMb: + case XED_IFORM_MOVSX_GPRv_MEMw: + case XED_IFORM_MOVSXD_GPRv_GPRz: + case XED_IFORM_MOVSXD_GPRv_MEMz: + case XED_IFORM_MOVUPD_MEMpd_XMMpd: + case XED_IFORM_MOVUPD_XMMpd_MEMpd: + case XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10: + case XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11: + case XED_IFORM_MOVUPS_MEMps_XMMps: + case XED_IFORM_MOVUPS_XMMps_MEMps: + case XED_IFORM_MOVUPS_XMMps_XMMps_0F10: + case XED_IFORM_MOVUPS_XMMps_XMMps_0F11: + case XED_IFORM_MOVZX_GPRv_GPR16: + case XED_IFORM_MOVZX_GPRv_GPR8: + case XED_IFORM_MOVZX_GPRv_MEMb: + case XED_IFORM_MOVZX_GPRv_MEMw: + case XED_IFORM_MOV_CR_CR_GPR32: + case XED_IFORM_MOV_CR_CR_GPR64: + case XED_IFORM_MOV_CR_GPR32_CR: + case XED_IFORM_MOV_CR_GPR64_CR: + case XED_IFORM_MOV_DR_DR_GPR32: + case XED_IFORM_MOV_DR_DR_GPR64: + case XED_IFORM_MOV_DR_GPR32_DR: + case XED_IFORM_MOV_DR_GPR64_DR: + case XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb: + case XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb: + case XED_IFORM_MUL_GPR8: + case XED_IFORM_MUL_GPRv: + case XED_IFORM_MUL_MEMb: + case XED_IFORM_MUL_MEMv: + case XED_IFORM_MULPD_XMMpd_MEMpd: + case XED_IFORM_MULPD_XMMpd_XMMpd: + case XED_IFORM_MULPS_XMMps_MEMps: + case XED_IFORM_MULPS_XMMps_XMMps: + case XED_IFORM_MULSD_XMMsd_MEMsd: + case XED_IFORM_MULSD_XMMsd_XMMsd: + case XED_IFORM_MULSS_XMMss_MEMss: + case XED_IFORM_MULSS_XMMss_XMMss: + case XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd: + case XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq: + case XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_MWAIT: + case XED_IFORM_MWAITX: + case XED_IFORM_NEG_GPR8: + case XED_IFORM_NEG_GPRv: + case XED_IFORM_NEG_MEMb: + case XED_IFORM_NEG_MEMv: + case XED_IFORM_NEG_LOCK_MEMb: + case XED_IFORM_NEG_LOCK_MEMv: + case XED_IFORM_NOP_90: + case XED_IFORM_NOP_GPRv_0F18r0: + case XED_IFORM_NOP_GPRv_0F18r1: + case XED_IFORM_NOP_GPRv_0F18r2: + case XED_IFORM_NOP_GPRv_0F18r3: + case XED_IFORM_NOP_GPRv_0F18r4: + case XED_IFORM_NOP_GPRv_0F18r5: + case XED_IFORM_NOP_GPRv_0F18r6: + case XED_IFORM_NOP_GPRv_0F18r7: + case XED_IFORM_NOP_GPRv_GPRv_0F0D: + case XED_IFORM_NOP_GPRv_GPRv_0F19: + case XED_IFORM_NOP_GPRv_GPRv_0F1A: + case XED_IFORM_NOP_GPRv_GPRv_0F1B: + case XED_IFORM_NOP_GPRv_GPRv_0F1C: + case XED_IFORM_NOP_GPRv_GPRv_0F1D: + case XED_IFORM_NOP_GPRv_GPRv_0F1E: + case XED_IFORM_NOP_GPRv_GPRv_0F1F: + case XED_IFORM_NOP_GPRv_MEM_0F1B: + case XED_IFORM_NOP_GPRv_MEMv_0F1A: + case XED_IFORM_NOP_MEMv_0F18r4: + case XED_IFORM_NOP_MEMv_0F18r5: + case XED_IFORM_NOP_MEMv_0F18r6: + case XED_IFORM_NOP_MEMv_0F18r7: + case XED_IFORM_NOP_MEMv_GPRv_0F19: + case XED_IFORM_NOP_MEMv_GPRv_0F1C: + case XED_IFORM_NOP_MEMv_GPRv_0F1D: + case XED_IFORM_NOP_MEMv_GPRv_0F1E: + case XED_IFORM_NOP_MEMv_GPRv_0F1F: + case XED_IFORM_NOT_GPR8: + case XED_IFORM_NOT_GPRv: + case XED_IFORM_NOT_MEMb: + case XED_IFORM_NOT_MEMv: + case XED_IFORM_NOT_LOCK_MEMb: + case XED_IFORM_NOT_LOCK_MEMv: + case XED_IFORM_OR_AL_IMMb: + case XED_IFORM_OR_GPR8_GPR8_08: + case XED_IFORM_OR_GPR8_GPR8_0A: + case XED_IFORM_OR_GPR8_IMMb_80r1: + case XED_IFORM_OR_GPR8_IMMb_82r1: + case XED_IFORM_OR_GPR8_MEMb: + case XED_IFORM_OR_GPRv_GPRv_09: + case XED_IFORM_OR_GPRv_GPRv_0B: + case XED_IFORM_OR_GPRv_IMMb: + case XED_IFORM_OR_GPRv_IMMz: + case XED_IFORM_OR_GPRv_MEMv: + case XED_IFORM_OR_MEMb_GPR8: + case XED_IFORM_OR_MEMb_IMMb_80r1: + case XED_IFORM_OR_MEMb_IMMb_82r1: + case XED_IFORM_OR_MEMv_GPRv: + case XED_IFORM_OR_MEMv_IMMb: + case XED_IFORM_OR_MEMv_IMMz: + case XED_IFORM_OR_OrAX_IMMz: + case XED_IFORM_ORPD_XMMxuq_MEMxuq: + case XED_IFORM_ORPD_XMMxuq_XMMxuq: + case XED_IFORM_ORPS_XMMxud_MEMxud: + case XED_IFORM_ORPS_XMMxud_XMMxud: + case XED_IFORM_OR_LOCK_MEMb_GPR8: + case XED_IFORM_OR_LOCK_MEMb_IMMb_80r1: + case XED_IFORM_OR_LOCK_MEMb_IMMb_82r1: + case XED_IFORM_OR_LOCK_MEMv_GPRv: + case XED_IFORM_OR_LOCK_MEMv_IMMb: + case XED_IFORM_OR_LOCK_MEMv_IMMz: + case XED_IFORM_OUT_DX_AL: + case XED_IFORM_OUT_DX_OeAX: + case XED_IFORM_OUT_IMMb_AL: + case XED_IFORM_OUT_IMMb_OeAX: + case XED_IFORM_OUTSB: + case XED_IFORM_OUTSD: + case XED_IFORM_OUTSW: + case XED_IFORM_PABSB_MMXq_MEMq: + case XED_IFORM_PABSB_MMXq_MMXq: + case XED_IFORM_PABSB_XMMdq_MEMdq: + case XED_IFORM_PABSB_XMMdq_XMMdq: + case XED_IFORM_PABSD_MMXq_MEMq: + case XED_IFORM_PABSD_MMXq_MMXq: + case XED_IFORM_PABSD_XMMdq_MEMdq: + case XED_IFORM_PABSD_XMMdq_XMMdq: + case XED_IFORM_PABSW_MMXq_MEMq: + case XED_IFORM_PABSW_MMXq_MMXq: + case XED_IFORM_PABSW_XMMdq_MEMdq: + case XED_IFORM_PABSW_XMMdq_XMMdq: + case XED_IFORM_PACKSSDW_MMXq_MEMq: + case XED_IFORM_PACKSSDW_MMXq_MMXq: + case XED_IFORM_PACKSSDW_XMMdq_MEMdq: + case XED_IFORM_PACKSSDW_XMMdq_XMMdq: + case XED_IFORM_PACKSSWB_MMXq_MEMq: + case XED_IFORM_PACKSSWB_MMXq_MMXq: + case XED_IFORM_PACKSSWB_XMMdq_MEMdq: + case XED_IFORM_PACKSSWB_XMMdq_XMMdq: + case XED_IFORM_PACKUSDW_XMMdq_MEMdq: + case XED_IFORM_PACKUSDW_XMMdq_XMMdq: + case XED_IFORM_PACKUSWB_MMXq_MEMq: + case XED_IFORM_PACKUSWB_MMXq_MMXq: + case XED_IFORM_PACKUSWB_XMMdq_MEMdq: + case XED_IFORM_PACKUSWB_XMMdq_XMMdq: + case XED_IFORM_PADDB_MMXq_MEMq: + case XED_IFORM_PADDB_MMXq_MMXq: + case XED_IFORM_PADDB_XMMdq_MEMdq: + case XED_IFORM_PADDB_XMMdq_XMMdq: + case XED_IFORM_PADDD_MMXq_MEMq: + case XED_IFORM_PADDD_MMXq_MMXq: + case XED_IFORM_PADDD_XMMdq_MEMdq: + case XED_IFORM_PADDD_XMMdq_XMMdq: + case XED_IFORM_PADDQ_MMXq_MEMq: + case XED_IFORM_PADDQ_MMXq_MMXq: + case XED_IFORM_PADDQ_XMMdq_MEMdq: + case XED_IFORM_PADDQ_XMMdq_XMMdq: + case XED_IFORM_PADDSB_MMXq_MEMq: + case XED_IFORM_PADDSB_MMXq_MMXq: + case XED_IFORM_PADDSB_XMMdq_MEMdq: + case XED_IFORM_PADDSB_XMMdq_XMMdq: + case XED_IFORM_PADDSW_MMXq_MEMq: + case XED_IFORM_PADDSW_MMXq_MMXq: + case XED_IFORM_PADDSW_XMMdq_MEMdq: + case XED_IFORM_PADDSW_XMMdq_XMMdq: + case XED_IFORM_PADDUSB_MMXq_MEMq: + case XED_IFORM_PADDUSB_MMXq_MMXq: + case XED_IFORM_PADDUSB_XMMdq_MEMdq: + case XED_IFORM_PADDUSB_XMMdq_XMMdq: + case XED_IFORM_PADDUSW_MMXq_MEMq: + case XED_IFORM_PADDUSW_MMXq_MMXq: + case XED_IFORM_PADDUSW_XMMdq_MEMdq: + case XED_IFORM_PADDUSW_XMMdq_XMMdq: + case XED_IFORM_PADDW_MMXq_MEMq: + case XED_IFORM_PADDW_MMXq_MMXq: + case XED_IFORM_PADDW_XMMdq_MEMdq: + case XED_IFORM_PADDW_XMMdq_XMMdq: + case XED_IFORM_PALIGNR_MMXq_MEMq_IMMb: + case XED_IFORM_PALIGNR_MMXq_MMXq_IMMb: + case XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb: + case XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb: + case XED_IFORM_PAND_MMXq_MEMq: + case XED_IFORM_PAND_MMXq_MMXq: + case XED_IFORM_PAND_XMMdq_MEMdq: + case XED_IFORM_PAND_XMMdq_XMMdq: + case XED_IFORM_PANDN_MMXq_MEMq: + case XED_IFORM_PANDN_MMXq_MMXq: + case XED_IFORM_PANDN_XMMdq_MEMdq: + case XED_IFORM_PANDN_XMMdq_XMMdq: + case XED_IFORM_PAUSE: + case XED_IFORM_PAVGB_MMXq_MEMq: + case XED_IFORM_PAVGB_MMXq_MMXq: + case XED_IFORM_PAVGB_XMMdq_MEMdq: + case XED_IFORM_PAVGB_XMMdq_XMMdq: + case XED_IFORM_PAVGUSB_MMXq_MEMq: + case XED_IFORM_PAVGUSB_MMXq_MMXq: + case XED_IFORM_PAVGW_MMXq_MEMq: + case XED_IFORM_PAVGW_MMXq_MMXq: + case XED_IFORM_PAVGW_XMMdq_MEMdq: + case XED_IFORM_PAVGW_XMMdq_XMMdq: + case XED_IFORM_PBLENDVB_XMMdq_MEMdq: + case XED_IFORM_PBLENDVB_XMMdq_XMMdq: + case XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb: + case XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPEQB_MMXq_MEMq: + case XED_IFORM_PCMPEQB_MMXq_MMXq: + case XED_IFORM_PCMPEQB_XMMdq_MEMdq: + case XED_IFORM_PCMPEQB_XMMdq_XMMdq: + case XED_IFORM_PCMPEQD_MMXq_MEMq: + case XED_IFORM_PCMPEQD_MMXq_MMXq: + case XED_IFORM_PCMPEQD_XMMdq_MEMdq: + case XED_IFORM_PCMPEQD_XMMdq_XMMdq: + case XED_IFORM_PCMPEQQ_XMMdq_MEMdq: + case XED_IFORM_PCMPEQQ_XMMdq_XMMdq: + case XED_IFORM_PCMPEQW_MMXq_MEMq: + case XED_IFORM_PCMPEQW_MMXq_MMXq: + case XED_IFORM_PCMPEQW_XMMdq_MEMdq: + case XED_IFORM_PCMPEQW_XMMdq_XMMdq: + case XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPGTB_MMXq_MEMq: + case XED_IFORM_PCMPGTB_MMXq_MMXq: + case XED_IFORM_PCMPGTB_XMMdq_MEMdq: + case XED_IFORM_PCMPGTB_XMMdq_XMMdq: + case XED_IFORM_PCMPGTD_MMXq_MEMq: + case XED_IFORM_PCMPGTD_MMXq_MMXq: + case XED_IFORM_PCMPGTD_XMMdq_MEMdq: + case XED_IFORM_PCMPGTD_XMMdq_XMMdq: + case XED_IFORM_PCMPGTQ_XMMdq_MEMdq: + case XED_IFORM_PCMPGTQ_XMMdq_XMMdq: + case XED_IFORM_PCMPGTW_MMXq_MEMq: + case XED_IFORM_PCMPGTW_MMXq_MMXq: + case XED_IFORM_PCMPGTW_XMMdq_MEMdq: + case XED_IFORM_PCMPGTW_XMMdq_XMMdq: + case XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb: + case XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb: + case XED_IFORM_PCONFIG: + case XED_IFORM_PCONFIG64: + case XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd: + case XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq: + case XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd: + case XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq: + case XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb: + case XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb: + case XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb: + case XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb: + case XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb: + case XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb: + case XED_IFORM_PEXTRW_GPR32_MMXq_IMMb: + case XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb: + case XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb: + case XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb: + case XED_IFORM_PF2ID_MMXq_MEMq: + case XED_IFORM_PF2ID_MMXq_MMXq: + case XED_IFORM_PF2IW_MMXq_MEMq: + case XED_IFORM_PF2IW_MMXq_MMXq: + case XED_IFORM_PFACC_MMXq_MEMq: + case XED_IFORM_PFACC_MMXq_MMXq: + case XED_IFORM_PFADD_MMXq_MEMq: + case XED_IFORM_PFADD_MMXq_MMXq: + case XED_IFORM_PFCMPEQ_MMXq_MEMq: + case XED_IFORM_PFCMPEQ_MMXq_MMXq: + case XED_IFORM_PFCMPGE_MMXq_MEMq: + case XED_IFORM_PFCMPGE_MMXq_MMXq: + case XED_IFORM_PFCMPGT_MMXq_MEMq: + case XED_IFORM_PFCMPGT_MMXq_MMXq: + case XED_IFORM_PFMAX_MMXq_MEMq: + case XED_IFORM_PFMAX_MMXq_MMXq: + case XED_IFORM_PFMIN_MMXq_MEMq: + case XED_IFORM_PFMIN_MMXq_MMXq: + case XED_IFORM_PFMUL_MMXq_MEMq: + case XED_IFORM_PFMUL_MMXq_MMXq: + case XED_IFORM_PFNACC_MMXq_MEMq: + case XED_IFORM_PFNACC_MMXq_MMXq: + case XED_IFORM_PFPNACC_MMXq_MEMq: + case XED_IFORM_PFPNACC_MMXq_MMXq: + case XED_IFORM_PFRCP_MMXq_MEMq: + case XED_IFORM_PFRCP_MMXq_MMXq: + case XED_IFORM_PFRCPIT1_MMXq_MEMq: + case XED_IFORM_PFRCPIT1_MMXq_MMXq: + case XED_IFORM_PFRCPIT2_MMXq_MEMq: + case XED_IFORM_PFRCPIT2_MMXq_MMXq: + case XED_IFORM_PFRSQIT1_MMXq_MEMq: + case XED_IFORM_PFRSQIT1_MMXq_MMXq: + case XED_IFORM_PFRSQRT_MMXq_MEMq: + case XED_IFORM_PFRSQRT_MMXq_MMXq: + case XED_IFORM_PFSUB_MMXq_MEMq: + case XED_IFORM_PFSUB_MMXq_MMXq: + case XED_IFORM_PFSUBR_MMXq_MEMq: + case XED_IFORM_PFSUBR_MMXq_MMXq: + case XED_IFORM_PHADDD_MMXq_MEMq: + case XED_IFORM_PHADDD_MMXq_MMXq: + case XED_IFORM_PHADDD_XMMdq_MEMdq: + case XED_IFORM_PHADDD_XMMdq_XMMdq: + case XED_IFORM_PHADDSW_MMXq_MEMq: + case XED_IFORM_PHADDSW_MMXq_MMXq: + case XED_IFORM_PHADDSW_XMMdq_MEMdq: + case XED_IFORM_PHADDSW_XMMdq_XMMdq: + case XED_IFORM_PHADDW_MMXq_MEMq: + case XED_IFORM_PHADDW_MMXq_MMXq: + case XED_IFORM_PHADDW_XMMdq_MEMdq: + case XED_IFORM_PHADDW_XMMdq_XMMdq: + case XED_IFORM_PHMINPOSUW_XMMdq_MEMdq: + case XED_IFORM_PHMINPOSUW_XMMdq_XMMdq: + case XED_IFORM_PHSUBD_MMXq_MEMq: + case XED_IFORM_PHSUBD_MMXq_MMXq: + case XED_IFORM_PHSUBD_XMMdq_MEMdq: + case XED_IFORM_PHSUBD_XMMdq_XMMdq: + case XED_IFORM_PHSUBSW_MMXq_MEMq: + case XED_IFORM_PHSUBSW_MMXq_MMXq: + case XED_IFORM_PHSUBSW_XMMdq_MEMdq: + case XED_IFORM_PHSUBSW_XMMdq_XMMdq: + case XED_IFORM_PHSUBW_MMXq_MEMq: + case XED_IFORM_PHSUBW_MMXq_MMXq: + case XED_IFORM_PHSUBW_XMMdq_MEMdq: + case XED_IFORM_PHSUBW_XMMdq_XMMdq: + case XED_IFORM_PI2FD_MMXq_MEMq: + case XED_IFORM_PI2FD_MMXq_MMXq: + case XED_IFORM_PI2FW_MMXq_MEMq: + case XED_IFORM_PI2FW_MMXq_MMXq: + case XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb: + case XED_IFORM_PINSRB_XMMdq_MEMb_IMMb: + case XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb: + case XED_IFORM_PINSRD_XMMdq_MEMd_IMMb: + case XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb: + case XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb: + case XED_IFORM_PINSRW_MMXq_GPR32_IMMb: + case XED_IFORM_PINSRW_MMXq_MEMw_IMMb: + case XED_IFORM_PINSRW_XMMdq_GPR32_IMMb: + case XED_IFORM_PINSRW_XMMdq_MEMw_IMMb: + case XED_IFORM_PMADDUBSW_MMXq_MEMq: + case XED_IFORM_PMADDUBSW_MMXq_MMXq: + case XED_IFORM_PMADDUBSW_XMMdq_MEMdq: + case XED_IFORM_PMADDUBSW_XMMdq_XMMdq: + case XED_IFORM_PMADDWD_MMXq_MEMq: + case XED_IFORM_PMADDWD_MMXq_MMXq: + case XED_IFORM_PMADDWD_XMMdq_MEMdq: + case XED_IFORM_PMADDWD_XMMdq_XMMdq: + case XED_IFORM_PMAXSB_XMMdq_MEMdq: + case XED_IFORM_PMAXSB_XMMdq_XMMdq: + case XED_IFORM_PMAXSD_XMMdq_MEMdq: + case XED_IFORM_PMAXSD_XMMdq_XMMdq: + case XED_IFORM_PMAXSW_MMXq_MEMq: + case XED_IFORM_PMAXSW_MMXq_MMXq: + case XED_IFORM_PMAXSW_XMMdq_MEMdq: + case XED_IFORM_PMAXSW_XMMdq_XMMdq: + case XED_IFORM_PMAXUB_MMXq_MEMq: + case XED_IFORM_PMAXUB_MMXq_MMXq: + case XED_IFORM_PMAXUB_XMMdq_MEMdq: + case XED_IFORM_PMAXUB_XMMdq_XMMdq: + case XED_IFORM_PMAXUD_XMMdq_MEMdq: + case XED_IFORM_PMAXUD_XMMdq_XMMdq: + case XED_IFORM_PMAXUW_XMMdq_MEMdq: + case XED_IFORM_PMAXUW_XMMdq_XMMdq: + case XED_IFORM_PMINSB_XMMdq_MEMdq: + case XED_IFORM_PMINSB_XMMdq_XMMdq: + case XED_IFORM_PMINSD_XMMdq_MEMdq: + case XED_IFORM_PMINSD_XMMdq_XMMdq: + case XED_IFORM_PMINSW_MMXq_MEMq: + case XED_IFORM_PMINSW_MMXq_MMXq: + case XED_IFORM_PMINSW_XMMdq_MEMdq: + case XED_IFORM_PMINSW_XMMdq_XMMdq: + case XED_IFORM_PMINUB_MMXq_MEMq: + case XED_IFORM_PMINUB_MMXq_MMXq: + case XED_IFORM_PMINUB_XMMdq_MEMdq: + case XED_IFORM_PMINUB_XMMdq_XMMdq: + case XED_IFORM_PMINUD_XMMdq_MEMdq: + case XED_IFORM_PMINUD_XMMdq_XMMdq: + case XED_IFORM_PMINUW_XMMdq_MEMdq: + case XED_IFORM_PMINUW_XMMdq_XMMdq: + case XED_IFORM_PMOVMSKB_GPR32_MMXq: + case XED_IFORM_PMOVMSKB_GPR32_XMMdq: + case XED_IFORM_PMOVSXBD_XMMdq_MEMd: + case XED_IFORM_PMOVSXBD_XMMdq_XMMd: + case XED_IFORM_PMOVSXBQ_XMMdq_MEMw: + case XED_IFORM_PMOVSXBQ_XMMdq_XMMw: + case XED_IFORM_PMOVSXBW_XMMdq_MEMq: + case XED_IFORM_PMOVSXBW_XMMdq_XMMq: + case XED_IFORM_PMOVSXDQ_XMMdq_MEMq: + case XED_IFORM_PMOVSXDQ_XMMdq_XMMq: + case XED_IFORM_PMOVSXWD_XMMdq_MEMq: + case XED_IFORM_PMOVSXWD_XMMdq_XMMq: + case XED_IFORM_PMOVSXWQ_XMMdq_MEMd: + case XED_IFORM_PMOVSXWQ_XMMdq_XMMd: + case XED_IFORM_PMOVZXBD_XMMdq_MEMd: + case XED_IFORM_PMOVZXBD_XMMdq_XMMd: + case XED_IFORM_PMOVZXBQ_XMMdq_MEMw: + case XED_IFORM_PMOVZXBQ_XMMdq_XMMw: + case XED_IFORM_PMOVZXBW_XMMdq_MEMq: + case XED_IFORM_PMOVZXBW_XMMdq_XMMq: + case XED_IFORM_PMOVZXDQ_XMMdq_MEMq: + case XED_IFORM_PMOVZXDQ_XMMdq_XMMq: + case XED_IFORM_PMOVZXWD_XMMdq_MEMq: + case XED_IFORM_PMOVZXWD_XMMdq_XMMq: + case XED_IFORM_PMOVZXWQ_XMMdq_MEMd: + case XED_IFORM_PMOVZXWQ_XMMdq_XMMd: + case XED_IFORM_PMULDQ_XMMdq_MEMdq: + case XED_IFORM_PMULDQ_XMMdq_XMMdq: + case XED_IFORM_PMULHRSW_MMXq_MEMq: + case XED_IFORM_PMULHRSW_MMXq_MMXq: + case XED_IFORM_PMULHRSW_XMMdq_MEMdq: + case XED_IFORM_PMULHRSW_XMMdq_XMMdq: + case XED_IFORM_PMULHRW_MMXq_MEMq: + case XED_IFORM_PMULHRW_MMXq_MMXq: + case XED_IFORM_PMULHUW_MMXq_MEMq: + case XED_IFORM_PMULHUW_MMXq_MMXq: + case XED_IFORM_PMULHUW_XMMdq_MEMdq: + case XED_IFORM_PMULHUW_XMMdq_XMMdq: + case XED_IFORM_PMULHW_MMXq_MEMq: + case XED_IFORM_PMULHW_MMXq_MMXq: + case XED_IFORM_PMULHW_XMMdq_MEMdq: + case XED_IFORM_PMULHW_XMMdq_XMMdq: + case XED_IFORM_PMULLD_XMMdq_MEMdq: + case XED_IFORM_PMULLD_XMMdq_XMMdq: + case XED_IFORM_PMULLW_MMXq_MEMq: + case XED_IFORM_PMULLW_MMXq_MMXq: + case XED_IFORM_PMULLW_XMMdq_MEMdq: + case XED_IFORM_PMULLW_XMMdq_XMMdq: + case XED_IFORM_PMULUDQ_MMXq_MEMq: + case XED_IFORM_PMULUDQ_MMXq_MMXq: + case XED_IFORM_PMULUDQ_XMMdq_MEMdq: + case XED_IFORM_PMULUDQ_XMMdq_XMMdq: + case XED_IFORM_POP_DS: + case XED_IFORM_POP_ES: + case XED_IFORM_POP_FS: + case XED_IFORM_POP_GPRv_58: + case XED_IFORM_POP_GPRv_8F: + case XED_IFORM_POP_GS: + case XED_IFORM_POP_MEMv: + case XED_IFORM_POP_SS: + case XED_IFORM_POPA: + case XED_IFORM_POPAD: + case XED_IFORM_POPCNT_GPRv_GPRv: + case XED_IFORM_POPCNT_GPRv_MEMv: + case XED_IFORM_POPF: + case XED_IFORM_POPFD: + case XED_IFORM_POPFQ: + case XED_IFORM_POR_MMXq_MEMq: + case XED_IFORM_POR_MMXq_MMXq: + case XED_IFORM_POR_XMMdq_MEMdq: + case XED_IFORM_POR_XMMdq_XMMdq: + case XED_IFORM_PREFETCHNTA_MEMmprefetch: + case XED_IFORM_PREFETCHT0_MEMmprefetch: + case XED_IFORM_PREFETCHT1_MEMmprefetch: + case XED_IFORM_PREFETCHT2_MEMmprefetch: + case XED_IFORM_PREFETCHW_0F0Dr1: + case XED_IFORM_PREFETCHW_0F0Dr3: + case XED_IFORM_PREFETCHWT1_MEMu8: + case XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch: + case XED_IFORM_PREFETCH_RESERVED_0F0Dr4: + case XED_IFORM_PREFETCH_RESERVED_0F0Dr5: + case XED_IFORM_PREFETCH_RESERVED_0F0Dr6: + case XED_IFORM_PREFETCH_RESERVED_0F0Dr7: + case XED_IFORM_PSADBW_MMXq_MEMq: + case XED_IFORM_PSADBW_MMXq_MMXq: + case XED_IFORM_PSADBW_XMMdq_MEMdq: + case XED_IFORM_PSADBW_XMMdq_XMMdq: + case XED_IFORM_PSHUFB_MMXq_MEMq: + case XED_IFORM_PSHUFB_MMXq_MMXq: + case XED_IFORM_PSHUFB_XMMdq_MEMdq: + case XED_IFORM_PSHUFB_XMMdq_XMMdq: + case XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb: + case XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb: + case XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb: + case XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb: + case XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb: + case XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb: + case XED_IFORM_PSHUFW_MMXq_MEMq_IMMb: + case XED_IFORM_PSHUFW_MMXq_MMXq_IMMb: + case XED_IFORM_PSIGNB_MMXq_MEMq: + case XED_IFORM_PSIGNB_MMXq_MMXq: + case XED_IFORM_PSIGNB_XMMdq_MEMdq: + case XED_IFORM_PSIGNB_XMMdq_XMMdq: + case XED_IFORM_PSIGND_MMXq_MEMq: + case XED_IFORM_PSIGND_MMXq_MMXq: + case XED_IFORM_PSIGND_XMMdq_MEMdq: + case XED_IFORM_PSIGND_XMMdq_XMMdq: + case XED_IFORM_PSIGNW_MMXq_MEMq: + case XED_IFORM_PSIGNW_MMXq_MMXq: + case XED_IFORM_PSIGNW_XMMdq_MEMdq: + case XED_IFORM_PSIGNW_XMMdq_XMMdq: + case XED_IFORM_PSLLD_MMXq_IMMb: + case XED_IFORM_PSLLD_MMXq_MEMq: + case XED_IFORM_PSLLD_MMXq_MMXq: + case XED_IFORM_PSLLD_XMMdq_IMMb: + case XED_IFORM_PSLLD_XMMdq_MEMdq: + case XED_IFORM_PSLLD_XMMdq_XMMdq: + case XED_IFORM_PSLLDQ_XMMdq_IMMb: + case XED_IFORM_PSLLQ_MMXq_IMMb: + case XED_IFORM_PSLLQ_MMXq_MEMq: + case XED_IFORM_PSLLQ_MMXq_MMXq: + case XED_IFORM_PSLLQ_XMMdq_IMMb: + case XED_IFORM_PSLLQ_XMMdq_MEMdq: + case XED_IFORM_PSLLQ_XMMdq_XMMdq: + case XED_IFORM_PSLLW_MMXq_IMMb: + case XED_IFORM_PSLLW_MMXq_MEMq: + case XED_IFORM_PSLLW_MMXq_MMXq: + case XED_IFORM_PSLLW_XMMdq_IMMb: + case XED_IFORM_PSLLW_XMMdq_MEMdq: + case XED_IFORM_PSLLW_XMMdq_XMMdq: + case XED_IFORM_PSMASH_RAX: + case XED_IFORM_PSRAD_MMXq_IMMb: + case XED_IFORM_PSRAD_MMXq_MEMq: + case XED_IFORM_PSRAD_MMXq_MMXq: + case XED_IFORM_PSRAD_XMMdq_IMMb: + case XED_IFORM_PSRAD_XMMdq_MEMdq: + case XED_IFORM_PSRAD_XMMdq_XMMdq: + case XED_IFORM_PSRAW_MMXq_IMMb: + case XED_IFORM_PSRAW_MMXq_MEMq: + case XED_IFORM_PSRAW_MMXq_MMXq: + case XED_IFORM_PSRAW_XMMdq_IMMb: + case XED_IFORM_PSRAW_XMMdq_MEMdq: + case XED_IFORM_PSRAW_XMMdq_XMMdq: + case XED_IFORM_PSRLD_MMXq_IMMb: + case XED_IFORM_PSRLD_MMXq_MEMq: + case XED_IFORM_PSRLD_MMXq_MMXq: + case XED_IFORM_PSRLD_XMMdq_IMMb: + case XED_IFORM_PSRLD_XMMdq_MEMdq: + case XED_IFORM_PSRLD_XMMdq_XMMdq: + case XED_IFORM_PSRLDQ_XMMdq_IMMb: + case XED_IFORM_PSRLQ_MMXq_IMMb: + case XED_IFORM_PSRLQ_MMXq_MEMq: + case XED_IFORM_PSRLQ_MMXq_MMXq: + case XED_IFORM_PSRLQ_XMMdq_IMMb: + case XED_IFORM_PSRLQ_XMMdq_MEMdq: + case XED_IFORM_PSRLQ_XMMdq_XMMdq: + case XED_IFORM_PSRLW_MMXq_IMMb: + case XED_IFORM_PSRLW_MMXq_MEMq: + case XED_IFORM_PSRLW_MMXq_MMXq: + case XED_IFORM_PSRLW_XMMdq_IMMb: + case XED_IFORM_PSRLW_XMMdq_MEMdq: + case XED_IFORM_PSRLW_XMMdq_XMMdq: + case XED_IFORM_PSUBB_MMXq_MEMq: + case XED_IFORM_PSUBB_MMXq_MMXq: + case XED_IFORM_PSUBB_XMMdq_MEMdq: + case XED_IFORM_PSUBB_XMMdq_XMMdq: + case XED_IFORM_PSUBD_MMXq_MEMq: + case XED_IFORM_PSUBD_MMXq_MMXq: + case XED_IFORM_PSUBD_XMMdq_MEMdq: + case XED_IFORM_PSUBD_XMMdq_XMMdq: + case XED_IFORM_PSUBQ_MMXq_MEMq: + case XED_IFORM_PSUBQ_MMXq_MMXq: + case XED_IFORM_PSUBQ_XMMdq_MEMdq: + case XED_IFORM_PSUBQ_XMMdq_XMMdq: + case XED_IFORM_PSUBSB_MMXq_MEMq: + case XED_IFORM_PSUBSB_MMXq_MMXq: + case XED_IFORM_PSUBSB_XMMdq_MEMdq: + case XED_IFORM_PSUBSB_XMMdq_XMMdq: + case XED_IFORM_PSUBSW_MMXq_MEMq: + case XED_IFORM_PSUBSW_MMXq_MMXq: + case XED_IFORM_PSUBSW_XMMdq_MEMdq: + case XED_IFORM_PSUBSW_XMMdq_XMMdq: + case XED_IFORM_PSUBUSB_MMXq_MEMq: + case XED_IFORM_PSUBUSB_MMXq_MMXq: + case XED_IFORM_PSUBUSB_XMMdq_MEMdq: + case XED_IFORM_PSUBUSB_XMMdq_XMMdq: + case XED_IFORM_PSUBUSW_MMXq_MEMq: + case XED_IFORM_PSUBUSW_MMXq_MMXq: + case XED_IFORM_PSUBUSW_XMMdq_MEMdq: + case XED_IFORM_PSUBUSW_XMMdq_XMMdq: + case XED_IFORM_PSUBW_MMXq_MEMq: + case XED_IFORM_PSUBW_MMXq_MMXq: + case XED_IFORM_PSUBW_XMMdq_MEMdq: + case XED_IFORM_PSUBW_XMMdq_XMMdq: + case XED_IFORM_PSWAPD_MMXq_MEMq: + case XED_IFORM_PSWAPD_MMXq_MMXq: + case XED_IFORM_PTEST_XMMdq_MEMdq: + case XED_IFORM_PTEST_XMMdq_XMMdq: + case XED_IFORM_PTWRITE_GPRy: + case XED_IFORM_PTWRITE_MEMy: + case XED_IFORM_PUNPCKHBW_MMXq_MEMq: + case XED_IFORM_PUNPCKHBW_MMXq_MMXd: + case XED_IFORM_PUNPCKHBW_XMMdq_MEMdq: + case XED_IFORM_PUNPCKHBW_XMMdq_XMMq: + case XED_IFORM_PUNPCKHDQ_MMXq_MEMq: + case XED_IFORM_PUNPCKHDQ_MMXq_MMXd: + case XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq: + case XED_IFORM_PUNPCKHDQ_XMMdq_XMMq: + case XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq: + case XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq: + case XED_IFORM_PUNPCKHWD_MMXq_MEMq: + case XED_IFORM_PUNPCKHWD_MMXq_MMXd: + case XED_IFORM_PUNPCKHWD_XMMdq_MEMdq: + case XED_IFORM_PUNPCKHWD_XMMdq_XMMq: + case XED_IFORM_PUNPCKLBW_MMXq_MEMd: + case XED_IFORM_PUNPCKLBW_MMXq_MMXd: + case XED_IFORM_PUNPCKLBW_XMMdq_MEMdq: + case XED_IFORM_PUNPCKLBW_XMMdq_XMMq: + case XED_IFORM_PUNPCKLDQ_MMXq_MEMd: + case XED_IFORM_PUNPCKLDQ_MMXq_MMXd: + case XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq: + case XED_IFORM_PUNPCKLDQ_XMMdq_XMMq: + case XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq: + case XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq: + case XED_IFORM_PUNPCKLWD_MMXq_MEMd: + case XED_IFORM_PUNPCKLWD_MMXq_MMXd: + case XED_IFORM_PUNPCKLWD_XMMdq_MEMdq: + case XED_IFORM_PUNPCKLWD_XMMdq_XMMq: + case XED_IFORM_PUSH_CS: + case XED_IFORM_PUSH_DS: + case XED_IFORM_PUSH_ES: + case XED_IFORM_PUSH_FS: + case XED_IFORM_PUSH_GPRv_50: + case XED_IFORM_PUSH_GPRv_FFr6: + case XED_IFORM_PUSH_GS: + case XED_IFORM_PUSH_IMMb: + case XED_IFORM_PUSH_IMMz: + case XED_IFORM_PUSH_MEMv: + case XED_IFORM_PUSH_SS: + case XED_IFORM_PUSHA: + case XED_IFORM_PUSHAD: + case XED_IFORM_PUSHF: + case XED_IFORM_PUSHFD: + case XED_IFORM_PUSHFQ: + case XED_IFORM_PVALIDATE_RAX_ECX_EDX: + case XED_IFORM_PXOR_MMXq_MEMq: + case XED_IFORM_PXOR_MMXq_MMXq: + case XED_IFORM_PXOR_XMMdq_MEMdq: + case XED_IFORM_PXOR_XMMdq_XMMdq: + case XED_IFORM_RCL_GPR8_CL: + case XED_IFORM_RCL_GPR8_IMMb: + case XED_IFORM_RCL_GPR8_ONE: + case XED_IFORM_RCL_GPRv_CL: + case XED_IFORM_RCL_GPRv_IMMb: + case XED_IFORM_RCL_GPRv_ONE: + case XED_IFORM_RCL_MEMb_CL: + case XED_IFORM_RCL_MEMb_IMMb: + case XED_IFORM_RCL_MEMb_ONE: + case XED_IFORM_RCL_MEMv_CL: + case XED_IFORM_RCL_MEMv_IMMb: + case XED_IFORM_RCL_MEMv_ONE: + case XED_IFORM_RCPPS_XMMps_MEMps: + case XED_IFORM_RCPPS_XMMps_XMMps: + case XED_IFORM_RCPSS_XMMss_MEMss: + case XED_IFORM_RCPSS_XMMss_XMMss: + case XED_IFORM_RCR_GPR8_CL: + case XED_IFORM_RCR_GPR8_IMMb: + case XED_IFORM_RCR_GPR8_ONE: + case XED_IFORM_RCR_GPRv_CL: + case XED_IFORM_RCR_GPRv_IMMb: + case XED_IFORM_RCR_GPRv_ONE: + case XED_IFORM_RCR_MEMb_CL: + case XED_IFORM_RCR_MEMb_IMMb: + case XED_IFORM_RCR_MEMb_ONE: + case XED_IFORM_RCR_MEMv_CL: + case XED_IFORM_RCR_MEMv_IMMb: + case XED_IFORM_RCR_MEMv_ONE: + case XED_IFORM_RDFSBASE_GPRy: + case XED_IFORM_RDGSBASE_GPRy: + case XED_IFORM_RDMSR: + case XED_IFORM_RDPID_GPR32u32: + case XED_IFORM_RDPID_GPR64u64: + case XED_IFORM_RDPKRU: + case XED_IFORM_RDPMC: + case XED_IFORM_RDPRU: + case XED_IFORM_RDRAND_GPRv: + case XED_IFORM_RDSEED_GPRv: + case XED_IFORM_RDSSPD_GPR32u32: + case XED_IFORM_RDSSPQ_GPR64u64: + case XED_IFORM_RDTSC: + case XED_IFORM_RDTSCP: + case XED_IFORM_REPE_CMPSB: + case XED_IFORM_REPE_CMPSD: + case XED_IFORM_REPE_CMPSQ: + case XED_IFORM_REPE_CMPSW: + case XED_IFORM_REPE_SCASB: + case XED_IFORM_REPE_SCASD: + case XED_IFORM_REPE_SCASQ: + case XED_IFORM_REPE_SCASW: + case XED_IFORM_REPNE_CMPSB: + case XED_IFORM_REPNE_CMPSD: + case XED_IFORM_REPNE_CMPSQ: + case XED_IFORM_REPNE_CMPSW: + case XED_IFORM_REPNE_SCASB: + case XED_IFORM_REPNE_SCASD: + case XED_IFORM_REPNE_SCASQ: + case XED_IFORM_REPNE_SCASW: + case XED_IFORM_REP_INSB: + case XED_IFORM_REP_INSD: + case XED_IFORM_REP_INSW: + case XED_IFORM_REP_LODSB: + case XED_IFORM_REP_LODSD: + case XED_IFORM_REP_LODSQ: + case XED_IFORM_REP_LODSW: + case XED_IFORM_REP_MONTMUL: + case XED_IFORM_REP_MOVSB: + case XED_IFORM_REP_MOVSD: + case XED_IFORM_REP_MOVSQ: + case XED_IFORM_REP_MOVSW: + case XED_IFORM_REP_OUTSB: + case XED_IFORM_REP_OUTSD: + case XED_IFORM_REP_OUTSW: + case XED_IFORM_REP_STOSB: + case XED_IFORM_REP_STOSD: + case XED_IFORM_REP_STOSQ: + case XED_IFORM_REP_STOSW: + case XED_IFORM_REP_XCRYPTCBC: + case XED_IFORM_REP_XCRYPTCFB: + case XED_IFORM_REP_XCRYPTCTR: + case XED_IFORM_REP_XCRYPTECB: + case XED_IFORM_REP_XCRYPTOFB: + case XED_IFORM_REP_XSHA1: + case XED_IFORM_REP_XSHA256: + case XED_IFORM_REP_XSTORE: + case XED_IFORM_RET_FAR: + case XED_IFORM_RET_FAR_IMMw: + case XED_IFORM_RET_NEAR: + case XED_IFORM_RET_NEAR_IMMw: + case XED_IFORM_RMPADJUST_RAX_RCX_RDX: + case XED_IFORM_RMPUPDATE_RAX_RCX: + case XED_IFORM_ROL_GPR8_CL: + case XED_IFORM_ROL_GPR8_IMMb: + case XED_IFORM_ROL_GPR8_ONE: + case XED_IFORM_ROL_GPRv_CL: + case XED_IFORM_ROL_GPRv_IMMb: + case XED_IFORM_ROL_GPRv_ONE: + case XED_IFORM_ROL_MEMb_CL: + case XED_IFORM_ROL_MEMb_IMMb: + case XED_IFORM_ROL_MEMb_ONE: + case XED_IFORM_ROL_MEMv_CL: + case XED_IFORM_ROL_MEMv_IMMb: + case XED_IFORM_ROL_MEMv_ONE: + case XED_IFORM_ROR_GPR8_CL: + case XED_IFORM_ROR_GPR8_IMMb: + case XED_IFORM_ROR_GPR8_ONE: + case XED_IFORM_ROR_GPRv_CL: + case XED_IFORM_ROR_GPRv_IMMb: + case XED_IFORM_ROR_GPRv_ONE: + case XED_IFORM_ROR_MEMb_CL: + case XED_IFORM_ROR_MEMb_IMMb: + case XED_IFORM_ROR_MEMb_ONE: + case XED_IFORM_ROR_MEMv_CL: + case XED_IFORM_ROR_MEMv_IMMb: + case XED_IFORM_ROR_MEMv_ONE: + case XED_IFORM_RORX_VGPR32d_MEMd_IMMb: + case XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb: + case XED_IFORM_RORX_VGPR64q_MEMq_IMMb: + case XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb: + case XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb: + case XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb: + case XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb: + case XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb: + case XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb: + case XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb: + case XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb: + case XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb: + case XED_IFORM_RSM: + case XED_IFORM_RSQRTPS_XMMps_MEMps: + case XED_IFORM_RSQRTPS_XMMps_XMMps: + case XED_IFORM_RSQRTSS_XMMss_MEMss: + case XED_IFORM_RSQRTSS_XMMss_XMMss: + case XED_IFORM_RSTORSSP_MEMu64: + case XED_IFORM_SAHF: + case XED_IFORM_SALC: + case XED_IFORM_SAR_GPR8_CL: + case XED_IFORM_SAR_GPR8_IMMb: + case XED_IFORM_SAR_GPR8_ONE: + case XED_IFORM_SAR_GPRv_CL: + case XED_IFORM_SAR_GPRv_IMMb: + case XED_IFORM_SAR_GPRv_ONE: + case XED_IFORM_SAR_MEMb_CL: + case XED_IFORM_SAR_MEMb_IMMb: + case XED_IFORM_SAR_MEMb_ONE: + case XED_IFORM_SAR_MEMv_CL: + case XED_IFORM_SAR_MEMv_IMMb: + case XED_IFORM_SAR_MEMv_ONE: + case XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d: + case XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q: + case XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_SAVEPREVSSP: + case XED_IFORM_SBB_AL_IMMb: + case XED_IFORM_SBB_GPR8_GPR8_18: + case XED_IFORM_SBB_GPR8_GPR8_1A: + case XED_IFORM_SBB_GPR8_IMMb_80r3: + case XED_IFORM_SBB_GPR8_IMMb_82r3: + case XED_IFORM_SBB_GPR8_MEMb: + case XED_IFORM_SBB_GPRv_GPRv_19: + case XED_IFORM_SBB_GPRv_GPRv_1B: + case XED_IFORM_SBB_GPRv_IMMb: + case XED_IFORM_SBB_GPRv_IMMz: + case XED_IFORM_SBB_GPRv_MEMv: + case XED_IFORM_SBB_MEMb_GPR8: + case XED_IFORM_SBB_MEMb_IMMb_80r3: + case XED_IFORM_SBB_MEMb_IMMb_82r3: + case XED_IFORM_SBB_MEMv_GPRv: + case XED_IFORM_SBB_MEMv_IMMb: + case XED_IFORM_SBB_MEMv_IMMz: + case XED_IFORM_SBB_OrAX_IMMz: + case XED_IFORM_SBB_LOCK_MEMb_GPR8: + case XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3: + case XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3: + case XED_IFORM_SBB_LOCK_MEMv_GPRv: + case XED_IFORM_SBB_LOCK_MEMv_IMMb: + case XED_IFORM_SBB_LOCK_MEMv_IMMz: + case XED_IFORM_SCASB: + case XED_IFORM_SCASD: + case XED_IFORM_SCASQ: + case XED_IFORM_SCASW: + case XED_IFORM_SEAMCALL: + case XED_IFORM_SEAMOPS: + case XED_IFORM_SEAMRET: + case XED_IFORM_SENDUIPI_GPR32u32: + case XED_IFORM_SERIALIZE: + case XED_IFORM_SETB_GPR8: + case XED_IFORM_SETB_MEMb: + case XED_IFORM_SETBE_GPR8: + case XED_IFORM_SETBE_MEMb: + case XED_IFORM_SETL_GPR8: + case XED_IFORM_SETL_MEMb: + case XED_IFORM_SETLE_GPR8: + case XED_IFORM_SETLE_MEMb: + case XED_IFORM_SETNB_GPR8: + case XED_IFORM_SETNB_MEMb: + case XED_IFORM_SETNBE_GPR8: + case XED_IFORM_SETNBE_MEMb: + case XED_IFORM_SETNL_GPR8: + case XED_IFORM_SETNL_MEMb: + case XED_IFORM_SETNLE_GPR8: + case XED_IFORM_SETNLE_MEMb: + case XED_IFORM_SETNO_GPR8: + case XED_IFORM_SETNO_MEMb: + case XED_IFORM_SETNP_GPR8: + case XED_IFORM_SETNP_MEMb: + case XED_IFORM_SETNS_GPR8: + case XED_IFORM_SETNS_MEMb: + case XED_IFORM_SETNZ_GPR8: + case XED_IFORM_SETNZ_MEMb: + case XED_IFORM_SETO_GPR8: + case XED_IFORM_SETO_MEMb: + case XED_IFORM_SETP_GPR8: + case XED_IFORM_SETP_MEMb: + case XED_IFORM_SETS_GPR8: + case XED_IFORM_SETS_MEMb: + case XED_IFORM_SETSSBSY: + case XED_IFORM_SETZ_GPR8: + case XED_IFORM_SETZ_MEMb: + case XED_IFORM_SFENCE: + case XED_IFORM_SGDT_MEMs: + case XED_IFORM_SGDT_MEMs64: + case XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA: + case XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA: + case XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA: + case XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA: + case XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA: + case XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA: + case XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA: + case XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA: + case XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA: + case XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA: + case XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA: + case XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA: + case XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA: + case XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA: + case XED_IFORM_SHL_GPR8_CL_D2r4: + case XED_IFORM_SHL_GPR8_CL_D2r6: + case XED_IFORM_SHL_GPR8_IMMb_C0r4: + case XED_IFORM_SHL_GPR8_IMMb_C0r6: + case XED_IFORM_SHL_GPR8_ONE_D0r4: + case XED_IFORM_SHL_GPR8_ONE_D0r6: + case XED_IFORM_SHL_GPRv_CL_D3r4: + case XED_IFORM_SHL_GPRv_CL_D3r6: + case XED_IFORM_SHL_GPRv_IMMb_C1r4: + case XED_IFORM_SHL_GPRv_IMMb_C1r6: + case XED_IFORM_SHL_GPRv_ONE_D1r4: + case XED_IFORM_SHL_GPRv_ONE_D1r6: + case XED_IFORM_SHL_MEMb_CL_D2r4: + case XED_IFORM_SHL_MEMb_CL_D2r6: + case XED_IFORM_SHL_MEMb_IMMb_C0r4: + case XED_IFORM_SHL_MEMb_IMMb_C0r6: + case XED_IFORM_SHL_MEMb_ONE_D0r4: + case XED_IFORM_SHL_MEMb_ONE_D0r6: + case XED_IFORM_SHL_MEMv_CL_D3r4: + case XED_IFORM_SHL_MEMv_CL_D3r6: + case XED_IFORM_SHL_MEMv_IMMb_C1r4: + case XED_IFORM_SHL_MEMv_IMMb_C1r6: + case XED_IFORM_SHL_MEMv_ONE_D1r4: + case XED_IFORM_SHL_MEMv_ONE_D1r6: + case XED_IFORM_SHLD_GPRv_GPRv_CL: + case XED_IFORM_SHLD_GPRv_GPRv_IMMb: + case XED_IFORM_SHLD_MEMv_GPRv_CL: + case XED_IFORM_SHLD_MEMv_GPRv_IMMb: + case XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d: + case XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q: + case XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_SHR_GPR8_CL: + case XED_IFORM_SHR_GPR8_IMMb: + case XED_IFORM_SHR_GPR8_ONE: + case XED_IFORM_SHR_GPRv_CL: + case XED_IFORM_SHR_GPRv_IMMb: + case XED_IFORM_SHR_GPRv_ONE: + case XED_IFORM_SHR_MEMb_CL: + case XED_IFORM_SHR_MEMb_IMMb: + case XED_IFORM_SHR_MEMb_ONE: + case XED_IFORM_SHR_MEMv_CL: + case XED_IFORM_SHR_MEMv_IMMb: + case XED_IFORM_SHR_MEMv_ONE: + case XED_IFORM_SHRD_GPRv_GPRv_CL: + case XED_IFORM_SHRD_GPRv_GPRv_IMMb: + case XED_IFORM_SHRD_MEMv_GPRv_CL: + case XED_IFORM_SHRD_MEMv_GPRv_IMMb: + case XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d: + case XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d: + case XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q: + case XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q: + case XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb: + case XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb: + case XED_IFORM_SHUFPS_XMMps_MEMps_IMMb: + case XED_IFORM_SHUFPS_XMMps_XMMps_IMMb: + case XED_IFORM_SIDT_MEMs: + case XED_IFORM_SIDT_MEMs64: + case XED_IFORM_SKINIT_EAX: + case XED_IFORM_SLDT_GPRv: + case XED_IFORM_SLDT_MEMw: + case XED_IFORM_SLWPCB_VGPRyy: + case XED_IFORM_SMSW_GPRv: + case XED_IFORM_SMSW_MEMw: + case XED_IFORM_SQRTPD_XMMpd_MEMpd: + case XED_IFORM_SQRTPD_XMMpd_XMMpd: + case XED_IFORM_SQRTPS_XMMps_MEMps: + case XED_IFORM_SQRTPS_XMMps_XMMps: + case XED_IFORM_SQRTSD_XMMsd_MEMsd: + case XED_IFORM_SQRTSD_XMMsd_XMMsd: + case XED_IFORM_SQRTSS_XMMss_MEMss: + case XED_IFORM_SQRTSS_XMMss_XMMss: + case XED_IFORM_STAC: + case XED_IFORM_STC: + case XED_IFORM_STD: + case XED_IFORM_STGI: + case XED_IFORM_STI: + case XED_IFORM_STMXCSR_MEMd: + case XED_IFORM_STOSB: + case XED_IFORM_STOSD: + case XED_IFORM_STOSQ: + case XED_IFORM_STOSW: + case XED_IFORM_STR_GPRv: + case XED_IFORM_STR_MEMw: + case XED_IFORM_STTILECFG_MEM: + case XED_IFORM_STUI: + case XED_IFORM_SUB_AL_IMMb: + case XED_IFORM_SUB_GPR8_GPR8_28: + case XED_IFORM_SUB_GPR8_GPR8_2A: + case XED_IFORM_SUB_GPR8_IMMb_80r5: + case XED_IFORM_SUB_GPR8_IMMb_82r5: + case XED_IFORM_SUB_GPR8_MEMb: + case XED_IFORM_SUB_GPRv_GPRv_29: + case XED_IFORM_SUB_GPRv_GPRv_2B: + case XED_IFORM_SUB_GPRv_IMMb: + case XED_IFORM_SUB_GPRv_IMMz: + case XED_IFORM_SUB_GPRv_MEMv: + case XED_IFORM_SUB_MEMb_GPR8: + case XED_IFORM_SUB_MEMb_IMMb_80r5: + case XED_IFORM_SUB_MEMb_IMMb_82r5: + case XED_IFORM_SUB_MEMv_GPRv: + case XED_IFORM_SUB_MEMv_IMMb: + case XED_IFORM_SUB_MEMv_IMMz: + case XED_IFORM_SUB_OrAX_IMMz: + case XED_IFORM_SUBPD_XMMpd_MEMpd: + case XED_IFORM_SUBPD_XMMpd_XMMpd: + case XED_IFORM_SUBPS_XMMps_MEMps: + case XED_IFORM_SUBPS_XMMps_XMMps: + case XED_IFORM_SUBSD_XMMsd_MEMsd: + case XED_IFORM_SUBSD_XMMsd_XMMsd: + case XED_IFORM_SUBSS_XMMss_MEMss: + case XED_IFORM_SUBSS_XMMss_XMMss: + case XED_IFORM_SUB_LOCK_MEMb_GPR8: + case XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5: + case XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5: + case XED_IFORM_SUB_LOCK_MEMv_GPRv: + case XED_IFORM_SUB_LOCK_MEMv_IMMb: + case XED_IFORM_SUB_LOCK_MEMv_IMMz: + case XED_IFORM_SWAPGS: + case XED_IFORM_SYSCALL: + case XED_IFORM_SYSCALL_AMD: + case XED_IFORM_SYSENTER: + case XED_IFORM_SYSEXIT: + case XED_IFORM_SYSRET: + case XED_IFORM_SYSRET64: + case XED_IFORM_SYSRET_AMD: + case XED_IFORM_T1MSKC_VGPR32d_MEMd: + case XED_IFORM_T1MSKC_VGPR32d_VGPR32d: + case XED_IFORM_T1MSKC_VGPRyy_MEMy: + case XED_IFORM_T1MSKC_VGPRyy_VGPRyy: + case XED_IFORM_TDCALL: + case XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32: + case XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32: + case XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32: + case XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32: + case XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32: + case XED_IFORM_TEST_AL_IMMb: + case XED_IFORM_TEST_GPR8_GPR8: + case XED_IFORM_TEST_GPR8_IMMb_F6r0: + case XED_IFORM_TEST_GPR8_IMMb_F6r1: + case XED_IFORM_TEST_GPRv_GPRv: + case XED_IFORM_TEST_GPRv_IMMz_F7r0: + case XED_IFORM_TEST_GPRv_IMMz_F7r1: + case XED_IFORM_TEST_MEMb_GPR8: + case XED_IFORM_TEST_MEMb_IMMb_F6r0: + case XED_IFORM_TEST_MEMb_IMMb_F6r1: + case XED_IFORM_TEST_MEMv_GPRv: + case XED_IFORM_TEST_MEMv_IMMz_F7r0: + case XED_IFORM_TEST_MEMv_IMMz_F7r1: + case XED_IFORM_TEST_OrAX_IMMz: + case XED_IFORM_TESTUI: + case XED_IFORM_TILELOADD_TMMu32_MEMu32: + case XED_IFORM_TILELOADDT1_TMMu32_MEMu32: + case XED_IFORM_TILERELEASE: + case XED_IFORM_TILESTORED_MEMu32_TMMu32: + case XED_IFORM_TILEZERO_TMMu32: + case XED_IFORM_TLBSYNC: + case XED_IFORM_TPAUSE_GPR32u32: + case XED_IFORM_TZCNT_GPRv_GPRv: + case XED_IFORM_TZCNT_GPRv_MEMv: + case XED_IFORM_TZMSK_VGPR32d_MEMd: + case XED_IFORM_TZMSK_VGPR32d_VGPR32d: + case XED_IFORM_TZMSK_VGPRyy_MEMy: + case XED_IFORM_TZMSK_VGPRyy_VGPRyy: + case XED_IFORM_UCOMISD_XMMsd_MEMsd: + case XED_IFORM_UCOMISD_XMMsd_XMMsd: + case XED_IFORM_UCOMISS_XMMss_MEMss: + case XED_IFORM_UCOMISS_XMMss_XMMss: + case XED_IFORM_UD0: + case XED_IFORM_UD0_GPR32_GPR32: + case XED_IFORM_UD0_GPR32_MEMd: + case XED_IFORM_UD1_GPR32_GPR32: + case XED_IFORM_UD1_GPR32_MEMd: + case XED_IFORM_UD2: + case XED_IFORM_UIRET: + case XED_IFORM_UMONITOR_GPRa: + case XED_IFORM_UMWAIT_GPR32: + case XED_IFORM_UNPCKHPD_XMMpd_MEMdq: + case XED_IFORM_UNPCKHPD_XMMpd_XMMq: + case XED_IFORM_UNPCKHPS_XMMps_MEMdq: + case XED_IFORM_UNPCKHPS_XMMps_XMMdq: + case XED_IFORM_UNPCKLPD_XMMpd_MEMdq: + case XED_IFORM_UNPCKLPD_XMMpd_XMMq: + case XED_IFORM_UNPCKLPS_XMMps_MEMdq: + case XED_IFORM_UNPCKLPS_XMMps_XMMq: + case XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512: + case XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512: + case XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128: + case XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512: + case XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128: + case XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512: + case XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512: + case XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512: + case XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512: + case XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512: + case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128: + case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512: + case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128: + case XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512: + case XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512: + case XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + case XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512: + case XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512: + case XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128: + case XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512: + case XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128: + case XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512: + case XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512: + case XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512: + case XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512: + case XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512: + case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128: + case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512: + case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128: + case XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512: + case XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512: + case XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512: + case XED_IFORM_VAESIMC_XMMdq_MEMdq: + case XED_IFORM_VAESIMC_XMMdq_XMMdq: + case XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb: + case XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb: + case XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + case XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VBROADCASTF128_YMMqq_MEMdq: + case XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VBROADCASTI128_YMMqq_MEMdq: + case XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VBROADCASTSD_YMMqq_MEMq: + case XED_IFORM_VBROADCASTSD_YMMqq_XMMdq: + case XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VBROADCASTSS_XMMdq_MEMd: + case XED_IFORM_VBROADCASTSS_XMMdq_XMMdq: + case XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VBROADCASTSS_YMMqq_MEMd: + case XED_IFORM_VBROADCASTSS_YMMqq_XMMdq: + case XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + case XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512: + case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512: + case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512: + case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + case XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb: + case XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb: + case XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512: + case XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb: + case XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb: + case XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512: + case XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512: + case XED_IFORM_VCOMISD_XMMq_MEMq: + case XED_IFORM_VCOMISD_XMMq_XMMq: + case XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512: + case XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512: + case XED_IFORM_VCOMISS_XMMd_MEMd: + case XED_IFORM_VCOMISS_XMMd_XMMd: + case XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512: + case XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512: + case XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTDQ2PD_XMMdq_MEMq: + case XED_IFORM_VCVTDQ2PD_XMMdq_XMMq: + case XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq: + case XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq: + case XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128: + case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256: + case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq: + case XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq: + case XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq: + case XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq: + case XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128: + case XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256: + case XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512: + case XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128: + case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256: + case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512: + case XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq: + case XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq: + case XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq: + case XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq: + case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCVTPD2PS_XMMdq_MEMdq: + case XED_IFORM_VCVTPD2PS_XMMdq_MEMqq: + case XED_IFORM_VCVTPD2PS_XMMdq_XMMdq: + case XED_IFORM_VCVTPD2PS_XMMdq_YMMqq: + case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PS_XMMdq_MEMq: + case XED_IFORM_VCVTPH2PS_XMMdq_XMMq: + case XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PS_YMMqq_MEMdq: + case XED_IFORM_VCVTPH2PS_YMMqq_XMMdq: + case XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq: + case XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq: + case XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq: + case XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq: + case XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTPS2PD_XMMdq_MEMq: + case XED_IFORM_VCVTPS2PD_XMMdq_XMMq: + case XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2PD_YMMqq_MEMdq: + case XED_IFORM_VCVTPS2PD_YMMqq_XMMdq: + case XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb: + case XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb: + case XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb: + case XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb: + case XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128: + case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256: + case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512: + case XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128: + case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256: + case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512: + case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128: + case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256: + case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + case XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + case XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512: + case XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + case XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VCVTSD2SI_GPR32d_MEMq: + case XED_IFORM_VCVTSD2SI_GPR32d_XMMq: + case XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512: + case XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512: + case XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512: + case XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512: + case XED_IFORM_VCVTSD2SI_GPR64q_MEMq: + case XED_IFORM_VCVTSD2SI_GPR64q_XMMq: + case XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq: + case XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq: + case XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512: + case XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512: + case XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512: + case XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512: + case XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512: + case XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512: + case XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512: + case XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512: + case XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512: + case XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512: + case XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512: + case XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512: + case XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512: + case XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512: + case XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512: + case XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512: + case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d: + case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q: + case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd: + case XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512: + case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512: + case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512: + case XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512: + case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512: + case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512: + case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512: + case XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512: + case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d: + case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q: + case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq: + case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512: + case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512: + case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512: + case XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512: + case XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd: + case XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd: + case XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512: + case XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512: + case XED_IFORM_VCVTSS2SI_GPR32d_MEMd: + case XED_IFORM_VCVTSS2SI_GPR32d_XMMd: + case XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512: + case XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512: + case XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512: + case XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512: + case XED_IFORM_VCVTSS2SI_GPR64q_MEMd: + case XED_IFORM_VCVTSS2SI_GPR64q_XMMd: + case XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512: + case XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512: + case XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512: + case XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512: + case XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq: + case XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq: + case XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq: + case XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq: + case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq: + case XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq: + case XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq: + case XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq: + case XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VCVTTSD2SI_GPR32d_MEMq: + case XED_IFORM_VCVTTSD2SI_GPR32d_XMMq: + case XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512: + case XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512: + case XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512: + case XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512: + case XED_IFORM_VCVTTSD2SI_GPR64q_MEMq: + case XED_IFORM_VCVTTSD2SI_GPR64q_XMMq: + case XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512: + case XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512: + case XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512: + case XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512: + case XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512: + case XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512: + case XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512: + case XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512: + case XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512: + case XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512: + case XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512: + case XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512: + case XED_IFORM_VCVTTSS2SI_GPR32d_MEMd: + case XED_IFORM_VCVTTSS2SI_GPR32d_XMMd: + case XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512: + case XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512: + case XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512: + case XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512: + case XED_IFORM_VCVTTSS2SI_GPR64q_MEMd: + case XED_IFORM_VCVTTSS2SI_GPR64q_XMMd: + case XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512: + case XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512: + case XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512: + case XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512: + case XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128: + case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256: + case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128: + case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256: + case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512: + case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128: + case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256: + case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128: + case XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256: + case XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512: + case XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512: + case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512: + case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512: + case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512: + case XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512: + case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512: + case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512: + case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512: + case XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512: + case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512: + case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512: + case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512: + case XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512: + case XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512: + case XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512: + case XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + case XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + case XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + case XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VERR_GPR16: + case XED_IFORM_VERR_MEMw: + case XED_IFORM_VERW_GPR16: + case XED_IFORM_VERW_MEMw: + case XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + case XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + case XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + case XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + case XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb: + case XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb: + case XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb: + case XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb: + case XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb: + case XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512: + case XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb: + case XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512: + case XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512: + case XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512: + case XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512: + case XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512: + case XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512: + case XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq: + case XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq: + case XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq: + case XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd: + case XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd: + case XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd: + case XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq: + case XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq: + case XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq: + case XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd: + case XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd: + case XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd: + case XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512: + case XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512: + case XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512: + case XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512: + case XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq: + case XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq: + case XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq: + case XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd: + case XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd: + case XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd: + case XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq: + case XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq: + case XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd: + case XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd: + case XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq: + case XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq: + case XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq: + case XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd: + case XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd: + case XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd: + case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128: + case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256: + case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512: + case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128: + case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256: + case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512: + case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512: + case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512: + case XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512: + case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128: + case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256: + case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512: + case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512: + case XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512: + case XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VFRCZPD_XMMdq_MEMdq: + case XED_IFORM_VFRCZPD_XMMdq_XMMdq: + case XED_IFORM_VFRCZPD_YMMqq_MEMqq: + case XED_IFORM_VFRCZPD_YMMqq_YMMqq: + case XED_IFORM_VFRCZPS_XMMdq_MEMdq: + case XED_IFORM_VFRCZPS_XMMdq_XMMdq: + case XED_IFORM_VFRCZPS_YMMqq_MEMqq: + case XED_IFORM_VFRCZPS_YMMqq_YMMqq: + case XED_IFORM_VFRCZSD_XMMdq_MEMq: + case XED_IFORM_VFRCZSD_XMMdq_XMMq: + case XED_IFORM_VFRCZSS_XMMdq_MEMd: + case XED_IFORM_VFRCZSS_XMMdq_XMMd: + case XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128: + case XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256: + case XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + case XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128: + case XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256: + case XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256: + case XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512: + case XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128: + case XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128: + case XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256: + case XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256: + case XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512: + case XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128: + case XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256: + case XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128: + case XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256: + case XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512: + case XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512: + case XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8: + case XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512: + case XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8: + case XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8: + case XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8: + case XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8: + case XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb: + case XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb: + case XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512: + case XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512: + case XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb: + case XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb: + case XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb: + case XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VLDDQU_XMMdq_MEMdq: + case XED_IFORM_VLDDQU_YMMqq_MEMqq: + case XED_IFORM_VLDMXCSR_MEMd: + case XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq: + case XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq: + case XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq: + case XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq: + case XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq: + case XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMCALL: + case XED_IFORM_VMCLEAR_MEMq: + case XED_IFORM_VMFUNC: + case XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMLAUNCH: + case XED_IFORM_VMLOAD_ArAX: + case XED_IFORM_VMMCALL: + case XED_IFORM_VMOVAPD_MEMdq_XMMdq: + case XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VMOVAPD_MEMqq_YMMqq: + case XED_IFORM_VMOVAPD_XMMdq_MEMdq: + case XED_IFORM_VMOVAPD_XMMdq_XMMdq_28: + case XED_IFORM_VMOVAPD_XMMdq_XMMdq_29: + case XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VMOVAPD_YMMqq_MEMqq: + case XED_IFORM_VMOVAPD_YMMqq_YMMqq_28: + case XED_IFORM_VMOVAPD_YMMqq_YMMqq_29: + case XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VMOVAPS_MEMdq_XMMdq: + case XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VMOVAPS_MEMqq_YMMqq: + case XED_IFORM_VMOVAPS_XMMdq_MEMdq: + case XED_IFORM_VMOVAPS_XMMdq_XMMdq_28: + case XED_IFORM_VMOVAPS_XMMdq_XMMdq_29: + case XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VMOVAPS_YMMqq_MEMqq: + case XED_IFORM_VMOVAPS_YMMqq_YMMqq_28: + case XED_IFORM_VMOVAPS_YMMqq_YMMqq_29: + case XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VMOVD_GPR32d_XMMd: + case XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512: + case XED_IFORM_VMOVD_MEMd_XMMd: + case XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512: + case XED_IFORM_VMOVD_XMMdq_GPR32d: + case XED_IFORM_VMOVD_XMMdq_MEMd: + case XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512: + case XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512: + case XED_IFORM_VMOVDDUP_XMMdq_MEMq: + case XED_IFORM_VMOVDDUP_XMMdq_XMMq: + case XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VMOVDDUP_YMMqq_MEMqq: + case XED_IFORM_VMOVDDUP_YMMqq_YMMqq: + case XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VMOVDQA_MEMdq_XMMdq: + case XED_IFORM_VMOVDQA_MEMqq_YMMqq: + case XED_IFORM_VMOVDQA_XMMdq_MEMdq: + case XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F: + case XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F: + case XED_IFORM_VMOVDQA_YMMqq_MEMqq: + case XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F: + case XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F: + case XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VMOVDQU_MEMdq_XMMdq: + case XED_IFORM_VMOVDQU_MEMqq_YMMqq: + case XED_IFORM_VMOVDQU_XMMdq_MEMdq: + case XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F: + case XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F: + case XED_IFORM_VMOVDQU_YMMqq_MEMqq: + case XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F: + case XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F: + case XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512: + case XED_IFORM_VMOVHPD_MEMq_XMMdq: + case XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq: + case XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512: + case XED_IFORM_VMOVHPS_MEMq_XMMdq: + case XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq: + case XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq: + case XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512: + case XED_IFORM_VMOVLPD_MEMq_XMMq: + case XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512: + case XED_IFORM_VMOVLPS_MEMq_XMMq: + case XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq: + case XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMOVMSKPD_GPR32d_XMMdq: + case XED_IFORM_VMOVMSKPD_GPR32d_YMMqq: + case XED_IFORM_VMOVMSKPS_GPR32d_XMMdq: + case XED_IFORM_VMOVMSKPS_GPR32d_YMMqq: + case XED_IFORM_VMOVNTDQ_MEMdq_XMMdq: + case XED_IFORM_VMOVNTDQ_MEMqq_YMMqq: + case XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512: + case XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512: + case XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512: + case XED_IFORM_VMOVNTDQA_XMMdq_MEMdq: + case XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512: + case XED_IFORM_VMOVNTDQA_YMMqq_MEMqq: + case XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512: + case XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VMOVNTPD_MEMdq_XMMdq: + case XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512: + case XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512: + case XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512: + case XED_IFORM_VMOVNTPD_MEMqq_YMMqq: + case XED_IFORM_VMOVNTPS_MEMdq_XMMdq: + case XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512: + case XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512: + case XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512: + case XED_IFORM_VMOVNTPS_MEMqq_YMMqq: + case XED_IFORM_VMOVQ_GPR64q_XMMq: + case XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512: + case XED_IFORM_VMOVQ_MEMq_XMMq_7E: + case XED_IFORM_VMOVQ_MEMq_XMMq_D6: + case XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512: + case XED_IFORM_VMOVQ_XMMdq_GPR64q: + case XED_IFORM_VMOVQ_XMMdq_MEMq_6E: + case XED_IFORM_VMOVQ_XMMdq_MEMq_7E: + case XED_IFORM_VMOVQ_XMMdq_XMMq_7E: + case XED_IFORM_VMOVQ_XMMdq_XMMq_D6: + case XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512: + case XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512: + case XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512: + case XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VMOVSD_MEMq_XMMq: + case XED_IFORM_VMOVSD_XMMdq_MEMq: + case XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10: + case XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11: + case XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMOVSHDUP_XMMdq_MEMdq: + case XED_IFORM_VMOVSHDUP_XMMdq_XMMdq: + case XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VMOVSHDUP_YMMqq_MEMqq: + case XED_IFORM_VMOVSHDUP_YMMqq_YMMqq: + case XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VMOVSLDUP_XMMdq_MEMdq: + case XED_IFORM_VMOVSLDUP_XMMdq_XMMdq: + case XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VMOVSLDUP_YMMqq_MEMqq: + case XED_IFORM_VMOVSLDUP_YMMqq_YMMqq: + case XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VMOVSS_MEMd_XMMd: + case XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVSS_XMMdq_MEMd: + case XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10: + case XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11: + case XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMOVUPD_MEMdq_XMMdq: + case XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VMOVUPD_MEMqq_YMMqq: + case XED_IFORM_VMOVUPD_XMMdq_MEMdq: + case XED_IFORM_VMOVUPD_XMMdq_XMMdq_10: + case XED_IFORM_VMOVUPD_XMMdq_XMMdq_11: + case XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VMOVUPD_YMMqq_MEMqq: + case XED_IFORM_VMOVUPD_YMMqq_YMMqq_10: + case XED_IFORM_VMOVUPD_YMMqq_YMMqq_11: + case XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VMOVUPS_MEMdq_XMMdq: + case XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VMOVUPS_MEMqq_YMMqq: + case XED_IFORM_VMOVUPS_XMMdq_MEMdq: + case XED_IFORM_VMOVUPS_XMMdq_XMMdq_10: + case XED_IFORM_VMOVUPS_XMMdq_XMMdq_11: + case XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VMOVUPS_YMMqq_MEMqq: + case XED_IFORM_VMOVUPS_YMMqq_YMMqq_10: + case XED_IFORM_VMOVUPS_YMMqq_YMMqq_11: + case XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512: + case XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512: + case XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512: + case XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VMPTRLD_MEMq: + case XED_IFORM_VMPTRST_MEMq: + case XED_IFORM_VMREAD_GPR32_GPR32: + case XED_IFORM_VMREAD_GPR64_GPR64: + case XED_IFORM_VMREAD_MEMd_GPR32: + case XED_IFORM_VMREAD_MEMq_GPR64: + case XED_IFORM_VMRESUME: + case XED_IFORM_VMRUN_ArAX: + case XED_IFORM_VMSAVE: + case XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VMWRITE_GPR32_GPR32: + case XED_IFORM_VMWRITE_GPR32_MEMd: + case XED_IFORM_VMWRITE_GPR64_GPR64: + case XED_IFORM_VMWRITE_GPR64_MEMq: + case XED_IFORM_VMXOFF: + case XED_IFORM_VMXON_MEMq: + case XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + case XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + case XED_IFORM_VPABSB_XMMdq_MEMdq: + case XED_IFORM_VPABSB_XMMdq_XMMdq: + case XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512: + case XED_IFORM_VPABSB_YMMqq_MEMqq: + case XED_IFORM_VPABSB_YMMqq_YMMqq: + case XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512: + case XED_IFORM_VPABSD_XMMdq_MEMdq: + case XED_IFORM_VPABSD_XMMdq_XMMdq: + case XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPABSD_YMMqq_MEMqq: + case XED_IFORM_VPABSD_YMMqq_YMMqq: + case XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512: + case XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512: + case XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512: + case XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPABSW_XMMdq_MEMdq: + case XED_IFORM_VPABSW_XMMdq_XMMdq: + case XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512: + case XED_IFORM_VPABSW_YMMqq_MEMqq: + case XED_IFORM_VPABSW_YMMqq_YMMqq: + case XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512: + case XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512: + case XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512: + case XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512: + case XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512: + case XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512: + case XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512: + case XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + case XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + case XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + case XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + case XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + case XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + case XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + case XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + case XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + case XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPBROADCASTB_XMMdq_MEMb: + case XED_IFORM_VPBROADCASTB_XMMdq_XMMb: + case XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512: + case XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPBROADCASTB_YMMqq_MEMb: + case XED_IFORM_VPBROADCASTB_YMMqq_XMMb: + case XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512: + case XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512: + case XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPBROADCASTD_XMMdq_MEMd: + case XED_IFORM_VPBROADCASTD_XMMdq_XMMd: + case XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512: + case XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPBROADCASTD_YMMqq_MEMd: + case XED_IFORM_VPBROADCASTD_YMMqq_XMMd: + case XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512: + case XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512: + case XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512: + case XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512: + case XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD: + case XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512: + case XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512: + case XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD: + case XED_IFORM_VPBROADCASTQ_XMMdq_MEMq: + case XED_IFORM_VPBROADCASTQ_XMMdq_XMMq: + case XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512: + case XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPBROADCASTQ_YMMqq_MEMq: + case XED_IFORM_VPBROADCASTQ_YMMqq_XMMq: + case XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512: + case XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512: + case XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPBROADCASTW_XMMdq_MEMw: + case XED_IFORM_VPBROADCASTW_XMMdq_XMMw: + case XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512: + case XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPBROADCASTW_YMMqq_MEMw: + case XED_IFORM_VPBROADCASTW_YMMqq_XMMw: + case XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512: + case XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512: + case XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8: + case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8: + case XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq: + case XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512: + case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512: + case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512: + case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512: + case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512: + case XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512: + case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512: + case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512: + case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512: + case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512: + case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512: + case XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512: + case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512: + case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512: + case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512: + case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512: + case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512: + case XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512: + case XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512: + case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512: + case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512: + case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512: + case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512: + case XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512: + case XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512: + case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512: + case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512: + case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512: + case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512: + case XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512: + case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512: + case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512: + case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512: + case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512: + case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512: + case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512: + case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512: + case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512: + case XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512: + case XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD: + case XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + case XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD: + case XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + case XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512: + case XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + case XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32: + case XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32: + case XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512: + case XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + case XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32: + case XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32: + case XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512: + case XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + case XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512: + case XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512: + case XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32: + case XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32: + case XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512: + case XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512: + case XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32: + case XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32: + case XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512: + case XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512: + case XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512: + case XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + case XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32: + case XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32: + case XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512: + case XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + case XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32: + case XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32: + case XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + case XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + case XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512: + case XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512: + case XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32: + case XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32: + case XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512: + case XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512: + case XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32: + case XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32: + case XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512: + case XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512: + case XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb: + case XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb: + case XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb: + case XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb: + case XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb: + case XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512: + case XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb: + case XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512: + case XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb: + case XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512: + case XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb: + case XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb: + case XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb: + case XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15: + case XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5: + case XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512: + case XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512: + case XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb: + case XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5: + case XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + case XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128: + case XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256: + case XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256: + case XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512: + case XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + case XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128: + case XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + case XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256: + case XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + case XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128: + case XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256: + case XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128: + case XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256: + case XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512: + case XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128: + case XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128: + case XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256: + case XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256: + case XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512: + case XED_IFORM_VPHADDBD_XMMdq_MEMdq: + case XED_IFORM_VPHADDBD_XMMdq_XMMdq: + case XED_IFORM_VPHADDBQ_XMMdq_MEMdq: + case XED_IFORM_VPHADDBQ_XMMdq_XMMdq: + case XED_IFORM_VPHADDBW_XMMdq_MEMdq: + case XED_IFORM_VPHADDBW_XMMdq_XMMdq: + case XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPHADDDQ_XMMdq_MEMdq: + case XED_IFORM_VPHADDDQ_XMMdq_XMMdq: + case XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPHADDUBD_XMMdq_MEMdq: + case XED_IFORM_VPHADDUBD_XMMdq_XMMdq: + case XED_IFORM_VPHADDUBQ_XMMdq_MEMdq: + case XED_IFORM_VPHADDUBQ_XMMdq_XMMdq: + case XED_IFORM_VPHADDUBW_XMMdq_MEMdq: + case XED_IFORM_VPHADDUBW_XMMdq_XMMdq: + case XED_IFORM_VPHADDUDQ_XMMdq_MEMdq: + case XED_IFORM_VPHADDUDQ_XMMdq_XMMdq: + case XED_IFORM_VPHADDUWD_XMMdq_MEMdq: + case XED_IFORM_VPHADDUWD_XMMdq_XMMdq: + case XED_IFORM_VPHADDUWQ_XMMdq_MEMdq: + case XED_IFORM_VPHADDUWQ_XMMdq_XMMdq: + case XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPHADDWD_XMMdq_MEMdq: + case XED_IFORM_VPHADDWD_XMMdq_XMMdq: + case XED_IFORM_VPHADDWQ_XMMdq_MEMdq: + case XED_IFORM_VPHADDWQ_XMMdq_XMMdq: + case XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq: + case XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq: + case XED_IFORM_VPHSUBBW_XMMdq_MEMdq: + case XED_IFORM_VPHSUBBW_XMMdq_XMMdq: + case XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPHSUBDQ_XMMdq_MEMdq: + case XED_IFORM_VPHSUBDQ_XMMdq_XMMdq: + case XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPHSUBWD_XMMdq_MEMdq: + case XED_IFORM_VPHSUBWD_XMMdq_XMMdq: + case XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb: + case XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb: + case XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512: + case XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb: + case XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb: + case XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512: + case XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb: + case XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb: + case XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512: + case XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb: + case XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb: + case XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512: + case XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD: + case XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD: + case XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD: + case XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD: + case XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq: + case XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq: + case XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq: + case XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq: + case XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + case XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + case XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + case XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + case XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + case XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + case XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512: + case XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + case XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512: + case XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + case XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512: + case XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + case XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512: + case XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + case XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512: + case XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + case XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512: + case XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + case XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + case XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + case XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + case XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + case XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + case XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + case XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512: + case XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512: + case XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512: + case XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512: + case XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512: + case XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512: + case XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512: + case XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512: + case XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512: + case XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512: + case XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512: + case XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512: + case XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512: + case XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512: + case XED_IFORM_VPMOVMSKB_GPR32d_XMMdq: + case XED_IFORM_VPMOVMSKB_GPR32d_YMMqq: + case XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512: + case XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512: + case XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512: + case XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512: + case XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512: + case XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512: + case XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512: + case XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512: + case XED_IFORM_VPMOVSXBD_XMMdq_MEMd: + case XED_IFORM_VPMOVSXBD_XMMdq_XMMd: + case XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBD_YMMqq_MEMq: + case XED_IFORM_VPMOVSXBD_YMMqq_XMMq: + case XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBQ_XMMdq_MEMw: + case XED_IFORM_VPMOVSXBQ_XMMdq_XMMw: + case XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBQ_YMMqq_MEMd: + case XED_IFORM_VPMOVSXBQ_YMMqq_XMMd: + case XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBW_XMMdq_MEMq: + case XED_IFORM_VPMOVSXBW_XMMdq_XMMq: + case XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVSXBW_YMMqq_MEMdq: + case XED_IFORM_VPMOVSXBW_YMMqq_XMMdq: + case XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + case XED_IFORM_VPMOVSXDQ_XMMdq_MEMq: + case XED_IFORM_VPMOVSXDQ_XMMdq_XMMq: + case XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq: + case XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq: + case XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPMOVSXWD_XMMdq_MEMq: + case XED_IFORM_VPMOVSXWD_XMMdq_XMMq: + case XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVSXWD_YMMqq_MEMdq: + case XED_IFORM_VPMOVSXWD_YMMqq_XMMdq: + case XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + case XED_IFORM_VPMOVSXWQ_XMMdq_MEMd: + case XED_IFORM_VPMOVSXWQ_XMMdq_XMMd: + case XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVSXWQ_YMMqq_MEMq: + case XED_IFORM_VPMOVSXWQ_YMMqq_XMMq: + case XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPMOVZXBD_XMMdq_MEMd: + case XED_IFORM_VPMOVZXBD_XMMdq_XMMd: + case XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBD_YMMqq_MEMq: + case XED_IFORM_VPMOVZXBD_YMMqq_XMMq: + case XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBQ_XMMdq_MEMw: + case XED_IFORM_VPMOVZXBQ_XMMdq_XMMw: + case XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBQ_YMMqq_MEMd: + case XED_IFORM_VPMOVZXBQ_YMMqq_XMMd: + case XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBW_XMMdq_MEMq: + case XED_IFORM_VPMOVZXBW_XMMdq_XMMq: + case XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512: + case XED_IFORM_VPMOVZXBW_YMMqq_MEMdq: + case XED_IFORM_VPMOVZXBW_YMMqq_XMMdq: + case XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512: + case XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512: + case XED_IFORM_VPMOVZXDQ_XMMdq_MEMq: + case XED_IFORM_VPMOVZXDQ_XMMdq_XMMq: + case XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512: + case XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq: + case XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq: + case XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512: + case XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512: + case XED_IFORM_VPMOVZXWD_XMMdq_MEMq: + case XED_IFORM_VPMOVZXWD_XMMdq_XMMq: + case XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVZXWD_YMMqq_MEMdq: + case XED_IFORM_VPMOVZXWD_YMMqq_XMMdq: + case XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512: + case XED_IFORM_VPMOVZXWQ_XMMdq_MEMd: + case XED_IFORM_VPMOVZXWQ_XMMdq_XMMd: + case XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMOVZXWQ_YMMqq_MEMq: + case XED_IFORM_VPMOVZXWQ_YMMqq_XMMq: + case XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512: + case XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512: + case XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512: + case XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512: + case XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512: + case XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512: + case XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512: + case XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512: + case XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512: + case XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512: + case XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512: + case XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512: + case XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512: + case XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512: + case XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512: + case XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512: + case XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512: + case XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512: + case XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512: + case XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512: + case XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512: + case XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512: + case XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512: + case XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512: + case XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512: + case XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512: + case XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512: + case XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512: + case XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512: + case XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512: + case XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + case XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + case XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + case XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + case XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + case XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256: + case XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512: + case XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + case XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + case XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + case XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128: + case XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256: + case XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512: + case XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128: + case XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256: + case XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512: + case XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq: + case XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512: + case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512: + case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512: + case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512: + case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512: + case XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512: + case XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + case XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb: + case XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb: + case XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + case XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + case XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512: + case XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512: + case XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + case XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + case XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + case XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512: + case XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512: + case XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512: + case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512: + case XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512: + case XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512: + case XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512: + case XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512: + case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512: + case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512: + case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb: + case XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512: + case XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb: + case XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq: + case XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq: + case XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512: + case XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512: + case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512: + case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512: + case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512: + case XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512: + case XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512: + case XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512: + case XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512: + case XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512: + case XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512: + case XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512: + case XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512: + case XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512: + case XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512: + case XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512: + case XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512: + case XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512: + case XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + case XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512: + case XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VPTEST_XMMdq_MEMdq: + case XED_IFORM_VPTEST_XMMdq_XMMdq: + case XED_IFORM_VPTEST_YMMqq_MEMqq: + case XED_IFORM_VPTEST_YMMqq_YMMqq: + case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512: + case XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512: + case XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512: + case XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512: + case XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512: + case XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512: + case XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512: + case XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512: + case XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512: + case XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512: + case XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512: + case XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512: + case XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + case XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + case XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + case XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + case XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + case XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + case XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + case XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + case XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER: + case XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + case XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER: + case XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + case XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VRCPPS_XMMdq_MEMdq: + case XED_IFORM_VRCPPS_XMMdq_XMMdq: + case XED_IFORM_VRCPPS_YMMqq_MEMqq: + case XED_IFORM_VRCPPS_YMMqq_YMMqq: + case XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + case XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512: + case XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512: + case XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512: + case XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512: + case XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512: + case XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb: + case XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb: + case XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb: + case XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb: + case XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb: + case XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb: + case XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb: + case XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb: + case XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb: + case XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb: + case XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb: + case XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb: + case XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER: + case XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER: + case XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER: + case XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER: + case XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER: + case XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER: + case XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER: + case XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER: + case XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VRSQRTPS_XMMdq_MEMdq: + case XED_IFORM_VRSQRTPS_XMMdq_XMMdq: + case XED_IFORM_VRSQRTPS_YMMqq_MEMqq: + case XED_IFORM_VRSQRTPS_YMMqq_YMMqq: + case XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + case XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256: + case XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512: + case XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512: + case XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128: + case XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256: + case XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512: + case XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128: + case XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256: + case XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512: + case XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + case XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + case XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + case XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + case XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512: + case XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512: + case XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512: + case XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512: + case XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512: + case XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512: + case XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512: + case XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512: + case XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512: + case XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512: + case XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb: + case XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb: + case XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512: + case XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512: + case XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb: + case XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb: + case XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512: + case XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512: + case XED_IFORM_VSQRTPD_XMMdq_MEMdq: + case XED_IFORM_VSQRTPD_XMMdq_XMMdq: + case XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512: + case XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512: + case XED_IFORM_VSQRTPD_YMMqq_MEMqq: + case XED_IFORM_VSQRTPD_YMMqq_YMMqq: + case XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512: + case XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512: + case XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512: + case XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512: + case XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512: + case XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512: + case XED_IFORM_VSQRTPS_XMMdq_MEMdq: + case XED_IFORM_VSQRTPS_XMMdq_XMMdq: + case XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512: + case XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512: + case XED_IFORM_VSQRTPS_YMMqq_MEMqq: + case XED_IFORM_VSQRTPS_YMMqq_YMMqq: + case XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512: + case XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512: + case XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VSTMXCSR_MEMd: + case XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512: + case XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512: + case XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512: + case XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512: + case XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq: + case XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq: + case XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512: + case XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512: + case XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd: + case XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd: + case XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VTESTPD_XMMdq_MEMdq: + case XED_IFORM_VTESTPD_XMMdq_XMMdq: + case XED_IFORM_VTESTPD_YMMqq_MEMqq: + case XED_IFORM_VTESTPD_YMMqq_YMMqq: + case XED_IFORM_VTESTPS_XMMdq_MEMdq: + case XED_IFORM_VTESTPS_XMMdq_XMMdq: + case XED_IFORM_VTESTPS_YMMqq_MEMqq: + case XED_IFORM_VTESTPS_YMMqq_YMMqq: + case XED_IFORM_VUCOMISD_XMMdq_MEMq: + case XED_IFORM_VUCOMISD_XMMdq_XMMq: + case XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512: + case XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512: + case XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512: + case XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512: + case XED_IFORM_VUCOMISS_XMMdq_MEMd: + case XED_IFORM_VUCOMISS_XMMdq_XMMd: + case XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512: + case XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512: + case XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512: + case XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512: + case XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512: + case XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512: + case XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512: + case XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512: + case XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512: + case XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512: + case XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512: + case XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512: + case XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512: + case XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512: + case XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512: + case XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512: + case XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512: + case XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512: + case XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512: + case XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512: + case XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq: + case XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq: + case XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512: + case XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512: + case XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq: + case XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq: + case XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512: + case XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512: + case XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512: + case XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512: + case XED_IFORM_VZEROALL: + case XED_IFORM_VZEROUPPER: + case XED_IFORM_WBINVD: + case XED_IFORM_WBNOINVD: + case XED_IFORM_WRFSBASE_GPRy: + case XED_IFORM_WRGSBASE_GPRy: + case XED_IFORM_WRMSR: + case XED_IFORM_WRPKRU: + case XED_IFORM_WRSSD_MEMu32_GPR32u32: + case XED_IFORM_WRSSQ_MEMu64_GPR64u64: + case XED_IFORM_WRUSSD_MEMu32_GPR32u32: + case XED_IFORM_WRUSSQ_MEMu64_GPR64u64: + case XED_IFORM_XABORT_IMMb: + case XED_IFORM_XADD_GPR8_GPR8: + case XED_IFORM_XADD_GPRv_GPRv: + case XED_IFORM_XADD_MEMb_GPR8: + case XED_IFORM_XADD_MEMv_GPRv: + case XED_IFORM_XADD_LOCK_MEMb_GPR8: + case XED_IFORM_XADD_LOCK_MEMv_GPRv: + case XED_IFORM_XBEGIN_RELBRz: + case XED_IFORM_XCHG_GPR8_GPR8: + case XED_IFORM_XCHG_GPRv_GPRv: + case XED_IFORM_XCHG_GPRv_OrAX: + case XED_IFORM_XCHG_MEMb_GPR8: + case XED_IFORM_XCHG_MEMv_GPRv: + case XED_IFORM_XEND: + case XED_IFORM_XGETBV: + case XED_IFORM_XLAT: + case XED_IFORM_XOR_AL_IMMb: + case XED_IFORM_XOR_GPR8_GPR8_30: + case XED_IFORM_XOR_GPR8_GPR8_32: + case XED_IFORM_XOR_GPR8_IMMb_80r6: + case XED_IFORM_XOR_GPR8_IMMb_82r6: + case XED_IFORM_XOR_GPR8_MEMb: + case XED_IFORM_XOR_GPRv_GPRv_31: + case XED_IFORM_XOR_GPRv_GPRv_33: + case XED_IFORM_XOR_GPRv_IMMb: + case XED_IFORM_XOR_GPRv_IMMz: + case XED_IFORM_XOR_GPRv_MEMv: + case XED_IFORM_XOR_MEMb_GPR8: + case XED_IFORM_XOR_MEMb_IMMb_80r6: + case XED_IFORM_XOR_MEMb_IMMb_82r6: + case XED_IFORM_XOR_MEMv_GPRv: + case XED_IFORM_XOR_MEMv_IMMb: + case XED_IFORM_XOR_MEMv_IMMz: + case XED_IFORM_XOR_OrAX_IMMz: + case XED_IFORM_XORPD_XMMxuq_MEMxuq: + case XED_IFORM_XORPD_XMMxuq_XMMxuq: + case XED_IFORM_XORPS_XMMxud_MEMxud: + case XED_IFORM_XORPS_XMMxud_XMMxud: + case XED_IFORM_XOR_LOCK_MEMb_GPR8: + case XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6: + case XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6: + case XED_IFORM_XOR_LOCK_MEMv_GPRv: + case XED_IFORM_XOR_LOCK_MEMv_IMMb: + case XED_IFORM_XOR_LOCK_MEMv_IMMz: + case XED_IFORM_XRESLDTRK: + case XED_IFORM_XRSTOR_MEMmxsave: + case XED_IFORM_XRSTOR64_MEMmxsave: + case XED_IFORM_XRSTORS_MEMmxsave: + case XED_IFORM_XRSTORS64_MEMmxsave: + case XED_IFORM_XSAVE_MEMmxsave: + case XED_IFORM_XSAVE64_MEMmxsave: + case XED_IFORM_XSAVEC_MEMmxsave: + case XED_IFORM_XSAVEC64_MEMmxsave: + case XED_IFORM_XSAVEOPT_MEMmxsave: + case XED_IFORM_XSAVEOPT64_MEMmxsave: + case XED_IFORM_XSAVES_MEMmxsave: + case XED_IFORM_XSAVES64_MEMmxsave: + case XED_IFORM_XSETBV: + case XED_IFORM_XSTORE: + case XED_IFORM_XSUSLDTRK: + case XED_IFORM_XTEST: + case XED_IFORM_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-iform-enum.h b/CodeVirtualizer/build/obj/xed-iform-enum.h new file mode 100644 index 0000000..77c78a3 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iform-enum.h @@ -0,0 +1,13762 @@ +/// @file xed-iform-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_IFORM_ENUM_H) +# define XED_IFORM_ENUM_H +#include "xed-common-hdrs.h" +#include "xed-iclass-enum.h" +#define XED_IFORM_INVALID_DEFINED 1 +#define XED_IFORM_AAA_DEFINED 1 +#define XED_IFORM_AAD_IMMb_DEFINED 1 +#define XED_IFORM_AAM_IMMb_DEFINED 1 +#define XED_IFORM_AAS_DEFINED 1 +#define XED_IFORM_ADC_AL_IMMb_DEFINED 1 +#define XED_IFORM_ADC_GPR8_GPR8_10_DEFINED 1 +#define XED_IFORM_ADC_GPR8_GPR8_12_DEFINED 1 +#define XED_IFORM_ADC_GPR8_IMMb_80r2_DEFINED 1 +#define XED_IFORM_ADC_GPR8_IMMb_82r2_DEFINED 1 +#define XED_IFORM_ADC_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_ADC_GPRv_GPRv_11_DEFINED 1 +#define XED_IFORM_ADC_GPRv_GPRv_13_DEFINED 1 +#define XED_IFORM_ADC_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ADC_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_ADC_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_ADC_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADC_MEMb_IMMb_80r2_DEFINED 1 +#define XED_IFORM_ADC_MEMb_IMMb_82r2_DEFINED 1 +#define XED_IFORM_ADC_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADC_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADC_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADC_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ADCX_GPR32d_GPR32d_DEFINED 1 +#define XED_IFORM_ADCX_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_ADCX_GPR64q_GPR64q_DEFINED 1 +#define XED_IFORM_ADCX_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADC_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADD_AL_IMMb_DEFINED 1 +#define XED_IFORM_ADD_GPR8_GPR8_00_DEFINED 1 +#define XED_IFORM_ADD_GPR8_GPR8_02_DEFINED 1 +#define XED_IFORM_ADD_GPR8_IMMb_80r0_DEFINED 1 +#define XED_IFORM_ADD_GPR8_IMMb_82r0_DEFINED 1 +#define XED_IFORM_ADD_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_ADD_GPRv_GPRv_01_DEFINED 1 +#define XED_IFORM_ADD_GPRv_GPRv_03_DEFINED 1 +#define XED_IFORM_ADD_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ADD_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_ADD_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_ADD_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADD_MEMb_IMMb_80r0_DEFINED 1 +#define XED_IFORM_ADD_MEMb_IMMb_82r0_DEFINED 1 +#define XED_IFORM_ADD_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADD_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADD_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADD_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ADDPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_ADDPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_ADDPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_ADDPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_ADDSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_ADDSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_ADDSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_ADDSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_ADDSUBPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_ADDSUBPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_ADDSUBPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_ADDSUBPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ADD_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ADOX_GPR32d_GPR32d_DEFINED 1 +#define XED_IFORM_ADOX_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_ADOX_GPR64q_GPR64q_DEFINED 1 +#define XED_IFORM_ADOX_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_AESDEC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESDEC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESDEC128KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESDEC256KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESDECLAST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESDECLAST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESDECWIDE128KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESDECWIDE256KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESENC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESENC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESENC128KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESENC256KL_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_AESENCLAST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESENCLAST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESENCWIDE128KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESENCWIDE256KL_MEMu8_DEFINED 1 +#define XED_IFORM_AESIMC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_AESIMC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_AND_AL_IMMb_DEFINED 1 +#define XED_IFORM_AND_GPR8_GPR8_20_DEFINED 1 +#define XED_IFORM_AND_GPR8_GPR8_22_DEFINED 1 +#define XED_IFORM_AND_GPR8_IMMb_80r4_DEFINED 1 +#define XED_IFORM_AND_GPR8_IMMb_82r4_DEFINED 1 +#define XED_IFORM_AND_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_AND_GPRv_GPRv_21_DEFINED 1 +#define XED_IFORM_AND_GPRv_GPRv_23_DEFINED 1 +#define XED_IFORM_AND_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_AND_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_AND_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_AND_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_AND_MEMb_IMMb_80r4_DEFINED 1 +#define XED_IFORM_AND_MEMb_IMMb_82r4_DEFINED 1 +#define XED_IFORM_AND_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_AND_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_AND_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_AND_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_ANDNPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_ANDNPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_ANDNPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_ANDNPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_ANDPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_ANDPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_ANDPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_ANDPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMb_IMMb_80r4_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMb_IMMb_82r4_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_AND_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_ARPL_GPR16_GPR16_DEFINED 1 +#define XED_IFORM_ARPL_MEMw_GPR16_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd_DEFINED 1 +#define XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCFILL_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCI_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCI_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCI_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCI_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCIC_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCIC_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCIC_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCIC_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCMSK_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLCS_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLCS_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLCS_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLCS_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_BLENDVPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_BLENDVPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_BLENDVPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_BLENDVPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLSFILL_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLSI_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSI_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSI_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_BLSI_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BLSIC_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSIC_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSIC_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_BLSIC_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_BLSMSK_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BLSR_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_BLSR_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BLSR_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_BLSR_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_BNDCL_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDCL_BND_GPR32_DEFINED 1 +#define XED_IFORM_BNDCL_BND_GPR64_DEFINED 1 +#define XED_IFORM_BNDCN_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDCN_BND_GPR32_DEFINED 1 +#define XED_IFORM_BNDCN_BND_GPR64_DEFINED 1 +#define XED_IFORM_BNDCU_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDCU_BND_GPR32_DEFINED 1 +#define XED_IFORM_BNDCU_BND_GPR64_DEFINED 1 +#define XED_IFORM_BNDLDX_BND_MEMbnd32_DEFINED 1 +#define XED_IFORM_BNDLDX_BND_MEMbnd64_DEFINED 1 +#define XED_IFORM_BNDMK_BND_AGEN_DEFINED 1 +#define XED_IFORM_BNDMOV_BND_BND_DEFINED 1 +#define XED_IFORM_BNDMOV_BND_MEMdq_DEFINED 1 +#define XED_IFORM_BNDMOV_BND_MEMq_DEFINED 1 +#define XED_IFORM_BNDMOV_MEMdq_BND_DEFINED 1 +#define XED_IFORM_BNDMOV_MEMq_BND_DEFINED 1 +#define XED_IFORM_BNDSTX_MEMbnd32_BND_DEFINED 1 +#define XED_IFORM_BNDSTX_MEMbnd64_BND_DEFINED 1 +#define XED_IFORM_BOUND_GPRv_MEMa16_DEFINED 1 +#define XED_IFORM_BOUND_GPRv_MEMa32_DEFINED 1 +#define XED_IFORM_BSF_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BSF_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_BSR_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BSR_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_BSWAP_GPRv_DEFINED 1 +#define XED_IFORM_BT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BT_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BT_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BT_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTC_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BTC_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BTC_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTC_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTC_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTC_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTR_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BTR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BTR_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTR_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTR_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTS_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_BTS_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_BTS_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTS_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BTS_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_BTS_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_CALL_FAR_MEMp2_DEFINED 1 +#define XED_IFORM_CALL_FAR_PTRp_IMMw_DEFINED 1 +#define XED_IFORM_CALL_NEAR_GPRv_DEFINED 1 +#define XED_IFORM_CALL_NEAR_MEMv_DEFINED 1 +#define XED_IFORM_CALL_NEAR_RELBRd_DEFINED 1 +#define XED_IFORM_CALL_NEAR_RELBRz_DEFINED 1 +#define XED_IFORM_CBW_DEFINED 1 +#define XED_IFORM_CDQ_DEFINED 1 +#define XED_IFORM_CDQE_DEFINED 1 +#define XED_IFORM_CLAC_DEFINED 1 +#define XED_IFORM_CLC_DEFINED 1 +#define XED_IFORM_CLD_DEFINED 1 +#define XED_IFORM_CLDEMOTE_MEMu8_DEFINED 1 +#define XED_IFORM_CLFLUSH_MEMmprefetch_DEFINED 1 +#define XED_IFORM_CLFLUSHOPT_MEMmprefetch_DEFINED 1 +#define XED_IFORM_CLGI_DEFINED 1 +#define XED_IFORM_CLI_DEFINED 1 +#define XED_IFORM_CLRSSBSY_MEMu64_DEFINED 1 +#define XED_IFORM_CLTS_DEFINED 1 +#define XED_IFORM_CLUI_DEFINED 1 +#define XED_IFORM_CLWB_MEMmprefetch_DEFINED 1 +#define XED_IFORM_CLZERO_DEFINED 1 +#define XED_IFORM_CMC_DEFINED 1 +#define XED_IFORM_CMOVB_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVBE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVBE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVL_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVL_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVLE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVLE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNB_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNBE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNBE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNL_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNL_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNLE_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNLE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNO_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNO_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNP_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNP_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNS_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNS_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVNZ_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVNZ_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVO_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVO_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVP_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVP_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVS_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVS_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMOVZ_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMOVZ_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMP_AL_IMMb_DEFINED 1 +#define XED_IFORM_CMP_GPR8_GPR8_38_DEFINED 1 +#define XED_IFORM_CMP_GPR8_GPR8_3A_DEFINED 1 +#define XED_IFORM_CMP_GPR8_IMMb_80r7_DEFINED 1 +#define XED_IFORM_CMP_GPR8_IMMb_82r7_DEFINED 1 +#define XED_IFORM_CMP_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_CMP_GPRv_GPRv_39_DEFINED 1 +#define XED_IFORM_CMP_GPRv_GPRv_3B_DEFINED 1 +#define XED_IFORM_CMP_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_CMP_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_CMP_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_CMP_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_CMP_MEMb_IMMb_80r7_DEFINED 1 +#define XED_IFORM_CMP_MEMb_IMMb_82r7_DEFINED 1 +#define XED_IFORM_CMP_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_CMP_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_CMP_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_CMP_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb_DEFINED 1 +#define XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb_DEFINED 1 +#define XED_IFORM_CMPPS_XMMps_MEMps_IMMb_DEFINED 1 +#define XED_IFORM_CMPPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_CMPSB_DEFINED 1 +#define XED_IFORM_CMPSD_DEFINED 1 +#define XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb_DEFINED 1 +#define XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb_DEFINED 1 +#define XED_IFORM_CMPSQ_DEFINED 1 +#define XED_IFORM_CMPSS_XMMss_MEMss_IMMb_DEFINED 1 +#define XED_IFORM_CMPSS_XMMss_XMMss_IMMb_DEFINED 1 +#define XED_IFORM_CMPSW_DEFINED 1 +#define XED_IFORM_CMPXCHG_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_CMPXCHG_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_CMPXCHG_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_CMPXCHG_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_CMPXCHG16B_MEMdq_DEFINED 1 +#define XED_IFORM_CMPXCHG16B_LOCK_MEMdq_DEFINED 1 +#define XED_IFORM_CMPXCHG8B_MEMq_DEFINED 1 +#define XED_IFORM_CMPXCHG8B_LOCK_MEMq_DEFINED 1 +#define XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_COMISD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_COMISD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_COMISS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_COMISS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_CPUID_DEFINED 1 +#define XED_IFORM_CQO_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_GPR8b_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_GPRv_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_MEMb_DEFINED 1 +#define XED_IFORM_CRC32_GPRyy_MEMv_DEFINED 1 +#define XED_IFORM_CVTDQ2PD_XMMpd_MEMq_DEFINED 1 +#define XED_IFORM_CVTDQ2PD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_CVTDQ2PS_XMMps_MEMdq_DEFINED 1 +#define XED_IFORM_CVTDQ2PS_XMMps_XMMdq_DEFINED 1 +#define XED_IFORM_CVTPD2DQ_XMMdq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTPD2DQ_XMMdq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PI_MMXq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PI_MMXq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PS_XMMps_MEMpd_DEFINED 1 +#define XED_IFORM_CVTPD2PS_XMMps_XMMpd_DEFINED 1 +#define XED_IFORM_CVTPI2PD_XMMpd_MEMq_DEFINED 1 +#define XED_IFORM_CVTPI2PD_XMMpd_MMXq_DEFINED 1 +#define XED_IFORM_CVTPI2PS_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_CVTPI2PS_XMMq_MMXq_DEFINED 1 +#define XED_IFORM_CVTPS2DQ_XMMdq_MEMps_DEFINED 1 +#define XED_IFORM_CVTPS2DQ_XMMdq_XMMps_DEFINED 1 +#define XED_IFORM_CVTPS2PD_XMMpd_MEMq_DEFINED 1 +#define XED_IFORM_CVTPS2PD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_CVTPS2PI_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_CVTPS2PI_MMXq_XMMq_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR32d_MEMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR32d_XMMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR64q_MEMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SI_GPR64q_XMMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SS_XMMss_MEMsd_DEFINED 1 +#define XED_IFORM_CVTSD2SS_XMMss_XMMsd_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_GPR32d_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_GPR64q_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_MEMd_DEFINED 1 +#define XED_IFORM_CVTSI2SD_XMMsd_MEMq_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_GPR32d_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_GPR64q_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_MEMd_DEFINED 1 +#define XED_IFORM_CVTSI2SS_XMMss_MEMq_DEFINED 1 +#define XED_IFORM_CVTSS2SD_XMMsd_MEMss_DEFINED 1 +#define XED_IFORM_CVTSS2SD_XMMsd_XMMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR32d_MEMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR32d_XMMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR64q_MEMss_DEFINED 1 +#define XED_IFORM_CVTSS2SI_GPR64q_XMMss_DEFINED 1 +#define XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTTPD2PI_MMXq_MEMpd_DEFINED 1 +#define XED_IFORM_CVTTPD2PI_MMXq_XMMpd_DEFINED 1 +#define XED_IFORM_CVTTPS2DQ_XMMdq_MEMps_DEFINED 1 +#define XED_IFORM_CVTTPS2DQ_XMMdq_XMMps_DEFINED 1 +#define XED_IFORM_CVTTPS2PI_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_CVTTPS2PI_MMXq_XMMq_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR32d_MEMsd_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR32d_XMMsd_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR64q_MEMsd_DEFINED 1 +#define XED_IFORM_CVTTSD2SI_GPR64q_XMMsd_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR32d_MEMss_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR32d_XMMss_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR64q_MEMss_DEFINED 1 +#define XED_IFORM_CVTTSS2SI_GPR64q_XMMss_DEFINED 1 +#define XED_IFORM_CWD_DEFINED 1 +#define XED_IFORM_CWDE_DEFINED 1 +#define XED_IFORM_DAA_DEFINED 1 +#define XED_IFORM_DAS_DEFINED 1 +#define XED_IFORM_DEC_GPR8_DEFINED 1 +#define XED_IFORM_DEC_GPRv_48_DEFINED 1 +#define XED_IFORM_DEC_GPRv_FFr1_DEFINED 1 +#define XED_IFORM_DEC_MEMb_DEFINED 1 +#define XED_IFORM_DEC_MEMv_DEFINED 1 +#define XED_IFORM_DEC_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_DEC_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_DIV_GPR8_DEFINED 1 +#define XED_IFORM_DIV_GPRv_DEFINED 1 +#define XED_IFORM_DIV_MEMb_DEFINED 1 +#define XED_IFORM_DIV_MEMv_DEFINED 1 +#define XED_IFORM_DIVPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_DIVPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_DIVPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_DIVPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_DIVSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_DIVSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_DIVSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_DIVSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_DPPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_DPPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_DPPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_DPPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_EMMS_DEFINED 1 +#define XED_IFORM_ENCLS_DEFINED 1 +#define XED_IFORM_ENCLU_DEFINED 1 +#define XED_IFORM_ENCLV_DEFINED 1 +#define XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8_DEFINED 1 +#define XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8_DEFINED 1 +#define XED_IFORM_ENDBR32_DEFINED 1 +#define XED_IFORM_ENDBR64_DEFINED 1 +#define XED_IFORM_ENQCMD_GPRa_MEMu32_DEFINED 1 +#define XED_IFORM_ENQCMDS_GPRa_MEMu32_DEFINED 1 +#define XED_IFORM_ENTER_IMMw_IMMb_DEFINED 1 +#define XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_EXTRQ_XMMq_IMMb_IMMb_DEFINED 1 +#define XED_IFORM_EXTRQ_XMMq_XMMdq_DEFINED 1 +#define XED_IFORM_F2XM1_DEFINED 1 +#define XED_IFORM_FABS_DEFINED 1 +#define XED_IFORM_FADD_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FADD_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FADD_ST0_X87_DEFINED 1 +#define XED_IFORM_FADD_X87_ST0_DEFINED 1 +#define XED_IFORM_FADDP_X87_ST0_DEFINED 1 +#define XED_IFORM_FBLD_ST0_MEMmem80dec_DEFINED 1 +#define XED_IFORM_FBSTP_MEMmem80dec_ST0_DEFINED 1 +#define XED_IFORM_FCHS_DEFINED 1 +#define XED_IFORM_FCMOVB_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVBE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNB_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNBE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNE_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVNU_ST0_X87_DEFINED 1 +#define XED_IFORM_FCMOVU_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOM_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FCOM_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FCOM_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOM_ST0_X87_DCD0_DEFINED 1 +#define XED_IFORM_FCOMI_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOMIP_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_X87_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_X87_DCD1_DEFINED 1 +#define XED_IFORM_FCOMP_ST0_X87_DED0_DEFINED 1 +#define XED_IFORM_FCOMPP_DEFINED 1 +#define XED_IFORM_FCOS_DEFINED 1 +#define XED_IFORM_FDECSTP_DEFINED 1 +#define XED_IFORM_FDISI8087_NOP_DEFINED 1 +#define XED_IFORM_FDIV_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FDIV_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FDIV_ST0_X87_DEFINED 1 +#define XED_IFORM_FDIV_X87_ST0_DEFINED 1 +#define XED_IFORM_FDIVP_X87_ST0_DEFINED 1 +#define XED_IFORM_FDIVR_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FDIVR_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FDIVR_ST0_X87_DEFINED 1 +#define XED_IFORM_FDIVR_X87_ST0_DEFINED 1 +#define XED_IFORM_FDIVRP_X87_ST0_DEFINED 1 +#define XED_IFORM_FEMMS_DEFINED 1 +#define XED_IFORM_FENI8087_NOP_DEFINED 1 +#define XED_IFORM_FFREE_X87_DEFINED 1 +#define XED_IFORM_FFREEP_X87_DEFINED 1 +#define XED_IFORM_FIADD_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIADD_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FICOM_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FICOM_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FICOMP_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FICOMP_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FIDIV_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIDIV_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FIDIVR_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIDIVR_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FILD_ST0_MEMm64int_DEFINED 1 +#define XED_IFORM_FILD_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FILD_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FIMUL_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FIMUL_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FINCSTP_DEFINED 1 +#define XED_IFORM_FIST_MEMmem16int_ST0_DEFINED 1 +#define XED_IFORM_FIST_MEMmem32int_ST0_DEFINED 1 +#define XED_IFORM_FISTP_MEMm64int_ST0_DEFINED 1 +#define XED_IFORM_FISTP_MEMmem16int_ST0_DEFINED 1 +#define XED_IFORM_FISTP_MEMmem32int_ST0_DEFINED 1 +#define XED_IFORM_FISTTP_MEMm64int_ST0_DEFINED 1 +#define XED_IFORM_FISTTP_MEMmem16int_ST0_DEFINED 1 +#define XED_IFORM_FISTTP_MEMmem32int_ST0_DEFINED 1 +#define XED_IFORM_FISUB_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FISUB_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FISUBR_ST0_MEMmem16int_DEFINED 1 +#define XED_IFORM_FISUBR_ST0_MEMmem32int_DEFINED 1 +#define XED_IFORM_FLD_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FLD_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FLD_ST0_MEMmem80real_DEFINED 1 +#define XED_IFORM_FLD_ST0_X87_DEFINED 1 +#define XED_IFORM_FLD1_DEFINED 1 +#define XED_IFORM_FLDCW_MEMmem16_DEFINED 1 +#define XED_IFORM_FLDENV_MEMmem14_DEFINED 1 +#define XED_IFORM_FLDENV_MEMmem28_DEFINED 1 +#define XED_IFORM_FLDL2E_DEFINED 1 +#define XED_IFORM_FLDL2T_DEFINED 1 +#define XED_IFORM_FLDLG2_DEFINED 1 +#define XED_IFORM_FLDLN2_DEFINED 1 +#define XED_IFORM_FLDPI_DEFINED 1 +#define XED_IFORM_FLDZ_DEFINED 1 +#define XED_IFORM_FMUL_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FMUL_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FMUL_ST0_X87_DEFINED 1 +#define XED_IFORM_FMUL_X87_ST0_DEFINED 1 +#define XED_IFORM_FMULP_X87_ST0_DEFINED 1 +#define XED_IFORM_FNCLEX_DEFINED 1 +#define XED_IFORM_FNINIT_DEFINED 1 +#define XED_IFORM_FNOP_DEFINED 1 +#define XED_IFORM_FNSAVE_MEMmem108_DEFINED 1 +#define XED_IFORM_FNSAVE_MEMmem94_DEFINED 1 +#define XED_IFORM_FNSTCW_MEMmem16_DEFINED 1 +#define XED_IFORM_FNSTENV_MEMmem14_DEFINED 1 +#define XED_IFORM_FNSTENV_MEMmem28_DEFINED 1 +#define XED_IFORM_FNSTSW_AX_DEFINED 1 +#define XED_IFORM_FNSTSW_MEMmem16_DEFINED 1 +#define XED_IFORM_FPATAN_DEFINED 1 +#define XED_IFORM_FPREM_DEFINED 1 +#define XED_IFORM_FPREM1_DEFINED 1 +#define XED_IFORM_FPTAN_DEFINED 1 +#define XED_IFORM_FRNDINT_DEFINED 1 +#define XED_IFORM_FRSTOR_MEMmem108_DEFINED 1 +#define XED_IFORM_FRSTOR_MEMmem94_DEFINED 1 +#define XED_IFORM_FSCALE_DEFINED 1 +#define XED_IFORM_FSETPM287_NOP_DEFINED 1 +#define XED_IFORM_FSIN_DEFINED 1 +#define XED_IFORM_FSINCOS_DEFINED 1 +#define XED_IFORM_FSQRT_DEFINED 1 +#define XED_IFORM_FST_MEMm64real_ST0_DEFINED 1 +#define XED_IFORM_FST_MEMmem32real_ST0_DEFINED 1 +#define XED_IFORM_FST_X87_ST0_DEFINED 1 +#define XED_IFORM_FSTP_MEMm64real_ST0_DEFINED 1 +#define XED_IFORM_FSTP_MEMmem32real_ST0_DEFINED 1 +#define XED_IFORM_FSTP_MEMmem80real_ST0_DEFINED 1 +#define XED_IFORM_FSTP_X87_ST0_DEFINED 1 +#define XED_IFORM_FSTP_X87_ST0_DFD0_DEFINED 1 +#define XED_IFORM_FSTP_X87_ST0_DFD1_DEFINED 1 +#define XED_IFORM_FSTPNCE_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUB_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FSUB_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FSUB_ST0_X87_DEFINED 1 +#define XED_IFORM_FSUB_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUBP_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUBR_ST0_MEMm64real_DEFINED 1 +#define XED_IFORM_FSUBR_ST0_MEMmem32real_DEFINED 1 +#define XED_IFORM_FSUBR_ST0_X87_DEFINED 1 +#define XED_IFORM_FSUBR_X87_ST0_DEFINED 1 +#define XED_IFORM_FSUBRP_X87_ST0_DEFINED 1 +#define XED_IFORM_FTST_DEFINED 1 +#define XED_IFORM_FUCOM_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMI_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMIP_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMP_ST0_X87_DEFINED 1 +#define XED_IFORM_FUCOMPP_DEFINED 1 +#define XED_IFORM_FWAIT_DEFINED 1 +#define XED_IFORM_FXAM_DEFINED 1 +#define XED_IFORM_FXCH_ST0_X87_DEFINED 1 +#define XED_IFORM_FXCH_ST0_X87_DDC1_DEFINED 1 +#define XED_IFORM_FXCH_ST0_X87_DFC1_DEFINED 1 +#define XED_IFORM_FXRSTOR_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXRSTOR64_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXSAVE_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXSAVE64_MEMmfpxenv_DEFINED 1 +#define XED_IFORM_FXTRACT_DEFINED 1 +#define XED_IFORM_FYL2X_DEFINED 1 +#define XED_IFORM_FYL2XP1_DEFINED 1 +#define XED_IFORM_GETSEC_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_GF2P8MULB_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_GF2P8MULB_XMMu8_XMMu8_DEFINED 1 +#define XED_IFORM_HADDPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_HADDPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_HADDPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_HADDPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_HLT_DEFINED 1 +#define XED_IFORM_HRESET_IMM8_DEFINED 1 +#define XED_IFORM_HSUBPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_HSUBPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_HSUBPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_HSUBPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_IDIV_GPR8_DEFINED 1 +#define XED_IFORM_IDIV_GPRv_DEFINED 1 +#define XED_IFORM_IDIV_MEMb_DEFINED 1 +#define XED_IFORM_IDIV_MEMv_DEFINED 1 +#define XED_IFORM_IMUL_GPR8_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_IMUL_GPRv_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_IMUL_MEMb_DEFINED 1 +#define XED_IFORM_IMUL_MEMv_DEFINED 1 +#define XED_IFORM_IN_AL_DX_DEFINED 1 +#define XED_IFORM_IN_AL_IMMb_DEFINED 1 +#define XED_IFORM_IN_OeAX_DX_DEFINED 1 +#define XED_IFORM_IN_OeAX_IMMb_DEFINED 1 +#define XED_IFORM_INC_GPR8_DEFINED 1 +#define XED_IFORM_INC_GPRv_40_DEFINED 1 +#define XED_IFORM_INC_GPRv_FFr0_DEFINED 1 +#define XED_IFORM_INC_MEMb_DEFINED 1 +#define XED_IFORM_INC_MEMv_DEFINED 1 +#define XED_IFORM_INCSSPD_GPR32u8_DEFINED 1 +#define XED_IFORM_INCSSPQ_GPR64u8_DEFINED 1 +#define XED_IFORM_INC_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_INC_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_INSB_DEFINED 1 +#define XED_IFORM_INSD_DEFINED 1 +#define XED_IFORM_INSERTPS_XMMps_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_INSERTPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_INSERTQ_XMMq_XMMdq_DEFINED 1 +#define XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb_DEFINED 1 +#define XED_IFORM_INSW_DEFINED 1 +#define XED_IFORM_INT_IMMb_DEFINED 1 +#define XED_IFORM_INT1_DEFINED 1 +#define XED_IFORM_INT3_DEFINED 1 +#define XED_IFORM_INTO_DEFINED 1 +#define XED_IFORM_INVD_DEFINED 1 +#define XED_IFORM_INVEPT_GPR32_MEMdq_DEFINED 1 +#define XED_IFORM_INVEPT_GPR64_MEMdq_DEFINED 1 +#define XED_IFORM_INVLPG_MEMb_DEFINED 1 +#define XED_IFORM_INVLPGA_ArAX_ECX_DEFINED 1 +#define XED_IFORM_INVLPGB_EAX_EDX_ECX_DEFINED 1 +#define XED_IFORM_INVLPGB_RAX_EDX_ECX_DEFINED 1 +#define XED_IFORM_INVPCID_GPR32_MEMdq_DEFINED 1 +#define XED_IFORM_INVPCID_GPR64_MEMdq_DEFINED 1 +#define XED_IFORM_INVVPID_GPR32_MEMdq_DEFINED 1 +#define XED_IFORM_INVVPID_GPR64_MEMdq_DEFINED 1 +#define XED_IFORM_IRET_DEFINED 1 +#define XED_IFORM_IRETD_DEFINED 1 +#define XED_IFORM_IRETQ_DEFINED 1 +#define XED_IFORM_JB_RELBRb_DEFINED 1 +#define XED_IFORM_JB_RELBRd_DEFINED 1 +#define XED_IFORM_JB_RELBRz_DEFINED 1 +#define XED_IFORM_JBE_RELBRb_DEFINED 1 +#define XED_IFORM_JBE_RELBRd_DEFINED 1 +#define XED_IFORM_JBE_RELBRz_DEFINED 1 +#define XED_IFORM_JCXZ_RELBRb_DEFINED 1 +#define XED_IFORM_JECXZ_RELBRb_DEFINED 1 +#define XED_IFORM_JL_RELBRb_DEFINED 1 +#define XED_IFORM_JL_RELBRd_DEFINED 1 +#define XED_IFORM_JL_RELBRz_DEFINED 1 +#define XED_IFORM_JLE_RELBRb_DEFINED 1 +#define XED_IFORM_JLE_RELBRd_DEFINED 1 +#define XED_IFORM_JLE_RELBRz_DEFINED 1 +#define XED_IFORM_JMP_GPRv_DEFINED 1 +#define XED_IFORM_JMP_MEMv_DEFINED 1 +#define XED_IFORM_JMP_RELBRb_DEFINED 1 +#define XED_IFORM_JMP_RELBRd_DEFINED 1 +#define XED_IFORM_JMP_RELBRz_DEFINED 1 +#define XED_IFORM_JMP_FAR_MEMp2_DEFINED 1 +#define XED_IFORM_JMP_FAR_PTRp_IMMw_DEFINED 1 +#define XED_IFORM_JNB_RELBRb_DEFINED 1 +#define XED_IFORM_JNB_RELBRd_DEFINED 1 +#define XED_IFORM_JNB_RELBRz_DEFINED 1 +#define XED_IFORM_JNBE_RELBRb_DEFINED 1 +#define XED_IFORM_JNBE_RELBRd_DEFINED 1 +#define XED_IFORM_JNBE_RELBRz_DEFINED 1 +#define XED_IFORM_JNL_RELBRb_DEFINED 1 +#define XED_IFORM_JNL_RELBRd_DEFINED 1 +#define XED_IFORM_JNL_RELBRz_DEFINED 1 +#define XED_IFORM_JNLE_RELBRb_DEFINED 1 +#define XED_IFORM_JNLE_RELBRd_DEFINED 1 +#define XED_IFORM_JNLE_RELBRz_DEFINED 1 +#define XED_IFORM_JNO_RELBRb_DEFINED 1 +#define XED_IFORM_JNO_RELBRd_DEFINED 1 +#define XED_IFORM_JNO_RELBRz_DEFINED 1 +#define XED_IFORM_JNP_RELBRb_DEFINED 1 +#define XED_IFORM_JNP_RELBRd_DEFINED 1 +#define XED_IFORM_JNP_RELBRz_DEFINED 1 +#define XED_IFORM_JNS_RELBRb_DEFINED 1 +#define XED_IFORM_JNS_RELBRd_DEFINED 1 +#define XED_IFORM_JNS_RELBRz_DEFINED 1 +#define XED_IFORM_JNZ_RELBRb_DEFINED 1 +#define XED_IFORM_JNZ_RELBRd_DEFINED 1 +#define XED_IFORM_JNZ_RELBRz_DEFINED 1 +#define XED_IFORM_JO_RELBRb_DEFINED 1 +#define XED_IFORM_JO_RELBRd_DEFINED 1 +#define XED_IFORM_JO_RELBRz_DEFINED 1 +#define XED_IFORM_JP_RELBRb_DEFINED 1 +#define XED_IFORM_JP_RELBRd_DEFINED 1 +#define XED_IFORM_JP_RELBRz_DEFINED 1 +#define XED_IFORM_JRCXZ_RELBRb_DEFINED 1 +#define XED_IFORM_JS_RELBRb_DEFINED 1 +#define XED_IFORM_JS_RELBRd_DEFINED 1 +#define XED_IFORM_JS_RELBRz_DEFINED 1 +#define XED_IFORM_JZ_RELBRb_DEFINED 1 +#define XED_IFORM_JZ_RELBRd_DEFINED 1 +#define XED_IFORM_JZ_RELBRz_DEFINED 1 +#define XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_LAHF_DEFINED 1 +#define XED_IFORM_LAR_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_LAR_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_LDDQU_XMMpd_MEMdq_DEFINED 1 +#define XED_IFORM_LDMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_LDS_GPRz_MEMp_DEFINED 1 +#define XED_IFORM_LDTILECFG_MEM_DEFINED 1 +#define XED_IFORM_LEA_GPRv_AGEN_DEFINED 1 +#define XED_IFORM_LEAVE_DEFINED 1 +#define XED_IFORM_LES_GPRz_MEMp_DEFINED 1 +#define XED_IFORM_LFENCE_DEFINED 1 +#define XED_IFORM_LFS_GPRv_MEMp2_DEFINED 1 +#define XED_IFORM_LGDT_MEMs_DEFINED 1 +#define XED_IFORM_LGDT_MEMs64_DEFINED 1 +#define XED_IFORM_LGS_GPRv_MEMp2_DEFINED 1 +#define XED_IFORM_LIDT_MEMs_DEFINED 1 +#define XED_IFORM_LIDT_MEMs64_DEFINED 1 +#define XED_IFORM_LLDT_GPR16_DEFINED 1 +#define XED_IFORM_LLDT_MEMw_DEFINED 1 +#define XED_IFORM_LLWPCB_VGPRyy_DEFINED 1 +#define XED_IFORM_LMSW_GPR16_DEFINED 1 +#define XED_IFORM_LMSW_MEMw_DEFINED 1 +#define XED_IFORM_LOADIWKEY_XMMu8_XMMu8_DEFINED 1 +#define XED_IFORM_LODSB_DEFINED 1 +#define XED_IFORM_LODSD_DEFINED 1 +#define XED_IFORM_LODSQ_DEFINED 1 +#define XED_IFORM_LODSW_DEFINED 1 +#define XED_IFORM_LOOP_RELBRb_DEFINED 1 +#define XED_IFORM_LOOPE_RELBRb_DEFINED 1 +#define XED_IFORM_LOOPNE_RELBRb_DEFINED 1 +#define XED_IFORM_LSL_GPRv_GPRz_DEFINED 1 +#define XED_IFORM_LSL_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_LSS_GPRv_MEMp2_DEFINED 1 +#define XED_IFORM_LTR_GPR16_DEFINED 1 +#define XED_IFORM_LTR_MEMw_DEFINED 1 +#define XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd_DEFINED 1 +#define XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd_DEFINED 1 +#define XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd_DEFINED 1 +#define XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd_DEFINED 1 +#define XED_IFORM_LZCNT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_LZCNT_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_MASKMOVDQU_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MASKMOVQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_MAXPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MAXPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MAXPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MAXPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MAXSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_MAXSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MAXSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_MAXSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_MCOMMIT_DEFINED 1 +#define XED_IFORM_MFENCE_DEFINED 1 +#define XED_IFORM_MINPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MINPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MINPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MINPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MINSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_MINSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MINSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_MINSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_MONITOR_DEFINED 1 +#define XED_IFORM_MONITORX_DEFINED 1 +#define XED_IFORM_MOV_AL_MEMb_DEFINED 1 +#define XED_IFORM_MOV_GPR8_GPR8_88_DEFINED 1 +#define XED_IFORM_MOV_GPR8_GPR8_8A_DEFINED 1 +#define XED_IFORM_MOV_GPR8_IMMb_B0_DEFINED 1 +#define XED_IFORM_MOV_GPR8_IMMb_C6r0_DEFINED 1 +#define XED_IFORM_MOV_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_MOV_GPRv_GPRv_89_DEFINED 1 +#define XED_IFORM_MOV_GPRv_GPRv_8B_DEFINED 1 +#define XED_IFORM_MOV_GPRv_IMMv_DEFINED 1 +#define XED_IFORM_MOV_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_MOV_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_MOV_GPRv_SEG_DEFINED 1 +#define XED_IFORM_MOV_MEMb_AL_DEFINED 1 +#define XED_IFORM_MOV_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_MOV_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_MOV_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_MOV_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_MOV_MEMv_OrAX_DEFINED 1 +#define XED_IFORM_MOV_MEMw_SEG_DEFINED 1 +#define XED_IFORM_MOV_OrAX_MEMv_DEFINED 1 +#define XED_IFORM_MOV_SEG_GPR16_DEFINED 1 +#define XED_IFORM_MOV_SEG_MEMw_DEFINED 1 +#define XED_IFORM_MOVAPD_MEMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MOVAPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28_DEFINED 1 +#define XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29_DEFINED 1 +#define XED_IFORM_MOVAPS_MEMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVAPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVAPS_XMMps_XMMps_0F28_DEFINED 1 +#define XED_IFORM_MOVAPS_XMMps_XMMps_0F29_DEFINED 1 +#define XED_IFORM_MOVBE_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_MOVBE_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_MOVD_GPR32_MMXd_DEFINED 1 +#define XED_IFORM_MOVD_GPR32_XMMd_DEFINED 1 +#define XED_IFORM_MOVD_MEMd_MMXd_DEFINED 1 +#define XED_IFORM_MOVD_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_MOVD_MMXq_GPR32_DEFINED 1 +#define XED_IFORM_MOVD_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_MOVD_XMMdq_GPR32_DEFINED 1 +#define XED_IFORM_MOVD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_MOVDDUP_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_MOVDDUP_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_MOVDIR64B_GPRa_MEM_DEFINED 1 +#define XED_IFORM_MOVDIRI_MEMu32_GPR32u32_DEFINED 1 +#define XED_IFORM_MOVDIRI_MEMu64_GPR64u64_DEFINED 1 +#define XED_IFORM_MOVDQ2Q_MMXq_XMMq_DEFINED 1 +#define XED_IFORM_MOVDQA_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MOVDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F_DEFINED 1 +#define XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F_DEFINED 1 +#define XED_IFORM_MOVDQU_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MOVDQU_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F_DEFINED 1 +#define XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F_DEFINED 1 +#define XED_IFORM_MOVHLPS_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVHPD_MEMq_XMMsd_DEFINED 1 +#define XED_IFORM_MOVHPD_XMMsd_MEMq_DEFINED 1 +#define XED_IFORM_MOVHPS_MEMq_XMMps_DEFINED 1 +#define XED_IFORM_MOVHPS_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_MOVLHPS_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVLPD_MEMq_XMMsd_DEFINED 1 +#define XED_IFORM_MOVLPD_XMMsd_MEMq_DEFINED 1 +#define XED_IFORM_MOVLPS_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVLPS_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_MOVMSKPD_GPR32_XMMpd_DEFINED 1 +#define XED_IFORM_MOVMSKPS_GPR32_XMMps_DEFINED 1 +#define XED_IFORM_MOVNTDQ_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_MOVNTDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_MOVNTI_MEMd_GPR32_DEFINED 1 +#define XED_IFORM_MOVNTI_MEMq_GPR64_DEFINED 1 +#define XED_IFORM_MOVNTPD_MEMdq_XMMpd_DEFINED 1 +#define XED_IFORM_MOVNTPS_MEMdq_XMMps_DEFINED 1 +#define XED_IFORM_MOVNTQ_MEMq_MMXq_DEFINED 1 +#define XED_IFORM_MOVNTSD_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_MOVNTSS_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_MOVQ_GPR64_MMXq_DEFINED 1 +#define XED_IFORM_MOVQ_GPR64_XMMq_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_MMXq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_MMXq_0F7F_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_XMMq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_MEMq_XMMq_0FD6_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_GPR64_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MEMq_0F6E_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MEMq_0F6F_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MMXq_0F6F_DEFINED 1 +#define XED_IFORM_MOVQ_MMXq_MMXq_0F7F_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_GPR64_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_MEMq_0F6E_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_MEMq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_XMMq_0F7E_DEFINED 1 +#define XED_IFORM_MOVQ_XMMdq_XMMq_0FD6_DEFINED 1 +#define XED_IFORM_MOVQ2DQ_XMMdq_MMXq_DEFINED 1 +#define XED_IFORM_MOVSB_DEFINED 1 +#define XED_IFORM_MOVSD_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_MEMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_XMMdq_MEMsd_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10_DEFINED 1 +#define XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11_DEFINED 1 +#define XED_IFORM_MOVSHDUP_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVSHDUP_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVSLDUP_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVSLDUP_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVSQ_DEFINED 1 +#define XED_IFORM_MOVSS_MEMss_XMMss_DEFINED 1 +#define XED_IFORM_MOVSS_XMMdq_MEMss_DEFINED 1 +#define XED_IFORM_MOVSS_XMMss_XMMss_0F10_DEFINED 1 +#define XED_IFORM_MOVSS_XMMss_XMMss_0F11_DEFINED 1 +#define XED_IFORM_MOVSW_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_GPR16_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_GPR8_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_MEMb_DEFINED 1 +#define XED_IFORM_MOVSX_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_MOVSXD_GPRv_GPRz_DEFINED 1 +#define XED_IFORM_MOVSXD_GPRv_MEMz_DEFINED 1 +#define XED_IFORM_MOVUPD_MEMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MOVUPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10_DEFINED 1 +#define XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11_DEFINED 1 +#define XED_IFORM_MOVUPS_MEMps_XMMps_DEFINED 1 +#define XED_IFORM_MOVUPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MOVUPS_XMMps_XMMps_0F10_DEFINED 1 +#define XED_IFORM_MOVUPS_XMMps_XMMps_0F11_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_GPR16_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_GPR8_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_MEMb_DEFINED 1 +#define XED_IFORM_MOVZX_GPRv_MEMw_DEFINED 1 +#define XED_IFORM_MOV_CR_CR_GPR32_DEFINED 1 +#define XED_IFORM_MOV_CR_CR_GPR64_DEFINED 1 +#define XED_IFORM_MOV_CR_GPR32_CR_DEFINED 1 +#define XED_IFORM_MOV_CR_GPR64_CR_DEFINED 1 +#define XED_IFORM_MOV_DR_DR_GPR32_DEFINED 1 +#define XED_IFORM_MOV_DR_DR_GPR64_DEFINED 1 +#define XED_IFORM_MOV_DR_GPR32_DR_DEFINED 1 +#define XED_IFORM_MOV_DR_GPR64_DR_DEFINED 1 +#define XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_MUL_GPR8_DEFINED 1 +#define XED_IFORM_MUL_GPRv_DEFINED 1 +#define XED_IFORM_MUL_MEMb_DEFINED 1 +#define XED_IFORM_MUL_MEMv_DEFINED 1 +#define XED_IFORM_MULPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_MULPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_MULPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_MULPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_MULSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_MULSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_MULSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_MULSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_MWAIT_DEFINED 1 +#define XED_IFORM_MWAITX_DEFINED 1 +#define XED_IFORM_NEG_GPR8_DEFINED 1 +#define XED_IFORM_NEG_GPRv_DEFINED 1 +#define XED_IFORM_NEG_MEMb_DEFINED 1 +#define XED_IFORM_NEG_MEMv_DEFINED 1 +#define XED_IFORM_NEG_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_NEG_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_NOP_90_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r0_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r1_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r2_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r3_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r4_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r5_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r6_DEFINED 1 +#define XED_IFORM_NOP_GPRv_0F18r7_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F0D_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F19_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1A_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1B_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1C_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1D_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1E_DEFINED 1 +#define XED_IFORM_NOP_GPRv_GPRv_0F1F_DEFINED 1 +#define XED_IFORM_NOP_GPRv_MEM_0F1B_DEFINED 1 +#define XED_IFORM_NOP_GPRv_MEMv_0F1A_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r4_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r5_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r6_DEFINED 1 +#define XED_IFORM_NOP_MEMv_0F18r7_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F19_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1C_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1D_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1E_DEFINED 1 +#define XED_IFORM_NOP_MEMv_GPRv_0F1F_DEFINED 1 +#define XED_IFORM_NOT_GPR8_DEFINED 1 +#define XED_IFORM_NOT_GPRv_DEFINED 1 +#define XED_IFORM_NOT_MEMb_DEFINED 1 +#define XED_IFORM_NOT_MEMv_DEFINED 1 +#define XED_IFORM_NOT_LOCK_MEMb_DEFINED 1 +#define XED_IFORM_NOT_LOCK_MEMv_DEFINED 1 +#define XED_IFORM_OR_AL_IMMb_DEFINED 1 +#define XED_IFORM_OR_GPR8_GPR8_08_DEFINED 1 +#define XED_IFORM_OR_GPR8_GPR8_0A_DEFINED 1 +#define XED_IFORM_OR_GPR8_IMMb_80r1_DEFINED 1 +#define XED_IFORM_OR_GPR8_IMMb_82r1_DEFINED 1 +#define XED_IFORM_OR_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_OR_GPRv_GPRv_09_DEFINED 1 +#define XED_IFORM_OR_GPRv_GPRv_0B_DEFINED 1 +#define XED_IFORM_OR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_OR_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_OR_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_OR_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_OR_MEMb_IMMb_80r1_DEFINED 1 +#define XED_IFORM_OR_MEMb_IMMb_82r1_DEFINED 1 +#define XED_IFORM_OR_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_OR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_OR_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_OR_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_ORPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_ORPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_ORPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_ORPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMb_IMMb_80r1_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMb_IMMb_82r1_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_OR_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_OUT_DX_AL_DEFINED 1 +#define XED_IFORM_OUT_DX_OeAX_DEFINED 1 +#define XED_IFORM_OUT_IMMb_AL_DEFINED 1 +#define XED_IFORM_OUT_IMMb_OeAX_DEFINED 1 +#define XED_IFORM_OUTSB_DEFINED 1 +#define XED_IFORM_OUTSD_DEFINED 1 +#define XED_IFORM_OUTSW_DEFINED 1 +#define XED_IFORM_PABSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PABSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PABSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PABSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PABSD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PABSD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PABSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PABSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PABSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PABSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PABSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PABSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKSSDW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PACKSSDW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PACKSSDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKSSDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKSSWB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PACKSSWB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PACKSSWB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKSSWB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKUSDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKUSDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PACKUSWB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PACKUSWB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PACKUSWB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PACKUSWB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDUSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDUSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDUSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDUSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDUSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDUSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDUSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDUSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PADDW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PADDW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PADDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PADDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PALIGNR_MMXq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_PALIGNR_MMXq_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PAND_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAND_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAND_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PAND_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PANDN_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PANDN_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PANDN_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PANDN_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PAUSE_DEFINED 1 +#define XED_IFORM_PAVGB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAVGB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAVGB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PAVGB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PAVGUSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAVGUSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAVGW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PAVGW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PAVGW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PAVGW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PBLENDVB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PBLENDVB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPEQB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPEQB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPEQB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPEQD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPEQD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPEQD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPEQQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPEQW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPEQW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPEQW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPEQW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPGTB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPGTB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPGTB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPGTD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPGTD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPGTD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPGTQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPGTW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PCMPGTW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PCMPGTW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PCMPGTW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PCONFIG_DEFINED 1 +#define XED_IFORM_PCONFIG64_DEFINED 1 +#define XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq_DEFINED 1 +#define XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_GPR32_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PF2ID_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PF2ID_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PF2IW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PF2IW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFACC_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFACC_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFADD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFADD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFCMPEQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFCMPEQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFCMPGE_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFCMPGE_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFCMPGT_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFCMPGT_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFMAX_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFMAX_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFMIN_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFMIN_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFMUL_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFMUL_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFNACC_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFNACC_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFPNACC_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFPNACC_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRCP_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRCP_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRCPIT1_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRCPIT1_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRCPIT2_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRCPIT2_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRSQIT1_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRSQIT1_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFRSQRT_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFRSQRT_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFSUB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFSUB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PFSUBR_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PFSUBR_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHADDD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHADDD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHADDSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHADDSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHADDSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHADDW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHADDW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHADDW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHADDW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHMINPOSUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHMINPOSUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHSUBD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHSUBD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHSUBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHSUBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHSUBSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHSUBSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHSUBSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHSUBSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PHSUBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PHSUBW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PHSUBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PHSUBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PI2FD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PI2FD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PI2FW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PI2FW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_PINSRB_XMMdq_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_PINSRD_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb_DEFINED 1 +#define XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_MMXq_GPR32_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_MMXq_MEMw_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_XMMdq_GPR32_IMMb_DEFINED 1 +#define XED_IFORM_PINSRW_XMMdq_MEMw_IMMb_DEFINED 1 +#define XED_IFORM_PMADDUBSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMADDUBSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMADDUBSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMADDUBSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMADDWD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMADDWD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMADDWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMADDWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMAXSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMAXSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXUB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMAXUB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMAXUB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXUB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXUD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXUD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMAXUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMAXUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMINSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMINSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINUB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMINUB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMINUB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINUB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINUD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINUD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMINUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMINUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMOVMSKB_GPR32_MMXq_DEFINED 1 +#define XED_IFORM_PMOVMSKB_GPR32_XMMdq_DEFINED 1 +#define XED_IFORM_PMOVSXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVSXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMOVSXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_PMOVSXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_PMOVSXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVSXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVSXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVSXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVSXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVSXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVSXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVSXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMOVZXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVZXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMOVZXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_PMOVZXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_PMOVZXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVZXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVZXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVZXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVZXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_PMOVZXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PMOVZXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_PMOVZXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_PMULDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULHRSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHRSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHRSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULHRSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULHRW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHRW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHUW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHUW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULHUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULHW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULHW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULHW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULHW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULLD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULLD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULLW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULLW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULLW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULLW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PMULUDQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PMULUDQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PMULUDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PMULUDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_POP_DS_DEFINED 1 +#define XED_IFORM_POP_ES_DEFINED 1 +#define XED_IFORM_POP_FS_DEFINED 1 +#define XED_IFORM_POP_GPRv_58_DEFINED 1 +#define XED_IFORM_POP_GPRv_8F_DEFINED 1 +#define XED_IFORM_POP_GS_DEFINED 1 +#define XED_IFORM_POP_MEMv_DEFINED 1 +#define XED_IFORM_POP_SS_DEFINED 1 +#define XED_IFORM_POPA_DEFINED 1 +#define XED_IFORM_POPAD_DEFINED 1 +#define XED_IFORM_POPCNT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_POPCNT_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_POPF_DEFINED 1 +#define XED_IFORM_POPFD_DEFINED 1 +#define XED_IFORM_POPFQ_DEFINED 1 +#define XED_IFORM_POR_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_POR_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_POR_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_POR_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PREFETCHNTA_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHT0_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHT1_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHT2_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCHW_0F0Dr1_DEFINED 1 +#define XED_IFORM_PREFETCHW_0F0Dr3_DEFINED 1 +#define XED_IFORM_PREFETCHWT1_MEMu8_DEFINED 1 +#define XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr4_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr5_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr6_DEFINED 1 +#define XED_IFORM_PREFETCH_RESERVED_0F0Dr7_DEFINED 1 +#define XED_IFORM_PSADBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSADBW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSADBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSADBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSHUFB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSHUFB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSHUFB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSHUFB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFW_MMXq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_PSHUFW_MMXq_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSIGNB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSIGNB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSIGNB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSIGNB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSIGND_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSIGND_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSIGND_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSIGND_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSIGNW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSIGNW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSIGNW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSIGNW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSLLD_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSLLD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSLLD_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSLLD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSLLDQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLQ_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSLLQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSLLQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSLLQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSLLW_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSLLW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSLLW_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSLLW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSLLW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSMASH_RAX_DEFINED 1 +#define XED_IFORM_PSRAD_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRAD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRAD_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRAD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRAW_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRAW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRAW_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRAW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRAW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRLD_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRLD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRLD_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRLD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRLDQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLQ_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRLQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRLQ_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRLQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSRLW_MMXq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSRLW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSRLW_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_PSRLW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSRLW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBQ_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBUSB_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBUSB_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBUSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBUSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBUSW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBUSW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBUSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBUSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSUBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSUBW_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PSUBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PSUBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PSWAPD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PSWAPD_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PTEST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PTEST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_PTWRITE_GPRy_DEFINED 1 +#define XED_IFORM_PTWRITE_MEMy_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKHWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_MMXq_MEMd_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_MMXq_MMXd_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PUNPCKLWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_PUSH_CS_DEFINED 1 +#define XED_IFORM_PUSH_DS_DEFINED 1 +#define XED_IFORM_PUSH_ES_DEFINED 1 +#define XED_IFORM_PUSH_FS_DEFINED 1 +#define XED_IFORM_PUSH_GPRv_50_DEFINED 1 +#define XED_IFORM_PUSH_GPRv_FFr6_DEFINED 1 +#define XED_IFORM_PUSH_GS_DEFINED 1 +#define XED_IFORM_PUSH_IMMb_DEFINED 1 +#define XED_IFORM_PUSH_IMMz_DEFINED 1 +#define XED_IFORM_PUSH_MEMv_DEFINED 1 +#define XED_IFORM_PUSH_SS_DEFINED 1 +#define XED_IFORM_PUSHA_DEFINED 1 +#define XED_IFORM_PUSHAD_DEFINED 1 +#define XED_IFORM_PUSHF_DEFINED 1 +#define XED_IFORM_PUSHFD_DEFINED 1 +#define XED_IFORM_PUSHFQ_DEFINED 1 +#define XED_IFORM_PVALIDATE_RAX_ECX_EDX_DEFINED 1 +#define XED_IFORM_PXOR_MMXq_MEMq_DEFINED 1 +#define XED_IFORM_PXOR_MMXq_MMXq_DEFINED 1 +#define XED_IFORM_PXOR_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_PXOR_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_RCL_GPR8_CL_DEFINED 1 +#define XED_IFORM_RCL_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_RCL_GPR8_ONE_DEFINED 1 +#define XED_IFORM_RCL_GPRv_CL_DEFINED 1 +#define XED_IFORM_RCL_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_RCL_GPRv_ONE_DEFINED 1 +#define XED_IFORM_RCL_MEMb_CL_DEFINED 1 +#define XED_IFORM_RCL_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_RCL_MEMb_ONE_DEFINED 1 +#define XED_IFORM_RCL_MEMv_CL_DEFINED 1 +#define XED_IFORM_RCL_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_RCL_MEMv_ONE_DEFINED 1 +#define XED_IFORM_RCPPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_RCPPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_RCPSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_RCPSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_RCR_GPR8_CL_DEFINED 1 +#define XED_IFORM_RCR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_RCR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_RCR_GPRv_CL_DEFINED 1 +#define XED_IFORM_RCR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_RCR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_RCR_MEMb_CL_DEFINED 1 +#define XED_IFORM_RCR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_RCR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_RCR_MEMv_CL_DEFINED 1 +#define XED_IFORM_RCR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_RCR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_RDFSBASE_GPRy_DEFINED 1 +#define XED_IFORM_RDGSBASE_GPRy_DEFINED 1 +#define XED_IFORM_RDMSR_DEFINED 1 +#define XED_IFORM_RDPID_GPR32u32_DEFINED 1 +#define XED_IFORM_RDPID_GPR64u64_DEFINED 1 +#define XED_IFORM_RDPKRU_DEFINED 1 +#define XED_IFORM_RDPMC_DEFINED 1 +#define XED_IFORM_RDPRU_DEFINED 1 +#define XED_IFORM_RDRAND_GPRv_DEFINED 1 +#define XED_IFORM_RDSEED_GPRv_DEFINED 1 +#define XED_IFORM_RDSSPD_GPR32u32_DEFINED 1 +#define XED_IFORM_RDSSPQ_GPR64u64_DEFINED 1 +#define XED_IFORM_RDTSC_DEFINED 1 +#define XED_IFORM_RDTSCP_DEFINED 1 +#define XED_IFORM_REPE_CMPSB_DEFINED 1 +#define XED_IFORM_REPE_CMPSD_DEFINED 1 +#define XED_IFORM_REPE_CMPSQ_DEFINED 1 +#define XED_IFORM_REPE_CMPSW_DEFINED 1 +#define XED_IFORM_REPE_SCASB_DEFINED 1 +#define XED_IFORM_REPE_SCASD_DEFINED 1 +#define XED_IFORM_REPE_SCASQ_DEFINED 1 +#define XED_IFORM_REPE_SCASW_DEFINED 1 +#define XED_IFORM_REPNE_CMPSB_DEFINED 1 +#define XED_IFORM_REPNE_CMPSD_DEFINED 1 +#define XED_IFORM_REPNE_CMPSQ_DEFINED 1 +#define XED_IFORM_REPNE_CMPSW_DEFINED 1 +#define XED_IFORM_REPNE_SCASB_DEFINED 1 +#define XED_IFORM_REPNE_SCASD_DEFINED 1 +#define XED_IFORM_REPNE_SCASQ_DEFINED 1 +#define XED_IFORM_REPNE_SCASW_DEFINED 1 +#define XED_IFORM_REP_INSB_DEFINED 1 +#define XED_IFORM_REP_INSD_DEFINED 1 +#define XED_IFORM_REP_INSW_DEFINED 1 +#define XED_IFORM_REP_LODSB_DEFINED 1 +#define XED_IFORM_REP_LODSD_DEFINED 1 +#define XED_IFORM_REP_LODSQ_DEFINED 1 +#define XED_IFORM_REP_LODSW_DEFINED 1 +#define XED_IFORM_REP_MONTMUL_DEFINED 1 +#define XED_IFORM_REP_MOVSB_DEFINED 1 +#define XED_IFORM_REP_MOVSD_DEFINED 1 +#define XED_IFORM_REP_MOVSQ_DEFINED 1 +#define XED_IFORM_REP_MOVSW_DEFINED 1 +#define XED_IFORM_REP_OUTSB_DEFINED 1 +#define XED_IFORM_REP_OUTSD_DEFINED 1 +#define XED_IFORM_REP_OUTSW_DEFINED 1 +#define XED_IFORM_REP_STOSB_DEFINED 1 +#define XED_IFORM_REP_STOSD_DEFINED 1 +#define XED_IFORM_REP_STOSQ_DEFINED 1 +#define XED_IFORM_REP_STOSW_DEFINED 1 +#define XED_IFORM_REP_XCRYPTCBC_DEFINED 1 +#define XED_IFORM_REP_XCRYPTCFB_DEFINED 1 +#define XED_IFORM_REP_XCRYPTCTR_DEFINED 1 +#define XED_IFORM_REP_XCRYPTECB_DEFINED 1 +#define XED_IFORM_REP_XCRYPTOFB_DEFINED 1 +#define XED_IFORM_REP_XSHA1_DEFINED 1 +#define XED_IFORM_REP_XSHA256_DEFINED 1 +#define XED_IFORM_REP_XSTORE_DEFINED 1 +#define XED_IFORM_RET_FAR_DEFINED 1 +#define XED_IFORM_RET_FAR_IMMw_DEFINED 1 +#define XED_IFORM_RET_NEAR_DEFINED 1 +#define XED_IFORM_RET_NEAR_IMMw_DEFINED 1 +#define XED_IFORM_RMPADJUST_RAX_RCX_RDX_DEFINED 1 +#define XED_IFORM_RMPUPDATE_RAX_RCX_DEFINED 1 +#define XED_IFORM_ROL_GPR8_CL_DEFINED 1 +#define XED_IFORM_ROL_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_ROL_GPR8_ONE_DEFINED 1 +#define XED_IFORM_ROL_GPRv_CL_DEFINED 1 +#define XED_IFORM_ROL_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ROL_GPRv_ONE_DEFINED 1 +#define XED_IFORM_ROL_MEMb_CL_DEFINED 1 +#define XED_IFORM_ROL_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_ROL_MEMb_ONE_DEFINED 1 +#define XED_IFORM_ROL_MEMv_CL_DEFINED 1 +#define XED_IFORM_ROL_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ROL_MEMv_ONE_DEFINED 1 +#define XED_IFORM_ROR_GPR8_CL_DEFINED 1 +#define XED_IFORM_ROR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_ROR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_ROR_GPRv_CL_DEFINED 1 +#define XED_IFORM_ROR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_ROR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_ROR_MEMb_CL_DEFINED 1 +#define XED_IFORM_ROR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_ROR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_ROR_MEMv_CL_DEFINED 1 +#define XED_IFORM_ROR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_ROR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_RORX_VGPR32d_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb_DEFINED 1 +#define XED_IFORM_RORX_VGPR64q_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb_DEFINED 1 +#define XED_IFORM_RSM_DEFINED 1 +#define XED_IFORM_RSQRTPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_RSQRTPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_RSQRTSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_RSQRTSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_RSTORSSP_MEMu64_DEFINED 1 +#define XED_IFORM_SAHF_DEFINED 1 +#define XED_IFORM_SALC_DEFINED 1 +#define XED_IFORM_SAR_GPR8_CL_DEFINED 1 +#define XED_IFORM_SAR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_SAR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_SAR_GPRv_CL_DEFINED 1 +#define XED_IFORM_SAR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SAR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_SAR_MEMb_CL_DEFINED 1 +#define XED_IFORM_SAR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_SAR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_SAR_MEMv_CL_DEFINED 1 +#define XED_IFORM_SAR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SAR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_SAVEPREVSSP_DEFINED 1 +#define XED_IFORM_SBB_AL_IMMb_DEFINED 1 +#define XED_IFORM_SBB_GPR8_GPR8_18_DEFINED 1 +#define XED_IFORM_SBB_GPR8_GPR8_1A_DEFINED 1 +#define XED_IFORM_SBB_GPR8_IMMb_80r3_DEFINED 1 +#define XED_IFORM_SBB_GPR8_IMMb_82r3_DEFINED 1 +#define XED_IFORM_SBB_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_SBB_GPRv_GPRv_19_DEFINED 1 +#define XED_IFORM_SBB_GPRv_GPRv_1B_DEFINED 1 +#define XED_IFORM_SBB_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SBB_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_SBB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_SBB_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SBB_MEMb_IMMb_80r3_DEFINED 1 +#define XED_IFORM_SBB_MEMb_IMMb_82r3_DEFINED 1 +#define XED_IFORM_SBB_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SBB_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SBB_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SBB_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SBB_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SCASB_DEFINED 1 +#define XED_IFORM_SCASD_DEFINED 1 +#define XED_IFORM_SCASQ_DEFINED 1 +#define XED_IFORM_SCASW_DEFINED 1 +#define XED_IFORM_SEAMCALL_DEFINED 1 +#define XED_IFORM_SEAMOPS_DEFINED 1 +#define XED_IFORM_SEAMRET_DEFINED 1 +#define XED_IFORM_SENDUIPI_GPR32u32_DEFINED 1 +#define XED_IFORM_SERIALIZE_DEFINED 1 +#define XED_IFORM_SETB_GPR8_DEFINED 1 +#define XED_IFORM_SETB_MEMb_DEFINED 1 +#define XED_IFORM_SETBE_GPR8_DEFINED 1 +#define XED_IFORM_SETBE_MEMb_DEFINED 1 +#define XED_IFORM_SETL_GPR8_DEFINED 1 +#define XED_IFORM_SETL_MEMb_DEFINED 1 +#define XED_IFORM_SETLE_GPR8_DEFINED 1 +#define XED_IFORM_SETLE_MEMb_DEFINED 1 +#define XED_IFORM_SETNB_GPR8_DEFINED 1 +#define XED_IFORM_SETNB_MEMb_DEFINED 1 +#define XED_IFORM_SETNBE_GPR8_DEFINED 1 +#define XED_IFORM_SETNBE_MEMb_DEFINED 1 +#define XED_IFORM_SETNL_GPR8_DEFINED 1 +#define XED_IFORM_SETNL_MEMb_DEFINED 1 +#define XED_IFORM_SETNLE_GPR8_DEFINED 1 +#define XED_IFORM_SETNLE_MEMb_DEFINED 1 +#define XED_IFORM_SETNO_GPR8_DEFINED 1 +#define XED_IFORM_SETNO_MEMb_DEFINED 1 +#define XED_IFORM_SETNP_GPR8_DEFINED 1 +#define XED_IFORM_SETNP_MEMb_DEFINED 1 +#define XED_IFORM_SETNS_GPR8_DEFINED 1 +#define XED_IFORM_SETNS_MEMb_DEFINED 1 +#define XED_IFORM_SETNZ_GPR8_DEFINED 1 +#define XED_IFORM_SETNZ_MEMb_DEFINED 1 +#define XED_IFORM_SETO_GPR8_DEFINED 1 +#define XED_IFORM_SETO_MEMb_DEFINED 1 +#define XED_IFORM_SETP_GPR8_DEFINED 1 +#define XED_IFORM_SETP_MEMb_DEFINED 1 +#define XED_IFORM_SETS_GPR8_DEFINED 1 +#define XED_IFORM_SETS_MEMb_DEFINED 1 +#define XED_IFORM_SETSSBSY_DEFINED 1 +#define XED_IFORM_SETZ_GPR8_DEFINED 1 +#define XED_IFORM_SETZ_MEMb_DEFINED 1 +#define XED_IFORM_SFENCE_DEFINED 1 +#define XED_IFORM_SGDT_MEMs_DEFINED 1 +#define XED_IFORM_SGDT_MEMs64_DEFINED 1 +#define XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA_DEFINED 1 +#define XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA_DEFINED 1 +#define XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA_DEFINED 1 +#define XED_IFORM_SHL_GPR8_CL_D2r4_DEFINED 1 +#define XED_IFORM_SHL_GPR8_CL_D2r6_DEFINED 1 +#define XED_IFORM_SHL_GPR8_IMMb_C0r4_DEFINED 1 +#define XED_IFORM_SHL_GPR8_IMMb_C0r6_DEFINED 1 +#define XED_IFORM_SHL_GPR8_ONE_D0r4_DEFINED 1 +#define XED_IFORM_SHL_GPR8_ONE_D0r6_DEFINED 1 +#define XED_IFORM_SHL_GPRv_CL_D3r4_DEFINED 1 +#define XED_IFORM_SHL_GPRv_CL_D3r6_DEFINED 1 +#define XED_IFORM_SHL_GPRv_IMMb_C1r4_DEFINED 1 +#define XED_IFORM_SHL_GPRv_IMMb_C1r6_DEFINED 1 +#define XED_IFORM_SHL_GPRv_ONE_D1r4_DEFINED 1 +#define XED_IFORM_SHL_GPRv_ONE_D1r6_DEFINED 1 +#define XED_IFORM_SHL_MEMb_CL_D2r4_DEFINED 1 +#define XED_IFORM_SHL_MEMb_CL_D2r6_DEFINED 1 +#define XED_IFORM_SHL_MEMb_IMMb_C0r4_DEFINED 1 +#define XED_IFORM_SHL_MEMb_IMMb_C0r6_DEFINED 1 +#define XED_IFORM_SHL_MEMb_ONE_D0r4_DEFINED 1 +#define XED_IFORM_SHL_MEMb_ONE_D0r6_DEFINED 1 +#define XED_IFORM_SHL_MEMv_CL_D3r4_DEFINED 1 +#define XED_IFORM_SHL_MEMv_CL_D3r6_DEFINED 1 +#define XED_IFORM_SHL_MEMv_IMMb_C1r4_DEFINED 1 +#define XED_IFORM_SHL_MEMv_IMMb_C1r6_DEFINED 1 +#define XED_IFORM_SHL_MEMv_ONE_D1r4_DEFINED 1 +#define XED_IFORM_SHL_MEMv_ONE_D1r6_DEFINED 1 +#define XED_IFORM_SHLD_GPRv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHLD_GPRv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHLD_MEMv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHLD_MEMv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_SHR_GPR8_CL_DEFINED 1 +#define XED_IFORM_SHR_GPR8_IMMb_DEFINED 1 +#define XED_IFORM_SHR_GPR8_ONE_DEFINED 1 +#define XED_IFORM_SHR_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHR_GPRv_ONE_DEFINED 1 +#define XED_IFORM_SHR_MEMb_CL_DEFINED 1 +#define XED_IFORM_SHR_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_SHR_MEMb_ONE_DEFINED 1 +#define XED_IFORM_SHR_MEMv_CL_DEFINED 1 +#define XED_IFORM_SHR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SHR_MEMv_ONE_DEFINED 1 +#define XED_IFORM_SHRD_GPRv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHRD_GPRv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHRD_MEMv_GPRv_CL_DEFINED 1 +#define XED_IFORM_SHRD_MEMv_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d_DEFINED 1 +#define XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q_DEFINED 1 +#define XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q_DEFINED 1 +#define XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb_DEFINED 1 +#define XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb_DEFINED 1 +#define XED_IFORM_SHUFPS_XMMps_MEMps_IMMb_DEFINED 1 +#define XED_IFORM_SHUFPS_XMMps_XMMps_IMMb_DEFINED 1 +#define XED_IFORM_SIDT_MEMs_DEFINED 1 +#define XED_IFORM_SIDT_MEMs64_DEFINED 1 +#define XED_IFORM_SKINIT_EAX_DEFINED 1 +#define XED_IFORM_SLDT_GPRv_DEFINED 1 +#define XED_IFORM_SLDT_MEMw_DEFINED 1 +#define XED_IFORM_SLWPCB_VGPRyy_DEFINED 1 +#define XED_IFORM_SMSW_GPRv_DEFINED 1 +#define XED_IFORM_SMSW_MEMw_DEFINED 1 +#define XED_IFORM_SQRTPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_SQRTPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_SQRTPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_SQRTPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_SQRTSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_SQRTSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_SQRTSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_SQRTSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_STAC_DEFINED 1 +#define XED_IFORM_STC_DEFINED 1 +#define XED_IFORM_STD_DEFINED 1 +#define XED_IFORM_STGI_DEFINED 1 +#define XED_IFORM_STI_DEFINED 1 +#define XED_IFORM_STMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_STOSB_DEFINED 1 +#define XED_IFORM_STOSD_DEFINED 1 +#define XED_IFORM_STOSQ_DEFINED 1 +#define XED_IFORM_STOSW_DEFINED 1 +#define XED_IFORM_STR_GPRv_DEFINED 1 +#define XED_IFORM_STR_MEMw_DEFINED 1 +#define XED_IFORM_STTILECFG_MEM_DEFINED 1 +#define XED_IFORM_STUI_DEFINED 1 +#define XED_IFORM_SUB_AL_IMMb_DEFINED 1 +#define XED_IFORM_SUB_GPR8_GPR8_28_DEFINED 1 +#define XED_IFORM_SUB_GPR8_GPR8_2A_DEFINED 1 +#define XED_IFORM_SUB_GPR8_IMMb_80r5_DEFINED 1 +#define XED_IFORM_SUB_GPR8_IMMb_82r5_DEFINED 1 +#define XED_IFORM_SUB_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_SUB_GPRv_GPRv_29_DEFINED 1 +#define XED_IFORM_SUB_GPRv_GPRv_2B_DEFINED 1 +#define XED_IFORM_SUB_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_SUB_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_SUB_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_SUB_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SUB_MEMb_IMMb_80r5_DEFINED 1 +#define XED_IFORM_SUB_MEMb_IMMb_82r5_DEFINED 1 +#define XED_IFORM_SUB_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SUB_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SUB_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SUB_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_SUBPD_XMMpd_MEMpd_DEFINED 1 +#define XED_IFORM_SUBPD_XMMpd_XMMpd_DEFINED 1 +#define XED_IFORM_SUBPS_XMMps_MEMps_DEFINED 1 +#define XED_IFORM_SUBPS_XMMps_XMMps_DEFINED 1 +#define XED_IFORM_SUBSD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_SUBSD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_SUBSS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_SUBSS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_SUB_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_SWAPGS_DEFINED 1 +#define XED_IFORM_SYSCALL_DEFINED 1 +#define XED_IFORM_SYSCALL_AMD_DEFINED 1 +#define XED_IFORM_SYSENTER_DEFINED 1 +#define XED_IFORM_SYSEXIT_DEFINED 1 +#define XED_IFORM_SYSRET_DEFINED 1 +#define XED_IFORM_SYSRET64_DEFINED 1 +#define XED_IFORM_SYSRET_AMD_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_T1MSKC_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_TDCALL_DEFINED 1 +#define XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TEST_AL_IMMb_DEFINED 1 +#define XED_IFORM_TEST_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_TEST_GPR8_IMMb_F6r0_DEFINED 1 +#define XED_IFORM_TEST_GPR8_IMMb_F6r1_DEFINED 1 +#define XED_IFORM_TEST_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_TEST_GPRv_IMMz_F7r0_DEFINED 1 +#define XED_IFORM_TEST_GPRv_IMMz_F7r1_DEFINED 1 +#define XED_IFORM_TEST_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_TEST_MEMb_IMMb_F6r0_DEFINED 1 +#define XED_IFORM_TEST_MEMb_IMMb_F6r1_DEFINED 1 +#define XED_IFORM_TEST_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_TEST_MEMv_IMMz_F7r0_DEFINED 1 +#define XED_IFORM_TEST_MEMv_IMMz_F7r1_DEFINED 1 +#define XED_IFORM_TEST_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_TESTUI_DEFINED 1 +#define XED_IFORM_TILELOADD_TMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_TILELOADDT1_TMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_TILERELEASE_DEFINED 1 +#define XED_IFORM_TILESTORED_MEMu32_TMMu32_DEFINED 1 +#define XED_IFORM_TILEZERO_TMMu32_DEFINED 1 +#define XED_IFORM_TLBSYNC_DEFINED 1 +#define XED_IFORM_TPAUSE_GPR32u32_DEFINED 1 +#define XED_IFORM_TZCNT_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_TZCNT_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_TZMSK_VGPR32d_MEMd_DEFINED 1 +#define XED_IFORM_TZMSK_VGPR32d_VGPR32d_DEFINED 1 +#define XED_IFORM_TZMSK_VGPRyy_MEMy_DEFINED 1 +#define XED_IFORM_TZMSK_VGPRyy_VGPRyy_DEFINED 1 +#define XED_IFORM_UCOMISD_XMMsd_MEMsd_DEFINED 1 +#define XED_IFORM_UCOMISD_XMMsd_XMMsd_DEFINED 1 +#define XED_IFORM_UCOMISS_XMMss_MEMss_DEFINED 1 +#define XED_IFORM_UCOMISS_XMMss_XMMss_DEFINED 1 +#define XED_IFORM_UD0_DEFINED 1 +#define XED_IFORM_UD0_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_UD0_GPR32_MEMd_DEFINED 1 +#define XED_IFORM_UD1_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_UD1_GPR32_MEMd_DEFINED 1 +#define XED_IFORM_UD2_DEFINED 1 +#define XED_IFORM_UIRET_DEFINED 1 +#define XED_IFORM_UMONITOR_GPRa_DEFINED 1 +#define XED_IFORM_UMWAIT_GPR32_DEFINED 1 +#define XED_IFORM_UNPCKHPD_XMMpd_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKHPD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_UNPCKHPS_XMMps_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKHPS_XMMps_XMMdq_DEFINED 1 +#define XED_IFORM_UNPCKLPD_XMMpd_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKLPD_XMMpd_XMMq_DEFINED 1 +#define XED_IFORM_UNPCKLPS_XMMps_MEMdq_DEFINED 1 +#define XED_IFORM_UNPCKLPS_XMMps_XMMq_DEFINED 1 +#define XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_DEFINED 1 +#define XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512_DEFINED 1 +#define XED_IFORM_VAESIMC_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VAESIMC_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VBROADCASTF128_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI128_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VCOMISD_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMdq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32d_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32d_XMMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SI_GPR64q_XMMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32d_XMMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64q_MEMd_DEFINED 1 +#define XED_IFORM_VCVTSS2SI_GPR64q_XMMd_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32d_MEMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32d_XMMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64q_MEMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2SI_GPR64q_XMMq_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32d_MEMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32d_XMMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64q_MEMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2SI_GPR64q_XMMd_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VERR_GPR16_DEFINED 1 +#define XED_IFORM_VERR_MEMw_DEFINED 1 +#define XED_IFORM_VERW_GPR16_DEFINED 1 +#define XED_IFORM_VERW_MEMw_DEFINED 1 +#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd_DEFINED 1 +#define XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VFRCZPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFRCZPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFRCZPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFRCZPD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFRCZPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VFRCZPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VFRCZPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VFRCZPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VFRCZSD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VFRCZSD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VFRCZSS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VFRCZSS_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256_DEFINED 1 +#define XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256_DEFINED 1 +#define XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VLDDQU_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VLDDQU_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VLDMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMCALL_DEFINED 1 +#define XED_IFORM_VMCLEAR_MEMq_DEFINED 1 +#define XED_IFORM_VMFUNC_DEFINED 1 +#define XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMLAUNCH_DEFINED 1 +#define XED_IFORM_VMLOAD_ArAX_DEFINED 1 +#define XED_IFORM_VMMCALL_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_28_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMdq_XMMdq_29_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_28_DEFINED 1 +#define XED_IFORM_VMOVAPD_YMMqq_YMMqq_29_DEFINED 1 +#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_28_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMdq_XMMdq_29_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_28_DEFINED 1 +#define XED_IFORM_VMOVAPS_YMMqq_YMMqq_29_DEFINED 1 +#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_GPR32d_XMMd_DEFINED 1 +#define XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_XMMdq_GPR32d_DEFINED 1 +#define XED_IFORM_VMOVD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVDQA_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQA_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVDQU_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVDQU_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQU_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F_DEFINED 1 +#define XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F_DEFINED 1 +#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPD_MEMq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVHPS_MEMq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPD_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVLPS_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVMSKPD_GPR32d_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVMSKPD_GPR32d_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVMSKPS_GPR32d_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVMSKPS_GPR32d_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPD_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVNTPS_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVQ_GPR64q_XMMq_DEFINED 1 +#define XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_MEMq_XMMq_7E_DEFINED 1 +#define XED_IFORM_VMOVQ_MEMq_XMMq_D6_DEFINED 1 +#define XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_GPR64q_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_MEMq_6E_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_MEMq_7E_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_XMMq_7E_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMdq_XMMq_D6_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSD_MEMq_XMMq_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSS_MEMd_XMMd_DEFINED 1 +#define XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_10_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMdq_XMMdq_11_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_10_DEFINED 1 +#define XED_IFORM_VMOVUPD_YMMqq_YMMqq_11_DEFINED 1 +#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_10_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMdq_XMMdq_11_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_10_DEFINED 1 +#define XED_IFORM_VMOVUPS_YMMqq_YMMqq_11_DEFINED 1 +#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512_DEFINED 1 +#define XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VMPTRLD_MEMq_DEFINED 1 +#define XED_IFORM_VMPTRST_MEMq_DEFINED 1 +#define XED_IFORM_VMREAD_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_VMREAD_GPR64_GPR64_DEFINED 1 +#define XED_IFORM_VMREAD_MEMd_GPR32_DEFINED 1 +#define XED_IFORM_VMREAD_MEMq_GPR64_DEFINED 1 +#define XED_IFORM_VMRESUME_DEFINED 1 +#define XED_IFORM_VMRUN_ArAX_DEFINED 1 +#define XED_IFORM_VMSAVE_DEFINED 1 +#define XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR32_GPR32_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR32_MEMd_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR64_GPR64_DEFINED 1 +#define XED_IFORM_VMWRITE_GPR64_MEMq_DEFINED 1 +#define XED_IFORM_VMXOFF_DEFINED 1 +#define XED_IFORM_VMXON_MEMq_DEFINED 1 +#define XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPABSB_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPABSB_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPABSD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPABSD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPABSW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPABSW_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMdq_MEMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMdq_XMMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMqq_MEMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMqq_XMMb_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMqq_XMMd_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMqq_MEMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMqq_XMMw_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5_DEFINED 1 +#define XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256_DEFINED 1 +#define XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPHADDBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDBQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDBQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHADDDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHADDUBD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDUWQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHADDWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHADDWQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHADDWQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBBW_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBBW_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHSUBDQ_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBDQ_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPHSUBWD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPHSUBWD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD_DEFINED 1 +#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVMSKB_GPR32d_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVMSKB_GPR32d_YMMqq_DEFINED 1 +#define XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_YMMqq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMdq_MEMw_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMdq_XMMw_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMqq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_YMMqq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_YMMqq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMqq_MEMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VPTEST_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPTEST_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPTEST_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPTEST_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512_DEFINED 1 +#define XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VRCPPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VRCPPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VRCPPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb_DEFINED 1 +#define XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER_DEFINED 1 +#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VRSQRTPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VRSQRTPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VRSQRTPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128_DEFINED 1 +#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256_DEFINED 1 +#define XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb_DEFINED 1 +#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSQRTPD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSQRTPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSTMXCSR_MEMd_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VTESTPD_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VTESTPD_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VTESTPD_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VTESTPD_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VTESTPS_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VTESTPS_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VTESTPS_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VTESTPS_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMdq_MEMq_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMdq_XMMq_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMdq_MEMd_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMdq_XMMd_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512_DEFINED 1 +#define XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq_DEFINED 1 +#define XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq_DEFINED 1 +#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq_DEFINED 1 +#define XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq_DEFINED 1 +#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512_DEFINED 1 +#define XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512_DEFINED 1 +#define XED_IFORM_VZEROALL_DEFINED 1 +#define XED_IFORM_VZEROUPPER_DEFINED 1 +#define XED_IFORM_WBINVD_DEFINED 1 +#define XED_IFORM_WBNOINVD_DEFINED 1 +#define XED_IFORM_WRFSBASE_GPRy_DEFINED 1 +#define XED_IFORM_WRGSBASE_GPRy_DEFINED 1 +#define XED_IFORM_WRMSR_DEFINED 1 +#define XED_IFORM_WRPKRU_DEFINED 1 +#define XED_IFORM_WRSSD_MEMu32_GPR32u32_DEFINED 1 +#define XED_IFORM_WRSSQ_MEMu64_GPR64u64_DEFINED 1 +#define XED_IFORM_WRUSSD_MEMu32_GPR32u32_DEFINED 1 +#define XED_IFORM_WRUSSQ_MEMu64_GPR64u64_DEFINED 1 +#define XED_IFORM_XABORT_IMMb_DEFINED 1 +#define XED_IFORM_XADD_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_XADD_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_XADD_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XADD_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XADD_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XADD_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XBEGIN_RELBRz_DEFINED 1 +#define XED_IFORM_XCHG_GPR8_GPR8_DEFINED 1 +#define XED_IFORM_XCHG_GPRv_GPRv_DEFINED 1 +#define XED_IFORM_XCHG_GPRv_OrAX_DEFINED 1 +#define XED_IFORM_XCHG_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XCHG_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XEND_DEFINED 1 +#define XED_IFORM_XGETBV_DEFINED 1 +#define XED_IFORM_XLAT_DEFINED 1 +#define XED_IFORM_XOR_AL_IMMb_DEFINED 1 +#define XED_IFORM_XOR_GPR8_GPR8_30_DEFINED 1 +#define XED_IFORM_XOR_GPR8_GPR8_32_DEFINED 1 +#define XED_IFORM_XOR_GPR8_IMMb_80r6_DEFINED 1 +#define XED_IFORM_XOR_GPR8_IMMb_82r6_DEFINED 1 +#define XED_IFORM_XOR_GPR8_MEMb_DEFINED 1 +#define XED_IFORM_XOR_GPRv_GPRv_31_DEFINED 1 +#define XED_IFORM_XOR_GPRv_GPRv_33_DEFINED 1 +#define XED_IFORM_XOR_GPRv_IMMb_DEFINED 1 +#define XED_IFORM_XOR_GPRv_IMMz_DEFINED 1 +#define XED_IFORM_XOR_GPRv_MEMv_DEFINED 1 +#define XED_IFORM_XOR_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XOR_MEMb_IMMb_80r6_DEFINED 1 +#define XED_IFORM_XOR_MEMb_IMMb_82r6_DEFINED 1 +#define XED_IFORM_XOR_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XOR_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_XOR_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_XOR_OrAX_IMMz_DEFINED 1 +#define XED_IFORM_XORPD_XMMxuq_MEMxuq_DEFINED 1 +#define XED_IFORM_XORPD_XMMxuq_XMMxuq_DEFINED 1 +#define XED_IFORM_XORPS_XMMxud_MEMxud_DEFINED 1 +#define XED_IFORM_XORPS_XMMxud_XMMxud_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMb_GPR8_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMv_GPRv_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMv_IMMb_DEFINED 1 +#define XED_IFORM_XOR_LOCK_MEMv_IMMz_DEFINED 1 +#define XED_IFORM_XRESLDTRK_DEFINED 1 +#define XED_IFORM_XRSTOR_MEMmxsave_DEFINED 1 +#define XED_IFORM_XRSTOR64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XRSTORS_MEMmxsave_DEFINED 1 +#define XED_IFORM_XRSTORS64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVE_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVE64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEC_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEC64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEOPT_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVEOPT64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVES_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSAVES64_MEMmxsave_DEFINED 1 +#define XED_IFORM_XSETBV_DEFINED 1 +#define XED_IFORM_XSTORE_DEFINED 1 +#define XED_IFORM_XSUSLDTRK_DEFINED 1 +#define XED_IFORM_XTEST_DEFINED 1 +#define XED_IFORM_LAST_DEFINED 1 +typedef enum { + XED_IFORM_INVALID=0, + XED_IFORM_AAA=1, + XED_IFORM_AAD_IMMb=2, + XED_IFORM_AAM_IMMb=3, + XED_IFORM_AAS=4, + XED_IFORM_ADC_AL_IMMb=5, + XED_IFORM_ADC_GPR8_GPR8_10=6, + XED_IFORM_ADC_GPR8_GPR8_12=7, + XED_IFORM_ADC_GPR8_IMMb_80r2=8, + XED_IFORM_ADC_GPR8_IMMb_82r2=9, + XED_IFORM_ADC_GPR8_MEMb=10, + XED_IFORM_ADC_GPRv_GPRv_11=11, + XED_IFORM_ADC_GPRv_GPRv_13=12, + XED_IFORM_ADC_GPRv_IMMb=13, + XED_IFORM_ADC_GPRv_IMMz=14, + XED_IFORM_ADC_GPRv_MEMv=15, + XED_IFORM_ADC_MEMb_GPR8=16, + XED_IFORM_ADC_MEMb_IMMb_80r2=17, + XED_IFORM_ADC_MEMb_IMMb_82r2=18, + XED_IFORM_ADC_MEMv_GPRv=19, + XED_IFORM_ADC_MEMv_IMMb=20, + XED_IFORM_ADC_MEMv_IMMz=21, + XED_IFORM_ADC_OrAX_IMMz=22, + XED_IFORM_ADCX_GPR32d_GPR32d=23, + XED_IFORM_ADCX_GPR32d_MEMd=24, + XED_IFORM_ADCX_GPR64q_GPR64q=25, + XED_IFORM_ADCX_GPR64q_MEMq=26, + XED_IFORM_ADC_LOCK_MEMb_GPR8=27, + XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2=28, + XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2=29, + XED_IFORM_ADC_LOCK_MEMv_GPRv=30, + XED_IFORM_ADC_LOCK_MEMv_IMMb=31, + XED_IFORM_ADC_LOCK_MEMv_IMMz=32, + XED_IFORM_ADD_AL_IMMb=33, + XED_IFORM_ADD_GPR8_GPR8_00=34, + XED_IFORM_ADD_GPR8_GPR8_02=35, + XED_IFORM_ADD_GPR8_IMMb_80r0=36, + XED_IFORM_ADD_GPR8_IMMb_82r0=37, + XED_IFORM_ADD_GPR8_MEMb=38, + XED_IFORM_ADD_GPRv_GPRv_01=39, + XED_IFORM_ADD_GPRv_GPRv_03=40, + XED_IFORM_ADD_GPRv_IMMb=41, + XED_IFORM_ADD_GPRv_IMMz=42, + XED_IFORM_ADD_GPRv_MEMv=43, + XED_IFORM_ADD_MEMb_GPR8=44, + XED_IFORM_ADD_MEMb_IMMb_80r0=45, + XED_IFORM_ADD_MEMb_IMMb_82r0=46, + XED_IFORM_ADD_MEMv_GPRv=47, + XED_IFORM_ADD_MEMv_IMMb=48, + XED_IFORM_ADD_MEMv_IMMz=49, + XED_IFORM_ADD_OrAX_IMMz=50, + XED_IFORM_ADDPD_XMMpd_MEMpd=51, + XED_IFORM_ADDPD_XMMpd_XMMpd=52, + XED_IFORM_ADDPS_XMMps_MEMps=53, + XED_IFORM_ADDPS_XMMps_XMMps=54, + XED_IFORM_ADDSD_XMMsd_MEMsd=55, + XED_IFORM_ADDSD_XMMsd_XMMsd=56, + XED_IFORM_ADDSS_XMMss_MEMss=57, + XED_IFORM_ADDSS_XMMss_XMMss=58, + XED_IFORM_ADDSUBPD_XMMpd_MEMpd=59, + XED_IFORM_ADDSUBPD_XMMpd_XMMpd=60, + XED_IFORM_ADDSUBPS_XMMps_MEMps=61, + XED_IFORM_ADDSUBPS_XMMps_XMMps=62, + XED_IFORM_ADD_LOCK_MEMb_GPR8=63, + XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0=64, + XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0=65, + XED_IFORM_ADD_LOCK_MEMv_GPRv=66, + XED_IFORM_ADD_LOCK_MEMv_IMMb=67, + XED_IFORM_ADD_LOCK_MEMv_IMMz=68, + XED_IFORM_ADOX_GPR32d_GPR32d=69, + XED_IFORM_ADOX_GPR32d_MEMd=70, + XED_IFORM_ADOX_GPR64q_GPR64q=71, + XED_IFORM_ADOX_GPR64q_MEMq=72, + XED_IFORM_AESDEC_XMMdq_MEMdq=73, + XED_IFORM_AESDEC_XMMdq_XMMdq=74, + XED_IFORM_AESDEC128KL_XMMu8_MEMu8=75, + XED_IFORM_AESDEC256KL_XMMu8_MEMu8=76, + XED_IFORM_AESDECLAST_XMMdq_MEMdq=77, + XED_IFORM_AESDECLAST_XMMdq_XMMdq=78, + XED_IFORM_AESDECWIDE128KL_MEMu8=79, + XED_IFORM_AESDECWIDE256KL_MEMu8=80, + XED_IFORM_AESENC_XMMdq_MEMdq=81, + XED_IFORM_AESENC_XMMdq_XMMdq=82, + XED_IFORM_AESENC128KL_XMMu8_MEMu8=83, + XED_IFORM_AESENC256KL_XMMu8_MEMu8=84, + XED_IFORM_AESENCLAST_XMMdq_MEMdq=85, + XED_IFORM_AESENCLAST_XMMdq_XMMdq=86, + XED_IFORM_AESENCWIDE128KL_MEMu8=87, + XED_IFORM_AESENCWIDE256KL_MEMu8=88, + XED_IFORM_AESIMC_XMMdq_MEMdq=89, + XED_IFORM_AESIMC_XMMdq_XMMdq=90, + XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb=91, + XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb=92, + XED_IFORM_AND_AL_IMMb=93, + XED_IFORM_AND_GPR8_GPR8_20=94, + XED_IFORM_AND_GPR8_GPR8_22=95, + XED_IFORM_AND_GPR8_IMMb_80r4=96, + XED_IFORM_AND_GPR8_IMMb_82r4=97, + XED_IFORM_AND_GPR8_MEMb=98, + XED_IFORM_AND_GPRv_GPRv_21=99, + XED_IFORM_AND_GPRv_GPRv_23=100, + XED_IFORM_AND_GPRv_IMMb=101, + XED_IFORM_AND_GPRv_IMMz=102, + XED_IFORM_AND_GPRv_MEMv=103, + XED_IFORM_AND_MEMb_GPR8=104, + XED_IFORM_AND_MEMb_IMMb_80r4=105, + XED_IFORM_AND_MEMb_IMMb_82r4=106, + XED_IFORM_AND_MEMv_GPRv=107, + XED_IFORM_AND_MEMv_IMMb=108, + XED_IFORM_AND_MEMv_IMMz=109, + XED_IFORM_AND_OrAX_IMMz=110, + XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd=111, + XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d=112, + XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq=113, + XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q=114, + XED_IFORM_ANDNPD_XMMxuq_MEMxuq=115, + XED_IFORM_ANDNPD_XMMxuq_XMMxuq=116, + XED_IFORM_ANDNPS_XMMxud_MEMxud=117, + XED_IFORM_ANDNPS_XMMxud_XMMxud=118, + XED_IFORM_ANDPD_XMMxuq_MEMxuq=119, + XED_IFORM_ANDPD_XMMxuq_XMMxuq=120, + XED_IFORM_ANDPS_XMMxud_MEMxud=121, + XED_IFORM_ANDPS_XMMxud_XMMxud=122, + XED_IFORM_AND_LOCK_MEMb_GPR8=123, + XED_IFORM_AND_LOCK_MEMb_IMMb_80r4=124, + XED_IFORM_AND_LOCK_MEMb_IMMb_82r4=125, + XED_IFORM_AND_LOCK_MEMv_GPRv=126, + XED_IFORM_AND_LOCK_MEMv_IMMb=127, + XED_IFORM_AND_LOCK_MEMv_IMMz=128, + XED_IFORM_ARPL_GPR16_GPR16=129, + XED_IFORM_ARPL_MEMw_GPR16=130, + XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d=131, + XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d=132, + XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q=133, + XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q=134, + XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd=135, + XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd=136, + XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd=137, + XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd=138, + XED_IFORM_BLCFILL_VGPR32d_MEMd=139, + XED_IFORM_BLCFILL_VGPR32d_VGPR32d=140, + XED_IFORM_BLCFILL_VGPRyy_MEMy=141, + XED_IFORM_BLCFILL_VGPRyy_VGPRyy=142, + XED_IFORM_BLCI_VGPR32d_MEMd=143, + XED_IFORM_BLCI_VGPR32d_VGPR32d=144, + XED_IFORM_BLCI_VGPRyy_MEMy=145, + XED_IFORM_BLCI_VGPRyy_VGPRyy=146, + XED_IFORM_BLCIC_VGPR32d_MEMd=147, + XED_IFORM_BLCIC_VGPR32d_VGPR32d=148, + XED_IFORM_BLCIC_VGPRyy_MEMy=149, + XED_IFORM_BLCIC_VGPRyy_VGPRyy=150, + XED_IFORM_BLCMSK_VGPR32d_MEMd=151, + XED_IFORM_BLCMSK_VGPR32d_VGPR32d=152, + XED_IFORM_BLCMSK_VGPRyy_MEMy=153, + XED_IFORM_BLCMSK_VGPRyy_VGPRyy=154, + XED_IFORM_BLCS_VGPR32d_MEMd=155, + XED_IFORM_BLCS_VGPR32d_VGPR32d=156, + XED_IFORM_BLCS_VGPRyy_MEMy=157, + XED_IFORM_BLCS_VGPRyy_VGPRyy=158, + XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb=159, + XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb=160, + XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb=161, + XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb=162, + XED_IFORM_BLENDVPD_XMMdq_MEMdq=163, + XED_IFORM_BLENDVPD_XMMdq_XMMdq=164, + XED_IFORM_BLENDVPS_XMMdq_MEMdq=165, + XED_IFORM_BLENDVPS_XMMdq_XMMdq=166, + XED_IFORM_BLSFILL_VGPR32d_MEMd=167, + XED_IFORM_BLSFILL_VGPR32d_VGPR32d=168, + XED_IFORM_BLSFILL_VGPRyy_MEMy=169, + XED_IFORM_BLSFILL_VGPRyy_VGPRyy=170, + XED_IFORM_BLSI_VGPR32d_MEMd=171, + XED_IFORM_BLSI_VGPR32d_VGPR32d=172, + XED_IFORM_BLSI_VGPR64q_MEMq=173, + XED_IFORM_BLSI_VGPR64q_VGPR64q=174, + XED_IFORM_BLSIC_VGPR32d_MEMd=175, + XED_IFORM_BLSIC_VGPR32d_VGPR32d=176, + XED_IFORM_BLSIC_VGPRyy_MEMy=177, + XED_IFORM_BLSIC_VGPRyy_VGPRyy=178, + XED_IFORM_BLSMSK_VGPR32d_MEMd=179, + XED_IFORM_BLSMSK_VGPR32d_VGPR32d=180, + XED_IFORM_BLSMSK_VGPR64q_MEMq=181, + XED_IFORM_BLSMSK_VGPR64q_VGPR64q=182, + XED_IFORM_BLSR_VGPR32d_MEMd=183, + XED_IFORM_BLSR_VGPR32d_VGPR32d=184, + XED_IFORM_BLSR_VGPR64q_MEMq=185, + XED_IFORM_BLSR_VGPR64q_VGPR64q=186, + XED_IFORM_BNDCL_BND_AGEN=187, + XED_IFORM_BNDCL_BND_GPR32=188, + XED_IFORM_BNDCL_BND_GPR64=189, + XED_IFORM_BNDCN_BND_AGEN=190, + XED_IFORM_BNDCN_BND_GPR32=191, + XED_IFORM_BNDCN_BND_GPR64=192, + XED_IFORM_BNDCU_BND_AGEN=193, + XED_IFORM_BNDCU_BND_GPR32=194, + XED_IFORM_BNDCU_BND_GPR64=195, + XED_IFORM_BNDLDX_BND_MEMbnd32=196, + XED_IFORM_BNDLDX_BND_MEMbnd64=197, + XED_IFORM_BNDMK_BND_AGEN=198, + XED_IFORM_BNDMOV_BND_BND=199, + XED_IFORM_BNDMOV_BND_MEMdq=200, + XED_IFORM_BNDMOV_BND_MEMq=201, + XED_IFORM_BNDMOV_MEMdq_BND=202, + XED_IFORM_BNDMOV_MEMq_BND=203, + XED_IFORM_BNDSTX_MEMbnd32_BND=204, + XED_IFORM_BNDSTX_MEMbnd64_BND=205, + XED_IFORM_BOUND_GPRv_MEMa16=206, + XED_IFORM_BOUND_GPRv_MEMa32=207, + XED_IFORM_BSF_GPRv_GPRv=208, + XED_IFORM_BSF_GPRv_MEMv=209, + XED_IFORM_BSR_GPRv_GPRv=210, + XED_IFORM_BSR_GPRv_MEMv=211, + XED_IFORM_BSWAP_GPRv=212, + XED_IFORM_BT_GPRv_GPRv=213, + XED_IFORM_BT_GPRv_IMMb=214, + XED_IFORM_BT_MEMv_GPRv=215, + XED_IFORM_BT_MEMv_IMMb=216, + XED_IFORM_BTC_GPRv_GPRv=217, + XED_IFORM_BTC_GPRv_IMMb=218, + XED_IFORM_BTC_MEMv_GPRv=219, + XED_IFORM_BTC_MEMv_IMMb=220, + XED_IFORM_BTC_LOCK_MEMv_GPRv=221, + XED_IFORM_BTC_LOCK_MEMv_IMMb=222, + XED_IFORM_BTR_GPRv_GPRv=223, + XED_IFORM_BTR_GPRv_IMMb=224, + XED_IFORM_BTR_MEMv_GPRv=225, + XED_IFORM_BTR_MEMv_IMMb=226, + XED_IFORM_BTR_LOCK_MEMv_GPRv=227, + XED_IFORM_BTR_LOCK_MEMv_IMMb=228, + XED_IFORM_BTS_GPRv_GPRv=229, + XED_IFORM_BTS_GPRv_IMMb=230, + XED_IFORM_BTS_MEMv_GPRv=231, + XED_IFORM_BTS_MEMv_IMMb=232, + XED_IFORM_BTS_LOCK_MEMv_GPRv=233, + XED_IFORM_BTS_LOCK_MEMv_IMMb=234, + XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d=235, + XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d=236, + XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q=237, + XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q=238, + XED_IFORM_CALL_FAR_MEMp2=239, + XED_IFORM_CALL_FAR_PTRp_IMMw=240, + XED_IFORM_CALL_NEAR_GPRv=241, + XED_IFORM_CALL_NEAR_MEMv=242, + XED_IFORM_CALL_NEAR_RELBRd=243, + XED_IFORM_CALL_NEAR_RELBRz=244, + XED_IFORM_CBW=245, + XED_IFORM_CDQ=246, + XED_IFORM_CDQE=247, + XED_IFORM_CLAC=248, + XED_IFORM_CLC=249, + XED_IFORM_CLD=250, + XED_IFORM_CLDEMOTE_MEMu8=251, + XED_IFORM_CLFLUSH_MEMmprefetch=252, + XED_IFORM_CLFLUSHOPT_MEMmprefetch=253, + XED_IFORM_CLGI=254, + XED_IFORM_CLI=255, + XED_IFORM_CLRSSBSY_MEMu64=256, + XED_IFORM_CLTS=257, + XED_IFORM_CLUI=258, + XED_IFORM_CLWB_MEMmprefetch=259, + XED_IFORM_CLZERO=260, + XED_IFORM_CMC=261, + XED_IFORM_CMOVB_GPRv_GPRv=262, + XED_IFORM_CMOVB_GPRv_MEMv=263, + XED_IFORM_CMOVBE_GPRv_GPRv=264, + XED_IFORM_CMOVBE_GPRv_MEMv=265, + XED_IFORM_CMOVL_GPRv_GPRv=266, + XED_IFORM_CMOVL_GPRv_MEMv=267, + XED_IFORM_CMOVLE_GPRv_GPRv=268, + XED_IFORM_CMOVLE_GPRv_MEMv=269, + XED_IFORM_CMOVNB_GPRv_GPRv=270, + XED_IFORM_CMOVNB_GPRv_MEMv=271, + XED_IFORM_CMOVNBE_GPRv_GPRv=272, + XED_IFORM_CMOVNBE_GPRv_MEMv=273, + XED_IFORM_CMOVNL_GPRv_GPRv=274, + XED_IFORM_CMOVNL_GPRv_MEMv=275, + XED_IFORM_CMOVNLE_GPRv_GPRv=276, + XED_IFORM_CMOVNLE_GPRv_MEMv=277, + XED_IFORM_CMOVNO_GPRv_GPRv=278, + XED_IFORM_CMOVNO_GPRv_MEMv=279, + XED_IFORM_CMOVNP_GPRv_GPRv=280, + XED_IFORM_CMOVNP_GPRv_MEMv=281, + XED_IFORM_CMOVNS_GPRv_GPRv=282, + XED_IFORM_CMOVNS_GPRv_MEMv=283, + XED_IFORM_CMOVNZ_GPRv_GPRv=284, + XED_IFORM_CMOVNZ_GPRv_MEMv=285, + XED_IFORM_CMOVO_GPRv_GPRv=286, + XED_IFORM_CMOVO_GPRv_MEMv=287, + XED_IFORM_CMOVP_GPRv_GPRv=288, + XED_IFORM_CMOVP_GPRv_MEMv=289, + XED_IFORM_CMOVS_GPRv_GPRv=290, + XED_IFORM_CMOVS_GPRv_MEMv=291, + XED_IFORM_CMOVZ_GPRv_GPRv=292, + XED_IFORM_CMOVZ_GPRv_MEMv=293, + XED_IFORM_CMP_AL_IMMb=294, + XED_IFORM_CMP_GPR8_GPR8_38=295, + XED_IFORM_CMP_GPR8_GPR8_3A=296, + XED_IFORM_CMP_GPR8_IMMb_80r7=297, + XED_IFORM_CMP_GPR8_IMMb_82r7=298, + XED_IFORM_CMP_GPR8_MEMb=299, + XED_IFORM_CMP_GPRv_GPRv_39=300, + XED_IFORM_CMP_GPRv_GPRv_3B=301, + XED_IFORM_CMP_GPRv_IMMb=302, + XED_IFORM_CMP_GPRv_IMMz=303, + XED_IFORM_CMP_GPRv_MEMv=304, + XED_IFORM_CMP_MEMb_GPR8=305, + XED_IFORM_CMP_MEMb_IMMb_80r7=306, + XED_IFORM_CMP_MEMb_IMMb_82r7=307, + XED_IFORM_CMP_MEMv_GPRv=308, + XED_IFORM_CMP_MEMv_IMMb=309, + XED_IFORM_CMP_MEMv_IMMz=310, + XED_IFORM_CMP_OrAX_IMMz=311, + XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb=312, + XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb=313, + XED_IFORM_CMPPS_XMMps_MEMps_IMMb=314, + XED_IFORM_CMPPS_XMMps_XMMps_IMMb=315, + XED_IFORM_CMPSB=316, + XED_IFORM_CMPSD=317, + XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb=318, + XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb=319, + XED_IFORM_CMPSQ=320, + XED_IFORM_CMPSS_XMMss_MEMss_IMMb=321, + XED_IFORM_CMPSS_XMMss_XMMss_IMMb=322, + XED_IFORM_CMPSW=323, + XED_IFORM_CMPXCHG_GPR8_GPR8=324, + XED_IFORM_CMPXCHG_GPRv_GPRv=325, + XED_IFORM_CMPXCHG_MEMb_GPR8=326, + XED_IFORM_CMPXCHG_MEMv_GPRv=327, + XED_IFORM_CMPXCHG16B_MEMdq=328, + XED_IFORM_CMPXCHG16B_LOCK_MEMdq=329, + XED_IFORM_CMPXCHG8B_MEMq=330, + XED_IFORM_CMPXCHG8B_LOCK_MEMq=331, + XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8=332, + XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv=333, + XED_IFORM_COMISD_XMMsd_MEMsd=334, + XED_IFORM_COMISD_XMMsd_XMMsd=335, + XED_IFORM_COMISS_XMMss_MEMss=336, + XED_IFORM_COMISS_XMMss_XMMss=337, + XED_IFORM_CPUID=338, + XED_IFORM_CQO=339, + XED_IFORM_CRC32_GPRyy_GPR8b=340, + XED_IFORM_CRC32_GPRyy_GPRv=341, + XED_IFORM_CRC32_GPRyy_MEMb=342, + XED_IFORM_CRC32_GPRyy_MEMv=343, + XED_IFORM_CVTDQ2PD_XMMpd_MEMq=344, + XED_IFORM_CVTDQ2PD_XMMpd_XMMq=345, + XED_IFORM_CVTDQ2PS_XMMps_MEMdq=346, + XED_IFORM_CVTDQ2PS_XMMps_XMMdq=347, + XED_IFORM_CVTPD2DQ_XMMdq_MEMpd=348, + XED_IFORM_CVTPD2DQ_XMMdq_XMMpd=349, + XED_IFORM_CVTPD2PI_MMXq_MEMpd=350, + XED_IFORM_CVTPD2PI_MMXq_XMMpd=351, + XED_IFORM_CVTPD2PS_XMMps_MEMpd=352, + XED_IFORM_CVTPD2PS_XMMps_XMMpd=353, + XED_IFORM_CVTPI2PD_XMMpd_MEMq=354, + XED_IFORM_CVTPI2PD_XMMpd_MMXq=355, + XED_IFORM_CVTPI2PS_XMMq_MEMq=356, + XED_IFORM_CVTPI2PS_XMMq_MMXq=357, + XED_IFORM_CVTPS2DQ_XMMdq_MEMps=358, + XED_IFORM_CVTPS2DQ_XMMdq_XMMps=359, + XED_IFORM_CVTPS2PD_XMMpd_MEMq=360, + XED_IFORM_CVTPS2PD_XMMpd_XMMq=361, + XED_IFORM_CVTPS2PI_MMXq_MEMq=362, + XED_IFORM_CVTPS2PI_MMXq_XMMq=363, + XED_IFORM_CVTSD2SI_GPR32d_MEMsd=364, + XED_IFORM_CVTSD2SI_GPR32d_XMMsd=365, + XED_IFORM_CVTSD2SI_GPR64q_MEMsd=366, + XED_IFORM_CVTSD2SI_GPR64q_XMMsd=367, + XED_IFORM_CVTSD2SS_XMMss_MEMsd=368, + XED_IFORM_CVTSD2SS_XMMss_XMMsd=369, + XED_IFORM_CVTSI2SD_XMMsd_GPR32d=370, + XED_IFORM_CVTSI2SD_XMMsd_GPR64q=371, + XED_IFORM_CVTSI2SD_XMMsd_MEMd=372, + XED_IFORM_CVTSI2SD_XMMsd_MEMq=373, + XED_IFORM_CVTSI2SS_XMMss_GPR32d=374, + XED_IFORM_CVTSI2SS_XMMss_GPR64q=375, + XED_IFORM_CVTSI2SS_XMMss_MEMd=376, + XED_IFORM_CVTSI2SS_XMMss_MEMq=377, + XED_IFORM_CVTSS2SD_XMMsd_MEMss=378, + XED_IFORM_CVTSS2SD_XMMsd_XMMss=379, + XED_IFORM_CVTSS2SI_GPR32d_MEMss=380, + XED_IFORM_CVTSS2SI_GPR32d_XMMss=381, + XED_IFORM_CVTSS2SI_GPR64q_MEMss=382, + XED_IFORM_CVTSS2SI_GPR64q_XMMss=383, + XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd=384, + XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd=385, + XED_IFORM_CVTTPD2PI_MMXq_MEMpd=386, + XED_IFORM_CVTTPD2PI_MMXq_XMMpd=387, + XED_IFORM_CVTTPS2DQ_XMMdq_MEMps=388, + XED_IFORM_CVTTPS2DQ_XMMdq_XMMps=389, + XED_IFORM_CVTTPS2PI_MMXq_MEMq=390, + XED_IFORM_CVTTPS2PI_MMXq_XMMq=391, + XED_IFORM_CVTTSD2SI_GPR32d_MEMsd=392, + XED_IFORM_CVTTSD2SI_GPR32d_XMMsd=393, + XED_IFORM_CVTTSD2SI_GPR64q_MEMsd=394, + XED_IFORM_CVTTSD2SI_GPR64q_XMMsd=395, + XED_IFORM_CVTTSS2SI_GPR32d_MEMss=396, + XED_IFORM_CVTTSS2SI_GPR32d_XMMss=397, + XED_IFORM_CVTTSS2SI_GPR64q_MEMss=398, + XED_IFORM_CVTTSS2SI_GPR64q_XMMss=399, + XED_IFORM_CWD=400, + XED_IFORM_CWDE=401, + XED_IFORM_DAA=402, + XED_IFORM_DAS=403, + XED_IFORM_DEC_GPR8=404, + XED_IFORM_DEC_GPRv_48=405, + XED_IFORM_DEC_GPRv_FFr1=406, + XED_IFORM_DEC_MEMb=407, + XED_IFORM_DEC_MEMv=408, + XED_IFORM_DEC_LOCK_MEMb=409, + XED_IFORM_DEC_LOCK_MEMv=410, + XED_IFORM_DIV_GPR8=411, + XED_IFORM_DIV_GPRv=412, + XED_IFORM_DIV_MEMb=413, + XED_IFORM_DIV_MEMv=414, + XED_IFORM_DIVPD_XMMpd_MEMpd=415, + XED_IFORM_DIVPD_XMMpd_XMMpd=416, + XED_IFORM_DIVPS_XMMps_MEMps=417, + XED_IFORM_DIVPS_XMMps_XMMps=418, + XED_IFORM_DIVSD_XMMsd_MEMsd=419, + XED_IFORM_DIVSD_XMMsd_XMMsd=420, + XED_IFORM_DIVSS_XMMss_MEMss=421, + XED_IFORM_DIVSS_XMMss_XMMss=422, + XED_IFORM_DPPD_XMMdq_MEMdq_IMMb=423, + XED_IFORM_DPPD_XMMdq_XMMdq_IMMb=424, + XED_IFORM_DPPS_XMMdq_MEMdq_IMMb=425, + XED_IFORM_DPPS_XMMdq_XMMdq_IMMb=426, + XED_IFORM_EMMS=427, + XED_IFORM_ENCLS=428, + XED_IFORM_ENCLU=429, + XED_IFORM_ENCLV=430, + XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8=431, + XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8=432, + XED_IFORM_ENDBR32=433, + XED_IFORM_ENDBR64=434, + XED_IFORM_ENQCMD_GPRa_MEMu32=435, + XED_IFORM_ENQCMDS_GPRa_MEMu32=436, + XED_IFORM_ENTER_IMMw_IMMb=437, + XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb=438, + XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb=439, + XED_IFORM_EXTRQ_XMMq_IMMb_IMMb=440, + XED_IFORM_EXTRQ_XMMq_XMMdq=441, + XED_IFORM_F2XM1=442, + XED_IFORM_FABS=443, + XED_IFORM_FADD_ST0_MEMm64real=444, + XED_IFORM_FADD_ST0_MEMmem32real=445, + XED_IFORM_FADD_ST0_X87=446, + XED_IFORM_FADD_X87_ST0=447, + XED_IFORM_FADDP_X87_ST0=448, + XED_IFORM_FBLD_ST0_MEMmem80dec=449, + XED_IFORM_FBSTP_MEMmem80dec_ST0=450, + XED_IFORM_FCHS=451, + XED_IFORM_FCMOVB_ST0_X87=452, + XED_IFORM_FCMOVBE_ST0_X87=453, + XED_IFORM_FCMOVE_ST0_X87=454, + XED_IFORM_FCMOVNB_ST0_X87=455, + XED_IFORM_FCMOVNBE_ST0_X87=456, + XED_IFORM_FCMOVNE_ST0_X87=457, + XED_IFORM_FCMOVNU_ST0_X87=458, + XED_IFORM_FCMOVU_ST0_X87=459, + XED_IFORM_FCOM_ST0_MEMm64real=460, + XED_IFORM_FCOM_ST0_MEMmem32real=461, + XED_IFORM_FCOM_ST0_X87=462, + XED_IFORM_FCOM_ST0_X87_DCD0=463, + XED_IFORM_FCOMI_ST0_X87=464, + XED_IFORM_FCOMIP_ST0_X87=465, + XED_IFORM_FCOMP_ST0_MEMm64real=466, + XED_IFORM_FCOMP_ST0_MEMmem32real=467, + XED_IFORM_FCOMP_ST0_X87=468, + XED_IFORM_FCOMP_ST0_X87_DCD1=469, + XED_IFORM_FCOMP_ST0_X87_DED0=470, + XED_IFORM_FCOMPP=471, + XED_IFORM_FCOS=472, + XED_IFORM_FDECSTP=473, + XED_IFORM_FDISI8087_NOP=474, + XED_IFORM_FDIV_ST0_MEMm64real=475, + XED_IFORM_FDIV_ST0_MEMmem32real=476, + XED_IFORM_FDIV_ST0_X87=477, + XED_IFORM_FDIV_X87_ST0=478, + XED_IFORM_FDIVP_X87_ST0=479, + XED_IFORM_FDIVR_ST0_MEMm64real=480, + XED_IFORM_FDIVR_ST0_MEMmem32real=481, + XED_IFORM_FDIVR_ST0_X87=482, + XED_IFORM_FDIVR_X87_ST0=483, + XED_IFORM_FDIVRP_X87_ST0=484, + XED_IFORM_FEMMS=485, + XED_IFORM_FENI8087_NOP=486, + XED_IFORM_FFREE_X87=487, + XED_IFORM_FFREEP_X87=488, + XED_IFORM_FIADD_ST0_MEMmem16int=489, + XED_IFORM_FIADD_ST0_MEMmem32int=490, + XED_IFORM_FICOM_ST0_MEMmem16int=491, + XED_IFORM_FICOM_ST0_MEMmem32int=492, + XED_IFORM_FICOMP_ST0_MEMmem16int=493, + XED_IFORM_FICOMP_ST0_MEMmem32int=494, + XED_IFORM_FIDIV_ST0_MEMmem16int=495, + XED_IFORM_FIDIV_ST0_MEMmem32int=496, + XED_IFORM_FIDIVR_ST0_MEMmem16int=497, + XED_IFORM_FIDIVR_ST0_MEMmem32int=498, + XED_IFORM_FILD_ST0_MEMm64int=499, + XED_IFORM_FILD_ST0_MEMmem16int=500, + XED_IFORM_FILD_ST0_MEMmem32int=501, + XED_IFORM_FIMUL_ST0_MEMmem16int=502, + XED_IFORM_FIMUL_ST0_MEMmem32int=503, + XED_IFORM_FINCSTP=504, + XED_IFORM_FIST_MEMmem16int_ST0=505, + XED_IFORM_FIST_MEMmem32int_ST0=506, + XED_IFORM_FISTP_MEMm64int_ST0=507, + XED_IFORM_FISTP_MEMmem16int_ST0=508, + XED_IFORM_FISTP_MEMmem32int_ST0=509, + XED_IFORM_FISTTP_MEMm64int_ST0=510, + XED_IFORM_FISTTP_MEMmem16int_ST0=511, + XED_IFORM_FISTTP_MEMmem32int_ST0=512, + XED_IFORM_FISUB_ST0_MEMmem16int=513, + XED_IFORM_FISUB_ST0_MEMmem32int=514, + XED_IFORM_FISUBR_ST0_MEMmem16int=515, + XED_IFORM_FISUBR_ST0_MEMmem32int=516, + XED_IFORM_FLD_ST0_MEMm64real=517, + XED_IFORM_FLD_ST0_MEMmem32real=518, + XED_IFORM_FLD_ST0_MEMmem80real=519, + XED_IFORM_FLD_ST0_X87=520, + XED_IFORM_FLD1=521, + XED_IFORM_FLDCW_MEMmem16=522, + XED_IFORM_FLDENV_MEMmem14=523, + XED_IFORM_FLDENV_MEMmem28=524, + XED_IFORM_FLDL2E=525, + XED_IFORM_FLDL2T=526, + XED_IFORM_FLDLG2=527, + XED_IFORM_FLDLN2=528, + XED_IFORM_FLDPI=529, + XED_IFORM_FLDZ=530, + XED_IFORM_FMUL_ST0_MEMm64real=531, + XED_IFORM_FMUL_ST0_MEMmem32real=532, + XED_IFORM_FMUL_ST0_X87=533, + XED_IFORM_FMUL_X87_ST0=534, + XED_IFORM_FMULP_X87_ST0=535, + XED_IFORM_FNCLEX=536, + XED_IFORM_FNINIT=537, + XED_IFORM_FNOP=538, + XED_IFORM_FNSAVE_MEMmem108=539, + XED_IFORM_FNSAVE_MEMmem94=540, + XED_IFORM_FNSTCW_MEMmem16=541, + XED_IFORM_FNSTENV_MEMmem14=542, + XED_IFORM_FNSTENV_MEMmem28=543, + XED_IFORM_FNSTSW_AX=544, + XED_IFORM_FNSTSW_MEMmem16=545, + XED_IFORM_FPATAN=546, + XED_IFORM_FPREM=547, + XED_IFORM_FPREM1=548, + XED_IFORM_FPTAN=549, + XED_IFORM_FRNDINT=550, + XED_IFORM_FRSTOR_MEMmem108=551, + XED_IFORM_FRSTOR_MEMmem94=552, + XED_IFORM_FSCALE=553, + XED_IFORM_FSETPM287_NOP=554, + XED_IFORM_FSIN=555, + XED_IFORM_FSINCOS=556, + XED_IFORM_FSQRT=557, + XED_IFORM_FST_MEMm64real_ST0=558, + XED_IFORM_FST_MEMmem32real_ST0=559, + XED_IFORM_FST_X87_ST0=560, + XED_IFORM_FSTP_MEMm64real_ST0=561, + XED_IFORM_FSTP_MEMmem32real_ST0=562, + XED_IFORM_FSTP_MEMmem80real_ST0=563, + XED_IFORM_FSTP_X87_ST0=564, + XED_IFORM_FSTP_X87_ST0_DFD0=565, + XED_IFORM_FSTP_X87_ST0_DFD1=566, + XED_IFORM_FSTPNCE_X87_ST0=567, + XED_IFORM_FSUB_ST0_MEMm64real=568, + XED_IFORM_FSUB_ST0_MEMmem32real=569, + XED_IFORM_FSUB_ST0_X87=570, + XED_IFORM_FSUB_X87_ST0=571, + XED_IFORM_FSUBP_X87_ST0=572, + XED_IFORM_FSUBR_ST0_MEMm64real=573, + XED_IFORM_FSUBR_ST0_MEMmem32real=574, + XED_IFORM_FSUBR_ST0_X87=575, + XED_IFORM_FSUBR_X87_ST0=576, + XED_IFORM_FSUBRP_X87_ST0=577, + XED_IFORM_FTST=578, + XED_IFORM_FUCOM_ST0_X87=579, + XED_IFORM_FUCOMI_ST0_X87=580, + XED_IFORM_FUCOMIP_ST0_X87=581, + XED_IFORM_FUCOMP_ST0_X87=582, + XED_IFORM_FUCOMPP=583, + XED_IFORM_FWAIT=584, + XED_IFORM_FXAM=585, + XED_IFORM_FXCH_ST0_X87=586, + XED_IFORM_FXCH_ST0_X87_DDC1=587, + XED_IFORM_FXCH_ST0_X87_DFC1=588, + XED_IFORM_FXRSTOR_MEMmfpxenv=589, + XED_IFORM_FXRSTOR64_MEMmfpxenv=590, + XED_IFORM_FXSAVE_MEMmfpxenv=591, + XED_IFORM_FXSAVE64_MEMmfpxenv=592, + XED_IFORM_FXTRACT=593, + XED_IFORM_FYL2X=594, + XED_IFORM_FYL2XP1=595, + XED_IFORM_GETSEC=596, + XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8=597, + XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8=598, + XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8=599, + XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8=600, + XED_IFORM_GF2P8MULB_XMMu8_MEMu8=601, + XED_IFORM_GF2P8MULB_XMMu8_XMMu8=602, + XED_IFORM_HADDPD_XMMpd_MEMpd=603, + XED_IFORM_HADDPD_XMMpd_XMMpd=604, + XED_IFORM_HADDPS_XMMps_MEMps=605, + XED_IFORM_HADDPS_XMMps_XMMps=606, + XED_IFORM_HLT=607, + XED_IFORM_HRESET_IMM8=608, + XED_IFORM_HSUBPD_XMMpd_MEMpd=609, + XED_IFORM_HSUBPD_XMMpd_XMMpd=610, + XED_IFORM_HSUBPS_XMMps_MEMps=611, + XED_IFORM_HSUBPS_XMMps_XMMps=612, + XED_IFORM_IDIV_GPR8=613, + XED_IFORM_IDIV_GPRv=614, + XED_IFORM_IDIV_MEMb=615, + XED_IFORM_IDIV_MEMv=616, + XED_IFORM_IMUL_GPR8=617, + XED_IFORM_IMUL_GPRv=618, + XED_IFORM_IMUL_GPRv_GPRv=619, + XED_IFORM_IMUL_GPRv_GPRv_IMMb=620, + XED_IFORM_IMUL_GPRv_GPRv_IMMz=621, + XED_IFORM_IMUL_GPRv_MEMv=622, + XED_IFORM_IMUL_GPRv_MEMv_IMMb=623, + XED_IFORM_IMUL_GPRv_MEMv_IMMz=624, + XED_IFORM_IMUL_MEMb=625, + XED_IFORM_IMUL_MEMv=626, + XED_IFORM_IN_AL_DX=627, + XED_IFORM_IN_AL_IMMb=628, + XED_IFORM_IN_OeAX_DX=629, + XED_IFORM_IN_OeAX_IMMb=630, + XED_IFORM_INC_GPR8=631, + XED_IFORM_INC_GPRv_40=632, + XED_IFORM_INC_GPRv_FFr0=633, + XED_IFORM_INC_MEMb=634, + XED_IFORM_INC_MEMv=635, + XED_IFORM_INCSSPD_GPR32u8=636, + XED_IFORM_INCSSPQ_GPR64u8=637, + XED_IFORM_INC_LOCK_MEMb=638, + XED_IFORM_INC_LOCK_MEMv=639, + XED_IFORM_INSB=640, + XED_IFORM_INSD=641, + XED_IFORM_INSERTPS_XMMps_MEMd_IMMb=642, + XED_IFORM_INSERTPS_XMMps_XMMps_IMMb=643, + XED_IFORM_INSERTQ_XMMq_XMMdq=644, + XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb=645, + XED_IFORM_INSW=646, + XED_IFORM_INT_IMMb=647, + XED_IFORM_INT1=648, + XED_IFORM_INT3=649, + XED_IFORM_INTO=650, + XED_IFORM_INVD=651, + XED_IFORM_INVEPT_GPR32_MEMdq=652, + XED_IFORM_INVEPT_GPR64_MEMdq=653, + XED_IFORM_INVLPG_MEMb=654, + XED_IFORM_INVLPGA_ArAX_ECX=655, + XED_IFORM_INVLPGB_EAX_EDX_ECX=656, + XED_IFORM_INVLPGB_RAX_EDX_ECX=657, + XED_IFORM_INVPCID_GPR32_MEMdq=658, + XED_IFORM_INVPCID_GPR64_MEMdq=659, + XED_IFORM_INVVPID_GPR32_MEMdq=660, + XED_IFORM_INVVPID_GPR64_MEMdq=661, + XED_IFORM_IRET=662, + XED_IFORM_IRETD=663, + XED_IFORM_IRETQ=664, + XED_IFORM_JB_RELBRb=665, + XED_IFORM_JB_RELBRd=666, + XED_IFORM_JB_RELBRz=667, + XED_IFORM_JBE_RELBRb=668, + XED_IFORM_JBE_RELBRd=669, + XED_IFORM_JBE_RELBRz=670, + XED_IFORM_JCXZ_RELBRb=671, + XED_IFORM_JECXZ_RELBRb=672, + XED_IFORM_JL_RELBRb=673, + XED_IFORM_JL_RELBRd=674, + XED_IFORM_JL_RELBRz=675, + XED_IFORM_JLE_RELBRb=676, + XED_IFORM_JLE_RELBRd=677, + XED_IFORM_JLE_RELBRz=678, + XED_IFORM_JMP_GPRv=679, + XED_IFORM_JMP_MEMv=680, + XED_IFORM_JMP_RELBRb=681, + XED_IFORM_JMP_RELBRd=682, + XED_IFORM_JMP_RELBRz=683, + XED_IFORM_JMP_FAR_MEMp2=684, + XED_IFORM_JMP_FAR_PTRp_IMMw=685, + XED_IFORM_JNB_RELBRb=686, + XED_IFORM_JNB_RELBRd=687, + XED_IFORM_JNB_RELBRz=688, + XED_IFORM_JNBE_RELBRb=689, + XED_IFORM_JNBE_RELBRd=690, + XED_IFORM_JNBE_RELBRz=691, + XED_IFORM_JNL_RELBRb=692, + XED_IFORM_JNL_RELBRd=693, + XED_IFORM_JNL_RELBRz=694, + XED_IFORM_JNLE_RELBRb=695, + XED_IFORM_JNLE_RELBRd=696, + XED_IFORM_JNLE_RELBRz=697, + XED_IFORM_JNO_RELBRb=698, + XED_IFORM_JNO_RELBRd=699, + XED_IFORM_JNO_RELBRz=700, + XED_IFORM_JNP_RELBRb=701, + XED_IFORM_JNP_RELBRd=702, + XED_IFORM_JNP_RELBRz=703, + XED_IFORM_JNS_RELBRb=704, + XED_IFORM_JNS_RELBRd=705, + XED_IFORM_JNS_RELBRz=706, + XED_IFORM_JNZ_RELBRb=707, + XED_IFORM_JNZ_RELBRd=708, + XED_IFORM_JNZ_RELBRz=709, + XED_IFORM_JO_RELBRb=710, + XED_IFORM_JO_RELBRd=711, + XED_IFORM_JO_RELBRz=712, + XED_IFORM_JP_RELBRb=713, + XED_IFORM_JP_RELBRd=714, + XED_IFORM_JP_RELBRz=715, + XED_IFORM_JRCXZ_RELBRb=716, + XED_IFORM_JS_RELBRb=717, + XED_IFORM_JS_RELBRd=718, + XED_IFORM_JS_RELBRz=719, + XED_IFORM_JZ_RELBRb=720, + XED_IFORM_JZ_RELBRd=721, + XED_IFORM_JZ_RELBRz=722, + XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512=723, + XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512=724, + XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=725, + XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512=726, + XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512=727, + XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512=728, + XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512=729, + XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512=730, + XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512=731, + XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512=732, + XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=733, + XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512=734, + XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512=735, + XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512=736, + XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512=737, + XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512=738, + XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512=739, + XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512=740, + XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512=741, + XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512=742, + XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512=743, + XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512=744, + XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512=745, + XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512=746, + XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512=747, + XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512=748, + XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512=749, + XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512=750, + XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512=751, + XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512=752, + XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512=753, + XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512=754, + XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512=755, + XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512=756, + XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512=757, + XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512=758, + XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512=759, + XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512=760, + XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=761, + XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512=762, + XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512=763, + XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512=764, + XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512=765, + XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512=766, + XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512=767, + XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512=768, + XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512=769, + XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512=770, + XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512=771, + XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512=772, + XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512=773, + XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512=774, + XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512=775, + XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512=776, + XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512=777, + XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512=778, + XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512=779, + XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512=780, + XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512=781, + XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512=782, + XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512=783, + XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=784, + XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512=785, + XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512=786, + XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512=787, + XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512=788, + XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512=789, + XED_IFORM_LAHF=790, + XED_IFORM_LAR_GPRv_GPRv=791, + XED_IFORM_LAR_GPRv_MEMw=792, + XED_IFORM_LDDQU_XMMpd_MEMdq=793, + XED_IFORM_LDMXCSR_MEMd=794, + XED_IFORM_LDS_GPRz_MEMp=795, + XED_IFORM_LDTILECFG_MEM=796, + XED_IFORM_LEA_GPRv_AGEN=797, + XED_IFORM_LEAVE=798, + XED_IFORM_LES_GPRz_MEMp=799, + XED_IFORM_LFENCE=800, + XED_IFORM_LFS_GPRv_MEMp2=801, + XED_IFORM_LGDT_MEMs=802, + XED_IFORM_LGDT_MEMs64=803, + XED_IFORM_LGS_GPRv_MEMp2=804, + XED_IFORM_LIDT_MEMs=805, + XED_IFORM_LIDT_MEMs64=806, + XED_IFORM_LLDT_GPR16=807, + XED_IFORM_LLDT_MEMw=808, + XED_IFORM_LLWPCB_VGPRyy=809, + XED_IFORM_LMSW_GPR16=810, + XED_IFORM_LMSW_MEMw=811, + XED_IFORM_LOADIWKEY_XMMu8_XMMu8=812, + XED_IFORM_LODSB=813, + XED_IFORM_LODSD=814, + XED_IFORM_LODSQ=815, + XED_IFORM_LODSW=816, + XED_IFORM_LOOP_RELBRb=817, + XED_IFORM_LOOPE_RELBRb=818, + XED_IFORM_LOOPNE_RELBRb=819, + XED_IFORM_LSL_GPRv_GPRz=820, + XED_IFORM_LSL_GPRv_MEMw=821, + XED_IFORM_LSS_GPRv_MEMp2=822, + XED_IFORM_LTR_GPR16=823, + XED_IFORM_LTR_MEMw=824, + XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd=825, + XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd=826, + XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd=827, + XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd=828, + XED_IFORM_LZCNT_GPRv_GPRv=829, + XED_IFORM_LZCNT_GPRv_MEMv=830, + XED_IFORM_MASKMOVDQU_XMMdq_XMMdq=831, + XED_IFORM_MASKMOVQ_MMXq_MMXq=832, + XED_IFORM_MAXPD_XMMpd_MEMpd=833, + XED_IFORM_MAXPD_XMMpd_XMMpd=834, + XED_IFORM_MAXPS_XMMps_MEMps=835, + XED_IFORM_MAXPS_XMMps_XMMps=836, + XED_IFORM_MAXSD_XMMsd_MEMsd=837, + XED_IFORM_MAXSD_XMMsd_XMMsd=838, + XED_IFORM_MAXSS_XMMss_MEMss=839, + XED_IFORM_MAXSS_XMMss_XMMss=840, + XED_IFORM_MCOMMIT=841, + XED_IFORM_MFENCE=842, + XED_IFORM_MINPD_XMMpd_MEMpd=843, + XED_IFORM_MINPD_XMMpd_XMMpd=844, + XED_IFORM_MINPS_XMMps_MEMps=845, + XED_IFORM_MINPS_XMMps_XMMps=846, + XED_IFORM_MINSD_XMMsd_MEMsd=847, + XED_IFORM_MINSD_XMMsd_XMMsd=848, + XED_IFORM_MINSS_XMMss_MEMss=849, + XED_IFORM_MINSS_XMMss_XMMss=850, + XED_IFORM_MONITOR=851, + XED_IFORM_MONITORX=852, + XED_IFORM_MOV_AL_MEMb=853, + XED_IFORM_MOV_GPR8_GPR8_88=854, + XED_IFORM_MOV_GPR8_GPR8_8A=855, + XED_IFORM_MOV_GPR8_IMMb_B0=856, + XED_IFORM_MOV_GPR8_IMMb_C6r0=857, + XED_IFORM_MOV_GPR8_MEMb=858, + XED_IFORM_MOV_GPRv_GPRv_89=859, + XED_IFORM_MOV_GPRv_GPRv_8B=860, + XED_IFORM_MOV_GPRv_IMMv=861, + XED_IFORM_MOV_GPRv_IMMz=862, + XED_IFORM_MOV_GPRv_MEMv=863, + XED_IFORM_MOV_GPRv_SEG=864, + XED_IFORM_MOV_MEMb_AL=865, + XED_IFORM_MOV_MEMb_GPR8=866, + XED_IFORM_MOV_MEMb_IMMb=867, + XED_IFORM_MOV_MEMv_GPRv=868, + XED_IFORM_MOV_MEMv_IMMz=869, + XED_IFORM_MOV_MEMv_OrAX=870, + XED_IFORM_MOV_MEMw_SEG=871, + XED_IFORM_MOV_OrAX_MEMv=872, + XED_IFORM_MOV_SEG_GPR16=873, + XED_IFORM_MOV_SEG_MEMw=874, + XED_IFORM_MOVAPD_MEMpd_XMMpd=875, + XED_IFORM_MOVAPD_XMMpd_MEMpd=876, + XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28=877, + XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29=878, + XED_IFORM_MOVAPS_MEMps_XMMps=879, + XED_IFORM_MOVAPS_XMMps_MEMps=880, + XED_IFORM_MOVAPS_XMMps_XMMps_0F28=881, + XED_IFORM_MOVAPS_XMMps_XMMps_0F29=882, + XED_IFORM_MOVBE_GPRv_MEMv=883, + XED_IFORM_MOVBE_MEMv_GPRv=884, + XED_IFORM_MOVD_GPR32_MMXd=885, + XED_IFORM_MOVD_GPR32_XMMd=886, + XED_IFORM_MOVD_MEMd_MMXd=887, + XED_IFORM_MOVD_MEMd_XMMd=888, + XED_IFORM_MOVD_MMXq_GPR32=889, + XED_IFORM_MOVD_MMXq_MEMd=890, + XED_IFORM_MOVD_XMMdq_GPR32=891, + XED_IFORM_MOVD_XMMdq_MEMd=892, + XED_IFORM_MOVDDUP_XMMdq_MEMq=893, + XED_IFORM_MOVDDUP_XMMdq_XMMq=894, + XED_IFORM_MOVDIR64B_GPRa_MEM=895, + XED_IFORM_MOVDIRI_MEMu32_GPR32u32=896, + XED_IFORM_MOVDIRI_MEMu64_GPR64u64=897, + XED_IFORM_MOVDQ2Q_MMXq_XMMq=898, + XED_IFORM_MOVDQA_MEMdq_XMMdq=899, + XED_IFORM_MOVDQA_XMMdq_MEMdq=900, + XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F=901, + XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F=902, + XED_IFORM_MOVDQU_MEMdq_XMMdq=903, + XED_IFORM_MOVDQU_XMMdq_MEMdq=904, + XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F=905, + XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F=906, + XED_IFORM_MOVHLPS_XMMq_XMMq=907, + XED_IFORM_MOVHPD_MEMq_XMMsd=908, + XED_IFORM_MOVHPD_XMMsd_MEMq=909, + XED_IFORM_MOVHPS_MEMq_XMMps=910, + XED_IFORM_MOVHPS_XMMq_MEMq=911, + XED_IFORM_MOVLHPS_XMMq_XMMq=912, + XED_IFORM_MOVLPD_MEMq_XMMsd=913, + XED_IFORM_MOVLPD_XMMsd_MEMq=914, + XED_IFORM_MOVLPS_MEMq_XMMq=915, + XED_IFORM_MOVLPS_XMMq_MEMq=916, + XED_IFORM_MOVMSKPD_GPR32_XMMpd=917, + XED_IFORM_MOVMSKPS_GPR32_XMMps=918, + XED_IFORM_MOVNTDQ_MEMdq_XMMdq=919, + XED_IFORM_MOVNTDQA_XMMdq_MEMdq=920, + XED_IFORM_MOVNTI_MEMd_GPR32=921, + XED_IFORM_MOVNTI_MEMq_GPR64=922, + XED_IFORM_MOVNTPD_MEMdq_XMMpd=923, + XED_IFORM_MOVNTPS_MEMdq_XMMps=924, + XED_IFORM_MOVNTQ_MEMq_MMXq=925, + XED_IFORM_MOVNTSD_MEMq_XMMq=926, + XED_IFORM_MOVNTSS_MEMd_XMMd=927, + XED_IFORM_MOVQ_GPR64_MMXq=928, + XED_IFORM_MOVQ_GPR64_XMMq=929, + XED_IFORM_MOVQ_MEMq_MMXq_0F7E=930, + XED_IFORM_MOVQ_MEMq_MMXq_0F7F=931, + XED_IFORM_MOVQ_MEMq_XMMq_0F7E=932, + XED_IFORM_MOVQ_MEMq_XMMq_0FD6=933, + XED_IFORM_MOVQ_MMXq_GPR64=934, + XED_IFORM_MOVQ_MMXq_MEMq_0F6E=935, + XED_IFORM_MOVQ_MMXq_MEMq_0F6F=936, + XED_IFORM_MOVQ_MMXq_MMXq_0F6F=937, + XED_IFORM_MOVQ_MMXq_MMXq_0F7F=938, + XED_IFORM_MOVQ_XMMdq_GPR64=939, + XED_IFORM_MOVQ_XMMdq_MEMq_0F6E=940, + XED_IFORM_MOVQ_XMMdq_MEMq_0F7E=941, + XED_IFORM_MOVQ_XMMdq_XMMq_0F7E=942, + XED_IFORM_MOVQ_XMMdq_XMMq_0FD6=943, + XED_IFORM_MOVQ2DQ_XMMdq_MMXq=944, + XED_IFORM_MOVSB=945, + XED_IFORM_MOVSD=946, + XED_IFORM_MOVSD_XMM_MEMsd_XMMsd=947, + XED_IFORM_MOVSD_XMM_XMMdq_MEMsd=948, + XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10=949, + XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11=950, + XED_IFORM_MOVSHDUP_XMMps_MEMps=951, + XED_IFORM_MOVSHDUP_XMMps_XMMps=952, + XED_IFORM_MOVSLDUP_XMMps_MEMps=953, + XED_IFORM_MOVSLDUP_XMMps_XMMps=954, + XED_IFORM_MOVSQ=955, + XED_IFORM_MOVSS_MEMss_XMMss=956, + XED_IFORM_MOVSS_XMMdq_MEMss=957, + XED_IFORM_MOVSS_XMMss_XMMss_0F10=958, + XED_IFORM_MOVSS_XMMss_XMMss_0F11=959, + XED_IFORM_MOVSW=960, + XED_IFORM_MOVSX_GPRv_GPR16=961, + XED_IFORM_MOVSX_GPRv_GPR8=962, + XED_IFORM_MOVSX_GPRv_MEMb=963, + XED_IFORM_MOVSX_GPRv_MEMw=964, + XED_IFORM_MOVSXD_GPRv_GPRz=965, + XED_IFORM_MOVSXD_GPRv_MEMz=966, + XED_IFORM_MOVUPD_MEMpd_XMMpd=967, + XED_IFORM_MOVUPD_XMMpd_MEMpd=968, + XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10=969, + XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11=970, + XED_IFORM_MOVUPS_MEMps_XMMps=971, + XED_IFORM_MOVUPS_XMMps_MEMps=972, + XED_IFORM_MOVUPS_XMMps_XMMps_0F10=973, + XED_IFORM_MOVUPS_XMMps_XMMps_0F11=974, + XED_IFORM_MOVZX_GPRv_GPR16=975, + XED_IFORM_MOVZX_GPRv_GPR8=976, + XED_IFORM_MOVZX_GPRv_MEMb=977, + XED_IFORM_MOVZX_GPRv_MEMw=978, + XED_IFORM_MOV_CR_CR_GPR32=979, + XED_IFORM_MOV_CR_CR_GPR64=980, + XED_IFORM_MOV_CR_GPR32_CR=981, + XED_IFORM_MOV_CR_GPR64_CR=982, + XED_IFORM_MOV_DR_DR_GPR32=983, + XED_IFORM_MOV_DR_DR_GPR64=984, + XED_IFORM_MOV_DR_GPR32_DR=985, + XED_IFORM_MOV_DR_GPR64_DR=986, + XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb=987, + XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb=988, + XED_IFORM_MUL_GPR8=989, + XED_IFORM_MUL_GPRv=990, + XED_IFORM_MUL_MEMb=991, + XED_IFORM_MUL_MEMv=992, + XED_IFORM_MULPD_XMMpd_MEMpd=993, + XED_IFORM_MULPD_XMMpd_XMMpd=994, + XED_IFORM_MULPS_XMMps_MEMps=995, + XED_IFORM_MULPS_XMMps_XMMps=996, + XED_IFORM_MULSD_XMMsd_MEMsd=997, + XED_IFORM_MULSD_XMMsd_XMMsd=998, + XED_IFORM_MULSS_XMMss_MEMss=999, + XED_IFORM_MULSS_XMMss_XMMss=1000, + XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd=1001, + XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d=1002, + XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq=1003, + XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q=1004, + XED_IFORM_MWAIT=1005, + XED_IFORM_MWAITX=1006, + XED_IFORM_NEG_GPR8=1007, + XED_IFORM_NEG_GPRv=1008, + XED_IFORM_NEG_MEMb=1009, + XED_IFORM_NEG_MEMv=1010, + XED_IFORM_NEG_LOCK_MEMb=1011, + XED_IFORM_NEG_LOCK_MEMv=1012, + XED_IFORM_NOP_90=1013, + XED_IFORM_NOP_GPRv_0F18r0=1014, + XED_IFORM_NOP_GPRv_0F18r1=1015, + XED_IFORM_NOP_GPRv_0F18r2=1016, + XED_IFORM_NOP_GPRv_0F18r3=1017, + XED_IFORM_NOP_GPRv_0F18r4=1018, + XED_IFORM_NOP_GPRv_0F18r5=1019, + XED_IFORM_NOP_GPRv_0F18r6=1020, + XED_IFORM_NOP_GPRv_0F18r7=1021, + XED_IFORM_NOP_GPRv_GPRv_0F0D=1022, + XED_IFORM_NOP_GPRv_GPRv_0F19=1023, + XED_IFORM_NOP_GPRv_GPRv_0F1A=1024, + XED_IFORM_NOP_GPRv_GPRv_0F1B=1025, + XED_IFORM_NOP_GPRv_GPRv_0F1C=1026, + XED_IFORM_NOP_GPRv_GPRv_0F1D=1027, + XED_IFORM_NOP_GPRv_GPRv_0F1E=1028, + XED_IFORM_NOP_GPRv_GPRv_0F1F=1029, + XED_IFORM_NOP_GPRv_MEM_0F1B=1030, + XED_IFORM_NOP_GPRv_MEMv_0F1A=1031, + XED_IFORM_NOP_MEMv_0F18r4=1032, + XED_IFORM_NOP_MEMv_0F18r5=1033, + XED_IFORM_NOP_MEMv_0F18r6=1034, + XED_IFORM_NOP_MEMv_0F18r7=1035, + XED_IFORM_NOP_MEMv_GPRv_0F19=1036, + XED_IFORM_NOP_MEMv_GPRv_0F1C=1037, + XED_IFORM_NOP_MEMv_GPRv_0F1D=1038, + XED_IFORM_NOP_MEMv_GPRv_0F1E=1039, + XED_IFORM_NOP_MEMv_GPRv_0F1F=1040, + XED_IFORM_NOT_GPR8=1041, + XED_IFORM_NOT_GPRv=1042, + XED_IFORM_NOT_MEMb=1043, + XED_IFORM_NOT_MEMv=1044, + XED_IFORM_NOT_LOCK_MEMb=1045, + XED_IFORM_NOT_LOCK_MEMv=1046, + XED_IFORM_OR_AL_IMMb=1047, + XED_IFORM_OR_GPR8_GPR8_08=1048, + XED_IFORM_OR_GPR8_GPR8_0A=1049, + XED_IFORM_OR_GPR8_IMMb_80r1=1050, + XED_IFORM_OR_GPR8_IMMb_82r1=1051, + XED_IFORM_OR_GPR8_MEMb=1052, + XED_IFORM_OR_GPRv_GPRv_09=1053, + XED_IFORM_OR_GPRv_GPRv_0B=1054, + XED_IFORM_OR_GPRv_IMMb=1055, + XED_IFORM_OR_GPRv_IMMz=1056, + XED_IFORM_OR_GPRv_MEMv=1057, + XED_IFORM_OR_MEMb_GPR8=1058, + XED_IFORM_OR_MEMb_IMMb_80r1=1059, + XED_IFORM_OR_MEMb_IMMb_82r1=1060, + XED_IFORM_OR_MEMv_GPRv=1061, + XED_IFORM_OR_MEMv_IMMb=1062, + XED_IFORM_OR_MEMv_IMMz=1063, + XED_IFORM_OR_OrAX_IMMz=1064, + XED_IFORM_ORPD_XMMxuq_MEMxuq=1065, + XED_IFORM_ORPD_XMMxuq_XMMxuq=1066, + XED_IFORM_ORPS_XMMxud_MEMxud=1067, + XED_IFORM_ORPS_XMMxud_XMMxud=1068, + XED_IFORM_OR_LOCK_MEMb_GPR8=1069, + XED_IFORM_OR_LOCK_MEMb_IMMb_80r1=1070, + XED_IFORM_OR_LOCK_MEMb_IMMb_82r1=1071, + XED_IFORM_OR_LOCK_MEMv_GPRv=1072, + XED_IFORM_OR_LOCK_MEMv_IMMb=1073, + XED_IFORM_OR_LOCK_MEMv_IMMz=1074, + XED_IFORM_OUT_DX_AL=1075, + XED_IFORM_OUT_DX_OeAX=1076, + XED_IFORM_OUT_IMMb_AL=1077, + XED_IFORM_OUT_IMMb_OeAX=1078, + XED_IFORM_OUTSB=1079, + XED_IFORM_OUTSD=1080, + XED_IFORM_OUTSW=1081, + XED_IFORM_PABSB_MMXq_MEMq=1082, + XED_IFORM_PABSB_MMXq_MMXq=1083, + XED_IFORM_PABSB_XMMdq_MEMdq=1084, + XED_IFORM_PABSB_XMMdq_XMMdq=1085, + XED_IFORM_PABSD_MMXq_MEMq=1086, + XED_IFORM_PABSD_MMXq_MMXq=1087, + XED_IFORM_PABSD_XMMdq_MEMdq=1088, + XED_IFORM_PABSD_XMMdq_XMMdq=1089, + XED_IFORM_PABSW_MMXq_MEMq=1090, + XED_IFORM_PABSW_MMXq_MMXq=1091, + XED_IFORM_PABSW_XMMdq_MEMdq=1092, + XED_IFORM_PABSW_XMMdq_XMMdq=1093, + XED_IFORM_PACKSSDW_MMXq_MEMq=1094, + XED_IFORM_PACKSSDW_MMXq_MMXq=1095, + XED_IFORM_PACKSSDW_XMMdq_MEMdq=1096, + XED_IFORM_PACKSSDW_XMMdq_XMMdq=1097, + XED_IFORM_PACKSSWB_MMXq_MEMq=1098, + XED_IFORM_PACKSSWB_MMXq_MMXq=1099, + XED_IFORM_PACKSSWB_XMMdq_MEMdq=1100, + XED_IFORM_PACKSSWB_XMMdq_XMMdq=1101, + XED_IFORM_PACKUSDW_XMMdq_MEMdq=1102, + XED_IFORM_PACKUSDW_XMMdq_XMMdq=1103, + XED_IFORM_PACKUSWB_MMXq_MEMq=1104, + XED_IFORM_PACKUSWB_MMXq_MMXq=1105, + XED_IFORM_PACKUSWB_XMMdq_MEMdq=1106, + XED_IFORM_PACKUSWB_XMMdq_XMMdq=1107, + XED_IFORM_PADDB_MMXq_MEMq=1108, + XED_IFORM_PADDB_MMXq_MMXq=1109, + XED_IFORM_PADDB_XMMdq_MEMdq=1110, + XED_IFORM_PADDB_XMMdq_XMMdq=1111, + XED_IFORM_PADDD_MMXq_MEMq=1112, + XED_IFORM_PADDD_MMXq_MMXq=1113, + XED_IFORM_PADDD_XMMdq_MEMdq=1114, + XED_IFORM_PADDD_XMMdq_XMMdq=1115, + XED_IFORM_PADDQ_MMXq_MEMq=1116, + XED_IFORM_PADDQ_MMXq_MMXq=1117, + XED_IFORM_PADDQ_XMMdq_MEMdq=1118, + XED_IFORM_PADDQ_XMMdq_XMMdq=1119, + XED_IFORM_PADDSB_MMXq_MEMq=1120, + XED_IFORM_PADDSB_MMXq_MMXq=1121, + XED_IFORM_PADDSB_XMMdq_MEMdq=1122, + XED_IFORM_PADDSB_XMMdq_XMMdq=1123, + XED_IFORM_PADDSW_MMXq_MEMq=1124, + XED_IFORM_PADDSW_MMXq_MMXq=1125, + XED_IFORM_PADDSW_XMMdq_MEMdq=1126, + XED_IFORM_PADDSW_XMMdq_XMMdq=1127, + XED_IFORM_PADDUSB_MMXq_MEMq=1128, + XED_IFORM_PADDUSB_MMXq_MMXq=1129, + XED_IFORM_PADDUSB_XMMdq_MEMdq=1130, + XED_IFORM_PADDUSB_XMMdq_XMMdq=1131, + XED_IFORM_PADDUSW_MMXq_MEMq=1132, + XED_IFORM_PADDUSW_MMXq_MMXq=1133, + XED_IFORM_PADDUSW_XMMdq_MEMdq=1134, + XED_IFORM_PADDUSW_XMMdq_XMMdq=1135, + XED_IFORM_PADDW_MMXq_MEMq=1136, + XED_IFORM_PADDW_MMXq_MMXq=1137, + XED_IFORM_PADDW_XMMdq_MEMdq=1138, + XED_IFORM_PADDW_XMMdq_XMMdq=1139, + XED_IFORM_PALIGNR_MMXq_MEMq_IMMb=1140, + XED_IFORM_PALIGNR_MMXq_MMXq_IMMb=1141, + XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb=1142, + XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb=1143, + XED_IFORM_PAND_MMXq_MEMq=1144, + XED_IFORM_PAND_MMXq_MMXq=1145, + XED_IFORM_PAND_XMMdq_MEMdq=1146, + XED_IFORM_PAND_XMMdq_XMMdq=1147, + XED_IFORM_PANDN_MMXq_MEMq=1148, + XED_IFORM_PANDN_MMXq_MMXq=1149, + XED_IFORM_PANDN_XMMdq_MEMdq=1150, + XED_IFORM_PANDN_XMMdq_XMMdq=1151, + XED_IFORM_PAUSE=1152, + XED_IFORM_PAVGB_MMXq_MEMq=1153, + XED_IFORM_PAVGB_MMXq_MMXq=1154, + XED_IFORM_PAVGB_XMMdq_MEMdq=1155, + XED_IFORM_PAVGB_XMMdq_XMMdq=1156, + XED_IFORM_PAVGUSB_MMXq_MEMq=1157, + XED_IFORM_PAVGUSB_MMXq_MMXq=1158, + XED_IFORM_PAVGW_MMXq_MEMq=1159, + XED_IFORM_PAVGW_MMXq_MMXq=1160, + XED_IFORM_PAVGW_XMMdq_MEMdq=1161, + XED_IFORM_PAVGW_XMMdq_XMMdq=1162, + XED_IFORM_PBLENDVB_XMMdq_MEMdq=1163, + XED_IFORM_PBLENDVB_XMMdq_XMMdq=1164, + XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb=1165, + XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb=1166, + XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb=1167, + XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb=1168, + XED_IFORM_PCMPEQB_MMXq_MEMq=1169, + XED_IFORM_PCMPEQB_MMXq_MMXq=1170, + XED_IFORM_PCMPEQB_XMMdq_MEMdq=1171, + XED_IFORM_PCMPEQB_XMMdq_XMMdq=1172, + XED_IFORM_PCMPEQD_MMXq_MEMq=1173, + XED_IFORM_PCMPEQD_MMXq_MMXq=1174, + XED_IFORM_PCMPEQD_XMMdq_MEMdq=1175, + XED_IFORM_PCMPEQD_XMMdq_XMMdq=1176, + XED_IFORM_PCMPEQQ_XMMdq_MEMdq=1177, + XED_IFORM_PCMPEQQ_XMMdq_XMMdq=1178, + XED_IFORM_PCMPEQW_MMXq_MEMq=1179, + XED_IFORM_PCMPEQW_MMXq_MMXq=1180, + XED_IFORM_PCMPEQW_XMMdq_MEMdq=1181, + XED_IFORM_PCMPEQW_XMMdq_XMMdq=1182, + XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb=1183, + XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb=1184, + XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb=1185, + XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb=1186, + XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb=1187, + XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb=1188, + XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb=1189, + XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb=1190, + XED_IFORM_PCMPGTB_MMXq_MEMq=1191, + XED_IFORM_PCMPGTB_MMXq_MMXq=1192, + XED_IFORM_PCMPGTB_XMMdq_MEMdq=1193, + XED_IFORM_PCMPGTB_XMMdq_XMMdq=1194, + XED_IFORM_PCMPGTD_MMXq_MEMq=1195, + XED_IFORM_PCMPGTD_MMXq_MMXq=1196, + XED_IFORM_PCMPGTD_XMMdq_MEMdq=1197, + XED_IFORM_PCMPGTD_XMMdq_XMMdq=1198, + XED_IFORM_PCMPGTQ_XMMdq_MEMdq=1199, + XED_IFORM_PCMPGTQ_XMMdq_XMMdq=1200, + XED_IFORM_PCMPGTW_MMXq_MEMq=1201, + XED_IFORM_PCMPGTW_MMXq_MMXq=1202, + XED_IFORM_PCMPGTW_XMMdq_MEMdq=1203, + XED_IFORM_PCMPGTW_XMMdq_XMMdq=1204, + XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb=1205, + XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb=1206, + XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb=1207, + XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb=1208, + XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb=1209, + XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb=1210, + XED_IFORM_PCONFIG=1211, + XED_IFORM_PCONFIG64=1212, + XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd=1213, + XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d=1214, + XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq=1215, + XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q=1216, + XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd=1217, + XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d=1218, + XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq=1219, + XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q=1220, + XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb=1221, + XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb=1222, + XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb=1223, + XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb=1224, + XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb=1225, + XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb=1226, + XED_IFORM_PEXTRW_GPR32_MMXq_IMMb=1227, + XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb=1228, + XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb=1229, + XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb=1230, + XED_IFORM_PF2ID_MMXq_MEMq=1231, + XED_IFORM_PF2ID_MMXq_MMXq=1232, + XED_IFORM_PF2IW_MMXq_MEMq=1233, + XED_IFORM_PF2IW_MMXq_MMXq=1234, + XED_IFORM_PFACC_MMXq_MEMq=1235, + XED_IFORM_PFACC_MMXq_MMXq=1236, + XED_IFORM_PFADD_MMXq_MEMq=1237, + XED_IFORM_PFADD_MMXq_MMXq=1238, + XED_IFORM_PFCMPEQ_MMXq_MEMq=1239, + XED_IFORM_PFCMPEQ_MMXq_MMXq=1240, + XED_IFORM_PFCMPGE_MMXq_MEMq=1241, + XED_IFORM_PFCMPGE_MMXq_MMXq=1242, + XED_IFORM_PFCMPGT_MMXq_MEMq=1243, + XED_IFORM_PFCMPGT_MMXq_MMXq=1244, + XED_IFORM_PFMAX_MMXq_MEMq=1245, + XED_IFORM_PFMAX_MMXq_MMXq=1246, + XED_IFORM_PFMIN_MMXq_MEMq=1247, + XED_IFORM_PFMIN_MMXq_MMXq=1248, + XED_IFORM_PFMUL_MMXq_MEMq=1249, + XED_IFORM_PFMUL_MMXq_MMXq=1250, + XED_IFORM_PFNACC_MMXq_MEMq=1251, + XED_IFORM_PFNACC_MMXq_MMXq=1252, + XED_IFORM_PFPNACC_MMXq_MEMq=1253, + XED_IFORM_PFPNACC_MMXq_MMXq=1254, + XED_IFORM_PFRCP_MMXq_MEMq=1255, + XED_IFORM_PFRCP_MMXq_MMXq=1256, + XED_IFORM_PFRCPIT1_MMXq_MEMq=1257, + XED_IFORM_PFRCPIT1_MMXq_MMXq=1258, + XED_IFORM_PFRCPIT2_MMXq_MEMq=1259, + XED_IFORM_PFRCPIT2_MMXq_MMXq=1260, + XED_IFORM_PFRSQIT1_MMXq_MEMq=1261, + XED_IFORM_PFRSQIT1_MMXq_MMXq=1262, + XED_IFORM_PFRSQRT_MMXq_MEMq=1263, + XED_IFORM_PFRSQRT_MMXq_MMXq=1264, + XED_IFORM_PFSUB_MMXq_MEMq=1265, + XED_IFORM_PFSUB_MMXq_MMXq=1266, + XED_IFORM_PFSUBR_MMXq_MEMq=1267, + XED_IFORM_PFSUBR_MMXq_MMXq=1268, + XED_IFORM_PHADDD_MMXq_MEMq=1269, + XED_IFORM_PHADDD_MMXq_MMXq=1270, + XED_IFORM_PHADDD_XMMdq_MEMdq=1271, + XED_IFORM_PHADDD_XMMdq_XMMdq=1272, + XED_IFORM_PHADDSW_MMXq_MEMq=1273, + XED_IFORM_PHADDSW_MMXq_MMXq=1274, + XED_IFORM_PHADDSW_XMMdq_MEMdq=1275, + XED_IFORM_PHADDSW_XMMdq_XMMdq=1276, + XED_IFORM_PHADDW_MMXq_MEMq=1277, + XED_IFORM_PHADDW_MMXq_MMXq=1278, + XED_IFORM_PHADDW_XMMdq_MEMdq=1279, + XED_IFORM_PHADDW_XMMdq_XMMdq=1280, + XED_IFORM_PHMINPOSUW_XMMdq_MEMdq=1281, + XED_IFORM_PHMINPOSUW_XMMdq_XMMdq=1282, + XED_IFORM_PHSUBD_MMXq_MEMq=1283, + XED_IFORM_PHSUBD_MMXq_MMXq=1284, + XED_IFORM_PHSUBD_XMMdq_MEMdq=1285, + XED_IFORM_PHSUBD_XMMdq_XMMdq=1286, + XED_IFORM_PHSUBSW_MMXq_MEMq=1287, + XED_IFORM_PHSUBSW_MMXq_MMXq=1288, + XED_IFORM_PHSUBSW_XMMdq_MEMdq=1289, + XED_IFORM_PHSUBSW_XMMdq_XMMdq=1290, + XED_IFORM_PHSUBW_MMXq_MEMq=1291, + XED_IFORM_PHSUBW_MMXq_MMXq=1292, + XED_IFORM_PHSUBW_XMMdq_MEMdq=1293, + XED_IFORM_PHSUBW_XMMdq_XMMdq=1294, + XED_IFORM_PI2FD_MMXq_MEMq=1295, + XED_IFORM_PI2FD_MMXq_MMXq=1296, + XED_IFORM_PI2FW_MMXq_MEMq=1297, + XED_IFORM_PI2FW_MMXq_MMXq=1298, + XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb=1299, + XED_IFORM_PINSRB_XMMdq_MEMb_IMMb=1300, + XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb=1301, + XED_IFORM_PINSRD_XMMdq_MEMd_IMMb=1302, + XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb=1303, + XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb=1304, + XED_IFORM_PINSRW_MMXq_GPR32_IMMb=1305, + XED_IFORM_PINSRW_MMXq_MEMw_IMMb=1306, + XED_IFORM_PINSRW_XMMdq_GPR32_IMMb=1307, + XED_IFORM_PINSRW_XMMdq_MEMw_IMMb=1308, + XED_IFORM_PMADDUBSW_MMXq_MEMq=1309, + XED_IFORM_PMADDUBSW_MMXq_MMXq=1310, + XED_IFORM_PMADDUBSW_XMMdq_MEMdq=1311, + XED_IFORM_PMADDUBSW_XMMdq_XMMdq=1312, + XED_IFORM_PMADDWD_MMXq_MEMq=1313, + XED_IFORM_PMADDWD_MMXq_MMXq=1314, + XED_IFORM_PMADDWD_XMMdq_MEMdq=1315, + XED_IFORM_PMADDWD_XMMdq_XMMdq=1316, + XED_IFORM_PMAXSB_XMMdq_MEMdq=1317, + XED_IFORM_PMAXSB_XMMdq_XMMdq=1318, + XED_IFORM_PMAXSD_XMMdq_MEMdq=1319, + XED_IFORM_PMAXSD_XMMdq_XMMdq=1320, + XED_IFORM_PMAXSW_MMXq_MEMq=1321, + XED_IFORM_PMAXSW_MMXq_MMXq=1322, + XED_IFORM_PMAXSW_XMMdq_MEMdq=1323, + XED_IFORM_PMAXSW_XMMdq_XMMdq=1324, + XED_IFORM_PMAXUB_MMXq_MEMq=1325, + XED_IFORM_PMAXUB_MMXq_MMXq=1326, + XED_IFORM_PMAXUB_XMMdq_MEMdq=1327, + XED_IFORM_PMAXUB_XMMdq_XMMdq=1328, + XED_IFORM_PMAXUD_XMMdq_MEMdq=1329, + XED_IFORM_PMAXUD_XMMdq_XMMdq=1330, + XED_IFORM_PMAXUW_XMMdq_MEMdq=1331, + XED_IFORM_PMAXUW_XMMdq_XMMdq=1332, + XED_IFORM_PMINSB_XMMdq_MEMdq=1333, + XED_IFORM_PMINSB_XMMdq_XMMdq=1334, + XED_IFORM_PMINSD_XMMdq_MEMdq=1335, + XED_IFORM_PMINSD_XMMdq_XMMdq=1336, + XED_IFORM_PMINSW_MMXq_MEMq=1337, + XED_IFORM_PMINSW_MMXq_MMXq=1338, + XED_IFORM_PMINSW_XMMdq_MEMdq=1339, + XED_IFORM_PMINSW_XMMdq_XMMdq=1340, + XED_IFORM_PMINUB_MMXq_MEMq=1341, + XED_IFORM_PMINUB_MMXq_MMXq=1342, + XED_IFORM_PMINUB_XMMdq_MEMdq=1343, + XED_IFORM_PMINUB_XMMdq_XMMdq=1344, + XED_IFORM_PMINUD_XMMdq_MEMdq=1345, + XED_IFORM_PMINUD_XMMdq_XMMdq=1346, + XED_IFORM_PMINUW_XMMdq_MEMdq=1347, + XED_IFORM_PMINUW_XMMdq_XMMdq=1348, + XED_IFORM_PMOVMSKB_GPR32_MMXq=1349, + XED_IFORM_PMOVMSKB_GPR32_XMMdq=1350, + XED_IFORM_PMOVSXBD_XMMdq_MEMd=1351, + XED_IFORM_PMOVSXBD_XMMdq_XMMd=1352, + XED_IFORM_PMOVSXBQ_XMMdq_MEMw=1353, + XED_IFORM_PMOVSXBQ_XMMdq_XMMw=1354, + XED_IFORM_PMOVSXBW_XMMdq_MEMq=1355, + XED_IFORM_PMOVSXBW_XMMdq_XMMq=1356, + XED_IFORM_PMOVSXDQ_XMMdq_MEMq=1357, + XED_IFORM_PMOVSXDQ_XMMdq_XMMq=1358, + XED_IFORM_PMOVSXWD_XMMdq_MEMq=1359, + XED_IFORM_PMOVSXWD_XMMdq_XMMq=1360, + XED_IFORM_PMOVSXWQ_XMMdq_MEMd=1361, + XED_IFORM_PMOVSXWQ_XMMdq_XMMd=1362, + XED_IFORM_PMOVZXBD_XMMdq_MEMd=1363, + XED_IFORM_PMOVZXBD_XMMdq_XMMd=1364, + XED_IFORM_PMOVZXBQ_XMMdq_MEMw=1365, + XED_IFORM_PMOVZXBQ_XMMdq_XMMw=1366, + XED_IFORM_PMOVZXBW_XMMdq_MEMq=1367, + XED_IFORM_PMOVZXBW_XMMdq_XMMq=1368, + XED_IFORM_PMOVZXDQ_XMMdq_MEMq=1369, + XED_IFORM_PMOVZXDQ_XMMdq_XMMq=1370, + XED_IFORM_PMOVZXWD_XMMdq_MEMq=1371, + XED_IFORM_PMOVZXWD_XMMdq_XMMq=1372, + XED_IFORM_PMOVZXWQ_XMMdq_MEMd=1373, + XED_IFORM_PMOVZXWQ_XMMdq_XMMd=1374, + XED_IFORM_PMULDQ_XMMdq_MEMdq=1375, + XED_IFORM_PMULDQ_XMMdq_XMMdq=1376, + XED_IFORM_PMULHRSW_MMXq_MEMq=1377, + XED_IFORM_PMULHRSW_MMXq_MMXq=1378, + XED_IFORM_PMULHRSW_XMMdq_MEMdq=1379, + XED_IFORM_PMULHRSW_XMMdq_XMMdq=1380, + XED_IFORM_PMULHRW_MMXq_MEMq=1381, + XED_IFORM_PMULHRW_MMXq_MMXq=1382, + XED_IFORM_PMULHUW_MMXq_MEMq=1383, + XED_IFORM_PMULHUW_MMXq_MMXq=1384, + XED_IFORM_PMULHUW_XMMdq_MEMdq=1385, + XED_IFORM_PMULHUW_XMMdq_XMMdq=1386, + XED_IFORM_PMULHW_MMXq_MEMq=1387, + XED_IFORM_PMULHW_MMXq_MMXq=1388, + XED_IFORM_PMULHW_XMMdq_MEMdq=1389, + XED_IFORM_PMULHW_XMMdq_XMMdq=1390, + XED_IFORM_PMULLD_XMMdq_MEMdq=1391, + XED_IFORM_PMULLD_XMMdq_XMMdq=1392, + XED_IFORM_PMULLW_MMXq_MEMq=1393, + XED_IFORM_PMULLW_MMXq_MMXq=1394, + XED_IFORM_PMULLW_XMMdq_MEMdq=1395, + XED_IFORM_PMULLW_XMMdq_XMMdq=1396, + XED_IFORM_PMULUDQ_MMXq_MEMq=1397, + XED_IFORM_PMULUDQ_MMXq_MMXq=1398, + XED_IFORM_PMULUDQ_XMMdq_MEMdq=1399, + XED_IFORM_PMULUDQ_XMMdq_XMMdq=1400, + XED_IFORM_POP_DS=1401, + XED_IFORM_POP_ES=1402, + XED_IFORM_POP_FS=1403, + XED_IFORM_POP_GPRv_58=1404, + XED_IFORM_POP_GPRv_8F=1405, + XED_IFORM_POP_GS=1406, + XED_IFORM_POP_MEMv=1407, + XED_IFORM_POP_SS=1408, + XED_IFORM_POPA=1409, + XED_IFORM_POPAD=1410, + XED_IFORM_POPCNT_GPRv_GPRv=1411, + XED_IFORM_POPCNT_GPRv_MEMv=1412, + XED_IFORM_POPF=1413, + XED_IFORM_POPFD=1414, + XED_IFORM_POPFQ=1415, + XED_IFORM_POR_MMXq_MEMq=1416, + XED_IFORM_POR_MMXq_MMXq=1417, + XED_IFORM_POR_XMMdq_MEMdq=1418, + XED_IFORM_POR_XMMdq_XMMdq=1419, + XED_IFORM_PREFETCHNTA_MEMmprefetch=1420, + XED_IFORM_PREFETCHT0_MEMmprefetch=1421, + XED_IFORM_PREFETCHT1_MEMmprefetch=1422, + XED_IFORM_PREFETCHT2_MEMmprefetch=1423, + XED_IFORM_PREFETCHW_0F0Dr1=1424, + XED_IFORM_PREFETCHW_0F0Dr3=1425, + XED_IFORM_PREFETCHWT1_MEMu8=1426, + XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch=1427, + XED_IFORM_PREFETCH_RESERVED_0F0Dr4=1428, + XED_IFORM_PREFETCH_RESERVED_0F0Dr5=1429, + XED_IFORM_PREFETCH_RESERVED_0F0Dr6=1430, + XED_IFORM_PREFETCH_RESERVED_0F0Dr7=1431, + XED_IFORM_PSADBW_MMXq_MEMq=1432, + XED_IFORM_PSADBW_MMXq_MMXq=1433, + XED_IFORM_PSADBW_XMMdq_MEMdq=1434, + XED_IFORM_PSADBW_XMMdq_XMMdq=1435, + XED_IFORM_PSHUFB_MMXq_MEMq=1436, + XED_IFORM_PSHUFB_MMXq_MMXq=1437, + XED_IFORM_PSHUFB_XMMdq_MEMdq=1438, + XED_IFORM_PSHUFB_XMMdq_XMMdq=1439, + XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb=1440, + XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb=1441, + XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb=1442, + XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb=1443, + XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb=1444, + XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb=1445, + XED_IFORM_PSHUFW_MMXq_MEMq_IMMb=1446, + XED_IFORM_PSHUFW_MMXq_MMXq_IMMb=1447, + XED_IFORM_PSIGNB_MMXq_MEMq=1448, + XED_IFORM_PSIGNB_MMXq_MMXq=1449, + XED_IFORM_PSIGNB_XMMdq_MEMdq=1450, + XED_IFORM_PSIGNB_XMMdq_XMMdq=1451, + XED_IFORM_PSIGND_MMXq_MEMq=1452, + XED_IFORM_PSIGND_MMXq_MMXq=1453, + XED_IFORM_PSIGND_XMMdq_MEMdq=1454, + XED_IFORM_PSIGND_XMMdq_XMMdq=1455, + XED_IFORM_PSIGNW_MMXq_MEMq=1456, + XED_IFORM_PSIGNW_MMXq_MMXq=1457, + XED_IFORM_PSIGNW_XMMdq_MEMdq=1458, + XED_IFORM_PSIGNW_XMMdq_XMMdq=1459, + XED_IFORM_PSLLD_MMXq_IMMb=1460, + XED_IFORM_PSLLD_MMXq_MEMq=1461, + XED_IFORM_PSLLD_MMXq_MMXq=1462, + XED_IFORM_PSLLD_XMMdq_IMMb=1463, + XED_IFORM_PSLLD_XMMdq_MEMdq=1464, + XED_IFORM_PSLLD_XMMdq_XMMdq=1465, + XED_IFORM_PSLLDQ_XMMdq_IMMb=1466, + XED_IFORM_PSLLQ_MMXq_IMMb=1467, + XED_IFORM_PSLLQ_MMXq_MEMq=1468, + XED_IFORM_PSLLQ_MMXq_MMXq=1469, + XED_IFORM_PSLLQ_XMMdq_IMMb=1470, + XED_IFORM_PSLLQ_XMMdq_MEMdq=1471, + XED_IFORM_PSLLQ_XMMdq_XMMdq=1472, + XED_IFORM_PSLLW_MMXq_IMMb=1473, + XED_IFORM_PSLLW_MMXq_MEMq=1474, + XED_IFORM_PSLLW_MMXq_MMXq=1475, + XED_IFORM_PSLLW_XMMdq_IMMb=1476, + XED_IFORM_PSLLW_XMMdq_MEMdq=1477, + XED_IFORM_PSLLW_XMMdq_XMMdq=1478, + XED_IFORM_PSMASH_RAX=1479, + XED_IFORM_PSRAD_MMXq_IMMb=1480, + XED_IFORM_PSRAD_MMXq_MEMq=1481, + XED_IFORM_PSRAD_MMXq_MMXq=1482, + XED_IFORM_PSRAD_XMMdq_IMMb=1483, + XED_IFORM_PSRAD_XMMdq_MEMdq=1484, + XED_IFORM_PSRAD_XMMdq_XMMdq=1485, + XED_IFORM_PSRAW_MMXq_IMMb=1486, + XED_IFORM_PSRAW_MMXq_MEMq=1487, + XED_IFORM_PSRAW_MMXq_MMXq=1488, + XED_IFORM_PSRAW_XMMdq_IMMb=1489, + XED_IFORM_PSRAW_XMMdq_MEMdq=1490, + XED_IFORM_PSRAW_XMMdq_XMMdq=1491, + XED_IFORM_PSRLD_MMXq_IMMb=1492, + XED_IFORM_PSRLD_MMXq_MEMq=1493, + XED_IFORM_PSRLD_MMXq_MMXq=1494, + XED_IFORM_PSRLD_XMMdq_IMMb=1495, + XED_IFORM_PSRLD_XMMdq_MEMdq=1496, + XED_IFORM_PSRLD_XMMdq_XMMdq=1497, + XED_IFORM_PSRLDQ_XMMdq_IMMb=1498, + XED_IFORM_PSRLQ_MMXq_IMMb=1499, + XED_IFORM_PSRLQ_MMXq_MEMq=1500, + XED_IFORM_PSRLQ_MMXq_MMXq=1501, + XED_IFORM_PSRLQ_XMMdq_IMMb=1502, + XED_IFORM_PSRLQ_XMMdq_MEMdq=1503, + XED_IFORM_PSRLQ_XMMdq_XMMdq=1504, + XED_IFORM_PSRLW_MMXq_IMMb=1505, + XED_IFORM_PSRLW_MMXq_MEMq=1506, + XED_IFORM_PSRLW_MMXq_MMXq=1507, + XED_IFORM_PSRLW_XMMdq_IMMb=1508, + XED_IFORM_PSRLW_XMMdq_MEMdq=1509, + XED_IFORM_PSRLW_XMMdq_XMMdq=1510, + XED_IFORM_PSUBB_MMXq_MEMq=1511, + XED_IFORM_PSUBB_MMXq_MMXq=1512, + XED_IFORM_PSUBB_XMMdq_MEMdq=1513, + XED_IFORM_PSUBB_XMMdq_XMMdq=1514, + XED_IFORM_PSUBD_MMXq_MEMq=1515, + XED_IFORM_PSUBD_MMXq_MMXq=1516, + XED_IFORM_PSUBD_XMMdq_MEMdq=1517, + XED_IFORM_PSUBD_XMMdq_XMMdq=1518, + XED_IFORM_PSUBQ_MMXq_MEMq=1519, + XED_IFORM_PSUBQ_MMXq_MMXq=1520, + XED_IFORM_PSUBQ_XMMdq_MEMdq=1521, + XED_IFORM_PSUBQ_XMMdq_XMMdq=1522, + XED_IFORM_PSUBSB_MMXq_MEMq=1523, + XED_IFORM_PSUBSB_MMXq_MMXq=1524, + XED_IFORM_PSUBSB_XMMdq_MEMdq=1525, + XED_IFORM_PSUBSB_XMMdq_XMMdq=1526, + XED_IFORM_PSUBSW_MMXq_MEMq=1527, + XED_IFORM_PSUBSW_MMXq_MMXq=1528, + XED_IFORM_PSUBSW_XMMdq_MEMdq=1529, + XED_IFORM_PSUBSW_XMMdq_XMMdq=1530, + XED_IFORM_PSUBUSB_MMXq_MEMq=1531, + XED_IFORM_PSUBUSB_MMXq_MMXq=1532, + XED_IFORM_PSUBUSB_XMMdq_MEMdq=1533, + XED_IFORM_PSUBUSB_XMMdq_XMMdq=1534, + XED_IFORM_PSUBUSW_MMXq_MEMq=1535, + XED_IFORM_PSUBUSW_MMXq_MMXq=1536, + XED_IFORM_PSUBUSW_XMMdq_MEMdq=1537, + XED_IFORM_PSUBUSW_XMMdq_XMMdq=1538, + XED_IFORM_PSUBW_MMXq_MEMq=1539, + XED_IFORM_PSUBW_MMXq_MMXq=1540, + XED_IFORM_PSUBW_XMMdq_MEMdq=1541, + XED_IFORM_PSUBW_XMMdq_XMMdq=1542, + XED_IFORM_PSWAPD_MMXq_MEMq=1543, + XED_IFORM_PSWAPD_MMXq_MMXq=1544, + XED_IFORM_PTEST_XMMdq_MEMdq=1545, + XED_IFORM_PTEST_XMMdq_XMMdq=1546, + XED_IFORM_PTWRITE_GPRy=1547, + XED_IFORM_PTWRITE_MEMy=1548, + XED_IFORM_PUNPCKHBW_MMXq_MEMq=1549, + XED_IFORM_PUNPCKHBW_MMXq_MMXd=1550, + XED_IFORM_PUNPCKHBW_XMMdq_MEMdq=1551, + XED_IFORM_PUNPCKHBW_XMMdq_XMMq=1552, + XED_IFORM_PUNPCKHDQ_MMXq_MEMq=1553, + XED_IFORM_PUNPCKHDQ_MMXq_MMXd=1554, + XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq=1555, + XED_IFORM_PUNPCKHDQ_XMMdq_XMMq=1556, + XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq=1557, + XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq=1558, + XED_IFORM_PUNPCKHWD_MMXq_MEMq=1559, + XED_IFORM_PUNPCKHWD_MMXq_MMXd=1560, + XED_IFORM_PUNPCKHWD_XMMdq_MEMdq=1561, + XED_IFORM_PUNPCKHWD_XMMdq_XMMq=1562, + XED_IFORM_PUNPCKLBW_MMXq_MEMd=1563, + XED_IFORM_PUNPCKLBW_MMXq_MMXd=1564, + XED_IFORM_PUNPCKLBW_XMMdq_MEMdq=1565, + XED_IFORM_PUNPCKLBW_XMMdq_XMMq=1566, + XED_IFORM_PUNPCKLDQ_MMXq_MEMd=1567, + XED_IFORM_PUNPCKLDQ_MMXq_MMXd=1568, + XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq=1569, + XED_IFORM_PUNPCKLDQ_XMMdq_XMMq=1570, + XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq=1571, + XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq=1572, + XED_IFORM_PUNPCKLWD_MMXq_MEMd=1573, + XED_IFORM_PUNPCKLWD_MMXq_MMXd=1574, + XED_IFORM_PUNPCKLWD_XMMdq_MEMdq=1575, + XED_IFORM_PUNPCKLWD_XMMdq_XMMq=1576, + XED_IFORM_PUSH_CS=1577, + XED_IFORM_PUSH_DS=1578, + XED_IFORM_PUSH_ES=1579, + XED_IFORM_PUSH_FS=1580, + XED_IFORM_PUSH_GPRv_50=1581, + XED_IFORM_PUSH_GPRv_FFr6=1582, + XED_IFORM_PUSH_GS=1583, + XED_IFORM_PUSH_IMMb=1584, + XED_IFORM_PUSH_IMMz=1585, + XED_IFORM_PUSH_MEMv=1586, + XED_IFORM_PUSH_SS=1587, + XED_IFORM_PUSHA=1588, + XED_IFORM_PUSHAD=1589, + XED_IFORM_PUSHF=1590, + XED_IFORM_PUSHFD=1591, + XED_IFORM_PUSHFQ=1592, + XED_IFORM_PVALIDATE_RAX_ECX_EDX=1593, + XED_IFORM_PXOR_MMXq_MEMq=1594, + XED_IFORM_PXOR_MMXq_MMXq=1595, + XED_IFORM_PXOR_XMMdq_MEMdq=1596, + XED_IFORM_PXOR_XMMdq_XMMdq=1597, + XED_IFORM_RCL_GPR8_CL=1598, + XED_IFORM_RCL_GPR8_IMMb=1599, + XED_IFORM_RCL_GPR8_ONE=1600, + XED_IFORM_RCL_GPRv_CL=1601, + XED_IFORM_RCL_GPRv_IMMb=1602, + XED_IFORM_RCL_GPRv_ONE=1603, + XED_IFORM_RCL_MEMb_CL=1604, + XED_IFORM_RCL_MEMb_IMMb=1605, + XED_IFORM_RCL_MEMb_ONE=1606, + XED_IFORM_RCL_MEMv_CL=1607, + XED_IFORM_RCL_MEMv_IMMb=1608, + XED_IFORM_RCL_MEMv_ONE=1609, + XED_IFORM_RCPPS_XMMps_MEMps=1610, + XED_IFORM_RCPPS_XMMps_XMMps=1611, + XED_IFORM_RCPSS_XMMss_MEMss=1612, + XED_IFORM_RCPSS_XMMss_XMMss=1613, + XED_IFORM_RCR_GPR8_CL=1614, + XED_IFORM_RCR_GPR8_IMMb=1615, + XED_IFORM_RCR_GPR8_ONE=1616, + XED_IFORM_RCR_GPRv_CL=1617, + XED_IFORM_RCR_GPRv_IMMb=1618, + XED_IFORM_RCR_GPRv_ONE=1619, + XED_IFORM_RCR_MEMb_CL=1620, + XED_IFORM_RCR_MEMb_IMMb=1621, + XED_IFORM_RCR_MEMb_ONE=1622, + XED_IFORM_RCR_MEMv_CL=1623, + XED_IFORM_RCR_MEMv_IMMb=1624, + XED_IFORM_RCR_MEMv_ONE=1625, + XED_IFORM_RDFSBASE_GPRy=1626, + XED_IFORM_RDGSBASE_GPRy=1627, + XED_IFORM_RDMSR=1628, + XED_IFORM_RDPID_GPR32u32=1629, + XED_IFORM_RDPID_GPR64u64=1630, + XED_IFORM_RDPKRU=1631, + XED_IFORM_RDPMC=1632, + XED_IFORM_RDPRU=1633, + XED_IFORM_RDRAND_GPRv=1634, + XED_IFORM_RDSEED_GPRv=1635, + XED_IFORM_RDSSPD_GPR32u32=1636, + XED_IFORM_RDSSPQ_GPR64u64=1637, + XED_IFORM_RDTSC=1638, + XED_IFORM_RDTSCP=1639, + XED_IFORM_REPE_CMPSB=1640, + XED_IFORM_REPE_CMPSD=1641, + XED_IFORM_REPE_CMPSQ=1642, + XED_IFORM_REPE_CMPSW=1643, + XED_IFORM_REPE_SCASB=1644, + XED_IFORM_REPE_SCASD=1645, + XED_IFORM_REPE_SCASQ=1646, + XED_IFORM_REPE_SCASW=1647, + XED_IFORM_REPNE_CMPSB=1648, + XED_IFORM_REPNE_CMPSD=1649, + XED_IFORM_REPNE_CMPSQ=1650, + XED_IFORM_REPNE_CMPSW=1651, + XED_IFORM_REPNE_SCASB=1652, + XED_IFORM_REPNE_SCASD=1653, + XED_IFORM_REPNE_SCASQ=1654, + XED_IFORM_REPNE_SCASW=1655, + XED_IFORM_REP_INSB=1656, + XED_IFORM_REP_INSD=1657, + XED_IFORM_REP_INSW=1658, + XED_IFORM_REP_LODSB=1659, + XED_IFORM_REP_LODSD=1660, + XED_IFORM_REP_LODSQ=1661, + XED_IFORM_REP_LODSW=1662, + XED_IFORM_REP_MONTMUL=1663, + XED_IFORM_REP_MOVSB=1664, + XED_IFORM_REP_MOVSD=1665, + XED_IFORM_REP_MOVSQ=1666, + XED_IFORM_REP_MOVSW=1667, + XED_IFORM_REP_OUTSB=1668, + XED_IFORM_REP_OUTSD=1669, + XED_IFORM_REP_OUTSW=1670, + XED_IFORM_REP_STOSB=1671, + XED_IFORM_REP_STOSD=1672, + XED_IFORM_REP_STOSQ=1673, + XED_IFORM_REP_STOSW=1674, + XED_IFORM_REP_XCRYPTCBC=1675, + XED_IFORM_REP_XCRYPTCFB=1676, + XED_IFORM_REP_XCRYPTCTR=1677, + XED_IFORM_REP_XCRYPTECB=1678, + XED_IFORM_REP_XCRYPTOFB=1679, + XED_IFORM_REP_XSHA1=1680, + XED_IFORM_REP_XSHA256=1681, + XED_IFORM_REP_XSTORE=1682, + XED_IFORM_RET_FAR=1683, + XED_IFORM_RET_FAR_IMMw=1684, + XED_IFORM_RET_NEAR=1685, + XED_IFORM_RET_NEAR_IMMw=1686, + XED_IFORM_RMPADJUST_RAX_RCX_RDX=1687, + XED_IFORM_RMPUPDATE_RAX_RCX=1688, + XED_IFORM_ROL_GPR8_CL=1689, + XED_IFORM_ROL_GPR8_IMMb=1690, + XED_IFORM_ROL_GPR8_ONE=1691, + XED_IFORM_ROL_GPRv_CL=1692, + XED_IFORM_ROL_GPRv_IMMb=1693, + XED_IFORM_ROL_GPRv_ONE=1694, + XED_IFORM_ROL_MEMb_CL=1695, + XED_IFORM_ROL_MEMb_IMMb=1696, + XED_IFORM_ROL_MEMb_ONE=1697, + XED_IFORM_ROL_MEMv_CL=1698, + XED_IFORM_ROL_MEMv_IMMb=1699, + XED_IFORM_ROL_MEMv_ONE=1700, + XED_IFORM_ROR_GPR8_CL=1701, + XED_IFORM_ROR_GPR8_IMMb=1702, + XED_IFORM_ROR_GPR8_ONE=1703, + XED_IFORM_ROR_GPRv_CL=1704, + XED_IFORM_ROR_GPRv_IMMb=1705, + XED_IFORM_ROR_GPRv_ONE=1706, + XED_IFORM_ROR_MEMb_CL=1707, + XED_IFORM_ROR_MEMb_IMMb=1708, + XED_IFORM_ROR_MEMb_ONE=1709, + XED_IFORM_ROR_MEMv_CL=1710, + XED_IFORM_ROR_MEMv_IMMb=1711, + XED_IFORM_ROR_MEMv_ONE=1712, + XED_IFORM_RORX_VGPR32d_MEMd_IMMb=1713, + XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb=1714, + XED_IFORM_RORX_VGPR64q_MEMq_IMMb=1715, + XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb=1716, + XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb=1717, + XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb=1718, + XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb=1719, + XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb=1720, + XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb=1721, + XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb=1722, + XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb=1723, + XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb=1724, + XED_IFORM_RSM=1725, + XED_IFORM_RSQRTPS_XMMps_MEMps=1726, + XED_IFORM_RSQRTPS_XMMps_XMMps=1727, + XED_IFORM_RSQRTSS_XMMss_MEMss=1728, + XED_IFORM_RSQRTSS_XMMss_XMMss=1729, + XED_IFORM_RSTORSSP_MEMu64=1730, + XED_IFORM_SAHF=1731, + XED_IFORM_SALC=1732, + XED_IFORM_SAR_GPR8_CL=1733, + XED_IFORM_SAR_GPR8_IMMb=1734, + XED_IFORM_SAR_GPR8_ONE=1735, + XED_IFORM_SAR_GPRv_CL=1736, + XED_IFORM_SAR_GPRv_IMMb=1737, + XED_IFORM_SAR_GPRv_ONE=1738, + XED_IFORM_SAR_MEMb_CL=1739, + XED_IFORM_SAR_MEMb_IMMb=1740, + XED_IFORM_SAR_MEMb_ONE=1741, + XED_IFORM_SAR_MEMv_CL=1742, + XED_IFORM_SAR_MEMv_IMMb=1743, + XED_IFORM_SAR_MEMv_ONE=1744, + XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d=1745, + XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d=1746, + XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q=1747, + XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q=1748, + XED_IFORM_SAVEPREVSSP=1749, + XED_IFORM_SBB_AL_IMMb=1750, + XED_IFORM_SBB_GPR8_GPR8_18=1751, + XED_IFORM_SBB_GPR8_GPR8_1A=1752, + XED_IFORM_SBB_GPR8_IMMb_80r3=1753, + XED_IFORM_SBB_GPR8_IMMb_82r3=1754, + XED_IFORM_SBB_GPR8_MEMb=1755, + XED_IFORM_SBB_GPRv_GPRv_19=1756, + XED_IFORM_SBB_GPRv_GPRv_1B=1757, + XED_IFORM_SBB_GPRv_IMMb=1758, + XED_IFORM_SBB_GPRv_IMMz=1759, + XED_IFORM_SBB_GPRv_MEMv=1760, + XED_IFORM_SBB_MEMb_GPR8=1761, + XED_IFORM_SBB_MEMb_IMMb_80r3=1762, + XED_IFORM_SBB_MEMb_IMMb_82r3=1763, + XED_IFORM_SBB_MEMv_GPRv=1764, + XED_IFORM_SBB_MEMv_IMMb=1765, + XED_IFORM_SBB_MEMv_IMMz=1766, + XED_IFORM_SBB_OrAX_IMMz=1767, + XED_IFORM_SBB_LOCK_MEMb_GPR8=1768, + XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3=1769, + XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3=1770, + XED_IFORM_SBB_LOCK_MEMv_GPRv=1771, + XED_IFORM_SBB_LOCK_MEMv_IMMb=1772, + XED_IFORM_SBB_LOCK_MEMv_IMMz=1773, + XED_IFORM_SCASB=1774, + XED_IFORM_SCASD=1775, + XED_IFORM_SCASQ=1776, + XED_IFORM_SCASW=1777, + XED_IFORM_SEAMCALL=1778, + XED_IFORM_SEAMOPS=1779, + XED_IFORM_SEAMRET=1780, + XED_IFORM_SENDUIPI_GPR32u32=1781, + XED_IFORM_SERIALIZE=1782, + XED_IFORM_SETB_GPR8=1783, + XED_IFORM_SETB_MEMb=1784, + XED_IFORM_SETBE_GPR8=1785, + XED_IFORM_SETBE_MEMb=1786, + XED_IFORM_SETL_GPR8=1787, + XED_IFORM_SETL_MEMb=1788, + XED_IFORM_SETLE_GPR8=1789, + XED_IFORM_SETLE_MEMb=1790, + XED_IFORM_SETNB_GPR8=1791, + XED_IFORM_SETNB_MEMb=1792, + XED_IFORM_SETNBE_GPR8=1793, + XED_IFORM_SETNBE_MEMb=1794, + XED_IFORM_SETNL_GPR8=1795, + XED_IFORM_SETNL_MEMb=1796, + XED_IFORM_SETNLE_GPR8=1797, + XED_IFORM_SETNLE_MEMb=1798, + XED_IFORM_SETNO_GPR8=1799, + XED_IFORM_SETNO_MEMb=1800, + XED_IFORM_SETNP_GPR8=1801, + XED_IFORM_SETNP_MEMb=1802, + XED_IFORM_SETNS_GPR8=1803, + XED_IFORM_SETNS_MEMb=1804, + XED_IFORM_SETNZ_GPR8=1805, + XED_IFORM_SETNZ_MEMb=1806, + XED_IFORM_SETO_GPR8=1807, + XED_IFORM_SETO_MEMb=1808, + XED_IFORM_SETP_GPR8=1809, + XED_IFORM_SETP_MEMb=1810, + XED_IFORM_SETS_GPR8=1811, + XED_IFORM_SETS_MEMb=1812, + XED_IFORM_SETSSBSY=1813, + XED_IFORM_SETZ_GPR8=1814, + XED_IFORM_SETZ_MEMb=1815, + XED_IFORM_SFENCE=1816, + XED_IFORM_SGDT_MEMs=1817, + XED_IFORM_SGDT_MEMs64=1818, + XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA=1819, + XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA=1820, + XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA=1821, + XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA=1822, + XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA=1823, + XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA=1824, + XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA=1825, + XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA=1826, + XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA=1827, + XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA=1828, + XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA=1829, + XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA=1830, + XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA=1831, + XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA=1832, + XED_IFORM_SHL_GPR8_CL_D2r4=1833, + XED_IFORM_SHL_GPR8_CL_D2r6=1834, + XED_IFORM_SHL_GPR8_IMMb_C0r4=1835, + XED_IFORM_SHL_GPR8_IMMb_C0r6=1836, + XED_IFORM_SHL_GPR8_ONE_D0r4=1837, + XED_IFORM_SHL_GPR8_ONE_D0r6=1838, + XED_IFORM_SHL_GPRv_CL_D3r4=1839, + XED_IFORM_SHL_GPRv_CL_D3r6=1840, + XED_IFORM_SHL_GPRv_IMMb_C1r4=1841, + XED_IFORM_SHL_GPRv_IMMb_C1r6=1842, + XED_IFORM_SHL_GPRv_ONE_D1r4=1843, + XED_IFORM_SHL_GPRv_ONE_D1r6=1844, + XED_IFORM_SHL_MEMb_CL_D2r4=1845, + XED_IFORM_SHL_MEMb_CL_D2r6=1846, + XED_IFORM_SHL_MEMb_IMMb_C0r4=1847, + XED_IFORM_SHL_MEMb_IMMb_C0r6=1848, + XED_IFORM_SHL_MEMb_ONE_D0r4=1849, + XED_IFORM_SHL_MEMb_ONE_D0r6=1850, + XED_IFORM_SHL_MEMv_CL_D3r4=1851, + XED_IFORM_SHL_MEMv_CL_D3r6=1852, + XED_IFORM_SHL_MEMv_IMMb_C1r4=1853, + XED_IFORM_SHL_MEMv_IMMb_C1r6=1854, + XED_IFORM_SHL_MEMv_ONE_D1r4=1855, + XED_IFORM_SHL_MEMv_ONE_D1r6=1856, + XED_IFORM_SHLD_GPRv_GPRv_CL=1857, + XED_IFORM_SHLD_GPRv_GPRv_IMMb=1858, + XED_IFORM_SHLD_MEMv_GPRv_CL=1859, + XED_IFORM_SHLD_MEMv_GPRv_IMMb=1860, + XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d=1861, + XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d=1862, + XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q=1863, + XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q=1864, + XED_IFORM_SHR_GPR8_CL=1865, + XED_IFORM_SHR_GPR8_IMMb=1866, + XED_IFORM_SHR_GPR8_ONE=1867, + XED_IFORM_SHR_GPRv_CL=1868, + XED_IFORM_SHR_GPRv_IMMb=1869, + XED_IFORM_SHR_GPRv_ONE=1870, + XED_IFORM_SHR_MEMb_CL=1871, + XED_IFORM_SHR_MEMb_IMMb=1872, + XED_IFORM_SHR_MEMb_ONE=1873, + XED_IFORM_SHR_MEMv_CL=1874, + XED_IFORM_SHR_MEMv_IMMb=1875, + XED_IFORM_SHR_MEMv_ONE=1876, + XED_IFORM_SHRD_GPRv_GPRv_CL=1877, + XED_IFORM_SHRD_GPRv_GPRv_IMMb=1878, + XED_IFORM_SHRD_MEMv_GPRv_CL=1879, + XED_IFORM_SHRD_MEMv_GPRv_IMMb=1880, + XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d=1881, + XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d=1882, + XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q=1883, + XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q=1884, + XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb=1885, + XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb=1886, + XED_IFORM_SHUFPS_XMMps_MEMps_IMMb=1887, + XED_IFORM_SHUFPS_XMMps_XMMps_IMMb=1888, + XED_IFORM_SIDT_MEMs=1889, + XED_IFORM_SIDT_MEMs64=1890, + XED_IFORM_SKINIT_EAX=1891, + XED_IFORM_SLDT_GPRv=1892, + XED_IFORM_SLDT_MEMw=1893, + XED_IFORM_SLWPCB_VGPRyy=1894, + XED_IFORM_SMSW_GPRv=1895, + XED_IFORM_SMSW_MEMw=1896, + XED_IFORM_SQRTPD_XMMpd_MEMpd=1897, + XED_IFORM_SQRTPD_XMMpd_XMMpd=1898, + XED_IFORM_SQRTPS_XMMps_MEMps=1899, + XED_IFORM_SQRTPS_XMMps_XMMps=1900, + XED_IFORM_SQRTSD_XMMsd_MEMsd=1901, + XED_IFORM_SQRTSD_XMMsd_XMMsd=1902, + XED_IFORM_SQRTSS_XMMss_MEMss=1903, + XED_IFORM_SQRTSS_XMMss_XMMss=1904, + XED_IFORM_STAC=1905, + XED_IFORM_STC=1906, + XED_IFORM_STD=1907, + XED_IFORM_STGI=1908, + XED_IFORM_STI=1909, + XED_IFORM_STMXCSR_MEMd=1910, + XED_IFORM_STOSB=1911, + XED_IFORM_STOSD=1912, + XED_IFORM_STOSQ=1913, + XED_IFORM_STOSW=1914, + XED_IFORM_STR_GPRv=1915, + XED_IFORM_STR_MEMw=1916, + XED_IFORM_STTILECFG_MEM=1917, + XED_IFORM_STUI=1918, + XED_IFORM_SUB_AL_IMMb=1919, + XED_IFORM_SUB_GPR8_GPR8_28=1920, + XED_IFORM_SUB_GPR8_GPR8_2A=1921, + XED_IFORM_SUB_GPR8_IMMb_80r5=1922, + XED_IFORM_SUB_GPR8_IMMb_82r5=1923, + XED_IFORM_SUB_GPR8_MEMb=1924, + XED_IFORM_SUB_GPRv_GPRv_29=1925, + XED_IFORM_SUB_GPRv_GPRv_2B=1926, + XED_IFORM_SUB_GPRv_IMMb=1927, + XED_IFORM_SUB_GPRv_IMMz=1928, + XED_IFORM_SUB_GPRv_MEMv=1929, + XED_IFORM_SUB_MEMb_GPR8=1930, + XED_IFORM_SUB_MEMb_IMMb_80r5=1931, + XED_IFORM_SUB_MEMb_IMMb_82r5=1932, + XED_IFORM_SUB_MEMv_GPRv=1933, + XED_IFORM_SUB_MEMv_IMMb=1934, + XED_IFORM_SUB_MEMv_IMMz=1935, + XED_IFORM_SUB_OrAX_IMMz=1936, + XED_IFORM_SUBPD_XMMpd_MEMpd=1937, + XED_IFORM_SUBPD_XMMpd_XMMpd=1938, + XED_IFORM_SUBPS_XMMps_MEMps=1939, + XED_IFORM_SUBPS_XMMps_XMMps=1940, + XED_IFORM_SUBSD_XMMsd_MEMsd=1941, + XED_IFORM_SUBSD_XMMsd_XMMsd=1942, + XED_IFORM_SUBSS_XMMss_MEMss=1943, + XED_IFORM_SUBSS_XMMss_XMMss=1944, + XED_IFORM_SUB_LOCK_MEMb_GPR8=1945, + XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5=1946, + XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5=1947, + XED_IFORM_SUB_LOCK_MEMv_GPRv=1948, + XED_IFORM_SUB_LOCK_MEMv_IMMb=1949, + XED_IFORM_SUB_LOCK_MEMv_IMMz=1950, + XED_IFORM_SWAPGS=1951, + XED_IFORM_SYSCALL=1952, + XED_IFORM_SYSCALL_AMD=1953, + XED_IFORM_SYSENTER=1954, + XED_IFORM_SYSEXIT=1955, + XED_IFORM_SYSRET=1956, + XED_IFORM_SYSRET64=1957, + XED_IFORM_SYSRET_AMD=1958, + XED_IFORM_T1MSKC_VGPR32d_MEMd=1959, + XED_IFORM_T1MSKC_VGPR32d_VGPR32d=1960, + XED_IFORM_T1MSKC_VGPRyy_MEMy=1961, + XED_IFORM_T1MSKC_VGPRyy_VGPRyy=1962, + XED_IFORM_TDCALL=1963, + XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32=1964, + XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32=1965, + XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32=1966, + XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32=1967, + XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32=1968, + XED_IFORM_TEST_AL_IMMb=1969, + XED_IFORM_TEST_GPR8_GPR8=1970, + XED_IFORM_TEST_GPR8_IMMb_F6r0=1971, + XED_IFORM_TEST_GPR8_IMMb_F6r1=1972, + XED_IFORM_TEST_GPRv_GPRv=1973, + XED_IFORM_TEST_GPRv_IMMz_F7r0=1974, + XED_IFORM_TEST_GPRv_IMMz_F7r1=1975, + XED_IFORM_TEST_MEMb_GPR8=1976, + XED_IFORM_TEST_MEMb_IMMb_F6r0=1977, + XED_IFORM_TEST_MEMb_IMMb_F6r1=1978, + XED_IFORM_TEST_MEMv_GPRv=1979, + XED_IFORM_TEST_MEMv_IMMz_F7r0=1980, + XED_IFORM_TEST_MEMv_IMMz_F7r1=1981, + XED_IFORM_TEST_OrAX_IMMz=1982, + XED_IFORM_TESTUI=1983, + XED_IFORM_TILELOADD_TMMu32_MEMu32=1984, + XED_IFORM_TILELOADDT1_TMMu32_MEMu32=1985, + XED_IFORM_TILERELEASE=1986, + XED_IFORM_TILESTORED_MEMu32_TMMu32=1987, + XED_IFORM_TILEZERO_TMMu32=1988, + XED_IFORM_TLBSYNC=1989, + XED_IFORM_TPAUSE_GPR32u32=1990, + XED_IFORM_TZCNT_GPRv_GPRv=1991, + XED_IFORM_TZCNT_GPRv_MEMv=1992, + XED_IFORM_TZMSK_VGPR32d_MEMd=1993, + XED_IFORM_TZMSK_VGPR32d_VGPR32d=1994, + XED_IFORM_TZMSK_VGPRyy_MEMy=1995, + XED_IFORM_TZMSK_VGPRyy_VGPRyy=1996, + XED_IFORM_UCOMISD_XMMsd_MEMsd=1997, + XED_IFORM_UCOMISD_XMMsd_XMMsd=1998, + XED_IFORM_UCOMISS_XMMss_MEMss=1999, + XED_IFORM_UCOMISS_XMMss_XMMss=2000, + XED_IFORM_UD0=2001, + XED_IFORM_UD0_GPR32_GPR32=2002, + XED_IFORM_UD0_GPR32_MEMd=2003, + XED_IFORM_UD1_GPR32_GPR32=2004, + XED_IFORM_UD1_GPR32_MEMd=2005, + XED_IFORM_UD2=2006, + XED_IFORM_UIRET=2007, + XED_IFORM_UMONITOR_GPRa=2008, + XED_IFORM_UMWAIT_GPR32=2009, + XED_IFORM_UNPCKHPD_XMMpd_MEMdq=2010, + XED_IFORM_UNPCKHPD_XMMpd_XMMq=2011, + XED_IFORM_UNPCKHPS_XMMps_MEMdq=2012, + XED_IFORM_UNPCKHPS_XMMps_XMMdq=2013, + XED_IFORM_UNPCKLPD_XMMpd_MEMdq=2014, + XED_IFORM_UNPCKLPD_XMMpd_XMMq=2015, + XED_IFORM_UNPCKLPS_XMMps_MEMdq=2016, + XED_IFORM_UNPCKLPS_XMMps_XMMq=2017, + XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2018, + XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2019, + XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2020, + XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2021, + XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq=2022, + XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq=2023, + XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2024, + XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2025, + XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2026, + XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2027, + XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq=2028, + XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq=2029, + XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2030, + XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2031, + XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2032, + XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2033, + XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2034, + XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2035, + XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2036, + XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2037, + XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq=2038, + XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq=2039, + XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2040, + XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2041, + XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2042, + XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2043, + XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq=2044, + XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq=2045, + XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2046, + XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2047, + XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq=2048, + XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq=2049, + XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2050, + XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2051, + XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2052, + XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2053, + XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd=2054, + XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd=2055, + XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2056, + XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2057, + XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq=2058, + XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq=2059, + XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq=2060, + XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq=2061, + XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq=2062, + XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq=2063, + XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq=2064, + XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq=2065, + XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq=2066, + XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq=2067, + XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512=2068, + XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512=2069, + XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128=2070, + XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512=2071, + XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128=2072, + XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512=2073, + XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512=2074, + XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512=2075, + XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq=2076, + XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq=2077, + XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512=2078, + XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512=2079, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128=2080, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512=2081, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128=2082, + XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512=2083, + XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2084, + XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2085, + XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq=2086, + XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq=2087, + XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512=2088, + XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512=2089, + XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128=2090, + XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512=2091, + XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128=2092, + XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512=2093, + XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512=2094, + XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512=2095, + XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq=2096, + XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq=2097, + XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512=2098, + XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512=2099, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128=2100, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512=2101, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128=2102, + XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512=2103, + XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512=2104, + XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512=2105, + XED_IFORM_VAESIMC_XMMdq_MEMdq=2106, + XED_IFORM_VAESIMC_XMMdq_XMMdq=2107, + XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb=2108, + XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb=2109, + XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=2110, + XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=2111, + XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=2112, + XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=2113, + XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=2114, + XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=2115, + XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=2116, + XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=2117, + XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=2118, + XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=2119, + XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=2120, + XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=2121, + XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq=2122, + XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq=2123, + XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2124, + XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2125, + XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq=2126, + XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq=2127, + XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2128, + XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2129, + XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2130, + XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2131, + XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq=2132, + XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq=2133, + XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2134, + XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2135, + XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq=2136, + XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq=2137, + XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2138, + XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2139, + XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2140, + XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2141, + XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq=2142, + XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq=2143, + XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=2144, + XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=2145, + XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq=2146, + XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq=2147, + XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=2148, + XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=2149, + XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=2150, + XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=2151, + XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq=2152, + XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq=2153, + XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=2154, + XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=2155, + XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq=2156, + XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq=2157, + XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=2158, + XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=2159, + XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=2160, + XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=2161, + XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2162, + XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2163, + XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2164, + XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2165, + XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2166, + XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2167, + XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2168, + XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2169, + XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2170, + XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2171, + XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2172, + XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2173, + XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb=2174, + XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb=2175, + XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb=2176, + XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb=2177, + XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb=2178, + XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb=2179, + XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb=2180, + XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb=2181, + XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq=2182, + XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq=2183, + XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq=2184, + XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq=2185, + XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq=2186, + XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq=2187, + XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq=2188, + XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq=2189, + XED_IFORM_VBROADCASTF128_YMMqq_MEMdq=2190, + XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512=2191, + XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512=2192, + XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512=2193, + XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512=2194, + XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512=2195, + XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512=2196, + XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512=2197, + XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512=2198, + XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512=2199, + XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512=2200, + XED_IFORM_VBROADCASTI128_YMMqq_MEMdq=2201, + XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512=2202, + XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512=2203, + XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512=2204, + XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512=2205, + XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512=2206, + XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512=2207, + XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512=2208, + XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512=2209, + XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512=2210, + XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512=2211, + XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512=2212, + XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512=2213, + XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512=2214, + XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512=2215, + XED_IFORM_VBROADCASTSD_YMMqq_MEMq=2216, + XED_IFORM_VBROADCASTSD_YMMqq_XMMdq=2217, + XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512=2218, + XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512=2219, + XED_IFORM_VBROADCASTSS_XMMdq_MEMd=2220, + XED_IFORM_VBROADCASTSS_XMMdq_XMMdq=2221, + XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512=2222, + XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512=2223, + XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512=2224, + XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512=2225, + XED_IFORM_VBROADCASTSS_YMMqq_MEMd=2226, + XED_IFORM_VBROADCASTSS_YMMqq_XMMdq=2227, + XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512=2228, + XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512=2229, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2230, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2231, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2232, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2233, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2234, + XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2235, + XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb=2236, + XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb=2237, + XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb=2238, + XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb=2239, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=2240, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=2241, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512=2242, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512=2243, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512=2244, + XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512=2245, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2246, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2247, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2248, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2249, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2250, + XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2251, + XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb=2252, + XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb=2253, + XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb=2254, + XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb=2255, + XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2256, + XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2257, + XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb=2258, + XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb=2259, + XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=2260, + XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=2261, + XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2262, + XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2263, + XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb=2264, + XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb=2265, + XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512=2266, + XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512=2267, + XED_IFORM_VCOMISD_XMMq_MEMq=2268, + XED_IFORM_VCOMISD_XMMq_XMMq=2269, + XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512=2270, + XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512=2271, + XED_IFORM_VCOMISS_XMMd_MEMd=2272, + XED_IFORM_VCOMISS_XMMd_XMMd=2273, + XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512=2274, + XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512=2275, + XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512=2276, + XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512=2277, + XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512=2278, + XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512=2279, + XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512=2280, + XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2281, + XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512=2282, + XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512=2283, + XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512=2284, + XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512=2285, + XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512=2286, + XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2287, + XED_IFORM_VCVTDQ2PD_XMMdq_MEMq=2288, + XED_IFORM_VCVTDQ2PD_XMMdq_XMMq=2289, + XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512=2290, + XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512=2291, + XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512=2292, + XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512=2293, + XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq=2294, + XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq=2295, + XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512=2296, + XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512=2297, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128=2298, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256=2299, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512=2300, + XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512=2301, + XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512=2302, + XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512=2303, + XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq=2304, + XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq=2305, + XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512=2306, + XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512=2307, + XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512=2308, + XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512=2309, + XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq=2310, + XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq=2311, + XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512=2312, + XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512=2313, + XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128=2314, + XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512=2315, + XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256=2316, + XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512=2317, + XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512=2318, + XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512=2319, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128=2320, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256=2321, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512=2322, + XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512=2323, + XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512=2324, + XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512=2325, + XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq=2326, + XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq=2327, + XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq=2328, + XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq=2329, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2330, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2331, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2332, + XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2333, + XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2334, + XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2335, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128=2336, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256=2337, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512=2338, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512=2339, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512=2340, + XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512=2341, + XED_IFORM_VCVTPD2PS_XMMdq_MEMdq=2342, + XED_IFORM_VCVTPD2PS_XMMdq_MEMqq=2343, + XED_IFORM_VCVTPD2PS_XMMdq_XMMdq=2344, + XED_IFORM_VCVTPD2PS_XMMdq_YMMqq=2345, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128=2346, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256=2347, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128=2348, + XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256=2349, + XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512=2350, + XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512=2351, + XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2352, + XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2353, + XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2354, + XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2355, + XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2356, + XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2357, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2358, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2359, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2360, + XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2361, + XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2362, + XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2363, + XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2364, + XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2365, + XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2366, + XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2367, + XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2368, + XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2369, + XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512=2370, + XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512=2371, + XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512=2372, + XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512=2373, + XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512=2374, + XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512=2375, + XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512=2376, + XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512=2377, + XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512=2378, + XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512=2379, + XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512=2380, + XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512=2381, + XED_IFORM_VCVTPH2PS_XMMdq_MEMq=2382, + XED_IFORM_VCVTPH2PS_XMMdq_XMMq=2383, + XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512=2384, + XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512=2385, + XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512=2386, + XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512=2387, + XED_IFORM_VCVTPH2PS_YMMqq_MEMdq=2388, + XED_IFORM_VCVTPH2PS_YMMqq_XMMdq=2389, + XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512=2390, + XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512=2391, + XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512=2392, + XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512=2393, + XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512=2394, + XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512=2395, + XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512=2396, + XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512=2397, + XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512=2398, + XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512=2399, + XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512=2400, + XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512=2401, + XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512=2402, + XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512=2403, + XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512=2404, + XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512=2405, + XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512=2406, + XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512=2407, + XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512=2408, + XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512=2409, + XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512=2410, + XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512=2411, + XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512=2412, + XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512=2413, + XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512=2414, + XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512=2415, + XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512=2416, + XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512=2417, + XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512=2418, + XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512=2419, + XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512=2420, + XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512=2421, + XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512=2422, + XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512=2423, + XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512=2424, + XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512=2425, + XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512=2426, + XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512=2427, + XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq=2428, + XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq=2429, + XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2430, + XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2431, + XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2432, + XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2433, + XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq=2434, + XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq=2435, + XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2436, + XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2437, + XED_IFORM_VCVTPS2PD_XMMdq_MEMq=2438, + XED_IFORM_VCVTPS2PD_XMMdq_XMMq=2439, + XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512=2440, + XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512=2441, + XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512=2442, + XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512=2443, + XED_IFORM_VCVTPS2PD_YMMqq_MEMdq=2444, + XED_IFORM_VCVTPS2PD_YMMqq_XMMdq=2445, + XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512=2446, + XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512=2447, + XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb=2448, + XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512=2449, + XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512=2450, + XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512=2451, + XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb=2452, + XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb=2453, + XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512=2454, + XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512=2455, + XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb=2456, + XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512=2457, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128=2458, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256=2459, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512=2460, + XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512=2461, + XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512=2462, + XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512=2463, + XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2464, + XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2465, + XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2466, + XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2467, + XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2468, + XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2469, + XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2470, + XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2471, + XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2472, + XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2473, + XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2474, + XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2475, + XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2476, + XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2477, + XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2478, + XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2479, + XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2480, + XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2481, + XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512=2482, + XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512=2483, + XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512=2484, + XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512=2485, + XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512=2486, + XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512=2487, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128=2488, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256=2489, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512=2490, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512=2491, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512=2492, + XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512=2493, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2494, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2495, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2496, + XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2497, + XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2498, + XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2499, + XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512=2500, + XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512=2501, + XED_IFORM_VCVTSD2SI_GPR32d_MEMq=2502, + XED_IFORM_VCVTSD2SI_GPR32d_XMMq=2503, + XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512=2504, + XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512=2505, + XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512=2506, + XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512=2507, + XED_IFORM_VCVTSD2SI_GPR64q_MEMq=2508, + XED_IFORM_VCVTSD2SI_GPR64q_XMMq=2509, + XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq=2510, + XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq=2511, + XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512=2512, + XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512=2513, + XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512=2514, + XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512=2515, + XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512=2516, + XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512=2517, + XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512=2518, + XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512=2519, + XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512=2520, + XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512=2521, + XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512=2522, + XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512=2523, + XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512=2524, + XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512=2525, + XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512=2526, + XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512=2527, + XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512=2528, + XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512=2529, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d=2530, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q=2531, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd=2532, + XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq=2533, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512=2534, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512=2535, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512=2536, + XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512=2537, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512=2538, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512=2539, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512=2540, + XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512=2541, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d=2542, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q=2543, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd=2544, + XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq=2545, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512=2546, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512=2547, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512=2548, + XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512=2549, + XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd=2550, + XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd=2551, + XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512=2552, + XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512=2553, + XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512=2554, + XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512=2555, + XED_IFORM_VCVTSS2SI_GPR32d_MEMd=2556, + XED_IFORM_VCVTSS2SI_GPR32d_XMMd=2557, + XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512=2558, + XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512=2559, + XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512=2560, + XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512=2561, + XED_IFORM_VCVTSS2SI_GPR64q_MEMd=2562, + XED_IFORM_VCVTSS2SI_GPR64q_XMMd=2563, + XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512=2564, + XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512=2565, + XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512=2566, + XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512=2567, + XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq=2568, + XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq=2569, + XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq=2570, + XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq=2571, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128=2572, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256=2573, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128=2574, + XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256=2575, + XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512=2576, + XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512=2577, + XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512=2578, + XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512=2579, + XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512=2580, + XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512=2581, + XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512=2582, + XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512=2583, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128=2584, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256=2585, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128=2586, + XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256=2587, + XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512=2588, + XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512=2589, + XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512=2590, + XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512=2591, + XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512=2592, + XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512=2593, + XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512=2594, + XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512=2595, + XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512=2596, + XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512=2597, + XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512=2598, + XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512=2599, + XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512=2600, + XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512=2601, + XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512=2602, + XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512=2603, + XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512=2604, + XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512=2605, + XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512=2606, + XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512=2607, + XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512=2608, + XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512=2609, + XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512=2610, + XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512=2611, + XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512=2612, + XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512=2613, + XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512=2614, + XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512=2615, + XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512=2616, + XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512=2617, + XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512=2618, + XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512=2619, + XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512=2620, + XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512=2621, + XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512=2622, + XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512=2623, + XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512=2624, + XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512=2625, + XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512=2626, + XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512=2627, + XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512=2628, + XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512=2629, + XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512=2630, + XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512=2631, + XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq=2632, + XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq=2633, + XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512=2634, + XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512=2635, + XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512=2636, + XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512=2637, + XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq=2638, + XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq=2639, + XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512=2640, + XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512=2641, + XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512=2642, + XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512=2643, + XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512=2644, + XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512=2645, + XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512=2646, + XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512=2647, + XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512=2648, + XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512=2649, + XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512=2650, + XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512=2651, + XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512=2652, + XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512=2653, + XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512=2654, + XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512=2655, + XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512=2656, + XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512=2657, + XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512=2658, + XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512=2659, + XED_IFORM_VCVTTSD2SI_GPR32d_MEMq=2660, + XED_IFORM_VCVTTSD2SI_GPR32d_XMMq=2661, + XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512=2662, + XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512=2663, + XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512=2664, + XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512=2665, + XED_IFORM_VCVTTSD2SI_GPR64q_MEMq=2666, + XED_IFORM_VCVTTSD2SI_GPR64q_XMMq=2667, + XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512=2668, + XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512=2669, + XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512=2670, + XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512=2671, + XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512=2672, + XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512=2673, + XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512=2674, + XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512=2675, + XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512=2676, + XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512=2677, + XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512=2678, + XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512=2679, + XED_IFORM_VCVTTSS2SI_GPR32d_MEMd=2680, + XED_IFORM_VCVTTSS2SI_GPR32d_XMMd=2681, + XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512=2682, + XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512=2683, + XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512=2684, + XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512=2685, + XED_IFORM_VCVTTSS2SI_GPR64q_MEMd=2686, + XED_IFORM_VCVTTSS2SI_GPR64q_XMMd=2687, + XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512=2688, + XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512=2689, + XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512=2690, + XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512=2691, + XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512=2692, + XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512=2693, + XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512=2694, + XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512=2695, + XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512=2696, + XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512=2697, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128=2698, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256=2699, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512=2700, + XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512=2701, + XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512=2702, + XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512=2703, + XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512=2704, + XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512=2705, + XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512=2706, + XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512=2707, + XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512=2708, + XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512=2709, + XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512=2710, + XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512=2711, + XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512=2712, + XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512=2713, + XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512=2714, + XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512=2715, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128=2716, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256=2717, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512=2718, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512=2719, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512=2720, + XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512=2721, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128=2722, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256=2723, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128=2724, + XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256=2725, + XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512=2726, + XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512=2727, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512=2728, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512=2729, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512=2730, + XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512=2731, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512=2732, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512=2733, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512=2734, + XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512=2735, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512=2736, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512=2737, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512=2738, + XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512=2739, + XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512=2740, + XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512=2741, + XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512=2742, + XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512=2743, + XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512=2744, + XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512=2745, + XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512=2746, + XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512=2747, + XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512=2748, + XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512=2749, + XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512=2750, + XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512=2751, + XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=2752, + XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=2753, + XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=2754, + XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=2755, + XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=2756, + XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=2757, + XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq=2758, + XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq=2759, + XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2760, + XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2761, + XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2762, + XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2763, + XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq=2764, + XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq=2765, + XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2766, + XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2767, + XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2768, + XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2769, + XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2770, + XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2771, + XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2772, + XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2773, + XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq=2774, + XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq=2775, + XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2776, + XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2777, + XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2778, + XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2779, + XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq=2780, + XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq=2781, + XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2782, + XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2783, + XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq=2784, + XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq=2785, + XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2786, + XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2787, + XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2788, + XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2789, + XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd=2790, + XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd=2791, + XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2792, + XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2793, + XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512=2794, + XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512=2795, + XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512=2796, + XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512=2797, + XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512=2798, + XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512=2799, + XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb=2800, + XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb=2801, + XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb=2802, + XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb=2803, + XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb=2804, + XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb=2805, + XED_IFORM_VERR_GPR16=2806, + XED_IFORM_VERR_MEMw=2807, + XED_IFORM_VERW_GPR16=2808, + XED_IFORM_VERW_MEMw=2809, + XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=2810, + XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=2811, + XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=2812, + XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=2813, + XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512=2814, + XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512=2815, + XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512=2816, + XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512=2817, + XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512=2818, + XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512=2819, + XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512=2820, + XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512=2821, + XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512=2822, + XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512=2823, + XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512=2824, + XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512=2825, + XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb=2826, + XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb=2827, + XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512=2828, + XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2829, + XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512=2830, + XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2831, + XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512=2832, + XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512=2833, + XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512=2834, + XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2835, + XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512=2836, + XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2837, + XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512=2838, + XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512=2839, + XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb=2840, + XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb=2841, + XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512=2842, + XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2843, + XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512=2844, + XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2845, + XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512=2846, + XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512=2847, + XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512=2848, + XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2849, + XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512=2850, + XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2851, + XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512=2852, + XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512=2853, + XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb=2854, + XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512=2855, + XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb=2856, + XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512=2857, + XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2858, + XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2859, + XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=2860, + XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=2861, + XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=2862, + XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=2863, + XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2864, + XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2865, + XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2866, + XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2867, + XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=2868, + XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=2869, + XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=2870, + XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=2871, + XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2872, + XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2873, + XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2874, + XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2875, + XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=2876, + XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=2877, + XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=2878, + XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=2879, + XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2880, + XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2881, + XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=2882, + XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=2883, + XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=2884, + XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=2885, + XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=2886, + XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=2887, + XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=2888, + XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=2889, + XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq=2890, + XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq=2891, + XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2892, + XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2893, + XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2894, + XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2895, + XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq=2896, + XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq=2897, + XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2898, + XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2899, + XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2900, + XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2901, + XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2902, + XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2903, + XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2904, + XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2905, + XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq=2906, + XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq=2907, + XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2908, + XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2909, + XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2910, + XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2911, + XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq=2912, + XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq=2913, + XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2914, + XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2915, + XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq=2916, + XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq=2917, + XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2918, + XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2919, + XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2920, + XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2921, + XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd=2922, + XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd=2923, + XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2924, + XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2925, + XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq=2926, + XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq=2927, + XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2928, + XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2929, + XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2930, + XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2931, + XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq=2932, + XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq=2933, + XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2934, + XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2935, + XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2936, + XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2937, + XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2938, + XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2939, + XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2940, + XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2941, + XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq=2942, + XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq=2943, + XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2944, + XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2945, + XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2946, + XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2947, + XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq=2948, + XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq=2949, + XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2950, + XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2951, + XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq=2952, + XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq=2953, + XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2954, + XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2955, + XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2956, + XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2957, + XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd=2958, + XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd=2959, + XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2960, + XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2961, + XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq=2962, + XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq=2963, + XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2964, + XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2965, + XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=2966, + XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=2967, + XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq=2968, + XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq=2969, + XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=2970, + XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=2971, + XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2972, + XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2973, + XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=2974, + XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=2975, + XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=2976, + XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=2977, + XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq=2978, + XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq=2979, + XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2980, + XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2981, + XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=2982, + XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=2983, + XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq=2984, + XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq=2985, + XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=2986, + XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=2987, + XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq=2988, + XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq=2989, + XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=2990, + XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=2991, + XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=2992, + XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=2993, + XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd=2994, + XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd=2995, + XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=2996, + XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=2997, + XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=2998, + XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=2999, + XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=3000, + XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=3001, + XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=3002, + XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=3003, + XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3004, + XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3005, + XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3006, + XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3007, + XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3008, + XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3009, + XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3010, + XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3011, + XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3012, + XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3013, + XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3014, + XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3015, + XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3016, + XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3017, + XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq=3018, + XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq=3019, + XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq=3020, + XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd=3021, + XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd=3022, + XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd=3023, + XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq=3024, + XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq=3025, + XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3026, + XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3027, + XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3028, + XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3029, + XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq=3030, + XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq=3031, + XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3032, + XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3033, + XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3034, + XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3035, + XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3036, + XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3037, + XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3038, + XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3039, + XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq=3040, + XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq=3041, + XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3042, + XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3043, + XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3044, + XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3045, + XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq=3046, + XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq=3047, + XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3048, + XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3049, + XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq=3050, + XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq=3051, + XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3052, + XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3053, + XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3054, + XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3055, + XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq=3056, + XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq=3057, + XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3058, + XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3059, + XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3060, + XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3061, + XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3062, + XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3063, + XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3064, + XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3065, + XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq=3066, + XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq=3067, + XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3068, + XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3069, + XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3070, + XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3071, + XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq=3072, + XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq=3073, + XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3074, + XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3075, + XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq=3076, + XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq=3077, + XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3078, + XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3079, + XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3080, + XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3081, + XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq=3082, + XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq=3083, + XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3084, + XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3085, + XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3086, + XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3087, + XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3088, + XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3089, + XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3090, + XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3091, + XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq=3092, + XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq=3093, + XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3094, + XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3095, + XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3096, + XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3097, + XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq=3098, + XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq=3099, + XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3100, + XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3101, + XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3102, + XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3103, + XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3104, + XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3105, + XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3106, + XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3107, + XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3108, + XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3109, + XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3110, + XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3111, + XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3112, + XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3113, + XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq=3114, + XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq=3115, + XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3116, + XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3117, + XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3118, + XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3119, + XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq=3120, + XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq=3121, + XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3122, + XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3123, + XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3124, + XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3125, + XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3126, + XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3127, + XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3128, + XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3129, + XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq=3130, + XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq=3131, + XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3132, + XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3133, + XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3134, + XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3135, + XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq=3136, + XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq=3137, + XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3138, + XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3139, + XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq=3140, + XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq=3141, + XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3142, + XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3143, + XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3144, + XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3145, + XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd=3146, + XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd=3147, + XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3148, + XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3149, + XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq=3150, + XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq=3151, + XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3152, + XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3153, + XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3154, + XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3155, + XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq=3156, + XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq=3157, + XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3158, + XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3159, + XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3160, + XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3161, + XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3162, + XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3163, + XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3164, + XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3165, + XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq=3166, + XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq=3167, + XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3168, + XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3169, + XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3170, + XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3171, + XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq=3172, + XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq=3173, + XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3174, + XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3175, + XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq=3176, + XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq=3177, + XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3178, + XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3179, + XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3180, + XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3181, + XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd=3182, + XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd=3183, + XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3184, + XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3185, + XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq=3186, + XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq=3187, + XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3188, + XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3189, + XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3190, + XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3191, + XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq=3192, + XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq=3193, + XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3194, + XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3195, + XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3196, + XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3197, + XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3198, + XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3199, + XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3200, + XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3201, + XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq=3202, + XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq=3203, + XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3204, + XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3205, + XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3206, + XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3207, + XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq=3208, + XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq=3209, + XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3210, + XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3211, + XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq=3212, + XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq=3213, + XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3214, + XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3215, + XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3216, + XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3217, + XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd=3218, + XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd=3219, + XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3220, + XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3221, + XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq=3222, + XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq=3223, + XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3224, + XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3225, + XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3226, + XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3227, + XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq=3228, + XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq=3229, + XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3230, + XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3231, + XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3232, + XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3233, + XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3234, + XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3235, + XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3236, + XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3237, + XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq=3238, + XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq=3239, + XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3240, + XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3241, + XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3242, + XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3243, + XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq=3244, + XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq=3245, + XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3246, + XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3247, + XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq=3248, + XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq=3249, + XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3250, + XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3251, + XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3252, + XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3253, + XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq=3254, + XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq=3255, + XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3256, + XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3257, + XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3258, + XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3259, + XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3260, + XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3261, + XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3262, + XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3263, + XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq=3264, + XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq=3265, + XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3266, + XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3267, + XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3268, + XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3269, + XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq=3270, + XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq=3271, + XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3272, + XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3273, + XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq=3274, + XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq=3275, + XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3276, + XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3277, + XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3278, + XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3279, + XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq=3280, + XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq=3281, + XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3282, + XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3283, + XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3284, + XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3285, + XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3286, + XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3287, + XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3288, + XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3289, + XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq=3290, + XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq=3291, + XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3292, + XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3293, + XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3294, + XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3295, + XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq=3296, + XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq=3297, + XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3298, + XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3299, + XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3300, + XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3301, + XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3302, + XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3303, + XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3304, + XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3305, + XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3306, + XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3307, + XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3308, + XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3309, + XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3310, + XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3311, + XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3312, + XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3313, + XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3314, + XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3315, + XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3316, + XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3317, + XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3318, + XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3319, + XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3320, + XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3321, + XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3322, + XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3323, + XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq=3324, + XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq=3325, + XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq=3326, + XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd=3327, + XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd=3328, + XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd=3329, + XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3330, + XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3331, + XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512=3332, + XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512=3333, + XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512=3334, + XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512=3335, + XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512=3336, + XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512=3337, + XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq=3338, + XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq=3339, + XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3340, + XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3341, + XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3342, + XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3343, + XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq=3344, + XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq=3345, + XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3346, + XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3347, + XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3348, + XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3349, + XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3350, + XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3351, + XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3352, + XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3353, + XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq=3354, + XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq=3355, + XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3356, + XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3357, + XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3358, + XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3359, + XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq=3360, + XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq=3361, + XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3362, + XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3363, + XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq=3364, + XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq=3365, + XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3366, + XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3367, + XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3368, + XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3369, + XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd=3370, + XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd=3371, + XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3372, + XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3373, + XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq=3374, + XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq=3375, + XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3376, + XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3377, + XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3378, + XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3379, + XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq=3380, + XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq=3381, + XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3382, + XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3383, + XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3384, + XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3385, + XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3386, + XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3387, + XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3388, + XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3389, + XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq=3390, + XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq=3391, + XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3392, + XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3393, + XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3394, + XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3395, + XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq=3396, + XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq=3397, + XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3398, + XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3399, + XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq=3400, + XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq=3401, + XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3402, + XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3403, + XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3404, + XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3405, + XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd=3406, + XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd=3407, + XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3408, + XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3409, + XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq=3410, + XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq=3411, + XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3412, + XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3413, + XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3414, + XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3415, + XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq=3416, + XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq=3417, + XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3418, + XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3419, + XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3420, + XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3421, + XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3422, + XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3423, + XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3424, + XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3425, + XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq=3426, + XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq=3427, + XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3428, + XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3429, + XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3430, + XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3431, + XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq=3432, + XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq=3433, + XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3434, + XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3435, + XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq=3436, + XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq=3437, + XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3438, + XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3439, + XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3440, + XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3441, + XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd=3442, + XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd=3443, + XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3444, + XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3445, + XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq=3446, + XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq=3447, + XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq=3448, + XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq=3449, + XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq=3450, + XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq=3451, + XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq=3452, + XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq=3453, + XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq=3454, + XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq=3455, + XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq=3456, + XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq=3457, + XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq=3458, + XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq=3459, + XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq=3460, + XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd=3461, + XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd=3462, + XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd=3463, + XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq=3464, + XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq=3465, + XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3466, + XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3467, + XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3468, + XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3469, + XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq=3470, + XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq=3471, + XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3472, + XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3473, + XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3474, + XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3475, + XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3476, + XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3477, + XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3478, + XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3479, + XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq=3480, + XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq=3481, + XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3482, + XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3483, + XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3484, + XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3485, + XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq=3486, + XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq=3487, + XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3488, + XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3489, + XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq=3490, + XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq=3491, + XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3492, + XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3493, + XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3494, + XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3495, + XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd=3496, + XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd=3497, + XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3498, + XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3499, + XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq=3500, + XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq=3501, + XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3502, + XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3503, + XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3504, + XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3505, + XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq=3506, + XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq=3507, + XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3508, + XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3509, + XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3510, + XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3511, + XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3512, + XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3513, + XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3514, + XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3515, + XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq=3516, + XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq=3517, + XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3518, + XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3519, + XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3520, + XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3521, + XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq=3522, + XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq=3523, + XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3524, + XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3525, + XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq=3526, + XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq=3527, + XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3528, + XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3529, + XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3530, + XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3531, + XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd=3532, + XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd=3533, + XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3534, + XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3535, + XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq=3536, + XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq=3537, + XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3538, + XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3539, + XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3540, + XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3541, + XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq=3542, + XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq=3543, + XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3544, + XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3545, + XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3546, + XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3547, + XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3548, + XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3549, + XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3550, + XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3551, + XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq=3552, + XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq=3553, + XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3554, + XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3555, + XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3556, + XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3557, + XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq=3558, + XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq=3559, + XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3560, + XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3561, + XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq=3562, + XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq=3563, + XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3564, + XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3565, + XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3566, + XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3567, + XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd=3568, + XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd=3569, + XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3570, + XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3571, + XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq=3572, + XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq=3573, + XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq=3574, + XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq=3575, + XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq=3576, + XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq=3577, + XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq=3578, + XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq=3579, + XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq=3580, + XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq=3581, + XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq=3582, + XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq=3583, + XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq=3584, + XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq=3585, + XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq=3586, + XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd=3587, + XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd=3588, + XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd=3589, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128=3590, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256=3591, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512=3592, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3593, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512=3594, + XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512=3595, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128=3596, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256=3597, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512=3598, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512=3599, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512=3600, + XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512=3601, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128=3602, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256=3603, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512=3604, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3605, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512=3606, + XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512=3607, + XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512=3608, + XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512=3609, + XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512=3610, + XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512=3611, + XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512=3612, + XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512=3613, + XED_IFORM_VFRCZPD_XMMdq_MEMdq=3614, + XED_IFORM_VFRCZPD_XMMdq_XMMdq=3615, + XED_IFORM_VFRCZPD_YMMqq_MEMqq=3616, + XED_IFORM_VFRCZPD_YMMqq_YMMqq=3617, + XED_IFORM_VFRCZPS_XMMdq_MEMdq=3618, + XED_IFORM_VFRCZPS_XMMdq_XMMdq=3619, + XED_IFORM_VFRCZPS_YMMqq_MEMqq=3620, + XED_IFORM_VFRCZPS_YMMqq_YMMqq=3621, + XED_IFORM_VFRCZSD_XMMdq_MEMq=3622, + XED_IFORM_VFRCZSD_XMMdq_XMMq=3623, + XED_IFORM_VFRCZSS_XMMdq_MEMd=3624, + XED_IFORM_VFRCZSS_XMMdq_XMMd=3625, + XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3626, + XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128=3627, + XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3628, + XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256=3629, + XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3630, + XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3631, + XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128=3632, + XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256=3633, + XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256=3634, + XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512=3635, + XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=3636, + XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=3637, + XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=3638, + XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=3639, + XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=3640, + XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=3641, + XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=3642, + XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=3643, + XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128=3644, + XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128=3645, + XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256=3646, + XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256=3647, + XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512=3648, + XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128=3649, + XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256=3650, + XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128=3651, + XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256=3652, + XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512=3653, + XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512=3654, + XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512=3655, + XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512=3656, + XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512=3657, + XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512=3658, + XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3659, + XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512=3660, + XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512=3661, + XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512=3662, + XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512=3663, + XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512=3664, + XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512=3665, + XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512=3666, + XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512=3667, + XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512=3668, + XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512=3669, + XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512=3670, + XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3671, + XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3672, + XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3673, + XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3674, + XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3675, + XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3676, + XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3677, + XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=3678, + XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=3679, + XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=3680, + XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=3681, + XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=3682, + XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=3683, + XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=3684, + XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=3685, + XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=3686, + XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=3687, + XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=3688, + XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=3689, + XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=3690, + XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=3691, + XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=3692, + XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=3693, + XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=3694, + XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=3695, + XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=3696, + XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=3697, + XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=3698, + XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=3699, + XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=3700, + XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=3701, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3702, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3703, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8=3704, + XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8=3705, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3706, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3707, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8=3708, + XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8=3709, + XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3710, + XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3711, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512=3712, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512=3713, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8=3714, + XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8=3715, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512=3716, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512=3717, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8=3718, + XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8=3719, + XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512=3720, + XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512=3721, + XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=3722, + XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=3723, + XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8=3724, + XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8=3725, + XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=3726, + XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=3727, + XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8=3728, + XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8=3729, + XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=3730, + XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=3731, + XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq=3732, + XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq=3733, + XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq=3734, + XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq=3735, + XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq=3736, + XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq=3737, + XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq=3738, + XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq=3739, + XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq=3740, + XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq=3741, + XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq=3742, + XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq=3743, + XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq=3744, + XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq=3745, + XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq=3746, + XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq=3747, + XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb=3748, + XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb=3749, + XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=3750, + XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512=3751, + XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3752, + XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512=3753, + XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=3754, + XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512=3755, + XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=3756, + XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512=3757, + XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3758, + XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512=3759, + XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=3760, + XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512=3761, + XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb=3762, + XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb=3763, + XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=3764, + XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512=3765, + XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3766, + XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512=3767, + XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=3768, + XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512=3769, + XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=3770, + XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512=3771, + XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3772, + XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512=3773, + XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=3774, + XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512=3775, + XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb=3776, + XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb=3777, + XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512=3778, + XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512=3779, + XED_IFORM_VLDDQU_XMMdq_MEMdq=3780, + XED_IFORM_VLDDQU_YMMqq_MEMqq=3781, + XED_IFORM_VLDMXCSR_MEMd=3782, + XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq=3783, + XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq=3784, + XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq=3785, + XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq=3786, + XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq=3787, + XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq=3788, + XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq=3789, + XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq=3790, + XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq=3791, + XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq=3792, + XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq=3793, + XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3794, + XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3795, + XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3796, + XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3797, + XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq=3798, + XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq=3799, + XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3800, + XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3801, + XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3802, + XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3803, + XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3804, + XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3805, + XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3806, + XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3807, + XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq=3808, + XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq=3809, + XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3810, + XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3811, + XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3812, + XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3813, + XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq=3814, + XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq=3815, + XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3816, + XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3817, + XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq=3818, + XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq=3819, + XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3820, + XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3821, + XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3822, + XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3823, + XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd=3824, + XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd=3825, + XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3826, + XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3827, + XED_IFORM_VMCALL=3828, + XED_IFORM_VMCLEAR_MEMq=3829, + XED_IFORM_VMFUNC=3830, + XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq=3831, + XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq=3832, + XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3833, + XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3834, + XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=3835, + XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=3836, + XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq=3837, + XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq=3838, + XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=3839, + XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=3840, + XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3841, + XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3842, + XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=3843, + XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=3844, + XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=3845, + XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=3846, + XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq=3847, + XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq=3848, + XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3849, + XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3850, + XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=3851, + XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=3852, + XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq=3853, + XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq=3854, + XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=3855, + XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=3856, + XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq=3857, + XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq=3858, + XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=3859, + XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=3860, + XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=3861, + XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=3862, + XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd=3863, + XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd=3864, + XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=3865, + XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=3866, + XED_IFORM_VMLAUNCH=3867, + XED_IFORM_VMLOAD_ArAX=3868, + XED_IFORM_VMMCALL=3869, + XED_IFORM_VMOVAPD_MEMdq_XMMdq=3870, + XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512=3871, + XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512=3872, + XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512=3873, + XED_IFORM_VMOVAPD_MEMqq_YMMqq=3874, + XED_IFORM_VMOVAPD_XMMdq_MEMdq=3875, + XED_IFORM_VMOVAPD_XMMdq_XMMdq_28=3876, + XED_IFORM_VMOVAPD_XMMdq_XMMdq_29=3877, + XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512=3878, + XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512=3879, + XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512=3880, + XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512=3881, + XED_IFORM_VMOVAPD_YMMqq_MEMqq=3882, + XED_IFORM_VMOVAPD_YMMqq_YMMqq_28=3883, + XED_IFORM_VMOVAPD_YMMqq_YMMqq_29=3884, + XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512=3885, + XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512=3886, + XED_IFORM_VMOVAPS_MEMdq_XMMdq=3887, + XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512=3888, + XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512=3889, + XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512=3890, + XED_IFORM_VMOVAPS_MEMqq_YMMqq=3891, + XED_IFORM_VMOVAPS_XMMdq_MEMdq=3892, + XED_IFORM_VMOVAPS_XMMdq_XMMdq_28=3893, + XED_IFORM_VMOVAPS_XMMdq_XMMdq_29=3894, + XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512=3895, + XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512=3896, + XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512=3897, + XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512=3898, + XED_IFORM_VMOVAPS_YMMqq_MEMqq=3899, + XED_IFORM_VMOVAPS_YMMqq_YMMqq_28=3900, + XED_IFORM_VMOVAPS_YMMqq_YMMqq_29=3901, + XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512=3902, + XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512=3903, + XED_IFORM_VMOVD_GPR32d_XMMd=3904, + XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512=3905, + XED_IFORM_VMOVD_MEMd_XMMd=3906, + XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512=3907, + XED_IFORM_VMOVD_XMMdq_GPR32d=3908, + XED_IFORM_VMOVD_XMMdq_MEMd=3909, + XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512=3910, + XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512=3911, + XED_IFORM_VMOVDDUP_XMMdq_MEMq=3912, + XED_IFORM_VMOVDDUP_XMMdq_XMMq=3913, + XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512=3914, + XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512=3915, + XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512=3916, + XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512=3917, + XED_IFORM_VMOVDDUP_YMMqq_MEMqq=3918, + XED_IFORM_VMOVDDUP_YMMqq_YMMqq=3919, + XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512=3920, + XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512=3921, + XED_IFORM_VMOVDQA_MEMdq_XMMdq=3922, + XED_IFORM_VMOVDQA_MEMqq_YMMqq=3923, + XED_IFORM_VMOVDQA_XMMdq_MEMdq=3924, + XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F=3925, + XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F=3926, + XED_IFORM_VMOVDQA_YMMqq_MEMqq=3927, + XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F=3928, + XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F=3929, + XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512=3930, + XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512=3931, + XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512=3932, + XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512=3933, + XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512=3934, + XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512=3935, + XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512=3936, + XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512=3937, + XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512=3938, + XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512=3939, + XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512=3940, + XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512=3941, + XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512=3942, + XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512=3943, + XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512=3944, + XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512=3945, + XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512=3946, + XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512=3947, + XED_IFORM_VMOVDQU_MEMdq_XMMdq=3948, + XED_IFORM_VMOVDQU_MEMqq_YMMqq=3949, + XED_IFORM_VMOVDQU_XMMdq_MEMdq=3950, + XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F=3951, + XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F=3952, + XED_IFORM_VMOVDQU_YMMqq_MEMqq=3953, + XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F=3954, + XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F=3955, + XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512=3956, + XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512=3957, + XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512=3958, + XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512=3959, + XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512=3960, + XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512=3961, + XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512=3962, + XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512=3963, + XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512=3964, + XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512=3965, + XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512=3966, + XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512=3967, + XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512=3968, + XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512=3969, + XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512=3970, + XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512=3971, + XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512=3972, + XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512=3973, + XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512=3974, + XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512=3975, + XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512=3976, + XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512=3977, + XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512=3978, + XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512=3979, + XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512=3980, + XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512=3981, + XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512=3982, + XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512=3983, + XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512=3984, + XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512=3985, + XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512=3986, + XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512=3987, + XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512=3988, + XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512=3989, + XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512=3990, + XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512=3991, + XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq=3992, + XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512=3993, + XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512=3994, + XED_IFORM_VMOVHPD_MEMq_XMMdq=3995, + XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq=3996, + XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512=3997, + XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512=3998, + XED_IFORM_VMOVHPS_MEMq_XMMdq=3999, + XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq=4000, + XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512=4001, + XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq=4002, + XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512=4003, + XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512=4004, + XED_IFORM_VMOVLPD_MEMq_XMMq=4005, + XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq=4006, + XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512=4007, + XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512=4008, + XED_IFORM_VMOVLPS_MEMq_XMMq=4009, + XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq=4010, + XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512=4011, + XED_IFORM_VMOVMSKPD_GPR32d_XMMdq=4012, + XED_IFORM_VMOVMSKPD_GPR32d_YMMqq=4013, + XED_IFORM_VMOVMSKPS_GPR32d_XMMdq=4014, + XED_IFORM_VMOVMSKPS_GPR32d_YMMqq=4015, + XED_IFORM_VMOVNTDQ_MEMdq_XMMdq=4016, + XED_IFORM_VMOVNTDQ_MEMqq_YMMqq=4017, + XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512=4018, + XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512=4019, + XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512=4020, + XED_IFORM_VMOVNTDQA_XMMdq_MEMdq=4021, + XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512=4022, + XED_IFORM_VMOVNTDQA_YMMqq_MEMqq=4023, + XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512=4024, + XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512=4025, + XED_IFORM_VMOVNTPD_MEMdq_XMMdq=4026, + XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512=4027, + XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512=4028, + XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512=4029, + XED_IFORM_VMOVNTPD_MEMqq_YMMqq=4030, + XED_IFORM_VMOVNTPS_MEMdq_XMMdq=4031, + XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512=4032, + XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512=4033, + XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512=4034, + XED_IFORM_VMOVNTPS_MEMqq_YMMqq=4035, + XED_IFORM_VMOVQ_GPR64q_XMMq=4036, + XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512=4037, + XED_IFORM_VMOVQ_MEMq_XMMq_7E=4038, + XED_IFORM_VMOVQ_MEMq_XMMq_D6=4039, + XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512=4040, + XED_IFORM_VMOVQ_XMMdq_GPR64q=4041, + XED_IFORM_VMOVQ_XMMdq_MEMq_6E=4042, + XED_IFORM_VMOVQ_XMMdq_MEMq_7E=4043, + XED_IFORM_VMOVQ_XMMdq_XMMq_7E=4044, + XED_IFORM_VMOVQ_XMMdq_XMMq_D6=4045, + XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512=4046, + XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512=4047, + XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512=4048, + XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512=4049, + XED_IFORM_VMOVSD_MEMq_XMMq=4050, + XED_IFORM_VMOVSD_XMMdq_MEMq=4051, + XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10=4052, + XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11=4053, + XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512=4054, + XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4055, + XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512=4056, + XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512=4057, + XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4058, + XED_IFORM_VMOVSHDUP_XMMdq_MEMdq=4059, + XED_IFORM_VMOVSHDUP_XMMdq_XMMdq=4060, + XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512=4061, + XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512=4062, + XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512=4063, + XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512=4064, + XED_IFORM_VMOVSHDUP_YMMqq_MEMqq=4065, + XED_IFORM_VMOVSHDUP_YMMqq_YMMqq=4066, + XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512=4067, + XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=4068, + XED_IFORM_VMOVSLDUP_XMMdq_MEMdq=4069, + XED_IFORM_VMOVSLDUP_XMMdq_XMMdq=4070, + XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512=4071, + XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512=4072, + XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512=4073, + XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512=4074, + XED_IFORM_VMOVSLDUP_YMMqq_MEMqq=4075, + XED_IFORM_VMOVSLDUP_YMMqq_YMMqq=4076, + XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512=4077, + XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512=4078, + XED_IFORM_VMOVSS_MEMd_XMMd=4079, + XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512=4080, + XED_IFORM_VMOVSS_XMMdq_MEMd=4081, + XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10=4082, + XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11=4083, + XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512=4084, + XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4085, + XED_IFORM_VMOVUPD_MEMdq_XMMdq=4086, + XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512=4087, + XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512=4088, + XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512=4089, + XED_IFORM_VMOVUPD_MEMqq_YMMqq=4090, + XED_IFORM_VMOVUPD_XMMdq_MEMdq=4091, + XED_IFORM_VMOVUPD_XMMdq_XMMdq_10=4092, + XED_IFORM_VMOVUPD_XMMdq_XMMdq_11=4093, + XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512=4094, + XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512=4095, + XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512=4096, + XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512=4097, + XED_IFORM_VMOVUPD_YMMqq_MEMqq=4098, + XED_IFORM_VMOVUPD_YMMqq_YMMqq_10=4099, + XED_IFORM_VMOVUPD_YMMqq_YMMqq_11=4100, + XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512=4101, + XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512=4102, + XED_IFORM_VMOVUPS_MEMdq_XMMdq=4103, + XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512=4104, + XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512=4105, + XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512=4106, + XED_IFORM_VMOVUPS_MEMqq_YMMqq=4107, + XED_IFORM_VMOVUPS_XMMdq_MEMdq=4108, + XED_IFORM_VMOVUPS_XMMdq_XMMdq_10=4109, + XED_IFORM_VMOVUPS_XMMdq_XMMdq_11=4110, + XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512=4111, + XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512=4112, + XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512=4113, + XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512=4114, + XED_IFORM_VMOVUPS_YMMqq_MEMqq=4115, + XED_IFORM_VMOVUPS_YMMqq_YMMqq_10=4116, + XED_IFORM_VMOVUPS_YMMqq_YMMqq_11=4117, + XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512=4118, + XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512=4119, + XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512=4120, + XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512=4121, + XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512=4122, + XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512=4123, + XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb=4124, + XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb=4125, + XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb=4126, + XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb=4127, + XED_IFORM_VMPTRLD_MEMq=4128, + XED_IFORM_VMPTRST_MEMq=4129, + XED_IFORM_VMREAD_GPR32_GPR32=4130, + XED_IFORM_VMREAD_GPR64_GPR64=4131, + XED_IFORM_VMREAD_MEMd_GPR32=4132, + XED_IFORM_VMREAD_MEMq_GPR64=4133, + XED_IFORM_VMRESUME=4134, + XED_IFORM_VMRUN_ArAX=4135, + XED_IFORM_VMSAVE=4136, + XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq=4137, + XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq=4138, + XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4139, + XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4140, + XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4141, + XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4142, + XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq=4143, + XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq=4144, + XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4145, + XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4146, + XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=4147, + XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4148, + XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=4149, + XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=4150, + XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=4151, + XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=4152, + XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq=4153, + XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq=4154, + XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4155, + XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4156, + XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4157, + XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4158, + XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq=4159, + XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq=4160, + XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4161, + XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4162, + XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq=4163, + XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq=4164, + XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4165, + XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4166, + XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=4167, + XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=4168, + XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd=4169, + XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd=4170, + XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4171, + XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4172, + XED_IFORM_VMWRITE_GPR32_GPR32=4173, + XED_IFORM_VMWRITE_GPR32_MEMd=4174, + XED_IFORM_VMWRITE_GPR64_GPR64=4175, + XED_IFORM_VMWRITE_GPR64_MEMq=4176, + XED_IFORM_VMXOFF=4177, + XED_IFORM_VMXON_MEMq=4178, + XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq=4179, + XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq=4180, + XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4181, + XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4182, + XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq=4183, + XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq=4184, + XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4185, + XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4186, + XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4187, + XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4188, + XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq=4189, + XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq=4190, + XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4191, + XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4192, + XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq=4193, + XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq=4194, + XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4195, + XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4196, + XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4197, + XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4198, + XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512=4199, + XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512=4200, + XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512=4201, + XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512=4202, + XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512=4203, + XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512=4204, + XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512=4205, + XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512=4206, + XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512=4207, + XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512=4208, + XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512=4209, + XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512=4210, + XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4211, + XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4212, + XED_IFORM_VPABSB_XMMdq_MEMdq=4213, + XED_IFORM_VPABSB_XMMdq_XMMdq=4214, + XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512=4215, + XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512=4216, + XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512=4217, + XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512=4218, + XED_IFORM_VPABSB_YMMqq_MEMqq=4219, + XED_IFORM_VPABSB_YMMqq_YMMqq=4220, + XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512=4221, + XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512=4222, + XED_IFORM_VPABSD_XMMdq_MEMdq=4223, + XED_IFORM_VPABSD_XMMdq_XMMdq=4224, + XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512=4225, + XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512=4226, + XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512=4227, + XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512=4228, + XED_IFORM_VPABSD_YMMqq_MEMqq=4229, + XED_IFORM_VPABSD_YMMqq_YMMqq=4230, + XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512=4231, + XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512=4232, + XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512=4233, + XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512=4234, + XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512=4235, + XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512=4236, + XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512=4237, + XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512=4238, + XED_IFORM_VPABSW_XMMdq_MEMdq=4239, + XED_IFORM_VPABSW_XMMdq_XMMdq=4240, + XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512=4241, + XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512=4242, + XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512=4243, + XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512=4244, + XED_IFORM_VPABSW_YMMqq_MEMqq=4245, + XED_IFORM_VPABSW_YMMqq_YMMqq=4246, + XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512=4247, + XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512=4248, + XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq=4249, + XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq=4250, + XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512=4251, + XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512=4252, + XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512=4253, + XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512=4254, + XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq=4255, + XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq=4256, + XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512=4257, + XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512=4258, + XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq=4259, + XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq=4260, + XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512=4261, + XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512=4262, + XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512=4263, + XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512=4264, + XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq=4265, + XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq=4266, + XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512=4267, + XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512=4268, + XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq=4269, + XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq=4270, + XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512=4271, + XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512=4272, + XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq=4273, + XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq=4274, + XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512=4275, + XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512=4276, + XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512=4277, + XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512=4278, + XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq=4279, + XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq=4280, + XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512=4281, + XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512=4282, + XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq=4283, + XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq=4284, + XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512=4285, + XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512=4286, + XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512=4287, + XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512=4288, + XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq=4289, + XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq=4290, + XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4291, + XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4292, + XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq=4293, + XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq=4294, + XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4295, + XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4296, + XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4297, + XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4298, + XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq=4299, + XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq=4300, + XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4301, + XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4302, + XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq=4303, + XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq=4304, + XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4305, + XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4306, + XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4307, + XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4308, + XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq=4309, + XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq=4310, + XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4311, + XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4312, + XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq=4313, + XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq=4314, + XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4315, + XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4316, + XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4317, + XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4318, + XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq=4319, + XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq=4320, + XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=4321, + XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=4322, + XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=4323, + XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=4324, + XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq=4325, + XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq=4326, + XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=4327, + XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=4328, + XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq=4329, + XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq=4330, + XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=4331, + XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=4332, + XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=4333, + XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=4334, + XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq=4335, + XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq=4336, + XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=4337, + XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=4338, + XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq=4339, + XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq=4340, + XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4341, + XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4342, + XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq=4343, + XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq=4344, + XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4345, + XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4346, + XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4347, + XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4348, + XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq=4349, + XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq=4350, + XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4351, + XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4352, + XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq=4353, + XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq=4354, + XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4355, + XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4356, + XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4357, + XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4358, + XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq=4359, + XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq=4360, + XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4361, + XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4362, + XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq=4363, + XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq=4364, + XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4365, + XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4366, + XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4367, + XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4368, + XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb=4369, + XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb=4370, + XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4371, + XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4372, + XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb=4373, + XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb=4374, + XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4375, + XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4376, + XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4377, + XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4378, + XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq=4379, + XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq=4380, + XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq=4381, + XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq=4382, + XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4383, + XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4384, + XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4385, + XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4386, + XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4387, + XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4388, + XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq=4389, + XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq=4390, + XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq=4391, + XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq=4392, + XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4393, + XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4394, + XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4395, + XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4396, + XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4397, + XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4398, + XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4399, + XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4400, + XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4401, + XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4402, + XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4403, + XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4404, + XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4405, + XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4406, + XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4407, + XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4408, + XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4409, + XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4410, + XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq=4411, + XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq=4412, + XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4413, + XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4414, + XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq=4415, + XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq=4416, + XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4417, + XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4418, + XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4419, + XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4420, + XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq=4421, + XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq=4422, + XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4423, + XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4424, + XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq=4425, + XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq=4426, + XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4427, + XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4428, + XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4429, + XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4430, + XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb=4431, + XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb=4432, + XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb=4433, + XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb=4434, + XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4435, + XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4436, + XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4437, + XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4438, + XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4439, + XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4440, + XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4441, + XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4442, + XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4443, + XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4444, + XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4445, + XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4446, + XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4447, + XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4448, + XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4449, + XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4450, + XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4451, + XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4452, + XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4453, + XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4454, + XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4455, + XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4456, + XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4457, + XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4458, + XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq=4459, + XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq=4460, + XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq=4461, + XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq=4462, + XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb=4463, + XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb=4464, + XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb=4465, + XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb=4466, + XED_IFORM_VPBROADCASTB_XMMdq_MEMb=4467, + XED_IFORM_VPBROADCASTB_XMMdq_XMMb=4468, + XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512=4469, + XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512=4470, + XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512=4471, + XED_IFORM_VPBROADCASTB_YMMqq_MEMb=4472, + XED_IFORM_VPBROADCASTB_YMMqq_XMMb=4473, + XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512=4474, + XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512=4475, + XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512=4476, + XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512=4477, + XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512=4478, + XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512=4479, + XED_IFORM_VPBROADCASTD_XMMdq_MEMd=4480, + XED_IFORM_VPBROADCASTD_XMMdq_XMMd=4481, + XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512=4482, + XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512=4483, + XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512=4484, + XED_IFORM_VPBROADCASTD_YMMqq_MEMd=4485, + XED_IFORM_VPBROADCASTD_YMMqq_XMMd=4486, + XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512=4487, + XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512=4488, + XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512=4489, + XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512=4490, + XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512=4491, + XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512=4492, + XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512=4493, + XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512=4494, + XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD=4495, + XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512=4496, + XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512=4497, + XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD=4498, + XED_IFORM_VPBROADCASTQ_XMMdq_MEMq=4499, + XED_IFORM_VPBROADCASTQ_XMMdq_XMMq=4500, + XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512=4501, + XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512=4502, + XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512=4503, + XED_IFORM_VPBROADCASTQ_YMMqq_MEMq=4504, + XED_IFORM_VPBROADCASTQ_YMMqq_XMMq=4505, + XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512=4506, + XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512=4507, + XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512=4508, + XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512=4509, + XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512=4510, + XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512=4511, + XED_IFORM_VPBROADCASTW_XMMdq_MEMw=4512, + XED_IFORM_VPBROADCASTW_XMMdq_XMMw=4513, + XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512=4514, + XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512=4515, + XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512=4516, + XED_IFORM_VPBROADCASTW_YMMqq_MEMw=4517, + XED_IFORM_VPBROADCASTW_YMMqq_XMMw=4518, + XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512=4519, + XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512=4520, + XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512=4521, + XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512=4522, + XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512=4523, + XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512=4524, + XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb=4525, + XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb=4526, + XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512=4527, + XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512=4528, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8=4529, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512=4530, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8=4531, + XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512=4532, + XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512=4533, + XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512=4534, + XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq=4535, + XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq=4536, + XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq=4537, + XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq=4538, + XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq=4539, + XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq=4540, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512=4541, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512=4542, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512=4543, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512=4544, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512=4545, + XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512=4546, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512=4547, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512=4548, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512=4549, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512=4550, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512=4551, + XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512=4552, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4553, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4554, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4555, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4556, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4557, + XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4558, + XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq=4559, + XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq=4560, + XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq=4561, + XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq=4562, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=4563, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=4564, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=4565, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=4566, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=4567, + XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=4568, + XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq=4569, + XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq=4570, + XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq=4571, + XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq=4572, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=4573, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=4574, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=4575, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=4576, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=4577, + XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=4578, + XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq=4579, + XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq=4580, + XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq=4581, + XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq=4582, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4583, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4584, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4585, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4586, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4587, + XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4588, + XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq=4589, + XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq=4590, + XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq=4591, + XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq=4592, + XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb=4593, + XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb=4594, + XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb=4595, + XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb=4596, + XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb=4597, + XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb=4598, + XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb=4599, + XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb=4600, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=4601, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=4602, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=4603, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=4604, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=4605, + XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=4606, + XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq=4607, + XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq=4608, + XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq=4609, + XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq=4610, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512=4611, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512=4612, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512=4613, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512=4614, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512=4615, + XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512=4616, + XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq=4617, + XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq=4618, + XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq=4619, + XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq=4620, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512=4621, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512=4622, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512=4623, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512=4624, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512=4625, + XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512=4626, + XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq=4627, + XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq=4628, + XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq=4629, + XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq=4630, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=4631, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=4632, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=4633, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=4634, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=4635, + XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=4636, + XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq=4637, + XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq=4638, + XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq=4639, + XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq=4640, + XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb=4641, + XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb=4642, + XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb=4643, + XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb=4644, + XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb=4645, + XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb=4646, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512=4647, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512=4648, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512=4649, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512=4650, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512=4651, + XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512=4652, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512=4653, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512=4654, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512=4655, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512=4656, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512=4657, + XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512=4658, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=4659, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=4660, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=4661, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=4662, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=4663, + XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=4664, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=4665, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=4666, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=4667, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=4668, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=4669, + XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=4670, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=4671, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=4672, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=4673, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=4674, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=4675, + XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=4676, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512=4677, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512=4678, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512=4679, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512=4680, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512=4681, + XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512=4682, + XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb=4683, + XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb=4684, + XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb=4685, + XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb=4686, + XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512=4687, + XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512=4688, + XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512=4689, + XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512=4690, + XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512=4691, + XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512=4692, + XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512=4693, + XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512=4694, + XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512=4695, + XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512=4696, + XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512=4697, + XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512=4698, + XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512=4699, + XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512=4700, + XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512=4701, + XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512=4702, + XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512=4703, + XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4704, + XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512=4705, + XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512=4706, + XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512=4707, + XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512=4708, + XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512=4709, + XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512=4710, + XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb=4711, + XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb=4712, + XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb=4713, + XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb=4714, + XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb=4715, + XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb=4716, + XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb=4717, + XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb=4718, + XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb=4719, + XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb=4720, + XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb=4721, + XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb=4722, + XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512=4723, + XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512=4724, + XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512=4725, + XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512=4726, + XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=4727, + XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=4728, + XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512=4729, + XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512=4730, + XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512=4731, + XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512=4732, + XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=4733, + XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=4734, + XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4735, + XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4736, + XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32=4737, + XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32=4738, + XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4739, + XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4740, + XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32=4741, + XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32=4742, + XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4743, + XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4744, + XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512=4745, + XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512=4746, + XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32=4747, + XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32=4748, + XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512=4749, + XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512=4750, + XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32=4751, + XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32=4752, + XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512=4753, + XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512=4754, + XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4755, + XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4756, + XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32=4757, + XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32=4758, + XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4759, + XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4760, + XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32=4761, + XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32=4762, + XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4763, + XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4764, + XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512=4765, + XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512=4766, + XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32=4767, + XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32=4768, + XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512=4769, + XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512=4770, + XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32=4771, + XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32=4772, + XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512=4773, + XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512=4774, + XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb=4775, + XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb=4776, + XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb=4777, + XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb=4778, + XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4779, + XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4780, + XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4781, + XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4782, + XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4783, + XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4784, + XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq=4785, + XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq=4786, + XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4787, + XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4788, + XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4789, + XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4790, + XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4791, + XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4792, + XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4793, + XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4794, + XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4795, + XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4796, + XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4797, + XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4798, + XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4799, + XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4800, + XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4801, + XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4802, + XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4803, + XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4804, + XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4805, + XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4806, + XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4807, + XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4808, + XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4809, + XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4810, + XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4811, + XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4812, + XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4813, + XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4814, + XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4815, + XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4816, + XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4817, + XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4818, + XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4819, + XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4820, + XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4821, + XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4822, + XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4823, + XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4824, + XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4825, + XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4826, + XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4827, + XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4828, + XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4829, + XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4830, + XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4831, + XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4832, + XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb=4833, + XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb=4834, + XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb=4835, + XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb=4836, + XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb=4837, + XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb=4838, + XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb=4839, + XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb=4840, + XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq=4841, + XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq=4842, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=4843, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=4844, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4845, + XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4846, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4847, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4848, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4849, + XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4850, + XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb=4851, + XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb=4852, + XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq=4853, + XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq=4854, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4855, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4856, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4857, + XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4858, + XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb=4859, + XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb=4860, + XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq=4861, + XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq=4862, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=4863, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=4864, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4865, + XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4866, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=4867, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=4868, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4869, + XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4870, + XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb=4871, + XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb=4872, + XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq=4873, + XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq=4874, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=4875, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=4876, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4877, + XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4878, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=4879, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=4880, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4881, + XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4882, + XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb=4883, + XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb=4884, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=4885, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=4886, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4887, + XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4888, + XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4889, + XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4890, + XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq=4891, + XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq=4892, + XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4893, + XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4894, + XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb=4895, + XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb=4896, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=4897, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=4898, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4899, + XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4900, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=4901, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=4902, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4903, + XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4904, + XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=4905, + XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=4906, + XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=4907, + XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=4908, + XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=4909, + XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=4910, + XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=4911, + XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=4912, + XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=4913, + XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=4914, + XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=4915, + XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=4916, + XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=4917, + XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=4918, + XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=4919, + XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=4920, + XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=4921, + XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=4922, + XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=4923, + XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=4924, + XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=4925, + XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=4926, + XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=4927, + XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=4928, + XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=4929, + XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=4930, + XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=4931, + XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=4932, + XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=4933, + XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=4934, + XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4935, + XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4936, + XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4937, + XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4938, + XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4939, + XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4940, + XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=4941, + XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=4942, + XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=4943, + XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=4944, + XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=4945, + XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=4946, + XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512=4947, + XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512=4948, + XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512=4949, + XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512=4950, + XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512=4951, + XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512=4952, + XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512=4953, + XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512=4954, + XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512=4955, + XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512=4956, + XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512=4957, + XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512=4958, + XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512=4959, + XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512=4960, + XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512=4961, + XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512=4962, + XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512=4963, + XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512=4964, + XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512=4965, + XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512=4966, + XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512=4967, + XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512=4968, + XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512=4969, + XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512=4970, + XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb=4971, + XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512=4972, + XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb=4973, + XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512=4974, + XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb=4975, + XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512=4976, + XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb=4977, + XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512=4978, + XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb=4979, + XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512=4980, + XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb=4981, + XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512=4982, + XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15=4983, + XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5=4984, + XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512=4985, + XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512=4986, + XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb=4987, + XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5=4988, + XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4989, + XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128=4990, + XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256=4991, + XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256=4992, + XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512=4993, + XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=4994, + XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128=4995, + XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=4996, + XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256=4997, + XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=4998, + XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128=4999, + XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256=5000, + XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128=5001, + XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256=5002, + XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512=5003, + XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128=5004, + XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128=5005, + XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256=5006, + XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256=5007, + XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512=5008, + XED_IFORM_VPHADDBD_XMMdq_MEMdq=5009, + XED_IFORM_VPHADDBD_XMMdq_XMMdq=5010, + XED_IFORM_VPHADDBQ_XMMdq_MEMdq=5011, + XED_IFORM_VPHADDBQ_XMMdq_XMMdq=5012, + XED_IFORM_VPHADDBW_XMMdq_MEMdq=5013, + XED_IFORM_VPHADDBW_XMMdq_XMMdq=5014, + XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq=5015, + XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq=5016, + XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq=5017, + XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq=5018, + XED_IFORM_VPHADDDQ_XMMdq_MEMdq=5019, + XED_IFORM_VPHADDDQ_XMMdq_XMMdq=5020, + XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq=5021, + XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq=5022, + XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq=5023, + XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq=5024, + XED_IFORM_VPHADDUBD_XMMdq_MEMdq=5025, + XED_IFORM_VPHADDUBD_XMMdq_XMMdq=5026, + XED_IFORM_VPHADDUBQ_XMMdq_MEMdq=5027, + XED_IFORM_VPHADDUBQ_XMMdq_XMMdq=5028, + XED_IFORM_VPHADDUBW_XMMdq_MEMdq=5029, + XED_IFORM_VPHADDUBW_XMMdq_XMMdq=5030, + XED_IFORM_VPHADDUDQ_XMMdq_MEMdq=5031, + XED_IFORM_VPHADDUDQ_XMMdq_XMMdq=5032, + XED_IFORM_VPHADDUWD_XMMdq_MEMdq=5033, + XED_IFORM_VPHADDUWD_XMMdq_XMMdq=5034, + XED_IFORM_VPHADDUWQ_XMMdq_MEMdq=5035, + XED_IFORM_VPHADDUWQ_XMMdq_XMMdq=5036, + XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq=5037, + XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq=5038, + XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq=5039, + XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq=5040, + XED_IFORM_VPHADDWD_XMMdq_MEMdq=5041, + XED_IFORM_VPHADDWD_XMMdq_XMMdq=5042, + XED_IFORM_VPHADDWQ_XMMdq_MEMdq=5043, + XED_IFORM_VPHADDWQ_XMMdq_XMMdq=5044, + XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq=5045, + XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq=5046, + XED_IFORM_VPHSUBBW_XMMdq_MEMdq=5047, + XED_IFORM_VPHSUBBW_XMMdq_XMMdq=5048, + XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq=5049, + XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq=5050, + XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq=5051, + XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq=5052, + XED_IFORM_VPHSUBDQ_XMMdq_MEMdq=5053, + XED_IFORM_VPHSUBDQ_XMMdq_XMMdq=5054, + XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq=5055, + XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq=5056, + XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq=5057, + XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq=5058, + XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq=5059, + XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq=5060, + XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq=5061, + XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq=5062, + XED_IFORM_VPHSUBWD_XMMdq_MEMdq=5063, + XED_IFORM_VPHSUBWD_XMMdq_XMMdq=5064, + XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb=5065, + XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb=5066, + XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512=5067, + XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512=5068, + XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb=5069, + XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb=5070, + XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512=5071, + XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512=5072, + XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb=5073, + XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb=5074, + XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512=5075, + XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512=5076, + XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb=5077, + XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb=5078, + XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512=5079, + XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512=5080, + XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5081, + XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5082, + XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5083, + XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5084, + XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD=5085, + XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD=5086, + XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5087, + XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5088, + XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5089, + XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5090, + XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD=5091, + XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD=5092, + XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq=5093, + XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq=5094, + XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq=5095, + XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq=5096, + XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq=5097, + XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq=5098, + XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq=5099, + XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq=5100, + XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq=5101, + XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq=5102, + XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq=5103, + XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq=5104, + XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq=5105, + XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq=5106, + XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq=5107, + XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq=5108, + XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq=5109, + XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq=5110, + XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq=5111, + XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq=5112, + XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq=5113, + XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq=5114, + XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq=5115, + XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq=5116, + XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5117, + XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5118, + XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5119, + XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5120, + XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5121, + XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5122, + XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5123, + XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5124, + XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5125, + XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5126, + XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5127, + XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5128, + XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq=5129, + XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq=5130, + XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5131, + XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5132, + XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5133, + XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5134, + XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq=5135, + XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq=5136, + XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5137, + XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5138, + XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq=5139, + XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq=5140, + XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512=5141, + XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512=5142, + XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512=5143, + XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512=5144, + XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq=5145, + XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq=5146, + XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512=5147, + XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512=5148, + XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq=5149, + XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq=5150, + XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq=5151, + XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq=5152, + XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq=5153, + XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq=5154, + XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq=5155, + XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq=5156, + XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq=5157, + XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq=5158, + XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5159, + XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5160, + XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5161, + XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5162, + XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq=5163, + XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq=5164, + XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5165, + XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5166, + XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq=5167, + XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq=5168, + XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=5169, + XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=5170, + XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=5171, + XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=5172, + XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq=5173, + XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq=5174, + XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=5175, + XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=5176, + XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=5177, + XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=5178, + XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=5179, + XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=5180, + XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=5181, + XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=5182, + XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq=5183, + XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq=5184, + XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5185, + XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5186, + XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5187, + XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5188, + XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq=5189, + XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq=5190, + XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5191, + XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5192, + XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq=5193, + XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq=5194, + XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5195, + XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5196, + XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq=5197, + XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq=5198, + XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5199, + XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5200, + XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5201, + XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5202, + XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq=5203, + XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq=5204, + XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5205, + XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5206, + XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq=5207, + XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq=5208, + XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5209, + XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5210, + XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5211, + XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5212, + XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5213, + XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5214, + XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5215, + XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5216, + XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5217, + XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5218, + XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq=5219, + XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq=5220, + XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5221, + XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5222, + XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq=5223, + XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq=5224, + XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5225, + XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5226, + XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5227, + XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5228, + XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq=5229, + XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq=5230, + XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=5231, + XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=5232, + XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=5233, + XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=5234, + XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq=5235, + XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq=5236, + XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=5237, + XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=5238, + XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq=5239, + XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq=5240, + XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512=5241, + XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512=5242, + XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512=5243, + XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512=5244, + XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq=5245, + XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq=5246, + XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512=5247, + XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512=5248, + XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512=5249, + XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512=5250, + XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512=5251, + XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512=5252, + XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512=5253, + XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512=5254, + XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq=5255, + XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq=5256, + XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5257, + XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5258, + XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5259, + XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5260, + XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq=5261, + XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq=5262, + XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5263, + XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5264, + XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq=5265, + XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq=5266, + XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5267, + XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5268, + XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq=5269, + XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq=5270, + XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5271, + XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5272, + XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5273, + XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5274, + XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq=5275, + XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq=5276, + XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5277, + XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5278, + XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq=5279, + XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq=5280, + XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5281, + XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5282, + XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5283, + XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5284, + XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5285, + XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5286, + XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5287, + XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5288, + XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5289, + XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5290, + XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq=5291, + XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq=5292, + XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5293, + XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5294, + XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq=5295, + XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq=5296, + XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5297, + XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5298, + XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5299, + XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5300, + XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512=5301, + XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512=5302, + XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512=5303, + XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512=5304, + XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512=5305, + XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512=5306, + XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512=5307, + XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512=5308, + XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512=5309, + XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512=5310, + XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512=5311, + XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512=5312, + XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512=5313, + XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512=5314, + XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512=5315, + XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512=5316, + XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512=5317, + XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512=5318, + XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512=5319, + XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512=5320, + XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512=5321, + XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512=5322, + XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512=5323, + XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512=5324, + XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512=5325, + XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512=5326, + XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512=5327, + XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512=5328, + XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512=5329, + XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512=5330, + XED_IFORM_VPMOVMSKB_GPR32d_XMMdq=5331, + XED_IFORM_VPMOVMSKB_GPR32d_YMMqq=5332, + XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512=5333, + XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512=5334, + XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512=5335, + XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512=5336, + XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512=5337, + XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512=5338, + XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512=5339, + XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512=5340, + XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512=5341, + XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512=5342, + XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512=5343, + XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512=5344, + XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512=5345, + XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512=5346, + XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512=5347, + XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512=5348, + XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512=5349, + XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512=5350, + XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512=5351, + XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512=5352, + XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512=5353, + XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512=5354, + XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512=5355, + XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512=5356, + XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512=5357, + XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512=5358, + XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512=5359, + XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512=5360, + XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512=5361, + XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512=5362, + XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512=5363, + XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512=5364, + XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512=5365, + XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512=5366, + XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512=5367, + XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512=5368, + XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512=5369, + XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512=5370, + XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512=5371, + XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512=5372, + XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512=5373, + XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512=5374, + XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512=5375, + XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512=5376, + XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512=5377, + XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512=5378, + XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512=5379, + XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512=5380, + XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512=5381, + XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512=5382, + XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512=5383, + XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512=5384, + XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512=5385, + XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512=5386, + XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512=5387, + XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512=5388, + XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512=5389, + XED_IFORM_VPMOVSXBD_XMMdq_MEMd=5390, + XED_IFORM_VPMOVSXBD_XMMdq_XMMd=5391, + XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512=5392, + XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512=5393, + XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512=5394, + XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512=5395, + XED_IFORM_VPMOVSXBD_YMMqq_MEMq=5396, + XED_IFORM_VPMOVSXBD_YMMqq_XMMq=5397, + XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5398, + XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5399, + XED_IFORM_VPMOVSXBQ_XMMdq_MEMw=5400, + XED_IFORM_VPMOVSXBQ_XMMdq_XMMw=5401, + XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5402, + XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5403, + XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5404, + XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5405, + XED_IFORM_VPMOVSXBQ_YMMqq_MEMd=5406, + XED_IFORM_VPMOVSXBQ_YMMqq_XMMd=5407, + XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5408, + XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5409, + XED_IFORM_VPMOVSXBW_XMMdq_MEMq=5410, + XED_IFORM_VPMOVSXBW_XMMdq_XMMq=5411, + XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512=5412, + XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512=5413, + XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512=5414, + XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512=5415, + XED_IFORM_VPMOVSXBW_YMMqq_MEMdq=5416, + XED_IFORM_VPMOVSXBW_YMMqq_XMMdq=5417, + XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5418, + XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5419, + XED_IFORM_VPMOVSXDQ_XMMdq_MEMq=5420, + XED_IFORM_VPMOVSXDQ_XMMdq_XMMq=5421, + XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5422, + XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5423, + XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5424, + XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5425, + XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq=5426, + XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq=5427, + XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5428, + XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5429, + XED_IFORM_VPMOVSXWD_XMMdq_MEMq=5430, + XED_IFORM_VPMOVSXWD_XMMdq_XMMq=5431, + XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512=5432, + XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512=5433, + XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512=5434, + XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512=5435, + XED_IFORM_VPMOVSXWD_YMMqq_MEMdq=5436, + XED_IFORM_VPMOVSXWD_YMMqq_XMMdq=5437, + XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5438, + XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5439, + XED_IFORM_VPMOVSXWQ_XMMdq_MEMd=5440, + XED_IFORM_VPMOVSXWQ_XMMdq_XMMd=5441, + XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5442, + XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5443, + XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5444, + XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5445, + XED_IFORM_VPMOVSXWQ_YMMqq_MEMq=5446, + XED_IFORM_VPMOVSXWQ_YMMqq_XMMq=5447, + XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5448, + XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5449, + XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512=5450, + XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512=5451, + XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512=5452, + XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512=5453, + XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512=5454, + XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512=5455, + XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512=5456, + XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512=5457, + XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512=5458, + XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512=5459, + XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512=5460, + XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512=5461, + XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512=5462, + XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512=5463, + XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512=5464, + XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512=5465, + XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512=5466, + XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512=5467, + XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512=5468, + XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512=5469, + XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512=5470, + XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512=5471, + XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512=5472, + XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512=5473, + XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512=5474, + XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512=5475, + XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512=5476, + XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512=5477, + XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512=5478, + XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512=5479, + XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512=5480, + XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512=5481, + XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512=5482, + XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512=5483, + XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512=5484, + XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512=5485, + XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512=5486, + XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512=5487, + XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512=5488, + XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512=5489, + XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512=5490, + XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512=5491, + XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512=5492, + XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512=5493, + XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512=5494, + XED_IFORM_VPMOVZXBD_XMMdq_MEMd=5495, + XED_IFORM_VPMOVZXBD_XMMdq_XMMd=5496, + XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512=5497, + XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512=5498, + XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512=5499, + XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512=5500, + XED_IFORM_VPMOVZXBD_YMMqq_MEMq=5501, + XED_IFORM_VPMOVZXBD_YMMqq_XMMq=5502, + XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512=5503, + XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512=5504, + XED_IFORM_VPMOVZXBQ_XMMdq_MEMw=5505, + XED_IFORM_VPMOVZXBQ_XMMdq_XMMw=5506, + XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512=5507, + XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512=5508, + XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512=5509, + XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512=5510, + XED_IFORM_VPMOVZXBQ_YMMqq_MEMd=5511, + XED_IFORM_VPMOVZXBQ_YMMqq_XMMd=5512, + XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512=5513, + XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512=5514, + XED_IFORM_VPMOVZXBW_XMMdq_MEMq=5515, + XED_IFORM_VPMOVZXBW_XMMdq_XMMq=5516, + XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512=5517, + XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512=5518, + XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512=5519, + XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512=5520, + XED_IFORM_VPMOVZXBW_YMMqq_MEMdq=5521, + XED_IFORM_VPMOVZXBW_YMMqq_XMMdq=5522, + XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512=5523, + XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512=5524, + XED_IFORM_VPMOVZXDQ_XMMdq_MEMq=5525, + XED_IFORM_VPMOVZXDQ_XMMdq_XMMq=5526, + XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512=5527, + XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512=5528, + XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512=5529, + XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512=5530, + XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq=5531, + XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq=5532, + XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512=5533, + XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512=5534, + XED_IFORM_VPMOVZXWD_XMMdq_MEMq=5535, + XED_IFORM_VPMOVZXWD_XMMdq_XMMq=5536, + XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512=5537, + XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512=5538, + XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512=5539, + XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512=5540, + XED_IFORM_VPMOVZXWD_YMMqq_MEMdq=5541, + XED_IFORM_VPMOVZXWD_YMMqq_XMMdq=5542, + XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512=5543, + XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512=5544, + XED_IFORM_VPMOVZXWQ_XMMdq_MEMd=5545, + XED_IFORM_VPMOVZXWQ_XMMdq_XMMd=5546, + XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512=5547, + XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512=5548, + XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512=5549, + XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512=5550, + XED_IFORM_VPMOVZXWQ_YMMqq_MEMq=5551, + XED_IFORM_VPMOVZXWQ_YMMqq_XMMq=5552, + XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512=5553, + XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512=5554, + XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq=5555, + XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq=5556, + XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512=5557, + XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512=5558, + XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512=5559, + XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512=5560, + XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq=5561, + XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq=5562, + XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512=5563, + XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512=5564, + XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq=5565, + XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq=5566, + XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=5567, + XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=5568, + XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=5569, + XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=5570, + XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq=5571, + XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq=5572, + XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=5573, + XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=5574, + XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq=5575, + XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq=5576, + XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5577, + XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5578, + XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq=5579, + XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq=5580, + XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5581, + XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5582, + XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5583, + XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5584, + XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq=5585, + XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq=5586, + XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5587, + XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5588, + XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq=5589, + XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq=5590, + XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5591, + XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5592, + XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5593, + XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5594, + XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq=5595, + XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq=5596, + XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5597, + XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5598, + XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq=5599, + XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq=5600, + XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5601, + XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5602, + XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5603, + XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5604, + XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5605, + XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5606, + XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5607, + XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5608, + XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5609, + XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5610, + XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq=5611, + XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq=5612, + XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5613, + XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5614, + XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq=5615, + XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq=5616, + XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5617, + XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5618, + XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5619, + XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5620, + XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512=5621, + XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512=5622, + XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512=5623, + XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512=5624, + XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512=5625, + XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512=5626, + XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq=5627, + XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq=5628, + XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512=5629, + XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512=5630, + XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq=5631, + XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq=5632, + XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512=5633, + XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512=5634, + XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512=5635, + XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512=5636, + XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512=5637, + XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512=5638, + XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512=5639, + XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512=5640, + XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512=5641, + XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512=5642, + XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512=5643, + XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512=5644, + XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512=5645, + XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512=5646, + XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512=5647, + XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512=5648, + XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512=5649, + XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512=5650, + XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512=5651, + XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512=5652, + XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512=5653, + XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512=5654, + XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512=5655, + XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512=5656, + XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512=5657, + XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512=5658, + XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512=5659, + XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512=5660, + XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq=5661, + XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq=5662, + XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq=5663, + XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq=5664, + XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5665, + XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5666, + XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5667, + XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5668, + XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5669, + XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5670, + XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5671, + XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5672, + XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5673, + XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5674, + XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5675, + XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5676, + XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq=5677, + XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq=5678, + XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq=5679, + XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5680, + XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5681, + XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5682, + XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5683, + XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5684, + XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5685, + XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5686, + XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5687, + XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5688, + XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5689, + XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5690, + XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5691, + XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5692, + XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5693, + XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5694, + XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5695, + XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5696, + XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5697, + XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5698, + XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5699, + XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5700, + XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5701, + XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5702, + XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5703, + XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5704, + XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5705, + XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5706, + XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5707, + XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5708, + XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5709, + XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5710, + XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5711, + XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5712, + XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5713, + XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5714, + XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5715, + XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5716, + XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5717, + XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5718, + XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5719, + XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5720, + XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5721, + XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5722, + XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5723, + XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5724, + XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5725, + XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5726, + XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5727, + XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb=5728, + XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq=5729, + XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb=5730, + XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq=5731, + XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq=5732, + XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb=5733, + XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq=5734, + XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb=5735, + XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq=5736, + XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq=5737, + XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb=5738, + XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq=5739, + XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb=5740, + XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq=5741, + XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq=5742, + XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb=5743, + XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq=5744, + XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb=5745, + XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq=5746, + XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq=5747, + XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq=5748, + XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq=5749, + XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512=5750, + XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512=5751, + XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq=5752, + XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq=5753, + XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512=5754, + XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512=5755, + XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512=5756, + XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512=5757, + XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5758, + XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256=5759, + XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512=5760, + XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5761, + XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5762, + XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5763, + XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128=5764, + XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256=5765, + XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512=5766, + XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128=5767, + XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256=5768, + XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512=5769, + XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq=5770, + XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq=5771, + XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq=5772, + XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq=5773, + XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq=5774, + XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq=5775, + XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq=5776, + XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq=5777, + XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq=5778, + XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq=5779, + XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq=5780, + XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq=5781, + XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq=5782, + XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq=5783, + XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq=5784, + XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq=5785, + XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq=5786, + XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq=5787, + XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5788, + XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5789, + XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5790, + XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5791, + XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5792, + XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5793, + XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5794, + XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5795, + XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5796, + XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5797, + XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5798, + XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5799, + XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5800, + XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5801, + XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5802, + XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5803, + XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5804, + XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5805, + XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5806, + XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5807, + XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5808, + XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5809, + XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5810, + XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5811, + XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5812, + XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5813, + XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5814, + XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5815, + XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5816, + XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5817, + XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5818, + XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5819, + XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5820, + XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5821, + XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5822, + XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5823, + XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq=5824, + XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq=5825, + XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq=5826, + XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq=5827, + XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq=5828, + XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq=5829, + XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=5830, + XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=5831, + XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=5832, + XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=5833, + XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=5834, + XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=5835, + XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=5836, + XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=5837, + XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=5838, + XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=5839, + XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=5840, + XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=5841, + XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5842, + XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5843, + XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5844, + XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5845, + XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5846, + XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5847, + XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5848, + XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5849, + XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5850, + XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5851, + XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5852, + XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5853, + XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5854, + XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5855, + XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5856, + XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5857, + XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5858, + XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5859, + XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512=5860, + XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512=5861, + XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512=5862, + XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512=5863, + XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512=5864, + XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512=5865, + XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq=5866, + XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq=5867, + XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=5868, + XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=5869, + XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq=5870, + XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq=5871, + XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=5872, + XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=5873, + XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=5874, + XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=5875, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512=5876, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512=5877, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512=5878, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512=5879, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512=5880, + XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512=5881, + XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb=5882, + XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb=5883, + XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5884, + XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5885, + XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb=5886, + XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb=5887, + XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5888, + XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5889, + XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5890, + XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5891, + XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb=5892, + XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb=5893, + XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5894, + XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5895, + XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb=5896, + XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb=5897, + XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5898, + XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5899, + XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5900, + XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5901, + XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb=5902, + XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb=5903, + XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5904, + XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5905, + XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb=5906, + XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb=5907, + XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=5908, + XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=5909, + XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=5910, + XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=5911, + XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq=5912, + XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq=5913, + XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq=5914, + XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq=5915, + XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq=5916, + XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq=5917, + XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq=5918, + XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq=5919, + XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq=5920, + XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq=5921, + XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq=5922, + XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq=5923, + XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb=5924, + XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq=5925, + XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq=5926, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=5927, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=5928, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5929, + XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5930, + XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb=5931, + XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq=5932, + XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq=5933, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=5934, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=5935, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5936, + XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=5937, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=5938, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=5939, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5940, + XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=5941, + XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb=5942, + XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512=5943, + XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512=5944, + XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb=5945, + XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512=5946, + XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512=5947, + XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512=5948, + XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512=5949, + XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb=5950, + XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq=5951, + XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq=5952, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=5953, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=5954, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5955, + XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5956, + XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb=5957, + XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq=5958, + XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq=5959, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=5960, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=5961, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5962, + XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=5963, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=5964, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=5965, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5966, + XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=5967, + XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq=5968, + XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq=5969, + XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=5970, + XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=5971, + XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq=5972, + XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq=5973, + XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=5974, + XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=5975, + XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=5976, + XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=5977, + XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq=5978, + XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq=5979, + XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=5980, + XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=5981, + XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq=5982, + XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq=5983, + XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=5984, + XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=5985, + XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=5986, + XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=5987, + XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5988, + XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=5989, + XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=5990, + XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=5991, + XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=5992, + XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=5993, + XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb=5994, + XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq=5995, + XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq=5996, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=5997, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=5998, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=5999, + XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6000, + XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb=6001, + XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq=6002, + XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq=6003, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6004, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6005, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6006, + XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6007, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6008, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6009, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6010, + XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6011, + XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb=6012, + XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq=6013, + XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq=6014, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=6015, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=6016, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6017, + XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6018, + XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb=6019, + XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq=6020, + XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq=6021, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=6022, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=6023, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6024, + XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=6025, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=6026, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=6027, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6028, + XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=6029, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=6030, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=6031, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6032, + XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6033, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=6034, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=6035, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6036, + XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=6037, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=6038, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=6039, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6040, + XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=6041, + XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq=6042, + XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq=6043, + XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6044, + XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6045, + XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq=6046, + XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq=6047, + XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6048, + XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6049, + XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6050, + XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6051, + XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6052, + XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6053, + XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6054, + XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6055, + XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6056, + XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6057, + XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6058, + XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6059, + XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6060, + XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6061, + XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6062, + XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6063, + XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb=6064, + XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq=6065, + XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq=6066, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=6067, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=6068, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6069, + XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6070, + XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb=6071, + XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq=6072, + XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq=6073, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6074, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6075, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6076, + XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6077, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6078, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6079, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6080, + XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6081, + XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb=6082, + XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq=6083, + XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq=6084, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512=6085, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512=6086, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6087, + XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6088, + XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb=6089, + XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq=6090, + XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq=6091, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512=6092, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512=6093, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6094, + XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512=6095, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512=6096, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512=6097, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6098, + XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512=6099, + XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb=6100, + XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512=6101, + XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512=6102, + XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb=6103, + XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512=6104, + XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512=6105, + XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512=6106, + XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512=6107, + XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb=6108, + XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq=6109, + XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq=6110, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512=6111, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512=6112, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6113, + XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6114, + XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb=6115, + XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq=6116, + XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq=6117, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512=6118, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512=6119, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6120, + XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512=6121, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512=6122, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512=6123, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6124, + XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512=6125, + XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq=6126, + XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq=6127, + XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6128, + XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6129, + XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq=6130, + XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq=6131, + XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6132, + XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6133, + XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6134, + XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6135, + XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq=6136, + XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq=6137, + XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6138, + XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6139, + XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq=6140, + XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq=6141, + XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6142, + XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6143, + XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6144, + XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6145, + XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6146, + XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6147, + XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6148, + XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6149, + XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6150, + XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6151, + XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb=6152, + XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq=6153, + XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq=6154, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512=6155, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512=6156, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6157, + XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6158, + XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb=6159, + XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq=6160, + XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq=6161, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512=6162, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512=6163, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6164, + XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512=6165, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512=6166, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512=6167, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6168, + XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512=6169, + XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq=6170, + XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq=6171, + XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6172, + XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6173, + XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq=6174, + XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq=6175, + XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6176, + XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6177, + XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6178, + XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6179, + XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq=6180, + XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq=6181, + XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6182, + XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6183, + XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq=6184, + XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq=6185, + XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6186, + XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6187, + XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6188, + XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6189, + XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq=6190, + XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq=6191, + XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6192, + XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6193, + XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq=6194, + XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq=6195, + XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6196, + XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6197, + XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6198, + XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6199, + XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq=6200, + XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq=6201, + XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512=6202, + XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512=6203, + XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512=6204, + XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512=6205, + XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq=6206, + XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq=6207, + XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512=6208, + XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512=6209, + XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq=6210, + XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq=6211, + XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512=6212, + XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512=6213, + XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512=6214, + XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512=6215, + XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq=6216, + XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq=6217, + XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512=6218, + XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512=6219, + XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq=6220, + XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq=6221, + XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6222, + XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6223, + XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq=6224, + XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq=6225, + XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6226, + XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6227, + XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6228, + XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6229, + XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq=6230, + XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq=6231, + XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6232, + XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6233, + XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq=6234, + XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq=6235, + XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6236, + XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6237, + XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6238, + XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6239, + XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq=6240, + XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq=6241, + XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6242, + XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6243, + XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq=6244, + XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq=6245, + XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6246, + XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6247, + XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6248, + XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6249, + XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512=6250, + XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512=6251, + XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6252, + XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6253, + XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6254, + XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6255, + XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512=6256, + XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512=6257, + XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6258, + XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6259, + XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6260, + XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6261, + XED_IFORM_VPTEST_XMMdq_MEMdq=6262, + XED_IFORM_VPTEST_XMMdq_XMMdq=6263, + XED_IFORM_VPTEST_YMMqq_MEMqq=6264, + XED_IFORM_VPTEST_YMMqq_YMMqq=6265, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=6266, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=6267, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=6268, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=6269, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=6270, + XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=6271, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=6272, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=6273, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=6274, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=6275, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=6276, + XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=6277, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=6278, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=6279, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=6280, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=6281, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=6282, + XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=6283, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=6284, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=6285, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=6286, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=6287, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=6288, + XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=6289, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512=6290, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512=6291, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512=6292, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512=6293, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512=6294, + XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512=6295, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512=6296, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512=6297, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512=6298, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512=6299, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512=6300, + XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512=6301, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512=6302, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512=6303, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512=6304, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512=6305, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512=6306, + XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512=6307, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512=6308, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512=6309, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512=6310, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512=6311, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512=6312, + XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512=6313, + XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq=6314, + XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq=6315, + XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6316, + XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6317, + XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq=6318, + XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq=6319, + XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6320, + XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6321, + XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6322, + XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6323, + XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq=6324, + XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq=6325, + XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6326, + XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6327, + XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq=6328, + XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq=6329, + XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6330, + XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6331, + XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6332, + XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6333, + XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq=6334, + XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq=6335, + XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6336, + XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6337, + XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq=6338, + XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq=6339, + XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6340, + XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6341, + XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6342, + XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6343, + XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq=6344, + XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq=6345, + XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6346, + XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6347, + XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq=6348, + XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq=6349, + XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6350, + XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6351, + XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6352, + XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6353, + XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq=6354, + XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq=6355, + XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512=6356, + XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512=6357, + XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq=6358, + XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq=6359, + XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512=6360, + XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512=6361, + XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512=6362, + XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512=6363, + XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq=6364, + XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq=6365, + XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6366, + XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6367, + XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq=6368, + XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq=6369, + XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6370, + XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6371, + XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6372, + XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6373, + XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq=6374, + XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq=6375, + XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6376, + XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6377, + XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq=6378, + XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq=6379, + XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6380, + XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6381, + XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6382, + XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6383, + XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq=6384, + XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq=6385, + XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512=6386, + XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512=6387, + XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq=6388, + XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq=6389, + XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512=6390, + XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512=6391, + XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512=6392, + XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512=6393, + XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq=6394, + XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq=6395, + XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq=6396, + XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq=6397, + XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6398, + XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6399, + XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6400, + XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6401, + XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6402, + XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6403, + XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6404, + XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6405, + XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6406, + XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6407, + XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6408, + XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6409, + XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6410, + XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6411, + XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6412, + XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6413, + XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6414, + XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6415, + XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6416, + XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6417, + XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6418, + XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6419, + XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6420, + XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6421, + XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6422, + XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6423, + XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6424, + XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6425, + XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512=6426, + XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512=6427, + XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512=6428, + XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512=6429, + XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6430, + XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6431, + XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512=6432, + XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512=6433, + XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512=6434, + XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512=6435, + XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6436, + XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6437, + XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6438, + XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6439, + XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6440, + XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6441, + XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6442, + XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6443, + XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6444, + XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6445, + XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6446, + XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6447, + XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6448, + XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6449, + XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512=6450, + XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512=6451, + XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512=6452, + XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512=6453, + XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512=6454, + XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6455, + XED_IFORM_VRCPPS_XMMdq_MEMdq=6456, + XED_IFORM_VRCPPS_XMMdq_XMMdq=6457, + XED_IFORM_VRCPPS_YMMqq_MEMqq=6458, + XED_IFORM_VRCPPS_YMMqq_YMMqq=6459, + XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6460, + XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6461, + XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd=6462, + XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd=6463, + XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6464, + XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6465, + XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6466, + XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6467, + XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6468, + XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6469, + XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=6470, + XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=6471, + XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=6472, + XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=6473, + XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=6474, + XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=6475, + XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6476, + XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6477, + XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6478, + XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6479, + XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6480, + XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6481, + XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6482, + XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6483, + XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=6484, + XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=6485, + XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6486, + XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6487, + XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512=6488, + XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512=6489, + XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512=6490, + XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512=6491, + XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512=6492, + XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512=6493, + XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512=6494, + XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512=6495, + XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512=6496, + XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512=6497, + XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512=6498, + XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512=6499, + XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512=6500, + XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512=6501, + XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512=6502, + XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512=6503, + XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512=6504, + XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512=6505, + XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6506, + XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6507, + XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512=6508, + XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512=6509, + XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6510, + XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6511, + XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb=6512, + XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb=6513, + XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb=6514, + XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb=6515, + XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb=6516, + XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb=6517, + XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb=6518, + XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb=6519, + XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb=6520, + XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb=6521, + XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb=6522, + XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb=6523, + XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512=6524, + XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512=6525, + XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512=6526, + XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512=6527, + XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512=6528, + XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512=6529, + XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512=6530, + XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512=6531, + XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512=6532, + XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512=6533, + XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512=6534, + XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512=6535, + XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6536, + XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6537, + XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6538, + XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6539, + XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER=6540, + XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER=6541, + XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER=6542, + XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER=6543, + XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER=6544, + XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER=6545, + XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER=6546, + XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER=6547, + XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512=6548, + XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512=6549, + XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512=6550, + XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512=6551, + XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512=6552, + XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6553, + XED_IFORM_VRSQRTPS_XMMdq_MEMdq=6554, + XED_IFORM_VRSQRTPS_XMMdq_XMMdq=6555, + XED_IFORM_VRSQRTPS_YMMqq_MEMqq=6556, + XED_IFORM_VRSQRTPS_YMMqq_YMMqq=6557, + XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6558, + XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6559, + XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd=6560, + XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd=6561, + XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6562, + XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6563, + XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6564, + XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6565, + XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6566, + XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6567, + XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6568, + XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6569, + XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=6570, + XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=6571, + XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=6572, + XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=6573, + XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6574, + XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6575, + XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6576, + XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6577, + XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6578, + XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6579, + XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6580, + XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6581, + XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6582, + XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6583, + XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6584, + XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6585, + XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6586, + XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6587, + XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6588, + XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6589, + XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256=6590, + XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512=6591, + XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512=6592, + XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512=6593, + XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512=6594, + XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512=6595, + XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512=6596, + XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512=6597, + XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512=6598, + XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512=6599, + XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128=6600, + XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256=6601, + XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512=6602, + XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128=6603, + XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256=6604, + XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512=6605, + XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6606, + XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6607, + XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6608, + XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6609, + XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6610, + XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6611, + XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6612, + XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6613, + XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512=6614, + XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512=6615, + XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512=6616, + XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512=6617, + XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512=6618, + XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512=6619, + XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512=6620, + XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512=6621, + XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb=6622, + XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb=6623, + XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512=6624, + XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512=6625, + XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512=6626, + XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512=6627, + XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb=6628, + XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb=6629, + XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512=6630, + XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512=6631, + XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb=6632, + XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb=6633, + XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512=6634, + XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512=6635, + XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512=6636, + XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512=6637, + XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb=6638, + XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb=6639, + XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512=6640, + XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512=6641, + XED_IFORM_VSQRTPD_XMMdq_MEMdq=6642, + XED_IFORM_VSQRTPD_XMMdq_XMMdq=6643, + XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512=6644, + XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512=6645, + XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512=6646, + XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512=6647, + XED_IFORM_VSQRTPD_YMMqq_MEMqq=6648, + XED_IFORM_VSQRTPD_YMMqq_YMMqq=6649, + XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512=6650, + XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512=6651, + XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512=6652, + XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512=6653, + XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512=6654, + XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512=6655, + XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512=6656, + XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512=6657, + XED_IFORM_VSQRTPS_XMMdq_MEMdq=6658, + XED_IFORM_VSQRTPS_XMMdq_XMMdq=6659, + XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512=6660, + XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512=6661, + XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512=6662, + XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512=6663, + XED_IFORM_VSQRTPS_YMMqq_MEMqq=6664, + XED_IFORM_VSQRTPS_YMMqq_YMMqq=6665, + XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512=6666, + XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512=6667, + XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq=6668, + XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq=6669, + XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6670, + XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6671, + XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6672, + XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6673, + XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd=6674, + XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd=6675, + XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6676, + XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6677, + XED_IFORM_VSTMXCSR_MEMd=6678, + XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq=6679, + XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq=6680, + XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6681, + XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6682, + XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6683, + XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6684, + XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq=6685, + XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq=6686, + XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6687, + XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6688, + XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6689, + XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6690, + XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512=6691, + XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512=6692, + XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512=6693, + XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512=6694, + XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq=6695, + XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq=6696, + XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6697, + XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6698, + XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6699, + XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6700, + XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq=6701, + XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq=6702, + XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6703, + XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6704, + XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq=6705, + XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq=6706, + XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6707, + XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6708, + XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512=6709, + XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512=6710, + XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd=6711, + XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd=6712, + XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6713, + XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6714, + XED_IFORM_VTESTPD_XMMdq_MEMdq=6715, + XED_IFORM_VTESTPD_XMMdq_XMMdq=6716, + XED_IFORM_VTESTPD_YMMqq_MEMqq=6717, + XED_IFORM_VTESTPD_YMMqq_YMMqq=6718, + XED_IFORM_VTESTPS_XMMdq_MEMdq=6719, + XED_IFORM_VTESTPS_XMMdq_XMMdq=6720, + XED_IFORM_VTESTPS_YMMqq_MEMqq=6721, + XED_IFORM_VTESTPS_YMMqq_YMMqq=6722, + XED_IFORM_VUCOMISD_XMMdq_MEMq=6723, + XED_IFORM_VUCOMISD_XMMdq_XMMq=6724, + XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512=6725, + XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512=6726, + XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512=6727, + XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512=6728, + XED_IFORM_VUCOMISS_XMMdq_MEMd=6729, + XED_IFORM_VUCOMISS_XMMdq_XMMd=6730, + XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512=6731, + XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512=6732, + XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq=6733, + XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq=6734, + XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6735, + XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6736, + XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6737, + XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6738, + XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq=6739, + XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq=6740, + XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6741, + XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6742, + XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq=6743, + XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq=6744, + XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6745, + XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6746, + XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6747, + XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6748, + XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq=6749, + XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq=6750, + XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6751, + XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6752, + XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq=6753, + XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq=6754, + XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512=6755, + XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512=6756, + XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512=6757, + XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512=6758, + XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq=6759, + XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq=6760, + XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512=6761, + XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512=6762, + XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq=6763, + XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq=6764, + XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512=6765, + XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512=6766, + XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512=6767, + XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512=6768, + XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq=6769, + XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq=6770, + XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512=6771, + XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512=6772, + XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq=6773, + XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq=6774, + XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512=6775, + XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512=6776, + XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq=6777, + XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq=6778, + XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512=6779, + XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512=6780, + XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512=6781, + XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512=6782, + XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq=6783, + XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq=6784, + XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512=6785, + XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512=6786, + XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq=6787, + XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq=6788, + XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512=6789, + XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512=6790, + XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512=6791, + XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512=6792, + XED_IFORM_VZEROALL=6793, + XED_IFORM_VZEROUPPER=6794, + XED_IFORM_WBINVD=6795, + XED_IFORM_WBNOINVD=6796, + XED_IFORM_WRFSBASE_GPRy=6797, + XED_IFORM_WRGSBASE_GPRy=6798, + XED_IFORM_WRMSR=6799, + XED_IFORM_WRPKRU=6800, + XED_IFORM_WRSSD_MEMu32_GPR32u32=6801, + XED_IFORM_WRSSQ_MEMu64_GPR64u64=6802, + XED_IFORM_WRUSSD_MEMu32_GPR32u32=6803, + XED_IFORM_WRUSSQ_MEMu64_GPR64u64=6804, + XED_IFORM_XABORT_IMMb=6805, + XED_IFORM_XADD_GPR8_GPR8=6806, + XED_IFORM_XADD_GPRv_GPRv=6807, + XED_IFORM_XADD_MEMb_GPR8=6808, + XED_IFORM_XADD_MEMv_GPRv=6809, + XED_IFORM_XADD_LOCK_MEMb_GPR8=6810, + XED_IFORM_XADD_LOCK_MEMv_GPRv=6811, + XED_IFORM_XBEGIN_RELBRz=6812, + XED_IFORM_XCHG_GPR8_GPR8=6813, + XED_IFORM_XCHG_GPRv_GPRv=6814, + XED_IFORM_XCHG_GPRv_OrAX=6815, + XED_IFORM_XCHG_MEMb_GPR8=6816, + XED_IFORM_XCHG_MEMv_GPRv=6817, + XED_IFORM_XEND=6818, + XED_IFORM_XGETBV=6819, + XED_IFORM_XLAT=6820, + XED_IFORM_XOR_AL_IMMb=6821, + XED_IFORM_XOR_GPR8_GPR8_30=6822, + XED_IFORM_XOR_GPR8_GPR8_32=6823, + XED_IFORM_XOR_GPR8_IMMb_80r6=6824, + XED_IFORM_XOR_GPR8_IMMb_82r6=6825, + XED_IFORM_XOR_GPR8_MEMb=6826, + XED_IFORM_XOR_GPRv_GPRv_31=6827, + XED_IFORM_XOR_GPRv_GPRv_33=6828, + XED_IFORM_XOR_GPRv_IMMb=6829, + XED_IFORM_XOR_GPRv_IMMz=6830, + XED_IFORM_XOR_GPRv_MEMv=6831, + XED_IFORM_XOR_MEMb_GPR8=6832, + XED_IFORM_XOR_MEMb_IMMb_80r6=6833, + XED_IFORM_XOR_MEMb_IMMb_82r6=6834, + XED_IFORM_XOR_MEMv_GPRv=6835, + XED_IFORM_XOR_MEMv_IMMb=6836, + XED_IFORM_XOR_MEMv_IMMz=6837, + XED_IFORM_XOR_OrAX_IMMz=6838, + XED_IFORM_XORPD_XMMxuq_MEMxuq=6839, + XED_IFORM_XORPD_XMMxuq_XMMxuq=6840, + XED_IFORM_XORPS_XMMxud_MEMxud=6841, + XED_IFORM_XORPS_XMMxud_XMMxud=6842, + XED_IFORM_XOR_LOCK_MEMb_GPR8=6843, + XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6=6844, + XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6=6845, + XED_IFORM_XOR_LOCK_MEMv_GPRv=6846, + XED_IFORM_XOR_LOCK_MEMv_IMMb=6847, + XED_IFORM_XOR_LOCK_MEMv_IMMz=6848, + XED_IFORM_XRESLDTRK=6849, + XED_IFORM_XRSTOR_MEMmxsave=6850, + XED_IFORM_XRSTOR64_MEMmxsave=6851, + XED_IFORM_XRSTORS_MEMmxsave=6852, + XED_IFORM_XRSTORS64_MEMmxsave=6853, + XED_IFORM_XSAVE_MEMmxsave=6854, + XED_IFORM_XSAVE64_MEMmxsave=6855, + XED_IFORM_XSAVEC_MEMmxsave=6856, + XED_IFORM_XSAVEC64_MEMmxsave=6857, + XED_IFORM_XSAVEOPT_MEMmxsave=6858, + XED_IFORM_XSAVEOPT64_MEMmxsave=6859, + XED_IFORM_XSAVES_MEMmxsave=6860, + XED_IFORM_XSAVES64_MEMmxsave=6861, + XED_IFORM_XSETBV=6862, + XED_IFORM_XSTORE=6863, + XED_IFORM_XSUSLDTRK=6864, + XED_IFORM_XTEST=6865, + XED_IFORM_LAST +} xed_iform_enum_t; + +/// This converts strings to #xed_iform_enum_t types. +/// @param s A C-string. +/// @return #xed_iform_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_iform_enum_t str2xed_iform_enum_t(const char* s); +/// This converts strings to #xed_iform_enum_t types. +/// @param p An enumeration element of type xed_iform_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_iform_enum_t2str(const xed_iform_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_iform_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_iform_enum_t xed_iform_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-iform-enum.txt b/CodeVirtualizer/build/obj/xed-iform-enum.txt new file mode 100644 index 0000000..f3fe336 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iform-enum.txt @@ -0,0 +1,6897 @@ +# @file xed-iform-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-iform-enum.c +hfn xed-iform-enum.h +typename xed_iform_enum_t +prefix XED_IFORM_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +extra_header xed-iclass-enum.h +INVALID 0 +AAA 1 +AAD_IMMb 2 +AAM_IMMb 3 +AAS 4 +ADC_AL_IMMb 5 +ADC_GPR8_GPR8_10 6 +ADC_GPR8_GPR8_12 7 +ADC_GPR8_IMMb_80r2 8 +ADC_GPR8_IMMb_82r2 9 +ADC_GPR8_MEMb 10 +ADC_GPRv_GPRv_11 11 +ADC_GPRv_GPRv_13 12 +ADC_GPRv_IMMb 13 +ADC_GPRv_IMMz 14 +ADC_GPRv_MEMv 15 +ADC_MEMb_GPR8 16 +ADC_MEMb_IMMb_80r2 17 +ADC_MEMb_IMMb_82r2 18 +ADC_MEMv_GPRv 19 +ADC_MEMv_IMMb 20 +ADC_MEMv_IMMz 21 +ADC_OrAX_IMMz 22 +ADCX_GPR32d_GPR32d 23 +ADCX_GPR32d_MEMd 24 +ADCX_GPR64q_GPR64q 25 +ADCX_GPR64q_MEMq 26 +ADC_LOCK_MEMb_GPR8 27 +ADC_LOCK_MEMb_IMMb_80r2 28 +ADC_LOCK_MEMb_IMMb_82r2 29 +ADC_LOCK_MEMv_GPRv 30 +ADC_LOCK_MEMv_IMMb 31 +ADC_LOCK_MEMv_IMMz 32 +ADD_AL_IMMb 33 +ADD_GPR8_GPR8_00 34 +ADD_GPR8_GPR8_02 35 +ADD_GPR8_IMMb_80r0 36 +ADD_GPR8_IMMb_82r0 37 +ADD_GPR8_MEMb 38 +ADD_GPRv_GPRv_01 39 +ADD_GPRv_GPRv_03 40 +ADD_GPRv_IMMb 41 +ADD_GPRv_IMMz 42 +ADD_GPRv_MEMv 43 +ADD_MEMb_GPR8 44 +ADD_MEMb_IMMb_80r0 45 +ADD_MEMb_IMMb_82r0 46 +ADD_MEMv_GPRv 47 +ADD_MEMv_IMMb 48 +ADD_MEMv_IMMz 49 +ADD_OrAX_IMMz 50 +ADDPD_XMMpd_MEMpd 51 +ADDPD_XMMpd_XMMpd 52 +ADDPS_XMMps_MEMps 53 +ADDPS_XMMps_XMMps 54 +ADDSD_XMMsd_MEMsd 55 +ADDSD_XMMsd_XMMsd 56 +ADDSS_XMMss_MEMss 57 +ADDSS_XMMss_XMMss 58 +ADDSUBPD_XMMpd_MEMpd 59 +ADDSUBPD_XMMpd_XMMpd 60 +ADDSUBPS_XMMps_MEMps 61 +ADDSUBPS_XMMps_XMMps 62 +ADD_LOCK_MEMb_GPR8 63 +ADD_LOCK_MEMb_IMMb_80r0 64 +ADD_LOCK_MEMb_IMMb_82r0 65 +ADD_LOCK_MEMv_GPRv 66 +ADD_LOCK_MEMv_IMMb 67 +ADD_LOCK_MEMv_IMMz 68 +ADOX_GPR32d_GPR32d 69 +ADOX_GPR32d_MEMd 70 +ADOX_GPR64q_GPR64q 71 +ADOX_GPR64q_MEMq 72 +AESDEC_XMMdq_MEMdq 73 +AESDEC_XMMdq_XMMdq 74 +AESDEC128KL_XMMu8_MEMu8 75 +AESDEC256KL_XMMu8_MEMu8 76 +AESDECLAST_XMMdq_MEMdq 77 +AESDECLAST_XMMdq_XMMdq 78 +AESDECWIDE128KL_MEMu8 79 +AESDECWIDE256KL_MEMu8 80 +AESENC_XMMdq_MEMdq 81 +AESENC_XMMdq_XMMdq 82 +AESENC128KL_XMMu8_MEMu8 83 +AESENC256KL_XMMu8_MEMu8 84 +AESENCLAST_XMMdq_MEMdq 85 +AESENCLAST_XMMdq_XMMdq 86 +AESENCWIDE128KL_MEMu8 87 +AESENCWIDE256KL_MEMu8 88 +AESIMC_XMMdq_MEMdq 89 +AESIMC_XMMdq_XMMdq 90 +AESKEYGENASSIST_XMMdq_MEMdq_IMMb 91 +AESKEYGENASSIST_XMMdq_XMMdq_IMMb 92 +AND_AL_IMMb 93 +AND_GPR8_GPR8_20 94 +AND_GPR8_GPR8_22 95 +AND_GPR8_IMMb_80r4 96 +AND_GPR8_IMMb_82r4 97 +AND_GPR8_MEMb 98 +AND_GPRv_GPRv_21 99 +AND_GPRv_GPRv_23 100 +AND_GPRv_IMMb 101 +AND_GPRv_IMMz 102 +AND_GPRv_MEMv 103 +AND_MEMb_GPR8 104 +AND_MEMb_IMMb_80r4 105 +AND_MEMb_IMMb_82r4 106 +AND_MEMv_GPRv 107 +AND_MEMv_IMMb 108 +AND_MEMv_IMMz 109 +AND_OrAX_IMMz 110 +ANDN_VGPR32d_VGPR32d_MEMd 111 +ANDN_VGPR32d_VGPR32d_VGPR32d 112 +ANDN_VGPR64q_VGPR64q_MEMq 113 +ANDN_VGPR64q_VGPR64q_VGPR64q 114 +ANDNPD_XMMxuq_MEMxuq 115 +ANDNPD_XMMxuq_XMMxuq 116 +ANDNPS_XMMxud_MEMxud 117 +ANDNPS_XMMxud_XMMxud 118 +ANDPD_XMMxuq_MEMxuq 119 +ANDPD_XMMxuq_XMMxuq 120 +ANDPS_XMMxud_MEMxud 121 +ANDPS_XMMxud_XMMxud 122 +AND_LOCK_MEMb_GPR8 123 +AND_LOCK_MEMb_IMMb_80r4 124 +AND_LOCK_MEMb_IMMb_82r4 125 +AND_LOCK_MEMv_GPRv 126 +AND_LOCK_MEMv_IMMb 127 +AND_LOCK_MEMv_IMMz 128 +ARPL_GPR16_GPR16 129 +ARPL_MEMw_GPR16 130 +BEXTR_VGPR32d_MEMd_VGPR32d 131 +BEXTR_VGPR32d_VGPR32d_VGPR32d 132 +BEXTR_VGPR64q_MEMq_VGPR64q 133 +BEXTR_VGPR64q_VGPR64q_VGPR64q 134 +BEXTR_XOP_VGPR32d_MEMd_IMMd 135 +BEXTR_XOP_VGPR32d_VGPR32d_IMMd 136 +BEXTR_XOP_VGPRyy_MEMy_IMMd 137 +BEXTR_XOP_VGPRyy_VGPRyy_IMMd 138 +BLCFILL_VGPR32d_MEMd 139 +BLCFILL_VGPR32d_VGPR32d 140 +BLCFILL_VGPRyy_MEMy 141 +BLCFILL_VGPRyy_VGPRyy 142 +BLCI_VGPR32d_MEMd 143 +BLCI_VGPR32d_VGPR32d 144 +BLCI_VGPRyy_MEMy 145 +BLCI_VGPRyy_VGPRyy 146 +BLCIC_VGPR32d_MEMd 147 +BLCIC_VGPR32d_VGPR32d 148 +BLCIC_VGPRyy_MEMy 149 +BLCIC_VGPRyy_VGPRyy 150 +BLCMSK_VGPR32d_MEMd 151 +BLCMSK_VGPR32d_VGPR32d 152 +BLCMSK_VGPRyy_MEMy 153 +BLCMSK_VGPRyy_VGPRyy 154 +BLCS_VGPR32d_MEMd 155 +BLCS_VGPR32d_VGPR32d 156 +BLCS_VGPRyy_MEMy 157 +BLCS_VGPRyy_VGPRyy 158 +BLENDPD_XMMdq_MEMdq_IMMb 159 +BLENDPD_XMMdq_XMMdq_IMMb 160 +BLENDPS_XMMdq_MEMdq_IMMb 161 +BLENDPS_XMMdq_XMMdq_IMMb 162 +BLENDVPD_XMMdq_MEMdq 163 +BLENDVPD_XMMdq_XMMdq 164 +BLENDVPS_XMMdq_MEMdq 165 +BLENDVPS_XMMdq_XMMdq 166 +BLSFILL_VGPR32d_MEMd 167 +BLSFILL_VGPR32d_VGPR32d 168 +BLSFILL_VGPRyy_MEMy 169 +BLSFILL_VGPRyy_VGPRyy 170 +BLSI_VGPR32d_MEMd 171 +BLSI_VGPR32d_VGPR32d 172 +BLSI_VGPR64q_MEMq 173 +BLSI_VGPR64q_VGPR64q 174 +BLSIC_VGPR32d_MEMd 175 +BLSIC_VGPR32d_VGPR32d 176 +BLSIC_VGPRyy_MEMy 177 +BLSIC_VGPRyy_VGPRyy 178 +BLSMSK_VGPR32d_MEMd 179 +BLSMSK_VGPR32d_VGPR32d 180 +BLSMSK_VGPR64q_MEMq 181 +BLSMSK_VGPR64q_VGPR64q 182 +BLSR_VGPR32d_MEMd 183 +BLSR_VGPR32d_VGPR32d 184 +BLSR_VGPR64q_MEMq 185 +BLSR_VGPR64q_VGPR64q 186 +BNDCL_BND_AGEN 187 +BNDCL_BND_GPR32 188 +BNDCL_BND_GPR64 189 +BNDCN_BND_AGEN 190 +BNDCN_BND_GPR32 191 +BNDCN_BND_GPR64 192 +BNDCU_BND_AGEN 193 +BNDCU_BND_GPR32 194 +BNDCU_BND_GPR64 195 +BNDLDX_BND_MEMbnd32 196 +BNDLDX_BND_MEMbnd64 197 +BNDMK_BND_AGEN 198 +BNDMOV_BND_BND 199 +BNDMOV_BND_MEMdq 200 +BNDMOV_BND_MEMq 201 +BNDMOV_MEMdq_BND 202 +BNDMOV_MEMq_BND 203 +BNDSTX_MEMbnd32_BND 204 +BNDSTX_MEMbnd64_BND 205 +BOUND_GPRv_MEMa16 206 +BOUND_GPRv_MEMa32 207 +BSF_GPRv_GPRv 208 +BSF_GPRv_MEMv 209 +BSR_GPRv_GPRv 210 +BSR_GPRv_MEMv 211 +BSWAP_GPRv 212 +BT_GPRv_GPRv 213 +BT_GPRv_IMMb 214 +BT_MEMv_GPRv 215 +BT_MEMv_IMMb 216 +BTC_GPRv_GPRv 217 +BTC_GPRv_IMMb 218 +BTC_MEMv_GPRv 219 +BTC_MEMv_IMMb 220 +BTC_LOCK_MEMv_GPRv 221 +BTC_LOCK_MEMv_IMMb 222 +BTR_GPRv_GPRv 223 +BTR_GPRv_IMMb 224 +BTR_MEMv_GPRv 225 +BTR_MEMv_IMMb 226 +BTR_LOCK_MEMv_GPRv 227 +BTR_LOCK_MEMv_IMMb 228 +BTS_GPRv_GPRv 229 +BTS_GPRv_IMMb 230 +BTS_MEMv_GPRv 231 +BTS_MEMv_IMMb 232 +BTS_LOCK_MEMv_GPRv 233 +BTS_LOCK_MEMv_IMMb 234 +BZHI_VGPR32d_MEMd_VGPR32d 235 +BZHI_VGPR32d_VGPR32d_VGPR32d 236 +BZHI_VGPR64q_MEMq_VGPR64q 237 +BZHI_VGPR64q_VGPR64q_VGPR64q 238 +CALL_FAR_MEMp2 239 +CALL_FAR_PTRp_IMMw 240 +CALL_NEAR_GPRv 241 +CALL_NEAR_MEMv 242 +CALL_NEAR_RELBRd 243 +CALL_NEAR_RELBRz 244 +CBW 245 +CDQ 246 +CDQE 247 +CLAC 248 +CLC 249 +CLD 250 +CLDEMOTE_MEMu8 251 +CLFLUSH_MEMmprefetch 252 +CLFLUSHOPT_MEMmprefetch 253 +CLGI 254 +CLI 255 +CLRSSBSY_MEMu64 256 +CLTS 257 +CLUI 258 +CLWB_MEMmprefetch 259 +CLZERO 260 +CMC 261 +CMOVB_GPRv_GPRv 262 +CMOVB_GPRv_MEMv 263 +CMOVBE_GPRv_GPRv 264 +CMOVBE_GPRv_MEMv 265 +CMOVL_GPRv_GPRv 266 +CMOVL_GPRv_MEMv 267 +CMOVLE_GPRv_GPRv 268 +CMOVLE_GPRv_MEMv 269 +CMOVNB_GPRv_GPRv 270 +CMOVNB_GPRv_MEMv 271 +CMOVNBE_GPRv_GPRv 272 +CMOVNBE_GPRv_MEMv 273 +CMOVNL_GPRv_GPRv 274 +CMOVNL_GPRv_MEMv 275 +CMOVNLE_GPRv_GPRv 276 +CMOVNLE_GPRv_MEMv 277 +CMOVNO_GPRv_GPRv 278 +CMOVNO_GPRv_MEMv 279 +CMOVNP_GPRv_GPRv 280 +CMOVNP_GPRv_MEMv 281 +CMOVNS_GPRv_GPRv 282 +CMOVNS_GPRv_MEMv 283 +CMOVNZ_GPRv_GPRv 284 +CMOVNZ_GPRv_MEMv 285 +CMOVO_GPRv_GPRv 286 +CMOVO_GPRv_MEMv 287 +CMOVP_GPRv_GPRv 288 +CMOVP_GPRv_MEMv 289 +CMOVS_GPRv_GPRv 290 +CMOVS_GPRv_MEMv 291 +CMOVZ_GPRv_GPRv 292 +CMOVZ_GPRv_MEMv 293 +CMP_AL_IMMb 294 +CMP_GPR8_GPR8_38 295 +CMP_GPR8_GPR8_3A 296 +CMP_GPR8_IMMb_80r7 297 +CMP_GPR8_IMMb_82r7 298 +CMP_GPR8_MEMb 299 +CMP_GPRv_GPRv_39 300 +CMP_GPRv_GPRv_3B 301 +CMP_GPRv_IMMb 302 +CMP_GPRv_IMMz 303 +CMP_GPRv_MEMv 304 +CMP_MEMb_GPR8 305 +CMP_MEMb_IMMb_80r7 306 +CMP_MEMb_IMMb_82r7 307 +CMP_MEMv_GPRv 308 +CMP_MEMv_IMMb 309 +CMP_MEMv_IMMz 310 +CMP_OrAX_IMMz 311 +CMPPD_XMMpd_MEMpd_IMMb 312 +CMPPD_XMMpd_XMMpd_IMMb 313 +CMPPS_XMMps_MEMps_IMMb 314 +CMPPS_XMMps_XMMps_IMMb 315 +CMPSB 316 +CMPSD 317 +CMPSD_XMM_XMMsd_MEMsd_IMMb 318 +CMPSD_XMM_XMMsd_XMMsd_IMMb 319 +CMPSQ 320 +CMPSS_XMMss_MEMss_IMMb 321 +CMPSS_XMMss_XMMss_IMMb 322 +CMPSW 323 +CMPXCHG_GPR8_GPR8 324 +CMPXCHG_GPRv_GPRv 325 +CMPXCHG_MEMb_GPR8 326 +CMPXCHG_MEMv_GPRv 327 +CMPXCHG16B_MEMdq 328 +CMPXCHG16B_LOCK_MEMdq 329 +CMPXCHG8B_MEMq 330 +CMPXCHG8B_LOCK_MEMq 331 +CMPXCHG_LOCK_MEMb_GPR8 332 +CMPXCHG_LOCK_MEMv_GPRv 333 +COMISD_XMMsd_MEMsd 334 +COMISD_XMMsd_XMMsd 335 +COMISS_XMMss_MEMss 336 +COMISS_XMMss_XMMss 337 +CPUID 338 +CQO 339 +CRC32_GPRyy_GPR8b 340 +CRC32_GPRyy_GPRv 341 +CRC32_GPRyy_MEMb 342 +CRC32_GPRyy_MEMv 343 +CVTDQ2PD_XMMpd_MEMq 344 +CVTDQ2PD_XMMpd_XMMq 345 +CVTDQ2PS_XMMps_MEMdq 346 +CVTDQ2PS_XMMps_XMMdq 347 +CVTPD2DQ_XMMdq_MEMpd 348 +CVTPD2DQ_XMMdq_XMMpd 349 +CVTPD2PI_MMXq_MEMpd 350 +CVTPD2PI_MMXq_XMMpd 351 +CVTPD2PS_XMMps_MEMpd 352 +CVTPD2PS_XMMps_XMMpd 353 +CVTPI2PD_XMMpd_MEMq 354 +CVTPI2PD_XMMpd_MMXq 355 +CVTPI2PS_XMMq_MEMq 356 +CVTPI2PS_XMMq_MMXq 357 +CVTPS2DQ_XMMdq_MEMps 358 +CVTPS2DQ_XMMdq_XMMps 359 +CVTPS2PD_XMMpd_MEMq 360 +CVTPS2PD_XMMpd_XMMq 361 +CVTPS2PI_MMXq_MEMq 362 +CVTPS2PI_MMXq_XMMq 363 +CVTSD2SI_GPR32d_MEMsd 364 +CVTSD2SI_GPR32d_XMMsd 365 +CVTSD2SI_GPR64q_MEMsd 366 +CVTSD2SI_GPR64q_XMMsd 367 +CVTSD2SS_XMMss_MEMsd 368 +CVTSD2SS_XMMss_XMMsd 369 +CVTSI2SD_XMMsd_GPR32d 370 +CVTSI2SD_XMMsd_GPR64q 371 +CVTSI2SD_XMMsd_MEMd 372 +CVTSI2SD_XMMsd_MEMq 373 +CVTSI2SS_XMMss_GPR32d 374 +CVTSI2SS_XMMss_GPR64q 375 +CVTSI2SS_XMMss_MEMd 376 +CVTSI2SS_XMMss_MEMq 377 +CVTSS2SD_XMMsd_MEMss 378 +CVTSS2SD_XMMsd_XMMss 379 +CVTSS2SI_GPR32d_MEMss 380 +CVTSS2SI_GPR32d_XMMss 381 +CVTSS2SI_GPR64q_MEMss 382 +CVTSS2SI_GPR64q_XMMss 383 +CVTTPD2DQ_XMMdq_MEMpd 384 +CVTTPD2DQ_XMMdq_XMMpd 385 +CVTTPD2PI_MMXq_MEMpd 386 +CVTTPD2PI_MMXq_XMMpd 387 +CVTTPS2DQ_XMMdq_MEMps 388 +CVTTPS2DQ_XMMdq_XMMps 389 +CVTTPS2PI_MMXq_MEMq 390 +CVTTPS2PI_MMXq_XMMq 391 +CVTTSD2SI_GPR32d_MEMsd 392 +CVTTSD2SI_GPR32d_XMMsd 393 +CVTTSD2SI_GPR64q_MEMsd 394 +CVTTSD2SI_GPR64q_XMMsd 395 +CVTTSS2SI_GPR32d_MEMss 396 +CVTTSS2SI_GPR32d_XMMss 397 +CVTTSS2SI_GPR64q_MEMss 398 +CVTTSS2SI_GPR64q_XMMss 399 +CWD 400 +CWDE 401 +DAA 402 +DAS 403 +DEC_GPR8 404 +DEC_GPRv_48 405 +DEC_GPRv_FFr1 406 +DEC_MEMb 407 +DEC_MEMv 408 +DEC_LOCK_MEMb 409 +DEC_LOCK_MEMv 410 +DIV_GPR8 411 +DIV_GPRv 412 +DIV_MEMb 413 +DIV_MEMv 414 +DIVPD_XMMpd_MEMpd 415 +DIVPD_XMMpd_XMMpd 416 +DIVPS_XMMps_MEMps 417 +DIVPS_XMMps_XMMps 418 +DIVSD_XMMsd_MEMsd 419 +DIVSD_XMMsd_XMMsd 420 +DIVSS_XMMss_MEMss 421 +DIVSS_XMMss_XMMss 422 +DPPD_XMMdq_MEMdq_IMMb 423 +DPPD_XMMdq_XMMdq_IMMb 424 +DPPS_XMMdq_MEMdq_IMMb 425 +DPPS_XMMdq_XMMdq_IMMb 426 +EMMS 427 +ENCLS 428 +ENCLU 429 +ENCLV 430 +ENCODEKEY128_GPR32u8_GPR32u8 431 +ENCODEKEY256_GPR32u8_GPR32u8 432 +ENDBR32 433 +ENDBR64 434 +ENQCMD_GPRa_MEMu32 435 +ENQCMDS_GPRa_MEMu32 436 +ENTER_IMMw_IMMb 437 +EXTRACTPS_GPR32d_XMMdq_IMMb 438 +EXTRACTPS_MEMd_XMMps_IMMb 439 +EXTRQ_XMMq_IMMb_IMMb 440 +EXTRQ_XMMq_XMMdq 441 +F2XM1 442 +FABS 443 +FADD_ST0_MEMm64real 444 +FADD_ST0_MEMmem32real 445 +FADD_ST0_X87 446 +FADD_X87_ST0 447 +FADDP_X87_ST0 448 +FBLD_ST0_MEMmem80dec 449 +FBSTP_MEMmem80dec_ST0 450 +FCHS 451 +FCMOVB_ST0_X87 452 +FCMOVBE_ST0_X87 453 +FCMOVE_ST0_X87 454 +FCMOVNB_ST0_X87 455 +FCMOVNBE_ST0_X87 456 +FCMOVNE_ST0_X87 457 +FCMOVNU_ST0_X87 458 +FCMOVU_ST0_X87 459 +FCOM_ST0_MEMm64real 460 +FCOM_ST0_MEMmem32real 461 +FCOM_ST0_X87 462 +FCOM_ST0_X87_DCD0 463 +FCOMI_ST0_X87 464 +FCOMIP_ST0_X87 465 +FCOMP_ST0_MEMm64real 466 +FCOMP_ST0_MEMmem32real 467 +FCOMP_ST0_X87 468 +FCOMP_ST0_X87_DCD1 469 +FCOMP_ST0_X87_DED0 470 +FCOMPP 471 +FCOS 472 +FDECSTP 473 +FDISI8087_NOP 474 +FDIV_ST0_MEMm64real 475 +FDIV_ST0_MEMmem32real 476 +FDIV_ST0_X87 477 +FDIV_X87_ST0 478 +FDIVP_X87_ST0 479 +FDIVR_ST0_MEMm64real 480 +FDIVR_ST0_MEMmem32real 481 +FDIVR_ST0_X87 482 +FDIVR_X87_ST0 483 +FDIVRP_X87_ST0 484 +FEMMS 485 +FENI8087_NOP 486 +FFREE_X87 487 +FFREEP_X87 488 +FIADD_ST0_MEMmem16int 489 +FIADD_ST0_MEMmem32int 490 +FICOM_ST0_MEMmem16int 491 +FICOM_ST0_MEMmem32int 492 +FICOMP_ST0_MEMmem16int 493 +FICOMP_ST0_MEMmem32int 494 +FIDIV_ST0_MEMmem16int 495 +FIDIV_ST0_MEMmem32int 496 +FIDIVR_ST0_MEMmem16int 497 +FIDIVR_ST0_MEMmem32int 498 +FILD_ST0_MEMm64int 499 +FILD_ST0_MEMmem16int 500 +FILD_ST0_MEMmem32int 501 +FIMUL_ST0_MEMmem16int 502 +FIMUL_ST0_MEMmem32int 503 +FINCSTP 504 +FIST_MEMmem16int_ST0 505 +FIST_MEMmem32int_ST0 506 +FISTP_MEMm64int_ST0 507 +FISTP_MEMmem16int_ST0 508 +FISTP_MEMmem32int_ST0 509 +FISTTP_MEMm64int_ST0 510 +FISTTP_MEMmem16int_ST0 511 +FISTTP_MEMmem32int_ST0 512 +FISUB_ST0_MEMmem16int 513 +FISUB_ST0_MEMmem32int 514 +FISUBR_ST0_MEMmem16int 515 +FISUBR_ST0_MEMmem32int 516 +FLD_ST0_MEMm64real 517 +FLD_ST0_MEMmem32real 518 +FLD_ST0_MEMmem80real 519 +FLD_ST0_X87 520 +FLD1 521 +FLDCW_MEMmem16 522 +FLDENV_MEMmem14 523 +FLDENV_MEMmem28 524 +FLDL2E 525 +FLDL2T 526 +FLDLG2 527 +FLDLN2 528 +FLDPI 529 +FLDZ 530 +FMUL_ST0_MEMm64real 531 +FMUL_ST0_MEMmem32real 532 +FMUL_ST0_X87 533 +FMUL_X87_ST0 534 +FMULP_X87_ST0 535 +FNCLEX 536 +FNINIT 537 +FNOP 538 +FNSAVE_MEMmem108 539 +FNSAVE_MEMmem94 540 +FNSTCW_MEMmem16 541 +FNSTENV_MEMmem14 542 +FNSTENV_MEMmem28 543 +FNSTSW_AX 544 +FNSTSW_MEMmem16 545 +FPATAN 546 +FPREM 547 +FPREM1 548 +FPTAN 549 +FRNDINT 550 +FRSTOR_MEMmem108 551 +FRSTOR_MEMmem94 552 +FSCALE 553 +FSETPM287_NOP 554 +FSIN 555 +FSINCOS 556 +FSQRT 557 +FST_MEMm64real_ST0 558 +FST_MEMmem32real_ST0 559 +FST_X87_ST0 560 +FSTP_MEMm64real_ST0 561 +FSTP_MEMmem32real_ST0 562 +FSTP_MEMmem80real_ST0 563 +FSTP_X87_ST0 564 +FSTP_X87_ST0_DFD0 565 +FSTP_X87_ST0_DFD1 566 +FSTPNCE_X87_ST0 567 +FSUB_ST0_MEMm64real 568 +FSUB_ST0_MEMmem32real 569 +FSUB_ST0_X87 570 +FSUB_X87_ST0 571 +FSUBP_X87_ST0 572 +FSUBR_ST0_MEMm64real 573 +FSUBR_ST0_MEMmem32real 574 +FSUBR_ST0_X87 575 +FSUBR_X87_ST0 576 +FSUBRP_X87_ST0 577 +FTST 578 +FUCOM_ST0_X87 579 +FUCOMI_ST0_X87 580 +FUCOMIP_ST0_X87 581 +FUCOMP_ST0_X87 582 +FUCOMPP 583 +FWAIT 584 +FXAM 585 +FXCH_ST0_X87 586 +FXCH_ST0_X87_DDC1 587 +FXCH_ST0_X87_DFC1 588 +FXRSTOR_MEMmfpxenv 589 +FXRSTOR64_MEMmfpxenv 590 +FXSAVE_MEMmfpxenv 591 +FXSAVE64_MEMmfpxenv 592 +FXTRACT 593 +FYL2X 594 +FYL2XP1 595 +GETSEC 596 +GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 597 +GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 598 +GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 599 +GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 600 +GF2P8MULB_XMMu8_MEMu8 601 +GF2P8MULB_XMMu8_XMMu8 602 +HADDPD_XMMpd_MEMpd 603 +HADDPD_XMMpd_XMMpd 604 +HADDPS_XMMps_MEMps 605 +HADDPS_XMMps_XMMps 606 +HLT 607 +HRESET_IMM8 608 +HSUBPD_XMMpd_MEMpd 609 +HSUBPD_XMMpd_XMMpd 610 +HSUBPS_XMMps_MEMps 611 +HSUBPS_XMMps_XMMps 612 +IDIV_GPR8 613 +IDIV_GPRv 614 +IDIV_MEMb 615 +IDIV_MEMv 616 +IMUL_GPR8 617 +IMUL_GPRv 618 +IMUL_GPRv_GPRv 619 +IMUL_GPRv_GPRv_IMMb 620 +IMUL_GPRv_GPRv_IMMz 621 +IMUL_GPRv_MEMv 622 +IMUL_GPRv_MEMv_IMMb 623 +IMUL_GPRv_MEMv_IMMz 624 +IMUL_MEMb 625 +IMUL_MEMv 626 +IN_AL_DX 627 +IN_AL_IMMb 628 +IN_OeAX_DX 629 +IN_OeAX_IMMb 630 +INC_GPR8 631 +INC_GPRv_40 632 +INC_GPRv_FFr0 633 +INC_MEMb 634 +INC_MEMv 635 +INCSSPD_GPR32u8 636 +INCSSPQ_GPR64u8 637 +INC_LOCK_MEMb 638 +INC_LOCK_MEMv 639 +INSB 640 +INSD 641 +INSERTPS_XMMps_MEMd_IMMb 642 +INSERTPS_XMMps_XMMps_IMMb 643 +INSERTQ_XMMq_XMMdq 644 +INSERTQ_XMMq_XMMq_IMMb_IMMb 645 +INSW 646 +INT_IMMb 647 +INT1 648 +INT3 649 +INTO 650 +INVD 651 +INVEPT_GPR32_MEMdq 652 +INVEPT_GPR64_MEMdq 653 +INVLPG_MEMb 654 +INVLPGA_ArAX_ECX 655 +INVLPGB_EAX_EDX_ECX 656 +INVLPGB_RAX_EDX_ECX 657 +INVPCID_GPR32_MEMdq 658 +INVPCID_GPR64_MEMdq 659 +INVVPID_GPR32_MEMdq 660 +INVVPID_GPR64_MEMdq 661 +IRET 662 +IRETD 663 +IRETQ 664 +JB_RELBRb 665 +JB_RELBRd 666 +JB_RELBRz 667 +JBE_RELBRb 668 +JBE_RELBRd 669 +JBE_RELBRz 670 +JCXZ_RELBRb 671 +JECXZ_RELBRb 672 +JL_RELBRb 673 +JL_RELBRd 674 +JL_RELBRz 675 +JLE_RELBRb 676 +JLE_RELBRd 677 +JLE_RELBRz 678 +JMP_GPRv 679 +JMP_MEMv 680 +JMP_RELBRb 681 +JMP_RELBRd 682 +JMP_RELBRz 683 +JMP_FAR_MEMp2 684 +JMP_FAR_PTRp_IMMw 685 +JNB_RELBRb 686 +JNB_RELBRd 687 +JNB_RELBRz 688 +JNBE_RELBRb 689 +JNBE_RELBRd 690 +JNBE_RELBRz 691 +JNL_RELBRb 692 +JNL_RELBRd 693 +JNL_RELBRz 694 +JNLE_RELBRb 695 +JNLE_RELBRd 696 +JNLE_RELBRz 697 +JNO_RELBRb 698 +JNO_RELBRd 699 +JNO_RELBRz 700 +JNP_RELBRb 701 +JNP_RELBRd 702 +JNP_RELBRz 703 +JNS_RELBRb 704 +JNS_RELBRd 705 +JNS_RELBRz 706 +JNZ_RELBRb 707 +JNZ_RELBRd 708 +JNZ_RELBRz 709 +JO_RELBRb 710 +JO_RELBRd 711 +JO_RELBRz 712 +JP_RELBRb 713 +JP_RELBRd 714 +JP_RELBRz 715 +JRCXZ_RELBRb 716 +JS_RELBRb 717 +JS_RELBRd 718 +JS_RELBRz 719 +JZ_RELBRb 720 +JZ_RELBRd 721 +JZ_RELBRz 722 +KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 723 +KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 724 +KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 725 +KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 726 +KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 727 +KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 728 +KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 729 +KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 730 +KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 731 +KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 732 +KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 733 +KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 734 +KMOVB_GPR32u32_MASKmskw_AVX512 735 +KMOVB_MASKmskw_GPR32u32_AVX512 736 +KMOVB_MASKmskw_MASKu8_AVX512 737 +KMOVB_MASKmskw_MEMu8_AVX512 738 +KMOVB_MEMu8_MASKmskw_AVX512 739 +KMOVD_GPR32u32_MASKmskw_AVX512 740 +KMOVD_MASKmskw_GPR32u32_AVX512 741 +KMOVD_MASKmskw_MASKu32_AVX512 742 +KMOVD_MASKmskw_MEMu32_AVX512 743 +KMOVD_MEMu32_MASKmskw_AVX512 744 +KMOVQ_GPR64u64_MASKmskw_AVX512 745 +KMOVQ_MASKmskw_GPR64u64_AVX512 746 +KMOVQ_MASKmskw_MASKu64_AVX512 747 +KMOVQ_MASKmskw_MEMu64_AVX512 748 +KMOVQ_MEMu64_MASKmskw_AVX512 749 +KMOVW_GPR32u32_MASKmskw_AVX512 750 +KMOVW_MASKmskw_GPR32u32_AVX512 751 +KMOVW_MASKmskw_MASKu16_AVX512 752 +KMOVW_MASKmskw_MEMu16_AVX512 753 +KMOVW_MEMu16_MASKmskw_AVX512 754 +KNOTB_MASKmskw_MASKmskw_AVX512 755 +KNOTD_MASKmskw_MASKmskw_AVX512 756 +KNOTQ_MASKmskw_MASKmskw_AVX512 757 +KNOTW_MASKmskw_MASKmskw_AVX512 758 +KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 759 +KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 760 +KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 761 +KORTESTB_MASKmskw_MASKmskw_AVX512 762 +KORTESTD_MASKmskw_MASKmskw_AVX512 763 +KORTESTQ_MASKmskw_MASKmskw_AVX512 764 +KORTESTW_MASKmskw_MASKmskw_AVX512 765 +KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 766 +KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 767 +KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 768 +KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 769 +KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 770 +KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 771 +KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 772 +KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 773 +KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 774 +KTESTB_MASKmskw_MASKmskw_AVX512 775 +KTESTD_MASKmskw_MASKmskw_AVX512 776 +KTESTQ_MASKmskw_MASKmskw_AVX512 777 +KTESTW_MASKmskw_MASKmskw_AVX512 778 +KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 779 +KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 780 +KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 781 +KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 782 +KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 783 +KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 784 +KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 785 +KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 786 +KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 787 +KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 788 +KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 789 +LAHF 790 +LAR_GPRv_GPRv 791 +LAR_GPRv_MEMw 792 +LDDQU_XMMpd_MEMdq 793 +LDMXCSR_MEMd 794 +LDS_GPRz_MEMp 795 +LDTILECFG_MEM 796 +LEA_GPRv_AGEN 797 +LEAVE 798 +LES_GPRz_MEMp 799 +LFENCE 800 +LFS_GPRv_MEMp2 801 +LGDT_MEMs 802 +LGDT_MEMs64 803 +LGS_GPRv_MEMp2 804 +LIDT_MEMs 805 +LIDT_MEMs64 806 +LLDT_GPR16 807 +LLDT_MEMw 808 +LLWPCB_VGPRyy 809 +LMSW_GPR16 810 +LMSW_MEMw 811 +LOADIWKEY_XMMu8_XMMu8 812 +LODSB 813 +LODSD 814 +LODSQ 815 +LODSW 816 +LOOP_RELBRb 817 +LOOPE_RELBRb 818 +LOOPNE_RELBRb 819 +LSL_GPRv_GPRz 820 +LSL_GPRv_MEMw 821 +LSS_GPRv_MEMp2 822 +LTR_GPR16 823 +LTR_MEMw 824 +LWPINS_VGPRyy_MEMd_IMMd 825 +LWPINS_VGPRyy_VGPR32y_IMMd 826 +LWPVAL_VGPRyy_MEMd_IMMd 827 +LWPVAL_VGPRyy_VGPR32y_IMMd 828 +LZCNT_GPRv_GPRv 829 +LZCNT_GPRv_MEMv 830 +MASKMOVDQU_XMMdq_XMMdq 831 +MASKMOVQ_MMXq_MMXq 832 +MAXPD_XMMpd_MEMpd 833 +MAXPD_XMMpd_XMMpd 834 +MAXPS_XMMps_MEMps 835 +MAXPS_XMMps_XMMps 836 +MAXSD_XMMsd_MEMsd 837 +MAXSD_XMMsd_XMMsd 838 +MAXSS_XMMss_MEMss 839 +MAXSS_XMMss_XMMss 840 +MCOMMIT 841 +MFENCE 842 +MINPD_XMMpd_MEMpd 843 +MINPD_XMMpd_XMMpd 844 +MINPS_XMMps_MEMps 845 +MINPS_XMMps_XMMps 846 +MINSD_XMMsd_MEMsd 847 +MINSD_XMMsd_XMMsd 848 +MINSS_XMMss_MEMss 849 +MINSS_XMMss_XMMss 850 +MONITOR 851 +MONITORX 852 +MOV_AL_MEMb 853 +MOV_GPR8_GPR8_88 854 +MOV_GPR8_GPR8_8A 855 +MOV_GPR8_IMMb_B0 856 +MOV_GPR8_IMMb_C6r0 857 +MOV_GPR8_MEMb 858 +MOV_GPRv_GPRv_89 859 +MOV_GPRv_GPRv_8B 860 +MOV_GPRv_IMMv 861 +MOV_GPRv_IMMz 862 +MOV_GPRv_MEMv 863 +MOV_GPRv_SEG 864 +MOV_MEMb_AL 865 +MOV_MEMb_GPR8 866 +MOV_MEMb_IMMb 867 +MOV_MEMv_GPRv 868 +MOV_MEMv_IMMz 869 +MOV_MEMv_OrAX 870 +MOV_MEMw_SEG 871 +MOV_OrAX_MEMv 872 +MOV_SEG_GPR16 873 +MOV_SEG_MEMw 874 +MOVAPD_MEMpd_XMMpd 875 +MOVAPD_XMMpd_MEMpd 876 +MOVAPD_XMMpd_XMMpd_0F28 877 +MOVAPD_XMMpd_XMMpd_0F29 878 +MOVAPS_MEMps_XMMps 879 +MOVAPS_XMMps_MEMps 880 +MOVAPS_XMMps_XMMps_0F28 881 +MOVAPS_XMMps_XMMps_0F29 882 +MOVBE_GPRv_MEMv 883 +MOVBE_MEMv_GPRv 884 +MOVD_GPR32_MMXd 885 +MOVD_GPR32_XMMd 886 +MOVD_MEMd_MMXd 887 +MOVD_MEMd_XMMd 888 +MOVD_MMXq_GPR32 889 +MOVD_MMXq_MEMd 890 +MOVD_XMMdq_GPR32 891 +MOVD_XMMdq_MEMd 892 +MOVDDUP_XMMdq_MEMq 893 +MOVDDUP_XMMdq_XMMq 894 +MOVDIR64B_GPRa_MEM 895 +MOVDIRI_MEMu32_GPR32u32 896 +MOVDIRI_MEMu64_GPR64u64 897 +MOVDQ2Q_MMXq_XMMq 898 +MOVDQA_MEMdq_XMMdq 899 +MOVDQA_XMMdq_MEMdq 900 +MOVDQA_XMMdq_XMMdq_0F6F 901 +MOVDQA_XMMdq_XMMdq_0F7F 902 +MOVDQU_MEMdq_XMMdq 903 +MOVDQU_XMMdq_MEMdq 904 +MOVDQU_XMMdq_XMMdq_0F6F 905 +MOVDQU_XMMdq_XMMdq_0F7F 906 +MOVHLPS_XMMq_XMMq 907 +MOVHPD_MEMq_XMMsd 908 +MOVHPD_XMMsd_MEMq 909 +MOVHPS_MEMq_XMMps 910 +MOVHPS_XMMq_MEMq 911 +MOVLHPS_XMMq_XMMq 912 +MOVLPD_MEMq_XMMsd 913 +MOVLPD_XMMsd_MEMq 914 +MOVLPS_MEMq_XMMq 915 +MOVLPS_XMMq_MEMq 916 +MOVMSKPD_GPR32_XMMpd 917 +MOVMSKPS_GPR32_XMMps 918 +MOVNTDQ_MEMdq_XMMdq 919 +MOVNTDQA_XMMdq_MEMdq 920 +MOVNTI_MEMd_GPR32 921 +MOVNTI_MEMq_GPR64 922 +MOVNTPD_MEMdq_XMMpd 923 +MOVNTPS_MEMdq_XMMps 924 +MOVNTQ_MEMq_MMXq 925 +MOVNTSD_MEMq_XMMq 926 +MOVNTSS_MEMd_XMMd 927 +MOVQ_GPR64_MMXq 928 +MOVQ_GPR64_XMMq 929 +MOVQ_MEMq_MMXq_0F7E 930 +MOVQ_MEMq_MMXq_0F7F 931 +MOVQ_MEMq_XMMq_0F7E 932 +MOVQ_MEMq_XMMq_0FD6 933 +MOVQ_MMXq_GPR64 934 +MOVQ_MMXq_MEMq_0F6E 935 +MOVQ_MMXq_MEMq_0F6F 936 +MOVQ_MMXq_MMXq_0F6F 937 +MOVQ_MMXq_MMXq_0F7F 938 +MOVQ_XMMdq_GPR64 939 +MOVQ_XMMdq_MEMq_0F6E 940 +MOVQ_XMMdq_MEMq_0F7E 941 +MOVQ_XMMdq_XMMq_0F7E 942 +MOVQ_XMMdq_XMMq_0FD6 943 +MOVQ2DQ_XMMdq_MMXq 944 +MOVSB 945 +MOVSD 946 +MOVSD_XMM_MEMsd_XMMsd 947 +MOVSD_XMM_XMMdq_MEMsd 948 +MOVSD_XMM_XMMsd_XMMsd_0F10 949 +MOVSD_XMM_XMMsd_XMMsd_0F11 950 +MOVSHDUP_XMMps_MEMps 951 +MOVSHDUP_XMMps_XMMps 952 +MOVSLDUP_XMMps_MEMps 953 +MOVSLDUP_XMMps_XMMps 954 +MOVSQ 955 +MOVSS_MEMss_XMMss 956 +MOVSS_XMMdq_MEMss 957 +MOVSS_XMMss_XMMss_0F10 958 +MOVSS_XMMss_XMMss_0F11 959 +MOVSW 960 +MOVSX_GPRv_GPR16 961 +MOVSX_GPRv_GPR8 962 +MOVSX_GPRv_MEMb 963 +MOVSX_GPRv_MEMw 964 +MOVSXD_GPRv_GPRz 965 +MOVSXD_GPRv_MEMz 966 +MOVUPD_MEMpd_XMMpd 967 +MOVUPD_XMMpd_MEMpd 968 +MOVUPD_XMMpd_XMMpd_0F10 969 +MOVUPD_XMMpd_XMMpd_0F11 970 +MOVUPS_MEMps_XMMps 971 +MOVUPS_XMMps_MEMps 972 +MOVUPS_XMMps_XMMps_0F10 973 +MOVUPS_XMMps_XMMps_0F11 974 +MOVZX_GPRv_GPR16 975 +MOVZX_GPRv_GPR8 976 +MOVZX_GPRv_MEMb 977 +MOVZX_GPRv_MEMw 978 +MOV_CR_CR_GPR32 979 +MOV_CR_CR_GPR64 980 +MOV_CR_GPR32_CR 981 +MOV_CR_GPR64_CR 982 +MOV_DR_DR_GPR32 983 +MOV_DR_DR_GPR64 984 +MOV_DR_GPR32_DR 985 +MOV_DR_GPR64_DR 986 +MPSADBW_XMMdq_MEMdq_IMMb 987 +MPSADBW_XMMdq_XMMdq_IMMb 988 +MUL_GPR8 989 +MUL_GPRv 990 +MUL_MEMb 991 +MUL_MEMv 992 +MULPD_XMMpd_MEMpd 993 +MULPD_XMMpd_XMMpd 994 +MULPS_XMMps_MEMps 995 +MULPS_XMMps_XMMps 996 +MULSD_XMMsd_MEMsd 997 +MULSD_XMMsd_XMMsd 998 +MULSS_XMMss_MEMss 999 +MULSS_XMMss_XMMss 1000 +MULX_VGPR32d_VGPR32d_MEMd 1001 +MULX_VGPR32d_VGPR32d_VGPR32d 1002 +MULX_VGPR64q_VGPR64q_MEMq 1003 +MULX_VGPR64q_VGPR64q_VGPR64q 1004 +MWAIT 1005 +MWAITX 1006 +NEG_GPR8 1007 +NEG_GPRv 1008 +NEG_MEMb 1009 +NEG_MEMv 1010 +NEG_LOCK_MEMb 1011 +NEG_LOCK_MEMv 1012 +NOP_90 1013 +NOP_GPRv_0F18r0 1014 +NOP_GPRv_0F18r1 1015 +NOP_GPRv_0F18r2 1016 +NOP_GPRv_0F18r3 1017 +NOP_GPRv_0F18r4 1018 +NOP_GPRv_0F18r5 1019 +NOP_GPRv_0F18r6 1020 +NOP_GPRv_0F18r7 1021 +NOP_GPRv_GPRv_0F0D 1022 +NOP_GPRv_GPRv_0F19 1023 +NOP_GPRv_GPRv_0F1A 1024 +NOP_GPRv_GPRv_0F1B 1025 +NOP_GPRv_GPRv_0F1C 1026 +NOP_GPRv_GPRv_0F1D 1027 +NOP_GPRv_GPRv_0F1E 1028 +NOP_GPRv_GPRv_0F1F 1029 +NOP_GPRv_MEM_0F1B 1030 +NOP_GPRv_MEMv_0F1A 1031 +NOP_MEMv_0F18r4 1032 +NOP_MEMv_0F18r5 1033 +NOP_MEMv_0F18r6 1034 +NOP_MEMv_0F18r7 1035 +NOP_MEMv_GPRv_0F19 1036 +NOP_MEMv_GPRv_0F1C 1037 +NOP_MEMv_GPRv_0F1D 1038 +NOP_MEMv_GPRv_0F1E 1039 +NOP_MEMv_GPRv_0F1F 1040 +NOT_GPR8 1041 +NOT_GPRv 1042 +NOT_MEMb 1043 +NOT_MEMv 1044 +NOT_LOCK_MEMb 1045 +NOT_LOCK_MEMv 1046 +OR_AL_IMMb 1047 +OR_GPR8_GPR8_08 1048 +OR_GPR8_GPR8_0A 1049 +OR_GPR8_IMMb_80r1 1050 +OR_GPR8_IMMb_82r1 1051 +OR_GPR8_MEMb 1052 +OR_GPRv_GPRv_09 1053 +OR_GPRv_GPRv_0B 1054 +OR_GPRv_IMMb 1055 +OR_GPRv_IMMz 1056 +OR_GPRv_MEMv 1057 +OR_MEMb_GPR8 1058 +OR_MEMb_IMMb_80r1 1059 +OR_MEMb_IMMb_82r1 1060 +OR_MEMv_GPRv 1061 +OR_MEMv_IMMb 1062 +OR_MEMv_IMMz 1063 +OR_OrAX_IMMz 1064 +ORPD_XMMxuq_MEMxuq 1065 +ORPD_XMMxuq_XMMxuq 1066 +ORPS_XMMxud_MEMxud 1067 +ORPS_XMMxud_XMMxud 1068 +OR_LOCK_MEMb_GPR8 1069 +OR_LOCK_MEMb_IMMb_80r1 1070 +OR_LOCK_MEMb_IMMb_82r1 1071 +OR_LOCK_MEMv_GPRv 1072 +OR_LOCK_MEMv_IMMb 1073 +OR_LOCK_MEMv_IMMz 1074 +OUT_DX_AL 1075 +OUT_DX_OeAX 1076 +OUT_IMMb_AL 1077 +OUT_IMMb_OeAX 1078 +OUTSB 1079 +OUTSD 1080 +OUTSW 1081 +PABSB_MMXq_MEMq 1082 +PABSB_MMXq_MMXq 1083 +PABSB_XMMdq_MEMdq 1084 +PABSB_XMMdq_XMMdq 1085 +PABSD_MMXq_MEMq 1086 +PABSD_MMXq_MMXq 1087 +PABSD_XMMdq_MEMdq 1088 +PABSD_XMMdq_XMMdq 1089 +PABSW_MMXq_MEMq 1090 +PABSW_MMXq_MMXq 1091 +PABSW_XMMdq_MEMdq 1092 +PABSW_XMMdq_XMMdq 1093 +PACKSSDW_MMXq_MEMq 1094 +PACKSSDW_MMXq_MMXq 1095 +PACKSSDW_XMMdq_MEMdq 1096 +PACKSSDW_XMMdq_XMMdq 1097 +PACKSSWB_MMXq_MEMq 1098 +PACKSSWB_MMXq_MMXq 1099 +PACKSSWB_XMMdq_MEMdq 1100 +PACKSSWB_XMMdq_XMMdq 1101 +PACKUSDW_XMMdq_MEMdq 1102 +PACKUSDW_XMMdq_XMMdq 1103 +PACKUSWB_MMXq_MEMq 1104 +PACKUSWB_MMXq_MMXq 1105 +PACKUSWB_XMMdq_MEMdq 1106 +PACKUSWB_XMMdq_XMMdq 1107 +PADDB_MMXq_MEMq 1108 +PADDB_MMXq_MMXq 1109 +PADDB_XMMdq_MEMdq 1110 +PADDB_XMMdq_XMMdq 1111 +PADDD_MMXq_MEMq 1112 +PADDD_MMXq_MMXq 1113 +PADDD_XMMdq_MEMdq 1114 +PADDD_XMMdq_XMMdq 1115 +PADDQ_MMXq_MEMq 1116 +PADDQ_MMXq_MMXq 1117 +PADDQ_XMMdq_MEMdq 1118 +PADDQ_XMMdq_XMMdq 1119 +PADDSB_MMXq_MEMq 1120 +PADDSB_MMXq_MMXq 1121 +PADDSB_XMMdq_MEMdq 1122 +PADDSB_XMMdq_XMMdq 1123 +PADDSW_MMXq_MEMq 1124 +PADDSW_MMXq_MMXq 1125 +PADDSW_XMMdq_MEMdq 1126 +PADDSW_XMMdq_XMMdq 1127 +PADDUSB_MMXq_MEMq 1128 +PADDUSB_MMXq_MMXq 1129 +PADDUSB_XMMdq_MEMdq 1130 +PADDUSB_XMMdq_XMMdq 1131 +PADDUSW_MMXq_MEMq 1132 +PADDUSW_MMXq_MMXq 1133 +PADDUSW_XMMdq_MEMdq 1134 +PADDUSW_XMMdq_XMMdq 1135 +PADDW_MMXq_MEMq 1136 +PADDW_MMXq_MMXq 1137 +PADDW_XMMdq_MEMdq 1138 +PADDW_XMMdq_XMMdq 1139 +PALIGNR_MMXq_MEMq_IMMb 1140 +PALIGNR_MMXq_MMXq_IMMb 1141 +PALIGNR_XMMdq_MEMdq_IMMb 1142 +PALIGNR_XMMdq_XMMdq_IMMb 1143 +PAND_MMXq_MEMq 1144 +PAND_MMXq_MMXq 1145 +PAND_XMMdq_MEMdq 1146 +PAND_XMMdq_XMMdq 1147 +PANDN_MMXq_MEMq 1148 +PANDN_MMXq_MMXq 1149 +PANDN_XMMdq_MEMdq 1150 +PANDN_XMMdq_XMMdq 1151 +PAUSE 1152 +PAVGB_MMXq_MEMq 1153 +PAVGB_MMXq_MMXq 1154 +PAVGB_XMMdq_MEMdq 1155 +PAVGB_XMMdq_XMMdq 1156 +PAVGUSB_MMXq_MEMq 1157 +PAVGUSB_MMXq_MMXq 1158 +PAVGW_MMXq_MEMq 1159 +PAVGW_MMXq_MMXq 1160 +PAVGW_XMMdq_MEMdq 1161 +PAVGW_XMMdq_XMMdq 1162 +PBLENDVB_XMMdq_MEMdq 1163 +PBLENDVB_XMMdq_XMMdq 1164 +PBLENDW_XMMdq_MEMdq_IMMb 1165 +PBLENDW_XMMdq_XMMdq_IMMb 1166 +PCLMULQDQ_XMMdq_MEMdq_IMMb 1167 +PCLMULQDQ_XMMdq_XMMdq_IMMb 1168 +PCMPEQB_MMXq_MEMq 1169 +PCMPEQB_MMXq_MMXq 1170 +PCMPEQB_XMMdq_MEMdq 1171 +PCMPEQB_XMMdq_XMMdq 1172 +PCMPEQD_MMXq_MEMq 1173 +PCMPEQD_MMXq_MMXq 1174 +PCMPEQD_XMMdq_MEMdq 1175 +PCMPEQD_XMMdq_XMMdq 1176 +PCMPEQQ_XMMdq_MEMdq 1177 +PCMPEQQ_XMMdq_XMMdq 1178 +PCMPEQW_MMXq_MEMq 1179 +PCMPEQW_MMXq_MMXq 1180 +PCMPEQW_XMMdq_MEMdq 1181 +PCMPEQW_XMMdq_XMMdq 1182 +PCMPESTRI_XMMdq_MEMdq_IMMb 1183 +PCMPESTRI_XMMdq_XMMdq_IMMb 1184 +PCMPESTRI64_XMMdq_MEMdq_IMMb 1185 +PCMPESTRI64_XMMdq_XMMdq_IMMb 1186 +PCMPESTRM_XMMdq_MEMdq_IMMb 1187 +PCMPESTRM_XMMdq_XMMdq_IMMb 1188 +PCMPESTRM64_XMMdq_MEMdq_IMMb 1189 +PCMPESTRM64_XMMdq_XMMdq_IMMb 1190 +PCMPGTB_MMXq_MEMq 1191 +PCMPGTB_MMXq_MMXq 1192 +PCMPGTB_XMMdq_MEMdq 1193 +PCMPGTB_XMMdq_XMMdq 1194 +PCMPGTD_MMXq_MEMq 1195 +PCMPGTD_MMXq_MMXq 1196 +PCMPGTD_XMMdq_MEMdq 1197 +PCMPGTD_XMMdq_XMMdq 1198 +PCMPGTQ_XMMdq_MEMdq 1199 +PCMPGTQ_XMMdq_XMMdq 1200 +PCMPGTW_MMXq_MEMq 1201 +PCMPGTW_MMXq_MMXq 1202 +PCMPGTW_XMMdq_MEMdq 1203 +PCMPGTW_XMMdq_XMMdq 1204 +PCMPISTRI_XMMdq_MEMdq_IMMb 1205 +PCMPISTRI_XMMdq_XMMdq_IMMb 1206 +PCMPISTRI64_XMMdq_MEMdq_IMMb 1207 +PCMPISTRI64_XMMdq_XMMdq_IMMb 1208 +PCMPISTRM_XMMdq_MEMdq_IMMb 1209 +PCMPISTRM_XMMdq_XMMdq_IMMb 1210 +PCONFIG 1211 +PCONFIG64 1212 +PDEP_VGPR32d_VGPR32d_MEMd 1213 +PDEP_VGPR32d_VGPR32d_VGPR32d 1214 +PDEP_VGPR64q_VGPR64q_MEMq 1215 +PDEP_VGPR64q_VGPR64q_VGPR64q 1216 +PEXT_VGPR32d_VGPR32d_MEMd 1217 +PEXT_VGPR32d_VGPR32d_VGPR32d 1218 +PEXT_VGPR64q_VGPR64q_MEMq 1219 +PEXT_VGPR64q_VGPR64q_VGPR64q 1220 +PEXTRB_GPR32d_XMMdq_IMMb 1221 +PEXTRB_MEMb_XMMdq_IMMb 1222 +PEXTRD_GPR32d_XMMdq_IMMb 1223 +PEXTRD_MEMd_XMMdq_IMMb 1224 +PEXTRQ_GPR64q_XMMdq_IMMb 1225 +PEXTRQ_MEMq_XMMdq_IMMb 1226 +PEXTRW_GPR32_MMXq_IMMb 1227 +PEXTRW_GPR32_XMMdq_IMMb 1228 +PEXTRW_SSE4_GPR32_XMMdq_IMMb 1229 +PEXTRW_SSE4_MEMw_XMMdq_IMMb 1230 +PF2ID_MMXq_MEMq 1231 +PF2ID_MMXq_MMXq 1232 +PF2IW_MMXq_MEMq 1233 +PF2IW_MMXq_MMXq 1234 +PFACC_MMXq_MEMq 1235 +PFACC_MMXq_MMXq 1236 +PFADD_MMXq_MEMq 1237 +PFADD_MMXq_MMXq 1238 +PFCMPEQ_MMXq_MEMq 1239 +PFCMPEQ_MMXq_MMXq 1240 +PFCMPGE_MMXq_MEMq 1241 +PFCMPGE_MMXq_MMXq 1242 +PFCMPGT_MMXq_MEMq 1243 +PFCMPGT_MMXq_MMXq 1244 +PFMAX_MMXq_MEMq 1245 +PFMAX_MMXq_MMXq 1246 +PFMIN_MMXq_MEMq 1247 +PFMIN_MMXq_MMXq 1248 +PFMUL_MMXq_MEMq 1249 +PFMUL_MMXq_MMXq 1250 +PFNACC_MMXq_MEMq 1251 +PFNACC_MMXq_MMXq 1252 +PFPNACC_MMXq_MEMq 1253 +PFPNACC_MMXq_MMXq 1254 +PFRCP_MMXq_MEMq 1255 +PFRCP_MMXq_MMXq 1256 +PFRCPIT1_MMXq_MEMq 1257 +PFRCPIT1_MMXq_MMXq 1258 +PFRCPIT2_MMXq_MEMq 1259 +PFRCPIT2_MMXq_MMXq 1260 +PFRSQIT1_MMXq_MEMq 1261 +PFRSQIT1_MMXq_MMXq 1262 +PFRSQRT_MMXq_MEMq 1263 +PFRSQRT_MMXq_MMXq 1264 +PFSUB_MMXq_MEMq 1265 +PFSUB_MMXq_MMXq 1266 +PFSUBR_MMXq_MEMq 1267 +PFSUBR_MMXq_MMXq 1268 +PHADDD_MMXq_MEMq 1269 +PHADDD_MMXq_MMXq 1270 +PHADDD_XMMdq_MEMdq 1271 +PHADDD_XMMdq_XMMdq 1272 +PHADDSW_MMXq_MEMq 1273 +PHADDSW_MMXq_MMXq 1274 +PHADDSW_XMMdq_MEMdq 1275 +PHADDSW_XMMdq_XMMdq 1276 +PHADDW_MMXq_MEMq 1277 +PHADDW_MMXq_MMXq 1278 +PHADDW_XMMdq_MEMdq 1279 +PHADDW_XMMdq_XMMdq 1280 +PHMINPOSUW_XMMdq_MEMdq 1281 +PHMINPOSUW_XMMdq_XMMdq 1282 +PHSUBD_MMXq_MEMq 1283 +PHSUBD_MMXq_MMXq 1284 +PHSUBD_XMMdq_MEMdq 1285 +PHSUBD_XMMdq_XMMdq 1286 +PHSUBSW_MMXq_MEMq 1287 +PHSUBSW_MMXq_MMXq 1288 +PHSUBSW_XMMdq_MEMdq 1289 +PHSUBSW_XMMdq_XMMdq 1290 +PHSUBW_MMXq_MEMq 1291 +PHSUBW_MMXq_MMXq 1292 +PHSUBW_XMMdq_MEMdq 1293 +PHSUBW_XMMdq_XMMdq 1294 +PI2FD_MMXq_MEMq 1295 +PI2FD_MMXq_MMXq 1296 +PI2FW_MMXq_MEMq 1297 +PI2FW_MMXq_MMXq 1298 +PINSRB_XMMdq_GPR32d_IMMb 1299 +PINSRB_XMMdq_MEMb_IMMb 1300 +PINSRD_XMMdq_GPR32d_IMMb 1301 +PINSRD_XMMdq_MEMd_IMMb 1302 +PINSRQ_XMMdq_GPR64q_IMMb 1303 +PINSRQ_XMMdq_MEMq_IMMb 1304 +PINSRW_MMXq_GPR32_IMMb 1305 +PINSRW_MMXq_MEMw_IMMb 1306 +PINSRW_XMMdq_GPR32_IMMb 1307 +PINSRW_XMMdq_MEMw_IMMb 1308 +PMADDUBSW_MMXq_MEMq 1309 +PMADDUBSW_MMXq_MMXq 1310 +PMADDUBSW_XMMdq_MEMdq 1311 +PMADDUBSW_XMMdq_XMMdq 1312 +PMADDWD_MMXq_MEMq 1313 +PMADDWD_MMXq_MMXq 1314 +PMADDWD_XMMdq_MEMdq 1315 +PMADDWD_XMMdq_XMMdq 1316 +PMAXSB_XMMdq_MEMdq 1317 +PMAXSB_XMMdq_XMMdq 1318 +PMAXSD_XMMdq_MEMdq 1319 +PMAXSD_XMMdq_XMMdq 1320 +PMAXSW_MMXq_MEMq 1321 +PMAXSW_MMXq_MMXq 1322 +PMAXSW_XMMdq_MEMdq 1323 +PMAXSW_XMMdq_XMMdq 1324 +PMAXUB_MMXq_MEMq 1325 +PMAXUB_MMXq_MMXq 1326 +PMAXUB_XMMdq_MEMdq 1327 +PMAXUB_XMMdq_XMMdq 1328 +PMAXUD_XMMdq_MEMdq 1329 +PMAXUD_XMMdq_XMMdq 1330 +PMAXUW_XMMdq_MEMdq 1331 +PMAXUW_XMMdq_XMMdq 1332 +PMINSB_XMMdq_MEMdq 1333 +PMINSB_XMMdq_XMMdq 1334 +PMINSD_XMMdq_MEMdq 1335 +PMINSD_XMMdq_XMMdq 1336 +PMINSW_MMXq_MEMq 1337 +PMINSW_MMXq_MMXq 1338 +PMINSW_XMMdq_MEMdq 1339 +PMINSW_XMMdq_XMMdq 1340 +PMINUB_MMXq_MEMq 1341 +PMINUB_MMXq_MMXq 1342 +PMINUB_XMMdq_MEMdq 1343 +PMINUB_XMMdq_XMMdq 1344 +PMINUD_XMMdq_MEMdq 1345 +PMINUD_XMMdq_XMMdq 1346 +PMINUW_XMMdq_MEMdq 1347 +PMINUW_XMMdq_XMMdq 1348 +PMOVMSKB_GPR32_MMXq 1349 +PMOVMSKB_GPR32_XMMdq 1350 +PMOVSXBD_XMMdq_MEMd 1351 +PMOVSXBD_XMMdq_XMMd 1352 +PMOVSXBQ_XMMdq_MEMw 1353 +PMOVSXBQ_XMMdq_XMMw 1354 +PMOVSXBW_XMMdq_MEMq 1355 +PMOVSXBW_XMMdq_XMMq 1356 +PMOVSXDQ_XMMdq_MEMq 1357 +PMOVSXDQ_XMMdq_XMMq 1358 +PMOVSXWD_XMMdq_MEMq 1359 +PMOVSXWD_XMMdq_XMMq 1360 +PMOVSXWQ_XMMdq_MEMd 1361 +PMOVSXWQ_XMMdq_XMMd 1362 +PMOVZXBD_XMMdq_MEMd 1363 +PMOVZXBD_XMMdq_XMMd 1364 +PMOVZXBQ_XMMdq_MEMw 1365 +PMOVZXBQ_XMMdq_XMMw 1366 +PMOVZXBW_XMMdq_MEMq 1367 +PMOVZXBW_XMMdq_XMMq 1368 +PMOVZXDQ_XMMdq_MEMq 1369 +PMOVZXDQ_XMMdq_XMMq 1370 +PMOVZXWD_XMMdq_MEMq 1371 +PMOVZXWD_XMMdq_XMMq 1372 +PMOVZXWQ_XMMdq_MEMd 1373 +PMOVZXWQ_XMMdq_XMMd 1374 +PMULDQ_XMMdq_MEMdq 1375 +PMULDQ_XMMdq_XMMdq 1376 +PMULHRSW_MMXq_MEMq 1377 +PMULHRSW_MMXq_MMXq 1378 +PMULHRSW_XMMdq_MEMdq 1379 +PMULHRSW_XMMdq_XMMdq 1380 +PMULHRW_MMXq_MEMq 1381 +PMULHRW_MMXq_MMXq 1382 +PMULHUW_MMXq_MEMq 1383 +PMULHUW_MMXq_MMXq 1384 +PMULHUW_XMMdq_MEMdq 1385 +PMULHUW_XMMdq_XMMdq 1386 +PMULHW_MMXq_MEMq 1387 +PMULHW_MMXq_MMXq 1388 +PMULHW_XMMdq_MEMdq 1389 +PMULHW_XMMdq_XMMdq 1390 +PMULLD_XMMdq_MEMdq 1391 +PMULLD_XMMdq_XMMdq 1392 +PMULLW_MMXq_MEMq 1393 +PMULLW_MMXq_MMXq 1394 +PMULLW_XMMdq_MEMdq 1395 +PMULLW_XMMdq_XMMdq 1396 +PMULUDQ_MMXq_MEMq 1397 +PMULUDQ_MMXq_MMXq 1398 +PMULUDQ_XMMdq_MEMdq 1399 +PMULUDQ_XMMdq_XMMdq 1400 +POP_DS 1401 +POP_ES 1402 +POP_FS 1403 +POP_GPRv_58 1404 +POP_GPRv_8F 1405 +POP_GS 1406 +POP_MEMv 1407 +POP_SS 1408 +POPA 1409 +POPAD 1410 +POPCNT_GPRv_GPRv 1411 +POPCNT_GPRv_MEMv 1412 +POPF 1413 +POPFD 1414 +POPFQ 1415 +POR_MMXq_MEMq 1416 +POR_MMXq_MMXq 1417 +POR_XMMdq_MEMdq 1418 +POR_XMMdq_XMMdq 1419 +PREFETCHNTA_MEMmprefetch 1420 +PREFETCHT0_MEMmprefetch 1421 +PREFETCHT1_MEMmprefetch 1422 +PREFETCHT2_MEMmprefetch 1423 +PREFETCHW_0F0Dr1 1424 +PREFETCHW_0F0Dr3 1425 +PREFETCHWT1_MEMu8 1426 +PREFETCH_EXCLUSIVE_MEMmprefetch 1427 +PREFETCH_RESERVED_0F0Dr4 1428 +PREFETCH_RESERVED_0F0Dr5 1429 +PREFETCH_RESERVED_0F0Dr6 1430 +PREFETCH_RESERVED_0F0Dr7 1431 +PSADBW_MMXq_MEMq 1432 +PSADBW_MMXq_MMXq 1433 +PSADBW_XMMdq_MEMdq 1434 +PSADBW_XMMdq_XMMdq 1435 +PSHUFB_MMXq_MEMq 1436 +PSHUFB_MMXq_MMXq 1437 +PSHUFB_XMMdq_MEMdq 1438 +PSHUFB_XMMdq_XMMdq 1439 +PSHUFD_XMMdq_MEMdq_IMMb 1440 +PSHUFD_XMMdq_XMMdq_IMMb 1441 +PSHUFHW_XMMdq_MEMdq_IMMb 1442 +PSHUFHW_XMMdq_XMMdq_IMMb 1443 +PSHUFLW_XMMdq_MEMdq_IMMb 1444 +PSHUFLW_XMMdq_XMMdq_IMMb 1445 +PSHUFW_MMXq_MEMq_IMMb 1446 +PSHUFW_MMXq_MMXq_IMMb 1447 +PSIGNB_MMXq_MEMq 1448 +PSIGNB_MMXq_MMXq 1449 +PSIGNB_XMMdq_MEMdq 1450 +PSIGNB_XMMdq_XMMdq 1451 +PSIGND_MMXq_MEMq 1452 +PSIGND_MMXq_MMXq 1453 +PSIGND_XMMdq_MEMdq 1454 +PSIGND_XMMdq_XMMdq 1455 +PSIGNW_MMXq_MEMq 1456 +PSIGNW_MMXq_MMXq 1457 +PSIGNW_XMMdq_MEMdq 1458 +PSIGNW_XMMdq_XMMdq 1459 +PSLLD_MMXq_IMMb 1460 +PSLLD_MMXq_MEMq 1461 +PSLLD_MMXq_MMXq 1462 +PSLLD_XMMdq_IMMb 1463 +PSLLD_XMMdq_MEMdq 1464 +PSLLD_XMMdq_XMMdq 1465 +PSLLDQ_XMMdq_IMMb 1466 +PSLLQ_MMXq_IMMb 1467 +PSLLQ_MMXq_MEMq 1468 +PSLLQ_MMXq_MMXq 1469 +PSLLQ_XMMdq_IMMb 1470 +PSLLQ_XMMdq_MEMdq 1471 +PSLLQ_XMMdq_XMMdq 1472 +PSLLW_MMXq_IMMb 1473 +PSLLW_MMXq_MEMq 1474 +PSLLW_MMXq_MMXq 1475 +PSLLW_XMMdq_IMMb 1476 +PSLLW_XMMdq_MEMdq 1477 +PSLLW_XMMdq_XMMdq 1478 +PSMASH_RAX 1479 +PSRAD_MMXq_IMMb 1480 +PSRAD_MMXq_MEMq 1481 +PSRAD_MMXq_MMXq 1482 +PSRAD_XMMdq_IMMb 1483 +PSRAD_XMMdq_MEMdq 1484 +PSRAD_XMMdq_XMMdq 1485 +PSRAW_MMXq_IMMb 1486 +PSRAW_MMXq_MEMq 1487 +PSRAW_MMXq_MMXq 1488 +PSRAW_XMMdq_IMMb 1489 +PSRAW_XMMdq_MEMdq 1490 +PSRAW_XMMdq_XMMdq 1491 +PSRLD_MMXq_IMMb 1492 +PSRLD_MMXq_MEMq 1493 +PSRLD_MMXq_MMXq 1494 +PSRLD_XMMdq_IMMb 1495 +PSRLD_XMMdq_MEMdq 1496 +PSRLD_XMMdq_XMMdq 1497 +PSRLDQ_XMMdq_IMMb 1498 +PSRLQ_MMXq_IMMb 1499 +PSRLQ_MMXq_MEMq 1500 +PSRLQ_MMXq_MMXq 1501 +PSRLQ_XMMdq_IMMb 1502 +PSRLQ_XMMdq_MEMdq 1503 +PSRLQ_XMMdq_XMMdq 1504 +PSRLW_MMXq_IMMb 1505 +PSRLW_MMXq_MEMq 1506 +PSRLW_MMXq_MMXq 1507 +PSRLW_XMMdq_IMMb 1508 +PSRLW_XMMdq_MEMdq 1509 +PSRLW_XMMdq_XMMdq 1510 +PSUBB_MMXq_MEMq 1511 +PSUBB_MMXq_MMXq 1512 +PSUBB_XMMdq_MEMdq 1513 +PSUBB_XMMdq_XMMdq 1514 +PSUBD_MMXq_MEMq 1515 +PSUBD_MMXq_MMXq 1516 +PSUBD_XMMdq_MEMdq 1517 +PSUBD_XMMdq_XMMdq 1518 +PSUBQ_MMXq_MEMq 1519 +PSUBQ_MMXq_MMXq 1520 +PSUBQ_XMMdq_MEMdq 1521 +PSUBQ_XMMdq_XMMdq 1522 +PSUBSB_MMXq_MEMq 1523 +PSUBSB_MMXq_MMXq 1524 +PSUBSB_XMMdq_MEMdq 1525 +PSUBSB_XMMdq_XMMdq 1526 +PSUBSW_MMXq_MEMq 1527 +PSUBSW_MMXq_MMXq 1528 +PSUBSW_XMMdq_MEMdq 1529 +PSUBSW_XMMdq_XMMdq 1530 +PSUBUSB_MMXq_MEMq 1531 +PSUBUSB_MMXq_MMXq 1532 +PSUBUSB_XMMdq_MEMdq 1533 +PSUBUSB_XMMdq_XMMdq 1534 +PSUBUSW_MMXq_MEMq 1535 +PSUBUSW_MMXq_MMXq 1536 +PSUBUSW_XMMdq_MEMdq 1537 +PSUBUSW_XMMdq_XMMdq 1538 +PSUBW_MMXq_MEMq 1539 +PSUBW_MMXq_MMXq 1540 +PSUBW_XMMdq_MEMdq 1541 +PSUBW_XMMdq_XMMdq 1542 +PSWAPD_MMXq_MEMq 1543 +PSWAPD_MMXq_MMXq 1544 +PTEST_XMMdq_MEMdq 1545 +PTEST_XMMdq_XMMdq 1546 +PTWRITE_GPRy 1547 +PTWRITE_MEMy 1548 +PUNPCKHBW_MMXq_MEMq 1549 +PUNPCKHBW_MMXq_MMXd 1550 +PUNPCKHBW_XMMdq_MEMdq 1551 +PUNPCKHBW_XMMdq_XMMq 1552 +PUNPCKHDQ_MMXq_MEMq 1553 +PUNPCKHDQ_MMXq_MMXd 1554 +PUNPCKHDQ_XMMdq_MEMdq 1555 +PUNPCKHDQ_XMMdq_XMMq 1556 +PUNPCKHQDQ_XMMdq_MEMdq 1557 +PUNPCKHQDQ_XMMdq_XMMq 1558 +PUNPCKHWD_MMXq_MEMq 1559 +PUNPCKHWD_MMXq_MMXd 1560 +PUNPCKHWD_XMMdq_MEMdq 1561 +PUNPCKHWD_XMMdq_XMMq 1562 +PUNPCKLBW_MMXq_MEMd 1563 +PUNPCKLBW_MMXq_MMXd 1564 +PUNPCKLBW_XMMdq_MEMdq 1565 +PUNPCKLBW_XMMdq_XMMq 1566 +PUNPCKLDQ_MMXq_MEMd 1567 +PUNPCKLDQ_MMXq_MMXd 1568 +PUNPCKLDQ_XMMdq_MEMdq 1569 +PUNPCKLDQ_XMMdq_XMMq 1570 +PUNPCKLQDQ_XMMdq_MEMdq 1571 +PUNPCKLQDQ_XMMdq_XMMq 1572 +PUNPCKLWD_MMXq_MEMd 1573 +PUNPCKLWD_MMXq_MMXd 1574 +PUNPCKLWD_XMMdq_MEMdq 1575 +PUNPCKLWD_XMMdq_XMMq 1576 +PUSH_CS 1577 +PUSH_DS 1578 +PUSH_ES 1579 +PUSH_FS 1580 +PUSH_GPRv_50 1581 +PUSH_GPRv_FFr6 1582 +PUSH_GS 1583 +PUSH_IMMb 1584 +PUSH_IMMz 1585 +PUSH_MEMv 1586 +PUSH_SS 1587 +PUSHA 1588 +PUSHAD 1589 +PUSHF 1590 +PUSHFD 1591 +PUSHFQ 1592 +PVALIDATE_RAX_ECX_EDX 1593 +PXOR_MMXq_MEMq 1594 +PXOR_MMXq_MMXq 1595 +PXOR_XMMdq_MEMdq 1596 +PXOR_XMMdq_XMMdq 1597 +RCL_GPR8_CL 1598 +RCL_GPR8_IMMb 1599 +RCL_GPR8_ONE 1600 +RCL_GPRv_CL 1601 +RCL_GPRv_IMMb 1602 +RCL_GPRv_ONE 1603 +RCL_MEMb_CL 1604 +RCL_MEMb_IMMb 1605 +RCL_MEMb_ONE 1606 +RCL_MEMv_CL 1607 +RCL_MEMv_IMMb 1608 +RCL_MEMv_ONE 1609 +RCPPS_XMMps_MEMps 1610 +RCPPS_XMMps_XMMps 1611 +RCPSS_XMMss_MEMss 1612 +RCPSS_XMMss_XMMss 1613 +RCR_GPR8_CL 1614 +RCR_GPR8_IMMb 1615 +RCR_GPR8_ONE 1616 +RCR_GPRv_CL 1617 +RCR_GPRv_IMMb 1618 +RCR_GPRv_ONE 1619 +RCR_MEMb_CL 1620 +RCR_MEMb_IMMb 1621 +RCR_MEMb_ONE 1622 +RCR_MEMv_CL 1623 +RCR_MEMv_IMMb 1624 +RCR_MEMv_ONE 1625 +RDFSBASE_GPRy 1626 +RDGSBASE_GPRy 1627 +RDMSR 1628 +RDPID_GPR32u32 1629 +RDPID_GPR64u64 1630 +RDPKRU 1631 +RDPMC 1632 +RDPRU 1633 +RDRAND_GPRv 1634 +RDSEED_GPRv 1635 +RDSSPD_GPR32u32 1636 +RDSSPQ_GPR64u64 1637 +RDTSC 1638 +RDTSCP 1639 +REPE_CMPSB 1640 +REPE_CMPSD 1641 +REPE_CMPSQ 1642 +REPE_CMPSW 1643 +REPE_SCASB 1644 +REPE_SCASD 1645 +REPE_SCASQ 1646 +REPE_SCASW 1647 +REPNE_CMPSB 1648 +REPNE_CMPSD 1649 +REPNE_CMPSQ 1650 +REPNE_CMPSW 1651 +REPNE_SCASB 1652 +REPNE_SCASD 1653 +REPNE_SCASQ 1654 +REPNE_SCASW 1655 +REP_INSB 1656 +REP_INSD 1657 +REP_INSW 1658 +REP_LODSB 1659 +REP_LODSD 1660 +REP_LODSQ 1661 +REP_LODSW 1662 +REP_MONTMUL 1663 +REP_MOVSB 1664 +REP_MOVSD 1665 +REP_MOVSQ 1666 +REP_MOVSW 1667 +REP_OUTSB 1668 +REP_OUTSD 1669 +REP_OUTSW 1670 +REP_STOSB 1671 +REP_STOSD 1672 +REP_STOSQ 1673 +REP_STOSW 1674 +REP_XCRYPTCBC 1675 +REP_XCRYPTCFB 1676 +REP_XCRYPTCTR 1677 +REP_XCRYPTECB 1678 +REP_XCRYPTOFB 1679 +REP_XSHA1 1680 +REP_XSHA256 1681 +REP_XSTORE 1682 +RET_FAR 1683 +RET_FAR_IMMw 1684 +RET_NEAR 1685 +RET_NEAR_IMMw 1686 +RMPADJUST_RAX_RCX_RDX 1687 +RMPUPDATE_RAX_RCX 1688 +ROL_GPR8_CL 1689 +ROL_GPR8_IMMb 1690 +ROL_GPR8_ONE 1691 +ROL_GPRv_CL 1692 +ROL_GPRv_IMMb 1693 +ROL_GPRv_ONE 1694 +ROL_MEMb_CL 1695 +ROL_MEMb_IMMb 1696 +ROL_MEMb_ONE 1697 +ROL_MEMv_CL 1698 +ROL_MEMv_IMMb 1699 +ROL_MEMv_ONE 1700 +ROR_GPR8_CL 1701 +ROR_GPR8_IMMb 1702 +ROR_GPR8_ONE 1703 +ROR_GPRv_CL 1704 +ROR_GPRv_IMMb 1705 +ROR_GPRv_ONE 1706 +ROR_MEMb_CL 1707 +ROR_MEMb_IMMb 1708 +ROR_MEMb_ONE 1709 +ROR_MEMv_CL 1710 +ROR_MEMv_IMMb 1711 +ROR_MEMv_ONE 1712 +RORX_VGPR32d_MEMd_IMMb 1713 +RORX_VGPR32d_VGPR32d_IMMb 1714 +RORX_VGPR64q_MEMq_IMMb 1715 +RORX_VGPR64q_VGPR64q_IMMb 1716 +ROUNDPD_XMMpd_MEMpd_IMMb 1717 +ROUNDPD_XMMpd_XMMpd_IMMb 1718 +ROUNDPS_XMMps_MEMps_IMMb 1719 +ROUNDPS_XMMps_XMMps_IMMb 1720 +ROUNDSD_XMMq_MEMq_IMMb 1721 +ROUNDSD_XMMq_XMMq_IMMb 1722 +ROUNDSS_XMMd_MEMd_IMMb 1723 +ROUNDSS_XMMd_XMMd_IMMb 1724 +RSM 1725 +RSQRTPS_XMMps_MEMps 1726 +RSQRTPS_XMMps_XMMps 1727 +RSQRTSS_XMMss_MEMss 1728 +RSQRTSS_XMMss_XMMss 1729 +RSTORSSP_MEMu64 1730 +SAHF 1731 +SALC 1732 +SAR_GPR8_CL 1733 +SAR_GPR8_IMMb 1734 +SAR_GPR8_ONE 1735 +SAR_GPRv_CL 1736 +SAR_GPRv_IMMb 1737 +SAR_GPRv_ONE 1738 +SAR_MEMb_CL 1739 +SAR_MEMb_IMMb 1740 +SAR_MEMb_ONE 1741 +SAR_MEMv_CL 1742 +SAR_MEMv_IMMb 1743 +SAR_MEMv_ONE 1744 +SARX_VGPR32d_MEMd_VGPR32d 1745 +SARX_VGPR32d_VGPR32d_VGPR32d 1746 +SARX_VGPR64q_MEMq_VGPR64q 1747 +SARX_VGPR64q_VGPR64q_VGPR64q 1748 +SAVEPREVSSP 1749 +SBB_AL_IMMb 1750 +SBB_GPR8_GPR8_18 1751 +SBB_GPR8_GPR8_1A 1752 +SBB_GPR8_IMMb_80r3 1753 +SBB_GPR8_IMMb_82r3 1754 +SBB_GPR8_MEMb 1755 +SBB_GPRv_GPRv_19 1756 +SBB_GPRv_GPRv_1B 1757 +SBB_GPRv_IMMb 1758 +SBB_GPRv_IMMz 1759 +SBB_GPRv_MEMv 1760 +SBB_MEMb_GPR8 1761 +SBB_MEMb_IMMb_80r3 1762 +SBB_MEMb_IMMb_82r3 1763 +SBB_MEMv_GPRv 1764 +SBB_MEMv_IMMb 1765 +SBB_MEMv_IMMz 1766 +SBB_OrAX_IMMz 1767 +SBB_LOCK_MEMb_GPR8 1768 +SBB_LOCK_MEMb_IMMb_80r3 1769 +SBB_LOCK_MEMb_IMMb_82r3 1770 +SBB_LOCK_MEMv_GPRv 1771 +SBB_LOCK_MEMv_IMMb 1772 +SBB_LOCK_MEMv_IMMz 1773 +SCASB 1774 +SCASD 1775 +SCASQ 1776 +SCASW 1777 +SEAMCALL 1778 +SEAMOPS 1779 +SEAMRET 1780 +SENDUIPI_GPR32u32 1781 +SERIALIZE 1782 +SETB_GPR8 1783 +SETB_MEMb 1784 +SETBE_GPR8 1785 +SETBE_MEMb 1786 +SETL_GPR8 1787 +SETL_MEMb 1788 +SETLE_GPR8 1789 +SETLE_MEMb 1790 +SETNB_GPR8 1791 +SETNB_MEMb 1792 +SETNBE_GPR8 1793 +SETNBE_MEMb 1794 +SETNL_GPR8 1795 +SETNL_MEMb 1796 +SETNLE_GPR8 1797 +SETNLE_MEMb 1798 +SETNO_GPR8 1799 +SETNO_MEMb 1800 +SETNP_GPR8 1801 +SETNP_MEMb 1802 +SETNS_GPR8 1803 +SETNS_MEMb 1804 +SETNZ_GPR8 1805 +SETNZ_MEMb 1806 +SETO_GPR8 1807 +SETO_MEMb 1808 +SETP_GPR8 1809 +SETP_MEMb 1810 +SETS_GPR8 1811 +SETS_MEMb 1812 +SETSSBSY 1813 +SETZ_GPR8 1814 +SETZ_MEMb 1815 +SFENCE 1816 +SGDT_MEMs 1817 +SGDT_MEMs64 1818 +SHA1MSG1_XMMi32_MEMi32_SHA 1819 +SHA1MSG1_XMMi32_XMMi32_SHA 1820 +SHA1MSG2_XMMi32_MEMi32_SHA 1821 +SHA1MSG2_XMMi32_XMMi32_SHA 1822 +SHA1NEXTE_XMMi32_MEMi32_SHA 1823 +SHA1NEXTE_XMMi32_XMMi32_SHA 1824 +SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA 1825 +SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA 1826 +SHA256MSG1_XMMi32_MEMi32_SHA 1827 +SHA256MSG1_XMMi32_XMMi32_SHA 1828 +SHA256MSG2_XMMi32_MEMi32_SHA 1829 +SHA256MSG2_XMMi32_XMMi32_SHA 1830 +SHA256RNDS2_XMMi32_MEMi32_SHA 1831 +SHA256RNDS2_XMMi32_XMMi32_SHA 1832 +SHL_GPR8_CL_D2r4 1833 +SHL_GPR8_CL_D2r6 1834 +SHL_GPR8_IMMb_C0r4 1835 +SHL_GPR8_IMMb_C0r6 1836 +SHL_GPR8_ONE_D0r4 1837 +SHL_GPR8_ONE_D0r6 1838 +SHL_GPRv_CL_D3r4 1839 +SHL_GPRv_CL_D3r6 1840 +SHL_GPRv_IMMb_C1r4 1841 +SHL_GPRv_IMMb_C1r6 1842 +SHL_GPRv_ONE_D1r4 1843 +SHL_GPRv_ONE_D1r6 1844 +SHL_MEMb_CL_D2r4 1845 +SHL_MEMb_CL_D2r6 1846 +SHL_MEMb_IMMb_C0r4 1847 +SHL_MEMb_IMMb_C0r6 1848 +SHL_MEMb_ONE_D0r4 1849 +SHL_MEMb_ONE_D0r6 1850 +SHL_MEMv_CL_D3r4 1851 +SHL_MEMv_CL_D3r6 1852 +SHL_MEMv_IMMb_C1r4 1853 +SHL_MEMv_IMMb_C1r6 1854 +SHL_MEMv_ONE_D1r4 1855 +SHL_MEMv_ONE_D1r6 1856 +SHLD_GPRv_GPRv_CL 1857 +SHLD_GPRv_GPRv_IMMb 1858 +SHLD_MEMv_GPRv_CL 1859 +SHLD_MEMv_GPRv_IMMb 1860 +SHLX_VGPR32d_MEMd_VGPR32d 1861 +SHLX_VGPR32d_VGPR32d_VGPR32d 1862 +SHLX_VGPR64q_MEMq_VGPR64q 1863 +SHLX_VGPR64q_VGPR64q_VGPR64q 1864 +SHR_GPR8_CL 1865 +SHR_GPR8_IMMb 1866 +SHR_GPR8_ONE 1867 +SHR_GPRv_CL 1868 +SHR_GPRv_IMMb 1869 +SHR_GPRv_ONE 1870 +SHR_MEMb_CL 1871 +SHR_MEMb_IMMb 1872 +SHR_MEMb_ONE 1873 +SHR_MEMv_CL 1874 +SHR_MEMv_IMMb 1875 +SHR_MEMv_ONE 1876 +SHRD_GPRv_GPRv_CL 1877 +SHRD_GPRv_GPRv_IMMb 1878 +SHRD_MEMv_GPRv_CL 1879 +SHRD_MEMv_GPRv_IMMb 1880 +SHRX_VGPR32d_MEMd_VGPR32d 1881 +SHRX_VGPR32d_VGPR32d_VGPR32d 1882 +SHRX_VGPR64q_MEMq_VGPR64q 1883 +SHRX_VGPR64q_VGPR64q_VGPR64q 1884 +SHUFPD_XMMpd_MEMpd_IMMb 1885 +SHUFPD_XMMpd_XMMpd_IMMb 1886 +SHUFPS_XMMps_MEMps_IMMb 1887 +SHUFPS_XMMps_XMMps_IMMb 1888 +SIDT_MEMs 1889 +SIDT_MEMs64 1890 +SKINIT_EAX 1891 +SLDT_GPRv 1892 +SLDT_MEMw 1893 +SLWPCB_VGPRyy 1894 +SMSW_GPRv 1895 +SMSW_MEMw 1896 +SQRTPD_XMMpd_MEMpd 1897 +SQRTPD_XMMpd_XMMpd 1898 +SQRTPS_XMMps_MEMps 1899 +SQRTPS_XMMps_XMMps 1900 +SQRTSD_XMMsd_MEMsd 1901 +SQRTSD_XMMsd_XMMsd 1902 +SQRTSS_XMMss_MEMss 1903 +SQRTSS_XMMss_XMMss 1904 +STAC 1905 +STC 1906 +STD 1907 +STGI 1908 +STI 1909 +STMXCSR_MEMd 1910 +STOSB 1911 +STOSD 1912 +STOSQ 1913 +STOSW 1914 +STR_GPRv 1915 +STR_MEMw 1916 +STTILECFG_MEM 1917 +STUI 1918 +SUB_AL_IMMb 1919 +SUB_GPR8_GPR8_28 1920 +SUB_GPR8_GPR8_2A 1921 +SUB_GPR8_IMMb_80r5 1922 +SUB_GPR8_IMMb_82r5 1923 +SUB_GPR8_MEMb 1924 +SUB_GPRv_GPRv_29 1925 +SUB_GPRv_GPRv_2B 1926 +SUB_GPRv_IMMb 1927 +SUB_GPRv_IMMz 1928 +SUB_GPRv_MEMv 1929 +SUB_MEMb_GPR8 1930 +SUB_MEMb_IMMb_80r5 1931 +SUB_MEMb_IMMb_82r5 1932 +SUB_MEMv_GPRv 1933 +SUB_MEMv_IMMb 1934 +SUB_MEMv_IMMz 1935 +SUB_OrAX_IMMz 1936 +SUBPD_XMMpd_MEMpd 1937 +SUBPD_XMMpd_XMMpd 1938 +SUBPS_XMMps_MEMps 1939 +SUBPS_XMMps_XMMps 1940 +SUBSD_XMMsd_MEMsd 1941 +SUBSD_XMMsd_XMMsd 1942 +SUBSS_XMMss_MEMss 1943 +SUBSS_XMMss_XMMss 1944 +SUB_LOCK_MEMb_GPR8 1945 +SUB_LOCK_MEMb_IMMb_80r5 1946 +SUB_LOCK_MEMb_IMMb_82r5 1947 +SUB_LOCK_MEMv_GPRv 1948 +SUB_LOCK_MEMv_IMMb 1949 +SUB_LOCK_MEMv_IMMz 1950 +SWAPGS 1951 +SYSCALL 1952 +SYSCALL_AMD 1953 +SYSENTER 1954 +SYSEXIT 1955 +SYSRET 1956 +SYSRET64 1957 +SYSRET_AMD 1958 +T1MSKC_VGPR32d_MEMd 1959 +T1MSKC_VGPR32d_VGPR32d 1960 +T1MSKC_VGPRyy_MEMy 1961 +T1MSKC_VGPRyy_VGPRyy 1962 +TDCALL 1963 +TDPBF16PS_TMMf32_TMMu32_TMMu32 1964 +TDPBSSD_TMMi32_TMMu32_TMMu32 1965 +TDPBSUD_TMMi32_TMMu32_TMMu32 1966 +TDPBUSD_TMMi32_TMMu32_TMMu32 1967 +TDPBUUD_TMMu32_TMMu32_TMMu32 1968 +TEST_AL_IMMb 1969 +TEST_GPR8_GPR8 1970 +TEST_GPR8_IMMb_F6r0 1971 +TEST_GPR8_IMMb_F6r1 1972 +TEST_GPRv_GPRv 1973 +TEST_GPRv_IMMz_F7r0 1974 +TEST_GPRv_IMMz_F7r1 1975 +TEST_MEMb_GPR8 1976 +TEST_MEMb_IMMb_F6r0 1977 +TEST_MEMb_IMMb_F6r1 1978 +TEST_MEMv_GPRv 1979 +TEST_MEMv_IMMz_F7r0 1980 +TEST_MEMv_IMMz_F7r1 1981 +TEST_OrAX_IMMz 1982 +TESTUI 1983 +TILELOADD_TMMu32_MEMu32 1984 +TILELOADDT1_TMMu32_MEMu32 1985 +TILERELEASE 1986 +TILESTORED_MEMu32_TMMu32 1987 +TILEZERO_TMMu32 1988 +TLBSYNC 1989 +TPAUSE_GPR32u32 1990 +TZCNT_GPRv_GPRv 1991 +TZCNT_GPRv_MEMv 1992 +TZMSK_VGPR32d_MEMd 1993 +TZMSK_VGPR32d_VGPR32d 1994 +TZMSK_VGPRyy_MEMy 1995 +TZMSK_VGPRyy_VGPRyy 1996 +UCOMISD_XMMsd_MEMsd 1997 +UCOMISD_XMMsd_XMMsd 1998 +UCOMISS_XMMss_MEMss 1999 +UCOMISS_XMMss_XMMss 2000 +UD0 2001 +UD0_GPR32_GPR32 2002 +UD0_GPR32_MEMd 2003 +UD1_GPR32_GPR32 2004 +UD1_GPR32_MEMd 2005 +UD2 2006 +UIRET 2007 +UMONITOR_GPRa 2008 +UMWAIT_GPR32 2009 +UNPCKHPD_XMMpd_MEMdq 2010 +UNPCKHPD_XMMpd_XMMq 2011 +UNPCKHPS_XMMps_MEMdq 2012 +UNPCKHPS_XMMps_XMMdq 2013 +UNPCKLPD_XMMpd_MEMdq 2014 +UNPCKLPD_XMMpd_XMMq 2015 +UNPCKLPS_XMMps_MEMdq 2016 +UNPCKLPS_XMMps_XMMq 2017 +V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2018 +V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2019 +V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2020 +V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2021 +VADDPD_XMMdq_XMMdq_MEMdq 2022 +VADDPD_XMMdq_XMMdq_XMMdq 2023 +VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2024 +VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2025 +VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 2026 +VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 2027 +VADDPD_YMMqq_YMMqq_MEMqq 2028 +VADDPD_YMMqq_YMMqq_YMMqq 2029 +VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 2030 +VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 2031 +VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2032 +VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2033 +VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 2034 +VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 2035 +VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 2036 +VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 2037 +VADDPS_XMMdq_XMMdq_MEMdq 2038 +VADDPS_XMMdq_XMMdq_XMMdq 2039 +VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2040 +VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2041 +VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 2042 +VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 2043 +VADDPS_YMMqq_YMMqq_MEMqq 2044 +VADDPS_YMMqq_YMMqq_YMMqq 2045 +VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2046 +VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 2047 +VADDSD_XMMdq_XMMdq_MEMq 2048 +VADDSD_XMMdq_XMMdq_XMMq 2049 +VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2050 +VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2051 +VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2052 +VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2053 +VADDSS_XMMdq_XMMdq_MEMd 2054 +VADDSS_XMMdq_XMMdq_XMMd 2055 +VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2056 +VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2057 +VADDSUBPD_XMMdq_XMMdq_MEMdq 2058 +VADDSUBPD_XMMdq_XMMdq_XMMdq 2059 +VADDSUBPD_YMMqq_YMMqq_MEMqq 2060 +VADDSUBPD_YMMqq_YMMqq_YMMqq 2061 +VADDSUBPS_XMMdq_XMMdq_MEMdq 2062 +VADDSUBPS_XMMdq_XMMdq_XMMdq 2063 +VADDSUBPS_YMMqq_YMMqq_MEMqq 2064 +VADDSUBPS_YMMqq_YMMqq_YMMqq 2065 +VAESDEC_XMMdq_XMMdq_MEMdq 2066 +VAESDEC_XMMdq_XMMdq_XMMdq 2067 +VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 2068 +VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 2069 +VAESDEC_YMMu128_YMMu128_MEMu128 2070 +VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 2071 +VAESDEC_YMMu128_YMMu128_YMMu128 2072 +VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 2073 +VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 2074 +VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 2075 +VAESDECLAST_XMMdq_XMMdq_MEMdq 2076 +VAESDECLAST_XMMdq_XMMdq_XMMdq 2077 +VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 2078 +VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 2079 +VAESDECLAST_YMMu128_YMMu128_MEMu128 2080 +VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 2081 +VAESDECLAST_YMMu128_YMMu128_YMMu128 2082 +VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 2083 +VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 2084 +VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 2085 +VAESENC_XMMdq_XMMdq_MEMdq 2086 +VAESENC_XMMdq_XMMdq_XMMdq 2087 +VAESENC_XMMu128_XMMu128_MEMu128_AVX512 2088 +VAESENC_XMMu128_XMMu128_XMMu128_AVX512 2089 +VAESENC_YMMu128_YMMu128_MEMu128 2090 +VAESENC_YMMu128_YMMu128_MEMu128_AVX512 2091 +VAESENC_YMMu128_YMMu128_YMMu128 2092 +VAESENC_YMMu128_YMMu128_YMMu128_AVX512 2093 +VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 2094 +VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 2095 +VAESENCLAST_XMMdq_XMMdq_MEMdq 2096 +VAESENCLAST_XMMdq_XMMdq_XMMdq 2097 +VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 2098 +VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 2099 +VAESENCLAST_YMMu128_YMMu128_MEMu128 2100 +VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 2101 +VAESENCLAST_YMMu128_YMMu128_YMMu128 2102 +VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 2103 +VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 2104 +VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 2105 +VAESIMC_XMMdq_MEMdq 2106 +VAESIMC_XMMdq_XMMdq 2107 +VAESKEYGENASSIST_XMMdq_MEMdq_IMMb 2108 +VAESKEYGENASSIST_XMMdq_XMMdq_IMMb 2109 +VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 2110 +VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 2111 +VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 2112 +VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 2113 +VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 2114 +VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 2115 +VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 2116 +VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 2117 +VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 2118 +VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 2119 +VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 2120 +VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 2121 +VANDNPD_XMMdq_XMMdq_MEMdq 2122 +VANDNPD_XMMdq_XMMdq_XMMdq 2123 +VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 2124 +VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 2125 +VANDNPD_YMMqq_YMMqq_MEMqq 2126 +VANDNPD_YMMqq_YMMqq_YMMqq 2127 +VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 2128 +VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 2129 +VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 2130 +VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 2131 +VANDNPS_XMMdq_XMMdq_MEMdq 2132 +VANDNPS_XMMdq_XMMdq_XMMdq 2133 +VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 2134 +VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 2135 +VANDNPS_YMMqq_YMMqq_MEMqq 2136 +VANDNPS_YMMqq_YMMqq_YMMqq 2137 +VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 2138 +VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 2139 +VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 2140 +VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 2141 +VANDPD_XMMdq_XMMdq_MEMdq 2142 +VANDPD_XMMdq_XMMdq_XMMdq 2143 +VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 2144 +VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 2145 +VANDPD_YMMqq_YMMqq_MEMqq 2146 +VANDPD_YMMqq_YMMqq_YMMqq 2147 +VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 2148 +VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 2149 +VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 2150 +VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 2151 +VANDPS_XMMdq_XMMdq_MEMdq 2152 +VANDPS_XMMdq_XMMdq_XMMdq 2153 +VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 2154 +VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 2155 +VANDPS_YMMqq_YMMqq_MEMqq 2156 +VANDPS_YMMqq_YMMqq_YMMqq 2157 +VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 2158 +VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 2159 +VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 2160 +VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 2161 +VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2162 +VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2163 +VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 2164 +VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 2165 +VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 2166 +VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 2167 +VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2168 +VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2169 +VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 2170 +VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 2171 +VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2172 +VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 2173 +VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb 2174 +VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb 2175 +VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb 2176 +VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb 2177 +VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb 2178 +VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb 2179 +VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb 2180 +VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb 2181 +VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq 2182 +VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq 2183 +VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq 2184 +VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq 2185 +VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq 2186 +VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq 2187 +VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq 2188 +VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq 2189 +VBROADCASTF128_YMMqq_MEMdq 2190 +VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 2191 +VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 2192 +VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 2193 +VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 2194 +VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 2195 +VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 2196 +VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 2197 +VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 2198 +VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 2199 +VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 2200 +VBROADCASTI128_YMMqq_MEMdq 2201 +VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 2202 +VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 2203 +VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 2204 +VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 2205 +VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 2206 +VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 2207 +VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 2208 +VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 2209 +VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 2210 +VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 2211 +VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 2212 +VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 2213 +VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 2214 +VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 2215 +VBROADCASTSD_YMMqq_MEMq 2216 +VBROADCASTSD_YMMqq_XMMdq 2217 +VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 2218 +VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 2219 +VBROADCASTSS_XMMdq_MEMd 2220 +VBROADCASTSS_XMMdq_XMMdq 2221 +VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 2222 +VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 2223 +VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 2224 +VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 2225 +VBROADCASTSS_YMMqq_MEMd 2226 +VBROADCASTSS_YMMqq_XMMdq 2227 +VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 2228 +VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 2229 +VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 2230 +VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 2231 +VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 2232 +VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 2233 +VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 2234 +VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 2235 +VCMPPD_XMMdq_XMMdq_MEMdq_IMMb 2236 +VCMPPD_XMMdq_XMMdq_XMMdq_IMMb 2237 +VCMPPD_YMMqq_YMMqq_MEMqq_IMMb 2238 +VCMPPD_YMMqq_YMMqq_YMMqq_IMMb 2239 +VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 2240 +VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 2241 +VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 2242 +VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 2243 +VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 2244 +VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 2245 +VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 2246 +VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 2247 +VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 2248 +VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 2249 +VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 2250 +VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 2251 +VCMPPS_XMMdq_XMMdq_MEMdq_IMMb 2252 +VCMPPS_XMMdq_XMMdq_XMMdq_IMMb 2253 +VCMPPS_YMMqq_YMMqq_MEMqq_IMMb 2254 +VCMPPS_YMMqq_YMMqq_YMMqq_IMMb 2255 +VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 2256 +VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 2257 +VCMPSD_XMMdq_XMMdq_MEMq_IMMb 2258 +VCMPSD_XMMdq_XMMdq_XMMq_IMMb 2259 +VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 2260 +VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 2261 +VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 2262 +VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 2263 +VCMPSS_XMMdq_XMMdq_MEMd_IMMb 2264 +VCMPSS_XMMdq_XMMdq_XMMd_IMMb 2265 +VCOMISD_XMMf64_MEMf64_AVX512 2266 +VCOMISD_XMMf64_XMMf64_AVX512 2267 +VCOMISD_XMMq_MEMq 2268 +VCOMISD_XMMq_XMMq 2269 +VCOMISH_XMMf16_MEMf16_AVX512 2270 +VCOMISH_XMMf16_XMMf16_AVX512 2271 +VCOMISS_XMMd_MEMd 2272 +VCOMISS_XMMd_XMMd 2273 +VCOMISS_XMMf32_MEMf32_AVX512 2274 +VCOMISS_XMMf32_XMMf32_AVX512 2275 +VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 2276 +VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 2277 +VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 2278 +VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 2279 +VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 2280 +VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 2281 +VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 2282 +VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 2283 +VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 2284 +VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 2285 +VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 2286 +VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 2287 +VCVTDQ2PD_XMMdq_MEMq 2288 +VCVTDQ2PD_XMMdq_XMMq 2289 +VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 2290 +VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 2291 +VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 2292 +VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 2293 +VCVTDQ2PD_YMMqq_MEMdq 2294 +VCVTDQ2PD_YMMqq_XMMdq 2295 +VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 2296 +VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 2297 +VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 2298 +VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 2299 +VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 2300 +VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 2301 +VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 2302 +VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 2303 +VCVTDQ2PS_XMMdq_MEMdq 2304 +VCVTDQ2PS_XMMdq_XMMdq 2305 +VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 2306 +VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 2307 +VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 2308 +VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 2309 +VCVTDQ2PS_YMMqq_MEMqq 2310 +VCVTDQ2PS_YMMqq_YMMqq 2311 +VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 2312 +VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 2313 +VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 2314 +VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 2315 +VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 2316 +VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 2317 +VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 2318 +VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 2319 +VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 2320 +VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 2321 +VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 2322 +VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 2323 +VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 2324 +VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 2325 +VCVTPD2DQ_XMMdq_MEMdq 2326 +VCVTPD2DQ_XMMdq_MEMqq 2327 +VCVTPD2DQ_XMMdq_XMMdq 2328 +VCVTPD2DQ_XMMdq_YMMqq 2329 +VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 2330 +VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 2331 +VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 2332 +VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 2333 +VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 2334 +VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 2335 +VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 2336 +VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 2337 +VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 2338 +VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 2339 +VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 2340 +VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 2341 +VCVTPD2PS_XMMdq_MEMdq 2342 +VCVTPD2PS_XMMdq_MEMqq 2343 +VCVTPD2PS_XMMdq_XMMdq 2344 +VCVTPD2PS_XMMdq_YMMqq 2345 +VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 2346 +VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 2347 +VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 2348 +VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 2349 +VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 2350 +VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 2351 +VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 2352 +VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 2353 +VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 2354 +VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 2355 +VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 2356 +VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 2357 +VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 2358 +VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 2359 +VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 2360 +VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 2361 +VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 2362 +VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 2363 +VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 2364 +VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 2365 +VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 2366 +VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 2367 +VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 2368 +VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 2369 +VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 2370 +VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 2371 +VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 2372 +VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 2373 +VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 2374 +VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 2375 +VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 2376 +VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 2377 +VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 2378 +VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 2379 +VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 2380 +VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 2381 +VCVTPH2PS_XMMdq_MEMq 2382 +VCVTPH2PS_XMMdq_XMMq 2383 +VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 2384 +VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 2385 +VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 2386 +VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 2387 +VCVTPH2PS_YMMqq_MEMdq 2388 +VCVTPH2PS_YMMqq_XMMdq 2389 +VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 2390 +VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 2391 +VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 2392 +VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 2393 +VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 2394 +VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 2395 +VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 2396 +VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 2397 +VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 2398 +VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 2399 +VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 2400 +VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 2401 +VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 2402 +VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 2403 +VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 2404 +VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 2405 +VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 2406 +VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 2407 +VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 2408 +VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 2409 +VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 2410 +VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 2411 +VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 2412 +VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 2413 +VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 2414 +VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 2415 +VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 2416 +VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 2417 +VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 2418 +VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 2419 +VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 2420 +VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 2421 +VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 2422 +VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 2423 +VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 2424 +VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 2425 +VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 2426 +VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 2427 +VCVTPS2DQ_XMMdq_MEMdq 2428 +VCVTPS2DQ_XMMdq_XMMdq 2429 +VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 2430 +VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 2431 +VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 2432 +VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 2433 +VCVTPS2DQ_YMMqq_MEMqq 2434 +VCVTPS2DQ_YMMqq_YMMqq 2435 +VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 2436 +VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 2437 +VCVTPS2PD_XMMdq_MEMq 2438 +VCVTPS2PD_XMMdq_XMMq 2439 +VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 2440 +VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 2441 +VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 2442 +VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 2443 +VCVTPS2PD_YMMqq_MEMdq 2444 +VCVTPS2PD_YMMqq_XMMdq 2445 +VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 2446 +VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 2447 +VCVTPS2PH_MEMdq_YMMqq_IMMb 2448 +VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 2449 +VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 2450 +VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 2451 +VCVTPS2PH_MEMq_XMMdq_IMMb 2452 +VCVTPS2PH_XMMdq_YMMqq_IMMb 2453 +VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 2454 +VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 2455 +VCVTPS2PH_XMMq_XMMdq_IMMb 2456 +VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 2457 +VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 2458 +VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 2459 +VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 2460 +VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 2461 +VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 2462 +VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 2463 +VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 2464 +VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 2465 +VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 2466 +VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 2467 +VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 2468 +VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 2469 +VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 2470 +VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 2471 +VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 2472 +VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 2473 +VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 2474 +VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 2475 +VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 2476 +VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 2477 +VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 2478 +VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 2479 +VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 2480 +VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 2481 +VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 2482 +VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 2483 +VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 2484 +VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 2485 +VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 2486 +VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 2487 +VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 2488 +VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 2489 +VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 2490 +VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 2491 +VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 2492 +VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 2493 +VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 2494 +VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 2495 +VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 2496 +VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 2497 +VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 2498 +VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 2499 +VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 2500 +VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 2501 +VCVTSD2SI_GPR32d_MEMq 2502 +VCVTSD2SI_GPR32d_XMMq 2503 +VCVTSD2SI_GPR32i32_MEMf64_AVX512 2504 +VCVTSD2SI_GPR32i32_XMMf64_AVX512 2505 +VCVTSD2SI_GPR64i64_MEMf64_AVX512 2506 +VCVTSD2SI_GPR64i64_XMMf64_AVX512 2507 +VCVTSD2SI_GPR64q_MEMq 2508 +VCVTSD2SI_GPR64q_XMMq 2509 +VCVTSD2SS_XMMdq_XMMdq_MEMq 2510 +VCVTSD2SS_XMMdq_XMMdq_XMMq 2511 +VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 2512 +VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 2513 +VCVTSD2USI_GPR32u32_MEMf64_AVX512 2514 +VCVTSD2USI_GPR32u32_XMMf64_AVX512 2515 +VCVTSD2USI_GPR64u64_MEMf64_AVX512 2516 +VCVTSD2USI_GPR64u64_XMMf64_AVX512 2517 +VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 2518 +VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 2519 +VCVTSH2SI_GPR32i32_MEMf16_AVX512 2520 +VCVTSH2SI_GPR32i32_XMMf16_AVX512 2521 +VCVTSH2SI_GPR64i64_MEMf16_AVX512 2522 +VCVTSH2SI_GPR64i64_XMMf16_AVX512 2523 +VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 2524 +VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 2525 +VCVTSH2USI_GPR32u32_MEMf16_AVX512 2526 +VCVTSH2USI_GPR32u32_XMMf16_AVX512 2527 +VCVTSH2USI_GPR64u64_MEMf16_AVX512 2528 +VCVTSH2USI_GPR64u64_XMMf16_AVX512 2529 +VCVTSI2SD_XMMdq_XMMdq_GPR32d 2530 +VCVTSI2SD_XMMdq_XMMdq_GPR64q 2531 +VCVTSI2SD_XMMdq_XMMdq_MEMd 2532 +VCVTSI2SD_XMMdq_XMMdq_MEMq 2533 +VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 2534 +VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 2535 +VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 2536 +VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 2537 +VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 2538 +VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 2539 +VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 2540 +VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 2541 +VCVTSI2SS_XMMdq_XMMdq_GPR32d 2542 +VCVTSI2SS_XMMdq_XMMdq_GPR64q 2543 +VCVTSI2SS_XMMdq_XMMdq_MEMd 2544 +VCVTSI2SS_XMMdq_XMMdq_MEMq 2545 +VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 2546 +VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 2547 +VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 2548 +VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 2549 +VCVTSS2SD_XMMdq_XMMdq_MEMd 2550 +VCVTSS2SD_XMMdq_XMMdq_XMMd 2551 +VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 2552 +VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 2553 +VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 2554 +VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 2555 +VCVTSS2SI_GPR32d_MEMd 2556 +VCVTSS2SI_GPR32d_XMMd 2557 +VCVTSS2SI_GPR32i32_MEMf32_AVX512 2558 +VCVTSS2SI_GPR32i32_XMMf32_AVX512 2559 +VCVTSS2SI_GPR64i64_MEMf32_AVX512 2560 +VCVTSS2SI_GPR64i64_XMMf32_AVX512 2561 +VCVTSS2SI_GPR64q_MEMd 2562 +VCVTSS2SI_GPR64q_XMMd 2563 +VCVTSS2USI_GPR32u32_MEMf32_AVX512 2564 +VCVTSS2USI_GPR32u32_XMMf32_AVX512 2565 +VCVTSS2USI_GPR64u64_MEMf32_AVX512 2566 +VCVTSS2USI_GPR64u64_XMMf32_AVX512 2567 +VCVTTPD2DQ_XMMdq_MEMdq 2568 +VCVTTPD2DQ_XMMdq_MEMqq 2569 +VCVTTPD2DQ_XMMdq_XMMdq 2570 +VCVTTPD2DQ_XMMdq_YMMqq 2571 +VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 2572 +VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 2573 +VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 2574 +VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 2575 +VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 2576 +VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 2577 +VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 2578 +VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 2579 +VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 2580 +VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 2581 +VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 2582 +VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 2583 +VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 2584 +VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 2585 +VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 2586 +VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 2587 +VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 2588 +VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 2589 +VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 2590 +VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 2591 +VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 2592 +VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 2593 +VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 2594 +VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 2595 +VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 2596 +VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 2597 +VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 2598 +VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 2599 +VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 2600 +VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 2601 +VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 2602 +VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 2603 +VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 2604 +VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 2605 +VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 2606 +VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 2607 +VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 2608 +VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 2609 +VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 2610 +VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 2611 +VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 2612 +VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 2613 +VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 2614 +VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 2615 +VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 2616 +VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 2617 +VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 2618 +VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 2619 +VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 2620 +VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 2621 +VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 2622 +VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 2623 +VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 2624 +VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 2625 +VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 2626 +VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 2627 +VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 2628 +VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 2629 +VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 2630 +VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 2631 +VCVTTPS2DQ_XMMdq_MEMdq 2632 +VCVTTPS2DQ_XMMdq_XMMdq 2633 +VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 2634 +VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 2635 +VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 2636 +VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 2637 +VCVTTPS2DQ_YMMqq_MEMqq 2638 +VCVTTPS2DQ_YMMqq_YMMqq 2639 +VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 2640 +VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 2641 +VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 2642 +VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 2643 +VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 2644 +VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 2645 +VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 2646 +VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 2647 +VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 2648 +VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 2649 +VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 2650 +VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 2651 +VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 2652 +VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 2653 +VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 2654 +VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 2655 +VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 2656 +VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 2657 +VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 2658 +VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 2659 +VCVTTSD2SI_GPR32d_MEMq 2660 +VCVTTSD2SI_GPR32d_XMMq 2661 +VCVTTSD2SI_GPR32i32_MEMf64_AVX512 2662 +VCVTTSD2SI_GPR32i32_XMMf64_AVX512 2663 +VCVTTSD2SI_GPR64i64_MEMf64_AVX512 2664 +VCVTTSD2SI_GPR64i64_XMMf64_AVX512 2665 +VCVTTSD2SI_GPR64q_MEMq 2666 +VCVTTSD2SI_GPR64q_XMMq 2667 +VCVTTSD2USI_GPR32u32_MEMf64_AVX512 2668 +VCVTTSD2USI_GPR32u32_XMMf64_AVX512 2669 +VCVTTSD2USI_GPR64u64_MEMf64_AVX512 2670 +VCVTTSD2USI_GPR64u64_XMMf64_AVX512 2671 +VCVTTSH2SI_GPR32i32_MEMf16_AVX512 2672 +VCVTTSH2SI_GPR32i32_XMMf16_AVX512 2673 +VCVTTSH2SI_GPR64i64_MEMf16_AVX512 2674 +VCVTTSH2SI_GPR64i64_XMMf16_AVX512 2675 +VCVTTSH2USI_GPR32u32_MEMf16_AVX512 2676 +VCVTTSH2USI_GPR32u32_XMMf16_AVX512 2677 +VCVTTSH2USI_GPR64u64_MEMf16_AVX512 2678 +VCVTTSH2USI_GPR64u64_XMMf16_AVX512 2679 +VCVTTSS2SI_GPR32d_MEMd 2680 +VCVTTSS2SI_GPR32d_XMMd 2681 +VCVTTSS2SI_GPR32i32_MEMf32_AVX512 2682 +VCVTTSS2SI_GPR32i32_XMMf32_AVX512 2683 +VCVTTSS2SI_GPR64i64_MEMf32_AVX512 2684 +VCVTTSS2SI_GPR64i64_XMMf32_AVX512 2685 +VCVTTSS2SI_GPR64q_MEMd 2686 +VCVTTSS2SI_GPR64q_XMMd 2687 +VCVTTSS2USI_GPR32u32_MEMf32_AVX512 2688 +VCVTTSS2USI_GPR32u32_XMMf32_AVX512 2689 +VCVTTSS2USI_GPR64u64_MEMf32_AVX512 2690 +VCVTTSS2USI_GPR64u64_XMMf32_AVX512 2691 +VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 2692 +VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 2693 +VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 2694 +VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 2695 +VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 2696 +VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 2697 +VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 2698 +VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 2699 +VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 2700 +VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 2701 +VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 2702 +VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 2703 +VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 2704 +VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 2705 +VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 2706 +VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 2707 +VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 2708 +VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 2709 +VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 2710 +VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 2711 +VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 2712 +VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 2713 +VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 2714 +VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 2715 +VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 2716 +VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 2717 +VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 2718 +VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 2719 +VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 2720 +VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 2721 +VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 2722 +VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 2723 +VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 2724 +VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 2725 +VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 2726 +VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 2727 +VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 2728 +VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 2729 +VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 2730 +VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 2731 +VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 2732 +VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 2733 +VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 2734 +VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 2735 +VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 2736 +VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 2737 +VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 2738 +VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 2739 +VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 2740 +VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 2741 +VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 2742 +VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 2743 +VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 2744 +VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 2745 +VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 2746 +VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 2747 +VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 2748 +VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 2749 +VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 2750 +VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 2751 +VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 2752 +VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 2753 +VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 2754 +VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 2755 +VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 2756 +VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 2757 +VDIVPD_XMMdq_XMMdq_MEMdq 2758 +VDIVPD_XMMdq_XMMdq_XMMdq 2759 +VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2760 +VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2761 +VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 2762 +VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 2763 +VDIVPD_YMMqq_YMMqq_MEMqq 2764 +VDIVPD_YMMqq_YMMqq_YMMqq 2765 +VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 2766 +VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 2767 +VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2768 +VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2769 +VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 2770 +VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 2771 +VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 2772 +VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 2773 +VDIVPS_XMMdq_XMMdq_MEMdq 2774 +VDIVPS_XMMdq_XMMdq_XMMdq 2775 +VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2776 +VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2777 +VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 2778 +VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 2779 +VDIVPS_YMMqq_YMMqq_MEMqq 2780 +VDIVPS_YMMqq_YMMqq_YMMqq 2781 +VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2782 +VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 2783 +VDIVSD_XMMdq_XMMdq_MEMq 2784 +VDIVSD_XMMdq_XMMdq_XMMq 2785 +VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2786 +VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2787 +VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2788 +VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2789 +VDIVSS_XMMdq_XMMdq_MEMd 2790 +VDIVSS_XMMdq_XMMdq_XMMd 2791 +VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2792 +VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2793 +VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 2794 +VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 2795 +VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 2796 +VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 2797 +VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 2798 +VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 2799 +VDPPD_XMMdq_XMMdq_MEMdq_IMMb 2800 +VDPPD_XMMdq_XMMdq_XMMdq_IMMb 2801 +VDPPS_XMMdq_XMMdq_MEMdq_IMMb 2802 +VDPPS_XMMdq_XMMdq_XMMdq_IMMb 2803 +VDPPS_YMMqq_YMMqq_MEMqq_IMMb 2804 +VDPPS_YMMqq_YMMqq_YMMqq_IMMb 2805 +VERR_GPR16 2806 +VERR_MEMw 2807 +VERW_GPR16 2808 +VERW_MEMw 2809 +VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 2810 +VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 2811 +VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 2812 +VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 2813 +VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 2814 +VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 2815 +VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 2816 +VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 2817 +VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 2818 +VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 2819 +VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 2820 +VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 2821 +VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 2822 +VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 2823 +VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 2824 +VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 2825 +VEXTRACTF128_MEMdq_YMMdq_IMMb 2826 +VEXTRACTF128_XMMdq_YMMdq_IMMb 2827 +VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 2828 +VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 2829 +VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 2830 +VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 2831 +VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 2832 +VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 2833 +VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 2834 +VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 2835 +VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 2836 +VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 2837 +VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 2838 +VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 2839 +VEXTRACTI128_MEMdq_YMMqq_IMMb 2840 +VEXTRACTI128_XMMdq_YMMqq_IMMb 2841 +VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 2842 +VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 2843 +VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 2844 +VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 2845 +VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 2846 +VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 2847 +VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 2848 +VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 2849 +VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 2850 +VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 2851 +VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 2852 +VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 2853 +VEXTRACTPS_GPR32_XMMdq_IMMb 2854 +VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 2855 +VEXTRACTPS_MEMd_XMMdq_IMMb 2856 +VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 2857 +VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 2858 +VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 2859 +VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 2860 +VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 2861 +VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 2862 +VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 2863 +VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 2864 +VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 2865 +VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 2866 +VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 2867 +VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 2868 +VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 2869 +VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 2870 +VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 2871 +VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 2872 +VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 2873 +VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 2874 +VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 2875 +VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 2876 +VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 2877 +VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 2878 +VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 2879 +VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 2880 +VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 2881 +VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 2882 +VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 2883 +VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 2884 +VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 2885 +VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 2886 +VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 2887 +VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 2888 +VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 2889 +VFMADD132PD_XMMdq_XMMdq_MEMdq 2890 +VFMADD132PD_XMMdq_XMMdq_XMMdq 2891 +VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2892 +VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2893 +VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 2894 +VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 2895 +VFMADD132PD_YMMqq_YMMqq_MEMqq 2896 +VFMADD132PD_YMMqq_YMMqq_YMMqq 2897 +VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 2898 +VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 2899 +VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2900 +VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2901 +VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 2902 +VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 2903 +VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 2904 +VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 2905 +VFMADD132PS_XMMdq_XMMdq_MEMdq 2906 +VFMADD132PS_XMMdq_XMMdq_XMMdq 2907 +VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2908 +VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2909 +VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 2910 +VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 2911 +VFMADD132PS_YMMqq_YMMqq_MEMqq 2912 +VFMADD132PS_YMMqq_YMMqq_YMMqq 2913 +VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2914 +VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 2915 +VFMADD132SD_XMMdq_XMMq_MEMq 2916 +VFMADD132SD_XMMdq_XMMq_XMMq 2917 +VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2918 +VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2919 +VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2920 +VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2921 +VFMADD132SS_XMMdq_XMMd_MEMd 2922 +VFMADD132SS_XMMdq_XMMd_XMMd 2923 +VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2924 +VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2925 +VFMADD213PD_XMMdq_XMMdq_MEMdq 2926 +VFMADD213PD_XMMdq_XMMdq_XMMdq 2927 +VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2928 +VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2929 +VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 2930 +VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 2931 +VFMADD213PD_YMMqq_YMMqq_MEMqq 2932 +VFMADD213PD_YMMqq_YMMqq_YMMqq 2933 +VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 2934 +VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 2935 +VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2936 +VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2937 +VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 2938 +VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 2939 +VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 2940 +VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 2941 +VFMADD213PS_XMMdq_XMMdq_MEMdq 2942 +VFMADD213PS_XMMdq_XMMdq_XMMdq 2943 +VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2944 +VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2945 +VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 2946 +VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 2947 +VFMADD213PS_YMMqq_YMMqq_MEMqq 2948 +VFMADD213PS_YMMqq_YMMqq_YMMqq 2949 +VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2950 +VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 2951 +VFMADD213SD_XMMdq_XMMq_MEMq 2952 +VFMADD213SD_XMMdq_XMMq_XMMq 2953 +VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2954 +VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2955 +VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2956 +VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2957 +VFMADD213SS_XMMdq_XMMd_MEMd 2958 +VFMADD213SS_XMMdq_XMMd_XMMd 2959 +VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2960 +VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2961 +VFMADD231PD_XMMdq_XMMdq_MEMdq 2962 +VFMADD231PD_XMMdq_XMMdq_XMMdq 2963 +VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2964 +VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2965 +VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 2966 +VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 2967 +VFMADD231PD_YMMqq_YMMqq_MEMqq 2968 +VFMADD231PD_YMMqq_YMMqq_YMMqq 2969 +VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 2970 +VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 2971 +VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2972 +VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2973 +VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 2974 +VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 2975 +VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 2976 +VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 2977 +VFMADD231PS_XMMdq_XMMdq_MEMdq 2978 +VFMADD231PS_XMMdq_XMMdq_XMMdq 2979 +VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2980 +VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2981 +VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 2982 +VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 2983 +VFMADD231PS_YMMqq_YMMqq_MEMqq 2984 +VFMADD231PS_YMMqq_YMMqq_YMMqq 2985 +VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 2986 +VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 2987 +VFMADD231SD_XMMdq_XMMq_MEMq 2988 +VFMADD231SD_XMMdq_XMMq_XMMq 2989 +VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 2990 +VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 2991 +VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 2992 +VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 2993 +VFMADD231SS_XMMdq_XMMd_MEMd 2994 +VFMADD231SS_XMMdq_XMMd_XMMd 2995 +VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 2996 +VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 2997 +VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 2998 +VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 2999 +VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 3000 +VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 3001 +VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 3002 +VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 3003 +VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 3004 +VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 3005 +VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq 3006 +VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq 3007 +VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq 3008 +VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq 3009 +VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq 3010 +VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq 3011 +VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq 3012 +VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq 3013 +VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq 3014 +VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq 3015 +VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq 3016 +VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq 3017 +VFMADDSD_XMMdq_XMMq_MEMq_XMMq 3018 +VFMADDSD_XMMdq_XMMq_XMMq_MEMq 3019 +VFMADDSD_XMMdq_XMMq_XMMq_XMMq 3020 +VFMADDSS_XMMdq_XMMd_MEMd_XMMd 3021 +VFMADDSS_XMMdq_XMMd_XMMd_MEMd 3022 +VFMADDSS_XMMdq_XMMd_XMMd_XMMd 3023 +VFMADDSUB132PD_XMMdq_XMMdq_MEMdq 3024 +VFMADDSUB132PD_XMMdq_XMMdq_XMMdq 3025 +VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3026 +VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3027 +VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3028 +VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3029 +VFMADDSUB132PD_YMMqq_YMMqq_MEMqq 3030 +VFMADDSUB132PD_YMMqq_YMMqq_YMMqq 3031 +VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3032 +VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3033 +VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3034 +VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3035 +VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3036 +VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3037 +VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3038 +VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3039 +VFMADDSUB132PS_XMMdq_XMMdq_MEMdq 3040 +VFMADDSUB132PS_XMMdq_XMMdq_XMMdq 3041 +VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3042 +VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3043 +VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3044 +VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3045 +VFMADDSUB132PS_YMMqq_YMMqq_MEMqq 3046 +VFMADDSUB132PS_YMMqq_YMMqq_YMMqq 3047 +VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3048 +VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3049 +VFMADDSUB213PD_XMMdq_XMMdq_MEMdq 3050 +VFMADDSUB213PD_XMMdq_XMMdq_XMMdq 3051 +VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3052 +VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3053 +VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3054 +VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3055 +VFMADDSUB213PD_YMMqq_YMMqq_MEMqq 3056 +VFMADDSUB213PD_YMMqq_YMMqq_YMMqq 3057 +VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3058 +VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3059 +VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3060 +VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3061 +VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3062 +VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3063 +VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3064 +VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3065 +VFMADDSUB213PS_XMMdq_XMMdq_MEMdq 3066 +VFMADDSUB213PS_XMMdq_XMMdq_XMMdq 3067 +VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3068 +VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3069 +VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3070 +VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3071 +VFMADDSUB213PS_YMMqq_YMMqq_MEMqq 3072 +VFMADDSUB213PS_YMMqq_YMMqq_YMMqq 3073 +VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3074 +VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3075 +VFMADDSUB231PD_XMMdq_XMMdq_MEMdq 3076 +VFMADDSUB231PD_XMMdq_XMMdq_XMMdq 3077 +VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3078 +VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3079 +VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3080 +VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3081 +VFMADDSUB231PD_YMMqq_YMMqq_MEMqq 3082 +VFMADDSUB231PD_YMMqq_YMMqq_YMMqq 3083 +VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3084 +VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3085 +VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3086 +VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3087 +VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3088 +VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3089 +VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3090 +VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3091 +VFMADDSUB231PS_XMMdq_XMMdq_MEMdq 3092 +VFMADDSUB231PS_XMMdq_XMMdq_XMMdq 3093 +VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3094 +VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3095 +VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3096 +VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3097 +VFMADDSUB231PS_YMMqq_YMMqq_MEMqq 3098 +VFMADDSUB231PS_YMMqq_YMMqq_YMMqq 3099 +VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3100 +VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3101 +VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq 3102 +VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq 3103 +VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq 3104 +VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq 3105 +VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq 3106 +VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq 3107 +VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq 3108 +VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq 3109 +VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq 3110 +VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq 3111 +VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq 3112 +VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq 3113 +VFMSUB132PD_XMMdq_XMMdq_MEMdq 3114 +VFMSUB132PD_XMMdq_XMMdq_XMMdq 3115 +VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3116 +VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3117 +VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3118 +VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3119 +VFMSUB132PD_YMMqq_YMMqq_MEMqq 3120 +VFMSUB132PD_YMMqq_YMMqq_YMMqq 3121 +VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3122 +VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3123 +VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3124 +VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3125 +VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3126 +VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3127 +VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3128 +VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3129 +VFMSUB132PS_XMMdq_XMMdq_MEMdq 3130 +VFMSUB132PS_XMMdq_XMMdq_XMMdq 3131 +VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3132 +VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3133 +VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3134 +VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3135 +VFMSUB132PS_YMMqq_YMMqq_MEMqq 3136 +VFMSUB132PS_YMMqq_YMMqq_YMMqq 3137 +VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3138 +VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3139 +VFMSUB132SD_XMMdq_XMMq_MEMq 3140 +VFMSUB132SD_XMMdq_XMMq_XMMq 3141 +VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3142 +VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3143 +VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3144 +VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3145 +VFMSUB132SS_XMMdq_XMMd_MEMd 3146 +VFMSUB132SS_XMMdq_XMMd_XMMd 3147 +VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3148 +VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3149 +VFMSUB213PD_XMMdq_XMMdq_MEMdq 3150 +VFMSUB213PD_XMMdq_XMMdq_XMMdq 3151 +VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3152 +VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3153 +VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3154 +VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3155 +VFMSUB213PD_YMMqq_YMMqq_MEMqq 3156 +VFMSUB213PD_YMMqq_YMMqq_YMMqq 3157 +VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3158 +VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3159 +VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3160 +VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3161 +VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3162 +VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3163 +VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3164 +VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3165 +VFMSUB213PS_XMMdq_XMMdq_MEMdq 3166 +VFMSUB213PS_XMMdq_XMMdq_XMMdq 3167 +VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3168 +VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3169 +VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3170 +VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3171 +VFMSUB213PS_YMMqq_YMMqq_MEMqq 3172 +VFMSUB213PS_YMMqq_YMMqq_YMMqq 3173 +VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3174 +VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3175 +VFMSUB213SD_XMMdq_XMMq_MEMq 3176 +VFMSUB213SD_XMMdq_XMMq_XMMq 3177 +VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3178 +VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3179 +VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3180 +VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3181 +VFMSUB213SS_XMMdq_XMMd_MEMd 3182 +VFMSUB213SS_XMMdq_XMMd_XMMd 3183 +VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3184 +VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3185 +VFMSUB231PD_XMMdq_XMMdq_MEMdq 3186 +VFMSUB231PD_XMMdq_XMMdq_XMMdq 3187 +VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3188 +VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3189 +VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3190 +VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3191 +VFMSUB231PD_YMMqq_YMMqq_MEMqq 3192 +VFMSUB231PD_YMMqq_YMMqq_YMMqq 3193 +VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3194 +VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3195 +VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3196 +VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3197 +VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3198 +VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3199 +VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3200 +VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3201 +VFMSUB231PS_XMMdq_XMMdq_MEMdq 3202 +VFMSUB231PS_XMMdq_XMMdq_XMMdq 3203 +VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3204 +VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3205 +VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3206 +VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3207 +VFMSUB231PS_YMMqq_YMMqq_MEMqq 3208 +VFMSUB231PS_YMMqq_YMMqq_YMMqq 3209 +VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3210 +VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3211 +VFMSUB231SD_XMMdq_XMMq_MEMq 3212 +VFMSUB231SD_XMMdq_XMMq_XMMq 3213 +VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3214 +VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3215 +VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3216 +VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3217 +VFMSUB231SS_XMMdq_XMMd_MEMd 3218 +VFMSUB231SS_XMMdq_XMMd_XMMd 3219 +VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3220 +VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3221 +VFMSUBADD132PD_XMMdq_XMMdq_MEMdq 3222 +VFMSUBADD132PD_XMMdq_XMMdq_XMMdq 3223 +VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3224 +VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3225 +VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3226 +VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3227 +VFMSUBADD132PD_YMMqq_YMMqq_MEMqq 3228 +VFMSUBADD132PD_YMMqq_YMMqq_YMMqq 3229 +VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3230 +VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3231 +VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3232 +VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3233 +VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3234 +VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3235 +VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3236 +VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3237 +VFMSUBADD132PS_XMMdq_XMMdq_MEMdq 3238 +VFMSUBADD132PS_XMMdq_XMMdq_XMMdq 3239 +VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3240 +VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3241 +VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3242 +VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3243 +VFMSUBADD132PS_YMMqq_YMMqq_MEMqq 3244 +VFMSUBADD132PS_YMMqq_YMMqq_YMMqq 3245 +VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3246 +VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3247 +VFMSUBADD213PD_XMMdq_XMMdq_MEMdq 3248 +VFMSUBADD213PD_XMMdq_XMMdq_XMMdq 3249 +VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3250 +VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3251 +VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3252 +VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3253 +VFMSUBADD213PD_YMMqq_YMMqq_MEMqq 3254 +VFMSUBADD213PD_YMMqq_YMMqq_YMMqq 3255 +VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3256 +VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3257 +VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3258 +VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3259 +VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3260 +VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3261 +VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3262 +VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3263 +VFMSUBADD213PS_XMMdq_XMMdq_MEMdq 3264 +VFMSUBADD213PS_XMMdq_XMMdq_XMMdq 3265 +VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3266 +VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3267 +VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3268 +VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3269 +VFMSUBADD213PS_YMMqq_YMMqq_MEMqq 3270 +VFMSUBADD213PS_YMMqq_YMMqq_YMMqq 3271 +VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3272 +VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3273 +VFMSUBADD231PD_XMMdq_XMMdq_MEMdq 3274 +VFMSUBADD231PD_XMMdq_XMMdq_XMMdq 3275 +VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3276 +VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3277 +VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3278 +VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3279 +VFMSUBADD231PD_YMMqq_YMMqq_MEMqq 3280 +VFMSUBADD231PD_YMMqq_YMMqq_YMMqq 3281 +VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3282 +VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3283 +VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3284 +VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3285 +VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3286 +VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3287 +VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3288 +VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3289 +VFMSUBADD231PS_XMMdq_XMMdq_MEMdq 3290 +VFMSUBADD231PS_XMMdq_XMMdq_XMMdq 3291 +VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3292 +VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3293 +VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3294 +VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3295 +VFMSUBADD231PS_YMMqq_YMMqq_MEMqq 3296 +VFMSUBADD231PS_YMMqq_YMMqq_YMMqq 3297 +VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3298 +VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3299 +VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq 3300 +VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq 3301 +VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq 3302 +VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq 3303 +VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq 3304 +VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq 3305 +VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq 3306 +VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq 3307 +VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq 3308 +VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq 3309 +VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq 3310 +VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq 3311 +VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq 3312 +VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq 3313 +VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq 3314 +VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq 3315 +VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq 3316 +VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq 3317 +VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq 3318 +VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq 3319 +VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq 3320 +VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq 3321 +VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq 3322 +VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq 3323 +VFMSUBSD_XMMdq_XMMq_MEMq_XMMq 3324 +VFMSUBSD_XMMdq_XMMq_XMMq_MEMq 3325 +VFMSUBSD_XMMdq_XMMq_XMMq_XMMq 3326 +VFMSUBSS_XMMdq_XMMd_MEMd_XMMd 3327 +VFMSUBSS_XMMdq_XMMd_XMMd_MEMd 3328 +VFMSUBSS_XMMdq_XMMd_XMMd_XMMd 3329 +VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 3330 +VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 3331 +VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 3332 +VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 3333 +VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 3334 +VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 3335 +VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 3336 +VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 3337 +VFNMADD132PD_XMMdq_XMMdq_MEMdq 3338 +VFNMADD132PD_XMMdq_XMMdq_XMMdq 3339 +VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3340 +VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3341 +VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3342 +VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3343 +VFNMADD132PD_YMMqq_YMMqq_MEMqq 3344 +VFNMADD132PD_YMMqq_YMMqq_YMMqq 3345 +VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3346 +VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3347 +VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3348 +VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3349 +VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3350 +VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3351 +VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3352 +VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3353 +VFNMADD132PS_XMMdq_XMMdq_MEMdq 3354 +VFNMADD132PS_XMMdq_XMMdq_XMMdq 3355 +VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3356 +VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3357 +VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3358 +VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3359 +VFNMADD132PS_YMMqq_YMMqq_MEMqq 3360 +VFNMADD132PS_YMMqq_YMMqq_YMMqq 3361 +VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3362 +VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3363 +VFNMADD132SD_XMMdq_XMMq_MEMq 3364 +VFNMADD132SD_XMMdq_XMMq_XMMq 3365 +VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3366 +VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3367 +VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3368 +VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3369 +VFNMADD132SS_XMMdq_XMMd_MEMd 3370 +VFNMADD132SS_XMMdq_XMMd_XMMd 3371 +VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3372 +VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3373 +VFNMADD213PD_XMMdq_XMMdq_MEMdq 3374 +VFNMADD213PD_XMMdq_XMMdq_XMMdq 3375 +VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3376 +VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3377 +VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3378 +VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3379 +VFNMADD213PD_YMMqq_YMMqq_MEMqq 3380 +VFNMADD213PD_YMMqq_YMMqq_YMMqq 3381 +VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3382 +VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3383 +VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3384 +VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3385 +VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3386 +VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3387 +VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3388 +VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3389 +VFNMADD213PS_XMMdq_XMMdq_MEMdq 3390 +VFNMADD213PS_XMMdq_XMMdq_XMMdq 3391 +VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3392 +VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3393 +VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3394 +VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3395 +VFNMADD213PS_YMMqq_YMMqq_MEMqq 3396 +VFNMADD213PS_YMMqq_YMMqq_YMMqq 3397 +VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3398 +VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3399 +VFNMADD213SD_XMMdq_XMMq_MEMq 3400 +VFNMADD213SD_XMMdq_XMMq_XMMq 3401 +VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3402 +VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3403 +VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3404 +VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3405 +VFNMADD213SS_XMMdq_XMMd_MEMd 3406 +VFNMADD213SS_XMMdq_XMMd_XMMd 3407 +VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3408 +VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3409 +VFNMADD231PD_XMMdq_XMMdq_MEMdq 3410 +VFNMADD231PD_XMMdq_XMMdq_XMMdq 3411 +VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3412 +VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3413 +VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3414 +VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3415 +VFNMADD231PD_YMMqq_YMMqq_MEMqq 3416 +VFNMADD231PD_YMMqq_YMMqq_YMMqq 3417 +VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3418 +VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3419 +VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3420 +VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3421 +VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3422 +VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3423 +VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3424 +VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3425 +VFNMADD231PS_XMMdq_XMMdq_MEMdq 3426 +VFNMADD231PS_XMMdq_XMMdq_XMMdq 3427 +VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3428 +VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3429 +VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3430 +VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3431 +VFNMADD231PS_YMMqq_YMMqq_MEMqq 3432 +VFNMADD231PS_YMMqq_YMMqq_YMMqq 3433 +VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3434 +VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3435 +VFNMADD231SD_XMMdq_XMMq_MEMq 3436 +VFNMADD231SD_XMMdq_XMMq_XMMq 3437 +VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3438 +VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3439 +VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3440 +VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3441 +VFNMADD231SS_XMMdq_XMMd_MEMd 3442 +VFNMADD231SS_XMMdq_XMMd_XMMd 3443 +VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3444 +VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3445 +VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq 3446 +VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq 3447 +VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq 3448 +VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq 3449 +VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq 3450 +VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq 3451 +VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq 3452 +VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq 3453 +VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq 3454 +VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq 3455 +VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq 3456 +VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq 3457 +VFNMADDSD_XMMdq_XMMq_MEMq_XMMq 3458 +VFNMADDSD_XMMdq_XMMq_XMMq_MEMq 3459 +VFNMADDSD_XMMdq_XMMq_XMMq_XMMq 3460 +VFNMADDSS_XMMdq_XMMd_MEMd_XMMd 3461 +VFNMADDSS_XMMdq_XMMd_XMMd_MEMd 3462 +VFNMADDSS_XMMdq_XMMd_XMMd_XMMd 3463 +VFNMSUB132PD_XMMdq_XMMdq_MEMdq 3464 +VFNMSUB132PD_XMMdq_XMMdq_XMMdq 3465 +VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3466 +VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3467 +VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3468 +VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3469 +VFNMSUB132PD_YMMqq_YMMqq_MEMqq 3470 +VFNMSUB132PD_YMMqq_YMMqq_YMMqq 3471 +VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3472 +VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3473 +VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3474 +VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3475 +VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3476 +VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3477 +VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3478 +VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3479 +VFNMSUB132PS_XMMdq_XMMdq_MEMdq 3480 +VFNMSUB132PS_XMMdq_XMMdq_XMMdq 3481 +VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3482 +VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3483 +VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3484 +VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3485 +VFNMSUB132PS_YMMqq_YMMqq_MEMqq 3486 +VFNMSUB132PS_YMMqq_YMMqq_YMMqq 3487 +VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3488 +VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3489 +VFNMSUB132SD_XMMdq_XMMq_MEMq 3490 +VFNMSUB132SD_XMMdq_XMMq_XMMq 3491 +VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3492 +VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3493 +VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3494 +VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3495 +VFNMSUB132SS_XMMdq_XMMd_MEMd 3496 +VFNMSUB132SS_XMMdq_XMMd_XMMd 3497 +VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3498 +VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3499 +VFNMSUB213PD_XMMdq_XMMdq_MEMdq 3500 +VFNMSUB213PD_XMMdq_XMMdq_XMMdq 3501 +VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3502 +VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3503 +VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3504 +VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3505 +VFNMSUB213PD_YMMqq_YMMqq_MEMqq 3506 +VFNMSUB213PD_YMMqq_YMMqq_YMMqq 3507 +VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3508 +VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3509 +VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3510 +VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3511 +VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3512 +VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3513 +VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3514 +VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3515 +VFNMSUB213PS_XMMdq_XMMdq_MEMdq 3516 +VFNMSUB213PS_XMMdq_XMMdq_XMMdq 3517 +VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3518 +VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3519 +VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3520 +VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3521 +VFNMSUB213PS_YMMqq_YMMqq_MEMqq 3522 +VFNMSUB213PS_YMMqq_YMMqq_YMMqq 3523 +VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3524 +VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3525 +VFNMSUB213SD_XMMdq_XMMq_MEMq 3526 +VFNMSUB213SD_XMMdq_XMMq_XMMq 3527 +VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3528 +VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3529 +VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3530 +VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3531 +VFNMSUB213SS_XMMdq_XMMd_MEMd 3532 +VFNMSUB213SS_XMMdq_XMMd_XMMd 3533 +VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3534 +VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3535 +VFNMSUB231PD_XMMdq_XMMdq_MEMdq 3536 +VFNMSUB231PD_XMMdq_XMMdq_XMMdq 3537 +VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3538 +VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3539 +VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3540 +VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3541 +VFNMSUB231PD_YMMqq_YMMqq_MEMqq 3542 +VFNMSUB231PD_YMMqq_YMMqq_YMMqq 3543 +VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3544 +VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3545 +VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3546 +VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3547 +VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3548 +VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3549 +VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3550 +VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3551 +VFNMSUB231PS_XMMdq_XMMdq_MEMdq 3552 +VFNMSUB231PS_XMMdq_XMMdq_XMMdq 3553 +VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3554 +VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3555 +VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3556 +VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3557 +VFNMSUB231PS_YMMqq_YMMqq_MEMqq 3558 +VFNMSUB231PS_YMMqq_YMMqq_YMMqq 3559 +VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3560 +VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3561 +VFNMSUB231SD_XMMdq_XMMq_MEMq 3562 +VFNMSUB231SD_XMMdq_XMMq_XMMq 3563 +VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3564 +VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3565 +VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3566 +VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3567 +VFNMSUB231SS_XMMdq_XMMd_MEMd 3568 +VFNMSUB231SS_XMMdq_XMMd_XMMd 3569 +VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3570 +VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3571 +VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq 3572 +VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq 3573 +VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq 3574 +VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq 3575 +VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq 3576 +VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq 3577 +VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq 3578 +VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq 3579 +VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq 3580 +VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq 3581 +VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq 3582 +VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq 3583 +VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq 3584 +VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq 3585 +VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq 3586 +VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd 3587 +VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd 3588 +VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd 3589 +VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 3590 +VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 3591 +VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 3592 +VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 3593 +VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 3594 +VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 3595 +VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 3596 +VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 3597 +VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 3598 +VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 3599 +VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 3600 +VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 3601 +VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 3602 +VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 3603 +VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 3604 +VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 3605 +VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 3606 +VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 3607 +VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 3608 +VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 3609 +VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 3610 +VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 3611 +VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 3612 +VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 3613 +VFRCZPD_XMMdq_MEMdq 3614 +VFRCZPD_XMMdq_XMMdq 3615 +VFRCZPD_YMMqq_MEMqq 3616 +VFRCZPD_YMMqq_YMMqq 3617 +VFRCZPS_XMMdq_MEMdq 3618 +VFRCZPS_XMMdq_XMMdq 3619 +VFRCZPS_YMMqq_MEMqq 3620 +VFRCZPS_YMMqq_YMMqq 3621 +VFRCZSD_XMMdq_MEMq 3622 +VFRCZSD_XMMdq_XMMq 3623 +VFRCZSS_XMMdq_MEMd 3624 +VFRCZSS_XMMdq_XMMd 3625 +VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 3626 +VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 3627 +VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 3628 +VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 3629 +VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 3630 +VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 3631 +VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 3632 +VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 3633 +VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 3634 +VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 3635 +VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 3636 +VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 3637 +VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 3638 +VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 3639 +VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 3640 +VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 3641 +VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 3642 +VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 3643 +VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 3644 +VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 3645 +VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 3646 +VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 3647 +VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 3648 +VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 3649 +VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 3650 +VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 3651 +VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 3652 +VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 3653 +VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 3654 +VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 3655 +VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 3656 +VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 3657 +VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 3658 +VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 3659 +VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 3660 +VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 3661 +VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 3662 +VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 3663 +VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 3664 +VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 3665 +VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 3666 +VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 3667 +VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 3668 +VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 3669 +VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 3670 +VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 3671 +VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3672 +VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3673 +VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3674 +VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3675 +VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3676 +VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3677 +VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 3678 +VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 3679 +VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 3680 +VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 3681 +VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 3682 +VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 3683 +VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 3684 +VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 3685 +VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 3686 +VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 3687 +VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 3688 +VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 3689 +VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 3690 +VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 3691 +VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 3692 +VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 3693 +VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 3694 +VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 3695 +VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 3696 +VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 3697 +VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 3698 +VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 3699 +VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 3700 +VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 3701 +VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 3702 +VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 3703 +VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 3704 +VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 3705 +VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 3706 +VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 3707 +VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 3708 +VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 3709 +VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 3710 +VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 3711 +VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 3712 +VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 3713 +VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 3714 +VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 3715 +VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 3716 +VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 3717 +VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 3718 +VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 3719 +VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 3720 +VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 3721 +VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 3722 +VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 3723 +VGF2P8MULB_XMMu8_XMMu8_MEMu8 3724 +VGF2P8MULB_XMMu8_XMMu8_XMMu8 3725 +VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 3726 +VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 3727 +VGF2P8MULB_YMMu8_YMMu8_MEMu8 3728 +VGF2P8MULB_YMMu8_YMMu8_YMMu8 3729 +VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 3730 +VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 3731 +VHADDPD_XMMdq_XMMdq_MEMdq 3732 +VHADDPD_XMMdq_XMMdq_XMMdq 3733 +VHADDPD_YMMqq_YMMqq_MEMqq 3734 +VHADDPD_YMMqq_YMMqq_YMMqq 3735 +VHADDPS_XMMdq_XMMdq_MEMdq 3736 +VHADDPS_XMMdq_XMMdq_XMMdq 3737 +VHADDPS_YMMqq_YMMqq_MEMqq 3738 +VHADDPS_YMMqq_YMMqq_YMMqq 3739 +VHSUBPD_XMMdq_XMMdq_MEMdq 3740 +VHSUBPD_XMMdq_XMMdq_XMMdq 3741 +VHSUBPD_YMMqq_YMMqq_MEMqq 3742 +VHSUBPD_YMMqq_YMMqq_YMMqq 3743 +VHSUBPS_XMMdq_XMMdq_MEMdq 3744 +VHSUBPS_XMMdq_XMMdq_XMMdq 3745 +VHSUBPS_YMMqq_YMMqq_MEMqq 3746 +VHSUBPS_YMMqq_YMMqq_YMMqq 3747 +VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb 3748 +VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb 3749 +VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 3750 +VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 3751 +VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 3752 +VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 3753 +VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 3754 +VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 3755 +VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 3756 +VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 3757 +VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 3758 +VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 3759 +VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 3760 +VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 3761 +VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb 3762 +VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb 3763 +VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 3764 +VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 3765 +VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 3766 +VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 3767 +VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 3768 +VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 3769 +VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 3770 +VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 3771 +VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 3772 +VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 3773 +VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 3774 +VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 3775 +VINSERTPS_XMMdq_XMMdq_MEMd_IMMb 3776 +VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb 3777 +VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 3778 +VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 3779 +VLDDQU_XMMdq_MEMdq 3780 +VLDDQU_YMMqq_MEMqq 3781 +VLDMXCSR_MEMd 3782 +VMASKMOVDQU_XMMdq_XMMdq 3783 +VMASKMOVPD_MEMdq_XMMdq_XMMdq 3784 +VMASKMOVPD_MEMqq_YMMqq_YMMqq 3785 +VMASKMOVPD_XMMdq_XMMdq_MEMdq 3786 +VMASKMOVPD_YMMqq_YMMqq_MEMqq 3787 +VMASKMOVPS_MEMdq_XMMdq_XMMdq 3788 +VMASKMOVPS_MEMqq_YMMqq_YMMqq 3789 +VMASKMOVPS_XMMdq_XMMdq_MEMdq 3790 +VMASKMOVPS_YMMqq_YMMqq_MEMqq 3791 +VMAXPD_XMMdq_XMMdq_MEMdq 3792 +VMAXPD_XMMdq_XMMdq_XMMdq 3793 +VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3794 +VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3795 +VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3796 +VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3797 +VMAXPD_YMMqq_YMMqq_MEMqq 3798 +VMAXPD_YMMqq_YMMqq_YMMqq 3799 +VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3800 +VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3801 +VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3802 +VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3803 +VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3804 +VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3805 +VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3806 +VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3807 +VMAXPS_XMMdq_XMMdq_MEMdq 3808 +VMAXPS_XMMdq_XMMdq_XMMdq 3809 +VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3810 +VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3811 +VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3812 +VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3813 +VMAXPS_YMMqq_YMMqq_MEMqq 3814 +VMAXPS_YMMqq_YMMqq_YMMqq 3815 +VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3816 +VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3817 +VMAXSD_XMMdq_XMMdq_MEMq 3818 +VMAXSD_XMMdq_XMMdq_XMMq 3819 +VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3820 +VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3821 +VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3822 +VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3823 +VMAXSS_XMMdq_XMMdq_MEMd 3824 +VMAXSS_XMMdq_XMMdq_XMMd 3825 +VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3826 +VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3827 +VMCALL 3828 +VMCLEAR_MEMq 3829 +VMFUNC 3830 +VMINPD_XMMdq_XMMdq_MEMdq 3831 +VMINPD_XMMdq_XMMdq_XMMdq 3832 +VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3833 +VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3834 +VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 3835 +VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 3836 +VMINPD_YMMqq_YMMqq_MEMqq 3837 +VMINPD_YMMqq_YMMqq_YMMqq 3838 +VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 3839 +VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 3840 +VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3841 +VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3842 +VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 3843 +VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 3844 +VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 3845 +VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 3846 +VMINPS_XMMdq_XMMdq_MEMdq 3847 +VMINPS_XMMdq_XMMdq_XMMdq 3848 +VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3849 +VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3850 +VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 3851 +VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 3852 +VMINPS_YMMqq_YMMqq_MEMqq 3853 +VMINPS_YMMqq_YMMqq_YMMqq 3854 +VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 3855 +VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 3856 +VMINSD_XMMdq_XMMdq_MEMq 3857 +VMINSD_XMMdq_XMMdq_XMMq 3858 +VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 3859 +VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 3860 +VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 3861 +VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 3862 +VMINSS_XMMdq_XMMdq_MEMd 3863 +VMINSS_XMMdq_XMMdq_XMMd 3864 +VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 3865 +VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 3866 +VMLAUNCH 3867 +VMLOAD_ArAX 3868 +VMMCALL 3869 +VMOVAPD_MEMdq_XMMdq 3870 +VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 3871 +VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 3872 +VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 3873 +VMOVAPD_MEMqq_YMMqq 3874 +VMOVAPD_XMMdq_MEMdq 3875 +VMOVAPD_XMMdq_XMMdq_28 3876 +VMOVAPD_XMMdq_XMMdq_29 3877 +VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 3878 +VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 3879 +VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 3880 +VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 3881 +VMOVAPD_YMMqq_MEMqq 3882 +VMOVAPD_YMMqq_YMMqq_28 3883 +VMOVAPD_YMMqq_YMMqq_29 3884 +VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 3885 +VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 3886 +VMOVAPS_MEMdq_XMMdq 3887 +VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 3888 +VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 3889 +VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 3890 +VMOVAPS_MEMqq_YMMqq 3891 +VMOVAPS_XMMdq_MEMdq 3892 +VMOVAPS_XMMdq_XMMdq_28 3893 +VMOVAPS_XMMdq_XMMdq_29 3894 +VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 3895 +VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 3896 +VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 3897 +VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 3898 +VMOVAPS_YMMqq_MEMqq 3899 +VMOVAPS_YMMqq_YMMqq_28 3900 +VMOVAPS_YMMqq_YMMqq_29 3901 +VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 3902 +VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 3903 +VMOVD_GPR32d_XMMd 3904 +VMOVD_GPR32u32_XMMu32_AVX512 3905 +VMOVD_MEMd_XMMd 3906 +VMOVD_MEMu32_XMMu32_AVX512 3907 +VMOVD_XMMdq_GPR32d 3908 +VMOVD_XMMdq_MEMd 3909 +VMOVD_XMMu32_GPR32u32_AVX512 3910 +VMOVD_XMMu32_MEMu32_AVX512 3911 +VMOVDDUP_XMMdq_MEMq 3912 +VMOVDDUP_XMMdq_XMMq 3913 +VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 3914 +VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 3915 +VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 3916 +VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 3917 +VMOVDDUP_YMMqq_MEMqq 3918 +VMOVDDUP_YMMqq_YMMqq 3919 +VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 3920 +VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 3921 +VMOVDQA_MEMdq_XMMdq 3922 +VMOVDQA_MEMqq_YMMqq 3923 +VMOVDQA_XMMdq_MEMdq 3924 +VMOVDQA_XMMdq_XMMdq_6F 3925 +VMOVDQA_XMMdq_XMMdq_7F 3926 +VMOVDQA_YMMqq_MEMqq 3927 +VMOVDQA_YMMqq_YMMqq_6F 3928 +VMOVDQA_YMMqq_YMMqq_7F 3929 +VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 3930 +VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 3931 +VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 3932 +VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 3933 +VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 3934 +VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 3935 +VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 3936 +VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 3937 +VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 3938 +VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 3939 +VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 3940 +VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 3941 +VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 3942 +VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 3943 +VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 3944 +VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 3945 +VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 3946 +VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 3947 +VMOVDQU_MEMdq_XMMdq 3948 +VMOVDQU_MEMqq_YMMqq 3949 +VMOVDQU_XMMdq_MEMdq 3950 +VMOVDQU_XMMdq_XMMdq_6F 3951 +VMOVDQU_XMMdq_XMMdq_7F 3952 +VMOVDQU_YMMqq_MEMqq 3953 +VMOVDQU_YMMqq_YMMqq_6F 3954 +VMOVDQU_YMMqq_YMMqq_7F 3955 +VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 3956 +VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 3957 +VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 3958 +VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 3959 +VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 3960 +VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 3961 +VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 3962 +VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 3963 +VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 3964 +VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 3965 +VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 3966 +VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 3967 +VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 3968 +VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 3969 +VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 3970 +VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 3971 +VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 3972 +VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 3973 +VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 3974 +VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 3975 +VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 3976 +VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 3977 +VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 3978 +VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 3979 +VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 3980 +VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 3981 +VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 3982 +VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 3983 +VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 3984 +VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 3985 +VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 3986 +VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 3987 +VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 3988 +VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 3989 +VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 3990 +VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 3991 +VMOVHLPS_XMMdq_XMMdq_XMMdq 3992 +VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 3993 +VMOVHPD_MEMf64_XMMf64_AVX512 3994 +VMOVHPD_MEMq_XMMdq 3995 +VMOVHPD_XMMdq_XMMq_MEMq 3996 +VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 3997 +VMOVHPS_MEMf32_XMMf32_AVX512 3998 +VMOVHPS_MEMq_XMMdq 3999 +VMOVHPS_XMMdq_XMMq_MEMq 4000 +VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 4001 +VMOVLHPS_XMMdq_XMMq_XMMq 4002 +VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 4003 +VMOVLPD_MEMf64_XMMf64_AVX512 4004 +VMOVLPD_MEMq_XMMq 4005 +VMOVLPD_XMMdq_XMMdq_MEMq 4006 +VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 4007 +VMOVLPS_MEMf32_XMMf32_AVX512 4008 +VMOVLPS_MEMq_XMMq 4009 +VMOVLPS_XMMdq_XMMdq_MEMq 4010 +VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 4011 +VMOVMSKPD_GPR32d_XMMdq 4012 +VMOVMSKPD_GPR32d_YMMqq 4013 +VMOVMSKPS_GPR32d_XMMdq 4014 +VMOVMSKPS_GPR32d_YMMqq 4015 +VMOVNTDQ_MEMdq_XMMdq 4016 +VMOVNTDQ_MEMqq_YMMqq 4017 +VMOVNTDQ_MEMu32_XMMu32_AVX512 4018 +VMOVNTDQ_MEMu32_YMMu32_AVX512 4019 +VMOVNTDQ_MEMu32_ZMMu32_AVX512 4020 +VMOVNTDQA_XMMdq_MEMdq 4021 +VMOVNTDQA_XMMu32_MEMu32_AVX512 4022 +VMOVNTDQA_YMMqq_MEMqq 4023 +VMOVNTDQA_YMMu32_MEMu32_AVX512 4024 +VMOVNTDQA_ZMMu32_MEMu32_AVX512 4025 +VMOVNTPD_MEMdq_XMMdq 4026 +VMOVNTPD_MEMf64_XMMf64_AVX512 4027 +VMOVNTPD_MEMf64_YMMf64_AVX512 4028 +VMOVNTPD_MEMf64_ZMMf64_AVX512 4029 +VMOVNTPD_MEMqq_YMMqq 4030 +VMOVNTPS_MEMdq_XMMdq 4031 +VMOVNTPS_MEMf32_XMMf32_AVX512 4032 +VMOVNTPS_MEMf32_YMMf32_AVX512 4033 +VMOVNTPS_MEMf32_ZMMf32_AVX512 4034 +VMOVNTPS_MEMqq_YMMqq 4035 +VMOVQ_GPR64q_XMMq 4036 +VMOVQ_GPR64u64_XMMu64_AVX512 4037 +VMOVQ_MEMq_XMMq_7E 4038 +VMOVQ_MEMq_XMMq_D6 4039 +VMOVQ_MEMu64_XMMu64_AVX512 4040 +VMOVQ_XMMdq_GPR64q 4041 +VMOVQ_XMMdq_MEMq_6E 4042 +VMOVQ_XMMdq_MEMq_7E 4043 +VMOVQ_XMMdq_XMMq_7E 4044 +VMOVQ_XMMdq_XMMq_D6 4045 +VMOVQ_XMMu64_GPR64u64_AVX512 4046 +VMOVQ_XMMu64_MEMu64_AVX512 4047 +VMOVQ_XMMu64_XMMu64_AVX512 4048 +VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 4049 +VMOVSD_MEMq_XMMq 4050 +VMOVSD_XMMdq_MEMq 4051 +VMOVSD_XMMdq_XMMdq_XMMq_10 4052 +VMOVSD_XMMdq_XMMdq_XMMq_11 4053 +VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 4054 +VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 4055 +VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 4056 +VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 4057 +VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 4058 +VMOVSHDUP_XMMdq_MEMdq 4059 +VMOVSHDUP_XMMdq_XMMdq 4060 +VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 4061 +VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 4062 +VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 4063 +VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 4064 +VMOVSHDUP_YMMqq_MEMqq 4065 +VMOVSHDUP_YMMqq_YMMqq 4066 +VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 4067 +VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 4068 +VMOVSLDUP_XMMdq_MEMdq 4069 +VMOVSLDUP_XMMdq_XMMdq 4070 +VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 4071 +VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 4072 +VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 4073 +VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 4074 +VMOVSLDUP_YMMqq_MEMqq 4075 +VMOVSLDUP_YMMqq_YMMqq 4076 +VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 4077 +VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 4078 +VMOVSS_MEMd_XMMd 4079 +VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 4080 +VMOVSS_XMMdq_MEMd 4081 +VMOVSS_XMMdq_XMMdq_XMMd_10 4082 +VMOVSS_XMMdq_XMMdq_XMMd_11 4083 +VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 4084 +VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 4085 +VMOVUPD_MEMdq_XMMdq 4086 +VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 4087 +VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 4088 +VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 4089 +VMOVUPD_MEMqq_YMMqq 4090 +VMOVUPD_XMMdq_MEMdq 4091 +VMOVUPD_XMMdq_XMMdq_10 4092 +VMOVUPD_XMMdq_XMMdq_11 4093 +VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 4094 +VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 4095 +VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 4096 +VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 4097 +VMOVUPD_YMMqq_MEMqq 4098 +VMOVUPD_YMMqq_YMMqq_10 4099 +VMOVUPD_YMMqq_YMMqq_11 4100 +VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 4101 +VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 4102 +VMOVUPS_MEMdq_XMMdq 4103 +VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 4104 +VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 4105 +VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 4106 +VMOVUPS_MEMqq_YMMqq 4107 +VMOVUPS_XMMdq_MEMdq 4108 +VMOVUPS_XMMdq_XMMdq_10 4109 +VMOVUPS_XMMdq_XMMdq_11 4110 +VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 4111 +VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 4112 +VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 4113 +VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 4114 +VMOVUPS_YMMqq_MEMqq 4115 +VMOVUPS_YMMqq_YMMqq_10 4116 +VMOVUPS_YMMqq_YMMqq_11 4117 +VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 4118 +VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 4119 +VMOVW_GPR32f16_XMMf16_AVX512 4120 +VMOVW_MEMf16_XMMf16_AVX512 4121 +VMOVW_XMMf16_GPR32f16_AVX512 4122 +VMOVW_XMMf16_MEMf16_AVX512 4123 +VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb 4124 +VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb 4125 +VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb 4126 +VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb 4127 +VMPTRLD_MEMq 4128 +VMPTRST_MEMq 4129 +VMREAD_GPR32_GPR32 4130 +VMREAD_GPR64_GPR64 4131 +VMREAD_MEMd_GPR32 4132 +VMREAD_MEMq_GPR64 4133 +VMRESUME 4134 +VMRUN_ArAX 4135 +VMSAVE 4136 +VMULPD_XMMdq_XMMdq_MEMdq 4137 +VMULPD_XMMdq_XMMdq_XMMdq 4138 +VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 4139 +VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 4140 +VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 4141 +VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 4142 +VMULPD_YMMqq_YMMqq_MEMqq 4143 +VMULPD_YMMqq_YMMqq_YMMqq 4144 +VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 4145 +VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 4146 +VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 4147 +VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 4148 +VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 4149 +VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 4150 +VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 4151 +VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 4152 +VMULPS_XMMdq_XMMdq_MEMdq 4153 +VMULPS_XMMdq_XMMdq_XMMdq 4154 +VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 4155 +VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 4156 +VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 4157 +VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 4158 +VMULPS_YMMqq_YMMqq_MEMqq 4159 +VMULPS_YMMqq_YMMqq_YMMqq 4160 +VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 4161 +VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 4162 +VMULSD_XMMdq_XMMdq_MEMq 4163 +VMULSD_XMMdq_XMMdq_XMMq 4164 +VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 4165 +VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 4166 +VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 4167 +VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 4168 +VMULSS_XMMdq_XMMdq_MEMd 4169 +VMULSS_XMMdq_XMMdq_XMMd 4170 +VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 4171 +VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 4172 +VMWRITE_GPR32_GPR32 4173 +VMWRITE_GPR32_MEMd 4174 +VMWRITE_GPR64_GPR64 4175 +VMWRITE_GPR64_MEMq 4176 +VMXOFF 4177 +VMXON_MEMq 4178 +VORPD_XMMdq_XMMdq_MEMdq 4179 +VORPD_XMMdq_XMMdq_XMMdq 4180 +VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4181 +VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4182 +VORPD_YMMqq_YMMqq_MEMqq 4183 +VORPD_YMMqq_YMMqq_YMMqq 4184 +VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4185 +VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4186 +VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4187 +VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4188 +VORPS_XMMdq_XMMdq_MEMdq 4189 +VORPS_XMMdq_XMMdq_XMMdq 4190 +VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4191 +VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4192 +VORPS_YMMqq_YMMqq_MEMqq 4193 +VORPS_YMMqq_YMMqq_YMMqq 4194 +VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4195 +VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4196 +VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4197 +VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4198 +VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 4199 +VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 4200 +VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 4201 +VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 4202 +VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 4203 +VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 4204 +VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 4205 +VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 4206 +VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 4207 +VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 4208 +VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 4209 +VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 4210 +VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 4211 +VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 4212 +VPABSB_XMMdq_MEMdq 4213 +VPABSB_XMMdq_XMMdq 4214 +VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 4215 +VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 4216 +VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 4217 +VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 4218 +VPABSB_YMMqq_MEMqq 4219 +VPABSB_YMMqq_YMMqq 4220 +VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 4221 +VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 4222 +VPABSD_XMMdq_MEMdq 4223 +VPABSD_XMMdq_XMMdq 4224 +VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 4225 +VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 4226 +VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 4227 +VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 4228 +VPABSD_YMMqq_MEMqq 4229 +VPABSD_YMMqq_YMMqq 4230 +VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 4231 +VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 4232 +VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 4233 +VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 4234 +VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 4235 +VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 4236 +VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 4237 +VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 4238 +VPABSW_XMMdq_MEMdq 4239 +VPABSW_XMMdq_XMMdq 4240 +VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 4241 +VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 4242 +VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 4243 +VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 4244 +VPABSW_YMMqq_MEMqq 4245 +VPABSW_YMMqq_YMMqq 4246 +VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 4247 +VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 4248 +VPACKSSDW_XMMdq_XMMdq_MEMdq 4249 +VPACKSSDW_XMMdq_XMMdq_XMMdq 4250 +VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 4251 +VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 4252 +VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 4253 +VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 4254 +VPACKSSDW_YMMqq_YMMqq_MEMqq 4255 +VPACKSSDW_YMMqq_YMMqq_YMMqq 4256 +VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 4257 +VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 4258 +VPACKSSWB_XMMdq_XMMdq_MEMdq 4259 +VPACKSSWB_XMMdq_XMMdq_XMMdq 4260 +VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 4261 +VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 4262 +VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 4263 +VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 4264 +VPACKSSWB_YMMqq_YMMqq_MEMqq 4265 +VPACKSSWB_YMMqq_YMMqq_YMMqq 4266 +VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 4267 +VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 4268 +VPACKUSDW_XMMdq_XMMdq_MEMdq 4269 +VPACKUSDW_XMMdq_XMMdq_XMMdq 4270 +VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 4271 +VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 4272 +VPACKUSDW_YMMqq_YMMqq_MEMqq 4273 +VPACKUSDW_YMMqq_YMMqq_YMMqq 4274 +VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 4275 +VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 4276 +VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 4277 +VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 4278 +VPACKUSWB_XMMdq_XMMdq_MEMdq 4279 +VPACKUSWB_XMMdq_XMMdq_XMMdq 4280 +VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 4281 +VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 4282 +VPACKUSWB_YMMqq_YMMqq_MEMqq 4283 +VPACKUSWB_YMMqq_YMMqq_YMMqq 4284 +VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 4285 +VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 4286 +VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 4287 +VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 4288 +VPADDB_XMMdq_XMMdq_MEMdq 4289 +VPADDB_XMMdq_XMMdq_XMMdq 4290 +VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4291 +VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4292 +VPADDB_YMMqq_YMMqq_MEMqq 4293 +VPADDB_YMMqq_YMMqq_YMMqq 4294 +VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4295 +VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4296 +VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4297 +VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4298 +VPADDD_XMMdq_XMMdq_MEMdq 4299 +VPADDD_XMMdq_XMMdq_XMMdq 4300 +VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4301 +VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4302 +VPADDD_YMMqq_YMMqq_MEMqq 4303 +VPADDD_YMMqq_YMMqq_YMMqq 4304 +VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4305 +VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4306 +VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4307 +VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4308 +VPADDQ_XMMdq_XMMdq_MEMdq 4309 +VPADDQ_XMMdq_XMMdq_XMMdq 4310 +VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4311 +VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4312 +VPADDQ_YMMqq_YMMqq_MEMqq 4313 +VPADDQ_YMMqq_YMMqq_YMMqq 4314 +VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4315 +VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4316 +VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4317 +VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4318 +VPADDSB_XMMdq_XMMdq_MEMdq 4319 +VPADDSB_XMMdq_XMMdq_XMMdq 4320 +VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 4321 +VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 4322 +VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 4323 +VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 4324 +VPADDSB_YMMqq_YMMqq_MEMqq 4325 +VPADDSB_YMMqq_YMMqq_YMMqq 4326 +VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 4327 +VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 4328 +VPADDSW_XMMdq_XMMdq_MEMdq 4329 +VPADDSW_XMMdq_XMMdq_XMMdq 4330 +VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 4331 +VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 4332 +VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 4333 +VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 4334 +VPADDSW_YMMqq_YMMqq_MEMqq 4335 +VPADDSW_YMMqq_YMMqq_YMMqq 4336 +VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 4337 +VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 4338 +VPADDUSB_XMMdq_XMMdq_MEMdq 4339 +VPADDUSB_XMMdq_XMMdq_XMMdq 4340 +VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4341 +VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4342 +VPADDUSB_YMMqq_YMMqq_MEMqq 4343 +VPADDUSB_YMMqq_YMMqq_YMMqq 4344 +VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4345 +VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4346 +VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4347 +VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4348 +VPADDUSW_XMMdq_XMMdq_MEMdq 4349 +VPADDUSW_XMMdq_XMMdq_XMMdq 4350 +VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4351 +VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4352 +VPADDUSW_YMMqq_YMMqq_MEMqq 4353 +VPADDUSW_YMMqq_YMMqq_YMMqq 4354 +VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4355 +VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4356 +VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4357 +VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4358 +VPADDW_XMMdq_XMMdq_MEMdq 4359 +VPADDW_XMMdq_XMMdq_XMMdq 4360 +VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4361 +VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4362 +VPADDW_YMMqq_YMMqq_MEMqq 4363 +VPADDW_YMMqq_YMMqq_YMMqq 4364 +VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4365 +VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4366 +VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4367 +VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4368 +VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb 4369 +VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb 4370 +VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 4371 +VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 4372 +VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb 4373 +VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb 4374 +VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 4375 +VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 4376 +VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 4377 +VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 4378 +VPAND_XMMdq_XMMdq_MEMdq 4379 +VPAND_XMMdq_XMMdq_XMMdq 4380 +VPAND_YMMqq_YMMqq_MEMqq 4381 +VPAND_YMMqq_YMMqq_YMMqq 4382 +VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4383 +VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4384 +VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4385 +VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4386 +VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4387 +VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4388 +VPANDN_XMMdq_XMMdq_MEMdq 4389 +VPANDN_XMMdq_XMMdq_XMMdq 4390 +VPANDN_YMMqq_YMMqq_MEMqq 4391 +VPANDN_YMMqq_YMMqq_YMMqq 4392 +VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4393 +VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4394 +VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4395 +VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4396 +VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4397 +VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4398 +VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4399 +VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4400 +VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4401 +VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4402 +VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4403 +VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4404 +VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4405 +VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4406 +VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4407 +VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4408 +VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4409 +VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4410 +VPAVGB_XMMdq_XMMdq_MEMdq 4411 +VPAVGB_XMMdq_XMMdq_XMMdq 4412 +VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4413 +VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4414 +VPAVGB_YMMqq_YMMqq_MEMqq 4415 +VPAVGB_YMMqq_YMMqq_YMMqq 4416 +VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4417 +VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4418 +VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4419 +VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4420 +VPAVGW_XMMdq_XMMdq_MEMdq 4421 +VPAVGW_XMMdq_XMMdq_XMMdq 4422 +VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4423 +VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4424 +VPAVGW_YMMqq_YMMqq_MEMqq 4425 +VPAVGW_YMMqq_YMMqq_YMMqq 4426 +VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4427 +VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4428 +VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4429 +VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4430 +VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb 4431 +VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb 4432 +VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb 4433 +VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb 4434 +VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4435 +VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4436 +VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4437 +VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4438 +VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4439 +VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4440 +VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4441 +VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4442 +VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4443 +VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4444 +VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4445 +VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4446 +VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4447 +VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4448 +VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4449 +VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4450 +VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4451 +VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4452 +VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4453 +VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4454 +VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4455 +VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4456 +VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4457 +VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4458 +VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq 4459 +VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq 4460 +VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq 4461 +VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq 4462 +VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb 4463 +VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb 4464 +VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb 4465 +VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb 4466 +VPBROADCASTB_XMMdq_MEMb 4467 +VPBROADCASTB_XMMdq_XMMb 4468 +VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 4469 +VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 4470 +VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 4471 +VPBROADCASTB_YMMqq_MEMb 4472 +VPBROADCASTB_YMMqq_XMMb 4473 +VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 4474 +VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 4475 +VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 4476 +VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 4477 +VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 4478 +VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 4479 +VPBROADCASTD_XMMdq_MEMd 4480 +VPBROADCASTD_XMMdq_XMMd 4481 +VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 4482 +VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 4483 +VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 4484 +VPBROADCASTD_YMMqq_MEMd 4485 +VPBROADCASTD_YMMqq_XMMd 4486 +VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 4487 +VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 4488 +VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 4489 +VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 4490 +VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 4491 +VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 4492 +VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 4493 +VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 4494 +VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD 4495 +VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 4496 +VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 4497 +VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD 4498 +VPBROADCASTQ_XMMdq_MEMq 4499 +VPBROADCASTQ_XMMdq_XMMq 4500 +VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 4501 +VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 4502 +VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 4503 +VPBROADCASTQ_YMMqq_MEMq 4504 +VPBROADCASTQ_YMMqq_XMMq 4505 +VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 4506 +VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 4507 +VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 4508 +VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 4509 +VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 4510 +VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 4511 +VPBROADCASTW_XMMdq_MEMw 4512 +VPBROADCASTW_XMMdq_XMMw 4513 +VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 4514 +VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 4515 +VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 4516 +VPBROADCASTW_YMMqq_MEMw 4517 +VPBROADCASTW_YMMqq_XMMw 4518 +VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 4519 +VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 4520 +VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 4521 +VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 4522 +VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 4523 +VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 4524 +VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb 4525 +VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb 4526 +VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 4527 +VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 4528 +VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 4529 +VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 4530 +VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 4531 +VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 4532 +VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 4533 +VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 4534 +VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq 4535 +VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq 4536 +VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq 4537 +VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq 4538 +VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq 4539 +VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq 4540 +VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 4541 +VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 4542 +VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 4543 +VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 4544 +VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 4545 +VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 4546 +VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 4547 +VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 4548 +VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 4549 +VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 4550 +VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 4551 +VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 4552 +VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 4553 +VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 4554 +VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 4555 +VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 4556 +VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 4557 +VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 4558 +VPCMPEQB_XMMdq_XMMdq_MEMdq 4559 +VPCMPEQB_XMMdq_XMMdq_XMMdq 4560 +VPCMPEQB_YMMqq_YMMqq_MEMqq 4561 +VPCMPEQB_YMMqq_YMMqq_YMMqq 4562 +VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 4563 +VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 4564 +VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 4565 +VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 4566 +VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 4567 +VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 4568 +VPCMPEQD_XMMdq_XMMdq_MEMdq 4569 +VPCMPEQD_XMMdq_XMMdq_XMMdq 4570 +VPCMPEQD_YMMqq_YMMqq_MEMqq 4571 +VPCMPEQD_YMMqq_YMMqq_YMMqq 4572 +VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 4573 +VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 4574 +VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 4575 +VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 4576 +VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 4577 +VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 4578 +VPCMPEQQ_XMMdq_XMMdq_MEMdq 4579 +VPCMPEQQ_XMMdq_XMMdq_XMMdq 4580 +VPCMPEQQ_YMMqq_YMMqq_MEMqq 4581 +VPCMPEQQ_YMMqq_YMMqq_YMMqq 4582 +VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 4583 +VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 4584 +VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 4585 +VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 4586 +VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 4587 +VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 4588 +VPCMPEQW_XMMdq_XMMdq_MEMdq 4589 +VPCMPEQW_XMMdq_XMMdq_XMMdq 4590 +VPCMPEQW_YMMqq_YMMqq_MEMqq 4591 +VPCMPEQW_YMMqq_YMMqq_YMMqq 4592 +VPCMPESTRI_XMMdq_MEMdq_IMMb 4593 +VPCMPESTRI_XMMdq_XMMdq_IMMb 4594 +VPCMPESTRI64_XMMdq_MEMdq_IMMb 4595 +VPCMPESTRI64_XMMdq_XMMdq_IMMb 4596 +VPCMPESTRM_XMMdq_MEMdq_IMMb 4597 +VPCMPESTRM_XMMdq_XMMdq_IMMb 4598 +VPCMPESTRM64_XMMdq_MEMdq_IMMb 4599 +VPCMPESTRM64_XMMdq_XMMdq_IMMb 4600 +VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 4601 +VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 4602 +VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 4603 +VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 4604 +VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 4605 +VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 4606 +VPCMPGTB_XMMdq_XMMdq_MEMdq 4607 +VPCMPGTB_XMMdq_XMMdq_XMMdq 4608 +VPCMPGTB_YMMqq_YMMqq_MEMqq 4609 +VPCMPGTB_YMMqq_YMMqq_YMMqq 4610 +VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 4611 +VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 4612 +VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 4613 +VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 4614 +VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 4615 +VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 4616 +VPCMPGTD_XMMdq_XMMdq_MEMdq 4617 +VPCMPGTD_XMMdq_XMMdq_XMMdq 4618 +VPCMPGTD_YMMqq_YMMqq_MEMqq 4619 +VPCMPGTD_YMMqq_YMMqq_YMMqq 4620 +VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 4621 +VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 4622 +VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 4623 +VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 4624 +VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 4625 +VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 4626 +VPCMPGTQ_XMMdq_XMMdq_MEMdq 4627 +VPCMPGTQ_XMMdq_XMMdq_XMMdq 4628 +VPCMPGTQ_YMMqq_YMMqq_MEMqq 4629 +VPCMPGTQ_YMMqq_YMMqq_YMMqq 4630 +VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 4631 +VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 4632 +VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 4633 +VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 4634 +VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 4635 +VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 4636 +VPCMPGTW_XMMdq_XMMdq_MEMdq 4637 +VPCMPGTW_XMMdq_XMMdq_XMMdq 4638 +VPCMPGTW_YMMqq_YMMqq_MEMqq 4639 +VPCMPGTW_YMMqq_YMMqq_YMMqq 4640 +VPCMPISTRI_XMMdq_MEMdq_IMMb 4641 +VPCMPISTRI_XMMdq_XMMdq_IMMb 4642 +VPCMPISTRI64_XMMdq_MEMdq_IMMb 4643 +VPCMPISTRI64_XMMdq_XMMdq_IMMb 4644 +VPCMPISTRM_XMMdq_MEMdq_IMMb 4645 +VPCMPISTRM_XMMdq_XMMdq_IMMb 4646 +VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 4647 +VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 4648 +VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 4649 +VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 4650 +VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 4651 +VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 4652 +VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 4653 +VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 4654 +VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 4655 +VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 4656 +VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 4657 +VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 4658 +VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 4659 +VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 4660 +VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 4661 +VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 4662 +VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 4663 +VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 4664 +VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 4665 +VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 4666 +VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 4667 +VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 4668 +VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 4669 +VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 4670 +VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 4671 +VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 4672 +VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 4673 +VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 4674 +VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 4675 +VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 4676 +VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 4677 +VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 4678 +VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 4679 +VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 4680 +VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 4681 +VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 4682 +VPCOMB_XMMdq_XMMdq_MEMdq_IMMb 4683 +VPCOMB_XMMdq_XMMdq_XMMdq_IMMb 4684 +VPCOMD_XMMdq_XMMdq_MEMdq_IMMb 4685 +VPCOMD_XMMdq_XMMdq_XMMdq_IMMb 4686 +VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 4687 +VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 4688 +VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 4689 +VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 4690 +VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 4691 +VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 4692 +VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 4693 +VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 4694 +VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 4695 +VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 4696 +VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 4697 +VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 4698 +VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 4699 +VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 4700 +VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 4701 +VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 4702 +VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 4703 +VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 4704 +VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 4705 +VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 4706 +VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 4707 +VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 4708 +VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 4709 +VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 4710 +VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb 4711 +VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb 4712 +VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb 4713 +VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb 4714 +VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb 4715 +VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb 4716 +VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb 4717 +VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb 4718 +VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb 4719 +VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb 4720 +VPCOMW_XMMdq_XMMdq_MEMdq_IMMb 4721 +VPCOMW_XMMdq_XMMdq_XMMdq_IMMb 4722 +VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 4723 +VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 4724 +VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 4725 +VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 4726 +VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 4727 +VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 4728 +VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 4729 +VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 4730 +VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 4731 +VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 4732 +VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 4733 +VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 4734 +VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 4735 +VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 4736 +VPDPBUSD_XMMi32_XMMu32_MEMu32 4737 +VPDPBUSD_XMMi32_XMMu32_XMMu32 4738 +VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 4739 +VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 4740 +VPDPBUSD_YMMi32_YMMu32_MEMu32 4741 +VPDPBUSD_YMMi32_YMMu32_YMMu32 4742 +VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 4743 +VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 4744 +VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 4745 +VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 4746 +VPDPBUSDS_XMMi32_XMMu32_MEMu32 4747 +VPDPBUSDS_XMMi32_XMMu32_XMMu32 4748 +VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 4749 +VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 4750 +VPDPBUSDS_YMMi32_YMMu32_MEMu32 4751 +VPDPBUSDS_YMMi32_YMMu32_YMMu32 4752 +VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 4753 +VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 4754 +VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 4755 +VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 4756 +VPDPWSSD_XMMi32_XMMu32_MEMu32 4757 +VPDPWSSD_XMMi32_XMMu32_XMMu32 4758 +VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 4759 +VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 4760 +VPDPWSSD_YMMi32_YMMu32_MEMu32 4761 +VPDPWSSD_YMMi32_YMMu32_YMMu32 4762 +VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 4763 +VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 4764 +VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 4765 +VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 4766 +VPDPWSSDS_XMMi32_XMMu32_MEMu32 4767 +VPDPWSSDS_XMMi32_XMMu32_XMMu32 4768 +VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 4769 +VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 4770 +VPDPWSSDS_YMMi32_YMMu32_MEMu32 4771 +VPDPWSSDS_YMMi32_YMMu32_YMMu32 4772 +VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 4773 +VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 4774 +VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb 4775 +VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb 4776 +VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb 4777 +VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb 4778 +VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4779 +VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4780 +VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4781 +VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4782 +VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4783 +VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4784 +VPERMD_YMMqq_YMMqq_MEMqq 4785 +VPERMD_YMMqq_YMMqq_YMMqq 4786 +VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4787 +VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4788 +VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4789 +VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4790 +VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4791 +VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4792 +VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4793 +VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4794 +VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4795 +VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4796 +VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4797 +VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4798 +VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4799 +VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4800 +VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4801 +VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4802 +VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 4803 +VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 4804 +VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 4805 +VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 4806 +VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 4807 +VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 4808 +VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 4809 +VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 4810 +VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 4811 +VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 4812 +VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 4813 +VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 4814 +VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4815 +VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4816 +VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4817 +VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4818 +VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4819 +VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4820 +VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4821 +VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4822 +VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4823 +VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4824 +VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4825 +VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4826 +VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb 4827 +VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb 4828 +VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb 4829 +VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb 4830 +VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb 4831 +VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb 4832 +VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb 4833 +VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb 4834 +VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb 4835 +VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb 4836 +VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb 4837 +VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb 4838 +VPERMILPD_XMMdq_MEMdq_IMMb 4839 +VPERMILPD_XMMdq_XMMdq_IMMb 4840 +VPERMILPD_XMMdq_XMMdq_MEMdq 4841 +VPERMILPD_XMMdq_XMMdq_XMMdq 4842 +VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 4843 +VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 4844 +VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 4845 +VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 4846 +VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 4847 +VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 4848 +VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 4849 +VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 4850 +VPERMILPD_YMMqq_MEMqq_IMMb 4851 +VPERMILPD_YMMqq_YMMqq_IMMb 4852 +VPERMILPD_YMMqq_YMMqq_MEMqq 4853 +VPERMILPD_YMMqq_YMMqq_YMMqq 4854 +VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 4855 +VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 4856 +VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 4857 +VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 4858 +VPERMILPS_XMMdq_MEMdq_IMMb 4859 +VPERMILPS_XMMdq_XMMdq_IMMb 4860 +VPERMILPS_XMMdq_XMMdq_MEMdq 4861 +VPERMILPS_XMMdq_XMMdq_XMMdq 4862 +VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 4863 +VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 4864 +VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 4865 +VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 4866 +VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 4867 +VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 4868 +VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 4869 +VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 4870 +VPERMILPS_YMMqq_MEMqq_IMMb 4871 +VPERMILPS_YMMqq_YMMqq_IMMb 4872 +VPERMILPS_YMMqq_YMMqq_MEMqq 4873 +VPERMILPS_YMMqq_YMMqq_YMMqq 4874 +VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 4875 +VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 4876 +VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 4877 +VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 4878 +VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 4879 +VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 4880 +VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 4881 +VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 4882 +VPERMPD_YMMqq_MEMqq_IMMb 4883 +VPERMPD_YMMqq_YMMqq_IMMb 4884 +VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 4885 +VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 4886 +VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 4887 +VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 4888 +VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 4889 +VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 4890 +VPERMPS_YMMqq_YMMqq_MEMqq 4891 +VPERMPS_YMMqq_YMMqq_YMMqq 4892 +VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 4893 +VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 4894 +VPERMQ_YMMqq_MEMqq_IMMb 4895 +VPERMQ_YMMqq_YMMqq_IMMb 4896 +VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 4897 +VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 4898 +VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4899 +VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4900 +VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 4901 +VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 4902 +VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4903 +VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4904 +VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 4905 +VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 4906 +VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 4907 +VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 4908 +VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 4909 +VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 4910 +VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 4911 +VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 4912 +VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 4913 +VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 4914 +VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 4915 +VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 4916 +VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 4917 +VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 4918 +VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 4919 +VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 4920 +VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 4921 +VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 4922 +VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 4923 +VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 4924 +VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 4925 +VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 4926 +VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 4927 +VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 4928 +VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 4929 +VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 4930 +VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 4931 +VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 4932 +VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 4933 +VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 4934 +VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4935 +VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4936 +VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4937 +VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4938 +VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4939 +VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4940 +VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 4941 +VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 4942 +VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 4943 +VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 4944 +VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 4945 +VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 4946 +VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 4947 +VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 4948 +VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 4949 +VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 4950 +VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 4951 +VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 4952 +VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 4953 +VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 4954 +VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 4955 +VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 4956 +VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 4957 +VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 4958 +VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 4959 +VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 4960 +VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 4961 +VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 4962 +VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 4963 +VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 4964 +VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 4965 +VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 4966 +VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 4967 +VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 4968 +VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 4969 +VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 4970 +VPEXTRB_GPR32d_XMMdq_IMMb 4971 +VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 4972 +VPEXTRB_MEMb_XMMdq_IMMb 4973 +VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 4974 +VPEXTRD_GPR32d_XMMdq_IMMb 4975 +VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 4976 +VPEXTRD_MEMd_XMMdq_IMMb 4977 +VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 4978 +VPEXTRQ_GPR64q_XMMdq_IMMb 4979 +VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 4980 +VPEXTRQ_MEMq_XMMdq_IMMb 4981 +VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 4982 +VPEXTRW_GPR32d_XMMdq_IMMb_15 4983 +VPEXTRW_GPR32d_XMMdq_IMMb_C5 4984 +VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 4985 +VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 4986 +VPEXTRW_MEMw_XMMdq_IMMb 4987 +VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 4988 +VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 4989 +VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 4990 +VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 4991 +VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 4992 +VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 4993 +VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 4994 +VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 4995 +VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 4996 +VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 4997 +VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 4998 +VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 4999 +VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 5000 +VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 5001 +VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 5002 +VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 5003 +VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 5004 +VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 5005 +VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 5006 +VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 5007 +VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 5008 +VPHADDBD_XMMdq_MEMdq 5009 +VPHADDBD_XMMdq_XMMdq 5010 +VPHADDBQ_XMMdq_MEMdq 5011 +VPHADDBQ_XMMdq_XMMdq 5012 +VPHADDBW_XMMdq_MEMdq 5013 +VPHADDBW_XMMdq_XMMdq 5014 +VPHADDD_XMMdq_XMMdq_MEMdq 5015 +VPHADDD_XMMdq_XMMdq_XMMdq 5016 +VPHADDD_YMMqq_YMMqq_MEMqq 5017 +VPHADDD_YMMqq_YMMqq_YMMqq 5018 +VPHADDDQ_XMMdq_MEMdq 5019 +VPHADDDQ_XMMdq_XMMdq 5020 +VPHADDSW_XMMdq_XMMdq_MEMdq 5021 +VPHADDSW_XMMdq_XMMdq_XMMdq 5022 +VPHADDSW_YMMqq_YMMqq_MEMqq 5023 +VPHADDSW_YMMqq_YMMqq_YMMqq 5024 +VPHADDUBD_XMMdq_MEMdq 5025 +VPHADDUBD_XMMdq_XMMdq 5026 +VPHADDUBQ_XMMdq_MEMdq 5027 +VPHADDUBQ_XMMdq_XMMdq 5028 +VPHADDUBW_XMMdq_MEMdq 5029 +VPHADDUBW_XMMdq_XMMdq 5030 +VPHADDUDQ_XMMdq_MEMdq 5031 +VPHADDUDQ_XMMdq_XMMdq 5032 +VPHADDUWD_XMMdq_MEMdq 5033 +VPHADDUWD_XMMdq_XMMdq 5034 +VPHADDUWQ_XMMdq_MEMdq 5035 +VPHADDUWQ_XMMdq_XMMdq 5036 +VPHADDW_XMMdq_XMMdq_MEMdq 5037 +VPHADDW_XMMdq_XMMdq_XMMdq 5038 +VPHADDW_YMMqq_YMMqq_MEMqq 5039 +VPHADDW_YMMqq_YMMqq_YMMqq 5040 +VPHADDWD_XMMdq_MEMdq 5041 +VPHADDWD_XMMdq_XMMdq 5042 +VPHADDWQ_XMMdq_MEMdq 5043 +VPHADDWQ_XMMdq_XMMdq 5044 +VPHMINPOSUW_XMMdq_MEMdq 5045 +VPHMINPOSUW_XMMdq_XMMdq 5046 +VPHSUBBW_XMMdq_MEMdq 5047 +VPHSUBBW_XMMdq_XMMdq 5048 +VPHSUBD_XMMdq_XMMdq_MEMdq 5049 +VPHSUBD_XMMdq_XMMdq_XMMdq 5050 +VPHSUBD_YMMqq_YMMqq_MEMqq 5051 +VPHSUBD_YMMqq_YMMqq_YMMqq 5052 +VPHSUBDQ_XMMdq_MEMdq 5053 +VPHSUBDQ_XMMdq_XMMdq 5054 +VPHSUBSW_XMMdq_XMMdq_MEMdq 5055 +VPHSUBSW_XMMdq_XMMdq_XMMdq 5056 +VPHSUBSW_YMMqq_YMMqq_MEMqq 5057 +VPHSUBSW_YMMqq_YMMqq_YMMqq 5058 +VPHSUBW_XMMdq_XMMdq_MEMdq 5059 +VPHSUBW_XMMdq_XMMdq_XMMdq 5060 +VPHSUBW_YMMqq_YMMqq_MEMqq 5061 +VPHSUBW_YMMqq_YMMqq_YMMqq 5062 +VPHSUBWD_XMMdq_MEMdq 5063 +VPHSUBWD_XMMdq_XMMdq 5064 +VPINSRB_XMMdq_XMMdq_GPR32d_IMMb 5065 +VPINSRB_XMMdq_XMMdq_MEMb_IMMb 5066 +VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 5067 +VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 5068 +VPINSRD_XMMdq_XMMdq_GPR32d_IMMb 5069 +VPINSRD_XMMdq_XMMdq_MEMd_IMMb 5070 +VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 5071 +VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 5072 +VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb 5073 +VPINSRQ_XMMdq_XMMdq_MEMq_IMMb 5074 +VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 5075 +VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 5076 +VPINSRW_XMMdq_XMMdq_GPR32d_IMMb 5077 +VPINSRW_XMMdq_XMMdq_MEMw_IMMb 5078 +VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 5079 +VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 5080 +VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 5081 +VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 5082 +VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 5083 +VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 5084 +VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD 5085 +VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD 5086 +VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 5087 +VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 5088 +VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 5089 +VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 5090 +VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD 5091 +VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD 5092 +VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq 5093 +VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq 5094 +VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq 5095 +VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq 5096 +VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq 5097 +VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq 5098 +VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq 5099 +VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq 5100 +VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq 5101 +VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq 5102 +VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq 5103 +VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq 5104 +VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq 5105 +VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq 5106 +VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq 5107 +VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq 5108 +VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq 5109 +VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq 5110 +VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq 5111 +VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq 5112 +VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq 5113 +VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq 5114 +VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq 5115 +VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq 5116 +VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5117 +VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5118 +VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5119 +VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5120 +VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5121 +VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5122 +VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5123 +VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5124 +VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5125 +VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5126 +VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5127 +VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5128 +VPMADDUBSW_XMMdq_XMMdq_MEMdq 5129 +VPMADDUBSW_XMMdq_XMMdq_XMMdq 5130 +VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 5131 +VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 5132 +VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 5133 +VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 5134 +VPMADDUBSW_YMMqq_YMMqq_MEMqq 5135 +VPMADDUBSW_YMMqq_YMMqq_YMMqq 5136 +VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 5137 +VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 5138 +VPMADDWD_XMMdq_XMMdq_MEMdq 5139 +VPMADDWD_XMMdq_XMMdq_XMMdq 5140 +VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 5141 +VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 5142 +VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 5143 +VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 5144 +VPMADDWD_YMMqq_YMMqq_MEMqq 5145 +VPMADDWD_YMMqq_YMMqq_YMMqq 5146 +VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 5147 +VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 5148 +VPMASKMOVD_MEMdq_XMMdq_XMMdq 5149 +VPMASKMOVD_MEMqq_YMMqq_YMMqq 5150 +VPMASKMOVD_XMMdq_XMMdq_MEMdq 5151 +VPMASKMOVD_YMMqq_YMMqq_MEMqq 5152 +VPMASKMOVQ_MEMdq_XMMdq_XMMdq 5153 +VPMASKMOVQ_MEMqq_YMMqq_YMMqq 5154 +VPMASKMOVQ_XMMdq_XMMdq_MEMdq 5155 +VPMASKMOVQ_YMMqq_YMMqq_MEMqq 5156 +VPMAXSB_XMMdq_XMMdq_MEMdq 5157 +VPMAXSB_XMMdq_XMMdq_XMMdq 5158 +VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 5159 +VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 5160 +VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 5161 +VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 5162 +VPMAXSB_YMMqq_YMMqq_MEMqq 5163 +VPMAXSB_YMMqq_YMMqq_YMMqq 5164 +VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 5165 +VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 5166 +VPMAXSD_XMMdq_XMMdq_MEMdq 5167 +VPMAXSD_XMMdq_XMMdq_XMMdq 5168 +VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 5169 +VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 5170 +VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 5171 +VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 5172 +VPMAXSD_YMMqq_YMMqq_MEMqq 5173 +VPMAXSD_YMMqq_YMMqq_YMMqq 5174 +VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 5175 +VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 5176 +VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 5177 +VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 5178 +VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 5179 +VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 5180 +VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 5181 +VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 5182 +VPMAXSW_XMMdq_XMMdq_MEMdq 5183 +VPMAXSW_XMMdq_XMMdq_XMMdq 5184 +VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 5185 +VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 5186 +VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 5187 +VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 5188 +VPMAXSW_YMMqq_YMMqq_MEMqq 5189 +VPMAXSW_YMMqq_YMMqq_YMMqq 5190 +VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 5191 +VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 5192 +VPMAXUB_XMMdq_XMMdq_MEMdq 5193 +VPMAXUB_XMMdq_XMMdq_XMMdq 5194 +VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 5195 +VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 5196 +VPMAXUB_YMMqq_YMMqq_MEMqq 5197 +VPMAXUB_YMMqq_YMMqq_YMMqq 5198 +VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 5199 +VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 5200 +VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 5201 +VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 5202 +VPMAXUD_XMMdq_XMMdq_MEMdq 5203 +VPMAXUD_XMMdq_XMMdq_XMMdq 5204 +VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5205 +VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5206 +VPMAXUD_YMMqq_YMMqq_MEMqq 5207 +VPMAXUD_YMMqq_YMMqq_YMMqq 5208 +VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5209 +VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5210 +VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5211 +VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5212 +VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5213 +VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5214 +VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5215 +VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5216 +VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5217 +VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5218 +VPMAXUW_XMMdq_XMMdq_MEMdq 5219 +VPMAXUW_XMMdq_XMMdq_XMMdq 5220 +VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5221 +VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5222 +VPMAXUW_YMMqq_YMMqq_MEMqq 5223 +VPMAXUW_YMMqq_YMMqq_YMMqq 5224 +VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5225 +VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5226 +VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5227 +VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5228 +VPMINSB_XMMdq_XMMdq_MEMdq 5229 +VPMINSB_XMMdq_XMMdq_XMMdq 5230 +VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 5231 +VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 5232 +VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 5233 +VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 5234 +VPMINSB_YMMqq_YMMqq_MEMqq 5235 +VPMINSB_YMMqq_YMMqq_YMMqq 5236 +VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 5237 +VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 5238 +VPMINSD_XMMdq_XMMdq_MEMdq 5239 +VPMINSD_XMMdq_XMMdq_XMMdq 5240 +VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 5241 +VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 5242 +VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 5243 +VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 5244 +VPMINSD_YMMqq_YMMqq_MEMqq 5245 +VPMINSD_YMMqq_YMMqq_YMMqq 5246 +VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 5247 +VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 5248 +VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 5249 +VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 5250 +VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 5251 +VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 5252 +VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 5253 +VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 5254 +VPMINSW_XMMdq_XMMdq_MEMdq 5255 +VPMINSW_XMMdq_XMMdq_XMMdq 5256 +VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 5257 +VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 5258 +VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 5259 +VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 5260 +VPMINSW_YMMqq_YMMqq_MEMqq 5261 +VPMINSW_YMMqq_YMMqq_YMMqq 5262 +VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 5263 +VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 5264 +VPMINUB_XMMdq_XMMdq_MEMdq 5265 +VPMINUB_XMMdq_XMMdq_XMMdq 5266 +VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 5267 +VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 5268 +VPMINUB_YMMqq_YMMqq_MEMqq 5269 +VPMINUB_YMMqq_YMMqq_YMMqq 5270 +VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 5271 +VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 5272 +VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 5273 +VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 5274 +VPMINUD_XMMdq_XMMdq_MEMdq 5275 +VPMINUD_XMMdq_XMMdq_XMMdq 5276 +VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5277 +VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5278 +VPMINUD_YMMqq_YMMqq_MEMqq 5279 +VPMINUD_YMMqq_YMMqq_YMMqq 5280 +VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5281 +VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5282 +VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5283 +VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5284 +VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5285 +VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5286 +VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5287 +VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5288 +VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5289 +VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5290 +VPMINUW_XMMdq_XMMdq_MEMdq 5291 +VPMINUW_XMMdq_XMMdq_XMMdq 5292 +VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5293 +VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5294 +VPMINUW_YMMqq_YMMqq_MEMqq 5295 +VPMINUW_YMMqq_YMMqq_YMMqq 5296 +VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5297 +VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5298 +VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5299 +VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5300 +VPMOVB2M_MASKmskw_XMMu8_AVX512 5301 +VPMOVB2M_MASKmskw_YMMu8_AVX512 5302 +VPMOVB2M_MASKmskw_ZMMu8_AVX512 5303 +VPMOVD2M_MASKmskw_XMMu32_AVX512 5304 +VPMOVD2M_MASKmskw_YMMu32_AVX512 5305 +VPMOVD2M_MASKmskw_ZMMu32_AVX512 5306 +VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 5307 +VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 5308 +VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 5309 +VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 5310 +VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 5311 +VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 5312 +VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 5313 +VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 5314 +VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 5315 +VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 5316 +VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 5317 +VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 5318 +VPMOVM2B_XMMu8_MASKmskw_AVX512 5319 +VPMOVM2B_YMMu8_MASKmskw_AVX512 5320 +VPMOVM2B_ZMMu8_MASKmskw_AVX512 5321 +VPMOVM2D_XMMu32_MASKmskw_AVX512 5322 +VPMOVM2D_YMMu32_MASKmskw_AVX512 5323 +VPMOVM2D_ZMMu32_MASKmskw_AVX512 5324 +VPMOVM2Q_XMMu64_MASKmskw_AVX512 5325 +VPMOVM2Q_YMMu64_MASKmskw_AVX512 5326 +VPMOVM2Q_ZMMu64_MASKmskw_AVX512 5327 +VPMOVM2W_XMMu16_MASKmskw_AVX512 5328 +VPMOVM2W_YMMu16_MASKmskw_AVX512 5329 +VPMOVM2W_ZMMu16_MASKmskw_AVX512 5330 +VPMOVMSKB_GPR32d_XMMdq 5331 +VPMOVMSKB_GPR32d_YMMqq 5332 +VPMOVQ2M_MASKmskw_XMMu64_AVX512 5333 +VPMOVQ2M_MASKmskw_YMMu64_AVX512 5334 +VPMOVQ2M_MASKmskw_ZMMu64_AVX512 5335 +VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 5336 +VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 5337 +VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 5338 +VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 5339 +VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 5340 +VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 5341 +VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 5342 +VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 5343 +VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 5344 +VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 5345 +VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 5346 +VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 5347 +VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 5348 +VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 5349 +VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 5350 +VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 5351 +VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 5352 +VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 5353 +VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 5354 +VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 5355 +VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 5356 +VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 5357 +VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 5358 +VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 5359 +VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 5360 +VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 5361 +VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 5362 +VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 5363 +VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 5364 +VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 5365 +VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 5366 +VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 5367 +VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 5368 +VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 5369 +VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 5370 +VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 5371 +VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 5372 +VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 5373 +VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 5374 +VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 5375 +VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 5376 +VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 5377 +VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 5378 +VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 5379 +VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 5380 +VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 5381 +VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 5382 +VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 5383 +VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 5384 +VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 5385 +VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 5386 +VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 5387 +VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 5388 +VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 5389 +VPMOVSXBD_XMMdq_MEMd 5390 +VPMOVSXBD_XMMdq_XMMd 5391 +VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 5392 +VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 5393 +VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 5394 +VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 5395 +VPMOVSXBD_YMMqq_MEMq 5396 +VPMOVSXBD_YMMqq_XMMq 5397 +VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 5398 +VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 5399 +VPMOVSXBQ_XMMdq_MEMw 5400 +VPMOVSXBQ_XMMdq_XMMw 5401 +VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 5402 +VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 5403 +VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 5404 +VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 5405 +VPMOVSXBQ_YMMqq_MEMd 5406 +VPMOVSXBQ_YMMqq_XMMd 5407 +VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 5408 +VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 5409 +VPMOVSXBW_XMMdq_MEMq 5410 +VPMOVSXBW_XMMdq_XMMq 5411 +VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 5412 +VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 5413 +VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 5414 +VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 5415 +VPMOVSXBW_YMMqq_MEMdq 5416 +VPMOVSXBW_YMMqq_XMMdq 5417 +VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 5418 +VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 5419 +VPMOVSXDQ_XMMdq_MEMq 5420 +VPMOVSXDQ_XMMdq_XMMq 5421 +VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 5422 +VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 5423 +VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 5424 +VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 5425 +VPMOVSXDQ_YMMqq_MEMdq 5426 +VPMOVSXDQ_YMMqq_XMMdq 5427 +VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 5428 +VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 5429 +VPMOVSXWD_XMMdq_MEMq 5430 +VPMOVSXWD_XMMdq_XMMq 5431 +VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 5432 +VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 5433 +VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 5434 +VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 5435 +VPMOVSXWD_YMMqq_MEMdq 5436 +VPMOVSXWD_YMMqq_XMMdq 5437 +VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 5438 +VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 5439 +VPMOVSXWQ_XMMdq_MEMd 5440 +VPMOVSXWQ_XMMdq_XMMd 5441 +VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 5442 +VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 5443 +VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 5444 +VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 5445 +VPMOVSXWQ_YMMqq_MEMq 5446 +VPMOVSXWQ_YMMqq_XMMq 5447 +VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 5448 +VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 5449 +VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 5450 +VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 5451 +VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 5452 +VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 5453 +VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 5454 +VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 5455 +VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 5456 +VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 5457 +VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 5458 +VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 5459 +VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 5460 +VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 5461 +VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 5462 +VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 5463 +VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 5464 +VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 5465 +VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 5466 +VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 5467 +VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 5468 +VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 5469 +VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 5470 +VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 5471 +VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 5472 +VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 5473 +VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 5474 +VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 5475 +VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 5476 +VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 5477 +VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 5478 +VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 5479 +VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 5480 +VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 5481 +VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 5482 +VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 5483 +VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 5484 +VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 5485 +VPMOVW2M_MASKmskw_XMMu16_AVX512 5486 +VPMOVW2M_MASKmskw_YMMu16_AVX512 5487 +VPMOVW2M_MASKmskw_ZMMu16_AVX512 5488 +VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 5489 +VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 5490 +VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 5491 +VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 5492 +VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 5493 +VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 5494 +VPMOVZXBD_XMMdq_MEMd 5495 +VPMOVZXBD_XMMdq_XMMd 5496 +VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 5497 +VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 5498 +VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 5499 +VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 5500 +VPMOVZXBD_YMMqq_MEMq 5501 +VPMOVZXBD_YMMqq_XMMq 5502 +VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 5503 +VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 5504 +VPMOVZXBQ_XMMdq_MEMw 5505 +VPMOVZXBQ_XMMdq_XMMw 5506 +VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 5507 +VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 5508 +VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 5509 +VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 5510 +VPMOVZXBQ_YMMqq_MEMd 5511 +VPMOVZXBQ_YMMqq_XMMd 5512 +VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 5513 +VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 5514 +VPMOVZXBW_XMMdq_MEMq 5515 +VPMOVZXBW_XMMdq_XMMq 5516 +VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 5517 +VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 5518 +VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 5519 +VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 5520 +VPMOVZXBW_YMMqq_MEMdq 5521 +VPMOVZXBW_YMMqq_XMMdq 5522 +VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 5523 +VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 5524 +VPMOVZXDQ_XMMdq_MEMq 5525 +VPMOVZXDQ_XMMdq_XMMq 5526 +VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 5527 +VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 5528 +VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 5529 +VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 5530 +VPMOVZXDQ_YMMqq_MEMdq 5531 +VPMOVZXDQ_YMMqq_XMMdq 5532 +VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 5533 +VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 5534 +VPMOVZXWD_XMMdq_MEMq 5535 +VPMOVZXWD_XMMdq_XMMq 5536 +VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 5537 +VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 5538 +VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 5539 +VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 5540 +VPMOVZXWD_YMMqq_MEMdq 5541 +VPMOVZXWD_YMMqq_XMMdq 5542 +VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 5543 +VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 5544 +VPMOVZXWQ_XMMdq_MEMd 5545 +VPMOVZXWQ_XMMdq_XMMd 5546 +VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 5547 +VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 5548 +VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 5549 +VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 5550 +VPMOVZXWQ_YMMqq_MEMq 5551 +VPMOVZXWQ_YMMqq_XMMq 5552 +VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 5553 +VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 5554 +VPMULDQ_XMMdq_XMMdq_MEMdq 5555 +VPMULDQ_XMMdq_XMMdq_XMMdq 5556 +VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 5557 +VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 5558 +VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 5559 +VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 5560 +VPMULDQ_YMMqq_YMMqq_MEMqq 5561 +VPMULDQ_YMMqq_YMMqq_YMMqq 5562 +VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 5563 +VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 5564 +VPMULHRSW_XMMdq_XMMdq_MEMdq 5565 +VPMULHRSW_XMMdq_XMMdq_XMMdq 5566 +VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 5567 +VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 5568 +VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 5569 +VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 5570 +VPMULHRSW_YMMqq_YMMqq_MEMqq 5571 +VPMULHRSW_YMMqq_YMMqq_YMMqq 5572 +VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 5573 +VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 5574 +VPMULHUW_XMMdq_XMMdq_MEMdq 5575 +VPMULHUW_XMMdq_XMMdq_XMMdq 5576 +VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5577 +VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5578 +VPMULHUW_YMMqq_YMMqq_MEMqq 5579 +VPMULHUW_YMMqq_YMMqq_YMMqq 5580 +VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5581 +VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5582 +VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5583 +VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5584 +VPMULHW_XMMdq_XMMdq_MEMdq 5585 +VPMULHW_XMMdq_XMMdq_XMMdq 5586 +VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5587 +VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5588 +VPMULHW_YMMqq_YMMqq_MEMqq 5589 +VPMULHW_YMMqq_YMMqq_YMMqq 5590 +VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5591 +VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5592 +VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5593 +VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5594 +VPMULLD_XMMdq_XMMdq_MEMdq 5595 +VPMULLD_XMMdq_XMMdq_XMMdq 5596 +VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5597 +VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5598 +VPMULLD_YMMqq_YMMqq_MEMqq 5599 +VPMULLD_YMMqq_YMMqq_YMMqq 5600 +VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5601 +VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5602 +VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5603 +VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5604 +VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5605 +VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5606 +VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5607 +VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5608 +VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5609 +VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5610 +VPMULLW_XMMdq_XMMdq_MEMdq 5611 +VPMULLW_XMMdq_XMMdq_XMMdq 5612 +VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5613 +VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5614 +VPMULLW_YMMqq_YMMqq_MEMqq 5615 +VPMULLW_YMMqq_YMMqq_YMMqq 5616 +VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5617 +VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5618 +VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5619 +VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5620 +VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 5621 +VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 5622 +VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 5623 +VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 5624 +VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 5625 +VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 5626 +VPMULUDQ_XMMdq_XMMdq_MEMdq 5627 +VPMULUDQ_XMMdq_XMMdq_XMMdq 5628 +VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 5629 +VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 5630 +VPMULUDQ_YMMqq_YMMqq_MEMqq 5631 +VPMULUDQ_YMMqq_YMMqq_YMMqq 5632 +VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 5633 +VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 5634 +VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 5635 +VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 5636 +VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 5637 +VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 5638 +VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 5639 +VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 5640 +VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 5641 +VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 5642 +VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 5643 +VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 5644 +VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 5645 +VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 5646 +VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 5647 +VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 5648 +VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 5649 +VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 5650 +VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 5651 +VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 5652 +VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 5653 +VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 5654 +VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 5655 +VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 5656 +VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 5657 +VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 5658 +VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 5659 +VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 5660 +VPOR_XMMdq_XMMdq_MEMdq 5661 +VPOR_XMMdq_XMMdq_XMMdq 5662 +VPOR_YMMqq_YMMqq_MEMqq 5663 +VPOR_YMMqq_YMMqq_YMMqq 5664 +VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5665 +VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5666 +VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5667 +VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5668 +VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5669 +VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5670 +VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5671 +VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5672 +VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5673 +VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5674 +VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5675 +VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5676 +VPPERM_XMMdq_XMMdq_MEMdq_XMMdq 5677 +VPPERM_XMMdq_XMMdq_XMMdq_MEMdq 5678 +VPPERM_XMMdq_XMMdq_XMMdq_XMMdq 5679 +VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 5680 +VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 5681 +VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 5682 +VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 5683 +VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 5684 +VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 5685 +VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 5686 +VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 5687 +VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 5688 +VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 5689 +VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 5690 +VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 5691 +VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5692 +VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5693 +VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5694 +VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5695 +VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5696 +VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5697 +VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5698 +VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5699 +VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5700 +VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5701 +VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5702 +VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5703 +VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 5704 +VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 5705 +VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 5706 +VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 5707 +VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 5708 +VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 5709 +VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 5710 +VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 5711 +VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 5712 +VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 5713 +VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 5714 +VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 5715 +VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5716 +VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5717 +VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5718 +VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5719 +VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5720 +VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5721 +VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5722 +VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5723 +VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5724 +VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5725 +VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5726 +VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5727 +VPROTB_XMMdq_MEMdq_IMMb 5728 +VPROTB_XMMdq_MEMdq_XMMdq 5729 +VPROTB_XMMdq_XMMdq_IMMb 5730 +VPROTB_XMMdq_XMMdq_MEMdq 5731 +VPROTB_XMMdq_XMMdq_XMMdq 5732 +VPROTD_XMMdq_MEMdq_IMMb 5733 +VPROTD_XMMdq_MEMdq_XMMdq 5734 +VPROTD_XMMdq_XMMdq_IMMb 5735 +VPROTD_XMMdq_XMMdq_MEMdq 5736 +VPROTD_XMMdq_XMMdq_XMMdq 5737 +VPROTQ_XMMdq_MEMdq_IMMb 5738 +VPROTQ_XMMdq_MEMdq_XMMdq 5739 +VPROTQ_XMMdq_XMMdq_IMMb 5740 +VPROTQ_XMMdq_XMMdq_MEMdq 5741 +VPROTQ_XMMdq_XMMdq_XMMdq 5742 +VPROTW_XMMdq_MEMdq_IMMb 5743 +VPROTW_XMMdq_MEMdq_XMMdq 5744 +VPROTW_XMMdq_XMMdq_IMMb 5745 +VPROTW_XMMdq_XMMdq_MEMdq 5746 +VPROTW_XMMdq_XMMdq_XMMdq 5747 +VPSADBW_XMMdq_XMMdq_MEMdq 5748 +VPSADBW_XMMdq_XMMdq_XMMdq 5749 +VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 5750 +VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 5751 +VPSADBW_YMMqq_YMMqq_MEMqq 5752 +VPSADBW_YMMqq_YMMqq_YMMqq 5753 +VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 5754 +VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 5755 +VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 5756 +VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 5757 +VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 5758 +VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 5759 +VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 5760 +VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 5761 +VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 5762 +VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 5763 +VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 5764 +VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 5765 +VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 5766 +VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 5767 +VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 5768 +VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 5769 +VPSHAB_XMMdq_MEMdq_XMMdq 5770 +VPSHAB_XMMdq_XMMdq_MEMdq 5771 +VPSHAB_XMMdq_XMMdq_XMMdq 5772 +VPSHAD_XMMdq_MEMdq_XMMdq 5773 +VPSHAD_XMMdq_XMMdq_MEMdq 5774 +VPSHAD_XMMdq_XMMdq_XMMdq 5775 +VPSHAQ_XMMdq_MEMdq_XMMdq 5776 +VPSHAQ_XMMdq_XMMdq_MEMdq 5777 +VPSHAQ_XMMdq_XMMdq_XMMdq 5778 +VPSHAW_XMMdq_MEMdq_XMMdq 5779 +VPSHAW_XMMdq_XMMdq_MEMdq 5780 +VPSHAW_XMMdq_XMMdq_XMMdq 5781 +VPSHLB_XMMdq_MEMdq_XMMdq 5782 +VPSHLB_XMMdq_XMMdq_MEMdq 5783 +VPSHLB_XMMdq_XMMdq_XMMdq 5784 +VPSHLD_XMMdq_MEMdq_XMMdq 5785 +VPSHLD_XMMdq_XMMdq_MEMdq 5786 +VPSHLD_XMMdq_XMMdq_XMMdq 5787 +VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 5788 +VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 5789 +VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 5790 +VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 5791 +VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 5792 +VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 5793 +VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 5794 +VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 5795 +VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 5796 +VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 5797 +VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 5798 +VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 5799 +VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5800 +VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5801 +VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5802 +VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5803 +VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5804 +VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5805 +VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5806 +VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5807 +VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5808 +VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5809 +VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5810 +VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5811 +VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5812 +VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5813 +VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5814 +VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5815 +VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5816 +VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5817 +VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 5818 +VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 5819 +VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 5820 +VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 5821 +VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 5822 +VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 5823 +VPSHLQ_XMMdq_MEMdq_XMMdq 5824 +VPSHLQ_XMMdq_XMMdq_MEMdq 5825 +VPSHLQ_XMMdq_XMMdq_XMMdq 5826 +VPSHLW_XMMdq_MEMdq_XMMdq 5827 +VPSHLW_XMMdq_XMMdq_MEMdq 5828 +VPSHLW_XMMdq_XMMdq_XMMdq 5829 +VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 5830 +VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 5831 +VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 5832 +VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 5833 +VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 5834 +VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 5835 +VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 5836 +VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 5837 +VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 5838 +VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 5839 +VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 5840 +VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 5841 +VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5842 +VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5843 +VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5844 +VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5845 +VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5846 +VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5847 +VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5848 +VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5849 +VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5850 +VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5851 +VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5852 +VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5853 +VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5854 +VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5855 +VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5856 +VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5857 +VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5858 +VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5859 +VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 5860 +VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 5861 +VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 5862 +VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 5863 +VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 5864 +VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 5865 +VPSHUFB_XMMdq_XMMdq_MEMdq 5866 +VPSHUFB_XMMdq_XMMdq_XMMdq 5867 +VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 5868 +VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 5869 +VPSHUFB_YMMqq_YMMqq_MEMqq 5870 +VPSHUFB_YMMqq_YMMqq_YMMqq 5871 +VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 5872 +VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 5873 +VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 5874 +VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 5875 +VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 5876 +VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 5877 +VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 5878 +VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 5879 +VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 5880 +VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 5881 +VPSHUFD_XMMdq_MEMdq_IMMb 5882 +VPSHUFD_XMMdq_XMMdq_IMMb 5883 +VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 5884 +VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 5885 +VPSHUFD_YMMqq_MEMqq_IMMb 5886 +VPSHUFD_YMMqq_YMMqq_IMMb 5887 +VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 5888 +VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 5889 +VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 5890 +VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 5891 +VPSHUFHW_XMMdq_MEMdq_IMMb 5892 +VPSHUFHW_XMMdq_XMMdq_IMMb 5893 +VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 5894 +VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 5895 +VPSHUFHW_YMMqq_MEMqq_IMMb 5896 +VPSHUFHW_YMMqq_YMMqq_IMMb 5897 +VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 5898 +VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 5899 +VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 5900 +VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 5901 +VPSHUFLW_XMMdq_MEMdq_IMMb 5902 +VPSHUFLW_XMMdq_XMMdq_IMMb 5903 +VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 5904 +VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 5905 +VPSHUFLW_YMMqq_MEMqq_IMMb 5906 +VPSHUFLW_YMMqq_YMMqq_IMMb 5907 +VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 5908 +VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 5909 +VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 5910 +VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 5911 +VPSIGNB_XMMdq_XMMdq_MEMdq 5912 +VPSIGNB_XMMdq_XMMdq_XMMdq 5913 +VPSIGNB_YMMqq_YMMqq_MEMqq 5914 +VPSIGNB_YMMqq_YMMqq_YMMqq 5915 +VPSIGND_XMMdq_XMMdq_MEMdq 5916 +VPSIGND_XMMdq_XMMdq_XMMdq 5917 +VPSIGND_YMMqq_YMMqq_MEMqq 5918 +VPSIGND_YMMqq_YMMqq_YMMqq 5919 +VPSIGNW_XMMdq_XMMdq_MEMdq 5920 +VPSIGNW_XMMdq_XMMdq_XMMdq 5921 +VPSIGNW_YMMqq_YMMqq_MEMqq 5922 +VPSIGNW_YMMqq_YMMqq_YMMqq 5923 +VPSLLD_XMMdq_XMMdq_IMMb 5924 +VPSLLD_XMMdq_XMMdq_MEMdq 5925 +VPSLLD_XMMdq_XMMdq_XMMdq 5926 +VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 5927 +VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 5928 +VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5929 +VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5930 +VPSLLD_YMMqq_YMMqq_IMMb 5931 +VPSLLD_YMMqq_YMMqq_MEMdq 5932 +VPSLLD_YMMqq_YMMqq_XMMq 5933 +VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 5934 +VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 5935 +VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5936 +VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 5937 +VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 5938 +VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 5939 +VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5940 +VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 5941 +VPSLLDQ_XMMdq_XMMdq_IMMb 5942 +VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 5943 +VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 5944 +VPSLLDQ_YMMqq_YMMqq_IMMb 5945 +VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 5946 +VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 5947 +VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 5948 +VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 5949 +VPSLLQ_XMMdq_XMMdq_IMMb 5950 +VPSLLQ_XMMdq_XMMdq_MEMdq 5951 +VPSLLQ_XMMdq_XMMdq_XMMdq 5952 +VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 5953 +VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 5954 +VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5955 +VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5956 +VPSLLQ_YMMqq_YMMqq_IMMb 5957 +VPSLLQ_YMMqq_YMMqq_MEMdq 5958 +VPSLLQ_YMMqq_YMMqq_XMMq 5959 +VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 5960 +VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 5961 +VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5962 +VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 5963 +VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 5964 +VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 5965 +VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5966 +VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 5967 +VPSLLVD_XMMdq_XMMdq_MEMdq 5968 +VPSLLVD_XMMdq_XMMdq_XMMdq 5969 +VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 5970 +VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 5971 +VPSLLVD_YMMqq_YMMqq_MEMqq 5972 +VPSLLVD_YMMqq_YMMqq_YMMqq 5973 +VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 5974 +VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 5975 +VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 5976 +VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 5977 +VPSLLVQ_XMMdq_XMMdq_MEMdq 5978 +VPSLLVQ_XMMdq_XMMdq_XMMdq 5979 +VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 5980 +VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 5981 +VPSLLVQ_YMMqq_YMMqq_MEMqq 5982 +VPSLLVQ_YMMqq_YMMqq_YMMqq 5983 +VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 5984 +VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 5985 +VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 5986 +VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 5987 +VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5988 +VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 5989 +VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 5990 +VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 5991 +VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 5992 +VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 5993 +VPSLLW_XMMdq_XMMdq_IMMb 5994 +VPSLLW_XMMdq_XMMdq_MEMdq 5995 +VPSLLW_XMMdq_XMMdq_XMMdq 5996 +VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 5997 +VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 5998 +VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 5999 +VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6000 +VPSLLW_YMMqq_YMMqq_IMMb 6001 +VPSLLW_YMMqq_YMMqq_MEMdq 6002 +VPSLLW_YMMqq_YMMqq_XMMq 6003 +VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 6004 +VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 6005 +VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6006 +VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 6007 +VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 6008 +VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 6009 +VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6010 +VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 6011 +VPSRAD_XMMdq_XMMdq_IMMb 6012 +VPSRAD_XMMdq_XMMdq_MEMdq 6013 +VPSRAD_XMMdq_XMMdq_XMMdq 6014 +VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 6015 +VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 6016 +VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6017 +VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6018 +VPSRAD_YMMqq_YMMqq_IMMb 6019 +VPSRAD_YMMqq_YMMqq_MEMdq 6020 +VPSRAD_YMMqq_YMMqq_XMMq 6021 +VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 6022 +VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 6023 +VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6024 +VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 6025 +VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 6026 +VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 6027 +VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6028 +VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 6029 +VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 6030 +VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 6031 +VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6032 +VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6033 +VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 6034 +VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 6035 +VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6036 +VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 6037 +VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 6038 +VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 6039 +VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6040 +VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 6041 +VPSRAVD_XMMdq_XMMdq_MEMdq 6042 +VPSRAVD_XMMdq_XMMdq_XMMdq 6043 +VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6044 +VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6045 +VPSRAVD_YMMqq_YMMqq_MEMqq 6046 +VPSRAVD_YMMqq_YMMqq_YMMqq 6047 +VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6048 +VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6049 +VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6050 +VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6051 +VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6052 +VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6053 +VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6054 +VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6055 +VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6056 +VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6057 +VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6058 +VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6059 +VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6060 +VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 6061 +VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6062 +VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 6063 +VPSRAW_XMMdq_XMMdq_IMMb 6064 +VPSRAW_XMMdq_XMMdq_MEMdq 6065 +VPSRAW_XMMdq_XMMdq_XMMdq 6066 +VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 6067 +VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 6068 +VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6069 +VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6070 +VPSRAW_YMMqq_YMMqq_IMMb 6071 +VPSRAW_YMMqq_YMMqq_MEMdq 6072 +VPSRAW_YMMqq_YMMqq_XMMq 6073 +VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 6074 +VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 6075 +VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6076 +VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 6077 +VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 6078 +VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 6079 +VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6080 +VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 6081 +VPSRLD_XMMdq_XMMdq_IMMb 6082 +VPSRLD_XMMdq_XMMdq_MEMdq 6083 +VPSRLD_XMMdq_XMMdq_XMMdq 6084 +VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 6085 +VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 6086 +VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6087 +VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6088 +VPSRLD_YMMqq_YMMqq_IMMb 6089 +VPSRLD_YMMqq_YMMqq_MEMdq 6090 +VPSRLD_YMMqq_YMMqq_XMMq 6091 +VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 6092 +VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 6093 +VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6094 +VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 6095 +VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 6096 +VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 6097 +VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6098 +VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 6099 +VPSRLDQ_XMMdq_XMMdq_IMMb 6100 +VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 6101 +VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 6102 +VPSRLDQ_YMMqq_YMMqq_IMMb 6103 +VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 6104 +VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 6105 +VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 6106 +VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 6107 +VPSRLQ_XMMdq_XMMdq_IMMb 6108 +VPSRLQ_XMMdq_XMMdq_MEMdq 6109 +VPSRLQ_XMMdq_XMMdq_XMMdq 6110 +VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 6111 +VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 6112 +VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6113 +VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6114 +VPSRLQ_YMMqq_YMMqq_IMMb 6115 +VPSRLQ_YMMqq_YMMqq_MEMdq 6116 +VPSRLQ_YMMqq_YMMqq_XMMq 6117 +VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 6118 +VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 6119 +VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6120 +VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 6121 +VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 6122 +VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 6123 +VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6124 +VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 6125 +VPSRLVD_XMMdq_XMMdq_MEMdq 6126 +VPSRLVD_XMMdq_XMMdq_XMMdq 6127 +VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6128 +VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6129 +VPSRLVD_YMMqq_YMMqq_MEMqq 6130 +VPSRLVD_YMMqq_YMMqq_YMMqq 6131 +VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6132 +VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6133 +VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6134 +VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6135 +VPSRLVQ_XMMdq_XMMdq_MEMdq 6136 +VPSRLVQ_XMMdq_XMMdq_XMMdq 6137 +VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6138 +VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6139 +VPSRLVQ_YMMqq_YMMqq_MEMqq 6140 +VPSRLVQ_YMMqq_YMMqq_YMMqq 6141 +VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6142 +VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6143 +VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6144 +VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6145 +VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6146 +VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6147 +VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6148 +VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 6149 +VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6150 +VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 6151 +VPSRLW_XMMdq_XMMdq_IMMb 6152 +VPSRLW_XMMdq_XMMdq_MEMdq 6153 +VPSRLW_XMMdq_XMMdq_XMMdq 6154 +VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 6155 +VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 6156 +VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6157 +VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6158 +VPSRLW_YMMqq_YMMqq_IMMb 6159 +VPSRLW_YMMqq_YMMqq_MEMdq 6160 +VPSRLW_YMMqq_YMMqq_XMMq 6161 +VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 6162 +VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 6163 +VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6164 +VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 6165 +VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 6166 +VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 6167 +VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6168 +VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 6169 +VPSUBB_XMMdq_XMMdq_MEMdq 6170 +VPSUBB_XMMdq_XMMdq_XMMdq 6171 +VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 6172 +VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 6173 +VPSUBB_YMMqq_YMMqq_MEMqq 6174 +VPSUBB_YMMqq_YMMqq_YMMqq 6175 +VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 6176 +VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 6177 +VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 6178 +VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 6179 +VPSUBD_XMMdq_XMMdq_MEMdq 6180 +VPSUBD_XMMdq_XMMdq_XMMdq 6181 +VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6182 +VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6183 +VPSUBD_YMMqq_YMMqq_MEMqq 6184 +VPSUBD_YMMqq_YMMqq_YMMqq 6185 +VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6186 +VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6187 +VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6188 +VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6189 +VPSUBQ_XMMdq_XMMdq_MEMdq 6190 +VPSUBQ_XMMdq_XMMdq_XMMdq 6191 +VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6192 +VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6193 +VPSUBQ_YMMqq_YMMqq_MEMqq 6194 +VPSUBQ_YMMqq_YMMqq_YMMqq 6195 +VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6196 +VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6197 +VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6198 +VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6199 +VPSUBSB_XMMdq_XMMdq_MEMdq 6200 +VPSUBSB_XMMdq_XMMdq_XMMdq 6201 +VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 6202 +VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 6203 +VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 6204 +VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 6205 +VPSUBSB_YMMqq_YMMqq_MEMqq 6206 +VPSUBSB_YMMqq_YMMqq_YMMqq 6207 +VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 6208 +VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 6209 +VPSUBSW_XMMdq_XMMdq_MEMdq 6210 +VPSUBSW_XMMdq_XMMdq_XMMdq 6211 +VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 6212 +VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 6213 +VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 6214 +VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 6215 +VPSUBSW_YMMqq_YMMqq_MEMqq 6216 +VPSUBSW_YMMqq_YMMqq_YMMqq 6217 +VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 6218 +VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 6219 +VPSUBUSB_XMMdq_XMMdq_MEMdq 6220 +VPSUBUSB_XMMdq_XMMdq_XMMdq 6221 +VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 6222 +VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 6223 +VPSUBUSB_YMMqq_YMMqq_MEMqq 6224 +VPSUBUSB_YMMqq_YMMqq_YMMqq 6225 +VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 6226 +VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 6227 +VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 6228 +VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 6229 +VPSUBUSW_XMMdq_XMMdq_MEMdq 6230 +VPSUBUSW_XMMdq_XMMdq_XMMdq 6231 +VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6232 +VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6233 +VPSUBUSW_YMMqq_YMMqq_MEMqq 6234 +VPSUBUSW_YMMqq_YMMqq_YMMqq 6235 +VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6236 +VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 6237 +VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6238 +VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 6239 +VPSUBW_XMMdq_XMMdq_MEMdq 6240 +VPSUBW_XMMdq_XMMdq_XMMdq 6241 +VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6242 +VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6243 +VPSUBW_YMMqq_YMMqq_MEMqq 6244 +VPSUBW_YMMqq_YMMqq_YMMqq 6245 +VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6246 +VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 6247 +VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6248 +VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 6249 +VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 6250 +VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 6251 +VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 6252 +VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 6253 +VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 6254 +VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 6255 +VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 6256 +VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 6257 +VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 6258 +VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 6259 +VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 6260 +VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 6261 +VPTEST_XMMdq_MEMdq 6262 +VPTEST_XMMdq_XMMdq 6263 +VPTEST_YMMqq_MEMqq 6264 +VPTEST_YMMqq_YMMqq 6265 +VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 6266 +VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 6267 +VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 6268 +VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 6269 +VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 6270 +VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 6271 +VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 6272 +VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 6273 +VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 6274 +VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 6275 +VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 6276 +VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 6277 +VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 6278 +VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 6279 +VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 6280 +VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 6281 +VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 6282 +VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 6283 +VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 6284 +VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 6285 +VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 6286 +VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 6287 +VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 6288 +VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 6289 +VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 6290 +VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 6291 +VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 6292 +VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 6293 +VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 6294 +VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 6295 +VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 6296 +VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 6297 +VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 6298 +VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 6299 +VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 6300 +VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 6301 +VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 6302 +VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 6303 +VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 6304 +VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 6305 +VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 6306 +VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 6307 +VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 6308 +VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 6309 +VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 6310 +VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 6311 +VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 6312 +VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 6313 +VPUNPCKHBW_XMMdq_XMMdq_MEMdq 6314 +VPUNPCKHBW_XMMdq_XMMdq_XMMdq 6315 +VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 6316 +VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 6317 +VPUNPCKHBW_YMMqq_YMMqq_MEMqq 6318 +VPUNPCKHBW_YMMqq_YMMqq_YMMqq 6319 +VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 6320 +VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 6321 +VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 6322 +VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 6323 +VPUNPCKHDQ_XMMdq_XMMdq_MEMdq 6324 +VPUNPCKHDQ_XMMdq_XMMdq_XMMdq 6325 +VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6326 +VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6327 +VPUNPCKHDQ_YMMqq_YMMqq_MEMqq 6328 +VPUNPCKHDQ_YMMqq_YMMqq_YMMqq 6329 +VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6330 +VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6331 +VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6332 +VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6333 +VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq 6334 +VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq 6335 +VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6336 +VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6337 +VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq 6338 +VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq 6339 +VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6340 +VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6341 +VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6342 +VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6343 +VPUNPCKHWD_XMMdq_XMMdq_MEMdq 6344 +VPUNPCKHWD_XMMdq_XMMdq_XMMdq 6345 +VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6346 +VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6347 +VPUNPCKHWD_YMMqq_YMMqq_MEMqq 6348 +VPUNPCKHWD_YMMqq_YMMqq_YMMqq 6349 +VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6350 +VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 6351 +VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6352 +VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 6353 +VPUNPCKLBW_XMMdq_XMMdq_MEMdq 6354 +VPUNPCKLBW_XMMdq_XMMdq_XMMdq 6355 +VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 6356 +VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 6357 +VPUNPCKLBW_YMMqq_YMMqq_MEMqq 6358 +VPUNPCKLBW_YMMqq_YMMqq_YMMqq 6359 +VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 6360 +VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 6361 +VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 6362 +VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 6363 +VPUNPCKLDQ_XMMdq_XMMdq_MEMdq 6364 +VPUNPCKLDQ_XMMdq_XMMdq_XMMdq 6365 +VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6366 +VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6367 +VPUNPCKLDQ_YMMqq_YMMqq_MEMqq 6368 +VPUNPCKLDQ_YMMqq_YMMqq_YMMqq 6369 +VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6370 +VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6371 +VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6372 +VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6373 +VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq 6374 +VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq 6375 +VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6376 +VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6377 +VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq 6378 +VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq 6379 +VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6380 +VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6381 +VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6382 +VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6383 +VPUNPCKLWD_XMMdq_XMMdq_MEMdq 6384 +VPUNPCKLWD_XMMdq_XMMdq_XMMdq 6385 +VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 6386 +VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 6387 +VPUNPCKLWD_YMMqq_YMMqq_MEMqq 6388 +VPUNPCKLWD_YMMqq_YMMqq_YMMqq 6389 +VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 6390 +VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 6391 +VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 6392 +VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 6393 +VPXOR_XMMdq_XMMdq_MEMdq 6394 +VPXOR_XMMdq_XMMdq_XMMdq 6395 +VPXOR_YMMqq_YMMqq_MEMqq 6396 +VPXOR_YMMqq_YMMqq_YMMqq 6397 +VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6398 +VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6399 +VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6400 +VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6401 +VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6402 +VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6403 +VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6404 +VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6405 +VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6406 +VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6407 +VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6408 +VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6409 +VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 6410 +VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 6411 +VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 6412 +VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 6413 +VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 6414 +VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 6415 +VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 6416 +VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 6417 +VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 6418 +VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 6419 +VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 6420 +VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 6421 +VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 6422 +VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 6423 +VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 6424 +VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 6425 +VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 6426 +VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 6427 +VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 6428 +VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 6429 +VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 6430 +VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 6431 +VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 6432 +VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 6433 +VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 6434 +VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 6435 +VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 6436 +VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 6437 +VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6438 +VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6439 +VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6440 +VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6441 +VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 6442 +VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 6443 +VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 6444 +VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 6445 +VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 6446 +VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 6447 +VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 6448 +VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 6449 +VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 6450 +VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 6451 +VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 6452 +VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 6453 +VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 6454 +VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 6455 +VRCPPS_XMMdq_MEMdq 6456 +VRCPPS_XMMdq_XMMdq 6457 +VRCPPS_YMMqq_MEMqq 6458 +VRCPPS_YMMqq_YMMqq 6459 +VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6460 +VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6461 +VRCPSS_XMMdq_XMMdq_MEMd 6462 +VRCPSS_XMMdq_XMMdq_XMMd 6463 +VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 6464 +VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 6465 +VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 6466 +VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 6467 +VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 6468 +VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 6469 +VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 6470 +VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 6471 +VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 6472 +VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 6473 +VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 6474 +VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 6475 +VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 6476 +VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 6477 +VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 6478 +VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 6479 +VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 6480 +VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 6481 +VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 6482 +VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 6483 +VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 6484 +VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 6485 +VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 6486 +VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 6487 +VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 6488 +VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 6489 +VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 6490 +VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 6491 +VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 6492 +VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 6493 +VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 6494 +VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 6495 +VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 6496 +VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 6497 +VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 6498 +VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 6499 +VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 6500 +VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 6501 +VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 6502 +VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 6503 +VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 6504 +VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 6505 +VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 6506 +VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 6507 +VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 6508 +VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 6509 +VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 6510 +VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 6511 +VROUNDPD_XMMdq_MEMdq_IMMb 6512 +VROUNDPD_XMMdq_XMMdq_IMMb 6513 +VROUNDPD_YMMqq_MEMqq_IMMb 6514 +VROUNDPD_YMMqq_YMMqq_IMMb 6515 +VROUNDPS_XMMdq_MEMdq_IMMb 6516 +VROUNDPS_XMMdq_XMMdq_IMMb 6517 +VROUNDPS_YMMqq_MEMqq_IMMb 6518 +VROUNDPS_YMMqq_YMMqq_IMMb 6519 +VROUNDSD_XMMdq_XMMdq_MEMq_IMMb 6520 +VROUNDSD_XMMdq_XMMdq_XMMq_IMMb 6521 +VROUNDSS_XMMdq_XMMdq_MEMd_IMMb 6522 +VROUNDSS_XMMdq_XMMdq_XMMd_IMMb 6523 +VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 6524 +VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 6525 +VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 6526 +VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 6527 +VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 6528 +VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 6529 +VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 6530 +VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 6531 +VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 6532 +VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 6533 +VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 6534 +VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 6535 +VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6536 +VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6537 +VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6538 +VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6539 +VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER 6540 +VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER 6541 +VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER 6542 +VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER 6543 +VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER 6544 +VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER 6545 +VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER 6546 +VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER 6547 +VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 6548 +VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 6549 +VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 6550 +VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 6551 +VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 6552 +VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 6553 +VRSQRTPS_XMMdq_MEMdq 6554 +VRSQRTPS_XMMdq_XMMdq 6555 +VRSQRTPS_YMMqq_MEMqq 6556 +VRSQRTPS_YMMqq_YMMqq 6557 +VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6558 +VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6559 +VRSQRTSS_XMMdq_XMMdq_MEMd 6560 +VRSQRTSS_XMMdq_XMMdq_XMMd 6561 +VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6562 +VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6563 +VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 6564 +VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 6565 +VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 6566 +VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 6567 +VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6568 +VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6569 +VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 6570 +VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 6571 +VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 6572 +VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 6573 +VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6574 +VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6575 +VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 6576 +VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 6577 +VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 6578 +VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 6579 +VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6580 +VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6581 +VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6582 +VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6583 +VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6584 +VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6585 +VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 6586 +VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 6587 +VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 6588 +VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 6589 +VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 6590 +VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 6591 +VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 6592 +VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 6593 +VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 6594 +VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 6595 +VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 6596 +VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 6597 +VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 6598 +VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 6599 +VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 6600 +VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 6601 +VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 6602 +VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 6603 +VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 6604 +VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 6605 +VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 6606 +VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 6607 +VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 6608 +VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 6609 +VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 6610 +VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 6611 +VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 6612 +VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 6613 +VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 6614 +VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 6615 +VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 6616 +VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 6617 +VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 6618 +VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 6619 +VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 6620 +VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 6621 +VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb 6622 +VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb 6623 +VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 6624 +VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 6625 +VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 6626 +VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 6627 +VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb 6628 +VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb 6629 +VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 6630 +VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 6631 +VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb 6632 +VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb 6633 +VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 6634 +VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 6635 +VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 6636 +VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 6637 +VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb 6638 +VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb 6639 +VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 6640 +VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 6641 +VSQRTPD_XMMdq_MEMdq 6642 +VSQRTPD_XMMdq_XMMdq 6643 +VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 6644 +VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 6645 +VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 6646 +VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 6647 +VSQRTPD_YMMqq_MEMqq 6648 +VSQRTPD_YMMqq_YMMqq 6649 +VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 6650 +VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 6651 +VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 6652 +VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 6653 +VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 6654 +VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 6655 +VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 6656 +VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 6657 +VSQRTPS_XMMdq_MEMdq 6658 +VSQRTPS_XMMdq_XMMdq 6659 +VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 6660 +VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 6661 +VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 6662 +VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 6663 +VSQRTPS_YMMqq_MEMqq 6664 +VSQRTPS_YMMqq_YMMqq 6665 +VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 6666 +VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 6667 +VSQRTSD_XMMdq_XMMdq_MEMq 6668 +VSQRTSD_XMMdq_XMMdq_XMMq 6669 +VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6670 +VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6671 +VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6672 +VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6673 +VSQRTSS_XMMdq_XMMdq_MEMd 6674 +VSQRTSS_XMMdq_XMMdq_XMMd 6675 +VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6676 +VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6677 +VSTMXCSR_MEMd 6678 +VSUBPD_XMMdq_XMMdq_MEMdq 6679 +VSUBPD_XMMdq_XMMdq_XMMdq 6680 +VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6681 +VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6682 +VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 6683 +VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 6684 +VSUBPD_YMMqq_YMMqq_MEMqq 6685 +VSUBPD_YMMqq_YMMqq_YMMqq 6686 +VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 6687 +VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 6688 +VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6689 +VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6690 +VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 6691 +VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 6692 +VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 6693 +VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 6694 +VSUBPS_XMMdq_XMMdq_MEMdq 6695 +VSUBPS_XMMdq_XMMdq_XMMdq 6696 +VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6697 +VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6698 +VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 6699 +VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 6700 +VSUBPS_YMMqq_YMMqq_MEMqq 6701 +VSUBPS_YMMqq_YMMqq_YMMqq 6702 +VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 6703 +VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 6704 +VSUBSD_XMMdq_XMMdq_MEMq 6705 +VSUBSD_XMMdq_XMMdq_XMMq 6706 +VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6707 +VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6708 +VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 6709 +VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 6710 +VSUBSS_XMMdq_XMMdq_MEMd 6711 +VSUBSS_XMMdq_XMMdq_XMMd 6712 +VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6713 +VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6714 +VTESTPD_XMMdq_MEMdq 6715 +VTESTPD_XMMdq_XMMdq 6716 +VTESTPD_YMMqq_MEMqq 6717 +VTESTPD_YMMqq_YMMqq 6718 +VTESTPS_XMMdq_MEMdq 6719 +VTESTPS_XMMdq_XMMdq 6720 +VTESTPS_YMMqq_MEMqq 6721 +VTESTPS_YMMqq_YMMqq 6722 +VUCOMISD_XMMdq_MEMq 6723 +VUCOMISD_XMMdq_XMMq 6724 +VUCOMISD_XMMf64_MEMf64_AVX512 6725 +VUCOMISD_XMMf64_XMMf64_AVX512 6726 +VUCOMISH_XMMf16_MEMf16_AVX512 6727 +VUCOMISH_XMMf16_XMMf16_AVX512 6728 +VUCOMISS_XMMdq_MEMd 6729 +VUCOMISS_XMMdq_XMMd 6730 +VUCOMISS_XMMf32_MEMf32_AVX512 6731 +VUCOMISS_XMMf32_XMMf32_AVX512 6732 +VUNPCKHPD_XMMdq_XMMdq_MEMdq 6733 +VUNPCKHPD_XMMdq_XMMdq_XMMdq 6734 +VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6735 +VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6736 +VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 6737 +VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 6738 +VUNPCKHPD_YMMqq_YMMqq_MEMqq 6739 +VUNPCKHPD_YMMqq_YMMqq_YMMqq 6740 +VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 6741 +VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 6742 +VUNPCKHPS_XMMdq_XMMdq_MEMdq 6743 +VUNPCKHPS_XMMdq_XMMdq_XMMdq 6744 +VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6745 +VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6746 +VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 6747 +VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 6748 +VUNPCKHPS_YMMqq_YMMqq_MEMqq 6749 +VUNPCKHPS_YMMqq_YMMqq_YMMqq 6750 +VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 6751 +VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 6752 +VUNPCKLPD_XMMdq_XMMdq_MEMdq 6753 +VUNPCKLPD_XMMdq_XMMdq_XMMdq 6754 +VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 6755 +VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 6756 +VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 6757 +VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 6758 +VUNPCKLPD_YMMqq_YMMqq_MEMqq 6759 +VUNPCKLPD_YMMqq_YMMqq_YMMqq 6760 +VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 6761 +VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 6762 +VUNPCKLPS_XMMdq_XMMdq_MEMdq 6763 +VUNPCKLPS_XMMdq_XMMdq_XMMdq 6764 +VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 6765 +VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 6766 +VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 6767 +VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 6768 +VUNPCKLPS_YMMqq_YMMqq_MEMqq 6769 +VUNPCKLPS_YMMqq_YMMqq_YMMqq 6770 +VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 6771 +VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 6772 +VXORPD_XMMdq_XMMdq_MEMdq 6773 +VXORPD_XMMdq_XMMdq_XMMdq 6774 +VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 6775 +VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 6776 +VXORPD_YMMqq_YMMqq_MEMqq 6777 +VXORPD_YMMqq_YMMqq_YMMqq 6778 +VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 6779 +VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 6780 +VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 6781 +VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 6782 +VXORPS_XMMdq_XMMdq_MEMdq 6783 +VXORPS_XMMdq_XMMdq_XMMdq 6784 +VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 6785 +VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 6786 +VXORPS_YMMqq_YMMqq_MEMqq 6787 +VXORPS_YMMqq_YMMqq_YMMqq 6788 +VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 6789 +VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 6790 +VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 6791 +VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 6792 +VZEROALL 6793 +VZEROUPPER 6794 +WBINVD 6795 +WBNOINVD 6796 +WRFSBASE_GPRy 6797 +WRGSBASE_GPRy 6798 +WRMSR 6799 +WRPKRU 6800 +WRSSD_MEMu32_GPR32u32 6801 +WRSSQ_MEMu64_GPR64u64 6802 +WRUSSD_MEMu32_GPR32u32 6803 +WRUSSQ_MEMu64_GPR64u64 6804 +XABORT_IMMb 6805 +XADD_GPR8_GPR8 6806 +XADD_GPRv_GPRv 6807 +XADD_MEMb_GPR8 6808 +XADD_MEMv_GPRv 6809 +XADD_LOCK_MEMb_GPR8 6810 +XADD_LOCK_MEMv_GPRv 6811 +XBEGIN_RELBRz 6812 +XCHG_GPR8_GPR8 6813 +XCHG_GPRv_GPRv 6814 +XCHG_GPRv_OrAX 6815 +XCHG_MEMb_GPR8 6816 +XCHG_MEMv_GPRv 6817 +XEND 6818 +XGETBV 6819 +XLAT 6820 +XOR_AL_IMMb 6821 +XOR_GPR8_GPR8_30 6822 +XOR_GPR8_GPR8_32 6823 +XOR_GPR8_IMMb_80r6 6824 +XOR_GPR8_IMMb_82r6 6825 +XOR_GPR8_MEMb 6826 +XOR_GPRv_GPRv_31 6827 +XOR_GPRv_GPRv_33 6828 +XOR_GPRv_IMMb 6829 +XOR_GPRv_IMMz 6830 +XOR_GPRv_MEMv 6831 +XOR_MEMb_GPR8 6832 +XOR_MEMb_IMMb_80r6 6833 +XOR_MEMb_IMMb_82r6 6834 +XOR_MEMv_GPRv 6835 +XOR_MEMv_IMMb 6836 +XOR_MEMv_IMMz 6837 +XOR_OrAX_IMMz 6838 +XORPD_XMMxuq_MEMxuq 6839 +XORPD_XMMxuq_XMMxuq 6840 +XORPS_XMMxud_MEMxud 6841 +XORPS_XMMxud_XMMxud 6842 +XOR_LOCK_MEMb_GPR8 6843 +XOR_LOCK_MEMb_IMMb_80r6 6844 +XOR_LOCK_MEMb_IMMb_82r6 6845 +XOR_LOCK_MEMv_GPRv 6846 +XOR_LOCK_MEMv_IMMb 6847 +XOR_LOCK_MEMv_IMMz 6848 +XRESLDTRK 6849 +XRSTOR_MEMmxsave 6850 +XRSTOR64_MEMmxsave 6851 +XRSTORS_MEMmxsave 6852 +XRSTORS64_MEMmxsave 6853 +XSAVE_MEMmxsave 6854 +XSAVE64_MEMmxsave 6855 +XSAVEC_MEMmxsave 6856 +XSAVEC64_MEMmxsave 6857 +XSAVEOPT_MEMmxsave 6858 +XSAVEOPT64_MEMmxsave 6859 +XSAVES_MEMmxsave 6860 +XSAVES64_MEMmxsave 6861 +XSETBV 6862 +XSTORE 6863 +XSUSLDTRK 6864 +XTEST 6865 diff --git a/CodeVirtualizer/build/obj/xed-iform-map-init.c b/CodeVirtualizer/build/obj/xed-iform-map-init.c new file mode 100644 index 0000000..d5ceacf --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iform-map-init.c @@ -0,0 +1,6893 @@ +/// @file xed-iform-map-init.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-iform-map.h" + +const xed_iform_info_t xed_iform_db[XED_IFORM_LAST] = { +/* INVALID */ { (xed_uint16_t) XED_ICLASS_INVALID, (xed_uint8_t) XED_CATEGORY_INVALID, (xed_uint8_t)XED_EXTENSION_INVALID, (xed_uint16_t) XED_ISA_SET_INVALID, (xed_uint16_t) 0 }, +/* AAA */ { (xed_uint16_t) XED_ICLASS_AAA, (xed_uint8_t) XED_CATEGORY_DECIMAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AAD_IMMb */ { (xed_uint16_t) XED_ICLASS_AAD, (xed_uint8_t) XED_CATEGORY_DECIMAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AAM_IMMb */ { (xed_uint16_t) XED_ICLASS_AAM, (xed_uint8_t) XED_CATEGORY_DECIMAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AAS */ { (xed_uint16_t) XED_ICLASS_AAS, (xed_uint8_t) XED_CATEGORY_DECIMAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPR8_GPR8_10 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPR8_GPR8_12 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPR8_IMMb_80r2 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPR8_IMMb_82r2 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPRv_GPRv_11 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPRv_GPRv_13 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_MEMb_IMMb_80r2 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_MEMb_IMMb_82r2 */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADC_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_ADC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADCX_GPR32d_GPR32d */ { (xed_uint16_t) XED_ICLASS_ADCX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADCX_GPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_ADCX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADCX_GPR64q_GPR64q */ { (xed_uint16_t) XED_ICLASS_ADCX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADCX_GPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_ADCX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADC_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_ADC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 6 }, +/* ADC_LOCK_MEMb_IMMb_80r2 */ { (xed_uint16_t) XED_ICLASS_ADC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 6 }, +/* ADC_LOCK_MEMb_IMMb_82r2 */ { (xed_uint16_t) XED_ICLASS_ADC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 6 }, +/* ADC_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_ADC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 6 }, +/* ADC_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_ADC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 6 }, +/* ADC_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_ADC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 6 }, +/* ADD_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPR8_GPR8_00 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPR8_GPR8_02 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPR8_IMMb_80r0 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPR8_IMMb_82r0 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPRv_GPRv_01 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPRv_GPRv_03 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_MEMb_IMMb_80r0 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_MEMb_IMMb_82r0 */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADD_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_ADD, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ADDPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_ADDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ADDPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_ADDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ADDPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_ADDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ADDPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_ADDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ADDSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_ADDSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ADDSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_ADDSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ADDSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_ADDSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ADDSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_ADDSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ADDSUBPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_ADDSUBPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* ADDSUBPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_ADDSUBPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* ADDSUBPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_ADDSUBPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* ADDSUBPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_ADDSUBPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* ADD_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_ADD_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 2 }, +/* ADD_LOCK_MEMb_IMMb_80r0 */ { (xed_uint16_t) XED_ICLASS_ADD_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 2 }, +/* ADD_LOCK_MEMb_IMMb_82r0 */ { (xed_uint16_t) XED_ICLASS_ADD_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 2 }, +/* ADD_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_ADD_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 2 }, +/* ADD_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_ADD_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 2 }, +/* ADD_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_ADD_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 2 }, +/* ADOX_GPR32d_GPR32d */ { (xed_uint16_t) XED_ICLASS_ADOX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADOX_GPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_ADOX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADOX_GPR64q_GPR64q */ { (xed_uint16_t) XED_ICLASS_ADOX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* ADOX_GPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_ADOX, (xed_uint8_t) XED_CATEGORY_ADOX_ADCX, (xed_uint8_t)XED_EXTENSION_ADOX_ADCX, (xed_uint16_t) XED_ISA_SET_ADOX_ADCX, (xed_uint16_t) 0 }, +/* AESDEC_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_AESDEC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESDEC_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_AESDEC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESDEC128KL_XMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESDEC128KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* AESDEC256KL_XMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESDEC256KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* AESDECLAST_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_AESDECLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESDECLAST_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_AESDECLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESDECWIDE128KL_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESDECWIDE128KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER_WIDE, (xed_uint8_t)XED_EXTENSION_KEYLOCKER_WIDE, (xed_uint16_t)XED_ISA_SET_KEYLOCKER_WIDE, (xed_uint16_t) 0 }, +/* AESDECWIDE256KL_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESDECWIDE256KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER_WIDE, (xed_uint8_t)XED_EXTENSION_KEYLOCKER_WIDE, (xed_uint16_t)XED_ISA_SET_KEYLOCKER_WIDE, (xed_uint16_t) 0 }, +/* AESENC_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_AESENC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESENC_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_AESENC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESENC128KL_XMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESENC128KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* AESENC256KL_XMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESENC256KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* AESENCLAST_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_AESENCLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESENCLAST_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_AESENCLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESENCWIDE128KL_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESENCWIDE128KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER_WIDE, (xed_uint8_t)XED_EXTENSION_KEYLOCKER_WIDE, (xed_uint16_t)XED_ISA_SET_KEYLOCKER_WIDE, (xed_uint16_t) 0 }, +/* AESENCWIDE256KL_MEMu8 */ { (xed_uint16_t) XED_ICLASS_AESENCWIDE256KL, (xed_uint8_t) XED_CATEGORY_KEYLOCKER_WIDE, (xed_uint8_t)XED_EXTENSION_KEYLOCKER_WIDE, (xed_uint16_t)XED_ISA_SET_KEYLOCKER_WIDE, (xed_uint16_t) 0 }, +/* AESIMC_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_AESIMC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESIMC_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_AESIMC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESKEYGENASSIST_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_AESKEYGENASSIST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AESKEYGENASSIST_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_AESKEYGENASSIST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t) XED_EXTENSION_AES, (xed_uint16_t) XED_ISA_SET_AES, (xed_uint16_t) 0 }, +/* AND_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPR8_GPR8_20 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPR8_GPR8_22 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPR8_IMMb_80r4 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPR8_IMMb_82r4 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPRv_GPRv_21 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPRv_GPRv_23 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_MEMb_IMMb_80r4 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_MEMb_IMMb_82r4 */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* AND_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_AND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ANDN_VGPR32d_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_ANDN, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* ANDN_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_ANDN, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* ANDN_VGPR64q_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_ANDN, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* ANDN_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_ANDN, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* ANDNPD_XMMxuq_MEMxuq */ { (xed_uint16_t) XED_ICLASS_ANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ANDNPD_XMMxuq_XMMxuq */ { (xed_uint16_t) XED_ICLASS_ANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ANDNPS_XMMxud_MEMxud */ { (xed_uint16_t) XED_ICLASS_ANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ANDNPS_XMMxud_XMMxud */ { (xed_uint16_t) XED_ICLASS_ANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ANDPD_XMMxuq_MEMxuq */ { (xed_uint16_t) XED_ICLASS_ANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ANDPD_XMMxuq_XMMxuq */ { (xed_uint16_t) XED_ICLASS_ANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ANDPS_XMMxud_MEMxud */ { (xed_uint16_t) XED_ICLASS_ANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ANDPS_XMMxud_XMMxud */ { (xed_uint16_t) XED_ICLASS_ANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* AND_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_AND_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 10 }, +/* AND_LOCK_MEMb_IMMb_80r4 */ { (xed_uint16_t) XED_ICLASS_AND_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 10 }, +/* AND_LOCK_MEMb_IMMb_82r4 */ { (xed_uint16_t) XED_ICLASS_AND_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 10 }, +/* AND_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_AND_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 10 }, +/* AND_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_AND_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 10 }, +/* AND_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_AND_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 10 }, +/* ARPL_GPR16_GPR16 */ { (xed_uint16_t) XED_ICLASS_ARPL, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* ARPL_MEMw_GPR16 */ { (xed_uint16_t) XED_ICLASS_ARPL, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* BEXTR_VGPR32d_MEMd_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BEXTR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BEXTR_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BEXTR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BEXTR_VGPR64q_MEMq_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BEXTR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BEXTR_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BEXTR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BEXTR_XOP_VGPR32d_MEMd_IMMd */ { (xed_uint16_t) XED_ICLASS_BEXTR_XOP, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 132 }, +/* BEXTR_XOP_VGPR32d_VGPR32d_IMMd */ { (xed_uint16_t) XED_ICLASS_BEXTR_XOP, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 132 }, +/* BEXTR_XOP_VGPRyy_MEMy_IMMd */ { (xed_uint16_t) XED_ICLASS_BEXTR_XOP, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 132 }, +/* BEXTR_XOP_VGPRyy_VGPRyy_IMMd */ { (xed_uint16_t) XED_ICLASS_BEXTR_XOP, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 132 }, +/* BLCFILL_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLCFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCFILL_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLCFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCFILL_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLCFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCFILL_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLCFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCI_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLCI, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCI_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLCI, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCI_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLCI, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCI_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLCI, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCIC_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLCIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCIC_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLCIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCIC_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLCIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCIC_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLCIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCMSK_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLCMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCMSK_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLCMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCMSK_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLCMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCMSK_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLCMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCS_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLCS, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCS_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLCS, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCS_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLCS, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLCS_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLCS, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLENDPD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_BLENDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDPD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_BLENDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDPS_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_BLENDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDPS_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_BLENDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDVPD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_BLENDVPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDVPD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_BLENDVPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDVPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_BLENDVPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLENDVPS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_BLENDVPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* BLSFILL_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLSFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSFILL_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLSFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSFILL_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLSFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSFILL_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLSFILL, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSI_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLSI, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSI_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLSI, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSI_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_BLSI, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSI_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BLSI, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSIC_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLSIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSIC_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLSIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSIC_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_BLSIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSIC_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_BLSIC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* BLSMSK_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLSMSK, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSMSK_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLSMSK, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSMSK_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_BLSMSK, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSMSK_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BLSMSK, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSR_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_BLSR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSR_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BLSR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSR_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_BLSR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BLSR_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BLSR, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* BNDCL_BND_AGEN */ { (xed_uint16_t) XED_ICLASS_BNDCL, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCL_BND_GPR32 */ { (xed_uint16_t) XED_ICLASS_BNDCL, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCL_BND_GPR64 */ { (xed_uint16_t) XED_ICLASS_BNDCL, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCN_BND_AGEN */ { (xed_uint16_t) XED_ICLASS_BNDCN, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCN_BND_GPR32 */ { (xed_uint16_t) XED_ICLASS_BNDCN, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCN_BND_GPR64 */ { (xed_uint16_t) XED_ICLASS_BNDCN, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCU_BND_AGEN */ { (xed_uint16_t) XED_ICLASS_BNDCU, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCU_BND_GPR32 */ { (xed_uint16_t) XED_ICLASS_BNDCU, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDCU_BND_GPR64 */ { (xed_uint16_t) XED_ICLASS_BNDCU, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDLDX_BND_MEMbnd32 */ { (xed_uint16_t) XED_ICLASS_BNDLDX, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDLDX_BND_MEMbnd64 */ { (xed_uint16_t) XED_ICLASS_BNDLDX, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDMK_BND_AGEN */ { (xed_uint16_t) XED_ICLASS_BNDMK, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDMOV_BND_BND */ { (xed_uint16_t) XED_ICLASS_BNDMOV, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDMOV_BND_MEMdq */ { (xed_uint16_t) XED_ICLASS_BNDMOV, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDMOV_BND_MEMq */ { (xed_uint16_t) XED_ICLASS_BNDMOV, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDMOV_MEMdq_BND */ { (xed_uint16_t) XED_ICLASS_BNDMOV, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDMOV_MEMq_BND */ { (xed_uint16_t) XED_ICLASS_BNDMOV, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDSTX_MEMbnd32_BND */ { (xed_uint16_t) XED_ICLASS_BNDSTX, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BNDSTX_MEMbnd64_BND */ { (xed_uint16_t) XED_ICLASS_BNDSTX, (xed_uint8_t) XED_CATEGORY_MPX, (xed_uint8_t) XED_EXTENSION_MPX, (xed_uint16_t) XED_ISA_SET_MPX, (xed_uint16_t) 0 }, +/* BOUND_GPRv_MEMa16 */ { (xed_uint16_t) XED_ICLASS_BOUND, (xed_uint8_t) XED_CATEGORY_INTERRUPT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* BOUND_GPRv_MEMa32 */ { (xed_uint16_t) XED_ICLASS_BOUND, (xed_uint8_t) XED_CATEGORY_INTERRUPT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* BSF_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_BSF, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BSF_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_BSF, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BSR_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_BSR, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BSR_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_BSR, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BSWAP_GPRv */ { (xed_uint16_t) XED_ICLASS_BSWAP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* BT_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_BT, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BT_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_BT, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BT_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BT, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BT_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BT, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTC_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTC, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTC_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTC, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTC_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTC, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTC_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTC, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTC_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTC_LOCK, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 32 }, +/* BTC_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTC_LOCK, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 32 }, +/* BTR_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTR, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTR, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTR_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTR, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTR, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTR_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTR_LOCK, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 30 }, +/* BTR_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTR_LOCK, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 30 }, +/* BTS_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTS, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTS_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTS, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTS_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTS, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTS_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTS, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* BTS_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_BTS_LOCK, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 28 }, +/* BTS_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_BTS_LOCK, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 28 }, +/* BZHI_VGPR32d_MEMd_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BZHI, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* BZHI_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_BZHI, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* BZHI_VGPR64q_MEMq_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BZHI, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* BZHI_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_BZHI, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* CALL_FAR_MEMp2 */ { (xed_uint16_t) XED_ICLASS_CALL_FAR, (xed_uint8_t) XED_CATEGORY_CALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 50 }, +/* CALL_FAR_PTRp_IMMw */ { (xed_uint16_t) XED_ICLASS_CALL_FAR, (xed_uint8_t) XED_CATEGORY_CALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 50 }, +/* CALL_NEAR_GPRv */ { (xed_uint16_t) XED_ICLASS_CALL_NEAR, (xed_uint8_t) XED_CATEGORY_CALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 24 }, +/* CALL_NEAR_MEMv */ { (xed_uint16_t) XED_ICLASS_CALL_NEAR, (xed_uint8_t) XED_CATEGORY_CALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 24 }, +/* CALL_NEAR_RELBRd */ { (xed_uint16_t) XED_ICLASS_CALL_NEAR, (xed_uint8_t) XED_CATEGORY_CALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 24 }, +/* CALL_NEAR_RELBRz */ { (xed_uint16_t) XED_ICLASS_CALL_NEAR, (xed_uint8_t) XED_CATEGORY_CALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 24 }, +/* CBW */ { (xed_uint16_t) XED_ICLASS_CBW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CDQ */ { (xed_uint16_t) XED_ICLASS_CDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* CDQE */ { (xed_uint16_t) XED_ICLASS_CDQE, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* CLAC */ { (xed_uint16_t) XED_ICLASS_CLAC, (xed_uint8_t) XED_CATEGORY_SMAP, (xed_uint8_t) XED_EXTENSION_SMAP, (xed_uint16_t) XED_ISA_SET_SMAP, (xed_uint16_t) 0 }, +/* CLC */ { (xed_uint16_t) XED_ICLASS_CLC, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CLD */ { (xed_uint16_t) XED_ICLASS_CLD, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CLDEMOTE_MEMu8 */ { (xed_uint16_t) XED_ICLASS_CLDEMOTE, (xed_uint8_t) XED_CATEGORY_CLDEMOTE, (xed_uint8_t)XED_EXTENSION_CLDEMOTE, (xed_uint16_t) XED_ISA_SET_CLDEMOTE, (xed_uint16_t) 0 }, +/* CLFLUSH_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_CLFLUSH, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_CLFSH, (xed_uint16_t) XED_ISA_SET_CLFSH, (xed_uint16_t) 0 }, +/* CLFLUSHOPT_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_CLFLUSHOPT, (xed_uint8_t) XED_CATEGORY_CLFLUSHOPT, (xed_uint8_t)XED_EXTENSION_CLFLUSHOPT, (xed_uint16_t) XED_ISA_SET_CLFLUSHOPT, (xed_uint16_t) 0 }, +/* CLGI */ { (xed_uint16_t) XED_ICLASS_CLGI, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* CLI */ { (xed_uint16_t) XED_ICLASS_CLI, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CLRSSBSY_MEMu64 */ { (xed_uint16_t) XED_ICLASS_CLRSSBSY, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* CLTS */ { (xed_uint16_t) XED_ICLASS_CLTS, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* CLUI */ { (xed_uint16_t) XED_ICLASS_CLUI, (xed_uint8_t) XED_CATEGORY_UINTR, (xed_uint8_t) XED_EXTENSION_UINTR, (xed_uint16_t) XED_ISA_SET_UINTR, (xed_uint16_t) 0 }, +/* CLWB_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_CLWB, (xed_uint8_t) XED_CATEGORY_CLWB, (xed_uint8_t) XED_EXTENSION_CLWB, (xed_uint16_t) XED_ISA_SET_CLWB, (xed_uint16_t) 0 }, +/* CLZERO */ { (xed_uint16_t) XED_ICLASS_CLZERO, (xed_uint8_t) XED_CATEGORY_CLZERO, (xed_uint8_t)XED_EXTENSION_CLZERO, (xed_uint16_t) XED_ISA_SET_CLZERO, (xed_uint16_t) 0 }, +/* CMC */ { (xed_uint16_t) XED_ICLASS_CMC, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMOVB_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVB, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVB_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVB, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVBE_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVBE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVBE_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVBE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVL_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVL, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVL_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVL, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVLE_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVLE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVLE_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVLE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNB_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNB, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNB_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNB, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNBE_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNBE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNBE_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNBE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNL_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNL, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNL_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNL, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNLE_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNLE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNLE_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNLE, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNO_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNO, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNO_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNO, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNP_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNP, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNP_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNP, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNS_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNS, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNS_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNS, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNZ_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVNZ, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVNZ_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVNZ, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVO_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVO, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVO_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVO, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVP_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVP, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVP_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVP, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVS_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVS, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVS_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVS, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVZ_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMOVZ, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMOVZ_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMOVZ, (xed_uint8_t) XED_CATEGORY_CMOV, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_CMOV, (xed_uint16_t) 0 }, +/* CMP_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPR8_GPR8_38 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPR8_GPR8_3A */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPR8_IMMb_80r7 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPR8_IMMb_82r7 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPRv_GPRv_39 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPRv_GPRv_3B */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_MEMb_IMMb_80r7 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_MEMb_IMMb_82r7 */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMP_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_CMP, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMPPD_XMMpd_MEMpd_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CMPPD_XMMpd_XMMpd_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CMPPS_XMMps_MEMps_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CMPPS_XMMps_XMMps_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CMPSB */ { (xed_uint16_t) XED_ICLASS_CMPSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMPSD */ { (xed_uint16_t) XED_ICLASS_CMPSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* CMPSD_XMM_XMMsd_MEMsd_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPSD_XMM, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 64 }, +/* CMPSD_XMM_XMMsd_XMMsd_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPSD_XMM, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 64 }, +/* CMPSQ */ { (xed_uint16_t) XED_ICLASS_CMPSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* CMPSS_XMMss_MEMss_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CMPSS_XMMss_XMMss_IMMb */ { (xed_uint16_t) XED_ICLASS_CMPSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CMPSW */ { (xed_uint16_t) XED_ICLASS_CMPSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CMPXCHG_GPR8_GPR8 */ { (xed_uint16_t) XED_ICLASS_CMPXCHG, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* CMPXCHG_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMPXCHG, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* CMPXCHG_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_CMPXCHG, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* CMPXCHG_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMPXCHG, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* CMPXCHG16B_MEMdq */ { (xed_uint16_t) XED_ICLASS_CMPXCHG16B, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_CMPXCHG16B, (xed_uint16_t) 0 }, +/* CMPXCHG16B_LOCK_MEMdq */ { (xed_uint16_t) XED_ICLASS_CMPXCHG16B_LOCK, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_CMPXCHG16B, (xed_uint16_t) 36 }, +/* CMPXCHG8B_MEMq */ { (xed_uint16_t) XED_ICLASS_CMPXCHG8B, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PENTIUMREAL, (xed_uint16_t) 0 }, +/* CMPXCHG8B_LOCK_MEMq */ { (xed_uint16_t) XED_ICLASS_CMPXCHG8B_LOCK, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PENTIUMREAL, (xed_uint16_t) 34 }, +/* CMPXCHG_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_CMPXCHG_LOCK, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 100 }, +/* CMPXCHG_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_CMPXCHG_LOCK, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 100 }, +/* COMISD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_COMISD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* COMISD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_COMISD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* COMISS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_COMISS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* COMISS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_COMISS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CPUID */ { (xed_uint16_t) XED_ICLASS_CPUID, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* CQO */ { (xed_uint16_t) XED_ICLASS_CQO, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* CRC32_GPRyy_GPR8b */ { (xed_uint16_t) XED_ICLASS_CRC32, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* CRC32_GPRyy_GPRv */ { (xed_uint16_t) XED_ICLASS_CRC32, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* CRC32_GPRyy_MEMb */ { (xed_uint16_t) XED_ICLASS_CRC32, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* CRC32_GPRyy_MEMv */ { (xed_uint16_t) XED_ICLASS_CRC32, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* CVTDQ2PD_XMMpd_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTDQ2PD_XMMpd_XMMq */ { (xed_uint16_t) XED_ICLASS_CVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTDQ2PS_XMMps_MEMdq */ { (xed_uint16_t) XED_ICLASS_CVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTDQ2PS_XMMps_XMMdq */ { (xed_uint16_t) XED_ICLASS_CVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPD2DQ_XMMdq_MEMpd */ { (xed_uint16_t) XED_ICLASS_CVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPD2DQ_XMMdq_XMMpd */ { (xed_uint16_t) XED_ICLASS_CVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPD2PI_MMXq_MEMpd */ { (xed_uint16_t) XED_ICLASS_CVTPD2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPD2PI_MMXq_XMMpd */ { (xed_uint16_t) XED_ICLASS_CVTPD2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPD2PS_XMMps_MEMpd */ { (xed_uint16_t) XED_ICLASS_CVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPD2PS_XMMps_XMMpd */ { (xed_uint16_t) XED_ICLASS_CVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPI2PD_XMMpd_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTPI2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPI2PD_XMMpd_MMXq */ { (xed_uint16_t) XED_ICLASS_CVTPI2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPI2PS_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTPI2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTPI2PS_XMMq_MMXq */ { (xed_uint16_t) XED_ICLASS_CVTPI2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTPS2DQ_XMMdq_MEMps */ { (xed_uint16_t) XED_ICLASS_CVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPS2DQ_XMMdq_XMMps */ { (xed_uint16_t) XED_ICLASS_CVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPS2PD_XMMpd_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPS2PD_XMMpd_XMMq */ { (xed_uint16_t) XED_ICLASS_CVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTPS2PI_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTPS2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTPS2PI_MMXq_XMMq */ { (xed_uint16_t) XED_ICLASS_CVTPS2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSD2SI_GPR32d_MEMsd */ { (xed_uint16_t) XED_ICLASS_CVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSD2SI_GPR32d_XMMsd */ { (xed_uint16_t) XED_ICLASS_CVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSD2SI_GPR64q_MEMsd */ { (xed_uint16_t) XED_ICLASS_CVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSD2SI_GPR64q_XMMsd */ { (xed_uint16_t) XED_ICLASS_CVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSD2SS_XMMss_MEMsd */ { (xed_uint16_t) XED_ICLASS_CVTSD2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSD2SS_XMMss_XMMsd */ { (xed_uint16_t) XED_ICLASS_CVTSD2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSI2SD_XMMsd_GPR32d */ { (xed_uint16_t) XED_ICLASS_CVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSI2SD_XMMsd_GPR64q */ { (xed_uint16_t) XED_ICLASS_CVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSI2SD_XMMsd_MEMd */ { (xed_uint16_t) XED_ICLASS_CVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSI2SD_XMMsd_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSI2SS_XMMss_GPR32d */ { (xed_uint16_t) XED_ICLASS_CVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSI2SS_XMMss_GPR64q */ { (xed_uint16_t) XED_ICLASS_CVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSI2SS_XMMss_MEMd */ { (xed_uint16_t) XED_ICLASS_CVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSI2SS_XMMss_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSS2SD_XMMsd_MEMss */ { (xed_uint16_t) XED_ICLASS_CVTSS2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSS2SD_XMMsd_XMMss */ { (xed_uint16_t) XED_ICLASS_CVTSS2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTSS2SI_GPR32d_MEMss */ { (xed_uint16_t) XED_ICLASS_CVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSS2SI_GPR32d_XMMss */ { (xed_uint16_t) XED_ICLASS_CVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSS2SI_GPR64q_MEMss */ { (xed_uint16_t) XED_ICLASS_CVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTSS2SI_GPR64q_XMMss */ { (xed_uint16_t) XED_ICLASS_CVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTTPD2DQ_XMMdq_MEMpd */ { (xed_uint16_t) XED_ICLASS_CVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTPD2DQ_XMMdq_XMMpd */ { (xed_uint16_t) XED_ICLASS_CVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTPD2PI_MMXq_MEMpd */ { (xed_uint16_t) XED_ICLASS_CVTTPD2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTPD2PI_MMXq_XMMpd */ { (xed_uint16_t) XED_ICLASS_CVTTPD2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTPS2DQ_XMMdq_MEMps */ { (xed_uint16_t) XED_ICLASS_CVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTPS2DQ_XMMdq_XMMps */ { (xed_uint16_t) XED_ICLASS_CVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTPS2PI_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_CVTTPS2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTTPS2PI_MMXq_XMMq */ { (xed_uint16_t) XED_ICLASS_CVTTPS2PI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTTSD2SI_GPR32d_MEMsd */ { (xed_uint16_t) XED_ICLASS_CVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTSD2SI_GPR32d_XMMsd */ { (xed_uint16_t) XED_ICLASS_CVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTSD2SI_GPR64q_MEMsd */ { (xed_uint16_t) XED_ICLASS_CVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTSD2SI_GPR64q_XMMsd */ { (xed_uint16_t) XED_ICLASS_CVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* CVTTSS2SI_GPR32d_MEMss */ { (xed_uint16_t) XED_ICLASS_CVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTTSS2SI_GPR32d_XMMss */ { (xed_uint16_t) XED_ICLASS_CVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTTSS2SI_GPR64q_MEMss */ { (xed_uint16_t) XED_ICLASS_CVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CVTTSS2SI_GPR64q_XMMss */ { (xed_uint16_t) XED_ICLASS_CVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* CWD */ { (xed_uint16_t) XED_ICLASS_CWD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* CWDE */ { (xed_uint16_t) XED_ICLASS_CWDE, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* DAA */ { (xed_uint16_t) XED_ICLASS_DAA, (xed_uint8_t) XED_CATEGORY_DECIMAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DAS */ { (xed_uint16_t) XED_ICLASS_DAS, (xed_uint8_t) XED_CATEGORY_DECIMAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DEC_GPR8 */ { (xed_uint16_t) XED_ICLASS_DEC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DEC_GPRv_48 */ { (xed_uint16_t) XED_ICLASS_DEC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DEC_GPRv_FFr1 */ { (xed_uint16_t) XED_ICLASS_DEC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DEC_MEMb */ { (xed_uint16_t) XED_ICLASS_DEC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DEC_MEMv */ { (xed_uint16_t) XED_ICLASS_DEC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DEC_LOCK_MEMb */ { (xed_uint16_t) XED_ICLASS_DEC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 22 }, +/* DEC_LOCK_MEMv */ { (xed_uint16_t) XED_ICLASS_DEC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 22 }, +/* DIV_GPR8 */ { (xed_uint16_t) XED_ICLASS_DIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DIV_GPRv */ { (xed_uint16_t) XED_ICLASS_DIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DIV_MEMb */ { (xed_uint16_t) XED_ICLASS_DIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DIV_MEMv */ { (xed_uint16_t) XED_ICLASS_DIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* DIVPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_DIVPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* DIVPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_DIVPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* DIVPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_DIVPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* DIVPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_DIVPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* DIVSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_DIVSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* DIVSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_DIVSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* DIVSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_DIVSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* DIVSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_DIVSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* DPPD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_DPPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* DPPD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_DPPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* DPPS_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_DPPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* DPPS_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_DPPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* EMMS */ { (xed_uint16_t) XED_ICLASS_EMMS, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* ENCLS */ { (xed_uint16_t) XED_ICLASS_ENCLS, (xed_uint8_t) XED_CATEGORY_SGX, (xed_uint8_t) XED_EXTENSION_SGX, (xed_uint16_t) XED_ISA_SET_SGX, (xed_uint16_t) 0 }, +/* ENCLU */ { (xed_uint16_t) XED_ICLASS_ENCLU, (xed_uint8_t) XED_CATEGORY_SGX, (xed_uint8_t) XED_EXTENSION_SGX, (xed_uint16_t) XED_ISA_SET_SGX, (xed_uint16_t) 0 }, +/* ENCLV */ { (xed_uint16_t) XED_ICLASS_ENCLV, (xed_uint8_t) XED_CATEGORY_SGX, (xed_uint8_t)XED_EXTENSION_SGX_ENCLV, (xed_uint16_t) XED_ISA_SET_SGX_ENCLV, (xed_uint16_t) 0 }, +/* ENCODEKEY128_GPR32u8_GPR32u8 */ { (xed_uint16_t) XED_ICLASS_ENCODEKEY128, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* ENCODEKEY256_GPR32u8_GPR32u8 */ { (xed_uint16_t) XED_ICLASS_ENCODEKEY256, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* ENDBR32 */ { (xed_uint16_t) XED_ICLASS_ENDBR32, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* ENDBR64 */ { (xed_uint16_t) XED_ICLASS_ENDBR64, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* ENQCMD_GPRa_MEMu32 */ { (xed_uint16_t) XED_ICLASS_ENQCMD, (xed_uint8_t) XED_CATEGORY_ENQCMD, (xed_uint8_t)XED_EXTENSION_ENQCMD, (xed_uint16_t) XED_ISA_SET_ENQCMD, (xed_uint16_t) 0 }, +/* ENQCMDS_GPRa_MEMu32 */ { (xed_uint16_t) XED_ICLASS_ENQCMDS, (xed_uint8_t) XED_CATEGORY_ENQCMD, (xed_uint8_t)XED_EXTENSION_ENQCMD, (xed_uint16_t) XED_ISA_SET_ENQCMD, (xed_uint16_t) 0 }, +/* ENTER_IMMw_IMMb */ { (xed_uint16_t) XED_ICLASS_ENTER, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* EXTRACTPS_GPR32d_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_EXTRACTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* EXTRACTPS_MEMd_XMMps_IMMb */ { (xed_uint16_t) XED_ICLASS_EXTRACTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* EXTRQ_XMMq_IMMb_IMMb */ { (xed_uint16_t) XED_ICLASS_EXTRQ, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_SSE4A, (xed_uint16_t) XED_ISA_SET_SSE4A, (xed_uint16_t) 0 }, +/* EXTRQ_XMMq_XMMdq */ { (xed_uint16_t) XED_ICLASS_EXTRQ, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_SSE4A, (xed_uint16_t) XED_ISA_SET_SSE4A, (xed_uint16_t) 0 }, +/* F2XM1 */ { (xed_uint16_t) XED_ICLASS_F2XM1, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FABS */ { (xed_uint16_t) XED_ICLASS_FABS, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FADD_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FADD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FADD_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FADD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FADD_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FADD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FADD_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FADD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FADDP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FADDP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FBLD_ST0_MEMmem80dec */ { (xed_uint16_t) XED_ICLASS_FBLD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FBSTP_MEMmem80dec_ST0 */ { (xed_uint16_t) XED_ICLASS_FBSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCHS */ { (xed_uint16_t) XED_ICLASS_FCHS, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCMOVB_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVB, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVBE_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVBE, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVE_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVE, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVNB_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVNB, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVNBE_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVNBE, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVNE_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVNE, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVNU_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVNU, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCMOVU_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCMOVU, (xed_uint8_t) XED_CATEGORY_FCMOV, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_FCMOV, (xed_uint16_t) 0 }, +/* FCOM_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FCOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOM_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FCOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOM_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOM_ST0_X87_DCD0 */ { (xed_uint16_t) XED_ICLASS_FCOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOMI_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCOMI, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* FCOMIP_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCOMIP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* FCOMP_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FCOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOMP_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FCOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOMP_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FCOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOMP_ST0_X87_DCD1 */ { (xed_uint16_t) XED_ICLASS_FCOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOMP_ST0_X87_DED0 */ { (xed_uint16_t) XED_ICLASS_FCOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOMPP */ { (xed_uint16_t) XED_ICLASS_FCOMPP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FCOS */ { (xed_uint16_t) XED_ICLASS_FCOS, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDECSTP */ { (xed_uint16_t) XED_ICLASS_FDECSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDISI8087_NOP */ { (xed_uint16_t) XED_ICLASS_FDISI8087_NOP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIV_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FDIV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIV_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FDIV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIV_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FDIV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIV_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FDIV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIVP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FDIVP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIVR_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FDIVR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIVR_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FDIVR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIVR_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FDIVR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIVR_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FDIVR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FDIVRP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FDIVRP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FEMMS */ { (xed_uint16_t) XED_ICLASS_FEMMS, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* FENI8087_NOP */ { (xed_uint16_t) XED_ICLASS_FENI8087_NOP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FFREE_X87 */ { (xed_uint16_t) XED_ICLASS_FFREE, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FFREEP_X87 */ { (xed_uint16_t) XED_ICLASS_FFREEP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIADD_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FIADD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIADD_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FIADD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FICOM_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FICOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FICOM_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FICOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FICOMP_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FICOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FICOMP_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FICOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIDIV_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FIDIV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIDIV_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FIDIV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIDIVR_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FIDIVR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIDIVR_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FIDIVR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FILD_ST0_MEMm64int */ { (xed_uint16_t) XED_ICLASS_FILD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FILD_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FILD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FILD_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FILD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIMUL_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FIMUL, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIMUL_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FIMUL, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FINCSTP */ { (xed_uint16_t) XED_ICLASS_FINCSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIST_MEMmem16int_ST0 */ { (xed_uint16_t) XED_ICLASS_FIST, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FIST_MEMmem32int_ST0 */ { (xed_uint16_t) XED_ICLASS_FIST, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISTP_MEMm64int_ST0 */ { (xed_uint16_t) XED_ICLASS_FISTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISTP_MEMmem16int_ST0 */ { (xed_uint16_t) XED_ICLASS_FISTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISTP_MEMmem32int_ST0 */ { (xed_uint16_t) XED_ICLASS_FISTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISTTP_MEMm64int_ST0 */ { (xed_uint16_t) XED_ICLASS_FISTTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3X87, (xed_uint16_t) 0 }, +/* FISTTP_MEMmem16int_ST0 */ { (xed_uint16_t) XED_ICLASS_FISTTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3X87, (xed_uint16_t) 0 }, +/* FISTTP_MEMmem32int_ST0 */ { (xed_uint16_t) XED_ICLASS_FISTTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* FISUB_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FISUB, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISUB_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FISUB, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISUBR_ST0_MEMmem16int */ { (xed_uint16_t) XED_ICLASS_FISUBR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FISUBR_ST0_MEMmem32int */ { (xed_uint16_t) XED_ICLASS_FISUBR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLD_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FLD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLD_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FLD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLD_ST0_MEMmem80real */ { (xed_uint16_t) XED_ICLASS_FLD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLD_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FLD, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLD1 */ { (xed_uint16_t) XED_ICLASS_FLD1, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDCW_MEMmem16 */ { (xed_uint16_t) XED_ICLASS_FLDCW, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDENV_MEMmem14 */ { (xed_uint16_t) XED_ICLASS_FLDENV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDENV_MEMmem28 */ { (xed_uint16_t) XED_ICLASS_FLDENV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDL2E */ { (xed_uint16_t) XED_ICLASS_FLDL2E, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDL2T */ { (xed_uint16_t) XED_ICLASS_FLDL2T, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDLG2 */ { (xed_uint16_t) XED_ICLASS_FLDLG2, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDLN2 */ { (xed_uint16_t) XED_ICLASS_FLDLN2, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDPI */ { (xed_uint16_t) XED_ICLASS_FLDPI, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FLDZ */ { (xed_uint16_t) XED_ICLASS_FLDZ, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FMUL_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FMUL, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FMUL_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FMUL, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FMUL_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FMUL, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FMUL_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FMUL, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FMULP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FMULP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNCLEX */ { (xed_uint16_t) XED_ICLASS_FNCLEX, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNINIT */ { (xed_uint16_t) XED_ICLASS_FNINIT, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNOP */ { (xed_uint16_t) XED_ICLASS_FNOP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSAVE_MEMmem108 */ { (xed_uint16_t) XED_ICLASS_FNSAVE, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSAVE_MEMmem94 */ { (xed_uint16_t) XED_ICLASS_FNSAVE, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSTCW_MEMmem16 */ { (xed_uint16_t) XED_ICLASS_FNSTCW, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSTENV_MEMmem14 */ { (xed_uint16_t) XED_ICLASS_FNSTENV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSTENV_MEMmem28 */ { (xed_uint16_t) XED_ICLASS_FNSTENV, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSTSW_AX */ { (xed_uint16_t) XED_ICLASS_FNSTSW, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FNSTSW_MEMmem16 */ { (xed_uint16_t) XED_ICLASS_FNSTSW, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FPATAN */ { (xed_uint16_t) XED_ICLASS_FPATAN, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FPREM */ { (xed_uint16_t) XED_ICLASS_FPREM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FPREM1 */ { (xed_uint16_t) XED_ICLASS_FPREM1, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FPTAN */ { (xed_uint16_t) XED_ICLASS_FPTAN, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FRNDINT */ { (xed_uint16_t) XED_ICLASS_FRNDINT, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FRSTOR_MEMmem108 */ { (xed_uint16_t) XED_ICLASS_FRSTOR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FRSTOR_MEMmem94 */ { (xed_uint16_t) XED_ICLASS_FRSTOR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSCALE */ { (xed_uint16_t) XED_ICLASS_FSCALE, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSETPM287_NOP */ { (xed_uint16_t) XED_ICLASS_FSETPM287_NOP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSIN */ { (xed_uint16_t) XED_ICLASS_FSIN, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSINCOS */ { (xed_uint16_t) XED_ICLASS_FSINCOS, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSQRT */ { (xed_uint16_t) XED_ICLASS_FSQRT, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FST_MEMm64real_ST0 */ { (xed_uint16_t) XED_ICLASS_FST, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FST_MEMmem32real_ST0 */ { (xed_uint16_t) XED_ICLASS_FST, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FST_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FST, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTP_MEMm64real_ST0 */ { (xed_uint16_t) XED_ICLASS_FSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTP_MEMmem32real_ST0 */ { (xed_uint16_t) XED_ICLASS_FSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTP_MEMmem80real_ST0 */ { (xed_uint16_t) XED_ICLASS_FSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTP_X87_ST0_DFD0 */ { (xed_uint16_t) XED_ICLASS_FSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTP_X87_ST0_DFD1 */ { (xed_uint16_t) XED_ICLASS_FSTP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSTPNCE_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FSTPNCE, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUB_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FSUB, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUB_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FSUB, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUB_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FSUB, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUB_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FSUB, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUBP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FSUBP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUBR_ST0_MEMm64real */ { (xed_uint16_t) XED_ICLASS_FSUBR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUBR_ST0_MEMmem32real */ { (xed_uint16_t) XED_ICLASS_FSUBR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUBR_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FSUBR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUBR_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FSUBR, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FSUBRP_X87_ST0 */ { (xed_uint16_t) XED_ICLASS_FSUBRP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FTST */ { (xed_uint16_t) XED_ICLASS_FTST, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FUCOM_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FUCOM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FUCOMI_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FUCOMI, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* FUCOMIP_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FUCOMIP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* FUCOMP_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FUCOMP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FUCOMPP */ { (xed_uint16_t) XED_ICLASS_FUCOMPP, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FWAIT */ { (xed_uint16_t) XED_ICLASS_FWAIT, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FXAM */ { (xed_uint16_t) XED_ICLASS_FXAM, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FXCH_ST0_X87 */ { (xed_uint16_t) XED_ICLASS_FXCH, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FXCH_ST0_X87_DDC1 */ { (xed_uint16_t) XED_ICLASS_FXCH, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FXCH_ST0_X87_DFC1 */ { (xed_uint16_t) XED_ICLASS_FXCH, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FXRSTOR_MEMmfpxenv */ { (xed_uint16_t) XED_ICLASS_FXRSTOR, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_FXSAVE, (xed_uint16_t) 0 }, +/* FXRSTOR64_MEMmfpxenv */ { (xed_uint16_t) XED_ICLASS_FXRSTOR64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_FXSAVE64, (xed_uint16_t) 0 }, +/* FXSAVE_MEMmfpxenv */ { (xed_uint16_t) XED_ICLASS_FXSAVE, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_FXSAVE, (xed_uint16_t) 0 }, +/* FXSAVE64_MEMmfpxenv */ { (xed_uint16_t) XED_ICLASS_FXSAVE64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_FXSAVE64, (xed_uint16_t) 0 }, +/* FXTRACT */ { (xed_uint16_t) XED_ICLASS_FXTRACT, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FYL2X */ { (xed_uint16_t) XED_ICLASS_FYL2X, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* FYL2XP1 */ { (xed_uint16_t) XED_ICLASS_FYL2XP1, (xed_uint8_t) XED_CATEGORY_X87_ALU, (xed_uint8_t) XED_EXTENSION_X87, (xed_uint16_t) XED_ISA_SET_X87, (xed_uint16_t) 0 }, +/* GETSEC */ { (xed_uint16_t) XED_ICLASS_GETSEC, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SMX, (xed_uint16_t) XED_ISA_SET_SMX, (xed_uint16_t) 0 }, +/* GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_GF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_GFNI, (xed_uint16_t) 0 }, +/* GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_GF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_GFNI, (xed_uint16_t) 0 }, +/* GF2P8AFFINEQB_XMMu8_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_GF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_GFNI, (xed_uint16_t) 0 }, +/* GF2P8AFFINEQB_XMMu8_XMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_GF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_GFNI, (xed_uint16_t) 0 }, +/* GF2P8MULB_XMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_GF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_GFNI, (xed_uint16_t) 0 }, +/* GF2P8MULB_XMMu8_XMMu8 */ { (xed_uint16_t) XED_ICLASS_GF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_GFNI, (xed_uint16_t) 0 }, +/* HADDPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_HADDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HADDPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_HADDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HADDPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_HADDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HADDPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_HADDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HLT */ { (xed_uint16_t) XED_ICLASS_HLT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* HRESET_IMM8 */ { (xed_uint16_t) XED_ICLASS_HRESET, (xed_uint8_t) XED_CATEGORY_HRESET, (xed_uint8_t)XED_EXTENSION_HRESET, (xed_uint16_t) XED_ISA_SET_HRESET, (xed_uint16_t) 0 }, +/* HSUBPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_HSUBPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HSUBPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_HSUBPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HSUBPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_HSUBPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* HSUBPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_HSUBPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* IDIV_GPR8 */ { (xed_uint16_t) XED_ICLASS_IDIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IDIV_GPRv */ { (xed_uint16_t) XED_ICLASS_IDIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IDIV_MEMb */ { (xed_uint16_t) XED_ICLASS_IDIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IDIV_MEMv */ { (xed_uint16_t) XED_ICLASS_IDIV, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IMUL_GPR8 */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IMUL_GPRv */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IMUL_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IMUL_GPRv_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* IMUL_GPRv_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* IMUL_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IMUL_GPRv_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* IMUL_GPRv_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* IMUL_MEMb */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IMUL_MEMv */ { (xed_uint16_t) XED_ICLASS_IMUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IN_AL_DX */ { (xed_uint16_t) XED_ICLASS_IN, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IN_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_IN, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IN_OeAX_DX */ { (xed_uint16_t) XED_ICLASS_IN, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IN_OeAX_IMMb */ { (xed_uint16_t) XED_ICLASS_IN, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INC_GPR8 */ { (xed_uint16_t) XED_ICLASS_INC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INC_GPRv_40 */ { (xed_uint16_t) XED_ICLASS_INC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INC_GPRv_FFr0 */ { (xed_uint16_t) XED_ICLASS_INC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INC_MEMb */ { (xed_uint16_t) XED_ICLASS_INC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INC_MEMv */ { (xed_uint16_t) XED_ICLASS_INC, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INCSSPD_GPR32u8 */ { (xed_uint16_t) XED_ICLASS_INCSSPD, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* INCSSPQ_GPR64u8 */ { (xed_uint16_t) XED_ICLASS_INCSSPQ, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* INC_LOCK_MEMb */ { (xed_uint16_t) XED_ICLASS_INC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 20 }, +/* INC_LOCK_MEMv */ { (xed_uint16_t) XED_ICLASS_INC_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 20 }, +/* INSB */ { (xed_uint16_t) XED_ICLASS_INSB, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* INSD */ { (xed_uint16_t) XED_ICLASS_INSD, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* INSERTPS_XMMps_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_INSERTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* INSERTPS_XMMps_XMMps_IMMb */ { (xed_uint16_t) XED_ICLASS_INSERTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* INSERTQ_XMMq_XMMdq */ { (xed_uint16_t) XED_ICLASS_INSERTQ, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_SSE4A, (xed_uint16_t) XED_ISA_SET_SSE4A, (xed_uint16_t) 0 }, +/* INSERTQ_XMMq_XMMq_IMMb_IMMb */ { (xed_uint16_t) XED_ICLASS_INSERTQ, (xed_uint8_t) XED_CATEGORY_BITBYTE, (xed_uint8_t) XED_EXTENSION_SSE4A, (xed_uint16_t) XED_ISA_SET_SSE4A, (xed_uint16_t) 0 }, +/* INSW */ { (xed_uint16_t) XED_ICLASS_INSW, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 40 }, +/* INT_IMMb */ { (xed_uint16_t) XED_ICLASS_INT, (xed_uint8_t) XED_CATEGORY_INTERRUPT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INT1 */ { (xed_uint16_t) XED_ICLASS_INT1, (xed_uint8_t) XED_CATEGORY_INTERRUPT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INT3 */ { (xed_uint16_t) XED_ICLASS_INT3, (xed_uint8_t) XED_CATEGORY_INTERRUPT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INTO */ { (xed_uint16_t) XED_ICLASS_INTO, (xed_uint8_t) XED_CATEGORY_INTERRUPT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* INVD */ { (xed_uint16_t) XED_ICLASS_INVD, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* INVEPT_GPR32_MEMdq */ { (xed_uint16_t) XED_ICLASS_INVEPT, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* INVEPT_GPR64_MEMdq */ { (xed_uint16_t) XED_ICLASS_INVEPT, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* INVLPG_MEMb */ { (xed_uint16_t) XED_ICLASS_INVLPG, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* INVLPGA_ArAX_ECX */ { (xed_uint16_t) XED_ICLASS_INVLPGA, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* INVLPGB_EAX_EDX_ECX */ { (xed_uint16_t) XED_ICLASS_INVLPGB, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t)XED_EXTENSION_AMD_INVLPGB, (xed_uint16_t) XED_ISA_SET_AMD_INVLPGB, (xed_uint16_t) 0 }, +/* INVLPGB_RAX_EDX_ECX */ { (xed_uint16_t) XED_ICLASS_INVLPGB, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t)XED_EXTENSION_AMD_INVLPGB, (xed_uint16_t) XED_ISA_SET_AMD_INVLPGB, (xed_uint16_t) 0 }, +/* INVPCID_GPR32_MEMdq */ { (xed_uint16_t) XED_ICLASS_INVPCID, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_INVPCID, (xed_uint16_t) XED_ISA_SET_INVPCID, (xed_uint16_t) 0 }, +/* INVPCID_GPR64_MEMdq */ { (xed_uint16_t) XED_ICLASS_INVPCID, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_INVPCID, (xed_uint16_t) XED_ISA_SET_INVPCID, (xed_uint16_t) 0 }, +/* INVVPID_GPR32_MEMdq */ { (xed_uint16_t) XED_ICLASS_INVVPID, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* INVVPID_GPR64_MEMdq */ { (xed_uint16_t) XED_ICLASS_INVVPID, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* IRET */ { (xed_uint16_t) XED_ICLASS_IRET, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* IRETD */ { (xed_uint16_t) XED_ICLASS_IRETD, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* IRETQ */ { (xed_uint16_t) XED_ICLASS_IRETQ, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* JB_RELBRb */ { (xed_uint16_t) XED_ICLASS_JB, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JB_RELBRd */ { (xed_uint16_t) XED_ICLASS_JB, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JB_RELBRz */ { (xed_uint16_t) XED_ICLASS_JB, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JBE_RELBRb */ { (xed_uint16_t) XED_ICLASS_JBE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JBE_RELBRd */ { (xed_uint16_t) XED_ICLASS_JBE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JBE_RELBRz */ { (xed_uint16_t) XED_ICLASS_JBE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JCXZ_RELBRb */ { (xed_uint16_t) XED_ICLASS_JCXZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* JECXZ_RELBRb */ { (xed_uint16_t) XED_ICLASS_JECXZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* JL_RELBRb */ { (xed_uint16_t) XED_ICLASS_JL, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JL_RELBRd */ { (xed_uint16_t) XED_ICLASS_JL, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JL_RELBRz */ { (xed_uint16_t) XED_ICLASS_JL, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JLE_RELBRb */ { (xed_uint16_t) XED_ICLASS_JLE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JLE_RELBRd */ { (xed_uint16_t) XED_ICLASS_JLE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JLE_RELBRz */ { (xed_uint16_t) XED_ICLASS_JLE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JMP_GPRv */ { (xed_uint16_t) XED_ICLASS_JMP, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JMP_MEMv */ { (xed_uint16_t) XED_ICLASS_JMP, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JMP_RELBRb */ { (xed_uint16_t) XED_ICLASS_JMP, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JMP_RELBRd */ { (xed_uint16_t) XED_ICLASS_JMP, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JMP_RELBRz */ { (xed_uint16_t) XED_ICLASS_JMP, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JMP_FAR_MEMp2 */ { (xed_uint16_t) XED_ICLASS_JMP_FAR, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 26 }, +/* JMP_FAR_PTRp_IMMw */ { (xed_uint16_t) XED_ICLASS_JMP_FAR, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 26 }, +/* JNB_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNB, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNB_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNB, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNB_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNB, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNBE_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNBE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNBE_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNBE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNBE_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNBE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNL_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNL, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNL_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNL, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNL_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNL, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNLE_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNLE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNLE_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNLE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNLE_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNLE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNO_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNO, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNO_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNO, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNO_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNO, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNP_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNP_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNP_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNS_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNS, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNS_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNS, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNS_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNS, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNZ_RELBRb */ { (xed_uint16_t) XED_ICLASS_JNZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNZ_RELBRd */ { (xed_uint16_t) XED_ICLASS_JNZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JNZ_RELBRz */ { (xed_uint16_t) XED_ICLASS_JNZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JO_RELBRb */ { (xed_uint16_t) XED_ICLASS_JO, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JO_RELBRd */ { (xed_uint16_t) XED_ICLASS_JO, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JO_RELBRz */ { (xed_uint16_t) XED_ICLASS_JO, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JP_RELBRb */ { (xed_uint16_t) XED_ICLASS_JP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JP_RELBRd */ { (xed_uint16_t) XED_ICLASS_JP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JP_RELBRz */ { (xed_uint16_t) XED_ICLASS_JP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JRCXZ_RELBRb */ { (xed_uint16_t) XED_ICLASS_JRCXZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* JS_RELBRb */ { (xed_uint16_t) XED_ICLASS_JS, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JS_RELBRd */ { (xed_uint16_t) XED_ICLASS_JS, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JS_RELBRz */ { (xed_uint16_t) XED_ICLASS_JS, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JZ_RELBRb */ { (xed_uint16_t) XED_ICLASS_JZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JZ_RELBRd */ { (xed_uint16_t) XED_ICLASS_JZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* JZ_RELBRz */ { (xed_uint16_t) XED_ICLASS_JZ, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KADDB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KADDD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KADDQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KADDW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDNB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDND, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDNQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDNW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KANDW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KMOVB_GPR32u32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KMOVB_MASKmskw_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KMOVB_MASKmskw_MASKu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KMOVB_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KMOVB_MEMu8_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KMOVD_GPR32u32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVD_MASKmskw_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVD_MASKmskw_MASKu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVD_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVD_MEMu32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVQ_GPR64u64_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVQ_MASKmskw_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVQ_MASKmskw_MASKu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVQ_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVQ_MEMu64_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KMOVW_GPR32u32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KMOVW_MASKmskw_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KMOVW_MASKmskw_MASKu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KMOVW_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KMOVW_MEMu16_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KMOVW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KNOTB_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KNOTB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KNOTD_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KNOTD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KNOTQ_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KNOTQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KNOTW_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KNOTW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KORB_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KORD_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KORTESTB_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORTESTB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KORTESTD_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORTESTD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KORTESTQ_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORTESTQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KORTESTW_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORTESTW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KORW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KORW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTLB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTLD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTLQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTLW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTRB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTRD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTRQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_KSHIFTRW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KTESTB_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KTESTB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KTESTD_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KTESTD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KTESTQ_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KTESTQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KTESTW_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KTESTW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KUNPCKBW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KUNPCKDQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KUNPCKWD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXNORB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXNORD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXNORQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXNORW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXORB, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_KOP, (xed_uint16_t) 0 }, +/* KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXORD, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXORQ, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_KOP, (xed_uint16_t) 0 }, +/* KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_KXORW, (xed_uint8_t) XED_CATEGORY_KMASK, (xed_uint8_t)XED_EXTENSION_AVX512VEX, (xed_uint16_t) XED_ISA_SET_AVX512F_KOP, (xed_uint16_t) 0 }, +/* LAHF */ { (xed_uint16_t) XED_ICLASS_LAHF, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_LAHF, (xed_uint16_t) 0 }, +/* LAR_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_LAR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LAR_GPRv_MEMw */ { (xed_uint16_t) XED_ICLASS_LAR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LDDQU_XMMpd_MEMdq */ { (xed_uint16_t) XED_ICLASS_LDDQU, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* LDMXCSR_MEMd */ { (xed_uint16_t) XED_ICLASS_LDMXCSR, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSEMXCSR, (xed_uint16_t) 0 }, +/* LDS_GPRz_MEMp */ { (xed_uint16_t) XED_ICLASS_LDS, (xed_uint8_t) XED_CATEGORY_SEGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LDTILECFG_MEM */ { (xed_uint16_t) XED_ICLASS_LDTILECFG, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* LEA_GPRv_AGEN */ { (xed_uint16_t) XED_ICLASS_LEA, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LEAVE */ { (xed_uint16_t) XED_ICLASS_LEAVE, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* LES_GPRz_MEMp */ { (xed_uint16_t) XED_ICLASS_LES, (xed_uint8_t) XED_CATEGORY_SEGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LFENCE */ { (xed_uint16_t) XED_ICLASS_LFENCE, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* LFS_GPRv_MEMp2 */ { (xed_uint16_t) XED_ICLASS_LFS, (xed_uint8_t) XED_CATEGORY_SEGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* LGDT_MEMs */ { (xed_uint16_t) XED_ICLASS_LGDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* LGDT_MEMs64 */ { (xed_uint16_t) XED_ICLASS_LGDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* LGS_GPRv_MEMp2 */ { (xed_uint16_t) XED_ICLASS_LGS, (xed_uint8_t) XED_CATEGORY_SEGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* LIDT_MEMs */ { (xed_uint16_t) XED_ICLASS_LIDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* LIDT_MEMs64 */ { (xed_uint16_t) XED_ICLASS_LIDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* LLDT_GPR16 */ { (xed_uint16_t) XED_ICLASS_LLDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LLDT_MEMw */ { (xed_uint16_t) XED_ICLASS_LLDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LLWPCB_VGPRyy */ { (xed_uint16_t) XED_ICLASS_LLWPCB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_LWP, (xed_uint16_t) 0 }, +/* LMSW_GPR16 */ { (xed_uint16_t) XED_ICLASS_LMSW, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* LMSW_MEMw */ { (xed_uint16_t) XED_ICLASS_LMSW, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* LOADIWKEY_XMMu8_XMMu8 */ { (xed_uint16_t) XED_ICLASS_LOADIWKEY, (xed_uint8_t) XED_CATEGORY_KEYLOCKER, (xed_uint8_t)XED_EXTENSION_KEYLOCKER, (xed_uint16_t) XED_ISA_SET_KEYLOCKER, (xed_uint16_t) 0 }, +/* LODSB */ { (xed_uint16_t) XED_ICLASS_LODSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LODSD */ { (xed_uint16_t) XED_ICLASS_LODSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* LODSQ */ { (xed_uint16_t) XED_ICLASS_LODSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* LODSW */ { (xed_uint16_t) XED_ICLASS_LODSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LOOP_RELBRb */ { (xed_uint16_t) XED_ICLASS_LOOP, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LOOPE_RELBRb */ { (xed_uint16_t) XED_ICLASS_LOOPE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LOOPNE_RELBRb */ { (xed_uint16_t) XED_ICLASS_LOOPNE, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* LSL_GPRv_GPRz */ { (xed_uint16_t) XED_ICLASS_LSL, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LSL_GPRv_MEMw */ { (xed_uint16_t) XED_ICLASS_LSL, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LSS_GPRv_MEMp2 */ { (xed_uint16_t) XED_ICLASS_LSS, (xed_uint8_t) XED_CATEGORY_SEGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* LTR_GPR16 */ { (xed_uint16_t) XED_ICLASS_LTR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LTR_MEMw */ { (xed_uint16_t) XED_ICLASS_LTR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* LWPINS_VGPRyy_MEMd_IMMd */ { (xed_uint16_t) XED_ICLASS_LWPINS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_LWP, (xed_uint16_t) 0 }, +/* LWPINS_VGPRyy_VGPR32y_IMMd */ { (xed_uint16_t) XED_ICLASS_LWPINS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_LWP, (xed_uint16_t) 0 }, +/* LWPVAL_VGPRyy_MEMd_IMMd */ { (xed_uint16_t) XED_ICLASS_LWPVAL, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_LWP, (xed_uint16_t) 0 }, +/* LWPVAL_VGPRyy_VGPR32y_IMMd */ { (xed_uint16_t) XED_ICLASS_LWPVAL, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_LWP, (xed_uint16_t) 0 }, +/* LZCNT_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_LZCNT, (xed_uint8_t) XED_CATEGORY_LZCNT, (xed_uint8_t) XED_EXTENSION_LZCNT, (xed_uint16_t) XED_ISA_SET_LZCNT, (xed_uint16_t) 0 }, +/* LZCNT_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_LZCNT, (xed_uint8_t) XED_CATEGORY_LZCNT, (xed_uint8_t) XED_EXTENSION_LZCNT, (xed_uint16_t) XED_ISA_SET_LZCNT, (xed_uint16_t) 0 }, +/* MASKMOVDQU_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_MASKMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MASKMOVQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_MASKMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MAXPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_MAXPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MAXPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_MAXPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MAXPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MAXPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MAXPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MAXPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MAXSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_MAXSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MAXSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_MAXSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MAXSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_MAXSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MAXSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_MAXSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MCOMMIT */ { (xed_uint16_t) XED_ICLASS_MCOMMIT, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_MCOMMIT, (xed_uint16_t) XED_ISA_SET_MCOMMIT, (xed_uint16_t) 0 }, +/* MFENCE */ { (xed_uint16_t) XED_ICLASS_MFENCE, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MINPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_MINPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MINPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_MINPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MINPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MINPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MINPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MINPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MINSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_MINSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MINSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_MINSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MINSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_MINSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MINSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_MINSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MONITOR */ { (xed_uint16_t) XED_ICLASS_MONITOR, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_MONITOR, (xed_uint16_t) XED_ISA_SET_MONITOR, (xed_uint16_t) 0 }, +/* MONITORX */ { (xed_uint16_t) XED_ICLASS_MONITORX, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_MONITORX, (xed_uint16_t) XED_ISA_SET_MONITORX, (xed_uint16_t) 0 }, +/* MOV_AL_MEMb */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPR8_GPR8_88 */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPR8_GPR8_8A */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPR8_IMMb_B0 */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPR8_IMMb_C6r0 */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPRv_GPRv_89 */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPRv_GPRv_8B */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPRv_IMMv */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_GPRv_SEG */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMb_AL */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMv_OrAX */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_MEMw_SEG */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_OrAX_MEMv */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_SEG_GPR16 */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOV_SEG_MEMw */ { (xed_uint16_t) XED_ICLASS_MOV, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOVAPD_MEMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_MOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVAPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_MOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVAPD_XMMpd_XMMpd_0F28 */ { (xed_uint16_t) XED_ICLASS_MOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVAPD_XMMpd_XMMpd_0F29 */ { (xed_uint16_t) XED_ICLASS_MOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVAPS_MEMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVAPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVAPS_XMMps_XMMps_0F28 */ { (xed_uint16_t) XED_ICLASS_MOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVAPS_XMMps_XMMps_0F29 */ { (xed_uint16_t) XED_ICLASS_MOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVBE_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_MOVBE, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MOVBE, (xed_uint16_t) XED_ISA_SET_MOVBE, (xed_uint16_t) 0 }, +/* MOVBE_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_MOVBE, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MOVBE, (xed_uint16_t) XED_ISA_SET_MOVBE, (xed_uint16_t) 0 }, +/* MOVD_GPR32_MMXd */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVD_GPR32_XMMd */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVD_MEMd_MMXd */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVD_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVD_MMXq_GPR32 */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVD_MMXq_MEMd */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVD_XMMdq_GPR32 */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_MOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDDUP_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_MOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* MOVDDUP_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* MOVDIR64B_GPRa_MEM */ { (xed_uint16_t) XED_ICLASS_MOVDIR64B, (xed_uint8_t) XED_CATEGORY_MOVDIR, (xed_uint8_t)XED_EXTENSION_MOVDIR, (xed_uint16_t) XED_ISA_SET_MOVDIR, (xed_uint16_t) 0 }, +/* MOVDIRI_MEMu32_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_MOVDIRI, (xed_uint8_t) XED_CATEGORY_MOVDIR, (xed_uint8_t)XED_EXTENSION_MOVDIR, (xed_uint16_t) XED_ISA_SET_MOVDIR, (xed_uint16_t) 0 }, +/* MOVDIRI_MEMu64_GPR64u64 */ { (xed_uint16_t) XED_ICLASS_MOVDIRI, (xed_uint8_t) XED_CATEGORY_MOVDIR, (xed_uint8_t)XED_EXTENSION_MOVDIR, (xed_uint16_t) XED_ISA_SET_MOVDIR, (xed_uint16_t) 0 }, +/* MOVDQ2Q_MMXq_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVDQ2Q, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQA_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_MOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQA_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_MOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQA_XMMdq_XMMdq_0F6F */ { (xed_uint16_t) XED_ICLASS_MOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQA_XMMdq_XMMdq_0F7F */ { (xed_uint16_t) XED_ICLASS_MOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQU_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_MOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQU_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_MOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQU_XMMdq_XMMdq_0F6F */ { (xed_uint16_t) XED_ICLASS_MOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVDQU_XMMdq_XMMdq_0F7F */ { (xed_uint16_t) XED_ICLASS_MOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVHLPS_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVHLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVHPD_MEMq_XMMsd */ { (xed_uint16_t) XED_ICLASS_MOVHPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVHPD_XMMsd_MEMq */ { (xed_uint16_t) XED_ICLASS_MOVHPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVHPS_MEMq_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVHPS_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_MOVHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVLHPS_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVLHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVLPD_MEMq_XMMsd */ { (xed_uint16_t) XED_ICLASS_MOVLPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVLPD_XMMsd_MEMq */ { (xed_uint16_t) XED_ICLASS_MOVLPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVLPS_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVLPS_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_MOVLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVMSKPD_GPR32_XMMpd */ { (xed_uint16_t) XED_ICLASS_MOVMSKPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVMSKPS_GPR32_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVMSKPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVNTDQ_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_MOVNTDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVNTDQA_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_MOVNTDQA, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* MOVNTI_MEMd_GPR32 */ { (xed_uint16_t) XED_ICLASS_MOVNTI, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVNTI_MEMq_GPR64 */ { (xed_uint16_t) XED_ICLASS_MOVNTI, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVNTPD_MEMdq_XMMpd */ { (xed_uint16_t) XED_ICLASS_MOVNTPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVNTPS_MEMdq_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVNTPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVNTQ_MEMq_MMXq */ { (xed_uint16_t) XED_ICLASS_MOVNTQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVNTSD_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVNTSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE4A, (xed_uint16_t) XED_ISA_SET_SSE4A, (xed_uint16_t) 0 }, +/* MOVNTSS_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_MOVNTSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE4A, (xed_uint16_t) XED_ISA_SET_SSE4A, (xed_uint16_t) 0 }, +/* MOVQ_GPR64_MMXq */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_GPR64_XMMq */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_MEMq_MMXq_0F7E */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_MEMq_MMXq_0F7F */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_MEMq_XMMq_0F7E */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_MEMq_XMMq_0FD6 */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_MMXq_GPR64 */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_MMXq_MEMq_0F6E */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_MMXq_MEMq_0F6F */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_MMXq_MMXq_0F6F */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_MMXq_MMXq_0F7F */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* MOVQ_XMMdq_GPR64 */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_XMMdq_MEMq_0F6E */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_XMMdq_MEMq_0F7E */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_XMMdq_XMMq_0F7E */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ_XMMdq_XMMq_0FD6 */ { (xed_uint16_t) XED_ICLASS_MOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVQ2DQ_XMMdq_MMXq */ { (xed_uint16_t) XED_ICLASS_MOVQ2DQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVSB */ { (xed_uint16_t) XED_ICLASS_MOVSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOVSD */ { (xed_uint16_t) XED_ICLASS_MOVSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVSD_XMM_MEMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_MOVSD_XMM, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 56 }, +/* MOVSD_XMM_XMMdq_MEMsd */ { (xed_uint16_t) XED_ICLASS_MOVSD_XMM, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 56 }, +/* MOVSD_XMM_XMMsd_XMMsd_0F10 */ { (xed_uint16_t) XED_ICLASS_MOVSD_XMM, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 56 }, +/* MOVSD_XMM_XMMsd_XMMsd_0F11 */ { (xed_uint16_t) XED_ICLASS_MOVSD_XMM, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 56 }, +/* MOVSHDUP_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* MOVSHDUP_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* MOVSLDUP_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* MOVSLDUP_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE3, (xed_uint16_t) XED_ISA_SET_SSE3, (xed_uint16_t) 0 }, +/* MOVSQ */ { (xed_uint16_t) XED_ICLASS_MOVSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* MOVSS_MEMss_XMMss */ { (xed_uint16_t) XED_ICLASS_MOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVSS_XMMdq_MEMss */ { (xed_uint16_t) XED_ICLASS_MOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVSS_XMMss_XMMss_0F10 */ { (xed_uint16_t) XED_ICLASS_MOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVSS_XMMss_XMMss_0F11 */ { (xed_uint16_t) XED_ICLASS_MOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVSW */ { (xed_uint16_t) XED_ICLASS_MOVSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MOVSX_GPRv_GPR16 */ { (xed_uint16_t) XED_ICLASS_MOVSX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVSX_GPRv_GPR8 */ { (xed_uint16_t) XED_ICLASS_MOVSX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVSX_GPRv_MEMb */ { (xed_uint16_t) XED_ICLASS_MOVSX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVSX_GPRv_MEMw */ { (xed_uint16_t) XED_ICLASS_MOVSX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVSXD_GPRv_GPRz */ { (xed_uint16_t) XED_ICLASS_MOVSXD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* MOVSXD_GPRv_MEMz */ { (xed_uint16_t) XED_ICLASS_MOVSXD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* MOVUPD_MEMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_MOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVUPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_MOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVUPD_XMMpd_XMMpd_0F10 */ { (xed_uint16_t) XED_ICLASS_MOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVUPD_XMMpd_XMMpd_0F11 */ { (xed_uint16_t) XED_ICLASS_MOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MOVUPS_MEMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVUPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVUPS_XMMps_XMMps_0F10 */ { (xed_uint16_t) XED_ICLASS_MOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVUPS_XMMps_XMMps_0F11 */ { (xed_uint16_t) XED_ICLASS_MOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MOVZX_GPRv_GPR16 */ { (xed_uint16_t) XED_ICLASS_MOVZX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVZX_GPRv_GPR8 */ { (xed_uint16_t) XED_ICLASS_MOVZX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVZX_GPRv_MEMb */ { (xed_uint16_t) XED_ICLASS_MOVZX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOVZX_GPRv_MEMw */ { (xed_uint16_t) XED_ICLASS_MOVZX, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* MOV_CR_CR_GPR32 */ { (xed_uint16_t) XED_ICLASS_MOV_CR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_CR_CR_GPR64 */ { (xed_uint16_t) XED_ICLASS_MOV_CR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_CR_GPR32_CR */ { (xed_uint16_t) XED_ICLASS_MOV_CR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_CR_GPR64_CR */ { (xed_uint16_t) XED_ICLASS_MOV_CR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_DR_DR_GPR32 */ { (xed_uint16_t) XED_ICLASS_MOV_DR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_DR_DR_GPR64 */ { (xed_uint16_t) XED_ICLASS_MOV_DR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_DR_GPR32_DR */ { (xed_uint16_t) XED_ICLASS_MOV_DR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MOV_DR_GPR64_DR */ { (xed_uint16_t) XED_ICLASS_MOV_DR, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 98 }, +/* MPSADBW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_MPSADBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* MPSADBW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_MPSADBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* MUL_GPR8 */ { (xed_uint16_t) XED_ICLASS_MUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MUL_GPRv */ { (xed_uint16_t) XED_ICLASS_MUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MUL_MEMb */ { (xed_uint16_t) XED_ICLASS_MUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MUL_MEMv */ { (xed_uint16_t) XED_ICLASS_MUL, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* MULPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_MULPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MULPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_MULPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MULPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_MULPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MULPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_MULPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MULSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_MULSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MULSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_MULSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* MULSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_MULSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MULSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_MULSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* MULX_VGPR32d_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_MULX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* MULX_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_MULX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* MULX_VGPR64q_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_MULX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* MULX_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_MULX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* MWAIT */ { (xed_uint16_t) XED_ICLASS_MWAIT, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_MONITOR, (xed_uint16_t) XED_ISA_SET_MONITOR, (xed_uint16_t) 0 }, +/* MWAITX */ { (xed_uint16_t) XED_ICLASS_MWAITX, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t)XED_EXTENSION_MONITORX, (xed_uint16_t) XED_ISA_SET_MONITORX, (xed_uint16_t) 0 }, +/* NEG_GPR8 */ { (xed_uint16_t) XED_ICLASS_NEG, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NEG_GPRv */ { (xed_uint16_t) XED_ICLASS_NEG, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NEG_MEMb */ { (xed_uint16_t) XED_ICLASS_NEG, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NEG_MEMv */ { (xed_uint16_t) XED_ICLASS_NEG, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NEG_LOCK_MEMb */ { (xed_uint16_t) XED_ICLASS_NEG_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 18 }, +/* NEG_LOCK_MEMv */ { (xed_uint16_t) XED_ICLASS_NEG_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 18 }, +/* NOP_90 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_NOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r0 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r1 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r2 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r3 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r4 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r5 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r6 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_0F18r7 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F0D */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F19 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F1A */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F1B */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F1C */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F1D */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F1E */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_GPRv_GPRv_0F1F */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_GPRv_MEM_0F1B */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_GPRv_MEMv_0F1A */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_MEMv_0F18r4 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_MEMv_0F18r5 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_MEMv_0F18r6 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_MEMv_0F18r7 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_MEMv_GPRv_0F19 */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_MEMv_GPRv_0F1C */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_MEMv_GPRv_0F1D */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOP_MEMv_GPRv_0F1E */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* NOP_MEMv_GPRv_0F1F */ { (xed_uint16_t) XED_ICLASS_NOP, (xed_uint8_t) XED_CATEGORY_WIDENOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_FAT_NOP, (xed_uint16_t) 0 }, +/* NOT_GPR8 */ { (xed_uint16_t) XED_ICLASS_NOT, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NOT_GPRv */ { (xed_uint16_t) XED_ICLASS_NOT, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NOT_MEMb */ { (xed_uint16_t) XED_ICLASS_NOT, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NOT_MEMv */ { (xed_uint16_t) XED_ICLASS_NOT, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* NOT_LOCK_MEMb */ { (xed_uint16_t) XED_ICLASS_NOT_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 16 }, +/* NOT_LOCK_MEMv */ { (xed_uint16_t) XED_ICLASS_NOT_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 16 }, +/* OR_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPR8_GPR8_08 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPR8_GPR8_0A */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPR8_IMMb_80r1 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPR8_IMMb_82r1 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPRv_GPRv_09 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPRv_GPRv_0B */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_MEMb_IMMb_80r1 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_MEMb_IMMb_82r1 */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OR_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_OR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ORPD_XMMxuq_MEMxuq */ { (xed_uint16_t) XED_ICLASS_ORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ORPD_XMMxuq_XMMxuq */ { (xed_uint16_t) XED_ICLASS_ORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* ORPS_XMMxud_MEMxud */ { (xed_uint16_t) XED_ICLASS_ORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* ORPS_XMMxud_XMMxud */ { (xed_uint16_t) XED_ICLASS_ORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* OR_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_OR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 4 }, +/* OR_LOCK_MEMb_IMMb_80r1 */ { (xed_uint16_t) XED_ICLASS_OR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 4 }, +/* OR_LOCK_MEMb_IMMb_82r1 */ { (xed_uint16_t) XED_ICLASS_OR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 4 }, +/* OR_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_OR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 4 }, +/* OR_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_OR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 4 }, +/* OR_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_OR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 4 }, +/* OUT_DX_AL */ { (xed_uint16_t) XED_ICLASS_OUT, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OUT_DX_OeAX */ { (xed_uint16_t) XED_ICLASS_OUT, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OUT_IMMb_AL */ { (xed_uint16_t) XED_ICLASS_OUT, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OUT_IMMb_OeAX */ { (xed_uint16_t) XED_ICLASS_OUT, (xed_uint8_t) XED_CATEGORY_IO, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* OUTSB */ { (xed_uint16_t) XED_ICLASS_OUTSB, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* OUTSD */ { (xed_uint16_t) XED_ICLASS_OUTSD, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* OUTSW */ { (xed_uint16_t) XED_ICLASS_OUTSW, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* PABSB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PABSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PABSB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PABSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PABSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PABSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PABSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PABSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PABSD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PABSD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PABSD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PABSD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PABSD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PABSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PABSD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PABSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PABSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PABSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PABSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PABSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PABSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PABSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PABSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PABSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PACKSSDW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PACKSSDW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PACKSSDW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PACKSSDW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PACKSSDW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PACKSSDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PACKSSDW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PACKSSDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PACKSSWB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PACKSSWB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PACKSSWB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PACKSSWB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PACKSSWB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PACKSSWB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PACKSSWB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PACKSSWB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PACKUSDW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PACKUSDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PACKUSDW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PACKUSDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PACKUSWB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PACKUSWB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PACKUSWB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PACKUSWB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PACKUSWB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PACKUSWB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PACKUSWB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PACKUSWB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2MMX, (xed_uint16_t) 0 }, +/* PADDQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2MMX, (xed_uint16_t) 0 }, +/* PADDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDSB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDSB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDUSB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDUSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDUSB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDUSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDUSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDUSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDUSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDUSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDUSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDUSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDUSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDUSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDUSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDUSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDUSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDUSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PADDW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PADDW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PADDW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PADDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PADDW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PADDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PALIGNR_MMXq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_PALIGNR, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PALIGNR_MMXq_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PALIGNR, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PALIGNR_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PALIGNR, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PALIGNR_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PALIGNR, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PAND_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PAND_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PAND_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PAND_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PANDN_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PANDN_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PANDN_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PANDN_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PAUSE */ { (xed_uint16_t) XED_ICLASS_PAUSE, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_PAUSE, (xed_uint16_t) XED_ISA_SET_PAUSE, (xed_uint16_t) 0 }, +/* PAVGB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PAVGB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PAVGB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PAVGB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PAVGB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PAVGB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PAVGB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PAVGB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PAVGUSB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PAVGUSB, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PAVGUSB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PAVGUSB, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PAVGW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PAVGW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PAVGW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PAVGW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PAVGW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PAVGW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PAVGW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PAVGW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PBLENDVB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PBLENDVB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PBLENDVB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PBLENDVB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PBLENDW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PBLENDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PBLENDW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PBLENDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PCLMULQDQ_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCLMULQDQ, (xed_uint8_t) XED_CATEGORY_PCLMULQDQ, (xed_uint8_t)XED_EXTENSION_PCLMULQDQ, (xed_uint16_t) XED_ISA_SET_PCLMULQDQ, (xed_uint16_t) 0 }, +/* PCLMULQDQ_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCLMULQDQ, (xed_uint8_t) XED_CATEGORY_PCLMULQDQ, (xed_uint8_t)XED_EXTENSION_PCLMULQDQ, (xed_uint16_t) XED_ISA_SET_PCLMULQDQ, (xed_uint16_t) 0 }, +/* PCMPEQB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PCMPEQB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPEQB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PCMPEQB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPEQB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPEQB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPEQD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PCMPEQD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPEQD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PCMPEQD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPEQD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPEQD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPEQQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PCMPEQQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PCMPEQW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PCMPEQW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPEQW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PCMPEQW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPEQW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPEQW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPEQW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPESTRI_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRI, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPESTRI_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRI, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPESTRI64_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRI64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 106 }, +/* PCMPESTRI64_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRI64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 106 }, +/* PCMPESTRM_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRM, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPESTRM_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRM, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPESTRM64_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRM64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 110 }, +/* PCMPESTRM64_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPESTRM64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 110 }, +/* PCMPGTB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PCMPGTB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPGTB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PCMPGTB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPGTB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPGTB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPGTD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PCMPGTD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPGTD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PCMPGTD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPGTD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPGTD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPGTQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPGTQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPGTW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PCMPGTW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPGTW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PCMPGTW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PCMPGTW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPGTW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PCMPGTW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PCMPISTRI_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPISTRI, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPISTRI_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPISTRI, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPISTRI64_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPISTRI64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 108 }, +/* PCMPISTRI64_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPISTRI64, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 108 }, +/* PCMPISTRM_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPISTRM, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCMPISTRM_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PCMPISTRM, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE42, (xed_uint16_t) 0 }, +/* PCONFIG */ { (xed_uint16_t) XED_ICLASS_PCONFIG, (xed_uint8_t) XED_CATEGORY_PCONFIG, (xed_uint8_t)XED_EXTENSION_PCONFIG, (xed_uint16_t) XED_ISA_SET_PCONFIG, (xed_uint16_t) 0 }, +/* PCONFIG64 */ { (xed_uint16_t) XED_ICLASS_PCONFIG, (xed_uint8_t) XED_CATEGORY_PCONFIG, (xed_uint8_t)XED_EXTENSION_PCONFIG, (xed_uint16_t) XED_ISA_SET_PCONFIG, (xed_uint16_t) 0 }, +/* PDEP_VGPR32d_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_PDEP, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PDEP_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_PDEP, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PDEP_VGPR64q_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_PDEP, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PDEP_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_PDEP, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PEXT_VGPR32d_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_PEXT, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PEXT_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_PEXT, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PEXT_VGPR64q_VGPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_PEXT, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PEXT_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_PEXT, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* PEXTRB_GPR32d_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PEXTRB_MEMb_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PEXTRD_GPR32d_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PEXTRD_MEMd_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PEXTRQ_GPR64q_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PEXTRQ_MEMq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PEXTRW_GPR32_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PEXTRW_GPR32_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PEXTRW_SSE4_GPR32_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRW_SSE4, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 104 }, +/* PEXTRW_SSE4_MEMw_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PEXTRW_SSE4, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 104 }, +/* PF2ID_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PF2ID, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PF2ID_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PF2ID, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PF2IW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PF2IW, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PF2IW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PF2IW, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFACC_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFACC, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFACC_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFACC, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFADD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFADD, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFADD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFADD, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFCMPEQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFCMPEQ, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFCMPEQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFCMPEQ, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFCMPGE_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFCMPGE, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFCMPGE_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFCMPGE, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFCMPGT_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFCMPGT, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFCMPGT_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFCMPGT, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFMAX_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFMAX, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFMAX_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFMAX, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFMIN_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFMIN, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFMIN_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFMIN, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFMUL_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFMUL, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFMUL_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFMUL, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFNACC_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFNACC, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFNACC_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFNACC, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFPNACC_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFPNACC, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFPNACC_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFPNACC, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRCP_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFRCP, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRCP_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFRCP, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRCPIT1_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFRCPIT1, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRCPIT1_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFRCPIT1, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRCPIT2_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFRCPIT2, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRCPIT2_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFRCPIT2, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRSQIT1_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFRSQIT1, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRSQIT1_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFRSQIT1, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRSQRT_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFRSQRT, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFRSQRT_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFRSQRT, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFSUB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFSUB, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFSUB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFSUB, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFSUBR_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PFSUBR, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PFSUBR_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PFSUBR, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PHADDD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PHADDD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHADDD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PHADDD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHADDD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHADDD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHADDD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHADDD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHADDSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PHADDSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHADDSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PHADDSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHADDSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHADDSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHADDSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHADDSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHADDW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PHADDW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHADDW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PHADDW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHADDW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHADDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHADDW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHADDW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHMINPOSUW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHMINPOSUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PHMINPOSUW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHMINPOSUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PHSUBD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PHSUBD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHSUBD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PHSUBD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHSUBD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHSUBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHSUBD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHSUBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHSUBSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PHSUBSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHSUBSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PHSUBSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHSUBSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHSUBSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHSUBSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHSUBSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHSUBW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PHSUBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHSUBW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PHSUBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PHSUBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PHSUBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PHSUBW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PHSUBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PI2FD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PI2FD, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PI2FD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PI2FD, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PI2FW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PI2FW, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PI2FW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PI2FW, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PINSRB_XMMdq_GPR32d_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PINSRB_XMMdq_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PINSRD_XMMdq_GPR32d_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PINSRD_XMMdq_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PINSRQ_XMMdq_GPR64q_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PINSRQ_XMMdq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PINSRW_MMXq_GPR32_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PINSRW_MMXq_MEMw_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PINSRW_XMMdq_GPR32_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PINSRW_XMMdq_MEMw_IMMb */ { (xed_uint16_t) XED_ICLASS_PINSRW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMADDUBSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMADDUBSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PMADDUBSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMADDUBSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PMADDUBSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMADDUBSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PMADDUBSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMADDUBSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PMADDWD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMADDWD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMADDWD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMADDWD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMADDWD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMADDWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMADDWD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMADDWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMAXSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMAXSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMAXSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXSD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMAXSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXSD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMAXSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMAXSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMAXSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMAXSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMAXSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMAXSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMAXSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMAXSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMAXUB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMAXUB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMAXUB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMAXUB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMAXUB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMAXUB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMAXUB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMAXUB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMAXUD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMAXUD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXUD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMAXUD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXUW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMAXUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMAXUW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMAXUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMINSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMINSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINSD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMINSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINSD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMINSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMINSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMINSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMINSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMINSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMINSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMINSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMINSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMINUB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMINUB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMINUB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMINUB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMINUB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMINUB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMINUB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMINUB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMINUD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMINUD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINUD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMINUD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINUW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMINUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMINUW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMINUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVMSKB_GPR32_MMXq */ { (xed_uint16_t) XED_ICLASS_PMOVMSKB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* PMOVMSKB_GPR32_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMOVMSKB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMOVSXBD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_PMOVSXBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXBD_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_PMOVSXBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXBQ_XMMdq_MEMw */ { (xed_uint16_t) XED_ICLASS_PMOVSXBQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXBQ_XMMdq_XMMw */ { (xed_uint16_t) XED_ICLASS_PMOVSXBQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXBW_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMOVSXBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXBW_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PMOVSXBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXDQ_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMOVSXDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PMOVSXDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXWD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMOVSXWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXWD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PMOVSXWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXWQ_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_PMOVSXWQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVSXWQ_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_PMOVSXWQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXBD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_PMOVZXBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXBD_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_PMOVZXBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXBQ_XMMdq_MEMw */ { (xed_uint16_t) XED_ICLASS_PMOVZXBQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXBQ_XMMdq_XMMw */ { (xed_uint16_t) XED_ICLASS_PMOVZXBQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXBW_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMOVZXBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXBW_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PMOVZXBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXDQ_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMOVZXDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PMOVZXDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXWD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMOVZXWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXWD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PMOVZXWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXWQ_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_PMOVZXWQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMOVZXWQ_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_PMOVZXWQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMULDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMULDQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMULHRSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMULHRSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PMULHRSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMULHRSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PMULHRSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULHRSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PMULHRSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULHRSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PMULHRW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMULHRW, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PMULHRW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMULHRW, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PMULHUW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMULHUW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMULHUW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMULHUW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMULHUW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULHUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULHUW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULHUW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULHW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMULHW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMULHW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMULHW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMULHW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULHW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULHW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULHW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULLD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMULLD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PMULLW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMULLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMULLW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMULLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PMULLW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULLW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULUDQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PMULUDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2MMX, (xed_uint16_t) 0 }, +/* PMULUDQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PMULUDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2MMX, (xed_uint16_t) 0 }, +/* PMULUDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PMULUDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PMULUDQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PMULUDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* POP_DS */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_ES */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_FS */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_GPRv_58 */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_GPRv_8F */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_GS */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_MEMv */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POP_SS */ { (xed_uint16_t) XED_ICLASS_POP, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POPA */ { (xed_uint16_t) XED_ICLASS_POPA, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* POPAD */ { (xed_uint16_t) XED_ICLASS_POPAD, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* POPCNT_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_POPCNT, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_POPCNT, (xed_uint16_t) 0 }, +/* POPCNT_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_POPCNT, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_POPCNT, (xed_uint16_t) 0 }, +/* POPF */ { (xed_uint16_t) XED_ICLASS_POPF, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* POPFD */ { (xed_uint16_t) XED_ICLASS_POPFD, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* POPFQ */ { (xed_uint16_t) XED_ICLASS_POPFQ, (xed_uint8_t) XED_CATEGORY_POP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* POR_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_POR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* POR_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_POR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* POR_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_POR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* POR_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_POR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PREFETCHNTA_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_PREFETCHNTA, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE_PREFETCH, (xed_uint16_t) 0 }, +/* PREFETCHT0_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_PREFETCHT0, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE_PREFETCH, (xed_uint16_t) 0 }, +/* PREFETCHT1_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_PREFETCHT1, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE_PREFETCH, (xed_uint16_t) 0 }, +/* PREFETCHT2_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_PREFETCHT2, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE_PREFETCH, (xed_uint16_t) 0 }, +/* PREFETCHW_0F0Dr1 */ { (xed_uint16_t) XED_ICLASS_PREFETCHW, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PREFETCHW_0F0Dr3 */ { (xed_uint16_t) XED_ICLASS_PREFETCHW, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PREFETCHWT1_MEMu8 */ { (xed_uint16_t) XED_ICLASS_PREFETCHWT1, (xed_uint8_t) XED_CATEGORY_PREFETCHWT1, (xed_uint8_t)XED_EXTENSION_PREFETCHWT1, (xed_uint16_t) XED_ISA_SET_PREFETCHWT1, (xed_uint16_t) 0 }, +/* PREFETCH_EXCLUSIVE_MEMmprefetch */ { (xed_uint16_t) XED_ICLASS_PREFETCH_EXCLUSIVE, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PREFETCH_RESERVED_0F0Dr4 */ { (xed_uint16_t) XED_ICLASS_PREFETCH_RESERVED, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PREFETCH_RESERVED_0F0Dr5 */ { (xed_uint16_t) XED_ICLASS_PREFETCH_RESERVED, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PREFETCH_RESERVED_0F0Dr6 */ { (xed_uint16_t) XED_ICLASS_PREFETCH_RESERVED, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PREFETCH_RESERVED_0F0Dr7 */ { (xed_uint16_t) XED_ICLASS_PREFETCH_RESERVED, (xed_uint8_t) XED_CATEGORY_PREFETCH, (xed_uint8_t)XED_EXTENSION_3DNOW_PREFETCH, (xed_uint16_t) XED_ISA_SET_PREFETCH_NOP, (xed_uint16_t) 0 }, +/* PSADBW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSADBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSADBW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSADBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSADBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSADBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSADBW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSADBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSHUFB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSHUFB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSHUFB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSHUFB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSHUFB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSHUFB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSHUFB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSHUFD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFHW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFHW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFHW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFHW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFLW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFLW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSHUFW_MMXq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSHUFW_MMXq_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSHUFW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSIGNB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSIGNB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSIGNB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSIGNB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSIGNB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSIGNB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSIGNB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSIGNB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSIGND_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSIGND, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSIGND_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSIGND, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSIGND_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSIGND, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSIGND_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSIGND, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSIGNW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSIGNW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSIGNW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSIGNW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3MMX, (xed_uint16_t) 0 }, +/* PSIGNW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSIGNW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSIGNW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSIGNW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSSE3, (xed_uint16_t) XED_ISA_SET_SSSE3, (xed_uint16_t) 0 }, +/* PSLLD_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSLLD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSLLD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLD_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSLLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSLLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLDQ_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLQ_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSLLQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSLLQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLQ_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSLLQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSLLQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLW_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSLLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSLLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSLLW_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSLLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSLLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSLLW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSLLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSMASH_RAX */ { (xed_uint16_t) XED_ICLASS_PSMASH, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SNP, (xed_uint16_t) XED_ISA_SET_SNP, (xed_uint16_t) 0 }, +/* PSRAD_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRAD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRAD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSRAD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRAD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSRAD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRAD_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRAD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRAD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSRAD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRAD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSRAD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRAW_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRAW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRAW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSRAW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRAW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSRAW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRAW_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRAW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRAW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSRAW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRAW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSRAW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLD_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSRLD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSRLD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLD_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSRLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSRLD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLDQ_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLQ_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSRLQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSRLQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLQ_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSRLQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSRLQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLW_MMXq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSRLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSRLW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSRLW_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_PSRLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSRLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSRLW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSRLW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2MMX, (xed_uint16_t) 0 }, +/* PSUBQ_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2MMX, (xed_uint16_t) 0 }, +/* PSUBQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBSB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBSB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBUSB_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBUSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBUSB_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBUSB, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBUSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBUSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBUSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBUSB, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBUSW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBUSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBUSW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBUSW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBUSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBUSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBUSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBUSW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSUBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBW_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSUBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PSUBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PSUBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSUBW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PSUBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PSWAPD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PSWAPD, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PSWAPD_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PSWAPD, (xed_uint8_t) XED_CATEGORY_3DNOW, (xed_uint8_t) XED_EXTENSION_3DNOW, (xed_uint16_t) XED_ISA_SET_3DNOW, (xed_uint16_t) 0 }, +/* PTEST_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PTEST_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* PTWRITE_GPRy */ { (xed_uint16_t) XED_ICLASS_PTWRITE, (xed_uint8_t) XED_CATEGORY_PTWRITE, (xed_uint8_t)XED_EXTENSION_PTWRITE, (xed_uint16_t) XED_ISA_SET_PTWRITE, (xed_uint16_t) 0 }, +/* PTWRITE_MEMy */ { (xed_uint16_t) XED_ICLASS_PTWRITE, (xed_uint8_t) XED_CATEGORY_PTWRITE, (xed_uint8_t)XED_EXTENSION_PTWRITE, (xed_uint16_t) XED_ISA_SET_PTWRITE, (xed_uint16_t) 0 }, +/* PUNPCKHBW_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKHBW_MMXq_MMXd */ { (xed_uint16_t) XED_ICLASS_PUNPCKHBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKHBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHBW_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHDQ_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKHDQ_MMXq_MMXd */ { (xed_uint16_t) XED_ICLASS_PUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKHDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHQDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHQDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHWD_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHWD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKHWD_MMXq_MMXd */ { (xed_uint16_t) XED_ICLASS_PUNPCKHWD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKHWD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKHWD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKHWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLBW_MMXq_MEMd */ { (xed_uint16_t) XED_ICLASS_PUNPCKLBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKLBW_MMXq_MMXd */ { (xed_uint16_t) XED_ICLASS_PUNPCKLBW, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKLBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLBW_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLBW, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLDQ_MMXq_MEMd */ { (xed_uint16_t) XED_ICLASS_PUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKLDQ_MMXq_MMXd */ { (xed_uint16_t) XED_ICLASS_PUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKLDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLQDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLQDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLWD_MMXq_MEMd */ { (xed_uint16_t) XED_ICLASS_PUNPCKLWD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKLWD_MMXq_MMXd */ { (xed_uint16_t) XED_ICLASS_PUNPCKLWD, (xed_uint8_t) XED_CATEGORY_MMX, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PUNPCKLWD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUNPCKLWD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_PUNPCKLWD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PUSH_CS */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_DS */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_ES */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_FS */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_GPRv_50 */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_GPRv_FFr6 */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_GS */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_IMMb */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* PUSH_IMMz */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* PUSH_MEMv */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSH_SS */ { (xed_uint16_t) XED_ICLASS_PUSH, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSHA */ { (xed_uint16_t) XED_ICLASS_PUSHA, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* PUSHAD */ { (xed_uint16_t) XED_ICLASS_PUSHAD, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* PUSHF */ { (xed_uint16_t) XED_ICLASS_PUSHF, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* PUSHFD */ { (xed_uint16_t) XED_ICLASS_PUSHFD, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* PUSHFQ */ { (xed_uint16_t) XED_ICLASS_PUSHFQ, (xed_uint8_t) XED_CATEGORY_PUSH, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* PVALIDATE_RAX_ECX_EDX */ { (xed_uint16_t) XED_ICLASS_PVALIDATE, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SNP, (xed_uint16_t) XED_ISA_SET_SNP, (xed_uint16_t) 0 }, +/* PXOR_MMXq_MEMq */ { (xed_uint16_t) XED_ICLASS_PXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PXOR_MMXq_MMXq */ { (xed_uint16_t) XED_ICLASS_PXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_MMX, (xed_uint16_t) XED_ISA_SET_PENTIUMMMX, (xed_uint16_t) 0 }, +/* PXOR_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_PXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* PXOR_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_PXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* RCL_GPR8_CL */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_GPR8_IMMb */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCL_GPR8_ONE */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCL_GPRv_ONE */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_MEMb_CL */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCL_MEMb_ONE */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_MEMv_CL */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCL_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCL_MEMv_ONE */ { (xed_uint16_t) XED_ICLASS_RCL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCPPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_RCPPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RCPPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_RCPPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RCPSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_RCPSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RCPSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_RCPSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RCR_GPR8_CL */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_GPR8_IMMb */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCR_GPR8_ONE */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCR_GPRv_ONE */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_MEMb_CL */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCR_MEMb_ONE */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_MEMv_CL */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RCR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* RCR_MEMv_ONE */ { (xed_uint16_t) XED_ICLASS_RCR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RDFSBASE_GPRy */ { (xed_uint16_t) XED_ICLASS_RDFSBASE, (xed_uint8_t) XED_CATEGORY_RDWRFSGS, (xed_uint8_t)XED_EXTENSION_RDWRFSGS, (xed_uint16_t) XED_ISA_SET_RDWRFSGS, (xed_uint16_t) 0 }, +/* RDGSBASE_GPRy */ { (xed_uint16_t) XED_ICLASS_RDGSBASE, (xed_uint8_t) XED_CATEGORY_RDWRFSGS, (xed_uint8_t)XED_EXTENSION_RDWRFSGS, (xed_uint16_t) XED_ISA_SET_RDWRFSGS, (xed_uint16_t) 0 }, +/* RDMSR */ { (xed_uint16_t) XED_ICLASS_RDMSR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PENTIUMREAL, (xed_uint16_t) 0 }, +/* RDPID_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_RDPID, (xed_uint8_t) XED_CATEGORY_RDPID, (xed_uint8_t) XED_EXTENSION_RDPID, (xed_uint16_t) XED_ISA_SET_RDPID, (xed_uint16_t) 0 }, +/* RDPID_GPR64u64 */ { (xed_uint16_t) XED_ICLASS_RDPID, (xed_uint8_t) XED_CATEGORY_RDPID, (xed_uint8_t) XED_EXTENSION_RDPID, (xed_uint16_t) XED_ISA_SET_RDPID, (xed_uint16_t) 0 }, +/* RDPKRU */ { (xed_uint16_t) XED_ICLASS_RDPKRU, (xed_uint8_t) XED_CATEGORY_PKU, (xed_uint8_t) XED_EXTENSION_PKU, (xed_uint16_t) XED_ISA_SET_PKU, (xed_uint16_t) 0 }, +/* RDPMC */ { (xed_uint16_t) XED_ICLASS_RDPMC, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_RDPMC, (xed_uint16_t) 0 }, +/* RDPRU */ { (xed_uint16_t) XED_ICLASS_RDPRU, (xed_uint8_t) XED_CATEGORY_RDPRU, (xed_uint8_t) XED_EXTENSION_RDPRU, (xed_uint16_t) XED_ISA_SET_RDPRU, (xed_uint16_t) 0 }, +/* RDRAND_GPRv */ { (xed_uint16_t) XED_ICLASS_RDRAND, (xed_uint8_t) XED_CATEGORY_RDRAND, (xed_uint8_t)XED_EXTENSION_RDRAND, (xed_uint16_t) XED_ISA_SET_RDRAND, (xed_uint16_t) 0 }, +/* RDSEED_GPRv */ { (xed_uint16_t) XED_ICLASS_RDSEED, (xed_uint8_t) XED_CATEGORY_RDSEED, (xed_uint8_t)XED_EXTENSION_RDSEED, (xed_uint16_t) XED_ISA_SET_RDSEED, (xed_uint16_t) 0 }, +/* RDSSPD_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_RDSSPD, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* RDSSPQ_GPR64u64 */ { (xed_uint16_t) XED_ICLASS_RDSSPQ, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* RDTSC */ { (xed_uint16_t) XED_ICLASS_RDTSC, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PENTIUMREAL, (xed_uint16_t) 0 }, +/* RDTSCP */ { (xed_uint16_t) XED_ICLASS_RDTSCP, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t)XED_EXTENSION_RDTSCP, (xed_uint16_t) XED_ISA_SET_RDTSCP, (xed_uint16_t) 0 }, +/* REPE_CMPSB */ { (xed_uint16_t) XED_ICLASS_REPE_CMPSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 60 }, +/* REPE_CMPSD */ { (xed_uint16_t) XED_ICLASS_REPE_CMPSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 64 }, +/* REPE_CMPSQ */ { (xed_uint16_t) XED_ICLASS_REPE_CMPSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 66 }, +/* REPE_CMPSW */ { (xed_uint16_t) XED_ICLASS_REPE_CMPSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 62 }, +/* REPE_SCASB */ { (xed_uint16_t) XED_ICLASS_REPE_SCASB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 84 }, +/* REPE_SCASD */ { (xed_uint16_t) XED_ICLASS_REPE_SCASD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 88 }, +/* REPE_SCASQ */ { (xed_uint16_t) XED_ICLASS_REPE_SCASQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 90 }, +/* REPE_SCASW */ { (xed_uint16_t) XED_ICLASS_REPE_SCASW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 86 }, +/* REPNE_CMPSB */ { (xed_uint16_t) XED_ICLASS_REPNE_CMPSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 60 }, +/* REPNE_CMPSD */ { (xed_uint16_t) XED_ICLASS_REPNE_CMPSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 64 }, +/* REPNE_CMPSQ */ { (xed_uint16_t) XED_ICLASS_REPNE_CMPSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 66 }, +/* REPNE_CMPSW */ { (xed_uint16_t) XED_ICLASS_REPNE_CMPSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 62 }, +/* REPNE_SCASB */ { (xed_uint16_t) XED_ICLASS_REPNE_SCASB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 84 }, +/* REPNE_SCASD */ { (xed_uint16_t) XED_ICLASS_REPNE_SCASD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 88 }, +/* REPNE_SCASQ */ { (xed_uint16_t) XED_ICLASS_REPNE_SCASQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 90 }, +/* REPNE_SCASW */ { (xed_uint16_t) XED_ICLASS_REPNE_SCASW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 86 }, +/* REP_INSB */ { (xed_uint16_t) XED_ICLASS_REP_INSB, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 38 }, +/* REP_INSD */ { (xed_uint16_t) XED_ICLASS_REP_INSD, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 42 }, +/* REP_INSW */ { (xed_uint16_t) XED_ICLASS_REP_INSW, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 40 }, +/* REP_LODSB */ { (xed_uint16_t) XED_ICLASS_REP_LODSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 76 }, +/* REP_LODSD */ { (xed_uint16_t) XED_ICLASS_REP_LODSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 80 }, +/* REP_LODSQ */ { (xed_uint16_t) XED_ICLASS_REP_LODSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 82 }, +/* REP_LODSW */ { (xed_uint16_t) XED_ICLASS_REP_LODSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 78 }, +/* REP_MONTMUL */ { (xed_uint16_t) XED_ICLASS_REP_MONTMUL, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_MONTMUL, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_MONTMUL, (xed_uint16_t) 128 }, +/* REP_MOVSB */ { (xed_uint16_t) XED_ICLASS_REP_MOVSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 52 }, +/* REP_MOVSD */ { (xed_uint16_t) XED_ICLASS_REP_MOVSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 56 }, +/* REP_MOVSQ */ { (xed_uint16_t) XED_ICLASS_REP_MOVSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 58 }, +/* REP_MOVSW */ { (xed_uint16_t) XED_ICLASS_REP_MOVSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 54 }, +/* REP_OUTSB */ { (xed_uint16_t) XED_ICLASS_REP_OUTSB, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 44 }, +/* REP_OUTSD */ { (xed_uint16_t) XED_ICLASS_REP_OUTSD, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 48 }, +/* REP_OUTSW */ { (xed_uint16_t) XED_ICLASS_REP_OUTSW, (xed_uint8_t) XED_CATEGORY_IOSTRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 46 }, +/* REP_STOSB */ { (xed_uint16_t) XED_ICLASS_REP_STOSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 68 }, +/* REP_STOSD */ { (xed_uint16_t) XED_ICLASS_REP_STOSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 72 }, +/* REP_STOSQ */ { (xed_uint16_t) XED_ICLASS_REP_STOSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 74 }, +/* REP_STOSW */ { (xed_uint16_t) XED_ICLASS_REP_STOSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 70 }, +/* REP_XCRYPTCBC */ { (xed_uint16_t) XED_ICLASS_REP_XCRYPTCBC, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_AES, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_AES, (xed_uint16_t) 116 }, +/* REP_XCRYPTCFB */ { (xed_uint16_t) XED_ICLASS_REP_XCRYPTCFB, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_AES, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_AES, (xed_uint16_t) 120 }, +/* REP_XCRYPTCTR */ { (xed_uint16_t) XED_ICLASS_REP_XCRYPTCTR, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_AES, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_AES, (xed_uint16_t) 118 }, +/* REP_XCRYPTECB */ { (xed_uint16_t) XED_ICLASS_REP_XCRYPTECB, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_AES, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_AES, (xed_uint16_t) 114 }, +/* REP_XCRYPTOFB */ { (xed_uint16_t) XED_ICLASS_REP_XCRYPTOFB, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_AES, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_AES, (xed_uint16_t) 122 }, +/* REP_XSHA1 */ { (xed_uint16_t) XED_ICLASS_REP_XSHA1, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_SHA, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_SHA, (xed_uint16_t) 124 }, +/* REP_XSHA256 */ { (xed_uint16_t) XED_ICLASS_REP_XSHA256, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_SHA, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_SHA, (xed_uint16_t) 126 }, +/* REP_XSTORE */ { (xed_uint16_t) XED_ICLASS_REP_XSTORE, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_RNG, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_RNG, (xed_uint16_t) 112 }, +/* RET_FAR */ { (xed_uint16_t) XED_ICLASS_RET_FAR, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 94 }, +/* RET_FAR_IMMw */ { (xed_uint16_t) XED_ICLASS_RET_FAR, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 94 }, +/* RET_NEAR */ { (xed_uint16_t) XED_ICLASS_RET_NEAR, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 92 }, +/* RET_NEAR_IMMw */ { (xed_uint16_t) XED_ICLASS_RET_NEAR, (xed_uint8_t) XED_CATEGORY_RET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 92 }, +/* RMPADJUST_RAX_RCX_RDX */ { (xed_uint16_t) XED_ICLASS_RMPADJUST, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SNP, (xed_uint16_t) XED_ISA_SET_SNP, (xed_uint16_t) 0 }, +/* RMPUPDATE_RAX_RCX */ { (xed_uint16_t) XED_ICLASS_RMPUPDATE, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SNP, (xed_uint16_t) XED_ISA_SET_SNP, (xed_uint16_t) 0 }, +/* ROL_GPR8_CL */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_GPR8_IMMb */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROL_GPR8_ONE */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROL_GPRv_ONE */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_MEMb_CL */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROL_MEMb_ONE */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_MEMv_CL */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROL_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROL_MEMv_ONE */ { (xed_uint16_t) XED_ICLASS_ROL, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_GPR8_CL */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_GPR8_IMMb */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROR_GPR8_ONE */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROR_GPRv_ONE */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_MEMb_CL */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROR_MEMb_ONE */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_MEMv_CL */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* ROR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* ROR_MEMv_ONE */ { (xed_uint16_t) XED_ICLASS_ROR, (xed_uint8_t) XED_CATEGORY_ROTATE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* RORX_VGPR32d_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_RORX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* RORX_VGPR32d_VGPR32d_IMMb */ { (xed_uint16_t) XED_ICLASS_RORX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* RORX_VGPR64q_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_RORX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* RORX_VGPR64q_VGPR64q_IMMb */ { (xed_uint16_t) XED_ICLASS_RORX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* ROUNDPD_XMMpd_MEMpd_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDPD_XMMpd_XMMpd_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDPS_XMMps_MEMps_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDPS_XMMps_XMMps_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDSD_XMMq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDSD_XMMq_XMMq_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDSS_XMMd_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* ROUNDSS_XMMd_XMMd_IMMb */ { (xed_uint16_t) XED_ICLASS_ROUNDSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE4, (xed_uint16_t) XED_ISA_SET_SSE4, (xed_uint16_t) 0 }, +/* RSM */ { (xed_uint16_t) XED_ICLASS_RSM, (xed_uint8_t) XED_CATEGORY_SYSRET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486, (xed_uint16_t) 0 }, +/* RSQRTPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_RSQRTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RSQRTPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_RSQRTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RSQRTSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_RSQRTSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RSQRTSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_RSQRTSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* RSTORSSP_MEMu64 */ { (xed_uint16_t) XED_ICLASS_RSTORSSP, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* SAHF */ { (xed_uint16_t) XED_ICLASS_SAHF, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_LAHF, (xed_uint16_t) 0 }, +/* SALC */ { (xed_uint16_t) XED_ICLASS_SALC, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_GPR8_CL */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_GPR8_IMMb */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SAR_GPR8_ONE */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SAR_GPRv_ONE */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_MEMb_CL */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SAR_MEMb_ONE */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_MEMv_CL */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SAR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SAR_MEMv_ONE */ { (xed_uint16_t) XED_ICLASS_SAR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SARX_VGPR32d_MEMd_VGPR32d */ { (xed_uint16_t) XED_ICLASS_SARX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SARX_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_SARX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SARX_VGPR64q_MEMq_VGPR64q */ { (xed_uint16_t) XED_ICLASS_SARX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SARX_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_SARX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SAVEPREVSSP */ { (xed_uint16_t) XED_ICLASS_SAVEPREVSSP, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* SBB_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPR8_GPR8_18 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPR8_GPR8_1A */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPR8_IMMb_80r3 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPR8_IMMb_82r3 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPRv_GPRv_19 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPRv_GPRv_1B */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_MEMb_IMMb_80r3 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_MEMb_IMMb_82r3 */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_SBB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SBB_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_SBB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 8 }, +/* SBB_LOCK_MEMb_IMMb_80r3 */ { (xed_uint16_t) XED_ICLASS_SBB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 8 }, +/* SBB_LOCK_MEMb_IMMb_82r3 */ { (xed_uint16_t) XED_ICLASS_SBB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 8 }, +/* SBB_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_SBB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 8 }, +/* SBB_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_SBB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 8 }, +/* SBB_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_SBB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 8 }, +/* SCASB */ { (xed_uint16_t) XED_ICLASS_SCASB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SCASD */ { (xed_uint16_t) XED_ICLASS_SCASD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SCASQ */ { (xed_uint16_t) XED_ICLASS_SCASQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* SCASW */ { (xed_uint16_t) XED_ICLASS_SCASW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SEAMCALL */ { (xed_uint16_t) XED_ICLASS_SEAMCALL, (xed_uint8_t) XED_CATEGORY_LEGACY, (xed_uint8_t) XED_EXTENSION_TDX, (xed_uint16_t) XED_ISA_SET_TDX, (xed_uint16_t) 0 }, +/* SEAMOPS */ { (xed_uint16_t) XED_ICLASS_SEAMOPS, (xed_uint8_t) XED_CATEGORY_LEGACY, (xed_uint8_t) XED_EXTENSION_TDX, (xed_uint16_t) XED_ISA_SET_TDX, (xed_uint16_t) 0 }, +/* SEAMRET */ { (xed_uint16_t) XED_ICLASS_SEAMRET, (xed_uint8_t) XED_CATEGORY_LEGACY, (xed_uint8_t) XED_EXTENSION_TDX, (xed_uint16_t) XED_ISA_SET_TDX, (xed_uint16_t) 0 }, +/* SENDUIPI_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_SENDUIPI, (xed_uint8_t) XED_CATEGORY_UINTR, (xed_uint8_t) XED_EXTENSION_UINTR, (xed_uint16_t) XED_ISA_SET_UINTR, (xed_uint16_t) 0 }, +/* SERIALIZE */ { (xed_uint16_t) XED_ICLASS_SERIALIZE, (xed_uint8_t) XED_CATEGORY_SERIALIZE, (xed_uint8_t)XED_EXTENSION_SERIALIZE, (xed_uint16_t) XED_ISA_SET_SERIALIZE, (xed_uint16_t) 0 }, +/* SETB_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETB, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETB_MEMb */ { (xed_uint16_t) XED_ICLASS_SETB, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETBE_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETBE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETBE_MEMb */ { (xed_uint16_t) XED_ICLASS_SETBE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETL_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETL, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETL_MEMb */ { (xed_uint16_t) XED_ICLASS_SETL, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETLE_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETLE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETLE_MEMb */ { (xed_uint16_t) XED_ICLASS_SETLE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNB_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNB, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNB_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNB, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNBE_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNBE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNBE_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNBE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNL_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNL, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNL_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNL, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNLE_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNLE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNLE_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNLE, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNO_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNO, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNO_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNO, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNP_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNP, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNP_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNP, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNS_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNS, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNS_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNS, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNZ_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETNZ, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETNZ_MEMb */ { (xed_uint16_t) XED_ICLASS_SETNZ, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETO_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETO, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETO_MEMb */ { (xed_uint16_t) XED_ICLASS_SETO, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETP_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETP, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETP_MEMb */ { (xed_uint16_t) XED_ICLASS_SETP, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETS_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETS, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETS_MEMb */ { (xed_uint16_t) XED_ICLASS_SETS, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETSSBSY */ { (xed_uint16_t) XED_ICLASS_SETSSBSY, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* SETZ_GPR8 */ { (xed_uint16_t) XED_ICLASS_SETZ, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SETZ_MEMb */ { (xed_uint16_t) XED_ICLASS_SETZ, (xed_uint8_t) XED_CATEGORY_SETCC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SFENCE */ { (xed_uint16_t) XED_ICLASS_SFENCE, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SGDT_MEMs */ { (xed_uint16_t) XED_ICLASS_SGDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* SGDT_MEMs64 */ { (xed_uint16_t) XED_ICLASS_SGDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* SHA1MSG1_XMMi32_MEMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1MSG1, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1MSG1_XMMi32_XMMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1MSG1, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1MSG2_XMMi32_MEMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1MSG2, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1MSG2_XMMi32_XMMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1MSG2, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1NEXTE_XMMi32_MEMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1NEXTE, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1NEXTE_XMMi32_XMMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1NEXTE, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1RNDS4, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA */ { (xed_uint16_t) XED_ICLASS_SHA1RNDS4, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA256MSG1_XMMi32_MEMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA256MSG1, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA256MSG1_XMMi32_XMMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA256MSG1, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA256MSG2_XMMi32_MEMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA256MSG2, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA256MSG2_XMMi32_XMMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA256MSG2, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA256RNDS2_XMMi32_MEMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA256RNDS2, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHA256RNDS2_XMMi32_XMMi32_SHA */ { (xed_uint16_t) XED_ICLASS_SHA256RNDS2, (xed_uint8_t) XED_CATEGORY_SHA, (xed_uint8_t) XED_EXTENSION_SHA, (xed_uint16_t) XED_ISA_SET_SHA, (xed_uint16_t) 0 }, +/* SHL_GPR8_CL_D2r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPR8_CL_D2r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPR8_IMMb_C0r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_GPR8_IMMb_C0r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_GPR8_ONE_D0r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPR8_ONE_D0r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPRv_CL_D3r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPRv_CL_D3r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPRv_IMMb_C1r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_GPRv_IMMb_C1r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_GPRv_ONE_D1r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_GPRv_ONE_D1r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMb_CL_D2r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMb_CL_D2r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMb_IMMb_C0r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_MEMb_IMMb_C0r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_MEMb_ONE_D0r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMb_ONE_D0r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMv_CL_D3r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMv_CL_D3r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMv_IMMb_C1r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_MEMv_IMMb_C1r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHL_MEMv_ONE_D1r4 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHL_MEMv_ONE_D1r6 */ { (xed_uint16_t) XED_ICLASS_SHL, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHLD_GPRv_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_SHLD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHLD_GPRv_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SHLD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHLD_MEMv_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_SHLD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHLD_MEMv_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SHLD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHLX_VGPR32d_MEMd_VGPR32d */ { (xed_uint16_t) XED_ICLASS_SHLX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHLX_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_SHLX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHLX_VGPR64q_MEMq_VGPR64q */ { (xed_uint16_t) XED_ICLASS_SHLX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHLX_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_SHLX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHR_GPR8_CL */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_GPR8_IMMb */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHR_GPR8_ONE */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHR_GPRv_ONE */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_MEMb_CL */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHR_MEMb_ONE */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_MEMv_CL */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I186, (xed_uint16_t) 0 }, +/* SHR_MEMv_ONE */ { (xed_uint16_t) XED_ICLASS_SHR, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SHRD_GPRv_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_SHRD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHRD_GPRv_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SHRD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHRD_MEMv_GPRv_CL */ { (xed_uint16_t) XED_ICLASS_SHRD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHRD_MEMv_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SHRD, (xed_uint8_t) XED_CATEGORY_SHIFT, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* SHRX_VGPR32d_MEMd_VGPR32d */ { (xed_uint16_t) XED_ICLASS_SHRX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHRX_VGPR32d_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_SHRX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHRX_VGPR64q_MEMq_VGPR64q */ { (xed_uint16_t) XED_ICLASS_SHRX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHRX_VGPR64q_VGPR64q_VGPR64q */ { (xed_uint16_t) XED_ICLASS_SHRX, (xed_uint8_t) XED_CATEGORY_BMI2, (xed_uint8_t) XED_EXTENSION_BMI2, (xed_uint16_t) XED_ISA_SET_BMI2, (xed_uint16_t) 0 }, +/* SHUFPD_XMMpd_MEMpd_IMMb */ { (xed_uint16_t) XED_ICLASS_SHUFPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SHUFPD_XMMpd_XMMpd_IMMb */ { (xed_uint16_t) XED_ICLASS_SHUFPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SHUFPS_XMMps_MEMps_IMMb */ { (xed_uint16_t) XED_ICLASS_SHUFPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SHUFPS_XMMps_XMMps_IMMb */ { (xed_uint16_t) XED_ICLASS_SHUFPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SIDT_MEMs */ { (xed_uint16_t) XED_ICLASS_SIDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* SIDT_MEMs64 */ { (xed_uint16_t) XED_ICLASS_SIDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* SKINIT_EAX */ { (xed_uint16_t) XED_ICLASS_SKINIT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* SLDT_GPRv */ { (xed_uint16_t) XED_ICLASS_SLDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* SLDT_MEMw */ { (xed_uint16_t) XED_ICLASS_SLDT, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* SLWPCB_VGPRyy */ { (xed_uint16_t) XED_ICLASS_SLWPCB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_LWP, (xed_uint16_t) 0 }, +/* SMSW_GPRv */ { (xed_uint16_t) XED_ICLASS_SMSW, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* SMSW_MEMw */ { (xed_uint16_t) XED_ICLASS_SMSW, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I286REAL, (xed_uint16_t) 0 }, +/* SQRTPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_SQRTPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SQRTPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_SQRTPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SQRTPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_SQRTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SQRTPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_SQRTPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SQRTSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_SQRTSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SQRTSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_SQRTSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SQRTSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_SQRTSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SQRTSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_SQRTSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* STAC */ { (xed_uint16_t) XED_ICLASS_STAC, (xed_uint8_t) XED_CATEGORY_SMAP, (xed_uint8_t) XED_EXTENSION_SMAP, (xed_uint16_t) XED_ISA_SET_SMAP, (xed_uint16_t) 0 }, +/* STC */ { (xed_uint16_t) XED_ICLASS_STC, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* STD */ { (xed_uint16_t) XED_ICLASS_STD, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* STGI */ { (xed_uint16_t) XED_ICLASS_STGI, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* STI */ { (xed_uint16_t) XED_ICLASS_STI, (xed_uint8_t) XED_CATEGORY_FLAGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* STMXCSR_MEMd */ { (xed_uint16_t) XED_ICLASS_STMXCSR, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSEMXCSR, (xed_uint16_t) 0 }, +/* STOSB */ { (xed_uint16_t) XED_ICLASS_STOSB, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* STOSD */ { (xed_uint16_t) XED_ICLASS_STOSD, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I386, (xed_uint16_t) 0 }, +/* STOSQ */ { (xed_uint16_t) XED_ICLASS_STOSQ, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* STOSW */ { (xed_uint16_t) XED_ICLASS_STOSW, (xed_uint8_t) XED_CATEGORY_STRINGOP, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* STR_GPRv */ { (xed_uint16_t) XED_ICLASS_STR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* STR_MEMw */ { (xed_uint16_t) XED_ICLASS_STR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* STTILECFG_MEM */ { (xed_uint16_t) XED_ICLASS_STTILECFG, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* STUI */ { (xed_uint16_t) XED_ICLASS_STUI, (xed_uint8_t) XED_CATEGORY_UINTR, (xed_uint8_t) XED_EXTENSION_UINTR, (xed_uint16_t) XED_ISA_SET_UINTR, (xed_uint16_t) 0 }, +/* SUB_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPR8_GPR8_28 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPR8_GPR8_2A */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPR8_IMMb_80r5 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPR8_IMMb_82r5 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPRv_GPRv_29 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPRv_GPRv_2B */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_MEMb_IMMb_80r5 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_MEMb_IMMb_82r5 */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUB_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_SUB, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* SUBPD_XMMpd_MEMpd */ { (xed_uint16_t) XED_ICLASS_SUBPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SUBPD_XMMpd_XMMpd */ { (xed_uint16_t) XED_ICLASS_SUBPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SUBPS_XMMps_MEMps */ { (xed_uint16_t) XED_ICLASS_SUBPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SUBPS_XMMps_XMMps */ { (xed_uint16_t) XED_ICLASS_SUBPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SUBSD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_SUBSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SUBSD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_SUBSD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* SUBSS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_SUBSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SUBSS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_SUBSS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* SUB_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_SUB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 12 }, +/* SUB_LOCK_MEMb_IMMb_80r5 */ { (xed_uint16_t) XED_ICLASS_SUB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 12 }, +/* SUB_LOCK_MEMb_IMMb_82r5 */ { (xed_uint16_t) XED_ICLASS_SUB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 12 }, +/* SUB_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_SUB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 12 }, +/* SUB_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_SUB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 12 }, +/* SUB_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_SUB_LOCK, (xed_uint8_t) XED_CATEGORY_BINARY, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 12 }, +/* SWAPGS */ { (xed_uint16_t) XED_ICLASS_SWAPGS, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* SYSCALL */ { (xed_uint16_t) XED_ICLASS_SYSCALL, (xed_uint8_t) XED_CATEGORY_SYSCALL, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* SYSCALL_AMD */ { (xed_uint16_t) XED_ICLASS_SYSCALL_AMD, (xed_uint8_t) XED_CATEGORY_SYSCALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_AMD, (xed_uint16_t) 130 }, +/* SYSENTER */ { (xed_uint16_t) XED_ICLASS_SYSENTER, (xed_uint8_t) XED_CATEGORY_SYSCALL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* SYSEXIT */ { (xed_uint16_t) XED_ICLASS_SYSEXIT, (xed_uint8_t) XED_CATEGORY_SYSRET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* SYSRET */ { (xed_uint16_t) XED_ICLASS_SYSRET, (xed_uint8_t) XED_CATEGORY_SYSRET, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 0 }, +/* SYSRET64 */ { (xed_uint16_t) XED_ICLASS_SYSRET64, (xed_uint8_t) XED_CATEGORY_SYSRET, (xed_uint8_t)XED_EXTENSION_LONGMODE, (xed_uint16_t) XED_ISA_SET_LONGMODE, (xed_uint16_t) 96 }, +/* SYSRET_AMD */ { (xed_uint16_t) XED_ICLASS_SYSRET_AMD, (xed_uint8_t) XED_CATEGORY_SYSRET, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_AMD, (xed_uint16_t) 96 }, +/* T1MSKC_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_T1MSKC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* T1MSKC_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_T1MSKC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* T1MSKC_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_T1MSKC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* T1MSKC_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_T1MSKC, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* TDCALL */ { (xed_uint16_t) XED_ICLASS_TDCALL, (xed_uint8_t) XED_CATEGORY_LEGACY, (xed_uint8_t) XED_EXTENSION_TDX, (xed_uint16_t) XED_ISA_SET_TDX, (xed_uint16_t) 0 }, +/* TDPBF16PS_TMMf32_TMMu32_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TDPBF16PS, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_BF16, (xed_uint16_t) XED_ISA_SET_AMX_BF16, (xed_uint16_t) 0 }, +/* TDPBSSD_TMMi32_TMMu32_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TDPBSSD, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_INT8, (xed_uint16_t) XED_ISA_SET_AMX_INT8, (xed_uint16_t) 0 }, +/* TDPBSUD_TMMi32_TMMu32_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TDPBSUD, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_INT8, (xed_uint16_t) XED_ISA_SET_AMX_INT8, (xed_uint16_t) 0 }, +/* TDPBUSD_TMMi32_TMMu32_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TDPBUSD, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_INT8, (xed_uint16_t) XED_ISA_SET_AMX_INT8, (xed_uint16_t) 0 }, +/* TDPBUUD_TMMu32_TMMu32_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TDPBUUD, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_INT8, (xed_uint16_t) XED_ISA_SET_AMX_INT8, (xed_uint16_t) 0 }, +/* TEST_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_GPR8_GPR8 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_GPR8_IMMb_F6r0 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_GPR8_IMMb_F6r1 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_GPRv_IMMz_F7r0 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_GPRv_IMMz_F7r1 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_MEMb_IMMb_F6r0 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_MEMb_IMMb_F6r1 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_MEMv_IMMz_F7r0 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_MEMv_IMMz_F7r1 */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TEST_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_TEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* TESTUI */ { (xed_uint16_t) XED_ICLASS_TESTUI, (xed_uint8_t) XED_CATEGORY_UINTR, (xed_uint8_t) XED_EXTENSION_UINTR, (xed_uint16_t) XED_ISA_SET_UINTR, (xed_uint16_t) 0 }, +/* TILELOADD_TMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_TILELOADD, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* TILELOADDT1_TMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_TILELOADDT1, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* TILERELEASE */ { (xed_uint16_t) XED_ICLASS_TILERELEASE, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* TILESTORED_MEMu32_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TILESTORED, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* TILEZERO_TMMu32 */ { (xed_uint16_t) XED_ICLASS_TILEZERO, (xed_uint8_t) XED_CATEGORY_AMX_TILE, (xed_uint8_t)XED_EXTENSION_AMX_TILE, (xed_uint16_t) XED_ISA_SET_AMX_TILE, (xed_uint16_t) 0 }, +/* TLBSYNC */ { (xed_uint16_t) XED_ICLASS_TLBSYNC, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t)XED_EXTENSION_AMD_INVLPGB, (xed_uint16_t) XED_ISA_SET_AMD_INVLPGB, (xed_uint16_t) 0 }, +/* TPAUSE_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_TPAUSE, (xed_uint8_t) XED_CATEGORY_WAITPKG, (xed_uint8_t)XED_EXTENSION_WAITPKG, (xed_uint16_t) XED_ISA_SET_WAITPKG, (xed_uint16_t) 0 }, +/* TZCNT_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_TZCNT, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* TZCNT_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_TZCNT, (xed_uint8_t) XED_CATEGORY_BMI1, (xed_uint8_t) XED_EXTENSION_BMI1, (xed_uint16_t) XED_ISA_SET_BMI1, (xed_uint16_t) 0 }, +/* TZMSK_VGPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_TZMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* TZMSK_VGPR32d_VGPR32d */ { (xed_uint16_t) XED_ICLASS_TZMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* TZMSK_VGPRyy_MEMy */ { (xed_uint16_t) XED_ICLASS_TZMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* TZMSK_VGPRyy_VGPRyy */ { (xed_uint16_t) XED_ICLASS_TZMSK, (xed_uint8_t) XED_CATEGORY_TBM, (xed_uint8_t) XED_EXTENSION_TBM, (xed_uint16_t) XED_ISA_SET_TBM, (xed_uint16_t) 0 }, +/* UCOMISD_XMMsd_MEMsd */ { (xed_uint16_t) XED_ICLASS_UCOMISD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* UCOMISD_XMMsd_XMMsd */ { (xed_uint16_t) XED_ICLASS_UCOMISD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* UCOMISS_XMMss_MEMss */ { (xed_uint16_t) XED_ICLASS_UCOMISS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* UCOMISS_XMMss_XMMss */ { (xed_uint16_t) XED_ICLASS_UCOMISS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* UD0 */ { (xed_uint16_t) XED_ICLASS_UD0, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_PPRO_UD0_SHORT, (xed_uint16_t) 0 }, +/* UD0_GPR32_GPR32 */ { (xed_uint16_t) XED_ICLASS_UD0, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_PPRO_UD0_LONG, (xed_uint16_t) 0 }, +/* UD0_GPR32_MEMd */ { (xed_uint16_t) XED_ICLASS_UD0, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_PPRO_UD0_LONG, (xed_uint16_t) 0 }, +/* UD1_GPR32_GPR32 */ { (xed_uint16_t) XED_ICLASS_UD1, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* UD1_GPR32_MEMd */ { (xed_uint16_t) XED_ICLASS_UD1, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* UD2 */ { (xed_uint16_t) XED_ICLASS_UD2, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PPRO, (xed_uint16_t) 0 }, +/* UIRET */ { (xed_uint16_t) XED_ICLASS_UIRET, (xed_uint8_t) XED_CATEGORY_UINTR, (xed_uint8_t) XED_EXTENSION_UINTR, (xed_uint16_t) XED_ISA_SET_UINTR, (xed_uint16_t) 0 }, +/* UMONITOR_GPRa */ { (xed_uint16_t) XED_ICLASS_UMONITOR, (xed_uint8_t) XED_CATEGORY_WAITPKG, (xed_uint8_t)XED_EXTENSION_WAITPKG, (xed_uint16_t) XED_ISA_SET_WAITPKG, (xed_uint16_t) 0 }, +/* UMWAIT_GPR32 */ { (xed_uint16_t) XED_ICLASS_UMWAIT, (xed_uint8_t) XED_CATEGORY_WAITPKG, (xed_uint8_t)XED_EXTENSION_WAITPKG, (xed_uint16_t) XED_ISA_SET_WAITPKG, (xed_uint16_t) 0 }, +/* UNPCKHPD_XMMpd_MEMdq */ { (xed_uint16_t) XED_ICLASS_UNPCKHPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* UNPCKHPD_XMMpd_XMMq */ { (xed_uint16_t) XED_ICLASS_UNPCKHPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* UNPCKHPS_XMMps_MEMdq */ { (xed_uint16_t) XED_ICLASS_UNPCKHPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* UNPCKHPS_XMMps_XMMdq */ { (xed_uint16_t) XED_ICLASS_UNPCKHPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* UNPCKLPD_XMMpd_MEMdq */ { (xed_uint16_t) XED_ICLASS_UNPCKLPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* UNPCKLPD_XMMpd_XMMq */ { (xed_uint16_t) XED_ICLASS_UNPCKLPD, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* UNPCKLPS_XMMps_MEMdq */ { (xed_uint16_t) XED_ICLASS_UNPCKLPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* UNPCKLPS_XMMps_XMMq */ { (xed_uint16_t) XED_ICLASS_UNPCKLPS, (xed_uint8_t) XED_CATEGORY_SSE, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_V4FMADDPS, (xed_uint8_t) XED_CATEGORY_AVX512_4FMAPS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_4FMAPS_512, (xed_uint16_t) 0 }, +/* V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_V4FMADDSS, (xed_uint8_t) XED_CATEGORY_AVX512_4FMAPS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_4FMAPS_SCALAR, (xed_uint16_t) 0 }, +/* V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_V4FNMADDPS, (xed_uint8_t) XED_CATEGORY_AVX512_4FMAPS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_4FMAPS_512, (xed_uint16_t) 0 }, +/* V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_V4FNMADDSS, (xed_uint8_t) XED_CATEGORY_AVX512_4FMAPS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_4FMAPS_SCALAR, (xed_uint16_t) 0 }, +/* VADDPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VADDPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VADDPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VADDPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VADDSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VADDSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VADDSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VADDSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VADDSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VADDSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VADDSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VADDSUBPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VADDSUBPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VADDSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VAESDEC_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESDEC_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESDEC_XMMu128_XMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESDEC_XMMu128_XMMu128_XMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESDEC_YMMu128_YMMu128_MEMu128 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESDEC_YMMu128_YMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESDEC_YMMu128_YMMu128_YMMu128 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESDEC_YMMu128_YMMu128_YMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDEC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESDECLAST_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESDECLAST_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESDECLAST_YMMu128_YMMu128_MEMu128 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESDECLAST_YMMu128_YMMu128_YMMu128 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESDECLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESENC_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESENC_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESENC_XMMu128_XMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESENC_XMMu128_XMMu128_XMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESENC_YMMu128_YMMu128_MEMu128 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESENC_YMMu128_YMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESENC_YMMu128_YMMu128_YMMu128 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESENC_YMMu128_YMMu128_YMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENC, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESENCLAST_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESENCLAST_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_128, (xed_uint16_t) 0 }, +/* VAESENCLAST_YMMu128_YMMu128_MEMu128 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESENCLAST_YMMu128_YMMu128_YMMu128 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t) XED_EXTENSION_VAES, (xed_uint16_t) XED_ISA_SET_VAES, (xed_uint16_t) 0 }, +/* VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_256, (xed_uint16_t) 0 }, +/* VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512 */ { (xed_uint16_t) XED_ICLASS_VAESENCLAST, (xed_uint8_t) XED_CATEGORY_VAES, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VAES_512, (xed_uint16_t) 0 }, +/* VAESIMC_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VAESIMC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESIMC_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VAESIMC, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESKEYGENASSIST_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VAESKEYGENASSIST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VAESKEYGENASSIST_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VAESKEYGENASSIST, (xed_uint8_t) XED_CATEGORY_AES, (xed_uint8_t)XED_EXTENSION_AVXAES, (xed_uint16_t) XED_ISA_SET_AVXAES, (xed_uint16_t) 0 }, +/* VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGND, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGND, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGND, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGND, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGND, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGND, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGNQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGNQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGNQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGNQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGNQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VALIGNQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VANDNPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDNPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDNPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDNPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDNPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VANDPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VANDPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPS, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPS, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPS, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPS, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPS, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBLENDMPS, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VBLENDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VBLENDVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBROADCASTF128_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF128, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X4, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X4, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF32X8, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF64X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF64X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTF64X4, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTI128_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI128, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X4, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X4, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI32X8, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI64X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI64X2, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTI64X4, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBROADCASTSD_YMMqq_MEMq */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBROADCASTSD_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTSS_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBROADCASTSS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VBROADCASTSS_YMMqq_MEMd */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VBROADCASTSS_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VBROADCASTSS, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCMPPD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPD_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPD_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCMPPS_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPS_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPS_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPPS_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCMPSD_XMMdq_XMMdq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPSD_XMMdq_XMMdq_XMMq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCMPSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCMPSS_XMMdq_XMMdq_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCMPSS_XMMdq_XMMdq_XMMd_IMMb */ { (xed_uint16_t) XED_ICLASS_VCMPSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCOMISD_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMISD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCOMISD_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMISD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCOMISD_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCOMISD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCOMISD_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VCOMISD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCOMISH_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMISH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCOMISH_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMISH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCOMISS_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VCOMISS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCOMISS_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VCOMISS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCOMISS_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMISS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCOMISS_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMISS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPS, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPS, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPS, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPS, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPS, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCOMPRESSPS, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTNE2PS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_128, (xed_uint16_t) 0 }, +/* VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTNE2PS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_128, (xed_uint16_t) 0 }, +/* VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTNE2PS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_256, (xed_uint16_t) 0 }, +/* VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTNE2PS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_256, (xed_uint16_t) 0 }, +/* VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTNE2PS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_512, (xed_uint16_t) 0 }, +/* VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTNE2PS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_512, (xed_uint16_t) 0 }, +/* VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTNEPS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_128, (xed_uint16_t) 0 }, +/* VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTNEPS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_256, (xed_uint16_t) 0 }, +/* VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTNEPS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_128, (xed_uint16_t) 0 }, +/* VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTNEPS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_256, (xed_uint16_t) 0 }, +/* VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTNEPS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_512, (xed_uint16_t) 0 }, +/* VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTNEPS2BF16, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_512, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMdq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMdq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMdq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMdq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2PS_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPH2PS_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPH2PS_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPH2PS_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PSX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PSX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PSX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PSX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PSX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2PSX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2PD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2PD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2PD_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2PD_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2PH_MEMdq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2PH_MEMq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPS2PH_XMMdq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2PH_XMMq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_F16C, (xed_uint16_t) XED_ISA_SET_F16C, (xed_uint16_t) 0 }, +/* VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PHX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PHX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PHX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PHX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PHX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2PHX, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR32d_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR32d_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR32i32_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR32i32_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR64i64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR64i64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSD2SI_GPR64q_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSD2SS_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSD2SS_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2USI_GPR32u32_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2USI_GPR32u32_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2USI_GPR64u64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSD2USI_GPR64u64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SI_GPR32i32_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SI_GPR32i32_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SI_GPR64i64_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SI_GPR64i64_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2USI_GPR32u32_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2USI_GPR32u32_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2USI_GPR64u64_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSH2USI_GPR64u64_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMdq_XMMdq_GPR32d */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMdq_XMMdq_GPR64q */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMdq_XMMdq_GPR32d */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMdq_XMMdq_GPR64q */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SD_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSS2SD_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR32d_XMMd */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR32i32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR32i32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR64i64_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR64i64_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR64q_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSS2SI_GPR64q_XMMd */ { (xed_uint16_t) XED_ICLASS_VCVTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTSS2USI_GPR32u32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2USI_GPR32u32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2USI_GPR64u64_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTSS2USI_GPR64u64_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMdq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMdq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPD2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2UW, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPH2W, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2DQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2QQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UDQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTPS2UQQ, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR32d_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR32d_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR32i32_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR32i32_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR64i64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR64i64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR64q_MEMq */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSD2SI_GPR64q_XMMq */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSD2USI_GPR32u32_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2USI_GPR32u32_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2USI_GPR64u64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSD2USI_GPR64u64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSD2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2SI_GPR32i32_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2SI_GPR32i32_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2SI_GPR64i64_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2SI_GPR64i64_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2USI_GPR32u32_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2USI_GPR32u32_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2USI_GPR64u64_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSH2USI_GPR64u64_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSH2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR32d_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR32d_XMMd */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR32i32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR32i32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR64i64_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR64i64_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR64q_MEMd */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSS2SI_GPR64q_XMMd */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2SI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VCVTTSS2USI_GPR32u32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2USI_GPR32u32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2USI_GPR64u64_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTTSS2USI_GPR64u64_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTTSS2USI, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUDQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VCVTUQQ2PS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SD, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUSI2SS, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTUW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VCVTW2PH, (xed_uint8_t) XED_CATEGORY_CONVERT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDBPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDBPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDBPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDBPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDBPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDBPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VDIVPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VDIVPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VDIVPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VDIVPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VDIVSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VDIVSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VDIVSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VDIVSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VDIVSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VDIVSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDIVSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDPBF16PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_128, (xed_uint16_t) 0 }, +/* VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDPBF16PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_128, (xed_uint16_t) 0 }, +/* VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDPBF16PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_256, (xed_uint16_t) 0 }, +/* VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDPBF16PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_256, (xed_uint16_t) 0 }, +/* VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDPBF16PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_512, (xed_uint16_t) 0 }, +/* VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VDPBF16PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BF16_512, (xed_uint16_t) 0 }, +/* VDPPD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VDPPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDPPD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VDPPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDPPS_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VDPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDPPS_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VDPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDPPS_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VDPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VDPPS_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VDPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VERR_GPR16 */ { (xed_uint16_t) XED_ICLASS_VERR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* VERR_MEMw */ { (xed_uint16_t) XED_ICLASS_VERR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* VERW_GPR16 */ { (xed_uint16_t) XED_ICLASS_VERW, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* VERW_MEMw */ { (xed_uint16_t) XED_ICLASS_VERW, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t)XED_ISA_SET_I286PROTECTED, (xed_uint16_t) 0 }, +/* VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VEXP2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VEXP2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VEXP2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VEXP2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPS, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPS, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPS, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPS, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPS, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXPANDPS, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTF128_MEMdq_YMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF128, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VEXTRACTF128_XMMdq_YMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF128, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTF64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTI128_MEMdq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI128, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VEXTRACTI128_XMMdq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI128, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTI64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VEXTRACTPS_GPR32_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VEXTRACTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VEXTRACTPS_MEMd_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VEXTRACTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VEXTRACTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMADDCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFCMULCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFIXUPIMMSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD132PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD132PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADD132PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD132PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD132SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD132SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD213PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD213PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADD213PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD213PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD213SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD213SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD231PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD231PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADD231PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADD231PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADD231SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD231SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSD_XMMdq_XMMq_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMADDSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSD_XMMdq_XMMq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMADDSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSD_XMMdq_XMMq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMADDSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSS_XMMdq_XMMd_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMADDSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSS_XMMdq_XMMd_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMADDSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSS_XMMdq_XMMd_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMADDSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMADDSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMADDSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUB132PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB132PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUB132PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB132PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB132SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB132SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB213PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB213PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUB213PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB213PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB213SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB213SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB231PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB231PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUB231PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUB231PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUB231SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB231SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMSUBADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBSD_XMMdq_XMMq_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMSUBSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBSD_XMMdq_XMMq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFMSUBSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBSD_XMMdq_XMMq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFMSUBSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBSS_XMMdq_XMMd_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMSUBSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBSS_XMMdq_XMMd_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFMSUBSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMSUBSS_XMMdq_XMMd_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFMSUBSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFMULCSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD132PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD132PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMADD132PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD132PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD132SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD132SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD213PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD213PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMADD213PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD213PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD213SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD213SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD231PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD231PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMADD231PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMADD231PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMADD231SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD231SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMADD231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMADDPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDSD_XMMdq_XMMq_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMADDSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDSD_XMMdq_XMMq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMADDSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDSD_XMMdq_XMMq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMADDSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDSS_XMMdq_XMMd_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMADDSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDSS_XMMdq_XMMd_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMADDSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMADDSS_XMMdq_XMMd_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMADDSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB132SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB132SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB132SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB213SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB213SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB213SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231PS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VFNMSUB231SD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231SD_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SD, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB231SS_XMMdq_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231SS_XMMdq_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t) XED_EXTENSION_FMA, (xed_uint16_t) XED_ISA_SET_FMA, (xed_uint16_t) 0 }, +/* VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFNMSUB231SS, (xed_uint8_t) XED_CATEGORY_VFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBPS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFNMSUBSD, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUBSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUBSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VFNMSUBSS, (xed_uint8_t) XED_CATEGORY_FMA4, (xed_uint8_t) XED_EXTENSION_FMA4, (xed_uint16_t) XED_ISA_SET_FMA4, (xed_uint16_t) 0 }, +/* VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VFPCLASSSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VFRCZPD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFRCZPD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFRCZPD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPD_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFRCZPD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPD_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFRCZPD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VFRCZPS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VFRCZPS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VFRCZPS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZPS_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VFRCZPS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZSD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VFRCZSD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZSD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VFRCZSD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZSS_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VFRCZSS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VFRCZSS_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VFRCZSS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPS, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPS, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERDPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF0DPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF0DPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF0QPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF0QPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF1DPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF1DPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF1QPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERPF1QPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPS, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPS, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VGATHERQPS, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETEXPSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGETMANTSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_128, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_128, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_256, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_256, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_512, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEINVQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_512, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_128, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_128, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_256, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_256, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_512, (xed_uint16_t) 0 }, +/* VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8AFFINEQB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_512, (xed_uint16_t) 0 }, +/* VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_128, (xed_uint16_t) 0 }, +/* VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_128, (xed_uint16_t) 0 }, +/* VGF2P8MULB_XMMu8_XMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8MULB_XMMu8_XMMu8_XMMu8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_256, (xed_uint16_t) 0 }, +/* VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_256, (xed_uint16_t) 0 }, +/* VGF2P8MULB_YMMu8_YMMu8_MEMu8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8MULB_YMMu8_YMMu8_YMMu8 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t) XED_EXTENSION_GFNI, (xed_uint16_t) XED_ISA_SET_AVX_GFNI, (xed_uint16_t) 0 }, +/* VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_512, (xed_uint16_t) 0 }, +/* VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VGF2P8MULB, (xed_uint8_t) XED_CATEGORY_GFNI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_GFNI_512, (xed_uint16_t) 0 }, +/* VHADDPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VHADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VHADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VHADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VHADDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VHADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VHADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VHADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHADDPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VHADDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VHSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VHSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VHSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VHSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VHSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VHSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VHSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VHSUBPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VHSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VINSERTF128, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VINSERTF128, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTF64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VINSERTI128, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VINSERTI128, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI32X8, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTI64X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VINSERTPS_XMMdq_XMMdq_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_VINSERTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VINSERTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VINSERTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VLDDQU_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VLDDQU, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VLDDQU_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VLDDQU, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VLDMXCSR_MEMd */ { (xed_uint16_t) XED_ICLASS_VLDMXCSR, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVDQU_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVDQU, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPD_MEMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPD_MEMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPS_MEMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPS_MEMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMASKMOVPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMASKMOVPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMAXPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VMAXPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMAXPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMAXSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMAXSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMAXSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMAXSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VMAXSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VMAXSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMAXSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMCALL */ { (xed_uint16_t) XED_ICLASS_VMCALL, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMCLEAR_MEMq */ { (xed_uint16_t) XED_ICLASS_VMCLEAR, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMFUNC */ { (xed_uint16_t) XED_ICLASS_VMFUNC, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t)XED_EXTENSION_VMFUNC, (xed_uint16_t) XED_ISA_SET_VMFUNC, (xed_uint16_t) 0 }, +/* VMINPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMINPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VMINPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMINPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMINSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMINSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMINSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMINSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VMINSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VMINSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMINSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMLAUNCH */ { (xed_uint16_t) XED_ICLASS_VMLAUNCH, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMLOAD_ArAX */ { (xed_uint16_t) XED_ICLASS_VMLOAD, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* VMMCALL */ { (xed_uint16_t) XED_ICLASS_VMMCALL, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* VMOVAPD_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVAPD_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_XMMdq_XMMdq_28 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_XMMdq_XMMdq_29 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVAPD_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_YMMqq_YMMqq_28 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_YMMqq_YMMqq_29 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVAPS_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVAPS_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_XMMdq_XMMdq_28 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_XMMdq_XMMdq_29 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVAPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_YMMqq_YMMqq_28 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_YMMqq_YMMqq_29 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVAPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVD_GPR32d_XMMd */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVD_GPR32u32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVD_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVD_MEMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVD_XMMdq_GPR32d */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVD_XMMu32_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVD_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVDDUP_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDDUP_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDDUP_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDDUP_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQA_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_XMMdq_XMMdq_6F */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_XMMdq_XMMdq_7F */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_YMMqq_YMMqq_6F */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA_YMMqq_YMMqq_7F */ { (xed_uint16_t) XED_ICLASS_VMOVDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQA64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_XMMdq_XMMdq_6F */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_XMMdq_XMMdq_7F */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_YMMqq_YMMqq_6F */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU_YMMqq_YMMqq_7F */ { (xed_uint16_t) XED_ICLASS_VMOVDQU, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU16, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU32, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU64, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVDQU8, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VMOVHLPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVHLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVHLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVHPD_MEMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVHPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVHPD_MEMq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVHPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVHPD_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMOVHPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVHPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVHPS_MEMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVHPS_MEMq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVHPS_XMMdq_XMMq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMOVHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVLHPS_XMMdq_XMMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMOVLHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVLHPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVLPD_MEMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVLPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVLPD_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMOVLPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVLPD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMOVLPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVLPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVLPS_MEMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVLPS_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMOVLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVLPS_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMOVLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVLPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVMSKPD_GPR32d_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVMSKPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVMSKPD_GPR32d_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVMSKPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVMSKPS_GPR32d_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVMSKPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVMSKPS_GPR32d_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVMSKPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTDQ_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTDQ_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTDQ_MEMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVNTDQ_MEMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVNTDQ_MEMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVNTDQA_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTDQA_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVNTDQA_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VMOVNTDQA_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVNTDQA_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTDQA, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVNTPD_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVNTPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTPD_MEMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVNTPD_MEMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVNTPD_MEMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVNTPD_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVNTPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTPS_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVNTPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVNTPS_MEMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVNTPS_MEMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVNTPS_MEMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVNTPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVNTPS_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVNTPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_GPR64q_XMMq */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_GPR64u64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVQ_MEMq_XMMq_7E */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_MEMq_XMMq_D6 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_MEMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVQ_XMMdq_GPR64q */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_XMMdq_MEMq_6E */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_XMMdq_MEMq_7E */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_XMMdq_XMMq_7E */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_XMMdq_XMMq_D6 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVQ_XMMu64_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVQ_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVQ_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128N, (xed_uint16_t) 0 }, +/* VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSD_MEMq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSD_XMMdq_XMMdq_XMMq_10 */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSD_XMMdq_XMMdq_XMMq_11 */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSH, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSH, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSH, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSHDUP_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSHDUP_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVSHDUP_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSHDUP_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSHDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVSLDUP_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSLDUP_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVSLDUP_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSLDUP_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSLDUP, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVSS_MEMd_XMMd */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSS_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSS_XMMdq_XMMdq_XMMd_10 */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSS_XMMdq_XMMdq_XMMd_11 */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVSS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMOVUPD_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVUPD_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_XMMdq_XMMdq_10 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_XMMdq_XMMdq_11 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVUPD_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_YMMqq_YMMqq_10 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_YMMqq_YMMqq_11 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVUPS_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVUPS_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_XMMdq_XMMdq_10 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_XMMdq_XMMdq_11 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMOVUPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_YMMqq_YMMqq_10 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_YMMqq_YMMqq_11 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVUPS, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMOVW_GPR32f16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128N, (xed_uint16_t) 0 }, +/* VMOVW_MEMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128N, (xed_uint16_t) 0 }, +/* VMOVW_XMMf16_GPR32f16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128N, (xed_uint16_t) 0 }, +/* VMOVW_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMOVW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128N, (xed_uint16_t) 0 }, +/* VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VMPSADBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VMPSADBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VMPSADBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VMPSADBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VMPTRLD_MEMq */ { (xed_uint16_t) XED_ICLASS_VMPTRLD, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMPTRST_MEMq */ { (xed_uint16_t) XED_ICLASS_VMPTRST, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMREAD_GPR32_GPR32 */ { (xed_uint16_t) XED_ICLASS_VMREAD, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMREAD_GPR64_GPR64 */ { (xed_uint16_t) XED_ICLASS_VMREAD, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMREAD_MEMd_GPR32 */ { (xed_uint16_t) XED_ICLASS_VMREAD, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMREAD_MEMq_GPR64 */ { (xed_uint16_t) XED_ICLASS_VMREAD, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMRESUME */ { (xed_uint16_t) XED_ICLASS_VMRESUME, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMRUN_ArAX */ { (xed_uint16_t) XED_ICLASS_VMRUN, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* VMSAVE */ { (xed_uint16_t) XED_ICLASS_VMSAVE, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_SVM, (xed_uint16_t) XED_ISA_SET_SVM, (xed_uint16_t) 0 }, +/* VMULPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMULPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VMULPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VMULPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VMULSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VMULSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VMULSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VMULSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VMULSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VMULSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VMULSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VMWRITE_GPR32_GPR32 */ { (xed_uint16_t) XED_ICLASS_VMWRITE, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMWRITE_GPR32_MEMd */ { (xed_uint16_t) XED_ICLASS_VMWRITE, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMWRITE_GPR64_GPR64 */ { (xed_uint16_t) XED_ICLASS_VMWRITE, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMWRITE_GPR64_MEMq */ { (xed_uint16_t) XED_ICLASS_VMWRITE, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMXOFF */ { (xed_uint16_t) XED_ICLASS_VMXOFF, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VMXON_MEMq */ { (xed_uint16_t) XED_ICLASS_VMXON, (xed_uint8_t) XED_CATEGORY_VTX, (xed_uint8_t) XED_EXTENSION_VTX, (xed_uint16_t) XED_ISA_SET_VTX, (xed_uint16_t) 0 }, +/* VORPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VORPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VORPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VORPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTD, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_128, (xed_uint16_t) 0 }, +/* VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTD, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_128, (xed_uint16_t) 0 }, +/* VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTD, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_256, (xed_uint16_t) 0 }, +/* VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTD, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_256, (xed_uint16_t) 0 }, +/* VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTD, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_512, (xed_uint16_t) 0 }, +/* VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTD, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_512, (xed_uint16_t) 0 }, +/* VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTQ, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_128, (xed_uint16_t) 0 }, +/* VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTQ, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_128, (xed_uint16_t) 0 }, +/* VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTQ, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_256, (xed_uint16_t) 0 }, +/* VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTQ, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_256, (xed_uint16_t) 0 }, +/* VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTQ, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_512, (xed_uint16_t) 0 }, +/* VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP2INTERSECTQ, (xed_uint8_t) XED_CATEGORY_AVX512_VP2INTERSECT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VP2INTERSECT_512, (xed_uint16_t) 0 }, +/* VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP4DPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512_4VNNIW, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_4VNNIW_512, (xed_uint16_t) 0 }, +/* VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VP4DPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512_4VNNIW, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_4VNNIW_512, (xed_uint16_t) 0 }, +/* VPABSB_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPABSB_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPABSB_XMMi8_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPABSB_XMMi8_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPABSB_YMMi8_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPABSB_YMMi8_MASKmskw_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPABSB_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPABSB_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPABSD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPABSD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPABSD_XMMi32_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPABSD_XMMi32_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPABSD_YMMi32_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPABSD_YMMi32_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPABSD_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPABSD_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPABSW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPABSW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPABSW_XMMi16_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPABSW_XMMi16_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPABSW_YMMi16_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPABSW_YMMi16_MASKmskw_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPABSW_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPABSW_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPABSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKSSDW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKSSDW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKSSDW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKSSDW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKSSWB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKSSWB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKSSWB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKSSWB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKSSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKUSDW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKUSDW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKUSDW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKUSDW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKUSWB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKUSWB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPACKUSWB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKUSWB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPACKUSWB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPADDD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPADDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPADDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPADDSB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDSB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDSB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDSB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDUSB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDUSB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDUSB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDUSB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDUSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDUSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDUSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDUSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPADDW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPADDW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPALIGNR, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPAND_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPAND_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPAND_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPAND_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPAND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDN_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPANDN_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPANDN_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPANDN_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPANDN, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDND, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDNQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDNQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDNQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDNQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDNQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDNQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPANDQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPAVGB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPAVGB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPAVGB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPAVGB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPAVGW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPAVGW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPAVGW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPAVGW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPAVGW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMB, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMB, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMB, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMB, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMB, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMB, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMD, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMQ, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMQ, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMQ, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMQ, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMQ, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMQ, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMW, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMW, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMW, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMW, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMW, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBLENDMW, (xed_uint8_t) XED_CATEGORY_BLEND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPBLENDVB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPBLENDVB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPBLENDVB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPBLENDVB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPBLENDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTB_XMMdq_MEMb */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTB_XMMdq_XMMb */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBROADCASTB_YMMqq_MEMb */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTB_YMMqq_XMMb */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTB, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBROADCASTD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTD_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBROADCASTD_YMMqq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTD_YMMqq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTD, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTMB2Q, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTMB2Q, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTMB2Q, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPBROADCASTMW2D_XMMu32_MASKu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTMW2D, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPBROADCASTMW2D_YMMu32_MASKu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTMW2D, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTMW2D, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_YMMqq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTQ, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPBROADCASTW_XMMdq_MEMw */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTW_XMMdq_XMMw */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPBROADCASTW_YMMqq_MEMw */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTW_YMMqq_XMMw */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPBROADCASTW, (xed_uint8_t) XED_CATEGORY_BROADCAST, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPCLMULQDQ_128, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPCLMULQDQ_128, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_VPCLMULQDQ, (xed_uint16_t) XED_ISA_SET_VPCLMULQDQ, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPCLMULQDQ_256, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_VPCLMULQDQ, (xed_uint16_t) XED_ISA_SET_VPCLMULQDQ, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPCLMULQDQ_256, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPCLMULQDQ_512, (xed_uint16_t) 0 }, +/* VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCLMULQDQ, (xed_uint8_t) XED_CATEGORY_VPCLMULQDQ, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPCLMULQDQ_512, (xed_uint16_t) 0 }, +/* VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMOV, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMOV, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMOV, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMOV, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMOV, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMOV, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPEQB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPEQD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPEQQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPEQW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPEQW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPEQW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPEQW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPESTRI_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRI, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPESTRI_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRI, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPESTRI64_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRI64, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 134 }, +/* VPCMPESTRI64_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRI64, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 134 }, +/* VPCMPESTRM_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRM, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPESTRM_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRM, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPESTRM64_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRM64, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 138 }, +/* VPCMPESTRM64_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPESTRM64, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 138 }, +/* VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPGTB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPGTD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPGTQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPGTW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPGTW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPGTW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPCMPGTW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPCMPISTRI_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPISTRI, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPISTRI_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPISTRI, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPISTRI64_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPISTRI64, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 136 }, +/* VPCMPISTRI64_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPISTRI64, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 136 }, +/* VPCMPISTRM_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPISTRM, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPISTRM_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCMPISTRM, (xed_uint8_t) XED_CATEGORY_STTNI, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCMPW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPCOMB_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMB_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSB, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSB, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSB, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSB, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSB, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSB, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSD, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSQ, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSQ, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSQ, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSQ, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSQ, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSQ, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSW, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSW, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSW, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSW, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSW, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCOMPRESSW, (xed_uint8_t) XED_CATEGORY_COMPRESS, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMUW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMW_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCOMW_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPCOMW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPCONFLICTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPBUSD_XMMi32_XMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSD_XMMi32_XMMu32_XMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPBUSD_YMMi32_YMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSD_YMMi32_YMMu32_YMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPBUSDS_XMMi32_XMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSDS_XMMi32_XMMu32_XMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPBUSDS_YMMi32_YMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSDS_YMMi32_YMMu32_YMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPBUSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPWSSD_XMMi32_XMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSD_XMMi32_XMMu32_XMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPWSSD_YMMi32_YMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSD_YMMi32_YMMu32_YMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_128, (xed_uint16_t) 0 }, +/* VPDPWSSDS_XMMi32_XMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSDS_XMMi32_XMMu32_XMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_256, (xed_uint16_t) 0 }, +/* VPDPWSSDS_YMMi32_YMMu32_MEMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSDS_YMMi32_YMMu32_YMMu32 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_VEX, (xed_uint8_t)XED_EXTENSION_AVX_VNNI, (xed_uint16_t) XED_ISA_SET_AVX_VNNI, (xed_uint16_t) 0 }, +/* VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPDPWSSDS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VNNI_512, (xed_uint16_t) 0 }, +/* VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERM2F128, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERM2F128, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERM2I128, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERM2I128, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPERMD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPERMD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPERMD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMI2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMIL2PS, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMILPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMPD_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMPD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPERMPS, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPERMPS, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMQ_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMQ_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2B, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2D, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2Q, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMT2W, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPERMW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDB, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDB, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDB, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDB, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDB, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDB, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDD, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDQ, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDQ, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDQ, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDQ, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDQ, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDQ, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDW, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDW, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDW, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDW, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDW, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXPANDW, (xed_uint8_t) XED_CATEGORY_EXPAND, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPEXTRB_GPR32d_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPEXTRB_MEMb_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRB_MEMu8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPEXTRD_GPR32d_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPEXTRD_MEMd_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRD_MEMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPEXTRQ_GPR64q_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPEXTRQ_MEMq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPEXTRW_GPR32d_XMMdq_IMMb_15 */ { (xed_uint16_t) XED_ICLASS_VPEXTRW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRW_GPR32d_XMMdq_IMMb_C5 */ { (xed_uint16_t) XED_ICLASS_VPEXTRW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPEXTRW_MEMu16_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPEXTRW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPEXTRW_MEMw_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPEXTRW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5 */ { (xed_uint16_t) XED_ICLASS_VPEXTRW_C5, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 140 }, +/* VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPGATHERDD_XMMu32_MEMd_XMMi32_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPGATHERDD_YMMu32_MEMd_YMMi32_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDQ, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDQ, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDQ, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDQ, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPGATHERDQ, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPGATHERQD_XMMu32_MEMd_XMMi32_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERQD_XMMu32_MEMd_XMMi32_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQD, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQD, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQQ, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQQ, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQQ, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQQ, (xed_uint8_t) XED_CATEGORY_AVX2GATHER, (xed_uint8_t)XED_EXTENSION_AVX2GATHER, (xed_uint16_t) XED_ISA_SET_AVX2GATHER, (xed_uint16_t) 0 }, +/* VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPGATHERQQ, (xed_uint8_t) XED_CATEGORY_GATHER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPHADDBD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDBD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDBD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDBD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDBQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDBQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDBQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDBQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDBW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDBW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDBW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHADDD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHADDD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPHADDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHADDD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPHADDD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHADDDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDDQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDDQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDDQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHADDSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHADDSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPHADDSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHADDSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPHADDSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHADDUBD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUBD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUBD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUBD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUBQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUBQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUBQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUBQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUBW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUBW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUBW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUDQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUDQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUDQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUWD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUWD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUWQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUWQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDUWQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDUWQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHADDW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHADDW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPHADDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHADDW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPHADDW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHADDWD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDWD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDWQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDWQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHADDWQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHADDWQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHMINPOSUW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHMINPOSUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHMINPOSUW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHMINPOSUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBBW_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBBW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHSUBBW_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBBW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHSUBD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPHSUBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHSUBD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPHSUBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHSUBDQ_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBDQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHSUBDQ_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBDQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHSUBSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPHSUBSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHSUBSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPHSUBSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHSUBW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPHSUBW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPHSUBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHSUBW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPHSUBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPHSUBWD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPHSUBWD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPHSUBWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPINSRB_XMMdq_XMMdq_GPR32d_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRB_XMMdq_XMMdq_MEMb_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPINSRD_XMMdq_XMMdq_GPR32d_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRD_XMMdq_XMMdq_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRQ_XMMdq_XMMdq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_128N, (xed_uint16_t) 0 }, +/* VPINSRW_XMMdq_XMMdq_GPR32d_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRW_XMMdq_XMMdq_MEMw_IMMb */ { (xed_uint16_t) XED_ICLASS_VPINSRW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPINSRW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512BW_128N, (xed_uint16_t) 0 }, +/* VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPLZCNTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPLZCNTD, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_128, (xed_uint16_t) 0 }, +/* VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPLZCNTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_256, (xed_uint16_t) 0 }, +/* VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPLZCNTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD */ { (xed_uint16_t) XED_ICLASS_VPLZCNTQ, (xed_uint8_t) XED_CATEGORY_CONFLICT, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512CD_512, (xed_uint16_t) 0 }, +/* VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSDD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSDD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSDQH, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSDQH, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSDQL, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSDQL, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSDD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSDD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSDQH, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSDQH, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSDQL, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSDQL, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSWW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSSWW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSWW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMACSWW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMADCSSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMADCSSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMADCSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMADCSWD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52HUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_128, (xed_uint16_t) 0 }, +/* VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52HUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_128, (xed_uint16_t) 0 }, +/* VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52HUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_256, (xed_uint16_t) 0 }, +/* VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52HUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_256, (xed_uint16_t) 0 }, +/* VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52HUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_512, (xed_uint16_t) 0 }, +/* VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52HUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_512, (xed_uint16_t) 0 }, +/* VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52LUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_128, (xed_uint16_t) 0 }, +/* VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52LUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_128, (xed_uint16_t) 0 }, +/* VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52LUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_256, (xed_uint16_t) 0 }, +/* VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52LUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_256, (xed_uint16_t) 0 }, +/* VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52LUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_512, (xed_uint16_t) 0 }, +/* VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADD52LUQ, (xed_uint8_t) XED_CATEGORY_IFMA, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_IFMA_512, (xed_uint16_t) 0 }, +/* VPMADDUBSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMADDUBSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMADDUBSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMADDUBSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMADDWD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMADDWD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMADDWD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMADDWD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMADDWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMASKMOVD_MEMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVD_MEMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVQ_MEMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVQ_MEMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMASKMOVQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMASKMOVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXSB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXSB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXSD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXSD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXSD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXUB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXUB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXUB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXUB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXUD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXUD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXUD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXUD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMAXUW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXUW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMAXUW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXUW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMAXUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINSB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINSB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINSB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINSB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINSD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINSD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINSD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINSD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINUB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINUB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINUB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINUB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINUD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINUD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINUD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINUD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMINUW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINUW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMINUW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINUW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMINUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVB2M_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVB2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVB2M_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVB2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVB2M_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVB2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVD2M_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVD2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VPMOVD2M_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVD2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VPMOVD2M_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVD2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVM2B_XMMu8_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2B, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVM2B_YMMu8_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2B, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVM2B_ZMMu8_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2B, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVM2D_XMMu32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2D, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VPMOVM2D_YMMu32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2D, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VPMOVM2D_ZMMu32_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2D, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VPMOVM2Q_XMMu64_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2Q, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VPMOVM2Q_YMMu64_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2Q, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VPMOVM2Q_ZMMu64_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2Q, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VPMOVM2W_XMMu16_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2W, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVM2W_YMMu16_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2W, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVM2W_ZMMu16_MASKmskw_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVM2W, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVMSKB_GPR32d_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVMSKB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVMSKB_GPR32d_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMOVMSKB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVQ2M_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQ2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VPMOVQ2M_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQ2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VPMOVQ2M_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQ2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVSXBD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXBD_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXBD_YMMqq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXBD_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_XMMdq_MEMw */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_XMMdq_XMMw */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_YMMqq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_YMMqq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXBW_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXBW_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVSXBW_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXBW_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXWD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXWD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXWD_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXWD_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_YMMqq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVSXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSDW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSQW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVUSWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVW2M_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVW2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVW2M_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVW2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVW2M_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVW2M, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVWB, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVZXBD_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXBD_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXBD_YMMqq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXBD_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_XMMdq_MEMw */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_XMMdq_XMMw */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_YMMqq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_YMMqq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXBW_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXBW_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMOVZXBW_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXBW_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXBW, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXDQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXWD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXWD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXWD_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXWD_YMMqq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWD, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_YMMqq_MEMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMOVZXWQ, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMULDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMULDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMULHRSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULHRSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULHRSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULHRSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHRSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULHUW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULHUW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULHUW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULHUW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHUW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULHW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULHW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULHW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULHW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULLD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULLD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMULLD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULLD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VPMULLW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULLW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPMULLW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULLW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULTISHIFTQB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULTISHIFTQB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_128, (xed_uint16_t) 0 }, +/* VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULTISHIFTQB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULTISHIFTQB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_256, (xed_uint16_t) 0 }, +/* VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULTISHIFTQB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULTISHIFTQB, (xed_uint8_t) XED_CATEGORY_AVX512_VBMI, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI_512, (xed_uint16_t) 0 }, +/* VPMULUDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULUDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPMULUDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULUDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPMULUDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_128, (xed_uint16_t) 0 }, +/* VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_128, (xed_uint16_t) 0 }, +/* VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_256, (xed_uint16_t) 0 }, +/* VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_256, (xed_uint16_t) 0 }, +/* VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTB, (xed_uint8_t) XED_CATEGORY_AVX512_BITALG, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_512, (xed_uint16_t) 0 }, +/* VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTB, (xed_uint8_t) XED_CATEGORY_AVX512_BITALG, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_512, (xed_uint16_t) 0 }, +/* VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_128, (xed_uint16_t) 0 }, +/* VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_128, (xed_uint16_t) 0 }, +/* VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_256, (xed_uint16_t) 0 }, +/* VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_256, (xed_uint16_t) 0 }, +/* VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_512, (xed_uint16_t) 0 }, +/* VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_512, (xed_uint16_t) 0 }, +/* VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_128, (xed_uint16_t) 0 }, +/* VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_128, (xed_uint16_t) 0 }, +/* VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_256, (xed_uint16_t) 0 }, +/* VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_256, (xed_uint16_t) 0 }, +/* VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_512, (xed_uint16_t) 0 }, +/* VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VPOPCNTDQ_512, (xed_uint16_t) 0 }, +/* VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_128, (xed_uint16_t) 0 }, +/* VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_128, (xed_uint16_t) 0 }, +/* VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_256, (xed_uint16_t) 0 }, +/* VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_256, (xed_uint16_t) 0 }, +/* VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTW, (xed_uint8_t) XED_CATEGORY_AVX512_BITALG, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_512, (xed_uint16_t) 0 }, +/* VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPOPCNTW, (xed_uint8_t) XED_CATEGORY_AVX512_BITALG, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_512, (xed_uint16_t) 0 }, +/* VPOR_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPOR_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPOR_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPOR_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPPERM_XMMdq_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPPERM, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPPERM_XMMdq_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPPERM, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPPERM_XMMdq_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPPERM, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPROLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPRORVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPROTB_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTB_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTB_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPROTB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTD_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPROTD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTQ_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTQ_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTQ_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPROTQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTW_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPROTW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPROTW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPROTW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPROTW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSADBW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSADBW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSADBW_XMMu16_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSADBW_XMMu16_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSADBW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSADBW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSADBW_YMMu16_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSADBW_YMMu16_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSADBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERDD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERDD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERDD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERDQ, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERDQ, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERDQ, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERQD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERQD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERQD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERQQ, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERQQ, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VPSCATTERQQ, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSHAB_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAD_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAQ_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAW_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHAW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHAW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLB_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLB, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLD_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLD, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHLDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHLQ_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLQ, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLW_XMMdq_MEMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHLW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHLW, (xed_uint8_t) XED_CATEGORY_XOP, (xed_uint8_t) XED_EXTENSION_XOP, (xed_uint16_t) XED_ISA_SET_XOP, (xed_uint16_t) 0 }, +/* VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVD, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVQ, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDVW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_128, (xed_uint16_t) 0 }, +/* VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_256, (xed_uint16_t) 0 }, +/* VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHRDW, (xed_uint8_t) XED_CATEGORY_VBMI2, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_VBMI2_512, (xed_uint16_t) 0 }, +/* VPSHUFB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSHUFB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFBITQMB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_128, (xed_uint16_t) 0 }, +/* VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFBITQMB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_128, (xed_uint16_t) 0 }, +/* VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFBITQMB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_256, (xed_uint16_t) 0 }, +/* VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFBITQMB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_256, (xed_uint16_t) 0 }, +/* VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFBITQMB, (xed_uint8_t) XED_CATEGORY_AVX512_BITALG, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_512, (xed_uint16_t) 0 }, +/* VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFBITQMB, (xed_uint8_t) XED_CATEGORY_AVX512_BITALG, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_BITALG_512, (xed_uint16_t) 0 }, +/* VPSHUFD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSHUFD_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSHUFHW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFHW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSHUFHW_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFHW_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFHW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSHUFLW_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFLW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSHUFLW_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFLW_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSHUFLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSIGNB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSIGNB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSIGNB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSIGNB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSIGNB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSIGNB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSIGNB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSIGNB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSIGND_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSIGND, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSIGND_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSIGND, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSIGND_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSIGND, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSIGND_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSIGND, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSIGNW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSIGNW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSIGNW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSIGNW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSIGNW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSIGNW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSIGNW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSIGNW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLD_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLD_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLDQ_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLDQ_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLVD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLVD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLVQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSLLVQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSLLW_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLW_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLW_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSLLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRAD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRAD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRAD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAD_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAD_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAVD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAVD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAVD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAVD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRAW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRAW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRAW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRAW_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAW_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAW_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRAW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLD_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLD_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLDQ_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLDQ_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLVD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLVD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLVQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSRLVQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLVW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLW_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSRLW_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLW_YMMqq_YMMqq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLW_YMMqq_YMMqq_XMMq */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSRLW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSUBD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSUBQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPSUBQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPSUBSB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBSB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBSB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBSB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBUSB_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBUSB_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBUSB_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBUSB_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSB, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBUSW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBUSW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBUSW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBUSW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBUSW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPSUBW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPSUBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTERNLOGQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTEST_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPTEST_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPTEST_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPTEST_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMB, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPTESTNMW, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKHWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLBW, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLQDQ, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_128, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX2, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_256, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPUNPCKLWD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512BW_512, (xed_uint16_t) 0 }, +/* VPXOR_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VPXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPXOR_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VPXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VPXOR_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VPXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPXOR_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VPXOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_AVX2, (xed_uint16_t) XED_ISA_SET_AVX2, (xed_uint16_t) 0 }, +/* VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORD, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VPXORQ, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGESD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGESD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGESS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRANGESS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCP14SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRCP28SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VRCPPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VRCPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRCPPS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VRCPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRCPPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VRCPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRCPPS_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VRCPPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRCPSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VRCPSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VRCPSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRCPSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VRCPSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCESD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCESD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCESH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCESH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCESS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VREDUCESS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512DQ_SCALAR, (xed_uint16_t) 0 }, +/* VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALEPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALESD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALESD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALESH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALESH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALESS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRNDSCALESS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VROUNDPD_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPD_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPD_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPD_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPS_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPS_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPS_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDPS_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDSD_XMMdq_XMMdq_MEMq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDSD_XMMdq_XMMdq_XMMq_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDSS_XMMdq_XMMdq_MEMd_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VROUNDSS_XMMdq_XMMdq_XMMd_IMMb */ { (xed_uint16_t) XED_ICLASS_VROUNDSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRT14SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28PD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28PS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512ER_512, (xed_uint16_t) 0 }, +/* VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28SD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER */ { (xed_uint16_t) XED_ICLASS_VRSQRT28SS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512ER_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VRSQRTPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VRSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRSQRTPS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VRSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRSQRTPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VRSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRSQRTPS_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VRSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VRSQRTSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VRSQRTSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VRSQRTSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VRSQRTSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VRSQRTSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSCALEFSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VSCATTERDPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VSCATTERDPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERDPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VSCATTERDPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VSCATTERDPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERDPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF0DPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF0DPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF0QPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF0QPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF1DPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF1DPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF1QPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERPF1QPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512PF_512, (xed_uint16_t) 0 }, +/* VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VSCATTERQPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VSCATTERQPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERQPD, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128 */ { (xed_uint16_t) XED_ICLASS_VSCATTERQPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256 */ { (xed_uint16_t) XED_ICLASS_VSCATTERQPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512 */ { (xed_uint16_t) XED_ICLASS_VSCATTERQPS, (xed_uint8_t) XED_CATEGORY_SCATTER, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFF64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI32X4, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFI64X2, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSHUFPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSQRTPD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSQRTPD_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPD_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VSQRTPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSQRTPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPS_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSQRTSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VSQRTSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VSQRTSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VSQRTSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VSQRTSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VSQRTSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSQRTSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSTMXCSR_MEMd */ { (xed_uint16_t) XED_ICLASS_VSTMXCSR, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSUBPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_128, (xed_uint16_t) 0 }, +/* VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_256, (xed_uint16_t) 0 }, +/* VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_512, (xed_uint16_t) 0 }, +/* VSUBPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VSUBPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VSUBSD_XMMdq_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VSUBSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBSD_XMMdq_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VSUBSD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBSD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBSH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VSUBSS_XMMdq_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VSUBSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBSS_XMMdq_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VSUBSS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VSUBSS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VTESTPD_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VTESTPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPD_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VTESTPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPD_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VTESTPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPD_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VTESTPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPS_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VTESTPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPS_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VTESTPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPS_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VTESTPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VTESTPS_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VTESTPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUCOMISD_XMMdq_MEMq */ { (xed_uint16_t) XED_ICLASS_VUCOMISD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUCOMISD_XMMdq_XMMq */ { (xed_uint16_t) XED_ICLASS_VUCOMISD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUCOMISD_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUCOMISD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VUCOMISD_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUCOMISD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VUCOMISH_XMMf16_MEMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUCOMISH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VUCOMISH_XMMf16_XMMf16_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUCOMISH, (xed_uint8_t) XED_CATEGORY_FP16, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512_FP16_SCALAR, (xed_uint16_t) 0 }, +/* VUCOMISS_XMMdq_MEMd */ { (xed_uint16_t) XED_ICLASS_VUCOMISS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUCOMISS_XMMdq_XMMd */ { (xed_uint16_t) XED_ICLASS_VUCOMISS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUCOMISS_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUCOMISS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VUCOMISS_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUCOMISS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t)XED_ISA_SET_AVX512F_SCALAR, (xed_uint16_t) 0 }, +/* VUNPCKHPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKHPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKHPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKHPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKHPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKLPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKLPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPD, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKLPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_128, (xed_uint16_t) 0 }, +/* VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_256, (xed_uint16_t) 0 }, +/* VUNPCKLPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VUNPCKLPS, (xed_uint8_t) XED_CATEGORY_AVX512, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512F_512, (xed_uint16_t) 0 }, +/* VXORPD_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPD_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VXORPD_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPD_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VXORPS_XMMdq_XMMdq_MEMdq */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPS_XMMdq_XMMdq_XMMdq */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_128, (xed_uint16_t) 0 }, +/* VXORPS_YMMqq_YMMqq_MEMqq */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPS_YMMqq_YMMqq_YMMqq */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_256, (xed_uint16_t) 0 }, +/* VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512 */ { (xed_uint16_t) XED_ICLASS_VXORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t)XED_EXTENSION_AVX512EVEX, (xed_uint16_t) XED_ISA_SET_AVX512DQ_512, (xed_uint16_t) 0 }, +/* VZEROALL */ { (xed_uint16_t) XED_ICLASS_VZEROALL, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* VZEROUPPER */ { (xed_uint16_t) XED_ICLASS_VZEROUPPER, (xed_uint8_t) XED_CATEGORY_AVX, (xed_uint8_t) XED_EXTENSION_AVX, (xed_uint16_t) XED_ISA_SET_AVX, (xed_uint16_t) 0 }, +/* WBINVD */ { (xed_uint16_t) XED_ICLASS_WBINVD, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* WBNOINVD */ { (xed_uint16_t) XED_ICLASS_WBNOINVD, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t)XED_EXTENSION_WBNOINVD, (xed_uint16_t) XED_ISA_SET_WBNOINVD, (xed_uint16_t) 0 }, +/* WRFSBASE_GPRy */ { (xed_uint16_t) XED_ICLASS_WRFSBASE, (xed_uint8_t) XED_CATEGORY_RDWRFSGS, (xed_uint8_t)XED_EXTENSION_RDWRFSGS, (xed_uint16_t) XED_ISA_SET_RDWRFSGS, (xed_uint16_t) 0 }, +/* WRGSBASE_GPRy */ { (xed_uint16_t) XED_ICLASS_WRGSBASE, (xed_uint8_t) XED_CATEGORY_RDWRFSGS, (xed_uint8_t)XED_EXTENSION_RDWRFSGS, (xed_uint16_t) XED_ISA_SET_RDWRFSGS, (xed_uint16_t) 0 }, +/* WRMSR */ { (xed_uint16_t) XED_ICLASS_WRMSR, (xed_uint8_t) XED_CATEGORY_SYSTEM, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_PENTIUMREAL, (xed_uint16_t) 0 }, +/* WRPKRU */ { (xed_uint16_t) XED_ICLASS_WRPKRU, (xed_uint8_t) XED_CATEGORY_PKU, (xed_uint8_t) XED_EXTENSION_PKU, (xed_uint16_t) XED_ISA_SET_PKU, (xed_uint16_t) 0 }, +/* WRSSD_MEMu32_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_WRSSD, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* WRSSQ_MEMu64_GPR64u64 */ { (xed_uint16_t) XED_ICLASS_WRSSQ, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* WRUSSD_MEMu32_GPR32u32 */ { (xed_uint16_t) XED_ICLASS_WRUSSD, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* WRUSSQ_MEMu64_GPR64u64 */ { (xed_uint16_t) XED_ICLASS_WRUSSQ, (xed_uint8_t) XED_CATEGORY_CET, (xed_uint8_t) XED_EXTENSION_CET, (xed_uint16_t) XED_ISA_SET_CET, (xed_uint16_t) 0 }, +/* XABORT_IMMb */ { (xed_uint16_t) XED_ICLASS_XABORT, (xed_uint8_t) XED_CATEGORY_UNCOND_BR, (xed_uint8_t) XED_EXTENSION_RTM, (xed_uint16_t) XED_ISA_SET_RTM, (xed_uint16_t) 0 }, +/* XADD_GPR8_GPR8 */ { (xed_uint16_t) XED_ICLASS_XADD, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* XADD_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_XADD, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* XADD_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_XADD, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* XADD_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_XADD, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 0 }, +/* XADD_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_XADD_LOCK, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 102 }, +/* XADD_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_XADD_LOCK, (xed_uint8_t) XED_CATEGORY_SEMAPHORE, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I486REAL, (xed_uint16_t) 102 }, +/* XBEGIN_RELBRz */ { (xed_uint16_t) XED_ICLASS_XBEGIN, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_RTM, (xed_uint16_t) XED_ISA_SET_RTM, (xed_uint16_t) 0 }, +/* XCHG_GPR8_GPR8 */ { (xed_uint16_t) XED_ICLASS_XCHG, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XCHG_GPRv_GPRv */ { (xed_uint16_t) XED_ICLASS_XCHG, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XCHG_GPRv_OrAX */ { (xed_uint16_t) XED_ICLASS_XCHG, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XCHG_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_XCHG, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XCHG_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_XCHG, (xed_uint8_t) XED_CATEGORY_DATAXFER, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XEND */ { (xed_uint16_t) XED_ICLASS_XEND, (xed_uint8_t) XED_CATEGORY_COND_BR, (xed_uint8_t) XED_EXTENSION_RTM, (xed_uint16_t) XED_ISA_SET_RTM, (xed_uint16_t) 0 }, +/* XGETBV */ { (xed_uint16_t) XED_ICLASS_XGETBV, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t) XED_EXTENSION_XSAVE, (xed_uint16_t) XED_ISA_SET_XSAVE, (xed_uint16_t) 0 }, +/* XLAT */ { (xed_uint16_t) XED_ICLASS_XLAT, (xed_uint8_t) XED_CATEGORY_MISC, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_AL_IMMb */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPR8_GPR8_30 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPR8_GPR8_32 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPR8_IMMb_80r6 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPR8_IMMb_82r6 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPR8_MEMb */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPRv_GPRv_31 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPRv_GPRv_33 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPRv_IMMb */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPRv_IMMz */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_GPRv_MEMv */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_MEMb_IMMb_80r6 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_MEMb_IMMb_82r6 */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XOR_OrAX_IMMz */ { (xed_uint16_t) XED_ICLASS_XOR, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 0 }, +/* XORPD_XMMxuq_MEMxuq */ { (xed_uint16_t) XED_ICLASS_XORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* XORPD_XMMxuq_XMMxuq */ { (xed_uint16_t) XED_ICLASS_XORPD, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE2, (xed_uint16_t) XED_ISA_SET_SSE2, (xed_uint16_t) 0 }, +/* XORPS_XMMxud_MEMxud */ { (xed_uint16_t) XED_ICLASS_XORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* XORPS_XMMxud_XMMxud */ { (xed_uint16_t) XED_ICLASS_XORPS, (xed_uint8_t) XED_CATEGORY_LOGICAL_FP, (xed_uint8_t) XED_EXTENSION_SSE, (xed_uint16_t) XED_ISA_SET_SSE, (xed_uint16_t) 0 }, +/* XOR_LOCK_MEMb_GPR8 */ { (xed_uint16_t) XED_ICLASS_XOR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 14 }, +/* XOR_LOCK_MEMb_IMMb_80r6 */ { (xed_uint16_t) XED_ICLASS_XOR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 14 }, +/* XOR_LOCK_MEMb_IMMb_82r6 */ { (xed_uint16_t) XED_ICLASS_XOR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 14 }, +/* XOR_LOCK_MEMv_GPRv */ { (xed_uint16_t) XED_ICLASS_XOR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 14 }, +/* XOR_LOCK_MEMv_IMMb */ { (xed_uint16_t) XED_ICLASS_XOR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 14 }, +/* XOR_LOCK_MEMv_IMMz */ { (xed_uint16_t) XED_ICLASS_XOR_LOCK, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_BASE, (xed_uint16_t) XED_ISA_SET_I86, (xed_uint16_t) 14 }, +/* XRESLDTRK */ { (xed_uint16_t) XED_ICLASS_XRESLDTRK, (xed_uint8_t) XED_CATEGORY_TSX_LDTRK, (xed_uint8_t)XED_EXTENSION_TSX_LDTRK, (xed_uint16_t) XED_ISA_SET_TSX_LDTRK, (xed_uint16_t) 0 }, +/* XRSTOR_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XRSTOR, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t) XED_EXTENSION_XSAVE, (xed_uint16_t) XED_ISA_SET_XSAVE, (xed_uint16_t) 0 }, +/* XRSTOR64_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XRSTOR64, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t) XED_EXTENSION_XSAVE, (xed_uint16_t) XED_ISA_SET_XSAVE, (xed_uint16_t) 0 }, +/* XRSTORS_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XRSTORS, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t)XED_EXTENSION_XSAVES, (xed_uint16_t) XED_ISA_SET_XSAVES, (xed_uint16_t) 0 }, +/* XRSTORS64_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XRSTORS64, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t)XED_EXTENSION_XSAVES, (xed_uint16_t) XED_ISA_SET_XSAVES, (xed_uint16_t) 0 }, +/* XSAVE_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVE, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t) XED_EXTENSION_XSAVE, (xed_uint16_t) XED_ISA_SET_XSAVE, (xed_uint16_t) 0 }, +/* XSAVE64_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVE64, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t) XED_EXTENSION_XSAVE, (xed_uint16_t) XED_ISA_SET_XSAVE, (xed_uint16_t) 0 }, +/* XSAVEC_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVEC, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t)XED_EXTENSION_XSAVEC, (xed_uint16_t) XED_ISA_SET_XSAVEC, (xed_uint16_t) 0 }, +/* XSAVEC64_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVEC64, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t)XED_EXTENSION_XSAVEC, (xed_uint16_t) XED_ISA_SET_XSAVEC, (xed_uint16_t) 0 }, +/* XSAVEOPT_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVEOPT, (xed_uint8_t) XED_CATEGORY_XSAVEOPT, (xed_uint8_t)XED_EXTENSION_XSAVEOPT, (xed_uint16_t) XED_ISA_SET_XSAVEOPT, (xed_uint16_t) 0 }, +/* XSAVEOPT64_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVEOPT64, (xed_uint8_t) XED_CATEGORY_XSAVEOPT, (xed_uint8_t)XED_EXTENSION_XSAVEOPT, (xed_uint16_t) XED_ISA_SET_XSAVEOPT, (xed_uint16_t) 0 }, +/* XSAVES_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVES, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t)XED_EXTENSION_XSAVES, (xed_uint16_t) XED_ISA_SET_XSAVES, (xed_uint16_t) 0 }, +/* XSAVES64_MEMmxsave */ { (xed_uint16_t) XED_ICLASS_XSAVES64, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t)XED_EXTENSION_XSAVES, (xed_uint16_t) XED_ISA_SET_XSAVES, (xed_uint16_t) 0 }, +/* XSETBV */ { (xed_uint16_t) XED_ICLASS_XSETBV, (xed_uint8_t) XED_CATEGORY_XSAVE, (xed_uint8_t) XED_EXTENSION_XSAVE, (xed_uint16_t) XED_ISA_SET_XSAVE, (xed_uint16_t) 0 }, +/* XSTORE */ { (xed_uint16_t) XED_ICLASS_XSTORE, (xed_uint8_t) XED_CATEGORY_VIA_PADLOCK, (xed_uint8_t)XED_EXTENSION_VIA_PADLOCK_RNG, (xed_uint16_t)XED_ISA_SET_VIA_PADLOCK_RNG, (xed_uint16_t) 0 }, +/* XSUSLDTRK */ { (xed_uint16_t) XED_ICLASS_XSUSLDTRK, (xed_uint8_t) XED_CATEGORY_TSX_LDTRK, (xed_uint8_t)XED_EXTENSION_TSX_LDTRK, (xed_uint16_t) XED_ISA_SET_TSX_LDTRK, (xed_uint16_t) 0 }, +/* XTEST */ { (xed_uint16_t) XED_ICLASS_XTEST, (xed_uint8_t) XED_CATEGORY_LOGICAL, (xed_uint8_t) XED_EXTENSION_RTM, (xed_uint16_t) XED_ISA_SET_RTM, (xed_uint16_t) 0 } +}; diff --git a/CodeVirtualizer/build/obj/xed-iform-max.c b/CodeVirtualizer/build/obj/xed-iform-max.c new file mode 100644 index 0000000..cbd1775 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iform-max.c @@ -0,0 +1,3515 @@ +/// @file xed-iform-max.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +const xed_uint32_t xed_iform_max_per_iclass_table[XED_ICLASS_LAST] = { + /* INVALID */ 0, + /* AAA */ 1, + /* AAD */ 1, + /* AAM */ 1, + /* AAS */ 1, + /* ADC */ 18, + /* ADCX */ 4, + /* ADC_LOCK */ 6, + /* ADD */ 18, + /* ADDPD */ 2, + /* ADDPS */ 2, + /* ADDSD */ 2, + /* ADDSS */ 2, + /* ADDSUBPD */ 2, + /* ADDSUBPS */ 2, + /* ADD_LOCK */ 6, + /* ADOX */ 4, + /* AESDEC */ 2, + /* AESDEC128KL */ 1, + /* AESDEC256KL */ 1, + /* AESDECLAST */ 2, + /* AESDECWIDE128KL */ 1, + /* AESDECWIDE256KL */ 1, + /* AESENC */ 2, + /* AESENC128KL */ 1, + /* AESENC256KL */ 1, + /* AESENCLAST */ 2, + /* AESENCWIDE128KL */ 1, + /* AESENCWIDE256KL */ 1, + /* AESIMC */ 2, + /* AESKEYGENASSIST */ 2, + /* AND */ 18, + /* ANDN */ 4, + /* ANDNPD */ 2, + /* ANDNPS */ 2, + /* ANDPD */ 2, + /* ANDPS */ 2, + /* AND_LOCK */ 6, + /* ARPL */ 2, + /* BEXTR */ 4, + /* BEXTR_XOP */ 4, + /* BLCFILL */ 4, + /* BLCI */ 4, + /* BLCIC */ 4, + /* BLCMSK */ 4, + /* BLCS */ 4, + /* BLENDPD */ 2, + /* BLENDPS */ 2, + /* BLENDVPD */ 2, + /* BLENDVPS */ 2, + /* BLSFILL */ 4, + /* BLSI */ 4, + /* BLSIC */ 4, + /* BLSMSK */ 4, + /* BLSR */ 4, + /* BNDCL */ 3, + /* BNDCN */ 3, + /* BNDCU */ 3, + /* BNDLDX */ 2, + /* BNDMK */ 1, + /* BNDMOV */ 5, + /* BNDSTX */ 2, + /* BOUND */ 2, + /* BSF */ 2, + /* BSR */ 2, + /* BSWAP */ 1, + /* BT */ 4, + /* BTC */ 4, + /* BTC_LOCK */ 2, + /* BTR */ 4, + /* BTR_LOCK */ 2, + /* BTS */ 4, + /* BTS_LOCK */ 2, + /* BZHI */ 4, + /* CALL_FAR */ 2, + /* CALL_NEAR */ 4, + /* CBW */ 1, + /* CDQ */ 1, + /* CDQE */ 1, + /* CLAC */ 1, + /* CLC */ 1, + /* CLD */ 1, + /* CLDEMOTE */ 1, + /* CLFLUSH */ 1, + /* CLFLUSHOPT */ 1, + /* CLGI */ 1, + /* CLI */ 1, + /* CLRSSBSY */ 1, + /* CLTS */ 1, + /* CLUI */ 1, + /* CLWB */ 1, + /* CLZERO */ 1, + /* CMC */ 1, + /* CMOVB */ 2, + /* CMOVBE */ 2, + /* CMOVL */ 2, + /* CMOVLE */ 2, + /* CMOVNB */ 2, + /* CMOVNBE */ 2, + /* CMOVNL */ 2, + /* CMOVNLE */ 2, + /* CMOVNO */ 2, + /* CMOVNP */ 2, + /* CMOVNS */ 2, + /* CMOVNZ */ 2, + /* CMOVO */ 2, + /* CMOVP */ 2, + /* CMOVS */ 2, + /* CMOVZ */ 2, + /* CMP */ 18, + /* CMPPD */ 2, + /* CMPPS */ 2, + /* CMPSB */ 1, + /* CMPSD */ 1, + /* CMPSD_XMM */ 2, + /* CMPSQ */ 1, + /* CMPSS */ 2, + /* CMPSW */ 1, + /* CMPXCHG */ 4, + /* CMPXCHG16B */ 1, + /* CMPXCHG16B_LOCK */ 1, + /* CMPXCHG8B */ 1, + /* CMPXCHG8B_LOCK */ 1, + /* CMPXCHG_LOCK */ 2, + /* COMISD */ 2, + /* COMISS */ 2, + /* CPUID */ 1, + /* CQO */ 1, + /* CRC32 */ 4, + /* CVTDQ2PD */ 2, + /* CVTDQ2PS */ 2, + /* CVTPD2DQ */ 2, + /* CVTPD2PI */ 2, + /* CVTPD2PS */ 2, + /* CVTPI2PD */ 2, + /* CVTPI2PS */ 2, + /* CVTPS2DQ */ 2, + /* CVTPS2PD */ 2, + /* CVTPS2PI */ 2, + /* CVTSD2SI */ 4, + /* CVTSD2SS */ 2, + /* CVTSI2SD */ 4, + /* CVTSI2SS */ 4, + /* CVTSS2SD */ 2, + /* CVTSS2SI */ 4, + /* CVTTPD2DQ */ 2, + /* CVTTPD2PI */ 2, + /* CVTTPS2DQ */ 2, + /* CVTTPS2PI */ 2, + /* CVTTSD2SI */ 4, + /* CVTTSS2SI */ 4, + /* CWD */ 1, + /* CWDE */ 1, + /* DAA */ 1, + /* DAS */ 1, + /* DEC */ 5, + /* DEC_LOCK */ 2, + /* DIV */ 4, + /* DIVPD */ 2, + /* DIVPS */ 2, + /* DIVSD */ 2, + /* DIVSS */ 2, + /* DPPD */ 2, + /* DPPS */ 2, + /* EMMS */ 1, + /* ENCLS */ 1, + /* ENCLU */ 1, + /* ENCLV */ 1, + /* ENCODEKEY128 */ 1, + /* ENCODEKEY256 */ 1, + /* ENDBR32 */ 1, + /* ENDBR64 */ 1, + /* ENQCMD */ 1, + /* ENQCMDS */ 1, + /* ENTER */ 1, + /* EXTRACTPS */ 2, + /* EXTRQ */ 2, + /* F2XM1 */ 1, + /* FABS */ 1, + /* FADD */ 4, + /* FADDP */ 1, + /* FBLD */ 1, + /* FBSTP */ 1, + /* FCHS */ 1, + /* FCMOVB */ 1, + /* FCMOVBE */ 1, + /* FCMOVE */ 1, + /* FCMOVNB */ 1, + /* FCMOVNBE */ 1, + /* FCMOVNE */ 1, + /* FCMOVNU */ 1, + /* FCMOVU */ 1, + /* FCOM */ 4, + /* FCOMI */ 1, + /* FCOMIP */ 1, + /* FCOMP */ 5, + /* FCOMPP */ 1, + /* FCOS */ 1, + /* FDECSTP */ 1, + /* FDISI8087_NOP */ 1, + /* FDIV */ 4, + /* FDIVP */ 1, + /* FDIVR */ 4, + /* FDIVRP */ 1, + /* FEMMS */ 1, + /* FENI8087_NOP */ 1, + /* FFREE */ 1, + /* FFREEP */ 1, + /* FIADD */ 2, + /* FICOM */ 2, + /* FICOMP */ 2, + /* FIDIV */ 2, + /* FIDIVR */ 2, + /* FILD */ 3, + /* FIMUL */ 2, + /* FINCSTP */ 1, + /* FIST */ 2, + /* FISTP */ 3, + /* FISTTP */ 3, + /* FISUB */ 2, + /* FISUBR */ 2, + /* FLD */ 4, + /* FLD1 */ 1, + /* FLDCW */ 1, + /* FLDENV */ 2, + /* FLDL2E */ 1, + /* FLDL2T */ 1, + /* FLDLG2 */ 1, + /* FLDLN2 */ 1, + /* FLDPI */ 1, + /* FLDZ */ 1, + /* FMUL */ 4, + /* FMULP */ 1, + /* FNCLEX */ 1, + /* FNINIT */ 1, + /* FNOP */ 1, + /* FNSAVE */ 2, + /* FNSTCW */ 1, + /* FNSTENV */ 2, + /* FNSTSW */ 2, + /* FPATAN */ 1, + /* FPREM */ 1, + /* FPREM1 */ 1, + /* FPTAN */ 1, + /* FRNDINT */ 1, + /* FRSTOR */ 2, + /* FSCALE */ 1, + /* FSETPM287_NOP */ 1, + /* FSIN */ 1, + /* FSINCOS */ 1, + /* FSQRT */ 1, + /* FST */ 3, + /* FSTP */ 6, + /* FSTPNCE */ 1, + /* FSUB */ 4, + /* FSUBP */ 1, + /* FSUBR */ 4, + /* FSUBRP */ 1, + /* FTST */ 1, + /* FUCOM */ 1, + /* FUCOMI */ 1, + /* FUCOMIP */ 1, + /* FUCOMP */ 1, + /* FUCOMPP */ 1, + /* FWAIT */ 1, + /* FXAM */ 1, + /* FXCH */ 3, + /* FXRSTOR */ 1, + /* FXRSTOR64 */ 1, + /* FXSAVE */ 1, + /* FXSAVE64 */ 1, + /* FXTRACT */ 1, + /* FYL2X */ 1, + /* FYL2XP1 */ 1, + /* GETSEC */ 1, + /* GF2P8AFFINEINVQB */ 2, + /* GF2P8AFFINEQB */ 2, + /* GF2P8MULB */ 2, + /* HADDPD */ 2, + /* HADDPS */ 2, + /* HLT */ 1, + /* HRESET */ 1, + /* HSUBPD */ 2, + /* HSUBPS */ 2, + /* IDIV */ 4, + /* IMUL */ 10, + /* IN */ 4, + /* INC */ 5, + /* INCSSPD */ 1, + /* INCSSPQ */ 1, + /* INC_LOCK */ 2, + /* INSB */ 1, + /* INSD */ 1, + /* INSERTPS */ 2, + /* INSERTQ */ 2, + /* INSW */ 1, + /* INT */ 1, + /* INT1 */ 1, + /* INT3 */ 1, + /* INTO */ 1, + /* INVD */ 1, + /* INVEPT */ 2, + /* INVLPG */ 1, + /* INVLPGA */ 1, + /* INVLPGB */ 2, + /* INVPCID */ 2, + /* INVVPID */ 2, + /* IRET */ 1, + /* IRETD */ 1, + /* IRETQ */ 1, + /* JB */ 3, + /* JBE */ 3, + /* JCXZ */ 1, + /* JECXZ */ 1, + /* JL */ 3, + /* JLE */ 3, + /* JMP */ 5, + /* JMP_FAR */ 2, + /* JNB */ 3, + /* JNBE */ 3, + /* JNL */ 3, + /* JNLE */ 3, + /* JNO */ 3, + /* JNP */ 3, + /* JNS */ 3, + /* JNZ */ 3, + /* JO */ 3, + /* JP */ 3, + /* JRCXZ */ 1, + /* JS */ 3, + /* JZ */ 3, + /* KADDB */ 1, + /* KADDD */ 1, + /* KADDQ */ 1, + /* KADDW */ 1, + /* KANDB */ 1, + /* KANDD */ 1, + /* KANDNB */ 1, + /* KANDND */ 1, + /* KANDNQ */ 1, + /* KANDNW */ 1, + /* KANDQ */ 1, + /* KANDW */ 1, + /* KMOVB */ 5, + /* KMOVD */ 5, + /* KMOVQ */ 5, + /* KMOVW */ 5, + /* KNOTB */ 1, + /* KNOTD */ 1, + /* KNOTQ */ 1, + /* KNOTW */ 1, + /* KORB */ 1, + /* KORD */ 1, + /* KORQ */ 1, + /* KORTESTB */ 1, + /* KORTESTD */ 1, + /* KORTESTQ */ 1, + /* KORTESTW */ 1, + /* KORW */ 1, + /* KSHIFTLB */ 1, + /* KSHIFTLD */ 1, + /* KSHIFTLQ */ 1, + /* KSHIFTLW */ 1, + /* KSHIFTRB */ 1, + /* KSHIFTRD */ 1, + /* KSHIFTRQ */ 1, + /* KSHIFTRW */ 1, + /* KTESTB */ 1, + /* KTESTD */ 1, + /* KTESTQ */ 1, + /* KTESTW */ 1, + /* KUNPCKBW */ 1, + /* KUNPCKDQ */ 1, + /* KUNPCKWD */ 1, + /* KXNORB */ 1, + /* KXNORD */ 1, + /* KXNORQ */ 1, + /* KXNORW */ 1, + /* KXORB */ 1, + /* KXORD */ 1, + /* KXORQ */ 1, + /* KXORW */ 1, + /* LAHF */ 1, + /* LAR */ 2, + /* LDDQU */ 1, + /* LDMXCSR */ 1, + /* LDS */ 1, + /* LDTILECFG */ 1, + /* LEA */ 1, + /* LEAVE */ 1, + /* LES */ 1, + /* LFENCE */ 1, + /* LFS */ 1, + /* LGDT */ 2, + /* LGS */ 1, + /* LIDT */ 2, + /* LLDT */ 2, + /* LLWPCB */ 1, + /* LMSW */ 2, + /* LOADIWKEY */ 1, + /* LODSB */ 1, + /* LODSD */ 1, + /* LODSQ */ 1, + /* LODSW */ 1, + /* LOOP */ 1, + /* LOOPE */ 1, + /* LOOPNE */ 1, + /* LSL */ 2, + /* LSS */ 1, + /* LTR */ 2, + /* LWPINS */ 2, + /* LWPVAL */ 2, + /* LZCNT */ 2, + /* MASKMOVDQU */ 1, + /* MASKMOVQ */ 1, + /* MAXPD */ 2, + /* MAXPS */ 2, + /* MAXSD */ 2, + /* MAXSS */ 2, + /* MCOMMIT */ 1, + /* MFENCE */ 1, + /* MINPD */ 2, + /* MINPS */ 2, + /* MINSD */ 2, + /* MINSS */ 2, + /* MONITOR */ 1, + /* MONITORX */ 1, + /* MOV */ 22, + /* MOVAPD */ 4, + /* MOVAPS */ 4, + /* MOVBE */ 2, + /* MOVD */ 8, + /* MOVDDUP */ 2, + /* MOVDIR64B */ 1, + /* MOVDIRI */ 2, + /* MOVDQ2Q */ 1, + /* MOVDQA */ 4, + /* MOVDQU */ 4, + /* MOVHLPS */ 1, + /* MOVHPD */ 2, + /* MOVHPS */ 2, + /* MOVLHPS */ 1, + /* MOVLPD */ 2, + /* MOVLPS */ 2, + /* MOVMSKPD */ 1, + /* MOVMSKPS */ 1, + /* MOVNTDQ */ 1, + /* MOVNTDQA */ 1, + /* MOVNTI */ 2, + /* MOVNTPD */ 1, + /* MOVNTPS */ 1, + /* MOVNTQ */ 1, + /* MOVNTSD */ 1, + /* MOVNTSS */ 1, + /* MOVQ */ 16, + /* MOVQ2DQ */ 1, + /* MOVSB */ 1, + /* MOVSD */ 1, + /* MOVSD_XMM */ 4, + /* MOVSHDUP */ 2, + /* MOVSLDUP */ 2, + /* MOVSQ */ 1, + /* MOVSS */ 4, + /* MOVSW */ 1, + /* MOVSX */ 4, + /* MOVSXD */ 2, + /* MOVUPD */ 4, + /* MOVUPS */ 4, + /* MOVZX */ 4, + /* MOV_CR */ 4, + /* MOV_DR */ 4, + /* MPSADBW */ 2, + /* MUL */ 4, + /* MULPD */ 2, + /* MULPS */ 2, + /* MULSD */ 2, + /* MULSS */ 2, + /* MULX */ 4, + /* MWAIT */ 1, + /* MWAITX */ 1, + /* NEG */ 4, + /* NEG_LOCK */ 2, + /* NOP */ 28, + /* NOP2 */ 0, + /* NOP3 */ 0, + /* NOP4 */ 0, + /* NOP5 */ 0, + /* NOP6 */ 0, + /* NOP7 */ 0, + /* NOP8 */ 0, + /* NOP9 */ 0, + /* NOT */ 4, + /* NOT_LOCK */ 2, + /* OR */ 18, + /* ORPD */ 2, + /* ORPS */ 2, + /* OR_LOCK */ 6, + /* OUT */ 4, + /* OUTSB */ 1, + /* OUTSD */ 1, + /* OUTSW */ 1, + /* PABSB */ 4, + /* PABSD */ 4, + /* PABSW */ 4, + /* PACKSSDW */ 4, + /* PACKSSWB */ 4, + /* PACKUSDW */ 2, + /* PACKUSWB */ 4, + /* PADDB */ 4, + /* PADDD */ 4, + /* PADDQ */ 4, + /* PADDSB */ 4, + /* PADDSW */ 4, + /* PADDUSB */ 4, + /* PADDUSW */ 4, + /* PADDW */ 4, + /* PALIGNR */ 4, + /* PAND */ 4, + /* PANDN */ 4, + /* PAUSE */ 1, + /* PAVGB */ 4, + /* PAVGUSB */ 2, + /* PAVGW */ 4, + /* PBLENDVB */ 2, + /* PBLENDW */ 2, + /* PCLMULQDQ */ 2, + /* PCMPEQB */ 4, + /* PCMPEQD */ 4, + /* PCMPEQQ */ 2, + /* PCMPEQW */ 4, + /* PCMPESTRI */ 2, + /* PCMPESTRI64 */ 2, + /* PCMPESTRM */ 2, + /* PCMPESTRM64 */ 2, + /* PCMPGTB */ 4, + /* PCMPGTD */ 4, + /* PCMPGTQ */ 2, + /* PCMPGTW */ 4, + /* PCMPISTRI */ 2, + /* PCMPISTRI64 */ 2, + /* PCMPISTRM */ 2, + /* PCONFIG */ 2, + /* PDEP */ 4, + /* PEXT */ 4, + /* PEXTRB */ 2, + /* PEXTRD */ 2, + /* PEXTRQ */ 2, + /* PEXTRW */ 2, + /* PEXTRW_SSE4 */ 2, + /* PF2ID */ 2, + /* PF2IW */ 2, + /* PFACC */ 2, + /* PFADD */ 2, + /* PFCMPEQ */ 2, + /* PFCMPGE */ 2, + /* PFCMPGT */ 2, + /* PFMAX */ 2, + /* PFMIN */ 2, + /* PFMUL */ 2, + /* PFNACC */ 2, + /* PFPNACC */ 2, + /* PFRCP */ 2, + /* PFRCPIT1 */ 2, + /* PFRCPIT2 */ 2, + /* PFRSQIT1 */ 2, + /* PFRSQRT */ 2, + /* PFSUB */ 2, + /* PFSUBR */ 2, + /* PHADDD */ 4, + /* PHADDSW */ 4, + /* PHADDW */ 4, + /* PHMINPOSUW */ 2, + /* PHSUBD */ 4, + /* PHSUBSW */ 4, + /* PHSUBW */ 4, + /* PI2FD */ 2, + /* PI2FW */ 2, + /* PINSRB */ 2, + /* PINSRD */ 2, + /* PINSRQ */ 2, + /* PINSRW */ 4, + /* PMADDUBSW */ 4, + /* PMADDWD */ 4, + /* PMAXSB */ 2, + /* PMAXSD */ 2, + /* PMAXSW */ 4, + /* PMAXUB */ 4, + /* PMAXUD */ 2, + /* PMAXUW */ 2, + /* PMINSB */ 2, + /* PMINSD */ 2, + /* PMINSW */ 4, + /* PMINUB */ 4, + /* PMINUD */ 2, + /* PMINUW */ 2, + /* PMOVMSKB */ 2, + /* PMOVSXBD */ 2, + /* PMOVSXBQ */ 2, + /* PMOVSXBW */ 2, + /* PMOVSXDQ */ 2, + /* PMOVSXWD */ 2, + /* PMOVSXWQ */ 2, + /* PMOVZXBD */ 2, + /* PMOVZXBQ */ 2, + /* PMOVZXBW */ 2, + /* PMOVZXDQ */ 2, + /* PMOVZXWD */ 2, + /* PMOVZXWQ */ 2, + /* PMULDQ */ 2, + /* PMULHRSW */ 4, + /* PMULHRW */ 2, + /* PMULHUW */ 4, + /* PMULHW */ 4, + /* PMULLD */ 2, + /* PMULLW */ 4, + /* PMULUDQ */ 4, + /* POP */ 8, + /* POPA */ 1, + /* POPAD */ 1, + /* POPCNT */ 2, + /* POPF */ 1, + /* POPFD */ 1, + /* POPFQ */ 1, + /* POR */ 4, + /* PREFETCHNTA */ 1, + /* PREFETCHT0 */ 1, + /* PREFETCHT1 */ 1, + /* PREFETCHT2 */ 1, + /* PREFETCHW */ 2, + /* PREFETCHWT1 */ 1, + /* PREFETCH_EXCLUSIVE */ 1, + /* PREFETCH_RESERVED */ 4, + /* PSADBW */ 4, + /* PSHUFB */ 4, + /* PSHUFD */ 2, + /* PSHUFHW */ 2, + /* PSHUFLW */ 2, + /* PSHUFW */ 2, + /* PSIGNB */ 4, + /* PSIGND */ 4, + /* PSIGNW */ 4, + /* PSLLD */ 6, + /* PSLLDQ */ 1, + /* PSLLQ */ 6, + /* PSLLW */ 6, + /* PSMASH */ 1, + /* PSRAD */ 6, + /* PSRAW */ 6, + /* PSRLD */ 6, + /* PSRLDQ */ 1, + /* PSRLQ */ 6, + /* PSRLW */ 6, + /* PSUBB */ 4, + /* PSUBD */ 4, + /* PSUBQ */ 4, + /* PSUBSB */ 4, + /* PSUBSW */ 4, + /* PSUBUSB */ 4, + /* PSUBUSW */ 4, + /* PSUBW */ 4, + /* PSWAPD */ 2, + /* PTEST */ 2, + /* PTWRITE */ 2, + /* PUNPCKHBW */ 4, + /* PUNPCKHDQ */ 4, + /* PUNPCKHQDQ */ 2, + /* PUNPCKHWD */ 4, + /* PUNPCKLBW */ 4, + /* PUNPCKLDQ */ 4, + /* PUNPCKLQDQ */ 2, + /* PUNPCKLWD */ 4, + /* PUSH */ 11, + /* PUSHA */ 1, + /* PUSHAD */ 1, + /* PUSHF */ 1, + /* PUSHFD */ 1, + /* PUSHFQ */ 1, + /* PVALIDATE */ 1, + /* PXOR */ 4, + /* RCL */ 12, + /* RCPPS */ 2, + /* RCPSS */ 2, + /* RCR */ 12, + /* RDFSBASE */ 1, + /* RDGSBASE */ 1, + /* RDMSR */ 1, + /* RDPID */ 2, + /* RDPKRU */ 1, + /* RDPMC */ 1, + /* RDPRU */ 1, + /* RDRAND */ 1, + /* RDSEED */ 1, + /* RDSSPD */ 1, + /* RDSSPQ */ 1, + /* RDTSC */ 1, + /* RDTSCP */ 1, + /* REPE_CMPSB */ 1, + /* REPE_CMPSD */ 1, + /* REPE_CMPSQ */ 1, + /* REPE_CMPSW */ 1, + /* REPE_SCASB */ 1, + /* REPE_SCASD */ 1, + /* REPE_SCASQ */ 1, + /* REPE_SCASW */ 1, + /* REPNE_CMPSB */ 1, + /* REPNE_CMPSD */ 1, + /* REPNE_CMPSQ */ 1, + /* REPNE_CMPSW */ 1, + /* REPNE_SCASB */ 1, + /* REPNE_SCASD */ 1, + /* REPNE_SCASQ */ 1, + /* REPNE_SCASW */ 1, + /* REP_INSB */ 1, + /* REP_INSD */ 1, + /* REP_INSW */ 1, + /* REP_LODSB */ 1, + /* REP_LODSD */ 1, + /* REP_LODSQ */ 1, + /* REP_LODSW */ 1, + /* REP_MONTMUL */ 1, + /* REP_MOVSB */ 1, + /* REP_MOVSD */ 1, + /* REP_MOVSQ */ 1, + /* REP_MOVSW */ 1, + /* REP_OUTSB */ 1, + /* REP_OUTSD */ 1, + /* REP_OUTSW */ 1, + /* REP_STOSB */ 1, + /* REP_STOSD */ 1, + /* REP_STOSQ */ 1, + /* REP_STOSW */ 1, + /* REP_XCRYPTCBC */ 1, + /* REP_XCRYPTCFB */ 1, + /* REP_XCRYPTCTR */ 1, + /* REP_XCRYPTECB */ 1, + /* REP_XCRYPTOFB */ 1, + /* REP_XSHA1 */ 1, + /* REP_XSHA256 */ 1, + /* REP_XSTORE */ 1, + /* RET_FAR */ 2, + /* RET_NEAR */ 2, + /* RMPADJUST */ 1, + /* RMPUPDATE */ 1, + /* ROL */ 12, + /* ROR */ 12, + /* RORX */ 4, + /* ROUNDPD */ 2, + /* ROUNDPS */ 2, + /* ROUNDSD */ 2, + /* ROUNDSS */ 2, + /* RSM */ 1, + /* RSQRTPS */ 2, + /* RSQRTSS */ 2, + /* RSTORSSP */ 1, + /* SAHF */ 1, + /* SALC */ 1, + /* SAR */ 12, + /* SARX */ 4, + /* SAVEPREVSSP */ 1, + /* SBB */ 18, + /* SBB_LOCK */ 6, + /* SCASB */ 1, + /* SCASD */ 1, + /* SCASQ */ 1, + /* SCASW */ 1, + /* SEAMCALL */ 1, + /* SEAMOPS */ 1, + /* SEAMRET */ 1, + /* SENDUIPI */ 1, + /* SERIALIZE */ 1, + /* SETB */ 2, + /* SETBE */ 2, + /* SETL */ 2, + /* SETLE */ 2, + /* SETNB */ 2, + /* SETNBE */ 2, + /* SETNL */ 2, + /* SETNLE */ 2, + /* SETNO */ 2, + /* SETNP */ 2, + /* SETNS */ 2, + /* SETNZ */ 2, + /* SETO */ 2, + /* SETP */ 2, + /* SETS */ 2, + /* SETSSBSY */ 1, + /* SETZ */ 2, + /* SFENCE */ 1, + /* SGDT */ 2, + /* SHA1MSG1 */ 2, + /* SHA1MSG2 */ 2, + /* SHA1NEXTE */ 2, + /* SHA1RNDS4 */ 2, + /* SHA256MSG1 */ 2, + /* SHA256MSG2 */ 2, + /* SHA256RNDS2 */ 2, + /* SHL */ 24, + /* SHLD */ 4, + /* SHLX */ 4, + /* SHR */ 12, + /* SHRD */ 4, + /* SHRX */ 4, + /* SHUFPD */ 2, + /* SHUFPS */ 2, + /* SIDT */ 2, + /* SKINIT */ 1, + /* SLDT */ 2, + /* SLWPCB */ 1, + /* SMSW */ 2, + /* SQRTPD */ 2, + /* SQRTPS */ 2, + /* SQRTSD */ 2, + /* SQRTSS */ 2, + /* STAC */ 1, + /* STC */ 1, + /* STD */ 1, + /* STGI */ 1, + /* STI */ 1, + /* STMXCSR */ 1, + /* STOSB */ 1, + /* STOSD */ 1, + /* STOSQ */ 1, + /* STOSW */ 1, + /* STR */ 2, + /* STTILECFG */ 1, + /* STUI */ 1, + /* SUB */ 18, + /* SUBPD */ 2, + /* SUBPS */ 2, + /* SUBSD */ 2, + /* SUBSS */ 2, + /* SUB_LOCK */ 6, + /* SWAPGS */ 1, + /* SYSCALL */ 1, + /* SYSCALL_AMD */ 1, + /* SYSENTER */ 1, + /* SYSEXIT */ 1, + /* SYSRET */ 1, + /* SYSRET64 */ 1, + /* SYSRET_AMD */ 1, + /* T1MSKC */ 4, + /* TDCALL */ 1, + /* TDPBF16PS */ 1, + /* TDPBSSD */ 1, + /* TDPBSUD */ 1, + /* TDPBUSD */ 1, + /* TDPBUUD */ 1, + /* TEST */ 14, + /* TESTUI */ 1, + /* TILELOADD */ 1, + /* TILELOADDT1 */ 1, + /* TILERELEASE */ 1, + /* TILESTORED */ 1, + /* TILEZERO */ 1, + /* TLBSYNC */ 1, + /* TPAUSE */ 1, + /* TZCNT */ 2, + /* TZMSK */ 4, + /* UCOMISD */ 2, + /* UCOMISS */ 2, + /* UD0 */ 3, + /* UD1 */ 2, + /* UD2 */ 1, + /* UIRET */ 1, + /* UMONITOR */ 1, + /* UMWAIT */ 1, + /* UNPCKHPD */ 2, + /* UNPCKHPS */ 2, + /* UNPCKLPD */ 2, + /* UNPCKLPS */ 2, + /* V4FMADDPS */ 1, + /* V4FMADDSS */ 1, + /* V4FNMADDPS */ 1, + /* V4FNMADDSS */ 1, + /* VADDPD */ 10, + /* VADDPH */ 6, + /* VADDPS */ 10, + /* VADDSD */ 4, + /* VADDSH */ 2, + /* VADDSS */ 4, + /* VADDSUBPD */ 4, + /* VADDSUBPS */ 4, + /* VAESDEC */ 10, + /* VAESDECLAST */ 10, + /* VAESENC */ 10, + /* VAESENCLAST */ 10, + /* VAESIMC */ 2, + /* VAESKEYGENASSIST */ 2, + /* VALIGND */ 6, + /* VALIGNQ */ 6, + /* VANDNPD */ 10, + /* VANDNPS */ 10, + /* VANDPD */ 10, + /* VANDPS */ 10, + /* VBLENDMPD */ 6, + /* VBLENDMPS */ 6, + /* VBLENDPD */ 4, + /* VBLENDPS */ 4, + /* VBLENDVPD */ 4, + /* VBLENDVPS */ 4, + /* VBROADCASTF128 */ 1, + /* VBROADCASTF32X2 */ 4, + /* VBROADCASTF32X4 */ 2, + /* VBROADCASTF32X8 */ 1, + /* VBROADCASTF64X2 */ 2, + /* VBROADCASTF64X4 */ 1, + /* VBROADCASTI128 */ 1, + /* VBROADCASTI32X2 */ 6, + /* VBROADCASTI32X4 */ 2, + /* VBROADCASTI32X8 */ 1, + /* VBROADCASTI64X2 */ 2, + /* VBROADCASTI64X4 */ 1, + /* VBROADCASTSD */ 6, + /* VBROADCASTSS */ 10, + /* VCMPPD */ 10, + /* VCMPPH */ 6, + /* VCMPPS */ 10, + /* VCMPSD */ 4, + /* VCMPSH */ 2, + /* VCMPSS */ 4, + /* VCOMISD */ 4, + /* VCOMISH */ 2, + /* VCOMISS */ 4, + /* VCOMPRESSPD */ 6, + /* VCOMPRESSPS */ 6, + /* VCVTDQ2PD */ 10, + /* VCVTDQ2PH */ 6, + /* VCVTDQ2PS */ 10, + /* VCVTNE2PS2BF16 */ 6, + /* VCVTNEPS2BF16 */ 6, + /* VCVTPD2DQ */ 10, + /* VCVTPD2PH */ 6, + /* VCVTPD2PS */ 10, + /* VCVTPD2QQ */ 6, + /* VCVTPD2UDQ */ 6, + /* VCVTPD2UQQ */ 6, + /* VCVTPH2DQ */ 6, + /* VCVTPH2PD */ 6, + /* VCVTPH2PS */ 10, + /* VCVTPH2PSX */ 6, + /* VCVTPH2QQ */ 6, + /* VCVTPH2UDQ */ 6, + /* VCVTPH2UQQ */ 6, + /* VCVTPH2UW */ 6, + /* VCVTPH2W */ 6, + /* VCVTPS2DQ */ 10, + /* VCVTPS2PD */ 10, + /* VCVTPS2PH */ 10, + /* VCVTPS2PHX */ 6, + /* VCVTPS2QQ */ 6, + /* VCVTPS2UDQ */ 6, + /* VCVTPS2UQQ */ 6, + /* VCVTQQ2PD */ 6, + /* VCVTQQ2PH */ 6, + /* VCVTQQ2PS */ 6, + /* VCVTSD2SH */ 2, + /* VCVTSD2SI */ 8, + /* VCVTSD2SS */ 4, + /* VCVTSD2USI */ 4, + /* VCVTSH2SD */ 2, + /* VCVTSH2SI */ 4, + /* VCVTSH2SS */ 2, + /* VCVTSH2USI */ 4, + /* VCVTSI2SD */ 8, + /* VCVTSI2SH */ 4, + /* VCVTSI2SS */ 8, + /* VCVTSS2SD */ 4, + /* VCVTSS2SH */ 2, + /* VCVTSS2SI */ 8, + /* VCVTSS2USI */ 4, + /* VCVTTPD2DQ */ 10, + /* VCVTTPD2QQ */ 6, + /* VCVTTPD2UDQ */ 6, + /* VCVTTPD2UQQ */ 6, + /* VCVTTPH2DQ */ 6, + /* VCVTTPH2QQ */ 6, + /* VCVTTPH2UDQ */ 6, + /* VCVTTPH2UQQ */ 6, + /* VCVTTPH2UW */ 6, + /* VCVTTPH2W */ 6, + /* VCVTTPS2DQ */ 10, + /* VCVTTPS2QQ */ 6, + /* VCVTTPS2UDQ */ 6, + /* VCVTTPS2UQQ */ 6, + /* VCVTTSD2SI */ 8, + /* VCVTTSD2USI */ 4, + /* VCVTTSH2SI */ 4, + /* VCVTTSH2USI */ 4, + /* VCVTTSS2SI */ 8, + /* VCVTTSS2USI */ 4, + /* VCVTUDQ2PD */ 6, + /* VCVTUDQ2PH */ 6, + /* VCVTUDQ2PS */ 6, + /* VCVTUQQ2PD */ 6, + /* VCVTUQQ2PH */ 6, + /* VCVTUQQ2PS */ 6, + /* VCVTUSI2SD */ 4, + /* VCVTUSI2SH */ 4, + /* VCVTUSI2SS */ 4, + /* VCVTUW2PH */ 6, + /* VCVTW2PH */ 6, + /* VDBPSADBW */ 6, + /* VDIVPD */ 10, + /* VDIVPH */ 6, + /* VDIVPS */ 10, + /* VDIVSD */ 4, + /* VDIVSH */ 2, + /* VDIVSS */ 4, + /* VDPBF16PS */ 6, + /* VDPPD */ 2, + /* VDPPS */ 4, + /* VERR */ 2, + /* VERW */ 2, + /* VEXP2PD */ 2, + /* VEXP2PS */ 2, + /* VEXPANDPD */ 6, + /* VEXPANDPS */ 6, + /* VEXTRACTF128 */ 2, + /* VEXTRACTF32X4 */ 4, + /* VEXTRACTF32X8 */ 2, + /* VEXTRACTF64X2 */ 4, + /* VEXTRACTF64X4 */ 2, + /* VEXTRACTI128 */ 2, + /* VEXTRACTI32X4 */ 4, + /* VEXTRACTI32X8 */ 2, + /* VEXTRACTI64X2 */ 4, + /* VEXTRACTI64X4 */ 2, + /* VEXTRACTPS */ 4, + /* VFCMADDCPH */ 6, + /* VFCMADDCSH */ 2, + /* VFCMULCPH */ 6, + /* VFCMULCSH */ 2, + /* VFIXUPIMMPD */ 6, + /* VFIXUPIMMPS */ 6, + /* VFIXUPIMMSD */ 2, + /* VFIXUPIMMSS */ 2, + /* VFMADD132PD */ 10, + /* VFMADD132PH */ 6, + /* VFMADD132PS */ 10, + /* VFMADD132SD */ 4, + /* VFMADD132SH */ 2, + /* VFMADD132SS */ 4, + /* VFMADD213PD */ 10, + /* VFMADD213PH */ 6, + /* VFMADD213PS */ 10, + /* VFMADD213SD */ 4, + /* VFMADD213SH */ 2, + /* VFMADD213SS */ 4, + /* VFMADD231PD */ 10, + /* VFMADD231PH */ 6, + /* VFMADD231PS */ 10, + /* VFMADD231SD */ 4, + /* VFMADD231SH */ 2, + /* VFMADD231SS */ 4, + /* VFMADDCPH */ 6, + /* VFMADDCSH */ 2, + /* VFMADDPD */ 6, + /* VFMADDPS */ 6, + /* VFMADDSD */ 3, + /* VFMADDSS */ 3, + /* VFMADDSUB132PD */ 10, + /* VFMADDSUB132PH */ 6, + /* VFMADDSUB132PS */ 10, + /* VFMADDSUB213PD */ 10, + /* VFMADDSUB213PH */ 6, + /* VFMADDSUB213PS */ 10, + /* VFMADDSUB231PD */ 10, + /* VFMADDSUB231PH */ 6, + /* VFMADDSUB231PS */ 10, + /* VFMADDSUBPD */ 6, + /* VFMADDSUBPS */ 6, + /* VFMSUB132PD */ 10, + /* VFMSUB132PH */ 6, + /* VFMSUB132PS */ 10, + /* VFMSUB132SD */ 4, + /* VFMSUB132SH */ 2, + /* VFMSUB132SS */ 4, + /* VFMSUB213PD */ 10, + /* VFMSUB213PH */ 6, + /* VFMSUB213PS */ 10, + /* VFMSUB213SD */ 4, + /* VFMSUB213SH */ 2, + /* VFMSUB213SS */ 4, + /* VFMSUB231PD */ 10, + /* VFMSUB231PH */ 6, + /* VFMSUB231PS */ 10, + /* VFMSUB231SD */ 4, + /* VFMSUB231SH */ 2, + /* VFMSUB231SS */ 4, + /* VFMSUBADD132PD */ 10, + /* VFMSUBADD132PH */ 6, + /* VFMSUBADD132PS */ 10, + /* VFMSUBADD213PD */ 10, + /* VFMSUBADD213PH */ 6, + /* VFMSUBADD213PS */ 10, + /* VFMSUBADD231PD */ 10, + /* VFMSUBADD231PH */ 6, + /* VFMSUBADD231PS */ 10, + /* VFMSUBADDPD */ 6, + /* VFMSUBADDPS */ 6, + /* VFMSUBPD */ 6, + /* VFMSUBPS */ 6, + /* VFMSUBSD */ 3, + /* VFMSUBSS */ 3, + /* VFMULCPH */ 6, + /* VFMULCSH */ 2, + /* VFNMADD132PD */ 10, + /* VFNMADD132PH */ 6, + /* VFNMADD132PS */ 10, + /* VFNMADD132SD */ 4, + /* VFNMADD132SH */ 2, + /* VFNMADD132SS */ 4, + /* VFNMADD213PD */ 10, + /* VFNMADD213PH */ 6, + /* VFNMADD213PS */ 10, + /* VFNMADD213SD */ 4, + /* VFNMADD213SH */ 2, + /* VFNMADD213SS */ 4, + /* VFNMADD231PD */ 10, + /* VFNMADD231PH */ 6, + /* VFNMADD231PS */ 10, + /* VFNMADD231SD */ 4, + /* VFNMADD231SH */ 2, + /* VFNMADD231SS */ 4, + /* VFNMADDPD */ 6, + /* VFNMADDPS */ 6, + /* VFNMADDSD */ 3, + /* VFNMADDSS */ 3, + /* VFNMSUB132PD */ 10, + /* VFNMSUB132PH */ 6, + /* VFNMSUB132PS */ 10, + /* VFNMSUB132SD */ 4, + /* VFNMSUB132SH */ 2, + /* VFNMSUB132SS */ 4, + /* VFNMSUB213PD */ 10, + /* VFNMSUB213PH */ 6, + /* VFNMSUB213PS */ 10, + /* VFNMSUB213SD */ 4, + /* VFNMSUB213SH */ 2, + /* VFNMSUB213SS */ 4, + /* VFNMSUB231PD */ 10, + /* VFNMSUB231PH */ 6, + /* VFNMSUB231PS */ 10, + /* VFNMSUB231SD */ 4, + /* VFNMSUB231SH */ 2, + /* VFNMSUB231SS */ 4, + /* VFNMSUBPD */ 6, + /* VFNMSUBPS */ 6, + /* VFNMSUBSD */ 3, + /* VFNMSUBSS */ 3, + /* VFPCLASSPD */ 6, + /* VFPCLASSPH */ 6, + /* VFPCLASSPS */ 6, + /* VFPCLASSSD */ 2, + /* VFPCLASSSH */ 2, + /* VFPCLASSSS */ 2, + /* VFRCZPD */ 4, + /* VFRCZPS */ 4, + /* VFRCZSD */ 2, + /* VFRCZSS */ 2, + /* VGATHERDPD */ 5, + /* VGATHERDPS */ 5, + /* VGATHERPF0DPD */ 1, + /* VGATHERPF0DPS */ 1, + /* VGATHERPF0QPD */ 1, + /* VGATHERPF0QPS */ 1, + /* VGATHERPF1DPD */ 1, + /* VGATHERPF1DPS */ 1, + /* VGATHERPF1QPD */ 1, + /* VGATHERPF1QPS */ 1, + /* VGATHERQPD */ 5, + /* VGATHERQPS */ 5, + /* VGETEXPPD */ 6, + /* VGETEXPPH */ 6, + /* VGETEXPPS */ 6, + /* VGETEXPSD */ 2, + /* VGETEXPSH */ 2, + /* VGETEXPSS */ 2, + /* VGETMANTPD */ 6, + /* VGETMANTPH */ 6, + /* VGETMANTPS */ 6, + /* VGETMANTSD */ 2, + /* VGETMANTSH */ 2, + /* VGETMANTSS */ 2, + /* VGF2P8AFFINEINVQB */ 10, + /* VGF2P8AFFINEQB */ 10, + /* VGF2P8MULB */ 10, + /* VHADDPD */ 4, + /* VHADDPS */ 4, + /* VHSUBPD */ 4, + /* VHSUBPS */ 4, + /* VINSERTF128 */ 2, + /* VINSERTF32X4 */ 4, + /* VINSERTF32X8 */ 2, + /* VINSERTF64X2 */ 4, + /* VINSERTF64X4 */ 2, + /* VINSERTI128 */ 2, + /* VINSERTI32X4 */ 4, + /* VINSERTI32X8 */ 2, + /* VINSERTI64X2 */ 4, + /* VINSERTI64X4 */ 2, + /* VINSERTPS */ 4, + /* VLDDQU */ 2, + /* VLDMXCSR */ 1, + /* VMASKMOVDQU */ 1, + /* VMASKMOVPD */ 4, + /* VMASKMOVPS */ 4, + /* VMAXPD */ 10, + /* VMAXPH */ 6, + /* VMAXPS */ 10, + /* VMAXSD */ 4, + /* VMAXSH */ 2, + /* VMAXSS */ 4, + /* VMCALL */ 1, + /* VMCLEAR */ 1, + /* VMFUNC */ 1, + /* VMINPD */ 10, + /* VMINPH */ 6, + /* VMINPS */ 10, + /* VMINSD */ 4, + /* VMINSH */ 2, + /* VMINSS */ 4, + /* VMLAUNCH */ 1, + /* VMLOAD */ 1, + /* VMMCALL */ 1, + /* VMOVAPD */ 17, + /* VMOVAPS */ 17, + /* VMOVD */ 8, + /* VMOVDDUP */ 10, + /* VMOVDQA */ 8, + /* VMOVDQA32 */ 9, + /* VMOVDQA64 */ 9, + /* VMOVDQU */ 8, + /* VMOVDQU16 */ 9, + /* VMOVDQU32 */ 9, + /* VMOVDQU64 */ 9, + /* VMOVDQU8 */ 9, + /* VMOVHLPS */ 2, + /* VMOVHPD */ 4, + /* VMOVHPS */ 4, + /* VMOVLHPS */ 2, + /* VMOVLPD */ 4, + /* VMOVLPS */ 4, + /* VMOVMSKPD */ 2, + /* VMOVMSKPS */ 2, + /* VMOVNTDQ */ 5, + /* VMOVNTDQA */ 5, + /* VMOVNTPD */ 5, + /* VMOVNTPS */ 5, + /* VMOVQ */ 13, + /* VMOVSD */ 7, + /* VMOVSH */ 3, + /* VMOVSHDUP */ 10, + /* VMOVSLDUP */ 10, + /* VMOVSS */ 7, + /* VMOVUPD */ 17, + /* VMOVUPS */ 17, + /* VMOVW */ 4, + /* VMPSADBW */ 4, + /* VMPTRLD */ 1, + /* VMPTRST */ 1, + /* VMREAD */ 4, + /* VMRESUME */ 1, + /* VMRUN */ 1, + /* VMSAVE */ 1, + /* VMULPD */ 10, + /* VMULPH */ 6, + /* VMULPS */ 10, + /* VMULSD */ 4, + /* VMULSH */ 2, + /* VMULSS */ 4, + /* VMWRITE */ 4, + /* VMXOFF */ 1, + /* VMXON */ 1, + /* VORPD */ 10, + /* VORPS */ 10, + /* VP2INTERSECTD */ 6, + /* VP2INTERSECTQ */ 6, + /* VP4DPWSSD */ 1, + /* VP4DPWSSDS */ 1, + /* VPABSB */ 10, + /* VPABSD */ 10, + /* VPABSQ */ 6, + /* VPABSW */ 10, + /* VPACKSSDW */ 10, + /* VPACKSSWB */ 10, + /* VPACKUSDW */ 10, + /* VPACKUSWB */ 10, + /* VPADDB */ 10, + /* VPADDD */ 10, + /* VPADDQ */ 10, + /* VPADDSB */ 10, + /* VPADDSW */ 10, + /* VPADDUSB */ 10, + /* VPADDUSW */ 10, + /* VPADDW */ 10, + /* VPALIGNR */ 10, + /* VPAND */ 4, + /* VPANDD */ 6, + /* VPANDN */ 4, + /* VPANDND */ 6, + /* VPANDNQ */ 6, + /* VPANDQ */ 6, + /* VPAVGB */ 10, + /* VPAVGW */ 10, + /* VPBLENDD */ 4, + /* VPBLENDMB */ 6, + /* VPBLENDMD */ 6, + /* VPBLENDMQ */ 6, + /* VPBLENDMW */ 6, + /* VPBLENDVB */ 4, + /* VPBLENDW */ 4, + /* VPBROADCASTB */ 13, + /* VPBROADCASTD */ 13, + /* VPBROADCASTMB2Q */ 3, + /* VPBROADCASTMW2D */ 3, + /* VPBROADCASTQ */ 13, + /* VPBROADCASTW */ 13, + /* VPCLMULQDQ */ 10, + /* VPCMOV */ 6, + /* VPCMPB */ 6, + /* VPCMPD */ 6, + /* VPCMPEQB */ 10, + /* VPCMPEQD */ 10, + /* VPCMPEQQ */ 10, + /* VPCMPEQW */ 10, + /* VPCMPESTRI */ 2, + /* VPCMPESTRI64 */ 2, + /* VPCMPESTRM */ 2, + /* VPCMPESTRM64 */ 2, + /* VPCMPGTB */ 10, + /* VPCMPGTD */ 10, + /* VPCMPGTQ */ 10, + /* VPCMPGTW */ 10, + /* VPCMPISTRI */ 2, + /* VPCMPISTRI64 */ 2, + /* VPCMPISTRM */ 2, + /* VPCMPQ */ 6, + /* VPCMPUB */ 6, + /* VPCMPUD */ 6, + /* VPCMPUQ */ 6, + /* VPCMPUW */ 6, + /* VPCMPW */ 6, + /* VPCOMB */ 2, + /* VPCOMD */ 2, + /* VPCOMPRESSB */ 6, + /* VPCOMPRESSD */ 6, + /* VPCOMPRESSQ */ 6, + /* VPCOMPRESSW */ 6, + /* VPCOMQ */ 2, + /* VPCOMUB */ 2, + /* VPCOMUD */ 2, + /* VPCOMUQ */ 2, + /* VPCOMUW */ 2, + /* VPCOMW */ 2, + /* VPCONFLICTD */ 6, + /* VPCONFLICTQ */ 6, + /* VPDPBUSD */ 10, + /* VPDPBUSDS */ 10, + /* VPDPWSSD */ 10, + /* VPDPWSSDS */ 10, + /* VPERM2F128 */ 2, + /* VPERM2I128 */ 2, + /* VPERMB */ 6, + /* VPERMD */ 6, + /* VPERMI2B */ 6, + /* VPERMI2D */ 6, + /* VPERMI2PD */ 6, + /* VPERMI2PS */ 6, + /* VPERMI2Q */ 6, + /* VPERMI2W */ 6, + /* VPERMIL2PD */ 6, + /* VPERMIL2PS */ 6, + /* VPERMILPD */ 20, + /* VPERMILPS */ 20, + /* VPERMPD */ 10, + /* VPERMPS */ 6, + /* VPERMQ */ 10, + /* VPERMT2B */ 6, + /* VPERMT2D */ 6, + /* VPERMT2PD */ 6, + /* VPERMT2PS */ 6, + /* VPERMT2Q */ 6, + /* VPERMT2W */ 6, + /* VPERMW */ 6, + /* VPEXPANDB */ 6, + /* VPEXPANDD */ 6, + /* VPEXPANDQ */ 6, + /* VPEXPANDW */ 6, + /* VPEXTRB */ 4, + /* VPEXTRD */ 4, + /* VPEXTRQ */ 4, + /* VPEXTRW */ 5, + /* VPEXTRW_C5 */ 1, + /* VPGATHERDD */ 5, + /* VPGATHERDQ */ 5, + /* VPGATHERQD */ 5, + /* VPGATHERQQ */ 5, + /* VPHADDBD */ 2, + /* VPHADDBQ */ 2, + /* VPHADDBW */ 2, + /* VPHADDD */ 4, + /* VPHADDDQ */ 2, + /* VPHADDSW */ 4, + /* VPHADDUBD */ 2, + /* VPHADDUBQ */ 2, + /* VPHADDUBW */ 2, + /* VPHADDUDQ */ 2, + /* VPHADDUWD */ 2, + /* VPHADDUWQ */ 2, + /* VPHADDW */ 4, + /* VPHADDWD */ 2, + /* VPHADDWQ */ 2, + /* VPHMINPOSUW */ 2, + /* VPHSUBBW */ 2, + /* VPHSUBD */ 4, + /* VPHSUBDQ */ 2, + /* VPHSUBSW */ 4, + /* VPHSUBW */ 4, + /* VPHSUBWD */ 2, + /* VPINSRB */ 4, + /* VPINSRD */ 4, + /* VPINSRQ */ 4, + /* VPINSRW */ 4, + /* VPLZCNTD */ 6, + /* VPLZCNTQ */ 6, + /* VPMACSDD */ 2, + /* VPMACSDQH */ 2, + /* VPMACSDQL */ 2, + /* VPMACSSDD */ 2, + /* VPMACSSDQH */ 2, + /* VPMACSSDQL */ 2, + /* VPMACSSWD */ 2, + /* VPMACSSWW */ 2, + /* VPMACSWD */ 2, + /* VPMACSWW */ 2, + /* VPMADCSSWD */ 2, + /* VPMADCSWD */ 2, + /* VPMADD52HUQ */ 6, + /* VPMADD52LUQ */ 6, + /* VPMADDUBSW */ 10, + /* VPMADDWD */ 10, + /* VPMASKMOVD */ 4, + /* VPMASKMOVQ */ 4, + /* VPMAXSB */ 10, + /* VPMAXSD */ 10, + /* VPMAXSQ */ 6, + /* VPMAXSW */ 10, + /* VPMAXUB */ 10, + /* VPMAXUD */ 10, + /* VPMAXUQ */ 6, + /* VPMAXUW */ 10, + /* VPMINSB */ 10, + /* VPMINSD */ 10, + /* VPMINSQ */ 6, + /* VPMINSW */ 10, + /* VPMINUB */ 10, + /* VPMINUD */ 10, + /* VPMINUQ */ 6, + /* VPMINUW */ 10, + /* VPMOVB2M */ 3, + /* VPMOVD2M */ 3, + /* VPMOVDB */ 6, + /* VPMOVDW */ 6, + /* VPMOVM2B */ 3, + /* VPMOVM2D */ 3, + /* VPMOVM2Q */ 3, + /* VPMOVM2W */ 3, + /* VPMOVMSKB */ 2, + /* VPMOVQ2M */ 3, + /* VPMOVQB */ 6, + /* VPMOVQD */ 6, + /* VPMOVQW */ 6, + /* VPMOVSDB */ 6, + /* VPMOVSDW */ 6, + /* VPMOVSQB */ 6, + /* VPMOVSQD */ 6, + /* VPMOVSQW */ 6, + /* VPMOVSWB */ 6, + /* VPMOVSXBD */ 10, + /* VPMOVSXBQ */ 10, + /* VPMOVSXBW */ 10, + /* VPMOVSXDQ */ 10, + /* VPMOVSXWD */ 10, + /* VPMOVSXWQ */ 10, + /* VPMOVUSDB */ 6, + /* VPMOVUSDW */ 6, + /* VPMOVUSQB */ 6, + /* VPMOVUSQD */ 6, + /* VPMOVUSQW */ 6, + /* VPMOVUSWB */ 6, + /* VPMOVW2M */ 3, + /* VPMOVWB */ 6, + /* VPMOVZXBD */ 10, + /* VPMOVZXBQ */ 10, + /* VPMOVZXBW */ 10, + /* VPMOVZXDQ */ 10, + /* VPMOVZXWD */ 10, + /* VPMOVZXWQ */ 10, + /* VPMULDQ */ 10, + /* VPMULHRSW */ 10, + /* VPMULHUW */ 10, + /* VPMULHW */ 10, + /* VPMULLD */ 10, + /* VPMULLQ */ 6, + /* VPMULLW */ 10, + /* VPMULTISHIFTQB */ 6, + /* VPMULUDQ */ 10, + /* VPOPCNTB */ 6, + /* VPOPCNTD */ 6, + /* VPOPCNTQ */ 6, + /* VPOPCNTW */ 6, + /* VPOR */ 4, + /* VPORD */ 6, + /* VPORQ */ 6, + /* VPPERM */ 3, + /* VPROLD */ 6, + /* VPROLQ */ 6, + /* VPROLVD */ 6, + /* VPROLVQ */ 6, + /* VPRORD */ 6, + /* VPRORQ */ 6, + /* VPRORVD */ 6, + /* VPRORVQ */ 6, + /* VPROTB */ 5, + /* VPROTD */ 5, + /* VPROTQ */ 5, + /* VPROTW */ 5, + /* VPSADBW */ 10, + /* VPSCATTERDD */ 3, + /* VPSCATTERDQ */ 3, + /* VPSCATTERQD */ 3, + /* VPSCATTERQQ */ 3, + /* VPSHAB */ 3, + /* VPSHAD */ 3, + /* VPSHAQ */ 3, + /* VPSHAW */ 3, + /* VPSHLB */ 3, + /* VPSHLD */ 3, + /* VPSHLDD */ 6, + /* VPSHLDQ */ 6, + /* VPSHLDVD */ 6, + /* VPSHLDVQ */ 6, + /* VPSHLDVW */ 6, + /* VPSHLDW */ 6, + /* VPSHLQ */ 3, + /* VPSHLW */ 3, + /* VPSHRDD */ 6, + /* VPSHRDQ */ 6, + /* VPSHRDVD */ 6, + /* VPSHRDVQ */ 6, + /* VPSHRDVW */ 6, + /* VPSHRDW */ 6, + /* VPSHUFB */ 10, + /* VPSHUFBITQMB */ 6, + /* VPSHUFD */ 10, + /* VPSHUFHW */ 10, + /* VPSHUFLW */ 10, + /* VPSIGNB */ 4, + /* VPSIGND */ 4, + /* VPSIGNW */ 4, + /* VPSLLD */ 18, + /* VPSLLDQ */ 8, + /* VPSLLQ */ 18, + /* VPSLLVD */ 10, + /* VPSLLVQ */ 10, + /* VPSLLVW */ 6, + /* VPSLLW */ 18, + /* VPSRAD */ 18, + /* VPSRAQ */ 12, + /* VPSRAVD */ 10, + /* VPSRAVQ */ 6, + /* VPSRAVW */ 6, + /* VPSRAW */ 18, + /* VPSRLD */ 18, + /* VPSRLDQ */ 8, + /* VPSRLQ */ 18, + /* VPSRLVD */ 10, + /* VPSRLVQ */ 10, + /* VPSRLVW */ 6, + /* VPSRLW */ 18, + /* VPSUBB */ 10, + /* VPSUBD */ 10, + /* VPSUBQ */ 10, + /* VPSUBSB */ 10, + /* VPSUBSW */ 10, + /* VPSUBUSB */ 10, + /* VPSUBUSW */ 10, + /* VPSUBW */ 10, + /* VPTERNLOGD */ 6, + /* VPTERNLOGQ */ 6, + /* VPTEST */ 4, + /* VPTESTMB */ 6, + /* VPTESTMD */ 6, + /* VPTESTMQ */ 6, + /* VPTESTMW */ 6, + /* VPTESTNMB */ 6, + /* VPTESTNMD */ 6, + /* VPTESTNMQ */ 6, + /* VPTESTNMW */ 6, + /* VPUNPCKHBW */ 10, + /* VPUNPCKHDQ */ 10, + /* VPUNPCKHQDQ */ 10, + /* VPUNPCKHWD */ 10, + /* VPUNPCKLBW */ 10, + /* VPUNPCKLDQ */ 10, + /* VPUNPCKLQDQ */ 10, + /* VPUNPCKLWD */ 10, + /* VPXOR */ 4, + /* VPXORD */ 6, + /* VPXORQ */ 6, + /* VRANGEPD */ 6, + /* VRANGEPS */ 6, + /* VRANGESD */ 2, + /* VRANGESS */ 2, + /* VRCP14PD */ 6, + /* VRCP14PS */ 6, + /* VRCP14SD */ 2, + /* VRCP14SS */ 2, + /* VRCP28PD */ 2, + /* VRCP28PS */ 2, + /* VRCP28SD */ 2, + /* VRCP28SS */ 2, + /* VRCPPH */ 6, + /* VRCPPS */ 4, + /* VRCPSH */ 2, + /* VRCPSS */ 2, + /* VREDUCEPD */ 6, + /* VREDUCEPH */ 6, + /* VREDUCEPS */ 6, + /* VREDUCESD */ 2, + /* VREDUCESH */ 2, + /* VREDUCESS */ 2, + /* VRNDSCALEPD */ 6, + /* VRNDSCALEPH */ 6, + /* VRNDSCALEPS */ 6, + /* VRNDSCALESD */ 2, + /* VRNDSCALESH */ 2, + /* VRNDSCALESS */ 2, + /* VROUNDPD */ 4, + /* VROUNDPS */ 4, + /* VROUNDSD */ 2, + /* VROUNDSS */ 2, + /* VRSQRT14PD */ 6, + /* VRSQRT14PS */ 6, + /* VRSQRT14SD */ 2, + /* VRSQRT14SS */ 2, + /* VRSQRT28PD */ 2, + /* VRSQRT28PS */ 2, + /* VRSQRT28SD */ 2, + /* VRSQRT28SS */ 2, + /* VRSQRTPH */ 6, + /* VRSQRTPS */ 4, + /* VRSQRTSH */ 2, + /* VRSQRTSS */ 2, + /* VSCALEFPD */ 6, + /* VSCALEFPH */ 6, + /* VSCALEFPS */ 6, + /* VSCALEFSD */ 2, + /* VSCALEFSH */ 2, + /* VSCALEFSS */ 2, + /* VSCATTERDPD */ 3, + /* VSCATTERDPS */ 3, + /* VSCATTERPF0DPD */ 1, + /* VSCATTERPF0DPS */ 1, + /* VSCATTERPF0QPD */ 1, + /* VSCATTERPF0QPS */ 1, + /* VSCATTERPF1DPD */ 1, + /* VSCATTERPF1DPS */ 1, + /* VSCATTERPF1QPD */ 1, + /* VSCATTERPF1QPS */ 1, + /* VSCATTERQPD */ 3, + /* VSCATTERQPS */ 3, + /* VSHUFF32X4 */ 4, + /* VSHUFF64X2 */ 4, + /* VSHUFI32X4 */ 4, + /* VSHUFI64X2 */ 4, + /* VSHUFPD */ 10, + /* VSHUFPS */ 10, + /* VSQRTPD */ 10, + /* VSQRTPH */ 6, + /* VSQRTPS */ 10, + /* VSQRTSD */ 4, + /* VSQRTSH */ 2, + /* VSQRTSS */ 4, + /* VSTMXCSR */ 1, + /* VSUBPD */ 10, + /* VSUBPH */ 6, + /* VSUBPS */ 10, + /* VSUBSD */ 4, + /* VSUBSH */ 2, + /* VSUBSS */ 4, + /* VTESTPD */ 4, + /* VTESTPS */ 4, + /* VUCOMISD */ 4, + /* VUCOMISH */ 2, + /* VUCOMISS */ 4, + /* VUNPCKHPD */ 10, + /* VUNPCKHPS */ 10, + /* VUNPCKLPD */ 10, + /* VUNPCKLPS */ 10, + /* VXORPD */ 10, + /* VXORPS */ 10, + /* VZEROALL */ 1, + /* VZEROUPPER */ 1, + /* WBINVD */ 1, + /* WBNOINVD */ 1, + /* WRFSBASE */ 1, + /* WRGSBASE */ 1, + /* WRMSR */ 1, + /* WRPKRU */ 1, + /* WRSSD */ 1, + /* WRSSQ */ 1, + /* WRUSSD */ 1, + /* WRUSSQ */ 1, + /* XABORT */ 1, + /* XADD */ 4, + /* XADD_LOCK */ 2, + /* XBEGIN */ 1, + /* XCHG */ 5, + /* XEND */ 1, + /* XGETBV */ 1, + /* XLAT */ 1, + /* XOR */ 18, + /* XORPD */ 2, + /* XORPS */ 2, + /* XOR_LOCK */ 6, + /* XRESLDTRK */ 1, + /* XRSTOR */ 1, + /* XRSTOR64 */ 1, + /* XRSTORS */ 1, + /* XRSTORS64 */ 1, + /* XSAVE */ 1, + /* XSAVE64 */ 1, + /* XSAVEC */ 1, + /* XSAVEC64 */ 1, + /* XSAVEOPT */ 1, + /* XSAVEOPT64 */ 1, + /* XSAVES */ 1, + /* XSAVES64 */ 1, + /* XSETBV */ 1, + /* XSTORE */ 1, + /* XSUSLDTRK */ 1, + /* XTEST */ 1 +}; +const xed_uint32_t xed_iform_first_per_iclass_table[XED_ICLASS_LAST] = { + /* INVALID */ 0, + /* AAA */ 1, + /* AAD */ 2, + /* AAM */ 3, + /* AAS */ 4, + /* ADC */ 5, + /* ADCX */ 23, + /* ADC_LOCK */ 27, + /* ADD */ 33, + /* ADDPD */ 51, + /* ADDPS */ 53, + /* ADDSD */ 55, + /* ADDSS */ 57, + /* ADDSUBPD */ 59, + /* ADDSUBPS */ 61, + /* ADD_LOCK */ 63, + /* ADOX */ 69, + /* AESDEC */ 73, + /* AESDEC128KL */ 75, + /* AESDEC256KL */ 76, + /* AESDECLAST */ 77, + /* AESDECWIDE128KL */ 79, + /* AESDECWIDE256KL */ 80, + /* AESENC */ 81, + /* AESENC128KL */ 83, + /* AESENC256KL */ 84, + /* AESENCLAST */ 85, + /* AESENCWIDE128KL */ 87, + /* AESENCWIDE256KL */ 88, + /* AESIMC */ 89, + /* AESKEYGENASSIST */ 91, + /* AND */ 93, + /* ANDN */ 111, + /* ANDNPD */ 115, + /* ANDNPS */ 117, + /* ANDPD */ 119, + /* ANDPS */ 121, + /* AND_LOCK */ 123, + /* ARPL */ 129, + /* BEXTR */ 131, + /* BEXTR_XOP */ 135, + /* BLCFILL */ 139, + /* BLCI */ 143, + /* BLCIC */ 147, + /* BLCMSK */ 151, + /* BLCS */ 155, + /* BLENDPD */ 159, + /* BLENDPS */ 161, + /* BLENDVPD */ 163, + /* BLENDVPS */ 165, + /* BLSFILL */ 167, + /* BLSI */ 171, + /* BLSIC */ 175, + /* BLSMSK */ 179, + /* BLSR */ 183, + /* BNDCL */ 187, + /* BNDCN */ 190, + /* BNDCU */ 193, + /* BNDLDX */ 196, + /* BNDMK */ 198, + /* BNDMOV */ 199, + /* BNDSTX */ 204, + /* BOUND */ 206, + /* BSF */ 208, + /* BSR */ 210, + /* BSWAP */ 212, + /* BT */ 213, + /* BTC */ 217, + /* BTC_LOCK */ 221, + /* BTR */ 223, + /* BTR_LOCK */ 227, + /* BTS */ 229, + /* BTS_LOCK */ 233, + /* BZHI */ 235, + /* CALL_FAR */ 239, + /* CALL_NEAR */ 241, + /* CBW */ 245, + /* CDQ */ 246, + /* CDQE */ 247, + /* CLAC */ 248, + /* CLC */ 249, + /* CLD */ 250, + /* CLDEMOTE */ 251, + /* CLFLUSH */ 252, + /* CLFLUSHOPT */ 253, + /* CLGI */ 254, + /* CLI */ 255, + /* CLRSSBSY */ 256, + /* CLTS */ 257, + /* CLUI */ 258, + /* CLWB */ 259, + /* CLZERO */ 260, + /* CMC */ 261, + /* CMOVB */ 262, + /* CMOVBE */ 264, + /* CMOVL */ 266, + /* CMOVLE */ 268, + /* CMOVNB */ 270, + /* CMOVNBE */ 272, + /* CMOVNL */ 274, + /* CMOVNLE */ 276, + /* CMOVNO */ 278, + /* CMOVNP */ 280, + /* CMOVNS */ 282, + /* CMOVNZ */ 284, + /* CMOVO */ 286, + /* CMOVP */ 288, + /* CMOVS */ 290, + /* CMOVZ */ 292, + /* CMP */ 294, + /* CMPPD */ 312, + /* CMPPS */ 314, + /* CMPSB */ 316, + /* CMPSD */ 317, + /* CMPSD_XMM */ 318, + /* CMPSQ */ 320, + /* CMPSS */ 321, + /* CMPSW */ 323, + /* CMPXCHG */ 324, + /* CMPXCHG16B */ 328, + /* CMPXCHG16B_LOCK */ 329, + /* CMPXCHG8B */ 330, + /* CMPXCHG8B_LOCK */ 331, + /* CMPXCHG_LOCK */ 332, + /* COMISD */ 334, + /* COMISS */ 336, + /* CPUID */ 338, + /* CQO */ 339, + /* CRC32 */ 340, + /* CVTDQ2PD */ 344, + /* CVTDQ2PS */ 346, + /* CVTPD2DQ */ 348, + /* CVTPD2PI */ 350, + /* CVTPD2PS */ 352, + /* CVTPI2PD */ 354, + /* CVTPI2PS */ 356, + /* CVTPS2DQ */ 358, + /* CVTPS2PD */ 360, + /* CVTPS2PI */ 362, + /* CVTSD2SI */ 364, + /* CVTSD2SS */ 368, + /* CVTSI2SD */ 370, + /* CVTSI2SS */ 374, + /* CVTSS2SD */ 378, + /* CVTSS2SI */ 380, + /* CVTTPD2DQ */ 384, + /* CVTTPD2PI */ 386, + /* CVTTPS2DQ */ 388, + /* CVTTPS2PI */ 390, + /* CVTTSD2SI */ 392, + /* CVTTSS2SI */ 396, + /* CWD */ 400, + /* CWDE */ 401, + /* DAA */ 402, + /* DAS */ 403, + /* DEC */ 404, + /* DEC_LOCK */ 409, + /* DIV */ 411, + /* DIVPD */ 415, + /* DIVPS */ 417, + /* DIVSD */ 419, + /* DIVSS */ 421, + /* DPPD */ 423, + /* DPPS */ 425, + /* EMMS */ 427, + /* ENCLS */ 428, + /* ENCLU */ 429, + /* ENCLV */ 430, + /* ENCODEKEY128 */ 431, + /* ENCODEKEY256 */ 432, + /* ENDBR32 */ 433, + /* ENDBR64 */ 434, + /* ENQCMD */ 435, + /* ENQCMDS */ 436, + /* ENTER */ 437, + /* EXTRACTPS */ 438, + /* EXTRQ */ 440, + /* F2XM1 */ 442, + /* FABS */ 443, + /* FADD */ 444, + /* FADDP */ 448, + /* FBLD */ 449, + /* FBSTP */ 450, + /* FCHS */ 451, + /* FCMOVB */ 452, + /* FCMOVBE */ 453, + /* FCMOVE */ 454, + /* FCMOVNB */ 455, + /* FCMOVNBE */ 456, + /* FCMOVNE */ 457, + /* FCMOVNU */ 458, + /* FCMOVU */ 459, + /* FCOM */ 460, + /* FCOMI */ 464, + /* FCOMIP */ 465, + /* FCOMP */ 466, + /* FCOMPP */ 471, + /* FCOS */ 472, + /* FDECSTP */ 473, + /* FDISI8087_NOP */ 474, + /* FDIV */ 475, + /* FDIVP */ 479, + /* FDIVR */ 480, + /* FDIVRP */ 484, + /* FEMMS */ 485, + /* FENI8087_NOP */ 486, + /* FFREE */ 487, + /* FFREEP */ 488, + /* FIADD */ 489, + /* FICOM */ 491, + /* FICOMP */ 493, + /* FIDIV */ 495, + /* FIDIVR */ 497, + /* FILD */ 499, + /* FIMUL */ 502, + /* FINCSTP */ 504, + /* FIST */ 505, + /* FISTP */ 507, + /* FISTTP */ 510, + /* FISUB */ 513, + /* FISUBR */ 515, + /* FLD */ 517, + /* FLD1 */ 521, + /* FLDCW */ 522, + /* FLDENV */ 523, + /* FLDL2E */ 525, + /* FLDL2T */ 526, + /* FLDLG2 */ 527, + /* FLDLN2 */ 528, + /* FLDPI */ 529, + /* FLDZ */ 530, + /* FMUL */ 531, + /* FMULP */ 535, + /* FNCLEX */ 536, + /* FNINIT */ 537, + /* FNOP */ 538, + /* FNSAVE */ 539, + /* FNSTCW */ 541, + /* FNSTENV */ 542, + /* FNSTSW */ 544, + /* FPATAN */ 546, + /* FPREM */ 547, + /* FPREM1 */ 548, + /* FPTAN */ 549, + /* FRNDINT */ 550, + /* FRSTOR */ 551, + /* FSCALE */ 553, + /* FSETPM287_NOP */ 554, + /* FSIN */ 555, + /* FSINCOS */ 556, + /* FSQRT */ 557, + /* FST */ 558, + /* FSTP */ 561, + /* FSTPNCE */ 567, + /* FSUB */ 568, + /* FSUBP */ 572, + /* FSUBR */ 573, + /* FSUBRP */ 577, + /* FTST */ 578, + /* FUCOM */ 579, + /* FUCOMI */ 580, + /* FUCOMIP */ 581, + /* FUCOMP */ 582, + /* FUCOMPP */ 583, + /* FWAIT */ 584, + /* FXAM */ 585, + /* FXCH */ 586, + /* FXRSTOR */ 589, + /* FXRSTOR64 */ 590, + /* FXSAVE */ 591, + /* FXSAVE64 */ 592, + /* FXTRACT */ 593, + /* FYL2X */ 594, + /* FYL2XP1 */ 595, + /* GETSEC */ 596, + /* GF2P8AFFINEINVQB */ 597, + /* GF2P8AFFINEQB */ 599, + /* GF2P8MULB */ 601, + /* HADDPD */ 603, + /* HADDPS */ 605, + /* HLT */ 607, + /* HRESET */ 608, + /* HSUBPD */ 609, + /* HSUBPS */ 611, + /* IDIV */ 613, + /* IMUL */ 617, + /* IN */ 627, + /* INC */ 631, + /* INCSSPD */ 636, + /* INCSSPQ */ 637, + /* INC_LOCK */ 638, + /* INSB */ 640, + /* INSD */ 641, + /* INSERTPS */ 642, + /* INSERTQ */ 644, + /* INSW */ 646, + /* INT */ 647, + /* INT1 */ 648, + /* INT3 */ 649, + /* INTO */ 650, + /* INVD */ 651, + /* INVEPT */ 652, + /* INVLPG */ 654, + /* INVLPGA */ 655, + /* INVLPGB */ 656, + /* INVPCID */ 658, + /* INVVPID */ 660, + /* IRET */ 662, + /* IRETD */ 663, + /* IRETQ */ 664, + /* JB */ 665, + /* JBE */ 668, + /* JCXZ */ 671, + /* JECXZ */ 672, + /* JL */ 673, + /* JLE */ 676, + /* JMP */ 679, + /* JMP_FAR */ 684, + /* JNB */ 686, + /* JNBE */ 689, + /* JNL */ 692, + /* JNLE */ 695, + /* JNO */ 698, + /* JNP */ 701, + /* JNS */ 704, + /* JNZ */ 707, + /* JO */ 710, + /* JP */ 713, + /* JRCXZ */ 716, + /* JS */ 717, + /* JZ */ 720, + /* KADDB */ 723, + /* KADDD */ 724, + /* KADDQ */ 725, + /* KADDW */ 726, + /* KANDB */ 727, + /* KANDD */ 728, + /* KANDNB */ 729, + /* KANDND */ 730, + /* KANDNQ */ 731, + /* KANDNW */ 732, + /* KANDQ */ 733, + /* KANDW */ 734, + /* KMOVB */ 735, + /* KMOVD */ 740, + /* KMOVQ */ 745, + /* KMOVW */ 750, + /* KNOTB */ 755, + /* KNOTD */ 756, + /* KNOTQ */ 757, + /* KNOTW */ 758, + /* KORB */ 759, + /* KORD */ 760, + /* KORQ */ 761, + /* KORTESTB */ 762, + /* KORTESTD */ 763, + /* KORTESTQ */ 764, + /* KORTESTW */ 765, + /* KORW */ 766, + /* KSHIFTLB */ 767, + /* KSHIFTLD */ 768, + /* KSHIFTLQ */ 769, + /* KSHIFTLW */ 770, + /* KSHIFTRB */ 771, + /* KSHIFTRD */ 772, + /* KSHIFTRQ */ 773, + /* KSHIFTRW */ 774, + /* KTESTB */ 775, + /* KTESTD */ 776, + /* KTESTQ */ 777, + /* KTESTW */ 778, + /* KUNPCKBW */ 779, + /* KUNPCKDQ */ 780, + /* KUNPCKWD */ 781, + /* KXNORB */ 782, + /* KXNORD */ 783, + /* KXNORQ */ 784, + /* KXNORW */ 785, + /* KXORB */ 786, + /* KXORD */ 787, + /* KXORQ */ 788, + /* KXORW */ 789, + /* LAHF */ 790, + /* LAR */ 791, + /* LDDQU */ 793, + /* LDMXCSR */ 794, + /* LDS */ 795, + /* LDTILECFG */ 796, + /* LEA */ 797, + /* LEAVE */ 798, + /* LES */ 799, + /* LFENCE */ 800, + /* LFS */ 801, + /* LGDT */ 802, + /* LGS */ 804, + /* LIDT */ 805, + /* LLDT */ 807, + /* LLWPCB */ 809, + /* LMSW */ 810, + /* LOADIWKEY */ 812, + /* LODSB */ 813, + /* LODSD */ 814, + /* LODSQ */ 815, + /* LODSW */ 816, + /* LOOP */ 817, + /* LOOPE */ 818, + /* LOOPNE */ 819, + /* LSL */ 820, + /* LSS */ 822, + /* LTR */ 823, + /* LWPINS */ 825, + /* LWPVAL */ 827, + /* LZCNT */ 829, + /* MASKMOVDQU */ 831, + /* MASKMOVQ */ 832, + /* MAXPD */ 833, + /* MAXPS */ 835, + /* MAXSD */ 837, + /* MAXSS */ 839, + /* MCOMMIT */ 841, + /* MFENCE */ 842, + /* MINPD */ 843, + /* MINPS */ 845, + /* MINSD */ 847, + /* MINSS */ 849, + /* MONITOR */ 851, + /* MONITORX */ 852, + /* MOV */ 853, + /* MOVAPD */ 875, + /* MOVAPS */ 879, + /* MOVBE */ 883, + /* MOVD */ 885, + /* MOVDDUP */ 893, + /* MOVDIR64B */ 895, + /* MOVDIRI */ 896, + /* MOVDQ2Q */ 898, + /* MOVDQA */ 899, + /* MOVDQU */ 903, + /* MOVHLPS */ 907, + /* MOVHPD */ 908, + /* MOVHPS */ 910, + /* MOVLHPS */ 912, + /* MOVLPD */ 913, + /* MOVLPS */ 915, + /* MOVMSKPD */ 917, + /* MOVMSKPS */ 918, + /* MOVNTDQ */ 919, + /* MOVNTDQA */ 920, + /* MOVNTI */ 921, + /* MOVNTPD */ 923, + /* MOVNTPS */ 924, + /* MOVNTQ */ 925, + /* MOVNTSD */ 926, + /* MOVNTSS */ 927, + /* MOVQ */ 928, + /* MOVQ2DQ */ 944, + /* MOVSB */ 945, + /* MOVSD */ 946, + /* MOVSD_XMM */ 947, + /* MOVSHDUP */ 951, + /* MOVSLDUP */ 953, + /* MOVSQ */ 955, + /* MOVSS */ 956, + /* MOVSW */ 960, + /* MOVSX */ 961, + /* MOVSXD */ 965, + /* MOVUPD */ 967, + /* MOVUPS */ 971, + /* MOVZX */ 975, + /* MOV_CR */ 979, + /* MOV_DR */ 983, + /* MPSADBW */ 987, + /* MUL */ 989, + /* MULPD */ 993, + /* MULPS */ 995, + /* MULSD */ 997, + /* MULSS */ 999, + /* MULX */ 1001, + /* MWAIT */ 1005, + /* MWAITX */ 1006, + /* NEG */ 1007, + /* NEG_LOCK */ 1011, + /* NOP */ 1013, + /* NOP2 */ 0, + /* NOP3 */ 0, + /* NOP4 */ 0, + /* NOP5 */ 0, + /* NOP6 */ 0, + /* NOP7 */ 0, + /* NOP8 */ 0, + /* NOP9 */ 0, + /* NOT */ 1041, + /* NOT_LOCK */ 1045, + /* OR */ 1047, + /* ORPD */ 1065, + /* ORPS */ 1067, + /* OR_LOCK */ 1069, + /* OUT */ 1075, + /* OUTSB */ 1079, + /* OUTSD */ 1080, + /* OUTSW */ 1081, + /* PABSB */ 1082, + /* PABSD */ 1086, + /* PABSW */ 1090, + /* PACKSSDW */ 1094, + /* PACKSSWB */ 1098, + /* PACKUSDW */ 1102, + /* PACKUSWB */ 1104, + /* PADDB */ 1108, + /* PADDD */ 1112, + /* PADDQ */ 1116, + /* PADDSB */ 1120, + /* PADDSW */ 1124, + /* PADDUSB */ 1128, + /* PADDUSW */ 1132, + /* PADDW */ 1136, + /* PALIGNR */ 1140, + /* PAND */ 1144, + /* PANDN */ 1148, + /* PAUSE */ 1152, + /* PAVGB */ 1153, + /* PAVGUSB */ 1157, + /* PAVGW */ 1159, + /* PBLENDVB */ 1163, + /* PBLENDW */ 1165, + /* PCLMULQDQ */ 1167, + /* PCMPEQB */ 1169, + /* PCMPEQD */ 1173, + /* PCMPEQQ */ 1177, + /* PCMPEQW */ 1179, + /* PCMPESTRI */ 1183, + /* PCMPESTRI64 */ 1185, + /* PCMPESTRM */ 1187, + /* PCMPESTRM64 */ 1189, + /* PCMPGTB */ 1191, + /* PCMPGTD */ 1195, + /* PCMPGTQ */ 1199, + /* PCMPGTW */ 1201, + /* PCMPISTRI */ 1205, + /* PCMPISTRI64 */ 1207, + /* PCMPISTRM */ 1209, + /* PCONFIG */ 1211, + /* PDEP */ 1213, + /* PEXT */ 1217, + /* PEXTRB */ 1221, + /* PEXTRD */ 1223, + /* PEXTRQ */ 1225, + /* PEXTRW */ 1227, + /* PEXTRW_SSE4 */ 1229, + /* PF2ID */ 1231, + /* PF2IW */ 1233, + /* PFACC */ 1235, + /* PFADD */ 1237, + /* PFCMPEQ */ 1239, + /* PFCMPGE */ 1241, + /* PFCMPGT */ 1243, + /* PFMAX */ 1245, + /* PFMIN */ 1247, + /* PFMUL */ 1249, + /* PFNACC */ 1251, + /* PFPNACC */ 1253, + /* PFRCP */ 1255, + /* PFRCPIT1 */ 1257, + /* PFRCPIT2 */ 1259, + /* PFRSQIT1 */ 1261, + /* PFRSQRT */ 1263, + /* PFSUB */ 1265, + /* PFSUBR */ 1267, + /* PHADDD */ 1269, + /* PHADDSW */ 1273, + /* PHADDW */ 1277, + /* PHMINPOSUW */ 1281, + /* PHSUBD */ 1283, + /* PHSUBSW */ 1287, + /* PHSUBW */ 1291, + /* PI2FD */ 1295, + /* PI2FW */ 1297, + /* PINSRB */ 1299, + /* PINSRD */ 1301, + /* PINSRQ */ 1303, + /* PINSRW */ 1305, + /* PMADDUBSW */ 1309, + /* PMADDWD */ 1313, + /* PMAXSB */ 1317, + /* PMAXSD */ 1319, + /* PMAXSW */ 1321, + /* PMAXUB */ 1325, + /* PMAXUD */ 1329, + /* PMAXUW */ 1331, + /* PMINSB */ 1333, + /* PMINSD */ 1335, + /* PMINSW */ 1337, + /* PMINUB */ 1341, + /* PMINUD */ 1345, + /* PMINUW */ 1347, + /* PMOVMSKB */ 1349, + /* PMOVSXBD */ 1351, + /* PMOVSXBQ */ 1353, + /* PMOVSXBW */ 1355, + /* PMOVSXDQ */ 1357, + /* PMOVSXWD */ 1359, + /* PMOVSXWQ */ 1361, + /* PMOVZXBD */ 1363, + /* PMOVZXBQ */ 1365, + /* PMOVZXBW */ 1367, + /* PMOVZXDQ */ 1369, + /* PMOVZXWD */ 1371, + /* PMOVZXWQ */ 1373, + /* PMULDQ */ 1375, + /* PMULHRSW */ 1377, + /* PMULHRW */ 1381, + /* PMULHUW */ 1383, + /* PMULHW */ 1387, + /* PMULLD */ 1391, + /* PMULLW */ 1393, + /* PMULUDQ */ 1397, + /* POP */ 1401, + /* POPA */ 1409, + /* POPAD */ 1410, + /* POPCNT */ 1411, + /* POPF */ 1413, + /* POPFD */ 1414, + /* POPFQ */ 1415, + /* POR */ 1416, + /* PREFETCHNTA */ 1420, + /* PREFETCHT0 */ 1421, + /* PREFETCHT1 */ 1422, + /* PREFETCHT2 */ 1423, + /* PREFETCHW */ 1424, + /* PREFETCHWT1 */ 1426, + /* PREFETCH_EXCLUSIVE */ 1427, + /* PREFETCH_RESERVED */ 1428, + /* PSADBW */ 1432, + /* PSHUFB */ 1436, + /* PSHUFD */ 1440, + /* PSHUFHW */ 1442, + /* PSHUFLW */ 1444, + /* PSHUFW */ 1446, + /* PSIGNB */ 1448, + /* PSIGND */ 1452, + /* PSIGNW */ 1456, + /* PSLLD */ 1460, + /* PSLLDQ */ 1466, + /* PSLLQ */ 1467, + /* PSLLW */ 1473, + /* PSMASH */ 1479, + /* PSRAD */ 1480, + /* PSRAW */ 1486, + /* PSRLD */ 1492, + /* PSRLDQ */ 1498, + /* PSRLQ */ 1499, + /* PSRLW */ 1505, + /* PSUBB */ 1511, + /* PSUBD */ 1515, + /* PSUBQ */ 1519, + /* PSUBSB */ 1523, + /* PSUBSW */ 1527, + /* PSUBUSB */ 1531, + /* PSUBUSW */ 1535, + /* PSUBW */ 1539, + /* PSWAPD */ 1543, + /* PTEST */ 1545, + /* PTWRITE */ 1547, + /* PUNPCKHBW */ 1549, + /* PUNPCKHDQ */ 1553, + /* PUNPCKHQDQ */ 1557, + /* PUNPCKHWD */ 1559, + /* PUNPCKLBW */ 1563, + /* PUNPCKLDQ */ 1567, + /* PUNPCKLQDQ */ 1571, + /* PUNPCKLWD */ 1573, + /* PUSH */ 1577, + /* PUSHA */ 1588, + /* PUSHAD */ 1589, + /* PUSHF */ 1590, + /* PUSHFD */ 1591, + /* PUSHFQ */ 1592, + /* PVALIDATE */ 1593, + /* PXOR */ 1594, + /* RCL */ 1598, + /* RCPPS */ 1610, + /* RCPSS */ 1612, + /* RCR */ 1614, + /* RDFSBASE */ 1626, + /* RDGSBASE */ 1627, + /* RDMSR */ 1628, + /* RDPID */ 1629, + /* RDPKRU */ 1631, + /* RDPMC */ 1632, + /* RDPRU */ 1633, + /* RDRAND */ 1634, + /* RDSEED */ 1635, + /* RDSSPD */ 1636, + /* RDSSPQ */ 1637, + /* RDTSC */ 1638, + /* RDTSCP */ 1639, + /* REPE_CMPSB */ 1640, + /* REPE_CMPSD */ 1641, + /* REPE_CMPSQ */ 1642, + /* REPE_CMPSW */ 1643, + /* REPE_SCASB */ 1644, + /* REPE_SCASD */ 1645, + /* REPE_SCASQ */ 1646, + /* REPE_SCASW */ 1647, + /* REPNE_CMPSB */ 1648, + /* REPNE_CMPSD */ 1649, + /* REPNE_CMPSQ */ 1650, + /* REPNE_CMPSW */ 1651, + /* REPNE_SCASB */ 1652, + /* REPNE_SCASD */ 1653, + /* REPNE_SCASQ */ 1654, + /* REPNE_SCASW */ 1655, + /* REP_INSB */ 1656, + /* REP_INSD */ 1657, + /* REP_INSW */ 1658, + /* REP_LODSB */ 1659, + /* REP_LODSD */ 1660, + /* REP_LODSQ */ 1661, + /* REP_LODSW */ 1662, + /* REP_MONTMUL */ 1663, + /* REP_MOVSB */ 1664, + /* REP_MOVSD */ 1665, + /* REP_MOVSQ */ 1666, + /* REP_MOVSW */ 1667, + /* REP_OUTSB */ 1668, + /* REP_OUTSD */ 1669, + /* REP_OUTSW */ 1670, + /* REP_STOSB */ 1671, + /* REP_STOSD */ 1672, + /* REP_STOSQ */ 1673, + /* REP_STOSW */ 1674, + /* REP_XCRYPTCBC */ 1675, + /* REP_XCRYPTCFB */ 1676, + /* REP_XCRYPTCTR */ 1677, + /* REP_XCRYPTECB */ 1678, + /* REP_XCRYPTOFB */ 1679, + /* REP_XSHA1 */ 1680, + /* REP_XSHA256 */ 1681, + /* REP_XSTORE */ 1682, + /* RET_FAR */ 1683, + /* RET_NEAR */ 1685, + /* RMPADJUST */ 1687, + /* RMPUPDATE */ 1688, + /* ROL */ 1689, + /* ROR */ 1701, + /* RORX */ 1713, + /* ROUNDPD */ 1717, + /* ROUNDPS */ 1719, + /* ROUNDSD */ 1721, + /* ROUNDSS */ 1723, + /* RSM */ 1725, + /* RSQRTPS */ 1726, + /* RSQRTSS */ 1728, + /* RSTORSSP */ 1730, + /* SAHF */ 1731, + /* SALC */ 1732, + /* SAR */ 1733, + /* SARX */ 1745, + /* SAVEPREVSSP */ 1749, + /* SBB */ 1750, + /* SBB_LOCK */ 1768, + /* SCASB */ 1774, + /* SCASD */ 1775, + /* SCASQ */ 1776, + /* SCASW */ 1777, + /* SEAMCALL */ 1778, + /* SEAMOPS */ 1779, + /* SEAMRET */ 1780, + /* SENDUIPI */ 1781, + /* SERIALIZE */ 1782, + /* SETB */ 1783, + /* SETBE */ 1785, + /* SETL */ 1787, + /* SETLE */ 1789, + /* SETNB */ 1791, + /* SETNBE */ 1793, + /* SETNL */ 1795, + /* SETNLE */ 1797, + /* SETNO */ 1799, + /* SETNP */ 1801, + /* SETNS */ 1803, + /* SETNZ */ 1805, + /* SETO */ 1807, + /* SETP */ 1809, + /* SETS */ 1811, + /* SETSSBSY */ 1813, + /* SETZ */ 1814, + /* SFENCE */ 1816, + /* SGDT */ 1817, + /* SHA1MSG1 */ 1819, + /* SHA1MSG2 */ 1821, + /* SHA1NEXTE */ 1823, + /* SHA1RNDS4 */ 1825, + /* SHA256MSG1 */ 1827, + /* SHA256MSG2 */ 1829, + /* SHA256RNDS2 */ 1831, + /* SHL */ 1833, + /* SHLD */ 1857, + /* SHLX */ 1861, + /* SHR */ 1865, + /* SHRD */ 1877, + /* SHRX */ 1881, + /* SHUFPD */ 1885, + /* SHUFPS */ 1887, + /* SIDT */ 1889, + /* SKINIT */ 1891, + /* SLDT */ 1892, + /* SLWPCB */ 1894, + /* SMSW */ 1895, + /* SQRTPD */ 1897, + /* SQRTPS */ 1899, + /* SQRTSD */ 1901, + /* SQRTSS */ 1903, + /* STAC */ 1905, + /* STC */ 1906, + /* STD */ 1907, + /* STGI */ 1908, + /* STI */ 1909, + /* STMXCSR */ 1910, + /* STOSB */ 1911, + /* STOSD */ 1912, + /* STOSQ */ 1913, + /* STOSW */ 1914, + /* STR */ 1915, + /* STTILECFG */ 1917, + /* STUI */ 1918, + /* SUB */ 1919, + /* SUBPD */ 1937, + /* SUBPS */ 1939, + /* SUBSD */ 1941, + /* SUBSS */ 1943, + /* SUB_LOCK */ 1945, + /* SWAPGS */ 1951, + /* SYSCALL */ 1952, + /* SYSCALL_AMD */ 1953, + /* SYSENTER */ 1954, + /* SYSEXIT */ 1955, + /* SYSRET */ 1956, + /* SYSRET64 */ 1957, + /* SYSRET_AMD */ 1958, + /* T1MSKC */ 1959, + /* TDCALL */ 1963, + /* TDPBF16PS */ 1964, + /* TDPBSSD */ 1965, + /* TDPBSUD */ 1966, + /* TDPBUSD */ 1967, + /* TDPBUUD */ 1968, + /* TEST */ 1969, + /* TESTUI */ 1983, + /* TILELOADD */ 1984, + /* TILELOADDT1 */ 1985, + /* TILERELEASE */ 1986, + /* TILESTORED */ 1987, + /* TILEZERO */ 1988, + /* TLBSYNC */ 1989, + /* TPAUSE */ 1990, + /* TZCNT */ 1991, + /* TZMSK */ 1993, + /* UCOMISD */ 1997, + /* UCOMISS */ 1999, + /* UD0 */ 2001, + /* UD1 */ 2004, + /* UD2 */ 2006, + /* UIRET */ 2007, + /* UMONITOR */ 2008, + /* UMWAIT */ 2009, + /* UNPCKHPD */ 2010, + /* UNPCKHPS */ 2012, + /* UNPCKLPD */ 2014, + /* UNPCKLPS */ 2016, + /* V4FMADDPS */ 2018, + /* V4FMADDSS */ 2019, + /* V4FNMADDPS */ 2020, + /* V4FNMADDSS */ 2021, + /* VADDPD */ 2022, + /* VADDPH */ 2032, + /* VADDPS */ 2038, + /* VADDSD */ 2048, + /* VADDSH */ 2052, + /* VADDSS */ 2054, + /* VADDSUBPD */ 2058, + /* VADDSUBPS */ 2062, + /* VAESDEC */ 2066, + /* VAESDECLAST */ 2076, + /* VAESENC */ 2086, + /* VAESENCLAST */ 2096, + /* VAESIMC */ 2106, + /* VAESKEYGENASSIST */ 2108, + /* VALIGND */ 2110, + /* VALIGNQ */ 2116, + /* VANDNPD */ 2122, + /* VANDNPS */ 2132, + /* VANDPD */ 2142, + /* VANDPS */ 2152, + /* VBLENDMPD */ 2162, + /* VBLENDMPS */ 2168, + /* VBLENDPD */ 2174, + /* VBLENDPS */ 2178, + /* VBLENDVPD */ 2182, + /* VBLENDVPS */ 2186, + /* VBROADCASTF128 */ 2190, + /* VBROADCASTF32X2 */ 2191, + /* VBROADCASTF32X4 */ 2195, + /* VBROADCASTF32X8 */ 2197, + /* VBROADCASTF64X2 */ 2198, + /* VBROADCASTF64X4 */ 2200, + /* VBROADCASTI128 */ 2201, + /* VBROADCASTI32X2 */ 2202, + /* VBROADCASTI32X4 */ 2208, + /* VBROADCASTI32X8 */ 2210, + /* VBROADCASTI64X2 */ 2211, + /* VBROADCASTI64X4 */ 2213, + /* VBROADCASTSD */ 2214, + /* VBROADCASTSS */ 2220, + /* VCMPPD */ 2230, + /* VCMPPH */ 2240, + /* VCMPPS */ 2246, + /* VCMPSD */ 2256, + /* VCMPSH */ 2260, + /* VCMPSS */ 2262, + /* VCOMISD */ 2266, + /* VCOMISH */ 2270, + /* VCOMISS */ 2272, + /* VCOMPRESSPD */ 2276, + /* VCOMPRESSPS */ 2282, + /* VCVTDQ2PD */ 2288, + /* VCVTDQ2PH */ 2298, + /* VCVTDQ2PS */ 2304, + /* VCVTNE2PS2BF16 */ 2314, + /* VCVTNEPS2BF16 */ 2320, + /* VCVTPD2DQ */ 2326, + /* VCVTPD2PH */ 2336, + /* VCVTPD2PS */ 2342, + /* VCVTPD2QQ */ 2352, + /* VCVTPD2UDQ */ 2358, + /* VCVTPD2UQQ */ 2364, + /* VCVTPH2DQ */ 2370, + /* VCVTPH2PD */ 2376, + /* VCVTPH2PS */ 2382, + /* VCVTPH2PSX */ 2392, + /* VCVTPH2QQ */ 2398, + /* VCVTPH2UDQ */ 2404, + /* VCVTPH2UQQ */ 2410, + /* VCVTPH2UW */ 2416, + /* VCVTPH2W */ 2422, + /* VCVTPS2DQ */ 2428, + /* VCVTPS2PD */ 2438, + /* VCVTPS2PH */ 2448, + /* VCVTPS2PHX */ 2458, + /* VCVTPS2QQ */ 2464, + /* VCVTPS2UDQ */ 2470, + /* VCVTPS2UQQ */ 2476, + /* VCVTQQ2PD */ 2482, + /* VCVTQQ2PH */ 2488, + /* VCVTQQ2PS */ 2494, + /* VCVTSD2SH */ 2500, + /* VCVTSD2SI */ 2502, + /* VCVTSD2SS */ 2510, + /* VCVTSD2USI */ 2514, + /* VCVTSH2SD */ 2518, + /* VCVTSH2SI */ 2520, + /* VCVTSH2SS */ 2524, + /* VCVTSH2USI */ 2526, + /* VCVTSI2SD */ 2530, + /* VCVTSI2SH */ 2538, + /* VCVTSI2SS */ 2542, + /* VCVTSS2SD */ 2550, + /* VCVTSS2SH */ 2554, + /* VCVTSS2SI */ 2556, + /* VCVTSS2USI */ 2564, + /* VCVTTPD2DQ */ 2568, + /* VCVTTPD2QQ */ 2578, + /* VCVTTPD2UDQ */ 2584, + /* VCVTTPD2UQQ */ 2590, + /* VCVTTPH2DQ */ 2596, + /* VCVTTPH2QQ */ 2602, + /* VCVTTPH2UDQ */ 2608, + /* VCVTTPH2UQQ */ 2614, + /* VCVTTPH2UW */ 2620, + /* VCVTTPH2W */ 2626, + /* VCVTTPS2DQ */ 2632, + /* VCVTTPS2QQ */ 2642, + /* VCVTTPS2UDQ */ 2648, + /* VCVTTPS2UQQ */ 2654, + /* VCVTTSD2SI */ 2660, + /* VCVTTSD2USI */ 2668, + /* VCVTTSH2SI */ 2672, + /* VCVTTSH2USI */ 2676, + /* VCVTTSS2SI */ 2680, + /* VCVTTSS2USI */ 2688, + /* VCVTUDQ2PD */ 2692, + /* VCVTUDQ2PH */ 2698, + /* VCVTUDQ2PS */ 2704, + /* VCVTUQQ2PD */ 2710, + /* VCVTUQQ2PH */ 2716, + /* VCVTUQQ2PS */ 2722, + /* VCVTUSI2SD */ 2728, + /* VCVTUSI2SH */ 2732, + /* VCVTUSI2SS */ 2736, + /* VCVTUW2PH */ 2740, + /* VCVTW2PH */ 2746, + /* VDBPSADBW */ 2752, + /* VDIVPD */ 2758, + /* VDIVPH */ 2768, + /* VDIVPS */ 2774, + /* VDIVSD */ 2784, + /* VDIVSH */ 2788, + /* VDIVSS */ 2790, + /* VDPBF16PS */ 2794, + /* VDPPD */ 2800, + /* VDPPS */ 2802, + /* VERR */ 2806, + /* VERW */ 2808, + /* VEXP2PD */ 2810, + /* VEXP2PS */ 2812, + /* VEXPANDPD */ 2814, + /* VEXPANDPS */ 2820, + /* VEXTRACTF128 */ 2826, + /* VEXTRACTF32X4 */ 2828, + /* VEXTRACTF32X8 */ 2832, + /* VEXTRACTF64X2 */ 2834, + /* VEXTRACTF64X4 */ 2838, + /* VEXTRACTI128 */ 2840, + /* VEXTRACTI32X4 */ 2842, + /* VEXTRACTI32X8 */ 2846, + /* VEXTRACTI64X2 */ 2848, + /* VEXTRACTI64X4 */ 2852, + /* VEXTRACTPS */ 2854, + /* VFCMADDCPH */ 2858, + /* VFCMADDCSH */ 2864, + /* VFCMULCPH */ 2866, + /* VFCMULCSH */ 2872, + /* VFIXUPIMMPD */ 2874, + /* VFIXUPIMMPS */ 2880, + /* VFIXUPIMMSD */ 2886, + /* VFIXUPIMMSS */ 2888, + /* VFMADD132PD */ 2890, + /* VFMADD132PH */ 2900, + /* VFMADD132PS */ 2906, + /* VFMADD132SD */ 2916, + /* VFMADD132SH */ 2920, + /* VFMADD132SS */ 2922, + /* VFMADD213PD */ 2926, + /* VFMADD213PH */ 2936, + /* VFMADD213PS */ 2942, + /* VFMADD213SD */ 2952, + /* VFMADD213SH */ 2956, + /* VFMADD213SS */ 2958, + /* VFMADD231PD */ 2962, + /* VFMADD231PH */ 2972, + /* VFMADD231PS */ 2978, + /* VFMADD231SD */ 2988, + /* VFMADD231SH */ 2992, + /* VFMADD231SS */ 2994, + /* VFMADDCPH */ 2998, + /* VFMADDCSH */ 3004, + /* VFMADDPD */ 3006, + /* VFMADDPS */ 3012, + /* VFMADDSD */ 3018, + /* VFMADDSS */ 3021, + /* VFMADDSUB132PD */ 3024, + /* VFMADDSUB132PH */ 3034, + /* VFMADDSUB132PS */ 3040, + /* VFMADDSUB213PD */ 3050, + /* VFMADDSUB213PH */ 3060, + /* VFMADDSUB213PS */ 3066, + /* VFMADDSUB231PD */ 3076, + /* VFMADDSUB231PH */ 3086, + /* VFMADDSUB231PS */ 3092, + /* VFMADDSUBPD */ 3102, + /* VFMADDSUBPS */ 3108, + /* VFMSUB132PD */ 3114, + /* VFMSUB132PH */ 3124, + /* VFMSUB132PS */ 3130, + /* VFMSUB132SD */ 3140, + /* VFMSUB132SH */ 3144, + /* VFMSUB132SS */ 3146, + /* VFMSUB213PD */ 3150, + /* VFMSUB213PH */ 3160, + /* VFMSUB213PS */ 3166, + /* VFMSUB213SD */ 3176, + /* VFMSUB213SH */ 3180, + /* VFMSUB213SS */ 3182, + /* VFMSUB231PD */ 3186, + /* VFMSUB231PH */ 3196, + /* VFMSUB231PS */ 3202, + /* VFMSUB231SD */ 3212, + /* VFMSUB231SH */ 3216, + /* VFMSUB231SS */ 3218, + /* VFMSUBADD132PD */ 3222, + /* VFMSUBADD132PH */ 3232, + /* VFMSUBADD132PS */ 3238, + /* VFMSUBADD213PD */ 3248, + /* VFMSUBADD213PH */ 3258, + /* VFMSUBADD213PS */ 3264, + /* VFMSUBADD231PD */ 3274, + /* VFMSUBADD231PH */ 3284, + /* VFMSUBADD231PS */ 3290, + /* VFMSUBADDPD */ 3300, + /* VFMSUBADDPS */ 3306, + /* VFMSUBPD */ 3312, + /* VFMSUBPS */ 3318, + /* VFMSUBSD */ 3324, + /* VFMSUBSS */ 3327, + /* VFMULCPH */ 3330, + /* VFMULCSH */ 3336, + /* VFNMADD132PD */ 3338, + /* VFNMADD132PH */ 3348, + /* VFNMADD132PS */ 3354, + /* VFNMADD132SD */ 3364, + /* VFNMADD132SH */ 3368, + /* VFNMADD132SS */ 3370, + /* VFNMADD213PD */ 3374, + /* VFNMADD213PH */ 3384, + /* VFNMADD213PS */ 3390, + /* VFNMADD213SD */ 3400, + /* VFNMADD213SH */ 3404, + /* VFNMADD213SS */ 3406, + /* VFNMADD231PD */ 3410, + /* VFNMADD231PH */ 3420, + /* VFNMADD231PS */ 3426, + /* VFNMADD231SD */ 3436, + /* VFNMADD231SH */ 3440, + /* VFNMADD231SS */ 3442, + /* VFNMADDPD */ 3446, + /* VFNMADDPS */ 3452, + /* VFNMADDSD */ 3458, + /* VFNMADDSS */ 3461, + /* VFNMSUB132PD */ 3464, + /* VFNMSUB132PH */ 3474, + /* VFNMSUB132PS */ 3480, + /* VFNMSUB132SD */ 3490, + /* VFNMSUB132SH */ 3494, + /* VFNMSUB132SS */ 3496, + /* VFNMSUB213PD */ 3500, + /* VFNMSUB213PH */ 3510, + /* VFNMSUB213PS */ 3516, + /* VFNMSUB213SD */ 3526, + /* VFNMSUB213SH */ 3530, + /* VFNMSUB213SS */ 3532, + /* VFNMSUB231PD */ 3536, + /* VFNMSUB231PH */ 3546, + /* VFNMSUB231PS */ 3552, + /* VFNMSUB231SD */ 3562, + /* VFNMSUB231SH */ 3566, + /* VFNMSUB231SS */ 3568, + /* VFNMSUBPD */ 3572, + /* VFNMSUBPS */ 3578, + /* VFNMSUBSD */ 3584, + /* VFNMSUBSS */ 3587, + /* VFPCLASSPD */ 3590, + /* VFPCLASSPH */ 3596, + /* VFPCLASSPS */ 3602, + /* VFPCLASSSD */ 3608, + /* VFPCLASSSH */ 3610, + /* VFPCLASSSS */ 3612, + /* VFRCZPD */ 3614, + /* VFRCZPS */ 3618, + /* VFRCZSD */ 3622, + /* VFRCZSS */ 3624, + /* VGATHERDPD */ 3626, + /* VGATHERDPS */ 3631, + /* VGATHERPF0DPD */ 3636, + /* VGATHERPF0DPS */ 3637, + /* VGATHERPF0QPD */ 3638, + /* VGATHERPF0QPS */ 3639, + /* VGATHERPF1DPD */ 3640, + /* VGATHERPF1DPS */ 3641, + /* VGATHERPF1QPD */ 3642, + /* VGATHERPF1QPS */ 3643, + /* VGATHERQPD */ 3644, + /* VGATHERQPS */ 3649, + /* VGETEXPPD */ 3654, + /* VGETEXPPH */ 3660, + /* VGETEXPPS */ 3666, + /* VGETEXPSD */ 3672, + /* VGETEXPSH */ 3674, + /* VGETEXPSS */ 3676, + /* VGETMANTPD */ 3678, + /* VGETMANTPH */ 3684, + /* VGETMANTPS */ 3690, + /* VGETMANTSD */ 3696, + /* VGETMANTSH */ 3698, + /* VGETMANTSS */ 3700, + /* VGF2P8AFFINEINVQB */ 3702, + /* VGF2P8AFFINEQB */ 3712, + /* VGF2P8MULB */ 3722, + /* VHADDPD */ 3732, + /* VHADDPS */ 3736, + /* VHSUBPD */ 3740, + /* VHSUBPS */ 3744, + /* VINSERTF128 */ 3748, + /* VINSERTF32X4 */ 3750, + /* VINSERTF32X8 */ 3754, + /* VINSERTF64X2 */ 3756, + /* VINSERTF64X4 */ 3760, + /* VINSERTI128 */ 3762, + /* VINSERTI32X4 */ 3764, + /* VINSERTI32X8 */ 3768, + /* VINSERTI64X2 */ 3770, + /* VINSERTI64X4 */ 3774, + /* VINSERTPS */ 3776, + /* VLDDQU */ 3780, + /* VLDMXCSR */ 3782, + /* VMASKMOVDQU */ 3783, + /* VMASKMOVPD */ 3784, + /* VMASKMOVPS */ 3788, + /* VMAXPD */ 3792, + /* VMAXPH */ 3802, + /* VMAXPS */ 3808, + /* VMAXSD */ 3818, + /* VMAXSH */ 3822, + /* VMAXSS */ 3824, + /* VMCALL */ 3828, + /* VMCLEAR */ 3829, + /* VMFUNC */ 3830, + /* VMINPD */ 3831, + /* VMINPH */ 3841, + /* VMINPS */ 3847, + /* VMINSD */ 3857, + /* VMINSH */ 3861, + /* VMINSS */ 3863, + /* VMLAUNCH */ 3867, + /* VMLOAD */ 3868, + /* VMMCALL */ 3869, + /* VMOVAPD */ 3870, + /* VMOVAPS */ 3887, + /* VMOVD */ 3904, + /* VMOVDDUP */ 3912, + /* VMOVDQA */ 3922, + /* VMOVDQA32 */ 3930, + /* VMOVDQA64 */ 3939, + /* VMOVDQU */ 3948, + /* VMOVDQU16 */ 3956, + /* VMOVDQU32 */ 3965, + /* VMOVDQU64 */ 3974, + /* VMOVDQU8 */ 3983, + /* VMOVHLPS */ 3992, + /* VMOVHPD */ 3994, + /* VMOVHPS */ 3998, + /* VMOVLHPS */ 4002, + /* VMOVLPD */ 4004, + /* VMOVLPS */ 4008, + /* VMOVMSKPD */ 4012, + /* VMOVMSKPS */ 4014, + /* VMOVNTDQ */ 4016, + /* VMOVNTDQA */ 4021, + /* VMOVNTPD */ 4026, + /* VMOVNTPS */ 4031, + /* VMOVQ */ 4036, + /* VMOVSD */ 4049, + /* VMOVSH */ 4056, + /* VMOVSHDUP */ 4059, + /* VMOVSLDUP */ 4069, + /* VMOVSS */ 4079, + /* VMOVUPD */ 4086, + /* VMOVUPS */ 4103, + /* VMOVW */ 4120, + /* VMPSADBW */ 4124, + /* VMPTRLD */ 4128, + /* VMPTRST */ 4129, + /* VMREAD */ 4130, + /* VMRESUME */ 4134, + /* VMRUN */ 4135, + /* VMSAVE */ 4136, + /* VMULPD */ 4137, + /* VMULPH */ 4147, + /* VMULPS */ 4153, + /* VMULSD */ 4163, + /* VMULSH */ 4167, + /* VMULSS */ 4169, + /* VMWRITE */ 4173, + /* VMXOFF */ 4177, + /* VMXON */ 4178, + /* VORPD */ 4179, + /* VORPS */ 4189, + /* VP2INTERSECTD */ 4199, + /* VP2INTERSECTQ */ 4205, + /* VP4DPWSSD */ 4211, + /* VP4DPWSSDS */ 4212, + /* VPABSB */ 4213, + /* VPABSD */ 4223, + /* VPABSQ */ 4233, + /* VPABSW */ 4239, + /* VPACKSSDW */ 4249, + /* VPACKSSWB */ 4259, + /* VPACKUSDW */ 4269, + /* VPACKUSWB */ 4279, + /* VPADDB */ 4289, + /* VPADDD */ 4299, + /* VPADDQ */ 4309, + /* VPADDSB */ 4319, + /* VPADDSW */ 4329, + /* VPADDUSB */ 4339, + /* VPADDUSW */ 4349, + /* VPADDW */ 4359, + /* VPALIGNR */ 4369, + /* VPAND */ 4379, + /* VPANDD */ 4383, + /* VPANDN */ 4389, + /* VPANDND */ 4393, + /* VPANDNQ */ 4399, + /* VPANDQ */ 4405, + /* VPAVGB */ 4411, + /* VPAVGW */ 4421, + /* VPBLENDD */ 4431, + /* VPBLENDMB */ 4435, + /* VPBLENDMD */ 4441, + /* VPBLENDMQ */ 4447, + /* VPBLENDMW */ 4453, + /* VPBLENDVB */ 4459, + /* VPBLENDW */ 4463, + /* VPBROADCASTB */ 4467, + /* VPBROADCASTD */ 4480, + /* VPBROADCASTMB2Q */ 4493, + /* VPBROADCASTMW2D */ 4496, + /* VPBROADCASTQ */ 4499, + /* VPBROADCASTW */ 4512, + /* VPCLMULQDQ */ 4525, + /* VPCMOV */ 4535, + /* VPCMPB */ 4541, + /* VPCMPD */ 4547, + /* VPCMPEQB */ 4553, + /* VPCMPEQD */ 4563, + /* VPCMPEQQ */ 4573, + /* VPCMPEQW */ 4583, + /* VPCMPESTRI */ 4593, + /* VPCMPESTRI64 */ 4595, + /* VPCMPESTRM */ 4597, + /* VPCMPESTRM64 */ 4599, + /* VPCMPGTB */ 4601, + /* VPCMPGTD */ 4611, + /* VPCMPGTQ */ 4621, + /* VPCMPGTW */ 4631, + /* VPCMPISTRI */ 4641, + /* VPCMPISTRI64 */ 4643, + /* VPCMPISTRM */ 4645, + /* VPCMPQ */ 4647, + /* VPCMPUB */ 4653, + /* VPCMPUD */ 4659, + /* VPCMPUQ */ 4665, + /* VPCMPUW */ 4671, + /* VPCMPW */ 4677, + /* VPCOMB */ 4683, + /* VPCOMD */ 4685, + /* VPCOMPRESSB */ 4687, + /* VPCOMPRESSD */ 4693, + /* VPCOMPRESSQ */ 4699, + /* VPCOMPRESSW */ 4705, + /* VPCOMQ */ 4711, + /* VPCOMUB */ 4713, + /* VPCOMUD */ 4715, + /* VPCOMUQ */ 4717, + /* VPCOMUW */ 4719, + /* VPCOMW */ 4721, + /* VPCONFLICTD */ 4723, + /* VPCONFLICTQ */ 4729, + /* VPDPBUSD */ 4735, + /* VPDPBUSDS */ 4745, + /* VPDPWSSD */ 4755, + /* VPDPWSSDS */ 4765, + /* VPERM2F128 */ 4775, + /* VPERM2I128 */ 4777, + /* VPERMB */ 4779, + /* VPERMD */ 4785, + /* VPERMI2B */ 4791, + /* VPERMI2D */ 4797, + /* VPERMI2PD */ 4803, + /* VPERMI2PS */ 4809, + /* VPERMI2Q */ 4815, + /* VPERMI2W */ 4821, + /* VPERMIL2PD */ 4827, + /* VPERMIL2PS */ 4833, + /* VPERMILPD */ 4839, + /* VPERMILPS */ 4859, + /* VPERMPD */ 4879, + /* VPERMPS */ 4889, + /* VPERMQ */ 4895, + /* VPERMT2B */ 4905, + /* VPERMT2D */ 4911, + /* VPERMT2PD */ 4917, + /* VPERMT2PS */ 4923, + /* VPERMT2Q */ 4929, + /* VPERMT2W */ 4935, + /* VPERMW */ 4941, + /* VPEXPANDB */ 4947, + /* VPEXPANDD */ 4953, + /* VPEXPANDQ */ 4959, + /* VPEXPANDW */ 4965, + /* VPEXTRB */ 4971, + /* VPEXTRD */ 4975, + /* VPEXTRQ */ 4979, + /* VPEXTRW */ 4983, + /* VPEXTRW_C5 */ 4988, + /* VPGATHERDD */ 4989, + /* VPGATHERDQ */ 4994, + /* VPGATHERQD */ 4999, + /* VPGATHERQQ */ 5004, + /* VPHADDBD */ 5009, + /* VPHADDBQ */ 5011, + /* VPHADDBW */ 5013, + /* VPHADDD */ 5015, + /* VPHADDDQ */ 5019, + /* VPHADDSW */ 5021, + /* VPHADDUBD */ 5025, + /* VPHADDUBQ */ 5027, + /* VPHADDUBW */ 5029, + /* VPHADDUDQ */ 5031, + /* VPHADDUWD */ 5033, + /* VPHADDUWQ */ 5035, + /* VPHADDW */ 5037, + /* VPHADDWD */ 5041, + /* VPHADDWQ */ 5043, + /* VPHMINPOSUW */ 5045, + /* VPHSUBBW */ 5047, + /* VPHSUBD */ 5049, + /* VPHSUBDQ */ 5053, + /* VPHSUBSW */ 5055, + /* VPHSUBW */ 5059, + /* VPHSUBWD */ 5063, + /* VPINSRB */ 5065, + /* VPINSRD */ 5069, + /* VPINSRQ */ 5073, + /* VPINSRW */ 5077, + /* VPLZCNTD */ 5081, + /* VPLZCNTQ */ 5087, + /* VPMACSDD */ 5093, + /* VPMACSDQH */ 5095, + /* VPMACSDQL */ 5097, + /* VPMACSSDD */ 5099, + /* VPMACSSDQH */ 5101, + /* VPMACSSDQL */ 5103, + /* VPMACSSWD */ 5105, + /* VPMACSSWW */ 5107, + /* VPMACSWD */ 5109, + /* VPMACSWW */ 5111, + /* VPMADCSSWD */ 5113, + /* VPMADCSWD */ 5115, + /* VPMADD52HUQ */ 5117, + /* VPMADD52LUQ */ 5123, + /* VPMADDUBSW */ 5129, + /* VPMADDWD */ 5139, + /* VPMASKMOVD */ 5149, + /* VPMASKMOVQ */ 5153, + /* VPMAXSB */ 5157, + /* VPMAXSD */ 5167, + /* VPMAXSQ */ 5177, + /* VPMAXSW */ 5183, + /* VPMAXUB */ 5193, + /* VPMAXUD */ 5203, + /* VPMAXUQ */ 5213, + /* VPMAXUW */ 5219, + /* VPMINSB */ 5229, + /* VPMINSD */ 5239, + /* VPMINSQ */ 5249, + /* VPMINSW */ 5255, + /* VPMINUB */ 5265, + /* VPMINUD */ 5275, + /* VPMINUQ */ 5285, + /* VPMINUW */ 5291, + /* VPMOVB2M */ 5301, + /* VPMOVD2M */ 5304, + /* VPMOVDB */ 5307, + /* VPMOVDW */ 5313, + /* VPMOVM2B */ 5319, + /* VPMOVM2D */ 5322, + /* VPMOVM2Q */ 5325, + /* VPMOVM2W */ 5328, + /* VPMOVMSKB */ 5331, + /* VPMOVQ2M */ 5333, + /* VPMOVQB */ 5336, + /* VPMOVQD */ 5342, + /* VPMOVQW */ 5348, + /* VPMOVSDB */ 5354, + /* VPMOVSDW */ 5360, + /* VPMOVSQB */ 5366, + /* VPMOVSQD */ 5372, + /* VPMOVSQW */ 5378, + /* VPMOVSWB */ 5384, + /* VPMOVSXBD */ 5390, + /* VPMOVSXBQ */ 5400, + /* VPMOVSXBW */ 5410, + /* VPMOVSXDQ */ 5420, + /* VPMOVSXWD */ 5430, + /* VPMOVSXWQ */ 5440, + /* VPMOVUSDB */ 5450, + /* VPMOVUSDW */ 5456, + /* VPMOVUSQB */ 5462, + /* VPMOVUSQD */ 5468, + /* VPMOVUSQW */ 5474, + /* VPMOVUSWB */ 5480, + /* VPMOVW2M */ 5486, + /* VPMOVWB */ 5489, + /* VPMOVZXBD */ 5495, + /* VPMOVZXBQ */ 5505, + /* VPMOVZXBW */ 5515, + /* VPMOVZXDQ */ 5525, + /* VPMOVZXWD */ 5535, + /* VPMOVZXWQ */ 5545, + /* VPMULDQ */ 5555, + /* VPMULHRSW */ 5565, + /* VPMULHUW */ 5575, + /* VPMULHW */ 5585, + /* VPMULLD */ 5595, + /* VPMULLQ */ 5605, + /* VPMULLW */ 5611, + /* VPMULTISHIFTQB */ 5621, + /* VPMULUDQ */ 5627, + /* VPOPCNTB */ 5637, + /* VPOPCNTD */ 5643, + /* VPOPCNTQ */ 5649, + /* VPOPCNTW */ 5655, + /* VPOR */ 5661, + /* VPORD */ 5665, + /* VPORQ */ 5671, + /* VPPERM */ 5677, + /* VPROLD */ 5680, + /* VPROLQ */ 5686, + /* VPROLVD */ 5692, + /* VPROLVQ */ 5698, + /* VPRORD */ 5704, + /* VPRORQ */ 5710, + /* VPRORVD */ 5716, + /* VPRORVQ */ 5722, + /* VPROTB */ 5728, + /* VPROTD */ 5733, + /* VPROTQ */ 5738, + /* VPROTW */ 5743, + /* VPSADBW */ 5748, + /* VPSCATTERDD */ 5758, + /* VPSCATTERDQ */ 5761, + /* VPSCATTERQD */ 5764, + /* VPSCATTERQQ */ 5767, + /* VPSHAB */ 5770, + /* VPSHAD */ 5773, + /* VPSHAQ */ 5776, + /* VPSHAW */ 5779, + /* VPSHLB */ 5782, + /* VPSHLD */ 5785, + /* VPSHLDD */ 5788, + /* VPSHLDQ */ 5794, + /* VPSHLDVD */ 5800, + /* VPSHLDVQ */ 5806, + /* VPSHLDVW */ 5812, + /* VPSHLDW */ 5818, + /* VPSHLQ */ 5824, + /* VPSHLW */ 5827, + /* VPSHRDD */ 5830, + /* VPSHRDQ */ 5836, + /* VPSHRDVD */ 5842, + /* VPSHRDVQ */ 5848, + /* VPSHRDVW */ 5854, + /* VPSHRDW */ 5860, + /* VPSHUFB */ 5866, + /* VPSHUFBITQMB */ 5876, + /* VPSHUFD */ 5882, + /* VPSHUFHW */ 5892, + /* VPSHUFLW */ 5902, + /* VPSIGNB */ 5912, + /* VPSIGND */ 5916, + /* VPSIGNW */ 5920, + /* VPSLLD */ 5924, + /* VPSLLDQ */ 5942, + /* VPSLLQ */ 5950, + /* VPSLLVD */ 5968, + /* VPSLLVQ */ 5978, + /* VPSLLVW */ 5988, + /* VPSLLW */ 5994, + /* VPSRAD */ 6012, + /* VPSRAQ */ 6030, + /* VPSRAVD */ 6042, + /* VPSRAVQ */ 6052, + /* VPSRAVW */ 6058, + /* VPSRAW */ 6064, + /* VPSRLD */ 6082, + /* VPSRLDQ */ 6100, + /* VPSRLQ */ 6108, + /* VPSRLVD */ 6126, + /* VPSRLVQ */ 6136, + /* VPSRLVW */ 6146, + /* VPSRLW */ 6152, + /* VPSUBB */ 6170, + /* VPSUBD */ 6180, + /* VPSUBQ */ 6190, + /* VPSUBSB */ 6200, + /* VPSUBSW */ 6210, + /* VPSUBUSB */ 6220, + /* VPSUBUSW */ 6230, + /* VPSUBW */ 6240, + /* VPTERNLOGD */ 6250, + /* VPTERNLOGQ */ 6256, + /* VPTEST */ 6262, + /* VPTESTMB */ 6266, + /* VPTESTMD */ 6272, + /* VPTESTMQ */ 6278, + /* VPTESTMW */ 6284, + /* VPTESTNMB */ 6290, + /* VPTESTNMD */ 6296, + /* VPTESTNMQ */ 6302, + /* VPTESTNMW */ 6308, + /* VPUNPCKHBW */ 6314, + /* VPUNPCKHDQ */ 6324, + /* VPUNPCKHQDQ */ 6334, + /* VPUNPCKHWD */ 6344, + /* VPUNPCKLBW */ 6354, + /* VPUNPCKLDQ */ 6364, + /* VPUNPCKLQDQ */ 6374, + /* VPUNPCKLWD */ 6384, + /* VPXOR */ 6394, + /* VPXORD */ 6398, + /* VPXORQ */ 6404, + /* VRANGEPD */ 6410, + /* VRANGEPS */ 6416, + /* VRANGESD */ 6422, + /* VRANGESS */ 6424, + /* VRCP14PD */ 6426, + /* VRCP14PS */ 6432, + /* VRCP14SD */ 6438, + /* VRCP14SS */ 6440, + /* VRCP28PD */ 6442, + /* VRCP28PS */ 6444, + /* VRCP28SD */ 6446, + /* VRCP28SS */ 6448, + /* VRCPPH */ 6450, + /* VRCPPS */ 6456, + /* VRCPSH */ 6460, + /* VRCPSS */ 6462, + /* VREDUCEPD */ 6464, + /* VREDUCEPH */ 6470, + /* VREDUCEPS */ 6476, + /* VREDUCESD */ 6482, + /* VREDUCESH */ 6484, + /* VREDUCESS */ 6486, + /* VRNDSCALEPD */ 6488, + /* VRNDSCALEPH */ 6494, + /* VRNDSCALEPS */ 6500, + /* VRNDSCALESD */ 6506, + /* VRNDSCALESH */ 6508, + /* VRNDSCALESS */ 6510, + /* VROUNDPD */ 6512, + /* VROUNDPS */ 6516, + /* VROUNDSD */ 6520, + /* VROUNDSS */ 6522, + /* VRSQRT14PD */ 6524, + /* VRSQRT14PS */ 6530, + /* VRSQRT14SD */ 6536, + /* VRSQRT14SS */ 6538, + /* VRSQRT28PD */ 6540, + /* VRSQRT28PS */ 6542, + /* VRSQRT28SD */ 6544, + /* VRSQRT28SS */ 6546, + /* VRSQRTPH */ 6548, + /* VRSQRTPS */ 6554, + /* VRSQRTSH */ 6558, + /* VRSQRTSS */ 6560, + /* VSCALEFPD */ 6562, + /* VSCALEFPH */ 6568, + /* VSCALEFPS */ 6574, + /* VSCALEFSD */ 6580, + /* VSCALEFSH */ 6582, + /* VSCALEFSS */ 6584, + /* VSCATTERDPD */ 6586, + /* VSCATTERDPS */ 6589, + /* VSCATTERPF0DPD */ 6592, + /* VSCATTERPF0DPS */ 6593, + /* VSCATTERPF0QPD */ 6594, + /* VSCATTERPF0QPS */ 6595, + /* VSCATTERPF1DPD */ 6596, + /* VSCATTERPF1DPS */ 6597, + /* VSCATTERPF1QPD */ 6598, + /* VSCATTERPF1QPS */ 6599, + /* VSCATTERQPD */ 6600, + /* VSCATTERQPS */ 6603, + /* VSHUFF32X4 */ 6606, + /* VSHUFF64X2 */ 6610, + /* VSHUFI32X4 */ 6614, + /* VSHUFI64X2 */ 6618, + /* VSHUFPD */ 6622, + /* VSHUFPS */ 6632, + /* VSQRTPD */ 6642, + /* VSQRTPH */ 6652, + /* VSQRTPS */ 6658, + /* VSQRTSD */ 6668, + /* VSQRTSH */ 6672, + /* VSQRTSS */ 6674, + /* VSTMXCSR */ 6678, + /* VSUBPD */ 6679, + /* VSUBPH */ 6689, + /* VSUBPS */ 6695, + /* VSUBSD */ 6705, + /* VSUBSH */ 6709, + /* VSUBSS */ 6711, + /* VTESTPD */ 6715, + /* VTESTPS */ 6719, + /* VUCOMISD */ 6723, + /* VUCOMISH */ 6727, + /* VUCOMISS */ 6729, + /* VUNPCKHPD */ 6733, + /* VUNPCKHPS */ 6743, + /* VUNPCKLPD */ 6753, + /* VUNPCKLPS */ 6763, + /* VXORPD */ 6773, + /* VXORPS */ 6783, + /* VZEROALL */ 6793, + /* VZEROUPPER */ 6794, + /* WBINVD */ 6795, + /* WBNOINVD */ 6796, + /* WRFSBASE */ 6797, + /* WRGSBASE */ 6798, + /* WRMSR */ 6799, + /* WRPKRU */ 6800, + /* WRSSD */ 6801, + /* WRSSQ */ 6802, + /* WRUSSD */ 6803, + /* WRUSSQ */ 6804, + /* XABORT */ 6805, + /* XADD */ 6806, + /* XADD_LOCK */ 6810, + /* XBEGIN */ 6812, + /* XCHG */ 6813, + /* XEND */ 6818, + /* XGETBV */ 6819, + /* XLAT */ 6820, + /* XOR */ 6821, + /* XORPD */ 6839, + /* XORPS */ 6841, + /* XOR_LOCK */ 6843, + /* XRESLDTRK */ 6849, + /* XRSTOR */ 6850, + /* XRSTOR64 */ 6851, + /* XRSTORS */ 6852, + /* XRSTORS64 */ 6853, + /* XSAVE */ 6854, + /* XSAVE64 */ 6855, + /* XSAVEC */ 6856, + /* XSAVEC64 */ 6857, + /* XSAVEOPT */ 6858, + /* XSAVEOPT64 */ 6859, + /* XSAVES */ 6860, + /* XSAVES64 */ 6861, + /* XSETBV */ 6862, + /* XSTORE */ 6863, + /* XSUSLDTRK */ 6864, + /* XTEST */ 6865 +}; diff --git a/CodeVirtualizer/build/obj/xed-iformfl-enum.c b/CodeVirtualizer/build/obj/xed-iformfl-enum.c new file mode 100644 index 0000000..0a6a5ed --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iformfl-enum.c @@ -0,0 +1,3494 @@ +/// @file xed-iformfl-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-iformfl-enum.h" + +xed_iformfl_enum_t xed_iformfl_enum_t_last(void) { + return XED_IFORMFL_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_IFORMFL_AAA_FIRST: + case XED_IFORMFL_AAA_LAST: + case XED_IFORMFL_AAD_FIRST: + case XED_IFORMFL_AAD_LAST: + case XED_IFORMFL_AAM_FIRST: + case XED_IFORMFL_AAM_LAST: + case XED_IFORMFL_AAS_FIRST: + case XED_IFORMFL_AAS_LAST: + case XED_IFORMFL_ADC_FIRST: + case XED_IFORMFL_ADC_LAST: + case XED_IFORMFL_ADCX_FIRST: + case XED_IFORMFL_ADCX_LAST: + case XED_IFORMFL_ADC_LOCK_FIRST: + case XED_IFORMFL_ADC_LOCK_LAST: + case XED_IFORMFL_ADD_FIRST: + case XED_IFORMFL_ADD_LAST: + case XED_IFORMFL_ADDPD_FIRST: + case XED_IFORMFL_ADDPD_LAST: + case XED_IFORMFL_ADDPS_FIRST: + case XED_IFORMFL_ADDPS_LAST: + case XED_IFORMFL_ADDSD_FIRST: + case XED_IFORMFL_ADDSD_LAST: + case XED_IFORMFL_ADDSS_FIRST: + case XED_IFORMFL_ADDSS_LAST: + case XED_IFORMFL_ADDSUBPD_FIRST: + case XED_IFORMFL_ADDSUBPD_LAST: + case XED_IFORMFL_ADDSUBPS_FIRST: + case XED_IFORMFL_ADDSUBPS_LAST: + case XED_IFORMFL_ADD_LOCK_FIRST: + case XED_IFORMFL_ADD_LOCK_LAST: + case XED_IFORMFL_ADOX_FIRST: + case XED_IFORMFL_ADOX_LAST: + case XED_IFORMFL_AESDEC_FIRST: + case XED_IFORMFL_AESDEC_LAST: + case XED_IFORMFL_AESDEC128KL_FIRST: + case XED_IFORMFL_AESDEC128KL_LAST: + case XED_IFORMFL_AESDEC256KL_FIRST: + case XED_IFORMFL_AESDEC256KL_LAST: + case XED_IFORMFL_AESDECLAST_FIRST: + case XED_IFORMFL_AESDECLAST_LAST: + case XED_IFORMFL_AESDECWIDE128KL_FIRST: + case XED_IFORMFL_AESDECWIDE128KL_LAST: + case XED_IFORMFL_AESDECWIDE256KL_FIRST: + case XED_IFORMFL_AESDECWIDE256KL_LAST: + case XED_IFORMFL_AESENC_FIRST: + case XED_IFORMFL_AESENC_LAST: + case XED_IFORMFL_AESENC128KL_FIRST: + case XED_IFORMFL_AESENC128KL_LAST: + case XED_IFORMFL_AESENC256KL_FIRST: + case XED_IFORMFL_AESENC256KL_LAST: + case XED_IFORMFL_AESENCLAST_FIRST: + case XED_IFORMFL_AESENCLAST_LAST: + case XED_IFORMFL_AESENCWIDE128KL_FIRST: + case XED_IFORMFL_AESENCWIDE128KL_LAST: + case XED_IFORMFL_AESENCWIDE256KL_FIRST: + case XED_IFORMFL_AESENCWIDE256KL_LAST: + case XED_IFORMFL_AESIMC_FIRST: + case XED_IFORMFL_AESIMC_LAST: + case XED_IFORMFL_AESKEYGENASSIST_FIRST: + case XED_IFORMFL_AESKEYGENASSIST_LAST: + case XED_IFORMFL_AND_FIRST: + case XED_IFORMFL_AND_LAST: + case XED_IFORMFL_ANDN_FIRST: + case XED_IFORMFL_ANDN_LAST: + case XED_IFORMFL_ANDNPD_FIRST: + case XED_IFORMFL_ANDNPD_LAST: + case XED_IFORMFL_ANDNPS_FIRST: + case XED_IFORMFL_ANDNPS_LAST: + case XED_IFORMFL_ANDPD_FIRST: + case XED_IFORMFL_ANDPD_LAST: + case XED_IFORMFL_ANDPS_FIRST: + case XED_IFORMFL_ANDPS_LAST: + case XED_IFORMFL_AND_LOCK_FIRST: + case XED_IFORMFL_AND_LOCK_LAST: + case XED_IFORMFL_ARPL_FIRST: + case XED_IFORMFL_ARPL_LAST: + case XED_IFORMFL_BEXTR_FIRST: + case XED_IFORMFL_BEXTR_LAST: + case XED_IFORMFL_BEXTR_XOP_FIRST: + case XED_IFORMFL_BEXTR_XOP_LAST: + case XED_IFORMFL_BLCFILL_FIRST: + case XED_IFORMFL_BLCFILL_LAST: + case XED_IFORMFL_BLCI_FIRST: + case XED_IFORMFL_BLCI_LAST: + case XED_IFORMFL_BLCIC_FIRST: + case XED_IFORMFL_BLCIC_LAST: + case XED_IFORMFL_BLCMSK_FIRST: + case XED_IFORMFL_BLCMSK_LAST: + case XED_IFORMFL_BLCS_FIRST: + case XED_IFORMFL_BLCS_LAST: + case XED_IFORMFL_BLENDPD_FIRST: + case XED_IFORMFL_BLENDPD_LAST: + case XED_IFORMFL_BLENDPS_FIRST: + case XED_IFORMFL_BLENDPS_LAST: + case XED_IFORMFL_BLENDVPD_FIRST: + case XED_IFORMFL_BLENDVPD_LAST: + case XED_IFORMFL_BLENDVPS_FIRST: + case XED_IFORMFL_BLENDVPS_LAST: + case XED_IFORMFL_BLSFILL_FIRST: + case XED_IFORMFL_BLSFILL_LAST: + case XED_IFORMFL_BLSI_FIRST: + case XED_IFORMFL_BLSI_LAST: + case XED_IFORMFL_BLSIC_FIRST: + case XED_IFORMFL_BLSIC_LAST: + case XED_IFORMFL_BLSMSK_FIRST: + case XED_IFORMFL_BLSMSK_LAST: + case XED_IFORMFL_BLSR_FIRST: + case XED_IFORMFL_BLSR_LAST: + case XED_IFORMFL_BNDCL_FIRST: + case XED_IFORMFL_BNDCL_LAST: + case XED_IFORMFL_BNDCN_FIRST: + case XED_IFORMFL_BNDCN_LAST: + case XED_IFORMFL_BNDCU_FIRST: + case XED_IFORMFL_BNDCU_LAST: + case XED_IFORMFL_BNDLDX_FIRST: + case XED_IFORMFL_BNDLDX_LAST: + case XED_IFORMFL_BNDMK_FIRST: + case XED_IFORMFL_BNDMK_LAST: + case XED_IFORMFL_BNDMOV_FIRST: + case XED_IFORMFL_BNDMOV_LAST: + case XED_IFORMFL_BNDSTX_FIRST: + case XED_IFORMFL_BNDSTX_LAST: + case XED_IFORMFL_BOUND_FIRST: + case XED_IFORMFL_BOUND_LAST: + case XED_IFORMFL_BSF_FIRST: + case XED_IFORMFL_BSF_LAST: + case XED_IFORMFL_BSR_FIRST: + case XED_IFORMFL_BSR_LAST: + case XED_IFORMFL_BSWAP_FIRST: + case XED_IFORMFL_BSWAP_LAST: + case XED_IFORMFL_BT_FIRST: + case XED_IFORMFL_BT_LAST: + case XED_IFORMFL_BTC_FIRST: + case XED_IFORMFL_BTC_LAST: + case XED_IFORMFL_BTC_LOCK_FIRST: + case XED_IFORMFL_BTC_LOCK_LAST: + case XED_IFORMFL_BTR_FIRST: + case XED_IFORMFL_BTR_LAST: + case XED_IFORMFL_BTR_LOCK_FIRST: + case XED_IFORMFL_BTR_LOCK_LAST: + case XED_IFORMFL_BTS_FIRST: + case XED_IFORMFL_BTS_LAST: + case XED_IFORMFL_BTS_LOCK_FIRST: + case XED_IFORMFL_BTS_LOCK_LAST: + case XED_IFORMFL_BZHI_FIRST: + case XED_IFORMFL_BZHI_LAST: + case XED_IFORMFL_CALL_FAR_FIRST: + case XED_IFORMFL_CALL_FAR_LAST: + case XED_IFORMFL_CALL_NEAR_FIRST: + case XED_IFORMFL_CALL_NEAR_LAST: + case XED_IFORMFL_CBW_FIRST: + case XED_IFORMFL_CBW_LAST: + case XED_IFORMFL_CDQ_FIRST: + case XED_IFORMFL_CDQ_LAST: + case XED_IFORMFL_CDQE_FIRST: + case XED_IFORMFL_CDQE_LAST: + case XED_IFORMFL_CLAC_FIRST: + case XED_IFORMFL_CLAC_LAST: + case XED_IFORMFL_CLC_FIRST: + case XED_IFORMFL_CLC_LAST: + case XED_IFORMFL_CLD_FIRST: + case XED_IFORMFL_CLD_LAST: + case XED_IFORMFL_CLDEMOTE_FIRST: + case XED_IFORMFL_CLDEMOTE_LAST: + case XED_IFORMFL_CLFLUSH_FIRST: + case XED_IFORMFL_CLFLUSH_LAST: + case XED_IFORMFL_CLFLUSHOPT_FIRST: + case XED_IFORMFL_CLFLUSHOPT_LAST: + case XED_IFORMFL_CLGI_FIRST: + case XED_IFORMFL_CLGI_LAST: + case XED_IFORMFL_CLI_FIRST: + case XED_IFORMFL_CLI_LAST: + case XED_IFORMFL_CLRSSBSY_FIRST: + case XED_IFORMFL_CLRSSBSY_LAST: + case XED_IFORMFL_CLTS_FIRST: + case XED_IFORMFL_CLTS_LAST: + case XED_IFORMFL_CLUI_FIRST: + case XED_IFORMFL_CLUI_LAST: + case XED_IFORMFL_CLWB_FIRST: + case XED_IFORMFL_CLWB_LAST: + case XED_IFORMFL_CLZERO_FIRST: + case XED_IFORMFL_CLZERO_LAST: + case XED_IFORMFL_CMC_FIRST: + case XED_IFORMFL_CMC_LAST: + case XED_IFORMFL_CMOVB_FIRST: + case XED_IFORMFL_CMOVB_LAST: + case XED_IFORMFL_CMOVBE_FIRST: + case XED_IFORMFL_CMOVBE_LAST: + case XED_IFORMFL_CMOVL_FIRST: + case XED_IFORMFL_CMOVL_LAST: + case XED_IFORMFL_CMOVLE_FIRST: + case XED_IFORMFL_CMOVLE_LAST: + case XED_IFORMFL_CMOVNB_FIRST: + case XED_IFORMFL_CMOVNB_LAST: + case XED_IFORMFL_CMOVNBE_FIRST: + case XED_IFORMFL_CMOVNBE_LAST: + case XED_IFORMFL_CMOVNL_FIRST: + case XED_IFORMFL_CMOVNL_LAST: + case XED_IFORMFL_CMOVNLE_FIRST: + case XED_IFORMFL_CMOVNLE_LAST: + case XED_IFORMFL_CMOVNO_FIRST: + case XED_IFORMFL_CMOVNO_LAST: + case XED_IFORMFL_CMOVNP_FIRST: + case XED_IFORMFL_CMOVNP_LAST: + case XED_IFORMFL_CMOVNS_FIRST: + case XED_IFORMFL_CMOVNS_LAST: + case XED_IFORMFL_CMOVNZ_FIRST: + case XED_IFORMFL_CMOVNZ_LAST: + case XED_IFORMFL_CMOVO_FIRST: + case XED_IFORMFL_CMOVO_LAST: + case XED_IFORMFL_CMOVP_FIRST: + case XED_IFORMFL_CMOVP_LAST: + case XED_IFORMFL_CMOVS_FIRST: + case XED_IFORMFL_CMOVS_LAST: + case XED_IFORMFL_CMOVZ_FIRST: + case XED_IFORMFL_CMOVZ_LAST: + case XED_IFORMFL_CMP_FIRST: + case XED_IFORMFL_CMP_LAST: + case XED_IFORMFL_CMPPD_FIRST: + case XED_IFORMFL_CMPPD_LAST: + case XED_IFORMFL_CMPPS_FIRST: + case XED_IFORMFL_CMPPS_LAST: + case XED_IFORMFL_CMPSB_FIRST: + case XED_IFORMFL_CMPSB_LAST: + case XED_IFORMFL_CMPSD_FIRST: + case XED_IFORMFL_CMPSD_LAST: + case XED_IFORMFL_CMPSD_XMM_FIRST: + case XED_IFORMFL_CMPSD_XMM_LAST: + case XED_IFORMFL_CMPSQ_FIRST: + case XED_IFORMFL_CMPSQ_LAST: + case XED_IFORMFL_CMPSS_FIRST: + case XED_IFORMFL_CMPSS_LAST: + case XED_IFORMFL_CMPSW_FIRST: + case XED_IFORMFL_CMPSW_LAST: + case XED_IFORMFL_CMPXCHG_FIRST: + case XED_IFORMFL_CMPXCHG_LAST: + case XED_IFORMFL_CMPXCHG16B_FIRST: + case XED_IFORMFL_CMPXCHG16B_LAST: + case XED_IFORMFL_CMPXCHG16B_LOCK_FIRST: + case XED_IFORMFL_CMPXCHG16B_LOCK_LAST: + case XED_IFORMFL_CMPXCHG8B_FIRST: + case XED_IFORMFL_CMPXCHG8B_LAST: + case XED_IFORMFL_CMPXCHG8B_LOCK_FIRST: + case XED_IFORMFL_CMPXCHG8B_LOCK_LAST: + case XED_IFORMFL_CMPXCHG_LOCK_FIRST: + case XED_IFORMFL_CMPXCHG_LOCK_LAST: + case XED_IFORMFL_COMISD_FIRST: + case XED_IFORMFL_COMISD_LAST: + case XED_IFORMFL_COMISS_FIRST: + case XED_IFORMFL_COMISS_LAST: + case XED_IFORMFL_CPUID_FIRST: + case XED_IFORMFL_CPUID_LAST: + case XED_IFORMFL_CQO_FIRST: + case XED_IFORMFL_CQO_LAST: + case XED_IFORMFL_CRC32_FIRST: + case XED_IFORMFL_CRC32_LAST: + case XED_IFORMFL_CVTDQ2PD_FIRST: + case XED_IFORMFL_CVTDQ2PD_LAST: + case XED_IFORMFL_CVTDQ2PS_FIRST: + case XED_IFORMFL_CVTDQ2PS_LAST: + case XED_IFORMFL_CVTPD2DQ_FIRST: + case XED_IFORMFL_CVTPD2DQ_LAST: + case XED_IFORMFL_CVTPD2PI_FIRST: + case XED_IFORMFL_CVTPD2PI_LAST: + case XED_IFORMFL_CVTPD2PS_FIRST: + case XED_IFORMFL_CVTPD2PS_LAST: + case XED_IFORMFL_CVTPI2PD_FIRST: + case XED_IFORMFL_CVTPI2PD_LAST: + case XED_IFORMFL_CVTPI2PS_FIRST: + case XED_IFORMFL_CVTPI2PS_LAST: + case XED_IFORMFL_CVTPS2DQ_FIRST: + case XED_IFORMFL_CVTPS2DQ_LAST: + case XED_IFORMFL_CVTPS2PD_FIRST: + case XED_IFORMFL_CVTPS2PD_LAST: + case XED_IFORMFL_CVTPS2PI_FIRST: + case XED_IFORMFL_CVTPS2PI_LAST: + case XED_IFORMFL_CVTSD2SI_FIRST: + case XED_IFORMFL_CVTSD2SI_LAST: + case XED_IFORMFL_CVTSD2SS_FIRST: + case XED_IFORMFL_CVTSD2SS_LAST: + case XED_IFORMFL_CVTSI2SD_FIRST: + case XED_IFORMFL_CVTSI2SD_LAST: + case XED_IFORMFL_CVTSI2SS_FIRST: + case XED_IFORMFL_CVTSI2SS_LAST: + case XED_IFORMFL_CVTSS2SD_FIRST: + case XED_IFORMFL_CVTSS2SD_LAST: + case XED_IFORMFL_CVTSS2SI_FIRST: + case XED_IFORMFL_CVTSS2SI_LAST: + case XED_IFORMFL_CVTTPD2DQ_FIRST: + case XED_IFORMFL_CVTTPD2DQ_LAST: + case XED_IFORMFL_CVTTPD2PI_FIRST: + case XED_IFORMFL_CVTTPD2PI_LAST: + case XED_IFORMFL_CVTTPS2DQ_FIRST: + case XED_IFORMFL_CVTTPS2DQ_LAST: + case XED_IFORMFL_CVTTPS2PI_FIRST: + case XED_IFORMFL_CVTTPS2PI_LAST: + case XED_IFORMFL_CVTTSD2SI_FIRST: + case XED_IFORMFL_CVTTSD2SI_LAST: + case XED_IFORMFL_CVTTSS2SI_FIRST: + case XED_IFORMFL_CVTTSS2SI_LAST: + case XED_IFORMFL_CWD_FIRST: + case XED_IFORMFL_CWD_LAST: + case XED_IFORMFL_CWDE_FIRST: + case XED_IFORMFL_CWDE_LAST: + case XED_IFORMFL_DAA_FIRST: + case XED_IFORMFL_DAA_LAST: + case XED_IFORMFL_DAS_FIRST: + case XED_IFORMFL_DAS_LAST: + case XED_IFORMFL_DEC_FIRST: + case XED_IFORMFL_DEC_LAST: + case XED_IFORMFL_DEC_LOCK_FIRST: + case XED_IFORMFL_DEC_LOCK_LAST: + case XED_IFORMFL_DIV_FIRST: + case XED_IFORMFL_DIV_LAST: + case XED_IFORMFL_DIVPD_FIRST: + case XED_IFORMFL_DIVPD_LAST: + case XED_IFORMFL_DIVPS_FIRST: + case XED_IFORMFL_DIVPS_LAST: + case XED_IFORMFL_DIVSD_FIRST: + case XED_IFORMFL_DIVSD_LAST: + case XED_IFORMFL_DIVSS_FIRST: + case XED_IFORMFL_DIVSS_LAST: + case XED_IFORMFL_DPPD_FIRST: + case XED_IFORMFL_DPPD_LAST: + case XED_IFORMFL_DPPS_FIRST: + case XED_IFORMFL_DPPS_LAST: + case XED_IFORMFL_EMMS_FIRST: + case XED_IFORMFL_EMMS_LAST: + case XED_IFORMFL_ENCLS_FIRST: + case XED_IFORMFL_ENCLS_LAST: + case XED_IFORMFL_ENCLU_FIRST: + case XED_IFORMFL_ENCLU_LAST: + case XED_IFORMFL_ENCLV_FIRST: + case XED_IFORMFL_ENCLV_LAST: + case XED_IFORMFL_ENCODEKEY128_FIRST: + case XED_IFORMFL_ENCODEKEY128_LAST: + case XED_IFORMFL_ENCODEKEY256_FIRST: + case XED_IFORMFL_ENCODEKEY256_LAST: + case XED_IFORMFL_ENDBR32_FIRST: + case XED_IFORMFL_ENDBR32_LAST: + case XED_IFORMFL_ENDBR64_FIRST: + case XED_IFORMFL_ENDBR64_LAST: + case XED_IFORMFL_ENQCMD_FIRST: + case XED_IFORMFL_ENQCMD_LAST: + case XED_IFORMFL_ENQCMDS_FIRST: + case XED_IFORMFL_ENQCMDS_LAST: + case XED_IFORMFL_ENTER_FIRST: + case XED_IFORMFL_ENTER_LAST: + case XED_IFORMFL_EXTRACTPS_FIRST: + case XED_IFORMFL_EXTRACTPS_LAST: + case XED_IFORMFL_EXTRQ_FIRST: + case XED_IFORMFL_EXTRQ_LAST: + case XED_IFORMFL_F2XM1_FIRST: + case XED_IFORMFL_F2XM1_LAST: + case XED_IFORMFL_FABS_FIRST: + case XED_IFORMFL_FABS_LAST: + case XED_IFORMFL_FADD_FIRST: + case XED_IFORMFL_FADD_LAST: + case XED_IFORMFL_FADDP_FIRST: + case XED_IFORMFL_FADDP_LAST: + case XED_IFORMFL_FBLD_FIRST: + case XED_IFORMFL_FBLD_LAST: + case XED_IFORMFL_FBSTP_FIRST: + case XED_IFORMFL_FBSTP_LAST: + case XED_IFORMFL_FCHS_FIRST: + case XED_IFORMFL_FCHS_LAST: + case XED_IFORMFL_FCMOVB_FIRST: + case XED_IFORMFL_FCMOVB_LAST: + case XED_IFORMFL_FCMOVBE_FIRST: + case XED_IFORMFL_FCMOVBE_LAST: + case XED_IFORMFL_FCMOVE_FIRST: + case XED_IFORMFL_FCMOVE_LAST: + case XED_IFORMFL_FCMOVNB_FIRST: + case XED_IFORMFL_FCMOVNB_LAST: + case XED_IFORMFL_FCMOVNBE_FIRST: + case XED_IFORMFL_FCMOVNBE_LAST: + case XED_IFORMFL_FCMOVNE_FIRST: + case XED_IFORMFL_FCMOVNE_LAST: + case XED_IFORMFL_FCMOVNU_FIRST: + case XED_IFORMFL_FCMOVNU_LAST: + case XED_IFORMFL_FCMOVU_FIRST: + case XED_IFORMFL_FCMOVU_LAST: + case XED_IFORMFL_FCOM_FIRST: + case XED_IFORMFL_FCOM_LAST: + case XED_IFORMFL_FCOMI_FIRST: + case XED_IFORMFL_FCOMI_LAST: + case XED_IFORMFL_FCOMIP_FIRST: + case XED_IFORMFL_FCOMIP_LAST: + case XED_IFORMFL_FCOMP_FIRST: + case XED_IFORMFL_FCOMP_LAST: + case XED_IFORMFL_FCOMPP_FIRST: + case XED_IFORMFL_FCOMPP_LAST: + case XED_IFORMFL_FCOS_FIRST: + case XED_IFORMFL_FCOS_LAST: + case XED_IFORMFL_FDECSTP_FIRST: + case XED_IFORMFL_FDECSTP_LAST: + case XED_IFORMFL_FDISI8087_NOP_FIRST: + case XED_IFORMFL_FDISI8087_NOP_LAST: + case XED_IFORMFL_FDIV_FIRST: + case XED_IFORMFL_FDIV_LAST: + case XED_IFORMFL_FDIVP_FIRST: + case XED_IFORMFL_FDIVP_LAST: + case XED_IFORMFL_FDIVR_FIRST: + case XED_IFORMFL_FDIVR_LAST: + case XED_IFORMFL_FDIVRP_FIRST: + case XED_IFORMFL_FDIVRP_LAST: + case XED_IFORMFL_FEMMS_FIRST: + case XED_IFORMFL_FEMMS_LAST: + case XED_IFORMFL_FENI8087_NOP_FIRST: + case XED_IFORMFL_FENI8087_NOP_LAST: + case XED_IFORMFL_FFREE_FIRST: + case XED_IFORMFL_FFREE_LAST: + case XED_IFORMFL_FFREEP_FIRST: + case XED_IFORMFL_FFREEP_LAST: + case XED_IFORMFL_FIADD_FIRST: + case XED_IFORMFL_FIADD_LAST: + case XED_IFORMFL_FICOM_FIRST: + case XED_IFORMFL_FICOM_LAST: + case XED_IFORMFL_FICOMP_FIRST: + case XED_IFORMFL_FICOMP_LAST: + case XED_IFORMFL_FIDIV_FIRST: + case XED_IFORMFL_FIDIV_LAST: + case XED_IFORMFL_FIDIVR_FIRST: + case XED_IFORMFL_FIDIVR_LAST: + case XED_IFORMFL_FILD_FIRST: + case XED_IFORMFL_FILD_LAST: + case XED_IFORMFL_FIMUL_FIRST: + case XED_IFORMFL_FIMUL_LAST: + case XED_IFORMFL_FINCSTP_FIRST: + case XED_IFORMFL_FINCSTP_LAST: + case XED_IFORMFL_FIST_FIRST: + case XED_IFORMFL_FIST_LAST: + case XED_IFORMFL_FISTP_FIRST: + case XED_IFORMFL_FISTP_LAST: + case XED_IFORMFL_FISTTP_FIRST: + case XED_IFORMFL_FISTTP_LAST: + case XED_IFORMFL_FISUB_FIRST: + case XED_IFORMFL_FISUB_LAST: + case XED_IFORMFL_FISUBR_FIRST: + case XED_IFORMFL_FISUBR_LAST: + case XED_IFORMFL_FLD_FIRST: + case XED_IFORMFL_FLD_LAST: + case XED_IFORMFL_FLD1_FIRST: + case XED_IFORMFL_FLD1_LAST: + case XED_IFORMFL_FLDCW_FIRST: + case XED_IFORMFL_FLDCW_LAST: + case XED_IFORMFL_FLDENV_FIRST: + case XED_IFORMFL_FLDENV_LAST: + case XED_IFORMFL_FLDL2E_FIRST: + case XED_IFORMFL_FLDL2E_LAST: + case XED_IFORMFL_FLDL2T_FIRST: + case XED_IFORMFL_FLDL2T_LAST: + case XED_IFORMFL_FLDLG2_FIRST: + case XED_IFORMFL_FLDLG2_LAST: + case XED_IFORMFL_FLDLN2_FIRST: + case XED_IFORMFL_FLDLN2_LAST: + case XED_IFORMFL_FLDPI_FIRST: + case XED_IFORMFL_FLDPI_LAST: + case XED_IFORMFL_FLDZ_FIRST: + case XED_IFORMFL_FLDZ_LAST: + case XED_IFORMFL_FMUL_FIRST: + case XED_IFORMFL_FMUL_LAST: + case XED_IFORMFL_FMULP_FIRST: + case XED_IFORMFL_FMULP_LAST: + case XED_IFORMFL_FNCLEX_FIRST: + case XED_IFORMFL_FNCLEX_LAST: + case XED_IFORMFL_FNINIT_FIRST: + case XED_IFORMFL_FNINIT_LAST: + case XED_IFORMFL_FNOP_FIRST: + case XED_IFORMFL_FNOP_LAST: + case XED_IFORMFL_FNSAVE_FIRST: + case XED_IFORMFL_FNSAVE_LAST: + case XED_IFORMFL_FNSTCW_FIRST: + case XED_IFORMFL_FNSTCW_LAST: + case XED_IFORMFL_FNSTENV_FIRST: + case XED_IFORMFL_FNSTENV_LAST: + case XED_IFORMFL_FNSTSW_FIRST: + case XED_IFORMFL_FNSTSW_LAST: + case XED_IFORMFL_FPATAN_FIRST: + case XED_IFORMFL_FPATAN_LAST: + case XED_IFORMFL_FPREM_FIRST: + case XED_IFORMFL_FPREM_LAST: + case XED_IFORMFL_FPREM1_FIRST: + case XED_IFORMFL_FPREM1_LAST: + case XED_IFORMFL_FPTAN_FIRST: + case XED_IFORMFL_FPTAN_LAST: + case XED_IFORMFL_FRNDINT_FIRST: + case XED_IFORMFL_FRNDINT_LAST: + case XED_IFORMFL_FRSTOR_FIRST: + case XED_IFORMFL_FRSTOR_LAST: + case XED_IFORMFL_FSCALE_FIRST: + case XED_IFORMFL_FSCALE_LAST: + case XED_IFORMFL_FSETPM287_NOP_FIRST: + case XED_IFORMFL_FSETPM287_NOP_LAST: + case XED_IFORMFL_FSIN_FIRST: + case XED_IFORMFL_FSIN_LAST: + case XED_IFORMFL_FSINCOS_FIRST: + case XED_IFORMFL_FSINCOS_LAST: + case XED_IFORMFL_FSQRT_FIRST: + case XED_IFORMFL_FSQRT_LAST: + case XED_IFORMFL_FST_FIRST: + case XED_IFORMFL_FST_LAST: + case XED_IFORMFL_FSTP_FIRST: + case XED_IFORMFL_FSTP_LAST: + case XED_IFORMFL_FSTPNCE_FIRST: + case XED_IFORMFL_FSTPNCE_LAST: + case XED_IFORMFL_FSUB_FIRST: + case XED_IFORMFL_FSUB_LAST: + case XED_IFORMFL_FSUBP_FIRST: + case XED_IFORMFL_FSUBP_LAST: + case XED_IFORMFL_FSUBR_FIRST: + case XED_IFORMFL_FSUBR_LAST: + case XED_IFORMFL_FSUBRP_FIRST: + case XED_IFORMFL_FSUBRP_LAST: + case XED_IFORMFL_FTST_FIRST: + case XED_IFORMFL_FTST_LAST: + case XED_IFORMFL_FUCOM_FIRST: + case XED_IFORMFL_FUCOM_LAST: + case XED_IFORMFL_FUCOMI_FIRST: + case XED_IFORMFL_FUCOMI_LAST: + case XED_IFORMFL_FUCOMIP_FIRST: + case XED_IFORMFL_FUCOMIP_LAST: + case XED_IFORMFL_FUCOMP_FIRST: + case XED_IFORMFL_FUCOMP_LAST: + case XED_IFORMFL_FUCOMPP_FIRST: + case XED_IFORMFL_FUCOMPP_LAST: + case XED_IFORMFL_FWAIT_FIRST: + case XED_IFORMFL_FWAIT_LAST: + case XED_IFORMFL_FXAM_FIRST: + case XED_IFORMFL_FXAM_LAST: + case XED_IFORMFL_FXCH_FIRST: + case XED_IFORMFL_FXCH_LAST: + case XED_IFORMFL_FXRSTOR_FIRST: + case XED_IFORMFL_FXRSTOR_LAST: + case XED_IFORMFL_FXRSTOR64_FIRST: + case XED_IFORMFL_FXRSTOR64_LAST: + case XED_IFORMFL_FXSAVE_FIRST: + case XED_IFORMFL_FXSAVE_LAST: + case XED_IFORMFL_FXSAVE64_FIRST: + case XED_IFORMFL_FXSAVE64_LAST: + case XED_IFORMFL_FXTRACT_FIRST: + case XED_IFORMFL_FXTRACT_LAST: + case XED_IFORMFL_FYL2X_FIRST: + case XED_IFORMFL_FYL2X_LAST: + case XED_IFORMFL_FYL2XP1_FIRST: + case XED_IFORMFL_FYL2XP1_LAST: + case XED_IFORMFL_GETSEC_FIRST: + case XED_IFORMFL_GETSEC_LAST: + case XED_IFORMFL_GF2P8AFFINEINVQB_FIRST: + case XED_IFORMFL_GF2P8AFFINEINVQB_LAST: + case XED_IFORMFL_GF2P8AFFINEQB_FIRST: + case XED_IFORMFL_GF2P8AFFINEQB_LAST: + case XED_IFORMFL_GF2P8MULB_FIRST: + case XED_IFORMFL_GF2P8MULB_LAST: + case XED_IFORMFL_HADDPD_FIRST: + case XED_IFORMFL_HADDPD_LAST: + case XED_IFORMFL_HADDPS_FIRST: + case XED_IFORMFL_HADDPS_LAST: + case XED_IFORMFL_HLT_FIRST: + case XED_IFORMFL_HLT_LAST: + case XED_IFORMFL_HRESET_FIRST: + case XED_IFORMFL_HRESET_LAST: + case XED_IFORMFL_HSUBPD_FIRST: + case XED_IFORMFL_HSUBPD_LAST: + case XED_IFORMFL_HSUBPS_FIRST: + case XED_IFORMFL_HSUBPS_LAST: + case XED_IFORMFL_IDIV_FIRST: + case XED_IFORMFL_IDIV_LAST: + case XED_IFORMFL_IMUL_FIRST: + case XED_IFORMFL_IMUL_LAST: + case XED_IFORMFL_IN_FIRST: + case XED_IFORMFL_IN_LAST: + case XED_IFORMFL_INC_FIRST: + case XED_IFORMFL_INC_LAST: + case XED_IFORMFL_INCSSPD_FIRST: + case XED_IFORMFL_INCSSPD_LAST: + case XED_IFORMFL_INCSSPQ_FIRST: + case XED_IFORMFL_INCSSPQ_LAST: + case XED_IFORMFL_INC_LOCK_FIRST: + case XED_IFORMFL_INC_LOCK_LAST: + case XED_IFORMFL_INSB_FIRST: + case XED_IFORMFL_INSB_LAST: + case XED_IFORMFL_INSD_FIRST: + case XED_IFORMFL_INSD_LAST: + case XED_IFORMFL_INSERTPS_FIRST: + case XED_IFORMFL_INSERTPS_LAST: + case XED_IFORMFL_INSERTQ_FIRST: + case XED_IFORMFL_INSERTQ_LAST: + case XED_IFORMFL_INSW_FIRST: + case XED_IFORMFL_INSW_LAST: + case XED_IFORMFL_INT_FIRST: + case XED_IFORMFL_INT_LAST: + case XED_IFORMFL_INT1_FIRST: + case XED_IFORMFL_INT1_LAST: + case XED_IFORMFL_INT3_FIRST: + case XED_IFORMFL_INT3_LAST: + case XED_IFORMFL_INTO_FIRST: + case XED_IFORMFL_INTO_LAST: + case XED_IFORMFL_INVD_FIRST: + case XED_IFORMFL_INVD_LAST: + case XED_IFORMFL_INVEPT_FIRST: + case XED_IFORMFL_INVEPT_LAST: + case XED_IFORMFL_INVLPG_FIRST: + case XED_IFORMFL_INVLPG_LAST: + case XED_IFORMFL_INVLPGA_FIRST: + case XED_IFORMFL_INVLPGA_LAST: + case XED_IFORMFL_INVLPGB_FIRST: + case XED_IFORMFL_INVLPGB_LAST: + case XED_IFORMFL_INVPCID_FIRST: + case XED_IFORMFL_INVPCID_LAST: + case XED_IFORMFL_INVVPID_FIRST: + case XED_IFORMFL_INVVPID_LAST: + case XED_IFORMFL_IRET_FIRST: + case XED_IFORMFL_IRET_LAST: + case XED_IFORMFL_IRETD_FIRST: + case XED_IFORMFL_IRETD_LAST: + case XED_IFORMFL_IRETQ_FIRST: + case XED_IFORMFL_IRETQ_LAST: + case XED_IFORMFL_JB_FIRST: + case XED_IFORMFL_JB_LAST: + case XED_IFORMFL_JBE_FIRST: + case XED_IFORMFL_JBE_LAST: + case XED_IFORMFL_JCXZ_FIRST: + case XED_IFORMFL_JCXZ_LAST: + case XED_IFORMFL_JECXZ_FIRST: + case XED_IFORMFL_JECXZ_LAST: + case XED_IFORMFL_JL_FIRST: + case XED_IFORMFL_JL_LAST: + case XED_IFORMFL_JLE_FIRST: + case XED_IFORMFL_JLE_LAST: + case XED_IFORMFL_JMP_FIRST: + case XED_IFORMFL_JMP_LAST: + case XED_IFORMFL_JMP_FAR_FIRST: + case XED_IFORMFL_JMP_FAR_LAST: + case XED_IFORMFL_JNB_FIRST: + case XED_IFORMFL_JNB_LAST: + case XED_IFORMFL_JNBE_FIRST: + case XED_IFORMFL_JNBE_LAST: + case XED_IFORMFL_JNL_FIRST: + case XED_IFORMFL_JNL_LAST: + case XED_IFORMFL_JNLE_FIRST: + case XED_IFORMFL_JNLE_LAST: + case XED_IFORMFL_JNO_FIRST: + case XED_IFORMFL_JNO_LAST: + case XED_IFORMFL_JNP_FIRST: + case XED_IFORMFL_JNP_LAST: + case XED_IFORMFL_JNS_FIRST: + case XED_IFORMFL_JNS_LAST: + case XED_IFORMFL_JNZ_FIRST: + case XED_IFORMFL_JNZ_LAST: + case XED_IFORMFL_JO_FIRST: + case XED_IFORMFL_JO_LAST: + case XED_IFORMFL_JP_FIRST: + case XED_IFORMFL_JP_LAST: + case XED_IFORMFL_JRCXZ_FIRST: + case XED_IFORMFL_JRCXZ_LAST: + case XED_IFORMFL_JS_FIRST: + case XED_IFORMFL_JS_LAST: + case XED_IFORMFL_JZ_FIRST: + case XED_IFORMFL_JZ_LAST: + case XED_IFORMFL_KADDB_FIRST: + case XED_IFORMFL_KADDB_LAST: + case XED_IFORMFL_KADDD_FIRST: + case XED_IFORMFL_KADDD_LAST: + case XED_IFORMFL_KADDQ_FIRST: + case XED_IFORMFL_KADDQ_LAST: + case XED_IFORMFL_KADDW_FIRST: + case XED_IFORMFL_KADDW_LAST: + case XED_IFORMFL_KANDB_FIRST: + case XED_IFORMFL_KANDB_LAST: + case XED_IFORMFL_KANDD_FIRST: + case XED_IFORMFL_KANDD_LAST: + case XED_IFORMFL_KANDNB_FIRST: + case XED_IFORMFL_KANDNB_LAST: + case XED_IFORMFL_KANDND_FIRST: + case XED_IFORMFL_KANDND_LAST: + case XED_IFORMFL_KANDNQ_FIRST: + case XED_IFORMFL_KANDNQ_LAST: + case XED_IFORMFL_KANDNW_FIRST: + case XED_IFORMFL_KANDNW_LAST: + case XED_IFORMFL_KANDQ_FIRST: + case XED_IFORMFL_KANDQ_LAST: + case XED_IFORMFL_KANDW_FIRST: + case XED_IFORMFL_KANDW_LAST: + case XED_IFORMFL_KMOVB_FIRST: + case XED_IFORMFL_KMOVB_LAST: + case XED_IFORMFL_KMOVD_FIRST: + case XED_IFORMFL_KMOVD_LAST: + case XED_IFORMFL_KMOVQ_FIRST: + case XED_IFORMFL_KMOVQ_LAST: + case XED_IFORMFL_KMOVW_FIRST: + case XED_IFORMFL_KMOVW_LAST: + case XED_IFORMFL_KNOTB_FIRST: + case XED_IFORMFL_KNOTB_LAST: + case XED_IFORMFL_KNOTD_FIRST: + case XED_IFORMFL_KNOTD_LAST: + case XED_IFORMFL_KNOTQ_FIRST: + case XED_IFORMFL_KNOTQ_LAST: + case XED_IFORMFL_KNOTW_FIRST: + case XED_IFORMFL_KNOTW_LAST: + case XED_IFORMFL_KORB_FIRST: + case XED_IFORMFL_KORB_LAST: + case XED_IFORMFL_KORD_FIRST: + case XED_IFORMFL_KORD_LAST: + case XED_IFORMFL_KORQ_FIRST: + case XED_IFORMFL_KORQ_LAST: + case XED_IFORMFL_KORTESTB_FIRST: + case XED_IFORMFL_KORTESTB_LAST: + case XED_IFORMFL_KORTESTD_FIRST: + case XED_IFORMFL_KORTESTD_LAST: + case XED_IFORMFL_KORTESTQ_FIRST: + case XED_IFORMFL_KORTESTQ_LAST: + case XED_IFORMFL_KORTESTW_FIRST: + case XED_IFORMFL_KORTESTW_LAST: + case XED_IFORMFL_KORW_FIRST: + case XED_IFORMFL_KORW_LAST: + case XED_IFORMFL_KSHIFTLB_FIRST: + case XED_IFORMFL_KSHIFTLB_LAST: + case XED_IFORMFL_KSHIFTLD_FIRST: + case XED_IFORMFL_KSHIFTLD_LAST: + case XED_IFORMFL_KSHIFTLQ_FIRST: + case XED_IFORMFL_KSHIFTLQ_LAST: + case XED_IFORMFL_KSHIFTLW_FIRST: + case XED_IFORMFL_KSHIFTLW_LAST: + case XED_IFORMFL_KSHIFTRB_FIRST: + case XED_IFORMFL_KSHIFTRB_LAST: + case XED_IFORMFL_KSHIFTRD_FIRST: + case XED_IFORMFL_KSHIFTRD_LAST: + case XED_IFORMFL_KSHIFTRQ_FIRST: + case XED_IFORMFL_KSHIFTRQ_LAST: + case XED_IFORMFL_KSHIFTRW_FIRST: + case XED_IFORMFL_KSHIFTRW_LAST: + case XED_IFORMFL_KTESTB_FIRST: + case XED_IFORMFL_KTESTB_LAST: + case XED_IFORMFL_KTESTD_FIRST: + case XED_IFORMFL_KTESTD_LAST: + case XED_IFORMFL_KTESTQ_FIRST: + case XED_IFORMFL_KTESTQ_LAST: + case XED_IFORMFL_KTESTW_FIRST: + case XED_IFORMFL_KTESTW_LAST: + case XED_IFORMFL_KUNPCKBW_FIRST: + case XED_IFORMFL_KUNPCKBW_LAST: + case XED_IFORMFL_KUNPCKDQ_FIRST: + case XED_IFORMFL_KUNPCKDQ_LAST: + case XED_IFORMFL_KUNPCKWD_FIRST: + case XED_IFORMFL_KUNPCKWD_LAST: + case XED_IFORMFL_KXNORB_FIRST: + case XED_IFORMFL_KXNORB_LAST: + case XED_IFORMFL_KXNORD_FIRST: + case XED_IFORMFL_KXNORD_LAST: + case XED_IFORMFL_KXNORQ_FIRST: + case XED_IFORMFL_KXNORQ_LAST: + case XED_IFORMFL_KXNORW_FIRST: + case XED_IFORMFL_KXNORW_LAST: + case XED_IFORMFL_KXORB_FIRST: + case XED_IFORMFL_KXORB_LAST: + case XED_IFORMFL_KXORD_FIRST: + case XED_IFORMFL_KXORD_LAST: + case XED_IFORMFL_KXORQ_FIRST: + case XED_IFORMFL_KXORQ_LAST: + case XED_IFORMFL_KXORW_FIRST: + case XED_IFORMFL_KXORW_LAST: + case XED_IFORMFL_LAHF_FIRST: + case XED_IFORMFL_LAHF_LAST: + case XED_IFORMFL_LAR_FIRST: + case XED_IFORMFL_LAR_LAST: + case XED_IFORMFL_LDDQU_FIRST: + case XED_IFORMFL_LDDQU_LAST: + case XED_IFORMFL_LDMXCSR_FIRST: + case XED_IFORMFL_LDMXCSR_LAST: + case XED_IFORMFL_LDS_FIRST: + case XED_IFORMFL_LDS_LAST: + case XED_IFORMFL_LDTILECFG_FIRST: + case XED_IFORMFL_LDTILECFG_LAST: + case XED_IFORMFL_LEA_FIRST: + case XED_IFORMFL_LEA_LAST: + case XED_IFORMFL_LEAVE_FIRST: + case XED_IFORMFL_LEAVE_LAST: + case XED_IFORMFL_LES_FIRST: + case XED_IFORMFL_LES_LAST: + case XED_IFORMFL_LFENCE_FIRST: + case XED_IFORMFL_LFENCE_LAST: + case XED_IFORMFL_LFS_FIRST: + case XED_IFORMFL_LFS_LAST: + case XED_IFORMFL_LGDT_FIRST: + case XED_IFORMFL_LGDT_LAST: + case XED_IFORMFL_LGS_FIRST: + case XED_IFORMFL_LGS_LAST: + case XED_IFORMFL_LIDT_FIRST: + case XED_IFORMFL_LIDT_LAST: + case XED_IFORMFL_LLDT_FIRST: + case XED_IFORMFL_LLDT_LAST: + case XED_IFORMFL_LLWPCB_FIRST: + case XED_IFORMFL_LLWPCB_LAST: + case XED_IFORMFL_LMSW_FIRST: + case XED_IFORMFL_LMSW_LAST: + case XED_IFORMFL_LOADIWKEY_FIRST: + case XED_IFORMFL_LOADIWKEY_LAST: + case XED_IFORMFL_LODSB_FIRST: + case XED_IFORMFL_LODSB_LAST: + case XED_IFORMFL_LODSD_FIRST: + case XED_IFORMFL_LODSD_LAST: + case XED_IFORMFL_LODSQ_FIRST: + case XED_IFORMFL_LODSQ_LAST: + case XED_IFORMFL_LODSW_FIRST: + case XED_IFORMFL_LODSW_LAST: + case XED_IFORMFL_LOOP_FIRST: + case XED_IFORMFL_LOOP_LAST: + case XED_IFORMFL_LOOPE_FIRST: + case XED_IFORMFL_LOOPE_LAST: + case XED_IFORMFL_LOOPNE_FIRST: + case XED_IFORMFL_LOOPNE_LAST: + case XED_IFORMFL_LSL_FIRST: + case XED_IFORMFL_LSL_LAST: + case XED_IFORMFL_LSS_FIRST: + case XED_IFORMFL_LSS_LAST: + case XED_IFORMFL_LTR_FIRST: + case XED_IFORMFL_LTR_LAST: + case XED_IFORMFL_LWPINS_FIRST: + case XED_IFORMFL_LWPINS_LAST: + case XED_IFORMFL_LWPVAL_FIRST: + case XED_IFORMFL_LWPVAL_LAST: + case XED_IFORMFL_LZCNT_FIRST: + case XED_IFORMFL_LZCNT_LAST: + case XED_IFORMFL_MASKMOVDQU_FIRST: + case XED_IFORMFL_MASKMOVDQU_LAST: + case XED_IFORMFL_MASKMOVQ_FIRST: + case XED_IFORMFL_MASKMOVQ_LAST: + case XED_IFORMFL_MAXPD_FIRST: + case XED_IFORMFL_MAXPD_LAST: + case XED_IFORMFL_MAXPS_FIRST: + case XED_IFORMFL_MAXPS_LAST: + case XED_IFORMFL_MAXSD_FIRST: + case XED_IFORMFL_MAXSD_LAST: + case XED_IFORMFL_MAXSS_FIRST: + case XED_IFORMFL_MAXSS_LAST: + case XED_IFORMFL_MCOMMIT_FIRST: + case XED_IFORMFL_MCOMMIT_LAST: + case XED_IFORMFL_MFENCE_FIRST: + case XED_IFORMFL_MFENCE_LAST: + case XED_IFORMFL_MINPD_FIRST: + case XED_IFORMFL_MINPD_LAST: + case XED_IFORMFL_MINPS_FIRST: + case XED_IFORMFL_MINPS_LAST: + case XED_IFORMFL_MINSD_FIRST: + case XED_IFORMFL_MINSD_LAST: + case XED_IFORMFL_MINSS_FIRST: + case XED_IFORMFL_MINSS_LAST: + case XED_IFORMFL_MONITOR_FIRST: + case XED_IFORMFL_MONITOR_LAST: + case XED_IFORMFL_MONITORX_FIRST: + case XED_IFORMFL_MONITORX_LAST: + case XED_IFORMFL_MOV_FIRST: + case XED_IFORMFL_MOV_LAST: + case XED_IFORMFL_MOVAPD_FIRST: + case XED_IFORMFL_MOVAPD_LAST: + case XED_IFORMFL_MOVAPS_FIRST: + case XED_IFORMFL_MOVAPS_LAST: + case XED_IFORMFL_MOVBE_FIRST: + case XED_IFORMFL_MOVBE_LAST: + case XED_IFORMFL_MOVD_FIRST: + case XED_IFORMFL_MOVD_LAST: + case XED_IFORMFL_MOVDDUP_FIRST: + case XED_IFORMFL_MOVDDUP_LAST: + case XED_IFORMFL_MOVDIR64B_FIRST: + case XED_IFORMFL_MOVDIR64B_LAST: + case XED_IFORMFL_MOVDIRI_FIRST: + case XED_IFORMFL_MOVDIRI_LAST: + case XED_IFORMFL_MOVDQ2Q_FIRST: + case XED_IFORMFL_MOVDQ2Q_LAST: + case XED_IFORMFL_MOVDQA_FIRST: + case XED_IFORMFL_MOVDQA_LAST: + case XED_IFORMFL_MOVDQU_FIRST: + case XED_IFORMFL_MOVDQU_LAST: + case XED_IFORMFL_MOVHLPS_FIRST: + case XED_IFORMFL_MOVHLPS_LAST: + case XED_IFORMFL_MOVHPD_FIRST: + case XED_IFORMFL_MOVHPD_LAST: + case XED_IFORMFL_MOVHPS_FIRST: + case XED_IFORMFL_MOVHPS_LAST: + case XED_IFORMFL_MOVLHPS_FIRST: + case XED_IFORMFL_MOVLHPS_LAST: + case XED_IFORMFL_MOVLPD_FIRST: + case XED_IFORMFL_MOVLPD_LAST: + case XED_IFORMFL_MOVLPS_FIRST: + case XED_IFORMFL_MOVLPS_LAST: + case XED_IFORMFL_MOVMSKPD_FIRST: + case XED_IFORMFL_MOVMSKPD_LAST: + case XED_IFORMFL_MOVMSKPS_FIRST: + case XED_IFORMFL_MOVMSKPS_LAST: + case XED_IFORMFL_MOVNTDQ_FIRST: + case XED_IFORMFL_MOVNTDQ_LAST: + case XED_IFORMFL_MOVNTDQA_FIRST: + case XED_IFORMFL_MOVNTDQA_LAST: + case XED_IFORMFL_MOVNTI_FIRST: + case XED_IFORMFL_MOVNTI_LAST: + case XED_IFORMFL_MOVNTPD_FIRST: + case XED_IFORMFL_MOVNTPD_LAST: + case XED_IFORMFL_MOVNTPS_FIRST: + case XED_IFORMFL_MOVNTPS_LAST: + case XED_IFORMFL_MOVNTQ_FIRST: + case XED_IFORMFL_MOVNTQ_LAST: + case XED_IFORMFL_MOVNTSD_FIRST: + case XED_IFORMFL_MOVNTSD_LAST: + case XED_IFORMFL_MOVNTSS_FIRST: + case XED_IFORMFL_MOVNTSS_LAST: + case XED_IFORMFL_MOVQ_FIRST: + case XED_IFORMFL_MOVQ_LAST: + case XED_IFORMFL_MOVQ2DQ_FIRST: + case XED_IFORMFL_MOVQ2DQ_LAST: + case XED_IFORMFL_MOVSB_FIRST: + case XED_IFORMFL_MOVSB_LAST: + case XED_IFORMFL_MOVSD_FIRST: + case XED_IFORMFL_MOVSD_LAST: + case XED_IFORMFL_MOVSD_XMM_FIRST: + case XED_IFORMFL_MOVSD_XMM_LAST: + case XED_IFORMFL_MOVSHDUP_FIRST: + case XED_IFORMFL_MOVSHDUP_LAST: + case XED_IFORMFL_MOVSLDUP_FIRST: + case XED_IFORMFL_MOVSLDUP_LAST: + case XED_IFORMFL_MOVSQ_FIRST: + case XED_IFORMFL_MOVSQ_LAST: + case XED_IFORMFL_MOVSS_FIRST: + case XED_IFORMFL_MOVSS_LAST: + case XED_IFORMFL_MOVSW_FIRST: + case XED_IFORMFL_MOVSW_LAST: + case XED_IFORMFL_MOVSX_FIRST: + case XED_IFORMFL_MOVSX_LAST: + case XED_IFORMFL_MOVSXD_FIRST: + case XED_IFORMFL_MOVSXD_LAST: + case XED_IFORMFL_MOVUPD_FIRST: + case XED_IFORMFL_MOVUPD_LAST: + case XED_IFORMFL_MOVUPS_FIRST: + case XED_IFORMFL_MOVUPS_LAST: + case XED_IFORMFL_MOVZX_FIRST: + case XED_IFORMFL_MOVZX_LAST: + case XED_IFORMFL_MOV_CR_FIRST: + case XED_IFORMFL_MOV_CR_LAST: + case XED_IFORMFL_MOV_DR_FIRST: + case XED_IFORMFL_MOV_DR_LAST: + case XED_IFORMFL_MPSADBW_FIRST: + case XED_IFORMFL_MPSADBW_LAST: + case XED_IFORMFL_MUL_FIRST: + case XED_IFORMFL_MUL_LAST: + case XED_IFORMFL_MULPD_FIRST: + case XED_IFORMFL_MULPD_LAST: + case XED_IFORMFL_MULPS_FIRST: + case XED_IFORMFL_MULPS_LAST: + case XED_IFORMFL_MULSD_FIRST: + case XED_IFORMFL_MULSD_LAST: + case XED_IFORMFL_MULSS_FIRST: + case XED_IFORMFL_MULSS_LAST: + case XED_IFORMFL_MULX_FIRST: + case XED_IFORMFL_MULX_LAST: + case XED_IFORMFL_MWAIT_FIRST: + case XED_IFORMFL_MWAIT_LAST: + case XED_IFORMFL_MWAITX_FIRST: + case XED_IFORMFL_MWAITX_LAST: + case XED_IFORMFL_NEG_FIRST: + case XED_IFORMFL_NEG_LAST: + case XED_IFORMFL_NEG_LOCK_FIRST: + case XED_IFORMFL_NEG_LOCK_LAST: + case XED_IFORMFL_NOP_FIRST: + case XED_IFORMFL_NOP_LAST: + case XED_IFORMFL_NOT_FIRST: + case XED_IFORMFL_NOT_LAST: + case XED_IFORMFL_NOT_LOCK_FIRST: + case XED_IFORMFL_NOT_LOCK_LAST: + case XED_IFORMFL_OR_FIRST: + case XED_IFORMFL_OR_LAST: + case XED_IFORMFL_ORPD_FIRST: + case XED_IFORMFL_ORPD_LAST: + case XED_IFORMFL_ORPS_FIRST: + case XED_IFORMFL_ORPS_LAST: + case XED_IFORMFL_OR_LOCK_FIRST: + case XED_IFORMFL_OR_LOCK_LAST: + case XED_IFORMFL_OUT_FIRST: + case XED_IFORMFL_OUT_LAST: + case XED_IFORMFL_OUTSB_FIRST: + case XED_IFORMFL_OUTSB_LAST: + case XED_IFORMFL_OUTSD_FIRST: + case XED_IFORMFL_OUTSD_LAST: + case XED_IFORMFL_OUTSW_FIRST: + case XED_IFORMFL_OUTSW_LAST: + case XED_IFORMFL_PABSB_FIRST: + case XED_IFORMFL_PABSB_LAST: + case XED_IFORMFL_PABSD_FIRST: + case XED_IFORMFL_PABSD_LAST: + case XED_IFORMFL_PABSW_FIRST: + case XED_IFORMFL_PABSW_LAST: + case XED_IFORMFL_PACKSSDW_FIRST: + case XED_IFORMFL_PACKSSDW_LAST: + case XED_IFORMFL_PACKSSWB_FIRST: + case XED_IFORMFL_PACKSSWB_LAST: + case XED_IFORMFL_PACKUSDW_FIRST: + case XED_IFORMFL_PACKUSDW_LAST: + case XED_IFORMFL_PACKUSWB_FIRST: + case XED_IFORMFL_PACKUSWB_LAST: + case XED_IFORMFL_PADDB_FIRST: + case XED_IFORMFL_PADDB_LAST: + case XED_IFORMFL_PADDD_FIRST: + case XED_IFORMFL_PADDD_LAST: + case XED_IFORMFL_PADDQ_FIRST: + case XED_IFORMFL_PADDQ_LAST: + case XED_IFORMFL_PADDSB_FIRST: + case XED_IFORMFL_PADDSB_LAST: + case XED_IFORMFL_PADDSW_FIRST: + case XED_IFORMFL_PADDSW_LAST: + case XED_IFORMFL_PADDUSB_FIRST: + case XED_IFORMFL_PADDUSB_LAST: + case XED_IFORMFL_PADDUSW_FIRST: + case XED_IFORMFL_PADDUSW_LAST: + case XED_IFORMFL_PADDW_FIRST: + case XED_IFORMFL_PADDW_LAST: + case XED_IFORMFL_PALIGNR_FIRST: + case XED_IFORMFL_PALIGNR_LAST: + case XED_IFORMFL_PAND_FIRST: + case XED_IFORMFL_PAND_LAST: + case XED_IFORMFL_PANDN_FIRST: + case XED_IFORMFL_PANDN_LAST: + case XED_IFORMFL_PAUSE_FIRST: + case XED_IFORMFL_PAUSE_LAST: + case XED_IFORMFL_PAVGB_FIRST: + case XED_IFORMFL_PAVGB_LAST: + case XED_IFORMFL_PAVGUSB_FIRST: + case XED_IFORMFL_PAVGUSB_LAST: + case XED_IFORMFL_PAVGW_FIRST: + case XED_IFORMFL_PAVGW_LAST: + case XED_IFORMFL_PBLENDVB_FIRST: + case XED_IFORMFL_PBLENDVB_LAST: + case XED_IFORMFL_PBLENDW_FIRST: + case XED_IFORMFL_PBLENDW_LAST: + case XED_IFORMFL_PCLMULQDQ_FIRST: + case XED_IFORMFL_PCLMULQDQ_LAST: + case XED_IFORMFL_PCMPEQB_FIRST: + case XED_IFORMFL_PCMPEQB_LAST: + case XED_IFORMFL_PCMPEQD_FIRST: + case XED_IFORMFL_PCMPEQD_LAST: + case XED_IFORMFL_PCMPEQQ_FIRST: + case XED_IFORMFL_PCMPEQQ_LAST: + case XED_IFORMFL_PCMPEQW_FIRST: + case XED_IFORMFL_PCMPEQW_LAST: + case XED_IFORMFL_PCMPESTRI_FIRST: + case XED_IFORMFL_PCMPESTRI_LAST: + case XED_IFORMFL_PCMPESTRI64_FIRST: + case XED_IFORMFL_PCMPESTRI64_LAST: + case XED_IFORMFL_PCMPESTRM_FIRST: + case XED_IFORMFL_PCMPESTRM_LAST: + case XED_IFORMFL_PCMPESTRM64_FIRST: + case XED_IFORMFL_PCMPESTRM64_LAST: + case XED_IFORMFL_PCMPGTB_FIRST: + case XED_IFORMFL_PCMPGTB_LAST: + case XED_IFORMFL_PCMPGTD_FIRST: + case XED_IFORMFL_PCMPGTD_LAST: + case XED_IFORMFL_PCMPGTQ_FIRST: + case XED_IFORMFL_PCMPGTQ_LAST: + case XED_IFORMFL_PCMPGTW_FIRST: + case XED_IFORMFL_PCMPGTW_LAST: + case XED_IFORMFL_PCMPISTRI_FIRST: + case XED_IFORMFL_PCMPISTRI_LAST: + case XED_IFORMFL_PCMPISTRI64_FIRST: + case XED_IFORMFL_PCMPISTRI64_LAST: + case XED_IFORMFL_PCMPISTRM_FIRST: + case XED_IFORMFL_PCMPISTRM_LAST: + case XED_IFORMFL_PCONFIG_FIRST: + case XED_IFORMFL_PCONFIG_LAST: + case XED_IFORMFL_PDEP_FIRST: + case XED_IFORMFL_PDEP_LAST: + case XED_IFORMFL_PEXT_FIRST: + case XED_IFORMFL_PEXT_LAST: + case XED_IFORMFL_PEXTRB_FIRST: + case XED_IFORMFL_PEXTRB_LAST: + case XED_IFORMFL_PEXTRD_FIRST: + case XED_IFORMFL_PEXTRD_LAST: + case XED_IFORMFL_PEXTRQ_FIRST: + case XED_IFORMFL_PEXTRQ_LAST: + case XED_IFORMFL_PEXTRW_FIRST: + case XED_IFORMFL_PEXTRW_LAST: + case XED_IFORMFL_PEXTRW_SSE4_FIRST: + case XED_IFORMFL_PEXTRW_SSE4_LAST: + case XED_IFORMFL_PF2ID_FIRST: + case XED_IFORMFL_PF2ID_LAST: + case XED_IFORMFL_PF2IW_FIRST: + case XED_IFORMFL_PF2IW_LAST: + case XED_IFORMFL_PFACC_FIRST: + case XED_IFORMFL_PFACC_LAST: + case XED_IFORMFL_PFADD_FIRST: + case XED_IFORMFL_PFADD_LAST: + case XED_IFORMFL_PFCMPEQ_FIRST: + case XED_IFORMFL_PFCMPEQ_LAST: + case XED_IFORMFL_PFCMPGE_FIRST: + case XED_IFORMFL_PFCMPGE_LAST: + case XED_IFORMFL_PFCMPGT_FIRST: + case XED_IFORMFL_PFCMPGT_LAST: + case XED_IFORMFL_PFMAX_FIRST: + case XED_IFORMFL_PFMAX_LAST: + case XED_IFORMFL_PFMIN_FIRST: + case XED_IFORMFL_PFMIN_LAST: + case XED_IFORMFL_PFMUL_FIRST: + case XED_IFORMFL_PFMUL_LAST: + case XED_IFORMFL_PFNACC_FIRST: + case XED_IFORMFL_PFNACC_LAST: + case XED_IFORMFL_PFPNACC_FIRST: + case XED_IFORMFL_PFPNACC_LAST: + case XED_IFORMFL_PFRCP_FIRST: + case XED_IFORMFL_PFRCP_LAST: + case XED_IFORMFL_PFRCPIT1_FIRST: + case XED_IFORMFL_PFRCPIT1_LAST: + case XED_IFORMFL_PFRCPIT2_FIRST: + case XED_IFORMFL_PFRCPIT2_LAST: + case XED_IFORMFL_PFRSQIT1_FIRST: + case XED_IFORMFL_PFRSQIT1_LAST: + case XED_IFORMFL_PFRSQRT_FIRST: + case XED_IFORMFL_PFRSQRT_LAST: + case XED_IFORMFL_PFSUB_FIRST: + case XED_IFORMFL_PFSUB_LAST: + case XED_IFORMFL_PFSUBR_FIRST: + case XED_IFORMFL_PFSUBR_LAST: + case XED_IFORMFL_PHADDD_FIRST: + case XED_IFORMFL_PHADDD_LAST: + case XED_IFORMFL_PHADDSW_FIRST: + case XED_IFORMFL_PHADDSW_LAST: + case XED_IFORMFL_PHADDW_FIRST: + case XED_IFORMFL_PHADDW_LAST: + case XED_IFORMFL_PHMINPOSUW_FIRST: + case XED_IFORMFL_PHMINPOSUW_LAST: + case XED_IFORMFL_PHSUBD_FIRST: + case XED_IFORMFL_PHSUBD_LAST: + case XED_IFORMFL_PHSUBSW_FIRST: + case XED_IFORMFL_PHSUBSW_LAST: + case XED_IFORMFL_PHSUBW_FIRST: + case XED_IFORMFL_PHSUBW_LAST: + case XED_IFORMFL_PI2FD_FIRST: + case XED_IFORMFL_PI2FD_LAST: + case XED_IFORMFL_PI2FW_FIRST: + case XED_IFORMFL_PI2FW_LAST: + case XED_IFORMFL_PINSRB_FIRST: + case XED_IFORMFL_PINSRB_LAST: + case XED_IFORMFL_PINSRD_FIRST: + case XED_IFORMFL_PINSRD_LAST: + case XED_IFORMFL_PINSRQ_FIRST: + case XED_IFORMFL_PINSRQ_LAST: + case XED_IFORMFL_PINSRW_FIRST: + case XED_IFORMFL_PINSRW_LAST: + case XED_IFORMFL_PMADDUBSW_FIRST: + case XED_IFORMFL_PMADDUBSW_LAST: + case XED_IFORMFL_PMADDWD_FIRST: + case XED_IFORMFL_PMADDWD_LAST: + case XED_IFORMFL_PMAXSB_FIRST: + case XED_IFORMFL_PMAXSB_LAST: + case XED_IFORMFL_PMAXSD_FIRST: + case XED_IFORMFL_PMAXSD_LAST: + case XED_IFORMFL_PMAXSW_FIRST: + case XED_IFORMFL_PMAXSW_LAST: + case XED_IFORMFL_PMAXUB_FIRST: + case XED_IFORMFL_PMAXUB_LAST: + case XED_IFORMFL_PMAXUD_FIRST: + case XED_IFORMFL_PMAXUD_LAST: + case XED_IFORMFL_PMAXUW_FIRST: + case XED_IFORMFL_PMAXUW_LAST: + case XED_IFORMFL_PMINSB_FIRST: + case XED_IFORMFL_PMINSB_LAST: + case XED_IFORMFL_PMINSD_FIRST: + case XED_IFORMFL_PMINSD_LAST: + case XED_IFORMFL_PMINSW_FIRST: + case XED_IFORMFL_PMINSW_LAST: + case XED_IFORMFL_PMINUB_FIRST: + case XED_IFORMFL_PMINUB_LAST: + case XED_IFORMFL_PMINUD_FIRST: + case XED_IFORMFL_PMINUD_LAST: + case XED_IFORMFL_PMINUW_FIRST: + case XED_IFORMFL_PMINUW_LAST: + case XED_IFORMFL_PMOVMSKB_FIRST: + case XED_IFORMFL_PMOVMSKB_LAST: + case XED_IFORMFL_PMOVSXBD_FIRST: + case XED_IFORMFL_PMOVSXBD_LAST: + case XED_IFORMFL_PMOVSXBQ_FIRST: + case XED_IFORMFL_PMOVSXBQ_LAST: + case XED_IFORMFL_PMOVSXBW_FIRST: + case XED_IFORMFL_PMOVSXBW_LAST: + case XED_IFORMFL_PMOVSXDQ_FIRST: + case XED_IFORMFL_PMOVSXDQ_LAST: + case XED_IFORMFL_PMOVSXWD_FIRST: + case XED_IFORMFL_PMOVSXWD_LAST: + case XED_IFORMFL_PMOVSXWQ_FIRST: + case XED_IFORMFL_PMOVSXWQ_LAST: + case XED_IFORMFL_PMOVZXBD_FIRST: + case XED_IFORMFL_PMOVZXBD_LAST: + case XED_IFORMFL_PMOVZXBQ_FIRST: + case XED_IFORMFL_PMOVZXBQ_LAST: + case XED_IFORMFL_PMOVZXBW_FIRST: + case XED_IFORMFL_PMOVZXBW_LAST: + case XED_IFORMFL_PMOVZXDQ_FIRST: + case XED_IFORMFL_PMOVZXDQ_LAST: + case XED_IFORMFL_PMOVZXWD_FIRST: + case XED_IFORMFL_PMOVZXWD_LAST: + case XED_IFORMFL_PMOVZXWQ_FIRST: + case XED_IFORMFL_PMOVZXWQ_LAST: + case XED_IFORMFL_PMULDQ_FIRST: + case XED_IFORMFL_PMULDQ_LAST: + case XED_IFORMFL_PMULHRSW_FIRST: + case XED_IFORMFL_PMULHRSW_LAST: + case XED_IFORMFL_PMULHRW_FIRST: + case XED_IFORMFL_PMULHRW_LAST: + case XED_IFORMFL_PMULHUW_FIRST: + case XED_IFORMFL_PMULHUW_LAST: + case XED_IFORMFL_PMULHW_FIRST: + case XED_IFORMFL_PMULHW_LAST: + case XED_IFORMFL_PMULLD_FIRST: + case XED_IFORMFL_PMULLD_LAST: + case XED_IFORMFL_PMULLW_FIRST: + case XED_IFORMFL_PMULLW_LAST: + case XED_IFORMFL_PMULUDQ_FIRST: + case XED_IFORMFL_PMULUDQ_LAST: + case XED_IFORMFL_POP_FIRST: + case XED_IFORMFL_POP_LAST: + case XED_IFORMFL_POPA_FIRST: + case XED_IFORMFL_POPA_LAST: + case XED_IFORMFL_POPAD_FIRST: + case XED_IFORMFL_POPAD_LAST: + case XED_IFORMFL_POPCNT_FIRST: + case XED_IFORMFL_POPCNT_LAST: + case XED_IFORMFL_POPF_FIRST: + case XED_IFORMFL_POPF_LAST: + case XED_IFORMFL_POPFD_FIRST: + case XED_IFORMFL_POPFD_LAST: + case XED_IFORMFL_POPFQ_FIRST: + case XED_IFORMFL_POPFQ_LAST: + case XED_IFORMFL_POR_FIRST: + case XED_IFORMFL_POR_LAST: + case XED_IFORMFL_PREFETCHNTA_FIRST: + case XED_IFORMFL_PREFETCHNTA_LAST: + case XED_IFORMFL_PREFETCHT0_FIRST: + case XED_IFORMFL_PREFETCHT0_LAST: + case XED_IFORMFL_PREFETCHT1_FIRST: + case XED_IFORMFL_PREFETCHT1_LAST: + case XED_IFORMFL_PREFETCHT2_FIRST: + case XED_IFORMFL_PREFETCHT2_LAST: + case XED_IFORMFL_PREFETCHW_FIRST: + case XED_IFORMFL_PREFETCHW_LAST: + case XED_IFORMFL_PREFETCHWT1_FIRST: + case XED_IFORMFL_PREFETCHWT1_LAST: + case XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST: + case XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST: + case XED_IFORMFL_PREFETCH_RESERVED_FIRST: + case XED_IFORMFL_PREFETCH_RESERVED_LAST: + case XED_IFORMFL_PSADBW_FIRST: + case XED_IFORMFL_PSADBW_LAST: + case XED_IFORMFL_PSHUFB_FIRST: + case XED_IFORMFL_PSHUFB_LAST: + case XED_IFORMFL_PSHUFD_FIRST: + case XED_IFORMFL_PSHUFD_LAST: + case XED_IFORMFL_PSHUFHW_FIRST: + case XED_IFORMFL_PSHUFHW_LAST: + case XED_IFORMFL_PSHUFLW_FIRST: + case XED_IFORMFL_PSHUFLW_LAST: + case XED_IFORMFL_PSHUFW_FIRST: + case XED_IFORMFL_PSHUFW_LAST: + case XED_IFORMFL_PSIGNB_FIRST: + case XED_IFORMFL_PSIGNB_LAST: + case XED_IFORMFL_PSIGND_FIRST: + case XED_IFORMFL_PSIGND_LAST: + case XED_IFORMFL_PSIGNW_FIRST: + case XED_IFORMFL_PSIGNW_LAST: + case XED_IFORMFL_PSLLD_FIRST: + case XED_IFORMFL_PSLLD_LAST: + case XED_IFORMFL_PSLLDQ_FIRST: + case XED_IFORMFL_PSLLDQ_LAST: + case XED_IFORMFL_PSLLQ_FIRST: + case XED_IFORMFL_PSLLQ_LAST: + case XED_IFORMFL_PSLLW_FIRST: + case XED_IFORMFL_PSLLW_LAST: + case XED_IFORMFL_PSMASH_FIRST: + case XED_IFORMFL_PSMASH_LAST: + case XED_IFORMFL_PSRAD_FIRST: + case XED_IFORMFL_PSRAD_LAST: + case XED_IFORMFL_PSRAW_FIRST: + case XED_IFORMFL_PSRAW_LAST: + case XED_IFORMFL_PSRLD_FIRST: + case XED_IFORMFL_PSRLD_LAST: + case XED_IFORMFL_PSRLDQ_FIRST: + case XED_IFORMFL_PSRLDQ_LAST: + case XED_IFORMFL_PSRLQ_FIRST: + case XED_IFORMFL_PSRLQ_LAST: + case XED_IFORMFL_PSRLW_FIRST: + case XED_IFORMFL_PSRLW_LAST: + case XED_IFORMFL_PSUBB_FIRST: + case XED_IFORMFL_PSUBB_LAST: + case XED_IFORMFL_PSUBD_FIRST: + case XED_IFORMFL_PSUBD_LAST: + case XED_IFORMFL_PSUBQ_FIRST: + case XED_IFORMFL_PSUBQ_LAST: + case XED_IFORMFL_PSUBSB_FIRST: + case XED_IFORMFL_PSUBSB_LAST: + case XED_IFORMFL_PSUBSW_FIRST: + case XED_IFORMFL_PSUBSW_LAST: + case XED_IFORMFL_PSUBUSB_FIRST: + case XED_IFORMFL_PSUBUSB_LAST: + case XED_IFORMFL_PSUBUSW_FIRST: + case XED_IFORMFL_PSUBUSW_LAST: + case XED_IFORMFL_PSUBW_FIRST: + case XED_IFORMFL_PSUBW_LAST: + case XED_IFORMFL_PSWAPD_FIRST: + case XED_IFORMFL_PSWAPD_LAST: + case XED_IFORMFL_PTEST_FIRST: + case XED_IFORMFL_PTEST_LAST: + case XED_IFORMFL_PTWRITE_FIRST: + case XED_IFORMFL_PTWRITE_LAST: + case XED_IFORMFL_PUNPCKHBW_FIRST: + case XED_IFORMFL_PUNPCKHBW_LAST: + case XED_IFORMFL_PUNPCKHDQ_FIRST: + case XED_IFORMFL_PUNPCKHDQ_LAST: + case XED_IFORMFL_PUNPCKHQDQ_FIRST: + case XED_IFORMFL_PUNPCKHQDQ_LAST: + case XED_IFORMFL_PUNPCKHWD_FIRST: + case XED_IFORMFL_PUNPCKHWD_LAST: + case XED_IFORMFL_PUNPCKLBW_FIRST: + case XED_IFORMFL_PUNPCKLBW_LAST: + case XED_IFORMFL_PUNPCKLDQ_FIRST: + case XED_IFORMFL_PUNPCKLDQ_LAST: + case XED_IFORMFL_PUNPCKLQDQ_FIRST: + case XED_IFORMFL_PUNPCKLQDQ_LAST: + case XED_IFORMFL_PUNPCKLWD_FIRST: + case XED_IFORMFL_PUNPCKLWD_LAST: + case XED_IFORMFL_PUSH_FIRST: + case XED_IFORMFL_PUSH_LAST: + case XED_IFORMFL_PUSHA_FIRST: + case XED_IFORMFL_PUSHA_LAST: + case XED_IFORMFL_PUSHAD_FIRST: + case XED_IFORMFL_PUSHAD_LAST: + case XED_IFORMFL_PUSHF_FIRST: + case XED_IFORMFL_PUSHF_LAST: + case XED_IFORMFL_PUSHFD_FIRST: + case XED_IFORMFL_PUSHFD_LAST: + case XED_IFORMFL_PUSHFQ_FIRST: + case XED_IFORMFL_PUSHFQ_LAST: + case XED_IFORMFL_PVALIDATE_FIRST: + case XED_IFORMFL_PVALIDATE_LAST: + case XED_IFORMFL_PXOR_FIRST: + case XED_IFORMFL_PXOR_LAST: + case XED_IFORMFL_RCL_FIRST: + case XED_IFORMFL_RCL_LAST: + case XED_IFORMFL_RCPPS_FIRST: + case XED_IFORMFL_RCPPS_LAST: + case XED_IFORMFL_RCPSS_FIRST: + case XED_IFORMFL_RCPSS_LAST: + case XED_IFORMFL_RCR_FIRST: + case XED_IFORMFL_RCR_LAST: + case XED_IFORMFL_RDFSBASE_FIRST: + case XED_IFORMFL_RDFSBASE_LAST: + case XED_IFORMFL_RDGSBASE_FIRST: + case XED_IFORMFL_RDGSBASE_LAST: + case XED_IFORMFL_RDMSR_FIRST: + case XED_IFORMFL_RDMSR_LAST: + case XED_IFORMFL_RDPID_FIRST: + case XED_IFORMFL_RDPID_LAST: + case XED_IFORMFL_RDPKRU_FIRST: + case XED_IFORMFL_RDPKRU_LAST: + case XED_IFORMFL_RDPMC_FIRST: + case XED_IFORMFL_RDPMC_LAST: + case XED_IFORMFL_RDPRU_FIRST: + case XED_IFORMFL_RDPRU_LAST: + case XED_IFORMFL_RDRAND_FIRST: + case XED_IFORMFL_RDRAND_LAST: + case XED_IFORMFL_RDSEED_FIRST: + case XED_IFORMFL_RDSEED_LAST: + case XED_IFORMFL_RDSSPD_FIRST: + case XED_IFORMFL_RDSSPD_LAST: + case XED_IFORMFL_RDSSPQ_FIRST: + case XED_IFORMFL_RDSSPQ_LAST: + case XED_IFORMFL_RDTSC_FIRST: + case XED_IFORMFL_RDTSC_LAST: + case XED_IFORMFL_RDTSCP_FIRST: + case XED_IFORMFL_RDTSCP_LAST: + case XED_IFORMFL_REPE_CMPSB_FIRST: + case XED_IFORMFL_REPE_CMPSB_LAST: + case XED_IFORMFL_REPE_CMPSD_FIRST: + case XED_IFORMFL_REPE_CMPSD_LAST: + case XED_IFORMFL_REPE_CMPSQ_FIRST: + case XED_IFORMFL_REPE_CMPSQ_LAST: + case XED_IFORMFL_REPE_CMPSW_FIRST: + case XED_IFORMFL_REPE_CMPSW_LAST: + case XED_IFORMFL_REPE_SCASB_FIRST: + case XED_IFORMFL_REPE_SCASB_LAST: + case XED_IFORMFL_REPE_SCASD_FIRST: + case XED_IFORMFL_REPE_SCASD_LAST: + case XED_IFORMFL_REPE_SCASQ_FIRST: + case XED_IFORMFL_REPE_SCASQ_LAST: + case XED_IFORMFL_REPE_SCASW_FIRST: + case XED_IFORMFL_REPE_SCASW_LAST: + case XED_IFORMFL_REPNE_CMPSB_FIRST: + case XED_IFORMFL_REPNE_CMPSB_LAST: + case XED_IFORMFL_REPNE_CMPSD_FIRST: + case XED_IFORMFL_REPNE_CMPSD_LAST: + case XED_IFORMFL_REPNE_CMPSQ_FIRST: + case XED_IFORMFL_REPNE_CMPSQ_LAST: + case XED_IFORMFL_REPNE_CMPSW_FIRST: + case XED_IFORMFL_REPNE_CMPSW_LAST: + case XED_IFORMFL_REPNE_SCASB_FIRST: + case XED_IFORMFL_REPNE_SCASB_LAST: + case XED_IFORMFL_REPNE_SCASD_FIRST: + case XED_IFORMFL_REPNE_SCASD_LAST: + case XED_IFORMFL_REPNE_SCASQ_FIRST: + case XED_IFORMFL_REPNE_SCASQ_LAST: + case XED_IFORMFL_REPNE_SCASW_FIRST: + case XED_IFORMFL_REPNE_SCASW_LAST: + case XED_IFORMFL_REP_INSB_FIRST: + case XED_IFORMFL_REP_INSB_LAST: + case XED_IFORMFL_REP_INSD_FIRST: + case XED_IFORMFL_REP_INSD_LAST: + case XED_IFORMFL_REP_INSW_FIRST: + case XED_IFORMFL_REP_INSW_LAST: + case XED_IFORMFL_REP_LODSB_FIRST: + case XED_IFORMFL_REP_LODSB_LAST: + case XED_IFORMFL_REP_LODSD_FIRST: + case XED_IFORMFL_REP_LODSD_LAST: + case XED_IFORMFL_REP_LODSQ_FIRST: + case XED_IFORMFL_REP_LODSQ_LAST: + case XED_IFORMFL_REP_LODSW_FIRST: + case XED_IFORMFL_REP_LODSW_LAST: + case XED_IFORMFL_REP_MONTMUL_FIRST: + case XED_IFORMFL_REP_MONTMUL_LAST: + case XED_IFORMFL_REP_MOVSB_FIRST: + case XED_IFORMFL_REP_MOVSB_LAST: + case XED_IFORMFL_REP_MOVSD_FIRST: + case XED_IFORMFL_REP_MOVSD_LAST: + case XED_IFORMFL_REP_MOVSQ_FIRST: + case XED_IFORMFL_REP_MOVSQ_LAST: + case XED_IFORMFL_REP_MOVSW_FIRST: + case XED_IFORMFL_REP_MOVSW_LAST: + case XED_IFORMFL_REP_OUTSB_FIRST: + case XED_IFORMFL_REP_OUTSB_LAST: + case XED_IFORMFL_REP_OUTSD_FIRST: + case XED_IFORMFL_REP_OUTSD_LAST: + case XED_IFORMFL_REP_OUTSW_FIRST: + case XED_IFORMFL_REP_OUTSW_LAST: + case XED_IFORMFL_REP_STOSB_FIRST: + case XED_IFORMFL_REP_STOSB_LAST: + case XED_IFORMFL_REP_STOSD_FIRST: + case XED_IFORMFL_REP_STOSD_LAST: + case XED_IFORMFL_REP_STOSQ_FIRST: + case XED_IFORMFL_REP_STOSQ_LAST: + case XED_IFORMFL_REP_STOSW_FIRST: + case XED_IFORMFL_REP_STOSW_LAST: + case XED_IFORMFL_REP_XCRYPTCBC_FIRST: + case XED_IFORMFL_REP_XCRYPTCBC_LAST: + case XED_IFORMFL_REP_XCRYPTCFB_FIRST: + case XED_IFORMFL_REP_XCRYPTCFB_LAST: + case XED_IFORMFL_REP_XCRYPTCTR_FIRST: + case XED_IFORMFL_REP_XCRYPTCTR_LAST: + case XED_IFORMFL_REP_XCRYPTECB_FIRST: + case XED_IFORMFL_REP_XCRYPTECB_LAST: + case XED_IFORMFL_REP_XCRYPTOFB_FIRST: + case XED_IFORMFL_REP_XCRYPTOFB_LAST: + case XED_IFORMFL_REP_XSHA1_FIRST: + case XED_IFORMFL_REP_XSHA1_LAST: + case XED_IFORMFL_REP_XSHA256_FIRST: + case XED_IFORMFL_REP_XSHA256_LAST: + case XED_IFORMFL_REP_XSTORE_FIRST: + case XED_IFORMFL_REP_XSTORE_LAST: + case XED_IFORMFL_RET_FAR_FIRST: + case XED_IFORMFL_RET_FAR_LAST: + case XED_IFORMFL_RET_NEAR_FIRST: + case XED_IFORMFL_RET_NEAR_LAST: + case XED_IFORMFL_RMPADJUST_FIRST: + case XED_IFORMFL_RMPADJUST_LAST: + case XED_IFORMFL_RMPUPDATE_FIRST: + case XED_IFORMFL_RMPUPDATE_LAST: + case XED_IFORMFL_ROL_FIRST: + case XED_IFORMFL_ROL_LAST: + case XED_IFORMFL_ROR_FIRST: + case XED_IFORMFL_ROR_LAST: + case XED_IFORMFL_RORX_FIRST: + case XED_IFORMFL_RORX_LAST: + case XED_IFORMFL_ROUNDPD_FIRST: + case XED_IFORMFL_ROUNDPD_LAST: + case XED_IFORMFL_ROUNDPS_FIRST: + case XED_IFORMFL_ROUNDPS_LAST: + case XED_IFORMFL_ROUNDSD_FIRST: + case XED_IFORMFL_ROUNDSD_LAST: + case XED_IFORMFL_ROUNDSS_FIRST: + case XED_IFORMFL_ROUNDSS_LAST: + case XED_IFORMFL_RSM_FIRST: + case XED_IFORMFL_RSM_LAST: + case XED_IFORMFL_RSQRTPS_FIRST: + case XED_IFORMFL_RSQRTPS_LAST: + case XED_IFORMFL_RSQRTSS_FIRST: + case XED_IFORMFL_RSQRTSS_LAST: + case XED_IFORMFL_RSTORSSP_FIRST: + case XED_IFORMFL_RSTORSSP_LAST: + case XED_IFORMFL_SAHF_FIRST: + case XED_IFORMFL_SAHF_LAST: + case XED_IFORMFL_SALC_FIRST: + case XED_IFORMFL_SALC_LAST: + case XED_IFORMFL_SAR_FIRST: + case XED_IFORMFL_SAR_LAST: + case XED_IFORMFL_SARX_FIRST: + case XED_IFORMFL_SARX_LAST: + case XED_IFORMFL_SAVEPREVSSP_FIRST: + case XED_IFORMFL_SAVEPREVSSP_LAST: + case XED_IFORMFL_SBB_FIRST: + case XED_IFORMFL_SBB_LAST: + case XED_IFORMFL_SBB_LOCK_FIRST: + case XED_IFORMFL_SBB_LOCK_LAST: + case XED_IFORMFL_SCASB_FIRST: + case XED_IFORMFL_SCASB_LAST: + case XED_IFORMFL_SCASD_FIRST: + case XED_IFORMFL_SCASD_LAST: + case XED_IFORMFL_SCASQ_FIRST: + case XED_IFORMFL_SCASQ_LAST: + case XED_IFORMFL_SCASW_FIRST: + case XED_IFORMFL_SCASW_LAST: + case XED_IFORMFL_SEAMCALL_FIRST: + case XED_IFORMFL_SEAMCALL_LAST: + case XED_IFORMFL_SEAMOPS_FIRST: + case XED_IFORMFL_SEAMOPS_LAST: + case XED_IFORMFL_SEAMRET_FIRST: + case XED_IFORMFL_SEAMRET_LAST: + case XED_IFORMFL_SENDUIPI_FIRST: + case XED_IFORMFL_SENDUIPI_LAST: + case XED_IFORMFL_SERIALIZE_FIRST: + case XED_IFORMFL_SERIALIZE_LAST: + case XED_IFORMFL_SETB_FIRST: + case XED_IFORMFL_SETB_LAST: + case XED_IFORMFL_SETBE_FIRST: + case XED_IFORMFL_SETBE_LAST: + case XED_IFORMFL_SETL_FIRST: + case XED_IFORMFL_SETL_LAST: + case XED_IFORMFL_SETLE_FIRST: + case XED_IFORMFL_SETLE_LAST: + case XED_IFORMFL_SETNB_FIRST: + case XED_IFORMFL_SETNB_LAST: + case XED_IFORMFL_SETNBE_FIRST: + case XED_IFORMFL_SETNBE_LAST: + case XED_IFORMFL_SETNL_FIRST: + case XED_IFORMFL_SETNL_LAST: + case XED_IFORMFL_SETNLE_FIRST: + case XED_IFORMFL_SETNLE_LAST: + case XED_IFORMFL_SETNO_FIRST: + case XED_IFORMFL_SETNO_LAST: + case XED_IFORMFL_SETNP_FIRST: + case XED_IFORMFL_SETNP_LAST: + case XED_IFORMFL_SETNS_FIRST: + case XED_IFORMFL_SETNS_LAST: + case XED_IFORMFL_SETNZ_FIRST: + case XED_IFORMFL_SETNZ_LAST: + case XED_IFORMFL_SETO_FIRST: + case XED_IFORMFL_SETO_LAST: + case XED_IFORMFL_SETP_FIRST: + case XED_IFORMFL_SETP_LAST: + case XED_IFORMFL_SETS_FIRST: + case XED_IFORMFL_SETS_LAST: + case XED_IFORMFL_SETSSBSY_FIRST: + case XED_IFORMFL_SETSSBSY_LAST: + case XED_IFORMFL_SETZ_FIRST: + case XED_IFORMFL_SETZ_LAST: + case XED_IFORMFL_SFENCE_FIRST: + case XED_IFORMFL_SFENCE_LAST: + case XED_IFORMFL_SGDT_FIRST: + case XED_IFORMFL_SGDT_LAST: + case XED_IFORMFL_SHA1MSG1_FIRST: + case XED_IFORMFL_SHA1MSG1_LAST: + case XED_IFORMFL_SHA1MSG2_FIRST: + case XED_IFORMFL_SHA1MSG2_LAST: + case XED_IFORMFL_SHA1NEXTE_FIRST: + case XED_IFORMFL_SHA1NEXTE_LAST: + case XED_IFORMFL_SHA1RNDS4_FIRST: + case XED_IFORMFL_SHA1RNDS4_LAST: + case XED_IFORMFL_SHA256MSG1_FIRST: + case XED_IFORMFL_SHA256MSG1_LAST: + case XED_IFORMFL_SHA256MSG2_FIRST: + case XED_IFORMFL_SHA256MSG2_LAST: + case XED_IFORMFL_SHA256RNDS2_FIRST: + case XED_IFORMFL_SHA256RNDS2_LAST: + case XED_IFORMFL_SHL_FIRST: + case XED_IFORMFL_SHL_LAST: + case XED_IFORMFL_SHLD_FIRST: + case XED_IFORMFL_SHLD_LAST: + case XED_IFORMFL_SHLX_FIRST: + case XED_IFORMFL_SHLX_LAST: + case XED_IFORMFL_SHR_FIRST: + case XED_IFORMFL_SHR_LAST: + case XED_IFORMFL_SHRD_FIRST: + case XED_IFORMFL_SHRD_LAST: + case XED_IFORMFL_SHRX_FIRST: + case XED_IFORMFL_SHRX_LAST: + case XED_IFORMFL_SHUFPD_FIRST: + case XED_IFORMFL_SHUFPD_LAST: + case XED_IFORMFL_SHUFPS_FIRST: + case XED_IFORMFL_SHUFPS_LAST: + case XED_IFORMFL_SIDT_FIRST: + case XED_IFORMFL_SIDT_LAST: + case XED_IFORMFL_SKINIT_FIRST: + case XED_IFORMFL_SKINIT_LAST: + case XED_IFORMFL_SLDT_FIRST: + case XED_IFORMFL_SLDT_LAST: + case XED_IFORMFL_SLWPCB_FIRST: + case XED_IFORMFL_SLWPCB_LAST: + case XED_IFORMFL_SMSW_FIRST: + case XED_IFORMFL_SMSW_LAST: + case XED_IFORMFL_SQRTPD_FIRST: + case XED_IFORMFL_SQRTPD_LAST: + case XED_IFORMFL_SQRTPS_FIRST: + case XED_IFORMFL_SQRTPS_LAST: + case XED_IFORMFL_SQRTSD_FIRST: + case XED_IFORMFL_SQRTSD_LAST: + case XED_IFORMFL_SQRTSS_FIRST: + case XED_IFORMFL_SQRTSS_LAST: + case XED_IFORMFL_STAC_FIRST: + case XED_IFORMFL_STAC_LAST: + case XED_IFORMFL_STC_FIRST: + case XED_IFORMFL_STC_LAST: + case XED_IFORMFL_STD_FIRST: + case XED_IFORMFL_STD_LAST: + case XED_IFORMFL_STGI_FIRST: + case XED_IFORMFL_STGI_LAST: + case XED_IFORMFL_STI_FIRST: + case XED_IFORMFL_STI_LAST: + case XED_IFORMFL_STMXCSR_FIRST: + case XED_IFORMFL_STMXCSR_LAST: + case XED_IFORMFL_STOSB_FIRST: + case XED_IFORMFL_STOSB_LAST: + case XED_IFORMFL_STOSD_FIRST: + case XED_IFORMFL_STOSD_LAST: + case XED_IFORMFL_STOSQ_FIRST: + case XED_IFORMFL_STOSQ_LAST: + case XED_IFORMFL_STOSW_FIRST: + case XED_IFORMFL_STOSW_LAST: + case XED_IFORMFL_STR_FIRST: + case XED_IFORMFL_STR_LAST: + case XED_IFORMFL_STTILECFG_FIRST: + case XED_IFORMFL_STTILECFG_LAST: + case XED_IFORMFL_STUI_FIRST: + case XED_IFORMFL_STUI_LAST: + case XED_IFORMFL_SUB_FIRST: + case XED_IFORMFL_SUB_LAST: + case XED_IFORMFL_SUBPD_FIRST: + case XED_IFORMFL_SUBPD_LAST: + case XED_IFORMFL_SUBPS_FIRST: + case XED_IFORMFL_SUBPS_LAST: + case XED_IFORMFL_SUBSD_FIRST: + case XED_IFORMFL_SUBSD_LAST: + case XED_IFORMFL_SUBSS_FIRST: + case XED_IFORMFL_SUBSS_LAST: + case XED_IFORMFL_SUB_LOCK_FIRST: + case XED_IFORMFL_SUB_LOCK_LAST: + case XED_IFORMFL_SWAPGS_FIRST: + case XED_IFORMFL_SWAPGS_LAST: + case XED_IFORMFL_SYSCALL_FIRST: + case XED_IFORMFL_SYSCALL_LAST: + case XED_IFORMFL_SYSCALL_AMD_FIRST: + case XED_IFORMFL_SYSCALL_AMD_LAST: + case XED_IFORMFL_SYSENTER_FIRST: + case XED_IFORMFL_SYSENTER_LAST: + case XED_IFORMFL_SYSEXIT_FIRST: + case XED_IFORMFL_SYSEXIT_LAST: + case XED_IFORMFL_SYSRET_FIRST: + case XED_IFORMFL_SYSRET_LAST: + case XED_IFORMFL_SYSRET64_FIRST: + case XED_IFORMFL_SYSRET64_LAST: + case XED_IFORMFL_SYSRET_AMD_FIRST: + case XED_IFORMFL_SYSRET_AMD_LAST: + case XED_IFORMFL_T1MSKC_FIRST: + case XED_IFORMFL_T1MSKC_LAST: + case XED_IFORMFL_TDCALL_FIRST: + case XED_IFORMFL_TDCALL_LAST: + case XED_IFORMFL_TDPBF16PS_FIRST: + case XED_IFORMFL_TDPBF16PS_LAST: + case XED_IFORMFL_TDPBSSD_FIRST: + case XED_IFORMFL_TDPBSSD_LAST: + case XED_IFORMFL_TDPBSUD_FIRST: + case XED_IFORMFL_TDPBSUD_LAST: + case XED_IFORMFL_TDPBUSD_FIRST: + case XED_IFORMFL_TDPBUSD_LAST: + case XED_IFORMFL_TDPBUUD_FIRST: + case XED_IFORMFL_TDPBUUD_LAST: + case XED_IFORMFL_TEST_FIRST: + case XED_IFORMFL_TEST_LAST: + case XED_IFORMFL_TESTUI_FIRST: + case XED_IFORMFL_TESTUI_LAST: + case XED_IFORMFL_TILELOADD_FIRST: + case XED_IFORMFL_TILELOADD_LAST: + case XED_IFORMFL_TILELOADDT1_FIRST: + case XED_IFORMFL_TILELOADDT1_LAST: + case XED_IFORMFL_TILERELEASE_FIRST: + case XED_IFORMFL_TILERELEASE_LAST: + case XED_IFORMFL_TILESTORED_FIRST: + case XED_IFORMFL_TILESTORED_LAST: + case XED_IFORMFL_TILEZERO_FIRST: + case XED_IFORMFL_TILEZERO_LAST: + case XED_IFORMFL_TLBSYNC_FIRST: + case XED_IFORMFL_TLBSYNC_LAST: + case XED_IFORMFL_TPAUSE_FIRST: + case XED_IFORMFL_TPAUSE_LAST: + case XED_IFORMFL_TZCNT_FIRST: + case XED_IFORMFL_TZCNT_LAST: + case XED_IFORMFL_TZMSK_FIRST: + case XED_IFORMFL_TZMSK_LAST: + case XED_IFORMFL_UCOMISD_FIRST: + case XED_IFORMFL_UCOMISD_LAST: + case XED_IFORMFL_UCOMISS_FIRST: + case XED_IFORMFL_UCOMISS_LAST: + case XED_IFORMFL_UD0_FIRST: + case XED_IFORMFL_UD0_LAST: + case XED_IFORMFL_UD1_FIRST: + case XED_IFORMFL_UD1_LAST: + case XED_IFORMFL_UD2_FIRST: + case XED_IFORMFL_UD2_LAST: + case XED_IFORMFL_UIRET_FIRST: + case XED_IFORMFL_UIRET_LAST: + case XED_IFORMFL_UMONITOR_FIRST: + case XED_IFORMFL_UMONITOR_LAST: + case XED_IFORMFL_UMWAIT_FIRST: + case XED_IFORMFL_UMWAIT_LAST: + case XED_IFORMFL_UNPCKHPD_FIRST: + case XED_IFORMFL_UNPCKHPD_LAST: + case XED_IFORMFL_UNPCKHPS_FIRST: + case XED_IFORMFL_UNPCKHPS_LAST: + case XED_IFORMFL_UNPCKLPD_FIRST: + case XED_IFORMFL_UNPCKLPD_LAST: + case XED_IFORMFL_UNPCKLPS_FIRST: + case XED_IFORMFL_UNPCKLPS_LAST: + case XED_IFORMFL_V4FMADDPS_FIRST: + case XED_IFORMFL_V4FMADDPS_LAST: + case XED_IFORMFL_V4FMADDSS_FIRST: + case XED_IFORMFL_V4FMADDSS_LAST: + case XED_IFORMFL_V4FNMADDPS_FIRST: + case XED_IFORMFL_V4FNMADDPS_LAST: + case XED_IFORMFL_V4FNMADDSS_FIRST: + case XED_IFORMFL_V4FNMADDSS_LAST: + case XED_IFORMFL_VADDPD_FIRST: + case XED_IFORMFL_VADDPD_LAST: + case XED_IFORMFL_VADDPH_FIRST: + case XED_IFORMFL_VADDPH_LAST: + case XED_IFORMFL_VADDPS_FIRST: + case XED_IFORMFL_VADDPS_LAST: + case XED_IFORMFL_VADDSD_FIRST: + case XED_IFORMFL_VADDSD_LAST: + case XED_IFORMFL_VADDSH_FIRST: + case XED_IFORMFL_VADDSH_LAST: + case XED_IFORMFL_VADDSS_FIRST: + case XED_IFORMFL_VADDSS_LAST: + case XED_IFORMFL_VADDSUBPD_FIRST: + case XED_IFORMFL_VADDSUBPD_LAST: + case XED_IFORMFL_VADDSUBPS_FIRST: + case XED_IFORMFL_VADDSUBPS_LAST: + case XED_IFORMFL_VAESDEC_FIRST: + case XED_IFORMFL_VAESDEC_LAST: + case XED_IFORMFL_VAESDECLAST_FIRST: + case XED_IFORMFL_VAESDECLAST_LAST: + case XED_IFORMFL_VAESENC_FIRST: + case XED_IFORMFL_VAESENC_LAST: + case XED_IFORMFL_VAESENCLAST_FIRST: + case XED_IFORMFL_VAESENCLAST_LAST: + case XED_IFORMFL_VAESIMC_FIRST: + case XED_IFORMFL_VAESIMC_LAST: + case XED_IFORMFL_VAESKEYGENASSIST_FIRST: + case XED_IFORMFL_VAESKEYGENASSIST_LAST: + case XED_IFORMFL_VALIGND_FIRST: + case XED_IFORMFL_VALIGND_LAST: + case XED_IFORMFL_VALIGNQ_FIRST: + case XED_IFORMFL_VALIGNQ_LAST: + case XED_IFORMFL_VANDNPD_FIRST: + case XED_IFORMFL_VANDNPD_LAST: + case XED_IFORMFL_VANDNPS_FIRST: + case XED_IFORMFL_VANDNPS_LAST: + case XED_IFORMFL_VANDPD_FIRST: + case XED_IFORMFL_VANDPD_LAST: + case XED_IFORMFL_VANDPS_FIRST: + case XED_IFORMFL_VANDPS_LAST: + case XED_IFORMFL_VBLENDMPD_FIRST: + case XED_IFORMFL_VBLENDMPD_LAST: + case XED_IFORMFL_VBLENDMPS_FIRST: + case XED_IFORMFL_VBLENDMPS_LAST: + case XED_IFORMFL_VBLENDPD_FIRST: + case XED_IFORMFL_VBLENDPD_LAST: + case XED_IFORMFL_VBLENDPS_FIRST: + case XED_IFORMFL_VBLENDPS_LAST: + case XED_IFORMFL_VBLENDVPD_FIRST: + case XED_IFORMFL_VBLENDVPD_LAST: + case XED_IFORMFL_VBLENDVPS_FIRST: + case XED_IFORMFL_VBLENDVPS_LAST: + case XED_IFORMFL_VBROADCASTF128_FIRST: + case XED_IFORMFL_VBROADCASTF128_LAST: + case XED_IFORMFL_VBROADCASTF32X2_FIRST: + case XED_IFORMFL_VBROADCASTF32X2_LAST: + case XED_IFORMFL_VBROADCASTF32X4_FIRST: + case XED_IFORMFL_VBROADCASTF32X4_LAST: + case XED_IFORMFL_VBROADCASTF32X8_FIRST: + case XED_IFORMFL_VBROADCASTF32X8_LAST: + case XED_IFORMFL_VBROADCASTF64X2_FIRST: + case XED_IFORMFL_VBROADCASTF64X2_LAST: + case XED_IFORMFL_VBROADCASTF64X4_FIRST: + case XED_IFORMFL_VBROADCASTF64X4_LAST: + case XED_IFORMFL_VBROADCASTI128_FIRST: + case XED_IFORMFL_VBROADCASTI128_LAST: + case XED_IFORMFL_VBROADCASTI32X2_FIRST: + case XED_IFORMFL_VBROADCASTI32X2_LAST: + case XED_IFORMFL_VBROADCASTI32X4_FIRST: + case XED_IFORMFL_VBROADCASTI32X4_LAST: + case XED_IFORMFL_VBROADCASTI32X8_FIRST: + case XED_IFORMFL_VBROADCASTI32X8_LAST: + case XED_IFORMFL_VBROADCASTI64X2_FIRST: + case XED_IFORMFL_VBROADCASTI64X2_LAST: + case XED_IFORMFL_VBROADCASTI64X4_FIRST: + case XED_IFORMFL_VBROADCASTI64X4_LAST: + case XED_IFORMFL_VBROADCASTSD_FIRST: + case XED_IFORMFL_VBROADCASTSD_LAST: + case XED_IFORMFL_VBROADCASTSS_FIRST: + case XED_IFORMFL_VBROADCASTSS_LAST: + case XED_IFORMFL_VCMPPD_FIRST: + case XED_IFORMFL_VCMPPD_LAST: + case XED_IFORMFL_VCMPPH_FIRST: + case XED_IFORMFL_VCMPPH_LAST: + case XED_IFORMFL_VCMPPS_FIRST: + case XED_IFORMFL_VCMPPS_LAST: + case XED_IFORMFL_VCMPSD_FIRST: + case XED_IFORMFL_VCMPSD_LAST: + case XED_IFORMFL_VCMPSH_FIRST: + case XED_IFORMFL_VCMPSH_LAST: + case XED_IFORMFL_VCMPSS_FIRST: + case XED_IFORMFL_VCMPSS_LAST: + case XED_IFORMFL_VCOMISD_FIRST: + case XED_IFORMFL_VCOMISD_LAST: + case XED_IFORMFL_VCOMISH_FIRST: + case XED_IFORMFL_VCOMISH_LAST: + case XED_IFORMFL_VCOMISS_FIRST: + case XED_IFORMFL_VCOMISS_LAST: + case XED_IFORMFL_VCOMPRESSPD_FIRST: + case XED_IFORMFL_VCOMPRESSPD_LAST: + case XED_IFORMFL_VCOMPRESSPS_FIRST: + case XED_IFORMFL_VCOMPRESSPS_LAST: + case XED_IFORMFL_VCVTDQ2PD_FIRST: + case XED_IFORMFL_VCVTDQ2PD_LAST: + case XED_IFORMFL_VCVTDQ2PH_FIRST: + case XED_IFORMFL_VCVTDQ2PH_LAST: + case XED_IFORMFL_VCVTDQ2PS_FIRST: + case XED_IFORMFL_VCVTDQ2PS_LAST: + case XED_IFORMFL_VCVTNE2PS2BF16_FIRST: + case XED_IFORMFL_VCVTNE2PS2BF16_LAST: + case XED_IFORMFL_VCVTNEPS2BF16_FIRST: + case XED_IFORMFL_VCVTNEPS2BF16_LAST: + case XED_IFORMFL_VCVTPD2DQ_FIRST: + case XED_IFORMFL_VCVTPD2DQ_LAST: + case XED_IFORMFL_VCVTPD2PH_FIRST: + case XED_IFORMFL_VCVTPD2PH_LAST: + case XED_IFORMFL_VCVTPD2PS_FIRST: + case XED_IFORMFL_VCVTPD2PS_LAST: + case XED_IFORMFL_VCVTPD2QQ_FIRST: + case XED_IFORMFL_VCVTPD2QQ_LAST: + case XED_IFORMFL_VCVTPD2UDQ_FIRST: + case XED_IFORMFL_VCVTPD2UDQ_LAST: + case XED_IFORMFL_VCVTPD2UQQ_FIRST: + case XED_IFORMFL_VCVTPD2UQQ_LAST: + case XED_IFORMFL_VCVTPH2DQ_FIRST: + case XED_IFORMFL_VCVTPH2DQ_LAST: + case XED_IFORMFL_VCVTPH2PD_FIRST: + case XED_IFORMFL_VCVTPH2PD_LAST: + case XED_IFORMFL_VCVTPH2PS_FIRST: + case XED_IFORMFL_VCVTPH2PS_LAST: + case XED_IFORMFL_VCVTPH2PSX_FIRST: + case XED_IFORMFL_VCVTPH2PSX_LAST: + case XED_IFORMFL_VCVTPH2QQ_FIRST: + case XED_IFORMFL_VCVTPH2QQ_LAST: + case XED_IFORMFL_VCVTPH2UDQ_FIRST: + case XED_IFORMFL_VCVTPH2UDQ_LAST: + case XED_IFORMFL_VCVTPH2UQQ_FIRST: + case XED_IFORMFL_VCVTPH2UQQ_LAST: + case XED_IFORMFL_VCVTPH2UW_FIRST: + case XED_IFORMFL_VCVTPH2UW_LAST: + case XED_IFORMFL_VCVTPH2W_FIRST: + case XED_IFORMFL_VCVTPH2W_LAST: + case XED_IFORMFL_VCVTPS2DQ_FIRST: + case XED_IFORMFL_VCVTPS2DQ_LAST: + case XED_IFORMFL_VCVTPS2PD_FIRST: + case XED_IFORMFL_VCVTPS2PD_LAST: + case XED_IFORMFL_VCVTPS2PH_FIRST: + case XED_IFORMFL_VCVTPS2PH_LAST: + case XED_IFORMFL_VCVTPS2PHX_FIRST: + case XED_IFORMFL_VCVTPS2PHX_LAST: + case XED_IFORMFL_VCVTPS2QQ_FIRST: + case XED_IFORMFL_VCVTPS2QQ_LAST: + case XED_IFORMFL_VCVTPS2UDQ_FIRST: + case XED_IFORMFL_VCVTPS2UDQ_LAST: + case XED_IFORMFL_VCVTPS2UQQ_FIRST: + case XED_IFORMFL_VCVTPS2UQQ_LAST: + case XED_IFORMFL_VCVTQQ2PD_FIRST: + case XED_IFORMFL_VCVTQQ2PD_LAST: + case XED_IFORMFL_VCVTQQ2PH_FIRST: + case XED_IFORMFL_VCVTQQ2PH_LAST: + case XED_IFORMFL_VCVTQQ2PS_FIRST: + case XED_IFORMFL_VCVTQQ2PS_LAST: + case XED_IFORMFL_VCVTSD2SH_FIRST: + case XED_IFORMFL_VCVTSD2SH_LAST: + case XED_IFORMFL_VCVTSD2SI_FIRST: + case XED_IFORMFL_VCVTSD2SI_LAST: + case XED_IFORMFL_VCVTSD2SS_FIRST: + case XED_IFORMFL_VCVTSD2SS_LAST: + case XED_IFORMFL_VCVTSD2USI_FIRST: + case XED_IFORMFL_VCVTSD2USI_LAST: + case XED_IFORMFL_VCVTSH2SD_FIRST: + case XED_IFORMFL_VCVTSH2SD_LAST: + case XED_IFORMFL_VCVTSH2SI_FIRST: + case XED_IFORMFL_VCVTSH2SI_LAST: + case XED_IFORMFL_VCVTSH2SS_FIRST: + case XED_IFORMFL_VCVTSH2SS_LAST: + case XED_IFORMFL_VCVTSH2USI_FIRST: + case XED_IFORMFL_VCVTSH2USI_LAST: + case XED_IFORMFL_VCVTSI2SD_FIRST: + case XED_IFORMFL_VCVTSI2SD_LAST: + case XED_IFORMFL_VCVTSI2SH_FIRST: + case XED_IFORMFL_VCVTSI2SH_LAST: + case XED_IFORMFL_VCVTSI2SS_FIRST: + case XED_IFORMFL_VCVTSI2SS_LAST: + case XED_IFORMFL_VCVTSS2SD_FIRST: + case XED_IFORMFL_VCVTSS2SD_LAST: + case XED_IFORMFL_VCVTSS2SH_FIRST: + case XED_IFORMFL_VCVTSS2SH_LAST: + case XED_IFORMFL_VCVTSS2SI_FIRST: + case XED_IFORMFL_VCVTSS2SI_LAST: + case XED_IFORMFL_VCVTSS2USI_FIRST: + case XED_IFORMFL_VCVTSS2USI_LAST: + case XED_IFORMFL_VCVTTPD2DQ_FIRST: + case XED_IFORMFL_VCVTTPD2DQ_LAST: + case XED_IFORMFL_VCVTTPD2QQ_FIRST: + case XED_IFORMFL_VCVTTPD2QQ_LAST: + case XED_IFORMFL_VCVTTPD2UDQ_FIRST: + case XED_IFORMFL_VCVTTPD2UDQ_LAST: + case XED_IFORMFL_VCVTTPD2UQQ_FIRST: + case XED_IFORMFL_VCVTTPD2UQQ_LAST: + case XED_IFORMFL_VCVTTPH2DQ_FIRST: + case XED_IFORMFL_VCVTTPH2DQ_LAST: + case XED_IFORMFL_VCVTTPH2QQ_FIRST: + case XED_IFORMFL_VCVTTPH2QQ_LAST: + case XED_IFORMFL_VCVTTPH2UDQ_FIRST: + case XED_IFORMFL_VCVTTPH2UDQ_LAST: + case XED_IFORMFL_VCVTTPH2UQQ_FIRST: + case XED_IFORMFL_VCVTTPH2UQQ_LAST: + case XED_IFORMFL_VCVTTPH2UW_FIRST: + case XED_IFORMFL_VCVTTPH2UW_LAST: + case XED_IFORMFL_VCVTTPH2W_FIRST: + case XED_IFORMFL_VCVTTPH2W_LAST: + case XED_IFORMFL_VCVTTPS2DQ_FIRST: + case XED_IFORMFL_VCVTTPS2DQ_LAST: + case XED_IFORMFL_VCVTTPS2QQ_FIRST: + case XED_IFORMFL_VCVTTPS2QQ_LAST: + case XED_IFORMFL_VCVTTPS2UDQ_FIRST: + case XED_IFORMFL_VCVTTPS2UDQ_LAST: + case XED_IFORMFL_VCVTTPS2UQQ_FIRST: + case XED_IFORMFL_VCVTTPS2UQQ_LAST: + case XED_IFORMFL_VCVTTSD2SI_FIRST: + case XED_IFORMFL_VCVTTSD2SI_LAST: + case XED_IFORMFL_VCVTTSD2USI_FIRST: + case XED_IFORMFL_VCVTTSD2USI_LAST: + case XED_IFORMFL_VCVTTSH2SI_FIRST: + case XED_IFORMFL_VCVTTSH2SI_LAST: + case XED_IFORMFL_VCVTTSH2USI_FIRST: + case XED_IFORMFL_VCVTTSH2USI_LAST: + case XED_IFORMFL_VCVTTSS2SI_FIRST: + case XED_IFORMFL_VCVTTSS2SI_LAST: + case XED_IFORMFL_VCVTTSS2USI_FIRST: + case XED_IFORMFL_VCVTTSS2USI_LAST: + case XED_IFORMFL_VCVTUDQ2PD_FIRST: + case XED_IFORMFL_VCVTUDQ2PD_LAST: + case XED_IFORMFL_VCVTUDQ2PH_FIRST: + case XED_IFORMFL_VCVTUDQ2PH_LAST: + case XED_IFORMFL_VCVTUDQ2PS_FIRST: + case XED_IFORMFL_VCVTUDQ2PS_LAST: + case XED_IFORMFL_VCVTUQQ2PD_FIRST: + case XED_IFORMFL_VCVTUQQ2PD_LAST: + case XED_IFORMFL_VCVTUQQ2PH_FIRST: + case XED_IFORMFL_VCVTUQQ2PH_LAST: + case XED_IFORMFL_VCVTUQQ2PS_FIRST: + case XED_IFORMFL_VCVTUQQ2PS_LAST: + case XED_IFORMFL_VCVTUSI2SD_FIRST: + case XED_IFORMFL_VCVTUSI2SD_LAST: + case XED_IFORMFL_VCVTUSI2SH_FIRST: + case XED_IFORMFL_VCVTUSI2SH_LAST: + case XED_IFORMFL_VCVTUSI2SS_FIRST: + case XED_IFORMFL_VCVTUSI2SS_LAST: + case XED_IFORMFL_VCVTUW2PH_FIRST: + case XED_IFORMFL_VCVTUW2PH_LAST: + case XED_IFORMFL_VCVTW2PH_FIRST: + case XED_IFORMFL_VCVTW2PH_LAST: + case XED_IFORMFL_VDBPSADBW_FIRST: + case XED_IFORMFL_VDBPSADBW_LAST: + case XED_IFORMFL_VDIVPD_FIRST: + case XED_IFORMFL_VDIVPD_LAST: + case XED_IFORMFL_VDIVPH_FIRST: + case XED_IFORMFL_VDIVPH_LAST: + case XED_IFORMFL_VDIVPS_FIRST: + case XED_IFORMFL_VDIVPS_LAST: + case XED_IFORMFL_VDIVSD_FIRST: + case XED_IFORMFL_VDIVSD_LAST: + case XED_IFORMFL_VDIVSH_FIRST: + case XED_IFORMFL_VDIVSH_LAST: + case XED_IFORMFL_VDIVSS_FIRST: + case XED_IFORMFL_VDIVSS_LAST: + case XED_IFORMFL_VDPBF16PS_FIRST: + case XED_IFORMFL_VDPBF16PS_LAST: + case XED_IFORMFL_VDPPD_FIRST: + case XED_IFORMFL_VDPPD_LAST: + case XED_IFORMFL_VDPPS_FIRST: + case XED_IFORMFL_VDPPS_LAST: + case XED_IFORMFL_VERR_FIRST: + case XED_IFORMFL_VERR_LAST: + case XED_IFORMFL_VERW_FIRST: + case XED_IFORMFL_VERW_LAST: + case XED_IFORMFL_VEXP2PD_FIRST: + case XED_IFORMFL_VEXP2PD_LAST: + case XED_IFORMFL_VEXP2PS_FIRST: + case XED_IFORMFL_VEXP2PS_LAST: + case XED_IFORMFL_VEXPANDPD_FIRST: + case XED_IFORMFL_VEXPANDPD_LAST: + case XED_IFORMFL_VEXPANDPS_FIRST: + case XED_IFORMFL_VEXPANDPS_LAST: + case XED_IFORMFL_VEXTRACTF128_FIRST: + case XED_IFORMFL_VEXTRACTF128_LAST: + case XED_IFORMFL_VEXTRACTF32X4_FIRST: + case XED_IFORMFL_VEXTRACTF32X4_LAST: + case XED_IFORMFL_VEXTRACTF32X8_FIRST: + case XED_IFORMFL_VEXTRACTF32X8_LAST: + case XED_IFORMFL_VEXTRACTF64X2_FIRST: + case XED_IFORMFL_VEXTRACTF64X2_LAST: + case XED_IFORMFL_VEXTRACTF64X4_FIRST: + case XED_IFORMFL_VEXTRACTF64X4_LAST: + case XED_IFORMFL_VEXTRACTI128_FIRST: + case XED_IFORMFL_VEXTRACTI128_LAST: + case XED_IFORMFL_VEXTRACTI32X4_FIRST: + case XED_IFORMFL_VEXTRACTI32X4_LAST: + case XED_IFORMFL_VEXTRACTI32X8_FIRST: + case XED_IFORMFL_VEXTRACTI32X8_LAST: + case XED_IFORMFL_VEXTRACTI64X2_FIRST: + case XED_IFORMFL_VEXTRACTI64X2_LAST: + case XED_IFORMFL_VEXTRACTI64X4_FIRST: + case XED_IFORMFL_VEXTRACTI64X4_LAST: + case XED_IFORMFL_VEXTRACTPS_FIRST: + case XED_IFORMFL_VEXTRACTPS_LAST: + case XED_IFORMFL_VFCMADDCPH_FIRST: + case XED_IFORMFL_VFCMADDCPH_LAST: + case XED_IFORMFL_VFCMADDCSH_FIRST: + case XED_IFORMFL_VFCMADDCSH_LAST: + case XED_IFORMFL_VFCMULCPH_FIRST: + case XED_IFORMFL_VFCMULCPH_LAST: + case XED_IFORMFL_VFCMULCSH_FIRST: + case XED_IFORMFL_VFCMULCSH_LAST: + case XED_IFORMFL_VFIXUPIMMPD_FIRST: + case XED_IFORMFL_VFIXUPIMMPD_LAST: + case XED_IFORMFL_VFIXUPIMMPS_FIRST: + case XED_IFORMFL_VFIXUPIMMPS_LAST: + case XED_IFORMFL_VFIXUPIMMSD_FIRST: + case XED_IFORMFL_VFIXUPIMMSD_LAST: + case XED_IFORMFL_VFIXUPIMMSS_FIRST: + case XED_IFORMFL_VFIXUPIMMSS_LAST: + case XED_IFORMFL_VFMADD132PD_FIRST: + case XED_IFORMFL_VFMADD132PD_LAST: + case XED_IFORMFL_VFMADD132PH_FIRST: + case XED_IFORMFL_VFMADD132PH_LAST: + case XED_IFORMFL_VFMADD132PS_FIRST: + case XED_IFORMFL_VFMADD132PS_LAST: + case XED_IFORMFL_VFMADD132SD_FIRST: + case XED_IFORMFL_VFMADD132SD_LAST: + case XED_IFORMFL_VFMADD132SH_FIRST: + case XED_IFORMFL_VFMADD132SH_LAST: + case XED_IFORMFL_VFMADD132SS_FIRST: + case XED_IFORMFL_VFMADD132SS_LAST: + case XED_IFORMFL_VFMADD213PD_FIRST: + case XED_IFORMFL_VFMADD213PD_LAST: + case XED_IFORMFL_VFMADD213PH_FIRST: + case XED_IFORMFL_VFMADD213PH_LAST: + case XED_IFORMFL_VFMADD213PS_FIRST: + case XED_IFORMFL_VFMADD213PS_LAST: + case XED_IFORMFL_VFMADD213SD_FIRST: + case XED_IFORMFL_VFMADD213SD_LAST: + case XED_IFORMFL_VFMADD213SH_FIRST: + case XED_IFORMFL_VFMADD213SH_LAST: + case XED_IFORMFL_VFMADD213SS_FIRST: + case XED_IFORMFL_VFMADD213SS_LAST: + case XED_IFORMFL_VFMADD231PD_FIRST: + case XED_IFORMFL_VFMADD231PD_LAST: + case XED_IFORMFL_VFMADD231PH_FIRST: + case XED_IFORMFL_VFMADD231PH_LAST: + case XED_IFORMFL_VFMADD231PS_FIRST: + case XED_IFORMFL_VFMADD231PS_LAST: + case XED_IFORMFL_VFMADD231SD_FIRST: + case XED_IFORMFL_VFMADD231SD_LAST: + case XED_IFORMFL_VFMADD231SH_FIRST: + case XED_IFORMFL_VFMADD231SH_LAST: + case XED_IFORMFL_VFMADD231SS_FIRST: + case XED_IFORMFL_VFMADD231SS_LAST: + case XED_IFORMFL_VFMADDCPH_FIRST: + case XED_IFORMFL_VFMADDCPH_LAST: + case XED_IFORMFL_VFMADDCSH_FIRST: + case XED_IFORMFL_VFMADDCSH_LAST: + case XED_IFORMFL_VFMADDPD_FIRST: + case XED_IFORMFL_VFMADDPD_LAST: + case XED_IFORMFL_VFMADDPS_FIRST: + case XED_IFORMFL_VFMADDPS_LAST: + case XED_IFORMFL_VFMADDSD_FIRST: + case XED_IFORMFL_VFMADDSD_LAST: + case XED_IFORMFL_VFMADDSS_FIRST: + case XED_IFORMFL_VFMADDSS_LAST: + case XED_IFORMFL_VFMADDSUB132PD_FIRST: + case XED_IFORMFL_VFMADDSUB132PD_LAST: + case XED_IFORMFL_VFMADDSUB132PH_FIRST: + case XED_IFORMFL_VFMADDSUB132PH_LAST: + case XED_IFORMFL_VFMADDSUB132PS_FIRST: + case XED_IFORMFL_VFMADDSUB132PS_LAST: + case XED_IFORMFL_VFMADDSUB213PD_FIRST: + case XED_IFORMFL_VFMADDSUB213PD_LAST: + case XED_IFORMFL_VFMADDSUB213PH_FIRST: + case XED_IFORMFL_VFMADDSUB213PH_LAST: + case XED_IFORMFL_VFMADDSUB213PS_FIRST: + case XED_IFORMFL_VFMADDSUB213PS_LAST: + case XED_IFORMFL_VFMADDSUB231PD_FIRST: + case XED_IFORMFL_VFMADDSUB231PD_LAST: + case XED_IFORMFL_VFMADDSUB231PH_FIRST: + case XED_IFORMFL_VFMADDSUB231PH_LAST: + case XED_IFORMFL_VFMADDSUB231PS_FIRST: + case XED_IFORMFL_VFMADDSUB231PS_LAST: + case XED_IFORMFL_VFMADDSUBPD_FIRST: + case XED_IFORMFL_VFMADDSUBPD_LAST: + case XED_IFORMFL_VFMADDSUBPS_FIRST: + case XED_IFORMFL_VFMADDSUBPS_LAST: + case XED_IFORMFL_VFMSUB132PD_FIRST: + case XED_IFORMFL_VFMSUB132PD_LAST: + case XED_IFORMFL_VFMSUB132PH_FIRST: + case XED_IFORMFL_VFMSUB132PH_LAST: + case XED_IFORMFL_VFMSUB132PS_FIRST: + case XED_IFORMFL_VFMSUB132PS_LAST: + case XED_IFORMFL_VFMSUB132SD_FIRST: + case XED_IFORMFL_VFMSUB132SD_LAST: + case XED_IFORMFL_VFMSUB132SH_FIRST: + case XED_IFORMFL_VFMSUB132SH_LAST: + case XED_IFORMFL_VFMSUB132SS_FIRST: + case XED_IFORMFL_VFMSUB132SS_LAST: + case XED_IFORMFL_VFMSUB213PD_FIRST: + case XED_IFORMFL_VFMSUB213PD_LAST: + case XED_IFORMFL_VFMSUB213PH_FIRST: + case XED_IFORMFL_VFMSUB213PH_LAST: + case XED_IFORMFL_VFMSUB213PS_FIRST: + case XED_IFORMFL_VFMSUB213PS_LAST: + case XED_IFORMFL_VFMSUB213SD_FIRST: + case XED_IFORMFL_VFMSUB213SD_LAST: + case XED_IFORMFL_VFMSUB213SH_FIRST: + case XED_IFORMFL_VFMSUB213SH_LAST: + case XED_IFORMFL_VFMSUB213SS_FIRST: + case XED_IFORMFL_VFMSUB213SS_LAST: + case XED_IFORMFL_VFMSUB231PD_FIRST: + case XED_IFORMFL_VFMSUB231PD_LAST: + case XED_IFORMFL_VFMSUB231PH_FIRST: + case XED_IFORMFL_VFMSUB231PH_LAST: + case XED_IFORMFL_VFMSUB231PS_FIRST: + case XED_IFORMFL_VFMSUB231PS_LAST: + case XED_IFORMFL_VFMSUB231SD_FIRST: + case XED_IFORMFL_VFMSUB231SD_LAST: + case XED_IFORMFL_VFMSUB231SH_FIRST: + case XED_IFORMFL_VFMSUB231SH_LAST: + case XED_IFORMFL_VFMSUB231SS_FIRST: + case XED_IFORMFL_VFMSUB231SS_LAST: + case XED_IFORMFL_VFMSUBADD132PD_FIRST: + case XED_IFORMFL_VFMSUBADD132PD_LAST: + case XED_IFORMFL_VFMSUBADD132PH_FIRST: + case XED_IFORMFL_VFMSUBADD132PH_LAST: + case XED_IFORMFL_VFMSUBADD132PS_FIRST: + case XED_IFORMFL_VFMSUBADD132PS_LAST: + case XED_IFORMFL_VFMSUBADD213PD_FIRST: + case XED_IFORMFL_VFMSUBADD213PD_LAST: + case XED_IFORMFL_VFMSUBADD213PH_FIRST: + case XED_IFORMFL_VFMSUBADD213PH_LAST: + case XED_IFORMFL_VFMSUBADD213PS_FIRST: + case XED_IFORMFL_VFMSUBADD213PS_LAST: + case XED_IFORMFL_VFMSUBADD231PD_FIRST: + case XED_IFORMFL_VFMSUBADD231PD_LAST: + case XED_IFORMFL_VFMSUBADD231PH_FIRST: + case XED_IFORMFL_VFMSUBADD231PH_LAST: + case XED_IFORMFL_VFMSUBADD231PS_FIRST: + case XED_IFORMFL_VFMSUBADD231PS_LAST: + case XED_IFORMFL_VFMSUBADDPD_FIRST: + case XED_IFORMFL_VFMSUBADDPD_LAST: + case XED_IFORMFL_VFMSUBADDPS_FIRST: + case XED_IFORMFL_VFMSUBADDPS_LAST: + case XED_IFORMFL_VFMSUBPD_FIRST: + case XED_IFORMFL_VFMSUBPD_LAST: + case XED_IFORMFL_VFMSUBPS_FIRST: + case XED_IFORMFL_VFMSUBPS_LAST: + case XED_IFORMFL_VFMSUBSD_FIRST: + case XED_IFORMFL_VFMSUBSD_LAST: + case XED_IFORMFL_VFMSUBSS_FIRST: + case XED_IFORMFL_VFMSUBSS_LAST: + case XED_IFORMFL_VFMULCPH_FIRST: + case XED_IFORMFL_VFMULCPH_LAST: + case XED_IFORMFL_VFMULCSH_FIRST: + case XED_IFORMFL_VFMULCSH_LAST: + case XED_IFORMFL_VFNMADD132PD_FIRST: + case XED_IFORMFL_VFNMADD132PD_LAST: + case XED_IFORMFL_VFNMADD132PH_FIRST: + case XED_IFORMFL_VFNMADD132PH_LAST: + case XED_IFORMFL_VFNMADD132PS_FIRST: + case XED_IFORMFL_VFNMADD132PS_LAST: + case XED_IFORMFL_VFNMADD132SD_FIRST: + case XED_IFORMFL_VFNMADD132SD_LAST: + case XED_IFORMFL_VFNMADD132SH_FIRST: + case XED_IFORMFL_VFNMADD132SH_LAST: + case XED_IFORMFL_VFNMADD132SS_FIRST: + case XED_IFORMFL_VFNMADD132SS_LAST: + case XED_IFORMFL_VFNMADD213PD_FIRST: + case XED_IFORMFL_VFNMADD213PD_LAST: + case XED_IFORMFL_VFNMADD213PH_FIRST: + case XED_IFORMFL_VFNMADD213PH_LAST: + case XED_IFORMFL_VFNMADD213PS_FIRST: + case XED_IFORMFL_VFNMADD213PS_LAST: + case XED_IFORMFL_VFNMADD213SD_FIRST: + case XED_IFORMFL_VFNMADD213SD_LAST: + case XED_IFORMFL_VFNMADD213SH_FIRST: + case XED_IFORMFL_VFNMADD213SH_LAST: + case XED_IFORMFL_VFNMADD213SS_FIRST: + case XED_IFORMFL_VFNMADD213SS_LAST: + case XED_IFORMFL_VFNMADD231PD_FIRST: + case XED_IFORMFL_VFNMADD231PD_LAST: + case XED_IFORMFL_VFNMADD231PH_FIRST: + case XED_IFORMFL_VFNMADD231PH_LAST: + case XED_IFORMFL_VFNMADD231PS_FIRST: + case XED_IFORMFL_VFNMADD231PS_LAST: + case XED_IFORMFL_VFNMADD231SD_FIRST: + case XED_IFORMFL_VFNMADD231SD_LAST: + case XED_IFORMFL_VFNMADD231SH_FIRST: + case XED_IFORMFL_VFNMADD231SH_LAST: + case XED_IFORMFL_VFNMADD231SS_FIRST: + case XED_IFORMFL_VFNMADD231SS_LAST: + case XED_IFORMFL_VFNMADDPD_FIRST: + case XED_IFORMFL_VFNMADDPD_LAST: + case XED_IFORMFL_VFNMADDPS_FIRST: + case XED_IFORMFL_VFNMADDPS_LAST: + case XED_IFORMFL_VFNMADDSD_FIRST: + case XED_IFORMFL_VFNMADDSD_LAST: + case XED_IFORMFL_VFNMADDSS_FIRST: + case XED_IFORMFL_VFNMADDSS_LAST: + case XED_IFORMFL_VFNMSUB132PD_FIRST: + case XED_IFORMFL_VFNMSUB132PD_LAST: + case XED_IFORMFL_VFNMSUB132PH_FIRST: + case XED_IFORMFL_VFNMSUB132PH_LAST: + case XED_IFORMFL_VFNMSUB132PS_FIRST: + case XED_IFORMFL_VFNMSUB132PS_LAST: + case XED_IFORMFL_VFNMSUB132SD_FIRST: + case XED_IFORMFL_VFNMSUB132SD_LAST: + case XED_IFORMFL_VFNMSUB132SH_FIRST: + case XED_IFORMFL_VFNMSUB132SH_LAST: + case XED_IFORMFL_VFNMSUB132SS_FIRST: + case XED_IFORMFL_VFNMSUB132SS_LAST: + case XED_IFORMFL_VFNMSUB213PD_FIRST: + case XED_IFORMFL_VFNMSUB213PD_LAST: + case XED_IFORMFL_VFNMSUB213PH_FIRST: + case XED_IFORMFL_VFNMSUB213PH_LAST: + case XED_IFORMFL_VFNMSUB213PS_FIRST: + case XED_IFORMFL_VFNMSUB213PS_LAST: + case XED_IFORMFL_VFNMSUB213SD_FIRST: + case XED_IFORMFL_VFNMSUB213SD_LAST: + case XED_IFORMFL_VFNMSUB213SH_FIRST: + case XED_IFORMFL_VFNMSUB213SH_LAST: + case XED_IFORMFL_VFNMSUB213SS_FIRST: + case XED_IFORMFL_VFNMSUB213SS_LAST: + case XED_IFORMFL_VFNMSUB231PD_FIRST: + case XED_IFORMFL_VFNMSUB231PD_LAST: + case XED_IFORMFL_VFNMSUB231PH_FIRST: + case XED_IFORMFL_VFNMSUB231PH_LAST: + case XED_IFORMFL_VFNMSUB231PS_FIRST: + case XED_IFORMFL_VFNMSUB231PS_LAST: + case XED_IFORMFL_VFNMSUB231SD_FIRST: + case XED_IFORMFL_VFNMSUB231SD_LAST: + case XED_IFORMFL_VFNMSUB231SH_FIRST: + case XED_IFORMFL_VFNMSUB231SH_LAST: + case XED_IFORMFL_VFNMSUB231SS_FIRST: + case XED_IFORMFL_VFNMSUB231SS_LAST: + case XED_IFORMFL_VFNMSUBPD_FIRST: + case XED_IFORMFL_VFNMSUBPD_LAST: + case XED_IFORMFL_VFNMSUBPS_FIRST: + case XED_IFORMFL_VFNMSUBPS_LAST: + case XED_IFORMFL_VFNMSUBSD_FIRST: + case XED_IFORMFL_VFNMSUBSD_LAST: + case XED_IFORMFL_VFNMSUBSS_FIRST: + case XED_IFORMFL_VFNMSUBSS_LAST: + case XED_IFORMFL_VFPCLASSPD_FIRST: + case XED_IFORMFL_VFPCLASSPD_LAST: + case XED_IFORMFL_VFPCLASSPH_FIRST: + case XED_IFORMFL_VFPCLASSPH_LAST: + case XED_IFORMFL_VFPCLASSPS_FIRST: + case XED_IFORMFL_VFPCLASSPS_LAST: + case XED_IFORMFL_VFPCLASSSD_FIRST: + case XED_IFORMFL_VFPCLASSSD_LAST: + case XED_IFORMFL_VFPCLASSSH_FIRST: + case XED_IFORMFL_VFPCLASSSH_LAST: + case XED_IFORMFL_VFPCLASSSS_FIRST: + case XED_IFORMFL_VFPCLASSSS_LAST: + case XED_IFORMFL_VFRCZPD_FIRST: + case XED_IFORMFL_VFRCZPD_LAST: + case XED_IFORMFL_VFRCZPS_FIRST: + case XED_IFORMFL_VFRCZPS_LAST: + case XED_IFORMFL_VFRCZSD_FIRST: + case XED_IFORMFL_VFRCZSD_LAST: + case XED_IFORMFL_VFRCZSS_FIRST: + case XED_IFORMFL_VFRCZSS_LAST: + case XED_IFORMFL_VGATHERDPD_FIRST: + case XED_IFORMFL_VGATHERDPD_LAST: + case XED_IFORMFL_VGATHERDPS_FIRST: + case XED_IFORMFL_VGATHERDPS_LAST: + case XED_IFORMFL_VGATHERPF0DPD_FIRST: + case XED_IFORMFL_VGATHERPF0DPD_LAST: + case XED_IFORMFL_VGATHERPF0DPS_FIRST: + case XED_IFORMFL_VGATHERPF0DPS_LAST: + case XED_IFORMFL_VGATHERPF0QPD_FIRST: + case XED_IFORMFL_VGATHERPF0QPD_LAST: + case XED_IFORMFL_VGATHERPF0QPS_FIRST: + case XED_IFORMFL_VGATHERPF0QPS_LAST: + case XED_IFORMFL_VGATHERPF1DPD_FIRST: + case XED_IFORMFL_VGATHERPF1DPD_LAST: + case XED_IFORMFL_VGATHERPF1DPS_FIRST: + case XED_IFORMFL_VGATHERPF1DPS_LAST: + case XED_IFORMFL_VGATHERPF1QPD_FIRST: + case XED_IFORMFL_VGATHERPF1QPD_LAST: + case XED_IFORMFL_VGATHERPF1QPS_FIRST: + case XED_IFORMFL_VGATHERPF1QPS_LAST: + case XED_IFORMFL_VGATHERQPD_FIRST: + case XED_IFORMFL_VGATHERQPD_LAST: + case XED_IFORMFL_VGATHERQPS_FIRST: + case XED_IFORMFL_VGATHERQPS_LAST: + case XED_IFORMFL_VGETEXPPD_FIRST: + case XED_IFORMFL_VGETEXPPD_LAST: + case XED_IFORMFL_VGETEXPPH_FIRST: + case XED_IFORMFL_VGETEXPPH_LAST: + case XED_IFORMFL_VGETEXPPS_FIRST: + case XED_IFORMFL_VGETEXPPS_LAST: + case XED_IFORMFL_VGETEXPSD_FIRST: + case XED_IFORMFL_VGETEXPSD_LAST: + case XED_IFORMFL_VGETEXPSH_FIRST: + case XED_IFORMFL_VGETEXPSH_LAST: + case XED_IFORMFL_VGETEXPSS_FIRST: + case XED_IFORMFL_VGETEXPSS_LAST: + case XED_IFORMFL_VGETMANTPD_FIRST: + case XED_IFORMFL_VGETMANTPD_LAST: + case XED_IFORMFL_VGETMANTPH_FIRST: + case XED_IFORMFL_VGETMANTPH_LAST: + case XED_IFORMFL_VGETMANTPS_FIRST: + case XED_IFORMFL_VGETMANTPS_LAST: + case XED_IFORMFL_VGETMANTSD_FIRST: + case XED_IFORMFL_VGETMANTSD_LAST: + case XED_IFORMFL_VGETMANTSH_FIRST: + case XED_IFORMFL_VGETMANTSH_LAST: + case XED_IFORMFL_VGETMANTSS_FIRST: + case XED_IFORMFL_VGETMANTSS_LAST: + case XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST: + case XED_IFORMFL_VGF2P8AFFINEINVQB_LAST: + case XED_IFORMFL_VGF2P8AFFINEQB_FIRST: + case XED_IFORMFL_VGF2P8AFFINEQB_LAST: + case XED_IFORMFL_VGF2P8MULB_FIRST: + case XED_IFORMFL_VGF2P8MULB_LAST: + case XED_IFORMFL_VHADDPD_FIRST: + case XED_IFORMFL_VHADDPD_LAST: + case XED_IFORMFL_VHADDPS_FIRST: + case XED_IFORMFL_VHADDPS_LAST: + case XED_IFORMFL_VHSUBPD_FIRST: + case XED_IFORMFL_VHSUBPD_LAST: + case XED_IFORMFL_VHSUBPS_FIRST: + case XED_IFORMFL_VHSUBPS_LAST: + case XED_IFORMFL_VINSERTF128_FIRST: + case XED_IFORMFL_VINSERTF128_LAST: + case XED_IFORMFL_VINSERTF32X4_FIRST: + case XED_IFORMFL_VINSERTF32X4_LAST: + case XED_IFORMFL_VINSERTF32X8_FIRST: + case XED_IFORMFL_VINSERTF32X8_LAST: + case XED_IFORMFL_VINSERTF64X2_FIRST: + case XED_IFORMFL_VINSERTF64X2_LAST: + case XED_IFORMFL_VINSERTF64X4_FIRST: + case XED_IFORMFL_VINSERTF64X4_LAST: + case XED_IFORMFL_VINSERTI128_FIRST: + case XED_IFORMFL_VINSERTI128_LAST: + case XED_IFORMFL_VINSERTI32X4_FIRST: + case XED_IFORMFL_VINSERTI32X4_LAST: + case XED_IFORMFL_VINSERTI32X8_FIRST: + case XED_IFORMFL_VINSERTI32X8_LAST: + case XED_IFORMFL_VINSERTI64X2_FIRST: + case XED_IFORMFL_VINSERTI64X2_LAST: + case XED_IFORMFL_VINSERTI64X4_FIRST: + case XED_IFORMFL_VINSERTI64X4_LAST: + case XED_IFORMFL_VINSERTPS_FIRST: + case XED_IFORMFL_VINSERTPS_LAST: + case XED_IFORMFL_VLDDQU_FIRST: + case XED_IFORMFL_VLDDQU_LAST: + case XED_IFORMFL_VLDMXCSR_FIRST: + case XED_IFORMFL_VLDMXCSR_LAST: + case XED_IFORMFL_VMASKMOVDQU_FIRST: + case XED_IFORMFL_VMASKMOVDQU_LAST: + case XED_IFORMFL_VMASKMOVPD_FIRST: + case XED_IFORMFL_VMASKMOVPD_LAST: + case XED_IFORMFL_VMASKMOVPS_FIRST: + case XED_IFORMFL_VMASKMOVPS_LAST: + case XED_IFORMFL_VMAXPD_FIRST: + case XED_IFORMFL_VMAXPD_LAST: + case XED_IFORMFL_VMAXPH_FIRST: + case XED_IFORMFL_VMAXPH_LAST: + case XED_IFORMFL_VMAXPS_FIRST: + case XED_IFORMFL_VMAXPS_LAST: + case XED_IFORMFL_VMAXSD_FIRST: + case XED_IFORMFL_VMAXSD_LAST: + case XED_IFORMFL_VMAXSH_FIRST: + case XED_IFORMFL_VMAXSH_LAST: + case XED_IFORMFL_VMAXSS_FIRST: + case XED_IFORMFL_VMAXSS_LAST: + case XED_IFORMFL_VMCALL_FIRST: + case XED_IFORMFL_VMCALL_LAST: + case XED_IFORMFL_VMCLEAR_FIRST: + case XED_IFORMFL_VMCLEAR_LAST: + case XED_IFORMFL_VMFUNC_FIRST: + case XED_IFORMFL_VMFUNC_LAST: + case XED_IFORMFL_VMINPD_FIRST: + case XED_IFORMFL_VMINPD_LAST: + case XED_IFORMFL_VMINPH_FIRST: + case XED_IFORMFL_VMINPH_LAST: + case XED_IFORMFL_VMINPS_FIRST: + case XED_IFORMFL_VMINPS_LAST: + case XED_IFORMFL_VMINSD_FIRST: + case XED_IFORMFL_VMINSD_LAST: + case XED_IFORMFL_VMINSH_FIRST: + case XED_IFORMFL_VMINSH_LAST: + case XED_IFORMFL_VMINSS_FIRST: + case XED_IFORMFL_VMINSS_LAST: + case XED_IFORMFL_VMLAUNCH_FIRST: + case XED_IFORMFL_VMLAUNCH_LAST: + case XED_IFORMFL_VMLOAD_FIRST: + case XED_IFORMFL_VMLOAD_LAST: + case XED_IFORMFL_VMMCALL_FIRST: + case XED_IFORMFL_VMMCALL_LAST: + case XED_IFORMFL_VMOVAPD_FIRST: + case XED_IFORMFL_VMOVAPD_LAST: + case XED_IFORMFL_VMOVAPS_FIRST: + case XED_IFORMFL_VMOVAPS_LAST: + case XED_IFORMFL_VMOVD_FIRST: + case XED_IFORMFL_VMOVD_LAST: + case XED_IFORMFL_VMOVDDUP_FIRST: + case XED_IFORMFL_VMOVDDUP_LAST: + case XED_IFORMFL_VMOVDQA_FIRST: + case XED_IFORMFL_VMOVDQA_LAST: + case XED_IFORMFL_VMOVDQA32_FIRST: + case XED_IFORMFL_VMOVDQA32_LAST: + case XED_IFORMFL_VMOVDQA64_FIRST: + case XED_IFORMFL_VMOVDQA64_LAST: + case XED_IFORMFL_VMOVDQU_FIRST: + case XED_IFORMFL_VMOVDQU_LAST: + case XED_IFORMFL_VMOVDQU16_FIRST: + case XED_IFORMFL_VMOVDQU16_LAST: + case XED_IFORMFL_VMOVDQU32_FIRST: + case XED_IFORMFL_VMOVDQU32_LAST: + case XED_IFORMFL_VMOVDQU64_FIRST: + case XED_IFORMFL_VMOVDQU64_LAST: + case XED_IFORMFL_VMOVDQU8_FIRST: + case XED_IFORMFL_VMOVDQU8_LAST: + case XED_IFORMFL_VMOVHLPS_FIRST: + case XED_IFORMFL_VMOVHLPS_LAST: + case XED_IFORMFL_VMOVHPD_FIRST: + case XED_IFORMFL_VMOVHPD_LAST: + case XED_IFORMFL_VMOVHPS_FIRST: + case XED_IFORMFL_VMOVHPS_LAST: + case XED_IFORMFL_VMOVLHPS_FIRST: + case XED_IFORMFL_VMOVLHPS_LAST: + case XED_IFORMFL_VMOVLPD_FIRST: + case XED_IFORMFL_VMOVLPD_LAST: + case XED_IFORMFL_VMOVLPS_FIRST: + case XED_IFORMFL_VMOVLPS_LAST: + case XED_IFORMFL_VMOVMSKPD_FIRST: + case XED_IFORMFL_VMOVMSKPD_LAST: + case XED_IFORMFL_VMOVMSKPS_FIRST: + case XED_IFORMFL_VMOVMSKPS_LAST: + case XED_IFORMFL_VMOVNTDQ_FIRST: + case XED_IFORMFL_VMOVNTDQ_LAST: + case XED_IFORMFL_VMOVNTDQA_FIRST: + case XED_IFORMFL_VMOVNTDQA_LAST: + case XED_IFORMFL_VMOVNTPD_FIRST: + case XED_IFORMFL_VMOVNTPD_LAST: + case XED_IFORMFL_VMOVNTPS_FIRST: + case XED_IFORMFL_VMOVNTPS_LAST: + case XED_IFORMFL_VMOVQ_FIRST: + case XED_IFORMFL_VMOVQ_LAST: + case XED_IFORMFL_VMOVSD_FIRST: + case XED_IFORMFL_VMOVSD_LAST: + case XED_IFORMFL_VMOVSH_FIRST: + case XED_IFORMFL_VMOVSH_LAST: + case XED_IFORMFL_VMOVSHDUP_FIRST: + case XED_IFORMFL_VMOVSHDUP_LAST: + case XED_IFORMFL_VMOVSLDUP_FIRST: + case XED_IFORMFL_VMOVSLDUP_LAST: + case XED_IFORMFL_VMOVSS_FIRST: + case XED_IFORMFL_VMOVSS_LAST: + case XED_IFORMFL_VMOVUPD_FIRST: + case XED_IFORMFL_VMOVUPD_LAST: + case XED_IFORMFL_VMOVUPS_FIRST: + case XED_IFORMFL_VMOVUPS_LAST: + case XED_IFORMFL_VMOVW_FIRST: + case XED_IFORMFL_VMOVW_LAST: + case XED_IFORMFL_VMPSADBW_FIRST: + case XED_IFORMFL_VMPSADBW_LAST: + case XED_IFORMFL_VMPTRLD_FIRST: + case XED_IFORMFL_VMPTRLD_LAST: + case XED_IFORMFL_VMPTRST_FIRST: + case XED_IFORMFL_VMPTRST_LAST: + case XED_IFORMFL_VMREAD_FIRST: + case XED_IFORMFL_VMREAD_LAST: + case XED_IFORMFL_VMRESUME_FIRST: + case XED_IFORMFL_VMRESUME_LAST: + case XED_IFORMFL_VMRUN_FIRST: + case XED_IFORMFL_VMRUN_LAST: + case XED_IFORMFL_VMSAVE_FIRST: + case XED_IFORMFL_VMSAVE_LAST: + case XED_IFORMFL_VMULPD_FIRST: + case XED_IFORMFL_VMULPD_LAST: + case XED_IFORMFL_VMULPH_FIRST: + case XED_IFORMFL_VMULPH_LAST: + case XED_IFORMFL_VMULPS_FIRST: + case XED_IFORMFL_VMULPS_LAST: + case XED_IFORMFL_VMULSD_FIRST: + case XED_IFORMFL_VMULSD_LAST: + case XED_IFORMFL_VMULSH_FIRST: + case XED_IFORMFL_VMULSH_LAST: + case XED_IFORMFL_VMULSS_FIRST: + case XED_IFORMFL_VMULSS_LAST: + case XED_IFORMFL_VMWRITE_FIRST: + case XED_IFORMFL_VMWRITE_LAST: + case XED_IFORMFL_VMXOFF_FIRST: + case XED_IFORMFL_VMXOFF_LAST: + case XED_IFORMFL_VMXON_FIRST: + case XED_IFORMFL_VMXON_LAST: + case XED_IFORMFL_VORPD_FIRST: + case XED_IFORMFL_VORPD_LAST: + case XED_IFORMFL_VORPS_FIRST: + case XED_IFORMFL_VORPS_LAST: + case XED_IFORMFL_VP2INTERSECTD_FIRST: + case XED_IFORMFL_VP2INTERSECTD_LAST: + case XED_IFORMFL_VP2INTERSECTQ_FIRST: + case XED_IFORMFL_VP2INTERSECTQ_LAST: + case XED_IFORMFL_VP4DPWSSD_FIRST: + case XED_IFORMFL_VP4DPWSSD_LAST: + case XED_IFORMFL_VP4DPWSSDS_FIRST: + case XED_IFORMFL_VP4DPWSSDS_LAST: + case XED_IFORMFL_VPABSB_FIRST: + case XED_IFORMFL_VPABSB_LAST: + case XED_IFORMFL_VPABSD_FIRST: + case XED_IFORMFL_VPABSD_LAST: + case XED_IFORMFL_VPABSQ_FIRST: + case XED_IFORMFL_VPABSQ_LAST: + case XED_IFORMFL_VPABSW_FIRST: + case XED_IFORMFL_VPABSW_LAST: + case XED_IFORMFL_VPACKSSDW_FIRST: + case XED_IFORMFL_VPACKSSDW_LAST: + case XED_IFORMFL_VPACKSSWB_FIRST: + case XED_IFORMFL_VPACKSSWB_LAST: + case XED_IFORMFL_VPACKUSDW_FIRST: + case XED_IFORMFL_VPACKUSDW_LAST: + case XED_IFORMFL_VPACKUSWB_FIRST: + case XED_IFORMFL_VPACKUSWB_LAST: + case XED_IFORMFL_VPADDB_FIRST: + case XED_IFORMFL_VPADDB_LAST: + case XED_IFORMFL_VPADDD_FIRST: + case XED_IFORMFL_VPADDD_LAST: + case XED_IFORMFL_VPADDQ_FIRST: + case XED_IFORMFL_VPADDQ_LAST: + case XED_IFORMFL_VPADDSB_FIRST: + case XED_IFORMFL_VPADDSB_LAST: + case XED_IFORMFL_VPADDSW_FIRST: + case XED_IFORMFL_VPADDSW_LAST: + case XED_IFORMFL_VPADDUSB_FIRST: + case XED_IFORMFL_VPADDUSB_LAST: + case XED_IFORMFL_VPADDUSW_FIRST: + case XED_IFORMFL_VPADDUSW_LAST: + case XED_IFORMFL_VPADDW_FIRST: + case XED_IFORMFL_VPADDW_LAST: + case XED_IFORMFL_VPALIGNR_FIRST: + case XED_IFORMFL_VPALIGNR_LAST: + case XED_IFORMFL_VPAND_FIRST: + case XED_IFORMFL_VPAND_LAST: + case XED_IFORMFL_VPANDD_FIRST: + case XED_IFORMFL_VPANDD_LAST: + case XED_IFORMFL_VPANDN_FIRST: + case XED_IFORMFL_VPANDN_LAST: + case XED_IFORMFL_VPANDND_FIRST: + case XED_IFORMFL_VPANDND_LAST: + case XED_IFORMFL_VPANDNQ_FIRST: + case XED_IFORMFL_VPANDNQ_LAST: + case XED_IFORMFL_VPANDQ_FIRST: + case XED_IFORMFL_VPANDQ_LAST: + case XED_IFORMFL_VPAVGB_FIRST: + case XED_IFORMFL_VPAVGB_LAST: + case XED_IFORMFL_VPAVGW_FIRST: + case XED_IFORMFL_VPAVGW_LAST: + case XED_IFORMFL_VPBLENDD_FIRST: + case XED_IFORMFL_VPBLENDD_LAST: + case XED_IFORMFL_VPBLENDMB_FIRST: + case XED_IFORMFL_VPBLENDMB_LAST: + case XED_IFORMFL_VPBLENDMD_FIRST: + case XED_IFORMFL_VPBLENDMD_LAST: + case XED_IFORMFL_VPBLENDMQ_FIRST: + case XED_IFORMFL_VPBLENDMQ_LAST: + case XED_IFORMFL_VPBLENDMW_FIRST: + case XED_IFORMFL_VPBLENDMW_LAST: + case XED_IFORMFL_VPBLENDVB_FIRST: + case XED_IFORMFL_VPBLENDVB_LAST: + case XED_IFORMFL_VPBLENDW_FIRST: + case XED_IFORMFL_VPBLENDW_LAST: + case XED_IFORMFL_VPBROADCASTB_FIRST: + case XED_IFORMFL_VPBROADCASTB_LAST: + case XED_IFORMFL_VPBROADCASTD_FIRST: + case XED_IFORMFL_VPBROADCASTD_LAST: + case XED_IFORMFL_VPBROADCASTMB2Q_FIRST: + case XED_IFORMFL_VPBROADCASTMB2Q_LAST: + case XED_IFORMFL_VPBROADCASTMW2D_FIRST: + case XED_IFORMFL_VPBROADCASTMW2D_LAST: + case XED_IFORMFL_VPBROADCASTQ_FIRST: + case XED_IFORMFL_VPBROADCASTQ_LAST: + case XED_IFORMFL_VPBROADCASTW_FIRST: + case XED_IFORMFL_VPBROADCASTW_LAST: + case XED_IFORMFL_VPCLMULQDQ_FIRST: + case XED_IFORMFL_VPCLMULQDQ_LAST: + case XED_IFORMFL_VPCMOV_FIRST: + case XED_IFORMFL_VPCMOV_LAST: + case XED_IFORMFL_VPCMPB_FIRST: + case XED_IFORMFL_VPCMPB_LAST: + case XED_IFORMFL_VPCMPD_FIRST: + case XED_IFORMFL_VPCMPD_LAST: + case XED_IFORMFL_VPCMPEQB_FIRST: + case XED_IFORMFL_VPCMPEQB_LAST: + case XED_IFORMFL_VPCMPEQD_FIRST: + case XED_IFORMFL_VPCMPEQD_LAST: + case XED_IFORMFL_VPCMPEQQ_FIRST: + case XED_IFORMFL_VPCMPEQQ_LAST: + case XED_IFORMFL_VPCMPEQW_FIRST: + case XED_IFORMFL_VPCMPEQW_LAST: + case XED_IFORMFL_VPCMPESTRI_FIRST: + case XED_IFORMFL_VPCMPESTRI_LAST: + case XED_IFORMFL_VPCMPESTRI64_FIRST: + case XED_IFORMFL_VPCMPESTRI64_LAST: + case XED_IFORMFL_VPCMPESTRM_FIRST: + case XED_IFORMFL_VPCMPESTRM_LAST: + case XED_IFORMFL_VPCMPESTRM64_FIRST: + case XED_IFORMFL_VPCMPESTRM64_LAST: + case XED_IFORMFL_VPCMPGTB_FIRST: + case XED_IFORMFL_VPCMPGTB_LAST: + case XED_IFORMFL_VPCMPGTD_FIRST: + case XED_IFORMFL_VPCMPGTD_LAST: + case XED_IFORMFL_VPCMPGTQ_FIRST: + case XED_IFORMFL_VPCMPGTQ_LAST: + case XED_IFORMFL_VPCMPGTW_FIRST: + case XED_IFORMFL_VPCMPGTW_LAST: + case XED_IFORMFL_VPCMPISTRI_FIRST: + case XED_IFORMFL_VPCMPISTRI_LAST: + case XED_IFORMFL_VPCMPISTRI64_FIRST: + case XED_IFORMFL_VPCMPISTRI64_LAST: + case XED_IFORMFL_VPCMPISTRM_FIRST: + case XED_IFORMFL_VPCMPISTRM_LAST: + case XED_IFORMFL_VPCMPQ_FIRST: + case XED_IFORMFL_VPCMPQ_LAST: + case XED_IFORMFL_VPCMPUB_FIRST: + case XED_IFORMFL_VPCMPUB_LAST: + case XED_IFORMFL_VPCMPUD_FIRST: + case XED_IFORMFL_VPCMPUD_LAST: + case XED_IFORMFL_VPCMPUQ_FIRST: + case XED_IFORMFL_VPCMPUQ_LAST: + case XED_IFORMFL_VPCMPUW_FIRST: + case XED_IFORMFL_VPCMPUW_LAST: + case XED_IFORMFL_VPCMPW_FIRST: + case XED_IFORMFL_VPCMPW_LAST: + case XED_IFORMFL_VPCOMB_FIRST: + case XED_IFORMFL_VPCOMB_LAST: + case XED_IFORMFL_VPCOMD_FIRST: + case XED_IFORMFL_VPCOMD_LAST: + case XED_IFORMFL_VPCOMPRESSB_FIRST: + case XED_IFORMFL_VPCOMPRESSB_LAST: + case XED_IFORMFL_VPCOMPRESSD_FIRST: + case XED_IFORMFL_VPCOMPRESSD_LAST: + case XED_IFORMFL_VPCOMPRESSQ_FIRST: + case XED_IFORMFL_VPCOMPRESSQ_LAST: + case XED_IFORMFL_VPCOMPRESSW_FIRST: + case XED_IFORMFL_VPCOMPRESSW_LAST: + case XED_IFORMFL_VPCOMQ_FIRST: + case XED_IFORMFL_VPCOMQ_LAST: + case XED_IFORMFL_VPCOMUB_FIRST: + case XED_IFORMFL_VPCOMUB_LAST: + case XED_IFORMFL_VPCOMUD_FIRST: + case XED_IFORMFL_VPCOMUD_LAST: + case XED_IFORMFL_VPCOMUQ_FIRST: + case XED_IFORMFL_VPCOMUQ_LAST: + case XED_IFORMFL_VPCOMUW_FIRST: + case XED_IFORMFL_VPCOMUW_LAST: + case XED_IFORMFL_VPCOMW_FIRST: + case XED_IFORMFL_VPCOMW_LAST: + case XED_IFORMFL_VPCONFLICTD_FIRST: + case XED_IFORMFL_VPCONFLICTD_LAST: + case XED_IFORMFL_VPCONFLICTQ_FIRST: + case XED_IFORMFL_VPCONFLICTQ_LAST: + case XED_IFORMFL_VPDPBUSD_FIRST: + case XED_IFORMFL_VPDPBUSD_LAST: + case XED_IFORMFL_VPDPBUSDS_FIRST: + case XED_IFORMFL_VPDPBUSDS_LAST: + case XED_IFORMFL_VPDPWSSD_FIRST: + case XED_IFORMFL_VPDPWSSD_LAST: + case XED_IFORMFL_VPDPWSSDS_FIRST: + case XED_IFORMFL_VPDPWSSDS_LAST: + case XED_IFORMFL_VPERM2F128_FIRST: + case XED_IFORMFL_VPERM2F128_LAST: + case XED_IFORMFL_VPERM2I128_FIRST: + case XED_IFORMFL_VPERM2I128_LAST: + case XED_IFORMFL_VPERMB_FIRST: + case XED_IFORMFL_VPERMB_LAST: + case XED_IFORMFL_VPERMD_FIRST: + case XED_IFORMFL_VPERMD_LAST: + case XED_IFORMFL_VPERMI2B_FIRST: + case XED_IFORMFL_VPERMI2B_LAST: + case XED_IFORMFL_VPERMI2D_FIRST: + case XED_IFORMFL_VPERMI2D_LAST: + case XED_IFORMFL_VPERMI2PD_FIRST: + case XED_IFORMFL_VPERMI2PD_LAST: + case XED_IFORMFL_VPERMI2PS_FIRST: + case XED_IFORMFL_VPERMI2PS_LAST: + case XED_IFORMFL_VPERMI2Q_FIRST: + case XED_IFORMFL_VPERMI2Q_LAST: + case XED_IFORMFL_VPERMI2W_FIRST: + case XED_IFORMFL_VPERMI2W_LAST: + case XED_IFORMFL_VPERMIL2PD_FIRST: + case XED_IFORMFL_VPERMIL2PD_LAST: + case XED_IFORMFL_VPERMIL2PS_FIRST: + case XED_IFORMFL_VPERMIL2PS_LAST: + case XED_IFORMFL_VPERMILPD_FIRST: + case XED_IFORMFL_VPERMILPD_LAST: + case XED_IFORMFL_VPERMILPS_FIRST: + case XED_IFORMFL_VPERMILPS_LAST: + case XED_IFORMFL_VPERMPD_FIRST: + case XED_IFORMFL_VPERMPD_LAST: + case XED_IFORMFL_VPERMPS_FIRST: + case XED_IFORMFL_VPERMPS_LAST: + case XED_IFORMFL_VPERMQ_FIRST: + case XED_IFORMFL_VPERMQ_LAST: + case XED_IFORMFL_VPERMT2B_FIRST: + case XED_IFORMFL_VPERMT2B_LAST: + case XED_IFORMFL_VPERMT2D_FIRST: + case XED_IFORMFL_VPERMT2D_LAST: + case XED_IFORMFL_VPERMT2PD_FIRST: + case XED_IFORMFL_VPERMT2PD_LAST: + case XED_IFORMFL_VPERMT2PS_FIRST: + case XED_IFORMFL_VPERMT2PS_LAST: + case XED_IFORMFL_VPERMT2Q_FIRST: + case XED_IFORMFL_VPERMT2Q_LAST: + case XED_IFORMFL_VPERMT2W_FIRST: + case XED_IFORMFL_VPERMT2W_LAST: + case XED_IFORMFL_VPERMW_FIRST: + case XED_IFORMFL_VPERMW_LAST: + case XED_IFORMFL_VPEXPANDB_FIRST: + case XED_IFORMFL_VPEXPANDB_LAST: + case XED_IFORMFL_VPEXPANDD_FIRST: + case XED_IFORMFL_VPEXPANDD_LAST: + case XED_IFORMFL_VPEXPANDQ_FIRST: + case XED_IFORMFL_VPEXPANDQ_LAST: + case XED_IFORMFL_VPEXPANDW_FIRST: + case XED_IFORMFL_VPEXPANDW_LAST: + case XED_IFORMFL_VPEXTRB_FIRST: + case XED_IFORMFL_VPEXTRB_LAST: + case XED_IFORMFL_VPEXTRD_FIRST: + case XED_IFORMFL_VPEXTRD_LAST: + case XED_IFORMFL_VPEXTRQ_FIRST: + case XED_IFORMFL_VPEXTRQ_LAST: + case XED_IFORMFL_VPEXTRW_FIRST: + case XED_IFORMFL_VPEXTRW_LAST: + case XED_IFORMFL_VPEXTRW_C5_FIRST: + case XED_IFORMFL_VPEXTRW_C5_LAST: + case XED_IFORMFL_VPGATHERDD_FIRST: + case XED_IFORMFL_VPGATHERDD_LAST: + case XED_IFORMFL_VPGATHERDQ_FIRST: + case XED_IFORMFL_VPGATHERDQ_LAST: + case XED_IFORMFL_VPGATHERQD_FIRST: + case XED_IFORMFL_VPGATHERQD_LAST: + case XED_IFORMFL_VPGATHERQQ_FIRST: + case XED_IFORMFL_VPGATHERQQ_LAST: + case XED_IFORMFL_VPHADDBD_FIRST: + case XED_IFORMFL_VPHADDBD_LAST: + case XED_IFORMFL_VPHADDBQ_FIRST: + case XED_IFORMFL_VPHADDBQ_LAST: + case XED_IFORMFL_VPHADDBW_FIRST: + case XED_IFORMFL_VPHADDBW_LAST: + case XED_IFORMFL_VPHADDD_FIRST: + case XED_IFORMFL_VPHADDD_LAST: + case XED_IFORMFL_VPHADDDQ_FIRST: + case XED_IFORMFL_VPHADDDQ_LAST: + case XED_IFORMFL_VPHADDSW_FIRST: + case XED_IFORMFL_VPHADDSW_LAST: + case XED_IFORMFL_VPHADDUBD_FIRST: + case XED_IFORMFL_VPHADDUBD_LAST: + case XED_IFORMFL_VPHADDUBQ_FIRST: + case XED_IFORMFL_VPHADDUBQ_LAST: + case XED_IFORMFL_VPHADDUBW_FIRST: + case XED_IFORMFL_VPHADDUBW_LAST: + case XED_IFORMFL_VPHADDUDQ_FIRST: + case XED_IFORMFL_VPHADDUDQ_LAST: + case XED_IFORMFL_VPHADDUWD_FIRST: + case XED_IFORMFL_VPHADDUWD_LAST: + case XED_IFORMFL_VPHADDUWQ_FIRST: + case XED_IFORMFL_VPHADDUWQ_LAST: + case XED_IFORMFL_VPHADDW_FIRST: + case XED_IFORMFL_VPHADDW_LAST: + case XED_IFORMFL_VPHADDWD_FIRST: + case XED_IFORMFL_VPHADDWD_LAST: + case XED_IFORMFL_VPHADDWQ_FIRST: + case XED_IFORMFL_VPHADDWQ_LAST: + case XED_IFORMFL_VPHMINPOSUW_FIRST: + case XED_IFORMFL_VPHMINPOSUW_LAST: + case XED_IFORMFL_VPHSUBBW_FIRST: + case XED_IFORMFL_VPHSUBBW_LAST: + case XED_IFORMFL_VPHSUBD_FIRST: + case XED_IFORMFL_VPHSUBD_LAST: + case XED_IFORMFL_VPHSUBDQ_FIRST: + case XED_IFORMFL_VPHSUBDQ_LAST: + case XED_IFORMFL_VPHSUBSW_FIRST: + case XED_IFORMFL_VPHSUBSW_LAST: + case XED_IFORMFL_VPHSUBW_FIRST: + case XED_IFORMFL_VPHSUBW_LAST: + case XED_IFORMFL_VPHSUBWD_FIRST: + case XED_IFORMFL_VPHSUBWD_LAST: + case XED_IFORMFL_VPINSRB_FIRST: + case XED_IFORMFL_VPINSRB_LAST: + case XED_IFORMFL_VPINSRD_FIRST: + case XED_IFORMFL_VPINSRD_LAST: + case XED_IFORMFL_VPINSRQ_FIRST: + case XED_IFORMFL_VPINSRQ_LAST: + case XED_IFORMFL_VPINSRW_FIRST: + case XED_IFORMFL_VPINSRW_LAST: + case XED_IFORMFL_VPLZCNTD_FIRST: + case XED_IFORMFL_VPLZCNTD_LAST: + case XED_IFORMFL_VPLZCNTQ_FIRST: + case XED_IFORMFL_VPLZCNTQ_LAST: + case XED_IFORMFL_VPMACSDD_FIRST: + case XED_IFORMFL_VPMACSDD_LAST: + case XED_IFORMFL_VPMACSDQH_FIRST: + case XED_IFORMFL_VPMACSDQH_LAST: + case XED_IFORMFL_VPMACSDQL_FIRST: + case XED_IFORMFL_VPMACSDQL_LAST: + case XED_IFORMFL_VPMACSSDD_FIRST: + case XED_IFORMFL_VPMACSSDD_LAST: + case XED_IFORMFL_VPMACSSDQH_FIRST: + case XED_IFORMFL_VPMACSSDQH_LAST: + case XED_IFORMFL_VPMACSSDQL_FIRST: + case XED_IFORMFL_VPMACSSDQL_LAST: + case XED_IFORMFL_VPMACSSWD_FIRST: + case XED_IFORMFL_VPMACSSWD_LAST: + case XED_IFORMFL_VPMACSSWW_FIRST: + case XED_IFORMFL_VPMACSSWW_LAST: + case XED_IFORMFL_VPMACSWD_FIRST: + case XED_IFORMFL_VPMACSWD_LAST: + case XED_IFORMFL_VPMACSWW_FIRST: + case XED_IFORMFL_VPMACSWW_LAST: + case XED_IFORMFL_VPMADCSSWD_FIRST: + case XED_IFORMFL_VPMADCSSWD_LAST: + case XED_IFORMFL_VPMADCSWD_FIRST: + case XED_IFORMFL_VPMADCSWD_LAST: + case XED_IFORMFL_VPMADD52HUQ_FIRST: + case XED_IFORMFL_VPMADD52HUQ_LAST: + case XED_IFORMFL_VPMADD52LUQ_FIRST: + case XED_IFORMFL_VPMADD52LUQ_LAST: + case XED_IFORMFL_VPMADDUBSW_FIRST: + case XED_IFORMFL_VPMADDUBSW_LAST: + case XED_IFORMFL_VPMADDWD_FIRST: + case XED_IFORMFL_VPMADDWD_LAST: + case XED_IFORMFL_VPMASKMOVD_FIRST: + case XED_IFORMFL_VPMASKMOVD_LAST: + case XED_IFORMFL_VPMASKMOVQ_FIRST: + case XED_IFORMFL_VPMASKMOVQ_LAST: + case XED_IFORMFL_VPMAXSB_FIRST: + case XED_IFORMFL_VPMAXSB_LAST: + case XED_IFORMFL_VPMAXSD_FIRST: + case XED_IFORMFL_VPMAXSD_LAST: + case XED_IFORMFL_VPMAXSQ_FIRST: + case XED_IFORMFL_VPMAXSQ_LAST: + case XED_IFORMFL_VPMAXSW_FIRST: + case XED_IFORMFL_VPMAXSW_LAST: + case XED_IFORMFL_VPMAXUB_FIRST: + case XED_IFORMFL_VPMAXUB_LAST: + case XED_IFORMFL_VPMAXUD_FIRST: + case XED_IFORMFL_VPMAXUD_LAST: + case XED_IFORMFL_VPMAXUQ_FIRST: + case XED_IFORMFL_VPMAXUQ_LAST: + case XED_IFORMFL_VPMAXUW_FIRST: + case XED_IFORMFL_VPMAXUW_LAST: + case XED_IFORMFL_VPMINSB_FIRST: + case XED_IFORMFL_VPMINSB_LAST: + case XED_IFORMFL_VPMINSD_FIRST: + case XED_IFORMFL_VPMINSD_LAST: + case XED_IFORMFL_VPMINSQ_FIRST: + case XED_IFORMFL_VPMINSQ_LAST: + case XED_IFORMFL_VPMINSW_FIRST: + case XED_IFORMFL_VPMINSW_LAST: + case XED_IFORMFL_VPMINUB_FIRST: + case XED_IFORMFL_VPMINUB_LAST: + case XED_IFORMFL_VPMINUD_FIRST: + case XED_IFORMFL_VPMINUD_LAST: + case XED_IFORMFL_VPMINUQ_FIRST: + case XED_IFORMFL_VPMINUQ_LAST: + case XED_IFORMFL_VPMINUW_FIRST: + case XED_IFORMFL_VPMINUW_LAST: + case XED_IFORMFL_VPMOVB2M_FIRST: + case XED_IFORMFL_VPMOVB2M_LAST: + case XED_IFORMFL_VPMOVD2M_FIRST: + case XED_IFORMFL_VPMOVD2M_LAST: + case XED_IFORMFL_VPMOVDB_FIRST: + case XED_IFORMFL_VPMOVDB_LAST: + case XED_IFORMFL_VPMOVDW_FIRST: + case XED_IFORMFL_VPMOVDW_LAST: + case XED_IFORMFL_VPMOVM2B_FIRST: + case XED_IFORMFL_VPMOVM2B_LAST: + case XED_IFORMFL_VPMOVM2D_FIRST: + case XED_IFORMFL_VPMOVM2D_LAST: + case XED_IFORMFL_VPMOVM2Q_FIRST: + case XED_IFORMFL_VPMOVM2Q_LAST: + case XED_IFORMFL_VPMOVM2W_FIRST: + case XED_IFORMFL_VPMOVM2W_LAST: + case XED_IFORMFL_VPMOVMSKB_FIRST: + case XED_IFORMFL_VPMOVMSKB_LAST: + case XED_IFORMFL_VPMOVQ2M_FIRST: + case XED_IFORMFL_VPMOVQ2M_LAST: + case XED_IFORMFL_VPMOVQB_FIRST: + case XED_IFORMFL_VPMOVQB_LAST: + case XED_IFORMFL_VPMOVQD_FIRST: + case XED_IFORMFL_VPMOVQD_LAST: + case XED_IFORMFL_VPMOVQW_FIRST: + case XED_IFORMFL_VPMOVQW_LAST: + case XED_IFORMFL_VPMOVSDB_FIRST: + case XED_IFORMFL_VPMOVSDB_LAST: + case XED_IFORMFL_VPMOVSDW_FIRST: + case XED_IFORMFL_VPMOVSDW_LAST: + case XED_IFORMFL_VPMOVSQB_FIRST: + case XED_IFORMFL_VPMOVSQB_LAST: + case XED_IFORMFL_VPMOVSQD_FIRST: + case XED_IFORMFL_VPMOVSQD_LAST: + case XED_IFORMFL_VPMOVSQW_FIRST: + case XED_IFORMFL_VPMOVSQW_LAST: + case XED_IFORMFL_VPMOVSWB_FIRST: + case XED_IFORMFL_VPMOVSWB_LAST: + case XED_IFORMFL_VPMOVSXBD_FIRST: + case XED_IFORMFL_VPMOVSXBD_LAST: + case XED_IFORMFL_VPMOVSXBQ_FIRST: + case XED_IFORMFL_VPMOVSXBQ_LAST: + case XED_IFORMFL_VPMOVSXBW_FIRST: + case XED_IFORMFL_VPMOVSXBW_LAST: + case XED_IFORMFL_VPMOVSXDQ_FIRST: + case XED_IFORMFL_VPMOVSXDQ_LAST: + case XED_IFORMFL_VPMOVSXWD_FIRST: + case XED_IFORMFL_VPMOVSXWD_LAST: + case XED_IFORMFL_VPMOVSXWQ_FIRST: + case XED_IFORMFL_VPMOVSXWQ_LAST: + case XED_IFORMFL_VPMOVUSDB_FIRST: + case XED_IFORMFL_VPMOVUSDB_LAST: + case XED_IFORMFL_VPMOVUSDW_FIRST: + case XED_IFORMFL_VPMOVUSDW_LAST: + case XED_IFORMFL_VPMOVUSQB_FIRST: + case XED_IFORMFL_VPMOVUSQB_LAST: + case XED_IFORMFL_VPMOVUSQD_FIRST: + case XED_IFORMFL_VPMOVUSQD_LAST: + case XED_IFORMFL_VPMOVUSQW_FIRST: + case XED_IFORMFL_VPMOVUSQW_LAST: + case XED_IFORMFL_VPMOVUSWB_FIRST: + case XED_IFORMFL_VPMOVUSWB_LAST: + case XED_IFORMFL_VPMOVW2M_FIRST: + case XED_IFORMFL_VPMOVW2M_LAST: + case XED_IFORMFL_VPMOVWB_FIRST: + case XED_IFORMFL_VPMOVWB_LAST: + case XED_IFORMFL_VPMOVZXBD_FIRST: + case XED_IFORMFL_VPMOVZXBD_LAST: + case XED_IFORMFL_VPMOVZXBQ_FIRST: + case XED_IFORMFL_VPMOVZXBQ_LAST: + case XED_IFORMFL_VPMOVZXBW_FIRST: + case XED_IFORMFL_VPMOVZXBW_LAST: + case XED_IFORMFL_VPMOVZXDQ_FIRST: + case XED_IFORMFL_VPMOVZXDQ_LAST: + case XED_IFORMFL_VPMOVZXWD_FIRST: + case XED_IFORMFL_VPMOVZXWD_LAST: + case XED_IFORMFL_VPMOVZXWQ_FIRST: + case XED_IFORMFL_VPMOVZXWQ_LAST: + case XED_IFORMFL_VPMULDQ_FIRST: + case XED_IFORMFL_VPMULDQ_LAST: + case XED_IFORMFL_VPMULHRSW_FIRST: + case XED_IFORMFL_VPMULHRSW_LAST: + case XED_IFORMFL_VPMULHUW_FIRST: + case XED_IFORMFL_VPMULHUW_LAST: + case XED_IFORMFL_VPMULHW_FIRST: + case XED_IFORMFL_VPMULHW_LAST: + case XED_IFORMFL_VPMULLD_FIRST: + case XED_IFORMFL_VPMULLD_LAST: + case XED_IFORMFL_VPMULLQ_FIRST: + case XED_IFORMFL_VPMULLQ_LAST: + case XED_IFORMFL_VPMULLW_FIRST: + case XED_IFORMFL_VPMULLW_LAST: + case XED_IFORMFL_VPMULTISHIFTQB_FIRST: + case XED_IFORMFL_VPMULTISHIFTQB_LAST: + case XED_IFORMFL_VPMULUDQ_FIRST: + case XED_IFORMFL_VPMULUDQ_LAST: + case XED_IFORMFL_VPOPCNTB_FIRST: + case XED_IFORMFL_VPOPCNTB_LAST: + case XED_IFORMFL_VPOPCNTD_FIRST: + case XED_IFORMFL_VPOPCNTD_LAST: + case XED_IFORMFL_VPOPCNTQ_FIRST: + case XED_IFORMFL_VPOPCNTQ_LAST: + case XED_IFORMFL_VPOPCNTW_FIRST: + case XED_IFORMFL_VPOPCNTW_LAST: + case XED_IFORMFL_VPOR_FIRST: + case XED_IFORMFL_VPOR_LAST: + case XED_IFORMFL_VPORD_FIRST: + case XED_IFORMFL_VPORD_LAST: + case XED_IFORMFL_VPORQ_FIRST: + case XED_IFORMFL_VPORQ_LAST: + case XED_IFORMFL_VPPERM_FIRST: + case XED_IFORMFL_VPPERM_LAST: + case XED_IFORMFL_VPROLD_FIRST: + case XED_IFORMFL_VPROLD_LAST: + case XED_IFORMFL_VPROLQ_FIRST: + case XED_IFORMFL_VPROLQ_LAST: + case XED_IFORMFL_VPROLVD_FIRST: + case XED_IFORMFL_VPROLVD_LAST: + case XED_IFORMFL_VPROLVQ_FIRST: + case XED_IFORMFL_VPROLVQ_LAST: + case XED_IFORMFL_VPRORD_FIRST: + case XED_IFORMFL_VPRORD_LAST: + case XED_IFORMFL_VPRORQ_FIRST: + case XED_IFORMFL_VPRORQ_LAST: + case XED_IFORMFL_VPRORVD_FIRST: + case XED_IFORMFL_VPRORVD_LAST: + case XED_IFORMFL_VPRORVQ_FIRST: + case XED_IFORMFL_VPRORVQ_LAST: + case XED_IFORMFL_VPROTB_FIRST: + case XED_IFORMFL_VPROTB_LAST: + case XED_IFORMFL_VPROTD_FIRST: + case XED_IFORMFL_VPROTD_LAST: + case XED_IFORMFL_VPROTQ_FIRST: + case XED_IFORMFL_VPROTQ_LAST: + case XED_IFORMFL_VPROTW_FIRST: + case XED_IFORMFL_VPROTW_LAST: + case XED_IFORMFL_VPSADBW_FIRST: + case XED_IFORMFL_VPSADBW_LAST: + case XED_IFORMFL_VPSCATTERDD_FIRST: + case XED_IFORMFL_VPSCATTERDD_LAST: + case XED_IFORMFL_VPSCATTERDQ_FIRST: + case XED_IFORMFL_VPSCATTERDQ_LAST: + case XED_IFORMFL_VPSCATTERQD_FIRST: + case XED_IFORMFL_VPSCATTERQD_LAST: + case XED_IFORMFL_VPSCATTERQQ_FIRST: + case XED_IFORMFL_VPSCATTERQQ_LAST: + case XED_IFORMFL_VPSHAB_FIRST: + case XED_IFORMFL_VPSHAB_LAST: + case XED_IFORMFL_VPSHAD_FIRST: + case XED_IFORMFL_VPSHAD_LAST: + case XED_IFORMFL_VPSHAQ_FIRST: + case XED_IFORMFL_VPSHAQ_LAST: + case XED_IFORMFL_VPSHAW_FIRST: + case XED_IFORMFL_VPSHAW_LAST: + case XED_IFORMFL_VPSHLB_FIRST: + case XED_IFORMFL_VPSHLB_LAST: + case XED_IFORMFL_VPSHLD_FIRST: + case XED_IFORMFL_VPSHLD_LAST: + case XED_IFORMFL_VPSHLDD_FIRST: + case XED_IFORMFL_VPSHLDD_LAST: + case XED_IFORMFL_VPSHLDQ_FIRST: + case XED_IFORMFL_VPSHLDQ_LAST: + case XED_IFORMFL_VPSHLDVD_FIRST: + case XED_IFORMFL_VPSHLDVD_LAST: + case XED_IFORMFL_VPSHLDVQ_FIRST: + case XED_IFORMFL_VPSHLDVQ_LAST: + case XED_IFORMFL_VPSHLDVW_FIRST: + case XED_IFORMFL_VPSHLDVW_LAST: + case XED_IFORMFL_VPSHLDW_FIRST: + case XED_IFORMFL_VPSHLDW_LAST: + case XED_IFORMFL_VPSHLQ_FIRST: + case XED_IFORMFL_VPSHLQ_LAST: + case XED_IFORMFL_VPSHLW_FIRST: + case XED_IFORMFL_VPSHLW_LAST: + case XED_IFORMFL_VPSHRDD_FIRST: + case XED_IFORMFL_VPSHRDD_LAST: + case XED_IFORMFL_VPSHRDQ_FIRST: + case XED_IFORMFL_VPSHRDQ_LAST: + case XED_IFORMFL_VPSHRDVD_FIRST: + case XED_IFORMFL_VPSHRDVD_LAST: + case XED_IFORMFL_VPSHRDVQ_FIRST: + case XED_IFORMFL_VPSHRDVQ_LAST: + case XED_IFORMFL_VPSHRDVW_FIRST: + case XED_IFORMFL_VPSHRDVW_LAST: + case XED_IFORMFL_VPSHRDW_FIRST: + case XED_IFORMFL_VPSHRDW_LAST: + case XED_IFORMFL_VPSHUFB_FIRST: + case XED_IFORMFL_VPSHUFB_LAST: + case XED_IFORMFL_VPSHUFBITQMB_FIRST: + case XED_IFORMFL_VPSHUFBITQMB_LAST: + case XED_IFORMFL_VPSHUFD_FIRST: + case XED_IFORMFL_VPSHUFD_LAST: + case XED_IFORMFL_VPSHUFHW_FIRST: + case XED_IFORMFL_VPSHUFHW_LAST: + case XED_IFORMFL_VPSHUFLW_FIRST: + case XED_IFORMFL_VPSHUFLW_LAST: + case XED_IFORMFL_VPSIGNB_FIRST: + case XED_IFORMFL_VPSIGNB_LAST: + case XED_IFORMFL_VPSIGND_FIRST: + case XED_IFORMFL_VPSIGND_LAST: + case XED_IFORMFL_VPSIGNW_FIRST: + case XED_IFORMFL_VPSIGNW_LAST: + case XED_IFORMFL_VPSLLD_FIRST: + case XED_IFORMFL_VPSLLD_LAST: + case XED_IFORMFL_VPSLLDQ_FIRST: + case XED_IFORMFL_VPSLLDQ_LAST: + case XED_IFORMFL_VPSLLQ_FIRST: + case XED_IFORMFL_VPSLLQ_LAST: + case XED_IFORMFL_VPSLLVD_FIRST: + case XED_IFORMFL_VPSLLVD_LAST: + case XED_IFORMFL_VPSLLVQ_FIRST: + case XED_IFORMFL_VPSLLVQ_LAST: + case XED_IFORMFL_VPSLLVW_FIRST: + case XED_IFORMFL_VPSLLVW_LAST: + case XED_IFORMFL_VPSLLW_FIRST: + case XED_IFORMFL_VPSLLW_LAST: + case XED_IFORMFL_VPSRAD_FIRST: + case XED_IFORMFL_VPSRAD_LAST: + case XED_IFORMFL_VPSRAQ_FIRST: + case XED_IFORMFL_VPSRAQ_LAST: + case XED_IFORMFL_VPSRAVD_FIRST: + case XED_IFORMFL_VPSRAVD_LAST: + case XED_IFORMFL_VPSRAVQ_FIRST: + case XED_IFORMFL_VPSRAVQ_LAST: + case XED_IFORMFL_VPSRAVW_FIRST: + case XED_IFORMFL_VPSRAVW_LAST: + case XED_IFORMFL_VPSRAW_FIRST: + case XED_IFORMFL_VPSRAW_LAST: + case XED_IFORMFL_VPSRLD_FIRST: + case XED_IFORMFL_VPSRLD_LAST: + case XED_IFORMFL_VPSRLDQ_FIRST: + case XED_IFORMFL_VPSRLDQ_LAST: + case XED_IFORMFL_VPSRLQ_FIRST: + case XED_IFORMFL_VPSRLQ_LAST: + case XED_IFORMFL_VPSRLVD_FIRST: + case XED_IFORMFL_VPSRLVD_LAST: + case XED_IFORMFL_VPSRLVQ_FIRST: + case XED_IFORMFL_VPSRLVQ_LAST: + case XED_IFORMFL_VPSRLVW_FIRST: + case XED_IFORMFL_VPSRLVW_LAST: + case XED_IFORMFL_VPSRLW_FIRST: + case XED_IFORMFL_VPSRLW_LAST: + case XED_IFORMFL_VPSUBB_FIRST: + case XED_IFORMFL_VPSUBB_LAST: + case XED_IFORMFL_VPSUBD_FIRST: + case XED_IFORMFL_VPSUBD_LAST: + case XED_IFORMFL_VPSUBQ_FIRST: + case XED_IFORMFL_VPSUBQ_LAST: + case XED_IFORMFL_VPSUBSB_FIRST: + case XED_IFORMFL_VPSUBSB_LAST: + case XED_IFORMFL_VPSUBSW_FIRST: + case XED_IFORMFL_VPSUBSW_LAST: + case XED_IFORMFL_VPSUBUSB_FIRST: + case XED_IFORMFL_VPSUBUSB_LAST: + case XED_IFORMFL_VPSUBUSW_FIRST: + case XED_IFORMFL_VPSUBUSW_LAST: + case XED_IFORMFL_VPSUBW_FIRST: + case XED_IFORMFL_VPSUBW_LAST: + case XED_IFORMFL_VPTERNLOGD_FIRST: + case XED_IFORMFL_VPTERNLOGD_LAST: + case XED_IFORMFL_VPTERNLOGQ_FIRST: + case XED_IFORMFL_VPTERNLOGQ_LAST: + case XED_IFORMFL_VPTEST_FIRST: + case XED_IFORMFL_VPTEST_LAST: + case XED_IFORMFL_VPTESTMB_FIRST: + case XED_IFORMFL_VPTESTMB_LAST: + case XED_IFORMFL_VPTESTMD_FIRST: + case XED_IFORMFL_VPTESTMD_LAST: + case XED_IFORMFL_VPTESTMQ_FIRST: + case XED_IFORMFL_VPTESTMQ_LAST: + case XED_IFORMFL_VPTESTMW_FIRST: + case XED_IFORMFL_VPTESTMW_LAST: + case XED_IFORMFL_VPTESTNMB_FIRST: + case XED_IFORMFL_VPTESTNMB_LAST: + case XED_IFORMFL_VPTESTNMD_FIRST: + case XED_IFORMFL_VPTESTNMD_LAST: + case XED_IFORMFL_VPTESTNMQ_FIRST: + case XED_IFORMFL_VPTESTNMQ_LAST: + case XED_IFORMFL_VPTESTNMW_FIRST: + case XED_IFORMFL_VPTESTNMW_LAST: + case XED_IFORMFL_VPUNPCKHBW_FIRST: + case XED_IFORMFL_VPUNPCKHBW_LAST: + case XED_IFORMFL_VPUNPCKHDQ_FIRST: + case XED_IFORMFL_VPUNPCKHDQ_LAST: + case XED_IFORMFL_VPUNPCKHQDQ_FIRST: + case XED_IFORMFL_VPUNPCKHQDQ_LAST: + case XED_IFORMFL_VPUNPCKHWD_FIRST: + case XED_IFORMFL_VPUNPCKHWD_LAST: + case XED_IFORMFL_VPUNPCKLBW_FIRST: + case XED_IFORMFL_VPUNPCKLBW_LAST: + case XED_IFORMFL_VPUNPCKLDQ_FIRST: + case XED_IFORMFL_VPUNPCKLDQ_LAST: + case XED_IFORMFL_VPUNPCKLQDQ_FIRST: + case XED_IFORMFL_VPUNPCKLQDQ_LAST: + case XED_IFORMFL_VPUNPCKLWD_FIRST: + case XED_IFORMFL_VPUNPCKLWD_LAST: + case XED_IFORMFL_VPXOR_FIRST: + case XED_IFORMFL_VPXOR_LAST: + case XED_IFORMFL_VPXORD_FIRST: + case XED_IFORMFL_VPXORD_LAST: + case XED_IFORMFL_VPXORQ_FIRST: + case XED_IFORMFL_VPXORQ_LAST: + case XED_IFORMFL_VRANGEPD_FIRST: + case XED_IFORMFL_VRANGEPD_LAST: + case XED_IFORMFL_VRANGEPS_FIRST: + case XED_IFORMFL_VRANGEPS_LAST: + case XED_IFORMFL_VRANGESD_FIRST: + case XED_IFORMFL_VRANGESD_LAST: + case XED_IFORMFL_VRANGESS_FIRST: + case XED_IFORMFL_VRANGESS_LAST: + case XED_IFORMFL_VRCP14PD_FIRST: + case XED_IFORMFL_VRCP14PD_LAST: + case XED_IFORMFL_VRCP14PS_FIRST: + case XED_IFORMFL_VRCP14PS_LAST: + case XED_IFORMFL_VRCP14SD_FIRST: + case XED_IFORMFL_VRCP14SD_LAST: + case XED_IFORMFL_VRCP14SS_FIRST: + case XED_IFORMFL_VRCP14SS_LAST: + case XED_IFORMFL_VRCP28PD_FIRST: + case XED_IFORMFL_VRCP28PD_LAST: + case XED_IFORMFL_VRCP28PS_FIRST: + case XED_IFORMFL_VRCP28PS_LAST: + case XED_IFORMFL_VRCP28SD_FIRST: + case XED_IFORMFL_VRCP28SD_LAST: + case XED_IFORMFL_VRCP28SS_FIRST: + case XED_IFORMFL_VRCP28SS_LAST: + case XED_IFORMFL_VRCPPH_FIRST: + case XED_IFORMFL_VRCPPH_LAST: + case XED_IFORMFL_VRCPPS_FIRST: + case XED_IFORMFL_VRCPPS_LAST: + case XED_IFORMFL_VRCPSH_FIRST: + case XED_IFORMFL_VRCPSH_LAST: + case XED_IFORMFL_VRCPSS_FIRST: + case XED_IFORMFL_VRCPSS_LAST: + case XED_IFORMFL_VREDUCEPD_FIRST: + case XED_IFORMFL_VREDUCEPD_LAST: + case XED_IFORMFL_VREDUCEPH_FIRST: + case XED_IFORMFL_VREDUCEPH_LAST: + case XED_IFORMFL_VREDUCEPS_FIRST: + case XED_IFORMFL_VREDUCEPS_LAST: + case XED_IFORMFL_VREDUCESD_FIRST: + case XED_IFORMFL_VREDUCESD_LAST: + case XED_IFORMFL_VREDUCESH_FIRST: + case XED_IFORMFL_VREDUCESH_LAST: + case XED_IFORMFL_VREDUCESS_FIRST: + case XED_IFORMFL_VREDUCESS_LAST: + case XED_IFORMFL_VRNDSCALEPD_FIRST: + case XED_IFORMFL_VRNDSCALEPD_LAST: + case XED_IFORMFL_VRNDSCALEPH_FIRST: + case XED_IFORMFL_VRNDSCALEPH_LAST: + case XED_IFORMFL_VRNDSCALEPS_FIRST: + case XED_IFORMFL_VRNDSCALEPS_LAST: + case XED_IFORMFL_VRNDSCALESD_FIRST: + case XED_IFORMFL_VRNDSCALESD_LAST: + case XED_IFORMFL_VRNDSCALESH_FIRST: + case XED_IFORMFL_VRNDSCALESH_LAST: + case XED_IFORMFL_VRNDSCALESS_FIRST: + case XED_IFORMFL_VRNDSCALESS_LAST: + case XED_IFORMFL_VROUNDPD_FIRST: + case XED_IFORMFL_VROUNDPD_LAST: + case XED_IFORMFL_VROUNDPS_FIRST: + case XED_IFORMFL_VROUNDPS_LAST: + case XED_IFORMFL_VROUNDSD_FIRST: + case XED_IFORMFL_VROUNDSD_LAST: + case XED_IFORMFL_VROUNDSS_FIRST: + case XED_IFORMFL_VROUNDSS_LAST: + case XED_IFORMFL_VRSQRT14PD_FIRST: + case XED_IFORMFL_VRSQRT14PD_LAST: + case XED_IFORMFL_VRSQRT14PS_FIRST: + case XED_IFORMFL_VRSQRT14PS_LAST: + case XED_IFORMFL_VRSQRT14SD_FIRST: + case XED_IFORMFL_VRSQRT14SD_LAST: + case XED_IFORMFL_VRSQRT14SS_FIRST: + case XED_IFORMFL_VRSQRT14SS_LAST: + case XED_IFORMFL_VRSQRT28PD_FIRST: + case XED_IFORMFL_VRSQRT28PD_LAST: + case XED_IFORMFL_VRSQRT28PS_FIRST: + case XED_IFORMFL_VRSQRT28PS_LAST: + case XED_IFORMFL_VRSQRT28SD_FIRST: + case XED_IFORMFL_VRSQRT28SD_LAST: + case XED_IFORMFL_VRSQRT28SS_FIRST: + case XED_IFORMFL_VRSQRT28SS_LAST: + case XED_IFORMFL_VRSQRTPH_FIRST: + case XED_IFORMFL_VRSQRTPH_LAST: + case XED_IFORMFL_VRSQRTPS_FIRST: + case XED_IFORMFL_VRSQRTPS_LAST: + case XED_IFORMFL_VRSQRTSH_FIRST: + case XED_IFORMFL_VRSQRTSH_LAST: + case XED_IFORMFL_VRSQRTSS_FIRST: + case XED_IFORMFL_VRSQRTSS_LAST: + case XED_IFORMFL_VSCALEFPD_FIRST: + case XED_IFORMFL_VSCALEFPD_LAST: + case XED_IFORMFL_VSCALEFPH_FIRST: + case XED_IFORMFL_VSCALEFPH_LAST: + case XED_IFORMFL_VSCALEFPS_FIRST: + case XED_IFORMFL_VSCALEFPS_LAST: + case XED_IFORMFL_VSCALEFSD_FIRST: + case XED_IFORMFL_VSCALEFSD_LAST: + case XED_IFORMFL_VSCALEFSH_FIRST: + case XED_IFORMFL_VSCALEFSH_LAST: + case XED_IFORMFL_VSCALEFSS_FIRST: + case XED_IFORMFL_VSCALEFSS_LAST: + case XED_IFORMFL_VSCATTERDPD_FIRST: + case XED_IFORMFL_VSCATTERDPD_LAST: + case XED_IFORMFL_VSCATTERDPS_FIRST: + case XED_IFORMFL_VSCATTERDPS_LAST: + case XED_IFORMFL_VSCATTERPF0DPD_FIRST: + case XED_IFORMFL_VSCATTERPF0DPD_LAST: + case XED_IFORMFL_VSCATTERPF0DPS_FIRST: + case XED_IFORMFL_VSCATTERPF0DPS_LAST: + case XED_IFORMFL_VSCATTERPF0QPD_FIRST: + case XED_IFORMFL_VSCATTERPF0QPD_LAST: + case XED_IFORMFL_VSCATTERPF0QPS_FIRST: + case XED_IFORMFL_VSCATTERPF0QPS_LAST: + case XED_IFORMFL_VSCATTERPF1DPD_FIRST: + case XED_IFORMFL_VSCATTERPF1DPD_LAST: + case XED_IFORMFL_VSCATTERPF1DPS_FIRST: + case XED_IFORMFL_VSCATTERPF1DPS_LAST: + case XED_IFORMFL_VSCATTERPF1QPD_FIRST: + case XED_IFORMFL_VSCATTERPF1QPD_LAST: + case XED_IFORMFL_VSCATTERPF1QPS_FIRST: + case XED_IFORMFL_VSCATTERPF1QPS_LAST: + case XED_IFORMFL_VSCATTERQPD_FIRST: + case XED_IFORMFL_VSCATTERQPD_LAST: + case XED_IFORMFL_VSCATTERQPS_FIRST: + case XED_IFORMFL_VSCATTERQPS_LAST: + case XED_IFORMFL_VSHUFF32X4_FIRST: + case XED_IFORMFL_VSHUFF32X4_LAST: + case XED_IFORMFL_VSHUFF64X2_FIRST: + case XED_IFORMFL_VSHUFF64X2_LAST: + case XED_IFORMFL_VSHUFI32X4_FIRST: + case XED_IFORMFL_VSHUFI32X4_LAST: + case XED_IFORMFL_VSHUFI64X2_FIRST: + case XED_IFORMFL_VSHUFI64X2_LAST: + case XED_IFORMFL_VSHUFPD_FIRST: + case XED_IFORMFL_VSHUFPD_LAST: + case XED_IFORMFL_VSHUFPS_FIRST: + case XED_IFORMFL_VSHUFPS_LAST: + case XED_IFORMFL_VSQRTPD_FIRST: + case XED_IFORMFL_VSQRTPD_LAST: + case XED_IFORMFL_VSQRTPH_FIRST: + case XED_IFORMFL_VSQRTPH_LAST: + case XED_IFORMFL_VSQRTPS_FIRST: + case XED_IFORMFL_VSQRTPS_LAST: + case XED_IFORMFL_VSQRTSD_FIRST: + case XED_IFORMFL_VSQRTSD_LAST: + case XED_IFORMFL_VSQRTSH_FIRST: + case XED_IFORMFL_VSQRTSH_LAST: + case XED_IFORMFL_VSQRTSS_FIRST: + case XED_IFORMFL_VSQRTSS_LAST: + case XED_IFORMFL_VSTMXCSR_FIRST: + case XED_IFORMFL_VSTMXCSR_LAST: + case XED_IFORMFL_VSUBPD_FIRST: + case XED_IFORMFL_VSUBPD_LAST: + case XED_IFORMFL_VSUBPH_FIRST: + case XED_IFORMFL_VSUBPH_LAST: + case XED_IFORMFL_VSUBPS_FIRST: + case XED_IFORMFL_VSUBPS_LAST: + case XED_IFORMFL_VSUBSD_FIRST: + case XED_IFORMFL_VSUBSD_LAST: + case XED_IFORMFL_VSUBSH_FIRST: + case XED_IFORMFL_VSUBSH_LAST: + case XED_IFORMFL_VSUBSS_FIRST: + case XED_IFORMFL_VSUBSS_LAST: + case XED_IFORMFL_VTESTPD_FIRST: + case XED_IFORMFL_VTESTPD_LAST: + case XED_IFORMFL_VTESTPS_FIRST: + case XED_IFORMFL_VTESTPS_LAST: + case XED_IFORMFL_VUCOMISD_FIRST: + case XED_IFORMFL_VUCOMISD_LAST: + case XED_IFORMFL_VUCOMISH_FIRST: + case XED_IFORMFL_VUCOMISH_LAST: + case XED_IFORMFL_VUCOMISS_FIRST: + case XED_IFORMFL_VUCOMISS_LAST: + case XED_IFORMFL_VUNPCKHPD_FIRST: + case XED_IFORMFL_VUNPCKHPD_LAST: + case XED_IFORMFL_VUNPCKHPS_FIRST: + case XED_IFORMFL_VUNPCKHPS_LAST: + case XED_IFORMFL_VUNPCKLPD_FIRST: + case XED_IFORMFL_VUNPCKLPD_LAST: + case XED_IFORMFL_VUNPCKLPS_FIRST: + case XED_IFORMFL_VUNPCKLPS_LAST: + case XED_IFORMFL_VXORPD_FIRST: + case XED_IFORMFL_VXORPD_LAST: + case XED_IFORMFL_VXORPS_FIRST: + case XED_IFORMFL_VXORPS_LAST: + case XED_IFORMFL_VZEROALL_FIRST: + case XED_IFORMFL_VZEROALL_LAST: + case XED_IFORMFL_VZEROUPPER_FIRST: + case XED_IFORMFL_VZEROUPPER_LAST: + case XED_IFORMFL_WBINVD_FIRST: + case XED_IFORMFL_WBINVD_LAST: + case XED_IFORMFL_WBNOINVD_FIRST: + case XED_IFORMFL_WBNOINVD_LAST: + case XED_IFORMFL_WRFSBASE_FIRST: + case XED_IFORMFL_WRFSBASE_LAST: + case XED_IFORMFL_WRGSBASE_FIRST: + case XED_IFORMFL_WRGSBASE_LAST: + case XED_IFORMFL_WRMSR_FIRST: + case XED_IFORMFL_WRMSR_LAST: + case XED_IFORMFL_WRPKRU_FIRST: + case XED_IFORMFL_WRPKRU_LAST: + case XED_IFORMFL_WRSSD_FIRST: + case XED_IFORMFL_WRSSD_LAST: + case XED_IFORMFL_WRSSQ_FIRST: + case XED_IFORMFL_WRSSQ_LAST: + case XED_IFORMFL_WRUSSD_FIRST: + case XED_IFORMFL_WRUSSD_LAST: + case XED_IFORMFL_WRUSSQ_FIRST: + case XED_IFORMFL_WRUSSQ_LAST: + case XED_IFORMFL_XABORT_FIRST: + case XED_IFORMFL_XABORT_LAST: + case XED_IFORMFL_XADD_FIRST: + case XED_IFORMFL_XADD_LAST: + case XED_IFORMFL_XADD_LOCK_FIRST: + case XED_IFORMFL_XADD_LOCK_LAST: + case XED_IFORMFL_XBEGIN_FIRST: + case XED_IFORMFL_XBEGIN_LAST: + case XED_IFORMFL_XCHG_FIRST: + case XED_IFORMFL_XCHG_LAST: + case XED_IFORMFL_XEND_FIRST: + case XED_IFORMFL_XEND_LAST: + case XED_IFORMFL_XGETBV_FIRST: + case XED_IFORMFL_XGETBV_LAST: + case XED_IFORMFL_XLAT_FIRST: + case XED_IFORMFL_XLAT_LAST: + case XED_IFORMFL_XOR_FIRST: + case XED_IFORMFL_XOR_LAST: + case XED_IFORMFL_XORPD_FIRST: + case XED_IFORMFL_XORPD_LAST: + case XED_IFORMFL_XORPS_FIRST: + case XED_IFORMFL_XORPS_LAST: + case XED_IFORMFL_XOR_LOCK_FIRST: + case XED_IFORMFL_XOR_LOCK_LAST: + case XED_IFORMFL_XRESLDTRK_FIRST: + case XED_IFORMFL_XRESLDTRK_LAST: + case XED_IFORMFL_XRSTOR_FIRST: + case XED_IFORMFL_XRSTOR_LAST: + case XED_IFORMFL_XRSTOR64_FIRST: + case XED_IFORMFL_XRSTOR64_LAST: + case XED_IFORMFL_XRSTORS_FIRST: + case XED_IFORMFL_XRSTORS_LAST: + case XED_IFORMFL_XRSTORS64_FIRST: + case XED_IFORMFL_XRSTORS64_LAST: + case XED_IFORMFL_XSAVE_FIRST: + case XED_IFORMFL_XSAVE_LAST: + case XED_IFORMFL_XSAVE64_FIRST: + case XED_IFORMFL_XSAVE64_LAST: + case XED_IFORMFL_XSAVEC_FIRST: + case XED_IFORMFL_XSAVEC_LAST: + case XED_IFORMFL_XSAVEC64_FIRST: + case XED_IFORMFL_XSAVEC64_LAST: + case XED_IFORMFL_XSAVEOPT_FIRST: + case XED_IFORMFL_XSAVEOPT_LAST: + case XED_IFORMFL_XSAVEOPT64_FIRST: + case XED_IFORMFL_XSAVEOPT64_LAST: + case XED_IFORMFL_XSAVES_FIRST: + case XED_IFORMFL_XSAVES_LAST: + case XED_IFORMFL_XSAVES64_FIRST: + case XED_IFORMFL_XSAVES64_LAST: + case XED_IFORMFL_XSETBV_FIRST: + case XED_IFORMFL_XSETBV_LAST: + case XED_IFORMFL_XSTORE_FIRST: + case XED_IFORMFL_XSTORE_LAST: + case XED_IFORMFL_XSUSLDTRK_FIRST: + case XED_IFORMFL_XSUSLDTRK_LAST: + case XED_IFORMFL_XTEST_FIRST: + case XED_IFORMFL_XTEST_LAST: + case XED_IFORMFL_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-iformfl-enum.h b/CodeVirtualizer/build/obj/xed-iformfl-enum.h new file mode 100644 index 0000000..13c47f2 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iformfl-enum.h @@ -0,0 +1,6959 @@ +/// @file xed-iformfl-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_IFORMFL_ENUM_H) +# define XED_IFORMFL_ENUM_H +#include "xed-common-hdrs.h" +#include "xed-iclass-enum.h" +#define XED_IFORMFL_AAA_FIRST_DEFINED 1 +#define XED_IFORMFL_AAA_LAST_DEFINED 1 +#define XED_IFORMFL_AAD_FIRST_DEFINED 1 +#define XED_IFORMFL_AAD_LAST_DEFINED 1 +#define XED_IFORMFL_AAM_FIRST_DEFINED 1 +#define XED_IFORMFL_AAM_LAST_DEFINED 1 +#define XED_IFORMFL_AAS_FIRST_DEFINED 1 +#define XED_IFORMFL_AAS_LAST_DEFINED 1 +#define XED_IFORMFL_ADC_FIRST_DEFINED 1 +#define XED_IFORMFL_ADC_LAST_DEFINED 1 +#define XED_IFORMFL_ADCX_FIRST_DEFINED 1 +#define XED_IFORMFL_ADCX_LAST_DEFINED 1 +#define XED_IFORMFL_ADC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_ADC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_ADD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ADDSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_ADD_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_ADD_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_ADOX_FIRST_DEFINED 1 +#define XED_IFORMFL_ADOX_LAST_DEFINED 1 +#define XED_IFORMFL_AESDEC_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDEC_LAST_DEFINED 1 +#define XED_IFORMFL_AESDEC128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDEC128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESDEC256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDEC256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESDECLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDECLAST_LAST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESDECWIDE256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENC_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENC_LAST_DEFINED 1 +#define XED_IFORMFL_AESENC128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENC128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENC256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENC256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENCLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENCLAST_LAST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE128KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE128KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE256KL_FIRST_DEFINED 1 +#define XED_IFORMFL_AESENCWIDE256KL_LAST_DEFINED 1 +#define XED_IFORMFL_AESIMC_FIRST_DEFINED 1 +#define XED_IFORMFL_AESIMC_LAST_DEFINED 1 +#define XED_IFORMFL_AESKEYGENASSIST_FIRST_DEFINED 1 +#define XED_IFORMFL_AESKEYGENASSIST_LAST_DEFINED 1 +#define XED_IFORMFL_AND_FIRST_DEFINED 1 +#define XED_IFORMFL_AND_LAST_DEFINED 1 +#define XED_IFORMFL_ANDN_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDN_LAST_DEFINED 1 +#define XED_IFORMFL_ANDNPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDNPD_LAST_DEFINED 1 +#define XED_IFORMFL_ANDNPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDNPS_LAST_DEFINED 1 +#define XED_IFORMFL_ANDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDPD_LAST_DEFINED 1 +#define XED_IFORMFL_ANDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ANDPS_LAST_DEFINED 1 +#define XED_IFORMFL_AND_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_AND_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_ARPL_FIRST_DEFINED 1 +#define XED_IFORMFL_ARPL_LAST_DEFINED 1 +#define XED_IFORMFL_BEXTR_FIRST_DEFINED 1 +#define XED_IFORMFL_BEXTR_LAST_DEFINED 1 +#define XED_IFORMFL_BEXTR_XOP_FIRST_DEFINED 1 +#define XED_IFORMFL_BEXTR_XOP_LAST_DEFINED 1 +#define XED_IFORMFL_BLCFILL_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCFILL_LAST_DEFINED 1 +#define XED_IFORMFL_BLCI_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCI_LAST_DEFINED 1 +#define XED_IFORMFL_BLCIC_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCIC_LAST_DEFINED 1 +#define XED_IFORMFL_BLCMSK_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCMSK_LAST_DEFINED 1 +#define XED_IFORMFL_BLCS_FIRST_DEFINED 1 +#define XED_IFORMFL_BLCS_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDPD_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDPS_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDVPD_LAST_DEFINED 1 +#define XED_IFORMFL_BLENDVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_BLENDVPS_LAST_DEFINED 1 +#define XED_IFORMFL_BLSFILL_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSFILL_LAST_DEFINED 1 +#define XED_IFORMFL_BLSI_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSI_LAST_DEFINED 1 +#define XED_IFORMFL_BLSIC_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSIC_LAST_DEFINED 1 +#define XED_IFORMFL_BLSMSK_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSMSK_LAST_DEFINED 1 +#define XED_IFORMFL_BLSR_FIRST_DEFINED 1 +#define XED_IFORMFL_BLSR_LAST_DEFINED 1 +#define XED_IFORMFL_BNDCL_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDCL_LAST_DEFINED 1 +#define XED_IFORMFL_BNDCN_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDCN_LAST_DEFINED 1 +#define XED_IFORMFL_BNDCU_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDCU_LAST_DEFINED 1 +#define XED_IFORMFL_BNDLDX_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDLDX_LAST_DEFINED 1 +#define XED_IFORMFL_BNDMK_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDMK_LAST_DEFINED 1 +#define XED_IFORMFL_BNDMOV_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDMOV_LAST_DEFINED 1 +#define XED_IFORMFL_BNDSTX_FIRST_DEFINED 1 +#define XED_IFORMFL_BNDSTX_LAST_DEFINED 1 +#define XED_IFORMFL_BOUND_FIRST_DEFINED 1 +#define XED_IFORMFL_BOUND_LAST_DEFINED 1 +#define XED_IFORMFL_BSF_FIRST_DEFINED 1 +#define XED_IFORMFL_BSF_LAST_DEFINED 1 +#define XED_IFORMFL_BSR_FIRST_DEFINED 1 +#define XED_IFORMFL_BSR_LAST_DEFINED 1 +#define XED_IFORMFL_BSWAP_FIRST_DEFINED 1 +#define XED_IFORMFL_BSWAP_LAST_DEFINED 1 +#define XED_IFORMFL_BT_FIRST_DEFINED 1 +#define XED_IFORMFL_BT_LAST_DEFINED 1 +#define XED_IFORMFL_BTC_FIRST_DEFINED 1 +#define XED_IFORMFL_BTC_LAST_DEFINED 1 +#define XED_IFORMFL_BTC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_BTC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_BTR_FIRST_DEFINED 1 +#define XED_IFORMFL_BTR_LAST_DEFINED 1 +#define XED_IFORMFL_BTR_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_BTR_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_BTS_FIRST_DEFINED 1 +#define XED_IFORMFL_BTS_LAST_DEFINED 1 +#define XED_IFORMFL_BTS_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_BTS_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_BZHI_FIRST_DEFINED 1 +#define XED_IFORMFL_BZHI_LAST_DEFINED 1 +#define XED_IFORMFL_CALL_FAR_FIRST_DEFINED 1 +#define XED_IFORMFL_CALL_FAR_LAST_DEFINED 1 +#define XED_IFORMFL_CALL_NEAR_FIRST_DEFINED 1 +#define XED_IFORMFL_CALL_NEAR_LAST_DEFINED 1 +#define XED_IFORMFL_CBW_FIRST_DEFINED 1 +#define XED_IFORMFL_CBW_LAST_DEFINED 1 +#define XED_IFORMFL_CDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CDQ_LAST_DEFINED 1 +#define XED_IFORMFL_CDQE_FIRST_DEFINED 1 +#define XED_IFORMFL_CDQE_LAST_DEFINED 1 +#define XED_IFORMFL_CLAC_FIRST_DEFINED 1 +#define XED_IFORMFL_CLAC_LAST_DEFINED 1 +#define XED_IFORMFL_CLC_FIRST_DEFINED 1 +#define XED_IFORMFL_CLC_LAST_DEFINED 1 +#define XED_IFORMFL_CLD_FIRST_DEFINED 1 +#define XED_IFORMFL_CLD_LAST_DEFINED 1 +#define XED_IFORMFL_CLDEMOTE_FIRST_DEFINED 1 +#define XED_IFORMFL_CLDEMOTE_LAST_DEFINED 1 +#define XED_IFORMFL_CLFLUSH_FIRST_DEFINED 1 +#define XED_IFORMFL_CLFLUSH_LAST_DEFINED 1 +#define XED_IFORMFL_CLFLUSHOPT_FIRST_DEFINED 1 +#define XED_IFORMFL_CLFLUSHOPT_LAST_DEFINED 1 +#define XED_IFORMFL_CLGI_FIRST_DEFINED 1 +#define XED_IFORMFL_CLGI_LAST_DEFINED 1 +#define XED_IFORMFL_CLI_FIRST_DEFINED 1 +#define XED_IFORMFL_CLI_LAST_DEFINED 1 +#define XED_IFORMFL_CLRSSBSY_FIRST_DEFINED 1 +#define XED_IFORMFL_CLRSSBSY_LAST_DEFINED 1 +#define XED_IFORMFL_CLTS_FIRST_DEFINED 1 +#define XED_IFORMFL_CLTS_LAST_DEFINED 1 +#define XED_IFORMFL_CLUI_FIRST_DEFINED 1 +#define XED_IFORMFL_CLUI_LAST_DEFINED 1 +#define XED_IFORMFL_CLWB_FIRST_DEFINED 1 +#define XED_IFORMFL_CLWB_LAST_DEFINED 1 +#define XED_IFORMFL_CLZERO_FIRST_DEFINED 1 +#define XED_IFORMFL_CLZERO_LAST_DEFINED 1 +#define XED_IFORMFL_CMC_FIRST_DEFINED 1 +#define XED_IFORMFL_CMC_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVB_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVB_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVBE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVBE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVL_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVL_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVLE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVLE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNB_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNB_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNBE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNL_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNL_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNLE_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNLE_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNO_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNO_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNP_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNP_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNS_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVNZ_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVNZ_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVO_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVO_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVP_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVP_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVS_LAST_DEFINED 1 +#define XED_IFORMFL_CMOVZ_FIRST_DEFINED 1 +#define XED_IFORMFL_CMOVZ_LAST_DEFINED 1 +#define XED_IFORMFL_CMP_FIRST_DEFINED 1 +#define XED_IFORMFL_CMP_LAST_DEFINED 1 +#define XED_IFORMFL_CMPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPPD_LAST_DEFINED 1 +#define XED_IFORMFL_CMPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPPS_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSB_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSB_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSD_XMM_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSD_XMM_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSQ_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSS_LAST_DEFINED 1 +#define XED_IFORMFL_CMPSW_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPSW_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG16B_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG8B_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_CMPXCHG_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_COMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_COMISD_LAST_DEFINED 1 +#define XED_IFORMFL_COMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_COMISS_LAST_DEFINED 1 +#define XED_IFORMFL_CPUID_FIRST_DEFINED 1 +#define XED_IFORMFL_CPUID_LAST_DEFINED 1 +#define XED_IFORMFL_CQO_FIRST_DEFINED 1 +#define XED_IFORMFL_CQO_LAST_DEFINED 1 +#define XED_IFORMFL_CRC32_FIRST_DEFINED 1 +#define XED_IFORMFL_CRC32_LAST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTDQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPD2PS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPI2PS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTPS2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSD2SS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSI2SS_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SD_LAST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPD2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2PI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTPS2PI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CVTTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_CVTTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_CWD_FIRST_DEFINED 1 +#define XED_IFORMFL_CWD_LAST_DEFINED 1 +#define XED_IFORMFL_CWDE_FIRST_DEFINED 1 +#define XED_IFORMFL_CWDE_LAST_DEFINED 1 +#define XED_IFORMFL_DAA_FIRST_DEFINED 1 +#define XED_IFORMFL_DAA_LAST_DEFINED 1 +#define XED_IFORMFL_DAS_FIRST_DEFINED 1 +#define XED_IFORMFL_DAS_LAST_DEFINED 1 +#define XED_IFORMFL_DEC_FIRST_DEFINED 1 +#define XED_IFORMFL_DEC_LAST_DEFINED 1 +#define XED_IFORMFL_DEC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_DEC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_DIV_FIRST_DEFINED 1 +#define XED_IFORMFL_DIV_LAST_DEFINED 1 +#define XED_IFORMFL_DIVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVPD_LAST_DEFINED 1 +#define XED_IFORMFL_DIVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVPS_LAST_DEFINED 1 +#define XED_IFORMFL_DIVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVSD_LAST_DEFINED 1 +#define XED_IFORMFL_DIVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_DIVSS_LAST_DEFINED 1 +#define XED_IFORMFL_DPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_DPPD_LAST_DEFINED 1 +#define XED_IFORMFL_DPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_DPPS_LAST_DEFINED 1 +#define XED_IFORMFL_EMMS_FIRST_DEFINED 1 +#define XED_IFORMFL_EMMS_LAST_DEFINED 1 +#define XED_IFORMFL_ENCLS_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCLS_LAST_DEFINED 1 +#define XED_IFORMFL_ENCLU_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCLU_LAST_DEFINED 1 +#define XED_IFORMFL_ENCLV_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCLV_LAST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY128_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY128_LAST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY256_FIRST_DEFINED 1 +#define XED_IFORMFL_ENCODEKEY256_LAST_DEFINED 1 +#define XED_IFORMFL_ENDBR32_FIRST_DEFINED 1 +#define XED_IFORMFL_ENDBR32_LAST_DEFINED 1 +#define XED_IFORMFL_ENDBR64_FIRST_DEFINED 1 +#define XED_IFORMFL_ENDBR64_LAST_DEFINED 1 +#define XED_IFORMFL_ENQCMD_FIRST_DEFINED 1 +#define XED_IFORMFL_ENQCMD_LAST_DEFINED 1 +#define XED_IFORMFL_ENQCMDS_FIRST_DEFINED 1 +#define XED_IFORMFL_ENQCMDS_LAST_DEFINED 1 +#define XED_IFORMFL_ENTER_FIRST_DEFINED 1 +#define XED_IFORMFL_ENTER_LAST_DEFINED 1 +#define XED_IFORMFL_EXTRACTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_EXTRACTPS_LAST_DEFINED 1 +#define XED_IFORMFL_EXTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_EXTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_F2XM1_FIRST_DEFINED 1 +#define XED_IFORMFL_F2XM1_LAST_DEFINED 1 +#define XED_IFORMFL_FABS_FIRST_DEFINED 1 +#define XED_IFORMFL_FABS_LAST_DEFINED 1 +#define XED_IFORMFL_FADD_FIRST_DEFINED 1 +#define XED_IFORMFL_FADD_LAST_DEFINED 1 +#define XED_IFORMFL_FADDP_FIRST_DEFINED 1 +#define XED_IFORMFL_FADDP_LAST_DEFINED 1 +#define XED_IFORMFL_FBLD_FIRST_DEFINED 1 +#define XED_IFORMFL_FBLD_LAST_DEFINED 1 +#define XED_IFORMFL_FBSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FBSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FCHS_FIRST_DEFINED 1 +#define XED_IFORMFL_FCHS_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVB_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVB_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVBE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVBE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNB_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNB_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNBE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNE_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNE_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVNU_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVNU_LAST_DEFINED 1 +#define XED_IFORMFL_FCMOVU_FIRST_DEFINED 1 +#define XED_IFORMFL_FCMOVU_LAST_DEFINED 1 +#define XED_IFORMFL_FCOM_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOM_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMI_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMI_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMIP_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMIP_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMP_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMP_LAST_DEFINED 1 +#define XED_IFORMFL_FCOMPP_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOMPP_LAST_DEFINED 1 +#define XED_IFORMFL_FCOS_FIRST_DEFINED 1 +#define XED_IFORMFL_FCOS_LAST_DEFINED 1 +#define XED_IFORMFL_FDECSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDECSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FDISI8087_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDISI8087_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_FDIV_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIV_LAST_DEFINED 1 +#define XED_IFORMFL_FDIVP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIVP_LAST_DEFINED 1 +#define XED_IFORMFL_FDIVR_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIVR_LAST_DEFINED 1 +#define XED_IFORMFL_FDIVRP_FIRST_DEFINED 1 +#define XED_IFORMFL_FDIVRP_LAST_DEFINED 1 +#define XED_IFORMFL_FEMMS_FIRST_DEFINED 1 +#define XED_IFORMFL_FEMMS_LAST_DEFINED 1 +#define XED_IFORMFL_FENI8087_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FENI8087_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_FFREE_FIRST_DEFINED 1 +#define XED_IFORMFL_FFREE_LAST_DEFINED 1 +#define XED_IFORMFL_FFREEP_FIRST_DEFINED 1 +#define XED_IFORMFL_FFREEP_LAST_DEFINED 1 +#define XED_IFORMFL_FIADD_FIRST_DEFINED 1 +#define XED_IFORMFL_FIADD_LAST_DEFINED 1 +#define XED_IFORMFL_FICOM_FIRST_DEFINED 1 +#define XED_IFORMFL_FICOM_LAST_DEFINED 1 +#define XED_IFORMFL_FICOMP_FIRST_DEFINED 1 +#define XED_IFORMFL_FICOMP_LAST_DEFINED 1 +#define XED_IFORMFL_FIDIV_FIRST_DEFINED 1 +#define XED_IFORMFL_FIDIV_LAST_DEFINED 1 +#define XED_IFORMFL_FIDIVR_FIRST_DEFINED 1 +#define XED_IFORMFL_FIDIVR_LAST_DEFINED 1 +#define XED_IFORMFL_FILD_FIRST_DEFINED 1 +#define XED_IFORMFL_FILD_LAST_DEFINED 1 +#define XED_IFORMFL_FIMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_FIMUL_LAST_DEFINED 1 +#define XED_IFORMFL_FINCSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FINCSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FIST_FIRST_DEFINED 1 +#define XED_IFORMFL_FIST_LAST_DEFINED 1 +#define XED_IFORMFL_FISTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FISTP_LAST_DEFINED 1 +#define XED_IFORMFL_FISTTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FISTTP_LAST_DEFINED 1 +#define XED_IFORMFL_FISUB_FIRST_DEFINED 1 +#define XED_IFORMFL_FISUB_LAST_DEFINED 1 +#define XED_IFORMFL_FISUBR_FIRST_DEFINED 1 +#define XED_IFORMFL_FISUBR_LAST_DEFINED 1 +#define XED_IFORMFL_FLD_FIRST_DEFINED 1 +#define XED_IFORMFL_FLD_LAST_DEFINED 1 +#define XED_IFORMFL_FLD1_FIRST_DEFINED 1 +#define XED_IFORMFL_FLD1_LAST_DEFINED 1 +#define XED_IFORMFL_FLDCW_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDCW_LAST_DEFINED 1 +#define XED_IFORMFL_FLDENV_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDENV_LAST_DEFINED 1 +#define XED_IFORMFL_FLDL2E_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDL2E_LAST_DEFINED 1 +#define XED_IFORMFL_FLDL2T_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDL2T_LAST_DEFINED 1 +#define XED_IFORMFL_FLDLG2_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDLG2_LAST_DEFINED 1 +#define XED_IFORMFL_FLDLN2_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDLN2_LAST_DEFINED 1 +#define XED_IFORMFL_FLDPI_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDPI_LAST_DEFINED 1 +#define XED_IFORMFL_FLDZ_FIRST_DEFINED 1 +#define XED_IFORMFL_FLDZ_LAST_DEFINED 1 +#define XED_IFORMFL_FMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_FMUL_LAST_DEFINED 1 +#define XED_IFORMFL_FMULP_FIRST_DEFINED 1 +#define XED_IFORMFL_FMULP_LAST_DEFINED 1 +#define XED_IFORMFL_FNCLEX_FIRST_DEFINED 1 +#define XED_IFORMFL_FNCLEX_LAST_DEFINED 1 +#define XED_IFORMFL_FNINIT_FIRST_DEFINED 1 +#define XED_IFORMFL_FNINIT_LAST_DEFINED 1 +#define XED_IFORMFL_FNOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FNOP_LAST_DEFINED 1 +#define XED_IFORMFL_FNSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_FNSTCW_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSTCW_LAST_DEFINED 1 +#define XED_IFORMFL_FNSTENV_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSTENV_LAST_DEFINED 1 +#define XED_IFORMFL_FNSTSW_FIRST_DEFINED 1 +#define XED_IFORMFL_FNSTSW_LAST_DEFINED 1 +#define XED_IFORMFL_FPATAN_FIRST_DEFINED 1 +#define XED_IFORMFL_FPATAN_LAST_DEFINED 1 +#define XED_IFORMFL_FPREM_FIRST_DEFINED 1 +#define XED_IFORMFL_FPREM_LAST_DEFINED 1 +#define XED_IFORMFL_FPREM1_FIRST_DEFINED 1 +#define XED_IFORMFL_FPREM1_LAST_DEFINED 1 +#define XED_IFORMFL_FPTAN_FIRST_DEFINED 1 +#define XED_IFORMFL_FPTAN_LAST_DEFINED 1 +#define XED_IFORMFL_FRNDINT_FIRST_DEFINED 1 +#define XED_IFORMFL_FRNDINT_LAST_DEFINED 1 +#define XED_IFORMFL_FRSTOR_FIRST_DEFINED 1 +#define XED_IFORMFL_FRSTOR_LAST_DEFINED 1 +#define XED_IFORMFL_FSCALE_FIRST_DEFINED 1 +#define XED_IFORMFL_FSCALE_LAST_DEFINED 1 +#define XED_IFORMFL_FSETPM287_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSETPM287_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_FSIN_FIRST_DEFINED 1 +#define XED_IFORMFL_FSIN_LAST_DEFINED 1 +#define XED_IFORMFL_FSINCOS_FIRST_DEFINED 1 +#define XED_IFORMFL_FSINCOS_LAST_DEFINED 1 +#define XED_IFORMFL_FSQRT_FIRST_DEFINED 1 +#define XED_IFORMFL_FSQRT_LAST_DEFINED 1 +#define XED_IFORMFL_FST_FIRST_DEFINED 1 +#define XED_IFORMFL_FST_LAST_DEFINED 1 +#define XED_IFORMFL_FSTP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSTP_LAST_DEFINED 1 +#define XED_IFORMFL_FSTPNCE_FIRST_DEFINED 1 +#define XED_IFORMFL_FSTPNCE_LAST_DEFINED 1 +#define XED_IFORMFL_FSUB_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUB_LAST_DEFINED 1 +#define XED_IFORMFL_FSUBP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUBP_LAST_DEFINED 1 +#define XED_IFORMFL_FSUBR_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUBR_LAST_DEFINED 1 +#define XED_IFORMFL_FSUBRP_FIRST_DEFINED 1 +#define XED_IFORMFL_FSUBRP_LAST_DEFINED 1 +#define XED_IFORMFL_FTST_FIRST_DEFINED 1 +#define XED_IFORMFL_FTST_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOM_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOM_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMI_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMI_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMIP_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMIP_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMP_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMP_LAST_DEFINED 1 +#define XED_IFORMFL_FUCOMPP_FIRST_DEFINED 1 +#define XED_IFORMFL_FUCOMPP_LAST_DEFINED 1 +#define XED_IFORMFL_FWAIT_FIRST_DEFINED 1 +#define XED_IFORMFL_FWAIT_LAST_DEFINED 1 +#define XED_IFORMFL_FXAM_FIRST_DEFINED 1 +#define XED_IFORMFL_FXAM_LAST_DEFINED 1 +#define XED_IFORMFL_FXCH_FIRST_DEFINED 1 +#define XED_IFORMFL_FXCH_LAST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR_FIRST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR_LAST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR64_FIRST_DEFINED 1 +#define XED_IFORMFL_FXRSTOR64_LAST_DEFINED 1 +#define XED_IFORMFL_FXSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_FXSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_FXSAVE64_FIRST_DEFINED 1 +#define XED_IFORMFL_FXSAVE64_LAST_DEFINED 1 +#define XED_IFORMFL_FXTRACT_FIRST_DEFINED 1 +#define XED_IFORMFL_FXTRACT_LAST_DEFINED 1 +#define XED_IFORMFL_FYL2X_FIRST_DEFINED 1 +#define XED_IFORMFL_FYL2X_LAST_DEFINED 1 +#define XED_IFORMFL_FYL2XP1_FIRST_DEFINED 1 +#define XED_IFORMFL_FYL2XP1_LAST_DEFINED 1 +#define XED_IFORMFL_GETSEC_FIRST_DEFINED 1 +#define XED_IFORMFL_GETSEC_LAST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEINVQB_FIRST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEINVQB_LAST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_GF2P8AFFINEQB_LAST_DEFINED 1 +#define XED_IFORMFL_GF2P8MULB_FIRST_DEFINED 1 +#define XED_IFORMFL_GF2P8MULB_LAST_DEFINED 1 +#define XED_IFORMFL_HADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_HADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_HADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_HADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_HLT_FIRST_DEFINED 1 +#define XED_IFORMFL_HLT_LAST_DEFINED 1 +#define XED_IFORMFL_HRESET_FIRST_DEFINED 1 +#define XED_IFORMFL_HRESET_LAST_DEFINED 1 +#define XED_IFORMFL_HSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_HSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_HSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_HSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_IDIV_FIRST_DEFINED 1 +#define XED_IFORMFL_IDIV_LAST_DEFINED 1 +#define XED_IFORMFL_IMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_IMUL_LAST_DEFINED 1 +#define XED_IFORMFL_IN_FIRST_DEFINED 1 +#define XED_IFORMFL_IN_LAST_DEFINED 1 +#define XED_IFORMFL_INC_FIRST_DEFINED 1 +#define XED_IFORMFL_INC_LAST_DEFINED 1 +#define XED_IFORMFL_INCSSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_INCSSPD_LAST_DEFINED 1 +#define XED_IFORMFL_INCSSPQ_FIRST_DEFINED 1 +#define XED_IFORMFL_INCSSPQ_LAST_DEFINED 1 +#define XED_IFORMFL_INC_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_INC_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_INSB_FIRST_DEFINED 1 +#define XED_IFORMFL_INSB_LAST_DEFINED 1 +#define XED_IFORMFL_INSD_FIRST_DEFINED 1 +#define XED_IFORMFL_INSD_LAST_DEFINED 1 +#define XED_IFORMFL_INSERTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_INSERTPS_LAST_DEFINED 1 +#define XED_IFORMFL_INSERTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_INSERTQ_LAST_DEFINED 1 +#define XED_IFORMFL_INSW_FIRST_DEFINED 1 +#define XED_IFORMFL_INSW_LAST_DEFINED 1 +#define XED_IFORMFL_INT_FIRST_DEFINED 1 +#define XED_IFORMFL_INT_LAST_DEFINED 1 +#define XED_IFORMFL_INT1_FIRST_DEFINED 1 +#define XED_IFORMFL_INT1_LAST_DEFINED 1 +#define XED_IFORMFL_INT3_FIRST_DEFINED 1 +#define XED_IFORMFL_INT3_LAST_DEFINED 1 +#define XED_IFORMFL_INTO_FIRST_DEFINED 1 +#define XED_IFORMFL_INTO_LAST_DEFINED 1 +#define XED_IFORMFL_INVD_FIRST_DEFINED 1 +#define XED_IFORMFL_INVD_LAST_DEFINED 1 +#define XED_IFORMFL_INVEPT_FIRST_DEFINED 1 +#define XED_IFORMFL_INVEPT_LAST_DEFINED 1 +#define XED_IFORMFL_INVLPG_FIRST_DEFINED 1 +#define XED_IFORMFL_INVLPG_LAST_DEFINED 1 +#define XED_IFORMFL_INVLPGA_FIRST_DEFINED 1 +#define XED_IFORMFL_INVLPGA_LAST_DEFINED 1 +#define XED_IFORMFL_INVLPGB_FIRST_DEFINED 1 +#define XED_IFORMFL_INVLPGB_LAST_DEFINED 1 +#define XED_IFORMFL_INVPCID_FIRST_DEFINED 1 +#define XED_IFORMFL_INVPCID_LAST_DEFINED 1 +#define XED_IFORMFL_INVVPID_FIRST_DEFINED 1 +#define XED_IFORMFL_INVVPID_LAST_DEFINED 1 +#define XED_IFORMFL_IRET_FIRST_DEFINED 1 +#define XED_IFORMFL_IRET_LAST_DEFINED 1 +#define XED_IFORMFL_IRETD_FIRST_DEFINED 1 +#define XED_IFORMFL_IRETD_LAST_DEFINED 1 +#define XED_IFORMFL_IRETQ_FIRST_DEFINED 1 +#define XED_IFORMFL_IRETQ_LAST_DEFINED 1 +#define XED_IFORMFL_JB_FIRST_DEFINED 1 +#define XED_IFORMFL_JB_LAST_DEFINED 1 +#define XED_IFORMFL_JBE_FIRST_DEFINED 1 +#define XED_IFORMFL_JBE_LAST_DEFINED 1 +#define XED_IFORMFL_JCXZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JCXZ_LAST_DEFINED 1 +#define XED_IFORMFL_JECXZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JECXZ_LAST_DEFINED 1 +#define XED_IFORMFL_JL_FIRST_DEFINED 1 +#define XED_IFORMFL_JL_LAST_DEFINED 1 +#define XED_IFORMFL_JLE_FIRST_DEFINED 1 +#define XED_IFORMFL_JLE_LAST_DEFINED 1 +#define XED_IFORMFL_JMP_FIRST_DEFINED 1 +#define XED_IFORMFL_JMP_LAST_DEFINED 1 +#define XED_IFORMFL_JMP_FAR_FIRST_DEFINED 1 +#define XED_IFORMFL_JMP_FAR_LAST_DEFINED 1 +#define XED_IFORMFL_JNB_FIRST_DEFINED 1 +#define XED_IFORMFL_JNB_LAST_DEFINED 1 +#define XED_IFORMFL_JNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_JNBE_LAST_DEFINED 1 +#define XED_IFORMFL_JNL_FIRST_DEFINED 1 +#define XED_IFORMFL_JNL_LAST_DEFINED 1 +#define XED_IFORMFL_JNLE_FIRST_DEFINED 1 +#define XED_IFORMFL_JNLE_LAST_DEFINED 1 +#define XED_IFORMFL_JNO_FIRST_DEFINED 1 +#define XED_IFORMFL_JNO_LAST_DEFINED 1 +#define XED_IFORMFL_JNP_FIRST_DEFINED 1 +#define XED_IFORMFL_JNP_LAST_DEFINED 1 +#define XED_IFORMFL_JNS_FIRST_DEFINED 1 +#define XED_IFORMFL_JNS_LAST_DEFINED 1 +#define XED_IFORMFL_JNZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JNZ_LAST_DEFINED 1 +#define XED_IFORMFL_JO_FIRST_DEFINED 1 +#define XED_IFORMFL_JO_LAST_DEFINED 1 +#define XED_IFORMFL_JP_FIRST_DEFINED 1 +#define XED_IFORMFL_JP_LAST_DEFINED 1 +#define XED_IFORMFL_JRCXZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JRCXZ_LAST_DEFINED 1 +#define XED_IFORMFL_JS_FIRST_DEFINED 1 +#define XED_IFORMFL_JS_LAST_DEFINED 1 +#define XED_IFORMFL_JZ_FIRST_DEFINED 1 +#define XED_IFORMFL_JZ_LAST_DEFINED 1 +#define XED_IFORMFL_KADDB_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDB_LAST_DEFINED 1 +#define XED_IFORMFL_KADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDD_LAST_DEFINED 1 +#define XED_IFORMFL_KADDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDQ_LAST_DEFINED 1 +#define XED_IFORMFL_KADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_KADDW_LAST_DEFINED 1 +#define XED_IFORMFL_KANDB_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDB_LAST_DEFINED 1 +#define XED_IFORMFL_KANDD_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDD_LAST_DEFINED 1 +#define XED_IFORMFL_KANDNB_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDNB_LAST_DEFINED 1 +#define XED_IFORMFL_KANDND_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDND_LAST_DEFINED 1 +#define XED_IFORMFL_KANDNQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDNQ_LAST_DEFINED 1 +#define XED_IFORMFL_KANDNW_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDNW_LAST_DEFINED 1 +#define XED_IFORMFL_KANDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDQ_LAST_DEFINED 1 +#define XED_IFORMFL_KANDW_FIRST_DEFINED 1 +#define XED_IFORMFL_KANDW_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVB_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVB_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVD_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_KMOVW_FIRST_DEFINED 1 +#define XED_IFORMFL_KMOVW_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTB_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTB_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTD_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTD_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTQ_LAST_DEFINED 1 +#define XED_IFORMFL_KNOTW_FIRST_DEFINED 1 +#define XED_IFORMFL_KNOTW_LAST_DEFINED 1 +#define XED_IFORMFL_KORB_FIRST_DEFINED 1 +#define XED_IFORMFL_KORB_LAST_DEFINED 1 +#define XED_IFORMFL_KORD_FIRST_DEFINED 1 +#define XED_IFORMFL_KORD_LAST_DEFINED 1 +#define XED_IFORMFL_KORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KORQ_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTB_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTB_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTD_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTD_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTQ_LAST_DEFINED 1 +#define XED_IFORMFL_KORTESTW_FIRST_DEFINED 1 +#define XED_IFORMFL_KORTESTW_LAST_DEFINED 1 +#define XED_IFORMFL_KORW_FIRST_DEFINED 1 +#define XED_IFORMFL_KORW_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLB_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLB_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLD_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLD_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLQ_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLW_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTLW_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRB_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRB_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRD_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRD_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRW_FIRST_DEFINED 1 +#define XED_IFORMFL_KSHIFTRW_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTB_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTB_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTD_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTD_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTQ_LAST_DEFINED 1 +#define XED_IFORMFL_KTESTW_FIRST_DEFINED 1 +#define XED_IFORMFL_KTESTW_LAST_DEFINED 1 +#define XED_IFORMFL_KUNPCKBW_FIRST_DEFINED 1 +#define XED_IFORMFL_KUNPCKBW_LAST_DEFINED 1 +#define XED_IFORMFL_KUNPCKDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KUNPCKDQ_LAST_DEFINED 1 +#define XED_IFORMFL_KUNPCKWD_FIRST_DEFINED 1 +#define XED_IFORMFL_KUNPCKWD_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORB_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORB_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORD_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORD_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORQ_LAST_DEFINED 1 +#define XED_IFORMFL_KXNORW_FIRST_DEFINED 1 +#define XED_IFORMFL_KXNORW_LAST_DEFINED 1 +#define XED_IFORMFL_KXORB_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORB_LAST_DEFINED 1 +#define XED_IFORMFL_KXORD_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORD_LAST_DEFINED 1 +#define XED_IFORMFL_KXORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORQ_LAST_DEFINED 1 +#define XED_IFORMFL_KXORW_FIRST_DEFINED 1 +#define XED_IFORMFL_KXORW_LAST_DEFINED 1 +#define XED_IFORMFL_LAHF_FIRST_DEFINED 1 +#define XED_IFORMFL_LAHF_LAST_DEFINED 1 +#define XED_IFORMFL_LAR_FIRST_DEFINED 1 +#define XED_IFORMFL_LAR_LAST_DEFINED 1 +#define XED_IFORMFL_LDDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_LDDQU_LAST_DEFINED 1 +#define XED_IFORMFL_LDMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_LDMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_LDS_FIRST_DEFINED 1 +#define XED_IFORMFL_LDS_LAST_DEFINED 1 +#define XED_IFORMFL_LDTILECFG_FIRST_DEFINED 1 +#define XED_IFORMFL_LDTILECFG_LAST_DEFINED 1 +#define XED_IFORMFL_LEA_FIRST_DEFINED 1 +#define XED_IFORMFL_LEA_LAST_DEFINED 1 +#define XED_IFORMFL_LEAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_LEAVE_LAST_DEFINED 1 +#define XED_IFORMFL_LES_FIRST_DEFINED 1 +#define XED_IFORMFL_LES_LAST_DEFINED 1 +#define XED_IFORMFL_LFENCE_FIRST_DEFINED 1 +#define XED_IFORMFL_LFENCE_LAST_DEFINED 1 +#define XED_IFORMFL_LFS_FIRST_DEFINED 1 +#define XED_IFORMFL_LFS_LAST_DEFINED 1 +#define XED_IFORMFL_LGDT_FIRST_DEFINED 1 +#define XED_IFORMFL_LGDT_LAST_DEFINED 1 +#define XED_IFORMFL_LGS_FIRST_DEFINED 1 +#define XED_IFORMFL_LGS_LAST_DEFINED 1 +#define XED_IFORMFL_LIDT_FIRST_DEFINED 1 +#define XED_IFORMFL_LIDT_LAST_DEFINED 1 +#define XED_IFORMFL_LLDT_FIRST_DEFINED 1 +#define XED_IFORMFL_LLDT_LAST_DEFINED 1 +#define XED_IFORMFL_LLWPCB_FIRST_DEFINED 1 +#define XED_IFORMFL_LLWPCB_LAST_DEFINED 1 +#define XED_IFORMFL_LMSW_FIRST_DEFINED 1 +#define XED_IFORMFL_LMSW_LAST_DEFINED 1 +#define XED_IFORMFL_LOADIWKEY_FIRST_DEFINED 1 +#define XED_IFORMFL_LOADIWKEY_LAST_DEFINED 1 +#define XED_IFORMFL_LODSB_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSB_LAST_DEFINED 1 +#define XED_IFORMFL_LODSD_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSD_LAST_DEFINED 1 +#define XED_IFORMFL_LODSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSQ_LAST_DEFINED 1 +#define XED_IFORMFL_LODSW_FIRST_DEFINED 1 +#define XED_IFORMFL_LODSW_LAST_DEFINED 1 +#define XED_IFORMFL_LOOP_FIRST_DEFINED 1 +#define XED_IFORMFL_LOOP_LAST_DEFINED 1 +#define XED_IFORMFL_LOOPE_FIRST_DEFINED 1 +#define XED_IFORMFL_LOOPE_LAST_DEFINED 1 +#define XED_IFORMFL_LOOPNE_FIRST_DEFINED 1 +#define XED_IFORMFL_LOOPNE_LAST_DEFINED 1 +#define XED_IFORMFL_LSL_FIRST_DEFINED 1 +#define XED_IFORMFL_LSL_LAST_DEFINED 1 +#define XED_IFORMFL_LSS_FIRST_DEFINED 1 +#define XED_IFORMFL_LSS_LAST_DEFINED 1 +#define XED_IFORMFL_LTR_FIRST_DEFINED 1 +#define XED_IFORMFL_LTR_LAST_DEFINED 1 +#define XED_IFORMFL_LWPINS_FIRST_DEFINED 1 +#define XED_IFORMFL_LWPINS_LAST_DEFINED 1 +#define XED_IFORMFL_LWPVAL_FIRST_DEFINED 1 +#define XED_IFORMFL_LWPVAL_LAST_DEFINED 1 +#define XED_IFORMFL_LZCNT_FIRST_DEFINED 1 +#define XED_IFORMFL_LZCNT_LAST_DEFINED 1 +#define XED_IFORMFL_MASKMOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_MASKMOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_MASKMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MASKMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_MAXPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXPD_LAST_DEFINED 1 +#define XED_IFORMFL_MAXPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXPS_LAST_DEFINED 1 +#define XED_IFORMFL_MAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_MAXSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MAXSS_LAST_DEFINED 1 +#define XED_IFORMFL_MCOMMIT_FIRST_DEFINED 1 +#define XED_IFORMFL_MCOMMIT_LAST_DEFINED 1 +#define XED_IFORMFL_MFENCE_FIRST_DEFINED 1 +#define XED_IFORMFL_MFENCE_LAST_DEFINED 1 +#define XED_IFORMFL_MINPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MINPD_LAST_DEFINED 1 +#define XED_IFORMFL_MINPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MINPS_LAST_DEFINED 1 +#define XED_IFORMFL_MINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MINSD_LAST_DEFINED 1 +#define XED_IFORMFL_MINSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MINSS_LAST_DEFINED 1 +#define XED_IFORMFL_MONITOR_FIRST_DEFINED 1 +#define XED_IFORMFL_MONITOR_LAST_DEFINED 1 +#define XED_IFORMFL_MONITORX_FIRST_DEFINED 1 +#define XED_IFORMFL_MONITORX_LAST_DEFINED 1 +#define XED_IFORMFL_MOV_FIRST_DEFINED 1 +#define XED_IFORMFL_MOV_LAST_DEFINED 1 +#define XED_IFORMFL_MOVAPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVAPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVAPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVAPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVBE_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVBE_LAST_DEFINED 1 +#define XED_IFORMFL_MOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDDUP_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDIR64B_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDIR64B_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDIRI_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDIRI_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDQ2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDQ2Q_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDQA_LAST_DEFINED 1 +#define XED_IFORMFL_MOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_MOVHLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVHLPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVHPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVHPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVLHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVLHPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVLPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVLPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVMSKPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTDQA_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTI_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTI_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTSD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVNTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVNTSS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVQ2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVQ2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSB_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSB_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSD_XMM_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSD_XMM_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSHDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSHDUP_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSLDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSLDUP_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSQ_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSW_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSW_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSX_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSX_LAST_DEFINED 1 +#define XED_IFORMFL_MOVSXD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVSXD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVUPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVUPD_LAST_DEFINED 1 +#define XED_IFORMFL_MOVUPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVUPS_LAST_DEFINED 1 +#define XED_IFORMFL_MOVZX_FIRST_DEFINED 1 +#define XED_IFORMFL_MOVZX_LAST_DEFINED 1 +#define XED_IFORMFL_MOV_CR_FIRST_DEFINED 1 +#define XED_IFORMFL_MOV_CR_LAST_DEFINED 1 +#define XED_IFORMFL_MOV_DR_FIRST_DEFINED 1 +#define XED_IFORMFL_MOV_DR_LAST_DEFINED 1 +#define XED_IFORMFL_MPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_MPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_MUL_FIRST_DEFINED 1 +#define XED_IFORMFL_MUL_LAST_DEFINED 1 +#define XED_IFORMFL_MULPD_FIRST_DEFINED 1 +#define XED_IFORMFL_MULPD_LAST_DEFINED 1 +#define XED_IFORMFL_MULPS_FIRST_DEFINED 1 +#define XED_IFORMFL_MULPS_LAST_DEFINED 1 +#define XED_IFORMFL_MULSD_FIRST_DEFINED 1 +#define XED_IFORMFL_MULSD_LAST_DEFINED 1 +#define XED_IFORMFL_MULSS_FIRST_DEFINED 1 +#define XED_IFORMFL_MULSS_LAST_DEFINED 1 +#define XED_IFORMFL_MULX_FIRST_DEFINED 1 +#define XED_IFORMFL_MULX_LAST_DEFINED 1 +#define XED_IFORMFL_MWAIT_FIRST_DEFINED 1 +#define XED_IFORMFL_MWAIT_LAST_DEFINED 1 +#define XED_IFORMFL_MWAITX_FIRST_DEFINED 1 +#define XED_IFORMFL_MWAITX_LAST_DEFINED 1 +#define XED_IFORMFL_NEG_FIRST_DEFINED 1 +#define XED_IFORMFL_NEG_LAST_DEFINED 1 +#define XED_IFORMFL_NEG_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_NEG_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_NOP_FIRST_DEFINED 1 +#define XED_IFORMFL_NOP_LAST_DEFINED 1 +#define XED_IFORMFL_NOT_FIRST_DEFINED 1 +#define XED_IFORMFL_NOT_LAST_DEFINED 1 +#define XED_IFORMFL_NOT_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_NOT_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_OR_FIRST_DEFINED 1 +#define XED_IFORMFL_OR_LAST_DEFINED 1 +#define XED_IFORMFL_ORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ORPD_LAST_DEFINED 1 +#define XED_IFORMFL_ORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ORPS_LAST_DEFINED 1 +#define XED_IFORMFL_OR_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_OR_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_OUT_FIRST_DEFINED 1 +#define XED_IFORMFL_OUT_LAST_DEFINED 1 +#define XED_IFORMFL_OUTSB_FIRST_DEFINED 1 +#define XED_IFORMFL_OUTSB_LAST_DEFINED 1 +#define XED_IFORMFL_OUTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_OUTSD_LAST_DEFINED 1 +#define XED_IFORMFL_OUTSW_FIRST_DEFINED 1 +#define XED_IFORMFL_OUTSW_LAST_DEFINED 1 +#define XED_IFORMFL_PABSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PABSB_LAST_DEFINED 1 +#define XED_IFORMFL_PABSD_FIRST_DEFINED 1 +#define XED_IFORMFL_PABSD_LAST_DEFINED 1 +#define XED_IFORMFL_PABSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PABSW_LAST_DEFINED 1 +#define XED_IFORMFL_PACKSSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKSSDW_LAST_DEFINED 1 +#define XED_IFORMFL_PACKSSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKSSWB_LAST_DEFINED 1 +#define XED_IFORMFL_PACKUSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKUSDW_LAST_DEFINED 1 +#define XED_IFORMFL_PACKUSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_PACKUSWB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDB_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDD_LAST_DEFINED 1 +#define XED_IFORMFL_PADDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PADDSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDSB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_PADDUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDUSB_LAST_DEFINED 1 +#define XED_IFORMFL_PADDUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDUSW_LAST_DEFINED 1 +#define XED_IFORMFL_PADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PADDW_LAST_DEFINED 1 +#define XED_IFORMFL_PALIGNR_FIRST_DEFINED 1 +#define XED_IFORMFL_PALIGNR_LAST_DEFINED 1 +#define XED_IFORMFL_PAND_FIRST_DEFINED 1 +#define XED_IFORMFL_PAND_LAST_DEFINED 1 +#define XED_IFORMFL_PANDN_FIRST_DEFINED 1 +#define XED_IFORMFL_PANDN_LAST_DEFINED 1 +#define XED_IFORMFL_PAUSE_FIRST_DEFINED 1 +#define XED_IFORMFL_PAUSE_LAST_DEFINED 1 +#define XED_IFORMFL_PAVGB_FIRST_DEFINED 1 +#define XED_IFORMFL_PAVGB_LAST_DEFINED 1 +#define XED_IFORMFL_PAVGUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PAVGUSB_LAST_DEFINED 1 +#define XED_IFORMFL_PAVGW_FIRST_DEFINED 1 +#define XED_IFORMFL_PAVGW_LAST_DEFINED 1 +#define XED_IFORMFL_PBLENDVB_FIRST_DEFINED 1 +#define XED_IFORMFL_PBLENDVB_LAST_DEFINED 1 +#define XED_IFORMFL_PBLENDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PBLENDW_LAST_DEFINED 1 +#define XED_IFORMFL_PCLMULQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PCLMULQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQB_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQD_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQD_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQQ_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPEQW_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPEQW_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM64_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPESTRM64_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTB_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTB_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTD_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTD_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTQ_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPGTW_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPGTW_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_PCMPISTRM_LAST_DEFINED 1 +#define XED_IFORMFL_PCONFIG_FIRST_DEFINED 1 +#define XED_IFORMFL_PCONFIG_LAST_DEFINED 1 +#define XED_IFORMFL_PDEP_FIRST_DEFINED 1 +#define XED_IFORMFL_PDEP_LAST_DEFINED 1 +#define XED_IFORMFL_PEXT_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXT_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRB_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRB_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRD_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRD_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_LAST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_SSE4_FIRST_DEFINED 1 +#define XED_IFORMFL_PEXTRW_SSE4_LAST_DEFINED 1 +#define XED_IFORMFL_PF2ID_FIRST_DEFINED 1 +#define XED_IFORMFL_PF2ID_LAST_DEFINED 1 +#define XED_IFORMFL_PF2IW_FIRST_DEFINED 1 +#define XED_IFORMFL_PF2IW_LAST_DEFINED 1 +#define XED_IFORMFL_PFACC_FIRST_DEFINED 1 +#define XED_IFORMFL_PFACC_LAST_DEFINED 1 +#define XED_IFORMFL_PFADD_FIRST_DEFINED 1 +#define XED_IFORMFL_PFADD_LAST_DEFINED 1 +#define XED_IFORMFL_PFCMPEQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PFCMPEQ_LAST_DEFINED 1 +#define XED_IFORMFL_PFCMPGE_FIRST_DEFINED 1 +#define XED_IFORMFL_PFCMPGE_LAST_DEFINED 1 +#define XED_IFORMFL_PFCMPGT_FIRST_DEFINED 1 +#define XED_IFORMFL_PFCMPGT_LAST_DEFINED 1 +#define XED_IFORMFL_PFMAX_FIRST_DEFINED 1 +#define XED_IFORMFL_PFMAX_LAST_DEFINED 1 +#define XED_IFORMFL_PFMIN_FIRST_DEFINED 1 +#define XED_IFORMFL_PFMIN_LAST_DEFINED 1 +#define XED_IFORMFL_PFMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_PFMUL_LAST_DEFINED 1 +#define XED_IFORMFL_PFNACC_FIRST_DEFINED 1 +#define XED_IFORMFL_PFNACC_LAST_DEFINED 1 +#define XED_IFORMFL_PFPNACC_FIRST_DEFINED 1 +#define XED_IFORMFL_PFPNACC_LAST_DEFINED 1 +#define XED_IFORMFL_PFRCP_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRCP_LAST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT1_LAST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT2_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRCPIT2_LAST_DEFINED 1 +#define XED_IFORMFL_PFRSQIT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRSQIT1_LAST_DEFINED 1 +#define XED_IFORMFL_PFRSQRT_FIRST_DEFINED 1 +#define XED_IFORMFL_PFRSQRT_LAST_DEFINED 1 +#define XED_IFORMFL_PFSUB_FIRST_DEFINED 1 +#define XED_IFORMFL_PFSUB_LAST_DEFINED 1 +#define XED_IFORMFL_PFSUBR_FIRST_DEFINED 1 +#define XED_IFORMFL_PFSUBR_LAST_DEFINED 1 +#define XED_IFORMFL_PHADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_PHADDD_LAST_DEFINED 1 +#define XED_IFORMFL_PHADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_PHADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHADDW_LAST_DEFINED 1 +#define XED_IFORMFL_PHMINPOSUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHMINPOSUW_LAST_DEFINED 1 +#define XED_IFORMFL_PHSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PHSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_PHSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_PHSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PHSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_PI2FD_FIRST_DEFINED 1 +#define XED_IFORMFL_PI2FD_LAST_DEFINED 1 +#define XED_IFORMFL_PI2FW_FIRST_DEFINED 1 +#define XED_IFORMFL_PI2FW_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRB_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRB_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRD_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRD_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRQ_LAST_DEFINED 1 +#define XED_IFORMFL_PINSRW_FIRST_DEFINED 1 +#define XED_IFORMFL_PINSRW_LAST_DEFINED 1 +#define XED_IFORMFL_PMADDUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMADDUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMADDWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMADDWD_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXSB_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXUB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXUB_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXUD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXUD_LAST_DEFINED 1 +#define XED_IFORMFL_PMAXUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMAXUW_LAST_DEFINED 1 +#define XED_IFORMFL_PMINSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINSB_LAST_DEFINED 1 +#define XED_IFORMFL_PMINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINSD_LAST_DEFINED 1 +#define XED_IFORMFL_PMINSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMINUB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINUB_LAST_DEFINED 1 +#define XED_IFORMFL_PMINUD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINUD_LAST_DEFINED 1 +#define XED_IFORMFL_PMINUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMINUW_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVMSKB_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVMSKB_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXBW_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVSXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXBW_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWD_LAST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMOVZXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMULDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHRSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHRSW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHRW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHRW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHUW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHUW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULHW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULHW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULLD_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULLD_LAST_DEFINED 1 +#define XED_IFORMFL_PMULLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULLW_LAST_DEFINED 1 +#define XED_IFORMFL_PMULUDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PMULUDQ_LAST_DEFINED 1 +#define XED_IFORMFL_POP_FIRST_DEFINED 1 +#define XED_IFORMFL_POP_LAST_DEFINED 1 +#define XED_IFORMFL_POPA_FIRST_DEFINED 1 +#define XED_IFORMFL_POPA_LAST_DEFINED 1 +#define XED_IFORMFL_POPAD_FIRST_DEFINED 1 +#define XED_IFORMFL_POPAD_LAST_DEFINED 1 +#define XED_IFORMFL_POPCNT_FIRST_DEFINED 1 +#define XED_IFORMFL_POPCNT_LAST_DEFINED 1 +#define XED_IFORMFL_POPF_FIRST_DEFINED 1 +#define XED_IFORMFL_POPF_LAST_DEFINED 1 +#define XED_IFORMFL_POPFD_FIRST_DEFINED 1 +#define XED_IFORMFL_POPFD_LAST_DEFINED 1 +#define XED_IFORMFL_POPFQ_FIRST_DEFINED 1 +#define XED_IFORMFL_POPFQ_LAST_DEFINED 1 +#define XED_IFORMFL_POR_FIRST_DEFINED 1 +#define XED_IFORMFL_POR_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHNTA_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHNTA_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT0_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT0_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT1_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT2_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHT2_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHW_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHW_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCHWT1_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCHWT1_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_RESERVED_FIRST_DEFINED 1 +#define XED_IFORMFL_PREFETCH_RESERVED_LAST_DEFINED 1 +#define XED_IFORMFL_PSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFB_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFD_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFHW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFHW_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFLW_LAST_DEFINED 1 +#define XED_IFORMFL_PSHUFW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSHUFW_LAST_DEFINED 1 +#define XED_IFORMFL_PSIGNB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSIGNB_LAST_DEFINED 1 +#define XED_IFORMFL_PSIGND_FIRST_DEFINED 1 +#define XED_IFORMFL_PSIGND_LAST_DEFINED 1 +#define XED_IFORMFL_PSIGNW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSIGNW_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLD_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSLLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSLLW_LAST_DEFINED 1 +#define XED_IFORMFL_PSMASH_FIRST_DEFINED 1 +#define XED_IFORMFL_PSMASH_LAST_DEFINED 1 +#define XED_IFORMFL_PSRAD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRAD_LAST_DEFINED 1 +#define XED_IFORMFL_PSRAW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRAW_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLD_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSRLW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSRLW_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBB_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBQ_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBSB_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBUSB_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBUSW_LAST_DEFINED 1 +#define XED_IFORMFL_PSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_PSWAPD_FIRST_DEFINED 1 +#define XED_IFORMFL_PSWAPD_LAST_DEFINED 1 +#define XED_IFORMFL_PTEST_FIRST_DEFINED 1 +#define XED_IFORMFL_PTEST_LAST_DEFINED 1 +#define XED_IFORMFL_PTWRITE_FIRST_DEFINED 1 +#define XED_IFORMFL_PTWRITE_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHBW_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKHWD_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLBW_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLBW_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLWD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUNPCKLWD_LAST_DEFINED 1 +#define XED_IFORMFL_PUSH_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSH_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHA_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHA_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHAD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHAD_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHF_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHF_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHFD_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHFD_LAST_DEFINED 1 +#define XED_IFORMFL_PUSHFQ_FIRST_DEFINED 1 +#define XED_IFORMFL_PUSHFQ_LAST_DEFINED 1 +#define XED_IFORMFL_PVALIDATE_FIRST_DEFINED 1 +#define XED_IFORMFL_PVALIDATE_LAST_DEFINED 1 +#define XED_IFORMFL_PXOR_FIRST_DEFINED 1 +#define XED_IFORMFL_PXOR_LAST_DEFINED 1 +#define XED_IFORMFL_RCL_FIRST_DEFINED 1 +#define XED_IFORMFL_RCL_LAST_DEFINED 1 +#define XED_IFORMFL_RCPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_RCPPS_LAST_DEFINED 1 +#define XED_IFORMFL_RCPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_RCPSS_LAST_DEFINED 1 +#define XED_IFORMFL_RCR_FIRST_DEFINED 1 +#define XED_IFORMFL_RCR_LAST_DEFINED 1 +#define XED_IFORMFL_RDFSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_RDFSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_RDGSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_RDGSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_RDMSR_FIRST_DEFINED 1 +#define XED_IFORMFL_RDMSR_LAST_DEFINED 1 +#define XED_IFORMFL_RDPID_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPID_LAST_DEFINED 1 +#define XED_IFORMFL_RDPKRU_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPKRU_LAST_DEFINED 1 +#define XED_IFORMFL_RDPMC_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPMC_LAST_DEFINED 1 +#define XED_IFORMFL_RDPRU_FIRST_DEFINED 1 +#define XED_IFORMFL_RDPRU_LAST_DEFINED 1 +#define XED_IFORMFL_RDRAND_FIRST_DEFINED 1 +#define XED_IFORMFL_RDRAND_LAST_DEFINED 1 +#define XED_IFORMFL_RDSEED_FIRST_DEFINED 1 +#define XED_IFORMFL_RDSEED_LAST_DEFINED 1 +#define XED_IFORMFL_RDSSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_RDSSPD_LAST_DEFINED 1 +#define XED_IFORMFL_RDSSPQ_FIRST_DEFINED 1 +#define XED_IFORMFL_RDSSPQ_LAST_DEFINED 1 +#define XED_IFORMFL_RDTSC_FIRST_DEFINED 1 +#define XED_IFORMFL_RDTSC_LAST_DEFINED 1 +#define XED_IFORMFL_RDTSCP_FIRST_DEFINED 1 +#define XED_IFORMFL_RDTSCP_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSB_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_CMPSW_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASB_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASD_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPE_SCASW_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSB_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_CMPSW_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASB_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASB_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASD_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASD_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASQ_LAST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASW_FIRST_DEFINED 1 +#define XED_IFORMFL_REPNE_SCASW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_INSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_INSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_INSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_INSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_INSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_INSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REP_LODSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_LODSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MONTMUL_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MONTMUL_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_MOVSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_OUTSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSD_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSD_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSQ_LAST_DEFINED 1 +#define XED_IFORMFL_REP_STOSW_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_STOSW_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCBC_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCBC_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCFB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCFB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCTR_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTCTR_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTECB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTECB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTOFB_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XCRYPTOFB_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA1_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA1_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA256_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XSHA256_LAST_DEFINED 1 +#define XED_IFORMFL_REP_XSTORE_FIRST_DEFINED 1 +#define XED_IFORMFL_REP_XSTORE_LAST_DEFINED 1 +#define XED_IFORMFL_RET_FAR_FIRST_DEFINED 1 +#define XED_IFORMFL_RET_FAR_LAST_DEFINED 1 +#define XED_IFORMFL_RET_NEAR_FIRST_DEFINED 1 +#define XED_IFORMFL_RET_NEAR_LAST_DEFINED 1 +#define XED_IFORMFL_RMPADJUST_FIRST_DEFINED 1 +#define XED_IFORMFL_RMPADJUST_LAST_DEFINED 1 +#define XED_IFORMFL_RMPUPDATE_FIRST_DEFINED 1 +#define XED_IFORMFL_RMPUPDATE_LAST_DEFINED 1 +#define XED_IFORMFL_ROL_FIRST_DEFINED 1 +#define XED_IFORMFL_ROL_LAST_DEFINED 1 +#define XED_IFORMFL_ROR_FIRST_DEFINED 1 +#define XED_IFORMFL_ROR_LAST_DEFINED 1 +#define XED_IFORMFL_RORX_FIRST_DEFINED 1 +#define XED_IFORMFL_RORX_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDPD_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDPS_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDSD_LAST_DEFINED 1 +#define XED_IFORMFL_ROUNDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_ROUNDSS_LAST_DEFINED 1 +#define XED_IFORMFL_RSM_FIRST_DEFINED 1 +#define XED_IFORMFL_RSM_LAST_DEFINED 1 +#define XED_IFORMFL_RSQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_RSQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_RSQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_RSQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_RSTORSSP_FIRST_DEFINED 1 +#define XED_IFORMFL_RSTORSSP_LAST_DEFINED 1 +#define XED_IFORMFL_SAHF_FIRST_DEFINED 1 +#define XED_IFORMFL_SAHF_LAST_DEFINED 1 +#define XED_IFORMFL_SALC_FIRST_DEFINED 1 +#define XED_IFORMFL_SALC_LAST_DEFINED 1 +#define XED_IFORMFL_SAR_FIRST_DEFINED 1 +#define XED_IFORMFL_SAR_LAST_DEFINED 1 +#define XED_IFORMFL_SARX_FIRST_DEFINED 1 +#define XED_IFORMFL_SARX_LAST_DEFINED 1 +#define XED_IFORMFL_SAVEPREVSSP_FIRST_DEFINED 1 +#define XED_IFORMFL_SAVEPREVSSP_LAST_DEFINED 1 +#define XED_IFORMFL_SBB_FIRST_DEFINED 1 +#define XED_IFORMFL_SBB_LAST_DEFINED 1 +#define XED_IFORMFL_SBB_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_SBB_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_SCASB_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASB_LAST_DEFINED 1 +#define XED_IFORMFL_SCASD_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASD_LAST_DEFINED 1 +#define XED_IFORMFL_SCASQ_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASQ_LAST_DEFINED 1 +#define XED_IFORMFL_SCASW_FIRST_DEFINED 1 +#define XED_IFORMFL_SCASW_LAST_DEFINED 1 +#define XED_IFORMFL_SEAMCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_SEAMCALL_LAST_DEFINED 1 +#define XED_IFORMFL_SEAMOPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SEAMOPS_LAST_DEFINED 1 +#define XED_IFORMFL_SEAMRET_FIRST_DEFINED 1 +#define XED_IFORMFL_SEAMRET_LAST_DEFINED 1 +#define XED_IFORMFL_SENDUIPI_FIRST_DEFINED 1 +#define XED_IFORMFL_SENDUIPI_LAST_DEFINED 1 +#define XED_IFORMFL_SERIALIZE_FIRST_DEFINED 1 +#define XED_IFORMFL_SERIALIZE_LAST_DEFINED 1 +#define XED_IFORMFL_SETB_FIRST_DEFINED 1 +#define XED_IFORMFL_SETB_LAST_DEFINED 1 +#define XED_IFORMFL_SETBE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETBE_LAST_DEFINED 1 +#define XED_IFORMFL_SETL_FIRST_DEFINED 1 +#define XED_IFORMFL_SETL_LAST_DEFINED 1 +#define XED_IFORMFL_SETLE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETLE_LAST_DEFINED 1 +#define XED_IFORMFL_SETNB_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNB_LAST_DEFINED 1 +#define XED_IFORMFL_SETNBE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNBE_LAST_DEFINED 1 +#define XED_IFORMFL_SETNL_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNL_LAST_DEFINED 1 +#define XED_IFORMFL_SETNLE_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNLE_LAST_DEFINED 1 +#define XED_IFORMFL_SETNO_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNO_LAST_DEFINED 1 +#define XED_IFORMFL_SETNP_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNP_LAST_DEFINED 1 +#define XED_IFORMFL_SETNS_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNS_LAST_DEFINED 1 +#define XED_IFORMFL_SETNZ_FIRST_DEFINED 1 +#define XED_IFORMFL_SETNZ_LAST_DEFINED 1 +#define XED_IFORMFL_SETO_FIRST_DEFINED 1 +#define XED_IFORMFL_SETO_LAST_DEFINED 1 +#define XED_IFORMFL_SETP_FIRST_DEFINED 1 +#define XED_IFORMFL_SETP_LAST_DEFINED 1 +#define XED_IFORMFL_SETS_FIRST_DEFINED 1 +#define XED_IFORMFL_SETS_LAST_DEFINED 1 +#define XED_IFORMFL_SETSSBSY_FIRST_DEFINED 1 +#define XED_IFORMFL_SETSSBSY_LAST_DEFINED 1 +#define XED_IFORMFL_SETZ_FIRST_DEFINED 1 +#define XED_IFORMFL_SETZ_LAST_DEFINED 1 +#define XED_IFORMFL_SFENCE_FIRST_DEFINED 1 +#define XED_IFORMFL_SFENCE_LAST_DEFINED 1 +#define XED_IFORMFL_SGDT_FIRST_DEFINED 1 +#define XED_IFORMFL_SGDT_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG1_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG1_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG2_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1MSG2_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1NEXTE_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1NEXTE_LAST_DEFINED 1 +#define XED_IFORMFL_SHA1RNDS4_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA1RNDS4_LAST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG1_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG1_LAST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG2_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA256MSG2_LAST_DEFINED 1 +#define XED_IFORMFL_SHA256RNDS2_FIRST_DEFINED 1 +#define XED_IFORMFL_SHA256RNDS2_LAST_DEFINED 1 +#define XED_IFORMFL_SHL_FIRST_DEFINED 1 +#define XED_IFORMFL_SHL_LAST_DEFINED 1 +#define XED_IFORMFL_SHLD_FIRST_DEFINED 1 +#define XED_IFORMFL_SHLD_LAST_DEFINED 1 +#define XED_IFORMFL_SHLX_FIRST_DEFINED 1 +#define XED_IFORMFL_SHLX_LAST_DEFINED 1 +#define XED_IFORMFL_SHR_FIRST_DEFINED 1 +#define XED_IFORMFL_SHR_LAST_DEFINED 1 +#define XED_IFORMFL_SHRD_FIRST_DEFINED 1 +#define XED_IFORMFL_SHRD_LAST_DEFINED 1 +#define XED_IFORMFL_SHRX_FIRST_DEFINED 1 +#define XED_IFORMFL_SHRX_LAST_DEFINED 1 +#define XED_IFORMFL_SHUFPD_FIRST_DEFINED 1 +#define XED_IFORMFL_SHUFPD_LAST_DEFINED 1 +#define XED_IFORMFL_SHUFPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SHUFPS_LAST_DEFINED 1 +#define XED_IFORMFL_SIDT_FIRST_DEFINED 1 +#define XED_IFORMFL_SIDT_LAST_DEFINED 1 +#define XED_IFORMFL_SKINIT_FIRST_DEFINED 1 +#define XED_IFORMFL_SKINIT_LAST_DEFINED 1 +#define XED_IFORMFL_SLDT_FIRST_DEFINED 1 +#define XED_IFORMFL_SLDT_LAST_DEFINED 1 +#define XED_IFORMFL_SLWPCB_FIRST_DEFINED 1 +#define XED_IFORMFL_SLWPCB_LAST_DEFINED 1 +#define XED_IFORMFL_SMSW_FIRST_DEFINED 1 +#define XED_IFORMFL_SMSW_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTPD_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTSD_LAST_DEFINED 1 +#define XED_IFORMFL_SQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_SQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_STAC_FIRST_DEFINED 1 +#define XED_IFORMFL_STAC_LAST_DEFINED 1 +#define XED_IFORMFL_STC_FIRST_DEFINED 1 +#define XED_IFORMFL_STC_LAST_DEFINED 1 +#define XED_IFORMFL_STD_FIRST_DEFINED 1 +#define XED_IFORMFL_STD_LAST_DEFINED 1 +#define XED_IFORMFL_STGI_FIRST_DEFINED 1 +#define XED_IFORMFL_STGI_LAST_DEFINED 1 +#define XED_IFORMFL_STI_FIRST_DEFINED 1 +#define XED_IFORMFL_STI_LAST_DEFINED 1 +#define XED_IFORMFL_STMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_STMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_STOSB_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSB_LAST_DEFINED 1 +#define XED_IFORMFL_STOSD_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSD_LAST_DEFINED 1 +#define XED_IFORMFL_STOSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSQ_LAST_DEFINED 1 +#define XED_IFORMFL_STOSW_FIRST_DEFINED 1 +#define XED_IFORMFL_STOSW_LAST_DEFINED 1 +#define XED_IFORMFL_STR_FIRST_DEFINED 1 +#define XED_IFORMFL_STR_LAST_DEFINED 1 +#define XED_IFORMFL_STTILECFG_FIRST_DEFINED 1 +#define XED_IFORMFL_STTILECFG_LAST_DEFINED 1 +#define XED_IFORMFL_STUI_FIRST_DEFINED 1 +#define XED_IFORMFL_STUI_LAST_DEFINED 1 +#define XED_IFORMFL_SUB_FIRST_DEFINED 1 +#define XED_IFORMFL_SUB_LAST_DEFINED 1 +#define XED_IFORMFL_SUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_SUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_SUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_SUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_SUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_SUB_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_SUB_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_SWAPGS_FIRST_DEFINED 1 +#define XED_IFORMFL_SWAPGS_LAST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_LAST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_AMD_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSCALL_AMD_LAST_DEFINED 1 +#define XED_IFORMFL_SYSENTER_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSENTER_LAST_DEFINED 1 +#define XED_IFORMFL_SYSEXIT_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSEXIT_LAST_DEFINED 1 +#define XED_IFORMFL_SYSRET_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSRET_LAST_DEFINED 1 +#define XED_IFORMFL_SYSRET64_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSRET64_LAST_DEFINED 1 +#define XED_IFORMFL_SYSRET_AMD_FIRST_DEFINED 1 +#define XED_IFORMFL_SYSRET_AMD_LAST_DEFINED 1 +#define XED_IFORMFL_T1MSKC_FIRST_DEFINED 1 +#define XED_IFORMFL_T1MSKC_LAST_DEFINED 1 +#define XED_IFORMFL_TDCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_TDCALL_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBF16PS_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBF16PS_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBSSD_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBSUD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBSUD_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBUSD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBUSD_LAST_DEFINED 1 +#define XED_IFORMFL_TDPBUUD_FIRST_DEFINED 1 +#define XED_IFORMFL_TDPBUUD_LAST_DEFINED 1 +#define XED_IFORMFL_TEST_FIRST_DEFINED 1 +#define XED_IFORMFL_TEST_LAST_DEFINED 1 +#define XED_IFORMFL_TESTUI_FIRST_DEFINED 1 +#define XED_IFORMFL_TESTUI_LAST_DEFINED 1 +#define XED_IFORMFL_TILELOADD_FIRST_DEFINED 1 +#define XED_IFORMFL_TILELOADD_LAST_DEFINED 1 +#define XED_IFORMFL_TILELOADDT1_FIRST_DEFINED 1 +#define XED_IFORMFL_TILELOADDT1_LAST_DEFINED 1 +#define XED_IFORMFL_TILERELEASE_FIRST_DEFINED 1 +#define XED_IFORMFL_TILERELEASE_LAST_DEFINED 1 +#define XED_IFORMFL_TILESTORED_FIRST_DEFINED 1 +#define XED_IFORMFL_TILESTORED_LAST_DEFINED 1 +#define XED_IFORMFL_TILEZERO_FIRST_DEFINED 1 +#define XED_IFORMFL_TILEZERO_LAST_DEFINED 1 +#define XED_IFORMFL_TLBSYNC_FIRST_DEFINED 1 +#define XED_IFORMFL_TLBSYNC_LAST_DEFINED 1 +#define XED_IFORMFL_TPAUSE_FIRST_DEFINED 1 +#define XED_IFORMFL_TPAUSE_LAST_DEFINED 1 +#define XED_IFORMFL_TZCNT_FIRST_DEFINED 1 +#define XED_IFORMFL_TZCNT_LAST_DEFINED 1 +#define XED_IFORMFL_TZMSK_FIRST_DEFINED 1 +#define XED_IFORMFL_TZMSK_LAST_DEFINED 1 +#define XED_IFORMFL_UCOMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_UCOMISD_LAST_DEFINED 1 +#define XED_IFORMFL_UCOMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_UCOMISS_LAST_DEFINED 1 +#define XED_IFORMFL_UD0_FIRST_DEFINED 1 +#define XED_IFORMFL_UD0_LAST_DEFINED 1 +#define XED_IFORMFL_UD1_FIRST_DEFINED 1 +#define XED_IFORMFL_UD1_LAST_DEFINED 1 +#define XED_IFORMFL_UD2_FIRST_DEFINED 1 +#define XED_IFORMFL_UD2_LAST_DEFINED 1 +#define XED_IFORMFL_UIRET_FIRST_DEFINED 1 +#define XED_IFORMFL_UIRET_LAST_DEFINED 1 +#define XED_IFORMFL_UMONITOR_FIRST_DEFINED 1 +#define XED_IFORMFL_UMONITOR_LAST_DEFINED 1 +#define XED_IFORMFL_UMWAIT_FIRST_DEFINED 1 +#define XED_IFORMFL_UMWAIT_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPD_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKHPS_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPD_LAST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_UNPCKLPS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_V4FNMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VADDPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDPH_LAST_DEFINED 1 +#define XED_IFORMFL_VADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSH_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VADDSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VAESDEC_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESDEC_LAST_DEFINED 1 +#define XED_IFORMFL_VAESDECLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESDECLAST_LAST_DEFINED 1 +#define XED_IFORMFL_VAESENC_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESENC_LAST_DEFINED 1 +#define XED_IFORMFL_VAESENCLAST_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESENCLAST_LAST_DEFINED 1 +#define XED_IFORMFL_VAESIMC_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESIMC_LAST_DEFINED 1 +#define XED_IFORMFL_VAESKEYGENASSIST_FIRST_DEFINED 1 +#define XED_IFORMFL_VAESKEYGENASSIST_LAST_DEFINED 1 +#define XED_IFORMFL_VALIGND_FIRST_DEFINED 1 +#define XED_IFORMFL_VALIGND_LAST_DEFINED 1 +#define XED_IFORMFL_VALIGNQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VALIGNQ_LAST_DEFINED 1 +#define XED_IFORMFL_VANDNPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDNPD_LAST_DEFINED 1 +#define XED_IFORMFL_VANDNPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDNPS_LAST_DEFINED 1 +#define XED_IFORMFL_VANDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VANDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VANDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDMPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPD_LAST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBLENDVPS_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF128_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF128_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTF64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI128_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI128_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTI64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSD_LAST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VBROADCASTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPPD_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPPH_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPSD_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPSH_LAST_DEFINED 1 +#define XED_IFORMFL_VCMPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCMPSS_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMISD_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMISH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMISH_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMISS_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPD_LAST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCOMPRESSPS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTDQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTNE2PS2BF16_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTNE2PS2BF16_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTNEPS2BF16_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTNEPS2BF16_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPD2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PSX_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2PSX_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UW_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2UW_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPH2W_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PHX_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2PHX_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTPS2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTQQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSD2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSH2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSI2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTSS2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPD2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UW_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2UW_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPH2W_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2DQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2DQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2QQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2QQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTPS2UQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSD2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSH2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2SI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2SI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2USI_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTTSS2USI_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUDQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUQQ2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SD_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUSI2SS_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTUW2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTUW2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VCVTW2PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VCVTW2PH_LAST_DEFINED 1 +#define XED_IFORMFL_VDBPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VDBPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVPD_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVPH_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVPS_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVSD_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVSH_LAST_DEFINED 1 +#define XED_IFORMFL_VDIVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDIVSS_LAST_DEFINED 1 +#define XED_IFORMFL_VDPBF16PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDPBF16PS_LAST_DEFINED 1 +#define XED_IFORMFL_VDPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VDPPD_LAST_DEFINED 1 +#define XED_IFORMFL_VDPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VDPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VERR_FIRST_DEFINED 1 +#define XED_IFORMFL_VERR_LAST_DEFINED 1 +#define XED_IFORMFL_VERW_FIRST_DEFINED 1 +#define XED_IFORMFL_VERW_LAST_DEFINED 1 +#define XED_IFORMFL_VEXP2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXP2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VEXP2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXP2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXPANDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF128_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF128_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTF64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI128_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI128_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTI64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VEXTRACTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMADDCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMULCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMULCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFCMULCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFCMULCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFIXUPIMMSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADD231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUB231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMADDSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUB231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADD231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMSUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFMULCPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMULCPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFMULCSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFMULCSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADD231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMADDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB132SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB213SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231PS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SH_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUB231SS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFNMSUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPH_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSH_LAST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFPCLASSSS_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZPD_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZPS_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZSD_LAST_DEFINED 1 +#define XED_IFORMFL_VFRCZSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VFRCZSS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF0QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERPF1QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGATHERQPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETEXPSS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSD_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSH_LAST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VGETMANTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEINVQB_LAST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VGF2P8AFFINEQB_LAST_DEFINED 1 +#define XED_IFORMFL_VGF2P8MULB_FIRST_DEFINED 1 +#define XED_IFORMFL_VGF2P8MULB_LAST_DEFINED 1 +#define XED_IFORMFL_VHADDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VHADDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VHADDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VHADDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VHSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VHSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VHSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VHSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF128_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF128_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTF64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI128_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI128_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X8_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI32X8_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTI64X4_LAST_DEFINED 1 +#define XED_IFORMFL_VINSERTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VINSERTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VLDDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_VLDDQU_LAST_DEFINED 1 +#define XED_IFORMFL_VLDMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_VLDMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMASKMOVPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXPH_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMAXSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMAXSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_VMCALL_LAST_DEFINED 1 +#define XED_IFORMFL_VMCLEAR_FIRST_DEFINED 1 +#define XED_IFORMFL_VMCLEAR_LAST_DEFINED 1 +#define XED_IFORMFL_VMFUNC_FIRST_DEFINED 1 +#define XED_IFORMFL_VMFUNC_LAST_DEFINED 1 +#define XED_IFORMFL_VMINPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMINPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINPH_LAST_DEFINED 1 +#define XED_IFORMFL_VMINPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMINSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMINSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMINSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMLAUNCH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMLAUNCH_LAST_DEFINED 1 +#define XED_IFORMFL_VMLOAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMLOAD_LAST_DEFINED 1 +#define XED_IFORMFL_VMMCALL_FIRST_DEFINED 1 +#define XED_IFORMFL_VMMCALL_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVAPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVAPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVAPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVAPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDDUP_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA32_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA32_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA64_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQA64_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU16_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU16_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU32_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU32_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU64_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU64_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU8_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVDQU8_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVHLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVHLPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVHPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVHPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVLHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVLHPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVLPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVLPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVMSKPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQA_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTDQA_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVNTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSHDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSHDUP_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSLDUP_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSLDUP_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVUPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVUPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVUPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVUPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMOVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VMOVW_LAST_DEFINED 1 +#define XED_IFORMFL_VMPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VMPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_VMPTRLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMPTRLD_LAST_DEFINED 1 +#define XED_IFORMFL_VMPTRST_FIRST_DEFINED 1 +#define XED_IFORMFL_VMPTRST_LAST_DEFINED 1 +#define XED_IFORMFL_VMREAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMREAD_LAST_DEFINED 1 +#define XED_IFORMFL_VMRESUME_FIRST_DEFINED 1 +#define XED_IFORMFL_VMRESUME_LAST_DEFINED 1 +#define XED_IFORMFL_VMRUN_FIRST_DEFINED 1 +#define XED_IFORMFL_VMRUN_LAST_DEFINED 1 +#define XED_IFORMFL_VMSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_VMSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_VMULPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULPD_LAST_DEFINED 1 +#define XED_IFORMFL_VMULPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULPH_LAST_DEFINED 1 +#define XED_IFORMFL_VMULPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULPS_LAST_DEFINED 1 +#define XED_IFORMFL_VMULSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULSD_LAST_DEFINED 1 +#define XED_IFORMFL_VMULSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULSH_LAST_DEFINED 1 +#define XED_IFORMFL_VMULSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VMULSS_LAST_DEFINED 1 +#define XED_IFORMFL_VMWRITE_FIRST_DEFINED 1 +#define XED_IFORMFL_VMWRITE_LAST_DEFINED 1 +#define XED_IFORMFL_VMXOFF_FIRST_DEFINED 1 +#define XED_IFORMFL_VMXOFF_LAST_DEFINED 1 +#define XED_IFORMFL_VMXON_FIRST_DEFINED 1 +#define XED_IFORMFL_VMXON_LAST_DEFINED 1 +#define XED_IFORMFL_VORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VORPD_LAST_DEFINED 1 +#define XED_IFORMFL_VORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VORPS_LAST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTD_LAST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VP2INTERSECTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSD_LAST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSDS_FIRST_DEFINED 1 +#define XED_IFORMFL_VP4DPWSSDS_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPABSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPABSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKSSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKSSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKSSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKSSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKUSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKUSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPACKUSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPACKUSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDUSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDUSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPADDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPALIGNR_FIRST_DEFINED 1 +#define XED_IFORMFL_VPALIGNR_LAST_DEFINED 1 +#define XED_IFORMFL_VPAND_FIRST_DEFINED 1 +#define XED_IFORMFL_VPAND_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDN_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDN_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDND_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDND_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDNQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDNQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPANDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPANDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPAVGB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPAVGB_LAST_DEFINED 1 +#define XED_IFORMFL_VPAVGW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPAVGW_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDVB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDVB_LAST_DEFINED 1 +#define XED_IFORMFL_VPBLENDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBLENDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMB2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMB2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMW2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTMW2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPBROADCASTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCLMULQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCLMULQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMOV_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMOV_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPEQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM64_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPESTRM64_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPGTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI64_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRI64_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRM_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPISTRM_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCMPW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCMPW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMPRESSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCOMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCOMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPCONFLICTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSDS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPBUSDS_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSDS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPDPWSSDS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERM2F128_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERM2F128_LAST_DEFINED 1 +#define XED_IFORMFL_VPERM2I128_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERM2I128_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2B_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2B_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMI2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMI2W_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMIL2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMILPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMILPD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMILPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMILPS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMPD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMPS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2B_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2B_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PD_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2PS_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMT2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMT2W_LAST_DEFINED 1 +#define XED_IFORMFL_VPERMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPERMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXPANDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRB_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRD_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_LAST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_C5_FIRST_DEFINED 1 +#define XED_IFORMFL_VPEXTRW_C5_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPGATHERQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDUWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHADDWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHADDWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHMINPOSUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHMINPOSUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPHSUBWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPHSUBWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRB_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRD_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPINSRW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPINSRW_LAST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPLZCNTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQH_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQH_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQL_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSDQL_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQH_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQH_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQL_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSDQL_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSSWW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMACSWW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMACSWW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADCSSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADCSSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADCSWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADCSWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADD52HUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADD52HUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADD52LUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADD52LUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADDUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADDUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMADDWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMADDWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMASKMOVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMAXUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMAXUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMINUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMINUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVB2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVB2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVD2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVD2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2B_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2B_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2D_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2D_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2Q_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2Q_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2W_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVM2W_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVMSKB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVMSKB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQ2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQ2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVSXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSQW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVUSWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVW2M_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVW2M_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVWB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVWB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMOVZXWQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULHRSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULHRSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULHUW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULHUW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULHW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULHW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULTISHIFTQB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULTISHIFTQB_LAST_DEFINED 1 +#define XED_IFORMFL_VPMULUDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPMULUDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOPCNTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPOR_FIRST_DEFINED 1 +#define XED_IFORMFL_VPOR_LAST_DEFINED 1 +#define XED_IFORMFL_VPORD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPORD_LAST_DEFINED 1 +#define XED_IFORMFL_VPORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPORQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPPERM_FIRST_DEFINED 1 +#define XED_IFORMFL_VPPERM_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPROLVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROLVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORD_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPRORVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPRORVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTB_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTD_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPROTW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPROTW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSADBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSADBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSCATTERQQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHAW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHAW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHRDW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHRDW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFBITQMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFBITQMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFHW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFHW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSHUFLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSHUFLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSIGNB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSIGNB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSIGND_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSIGND_LAST_DEFINED 1 +#define XED_IFORMFL_VPSIGNW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSIGNW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSLLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSLLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRAW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRAW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLVD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLVD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLVQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLVQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLVW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLVW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSRLW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSRLW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBD_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSB_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBUSW_LAST_DEFINED 1 +#define XED_IFORMFL_VPSUBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPSUBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGD_LAST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTERNLOGQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPTEST_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTEST_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMB_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMB_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMD_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPTESTNMW_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKHWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLBW_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLBW_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLQDQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLQDQ_LAST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLWD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPUNPCKLWD_LAST_DEFINED 1 +#define XED_IFORMFL_VPXOR_FIRST_DEFINED 1 +#define XED_IFORMFL_VPXOR_LAST_DEFINED 1 +#define XED_IFORMFL_VPXORD_FIRST_DEFINED 1 +#define XED_IFORMFL_VPXORD_LAST_DEFINED 1 +#define XED_IFORMFL_VPXORQ_FIRST_DEFINED 1 +#define XED_IFORMFL_VPXORQ_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGEPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGEPD_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGEPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGEPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGESD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGESD_LAST_DEFINED 1 +#define XED_IFORMFL_VRANGESS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRANGESS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP14SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP14SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRCP28SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCP28SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPPH_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPSH_LAST_DEFINED 1 +#define XED_IFORMFL_VRCPSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRCPSS_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPD_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPH_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCEPS_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCESD_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCESD_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCESH_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCESH_LAST_DEFINED 1 +#define XED_IFORMFL_VREDUCESS_FIRST_DEFINED 1 +#define XED_IFORMFL_VREDUCESS_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPD_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPH_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALEPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESD_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESH_LAST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRNDSCALESS_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDSD_LAST_DEFINED 1 +#define XED_IFORMFL_VROUNDSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VROUNDSS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT14SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28PS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SD_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SD_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRT28SS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPH_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSH_LAST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VRSQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPH_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSH_LAST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCALEFSS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERDPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF0QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1DPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERPF1QPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSCATTERQPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFF32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFF32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFF64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFF64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFI32X4_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFI32X4_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFI64X2_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFI64X2_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSHUFPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSHUFPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTPH_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTSD_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTSH_LAST_DEFINED 1 +#define XED_IFORMFL_VSQRTSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSQRTSS_LAST_DEFINED 1 +#define XED_IFORMFL_VSTMXCSR_FIRST_DEFINED 1 +#define XED_IFORMFL_VSTMXCSR_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBPD_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBPH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBPH_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBPS_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBSD_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBSD_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBSH_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBSH_LAST_DEFINED 1 +#define XED_IFORMFL_VSUBSS_FIRST_DEFINED 1 +#define XED_IFORMFL_VSUBSS_LAST_DEFINED 1 +#define XED_IFORMFL_VTESTPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VTESTPD_LAST_DEFINED 1 +#define XED_IFORMFL_VTESTPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VTESTPS_LAST_DEFINED 1 +#define XED_IFORMFL_VUCOMISD_FIRST_DEFINED 1 +#define XED_IFORMFL_VUCOMISD_LAST_DEFINED 1 +#define XED_IFORMFL_VUCOMISH_FIRST_DEFINED 1 +#define XED_IFORMFL_VUCOMISH_LAST_DEFINED 1 +#define XED_IFORMFL_VUCOMISS_FIRST_DEFINED 1 +#define XED_IFORMFL_VUCOMISS_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPD_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKHPS_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPD_LAST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VUNPCKLPS_LAST_DEFINED 1 +#define XED_IFORMFL_VXORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_VXORPD_LAST_DEFINED 1 +#define XED_IFORMFL_VXORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_VXORPS_LAST_DEFINED 1 +#define XED_IFORMFL_VZEROALL_FIRST_DEFINED 1 +#define XED_IFORMFL_VZEROALL_LAST_DEFINED 1 +#define XED_IFORMFL_VZEROUPPER_FIRST_DEFINED 1 +#define XED_IFORMFL_VZEROUPPER_LAST_DEFINED 1 +#define XED_IFORMFL_WBINVD_FIRST_DEFINED 1 +#define XED_IFORMFL_WBINVD_LAST_DEFINED 1 +#define XED_IFORMFL_WBNOINVD_FIRST_DEFINED 1 +#define XED_IFORMFL_WBNOINVD_LAST_DEFINED 1 +#define XED_IFORMFL_WRFSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_WRFSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_WRGSBASE_FIRST_DEFINED 1 +#define XED_IFORMFL_WRGSBASE_LAST_DEFINED 1 +#define XED_IFORMFL_WRMSR_FIRST_DEFINED 1 +#define XED_IFORMFL_WRMSR_LAST_DEFINED 1 +#define XED_IFORMFL_WRPKRU_FIRST_DEFINED 1 +#define XED_IFORMFL_WRPKRU_LAST_DEFINED 1 +#define XED_IFORMFL_WRSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_WRSSD_LAST_DEFINED 1 +#define XED_IFORMFL_WRSSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_WRSSQ_LAST_DEFINED 1 +#define XED_IFORMFL_WRUSSD_FIRST_DEFINED 1 +#define XED_IFORMFL_WRUSSD_LAST_DEFINED 1 +#define XED_IFORMFL_WRUSSQ_FIRST_DEFINED 1 +#define XED_IFORMFL_WRUSSQ_LAST_DEFINED 1 +#define XED_IFORMFL_XABORT_FIRST_DEFINED 1 +#define XED_IFORMFL_XABORT_LAST_DEFINED 1 +#define XED_IFORMFL_XADD_FIRST_DEFINED 1 +#define XED_IFORMFL_XADD_LAST_DEFINED 1 +#define XED_IFORMFL_XADD_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_XADD_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_XBEGIN_FIRST_DEFINED 1 +#define XED_IFORMFL_XBEGIN_LAST_DEFINED 1 +#define XED_IFORMFL_XCHG_FIRST_DEFINED 1 +#define XED_IFORMFL_XCHG_LAST_DEFINED 1 +#define XED_IFORMFL_XEND_FIRST_DEFINED 1 +#define XED_IFORMFL_XEND_LAST_DEFINED 1 +#define XED_IFORMFL_XGETBV_FIRST_DEFINED 1 +#define XED_IFORMFL_XGETBV_LAST_DEFINED 1 +#define XED_IFORMFL_XLAT_FIRST_DEFINED 1 +#define XED_IFORMFL_XLAT_LAST_DEFINED 1 +#define XED_IFORMFL_XOR_FIRST_DEFINED 1 +#define XED_IFORMFL_XOR_LAST_DEFINED 1 +#define XED_IFORMFL_XORPD_FIRST_DEFINED 1 +#define XED_IFORMFL_XORPD_LAST_DEFINED 1 +#define XED_IFORMFL_XORPS_FIRST_DEFINED 1 +#define XED_IFORMFL_XORPS_LAST_DEFINED 1 +#define XED_IFORMFL_XOR_LOCK_FIRST_DEFINED 1 +#define XED_IFORMFL_XOR_LOCK_LAST_DEFINED 1 +#define XED_IFORMFL_XRESLDTRK_FIRST_DEFINED 1 +#define XED_IFORMFL_XRESLDTRK_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTOR_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTOR_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTOR64_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTOR64_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTORS_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTORS_LAST_DEFINED 1 +#define XED_IFORMFL_XRSTORS64_FIRST_DEFINED 1 +#define XED_IFORMFL_XRSTORS64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVE_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVE_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVE64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVE64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEC_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEC_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEC64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEC64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVEOPT64_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVES_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVES_LAST_DEFINED 1 +#define XED_IFORMFL_XSAVES64_FIRST_DEFINED 1 +#define XED_IFORMFL_XSAVES64_LAST_DEFINED 1 +#define XED_IFORMFL_XSETBV_FIRST_DEFINED 1 +#define XED_IFORMFL_XSETBV_LAST_DEFINED 1 +#define XED_IFORMFL_XSTORE_FIRST_DEFINED 1 +#define XED_IFORMFL_XSTORE_LAST_DEFINED 1 +#define XED_IFORMFL_XSUSLDTRK_FIRST_DEFINED 1 +#define XED_IFORMFL_XSUSLDTRK_LAST_DEFINED 1 +#define XED_IFORMFL_XTEST_FIRST_DEFINED 1 +#define XED_IFORMFL_XTEST_LAST_DEFINED 1 +#define XED_IFORMFL_LAST_DEFINED 1 +typedef enum { + XED_IFORMFL_AAA_FIRST=1, + XED_IFORMFL_AAA_LAST=1, + XED_IFORMFL_AAD_FIRST=2, + XED_IFORMFL_AAD_LAST=2, + XED_IFORMFL_AAM_FIRST=3, + XED_IFORMFL_AAM_LAST=3, + XED_IFORMFL_AAS_FIRST=4, + XED_IFORMFL_AAS_LAST=4, + XED_IFORMFL_ADC_FIRST=5, + XED_IFORMFL_ADC_LAST=22, + XED_IFORMFL_ADCX_FIRST=23, + XED_IFORMFL_ADCX_LAST=26, + XED_IFORMFL_ADC_LOCK_FIRST=27, + XED_IFORMFL_ADC_LOCK_LAST=32, + XED_IFORMFL_ADD_FIRST=33, + XED_IFORMFL_ADD_LAST=50, + XED_IFORMFL_ADDPD_FIRST=51, + XED_IFORMFL_ADDPD_LAST=52, + XED_IFORMFL_ADDPS_FIRST=53, + XED_IFORMFL_ADDPS_LAST=54, + XED_IFORMFL_ADDSD_FIRST=55, + XED_IFORMFL_ADDSD_LAST=56, + XED_IFORMFL_ADDSS_FIRST=57, + XED_IFORMFL_ADDSS_LAST=58, + XED_IFORMFL_ADDSUBPD_FIRST=59, + XED_IFORMFL_ADDSUBPD_LAST=60, + XED_IFORMFL_ADDSUBPS_FIRST=61, + XED_IFORMFL_ADDSUBPS_LAST=62, + XED_IFORMFL_ADD_LOCK_FIRST=63, + XED_IFORMFL_ADD_LOCK_LAST=68, + XED_IFORMFL_ADOX_FIRST=69, + XED_IFORMFL_ADOX_LAST=72, + XED_IFORMFL_AESDEC_FIRST=73, + XED_IFORMFL_AESDEC_LAST=74, + XED_IFORMFL_AESDEC128KL_FIRST=75, + XED_IFORMFL_AESDEC128KL_LAST=75, + XED_IFORMFL_AESDEC256KL_FIRST=76, + XED_IFORMFL_AESDEC256KL_LAST=76, + XED_IFORMFL_AESDECLAST_FIRST=77, + XED_IFORMFL_AESDECLAST_LAST=78, + XED_IFORMFL_AESDECWIDE128KL_FIRST=79, + XED_IFORMFL_AESDECWIDE128KL_LAST=79, + XED_IFORMFL_AESDECWIDE256KL_FIRST=80, + XED_IFORMFL_AESDECWIDE256KL_LAST=80, + XED_IFORMFL_AESENC_FIRST=81, + XED_IFORMFL_AESENC_LAST=82, + XED_IFORMFL_AESENC128KL_FIRST=83, + XED_IFORMFL_AESENC128KL_LAST=83, + XED_IFORMFL_AESENC256KL_FIRST=84, + XED_IFORMFL_AESENC256KL_LAST=84, + XED_IFORMFL_AESENCLAST_FIRST=85, + XED_IFORMFL_AESENCLAST_LAST=86, + XED_IFORMFL_AESENCWIDE128KL_FIRST=87, + XED_IFORMFL_AESENCWIDE128KL_LAST=87, + XED_IFORMFL_AESENCWIDE256KL_FIRST=88, + XED_IFORMFL_AESENCWIDE256KL_LAST=88, + XED_IFORMFL_AESIMC_FIRST=89, + XED_IFORMFL_AESIMC_LAST=90, + XED_IFORMFL_AESKEYGENASSIST_FIRST=91, + XED_IFORMFL_AESKEYGENASSIST_LAST=92, + XED_IFORMFL_AND_FIRST=93, + XED_IFORMFL_AND_LAST=110, + XED_IFORMFL_ANDN_FIRST=111, + XED_IFORMFL_ANDN_LAST=114, + XED_IFORMFL_ANDNPD_FIRST=115, + XED_IFORMFL_ANDNPD_LAST=116, + XED_IFORMFL_ANDNPS_FIRST=117, + XED_IFORMFL_ANDNPS_LAST=118, + XED_IFORMFL_ANDPD_FIRST=119, + XED_IFORMFL_ANDPD_LAST=120, + XED_IFORMFL_ANDPS_FIRST=121, + XED_IFORMFL_ANDPS_LAST=122, + XED_IFORMFL_AND_LOCK_FIRST=123, + XED_IFORMFL_AND_LOCK_LAST=128, + XED_IFORMFL_ARPL_FIRST=129, + XED_IFORMFL_ARPL_LAST=130, + XED_IFORMFL_BEXTR_FIRST=131, + XED_IFORMFL_BEXTR_LAST=134, + XED_IFORMFL_BEXTR_XOP_FIRST=135, + XED_IFORMFL_BEXTR_XOP_LAST=138, + XED_IFORMFL_BLCFILL_FIRST=139, + XED_IFORMFL_BLCFILL_LAST=142, + XED_IFORMFL_BLCI_FIRST=143, + XED_IFORMFL_BLCI_LAST=146, + XED_IFORMFL_BLCIC_FIRST=147, + XED_IFORMFL_BLCIC_LAST=150, + XED_IFORMFL_BLCMSK_FIRST=151, + XED_IFORMFL_BLCMSK_LAST=154, + XED_IFORMFL_BLCS_FIRST=155, + XED_IFORMFL_BLCS_LAST=158, + XED_IFORMFL_BLENDPD_FIRST=159, + XED_IFORMFL_BLENDPD_LAST=160, + XED_IFORMFL_BLENDPS_FIRST=161, + XED_IFORMFL_BLENDPS_LAST=162, + XED_IFORMFL_BLENDVPD_FIRST=163, + XED_IFORMFL_BLENDVPD_LAST=164, + XED_IFORMFL_BLENDVPS_FIRST=165, + XED_IFORMFL_BLENDVPS_LAST=166, + XED_IFORMFL_BLSFILL_FIRST=167, + XED_IFORMFL_BLSFILL_LAST=170, + XED_IFORMFL_BLSI_FIRST=171, + XED_IFORMFL_BLSI_LAST=174, + XED_IFORMFL_BLSIC_FIRST=175, + XED_IFORMFL_BLSIC_LAST=178, + XED_IFORMFL_BLSMSK_FIRST=179, + XED_IFORMFL_BLSMSK_LAST=182, + XED_IFORMFL_BLSR_FIRST=183, + XED_IFORMFL_BLSR_LAST=186, + XED_IFORMFL_BNDCL_FIRST=187, + XED_IFORMFL_BNDCL_LAST=189, + XED_IFORMFL_BNDCN_FIRST=190, + XED_IFORMFL_BNDCN_LAST=192, + XED_IFORMFL_BNDCU_FIRST=193, + XED_IFORMFL_BNDCU_LAST=195, + XED_IFORMFL_BNDLDX_FIRST=196, + XED_IFORMFL_BNDLDX_LAST=197, + XED_IFORMFL_BNDMK_FIRST=198, + XED_IFORMFL_BNDMK_LAST=198, + XED_IFORMFL_BNDMOV_FIRST=199, + XED_IFORMFL_BNDMOV_LAST=203, + XED_IFORMFL_BNDSTX_FIRST=204, + XED_IFORMFL_BNDSTX_LAST=205, + XED_IFORMFL_BOUND_FIRST=206, + XED_IFORMFL_BOUND_LAST=207, + XED_IFORMFL_BSF_FIRST=208, + XED_IFORMFL_BSF_LAST=209, + XED_IFORMFL_BSR_FIRST=210, + XED_IFORMFL_BSR_LAST=211, + XED_IFORMFL_BSWAP_FIRST=212, + XED_IFORMFL_BSWAP_LAST=212, + XED_IFORMFL_BT_FIRST=213, + XED_IFORMFL_BT_LAST=216, + XED_IFORMFL_BTC_FIRST=217, + XED_IFORMFL_BTC_LAST=220, + XED_IFORMFL_BTC_LOCK_FIRST=221, + XED_IFORMFL_BTC_LOCK_LAST=222, + XED_IFORMFL_BTR_FIRST=223, + XED_IFORMFL_BTR_LAST=226, + XED_IFORMFL_BTR_LOCK_FIRST=227, + XED_IFORMFL_BTR_LOCK_LAST=228, + XED_IFORMFL_BTS_FIRST=229, + XED_IFORMFL_BTS_LAST=232, + XED_IFORMFL_BTS_LOCK_FIRST=233, + XED_IFORMFL_BTS_LOCK_LAST=234, + XED_IFORMFL_BZHI_FIRST=235, + XED_IFORMFL_BZHI_LAST=238, + XED_IFORMFL_CALL_FAR_FIRST=239, + XED_IFORMFL_CALL_FAR_LAST=240, + XED_IFORMFL_CALL_NEAR_FIRST=241, + XED_IFORMFL_CALL_NEAR_LAST=244, + XED_IFORMFL_CBW_FIRST=245, + XED_IFORMFL_CBW_LAST=245, + XED_IFORMFL_CDQ_FIRST=246, + XED_IFORMFL_CDQ_LAST=246, + XED_IFORMFL_CDQE_FIRST=247, + XED_IFORMFL_CDQE_LAST=247, + XED_IFORMFL_CLAC_FIRST=248, + XED_IFORMFL_CLAC_LAST=248, + XED_IFORMFL_CLC_FIRST=249, + XED_IFORMFL_CLC_LAST=249, + XED_IFORMFL_CLD_FIRST=250, + XED_IFORMFL_CLD_LAST=250, + XED_IFORMFL_CLDEMOTE_FIRST=251, + XED_IFORMFL_CLDEMOTE_LAST=251, + XED_IFORMFL_CLFLUSH_FIRST=252, + XED_IFORMFL_CLFLUSH_LAST=252, + XED_IFORMFL_CLFLUSHOPT_FIRST=253, + XED_IFORMFL_CLFLUSHOPT_LAST=253, + XED_IFORMFL_CLGI_FIRST=254, + XED_IFORMFL_CLGI_LAST=254, + XED_IFORMFL_CLI_FIRST=255, + XED_IFORMFL_CLI_LAST=255, + XED_IFORMFL_CLRSSBSY_FIRST=256, + XED_IFORMFL_CLRSSBSY_LAST=256, + XED_IFORMFL_CLTS_FIRST=257, + XED_IFORMFL_CLTS_LAST=257, + XED_IFORMFL_CLUI_FIRST=258, + XED_IFORMFL_CLUI_LAST=258, + XED_IFORMFL_CLWB_FIRST=259, + XED_IFORMFL_CLWB_LAST=259, + XED_IFORMFL_CLZERO_FIRST=260, + XED_IFORMFL_CLZERO_LAST=260, + XED_IFORMFL_CMC_FIRST=261, + XED_IFORMFL_CMC_LAST=261, + XED_IFORMFL_CMOVB_FIRST=262, + XED_IFORMFL_CMOVB_LAST=263, + XED_IFORMFL_CMOVBE_FIRST=264, + XED_IFORMFL_CMOVBE_LAST=265, + XED_IFORMFL_CMOVL_FIRST=266, + XED_IFORMFL_CMOVL_LAST=267, + XED_IFORMFL_CMOVLE_FIRST=268, + XED_IFORMFL_CMOVLE_LAST=269, + XED_IFORMFL_CMOVNB_FIRST=270, + XED_IFORMFL_CMOVNB_LAST=271, + XED_IFORMFL_CMOVNBE_FIRST=272, + XED_IFORMFL_CMOVNBE_LAST=273, + XED_IFORMFL_CMOVNL_FIRST=274, + XED_IFORMFL_CMOVNL_LAST=275, + XED_IFORMFL_CMOVNLE_FIRST=276, + XED_IFORMFL_CMOVNLE_LAST=277, + XED_IFORMFL_CMOVNO_FIRST=278, + XED_IFORMFL_CMOVNO_LAST=279, + XED_IFORMFL_CMOVNP_FIRST=280, + XED_IFORMFL_CMOVNP_LAST=281, + XED_IFORMFL_CMOVNS_FIRST=282, + XED_IFORMFL_CMOVNS_LAST=283, + XED_IFORMFL_CMOVNZ_FIRST=284, + XED_IFORMFL_CMOVNZ_LAST=285, + XED_IFORMFL_CMOVO_FIRST=286, + XED_IFORMFL_CMOVO_LAST=287, + XED_IFORMFL_CMOVP_FIRST=288, + XED_IFORMFL_CMOVP_LAST=289, + XED_IFORMFL_CMOVS_FIRST=290, + XED_IFORMFL_CMOVS_LAST=291, + XED_IFORMFL_CMOVZ_FIRST=292, + XED_IFORMFL_CMOVZ_LAST=293, + XED_IFORMFL_CMP_FIRST=294, + XED_IFORMFL_CMP_LAST=311, + XED_IFORMFL_CMPPD_FIRST=312, + XED_IFORMFL_CMPPD_LAST=313, + XED_IFORMFL_CMPPS_FIRST=314, + XED_IFORMFL_CMPPS_LAST=315, + XED_IFORMFL_CMPSB_FIRST=316, + XED_IFORMFL_CMPSB_LAST=316, + XED_IFORMFL_CMPSD_FIRST=317, + XED_IFORMFL_CMPSD_LAST=317, + XED_IFORMFL_CMPSD_XMM_FIRST=318, + XED_IFORMFL_CMPSD_XMM_LAST=319, + XED_IFORMFL_CMPSQ_FIRST=320, + XED_IFORMFL_CMPSQ_LAST=320, + XED_IFORMFL_CMPSS_FIRST=321, + XED_IFORMFL_CMPSS_LAST=322, + XED_IFORMFL_CMPSW_FIRST=323, + XED_IFORMFL_CMPSW_LAST=323, + XED_IFORMFL_CMPXCHG_FIRST=324, + XED_IFORMFL_CMPXCHG_LAST=327, + XED_IFORMFL_CMPXCHG16B_FIRST=328, + XED_IFORMFL_CMPXCHG16B_LAST=328, + XED_IFORMFL_CMPXCHG16B_LOCK_FIRST=329, + XED_IFORMFL_CMPXCHG16B_LOCK_LAST=329, + XED_IFORMFL_CMPXCHG8B_FIRST=330, + XED_IFORMFL_CMPXCHG8B_LAST=330, + XED_IFORMFL_CMPXCHG8B_LOCK_FIRST=331, + XED_IFORMFL_CMPXCHG8B_LOCK_LAST=331, + XED_IFORMFL_CMPXCHG_LOCK_FIRST=332, + XED_IFORMFL_CMPXCHG_LOCK_LAST=333, + XED_IFORMFL_COMISD_FIRST=334, + XED_IFORMFL_COMISD_LAST=335, + XED_IFORMFL_COMISS_FIRST=336, + XED_IFORMFL_COMISS_LAST=337, + XED_IFORMFL_CPUID_FIRST=338, + XED_IFORMFL_CPUID_LAST=338, + XED_IFORMFL_CQO_FIRST=339, + XED_IFORMFL_CQO_LAST=339, + XED_IFORMFL_CRC32_FIRST=340, + XED_IFORMFL_CRC32_LAST=343, + XED_IFORMFL_CVTDQ2PD_FIRST=344, + XED_IFORMFL_CVTDQ2PD_LAST=345, + XED_IFORMFL_CVTDQ2PS_FIRST=346, + XED_IFORMFL_CVTDQ2PS_LAST=347, + XED_IFORMFL_CVTPD2DQ_FIRST=348, + XED_IFORMFL_CVTPD2DQ_LAST=349, + XED_IFORMFL_CVTPD2PI_FIRST=350, + XED_IFORMFL_CVTPD2PI_LAST=351, + XED_IFORMFL_CVTPD2PS_FIRST=352, + XED_IFORMFL_CVTPD2PS_LAST=353, + XED_IFORMFL_CVTPI2PD_FIRST=354, + XED_IFORMFL_CVTPI2PD_LAST=355, + XED_IFORMFL_CVTPI2PS_FIRST=356, + XED_IFORMFL_CVTPI2PS_LAST=357, + XED_IFORMFL_CVTPS2DQ_FIRST=358, + XED_IFORMFL_CVTPS2DQ_LAST=359, + XED_IFORMFL_CVTPS2PD_FIRST=360, + XED_IFORMFL_CVTPS2PD_LAST=361, + XED_IFORMFL_CVTPS2PI_FIRST=362, + XED_IFORMFL_CVTPS2PI_LAST=363, + XED_IFORMFL_CVTSD2SI_FIRST=364, + XED_IFORMFL_CVTSD2SI_LAST=367, + XED_IFORMFL_CVTSD2SS_FIRST=368, + XED_IFORMFL_CVTSD2SS_LAST=369, + XED_IFORMFL_CVTSI2SD_FIRST=370, + XED_IFORMFL_CVTSI2SD_LAST=373, + XED_IFORMFL_CVTSI2SS_FIRST=374, + XED_IFORMFL_CVTSI2SS_LAST=377, + XED_IFORMFL_CVTSS2SD_FIRST=378, + XED_IFORMFL_CVTSS2SD_LAST=379, + XED_IFORMFL_CVTSS2SI_FIRST=380, + XED_IFORMFL_CVTSS2SI_LAST=383, + XED_IFORMFL_CVTTPD2DQ_FIRST=384, + XED_IFORMFL_CVTTPD2DQ_LAST=385, + XED_IFORMFL_CVTTPD2PI_FIRST=386, + XED_IFORMFL_CVTTPD2PI_LAST=387, + XED_IFORMFL_CVTTPS2DQ_FIRST=388, + XED_IFORMFL_CVTTPS2DQ_LAST=389, + XED_IFORMFL_CVTTPS2PI_FIRST=390, + XED_IFORMFL_CVTTPS2PI_LAST=391, + XED_IFORMFL_CVTTSD2SI_FIRST=392, + XED_IFORMFL_CVTTSD2SI_LAST=395, + XED_IFORMFL_CVTTSS2SI_FIRST=396, + XED_IFORMFL_CVTTSS2SI_LAST=399, + XED_IFORMFL_CWD_FIRST=400, + XED_IFORMFL_CWD_LAST=400, + XED_IFORMFL_CWDE_FIRST=401, + XED_IFORMFL_CWDE_LAST=401, + XED_IFORMFL_DAA_FIRST=402, + XED_IFORMFL_DAA_LAST=402, + XED_IFORMFL_DAS_FIRST=403, + XED_IFORMFL_DAS_LAST=403, + XED_IFORMFL_DEC_FIRST=404, + XED_IFORMFL_DEC_LAST=408, + XED_IFORMFL_DEC_LOCK_FIRST=409, + XED_IFORMFL_DEC_LOCK_LAST=410, + XED_IFORMFL_DIV_FIRST=411, + XED_IFORMFL_DIV_LAST=414, + XED_IFORMFL_DIVPD_FIRST=415, + XED_IFORMFL_DIVPD_LAST=416, + XED_IFORMFL_DIVPS_FIRST=417, + XED_IFORMFL_DIVPS_LAST=418, + XED_IFORMFL_DIVSD_FIRST=419, + XED_IFORMFL_DIVSD_LAST=420, + XED_IFORMFL_DIVSS_FIRST=421, + XED_IFORMFL_DIVSS_LAST=422, + XED_IFORMFL_DPPD_FIRST=423, + XED_IFORMFL_DPPD_LAST=424, + XED_IFORMFL_DPPS_FIRST=425, + XED_IFORMFL_DPPS_LAST=426, + XED_IFORMFL_EMMS_FIRST=427, + XED_IFORMFL_EMMS_LAST=427, + XED_IFORMFL_ENCLS_FIRST=428, + XED_IFORMFL_ENCLS_LAST=428, + XED_IFORMFL_ENCLU_FIRST=429, + XED_IFORMFL_ENCLU_LAST=429, + XED_IFORMFL_ENCLV_FIRST=430, + XED_IFORMFL_ENCLV_LAST=430, + XED_IFORMFL_ENCODEKEY128_FIRST=431, + XED_IFORMFL_ENCODEKEY128_LAST=431, + XED_IFORMFL_ENCODEKEY256_FIRST=432, + XED_IFORMFL_ENCODEKEY256_LAST=432, + XED_IFORMFL_ENDBR32_FIRST=433, + XED_IFORMFL_ENDBR32_LAST=433, + XED_IFORMFL_ENDBR64_FIRST=434, + XED_IFORMFL_ENDBR64_LAST=434, + XED_IFORMFL_ENQCMD_FIRST=435, + XED_IFORMFL_ENQCMD_LAST=435, + XED_IFORMFL_ENQCMDS_FIRST=436, + XED_IFORMFL_ENQCMDS_LAST=436, + XED_IFORMFL_ENTER_FIRST=437, + XED_IFORMFL_ENTER_LAST=437, + XED_IFORMFL_EXTRACTPS_FIRST=438, + XED_IFORMFL_EXTRACTPS_LAST=439, + XED_IFORMFL_EXTRQ_FIRST=440, + XED_IFORMFL_EXTRQ_LAST=441, + XED_IFORMFL_F2XM1_FIRST=442, + XED_IFORMFL_F2XM1_LAST=442, + XED_IFORMFL_FABS_FIRST=443, + XED_IFORMFL_FABS_LAST=443, + XED_IFORMFL_FADD_FIRST=444, + XED_IFORMFL_FADD_LAST=447, + XED_IFORMFL_FADDP_FIRST=448, + XED_IFORMFL_FADDP_LAST=448, + XED_IFORMFL_FBLD_FIRST=449, + XED_IFORMFL_FBLD_LAST=449, + XED_IFORMFL_FBSTP_FIRST=450, + XED_IFORMFL_FBSTP_LAST=450, + XED_IFORMFL_FCHS_FIRST=451, + XED_IFORMFL_FCHS_LAST=451, + XED_IFORMFL_FCMOVB_FIRST=452, + XED_IFORMFL_FCMOVB_LAST=452, + XED_IFORMFL_FCMOVBE_FIRST=453, + XED_IFORMFL_FCMOVBE_LAST=453, + XED_IFORMFL_FCMOVE_FIRST=454, + XED_IFORMFL_FCMOVE_LAST=454, + XED_IFORMFL_FCMOVNB_FIRST=455, + XED_IFORMFL_FCMOVNB_LAST=455, + XED_IFORMFL_FCMOVNBE_FIRST=456, + XED_IFORMFL_FCMOVNBE_LAST=456, + XED_IFORMFL_FCMOVNE_FIRST=457, + XED_IFORMFL_FCMOVNE_LAST=457, + XED_IFORMFL_FCMOVNU_FIRST=458, + XED_IFORMFL_FCMOVNU_LAST=458, + XED_IFORMFL_FCMOVU_FIRST=459, + XED_IFORMFL_FCMOVU_LAST=459, + XED_IFORMFL_FCOM_FIRST=460, + XED_IFORMFL_FCOM_LAST=463, + XED_IFORMFL_FCOMI_FIRST=464, + XED_IFORMFL_FCOMI_LAST=464, + XED_IFORMFL_FCOMIP_FIRST=465, + XED_IFORMFL_FCOMIP_LAST=465, + XED_IFORMFL_FCOMP_FIRST=466, + XED_IFORMFL_FCOMP_LAST=470, + XED_IFORMFL_FCOMPP_FIRST=471, + XED_IFORMFL_FCOMPP_LAST=471, + XED_IFORMFL_FCOS_FIRST=472, + XED_IFORMFL_FCOS_LAST=472, + XED_IFORMFL_FDECSTP_FIRST=473, + XED_IFORMFL_FDECSTP_LAST=473, + XED_IFORMFL_FDISI8087_NOP_FIRST=474, + XED_IFORMFL_FDISI8087_NOP_LAST=474, + XED_IFORMFL_FDIV_FIRST=475, + XED_IFORMFL_FDIV_LAST=478, + XED_IFORMFL_FDIVP_FIRST=479, + XED_IFORMFL_FDIVP_LAST=479, + XED_IFORMFL_FDIVR_FIRST=480, + XED_IFORMFL_FDIVR_LAST=483, + XED_IFORMFL_FDIVRP_FIRST=484, + XED_IFORMFL_FDIVRP_LAST=484, + XED_IFORMFL_FEMMS_FIRST=485, + XED_IFORMFL_FEMMS_LAST=485, + XED_IFORMFL_FENI8087_NOP_FIRST=486, + XED_IFORMFL_FENI8087_NOP_LAST=486, + XED_IFORMFL_FFREE_FIRST=487, + XED_IFORMFL_FFREE_LAST=487, + XED_IFORMFL_FFREEP_FIRST=488, + XED_IFORMFL_FFREEP_LAST=488, + XED_IFORMFL_FIADD_FIRST=489, + XED_IFORMFL_FIADD_LAST=490, + XED_IFORMFL_FICOM_FIRST=491, + XED_IFORMFL_FICOM_LAST=492, + XED_IFORMFL_FICOMP_FIRST=493, + XED_IFORMFL_FICOMP_LAST=494, + XED_IFORMFL_FIDIV_FIRST=495, + XED_IFORMFL_FIDIV_LAST=496, + XED_IFORMFL_FIDIVR_FIRST=497, + XED_IFORMFL_FIDIVR_LAST=498, + XED_IFORMFL_FILD_FIRST=499, + XED_IFORMFL_FILD_LAST=501, + XED_IFORMFL_FIMUL_FIRST=502, + XED_IFORMFL_FIMUL_LAST=503, + XED_IFORMFL_FINCSTP_FIRST=504, + XED_IFORMFL_FINCSTP_LAST=504, + XED_IFORMFL_FIST_FIRST=505, + XED_IFORMFL_FIST_LAST=506, + XED_IFORMFL_FISTP_FIRST=507, + XED_IFORMFL_FISTP_LAST=509, + XED_IFORMFL_FISTTP_FIRST=510, + XED_IFORMFL_FISTTP_LAST=512, + XED_IFORMFL_FISUB_FIRST=513, + XED_IFORMFL_FISUB_LAST=514, + XED_IFORMFL_FISUBR_FIRST=515, + XED_IFORMFL_FISUBR_LAST=516, + XED_IFORMFL_FLD_FIRST=517, + XED_IFORMFL_FLD_LAST=520, + XED_IFORMFL_FLD1_FIRST=521, + XED_IFORMFL_FLD1_LAST=521, + XED_IFORMFL_FLDCW_FIRST=522, + XED_IFORMFL_FLDCW_LAST=522, + XED_IFORMFL_FLDENV_FIRST=523, + XED_IFORMFL_FLDENV_LAST=524, + XED_IFORMFL_FLDL2E_FIRST=525, + XED_IFORMFL_FLDL2E_LAST=525, + XED_IFORMFL_FLDL2T_FIRST=526, + XED_IFORMFL_FLDL2T_LAST=526, + XED_IFORMFL_FLDLG2_FIRST=527, + XED_IFORMFL_FLDLG2_LAST=527, + XED_IFORMFL_FLDLN2_FIRST=528, + XED_IFORMFL_FLDLN2_LAST=528, + XED_IFORMFL_FLDPI_FIRST=529, + XED_IFORMFL_FLDPI_LAST=529, + XED_IFORMFL_FLDZ_FIRST=530, + XED_IFORMFL_FLDZ_LAST=530, + XED_IFORMFL_FMUL_FIRST=531, + XED_IFORMFL_FMUL_LAST=534, + XED_IFORMFL_FMULP_FIRST=535, + XED_IFORMFL_FMULP_LAST=535, + XED_IFORMFL_FNCLEX_FIRST=536, + XED_IFORMFL_FNCLEX_LAST=536, + XED_IFORMFL_FNINIT_FIRST=537, + XED_IFORMFL_FNINIT_LAST=537, + XED_IFORMFL_FNOP_FIRST=538, + XED_IFORMFL_FNOP_LAST=538, + XED_IFORMFL_FNSAVE_FIRST=539, + XED_IFORMFL_FNSAVE_LAST=540, + XED_IFORMFL_FNSTCW_FIRST=541, + XED_IFORMFL_FNSTCW_LAST=541, + XED_IFORMFL_FNSTENV_FIRST=542, + XED_IFORMFL_FNSTENV_LAST=543, + XED_IFORMFL_FNSTSW_FIRST=544, + XED_IFORMFL_FNSTSW_LAST=545, + XED_IFORMFL_FPATAN_FIRST=546, + XED_IFORMFL_FPATAN_LAST=546, + XED_IFORMFL_FPREM_FIRST=547, + XED_IFORMFL_FPREM_LAST=547, + XED_IFORMFL_FPREM1_FIRST=548, + XED_IFORMFL_FPREM1_LAST=548, + XED_IFORMFL_FPTAN_FIRST=549, + XED_IFORMFL_FPTAN_LAST=549, + XED_IFORMFL_FRNDINT_FIRST=550, + XED_IFORMFL_FRNDINT_LAST=550, + XED_IFORMFL_FRSTOR_FIRST=551, + XED_IFORMFL_FRSTOR_LAST=552, + XED_IFORMFL_FSCALE_FIRST=553, + XED_IFORMFL_FSCALE_LAST=553, + XED_IFORMFL_FSETPM287_NOP_FIRST=554, + XED_IFORMFL_FSETPM287_NOP_LAST=554, + XED_IFORMFL_FSIN_FIRST=555, + XED_IFORMFL_FSIN_LAST=555, + XED_IFORMFL_FSINCOS_FIRST=556, + XED_IFORMFL_FSINCOS_LAST=556, + XED_IFORMFL_FSQRT_FIRST=557, + XED_IFORMFL_FSQRT_LAST=557, + XED_IFORMFL_FST_FIRST=558, + XED_IFORMFL_FST_LAST=560, + XED_IFORMFL_FSTP_FIRST=561, + XED_IFORMFL_FSTP_LAST=566, + XED_IFORMFL_FSTPNCE_FIRST=567, + XED_IFORMFL_FSTPNCE_LAST=567, + XED_IFORMFL_FSUB_FIRST=568, + XED_IFORMFL_FSUB_LAST=571, + XED_IFORMFL_FSUBP_FIRST=572, + XED_IFORMFL_FSUBP_LAST=572, + XED_IFORMFL_FSUBR_FIRST=573, + XED_IFORMFL_FSUBR_LAST=576, + XED_IFORMFL_FSUBRP_FIRST=577, + XED_IFORMFL_FSUBRP_LAST=577, + XED_IFORMFL_FTST_FIRST=578, + XED_IFORMFL_FTST_LAST=578, + XED_IFORMFL_FUCOM_FIRST=579, + XED_IFORMFL_FUCOM_LAST=579, + XED_IFORMFL_FUCOMI_FIRST=580, + XED_IFORMFL_FUCOMI_LAST=580, + XED_IFORMFL_FUCOMIP_FIRST=581, + XED_IFORMFL_FUCOMIP_LAST=581, + XED_IFORMFL_FUCOMP_FIRST=582, + XED_IFORMFL_FUCOMP_LAST=582, + XED_IFORMFL_FUCOMPP_FIRST=583, + XED_IFORMFL_FUCOMPP_LAST=583, + XED_IFORMFL_FWAIT_FIRST=584, + XED_IFORMFL_FWAIT_LAST=584, + XED_IFORMFL_FXAM_FIRST=585, + XED_IFORMFL_FXAM_LAST=585, + XED_IFORMFL_FXCH_FIRST=586, + XED_IFORMFL_FXCH_LAST=588, + XED_IFORMFL_FXRSTOR_FIRST=589, + XED_IFORMFL_FXRSTOR_LAST=589, + XED_IFORMFL_FXRSTOR64_FIRST=590, + XED_IFORMFL_FXRSTOR64_LAST=590, + XED_IFORMFL_FXSAVE_FIRST=591, + XED_IFORMFL_FXSAVE_LAST=591, + XED_IFORMFL_FXSAVE64_FIRST=592, + XED_IFORMFL_FXSAVE64_LAST=592, + XED_IFORMFL_FXTRACT_FIRST=593, + XED_IFORMFL_FXTRACT_LAST=593, + XED_IFORMFL_FYL2X_FIRST=594, + XED_IFORMFL_FYL2X_LAST=594, + XED_IFORMFL_FYL2XP1_FIRST=595, + XED_IFORMFL_FYL2XP1_LAST=595, + XED_IFORMFL_GETSEC_FIRST=596, + XED_IFORMFL_GETSEC_LAST=596, + XED_IFORMFL_GF2P8AFFINEINVQB_FIRST=597, + XED_IFORMFL_GF2P8AFFINEINVQB_LAST=598, + XED_IFORMFL_GF2P8AFFINEQB_FIRST=599, + XED_IFORMFL_GF2P8AFFINEQB_LAST=600, + XED_IFORMFL_GF2P8MULB_FIRST=601, + XED_IFORMFL_GF2P8MULB_LAST=602, + XED_IFORMFL_HADDPD_FIRST=603, + XED_IFORMFL_HADDPD_LAST=604, + XED_IFORMFL_HADDPS_FIRST=605, + XED_IFORMFL_HADDPS_LAST=606, + XED_IFORMFL_HLT_FIRST=607, + XED_IFORMFL_HLT_LAST=607, + XED_IFORMFL_HRESET_FIRST=608, + XED_IFORMFL_HRESET_LAST=608, + XED_IFORMFL_HSUBPD_FIRST=609, + XED_IFORMFL_HSUBPD_LAST=610, + XED_IFORMFL_HSUBPS_FIRST=611, + XED_IFORMFL_HSUBPS_LAST=612, + XED_IFORMFL_IDIV_FIRST=613, + XED_IFORMFL_IDIV_LAST=616, + XED_IFORMFL_IMUL_FIRST=617, + XED_IFORMFL_IMUL_LAST=626, + XED_IFORMFL_IN_FIRST=627, + XED_IFORMFL_IN_LAST=630, + XED_IFORMFL_INC_FIRST=631, + XED_IFORMFL_INC_LAST=635, + XED_IFORMFL_INCSSPD_FIRST=636, + XED_IFORMFL_INCSSPD_LAST=636, + XED_IFORMFL_INCSSPQ_FIRST=637, + XED_IFORMFL_INCSSPQ_LAST=637, + XED_IFORMFL_INC_LOCK_FIRST=638, + XED_IFORMFL_INC_LOCK_LAST=639, + XED_IFORMFL_INSB_FIRST=640, + XED_IFORMFL_INSB_LAST=640, + XED_IFORMFL_INSD_FIRST=641, + XED_IFORMFL_INSD_LAST=641, + XED_IFORMFL_INSERTPS_FIRST=642, + XED_IFORMFL_INSERTPS_LAST=643, + XED_IFORMFL_INSERTQ_FIRST=644, + XED_IFORMFL_INSERTQ_LAST=645, + XED_IFORMFL_INSW_FIRST=646, + XED_IFORMFL_INSW_LAST=646, + XED_IFORMFL_INT_FIRST=647, + XED_IFORMFL_INT_LAST=647, + XED_IFORMFL_INT1_FIRST=648, + XED_IFORMFL_INT1_LAST=648, + XED_IFORMFL_INT3_FIRST=649, + XED_IFORMFL_INT3_LAST=649, + XED_IFORMFL_INTO_FIRST=650, + XED_IFORMFL_INTO_LAST=650, + XED_IFORMFL_INVD_FIRST=651, + XED_IFORMFL_INVD_LAST=651, + XED_IFORMFL_INVEPT_FIRST=652, + XED_IFORMFL_INVEPT_LAST=653, + XED_IFORMFL_INVLPG_FIRST=654, + XED_IFORMFL_INVLPG_LAST=654, + XED_IFORMFL_INVLPGA_FIRST=655, + XED_IFORMFL_INVLPGA_LAST=655, + XED_IFORMFL_INVLPGB_FIRST=656, + XED_IFORMFL_INVLPGB_LAST=657, + XED_IFORMFL_INVPCID_FIRST=658, + XED_IFORMFL_INVPCID_LAST=659, + XED_IFORMFL_INVVPID_FIRST=660, + XED_IFORMFL_INVVPID_LAST=661, + XED_IFORMFL_IRET_FIRST=662, + XED_IFORMFL_IRET_LAST=662, + XED_IFORMFL_IRETD_FIRST=663, + XED_IFORMFL_IRETD_LAST=663, + XED_IFORMFL_IRETQ_FIRST=664, + XED_IFORMFL_IRETQ_LAST=664, + XED_IFORMFL_JB_FIRST=665, + XED_IFORMFL_JB_LAST=667, + XED_IFORMFL_JBE_FIRST=668, + XED_IFORMFL_JBE_LAST=670, + XED_IFORMFL_JCXZ_FIRST=671, + XED_IFORMFL_JCXZ_LAST=671, + XED_IFORMFL_JECXZ_FIRST=672, + XED_IFORMFL_JECXZ_LAST=672, + XED_IFORMFL_JL_FIRST=673, + XED_IFORMFL_JL_LAST=675, + XED_IFORMFL_JLE_FIRST=676, + XED_IFORMFL_JLE_LAST=678, + XED_IFORMFL_JMP_FIRST=679, + XED_IFORMFL_JMP_LAST=683, + XED_IFORMFL_JMP_FAR_FIRST=684, + XED_IFORMFL_JMP_FAR_LAST=685, + XED_IFORMFL_JNB_FIRST=686, + XED_IFORMFL_JNB_LAST=688, + XED_IFORMFL_JNBE_FIRST=689, + XED_IFORMFL_JNBE_LAST=691, + XED_IFORMFL_JNL_FIRST=692, + XED_IFORMFL_JNL_LAST=694, + XED_IFORMFL_JNLE_FIRST=695, + XED_IFORMFL_JNLE_LAST=697, + XED_IFORMFL_JNO_FIRST=698, + XED_IFORMFL_JNO_LAST=700, + XED_IFORMFL_JNP_FIRST=701, + XED_IFORMFL_JNP_LAST=703, + XED_IFORMFL_JNS_FIRST=704, + XED_IFORMFL_JNS_LAST=706, + XED_IFORMFL_JNZ_FIRST=707, + XED_IFORMFL_JNZ_LAST=709, + XED_IFORMFL_JO_FIRST=710, + XED_IFORMFL_JO_LAST=712, + XED_IFORMFL_JP_FIRST=713, + XED_IFORMFL_JP_LAST=715, + XED_IFORMFL_JRCXZ_FIRST=716, + XED_IFORMFL_JRCXZ_LAST=716, + XED_IFORMFL_JS_FIRST=717, + XED_IFORMFL_JS_LAST=719, + XED_IFORMFL_JZ_FIRST=720, + XED_IFORMFL_JZ_LAST=722, + XED_IFORMFL_KADDB_FIRST=723, + XED_IFORMFL_KADDB_LAST=723, + XED_IFORMFL_KADDD_FIRST=724, + XED_IFORMFL_KADDD_LAST=724, + XED_IFORMFL_KADDQ_FIRST=725, + XED_IFORMFL_KADDQ_LAST=725, + XED_IFORMFL_KADDW_FIRST=726, + XED_IFORMFL_KADDW_LAST=726, + XED_IFORMFL_KANDB_FIRST=727, + XED_IFORMFL_KANDB_LAST=727, + XED_IFORMFL_KANDD_FIRST=728, + XED_IFORMFL_KANDD_LAST=728, + XED_IFORMFL_KANDNB_FIRST=729, + XED_IFORMFL_KANDNB_LAST=729, + XED_IFORMFL_KANDND_FIRST=730, + XED_IFORMFL_KANDND_LAST=730, + XED_IFORMFL_KANDNQ_FIRST=731, + XED_IFORMFL_KANDNQ_LAST=731, + XED_IFORMFL_KANDNW_FIRST=732, + XED_IFORMFL_KANDNW_LAST=732, + XED_IFORMFL_KANDQ_FIRST=733, + XED_IFORMFL_KANDQ_LAST=733, + XED_IFORMFL_KANDW_FIRST=734, + XED_IFORMFL_KANDW_LAST=734, + XED_IFORMFL_KMOVB_FIRST=735, + XED_IFORMFL_KMOVB_LAST=739, + XED_IFORMFL_KMOVD_FIRST=740, + XED_IFORMFL_KMOVD_LAST=744, + XED_IFORMFL_KMOVQ_FIRST=745, + XED_IFORMFL_KMOVQ_LAST=749, + XED_IFORMFL_KMOVW_FIRST=750, + XED_IFORMFL_KMOVW_LAST=754, + XED_IFORMFL_KNOTB_FIRST=755, + XED_IFORMFL_KNOTB_LAST=755, + XED_IFORMFL_KNOTD_FIRST=756, + XED_IFORMFL_KNOTD_LAST=756, + XED_IFORMFL_KNOTQ_FIRST=757, + XED_IFORMFL_KNOTQ_LAST=757, + XED_IFORMFL_KNOTW_FIRST=758, + XED_IFORMFL_KNOTW_LAST=758, + XED_IFORMFL_KORB_FIRST=759, + XED_IFORMFL_KORB_LAST=759, + XED_IFORMFL_KORD_FIRST=760, + XED_IFORMFL_KORD_LAST=760, + XED_IFORMFL_KORQ_FIRST=761, + XED_IFORMFL_KORQ_LAST=761, + XED_IFORMFL_KORTESTB_FIRST=762, + XED_IFORMFL_KORTESTB_LAST=762, + XED_IFORMFL_KORTESTD_FIRST=763, + XED_IFORMFL_KORTESTD_LAST=763, + XED_IFORMFL_KORTESTQ_FIRST=764, + XED_IFORMFL_KORTESTQ_LAST=764, + XED_IFORMFL_KORTESTW_FIRST=765, + XED_IFORMFL_KORTESTW_LAST=765, + XED_IFORMFL_KORW_FIRST=766, + XED_IFORMFL_KORW_LAST=766, + XED_IFORMFL_KSHIFTLB_FIRST=767, + XED_IFORMFL_KSHIFTLB_LAST=767, + XED_IFORMFL_KSHIFTLD_FIRST=768, + XED_IFORMFL_KSHIFTLD_LAST=768, + XED_IFORMFL_KSHIFTLQ_FIRST=769, + XED_IFORMFL_KSHIFTLQ_LAST=769, + XED_IFORMFL_KSHIFTLW_FIRST=770, + XED_IFORMFL_KSHIFTLW_LAST=770, + XED_IFORMFL_KSHIFTRB_FIRST=771, + XED_IFORMFL_KSHIFTRB_LAST=771, + XED_IFORMFL_KSHIFTRD_FIRST=772, + XED_IFORMFL_KSHIFTRD_LAST=772, + XED_IFORMFL_KSHIFTRQ_FIRST=773, + XED_IFORMFL_KSHIFTRQ_LAST=773, + XED_IFORMFL_KSHIFTRW_FIRST=774, + XED_IFORMFL_KSHIFTRW_LAST=774, + XED_IFORMFL_KTESTB_FIRST=775, + XED_IFORMFL_KTESTB_LAST=775, + XED_IFORMFL_KTESTD_FIRST=776, + XED_IFORMFL_KTESTD_LAST=776, + XED_IFORMFL_KTESTQ_FIRST=777, + XED_IFORMFL_KTESTQ_LAST=777, + XED_IFORMFL_KTESTW_FIRST=778, + XED_IFORMFL_KTESTW_LAST=778, + XED_IFORMFL_KUNPCKBW_FIRST=779, + XED_IFORMFL_KUNPCKBW_LAST=779, + XED_IFORMFL_KUNPCKDQ_FIRST=780, + XED_IFORMFL_KUNPCKDQ_LAST=780, + XED_IFORMFL_KUNPCKWD_FIRST=781, + XED_IFORMFL_KUNPCKWD_LAST=781, + XED_IFORMFL_KXNORB_FIRST=782, + XED_IFORMFL_KXNORB_LAST=782, + XED_IFORMFL_KXNORD_FIRST=783, + XED_IFORMFL_KXNORD_LAST=783, + XED_IFORMFL_KXNORQ_FIRST=784, + XED_IFORMFL_KXNORQ_LAST=784, + XED_IFORMFL_KXNORW_FIRST=785, + XED_IFORMFL_KXNORW_LAST=785, + XED_IFORMFL_KXORB_FIRST=786, + XED_IFORMFL_KXORB_LAST=786, + XED_IFORMFL_KXORD_FIRST=787, + XED_IFORMFL_KXORD_LAST=787, + XED_IFORMFL_KXORQ_FIRST=788, + XED_IFORMFL_KXORQ_LAST=788, + XED_IFORMFL_KXORW_FIRST=789, + XED_IFORMFL_KXORW_LAST=789, + XED_IFORMFL_LAHF_FIRST=790, + XED_IFORMFL_LAHF_LAST=790, + XED_IFORMFL_LAR_FIRST=791, + XED_IFORMFL_LAR_LAST=792, + XED_IFORMFL_LDDQU_FIRST=793, + XED_IFORMFL_LDDQU_LAST=793, + XED_IFORMFL_LDMXCSR_FIRST=794, + XED_IFORMFL_LDMXCSR_LAST=794, + XED_IFORMFL_LDS_FIRST=795, + XED_IFORMFL_LDS_LAST=795, + XED_IFORMFL_LDTILECFG_FIRST=796, + XED_IFORMFL_LDTILECFG_LAST=796, + XED_IFORMFL_LEA_FIRST=797, + XED_IFORMFL_LEA_LAST=797, + XED_IFORMFL_LEAVE_FIRST=798, + XED_IFORMFL_LEAVE_LAST=798, + XED_IFORMFL_LES_FIRST=799, + XED_IFORMFL_LES_LAST=799, + XED_IFORMFL_LFENCE_FIRST=800, + XED_IFORMFL_LFENCE_LAST=800, + XED_IFORMFL_LFS_FIRST=801, + XED_IFORMFL_LFS_LAST=801, + XED_IFORMFL_LGDT_FIRST=802, + XED_IFORMFL_LGDT_LAST=803, + XED_IFORMFL_LGS_FIRST=804, + XED_IFORMFL_LGS_LAST=804, + XED_IFORMFL_LIDT_FIRST=805, + XED_IFORMFL_LIDT_LAST=806, + XED_IFORMFL_LLDT_FIRST=807, + XED_IFORMFL_LLDT_LAST=808, + XED_IFORMFL_LLWPCB_FIRST=809, + XED_IFORMFL_LLWPCB_LAST=809, + XED_IFORMFL_LMSW_FIRST=810, + XED_IFORMFL_LMSW_LAST=811, + XED_IFORMFL_LOADIWKEY_FIRST=812, + XED_IFORMFL_LOADIWKEY_LAST=812, + XED_IFORMFL_LODSB_FIRST=813, + XED_IFORMFL_LODSB_LAST=813, + XED_IFORMFL_LODSD_FIRST=814, + XED_IFORMFL_LODSD_LAST=814, + XED_IFORMFL_LODSQ_FIRST=815, + XED_IFORMFL_LODSQ_LAST=815, + XED_IFORMFL_LODSW_FIRST=816, + XED_IFORMFL_LODSW_LAST=816, + XED_IFORMFL_LOOP_FIRST=817, + XED_IFORMFL_LOOP_LAST=817, + XED_IFORMFL_LOOPE_FIRST=818, + XED_IFORMFL_LOOPE_LAST=818, + XED_IFORMFL_LOOPNE_FIRST=819, + XED_IFORMFL_LOOPNE_LAST=819, + XED_IFORMFL_LSL_FIRST=820, + XED_IFORMFL_LSL_LAST=821, + XED_IFORMFL_LSS_FIRST=822, + XED_IFORMFL_LSS_LAST=822, + XED_IFORMFL_LTR_FIRST=823, + XED_IFORMFL_LTR_LAST=824, + XED_IFORMFL_LWPINS_FIRST=825, + XED_IFORMFL_LWPINS_LAST=826, + XED_IFORMFL_LWPVAL_FIRST=827, + XED_IFORMFL_LWPVAL_LAST=828, + XED_IFORMFL_LZCNT_FIRST=829, + XED_IFORMFL_LZCNT_LAST=830, + XED_IFORMFL_MASKMOVDQU_FIRST=831, + XED_IFORMFL_MASKMOVDQU_LAST=831, + XED_IFORMFL_MASKMOVQ_FIRST=832, + XED_IFORMFL_MASKMOVQ_LAST=832, + XED_IFORMFL_MAXPD_FIRST=833, + XED_IFORMFL_MAXPD_LAST=834, + XED_IFORMFL_MAXPS_FIRST=835, + XED_IFORMFL_MAXPS_LAST=836, + XED_IFORMFL_MAXSD_FIRST=837, + XED_IFORMFL_MAXSD_LAST=838, + XED_IFORMFL_MAXSS_FIRST=839, + XED_IFORMFL_MAXSS_LAST=840, + XED_IFORMFL_MCOMMIT_FIRST=841, + XED_IFORMFL_MCOMMIT_LAST=841, + XED_IFORMFL_MFENCE_FIRST=842, + XED_IFORMFL_MFENCE_LAST=842, + XED_IFORMFL_MINPD_FIRST=843, + XED_IFORMFL_MINPD_LAST=844, + XED_IFORMFL_MINPS_FIRST=845, + XED_IFORMFL_MINPS_LAST=846, + XED_IFORMFL_MINSD_FIRST=847, + XED_IFORMFL_MINSD_LAST=848, + XED_IFORMFL_MINSS_FIRST=849, + XED_IFORMFL_MINSS_LAST=850, + XED_IFORMFL_MONITOR_FIRST=851, + XED_IFORMFL_MONITOR_LAST=851, + XED_IFORMFL_MONITORX_FIRST=852, + XED_IFORMFL_MONITORX_LAST=852, + XED_IFORMFL_MOV_FIRST=853, + XED_IFORMFL_MOV_LAST=874, + XED_IFORMFL_MOVAPD_FIRST=875, + XED_IFORMFL_MOVAPD_LAST=878, + XED_IFORMFL_MOVAPS_FIRST=879, + XED_IFORMFL_MOVAPS_LAST=882, + XED_IFORMFL_MOVBE_FIRST=883, + XED_IFORMFL_MOVBE_LAST=884, + XED_IFORMFL_MOVD_FIRST=885, + XED_IFORMFL_MOVD_LAST=892, + XED_IFORMFL_MOVDDUP_FIRST=893, + XED_IFORMFL_MOVDDUP_LAST=894, + XED_IFORMFL_MOVDIR64B_FIRST=895, + XED_IFORMFL_MOVDIR64B_LAST=895, + XED_IFORMFL_MOVDIRI_FIRST=896, + XED_IFORMFL_MOVDIRI_LAST=897, + XED_IFORMFL_MOVDQ2Q_FIRST=898, + XED_IFORMFL_MOVDQ2Q_LAST=898, + XED_IFORMFL_MOVDQA_FIRST=899, + XED_IFORMFL_MOVDQA_LAST=902, + XED_IFORMFL_MOVDQU_FIRST=903, + XED_IFORMFL_MOVDQU_LAST=906, + XED_IFORMFL_MOVHLPS_FIRST=907, + XED_IFORMFL_MOVHLPS_LAST=907, + XED_IFORMFL_MOVHPD_FIRST=908, + XED_IFORMFL_MOVHPD_LAST=909, + XED_IFORMFL_MOVHPS_FIRST=910, + XED_IFORMFL_MOVHPS_LAST=911, + XED_IFORMFL_MOVLHPS_FIRST=912, + XED_IFORMFL_MOVLHPS_LAST=912, + XED_IFORMFL_MOVLPD_FIRST=913, + XED_IFORMFL_MOVLPD_LAST=914, + XED_IFORMFL_MOVLPS_FIRST=915, + XED_IFORMFL_MOVLPS_LAST=916, + XED_IFORMFL_MOVMSKPD_FIRST=917, + XED_IFORMFL_MOVMSKPD_LAST=917, + XED_IFORMFL_MOVMSKPS_FIRST=918, + XED_IFORMFL_MOVMSKPS_LAST=918, + XED_IFORMFL_MOVNTDQ_FIRST=919, + XED_IFORMFL_MOVNTDQ_LAST=919, + XED_IFORMFL_MOVNTDQA_FIRST=920, + XED_IFORMFL_MOVNTDQA_LAST=920, + XED_IFORMFL_MOVNTI_FIRST=921, + XED_IFORMFL_MOVNTI_LAST=922, + XED_IFORMFL_MOVNTPD_FIRST=923, + XED_IFORMFL_MOVNTPD_LAST=923, + XED_IFORMFL_MOVNTPS_FIRST=924, + XED_IFORMFL_MOVNTPS_LAST=924, + XED_IFORMFL_MOVNTQ_FIRST=925, + XED_IFORMFL_MOVNTQ_LAST=925, + XED_IFORMFL_MOVNTSD_FIRST=926, + XED_IFORMFL_MOVNTSD_LAST=926, + XED_IFORMFL_MOVNTSS_FIRST=927, + XED_IFORMFL_MOVNTSS_LAST=927, + XED_IFORMFL_MOVQ_FIRST=928, + XED_IFORMFL_MOVQ_LAST=943, + XED_IFORMFL_MOVQ2DQ_FIRST=944, + XED_IFORMFL_MOVQ2DQ_LAST=944, + XED_IFORMFL_MOVSB_FIRST=945, + XED_IFORMFL_MOVSB_LAST=945, + XED_IFORMFL_MOVSD_FIRST=946, + XED_IFORMFL_MOVSD_LAST=946, + XED_IFORMFL_MOVSD_XMM_FIRST=947, + XED_IFORMFL_MOVSD_XMM_LAST=950, + XED_IFORMFL_MOVSHDUP_FIRST=951, + XED_IFORMFL_MOVSHDUP_LAST=952, + XED_IFORMFL_MOVSLDUP_FIRST=953, + XED_IFORMFL_MOVSLDUP_LAST=954, + XED_IFORMFL_MOVSQ_FIRST=955, + XED_IFORMFL_MOVSQ_LAST=955, + XED_IFORMFL_MOVSS_FIRST=956, + XED_IFORMFL_MOVSS_LAST=959, + XED_IFORMFL_MOVSW_FIRST=960, + XED_IFORMFL_MOVSW_LAST=960, + XED_IFORMFL_MOVSX_FIRST=961, + XED_IFORMFL_MOVSX_LAST=964, + XED_IFORMFL_MOVSXD_FIRST=965, + XED_IFORMFL_MOVSXD_LAST=966, + XED_IFORMFL_MOVUPD_FIRST=967, + XED_IFORMFL_MOVUPD_LAST=970, + XED_IFORMFL_MOVUPS_FIRST=971, + XED_IFORMFL_MOVUPS_LAST=974, + XED_IFORMFL_MOVZX_FIRST=975, + XED_IFORMFL_MOVZX_LAST=978, + XED_IFORMFL_MOV_CR_FIRST=979, + XED_IFORMFL_MOV_CR_LAST=982, + XED_IFORMFL_MOV_DR_FIRST=983, + XED_IFORMFL_MOV_DR_LAST=986, + XED_IFORMFL_MPSADBW_FIRST=987, + XED_IFORMFL_MPSADBW_LAST=988, + XED_IFORMFL_MUL_FIRST=989, + XED_IFORMFL_MUL_LAST=992, + XED_IFORMFL_MULPD_FIRST=993, + XED_IFORMFL_MULPD_LAST=994, + XED_IFORMFL_MULPS_FIRST=995, + XED_IFORMFL_MULPS_LAST=996, + XED_IFORMFL_MULSD_FIRST=997, + XED_IFORMFL_MULSD_LAST=998, + XED_IFORMFL_MULSS_FIRST=999, + XED_IFORMFL_MULSS_LAST=1000, + XED_IFORMFL_MULX_FIRST=1001, + XED_IFORMFL_MULX_LAST=1004, + XED_IFORMFL_MWAIT_FIRST=1005, + XED_IFORMFL_MWAIT_LAST=1005, + XED_IFORMFL_MWAITX_FIRST=1006, + XED_IFORMFL_MWAITX_LAST=1006, + XED_IFORMFL_NEG_FIRST=1007, + XED_IFORMFL_NEG_LAST=1010, + XED_IFORMFL_NEG_LOCK_FIRST=1011, + XED_IFORMFL_NEG_LOCK_LAST=1012, + XED_IFORMFL_NOP_FIRST=1013, + XED_IFORMFL_NOP_LAST=1040, + XED_IFORMFL_NOT_FIRST=1041, + XED_IFORMFL_NOT_LAST=1044, + XED_IFORMFL_NOT_LOCK_FIRST=1045, + XED_IFORMFL_NOT_LOCK_LAST=1046, + XED_IFORMFL_OR_FIRST=1047, + XED_IFORMFL_OR_LAST=1064, + XED_IFORMFL_ORPD_FIRST=1065, + XED_IFORMFL_ORPD_LAST=1066, + XED_IFORMFL_ORPS_FIRST=1067, + XED_IFORMFL_ORPS_LAST=1068, + XED_IFORMFL_OR_LOCK_FIRST=1069, + XED_IFORMFL_OR_LOCK_LAST=1074, + XED_IFORMFL_OUT_FIRST=1075, + XED_IFORMFL_OUT_LAST=1078, + XED_IFORMFL_OUTSB_FIRST=1079, + XED_IFORMFL_OUTSB_LAST=1079, + XED_IFORMFL_OUTSD_FIRST=1080, + XED_IFORMFL_OUTSD_LAST=1080, + XED_IFORMFL_OUTSW_FIRST=1081, + XED_IFORMFL_OUTSW_LAST=1081, + XED_IFORMFL_PABSB_FIRST=1082, + XED_IFORMFL_PABSB_LAST=1085, + XED_IFORMFL_PABSD_FIRST=1086, + XED_IFORMFL_PABSD_LAST=1089, + XED_IFORMFL_PABSW_FIRST=1090, + XED_IFORMFL_PABSW_LAST=1093, + XED_IFORMFL_PACKSSDW_FIRST=1094, + XED_IFORMFL_PACKSSDW_LAST=1097, + XED_IFORMFL_PACKSSWB_FIRST=1098, + XED_IFORMFL_PACKSSWB_LAST=1101, + XED_IFORMFL_PACKUSDW_FIRST=1102, + XED_IFORMFL_PACKUSDW_LAST=1103, + XED_IFORMFL_PACKUSWB_FIRST=1104, + XED_IFORMFL_PACKUSWB_LAST=1107, + XED_IFORMFL_PADDB_FIRST=1108, + XED_IFORMFL_PADDB_LAST=1111, + XED_IFORMFL_PADDD_FIRST=1112, + XED_IFORMFL_PADDD_LAST=1115, + XED_IFORMFL_PADDQ_FIRST=1116, + XED_IFORMFL_PADDQ_LAST=1119, + XED_IFORMFL_PADDSB_FIRST=1120, + XED_IFORMFL_PADDSB_LAST=1123, + XED_IFORMFL_PADDSW_FIRST=1124, + XED_IFORMFL_PADDSW_LAST=1127, + XED_IFORMFL_PADDUSB_FIRST=1128, + XED_IFORMFL_PADDUSB_LAST=1131, + XED_IFORMFL_PADDUSW_FIRST=1132, + XED_IFORMFL_PADDUSW_LAST=1135, + XED_IFORMFL_PADDW_FIRST=1136, + XED_IFORMFL_PADDW_LAST=1139, + XED_IFORMFL_PALIGNR_FIRST=1140, + XED_IFORMFL_PALIGNR_LAST=1143, + XED_IFORMFL_PAND_FIRST=1144, + XED_IFORMFL_PAND_LAST=1147, + XED_IFORMFL_PANDN_FIRST=1148, + XED_IFORMFL_PANDN_LAST=1151, + XED_IFORMFL_PAUSE_FIRST=1152, + XED_IFORMFL_PAUSE_LAST=1152, + XED_IFORMFL_PAVGB_FIRST=1153, + XED_IFORMFL_PAVGB_LAST=1156, + XED_IFORMFL_PAVGUSB_FIRST=1157, + XED_IFORMFL_PAVGUSB_LAST=1158, + XED_IFORMFL_PAVGW_FIRST=1159, + XED_IFORMFL_PAVGW_LAST=1162, + XED_IFORMFL_PBLENDVB_FIRST=1163, + XED_IFORMFL_PBLENDVB_LAST=1164, + XED_IFORMFL_PBLENDW_FIRST=1165, + XED_IFORMFL_PBLENDW_LAST=1166, + XED_IFORMFL_PCLMULQDQ_FIRST=1167, + XED_IFORMFL_PCLMULQDQ_LAST=1168, + XED_IFORMFL_PCMPEQB_FIRST=1169, + XED_IFORMFL_PCMPEQB_LAST=1172, + XED_IFORMFL_PCMPEQD_FIRST=1173, + XED_IFORMFL_PCMPEQD_LAST=1176, + XED_IFORMFL_PCMPEQQ_FIRST=1177, + XED_IFORMFL_PCMPEQQ_LAST=1178, + XED_IFORMFL_PCMPEQW_FIRST=1179, + XED_IFORMFL_PCMPEQW_LAST=1182, + XED_IFORMFL_PCMPESTRI_FIRST=1183, + XED_IFORMFL_PCMPESTRI_LAST=1184, + XED_IFORMFL_PCMPESTRI64_FIRST=1185, + XED_IFORMFL_PCMPESTRI64_LAST=1186, + XED_IFORMFL_PCMPESTRM_FIRST=1187, + XED_IFORMFL_PCMPESTRM_LAST=1188, + XED_IFORMFL_PCMPESTRM64_FIRST=1189, + XED_IFORMFL_PCMPESTRM64_LAST=1190, + XED_IFORMFL_PCMPGTB_FIRST=1191, + XED_IFORMFL_PCMPGTB_LAST=1194, + XED_IFORMFL_PCMPGTD_FIRST=1195, + XED_IFORMFL_PCMPGTD_LAST=1198, + XED_IFORMFL_PCMPGTQ_FIRST=1199, + XED_IFORMFL_PCMPGTQ_LAST=1200, + XED_IFORMFL_PCMPGTW_FIRST=1201, + XED_IFORMFL_PCMPGTW_LAST=1204, + XED_IFORMFL_PCMPISTRI_FIRST=1205, + XED_IFORMFL_PCMPISTRI_LAST=1206, + XED_IFORMFL_PCMPISTRI64_FIRST=1207, + XED_IFORMFL_PCMPISTRI64_LAST=1208, + XED_IFORMFL_PCMPISTRM_FIRST=1209, + XED_IFORMFL_PCMPISTRM_LAST=1210, + XED_IFORMFL_PCONFIG_FIRST=1211, + XED_IFORMFL_PCONFIG_LAST=1212, + XED_IFORMFL_PDEP_FIRST=1213, + XED_IFORMFL_PDEP_LAST=1216, + XED_IFORMFL_PEXT_FIRST=1217, + XED_IFORMFL_PEXT_LAST=1220, + XED_IFORMFL_PEXTRB_FIRST=1221, + XED_IFORMFL_PEXTRB_LAST=1222, + XED_IFORMFL_PEXTRD_FIRST=1223, + XED_IFORMFL_PEXTRD_LAST=1224, + XED_IFORMFL_PEXTRQ_FIRST=1225, + XED_IFORMFL_PEXTRQ_LAST=1226, + XED_IFORMFL_PEXTRW_FIRST=1227, + XED_IFORMFL_PEXTRW_LAST=1228, + XED_IFORMFL_PEXTRW_SSE4_FIRST=1229, + XED_IFORMFL_PEXTRW_SSE4_LAST=1230, + XED_IFORMFL_PF2ID_FIRST=1231, + XED_IFORMFL_PF2ID_LAST=1232, + XED_IFORMFL_PF2IW_FIRST=1233, + XED_IFORMFL_PF2IW_LAST=1234, + XED_IFORMFL_PFACC_FIRST=1235, + XED_IFORMFL_PFACC_LAST=1236, + XED_IFORMFL_PFADD_FIRST=1237, + XED_IFORMFL_PFADD_LAST=1238, + XED_IFORMFL_PFCMPEQ_FIRST=1239, + XED_IFORMFL_PFCMPEQ_LAST=1240, + XED_IFORMFL_PFCMPGE_FIRST=1241, + XED_IFORMFL_PFCMPGE_LAST=1242, + XED_IFORMFL_PFCMPGT_FIRST=1243, + XED_IFORMFL_PFCMPGT_LAST=1244, + XED_IFORMFL_PFMAX_FIRST=1245, + XED_IFORMFL_PFMAX_LAST=1246, + XED_IFORMFL_PFMIN_FIRST=1247, + XED_IFORMFL_PFMIN_LAST=1248, + XED_IFORMFL_PFMUL_FIRST=1249, + XED_IFORMFL_PFMUL_LAST=1250, + XED_IFORMFL_PFNACC_FIRST=1251, + XED_IFORMFL_PFNACC_LAST=1252, + XED_IFORMFL_PFPNACC_FIRST=1253, + XED_IFORMFL_PFPNACC_LAST=1254, + XED_IFORMFL_PFRCP_FIRST=1255, + XED_IFORMFL_PFRCP_LAST=1256, + XED_IFORMFL_PFRCPIT1_FIRST=1257, + XED_IFORMFL_PFRCPIT1_LAST=1258, + XED_IFORMFL_PFRCPIT2_FIRST=1259, + XED_IFORMFL_PFRCPIT2_LAST=1260, + XED_IFORMFL_PFRSQIT1_FIRST=1261, + XED_IFORMFL_PFRSQIT1_LAST=1262, + XED_IFORMFL_PFRSQRT_FIRST=1263, + XED_IFORMFL_PFRSQRT_LAST=1264, + XED_IFORMFL_PFSUB_FIRST=1265, + XED_IFORMFL_PFSUB_LAST=1266, + XED_IFORMFL_PFSUBR_FIRST=1267, + XED_IFORMFL_PFSUBR_LAST=1268, + XED_IFORMFL_PHADDD_FIRST=1269, + XED_IFORMFL_PHADDD_LAST=1272, + XED_IFORMFL_PHADDSW_FIRST=1273, + XED_IFORMFL_PHADDSW_LAST=1276, + XED_IFORMFL_PHADDW_FIRST=1277, + XED_IFORMFL_PHADDW_LAST=1280, + XED_IFORMFL_PHMINPOSUW_FIRST=1281, + XED_IFORMFL_PHMINPOSUW_LAST=1282, + XED_IFORMFL_PHSUBD_FIRST=1283, + XED_IFORMFL_PHSUBD_LAST=1286, + XED_IFORMFL_PHSUBSW_FIRST=1287, + XED_IFORMFL_PHSUBSW_LAST=1290, + XED_IFORMFL_PHSUBW_FIRST=1291, + XED_IFORMFL_PHSUBW_LAST=1294, + XED_IFORMFL_PI2FD_FIRST=1295, + XED_IFORMFL_PI2FD_LAST=1296, + XED_IFORMFL_PI2FW_FIRST=1297, + XED_IFORMFL_PI2FW_LAST=1298, + XED_IFORMFL_PINSRB_FIRST=1299, + XED_IFORMFL_PINSRB_LAST=1300, + XED_IFORMFL_PINSRD_FIRST=1301, + XED_IFORMFL_PINSRD_LAST=1302, + XED_IFORMFL_PINSRQ_FIRST=1303, + XED_IFORMFL_PINSRQ_LAST=1304, + XED_IFORMFL_PINSRW_FIRST=1305, + XED_IFORMFL_PINSRW_LAST=1308, + XED_IFORMFL_PMADDUBSW_FIRST=1309, + XED_IFORMFL_PMADDUBSW_LAST=1312, + XED_IFORMFL_PMADDWD_FIRST=1313, + XED_IFORMFL_PMADDWD_LAST=1316, + XED_IFORMFL_PMAXSB_FIRST=1317, + XED_IFORMFL_PMAXSB_LAST=1318, + XED_IFORMFL_PMAXSD_FIRST=1319, + XED_IFORMFL_PMAXSD_LAST=1320, + XED_IFORMFL_PMAXSW_FIRST=1321, + XED_IFORMFL_PMAXSW_LAST=1324, + XED_IFORMFL_PMAXUB_FIRST=1325, + XED_IFORMFL_PMAXUB_LAST=1328, + XED_IFORMFL_PMAXUD_FIRST=1329, + XED_IFORMFL_PMAXUD_LAST=1330, + XED_IFORMFL_PMAXUW_FIRST=1331, + XED_IFORMFL_PMAXUW_LAST=1332, + XED_IFORMFL_PMINSB_FIRST=1333, + XED_IFORMFL_PMINSB_LAST=1334, + XED_IFORMFL_PMINSD_FIRST=1335, + XED_IFORMFL_PMINSD_LAST=1336, + XED_IFORMFL_PMINSW_FIRST=1337, + XED_IFORMFL_PMINSW_LAST=1340, + XED_IFORMFL_PMINUB_FIRST=1341, + XED_IFORMFL_PMINUB_LAST=1344, + XED_IFORMFL_PMINUD_FIRST=1345, + XED_IFORMFL_PMINUD_LAST=1346, + XED_IFORMFL_PMINUW_FIRST=1347, + XED_IFORMFL_PMINUW_LAST=1348, + XED_IFORMFL_PMOVMSKB_FIRST=1349, + XED_IFORMFL_PMOVMSKB_LAST=1350, + XED_IFORMFL_PMOVSXBD_FIRST=1351, + XED_IFORMFL_PMOVSXBD_LAST=1352, + XED_IFORMFL_PMOVSXBQ_FIRST=1353, + XED_IFORMFL_PMOVSXBQ_LAST=1354, + XED_IFORMFL_PMOVSXBW_FIRST=1355, + XED_IFORMFL_PMOVSXBW_LAST=1356, + XED_IFORMFL_PMOVSXDQ_FIRST=1357, + XED_IFORMFL_PMOVSXDQ_LAST=1358, + XED_IFORMFL_PMOVSXWD_FIRST=1359, + XED_IFORMFL_PMOVSXWD_LAST=1360, + XED_IFORMFL_PMOVSXWQ_FIRST=1361, + XED_IFORMFL_PMOVSXWQ_LAST=1362, + XED_IFORMFL_PMOVZXBD_FIRST=1363, + XED_IFORMFL_PMOVZXBD_LAST=1364, + XED_IFORMFL_PMOVZXBQ_FIRST=1365, + XED_IFORMFL_PMOVZXBQ_LAST=1366, + XED_IFORMFL_PMOVZXBW_FIRST=1367, + XED_IFORMFL_PMOVZXBW_LAST=1368, + XED_IFORMFL_PMOVZXDQ_FIRST=1369, + XED_IFORMFL_PMOVZXDQ_LAST=1370, + XED_IFORMFL_PMOVZXWD_FIRST=1371, + XED_IFORMFL_PMOVZXWD_LAST=1372, + XED_IFORMFL_PMOVZXWQ_FIRST=1373, + XED_IFORMFL_PMOVZXWQ_LAST=1374, + XED_IFORMFL_PMULDQ_FIRST=1375, + XED_IFORMFL_PMULDQ_LAST=1376, + XED_IFORMFL_PMULHRSW_FIRST=1377, + XED_IFORMFL_PMULHRSW_LAST=1380, + XED_IFORMFL_PMULHRW_FIRST=1381, + XED_IFORMFL_PMULHRW_LAST=1382, + XED_IFORMFL_PMULHUW_FIRST=1383, + XED_IFORMFL_PMULHUW_LAST=1386, + XED_IFORMFL_PMULHW_FIRST=1387, + XED_IFORMFL_PMULHW_LAST=1390, + XED_IFORMFL_PMULLD_FIRST=1391, + XED_IFORMFL_PMULLD_LAST=1392, + XED_IFORMFL_PMULLW_FIRST=1393, + XED_IFORMFL_PMULLW_LAST=1396, + XED_IFORMFL_PMULUDQ_FIRST=1397, + XED_IFORMFL_PMULUDQ_LAST=1400, + XED_IFORMFL_POP_FIRST=1401, + XED_IFORMFL_POP_LAST=1408, + XED_IFORMFL_POPA_FIRST=1409, + XED_IFORMFL_POPA_LAST=1409, + XED_IFORMFL_POPAD_FIRST=1410, + XED_IFORMFL_POPAD_LAST=1410, + XED_IFORMFL_POPCNT_FIRST=1411, + XED_IFORMFL_POPCNT_LAST=1412, + XED_IFORMFL_POPF_FIRST=1413, + XED_IFORMFL_POPF_LAST=1413, + XED_IFORMFL_POPFD_FIRST=1414, + XED_IFORMFL_POPFD_LAST=1414, + XED_IFORMFL_POPFQ_FIRST=1415, + XED_IFORMFL_POPFQ_LAST=1415, + XED_IFORMFL_POR_FIRST=1416, + XED_IFORMFL_POR_LAST=1419, + XED_IFORMFL_PREFETCHNTA_FIRST=1420, + XED_IFORMFL_PREFETCHNTA_LAST=1420, + XED_IFORMFL_PREFETCHT0_FIRST=1421, + XED_IFORMFL_PREFETCHT0_LAST=1421, + XED_IFORMFL_PREFETCHT1_FIRST=1422, + XED_IFORMFL_PREFETCHT1_LAST=1422, + XED_IFORMFL_PREFETCHT2_FIRST=1423, + XED_IFORMFL_PREFETCHT2_LAST=1423, + XED_IFORMFL_PREFETCHW_FIRST=1424, + XED_IFORMFL_PREFETCHW_LAST=1425, + XED_IFORMFL_PREFETCHWT1_FIRST=1426, + XED_IFORMFL_PREFETCHWT1_LAST=1426, + XED_IFORMFL_PREFETCH_EXCLUSIVE_FIRST=1427, + XED_IFORMFL_PREFETCH_EXCLUSIVE_LAST=1427, + XED_IFORMFL_PREFETCH_RESERVED_FIRST=1428, + XED_IFORMFL_PREFETCH_RESERVED_LAST=1431, + XED_IFORMFL_PSADBW_FIRST=1432, + XED_IFORMFL_PSADBW_LAST=1435, + XED_IFORMFL_PSHUFB_FIRST=1436, + XED_IFORMFL_PSHUFB_LAST=1439, + XED_IFORMFL_PSHUFD_FIRST=1440, + XED_IFORMFL_PSHUFD_LAST=1441, + XED_IFORMFL_PSHUFHW_FIRST=1442, + XED_IFORMFL_PSHUFHW_LAST=1443, + XED_IFORMFL_PSHUFLW_FIRST=1444, + XED_IFORMFL_PSHUFLW_LAST=1445, + XED_IFORMFL_PSHUFW_FIRST=1446, + XED_IFORMFL_PSHUFW_LAST=1447, + XED_IFORMFL_PSIGNB_FIRST=1448, + XED_IFORMFL_PSIGNB_LAST=1451, + XED_IFORMFL_PSIGND_FIRST=1452, + XED_IFORMFL_PSIGND_LAST=1455, + XED_IFORMFL_PSIGNW_FIRST=1456, + XED_IFORMFL_PSIGNW_LAST=1459, + XED_IFORMFL_PSLLD_FIRST=1460, + XED_IFORMFL_PSLLD_LAST=1465, + XED_IFORMFL_PSLLDQ_FIRST=1466, + XED_IFORMFL_PSLLDQ_LAST=1466, + XED_IFORMFL_PSLLQ_FIRST=1467, + XED_IFORMFL_PSLLQ_LAST=1472, + XED_IFORMFL_PSLLW_FIRST=1473, + XED_IFORMFL_PSLLW_LAST=1478, + XED_IFORMFL_PSMASH_FIRST=1479, + XED_IFORMFL_PSMASH_LAST=1479, + XED_IFORMFL_PSRAD_FIRST=1480, + XED_IFORMFL_PSRAD_LAST=1485, + XED_IFORMFL_PSRAW_FIRST=1486, + XED_IFORMFL_PSRAW_LAST=1491, + XED_IFORMFL_PSRLD_FIRST=1492, + XED_IFORMFL_PSRLD_LAST=1497, + XED_IFORMFL_PSRLDQ_FIRST=1498, + XED_IFORMFL_PSRLDQ_LAST=1498, + XED_IFORMFL_PSRLQ_FIRST=1499, + XED_IFORMFL_PSRLQ_LAST=1504, + XED_IFORMFL_PSRLW_FIRST=1505, + XED_IFORMFL_PSRLW_LAST=1510, + XED_IFORMFL_PSUBB_FIRST=1511, + XED_IFORMFL_PSUBB_LAST=1514, + XED_IFORMFL_PSUBD_FIRST=1515, + XED_IFORMFL_PSUBD_LAST=1518, + XED_IFORMFL_PSUBQ_FIRST=1519, + XED_IFORMFL_PSUBQ_LAST=1522, + XED_IFORMFL_PSUBSB_FIRST=1523, + XED_IFORMFL_PSUBSB_LAST=1526, + XED_IFORMFL_PSUBSW_FIRST=1527, + XED_IFORMFL_PSUBSW_LAST=1530, + XED_IFORMFL_PSUBUSB_FIRST=1531, + XED_IFORMFL_PSUBUSB_LAST=1534, + XED_IFORMFL_PSUBUSW_FIRST=1535, + XED_IFORMFL_PSUBUSW_LAST=1538, + XED_IFORMFL_PSUBW_FIRST=1539, + XED_IFORMFL_PSUBW_LAST=1542, + XED_IFORMFL_PSWAPD_FIRST=1543, + XED_IFORMFL_PSWAPD_LAST=1544, + XED_IFORMFL_PTEST_FIRST=1545, + XED_IFORMFL_PTEST_LAST=1546, + XED_IFORMFL_PTWRITE_FIRST=1547, + XED_IFORMFL_PTWRITE_LAST=1548, + XED_IFORMFL_PUNPCKHBW_FIRST=1549, + XED_IFORMFL_PUNPCKHBW_LAST=1552, + XED_IFORMFL_PUNPCKHDQ_FIRST=1553, + XED_IFORMFL_PUNPCKHDQ_LAST=1556, + XED_IFORMFL_PUNPCKHQDQ_FIRST=1557, + XED_IFORMFL_PUNPCKHQDQ_LAST=1558, + XED_IFORMFL_PUNPCKHWD_FIRST=1559, + XED_IFORMFL_PUNPCKHWD_LAST=1562, + XED_IFORMFL_PUNPCKLBW_FIRST=1563, + XED_IFORMFL_PUNPCKLBW_LAST=1566, + XED_IFORMFL_PUNPCKLDQ_FIRST=1567, + XED_IFORMFL_PUNPCKLDQ_LAST=1570, + XED_IFORMFL_PUNPCKLQDQ_FIRST=1571, + XED_IFORMFL_PUNPCKLQDQ_LAST=1572, + XED_IFORMFL_PUNPCKLWD_FIRST=1573, + XED_IFORMFL_PUNPCKLWD_LAST=1576, + XED_IFORMFL_PUSH_FIRST=1577, + XED_IFORMFL_PUSH_LAST=1587, + XED_IFORMFL_PUSHA_FIRST=1588, + XED_IFORMFL_PUSHA_LAST=1588, + XED_IFORMFL_PUSHAD_FIRST=1589, + XED_IFORMFL_PUSHAD_LAST=1589, + XED_IFORMFL_PUSHF_FIRST=1590, + XED_IFORMFL_PUSHF_LAST=1590, + XED_IFORMFL_PUSHFD_FIRST=1591, + XED_IFORMFL_PUSHFD_LAST=1591, + XED_IFORMFL_PUSHFQ_FIRST=1592, + XED_IFORMFL_PUSHFQ_LAST=1592, + XED_IFORMFL_PVALIDATE_FIRST=1593, + XED_IFORMFL_PVALIDATE_LAST=1593, + XED_IFORMFL_PXOR_FIRST=1594, + XED_IFORMFL_PXOR_LAST=1597, + XED_IFORMFL_RCL_FIRST=1598, + XED_IFORMFL_RCL_LAST=1609, + XED_IFORMFL_RCPPS_FIRST=1610, + XED_IFORMFL_RCPPS_LAST=1611, + XED_IFORMFL_RCPSS_FIRST=1612, + XED_IFORMFL_RCPSS_LAST=1613, + XED_IFORMFL_RCR_FIRST=1614, + XED_IFORMFL_RCR_LAST=1625, + XED_IFORMFL_RDFSBASE_FIRST=1626, + XED_IFORMFL_RDFSBASE_LAST=1626, + XED_IFORMFL_RDGSBASE_FIRST=1627, + XED_IFORMFL_RDGSBASE_LAST=1627, + XED_IFORMFL_RDMSR_FIRST=1628, + XED_IFORMFL_RDMSR_LAST=1628, + XED_IFORMFL_RDPID_FIRST=1629, + XED_IFORMFL_RDPID_LAST=1630, + XED_IFORMFL_RDPKRU_FIRST=1631, + XED_IFORMFL_RDPKRU_LAST=1631, + XED_IFORMFL_RDPMC_FIRST=1632, + XED_IFORMFL_RDPMC_LAST=1632, + XED_IFORMFL_RDPRU_FIRST=1633, + XED_IFORMFL_RDPRU_LAST=1633, + XED_IFORMFL_RDRAND_FIRST=1634, + XED_IFORMFL_RDRAND_LAST=1634, + XED_IFORMFL_RDSEED_FIRST=1635, + XED_IFORMFL_RDSEED_LAST=1635, + XED_IFORMFL_RDSSPD_FIRST=1636, + XED_IFORMFL_RDSSPD_LAST=1636, + XED_IFORMFL_RDSSPQ_FIRST=1637, + XED_IFORMFL_RDSSPQ_LAST=1637, + XED_IFORMFL_RDTSC_FIRST=1638, + XED_IFORMFL_RDTSC_LAST=1638, + XED_IFORMFL_RDTSCP_FIRST=1639, + XED_IFORMFL_RDTSCP_LAST=1639, + XED_IFORMFL_REPE_CMPSB_FIRST=1640, + XED_IFORMFL_REPE_CMPSB_LAST=1640, + XED_IFORMFL_REPE_CMPSD_FIRST=1641, + XED_IFORMFL_REPE_CMPSD_LAST=1641, + XED_IFORMFL_REPE_CMPSQ_FIRST=1642, + XED_IFORMFL_REPE_CMPSQ_LAST=1642, + XED_IFORMFL_REPE_CMPSW_FIRST=1643, + XED_IFORMFL_REPE_CMPSW_LAST=1643, + XED_IFORMFL_REPE_SCASB_FIRST=1644, + XED_IFORMFL_REPE_SCASB_LAST=1644, + XED_IFORMFL_REPE_SCASD_FIRST=1645, + XED_IFORMFL_REPE_SCASD_LAST=1645, + XED_IFORMFL_REPE_SCASQ_FIRST=1646, + XED_IFORMFL_REPE_SCASQ_LAST=1646, + XED_IFORMFL_REPE_SCASW_FIRST=1647, + XED_IFORMFL_REPE_SCASW_LAST=1647, + XED_IFORMFL_REPNE_CMPSB_FIRST=1648, + XED_IFORMFL_REPNE_CMPSB_LAST=1648, + XED_IFORMFL_REPNE_CMPSD_FIRST=1649, + XED_IFORMFL_REPNE_CMPSD_LAST=1649, + XED_IFORMFL_REPNE_CMPSQ_FIRST=1650, + XED_IFORMFL_REPNE_CMPSQ_LAST=1650, + XED_IFORMFL_REPNE_CMPSW_FIRST=1651, + XED_IFORMFL_REPNE_CMPSW_LAST=1651, + XED_IFORMFL_REPNE_SCASB_FIRST=1652, + XED_IFORMFL_REPNE_SCASB_LAST=1652, + XED_IFORMFL_REPNE_SCASD_FIRST=1653, + XED_IFORMFL_REPNE_SCASD_LAST=1653, + XED_IFORMFL_REPNE_SCASQ_FIRST=1654, + XED_IFORMFL_REPNE_SCASQ_LAST=1654, + XED_IFORMFL_REPNE_SCASW_FIRST=1655, + XED_IFORMFL_REPNE_SCASW_LAST=1655, + XED_IFORMFL_REP_INSB_FIRST=1656, + XED_IFORMFL_REP_INSB_LAST=1656, + XED_IFORMFL_REP_INSD_FIRST=1657, + XED_IFORMFL_REP_INSD_LAST=1657, + XED_IFORMFL_REP_INSW_FIRST=1658, + XED_IFORMFL_REP_INSW_LAST=1658, + XED_IFORMFL_REP_LODSB_FIRST=1659, + XED_IFORMFL_REP_LODSB_LAST=1659, + XED_IFORMFL_REP_LODSD_FIRST=1660, + XED_IFORMFL_REP_LODSD_LAST=1660, + XED_IFORMFL_REP_LODSQ_FIRST=1661, + XED_IFORMFL_REP_LODSQ_LAST=1661, + XED_IFORMFL_REP_LODSW_FIRST=1662, + XED_IFORMFL_REP_LODSW_LAST=1662, + XED_IFORMFL_REP_MONTMUL_FIRST=1663, + XED_IFORMFL_REP_MONTMUL_LAST=1663, + XED_IFORMFL_REP_MOVSB_FIRST=1664, + XED_IFORMFL_REP_MOVSB_LAST=1664, + XED_IFORMFL_REP_MOVSD_FIRST=1665, + XED_IFORMFL_REP_MOVSD_LAST=1665, + XED_IFORMFL_REP_MOVSQ_FIRST=1666, + XED_IFORMFL_REP_MOVSQ_LAST=1666, + XED_IFORMFL_REP_MOVSW_FIRST=1667, + XED_IFORMFL_REP_MOVSW_LAST=1667, + XED_IFORMFL_REP_OUTSB_FIRST=1668, + XED_IFORMFL_REP_OUTSB_LAST=1668, + XED_IFORMFL_REP_OUTSD_FIRST=1669, + XED_IFORMFL_REP_OUTSD_LAST=1669, + XED_IFORMFL_REP_OUTSW_FIRST=1670, + XED_IFORMFL_REP_OUTSW_LAST=1670, + XED_IFORMFL_REP_STOSB_FIRST=1671, + XED_IFORMFL_REP_STOSB_LAST=1671, + XED_IFORMFL_REP_STOSD_FIRST=1672, + XED_IFORMFL_REP_STOSD_LAST=1672, + XED_IFORMFL_REP_STOSQ_FIRST=1673, + XED_IFORMFL_REP_STOSQ_LAST=1673, + XED_IFORMFL_REP_STOSW_FIRST=1674, + XED_IFORMFL_REP_STOSW_LAST=1674, + XED_IFORMFL_REP_XCRYPTCBC_FIRST=1675, + XED_IFORMFL_REP_XCRYPTCBC_LAST=1675, + XED_IFORMFL_REP_XCRYPTCFB_FIRST=1676, + XED_IFORMFL_REP_XCRYPTCFB_LAST=1676, + XED_IFORMFL_REP_XCRYPTCTR_FIRST=1677, + XED_IFORMFL_REP_XCRYPTCTR_LAST=1677, + XED_IFORMFL_REP_XCRYPTECB_FIRST=1678, + XED_IFORMFL_REP_XCRYPTECB_LAST=1678, + XED_IFORMFL_REP_XCRYPTOFB_FIRST=1679, + XED_IFORMFL_REP_XCRYPTOFB_LAST=1679, + XED_IFORMFL_REP_XSHA1_FIRST=1680, + XED_IFORMFL_REP_XSHA1_LAST=1680, + XED_IFORMFL_REP_XSHA256_FIRST=1681, + XED_IFORMFL_REP_XSHA256_LAST=1681, + XED_IFORMFL_REP_XSTORE_FIRST=1682, + XED_IFORMFL_REP_XSTORE_LAST=1682, + XED_IFORMFL_RET_FAR_FIRST=1683, + XED_IFORMFL_RET_FAR_LAST=1684, + XED_IFORMFL_RET_NEAR_FIRST=1685, + XED_IFORMFL_RET_NEAR_LAST=1686, + XED_IFORMFL_RMPADJUST_FIRST=1687, + XED_IFORMFL_RMPADJUST_LAST=1687, + XED_IFORMFL_RMPUPDATE_FIRST=1688, + XED_IFORMFL_RMPUPDATE_LAST=1688, + XED_IFORMFL_ROL_FIRST=1689, + XED_IFORMFL_ROL_LAST=1700, + XED_IFORMFL_ROR_FIRST=1701, + XED_IFORMFL_ROR_LAST=1712, + XED_IFORMFL_RORX_FIRST=1713, + XED_IFORMFL_RORX_LAST=1716, + XED_IFORMFL_ROUNDPD_FIRST=1717, + XED_IFORMFL_ROUNDPD_LAST=1718, + XED_IFORMFL_ROUNDPS_FIRST=1719, + XED_IFORMFL_ROUNDPS_LAST=1720, + XED_IFORMFL_ROUNDSD_FIRST=1721, + XED_IFORMFL_ROUNDSD_LAST=1722, + XED_IFORMFL_ROUNDSS_FIRST=1723, + XED_IFORMFL_ROUNDSS_LAST=1724, + XED_IFORMFL_RSM_FIRST=1725, + XED_IFORMFL_RSM_LAST=1725, + XED_IFORMFL_RSQRTPS_FIRST=1726, + XED_IFORMFL_RSQRTPS_LAST=1727, + XED_IFORMFL_RSQRTSS_FIRST=1728, + XED_IFORMFL_RSQRTSS_LAST=1729, + XED_IFORMFL_RSTORSSP_FIRST=1730, + XED_IFORMFL_RSTORSSP_LAST=1730, + XED_IFORMFL_SAHF_FIRST=1731, + XED_IFORMFL_SAHF_LAST=1731, + XED_IFORMFL_SALC_FIRST=1732, + XED_IFORMFL_SALC_LAST=1732, + XED_IFORMFL_SAR_FIRST=1733, + XED_IFORMFL_SAR_LAST=1744, + XED_IFORMFL_SARX_FIRST=1745, + XED_IFORMFL_SARX_LAST=1748, + XED_IFORMFL_SAVEPREVSSP_FIRST=1749, + XED_IFORMFL_SAVEPREVSSP_LAST=1749, + XED_IFORMFL_SBB_FIRST=1750, + XED_IFORMFL_SBB_LAST=1767, + XED_IFORMFL_SBB_LOCK_FIRST=1768, + XED_IFORMFL_SBB_LOCK_LAST=1773, + XED_IFORMFL_SCASB_FIRST=1774, + XED_IFORMFL_SCASB_LAST=1774, + XED_IFORMFL_SCASD_FIRST=1775, + XED_IFORMFL_SCASD_LAST=1775, + XED_IFORMFL_SCASQ_FIRST=1776, + XED_IFORMFL_SCASQ_LAST=1776, + XED_IFORMFL_SCASW_FIRST=1777, + XED_IFORMFL_SCASW_LAST=1777, + XED_IFORMFL_SEAMCALL_FIRST=1778, + XED_IFORMFL_SEAMCALL_LAST=1778, + XED_IFORMFL_SEAMOPS_FIRST=1779, + XED_IFORMFL_SEAMOPS_LAST=1779, + XED_IFORMFL_SEAMRET_FIRST=1780, + XED_IFORMFL_SEAMRET_LAST=1780, + XED_IFORMFL_SENDUIPI_FIRST=1781, + XED_IFORMFL_SENDUIPI_LAST=1781, + XED_IFORMFL_SERIALIZE_FIRST=1782, + XED_IFORMFL_SERIALIZE_LAST=1782, + XED_IFORMFL_SETB_FIRST=1783, + XED_IFORMFL_SETB_LAST=1784, + XED_IFORMFL_SETBE_FIRST=1785, + XED_IFORMFL_SETBE_LAST=1786, + XED_IFORMFL_SETL_FIRST=1787, + XED_IFORMFL_SETL_LAST=1788, + XED_IFORMFL_SETLE_FIRST=1789, + XED_IFORMFL_SETLE_LAST=1790, + XED_IFORMFL_SETNB_FIRST=1791, + XED_IFORMFL_SETNB_LAST=1792, + XED_IFORMFL_SETNBE_FIRST=1793, + XED_IFORMFL_SETNBE_LAST=1794, + XED_IFORMFL_SETNL_FIRST=1795, + XED_IFORMFL_SETNL_LAST=1796, + XED_IFORMFL_SETNLE_FIRST=1797, + XED_IFORMFL_SETNLE_LAST=1798, + XED_IFORMFL_SETNO_FIRST=1799, + XED_IFORMFL_SETNO_LAST=1800, + XED_IFORMFL_SETNP_FIRST=1801, + XED_IFORMFL_SETNP_LAST=1802, + XED_IFORMFL_SETNS_FIRST=1803, + XED_IFORMFL_SETNS_LAST=1804, + XED_IFORMFL_SETNZ_FIRST=1805, + XED_IFORMFL_SETNZ_LAST=1806, + XED_IFORMFL_SETO_FIRST=1807, + XED_IFORMFL_SETO_LAST=1808, + XED_IFORMFL_SETP_FIRST=1809, + XED_IFORMFL_SETP_LAST=1810, + XED_IFORMFL_SETS_FIRST=1811, + XED_IFORMFL_SETS_LAST=1812, + XED_IFORMFL_SETSSBSY_FIRST=1813, + XED_IFORMFL_SETSSBSY_LAST=1813, + XED_IFORMFL_SETZ_FIRST=1814, + XED_IFORMFL_SETZ_LAST=1815, + XED_IFORMFL_SFENCE_FIRST=1816, + XED_IFORMFL_SFENCE_LAST=1816, + XED_IFORMFL_SGDT_FIRST=1817, + XED_IFORMFL_SGDT_LAST=1818, + XED_IFORMFL_SHA1MSG1_FIRST=1819, + XED_IFORMFL_SHA1MSG1_LAST=1820, + XED_IFORMFL_SHA1MSG2_FIRST=1821, + XED_IFORMFL_SHA1MSG2_LAST=1822, + XED_IFORMFL_SHA1NEXTE_FIRST=1823, + XED_IFORMFL_SHA1NEXTE_LAST=1824, + XED_IFORMFL_SHA1RNDS4_FIRST=1825, + XED_IFORMFL_SHA1RNDS4_LAST=1826, + XED_IFORMFL_SHA256MSG1_FIRST=1827, + XED_IFORMFL_SHA256MSG1_LAST=1828, + XED_IFORMFL_SHA256MSG2_FIRST=1829, + XED_IFORMFL_SHA256MSG2_LAST=1830, + XED_IFORMFL_SHA256RNDS2_FIRST=1831, + XED_IFORMFL_SHA256RNDS2_LAST=1832, + XED_IFORMFL_SHL_FIRST=1833, + XED_IFORMFL_SHL_LAST=1856, + XED_IFORMFL_SHLD_FIRST=1857, + XED_IFORMFL_SHLD_LAST=1860, + XED_IFORMFL_SHLX_FIRST=1861, + XED_IFORMFL_SHLX_LAST=1864, + XED_IFORMFL_SHR_FIRST=1865, + XED_IFORMFL_SHR_LAST=1876, + XED_IFORMFL_SHRD_FIRST=1877, + XED_IFORMFL_SHRD_LAST=1880, + XED_IFORMFL_SHRX_FIRST=1881, + XED_IFORMFL_SHRX_LAST=1884, + XED_IFORMFL_SHUFPD_FIRST=1885, + XED_IFORMFL_SHUFPD_LAST=1886, + XED_IFORMFL_SHUFPS_FIRST=1887, + XED_IFORMFL_SHUFPS_LAST=1888, + XED_IFORMFL_SIDT_FIRST=1889, + XED_IFORMFL_SIDT_LAST=1890, + XED_IFORMFL_SKINIT_FIRST=1891, + XED_IFORMFL_SKINIT_LAST=1891, + XED_IFORMFL_SLDT_FIRST=1892, + XED_IFORMFL_SLDT_LAST=1893, + XED_IFORMFL_SLWPCB_FIRST=1894, + XED_IFORMFL_SLWPCB_LAST=1894, + XED_IFORMFL_SMSW_FIRST=1895, + XED_IFORMFL_SMSW_LAST=1896, + XED_IFORMFL_SQRTPD_FIRST=1897, + XED_IFORMFL_SQRTPD_LAST=1898, + XED_IFORMFL_SQRTPS_FIRST=1899, + XED_IFORMFL_SQRTPS_LAST=1900, + XED_IFORMFL_SQRTSD_FIRST=1901, + XED_IFORMFL_SQRTSD_LAST=1902, + XED_IFORMFL_SQRTSS_FIRST=1903, + XED_IFORMFL_SQRTSS_LAST=1904, + XED_IFORMFL_STAC_FIRST=1905, + XED_IFORMFL_STAC_LAST=1905, + XED_IFORMFL_STC_FIRST=1906, + XED_IFORMFL_STC_LAST=1906, + XED_IFORMFL_STD_FIRST=1907, + XED_IFORMFL_STD_LAST=1907, + XED_IFORMFL_STGI_FIRST=1908, + XED_IFORMFL_STGI_LAST=1908, + XED_IFORMFL_STI_FIRST=1909, + XED_IFORMFL_STI_LAST=1909, + XED_IFORMFL_STMXCSR_FIRST=1910, + XED_IFORMFL_STMXCSR_LAST=1910, + XED_IFORMFL_STOSB_FIRST=1911, + XED_IFORMFL_STOSB_LAST=1911, + XED_IFORMFL_STOSD_FIRST=1912, + XED_IFORMFL_STOSD_LAST=1912, + XED_IFORMFL_STOSQ_FIRST=1913, + XED_IFORMFL_STOSQ_LAST=1913, + XED_IFORMFL_STOSW_FIRST=1914, + XED_IFORMFL_STOSW_LAST=1914, + XED_IFORMFL_STR_FIRST=1915, + XED_IFORMFL_STR_LAST=1916, + XED_IFORMFL_STTILECFG_FIRST=1917, + XED_IFORMFL_STTILECFG_LAST=1917, + XED_IFORMFL_STUI_FIRST=1918, + XED_IFORMFL_STUI_LAST=1918, + XED_IFORMFL_SUB_FIRST=1919, + XED_IFORMFL_SUB_LAST=1936, + XED_IFORMFL_SUBPD_FIRST=1937, + XED_IFORMFL_SUBPD_LAST=1938, + XED_IFORMFL_SUBPS_FIRST=1939, + XED_IFORMFL_SUBPS_LAST=1940, + XED_IFORMFL_SUBSD_FIRST=1941, + XED_IFORMFL_SUBSD_LAST=1942, + XED_IFORMFL_SUBSS_FIRST=1943, + XED_IFORMFL_SUBSS_LAST=1944, + XED_IFORMFL_SUB_LOCK_FIRST=1945, + XED_IFORMFL_SUB_LOCK_LAST=1950, + XED_IFORMFL_SWAPGS_FIRST=1951, + XED_IFORMFL_SWAPGS_LAST=1951, + XED_IFORMFL_SYSCALL_FIRST=1952, + XED_IFORMFL_SYSCALL_LAST=1952, + XED_IFORMFL_SYSCALL_AMD_FIRST=1953, + XED_IFORMFL_SYSCALL_AMD_LAST=1953, + XED_IFORMFL_SYSENTER_FIRST=1954, + XED_IFORMFL_SYSENTER_LAST=1954, + XED_IFORMFL_SYSEXIT_FIRST=1955, + XED_IFORMFL_SYSEXIT_LAST=1955, + XED_IFORMFL_SYSRET_FIRST=1956, + XED_IFORMFL_SYSRET_LAST=1956, + XED_IFORMFL_SYSRET64_FIRST=1957, + XED_IFORMFL_SYSRET64_LAST=1957, + XED_IFORMFL_SYSRET_AMD_FIRST=1958, + XED_IFORMFL_SYSRET_AMD_LAST=1958, + XED_IFORMFL_T1MSKC_FIRST=1959, + XED_IFORMFL_T1MSKC_LAST=1962, + XED_IFORMFL_TDCALL_FIRST=1963, + XED_IFORMFL_TDCALL_LAST=1963, + XED_IFORMFL_TDPBF16PS_FIRST=1964, + XED_IFORMFL_TDPBF16PS_LAST=1964, + XED_IFORMFL_TDPBSSD_FIRST=1965, + XED_IFORMFL_TDPBSSD_LAST=1965, + XED_IFORMFL_TDPBSUD_FIRST=1966, + XED_IFORMFL_TDPBSUD_LAST=1966, + XED_IFORMFL_TDPBUSD_FIRST=1967, + XED_IFORMFL_TDPBUSD_LAST=1967, + XED_IFORMFL_TDPBUUD_FIRST=1968, + XED_IFORMFL_TDPBUUD_LAST=1968, + XED_IFORMFL_TEST_FIRST=1969, + XED_IFORMFL_TEST_LAST=1982, + XED_IFORMFL_TESTUI_FIRST=1983, + XED_IFORMFL_TESTUI_LAST=1983, + XED_IFORMFL_TILELOADD_FIRST=1984, + XED_IFORMFL_TILELOADD_LAST=1984, + XED_IFORMFL_TILELOADDT1_FIRST=1985, + XED_IFORMFL_TILELOADDT1_LAST=1985, + XED_IFORMFL_TILERELEASE_FIRST=1986, + XED_IFORMFL_TILERELEASE_LAST=1986, + XED_IFORMFL_TILESTORED_FIRST=1987, + XED_IFORMFL_TILESTORED_LAST=1987, + XED_IFORMFL_TILEZERO_FIRST=1988, + XED_IFORMFL_TILEZERO_LAST=1988, + XED_IFORMFL_TLBSYNC_FIRST=1989, + XED_IFORMFL_TLBSYNC_LAST=1989, + XED_IFORMFL_TPAUSE_FIRST=1990, + XED_IFORMFL_TPAUSE_LAST=1990, + XED_IFORMFL_TZCNT_FIRST=1991, + XED_IFORMFL_TZCNT_LAST=1992, + XED_IFORMFL_TZMSK_FIRST=1993, + XED_IFORMFL_TZMSK_LAST=1996, + XED_IFORMFL_UCOMISD_FIRST=1997, + XED_IFORMFL_UCOMISD_LAST=1998, + XED_IFORMFL_UCOMISS_FIRST=1999, + XED_IFORMFL_UCOMISS_LAST=2000, + XED_IFORMFL_UD0_FIRST=2001, + XED_IFORMFL_UD0_LAST=2003, + XED_IFORMFL_UD1_FIRST=2004, + XED_IFORMFL_UD1_LAST=2005, + XED_IFORMFL_UD2_FIRST=2006, + XED_IFORMFL_UD2_LAST=2006, + XED_IFORMFL_UIRET_FIRST=2007, + XED_IFORMFL_UIRET_LAST=2007, + XED_IFORMFL_UMONITOR_FIRST=2008, + XED_IFORMFL_UMONITOR_LAST=2008, + XED_IFORMFL_UMWAIT_FIRST=2009, + XED_IFORMFL_UMWAIT_LAST=2009, + XED_IFORMFL_UNPCKHPD_FIRST=2010, + XED_IFORMFL_UNPCKHPD_LAST=2011, + XED_IFORMFL_UNPCKHPS_FIRST=2012, + XED_IFORMFL_UNPCKHPS_LAST=2013, + XED_IFORMFL_UNPCKLPD_FIRST=2014, + XED_IFORMFL_UNPCKLPD_LAST=2015, + XED_IFORMFL_UNPCKLPS_FIRST=2016, + XED_IFORMFL_UNPCKLPS_LAST=2017, + XED_IFORMFL_V4FMADDPS_FIRST=2018, + XED_IFORMFL_V4FMADDPS_LAST=2018, + XED_IFORMFL_V4FMADDSS_FIRST=2019, + XED_IFORMFL_V4FMADDSS_LAST=2019, + XED_IFORMFL_V4FNMADDPS_FIRST=2020, + XED_IFORMFL_V4FNMADDPS_LAST=2020, + XED_IFORMFL_V4FNMADDSS_FIRST=2021, + XED_IFORMFL_V4FNMADDSS_LAST=2021, + XED_IFORMFL_VADDPD_FIRST=2022, + XED_IFORMFL_VADDPD_LAST=2031, + XED_IFORMFL_VADDPH_FIRST=2032, + XED_IFORMFL_VADDPH_LAST=2037, + XED_IFORMFL_VADDPS_FIRST=2038, + XED_IFORMFL_VADDPS_LAST=2047, + XED_IFORMFL_VADDSD_FIRST=2048, + XED_IFORMFL_VADDSD_LAST=2051, + XED_IFORMFL_VADDSH_FIRST=2052, + XED_IFORMFL_VADDSH_LAST=2053, + XED_IFORMFL_VADDSS_FIRST=2054, + XED_IFORMFL_VADDSS_LAST=2057, + XED_IFORMFL_VADDSUBPD_FIRST=2058, + XED_IFORMFL_VADDSUBPD_LAST=2061, + XED_IFORMFL_VADDSUBPS_FIRST=2062, + XED_IFORMFL_VADDSUBPS_LAST=2065, + XED_IFORMFL_VAESDEC_FIRST=2066, + XED_IFORMFL_VAESDEC_LAST=2075, + XED_IFORMFL_VAESDECLAST_FIRST=2076, + XED_IFORMFL_VAESDECLAST_LAST=2085, + XED_IFORMFL_VAESENC_FIRST=2086, + XED_IFORMFL_VAESENC_LAST=2095, + XED_IFORMFL_VAESENCLAST_FIRST=2096, + XED_IFORMFL_VAESENCLAST_LAST=2105, + XED_IFORMFL_VAESIMC_FIRST=2106, + XED_IFORMFL_VAESIMC_LAST=2107, + XED_IFORMFL_VAESKEYGENASSIST_FIRST=2108, + XED_IFORMFL_VAESKEYGENASSIST_LAST=2109, + XED_IFORMFL_VALIGND_FIRST=2110, + XED_IFORMFL_VALIGND_LAST=2115, + XED_IFORMFL_VALIGNQ_FIRST=2116, + XED_IFORMFL_VALIGNQ_LAST=2121, + XED_IFORMFL_VANDNPD_FIRST=2122, + XED_IFORMFL_VANDNPD_LAST=2131, + XED_IFORMFL_VANDNPS_FIRST=2132, + XED_IFORMFL_VANDNPS_LAST=2141, + XED_IFORMFL_VANDPD_FIRST=2142, + XED_IFORMFL_VANDPD_LAST=2151, + XED_IFORMFL_VANDPS_FIRST=2152, + XED_IFORMFL_VANDPS_LAST=2161, + XED_IFORMFL_VBLENDMPD_FIRST=2162, + XED_IFORMFL_VBLENDMPD_LAST=2167, + XED_IFORMFL_VBLENDMPS_FIRST=2168, + XED_IFORMFL_VBLENDMPS_LAST=2173, + XED_IFORMFL_VBLENDPD_FIRST=2174, + XED_IFORMFL_VBLENDPD_LAST=2177, + XED_IFORMFL_VBLENDPS_FIRST=2178, + XED_IFORMFL_VBLENDPS_LAST=2181, + XED_IFORMFL_VBLENDVPD_FIRST=2182, + XED_IFORMFL_VBLENDVPD_LAST=2185, + XED_IFORMFL_VBLENDVPS_FIRST=2186, + XED_IFORMFL_VBLENDVPS_LAST=2189, + XED_IFORMFL_VBROADCASTF128_FIRST=2190, + XED_IFORMFL_VBROADCASTF128_LAST=2190, + XED_IFORMFL_VBROADCASTF32X2_FIRST=2191, + XED_IFORMFL_VBROADCASTF32X2_LAST=2194, + XED_IFORMFL_VBROADCASTF32X4_FIRST=2195, + XED_IFORMFL_VBROADCASTF32X4_LAST=2196, + XED_IFORMFL_VBROADCASTF32X8_FIRST=2197, + XED_IFORMFL_VBROADCASTF32X8_LAST=2197, + XED_IFORMFL_VBROADCASTF64X2_FIRST=2198, + XED_IFORMFL_VBROADCASTF64X2_LAST=2199, + XED_IFORMFL_VBROADCASTF64X4_FIRST=2200, + XED_IFORMFL_VBROADCASTF64X4_LAST=2200, + XED_IFORMFL_VBROADCASTI128_FIRST=2201, + XED_IFORMFL_VBROADCASTI128_LAST=2201, + XED_IFORMFL_VBROADCASTI32X2_FIRST=2202, + XED_IFORMFL_VBROADCASTI32X2_LAST=2207, + XED_IFORMFL_VBROADCASTI32X4_FIRST=2208, + XED_IFORMFL_VBROADCASTI32X4_LAST=2209, + XED_IFORMFL_VBROADCASTI32X8_FIRST=2210, + XED_IFORMFL_VBROADCASTI32X8_LAST=2210, + XED_IFORMFL_VBROADCASTI64X2_FIRST=2211, + XED_IFORMFL_VBROADCASTI64X2_LAST=2212, + XED_IFORMFL_VBROADCASTI64X4_FIRST=2213, + XED_IFORMFL_VBROADCASTI64X4_LAST=2213, + XED_IFORMFL_VBROADCASTSD_FIRST=2214, + XED_IFORMFL_VBROADCASTSD_LAST=2219, + XED_IFORMFL_VBROADCASTSS_FIRST=2220, + XED_IFORMFL_VBROADCASTSS_LAST=2229, + XED_IFORMFL_VCMPPD_FIRST=2230, + XED_IFORMFL_VCMPPD_LAST=2239, + XED_IFORMFL_VCMPPH_FIRST=2240, + XED_IFORMFL_VCMPPH_LAST=2245, + XED_IFORMFL_VCMPPS_FIRST=2246, + XED_IFORMFL_VCMPPS_LAST=2255, + XED_IFORMFL_VCMPSD_FIRST=2256, + XED_IFORMFL_VCMPSD_LAST=2259, + XED_IFORMFL_VCMPSH_FIRST=2260, + XED_IFORMFL_VCMPSH_LAST=2261, + XED_IFORMFL_VCMPSS_FIRST=2262, + XED_IFORMFL_VCMPSS_LAST=2265, + XED_IFORMFL_VCOMISD_FIRST=2266, + XED_IFORMFL_VCOMISD_LAST=2269, + XED_IFORMFL_VCOMISH_FIRST=2270, + XED_IFORMFL_VCOMISH_LAST=2271, + XED_IFORMFL_VCOMISS_FIRST=2272, + XED_IFORMFL_VCOMISS_LAST=2275, + XED_IFORMFL_VCOMPRESSPD_FIRST=2276, + XED_IFORMFL_VCOMPRESSPD_LAST=2281, + XED_IFORMFL_VCOMPRESSPS_FIRST=2282, + XED_IFORMFL_VCOMPRESSPS_LAST=2287, + XED_IFORMFL_VCVTDQ2PD_FIRST=2288, + XED_IFORMFL_VCVTDQ2PD_LAST=2297, + XED_IFORMFL_VCVTDQ2PH_FIRST=2298, + XED_IFORMFL_VCVTDQ2PH_LAST=2303, + XED_IFORMFL_VCVTDQ2PS_FIRST=2304, + XED_IFORMFL_VCVTDQ2PS_LAST=2313, + XED_IFORMFL_VCVTNE2PS2BF16_FIRST=2314, + XED_IFORMFL_VCVTNE2PS2BF16_LAST=2319, + XED_IFORMFL_VCVTNEPS2BF16_FIRST=2320, + XED_IFORMFL_VCVTNEPS2BF16_LAST=2325, + XED_IFORMFL_VCVTPD2DQ_FIRST=2326, + XED_IFORMFL_VCVTPD2DQ_LAST=2335, + XED_IFORMFL_VCVTPD2PH_FIRST=2336, + XED_IFORMFL_VCVTPD2PH_LAST=2341, + XED_IFORMFL_VCVTPD2PS_FIRST=2342, + XED_IFORMFL_VCVTPD2PS_LAST=2351, + XED_IFORMFL_VCVTPD2QQ_FIRST=2352, + XED_IFORMFL_VCVTPD2QQ_LAST=2357, + XED_IFORMFL_VCVTPD2UDQ_FIRST=2358, + XED_IFORMFL_VCVTPD2UDQ_LAST=2363, + XED_IFORMFL_VCVTPD2UQQ_FIRST=2364, + XED_IFORMFL_VCVTPD2UQQ_LAST=2369, + XED_IFORMFL_VCVTPH2DQ_FIRST=2370, + XED_IFORMFL_VCVTPH2DQ_LAST=2375, + XED_IFORMFL_VCVTPH2PD_FIRST=2376, + XED_IFORMFL_VCVTPH2PD_LAST=2381, + XED_IFORMFL_VCVTPH2PS_FIRST=2382, + XED_IFORMFL_VCVTPH2PS_LAST=2391, + XED_IFORMFL_VCVTPH2PSX_FIRST=2392, + XED_IFORMFL_VCVTPH2PSX_LAST=2397, + XED_IFORMFL_VCVTPH2QQ_FIRST=2398, + XED_IFORMFL_VCVTPH2QQ_LAST=2403, + XED_IFORMFL_VCVTPH2UDQ_FIRST=2404, + XED_IFORMFL_VCVTPH2UDQ_LAST=2409, + XED_IFORMFL_VCVTPH2UQQ_FIRST=2410, + XED_IFORMFL_VCVTPH2UQQ_LAST=2415, + XED_IFORMFL_VCVTPH2UW_FIRST=2416, + XED_IFORMFL_VCVTPH2UW_LAST=2421, + XED_IFORMFL_VCVTPH2W_FIRST=2422, + XED_IFORMFL_VCVTPH2W_LAST=2427, + XED_IFORMFL_VCVTPS2DQ_FIRST=2428, + XED_IFORMFL_VCVTPS2DQ_LAST=2437, + XED_IFORMFL_VCVTPS2PD_FIRST=2438, + XED_IFORMFL_VCVTPS2PD_LAST=2447, + XED_IFORMFL_VCVTPS2PH_FIRST=2448, + XED_IFORMFL_VCVTPS2PH_LAST=2457, + XED_IFORMFL_VCVTPS2PHX_FIRST=2458, + XED_IFORMFL_VCVTPS2PHX_LAST=2463, + XED_IFORMFL_VCVTPS2QQ_FIRST=2464, + XED_IFORMFL_VCVTPS2QQ_LAST=2469, + XED_IFORMFL_VCVTPS2UDQ_FIRST=2470, + XED_IFORMFL_VCVTPS2UDQ_LAST=2475, + XED_IFORMFL_VCVTPS2UQQ_FIRST=2476, + XED_IFORMFL_VCVTPS2UQQ_LAST=2481, + XED_IFORMFL_VCVTQQ2PD_FIRST=2482, + XED_IFORMFL_VCVTQQ2PD_LAST=2487, + XED_IFORMFL_VCVTQQ2PH_FIRST=2488, + XED_IFORMFL_VCVTQQ2PH_LAST=2493, + XED_IFORMFL_VCVTQQ2PS_FIRST=2494, + XED_IFORMFL_VCVTQQ2PS_LAST=2499, + XED_IFORMFL_VCVTSD2SH_FIRST=2500, + XED_IFORMFL_VCVTSD2SH_LAST=2501, + XED_IFORMFL_VCVTSD2SI_FIRST=2502, + XED_IFORMFL_VCVTSD2SI_LAST=2509, + XED_IFORMFL_VCVTSD2SS_FIRST=2510, + XED_IFORMFL_VCVTSD2SS_LAST=2513, + XED_IFORMFL_VCVTSD2USI_FIRST=2514, + XED_IFORMFL_VCVTSD2USI_LAST=2517, + XED_IFORMFL_VCVTSH2SD_FIRST=2518, + XED_IFORMFL_VCVTSH2SD_LAST=2519, + XED_IFORMFL_VCVTSH2SI_FIRST=2520, + XED_IFORMFL_VCVTSH2SI_LAST=2523, + XED_IFORMFL_VCVTSH2SS_FIRST=2524, + XED_IFORMFL_VCVTSH2SS_LAST=2525, + XED_IFORMFL_VCVTSH2USI_FIRST=2526, + XED_IFORMFL_VCVTSH2USI_LAST=2529, + XED_IFORMFL_VCVTSI2SD_FIRST=2530, + XED_IFORMFL_VCVTSI2SD_LAST=2537, + XED_IFORMFL_VCVTSI2SH_FIRST=2538, + XED_IFORMFL_VCVTSI2SH_LAST=2541, + XED_IFORMFL_VCVTSI2SS_FIRST=2542, + XED_IFORMFL_VCVTSI2SS_LAST=2549, + XED_IFORMFL_VCVTSS2SD_FIRST=2550, + XED_IFORMFL_VCVTSS2SD_LAST=2553, + XED_IFORMFL_VCVTSS2SH_FIRST=2554, + XED_IFORMFL_VCVTSS2SH_LAST=2555, + XED_IFORMFL_VCVTSS2SI_FIRST=2556, + XED_IFORMFL_VCVTSS2SI_LAST=2563, + XED_IFORMFL_VCVTSS2USI_FIRST=2564, + XED_IFORMFL_VCVTSS2USI_LAST=2567, + XED_IFORMFL_VCVTTPD2DQ_FIRST=2568, + XED_IFORMFL_VCVTTPD2DQ_LAST=2577, + XED_IFORMFL_VCVTTPD2QQ_FIRST=2578, + XED_IFORMFL_VCVTTPD2QQ_LAST=2583, + XED_IFORMFL_VCVTTPD2UDQ_FIRST=2584, + XED_IFORMFL_VCVTTPD2UDQ_LAST=2589, + XED_IFORMFL_VCVTTPD2UQQ_FIRST=2590, + XED_IFORMFL_VCVTTPD2UQQ_LAST=2595, + XED_IFORMFL_VCVTTPH2DQ_FIRST=2596, + XED_IFORMFL_VCVTTPH2DQ_LAST=2601, + XED_IFORMFL_VCVTTPH2QQ_FIRST=2602, + XED_IFORMFL_VCVTTPH2QQ_LAST=2607, + XED_IFORMFL_VCVTTPH2UDQ_FIRST=2608, + XED_IFORMFL_VCVTTPH2UDQ_LAST=2613, + XED_IFORMFL_VCVTTPH2UQQ_FIRST=2614, + XED_IFORMFL_VCVTTPH2UQQ_LAST=2619, + XED_IFORMFL_VCVTTPH2UW_FIRST=2620, + XED_IFORMFL_VCVTTPH2UW_LAST=2625, + XED_IFORMFL_VCVTTPH2W_FIRST=2626, + XED_IFORMFL_VCVTTPH2W_LAST=2631, + XED_IFORMFL_VCVTTPS2DQ_FIRST=2632, + XED_IFORMFL_VCVTTPS2DQ_LAST=2641, + XED_IFORMFL_VCVTTPS2QQ_FIRST=2642, + XED_IFORMFL_VCVTTPS2QQ_LAST=2647, + XED_IFORMFL_VCVTTPS2UDQ_FIRST=2648, + XED_IFORMFL_VCVTTPS2UDQ_LAST=2653, + XED_IFORMFL_VCVTTPS2UQQ_FIRST=2654, + XED_IFORMFL_VCVTTPS2UQQ_LAST=2659, + XED_IFORMFL_VCVTTSD2SI_FIRST=2660, + XED_IFORMFL_VCVTTSD2SI_LAST=2667, + XED_IFORMFL_VCVTTSD2USI_FIRST=2668, + XED_IFORMFL_VCVTTSD2USI_LAST=2671, + XED_IFORMFL_VCVTTSH2SI_FIRST=2672, + XED_IFORMFL_VCVTTSH2SI_LAST=2675, + XED_IFORMFL_VCVTTSH2USI_FIRST=2676, + XED_IFORMFL_VCVTTSH2USI_LAST=2679, + XED_IFORMFL_VCVTTSS2SI_FIRST=2680, + XED_IFORMFL_VCVTTSS2SI_LAST=2687, + XED_IFORMFL_VCVTTSS2USI_FIRST=2688, + XED_IFORMFL_VCVTTSS2USI_LAST=2691, + XED_IFORMFL_VCVTUDQ2PD_FIRST=2692, + XED_IFORMFL_VCVTUDQ2PD_LAST=2697, + XED_IFORMFL_VCVTUDQ2PH_FIRST=2698, + XED_IFORMFL_VCVTUDQ2PH_LAST=2703, + XED_IFORMFL_VCVTUDQ2PS_FIRST=2704, + XED_IFORMFL_VCVTUDQ2PS_LAST=2709, + XED_IFORMFL_VCVTUQQ2PD_FIRST=2710, + XED_IFORMFL_VCVTUQQ2PD_LAST=2715, + XED_IFORMFL_VCVTUQQ2PH_FIRST=2716, + XED_IFORMFL_VCVTUQQ2PH_LAST=2721, + XED_IFORMFL_VCVTUQQ2PS_FIRST=2722, + XED_IFORMFL_VCVTUQQ2PS_LAST=2727, + XED_IFORMFL_VCVTUSI2SD_FIRST=2728, + XED_IFORMFL_VCVTUSI2SD_LAST=2731, + XED_IFORMFL_VCVTUSI2SH_FIRST=2732, + XED_IFORMFL_VCVTUSI2SH_LAST=2735, + XED_IFORMFL_VCVTUSI2SS_FIRST=2736, + XED_IFORMFL_VCVTUSI2SS_LAST=2739, + XED_IFORMFL_VCVTUW2PH_FIRST=2740, + XED_IFORMFL_VCVTUW2PH_LAST=2745, + XED_IFORMFL_VCVTW2PH_FIRST=2746, + XED_IFORMFL_VCVTW2PH_LAST=2751, + XED_IFORMFL_VDBPSADBW_FIRST=2752, + XED_IFORMFL_VDBPSADBW_LAST=2757, + XED_IFORMFL_VDIVPD_FIRST=2758, + XED_IFORMFL_VDIVPD_LAST=2767, + XED_IFORMFL_VDIVPH_FIRST=2768, + XED_IFORMFL_VDIVPH_LAST=2773, + XED_IFORMFL_VDIVPS_FIRST=2774, + XED_IFORMFL_VDIVPS_LAST=2783, + XED_IFORMFL_VDIVSD_FIRST=2784, + XED_IFORMFL_VDIVSD_LAST=2787, + XED_IFORMFL_VDIVSH_FIRST=2788, + XED_IFORMFL_VDIVSH_LAST=2789, + XED_IFORMFL_VDIVSS_FIRST=2790, + XED_IFORMFL_VDIVSS_LAST=2793, + XED_IFORMFL_VDPBF16PS_FIRST=2794, + XED_IFORMFL_VDPBF16PS_LAST=2799, + XED_IFORMFL_VDPPD_FIRST=2800, + XED_IFORMFL_VDPPD_LAST=2801, + XED_IFORMFL_VDPPS_FIRST=2802, + XED_IFORMFL_VDPPS_LAST=2805, + XED_IFORMFL_VERR_FIRST=2806, + XED_IFORMFL_VERR_LAST=2807, + XED_IFORMFL_VERW_FIRST=2808, + XED_IFORMFL_VERW_LAST=2809, + XED_IFORMFL_VEXP2PD_FIRST=2810, + XED_IFORMFL_VEXP2PD_LAST=2811, + XED_IFORMFL_VEXP2PS_FIRST=2812, + XED_IFORMFL_VEXP2PS_LAST=2813, + XED_IFORMFL_VEXPANDPD_FIRST=2814, + XED_IFORMFL_VEXPANDPD_LAST=2819, + XED_IFORMFL_VEXPANDPS_FIRST=2820, + XED_IFORMFL_VEXPANDPS_LAST=2825, + XED_IFORMFL_VEXTRACTF128_FIRST=2826, + XED_IFORMFL_VEXTRACTF128_LAST=2827, + XED_IFORMFL_VEXTRACTF32X4_FIRST=2828, + XED_IFORMFL_VEXTRACTF32X4_LAST=2831, + XED_IFORMFL_VEXTRACTF32X8_FIRST=2832, + XED_IFORMFL_VEXTRACTF32X8_LAST=2833, + XED_IFORMFL_VEXTRACTF64X2_FIRST=2834, + XED_IFORMFL_VEXTRACTF64X2_LAST=2837, + XED_IFORMFL_VEXTRACTF64X4_FIRST=2838, + XED_IFORMFL_VEXTRACTF64X4_LAST=2839, + XED_IFORMFL_VEXTRACTI128_FIRST=2840, + XED_IFORMFL_VEXTRACTI128_LAST=2841, + XED_IFORMFL_VEXTRACTI32X4_FIRST=2842, + XED_IFORMFL_VEXTRACTI32X4_LAST=2845, + XED_IFORMFL_VEXTRACTI32X8_FIRST=2846, + XED_IFORMFL_VEXTRACTI32X8_LAST=2847, + XED_IFORMFL_VEXTRACTI64X2_FIRST=2848, + XED_IFORMFL_VEXTRACTI64X2_LAST=2851, + XED_IFORMFL_VEXTRACTI64X4_FIRST=2852, + XED_IFORMFL_VEXTRACTI64X4_LAST=2853, + XED_IFORMFL_VEXTRACTPS_FIRST=2854, + XED_IFORMFL_VEXTRACTPS_LAST=2857, + XED_IFORMFL_VFCMADDCPH_FIRST=2858, + XED_IFORMFL_VFCMADDCPH_LAST=2863, + XED_IFORMFL_VFCMADDCSH_FIRST=2864, + XED_IFORMFL_VFCMADDCSH_LAST=2865, + XED_IFORMFL_VFCMULCPH_FIRST=2866, + XED_IFORMFL_VFCMULCPH_LAST=2871, + XED_IFORMFL_VFCMULCSH_FIRST=2872, + XED_IFORMFL_VFCMULCSH_LAST=2873, + XED_IFORMFL_VFIXUPIMMPD_FIRST=2874, + XED_IFORMFL_VFIXUPIMMPD_LAST=2879, + XED_IFORMFL_VFIXUPIMMPS_FIRST=2880, + XED_IFORMFL_VFIXUPIMMPS_LAST=2885, + XED_IFORMFL_VFIXUPIMMSD_FIRST=2886, + XED_IFORMFL_VFIXUPIMMSD_LAST=2887, + XED_IFORMFL_VFIXUPIMMSS_FIRST=2888, + XED_IFORMFL_VFIXUPIMMSS_LAST=2889, + XED_IFORMFL_VFMADD132PD_FIRST=2890, + XED_IFORMFL_VFMADD132PD_LAST=2899, + XED_IFORMFL_VFMADD132PH_FIRST=2900, + XED_IFORMFL_VFMADD132PH_LAST=2905, + XED_IFORMFL_VFMADD132PS_FIRST=2906, + XED_IFORMFL_VFMADD132PS_LAST=2915, + XED_IFORMFL_VFMADD132SD_FIRST=2916, + XED_IFORMFL_VFMADD132SD_LAST=2919, + XED_IFORMFL_VFMADD132SH_FIRST=2920, + XED_IFORMFL_VFMADD132SH_LAST=2921, + XED_IFORMFL_VFMADD132SS_FIRST=2922, + XED_IFORMFL_VFMADD132SS_LAST=2925, + XED_IFORMFL_VFMADD213PD_FIRST=2926, + XED_IFORMFL_VFMADD213PD_LAST=2935, + XED_IFORMFL_VFMADD213PH_FIRST=2936, + XED_IFORMFL_VFMADD213PH_LAST=2941, + XED_IFORMFL_VFMADD213PS_FIRST=2942, + XED_IFORMFL_VFMADD213PS_LAST=2951, + XED_IFORMFL_VFMADD213SD_FIRST=2952, + XED_IFORMFL_VFMADD213SD_LAST=2955, + XED_IFORMFL_VFMADD213SH_FIRST=2956, + XED_IFORMFL_VFMADD213SH_LAST=2957, + XED_IFORMFL_VFMADD213SS_FIRST=2958, + XED_IFORMFL_VFMADD213SS_LAST=2961, + XED_IFORMFL_VFMADD231PD_FIRST=2962, + XED_IFORMFL_VFMADD231PD_LAST=2971, + XED_IFORMFL_VFMADD231PH_FIRST=2972, + XED_IFORMFL_VFMADD231PH_LAST=2977, + XED_IFORMFL_VFMADD231PS_FIRST=2978, + XED_IFORMFL_VFMADD231PS_LAST=2987, + XED_IFORMFL_VFMADD231SD_FIRST=2988, + XED_IFORMFL_VFMADD231SD_LAST=2991, + XED_IFORMFL_VFMADD231SH_FIRST=2992, + XED_IFORMFL_VFMADD231SH_LAST=2993, + XED_IFORMFL_VFMADD231SS_FIRST=2994, + XED_IFORMFL_VFMADD231SS_LAST=2997, + XED_IFORMFL_VFMADDCPH_FIRST=2998, + XED_IFORMFL_VFMADDCPH_LAST=3003, + XED_IFORMFL_VFMADDCSH_FIRST=3004, + XED_IFORMFL_VFMADDCSH_LAST=3005, + XED_IFORMFL_VFMADDPD_FIRST=3006, + XED_IFORMFL_VFMADDPD_LAST=3011, + XED_IFORMFL_VFMADDPS_FIRST=3012, + XED_IFORMFL_VFMADDPS_LAST=3017, + XED_IFORMFL_VFMADDSD_FIRST=3018, + XED_IFORMFL_VFMADDSD_LAST=3020, + XED_IFORMFL_VFMADDSS_FIRST=3021, + XED_IFORMFL_VFMADDSS_LAST=3023, + XED_IFORMFL_VFMADDSUB132PD_FIRST=3024, + XED_IFORMFL_VFMADDSUB132PD_LAST=3033, + XED_IFORMFL_VFMADDSUB132PH_FIRST=3034, + XED_IFORMFL_VFMADDSUB132PH_LAST=3039, + XED_IFORMFL_VFMADDSUB132PS_FIRST=3040, + XED_IFORMFL_VFMADDSUB132PS_LAST=3049, + XED_IFORMFL_VFMADDSUB213PD_FIRST=3050, + XED_IFORMFL_VFMADDSUB213PD_LAST=3059, + XED_IFORMFL_VFMADDSUB213PH_FIRST=3060, + XED_IFORMFL_VFMADDSUB213PH_LAST=3065, + XED_IFORMFL_VFMADDSUB213PS_FIRST=3066, + XED_IFORMFL_VFMADDSUB213PS_LAST=3075, + XED_IFORMFL_VFMADDSUB231PD_FIRST=3076, + XED_IFORMFL_VFMADDSUB231PD_LAST=3085, + XED_IFORMFL_VFMADDSUB231PH_FIRST=3086, + XED_IFORMFL_VFMADDSUB231PH_LAST=3091, + XED_IFORMFL_VFMADDSUB231PS_FIRST=3092, + XED_IFORMFL_VFMADDSUB231PS_LAST=3101, + XED_IFORMFL_VFMADDSUBPD_FIRST=3102, + XED_IFORMFL_VFMADDSUBPD_LAST=3107, + XED_IFORMFL_VFMADDSUBPS_FIRST=3108, + XED_IFORMFL_VFMADDSUBPS_LAST=3113, + XED_IFORMFL_VFMSUB132PD_FIRST=3114, + XED_IFORMFL_VFMSUB132PD_LAST=3123, + XED_IFORMFL_VFMSUB132PH_FIRST=3124, + XED_IFORMFL_VFMSUB132PH_LAST=3129, + XED_IFORMFL_VFMSUB132PS_FIRST=3130, + XED_IFORMFL_VFMSUB132PS_LAST=3139, + XED_IFORMFL_VFMSUB132SD_FIRST=3140, + XED_IFORMFL_VFMSUB132SD_LAST=3143, + XED_IFORMFL_VFMSUB132SH_FIRST=3144, + XED_IFORMFL_VFMSUB132SH_LAST=3145, + XED_IFORMFL_VFMSUB132SS_FIRST=3146, + XED_IFORMFL_VFMSUB132SS_LAST=3149, + XED_IFORMFL_VFMSUB213PD_FIRST=3150, + XED_IFORMFL_VFMSUB213PD_LAST=3159, + XED_IFORMFL_VFMSUB213PH_FIRST=3160, + XED_IFORMFL_VFMSUB213PH_LAST=3165, + XED_IFORMFL_VFMSUB213PS_FIRST=3166, + XED_IFORMFL_VFMSUB213PS_LAST=3175, + XED_IFORMFL_VFMSUB213SD_FIRST=3176, + XED_IFORMFL_VFMSUB213SD_LAST=3179, + XED_IFORMFL_VFMSUB213SH_FIRST=3180, + XED_IFORMFL_VFMSUB213SH_LAST=3181, + XED_IFORMFL_VFMSUB213SS_FIRST=3182, + XED_IFORMFL_VFMSUB213SS_LAST=3185, + XED_IFORMFL_VFMSUB231PD_FIRST=3186, + XED_IFORMFL_VFMSUB231PD_LAST=3195, + XED_IFORMFL_VFMSUB231PH_FIRST=3196, + XED_IFORMFL_VFMSUB231PH_LAST=3201, + XED_IFORMFL_VFMSUB231PS_FIRST=3202, + XED_IFORMFL_VFMSUB231PS_LAST=3211, + XED_IFORMFL_VFMSUB231SD_FIRST=3212, + XED_IFORMFL_VFMSUB231SD_LAST=3215, + XED_IFORMFL_VFMSUB231SH_FIRST=3216, + XED_IFORMFL_VFMSUB231SH_LAST=3217, + XED_IFORMFL_VFMSUB231SS_FIRST=3218, + XED_IFORMFL_VFMSUB231SS_LAST=3221, + XED_IFORMFL_VFMSUBADD132PD_FIRST=3222, + XED_IFORMFL_VFMSUBADD132PD_LAST=3231, + XED_IFORMFL_VFMSUBADD132PH_FIRST=3232, + XED_IFORMFL_VFMSUBADD132PH_LAST=3237, + XED_IFORMFL_VFMSUBADD132PS_FIRST=3238, + XED_IFORMFL_VFMSUBADD132PS_LAST=3247, + XED_IFORMFL_VFMSUBADD213PD_FIRST=3248, + XED_IFORMFL_VFMSUBADD213PD_LAST=3257, + XED_IFORMFL_VFMSUBADD213PH_FIRST=3258, + XED_IFORMFL_VFMSUBADD213PH_LAST=3263, + XED_IFORMFL_VFMSUBADD213PS_FIRST=3264, + XED_IFORMFL_VFMSUBADD213PS_LAST=3273, + XED_IFORMFL_VFMSUBADD231PD_FIRST=3274, + XED_IFORMFL_VFMSUBADD231PD_LAST=3283, + XED_IFORMFL_VFMSUBADD231PH_FIRST=3284, + XED_IFORMFL_VFMSUBADD231PH_LAST=3289, + XED_IFORMFL_VFMSUBADD231PS_FIRST=3290, + XED_IFORMFL_VFMSUBADD231PS_LAST=3299, + XED_IFORMFL_VFMSUBADDPD_FIRST=3300, + XED_IFORMFL_VFMSUBADDPD_LAST=3305, + XED_IFORMFL_VFMSUBADDPS_FIRST=3306, + XED_IFORMFL_VFMSUBADDPS_LAST=3311, + XED_IFORMFL_VFMSUBPD_FIRST=3312, + XED_IFORMFL_VFMSUBPD_LAST=3317, + XED_IFORMFL_VFMSUBPS_FIRST=3318, + XED_IFORMFL_VFMSUBPS_LAST=3323, + XED_IFORMFL_VFMSUBSD_FIRST=3324, + XED_IFORMFL_VFMSUBSD_LAST=3326, + XED_IFORMFL_VFMSUBSS_FIRST=3327, + XED_IFORMFL_VFMSUBSS_LAST=3329, + XED_IFORMFL_VFMULCPH_FIRST=3330, + XED_IFORMFL_VFMULCPH_LAST=3335, + XED_IFORMFL_VFMULCSH_FIRST=3336, + XED_IFORMFL_VFMULCSH_LAST=3337, + XED_IFORMFL_VFNMADD132PD_FIRST=3338, + XED_IFORMFL_VFNMADD132PD_LAST=3347, + XED_IFORMFL_VFNMADD132PH_FIRST=3348, + XED_IFORMFL_VFNMADD132PH_LAST=3353, + XED_IFORMFL_VFNMADD132PS_FIRST=3354, + XED_IFORMFL_VFNMADD132PS_LAST=3363, + XED_IFORMFL_VFNMADD132SD_FIRST=3364, + XED_IFORMFL_VFNMADD132SD_LAST=3367, + XED_IFORMFL_VFNMADD132SH_FIRST=3368, + XED_IFORMFL_VFNMADD132SH_LAST=3369, + XED_IFORMFL_VFNMADD132SS_FIRST=3370, + XED_IFORMFL_VFNMADD132SS_LAST=3373, + XED_IFORMFL_VFNMADD213PD_FIRST=3374, + XED_IFORMFL_VFNMADD213PD_LAST=3383, + XED_IFORMFL_VFNMADD213PH_FIRST=3384, + XED_IFORMFL_VFNMADD213PH_LAST=3389, + XED_IFORMFL_VFNMADD213PS_FIRST=3390, + XED_IFORMFL_VFNMADD213PS_LAST=3399, + XED_IFORMFL_VFNMADD213SD_FIRST=3400, + XED_IFORMFL_VFNMADD213SD_LAST=3403, + XED_IFORMFL_VFNMADD213SH_FIRST=3404, + XED_IFORMFL_VFNMADD213SH_LAST=3405, + XED_IFORMFL_VFNMADD213SS_FIRST=3406, + XED_IFORMFL_VFNMADD213SS_LAST=3409, + XED_IFORMFL_VFNMADD231PD_FIRST=3410, + XED_IFORMFL_VFNMADD231PD_LAST=3419, + XED_IFORMFL_VFNMADD231PH_FIRST=3420, + XED_IFORMFL_VFNMADD231PH_LAST=3425, + XED_IFORMFL_VFNMADD231PS_FIRST=3426, + XED_IFORMFL_VFNMADD231PS_LAST=3435, + XED_IFORMFL_VFNMADD231SD_FIRST=3436, + XED_IFORMFL_VFNMADD231SD_LAST=3439, + XED_IFORMFL_VFNMADD231SH_FIRST=3440, + XED_IFORMFL_VFNMADD231SH_LAST=3441, + XED_IFORMFL_VFNMADD231SS_FIRST=3442, + XED_IFORMFL_VFNMADD231SS_LAST=3445, + XED_IFORMFL_VFNMADDPD_FIRST=3446, + XED_IFORMFL_VFNMADDPD_LAST=3451, + XED_IFORMFL_VFNMADDPS_FIRST=3452, + XED_IFORMFL_VFNMADDPS_LAST=3457, + XED_IFORMFL_VFNMADDSD_FIRST=3458, + XED_IFORMFL_VFNMADDSD_LAST=3460, + XED_IFORMFL_VFNMADDSS_FIRST=3461, + XED_IFORMFL_VFNMADDSS_LAST=3463, + XED_IFORMFL_VFNMSUB132PD_FIRST=3464, + XED_IFORMFL_VFNMSUB132PD_LAST=3473, + XED_IFORMFL_VFNMSUB132PH_FIRST=3474, + XED_IFORMFL_VFNMSUB132PH_LAST=3479, + XED_IFORMFL_VFNMSUB132PS_FIRST=3480, + XED_IFORMFL_VFNMSUB132PS_LAST=3489, + XED_IFORMFL_VFNMSUB132SD_FIRST=3490, + XED_IFORMFL_VFNMSUB132SD_LAST=3493, + XED_IFORMFL_VFNMSUB132SH_FIRST=3494, + XED_IFORMFL_VFNMSUB132SH_LAST=3495, + XED_IFORMFL_VFNMSUB132SS_FIRST=3496, + XED_IFORMFL_VFNMSUB132SS_LAST=3499, + XED_IFORMFL_VFNMSUB213PD_FIRST=3500, + XED_IFORMFL_VFNMSUB213PD_LAST=3509, + XED_IFORMFL_VFNMSUB213PH_FIRST=3510, + XED_IFORMFL_VFNMSUB213PH_LAST=3515, + XED_IFORMFL_VFNMSUB213PS_FIRST=3516, + XED_IFORMFL_VFNMSUB213PS_LAST=3525, + XED_IFORMFL_VFNMSUB213SD_FIRST=3526, + XED_IFORMFL_VFNMSUB213SD_LAST=3529, + XED_IFORMFL_VFNMSUB213SH_FIRST=3530, + XED_IFORMFL_VFNMSUB213SH_LAST=3531, + XED_IFORMFL_VFNMSUB213SS_FIRST=3532, + XED_IFORMFL_VFNMSUB213SS_LAST=3535, + XED_IFORMFL_VFNMSUB231PD_FIRST=3536, + XED_IFORMFL_VFNMSUB231PD_LAST=3545, + XED_IFORMFL_VFNMSUB231PH_FIRST=3546, + XED_IFORMFL_VFNMSUB231PH_LAST=3551, + XED_IFORMFL_VFNMSUB231PS_FIRST=3552, + XED_IFORMFL_VFNMSUB231PS_LAST=3561, + XED_IFORMFL_VFNMSUB231SD_FIRST=3562, + XED_IFORMFL_VFNMSUB231SD_LAST=3565, + XED_IFORMFL_VFNMSUB231SH_FIRST=3566, + XED_IFORMFL_VFNMSUB231SH_LAST=3567, + XED_IFORMFL_VFNMSUB231SS_FIRST=3568, + XED_IFORMFL_VFNMSUB231SS_LAST=3571, + XED_IFORMFL_VFNMSUBPD_FIRST=3572, + XED_IFORMFL_VFNMSUBPD_LAST=3577, + XED_IFORMFL_VFNMSUBPS_FIRST=3578, + XED_IFORMFL_VFNMSUBPS_LAST=3583, + XED_IFORMFL_VFNMSUBSD_FIRST=3584, + XED_IFORMFL_VFNMSUBSD_LAST=3586, + XED_IFORMFL_VFNMSUBSS_FIRST=3587, + XED_IFORMFL_VFNMSUBSS_LAST=3589, + XED_IFORMFL_VFPCLASSPD_FIRST=3590, + XED_IFORMFL_VFPCLASSPD_LAST=3595, + XED_IFORMFL_VFPCLASSPH_FIRST=3596, + XED_IFORMFL_VFPCLASSPH_LAST=3601, + XED_IFORMFL_VFPCLASSPS_FIRST=3602, + XED_IFORMFL_VFPCLASSPS_LAST=3607, + XED_IFORMFL_VFPCLASSSD_FIRST=3608, + XED_IFORMFL_VFPCLASSSD_LAST=3609, + XED_IFORMFL_VFPCLASSSH_FIRST=3610, + XED_IFORMFL_VFPCLASSSH_LAST=3611, + XED_IFORMFL_VFPCLASSSS_FIRST=3612, + XED_IFORMFL_VFPCLASSSS_LAST=3613, + XED_IFORMFL_VFRCZPD_FIRST=3614, + XED_IFORMFL_VFRCZPD_LAST=3617, + XED_IFORMFL_VFRCZPS_FIRST=3618, + XED_IFORMFL_VFRCZPS_LAST=3621, + XED_IFORMFL_VFRCZSD_FIRST=3622, + XED_IFORMFL_VFRCZSD_LAST=3623, + XED_IFORMFL_VFRCZSS_FIRST=3624, + XED_IFORMFL_VFRCZSS_LAST=3625, + XED_IFORMFL_VGATHERDPD_FIRST=3626, + XED_IFORMFL_VGATHERDPD_LAST=3630, + XED_IFORMFL_VGATHERDPS_FIRST=3631, + XED_IFORMFL_VGATHERDPS_LAST=3635, + XED_IFORMFL_VGATHERPF0DPD_FIRST=3636, + XED_IFORMFL_VGATHERPF0DPD_LAST=3636, + XED_IFORMFL_VGATHERPF0DPS_FIRST=3637, + XED_IFORMFL_VGATHERPF0DPS_LAST=3637, + XED_IFORMFL_VGATHERPF0QPD_FIRST=3638, + XED_IFORMFL_VGATHERPF0QPD_LAST=3638, + XED_IFORMFL_VGATHERPF0QPS_FIRST=3639, + XED_IFORMFL_VGATHERPF0QPS_LAST=3639, + XED_IFORMFL_VGATHERPF1DPD_FIRST=3640, + XED_IFORMFL_VGATHERPF1DPD_LAST=3640, + XED_IFORMFL_VGATHERPF1DPS_FIRST=3641, + XED_IFORMFL_VGATHERPF1DPS_LAST=3641, + XED_IFORMFL_VGATHERPF1QPD_FIRST=3642, + XED_IFORMFL_VGATHERPF1QPD_LAST=3642, + XED_IFORMFL_VGATHERPF1QPS_FIRST=3643, + XED_IFORMFL_VGATHERPF1QPS_LAST=3643, + XED_IFORMFL_VGATHERQPD_FIRST=3644, + XED_IFORMFL_VGATHERQPD_LAST=3648, + XED_IFORMFL_VGATHERQPS_FIRST=3649, + XED_IFORMFL_VGATHERQPS_LAST=3653, + XED_IFORMFL_VGETEXPPD_FIRST=3654, + XED_IFORMFL_VGETEXPPD_LAST=3659, + XED_IFORMFL_VGETEXPPH_FIRST=3660, + XED_IFORMFL_VGETEXPPH_LAST=3665, + XED_IFORMFL_VGETEXPPS_FIRST=3666, + XED_IFORMFL_VGETEXPPS_LAST=3671, + XED_IFORMFL_VGETEXPSD_FIRST=3672, + XED_IFORMFL_VGETEXPSD_LAST=3673, + XED_IFORMFL_VGETEXPSH_FIRST=3674, + XED_IFORMFL_VGETEXPSH_LAST=3675, + XED_IFORMFL_VGETEXPSS_FIRST=3676, + XED_IFORMFL_VGETEXPSS_LAST=3677, + XED_IFORMFL_VGETMANTPD_FIRST=3678, + XED_IFORMFL_VGETMANTPD_LAST=3683, + XED_IFORMFL_VGETMANTPH_FIRST=3684, + XED_IFORMFL_VGETMANTPH_LAST=3689, + XED_IFORMFL_VGETMANTPS_FIRST=3690, + XED_IFORMFL_VGETMANTPS_LAST=3695, + XED_IFORMFL_VGETMANTSD_FIRST=3696, + XED_IFORMFL_VGETMANTSD_LAST=3697, + XED_IFORMFL_VGETMANTSH_FIRST=3698, + XED_IFORMFL_VGETMANTSH_LAST=3699, + XED_IFORMFL_VGETMANTSS_FIRST=3700, + XED_IFORMFL_VGETMANTSS_LAST=3701, + XED_IFORMFL_VGF2P8AFFINEINVQB_FIRST=3702, + XED_IFORMFL_VGF2P8AFFINEINVQB_LAST=3711, + XED_IFORMFL_VGF2P8AFFINEQB_FIRST=3712, + XED_IFORMFL_VGF2P8AFFINEQB_LAST=3721, + XED_IFORMFL_VGF2P8MULB_FIRST=3722, + XED_IFORMFL_VGF2P8MULB_LAST=3731, + XED_IFORMFL_VHADDPD_FIRST=3732, + XED_IFORMFL_VHADDPD_LAST=3735, + XED_IFORMFL_VHADDPS_FIRST=3736, + XED_IFORMFL_VHADDPS_LAST=3739, + XED_IFORMFL_VHSUBPD_FIRST=3740, + XED_IFORMFL_VHSUBPD_LAST=3743, + XED_IFORMFL_VHSUBPS_FIRST=3744, + XED_IFORMFL_VHSUBPS_LAST=3747, + XED_IFORMFL_VINSERTF128_FIRST=3748, + XED_IFORMFL_VINSERTF128_LAST=3749, + XED_IFORMFL_VINSERTF32X4_FIRST=3750, + XED_IFORMFL_VINSERTF32X4_LAST=3753, + XED_IFORMFL_VINSERTF32X8_FIRST=3754, + XED_IFORMFL_VINSERTF32X8_LAST=3755, + XED_IFORMFL_VINSERTF64X2_FIRST=3756, + XED_IFORMFL_VINSERTF64X2_LAST=3759, + XED_IFORMFL_VINSERTF64X4_FIRST=3760, + XED_IFORMFL_VINSERTF64X4_LAST=3761, + XED_IFORMFL_VINSERTI128_FIRST=3762, + XED_IFORMFL_VINSERTI128_LAST=3763, + XED_IFORMFL_VINSERTI32X4_FIRST=3764, + XED_IFORMFL_VINSERTI32X4_LAST=3767, + XED_IFORMFL_VINSERTI32X8_FIRST=3768, + XED_IFORMFL_VINSERTI32X8_LAST=3769, + XED_IFORMFL_VINSERTI64X2_FIRST=3770, + XED_IFORMFL_VINSERTI64X2_LAST=3773, + XED_IFORMFL_VINSERTI64X4_FIRST=3774, + XED_IFORMFL_VINSERTI64X4_LAST=3775, + XED_IFORMFL_VINSERTPS_FIRST=3776, + XED_IFORMFL_VINSERTPS_LAST=3779, + XED_IFORMFL_VLDDQU_FIRST=3780, + XED_IFORMFL_VLDDQU_LAST=3781, + XED_IFORMFL_VLDMXCSR_FIRST=3782, + XED_IFORMFL_VLDMXCSR_LAST=3782, + XED_IFORMFL_VMASKMOVDQU_FIRST=3783, + XED_IFORMFL_VMASKMOVDQU_LAST=3783, + XED_IFORMFL_VMASKMOVPD_FIRST=3784, + XED_IFORMFL_VMASKMOVPD_LAST=3787, + XED_IFORMFL_VMASKMOVPS_FIRST=3788, + XED_IFORMFL_VMASKMOVPS_LAST=3791, + XED_IFORMFL_VMAXPD_FIRST=3792, + XED_IFORMFL_VMAXPD_LAST=3801, + XED_IFORMFL_VMAXPH_FIRST=3802, + XED_IFORMFL_VMAXPH_LAST=3807, + XED_IFORMFL_VMAXPS_FIRST=3808, + XED_IFORMFL_VMAXPS_LAST=3817, + XED_IFORMFL_VMAXSD_FIRST=3818, + XED_IFORMFL_VMAXSD_LAST=3821, + XED_IFORMFL_VMAXSH_FIRST=3822, + XED_IFORMFL_VMAXSH_LAST=3823, + XED_IFORMFL_VMAXSS_FIRST=3824, + XED_IFORMFL_VMAXSS_LAST=3827, + XED_IFORMFL_VMCALL_FIRST=3828, + XED_IFORMFL_VMCALL_LAST=3828, + XED_IFORMFL_VMCLEAR_FIRST=3829, + XED_IFORMFL_VMCLEAR_LAST=3829, + XED_IFORMFL_VMFUNC_FIRST=3830, + XED_IFORMFL_VMFUNC_LAST=3830, + XED_IFORMFL_VMINPD_FIRST=3831, + XED_IFORMFL_VMINPD_LAST=3840, + XED_IFORMFL_VMINPH_FIRST=3841, + XED_IFORMFL_VMINPH_LAST=3846, + XED_IFORMFL_VMINPS_FIRST=3847, + XED_IFORMFL_VMINPS_LAST=3856, + XED_IFORMFL_VMINSD_FIRST=3857, + XED_IFORMFL_VMINSD_LAST=3860, + XED_IFORMFL_VMINSH_FIRST=3861, + XED_IFORMFL_VMINSH_LAST=3862, + XED_IFORMFL_VMINSS_FIRST=3863, + XED_IFORMFL_VMINSS_LAST=3866, + XED_IFORMFL_VMLAUNCH_FIRST=3867, + XED_IFORMFL_VMLAUNCH_LAST=3867, + XED_IFORMFL_VMLOAD_FIRST=3868, + XED_IFORMFL_VMLOAD_LAST=3868, + XED_IFORMFL_VMMCALL_FIRST=3869, + XED_IFORMFL_VMMCALL_LAST=3869, + XED_IFORMFL_VMOVAPD_FIRST=3870, + XED_IFORMFL_VMOVAPD_LAST=3886, + XED_IFORMFL_VMOVAPS_FIRST=3887, + XED_IFORMFL_VMOVAPS_LAST=3903, + XED_IFORMFL_VMOVD_FIRST=3904, + XED_IFORMFL_VMOVD_LAST=3911, + XED_IFORMFL_VMOVDDUP_FIRST=3912, + XED_IFORMFL_VMOVDDUP_LAST=3921, + XED_IFORMFL_VMOVDQA_FIRST=3922, + XED_IFORMFL_VMOVDQA_LAST=3929, + XED_IFORMFL_VMOVDQA32_FIRST=3930, + XED_IFORMFL_VMOVDQA32_LAST=3938, + XED_IFORMFL_VMOVDQA64_FIRST=3939, + XED_IFORMFL_VMOVDQA64_LAST=3947, + XED_IFORMFL_VMOVDQU_FIRST=3948, + XED_IFORMFL_VMOVDQU_LAST=3955, + XED_IFORMFL_VMOVDQU16_FIRST=3956, + XED_IFORMFL_VMOVDQU16_LAST=3964, + XED_IFORMFL_VMOVDQU32_FIRST=3965, + XED_IFORMFL_VMOVDQU32_LAST=3973, + XED_IFORMFL_VMOVDQU64_FIRST=3974, + XED_IFORMFL_VMOVDQU64_LAST=3982, + XED_IFORMFL_VMOVDQU8_FIRST=3983, + XED_IFORMFL_VMOVDQU8_LAST=3991, + XED_IFORMFL_VMOVHLPS_FIRST=3992, + XED_IFORMFL_VMOVHLPS_LAST=3993, + XED_IFORMFL_VMOVHPD_FIRST=3994, + XED_IFORMFL_VMOVHPD_LAST=3997, + XED_IFORMFL_VMOVHPS_FIRST=3998, + XED_IFORMFL_VMOVHPS_LAST=4001, + XED_IFORMFL_VMOVLHPS_FIRST=4002, + XED_IFORMFL_VMOVLHPS_LAST=4003, + XED_IFORMFL_VMOVLPD_FIRST=4004, + XED_IFORMFL_VMOVLPD_LAST=4007, + XED_IFORMFL_VMOVLPS_FIRST=4008, + XED_IFORMFL_VMOVLPS_LAST=4011, + XED_IFORMFL_VMOVMSKPD_FIRST=4012, + XED_IFORMFL_VMOVMSKPD_LAST=4013, + XED_IFORMFL_VMOVMSKPS_FIRST=4014, + XED_IFORMFL_VMOVMSKPS_LAST=4015, + XED_IFORMFL_VMOVNTDQ_FIRST=4016, + XED_IFORMFL_VMOVNTDQ_LAST=4020, + XED_IFORMFL_VMOVNTDQA_FIRST=4021, + XED_IFORMFL_VMOVNTDQA_LAST=4025, + XED_IFORMFL_VMOVNTPD_FIRST=4026, + XED_IFORMFL_VMOVNTPD_LAST=4030, + XED_IFORMFL_VMOVNTPS_FIRST=4031, + XED_IFORMFL_VMOVNTPS_LAST=4035, + XED_IFORMFL_VMOVQ_FIRST=4036, + XED_IFORMFL_VMOVQ_LAST=4048, + XED_IFORMFL_VMOVSD_FIRST=4049, + XED_IFORMFL_VMOVSD_LAST=4055, + XED_IFORMFL_VMOVSH_FIRST=4056, + XED_IFORMFL_VMOVSH_LAST=4058, + XED_IFORMFL_VMOVSHDUP_FIRST=4059, + XED_IFORMFL_VMOVSHDUP_LAST=4068, + XED_IFORMFL_VMOVSLDUP_FIRST=4069, + XED_IFORMFL_VMOVSLDUP_LAST=4078, + XED_IFORMFL_VMOVSS_FIRST=4079, + XED_IFORMFL_VMOVSS_LAST=4085, + XED_IFORMFL_VMOVUPD_FIRST=4086, + XED_IFORMFL_VMOVUPD_LAST=4102, + XED_IFORMFL_VMOVUPS_FIRST=4103, + XED_IFORMFL_VMOVUPS_LAST=4119, + XED_IFORMFL_VMOVW_FIRST=4120, + XED_IFORMFL_VMOVW_LAST=4123, + XED_IFORMFL_VMPSADBW_FIRST=4124, + XED_IFORMFL_VMPSADBW_LAST=4127, + XED_IFORMFL_VMPTRLD_FIRST=4128, + XED_IFORMFL_VMPTRLD_LAST=4128, + XED_IFORMFL_VMPTRST_FIRST=4129, + XED_IFORMFL_VMPTRST_LAST=4129, + XED_IFORMFL_VMREAD_FIRST=4130, + XED_IFORMFL_VMREAD_LAST=4133, + XED_IFORMFL_VMRESUME_FIRST=4134, + XED_IFORMFL_VMRESUME_LAST=4134, + XED_IFORMFL_VMRUN_FIRST=4135, + XED_IFORMFL_VMRUN_LAST=4135, + XED_IFORMFL_VMSAVE_FIRST=4136, + XED_IFORMFL_VMSAVE_LAST=4136, + XED_IFORMFL_VMULPD_FIRST=4137, + XED_IFORMFL_VMULPD_LAST=4146, + XED_IFORMFL_VMULPH_FIRST=4147, + XED_IFORMFL_VMULPH_LAST=4152, + XED_IFORMFL_VMULPS_FIRST=4153, + XED_IFORMFL_VMULPS_LAST=4162, + XED_IFORMFL_VMULSD_FIRST=4163, + XED_IFORMFL_VMULSD_LAST=4166, + XED_IFORMFL_VMULSH_FIRST=4167, + XED_IFORMFL_VMULSH_LAST=4168, + XED_IFORMFL_VMULSS_FIRST=4169, + XED_IFORMFL_VMULSS_LAST=4172, + XED_IFORMFL_VMWRITE_FIRST=4173, + XED_IFORMFL_VMWRITE_LAST=4176, + XED_IFORMFL_VMXOFF_FIRST=4177, + XED_IFORMFL_VMXOFF_LAST=4177, + XED_IFORMFL_VMXON_FIRST=4178, + XED_IFORMFL_VMXON_LAST=4178, + XED_IFORMFL_VORPD_FIRST=4179, + XED_IFORMFL_VORPD_LAST=4188, + XED_IFORMFL_VORPS_FIRST=4189, + XED_IFORMFL_VORPS_LAST=4198, + XED_IFORMFL_VP2INTERSECTD_FIRST=4199, + XED_IFORMFL_VP2INTERSECTD_LAST=4204, + XED_IFORMFL_VP2INTERSECTQ_FIRST=4205, + XED_IFORMFL_VP2INTERSECTQ_LAST=4210, + XED_IFORMFL_VP4DPWSSD_FIRST=4211, + XED_IFORMFL_VP4DPWSSD_LAST=4211, + XED_IFORMFL_VP4DPWSSDS_FIRST=4212, + XED_IFORMFL_VP4DPWSSDS_LAST=4212, + XED_IFORMFL_VPABSB_FIRST=4213, + XED_IFORMFL_VPABSB_LAST=4222, + XED_IFORMFL_VPABSD_FIRST=4223, + XED_IFORMFL_VPABSD_LAST=4232, + XED_IFORMFL_VPABSQ_FIRST=4233, + XED_IFORMFL_VPABSQ_LAST=4238, + XED_IFORMFL_VPABSW_FIRST=4239, + XED_IFORMFL_VPABSW_LAST=4248, + XED_IFORMFL_VPACKSSDW_FIRST=4249, + XED_IFORMFL_VPACKSSDW_LAST=4258, + XED_IFORMFL_VPACKSSWB_FIRST=4259, + XED_IFORMFL_VPACKSSWB_LAST=4268, + XED_IFORMFL_VPACKUSDW_FIRST=4269, + XED_IFORMFL_VPACKUSDW_LAST=4278, + XED_IFORMFL_VPACKUSWB_FIRST=4279, + XED_IFORMFL_VPACKUSWB_LAST=4288, + XED_IFORMFL_VPADDB_FIRST=4289, + XED_IFORMFL_VPADDB_LAST=4298, + XED_IFORMFL_VPADDD_FIRST=4299, + XED_IFORMFL_VPADDD_LAST=4308, + XED_IFORMFL_VPADDQ_FIRST=4309, + XED_IFORMFL_VPADDQ_LAST=4318, + XED_IFORMFL_VPADDSB_FIRST=4319, + XED_IFORMFL_VPADDSB_LAST=4328, + XED_IFORMFL_VPADDSW_FIRST=4329, + XED_IFORMFL_VPADDSW_LAST=4338, + XED_IFORMFL_VPADDUSB_FIRST=4339, + XED_IFORMFL_VPADDUSB_LAST=4348, + XED_IFORMFL_VPADDUSW_FIRST=4349, + XED_IFORMFL_VPADDUSW_LAST=4358, + XED_IFORMFL_VPADDW_FIRST=4359, + XED_IFORMFL_VPADDW_LAST=4368, + XED_IFORMFL_VPALIGNR_FIRST=4369, + XED_IFORMFL_VPALIGNR_LAST=4378, + XED_IFORMFL_VPAND_FIRST=4379, + XED_IFORMFL_VPAND_LAST=4382, + XED_IFORMFL_VPANDD_FIRST=4383, + XED_IFORMFL_VPANDD_LAST=4388, + XED_IFORMFL_VPANDN_FIRST=4389, + XED_IFORMFL_VPANDN_LAST=4392, + XED_IFORMFL_VPANDND_FIRST=4393, + XED_IFORMFL_VPANDND_LAST=4398, + XED_IFORMFL_VPANDNQ_FIRST=4399, + XED_IFORMFL_VPANDNQ_LAST=4404, + XED_IFORMFL_VPANDQ_FIRST=4405, + XED_IFORMFL_VPANDQ_LAST=4410, + XED_IFORMFL_VPAVGB_FIRST=4411, + XED_IFORMFL_VPAVGB_LAST=4420, + XED_IFORMFL_VPAVGW_FIRST=4421, + XED_IFORMFL_VPAVGW_LAST=4430, + XED_IFORMFL_VPBLENDD_FIRST=4431, + XED_IFORMFL_VPBLENDD_LAST=4434, + XED_IFORMFL_VPBLENDMB_FIRST=4435, + XED_IFORMFL_VPBLENDMB_LAST=4440, + XED_IFORMFL_VPBLENDMD_FIRST=4441, + XED_IFORMFL_VPBLENDMD_LAST=4446, + XED_IFORMFL_VPBLENDMQ_FIRST=4447, + XED_IFORMFL_VPBLENDMQ_LAST=4452, + XED_IFORMFL_VPBLENDMW_FIRST=4453, + XED_IFORMFL_VPBLENDMW_LAST=4458, + XED_IFORMFL_VPBLENDVB_FIRST=4459, + XED_IFORMFL_VPBLENDVB_LAST=4462, + XED_IFORMFL_VPBLENDW_FIRST=4463, + XED_IFORMFL_VPBLENDW_LAST=4466, + XED_IFORMFL_VPBROADCASTB_FIRST=4467, + XED_IFORMFL_VPBROADCASTB_LAST=4479, + XED_IFORMFL_VPBROADCASTD_FIRST=4480, + XED_IFORMFL_VPBROADCASTD_LAST=4492, + XED_IFORMFL_VPBROADCASTMB2Q_FIRST=4493, + XED_IFORMFL_VPBROADCASTMB2Q_LAST=4495, + XED_IFORMFL_VPBROADCASTMW2D_FIRST=4496, + XED_IFORMFL_VPBROADCASTMW2D_LAST=4498, + XED_IFORMFL_VPBROADCASTQ_FIRST=4499, + XED_IFORMFL_VPBROADCASTQ_LAST=4511, + XED_IFORMFL_VPBROADCASTW_FIRST=4512, + XED_IFORMFL_VPBROADCASTW_LAST=4524, + XED_IFORMFL_VPCLMULQDQ_FIRST=4525, + XED_IFORMFL_VPCLMULQDQ_LAST=4534, + XED_IFORMFL_VPCMOV_FIRST=4535, + XED_IFORMFL_VPCMOV_LAST=4540, + XED_IFORMFL_VPCMPB_FIRST=4541, + XED_IFORMFL_VPCMPB_LAST=4546, + XED_IFORMFL_VPCMPD_FIRST=4547, + XED_IFORMFL_VPCMPD_LAST=4552, + XED_IFORMFL_VPCMPEQB_FIRST=4553, + XED_IFORMFL_VPCMPEQB_LAST=4562, + XED_IFORMFL_VPCMPEQD_FIRST=4563, + XED_IFORMFL_VPCMPEQD_LAST=4572, + XED_IFORMFL_VPCMPEQQ_FIRST=4573, + XED_IFORMFL_VPCMPEQQ_LAST=4582, + XED_IFORMFL_VPCMPEQW_FIRST=4583, + XED_IFORMFL_VPCMPEQW_LAST=4592, + XED_IFORMFL_VPCMPESTRI_FIRST=4593, + XED_IFORMFL_VPCMPESTRI_LAST=4594, + XED_IFORMFL_VPCMPESTRI64_FIRST=4595, + XED_IFORMFL_VPCMPESTRI64_LAST=4596, + XED_IFORMFL_VPCMPESTRM_FIRST=4597, + XED_IFORMFL_VPCMPESTRM_LAST=4598, + XED_IFORMFL_VPCMPESTRM64_FIRST=4599, + XED_IFORMFL_VPCMPESTRM64_LAST=4600, + XED_IFORMFL_VPCMPGTB_FIRST=4601, + XED_IFORMFL_VPCMPGTB_LAST=4610, + XED_IFORMFL_VPCMPGTD_FIRST=4611, + XED_IFORMFL_VPCMPGTD_LAST=4620, + XED_IFORMFL_VPCMPGTQ_FIRST=4621, + XED_IFORMFL_VPCMPGTQ_LAST=4630, + XED_IFORMFL_VPCMPGTW_FIRST=4631, + XED_IFORMFL_VPCMPGTW_LAST=4640, + XED_IFORMFL_VPCMPISTRI_FIRST=4641, + XED_IFORMFL_VPCMPISTRI_LAST=4642, + XED_IFORMFL_VPCMPISTRI64_FIRST=4643, + XED_IFORMFL_VPCMPISTRI64_LAST=4644, + XED_IFORMFL_VPCMPISTRM_FIRST=4645, + XED_IFORMFL_VPCMPISTRM_LAST=4646, + XED_IFORMFL_VPCMPQ_FIRST=4647, + XED_IFORMFL_VPCMPQ_LAST=4652, + XED_IFORMFL_VPCMPUB_FIRST=4653, + XED_IFORMFL_VPCMPUB_LAST=4658, + XED_IFORMFL_VPCMPUD_FIRST=4659, + XED_IFORMFL_VPCMPUD_LAST=4664, + XED_IFORMFL_VPCMPUQ_FIRST=4665, + XED_IFORMFL_VPCMPUQ_LAST=4670, + XED_IFORMFL_VPCMPUW_FIRST=4671, + XED_IFORMFL_VPCMPUW_LAST=4676, + XED_IFORMFL_VPCMPW_FIRST=4677, + XED_IFORMFL_VPCMPW_LAST=4682, + XED_IFORMFL_VPCOMB_FIRST=4683, + XED_IFORMFL_VPCOMB_LAST=4684, + XED_IFORMFL_VPCOMD_FIRST=4685, + XED_IFORMFL_VPCOMD_LAST=4686, + XED_IFORMFL_VPCOMPRESSB_FIRST=4687, + XED_IFORMFL_VPCOMPRESSB_LAST=4692, + XED_IFORMFL_VPCOMPRESSD_FIRST=4693, + XED_IFORMFL_VPCOMPRESSD_LAST=4698, + XED_IFORMFL_VPCOMPRESSQ_FIRST=4699, + XED_IFORMFL_VPCOMPRESSQ_LAST=4704, + XED_IFORMFL_VPCOMPRESSW_FIRST=4705, + XED_IFORMFL_VPCOMPRESSW_LAST=4710, + XED_IFORMFL_VPCOMQ_FIRST=4711, + XED_IFORMFL_VPCOMQ_LAST=4712, + XED_IFORMFL_VPCOMUB_FIRST=4713, + XED_IFORMFL_VPCOMUB_LAST=4714, + XED_IFORMFL_VPCOMUD_FIRST=4715, + XED_IFORMFL_VPCOMUD_LAST=4716, + XED_IFORMFL_VPCOMUQ_FIRST=4717, + XED_IFORMFL_VPCOMUQ_LAST=4718, + XED_IFORMFL_VPCOMUW_FIRST=4719, + XED_IFORMFL_VPCOMUW_LAST=4720, + XED_IFORMFL_VPCOMW_FIRST=4721, + XED_IFORMFL_VPCOMW_LAST=4722, + XED_IFORMFL_VPCONFLICTD_FIRST=4723, + XED_IFORMFL_VPCONFLICTD_LAST=4728, + XED_IFORMFL_VPCONFLICTQ_FIRST=4729, + XED_IFORMFL_VPCONFLICTQ_LAST=4734, + XED_IFORMFL_VPDPBUSD_FIRST=4735, + XED_IFORMFL_VPDPBUSD_LAST=4744, + XED_IFORMFL_VPDPBUSDS_FIRST=4745, + XED_IFORMFL_VPDPBUSDS_LAST=4754, + XED_IFORMFL_VPDPWSSD_FIRST=4755, + XED_IFORMFL_VPDPWSSD_LAST=4764, + XED_IFORMFL_VPDPWSSDS_FIRST=4765, + XED_IFORMFL_VPDPWSSDS_LAST=4774, + XED_IFORMFL_VPERM2F128_FIRST=4775, + XED_IFORMFL_VPERM2F128_LAST=4776, + XED_IFORMFL_VPERM2I128_FIRST=4777, + XED_IFORMFL_VPERM2I128_LAST=4778, + XED_IFORMFL_VPERMB_FIRST=4779, + XED_IFORMFL_VPERMB_LAST=4784, + XED_IFORMFL_VPERMD_FIRST=4785, + XED_IFORMFL_VPERMD_LAST=4790, + XED_IFORMFL_VPERMI2B_FIRST=4791, + XED_IFORMFL_VPERMI2B_LAST=4796, + XED_IFORMFL_VPERMI2D_FIRST=4797, + XED_IFORMFL_VPERMI2D_LAST=4802, + XED_IFORMFL_VPERMI2PD_FIRST=4803, + XED_IFORMFL_VPERMI2PD_LAST=4808, + XED_IFORMFL_VPERMI2PS_FIRST=4809, + XED_IFORMFL_VPERMI2PS_LAST=4814, + XED_IFORMFL_VPERMI2Q_FIRST=4815, + XED_IFORMFL_VPERMI2Q_LAST=4820, + XED_IFORMFL_VPERMI2W_FIRST=4821, + XED_IFORMFL_VPERMI2W_LAST=4826, + XED_IFORMFL_VPERMIL2PD_FIRST=4827, + XED_IFORMFL_VPERMIL2PD_LAST=4832, + XED_IFORMFL_VPERMIL2PS_FIRST=4833, + XED_IFORMFL_VPERMIL2PS_LAST=4838, + XED_IFORMFL_VPERMILPD_FIRST=4839, + XED_IFORMFL_VPERMILPD_LAST=4858, + XED_IFORMFL_VPERMILPS_FIRST=4859, + XED_IFORMFL_VPERMILPS_LAST=4878, + XED_IFORMFL_VPERMPD_FIRST=4879, + XED_IFORMFL_VPERMPD_LAST=4888, + XED_IFORMFL_VPERMPS_FIRST=4889, + XED_IFORMFL_VPERMPS_LAST=4894, + XED_IFORMFL_VPERMQ_FIRST=4895, + XED_IFORMFL_VPERMQ_LAST=4904, + XED_IFORMFL_VPERMT2B_FIRST=4905, + XED_IFORMFL_VPERMT2B_LAST=4910, + XED_IFORMFL_VPERMT2D_FIRST=4911, + XED_IFORMFL_VPERMT2D_LAST=4916, + XED_IFORMFL_VPERMT2PD_FIRST=4917, + XED_IFORMFL_VPERMT2PD_LAST=4922, + XED_IFORMFL_VPERMT2PS_FIRST=4923, + XED_IFORMFL_VPERMT2PS_LAST=4928, + XED_IFORMFL_VPERMT2Q_FIRST=4929, + XED_IFORMFL_VPERMT2Q_LAST=4934, + XED_IFORMFL_VPERMT2W_FIRST=4935, + XED_IFORMFL_VPERMT2W_LAST=4940, + XED_IFORMFL_VPERMW_FIRST=4941, + XED_IFORMFL_VPERMW_LAST=4946, + XED_IFORMFL_VPEXPANDB_FIRST=4947, + XED_IFORMFL_VPEXPANDB_LAST=4952, + XED_IFORMFL_VPEXPANDD_FIRST=4953, + XED_IFORMFL_VPEXPANDD_LAST=4958, + XED_IFORMFL_VPEXPANDQ_FIRST=4959, + XED_IFORMFL_VPEXPANDQ_LAST=4964, + XED_IFORMFL_VPEXPANDW_FIRST=4965, + XED_IFORMFL_VPEXPANDW_LAST=4970, + XED_IFORMFL_VPEXTRB_FIRST=4971, + XED_IFORMFL_VPEXTRB_LAST=4974, + XED_IFORMFL_VPEXTRD_FIRST=4975, + XED_IFORMFL_VPEXTRD_LAST=4978, + XED_IFORMFL_VPEXTRQ_FIRST=4979, + XED_IFORMFL_VPEXTRQ_LAST=4982, + XED_IFORMFL_VPEXTRW_FIRST=4983, + XED_IFORMFL_VPEXTRW_LAST=4987, + XED_IFORMFL_VPEXTRW_C5_FIRST=4988, + XED_IFORMFL_VPEXTRW_C5_LAST=4988, + XED_IFORMFL_VPGATHERDD_FIRST=4989, + XED_IFORMFL_VPGATHERDD_LAST=4993, + XED_IFORMFL_VPGATHERDQ_FIRST=4994, + XED_IFORMFL_VPGATHERDQ_LAST=4998, + XED_IFORMFL_VPGATHERQD_FIRST=4999, + XED_IFORMFL_VPGATHERQD_LAST=5003, + XED_IFORMFL_VPGATHERQQ_FIRST=5004, + XED_IFORMFL_VPGATHERQQ_LAST=5008, + XED_IFORMFL_VPHADDBD_FIRST=5009, + XED_IFORMFL_VPHADDBD_LAST=5010, + XED_IFORMFL_VPHADDBQ_FIRST=5011, + XED_IFORMFL_VPHADDBQ_LAST=5012, + XED_IFORMFL_VPHADDBW_FIRST=5013, + XED_IFORMFL_VPHADDBW_LAST=5014, + XED_IFORMFL_VPHADDD_FIRST=5015, + XED_IFORMFL_VPHADDD_LAST=5018, + XED_IFORMFL_VPHADDDQ_FIRST=5019, + XED_IFORMFL_VPHADDDQ_LAST=5020, + XED_IFORMFL_VPHADDSW_FIRST=5021, + XED_IFORMFL_VPHADDSW_LAST=5024, + XED_IFORMFL_VPHADDUBD_FIRST=5025, + XED_IFORMFL_VPHADDUBD_LAST=5026, + XED_IFORMFL_VPHADDUBQ_FIRST=5027, + XED_IFORMFL_VPHADDUBQ_LAST=5028, + XED_IFORMFL_VPHADDUBW_FIRST=5029, + XED_IFORMFL_VPHADDUBW_LAST=5030, + XED_IFORMFL_VPHADDUDQ_FIRST=5031, + XED_IFORMFL_VPHADDUDQ_LAST=5032, + XED_IFORMFL_VPHADDUWD_FIRST=5033, + XED_IFORMFL_VPHADDUWD_LAST=5034, + XED_IFORMFL_VPHADDUWQ_FIRST=5035, + XED_IFORMFL_VPHADDUWQ_LAST=5036, + XED_IFORMFL_VPHADDW_FIRST=5037, + XED_IFORMFL_VPHADDW_LAST=5040, + XED_IFORMFL_VPHADDWD_FIRST=5041, + XED_IFORMFL_VPHADDWD_LAST=5042, + XED_IFORMFL_VPHADDWQ_FIRST=5043, + XED_IFORMFL_VPHADDWQ_LAST=5044, + XED_IFORMFL_VPHMINPOSUW_FIRST=5045, + XED_IFORMFL_VPHMINPOSUW_LAST=5046, + XED_IFORMFL_VPHSUBBW_FIRST=5047, + XED_IFORMFL_VPHSUBBW_LAST=5048, + XED_IFORMFL_VPHSUBD_FIRST=5049, + XED_IFORMFL_VPHSUBD_LAST=5052, + XED_IFORMFL_VPHSUBDQ_FIRST=5053, + XED_IFORMFL_VPHSUBDQ_LAST=5054, + XED_IFORMFL_VPHSUBSW_FIRST=5055, + XED_IFORMFL_VPHSUBSW_LAST=5058, + XED_IFORMFL_VPHSUBW_FIRST=5059, + XED_IFORMFL_VPHSUBW_LAST=5062, + XED_IFORMFL_VPHSUBWD_FIRST=5063, + XED_IFORMFL_VPHSUBWD_LAST=5064, + XED_IFORMFL_VPINSRB_FIRST=5065, + XED_IFORMFL_VPINSRB_LAST=5068, + XED_IFORMFL_VPINSRD_FIRST=5069, + XED_IFORMFL_VPINSRD_LAST=5072, + XED_IFORMFL_VPINSRQ_FIRST=5073, + XED_IFORMFL_VPINSRQ_LAST=5076, + XED_IFORMFL_VPINSRW_FIRST=5077, + XED_IFORMFL_VPINSRW_LAST=5080, + XED_IFORMFL_VPLZCNTD_FIRST=5081, + XED_IFORMFL_VPLZCNTD_LAST=5086, + XED_IFORMFL_VPLZCNTQ_FIRST=5087, + XED_IFORMFL_VPLZCNTQ_LAST=5092, + XED_IFORMFL_VPMACSDD_FIRST=5093, + XED_IFORMFL_VPMACSDD_LAST=5094, + XED_IFORMFL_VPMACSDQH_FIRST=5095, + XED_IFORMFL_VPMACSDQH_LAST=5096, + XED_IFORMFL_VPMACSDQL_FIRST=5097, + XED_IFORMFL_VPMACSDQL_LAST=5098, + XED_IFORMFL_VPMACSSDD_FIRST=5099, + XED_IFORMFL_VPMACSSDD_LAST=5100, + XED_IFORMFL_VPMACSSDQH_FIRST=5101, + XED_IFORMFL_VPMACSSDQH_LAST=5102, + XED_IFORMFL_VPMACSSDQL_FIRST=5103, + XED_IFORMFL_VPMACSSDQL_LAST=5104, + XED_IFORMFL_VPMACSSWD_FIRST=5105, + XED_IFORMFL_VPMACSSWD_LAST=5106, + XED_IFORMFL_VPMACSSWW_FIRST=5107, + XED_IFORMFL_VPMACSSWW_LAST=5108, + XED_IFORMFL_VPMACSWD_FIRST=5109, + XED_IFORMFL_VPMACSWD_LAST=5110, + XED_IFORMFL_VPMACSWW_FIRST=5111, + XED_IFORMFL_VPMACSWW_LAST=5112, + XED_IFORMFL_VPMADCSSWD_FIRST=5113, + XED_IFORMFL_VPMADCSSWD_LAST=5114, + XED_IFORMFL_VPMADCSWD_FIRST=5115, + XED_IFORMFL_VPMADCSWD_LAST=5116, + XED_IFORMFL_VPMADD52HUQ_FIRST=5117, + XED_IFORMFL_VPMADD52HUQ_LAST=5122, + XED_IFORMFL_VPMADD52LUQ_FIRST=5123, + XED_IFORMFL_VPMADD52LUQ_LAST=5128, + XED_IFORMFL_VPMADDUBSW_FIRST=5129, + XED_IFORMFL_VPMADDUBSW_LAST=5138, + XED_IFORMFL_VPMADDWD_FIRST=5139, + XED_IFORMFL_VPMADDWD_LAST=5148, + XED_IFORMFL_VPMASKMOVD_FIRST=5149, + XED_IFORMFL_VPMASKMOVD_LAST=5152, + XED_IFORMFL_VPMASKMOVQ_FIRST=5153, + XED_IFORMFL_VPMASKMOVQ_LAST=5156, + XED_IFORMFL_VPMAXSB_FIRST=5157, + XED_IFORMFL_VPMAXSB_LAST=5166, + XED_IFORMFL_VPMAXSD_FIRST=5167, + XED_IFORMFL_VPMAXSD_LAST=5176, + XED_IFORMFL_VPMAXSQ_FIRST=5177, + XED_IFORMFL_VPMAXSQ_LAST=5182, + XED_IFORMFL_VPMAXSW_FIRST=5183, + XED_IFORMFL_VPMAXSW_LAST=5192, + XED_IFORMFL_VPMAXUB_FIRST=5193, + XED_IFORMFL_VPMAXUB_LAST=5202, + XED_IFORMFL_VPMAXUD_FIRST=5203, + XED_IFORMFL_VPMAXUD_LAST=5212, + XED_IFORMFL_VPMAXUQ_FIRST=5213, + XED_IFORMFL_VPMAXUQ_LAST=5218, + XED_IFORMFL_VPMAXUW_FIRST=5219, + XED_IFORMFL_VPMAXUW_LAST=5228, + XED_IFORMFL_VPMINSB_FIRST=5229, + XED_IFORMFL_VPMINSB_LAST=5238, + XED_IFORMFL_VPMINSD_FIRST=5239, + XED_IFORMFL_VPMINSD_LAST=5248, + XED_IFORMFL_VPMINSQ_FIRST=5249, + XED_IFORMFL_VPMINSQ_LAST=5254, + XED_IFORMFL_VPMINSW_FIRST=5255, + XED_IFORMFL_VPMINSW_LAST=5264, + XED_IFORMFL_VPMINUB_FIRST=5265, + XED_IFORMFL_VPMINUB_LAST=5274, + XED_IFORMFL_VPMINUD_FIRST=5275, + XED_IFORMFL_VPMINUD_LAST=5284, + XED_IFORMFL_VPMINUQ_FIRST=5285, + XED_IFORMFL_VPMINUQ_LAST=5290, + XED_IFORMFL_VPMINUW_FIRST=5291, + XED_IFORMFL_VPMINUW_LAST=5300, + XED_IFORMFL_VPMOVB2M_FIRST=5301, + XED_IFORMFL_VPMOVB2M_LAST=5303, + XED_IFORMFL_VPMOVD2M_FIRST=5304, + XED_IFORMFL_VPMOVD2M_LAST=5306, + XED_IFORMFL_VPMOVDB_FIRST=5307, + XED_IFORMFL_VPMOVDB_LAST=5312, + XED_IFORMFL_VPMOVDW_FIRST=5313, + XED_IFORMFL_VPMOVDW_LAST=5318, + XED_IFORMFL_VPMOVM2B_FIRST=5319, + XED_IFORMFL_VPMOVM2B_LAST=5321, + XED_IFORMFL_VPMOVM2D_FIRST=5322, + XED_IFORMFL_VPMOVM2D_LAST=5324, + XED_IFORMFL_VPMOVM2Q_FIRST=5325, + XED_IFORMFL_VPMOVM2Q_LAST=5327, + XED_IFORMFL_VPMOVM2W_FIRST=5328, + XED_IFORMFL_VPMOVM2W_LAST=5330, + XED_IFORMFL_VPMOVMSKB_FIRST=5331, + XED_IFORMFL_VPMOVMSKB_LAST=5332, + XED_IFORMFL_VPMOVQ2M_FIRST=5333, + XED_IFORMFL_VPMOVQ2M_LAST=5335, + XED_IFORMFL_VPMOVQB_FIRST=5336, + XED_IFORMFL_VPMOVQB_LAST=5341, + XED_IFORMFL_VPMOVQD_FIRST=5342, + XED_IFORMFL_VPMOVQD_LAST=5347, + XED_IFORMFL_VPMOVQW_FIRST=5348, + XED_IFORMFL_VPMOVQW_LAST=5353, + XED_IFORMFL_VPMOVSDB_FIRST=5354, + XED_IFORMFL_VPMOVSDB_LAST=5359, + XED_IFORMFL_VPMOVSDW_FIRST=5360, + XED_IFORMFL_VPMOVSDW_LAST=5365, + XED_IFORMFL_VPMOVSQB_FIRST=5366, + XED_IFORMFL_VPMOVSQB_LAST=5371, + XED_IFORMFL_VPMOVSQD_FIRST=5372, + XED_IFORMFL_VPMOVSQD_LAST=5377, + XED_IFORMFL_VPMOVSQW_FIRST=5378, + XED_IFORMFL_VPMOVSQW_LAST=5383, + XED_IFORMFL_VPMOVSWB_FIRST=5384, + XED_IFORMFL_VPMOVSWB_LAST=5389, + XED_IFORMFL_VPMOVSXBD_FIRST=5390, + XED_IFORMFL_VPMOVSXBD_LAST=5399, + XED_IFORMFL_VPMOVSXBQ_FIRST=5400, + XED_IFORMFL_VPMOVSXBQ_LAST=5409, + XED_IFORMFL_VPMOVSXBW_FIRST=5410, + XED_IFORMFL_VPMOVSXBW_LAST=5419, + XED_IFORMFL_VPMOVSXDQ_FIRST=5420, + XED_IFORMFL_VPMOVSXDQ_LAST=5429, + XED_IFORMFL_VPMOVSXWD_FIRST=5430, + XED_IFORMFL_VPMOVSXWD_LAST=5439, + XED_IFORMFL_VPMOVSXWQ_FIRST=5440, + XED_IFORMFL_VPMOVSXWQ_LAST=5449, + XED_IFORMFL_VPMOVUSDB_FIRST=5450, + XED_IFORMFL_VPMOVUSDB_LAST=5455, + XED_IFORMFL_VPMOVUSDW_FIRST=5456, + XED_IFORMFL_VPMOVUSDW_LAST=5461, + XED_IFORMFL_VPMOVUSQB_FIRST=5462, + XED_IFORMFL_VPMOVUSQB_LAST=5467, + XED_IFORMFL_VPMOVUSQD_FIRST=5468, + XED_IFORMFL_VPMOVUSQD_LAST=5473, + XED_IFORMFL_VPMOVUSQW_FIRST=5474, + XED_IFORMFL_VPMOVUSQW_LAST=5479, + XED_IFORMFL_VPMOVUSWB_FIRST=5480, + XED_IFORMFL_VPMOVUSWB_LAST=5485, + XED_IFORMFL_VPMOVW2M_FIRST=5486, + XED_IFORMFL_VPMOVW2M_LAST=5488, + XED_IFORMFL_VPMOVWB_FIRST=5489, + XED_IFORMFL_VPMOVWB_LAST=5494, + XED_IFORMFL_VPMOVZXBD_FIRST=5495, + XED_IFORMFL_VPMOVZXBD_LAST=5504, + XED_IFORMFL_VPMOVZXBQ_FIRST=5505, + XED_IFORMFL_VPMOVZXBQ_LAST=5514, + XED_IFORMFL_VPMOVZXBW_FIRST=5515, + XED_IFORMFL_VPMOVZXBW_LAST=5524, + XED_IFORMFL_VPMOVZXDQ_FIRST=5525, + XED_IFORMFL_VPMOVZXDQ_LAST=5534, + XED_IFORMFL_VPMOVZXWD_FIRST=5535, + XED_IFORMFL_VPMOVZXWD_LAST=5544, + XED_IFORMFL_VPMOVZXWQ_FIRST=5545, + XED_IFORMFL_VPMOVZXWQ_LAST=5554, + XED_IFORMFL_VPMULDQ_FIRST=5555, + XED_IFORMFL_VPMULDQ_LAST=5564, + XED_IFORMFL_VPMULHRSW_FIRST=5565, + XED_IFORMFL_VPMULHRSW_LAST=5574, + XED_IFORMFL_VPMULHUW_FIRST=5575, + XED_IFORMFL_VPMULHUW_LAST=5584, + XED_IFORMFL_VPMULHW_FIRST=5585, + XED_IFORMFL_VPMULHW_LAST=5594, + XED_IFORMFL_VPMULLD_FIRST=5595, + XED_IFORMFL_VPMULLD_LAST=5604, + XED_IFORMFL_VPMULLQ_FIRST=5605, + XED_IFORMFL_VPMULLQ_LAST=5610, + XED_IFORMFL_VPMULLW_FIRST=5611, + XED_IFORMFL_VPMULLW_LAST=5620, + XED_IFORMFL_VPMULTISHIFTQB_FIRST=5621, + XED_IFORMFL_VPMULTISHIFTQB_LAST=5626, + XED_IFORMFL_VPMULUDQ_FIRST=5627, + XED_IFORMFL_VPMULUDQ_LAST=5636, + XED_IFORMFL_VPOPCNTB_FIRST=5637, + XED_IFORMFL_VPOPCNTB_LAST=5642, + XED_IFORMFL_VPOPCNTD_FIRST=5643, + XED_IFORMFL_VPOPCNTD_LAST=5648, + XED_IFORMFL_VPOPCNTQ_FIRST=5649, + XED_IFORMFL_VPOPCNTQ_LAST=5654, + XED_IFORMFL_VPOPCNTW_FIRST=5655, + XED_IFORMFL_VPOPCNTW_LAST=5660, + XED_IFORMFL_VPOR_FIRST=5661, + XED_IFORMFL_VPOR_LAST=5664, + XED_IFORMFL_VPORD_FIRST=5665, + XED_IFORMFL_VPORD_LAST=5670, + XED_IFORMFL_VPORQ_FIRST=5671, + XED_IFORMFL_VPORQ_LAST=5676, + XED_IFORMFL_VPPERM_FIRST=5677, + XED_IFORMFL_VPPERM_LAST=5679, + XED_IFORMFL_VPROLD_FIRST=5680, + XED_IFORMFL_VPROLD_LAST=5685, + XED_IFORMFL_VPROLQ_FIRST=5686, + XED_IFORMFL_VPROLQ_LAST=5691, + XED_IFORMFL_VPROLVD_FIRST=5692, + XED_IFORMFL_VPROLVD_LAST=5697, + XED_IFORMFL_VPROLVQ_FIRST=5698, + XED_IFORMFL_VPROLVQ_LAST=5703, + XED_IFORMFL_VPRORD_FIRST=5704, + XED_IFORMFL_VPRORD_LAST=5709, + XED_IFORMFL_VPRORQ_FIRST=5710, + XED_IFORMFL_VPRORQ_LAST=5715, + XED_IFORMFL_VPRORVD_FIRST=5716, + XED_IFORMFL_VPRORVD_LAST=5721, + XED_IFORMFL_VPRORVQ_FIRST=5722, + XED_IFORMFL_VPRORVQ_LAST=5727, + XED_IFORMFL_VPROTB_FIRST=5728, + XED_IFORMFL_VPROTB_LAST=5732, + XED_IFORMFL_VPROTD_FIRST=5733, + XED_IFORMFL_VPROTD_LAST=5737, + XED_IFORMFL_VPROTQ_FIRST=5738, + XED_IFORMFL_VPROTQ_LAST=5742, + XED_IFORMFL_VPROTW_FIRST=5743, + XED_IFORMFL_VPROTW_LAST=5747, + XED_IFORMFL_VPSADBW_FIRST=5748, + XED_IFORMFL_VPSADBW_LAST=5757, + XED_IFORMFL_VPSCATTERDD_FIRST=5758, + XED_IFORMFL_VPSCATTERDD_LAST=5760, + XED_IFORMFL_VPSCATTERDQ_FIRST=5761, + XED_IFORMFL_VPSCATTERDQ_LAST=5763, + XED_IFORMFL_VPSCATTERQD_FIRST=5764, + XED_IFORMFL_VPSCATTERQD_LAST=5766, + XED_IFORMFL_VPSCATTERQQ_FIRST=5767, + XED_IFORMFL_VPSCATTERQQ_LAST=5769, + XED_IFORMFL_VPSHAB_FIRST=5770, + XED_IFORMFL_VPSHAB_LAST=5772, + XED_IFORMFL_VPSHAD_FIRST=5773, + XED_IFORMFL_VPSHAD_LAST=5775, + XED_IFORMFL_VPSHAQ_FIRST=5776, + XED_IFORMFL_VPSHAQ_LAST=5778, + XED_IFORMFL_VPSHAW_FIRST=5779, + XED_IFORMFL_VPSHAW_LAST=5781, + XED_IFORMFL_VPSHLB_FIRST=5782, + XED_IFORMFL_VPSHLB_LAST=5784, + XED_IFORMFL_VPSHLD_FIRST=5785, + XED_IFORMFL_VPSHLD_LAST=5787, + XED_IFORMFL_VPSHLDD_FIRST=5788, + XED_IFORMFL_VPSHLDD_LAST=5793, + XED_IFORMFL_VPSHLDQ_FIRST=5794, + XED_IFORMFL_VPSHLDQ_LAST=5799, + XED_IFORMFL_VPSHLDVD_FIRST=5800, + XED_IFORMFL_VPSHLDVD_LAST=5805, + XED_IFORMFL_VPSHLDVQ_FIRST=5806, + XED_IFORMFL_VPSHLDVQ_LAST=5811, + XED_IFORMFL_VPSHLDVW_FIRST=5812, + XED_IFORMFL_VPSHLDVW_LAST=5817, + XED_IFORMFL_VPSHLDW_FIRST=5818, + XED_IFORMFL_VPSHLDW_LAST=5823, + XED_IFORMFL_VPSHLQ_FIRST=5824, + XED_IFORMFL_VPSHLQ_LAST=5826, + XED_IFORMFL_VPSHLW_FIRST=5827, + XED_IFORMFL_VPSHLW_LAST=5829, + XED_IFORMFL_VPSHRDD_FIRST=5830, + XED_IFORMFL_VPSHRDD_LAST=5835, + XED_IFORMFL_VPSHRDQ_FIRST=5836, + XED_IFORMFL_VPSHRDQ_LAST=5841, + XED_IFORMFL_VPSHRDVD_FIRST=5842, + XED_IFORMFL_VPSHRDVD_LAST=5847, + XED_IFORMFL_VPSHRDVQ_FIRST=5848, + XED_IFORMFL_VPSHRDVQ_LAST=5853, + XED_IFORMFL_VPSHRDVW_FIRST=5854, + XED_IFORMFL_VPSHRDVW_LAST=5859, + XED_IFORMFL_VPSHRDW_FIRST=5860, + XED_IFORMFL_VPSHRDW_LAST=5865, + XED_IFORMFL_VPSHUFB_FIRST=5866, + XED_IFORMFL_VPSHUFB_LAST=5875, + XED_IFORMFL_VPSHUFBITQMB_FIRST=5876, + XED_IFORMFL_VPSHUFBITQMB_LAST=5881, + XED_IFORMFL_VPSHUFD_FIRST=5882, + XED_IFORMFL_VPSHUFD_LAST=5891, + XED_IFORMFL_VPSHUFHW_FIRST=5892, + XED_IFORMFL_VPSHUFHW_LAST=5901, + XED_IFORMFL_VPSHUFLW_FIRST=5902, + XED_IFORMFL_VPSHUFLW_LAST=5911, + XED_IFORMFL_VPSIGNB_FIRST=5912, + XED_IFORMFL_VPSIGNB_LAST=5915, + XED_IFORMFL_VPSIGND_FIRST=5916, + XED_IFORMFL_VPSIGND_LAST=5919, + XED_IFORMFL_VPSIGNW_FIRST=5920, + XED_IFORMFL_VPSIGNW_LAST=5923, + XED_IFORMFL_VPSLLD_FIRST=5924, + XED_IFORMFL_VPSLLD_LAST=5941, + XED_IFORMFL_VPSLLDQ_FIRST=5942, + XED_IFORMFL_VPSLLDQ_LAST=5949, + XED_IFORMFL_VPSLLQ_FIRST=5950, + XED_IFORMFL_VPSLLQ_LAST=5967, + XED_IFORMFL_VPSLLVD_FIRST=5968, + XED_IFORMFL_VPSLLVD_LAST=5977, + XED_IFORMFL_VPSLLVQ_FIRST=5978, + XED_IFORMFL_VPSLLVQ_LAST=5987, + XED_IFORMFL_VPSLLVW_FIRST=5988, + XED_IFORMFL_VPSLLVW_LAST=5993, + XED_IFORMFL_VPSLLW_FIRST=5994, + XED_IFORMFL_VPSLLW_LAST=6011, + XED_IFORMFL_VPSRAD_FIRST=6012, + XED_IFORMFL_VPSRAD_LAST=6029, + XED_IFORMFL_VPSRAQ_FIRST=6030, + XED_IFORMFL_VPSRAQ_LAST=6041, + XED_IFORMFL_VPSRAVD_FIRST=6042, + XED_IFORMFL_VPSRAVD_LAST=6051, + XED_IFORMFL_VPSRAVQ_FIRST=6052, + XED_IFORMFL_VPSRAVQ_LAST=6057, + XED_IFORMFL_VPSRAVW_FIRST=6058, + XED_IFORMFL_VPSRAVW_LAST=6063, + XED_IFORMFL_VPSRAW_FIRST=6064, + XED_IFORMFL_VPSRAW_LAST=6081, + XED_IFORMFL_VPSRLD_FIRST=6082, + XED_IFORMFL_VPSRLD_LAST=6099, + XED_IFORMFL_VPSRLDQ_FIRST=6100, + XED_IFORMFL_VPSRLDQ_LAST=6107, + XED_IFORMFL_VPSRLQ_FIRST=6108, + XED_IFORMFL_VPSRLQ_LAST=6125, + XED_IFORMFL_VPSRLVD_FIRST=6126, + XED_IFORMFL_VPSRLVD_LAST=6135, + XED_IFORMFL_VPSRLVQ_FIRST=6136, + XED_IFORMFL_VPSRLVQ_LAST=6145, + XED_IFORMFL_VPSRLVW_FIRST=6146, + XED_IFORMFL_VPSRLVW_LAST=6151, + XED_IFORMFL_VPSRLW_FIRST=6152, + XED_IFORMFL_VPSRLW_LAST=6169, + XED_IFORMFL_VPSUBB_FIRST=6170, + XED_IFORMFL_VPSUBB_LAST=6179, + XED_IFORMFL_VPSUBD_FIRST=6180, + XED_IFORMFL_VPSUBD_LAST=6189, + XED_IFORMFL_VPSUBQ_FIRST=6190, + XED_IFORMFL_VPSUBQ_LAST=6199, + XED_IFORMFL_VPSUBSB_FIRST=6200, + XED_IFORMFL_VPSUBSB_LAST=6209, + XED_IFORMFL_VPSUBSW_FIRST=6210, + XED_IFORMFL_VPSUBSW_LAST=6219, + XED_IFORMFL_VPSUBUSB_FIRST=6220, + XED_IFORMFL_VPSUBUSB_LAST=6229, + XED_IFORMFL_VPSUBUSW_FIRST=6230, + XED_IFORMFL_VPSUBUSW_LAST=6239, + XED_IFORMFL_VPSUBW_FIRST=6240, + XED_IFORMFL_VPSUBW_LAST=6249, + XED_IFORMFL_VPTERNLOGD_FIRST=6250, + XED_IFORMFL_VPTERNLOGD_LAST=6255, + XED_IFORMFL_VPTERNLOGQ_FIRST=6256, + XED_IFORMFL_VPTERNLOGQ_LAST=6261, + XED_IFORMFL_VPTEST_FIRST=6262, + XED_IFORMFL_VPTEST_LAST=6265, + XED_IFORMFL_VPTESTMB_FIRST=6266, + XED_IFORMFL_VPTESTMB_LAST=6271, + XED_IFORMFL_VPTESTMD_FIRST=6272, + XED_IFORMFL_VPTESTMD_LAST=6277, + XED_IFORMFL_VPTESTMQ_FIRST=6278, + XED_IFORMFL_VPTESTMQ_LAST=6283, + XED_IFORMFL_VPTESTMW_FIRST=6284, + XED_IFORMFL_VPTESTMW_LAST=6289, + XED_IFORMFL_VPTESTNMB_FIRST=6290, + XED_IFORMFL_VPTESTNMB_LAST=6295, + XED_IFORMFL_VPTESTNMD_FIRST=6296, + XED_IFORMFL_VPTESTNMD_LAST=6301, + XED_IFORMFL_VPTESTNMQ_FIRST=6302, + XED_IFORMFL_VPTESTNMQ_LAST=6307, + XED_IFORMFL_VPTESTNMW_FIRST=6308, + XED_IFORMFL_VPTESTNMW_LAST=6313, + XED_IFORMFL_VPUNPCKHBW_FIRST=6314, + XED_IFORMFL_VPUNPCKHBW_LAST=6323, + XED_IFORMFL_VPUNPCKHDQ_FIRST=6324, + XED_IFORMFL_VPUNPCKHDQ_LAST=6333, + XED_IFORMFL_VPUNPCKHQDQ_FIRST=6334, + XED_IFORMFL_VPUNPCKHQDQ_LAST=6343, + XED_IFORMFL_VPUNPCKHWD_FIRST=6344, + XED_IFORMFL_VPUNPCKHWD_LAST=6353, + XED_IFORMFL_VPUNPCKLBW_FIRST=6354, + XED_IFORMFL_VPUNPCKLBW_LAST=6363, + XED_IFORMFL_VPUNPCKLDQ_FIRST=6364, + XED_IFORMFL_VPUNPCKLDQ_LAST=6373, + XED_IFORMFL_VPUNPCKLQDQ_FIRST=6374, + XED_IFORMFL_VPUNPCKLQDQ_LAST=6383, + XED_IFORMFL_VPUNPCKLWD_FIRST=6384, + XED_IFORMFL_VPUNPCKLWD_LAST=6393, + XED_IFORMFL_VPXOR_FIRST=6394, + XED_IFORMFL_VPXOR_LAST=6397, + XED_IFORMFL_VPXORD_FIRST=6398, + XED_IFORMFL_VPXORD_LAST=6403, + XED_IFORMFL_VPXORQ_FIRST=6404, + XED_IFORMFL_VPXORQ_LAST=6409, + XED_IFORMFL_VRANGEPD_FIRST=6410, + XED_IFORMFL_VRANGEPD_LAST=6415, + XED_IFORMFL_VRANGEPS_FIRST=6416, + XED_IFORMFL_VRANGEPS_LAST=6421, + XED_IFORMFL_VRANGESD_FIRST=6422, + XED_IFORMFL_VRANGESD_LAST=6423, + XED_IFORMFL_VRANGESS_FIRST=6424, + XED_IFORMFL_VRANGESS_LAST=6425, + XED_IFORMFL_VRCP14PD_FIRST=6426, + XED_IFORMFL_VRCP14PD_LAST=6431, + XED_IFORMFL_VRCP14PS_FIRST=6432, + XED_IFORMFL_VRCP14PS_LAST=6437, + XED_IFORMFL_VRCP14SD_FIRST=6438, + XED_IFORMFL_VRCP14SD_LAST=6439, + XED_IFORMFL_VRCP14SS_FIRST=6440, + XED_IFORMFL_VRCP14SS_LAST=6441, + XED_IFORMFL_VRCP28PD_FIRST=6442, + XED_IFORMFL_VRCP28PD_LAST=6443, + XED_IFORMFL_VRCP28PS_FIRST=6444, + XED_IFORMFL_VRCP28PS_LAST=6445, + XED_IFORMFL_VRCP28SD_FIRST=6446, + XED_IFORMFL_VRCP28SD_LAST=6447, + XED_IFORMFL_VRCP28SS_FIRST=6448, + XED_IFORMFL_VRCP28SS_LAST=6449, + XED_IFORMFL_VRCPPH_FIRST=6450, + XED_IFORMFL_VRCPPH_LAST=6455, + XED_IFORMFL_VRCPPS_FIRST=6456, + XED_IFORMFL_VRCPPS_LAST=6459, + XED_IFORMFL_VRCPSH_FIRST=6460, + XED_IFORMFL_VRCPSH_LAST=6461, + XED_IFORMFL_VRCPSS_FIRST=6462, + XED_IFORMFL_VRCPSS_LAST=6463, + XED_IFORMFL_VREDUCEPD_FIRST=6464, + XED_IFORMFL_VREDUCEPD_LAST=6469, + XED_IFORMFL_VREDUCEPH_FIRST=6470, + XED_IFORMFL_VREDUCEPH_LAST=6475, + XED_IFORMFL_VREDUCEPS_FIRST=6476, + XED_IFORMFL_VREDUCEPS_LAST=6481, + XED_IFORMFL_VREDUCESD_FIRST=6482, + XED_IFORMFL_VREDUCESD_LAST=6483, + XED_IFORMFL_VREDUCESH_FIRST=6484, + XED_IFORMFL_VREDUCESH_LAST=6485, + XED_IFORMFL_VREDUCESS_FIRST=6486, + XED_IFORMFL_VREDUCESS_LAST=6487, + XED_IFORMFL_VRNDSCALEPD_FIRST=6488, + XED_IFORMFL_VRNDSCALEPD_LAST=6493, + XED_IFORMFL_VRNDSCALEPH_FIRST=6494, + XED_IFORMFL_VRNDSCALEPH_LAST=6499, + XED_IFORMFL_VRNDSCALEPS_FIRST=6500, + XED_IFORMFL_VRNDSCALEPS_LAST=6505, + XED_IFORMFL_VRNDSCALESD_FIRST=6506, + XED_IFORMFL_VRNDSCALESD_LAST=6507, + XED_IFORMFL_VRNDSCALESH_FIRST=6508, + XED_IFORMFL_VRNDSCALESH_LAST=6509, + XED_IFORMFL_VRNDSCALESS_FIRST=6510, + XED_IFORMFL_VRNDSCALESS_LAST=6511, + XED_IFORMFL_VROUNDPD_FIRST=6512, + XED_IFORMFL_VROUNDPD_LAST=6515, + XED_IFORMFL_VROUNDPS_FIRST=6516, + XED_IFORMFL_VROUNDPS_LAST=6519, + XED_IFORMFL_VROUNDSD_FIRST=6520, + XED_IFORMFL_VROUNDSD_LAST=6521, + XED_IFORMFL_VROUNDSS_FIRST=6522, + XED_IFORMFL_VROUNDSS_LAST=6523, + XED_IFORMFL_VRSQRT14PD_FIRST=6524, + XED_IFORMFL_VRSQRT14PD_LAST=6529, + XED_IFORMFL_VRSQRT14PS_FIRST=6530, + XED_IFORMFL_VRSQRT14PS_LAST=6535, + XED_IFORMFL_VRSQRT14SD_FIRST=6536, + XED_IFORMFL_VRSQRT14SD_LAST=6537, + XED_IFORMFL_VRSQRT14SS_FIRST=6538, + XED_IFORMFL_VRSQRT14SS_LAST=6539, + XED_IFORMFL_VRSQRT28PD_FIRST=6540, + XED_IFORMFL_VRSQRT28PD_LAST=6541, + XED_IFORMFL_VRSQRT28PS_FIRST=6542, + XED_IFORMFL_VRSQRT28PS_LAST=6543, + XED_IFORMFL_VRSQRT28SD_FIRST=6544, + XED_IFORMFL_VRSQRT28SD_LAST=6545, + XED_IFORMFL_VRSQRT28SS_FIRST=6546, + XED_IFORMFL_VRSQRT28SS_LAST=6547, + XED_IFORMFL_VRSQRTPH_FIRST=6548, + XED_IFORMFL_VRSQRTPH_LAST=6553, + XED_IFORMFL_VRSQRTPS_FIRST=6554, + XED_IFORMFL_VRSQRTPS_LAST=6557, + XED_IFORMFL_VRSQRTSH_FIRST=6558, + XED_IFORMFL_VRSQRTSH_LAST=6559, + XED_IFORMFL_VRSQRTSS_FIRST=6560, + XED_IFORMFL_VRSQRTSS_LAST=6561, + XED_IFORMFL_VSCALEFPD_FIRST=6562, + XED_IFORMFL_VSCALEFPD_LAST=6567, + XED_IFORMFL_VSCALEFPH_FIRST=6568, + XED_IFORMFL_VSCALEFPH_LAST=6573, + XED_IFORMFL_VSCALEFPS_FIRST=6574, + XED_IFORMFL_VSCALEFPS_LAST=6579, + XED_IFORMFL_VSCALEFSD_FIRST=6580, + XED_IFORMFL_VSCALEFSD_LAST=6581, + XED_IFORMFL_VSCALEFSH_FIRST=6582, + XED_IFORMFL_VSCALEFSH_LAST=6583, + XED_IFORMFL_VSCALEFSS_FIRST=6584, + XED_IFORMFL_VSCALEFSS_LAST=6585, + XED_IFORMFL_VSCATTERDPD_FIRST=6586, + XED_IFORMFL_VSCATTERDPD_LAST=6588, + XED_IFORMFL_VSCATTERDPS_FIRST=6589, + XED_IFORMFL_VSCATTERDPS_LAST=6591, + XED_IFORMFL_VSCATTERPF0DPD_FIRST=6592, + XED_IFORMFL_VSCATTERPF0DPD_LAST=6592, + XED_IFORMFL_VSCATTERPF0DPS_FIRST=6593, + XED_IFORMFL_VSCATTERPF0DPS_LAST=6593, + XED_IFORMFL_VSCATTERPF0QPD_FIRST=6594, + XED_IFORMFL_VSCATTERPF0QPD_LAST=6594, + XED_IFORMFL_VSCATTERPF0QPS_FIRST=6595, + XED_IFORMFL_VSCATTERPF0QPS_LAST=6595, + XED_IFORMFL_VSCATTERPF1DPD_FIRST=6596, + XED_IFORMFL_VSCATTERPF1DPD_LAST=6596, + XED_IFORMFL_VSCATTERPF1DPS_FIRST=6597, + XED_IFORMFL_VSCATTERPF1DPS_LAST=6597, + XED_IFORMFL_VSCATTERPF1QPD_FIRST=6598, + XED_IFORMFL_VSCATTERPF1QPD_LAST=6598, + XED_IFORMFL_VSCATTERPF1QPS_FIRST=6599, + XED_IFORMFL_VSCATTERPF1QPS_LAST=6599, + XED_IFORMFL_VSCATTERQPD_FIRST=6600, + XED_IFORMFL_VSCATTERQPD_LAST=6602, + XED_IFORMFL_VSCATTERQPS_FIRST=6603, + XED_IFORMFL_VSCATTERQPS_LAST=6605, + XED_IFORMFL_VSHUFF32X4_FIRST=6606, + XED_IFORMFL_VSHUFF32X4_LAST=6609, + XED_IFORMFL_VSHUFF64X2_FIRST=6610, + XED_IFORMFL_VSHUFF64X2_LAST=6613, + XED_IFORMFL_VSHUFI32X4_FIRST=6614, + XED_IFORMFL_VSHUFI32X4_LAST=6617, + XED_IFORMFL_VSHUFI64X2_FIRST=6618, + XED_IFORMFL_VSHUFI64X2_LAST=6621, + XED_IFORMFL_VSHUFPD_FIRST=6622, + XED_IFORMFL_VSHUFPD_LAST=6631, + XED_IFORMFL_VSHUFPS_FIRST=6632, + XED_IFORMFL_VSHUFPS_LAST=6641, + XED_IFORMFL_VSQRTPD_FIRST=6642, + XED_IFORMFL_VSQRTPD_LAST=6651, + XED_IFORMFL_VSQRTPH_FIRST=6652, + XED_IFORMFL_VSQRTPH_LAST=6657, + XED_IFORMFL_VSQRTPS_FIRST=6658, + XED_IFORMFL_VSQRTPS_LAST=6667, + XED_IFORMFL_VSQRTSD_FIRST=6668, + XED_IFORMFL_VSQRTSD_LAST=6671, + XED_IFORMFL_VSQRTSH_FIRST=6672, + XED_IFORMFL_VSQRTSH_LAST=6673, + XED_IFORMFL_VSQRTSS_FIRST=6674, + XED_IFORMFL_VSQRTSS_LAST=6677, + XED_IFORMFL_VSTMXCSR_FIRST=6678, + XED_IFORMFL_VSTMXCSR_LAST=6678, + XED_IFORMFL_VSUBPD_FIRST=6679, + XED_IFORMFL_VSUBPD_LAST=6688, + XED_IFORMFL_VSUBPH_FIRST=6689, + XED_IFORMFL_VSUBPH_LAST=6694, + XED_IFORMFL_VSUBPS_FIRST=6695, + XED_IFORMFL_VSUBPS_LAST=6704, + XED_IFORMFL_VSUBSD_FIRST=6705, + XED_IFORMFL_VSUBSD_LAST=6708, + XED_IFORMFL_VSUBSH_FIRST=6709, + XED_IFORMFL_VSUBSH_LAST=6710, + XED_IFORMFL_VSUBSS_FIRST=6711, + XED_IFORMFL_VSUBSS_LAST=6714, + XED_IFORMFL_VTESTPD_FIRST=6715, + XED_IFORMFL_VTESTPD_LAST=6718, + XED_IFORMFL_VTESTPS_FIRST=6719, + XED_IFORMFL_VTESTPS_LAST=6722, + XED_IFORMFL_VUCOMISD_FIRST=6723, + XED_IFORMFL_VUCOMISD_LAST=6726, + XED_IFORMFL_VUCOMISH_FIRST=6727, + XED_IFORMFL_VUCOMISH_LAST=6728, + XED_IFORMFL_VUCOMISS_FIRST=6729, + XED_IFORMFL_VUCOMISS_LAST=6732, + XED_IFORMFL_VUNPCKHPD_FIRST=6733, + XED_IFORMFL_VUNPCKHPD_LAST=6742, + XED_IFORMFL_VUNPCKHPS_FIRST=6743, + XED_IFORMFL_VUNPCKHPS_LAST=6752, + XED_IFORMFL_VUNPCKLPD_FIRST=6753, + XED_IFORMFL_VUNPCKLPD_LAST=6762, + XED_IFORMFL_VUNPCKLPS_FIRST=6763, + XED_IFORMFL_VUNPCKLPS_LAST=6772, + XED_IFORMFL_VXORPD_FIRST=6773, + XED_IFORMFL_VXORPD_LAST=6782, + XED_IFORMFL_VXORPS_FIRST=6783, + XED_IFORMFL_VXORPS_LAST=6792, + XED_IFORMFL_VZEROALL_FIRST=6793, + XED_IFORMFL_VZEROALL_LAST=6793, + XED_IFORMFL_VZEROUPPER_FIRST=6794, + XED_IFORMFL_VZEROUPPER_LAST=6794, + XED_IFORMFL_WBINVD_FIRST=6795, + XED_IFORMFL_WBINVD_LAST=6795, + XED_IFORMFL_WBNOINVD_FIRST=6796, + XED_IFORMFL_WBNOINVD_LAST=6796, + XED_IFORMFL_WRFSBASE_FIRST=6797, + XED_IFORMFL_WRFSBASE_LAST=6797, + XED_IFORMFL_WRGSBASE_FIRST=6798, + XED_IFORMFL_WRGSBASE_LAST=6798, + XED_IFORMFL_WRMSR_FIRST=6799, + XED_IFORMFL_WRMSR_LAST=6799, + XED_IFORMFL_WRPKRU_FIRST=6800, + XED_IFORMFL_WRPKRU_LAST=6800, + XED_IFORMFL_WRSSD_FIRST=6801, + XED_IFORMFL_WRSSD_LAST=6801, + XED_IFORMFL_WRSSQ_FIRST=6802, + XED_IFORMFL_WRSSQ_LAST=6802, + XED_IFORMFL_WRUSSD_FIRST=6803, + XED_IFORMFL_WRUSSD_LAST=6803, + XED_IFORMFL_WRUSSQ_FIRST=6804, + XED_IFORMFL_WRUSSQ_LAST=6804, + XED_IFORMFL_XABORT_FIRST=6805, + XED_IFORMFL_XABORT_LAST=6805, + XED_IFORMFL_XADD_FIRST=6806, + XED_IFORMFL_XADD_LAST=6809, + XED_IFORMFL_XADD_LOCK_FIRST=6810, + XED_IFORMFL_XADD_LOCK_LAST=6811, + XED_IFORMFL_XBEGIN_FIRST=6812, + XED_IFORMFL_XBEGIN_LAST=6812, + XED_IFORMFL_XCHG_FIRST=6813, + XED_IFORMFL_XCHG_LAST=6817, + XED_IFORMFL_XEND_FIRST=6818, + XED_IFORMFL_XEND_LAST=6818, + XED_IFORMFL_XGETBV_FIRST=6819, + XED_IFORMFL_XGETBV_LAST=6819, + XED_IFORMFL_XLAT_FIRST=6820, + XED_IFORMFL_XLAT_LAST=6820, + XED_IFORMFL_XOR_FIRST=6821, + XED_IFORMFL_XOR_LAST=6838, + XED_IFORMFL_XORPD_FIRST=6839, + XED_IFORMFL_XORPD_LAST=6840, + XED_IFORMFL_XORPS_FIRST=6841, + XED_IFORMFL_XORPS_LAST=6842, + XED_IFORMFL_XOR_LOCK_FIRST=6843, + XED_IFORMFL_XOR_LOCK_LAST=6848, + XED_IFORMFL_XRESLDTRK_FIRST=6849, + XED_IFORMFL_XRESLDTRK_LAST=6849, + XED_IFORMFL_XRSTOR_FIRST=6850, + XED_IFORMFL_XRSTOR_LAST=6850, + XED_IFORMFL_XRSTOR64_FIRST=6851, + XED_IFORMFL_XRSTOR64_LAST=6851, + XED_IFORMFL_XRSTORS_FIRST=6852, + XED_IFORMFL_XRSTORS_LAST=6852, + XED_IFORMFL_XRSTORS64_FIRST=6853, + XED_IFORMFL_XRSTORS64_LAST=6853, + XED_IFORMFL_XSAVE_FIRST=6854, + XED_IFORMFL_XSAVE_LAST=6854, + XED_IFORMFL_XSAVE64_FIRST=6855, + XED_IFORMFL_XSAVE64_LAST=6855, + XED_IFORMFL_XSAVEC_FIRST=6856, + XED_IFORMFL_XSAVEC_LAST=6856, + XED_IFORMFL_XSAVEC64_FIRST=6857, + XED_IFORMFL_XSAVEC64_LAST=6857, + XED_IFORMFL_XSAVEOPT_FIRST=6858, + XED_IFORMFL_XSAVEOPT_LAST=6858, + XED_IFORMFL_XSAVEOPT64_FIRST=6859, + XED_IFORMFL_XSAVEOPT64_LAST=6859, + XED_IFORMFL_XSAVES_FIRST=6860, + XED_IFORMFL_XSAVES_LAST=6860, + XED_IFORMFL_XSAVES64_FIRST=6861, + XED_IFORMFL_XSAVES64_LAST=6861, + XED_IFORMFL_XSETBV_FIRST=6862, + XED_IFORMFL_XSETBV_LAST=6862, + XED_IFORMFL_XSTORE_FIRST=6863, + XED_IFORMFL_XSTORE_LAST=6863, + XED_IFORMFL_XSUSLDTRK_FIRST=6864, + XED_IFORMFL_XSUSLDTRK_LAST=6864, + XED_IFORMFL_XTEST_FIRST=6865, + XED_IFORMFL_XTEST_LAST=6865, + XED_IFORMFL_LAST +} xed_iformfl_enum_t; + +/// Returns the last element of the enumeration +/// @return xed_iformfl_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_iformfl_enum_t xed_iformfl_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-iformfl-enum.txt b/CodeVirtualizer/build/obj/xed-iformfl-enum.txt new file mode 100644 index 0000000..b1ab550 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-iformfl-enum.txt @@ -0,0 +1,3501 @@ +# @file xed-iformfl-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-iformfl-enum.c +hfn xed-iformfl-enum.h +typename xed_iformfl_enum_t +prefix XED_IFORMFL_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +extra_header xed-iclass-enum.h +AAA_FIRST 1 +AAA_LAST 1 +AAD_FIRST 2 +AAD_LAST 2 +AAM_FIRST 3 +AAM_LAST 3 +AAS_FIRST 4 +AAS_LAST 4 +ADC_FIRST 5 +ADC_LAST 22 +ADCX_FIRST 23 +ADCX_LAST 26 +ADC_LOCK_FIRST 27 +ADC_LOCK_LAST 32 +ADD_FIRST 33 +ADD_LAST 50 +ADDPD_FIRST 51 +ADDPD_LAST 52 +ADDPS_FIRST 53 +ADDPS_LAST 54 +ADDSD_FIRST 55 +ADDSD_LAST 56 +ADDSS_FIRST 57 +ADDSS_LAST 58 +ADDSUBPD_FIRST 59 +ADDSUBPD_LAST 60 +ADDSUBPS_FIRST 61 +ADDSUBPS_LAST 62 +ADD_LOCK_FIRST 63 +ADD_LOCK_LAST 68 +ADOX_FIRST 69 +ADOX_LAST 72 +AESDEC_FIRST 73 +AESDEC_LAST 74 +AESDEC128KL_FIRST 75 +AESDEC128KL_LAST 75 +AESDEC256KL_FIRST 76 +AESDEC256KL_LAST 76 +AESDECLAST_FIRST 77 +AESDECLAST_LAST 78 +AESDECWIDE128KL_FIRST 79 +AESDECWIDE128KL_LAST 79 +AESDECWIDE256KL_FIRST 80 +AESDECWIDE256KL_LAST 80 +AESENC_FIRST 81 +AESENC_LAST 82 +AESENC128KL_FIRST 83 +AESENC128KL_LAST 83 +AESENC256KL_FIRST 84 +AESENC256KL_LAST 84 +AESENCLAST_FIRST 85 +AESENCLAST_LAST 86 +AESENCWIDE128KL_FIRST 87 +AESENCWIDE128KL_LAST 87 +AESENCWIDE256KL_FIRST 88 +AESENCWIDE256KL_LAST 88 +AESIMC_FIRST 89 +AESIMC_LAST 90 +AESKEYGENASSIST_FIRST 91 +AESKEYGENASSIST_LAST 92 +AND_FIRST 93 +AND_LAST 110 +ANDN_FIRST 111 +ANDN_LAST 114 +ANDNPD_FIRST 115 +ANDNPD_LAST 116 +ANDNPS_FIRST 117 +ANDNPS_LAST 118 +ANDPD_FIRST 119 +ANDPD_LAST 120 +ANDPS_FIRST 121 +ANDPS_LAST 122 +AND_LOCK_FIRST 123 +AND_LOCK_LAST 128 +ARPL_FIRST 129 +ARPL_LAST 130 +BEXTR_FIRST 131 +BEXTR_LAST 134 +BEXTR_XOP_FIRST 135 +BEXTR_XOP_LAST 138 +BLCFILL_FIRST 139 +BLCFILL_LAST 142 +BLCI_FIRST 143 +BLCI_LAST 146 +BLCIC_FIRST 147 +BLCIC_LAST 150 +BLCMSK_FIRST 151 +BLCMSK_LAST 154 +BLCS_FIRST 155 +BLCS_LAST 158 +BLENDPD_FIRST 159 +BLENDPD_LAST 160 +BLENDPS_FIRST 161 +BLENDPS_LAST 162 +BLENDVPD_FIRST 163 +BLENDVPD_LAST 164 +BLENDVPS_FIRST 165 +BLENDVPS_LAST 166 +BLSFILL_FIRST 167 +BLSFILL_LAST 170 +BLSI_FIRST 171 +BLSI_LAST 174 +BLSIC_FIRST 175 +BLSIC_LAST 178 +BLSMSK_FIRST 179 +BLSMSK_LAST 182 +BLSR_FIRST 183 +BLSR_LAST 186 +BNDCL_FIRST 187 +BNDCL_LAST 189 +BNDCN_FIRST 190 +BNDCN_LAST 192 +BNDCU_FIRST 193 +BNDCU_LAST 195 +BNDLDX_FIRST 196 +BNDLDX_LAST 197 +BNDMK_FIRST 198 +BNDMK_LAST 198 +BNDMOV_FIRST 199 +BNDMOV_LAST 203 +BNDSTX_FIRST 204 +BNDSTX_LAST 205 +BOUND_FIRST 206 +BOUND_LAST 207 +BSF_FIRST 208 +BSF_LAST 209 +BSR_FIRST 210 +BSR_LAST 211 +BSWAP_FIRST 212 +BSWAP_LAST 212 +BT_FIRST 213 +BT_LAST 216 +BTC_FIRST 217 +BTC_LAST 220 +BTC_LOCK_FIRST 221 +BTC_LOCK_LAST 222 +BTR_FIRST 223 +BTR_LAST 226 +BTR_LOCK_FIRST 227 +BTR_LOCK_LAST 228 +BTS_FIRST 229 +BTS_LAST 232 +BTS_LOCK_FIRST 233 +BTS_LOCK_LAST 234 +BZHI_FIRST 235 +BZHI_LAST 238 +CALL_FAR_FIRST 239 +CALL_FAR_LAST 240 +CALL_NEAR_FIRST 241 +CALL_NEAR_LAST 244 +CBW_FIRST 245 +CBW_LAST 245 +CDQ_FIRST 246 +CDQ_LAST 246 +CDQE_FIRST 247 +CDQE_LAST 247 +CLAC_FIRST 248 +CLAC_LAST 248 +CLC_FIRST 249 +CLC_LAST 249 +CLD_FIRST 250 +CLD_LAST 250 +CLDEMOTE_FIRST 251 +CLDEMOTE_LAST 251 +CLFLUSH_FIRST 252 +CLFLUSH_LAST 252 +CLFLUSHOPT_FIRST 253 +CLFLUSHOPT_LAST 253 +CLGI_FIRST 254 +CLGI_LAST 254 +CLI_FIRST 255 +CLI_LAST 255 +CLRSSBSY_FIRST 256 +CLRSSBSY_LAST 256 +CLTS_FIRST 257 +CLTS_LAST 257 +CLUI_FIRST 258 +CLUI_LAST 258 +CLWB_FIRST 259 +CLWB_LAST 259 +CLZERO_FIRST 260 +CLZERO_LAST 260 +CMC_FIRST 261 +CMC_LAST 261 +CMOVB_FIRST 262 +CMOVB_LAST 263 +CMOVBE_FIRST 264 +CMOVBE_LAST 265 +CMOVL_FIRST 266 +CMOVL_LAST 267 +CMOVLE_FIRST 268 +CMOVLE_LAST 269 +CMOVNB_FIRST 270 +CMOVNB_LAST 271 +CMOVNBE_FIRST 272 +CMOVNBE_LAST 273 +CMOVNL_FIRST 274 +CMOVNL_LAST 275 +CMOVNLE_FIRST 276 +CMOVNLE_LAST 277 +CMOVNO_FIRST 278 +CMOVNO_LAST 279 +CMOVNP_FIRST 280 +CMOVNP_LAST 281 +CMOVNS_FIRST 282 +CMOVNS_LAST 283 +CMOVNZ_FIRST 284 +CMOVNZ_LAST 285 +CMOVO_FIRST 286 +CMOVO_LAST 287 +CMOVP_FIRST 288 +CMOVP_LAST 289 +CMOVS_FIRST 290 +CMOVS_LAST 291 +CMOVZ_FIRST 292 +CMOVZ_LAST 293 +CMP_FIRST 294 +CMP_LAST 311 +CMPPD_FIRST 312 +CMPPD_LAST 313 +CMPPS_FIRST 314 +CMPPS_LAST 315 +CMPSB_FIRST 316 +CMPSB_LAST 316 +CMPSD_FIRST 317 +CMPSD_LAST 317 +CMPSD_XMM_FIRST 318 +CMPSD_XMM_LAST 319 +CMPSQ_FIRST 320 +CMPSQ_LAST 320 +CMPSS_FIRST 321 +CMPSS_LAST 322 +CMPSW_FIRST 323 +CMPSW_LAST 323 +CMPXCHG_FIRST 324 +CMPXCHG_LAST 327 +CMPXCHG16B_FIRST 328 +CMPXCHG16B_LAST 328 +CMPXCHG16B_LOCK_FIRST 329 +CMPXCHG16B_LOCK_LAST 329 +CMPXCHG8B_FIRST 330 +CMPXCHG8B_LAST 330 +CMPXCHG8B_LOCK_FIRST 331 +CMPXCHG8B_LOCK_LAST 331 +CMPXCHG_LOCK_FIRST 332 +CMPXCHG_LOCK_LAST 333 +COMISD_FIRST 334 +COMISD_LAST 335 +COMISS_FIRST 336 +COMISS_LAST 337 +CPUID_FIRST 338 +CPUID_LAST 338 +CQO_FIRST 339 +CQO_LAST 339 +CRC32_FIRST 340 +CRC32_LAST 343 +CVTDQ2PD_FIRST 344 +CVTDQ2PD_LAST 345 +CVTDQ2PS_FIRST 346 +CVTDQ2PS_LAST 347 +CVTPD2DQ_FIRST 348 +CVTPD2DQ_LAST 349 +CVTPD2PI_FIRST 350 +CVTPD2PI_LAST 351 +CVTPD2PS_FIRST 352 +CVTPD2PS_LAST 353 +CVTPI2PD_FIRST 354 +CVTPI2PD_LAST 355 +CVTPI2PS_FIRST 356 +CVTPI2PS_LAST 357 +CVTPS2DQ_FIRST 358 +CVTPS2DQ_LAST 359 +CVTPS2PD_FIRST 360 +CVTPS2PD_LAST 361 +CVTPS2PI_FIRST 362 +CVTPS2PI_LAST 363 +CVTSD2SI_FIRST 364 +CVTSD2SI_LAST 367 +CVTSD2SS_FIRST 368 +CVTSD2SS_LAST 369 +CVTSI2SD_FIRST 370 +CVTSI2SD_LAST 373 +CVTSI2SS_FIRST 374 +CVTSI2SS_LAST 377 +CVTSS2SD_FIRST 378 +CVTSS2SD_LAST 379 +CVTSS2SI_FIRST 380 +CVTSS2SI_LAST 383 +CVTTPD2DQ_FIRST 384 +CVTTPD2DQ_LAST 385 +CVTTPD2PI_FIRST 386 +CVTTPD2PI_LAST 387 +CVTTPS2DQ_FIRST 388 +CVTTPS2DQ_LAST 389 +CVTTPS2PI_FIRST 390 +CVTTPS2PI_LAST 391 +CVTTSD2SI_FIRST 392 +CVTTSD2SI_LAST 395 +CVTTSS2SI_FIRST 396 +CVTTSS2SI_LAST 399 +CWD_FIRST 400 +CWD_LAST 400 +CWDE_FIRST 401 +CWDE_LAST 401 +DAA_FIRST 402 +DAA_LAST 402 +DAS_FIRST 403 +DAS_LAST 403 +DEC_FIRST 404 +DEC_LAST 408 +DEC_LOCK_FIRST 409 +DEC_LOCK_LAST 410 +DIV_FIRST 411 +DIV_LAST 414 +DIVPD_FIRST 415 +DIVPD_LAST 416 +DIVPS_FIRST 417 +DIVPS_LAST 418 +DIVSD_FIRST 419 +DIVSD_LAST 420 +DIVSS_FIRST 421 +DIVSS_LAST 422 +DPPD_FIRST 423 +DPPD_LAST 424 +DPPS_FIRST 425 +DPPS_LAST 426 +EMMS_FIRST 427 +EMMS_LAST 427 +ENCLS_FIRST 428 +ENCLS_LAST 428 +ENCLU_FIRST 429 +ENCLU_LAST 429 +ENCLV_FIRST 430 +ENCLV_LAST 430 +ENCODEKEY128_FIRST 431 +ENCODEKEY128_LAST 431 +ENCODEKEY256_FIRST 432 +ENCODEKEY256_LAST 432 +ENDBR32_FIRST 433 +ENDBR32_LAST 433 +ENDBR64_FIRST 434 +ENDBR64_LAST 434 +ENQCMD_FIRST 435 +ENQCMD_LAST 435 +ENQCMDS_FIRST 436 +ENQCMDS_LAST 436 +ENTER_FIRST 437 +ENTER_LAST 437 +EXTRACTPS_FIRST 438 +EXTRACTPS_LAST 439 +EXTRQ_FIRST 440 +EXTRQ_LAST 441 +F2XM1_FIRST 442 +F2XM1_LAST 442 +FABS_FIRST 443 +FABS_LAST 443 +FADD_FIRST 444 +FADD_LAST 447 +FADDP_FIRST 448 +FADDP_LAST 448 +FBLD_FIRST 449 +FBLD_LAST 449 +FBSTP_FIRST 450 +FBSTP_LAST 450 +FCHS_FIRST 451 +FCHS_LAST 451 +FCMOVB_FIRST 452 +FCMOVB_LAST 452 +FCMOVBE_FIRST 453 +FCMOVBE_LAST 453 +FCMOVE_FIRST 454 +FCMOVE_LAST 454 +FCMOVNB_FIRST 455 +FCMOVNB_LAST 455 +FCMOVNBE_FIRST 456 +FCMOVNBE_LAST 456 +FCMOVNE_FIRST 457 +FCMOVNE_LAST 457 +FCMOVNU_FIRST 458 +FCMOVNU_LAST 458 +FCMOVU_FIRST 459 +FCMOVU_LAST 459 +FCOM_FIRST 460 +FCOM_LAST 463 +FCOMI_FIRST 464 +FCOMI_LAST 464 +FCOMIP_FIRST 465 +FCOMIP_LAST 465 +FCOMP_FIRST 466 +FCOMP_LAST 470 +FCOMPP_FIRST 471 +FCOMPP_LAST 471 +FCOS_FIRST 472 +FCOS_LAST 472 +FDECSTP_FIRST 473 +FDECSTP_LAST 473 +FDISI8087_NOP_FIRST 474 +FDISI8087_NOP_LAST 474 +FDIV_FIRST 475 +FDIV_LAST 478 +FDIVP_FIRST 479 +FDIVP_LAST 479 +FDIVR_FIRST 480 +FDIVR_LAST 483 +FDIVRP_FIRST 484 +FDIVRP_LAST 484 +FEMMS_FIRST 485 +FEMMS_LAST 485 +FENI8087_NOP_FIRST 486 +FENI8087_NOP_LAST 486 +FFREE_FIRST 487 +FFREE_LAST 487 +FFREEP_FIRST 488 +FFREEP_LAST 488 +FIADD_FIRST 489 +FIADD_LAST 490 +FICOM_FIRST 491 +FICOM_LAST 492 +FICOMP_FIRST 493 +FICOMP_LAST 494 +FIDIV_FIRST 495 +FIDIV_LAST 496 +FIDIVR_FIRST 497 +FIDIVR_LAST 498 +FILD_FIRST 499 +FILD_LAST 501 +FIMUL_FIRST 502 +FIMUL_LAST 503 +FINCSTP_FIRST 504 +FINCSTP_LAST 504 +FIST_FIRST 505 +FIST_LAST 506 +FISTP_FIRST 507 +FISTP_LAST 509 +FISTTP_FIRST 510 +FISTTP_LAST 512 +FISUB_FIRST 513 +FISUB_LAST 514 +FISUBR_FIRST 515 +FISUBR_LAST 516 +FLD_FIRST 517 +FLD_LAST 520 +FLD1_FIRST 521 +FLD1_LAST 521 +FLDCW_FIRST 522 +FLDCW_LAST 522 +FLDENV_FIRST 523 +FLDENV_LAST 524 +FLDL2E_FIRST 525 +FLDL2E_LAST 525 +FLDL2T_FIRST 526 +FLDL2T_LAST 526 +FLDLG2_FIRST 527 +FLDLG2_LAST 527 +FLDLN2_FIRST 528 +FLDLN2_LAST 528 +FLDPI_FIRST 529 +FLDPI_LAST 529 +FLDZ_FIRST 530 +FLDZ_LAST 530 +FMUL_FIRST 531 +FMUL_LAST 534 +FMULP_FIRST 535 +FMULP_LAST 535 +FNCLEX_FIRST 536 +FNCLEX_LAST 536 +FNINIT_FIRST 537 +FNINIT_LAST 537 +FNOP_FIRST 538 +FNOP_LAST 538 +FNSAVE_FIRST 539 +FNSAVE_LAST 540 +FNSTCW_FIRST 541 +FNSTCW_LAST 541 +FNSTENV_FIRST 542 +FNSTENV_LAST 543 +FNSTSW_FIRST 544 +FNSTSW_LAST 545 +FPATAN_FIRST 546 +FPATAN_LAST 546 +FPREM_FIRST 547 +FPREM_LAST 547 +FPREM1_FIRST 548 +FPREM1_LAST 548 +FPTAN_FIRST 549 +FPTAN_LAST 549 +FRNDINT_FIRST 550 +FRNDINT_LAST 550 +FRSTOR_FIRST 551 +FRSTOR_LAST 552 +FSCALE_FIRST 553 +FSCALE_LAST 553 +FSETPM287_NOP_FIRST 554 +FSETPM287_NOP_LAST 554 +FSIN_FIRST 555 +FSIN_LAST 555 +FSINCOS_FIRST 556 +FSINCOS_LAST 556 +FSQRT_FIRST 557 +FSQRT_LAST 557 +FST_FIRST 558 +FST_LAST 560 +FSTP_FIRST 561 +FSTP_LAST 566 +FSTPNCE_FIRST 567 +FSTPNCE_LAST 567 +FSUB_FIRST 568 +FSUB_LAST 571 +FSUBP_FIRST 572 +FSUBP_LAST 572 +FSUBR_FIRST 573 +FSUBR_LAST 576 +FSUBRP_FIRST 577 +FSUBRP_LAST 577 +FTST_FIRST 578 +FTST_LAST 578 +FUCOM_FIRST 579 +FUCOM_LAST 579 +FUCOMI_FIRST 580 +FUCOMI_LAST 580 +FUCOMIP_FIRST 581 +FUCOMIP_LAST 581 +FUCOMP_FIRST 582 +FUCOMP_LAST 582 +FUCOMPP_FIRST 583 +FUCOMPP_LAST 583 +FWAIT_FIRST 584 +FWAIT_LAST 584 +FXAM_FIRST 585 +FXAM_LAST 585 +FXCH_FIRST 586 +FXCH_LAST 588 +FXRSTOR_FIRST 589 +FXRSTOR_LAST 589 +FXRSTOR64_FIRST 590 +FXRSTOR64_LAST 590 +FXSAVE_FIRST 591 +FXSAVE_LAST 591 +FXSAVE64_FIRST 592 +FXSAVE64_LAST 592 +FXTRACT_FIRST 593 +FXTRACT_LAST 593 +FYL2X_FIRST 594 +FYL2X_LAST 594 +FYL2XP1_FIRST 595 +FYL2XP1_LAST 595 +GETSEC_FIRST 596 +GETSEC_LAST 596 +GF2P8AFFINEINVQB_FIRST 597 +GF2P8AFFINEINVQB_LAST 598 +GF2P8AFFINEQB_FIRST 599 +GF2P8AFFINEQB_LAST 600 +GF2P8MULB_FIRST 601 +GF2P8MULB_LAST 602 +HADDPD_FIRST 603 +HADDPD_LAST 604 +HADDPS_FIRST 605 +HADDPS_LAST 606 +HLT_FIRST 607 +HLT_LAST 607 +HRESET_FIRST 608 +HRESET_LAST 608 +HSUBPD_FIRST 609 +HSUBPD_LAST 610 +HSUBPS_FIRST 611 +HSUBPS_LAST 612 +IDIV_FIRST 613 +IDIV_LAST 616 +IMUL_FIRST 617 +IMUL_LAST 626 +IN_FIRST 627 +IN_LAST 630 +INC_FIRST 631 +INC_LAST 635 +INCSSPD_FIRST 636 +INCSSPD_LAST 636 +INCSSPQ_FIRST 637 +INCSSPQ_LAST 637 +INC_LOCK_FIRST 638 +INC_LOCK_LAST 639 +INSB_FIRST 640 +INSB_LAST 640 +INSD_FIRST 641 +INSD_LAST 641 +INSERTPS_FIRST 642 +INSERTPS_LAST 643 +INSERTQ_FIRST 644 +INSERTQ_LAST 645 +INSW_FIRST 646 +INSW_LAST 646 +INT_FIRST 647 +INT_LAST 647 +INT1_FIRST 648 +INT1_LAST 648 +INT3_FIRST 649 +INT3_LAST 649 +INTO_FIRST 650 +INTO_LAST 650 +INVD_FIRST 651 +INVD_LAST 651 +INVEPT_FIRST 652 +INVEPT_LAST 653 +INVLPG_FIRST 654 +INVLPG_LAST 654 +INVLPGA_FIRST 655 +INVLPGA_LAST 655 +INVLPGB_FIRST 656 +INVLPGB_LAST 657 +INVPCID_FIRST 658 +INVPCID_LAST 659 +INVVPID_FIRST 660 +INVVPID_LAST 661 +IRET_FIRST 662 +IRET_LAST 662 +IRETD_FIRST 663 +IRETD_LAST 663 +IRETQ_FIRST 664 +IRETQ_LAST 664 +JB_FIRST 665 +JB_LAST 667 +JBE_FIRST 668 +JBE_LAST 670 +JCXZ_FIRST 671 +JCXZ_LAST 671 +JECXZ_FIRST 672 +JECXZ_LAST 672 +JL_FIRST 673 +JL_LAST 675 +JLE_FIRST 676 +JLE_LAST 678 +JMP_FIRST 679 +JMP_LAST 683 +JMP_FAR_FIRST 684 +JMP_FAR_LAST 685 +JNB_FIRST 686 +JNB_LAST 688 +JNBE_FIRST 689 +JNBE_LAST 691 +JNL_FIRST 692 +JNL_LAST 694 +JNLE_FIRST 695 +JNLE_LAST 697 +JNO_FIRST 698 +JNO_LAST 700 +JNP_FIRST 701 +JNP_LAST 703 +JNS_FIRST 704 +JNS_LAST 706 +JNZ_FIRST 707 +JNZ_LAST 709 +JO_FIRST 710 +JO_LAST 712 +JP_FIRST 713 +JP_LAST 715 +JRCXZ_FIRST 716 +JRCXZ_LAST 716 +JS_FIRST 717 +JS_LAST 719 +JZ_FIRST 720 +JZ_LAST 722 +KADDB_FIRST 723 +KADDB_LAST 723 +KADDD_FIRST 724 +KADDD_LAST 724 +KADDQ_FIRST 725 +KADDQ_LAST 725 +KADDW_FIRST 726 +KADDW_LAST 726 +KANDB_FIRST 727 +KANDB_LAST 727 +KANDD_FIRST 728 +KANDD_LAST 728 +KANDNB_FIRST 729 +KANDNB_LAST 729 +KANDND_FIRST 730 +KANDND_LAST 730 +KANDNQ_FIRST 731 +KANDNQ_LAST 731 +KANDNW_FIRST 732 +KANDNW_LAST 732 +KANDQ_FIRST 733 +KANDQ_LAST 733 +KANDW_FIRST 734 +KANDW_LAST 734 +KMOVB_FIRST 735 +KMOVB_LAST 739 +KMOVD_FIRST 740 +KMOVD_LAST 744 +KMOVQ_FIRST 745 +KMOVQ_LAST 749 +KMOVW_FIRST 750 +KMOVW_LAST 754 +KNOTB_FIRST 755 +KNOTB_LAST 755 +KNOTD_FIRST 756 +KNOTD_LAST 756 +KNOTQ_FIRST 757 +KNOTQ_LAST 757 +KNOTW_FIRST 758 +KNOTW_LAST 758 +KORB_FIRST 759 +KORB_LAST 759 +KORD_FIRST 760 +KORD_LAST 760 +KORQ_FIRST 761 +KORQ_LAST 761 +KORTESTB_FIRST 762 +KORTESTB_LAST 762 +KORTESTD_FIRST 763 +KORTESTD_LAST 763 +KORTESTQ_FIRST 764 +KORTESTQ_LAST 764 +KORTESTW_FIRST 765 +KORTESTW_LAST 765 +KORW_FIRST 766 +KORW_LAST 766 +KSHIFTLB_FIRST 767 +KSHIFTLB_LAST 767 +KSHIFTLD_FIRST 768 +KSHIFTLD_LAST 768 +KSHIFTLQ_FIRST 769 +KSHIFTLQ_LAST 769 +KSHIFTLW_FIRST 770 +KSHIFTLW_LAST 770 +KSHIFTRB_FIRST 771 +KSHIFTRB_LAST 771 +KSHIFTRD_FIRST 772 +KSHIFTRD_LAST 772 +KSHIFTRQ_FIRST 773 +KSHIFTRQ_LAST 773 +KSHIFTRW_FIRST 774 +KSHIFTRW_LAST 774 +KTESTB_FIRST 775 +KTESTB_LAST 775 +KTESTD_FIRST 776 +KTESTD_LAST 776 +KTESTQ_FIRST 777 +KTESTQ_LAST 777 +KTESTW_FIRST 778 +KTESTW_LAST 778 +KUNPCKBW_FIRST 779 +KUNPCKBW_LAST 779 +KUNPCKDQ_FIRST 780 +KUNPCKDQ_LAST 780 +KUNPCKWD_FIRST 781 +KUNPCKWD_LAST 781 +KXNORB_FIRST 782 +KXNORB_LAST 782 +KXNORD_FIRST 783 +KXNORD_LAST 783 +KXNORQ_FIRST 784 +KXNORQ_LAST 784 +KXNORW_FIRST 785 +KXNORW_LAST 785 +KXORB_FIRST 786 +KXORB_LAST 786 +KXORD_FIRST 787 +KXORD_LAST 787 +KXORQ_FIRST 788 +KXORQ_LAST 788 +KXORW_FIRST 789 +KXORW_LAST 789 +LAHF_FIRST 790 +LAHF_LAST 790 +LAR_FIRST 791 +LAR_LAST 792 +LDDQU_FIRST 793 +LDDQU_LAST 793 +LDMXCSR_FIRST 794 +LDMXCSR_LAST 794 +LDS_FIRST 795 +LDS_LAST 795 +LDTILECFG_FIRST 796 +LDTILECFG_LAST 796 +LEA_FIRST 797 +LEA_LAST 797 +LEAVE_FIRST 798 +LEAVE_LAST 798 +LES_FIRST 799 +LES_LAST 799 +LFENCE_FIRST 800 +LFENCE_LAST 800 +LFS_FIRST 801 +LFS_LAST 801 +LGDT_FIRST 802 +LGDT_LAST 803 +LGS_FIRST 804 +LGS_LAST 804 +LIDT_FIRST 805 +LIDT_LAST 806 +LLDT_FIRST 807 +LLDT_LAST 808 +LLWPCB_FIRST 809 +LLWPCB_LAST 809 +LMSW_FIRST 810 +LMSW_LAST 811 +LOADIWKEY_FIRST 812 +LOADIWKEY_LAST 812 +LODSB_FIRST 813 +LODSB_LAST 813 +LODSD_FIRST 814 +LODSD_LAST 814 +LODSQ_FIRST 815 +LODSQ_LAST 815 +LODSW_FIRST 816 +LODSW_LAST 816 +LOOP_FIRST 817 +LOOP_LAST 817 +LOOPE_FIRST 818 +LOOPE_LAST 818 +LOOPNE_FIRST 819 +LOOPNE_LAST 819 +LSL_FIRST 820 +LSL_LAST 821 +LSS_FIRST 822 +LSS_LAST 822 +LTR_FIRST 823 +LTR_LAST 824 +LWPINS_FIRST 825 +LWPINS_LAST 826 +LWPVAL_FIRST 827 +LWPVAL_LAST 828 +LZCNT_FIRST 829 +LZCNT_LAST 830 +MASKMOVDQU_FIRST 831 +MASKMOVDQU_LAST 831 +MASKMOVQ_FIRST 832 +MASKMOVQ_LAST 832 +MAXPD_FIRST 833 +MAXPD_LAST 834 +MAXPS_FIRST 835 +MAXPS_LAST 836 +MAXSD_FIRST 837 +MAXSD_LAST 838 +MAXSS_FIRST 839 +MAXSS_LAST 840 +MCOMMIT_FIRST 841 +MCOMMIT_LAST 841 +MFENCE_FIRST 842 +MFENCE_LAST 842 +MINPD_FIRST 843 +MINPD_LAST 844 +MINPS_FIRST 845 +MINPS_LAST 846 +MINSD_FIRST 847 +MINSD_LAST 848 +MINSS_FIRST 849 +MINSS_LAST 850 +MONITOR_FIRST 851 +MONITOR_LAST 851 +MONITORX_FIRST 852 +MONITORX_LAST 852 +MOV_FIRST 853 +MOV_LAST 874 +MOVAPD_FIRST 875 +MOVAPD_LAST 878 +MOVAPS_FIRST 879 +MOVAPS_LAST 882 +MOVBE_FIRST 883 +MOVBE_LAST 884 +MOVD_FIRST 885 +MOVD_LAST 892 +MOVDDUP_FIRST 893 +MOVDDUP_LAST 894 +MOVDIR64B_FIRST 895 +MOVDIR64B_LAST 895 +MOVDIRI_FIRST 896 +MOVDIRI_LAST 897 +MOVDQ2Q_FIRST 898 +MOVDQ2Q_LAST 898 +MOVDQA_FIRST 899 +MOVDQA_LAST 902 +MOVDQU_FIRST 903 +MOVDQU_LAST 906 +MOVHLPS_FIRST 907 +MOVHLPS_LAST 907 +MOVHPD_FIRST 908 +MOVHPD_LAST 909 +MOVHPS_FIRST 910 +MOVHPS_LAST 911 +MOVLHPS_FIRST 912 +MOVLHPS_LAST 912 +MOVLPD_FIRST 913 +MOVLPD_LAST 914 +MOVLPS_FIRST 915 +MOVLPS_LAST 916 +MOVMSKPD_FIRST 917 +MOVMSKPD_LAST 917 +MOVMSKPS_FIRST 918 +MOVMSKPS_LAST 918 +MOVNTDQ_FIRST 919 +MOVNTDQ_LAST 919 +MOVNTDQA_FIRST 920 +MOVNTDQA_LAST 920 +MOVNTI_FIRST 921 +MOVNTI_LAST 922 +MOVNTPD_FIRST 923 +MOVNTPD_LAST 923 +MOVNTPS_FIRST 924 +MOVNTPS_LAST 924 +MOVNTQ_FIRST 925 +MOVNTQ_LAST 925 +MOVNTSD_FIRST 926 +MOVNTSD_LAST 926 +MOVNTSS_FIRST 927 +MOVNTSS_LAST 927 +MOVQ_FIRST 928 +MOVQ_LAST 943 +MOVQ2DQ_FIRST 944 +MOVQ2DQ_LAST 944 +MOVSB_FIRST 945 +MOVSB_LAST 945 +MOVSD_FIRST 946 +MOVSD_LAST 946 +MOVSD_XMM_FIRST 947 +MOVSD_XMM_LAST 950 +MOVSHDUP_FIRST 951 +MOVSHDUP_LAST 952 +MOVSLDUP_FIRST 953 +MOVSLDUP_LAST 954 +MOVSQ_FIRST 955 +MOVSQ_LAST 955 +MOVSS_FIRST 956 +MOVSS_LAST 959 +MOVSW_FIRST 960 +MOVSW_LAST 960 +MOVSX_FIRST 961 +MOVSX_LAST 964 +MOVSXD_FIRST 965 +MOVSXD_LAST 966 +MOVUPD_FIRST 967 +MOVUPD_LAST 970 +MOVUPS_FIRST 971 +MOVUPS_LAST 974 +MOVZX_FIRST 975 +MOVZX_LAST 978 +MOV_CR_FIRST 979 +MOV_CR_LAST 982 +MOV_DR_FIRST 983 +MOV_DR_LAST 986 +MPSADBW_FIRST 987 +MPSADBW_LAST 988 +MUL_FIRST 989 +MUL_LAST 992 +MULPD_FIRST 993 +MULPD_LAST 994 +MULPS_FIRST 995 +MULPS_LAST 996 +MULSD_FIRST 997 +MULSD_LAST 998 +MULSS_FIRST 999 +MULSS_LAST 1000 +MULX_FIRST 1001 +MULX_LAST 1004 +MWAIT_FIRST 1005 +MWAIT_LAST 1005 +MWAITX_FIRST 1006 +MWAITX_LAST 1006 +NEG_FIRST 1007 +NEG_LAST 1010 +NEG_LOCK_FIRST 1011 +NEG_LOCK_LAST 1012 +NOP_FIRST 1013 +NOP_LAST 1040 +NOT_FIRST 1041 +NOT_LAST 1044 +NOT_LOCK_FIRST 1045 +NOT_LOCK_LAST 1046 +OR_FIRST 1047 +OR_LAST 1064 +ORPD_FIRST 1065 +ORPD_LAST 1066 +ORPS_FIRST 1067 +ORPS_LAST 1068 +OR_LOCK_FIRST 1069 +OR_LOCK_LAST 1074 +OUT_FIRST 1075 +OUT_LAST 1078 +OUTSB_FIRST 1079 +OUTSB_LAST 1079 +OUTSD_FIRST 1080 +OUTSD_LAST 1080 +OUTSW_FIRST 1081 +OUTSW_LAST 1081 +PABSB_FIRST 1082 +PABSB_LAST 1085 +PABSD_FIRST 1086 +PABSD_LAST 1089 +PABSW_FIRST 1090 +PABSW_LAST 1093 +PACKSSDW_FIRST 1094 +PACKSSDW_LAST 1097 +PACKSSWB_FIRST 1098 +PACKSSWB_LAST 1101 +PACKUSDW_FIRST 1102 +PACKUSDW_LAST 1103 +PACKUSWB_FIRST 1104 +PACKUSWB_LAST 1107 +PADDB_FIRST 1108 +PADDB_LAST 1111 +PADDD_FIRST 1112 +PADDD_LAST 1115 +PADDQ_FIRST 1116 +PADDQ_LAST 1119 +PADDSB_FIRST 1120 +PADDSB_LAST 1123 +PADDSW_FIRST 1124 +PADDSW_LAST 1127 +PADDUSB_FIRST 1128 +PADDUSB_LAST 1131 +PADDUSW_FIRST 1132 +PADDUSW_LAST 1135 +PADDW_FIRST 1136 +PADDW_LAST 1139 +PALIGNR_FIRST 1140 +PALIGNR_LAST 1143 +PAND_FIRST 1144 +PAND_LAST 1147 +PANDN_FIRST 1148 +PANDN_LAST 1151 +PAUSE_FIRST 1152 +PAUSE_LAST 1152 +PAVGB_FIRST 1153 +PAVGB_LAST 1156 +PAVGUSB_FIRST 1157 +PAVGUSB_LAST 1158 +PAVGW_FIRST 1159 +PAVGW_LAST 1162 +PBLENDVB_FIRST 1163 +PBLENDVB_LAST 1164 +PBLENDW_FIRST 1165 +PBLENDW_LAST 1166 +PCLMULQDQ_FIRST 1167 +PCLMULQDQ_LAST 1168 +PCMPEQB_FIRST 1169 +PCMPEQB_LAST 1172 +PCMPEQD_FIRST 1173 +PCMPEQD_LAST 1176 +PCMPEQQ_FIRST 1177 +PCMPEQQ_LAST 1178 +PCMPEQW_FIRST 1179 +PCMPEQW_LAST 1182 +PCMPESTRI_FIRST 1183 +PCMPESTRI_LAST 1184 +PCMPESTRI64_FIRST 1185 +PCMPESTRI64_LAST 1186 +PCMPESTRM_FIRST 1187 +PCMPESTRM_LAST 1188 +PCMPESTRM64_FIRST 1189 +PCMPESTRM64_LAST 1190 +PCMPGTB_FIRST 1191 +PCMPGTB_LAST 1194 +PCMPGTD_FIRST 1195 +PCMPGTD_LAST 1198 +PCMPGTQ_FIRST 1199 +PCMPGTQ_LAST 1200 +PCMPGTW_FIRST 1201 +PCMPGTW_LAST 1204 +PCMPISTRI_FIRST 1205 +PCMPISTRI_LAST 1206 +PCMPISTRI64_FIRST 1207 +PCMPISTRI64_LAST 1208 +PCMPISTRM_FIRST 1209 +PCMPISTRM_LAST 1210 +PCONFIG_FIRST 1211 +PCONFIG_LAST 1212 +PDEP_FIRST 1213 +PDEP_LAST 1216 +PEXT_FIRST 1217 +PEXT_LAST 1220 +PEXTRB_FIRST 1221 +PEXTRB_LAST 1222 +PEXTRD_FIRST 1223 +PEXTRD_LAST 1224 +PEXTRQ_FIRST 1225 +PEXTRQ_LAST 1226 +PEXTRW_FIRST 1227 +PEXTRW_LAST 1228 +PEXTRW_SSE4_FIRST 1229 +PEXTRW_SSE4_LAST 1230 +PF2ID_FIRST 1231 +PF2ID_LAST 1232 +PF2IW_FIRST 1233 +PF2IW_LAST 1234 +PFACC_FIRST 1235 +PFACC_LAST 1236 +PFADD_FIRST 1237 +PFADD_LAST 1238 +PFCMPEQ_FIRST 1239 +PFCMPEQ_LAST 1240 +PFCMPGE_FIRST 1241 +PFCMPGE_LAST 1242 +PFCMPGT_FIRST 1243 +PFCMPGT_LAST 1244 +PFMAX_FIRST 1245 +PFMAX_LAST 1246 +PFMIN_FIRST 1247 +PFMIN_LAST 1248 +PFMUL_FIRST 1249 +PFMUL_LAST 1250 +PFNACC_FIRST 1251 +PFNACC_LAST 1252 +PFPNACC_FIRST 1253 +PFPNACC_LAST 1254 +PFRCP_FIRST 1255 +PFRCP_LAST 1256 +PFRCPIT1_FIRST 1257 +PFRCPIT1_LAST 1258 +PFRCPIT2_FIRST 1259 +PFRCPIT2_LAST 1260 +PFRSQIT1_FIRST 1261 +PFRSQIT1_LAST 1262 +PFRSQRT_FIRST 1263 +PFRSQRT_LAST 1264 +PFSUB_FIRST 1265 +PFSUB_LAST 1266 +PFSUBR_FIRST 1267 +PFSUBR_LAST 1268 +PHADDD_FIRST 1269 +PHADDD_LAST 1272 +PHADDSW_FIRST 1273 +PHADDSW_LAST 1276 +PHADDW_FIRST 1277 +PHADDW_LAST 1280 +PHMINPOSUW_FIRST 1281 +PHMINPOSUW_LAST 1282 +PHSUBD_FIRST 1283 +PHSUBD_LAST 1286 +PHSUBSW_FIRST 1287 +PHSUBSW_LAST 1290 +PHSUBW_FIRST 1291 +PHSUBW_LAST 1294 +PI2FD_FIRST 1295 +PI2FD_LAST 1296 +PI2FW_FIRST 1297 +PI2FW_LAST 1298 +PINSRB_FIRST 1299 +PINSRB_LAST 1300 +PINSRD_FIRST 1301 +PINSRD_LAST 1302 +PINSRQ_FIRST 1303 +PINSRQ_LAST 1304 +PINSRW_FIRST 1305 +PINSRW_LAST 1308 +PMADDUBSW_FIRST 1309 +PMADDUBSW_LAST 1312 +PMADDWD_FIRST 1313 +PMADDWD_LAST 1316 +PMAXSB_FIRST 1317 +PMAXSB_LAST 1318 +PMAXSD_FIRST 1319 +PMAXSD_LAST 1320 +PMAXSW_FIRST 1321 +PMAXSW_LAST 1324 +PMAXUB_FIRST 1325 +PMAXUB_LAST 1328 +PMAXUD_FIRST 1329 +PMAXUD_LAST 1330 +PMAXUW_FIRST 1331 +PMAXUW_LAST 1332 +PMINSB_FIRST 1333 +PMINSB_LAST 1334 +PMINSD_FIRST 1335 +PMINSD_LAST 1336 +PMINSW_FIRST 1337 +PMINSW_LAST 1340 +PMINUB_FIRST 1341 +PMINUB_LAST 1344 +PMINUD_FIRST 1345 +PMINUD_LAST 1346 +PMINUW_FIRST 1347 +PMINUW_LAST 1348 +PMOVMSKB_FIRST 1349 +PMOVMSKB_LAST 1350 +PMOVSXBD_FIRST 1351 +PMOVSXBD_LAST 1352 +PMOVSXBQ_FIRST 1353 +PMOVSXBQ_LAST 1354 +PMOVSXBW_FIRST 1355 +PMOVSXBW_LAST 1356 +PMOVSXDQ_FIRST 1357 +PMOVSXDQ_LAST 1358 +PMOVSXWD_FIRST 1359 +PMOVSXWD_LAST 1360 +PMOVSXWQ_FIRST 1361 +PMOVSXWQ_LAST 1362 +PMOVZXBD_FIRST 1363 +PMOVZXBD_LAST 1364 +PMOVZXBQ_FIRST 1365 +PMOVZXBQ_LAST 1366 +PMOVZXBW_FIRST 1367 +PMOVZXBW_LAST 1368 +PMOVZXDQ_FIRST 1369 +PMOVZXDQ_LAST 1370 +PMOVZXWD_FIRST 1371 +PMOVZXWD_LAST 1372 +PMOVZXWQ_FIRST 1373 +PMOVZXWQ_LAST 1374 +PMULDQ_FIRST 1375 +PMULDQ_LAST 1376 +PMULHRSW_FIRST 1377 +PMULHRSW_LAST 1380 +PMULHRW_FIRST 1381 +PMULHRW_LAST 1382 +PMULHUW_FIRST 1383 +PMULHUW_LAST 1386 +PMULHW_FIRST 1387 +PMULHW_LAST 1390 +PMULLD_FIRST 1391 +PMULLD_LAST 1392 +PMULLW_FIRST 1393 +PMULLW_LAST 1396 +PMULUDQ_FIRST 1397 +PMULUDQ_LAST 1400 +POP_FIRST 1401 +POP_LAST 1408 +POPA_FIRST 1409 +POPA_LAST 1409 +POPAD_FIRST 1410 +POPAD_LAST 1410 +POPCNT_FIRST 1411 +POPCNT_LAST 1412 +POPF_FIRST 1413 +POPF_LAST 1413 +POPFD_FIRST 1414 +POPFD_LAST 1414 +POPFQ_FIRST 1415 +POPFQ_LAST 1415 +POR_FIRST 1416 +POR_LAST 1419 +PREFETCHNTA_FIRST 1420 +PREFETCHNTA_LAST 1420 +PREFETCHT0_FIRST 1421 +PREFETCHT0_LAST 1421 +PREFETCHT1_FIRST 1422 +PREFETCHT1_LAST 1422 +PREFETCHT2_FIRST 1423 +PREFETCHT2_LAST 1423 +PREFETCHW_FIRST 1424 +PREFETCHW_LAST 1425 +PREFETCHWT1_FIRST 1426 +PREFETCHWT1_LAST 1426 +PREFETCH_EXCLUSIVE_FIRST 1427 +PREFETCH_EXCLUSIVE_LAST 1427 +PREFETCH_RESERVED_FIRST 1428 +PREFETCH_RESERVED_LAST 1431 +PSADBW_FIRST 1432 +PSADBW_LAST 1435 +PSHUFB_FIRST 1436 +PSHUFB_LAST 1439 +PSHUFD_FIRST 1440 +PSHUFD_LAST 1441 +PSHUFHW_FIRST 1442 +PSHUFHW_LAST 1443 +PSHUFLW_FIRST 1444 +PSHUFLW_LAST 1445 +PSHUFW_FIRST 1446 +PSHUFW_LAST 1447 +PSIGNB_FIRST 1448 +PSIGNB_LAST 1451 +PSIGND_FIRST 1452 +PSIGND_LAST 1455 +PSIGNW_FIRST 1456 +PSIGNW_LAST 1459 +PSLLD_FIRST 1460 +PSLLD_LAST 1465 +PSLLDQ_FIRST 1466 +PSLLDQ_LAST 1466 +PSLLQ_FIRST 1467 +PSLLQ_LAST 1472 +PSLLW_FIRST 1473 +PSLLW_LAST 1478 +PSMASH_FIRST 1479 +PSMASH_LAST 1479 +PSRAD_FIRST 1480 +PSRAD_LAST 1485 +PSRAW_FIRST 1486 +PSRAW_LAST 1491 +PSRLD_FIRST 1492 +PSRLD_LAST 1497 +PSRLDQ_FIRST 1498 +PSRLDQ_LAST 1498 +PSRLQ_FIRST 1499 +PSRLQ_LAST 1504 +PSRLW_FIRST 1505 +PSRLW_LAST 1510 +PSUBB_FIRST 1511 +PSUBB_LAST 1514 +PSUBD_FIRST 1515 +PSUBD_LAST 1518 +PSUBQ_FIRST 1519 +PSUBQ_LAST 1522 +PSUBSB_FIRST 1523 +PSUBSB_LAST 1526 +PSUBSW_FIRST 1527 +PSUBSW_LAST 1530 +PSUBUSB_FIRST 1531 +PSUBUSB_LAST 1534 +PSUBUSW_FIRST 1535 +PSUBUSW_LAST 1538 +PSUBW_FIRST 1539 +PSUBW_LAST 1542 +PSWAPD_FIRST 1543 +PSWAPD_LAST 1544 +PTEST_FIRST 1545 +PTEST_LAST 1546 +PTWRITE_FIRST 1547 +PTWRITE_LAST 1548 +PUNPCKHBW_FIRST 1549 +PUNPCKHBW_LAST 1552 +PUNPCKHDQ_FIRST 1553 +PUNPCKHDQ_LAST 1556 +PUNPCKHQDQ_FIRST 1557 +PUNPCKHQDQ_LAST 1558 +PUNPCKHWD_FIRST 1559 +PUNPCKHWD_LAST 1562 +PUNPCKLBW_FIRST 1563 +PUNPCKLBW_LAST 1566 +PUNPCKLDQ_FIRST 1567 +PUNPCKLDQ_LAST 1570 +PUNPCKLQDQ_FIRST 1571 +PUNPCKLQDQ_LAST 1572 +PUNPCKLWD_FIRST 1573 +PUNPCKLWD_LAST 1576 +PUSH_FIRST 1577 +PUSH_LAST 1587 +PUSHA_FIRST 1588 +PUSHA_LAST 1588 +PUSHAD_FIRST 1589 +PUSHAD_LAST 1589 +PUSHF_FIRST 1590 +PUSHF_LAST 1590 +PUSHFD_FIRST 1591 +PUSHFD_LAST 1591 +PUSHFQ_FIRST 1592 +PUSHFQ_LAST 1592 +PVALIDATE_FIRST 1593 +PVALIDATE_LAST 1593 +PXOR_FIRST 1594 +PXOR_LAST 1597 +RCL_FIRST 1598 +RCL_LAST 1609 +RCPPS_FIRST 1610 +RCPPS_LAST 1611 +RCPSS_FIRST 1612 +RCPSS_LAST 1613 +RCR_FIRST 1614 +RCR_LAST 1625 +RDFSBASE_FIRST 1626 +RDFSBASE_LAST 1626 +RDGSBASE_FIRST 1627 +RDGSBASE_LAST 1627 +RDMSR_FIRST 1628 +RDMSR_LAST 1628 +RDPID_FIRST 1629 +RDPID_LAST 1630 +RDPKRU_FIRST 1631 +RDPKRU_LAST 1631 +RDPMC_FIRST 1632 +RDPMC_LAST 1632 +RDPRU_FIRST 1633 +RDPRU_LAST 1633 +RDRAND_FIRST 1634 +RDRAND_LAST 1634 +RDSEED_FIRST 1635 +RDSEED_LAST 1635 +RDSSPD_FIRST 1636 +RDSSPD_LAST 1636 +RDSSPQ_FIRST 1637 +RDSSPQ_LAST 1637 +RDTSC_FIRST 1638 +RDTSC_LAST 1638 +RDTSCP_FIRST 1639 +RDTSCP_LAST 1639 +REPE_CMPSB_FIRST 1640 +REPE_CMPSB_LAST 1640 +REPE_CMPSD_FIRST 1641 +REPE_CMPSD_LAST 1641 +REPE_CMPSQ_FIRST 1642 +REPE_CMPSQ_LAST 1642 +REPE_CMPSW_FIRST 1643 +REPE_CMPSW_LAST 1643 +REPE_SCASB_FIRST 1644 +REPE_SCASB_LAST 1644 +REPE_SCASD_FIRST 1645 +REPE_SCASD_LAST 1645 +REPE_SCASQ_FIRST 1646 +REPE_SCASQ_LAST 1646 +REPE_SCASW_FIRST 1647 +REPE_SCASW_LAST 1647 +REPNE_CMPSB_FIRST 1648 +REPNE_CMPSB_LAST 1648 +REPNE_CMPSD_FIRST 1649 +REPNE_CMPSD_LAST 1649 +REPNE_CMPSQ_FIRST 1650 +REPNE_CMPSQ_LAST 1650 +REPNE_CMPSW_FIRST 1651 +REPNE_CMPSW_LAST 1651 +REPNE_SCASB_FIRST 1652 +REPNE_SCASB_LAST 1652 +REPNE_SCASD_FIRST 1653 +REPNE_SCASD_LAST 1653 +REPNE_SCASQ_FIRST 1654 +REPNE_SCASQ_LAST 1654 +REPNE_SCASW_FIRST 1655 +REPNE_SCASW_LAST 1655 +REP_INSB_FIRST 1656 +REP_INSB_LAST 1656 +REP_INSD_FIRST 1657 +REP_INSD_LAST 1657 +REP_INSW_FIRST 1658 +REP_INSW_LAST 1658 +REP_LODSB_FIRST 1659 +REP_LODSB_LAST 1659 +REP_LODSD_FIRST 1660 +REP_LODSD_LAST 1660 +REP_LODSQ_FIRST 1661 +REP_LODSQ_LAST 1661 +REP_LODSW_FIRST 1662 +REP_LODSW_LAST 1662 +REP_MONTMUL_FIRST 1663 +REP_MONTMUL_LAST 1663 +REP_MOVSB_FIRST 1664 +REP_MOVSB_LAST 1664 +REP_MOVSD_FIRST 1665 +REP_MOVSD_LAST 1665 +REP_MOVSQ_FIRST 1666 +REP_MOVSQ_LAST 1666 +REP_MOVSW_FIRST 1667 +REP_MOVSW_LAST 1667 +REP_OUTSB_FIRST 1668 +REP_OUTSB_LAST 1668 +REP_OUTSD_FIRST 1669 +REP_OUTSD_LAST 1669 +REP_OUTSW_FIRST 1670 +REP_OUTSW_LAST 1670 +REP_STOSB_FIRST 1671 +REP_STOSB_LAST 1671 +REP_STOSD_FIRST 1672 +REP_STOSD_LAST 1672 +REP_STOSQ_FIRST 1673 +REP_STOSQ_LAST 1673 +REP_STOSW_FIRST 1674 +REP_STOSW_LAST 1674 +REP_XCRYPTCBC_FIRST 1675 +REP_XCRYPTCBC_LAST 1675 +REP_XCRYPTCFB_FIRST 1676 +REP_XCRYPTCFB_LAST 1676 +REP_XCRYPTCTR_FIRST 1677 +REP_XCRYPTCTR_LAST 1677 +REP_XCRYPTECB_FIRST 1678 +REP_XCRYPTECB_LAST 1678 +REP_XCRYPTOFB_FIRST 1679 +REP_XCRYPTOFB_LAST 1679 +REP_XSHA1_FIRST 1680 +REP_XSHA1_LAST 1680 +REP_XSHA256_FIRST 1681 +REP_XSHA256_LAST 1681 +REP_XSTORE_FIRST 1682 +REP_XSTORE_LAST 1682 +RET_FAR_FIRST 1683 +RET_FAR_LAST 1684 +RET_NEAR_FIRST 1685 +RET_NEAR_LAST 1686 +RMPADJUST_FIRST 1687 +RMPADJUST_LAST 1687 +RMPUPDATE_FIRST 1688 +RMPUPDATE_LAST 1688 +ROL_FIRST 1689 +ROL_LAST 1700 +ROR_FIRST 1701 +ROR_LAST 1712 +RORX_FIRST 1713 +RORX_LAST 1716 +ROUNDPD_FIRST 1717 +ROUNDPD_LAST 1718 +ROUNDPS_FIRST 1719 +ROUNDPS_LAST 1720 +ROUNDSD_FIRST 1721 +ROUNDSD_LAST 1722 +ROUNDSS_FIRST 1723 +ROUNDSS_LAST 1724 +RSM_FIRST 1725 +RSM_LAST 1725 +RSQRTPS_FIRST 1726 +RSQRTPS_LAST 1727 +RSQRTSS_FIRST 1728 +RSQRTSS_LAST 1729 +RSTORSSP_FIRST 1730 +RSTORSSP_LAST 1730 +SAHF_FIRST 1731 +SAHF_LAST 1731 +SALC_FIRST 1732 +SALC_LAST 1732 +SAR_FIRST 1733 +SAR_LAST 1744 +SARX_FIRST 1745 +SARX_LAST 1748 +SAVEPREVSSP_FIRST 1749 +SAVEPREVSSP_LAST 1749 +SBB_FIRST 1750 +SBB_LAST 1767 +SBB_LOCK_FIRST 1768 +SBB_LOCK_LAST 1773 +SCASB_FIRST 1774 +SCASB_LAST 1774 +SCASD_FIRST 1775 +SCASD_LAST 1775 +SCASQ_FIRST 1776 +SCASQ_LAST 1776 +SCASW_FIRST 1777 +SCASW_LAST 1777 +SEAMCALL_FIRST 1778 +SEAMCALL_LAST 1778 +SEAMOPS_FIRST 1779 +SEAMOPS_LAST 1779 +SEAMRET_FIRST 1780 +SEAMRET_LAST 1780 +SENDUIPI_FIRST 1781 +SENDUIPI_LAST 1781 +SERIALIZE_FIRST 1782 +SERIALIZE_LAST 1782 +SETB_FIRST 1783 +SETB_LAST 1784 +SETBE_FIRST 1785 +SETBE_LAST 1786 +SETL_FIRST 1787 +SETL_LAST 1788 +SETLE_FIRST 1789 +SETLE_LAST 1790 +SETNB_FIRST 1791 +SETNB_LAST 1792 +SETNBE_FIRST 1793 +SETNBE_LAST 1794 +SETNL_FIRST 1795 +SETNL_LAST 1796 +SETNLE_FIRST 1797 +SETNLE_LAST 1798 +SETNO_FIRST 1799 +SETNO_LAST 1800 +SETNP_FIRST 1801 +SETNP_LAST 1802 +SETNS_FIRST 1803 +SETNS_LAST 1804 +SETNZ_FIRST 1805 +SETNZ_LAST 1806 +SETO_FIRST 1807 +SETO_LAST 1808 +SETP_FIRST 1809 +SETP_LAST 1810 +SETS_FIRST 1811 +SETS_LAST 1812 +SETSSBSY_FIRST 1813 +SETSSBSY_LAST 1813 +SETZ_FIRST 1814 +SETZ_LAST 1815 +SFENCE_FIRST 1816 +SFENCE_LAST 1816 +SGDT_FIRST 1817 +SGDT_LAST 1818 +SHA1MSG1_FIRST 1819 +SHA1MSG1_LAST 1820 +SHA1MSG2_FIRST 1821 +SHA1MSG2_LAST 1822 +SHA1NEXTE_FIRST 1823 +SHA1NEXTE_LAST 1824 +SHA1RNDS4_FIRST 1825 +SHA1RNDS4_LAST 1826 +SHA256MSG1_FIRST 1827 +SHA256MSG1_LAST 1828 +SHA256MSG2_FIRST 1829 +SHA256MSG2_LAST 1830 +SHA256RNDS2_FIRST 1831 +SHA256RNDS2_LAST 1832 +SHL_FIRST 1833 +SHL_LAST 1856 +SHLD_FIRST 1857 +SHLD_LAST 1860 +SHLX_FIRST 1861 +SHLX_LAST 1864 +SHR_FIRST 1865 +SHR_LAST 1876 +SHRD_FIRST 1877 +SHRD_LAST 1880 +SHRX_FIRST 1881 +SHRX_LAST 1884 +SHUFPD_FIRST 1885 +SHUFPD_LAST 1886 +SHUFPS_FIRST 1887 +SHUFPS_LAST 1888 +SIDT_FIRST 1889 +SIDT_LAST 1890 +SKINIT_FIRST 1891 +SKINIT_LAST 1891 +SLDT_FIRST 1892 +SLDT_LAST 1893 +SLWPCB_FIRST 1894 +SLWPCB_LAST 1894 +SMSW_FIRST 1895 +SMSW_LAST 1896 +SQRTPD_FIRST 1897 +SQRTPD_LAST 1898 +SQRTPS_FIRST 1899 +SQRTPS_LAST 1900 +SQRTSD_FIRST 1901 +SQRTSD_LAST 1902 +SQRTSS_FIRST 1903 +SQRTSS_LAST 1904 +STAC_FIRST 1905 +STAC_LAST 1905 +STC_FIRST 1906 +STC_LAST 1906 +STD_FIRST 1907 +STD_LAST 1907 +STGI_FIRST 1908 +STGI_LAST 1908 +STI_FIRST 1909 +STI_LAST 1909 +STMXCSR_FIRST 1910 +STMXCSR_LAST 1910 +STOSB_FIRST 1911 +STOSB_LAST 1911 +STOSD_FIRST 1912 +STOSD_LAST 1912 +STOSQ_FIRST 1913 +STOSQ_LAST 1913 +STOSW_FIRST 1914 +STOSW_LAST 1914 +STR_FIRST 1915 +STR_LAST 1916 +STTILECFG_FIRST 1917 +STTILECFG_LAST 1917 +STUI_FIRST 1918 +STUI_LAST 1918 +SUB_FIRST 1919 +SUB_LAST 1936 +SUBPD_FIRST 1937 +SUBPD_LAST 1938 +SUBPS_FIRST 1939 +SUBPS_LAST 1940 +SUBSD_FIRST 1941 +SUBSD_LAST 1942 +SUBSS_FIRST 1943 +SUBSS_LAST 1944 +SUB_LOCK_FIRST 1945 +SUB_LOCK_LAST 1950 +SWAPGS_FIRST 1951 +SWAPGS_LAST 1951 +SYSCALL_FIRST 1952 +SYSCALL_LAST 1952 +SYSCALL_AMD_FIRST 1953 +SYSCALL_AMD_LAST 1953 +SYSENTER_FIRST 1954 +SYSENTER_LAST 1954 +SYSEXIT_FIRST 1955 +SYSEXIT_LAST 1955 +SYSRET_FIRST 1956 +SYSRET_LAST 1956 +SYSRET64_FIRST 1957 +SYSRET64_LAST 1957 +SYSRET_AMD_FIRST 1958 +SYSRET_AMD_LAST 1958 +T1MSKC_FIRST 1959 +T1MSKC_LAST 1962 +TDCALL_FIRST 1963 +TDCALL_LAST 1963 +TDPBF16PS_FIRST 1964 +TDPBF16PS_LAST 1964 +TDPBSSD_FIRST 1965 +TDPBSSD_LAST 1965 +TDPBSUD_FIRST 1966 +TDPBSUD_LAST 1966 +TDPBUSD_FIRST 1967 +TDPBUSD_LAST 1967 +TDPBUUD_FIRST 1968 +TDPBUUD_LAST 1968 +TEST_FIRST 1969 +TEST_LAST 1982 +TESTUI_FIRST 1983 +TESTUI_LAST 1983 +TILELOADD_FIRST 1984 +TILELOADD_LAST 1984 +TILELOADDT1_FIRST 1985 +TILELOADDT1_LAST 1985 +TILERELEASE_FIRST 1986 +TILERELEASE_LAST 1986 +TILESTORED_FIRST 1987 +TILESTORED_LAST 1987 +TILEZERO_FIRST 1988 +TILEZERO_LAST 1988 +TLBSYNC_FIRST 1989 +TLBSYNC_LAST 1989 +TPAUSE_FIRST 1990 +TPAUSE_LAST 1990 +TZCNT_FIRST 1991 +TZCNT_LAST 1992 +TZMSK_FIRST 1993 +TZMSK_LAST 1996 +UCOMISD_FIRST 1997 +UCOMISD_LAST 1998 +UCOMISS_FIRST 1999 +UCOMISS_LAST 2000 +UD0_FIRST 2001 +UD0_LAST 2003 +UD1_FIRST 2004 +UD1_LAST 2005 +UD2_FIRST 2006 +UD2_LAST 2006 +UIRET_FIRST 2007 +UIRET_LAST 2007 +UMONITOR_FIRST 2008 +UMONITOR_LAST 2008 +UMWAIT_FIRST 2009 +UMWAIT_LAST 2009 +UNPCKHPD_FIRST 2010 +UNPCKHPD_LAST 2011 +UNPCKHPS_FIRST 2012 +UNPCKHPS_LAST 2013 +UNPCKLPD_FIRST 2014 +UNPCKLPD_LAST 2015 +UNPCKLPS_FIRST 2016 +UNPCKLPS_LAST 2017 +V4FMADDPS_FIRST 2018 +V4FMADDPS_LAST 2018 +V4FMADDSS_FIRST 2019 +V4FMADDSS_LAST 2019 +V4FNMADDPS_FIRST 2020 +V4FNMADDPS_LAST 2020 +V4FNMADDSS_FIRST 2021 +V4FNMADDSS_LAST 2021 +VADDPD_FIRST 2022 +VADDPD_LAST 2031 +VADDPH_FIRST 2032 +VADDPH_LAST 2037 +VADDPS_FIRST 2038 +VADDPS_LAST 2047 +VADDSD_FIRST 2048 +VADDSD_LAST 2051 +VADDSH_FIRST 2052 +VADDSH_LAST 2053 +VADDSS_FIRST 2054 +VADDSS_LAST 2057 +VADDSUBPD_FIRST 2058 +VADDSUBPD_LAST 2061 +VADDSUBPS_FIRST 2062 +VADDSUBPS_LAST 2065 +VAESDEC_FIRST 2066 +VAESDEC_LAST 2075 +VAESDECLAST_FIRST 2076 +VAESDECLAST_LAST 2085 +VAESENC_FIRST 2086 +VAESENC_LAST 2095 +VAESENCLAST_FIRST 2096 +VAESENCLAST_LAST 2105 +VAESIMC_FIRST 2106 +VAESIMC_LAST 2107 +VAESKEYGENASSIST_FIRST 2108 +VAESKEYGENASSIST_LAST 2109 +VALIGND_FIRST 2110 +VALIGND_LAST 2115 +VALIGNQ_FIRST 2116 +VALIGNQ_LAST 2121 +VANDNPD_FIRST 2122 +VANDNPD_LAST 2131 +VANDNPS_FIRST 2132 +VANDNPS_LAST 2141 +VANDPD_FIRST 2142 +VANDPD_LAST 2151 +VANDPS_FIRST 2152 +VANDPS_LAST 2161 +VBLENDMPD_FIRST 2162 +VBLENDMPD_LAST 2167 +VBLENDMPS_FIRST 2168 +VBLENDMPS_LAST 2173 +VBLENDPD_FIRST 2174 +VBLENDPD_LAST 2177 +VBLENDPS_FIRST 2178 +VBLENDPS_LAST 2181 +VBLENDVPD_FIRST 2182 +VBLENDVPD_LAST 2185 +VBLENDVPS_FIRST 2186 +VBLENDVPS_LAST 2189 +VBROADCASTF128_FIRST 2190 +VBROADCASTF128_LAST 2190 +VBROADCASTF32X2_FIRST 2191 +VBROADCASTF32X2_LAST 2194 +VBROADCASTF32X4_FIRST 2195 +VBROADCASTF32X4_LAST 2196 +VBROADCASTF32X8_FIRST 2197 +VBROADCASTF32X8_LAST 2197 +VBROADCASTF64X2_FIRST 2198 +VBROADCASTF64X2_LAST 2199 +VBROADCASTF64X4_FIRST 2200 +VBROADCASTF64X4_LAST 2200 +VBROADCASTI128_FIRST 2201 +VBROADCASTI128_LAST 2201 +VBROADCASTI32X2_FIRST 2202 +VBROADCASTI32X2_LAST 2207 +VBROADCASTI32X4_FIRST 2208 +VBROADCASTI32X4_LAST 2209 +VBROADCASTI32X8_FIRST 2210 +VBROADCASTI32X8_LAST 2210 +VBROADCASTI64X2_FIRST 2211 +VBROADCASTI64X2_LAST 2212 +VBROADCASTI64X4_FIRST 2213 +VBROADCASTI64X4_LAST 2213 +VBROADCASTSD_FIRST 2214 +VBROADCASTSD_LAST 2219 +VBROADCASTSS_FIRST 2220 +VBROADCASTSS_LAST 2229 +VCMPPD_FIRST 2230 +VCMPPD_LAST 2239 +VCMPPH_FIRST 2240 +VCMPPH_LAST 2245 +VCMPPS_FIRST 2246 +VCMPPS_LAST 2255 +VCMPSD_FIRST 2256 +VCMPSD_LAST 2259 +VCMPSH_FIRST 2260 +VCMPSH_LAST 2261 +VCMPSS_FIRST 2262 +VCMPSS_LAST 2265 +VCOMISD_FIRST 2266 +VCOMISD_LAST 2269 +VCOMISH_FIRST 2270 +VCOMISH_LAST 2271 +VCOMISS_FIRST 2272 +VCOMISS_LAST 2275 +VCOMPRESSPD_FIRST 2276 +VCOMPRESSPD_LAST 2281 +VCOMPRESSPS_FIRST 2282 +VCOMPRESSPS_LAST 2287 +VCVTDQ2PD_FIRST 2288 +VCVTDQ2PD_LAST 2297 +VCVTDQ2PH_FIRST 2298 +VCVTDQ2PH_LAST 2303 +VCVTDQ2PS_FIRST 2304 +VCVTDQ2PS_LAST 2313 +VCVTNE2PS2BF16_FIRST 2314 +VCVTNE2PS2BF16_LAST 2319 +VCVTNEPS2BF16_FIRST 2320 +VCVTNEPS2BF16_LAST 2325 +VCVTPD2DQ_FIRST 2326 +VCVTPD2DQ_LAST 2335 +VCVTPD2PH_FIRST 2336 +VCVTPD2PH_LAST 2341 +VCVTPD2PS_FIRST 2342 +VCVTPD2PS_LAST 2351 +VCVTPD2QQ_FIRST 2352 +VCVTPD2QQ_LAST 2357 +VCVTPD2UDQ_FIRST 2358 +VCVTPD2UDQ_LAST 2363 +VCVTPD2UQQ_FIRST 2364 +VCVTPD2UQQ_LAST 2369 +VCVTPH2DQ_FIRST 2370 +VCVTPH2DQ_LAST 2375 +VCVTPH2PD_FIRST 2376 +VCVTPH2PD_LAST 2381 +VCVTPH2PS_FIRST 2382 +VCVTPH2PS_LAST 2391 +VCVTPH2PSX_FIRST 2392 +VCVTPH2PSX_LAST 2397 +VCVTPH2QQ_FIRST 2398 +VCVTPH2QQ_LAST 2403 +VCVTPH2UDQ_FIRST 2404 +VCVTPH2UDQ_LAST 2409 +VCVTPH2UQQ_FIRST 2410 +VCVTPH2UQQ_LAST 2415 +VCVTPH2UW_FIRST 2416 +VCVTPH2UW_LAST 2421 +VCVTPH2W_FIRST 2422 +VCVTPH2W_LAST 2427 +VCVTPS2DQ_FIRST 2428 +VCVTPS2DQ_LAST 2437 +VCVTPS2PD_FIRST 2438 +VCVTPS2PD_LAST 2447 +VCVTPS2PH_FIRST 2448 +VCVTPS2PH_LAST 2457 +VCVTPS2PHX_FIRST 2458 +VCVTPS2PHX_LAST 2463 +VCVTPS2QQ_FIRST 2464 +VCVTPS2QQ_LAST 2469 +VCVTPS2UDQ_FIRST 2470 +VCVTPS2UDQ_LAST 2475 +VCVTPS2UQQ_FIRST 2476 +VCVTPS2UQQ_LAST 2481 +VCVTQQ2PD_FIRST 2482 +VCVTQQ2PD_LAST 2487 +VCVTQQ2PH_FIRST 2488 +VCVTQQ2PH_LAST 2493 +VCVTQQ2PS_FIRST 2494 +VCVTQQ2PS_LAST 2499 +VCVTSD2SH_FIRST 2500 +VCVTSD2SH_LAST 2501 +VCVTSD2SI_FIRST 2502 +VCVTSD2SI_LAST 2509 +VCVTSD2SS_FIRST 2510 +VCVTSD2SS_LAST 2513 +VCVTSD2USI_FIRST 2514 +VCVTSD2USI_LAST 2517 +VCVTSH2SD_FIRST 2518 +VCVTSH2SD_LAST 2519 +VCVTSH2SI_FIRST 2520 +VCVTSH2SI_LAST 2523 +VCVTSH2SS_FIRST 2524 +VCVTSH2SS_LAST 2525 +VCVTSH2USI_FIRST 2526 +VCVTSH2USI_LAST 2529 +VCVTSI2SD_FIRST 2530 +VCVTSI2SD_LAST 2537 +VCVTSI2SH_FIRST 2538 +VCVTSI2SH_LAST 2541 +VCVTSI2SS_FIRST 2542 +VCVTSI2SS_LAST 2549 +VCVTSS2SD_FIRST 2550 +VCVTSS2SD_LAST 2553 +VCVTSS2SH_FIRST 2554 +VCVTSS2SH_LAST 2555 +VCVTSS2SI_FIRST 2556 +VCVTSS2SI_LAST 2563 +VCVTSS2USI_FIRST 2564 +VCVTSS2USI_LAST 2567 +VCVTTPD2DQ_FIRST 2568 +VCVTTPD2DQ_LAST 2577 +VCVTTPD2QQ_FIRST 2578 +VCVTTPD2QQ_LAST 2583 +VCVTTPD2UDQ_FIRST 2584 +VCVTTPD2UDQ_LAST 2589 +VCVTTPD2UQQ_FIRST 2590 +VCVTTPD2UQQ_LAST 2595 +VCVTTPH2DQ_FIRST 2596 +VCVTTPH2DQ_LAST 2601 +VCVTTPH2QQ_FIRST 2602 +VCVTTPH2QQ_LAST 2607 +VCVTTPH2UDQ_FIRST 2608 +VCVTTPH2UDQ_LAST 2613 +VCVTTPH2UQQ_FIRST 2614 +VCVTTPH2UQQ_LAST 2619 +VCVTTPH2UW_FIRST 2620 +VCVTTPH2UW_LAST 2625 +VCVTTPH2W_FIRST 2626 +VCVTTPH2W_LAST 2631 +VCVTTPS2DQ_FIRST 2632 +VCVTTPS2DQ_LAST 2641 +VCVTTPS2QQ_FIRST 2642 +VCVTTPS2QQ_LAST 2647 +VCVTTPS2UDQ_FIRST 2648 +VCVTTPS2UDQ_LAST 2653 +VCVTTPS2UQQ_FIRST 2654 +VCVTTPS2UQQ_LAST 2659 +VCVTTSD2SI_FIRST 2660 +VCVTTSD2SI_LAST 2667 +VCVTTSD2USI_FIRST 2668 +VCVTTSD2USI_LAST 2671 +VCVTTSH2SI_FIRST 2672 +VCVTTSH2SI_LAST 2675 +VCVTTSH2USI_FIRST 2676 +VCVTTSH2USI_LAST 2679 +VCVTTSS2SI_FIRST 2680 +VCVTTSS2SI_LAST 2687 +VCVTTSS2USI_FIRST 2688 +VCVTTSS2USI_LAST 2691 +VCVTUDQ2PD_FIRST 2692 +VCVTUDQ2PD_LAST 2697 +VCVTUDQ2PH_FIRST 2698 +VCVTUDQ2PH_LAST 2703 +VCVTUDQ2PS_FIRST 2704 +VCVTUDQ2PS_LAST 2709 +VCVTUQQ2PD_FIRST 2710 +VCVTUQQ2PD_LAST 2715 +VCVTUQQ2PH_FIRST 2716 +VCVTUQQ2PH_LAST 2721 +VCVTUQQ2PS_FIRST 2722 +VCVTUQQ2PS_LAST 2727 +VCVTUSI2SD_FIRST 2728 +VCVTUSI2SD_LAST 2731 +VCVTUSI2SH_FIRST 2732 +VCVTUSI2SH_LAST 2735 +VCVTUSI2SS_FIRST 2736 +VCVTUSI2SS_LAST 2739 +VCVTUW2PH_FIRST 2740 +VCVTUW2PH_LAST 2745 +VCVTW2PH_FIRST 2746 +VCVTW2PH_LAST 2751 +VDBPSADBW_FIRST 2752 +VDBPSADBW_LAST 2757 +VDIVPD_FIRST 2758 +VDIVPD_LAST 2767 +VDIVPH_FIRST 2768 +VDIVPH_LAST 2773 +VDIVPS_FIRST 2774 +VDIVPS_LAST 2783 +VDIVSD_FIRST 2784 +VDIVSD_LAST 2787 +VDIVSH_FIRST 2788 +VDIVSH_LAST 2789 +VDIVSS_FIRST 2790 +VDIVSS_LAST 2793 +VDPBF16PS_FIRST 2794 +VDPBF16PS_LAST 2799 +VDPPD_FIRST 2800 +VDPPD_LAST 2801 +VDPPS_FIRST 2802 +VDPPS_LAST 2805 +VERR_FIRST 2806 +VERR_LAST 2807 +VERW_FIRST 2808 +VERW_LAST 2809 +VEXP2PD_FIRST 2810 +VEXP2PD_LAST 2811 +VEXP2PS_FIRST 2812 +VEXP2PS_LAST 2813 +VEXPANDPD_FIRST 2814 +VEXPANDPD_LAST 2819 +VEXPANDPS_FIRST 2820 +VEXPANDPS_LAST 2825 +VEXTRACTF128_FIRST 2826 +VEXTRACTF128_LAST 2827 +VEXTRACTF32X4_FIRST 2828 +VEXTRACTF32X4_LAST 2831 +VEXTRACTF32X8_FIRST 2832 +VEXTRACTF32X8_LAST 2833 +VEXTRACTF64X2_FIRST 2834 +VEXTRACTF64X2_LAST 2837 +VEXTRACTF64X4_FIRST 2838 +VEXTRACTF64X4_LAST 2839 +VEXTRACTI128_FIRST 2840 +VEXTRACTI128_LAST 2841 +VEXTRACTI32X4_FIRST 2842 +VEXTRACTI32X4_LAST 2845 +VEXTRACTI32X8_FIRST 2846 +VEXTRACTI32X8_LAST 2847 +VEXTRACTI64X2_FIRST 2848 +VEXTRACTI64X2_LAST 2851 +VEXTRACTI64X4_FIRST 2852 +VEXTRACTI64X4_LAST 2853 +VEXTRACTPS_FIRST 2854 +VEXTRACTPS_LAST 2857 +VFCMADDCPH_FIRST 2858 +VFCMADDCPH_LAST 2863 +VFCMADDCSH_FIRST 2864 +VFCMADDCSH_LAST 2865 +VFCMULCPH_FIRST 2866 +VFCMULCPH_LAST 2871 +VFCMULCSH_FIRST 2872 +VFCMULCSH_LAST 2873 +VFIXUPIMMPD_FIRST 2874 +VFIXUPIMMPD_LAST 2879 +VFIXUPIMMPS_FIRST 2880 +VFIXUPIMMPS_LAST 2885 +VFIXUPIMMSD_FIRST 2886 +VFIXUPIMMSD_LAST 2887 +VFIXUPIMMSS_FIRST 2888 +VFIXUPIMMSS_LAST 2889 +VFMADD132PD_FIRST 2890 +VFMADD132PD_LAST 2899 +VFMADD132PH_FIRST 2900 +VFMADD132PH_LAST 2905 +VFMADD132PS_FIRST 2906 +VFMADD132PS_LAST 2915 +VFMADD132SD_FIRST 2916 +VFMADD132SD_LAST 2919 +VFMADD132SH_FIRST 2920 +VFMADD132SH_LAST 2921 +VFMADD132SS_FIRST 2922 +VFMADD132SS_LAST 2925 +VFMADD213PD_FIRST 2926 +VFMADD213PD_LAST 2935 +VFMADD213PH_FIRST 2936 +VFMADD213PH_LAST 2941 +VFMADD213PS_FIRST 2942 +VFMADD213PS_LAST 2951 +VFMADD213SD_FIRST 2952 +VFMADD213SD_LAST 2955 +VFMADD213SH_FIRST 2956 +VFMADD213SH_LAST 2957 +VFMADD213SS_FIRST 2958 +VFMADD213SS_LAST 2961 +VFMADD231PD_FIRST 2962 +VFMADD231PD_LAST 2971 +VFMADD231PH_FIRST 2972 +VFMADD231PH_LAST 2977 +VFMADD231PS_FIRST 2978 +VFMADD231PS_LAST 2987 +VFMADD231SD_FIRST 2988 +VFMADD231SD_LAST 2991 +VFMADD231SH_FIRST 2992 +VFMADD231SH_LAST 2993 +VFMADD231SS_FIRST 2994 +VFMADD231SS_LAST 2997 +VFMADDCPH_FIRST 2998 +VFMADDCPH_LAST 3003 +VFMADDCSH_FIRST 3004 +VFMADDCSH_LAST 3005 +VFMADDPD_FIRST 3006 +VFMADDPD_LAST 3011 +VFMADDPS_FIRST 3012 +VFMADDPS_LAST 3017 +VFMADDSD_FIRST 3018 +VFMADDSD_LAST 3020 +VFMADDSS_FIRST 3021 +VFMADDSS_LAST 3023 +VFMADDSUB132PD_FIRST 3024 +VFMADDSUB132PD_LAST 3033 +VFMADDSUB132PH_FIRST 3034 +VFMADDSUB132PH_LAST 3039 +VFMADDSUB132PS_FIRST 3040 +VFMADDSUB132PS_LAST 3049 +VFMADDSUB213PD_FIRST 3050 +VFMADDSUB213PD_LAST 3059 +VFMADDSUB213PH_FIRST 3060 +VFMADDSUB213PH_LAST 3065 +VFMADDSUB213PS_FIRST 3066 +VFMADDSUB213PS_LAST 3075 +VFMADDSUB231PD_FIRST 3076 +VFMADDSUB231PD_LAST 3085 +VFMADDSUB231PH_FIRST 3086 +VFMADDSUB231PH_LAST 3091 +VFMADDSUB231PS_FIRST 3092 +VFMADDSUB231PS_LAST 3101 +VFMADDSUBPD_FIRST 3102 +VFMADDSUBPD_LAST 3107 +VFMADDSUBPS_FIRST 3108 +VFMADDSUBPS_LAST 3113 +VFMSUB132PD_FIRST 3114 +VFMSUB132PD_LAST 3123 +VFMSUB132PH_FIRST 3124 +VFMSUB132PH_LAST 3129 +VFMSUB132PS_FIRST 3130 +VFMSUB132PS_LAST 3139 +VFMSUB132SD_FIRST 3140 +VFMSUB132SD_LAST 3143 +VFMSUB132SH_FIRST 3144 +VFMSUB132SH_LAST 3145 +VFMSUB132SS_FIRST 3146 +VFMSUB132SS_LAST 3149 +VFMSUB213PD_FIRST 3150 +VFMSUB213PD_LAST 3159 +VFMSUB213PH_FIRST 3160 +VFMSUB213PH_LAST 3165 +VFMSUB213PS_FIRST 3166 +VFMSUB213PS_LAST 3175 +VFMSUB213SD_FIRST 3176 +VFMSUB213SD_LAST 3179 +VFMSUB213SH_FIRST 3180 +VFMSUB213SH_LAST 3181 +VFMSUB213SS_FIRST 3182 +VFMSUB213SS_LAST 3185 +VFMSUB231PD_FIRST 3186 +VFMSUB231PD_LAST 3195 +VFMSUB231PH_FIRST 3196 +VFMSUB231PH_LAST 3201 +VFMSUB231PS_FIRST 3202 +VFMSUB231PS_LAST 3211 +VFMSUB231SD_FIRST 3212 +VFMSUB231SD_LAST 3215 +VFMSUB231SH_FIRST 3216 +VFMSUB231SH_LAST 3217 +VFMSUB231SS_FIRST 3218 +VFMSUB231SS_LAST 3221 +VFMSUBADD132PD_FIRST 3222 +VFMSUBADD132PD_LAST 3231 +VFMSUBADD132PH_FIRST 3232 +VFMSUBADD132PH_LAST 3237 +VFMSUBADD132PS_FIRST 3238 +VFMSUBADD132PS_LAST 3247 +VFMSUBADD213PD_FIRST 3248 +VFMSUBADD213PD_LAST 3257 +VFMSUBADD213PH_FIRST 3258 +VFMSUBADD213PH_LAST 3263 +VFMSUBADD213PS_FIRST 3264 +VFMSUBADD213PS_LAST 3273 +VFMSUBADD231PD_FIRST 3274 +VFMSUBADD231PD_LAST 3283 +VFMSUBADD231PH_FIRST 3284 +VFMSUBADD231PH_LAST 3289 +VFMSUBADD231PS_FIRST 3290 +VFMSUBADD231PS_LAST 3299 +VFMSUBADDPD_FIRST 3300 +VFMSUBADDPD_LAST 3305 +VFMSUBADDPS_FIRST 3306 +VFMSUBADDPS_LAST 3311 +VFMSUBPD_FIRST 3312 +VFMSUBPD_LAST 3317 +VFMSUBPS_FIRST 3318 +VFMSUBPS_LAST 3323 +VFMSUBSD_FIRST 3324 +VFMSUBSD_LAST 3326 +VFMSUBSS_FIRST 3327 +VFMSUBSS_LAST 3329 +VFMULCPH_FIRST 3330 +VFMULCPH_LAST 3335 +VFMULCSH_FIRST 3336 +VFMULCSH_LAST 3337 +VFNMADD132PD_FIRST 3338 +VFNMADD132PD_LAST 3347 +VFNMADD132PH_FIRST 3348 +VFNMADD132PH_LAST 3353 +VFNMADD132PS_FIRST 3354 +VFNMADD132PS_LAST 3363 +VFNMADD132SD_FIRST 3364 +VFNMADD132SD_LAST 3367 +VFNMADD132SH_FIRST 3368 +VFNMADD132SH_LAST 3369 +VFNMADD132SS_FIRST 3370 +VFNMADD132SS_LAST 3373 +VFNMADD213PD_FIRST 3374 +VFNMADD213PD_LAST 3383 +VFNMADD213PH_FIRST 3384 +VFNMADD213PH_LAST 3389 +VFNMADD213PS_FIRST 3390 +VFNMADD213PS_LAST 3399 +VFNMADD213SD_FIRST 3400 +VFNMADD213SD_LAST 3403 +VFNMADD213SH_FIRST 3404 +VFNMADD213SH_LAST 3405 +VFNMADD213SS_FIRST 3406 +VFNMADD213SS_LAST 3409 +VFNMADD231PD_FIRST 3410 +VFNMADD231PD_LAST 3419 +VFNMADD231PH_FIRST 3420 +VFNMADD231PH_LAST 3425 +VFNMADD231PS_FIRST 3426 +VFNMADD231PS_LAST 3435 +VFNMADD231SD_FIRST 3436 +VFNMADD231SD_LAST 3439 +VFNMADD231SH_FIRST 3440 +VFNMADD231SH_LAST 3441 +VFNMADD231SS_FIRST 3442 +VFNMADD231SS_LAST 3445 +VFNMADDPD_FIRST 3446 +VFNMADDPD_LAST 3451 +VFNMADDPS_FIRST 3452 +VFNMADDPS_LAST 3457 +VFNMADDSD_FIRST 3458 +VFNMADDSD_LAST 3460 +VFNMADDSS_FIRST 3461 +VFNMADDSS_LAST 3463 +VFNMSUB132PD_FIRST 3464 +VFNMSUB132PD_LAST 3473 +VFNMSUB132PH_FIRST 3474 +VFNMSUB132PH_LAST 3479 +VFNMSUB132PS_FIRST 3480 +VFNMSUB132PS_LAST 3489 +VFNMSUB132SD_FIRST 3490 +VFNMSUB132SD_LAST 3493 +VFNMSUB132SH_FIRST 3494 +VFNMSUB132SH_LAST 3495 +VFNMSUB132SS_FIRST 3496 +VFNMSUB132SS_LAST 3499 +VFNMSUB213PD_FIRST 3500 +VFNMSUB213PD_LAST 3509 +VFNMSUB213PH_FIRST 3510 +VFNMSUB213PH_LAST 3515 +VFNMSUB213PS_FIRST 3516 +VFNMSUB213PS_LAST 3525 +VFNMSUB213SD_FIRST 3526 +VFNMSUB213SD_LAST 3529 +VFNMSUB213SH_FIRST 3530 +VFNMSUB213SH_LAST 3531 +VFNMSUB213SS_FIRST 3532 +VFNMSUB213SS_LAST 3535 +VFNMSUB231PD_FIRST 3536 +VFNMSUB231PD_LAST 3545 +VFNMSUB231PH_FIRST 3546 +VFNMSUB231PH_LAST 3551 +VFNMSUB231PS_FIRST 3552 +VFNMSUB231PS_LAST 3561 +VFNMSUB231SD_FIRST 3562 +VFNMSUB231SD_LAST 3565 +VFNMSUB231SH_FIRST 3566 +VFNMSUB231SH_LAST 3567 +VFNMSUB231SS_FIRST 3568 +VFNMSUB231SS_LAST 3571 +VFNMSUBPD_FIRST 3572 +VFNMSUBPD_LAST 3577 +VFNMSUBPS_FIRST 3578 +VFNMSUBPS_LAST 3583 +VFNMSUBSD_FIRST 3584 +VFNMSUBSD_LAST 3586 +VFNMSUBSS_FIRST 3587 +VFNMSUBSS_LAST 3589 +VFPCLASSPD_FIRST 3590 +VFPCLASSPD_LAST 3595 +VFPCLASSPH_FIRST 3596 +VFPCLASSPH_LAST 3601 +VFPCLASSPS_FIRST 3602 +VFPCLASSPS_LAST 3607 +VFPCLASSSD_FIRST 3608 +VFPCLASSSD_LAST 3609 +VFPCLASSSH_FIRST 3610 +VFPCLASSSH_LAST 3611 +VFPCLASSSS_FIRST 3612 +VFPCLASSSS_LAST 3613 +VFRCZPD_FIRST 3614 +VFRCZPD_LAST 3617 +VFRCZPS_FIRST 3618 +VFRCZPS_LAST 3621 +VFRCZSD_FIRST 3622 +VFRCZSD_LAST 3623 +VFRCZSS_FIRST 3624 +VFRCZSS_LAST 3625 +VGATHERDPD_FIRST 3626 +VGATHERDPD_LAST 3630 +VGATHERDPS_FIRST 3631 +VGATHERDPS_LAST 3635 +VGATHERPF0DPD_FIRST 3636 +VGATHERPF0DPD_LAST 3636 +VGATHERPF0DPS_FIRST 3637 +VGATHERPF0DPS_LAST 3637 +VGATHERPF0QPD_FIRST 3638 +VGATHERPF0QPD_LAST 3638 +VGATHERPF0QPS_FIRST 3639 +VGATHERPF0QPS_LAST 3639 +VGATHERPF1DPD_FIRST 3640 +VGATHERPF1DPD_LAST 3640 +VGATHERPF1DPS_FIRST 3641 +VGATHERPF1DPS_LAST 3641 +VGATHERPF1QPD_FIRST 3642 +VGATHERPF1QPD_LAST 3642 +VGATHERPF1QPS_FIRST 3643 +VGATHERPF1QPS_LAST 3643 +VGATHERQPD_FIRST 3644 +VGATHERQPD_LAST 3648 +VGATHERQPS_FIRST 3649 +VGATHERQPS_LAST 3653 +VGETEXPPD_FIRST 3654 +VGETEXPPD_LAST 3659 +VGETEXPPH_FIRST 3660 +VGETEXPPH_LAST 3665 +VGETEXPPS_FIRST 3666 +VGETEXPPS_LAST 3671 +VGETEXPSD_FIRST 3672 +VGETEXPSD_LAST 3673 +VGETEXPSH_FIRST 3674 +VGETEXPSH_LAST 3675 +VGETEXPSS_FIRST 3676 +VGETEXPSS_LAST 3677 +VGETMANTPD_FIRST 3678 +VGETMANTPD_LAST 3683 +VGETMANTPH_FIRST 3684 +VGETMANTPH_LAST 3689 +VGETMANTPS_FIRST 3690 +VGETMANTPS_LAST 3695 +VGETMANTSD_FIRST 3696 +VGETMANTSD_LAST 3697 +VGETMANTSH_FIRST 3698 +VGETMANTSH_LAST 3699 +VGETMANTSS_FIRST 3700 +VGETMANTSS_LAST 3701 +VGF2P8AFFINEINVQB_FIRST 3702 +VGF2P8AFFINEINVQB_LAST 3711 +VGF2P8AFFINEQB_FIRST 3712 +VGF2P8AFFINEQB_LAST 3721 +VGF2P8MULB_FIRST 3722 +VGF2P8MULB_LAST 3731 +VHADDPD_FIRST 3732 +VHADDPD_LAST 3735 +VHADDPS_FIRST 3736 +VHADDPS_LAST 3739 +VHSUBPD_FIRST 3740 +VHSUBPD_LAST 3743 +VHSUBPS_FIRST 3744 +VHSUBPS_LAST 3747 +VINSERTF128_FIRST 3748 +VINSERTF128_LAST 3749 +VINSERTF32X4_FIRST 3750 +VINSERTF32X4_LAST 3753 +VINSERTF32X8_FIRST 3754 +VINSERTF32X8_LAST 3755 +VINSERTF64X2_FIRST 3756 +VINSERTF64X2_LAST 3759 +VINSERTF64X4_FIRST 3760 +VINSERTF64X4_LAST 3761 +VINSERTI128_FIRST 3762 +VINSERTI128_LAST 3763 +VINSERTI32X4_FIRST 3764 +VINSERTI32X4_LAST 3767 +VINSERTI32X8_FIRST 3768 +VINSERTI32X8_LAST 3769 +VINSERTI64X2_FIRST 3770 +VINSERTI64X2_LAST 3773 +VINSERTI64X4_FIRST 3774 +VINSERTI64X4_LAST 3775 +VINSERTPS_FIRST 3776 +VINSERTPS_LAST 3779 +VLDDQU_FIRST 3780 +VLDDQU_LAST 3781 +VLDMXCSR_FIRST 3782 +VLDMXCSR_LAST 3782 +VMASKMOVDQU_FIRST 3783 +VMASKMOVDQU_LAST 3783 +VMASKMOVPD_FIRST 3784 +VMASKMOVPD_LAST 3787 +VMASKMOVPS_FIRST 3788 +VMASKMOVPS_LAST 3791 +VMAXPD_FIRST 3792 +VMAXPD_LAST 3801 +VMAXPH_FIRST 3802 +VMAXPH_LAST 3807 +VMAXPS_FIRST 3808 +VMAXPS_LAST 3817 +VMAXSD_FIRST 3818 +VMAXSD_LAST 3821 +VMAXSH_FIRST 3822 +VMAXSH_LAST 3823 +VMAXSS_FIRST 3824 +VMAXSS_LAST 3827 +VMCALL_FIRST 3828 +VMCALL_LAST 3828 +VMCLEAR_FIRST 3829 +VMCLEAR_LAST 3829 +VMFUNC_FIRST 3830 +VMFUNC_LAST 3830 +VMINPD_FIRST 3831 +VMINPD_LAST 3840 +VMINPH_FIRST 3841 +VMINPH_LAST 3846 +VMINPS_FIRST 3847 +VMINPS_LAST 3856 +VMINSD_FIRST 3857 +VMINSD_LAST 3860 +VMINSH_FIRST 3861 +VMINSH_LAST 3862 +VMINSS_FIRST 3863 +VMINSS_LAST 3866 +VMLAUNCH_FIRST 3867 +VMLAUNCH_LAST 3867 +VMLOAD_FIRST 3868 +VMLOAD_LAST 3868 +VMMCALL_FIRST 3869 +VMMCALL_LAST 3869 +VMOVAPD_FIRST 3870 +VMOVAPD_LAST 3886 +VMOVAPS_FIRST 3887 +VMOVAPS_LAST 3903 +VMOVD_FIRST 3904 +VMOVD_LAST 3911 +VMOVDDUP_FIRST 3912 +VMOVDDUP_LAST 3921 +VMOVDQA_FIRST 3922 +VMOVDQA_LAST 3929 +VMOVDQA32_FIRST 3930 +VMOVDQA32_LAST 3938 +VMOVDQA64_FIRST 3939 +VMOVDQA64_LAST 3947 +VMOVDQU_FIRST 3948 +VMOVDQU_LAST 3955 +VMOVDQU16_FIRST 3956 +VMOVDQU16_LAST 3964 +VMOVDQU32_FIRST 3965 +VMOVDQU32_LAST 3973 +VMOVDQU64_FIRST 3974 +VMOVDQU64_LAST 3982 +VMOVDQU8_FIRST 3983 +VMOVDQU8_LAST 3991 +VMOVHLPS_FIRST 3992 +VMOVHLPS_LAST 3993 +VMOVHPD_FIRST 3994 +VMOVHPD_LAST 3997 +VMOVHPS_FIRST 3998 +VMOVHPS_LAST 4001 +VMOVLHPS_FIRST 4002 +VMOVLHPS_LAST 4003 +VMOVLPD_FIRST 4004 +VMOVLPD_LAST 4007 +VMOVLPS_FIRST 4008 +VMOVLPS_LAST 4011 +VMOVMSKPD_FIRST 4012 +VMOVMSKPD_LAST 4013 +VMOVMSKPS_FIRST 4014 +VMOVMSKPS_LAST 4015 +VMOVNTDQ_FIRST 4016 +VMOVNTDQ_LAST 4020 +VMOVNTDQA_FIRST 4021 +VMOVNTDQA_LAST 4025 +VMOVNTPD_FIRST 4026 +VMOVNTPD_LAST 4030 +VMOVNTPS_FIRST 4031 +VMOVNTPS_LAST 4035 +VMOVQ_FIRST 4036 +VMOVQ_LAST 4048 +VMOVSD_FIRST 4049 +VMOVSD_LAST 4055 +VMOVSH_FIRST 4056 +VMOVSH_LAST 4058 +VMOVSHDUP_FIRST 4059 +VMOVSHDUP_LAST 4068 +VMOVSLDUP_FIRST 4069 +VMOVSLDUP_LAST 4078 +VMOVSS_FIRST 4079 +VMOVSS_LAST 4085 +VMOVUPD_FIRST 4086 +VMOVUPD_LAST 4102 +VMOVUPS_FIRST 4103 +VMOVUPS_LAST 4119 +VMOVW_FIRST 4120 +VMOVW_LAST 4123 +VMPSADBW_FIRST 4124 +VMPSADBW_LAST 4127 +VMPTRLD_FIRST 4128 +VMPTRLD_LAST 4128 +VMPTRST_FIRST 4129 +VMPTRST_LAST 4129 +VMREAD_FIRST 4130 +VMREAD_LAST 4133 +VMRESUME_FIRST 4134 +VMRESUME_LAST 4134 +VMRUN_FIRST 4135 +VMRUN_LAST 4135 +VMSAVE_FIRST 4136 +VMSAVE_LAST 4136 +VMULPD_FIRST 4137 +VMULPD_LAST 4146 +VMULPH_FIRST 4147 +VMULPH_LAST 4152 +VMULPS_FIRST 4153 +VMULPS_LAST 4162 +VMULSD_FIRST 4163 +VMULSD_LAST 4166 +VMULSH_FIRST 4167 +VMULSH_LAST 4168 +VMULSS_FIRST 4169 +VMULSS_LAST 4172 +VMWRITE_FIRST 4173 +VMWRITE_LAST 4176 +VMXOFF_FIRST 4177 +VMXOFF_LAST 4177 +VMXON_FIRST 4178 +VMXON_LAST 4178 +VORPD_FIRST 4179 +VORPD_LAST 4188 +VORPS_FIRST 4189 +VORPS_LAST 4198 +VP2INTERSECTD_FIRST 4199 +VP2INTERSECTD_LAST 4204 +VP2INTERSECTQ_FIRST 4205 +VP2INTERSECTQ_LAST 4210 +VP4DPWSSD_FIRST 4211 +VP4DPWSSD_LAST 4211 +VP4DPWSSDS_FIRST 4212 +VP4DPWSSDS_LAST 4212 +VPABSB_FIRST 4213 +VPABSB_LAST 4222 +VPABSD_FIRST 4223 +VPABSD_LAST 4232 +VPABSQ_FIRST 4233 +VPABSQ_LAST 4238 +VPABSW_FIRST 4239 +VPABSW_LAST 4248 +VPACKSSDW_FIRST 4249 +VPACKSSDW_LAST 4258 +VPACKSSWB_FIRST 4259 +VPACKSSWB_LAST 4268 +VPACKUSDW_FIRST 4269 +VPACKUSDW_LAST 4278 +VPACKUSWB_FIRST 4279 +VPACKUSWB_LAST 4288 +VPADDB_FIRST 4289 +VPADDB_LAST 4298 +VPADDD_FIRST 4299 +VPADDD_LAST 4308 +VPADDQ_FIRST 4309 +VPADDQ_LAST 4318 +VPADDSB_FIRST 4319 +VPADDSB_LAST 4328 +VPADDSW_FIRST 4329 +VPADDSW_LAST 4338 +VPADDUSB_FIRST 4339 +VPADDUSB_LAST 4348 +VPADDUSW_FIRST 4349 +VPADDUSW_LAST 4358 +VPADDW_FIRST 4359 +VPADDW_LAST 4368 +VPALIGNR_FIRST 4369 +VPALIGNR_LAST 4378 +VPAND_FIRST 4379 +VPAND_LAST 4382 +VPANDD_FIRST 4383 +VPANDD_LAST 4388 +VPANDN_FIRST 4389 +VPANDN_LAST 4392 +VPANDND_FIRST 4393 +VPANDND_LAST 4398 +VPANDNQ_FIRST 4399 +VPANDNQ_LAST 4404 +VPANDQ_FIRST 4405 +VPANDQ_LAST 4410 +VPAVGB_FIRST 4411 +VPAVGB_LAST 4420 +VPAVGW_FIRST 4421 +VPAVGW_LAST 4430 +VPBLENDD_FIRST 4431 +VPBLENDD_LAST 4434 +VPBLENDMB_FIRST 4435 +VPBLENDMB_LAST 4440 +VPBLENDMD_FIRST 4441 +VPBLENDMD_LAST 4446 +VPBLENDMQ_FIRST 4447 +VPBLENDMQ_LAST 4452 +VPBLENDMW_FIRST 4453 +VPBLENDMW_LAST 4458 +VPBLENDVB_FIRST 4459 +VPBLENDVB_LAST 4462 +VPBLENDW_FIRST 4463 +VPBLENDW_LAST 4466 +VPBROADCASTB_FIRST 4467 +VPBROADCASTB_LAST 4479 +VPBROADCASTD_FIRST 4480 +VPBROADCASTD_LAST 4492 +VPBROADCASTMB2Q_FIRST 4493 +VPBROADCASTMB2Q_LAST 4495 +VPBROADCASTMW2D_FIRST 4496 +VPBROADCASTMW2D_LAST 4498 +VPBROADCASTQ_FIRST 4499 +VPBROADCASTQ_LAST 4511 +VPBROADCASTW_FIRST 4512 +VPBROADCASTW_LAST 4524 +VPCLMULQDQ_FIRST 4525 +VPCLMULQDQ_LAST 4534 +VPCMOV_FIRST 4535 +VPCMOV_LAST 4540 +VPCMPB_FIRST 4541 +VPCMPB_LAST 4546 +VPCMPD_FIRST 4547 +VPCMPD_LAST 4552 +VPCMPEQB_FIRST 4553 +VPCMPEQB_LAST 4562 +VPCMPEQD_FIRST 4563 +VPCMPEQD_LAST 4572 +VPCMPEQQ_FIRST 4573 +VPCMPEQQ_LAST 4582 +VPCMPEQW_FIRST 4583 +VPCMPEQW_LAST 4592 +VPCMPESTRI_FIRST 4593 +VPCMPESTRI_LAST 4594 +VPCMPESTRI64_FIRST 4595 +VPCMPESTRI64_LAST 4596 +VPCMPESTRM_FIRST 4597 +VPCMPESTRM_LAST 4598 +VPCMPESTRM64_FIRST 4599 +VPCMPESTRM64_LAST 4600 +VPCMPGTB_FIRST 4601 +VPCMPGTB_LAST 4610 +VPCMPGTD_FIRST 4611 +VPCMPGTD_LAST 4620 +VPCMPGTQ_FIRST 4621 +VPCMPGTQ_LAST 4630 +VPCMPGTW_FIRST 4631 +VPCMPGTW_LAST 4640 +VPCMPISTRI_FIRST 4641 +VPCMPISTRI_LAST 4642 +VPCMPISTRI64_FIRST 4643 +VPCMPISTRI64_LAST 4644 +VPCMPISTRM_FIRST 4645 +VPCMPISTRM_LAST 4646 +VPCMPQ_FIRST 4647 +VPCMPQ_LAST 4652 +VPCMPUB_FIRST 4653 +VPCMPUB_LAST 4658 +VPCMPUD_FIRST 4659 +VPCMPUD_LAST 4664 +VPCMPUQ_FIRST 4665 +VPCMPUQ_LAST 4670 +VPCMPUW_FIRST 4671 +VPCMPUW_LAST 4676 +VPCMPW_FIRST 4677 +VPCMPW_LAST 4682 +VPCOMB_FIRST 4683 +VPCOMB_LAST 4684 +VPCOMD_FIRST 4685 +VPCOMD_LAST 4686 +VPCOMPRESSB_FIRST 4687 +VPCOMPRESSB_LAST 4692 +VPCOMPRESSD_FIRST 4693 +VPCOMPRESSD_LAST 4698 +VPCOMPRESSQ_FIRST 4699 +VPCOMPRESSQ_LAST 4704 +VPCOMPRESSW_FIRST 4705 +VPCOMPRESSW_LAST 4710 +VPCOMQ_FIRST 4711 +VPCOMQ_LAST 4712 +VPCOMUB_FIRST 4713 +VPCOMUB_LAST 4714 +VPCOMUD_FIRST 4715 +VPCOMUD_LAST 4716 +VPCOMUQ_FIRST 4717 +VPCOMUQ_LAST 4718 +VPCOMUW_FIRST 4719 +VPCOMUW_LAST 4720 +VPCOMW_FIRST 4721 +VPCOMW_LAST 4722 +VPCONFLICTD_FIRST 4723 +VPCONFLICTD_LAST 4728 +VPCONFLICTQ_FIRST 4729 +VPCONFLICTQ_LAST 4734 +VPDPBUSD_FIRST 4735 +VPDPBUSD_LAST 4744 +VPDPBUSDS_FIRST 4745 +VPDPBUSDS_LAST 4754 +VPDPWSSD_FIRST 4755 +VPDPWSSD_LAST 4764 +VPDPWSSDS_FIRST 4765 +VPDPWSSDS_LAST 4774 +VPERM2F128_FIRST 4775 +VPERM2F128_LAST 4776 +VPERM2I128_FIRST 4777 +VPERM2I128_LAST 4778 +VPERMB_FIRST 4779 +VPERMB_LAST 4784 +VPERMD_FIRST 4785 +VPERMD_LAST 4790 +VPERMI2B_FIRST 4791 +VPERMI2B_LAST 4796 +VPERMI2D_FIRST 4797 +VPERMI2D_LAST 4802 +VPERMI2PD_FIRST 4803 +VPERMI2PD_LAST 4808 +VPERMI2PS_FIRST 4809 +VPERMI2PS_LAST 4814 +VPERMI2Q_FIRST 4815 +VPERMI2Q_LAST 4820 +VPERMI2W_FIRST 4821 +VPERMI2W_LAST 4826 +VPERMIL2PD_FIRST 4827 +VPERMIL2PD_LAST 4832 +VPERMIL2PS_FIRST 4833 +VPERMIL2PS_LAST 4838 +VPERMILPD_FIRST 4839 +VPERMILPD_LAST 4858 +VPERMILPS_FIRST 4859 +VPERMILPS_LAST 4878 +VPERMPD_FIRST 4879 +VPERMPD_LAST 4888 +VPERMPS_FIRST 4889 +VPERMPS_LAST 4894 +VPERMQ_FIRST 4895 +VPERMQ_LAST 4904 +VPERMT2B_FIRST 4905 +VPERMT2B_LAST 4910 +VPERMT2D_FIRST 4911 +VPERMT2D_LAST 4916 +VPERMT2PD_FIRST 4917 +VPERMT2PD_LAST 4922 +VPERMT2PS_FIRST 4923 +VPERMT2PS_LAST 4928 +VPERMT2Q_FIRST 4929 +VPERMT2Q_LAST 4934 +VPERMT2W_FIRST 4935 +VPERMT2W_LAST 4940 +VPERMW_FIRST 4941 +VPERMW_LAST 4946 +VPEXPANDB_FIRST 4947 +VPEXPANDB_LAST 4952 +VPEXPANDD_FIRST 4953 +VPEXPANDD_LAST 4958 +VPEXPANDQ_FIRST 4959 +VPEXPANDQ_LAST 4964 +VPEXPANDW_FIRST 4965 +VPEXPANDW_LAST 4970 +VPEXTRB_FIRST 4971 +VPEXTRB_LAST 4974 +VPEXTRD_FIRST 4975 +VPEXTRD_LAST 4978 +VPEXTRQ_FIRST 4979 +VPEXTRQ_LAST 4982 +VPEXTRW_FIRST 4983 +VPEXTRW_LAST 4987 +VPEXTRW_C5_FIRST 4988 +VPEXTRW_C5_LAST 4988 +VPGATHERDD_FIRST 4989 +VPGATHERDD_LAST 4993 +VPGATHERDQ_FIRST 4994 +VPGATHERDQ_LAST 4998 +VPGATHERQD_FIRST 4999 +VPGATHERQD_LAST 5003 +VPGATHERQQ_FIRST 5004 +VPGATHERQQ_LAST 5008 +VPHADDBD_FIRST 5009 +VPHADDBD_LAST 5010 +VPHADDBQ_FIRST 5011 +VPHADDBQ_LAST 5012 +VPHADDBW_FIRST 5013 +VPHADDBW_LAST 5014 +VPHADDD_FIRST 5015 +VPHADDD_LAST 5018 +VPHADDDQ_FIRST 5019 +VPHADDDQ_LAST 5020 +VPHADDSW_FIRST 5021 +VPHADDSW_LAST 5024 +VPHADDUBD_FIRST 5025 +VPHADDUBD_LAST 5026 +VPHADDUBQ_FIRST 5027 +VPHADDUBQ_LAST 5028 +VPHADDUBW_FIRST 5029 +VPHADDUBW_LAST 5030 +VPHADDUDQ_FIRST 5031 +VPHADDUDQ_LAST 5032 +VPHADDUWD_FIRST 5033 +VPHADDUWD_LAST 5034 +VPHADDUWQ_FIRST 5035 +VPHADDUWQ_LAST 5036 +VPHADDW_FIRST 5037 +VPHADDW_LAST 5040 +VPHADDWD_FIRST 5041 +VPHADDWD_LAST 5042 +VPHADDWQ_FIRST 5043 +VPHADDWQ_LAST 5044 +VPHMINPOSUW_FIRST 5045 +VPHMINPOSUW_LAST 5046 +VPHSUBBW_FIRST 5047 +VPHSUBBW_LAST 5048 +VPHSUBD_FIRST 5049 +VPHSUBD_LAST 5052 +VPHSUBDQ_FIRST 5053 +VPHSUBDQ_LAST 5054 +VPHSUBSW_FIRST 5055 +VPHSUBSW_LAST 5058 +VPHSUBW_FIRST 5059 +VPHSUBW_LAST 5062 +VPHSUBWD_FIRST 5063 +VPHSUBWD_LAST 5064 +VPINSRB_FIRST 5065 +VPINSRB_LAST 5068 +VPINSRD_FIRST 5069 +VPINSRD_LAST 5072 +VPINSRQ_FIRST 5073 +VPINSRQ_LAST 5076 +VPINSRW_FIRST 5077 +VPINSRW_LAST 5080 +VPLZCNTD_FIRST 5081 +VPLZCNTD_LAST 5086 +VPLZCNTQ_FIRST 5087 +VPLZCNTQ_LAST 5092 +VPMACSDD_FIRST 5093 +VPMACSDD_LAST 5094 +VPMACSDQH_FIRST 5095 +VPMACSDQH_LAST 5096 +VPMACSDQL_FIRST 5097 +VPMACSDQL_LAST 5098 +VPMACSSDD_FIRST 5099 +VPMACSSDD_LAST 5100 +VPMACSSDQH_FIRST 5101 +VPMACSSDQH_LAST 5102 +VPMACSSDQL_FIRST 5103 +VPMACSSDQL_LAST 5104 +VPMACSSWD_FIRST 5105 +VPMACSSWD_LAST 5106 +VPMACSSWW_FIRST 5107 +VPMACSSWW_LAST 5108 +VPMACSWD_FIRST 5109 +VPMACSWD_LAST 5110 +VPMACSWW_FIRST 5111 +VPMACSWW_LAST 5112 +VPMADCSSWD_FIRST 5113 +VPMADCSSWD_LAST 5114 +VPMADCSWD_FIRST 5115 +VPMADCSWD_LAST 5116 +VPMADD52HUQ_FIRST 5117 +VPMADD52HUQ_LAST 5122 +VPMADD52LUQ_FIRST 5123 +VPMADD52LUQ_LAST 5128 +VPMADDUBSW_FIRST 5129 +VPMADDUBSW_LAST 5138 +VPMADDWD_FIRST 5139 +VPMADDWD_LAST 5148 +VPMASKMOVD_FIRST 5149 +VPMASKMOVD_LAST 5152 +VPMASKMOVQ_FIRST 5153 +VPMASKMOVQ_LAST 5156 +VPMAXSB_FIRST 5157 +VPMAXSB_LAST 5166 +VPMAXSD_FIRST 5167 +VPMAXSD_LAST 5176 +VPMAXSQ_FIRST 5177 +VPMAXSQ_LAST 5182 +VPMAXSW_FIRST 5183 +VPMAXSW_LAST 5192 +VPMAXUB_FIRST 5193 +VPMAXUB_LAST 5202 +VPMAXUD_FIRST 5203 +VPMAXUD_LAST 5212 +VPMAXUQ_FIRST 5213 +VPMAXUQ_LAST 5218 +VPMAXUW_FIRST 5219 +VPMAXUW_LAST 5228 +VPMINSB_FIRST 5229 +VPMINSB_LAST 5238 +VPMINSD_FIRST 5239 +VPMINSD_LAST 5248 +VPMINSQ_FIRST 5249 +VPMINSQ_LAST 5254 +VPMINSW_FIRST 5255 +VPMINSW_LAST 5264 +VPMINUB_FIRST 5265 +VPMINUB_LAST 5274 +VPMINUD_FIRST 5275 +VPMINUD_LAST 5284 +VPMINUQ_FIRST 5285 +VPMINUQ_LAST 5290 +VPMINUW_FIRST 5291 +VPMINUW_LAST 5300 +VPMOVB2M_FIRST 5301 +VPMOVB2M_LAST 5303 +VPMOVD2M_FIRST 5304 +VPMOVD2M_LAST 5306 +VPMOVDB_FIRST 5307 +VPMOVDB_LAST 5312 +VPMOVDW_FIRST 5313 +VPMOVDW_LAST 5318 +VPMOVM2B_FIRST 5319 +VPMOVM2B_LAST 5321 +VPMOVM2D_FIRST 5322 +VPMOVM2D_LAST 5324 +VPMOVM2Q_FIRST 5325 +VPMOVM2Q_LAST 5327 +VPMOVM2W_FIRST 5328 +VPMOVM2W_LAST 5330 +VPMOVMSKB_FIRST 5331 +VPMOVMSKB_LAST 5332 +VPMOVQ2M_FIRST 5333 +VPMOVQ2M_LAST 5335 +VPMOVQB_FIRST 5336 +VPMOVQB_LAST 5341 +VPMOVQD_FIRST 5342 +VPMOVQD_LAST 5347 +VPMOVQW_FIRST 5348 +VPMOVQW_LAST 5353 +VPMOVSDB_FIRST 5354 +VPMOVSDB_LAST 5359 +VPMOVSDW_FIRST 5360 +VPMOVSDW_LAST 5365 +VPMOVSQB_FIRST 5366 +VPMOVSQB_LAST 5371 +VPMOVSQD_FIRST 5372 +VPMOVSQD_LAST 5377 +VPMOVSQW_FIRST 5378 +VPMOVSQW_LAST 5383 +VPMOVSWB_FIRST 5384 +VPMOVSWB_LAST 5389 +VPMOVSXBD_FIRST 5390 +VPMOVSXBD_LAST 5399 +VPMOVSXBQ_FIRST 5400 +VPMOVSXBQ_LAST 5409 +VPMOVSXBW_FIRST 5410 +VPMOVSXBW_LAST 5419 +VPMOVSXDQ_FIRST 5420 +VPMOVSXDQ_LAST 5429 +VPMOVSXWD_FIRST 5430 +VPMOVSXWD_LAST 5439 +VPMOVSXWQ_FIRST 5440 +VPMOVSXWQ_LAST 5449 +VPMOVUSDB_FIRST 5450 +VPMOVUSDB_LAST 5455 +VPMOVUSDW_FIRST 5456 +VPMOVUSDW_LAST 5461 +VPMOVUSQB_FIRST 5462 +VPMOVUSQB_LAST 5467 +VPMOVUSQD_FIRST 5468 +VPMOVUSQD_LAST 5473 +VPMOVUSQW_FIRST 5474 +VPMOVUSQW_LAST 5479 +VPMOVUSWB_FIRST 5480 +VPMOVUSWB_LAST 5485 +VPMOVW2M_FIRST 5486 +VPMOVW2M_LAST 5488 +VPMOVWB_FIRST 5489 +VPMOVWB_LAST 5494 +VPMOVZXBD_FIRST 5495 +VPMOVZXBD_LAST 5504 +VPMOVZXBQ_FIRST 5505 +VPMOVZXBQ_LAST 5514 +VPMOVZXBW_FIRST 5515 +VPMOVZXBW_LAST 5524 +VPMOVZXDQ_FIRST 5525 +VPMOVZXDQ_LAST 5534 +VPMOVZXWD_FIRST 5535 +VPMOVZXWD_LAST 5544 +VPMOVZXWQ_FIRST 5545 +VPMOVZXWQ_LAST 5554 +VPMULDQ_FIRST 5555 +VPMULDQ_LAST 5564 +VPMULHRSW_FIRST 5565 +VPMULHRSW_LAST 5574 +VPMULHUW_FIRST 5575 +VPMULHUW_LAST 5584 +VPMULHW_FIRST 5585 +VPMULHW_LAST 5594 +VPMULLD_FIRST 5595 +VPMULLD_LAST 5604 +VPMULLQ_FIRST 5605 +VPMULLQ_LAST 5610 +VPMULLW_FIRST 5611 +VPMULLW_LAST 5620 +VPMULTISHIFTQB_FIRST 5621 +VPMULTISHIFTQB_LAST 5626 +VPMULUDQ_FIRST 5627 +VPMULUDQ_LAST 5636 +VPOPCNTB_FIRST 5637 +VPOPCNTB_LAST 5642 +VPOPCNTD_FIRST 5643 +VPOPCNTD_LAST 5648 +VPOPCNTQ_FIRST 5649 +VPOPCNTQ_LAST 5654 +VPOPCNTW_FIRST 5655 +VPOPCNTW_LAST 5660 +VPOR_FIRST 5661 +VPOR_LAST 5664 +VPORD_FIRST 5665 +VPORD_LAST 5670 +VPORQ_FIRST 5671 +VPORQ_LAST 5676 +VPPERM_FIRST 5677 +VPPERM_LAST 5679 +VPROLD_FIRST 5680 +VPROLD_LAST 5685 +VPROLQ_FIRST 5686 +VPROLQ_LAST 5691 +VPROLVD_FIRST 5692 +VPROLVD_LAST 5697 +VPROLVQ_FIRST 5698 +VPROLVQ_LAST 5703 +VPRORD_FIRST 5704 +VPRORD_LAST 5709 +VPRORQ_FIRST 5710 +VPRORQ_LAST 5715 +VPRORVD_FIRST 5716 +VPRORVD_LAST 5721 +VPRORVQ_FIRST 5722 +VPRORVQ_LAST 5727 +VPROTB_FIRST 5728 +VPROTB_LAST 5732 +VPROTD_FIRST 5733 +VPROTD_LAST 5737 +VPROTQ_FIRST 5738 +VPROTQ_LAST 5742 +VPROTW_FIRST 5743 +VPROTW_LAST 5747 +VPSADBW_FIRST 5748 +VPSADBW_LAST 5757 +VPSCATTERDD_FIRST 5758 +VPSCATTERDD_LAST 5760 +VPSCATTERDQ_FIRST 5761 +VPSCATTERDQ_LAST 5763 +VPSCATTERQD_FIRST 5764 +VPSCATTERQD_LAST 5766 +VPSCATTERQQ_FIRST 5767 +VPSCATTERQQ_LAST 5769 +VPSHAB_FIRST 5770 +VPSHAB_LAST 5772 +VPSHAD_FIRST 5773 +VPSHAD_LAST 5775 +VPSHAQ_FIRST 5776 +VPSHAQ_LAST 5778 +VPSHAW_FIRST 5779 +VPSHAW_LAST 5781 +VPSHLB_FIRST 5782 +VPSHLB_LAST 5784 +VPSHLD_FIRST 5785 +VPSHLD_LAST 5787 +VPSHLDD_FIRST 5788 +VPSHLDD_LAST 5793 +VPSHLDQ_FIRST 5794 +VPSHLDQ_LAST 5799 +VPSHLDVD_FIRST 5800 +VPSHLDVD_LAST 5805 +VPSHLDVQ_FIRST 5806 +VPSHLDVQ_LAST 5811 +VPSHLDVW_FIRST 5812 +VPSHLDVW_LAST 5817 +VPSHLDW_FIRST 5818 +VPSHLDW_LAST 5823 +VPSHLQ_FIRST 5824 +VPSHLQ_LAST 5826 +VPSHLW_FIRST 5827 +VPSHLW_LAST 5829 +VPSHRDD_FIRST 5830 +VPSHRDD_LAST 5835 +VPSHRDQ_FIRST 5836 +VPSHRDQ_LAST 5841 +VPSHRDVD_FIRST 5842 +VPSHRDVD_LAST 5847 +VPSHRDVQ_FIRST 5848 +VPSHRDVQ_LAST 5853 +VPSHRDVW_FIRST 5854 +VPSHRDVW_LAST 5859 +VPSHRDW_FIRST 5860 +VPSHRDW_LAST 5865 +VPSHUFB_FIRST 5866 +VPSHUFB_LAST 5875 +VPSHUFBITQMB_FIRST 5876 +VPSHUFBITQMB_LAST 5881 +VPSHUFD_FIRST 5882 +VPSHUFD_LAST 5891 +VPSHUFHW_FIRST 5892 +VPSHUFHW_LAST 5901 +VPSHUFLW_FIRST 5902 +VPSHUFLW_LAST 5911 +VPSIGNB_FIRST 5912 +VPSIGNB_LAST 5915 +VPSIGND_FIRST 5916 +VPSIGND_LAST 5919 +VPSIGNW_FIRST 5920 +VPSIGNW_LAST 5923 +VPSLLD_FIRST 5924 +VPSLLD_LAST 5941 +VPSLLDQ_FIRST 5942 +VPSLLDQ_LAST 5949 +VPSLLQ_FIRST 5950 +VPSLLQ_LAST 5967 +VPSLLVD_FIRST 5968 +VPSLLVD_LAST 5977 +VPSLLVQ_FIRST 5978 +VPSLLVQ_LAST 5987 +VPSLLVW_FIRST 5988 +VPSLLVW_LAST 5993 +VPSLLW_FIRST 5994 +VPSLLW_LAST 6011 +VPSRAD_FIRST 6012 +VPSRAD_LAST 6029 +VPSRAQ_FIRST 6030 +VPSRAQ_LAST 6041 +VPSRAVD_FIRST 6042 +VPSRAVD_LAST 6051 +VPSRAVQ_FIRST 6052 +VPSRAVQ_LAST 6057 +VPSRAVW_FIRST 6058 +VPSRAVW_LAST 6063 +VPSRAW_FIRST 6064 +VPSRAW_LAST 6081 +VPSRLD_FIRST 6082 +VPSRLD_LAST 6099 +VPSRLDQ_FIRST 6100 +VPSRLDQ_LAST 6107 +VPSRLQ_FIRST 6108 +VPSRLQ_LAST 6125 +VPSRLVD_FIRST 6126 +VPSRLVD_LAST 6135 +VPSRLVQ_FIRST 6136 +VPSRLVQ_LAST 6145 +VPSRLVW_FIRST 6146 +VPSRLVW_LAST 6151 +VPSRLW_FIRST 6152 +VPSRLW_LAST 6169 +VPSUBB_FIRST 6170 +VPSUBB_LAST 6179 +VPSUBD_FIRST 6180 +VPSUBD_LAST 6189 +VPSUBQ_FIRST 6190 +VPSUBQ_LAST 6199 +VPSUBSB_FIRST 6200 +VPSUBSB_LAST 6209 +VPSUBSW_FIRST 6210 +VPSUBSW_LAST 6219 +VPSUBUSB_FIRST 6220 +VPSUBUSB_LAST 6229 +VPSUBUSW_FIRST 6230 +VPSUBUSW_LAST 6239 +VPSUBW_FIRST 6240 +VPSUBW_LAST 6249 +VPTERNLOGD_FIRST 6250 +VPTERNLOGD_LAST 6255 +VPTERNLOGQ_FIRST 6256 +VPTERNLOGQ_LAST 6261 +VPTEST_FIRST 6262 +VPTEST_LAST 6265 +VPTESTMB_FIRST 6266 +VPTESTMB_LAST 6271 +VPTESTMD_FIRST 6272 +VPTESTMD_LAST 6277 +VPTESTMQ_FIRST 6278 +VPTESTMQ_LAST 6283 +VPTESTMW_FIRST 6284 +VPTESTMW_LAST 6289 +VPTESTNMB_FIRST 6290 +VPTESTNMB_LAST 6295 +VPTESTNMD_FIRST 6296 +VPTESTNMD_LAST 6301 +VPTESTNMQ_FIRST 6302 +VPTESTNMQ_LAST 6307 +VPTESTNMW_FIRST 6308 +VPTESTNMW_LAST 6313 +VPUNPCKHBW_FIRST 6314 +VPUNPCKHBW_LAST 6323 +VPUNPCKHDQ_FIRST 6324 +VPUNPCKHDQ_LAST 6333 +VPUNPCKHQDQ_FIRST 6334 +VPUNPCKHQDQ_LAST 6343 +VPUNPCKHWD_FIRST 6344 +VPUNPCKHWD_LAST 6353 +VPUNPCKLBW_FIRST 6354 +VPUNPCKLBW_LAST 6363 +VPUNPCKLDQ_FIRST 6364 +VPUNPCKLDQ_LAST 6373 +VPUNPCKLQDQ_FIRST 6374 +VPUNPCKLQDQ_LAST 6383 +VPUNPCKLWD_FIRST 6384 +VPUNPCKLWD_LAST 6393 +VPXOR_FIRST 6394 +VPXOR_LAST 6397 +VPXORD_FIRST 6398 +VPXORD_LAST 6403 +VPXORQ_FIRST 6404 +VPXORQ_LAST 6409 +VRANGEPD_FIRST 6410 +VRANGEPD_LAST 6415 +VRANGEPS_FIRST 6416 +VRANGEPS_LAST 6421 +VRANGESD_FIRST 6422 +VRANGESD_LAST 6423 +VRANGESS_FIRST 6424 +VRANGESS_LAST 6425 +VRCP14PD_FIRST 6426 +VRCP14PD_LAST 6431 +VRCP14PS_FIRST 6432 +VRCP14PS_LAST 6437 +VRCP14SD_FIRST 6438 +VRCP14SD_LAST 6439 +VRCP14SS_FIRST 6440 +VRCP14SS_LAST 6441 +VRCP28PD_FIRST 6442 +VRCP28PD_LAST 6443 +VRCP28PS_FIRST 6444 +VRCP28PS_LAST 6445 +VRCP28SD_FIRST 6446 +VRCP28SD_LAST 6447 +VRCP28SS_FIRST 6448 +VRCP28SS_LAST 6449 +VRCPPH_FIRST 6450 +VRCPPH_LAST 6455 +VRCPPS_FIRST 6456 +VRCPPS_LAST 6459 +VRCPSH_FIRST 6460 +VRCPSH_LAST 6461 +VRCPSS_FIRST 6462 +VRCPSS_LAST 6463 +VREDUCEPD_FIRST 6464 +VREDUCEPD_LAST 6469 +VREDUCEPH_FIRST 6470 +VREDUCEPH_LAST 6475 +VREDUCEPS_FIRST 6476 +VREDUCEPS_LAST 6481 +VREDUCESD_FIRST 6482 +VREDUCESD_LAST 6483 +VREDUCESH_FIRST 6484 +VREDUCESH_LAST 6485 +VREDUCESS_FIRST 6486 +VREDUCESS_LAST 6487 +VRNDSCALEPD_FIRST 6488 +VRNDSCALEPD_LAST 6493 +VRNDSCALEPH_FIRST 6494 +VRNDSCALEPH_LAST 6499 +VRNDSCALEPS_FIRST 6500 +VRNDSCALEPS_LAST 6505 +VRNDSCALESD_FIRST 6506 +VRNDSCALESD_LAST 6507 +VRNDSCALESH_FIRST 6508 +VRNDSCALESH_LAST 6509 +VRNDSCALESS_FIRST 6510 +VRNDSCALESS_LAST 6511 +VROUNDPD_FIRST 6512 +VROUNDPD_LAST 6515 +VROUNDPS_FIRST 6516 +VROUNDPS_LAST 6519 +VROUNDSD_FIRST 6520 +VROUNDSD_LAST 6521 +VROUNDSS_FIRST 6522 +VROUNDSS_LAST 6523 +VRSQRT14PD_FIRST 6524 +VRSQRT14PD_LAST 6529 +VRSQRT14PS_FIRST 6530 +VRSQRT14PS_LAST 6535 +VRSQRT14SD_FIRST 6536 +VRSQRT14SD_LAST 6537 +VRSQRT14SS_FIRST 6538 +VRSQRT14SS_LAST 6539 +VRSQRT28PD_FIRST 6540 +VRSQRT28PD_LAST 6541 +VRSQRT28PS_FIRST 6542 +VRSQRT28PS_LAST 6543 +VRSQRT28SD_FIRST 6544 +VRSQRT28SD_LAST 6545 +VRSQRT28SS_FIRST 6546 +VRSQRT28SS_LAST 6547 +VRSQRTPH_FIRST 6548 +VRSQRTPH_LAST 6553 +VRSQRTPS_FIRST 6554 +VRSQRTPS_LAST 6557 +VRSQRTSH_FIRST 6558 +VRSQRTSH_LAST 6559 +VRSQRTSS_FIRST 6560 +VRSQRTSS_LAST 6561 +VSCALEFPD_FIRST 6562 +VSCALEFPD_LAST 6567 +VSCALEFPH_FIRST 6568 +VSCALEFPH_LAST 6573 +VSCALEFPS_FIRST 6574 +VSCALEFPS_LAST 6579 +VSCALEFSD_FIRST 6580 +VSCALEFSD_LAST 6581 +VSCALEFSH_FIRST 6582 +VSCALEFSH_LAST 6583 +VSCALEFSS_FIRST 6584 +VSCALEFSS_LAST 6585 +VSCATTERDPD_FIRST 6586 +VSCATTERDPD_LAST 6588 +VSCATTERDPS_FIRST 6589 +VSCATTERDPS_LAST 6591 +VSCATTERPF0DPD_FIRST 6592 +VSCATTERPF0DPD_LAST 6592 +VSCATTERPF0DPS_FIRST 6593 +VSCATTERPF0DPS_LAST 6593 +VSCATTERPF0QPD_FIRST 6594 +VSCATTERPF0QPD_LAST 6594 +VSCATTERPF0QPS_FIRST 6595 +VSCATTERPF0QPS_LAST 6595 +VSCATTERPF1DPD_FIRST 6596 +VSCATTERPF1DPD_LAST 6596 +VSCATTERPF1DPS_FIRST 6597 +VSCATTERPF1DPS_LAST 6597 +VSCATTERPF1QPD_FIRST 6598 +VSCATTERPF1QPD_LAST 6598 +VSCATTERPF1QPS_FIRST 6599 +VSCATTERPF1QPS_LAST 6599 +VSCATTERQPD_FIRST 6600 +VSCATTERQPD_LAST 6602 +VSCATTERQPS_FIRST 6603 +VSCATTERQPS_LAST 6605 +VSHUFF32X4_FIRST 6606 +VSHUFF32X4_LAST 6609 +VSHUFF64X2_FIRST 6610 +VSHUFF64X2_LAST 6613 +VSHUFI32X4_FIRST 6614 +VSHUFI32X4_LAST 6617 +VSHUFI64X2_FIRST 6618 +VSHUFI64X2_LAST 6621 +VSHUFPD_FIRST 6622 +VSHUFPD_LAST 6631 +VSHUFPS_FIRST 6632 +VSHUFPS_LAST 6641 +VSQRTPD_FIRST 6642 +VSQRTPD_LAST 6651 +VSQRTPH_FIRST 6652 +VSQRTPH_LAST 6657 +VSQRTPS_FIRST 6658 +VSQRTPS_LAST 6667 +VSQRTSD_FIRST 6668 +VSQRTSD_LAST 6671 +VSQRTSH_FIRST 6672 +VSQRTSH_LAST 6673 +VSQRTSS_FIRST 6674 +VSQRTSS_LAST 6677 +VSTMXCSR_FIRST 6678 +VSTMXCSR_LAST 6678 +VSUBPD_FIRST 6679 +VSUBPD_LAST 6688 +VSUBPH_FIRST 6689 +VSUBPH_LAST 6694 +VSUBPS_FIRST 6695 +VSUBPS_LAST 6704 +VSUBSD_FIRST 6705 +VSUBSD_LAST 6708 +VSUBSH_FIRST 6709 +VSUBSH_LAST 6710 +VSUBSS_FIRST 6711 +VSUBSS_LAST 6714 +VTESTPD_FIRST 6715 +VTESTPD_LAST 6718 +VTESTPS_FIRST 6719 +VTESTPS_LAST 6722 +VUCOMISD_FIRST 6723 +VUCOMISD_LAST 6726 +VUCOMISH_FIRST 6727 +VUCOMISH_LAST 6728 +VUCOMISS_FIRST 6729 +VUCOMISS_LAST 6732 +VUNPCKHPD_FIRST 6733 +VUNPCKHPD_LAST 6742 +VUNPCKHPS_FIRST 6743 +VUNPCKHPS_LAST 6752 +VUNPCKLPD_FIRST 6753 +VUNPCKLPD_LAST 6762 +VUNPCKLPS_FIRST 6763 +VUNPCKLPS_LAST 6772 +VXORPD_FIRST 6773 +VXORPD_LAST 6782 +VXORPS_FIRST 6783 +VXORPS_LAST 6792 +VZEROALL_FIRST 6793 +VZEROALL_LAST 6793 +VZEROUPPER_FIRST 6794 +VZEROUPPER_LAST 6794 +WBINVD_FIRST 6795 +WBINVD_LAST 6795 +WBNOINVD_FIRST 6796 +WBNOINVD_LAST 6796 +WRFSBASE_FIRST 6797 +WRFSBASE_LAST 6797 +WRGSBASE_FIRST 6798 +WRGSBASE_LAST 6798 +WRMSR_FIRST 6799 +WRMSR_LAST 6799 +WRPKRU_FIRST 6800 +WRPKRU_LAST 6800 +WRSSD_FIRST 6801 +WRSSD_LAST 6801 +WRSSQ_FIRST 6802 +WRSSQ_LAST 6802 +WRUSSD_FIRST 6803 +WRUSSD_LAST 6803 +WRUSSQ_FIRST 6804 +WRUSSQ_LAST 6804 +XABORT_FIRST 6805 +XABORT_LAST 6805 +XADD_FIRST 6806 +XADD_LAST 6809 +XADD_LOCK_FIRST 6810 +XADD_LOCK_LAST 6811 +XBEGIN_FIRST 6812 +XBEGIN_LAST 6812 +XCHG_FIRST 6813 +XCHG_LAST 6817 +XEND_FIRST 6818 +XEND_LAST 6818 +XGETBV_FIRST 6819 +XGETBV_LAST 6819 +XLAT_FIRST 6820 +XLAT_LAST 6820 +XOR_FIRST 6821 +XOR_LAST 6838 +XORPD_FIRST 6839 +XORPD_LAST 6840 +XORPS_FIRST 6841 +XORPS_LAST 6842 +XOR_LOCK_FIRST 6843 +XOR_LOCK_LAST 6848 +XRESLDTRK_FIRST 6849 +XRESLDTRK_LAST 6849 +XRSTOR_FIRST 6850 +XRSTOR_LAST 6850 +XRSTOR64_FIRST 6851 +XRSTOR64_LAST 6851 +XRSTORS_FIRST 6852 +XRSTORS_LAST 6852 +XRSTORS64_FIRST 6853 +XRSTORS64_LAST 6853 +XSAVE_FIRST 6854 +XSAVE_LAST 6854 +XSAVE64_FIRST 6855 +XSAVE64_LAST 6855 +XSAVEC_FIRST 6856 +XSAVEC_LAST 6856 +XSAVEC64_FIRST 6857 +XSAVEC64_LAST 6857 +XSAVEOPT_FIRST 6858 +XSAVEOPT_LAST 6858 +XSAVEOPT64_FIRST 6859 +XSAVEOPT64_LAST 6859 +XSAVES_FIRST 6860 +XSAVES_LAST 6860 +XSAVES64_FIRST 6861 +XSAVES64_LAST 6861 +XSETBV_FIRST 6862 +XSETBV_LAST 6862 +XSTORE_FIRST 6863 +XSTORE_LAST 6863 +XSUSLDTRK_FIRST 6864 +XSUSLDTRK_LAST 6864 +XTEST_FIRST 6865 +XTEST_LAST 6865 diff --git a/CodeVirtualizer/build/obj/xed-ild-disp-l3.c b/CodeVirtualizer/build/obj/xed-ild-disp-l3.c new file mode 100644 index 0000000..20724c8 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-ild-disp-l3.c @@ -0,0 +1,48 @@ +/// @file xed-ild-disp-l3.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +/*Array declaration*/ +xed_bits_t xed_lookup_BRDISPz_BRDISP_WIDTH[4]; + +/*Array initialization*/ +void xed_lookup_function_init_BRDISPz_BRDISP_WIDTH(void) +{ +xed_lookup_BRDISPz_BRDISP_WIDTH[1]=0x10; +xed_lookup_BRDISPz_BRDISP_WIDTH[2]=0x20; +xed_lookup_BRDISPz_BRDISP_WIDTH[3]=0x20; +} +/*Array declaration*/ +xed_bits_t xed_lookup_MEMDISPv_DISP_WIDTH[4]; + +/*Array initialization*/ +void xed_lookup_function_init_MEMDISPv_DISP_WIDTH(void) +{ +xed_lookup_MEMDISPv_DISP_WIDTH[1]=0x10; +xed_lookup_MEMDISPv_DISP_WIDTH[2]=0x20; +xed_lookup_MEMDISPv_DISP_WIDTH[3]=0x40; +} +void xed_ild_disp_l3_init(void) +{ +xed_lookup_function_init_BRDISPz_BRDISP_WIDTH(); +xed_lookup_function_init_MEMDISPv_DISP_WIDTH(); +} diff --git a/CodeVirtualizer/build/obj/xed-ild-easz.c b/CodeVirtualizer/build/obj/xed-ild-easz.c new file mode 100644 index 0000000..6abba44 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-ild-easz.c @@ -0,0 +1,40 @@ +/// @file xed-ild-easz.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +/*Array declaration*/ +xed_bits_t xed_lookup_ASZ_NONTERM_EASZ[3][2]; + +/*Array initialization*/ +void xed_lookup_function_init_ASZ_NONTERM_EASZ(void) +{ +xed_lookup_ASZ_NONTERM_EASZ[0][0]=0x1; +xed_lookup_ASZ_NONTERM_EASZ[0][1]=0x2; +xed_lookup_ASZ_NONTERM_EASZ[1][0]=0x2; +xed_lookup_ASZ_NONTERM_EASZ[1][1]=0x1; +xed_lookup_ASZ_NONTERM_EASZ[2][0]=0x3; +xed_lookup_ASZ_NONTERM_EASZ[2][1]=0x2; +} +void xed_ild_easz_init(void) +{ +xed_lookup_function_init_ASZ_NONTERM_EASZ(); +} diff --git a/CodeVirtualizer/build/obj/xed-ild-enum.c b/CodeVirtualizer/build/obj/xed-ild-enum.c new file mode 100644 index 0000000..bcd0cf0 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-ild-enum.c @@ -0,0 +1,95 @@ +/// @file xed-ild-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-ild-enum.h" + +typedef struct { + const char* name; + xed_ild_map_enum_t value; +} name_table_xed_ild_map_enum_t; +static const name_table_xed_ild_map_enum_t name_array_xed_ild_map_enum_t[] = { +{"AMD_3DNOW", XED_ILD_AMD_3DNOW}, +{"AMD_XOP8", XED_ILD_AMD_XOP8}, +{"AMD_XOP9", XED_ILD_AMD_XOP9}, +{"AMD_XOPA", XED_ILD_AMD_XOPA}, +{"EVEX_MAP1", XED_ILD_EVEX_MAP1}, +{"EVEX_MAP2", XED_ILD_EVEX_MAP2}, +{"EVEX_MAP3", XED_ILD_EVEX_MAP3}, +{"EVEX_MAP5", XED_ILD_EVEX_MAP5}, +{"EVEX_MAP6", XED_ILD_EVEX_MAP6}, +{"LEGACY_MAP0", XED_ILD_LEGACY_MAP0}, +{"LEGACY_MAP1", XED_ILD_LEGACY_MAP1}, +{"LEGACY_MAP2", XED_ILD_LEGACY_MAP2}, +{"LEGACY_MAP3", XED_ILD_LEGACY_MAP3}, +{"VEX_MAP1", XED_ILD_VEX_MAP1}, +{"VEX_MAP2", XED_ILD_VEX_MAP2}, +{"VEX_MAP3", XED_ILD_VEX_MAP3}, +{"MAP_INVALID", XED_ILD_MAP_INVALID}, +{"LAST", XED_ILD_LAST}, +{0, XED_ILD_LAST}, +}; + + +xed_ild_map_enum_t str2xed_ild_map_enum_t(const char* s) +{ + const name_table_xed_ild_map_enum_t* p = name_array_xed_ild_map_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_ILD_LAST; +} + + +const char* xed_ild_map_enum_t2str(const xed_ild_map_enum_t p) +{ + const name_table_xed_ild_map_enum_t* q = name_array_xed_ild_map_enum_t; + while( q->name ) { + if (q->value == p) { + return q->name; + } + q++; + } + return "???"; +} + +xed_ild_map_enum_t xed_ild_map_enum_t_last(void) { + return XED_ILD_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_ILD_AMD_3DNOW: + case XED_ILD_AMD_XOP8: + case XED_ILD_AMD_XOP9: + case XED_ILD_AMD_XOPA: + case XED_ILD_EVEX_MAP1: + case XED_ILD_EVEX_MAP2: + case XED_ILD_EVEX_MAP3: + case XED_ILD_EVEX_MAP5: + case XED_ILD_EVEX_MAP6: + case XED_ILD_LEGACY_MAP0: + case XED_ILD_LEGACY_MAP1: + case XED_ILD_LEGACY_MAP2: + case XED_ILD_LEGACY_MAP3: + case XED_ILD_VEX_MAP1: + case XED_ILD_VEX_MAP2: + case XED_ILD_VEX_MAP3: + case XED_ILD_MAP_INVALID: + case XED_ILD_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-ild-enum.h b/CodeVirtualizer/build/obj/xed-ild-enum.h new file mode 100644 index 0000000..1a8cd42 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-ild-enum.h @@ -0,0 +1,63 @@ +/// @file xed-ild-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ILD_ENUM_H) +# define XED_ILD_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ILD_AMD_3DNOW_DEFINED 1 +#define XED_ILD_AMD_XOP8_DEFINED 1 +#define XED_ILD_AMD_XOP9_DEFINED 1 +#define XED_ILD_AMD_XOPA_DEFINED 1 +#define XED_ILD_EVEX_MAP1_DEFINED 1 +#define XED_ILD_EVEX_MAP2_DEFINED 1 +#define XED_ILD_EVEX_MAP3_DEFINED 1 +#define XED_ILD_EVEX_MAP5_DEFINED 1 +#define XED_ILD_EVEX_MAP6_DEFINED 1 +#define XED_ILD_LEGACY_MAP0_DEFINED 1 +#define XED_ILD_LEGACY_MAP1_DEFINED 1 +#define XED_ILD_LEGACY_MAP2_DEFINED 1 +#define XED_ILD_LEGACY_MAP3_DEFINED 1 +#define XED_ILD_VEX_MAP1_DEFINED 1 +#define XED_ILD_VEX_MAP2_DEFINED 1 +#define XED_ILD_VEX_MAP3_DEFINED 1 +#define XED_ILD_MAP_INVALID_DEFINED 1 +#define XED_ILD_LAST_DEFINED 1 +typedef enum { + XED_ILD_AMD_3DNOW=4, + XED_ILD_AMD_XOP8=8, + XED_ILD_AMD_XOP9=9, + XED_ILD_AMD_XOPA=10, + XED_ILD_EVEX_MAP1=1, + XED_ILD_EVEX_MAP2=2, + XED_ILD_EVEX_MAP3=3, + XED_ILD_EVEX_MAP5=5, + XED_ILD_EVEX_MAP6=6, + XED_ILD_LEGACY_MAP0=0, + XED_ILD_LEGACY_MAP1=1, + XED_ILD_LEGACY_MAP2=2, + XED_ILD_LEGACY_MAP3=3, + XED_ILD_VEX_MAP1=1, + XED_ILD_VEX_MAP2=2, + XED_ILD_VEX_MAP3=3, + XED_ILD_MAP_INVALID, + XED_ILD_LAST +} xed_ild_map_enum_t; + +/// This converts strings to #xed_ild_map_enum_t types. +/// @param s A C-string. +/// @return #xed_ild_map_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_ild_map_enum_t str2xed_ild_map_enum_t(const char* s); +/// This converts strings to #xed_ild_map_enum_t types. +/// @param p An enumeration element of type xed_ild_map_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_ild_map_enum_t2str(const xed_ild_map_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_ild_map_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_ild_map_enum_t xed_ild_map_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-ild-eosz.c b/CodeVirtualizer/build/obj/xed-ild-eosz.c new file mode 100644 index 0000000..8c35c5f --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-ild-eosz.c @@ -0,0 +1,246 @@ +/// @file xed-ild-eosz.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[2][1][0]=0x1; +xed_lookup_OSZ_NONTERM_EOSZ[2][0][0]=0x2; +xed_lookup_OSZ_NONTERM_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_CR_WIDTH_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[0][0][0]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[0][0][1]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[1][1][0]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[1][1][1]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[2][1][0]=0x3; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[2][0][0]=0x3; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_CR_WIDTH_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_DF64_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_DF64_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_DF64_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[2][1][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[2][0][0]=0x3; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_DF64_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_DF64_FORCE64_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[2][1][0]=0x3; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[2][0][0]=0x3; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_DF64_FORCE64_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[2][1][0]=0x3; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[2][0][0]=0x3; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_FORCE64_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[2][1][0]=0x3; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[2][0][0]=0x3; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_FORCE64_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_IGNORE66_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[0][1][0]=0x1; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[0][1][1]=0x1; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[1][1][0]=0x2; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[1][1][1]=0x2; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[2][1][0]=0x2; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[2][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_IGNORE66_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_IMMUNE66_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[0][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[0][0][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[1][1][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[1][1][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[2][1][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[2][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_IMMUNE66_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_IMMUNE_REXW_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[1][1][0]=0x1; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[1][1][1]=0x1; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[2][1][0]=0x1; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[2][0][0]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[2][1][1]=0x2; +xed_lookup_OSZ_NONTERM_IMMUNE_REXW_EOSZ[2][0][1]=0x2; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_REFINING66_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[0][0][0]=0x1; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[0][0][1]=0x1; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[0][1][0]=0x1; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[0][1][1]=0x1; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[1][1][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[1][1][1]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[2][1][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[2][0][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_REFINING66_EOSZ[2][0][1]=0x3; +} +/*Array declaration*/ +xed_bits_t xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[3][2][2]; + +/*Array initialization*/ +void xed_lookup_function_init_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(void) +{ +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[0][0][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[0][0][1]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[0][1][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[0][1][1]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[1][1][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[1][1][1]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[1][0][0]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[1][0][1]=0x2; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[2][1][0]=0x3; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[2][0][0]=0x3; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[2][1][1]=0x3; +xed_lookup_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ[2][0][1]=0x3; +} +void xed_ild_eosz_init(void) +{ +xed_lookup_function_init_OSZ_NONTERM_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_CR_WIDTH_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_DF64_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_DF64_FORCE64_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_DF64_IMMUNE66_LOOP64_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_FORCE64_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_IGNORE66_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_IMMUNE66_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_IMMUNE_REXW_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_REFINING66_EOSZ(); +xed_lookup_function_init_OSZ_NONTERM_REFINING66_CR_WIDTH_EOSZ(); +} diff --git a/CodeVirtualizer/build/obj/xed-ild-imm-l3.c b/CodeVirtualizer/build/obj/xed-ild-imm-l3.c new file mode 100644 index 0000000..b3eb520 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-ild-imm-l3.c @@ -0,0 +1,48 @@ +/// @file xed-ild-imm-l3.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +/*Array declaration*/ +xed_bits_t xed_lookup_SIMMz_IMM_WIDTH[4]; + +/*Array initialization*/ +void xed_lookup_function_init_SIMMz_IMM_WIDTH(void) +{ +xed_lookup_SIMMz_IMM_WIDTH[1]=0x10; +xed_lookup_SIMMz_IMM_WIDTH[2]=0x20; +xed_lookup_SIMMz_IMM_WIDTH[3]=0x20; +} +/*Array declaration*/ +xed_bits_t xed_lookup_UIMMv_IMM_WIDTH[4]; + +/*Array initialization*/ +void xed_lookup_function_init_UIMMv_IMM_WIDTH(void) +{ +xed_lookup_UIMMv_IMM_WIDTH[1]=0x10; +xed_lookup_UIMMv_IMM_WIDTH[2]=0x20; +xed_lookup_UIMMv_IMM_WIDTH[3]=0x40; +} +void xed_ild_imm_l3_init(void) +{ +xed_lookup_function_init_SIMMz_IMM_WIDTH(); +xed_lookup_function_init_UIMMv_IMM_WIDTH(); +} diff --git a/CodeVirtualizer/build/obj/xed-init-inst-table-0.c b/CodeVirtualizer/build/obj/xed-init-inst-table-0.c new file mode 100644 index 0000000..57d4a8b --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-inst-table-0.c @@ -0,0 +1,26 @@ +/// @file xed-init-inst-table-0.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_init_inst_table_0(void) +{ +} diff --git a/CodeVirtualizer/build/obj/xed-init-inst-table-data.c b/CodeVirtualizer/build/obj/xed-init-inst-table-data.c new file mode 100644 index 0000000..f40b08c --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-inst-table-data.c @@ -0,0 +1,7640 @@ +/// @file xed-init-inst-table-data.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-inst-defs.h" +const xed_inst_t xed_inst_table[XED_MAX_INST_TABLE_NODES] = { +/* 0*/ XED_DEF_INST(XED_ICLASS_INVALID,XED_CATEGORY_INVALID,XED_EXTENSION_INVALID,3,XED_IFORM_INVALID,0,0,0,0,0,XED_EXCEPTION_INVALID), +/* 1*/ XED_DEF_INST(XED_ICLASS_FADD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FADD_ST0_MEMmem32real,59,3,1,0,1,XED_EXCEPTION_INVALID), +/* 2*/ XED_DEF_INST(XED_ICLASS_FADD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FADD_ST0_X87,62,3,1,0,1,XED_EXCEPTION_INVALID), +/* 3*/ XED_DEF_INST(XED_ICLASS_FADD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FADD_ST0_MEMm64real,65,3,1,0,1,XED_EXCEPTION_INVALID), +/* 4*/ XED_DEF_INST(XED_ICLASS_FADD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FADD_X87_ST0,68,3,1,0,1,XED_EXCEPTION_INVALID), +/* 5*/ XED_DEF_INST(XED_ICLASS_FMUL,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FMUL_ST0_MEMmem32real,59,3,1,0,1,XED_EXCEPTION_INVALID), +/* 6*/ XED_DEF_INST(XED_ICLASS_FMUL,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FMUL_ST0_X87,62,3,1,0,1,XED_EXCEPTION_INVALID), +/* 7*/ XED_DEF_INST(XED_ICLASS_FMUL,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FMUL_ST0_MEMm64real,65,3,1,0,1,XED_EXCEPTION_INVALID), +/* 8*/ XED_DEF_INST(XED_ICLASS_FMUL,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FMUL_X87_ST0,68,3,1,0,1,XED_EXCEPTION_INVALID), +/* 9*/ XED_DEF_INST(XED_ICLASS_FCOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMP_ST0_MEMmem32real,71,4,2,0,1,XED_EXCEPTION_INVALID), +/* 10*/ XED_DEF_INST(XED_ICLASS_FCOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMP_ST0_X87,75,4,2,0,1,XED_EXCEPTION_INVALID), +/* 11*/ XED_DEF_INST(XED_ICLASS_FCOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMP_ST0_X87_DCD1,75,4,2,0,1,XED_EXCEPTION_INVALID), +/* 12*/ XED_DEF_INST(XED_ICLASS_FCOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMP_ST0_X87_DED0,75,4,2,0,1,XED_EXCEPTION_INVALID), +/* 13*/ XED_DEF_INST(XED_ICLASS_FCOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMP_ST0_MEMm64real,79,4,2,0,1,XED_EXCEPTION_INVALID), +/* 14*/ XED_DEF_INST(XED_ICLASS_FSUB,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUB_ST0_MEMmem32real,59,3,1,0,1,XED_EXCEPTION_INVALID), +/* 15*/ XED_DEF_INST(XED_ICLASS_FSUB,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUB_ST0_X87,62,3,1,0,1,XED_EXCEPTION_INVALID), +/* 16*/ XED_DEF_INST(XED_ICLASS_FSUB,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUB_ST0_MEMm64real,65,3,1,0,1,XED_EXCEPTION_INVALID), +/* 17*/ XED_DEF_INST(XED_ICLASS_FSUB,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUB_X87_ST0,68,3,1,0,1,XED_EXCEPTION_INVALID), +/* 18*/ XED_DEF_INST(XED_ICLASS_FSUBR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUBR_ST0_MEMmem32real,59,3,1,0,1,XED_EXCEPTION_INVALID), +/* 19*/ XED_DEF_INST(XED_ICLASS_FSUBR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUBR_ST0_X87,62,3,1,0,1,XED_EXCEPTION_INVALID), +/* 20*/ XED_DEF_INST(XED_ICLASS_FSUBR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUBR_ST0_MEMm64real,65,3,1,0,1,XED_EXCEPTION_INVALID), +/* 21*/ XED_DEF_INST(XED_ICLASS_FSUBR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUBR_X87_ST0,68,3,1,0,1,XED_EXCEPTION_INVALID), +/* 22*/ XED_DEF_INST(XED_ICLASS_FDIV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIV_ST0_MEMmem32real,59,3,1,0,1,XED_EXCEPTION_INVALID), +/* 23*/ XED_DEF_INST(XED_ICLASS_FDIV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIV_ST0_X87,62,3,1,0,1,XED_EXCEPTION_INVALID), +/* 24*/ XED_DEF_INST(XED_ICLASS_FDIV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIV_ST0_MEMm64real,65,3,1,0,1,XED_EXCEPTION_INVALID), +/* 25*/ XED_DEF_INST(XED_ICLASS_FDIV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIV_X87_ST0,68,3,1,0,1,XED_EXCEPTION_INVALID), +/* 26*/ XED_DEF_INST(XED_ICLASS_FDIVR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIVR_ST0_MEMmem32real,59,3,1,0,1,XED_EXCEPTION_INVALID), +/* 27*/ XED_DEF_INST(XED_ICLASS_FDIVR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIVR_ST0_X87,62,3,1,0,1,XED_EXCEPTION_INVALID), +/* 28*/ XED_DEF_INST(XED_ICLASS_FDIVR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIVR_ST0_MEMm64real,65,3,1,0,1,XED_EXCEPTION_INVALID), +/* 29*/ XED_DEF_INST(XED_ICLASS_FDIVR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIVR_X87_ST0,68,3,1,0,1,XED_EXCEPTION_INVALID), +/* 30*/ XED_DEF_INST(XED_ICLASS_FCOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOM_ST0_MEMmem32real,83,3,2,0,1,XED_EXCEPTION_INVALID), +/* 31*/ XED_DEF_INST(XED_ICLASS_FCOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOM_ST0_MEMm64real,86,3,2,0,1,XED_EXCEPTION_INVALID), +/* 32*/ XED_DEF_INST(XED_ICLASS_FCOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOM_ST0_X87,89,3,2,0,1,XED_EXCEPTION_INVALID), +/* 33*/ XED_DEF_INST(XED_ICLASS_FCOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOM_ST0_X87_DCD0,89,3,2,0,1,XED_EXCEPTION_INVALID), +/* 34*/ XED_DEF_INST(XED_ICLASS_FLD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLD_ST0_MEMmem32real,92,4,1,0,1,XED_EXCEPTION_INVALID), +/* 35*/ XED_DEF_INST(XED_ICLASS_FLD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLD_ST0_X87,96,4,1,0,1,XED_EXCEPTION_INVALID), +/* 36*/ XED_DEF_INST(XED_ICLASS_FLD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLD_ST0_MEMmem80real,100,4,1,0,1,XED_EXCEPTION_INVALID), +/* 37*/ XED_DEF_INST(XED_ICLASS_FLD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLD_ST0_MEMm64real,104,4,1,0,1,XED_EXCEPTION_INVALID), +/* 38*/ XED_DEF_INST(XED_ICLASS_FST,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FST_MEMmem32real_ST0,108,3,1,0,1,XED_EXCEPTION_INVALID), +/* 39*/ XED_DEF_INST(XED_ICLASS_FST,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FST_MEMm64real_ST0,111,3,1,0,1,XED_EXCEPTION_INVALID), +/* 40*/ XED_DEF_INST(XED_ICLASS_FST,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FST_X87_ST0,114,3,1,0,1,XED_EXCEPTION_INVALID), +/* 41*/ XED_DEF_INST(XED_ICLASS_FSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTP_MEMmem32real_ST0,117,4,1,0,1,XED_EXCEPTION_INVALID), +/* 42*/ XED_DEF_INST(XED_ICLASS_FSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTP_MEMmem80real_ST0,121,4,1,0,1,XED_EXCEPTION_INVALID), +/* 43*/ XED_DEF_INST(XED_ICLASS_FSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTP_MEMm64real_ST0,125,4,1,0,1,XED_EXCEPTION_INVALID), +/* 44*/ XED_DEF_INST(XED_ICLASS_FSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTP_X87_ST0,129,4,1,0,1,XED_EXCEPTION_INVALID), +/* 45*/ XED_DEF_INST(XED_ICLASS_FSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTP_X87_ST0_DFD0,129,4,1,0,1,XED_EXCEPTION_INVALID), +/* 46*/ XED_DEF_INST(XED_ICLASS_FSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTP_X87_ST0_DFD1,129,4,1,0,1,XED_EXCEPTION_INVALID), +/* 47*/ XED_DEF_INST(XED_ICLASS_FSTPNCE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSTPNCE_X87_ST0,129,4,1,0,1,XED_EXCEPTION_INVALID), +/* 48*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem14,133,2,2,0,2,XED_EXCEPTION_INVALID), +/* 49*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem14,133,2,2,0,2,XED_EXCEPTION_INVALID), +/* 50*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem14,133,2,2,0,2,XED_EXCEPTION_INVALID), +/* 51*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem28,135,2,2,0,2,XED_EXCEPTION_INVALID), +/* 52*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem28,135,2,2,0,2,XED_EXCEPTION_INVALID), +/* 53*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem28,135,2,2,0,2,XED_EXCEPTION_INVALID), +/* 54*/ XED_DEF_INST(XED_ICLASS_FLDENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDENV_MEMmem28,135,2,2,0,2,XED_EXCEPTION_INVALID), +/* 55*/ XED_DEF_INST(XED_ICLASS_FLDCW,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDCW_MEMmem16,137,3,3,0,2,XED_EXCEPTION_INVALID), +/* 56*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem14,140,2,3,0,3,XED_EXCEPTION_INVALID), +/* 57*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem14,140,2,3,0,3,XED_EXCEPTION_INVALID), +/* 58*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem14,140,2,3,0,3,XED_EXCEPTION_INVALID), +/* 59*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem28,142,2,3,0,3,XED_EXCEPTION_INVALID), +/* 60*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem28,142,2,3,0,3,XED_EXCEPTION_INVALID), +/* 61*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem28,142,2,3,0,3,XED_EXCEPTION_INVALID), +/* 62*/ XED_DEF_INST(XED_ICLASS_FNSTENV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTENV_MEMmem28,142,2,3,0,3,XED_EXCEPTION_INVALID), +/* 63*/ XED_DEF_INST(XED_ICLASS_FNSTCW,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTCW_MEMmem16,144,3,3,0,3,XED_EXCEPTION_INVALID), +/* 64*/ XED_DEF_INST(XED_ICLASS_FXCH,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FXCH_ST0_X87,147,3,1,0,1,XED_EXCEPTION_INVALID), +/* 65*/ XED_DEF_INST(XED_ICLASS_FXCH,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FXCH_ST0_X87_DFC1,147,3,1,0,1,XED_EXCEPTION_INVALID), +/* 66*/ XED_DEF_INST(XED_ICLASS_FXCH,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FXCH_ST0_X87_DDC1,147,3,1,0,1,XED_EXCEPTION_INVALID), +/* 67*/ XED_DEF_INST(XED_ICLASS_FNOP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNOP,0,0,0,0,4,XED_EXCEPTION_INVALID), +/* 68*/ XED_DEF_INST(XED_ICLASS_FCHS,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCHS,150,2,1,0,1,XED_EXCEPTION_INVALID), +/* 69*/ XED_DEF_INST(XED_ICLASS_FABS,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FABS,150,2,1,0,1,XED_EXCEPTION_INVALID), +/* 70*/ XED_DEF_INST(XED_ICLASS_FTST,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FTST,150,2,2,0,1,XED_EXCEPTION_INVALID), +/* 71*/ XED_DEF_INST(XED_ICLASS_FXAM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FXAM,150,2,2,0,1,XED_EXCEPTION_INVALID), +/* 72*/ XED_DEF_INST(XED_ICLASS_FLD1,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLD1,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 73*/ XED_DEF_INST(XED_ICLASS_FLDL2T,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDL2T,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 74*/ XED_DEF_INST(XED_ICLASS_FLDL2E,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDL2E,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 75*/ XED_DEF_INST(XED_ICLASS_FLDPI,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDPI,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 76*/ XED_DEF_INST(XED_ICLASS_FLDLG2,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDLG2,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 77*/ XED_DEF_INST(XED_ICLASS_FLDLN2,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDLN2,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 78*/ XED_DEF_INST(XED_ICLASS_FLDZ,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FLDZ,152,3,1,0,1,XED_EXCEPTION_INVALID), +/* 79*/ XED_DEF_INST(XED_ICLASS_F2XM1,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_F2XM1,150,2,1,0,1,XED_EXCEPTION_INVALID), +/* 80*/ XED_DEF_INST(XED_ICLASS_FYL2X,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FYL2X,155,4,1,0,1,XED_EXCEPTION_INVALID), +/* 81*/ XED_DEF_INST(XED_ICLASS_FPTAN,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FPTAN,159,3,4,0,1,XED_EXCEPTION_INVALID), +/* 82*/ XED_DEF_INST(XED_ICLASS_FPATAN,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FPATAN,155,4,1,0,1,XED_EXCEPTION_INVALID), +/* 83*/ XED_DEF_INST(XED_ICLASS_FXTRACT,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FXTRACT,159,3,1,0,1,XED_EXCEPTION_INVALID), +/* 84*/ XED_DEF_INST(XED_ICLASS_FPREM1,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FPREM1,162,3,2,0,1,XED_EXCEPTION_INVALID), +/* 85*/ XED_DEF_INST(XED_ICLASS_FDECSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDECSTP,165,1,1,0,2,XED_EXCEPTION_INVALID), +/* 86*/ XED_DEF_INST(XED_ICLASS_FINCSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FINCSTP,165,1,1,0,2,XED_EXCEPTION_INVALID), +/* 87*/ XED_DEF_INST(XED_ICLASS_FPREM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FPREM,162,3,2,0,1,XED_EXCEPTION_INVALID), +/* 88*/ XED_DEF_INST(XED_ICLASS_FYL2XP1,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FYL2XP1,155,4,1,0,1,XED_EXCEPTION_INVALID), +/* 89*/ XED_DEF_INST(XED_ICLASS_FSQRT,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSQRT,150,2,1,0,1,XED_EXCEPTION_INVALID), +/* 90*/ XED_DEF_INST(XED_ICLASS_FSINCOS,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSINCOS,159,3,4,0,1,XED_EXCEPTION_INVALID), +/* 91*/ XED_DEF_INST(XED_ICLASS_FRNDINT,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRNDINT,150,2,1,0,1,XED_EXCEPTION_INVALID), +/* 92*/ XED_DEF_INST(XED_ICLASS_FSCALE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSCALE,162,3,1,0,1,XED_EXCEPTION_INVALID), +/* 93*/ XED_DEF_INST(XED_ICLASS_FSIN,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSIN,150,2,4,0,1,XED_EXCEPTION_INVALID), +/* 94*/ XED_DEF_INST(XED_ICLASS_FCOS,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOS,150,2,4,0,1,XED_EXCEPTION_INVALID), +/* 95*/ XED_DEF_INST(XED_ICLASS_FIADD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIADD_ST0_MEMmem32int,166,3,1,0,1,XED_EXCEPTION_INVALID), +/* 96*/ XED_DEF_INST(XED_ICLASS_FIADD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIADD_ST0_MEMmem16int,169,3,1,0,1,XED_EXCEPTION_INVALID), +/* 97*/ XED_DEF_INST(XED_ICLASS_FIMUL,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIMUL_ST0_MEMmem32int,166,3,1,0,1,XED_EXCEPTION_INVALID), +/* 98*/ XED_DEF_INST(XED_ICLASS_FIMUL,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIMUL_ST0_MEMmem16int,169,3,1,0,1,XED_EXCEPTION_INVALID), +/* 99*/ XED_DEF_INST(XED_ICLASS_FICOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FICOM_ST0_MEMmem32int,172,3,2,0,1,XED_EXCEPTION_INVALID), +/* 100*/ XED_DEF_INST(XED_ICLASS_FICOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FICOM_ST0_MEMmem16int,175,3,2,0,1,XED_EXCEPTION_INVALID), +/* 101*/ XED_DEF_INST(XED_ICLASS_FICOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FICOMP_ST0_MEMmem32int,178,4,2,0,1,XED_EXCEPTION_INVALID), +/* 102*/ XED_DEF_INST(XED_ICLASS_FICOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FICOMP_ST0_MEMmem16int,182,4,2,0,1,XED_EXCEPTION_INVALID), +/* 103*/ XED_DEF_INST(XED_ICLASS_FISUB,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISUB_ST0_MEMmem32int,166,3,1,0,1,XED_EXCEPTION_INVALID), +/* 104*/ XED_DEF_INST(XED_ICLASS_FISUB,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISUB_ST0_MEMmem16int,169,3,1,0,1,XED_EXCEPTION_INVALID), +/* 105*/ XED_DEF_INST(XED_ICLASS_FISUBR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISUBR_ST0_MEMmem32int,166,3,1,0,1,XED_EXCEPTION_INVALID), +/* 106*/ XED_DEF_INST(XED_ICLASS_FISUBR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISUBR_ST0_MEMmem16int,169,3,1,0,1,XED_EXCEPTION_INVALID), +/* 107*/ XED_DEF_INST(XED_ICLASS_FIDIV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIDIV_ST0_MEMmem32int,166,3,1,0,1,XED_EXCEPTION_INVALID), +/* 108*/ XED_DEF_INST(XED_ICLASS_FIDIV,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIDIV_ST0_MEMmem16int,169,3,1,0,1,XED_EXCEPTION_INVALID), +/* 109*/ XED_DEF_INST(XED_ICLASS_FIDIVR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIDIVR_ST0_MEMmem32int,166,3,1,0,1,XED_EXCEPTION_INVALID), +/* 110*/ XED_DEF_INST(XED_ICLASS_FIDIVR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIDIVR_ST0_MEMmem16int,169,3,1,0,1,XED_EXCEPTION_INVALID), +/* 111*/ XED_DEF_INST(XED_ICLASS_FCMOVB,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVB_ST0_X87,186,4,5,0,1,XED_EXCEPTION_INVALID), +/* 112*/ XED_DEF_INST(XED_ICLASS_FCMOVE,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVE_ST0_X87,186,4,6,0,1,XED_EXCEPTION_INVALID), +/* 113*/ XED_DEF_INST(XED_ICLASS_FCMOVBE,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVBE_ST0_X87,186,4,7,0,1,XED_EXCEPTION_INVALID), +/* 114*/ XED_DEF_INST(XED_ICLASS_FCMOVU,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVU_ST0_X87,186,4,8,0,1,XED_EXCEPTION_INVALID), +/* 115*/ XED_DEF_INST(XED_ICLASS_FUCOMPP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FUCOMPP,190,4,2,0,1,XED_EXCEPTION_INVALID), +/* 116*/ XED_DEF_INST(XED_ICLASS_FILD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FILD_ST0_MEMmem32int,194,4,1,0,1,XED_EXCEPTION_INVALID), +/* 117*/ XED_DEF_INST(XED_ICLASS_FILD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FILD_ST0_MEMmem16int,198,4,1,0,1,XED_EXCEPTION_INVALID), +/* 118*/ XED_DEF_INST(XED_ICLASS_FILD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FILD_ST0_MEMm64int,202,4,1,0,1,XED_EXCEPTION_INVALID), +/* 119*/ XED_DEF_INST(XED_ICLASS_FISTTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_SSE3,3,XED_IFORM_FISTTP_MEMmem32int_ST0,206,4,1,0,1,XED_EXCEPTION_INVALID), +/* 120*/ XED_DEF_INST(XED_ICLASS_FISTTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_SSE3,3,XED_IFORM_FISTTP_MEMm64int_ST0,210,4,1,0,1,XED_EXCEPTION_INVALID), +/* 121*/ XED_DEF_INST(XED_ICLASS_FISTTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_SSE3,3,XED_IFORM_FISTTP_MEMmem16int_ST0,214,4,1,0,1,XED_EXCEPTION_INVALID), +/* 122*/ XED_DEF_INST(XED_ICLASS_FIST,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIST_MEMmem32int_ST0,218,3,1,0,1,XED_EXCEPTION_INVALID), +/* 123*/ XED_DEF_INST(XED_ICLASS_FIST,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FIST_MEMmem16int_ST0,221,3,1,0,1,XED_EXCEPTION_INVALID), +/* 124*/ XED_DEF_INST(XED_ICLASS_FISTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISTP_MEMmem32int_ST0,206,4,1,0,1,XED_EXCEPTION_INVALID), +/* 125*/ XED_DEF_INST(XED_ICLASS_FISTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISTP_MEMmem16int_ST0,214,4,1,0,1,XED_EXCEPTION_INVALID), +/* 126*/ XED_DEF_INST(XED_ICLASS_FISTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FISTP_MEMm64int_ST0,210,4,1,0,1,XED_EXCEPTION_INVALID), +/* 127*/ XED_DEF_INST(XED_ICLASS_FCMOVNB,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVNB_ST0_X87,186,4,5,0,1,XED_EXCEPTION_INVALID), +/* 128*/ XED_DEF_INST(XED_ICLASS_FCMOVNE,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVNE_ST0_X87,186,4,6,0,1,XED_EXCEPTION_INVALID), +/* 129*/ XED_DEF_INST(XED_ICLASS_FCMOVNBE,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVNBE_ST0_X87,186,4,7,0,1,XED_EXCEPTION_INVALID), +/* 130*/ XED_DEF_INST(XED_ICLASS_FCMOVNU,XED_CATEGORY_FCMOV,XED_EXTENSION_X87,3,XED_IFORM_FCMOVNU_ST0_X87,186,4,8,0,1,XED_EXCEPTION_INVALID), +/* 131*/ XED_DEF_INST(XED_ICLASS_FNCLEX,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNCLEX,224,1,3,0,3,XED_EXCEPTION_INVALID), +/* 132*/ XED_DEF_INST(XED_ICLASS_FNINIT,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNINIT,225,3,2,0,5,XED_EXCEPTION_INVALID), +/* 133*/ XED_DEF_INST(XED_ICLASS_FSETPM287_NOP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSETPM287_NOP,0,0,0,0,6,XED_EXCEPTION_INVALID), +/* 134*/ XED_DEF_INST(XED_ICLASS_FENI8087_NOP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FENI8087_NOP,0,0,0,0,6,XED_EXCEPTION_INVALID), +/* 135*/ XED_DEF_INST(XED_ICLASS_FDISI8087_NOP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDISI8087_NOP,0,0,0,0,6,XED_EXCEPTION_INVALID), +/* 136*/ XED_DEF_INST(XED_ICLASS_FUCOMI,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FUCOMI_ST0_X87,228,4,9,0,1,XED_EXCEPTION_INVALID), +/* 137*/ XED_DEF_INST(XED_ICLASS_FCOMI,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMI_ST0_X87,228,4,9,0,1,XED_EXCEPTION_INVALID), +/* 138*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem94,232,2,2,0,7,XED_EXCEPTION_INVALID), +/* 139*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem94,232,2,2,0,7,XED_EXCEPTION_INVALID), +/* 140*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem94,232,2,2,0,7,XED_EXCEPTION_INVALID), +/* 141*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem108,234,2,2,0,7,XED_EXCEPTION_INVALID), +/* 142*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem108,234,2,2,0,7,XED_EXCEPTION_INVALID), +/* 143*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem108,234,2,2,0,7,XED_EXCEPTION_INVALID), +/* 144*/ XED_DEF_INST(XED_ICLASS_FRSTOR,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FRSTOR_MEMmem108,234,2,2,0,7,XED_EXCEPTION_INVALID), +/* 145*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem94,236,4,2,0,8,XED_EXCEPTION_INVALID), +/* 146*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem94,236,4,2,0,8,XED_EXCEPTION_INVALID), +/* 147*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem94,236,4,2,0,8,XED_EXCEPTION_INVALID), +/* 148*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem108,240,4,2,0,8,XED_EXCEPTION_INVALID), +/* 149*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem108,240,4,2,0,8,XED_EXCEPTION_INVALID), +/* 150*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem108,240,4,2,0,8,XED_EXCEPTION_INVALID), +/* 151*/ XED_DEF_INST(XED_ICLASS_FNSAVE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSAVE_MEMmem108,240,4,2,0,8,XED_EXCEPTION_INVALID), +/* 152*/ XED_DEF_INST(XED_ICLASS_FNSTSW,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTSW_MEMmem16,244,2,3,0,3,XED_EXCEPTION_INVALID), +/* 153*/ XED_DEF_INST(XED_ICLASS_FNSTSW,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FNSTSW_AX,246,2,3,0,3,XED_EXCEPTION_INVALID), +/* 154*/ XED_DEF_INST(XED_ICLASS_FFREE,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FFREE_X87,248,2,3,0,2,XED_EXCEPTION_INVALID), +/* 155*/ XED_DEF_INST(XED_ICLASS_FUCOM,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FUCOM_ST0_X87,89,3,2,0,1,XED_EXCEPTION_INVALID), +/* 156*/ XED_DEF_INST(XED_ICLASS_FUCOMP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FUCOMP_ST0_X87,250,4,2,0,1,XED_EXCEPTION_INVALID), +/* 157*/ XED_DEF_INST(XED_ICLASS_FADDP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FADDP_X87_ST0,254,4,1,0,1,XED_EXCEPTION_INVALID), +/* 158*/ XED_DEF_INST(XED_ICLASS_FMULP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FMULP_X87_ST0,254,4,1,0,1,XED_EXCEPTION_INVALID), +/* 159*/ XED_DEF_INST(XED_ICLASS_FCOMPP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMPP,258,4,2,0,1,XED_EXCEPTION_INVALID), +/* 160*/ XED_DEF_INST(XED_ICLASS_FSUBRP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUBRP_X87_ST0,254,4,1,0,1,XED_EXCEPTION_INVALID), +/* 161*/ XED_DEF_INST(XED_ICLASS_FSUBP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FSUBP_X87_ST0,254,4,1,0,1,XED_EXCEPTION_INVALID), +/* 162*/ XED_DEF_INST(XED_ICLASS_FDIVRP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIVRP_X87_ST0,254,4,1,0,1,XED_EXCEPTION_INVALID), +/* 163*/ XED_DEF_INST(XED_ICLASS_FDIVP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FDIVP_X87_ST0,254,4,1,0,1,XED_EXCEPTION_INVALID), +/* 164*/ XED_DEF_INST(XED_ICLASS_FBLD,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FBLD_ST0_MEMmem80dec,262,4,1,0,1,XED_EXCEPTION_INVALID), +/* 165*/ XED_DEF_INST(XED_ICLASS_FBSTP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FBSTP_MEMmem80dec_ST0,266,4,1,0,1,XED_EXCEPTION_INVALID), +/* 166*/ XED_DEF_INST(XED_ICLASS_FFREEP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FFREEP_X87,270,3,3,0,2,XED_EXCEPTION_INVALID), +/* 167*/ XED_DEF_INST(XED_ICLASS_FUCOMIP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FUCOMIP_ST0_X87,273,5,9,0,1,XED_EXCEPTION_INVALID), +/* 168*/ XED_DEF_INST(XED_ICLASS_FCOMIP,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FCOMIP_ST0_X87,273,5,9,0,1,XED_EXCEPTION_INVALID), +/* 169*/ XED_DEF_INST(XED_ICLASS_ADD_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_LOCK_MEMb_IMMb_80r0,278,3,10,0,9,XED_EXCEPTION_INVALID), +/* 170*/ XED_DEF_INST(XED_ICLASS_ADD_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_LOCK_MEMv_IMMz,281,3,10,0,10,XED_EXCEPTION_INVALID), +/* 171*/ XED_DEF_INST(XED_ICLASS_ADD_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_LOCK_MEMb_IMMb_82r0,278,3,10,0,9,XED_EXCEPTION_INVALID), +/* 172*/ XED_DEF_INST(XED_ICLASS_ADD_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_LOCK_MEMv_IMMb,284,3,10,0,10,XED_EXCEPTION_INVALID), +/* 173*/ XED_DEF_INST(XED_ICLASS_ADD_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_LOCK_MEMb_GPR8,287,3,10,0,9,XED_EXCEPTION_INVALID), +/* 174*/ XED_DEF_INST(XED_ICLASS_ADD_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_LOCK_MEMv_GPRv,290,3,10,0,10,XED_EXCEPTION_INVALID), +/* 175*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_MEMb_IMMb_80r0,278,3,10,0,11,XED_EXCEPTION_INVALID), +/* 176*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPR8_IMMb_80r0,293,3,10,0,12,XED_EXCEPTION_INVALID), +/* 177*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_MEMv_IMMz,281,3,10,0,13,XED_EXCEPTION_INVALID), +/* 178*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPRv_IMMz,296,3,10,0,14,XED_EXCEPTION_INVALID), +/* 179*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_MEMb_IMMb_82r0,278,3,10,0,11,XED_EXCEPTION_INVALID), +/* 180*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPR8_IMMb_82r0,299,3,10,0,12,XED_EXCEPTION_INVALID), +/* 181*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_MEMv_IMMb,284,3,10,0,13,XED_EXCEPTION_INVALID), +/* 182*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPRv_IMMb,302,3,10,0,14,XED_EXCEPTION_INVALID), +/* 183*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_MEMb_GPR8,287,3,10,0,11,XED_EXCEPTION_INVALID), +/* 184*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPR8_GPR8_00,305,3,10,0,12,XED_EXCEPTION_INVALID), +/* 185*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_MEMv_GPRv,290,3,10,0,13,XED_EXCEPTION_INVALID), +/* 186*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPRv_GPRv_01,308,3,10,0,14,XED_EXCEPTION_INVALID), +/* 187*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPR8_MEMb,311,3,10,0,12,XED_EXCEPTION_INVALID), +/* 188*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPR8_GPR8_02,314,3,10,0,12,XED_EXCEPTION_INVALID), +/* 189*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPRv_MEMv,317,3,10,0,14,XED_EXCEPTION_INVALID), +/* 190*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_GPRv_GPRv_03,320,3,10,0,14,XED_EXCEPTION_INVALID), +/* 191*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_AL_IMMb,323,3,10,0,12,XED_EXCEPTION_INVALID), +/* 192*/ XED_DEF_INST(XED_ICLASS_ADD,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADD_OrAX_IMMz,326,3,10,0,14,XED_EXCEPTION_INVALID), +/* 193*/ XED_DEF_INST(XED_ICLASS_OR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_LOCK_MEMb_IMMb_80r1,278,3,11,0,9,XED_EXCEPTION_INVALID), +/* 194*/ XED_DEF_INST(XED_ICLASS_OR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_LOCK_MEMv_IMMz,281,3,11,0,10,XED_EXCEPTION_INVALID), +/* 195*/ XED_DEF_INST(XED_ICLASS_OR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_LOCK_MEMb_IMMb_82r1,278,3,11,0,9,XED_EXCEPTION_INVALID), +/* 196*/ XED_DEF_INST(XED_ICLASS_OR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_LOCK_MEMv_IMMb,284,3,11,0,10,XED_EXCEPTION_INVALID), +/* 197*/ XED_DEF_INST(XED_ICLASS_OR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_LOCK_MEMb_GPR8,287,3,11,0,9,XED_EXCEPTION_INVALID), +/* 198*/ XED_DEF_INST(XED_ICLASS_OR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_LOCK_MEMv_GPRv,290,3,11,0,10,XED_EXCEPTION_INVALID), +/* 199*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_MEMb_IMMb_80r1,278,3,11,0,11,XED_EXCEPTION_INVALID), +/* 200*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPR8_IMMb_80r1,299,3,11,0,12,XED_EXCEPTION_INVALID), +/* 201*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_MEMv_IMMz,281,3,11,0,13,XED_EXCEPTION_INVALID), +/* 202*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPRv_IMMz,296,3,11,0,14,XED_EXCEPTION_INVALID), +/* 203*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_MEMb_IMMb_82r1,278,3,11,0,11,XED_EXCEPTION_INVALID), +/* 204*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPR8_IMMb_82r1,299,3,11,0,12,XED_EXCEPTION_INVALID), +/* 205*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_MEMv_IMMb,284,3,11,0,13,XED_EXCEPTION_INVALID), +/* 206*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPRv_IMMb,302,3,11,0,14,XED_EXCEPTION_INVALID), +/* 207*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_MEMb_GPR8,287,3,11,0,11,XED_EXCEPTION_INVALID), +/* 208*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPR8_GPR8_08,305,3,11,0,12,XED_EXCEPTION_INVALID), +/* 209*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_MEMv_GPRv,290,3,11,0,13,XED_EXCEPTION_INVALID), +/* 210*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPRv_GPRv_09,308,3,11,0,14,XED_EXCEPTION_INVALID), +/* 211*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPR8_MEMb,311,3,11,0,12,XED_EXCEPTION_INVALID), +/* 212*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPR8_GPR8_0A,314,3,11,0,12,XED_EXCEPTION_INVALID), +/* 213*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPRv_MEMv,317,3,11,0,14,XED_EXCEPTION_INVALID), +/* 214*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_GPRv_GPRv_0B,320,3,11,0,14,XED_EXCEPTION_INVALID), +/* 215*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_AL_IMMb,329,3,11,0,12,XED_EXCEPTION_INVALID), +/* 216*/ XED_DEF_INST(XED_ICLASS_OR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_OR_OrAX_IMMz,326,3,11,0,14,XED_EXCEPTION_INVALID), +/* 217*/ XED_DEF_INST(XED_ICLASS_ADC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_LOCK_MEMb_IMMb_80r2,332,3,12,0,9,XED_EXCEPTION_INVALID), +/* 218*/ XED_DEF_INST(XED_ICLASS_ADC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_LOCK_MEMv_IMMz,335,3,12,0,10,XED_EXCEPTION_INVALID), +/* 219*/ XED_DEF_INST(XED_ICLASS_ADC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_LOCK_MEMb_IMMb_82r2,332,3,12,0,9,XED_EXCEPTION_INVALID), +/* 220*/ XED_DEF_INST(XED_ICLASS_ADC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_LOCK_MEMv_IMMb,338,3,12,0,10,XED_EXCEPTION_INVALID), +/* 221*/ XED_DEF_INST(XED_ICLASS_ADC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_LOCK_MEMb_GPR8,341,3,12,0,9,XED_EXCEPTION_INVALID), +/* 222*/ XED_DEF_INST(XED_ICLASS_ADC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_LOCK_MEMv_GPRv,344,3,12,0,10,XED_EXCEPTION_INVALID), +/* 223*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_MEMb_IMMb_80r2,332,3,12,0,11,XED_EXCEPTION_INVALID), +/* 224*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPR8_IMMb_80r2,347,3,12,0,12,XED_EXCEPTION_INVALID), +/* 225*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_MEMv_IMMz,335,3,12,0,13,XED_EXCEPTION_INVALID), +/* 226*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPRv_IMMz,350,3,12,0,14,XED_EXCEPTION_INVALID), +/* 227*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_MEMb_IMMb_82r2,332,3,12,0,11,XED_EXCEPTION_INVALID), +/* 228*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPR8_IMMb_82r2,347,3,12,0,12,XED_EXCEPTION_INVALID), +/* 229*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_MEMv_IMMb,338,3,12,0,13,XED_EXCEPTION_INVALID), +/* 230*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPRv_IMMb,353,3,12,0,14,XED_EXCEPTION_INVALID), +/* 231*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_MEMb_GPR8,341,3,12,0,11,XED_EXCEPTION_INVALID), +/* 232*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPR8_GPR8_10,356,3,12,0,12,XED_EXCEPTION_INVALID), +/* 233*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_MEMv_GPRv,344,3,12,0,13,XED_EXCEPTION_INVALID), +/* 234*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPRv_GPRv_11,359,3,12,0,14,XED_EXCEPTION_INVALID), +/* 235*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPR8_MEMb,362,3,12,0,12,XED_EXCEPTION_INVALID), +/* 236*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPR8_GPR8_12,365,3,12,0,12,XED_EXCEPTION_INVALID), +/* 237*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPRv_MEMv,368,3,12,0,14,XED_EXCEPTION_INVALID), +/* 238*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_GPRv_GPRv_13,371,3,12,0,14,XED_EXCEPTION_INVALID), +/* 239*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_AL_IMMb,374,3,12,0,12,XED_EXCEPTION_INVALID), +/* 240*/ XED_DEF_INST(XED_ICLASS_ADC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_ADC_OrAX_IMMz,377,3,12,0,14,XED_EXCEPTION_INVALID), +/* 241*/ XED_DEF_INST(XED_ICLASS_SBB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_LOCK_MEMb_IMMb_80r3,332,3,13,0,9,XED_EXCEPTION_INVALID), +/* 242*/ XED_DEF_INST(XED_ICLASS_SBB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_LOCK_MEMv_IMMz,335,3,13,0,10,XED_EXCEPTION_INVALID), +/* 243*/ XED_DEF_INST(XED_ICLASS_SBB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_LOCK_MEMb_IMMb_82r3,332,3,13,0,9,XED_EXCEPTION_INVALID), +/* 244*/ XED_DEF_INST(XED_ICLASS_SBB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_LOCK_MEMv_IMMb,338,3,13,0,10,XED_EXCEPTION_INVALID), +/* 245*/ XED_DEF_INST(XED_ICLASS_SBB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_LOCK_MEMb_GPR8,341,3,13,0,9,XED_EXCEPTION_INVALID), +/* 246*/ XED_DEF_INST(XED_ICLASS_SBB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_LOCK_MEMv_GPRv,344,3,13,0,10,XED_EXCEPTION_INVALID), +/* 247*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_MEMb_IMMb_80r3,332,3,13,0,11,XED_EXCEPTION_INVALID), +/* 248*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPR8_IMMb_80r3,347,3,13,0,12,XED_EXCEPTION_INVALID), +/* 249*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_MEMv_IMMz,335,3,13,0,13,XED_EXCEPTION_INVALID), +/* 250*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPRv_IMMz,350,3,13,0,14,XED_EXCEPTION_INVALID), +/* 251*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_MEMb_IMMb_82r3,332,3,13,0,11,XED_EXCEPTION_INVALID), +/* 252*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPR8_IMMb_82r3,347,3,13,0,12,XED_EXCEPTION_INVALID), +/* 253*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_MEMv_IMMb,338,3,13,0,13,XED_EXCEPTION_INVALID), +/* 254*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPRv_IMMb,353,3,13,0,14,XED_EXCEPTION_INVALID), +/* 255*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_MEMb_GPR8,341,3,13,0,11,XED_EXCEPTION_INVALID), +/* 256*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPR8_GPR8_18,356,3,13,0,12,XED_EXCEPTION_INVALID), +/* 257*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_MEMv_GPRv,344,3,13,0,13,XED_EXCEPTION_INVALID), +/* 258*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPRv_GPRv_19,359,3,13,0,14,XED_EXCEPTION_INVALID), +/* 259*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPR8_GPR8_1A,365,3,13,0,12,XED_EXCEPTION_INVALID), +/* 260*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPR8_MEMb,362,3,13,0,12,XED_EXCEPTION_INVALID), +/* 261*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPRv_GPRv_1B,371,3,13,0,14,XED_EXCEPTION_INVALID), +/* 262*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_GPRv_MEMv,368,3,13,0,14,XED_EXCEPTION_INVALID), +/* 263*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_AL_IMMb,374,3,13,0,12,XED_EXCEPTION_INVALID), +/* 264*/ XED_DEF_INST(XED_ICLASS_SBB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SBB_OrAX_IMMz,377,3,13,0,14,XED_EXCEPTION_INVALID), +/* 265*/ XED_DEF_INST(XED_ICLASS_AND_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_LOCK_MEMb_IMMb_80r4,380,3,11,0,9,XED_EXCEPTION_INVALID), +/* 266*/ XED_DEF_INST(XED_ICLASS_AND_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_LOCK_MEMv_IMMz,281,3,11,0,10,XED_EXCEPTION_INVALID), +/* 267*/ XED_DEF_INST(XED_ICLASS_AND_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_LOCK_MEMb_IMMb_82r4,380,3,11,0,9,XED_EXCEPTION_INVALID), +/* 268*/ XED_DEF_INST(XED_ICLASS_AND_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_LOCK_MEMv_IMMb,284,3,11,0,10,XED_EXCEPTION_INVALID), +/* 269*/ XED_DEF_INST(XED_ICLASS_AND_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_LOCK_MEMb_GPR8,287,3,11,0,9,XED_EXCEPTION_INVALID), +/* 270*/ XED_DEF_INST(XED_ICLASS_AND_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_LOCK_MEMv_GPRv,290,3,11,0,10,XED_EXCEPTION_INVALID), +/* 271*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_MEMb_IMMb_80r4,380,3,11,0,11,XED_EXCEPTION_INVALID), +/* 272*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPR8_IMMb_80r4,293,3,11,0,12,XED_EXCEPTION_INVALID), +/* 273*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_MEMv_IMMz,281,3,11,0,13,XED_EXCEPTION_INVALID), +/* 274*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPRv_IMMz,296,3,11,0,14,XED_EXCEPTION_INVALID), +/* 275*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_MEMb_IMMb_82r4,380,3,11,0,11,XED_EXCEPTION_INVALID), +/* 276*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPR8_IMMb_82r4,293,3,11,0,12,XED_EXCEPTION_INVALID), +/* 277*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_MEMv_IMMb,284,3,11,0,13,XED_EXCEPTION_INVALID), +/* 278*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPRv_IMMb,302,3,11,0,14,XED_EXCEPTION_INVALID), +/* 279*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_MEMb_GPR8,287,3,11,0,11,XED_EXCEPTION_INVALID), +/* 280*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPR8_GPR8_20,305,3,11,0,12,XED_EXCEPTION_INVALID), +/* 281*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_MEMv_GPRv,290,3,11,0,13,XED_EXCEPTION_INVALID), +/* 282*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPRv_GPRv_21,308,3,11,0,14,XED_EXCEPTION_INVALID), +/* 283*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPR8_GPR8_22,314,3,11,0,12,XED_EXCEPTION_INVALID), +/* 284*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPR8_MEMb,311,3,11,0,12,XED_EXCEPTION_INVALID), +/* 285*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPRv_GPRv_23,320,3,11,0,14,XED_EXCEPTION_INVALID), +/* 286*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_GPRv_MEMv,317,3,11,0,14,XED_EXCEPTION_INVALID), +/* 287*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_AL_IMMb,323,3,11,0,12,XED_EXCEPTION_INVALID), +/* 288*/ XED_DEF_INST(XED_ICLASS_AND,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_AND_OrAX_IMMz,326,3,11,0,14,XED_EXCEPTION_INVALID), +/* 289*/ XED_DEF_INST(XED_ICLASS_SUB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_LOCK_MEMb_IMMb_80r5,278,3,10,0,9,XED_EXCEPTION_INVALID), +/* 290*/ XED_DEF_INST(XED_ICLASS_SUB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_LOCK_MEMv_IMMz,281,3,10,0,10,XED_EXCEPTION_INVALID), +/* 291*/ XED_DEF_INST(XED_ICLASS_SUB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_LOCK_MEMb_IMMb_82r5,278,3,10,0,9,XED_EXCEPTION_INVALID), +/* 292*/ XED_DEF_INST(XED_ICLASS_SUB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_LOCK_MEMv_IMMb,284,3,10,0,10,XED_EXCEPTION_INVALID), +/* 293*/ XED_DEF_INST(XED_ICLASS_SUB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_LOCK_MEMb_GPR8,287,3,10,0,9,XED_EXCEPTION_INVALID), +/* 294*/ XED_DEF_INST(XED_ICLASS_SUB_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_LOCK_MEMv_GPRv,290,3,10,0,10,XED_EXCEPTION_INVALID), +/* 295*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_MEMb_IMMb_80r5,278,3,10,0,11,XED_EXCEPTION_INVALID), +/* 296*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPR8_IMMb_80r5,299,3,10,0,12,XED_EXCEPTION_INVALID), +/* 297*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_MEMv_IMMz,281,3,10,0,13,XED_EXCEPTION_INVALID), +/* 298*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPRv_IMMz,296,3,10,0,14,XED_EXCEPTION_INVALID), +/* 299*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_MEMb_IMMb_82r5,278,3,10,0,11,XED_EXCEPTION_INVALID), +/* 300*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPR8_IMMb_82r5,299,3,10,0,12,XED_EXCEPTION_INVALID), +/* 301*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_MEMv_IMMb,284,3,10,0,13,XED_EXCEPTION_INVALID), +/* 302*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPRv_IMMb,302,3,10,0,14,XED_EXCEPTION_INVALID), +/* 303*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_MEMb_GPR8,287,3,10,0,11,XED_EXCEPTION_INVALID), +/* 304*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPR8_GPR8_28,305,3,10,0,12,XED_EXCEPTION_INVALID), +/* 305*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_MEMv_GPRv,290,3,10,0,13,XED_EXCEPTION_INVALID), +/* 306*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPRv_GPRv_29,308,3,10,0,14,XED_EXCEPTION_INVALID), +/* 307*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPR8_GPR8_2A,314,3,10,0,12,XED_EXCEPTION_INVALID), +/* 308*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPR8_MEMb,311,3,10,0,12,XED_EXCEPTION_INVALID), +/* 309*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPRv_GPRv_2B,320,3,10,0,14,XED_EXCEPTION_INVALID), +/* 310*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_GPRv_MEMv,317,3,10,0,14,XED_EXCEPTION_INVALID), +/* 311*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_AL_IMMb,323,3,10,0,12,XED_EXCEPTION_INVALID), +/* 312*/ XED_DEF_INST(XED_ICLASS_SUB,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_SUB_OrAX_IMMz,326,3,10,0,14,XED_EXCEPTION_INVALID), +/* 313*/ XED_DEF_INST(XED_ICLASS_XOR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_LOCK_MEMb_IMMb_80r6,380,3,11,0,9,XED_EXCEPTION_INVALID), +/* 314*/ XED_DEF_INST(XED_ICLASS_XOR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_LOCK_MEMv_IMMz,281,3,11,0,10,XED_EXCEPTION_INVALID), +/* 315*/ XED_DEF_INST(XED_ICLASS_XOR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_LOCK_MEMb_IMMb_82r6,380,3,11,0,9,XED_EXCEPTION_INVALID), +/* 316*/ XED_DEF_INST(XED_ICLASS_XOR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_LOCK_MEMv_IMMb,284,3,11,0,10,XED_EXCEPTION_INVALID), +/* 317*/ XED_DEF_INST(XED_ICLASS_XOR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_LOCK_MEMb_GPR8,287,3,11,0,9,XED_EXCEPTION_INVALID), +/* 318*/ XED_DEF_INST(XED_ICLASS_XOR_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_LOCK_MEMv_GPRv,290,3,11,0,10,XED_EXCEPTION_INVALID), +/* 319*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_MEMb_IMMb_80r6,380,3,11,0,11,XED_EXCEPTION_INVALID), +/* 320*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPR8_IMMb_80r6,293,3,11,0,12,XED_EXCEPTION_INVALID), +/* 321*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_MEMv_IMMz,281,3,11,0,13,XED_EXCEPTION_INVALID), +/* 322*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPRv_IMMz,296,3,11,0,14,XED_EXCEPTION_INVALID), +/* 323*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_MEMb_IMMb_82r6,380,3,11,0,11,XED_EXCEPTION_INVALID), +/* 324*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPR8_IMMb_82r6,293,3,11,0,12,XED_EXCEPTION_INVALID), +/* 325*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_MEMv_IMMb,284,3,11,0,13,XED_EXCEPTION_INVALID), +/* 326*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPRv_IMMb,302,3,11,0,14,XED_EXCEPTION_INVALID), +/* 327*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_MEMb_GPR8,287,3,11,0,11,XED_EXCEPTION_INVALID), +/* 328*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPR8_GPR8_30,305,3,11,0,12,XED_EXCEPTION_INVALID), +/* 329*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_MEMv_GPRv,290,3,11,0,13,XED_EXCEPTION_INVALID), +/* 330*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPRv_GPRv_31,308,3,11,0,14,XED_EXCEPTION_INVALID), +/* 331*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPR8_GPR8_32,314,3,11,0,12,XED_EXCEPTION_INVALID), +/* 332*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPR8_MEMb,311,3,11,0,12,XED_EXCEPTION_INVALID), +/* 333*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPRv_GPRv_33,320,3,11,0,14,XED_EXCEPTION_INVALID), +/* 334*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_GPRv_MEMv,317,3,11,0,14,XED_EXCEPTION_INVALID), +/* 335*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_AL_IMMb,329,3,11,0,12,XED_EXCEPTION_INVALID), +/* 336*/ XED_DEF_INST(XED_ICLASS_XOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_XOR_OrAX_IMMz,326,3,11,0,14,XED_EXCEPTION_INVALID), +/* 337*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_MEMb_IMMb_80r7,383,3,10,0,12,XED_EXCEPTION_INVALID), +/* 338*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPR8_IMMb_80r7,386,3,10,0,12,XED_EXCEPTION_INVALID), +/* 339*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_MEMv_IMMz,389,3,10,0,14,XED_EXCEPTION_INVALID), +/* 340*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPRv_IMMz,392,3,10,0,14,XED_EXCEPTION_INVALID), +/* 341*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_MEMb_IMMb_82r7,383,3,10,0,12,XED_EXCEPTION_INVALID), +/* 342*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPR8_IMMb_82r7,386,3,10,0,12,XED_EXCEPTION_INVALID), +/* 343*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_MEMv_IMMb,395,3,10,0,14,XED_EXCEPTION_INVALID), +/* 344*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPRv_IMMb,398,3,10,0,14,XED_EXCEPTION_INVALID), +/* 345*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_MEMb_GPR8,401,3,10,0,12,XED_EXCEPTION_INVALID), +/* 346*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPR8_GPR8_38,404,3,10,0,12,XED_EXCEPTION_INVALID), +/* 347*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_MEMv_GPRv,407,3,10,0,14,XED_EXCEPTION_INVALID), +/* 348*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPRv_GPRv_39,410,3,10,0,14,XED_EXCEPTION_INVALID), +/* 349*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPR8_MEMb,413,3,10,0,12,XED_EXCEPTION_INVALID), +/* 350*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPR8_GPR8_3A,416,3,10,0,12,XED_EXCEPTION_INVALID), +/* 351*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPRv_MEMv,419,3,10,0,14,XED_EXCEPTION_INVALID), +/* 352*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_GPRv_GPRv_3B,422,3,10,0,14,XED_EXCEPTION_INVALID), +/* 353*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_AL_IMMb,425,3,10,0,12,XED_EXCEPTION_INVALID), +/* 354*/ XED_DEF_INST(XED_ICLASS_CMP,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_CMP_OrAX_IMMz,428,3,10,0,14,XED_EXCEPTION_INVALID), +/* 355*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_MEMv,431,4,0,0,15,XED_EXCEPTION_INVALID), +/* 356*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_GPRv_8F,435,4,0,0,16,XED_EXCEPTION_INVALID), +/* 357*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_ES,439,4,0,0,17,XED_EXCEPTION_INVALID), +/* 358*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_SS,443,4,0,0,17,XED_EXCEPTION_INVALID), +/* 359*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_DS,447,4,0,0,17,XED_EXCEPTION_INVALID), +/* 360*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_GPRv_58,451,4,0,0,16,XED_EXCEPTION_INVALID), +/* 361*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_FS,455,4,0,0,17,XED_EXCEPTION_INVALID), +/* 362*/ XED_DEF_INST(XED_ICLASS_POP,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POP_GS,459,4,0,0,17,XED_EXCEPTION_INVALID), +/* 363*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_MEMb_IMMb,380,3,1,1,12,XED_EXCEPTION_INVALID), +/* 364*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_GPR8_IMMb,293,3,2,1,12,XED_EXCEPTION_INVALID), +/* 365*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_MEMv_IMMb,463,3,3,1,14,XED_EXCEPTION_INVALID), +/* 366*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_GPRv_IMMb,466,3,4,1,14,XED_EXCEPTION_INVALID), +/* 367*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_MEMb_ONE,469,3,14,0,18,XED_EXCEPTION_INVALID), +/* 368*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_GPR8_ONE,472,3,14,0,18,XED_EXCEPTION_INVALID), +/* 369*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_MEMv_ONE,475,3,14,0,19,XED_EXCEPTION_INVALID), +/* 370*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_GPRv_ONE,478,3,14,0,19,XED_EXCEPTION_INVALID), +/* 371*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_MEMb_CL,481,3,16,0,12,XED_EXCEPTION_INVALID), +/* 372*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_GPR8_CL,484,3,16,0,12,XED_EXCEPTION_INVALID), +/* 373*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_MEMv_CL,487,3,16,0,14,XED_EXCEPTION_INVALID), +/* 374*/ XED_DEF_INST(XED_ICLASS_ROL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROL_GPRv_CL,490,3,16,0,14,XED_EXCEPTION_INVALID), +/* 375*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_MEMb_IMMb,380,3,5,1,12,XED_EXCEPTION_INVALID), +/* 376*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_GPR8_IMMb,293,3,6,1,12,XED_EXCEPTION_INVALID), +/* 377*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_GPRv_IMMb,466,3,7,1,14,XED_EXCEPTION_INVALID), +/* 378*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_MEMv_IMMb,463,3,8,1,14,XED_EXCEPTION_INVALID), +/* 379*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_MEMb_ONE,469,3,14,0,18,XED_EXCEPTION_INVALID), +/* 380*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_GPR8_ONE,472,3,14,0,18,XED_EXCEPTION_INVALID), +/* 381*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_MEMv_ONE,475,3,14,0,19,XED_EXCEPTION_INVALID), +/* 382*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_GPRv_ONE,478,3,14,0,19,XED_EXCEPTION_INVALID), +/* 383*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_MEMb_CL,481,3,16,0,12,XED_EXCEPTION_INVALID), +/* 384*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_GPR8_CL,484,3,16,0,12,XED_EXCEPTION_INVALID), +/* 385*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_MEMv_CL,487,3,16,0,14,XED_EXCEPTION_INVALID), +/* 386*/ XED_DEF_INST(XED_ICLASS_ROR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_ROR_GPRv_CL,490,3,16,0,14,XED_EXCEPTION_INVALID), +/* 387*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_MEMb_IMMb,493,3,9,1,12,XED_EXCEPTION_INVALID), +/* 388*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_GPR8_IMMb,496,3,10,1,12,XED_EXCEPTION_INVALID), +/* 389*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_MEMv_IMMb,499,3,11,1,14,XED_EXCEPTION_INVALID), +/* 390*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_GPRv_IMMb,502,3,12,1,14,XED_EXCEPTION_INVALID), +/* 391*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_MEMb_ONE,505,3,17,0,18,XED_EXCEPTION_INVALID), +/* 392*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_GPR8_ONE,508,3,17,0,18,XED_EXCEPTION_INVALID), +/* 393*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_MEMv_ONE,511,3,17,0,19,XED_EXCEPTION_INVALID), +/* 394*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_GPRv_ONE,514,3,17,0,19,XED_EXCEPTION_INVALID), +/* 395*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_MEMb_CL,517,3,19,0,12,XED_EXCEPTION_INVALID), +/* 396*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_GPR8_CL,520,3,19,0,12,XED_EXCEPTION_INVALID), +/* 397*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_MEMv_CL,523,3,19,0,14,XED_EXCEPTION_INVALID), +/* 398*/ XED_DEF_INST(XED_ICLASS_RCL,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCL_GPRv_CL,526,3,19,0,14,XED_EXCEPTION_INVALID), +/* 399*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_MEMb_IMMb,493,3,13,1,12,XED_EXCEPTION_INVALID), +/* 400*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_GPR8_IMMb,496,3,14,1,12,XED_EXCEPTION_INVALID), +/* 401*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_MEMv_IMMb,499,3,15,1,14,XED_EXCEPTION_INVALID), +/* 402*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_GPRv_IMMb,502,3,16,1,14,XED_EXCEPTION_INVALID), +/* 403*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_MEMb_ONE,505,3,17,0,18,XED_EXCEPTION_INVALID), +/* 404*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_GPR8_ONE,508,3,17,0,18,XED_EXCEPTION_INVALID), +/* 405*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_MEMv_ONE,511,3,17,0,19,XED_EXCEPTION_INVALID), +/* 406*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_GPRv_ONE,514,3,17,0,19,XED_EXCEPTION_INVALID), +/* 407*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_MEMb_CL,517,3,19,0,12,XED_EXCEPTION_INVALID), +/* 408*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_GPR8_CL,520,3,19,0,12,XED_EXCEPTION_INVALID), +/* 409*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_MEMv_CL,523,3,19,0,14,XED_EXCEPTION_INVALID), +/* 410*/ XED_DEF_INST(XED_ICLASS_RCR,XED_CATEGORY_ROTATE,XED_EXTENSION_BASE,3,XED_IFORM_RCR_GPRv_CL,526,3,19,0,14,XED_EXCEPTION_INVALID), +/* 411*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMb_IMMb_C0r4,380,3,17,1,12,XED_EXCEPTION_INVALID), +/* 412*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPR8_IMMb_C0r4,293,3,18,1,12,XED_EXCEPTION_INVALID), +/* 413*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMb_IMMb_C0r6,380,3,19,1,12,XED_EXCEPTION_INVALID), +/* 414*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPR8_IMMb_C0r6,293,3,20,1,12,XED_EXCEPTION_INVALID), +/* 415*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMv_IMMb_C1r4,463,3,21,1,14,XED_EXCEPTION_INVALID), +/* 416*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPRv_IMMb_C1r4,466,3,22,1,14,XED_EXCEPTION_INVALID), +/* 417*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMv_IMMb_C1r6,463,3,23,1,14,XED_EXCEPTION_INVALID), +/* 418*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPRv_IMMb_C1r6,466,3,24,1,14,XED_EXCEPTION_INVALID), +/* 419*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMb_ONE_D0r4,469,3,20,0,18,XED_EXCEPTION_INVALID), +/* 420*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPR8_ONE_D0r4,472,3,20,0,18,XED_EXCEPTION_INVALID), +/* 421*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMb_ONE_D0r6,469,3,20,0,18,XED_EXCEPTION_INVALID), +/* 422*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPR8_ONE_D0r6,472,3,20,0,18,XED_EXCEPTION_INVALID), +/* 423*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMv_ONE_D1r6,475,3,20,0,19,XED_EXCEPTION_INVALID), +/* 424*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPRv_ONE_D1r6,478,3,20,0,19,XED_EXCEPTION_INVALID), +/* 425*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMv_ONE_D1r4,475,3,20,0,19,XED_EXCEPTION_INVALID), +/* 426*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPRv_ONE_D1r4,478,3,20,0,19,XED_EXCEPTION_INVALID), +/* 427*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMb_CL_D2r4,481,3,22,0,12,XED_EXCEPTION_INVALID), +/* 428*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPR8_CL_D2r4,484,3,22,0,12,XED_EXCEPTION_INVALID), +/* 429*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMb_CL_D2r6,481,3,22,0,12,XED_EXCEPTION_INVALID), +/* 430*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPR8_CL_D2r6,484,3,22,0,12,XED_EXCEPTION_INVALID), +/* 431*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMv_CL_D3r4,487,3,22,0,14,XED_EXCEPTION_INVALID), +/* 432*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPRv_CL_D3r4,490,3,22,0,14,XED_EXCEPTION_INVALID), +/* 433*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_MEMv_CL_D3r6,487,3,22,0,14,XED_EXCEPTION_INVALID), +/* 434*/ XED_DEF_INST(XED_ICLASS_SHL,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHL_GPRv_CL_D3r6,490,3,22,0,14,XED_EXCEPTION_INVALID), +/* 435*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_MEMb_IMMb,380,3,25,1,12,XED_EXCEPTION_INVALID), +/* 436*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_GPR8_IMMb,293,3,26,1,12,XED_EXCEPTION_INVALID), +/* 437*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_MEMv_IMMb,463,3,27,1,14,XED_EXCEPTION_INVALID), +/* 438*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_GPRv_IMMb,466,3,28,1,14,XED_EXCEPTION_INVALID), +/* 439*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_MEMb_ONE,469,3,20,0,18,XED_EXCEPTION_INVALID), +/* 440*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_GPR8_ONE,472,3,20,0,18,XED_EXCEPTION_INVALID), +/* 441*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_MEMv_ONE,475,3,20,0,19,XED_EXCEPTION_INVALID), +/* 442*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_GPRv_ONE,478,3,20,0,19,XED_EXCEPTION_INVALID), +/* 443*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_MEMb_CL,481,3,22,0,12,XED_EXCEPTION_INVALID), +/* 444*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_GPR8_CL,484,3,22,0,12,XED_EXCEPTION_INVALID), +/* 445*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_MEMv_CL,487,3,22,0,14,XED_EXCEPTION_INVALID), +/* 446*/ XED_DEF_INST(XED_ICLASS_SHR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHR_GPRv_CL,490,3,22,0,14,XED_EXCEPTION_INVALID), +/* 447*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_MEMb_IMMb,380,3,29,1,12,XED_EXCEPTION_INVALID), +/* 448*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_GPR8_IMMb,293,3,30,1,12,XED_EXCEPTION_INVALID), +/* 449*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_MEMv_IMMb,463,3,31,1,14,XED_EXCEPTION_INVALID), +/* 450*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_GPRv_IMMb,466,3,32,1,14,XED_EXCEPTION_INVALID), +/* 451*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_MEMb_ONE,469,3,20,0,18,XED_EXCEPTION_INVALID), +/* 452*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_GPR8_ONE,472,3,20,0,18,XED_EXCEPTION_INVALID), +/* 453*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_MEMv_ONE,475,3,20,0,19,XED_EXCEPTION_INVALID), +/* 454*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_GPRv_ONE,478,3,20,0,19,XED_EXCEPTION_INVALID), +/* 455*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_MEMb_CL,481,3,22,0,12,XED_EXCEPTION_INVALID), +/* 456*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_GPR8_CL,484,3,22,0,12,XED_EXCEPTION_INVALID), +/* 457*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_MEMv_CL,487,3,22,0,14,XED_EXCEPTION_INVALID), +/* 458*/ XED_DEF_INST(XED_ICLASS_SAR,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SAR_GPRv_CL,490,3,22,0,14,XED_EXCEPTION_INVALID), +/* 459*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_MEMb_IMMb_F6r0,383,3,11,0,12,XED_EXCEPTION_INVALID), +/* 460*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_MEMb_IMMb_F6r1,383,3,11,0,12,XED_EXCEPTION_INVALID), +/* 461*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_GPR8_IMMb_F6r0,386,3,11,0,12,XED_EXCEPTION_INVALID), +/* 462*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_GPR8_IMMb_F6r1,386,3,11,0,12,XED_EXCEPTION_INVALID), +/* 463*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_MEMv_IMMz_F7r0,389,3,11,0,14,XED_EXCEPTION_INVALID), +/* 464*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_MEMv_IMMz_F7r1,389,3,11,0,14,XED_EXCEPTION_INVALID), +/* 465*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_GPRv_IMMz_F7r0,392,3,11,0,14,XED_EXCEPTION_INVALID), +/* 466*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_GPRv_IMMz_F7r1,392,3,11,0,14,XED_EXCEPTION_INVALID), +/* 467*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_MEMb_GPR8,401,3,11,0,12,XED_EXCEPTION_INVALID), +/* 468*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_GPR8_GPR8,404,3,11,0,12,XED_EXCEPTION_INVALID), +/* 469*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_MEMv_GPRv,407,3,11,0,14,XED_EXCEPTION_INVALID), +/* 470*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_GPRv_GPRv,410,3,11,0,14,XED_EXCEPTION_INVALID), +/* 471*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_AL_IMMb,425,3,11,0,12,XED_EXCEPTION_INVALID), +/* 472*/ XED_DEF_INST(XED_ICLASS_TEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_TEST_OrAX_IMMz,428,3,11,0,14,XED_EXCEPTION_INVALID), +/* 473*/ XED_DEF_INST(XED_ICLASS_NOT_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_NOT_LOCK_MEMb,529,1,0,0,9,XED_EXCEPTION_INVALID), +/* 474*/ XED_DEF_INST(XED_ICLASS_NOT_LOCK,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_NOT_LOCK_MEMv,530,1,0,0,10,XED_EXCEPTION_INVALID), +/* 475*/ XED_DEF_INST(XED_ICLASS_NOT,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_NOT_MEMb,529,1,0,0,11,XED_EXCEPTION_INVALID), +/* 476*/ XED_DEF_INST(XED_ICLASS_NOT,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_NOT_GPR8,531,1,0,0,12,XED_EXCEPTION_INVALID), +/* 477*/ XED_DEF_INST(XED_ICLASS_NOT,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_NOT_MEMv,530,1,0,0,13,XED_EXCEPTION_INVALID), +/* 478*/ XED_DEF_INST(XED_ICLASS_NOT,XED_CATEGORY_LOGICAL,XED_EXTENSION_BASE,3,XED_IFORM_NOT_GPRv,532,1,0,0,14,XED_EXCEPTION_INVALID), +/* 479*/ XED_DEF_INST(XED_ICLASS_NEG_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_NEG_LOCK_MEMb,533,2,10,0,9,XED_EXCEPTION_INVALID), +/* 480*/ XED_DEF_INST(XED_ICLASS_NEG_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_NEG_LOCK_MEMv,535,2,10,0,10,XED_EXCEPTION_INVALID), +/* 481*/ XED_DEF_INST(XED_ICLASS_NEG,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_NEG_MEMb,533,2,10,0,11,XED_EXCEPTION_INVALID), +/* 482*/ XED_DEF_INST(XED_ICLASS_NEG,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_NEG_GPR8,537,2,10,0,12,XED_EXCEPTION_INVALID), +/* 483*/ XED_DEF_INST(XED_ICLASS_NEG,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_NEG_MEMv,535,2,10,0,13,XED_EXCEPTION_INVALID), +/* 484*/ XED_DEF_INST(XED_ICLASS_NEG,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_NEG_GPRv,539,2,10,0,14,XED_EXCEPTION_INVALID), +/* 485*/ XED_DEF_INST(XED_ICLASS_MUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_MUL_MEMb,541,4,23,0,12,XED_EXCEPTION_INVALID), +/* 486*/ XED_DEF_INST(XED_ICLASS_MUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_MUL_GPR8,545,4,23,0,12,XED_EXCEPTION_INVALID), +/* 487*/ XED_DEF_INST(XED_ICLASS_MUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_MUL_MEMv,549,4,23,0,14,XED_EXCEPTION_INVALID), +/* 488*/ XED_DEF_INST(XED_ICLASS_MUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_MUL_GPRv,553,4,23,0,14,XED_EXCEPTION_INVALID), +/* 489*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_MEMb,541,4,23,0,12,XED_EXCEPTION_INVALID), +/* 490*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPR8,545,4,23,0,12,XED_EXCEPTION_INVALID), +/* 491*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_MEMv,549,4,23,0,14,XED_EXCEPTION_INVALID), +/* 492*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv,553,4,23,0,14,XED_EXCEPTION_INVALID), +/* 493*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv_MEMv_IMMz,557,4,23,0,14,XED_EXCEPTION_INVALID), +/* 494*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv_GPRv_IMMz,561,4,23,0,14,XED_EXCEPTION_INVALID), +/* 495*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv_MEMv_IMMb,565,4,23,0,14,XED_EXCEPTION_INVALID), +/* 496*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv_GPRv_IMMb,569,4,23,0,14,XED_EXCEPTION_INVALID), +/* 497*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv_MEMv,317,3,23,0,14,XED_EXCEPTION_INVALID), +/* 498*/ XED_DEF_INST(XED_ICLASS_IMUL,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IMUL_GPRv_GPRv,320,3,23,0,14,XED_EXCEPTION_INVALID), +/* 499*/ XED_DEF_INST(XED_ICLASS_DIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DIV_MEMb,573,3,24,0,12,XED_EXCEPTION_INVALID), +/* 500*/ XED_DEF_INST(XED_ICLASS_DIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DIV_GPR8,576,3,24,0,12,XED_EXCEPTION_INVALID), +/* 501*/ XED_DEF_INST(XED_ICLASS_DIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DIV_MEMv,579,4,24,0,14,XED_EXCEPTION_INVALID), +/* 502*/ XED_DEF_INST(XED_ICLASS_DIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DIV_GPRv,583,4,24,0,14,XED_EXCEPTION_INVALID), +/* 503*/ XED_DEF_INST(XED_ICLASS_IDIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IDIV_MEMb,573,3,24,0,12,XED_EXCEPTION_INVALID), +/* 504*/ XED_DEF_INST(XED_ICLASS_IDIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IDIV_GPR8,576,3,24,0,12,XED_EXCEPTION_INVALID), +/* 505*/ XED_DEF_INST(XED_ICLASS_IDIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IDIV_MEMv,579,4,24,0,14,XED_EXCEPTION_INVALID), +/* 506*/ XED_DEF_INST(XED_ICLASS_IDIV,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_IDIV_GPRv,583,4,24,0,14,XED_EXCEPTION_INVALID), +/* 507*/ XED_DEF_INST(XED_ICLASS_INC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_LOCK_MEMb,533,2,25,0,9,XED_EXCEPTION_INVALID), +/* 508*/ XED_DEF_INST(XED_ICLASS_INC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_LOCK_MEMv,535,2,25,0,10,XED_EXCEPTION_INVALID), +/* 509*/ XED_DEF_INST(XED_ICLASS_INC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_MEMb,533,2,25,0,11,XED_EXCEPTION_INVALID), +/* 510*/ XED_DEF_INST(XED_ICLASS_INC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_GPR8,537,2,25,0,12,XED_EXCEPTION_INVALID), +/* 511*/ XED_DEF_INST(XED_ICLASS_INC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_MEMv,535,2,25,0,13,XED_EXCEPTION_INVALID), +/* 512*/ XED_DEF_INST(XED_ICLASS_INC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_GPRv_FFr0,539,2,25,0,14,XED_EXCEPTION_INVALID), +/* 513*/ XED_DEF_INST(XED_ICLASS_INC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_INC_GPRv_40,587,2,25,0,14,XED_EXCEPTION_INVALID), +/* 514*/ XED_DEF_INST(XED_ICLASS_DEC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_LOCK_MEMb,533,2,25,0,9,XED_EXCEPTION_INVALID), +/* 515*/ XED_DEF_INST(XED_ICLASS_DEC_LOCK,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_LOCK_MEMv,535,2,25,0,10,XED_EXCEPTION_INVALID), +/* 516*/ XED_DEF_INST(XED_ICLASS_DEC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_MEMb,533,2,25,0,11,XED_EXCEPTION_INVALID), +/* 517*/ XED_DEF_INST(XED_ICLASS_DEC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_GPR8,537,2,25,0,12,XED_EXCEPTION_INVALID), +/* 518*/ XED_DEF_INST(XED_ICLASS_DEC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_MEMv,535,2,25,0,13,XED_EXCEPTION_INVALID), +/* 519*/ XED_DEF_INST(XED_ICLASS_DEC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_GPRv_FFr1,539,2,25,0,14,XED_EXCEPTION_INVALID), +/* 520*/ XED_DEF_INST(XED_ICLASS_DEC,XED_CATEGORY_BINARY,XED_EXTENSION_BASE,3,XED_IFORM_DEC_GPRv_48,587,2,25,0,14,XED_EXCEPTION_INVALID), +/* 521*/ XED_DEF_INST(XED_ICLASS_CALL_NEAR,XED_CATEGORY_CALL,XED_EXTENSION_BASE,3,XED_IFORM_CALL_NEAR_MEMv,589,5,0,0,20,XED_EXCEPTION_INVALID), +/* 522*/ XED_DEF_INST(XED_ICLASS_CALL_NEAR,XED_CATEGORY_CALL,XED_EXTENSION_BASE,3,XED_IFORM_CALL_NEAR_GPRv,594,5,0,0,21,XED_EXCEPTION_INVALID), +/* 523*/ XED_DEF_INST(XED_ICLASS_CALL_NEAR,XED_CATEGORY_CALL,XED_EXTENSION_BASE,3,XED_IFORM_CALL_NEAR_RELBRz,599,5,0,0,22,XED_EXCEPTION_INVALID), +/* 524*/ XED_DEF_INST(XED_ICLASS_CALL_NEAR,XED_CATEGORY_CALL,XED_EXTENSION_BASE,3,XED_IFORM_CALL_NEAR_RELBRd,604,5,0,0,22,XED_EXCEPTION_INVALID), +/* 525*/ XED_DEF_INST(XED_ICLASS_JMP,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_MEMv,609,2,0,0,23,XED_EXCEPTION_INVALID), +/* 526*/ XED_DEF_INST(XED_ICLASS_JMP,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_GPRv,611,2,0,0,23,XED_EXCEPTION_INVALID), +/* 527*/ XED_DEF_INST(XED_ICLASS_JMP,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_RELBRz,613,2,0,0,24,XED_EXCEPTION_INVALID), +/* 528*/ XED_DEF_INST(XED_ICLASS_JMP,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_RELBRd,615,2,0,0,25,XED_EXCEPTION_INVALID), +/* 529*/ XED_DEF_INST(XED_ICLASS_JMP,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_RELBRb,617,2,0,0,0,XED_EXCEPTION_INVALID), +/* 530*/ XED_DEF_INST(XED_ICLASS_JMP,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_RELBRb,619,2,0,0,0,XED_EXCEPTION_INVALID), +/* 531*/ XED_DEF_INST(XED_ICLASS_JMP_FAR,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_FAR_MEMp2,621,2,0,0,26,XED_EXCEPTION_INVALID), +/* 532*/ XED_DEF_INST(XED_ICLASS_JMP_FAR,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JMP_FAR_PTRp_IMMw,623,3,0,0,27,XED_EXCEPTION_INVALID), +/* 533*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_MEMv,626,4,0,0,28,XED_EXCEPTION_INVALID), +/* 534*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_GPRv_FFr6,630,4,0,0,29,XED_EXCEPTION_INVALID), +/* 535*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_ES,634,4,0,0,29,XED_EXCEPTION_INVALID), +/* 536*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_CS,638,4,0,0,29,XED_EXCEPTION_INVALID), +/* 537*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_SS,642,4,0,0,29,XED_EXCEPTION_INVALID), +/* 538*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_DS,646,4,0,0,29,XED_EXCEPTION_INVALID), +/* 539*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_GPRv_50,650,4,0,0,29,XED_EXCEPTION_INVALID), +/* 540*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_IMMz,654,4,0,0,29,XED_EXCEPTION_INVALID), +/* 541*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_IMMb,658,4,0,0,29,XED_EXCEPTION_INVALID), +/* 542*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_FS,662,4,0,0,29,XED_EXCEPTION_INVALID), +/* 543*/ XED_DEF_INST(XED_ICLASS_PUSH,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSH_GS,666,4,0,0,29,XED_EXCEPTION_INVALID), +/* 544*/ XED_DEF_INST(XED_ICLASS_SLDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SLDT_MEMw,670,2,0,0,30,XED_EXCEPTION_INVALID), +/* 545*/ XED_DEF_INST(XED_ICLASS_SLDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SLDT_GPRv,672,2,0,0,31,XED_EXCEPTION_INVALID), +/* 546*/ XED_DEF_INST(XED_ICLASS_STR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_STR_MEMw,674,2,0,0,30,XED_EXCEPTION_INVALID), +/* 547*/ XED_DEF_INST(XED_ICLASS_STR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_STR_GPRv,676,2,0,0,31,XED_EXCEPTION_INVALID), +/* 548*/ XED_DEF_INST(XED_ICLASS_LLDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LLDT_MEMw,678,2,0,0,32,XED_EXCEPTION_INVALID), +/* 549*/ XED_DEF_INST(XED_ICLASS_LLDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LLDT_GPR16,680,2,0,0,32,XED_EXCEPTION_INVALID), +/* 550*/ XED_DEF_INST(XED_ICLASS_LTR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LTR_MEMw,682,2,0,0,32,XED_EXCEPTION_INVALID), +/* 551*/ XED_DEF_INST(XED_ICLASS_LTR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LTR_GPR16,684,2,0,0,32,XED_EXCEPTION_INVALID), +/* 552*/ XED_DEF_INST(XED_ICLASS_VERR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_VERR_MEMw,686,2,26,0,33,XED_EXCEPTION_INVALID), +/* 553*/ XED_DEF_INST(XED_ICLASS_VERR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_VERR_GPR16,688,2,26,0,33,XED_EXCEPTION_INVALID), +/* 554*/ XED_DEF_INST(XED_ICLASS_VERW,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_VERW_MEMw,686,2,26,0,33,XED_EXCEPTION_INVALID), +/* 555*/ XED_DEF_INST(XED_ICLASS_VERW,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_VERW_GPR16,688,2,26,0,33,XED_EXCEPTION_INVALID), +/* 556*/ XED_DEF_INST(XED_ICLASS_LGDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_LGDT_MEMs64,690,2,0,0,1,XED_EXCEPTION_INVALID), +/* 557*/ XED_DEF_INST(XED_ICLASS_LGDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_LGDT_MEMs,692,2,0,0,34,XED_EXCEPTION_INVALID), +/* 558*/ XED_DEF_INST(XED_ICLASS_SMSW,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SMSW_MEMw,694,2,0,0,0,XED_EXCEPTION_INVALID), +/* 559*/ XED_DEF_INST(XED_ICLASS_SMSW,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SMSW_GPRv,696,2,0,0,14,XED_EXCEPTION_INVALID), +/* 560*/ XED_DEF_INST(XED_ICLASS_LMSW,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LMSW_MEMw,698,2,0,0,35,XED_EXCEPTION_INVALID), +/* 561*/ XED_DEF_INST(XED_ICLASS_LMSW,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LMSW_GPR16,700,2,0,0,35,XED_EXCEPTION_INVALID), +/* 562*/ XED_DEF_INST(XED_ICLASS_BT,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BT_MEMv_IMMb,702,3,27,0,14,XED_EXCEPTION_INVALID), +/* 563*/ XED_DEF_INST(XED_ICLASS_BT,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BT_GPRv_IMMb,705,3,27,0,14,XED_EXCEPTION_INVALID), +/* 564*/ XED_DEF_INST(XED_ICLASS_BT,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BT_MEMv_GPRv,407,3,27,0,14,XED_EXCEPTION_INVALID), +/* 565*/ XED_DEF_INST(XED_ICLASS_BT,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BT_GPRv_GPRv,410,3,27,0,14,XED_EXCEPTION_INVALID), +/* 566*/ XED_DEF_INST(XED_ICLASS_BTS_LOCK,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTS_LOCK_MEMv_IMMb,463,3,27,0,10,XED_EXCEPTION_INVALID), +/* 567*/ XED_DEF_INST(XED_ICLASS_BTS_LOCK,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTS_LOCK_MEMv_GPRv,290,3,27,0,10,XED_EXCEPTION_INVALID), +/* 568*/ XED_DEF_INST(XED_ICLASS_BTS,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTS_MEMv_IMMb,463,3,27,0,13,XED_EXCEPTION_INVALID), +/* 569*/ XED_DEF_INST(XED_ICLASS_BTS,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTS_GPRv_IMMb,466,3,27,0,14,XED_EXCEPTION_INVALID), +/* 570*/ XED_DEF_INST(XED_ICLASS_BTS,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTS_MEMv_GPRv,290,3,27,0,13,XED_EXCEPTION_INVALID), +/* 571*/ XED_DEF_INST(XED_ICLASS_BTS,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTS_GPRv_GPRv,308,3,27,0,14,XED_EXCEPTION_INVALID), +/* 572*/ XED_DEF_INST(XED_ICLASS_BTR_LOCK,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTR_LOCK_MEMv_IMMb,463,3,27,0,10,XED_EXCEPTION_INVALID), +/* 573*/ XED_DEF_INST(XED_ICLASS_BTR_LOCK,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTR_LOCK_MEMv_GPRv,290,3,27,0,10,XED_EXCEPTION_INVALID), +/* 574*/ XED_DEF_INST(XED_ICLASS_BTR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTR_MEMv_IMMb,463,3,27,0,13,XED_EXCEPTION_INVALID), +/* 575*/ XED_DEF_INST(XED_ICLASS_BTR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTR_GPRv_IMMb,466,3,27,0,14,XED_EXCEPTION_INVALID), +/* 576*/ XED_DEF_INST(XED_ICLASS_BTR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTR_MEMv_GPRv,290,3,27,0,13,XED_EXCEPTION_INVALID), +/* 577*/ XED_DEF_INST(XED_ICLASS_BTR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTR_GPRv_GPRv,308,3,27,0,14,XED_EXCEPTION_INVALID), +/* 578*/ XED_DEF_INST(XED_ICLASS_BTC_LOCK,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTC_LOCK_MEMv_IMMb,463,3,27,0,10,XED_EXCEPTION_INVALID), +/* 579*/ XED_DEF_INST(XED_ICLASS_BTC_LOCK,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTC_LOCK_MEMv_GPRv,290,3,27,0,10,XED_EXCEPTION_INVALID), +/* 580*/ XED_DEF_INST(XED_ICLASS_BTC,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTC_MEMv_IMMb,463,3,27,0,13,XED_EXCEPTION_INVALID), +/* 581*/ XED_DEF_INST(XED_ICLASS_BTC,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTC_GPRv_IMMb,466,3,27,0,14,XED_EXCEPTION_INVALID), +/* 582*/ XED_DEF_INST(XED_ICLASS_BTC,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTC_MEMv_GPRv,290,3,27,0,13,XED_EXCEPTION_INVALID), +/* 583*/ XED_DEF_INST(XED_ICLASS_BTC,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BTC_GPRv_GPRv,308,3,27,0,14,XED_EXCEPTION_INVALID), +/* 584*/ XED_DEF_INST(XED_ICLASS_VMCLEAR,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMCLEAR_MEMq,708,2,28,0,1,XED_EXCEPTION_INVALID), +/* 585*/ XED_DEF_INST(XED_ICLASS_VMPTRLD,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMPTRLD_MEMq,708,2,28,0,1,XED_EXCEPTION_INVALID), +/* 586*/ XED_DEF_INST(XED_ICLASS_VMPTRST,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMPTRST_MEMq,710,2,28,0,1,XED_EXCEPTION_INVALID), +/* 587*/ XED_DEF_INST(XED_ICLASS_VMXON,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMXON_MEMq,708,2,28,0,30,XED_EXCEPTION_INVALID), +/* 588*/ XED_DEF_INST(XED_ICLASS_CMPXCHG8B_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG8B_LOCK_MEMq,712,6,26,0,36,XED_EXCEPTION_INVALID), +/* 589*/ XED_DEF_INST(XED_ICLASS_CMPXCHG8B_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG8B_LOCK_MEMq,712,6,26,0,36,XED_EXCEPTION_INVALID), +/* 590*/ XED_DEF_INST(XED_ICLASS_CMPXCHG8B,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG8B_MEMq,712,6,26,0,37,XED_EXCEPTION_INVALID), +/* 591*/ XED_DEF_INST(XED_ICLASS_CMPXCHG8B,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG8B_MEMq,712,6,26,0,37,XED_EXCEPTION_INVALID), +/* 592*/ XED_DEF_INST(XED_ICLASS_CMPXCHG16B_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_LONGMODE,3,XED_IFORM_CMPXCHG16B_LOCK_MEMdq,718,6,26,0,38,XED_EXCEPTION_INVALID), +/* 593*/ XED_DEF_INST(XED_ICLASS_CMPXCHG16B,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_LONGMODE,3,XED_IFORM_CMPXCHG16B_MEMdq,718,6,26,0,39,XED_EXCEPTION_INVALID), +/* 594*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPR8_IMMb_C6r0,724,2,0,0,12,XED_EXCEPTION_INVALID), +/* 595*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMb_IMMb,726,2,0,0,40,XED_EXCEPTION_INVALID), +/* 596*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPRv_IMMz,728,2,0,0,14,XED_EXCEPTION_INVALID), +/* 597*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMv_IMMz,730,2,0,0,41,XED_EXCEPTION_INVALID), +/* 598*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPR8_GPR8_88,732,2,0,0,12,XED_EXCEPTION_INVALID), +/* 599*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMb_GPR8,734,2,0,0,40,XED_EXCEPTION_INVALID), +/* 600*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMv_GPRv,736,2,0,0,41,XED_EXCEPTION_INVALID), +/* 601*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPRv_GPRv_89,738,2,0,0,14,XED_EXCEPTION_INVALID), +/* 602*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPR8_MEMb,740,2,0,0,12,XED_EXCEPTION_INVALID), +/* 603*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPR8_GPR8_8A,742,2,0,0,12,XED_EXCEPTION_INVALID), +/* 604*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPRv_MEMv,744,2,0,0,14,XED_EXCEPTION_INVALID), +/* 605*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPRv_GPRv_8B,746,2,0,0,14,XED_EXCEPTION_INVALID), +/* 606*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMw_SEG,748,2,0,0,0,XED_EXCEPTION_INVALID), +/* 607*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPRv_SEG,750,2,0,0,14,XED_EXCEPTION_INVALID), +/* 608*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_SEG_MEMw,752,2,0,0,1,XED_EXCEPTION_INVALID), +/* 609*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_SEG_GPR16,754,2,0,0,1,XED_EXCEPTION_INVALID), +/* 610*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_AL_MEMb,756,2,0,0,42,XED_EXCEPTION_INVALID), +/* 611*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_OrAX_MEMv,758,2,0,0,43,XED_EXCEPTION_INVALID), +/* 612*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMb_AL,760,2,0,0,42,XED_EXCEPTION_INVALID), +/* 613*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_MEMv_OrAX,762,2,0,0,43,XED_EXCEPTION_INVALID), +/* 614*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPR8_IMMb_B0,764,2,0,0,12,XED_EXCEPTION_INVALID), +/* 615*/ XED_DEF_INST(XED_ICLASS_MOV,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOV_GPRv_IMMv,766,2,0,0,14,XED_EXCEPTION_INVALID), +/* 616*/ XED_DEF_INST(XED_ICLASS_PSRLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLW_MMXq_IMMb,768,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 617*/ XED_DEF_INST(XED_ICLASS_PSRLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLW_XMMdq_IMMb,770,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 618*/ XED_DEF_INST(XED_ICLASS_PSRLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLW_MMXq_MEMq,772,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 619*/ XED_DEF_INST(XED_ICLASS_PSRLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLW_MMXq_MMXq,774,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 620*/ XED_DEF_INST(XED_ICLASS_PSRLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 621*/ XED_DEF_INST(XED_ICLASS_PSRLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 622*/ XED_DEF_INST(XED_ICLASS_PSRAW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRAW_MMXq_IMMb,780,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 623*/ XED_DEF_INST(XED_ICLASS_PSRAW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRAW_XMMdq_IMMb,782,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 624*/ XED_DEF_INST(XED_ICLASS_PSRAW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRAW_MMXq_MEMq,784,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 625*/ XED_DEF_INST(XED_ICLASS_PSRAW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRAW_MMXq_MMXq,786,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 626*/ XED_DEF_INST(XED_ICLASS_PSRAW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRAW_XMMdq_MEMdq,788,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 627*/ XED_DEF_INST(XED_ICLASS_PSRAW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRAW_XMMdq_XMMdq,790,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 628*/ XED_DEF_INST(XED_ICLASS_PSLLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLW_MMXq_IMMb,768,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 629*/ XED_DEF_INST(XED_ICLASS_PSLLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLW_XMMdq_IMMb,770,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 630*/ XED_DEF_INST(XED_ICLASS_PSLLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLW_MMXq_MEMq,772,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 631*/ XED_DEF_INST(XED_ICLASS_PSLLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLW_MMXq_MMXq,774,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 632*/ XED_DEF_INST(XED_ICLASS_PSLLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLW_XMMdq_MEMdq,792,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 633*/ XED_DEF_INST(XED_ICLASS_PSLLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLW_XMMdq_XMMdq,794,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 634*/ XED_DEF_INST(XED_ICLASS_PSRLD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLD_MMXq_IMMb,796,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 635*/ XED_DEF_INST(XED_ICLASS_PSRLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLD_XMMdq_IMMb,798,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 636*/ XED_DEF_INST(XED_ICLASS_PSRLD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLD_MMXq_MEMq,800,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 637*/ XED_DEF_INST(XED_ICLASS_PSRLD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLD_MMXq_MMXq,802,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 638*/ XED_DEF_INST(XED_ICLASS_PSRLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 639*/ XED_DEF_INST(XED_ICLASS_PSRLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 640*/ XED_DEF_INST(XED_ICLASS_PSRAD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRAD_MMXq_IMMb,804,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 641*/ XED_DEF_INST(XED_ICLASS_PSRAD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRAD_XMMdq_IMMb,806,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 642*/ XED_DEF_INST(XED_ICLASS_PSRAD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRAD_MMXq_MEMq,808,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 643*/ XED_DEF_INST(XED_ICLASS_PSRAD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRAD_MMXq_MMXq,810,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 644*/ XED_DEF_INST(XED_ICLASS_PSRAD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRAD_XMMdq_MEMdq,812,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 645*/ XED_DEF_INST(XED_ICLASS_PSRAD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRAD_XMMdq_XMMdq,814,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 646*/ XED_DEF_INST(XED_ICLASS_PSLLD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLD_MMXq_IMMb,796,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 647*/ XED_DEF_INST(XED_ICLASS_PSLLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLD_XMMdq_IMMb,798,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 648*/ XED_DEF_INST(XED_ICLASS_PSLLD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLD_MMXq_MEMq,800,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 649*/ XED_DEF_INST(XED_ICLASS_PSLLD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLD_MMXq_MMXq,802,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 650*/ XED_DEF_INST(XED_ICLASS_PSLLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 651*/ XED_DEF_INST(XED_ICLASS_PSLLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 652*/ XED_DEF_INST(XED_ICLASS_PSRLQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLQ_MMXq_IMMb,816,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 653*/ XED_DEF_INST(XED_ICLASS_PSRLQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLQ_XMMdq_IMMb,818,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 654*/ XED_DEF_INST(XED_ICLASS_PSRLQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLQ_MMXq_MEMq,820,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 655*/ XED_DEF_INST(XED_ICLASS_PSRLQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSRLQ_MMXq_MMXq,822,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 656*/ XED_DEF_INST(XED_ICLASS_PSRLQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 657*/ XED_DEF_INST(XED_ICLASS_PSRLQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 658*/ XED_DEF_INST(XED_ICLASS_PSLLQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLQ_MMXq_IMMb,816,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 659*/ XED_DEF_INST(XED_ICLASS_PSLLQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLQ_XMMdq_IMMb,818,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 660*/ XED_DEF_INST(XED_ICLASS_PSLLQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLQ_MMXq_MEMq,820,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 661*/ XED_DEF_INST(XED_ICLASS_PSLLQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSLLQ_MMXq_MMXq,822,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/* 662*/ XED_DEF_INST(XED_ICLASS_PSLLQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLQ_XMMdq_MEMdq,824,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/* 663*/ XED_DEF_INST(XED_ICLASS_PSLLQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLQ_XMMdq_XMMdq,826,2,0,0,44,XED_EXCEPTION_SSE_TYPE_7), +/* 664*/ XED_DEF_INST(XED_ICLASS_PSRLDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSRLDQ_XMMdq_IMMb,828,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 665*/ XED_DEF_INST(XED_ICLASS_PSLLDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSLLDQ_XMMdq_IMMb,828,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 666*/ XED_DEF_INST(XED_ICLASS_FXSAVE,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_FXSAVE_MEMmfpxenv,830,2,0,0,45,XED_EXCEPTION_INVALID), +/* 667*/ XED_DEF_INST(XED_ICLASS_FXRSTOR,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_FXRSTOR_MEMmfpxenv,832,2,0,0,46,XED_EXCEPTION_INVALID), +/* 668*/ XED_DEF_INST(XED_ICLASS_FXSAVE64,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_FXSAVE64_MEMmfpxenv,830,2,0,0,45,XED_EXCEPTION_INVALID), +/* 669*/ XED_DEF_INST(XED_ICLASS_FXRSTOR64,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_FXRSTOR64_MEMmfpxenv,832,2,0,0,46,XED_EXCEPTION_INVALID), +/* 670*/ XED_DEF_INST(XED_ICLASS_LDMXCSR,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_LDMXCSR_MEMd,834,2,0,0,47,XED_EXCEPTION_SSE_TYPE_5), +/* 671*/ XED_DEF_INST(XED_ICLASS_STMXCSR,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_STMXCSR_MEMd,836,2,0,0,48,XED_EXCEPTION_SSE_TYPE_5), +/* 672*/ XED_DEF_INST(XED_ICLASS_PREFETCHNTA,XED_CATEGORY_PREFETCH,XED_EXTENSION_SSE,3,XED_IFORM_PREFETCHNTA_MEMmprefetch,838,1,0,0,49,XED_EXCEPTION_INVALID), +/* 673*/ XED_DEF_INST(XED_ICLASS_PREFETCHT0,XED_CATEGORY_PREFETCH,XED_EXTENSION_SSE,3,XED_IFORM_PREFETCHT0_MEMmprefetch,838,1,0,0,50,XED_EXCEPTION_INVALID), +/* 674*/ XED_DEF_INST(XED_ICLASS_PREFETCHT1,XED_CATEGORY_PREFETCH,XED_EXTENSION_SSE,3,XED_IFORM_PREFETCHT1_MEMmprefetch,838,1,0,0,50,XED_EXCEPTION_INVALID), +/* 675*/ XED_DEF_INST(XED_ICLASS_PREFETCHT2,XED_CATEGORY_PREFETCH,XED_EXTENSION_SSE,3,XED_IFORM_PREFETCHT2_MEMmprefetch,838,1,0,0,50,XED_EXCEPTION_INVALID), +/* 676*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r0,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 677*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r1,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 678*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r2,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 679*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r3,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 680*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_0F18r4,840,1,0,0,51,XED_EXCEPTION_INVALID), +/* 681*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r4,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 682*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_0F18r5,840,1,0,0,51,XED_EXCEPTION_INVALID), +/* 683*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r5,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 684*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r6,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 685*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_0F18r7,839,1,0,0,51,XED_EXCEPTION_INVALID), +/* 686*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_0F18r6,840,1,0,0,51,XED_EXCEPTION_INVALID), +/* 687*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_0F18r7,840,1,0,0,51,XED_EXCEPTION_INVALID), +/* 688*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F19,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 689*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F19,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 690*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1D,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 691*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1D,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 692*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1F,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 693*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1F,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 694*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_NOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_90,0,0,0,0,52,XED_EXCEPTION_INVALID), +/* 695*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_NOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_90,0,0,0,0,52,XED_EXCEPTION_INVALID), +/* 696*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F0D,843,2,0,0,14,XED_EXCEPTION_INVALID), +/* 697*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1A,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 698*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1B,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 699*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1B,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 700*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1A,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 701*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1B,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 702*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_MEMv_0F1A,845,2,0,0,51,XED_EXCEPTION_INVALID), +/* 703*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_MEM_0F1B,845,2,0,0,51,XED_EXCEPTION_INVALID), +/* 704*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1E,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 705*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 706*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 707*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 708*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 709*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 710*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 711*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 712*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 713*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 714*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 715*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 716*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 717*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 718*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 719*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 720*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 721*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 722*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 723*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1E,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 724*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 725*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 726*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 727*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 728*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 729*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 730*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 731*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 732*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 733*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 734*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_GPRv_GPRv_0F1C,843,2,0,0,51,XED_EXCEPTION_INVALID), +/* 735*/ XED_DEF_INST(XED_ICLASS_NOP,XED_CATEGORY_WIDENOP,XED_EXTENSION_BASE,3,XED_IFORM_NOP_MEMv_GPRv_0F1C,841,2,0,0,51,XED_EXCEPTION_INVALID), +/* 736*/ XED_DEF_INST(XED_ICLASS_VMCALL,XED_CATEGORY_VTX,XED_EXTENSION_VTX,3,XED_IFORM_VMCALL,847,1,29,0,1,XED_EXCEPTION_INVALID), +/* 737*/ XED_DEF_INST(XED_ICLASS_VMLAUNCH,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMLAUNCH,847,1,29,0,1,XED_EXCEPTION_INVALID), +/* 738*/ XED_DEF_INST(XED_ICLASS_VMRESUME,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMRESUME,847,1,29,0,1,XED_EXCEPTION_INVALID), +/* 739*/ XED_DEF_INST(XED_ICLASS_VMXOFF,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMXOFF,848,1,30,0,1,XED_EXCEPTION_INVALID), +/* 740*/ XED_DEF_INST(XED_ICLASS_SGDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SGDT_MEMs64,849,2,0,0,1,XED_EXCEPTION_INVALID), +/* 741*/ XED_DEF_INST(XED_ICLASS_SGDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SGDT_MEMs,851,2,0,0,34,XED_EXCEPTION_INVALID), +/* 742*/ XED_DEF_INST(XED_ICLASS_LIDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LIDT_MEMs64,853,2,0,0,35,XED_EXCEPTION_INVALID), +/* 743*/ XED_DEF_INST(XED_ICLASS_LIDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_LIDT_MEMs,855,2,0,0,53,XED_EXCEPTION_INVALID), +/* 744*/ XED_DEF_INST(XED_ICLASS_MONITOR,XED_CATEGORY_MISC,XED_EXTENSION_MONITOR,0,XED_IFORM_MONITOR,857,3,0,0,35,XED_EXCEPTION_INVALID), +/* 745*/ XED_DEF_INST(XED_ICLASS_MONITOR,XED_CATEGORY_MISC,XED_EXTENSION_MONITOR,0,XED_IFORM_MONITOR,860,3,0,0,35,XED_EXCEPTION_INVALID), +/* 746*/ XED_DEF_INST(XED_ICLASS_MONITOR,XED_CATEGORY_MISC,XED_EXTENSION_MONITOR,0,XED_IFORM_MONITOR,863,3,0,0,35,XED_EXCEPTION_INVALID), +/* 747*/ XED_DEF_INST(XED_ICLASS_MONITOR,XED_CATEGORY_MISC,XED_EXTENSION_MONITOR,0,XED_IFORM_MONITOR,863,3,0,0,35,XED_EXCEPTION_INVALID), +/* 748*/ XED_DEF_INST(XED_ICLASS_MWAIT,XED_CATEGORY_MISC,XED_EXTENSION_MONITOR,0,XED_IFORM_MWAIT,866,2,0,0,35,XED_EXCEPTION_INVALID), +/* 749*/ XED_DEF_INST(XED_ICLASS_SIDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SIDT_MEMs,868,2,0,0,34,XED_EXCEPTION_INVALID), +/* 750*/ XED_DEF_INST(XED_ICLASS_SIDT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_SIDT_MEMs64,870,2,0,0,0,XED_EXCEPTION_INVALID), +/* 751*/ XED_DEF_INST(XED_ICLASS_INVLPG,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_INVLPG_MEMb,872,1,0,0,54,XED_EXCEPTION_INVALID), +/* 752*/ XED_DEF_INST(XED_ICLASS_SWAPGS,XED_CATEGORY_SYSTEM,XED_EXTENSION_LONGMODE,0,XED_IFORM_SWAPGS,0,0,0,0,35,XED_EXCEPTION_INVALID), +/* 753*/ XED_DEF_INST(XED_ICLASS_RDTSCP,XED_CATEGORY_SYSTEM,XED_EXTENSION_RDTSCP,3,XED_IFORM_RDTSCP,873,5,0,0,0,XED_EXCEPTION_INVALID), +/* 754*/ XED_DEF_INST(XED_ICLASS_SFENCE,XED_CATEGORY_MISC,XED_EXTENSION_SSE,3,XED_IFORM_SFENCE,0,0,0,0,55,XED_EXCEPTION_INVALID), +/* 755*/ XED_DEF_INST(XED_ICLASS_CLFLUSH,XED_CATEGORY_MISC,XED_EXTENSION_CLFSH,3,XED_IFORM_CLFLUSH_MEMmprefetch,838,1,0,0,1,XED_EXCEPTION_INVALID), +/* 756*/ XED_DEF_INST(XED_ICLASS_LFENCE,XED_CATEGORY_MISC,XED_EXTENSION_SSE2,3,XED_IFORM_LFENCE,0,0,0,0,55,XED_EXCEPTION_INVALID), +/* 757*/ XED_DEF_INST(XED_ICLASS_MFENCE,XED_CATEGORY_MISC,XED_EXTENSION_SSE2,3,XED_IFORM_MFENCE,0,0,0,0,55,XED_EXCEPTION_INVALID), +/* 758*/ XED_DEF_INST(XED_ICLASS_MOVHLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVHLPS_XMMq_XMMq,878,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 759*/ XED_DEF_INST(XED_ICLASS_MOVLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVLPS_XMMq_MEMq,880,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/* 760*/ XED_DEF_INST(XED_ICLASS_MOVLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVLPS_MEMq_XMMq,882,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/* 761*/ XED_DEF_INST(XED_ICLASS_MOVLHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVLHPS_XMMq_XMMq,878,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/* 762*/ XED_DEF_INST(XED_ICLASS_MOVHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVHPS_XMMq_MEMq,880,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/* 763*/ XED_DEF_INST(XED_ICLASS_MOVHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVHPS_MEMq_XMMps,884,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/* 764*/ XED_DEF_INST(XED_ICLASS_DAA,XED_CATEGORY_DECIMAL,XED_EXTENSION_BASE,3,XED_IFORM_DAA,886,2,31,0,0,XED_EXCEPTION_INVALID), +/* 765*/ XED_DEF_INST(XED_ICLASS_DAS,XED_CATEGORY_DECIMAL,XED_EXTENSION_BASE,3,XED_IFORM_DAS,886,2,31,0,0,XED_EXCEPTION_INVALID), +/* 766*/ XED_DEF_INST(XED_ICLASS_AAA,XED_CATEGORY_DECIMAL,XED_EXTENSION_BASE,3,XED_IFORM_AAA,888,3,32,0,0,XED_EXCEPTION_INVALID), +/* 767*/ XED_DEF_INST(XED_ICLASS_AAS,XED_CATEGORY_DECIMAL,XED_EXTENSION_BASE,3,XED_IFORM_AAS,888,3,32,0,0,XED_EXCEPTION_INVALID), +/* 768*/ XED_DEF_INST(XED_ICLASS_PUSHA,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHA,891,11,0,0,29,XED_EXCEPTION_INVALID), +/* 769*/ XED_DEF_INST(XED_ICLASS_PUSHA,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHA,891,11,0,0,29,XED_EXCEPTION_INVALID), +/* 770*/ XED_DEF_INST(XED_ICLASS_PUSHAD,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHAD,902,11,0,0,29,XED_EXCEPTION_INVALID), +/* 771*/ XED_DEF_INST(XED_ICLASS_PUSHAD,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHAD,902,11,0,0,29,XED_EXCEPTION_INVALID), +/* 772*/ XED_DEF_INST(XED_ICLASS_POPA,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPA,913,10,0,0,16,XED_EXCEPTION_INVALID), +/* 773*/ XED_DEF_INST(XED_ICLASS_POPA,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPA,913,10,0,0,16,XED_EXCEPTION_INVALID), +/* 774*/ XED_DEF_INST(XED_ICLASS_POPAD,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPAD,923,10,0,0,16,XED_EXCEPTION_INVALID), +/* 775*/ XED_DEF_INST(XED_ICLASS_POPAD,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPAD,923,10,0,0,16,XED_EXCEPTION_INVALID), +/* 776*/ XED_DEF_INST(XED_ICLASS_BOUND,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_BOUND_GPRv_MEMa16,933,2,0,0,56,XED_EXCEPTION_INVALID), +/* 777*/ XED_DEF_INST(XED_ICLASS_BOUND,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_BOUND_GPRv_MEMa16,933,2,0,0,56,XED_EXCEPTION_INVALID), +/* 778*/ XED_DEF_INST(XED_ICLASS_BOUND,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_BOUND_GPRv_MEMa32,935,2,0,0,56,XED_EXCEPTION_INVALID), +/* 779*/ XED_DEF_INST(XED_ICLASS_BOUND,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_BOUND_GPRv_MEMa32,935,2,0,0,56,XED_EXCEPTION_INVALID), +/* 780*/ XED_DEF_INST(XED_ICLASS_ARPL,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_ARPL_MEMw_GPR16,937,3,26,0,33,XED_EXCEPTION_INVALID), +/* 781*/ XED_DEF_INST(XED_ICLASS_ARPL,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_ARPL_GPR16_GPR16,940,3,26,0,33,XED_EXCEPTION_INVALID), +/* 782*/ XED_DEF_INST(XED_ICLASS_MOVSXD,XED_CATEGORY_DATAXFER,XED_EXTENSION_LONGMODE,3,XED_IFORM_MOVSXD_GPRv_MEMz,943,2,0,0,14,XED_EXCEPTION_INVALID), +/* 783*/ XED_DEF_INST(XED_ICLASS_MOVSXD,XED_CATEGORY_DATAXFER,XED_EXTENSION_LONGMODE,3,XED_IFORM_MOVSXD_GPRv_GPRz,945,2,0,0,14,XED_EXCEPTION_INVALID), +/* 784*/ XED_DEF_INST(XED_ICLASS_REP_INSB,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSB,947,5,33,0,57,XED_EXCEPTION_INVALID), +/* 785*/ XED_DEF_INST(XED_ICLASS_REP_INSB,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSB,947,5,33,0,57,XED_EXCEPTION_INVALID), +/* 786*/ XED_DEF_INST(XED_ICLASS_INSB,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSB,952,4,33,0,58,XED_EXCEPTION_INVALID), +/* 787*/ XED_DEF_INST(XED_ICLASS_REP_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSW,956,5,33,0,59,XED_EXCEPTION_INVALID), +/* 788*/ XED_DEF_INST(XED_ICLASS_REP_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSW,956,5,33,0,59,XED_EXCEPTION_INVALID), +/* 789*/ XED_DEF_INST(XED_ICLASS_REP_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSW,956,5,33,0,59,XED_EXCEPTION_INVALID), +/* 790*/ XED_DEF_INST(XED_ICLASS_REP_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSW,956,5,33,0,59,XED_EXCEPTION_INVALID), +/* 791*/ XED_DEF_INST(XED_ICLASS_REP_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSW,956,5,33,0,59,XED_EXCEPTION_INVALID), +/* 792*/ XED_DEF_INST(XED_ICLASS_REP_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSW,956,5,33,0,59,XED_EXCEPTION_INVALID), +/* 793*/ XED_DEF_INST(XED_ICLASS_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSW,961,4,33,0,60,XED_EXCEPTION_INVALID), +/* 794*/ XED_DEF_INST(XED_ICLASS_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSW,961,4,33,0,60,XED_EXCEPTION_INVALID), +/* 795*/ XED_DEF_INST(XED_ICLASS_INSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSW,961,4,33,0,60,XED_EXCEPTION_INVALID), +/* 796*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 797*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 798*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 799*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 800*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 801*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 802*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 803*/ XED_DEF_INST(XED_ICLASS_REP_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_INSD,965,5,33,0,59,XED_EXCEPTION_INVALID), +/* 804*/ XED_DEF_INST(XED_ICLASS_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSD,970,4,33,0,60,XED_EXCEPTION_INVALID), +/* 805*/ XED_DEF_INST(XED_ICLASS_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSD,970,4,33,0,60,XED_EXCEPTION_INVALID), +/* 806*/ XED_DEF_INST(XED_ICLASS_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSD,970,4,33,0,60,XED_EXCEPTION_INVALID), +/* 807*/ XED_DEF_INST(XED_ICLASS_INSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_INSD,970,4,33,0,60,XED_EXCEPTION_INVALID), +/* 808*/ XED_DEF_INST(XED_ICLASS_REP_OUTSB,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSB,974,5,33,0,57,XED_EXCEPTION_INVALID), +/* 809*/ XED_DEF_INST(XED_ICLASS_REP_OUTSB,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSB,974,5,33,0,57,XED_EXCEPTION_INVALID), +/* 810*/ XED_DEF_INST(XED_ICLASS_OUTSB,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSB,979,4,33,0,58,XED_EXCEPTION_INVALID), +/* 811*/ XED_DEF_INST(XED_ICLASS_REP_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSW,983,5,33,0,59,XED_EXCEPTION_INVALID), +/* 812*/ XED_DEF_INST(XED_ICLASS_REP_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSW,983,5,33,0,59,XED_EXCEPTION_INVALID), +/* 813*/ XED_DEF_INST(XED_ICLASS_REP_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSW,983,5,33,0,59,XED_EXCEPTION_INVALID), +/* 814*/ XED_DEF_INST(XED_ICLASS_REP_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSW,983,5,33,0,59,XED_EXCEPTION_INVALID), +/* 815*/ XED_DEF_INST(XED_ICLASS_REP_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSW,983,5,33,0,59,XED_EXCEPTION_INVALID), +/* 816*/ XED_DEF_INST(XED_ICLASS_REP_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSW,983,5,33,0,59,XED_EXCEPTION_INVALID), +/* 817*/ XED_DEF_INST(XED_ICLASS_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSW,988,4,33,0,60,XED_EXCEPTION_INVALID), +/* 818*/ XED_DEF_INST(XED_ICLASS_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSW,988,4,33,0,60,XED_EXCEPTION_INVALID), +/* 819*/ XED_DEF_INST(XED_ICLASS_OUTSW,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSW,988,4,33,0,60,XED_EXCEPTION_INVALID), +/* 820*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 821*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 822*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 823*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 824*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 825*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 826*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 827*/ XED_DEF_INST(XED_ICLASS_REP_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_OUTSD,992,5,33,0,59,XED_EXCEPTION_INVALID), +/* 828*/ XED_DEF_INST(XED_ICLASS_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSD,997,4,33,0,60,XED_EXCEPTION_INVALID), +/* 829*/ XED_DEF_INST(XED_ICLASS_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSD,997,4,33,0,60,XED_EXCEPTION_INVALID), +/* 830*/ XED_DEF_INST(XED_ICLASS_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSD,997,4,33,0,60,XED_EXCEPTION_INVALID), +/* 831*/ XED_DEF_INST(XED_ICLASS_OUTSD,XED_CATEGORY_IOSTRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_OUTSD,997,4,33,0,60,XED_EXCEPTION_INVALID), +/* 832*/ XED_DEF_INST(XED_ICLASS_JO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JO_RELBRb,1001,3,34,0,25,XED_EXCEPTION_INVALID), +/* 833*/ XED_DEF_INST(XED_ICLASS_JO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JO_RELBRb,1004,3,34,0,25,XED_EXCEPTION_INVALID), +/* 834*/ XED_DEF_INST(XED_ICLASS_JO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JO_RELBRd,1007,3,34,0,25,XED_EXCEPTION_INVALID), +/* 835*/ XED_DEF_INST(XED_ICLASS_JO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JO_RELBRz,1010,3,34,0,61,XED_EXCEPTION_INVALID), +/* 836*/ XED_DEF_INST(XED_ICLASS_JNO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNO_RELBRb,1001,3,34,0,25,XED_EXCEPTION_INVALID), +/* 837*/ XED_DEF_INST(XED_ICLASS_JNO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNO_RELBRb,1004,3,34,0,25,XED_EXCEPTION_INVALID), +/* 838*/ XED_DEF_INST(XED_ICLASS_JNO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNO_RELBRz,1010,3,34,0,61,XED_EXCEPTION_INVALID), +/* 839*/ XED_DEF_INST(XED_ICLASS_JNO,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNO_RELBRd,1007,3,34,0,25,XED_EXCEPTION_INVALID), +/* 840*/ XED_DEF_INST(XED_ICLASS_JB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JB_RELBRb,1001,3,35,0,25,XED_EXCEPTION_INVALID), +/* 841*/ XED_DEF_INST(XED_ICLASS_JB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JB_RELBRb,1004,3,35,0,25,XED_EXCEPTION_INVALID), +/* 842*/ XED_DEF_INST(XED_ICLASS_JB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JB_RELBRz,1010,3,35,0,61,XED_EXCEPTION_INVALID), +/* 843*/ XED_DEF_INST(XED_ICLASS_JB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JB_RELBRd,1007,3,35,0,25,XED_EXCEPTION_INVALID), +/* 844*/ XED_DEF_INST(XED_ICLASS_JNB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNB_RELBRb,1001,3,35,0,25,XED_EXCEPTION_INVALID), +/* 845*/ XED_DEF_INST(XED_ICLASS_JNB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNB_RELBRb,1004,3,35,0,25,XED_EXCEPTION_INVALID), +/* 846*/ XED_DEF_INST(XED_ICLASS_JNB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNB_RELBRz,1010,3,35,0,61,XED_EXCEPTION_INVALID), +/* 847*/ XED_DEF_INST(XED_ICLASS_JNB,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNB_RELBRd,1007,3,35,0,25,XED_EXCEPTION_INVALID), +/* 848*/ XED_DEF_INST(XED_ICLASS_JZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JZ_RELBRb,1001,3,36,0,25,XED_EXCEPTION_INVALID), +/* 849*/ XED_DEF_INST(XED_ICLASS_JZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JZ_RELBRb,1004,3,36,0,25,XED_EXCEPTION_INVALID), +/* 850*/ XED_DEF_INST(XED_ICLASS_JZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JZ_RELBRz,1010,3,36,0,61,XED_EXCEPTION_INVALID), +/* 851*/ XED_DEF_INST(XED_ICLASS_JZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JZ_RELBRd,1007,3,36,0,25,XED_EXCEPTION_INVALID), +/* 852*/ XED_DEF_INST(XED_ICLASS_JNZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNZ_RELBRb,1001,3,36,0,25,XED_EXCEPTION_INVALID), +/* 853*/ XED_DEF_INST(XED_ICLASS_JNZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNZ_RELBRb,1004,3,36,0,25,XED_EXCEPTION_INVALID), +/* 854*/ XED_DEF_INST(XED_ICLASS_JNZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNZ_RELBRz,1010,3,36,0,61,XED_EXCEPTION_INVALID), +/* 855*/ XED_DEF_INST(XED_ICLASS_JNZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNZ_RELBRd,1007,3,36,0,25,XED_EXCEPTION_INVALID), +/* 856*/ XED_DEF_INST(XED_ICLASS_JBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JBE_RELBRb,1001,3,37,0,25,XED_EXCEPTION_INVALID), +/* 857*/ XED_DEF_INST(XED_ICLASS_JBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JBE_RELBRb,1004,3,37,0,25,XED_EXCEPTION_INVALID), +/* 858*/ XED_DEF_INST(XED_ICLASS_JBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JBE_RELBRz,1010,3,37,0,61,XED_EXCEPTION_INVALID), +/* 859*/ XED_DEF_INST(XED_ICLASS_JBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JBE_RELBRd,1007,3,37,0,25,XED_EXCEPTION_INVALID), +/* 860*/ XED_DEF_INST(XED_ICLASS_JNBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNBE_RELBRb,1001,3,37,0,25,XED_EXCEPTION_INVALID), +/* 861*/ XED_DEF_INST(XED_ICLASS_JNBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNBE_RELBRb,1004,3,37,0,25,XED_EXCEPTION_INVALID), +/* 862*/ XED_DEF_INST(XED_ICLASS_JNBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNBE_RELBRz,1010,3,37,0,61,XED_EXCEPTION_INVALID), +/* 863*/ XED_DEF_INST(XED_ICLASS_JNBE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNBE_RELBRd,1007,3,37,0,25,XED_EXCEPTION_INVALID), +/* 864*/ XED_DEF_INST(XED_ICLASS_JS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JS_RELBRb,1001,3,38,0,25,XED_EXCEPTION_INVALID), +/* 865*/ XED_DEF_INST(XED_ICLASS_JS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JS_RELBRb,1004,3,38,0,25,XED_EXCEPTION_INVALID), +/* 866*/ XED_DEF_INST(XED_ICLASS_JS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JS_RELBRz,1010,3,38,0,61,XED_EXCEPTION_INVALID), +/* 867*/ XED_DEF_INST(XED_ICLASS_JS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JS_RELBRd,1007,3,38,0,25,XED_EXCEPTION_INVALID), +/* 868*/ XED_DEF_INST(XED_ICLASS_JNS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNS_RELBRb,1001,3,38,0,25,XED_EXCEPTION_INVALID), +/* 869*/ XED_DEF_INST(XED_ICLASS_JNS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNS_RELBRb,1004,3,38,0,25,XED_EXCEPTION_INVALID), +/* 870*/ XED_DEF_INST(XED_ICLASS_JNS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNS_RELBRz,1010,3,38,0,61,XED_EXCEPTION_INVALID), +/* 871*/ XED_DEF_INST(XED_ICLASS_JNS,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNS_RELBRd,1007,3,38,0,25,XED_EXCEPTION_INVALID), +/* 872*/ XED_DEF_INST(XED_ICLASS_JP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JP_RELBRb,1001,3,39,0,25,XED_EXCEPTION_INVALID), +/* 873*/ XED_DEF_INST(XED_ICLASS_JP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JP_RELBRb,1004,3,39,0,25,XED_EXCEPTION_INVALID), +/* 874*/ XED_DEF_INST(XED_ICLASS_JP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JP_RELBRz,1010,3,39,0,61,XED_EXCEPTION_INVALID), +/* 875*/ XED_DEF_INST(XED_ICLASS_JP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JP_RELBRd,1007,3,39,0,25,XED_EXCEPTION_INVALID), +/* 876*/ XED_DEF_INST(XED_ICLASS_JNP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNP_RELBRb,1001,3,39,0,25,XED_EXCEPTION_INVALID), +/* 877*/ XED_DEF_INST(XED_ICLASS_JNP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNP_RELBRb,1004,3,39,0,25,XED_EXCEPTION_INVALID), +/* 878*/ XED_DEF_INST(XED_ICLASS_JNP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNP_RELBRz,1010,3,39,0,61,XED_EXCEPTION_INVALID), +/* 879*/ XED_DEF_INST(XED_ICLASS_JNP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNP_RELBRd,1007,3,39,0,25,XED_EXCEPTION_INVALID), +/* 880*/ XED_DEF_INST(XED_ICLASS_JL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JL_RELBRb,1001,3,40,0,25,XED_EXCEPTION_INVALID), +/* 881*/ XED_DEF_INST(XED_ICLASS_JL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JL_RELBRb,1004,3,40,0,25,XED_EXCEPTION_INVALID), +/* 882*/ XED_DEF_INST(XED_ICLASS_JL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JL_RELBRz,1010,3,40,0,61,XED_EXCEPTION_INVALID), +/* 883*/ XED_DEF_INST(XED_ICLASS_JL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JL_RELBRd,1007,3,40,0,25,XED_EXCEPTION_INVALID), +/* 884*/ XED_DEF_INST(XED_ICLASS_JNL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNL_RELBRb,1001,3,40,0,25,XED_EXCEPTION_INVALID), +/* 885*/ XED_DEF_INST(XED_ICLASS_JNL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNL_RELBRb,1004,3,40,0,25,XED_EXCEPTION_INVALID), +/* 886*/ XED_DEF_INST(XED_ICLASS_JNL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNL_RELBRz,1010,3,40,0,61,XED_EXCEPTION_INVALID), +/* 887*/ XED_DEF_INST(XED_ICLASS_JNL,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNL_RELBRd,1007,3,40,0,25,XED_EXCEPTION_INVALID), +/* 888*/ XED_DEF_INST(XED_ICLASS_JLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JLE_RELBRb,1001,3,41,0,25,XED_EXCEPTION_INVALID), +/* 889*/ XED_DEF_INST(XED_ICLASS_JLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JLE_RELBRb,1004,3,41,0,25,XED_EXCEPTION_INVALID), +/* 890*/ XED_DEF_INST(XED_ICLASS_JLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JLE_RELBRz,1010,3,41,0,61,XED_EXCEPTION_INVALID), +/* 891*/ XED_DEF_INST(XED_ICLASS_JLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JLE_RELBRd,1007,3,41,0,25,XED_EXCEPTION_INVALID), +/* 892*/ XED_DEF_INST(XED_ICLASS_JNLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNLE_RELBRb,1001,3,41,0,25,XED_EXCEPTION_INVALID), +/* 893*/ XED_DEF_INST(XED_ICLASS_JNLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNLE_RELBRb,1004,3,41,0,25,XED_EXCEPTION_INVALID), +/* 894*/ XED_DEF_INST(XED_ICLASS_JNLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNLE_RELBRz,1010,3,41,0,61,XED_EXCEPTION_INVALID), +/* 895*/ XED_DEF_INST(XED_ICLASS_JNLE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JNLE_RELBRd,1007,3,41,0,25,XED_EXCEPTION_INVALID), +/* 896*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_MEMb_GPR8,1013,2,0,0,9,XED_EXCEPTION_INVALID), +/* 897*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_MEMb_GPR8,1013,2,0,0,9,XED_EXCEPTION_INVALID), +/* 898*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_GPR8_GPR8,1015,2,0,0,12,XED_EXCEPTION_INVALID), +/* 899*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_MEMv_GPRv,1017,2,0,0,10,XED_EXCEPTION_INVALID), +/* 900*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_MEMv_GPRv,1017,2,0,0,10,XED_EXCEPTION_INVALID), +/* 901*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_GPRv_GPRv,1019,2,0,0,14,XED_EXCEPTION_INVALID), +/* 902*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_GPRv_OrAX,1021,2,0,0,14,XED_EXCEPTION_INVALID), +/* 903*/ XED_DEF_INST(XED_ICLASS_XCHG,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_XCHG_GPRv_OrAX,1021,2,0,0,14,XED_EXCEPTION_INVALID), +/* 904*/ XED_DEF_INST(XED_ICLASS_LEA,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_LEA_GPRv_AGEN,1023,2,0,0,14,XED_EXCEPTION_INVALID), +/* 905*/ XED_DEF_INST(XED_ICLASS_PAUSE,XED_CATEGORY_MISC,XED_EXTENSION_PAUSE,3,XED_IFORM_PAUSE,0,0,0,0,1,XED_EXCEPTION_INVALID), +/* 906*/ XED_DEF_INST(XED_ICLASS_CBW,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CBW,1025,2,0,0,0,XED_EXCEPTION_INVALID), +/* 907*/ XED_DEF_INST(XED_ICLASS_CBW,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CBW,1025,2,0,0,0,XED_EXCEPTION_INVALID), +/* 908*/ XED_DEF_INST(XED_ICLASS_CBW,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CBW,1025,2,0,0,0,XED_EXCEPTION_INVALID), +/* 909*/ XED_DEF_INST(XED_ICLASS_CDQE,XED_CATEGORY_CONVERT,XED_EXTENSION_LONGMODE,3,XED_IFORM_CDQE,1027,2,0,0,0,XED_EXCEPTION_INVALID), +/* 910*/ XED_DEF_INST(XED_ICLASS_CWDE,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CWDE,1029,2,0,0,0,XED_EXCEPTION_INVALID), +/* 911*/ XED_DEF_INST(XED_ICLASS_CWDE,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CWDE,1029,2,0,0,0,XED_EXCEPTION_INVALID), +/* 912*/ XED_DEF_INST(XED_ICLASS_CWDE,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CWDE,1029,2,0,0,0,XED_EXCEPTION_INVALID), +/* 913*/ XED_DEF_INST(XED_ICLASS_CWD,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CWD,1031,2,0,0,0,XED_EXCEPTION_INVALID), +/* 914*/ XED_DEF_INST(XED_ICLASS_CWD,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CWD,1031,2,0,0,0,XED_EXCEPTION_INVALID), +/* 915*/ XED_DEF_INST(XED_ICLASS_CWD,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CWD,1031,2,0,0,0,XED_EXCEPTION_INVALID), +/* 916*/ XED_DEF_INST(XED_ICLASS_CQO,XED_CATEGORY_CONVERT,XED_EXTENSION_LONGMODE,3,XED_IFORM_CQO,1033,2,0,0,0,XED_EXCEPTION_INVALID), +/* 917*/ XED_DEF_INST(XED_ICLASS_CDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CDQ,1035,2,0,0,0,XED_EXCEPTION_INVALID), +/* 918*/ XED_DEF_INST(XED_ICLASS_CDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CDQ,1035,2,0,0,0,XED_EXCEPTION_INVALID), +/* 919*/ XED_DEF_INST(XED_ICLASS_CDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_BASE,3,XED_IFORM_CDQ,1035,2,0,0,0,XED_EXCEPTION_INVALID), +/* 920*/ XED_DEF_INST(XED_ICLASS_CALL_FAR,XED_CATEGORY_CALL,XED_EXTENSION_BASE,3,XED_IFORM_CALL_FAR_MEMp2,1037,5,0,0,62,XED_EXCEPTION_INVALID), +/* 921*/ XED_DEF_INST(XED_ICLASS_CALL_FAR,XED_CATEGORY_CALL,XED_EXTENSION_BASE,3,XED_IFORM_CALL_FAR_PTRp_IMMw,1042,6,0,0,63,XED_EXCEPTION_INVALID), +/* 922*/ XED_DEF_INST(XED_ICLASS_FWAIT,XED_CATEGORY_X87_ALU,XED_EXTENSION_X87,3,XED_IFORM_FWAIT,0,0,0,0,2,XED_EXCEPTION_INVALID), +/* 923*/ XED_DEF_INST(XED_ICLASS_PUSHF,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHF,1048,4,42,0,64,XED_EXCEPTION_INVALID), +/* 924*/ XED_DEF_INST(XED_ICLASS_PUSHF,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHF,1048,4,42,0,64,XED_EXCEPTION_INVALID), +/* 925*/ XED_DEF_INST(XED_ICLASS_PUSHF,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHF,1048,4,42,0,64,XED_EXCEPTION_INVALID), +/* 926*/ XED_DEF_INST(XED_ICLASS_PUSHFD,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHFD,1052,4,42,0,64,XED_EXCEPTION_INVALID), +/* 927*/ XED_DEF_INST(XED_ICLASS_PUSHFD,XED_CATEGORY_PUSH,XED_EXTENSION_BASE,3,XED_IFORM_PUSHFD,1052,4,42,0,64,XED_EXCEPTION_INVALID), +/* 928*/ XED_DEF_INST(XED_ICLASS_PUSHFQ,XED_CATEGORY_PUSH,XED_EXTENSION_LONGMODE,3,XED_IFORM_PUSHFQ,1056,4,42,0,64,XED_EXCEPTION_INVALID), +/* 929*/ XED_DEF_INST(XED_ICLASS_PUSHFQ,XED_CATEGORY_PUSH,XED_EXTENSION_LONGMODE,3,XED_IFORM_PUSHFQ,1056,4,42,0,64,XED_EXCEPTION_INVALID), +/* 930*/ XED_DEF_INST(XED_ICLASS_POPF,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPF,1060,4,43,0,65,XED_EXCEPTION_INVALID), +/* 931*/ XED_DEF_INST(XED_ICLASS_POPF,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPF,1060,4,43,0,65,XED_EXCEPTION_INVALID), +/* 932*/ XED_DEF_INST(XED_ICLASS_POPF,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPF,1060,4,43,0,65,XED_EXCEPTION_INVALID), +/* 933*/ XED_DEF_INST(XED_ICLASS_POPFD,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPFD,1064,4,43,0,65,XED_EXCEPTION_INVALID), +/* 934*/ XED_DEF_INST(XED_ICLASS_POPFD,XED_CATEGORY_POP,XED_EXTENSION_BASE,3,XED_IFORM_POPFD,1064,4,43,0,65,XED_EXCEPTION_INVALID), +/* 935*/ XED_DEF_INST(XED_ICLASS_POPFQ,XED_CATEGORY_POP,XED_EXTENSION_LONGMODE,3,XED_IFORM_POPFQ,1068,4,43,0,65,XED_EXCEPTION_INVALID), +/* 936*/ XED_DEF_INST(XED_ICLASS_POPFQ,XED_CATEGORY_POP,XED_EXTENSION_LONGMODE,3,XED_IFORM_POPFQ,1068,4,43,0,65,XED_EXCEPTION_INVALID), +/* 937*/ XED_DEF_INST(XED_ICLASS_SAHF,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_SAHF,1072,2,44,0,0,XED_EXCEPTION_INVALID), +/* 938*/ XED_DEF_INST(XED_ICLASS_LAHF,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_LAHF,1074,2,45,0,0,XED_EXCEPTION_INVALID), +/* 939*/ XED_DEF_INST(XED_ICLASS_REP_MOVSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSB,1076,6,46,0,66,XED_EXCEPTION_INVALID), +/* 940*/ XED_DEF_INST(XED_ICLASS_REP_MOVSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSB,1076,6,46,0,66,XED_EXCEPTION_INVALID), +/* 941*/ XED_DEF_INST(XED_ICLASS_MOVSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSB,1082,5,46,0,67,XED_EXCEPTION_INVALID), +/* 942*/ XED_DEF_INST(XED_ICLASS_REP_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSW,1087,6,46,0,68,XED_EXCEPTION_INVALID), +/* 943*/ XED_DEF_INST(XED_ICLASS_REP_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSW,1087,6,46,0,68,XED_EXCEPTION_INVALID), +/* 944*/ XED_DEF_INST(XED_ICLASS_REP_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSW,1087,6,46,0,68,XED_EXCEPTION_INVALID), +/* 945*/ XED_DEF_INST(XED_ICLASS_REP_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSW,1087,6,46,0,68,XED_EXCEPTION_INVALID), +/* 946*/ XED_DEF_INST(XED_ICLASS_REP_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSW,1087,6,46,0,68,XED_EXCEPTION_INVALID), +/* 947*/ XED_DEF_INST(XED_ICLASS_REP_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSW,1087,6,46,0,68,XED_EXCEPTION_INVALID), +/* 948*/ XED_DEF_INST(XED_ICLASS_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSW,1093,5,46,0,69,XED_EXCEPTION_INVALID), +/* 949*/ XED_DEF_INST(XED_ICLASS_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSW,1093,5,46,0,69,XED_EXCEPTION_INVALID), +/* 950*/ XED_DEF_INST(XED_ICLASS_MOVSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSW,1093,5,46,0,69,XED_EXCEPTION_INVALID), +/* 951*/ XED_DEF_INST(XED_ICLASS_REP_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSD,1098,6,46,0,68,XED_EXCEPTION_INVALID), +/* 952*/ XED_DEF_INST(XED_ICLASS_REP_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSD,1098,6,46,0,68,XED_EXCEPTION_INVALID), +/* 953*/ XED_DEF_INST(XED_ICLASS_REP_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSD,1098,6,46,0,68,XED_EXCEPTION_INVALID), +/* 954*/ XED_DEF_INST(XED_ICLASS_REP_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSD,1098,6,46,0,68,XED_EXCEPTION_INVALID), +/* 955*/ XED_DEF_INST(XED_ICLASS_REP_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSD,1098,6,46,0,68,XED_EXCEPTION_INVALID), +/* 956*/ XED_DEF_INST(XED_ICLASS_REP_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_MOVSD,1098,6,46,0,68,XED_EXCEPTION_INVALID), +/* 957*/ XED_DEF_INST(XED_ICLASS_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSD,1104,5,46,0,69,XED_EXCEPTION_INVALID), +/* 958*/ XED_DEF_INST(XED_ICLASS_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSD,1104,5,46,0,69,XED_EXCEPTION_INVALID), +/* 959*/ XED_DEF_INST(XED_ICLASS_MOVSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_MOVSD,1104,5,46,0,69,XED_EXCEPTION_INVALID), +/* 960*/ XED_DEF_INST(XED_ICLASS_REP_MOVSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REP_MOVSQ,1109,6,46,0,68,XED_EXCEPTION_INVALID), +/* 961*/ XED_DEF_INST(XED_ICLASS_REP_MOVSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REP_MOVSQ,1109,6,46,0,68,XED_EXCEPTION_INVALID), +/* 962*/ XED_DEF_INST(XED_ICLASS_MOVSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_MOVSQ,1115,5,46,0,69,XED_EXCEPTION_INVALID), +/* 963*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSB,1120,6,47,0,66,XED_EXCEPTION_INVALID), +/* 964*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSB,1120,6,47,0,66,XED_EXCEPTION_INVALID), +/* 965*/ XED_DEF_INST(XED_ICLASS_CMPSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSB,1126,5,48,0,67,XED_EXCEPTION_INVALID), +/* 966*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSW,1131,6,47,0,68,XED_EXCEPTION_INVALID), +/* 967*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSW,1131,6,47,0,68,XED_EXCEPTION_INVALID), +/* 968*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSW,1131,6,47,0,68,XED_EXCEPTION_INVALID), +/* 969*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSW,1131,6,47,0,68,XED_EXCEPTION_INVALID), +/* 970*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSW,1131,6,47,0,68,XED_EXCEPTION_INVALID), +/* 971*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSW,1131,6,47,0,68,XED_EXCEPTION_INVALID), +/* 972*/ XED_DEF_INST(XED_ICLASS_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSW,1137,5,48,0,69,XED_EXCEPTION_INVALID), +/* 973*/ XED_DEF_INST(XED_ICLASS_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSW,1137,5,48,0,69,XED_EXCEPTION_INVALID), +/* 974*/ XED_DEF_INST(XED_ICLASS_CMPSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSW,1137,5,48,0,69,XED_EXCEPTION_INVALID), +/* 975*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSD,1142,6,47,0,68,XED_EXCEPTION_INVALID), +/* 976*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSD,1142,6,47,0,68,XED_EXCEPTION_INVALID), +/* 977*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_CMPSD,1142,6,47,0,68,XED_EXCEPTION_INVALID), +/* 978*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSD,1142,6,47,0,68,XED_EXCEPTION_INVALID), +/* 979*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSD,1142,6,47,0,68,XED_EXCEPTION_INVALID), +/* 980*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_CMPSD,1142,6,47,0,68,XED_EXCEPTION_INVALID), +/* 981*/ XED_DEF_INST(XED_ICLASS_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSD,1148,5,48,0,69,XED_EXCEPTION_INVALID), +/* 982*/ XED_DEF_INST(XED_ICLASS_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSD,1148,5,48,0,69,XED_EXCEPTION_INVALID), +/* 983*/ XED_DEF_INST(XED_ICLASS_CMPSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMPSD,1148,5,48,0,69,XED_EXCEPTION_INVALID), +/* 984*/ XED_DEF_INST(XED_ICLASS_REPE_CMPSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REPE_CMPSQ,1153,6,47,0,68,XED_EXCEPTION_INVALID), +/* 985*/ XED_DEF_INST(XED_ICLASS_REPNE_CMPSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REPNE_CMPSQ,1153,6,47,0,68,XED_EXCEPTION_INVALID), +/* 986*/ XED_DEF_INST(XED_ICLASS_CMPSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_CMPSQ,1159,5,48,0,69,XED_EXCEPTION_INVALID), +/* 987*/ XED_DEF_INST(XED_ICLASS_REP_STOSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSB,1164,5,46,0,70,XED_EXCEPTION_INVALID), +/* 988*/ XED_DEF_INST(XED_ICLASS_REP_STOSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSB,1164,5,46,0,70,XED_EXCEPTION_INVALID), +/* 989*/ XED_DEF_INST(XED_ICLASS_STOSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSB,1169,4,46,0,42,XED_EXCEPTION_INVALID), +/* 990*/ XED_DEF_INST(XED_ICLASS_REP_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSW,1173,5,46,0,71,XED_EXCEPTION_INVALID), +/* 991*/ XED_DEF_INST(XED_ICLASS_REP_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSW,1173,5,46,0,71,XED_EXCEPTION_INVALID), +/* 992*/ XED_DEF_INST(XED_ICLASS_REP_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSW,1173,5,46,0,71,XED_EXCEPTION_INVALID), +/* 993*/ XED_DEF_INST(XED_ICLASS_REP_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSW,1173,5,46,0,71,XED_EXCEPTION_INVALID), +/* 994*/ XED_DEF_INST(XED_ICLASS_REP_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSW,1173,5,46,0,71,XED_EXCEPTION_INVALID), +/* 995*/ XED_DEF_INST(XED_ICLASS_REP_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSW,1173,5,46,0,71,XED_EXCEPTION_INVALID), +/* 996*/ XED_DEF_INST(XED_ICLASS_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSW,1178,4,46,0,72,XED_EXCEPTION_INVALID), +/* 997*/ XED_DEF_INST(XED_ICLASS_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSW,1178,4,46,0,72,XED_EXCEPTION_INVALID), +/* 998*/ XED_DEF_INST(XED_ICLASS_STOSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSW,1178,4,46,0,72,XED_EXCEPTION_INVALID), +/* 999*/ XED_DEF_INST(XED_ICLASS_REP_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSD,1182,5,46,0,71,XED_EXCEPTION_INVALID), +/*1000*/ XED_DEF_INST(XED_ICLASS_REP_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSD,1182,5,46,0,71,XED_EXCEPTION_INVALID), +/*1001*/ XED_DEF_INST(XED_ICLASS_REP_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSD,1182,5,46,0,71,XED_EXCEPTION_INVALID), +/*1002*/ XED_DEF_INST(XED_ICLASS_REP_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSD,1182,5,46,0,71,XED_EXCEPTION_INVALID), +/*1003*/ XED_DEF_INST(XED_ICLASS_REP_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSD,1182,5,46,0,71,XED_EXCEPTION_INVALID), +/*1004*/ XED_DEF_INST(XED_ICLASS_REP_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_STOSD,1182,5,46,0,71,XED_EXCEPTION_INVALID), +/*1005*/ XED_DEF_INST(XED_ICLASS_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSD,1187,4,46,0,72,XED_EXCEPTION_INVALID), +/*1006*/ XED_DEF_INST(XED_ICLASS_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSD,1187,4,46,0,72,XED_EXCEPTION_INVALID), +/*1007*/ XED_DEF_INST(XED_ICLASS_STOSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_STOSD,1187,4,46,0,72,XED_EXCEPTION_INVALID), +/*1008*/ XED_DEF_INST(XED_ICLASS_REP_STOSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REP_STOSQ,1191,5,46,0,71,XED_EXCEPTION_INVALID), +/*1009*/ XED_DEF_INST(XED_ICLASS_REP_STOSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REP_STOSQ,1191,5,46,0,71,XED_EXCEPTION_INVALID), +/*1010*/ XED_DEF_INST(XED_ICLASS_STOSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_STOSQ,1196,4,46,0,72,XED_EXCEPTION_INVALID), +/*1011*/ XED_DEF_INST(XED_ICLASS_REP_LODSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSB,1200,5,46,0,70,XED_EXCEPTION_INVALID), +/*1012*/ XED_DEF_INST(XED_ICLASS_REP_LODSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSB,1200,5,46,0,70,XED_EXCEPTION_INVALID), +/*1013*/ XED_DEF_INST(XED_ICLASS_LODSB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSB,1205,4,46,0,42,XED_EXCEPTION_INVALID), +/*1014*/ XED_DEF_INST(XED_ICLASS_REP_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSW,1209,5,46,0,71,XED_EXCEPTION_INVALID), +/*1015*/ XED_DEF_INST(XED_ICLASS_REP_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSW,1209,5,46,0,71,XED_EXCEPTION_INVALID), +/*1016*/ XED_DEF_INST(XED_ICLASS_REP_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSW,1209,5,46,0,71,XED_EXCEPTION_INVALID), +/*1017*/ XED_DEF_INST(XED_ICLASS_REP_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSW,1209,5,46,0,71,XED_EXCEPTION_INVALID), +/*1018*/ XED_DEF_INST(XED_ICLASS_REP_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSW,1209,5,46,0,71,XED_EXCEPTION_INVALID), +/*1019*/ XED_DEF_INST(XED_ICLASS_REP_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSW,1209,5,46,0,71,XED_EXCEPTION_INVALID), +/*1020*/ XED_DEF_INST(XED_ICLASS_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSW,1214,4,46,0,72,XED_EXCEPTION_INVALID), +/*1021*/ XED_DEF_INST(XED_ICLASS_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSW,1214,4,46,0,72,XED_EXCEPTION_INVALID), +/*1022*/ XED_DEF_INST(XED_ICLASS_LODSW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSW,1214,4,46,0,72,XED_EXCEPTION_INVALID), +/*1023*/ XED_DEF_INST(XED_ICLASS_REP_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSD,1218,5,46,0,71,XED_EXCEPTION_INVALID), +/*1024*/ XED_DEF_INST(XED_ICLASS_REP_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSD,1218,5,46,0,71,XED_EXCEPTION_INVALID), +/*1025*/ XED_DEF_INST(XED_ICLASS_REP_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSD,1218,5,46,0,71,XED_EXCEPTION_INVALID), +/*1026*/ XED_DEF_INST(XED_ICLASS_REP_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSD,1218,5,46,0,71,XED_EXCEPTION_INVALID), +/*1027*/ XED_DEF_INST(XED_ICLASS_REP_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSD,1218,5,46,0,71,XED_EXCEPTION_INVALID), +/*1028*/ XED_DEF_INST(XED_ICLASS_REP_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REP_LODSD,1218,5,46,0,71,XED_EXCEPTION_INVALID), +/*1029*/ XED_DEF_INST(XED_ICLASS_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSD,1223,4,46,0,72,XED_EXCEPTION_INVALID), +/*1030*/ XED_DEF_INST(XED_ICLASS_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSD,1223,4,46,0,72,XED_EXCEPTION_INVALID), +/*1031*/ XED_DEF_INST(XED_ICLASS_LODSD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_LODSD,1223,4,46,0,72,XED_EXCEPTION_INVALID), +/*1032*/ XED_DEF_INST(XED_ICLASS_REP_LODSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REP_LODSQ,1227,5,46,0,71,XED_EXCEPTION_INVALID), +/*1033*/ XED_DEF_INST(XED_ICLASS_REP_LODSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REP_LODSQ,1227,5,46,0,71,XED_EXCEPTION_INVALID), +/*1034*/ XED_DEF_INST(XED_ICLASS_LODSQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_LODSQ,1232,4,46,0,72,XED_EXCEPTION_INVALID), +/*1035*/ XED_DEF_INST(XED_ICLASS_REPE_SCASB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASB,1236,5,47,0,70,XED_EXCEPTION_INVALID), +/*1036*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASB,1236,5,47,0,70,XED_EXCEPTION_INVALID), +/*1037*/ XED_DEF_INST(XED_ICLASS_SCASB,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASB,1241,4,48,0,42,XED_EXCEPTION_INVALID), +/*1038*/ XED_DEF_INST(XED_ICLASS_REPE_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASW,1245,5,47,0,71,XED_EXCEPTION_INVALID), +/*1039*/ XED_DEF_INST(XED_ICLASS_REPE_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASW,1245,5,47,0,71,XED_EXCEPTION_INVALID), +/*1040*/ XED_DEF_INST(XED_ICLASS_REPE_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASW,1245,5,47,0,71,XED_EXCEPTION_INVALID), +/*1041*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASW,1245,5,47,0,71,XED_EXCEPTION_INVALID), +/*1042*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASW,1245,5,47,0,71,XED_EXCEPTION_INVALID), +/*1043*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASW,1245,5,47,0,71,XED_EXCEPTION_INVALID), +/*1044*/ XED_DEF_INST(XED_ICLASS_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASW,1250,4,48,0,72,XED_EXCEPTION_INVALID), +/*1045*/ XED_DEF_INST(XED_ICLASS_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASW,1250,4,48,0,72,XED_EXCEPTION_INVALID), +/*1046*/ XED_DEF_INST(XED_ICLASS_SCASW,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASW,1250,4,48,0,72,XED_EXCEPTION_INVALID), +/*1047*/ XED_DEF_INST(XED_ICLASS_REPE_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASD,1254,5,47,0,71,XED_EXCEPTION_INVALID), +/*1048*/ XED_DEF_INST(XED_ICLASS_REPE_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASD,1254,5,47,0,71,XED_EXCEPTION_INVALID), +/*1049*/ XED_DEF_INST(XED_ICLASS_REPE_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPE_SCASD,1254,5,47,0,71,XED_EXCEPTION_INVALID), +/*1050*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASD,1254,5,47,0,71,XED_EXCEPTION_INVALID), +/*1051*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASD,1254,5,47,0,71,XED_EXCEPTION_INVALID), +/*1052*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_REPNE_SCASD,1254,5,47,0,71,XED_EXCEPTION_INVALID), +/*1053*/ XED_DEF_INST(XED_ICLASS_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASD,1259,4,48,0,72,XED_EXCEPTION_INVALID), +/*1054*/ XED_DEF_INST(XED_ICLASS_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASD,1259,4,48,0,72,XED_EXCEPTION_INVALID), +/*1055*/ XED_DEF_INST(XED_ICLASS_SCASD,XED_CATEGORY_STRINGOP,XED_EXTENSION_BASE,3,XED_IFORM_SCASD,1259,4,48,0,72,XED_EXCEPTION_INVALID), +/*1056*/ XED_DEF_INST(XED_ICLASS_REPE_SCASQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REPE_SCASQ,1263,5,47,0,71,XED_EXCEPTION_INVALID), +/*1057*/ XED_DEF_INST(XED_ICLASS_REPNE_SCASQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_REPNE_SCASQ,1263,5,47,0,71,XED_EXCEPTION_INVALID), +/*1058*/ XED_DEF_INST(XED_ICLASS_SCASQ,XED_CATEGORY_STRINGOP,XED_EXTENSION_LONGMODE,3,XED_IFORM_SCASQ,1268,4,48,0,72,XED_EXCEPTION_INVALID), +/*1059*/ XED_DEF_INST(XED_ICLASS_RET_NEAR,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_RET_NEAR_IMMw,1272,5,0,0,73,XED_EXCEPTION_INVALID), +/*1060*/ XED_DEF_INST(XED_ICLASS_RET_NEAR,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_RET_NEAR,1277,4,0,0,73,XED_EXCEPTION_INVALID), +/*1061*/ XED_DEF_INST(XED_ICLASS_LES,XED_CATEGORY_SEGOP,XED_EXTENSION_BASE,3,XED_IFORM_LES_GPRz_MEMp,1281,3,0,0,34,XED_EXCEPTION_INVALID), +/*1062*/ XED_DEF_INST(XED_ICLASS_LDS,XED_CATEGORY_SEGOP,XED_EXTENSION_BASE,3,XED_IFORM_LDS_GPRz_MEMp,1284,3,0,0,34,XED_EXCEPTION_INVALID), +/*1063*/ XED_DEF_INST(XED_ICLASS_ENTER,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_ENTER_IMMw_IMMb,1287,6,0,0,74,XED_EXCEPTION_INVALID), +/*1064*/ XED_DEF_INST(XED_ICLASS_LEAVE,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_LEAVE,1293,4,0,0,43,XED_EXCEPTION_INVALID), +/*1065*/ XED_DEF_INST(XED_ICLASS_RET_FAR,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_RET_FAR_IMMw,1297,5,0,0,75,XED_EXCEPTION_INVALID), +/*1066*/ XED_DEF_INST(XED_ICLASS_RET_FAR,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_RET_FAR,1302,4,0,0,75,XED_EXCEPTION_INVALID), +/*1067*/ XED_DEF_INST(XED_ICLASS_INT3,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_INT3,1306,2,49,0,1,XED_EXCEPTION_INVALID), +/*1068*/ XED_DEF_INST(XED_ICLASS_INT,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_INT_IMMb,1308,3,49,0,1,XED_EXCEPTION_INVALID), +/*1069*/ XED_DEF_INST(XED_ICLASS_INTO,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_INTO,1311,2,50,0,1,XED_EXCEPTION_INVALID), +/*1070*/ XED_DEF_INST(XED_ICLASS_IRET,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_IRET,1313,5,51,0,17,XED_EXCEPTION_INVALID), +/*1071*/ XED_DEF_INST(XED_ICLASS_IRET,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_IRET,1313,5,51,0,17,XED_EXCEPTION_INVALID), +/*1072*/ XED_DEF_INST(XED_ICLASS_IRET,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_IRET,1313,5,51,0,17,XED_EXCEPTION_INVALID), +/*1073*/ XED_DEF_INST(XED_ICLASS_IRETD,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_IRETD,1313,5,51,0,17,XED_EXCEPTION_INVALID), +/*1074*/ XED_DEF_INST(XED_ICLASS_IRETD,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_IRETD,1313,5,51,0,17,XED_EXCEPTION_INVALID), +/*1075*/ XED_DEF_INST(XED_ICLASS_IRETD,XED_CATEGORY_RET,XED_EXTENSION_BASE,3,XED_IFORM_IRETD,1313,5,51,0,17,XED_EXCEPTION_INVALID), +/*1076*/ XED_DEF_INST(XED_ICLASS_IRETQ,XED_CATEGORY_RET,XED_EXTENSION_LONGMODE,3,XED_IFORM_IRETQ,1318,5,51,0,17,XED_EXCEPTION_INVALID), +/*1077*/ XED_DEF_INST(XED_ICLASS_AAM,XED_CATEGORY_DECIMAL,XED_EXTENSION_BASE,3,XED_IFORM_AAM_IMMb,1323,4,52,0,0,XED_EXCEPTION_INVALID), +/*1078*/ XED_DEF_INST(XED_ICLASS_AAD,XED_CATEGORY_DECIMAL,XED_EXTENSION_BASE,3,XED_IFORM_AAD_IMMb,1327,4,52,0,0,XED_EXCEPTION_INVALID), +/*1079*/ XED_DEF_INST(XED_ICLASS_SALC,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_SALC,1331,2,53,0,0,XED_EXCEPTION_INVALID), +/*1080*/ XED_DEF_INST(XED_ICLASS_XLAT,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_XLAT,1333,3,0,0,72,XED_EXCEPTION_INVALID), +/*1081*/ XED_DEF_INST(XED_ICLASS_LOOPNE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPNE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1082*/ XED_DEF_INST(XED_ICLASS_LOOPNE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPNE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1083*/ XED_DEF_INST(XED_ICLASS_LOOPNE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPNE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1084*/ XED_DEF_INST(XED_ICLASS_LOOPNE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPNE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1085*/ XED_DEF_INST(XED_ICLASS_LOOPE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1086*/ XED_DEF_INST(XED_ICLASS_LOOPE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1087*/ XED_DEF_INST(XED_ICLASS_LOOPE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1088*/ XED_DEF_INST(XED_ICLASS_LOOPE,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOPE_RELBRb,1336,4,36,0,0,XED_EXCEPTION_INVALID), +/*1089*/ XED_DEF_INST(XED_ICLASS_LOOP,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_LOOP_RELBRb,1340,3,0,0,0,XED_EXCEPTION_INVALID), +/*1090*/ XED_DEF_INST(XED_ICLASS_JCXZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JCXZ_RELBRb,1343,3,0,0,0,XED_EXCEPTION_INVALID), +/*1091*/ XED_DEF_INST(XED_ICLASS_JECXZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JECXZ_RELBRb,1346,3,0,0,0,XED_EXCEPTION_INVALID), +/*1092*/ XED_DEF_INST(XED_ICLASS_JECXZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JECXZ_RELBRb,1349,3,0,0,0,XED_EXCEPTION_INVALID), +/*1093*/ XED_DEF_INST(XED_ICLASS_JRCXZ,XED_CATEGORY_COND_BR,XED_EXTENSION_BASE,3,XED_IFORM_JRCXZ_RELBRb,1352,3,0,0,0,XED_EXCEPTION_INVALID), +/*1094*/ XED_DEF_INST(XED_ICLASS_IN,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_IN_AL_IMMb,1355,3,54,0,76,XED_EXCEPTION_INVALID), +/*1095*/ XED_DEF_INST(XED_ICLASS_IN,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_IN_OeAX_IMMb,1358,3,54,0,34,XED_EXCEPTION_INVALID), +/*1096*/ XED_DEF_INST(XED_ICLASS_IN,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_IN_AL_DX,1361,3,54,0,12,XED_EXCEPTION_INVALID), +/*1097*/ XED_DEF_INST(XED_ICLASS_IN,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_IN_OeAX_DX,1364,3,54,0,14,XED_EXCEPTION_INVALID), +/*1098*/ XED_DEF_INST(XED_ICLASS_OUT,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_OUT_IMMb_AL,1367,3,54,0,76,XED_EXCEPTION_INVALID), +/*1099*/ XED_DEF_INST(XED_ICLASS_OUT,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_OUT_IMMb_OeAX,1370,3,54,0,34,XED_EXCEPTION_INVALID), +/*1100*/ XED_DEF_INST(XED_ICLASS_OUT,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_OUT_DX_AL,1373,3,54,0,12,XED_EXCEPTION_INVALID), +/*1101*/ XED_DEF_INST(XED_ICLASS_OUT,XED_CATEGORY_IO,XED_EXTENSION_BASE,3,XED_IFORM_OUT_DX_OeAX,1376,3,54,0,14,XED_EXCEPTION_INVALID), +/*1102*/ XED_DEF_INST(XED_ICLASS_INT1,XED_CATEGORY_INTERRUPT,XED_EXTENSION_BASE,3,XED_IFORM_INT1,1379,1,0,0,0,XED_EXCEPTION_INVALID), +/*1103*/ XED_DEF_INST(XED_ICLASS_HLT,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_HLT,0,0,0,0,35,XED_EXCEPTION_INVALID), +/*1104*/ XED_DEF_INST(XED_ICLASS_CMC,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_CMC,1380,1,55,0,0,XED_EXCEPTION_INVALID), +/*1105*/ XED_DEF_INST(XED_ICLASS_CLC,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_CLC,848,1,56,0,0,XED_EXCEPTION_INVALID), +/*1106*/ XED_DEF_INST(XED_ICLASS_STC,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_STC,848,1,57,0,0,XED_EXCEPTION_INVALID), +/*1107*/ XED_DEF_INST(XED_ICLASS_CLI,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_CLI,1380,1,58,0,1,XED_EXCEPTION_INVALID), +/*1108*/ XED_DEF_INST(XED_ICLASS_STI,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_STI,1380,1,58,0,1,XED_EXCEPTION_INVALID), +/*1109*/ XED_DEF_INST(XED_ICLASS_CLD,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_CLD,848,1,59,0,77,XED_EXCEPTION_INVALID), +/*1110*/ XED_DEF_INST(XED_ICLASS_STD,XED_CATEGORY_FLAGOP,XED_EXTENSION_BASE,3,XED_IFORM_STD,848,1,60,0,77,XED_EXCEPTION_INVALID), +/*1111*/ XED_DEF_INST(XED_ICLASS_LAR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_LAR_GPRv_MEMw,1381,3,26,0,78,XED_EXCEPTION_INVALID), +/*1112*/ XED_DEF_INST(XED_ICLASS_LAR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_LAR_GPRv_GPRv,1384,3,26,0,78,XED_EXCEPTION_INVALID), +/*1113*/ XED_DEF_INST(XED_ICLASS_LSL,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_LSL_GPRv_MEMw,1387,3,26,0,78,XED_EXCEPTION_INVALID), +/*1114*/ XED_DEF_INST(XED_ICLASS_LSL,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_LSL_GPRv_GPRz,1390,3,26,0,78,XED_EXCEPTION_INVALID), +/*1115*/ XED_DEF_INST(XED_ICLASS_SYSCALL,XED_CATEGORY_SYSCALL,XED_EXTENSION_LONGMODE,3,XED_IFORM_SYSCALL,1393,4,61,0,1,XED_EXCEPTION_INVALID), +/*1116*/ XED_DEF_INST(XED_ICLASS_CLTS,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_CLTS,0,0,0,0,35,XED_EXCEPTION_INVALID), +/*1117*/ XED_DEF_INST(XED_ICLASS_SYSRET,XED_CATEGORY_SYSRET,XED_EXTENSION_LONGMODE,0,XED_IFORM_SYSRET,1397,3,62,0,32,XED_EXCEPTION_INVALID), +/*1118*/ XED_DEF_INST(XED_ICLASS_SYSRET64,XED_CATEGORY_SYSRET,XED_EXTENSION_LONGMODE,0,XED_IFORM_SYSRET64,1400,4,62,0,32,XED_EXCEPTION_INVALID), +/*1119*/ XED_DEF_INST(XED_ICLASS_MOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVUPS_XMMps_MEMps,1404,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1120*/ XED_DEF_INST(XED_ICLASS_MOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVUPS_XMMps_XMMps_0F10,1406,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1121*/ XED_DEF_INST(XED_ICLASS_MOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVUPS_MEMps_XMMps,1408,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1122*/ XED_DEF_INST(XED_ICLASS_MOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVUPS_XMMps_XMMps_0F11,1410,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1123*/ XED_DEF_INST(XED_ICLASS_UNPCKLPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_UNPCKLPS_XMMps_MEMdq,1412,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1124*/ XED_DEF_INST(XED_ICLASS_UNPCKLPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_UNPCKLPS_XMMps_XMMq,1414,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1125*/ XED_DEF_INST(XED_ICLASS_UNPCKHPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_UNPCKHPS_XMMps_MEMdq,1412,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1126*/ XED_DEF_INST(XED_ICLASS_UNPCKHPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_UNPCKHPS_XMMps_XMMdq,1416,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1127*/ XED_DEF_INST(XED_ICLASS_MOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVSS_XMMdq_MEMss,1418,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1128*/ XED_DEF_INST(XED_ICLASS_MOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVSS_XMMss_XMMss_0F10,1420,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1129*/ XED_DEF_INST(XED_ICLASS_MOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVSS_MEMss_XMMss,1422,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1130*/ XED_DEF_INST(XED_ICLASS_MOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVSS_XMMss_XMMss_0F11,1424,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1131*/ XED_DEF_INST(XED_ICLASS_MOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE3,3,XED_IFORM_MOVSLDUP_XMMps_MEMps,1404,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1132*/ XED_DEF_INST(XED_ICLASS_MOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE3,3,XED_IFORM_MOVSLDUP_XMMps_XMMps,1406,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1133*/ XED_DEF_INST(XED_ICLASS_MOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE3,3,XED_IFORM_MOVSHDUP_XMMps_MEMps,1404,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1134*/ XED_DEF_INST(XED_ICLASS_MOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE3,3,XED_IFORM_MOVSHDUP_XMMps_XMMps,1406,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1135*/ XED_DEF_INST(XED_ICLASS_MOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVUPD_XMMpd_MEMpd,1426,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1136*/ XED_DEF_INST(XED_ICLASS_MOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVUPD_XMMpd_XMMpd_0F10,1428,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1137*/ XED_DEF_INST(XED_ICLASS_MOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVUPD_MEMpd_XMMpd,1430,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1138*/ XED_DEF_INST(XED_ICLASS_MOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVUPD_XMMpd_XMMpd_0F11,1432,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1139*/ XED_DEF_INST(XED_ICLASS_MOVLPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVLPD_XMMsd_MEMq,1434,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1140*/ XED_DEF_INST(XED_ICLASS_MOVLPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVLPD_MEMq_XMMsd,1436,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1141*/ XED_DEF_INST(XED_ICLASS_UNPCKLPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_UNPCKLPD_XMMpd_MEMdq,1438,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1142*/ XED_DEF_INST(XED_ICLASS_UNPCKLPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_UNPCKLPD_XMMpd_XMMq,1440,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1143*/ XED_DEF_INST(XED_ICLASS_UNPCKHPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_UNPCKHPD_XMMpd_MEMdq,1438,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1144*/ XED_DEF_INST(XED_ICLASS_UNPCKHPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_UNPCKHPD_XMMpd_XMMq,1440,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1145*/ XED_DEF_INST(XED_ICLASS_MOVHPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVHPD_XMMsd_MEMq,1434,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1146*/ XED_DEF_INST(XED_ICLASS_MOVHPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVHPD_MEMq_XMMsd,1436,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1147*/ XED_DEF_INST(XED_ICLASS_MOVSD_XMM,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVSD_XMM_XMMdq_MEMsd,1442,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1148*/ XED_DEF_INST(XED_ICLASS_MOVSD_XMM,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F10,1444,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1149*/ XED_DEF_INST(XED_ICLASS_MOVSD_XMM,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVSD_XMM_MEMsd_XMMsd,1446,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1150*/ XED_DEF_INST(XED_ICLASS_MOVSD_XMM,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVSD_XMM_XMMsd_XMMsd_0F11,1448,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1151*/ XED_DEF_INST(XED_ICLASS_MOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE3,3,XED_IFORM_MOVDDUP_XMMdq_MEMq,1450,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1152*/ XED_DEF_INST(XED_ICLASS_MOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE3,3,XED_IFORM_MOVDDUP_XMMdq_XMMq,1452,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1153*/ XED_DEF_INST(XED_ICLASS_MOV_CR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_CR_CR_GPR32,1454,2,0,0,35,XED_EXCEPTION_INVALID), +/*1154*/ XED_DEF_INST(XED_ICLASS_MOV_CR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_CR_CR_GPR64,1456,2,0,0,35,XED_EXCEPTION_INVALID), +/*1155*/ XED_DEF_INST(XED_ICLASS_MOV_CR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_CR_GPR32_CR,1458,2,0,0,81,XED_EXCEPTION_INVALID), +/*1156*/ XED_DEF_INST(XED_ICLASS_MOV_CR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_CR_GPR64_CR,1460,2,0,0,81,XED_EXCEPTION_INVALID), +/*1157*/ XED_DEF_INST(XED_ICLASS_MOV_DR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_DR_DR_GPR32,1462,2,0,0,35,XED_EXCEPTION_INVALID), +/*1158*/ XED_DEF_INST(XED_ICLASS_MOV_DR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_DR_DR_GPR64,1464,2,0,0,35,XED_EXCEPTION_INVALID), +/*1159*/ XED_DEF_INST(XED_ICLASS_MOV_DR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_DR_GPR32_DR,1466,2,0,0,81,XED_EXCEPTION_INVALID), +/*1160*/ XED_DEF_INST(XED_ICLASS_MOV_DR,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,0,XED_IFORM_MOV_DR_GPR64_DR,1468,2,0,0,81,XED_EXCEPTION_INVALID), +/*1161*/ XED_DEF_INST(XED_ICLASS_WRMSR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_WRMSR,1470,4,0,0,35,XED_EXCEPTION_INVALID), +/*1162*/ XED_DEF_INST(XED_ICLASS_RDTSC,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_RDTSC,1474,3,0,0,0,XED_EXCEPTION_INVALID), +/*1163*/ XED_DEF_INST(XED_ICLASS_RDMSR,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_RDMSR,1477,4,0,0,35,XED_EXCEPTION_INVALID), +/*1164*/ XED_DEF_INST(XED_ICLASS_RDPMC,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,3,XED_IFORM_RDPMC,1477,4,0,0,0,XED_EXCEPTION_INVALID), +/*1165*/ XED_DEF_INST(XED_ICLASS_SYSENTER,XED_CATEGORY_SYSCALL,XED_EXTENSION_BASE,3,XED_IFORM_SYSENTER,1481,3,63,0,30,XED_EXCEPTION_INVALID), +/*1166*/ XED_DEF_INST(XED_ICLASS_SYSENTER,XED_CATEGORY_SYSCALL,XED_EXTENSION_BASE,3,XED_IFORM_SYSENTER,1484,3,63,0,30,XED_EXCEPTION_INVALID), +/*1167*/ XED_DEF_INST(XED_ICLASS_SYSEXIT,XED_CATEGORY_SYSRET,XED_EXTENSION_BASE,0,XED_IFORM_SYSEXIT,1487,4,0,0,32,XED_EXCEPTION_INVALID), +/*1168*/ XED_DEF_INST(XED_ICLASS_SYSEXIT,XED_CATEGORY_SYSRET,XED_EXTENSION_BASE,0,XED_IFORM_SYSEXIT,1491,4,0,0,32,XED_EXCEPTION_INVALID), +/*1169*/ XED_DEF_INST(XED_ICLASS_CMOVO,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVO_GPRv_MEMv,1495,3,34,0,14,XED_EXCEPTION_INVALID), +/*1170*/ XED_DEF_INST(XED_ICLASS_CMOVO,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVO_GPRv_GPRv,1498,3,34,0,14,XED_EXCEPTION_INVALID), +/*1171*/ XED_DEF_INST(XED_ICLASS_CMOVNO,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNO_GPRv_MEMv,1495,3,34,0,14,XED_EXCEPTION_INVALID), +/*1172*/ XED_DEF_INST(XED_ICLASS_CMOVNO,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNO_GPRv_GPRv,1498,3,34,0,14,XED_EXCEPTION_INVALID), +/*1173*/ XED_DEF_INST(XED_ICLASS_CMOVB,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVB_GPRv_MEMv,1495,3,64,0,14,XED_EXCEPTION_INVALID), +/*1174*/ XED_DEF_INST(XED_ICLASS_CMOVB,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVB_GPRv_GPRv,1498,3,64,0,14,XED_EXCEPTION_INVALID), +/*1175*/ XED_DEF_INST(XED_ICLASS_CMOVNB,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNB_GPRv_MEMv,1495,3,64,0,14,XED_EXCEPTION_INVALID), +/*1176*/ XED_DEF_INST(XED_ICLASS_CMOVNB,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNB_GPRv_GPRv,1498,3,64,0,14,XED_EXCEPTION_INVALID), +/*1177*/ XED_DEF_INST(XED_ICLASS_CMOVZ,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVZ_GPRv_MEMv,1495,3,36,0,14,XED_EXCEPTION_INVALID), +/*1178*/ XED_DEF_INST(XED_ICLASS_CMOVZ,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVZ_GPRv_GPRv,1498,3,36,0,14,XED_EXCEPTION_INVALID), +/*1179*/ XED_DEF_INST(XED_ICLASS_CMOVNZ,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNZ_GPRv_MEMv,1495,3,36,0,14,XED_EXCEPTION_INVALID), +/*1180*/ XED_DEF_INST(XED_ICLASS_CMOVNZ,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNZ_GPRv_GPRv,1498,3,36,0,14,XED_EXCEPTION_INVALID), +/*1181*/ XED_DEF_INST(XED_ICLASS_CMOVBE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVBE_GPRv_MEMv,1495,3,37,0,14,XED_EXCEPTION_INVALID), +/*1182*/ XED_DEF_INST(XED_ICLASS_CMOVBE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVBE_GPRv_GPRv,1498,3,37,0,14,XED_EXCEPTION_INVALID), +/*1183*/ XED_DEF_INST(XED_ICLASS_CMOVNBE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNBE_GPRv_MEMv,1495,3,37,0,14,XED_EXCEPTION_INVALID), +/*1184*/ XED_DEF_INST(XED_ICLASS_CMOVNBE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNBE_GPRv_GPRv,1498,3,37,0,14,XED_EXCEPTION_INVALID), +/*1185*/ XED_DEF_INST(XED_ICLASS_MOVMSKPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVMSKPS_GPR32_XMMps,1501,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/*1186*/ XED_DEF_INST(XED_ICLASS_SQRTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SQRTPS_XMMps_MEMps,1404,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1187*/ XED_DEF_INST(XED_ICLASS_SQRTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SQRTPS_XMMps_XMMps,1406,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1188*/ XED_DEF_INST(XED_ICLASS_RSQRTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RSQRTPS_XMMps_MEMps,1404,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1189*/ XED_DEF_INST(XED_ICLASS_RSQRTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RSQRTPS_XMMps_XMMps,1406,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1190*/ XED_DEF_INST(XED_ICLASS_RCPPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RCPPS_XMMps_MEMps,1404,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1191*/ XED_DEF_INST(XED_ICLASS_RCPPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RCPPS_XMMps_XMMps,1406,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1192*/ XED_DEF_INST(XED_ICLASS_ANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_ANDPS_XMMxud_MEMxud,1503,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1193*/ XED_DEF_INST(XED_ICLASS_ANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_ANDPS_XMMxud_XMMxud,1505,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1194*/ XED_DEF_INST(XED_ICLASS_ANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_ANDNPS_XMMxud_MEMxud,1503,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1195*/ XED_DEF_INST(XED_ICLASS_ANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_ANDNPS_XMMxud_XMMxud,1505,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1196*/ XED_DEF_INST(XED_ICLASS_ORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_ORPS_XMMxud_MEMxud,1503,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1197*/ XED_DEF_INST(XED_ICLASS_ORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_ORPS_XMMxud_XMMxud,1505,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1198*/ XED_DEF_INST(XED_ICLASS_XORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_XORPS_XMMxud_MEMxud,1503,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1199*/ XED_DEF_INST(XED_ICLASS_XORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE,3,XED_IFORM_XORPS_XMMxud_XMMxud,1505,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1200*/ XED_DEF_INST(XED_ICLASS_SQRTSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SQRTSS_XMMss_MEMss,1507,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1201*/ XED_DEF_INST(XED_ICLASS_SQRTSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SQRTSS_XMMss_XMMss,1420,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1202*/ XED_DEF_INST(XED_ICLASS_RSQRTSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RSQRTSS_XMMss_MEMss,1507,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1203*/ XED_DEF_INST(XED_ICLASS_RSQRTSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RSQRTSS_XMMss_XMMss,1420,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1204*/ XED_DEF_INST(XED_ICLASS_RCPSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RCPSS_XMMss_MEMss,1507,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1205*/ XED_DEF_INST(XED_ICLASS_RCPSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_RCPSS_XMMss_XMMss,1420,2,0,0,80,XED_EXCEPTION_SSE_TYPE_5), +/*1206*/ XED_DEF_INST(XED_ICLASS_MOVMSKPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVMSKPD_GPR32_XMMpd,1509,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/*1207*/ XED_DEF_INST(XED_ICLASS_SQRTPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SQRTPD_XMMpd_MEMpd,1426,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1208*/ XED_DEF_INST(XED_ICLASS_SQRTPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SQRTPD_XMMpd_XMMpd,1428,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1209*/ XED_DEF_INST(XED_ICLASS_ANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_ANDPD_XMMxuq_MEMxuq,1511,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1210*/ XED_DEF_INST(XED_ICLASS_ANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_ANDPD_XMMxuq_XMMxuq,1513,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1211*/ XED_DEF_INST(XED_ICLASS_ANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_ANDNPD_XMMxuq_MEMxuq,1511,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1212*/ XED_DEF_INST(XED_ICLASS_ANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_ANDNPD_XMMxuq_XMMxuq,1513,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1213*/ XED_DEF_INST(XED_ICLASS_ORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_ORPD_XMMxuq_MEMxuq,1511,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1214*/ XED_DEF_INST(XED_ICLASS_ORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_ORPD_XMMxuq_XMMxuq,1513,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1215*/ XED_DEF_INST(XED_ICLASS_XORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_XORPD_XMMxuq_MEMxuq,1511,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1216*/ XED_DEF_INST(XED_ICLASS_XORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_SSE2,3,XED_IFORM_XORPD_XMMxuq_XMMxuq,1513,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1217*/ XED_DEF_INST(XED_ICLASS_SQRTSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SQRTSD_XMMsd_MEMsd,1515,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1218*/ XED_DEF_INST(XED_ICLASS_SQRTSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SQRTSD_XMMsd_XMMsd,1444,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1219*/ XED_DEF_INST(XED_ICLASS_PUNPCKLBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKLBW_MMXq_MEMd,1517,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1220*/ XED_DEF_INST(XED_ICLASS_PUNPCKLBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKLBW_MMXq_MMXd,1519,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1221*/ XED_DEF_INST(XED_ICLASS_PUNPCKLBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLBW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1222*/ XED_DEF_INST(XED_ICLASS_PUNPCKLBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLBW_XMMdq_XMMq,1521,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1223*/ XED_DEF_INST(XED_ICLASS_PUNPCKLWD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKLWD_MMXq_MEMd,1523,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1224*/ XED_DEF_INST(XED_ICLASS_PUNPCKLWD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKLWD_MMXq_MMXd,1525,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1225*/ XED_DEF_INST(XED_ICLASS_PUNPCKLWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLWD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1226*/ XED_DEF_INST(XED_ICLASS_PUNPCKLWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLWD_XMMdq_XMMq,1521,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1227*/ XED_DEF_INST(XED_ICLASS_PUNPCKLDQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKLDQ_MMXq_MEMd,1527,2,0,0,1,XED_EXCEPTION_INVALID), +/*1228*/ XED_DEF_INST(XED_ICLASS_PUNPCKLDQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKLDQ_MMXq_MMXd,1529,2,0,0,1,XED_EXCEPTION_INVALID), +/*1229*/ XED_DEF_INST(XED_ICLASS_PUNPCKLDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLDQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1230*/ XED_DEF_INST(XED_ICLASS_PUNPCKLDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLDQ_XMMdq_XMMq,1521,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1231*/ XED_DEF_INST(XED_ICLASS_PACKSSWB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PACKSSWB_MMXq_MEMq,1531,2,0,0,84,XED_EXCEPTION_MMX_MEM), +/*1232*/ XED_DEF_INST(XED_ICLASS_PACKSSWB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PACKSSWB_MMXq_MMXq,1533,2,0,0,84,XED_EXCEPTION_INVALID), +/*1233*/ XED_DEF_INST(XED_ICLASS_PACKSSWB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PACKSSWB_XMMdq_MEMdq,1535,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1234*/ XED_DEF_INST(XED_ICLASS_PACKSSWB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PACKSSWB_XMMdq_XMMdq,1537,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1235*/ XED_DEF_INST(XED_ICLASS_PCMPGTB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPGTB_MMXq_MEMq,1539,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1236*/ XED_DEF_INST(XED_ICLASS_PCMPGTB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPGTB_MMXq_MMXq,1541,2,0,0,1,XED_EXCEPTION_INVALID), +/*1237*/ XED_DEF_INST(XED_ICLASS_PCMPGTB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPGTB_XMMdq_MEMdq,1543,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1238*/ XED_DEF_INST(XED_ICLASS_PCMPGTB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPGTB_XMMdq_XMMdq,1545,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1239*/ XED_DEF_INST(XED_ICLASS_PCMPGTW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPGTW_MMXq_MEMq,1531,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1240*/ XED_DEF_INST(XED_ICLASS_PCMPGTW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPGTW_MMXq_MMXq,1533,2,0,0,1,XED_EXCEPTION_INVALID), +/*1241*/ XED_DEF_INST(XED_ICLASS_PCMPGTW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPGTW_XMMdq_MEMdq,1535,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1242*/ XED_DEF_INST(XED_ICLASS_PCMPGTW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPGTW_XMMdq_XMMdq,1537,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1243*/ XED_DEF_INST(XED_ICLASS_PCMPGTD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPGTD_MMXq_MEMq,1547,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1244*/ XED_DEF_INST(XED_ICLASS_PCMPGTD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPGTD_MMXq_MMXq,1549,2,0,0,1,XED_EXCEPTION_INVALID), +/*1245*/ XED_DEF_INST(XED_ICLASS_PCMPGTD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPGTD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1246*/ XED_DEF_INST(XED_ICLASS_PCMPGTD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPGTD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1247*/ XED_DEF_INST(XED_ICLASS_PACKUSWB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PACKUSWB_MMXq_MEMq,1531,2,0,0,84,XED_EXCEPTION_MMX_MEM), +/*1248*/ XED_DEF_INST(XED_ICLASS_PACKUSWB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PACKUSWB_MMXq_MMXq,1533,2,0,0,84,XED_EXCEPTION_INVALID), +/*1249*/ XED_DEF_INST(XED_ICLASS_PACKUSWB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PACKUSWB_XMMdq_MEMdq,1535,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1250*/ XED_DEF_INST(XED_ICLASS_PACKUSWB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PACKUSWB_XMMdq_XMMdq,1537,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1251*/ XED_DEF_INST(XED_ICLASS_PSHUFW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSHUFW_MMXq_MEMq_IMMb,1551,3,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1252*/ XED_DEF_INST(XED_ICLASS_PSHUFW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSHUFW_MMXq_MMXq_IMMb,1554,3,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1253*/ XED_DEF_INST(XED_ICLASS_PCMPEQB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPEQB_MMXq_MEMq,1539,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1254*/ XED_DEF_INST(XED_ICLASS_PCMPEQB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPEQB_MMXq_MMXq,1541,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1255*/ XED_DEF_INST(XED_ICLASS_PCMPEQB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPEQB_XMMdq_MEMdq,1543,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1256*/ XED_DEF_INST(XED_ICLASS_PCMPEQB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPEQB_XMMdq_XMMdq,1545,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1257*/ XED_DEF_INST(XED_ICLASS_PCMPEQW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPEQW_MMXq_MEMq,1531,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1258*/ XED_DEF_INST(XED_ICLASS_PCMPEQW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPEQW_MMXq_MMXq,1533,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1259*/ XED_DEF_INST(XED_ICLASS_PCMPEQW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPEQW_XMMdq_MEMdq,1535,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1260*/ XED_DEF_INST(XED_ICLASS_PCMPEQW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPEQW_XMMdq_XMMdq,1537,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1261*/ XED_DEF_INST(XED_ICLASS_PCMPEQD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPEQD_MMXq_MEMq,1547,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1262*/ XED_DEF_INST(XED_ICLASS_PCMPEQD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PCMPEQD_MMXq_MMXq,1549,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1263*/ XED_DEF_INST(XED_ICLASS_PCMPEQD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPEQD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1264*/ XED_DEF_INST(XED_ICLASS_PCMPEQD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PCMPEQD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1265*/ XED_DEF_INST(XED_ICLASS_EMMS,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_EMMS,0,0,0,0,86,XED_EXCEPTION_INVALID), +/*1266*/ XED_DEF_INST(XED_ICLASS_PSHUFD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSHUFD_XMMdq_MEMdq_IMMb,1557,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1267*/ XED_DEF_INST(XED_ICLASS_PSHUFD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSHUFD_XMMdq_XMMdq_IMMb,1560,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1268*/ XED_DEF_INST(XED_ICLASS_PSHUFLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSHUFLW_XMMdq_MEMdq_IMMb,1563,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1269*/ XED_DEF_INST(XED_ICLASS_PSHUFLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSHUFLW_XMMdq_XMMdq_IMMb,1566,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1270*/ XED_DEF_INST(XED_ICLASS_PSHUFHW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSHUFHW_XMMdq_MEMdq_IMMb,1563,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1271*/ XED_DEF_INST(XED_ICLASS_PSHUFHW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSHUFHW_XMMdq_XMMdq_IMMb,1566,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1272*/ XED_DEF_INST(XED_ICLASS_SETO,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETO_MEMb,1569,2,34,0,12,XED_EXCEPTION_INVALID), +/*1273*/ XED_DEF_INST(XED_ICLASS_SETO,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETO_GPR8,1571,2,34,0,12,XED_EXCEPTION_INVALID), +/*1274*/ XED_DEF_INST(XED_ICLASS_SETNO,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNO_MEMb,1569,2,34,0,12,XED_EXCEPTION_INVALID), +/*1275*/ XED_DEF_INST(XED_ICLASS_SETNO,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNO_GPR8,1571,2,34,0,12,XED_EXCEPTION_INVALID), +/*1276*/ XED_DEF_INST(XED_ICLASS_SETB,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETB_MEMb,1569,2,64,0,12,XED_EXCEPTION_INVALID), +/*1277*/ XED_DEF_INST(XED_ICLASS_SETB,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETB_GPR8,1571,2,64,0,12,XED_EXCEPTION_INVALID), +/*1278*/ XED_DEF_INST(XED_ICLASS_SETNB,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNB_MEMb,1569,2,64,0,12,XED_EXCEPTION_INVALID), +/*1279*/ XED_DEF_INST(XED_ICLASS_SETNB,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNB_GPR8,1571,2,64,0,12,XED_EXCEPTION_INVALID), +/*1280*/ XED_DEF_INST(XED_ICLASS_SETZ,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETZ_MEMb,1569,2,36,0,12,XED_EXCEPTION_INVALID), +/*1281*/ XED_DEF_INST(XED_ICLASS_SETZ,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETZ_GPR8,1571,2,36,0,12,XED_EXCEPTION_INVALID), +/*1282*/ XED_DEF_INST(XED_ICLASS_SETNZ,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNZ_MEMb,1569,2,36,0,12,XED_EXCEPTION_INVALID), +/*1283*/ XED_DEF_INST(XED_ICLASS_SETNZ,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNZ_GPR8,1571,2,36,0,12,XED_EXCEPTION_INVALID), +/*1284*/ XED_DEF_INST(XED_ICLASS_SETBE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETBE_MEMb,1569,2,37,0,12,XED_EXCEPTION_INVALID), +/*1285*/ XED_DEF_INST(XED_ICLASS_SETBE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETBE_GPR8,1571,2,37,0,12,XED_EXCEPTION_INVALID), +/*1286*/ XED_DEF_INST(XED_ICLASS_SETNBE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNBE_MEMb,1569,2,37,0,12,XED_EXCEPTION_INVALID), +/*1287*/ XED_DEF_INST(XED_ICLASS_SETNBE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNBE_GPR8,1571,2,37,0,12,XED_EXCEPTION_INVALID), +/*1288*/ XED_DEF_INST(XED_ICLASS_CPUID,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_CPUID,1573,4,0,0,1,XED_EXCEPTION_INVALID), +/*1289*/ XED_DEF_INST(XED_ICLASS_CMPXCHG_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG_LOCK_MEMb_GPR8,1577,4,10,0,9,XED_EXCEPTION_INVALID), +/*1290*/ XED_DEF_INST(XED_ICLASS_CMPXCHG_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG_LOCK_MEMv_GPRv,1581,4,10,0,10,XED_EXCEPTION_INVALID), +/*1291*/ XED_DEF_INST(XED_ICLASS_CMPXCHG,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG_MEMb_GPR8,1577,4,10,0,11,XED_EXCEPTION_INVALID), +/*1292*/ XED_DEF_INST(XED_ICLASS_CMPXCHG,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG_GPR8_GPR8,1585,4,10,0,12,XED_EXCEPTION_INVALID), +/*1293*/ XED_DEF_INST(XED_ICLASS_CMPXCHG,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG_MEMv_GPRv,1581,4,10,0,13,XED_EXCEPTION_INVALID), +/*1294*/ XED_DEF_INST(XED_ICLASS_CMPXCHG,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_CMPXCHG_GPRv_GPRv,1589,4,10,0,14,XED_EXCEPTION_INVALID), +/*1295*/ XED_DEF_INST(XED_ICLASS_LSS,XED_CATEGORY_SEGOP,XED_EXTENSION_BASE,3,XED_IFORM_LSS_GPRv_MEMp2,1593,3,0,0,34,XED_EXCEPTION_INVALID), +/*1296*/ XED_DEF_INST(XED_ICLASS_LFS,XED_CATEGORY_SEGOP,XED_EXTENSION_BASE,3,XED_IFORM_LFS_GPRv_MEMp2,1596,3,0,0,34,XED_EXCEPTION_INVALID), +/*1297*/ XED_DEF_INST(XED_ICLASS_LGS,XED_CATEGORY_SEGOP,XED_EXTENSION_BASE,3,XED_IFORM_LGS_GPRv_MEMp2,1599,3,0,0,34,XED_EXCEPTION_INVALID), +/*1298*/ XED_DEF_INST(XED_ICLASS_MOVZX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVZX_GPRv_MEMb,1602,2,0,0,14,XED_EXCEPTION_INVALID), +/*1299*/ XED_DEF_INST(XED_ICLASS_MOVZX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVZX_GPRv_GPR8,1604,2,0,0,14,XED_EXCEPTION_INVALID), +/*1300*/ XED_DEF_INST(XED_ICLASS_MOVZX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVZX_GPRv_MEMw,1606,2,0,0,14,XED_EXCEPTION_INVALID), +/*1301*/ XED_DEF_INST(XED_ICLASS_MOVZX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVZX_GPRv_GPR16,1608,2,0,0,14,XED_EXCEPTION_INVALID), +/*1302*/ XED_DEF_INST(XED_ICLASS_XADD_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_XADD_LOCK_MEMb_GPR8,1610,3,10,0,9,XED_EXCEPTION_INVALID), +/*1303*/ XED_DEF_INST(XED_ICLASS_XADD_LOCK,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_XADD_LOCK_MEMv_GPRv,1613,3,10,0,10,XED_EXCEPTION_INVALID), +/*1304*/ XED_DEF_INST(XED_ICLASS_XADD,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_XADD_MEMb_GPR8,1610,3,10,0,11,XED_EXCEPTION_INVALID), +/*1305*/ XED_DEF_INST(XED_ICLASS_XADD,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_XADD_GPR8_GPR8,1616,3,10,0,12,XED_EXCEPTION_INVALID), +/*1306*/ XED_DEF_INST(XED_ICLASS_XADD,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_XADD_MEMv_GPRv,1613,3,10,0,13,XED_EXCEPTION_INVALID), +/*1307*/ XED_DEF_INST(XED_ICLASS_XADD,XED_CATEGORY_SEMAPHORE,XED_EXTENSION_BASE,3,XED_IFORM_XADD_GPRv_GPRv,1619,3,10,0,14,XED_EXCEPTION_INVALID), +/*1308*/ XED_DEF_INST(XED_ICLASS_CMPPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_CMPPS_XMMps_MEMps_IMMb,1622,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1309*/ XED_DEF_INST(XED_ICLASS_CMPPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_CMPPS_XMMps_XMMps_IMMb,1625,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1310*/ XED_DEF_INST(XED_ICLASS_MOVNTI,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVNTI_MEMd_GPR32,1628,2,0,0,87,XED_EXCEPTION_INVALID), +/*1311*/ XED_DEF_INST(XED_ICLASS_MOVNTI,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVNTI_MEMd_GPR32,1628,2,0,0,87,XED_EXCEPTION_INVALID), +/*1312*/ XED_DEF_INST(XED_ICLASS_MOVNTI,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVNTI_MEMq_GPR64,1630,2,0,0,87,XED_EXCEPTION_INVALID), +/*1313*/ XED_DEF_INST(XED_ICLASS_PINSRW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PINSRW_MMXq_MEMw_IMMb,1632,3,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1314*/ XED_DEF_INST(XED_ICLASS_PINSRW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PINSRW_MMXq_GPR32_IMMb,1635,3,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1315*/ XED_DEF_INST(XED_ICLASS_PINSRW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PINSRW_XMMdq_MEMw_IMMb,1638,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1316*/ XED_DEF_INST(XED_ICLASS_PINSRW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PINSRW_XMMdq_GPR32_IMMb,1641,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1317*/ XED_DEF_INST(XED_ICLASS_PEXTRW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PEXTRW_GPR32_MMXq_IMMb,1644,3,0,0,1,XED_EXCEPTION_MMX_NOMEM), +/*1318*/ XED_DEF_INST(XED_ICLASS_PEXTRW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PEXTRW_GPR32_XMMdq_IMMb,1647,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1319*/ XED_DEF_INST(XED_ICLASS_SHUFPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SHUFPS_XMMps_MEMps_IMMb,1622,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1320*/ XED_DEF_INST(XED_ICLASS_SHUFPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SHUFPS_XMMps_XMMps_IMMb,1625,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1321*/ XED_DEF_INST(XED_ICLASS_CMPSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_CMPSS_XMMss_MEMss_IMMb,1650,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1322*/ XED_DEF_INST(XED_ICLASS_CMPSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_CMPSS_XMMss_XMMss_IMMb,1653,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1323*/ XED_DEF_INST(XED_ICLASS_CMPPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_CMPPD_XMMpd_MEMpd_IMMb,1656,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1324*/ XED_DEF_INST(XED_ICLASS_CMPPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_CMPPD_XMMpd_XMMpd_IMMb,1659,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1325*/ XED_DEF_INST(XED_ICLASS_SHUFPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SHUFPD_XMMpd_MEMpd_IMMb,1656,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1326*/ XED_DEF_INST(XED_ICLASS_SHUFPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SHUFPD_XMMpd_XMMpd_IMMb,1659,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1327*/ XED_DEF_INST(XED_ICLASS_CMPSD_XMM,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_CMPSD_XMM_XMMsd_MEMsd_IMMb,1662,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1328*/ XED_DEF_INST(XED_ICLASS_CMPSD_XMM,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_CMPSD_XMM_XMMsd_XMMsd_IMMb,1665,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1329*/ XED_DEF_INST(XED_ICLASS_PADDQ,XED_CATEGORY_MMX,XED_EXTENSION_SSE2,3,XED_IFORM_PADDQ_MMXq_MEMq,1668,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1330*/ XED_DEF_INST(XED_ICLASS_PADDQ,XED_CATEGORY_MMX,XED_EXTENSION_SSE2,3,XED_IFORM_PADDQ_MMXq_MMXq,1670,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1331*/ XED_DEF_INST(XED_ICLASS_PADDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1332*/ XED_DEF_INST(XED_ICLASS_PADDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1333*/ XED_DEF_INST(XED_ICLASS_PMULLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMULLW_MMXq_MEMq,1531,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1334*/ XED_DEF_INST(XED_ICLASS_PMULLW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMULLW_MMXq_MMXq,1533,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1335*/ XED_DEF_INST(XED_ICLASS_PMULLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULLW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1336*/ XED_DEF_INST(XED_ICLASS_PMULLW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULLW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1337*/ XED_DEF_INST(XED_ICLASS_PMOVMSKB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMOVMSKB_GPR32_MMXq,1672,2,0,0,1,XED_EXCEPTION_MMX_NOMEM), +/*1338*/ XED_DEF_INST(XED_ICLASS_PMOVMSKB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMOVMSKB_GPR32_XMMdq,1674,2,0,0,0,XED_EXCEPTION_SSE_TYPE_7), +/*1339*/ XED_DEF_INST(XED_ICLASS_ADDSUBPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_ADDSUBPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1340*/ XED_DEF_INST(XED_ICLASS_ADDSUBPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_ADDSUBPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1341*/ XED_DEF_INST(XED_ICLASS_MOVQ2DQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ2DQ_XMMdq_MMXq,1680,2,0,0,88,XED_EXCEPTION_INVALID), +/*1342*/ XED_DEF_INST(XED_ICLASS_ADDSUBPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_ADDSUBPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1343*/ XED_DEF_INST(XED_ICLASS_ADDSUBPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_ADDSUBPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1344*/ XED_DEF_INST(XED_ICLASS_MOVDQ2Q,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQ2Q_MMXq_XMMq,1686,2,0,0,88,XED_EXCEPTION_INVALID), +/*1345*/ XED_DEF_INST(XED_ICLASS_PAVGB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PAVGB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1346*/ XED_DEF_INST(XED_ICLASS_PAVGB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PAVGB_MMXq_MMXq,1541,2,0,0,1,XED_EXCEPTION_INVALID), +/*1347*/ XED_DEF_INST(XED_ICLASS_PAVGB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PAVGB_XMMdq_MEMdq,1690,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1348*/ XED_DEF_INST(XED_ICLASS_PAVGB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PAVGB_XMMdq_XMMdq,1692,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1349*/ XED_DEF_INST(XED_ICLASS_PAVGW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PAVGW_MMXq_MEMq,1531,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1350*/ XED_DEF_INST(XED_ICLASS_PAVGW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PAVGW_MMXq_MMXq,1533,2,0,0,1,XED_EXCEPTION_INVALID), +/*1351*/ XED_DEF_INST(XED_ICLASS_PAVGW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PAVGW_XMMdq_MEMdq,1694,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1352*/ XED_DEF_INST(XED_ICLASS_PAVGW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PAVGW_XMMdq_XMMdq,1696,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1353*/ XED_DEF_INST(XED_ICLASS_PMULHUW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMULHUW_MMXq_MEMq,1698,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1354*/ XED_DEF_INST(XED_ICLASS_PMULHUW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMULHUW_MMXq_MMXq,1700,2,0,0,1,XED_EXCEPTION_INVALID), +/*1355*/ XED_DEF_INST(XED_ICLASS_PMULHUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULHUW_XMMdq_MEMdq,1694,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1356*/ XED_DEF_INST(XED_ICLASS_PMULHUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULHUW_XMMdq_XMMdq,1696,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1357*/ XED_DEF_INST(XED_ICLASS_PMULHW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMULHW_MMXq_MEMq,1531,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1358*/ XED_DEF_INST(XED_ICLASS_PMULHW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMULHW_MMXq_MMXq,1533,2,0,0,1,XED_EXCEPTION_INVALID), +/*1359*/ XED_DEF_INST(XED_ICLASS_PMULHW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULHW_XMMdq_MEMdq,1535,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1360*/ XED_DEF_INST(XED_ICLASS_PMULHW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULHW_XMMdq_XMMdq,1537,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1361*/ XED_DEF_INST(XED_ICLASS_MOVNTQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVNTQ_MEMq_MMXq,1702,2,0,0,89,XED_EXCEPTION_MMX_NOFP2), +/*1362*/ XED_DEF_INST(XED_ICLASS_CVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTPD2DQ_XMMdq_MEMpd,1704,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1363*/ XED_DEF_INST(XED_ICLASS_CVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTPD2DQ_XMMdq_XMMpd,1706,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1364*/ XED_DEF_INST(XED_ICLASS_MOVNTDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVNTDQ_MEMdq_XMMdq,1708,2,0,0,90,XED_EXCEPTION_SSE_TYPE_1), +/*1365*/ XED_DEF_INST(XED_ICLASS_CVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTDQ2PD_XMMpd_MEMq,1710,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1366*/ XED_DEF_INST(XED_ICLASS_CVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTDQ2PD_XMMpd_XMMq,1712,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1367*/ XED_DEF_INST(XED_ICLASS_CVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPD2DQ_XMMdq_MEMpd,1704,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1368*/ XED_DEF_INST(XED_ICLASS_CVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPD2DQ_XMMdq_XMMpd,1706,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1369*/ XED_DEF_INST(XED_ICLASS_PMULUDQ,XED_CATEGORY_MMX,XED_EXTENSION_SSE2,3,XED_IFORM_PMULUDQ_MMXq_MEMq,1714,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1370*/ XED_DEF_INST(XED_ICLASS_PMULUDQ,XED_CATEGORY_MMX,XED_EXTENSION_SSE2,3,XED_IFORM_PMULUDQ_MMXq_MMXq,1716,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1371*/ XED_DEF_INST(XED_ICLASS_PMULUDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULUDQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1372*/ XED_DEF_INST(XED_ICLASS_PMULUDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMULUDQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1373*/ XED_DEF_INST(XED_ICLASS_PMADDWD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMADDWD_MMXq_MEMq,1531,2,0,0,91,XED_EXCEPTION_MMX_MEM), +/*1374*/ XED_DEF_INST(XED_ICLASS_PMADDWD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMADDWD_MMXq_MMXq,1533,2,0,0,91,XED_EXCEPTION_MMX_MEM), +/*1375*/ XED_DEF_INST(XED_ICLASS_PMADDWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMADDWD_XMMdq_MEMdq,1535,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1376*/ XED_DEF_INST(XED_ICLASS_PMADDWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMADDWD_XMMdq_XMMdq,1537,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1377*/ XED_DEF_INST(XED_ICLASS_PSADBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSADBW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1378*/ XED_DEF_INST(XED_ICLASS_PSADBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSADBW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1379*/ XED_DEF_INST(XED_ICLASS_PSADBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSADBW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1380*/ XED_DEF_INST(XED_ICLASS_PSADBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSADBW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1381*/ XED_DEF_INST(XED_ICLASS_MASKMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MASKMOVQ_MMXq_MMXq,1720,4,0,0,92,XED_EXCEPTION_MMX_NOFP2), +/*1382*/ XED_DEF_INST(XED_ICLASS_MASKMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MASKMOVDQU_XMMdq_XMMdq,1724,4,0,0,92,XED_EXCEPTION_SSE_TYPE_4), +/*1383*/ XED_DEF_INST(XED_ICLASS_LDDQU,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_LDDQU_XMMpd_MEMdq,1728,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1384*/ XED_DEF_INST(XED_ICLASS_INVD,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_INVD,0,0,0,0,35,XED_EXCEPTION_INVALID), +/*1385*/ XED_DEF_INST(XED_ICLASS_UD0,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_UD0,0,0,0,0,1,XED_EXCEPTION_INVALID), +/*1386*/ XED_DEF_INST(XED_ICLASS_UD0,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_UD0_GPR32_MEMd,1730,2,0,0,1,XED_EXCEPTION_INVALID), +/*1387*/ XED_DEF_INST(XED_ICLASS_UD0,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_UD0_GPR32_GPR32,1732,2,0,0,1,XED_EXCEPTION_INVALID), +/*1388*/ XED_DEF_INST(XED_ICLASS_UD1,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_UD1_GPR32_MEMd,1730,2,0,0,1,XED_EXCEPTION_INVALID), +/*1389*/ XED_DEF_INST(XED_ICLASS_UD1,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_UD1_GPR32_GPR32,1732,2,0,0,1,XED_EXCEPTION_INVALID), +/*1390*/ XED_DEF_INST(XED_ICLASS_UD2,XED_CATEGORY_MISC,XED_EXTENSION_BASE,3,XED_IFORM_UD2,0,0,0,0,1,XED_EXCEPTION_INVALID), +/*1391*/ XED_DEF_INST(XED_ICLASS_MOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVAPS_XMMps_MEMps,1404,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1392*/ XED_DEF_INST(XED_ICLASS_MOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVAPS_XMMps_XMMps_0F28,1406,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1393*/ XED_DEF_INST(XED_ICLASS_MOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVAPS_MEMps_XMMps,1408,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1394*/ XED_DEF_INST(XED_ICLASS_MOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVAPS_XMMps_XMMps_0F29,1410,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1395*/ XED_DEF_INST(XED_ICLASS_CVTPI2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTPI2PS_XMMq_MEMq,1734,2,0,0,93,XED_EXCEPTION_MMX_FP), +/*1396*/ XED_DEF_INST(XED_ICLASS_CVTPI2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTPI2PS_XMMq_MMXq,1736,2,0,0,93,XED_EXCEPTION_MMX_FP), +/*1397*/ XED_DEF_INST(XED_ICLASS_MOVNTPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE,3,XED_IFORM_MOVNTPS_MEMdq_XMMps,1738,2,0,0,90,XED_EXCEPTION_SSE_TYPE_1), +/*1398*/ XED_DEF_INST(XED_ICLASS_CVTTPS2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTTPS2PI_MMXq_MEMq,1740,2,0,0,93,XED_EXCEPTION_MMX_FP), +/*1399*/ XED_DEF_INST(XED_ICLASS_CVTTPS2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTTPS2PI_MMXq_XMMq,1742,2,0,0,93,XED_EXCEPTION_MMX_FP), +/*1400*/ XED_DEF_INST(XED_ICLASS_CVTPS2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTPS2PI_MMXq_MEMq,1740,2,0,0,93,XED_EXCEPTION_MMX_FP), +/*1401*/ XED_DEF_INST(XED_ICLASS_CVTPS2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTPS2PI_MMXq_XMMq,1742,2,0,0,93,XED_EXCEPTION_MMX_FP), +/*1402*/ XED_DEF_INST(XED_ICLASS_UCOMISS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_UCOMISS_XMMss_MEMss,1744,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1403*/ XED_DEF_INST(XED_ICLASS_UCOMISS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_UCOMISS_XMMss_XMMss,1747,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1404*/ XED_DEF_INST(XED_ICLASS_COMISS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_COMISS_XMMss_MEMss,1744,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1405*/ XED_DEF_INST(XED_ICLASS_COMISS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_COMISS_XMMss_XMMss,1747,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1406*/ XED_DEF_INST(XED_ICLASS_CVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSI2SS_XMMss_MEMd,1750,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1407*/ XED_DEF_INST(XED_ICLASS_CVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSI2SS_XMMss_GPR32d,1752,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1408*/ XED_DEF_INST(XED_ICLASS_CVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSI2SS_XMMss_MEMq,1754,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1409*/ XED_DEF_INST(XED_ICLASS_CVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSI2SS_XMMss_GPR64q,1756,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1410*/ XED_DEF_INST(XED_ICLASS_CVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTTSS2SI_GPR32d_MEMss,1758,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1411*/ XED_DEF_INST(XED_ICLASS_CVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTTSS2SI_GPR32d_XMMss,1760,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1412*/ XED_DEF_INST(XED_ICLASS_CVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTTSS2SI_GPR64q_MEMss,1762,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1413*/ XED_DEF_INST(XED_ICLASS_CVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTTSS2SI_GPR64q_XMMss,1764,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1414*/ XED_DEF_INST(XED_ICLASS_CVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSS2SI_GPR32d_MEMss,1758,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1415*/ XED_DEF_INST(XED_ICLASS_CVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSS2SI_GPR32d_XMMss,1760,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1416*/ XED_DEF_INST(XED_ICLASS_CVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSS2SI_GPR64q_MEMss,1762,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1417*/ XED_DEF_INST(XED_ICLASS_CVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE,3,XED_IFORM_CVTSS2SI_GPR64q_XMMss,1764,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1418*/ XED_DEF_INST(XED_ICLASS_MOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVAPD_XMMpd_MEMpd,1426,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1419*/ XED_DEF_INST(XED_ICLASS_MOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVAPD_XMMpd_XMMpd_0F28,1428,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1420*/ XED_DEF_INST(XED_ICLASS_MOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVAPD_MEMpd_XMMpd,1430,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1421*/ XED_DEF_INST(XED_ICLASS_MOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVAPD_XMMpd_XMMpd_0F29,1432,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1422*/ XED_DEF_INST(XED_ICLASS_CVTPI2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPI2PD_XMMpd_MEMq,1710,2,0,0,93,XED_EXCEPTION_MMX_NOFP), +/*1423*/ XED_DEF_INST(XED_ICLASS_CVTPI2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPI2PD_XMMpd_MMXq,1766,2,0,0,93,XED_EXCEPTION_MMX_NOFP), +/*1424*/ XED_DEF_INST(XED_ICLASS_MOVNTPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVNTPD_MEMdq_XMMpd,1768,2,0,0,90,XED_EXCEPTION_SSE_TYPE_1), +/*1425*/ XED_DEF_INST(XED_ICLASS_CVTTPD2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTPD2PI_MMXq_MEMpd,1770,2,0,0,94,XED_EXCEPTION_MMX_FP_16ALIGN), +/*1426*/ XED_DEF_INST(XED_ICLASS_CVTTPD2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTPD2PI_MMXq_XMMpd,1772,2,0,0,94,XED_EXCEPTION_MMX_FP_16ALIGN), +/*1427*/ XED_DEF_INST(XED_ICLASS_CVTPD2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPD2PI_MMXq_MEMpd,1770,2,0,0,94,XED_EXCEPTION_MMX_FP_16ALIGN), +/*1428*/ XED_DEF_INST(XED_ICLASS_CVTPD2PI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPD2PI_MMXq_XMMpd,1772,2,0,0,94,XED_EXCEPTION_MMX_FP_16ALIGN), +/*1429*/ XED_DEF_INST(XED_ICLASS_UCOMISD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_UCOMISD_XMMsd_MEMsd,1774,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1430*/ XED_DEF_INST(XED_ICLASS_UCOMISD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_UCOMISD_XMMsd_XMMsd,1777,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1431*/ XED_DEF_INST(XED_ICLASS_COMISD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_COMISD_XMMsd_MEMsd,1774,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1432*/ XED_DEF_INST(XED_ICLASS_COMISD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_COMISD_XMMsd_XMMsd,1777,3,65,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1433*/ XED_DEF_INST(XED_ICLASS_CVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSI2SD_XMMsd_MEMd,1780,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1434*/ XED_DEF_INST(XED_ICLASS_CVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSI2SD_XMMsd_GPR32d,1782,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1435*/ XED_DEF_INST(XED_ICLASS_CVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSI2SD_XMMsd_MEMq,1784,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1436*/ XED_DEF_INST(XED_ICLASS_CVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSI2SD_XMMsd_GPR64q,1786,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1437*/ XED_DEF_INST(XED_ICLASS_CVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTSD2SI_GPR32d_MEMsd,1788,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1438*/ XED_DEF_INST(XED_ICLASS_CVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTSD2SI_GPR32d_XMMsd,1790,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1439*/ XED_DEF_INST(XED_ICLASS_CVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTSD2SI_GPR64q_MEMsd,1792,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1440*/ XED_DEF_INST(XED_ICLASS_CVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTSD2SI_GPR64q_XMMsd,1794,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1441*/ XED_DEF_INST(XED_ICLASS_CVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSD2SI_GPR32d_MEMsd,1788,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1442*/ XED_DEF_INST(XED_ICLASS_CVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSD2SI_GPR32d_XMMsd,1790,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1443*/ XED_DEF_INST(XED_ICLASS_CVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSD2SI_GPR64q_MEMsd,1792,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1444*/ XED_DEF_INST(XED_ICLASS_CVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSD2SI_GPR64q_XMMsd,1794,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1445*/ XED_DEF_INST(XED_ICLASS_CMOVS,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVS_GPRv_MEMv,1495,3,66,0,14,XED_EXCEPTION_INVALID), +/*1446*/ XED_DEF_INST(XED_ICLASS_CMOVS,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVS_GPRv_GPRv,1498,3,66,0,14,XED_EXCEPTION_INVALID), +/*1447*/ XED_DEF_INST(XED_ICLASS_CMOVNS,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNS_GPRv_MEMv,1495,3,66,0,14,XED_EXCEPTION_INVALID), +/*1448*/ XED_DEF_INST(XED_ICLASS_CMOVNS,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNS_GPRv_GPRv,1498,3,66,0,14,XED_EXCEPTION_INVALID), +/*1449*/ XED_DEF_INST(XED_ICLASS_CMOVP,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVP_GPRv_MEMv,1495,3,39,0,14,XED_EXCEPTION_INVALID), +/*1450*/ XED_DEF_INST(XED_ICLASS_CMOVP,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVP_GPRv_GPRv,1498,3,39,0,14,XED_EXCEPTION_INVALID), +/*1451*/ XED_DEF_INST(XED_ICLASS_CMOVNP,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNP_GPRv_MEMv,1495,3,39,0,14,XED_EXCEPTION_INVALID), +/*1452*/ XED_DEF_INST(XED_ICLASS_CMOVNP,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNP_GPRv_GPRv,1498,3,39,0,14,XED_EXCEPTION_INVALID), +/*1453*/ XED_DEF_INST(XED_ICLASS_CMOVL,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVL_GPRv_MEMv,1495,3,67,0,14,XED_EXCEPTION_INVALID), +/*1454*/ XED_DEF_INST(XED_ICLASS_CMOVL,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVL_GPRv_GPRv,1498,3,67,0,14,XED_EXCEPTION_INVALID), +/*1455*/ XED_DEF_INST(XED_ICLASS_CMOVNL,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNL_GPRv_MEMv,1495,3,67,0,14,XED_EXCEPTION_INVALID), +/*1456*/ XED_DEF_INST(XED_ICLASS_CMOVNL,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNL_GPRv_GPRv,1498,3,67,0,14,XED_EXCEPTION_INVALID), +/*1457*/ XED_DEF_INST(XED_ICLASS_CMOVLE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVLE_GPRv_MEMv,1495,3,41,0,14,XED_EXCEPTION_INVALID), +/*1458*/ XED_DEF_INST(XED_ICLASS_CMOVLE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVLE_GPRv_GPRv,1498,3,41,0,14,XED_EXCEPTION_INVALID), +/*1459*/ XED_DEF_INST(XED_ICLASS_CMOVNLE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNLE_GPRv_MEMv,1495,3,41,0,14,XED_EXCEPTION_INVALID), +/*1460*/ XED_DEF_INST(XED_ICLASS_CMOVNLE,XED_CATEGORY_CMOV,XED_EXTENSION_BASE,3,XED_IFORM_CMOVNLE_GPRv_GPRv,1498,3,41,0,14,XED_EXCEPTION_INVALID), +/*1461*/ XED_DEF_INST(XED_ICLASS_ADDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_ADDPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1462*/ XED_DEF_INST(XED_ICLASS_ADDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_ADDPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1463*/ XED_DEF_INST(XED_ICLASS_MULPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MULPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1464*/ XED_DEF_INST(XED_ICLASS_MULPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MULPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1465*/ XED_DEF_INST(XED_ICLASS_CVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPS2PD_XMMpd_MEMq,1796,2,0,0,47,XED_EXCEPTION_SSE_TYPE_3), +/*1466*/ XED_DEF_INST(XED_ICLASS_CVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPS2PD_XMMpd_XMMq,1798,2,0,0,47,XED_EXCEPTION_SSE_TYPE_3), +/*1467*/ XED_DEF_INST(XED_ICLASS_CVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTDQ2PS_XMMps_MEMdq,1800,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1468*/ XED_DEF_INST(XED_ICLASS_CVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTDQ2PS_XMMps_XMMdq,1802,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1469*/ XED_DEF_INST(XED_ICLASS_SUBPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SUBPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1470*/ XED_DEF_INST(XED_ICLASS_SUBPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SUBPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1471*/ XED_DEF_INST(XED_ICLASS_MINPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MINPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1472*/ XED_DEF_INST(XED_ICLASS_MINPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MINPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1473*/ XED_DEF_INST(XED_ICLASS_DIVPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_DIVPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1474*/ XED_DEF_INST(XED_ICLASS_DIVPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_DIVPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1475*/ XED_DEF_INST(XED_ICLASS_MAXPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MAXPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1476*/ XED_DEF_INST(XED_ICLASS_MAXPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MAXPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1477*/ XED_DEF_INST(XED_ICLASS_ADDSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_ADDSS_XMMss_MEMss,1804,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1478*/ XED_DEF_INST(XED_ICLASS_ADDSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_ADDSS_XMMss_XMMss,1806,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1479*/ XED_DEF_INST(XED_ICLASS_MULSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MULSS_XMMss_MEMss,1804,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1480*/ XED_DEF_INST(XED_ICLASS_MULSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MULSS_XMMss_XMMss,1806,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1481*/ XED_DEF_INST(XED_ICLASS_CVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSS2SD_XMMsd_MEMss,1808,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1482*/ XED_DEF_INST(XED_ICLASS_CVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSS2SD_XMMsd_XMMss,1810,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1483*/ XED_DEF_INST(XED_ICLASS_CVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTPS2DQ_XMMdq_MEMps,1812,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1484*/ XED_DEF_INST(XED_ICLASS_CVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTTPS2DQ_XMMdq_XMMps,1814,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1485*/ XED_DEF_INST(XED_ICLASS_SUBSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SUBSS_XMMss_MEMss,1804,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1486*/ XED_DEF_INST(XED_ICLASS_SUBSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_SUBSS_XMMss_XMMss,1806,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1487*/ XED_DEF_INST(XED_ICLASS_MINSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MINSS_XMMss_MEMss,1804,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1488*/ XED_DEF_INST(XED_ICLASS_MINSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MINSS_XMMss_XMMss,1806,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1489*/ XED_DEF_INST(XED_ICLASS_DIVSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_DIVSS_XMMss_MEMss,1804,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1490*/ XED_DEF_INST(XED_ICLASS_DIVSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_DIVSS_XMMss_XMMss,1806,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1491*/ XED_DEF_INST(XED_ICLASS_MAXSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MAXSS_XMMss_MEMss,1804,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1492*/ XED_DEF_INST(XED_ICLASS_MAXSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE,3,XED_IFORM_MAXSS_XMMss_XMMss,1806,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1493*/ XED_DEF_INST(XED_ICLASS_ADDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_ADDPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1494*/ XED_DEF_INST(XED_ICLASS_ADDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_ADDPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1495*/ XED_DEF_INST(XED_ICLASS_MULPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MULPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1496*/ XED_DEF_INST(XED_ICLASS_MULPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MULPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1497*/ XED_DEF_INST(XED_ICLASS_CVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPD2PS_XMMps_MEMpd,1816,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1498*/ XED_DEF_INST(XED_ICLASS_CVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPD2PS_XMMps_XMMpd,1818,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1499*/ XED_DEF_INST(XED_ICLASS_CVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPS2DQ_XMMdq_MEMps,1812,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1500*/ XED_DEF_INST(XED_ICLASS_CVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTPS2DQ_XMMdq_XMMps,1814,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1501*/ XED_DEF_INST(XED_ICLASS_SUBPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SUBPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1502*/ XED_DEF_INST(XED_ICLASS_SUBPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SUBPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1503*/ XED_DEF_INST(XED_ICLASS_MINPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MINPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1504*/ XED_DEF_INST(XED_ICLASS_MINPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MINPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1505*/ XED_DEF_INST(XED_ICLASS_DIVPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_DIVPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1506*/ XED_DEF_INST(XED_ICLASS_DIVPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_DIVPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1507*/ XED_DEF_INST(XED_ICLASS_MAXPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MAXPD_XMMpd_MEMpd,1676,2,0,0,95,XED_EXCEPTION_SSE_TYPE_2), +/*1508*/ XED_DEF_INST(XED_ICLASS_MAXPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MAXPD_XMMpd_XMMpd,1678,2,0,0,95,XED_EXCEPTION_SSE_TYPE_2), +/*1509*/ XED_DEF_INST(XED_ICLASS_ADDSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_ADDSD_XMMsd_MEMsd,1820,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1510*/ XED_DEF_INST(XED_ICLASS_ADDSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_ADDSD_XMMsd_XMMsd,1822,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1511*/ XED_DEF_INST(XED_ICLASS_MULSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MULSD_XMMsd_MEMsd,1820,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1512*/ XED_DEF_INST(XED_ICLASS_MULSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MULSD_XMMsd_XMMsd,1822,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1513*/ XED_DEF_INST(XED_ICLASS_CVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSD2SS_XMMss_MEMsd,1824,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1514*/ XED_DEF_INST(XED_ICLASS_CVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_SSE2,3,XED_IFORM_CVTSD2SS_XMMss_XMMsd,1826,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1515*/ XED_DEF_INST(XED_ICLASS_SUBSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SUBSD_XMMsd_MEMsd,1820,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1516*/ XED_DEF_INST(XED_ICLASS_SUBSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_SUBSD_XMMsd_XMMsd,1822,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1517*/ XED_DEF_INST(XED_ICLASS_MINSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MINSD_XMMsd_MEMsd,1820,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1518*/ XED_DEF_INST(XED_ICLASS_MINSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MINSD_XMMsd_XMMsd,1822,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1519*/ XED_DEF_INST(XED_ICLASS_DIVSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_DIVSD_XMMsd_MEMsd,1820,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1520*/ XED_DEF_INST(XED_ICLASS_DIVSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_DIVSD_XMMsd_XMMsd,1822,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1521*/ XED_DEF_INST(XED_ICLASS_MAXSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MAXSD_XMMsd_MEMsd,1820,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1522*/ XED_DEF_INST(XED_ICLASS_MAXSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_MAXSD_XMMsd_XMMsd,1822,2,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1523*/ XED_DEF_INST(XED_ICLASS_PUNPCKHBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKHBW_MMXq_MEMq,1688,2,0,0,96,XED_EXCEPTION_MMX_MEM), +/*1524*/ XED_DEF_INST(XED_ICLASS_PUNPCKHBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKHBW_MMXq_MMXd,1828,2,0,0,96,XED_EXCEPTION_MMX_MEM), +/*1525*/ XED_DEF_INST(XED_ICLASS_PUNPCKHBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHBW_XMMdq_MEMdq,776,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1526*/ XED_DEF_INST(XED_ICLASS_PUNPCKHBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHBW_XMMdq_XMMq,1521,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1527*/ XED_DEF_INST(XED_ICLASS_PUNPCKHWD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKHWD_MMXq_MEMq,1688,2,0,0,96,XED_EXCEPTION_MMX_MEM), +/*1528*/ XED_DEF_INST(XED_ICLASS_PUNPCKHWD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKHWD_MMXq_MMXd,1828,2,0,0,96,XED_EXCEPTION_MMX_MEM), +/*1529*/ XED_DEF_INST(XED_ICLASS_PUNPCKHWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHWD_XMMdq_MEMdq,776,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1530*/ XED_DEF_INST(XED_ICLASS_PUNPCKHWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHWD_XMMdq_XMMq,1521,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1531*/ XED_DEF_INST(XED_ICLASS_PUNPCKHDQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKHDQ_MMXq_MEMq,1688,2,0,0,96,XED_EXCEPTION_MMX_MEM), +/*1532*/ XED_DEF_INST(XED_ICLASS_PUNPCKHDQ,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PUNPCKHDQ_MMXq_MMXd,1828,2,0,0,96,XED_EXCEPTION_MMX_MEM), +/*1533*/ XED_DEF_INST(XED_ICLASS_PUNPCKHDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHDQ_XMMdq_MEMdq,776,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1534*/ XED_DEF_INST(XED_ICLASS_PUNPCKHDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHDQ_XMMdq_XMMq,1521,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1535*/ XED_DEF_INST(XED_ICLASS_PACKSSDW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PACKSSDW_MMXq_MEMq,1547,2,0,0,84,XED_EXCEPTION_MMX_MEM), +/*1536*/ XED_DEF_INST(XED_ICLASS_PACKSSDW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PACKSSDW_MMXq_MMXq,1549,2,0,0,84,XED_EXCEPTION_INVALID), +/*1537*/ XED_DEF_INST(XED_ICLASS_PACKSSDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PACKSSDW_XMMdq_MEMdq,776,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1538*/ XED_DEF_INST(XED_ICLASS_PACKSSDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PACKSSDW_XMMdq_XMMdq,778,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1539*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_XMMdq_MEMd,1830,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1540*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_XMMdq_GPR32,1832,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1541*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_XMMdq_MEMd,1830,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1542*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_XMMdq_GPR32,1832,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1543*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_MEMd_XMMd,1834,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1544*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_GPR32_XMMd,1836,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1545*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_MEMd_XMMd,1834,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1546*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVD_GPR32_XMMd,1836,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1547*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_MMXq_MEMd,1838,2,0,0,1,XED_EXCEPTION_INVALID), +/*1548*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_MMXq_GPR32,1840,2,0,0,1,XED_EXCEPTION_INVALID), +/*1549*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_MMXq_MEMd,1838,2,0,0,1,XED_EXCEPTION_INVALID), +/*1550*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_MMXq_GPR32,1840,2,0,0,1,XED_EXCEPTION_INVALID), +/*1551*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_MEMd_MMXd,1842,2,0,0,1,XED_EXCEPTION_INVALID), +/*1552*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_GPR32_MMXd,1844,2,0,0,1,XED_EXCEPTION_INVALID), +/*1553*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_MEMd_MMXd,1842,2,0,0,1,XED_EXCEPTION_INVALID), +/*1554*/ XED_DEF_INST(XED_ICLASS_MOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVD_GPR32_MMXd,1844,2,0,0,1,XED_EXCEPTION_INVALID), +/*1555*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_XMMdq_MEMq_0F6E,1450,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1556*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_XMMdq_GPR64,1846,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1557*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_MEMq_XMMq_0F7E,1848,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1558*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_GPR64_XMMq,1850,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1559*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_MEMq_XMMq_0FD6,1848,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1560*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_XMMdq_XMMq_0FD6,1852,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1561*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_XMMdq_MEMq_0F7E,1450,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1562*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVQ_XMMdq_XMMq_0F7E,1452,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1563*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MMXq_MEMq_0F6E,1854,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1564*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MMXq_GPR64,1856,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1565*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MEMq_MMXq_0F7E,1702,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1566*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_GPR64_MMXq,1858,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1567*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MMXq_MEMq_0F6F,1854,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1568*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MMXq_MMXq_0F6F,1860,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1569*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MEMq_MMXq_0F7F,1702,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1570*/ XED_DEF_INST(XED_ICLASS_MOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_MMX,3,XED_IFORM_MOVQ_MMXq_MMXq_0F7F,1862,2,0,0,1,XED_EXCEPTION_MMX_NOFP2), +/*1571*/ XED_DEF_INST(XED_ICLASS_PUNPCKLQDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLQDQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1572*/ XED_DEF_INST(XED_ICLASS_PUNPCKLQDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKLQDQ_XMMdq_XMMq,1521,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1573*/ XED_DEF_INST(XED_ICLASS_PUNPCKHQDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHQDQ_XMMdq_MEMdq,776,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1574*/ XED_DEF_INST(XED_ICLASS_PUNPCKHQDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PUNPCKHQDQ_XMMdq_XMMq,1521,2,0,0,79,XED_EXCEPTION_SSE_TYPE_4), +/*1575*/ XED_DEF_INST(XED_ICLASS_MOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQU_XMMdq_MEMdq,1864,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1576*/ XED_DEF_INST(XED_ICLASS_MOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQU_XMMdq_XMMdq_0F6F,1866,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1577*/ XED_DEF_INST(XED_ICLASS_MOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQU_MEMdq_XMMdq,1708,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1578*/ XED_DEF_INST(XED_ICLASS_MOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQU_XMMdq_XMMdq_0F7F,1868,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4M), +/*1579*/ XED_DEF_INST(XED_ICLASS_VMREAD,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMREAD_MEMq_GPR64,1870,3,28,0,0,XED_EXCEPTION_INVALID), +/*1580*/ XED_DEF_INST(XED_ICLASS_VMREAD,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMREAD_GPR64_GPR64,1873,3,28,0,0,XED_EXCEPTION_INVALID), +/*1581*/ XED_DEF_INST(XED_ICLASS_VMREAD,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMREAD_MEMd_GPR32,1876,3,28,0,0,XED_EXCEPTION_INVALID), +/*1582*/ XED_DEF_INST(XED_ICLASS_VMREAD,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMREAD_GPR32_GPR32,1879,3,28,0,0,XED_EXCEPTION_INVALID), +/*1583*/ XED_DEF_INST(XED_ICLASS_VMWRITE,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMWRITE_GPR64_MEMq,1882,3,28,0,0,XED_EXCEPTION_INVALID), +/*1584*/ XED_DEF_INST(XED_ICLASS_VMWRITE,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMWRITE_GPR64_GPR64,1885,3,28,0,0,XED_EXCEPTION_INVALID), +/*1585*/ XED_DEF_INST(XED_ICLASS_VMWRITE,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMWRITE_GPR32_MEMd,1888,3,28,0,0,XED_EXCEPTION_INVALID), +/*1586*/ XED_DEF_INST(XED_ICLASS_VMWRITE,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_VMWRITE_GPR32_GPR32,1891,3,28,0,0,XED_EXCEPTION_INVALID), +/*1587*/ XED_DEF_INST(XED_ICLASS_HADDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HADDPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1588*/ XED_DEF_INST(XED_ICLASS_HADDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HADDPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1589*/ XED_DEF_INST(XED_ICLASS_HSUBPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HSUBPD_XMMpd_MEMpd,1676,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1590*/ XED_DEF_INST(XED_ICLASS_HSUBPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HSUBPD_XMMpd_XMMpd,1678,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1591*/ XED_DEF_INST(XED_ICLASS_MOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQA_MEMdq_XMMdq,1708,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1592*/ XED_DEF_INST(XED_ICLASS_MOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQA_XMMdq_XMMdq_0F7F,1868,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1593*/ XED_DEF_INST(XED_ICLASS_MOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQA_XMMdq_MEMdq,1864,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1594*/ XED_DEF_INST(XED_ICLASS_MOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE2,3,XED_IFORM_MOVDQA_XMMdq_XMMdq_0F6F,1866,2,0,0,44,XED_EXCEPTION_SSE_TYPE_1), +/*1595*/ XED_DEF_INST(XED_ICLASS_HADDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HADDPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1596*/ XED_DEF_INST(XED_ICLASS_HADDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HADDPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1597*/ XED_DEF_INST(XED_ICLASS_HSUBPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HSUBPS_XMMps_MEMps,1682,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1598*/ XED_DEF_INST(XED_ICLASS_HSUBPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE3,3,XED_IFORM_HSUBPS_XMMps_XMMps,1684,2,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1599*/ XED_DEF_INST(XED_ICLASS_SETS,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETS_MEMb,1569,2,66,0,12,XED_EXCEPTION_INVALID), +/*1600*/ XED_DEF_INST(XED_ICLASS_SETS,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETS_GPR8,1571,2,66,0,12,XED_EXCEPTION_INVALID), +/*1601*/ XED_DEF_INST(XED_ICLASS_SETNS,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNS_MEMb,1569,2,66,0,12,XED_EXCEPTION_INVALID), +/*1602*/ XED_DEF_INST(XED_ICLASS_SETNS,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNS_GPR8,1571,2,66,0,12,XED_EXCEPTION_INVALID), +/*1603*/ XED_DEF_INST(XED_ICLASS_SETP,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETP_MEMb,1569,2,39,0,12,XED_EXCEPTION_INVALID), +/*1604*/ XED_DEF_INST(XED_ICLASS_SETP,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETP_GPR8,1571,2,39,0,12,XED_EXCEPTION_INVALID), +/*1605*/ XED_DEF_INST(XED_ICLASS_SETNP,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNP_MEMb,1569,2,39,0,12,XED_EXCEPTION_INVALID), +/*1606*/ XED_DEF_INST(XED_ICLASS_SETNP,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNP_GPR8,1571,2,39,0,12,XED_EXCEPTION_INVALID), +/*1607*/ XED_DEF_INST(XED_ICLASS_SETL,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETL_MEMb,1569,2,67,0,12,XED_EXCEPTION_INVALID), +/*1608*/ XED_DEF_INST(XED_ICLASS_SETL,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETL_GPR8,1571,2,67,0,12,XED_EXCEPTION_INVALID), +/*1609*/ XED_DEF_INST(XED_ICLASS_SETNL,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNL_MEMb,1569,2,67,0,12,XED_EXCEPTION_INVALID), +/*1610*/ XED_DEF_INST(XED_ICLASS_SETNL,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNL_GPR8,1571,2,67,0,12,XED_EXCEPTION_INVALID), +/*1611*/ XED_DEF_INST(XED_ICLASS_SETLE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETLE_MEMb,1569,2,41,0,12,XED_EXCEPTION_INVALID), +/*1612*/ XED_DEF_INST(XED_ICLASS_SETLE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETLE_GPR8,1571,2,41,0,12,XED_EXCEPTION_INVALID), +/*1613*/ XED_DEF_INST(XED_ICLASS_SETNLE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNLE_MEMb,1569,2,41,0,12,XED_EXCEPTION_INVALID), +/*1614*/ XED_DEF_INST(XED_ICLASS_SETNLE,XED_CATEGORY_SETCC,XED_EXTENSION_BASE,3,XED_IFORM_SETNLE_GPR8,1571,2,41,0,12,XED_EXCEPTION_INVALID), +/*1615*/ XED_DEF_INST(XED_ICLASS_RSM,XED_CATEGORY_SYSRET,XED_EXTENSION_BASE,3,XED_IFORM_RSM,1894,2,68,0,1,XED_EXCEPTION_INVALID), +/*1616*/ XED_DEF_INST(XED_ICLASS_SHRD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHRD_MEMv_GPRv_IMMb,1896,4,33,1,14,XED_EXCEPTION_INVALID), +/*1617*/ XED_DEF_INST(XED_ICLASS_SHRD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHRD_GPRv_GPRv_IMMb,1900,4,34,1,14,XED_EXCEPTION_INVALID), +/*1618*/ XED_DEF_INST(XED_ICLASS_SHRD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHRD_MEMv_GPRv_CL,1904,4,22,0,14,XED_EXCEPTION_INVALID), +/*1619*/ XED_DEF_INST(XED_ICLASS_SHRD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHRD_GPRv_GPRv_CL,1908,4,22,0,14,XED_EXCEPTION_INVALID), +/*1620*/ XED_DEF_INST(XED_ICLASS_SHLD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHLD_MEMv_GPRv_IMMb,1896,4,35,1,14,XED_EXCEPTION_INVALID), +/*1621*/ XED_DEF_INST(XED_ICLASS_SHLD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHLD_GPRv_GPRv_IMMb,1900,4,36,1,14,XED_EXCEPTION_INVALID), +/*1622*/ XED_DEF_INST(XED_ICLASS_SHLD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHLD_MEMv_GPRv_CL,1904,4,22,0,14,XED_EXCEPTION_INVALID), +/*1623*/ XED_DEF_INST(XED_ICLASS_SHLD,XED_CATEGORY_SHIFT,XED_EXTENSION_BASE,3,XED_IFORM_SHLD_GPRv_GPRv_CL,1908,4,22,0,14,XED_EXCEPTION_INVALID), +/*1624*/ XED_DEF_INST(XED_ICLASS_MOVSX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVSX_GPRv_MEMb,1602,2,0,0,14,XED_EXCEPTION_INVALID), +/*1625*/ XED_DEF_INST(XED_ICLASS_MOVSX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVSX_GPRv_GPR8,1604,2,0,0,14,XED_EXCEPTION_INVALID), +/*1626*/ XED_DEF_INST(XED_ICLASS_MOVSX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVSX_GPRv_MEMw,1606,2,0,0,14,XED_EXCEPTION_INVALID), +/*1627*/ XED_DEF_INST(XED_ICLASS_MOVSX,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_MOVSX_GPRv_GPR16,1608,2,0,0,14,XED_EXCEPTION_INVALID), +/*1628*/ XED_DEF_INST(XED_ICLASS_BSWAP,XED_CATEGORY_DATAXFER,XED_EXTENSION_BASE,3,XED_IFORM_BSWAP_GPRv,1912,1,0,0,14,XED_EXCEPTION_INVALID), +/*1629*/ XED_DEF_INST(XED_ICLASS_PSUBUSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBUSB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1630*/ XED_DEF_INST(XED_ICLASS_PSUBUSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBUSB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1631*/ XED_DEF_INST(XED_ICLASS_PSUBUSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBUSB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1632*/ XED_DEF_INST(XED_ICLASS_PSUBUSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBUSB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1633*/ XED_DEF_INST(XED_ICLASS_PSUBUSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBUSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1634*/ XED_DEF_INST(XED_ICLASS_PSUBUSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBUSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1635*/ XED_DEF_INST(XED_ICLASS_PSUBUSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBUSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1636*/ XED_DEF_INST(XED_ICLASS_PSUBUSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBUSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1637*/ XED_DEF_INST(XED_ICLASS_PMINUB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMINUB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1638*/ XED_DEF_INST(XED_ICLASS_PMINUB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMINUB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1639*/ XED_DEF_INST(XED_ICLASS_PMINUB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMINUB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1640*/ XED_DEF_INST(XED_ICLASS_PMINUB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMINUB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1641*/ XED_DEF_INST(XED_ICLASS_PAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_PAND_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1642*/ XED_DEF_INST(XED_ICLASS_PAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_PAND_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1643*/ XED_DEF_INST(XED_ICLASS_PAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_PAND_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1644*/ XED_DEF_INST(XED_ICLASS_PAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_PAND_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1645*/ XED_DEF_INST(XED_ICLASS_PADDUSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDUSB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1646*/ XED_DEF_INST(XED_ICLASS_PADDUSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDUSB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1647*/ XED_DEF_INST(XED_ICLASS_PADDUSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDUSB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1648*/ XED_DEF_INST(XED_ICLASS_PADDUSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDUSB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1649*/ XED_DEF_INST(XED_ICLASS_PADDUSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDUSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1650*/ XED_DEF_INST(XED_ICLASS_PADDUSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDUSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1651*/ XED_DEF_INST(XED_ICLASS_PADDUSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDUSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1652*/ XED_DEF_INST(XED_ICLASS_PADDUSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDUSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1653*/ XED_DEF_INST(XED_ICLASS_PMAXUB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMAXUB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1654*/ XED_DEF_INST(XED_ICLASS_PMAXUB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMAXUB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1655*/ XED_DEF_INST(XED_ICLASS_PMAXUB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMAXUB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1656*/ XED_DEF_INST(XED_ICLASS_PMAXUB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMAXUB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1657*/ XED_DEF_INST(XED_ICLASS_PANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_PANDN_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1658*/ XED_DEF_INST(XED_ICLASS_PANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_PANDN_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1659*/ XED_DEF_INST(XED_ICLASS_PANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_PANDN_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1660*/ XED_DEF_INST(XED_ICLASS_PANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_PANDN_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1661*/ XED_DEF_INST(XED_ICLASS_PSUBSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBSB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1662*/ XED_DEF_INST(XED_ICLASS_PSUBSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBSB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1663*/ XED_DEF_INST(XED_ICLASS_PSUBSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBSB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1664*/ XED_DEF_INST(XED_ICLASS_PSUBSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBSB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1665*/ XED_DEF_INST(XED_ICLASS_PSUBSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1666*/ XED_DEF_INST(XED_ICLASS_PSUBSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1667*/ XED_DEF_INST(XED_ICLASS_PSUBSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1668*/ XED_DEF_INST(XED_ICLASS_PSUBSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1669*/ XED_DEF_INST(XED_ICLASS_PMINSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMINSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1670*/ XED_DEF_INST(XED_ICLASS_PMINSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMINSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1671*/ XED_DEF_INST(XED_ICLASS_PMINSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMINSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1672*/ XED_DEF_INST(XED_ICLASS_PMINSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMINSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1673*/ XED_DEF_INST(XED_ICLASS_POR,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_POR_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_INVALID), +/*1674*/ XED_DEF_INST(XED_ICLASS_POR,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_POR_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_INVALID), +/*1675*/ XED_DEF_INST(XED_ICLASS_POR,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_POR_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1676*/ XED_DEF_INST(XED_ICLASS_POR,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_POR_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1677*/ XED_DEF_INST(XED_ICLASS_PADDSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDSB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1678*/ XED_DEF_INST(XED_ICLASS_PADDSB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDSB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1679*/ XED_DEF_INST(XED_ICLASS_PADDSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDSB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1680*/ XED_DEF_INST(XED_ICLASS_PADDSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDSB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1681*/ XED_DEF_INST(XED_ICLASS_PADDSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1682*/ XED_DEF_INST(XED_ICLASS_PADDSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1683*/ XED_DEF_INST(XED_ICLASS_PADDSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1684*/ XED_DEF_INST(XED_ICLASS_PADDSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1685*/ XED_DEF_INST(XED_ICLASS_PMAXSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMAXSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1686*/ XED_DEF_INST(XED_ICLASS_PMAXSW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PMAXSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1687*/ XED_DEF_INST(XED_ICLASS_PMAXSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMAXSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1688*/ XED_DEF_INST(XED_ICLASS_PMAXSW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PMAXSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1689*/ XED_DEF_INST(XED_ICLASS_PXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_PXOR_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1690*/ XED_DEF_INST(XED_ICLASS_PXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_MMX,3,XED_IFORM_PXOR_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1691*/ XED_DEF_INST(XED_ICLASS_PXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_PXOR_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1692*/ XED_DEF_INST(XED_ICLASS_PXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE2,3,XED_IFORM_PXOR_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1693*/ XED_DEF_INST(XED_ICLASS_PSUBB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1694*/ XED_DEF_INST(XED_ICLASS_PSUBB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1695*/ XED_DEF_INST(XED_ICLASS_PSUBB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1696*/ XED_DEF_INST(XED_ICLASS_PSUBB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1697*/ XED_DEF_INST(XED_ICLASS_PSUBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1698*/ XED_DEF_INST(XED_ICLASS_PSUBW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1699*/ XED_DEF_INST(XED_ICLASS_PSUBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1700*/ XED_DEF_INST(XED_ICLASS_PSUBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1701*/ XED_DEF_INST(XED_ICLASS_PSUBD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBD_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1702*/ XED_DEF_INST(XED_ICLASS_PSUBD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PSUBD_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1703*/ XED_DEF_INST(XED_ICLASS_PSUBD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1704*/ XED_DEF_INST(XED_ICLASS_PSUBD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1705*/ XED_DEF_INST(XED_ICLASS_PSUBQ,XED_CATEGORY_MMX,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBQ_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1706*/ XED_DEF_INST(XED_ICLASS_PSUBQ,XED_CATEGORY_MMX,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBQ_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1707*/ XED_DEF_INST(XED_ICLASS_PSUBQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1708*/ XED_DEF_INST(XED_ICLASS_PSUBQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PSUBQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1709*/ XED_DEF_INST(XED_ICLASS_PADDB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1710*/ XED_DEF_INST(XED_ICLASS_PADDB,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1711*/ XED_DEF_INST(XED_ICLASS_PADDB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1712*/ XED_DEF_INST(XED_ICLASS_PADDB,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1713*/ XED_DEF_INST(XED_ICLASS_PADDW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1714*/ XED_DEF_INST(XED_ICLASS_PADDW,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1715*/ XED_DEF_INST(XED_ICLASS_PADDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDW_XMMdq_MEMdq,1535,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1716*/ XED_DEF_INST(XED_ICLASS_PADDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDW_XMMdq_XMMdq,1537,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1717*/ XED_DEF_INST(XED_ICLASS_PADDD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDD_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1718*/ XED_DEF_INST(XED_ICLASS_PADDD,XED_CATEGORY_MMX,XED_EXTENSION_MMX,3,XED_IFORM_PADDD_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1719*/ XED_DEF_INST(XED_ICLASS_PADDD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1720*/ XED_DEF_INST(XED_ICLASS_PADDD,XED_CATEGORY_SSE,XED_EXTENSION_SSE2,3,XED_IFORM_PADDD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1721*/ XED_DEF_INST(XED_ICLASS_PHADDW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1722*/ XED_DEF_INST(XED_ICLASS_PHADDW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1723*/ XED_DEF_INST(XED_ICLASS_PHADDW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1724*/ XED_DEF_INST(XED_ICLASS_PHADDW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1725*/ XED_DEF_INST(XED_ICLASS_PHADDD,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDD_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1726*/ XED_DEF_INST(XED_ICLASS_PHADDD,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDD_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1727*/ XED_DEF_INST(XED_ICLASS_PHADDD,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1728*/ XED_DEF_INST(XED_ICLASS_PHADDD,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1729*/ XED_DEF_INST(XED_ICLASS_PHADDSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1730*/ XED_DEF_INST(XED_ICLASS_PHADDSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1731*/ XED_DEF_INST(XED_ICLASS_PHADDSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1732*/ XED_DEF_INST(XED_ICLASS_PHADDSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHADDSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1733*/ XED_DEF_INST(XED_ICLASS_PHSUBW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1734*/ XED_DEF_INST(XED_ICLASS_PHSUBW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1735*/ XED_DEF_INST(XED_ICLASS_PHSUBW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1736*/ XED_DEF_INST(XED_ICLASS_PHSUBW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1737*/ XED_DEF_INST(XED_ICLASS_PHSUBD,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBD_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1738*/ XED_DEF_INST(XED_ICLASS_PHSUBD,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBD_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1739*/ XED_DEF_INST(XED_ICLASS_PHSUBD,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1740*/ XED_DEF_INST(XED_ICLASS_PHSUBD,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1741*/ XED_DEF_INST(XED_ICLASS_PHSUBSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1742*/ XED_DEF_INST(XED_ICLASS_PHSUBSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1743*/ XED_DEF_INST(XED_ICLASS_PHSUBSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1744*/ XED_DEF_INST(XED_ICLASS_PHSUBSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PHSUBSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1745*/ XED_DEF_INST(XED_ICLASS_PMADDUBSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PMADDUBSW_MMXq_MEMq,1539,2,0,0,91,XED_EXCEPTION_MMX_MEM), +/*1746*/ XED_DEF_INST(XED_ICLASS_PMADDUBSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PMADDUBSW_MMXq_MMXq,1541,2,0,0,91,XED_EXCEPTION_MMX_MEM), +/*1747*/ XED_DEF_INST(XED_ICLASS_PMADDUBSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PMADDUBSW_XMMdq_MEMdq,1543,2,0,0,97,XED_EXCEPTION_SSE_TYPE_4), +/*1748*/ XED_DEF_INST(XED_ICLASS_PMADDUBSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PMADDUBSW_XMMdq_XMMdq,1545,2,0,0,97,XED_EXCEPTION_SSE_TYPE_4), +/*1749*/ XED_DEF_INST(XED_ICLASS_PMULHRSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PMULHRSW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1750*/ XED_DEF_INST(XED_ICLASS_PMULHRSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PMULHRSW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1751*/ XED_DEF_INST(XED_ICLASS_PMULHRSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PMULHRSW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1752*/ XED_DEF_INST(XED_ICLASS_PMULHRSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PMULHRSW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1753*/ XED_DEF_INST(XED_ICLASS_PSHUFB,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSHUFB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1754*/ XED_DEF_INST(XED_ICLASS_PSHUFB,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSHUFB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1755*/ XED_DEF_INST(XED_ICLASS_PSHUFB,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSHUFB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1756*/ XED_DEF_INST(XED_ICLASS_PSHUFB,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSHUFB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1757*/ XED_DEF_INST(XED_ICLASS_PSIGNB,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNB_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1758*/ XED_DEF_INST(XED_ICLASS_PSIGNB,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNB_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1759*/ XED_DEF_INST(XED_ICLASS_PSIGNB,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1760*/ XED_DEF_INST(XED_ICLASS_PSIGNB,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1761*/ XED_DEF_INST(XED_ICLASS_PSIGNW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNW_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1762*/ XED_DEF_INST(XED_ICLASS_PSIGNW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNW_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1763*/ XED_DEF_INST(XED_ICLASS_PSIGNW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1764*/ XED_DEF_INST(XED_ICLASS_PSIGNW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGNW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1765*/ XED_DEF_INST(XED_ICLASS_PSIGND,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGND_MMXq_MEMq,1688,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1766*/ XED_DEF_INST(XED_ICLASS_PSIGND,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGND_MMXq_MMXq,1718,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1767*/ XED_DEF_INST(XED_ICLASS_PSIGND,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGND_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1768*/ XED_DEF_INST(XED_ICLASS_PSIGND,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PSIGND_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1769*/ XED_DEF_INST(XED_ICLASS_PALIGNR,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PALIGNR_MMXq_MEMq_IMMb,1913,3,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1770*/ XED_DEF_INST(XED_ICLASS_PALIGNR,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PALIGNR_MMXq_MMXq_IMMb,1916,3,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1771*/ XED_DEF_INST(XED_ICLASS_PALIGNR,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PALIGNR_XMMdq_MEMdq_IMMb,1919,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1772*/ XED_DEF_INST(XED_ICLASS_PALIGNR,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PALIGNR_XMMdq_XMMdq_IMMb,1922,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1773*/ XED_DEF_INST(XED_ICLASS_PABSB,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSB_MMXq_MEMq,1854,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1774*/ XED_DEF_INST(XED_ICLASS_PABSB,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSB_MMXq_MMXq,1860,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1775*/ XED_DEF_INST(XED_ICLASS_PABSB,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSB_XMMdq_MEMdq,1864,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1776*/ XED_DEF_INST(XED_ICLASS_PABSB,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSB_XMMdq_XMMdq,1866,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1777*/ XED_DEF_INST(XED_ICLASS_PABSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSW_MMXq_MEMq,1854,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1778*/ XED_DEF_INST(XED_ICLASS_PABSW,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSW_MMXq_MMXq,1860,2,0,0,1,XED_EXCEPTION_MMX_MEM), +/*1779*/ XED_DEF_INST(XED_ICLASS_PABSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSW_XMMdq_MEMdq,1864,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1780*/ XED_DEF_INST(XED_ICLASS_PABSW,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSW_XMMdq_XMMdq,1866,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1781*/ XED_DEF_INST(XED_ICLASS_PABSD,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSD_MMXq_MEMq,1854,2,0,0,98,XED_EXCEPTION_MMX_MEM), +/*1782*/ XED_DEF_INST(XED_ICLASS_PABSD,XED_CATEGORY_MMX,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSD_MMXq_MMXq,1860,2,0,0,98,XED_EXCEPTION_INVALID), +/*1783*/ XED_DEF_INST(XED_ICLASS_PABSD,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSD_XMMdq_MEMdq,1864,2,0,0,99,XED_EXCEPTION_SSE_TYPE_4), +/*1784*/ XED_DEF_INST(XED_ICLASS_PABSD,XED_CATEGORY_SSE,XED_EXTENSION_SSSE3,3,XED_IFORM_PABSD_XMMdq_XMMdq,1866,2,0,0,80,XED_EXCEPTION_SSE_TYPE_4), +/*1785*/ XED_DEF_INST(XED_ICLASS_POPCNT,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_POPCNT_GPRv_MEMv,1925,3,69,0,100,XED_EXCEPTION_INVALID), +/*1786*/ XED_DEF_INST(XED_ICLASS_POPCNT,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_POPCNT_GPRv_GPRv,1928,3,69,0,100,XED_EXCEPTION_INVALID), +/*1787*/ XED_DEF_INST(XED_ICLASS_PCMPGTQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPGTQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1788*/ XED_DEF_INST(XED_ICLASS_PCMPGTQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPGTQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1789*/ XED_DEF_INST(XED_ICLASS_CRC32,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_CRC32_GPRyy_MEMb,1931,2,0,0,100,XED_EXCEPTION_INVALID), +/*1790*/ XED_DEF_INST(XED_ICLASS_CRC32,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_CRC32_GPRyy_GPR8b,1933,2,0,0,100,XED_EXCEPTION_INVALID), +/*1791*/ XED_DEF_INST(XED_ICLASS_CRC32,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_CRC32_GPRyy_MEMv,1935,2,0,0,100,XED_EXCEPTION_INVALID), +/*1792*/ XED_DEF_INST(XED_ICLASS_CRC32,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_CRC32_GPRyy_GPRv,1937,2,0,0,100,XED_EXCEPTION_INVALID), +/*1793*/ XED_DEF_INST(XED_ICLASS_BLENDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDPD_XMMdq_MEMdq_IMMb,1939,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1794*/ XED_DEF_INST(XED_ICLASS_BLENDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDPD_XMMdq_XMMdq_IMMb,1942,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1795*/ XED_DEF_INST(XED_ICLASS_BLENDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDPS_XMMdq_MEMdq_IMMb,1945,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1796*/ XED_DEF_INST(XED_ICLASS_BLENDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDPS_XMMdq_XMMdq_IMMb,1948,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1797*/ XED_DEF_INST(XED_ICLASS_BLENDVPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDVPD_XMMdq_MEMdq,1951,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1798*/ XED_DEF_INST(XED_ICLASS_BLENDVPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDVPD_XMMdq_XMMdq,1954,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1799*/ XED_DEF_INST(XED_ICLASS_BLENDVPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDVPS_XMMdq_MEMdq,1957,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1800*/ XED_DEF_INST(XED_ICLASS_BLENDVPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_BLENDVPS_XMMdq_XMMdq,1960,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1801*/ XED_DEF_INST(XED_ICLASS_PCMPEQQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPEQQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1802*/ XED_DEF_INST(XED_ICLASS_PCMPEQQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPEQQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1803*/ XED_DEF_INST(XED_ICLASS_DPPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_DPPD_XMMdq_MEMdq_IMMb,1939,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2D), +/*1804*/ XED_DEF_INST(XED_ICLASS_DPPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_DPPD_XMMdq_XMMdq_IMMb,1942,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2D), +/*1805*/ XED_DEF_INST(XED_ICLASS_DPPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_DPPS_XMMdq_MEMdq_IMMb,1945,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2D), +/*1806*/ XED_DEF_INST(XED_ICLASS_DPPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_DPPS_XMMdq_XMMdq_IMMb,1948,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2D), +/*1807*/ XED_DEF_INST(XED_ICLASS_MOVNTDQA,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_MOVNTDQA_XMMdq_MEMdq,1864,2,0,0,90,XED_EXCEPTION_SSE_TYPE_1), +/*1808*/ XED_DEF_INST(XED_ICLASS_EXTRACTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_EXTRACTPS_MEMd_XMMps_IMMb,1963,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1809*/ XED_DEF_INST(XED_ICLASS_EXTRACTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_EXTRACTPS_GPR32d_XMMdq_IMMb,1966,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1810*/ XED_DEF_INST(XED_ICLASS_INSERTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_INSERTPS_XMMps_MEMd_IMMb,1969,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1811*/ XED_DEF_INST(XED_ICLASS_INSERTPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_INSERTPS_XMMps_XMMps_IMMb,1625,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1812*/ XED_DEF_INST(XED_ICLASS_MPSADBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_MPSADBW_XMMdq_MEMdq_IMMb,1972,3,0,0,97,XED_EXCEPTION_SSE_TYPE_4), +/*1813*/ XED_DEF_INST(XED_ICLASS_MPSADBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_MPSADBW_XMMdq_XMMdq_IMMb,1975,3,0,0,97,XED_EXCEPTION_SSE_TYPE_4), +/*1814*/ XED_DEF_INST(XED_ICLASS_PACKUSDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PACKUSDW_XMMdq_MEMdq,776,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1815*/ XED_DEF_INST(XED_ICLASS_PACKUSDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PACKUSDW_XMMdq_XMMdq,778,2,0,0,85,XED_EXCEPTION_SSE_TYPE_4), +/*1816*/ XED_DEF_INST(XED_ICLASS_PBLENDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PBLENDW_XMMdq_MEMdq_IMMb,1919,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1817*/ XED_DEF_INST(XED_ICLASS_PBLENDW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PBLENDW_XMMdq_XMMdq_IMMb,1922,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1818*/ XED_DEF_INST(XED_ICLASS_PBLENDVB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PBLENDVB_XMMdq_MEMdq,1978,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1819*/ XED_DEF_INST(XED_ICLASS_PBLENDVB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PBLENDVB_XMMdq_XMMdq,1981,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1820*/ XED_DEF_INST(XED_ICLASS_PEXTRB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRB_MEMb_XMMdq_IMMb,1984,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1821*/ XED_DEF_INST(XED_ICLASS_PEXTRB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRB_GPR32d_XMMdq_IMMb,1966,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1822*/ XED_DEF_INST(XED_ICLASS_PEXTRW_SSE4,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRW_SSE4_MEMw_XMMdq_IMMb,1987,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1823*/ XED_DEF_INST(XED_ICLASS_PEXTRW_SSE4,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRW_SSE4_GPR32_XMMdq_IMMb,1990,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1824*/ XED_DEF_INST(XED_ICLASS_PEXTRQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRQ_MEMq_XMMdq_IMMb,1993,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1825*/ XED_DEF_INST(XED_ICLASS_PEXTRQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRQ_GPR64q_XMMdq_IMMb,1996,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1826*/ XED_DEF_INST(XED_ICLASS_PEXTRD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRD_MEMd_XMMdq_IMMb,1999,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1827*/ XED_DEF_INST(XED_ICLASS_PEXTRD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PEXTRD_GPR32d_XMMdq_IMMb,1966,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1828*/ XED_DEF_INST(XED_ICLASS_PINSRB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PINSRB_XMMdq_MEMb_IMMb,2002,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1829*/ XED_DEF_INST(XED_ICLASS_PINSRB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PINSRB_XMMdq_GPR32d_IMMb,2005,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1830*/ XED_DEF_INST(XED_ICLASS_PINSRD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PINSRD_XMMdq_MEMd_IMMb,2008,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1831*/ XED_DEF_INST(XED_ICLASS_PINSRD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PINSRD_XMMdq_GPR32d_IMMb,2005,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1832*/ XED_DEF_INST(XED_ICLASS_PINSRQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PINSRQ_XMMdq_MEMq_IMMb,2011,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1833*/ XED_DEF_INST(XED_ICLASS_PINSRQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PINSRQ_XMMdq_GPR64q_IMMb,2014,3,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1834*/ XED_DEF_INST(XED_ICLASS_ROUNDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDPD_XMMpd_MEMpd_IMMb,2017,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1835*/ XED_DEF_INST(XED_ICLASS_ROUNDPD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDPD_XMMpd_XMMpd_IMMb,2020,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1836*/ XED_DEF_INST(XED_ICLASS_ROUNDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDPS_XMMps_MEMps_IMMb,2023,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1837*/ XED_DEF_INST(XED_ICLASS_ROUNDPS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDPS_XMMps_XMMps_IMMb,2026,3,0,0,82,XED_EXCEPTION_SSE_TYPE_2), +/*1838*/ XED_DEF_INST(XED_ICLASS_ROUNDSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDSD_XMMq_MEMq_IMMb,2029,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1839*/ XED_DEF_INST(XED_ICLASS_ROUNDSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDSD_XMMq_XMMq_IMMb,2032,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1840*/ XED_DEF_INST(XED_ICLASS_ROUNDSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDSS_XMMd_MEMd_IMMb,2035,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1841*/ XED_DEF_INST(XED_ICLASS_ROUNDSS,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_ROUNDSS_XMMd_XMMd_IMMb,2038,3,0,0,83,XED_EXCEPTION_SSE_TYPE_3), +/*1842*/ XED_DEF_INST(XED_ICLASS_PTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE4,3,XED_IFORM_PTEST_XMMdq_MEMdq,2041,3,70,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1843*/ XED_DEF_INST(XED_ICLASS_PTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_SSE4,3,XED_IFORM_PTEST_XMMdq_XMMdq,2044,3,70,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1844*/ XED_DEF_INST(XED_ICLASS_PHMINPOSUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PHMINPOSUW_XMMdq_MEMdq,1864,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1845*/ XED_DEF_INST(XED_ICLASS_PHMINPOSUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PHMINPOSUW_XMMdq_XMMdq,1866,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1846*/ XED_DEF_INST(XED_ICLASS_PMAXSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXSB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1847*/ XED_DEF_INST(XED_ICLASS_PMAXSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXSB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1848*/ XED_DEF_INST(XED_ICLASS_PMAXSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXSD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1849*/ XED_DEF_INST(XED_ICLASS_PMAXSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXSD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1850*/ XED_DEF_INST(XED_ICLASS_PMAXUD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXUD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1851*/ XED_DEF_INST(XED_ICLASS_PMAXUD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXUD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1852*/ XED_DEF_INST(XED_ICLASS_PMAXUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXUW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1853*/ XED_DEF_INST(XED_ICLASS_PMAXUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMAXUW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1854*/ XED_DEF_INST(XED_ICLASS_PMINSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINSB_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1855*/ XED_DEF_INST(XED_ICLASS_PMINSB,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINSB_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1856*/ XED_DEF_INST(XED_ICLASS_PMINSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINSD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1857*/ XED_DEF_INST(XED_ICLASS_PMINSD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINSD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1858*/ XED_DEF_INST(XED_ICLASS_PMINUD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINUD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1859*/ XED_DEF_INST(XED_ICLASS_PMINUD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINUD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1860*/ XED_DEF_INST(XED_ICLASS_PMINUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINUW_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1861*/ XED_DEF_INST(XED_ICLASS_PMINUW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMINUW_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1862*/ XED_DEF_INST(XED_ICLASS_PMULLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMULLD_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1863*/ XED_DEF_INST(XED_ICLASS_PMULLD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMULLD_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1864*/ XED_DEF_INST(XED_ICLASS_PMULDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMULDQ_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1865*/ XED_DEF_INST(XED_ICLASS_PMULDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMULDQ_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1866*/ XED_DEF_INST(XED_ICLASS_PMOVSXBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXBW_XMMdq_MEMq,2047,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1867*/ XED_DEF_INST(XED_ICLASS_PMOVSXBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXBW_XMMdq_XMMq,2049,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1868*/ XED_DEF_INST(XED_ICLASS_PMOVSXBD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXBD_XMMdq_MEMd,2051,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1869*/ XED_DEF_INST(XED_ICLASS_PMOVSXBD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXBD_XMMdq_XMMd,2053,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1870*/ XED_DEF_INST(XED_ICLASS_PMOVSXBQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXBQ_XMMdq_MEMw,2055,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1871*/ XED_DEF_INST(XED_ICLASS_PMOVSXBQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXBQ_XMMdq_XMMw,2057,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1872*/ XED_DEF_INST(XED_ICLASS_PMOVSXWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXWD_XMMdq_MEMq,2059,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1873*/ XED_DEF_INST(XED_ICLASS_PMOVSXWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXWD_XMMdq_XMMq,2061,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1874*/ XED_DEF_INST(XED_ICLASS_PMOVSXWQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXWQ_XMMdq_MEMd,2063,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1875*/ XED_DEF_INST(XED_ICLASS_PMOVSXWQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXWQ_XMMdq_XMMd,2065,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1876*/ XED_DEF_INST(XED_ICLASS_PMOVSXDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXDQ_XMMdq_MEMq,2067,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1877*/ XED_DEF_INST(XED_ICLASS_PMOVSXDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVSXDQ_XMMdq_XMMq,2069,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1878*/ XED_DEF_INST(XED_ICLASS_PMOVZXBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXBW_XMMdq_MEMq,2071,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1879*/ XED_DEF_INST(XED_ICLASS_PMOVZXBW,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXBW_XMMdq_XMMq,2073,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1880*/ XED_DEF_INST(XED_ICLASS_PMOVZXBD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXBD_XMMdq_MEMd,2075,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1881*/ XED_DEF_INST(XED_ICLASS_PMOVZXBD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXBD_XMMdq_XMMd,2077,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1882*/ XED_DEF_INST(XED_ICLASS_PMOVZXBQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXBQ_XMMdq_MEMw,2079,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1883*/ XED_DEF_INST(XED_ICLASS_PMOVZXBQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXBQ_XMMdq_XMMw,2081,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1884*/ XED_DEF_INST(XED_ICLASS_PMOVZXWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXWD_XMMdq_MEMq,2083,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1885*/ XED_DEF_INST(XED_ICLASS_PMOVZXWD,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXWD_XMMdq_XMMq,2085,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1886*/ XED_DEF_INST(XED_ICLASS_PMOVZXWQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXWQ_XMMdq_MEMd,2087,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1887*/ XED_DEF_INST(XED_ICLASS_PMOVZXWQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXWQ_XMMdq_XMMd,2089,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1888*/ XED_DEF_INST(XED_ICLASS_PMOVZXDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXDQ_XMMdq_MEMq,2091,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1889*/ XED_DEF_INST(XED_ICLASS_PMOVZXDQ,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PMOVZXDQ_XMMdq_XMMq,2093,2,0,0,0,XED_EXCEPTION_SSE_TYPE_5), +/*1890*/ XED_DEF_INST(XED_ICLASS_PCMPESTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb,2095,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1891*/ XED_DEF_INST(XED_ICLASS_PCMPESTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb,2102,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1892*/ XED_DEF_INST(XED_ICLASS_PCMPESTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRI_XMMdq_MEMdq_IMMb,2095,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1893*/ XED_DEF_INST(XED_ICLASS_PCMPESTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRI_XMMdq_XMMdq_IMMb,2102,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1894*/ XED_DEF_INST(XED_ICLASS_PCMPESTRI64,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRI64_XMMdq_MEMdq_IMMb,2109,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1895*/ XED_DEF_INST(XED_ICLASS_PCMPESTRI64,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRI64_XMMdq_XMMdq_IMMb,2116,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1896*/ XED_DEF_INST(XED_ICLASS_PCMPISTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb,2123,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1897*/ XED_DEF_INST(XED_ICLASS_PCMPISTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb,2128,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1898*/ XED_DEF_INST(XED_ICLASS_PCMPISTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRI_XMMdq_MEMdq_IMMb,2123,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1899*/ XED_DEF_INST(XED_ICLASS_PCMPISTRI,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRI_XMMdq_XMMdq_IMMb,2128,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1900*/ XED_DEF_INST(XED_ICLASS_PCMPISTRI64,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRI64_XMMdq_MEMdq_IMMb,2133,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1901*/ XED_DEF_INST(XED_ICLASS_PCMPISTRI64,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRI64_XMMdq_XMMdq_IMMb,2138,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1902*/ XED_DEF_INST(XED_ICLASS_PCMPESTRM,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb,2143,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1903*/ XED_DEF_INST(XED_ICLASS_PCMPESTRM,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb,2150,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1904*/ XED_DEF_INST(XED_ICLASS_PCMPESTRM,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRM_XMMdq_MEMdq_IMMb,2143,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1905*/ XED_DEF_INST(XED_ICLASS_PCMPESTRM,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRM_XMMdq_XMMdq_IMMb,2150,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1906*/ XED_DEF_INST(XED_ICLASS_PCMPESTRM64,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRM64_XMMdq_MEMdq_IMMb,2157,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1907*/ XED_DEF_INST(XED_ICLASS_PCMPESTRM64,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPESTRM64_XMMdq_XMMdq_IMMb,2164,7,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1908*/ XED_DEF_INST(XED_ICLASS_PCMPISTRM,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRM_XMMdq_MEMdq_IMMb,2171,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1909*/ XED_DEF_INST(XED_ICLASS_PCMPISTRM,XED_CATEGORY_SSE,XED_EXTENSION_SSE4,3,XED_IFORM_PCMPISTRM_XMMdq_XMMdq_IMMb,2176,5,71,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*1910*/ XED_DEF_INST(XED_ICLASS_XGETBV,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVE,3,XED_IFORM_XGETBV,2181,4,0,0,0,XED_EXCEPTION_INVALID), +/*1911*/ XED_DEF_INST(XED_ICLASS_XSETBV,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVE,0,XED_IFORM_XSETBV,2185,4,0,0,35,XED_EXCEPTION_INVALID), +/*1912*/ XED_DEF_INST(XED_ICLASS_XSAVE,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVE,3,XED_IFORM_XSAVE_MEMmxsave,2189,4,0,0,101,XED_EXCEPTION_INVALID), +/*1913*/ XED_DEF_INST(XED_ICLASS_XRSTOR,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVE,3,XED_IFORM_XRSTOR_MEMmxsave,2193,4,0,0,102,XED_EXCEPTION_INVALID), +/*1914*/ XED_DEF_INST(XED_ICLASS_XSAVE64,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVE,3,XED_IFORM_XSAVE64_MEMmxsave,2189,4,0,0,101,XED_EXCEPTION_INVALID), +/*1915*/ XED_DEF_INST(XED_ICLASS_XRSTOR64,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVE,3,XED_IFORM_XRSTOR64_MEMmxsave,2193,4,0,0,102,XED_EXCEPTION_INVALID), +/*1916*/ XED_DEF_INST(XED_ICLASS_MOVBE,XED_CATEGORY_DATAXFER,XED_EXTENSION_MOVBE,3,XED_IFORM_MOVBE_GPRv_MEMv,744,2,0,0,14,XED_EXCEPTION_INVALID), +/*1917*/ XED_DEF_INST(XED_ICLASS_MOVBE,XED_CATEGORY_DATAXFER,XED_EXTENSION_MOVBE,3,XED_IFORM_MOVBE_MEMv_GPRv,736,2,0,0,14,XED_EXCEPTION_INVALID), +/*1918*/ XED_DEF_INST(XED_ICLASS_GETSEC,XED_CATEGORY_SYSTEM,XED_EXTENSION_SMX,3,XED_IFORM_GETSEC,2197,2,0,0,30,XED_EXCEPTION_INVALID), +/*1919*/ XED_DEF_INST(XED_ICLASS_AESKEYGENASSIST,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESKEYGENASSIST_XMMdq_XMMdq_IMMb,2199,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1920*/ XED_DEF_INST(XED_ICLASS_AESKEYGENASSIST,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESKEYGENASSIST_XMMdq_MEMdq_IMMb,2202,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1921*/ XED_DEF_INST(XED_ICLASS_AESENC,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESENC_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1922*/ XED_DEF_INST(XED_ICLASS_AESENC,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESENC_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1923*/ XED_DEF_INST(XED_ICLASS_AESENCLAST,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESENCLAST_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1924*/ XED_DEF_INST(XED_ICLASS_AESENCLAST,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESENCLAST_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1925*/ XED_DEF_INST(XED_ICLASS_AESDEC,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESDEC_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1926*/ XED_DEF_INST(XED_ICLASS_AESDEC,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESDEC_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1927*/ XED_DEF_INST(XED_ICLASS_AESDECLAST,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESDECLAST_XMMdq_XMMdq,778,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1928*/ XED_DEF_INST(XED_ICLASS_AESDECLAST,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESDECLAST_XMMdq_MEMdq,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1929*/ XED_DEF_INST(XED_ICLASS_AESIMC,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESIMC_XMMdq_XMMdq,1866,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1930*/ XED_DEF_INST(XED_ICLASS_AESIMC,XED_CATEGORY_AES,XED_EXTENSION_AES,3,XED_IFORM_AESIMC_XMMdq_MEMdq,1864,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1931*/ XED_DEF_INST(XED_ICLASS_PCLMULQDQ,XED_CATEGORY_PCLMULQDQ,XED_EXTENSION_PCLMULQDQ,3,XED_IFORM_PCLMULQDQ_XMMdq_XMMdq_IMMb,1922,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1932*/ XED_DEF_INST(XED_ICLASS_PCLMULQDQ,XED_CATEGORY_PCLMULQDQ,XED_EXTENSION_PCLMULQDQ,3,XED_IFORM_PCLMULQDQ_XMMdq_MEMdq_IMMb,1919,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*1933*/ XED_DEF_INST(XED_ICLASS_INVEPT,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_INVEPT_GPR64_MEMdq,2205,3,28,0,35,XED_EXCEPTION_INVALID), +/*1934*/ XED_DEF_INST(XED_ICLASS_INVEPT,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_INVEPT_GPR32_MEMdq,2208,3,28,0,35,XED_EXCEPTION_INVALID), +/*1935*/ XED_DEF_INST(XED_ICLASS_INVVPID,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_INVVPID_GPR64_MEMdq,2205,3,28,0,35,XED_EXCEPTION_INVALID), +/*1936*/ XED_DEF_INST(XED_ICLASS_INVVPID,XED_CATEGORY_VTX,XED_EXTENSION_VTX,0,XED_IFORM_INVVPID_GPR32_MEMdq,2208,3,28,0,35,XED_EXCEPTION_INVALID), +/*1937*/ XED_DEF_INST(XED_ICLASS_PREFETCH_EXCLUSIVE,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCH_EXCLUSIVE_MEMmprefetch,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1938*/ XED_DEF_INST(XED_ICLASS_PREFETCHW,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCHW_0F0Dr1,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1939*/ XED_DEF_INST(XED_ICLASS_PREFETCHW,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCHW_0F0Dr3,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1940*/ XED_DEF_INST(XED_ICLASS_PREFETCH_RESERVED,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCH_RESERVED_0F0Dr4,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1941*/ XED_DEF_INST(XED_ICLASS_PREFETCH_RESERVED,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCH_RESERVED_0F0Dr5,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1942*/ XED_DEF_INST(XED_ICLASS_PREFETCH_RESERVED,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCH_RESERVED_0F0Dr6,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1943*/ XED_DEF_INST(XED_ICLASS_PREFETCH_RESERVED,XED_CATEGORY_PREFETCH,XED_EXTENSION_3DNOW_PREFETCH,3,XED_IFORM_PREFETCH_RESERVED_0F0Dr7,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*1944*/ XED_DEF_INST(XED_ICLASS_XSTORE,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_RNG,3,XED_IFORM_XSTORE,2211,5,0,0,14,XED_EXCEPTION_INVALID), +/*1945*/ XED_DEF_INST(XED_ICLASS_REP_XSTORE,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_RNG,3,XED_IFORM_REP_XSTORE,2216,5,0,0,103,XED_EXCEPTION_INVALID), +/*1946*/ XED_DEF_INST(XED_ICLASS_REP_XCRYPTECB,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_AES,3,XED_IFORM_REP_XCRYPTECB,2221,7,0,0,103,XED_EXCEPTION_INVALID), +/*1947*/ XED_DEF_INST(XED_ICLASS_REP_XCRYPTCBC,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_AES,3,XED_IFORM_REP_XCRYPTCBC,2228,8,0,0,103,XED_EXCEPTION_INVALID), +/*1948*/ XED_DEF_INST(XED_ICLASS_REP_XCRYPTCTR,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_AES,3,XED_IFORM_REP_XCRYPTCTR,2228,8,0,0,103,XED_EXCEPTION_INVALID), +/*1949*/ XED_DEF_INST(XED_ICLASS_REP_XCRYPTCFB,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_AES,3,XED_IFORM_REP_XCRYPTCFB,2228,8,0,0,103,XED_EXCEPTION_INVALID), +/*1950*/ XED_DEF_INST(XED_ICLASS_REP_XCRYPTOFB,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_AES,3,XED_IFORM_REP_XCRYPTOFB,2228,8,0,0,103,XED_EXCEPTION_INVALID), +/*1951*/ XED_DEF_INST(XED_ICLASS_REP_XSHA1,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_SHA,3,XED_IFORM_REP_XSHA1,2236,6,0,0,103,XED_EXCEPTION_INVALID), +/*1952*/ XED_DEF_INST(XED_ICLASS_REP_XSHA256,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_SHA,3,XED_IFORM_REP_XSHA256,2236,6,0,0,103,XED_EXCEPTION_INVALID), +/*1953*/ XED_DEF_INST(XED_ICLASS_REP_MONTMUL,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_MONTMUL,3,XED_IFORM_REP_MONTMUL,2242,5,0,0,71,XED_EXCEPTION_INVALID), +/*1954*/ XED_DEF_INST(XED_ICLASS_REP_MONTMUL,XED_CATEGORY_VIA_PADLOCK,XED_EXTENSION_VIA_PADLOCK_MONTMUL,3,XED_IFORM_REP_MONTMUL,2247,5,0,0,71,XED_EXCEPTION_INVALID), +/*1955*/ XED_DEF_INST(XED_ICLASS_FEMMS,XED_CATEGORY_MMX,XED_EXTENSION_3DNOW,3,XED_IFORM_FEMMS,0,0,0,0,104,XED_EXCEPTION_INVALID), +/*1956*/ XED_DEF_INST(XED_ICLASS_PI2FW,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PI2FW_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1957*/ XED_DEF_INST(XED_ICLASS_PI2FW,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PI2FW_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1958*/ XED_DEF_INST(XED_ICLASS_PI2FD,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PI2FD_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1959*/ XED_DEF_INST(XED_ICLASS_PI2FD,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PI2FD_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1960*/ XED_DEF_INST(XED_ICLASS_PF2IW,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PF2IW_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1961*/ XED_DEF_INST(XED_ICLASS_PF2IW,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PF2IW_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1962*/ XED_DEF_INST(XED_ICLASS_PF2ID,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PF2ID_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1963*/ XED_DEF_INST(XED_ICLASS_PF2ID,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PF2ID_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1964*/ XED_DEF_INST(XED_ICLASS_PFNACC,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFNACC_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1965*/ XED_DEF_INST(XED_ICLASS_PFNACC,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFNACC_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1966*/ XED_DEF_INST(XED_ICLASS_PFPNACC,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFPNACC_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1967*/ XED_DEF_INST(XED_ICLASS_PFPNACC,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFPNACC_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1968*/ XED_DEF_INST(XED_ICLASS_PFCMPGE,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFCMPGE_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1969*/ XED_DEF_INST(XED_ICLASS_PFCMPGE,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFCMPGE_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1970*/ XED_DEF_INST(XED_ICLASS_PFMIN,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFMIN_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1971*/ XED_DEF_INST(XED_ICLASS_PFMIN,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFMIN_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1972*/ XED_DEF_INST(XED_ICLASS_PFRCP,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRCP_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1973*/ XED_DEF_INST(XED_ICLASS_PFRCP,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRCP_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1974*/ XED_DEF_INST(XED_ICLASS_PFRSQRT,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRSQRT_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1975*/ XED_DEF_INST(XED_ICLASS_PFRSQRT,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRSQRT_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1976*/ XED_DEF_INST(XED_ICLASS_PFSUB,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFSUB_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1977*/ XED_DEF_INST(XED_ICLASS_PFSUB,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFSUB_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1978*/ XED_DEF_INST(XED_ICLASS_PFADD,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFADD_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1979*/ XED_DEF_INST(XED_ICLASS_PFADD,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFADD_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1980*/ XED_DEF_INST(XED_ICLASS_PFCMPGT,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFCMPGT_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1981*/ XED_DEF_INST(XED_ICLASS_PFCMPGT,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFCMPGT_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1982*/ XED_DEF_INST(XED_ICLASS_PFMAX,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFMAX_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1983*/ XED_DEF_INST(XED_ICLASS_PFMAX,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFMAX_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1984*/ XED_DEF_INST(XED_ICLASS_PFRCPIT1,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRCPIT1_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1985*/ XED_DEF_INST(XED_ICLASS_PFRCPIT1,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRCPIT1_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1986*/ XED_DEF_INST(XED_ICLASS_PFRSQIT1,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRSQIT1_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1987*/ XED_DEF_INST(XED_ICLASS_PFRSQIT1,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRSQIT1_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1988*/ XED_DEF_INST(XED_ICLASS_PFSUBR,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFSUBR_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1989*/ XED_DEF_INST(XED_ICLASS_PFSUBR,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFSUBR_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1990*/ XED_DEF_INST(XED_ICLASS_PFACC,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFACC_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1991*/ XED_DEF_INST(XED_ICLASS_PFACC,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFACC_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1992*/ XED_DEF_INST(XED_ICLASS_PFCMPEQ,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFCMPEQ_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1993*/ XED_DEF_INST(XED_ICLASS_PFCMPEQ,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFCMPEQ_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1994*/ XED_DEF_INST(XED_ICLASS_PFMUL,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFMUL_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1995*/ XED_DEF_INST(XED_ICLASS_PFMUL,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFMUL_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1996*/ XED_DEF_INST(XED_ICLASS_PFRCPIT2,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRCPIT2_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1997*/ XED_DEF_INST(XED_ICLASS_PFRCPIT2,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PFRCPIT2_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*1998*/ XED_DEF_INST(XED_ICLASS_PMULHRW,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PMULHRW_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*1999*/ XED_DEF_INST(XED_ICLASS_PMULHRW,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PMULHRW_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*2000*/ XED_DEF_INST(XED_ICLASS_PSWAPD,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PSWAPD_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*2001*/ XED_DEF_INST(XED_ICLASS_PSWAPD,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PSWAPD_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*2002*/ XED_DEF_INST(XED_ICLASS_PAVGUSB,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PAVGUSB_MMXq_MEMq,1688,2,0,0,105,XED_EXCEPTION_INVALID), +/*2003*/ XED_DEF_INST(XED_ICLASS_PAVGUSB,XED_CATEGORY_3DNOW,XED_EXTENSION_3DNOW,3,XED_IFORM_PAVGUSB_MMXq_MMXq,1718,2,0,0,105,XED_EXCEPTION_INVALID), +/*2004*/ XED_DEF_INST(XED_ICLASS_SYSCALL_AMD,XED_CATEGORY_SYSCALL,XED_EXTENSION_BASE,3,XED_IFORM_SYSCALL_AMD,1894,2,61,0,105,XED_EXCEPTION_INVALID), +/*2005*/ XED_DEF_INST(XED_ICLASS_SYSRET_AMD,XED_CATEGORY_SYSRET,XED_EXTENSION_BASE,0,XED_IFORM_SYSRET_AMD,2252,2,62,0,106,XED_EXCEPTION_INVALID), +/*2006*/ XED_DEF_INST(XED_ICLASS_VMRUN,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_VMRUN_ArAX,2254,1,0,0,107,XED_EXCEPTION_INVALID), +/*2007*/ XED_DEF_INST(XED_ICLASS_VMMCALL,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_VMMCALL,0,0,0,0,105,XED_EXCEPTION_INVALID), +/*2008*/ XED_DEF_INST(XED_ICLASS_VMLOAD,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_VMLOAD_ArAX,2254,1,0,0,107,XED_EXCEPTION_INVALID), +/*2009*/ XED_DEF_INST(XED_ICLASS_VMSAVE,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_VMSAVE,0,0,0,0,107,XED_EXCEPTION_INVALID), +/*2010*/ XED_DEF_INST(XED_ICLASS_STGI,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_STGI,0,0,0,0,107,XED_EXCEPTION_INVALID), +/*2011*/ XED_DEF_INST(XED_ICLASS_CLGI,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_CLGI,0,0,0,0,107,XED_EXCEPTION_INVALID), +/*2012*/ XED_DEF_INST(XED_ICLASS_SKINIT,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,3,XED_IFORM_SKINIT_EAX,2255,1,0,0,107,XED_EXCEPTION_INVALID), +/*2013*/ XED_DEF_INST(XED_ICLASS_INVLPGA,XED_CATEGORY_SYSTEM,XED_EXTENSION_SVM,0,XED_IFORM_INVLPGA_ArAX_ECX,2256,2,0,0,107,XED_EXCEPTION_INVALID), +/*2014*/ XED_DEF_INST(XED_ICLASS_EXTRQ,XED_CATEGORY_BITBYTE,XED_EXTENSION_SSE4A,3,XED_IFORM_EXTRQ_XMMq_IMMb_IMMb,2258,3,0,0,108,XED_EXCEPTION_INVALID), +/*2015*/ XED_DEF_INST(XED_ICLASS_EXTRQ,XED_CATEGORY_BITBYTE,XED_EXTENSION_SSE4A,3,XED_IFORM_EXTRQ_XMMq_XMMdq,2261,2,0,0,108,XED_EXCEPTION_INVALID), +/*2016*/ XED_DEF_INST(XED_ICLASS_INSERTQ,XED_CATEGORY_BITBYTE,XED_EXTENSION_SSE4A,3,XED_IFORM_INSERTQ_XMMq_XMMq_IMMb_IMMb,2263,4,0,0,108,XED_EXCEPTION_INVALID), +/*2017*/ XED_DEF_INST(XED_ICLASS_INSERTQ,XED_CATEGORY_BITBYTE,XED_EXTENSION_SSE4A,3,XED_IFORM_INSERTQ_XMMq_XMMdq,2261,2,0,0,108,XED_EXCEPTION_INVALID), +/*2018*/ XED_DEF_INST(XED_ICLASS_MOVNTSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE4A,3,XED_IFORM_MOVNTSD_MEMq_XMMq,1848,2,0,0,109,XED_EXCEPTION_INVALID), +/*2019*/ XED_DEF_INST(XED_ICLASS_MOVNTSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_SSE4A,3,XED_IFORM_MOVNTSS_MEMd_XMMd,1834,2,0,0,109,XED_EXCEPTION_INVALID), +/*2020*/ XED_DEF_INST(XED_ICLASS_CLZERO,XED_CATEGORY_CLZERO,XED_EXTENSION_CLZERO,3,XED_IFORM_CLZERO,2267,1,0,0,105,XED_EXCEPTION_INVALID), +/*2021*/ XED_DEF_INST(XED_ICLASS_MONITORX,XED_CATEGORY_MISC,XED_EXTENSION_MONITORX,3,XED_IFORM_MONITORX,857,3,0,0,105,XED_EXCEPTION_INVALID), +/*2022*/ XED_DEF_INST(XED_ICLASS_MONITORX,XED_CATEGORY_MISC,XED_EXTENSION_MONITORX,3,XED_IFORM_MONITORX,860,3,0,0,105,XED_EXCEPTION_INVALID), +/*2023*/ XED_DEF_INST(XED_ICLASS_MONITORX,XED_CATEGORY_MISC,XED_EXTENSION_MONITORX,3,XED_IFORM_MONITORX,863,3,0,0,105,XED_EXCEPTION_INVALID), +/*2024*/ XED_DEF_INST(XED_ICLASS_MONITORX,XED_CATEGORY_MISC,XED_EXTENSION_MONITORX,3,XED_IFORM_MONITORX,857,3,0,0,105,XED_EXCEPTION_INVALID), +/*2025*/ XED_DEF_INST(XED_ICLASS_MWAITX,XED_CATEGORY_MISC,XED_EXTENSION_MONITORX,3,XED_IFORM_MWAITX,2268,2,0,0,105,XED_EXCEPTION_INVALID), +/*2026*/ XED_DEF_INST(XED_ICLASS_MCOMMIT,XED_CATEGORY_MISC,XED_EXTENSION_MCOMMIT,3,XED_IFORM_MCOMMIT,848,1,72,0,105,XED_EXCEPTION_INVALID), +/*2027*/ XED_DEF_INST(XED_ICLASS_RDPRU,XED_CATEGORY_RDPRU,XED_EXTENSION_RDPRU,3,XED_IFORM_RDPRU,2270,3,0,0,105,XED_EXCEPTION_INVALID), +/*2028*/ XED_DEF_INST(XED_ICLASS_PSMASH,XED_CATEGORY_SYSTEM,XED_EXTENSION_SNP,0,XED_IFORM_PSMASH_RAX,2273,2,25,0,105,XED_EXCEPTION_INVALID), +/*2029*/ XED_DEF_INST(XED_ICLASS_PVALIDATE,XED_CATEGORY_SYSTEM,XED_EXTENSION_SNP,0,XED_IFORM_PVALIDATE_RAX_ECX_EDX,2275,4,10,0,105,XED_EXCEPTION_INVALID), +/*2030*/ XED_DEF_INST(XED_ICLASS_RMPADJUST,XED_CATEGORY_SYSTEM,XED_EXTENSION_SNP,0,XED_IFORM_RMPADJUST_RAX_RCX_RDX,2279,4,25,0,105,XED_EXCEPTION_INVALID), +/*2031*/ XED_DEF_INST(XED_ICLASS_RMPUPDATE,XED_CATEGORY_SYSTEM,XED_EXTENSION_SNP,0,XED_IFORM_RMPUPDATE_RAX_RCX,2283,3,25,0,105,XED_EXCEPTION_INVALID), +/*2032*/ XED_DEF_INST(XED_ICLASS_INVLPGB,XED_CATEGORY_SYSTEM,XED_EXTENSION_AMD_INVLPGB,0,XED_IFORM_INVLPGB_EAX_EDX_ECX,2286,3,0,0,105,XED_EXCEPTION_INVALID), +/*2033*/ XED_DEF_INST(XED_ICLASS_INVLPGB,XED_CATEGORY_SYSTEM,XED_EXTENSION_AMD_INVLPGB,0,XED_IFORM_INVLPGB_RAX_EDX_ECX,2289,3,0,0,105,XED_EXCEPTION_INVALID), +/*2034*/ XED_DEF_INST(XED_ICLASS_TLBSYNC,XED_CATEGORY_SYSTEM,XED_EXTENSION_AMD_INVLPGB,0,XED_IFORM_TLBSYNC,0,0,0,0,105,XED_EXCEPTION_INVALID), +/*2035*/ XED_DEF_INST(XED_ICLASS_BNDMK,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMK_BND_AGEN,2292,2,0,0,110,XED_EXCEPTION_INVALID), +/*2036*/ XED_DEF_INST(XED_ICLASS_BNDCL,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCL_BND_AGEN,2294,2,0,0,111,XED_EXCEPTION_INVALID), +/*2037*/ XED_DEF_INST(XED_ICLASS_BNDCL,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCL_BND_GPR64,2296,2,0,0,111,XED_EXCEPTION_INVALID), +/*2038*/ XED_DEF_INST(XED_ICLASS_BNDCL,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCL_BND_GPR32,2298,2,0,0,111,XED_EXCEPTION_INVALID), +/*2039*/ XED_DEF_INST(XED_ICLASS_BNDCU,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCU_BND_AGEN,2294,2,0,0,111,XED_EXCEPTION_INVALID), +/*2040*/ XED_DEF_INST(XED_ICLASS_BNDCU,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCU_BND_GPR64,2296,2,0,0,111,XED_EXCEPTION_INVALID), +/*2041*/ XED_DEF_INST(XED_ICLASS_BNDCU,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCU_BND_GPR32,2298,2,0,0,111,XED_EXCEPTION_INVALID), +/*2042*/ XED_DEF_INST(XED_ICLASS_BNDCN,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCN_BND_AGEN,2294,2,0,0,111,XED_EXCEPTION_INVALID), +/*2043*/ XED_DEF_INST(XED_ICLASS_BNDCN,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCN_BND_GPR64,2296,2,0,0,111,XED_EXCEPTION_INVALID), +/*2044*/ XED_DEF_INST(XED_ICLASS_BNDCN,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDCN_BND_GPR32,2298,2,0,0,111,XED_EXCEPTION_INVALID), +/*2045*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_BND_BND,2300,2,0,0,0,XED_EXCEPTION_INVALID), +/*2046*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_BND_MEMq,2302,2,0,0,0,XED_EXCEPTION_INVALID), +/*2047*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_BND_MEMq,2302,2,0,0,0,XED_EXCEPTION_INVALID), +/*2048*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_BND_MEMdq,2304,2,0,0,0,XED_EXCEPTION_INVALID), +/*2049*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_BND_BND,2306,2,0,0,0,XED_EXCEPTION_INVALID), +/*2050*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_MEMq_BND,2308,2,0,0,0,XED_EXCEPTION_INVALID), +/*2051*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_MEMq_BND,2308,2,0,0,0,XED_EXCEPTION_INVALID), +/*2052*/ XED_DEF_INST(XED_ICLASS_BNDMOV,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDMOV_MEMdq_BND,2310,2,0,0,0,XED_EXCEPTION_INVALID), +/*2053*/ XED_DEF_INST(XED_ICLASS_BNDLDX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDLDX_BND_MEMbnd32,2312,2,0,0,112,XED_EXCEPTION_INVALID), +/*2054*/ XED_DEF_INST(XED_ICLASS_BNDLDX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDLDX_BND_MEMbnd64,2314,2,0,0,112,XED_EXCEPTION_INVALID), +/*2055*/ XED_DEF_INST(XED_ICLASS_BNDLDX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDLDX_BND_MEMbnd64,2314,2,0,0,112,XED_EXCEPTION_INVALID), +/*2056*/ XED_DEF_INST(XED_ICLASS_BNDLDX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDLDX_BND_MEMbnd64,2314,2,0,0,112,XED_EXCEPTION_INVALID), +/*2057*/ XED_DEF_INST(XED_ICLASS_BNDSTX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDSTX_MEMbnd32_BND,2316,2,0,0,112,XED_EXCEPTION_INVALID), +/*2058*/ XED_DEF_INST(XED_ICLASS_BNDSTX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDSTX_MEMbnd64_BND,2318,2,0,0,112,XED_EXCEPTION_INVALID), +/*2059*/ XED_DEF_INST(XED_ICLASS_BNDSTX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDSTX_MEMbnd64_BND,2318,2,0,0,112,XED_EXCEPTION_INVALID), +/*2060*/ XED_DEF_INST(XED_ICLASS_BNDSTX,XED_CATEGORY_MPX,XED_EXTENSION_MPX,3,XED_IFORM_BNDSTX_MEMbnd64_BND,2318,2,0,0,112,XED_EXCEPTION_INVALID), +/*2061*/ XED_DEF_INST(XED_ICLASS_CLRSSBSY,XED_CATEGORY_CET,XED_EXTENSION_CET,0,XED_IFORM_CLRSSBSY_MEMu64,2320,1,0,0,0,XED_EXCEPTION_INVALID), +/*2062*/ XED_DEF_INST(XED_ICLASS_ENDBR32,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_ENDBR32,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2063*/ XED_DEF_INST(XED_ICLASS_ENDBR64,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_ENDBR64,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2064*/ XED_DEF_INST(XED_ICLASS_INCSSPD,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_INCSSPD_GPR32u8,2321,2,0,0,0,XED_EXCEPTION_INVALID), +/*2065*/ XED_DEF_INST(XED_ICLASS_INCSSPQ,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_INCSSPQ_GPR64u8,2323,2,0,0,0,XED_EXCEPTION_INVALID), +/*2066*/ XED_DEF_INST(XED_ICLASS_RDSSPD,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_RDSSPD_GPR32u32,2325,2,0,0,0,XED_EXCEPTION_INVALID), +/*2067*/ XED_DEF_INST(XED_ICLASS_RDSSPQ,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_RDSSPQ_GPR64u64,2327,2,0,0,0,XED_EXCEPTION_INVALID), +/*2068*/ XED_DEF_INST(XED_ICLASS_RSTORSSP,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_RSTORSSP_MEMu64,2329,2,0,0,0,XED_EXCEPTION_INVALID), +/*2069*/ XED_DEF_INST(XED_ICLASS_SAVEPREVSSP,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_SAVEPREVSSP,2331,1,0,0,0,XED_EXCEPTION_INVALID), +/*2070*/ XED_DEF_INST(XED_ICLASS_SETSSBSY,XED_CATEGORY_CET,XED_EXTENSION_CET,0,XED_IFORM_SETSSBSY,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2071*/ XED_DEF_INST(XED_ICLASS_WRSSD,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_WRSSD_MEMu32_GPR32u32,2332,2,0,0,0,XED_EXCEPTION_INVALID), +/*2072*/ XED_DEF_INST(XED_ICLASS_WRSSQ,XED_CATEGORY_CET,XED_EXTENSION_CET,3,XED_IFORM_WRSSQ_MEMu64_GPR64u64,2334,2,0,0,0,XED_EXCEPTION_INVALID), +/*2073*/ XED_DEF_INST(XED_ICLASS_WRUSSD,XED_CATEGORY_CET,XED_EXTENSION_CET,0,XED_IFORM_WRUSSD_MEMu32_GPR32u32,2332,2,0,0,0,XED_EXCEPTION_INVALID), +/*2074*/ XED_DEF_INST(XED_ICLASS_WRUSSQ,XED_CATEGORY_CET,XED_EXTENSION_CET,0,XED_IFORM_WRUSSQ_MEMu64_GPR64u64,2334,2,0,0,0,XED_EXCEPTION_INVALID), +/*2075*/ XED_DEF_INST(XED_ICLASS_RDRAND,XED_CATEGORY_RDRAND,XED_EXTENSION_RDRAND,3,XED_IFORM_RDRAND_GPRv,2336,2,73,0,14,XED_EXCEPTION_INVALID), +/*2076*/ XED_DEF_INST(XED_ICLASS_SHA1MSG1,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1MSG1_XMMi32_XMMi32_SHA,778,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2077*/ XED_DEF_INST(XED_ICLASS_SHA1MSG1,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1MSG1_XMMi32_MEMi32_SHA,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2078*/ XED_DEF_INST(XED_ICLASS_SHA1MSG2,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1MSG2_XMMi32_XMMi32_SHA,778,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2079*/ XED_DEF_INST(XED_ICLASS_SHA1MSG2,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1MSG2_XMMi32_MEMi32_SHA,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2080*/ XED_DEF_INST(XED_ICLASS_SHA1NEXTE,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1NEXTE_XMMi32_XMMi32_SHA,778,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2081*/ XED_DEF_INST(XED_ICLASS_SHA1NEXTE,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1NEXTE_XMMi32_MEMi32_SHA,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2082*/ XED_DEF_INST(XED_ICLASS_SHA1RNDS4,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1RNDS4_XMMi32_XMMi32_IMM8_SHA,1922,3,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2083*/ XED_DEF_INST(XED_ICLASS_SHA1RNDS4,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA1RNDS4_XMMi32_MEMi32_IMM8_SHA,1919,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2084*/ XED_DEF_INST(XED_ICLASS_SHA256MSG1,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA256MSG1_XMMi32_XMMi32_SHA,778,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2085*/ XED_DEF_INST(XED_ICLASS_SHA256MSG1,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA256MSG1_XMMi32_MEMi32_SHA,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2086*/ XED_DEF_INST(XED_ICLASS_SHA256MSG2,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA256MSG2_XMMi32_XMMi32_SHA,778,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2087*/ XED_DEF_INST(XED_ICLASS_SHA256MSG2,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA256MSG2_XMMi32_MEMi32_SHA,776,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2088*/ XED_DEF_INST(XED_ICLASS_SHA256RNDS2,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA256RNDS2_XMMi32_XMMi32_SHA,2338,3,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2089*/ XED_DEF_INST(XED_ICLASS_SHA256RNDS2,XED_CATEGORY_SHA,XED_EXTENSION_SHA,3,XED_IFORM_SHA256RNDS2_XMMi32_MEMi32_SHA,2341,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2090*/ XED_DEF_INST(XED_ICLASS_XSAVEOPT,XED_CATEGORY_XSAVEOPT,XED_EXTENSION_XSAVEOPT,3,XED_IFORM_XSAVEOPT_MEMmxsave,2189,4,0,0,113,XED_EXCEPTION_INVALID), +/*2091*/ XED_DEF_INST(XED_ICLASS_XSAVEOPT64,XED_CATEGORY_XSAVEOPT,XED_EXTENSION_XSAVEOPT,3,XED_IFORM_XSAVEOPT64_MEMmxsave,2189,4,0,0,113,XED_EXCEPTION_INVALID), +/*2092*/ XED_DEF_INST(XED_ICLASS_XSAVES,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVES,0,XED_IFORM_XSAVES_MEMmxsave,2344,4,0,0,101,XED_EXCEPTION_INVALID), +/*2093*/ XED_DEF_INST(XED_ICLASS_XSAVES64,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVES,0,XED_IFORM_XSAVES64_MEMmxsave,2344,4,0,0,101,XED_EXCEPTION_INVALID), +/*2094*/ XED_DEF_INST(XED_ICLASS_XRSTORS,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVES,0,XED_IFORM_XRSTORS_MEMmxsave,2193,4,0,0,114,XED_EXCEPTION_INVALID), +/*2095*/ XED_DEF_INST(XED_ICLASS_XRSTORS64,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVES,0,XED_IFORM_XRSTORS64_MEMmxsave,2193,4,0,0,114,XED_EXCEPTION_INVALID), +/*2096*/ XED_DEF_INST(XED_ICLASS_XSAVEC,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVEC,3,XED_IFORM_XSAVEC_MEMmxsave,2344,4,0,0,101,XED_EXCEPTION_INVALID), +/*2097*/ XED_DEF_INST(XED_ICLASS_XSAVEC64,XED_CATEGORY_XSAVE,XED_EXTENSION_XSAVEC,3,XED_IFORM_XSAVEC64_MEMmxsave,2344,4,0,0,101,XED_EXCEPTION_INVALID), +/*2098*/ XED_DEF_INST(XED_ICLASS_CLFLUSHOPT,XED_CATEGORY_CLFLUSHOPT,XED_EXTENSION_CLFLUSHOPT,3,XED_IFORM_CLFLUSHOPT_MEMmprefetch,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*2099*/ XED_DEF_INST(XED_ICLASS_RDSEED,XED_CATEGORY_RDSEED,XED_EXTENSION_RDSEED,3,XED_IFORM_RDSEED_GPRv,2336,2,73,0,14,XED_EXCEPTION_INVALID), +/*2100*/ XED_DEF_INST(XED_ICLASS_RDFSBASE,XED_CATEGORY_RDWRFSGS,XED_EXTENSION_RDWRFSGS,3,XED_IFORM_RDFSBASE_GPRy,2348,2,0,0,14,XED_EXCEPTION_INVALID), +/*2101*/ XED_DEF_INST(XED_ICLASS_RDGSBASE,XED_CATEGORY_RDWRFSGS,XED_EXTENSION_RDWRFSGS,3,XED_IFORM_RDGSBASE_GPRy,2350,2,0,0,14,XED_EXCEPTION_INVALID), +/*2102*/ XED_DEF_INST(XED_ICLASS_WRFSBASE,XED_CATEGORY_RDWRFSGS,XED_EXTENSION_RDWRFSGS,3,XED_IFORM_WRFSBASE_GPRy,2352,2,0,0,34,XED_EXCEPTION_INVALID), +/*2103*/ XED_DEF_INST(XED_ICLASS_WRGSBASE,XED_CATEGORY_RDWRFSGS,XED_EXTENSION_RDWRFSGS,3,XED_IFORM_WRGSBASE_GPRy,2354,2,0,0,34,XED_EXCEPTION_INVALID), +/*2104*/ XED_DEF_INST(XED_ICLASS_CLAC,XED_CATEGORY_SMAP,XED_EXTENSION_SMAP,0,XED_IFORM_CLAC,848,1,74,0,0,XED_EXCEPTION_INVALID), +/*2105*/ XED_DEF_INST(XED_ICLASS_STAC,XED_CATEGORY_SMAP,XED_EXTENSION_SMAP,0,XED_IFORM_STAC,848,1,75,0,0,XED_EXCEPTION_INVALID), +/*2106*/ XED_DEF_INST(XED_ICLASS_ENCLU,XED_CATEGORY_SGX,XED_EXTENSION_SGX,3,XED_IFORM_ENCLU,2356,4,0,0,0,XED_EXCEPTION_INVALID), +/*2107*/ XED_DEF_INST(XED_ICLASS_ENCLS,XED_CATEGORY_SGX,XED_EXTENSION_SGX,0,XED_IFORM_ENCLS,2356,4,0,0,0,XED_EXCEPTION_INVALID), +/*2108*/ XED_DEF_INST(XED_ICLASS_RDPID,XED_CATEGORY_RDPID,XED_EXTENSION_RDPID,3,XED_IFORM_RDPID_GPR32u32,2360,2,0,0,0,XED_EXCEPTION_INVALID), +/*2109*/ XED_DEF_INST(XED_ICLASS_RDPID,XED_CATEGORY_RDPID,XED_EXTENSION_RDPID,3,XED_IFORM_RDPID_GPR64u64,2362,2,0,0,0,XED_EXCEPTION_INVALID), +/*2110*/ XED_DEF_INST(XED_ICLASS_PTWRITE,XED_CATEGORY_PTWRITE,XED_EXTENSION_PTWRITE,3,XED_IFORM_PTWRITE_GPRy,2364,1,0,0,14,XED_EXCEPTION_INVALID), +/*2111*/ XED_DEF_INST(XED_ICLASS_PTWRITE,XED_CATEGORY_PTWRITE,XED_EXTENSION_PTWRITE,3,XED_IFORM_PTWRITE_MEMy,2365,1,0,0,14,XED_EXCEPTION_INVALID), +/*2112*/ XED_DEF_INST(XED_ICLASS_MOVDIR64B,XED_CATEGORY_MOVDIR,XED_EXTENSION_MOVDIR,3,XED_IFORM_MOVDIR64B_GPRa_MEM,2366,4,0,0,44,XED_EXCEPTION_INVALID), +/*2113*/ XED_DEF_INST(XED_ICLASS_MOVDIR64B,XED_CATEGORY_MOVDIR,XED_EXTENSION_MOVDIR,3,XED_IFORM_MOVDIR64B_GPRa_MEM,2366,4,0,0,44,XED_EXCEPTION_INVALID), +/*2114*/ XED_DEF_INST(XED_ICLASS_MOVDIRI,XED_CATEGORY_MOVDIR,XED_EXTENSION_MOVDIR,3,XED_IFORM_MOVDIRI_MEMu32_GPR32u32,2332,2,0,0,0,XED_EXCEPTION_INVALID), +/*2115*/ XED_DEF_INST(XED_ICLASS_MOVDIRI,XED_CATEGORY_MOVDIR,XED_EXTENSION_MOVDIR,3,XED_IFORM_MOVDIRI_MEMu64_GPR64u64,2334,2,0,0,0,XED_EXCEPTION_INVALID), +/*2116*/ XED_DEF_INST(XED_ICLASS_TPAUSE,XED_CATEGORY_WAITPKG,XED_EXTENSION_WAITPKG,3,XED_IFORM_TPAUSE_GPR32u32,2370,4,76,0,0,XED_EXCEPTION_INVALID), +/*2117*/ XED_DEF_INST(XED_ICLASS_UMONITOR,XED_CATEGORY_WAITPKG,XED_EXTENSION_WAITPKG,3,XED_IFORM_UMONITOR_GPRa,2374,1,0,0,1,XED_EXCEPTION_INVALID), +/*2118*/ XED_DEF_INST(XED_ICLASS_UMWAIT,XED_CATEGORY_WAITPKG,XED_EXTENSION_WAITPKG,3,XED_IFORM_UMWAIT_GPR32,2370,4,76,0,1,XED_EXCEPTION_INVALID), +/*2119*/ XED_DEF_INST(XED_ICLASS_CLDEMOTE,XED_CATEGORY_CLDEMOTE,XED_EXTENSION_CLDEMOTE,3,XED_IFORM_CLDEMOTE_MEMu8,872,1,0,0,0,XED_EXCEPTION_INVALID), +/*2120*/ XED_DEF_INST(XED_ICLASS_ENCLV,XED_CATEGORY_SGX,XED_EXTENSION_SGX_ENCLV,3,XED_IFORM_ENCLV,2375,4,0,0,0,XED_EXCEPTION_INVALID), +/*2121*/ XED_DEF_INST(XED_ICLASS_TZCNT,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_TZCNT_GPRv_MEMv,2379,3,77,0,14,XED_EXCEPTION_INVALID), +/*2122*/ XED_DEF_INST(XED_ICLASS_TZCNT,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_TZCNT_GPRv_GPRv,2382,3,77,0,14,XED_EXCEPTION_INVALID), +/*2123*/ XED_DEF_INST(XED_ICLASS_BSF,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSF_GPRv_MEMv,2385,3,78,0,14,XED_EXCEPTION_INVALID), +/*2124*/ XED_DEF_INST(XED_ICLASS_BSF,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSF_GPRv_GPRv,1384,3,78,0,14,XED_EXCEPTION_INVALID), +/*2125*/ XED_DEF_INST(XED_ICLASS_BSF,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSF_GPRv_MEMv,2385,3,78,0,14,XED_EXCEPTION_INVALID), +/*2126*/ XED_DEF_INST(XED_ICLASS_BSF,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSF_GPRv_GPRv,1384,3,78,0,14,XED_EXCEPTION_INVALID), +/*2127*/ XED_DEF_INST(XED_ICLASS_VMFUNC,XED_CATEGORY_VTX,XED_EXTENSION_VMFUNC,3,XED_IFORM_VMFUNC,2388,1,0,0,0,XED_EXCEPTION_INVALID), +/*2128*/ XED_DEF_INST(XED_ICLASS_INVPCID,XED_CATEGORY_MISC,XED_EXTENSION_INVPCID,0,XED_IFORM_INVPCID_GPR64_MEMdq,2389,2,0,0,35,XED_EXCEPTION_INVALID), +/*2129*/ XED_DEF_INST(XED_ICLASS_INVPCID,XED_CATEGORY_MISC,XED_EXTENSION_INVPCID,0,XED_IFORM_INVPCID_GPR32_MEMdq,2391,2,0,0,35,XED_EXCEPTION_INVALID), +/*2130*/ XED_DEF_INST(XED_ICLASS_LZCNT,XED_CATEGORY_LZCNT,XED_EXTENSION_LZCNT,3,XED_IFORM_LZCNT_GPRv_MEMv,1925,3,79,0,14,XED_EXCEPTION_INVALID), +/*2131*/ XED_DEF_INST(XED_ICLASS_LZCNT,XED_CATEGORY_LZCNT,XED_EXTENSION_LZCNT,3,XED_IFORM_LZCNT_GPRv_GPRv,1928,3,79,0,14,XED_EXCEPTION_INVALID), +/*2132*/ XED_DEF_INST(XED_ICLASS_BSR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSR_GPRv_MEMv,2385,3,78,0,14,XED_EXCEPTION_INVALID), +/*2133*/ XED_DEF_INST(XED_ICLASS_BSR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSR_GPRv_GPRv,1384,3,78,0,14,XED_EXCEPTION_INVALID), +/*2134*/ XED_DEF_INST(XED_ICLASS_BSR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSR_GPRv_MEMv,2385,3,78,0,14,XED_EXCEPTION_INVALID), +/*2135*/ XED_DEF_INST(XED_ICLASS_BSR,XED_CATEGORY_BITBYTE,XED_EXTENSION_BASE,3,XED_IFORM_BSR_GPRv_GPRv,1384,3,78,0,14,XED_EXCEPTION_INVALID), +/*2136*/ XED_DEF_INST(XED_ICLASS_XBEGIN,XED_CATEGORY_COND_BR,XED_EXTENSION_RTM,3,XED_IFORM_XBEGIN_RELBRz,2393,3,0,0,14,XED_EXCEPTION_INVALID), +/*2137*/ XED_DEF_INST(XED_ICLASS_XEND,XED_CATEGORY_COND_BR,XED_EXTENSION_RTM,3,XED_IFORM_XEND,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2138*/ XED_DEF_INST(XED_ICLASS_XABORT,XED_CATEGORY_UNCOND_BR,XED_EXTENSION_RTM,3,XED_IFORM_XABORT_IMMb,2396,2,0,0,0,XED_EXCEPTION_INVALID), +/*2139*/ XED_DEF_INST(XED_ICLASS_XTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_RTM,3,XED_IFORM_XTEST,848,1,80,0,0,XED_EXCEPTION_INVALID), +/*2140*/ XED_DEF_INST(XED_ICLASS_ADCX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADCX_GPR32d_GPR32d,2398,3,55,0,0,XED_EXCEPTION_INVALID), +/*2141*/ XED_DEF_INST(XED_ICLASS_ADCX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADCX_GPR32d_MEMd,2401,3,55,0,0,XED_EXCEPTION_INVALID), +/*2142*/ XED_DEF_INST(XED_ICLASS_ADCX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADCX_GPR64q_GPR64q,2404,3,55,0,0,XED_EXCEPTION_INVALID), +/*2143*/ XED_DEF_INST(XED_ICLASS_ADCX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADCX_GPR64q_MEMq,2407,3,55,0,0,XED_EXCEPTION_INVALID), +/*2144*/ XED_DEF_INST(XED_ICLASS_ADOX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADOX_GPR32d_GPR32d,2398,3,81,0,0,XED_EXCEPTION_INVALID), +/*2145*/ XED_DEF_INST(XED_ICLASS_ADOX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADOX_GPR32d_MEMd,2401,3,81,0,0,XED_EXCEPTION_INVALID), +/*2146*/ XED_DEF_INST(XED_ICLASS_ADOX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADOX_GPR64q_GPR64q,2404,3,81,0,0,XED_EXCEPTION_INVALID), +/*2147*/ XED_DEF_INST(XED_ICLASS_ADOX,XED_CATEGORY_ADOX_ADCX,XED_EXTENSION_ADOX_ADCX,3,XED_IFORM_ADOX_GPR64q_MEMq,2407,3,81,0,0,XED_EXCEPTION_INVALID), +/*2148*/ XED_DEF_INST(XED_ICLASS_RDPKRU,XED_CATEGORY_PKU,XED_EXTENSION_PKU,3,XED_IFORM_RDPKRU,2410,3,0,0,0,XED_EXCEPTION_INVALID), +/*2149*/ XED_DEF_INST(XED_ICLASS_WRPKRU,XED_CATEGORY_PKU,XED_EXTENSION_PKU,3,XED_IFORM_WRPKRU,2413,3,0,0,0,XED_EXCEPTION_INVALID), +/*2150*/ XED_DEF_INST(XED_ICLASS_CLWB,XED_CATEGORY_CLWB,XED_EXTENSION_CLWB,3,XED_IFORM_CLWB_MEMmprefetch,838,1,0,0,50,XED_EXCEPTION_INVALID), +/*2151*/ XED_DEF_INST(XED_ICLASS_PREFETCHWT1,XED_CATEGORY_PREFETCHWT1,XED_EXTENSION_PREFETCHWT1,3,XED_IFORM_PREFETCHWT1_MEMu8,872,1,0,0,50,XED_EXCEPTION_INVALID), +/*2152*/ XED_DEF_INST(XED_ICLASS_WBINVD,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_WBINVD,0,0,0,0,35,XED_EXCEPTION_INVALID), +/*2153*/ XED_DEF_INST(XED_ICLASS_WBINVD,XED_CATEGORY_SYSTEM,XED_EXTENSION_BASE,0,XED_IFORM_WBINVD,0,0,0,0,35,XED_EXCEPTION_INVALID), +/*2154*/ XED_DEF_INST(XED_ICLASS_WBNOINVD,XED_CATEGORY_SYSTEM,XED_EXTENSION_WBNOINVD,0,XED_IFORM_WBNOINVD,0,0,0,0,35,XED_EXCEPTION_INVALID), +/*2155*/ XED_DEF_INST(XED_ICLASS_PCONFIG,XED_CATEGORY_PCONFIG,XED_EXTENSION_PCONFIG,0,XED_IFORM_PCONFIG,2416,5,82,0,0,XED_EXCEPTION_INVALID), +/*2156*/ XED_DEF_INST(XED_ICLASS_PCONFIG,XED_CATEGORY_PCONFIG,XED_EXTENSION_PCONFIG,0,XED_IFORM_PCONFIG64,2421,5,82,0,0,XED_EXCEPTION_INVALID), +/*2157*/ XED_DEF_INST(XED_ICLASS_GF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_GF2P8AFFINEINVQB_XMMu8_XMMu64_IMM8,2426,3,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2158*/ XED_DEF_INST(XED_ICLASS_GF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_GF2P8AFFINEINVQB_XMMu8_MEMu64_IMM8,2429,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2159*/ XED_DEF_INST(XED_ICLASS_GF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_GF2P8AFFINEQB_XMMu8_XMMu64_IMM8,2426,3,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2160*/ XED_DEF_INST(XED_ICLASS_GF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_GF2P8AFFINEQB_XMMu8_MEMu64_IMM8,2429,3,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2161*/ XED_DEF_INST(XED_ICLASS_GF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_GF2P8MULB_XMMu8_XMMu8,1692,2,0,0,0,XED_EXCEPTION_SSE_TYPE_4), +/*2162*/ XED_DEF_INST(XED_ICLASS_GF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_GF2P8MULB_XMMu8_MEMu8,1690,2,0,0,44,XED_EXCEPTION_SSE_TYPE_4), +/*2163*/ XED_DEF_INST(XED_ICLASS_AESDEC128KL,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,3,XED_IFORM_AESDEC128KL_XMMu8_MEMu8,2432,3,83,0,0,XED_EXCEPTION_INVALID), +/*2164*/ XED_DEF_INST(XED_ICLASS_AESDEC256KL,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,3,XED_IFORM_AESDEC256KL_XMMu8_MEMu8,2435,3,83,0,0,XED_EXCEPTION_INVALID), +/*2165*/ XED_DEF_INST(XED_ICLASS_AESDECWIDE128KL,XED_CATEGORY_KEYLOCKER_WIDE,XED_EXTENSION_KEYLOCKER_WIDE,3,XED_IFORM_AESDECWIDE128KL_MEMu8,2438,10,83,0,0,XED_EXCEPTION_INVALID), +/*2166*/ XED_DEF_INST(XED_ICLASS_AESDECWIDE256KL,XED_CATEGORY_KEYLOCKER_WIDE,XED_EXTENSION_KEYLOCKER_WIDE,3,XED_IFORM_AESDECWIDE256KL_MEMu8,2448,10,83,0,0,XED_EXCEPTION_INVALID), +/*2167*/ XED_DEF_INST(XED_ICLASS_AESENC128KL,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,3,XED_IFORM_AESENC128KL_XMMu8_MEMu8,2432,3,83,0,0,XED_EXCEPTION_INVALID), +/*2168*/ XED_DEF_INST(XED_ICLASS_AESENC256KL,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,3,XED_IFORM_AESENC256KL_XMMu8_MEMu8,2435,3,83,0,0,XED_EXCEPTION_INVALID), +/*2169*/ XED_DEF_INST(XED_ICLASS_AESENCWIDE128KL,XED_CATEGORY_KEYLOCKER_WIDE,XED_EXTENSION_KEYLOCKER_WIDE,3,XED_IFORM_AESENCWIDE128KL_MEMu8,2438,10,83,0,0,XED_EXCEPTION_INVALID), +/*2170*/ XED_DEF_INST(XED_ICLASS_AESENCWIDE256KL,XED_CATEGORY_KEYLOCKER_WIDE,XED_EXTENSION_KEYLOCKER_WIDE,3,XED_IFORM_AESENCWIDE256KL_MEMu8,2448,10,83,0,0,XED_EXCEPTION_INVALID), +/*2171*/ XED_DEF_INST(XED_ICLASS_ENCODEKEY128,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,3,XED_IFORM_ENCODEKEY128_GPR32u8_GPR32u8,2458,9,84,0,0,XED_EXCEPTION_INVALID), +/*2172*/ XED_DEF_INST(XED_ICLASS_ENCODEKEY256,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,3,XED_IFORM_ENCODEKEY256_GPR32u8_GPR32u8,2467,10,84,0,0,XED_EXCEPTION_INVALID), +/*2173*/ XED_DEF_INST(XED_ICLASS_LOADIWKEY,XED_CATEGORY_KEYLOCKER,XED_EXTENSION_KEYLOCKER,0,XED_IFORM_LOADIWKEY_XMMu8_XMMu8,2477,5,83,0,0,XED_EXCEPTION_INVALID), +/*2174*/ XED_DEF_INST(XED_ICLASS_HRESET,XED_CATEGORY_HRESET,XED_EXTENSION_HRESET,0,XED_IFORM_HRESET_IMM8,2482,2,0,0,0,XED_EXCEPTION_INVALID), +/*2175*/ XED_DEF_INST(XED_ICLASS_CLUI,XED_CATEGORY_UINTR,XED_EXTENSION_UINTR,3,XED_IFORM_CLUI,2484,1,0,0,0,XED_EXCEPTION_INVALID), +/*2176*/ XED_DEF_INST(XED_ICLASS_SENDUIPI,XED_CATEGORY_UINTR,XED_EXTENSION_UINTR,3,XED_IFORM_SENDUIPI_GPR32u32,2485,1,0,0,0,XED_EXCEPTION_INVALID), +/*2177*/ XED_DEF_INST(XED_ICLASS_STUI,XED_CATEGORY_UINTR,XED_EXTENSION_UINTR,3,XED_IFORM_STUI,2484,1,0,0,0,XED_EXCEPTION_INVALID), +/*2178*/ XED_DEF_INST(XED_ICLASS_TESTUI,XED_CATEGORY_UINTR,XED_EXTENSION_UINTR,3,XED_IFORM_TESTUI,2486,2,85,0,0,XED_EXCEPTION_INVALID), +/*2179*/ XED_DEF_INST(XED_ICLASS_UIRET,XED_CATEGORY_UINTR,XED_EXTENSION_UINTR,3,XED_IFORM_UIRET,2488,5,86,0,16,XED_EXCEPTION_INVALID), +/*2180*/ XED_DEF_INST(XED_ICLASS_ENQCMD,XED_CATEGORY_ENQCMD,XED_EXTENSION_ENQCMD,3,XED_IFORM_ENQCMD_GPRa_MEMu32,2493,3,82,0,0,XED_EXCEPTION_INVALID), +/*2181*/ XED_DEF_INST(XED_ICLASS_ENQCMDS,XED_CATEGORY_ENQCMD,XED_EXTENSION_ENQCMD,3,XED_IFORM_ENQCMDS_GPRa_MEMu32,2493,3,82,0,0,XED_EXCEPTION_INVALID), +/*2182*/ XED_DEF_INST(XED_ICLASS_XRESLDTRK,XED_CATEGORY_TSX_LDTRK,XED_EXTENSION_TSX_LDTRK,3,XED_IFORM_XRESLDTRK,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2183*/ XED_DEF_INST(XED_ICLASS_XSUSLDTRK,XED_CATEGORY_TSX_LDTRK,XED_EXTENSION_TSX_LDTRK,3,XED_IFORM_XSUSLDTRK,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2184*/ XED_DEF_INST(XED_ICLASS_SERIALIZE,XED_CATEGORY_SERIALIZE,XED_EXTENSION_SERIALIZE,3,XED_IFORM_SERIALIZE,0,0,0,0,0,XED_EXCEPTION_INVALID), +/*2185*/ XED_DEF_INST(XED_ICLASS_SEAMCALL,XED_CATEGORY_LEGACY,XED_EXTENSION_TDX,0,XED_IFORM_SEAMCALL,2496,2,87,0,1,XED_EXCEPTION_INVALID), +/*2186*/ XED_DEF_INST(XED_ICLASS_SEAMOPS,XED_CATEGORY_LEGACY,XED_EXTENSION_TDX,0,XED_IFORM_SEAMOPS,2496,2,87,0,1,XED_EXCEPTION_INVALID), +/*2187*/ XED_DEF_INST(XED_ICLASS_SEAMRET,XED_CATEGORY_LEGACY,XED_EXTENSION_TDX,0,XED_IFORM_SEAMRET,848,1,87,0,1,XED_EXCEPTION_INVALID), +/*2188*/ XED_DEF_INST(XED_ICLASS_TDCALL,XED_CATEGORY_LEGACY,XED_EXTENSION_TDX,0,XED_IFORM_TDCALL,2498,1,0,0,1,XED_EXCEPTION_INVALID), +/*2189*/ XED_DEF_INST(XED_ICLASS_TDCALL,XED_CATEGORY_LEGACY,XED_EXTENSION_TDX,0,XED_IFORM_TDCALL,2499,1,0,0,1,XED_EXCEPTION_INVALID), +/*2190*/ XED_DEF_INST(XED_ICLASS_VPMACSSWW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSWW_XMMdq_XMMdq_MEMdq_XMMdq,2500,4,0,0,105,XED_EXCEPTION_INVALID), +/*2191*/ XED_DEF_INST(XED_ICLASS_VPMACSSWW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSWW_XMMdq_XMMdq_XMMdq_XMMdq,2504,4,0,0,105,XED_EXCEPTION_INVALID), +/*2192*/ XED_DEF_INST(XED_ICLASS_VPMACSSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSWD_XMMdq_XMMdq_MEMdq_XMMdq,2508,4,0,0,105,XED_EXCEPTION_INVALID), +/*2193*/ XED_DEF_INST(XED_ICLASS_VPMACSSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSWD_XMMdq_XMMdq_XMMdq_XMMdq,2512,4,0,0,105,XED_EXCEPTION_INVALID), +/*2194*/ XED_DEF_INST(XED_ICLASS_VPMACSSDQL,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_MEMdq_XMMdq,2516,4,0,0,105,XED_EXCEPTION_INVALID), +/*2195*/ XED_DEF_INST(XED_ICLASS_VPMACSSDQL,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSDQL_XMMdq_XMMdq_XMMdq_XMMdq,2520,4,0,0,105,XED_EXCEPTION_INVALID), +/*2196*/ XED_DEF_INST(XED_ICLASS_VPMACSWW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSWW_XMMdq_XMMdq_MEMdq_XMMdq,2500,4,0,0,105,XED_EXCEPTION_INVALID), +/*2197*/ XED_DEF_INST(XED_ICLASS_VPMACSWW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSWW_XMMdq_XMMdq_XMMdq_XMMdq,2504,4,0,0,105,XED_EXCEPTION_INVALID), +/*2198*/ XED_DEF_INST(XED_ICLASS_VPMACSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSWD_XMMdq_XMMdq_MEMdq_XMMdq,2508,4,0,0,105,XED_EXCEPTION_INVALID), +/*2199*/ XED_DEF_INST(XED_ICLASS_VPMACSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSWD_XMMdq_XMMdq_XMMdq_XMMdq,2512,4,0,0,105,XED_EXCEPTION_INVALID), +/*2200*/ XED_DEF_INST(XED_ICLASS_VPMACSDQL,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSDQL_XMMdq_XMMdq_MEMdq_XMMdq,2516,4,0,0,105,XED_EXCEPTION_INVALID), +/*2201*/ XED_DEF_INST(XED_ICLASS_VPMACSDQL,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSDQL_XMMdq_XMMdq_XMMdq_XMMdq,2520,4,0,0,105,XED_EXCEPTION_INVALID), +/*2202*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_XMMdq_XMMdq_MEMdq_XMMdq,2524,4,0,0,105,XED_EXCEPTION_INVALID), +/*2203*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq,2528,4,0,0,105,XED_EXCEPTION_INVALID), +/*2204*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_MEMdq,2532,4,0,0,105,XED_EXCEPTION_INVALID), +/*2205*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_XMMdq_XMMdq_XMMdq_XMMdq,2536,4,0,0,105,XED_EXCEPTION_INVALID), +/*2206*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_YMMqq_YMMqq_MEMqq_YMMqq,2540,4,0,0,105,XED_EXCEPTION_INVALID), +/*2207*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq,2544,4,0,0,105,XED_EXCEPTION_INVALID), +/*2208*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_MEMqq,2548,4,0,0,105,XED_EXCEPTION_INVALID), +/*2209*/ XED_DEF_INST(XED_ICLASS_VPCMOV,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCMOV_YMMqq_YMMqq_YMMqq_YMMqq,2552,4,0,0,105,XED_EXCEPTION_INVALID), +/*2210*/ XED_DEF_INST(XED_ICLASS_VPPERM,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPPERM_XMMdq_XMMdq_MEMdq_XMMdq,2500,4,0,0,105,XED_EXCEPTION_INVALID), +/*2211*/ XED_DEF_INST(XED_ICLASS_VPPERM,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq,2504,4,0,0,105,XED_EXCEPTION_INVALID), +/*2212*/ XED_DEF_INST(XED_ICLASS_VPPERM,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_MEMdq,2556,4,0,0,105,XED_EXCEPTION_INVALID), +/*2213*/ XED_DEF_INST(XED_ICLASS_VPPERM,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPPERM_XMMdq_XMMdq_XMMdq_XMMdq,2560,4,0,0,105,XED_EXCEPTION_INVALID), +/*2214*/ XED_DEF_INST(XED_ICLASS_VPMADCSSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_MEMdq_XMMdq,2508,4,0,0,105,XED_EXCEPTION_INVALID), +/*2215*/ XED_DEF_INST(XED_ICLASS_VPMADCSSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMADCSSWD_XMMdq_XMMdq_XMMdq_XMMdq,2512,4,0,0,105,XED_EXCEPTION_INVALID), +/*2216*/ XED_DEF_INST(XED_ICLASS_VPMADCSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMADCSWD_XMMdq_XMMdq_MEMdq_XMMdq,2508,4,0,0,105,XED_EXCEPTION_INVALID), +/*2217*/ XED_DEF_INST(XED_ICLASS_VPMADCSWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMADCSWD_XMMdq_XMMdq_XMMdq_XMMdq,2512,4,0,0,105,XED_EXCEPTION_INVALID), +/*2218*/ XED_DEF_INST(XED_ICLASS_VPROTB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTB_XMMdq_MEMdq_IMMb,2564,3,0,0,105,XED_EXCEPTION_INVALID), +/*2219*/ XED_DEF_INST(XED_ICLASS_VPROTB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTB_XMMdq_XMMdq_IMMb,2567,3,0,0,105,XED_EXCEPTION_INVALID), +/*2220*/ XED_DEF_INST(XED_ICLASS_VPROTB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTB_XMMdq_MEMdq_XMMdq,2570,3,0,0,105,XED_EXCEPTION_INVALID), +/*2221*/ XED_DEF_INST(XED_ICLASS_VPROTB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq,2573,3,0,0,105,XED_EXCEPTION_INVALID), +/*2222*/ XED_DEF_INST(XED_ICLASS_VPROTB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTB_XMMdq_XMMdq_MEMdq,2576,3,0,0,105,XED_EXCEPTION_INVALID), +/*2223*/ XED_DEF_INST(XED_ICLASS_VPROTB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTB_XMMdq_XMMdq_XMMdq,2579,3,0,0,105,XED_EXCEPTION_INVALID), +/*2224*/ XED_DEF_INST(XED_ICLASS_VPROTW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTW_XMMdq_MEMdq_IMMb,1563,3,0,0,105,XED_EXCEPTION_INVALID), +/*2225*/ XED_DEF_INST(XED_ICLASS_VPROTW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTW_XMMdq_XMMdq_IMMb,1566,3,0,0,105,XED_EXCEPTION_INVALID), +/*2226*/ XED_DEF_INST(XED_ICLASS_VPROTW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTW_XMMdq_MEMdq_XMMdq,2582,3,0,0,105,XED_EXCEPTION_INVALID), +/*2227*/ XED_DEF_INST(XED_ICLASS_VPROTW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq,2585,3,0,0,105,XED_EXCEPTION_INVALID), +/*2228*/ XED_DEF_INST(XED_ICLASS_VPROTW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTW_XMMdq_XMMdq_MEMdq,2588,3,0,0,105,XED_EXCEPTION_INVALID), +/*2229*/ XED_DEF_INST(XED_ICLASS_VPROTW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTW_XMMdq_XMMdq_XMMdq,2591,3,0,0,105,XED_EXCEPTION_INVALID), +/*2230*/ XED_DEF_INST(XED_ICLASS_VPROTD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTD_XMMdq_MEMdq_IMMb,1557,3,0,0,105,XED_EXCEPTION_INVALID), +/*2231*/ XED_DEF_INST(XED_ICLASS_VPROTD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTD_XMMdq_XMMdq_IMMb,1560,3,0,0,105,XED_EXCEPTION_INVALID), +/*2232*/ XED_DEF_INST(XED_ICLASS_VPROTD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTD_XMMdq_MEMdq_XMMdq,2594,3,0,0,105,XED_EXCEPTION_INVALID), +/*2233*/ XED_DEF_INST(XED_ICLASS_VPROTD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq,2597,3,0,0,105,XED_EXCEPTION_INVALID), +/*2234*/ XED_DEF_INST(XED_ICLASS_VPROTD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTD_XMMdq_XMMdq_MEMdq,2600,3,0,0,105,XED_EXCEPTION_INVALID), +/*2235*/ XED_DEF_INST(XED_ICLASS_VPROTD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTD_XMMdq_XMMdq_XMMdq,2603,3,0,0,105,XED_EXCEPTION_INVALID), +/*2236*/ XED_DEF_INST(XED_ICLASS_VPROTQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTQ_XMMdq_MEMdq_IMMb,2606,3,0,0,105,XED_EXCEPTION_INVALID), +/*2237*/ XED_DEF_INST(XED_ICLASS_VPROTQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTQ_XMMdq_XMMdq_IMMb,2609,3,0,0,105,XED_EXCEPTION_INVALID), +/*2238*/ XED_DEF_INST(XED_ICLASS_VPROTQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTQ_XMMdq_MEMdq_XMMdq,2612,3,0,0,105,XED_EXCEPTION_INVALID), +/*2239*/ XED_DEF_INST(XED_ICLASS_VPROTQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq,2615,3,0,0,105,XED_EXCEPTION_INVALID), +/*2240*/ XED_DEF_INST(XED_ICLASS_VPROTQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,105,XED_EXCEPTION_INVALID), +/*2241*/ XED_DEF_INST(XED_ICLASS_VPROTQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPROTQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,105,XED_EXCEPTION_INVALID), +/*2242*/ XED_DEF_INST(XED_ICLASS_VPMACSSDD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSDD_XMMdq_XMMdq_MEMdq_XMMdq,2624,4,0,0,105,XED_EXCEPTION_INVALID), +/*2243*/ XED_DEF_INST(XED_ICLASS_VPMACSSDD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSDD_XMMdq_XMMdq_XMMdq_XMMdq,2628,4,0,0,105,XED_EXCEPTION_INVALID), +/*2244*/ XED_DEF_INST(XED_ICLASS_VPMACSSDQH,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_MEMdq_XMMdq,2516,4,0,0,105,XED_EXCEPTION_INVALID), +/*2245*/ XED_DEF_INST(XED_ICLASS_VPMACSSDQH,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSSDQH_XMMdq_XMMdq_XMMdq_XMMdq,2520,4,0,0,105,XED_EXCEPTION_INVALID), +/*2246*/ XED_DEF_INST(XED_ICLASS_VPMACSDD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSDD_XMMdq_XMMdq_MEMdq_XMMdq,2624,4,0,0,105,XED_EXCEPTION_INVALID), +/*2247*/ XED_DEF_INST(XED_ICLASS_VPMACSDD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSDD_XMMdq_XMMdq_XMMdq_XMMdq,2628,4,0,0,105,XED_EXCEPTION_INVALID), +/*2248*/ XED_DEF_INST(XED_ICLASS_VPMACSDQH,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSDQH_XMMdq_XMMdq_MEMdq_XMMdq,2516,4,0,0,105,XED_EXCEPTION_INVALID), +/*2249*/ XED_DEF_INST(XED_ICLASS_VPMACSDQH,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPMACSDQH_XMMdq_XMMdq_XMMdq_XMMdq,2520,4,0,0,105,XED_EXCEPTION_INVALID), +/*2250*/ XED_DEF_INST(XED_ICLASS_VPCOMB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMB_XMMdq_XMMdq_MEMdq_IMMb,2632,4,0,0,105,XED_EXCEPTION_INVALID), +/*2251*/ XED_DEF_INST(XED_ICLASS_VPCOMB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMB_XMMdq_XMMdq_XMMdq_IMMb,2636,4,0,0,105,XED_EXCEPTION_INVALID), +/*2252*/ XED_DEF_INST(XED_ICLASS_VPCOMW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMW_XMMdq_XMMdq_MEMdq_IMMb,2640,4,0,0,105,XED_EXCEPTION_INVALID), +/*2253*/ XED_DEF_INST(XED_ICLASS_VPCOMW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMW_XMMdq_XMMdq_XMMdq_IMMb,2644,4,0,0,105,XED_EXCEPTION_INVALID), +/*2254*/ XED_DEF_INST(XED_ICLASS_VPCOMD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMD_XMMdq_XMMdq_MEMdq_IMMb,2648,4,0,0,105,XED_EXCEPTION_INVALID), +/*2255*/ XED_DEF_INST(XED_ICLASS_VPCOMD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMD_XMMdq_XMMdq_XMMdq_IMMb,2652,4,0,0,105,XED_EXCEPTION_INVALID), +/*2256*/ XED_DEF_INST(XED_ICLASS_VPCOMQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMQ_XMMdq_XMMdq_MEMdq_IMMb,2656,4,0,0,105,XED_EXCEPTION_INVALID), +/*2257*/ XED_DEF_INST(XED_ICLASS_VPCOMQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMQ_XMMdq_XMMdq_XMMdq_IMMb,2660,4,0,0,105,XED_EXCEPTION_INVALID), +/*2258*/ XED_DEF_INST(XED_ICLASS_VPCOMUB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUB_XMMdq_XMMdq_MEMdq_IMMb,2664,4,0,0,105,XED_EXCEPTION_INVALID), +/*2259*/ XED_DEF_INST(XED_ICLASS_VPCOMUB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUB_XMMdq_XMMdq_XMMdq_IMMb,2668,4,0,0,105,XED_EXCEPTION_INVALID), +/*2260*/ XED_DEF_INST(XED_ICLASS_VPCOMUW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUW_XMMdq_XMMdq_MEMdq_IMMb,2672,4,0,0,105,XED_EXCEPTION_INVALID), +/*2261*/ XED_DEF_INST(XED_ICLASS_VPCOMUW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUW_XMMdq_XMMdq_XMMdq_IMMb,2676,4,0,0,105,XED_EXCEPTION_INVALID), +/*2262*/ XED_DEF_INST(XED_ICLASS_VPCOMUD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUD_XMMdq_XMMdq_MEMdq_IMMb,2680,4,0,0,105,XED_EXCEPTION_INVALID), +/*2263*/ XED_DEF_INST(XED_ICLASS_VPCOMUD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUD_XMMdq_XMMdq_XMMdq_IMMb,2684,4,0,0,105,XED_EXCEPTION_INVALID), +/*2264*/ XED_DEF_INST(XED_ICLASS_VPCOMUQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUQ_XMMdq_XMMdq_MEMdq_IMMb,2688,4,0,0,105,XED_EXCEPTION_INVALID), +/*2265*/ XED_DEF_INST(XED_ICLASS_VPCOMUQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPCOMUQ_XMMdq_XMMdq_XMMdq_IMMb,2692,4,0,0,105,XED_EXCEPTION_INVALID), +/*2266*/ XED_DEF_INST(XED_ICLASS_VFRCZPS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPS_XMMdq_MEMdq,2696,2,0,0,115,XED_EXCEPTION_INVALID), +/*2267*/ XED_DEF_INST(XED_ICLASS_VFRCZPS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPS_XMMdq_XMMdq,2698,2,0,0,115,XED_EXCEPTION_INVALID), +/*2268*/ XED_DEF_INST(XED_ICLASS_VFRCZPS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPS_YMMqq_MEMqq,2700,2,0,0,115,XED_EXCEPTION_INVALID), +/*2269*/ XED_DEF_INST(XED_ICLASS_VFRCZPS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPS_YMMqq_YMMqq,2702,2,0,0,115,XED_EXCEPTION_INVALID), +/*2270*/ XED_DEF_INST(XED_ICLASS_VFRCZPD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPD_XMMdq_MEMdq,2704,2,0,0,115,XED_EXCEPTION_INVALID), +/*2271*/ XED_DEF_INST(XED_ICLASS_VFRCZPD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPD_XMMdq_XMMdq,2706,2,0,0,115,XED_EXCEPTION_INVALID), +/*2272*/ XED_DEF_INST(XED_ICLASS_VFRCZPD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPD_YMMqq_MEMqq,2708,2,0,0,115,XED_EXCEPTION_INVALID), +/*2273*/ XED_DEF_INST(XED_ICLASS_VFRCZPD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZPD_YMMqq_YMMqq,2710,2,0,0,115,XED_EXCEPTION_INVALID), +/*2274*/ XED_DEF_INST(XED_ICLASS_VFRCZSS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZSS_XMMdq_MEMd,2712,2,0,0,116,XED_EXCEPTION_INVALID), +/*2275*/ XED_DEF_INST(XED_ICLASS_VFRCZSS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZSS_XMMdq_XMMd,2714,2,0,0,116,XED_EXCEPTION_INVALID), +/*2276*/ XED_DEF_INST(XED_ICLASS_VFRCZSD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZSD_XMMdq_MEMq,2716,2,0,0,116,XED_EXCEPTION_INVALID), +/*2277*/ XED_DEF_INST(XED_ICLASS_VFRCZSD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VFRCZSD_XMMdq_XMMq,2718,2,0,0,116,XED_EXCEPTION_INVALID), +/*2278*/ XED_DEF_INST(XED_ICLASS_VPSHLB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLB_XMMdq_MEMdq_XMMdq,2570,3,0,0,105,XED_EXCEPTION_INVALID), +/*2279*/ XED_DEF_INST(XED_ICLASS_VPSHLB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq,2573,3,0,0,105,XED_EXCEPTION_INVALID), +/*2280*/ XED_DEF_INST(XED_ICLASS_VPSHLB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLB_XMMdq_XMMdq_MEMdq,2576,3,0,0,105,XED_EXCEPTION_INVALID), +/*2281*/ XED_DEF_INST(XED_ICLASS_VPSHLB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLB_XMMdq_XMMdq_XMMdq,2579,3,0,0,105,XED_EXCEPTION_INVALID), +/*2282*/ XED_DEF_INST(XED_ICLASS_VPSHLW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLW_XMMdq_MEMdq_XMMdq,2582,3,0,0,105,XED_EXCEPTION_INVALID), +/*2283*/ XED_DEF_INST(XED_ICLASS_VPSHLW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq,2585,3,0,0,105,XED_EXCEPTION_INVALID), +/*2284*/ XED_DEF_INST(XED_ICLASS_VPSHLW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLW_XMMdq_XMMdq_MEMdq,2588,3,0,0,105,XED_EXCEPTION_INVALID), +/*2285*/ XED_DEF_INST(XED_ICLASS_VPSHLW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLW_XMMdq_XMMdq_XMMdq,2591,3,0,0,105,XED_EXCEPTION_INVALID), +/*2286*/ XED_DEF_INST(XED_ICLASS_VPSHLD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLD_XMMdq_MEMdq_XMMdq,2594,3,0,0,105,XED_EXCEPTION_INVALID), +/*2287*/ XED_DEF_INST(XED_ICLASS_VPSHLD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq,2597,3,0,0,105,XED_EXCEPTION_INVALID), +/*2288*/ XED_DEF_INST(XED_ICLASS_VPSHLD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLD_XMMdq_XMMdq_MEMdq,2600,3,0,0,105,XED_EXCEPTION_INVALID), +/*2289*/ XED_DEF_INST(XED_ICLASS_VPSHLD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLD_XMMdq_XMMdq_XMMdq,2603,3,0,0,105,XED_EXCEPTION_INVALID), +/*2290*/ XED_DEF_INST(XED_ICLASS_VPSHLQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLQ_XMMdq_MEMdq_XMMdq,2612,3,0,0,105,XED_EXCEPTION_INVALID), +/*2291*/ XED_DEF_INST(XED_ICLASS_VPSHLQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq,2615,3,0,0,105,XED_EXCEPTION_INVALID), +/*2292*/ XED_DEF_INST(XED_ICLASS_VPSHLQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,105,XED_EXCEPTION_INVALID), +/*2293*/ XED_DEF_INST(XED_ICLASS_VPSHLQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHLQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,105,XED_EXCEPTION_INVALID), +/*2294*/ XED_DEF_INST(XED_ICLASS_VPHADDBW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDBW_XMMdq_MEMdq,2720,2,0,0,105,XED_EXCEPTION_INVALID), +/*2295*/ XED_DEF_INST(XED_ICLASS_VPHADDBW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDBW_XMMdq_XMMdq,2722,2,0,0,105,XED_EXCEPTION_INVALID), +/*2296*/ XED_DEF_INST(XED_ICLASS_VPHADDBD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDBD_XMMdq_MEMdq,2724,2,0,0,105,XED_EXCEPTION_INVALID), +/*2297*/ XED_DEF_INST(XED_ICLASS_VPHADDBD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDBD_XMMdq_XMMdq,2726,2,0,0,105,XED_EXCEPTION_INVALID), +/*2298*/ XED_DEF_INST(XED_ICLASS_VPHADDBQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDBQ_XMMdq_MEMdq,2728,2,0,0,105,XED_EXCEPTION_INVALID), +/*2299*/ XED_DEF_INST(XED_ICLASS_VPHADDBQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDBQ_XMMdq_XMMdq,2730,2,0,0,105,XED_EXCEPTION_INVALID), +/*2300*/ XED_DEF_INST(XED_ICLASS_VPHADDWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDWD_XMMdq_MEMdq,2732,2,0,0,105,XED_EXCEPTION_INVALID), +/*2301*/ XED_DEF_INST(XED_ICLASS_VPHADDWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDWD_XMMdq_XMMdq,2734,2,0,0,105,XED_EXCEPTION_INVALID), +/*2302*/ XED_DEF_INST(XED_ICLASS_VPHADDWQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDWQ_XMMdq_MEMdq,2736,2,0,0,105,XED_EXCEPTION_INVALID), +/*2303*/ XED_DEF_INST(XED_ICLASS_VPHADDWQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDWQ_XMMdq_XMMdq,2738,2,0,0,105,XED_EXCEPTION_INVALID), +/*2304*/ XED_DEF_INST(XED_ICLASS_VPHADDUBW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUBW_XMMdq_MEMdq,2740,2,0,0,105,XED_EXCEPTION_INVALID), +/*2305*/ XED_DEF_INST(XED_ICLASS_VPHADDUBW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUBW_XMMdq_XMMdq,2742,2,0,0,105,XED_EXCEPTION_INVALID), +/*2306*/ XED_DEF_INST(XED_ICLASS_VPHADDUBD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUBD_XMMdq_MEMdq,2744,2,0,0,105,XED_EXCEPTION_INVALID), +/*2307*/ XED_DEF_INST(XED_ICLASS_VPHADDUBD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUBD_XMMdq_XMMdq,2746,2,0,0,105,XED_EXCEPTION_INVALID), +/*2308*/ XED_DEF_INST(XED_ICLASS_VPHADDUBQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUBQ_XMMdq_MEMdq,2748,2,0,0,105,XED_EXCEPTION_INVALID), +/*2309*/ XED_DEF_INST(XED_ICLASS_VPHADDUBQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUBQ_XMMdq_XMMdq,2750,2,0,0,105,XED_EXCEPTION_INVALID), +/*2310*/ XED_DEF_INST(XED_ICLASS_VPHADDUWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUWD_XMMdq_MEMdq,2752,2,0,0,105,XED_EXCEPTION_INVALID), +/*2311*/ XED_DEF_INST(XED_ICLASS_VPHADDUWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUWD_XMMdq_XMMdq,2754,2,0,0,105,XED_EXCEPTION_INVALID), +/*2312*/ XED_DEF_INST(XED_ICLASS_VPHADDUWQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUWQ_XMMdq_MEMdq,2756,2,0,0,105,XED_EXCEPTION_INVALID), +/*2313*/ XED_DEF_INST(XED_ICLASS_VPHADDUWQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUWQ_XMMdq_XMMdq,2758,2,0,0,105,XED_EXCEPTION_INVALID), +/*2314*/ XED_DEF_INST(XED_ICLASS_VPHSUBBW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHSUBBW_XMMdq_MEMdq,2760,2,0,0,105,XED_EXCEPTION_INVALID), +/*2315*/ XED_DEF_INST(XED_ICLASS_VPHSUBBW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHSUBBW_XMMdq_XMMdq,2762,2,0,0,105,XED_EXCEPTION_INVALID), +/*2316*/ XED_DEF_INST(XED_ICLASS_VPHSUBWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHSUBWD_XMMdq_MEMdq,2732,2,0,0,105,XED_EXCEPTION_INVALID), +/*2317*/ XED_DEF_INST(XED_ICLASS_VPHSUBWD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHSUBWD_XMMdq_XMMdq,2734,2,0,0,105,XED_EXCEPTION_INVALID), +/*2318*/ XED_DEF_INST(XED_ICLASS_VPHSUBDQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHSUBDQ_XMMdq_MEMdq,2764,2,0,0,105,XED_EXCEPTION_INVALID), +/*2319*/ XED_DEF_INST(XED_ICLASS_VPHSUBDQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHSUBDQ_XMMdq_XMMdq,2766,2,0,0,105,XED_EXCEPTION_INVALID), +/*2320*/ XED_DEF_INST(XED_ICLASS_VPSHAB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAB_XMMdq_MEMdq_XMMdq,2768,3,0,0,105,XED_EXCEPTION_INVALID), +/*2321*/ XED_DEF_INST(XED_ICLASS_VPSHAB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq,2771,3,0,0,105,XED_EXCEPTION_INVALID), +/*2322*/ XED_DEF_INST(XED_ICLASS_VPSHAB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAB_XMMdq_XMMdq_MEMdq,2774,3,0,0,105,XED_EXCEPTION_INVALID), +/*2323*/ XED_DEF_INST(XED_ICLASS_VPSHAB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAB_XMMdq_XMMdq_XMMdq,2777,3,0,0,105,XED_EXCEPTION_INVALID), +/*2324*/ XED_DEF_INST(XED_ICLASS_VPSHAW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAW_XMMdq_MEMdq_XMMdq,2780,3,0,0,105,XED_EXCEPTION_INVALID), +/*2325*/ XED_DEF_INST(XED_ICLASS_VPSHAW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq,2783,3,0,0,105,XED_EXCEPTION_INVALID), +/*2326*/ XED_DEF_INST(XED_ICLASS_VPSHAW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAW_XMMdq_XMMdq_MEMdq,2786,3,0,0,105,XED_EXCEPTION_INVALID), +/*2327*/ XED_DEF_INST(XED_ICLASS_VPSHAW,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAW_XMMdq_XMMdq_XMMdq,2789,3,0,0,105,XED_EXCEPTION_INVALID), +/*2328*/ XED_DEF_INST(XED_ICLASS_VPSHAD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAD_XMMdq_MEMdq_XMMdq,2792,3,0,0,105,XED_EXCEPTION_INVALID), +/*2329*/ XED_DEF_INST(XED_ICLASS_VPSHAD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq,2795,3,0,0,105,XED_EXCEPTION_INVALID), +/*2330*/ XED_DEF_INST(XED_ICLASS_VPSHAD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAD_XMMdq_XMMdq_MEMdq,2798,3,0,0,105,XED_EXCEPTION_INVALID), +/*2331*/ XED_DEF_INST(XED_ICLASS_VPSHAD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAD_XMMdq_XMMdq_XMMdq,2801,3,0,0,105,XED_EXCEPTION_INVALID), +/*2332*/ XED_DEF_INST(XED_ICLASS_VPSHAQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAQ_XMMdq_MEMdq_XMMdq,2804,3,0,0,105,XED_EXCEPTION_INVALID), +/*2333*/ XED_DEF_INST(XED_ICLASS_VPSHAQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq,2807,3,0,0,105,XED_EXCEPTION_INVALID), +/*2334*/ XED_DEF_INST(XED_ICLASS_VPSHAQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAQ_XMMdq_XMMdq_MEMdq,2810,3,0,0,105,XED_EXCEPTION_INVALID), +/*2335*/ XED_DEF_INST(XED_ICLASS_VPSHAQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPSHAQ_XMMdq_XMMdq_XMMdq,2813,3,0,0,105,XED_EXCEPTION_INVALID), +/*2336*/ XED_DEF_INST(XED_ICLASS_VPHADDDQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDDQ_XMMdq_MEMdq,2764,2,0,0,105,XED_EXCEPTION_INVALID), +/*2337*/ XED_DEF_INST(XED_ICLASS_VPHADDDQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDDQ_XMMdq_XMMdq,2766,2,0,0,105,XED_EXCEPTION_INVALID), +/*2338*/ XED_DEF_INST(XED_ICLASS_VPHADDUDQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUDQ_XMMdq_MEMdq,2816,2,0,0,105,XED_EXCEPTION_INVALID), +/*2339*/ XED_DEF_INST(XED_ICLASS_VPHADDUDQ,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPHADDUDQ_XMMdq_XMMdq,2818,2,0,0,105,XED_EXCEPTION_INVALID), +/*2340*/ XED_DEF_INST(XED_ICLASS_BEXTR_XOP,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BEXTR_XOP_VGPR32d_MEMd_IMMd,2820,4,88,0,105,XED_EXCEPTION_INVALID), +/*2341*/ XED_DEF_INST(XED_ICLASS_BEXTR_XOP,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BEXTR_XOP_VGPRyy_MEMy_IMMd,2824,4,88,0,117,XED_EXCEPTION_INVALID), +/*2342*/ XED_DEF_INST(XED_ICLASS_BEXTR_XOP,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BEXTR_XOP_VGPR32d_VGPR32d_IMMd,2828,4,88,0,105,XED_EXCEPTION_INVALID), +/*2343*/ XED_DEF_INST(XED_ICLASS_BEXTR_XOP,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BEXTR_XOP_VGPRyy_VGPRyy_IMMd,2832,4,88,0,117,XED_EXCEPTION_INVALID), +/*2344*/ XED_DEF_INST(XED_ICLASS_BLCFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCFILL_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2345*/ XED_DEF_INST(XED_ICLASS_BLCFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCFILL_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2346*/ XED_DEF_INST(XED_ICLASS_BLCFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCFILL_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2347*/ XED_DEF_INST(XED_ICLASS_BLCFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCFILL_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2348*/ XED_DEF_INST(XED_ICLASS_BLSFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSFILL_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2349*/ XED_DEF_INST(XED_ICLASS_BLSFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSFILL_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2350*/ XED_DEF_INST(XED_ICLASS_BLSFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSFILL_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2351*/ XED_DEF_INST(XED_ICLASS_BLSFILL,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSFILL_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2352*/ XED_DEF_INST(XED_ICLASS_BLCS,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCS_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2353*/ XED_DEF_INST(XED_ICLASS_BLCS,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCS_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2354*/ XED_DEF_INST(XED_ICLASS_BLCS,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCS_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2355*/ XED_DEF_INST(XED_ICLASS_BLCS,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCS_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2356*/ XED_DEF_INST(XED_ICLASS_TZMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_TZMSK_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2357*/ XED_DEF_INST(XED_ICLASS_TZMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_TZMSK_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2358*/ XED_DEF_INST(XED_ICLASS_TZMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_TZMSK_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2359*/ XED_DEF_INST(XED_ICLASS_TZMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_TZMSK_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2360*/ XED_DEF_INST(XED_ICLASS_BLCIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCIC_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2361*/ XED_DEF_INST(XED_ICLASS_BLCIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCIC_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2362*/ XED_DEF_INST(XED_ICLASS_BLCIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCIC_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2363*/ XED_DEF_INST(XED_ICLASS_BLCIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCIC_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2364*/ XED_DEF_INST(XED_ICLASS_BLSIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSIC_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2365*/ XED_DEF_INST(XED_ICLASS_BLSIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSIC_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2366*/ XED_DEF_INST(XED_ICLASS_BLSIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSIC_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2367*/ XED_DEF_INST(XED_ICLASS_BLSIC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLSIC_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2368*/ XED_DEF_INST(XED_ICLASS_T1MSKC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_T1MSKC_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2369*/ XED_DEF_INST(XED_ICLASS_T1MSKC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_T1MSKC_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2370*/ XED_DEF_INST(XED_ICLASS_T1MSKC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_T1MSKC_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2371*/ XED_DEF_INST(XED_ICLASS_T1MSKC,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_T1MSKC_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2372*/ XED_DEF_INST(XED_ICLASS_BLCMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCMSK_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2373*/ XED_DEF_INST(XED_ICLASS_BLCMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCMSK_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2374*/ XED_DEF_INST(XED_ICLASS_BLCMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCMSK_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2375*/ XED_DEF_INST(XED_ICLASS_BLCMSK,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCMSK_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2376*/ XED_DEF_INST(XED_ICLASS_BLCI,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCI_VGPR32d_MEMd,2836,3,89,0,105,XED_EXCEPTION_INVALID), +/*2377*/ XED_DEF_INST(XED_ICLASS_BLCI,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCI_VGPRyy_MEMy,2839,3,89,0,117,XED_EXCEPTION_INVALID), +/*2378*/ XED_DEF_INST(XED_ICLASS_BLCI,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCI_VGPR32d_VGPR32d,2842,3,89,0,105,XED_EXCEPTION_INVALID), +/*2379*/ XED_DEF_INST(XED_ICLASS_BLCI,XED_CATEGORY_TBM,XED_EXTENSION_TBM,3,XED_IFORM_BLCI_VGPRyy_VGPRyy,2845,3,89,0,117,XED_EXCEPTION_INVALID), +/*2380*/ XED_DEF_INST(XED_ICLASS_LLWPCB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_LLWPCB_VGPRyy,2848,1,0,0,117,XED_EXCEPTION_INVALID), +/*2381*/ XED_DEF_INST(XED_ICLASS_SLWPCB,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_SLWPCB_VGPRyy,2848,1,0,0,117,XED_EXCEPTION_INVALID), +/*2382*/ XED_DEF_INST(XED_ICLASS_LWPINS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_LWPINS_VGPRyy_MEMd_IMMd,2849,4,90,0,117,XED_EXCEPTION_INVALID), +/*2383*/ XED_DEF_INST(XED_ICLASS_LWPINS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_LWPINS_VGPRyy_VGPR32y_IMMd,2853,4,90,0,117,XED_EXCEPTION_INVALID), +/*2384*/ XED_DEF_INST(XED_ICLASS_LWPVAL,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_LWPVAL_VGPRyy_MEMd_IMMd,2857,3,0,0,117,XED_EXCEPTION_INVALID), +/*2385*/ XED_DEF_INST(XED_ICLASS_LWPVAL,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_LWPVAL_VGPRyy_VGPR32y_IMMd,2860,3,0,0,117,XED_EXCEPTION_INVALID), +/*2386*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_MEMdq_XMMdq,2863,4,0,0,115,XED_EXCEPTION_INVALID), +/*2387*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq,2867,4,0,0,115,XED_EXCEPTION_INVALID), +/*2388*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_MEMdq,2871,4,0,0,115,XED_EXCEPTION_INVALID), +/*2389*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_XMMdq_XMMdq_XMMdq_XMMdq,2875,4,0,0,115,XED_EXCEPTION_INVALID), +/*2390*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_MEMqq_YMMqq,2879,4,0,0,115,XED_EXCEPTION_INVALID), +/*2391*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq,2883,4,0,0,115,XED_EXCEPTION_INVALID), +/*2392*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_MEMqq,2887,4,0,0,115,XED_EXCEPTION_INVALID), +/*2393*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPS_YMMqq_YMMqq_YMMqq_YMMqq,2891,4,0,0,115,XED_EXCEPTION_INVALID), +/*2394*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_MEMdq_XMMdq,2895,4,0,0,115,XED_EXCEPTION_INVALID), +/*2395*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq,2899,4,0,0,115,XED_EXCEPTION_INVALID), +/*2396*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_MEMdq,2903,4,0,0,115,XED_EXCEPTION_INVALID), +/*2397*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_XMMdq_XMMdq_XMMdq_XMMdq,2907,4,0,0,115,XED_EXCEPTION_INVALID), +/*2398*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_MEMqq_YMMqq,2911,4,0,0,115,XED_EXCEPTION_INVALID), +/*2399*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq,2915,4,0,0,115,XED_EXCEPTION_INVALID), +/*2400*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_MEMqq,2919,4,0,0,115,XED_EXCEPTION_INVALID), +/*2401*/ XED_DEF_INST(XED_ICLASS_VFMADDSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSUBPD_YMMqq_YMMqq_YMMqq_YMMqq,2923,4,0,0,115,XED_EXCEPTION_INVALID), +/*2402*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_MEMdq_XMMdq,2863,4,0,0,115,XED_EXCEPTION_INVALID), +/*2403*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq,2867,4,0,0,115,XED_EXCEPTION_INVALID), +/*2404*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_MEMdq,2871,4,0,0,115,XED_EXCEPTION_INVALID), +/*2405*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_XMMdq_XMMdq_XMMdq_XMMdq,2875,4,0,0,115,XED_EXCEPTION_INVALID), +/*2406*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_MEMqq_YMMqq,2879,4,0,0,115,XED_EXCEPTION_INVALID), +/*2407*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq,2883,4,0,0,115,XED_EXCEPTION_INVALID), +/*2408*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_MEMqq,2887,4,0,0,115,XED_EXCEPTION_INVALID), +/*2409*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPS_YMMqq_YMMqq_YMMqq_YMMqq,2891,4,0,0,115,XED_EXCEPTION_INVALID), +/*2410*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_MEMdq_XMMdq,2895,4,0,0,115,XED_EXCEPTION_INVALID), +/*2411*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq,2899,4,0,0,115,XED_EXCEPTION_INVALID), +/*2412*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_MEMdq,2903,4,0,0,115,XED_EXCEPTION_INVALID), +/*2413*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_XMMdq_XMMdq_XMMdq_XMMdq,2907,4,0,0,115,XED_EXCEPTION_INVALID), +/*2414*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_MEMqq_YMMqq,2911,4,0,0,115,XED_EXCEPTION_INVALID), +/*2415*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq,2915,4,0,0,115,XED_EXCEPTION_INVALID), +/*2416*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_MEMqq,2919,4,0,0,115,XED_EXCEPTION_INVALID), +/*2417*/ XED_DEF_INST(XED_ICLASS_VFMSUBADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBADDPD_YMMqq_YMMqq_YMMqq_YMMqq,2923,4,0,0,115,XED_EXCEPTION_INVALID), +/*2418*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_XMMdq_XMMdq_MEMdq_XMMdq,2863,4,0,0,115,XED_EXCEPTION_INVALID), +/*2419*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq,2867,4,0,0,115,XED_EXCEPTION_INVALID), +/*2420*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_MEMdq,2871,4,0,0,115,XED_EXCEPTION_INVALID), +/*2421*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_XMMdq_XMMdq_XMMdq_XMMdq,2875,4,0,0,115,XED_EXCEPTION_INVALID), +/*2422*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_YMMqq_YMMqq_MEMqq_YMMqq,2879,4,0,0,115,XED_EXCEPTION_INVALID), +/*2423*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq,2883,4,0,0,115,XED_EXCEPTION_INVALID), +/*2424*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_MEMqq,2887,4,0,0,115,XED_EXCEPTION_INVALID), +/*2425*/ XED_DEF_INST(XED_ICLASS_VFMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPS_YMMqq_YMMqq_YMMqq_YMMqq,2891,4,0,0,115,XED_EXCEPTION_INVALID), +/*2426*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_XMMdq_XMMdq_MEMdq_XMMdq,2895,4,0,0,115,XED_EXCEPTION_INVALID), +/*2427*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq,2899,4,0,0,115,XED_EXCEPTION_INVALID), +/*2428*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_MEMdq,2903,4,0,0,115,XED_EXCEPTION_INVALID), +/*2429*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_XMMdq_XMMdq_XMMdq_XMMdq,2907,4,0,0,115,XED_EXCEPTION_INVALID), +/*2430*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_YMMqq_YMMqq_MEMqq_YMMqq,2911,4,0,0,115,XED_EXCEPTION_INVALID), +/*2431*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq,2915,4,0,0,115,XED_EXCEPTION_INVALID), +/*2432*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_MEMqq,2919,4,0,0,115,XED_EXCEPTION_INVALID), +/*2433*/ XED_DEF_INST(XED_ICLASS_VFMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDPD_YMMqq_YMMqq_YMMqq_YMMqq,2923,4,0,0,115,XED_EXCEPTION_INVALID), +/*2434*/ XED_DEF_INST(XED_ICLASS_VFMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSS_XMMdq_XMMd_MEMd_XMMd,2927,4,0,0,116,XED_EXCEPTION_INVALID), +/*2435*/ XED_DEF_INST(XED_ICLASS_VFMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd,2931,4,0,0,116,XED_EXCEPTION_INVALID), +/*2436*/ XED_DEF_INST(XED_ICLASS_VFMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_MEMd,2935,4,0,0,116,XED_EXCEPTION_INVALID), +/*2437*/ XED_DEF_INST(XED_ICLASS_VFMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSS_XMMdq_XMMd_XMMd_XMMd,2939,4,0,0,116,XED_EXCEPTION_INVALID), +/*2438*/ XED_DEF_INST(XED_ICLASS_VFMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSD_XMMdq_XMMq_MEMq_XMMq,2943,4,0,0,116,XED_EXCEPTION_INVALID), +/*2439*/ XED_DEF_INST(XED_ICLASS_VFMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq,2947,4,0,0,116,XED_EXCEPTION_INVALID), +/*2440*/ XED_DEF_INST(XED_ICLASS_VFMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_MEMq,2951,4,0,0,116,XED_EXCEPTION_INVALID), +/*2441*/ XED_DEF_INST(XED_ICLASS_VFMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMADDSD_XMMdq_XMMq_XMMq_XMMq,2955,4,0,0,116,XED_EXCEPTION_INVALID), +/*2442*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq,2863,4,0,0,115,XED_EXCEPTION_INVALID), +/*2443*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq,2867,4,0,0,115,XED_EXCEPTION_INVALID), +/*2444*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq,2871,4,0,0,115,XED_EXCEPTION_INVALID), +/*2445*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq,2875,4,0,0,115,XED_EXCEPTION_INVALID), +/*2446*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq,2879,4,0,0,115,XED_EXCEPTION_INVALID), +/*2447*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq,2883,4,0,0,115,XED_EXCEPTION_INVALID), +/*2448*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq,2887,4,0,0,115,XED_EXCEPTION_INVALID), +/*2449*/ XED_DEF_INST(XED_ICLASS_VFMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq,2891,4,0,0,115,XED_EXCEPTION_INVALID), +/*2450*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq,2895,4,0,0,115,XED_EXCEPTION_INVALID), +/*2451*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq,2899,4,0,0,115,XED_EXCEPTION_INVALID), +/*2452*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq,2903,4,0,0,115,XED_EXCEPTION_INVALID), +/*2453*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq,2907,4,0,0,115,XED_EXCEPTION_INVALID), +/*2454*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq,2911,4,0,0,115,XED_EXCEPTION_INVALID), +/*2455*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq,2915,4,0,0,115,XED_EXCEPTION_INVALID), +/*2456*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq,2919,4,0,0,115,XED_EXCEPTION_INVALID), +/*2457*/ XED_DEF_INST(XED_ICLASS_VFMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq,2923,4,0,0,115,XED_EXCEPTION_INVALID), +/*2458*/ XED_DEF_INST(XED_ICLASS_VFMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSS_XMMdq_XMMd_MEMd_XMMd,2927,4,0,0,116,XED_EXCEPTION_INVALID), +/*2459*/ XED_DEF_INST(XED_ICLASS_VFMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd,2931,4,0,0,116,XED_EXCEPTION_INVALID), +/*2460*/ XED_DEF_INST(XED_ICLASS_VFMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_MEMd,2935,4,0,0,116,XED_EXCEPTION_INVALID), +/*2461*/ XED_DEF_INST(XED_ICLASS_VFMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSS_XMMdq_XMMd_XMMd_XMMd,2939,4,0,0,116,XED_EXCEPTION_INVALID), +/*2462*/ XED_DEF_INST(XED_ICLASS_VFMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSD_XMMdq_XMMq_MEMq_XMMq,2943,4,0,0,116,XED_EXCEPTION_INVALID), +/*2463*/ XED_DEF_INST(XED_ICLASS_VFMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq,2947,4,0,0,116,XED_EXCEPTION_INVALID), +/*2464*/ XED_DEF_INST(XED_ICLASS_VFMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_MEMq,2951,4,0,0,116,XED_EXCEPTION_INVALID), +/*2465*/ XED_DEF_INST(XED_ICLASS_VFMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFMSUBSD_XMMdq_XMMq_XMMq_XMMq,2955,4,0,0,116,XED_EXCEPTION_INVALID), +/*2466*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_XMMdq_XMMdq_MEMdq_XMMdq,2863,4,0,0,115,XED_EXCEPTION_INVALID), +/*2467*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq,2867,4,0,0,115,XED_EXCEPTION_INVALID), +/*2468*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_MEMdq,2871,4,0,0,115,XED_EXCEPTION_INVALID), +/*2469*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_XMMdq_XMMdq_XMMdq_XMMdq,2875,4,0,0,115,XED_EXCEPTION_INVALID), +/*2470*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_YMMqq_YMMqq_MEMqq_YMMqq,2879,4,0,0,115,XED_EXCEPTION_INVALID), +/*2471*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq,2883,4,0,0,115,XED_EXCEPTION_INVALID), +/*2472*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_MEMqq,2887,4,0,0,115,XED_EXCEPTION_INVALID), +/*2473*/ XED_DEF_INST(XED_ICLASS_VFNMADDPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPS_YMMqq_YMMqq_YMMqq_YMMqq,2891,4,0,0,115,XED_EXCEPTION_INVALID), +/*2474*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_XMMdq_XMMdq_MEMdq_XMMdq,2895,4,0,0,115,XED_EXCEPTION_INVALID), +/*2475*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq,2899,4,0,0,115,XED_EXCEPTION_INVALID), +/*2476*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_MEMdq,2903,4,0,0,115,XED_EXCEPTION_INVALID), +/*2477*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_XMMdq_XMMdq_XMMdq_XMMdq,2907,4,0,0,115,XED_EXCEPTION_INVALID), +/*2478*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_YMMqq_YMMqq_MEMqq_YMMqq,2911,4,0,0,115,XED_EXCEPTION_INVALID), +/*2479*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq,2915,4,0,0,115,XED_EXCEPTION_INVALID), +/*2480*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_MEMqq,2919,4,0,0,115,XED_EXCEPTION_INVALID), +/*2481*/ XED_DEF_INST(XED_ICLASS_VFNMADDPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDPD_YMMqq_YMMqq_YMMqq_YMMqq,2923,4,0,0,115,XED_EXCEPTION_INVALID), +/*2482*/ XED_DEF_INST(XED_ICLASS_VFNMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSS_XMMdq_XMMd_MEMd_XMMd,2927,4,0,0,116,XED_EXCEPTION_INVALID), +/*2483*/ XED_DEF_INST(XED_ICLASS_VFNMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd,2931,4,0,0,116,XED_EXCEPTION_INVALID), +/*2484*/ XED_DEF_INST(XED_ICLASS_VFNMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_MEMd,2935,4,0,0,116,XED_EXCEPTION_INVALID), +/*2485*/ XED_DEF_INST(XED_ICLASS_VFNMADDSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSS_XMMdq_XMMd_XMMd_XMMd,2939,4,0,0,116,XED_EXCEPTION_INVALID), +/*2486*/ XED_DEF_INST(XED_ICLASS_VFNMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSD_XMMdq_XMMq_MEMq_XMMq,2943,4,0,0,116,XED_EXCEPTION_INVALID), +/*2487*/ XED_DEF_INST(XED_ICLASS_VFNMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq,2947,4,0,0,116,XED_EXCEPTION_INVALID), +/*2488*/ XED_DEF_INST(XED_ICLASS_VFNMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_MEMq,2951,4,0,0,116,XED_EXCEPTION_INVALID), +/*2489*/ XED_DEF_INST(XED_ICLASS_VFNMADDSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMADDSD_XMMdq_XMMq_XMMq_XMMq,2955,4,0,0,116,XED_EXCEPTION_INVALID), +/*2490*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_MEMdq_XMMdq,2863,4,0,0,115,XED_EXCEPTION_INVALID), +/*2491*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq,2867,4,0,0,115,XED_EXCEPTION_INVALID), +/*2492*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_MEMdq,2871,4,0,0,115,XED_EXCEPTION_INVALID), +/*2493*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_XMMdq_XMMdq_XMMdq_XMMdq,2875,4,0,0,115,XED_EXCEPTION_INVALID), +/*2494*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_MEMqq_YMMqq,2879,4,0,0,115,XED_EXCEPTION_INVALID), +/*2495*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq,2883,4,0,0,115,XED_EXCEPTION_INVALID), +/*2496*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_MEMqq,2887,4,0,0,115,XED_EXCEPTION_INVALID), +/*2497*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPS_YMMqq_YMMqq_YMMqq_YMMqq,2891,4,0,0,115,XED_EXCEPTION_INVALID), +/*2498*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_MEMdq_XMMdq,2895,4,0,0,115,XED_EXCEPTION_INVALID), +/*2499*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq,2899,4,0,0,115,XED_EXCEPTION_INVALID), +/*2500*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_MEMdq,2903,4,0,0,115,XED_EXCEPTION_INVALID), +/*2501*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_XMMdq_XMMdq_XMMdq_XMMdq,2907,4,0,0,115,XED_EXCEPTION_INVALID), +/*2502*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_MEMqq_YMMqq,2911,4,0,0,115,XED_EXCEPTION_INVALID), +/*2503*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq,2915,4,0,0,115,XED_EXCEPTION_INVALID), +/*2504*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_MEMqq,2919,4,0,0,115,XED_EXCEPTION_INVALID), +/*2505*/ XED_DEF_INST(XED_ICLASS_VFNMSUBPD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBPD_YMMqq_YMMqq_YMMqq_YMMqq,2923,4,0,0,115,XED_EXCEPTION_INVALID), +/*2506*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSS_XMMdq_XMMd_MEMd_XMMd,2927,4,0,0,116,XED_EXCEPTION_INVALID), +/*2507*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd,2931,4,0,0,116,XED_EXCEPTION_INVALID), +/*2508*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_MEMd,2935,4,0,0,116,XED_EXCEPTION_INVALID), +/*2509*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSS,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSS_XMMdq_XMMd_XMMd_XMMd,2939,4,0,0,116,XED_EXCEPTION_INVALID), +/*2510*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSD_XMMdq_XMMq_MEMq_XMMq,2943,4,0,0,116,XED_EXCEPTION_INVALID), +/*2511*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq,2947,4,0,0,116,XED_EXCEPTION_INVALID), +/*2512*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_MEMq,2951,4,0,0,116,XED_EXCEPTION_INVALID), +/*2513*/ XED_DEF_INST(XED_ICLASS_VFNMSUBSD,XED_CATEGORY_FMA4,XED_EXTENSION_FMA4,3,XED_IFORM_VFNMSUBSD_XMMdq_XMMq_XMMq_XMMq,2955,4,0,0,116,XED_EXCEPTION_INVALID), +/*2514*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_MEMdq_XMMdq_IMMb,2959,5,0,0,105,XED_EXCEPTION_INVALID), +/*2515*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb,2964,5,0,0,105,XED_EXCEPTION_INVALID), +/*2516*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_MEMqq_YMMqq_IMMb,2969,5,0,0,105,XED_EXCEPTION_INVALID), +/*2517*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb,2974,5,0,0,105,XED_EXCEPTION_INVALID), +/*2518*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_MEMdq_IMMb,2979,5,0,0,105,XED_EXCEPTION_INVALID), +/*2519*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_XMMdq_XMMdq_XMMdq_XMMdq_IMMb,2984,5,0,0,105,XED_EXCEPTION_INVALID), +/*2520*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_MEMqq_IMMb,2989,5,0,0,105,XED_EXCEPTION_INVALID), +/*2521*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PS,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PS_YMMqq_YMMqq_YMMqq_YMMqq_IMMb,2994,5,0,0,105,XED_EXCEPTION_INVALID), +/*2522*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_MEMdq_XMMdq_IMMb,2999,5,0,0,105,XED_EXCEPTION_INVALID), +/*2523*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb,3004,5,0,0,105,XED_EXCEPTION_INVALID), +/*2524*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_MEMqq_YMMqq_IMMb,3009,5,0,0,105,XED_EXCEPTION_INVALID), +/*2525*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb,3014,5,0,0,105,XED_EXCEPTION_INVALID), +/*2526*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_MEMdq_IMMb,3019,5,0,0,105,XED_EXCEPTION_INVALID), +/*2527*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_XMMdq_XMMdq_XMMdq_XMMdq_IMMb,3024,5,0,0,105,XED_EXCEPTION_INVALID), +/*2528*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_MEMqq_IMMb,3029,5,0,0,105,XED_EXCEPTION_INVALID), +/*2529*/ XED_DEF_INST(XED_ICLASS_VPERMIL2PD,XED_CATEGORY_XOP,XED_EXTENSION_XOP,3,XED_IFORM_VPERMIL2PD_YMMqq_YMMqq_YMMqq_YMMqq_IMMb,3034,5,0,0,105,XED_EXCEPTION_INVALID), +/*2530*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2531*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2532*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2533*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2534*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2535*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2536*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2537*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2538*/ XED_DEF_INST(XED_ICLASS_VADDSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2539*/ XED_DEF_INST(XED_ICLASS_VADDSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2540*/ XED_DEF_INST(XED_ICLASS_VADDSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2541*/ XED_DEF_INST(XED_ICLASS_VADDSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2542*/ XED_DEF_INST(XED_ICLASS_VADDSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2543*/ XED_DEF_INST(XED_ICLASS_VADDSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2544*/ XED_DEF_INST(XED_ICLASS_VADDSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2545*/ XED_DEF_INST(XED_ICLASS_VADDSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2546*/ XED_DEF_INST(XED_ICLASS_VADDSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2547*/ XED_DEF_INST(XED_ICLASS_VADDSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2548*/ XED_DEF_INST(XED_ICLASS_VADDSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2549*/ XED_DEF_INST(XED_ICLASS_VADDSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VADDSUBPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2550*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPD_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2551*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPD_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2552*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPD_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2553*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPD_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2554*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPS_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2555*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPS_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2556*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPS_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2557*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDPS_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2558*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPD_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2559*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPD_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2560*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPD_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2561*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPD_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2562*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPS_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2563*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPS_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2564*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPS_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2565*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VANDNPS_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2566*/ XED_DEF_INST(XED_ICLASS_VBLENDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPD_XMMdq_XMMdq_MEMdq_IMMb,3087,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2567*/ XED_DEF_INST(XED_ICLASS_VBLENDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPD_XMMdq_XMMdq_XMMdq_IMMb,3091,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2568*/ XED_DEF_INST(XED_ICLASS_VBLENDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPD_YMMqq_YMMqq_MEMqq_IMMb,3095,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2569*/ XED_DEF_INST(XED_ICLASS_VBLENDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPD_YMMqq_YMMqq_YMMqq_IMMb,3099,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2570*/ XED_DEF_INST(XED_ICLASS_VBLENDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPS_XMMdq_XMMdq_MEMdq_IMMb,3103,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2571*/ XED_DEF_INST(XED_ICLASS_VBLENDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPS_XMMdq_XMMdq_XMMdq_IMMb,3107,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2572*/ XED_DEF_INST(XED_ICLASS_VBLENDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPS_YMMqq_YMMqq_MEMqq_IMMb,3111,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2573*/ XED_DEF_INST(XED_ICLASS_VBLENDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDPS_YMMqq_YMMqq_YMMqq_IMMb,3115,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2574*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPD_XMMdq_XMMdq_MEMdq_IMMb,3087,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2575*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPD_XMMdq_XMMdq_XMMdq_IMMb,3091,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2576*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPD_YMMqq_YMMqq_MEMqq_IMMb,3095,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2577*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPD_YMMqq_YMMqq_YMMqq_IMMb,3099,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2578*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPS_XMMdq_XMMdq_MEMdq_IMMb,3103,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2579*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPS_XMMdq_XMMdq_XMMdq_IMMb,3107,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2580*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPS_YMMqq_YMMqq_MEMqq_IMMb,3111,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2581*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPPS_YMMqq_YMMqq_YMMqq_IMMb,3115,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2582*/ XED_DEF_INST(XED_ICLASS_VCMPSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPSD_XMMdq_XMMdq_MEMq_IMMb,3119,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2583*/ XED_DEF_INST(XED_ICLASS_VCMPSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPSD_XMMdq_XMMdq_XMMq_IMMb,3123,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2584*/ XED_DEF_INST(XED_ICLASS_VCMPSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPSS_XMMdq_XMMdq_MEMd_IMMb,3127,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2585*/ XED_DEF_INST(XED_ICLASS_VCMPSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCMPSS_XMMdq_XMMdq_XMMd_IMMb,3131,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2586*/ XED_DEF_INST(XED_ICLASS_VCOMISD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCOMISD_XMMq_MEMq,3135,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2587*/ XED_DEF_INST(XED_ICLASS_VCOMISD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCOMISD_XMMq_XMMq,3138,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2588*/ XED_DEF_INST(XED_ICLASS_VCOMISS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCOMISS_XMMd_MEMd,3141,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2589*/ XED_DEF_INST(XED_ICLASS_VCOMISS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VCOMISS_XMMd_XMMd,3144,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2590*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PD_XMMdq_MEMq,3147,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2591*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PD_XMMdq_XMMq,3149,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2592*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PD_YMMqq_MEMdq,3151,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2593*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PD_YMMqq_XMMdq,3153,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2594*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PS_XMMdq_MEMdq,3155,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2595*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PS_XMMdq_XMMdq,3157,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2596*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PS_YMMqq_MEMqq,3159,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2597*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTDQ2PS_YMMqq_YMMqq,3161,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2598*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2DQ_XMMdq_MEMdq,3163,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2599*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2DQ_XMMdq_XMMdq,3165,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2600*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2DQ_XMMdq_MEMqq,3167,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2601*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2DQ_XMMdq_YMMqq,3169,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2602*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPD2DQ_XMMdq_MEMdq,3163,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2603*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPD2DQ_XMMdq_XMMdq,3165,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2604*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPD2DQ_XMMdq_MEMqq,3167,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2605*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPD2DQ_XMMdq_YMMqq,3169,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2606*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2PS_XMMdq_MEMdq,3171,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2607*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2PS_XMMdq_XMMdq,3173,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2608*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2PS_XMMdq_MEMqq,3175,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2609*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPD2PS_XMMdq_YMMqq,3177,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2610*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2DQ_XMMdq_MEMdq,3179,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2611*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2DQ_XMMdq_XMMdq,3181,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2612*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2DQ_YMMqq_MEMqq,3183,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2613*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2DQ_YMMqq_YMMqq,3185,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2614*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPS2DQ_XMMdq_MEMdq,3179,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2615*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPS2DQ_XMMdq_XMMdq,3181,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2616*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPS2DQ_YMMqq_MEMqq,3183,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2617*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTPS2DQ_YMMqq_YMMqq,3185,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2618*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2PD_XMMdq_MEMq,3187,2,0,0,47,XED_EXCEPTION_AVX_TYPE_3), +/*2619*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2PD_XMMdq_XMMq,3189,2,0,0,47,XED_EXCEPTION_AVX_TYPE_3), +/*2620*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2PD_YMMqq_MEMdq,3191,2,0,0,47,XED_EXCEPTION_AVX_TYPE_3), +/*2621*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTPS2PD_YMMqq_XMMdq,3193,2,0,0,47,XED_EXCEPTION_AVX_TYPE_3), +/*2622*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SI_GPR32d_MEMq,3195,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2623*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SI_GPR32d_XMMq,3197,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2624*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SI_GPR32d_MEMq,3195,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2625*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SI_GPR32d_XMMq,3197,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2626*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SI_GPR64q_MEMq,3199,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2627*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SI_GPR64q_XMMq,3201,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2628*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSD2SI_GPR32d_MEMq,3195,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2629*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSD2SI_GPR32d_XMMq,3197,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2630*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSD2SI_GPR32d_MEMq,3195,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2631*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSD2SI_GPR32d_XMMq,3197,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2632*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSD2SI_GPR64q_MEMq,3199,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2633*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSD2SI_GPR64q_XMMq,3201,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2634*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SI_GPR32d_MEMd,3203,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2635*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SI_GPR32d_XMMd,3205,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2636*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SI_GPR32d_MEMd,3203,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2637*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SI_GPR32d_XMMd,3205,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2638*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SI_GPR64q_MEMd,3207,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2639*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SI_GPR64q_XMMd,3209,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2640*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSS2SI_GPR32d_MEMd,3203,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2641*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSS2SI_GPR32d_XMMd,3205,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2642*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSS2SI_GPR32d_MEMd,3203,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2643*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSS2SI_GPR32d_XMMd,3205,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2644*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSS2SI_GPR64q_MEMd,3207,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2645*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTTSS2SI_GPR64q_XMMd,3209,2,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2646*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_MEMq,3211,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2647*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSD2SS_XMMdq_XMMdq_XMMq,3214,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2648*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd,3217,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2649*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d,3220,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2650*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMd,3217,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2651*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR32d,3220,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2652*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_MEMq,3223,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2653*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SD_XMMdq_XMMdq_GPR64q,3226,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2654*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd,3229,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2655*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d,3232,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2656*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMd,3229,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2657*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR32d,3232,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2658*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_MEMq,3235,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2659*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSI2SS_XMMdq_XMMdq_GPR64q,3238,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2660*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_MEMd,3241,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2661*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX,3,XED_IFORM_VCVTSS2SD_XMMdq_XMMdq_XMMd,3244,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2662*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2663*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2664*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2665*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2666*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2667*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2668*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2669*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2670*/ XED_DEF_INST(XED_ICLASS_VDIVSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2671*/ XED_DEF_INST(XED_ICLASS_VDIVSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2672*/ XED_DEF_INST(XED_ICLASS_VDIVSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2673*/ XED_DEF_INST(XED_ICLASS_VDIVSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDIVSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2674*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF128,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VEXTRACTF128_MEMdq_YMMdq_IMMb,3247,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2675*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF128,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VEXTRACTF128_XMMdq_YMMdq_IMMb,3250,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2676*/ XED_DEF_INST(XED_ICLASS_VDPPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDPPD_XMMdq_XMMdq_MEMdq_IMMb,3087,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2D), +/*2677*/ XED_DEF_INST(XED_ICLASS_VDPPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDPPD_XMMdq_XMMdq_XMMdq_IMMb,3091,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2D), +/*2678*/ XED_DEF_INST(XED_ICLASS_VDPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDPPS_XMMdq_XMMdq_MEMdq_IMMb,3103,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2D), +/*2679*/ XED_DEF_INST(XED_ICLASS_VDPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDPPS_XMMdq_XMMdq_XMMdq_IMMb,3107,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2D), +/*2680*/ XED_DEF_INST(XED_ICLASS_VDPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDPPS_YMMqq_YMMqq_MEMqq_IMMb,3111,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2D), +/*2681*/ XED_DEF_INST(XED_ICLASS_VDPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VDPPS_YMMqq_YMMqq_YMMqq_IMMb,3115,4,0,0,47,XED_EXCEPTION_AVX_TYPE_2D), +/*2682*/ XED_DEF_INST(XED_ICLASS_VEXTRACTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VEXTRACTPS_MEMd_XMMdq_IMMb,3253,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2683*/ XED_DEF_INST(XED_ICLASS_VEXTRACTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VEXTRACTPS_GPR32_XMMdq_IMMb,3256,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2684*/ XED_DEF_INST(XED_ICLASS_VZEROALL,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VZEROALL,0,0,0,0,118,XED_EXCEPTION_AVX_TYPE_8), +/*2685*/ XED_DEF_INST(XED_ICLASS_VZEROUPPER,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VZEROUPPER,0,0,0,0,119,XED_EXCEPTION_AVX_TYPE_8), +/*2686*/ XED_DEF_INST(XED_ICLASS_VHADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2687*/ XED_DEF_INST(XED_ICLASS_VHADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2688*/ XED_DEF_INST(XED_ICLASS_VHADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2689*/ XED_DEF_INST(XED_ICLASS_VHADDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2690*/ XED_DEF_INST(XED_ICLASS_VHADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2691*/ XED_DEF_INST(XED_ICLASS_VHADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2692*/ XED_DEF_INST(XED_ICLASS_VHADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2693*/ XED_DEF_INST(XED_ICLASS_VHADDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHADDPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2694*/ XED_DEF_INST(XED_ICLASS_VHSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2695*/ XED_DEF_INST(XED_ICLASS_VHSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2696*/ XED_DEF_INST(XED_ICLASS_VHSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2697*/ XED_DEF_INST(XED_ICLASS_VHSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2698*/ XED_DEF_INST(XED_ICLASS_VHSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2699*/ XED_DEF_INST(XED_ICLASS_VHSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2700*/ XED_DEF_INST(XED_ICLASS_VHSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2701*/ XED_DEF_INST(XED_ICLASS_VHSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VHSUBPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2702*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_XMMdq_XMMdq_MEMdq,3259,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2703*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_XMMdq_XMMdq_XMMdq,3262,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2704*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_YMMqq_YMMqq_MEMqq,3265,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2705*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_YMMqq_YMMqq_YMMqq,3268,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2706*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_XMMdq_MEMdq_IMMb,3271,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2707*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_XMMdq_XMMdq_IMMb,3274,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2708*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_YMMqq_MEMqq_IMMb,3277,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2709*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPD_YMMqq_YMMqq_IMMb,3280,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2710*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_XMMdq_XMMdq_MEMdq,3283,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2711*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_XMMdq_XMMdq_XMMdq,3286,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2712*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_YMMqq_YMMqq_MEMqq,3289,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2713*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_YMMqq_YMMqq_YMMqq,3292,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2714*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_XMMdq_MEMdq_IMMb,3295,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2715*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_XMMdq_XMMdq_IMMb,3298,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2716*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_YMMqq_MEMqq_IMMb,3301,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2717*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERMILPS_YMMqq_YMMqq_IMMb,3304,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2718*/ XED_DEF_INST(XED_ICLASS_VPERM2F128,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERM2F128_YMMqq_YMMqq_MEMqq_IMMb,3095,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2719*/ XED_DEF_INST(XED_ICLASS_VPERM2F128,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPERM2F128_YMMqq_YMMqq_YMMqq_IMMb,3099,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2720*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX,3,XED_IFORM_VBROADCASTSS_XMMdq_MEMd,2712,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2721*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX,3,XED_IFORM_VBROADCASTSS_YMMqq_MEMd,3307,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2722*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VBROADCASTSS_XMMdq_XMMdq,2698,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2723*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VBROADCASTSS_YMMqq_XMMdq,3309,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2724*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX,3,XED_IFORM_VBROADCASTSD_YMMqq_MEMq,3311,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2725*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VBROADCASTSD_YMMqq_XMMdq,3313,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2726*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF128,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX,3,XED_IFORM_VBROADCASTF128_YMMqq_MEMdq,3315,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2727*/ XED_DEF_INST(XED_ICLASS_VINSERTF128,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VINSERTF128_YMMqq_YMMqq_MEMdq_IMMb,3317,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2728*/ XED_DEF_INST(XED_ICLASS_VINSERTF128,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VINSERTF128_YMMqq_YMMqq_XMMdq_IMMb,3321,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*2729*/ XED_DEF_INST(XED_ICLASS_VINSERTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VINSERTPS_XMMdq_XMMdq_MEMd_IMMb,3127,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2730*/ XED_DEF_INST(XED_ICLASS_VINSERTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VINSERTPS_XMMdq_XMMdq_XMMdq_IMMb,3107,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2731*/ XED_DEF_INST(XED_ICLASS_VLDDQU,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VLDDQU_XMMdq_MEMdq,1864,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2732*/ XED_DEF_INST(XED_ICLASS_VLDDQU,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VLDDQU_YMMqq_MEMqq,3325,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2733*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPS_XMMdq_XMMdq_MEMdq,3327,3,0,0,120,XED_EXCEPTION_AVX_TYPE_6), +/*2734*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPS_YMMqq_YMMqq_MEMqq,3330,3,0,0,120,XED_EXCEPTION_AVX_TYPE_6), +/*2735*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPS_MEMdq_XMMdq_XMMdq,3333,3,0,0,120,XED_EXCEPTION_AVX_TYPE_6), +/*2736*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPS_MEMqq_YMMqq_YMMqq,3336,3,0,0,120,XED_EXCEPTION_AVX_TYPE_6), +/*2737*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPD_XMMdq_XMMdq_MEMdq,3339,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*2738*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPD_YMMqq_YMMqq_MEMqq,3342,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*2739*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPD_MEMdq_XMMdq_XMMdq,3345,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*2740*/ XED_DEF_INST(XED_ICLASS_VMASKMOVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVPD_MEMqq_YMMqq_YMMqq,3348,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*2741*/ XED_DEF_INST(XED_ICLASS_VPTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPTEST_XMMdq_MEMdq,2041,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2742*/ XED_DEF_INST(XED_ICLASS_VPTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPTEST_XMMdq_XMMdq,2044,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2743*/ XED_DEF_INST(XED_ICLASS_VPTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPTEST_YMMqq_MEMqq,3351,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2744*/ XED_DEF_INST(XED_ICLASS_VPTEST,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPTEST_YMMqq_YMMqq,3354,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2745*/ XED_DEF_INST(XED_ICLASS_VTESTPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPS_XMMdq_MEMdq,3357,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2746*/ XED_DEF_INST(XED_ICLASS_VTESTPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPS_XMMdq_XMMdq,3360,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2747*/ XED_DEF_INST(XED_ICLASS_VTESTPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPS_YMMqq_MEMqq,3363,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2748*/ XED_DEF_INST(XED_ICLASS_VTESTPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPS_YMMqq_YMMqq,3366,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2749*/ XED_DEF_INST(XED_ICLASS_VTESTPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPD_XMMdq_MEMdq,3369,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2750*/ XED_DEF_INST(XED_ICLASS_VTESTPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPD_XMMdq_XMMdq,3372,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2751*/ XED_DEF_INST(XED_ICLASS_VTESTPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPD_YMMqq_MEMqq,3375,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2752*/ XED_DEF_INST(XED_ICLASS_VTESTPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VTESTPD_YMMqq_YMMqq,3378,3,92,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2753*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2754*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2755*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2756*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2757*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2758*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2759*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2760*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2761*/ XED_DEF_INST(XED_ICLASS_VMAXSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2762*/ XED_DEF_INST(XED_ICLASS_VMAXSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2763*/ XED_DEF_INST(XED_ICLASS_VMAXSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2764*/ XED_DEF_INST(XED_ICLASS_VMAXSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMAXSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2765*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2766*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2767*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2768*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2769*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2770*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2771*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2772*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*2773*/ XED_DEF_INST(XED_ICLASS_VMINSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2774*/ XED_DEF_INST(XED_ICLASS_VMINSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2775*/ XED_DEF_INST(XED_ICLASS_VMINSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2776*/ XED_DEF_INST(XED_ICLASS_VMINSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMINSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*2777*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_XMMdq_MEMdq,2704,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2778*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_XMMdq_XMMdq_28,2706,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2779*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_MEMdq_XMMdq,3381,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2780*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_XMMdq_XMMdq_29,3383,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2781*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_YMMqq_MEMqq,2708,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2782*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_YMMqq_YMMqq_28,2710,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2783*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_MEMqq_YMMqq,3385,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2784*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPD_YMMqq_YMMqq_29,3387,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2785*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_XMMdq_MEMdq,2696,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2786*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_XMMdq_XMMdq_28,2698,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2787*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_MEMdq_XMMdq,3389,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2788*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_XMMdq_XMMdq_29,3391,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2789*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_YMMqq_MEMqq,2700,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2790*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_YMMqq_YMMqq_28,2702,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2791*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_MEMqq_YMMqq,3393,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2792*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVAPS_YMMqq_YMMqq_29,3395,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2793*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_XMMdq_MEMd,1830,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2794*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_XMMdq_GPR32d,3397,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2795*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_MEMd_XMMd,1834,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2796*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_GPR32d_XMMd,3399,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2797*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_XMMdq_MEMd,1830,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2798*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_XMMdq_GPR32d,3397,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2799*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_MEMd_XMMd,1834,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2800*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVD_GPR32d_XMMd,3399,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2801*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_XMMdq_MEMq_6E,1450,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2802*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_XMMdq_GPR64q,3401,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2803*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_MEMq_XMMq_7E,1848,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2804*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_GPR64q_XMMq,3403,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2805*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_XMMdq_MEMq_7E,1450,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2806*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_XMMdq_XMMq_7E,1452,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2807*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_MEMq_XMMq_D6,1848,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2808*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVQ_XMMdq_XMMq_D6,1852,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2809*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDDUP_XMMdq_MEMq,2716,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2810*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDDUP_XMMdq_XMMq,2718,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2811*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDDUP_YMMqq_MEMqq,2708,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2812*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDDUP_YMMqq_YMMqq,2710,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*2813*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_XMMdq_MEMdq,1864,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2814*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_XMMdq_XMMdq_6F,1866,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2815*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_MEMdq_XMMdq,1708,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2816*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_XMMdq_XMMdq_7F,1868,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2817*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_YMMqq_MEMqq,3325,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2818*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_YMMqq_YMMqq_6F,3405,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2819*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_MEMqq_YMMqq,3407,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2820*/ XED_DEF_INST(XED_ICLASS_VMOVDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQA_YMMqq_YMMqq_7F,3409,2,0,0,44,XED_EXCEPTION_AVX_TYPE_1), +/*2821*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_XMMdq_MEMdq,1864,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2822*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_XMMdq_XMMdq_6F,1866,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2823*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_YMMqq_MEMqq,3325,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2824*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_YMMqq_YMMqq_6F,3405,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2825*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_MEMdq_XMMdq,1708,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2826*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_XMMdq_XMMdq_7F,1868,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2827*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_MEMqq_YMMqq,3407,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2828*/ XED_DEF_INST(XED_ICLASS_VMOVDQU,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVDQU_YMMqq_YMMqq_7F,3409,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*2829*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSHDUP_XMMdq_MEMdq,2696,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2830*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSHDUP_XMMdq_XMMdq,2698,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2831*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSHDUP_YMMqq_MEMqq,2700,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2832*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSHDUP_YMMqq_YMMqq,2702,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2833*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSLDUP_XMMdq_MEMdq,2696,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2834*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSLDUP_XMMdq_XMMdq,2698,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2835*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSLDUP_YMMqq_MEMqq,2700,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2836*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSLDUP_YMMqq_YMMqq,2702,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2837*/ XED_DEF_INST(XED_ICLASS_VPOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPOR_XMMdq_XMMdq_MEMdq,3411,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2838*/ XED_DEF_INST(XED_ICLASS_VPOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPOR_XMMdq_XMMdq_XMMdq,3414,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2839*/ XED_DEF_INST(XED_ICLASS_VPOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPOR_YMMqq_YMMqq_MEMqq,3417,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2840*/ XED_DEF_INST(XED_ICLASS_VPOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPOR_YMMqq_YMMqq_YMMqq,3420,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2841*/ XED_DEF_INST(XED_ICLASS_VPAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPAND_XMMdq_XMMdq_MEMdq,3411,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2842*/ XED_DEF_INST(XED_ICLASS_VPAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPAND_XMMdq_XMMdq_XMMdq,3414,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2843*/ XED_DEF_INST(XED_ICLASS_VPAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPAND_YMMqq_YMMqq_MEMqq,3417,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2844*/ XED_DEF_INST(XED_ICLASS_VPAND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPAND_YMMqq_YMMqq_YMMqq,3420,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2845*/ XED_DEF_INST(XED_ICLASS_VPANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPANDN_XMMdq_XMMdq_MEMdq,3411,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2846*/ XED_DEF_INST(XED_ICLASS_VPANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPANDN_XMMdq_XMMdq_XMMdq,3414,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2847*/ XED_DEF_INST(XED_ICLASS_VPANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPANDN_YMMqq_YMMqq_MEMqq,3417,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2848*/ XED_DEF_INST(XED_ICLASS_VPANDN,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPANDN_YMMqq_YMMqq_YMMqq,3420,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2849*/ XED_DEF_INST(XED_ICLASS_VPXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPXOR_XMMdq_XMMdq_MEMdq,3411,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2850*/ XED_DEF_INST(XED_ICLASS_VPXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX,3,XED_IFORM_VPXOR_XMMdq_XMMdq_XMMdq,3414,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2851*/ XED_DEF_INST(XED_ICLASS_VPXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPXOR_YMMqq_YMMqq_MEMqq,3417,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2852*/ XED_DEF_INST(XED_ICLASS_VPXOR,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX2,3,XED_IFORM_VPXOR_YMMqq_YMMqq_YMMqq,3420,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2853*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPABSB_XMMdq_MEMdq,3423,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2854*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPABSB_XMMdq_XMMdq,3425,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2855*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPABSB_YMMqq_MEMqq,3427,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2856*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPABSB_YMMqq_YMMqq,3429,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2857*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPABSW_XMMdq_MEMdq,3431,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2858*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPABSW_XMMdq_XMMdq,3433,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2859*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPABSW_YMMqq_MEMqq,3435,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2860*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPABSW_YMMqq_YMMqq,3437,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2861*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPABSD_XMMdq_MEMdq,3439,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2862*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPABSD_XMMdq_XMMdq,3441,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2863*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPABSD_YMMqq_MEMqq,3443,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2864*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPABSD_YMMqq_YMMqq,3445,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2865*/ XED_DEF_INST(XED_ICLASS_VPHMINPOSUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHMINPOSUW_XMMdq_MEMdq,3447,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2866*/ XED_DEF_INST(XED_ICLASS_VPHMINPOSUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHMINPOSUW_XMMdq_XMMdq,3449,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2867*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFD_XMMdq_MEMdq_IMMb,2202,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2868*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFD_XMMdq_XMMdq_IMMb,2199,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2869*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFD_YMMqq_MEMqq_IMMb,3451,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2870*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFD_YMMqq_YMMqq_IMMb,3454,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2871*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFHW_XMMdq_MEMdq_IMMb,2202,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2872*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFHW_XMMdq_XMMdq_IMMb,2199,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2873*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFHW_YMMqq_MEMqq_IMMb,3457,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2874*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFHW_YMMqq_YMMqq_IMMb,3460,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2875*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFLW_XMMdq_MEMdq_IMMb,2202,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2876*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFLW_XMMdq_XMMdq_IMMb,2199,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2877*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFLW_YMMqq_MEMqq_IMMb,3457,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2878*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFLW_YMMqq_YMMqq_IMMb,3460,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2879*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKSSWB_XMMdq_XMMdq_MEMdq,3463,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2880*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKSSWB_XMMdq_XMMdq_XMMdq,3466,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2881*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKSSWB_YMMqq_YMMqq_MEMqq,3469,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2882*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKSSWB_YMMqq_YMMqq_YMMqq,3472,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2883*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKSSDW_XMMdq_XMMdq_MEMdq,3475,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2884*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKSSDW_XMMdq_XMMdq_XMMdq,3478,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2885*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKSSDW_YMMqq_YMMqq_MEMqq,3481,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2886*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKSSDW_YMMqq_YMMqq_YMMqq,3484,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2887*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKUSWB_XMMdq_XMMdq_MEMdq,3487,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2888*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKUSWB_XMMdq_XMMdq_XMMdq,3490,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2889*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKUSWB_YMMqq_YMMqq_MEMqq,3493,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2890*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKUSWB_YMMqq_YMMqq_YMMqq,3496,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2891*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKUSDW_XMMdq_XMMdq_MEMdq,3499,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2892*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPACKUSDW_XMMdq_XMMdq_XMMdq,3502,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2893*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKUSDW_YMMqq_YMMqq_MEMqq,3505,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2894*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPACKUSDW_YMMqq_YMMqq_YMMqq,3508,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2895*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLW_XMMdq_XMMdq_MEMdq,3511,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2896*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLW_XMMdq_XMMdq_XMMdq,3514,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2897*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLW_XMMdq_XMMdq_IMMb,3517,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2898*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLW_YMMqq_YMMqq_MEMdq,3520,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2899*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLW_YMMqq_YMMqq_XMMq,3523,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2900*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLW_YMMqq_YMMqq_IMMb,3526,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2901*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLD_XMMdq_XMMdq_MEMdq,3529,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2902*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLD_XMMdq_XMMdq_XMMdq,3532,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2903*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLD_XMMdq_XMMdq_IMMb,3535,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2904*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLD_YMMqq_YMMqq_MEMdq,3538,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2905*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLD_YMMqq_YMMqq_XMMq,3541,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2906*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLD_YMMqq_YMMqq_IMMb,3544,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2907*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2908*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2909*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLQ_XMMdq_XMMdq_IMMb,3547,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2910*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLQ_YMMqq_YMMqq_MEMdq,3550,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2911*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLQ_YMMqq_YMMqq_XMMq,3553,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2912*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLQ_YMMqq_YMMqq_IMMb,3556,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2913*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLW_XMMdq_XMMdq_MEMdq,3511,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2914*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLW_XMMdq_XMMdq_XMMdq,3514,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2915*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLW_XMMdq_XMMdq_IMMb,3517,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2916*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLW_YMMqq_YMMqq_MEMdq,3520,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2917*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLW_YMMqq_YMMqq_XMMq,3523,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2918*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLW_YMMqq_YMMqq_IMMb,3526,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2919*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLD_XMMdq_XMMdq_MEMdq,3529,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2920*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLD_XMMdq_XMMdq_XMMdq,3532,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2921*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLD_XMMdq_XMMdq_IMMb,3535,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2922*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLD_YMMqq_YMMqq_MEMdq,3538,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2923*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLD_YMMqq_YMMqq_XMMq,3541,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2924*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLD_YMMqq_YMMqq_IMMb,3544,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2925*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2926*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2927*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLQ_XMMdq_XMMdq_IMMb,3547,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2928*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLQ_YMMqq_YMMqq_MEMdq,3550,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2929*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLQ_YMMqq_YMMqq_XMMq,3553,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2930*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLQ_YMMqq_YMMqq_IMMb,3556,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2931*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRAW_XMMdq_XMMdq_MEMdq,3559,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2932*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRAW_XMMdq_XMMdq_XMMdq,3562,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2933*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRAW_XMMdq_XMMdq_IMMb,3565,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2934*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAW_YMMqq_YMMqq_MEMdq,3568,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2935*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAW_YMMqq_YMMqq_XMMq,3571,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2936*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAW_YMMqq_YMMqq_IMMb,3574,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2937*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRAD_XMMdq_XMMdq_MEMdq,3577,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2938*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRAD_XMMdq_XMMdq_XMMdq,3580,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2939*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRAD_XMMdq_XMMdq_IMMb,3583,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2940*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAD_YMMqq_YMMqq_MEMdq,3586,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2941*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAD_YMMqq_YMMqq_XMMq,3589,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2942*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAD_YMMqq_YMMqq_IMMb,3592,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*2943*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2944*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2945*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2946*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2947*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2948*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2949*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2950*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2951*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2952*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2953*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2954*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2955*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDQ_XMMdq_XMMdq_MEMdq,2810,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2956*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDQ_XMMdq_XMMdq_XMMdq,2813,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2957*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDQ_YMMqq_YMMqq_MEMqq,3607,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2958*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDQ_YMMqq_YMMqq_YMMqq,3610,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2959*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDSB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2960*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDSB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2961*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDSB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2962*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDSB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2963*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2964*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2965*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2966*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2967*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDUSB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2968*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDUSB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2969*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDUSB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2970*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDUSB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2971*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDUSW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2972*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPADDUSW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2973*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDUSW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2974*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPADDUSW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2975*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPAVGB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2976*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPAVGB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2977*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPAVGB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2978*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPAVGB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2979*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPAVGW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2980*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPAVGW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2981*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPAVGW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2982*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPAVGW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2983*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2984*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2985*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2986*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2987*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2988*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2989*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2990*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2991*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQD_XMMdq_XMMdq_MEMdq,2600,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2992*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQD_XMMdq_XMMdq_XMMdq,2603,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2993*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQD_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2994*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQD_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2995*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2996*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPEQQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2997*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2998*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPEQQ_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*2999*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3000*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3001*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3002*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3003*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3004*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3005*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3006*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3007*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3008*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3009*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3010*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3011*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_MEMdq,3631,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3012*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPGTQ_XMMdq_XMMdq_XMMdq,3634,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3013*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_MEMqq,3607,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3014*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPCMPGTQ_YMMqq_YMMqq_YMMqq,3610,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3015*/ XED_DEF_INST(XED_ICLASS_VPHADDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHADDW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3016*/ XED_DEF_INST(XED_ICLASS_VPHADDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHADDW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3017*/ XED_DEF_INST(XED_ICLASS_VPHADDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHADDW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3018*/ XED_DEF_INST(XED_ICLASS_VPHADDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHADDW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3019*/ XED_DEF_INST(XED_ICLASS_VPHADDD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHADDD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3020*/ XED_DEF_INST(XED_ICLASS_VPHADDD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHADDD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3021*/ XED_DEF_INST(XED_ICLASS_VPHADDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHADDD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3022*/ XED_DEF_INST(XED_ICLASS_VPHADDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHADDD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3023*/ XED_DEF_INST(XED_ICLASS_VPHADDSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHADDSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3024*/ XED_DEF_INST(XED_ICLASS_VPHADDSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHADDSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3025*/ XED_DEF_INST(XED_ICLASS_VPHADDSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHADDSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3026*/ XED_DEF_INST(XED_ICLASS_VPHADDSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHADDSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3027*/ XED_DEF_INST(XED_ICLASS_VPHSUBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHSUBW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3028*/ XED_DEF_INST(XED_ICLASS_VPHSUBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHSUBW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3029*/ XED_DEF_INST(XED_ICLASS_VPHSUBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHSUBW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3030*/ XED_DEF_INST(XED_ICLASS_VPHSUBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHSUBW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3031*/ XED_DEF_INST(XED_ICLASS_VPHSUBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHSUBD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3032*/ XED_DEF_INST(XED_ICLASS_VPHSUBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHSUBD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3033*/ XED_DEF_INST(XED_ICLASS_VPHSUBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHSUBD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3034*/ XED_DEF_INST(XED_ICLASS_VPHSUBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHSUBD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3035*/ XED_DEF_INST(XED_ICLASS_VPHSUBSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHSUBSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3036*/ XED_DEF_INST(XED_ICLASS_VPHSUBSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPHSUBSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3037*/ XED_DEF_INST(XED_ICLASS_VPHSUBSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHSUBSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3038*/ XED_DEF_INST(XED_ICLASS_VPHSUBSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPHSUBSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3039*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULHUW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3040*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULHUW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3041*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULHUW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3042*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULHUW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3043*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULHRSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3044*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULHRSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3045*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULHRSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3046*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULHRSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3047*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULHW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3048*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULHW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3049*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULHW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3050*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULHW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3051*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULLW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3052*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULLW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3053*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULLW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3054*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULLW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3055*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULLD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3056*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULLD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3057*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULLD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3058*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULLD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3059*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULUDQ_XMMdq_XMMdq_MEMdq,3637,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3060*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULUDQ_XMMdq_XMMdq_XMMdq,3640,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3061*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULUDQ_YMMqq_YMMqq_MEMqq,3643,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3062*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULUDQ_YMMqq_YMMqq_YMMqq,3646,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3063*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULDQ_XMMdq_XMMdq_MEMdq,3649,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3064*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMULDQ_XMMdq_XMMdq_XMMdq,3652,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3065*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULDQ_YMMqq_YMMqq_MEMqq,3655,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3066*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMULDQ_YMMqq_YMMqq_YMMqq,3658,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3067*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSADBW_XMMdq_XMMdq_MEMdq,3661,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3068*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSADBW_XMMdq_XMMdq_XMMdq,3664,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3069*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSADBW_YMMqq_YMMqq_MEMqq,3667,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3070*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSADBW_YMMqq_YMMqq_YMMqq,3670,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3071*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3072*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSHUFB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3073*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3074*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSHUFB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3075*/ XED_DEF_INST(XED_ICLASS_VPSIGNB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSIGNB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3076*/ XED_DEF_INST(XED_ICLASS_VPSIGNB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSIGNB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3077*/ XED_DEF_INST(XED_ICLASS_VPSIGNB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSIGNB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3078*/ XED_DEF_INST(XED_ICLASS_VPSIGNB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSIGNB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3079*/ XED_DEF_INST(XED_ICLASS_VPSIGNW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSIGNW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3080*/ XED_DEF_INST(XED_ICLASS_VPSIGNW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSIGNW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3081*/ XED_DEF_INST(XED_ICLASS_VPSIGNW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSIGNW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3082*/ XED_DEF_INST(XED_ICLASS_VPSIGNW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSIGNW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3083*/ XED_DEF_INST(XED_ICLASS_VPSIGND,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSIGND_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3084*/ XED_DEF_INST(XED_ICLASS_VPSIGND,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSIGND_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3085*/ XED_DEF_INST(XED_ICLASS_VPSIGND,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSIGND_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3086*/ XED_DEF_INST(XED_ICLASS_VPSIGND,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSIGND_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3087*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBSB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3088*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBSB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3089*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBSB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3090*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBSB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3091*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3092*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3093*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3094*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3095*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBUSB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3096*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBUSB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3097*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBUSB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3098*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBUSB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3099*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBUSW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3100*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBUSW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3101*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBUSW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3102*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBUSW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3103*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3104*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3105*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3106*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3107*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3108*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3109*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3110*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3111*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3112*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3113*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3114*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3115*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBQ_XMMdq_XMMdq_MEMdq,2810,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3116*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSUBQ_XMMdq_XMMdq_XMMdq,2813,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3117*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBQ_YMMqq_YMMqq_MEMqq,3607,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3118*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSUBQ_YMMqq_YMMqq_YMMqq,3610,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3119*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3120*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHBW_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3121*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3122*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHBW_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3123*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3124*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHWD_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3125*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3126*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHWD_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3127*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_MEMdq,2600,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3128*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHDQ_XMMdq_XMMdq_XMMdq,2603,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3129*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3130*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHDQ_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3131*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3132*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKHQDQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3133*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3134*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKHQDQ_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3135*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3136*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLBW_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3137*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3138*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLBW_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3139*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3140*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLWD_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3141*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3142*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLWD_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3143*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_MEMdq,2600,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3144*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLDQ_XMMdq_XMMdq_XMMdq,2603,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3145*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3146*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLDQ_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3147*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3148*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPUNPCKLQDQ_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3149*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3150*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPUNPCKLQDQ_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3151*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSRLDQ_XMMdq_XMMdq_IMMb,3673,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3152*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLDQ_YMMqq_YMMqq_IMMb,3676,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3153*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPSLLDQ_XMMdq_XMMdq_IMMb,3673,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3154*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLDQ_YMMqq_YMMqq_IMMb,3676,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3155*/ XED_DEF_INST(XED_ICLASS_VMOVLHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVLHPS_XMMdq_XMMq_XMMq,3679,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3156*/ XED_DEF_INST(XED_ICLASS_VMOVHLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVHLPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3157*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPALIGNR_XMMdq_XMMdq_MEMdq_IMMb,2664,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3158*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPALIGNR_XMMdq_XMMdq_XMMdq_IMMb,2668,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3159*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPALIGNR_YMMqq_YMMqq_MEMqq_IMMb,3682,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3160*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPALIGNR_YMMqq_YMMqq_YMMqq_IMMb,3686,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3161*/ XED_DEF_INST(XED_ICLASS_VPBLENDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPBLENDW_XMMdq_XMMdq_MEMdq_IMMb,2672,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3162*/ XED_DEF_INST(XED_ICLASS_VPBLENDW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPBLENDW_XMMdq_XMMdq_XMMdq_IMMb,2676,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3163*/ XED_DEF_INST(XED_ICLASS_VPBLENDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDW_YMMqq_YMMqq_MEMqq_IMMb,3690,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3164*/ XED_DEF_INST(XED_ICLASS_VPBLENDW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDW_YMMqq_YMMqq_YMMqq_IMMb,3694,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3165*/ XED_DEF_INST(XED_ICLASS_VROUNDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPD_XMMdq_MEMdq_IMMb,3271,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3166*/ XED_DEF_INST(XED_ICLASS_VROUNDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPD_XMMdq_XMMdq_IMMb,3274,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3167*/ XED_DEF_INST(XED_ICLASS_VROUNDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPD_YMMqq_MEMqq_IMMb,3277,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3168*/ XED_DEF_INST(XED_ICLASS_VROUNDPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPD_YMMqq_YMMqq_IMMb,3280,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3169*/ XED_DEF_INST(XED_ICLASS_VROUNDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPS_XMMdq_MEMdq_IMMb,3295,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3170*/ XED_DEF_INST(XED_ICLASS_VROUNDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPS_XMMdq_XMMdq_IMMb,3298,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3171*/ XED_DEF_INST(XED_ICLASS_VROUNDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPS_YMMqq_MEMqq_IMMb,3301,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3172*/ XED_DEF_INST(XED_ICLASS_VROUNDPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDPS_YMMqq_YMMqq_IMMb,3304,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3173*/ XED_DEF_INST(XED_ICLASS_VROUNDSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDSD_XMMdq_XMMdq_MEMq_IMMb,3119,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3174*/ XED_DEF_INST(XED_ICLASS_VROUNDSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDSD_XMMdq_XMMdq_XMMq_IMMb,3123,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3175*/ XED_DEF_INST(XED_ICLASS_VROUNDSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDSS_XMMdq_XMMdq_MEMd_IMMb,3127,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3176*/ XED_DEF_INST(XED_ICLASS_VROUNDSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VROUNDSS_XMMdq_XMMdq_XMMd_IMMb,3131,4,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3177*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPD_XMMdq_XMMdq_MEMdq_IMMb,3087,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3178*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPD_XMMdq_XMMdq_XMMdq_IMMb,3091,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3179*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPD_YMMqq_YMMqq_MEMqq_IMMb,3095,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3180*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPD_YMMqq_YMMqq_YMMqq_IMMb,3099,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3181*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPS_XMMdq_XMMdq_MEMdq_IMMb,3103,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3182*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPS_XMMdq_XMMdq_XMMdq_IMMb,3107,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3183*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPS_YMMqq_YMMqq_MEMqq_IMMb,3111,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3184*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSHUFPS_YMMqq_YMMqq_YMMqq_IMMb,3115,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3185*/ XED_DEF_INST(XED_ICLASS_VRCPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRCPPS_XMMdq_MEMdq,2696,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3186*/ XED_DEF_INST(XED_ICLASS_VRCPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRCPPS_XMMdq_XMMdq,2698,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3187*/ XED_DEF_INST(XED_ICLASS_VRCPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRCPPS_YMMqq_MEMqq,2700,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3188*/ XED_DEF_INST(XED_ICLASS_VRCPPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRCPPS_YMMqq_YMMqq,2702,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3189*/ XED_DEF_INST(XED_ICLASS_VRCPSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRCPSS_XMMdq_XMMdq_MEMd,3069,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3190*/ XED_DEF_INST(XED_ICLASS_VRCPSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRCPSS_XMMdq_XMMdq_XMMd,3072,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3191*/ XED_DEF_INST(XED_ICLASS_VRSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRSQRTPS_XMMdq_MEMdq,2696,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3192*/ XED_DEF_INST(XED_ICLASS_VRSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRSQRTPS_XMMdq_XMMdq,2698,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3193*/ XED_DEF_INST(XED_ICLASS_VRSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRSQRTPS_YMMqq_MEMqq,2700,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3194*/ XED_DEF_INST(XED_ICLASS_VRSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRSQRTPS_YMMqq_YMMqq,2702,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3195*/ XED_DEF_INST(XED_ICLASS_VRSQRTSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRSQRTSS_XMMdq_XMMdq_MEMd,3069,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3196*/ XED_DEF_INST(XED_ICLASS_VRSQRTSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VRSQRTSS_XMMdq_XMMdq_XMMd,3072,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3197*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPD_XMMdq_MEMdq,2704,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3198*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPD_XMMdq_XMMdq,2706,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3199*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPD_YMMqq_MEMqq,2708,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3200*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPD_YMMqq_YMMqq,2710,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3201*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPS_XMMdq_MEMdq,2696,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3202*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPS_XMMdq_XMMdq,2698,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3203*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPS_YMMqq_MEMqq,2700,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3204*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTPS_YMMqq_YMMqq,2702,2,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3205*/ XED_DEF_INST(XED_ICLASS_VSQRTSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3206*/ XED_DEF_INST(XED_ICLASS_VSQRTSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3207*/ XED_DEF_INST(XED_ICLASS_VSQRTSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3208*/ XED_DEF_INST(XED_ICLASS_VSQRTSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSQRTSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3209*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3210*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3211*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3212*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3213*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3214*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3215*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3216*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKHPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3217*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3218*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3219*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3220*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3221*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3222*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3223*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3224*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3225*/ XED_DEF_INST(XED_ICLASS_VSUBSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3226*/ XED_DEF_INST(XED_ICLASS_VSUBSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3227*/ XED_DEF_INST(XED_ICLASS_VSUBSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3228*/ XED_DEF_INST(XED_ICLASS_VSUBSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSUBSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3229*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3230*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3231*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3232*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3233*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3234*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3235*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3236*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3237*/ XED_DEF_INST(XED_ICLASS_VMULSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULSD_XMMdq_XMMdq_MEMq,3063,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3238*/ XED_DEF_INST(XED_ICLASS_VMULSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULSD_XMMdq_XMMdq_XMMq,3066,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3239*/ XED_DEF_INST(XED_ICLASS_VMULSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULSS_XMMdq_XMMdq_MEMd,3069,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3240*/ XED_DEF_INST(XED_ICLASS_VMULSS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMULSS_XMMdq_XMMdq_XMMd,3072,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3241*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPD_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3242*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPD_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3243*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPD_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3244*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPD_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3245*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPS_XMMdq_XMMdq_MEMdq,2600,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3246*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPS_XMMdq_XMMdq_XMMdq,2603,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3247*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPS_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3248*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VORPS_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3249*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXSB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3250*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXSB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3251*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXSB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3252*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXSB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3253*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3254*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3255*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3256*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3257*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXSD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3258*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXSD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3259*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXSD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3260*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXSD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3261*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXUB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3262*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXUB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3263*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXUB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3264*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXUB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3265*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXUW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3266*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXUW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3267*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXUW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3268*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXUW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3269*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXUD_XMMdq_XMMdq_MEMdq,2600,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3270*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMAXUD_XMMdq_XMMdq_XMMdq,2603,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3271*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXUD_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3272*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMAXUD_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3273*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINSB_XMMdq_XMMdq_MEMdq,2774,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3274*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINSB_XMMdq_XMMdq_XMMdq,2777,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3275*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINSB_YMMqq_YMMqq_MEMqq,3595,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3276*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINSB_YMMqq_YMMqq_YMMqq,3598,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3277*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINSW_XMMdq_XMMdq_MEMdq,2786,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3278*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINSW_XMMdq_XMMdq_XMMdq,2789,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3279*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINSW_YMMqq_YMMqq_MEMqq,3601,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3280*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINSW_YMMqq_YMMqq_YMMqq,3604,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3281*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINSD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3282*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINSD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3283*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINSD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3284*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINSD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3285*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINUB_XMMdq_XMMdq_MEMdq,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3286*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINUB_XMMdq_XMMdq_XMMdq,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3287*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINUB_YMMqq_YMMqq_MEMqq,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3288*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINUB_YMMqq_YMMqq_YMMqq,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3289*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINUW_XMMdq_XMMdq_MEMdq,2588,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3290*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINUW_XMMdq_XMMdq_XMMdq,2591,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3291*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINUW_YMMqq_YMMqq_MEMqq,3619,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3292*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINUW_YMMqq_YMMqq_YMMqq,3622,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3293*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINUD_XMMdq_XMMdq_MEMdq,2600,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3294*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMINUD_XMMdq_XMMdq_XMMdq,2603,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3295*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINUD_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3296*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMINUD_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3297*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMADDWD_XMMdq_XMMdq_MEMdq,3698,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3298*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMADDWD_XMMdq_XMMdq_XMMdq,3701,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3299*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMADDWD_YMMqq_YMMqq_MEMqq,3704,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3300*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMADDWD_YMMqq_YMMqq_YMMqq,3707,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3301*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_MEMdq,3710,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3302*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMADDUBSW_XMMdq_XMMdq_XMMdq,3713,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3303*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_MEMqq,3716,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3304*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMADDUBSW_YMMqq_YMMqq_YMMqq,3719,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3305*/ XED_DEF_INST(XED_ICLASS_VMPSADBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMPSADBW_XMMdq_XMMdq_MEMdq_IMMb,3722,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3306*/ XED_DEF_INST(XED_ICLASS_VMPSADBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMPSADBW_XMMdq_XMMdq_XMMdq_IMMb,3726,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3307*/ XED_DEF_INST(XED_ICLASS_VMPSADBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VMPSADBW_YMMqq_YMMqq_MEMqq_IMMb,3730,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3308*/ XED_DEF_INST(XED_ICLASS_VMPSADBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VMPSADBW_YMMqq_YMMqq_YMMqq_IMMb,3734,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3309*/ XED_DEF_INST(XED_ICLASS_VUCOMISD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUCOMISD_XMMdq_MEMq,3738,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3310*/ XED_DEF_INST(XED_ICLASS_VUCOMISD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUCOMISD_XMMdq_XMMq,3741,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3311*/ XED_DEF_INST(XED_ICLASS_VUCOMISS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUCOMISS_XMMdq_MEMd,3744,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3312*/ XED_DEF_INST(XED_ICLASS_VUCOMISS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUCOMISS_XMMdq_XMMd,3747,3,91,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3313*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_MEMdq,3039,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3314*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPD_XMMdq_XMMdq_XMMdq,3042,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3315*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_MEMqq,3045,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3316*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPD_YMMqq_YMMqq_YMMqq,3048,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3317*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_MEMdq,3051,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3318*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPS_XMMdq_XMMdq_XMMdq,3054,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3319*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3320*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VUNPCKLPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3321*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPD_XMMdq_XMMdq_MEMdq,2618,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3322*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPD_XMMdq_XMMdq_XMMdq,2621,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3323*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPD_YMMqq_YMMqq_MEMqq,3075,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3324*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPD_YMMqq_YMMqq_YMMqq,3078,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3325*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPS_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3326*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPS_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3327*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPS_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3328*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX,3,XED_IFORM_VXORPS_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3329*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSS_XMMdq_MEMd,2712,2,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3330*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_10,3072,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3331*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSS_MEMd_XMMd,3750,2,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3332*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSS_XMMdq_XMMdq_XMMd_11,3752,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3333*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSD_XMMdq_MEMq,2716,2,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3334*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_10,3066,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3335*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSD_MEMq_XMMq,3755,2,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3336*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVSD_XMMdq_XMMdq_XMMq_11,3757,3,0,0,80,XED_EXCEPTION_AVX_TYPE_5), +/*3337*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_XMMdq_MEMdq,2704,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3338*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_XMMdq_XMMdq_10,2706,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3339*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_MEMdq_XMMdq,3381,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3340*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_XMMdq_XMMdq_11,3383,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3341*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_YMMqq_MEMqq,2708,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3342*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_YMMqq_YMMqq_10,2710,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3343*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_MEMqq_YMMqq,3385,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3344*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPD_YMMqq_YMMqq_11,3387,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3345*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_XMMdq_MEMdq,2696,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3346*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_XMMdq_XMMdq_10,2698,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3347*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_MEMdq_XMMdq,3389,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3348*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_XMMdq_XMMdq_11,3391,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3349*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_YMMqq_MEMqq,2700,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3350*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_YMMqq_YMMqq_10,2702,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3351*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_MEMqq_YMMqq,3393,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3352*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVUPS_YMMqq_YMMqq_11,3395,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4M), +/*3353*/ XED_DEF_INST(XED_ICLASS_VMOVLPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVLPD_XMMdq_XMMdq_MEMq,3063,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3354*/ XED_DEF_INST(XED_ICLASS_VMOVLPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVLPD_MEMq_XMMq,3755,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3355*/ XED_DEF_INST(XED_ICLASS_VMOVLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVLPS_XMMdq_XMMdq_MEMq,3760,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3356*/ XED_DEF_INST(XED_ICLASS_VMOVLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVLPS_MEMq_XMMq,882,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3357*/ XED_DEF_INST(XED_ICLASS_VMOVHPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVHPD_XMMdq_XMMq_MEMq,3763,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3358*/ XED_DEF_INST(XED_ICLASS_VMOVHPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVHPD_MEMq_XMMdq,3766,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3359*/ XED_DEF_INST(XED_ICLASS_VMOVHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVHPS_XMMdq_XMMq_MEMq,3768,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3360*/ XED_DEF_INST(XED_ICLASS_VMOVHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVHPS_MEMq_XMMdq,3771,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3361*/ XED_DEF_INST(XED_ICLASS_VMOVMSKPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVMSKPD_GPR32d_XMMdq,3773,2,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3362*/ XED_DEF_INST(XED_ICLASS_VMOVMSKPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVMSKPD_GPR32d_YMMqq,3775,2,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3363*/ XED_DEF_INST(XED_ICLASS_VMOVMSKPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVMSKPS_GPR32d_XMMdq,3777,2,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3364*/ XED_DEF_INST(XED_ICLASS_VMOVMSKPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVMSKPS_GPR32d_YMMqq,3779,2,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3365*/ XED_DEF_INST(XED_ICLASS_VPMOVMSKB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVMSKB_GPR32d_XMMdq,3781,2,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3366*/ XED_DEF_INST(XED_ICLASS_VPMOVMSKB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVMSKB_GPR32d_YMMqq,3783,2,0,0,0,XED_EXCEPTION_AVX_TYPE_7), +/*3367*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXBW_XMMdq_XMMq,2049,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3368*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXBW_XMMdq_MEMq,2047,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3369*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXBW_YMMqq_XMMdq,3785,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3370*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXBW_YMMqq_MEMdq,3787,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3371*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXBD_XMMdq_XMMd,2053,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3372*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXBD_XMMdq_MEMd,2051,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3373*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXBD_YMMqq_XMMq,3789,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3374*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXBD_YMMqq_MEMq,3791,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3375*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXBQ_XMMdq_XMMw,2057,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3376*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXBQ_XMMdq_MEMw,2055,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3377*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXBQ_YMMqq_XMMd,3793,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3378*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXBQ_YMMqq_MEMd,3795,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3379*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXWD_XMMdq_XMMq,2061,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3380*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXWD_XMMdq_MEMq,2059,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3381*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXWD_YMMqq_XMMdq,3797,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3382*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXWD_YMMqq_MEMdq,3799,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3383*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXWQ_XMMdq_XMMd,2065,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3384*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXWQ_XMMdq_MEMd,2063,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3385*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXWQ_YMMqq_XMMq,3801,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3386*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXWQ_YMMqq_MEMq,3803,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3387*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXDQ_XMMdq_XMMq,2069,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3388*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVSXDQ_XMMdq_MEMq,2067,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3389*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXDQ_YMMqq_XMMdq,3805,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3390*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVSXDQ_YMMqq_MEMdq,3807,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3391*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXBW_XMMdq_XMMq,2073,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3392*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXBW_XMMdq_MEMq,2071,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3393*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXBW_YMMqq_XMMdq,3809,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3394*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXBW_YMMqq_MEMdq,3811,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3395*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXBD_XMMdq_XMMd,2077,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3396*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXBD_XMMdq_MEMd,2075,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3397*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXBD_YMMqq_XMMq,3813,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3398*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXBD_YMMqq_MEMq,3815,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3399*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXBQ_XMMdq_XMMw,2081,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3400*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXBQ_XMMdq_MEMw,2079,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3401*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXBQ_YMMqq_XMMd,3817,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3402*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXBQ_YMMqq_MEMd,3819,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3403*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXWD_XMMdq_XMMq,2085,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3404*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXWD_XMMdq_MEMq,2083,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3405*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXWD_YMMqq_XMMdq,3821,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3406*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXWD_YMMqq_MEMdq,3823,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3407*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXWQ_XMMdq_XMMd,2089,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3408*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXWQ_XMMdq_MEMd,2087,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3409*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXWQ_YMMqq_XMMq,3825,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3410*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXWQ_YMMqq_MEMq,3827,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3411*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXDQ_XMMdq_XMMq,2093,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3412*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPMOVZXDQ_XMMdq_MEMq,2091,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3413*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXDQ_YMMqq_XMMdq,3829,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3414*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMOVZXDQ_YMMqq_MEMdq,3831,2,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3415*/ XED_DEF_INST(XED_ICLASS_VPEXTRB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRB_MEMb_XMMdq_IMMb,3833,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3416*/ XED_DEF_INST(XED_ICLASS_VPEXTRB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRB_GPR32d_XMMdq_IMMb,3836,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3417*/ XED_DEF_INST(XED_ICLASS_VPEXTRW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRW_MEMw_XMMdq_IMMb,3839,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3418*/ XED_DEF_INST(XED_ICLASS_VPEXTRW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_15,3842,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3419*/ XED_DEF_INST(XED_ICLASS_VPEXTRW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRW_GPR32d_XMMdq_IMMb_C5,3845,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3420*/ XED_DEF_INST(XED_ICLASS_VPEXTRQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRQ_MEMq_XMMdq_IMMb,3848,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3421*/ XED_DEF_INST(XED_ICLASS_VPEXTRQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRQ_GPR64q_XMMdq_IMMb,3851,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3422*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb,3854,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3423*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb,3857,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3424*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRD_MEMd_XMMdq_IMMb,3854,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3425*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPEXTRD_GPR32d_XMMdq_IMMb,3857,3,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3426*/ XED_DEF_INST(XED_ICLASS_VPINSRB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRB_XMMdq_XMMdq_MEMb_IMMb,3860,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3427*/ XED_DEF_INST(XED_ICLASS_VPINSRB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRB_XMMdq_XMMdq_GPR32d_IMMb,3864,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3428*/ XED_DEF_INST(XED_ICLASS_VPINSRW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRW_XMMdq_XMMdq_MEMw_IMMb,3868,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3429*/ XED_DEF_INST(XED_ICLASS_VPINSRW,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRW_XMMdq_XMMdq_GPR32d_IMMb,3872,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3430*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb,3876,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3431*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb,3880,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3432*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRD_XMMdq_XMMdq_MEMd_IMMb,3876,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3433*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRD_XMMdq_XMMdq_GPR32d_IMMb,3880,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3434*/ XED_DEF_INST(XED_ICLASS_VPINSRQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRQ_XMMdq_XMMdq_MEMq_IMMb,3884,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3435*/ XED_DEF_INST(XED_ICLASS_VPINSRQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPINSRQ_XMMdq_XMMdq_GPR64q_IMMb,3888,4,0,0,0,XED_EXCEPTION_AVX_TYPE_5), +/*3436*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb,2095,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3437*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb,2102,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3438*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRI_XMMdq_MEMdq_IMMb,2095,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3439*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRI_XMMdq_XMMdq_IMMb,2102,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3440*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRI64,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRI64_XMMdq_MEMdq_IMMb,2109,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3441*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRI64,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRI64_XMMdq_XMMdq_IMMb,2116,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3442*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb,2123,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3443*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb,2128,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3444*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRI_XMMdq_MEMdq_IMMb,2123,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3445*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRI,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRI_XMMdq_XMMdq_IMMb,2128,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3446*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRI64,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRI64_XMMdq_MEMdq_IMMb,2133,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3447*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRI64,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRI64_XMMdq_XMMdq_IMMb,2138,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3448*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRM,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb,2143,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3449*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRM,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb,2150,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3450*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRM,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRM_XMMdq_MEMdq_IMMb,2143,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3451*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRM,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRM_XMMdq_XMMdq_IMMb,2150,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3452*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRM64,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRM64_XMMdq_MEMdq_IMMb,2157,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3453*/ XED_DEF_INST(XED_ICLASS_VPCMPESTRM64,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPESTRM64_XMMdq_XMMdq_IMMb,2164,7,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3454*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRM,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRM_XMMdq_MEMdq_IMMb,2171,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3455*/ XED_DEF_INST(XED_ICLASS_VPCMPISTRM,XED_CATEGORY_STTNI,XED_EXTENSION_AVX,3,XED_IFORM_VPCMPISTRM_XMMdq_XMMdq_IMMb,2176,5,71,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3456*/ XED_DEF_INST(XED_ICLASS_VMASKMOVDQU,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VMASKMOVDQU_XMMdq_XMMdq,3892,4,0,0,92,XED_EXCEPTION_AVX_TYPE_4), +/*3457*/ XED_DEF_INST(XED_ICLASS_VLDMXCSR,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VLDMXCSR_MEMd,834,2,0,0,47,XED_EXCEPTION_AVX_TYPE_5L), +/*3458*/ XED_DEF_INST(XED_ICLASS_VSTMXCSR,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VSTMXCSR_MEMd,836,2,0,0,48,XED_EXCEPTION_AVX_TYPE_5), +/*3459*/ XED_DEF_INST(XED_ICLASS_VPBLENDVB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPBLENDVB_XMMdq_XMMdq_MEMdq_XMMdq,3896,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3460*/ XED_DEF_INST(XED_ICLASS_VPBLENDVB,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPBLENDVB_XMMdq_XMMdq_XMMdq_XMMdq,3900,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3461*/ XED_DEF_INST(XED_ICLASS_VPBLENDVB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDVB_YMMqq_YMMqq_MEMqq_YMMqq,3904,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3462*/ XED_DEF_INST(XED_ICLASS_VPBLENDVB,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDVB_YMMqq_YMMqq_YMMqq_YMMqq,3908,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3463*/ XED_DEF_INST(XED_ICLASS_VBLENDVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPD_XMMdq_XMMdq_MEMdq_XMMdq,3912,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3464*/ XED_DEF_INST(XED_ICLASS_VBLENDVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPD_XMMdq_XMMdq_XMMdq_XMMdq,3916,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3465*/ XED_DEF_INST(XED_ICLASS_VBLENDVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPD_YMMqq_YMMqq_MEMqq_YMMqq,3920,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3466*/ XED_DEF_INST(XED_ICLASS_VBLENDVPD,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPD_YMMqq_YMMqq_YMMqq_YMMqq,3924,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3467*/ XED_DEF_INST(XED_ICLASS_VBLENDVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPS_XMMdq_XMMdq_MEMdq_XMMdq,3928,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3468*/ XED_DEF_INST(XED_ICLASS_VBLENDVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPS_XMMdq_XMMdq_XMMdq_XMMdq,3932,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3469*/ XED_DEF_INST(XED_ICLASS_VBLENDVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPS_YMMqq_YMMqq_MEMqq_YMMqq,3936,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3470*/ XED_DEF_INST(XED_ICLASS_VBLENDVPS,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VBLENDVPS_YMMqq_YMMqq_YMMqq_YMMqq,3940,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3471*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTDQA_XMMdq_MEMdq,1864,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3472*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX2,3,XED_IFORM_VMOVNTDQA_YMMqq_MEMqq,3325,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3473*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTDQ_MEMdq_XMMdq,1708,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3474*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTDQ_MEMqq_YMMqq,3407,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3475*/ XED_DEF_INST(XED_ICLASS_VMOVNTPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTPD_MEMdq_XMMdq,3381,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3476*/ XED_DEF_INST(XED_ICLASS_VMOVNTPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTPD_MEMqq_YMMqq,3385,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3477*/ XED_DEF_INST(XED_ICLASS_VMOVNTPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTPS_MEMdq_XMMdq,3389,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3478*/ XED_DEF_INST(XED_ICLASS_VMOVNTPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX,3,XED_IFORM_VMOVNTPS_MEMqq_YMMqq,3393,2,0,0,90,XED_EXCEPTION_AVX_TYPE_1), +/*3479*/ XED_DEF_INST(XED_ICLASS_VAESKEYGENASSIST,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESKEYGENASSIST_XMMdq_XMMdq_IMMb,2199,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3480*/ XED_DEF_INST(XED_ICLASS_VAESKEYGENASSIST,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESKEYGENASSIST_XMMdq_MEMdq_IMMb,2202,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3481*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESENC_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3482*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESENC_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3483*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128,3944,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3484*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128,3947,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3485*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESENCLAST_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3486*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESENCLAST_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3487*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128,3944,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3488*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128,3947,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3489*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESDEC_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3490*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESDEC_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3491*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128,3944,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3492*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128,3947,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3493*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESDECLAST_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3494*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESDECLAST_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3495*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128,3944,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3496*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_VAES,3,XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128,3947,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3497*/ XED_DEF_INST(XED_ICLASS_VAESIMC,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESIMC_XMMdq_XMMdq,1866,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3498*/ XED_DEF_INST(XED_ICLASS_VAESIMC,XED_CATEGORY_AES,XED_EXTENSION_AVXAES,3,XED_IFORM_VAESIMC_XMMdq_MEMdq,1864,2,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3499*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_XMMdq_IMMb,3950,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3500*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_AVX,XED_EXTENSION_AVX,3,XED_IFORM_VPCLMULQDQ_XMMdq_XMMdq_MEMdq_IMMb,3954,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3501*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_VPCLMULQDQ,3,XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8,3958,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3502*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_VPCLMULQDQ,3,XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8,3962,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3503*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPH2PS_XMMdq_MEMq,3966,2,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3504*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPH2PS_XMMdq_XMMq,3968,2,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3505*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPH2PS_YMMqq_MEMdq,3970,2,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3506*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPH2PS_YMMqq_XMMdq,3972,2,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3507*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPS2PH_MEMq_XMMdq_IMMb,3974,3,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3508*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPS2PH_XMMq_XMMdq_IMMb,3977,3,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3509*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPS2PH_MEMdq_YMMqq_IMMb,3980,3,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3510*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_F16C,3,XED_IFORM_VCVTPS2PH_XMMdq_YMMqq_IMMb,3983,3,0,0,47,XED_EXCEPTION_AVX_TYPE_11), +/*3511*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3512*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3513*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3514*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3515*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3516*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3517*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3518*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3519*/ XED_DEF_INST(XED_ICLASS_VFMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3520*/ XED_DEF_INST(XED_ICLASS_VFMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3521*/ XED_DEF_INST(XED_ICLASS_VFMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3522*/ XED_DEF_INST(XED_ICLASS_VFMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD132SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3523*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3524*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3525*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3526*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3527*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3528*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3529*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3530*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3531*/ XED_DEF_INST(XED_ICLASS_VFMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3532*/ XED_DEF_INST(XED_ICLASS_VFMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3533*/ XED_DEF_INST(XED_ICLASS_VFMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3534*/ XED_DEF_INST(XED_ICLASS_VFMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD213SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3535*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3536*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3537*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3538*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3539*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3540*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3541*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3542*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3543*/ XED_DEF_INST(XED_ICLASS_VFMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3544*/ XED_DEF_INST(XED_ICLASS_VFMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3545*/ XED_DEF_INST(XED_ICLASS_VFMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3546*/ XED_DEF_INST(XED_ICLASS_VFMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADD231SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3547*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3548*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3549*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3550*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3551*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3552*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3553*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3554*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3555*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3556*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3557*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3558*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3559*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3560*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3561*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3562*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB132PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3563*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3564*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3565*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3566*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB213PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3567*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3568*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3569*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3570*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMADDSUB231PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3571*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3572*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3573*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3574*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3575*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3576*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3577*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3578*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3579*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3580*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3581*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3582*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3583*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3584*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3585*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3586*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD132PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3587*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3588*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3589*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3590*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD213PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3591*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3592*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3593*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3594*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUBADD231PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3595*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3596*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3597*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3598*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3599*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3600*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3601*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3602*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3603*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3604*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3605*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3606*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB132SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3607*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3608*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3609*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3610*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3611*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3612*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3613*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3614*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3615*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3616*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3617*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3618*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB213SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3619*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3620*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3621*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3622*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3623*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3624*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3625*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3626*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3627*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3628*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3629*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3630*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFMSUB231SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3631*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3632*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3633*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3634*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3635*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3636*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3637*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3638*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3639*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3640*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3641*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3642*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD132SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3643*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3644*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3645*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3646*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3647*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3648*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3649*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3650*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3651*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3652*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3653*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3654*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD213SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3655*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3656*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3657*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3658*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3659*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3660*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3661*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3662*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3663*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3664*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3665*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3666*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMADD231SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3667*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3668*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3669*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3670*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3671*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3672*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3673*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3674*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3675*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3676*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3677*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3678*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB132SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3679*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3680*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3681*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3682*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3683*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3684*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3685*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3686*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3687*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3688*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3689*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3690*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB213SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3691*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_MEMdq,3986,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3692*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PD_XMMdq_XMMdq_XMMdq,3989,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3693*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_MEMqq,3992,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3694*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PD_YMMqq_YMMqq_YMMqq,3995,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3695*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_MEMdq,3998,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3696*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PS_XMMdq_XMMdq_XMMdq,4001,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3697*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_MEMqq,4004,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3698*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231PS_YMMqq_YMMqq_YMMqq,4007,3,0,0,47,XED_EXCEPTION_AVX_TYPE_2), +/*3699*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_MEMq,4010,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3700*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231SD_XMMdq_XMMq_XMMq,4013,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3701*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_MEMd,4016,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3702*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_FMA,3,XED_IFORM_VFNMSUB231SS_XMMdq_XMMd_XMMd,4019,3,0,0,83,XED_EXCEPTION_AVX_TYPE_3), +/*3703*/ XED_DEF_INST(XED_ICLASS_VGATHERDPD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERDPD_YMMf64_MEMf64_YMMi64_VL256,4022,3,0,0,122,XED_EXCEPTION_AVX_TYPE_12), +/*3704*/ XED_DEF_INST(XED_ICLASS_VGATHERDPD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERDPD_XMMf64_MEMf64_XMMi64_VL128,4025,3,0,0,122,XED_EXCEPTION_AVX_TYPE_12), +/*3705*/ XED_DEF_INST(XED_ICLASS_VGATHERDPS,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERDPS_YMMf32_MEMf32_YMMi32_VL256,4028,3,0,0,123,XED_EXCEPTION_AVX_TYPE_12), +/*3706*/ XED_DEF_INST(XED_ICLASS_VGATHERDPS,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERDPS_XMMf32_MEMf32_XMMi32_VL128,4031,3,0,0,123,XED_EXCEPTION_AVX_TYPE_12), +/*3707*/ XED_DEF_INST(XED_ICLASS_VGATHERQPD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERQPD_YMMf64_MEMf64_YMMi64_VL256,4022,3,0,0,124,XED_EXCEPTION_AVX_TYPE_12), +/*3708*/ XED_DEF_INST(XED_ICLASS_VGATHERQPD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERQPD_XMMf64_MEMf64_XMMi64_VL128,4025,3,0,0,124,XED_EXCEPTION_AVX_TYPE_12), +/*3709*/ XED_DEF_INST(XED_ICLASS_VGATHERQPS,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL256,4031,3,0,0,125,XED_EXCEPTION_AVX_TYPE_12), +/*3710*/ XED_DEF_INST(XED_ICLASS_VGATHERQPS,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VGATHERQPS_XMMf32_MEMf32_XMMi32_VL128,4034,3,0,0,125,XED_EXCEPTION_AVX_TYPE_12), +/*3711*/ XED_DEF_INST(XED_ICLASS_VPGATHERDQ,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256,4037,3,0,0,122,XED_EXCEPTION_AVX_TYPE_12), +/*3712*/ XED_DEF_INST(XED_ICLASS_VPGATHERDQ,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128,4040,3,0,0,122,XED_EXCEPTION_AVX_TYPE_12), +/*3713*/ XED_DEF_INST(XED_ICLASS_VPGATHERDD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERDD_YMMu32_MEMd_YMMi32_VL256,4043,3,0,0,123,XED_EXCEPTION_AVX_TYPE_12), +/*3714*/ XED_DEF_INST(XED_ICLASS_VPGATHERDD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERDD_XMMu32_MEMd_XMMi32_VL128,4046,3,0,0,123,XED_EXCEPTION_AVX_TYPE_12), +/*3715*/ XED_DEF_INST(XED_ICLASS_VPGATHERQQ,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERQQ_YMMu64_MEMq_YMMi64_VL256,4037,3,0,0,124,XED_EXCEPTION_AVX_TYPE_12), +/*3716*/ XED_DEF_INST(XED_ICLASS_VPGATHERQQ,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERQQ_XMMu64_MEMq_XMMi64_VL128,4040,3,0,0,124,XED_EXCEPTION_AVX_TYPE_12), +/*3717*/ XED_DEF_INST(XED_ICLASS_VPGATHERQD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL256,4046,3,0,0,125,XED_EXCEPTION_AVX_TYPE_12), +/*3718*/ XED_DEF_INST(XED_ICLASS_VPGATHERQD,XED_CATEGORY_AVX2GATHER,XED_EXTENSION_AVX2GATHER,3,XED_IFORM_VPGATHERQD_XMMu32_MEMd_XMMi32_VL128,4049,3,0,0,125,XED_EXCEPTION_AVX_TYPE_12), +/*3719*/ XED_DEF_INST(XED_ICLASS_VINSERTI128,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VINSERTI128_YMMqq_YMMqq_MEMdq_IMMb,4052,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3720*/ XED_DEF_INST(XED_ICLASS_VINSERTI128,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VINSERTI128_YMMqq_YMMqq_XMMdq_IMMb,4056,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3721*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI128,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VEXTRACTI128_MEMdq_YMMqq_IMMb,4060,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3722*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI128,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VEXTRACTI128_XMMdq_YMMqq_IMMb,4063,3,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3723*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVD_XMMdq_XMMdq_MEMdq,2600,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3724*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVD_YMMqq_YMMqq_MEMqq,3625,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3725*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVD_MEMdq_XMMdq_XMMdq,4066,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3726*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVD_MEMqq_YMMqq_YMMqq,4069,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3727*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVQ_XMMdq_XMMdq_MEMdq,2618,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3728*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVQ_YMMqq_YMMqq_MEMqq,3075,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3729*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVQ_MEMdq_XMMdq_XMMdq,4072,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3730*/ XED_DEF_INST(XED_ICLASS_VPMASKMOVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPMASKMOVQ_MEMqq_YMMqq_YMMqq,4075,3,0,0,121,XED_EXCEPTION_AVX_TYPE_6), +/*3731*/ XED_DEF_INST(XED_ICLASS_VPERM2I128,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERM2I128_YMMqq_YMMqq_MEMqq_IMMb,4078,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3732*/ XED_DEF_INST(XED_ICLASS_VPERM2I128,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERM2I128_YMMqq_YMMqq_YMMqq_IMMb,4082,4,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3733*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMQ_YMMqq_MEMqq_IMMb,4086,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3734*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMQ_YMMqq_YMMqq_IMMb,4089,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3735*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMPD_YMMqq_MEMqq_IMMb,3277,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3736*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMPD_YMMqq_YMMqq_IMMb,3280,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3737*/ XED_DEF_INST(XED_ICLASS_VPERMD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMD_YMMqq_YMMqq_MEMqq,3625,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3738*/ XED_DEF_INST(XED_ICLASS_VPERMD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMD_YMMqq_YMMqq_YMMqq,3628,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3739*/ XED_DEF_INST(XED_ICLASS_VPERMPS,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMPS_YMMqq_YMMqq_MEMqq,3057,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3740*/ XED_DEF_INST(XED_ICLASS_VPERMPS,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPERMPS_YMMqq_YMMqq_YMMqq,3060,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3741*/ XED_DEF_INST(XED_ICLASS_VPBLENDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDD_XMMdq_XMMdq_MEMdq_IMMb,2680,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3742*/ XED_DEF_INST(XED_ICLASS_VPBLENDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDD_XMMdq_XMMdq_XMMdq_IMMb,2684,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3743*/ XED_DEF_INST(XED_ICLASS_VPBLENDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDD_YMMqq_YMMqq_MEMqq_IMMb,4092,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3744*/ XED_DEF_INST(XED_ICLASS_VPBLENDD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPBLENDD_YMMqq_YMMqq_YMMqq_IMMb,4096,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3745*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTB_XMMdq_MEMb,4100,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3746*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTB_XMMdq_XMMb,4102,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3747*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTB_YMMqq_MEMb,4104,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3748*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTB_YMMqq_XMMb,4106,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3749*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTW_XMMdq_MEMw,4108,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3750*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTW_XMMdq_XMMw,4110,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3751*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTW_YMMqq_MEMw,4112,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3752*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTW_YMMqq_XMMw,4114,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3753*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTD_XMMdq_MEMd,4116,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3754*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTD_XMMdq_XMMd,4118,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3755*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTD_YMMqq_MEMd,4120,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3756*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTD_YMMqq_XMMd,4122,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3757*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTQ_XMMdq_MEMq,4124,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3758*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTQ_XMMdq_XMMq,4126,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3759*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTQ_YMMqq_MEMq,4128,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3760*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VPBROADCASTQ_YMMqq_XMMq,4130,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3761*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI128,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX2,3,XED_IFORM_VBROADCASTI128_YMMqq_MEMdq,4132,2,0,0,0,XED_EXCEPTION_AVX_TYPE_6), +/*3762*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3763*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3764*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3765*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3766*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVQ_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3767*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVQ_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3768*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVQ_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3769*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSLLVQ_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3770*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3771*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3772*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3773*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3774*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVQ_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3775*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVQ_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3776*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVQ_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3777*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRLVQ_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3778*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAVD_XMMdq_XMMdq_MEMdq,2798,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3779*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAVD_XMMdq_XMMdq_XMMdq,2801,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3780*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAVD_YMMqq_YMMqq_MEMqq,3081,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3781*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX2,XED_EXTENSION_AVX2,3,XED_IFORM_VPSRAVD_YMMqq_YMMqq_YMMqq,3084,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3782*/ XED_DEF_INST(XED_ICLASS_PDEP,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd,4134,3,0,0,0,XED_EXCEPTION_INVALID), +/*3783*/ XED_DEF_INST(XED_ICLASS_PDEP,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PDEP_VGPR32d_VGPR32d_MEMd,4134,3,0,0,0,XED_EXCEPTION_INVALID), +/*3784*/ XED_DEF_INST(XED_ICLASS_PDEP,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d,4137,3,0,0,0,XED_EXCEPTION_INVALID), +/*3785*/ XED_DEF_INST(XED_ICLASS_PDEP,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PDEP_VGPR32d_VGPR32d_VGPR32d,4137,3,0,0,0,XED_EXCEPTION_INVALID), +/*3786*/ XED_DEF_INST(XED_ICLASS_PDEP,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PDEP_VGPR64q_VGPR64q_MEMq,4140,3,0,0,0,XED_EXCEPTION_INVALID), +/*3787*/ XED_DEF_INST(XED_ICLASS_PDEP,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PDEP_VGPR64q_VGPR64q_VGPR64q,4143,3,0,0,0,XED_EXCEPTION_INVALID), +/*3788*/ XED_DEF_INST(XED_ICLASS_PEXT,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd,4134,3,0,0,0,XED_EXCEPTION_INVALID), +/*3789*/ XED_DEF_INST(XED_ICLASS_PEXT,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PEXT_VGPR32d_VGPR32d_MEMd,4134,3,0,0,0,XED_EXCEPTION_INVALID), +/*3790*/ XED_DEF_INST(XED_ICLASS_PEXT,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d,4137,3,0,0,0,XED_EXCEPTION_INVALID), +/*3791*/ XED_DEF_INST(XED_ICLASS_PEXT,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PEXT_VGPR32d_VGPR32d_VGPR32d,4137,3,0,0,0,XED_EXCEPTION_INVALID), +/*3792*/ XED_DEF_INST(XED_ICLASS_PEXT,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PEXT_VGPR64q_VGPR64q_MEMq,4140,3,0,0,0,XED_EXCEPTION_INVALID), +/*3793*/ XED_DEF_INST(XED_ICLASS_PEXT,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_PEXT_VGPR64q_VGPR64q_VGPR64q,4143,3,0,0,0,XED_EXCEPTION_INVALID), +/*3794*/ XED_DEF_INST(XED_ICLASS_ANDN,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd,4146,4,93,0,0,XED_EXCEPTION_INVALID), +/*3795*/ XED_DEF_INST(XED_ICLASS_ANDN,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_ANDN_VGPR32d_VGPR32d_MEMd,4146,4,93,0,0,XED_EXCEPTION_INVALID), +/*3796*/ XED_DEF_INST(XED_ICLASS_ANDN,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d,4150,4,93,0,0,XED_EXCEPTION_INVALID), +/*3797*/ XED_DEF_INST(XED_ICLASS_ANDN,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_ANDN_VGPR32d_VGPR32d_VGPR32d,4150,4,93,0,0,XED_EXCEPTION_INVALID), +/*3798*/ XED_DEF_INST(XED_ICLASS_ANDN,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_ANDN_VGPR64q_VGPR64q_MEMq,4154,4,93,0,0,XED_EXCEPTION_INVALID), +/*3799*/ XED_DEF_INST(XED_ICLASS_ANDN,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_ANDN_VGPR64q_VGPR64q_VGPR64q,4158,4,93,0,0,XED_EXCEPTION_INVALID), +/*3800*/ XED_DEF_INST(XED_ICLASS_BLSR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSR_VGPR32d_MEMd,2836,3,94,0,0,XED_EXCEPTION_INVALID), +/*3801*/ XED_DEF_INST(XED_ICLASS_BLSR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSR_VGPR32d_MEMd,2836,3,94,0,0,XED_EXCEPTION_INVALID), +/*3802*/ XED_DEF_INST(XED_ICLASS_BLSR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSR_VGPR32d_VGPR32d,2842,3,94,0,0,XED_EXCEPTION_INVALID), +/*3803*/ XED_DEF_INST(XED_ICLASS_BLSR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSR_VGPR32d_VGPR32d,2842,3,94,0,0,XED_EXCEPTION_INVALID), +/*3804*/ XED_DEF_INST(XED_ICLASS_BLSR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSR_VGPR64q_MEMq,4162,3,94,0,0,XED_EXCEPTION_INVALID), +/*3805*/ XED_DEF_INST(XED_ICLASS_BLSR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSR_VGPR64q_VGPR64q,4165,3,94,0,0,XED_EXCEPTION_INVALID), +/*3806*/ XED_DEF_INST(XED_ICLASS_BLSMSK,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSMSK_VGPR32d_MEMd,2836,3,95,0,0,XED_EXCEPTION_INVALID), +/*3807*/ XED_DEF_INST(XED_ICLASS_BLSMSK,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSMSK_VGPR32d_MEMd,2836,3,95,0,0,XED_EXCEPTION_INVALID), +/*3808*/ XED_DEF_INST(XED_ICLASS_BLSMSK,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSMSK_VGPR32d_VGPR32d,2842,3,95,0,0,XED_EXCEPTION_INVALID), +/*3809*/ XED_DEF_INST(XED_ICLASS_BLSMSK,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSMSK_VGPR32d_VGPR32d,2842,3,95,0,0,XED_EXCEPTION_INVALID), +/*3810*/ XED_DEF_INST(XED_ICLASS_BLSMSK,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSMSK_VGPR64q_MEMq,4162,3,95,0,0,XED_EXCEPTION_INVALID), +/*3811*/ XED_DEF_INST(XED_ICLASS_BLSMSK,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSMSK_VGPR64q_VGPR64q,4165,3,95,0,0,XED_EXCEPTION_INVALID), +/*3812*/ XED_DEF_INST(XED_ICLASS_BLSI,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSI_VGPR32d_MEMd,2836,3,93,0,0,XED_EXCEPTION_INVALID), +/*3813*/ XED_DEF_INST(XED_ICLASS_BLSI,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSI_VGPR32d_MEMd,2836,3,93,0,0,XED_EXCEPTION_INVALID), +/*3814*/ XED_DEF_INST(XED_ICLASS_BLSI,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSI_VGPR32d_VGPR32d,2842,3,93,0,0,XED_EXCEPTION_INVALID), +/*3815*/ XED_DEF_INST(XED_ICLASS_BLSI,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSI_VGPR32d_VGPR32d,2842,3,93,0,0,XED_EXCEPTION_INVALID), +/*3816*/ XED_DEF_INST(XED_ICLASS_BLSI,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSI_VGPR64q_MEMq,4162,3,93,0,0,XED_EXCEPTION_INVALID), +/*3817*/ XED_DEF_INST(XED_ICLASS_BLSI,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BLSI_VGPR64q_VGPR64q,4165,3,93,0,0,XED_EXCEPTION_INVALID), +/*3818*/ XED_DEF_INST(XED_ICLASS_BZHI,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d,4168,4,94,0,0,XED_EXCEPTION_INVALID), +/*3819*/ XED_DEF_INST(XED_ICLASS_BZHI,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_BZHI_VGPR32d_MEMd_VGPR32d,4168,4,94,0,0,XED_EXCEPTION_INVALID), +/*3820*/ XED_DEF_INST(XED_ICLASS_BZHI,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d,4172,4,94,0,0,XED_EXCEPTION_INVALID), +/*3821*/ XED_DEF_INST(XED_ICLASS_BZHI,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_BZHI_VGPR32d_VGPR32d_VGPR32d,4172,4,94,0,0,XED_EXCEPTION_INVALID), +/*3822*/ XED_DEF_INST(XED_ICLASS_BZHI,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_BZHI_VGPR64q_MEMq_VGPR64q,4176,4,94,0,0,XED_EXCEPTION_INVALID), +/*3823*/ XED_DEF_INST(XED_ICLASS_BZHI,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_BZHI_VGPR64q_VGPR64q_VGPR64q,4180,4,94,0,0,XED_EXCEPTION_INVALID), +/*3824*/ XED_DEF_INST(XED_ICLASS_BEXTR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d,4168,4,78,0,0,XED_EXCEPTION_INVALID), +/*3825*/ XED_DEF_INST(XED_ICLASS_BEXTR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BEXTR_VGPR32d_MEMd_VGPR32d,4168,4,78,0,0,XED_EXCEPTION_INVALID), +/*3826*/ XED_DEF_INST(XED_ICLASS_BEXTR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d,4172,4,78,0,0,XED_EXCEPTION_INVALID), +/*3827*/ XED_DEF_INST(XED_ICLASS_BEXTR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BEXTR_VGPR32d_VGPR32d_VGPR32d,4172,4,78,0,0,XED_EXCEPTION_INVALID), +/*3828*/ XED_DEF_INST(XED_ICLASS_BEXTR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BEXTR_VGPR64q_MEMq_VGPR64q,4176,4,78,0,0,XED_EXCEPTION_INVALID), +/*3829*/ XED_DEF_INST(XED_ICLASS_BEXTR,XED_CATEGORY_BMI1,XED_EXTENSION_BMI1,3,XED_IFORM_BEXTR_VGPR64q_VGPR64q_VGPR64q,4180,4,78,0,0,XED_EXCEPTION_INVALID), +/*3830*/ XED_DEF_INST(XED_ICLASS_SHLX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d,4184,3,0,0,0,XED_EXCEPTION_INVALID), +/*3831*/ XED_DEF_INST(XED_ICLASS_SHLX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHLX_VGPR32d_MEMd_VGPR32d,4184,3,0,0,0,XED_EXCEPTION_INVALID), +/*3832*/ XED_DEF_INST(XED_ICLASS_SHLX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d,4187,3,0,0,0,XED_EXCEPTION_INVALID), +/*3833*/ XED_DEF_INST(XED_ICLASS_SHLX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHLX_VGPR32d_VGPR32d_VGPR32d,4187,3,0,0,0,XED_EXCEPTION_INVALID), +/*3834*/ XED_DEF_INST(XED_ICLASS_SHLX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHLX_VGPR64q_MEMq_VGPR64q,4190,3,0,0,0,XED_EXCEPTION_INVALID), +/*3835*/ XED_DEF_INST(XED_ICLASS_SHLX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHLX_VGPR64q_VGPR64q_VGPR64q,4193,3,0,0,0,XED_EXCEPTION_INVALID), +/*3836*/ XED_DEF_INST(XED_ICLASS_SARX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d,4184,3,0,0,0,XED_EXCEPTION_INVALID), +/*3837*/ XED_DEF_INST(XED_ICLASS_SARX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SARX_VGPR32d_MEMd_VGPR32d,4184,3,0,0,0,XED_EXCEPTION_INVALID), +/*3838*/ XED_DEF_INST(XED_ICLASS_SARX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d,4187,3,0,0,0,XED_EXCEPTION_INVALID), +/*3839*/ XED_DEF_INST(XED_ICLASS_SARX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SARX_VGPR32d_VGPR32d_VGPR32d,4187,3,0,0,0,XED_EXCEPTION_INVALID), +/*3840*/ XED_DEF_INST(XED_ICLASS_SARX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SARX_VGPR64q_MEMq_VGPR64q,4190,3,0,0,0,XED_EXCEPTION_INVALID), +/*3841*/ XED_DEF_INST(XED_ICLASS_SARX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SARX_VGPR64q_VGPR64q_VGPR64q,4193,3,0,0,0,XED_EXCEPTION_INVALID), +/*3842*/ XED_DEF_INST(XED_ICLASS_SHRX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d,4184,3,0,0,0,XED_EXCEPTION_INVALID), +/*3843*/ XED_DEF_INST(XED_ICLASS_SHRX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHRX_VGPR32d_MEMd_VGPR32d,4184,3,0,0,0,XED_EXCEPTION_INVALID), +/*3844*/ XED_DEF_INST(XED_ICLASS_SHRX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d,4187,3,0,0,0,XED_EXCEPTION_INVALID), +/*3845*/ XED_DEF_INST(XED_ICLASS_SHRX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHRX_VGPR32d_VGPR32d_VGPR32d,4187,3,0,0,0,XED_EXCEPTION_INVALID), +/*3846*/ XED_DEF_INST(XED_ICLASS_SHRX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHRX_VGPR64q_MEMq_VGPR64q,4190,3,0,0,0,XED_EXCEPTION_INVALID), +/*3847*/ XED_DEF_INST(XED_ICLASS_SHRX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_SHRX_VGPR64q_VGPR64q_VGPR64q,4193,3,0,0,0,XED_EXCEPTION_INVALID), +/*3848*/ XED_DEF_INST(XED_ICLASS_MULX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d,4196,4,0,0,0,XED_EXCEPTION_INVALID), +/*3849*/ XED_DEF_INST(XED_ICLASS_MULX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_MULX_VGPR32d_VGPR32d_VGPR32d,4196,4,0,0,0,XED_EXCEPTION_INVALID), +/*3850*/ XED_DEF_INST(XED_ICLASS_MULX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd,4200,4,0,0,0,XED_EXCEPTION_INVALID), +/*3851*/ XED_DEF_INST(XED_ICLASS_MULX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_MULX_VGPR32d_VGPR32d_MEMd,4200,4,0,0,0,XED_EXCEPTION_INVALID), +/*3852*/ XED_DEF_INST(XED_ICLASS_MULX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_MULX_VGPR64q_VGPR64q_VGPR64q,4204,4,0,0,0,XED_EXCEPTION_INVALID), +/*3853*/ XED_DEF_INST(XED_ICLASS_MULX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_MULX_VGPR64q_VGPR64q_MEMq,4208,4,0,0,0,XED_EXCEPTION_INVALID), +/*3854*/ XED_DEF_INST(XED_ICLASS_RORX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb,4212,3,0,0,0,XED_EXCEPTION_INVALID), +/*3855*/ XED_DEF_INST(XED_ICLASS_RORX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_RORX_VGPR32d_VGPR32d_IMMb,4212,3,0,0,0,XED_EXCEPTION_INVALID), +/*3856*/ XED_DEF_INST(XED_ICLASS_RORX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_RORX_VGPR32d_MEMd_IMMb,4215,3,0,0,0,XED_EXCEPTION_INVALID), +/*3857*/ XED_DEF_INST(XED_ICLASS_RORX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_RORX_VGPR32d_MEMd_IMMb,4215,3,0,0,0,XED_EXCEPTION_INVALID), +/*3858*/ XED_DEF_INST(XED_ICLASS_RORX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_RORX_VGPR64q_VGPR64q_IMMb,4218,3,0,0,0,XED_EXCEPTION_INVALID), +/*3859*/ XED_DEF_INST(XED_ICLASS_RORX,XED_CATEGORY_BMI2,XED_EXTENSION_BMI2,3,XED_IFORM_RORX_VGPR64q_MEMq_IMMb,4221,3,0,0,0,XED_EXCEPTION_INVALID), +/*3860*/ XED_DEF_INST(XED_ICLASS_KANDNW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDNW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3861*/ XED_DEF_INST(XED_ICLASS_KANDW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3862*/ XED_DEF_INST(XED_ICLASS_KMOVW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVW_MASKmskw_MASKu16_AVX512,4227,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3863*/ XED_DEF_INST(XED_ICLASS_KMOVW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVW_MASKmskw_MEMu16_AVX512,4229,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3864*/ XED_DEF_INST(XED_ICLASS_KMOVW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVW_MEMu16_MASKmskw_AVX512,4231,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3865*/ XED_DEF_INST(XED_ICLASS_KMOVW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVW_MASKmskw_GPR32u32_AVX512,4233,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3866*/ XED_DEF_INST(XED_ICLASS_KMOVW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVW_GPR32u32_MASKmskw_AVX512,4235,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3867*/ XED_DEF_INST(XED_ICLASS_KNOTW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KNOTW_MASKmskw_MASKmskw_AVX512,4237,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3868*/ XED_DEF_INST(XED_ICLASS_KORTESTW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORTESTW_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3869*/ XED_DEF_INST(XED_ICLASS_KORW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3870*/ XED_DEF_INST(XED_ICLASS_KSHIFTLW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTLW_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3871*/ XED_DEF_INST(XED_ICLASS_KSHIFTRW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTRW_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3872*/ XED_DEF_INST(XED_ICLASS_KUNPCKBW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KUNPCKBW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3873*/ XED_DEF_INST(XED_ICLASS_KXNORW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXNORW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3874*/ XED_DEF_INST(XED_ICLASS_KXORW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXORW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3875*/ XED_DEF_INST(XED_ICLASS_KADDB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KADDB_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3876*/ XED_DEF_INST(XED_ICLASS_KADDD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KADDD_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3877*/ XED_DEF_INST(XED_ICLASS_KADDQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KADDQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3878*/ XED_DEF_INST(XED_ICLASS_KADDW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KADDW_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3879*/ XED_DEF_INST(XED_ICLASS_KANDB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDB_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3880*/ XED_DEF_INST(XED_ICLASS_KANDD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDD_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3881*/ XED_DEF_INST(XED_ICLASS_KANDNB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDNB_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3882*/ XED_DEF_INST(XED_ICLASS_KANDND,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDND_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3883*/ XED_DEF_INST(XED_ICLASS_KANDNQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDNQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3884*/ XED_DEF_INST(XED_ICLASS_KANDQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KANDQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3885*/ XED_DEF_INST(XED_ICLASS_KMOVB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVB_MASKmskw_MASKu8_AVX512,4245,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3886*/ XED_DEF_INST(XED_ICLASS_KMOVB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVB_MASKmskw_MEMu8_AVX512,4247,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3887*/ XED_DEF_INST(XED_ICLASS_KMOVB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVB_MEMu8_MASKmskw_AVX512,4249,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3888*/ XED_DEF_INST(XED_ICLASS_KMOVB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVB_MASKmskw_GPR32u32_AVX512,4233,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3889*/ XED_DEF_INST(XED_ICLASS_KMOVB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVB_GPR32u32_MASKmskw_AVX512,4235,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3890*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_MASKmskw_MASKu32_AVX512,4251,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3891*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_MASKmskw_MEMu32_AVX512,4253,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3892*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_MEMu32_MASKmskw_AVX512,4255,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3893*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512,4233,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3894*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_MASKmskw_GPR32u32_AVX512,4233,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3895*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512,4235,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3896*/ XED_DEF_INST(XED_ICLASS_KMOVD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVD_GPR32u32_MASKmskw_AVX512,4235,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3897*/ XED_DEF_INST(XED_ICLASS_KMOVQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVQ_MASKmskw_MASKu64_AVX512,4257,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3898*/ XED_DEF_INST(XED_ICLASS_KMOVQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVQ_MASKmskw_MEMu64_AVX512,4259,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3899*/ XED_DEF_INST(XED_ICLASS_KMOVQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVQ_MEMu64_MASKmskw_AVX512,4261,2,0,0,126,XED_EXCEPTION_AVX512_K21), +/*3900*/ XED_DEF_INST(XED_ICLASS_KMOVQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVQ_MASKmskw_GPR64u64_AVX512,4263,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3901*/ XED_DEF_INST(XED_ICLASS_KMOVQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KMOVQ_GPR64u64_MASKmskw_AVX512,4265,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3902*/ XED_DEF_INST(XED_ICLASS_KNOTB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KNOTB_MASKmskw_MASKmskw_AVX512,4237,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3903*/ XED_DEF_INST(XED_ICLASS_KNOTD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KNOTD_MASKmskw_MASKmskw_AVX512,4237,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3904*/ XED_DEF_INST(XED_ICLASS_KNOTQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KNOTQ_MASKmskw_MASKmskw_AVX512,4237,2,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3905*/ XED_DEF_INST(XED_ICLASS_KORB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORB_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3906*/ XED_DEF_INST(XED_ICLASS_KORD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORD_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3907*/ XED_DEF_INST(XED_ICLASS_KORQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3908*/ XED_DEF_INST(XED_ICLASS_KORTESTB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORTESTB_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3909*/ XED_DEF_INST(XED_ICLASS_KORTESTD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORTESTD_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3910*/ XED_DEF_INST(XED_ICLASS_KORTESTQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KORTESTQ_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3911*/ XED_DEF_INST(XED_ICLASS_KSHIFTLB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTLB_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3912*/ XED_DEF_INST(XED_ICLASS_KSHIFTLD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTLD_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3913*/ XED_DEF_INST(XED_ICLASS_KSHIFTLQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTLQ_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3914*/ XED_DEF_INST(XED_ICLASS_KSHIFTRB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTRB_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3915*/ XED_DEF_INST(XED_ICLASS_KSHIFTRD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTRD_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3916*/ XED_DEF_INST(XED_ICLASS_KSHIFTRQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KSHIFTRQ_MASKmskw_MASKmskw_IMM8_AVX512,4242,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3917*/ XED_DEF_INST(XED_ICLASS_KTESTB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KTESTB_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3918*/ XED_DEF_INST(XED_ICLASS_KTESTD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KTESTD_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3919*/ XED_DEF_INST(XED_ICLASS_KTESTQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KTESTQ_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3920*/ XED_DEF_INST(XED_ICLASS_KTESTW,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KTESTW_MASKmskw_MASKmskw_AVX512,4239,3,96,0,126,XED_EXCEPTION_AVX512_K20), +/*3921*/ XED_DEF_INST(XED_ICLASS_KUNPCKDQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KUNPCKDQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3922*/ XED_DEF_INST(XED_ICLASS_KUNPCKWD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KUNPCKWD_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3923*/ XED_DEF_INST(XED_ICLASS_KXNORB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXNORB_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3924*/ XED_DEF_INST(XED_ICLASS_KXNORD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXNORD_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3925*/ XED_DEF_INST(XED_ICLASS_KXNORQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXNORQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3926*/ XED_DEF_INST(XED_ICLASS_KXORB,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXORB_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3927*/ XED_DEF_INST(XED_ICLASS_KXORD,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXORD_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3928*/ XED_DEF_INST(XED_ICLASS_KXORQ,XED_CATEGORY_KMASK,XED_EXTENSION_AVX512VEX,3,XED_IFORM_KXORQ_MASKmskw_MASKmskw_MASKmskw_AVX512,4224,3,0,0,126,XED_EXCEPTION_AVX512_K20), +/*3929*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_XMMu64_IMM8,4267,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3930*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_XMMu8_MEMu64_IMM8,4271,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3931*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_YMMu64_IMM8,4275,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3932*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_YMMu8_MEMu64_IMM8,4279,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3933*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_XMMu64_IMM8,4267,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3934*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEQB_XMMu8_XMMu8_MEMu64_IMM8,4271,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3935*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_YMMu64_IMM8,4275,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3936*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8AFFINEQB_YMMu8_YMMu8_MEMu64_IMM8,4279,4,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3937*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_XMMu8,2579,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3938*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8MULB_XMMu8_XMMu8_MEMu8,2576,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3939*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_YMMu8,3616,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3940*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_GFNI,3,XED_IFORM_VGF2P8MULB_YMMu8_YMMu8_MEMu8,3613,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3941*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSD_XMMi32_XMMu32_XMMu32,4283,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3942*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSD_XMMi32_XMMu32_MEMu32,4286,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3943*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSD_YMMi32_YMMu32_YMMu32,4289,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3944*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSD_YMMi32_YMMu32_MEMu32,4292,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3945*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_XMMu32,4283,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3946*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSDS_XMMi32_XMMu32_MEMu32,4286,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3947*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_YMMu32,4289,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3948*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPBUSDS_YMMi32_YMMu32_MEMu32,4292,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3949*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSD_XMMi32_XMMu32_XMMu32,4283,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3950*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSD_XMMi32_XMMu32_MEMu32,4286,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3951*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSD_YMMi32_YMMu32_YMMu32,4289,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3952*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSD_YMMi32_YMMu32_MEMu32,4292,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3953*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_XMMu32,4283,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3954*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSDS_XMMi32_XMMu32_MEMu32,4286,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3955*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_YMMu32,4289,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3956*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_VEX,XED_EXTENSION_AVX_VNNI,3,XED_IFORM_VPDPWSSDS_YMMi32_YMMu32_MEMu32,4292,3,0,0,0,XED_EXCEPTION_AVX_TYPE_4), +/*3957*/ XED_DEF_INST(XED_ICLASS_LDTILECFG,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_LDTILECFG_MEM,4295,1,0,0,1,XED_EXCEPTION_AMX_E1), +/*3958*/ XED_DEF_INST(XED_ICLASS_STTILECFG,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_STTILECFG_MEM,4296,1,0,0,1,XED_EXCEPTION_AMX_E2), +/*3959*/ XED_DEF_INST(XED_ICLASS_TDPBF16PS,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_BF16,3,XED_IFORM_TDPBF16PS_TMMf32_TMMu32_TMMu32,4297,3,0,0,1,XED_EXCEPTION_AMX_E4), +/*3960*/ XED_DEF_INST(XED_ICLASS_TDPBSSD,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_INT8,3,XED_IFORM_TDPBSSD_TMMi32_TMMu32_TMMu32,4300,3,0,0,1,XED_EXCEPTION_AMX_E4), +/*3961*/ XED_DEF_INST(XED_ICLASS_TDPBSUD,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_INT8,3,XED_IFORM_TDPBSUD_TMMi32_TMMu32_TMMu32,4300,3,0,0,1,XED_EXCEPTION_AMX_E4), +/*3962*/ XED_DEF_INST(XED_ICLASS_TDPBUSD,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_INT8,3,XED_IFORM_TDPBUSD_TMMi32_TMMu32_TMMu32,4300,3,0,0,1,XED_EXCEPTION_AMX_E4), +/*3963*/ XED_DEF_INST(XED_ICLASS_TDPBUUD,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_INT8,3,XED_IFORM_TDPBUUD_TMMu32_TMMu32_TMMu32,4303,3,0,0,1,XED_EXCEPTION_AMX_E4), +/*3964*/ XED_DEF_INST(XED_ICLASS_TILELOADD,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_TILELOADD_TMMu32_MEMu32,4306,2,0,0,127,XED_EXCEPTION_AMX_E3), +/*3965*/ XED_DEF_INST(XED_ICLASS_TILELOADDT1,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_TILELOADDT1_TMMu32_MEMu32,4306,2,0,0,127,XED_EXCEPTION_AMX_E3), +/*3966*/ XED_DEF_INST(XED_ICLASS_TILERELEASE,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_TILERELEASE,0,0,0,0,1,XED_EXCEPTION_AMX_E6), +/*3967*/ XED_DEF_INST(XED_ICLASS_TILESTORED,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_TILESTORED_MEMu32_TMMu32,4308,2,0,0,127,XED_EXCEPTION_AMX_E3), +/*3968*/ XED_DEF_INST(XED_ICLASS_TILEZERO,XED_CATEGORY_AMX_TILE,XED_EXTENSION_AMX_TILE,3,XED_IFORM_TILEZERO_TMMu32,4310,1,0,0,1,XED_EXCEPTION_AMX_E5), +/*3969*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512,4311,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3970*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512,4315,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3971*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512,4319,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3972*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512,4323,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3973*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512,4327,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3974*/ XED_DEF_INST(XED_ICLASS_VPDPBUSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512,4331,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3975*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512,4311,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3976*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512,4315,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3977*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512,4319,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3978*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512,4323,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3979*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512,4327,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3980*/ XED_DEF_INST(XED_ICLASS_VPDPBUSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512,4331,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3981*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512,4335,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3982*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512,4339,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3983*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512,4343,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3984*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512,4347,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3985*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512,4351,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3986*/ XED_DEF_INST(XED_ICLASS_VPDPWSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512,4355,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3987*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512,4335,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3988*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512,4339,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3989*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512,4343,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3990*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512,4347,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3991*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512,4351,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3992*/ XED_DEF_INST(XED_ICLASS_VPDPWSSDS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512,4355,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*3993*/ XED_DEF_INST(XED_ICLASS_VCVTNE2PS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512,4359,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3994*/ XED_DEF_INST(XED_ICLASS_VCVTNE2PS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128,4363,4,0,0,130,XED_EXCEPTION_AVX512_E4), +/*3995*/ XED_DEF_INST(XED_ICLASS_VCVTNE2PS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512,4367,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3996*/ XED_DEF_INST(XED_ICLASS_VCVTNE2PS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256,4371,4,0,0,130,XED_EXCEPTION_AVX512_E4), +/*3997*/ XED_DEF_INST(XED_ICLASS_VCVTNE2PS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512,4375,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*3998*/ XED_DEF_INST(XED_ICLASS_VCVTNE2PS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512,4379,4,0,0,130,XED_EXCEPTION_AVX512_E4), +/*3999*/ XED_DEF_INST(XED_ICLASS_VCVTNEPS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512,4383,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4000*/ XED_DEF_INST(XED_ICLASS_VCVTNEPS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128,4386,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4001*/ XED_DEF_INST(XED_ICLASS_VCVTNEPS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512,4389,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4002*/ XED_DEF_INST(XED_ICLASS_VCVTNEPS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256,4386,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4003*/ XED_DEF_INST(XED_ICLASS_VCVTNEPS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512,4392,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4004*/ XED_DEF_INST(XED_ICLASS_VCVTNEPS2BF16,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512,4395,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4005*/ XED_DEF_INST(XED_ICLASS_VDPBF16PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512,4398,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4006*/ XED_DEF_INST(XED_ICLASS_VDPBF16PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512,4402,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4007*/ XED_DEF_INST(XED_ICLASS_VDPBF16PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512,4406,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4008*/ XED_DEF_INST(XED_ICLASS_VDPBF16PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512,4410,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4009*/ XED_DEF_INST(XED_ICLASS_VDPBF16PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512,4414,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4010*/ XED_DEF_INST(XED_ICLASS_VDPBF16PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512,4418,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4011*/ XED_DEF_INST(XED_ICLASS_VEXP2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER,4422,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4012*/ XED_DEF_INST(XED_ICLASS_VEXP2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER,4425,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4013*/ XED_DEF_INST(XED_ICLASS_VEXP2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER,4428,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4014*/ XED_DEF_INST(XED_ICLASS_VEXP2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER,4431,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4015*/ XED_DEF_INST(XED_ICLASS_VEXP2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER,4434,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4016*/ XED_DEF_INST(XED_ICLASS_VEXP2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER,4437,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4017*/ XED_DEF_INST(XED_ICLASS_VGATHERPF0DPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,133,XED_EXCEPTION_AVX512_E12NP), +/*4018*/ XED_DEF_INST(XED_ICLASS_VGATHERPF0DPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,133,XED_EXCEPTION_AVX512_E12NP), +/*4019*/ XED_DEF_INST(XED_ICLASS_VGATHERPF0QPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,134,XED_EXCEPTION_AVX512_E12NP), +/*4020*/ XED_DEF_INST(XED_ICLASS_VGATHERPF0QPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,134,XED_EXCEPTION_AVX512_E12NP), +/*4021*/ XED_DEF_INST(XED_ICLASS_VGATHERPF1DPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,133,XED_EXCEPTION_AVX512_E12NP), +/*4022*/ XED_DEF_INST(XED_ICLASS_VGATHERPF1DPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,133,XED_EXCEPTION_AVX512_E12NP), +/*4023*/ XED_DEF_INST(XED_ICLASS_VGATHERPF1QPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,134,XED_EXCEPTION_AVX512_E12NP), +/*4024*/ XED_DEF_INST(XED_ICLASS_VGATHERPF1QPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,134,XED_EXCEPTION_AVX512_E12NP), +/*4025*/ XED_DEF_INST(XED_ICLASS_VRCP28PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER,4422,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4026*/ XED_DEF_INST(XED_ICLASS_VRCP28PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER,4425,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4027*/ XED_DEF_INST(XED_ICLASS_VRCP28PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER,4428,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4028*/ XED_DEF_INST(XED_ICLASS_VRCP28PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER,4431,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4029*/ XED_DEF_INST(XED_ICLASS_VRCP28PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER,4434,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4030*/ XED_DEF_INST(XED_ICLASS_VRCP28PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER,4437,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4031*/ XED_DEF_INST(XED_ICLASS_VRCP28SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4032*/ XED_DEF_INST(XED_ICLASS_VRCP28SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER,4448,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4033*/ XED_DEF_INST(XED_ICLASS_VRCP28SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4034*/ XED_DEF_INST(XED_ICLASS_VRCP28SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4035*/ XED_DEF_INST(XED_ICLASS_VRCP28SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER,4460,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4036*/ XED_DEF_INST(XED_ICLASS_VRCP28SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4037*/ XED_DEF_INST(XED_ICLASS_VRSQRT28PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER,4422,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4038*/ XED_DEF_INST(XED_ICLASS_VRSQRT28PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER,4425,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4039*/ XED_DEF_INST(XED_ICLASS_VRSQRT28PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER,4428,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4040*/ XED_DEF_INST(XED_ICLASS_VRSQRT28PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER,4431,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4041*/ XED_DEF_INST(XED_ICLASS_VRSQRT28PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER,4434,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4042*/ XED_DEF_INST(XED_ICLASS_VRSQRT28PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER,4437,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4043*/ XED_DEF_INST(XED_ICLASS_VRSQRT28SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4044*/ XED_DEF_INST(XED_ICLASS_VRSQRT28SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER,4448,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4045*/ XED_DEF_INST(XED_ICLASS_VRSQRT28SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4046*/ XED_DEF_INST(XED_ICLASS_VRSQRT28SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4047*/ XED_DEF_INST(XED_ICLASS_VRSQRT28SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER,4460,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4048*/ XED_DEF_INST(XED_ICLASS_VRSQRT28SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4049*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF0DPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF0DPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,137,XED_EXCEPTION_AVX512_E12NP), +/*4050*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF0DPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF0DPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,137,XED_EXCEPTION_AVX512_E12NP), +/*4051*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF0QPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF0QPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,138,XED_EXCEPTION_AVX512_E12NP), +/*4052*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF0QPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF0QPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,138,XED_EXCEPTION_AVX512_E12NP), +/*4053*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF1DPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF1DPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,137,XED_EXCEPTION_AVX512_E12NP), +/*4054*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF1DPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF1DPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,137,XED_EXCEPTION_AVX512_E12NP), +/*4055*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF1QPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF1QPD_MEMf64_MASKmskw_AVX512PF_VL512,4440,2,0,0,138,XED_EXCEPTION_AVX512_E12NP), +/*4056*/ XED_DEF_INST(XED_ICLASS_VSCATTERPF1QPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERPF1QPS_MEMf32_MASKmskw_AVX512PF_VL512,4442,2,0,0,138,XED_EXCEPTION_AVX512_E12NP), +/*4057*/ XED_DEF_INST(XED_ICLASS_V4FMADDPS,XED_CATEGORY_AVX512_4FMAPS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4468,4,0,0,139,XED_EXCEPTION_AVX512_E2), +/*4058*/ XED_DEF_INST(XED_ICLASS_V4FMADDSS,XED_CATEGORY_AVX512_4FMAPS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4472,4,0,0,140,XED_EXCEPTION_AVX512_E2), +/*4059*/ XED_DEF_INST(XED_ICLASS_V4FNMADDPS,XED_CATEGORY_AVX512_4FMAPS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4468,4,0,0,139,XED_EXCEPTION_AVX512_E2), +/*4060*/ XED_DEF_INST(XED_ICLASS_V4FNMADDSS,XED_CATEGORY_AVX512_4FMAPS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4472,4,0,0,140,XED_EXCEPTION_AVX512_E2), +/*4061*/ XED_DEF_INST(XED_ICLASS_VP4DPWSSD,XED_CATEGORY_AVX512_4VNNIW,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512,4476,4,0,0,141,XED_EXCEPTION_AVX512_E4), +/*4062*/ XED_DEF_INST(XED_ICLASS_VP4DPWSSDS,XED_CATEGORY_AVX512_4VNNIW,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512,4476,4,0,0,141,XED_EXCEPTION_AVX512_E4), +/*4063*/ XED_DEF_INST(XED_ICLASS_VPOPCNTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512,4480,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4064*/ XED_DEF_INST(XED_ICLASS_VPOPCNTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512,4483,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4065*/ XED_DEF_INST(XED_ICLASS_VPOPCNTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4066*/ XED_DEF_INST(XED_ICLASS_VPOPCNTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512,4489,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4067*/ XED_DEF_INST(XED_ICLASS_VPOPCNTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512,4492,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4068*/ XED_DEF_INST(XED_ICLASS_VPOPCNTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512,4495,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4069*/ XED_DEF_INST(XED_ICLASS_VPOPCNTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512,4498,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4070*/ XED_DEF_INST(XED_ICLASS_VPOPCNTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512,4501,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4071*/ XED_DEF_INST(XED_ICLASS_VPOPCNTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4072*/ XED_DEF_INST(XED_ICLASS_VPOPCNTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512,4507,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4073*/ XED_DEF_INST(XED_ICLASS_VPOPCNTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512,4510,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4074*/ XED_DEF_INST(XED_ICLASS_VPOPCNTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512,4513,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*4075*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4076*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4520,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4077*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4078*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4079*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4080*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4081*/ XED_DEF_INST(XED_ICLASS_VADDPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4082*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4083*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4544,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4084*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4085*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4086*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4087*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4088*/ XED_DEF_INST(XED_ICLASS_VADDPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4089*/ XED_DEF_INST(XED_ICLASS_VADDSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4090*/ XED_DEF_INST(XED_ICLASS_VADDSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4564,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4091*/ XED_DEF_INST(XED_ICLASS_VADDSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4092*/ XED_DEF_INST(XED_ICLASS_VADDSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4093*/ XED_DEF_INST(XED_ICLASS_VADDSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4568,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4094*/ XED_DEF_INST(XED_ICLASS_VADDSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4095*/ XED_DEF_INST(XED_ICLASS_VALIGND,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512,4572,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*4096*/ XED_DEF_INST(XED_ICLASS_VALIGND,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,4577,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*4097*/ XED_DEF_INST(XED_ICLASS_VALIGND,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512,4582,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*4098*/ XED_DEF_INST(XED_ICLASS_VALIGND,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512,4587,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*4099*/ XED_DEF_INST(XED_ICLASS_VALIGND,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512,4592,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*4100*/ XED_DEF_INST(XED_ICLASS_VALIGND,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,4597,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*4101*/ XED_DEF_INST(XED_ICLASS_VALIGNQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512,4602,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*4102*/ XED_DEF_INST(XED_ICLASS_VALIGNQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,4607,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*4103*/ XED_DEF_INST(XED_ICLASS_VALIGNQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512,4612,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*4104*/ XED_DEF_INST(XED_ICLASS_VALIGNQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512,4617,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*4105*/ XED_DEF_INST(XED_ICLASS_VALIGNQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512,4622,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*4106*/ XED_DEF_INST(XED_ICLASS_VALIGNQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,4627,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*4107*/ XED_DEF_INST(XED_ICLASS_VBLENDMPD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*4108*/ XED_DEF_INST(XED_ICLASS_VBLENDMPD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*4109*/ XED_DEF_INST(XED_ICLASS_VBLENDMPD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*4110*/ XED_DEF_INST(XED_ICLASS_VBLENDMPD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*4111*/ XED_DEF_INST(XED_ICLASS_VBLENDMPD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*4112*/ XED_DEF_INST(XED_ICLASS_VBLENDMPD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*4113*/ XED_DEF_INST(XED_ICLASS_VBLENDMPS,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*4114*/ XED_DEF_INST(XED_ICLASS_VBLENDMPS,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*4115*/ XED_DEF_INST(XED_ICLASS_VBLENDMPS,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*4116*/ XED_DEF_INST(XED_ICLASS_VBLENDMPS,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*4117*/ XED_DEF_INST(XED_ICLASS_VBLENDMPS,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*4118*/ XED_DEF_INST(XED_ICLASS_VBLENDMPS,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*4119*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X4,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512,4632,3,0,0,144,XED_EXCEPTION_AVX512_E6), +/*4120*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X4,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512,4635,3,0,0,144,XED_EXCEPTION_AVX512_E6), +/*4121*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF64X4,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512,4638,3,0,0,144,XED_EXCEPTION_AVX512_E6), +/*4122*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X4,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512,4641,3,0,0,144,XED_EXCEPTION_AVX512_E6), +/*4123*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X4,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512,4644,3,0,0,144,XED_EXCEPTION_AVX512_E6), +/*4124*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI64X4,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512,4647,3,0,0,144,XED_EXCEPTION_AVX512_E6), +/*4125*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512,4650,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*4126*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512,4653,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*4127*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512,4656,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*4128*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512,4659,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*4129*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512,4662,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*4130*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512,4665,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*4131*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512,4668,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*4132*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*4133*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512,4674,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*4134*/ XED_DEF_INST(XED_ICLASS_VBROADCASTSS,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512,4677,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*4135*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,4680,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4136*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,4685,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4137*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,4690,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4138*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,4695,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4139*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,4700,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4140*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512,4705,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4141*/ XED_DEF_INST(XED_ICLASS_VCMPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512,4710,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4142*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,4715,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4143*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,4720,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4144*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,4725,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4145*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,4730,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4146*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,4735,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4147*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512,4740,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4148*/ XED_DEF_INST(XED_ICLASS_VCMPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512,4745,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4149*/ XED_DEF_INST(XED_ICLASS_VCMPSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,4695,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4150*/ XED_DEF_INST(XED_ICLASS_VCMPSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,4750,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4151*/ XED_DEF_INST(XED_ICLASS_VCMPSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,4755,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4152*/ XED_DEF_INST(XED_ICLASS_VCMPSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,4730,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4153*/ XED_DEF_INST(XED_ICLASS_VCMPSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,4760,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4154*/ XED_DEF_INST(XED_ICLASS_VCMPSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,4765,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4155*/ XED_DEF_INST(XED_ICLASS_VCOMISD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512,4770,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4156*/ XED_DEF_INST(XED_ICLASS_VCOMISD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISD_XMMf64_XMMf64_AVX512,4773,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4157*/ XED_DEF_INST(XED_ICLASS_VCOMISD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISD_XMMf64_MEMf64_AVX512,4776,3,97,0,146,XED_EXCEPTION_AVX512_E3NF), +/*4158*/ XED_DEF_INST(XED_ICLASS_VCOMISS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512,4779,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4159*/ XED_DEF_INST(XED_ICLASS_VCOMISS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISS_XMMf32_XMMf32_AVX512,4782,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4160*/ XED_DEF_INST(XED_ICLASS_VCOMISS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISS_XMMf32_MEMf32_AVX512,4785,3,97,0,146,XED_EXCEPTION_AVX512_E3NF), +/*4161*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512,4788,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4162*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4791,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4163*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512,4794,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4164*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512,4797,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4165*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512,4800,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4166*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512,4803,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4167*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPS,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512,4806,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4168*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPS,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4809,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4169*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPS,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512,4812,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4170*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPS,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512,4815,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4171*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPS,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512,4818,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4172*/ XED_DEF_INST(XED_ICLASS_VCOMPRESSPS,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512,4821,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4173*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512,4824,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4174*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512,4824,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4175*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512,4827,3,0,0,148,XED_EXCEPTION_AVX512_E5), +/*4176*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512,4830,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4177*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512,4833,3,0,0,148,XED_EXCEPTION_AVX512_E5), +/*4178*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512,4836,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4179*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512,4839,3,0,0,148,XED_EXCEPTION_AVX512_E5), +/*4180*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512,4842,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4181*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512,4845,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4182*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512,4848,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4183*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512,4851,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4184*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512,4854,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4185*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512,4857,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4186*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512,4860,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4187*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512,4863,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4188*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512,4866,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4189*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512,4869,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4190*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128,4872,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4191*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128,4875,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4192*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256,4878,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4193*/ XED_DEF_INST(XED_ICLASS_VCVTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256,4875,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4194*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512,4881,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4195*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512,4884,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4196*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512,4887,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4197*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128,4890,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4198*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128,4893,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4199*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256,4896,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4200*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256,4893,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4201*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512,4899,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4202*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512,4902,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4203*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512,4905,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4204*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128,4908,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4205*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128,4911,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4206*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256,4914,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4207*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256,4911,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4208*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512,4917,3,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4209*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512,4920,3,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4210*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512,4923,3,0,0,149,XED_EXCEPTION_AVX512_E11), +/*4211*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512,4926,3,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4212*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512,4929,3,0,0,149,XED_EXCEPTION_AVX512_E11), +/*4213*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512,4932,3,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4214*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512,4935,3,0,0,149,XED_EXCEPTION_AVX512_E11), +/*4215*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512,4938,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4216*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512,4941,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4217*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512,4944,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4218*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512,4947,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4219*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512,4950,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4220*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512,4953,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4221*/ XED_DEF_INST(XED_ICLASS_VCVTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512,4956,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4222*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512,4959,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*4223*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512,4962,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*4224*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512,4965,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*4225*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512,4968,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*4226*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512,4971,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*4227*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512,4974,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*4228*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512,4977,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*4229*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512,4980,4,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4230*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512,4984,4,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4231*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512,4988,4,0,0,149,XED_EXCEPTION_AVX512_E11), +/*4232*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512,4992,4,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4233*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512,4996,4,0,0,149,XED_EXCEPTION_AVX512_E11), +/*4234*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512,5000,4,0,0,131,XED_EXCEPTION_AVX512_E11), +/*4235*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512,5004,4,0,0,149,XED_EXCEPTION_AVX512_E11), +/*4236*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512,5008,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4237*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512,5011,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4238*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512,5014,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4239*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512,5017,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4240*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512,5020,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4241*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512,5023,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4242*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512,5026,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4243*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512,5029,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4244*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512,5029,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4245*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512,5031,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4246*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR32i32_XMMf64_AVX512,5031,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4247*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512,3195,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4248*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR32i32_MEMf64_AVX512,3195,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4249*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512,5033,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4250*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR64i64_XMMf64_AVX512,5035,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4251*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SI_GPR64i64_MEMf64_AVX512,3199,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4252*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512,5037,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4253*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512,5041,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4254*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512,5045,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4255*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512,5049,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4256*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512,5049,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4257*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512,5051,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4258*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR32u32_XMMf64_AVX512,5051,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4259*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512,5053,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4260*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR32u32_MEMf64_AVX512,5053,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4261*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512,5055,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4262*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR64u64_XMMf64_AVX512,5057,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4263*/ XED_DEF_INST(XED_ICLASS_VCVTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2USI_GPR64u64_MEMf64_AVX512,5059,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4264*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512,5061,3,0,0,80,XED_EXCEPTION_AVX512_E10NF), +/*4265*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512,5061,3,0,0,80,XED_EXCEPTION_AVX512_E10NF), +/*4266*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512,5064,3,0,0,152,XED_EXCEPTION_AVX512_E10NF), +/*4267*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512,5064,3,0,0,152,XED_EXCEPTION_AVX512_E10NF), +/*4268*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512,5067,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4269*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512,5070,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4270*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512,5073,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4271*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512,5076,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4272*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512,5076,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4273*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512,5079,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4274*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512,5079,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4275*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512,5082,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4276*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512,5082,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4277*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512,5085,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4278*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512,5088,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4279*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512,5091,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4280*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512,5094,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4281*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512,5098,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4282*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512,5102,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4283*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512,5106,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4284*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512,5106,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4285*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512,5108,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4286*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR32i32_XMMf32_AVX512,5108,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4287*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512,3203,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4288*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR32i32_MEMf32_AVX512,3203,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4289*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512,5110,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4290*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR64i64_XMMf32_AVX512,5112,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4291*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SI_GPR64i64_MEMf32_AVX512,3207,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4292*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512,5114,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4293*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512,5114,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4294*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512,5116,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4295*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR32u32_XMMf32_AVX512,5116,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4296*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512,5118,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4297*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR32u32_MEMf32_AVX512,5118,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4298*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512,5120,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4299*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR64u64_XMMf32_AVX512,5122,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4300*/ XED_DEF_INST(XED_ICLASS_VCVTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2USI_GPR64u64_MEMf32_AVX512,5124,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4301*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512,4863,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4302*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512,5126,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4303*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512,4869,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4304*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128,4872,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4305*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128,4875,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4306*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256,4878,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4307*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256,4875,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4308*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512,4899,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4309*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512,5129,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4310*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512,4905,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4311*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128,4908,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4312*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128,4911,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4313*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256,4914,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4314*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256,4911,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4315*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512,4938,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4316*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512,5132,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4317*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512,4944,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4318*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512,4947,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4319*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512,4950,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4320*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512,4953,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4321*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512,4956,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4322*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512,5008,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4323*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512,5135,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4324*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512,5014,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4325*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512,5017,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4326*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512,5020,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4327*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512,5023,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4328*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512,5026,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4329*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512,5029,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4330*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512,5029,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4331*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512,5138,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4332*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR32i32_XMMf64_AVX512,5138,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4333*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512,3195,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4334*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR32i32_MEMf64_AVX512,3195,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4335*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512,5033,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4336*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR64i64_XMMf64_AVX512,5140,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4337*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2SI_GPR64i64_MEMf64_AVX512,3199,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4338*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512,5049,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4339*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512,5049,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4340*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512,5142,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4341*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR32u32_XMMf64_AVX512,5142,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4342*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512,5053,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4343*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR32u32_MEMf64_AVX512,5053,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4344*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512,5055,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4345*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR64u64_XMMf64_AVX512,5144,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4346*/ XED_DEF_INST(XED_ICLASS_VCVTTSD2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSD2USI_GPR64u64_MEMf64_AVX512,5059,2,0,0,151,XED_EXCEPTION_AVX512_E3NF), +/*4347*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512,5106,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4348*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512,5106,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4349*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512,5146,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4350*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR32i32_XMMf32_AVX512,5146,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4351*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512,3203,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4352*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR32i32_MEMf32_AVX512,3203,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4353*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512,5110,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4354*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR64i64_XMMf32_AVX512,5148,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4355*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2SI_GPR64i64_MEMf32_AVX512,3207,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4356*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512,5114,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4357*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512,5114,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4358*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512,5150,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4359*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR32u32_XMMf32_AVX512,5150,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4360*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512,5118,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4361*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR32u32_MEMf32_AVX512,5118,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4362*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512,5120,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4363*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR64u64_XMMf32_AVX512,5152,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4364*/ XED_DEF_INST(XED_ICLASS_VCVTTSS2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSS2USI_GPR64u64_MEMf32_AVX512,5124,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*4365*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512,5154,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4366*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512,5154,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4367*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512,5157,3,0,0,148,XED_EXCEPTION_AVX512_E5), +/*4368*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512,5160,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4369*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512,5163,3,0,0,148,XED_EXCEPTION_AVX512_E5), +/*4370*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512,5166,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*4371*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512,5169,3,0,0,148,XED_EXCEPTION_AVX512_E5), +/*4372*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512,5172,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4373*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512,5175,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4374*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512,5178,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4375*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512,5181,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4376*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512,5184,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4377*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512,5187,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4378*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512,5190,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4379*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512,5193,3,0,0,80,XED_EXCEPTION_AVX512_E10NF), +/*4380*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512,5193,3,0,0,80,XED_EXCEPTION_AVX512_E10NF), +/*4381*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512,5196,3,0,0,152,XED_EXCEPTION_AVX512_E10NF), +/*4382*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512,5196,3,0,0,152,XED_EXCEPTION_AVX512_E10NF), +/*4383*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512,5199,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4384*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512,5202,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4385*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512,5205,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4386*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512,5208,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4387*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512,5208,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4388*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512,5211,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4389*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512,5211,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4390*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512,5214,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4391*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512,5214,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4392*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512,5217,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4393*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512,5220,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*4394*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512,5223,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*4395*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4396*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4520,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4397*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4398*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4399*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4400*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4401*/ XED_DEF_INST(XED_ICLASS_VDIVPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4402*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4403*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4544,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4404*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4405*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4406*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4407*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4408*/ XED_DEF_INST(XED_ICLASS_VDIVPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4409*/ XED_DEF_INST(XED_ICLASS_VDIVSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4410*/ XED_DEF_INST(XED_ICLASS_VDIVSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4564,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4411*/ XED_DEF_INST(XED_ICLASS_VDIVSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4412*/ XED_DEF_INST(XED_ICLASS_VDIVSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4413*/ XED_DEF_INST(XED_ICLASS_VDIVSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4568,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4414*/ XED_DEF_INST(XED_ICLASS_VDIVSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4415*/ XED_DEF_INST(XED_ICLASS_VEXPANDPD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512,5226,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4416*/ XED_DEF_INST(XED_ICLASS_VEXPANDPD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4417*/ XED_DEF_INST(XED_ICLASS_VEXPANDPD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512,5229,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4418*/ XED_DEF_INST(XED_ICLASS_VEXPANDPD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4419*/ XED_DEF_INST(XED_ICLASS_VEXPANDPD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512,5235,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4420*/ XED_DEF_INST(XED_ICLASS_VEXPANDPD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4421*/ XED_DEF_INST(XED_ICLASS_VEXPANDPS,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512,5241,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4422*/ XED_DEF_INST(XED_ICLASS_VEXPANDPS,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4423*/ XED_DEF_INST(XED_ICLASS_VEXPANDPS,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512,5244,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4424*/ XED_DEF_INST(XED_ICLASS_VEXPANDPS,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4425*/ XED_DEF_INST(XED_ICLASS_VEXPANDPS,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512,5247,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*4426*/ XED_DEF_INST(XED_ICLASS_VEXPANDPS,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4427*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5253,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4428*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512,5257,4,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4429*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512,5261,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4430*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512,5265,4,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4431*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5269,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4432*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512,5273,4,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4433*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512,5277,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4434*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512,5281,4,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4435*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512,5285,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4436*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512,5289,4,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4437*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512,5293,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4438*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512,5297,4,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4439*/ XED_DEF_INST(XED_ICLASS_VEXTRACTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512,5301,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*4440*/ XED_DEF_INST(XED_ICLASS_VEXTRACTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512,5304,3,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*4441*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,5307,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4442*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,5312,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4443*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,5317,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4444*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5322,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4445*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,5327,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4446*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512,5332,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4447*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512,5337,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4448*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,5342,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4449*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,5347,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4450*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,5352,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4451*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5357,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4452*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,5362,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4453*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512,5367,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4454*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512,5372,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4455*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5322,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4456*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5377,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4457*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,5382,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4458*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5357,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4459*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5387,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4460*/ XED_DEF_INST(XED_ICLASS_VFIXUPIMMSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,5392,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4461*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4462*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4463*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4464*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4465*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4466*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4467*/ XED_DEF_INST(XED_ICLASS_VFMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4468*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4469*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4470*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4471*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4472*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4473*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4474*/ XED_DEF_INST(XED_ICLASS_VFMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4475*/ XED_DEF_INST(XED_ICLASS_VFMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4476*/ XED_DEF_INST(XED_ICLASS_VFMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4477*/ XED_DEF_INST(XED_ICLASS_VFMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4478*/ XED_DEF_INST(XED_ICLASS_VFMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4479*/ XED_DEF_INST(XED_ICLASS_VFMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4480*/ XED_DEF_INST(XED_ICLASS_VFMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4481*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4482*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4483*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4484*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4485*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4486*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4487*/ XED_DEF_INST(XED_ICLASS_VFMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4488*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4489*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4490*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4491*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4492*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4493*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4494*/ XED_DEF_INST(XED_ICLASS_VFMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4495*/ XED_DEF_INST(XED_ICLASS_VFMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4496*/ XED_DEF_INST(XED_ICLASS_VFMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4497*/ XED_DEF_INST(XED_ICLASS_VFMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4498*/ XED_DEF_INST(XED_ICLASS_VFMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4499*/ XED_DEF_INST(XED_ICLASS_VFMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4500*/ XED_DEF_INST(XED_ICLASS_VFMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4501*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4502*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4503*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4504*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4505*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4506*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4507*/ XED_DEF_INST(XED_ICLASS_VFMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4508*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4509*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4510*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4511*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4512*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4513*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4514*/ XED_DEF_INST(XED_ICLASS_VFMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4515*/ XED_DEF_INST(XED_ICLASS_VFMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4516*/ XED_DEF_INST(XED_ICLASS_VFMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4517*/ XED_DEF_INST(XED_ICLASS_VFMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4518*/ XED_DEF_INST(XED_ICLASS_VFMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4519*/ XED_DEF_INST(XED_ICLASS_VFMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4520*/ XED_DEF_INST(XED_ICLASS_VFMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4521*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4522*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4523*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4524*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4525*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4526*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4527*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4528*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4529*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4530*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4531*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4532*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4533*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4534*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4535*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4536*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4537*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4538*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4539*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4540*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4541*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4542*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4543*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4544*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4545*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4546*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4547*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4548*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4549*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4550*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4551*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4552*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4553*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4554*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4555*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4556*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4557*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4558*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4559*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4560*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4561*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4562*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4563*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4564*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4565*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4566*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4567*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4568*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4569*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4570*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4571*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4572*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4573*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4574*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4575*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4576*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4577*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4578*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4579*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4580*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4581*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4582*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4583*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4584*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4585*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4586*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4587*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4588*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4589*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4590*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4591*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4592*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4593*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4594*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4595*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4596*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4597*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4598*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4599*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4600*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4601*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4602*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4603*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4604*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4605*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4606*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4607*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4608*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4609*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4610*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4611*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4612*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4613*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4614*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4615*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4616*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4617*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4618*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4619*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4620*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4621*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4622*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4623*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4624*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4625*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4626*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4627*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4628*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4629*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4630*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4631*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4632*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4633*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4634*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4635*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4636*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4637*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4638*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4639*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4640*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4641*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4642*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4643*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4644*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4645*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4646*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4647*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4648*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4649*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4650*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4651*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4652*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4653*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4654*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4655*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4656*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4657*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4658*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4659*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4660*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4661*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4662*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4663*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4664*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4665*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4666*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4667*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4668*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4669*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4670*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4671*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4672*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4673*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4674*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4675*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4676*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4677*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4678*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4679*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4680*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4681*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4682*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4683*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4684*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4685*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4686*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4687*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4688*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4689*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4690*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4691*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4692*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4693*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4694*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4695*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4696*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4697*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4698*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4699*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4700*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4701*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4702*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4703*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4704*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4705*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4706*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4707*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4708*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4709*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4710*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4711*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4712*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4713*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4714*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4715*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4716*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4717*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4718*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4719*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4720*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4721*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4722*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4723*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4724*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4725*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4726*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4727*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4728*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4729*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4730*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4731*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4732*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4733*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4734*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4735*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4736*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4737*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4738*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4739*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4740*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4741*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4742*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4743*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4744*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4745*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4746*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4747*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4748*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4749*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4750*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4751*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4752*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4753*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4754*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4755*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4756*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4757*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4758*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4759*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4760*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4761*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4762*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4763*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4764*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4765*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4766*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5401,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4767*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4768*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4769*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4770*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4771*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4772*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4773*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5429,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4774*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4775*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4776*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4777*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4778*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4779*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4780*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5453,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4781*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SD,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5457,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4782*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4783*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5461,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4784*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SS,XED_CATEGORY_VFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5465,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4785*/ XED_DEF_INST(XED_ICLASS_VGATHERDPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERDPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512,5469,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*4786*/ XED_DEF_INST(XED_ICLASS_VGATHERDPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERDPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128,5472,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*4787*/ XED_DEF_INST(XED_ICLASS_VGATHERDPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERDPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256,5475,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*4788*/ XED_DEF_INST(XED_ICLASS_VGATHERDPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERDPS_ZMMf32_MASKmskw_MEMf32_AVX512_VL512,5478,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*4789*/ XED_DEF_INST(XED_ICLASS_VGATHERDPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERDPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128,5481,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*4790*/ XED_DEF_INST(XED_ICLASS_VGATHERDPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERDPS_YMMf32_MASKmskw_MEMf32_AVX512_VL256,5484,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*4791*/ XED_DEF_INST(XED_ICLASS_VGATHERQPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERQPD_ZMMf64_MASKmskw_MEMf64_AVX512_VL512,5469,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*4792*/ XED_DEF_INST(XED_ICLASS_VGATHERQPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERQPD_XMMf64_MASKmskw_MEMf64_AVX512_VL128,5472,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*4793*/ XED_DEF_INST(XED_ICLASS_VGATHERQPD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERQPD_YMMf64_MASKmskw_MEMf64_AVX512_VL256,5475,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*4794*/ XED_DEF_INST(XED_ICLASS_VGATHERQPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERQPS_YMMf32_MASKmskw_MEMf32_AVX512_VL512,5484,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*4795*/ XED_DEF_INST(XED_ICLASS_VGATHERQPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL128,5481,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*4796*/ XED_DEF_INST(XED_ICLASS_VGATHERQPS,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGATHERQPS_XMMf32_MASKmskw_MEMf32_AVX512_VL256,5481,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*4797*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4798*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4425,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4799*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512,4428,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4800*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4801*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512,5487,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4802*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4803*/ XED_DEF_INST(XED_ICLASS_VGETEXPPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512,5490,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4804*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4805*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4434,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4806*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512,4437,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4807*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4808*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512,5493,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4809*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4810*/ XED_DEF_INST(XED_ICLASS_VGETEXPPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512,5496,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4811*/ XED_DEF_INST(XED_ICLASS_VGETEXPSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4812*/ XED_DEF_INST(XED_ICLASS_VGETEXPSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4448,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4813*/ XED_DEF_INST(XED_ICLASS_VGETEXPSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4814*/ XED_DEF_INST(XED_ICLASS_VGETEXPSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4815*/ XED_DEF_INST(XED_ICLASS_VGETEXPSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4460,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4816*/ XED_DEF_INST(XED_ICLASS_VGETEXPSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4817*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5499,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4818*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5503,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4819*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512,5507,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4820*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512,5511,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4821*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512,5515,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4822*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512,5519,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4823*/ XED_DEF_INST(XED_ICLASS_VGETMANTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512,5523,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4824*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5527,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4825*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5531,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4826*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512,5535,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4827*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512,5539,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4828*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512,5543,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4829*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512,5547,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4830*/ XED_DEF_INST(XED_ICLASS_VGETMANTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512,5551,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4831*/ XED_DEF_INST(XED_ICLASS_VGETMANTSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5555,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4832*/ XED_DEF_INST(XED_ICLASS_VGETMANTSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5560,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4833*/ XED_DEF_INST(XED_ICLASS_VGETMANTSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,5565,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4834*/ XED_DEF_INST(XED_ICLASS_VGETMANTSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5570,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4835*/ XED_DEF_INST(XED_ICLASS_VGETMANTSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5575,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4836*/ XED_DEF_INST(XED_ICLASS_VGETMANTSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,5580,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4837*/ XED_DEF_INST(XED_ICLASS_VINSERTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512,5585,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4838*/ XED_DEF_INST(XED_ICLASS_VINSERTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,5590,5,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4839*/ XED_DEF_INST(XED_ICLASS_VINSERTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512,5595,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4840*/ XED_DEF_INST(XED_ICLASS_VINSERTF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512,5600,5,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4841*/ XED_DEF_INST(XED_ICLASS_VINSERTF64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512,5605,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4842*/ XED_DEF_INST(XED_ICLASS_VINSERTF64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,5610,5,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4843*/ XED_DEF_INST(XED_ICLASS_VINSERTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512,5615,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4844*/ XED_DEF_INST(XED_ICLASS_VINSERTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,5620,5,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4845*/ XED_DEF_INST(XED_ICLASS_VINSERTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512,5625,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4846*/ XED_DEF_INST(XED_ICLASS_VINSERTI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,5630,5,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4847*/ XED_DEF_INST(XED_ICLASS_VINSERTI64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512,5635,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*4848*/ XED_DEF_INST(XED_ICLASS_VINSERTI64X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,5640,5,0,0,155,XED_EXCEPTION_AVX512_E6NF), +/*4849*/ XED_DEF_INST(XED_ICLASS_VINSERTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512,5645,4,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*4850*/ XED_DEF_INST(XED_ICLASS_VINSERTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512,5649,4,0,0,159,XED_EXCEPTION_AVX512_E9NF), +/*4851*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4852*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5653,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4853*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4854*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4855*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4856*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4857*/ XED_DEF_INST(XED_ICLASS_VMAXPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4858*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4859*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5657,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4860*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4861*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4862*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4863*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4864*/ XED_DEF_INST(XED_ICLASS_VMAXPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4865*/ XED_DEF_INST(XED_ICLASS_VMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4866*/ XED_DEF_INST(XED_ICLASS_VMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4448,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4867*/ XED_DEF_INST(XED_ICLASS_VMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4868*/ XED_DEF_INST(XED_ICLASS_VMAXSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4869*/ XED_DEF_INST(XED_ICLASS_VMAXSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4460,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4870*/ XED_DEF_INST(XED_ICLASS_VMAXSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4871*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4872*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5653,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4873*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4874*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4875*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4876*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4877*/ XED_DEF_INST(XED_ICLASS_VMINPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4878*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4879*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5657,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4880*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4881*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4882*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4883*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*4884*/ XED_DEF_INST(XED_ICLASS_VMINPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*4885*/ XED_DEF_INST(XED_ICLASS_VMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4886*/ XED_DEF_INST(XED_ICLASS_VMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4448,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4887*/ XED_DEF_INST(XED_ICLASS_VMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4888*/ XED_DEF_INST(XED_ICLASS_VMINSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4889*/ XED_DEF_INST(XED_ICLASS_VMINSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4460,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*4890*/ XED_DEF_INST(XED_ICLASS_VMINSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*4891*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4892*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512,5226,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4893*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4791,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4894*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512,4788,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4895*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4896*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512,5229,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4897*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512,4797,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4898*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512,4794,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4899*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4900*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512,5235,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4901*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512,4803,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4902*/ XED_DEF_INST(XED_ICLASS_VMOVAPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512,4800,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4903*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4904*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512,5241,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4905*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4809,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4906*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512,4806,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4907*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4908*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512,5244,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4909*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512,4815,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4910*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512,4812,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4911*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4912*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512,5247,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4913*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512,4821,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4914*/ XED_DEF_INST(XED_ICLASS_VMOVAPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512,4818,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4915*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512,5661,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*4916*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_XMMu32_GPR32u32_AVX512,5661,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*4917*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512,5663,2,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*4918*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_XMMu32_MEMu32_AVX512,5663,2,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*4919*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512,5665,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*4920*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_GPR32u32_XMMu32_AVX512,5665,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*4921*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512,5667,2,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*4922*/ XED_DEF_INST(XED_ICLASS_VMOVD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVD_MEMu32_XMMu32_AVX512,5667,2,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*4923*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,128,XED_EXCEPTION_AVX512_E5NF), +/*4924*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512,5226,3,0,0,162,XED_EXCEPTION_AVX512_E5NF), +/*4925*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,128,XED_EXCEPTION_AVX512_E5NF), +/*4926*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512,5669,3,0,0,162,XED_EXCEPTION_AVX512_E5NF), +/*4927*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,128,XED_EXCEPTION_AVX512_E5NF), +/*4928*/ XED_DEF_INST(XED_ICLASS_VMOVDDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512,5235,3,0,0,162,XED_EXCEPTION_AVX512_E5NF), +/*4929*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512,4480,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4930*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512,5672,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4931*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512,5675,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4932*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512,5678,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4933*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4934*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512,5681,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4935*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512,5684,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4936*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512,5687,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4937*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512,4492,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4938*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512,5690,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4939*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512,5693,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4940*/ XED_DEF_INST(XED_ICLASS_VMOVDQA32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512,5696,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4941*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512,4498,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4942*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512,5699,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4943*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512,5702,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4944*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512,5705,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4945*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4946*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512,5708,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4947*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512,5711,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4948*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512,5714,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4949*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512,4510,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4950*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512,5717,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4951*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512,5720,3,0,0,128,XED_EXCEPTION_AVX512_E1), +/*4952*/ XED_DEF_INST(XED_ICLASS_VMOVDQA64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512,5723,3,0,0,160,XED_EXCEPTION_AVX512_E1), +/*4953*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512,4480,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4954*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512,5672,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4955*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512,5675,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4956*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512,5678,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4957*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4958*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512,5681,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4959*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512,5684,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4960*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512,5687,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4961*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512,4492,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4962*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512,5690,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4963*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512,5693,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4964*/ XED_DEF_INST(XED_ICLASS_VMOVDQU32,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512,5696,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4965*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512,4498,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4966*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512,5699,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4967*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512,5702,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4968*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512,5705,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4969*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4970*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512,5708,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4971*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512,5711,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4972*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512,5714,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4973*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512,4510,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4974*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512,5717,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4975*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512,5720,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*4976*/ XED_DEF_INST(XED_ICLASS_VMOVDQU64,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512,5723,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*4977*/ XED_DEF_INST(XED_ICLASS_VMOVHLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512,5726,3,0,0,0,XED_EXCEPTION_AVX512_E7NM128), +/*4978*/ XED_DEF_INST(XED_ICLASS_VMOVHPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512,5729,3,0,0,164,XED_EXCEPTION_AVX512_E9NF), +/*4979*/ XED_DEF_INST(XED_ICLASS_VMOVHPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVHPD_MEMf64_XMMf64_AVX512,5732,2,0,0,164,XED_EXCEPTION_AVX512_E9NF), +/*4980*/ XED_DEF_INST(XED_ICLASS_VMOVHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512,5734,3,0,0,165,XED_EXCEPTION_AVX512_E9NF), +/*4981*/ XED_DEF_INST(XED_ICLASS_VMOVHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVHPS_MEMf32_XMMf32_AVX512,5737,2,0,0,165,XED_EXCEPTION_AVX512_E9NF), +/*4982*/ XED_DEF_INST(XED_ICLASS_VMOVLHPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512,5739,3,0,0,0,XED_EXCEPTION_AVX512_E7NM128), +/*4983*/ XED_DEF_INST(XED_ICLASS_VMOVLPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512,5742,3,0,0,164,XED_EXCEPTION_AVX512_E9NF), +/*4984*/ XED_DEF_INST(XED_ICLASS_VMOVLPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVLPD_MEMf64_XMMf64_AVX512,5745,2,0,0,164,XED_EXCEPTION_AVX512_E9NF), +/*4985*/ XED_DEF_INST(XED_ICLASS_VMOVLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512,5747,3,0,0,165,XED_EXCEPTION_AVX512_E9NF), +/*4986*/ XED_DEF_INST(XED_ICLASS_VMOVLPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVLPS_MEMf32_XMMf32_AVX512,5750,2,0,0,165,XED_EXCEPTION_AVX512_E9NF), +/*4987*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTDQ_MEMu32_ZMMu32_AVX512,5752,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4988*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTDQ_MEMu32_XMMu32_AVX512,5754,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4989*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTDQ_MEMu32_YMMu32_AVX512,5756,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4990*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTDQA_ZMMu32_MEMu32_AVX512,5758,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4991*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTDQA_XMMu32_MEMu32_AVX512,5760,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4992*/ XED_DEF_INST(XED_ICLASS_VMOVNTDQA,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTDQA_YMMu32_MEMu32_AVX512,5762,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4993*/ XED_DEF_INST(XED_ICLASS_VMOVNTPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTPD_MEMf64_ZMMf64_AVX512,5764,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4994*/ XED_DEF_INST(XED_ICLASS_VMOVNTPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTPD_MEMf64_XMMf64_AVX512,5766,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4995*/ XED_DEF_INST(XED_ICLASS_VMOVNTPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTPD_MEMf64_YMMf64_AVX512,5768,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4996*/ XED_DEF_INST(XED_ICLASS_VMOVNTPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTPS_MEMf32_ZMMf32_AVX512,5770,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4997*/ XED_DEF_INST(XED_ICLASS_VMOVNTPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTPS_MEMf32_XMMf32_AVX512,5772,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4998*/ XED_DEF_INST(XED_ICLASS_VMOVNTPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVNTPS_MEMf32_YMMf32_AVX512,5774,2,0,0,166,XED_EXCEPTION_AVX512_E1NF), +/*4999*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_XMMu64_GPR64u64_AVX512,5776,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*5000*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512,5778,2,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*5001*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_GPR64u64_XMMu64_AVX512,5780,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*5002*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512,5782,2,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*5003*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512,5784,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*5004*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_XMMu64_MEMu64_AVX512,5778,2,0,0,164,XED_EXCEPTION_AVX512_E9NF), +/*5005*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_XMMu64_XMMu64_AVX512,5786,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*5006*/ XED_DEF_INST(XED_ICLASS_VMOVQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVQ_MEMu64_XMMu64_AVX512,5782,2,0,0,164,XED_EXCEPTION_AVX512_E9NF), +/*5007*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512,5669,3,0,0,167,XED_EXCEPTION_AVX512_E5), +/*5008*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512,5788,3,0,0,167,XED_EXCEPTION_AVX512_E5), +/*5009*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,168,XED_EXCEPTION_AVX512_E5), +/*5010*/ XED_DEF_INST(XED_ICLASS_VMOVSD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5791,4,0,0,168,XED_EXCEPTION_AVX512_E5), +/*5011*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5012*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512,5241,3,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*5013*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5014*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512,5244,3,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*5015*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5016*/ XED_DEF_INST(XED_ICLASS_VMOVSHDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512,5247,3,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*5017*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5018*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512,5241,3,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*5019*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5020*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512,5244,3,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*5021*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5022*/ XED_DEF_INST(XED_ICLASS_VMOVSLDUP,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512,5247,3,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*5023*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512,4668,3,0,0,167,XED_EXCEPTION_AVX512_E5), +/*5024*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512,5795,3,0,0,167,XED_EXCEPTION_AVX512_E5), +/*5025*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,168,XED_EXCEPTION_AVX512_E5), +/*5026*/ XED_DEF_INST(XED_ICLASS_VMOVSS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5798,4,0,0,168,XED_EXCEPTION_AVX512_E5), +/*5027*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5028*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512,5226,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5029*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4791,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5030*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512,4788,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5031*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5032*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512,5229,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5033*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512,4797,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5034*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512,4794,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5035*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5036*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512,5235,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5037*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512,4803,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5038*/ XED_DEF_INST(XED_ICLASS_VMOVUPD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512,4800,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5039*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5040*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512,5241,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5041*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4809,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5042*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512,4806,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5043*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5044*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512,5244,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5045*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512,4815,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5046*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512,4812,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5047*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5048*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512,5247,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5049*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512,4821,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5050*/ XED_DEF_INST(XED_ICLASS_VMOVUPS,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512,4818,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*5051*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5052*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4520,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5053*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5054*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5055*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5056*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5057*/ XED_DEF_INST(XED_ICLASS_VMULPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5058*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5059*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4544,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5060*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5061*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5062*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5063*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5064*/ XED_DEF_INST(XED_ICLASS_VMULPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5065*/ XED_DEF_INST(XED_ICLASS_VMULSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5066*/ XED_DEF_INST(XED_ICLASS_VMULSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4564,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5067*/ XED_DEF_INST(XED_ICLASS_VMULSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5068*/ XED_DEF_INST(XED_ICLASS_VMULSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5069*/ XED_DEF_INST(XED_ICLASS_VMULSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4568,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5070*/ XED_DEF_INST(XED_ICLASS_VMULSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5071*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512,5802,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5072*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512,5805,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5073*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSD_XMMi32_MASKmskw_XMMi32_AVX512,5808,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5074*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSD_XMMi32_MASKmskw_MEMi32_AVX512,5811,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5075*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSD_YMMi32_MASKmskw_YMMi32_AVX512,5814,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5076*/ XED_DEF_INST(XED_ICLASS_VPABSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSD_YMMi32_MASKmskw_MEMi32_AVX512,5817,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5077*/ XED_DEF_INST(XED_ICLASS_VPABSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512,5820,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5078*/ XED_DEF_INST(XED_ICLASS_VPABSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512,5823,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5079*/ XED_DEF_INST(XED_ICLASS_VPABSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512,5826,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5080*/ XED_DEF_INST(XED_ICLASS_VPABSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512,5829,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5081*/ XED_DEF_INST(XED_ICLASS_VPABSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512,5832,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5082*/ XED_DEF_INST(XED_ICLASS_VPABSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512,5835,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5083*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5084*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5085*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5086*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5087*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5088*/ XED_DEF_INST(XED_ICLASS_VPADDD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5089*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5090*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5091*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5092*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5093*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5094*/ XED_DEF_INST(XED_ICLASS_VPADDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5095*/ XED_DEF_INST(XED_ICLASS_VPANDD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5096*/ XED_DEF_INST(XED_ICLASS_VPANDD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5097*/ XED_DEF_INST(XED_ICLASS_VPANDD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5098*/ XED_DEF_INST(XED_ICLASS_VPANDD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5099*/ XED_DEF_INST(XED_ICLASS_VPANDD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5100*/ XED_DEF_INST(XED_ICLASS_VPANDD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5101*/ XED_DEF_INST(XED_ICLASS_VPANDND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5102*/ XED_DEF_INST(XED_ICLASS_VPANDND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5103*/ XED_DEF_INST(XED_ICLASS_VPANDND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5104*/ XED_DEF_INST(XED_ICLASS_VPANDND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5105*/ XED_DEF_INST(XED_ICLASS_VPANDND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5106*/ XED_DEF_INST(XED_ICLASS_VPANDND,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5107*/ XED_DEF_INST(XED_ICLASS_VPANDNQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5108*/ XED_DEF_INST(XED_ICLASS_VPANDNQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5109*/ XED_DEF_INST(XED_ICLASS_VPANDNQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5110*/ XED_DEF_INST(XED_ICLASS_VPANDNQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5111*/ XED_DEF_INST(XED_ICLASS_VPANDNQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5112*/ XED_DEF_INST(XED_ICLASS_VPANDNQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5113*/ XED_DEF_INST(XED_ICLASS_VPANDQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5114*/ XED_DEF_INST(XED_ICLASS_VPANDQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5115*/ XED_DEF_INST(XED_ICLASS_VPANDQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5116*/ XED_DEF_INST(XED_ICLASS_VPANDQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5117*/ XED_DEF_INST(XED_ICLASS_VPANDQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5118*/ XED_DEF_INST(XED_ICLASS_VPANDQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5119*/ XED_DEF_INST(XED_ICLASS_VPBLENDMD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*5120*/ XED_DEF_INST(XED_ICLASS_VPBLENDMD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*5121*/ XED_DEF_INST(XED_ICLASS_VPBLENDMD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*5122*/ XED_DEF_INST(XED_ICLASS_VPBLENDMD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*5123*/ XED_DEF_INST(XED_ICLASS_VPBLENDMD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*5124*/ XED_DEF_INST(XED_ICLASS_VPBLENDMD,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*5125*/ XED_DEF_INST(XED_ICLASS_VPBLENDMQ,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*5126*/ XED_DEF_INST(XED_ICLASS_VPBLENDMQ,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*5127*/ XED_DEF_INST(XED_ICLASS_VPBLENDMQ,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*5128*/ XED_DEF_INST(XED_ICLASS_VPBLENDMQ,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*5129*/ XED_DEF_INST(XED_ICLASS_VPBLENDMQ,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*5130*/ XED_DEF_INST(XED_ICLASS_VPBLENDMQ,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,143,XED_EXCEPTION_AVX512_E4), +/*5131*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512,5886,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*5132*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512,5889,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*5133*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512,5892,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5134*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512,5892,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5135*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512,5895,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*5136*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*5137*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512,5898,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5138*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512,5898,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5139*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512,5901,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*5140*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512,5904,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*5141*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512,5907,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5142*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTD,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512,5907,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5143*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512,5910,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*5144*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512,5913,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*5145*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512,5916,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5146*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512,5919,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*5147*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*5148*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512,5922,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5149*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512,5925,3,0,0,145,XED_EXCEPTION_AVX512_E6), +/*5150*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512,5928,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*5151*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTQ,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512,5931,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*5152*/ XED_DEF_INST(XED_ICLASS_VPCMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512,5934,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5153*/ XED_DEF_INST(XED_ICLASS_VPCMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512,5939,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5154*/ XED_DEF_INST(XED_ICLASS_VPCMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512,5944,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5155*/ XED_DEF_INST(XED_ICLASS_VPCMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512,5949,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5156*/ XED_DEF_INST(XED_ICLASS_VPCMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512,5954,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5157*/ XED_DEF_INST(XED_ICLASS_VPCMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512,5959,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5158*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512,5964,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5159*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512,5968,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5160*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512,5972,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5161*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512,5976,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5162*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512,5980,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5163*/ XED_DEF_INST(XED_ICLASS_VPCMPEQD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512,5984,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5164*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512,5988,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5165*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512,5992,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5166*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512,5996,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5167*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512,6000,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5168*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512,6004,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5169*/ XED_DEF_INST(XED_ICLASS_VPCMPEQQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512,6008,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5170*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512,6012,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5171*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512,6016,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5172*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512,6020,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5173*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512,6024,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5174*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512,6028,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5175*/ XED_DEF_INST(XED_ICLASS_VPCMPGTD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512,6032,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5176*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512,6036,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5177*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512,6040,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5178*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512,6044,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5179*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512,6048,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5180*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512,6052,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5181*/ XED_DEF_INST(XED_ICLASS_VPCMPGTQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512,6056,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5182*/ XED_DEF_INST(XED_ICLASS_VPCMPQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512,6060,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5183*/ XED_DEF_INST(XED_ICLASS_VPCMPQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512,6065,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5184*/ XED_DEF_INST(XED_ICLASS_VPCMPQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512,6070,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5185*/ XED_DEF_INST(XED_ICLASS_VPCMPQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512,6075,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5186*/ XED_DEF_INST(XED_ICLASS_VPCMPQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512,6080,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5187*/ XED_DEF_INST(XED_ICLASS_VPCMPQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512,6085,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5188*/ XED_DEF_INST(XED_ICLASS_VPCMPUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512,6090,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5189*/ XED_DEF_INST(XED_ICLASS_VPCMPUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,6095,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5190*/ XED_DEF_INST(XED_ICLASS_VPCMPUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512,6100,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5191*/ XED_DEF_INST(XED_ICLASS_VPCMPUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512,6105,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5192*/ XED_DEF_INST(XED_ICLASS_VPCMPUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512,6110,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5193*/ XED_DEF_INST(XED_ICLASS_VPCMPUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,6115,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5194*/ XED_DEF_INST(XED_ICLASS_VPCMPUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512,6120,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5195*/ XED_DEF_INST(XED_ICLASS_VPCMPUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,6125,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5196*/ XED_DEF_INST(XED_ICLASS_VPCMPUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512,6130,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5197*/ XED_DEF_INST(XED_ICLASS_VPCMPUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512,6135,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5198*/ XED_DEF_INST(XED_ICLASS_VPCMPUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512,6140,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5199*/ XED_DEF_INST(XED_ICLASS_VPCMPUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,6145,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5200*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512,5678,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5201*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512,5675,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5202*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512,5687,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5203*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512,5684,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5204*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512,5696,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5205*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSD,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512,5693,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5206*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSQ,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512,5705,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5207*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSQ,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512,5702,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5208*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSQ,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512,5714,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5209*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSQ,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512,5711,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5210*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSQ,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512,5723,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5211*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSQ,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512,5720,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5212*/ XED_DEF_INST(XED_ICLASS_VPERMD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5213*/ XED_DEF_INST(XED_ICLASS_VPERMD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5214*/ XED_DEF_INST(XED_ICLASS_VPERMD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5215*/ XED_DEF_INST(XED_ICLASS_VPERMD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5216*/ XED_DEF_INST(XED_ICLASS_VPERMI2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,6150,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5217*/ XED_DEF_INST(XED_ICLASS_VPERMI2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6154,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5218*/ XED_DEF_INST(XED_ICLASS_VPERMI2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,6158,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5219*/ XED_DEF_INST(XED_ICLASS_VPERMI2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6162,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5220*/ XED_DEF_INST(XED_ICLASS_VPERMI2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,6166,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5221*/ XED_DEF_INST(XED_ICLASS_VPERMI2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6170,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5222*/ XED_DEF_INST(XED_ICLASS_VPERMI2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5223*/ XED_DEF_INST(XED_ICLASS_VPERMI2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5224*/ XED_DEF_INST(XED_ICLASS_VPERMI2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5225*/ XED_DEF_INST(XED_ICLASS_VPERMI2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5226*/ XED_DEF_INST(XED_ICLASS_VPERMI2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5227*/ XED_DEF_INST(XED_ICLASS_VPERMI2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5228*/ XED_DEF_INST(XED_ICLASS_VPERMI2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5229*/ XED_DEF_INST(XED_ICLASS_VPERMI2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5230*/ XED_DEF_INST(XED_ICLASS_VPERMI2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5231*/ XED_DEF_INST(XED_ICLASS_VPERMI2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5232*/ XED_DEF_INST(XED_ICLASS_VPERMI2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5233*/ XED_DEF_INST(XED_ICLASS_VPERMI2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5234*/ XED_DEF_INST(XED_ICLASS_VPERMI2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,6174,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5235*/ XED_DEF_INST(XED_ICLASS_VPERMI2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6178,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5236*/ XED_DEF_INST(XED_ICLASS_VPERMI2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,6182,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5237*/ XED_DEF_INST(XED_ICLASS_VPERMI2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6186,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5238*/ XED_DEF_INST(XED_ICLASS_VPERMI2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,6190,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5239*/ XED_DEF_INST(XED_ICLASS_VPERMI2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6194,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5240*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5499,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5241*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512,5507,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5242*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5243*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5244*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512,5511,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5245*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512,5515,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5246*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5247*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5248*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512,5519,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5249*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512,5523,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5250*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5251*/ XED_DEF_INST(XED_ICLASS_VPERMILPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5252*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5527,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5253*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512,5535,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5254*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5255*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5256*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512,5539,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5257*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512,5543,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5258*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5259*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5260*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512,5547,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5261*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512,5551,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5262*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5263*/ XED_DEF_INST(XED_ICLASS_VPERMILPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5264*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5499,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5265*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512,5507,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5266*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5267*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5268*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512,5519,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5269*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512,5523,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5270*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5271*/ XED_DEF_INST(XED_ICLASS_VPERMPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5272*/ XED_DEF_INST(XED_ICLASS_VPERMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5273*/ XED_DEF_INST(XED_ICLASS_VPERMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5274*/ XED_DEF_INST(XED_ICLASS_VPERMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5275*/ XED_DEF_INST(XED_ICLASS_VPERMPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5276*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512,6198,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5277*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512,6202,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5278*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5279*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5280*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512,6206,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5281*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512,6210,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5282*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5283*/ XED_DEF_INST(XED_ICLASS_VPERMQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5284*/ XED_DEF_INST(XED_ICLASS_VPERMT2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,6150,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5285*/ XED_DEF_INST(XED_ICLASS_VPERMT2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6154,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5286*/ XED_DEF_INST(XED_ICLASS_VPERMT2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,6158,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5287*/ XED_DEF_INST(XED_ICLASS_VPERMT2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6162,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5288*/ XED_DEF_INST(XED_ICLASS_VPERMT2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,6166,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5289*/ XED_DEF_INST(XED_ICLASS_VPERMT2D,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6170,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5290*/ XED_DEF_INST(XED_ICLASS_VPERMT2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,5397,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5291*/ XED_DEF_INST(XED_ICLASS_VPERMT2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,5405,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5292*/ XED_DEF_INST(XED_ICLASS_VPERMT2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,5409,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5293*/ XED_DEF_INST(XED_ICLASS_VPERMT2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,5413,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5294*/ XED_DEF_INST(XED_ICLASS_VPERMT2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,5417,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5295*/ XED_DEF_INST(XED_ICLASS_VPERMT2PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,5421,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5296*/ XED_DEF_INST(XED_ICLASS_VPERMT2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,5425,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5297*/ XED_DEF_INST(XED_ICLASS_VPERMT2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,5433,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5298*/ XED_DEF_INST(XED_ICLASS_VPERMT2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,5437,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5299*/ XED_DEF_INST(XED_ICLASS_VPERMT2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,5441,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5300*/ XED_DEF_INST(XED_ICLASS_VPERMT2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,5445,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5301*/ XED_DEF_INST(XED_ICLASS_VPERMT2PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,5449,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5302*/ XED_DEF_INST(XED_ICLASS_VPERMT2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,6174,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5303*/ XED_DEF_INST(XED_ICLASS_VPERMT2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6178,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5304*/ XED_DEF_INST(XED_ICLASS_VPERMT2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,6182,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5305*/ XED_DEF_INST(XED_ICLASS_VPERMT2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6186,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5306*/ XED_DEF_INST(XED_ICLASS_VPERMT2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,6190,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5307*/ XED_DEF_INST(XED_ICLASS_VPERMT2Q,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6194,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5308*/ XED_DEF_INST(XED_ICLASS_VPEXPANDD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512,5672,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5309*/ XED_DEF_INST(XED_ICLASS_VPEXPANDD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512,4480,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5310*/ XED_DEF_INST(XED_ICLASS_VPEXPANDD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512,5681,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5311*/ XED_DEF_INST(XED_ICLASS_VPEXPANDD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5312*/ XED_DEF_INST(XED_ICLASS_VPEXPANDD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512,5690,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5313*/ XED_DEF_INST(XED_ICLASS_VPEXPANDD,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512,4492,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5314*/ XED_DEF_INST(XED_ICLASS_VPEXPANDQ,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512,5699,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5315*/ XED_DEF_INST(XED_ICLASS_VPEXPANDQ,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512,4498,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5316*/ XED_DEF_INST(XED_ICLASS_VPEXPANDQ,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512,5708,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5317*/ XED_DEF_INST(XED_ICLASS_VPEXPANDQ,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5318*/ XED_DEF_INST(XED_ICLASS_VPEXPANDQ,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512,5717,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*5319*/ XED_DEF_INST(XED_ICLASS_VPEXPANDQ,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512,4510,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5320*/ XED_DEF_INST(XED_ICLASS_VPGATHERDD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERDD_ZMMu32_MASKmskw_MEMu32_AVX512_VL512,6214,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*5321*/ XED_DEF_INST(XED_ICLASS_VPGATHERDD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERDD_XMMu32_MASKmskw_MEMu32_AVX512_VL128,6217,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*5322*/ XED_DEF_INST(XED_ICLASS_VPGATHERDD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERDD_YMMu32_MASKmskw_MEMu32_AVX512_VL256,6220,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*5323*/ XED_DEF_INST(XED_ICLASS_VPGATHERDQ,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512,6223,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*5324*/ XED_DEF_INST(XED_ICLASS_VPGATHERDQ,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128,6226,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*5325*/ XED_DEF_INST(XED_ICLASS_VPGATHERDQ,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256,6229,3,0,0,157,XED_EXCEPTION_AVX512_E12), +/*5326*/ XED_DEF_INST(XED_ICLASS_VPGATHERQD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERQD_YMMu32_MASKmskw_MEMu32_AVX512_VL512,6220,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*5327*/ XED_DEF_INST(XED_ICLASS_VPGATHERQD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL128,6217,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*5328*/ XED_DEF_INST(XED_ICLASS_VPGATHERQD,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERQD_XMMu32_MASKmskw_MEMu32_AVX512_VL256,6217,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*5329*/ XED_DEF_INST(XED_ICLASS_VPGATHERQQ,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERQQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512,6223,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*5330*/ XED_DEF_INST(XED_ICLASS_VPGATHERQQ,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERQQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128,6226,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*5331*/ XED_DEF_INST(XED_ICLASS_VPGATHERQQ,XED_CATEGORY_GATHER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPGATHERQQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256,6229,3,0,0,158,XED_EXCEPTION_AVX512_E12), +/*5332*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512,6232,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5333*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512,6236,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5334*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512,6240,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5335*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512,6244,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5336*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512,6248,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5337*/ XED_DEF_INST(XED_ICLASS_VPMAXSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512,6252,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5338*/ XED_DEF_INST(XED_ICLASS_VPMAXSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512,6256,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5339*/ XED_DEF_INST(XED_ICLASS_VPMAXSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512,6260,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5340*/ XED_DEF_INST(XED_ICLASS_VPMAXSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512,6264,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5341*/ XED_DEF_INST(XED_ICLASS_VPMAXSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512,6268,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5342*/ XED_DEF_INST(XED_ICLASS_VPMAXSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512,6272,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5343*/ XED_DEF_INST(XED_ICLASS_VPMAXSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512,6276,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5344*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5345*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5346*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5347*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5348*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5349*/ XED_DEF_INST(XED_ICLASS_VPMAXUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5350*/ XED_DEF_INST(XED_ICLASS_VPMAXUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5351*/ XED_DEF_INST(XED_ICLASS_VPMAXUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5352*/ XED_DEF_INST(XED_ICLASS_VPMAXUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5353*/ XED_DEF_INST(XED_ICLASS_VPMAXUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5354*/ XED_DEF_INST(XED_ICLASS_VPMAXUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5355*/ XED_DEF_INST(XED_ICLASS_VPMAXUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5356*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512,6232,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5357*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512,6236,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5358*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512,6240,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5359*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512,6244,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5360*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512,6248,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5361*/ XED_DEF_INST(XED_ICLASS_VPMINSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512,6252,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5362*/ XED_DEF_INST(XED_ICLASS_VPMINSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512,6256,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5363*/ XED_DEF_INST(XED_ICLASS_VPMINSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512,6260,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5364*/ XED_DEF_INST(XED_ICLASS_VPMINSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512,6264,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5365*/ XED_DEF_INST(XED_ICLASS_VPMINSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512,6268,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5366*/ XED_DEF_INST(XED_ICLASS_VPMINSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512,6272,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5367*/ XED_DEF_INST(XED_ICLASS_VPMINSQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512,6276,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5368*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5369*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5370*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5371*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5372*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5373*/ XED_DEF_INST(XED_ICLASS_VPMINUD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5374*/ XED_DEF_INST(XED_ICLASS_VPMINUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5375*/ XED_DEF_INST(XED_ICLASS_VPMINUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5376*/ XED_DEF_INST(XED_ICLASS_VPMINUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5377*/ XED_DEF_INST(XED_ICLASS_VPMINUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5378*/ XED_DEF_INST(XED_ICLASS_VPMINUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5379*/ XED_DEF_INST(XED_ICLASS_VPMINUQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5380*/ XED_DEF_INST(XED_ICLASS_VPMOVDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512,6280,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5381*/ XED_DEF_INST(XED_ICLASS_VPMOVDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512,6283,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5382*/ XED_DEF_INST(XED_ICLASS_VPMOVDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512,6286,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5383*/ XED_DEF_INST(XED_ICLASS_VPMOVDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512,6289,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5384*/ XED_DEF_INST(XED_ICLASS_VPMOVDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512,6292,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5385*/ XED_DEF_INST(XED_ICLASS_VPMOVDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512,6295,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5386*/ XED_DEF_INST(XED_ICLASS_VPMOVDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512,6298,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5387*/ XED_DEF_INST(XED_ICLASS_VPMOVDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512,6301,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5388*/ XED_DEF_INST(XED_ICLASS_VPMOVDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512,6304,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5389*/ XED_DEF_INST(XED_ICLASS_VPMOVDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512,6307,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5390*/ XED_DEF_INST(XED_ICLASS_VPMOVDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512,6310,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5391*/ XED_DEF_INST(XED_ICLASS_VPMOVDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512,6313,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5392*/ XED_DEF_INST(XED_ICLASS_VPMOVQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512,6316,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5393*/ XED_DEF_INST(XED_ICLASS_VPMOVQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512,6319,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5394*/ XED_DEF_INST(XED_ICLASS_VPMOVQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512,6322,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5395*/ XED_DEF_INST(XED_ICLASS_VPMOVQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512,6325,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5396*/ XED_DEF_INST(XED_ICLASS_VPMOVQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512,6328,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5397*/ XED_DEF_INST(XED_ICLASS_VPMOVQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512,6331,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5398*/ XED_DEF_INST(XED_ICLASS_VPMOVQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512,6334,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5399*/ XED_DEF_INST(XED_ICLASS_VPMOVQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512,6337,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5400*/ XED_DEF_INST(XED_ICLASS_VPMOVQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512,6340,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5401*/ XED_DEF_INST(XED_ICLASS_VPMOVQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512,6343,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5402*/ XED_DEF_INST(XED_ICLASS_VPMOVQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512,6346,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5403*/ XED_DEF_INST(XED_ICLASS_VPMOVQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512,6349,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5404*/ XED_DEF_INST(XED_ICLASS_VPMOVQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512,6352,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5405*/ XED_DEF_INST(XED_ICLASS_VPMOVQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512,6355,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5406*/ XED_DEF_INST(XED_ICLASS_VPMOVQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512,6358,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5407*/ XED_DEF_INST(XED_ICLASS_VPMOVQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512,6361,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5408*/ XED_DEF_INST(XED_ICLASS_VPMOVQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512,6364,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5409*/ XED_DEF_INST(XED_ICLASS_VPMOVQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512,6367,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5410*/ XED_DEF_INST(XED_ICLASS_VPMOVSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512,6370,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5411*/ XED_DEF_INST(XED_ICLASS_VPMOVSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512,6373,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5412*/ XED_DEF_INST(XED_ICLASS_VPMOVSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512,6376,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5413*/ XED_DEF_INST(XED_ICLASS_VPMOVSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512,6379,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5414*/ XED_DEF_INST(XED_ICLASS_VPMOVSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512,6382,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5415*/ XED_DEF_INST(XED_ICLASS_VPMOVSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512,6385,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5416*/ XED_DEF_INST(XED_ICLASS_VPMOVSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512,6388,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5417*/ XED_DEF_INST(XED_ICLASS_VPMOVSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512,6391,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5418*/ XED_DEF_INST(XED_ICLASS_VPMOVSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512,6394,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5419*/ XED_DEF_INST(XED_ICLASS_VPMOVSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512,6397,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5420*/ XED_DEF_INST(XED_ICLASS_VPMOVSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512,6400,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5421*/ XED_DEF_INST(XED_ICLASS_VPMOVSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512,6403,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5422*/ XED_DEF_INST(XED_ICLASS_VPMOVSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512,6406,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5423*/ XED_DEF_INST(XED_ICLASS_VPMOVSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512,6409,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5424*/ XED_DEF_INST(XED_ICLASS_VPMOVSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512,6412,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5425*/ XED_DEF_INST(XED_ICLASS_VPMOVSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512,6415,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5426*/ XED_DEF_INST(XED_ICLASS_VPMOVSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512,6418,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5427*/ XED_DEF_INST(XED_ICLASS_VPMOVSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512,6421,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5428*/ XED_DEF_INST(XED_ICLASS_VPMOVSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512,6424,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5429*/ XED_DEF_INST(XED_ICLASS_VPMOVSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512,6427,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5430*/ XED_DEF_INST(XED_ICLASS_VPMOVSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512,6430,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5431*/ XED_DEF_INST(XED_ICLASS_VPMOVSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512,6433,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5432*/ XED_DEF_INST(XED_ICLASS_VPMOVSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512,6436,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5433*/ XED_DEF_INST(XED_ICLASS_VPMOVSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512,6439,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5434*/ XED_DEF_INST(XED_ICLASS_VPMOVSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512,6442,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5435*/ XED_DEF_INST(XED_ICLASS_VPMOVSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512,6445,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5436*/ XED_DEF_INST(XED_ICLASS_VPMOVSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512,6448,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5437*/ XED_DEF_INST(XED_ICLASS_VPMOVSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512,6451,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5438*/ XED_DEF_INST(XED_ICLASS_VPMOVSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512,6454,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5439*/ XED_DEF_INST(XED_ICLASS_VPMOVSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512,6457,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5440*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512,6460,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5441*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512,6463,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5442*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512,6466,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5443*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512,6469,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5444*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512,6472,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5445*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512,6475,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5446*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512,6478,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5447*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512,6481,3,0,0,172,XED_EXCEPTION_AVX512_E5), +/*5448*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512,6484,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5449*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512,6487,3,0,0,172,XED_EXCEPTION_AVX512_E5), +/*5450*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512,6490,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5451*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512,6493,3,0,0,172,XED_EXCEPTION_AVX512_E5), +/*5452*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512,6496,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5453*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512,6499,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5454*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512,6502,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5455*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512,6505,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5456*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512,6508,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5457*/ XED_DEF_INST(XED_ICLASS_VPMOVSXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512,6511,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5458*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512,6514,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5459*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512,6517,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5460*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512,6520,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5461*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512,6523,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5462*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512,6526,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5463*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512,6529,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5464*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512,6532,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5465*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512,6535,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5466*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512,6538,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5467*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512,6541,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5468*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512,6544,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5469*/ XED_DEF_INST(XED_ICLASS_VPMOVSXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512,6547,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5470*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512,6280,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5471*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512,6283,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5472*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512,6286,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5473*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512,6289,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5474*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512,6292,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5475*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512,6295,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5476*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512,6298,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5477*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512,6301,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5478*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512,6304,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5479*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512,6307,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5480*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512,6310,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5481*/ XED_DEF_INST(XED_ICLASS_VPMOVUSDW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512,6313,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5482*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512,6316,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5483*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512,6319,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5484*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512,6322,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5485*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512,6325,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5486*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512,6328,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5487*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512,6331,3,0,0,172,XED_EXCEPTION_AVX512_E6), +/*5488*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512,6334,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5489*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512,6337,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5490*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512,6340,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5491*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512,6343,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5492*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512,6346,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5493*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512,6349,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*5494*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512,6352,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5495*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512,6355,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5496*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512,6358,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5497*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512,6361,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5498*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512,6364,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*5499*/ XED_DEF_INST(XED_ICLASS_VPMOVUSQW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512,6367,3,0,0,170,XED_EXCEPTION_AVX512_E6), +/*5500*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512,6460,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5501*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512,6463,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5502*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512,6466,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5503*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512,6469,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5504*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512,6472,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5505*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512,6475,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5506*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512,6478,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5507*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512,6481,3,0,0,172,XED_EXCEPTION_AVX512_E5), +/*5508*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512,6484,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5509*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512,6487,3,0,0,172,XED_EXCEPTION_AVX512_E5), +/*5510*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512,6490,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5511*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512,6493,3,0,0,172,XED_EXCEPTION_AVX512_E5), +/*5512*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512,6496,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5513*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512,6499,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5514*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512,6502,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5515*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512,6505,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5516*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512,6508,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5517*/ XED_DEF_INST(XED_ICLASS_VPMOVZXDQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512,6511,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5518*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512,6514,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5519*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512,6517,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5520*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512,6520,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5521*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512,6523,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5522*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512,6526,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5523*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWD,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512,6529,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*5524*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512,6532,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5525*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512,6535,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5526*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512,6538,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5527*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512,6541,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5528*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512,6544,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*5529*/ XED_DEF_INST(XED_ICLASS_VPMOVZXWQ,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512,6547,3,0,0,170,XED_EXCEPTION_AVX512_E5), +/*5530*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512,6256,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5531*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512,6260,4,0,0,173,XED_EXCEPTION_AVX512_E4), +/*5532*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512,6264,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5533*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512,6268,4,0,0,173,XED_EXCEPTION_AVX512_E4), +/*5534*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512,6272,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5535*/ XED_DEF_INST(XED_ICLASS_VPMULDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512,6276,4,0,0,173,XED_EXCEPTION_AVX512_E4), +/*5536*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5537*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5538*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5539*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5540*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5541*/ XED_DEF_INST(XED_ICLASS_VPMULLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5542*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5543*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512,5866,4,0,0,173,XED_EXCEPTION_AVX512_E4), +/*5544*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5545*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512,5874,4,0,0,173,XED_EXCEPTION_AVX512_E4), +/*5546*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5547*/ XED_DEF_INST(XED_ICLASS_VPMULUDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512,5882,4,0,0,173,XED_EXCEPTION_AVX512_E4), +/*5548*/ XED_DEF_INST(XED_ICLASS_VPORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5549*/ XED_DEF_INST(XED_ICLASS_VPORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5550*/ XED_DEF_INST(XED_ICLASS_VPORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5551*/ XED_DEF_INST(XED_ICLASS_VPORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5552*/ XED_DEF_INST(XED_ICLASS_VPORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5553*/ XED_DEF_INST(XED_ICLASS_VPORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5554*/ XED_DEF_INST(XED_ICLASS_VPORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5555*/ XED_DEF_INST(XED_ICLASS_VPORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5556*/ XED_DEF_INST(XED_ICLASS_VPORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5557*/ XED_DEF_INST(XED_ICLASS_VPORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5558*/ XED_DEF_INST(XED_ICLASS_VPORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5559*/ XED_DEF_INST(XED_ICLASS_VPORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5560*/ XED_DEF_INST(XED_ICLASS_VPROLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512,6550,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5561*/ XED_DEF_INST(XED_ICLASS_VPROLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512,6554,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5562*/ XED_DEF_INST(XED_ICLASS_VPROLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512,6558,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5563*/ XED_DEF_INST(XED_ICLASS_VPROLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512,6562,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5564*/ XED_DEF_INST(XED_ICLASS_VPROLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512,6566,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5565*/ XED_DEF_INST(XED_ICLASS_VPROLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512,6570,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5566*/ XED_DEF_INST(XED_ICLASS_VPROLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512,6574,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5567*/ XED_DEF_INST(XED_ICLASS_VPROLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512,6578,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5568*/ XED_DEF_INST(XED_ICLASS_VPROLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512,6582,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5569*/ XED_DEF_INST(XED_ICLASS_VPROLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512,6586,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5570*/ XED_DEF_INST(XED_ICLASS_VPROLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512,6590,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5571*/ XED_DEF_INST(XED_ICLASS_VPROLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512,6594,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5572*/ XED_DEF_INST(XED_ICLASS_VPROLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5573*/ XED_DEF_INST(XED_ICLASS_VPROLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5574*/ XED_DEF_INST(XED_ICLASS_VPROLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5575*/ XED_DEF_INST(XED_ICLASS_VPROLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5576*/ XED_DEF_INST(XED_ICLASS_VPROLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5577*/ XED_DEF_INST(XED_ICLASS_VPROLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5578*/ XED_DEF_INST(XED_ICLASS_VPROLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5579*/ XED_DEF_INST(XED_ICLASS_VPROLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5580*/ XED_DEF_INST(XED_ICLASS_VPROLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5581*/ XED_DEF_INST(XED_ICLASS_VPROLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5582*/ XED_DEF_INST(XED_ICLASS_VPROLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5583*/ XED_DEF_INST(XED_ICLASS_VPROLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5584*/ XED_DEF_INST(XED_ICLASS_VPRORD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512,6550,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5585*/ XED_DEF_INST(XED_ICLASS_VPRORD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512,6554,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5586*/ XED_DEF_INST(XED_ICLASS_VPRORD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512,6558,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5587*/ XED_DEF_INST(XED_ICLASS_VPRORD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512,6562,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5588*/ XED_DEF_INST(XED_ICLASS_VPRORD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512,6566,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5589*/ XED_DEF_INST(XED_ICLASS_VPRORD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512,6570,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5590*/ XED_DEF_INST(XED_ICLASS_VPRORQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512,6574,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5591*/ XED_DEF_INST(XED_ICLASS_VPRORQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512,6578,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5592*/ XED_DEF_INST(XED_ICLASS_VPRORQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512,6582,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5593*/ XED_DEF_INST(XED_ICLASS_VPRORQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512,6586,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5594*/ XED_DEF_INST(XED_ICLASS_VPRORQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512,6590,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5595*/ XED_DEF_INST(XED_ICLASS_VPRORQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512,6594,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5596*/ XED_DEF_INST(XED_ICLASS_VPRORVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5597*/ XED_DEF_INST(XED_ICLASS_VPRORVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5598*/ XED_DEF_INST(XED_ICLASS_VPRORVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5599*/ XED_DEF_INST(XED_ICLASS_VPRORVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5600*/ XED_DEF_INST(XED_ICLASS_VPRORVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5601*/ XED_DEF_INST(XED_ICLASS_VPRORVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5602*/ XED_DEF_INST(XED_ICLASS_VPRORVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5603*/ XED_DEF_INST(XED_ICLASS_VPRORVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5604*/ XED_DEF_INST(XED_ICLASS_VPRORVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5605*/ XED_DEF_INST(XED_ICLASS_VPRORVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5606*/ XED_DEF_INST(XED_ICLASS_VPRORVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5607*/ XED_DEF_INST(XED_ICLASS_VPRORVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5608*/ XED_DEF_INST(XED_ICLASS_VPSCATTERDD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_ZMMu32_AVX512_VL512,6598,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5609*/ XED_DEF_INST(XED_ICLASS_VPSCATTERDD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_XMMu32_AVX512_VL128,6601,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5610*/ XED_DEF_INST(XED_ICLASS_VPSCATTERDD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERDD_MEMu32_MASKmskw_YMMu32_AVX512_VL256,6604,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5611*/ XED_DEF_INST(XED_ICLASS_VPSCATTERDQ,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512,6607,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5612*/ XED_DEF_INST(XED_ICLASS_VPSCATTERDQ,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128,6610,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5613*/ XED_DEF_INST(XED_ICLASS_VPSCATTERDQ,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERDQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256,6613,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5614*/ XED_DEF_INST(XED_ICLASS_VPSCATTERQD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_YMMu32_AVX512_VL512,6604,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5615*/ XED_DEF_INST(XED_ICLASS_VPSCATTERQD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL128,6601,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5616*/ XED_DEF_INST(XED_ICLASS_VPSCATTERQD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERQD_MEMu32_MASKmskw_XMMu32_AVX512_VL256,6601,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5617*/ XED_DEF_INST(XED_ICLASS_VPSCATTERQQ,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_ZMMu64_AVX512_VL512,6607,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5618*/ XED_DEF_INST(XED_ICLASS_VPSCATTERQQ,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_XMMu64_AVX512_VL128,6610,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5619*/ XED_DEF_INST(XED_ICLASS_VPSCATTERQQ,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSCATTERQQ_MEMu64_MASKmskw_YMMu64_AVX512_VL256,6613,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5620*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512,6616,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5621*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512,6620,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5622*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512,6624,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5623*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512,6628,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5624*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512,6632,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5625*/ XED_DEF_INST(XED_ICLASS_VPSHUFD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512,6636,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5626*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512,6640,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5627*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6644,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5628*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512,6550,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5629*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512,6554,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5630*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5631*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6648,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5632*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512,6558,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5633*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512,6562,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5634*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512,6652,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5635*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6656,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5636*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512,6566,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5637*/ XED_DEF_INST(XED_ICLASS_VPSLLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512,6570,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5638*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512,6660,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5639*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6664,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5640*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512,6574,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5641*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512,6578,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5642*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5643*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6668,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5644*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512,6582,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5645*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512,6586,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5646*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512,6672,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5647*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6676,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5648*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512,6590,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5649*/ XED_DEF_INST(XED_ICLASS_VPSLLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512,6594,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5650*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5651*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5652*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5653*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5654*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5655*/ XED_DEF_INST(XED_ICLASS_VPSLLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5656*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5657*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5658*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5659*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5660*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5661*/ XED_DEF_INST(XED_ICLASS_VPSLLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5662*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512,6640,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5663*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6644,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5664*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512,6550,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5665*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512,6554,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5666*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5667*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6648,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5668*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512,6558,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5669*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512,6562,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5670*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512,6652,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5671*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6656,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5672*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512,6566,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5673*/ XED_DEF_INST(XED_ICLASS_VPSRAD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512,6570,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5674*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512,6660,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5675*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6664,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5676*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512,6574,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5677*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512,6578,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5678*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5679*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6668,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5680*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512,6582,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5681*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512,6586,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5682*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512,6672,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5683*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6676,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5684*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512,6590,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5685*/ XED_DEF_INST(XED_ICLASS_VPSRAQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512,6594,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5686*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5687*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5688*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5689*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5690*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5691*/ XED_DEF_INST(XED_ICLASS_VPSRAVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5692*/ XED_DEF_INST(XED_ICLASS_VPSRAVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5693*/ XED_DEF_INST(XED_ICLASS_VPSRAVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5694*/ XED_DEF_INST(XED_ICLASS_VPSRAVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5695*/ XED_DEF_INST(XED_ICLASS_VPSRAVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5696*/ XED_DEF_INST(XED_ICLASS_VPSRAVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5697*/ XED_DEF_INST(XED_ICLASS_VPSRAVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5698*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512,6640,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5699*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6644,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5700*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512,6550,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5701*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512,6554,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5702*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5703*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6648,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5704*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512,6558,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5705*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512,6562,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5706*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512,6652,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5707*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6656,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5708*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512,6566,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5709*/ XED_DEF_INST(XED_ICLASS_VPSRLD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512,6570,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5710*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512,6660,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5711*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6664,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5712*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512,6574,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5713*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512,6578,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5714*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5715*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6668,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5716*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512,6582,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5717*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512,6586,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5718*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512,6672,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5719*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6676,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*5720*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512,6590,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5721*/ XED_DEF_INST(XED_ICLASS_VPSRLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512,6594,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5722*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5723*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5724*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5725*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5726*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5727*/ XED_DEF_INST(XED_ICLASS_VPSRLVD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5728*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5729*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5730*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5731*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5732*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5733*/ XED_DEF_INST(XED_ICLASS_VPSRLVQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5734*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5735*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5736*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5737*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5738*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5739*/ XED_DEF_INST(XED_ICLASS_VPSUBD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5740*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5741*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5742*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5743*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5744*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5745*/ XED_DEF_INST(XED_ICLASS_VPSUBQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5746*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512,6680,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5747*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,6685,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5748*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512,6690,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5749*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512,6695,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5750*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512,6700,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5751*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,6705,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5752*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512,6710,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5753*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,6715,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5754*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512,6720,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5755*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512,6725,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5756*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512,6730,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5757*/ XED_DEF_INST(XED_ICLASS_VPTERNLOGQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,6735,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5758*/ XED_DEF_INST(XED_ICLASS_VPTESTMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512,5964,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5759*/ XED_DEF_INST(XED_ICLASS_VPTESTMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512,5968,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5760*/ XED_DEF_INST(XED_ICLASS_VPTESTMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512,5972,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5761*/ XED_DEF_INST(XED_ICLASS_VPTESTMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512,5976,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5762*/ XED_DEF_INST(XED_ICLASS_VPTESTMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512,5980,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5763*/ XED_DEF_INST(XED_ICLASS_VPTESTMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512,5984,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5764*/ XED_DEF_INST(XED_ICLASS_VPTESTMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512,5988,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5765*/ XED_DEF_INST(XED_ICLASS_VPTESTMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512,5992,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5766*/ XED_DEF_INST(XED_ICLASS_VPTESTMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512,5996,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5767*/ XED_DEF_INST(XED_ICLASS_VPTESTMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512,6000,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5768*/ XED_DEF_INST(XED_ICLASS_VPTESTMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512,6004,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5769*/ XED_DEF_INST(XED_ICLASS_VPTESTMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512,6008,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5770*/ XED_DEF_INST(XED_ICLASS_VPTESTNMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512,5964,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5771*/ XED_DEF_INST(XED_ICLASS_VPTESTNMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512,5968,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5772*/ XED_DEF_INST(XED_ICLASS_VPTESTNMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512,5972,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5773*/ XED_DEF_INST(XED_ICLASS_VPTESTNMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512,5976,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5774*/ XED_DEF_INST(XED_ICLASS_VPTESTNMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512,5980,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5775*/ XED_DEF_INST(XED_ICLASS_VPTESTNMD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512,5984,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5776*/ XED_DEF_INST(XED_ICLASS_VPTESTNMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512,5988,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5777*/ XED_DEF_INST(XED_ICLASS_VPTESTNMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512,5992,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5778*/ XED_DEF_INST(XED_ICLASS_VPTESTNMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512,5996,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5779*/ XED_DEF_INST(XED_ICLASS_VPTESTNMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512,6000,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5780*/ XED_DEF_INST(XED_ICLASS_VPTESTNMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512,6004,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5781*/ XED_DEF_INST(XED_ICLASS_VPTESTNMQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512,6008,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5782*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5783*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5784*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5785*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5786*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5787*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5788*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5789*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5790*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5791*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5792*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5793*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5794*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5795*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5796*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5797*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5798*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5799*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5800*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5801*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5802*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5803*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5804*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5805*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLQDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5806*/ XED_DEF_INST(XED_ICLASS_VPXORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5807*/ XED_DEF_INST(XED_ICLASS_VPXORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5808*/ XED_DEF_INST(XED_ICLASS_VPXORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5809*/ XED_DEF_INST(XED_ICLASS_VPXORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5810*/ XED_DEF_INST(XED_ICLASS_VPXORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5811*/ XED_DEF_INST(XED_ICLASS_VPXORD,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5812*/ XED_DEF_INST(XED_ICLASS_VPXORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5813*/ XED_DEF_INST(XED_ICLASS_VPXORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5814*/ XED_DEF_INST(XED_ICLASS_VPXORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5815*/ XED_DEF_INST(XED_ICLASS_VPXORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5816*/ XED_DEF_INST(XED_ICLASS_VPXORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*5817*/ XED_DEF_INST(XED_ICLASS_VPXORQ,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*5818*/ XED_DEF_INST(XED_ICLASS_VRCP14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5819*/ XED_DEF_INST(XED_ICLASS_VRCP14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512,4428,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5820*/ XED_DEF_INST(XED_ICLASS_VRCP14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5821*/ XED_DEF_INST(XED_ICLASS_VRCP14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512,5487,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5822*/ XED_DEF_INST(XED_ICLASS_VRCP14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5823*/ XED_DEF_INST(XED_ICLASS_VRCP14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512,5490,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5824*/ XED_DEF_INST(XED_ICLASS_VRCP14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5825*/ XED_DEF_INST(XED_ICLASS_VRCP14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512,4437,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5826*/ XED_DEF_INST(XED_ICLASS_VRCP14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5827*/ XED_DEF_INST(XED_ICLASS_VRCP14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512,5493,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5828*/ XED_DEF_INST(XED_ICLASS_VRCP14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5829*/ XED_DEF_INST(XED_ICLASS_VRCP14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512,5496,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5830*/ XED_DEF_INST(XED_ICLASS_VRCP14SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E10), +/*5831*/ XED_DEF_INST(XED_ICLASS_VRCP14SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E10), +/*5832*/ XED_DEF_INST(XED_ICLASS_VRCP14SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E10), +/*5833*/ XED_DEF_INST(XED_ICLASS_VRCP14SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E10), +/*5834*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5499,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5835*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5503,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5836*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512,5507,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5837*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512,5511,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5838*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512,5515,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5839*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512,5519,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5840*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512,5523,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5841*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5527,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5842*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5531,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5843*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512,5535,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5844*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512,5539,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5845*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512,5543,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5846*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512,5547,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5847*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512,5551,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5848*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5555,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5849*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5560,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5850*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,5565,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5851*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5570,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5852*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5575,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5853*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,5580,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5854*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5855*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512,4428,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5856*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5857*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512,5487,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5858*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5859*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512,5490,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5860*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5861*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512,4437,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5862*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5863*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512,5493,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5864*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,131,XED_EXCEPTION_AVX512_E4), +/*5865*/ XED_DEF_INST(XED_ICLASS_VRSQRT14PS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512,5496,3,0,0,132,XED_EXCEPTION_AVX512_E4), +/*5866*/ XED_DEF_INST(XED_ICLASS_VRSQRT14SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E10), +/*5867*/ XED_DEF_INST(XED_ICLASS_VRSQRT14SD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E10), +/*5868*/ XED_DEF_INST(XED_ICLASS_VRSQRT14SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E10), +/*5869*/ XED_DEF_INST(XED_ICLASS_VRSQRT14SS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E10), +/*5870*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5871*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4520,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5872*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5873*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5874*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5875*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5876*/ XED_DEF_INST(XED_ICLASS_VSCALEFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5877*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5878*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4544,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5879*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5880*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5881*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5882*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5883*/ XED_DEF_INST(XED_ICLASS_VSCALEFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5884*/ XED_DEF_INST(XED_ICLASS_VSCALEFSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5885*/ XED_DEF_INST(XED_ICLASS_VSCALEFSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4564,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5886*/ XED_DEF_INST(XED_ICLASS_VSCALEFSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5887*/ XED_DEF_INST(XED_ICLASS_VSCALEFSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5888*/ XED_DEF_INST(XED_ICLASS_VSCALEFSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4568,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5889*/ XED_DEF_INST(XED_ICLASS_VSCALEFSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5890*/ XED_DEF_INST(XED_ICLASS_VSCATTERDPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512,6740,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5891*/ XED_DEF_INST(XED_ICLASS_VSCATTERDPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128,6743,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5892*/ XED_DEF_INST(XED_ICLASS_VSCATTERDPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERDPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256,6746,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5893*/ XED_DEF_INST(XED_ICLASS_VSCATTERDPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_ZMMf32_AVX512_VL512,6749,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5894*/ XED_DEF_INST(XED_ICLASS_VSCATTERDPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128,6752,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5895*/ XED_DEF_INST(XED_ICLASS_VSCATTERDPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERDPS_MEMf32_MASKmskw_YMMf32_AVX512_VL256,6755,3,0,0,174,XED_EXCEPTION_AVX512_E12), +/*5896*/ XED_DEF_INST(XED_ICLASS_VSCATTERQPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_ZMMf64_AVX512_VL512,6740,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5897*/ XED_DEF_INST(XED_ICLASS_VSCATTERQPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_XMMf64_AVX512_VL128,6743,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5898*/ XED_DEF_INST(XED_ICLASS_VSCATTERQPD,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERQPD_MEMf64_MASKmskw_YMMf64_AVX512_VL256,6746,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5899*/ XED_DEF_INST(XED_ICLASS_VSCATTERQPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_YMMf32_AVX512_VL512,6755,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5900*/ XED_DEF_INST(XED_ICLASS_VSCATTERQPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL128,6752,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5901*/ XED_DEF_INST(XED_ICLASS_VSCATTERQPS,XED_CATEGORY_SCATTER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCATTERQPS_MEMf32_MASKmskw_XMMf32_AVX512_VL256,6752,3,0,0,175,XED_EXCEPTION_AVX512_E12), +/*5902*/ XED_DEF_INST(XED_ICLASS_VSHUFF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,6758,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5903*/ XED_DEF_INST(XED_ICLASS_VSHUFF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,6763,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5904*/ XED_DEF_INST(XED_ICLASS_VSHUFF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512,6768,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5905*/ XED_DEF_INST(XED_ICLASS_VSHUFF32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512,6773,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5906*/ XED_DEF_INST(XED_ICLASS_VSHUFF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,6778,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5907*/ XED_DEF_INST(XED_ICLASS_VSHUFF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,6783,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5908*/ XED_DEF_INST(XED_ICLASS_VSHUFF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512,6788,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5909*/ XED_DEF_INST(XED_ICLASS_VSHUFF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512,6793,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5910*/ XED_DEF_INST(XED_ICLASS_VSHUFI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512,4572,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5911*/ XED_DEF_INST(XED_ICLASS_VSHUFI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,4577,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5912*/ XED_DEF_INST(XED_ICLASS_VSHUFI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512,4592,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5913*/ XED_DEF_INST(XED_ICLASS_VSHUFI32X4,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,4597,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5914*/ XED_DEF_INST(XED_ICLASS_VSHUFI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512,4602,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5915*/ XED_DEF_INST(XED_ICLASS_VSHUFI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,4607,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5916*/ XED_DEF_INST(XED_ICLASS_VSHUFI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512,4622,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5917*/ XED_DEF_INST(XED_ICLASS_VSHUFI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,4627,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5918*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,6778,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5919*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,6783,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5920*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5555,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5921*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,6798,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5922*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512,6788,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5923*/ XED_DEF_INST(XED_ICLASS_VSHUFPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512,6793,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5924*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,6758,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5925*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,6763,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5926*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5570,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5927*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,6803,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5928*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512,6768,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5929*/ XED_DEF_INST(XED_ICLASS_VSHUFPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512,6773,5,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5930*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512,4422,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5931*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512,6808,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5932*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512,4428,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5933*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512,5232,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5934*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512,5487,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5935*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512,5238,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5936*/ XED_DEF_INST(XED_ICLASS_VSQRTPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512,5490,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5937*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512,4431,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5938*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512,6811,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5939*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512,4437,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5940*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512,4671,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5941*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512,5493,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5942*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512,5250,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5943*/ XED_DEF_INST(XED_ICLASS_VSQRTPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512,5496,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5944*/ XED_DEF_INST(XED_ICLASS_VSQRTSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5945*/ XED_DEF_INST(XED_ICLASS_VSQRTSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4564,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5946*/ XED_DEF_INST(XED_ICLASS_VSQRTSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5947*/ XED_DEF_INST(XED_ICLASS_VSQRTSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5948*/ XED_DEF_INST(XED_ICLASS_VSQRTSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4568,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5949*/ XED_DEF_INST(XED_ICLASS_VSQRTSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5950*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5951*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4520,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5952*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5953*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5954*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5955*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5956*/ XED_DEF_INST(XED_ICLASS_VSUBPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5957*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5958*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4544,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5959*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5960*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5961*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5962*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*5963*/ XED_DEF_INST(XED_ICLASS_VSUBPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*5964*/ XED_DEF_INST(XED_ICLASS_VSUBSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5965*/ XED_DEF_INST(XED_ICLASS_VSUBSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4564,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5966*/ XED_DEF_INST(XED_ICLASS_VSUBSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4452,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5967*/ XED_DEF_INST(XED_ICLASS_VSUBSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5968*/ XED_DEF_INST(XED_ICLASS_VSUBSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4568,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*5969*/ XED_DEF_INST(XED_ICLASS_VSUBSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4464,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*5970*/ XED_DEF_INST(XED_ICLASS_VUCOMISD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512,4770,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*5971*/ XED_DEF_INST(XED_ICLASS_VUCOMISD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISD_XMMf64_XMMf64_AVX512,4773,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*5972*/ XED_DEF_INST(XED_ICLASS_VUCOMISD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISD_XMMf64_MEMf64_AVX512,4776,3,97,0,146,XED_EXCEPTION_AVX512_E3NF), +/*5973*/ XED_DEF_INST(XED_ICLASS_VUCOMISS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512,4779,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*5974*/ XED_DEF_INST(XED_ICLASS_VUCOMISS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISS_XMMf32_XMMf32_AVX512,4782,3,97,0,83,XED_EXCEPTION_AVX512_E3NF), +/*5975*/ XED_DEF_INST(XED_ICLASS_VUCOMISS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISS_XMMf32_MEMf32_AVX512,4785,3,97,0,146,XED_EXCEPTION_AVX512_E3NF), +/*5976*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5977*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5978*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5979*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5980*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5981*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5982*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5983*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5984*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5985*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5986*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5987*/ XED_DEF_INST(XED_ICLASS_VUNPCKHPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5988*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512,4516,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5989*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512,4524,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5990*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512,4444,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5991*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512,4528,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5992*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512,4532,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5993*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512,4536,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5994*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512,4540,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5995*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512,4548,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5996*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512,4456,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5997*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512,4552,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*5998*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512,4556,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*5999*/ XED_DEF_INST(XED_ICLASS_VUNPCKLPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512,4560,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6000*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTMB2Q,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD,6814,2,0,0,0,XED_EXCEPTION_AVX512_E6NF), +/*6001*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTMB2Q,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512,6816,2,0,0,0,XED_EXCEPTION_AVX512_E6NF), +/*6002*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTMB2Q,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512,6818,2,0,0,0,XED_EXCEPTION_AVX512_E6NF), +/*6003*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTMW2D,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD,6820,2,0,0,0,XED_EXCEPTION_AVX512_E6NF), +/*6004*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTMW2D,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTMW2D_XMMu32_MASKu32_AVX512,6822,2,0,0,0,XED_EXCEPTION_AVX512_E6NF), +/*6005*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTMW2D,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTMW2D_YMMu32_MASKu32_AVX512,6824,2,0,0,0,XED_EXCEPTION_AVX512_E6NF), +/*6006*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD,4480,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6007*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD,4483,3,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6008*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6009*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512,4489,3,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6010*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512,4492,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6011*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512,4495,3,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6012*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD,4498,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6013*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD,4501,3,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6014*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6015*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512,4507,3,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6016*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512,4510,3,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6017*/ XED_DEF_INST(XED_ICLASS_VPCONFLICTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512,4513,3,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6018*/ XED_DEF_INST(XED_ICLASS_VPLZCNTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD,4480,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6019*/ XED_DEF_INST(XED_ICLASS_VPLZCNTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD,4483,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6020*/ XED_DEF_INST(XED_ICLASS_VPLZCNTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6021*/ XED_DEF_INST(XED_ICLASS_VPLZCNTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512,4489,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6022*/ XED_DEF_INST(XED_ICLASS_VPLZCNTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512,4492,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6023*/ XED_DEF_INST(XED_ICLASS_VPLZCNTD,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512,4495,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6024*/ XED_DEF_INST(XED_ICLASS_VPLZCNTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD,4498,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6025*/ XED_DEF_INST(XED_ICLASS_VPLZCNTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD,4501,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6026*/ XED_DEF_INST(XED_ICLASS_VPLZCNTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512,4504,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6027*/ XED_DEF_INST(XED_ICLASS_VPLZCNTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512,4507,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6028*/ XED_DEF_INST(XED_ICLASS_VPLZCNTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512,4510,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6029*/ XED_DEF_INST(XED_ICLASS_VPLZCNTQ,XED_CATEGORY_CONFLICT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512,4513,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6030*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6031*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6032*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6033*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6034*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6035*/ XED_DEF_INST(XED_ICLASS_VANDNPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6036*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6037*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6038*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6039*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6040*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6041*/ XED_DEF_INST(XED_ICLASS_VANDNPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6042*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6043*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6044*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6045*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6046*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6047*/ XED_DEF_INST(XED_ICLASS_VANDPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6048*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6049*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6050*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6051*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6052*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6053*/ XED_DEF_INST(XED_ICLASS_VANDPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6054*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512,4677,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6055*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512,6826,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6056*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512,4665,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6057*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512,6829,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6058*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF32X8,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512,6832,3,0,0,178,XED_EXCEPTION_AVX512_E6), +/*6059*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF64X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512,6835,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6060*/ XED_DEF_INST(XED_ICLASS_VBROADCASTF64X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512,6838,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6061*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512,4486,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6062*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512,6841,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6063*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512,5904,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6064*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512,6844,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6065*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512,5889,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6066*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512,6847,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6067*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI32X8,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512,6850,3,0,0,178,XED_EXCEPTION_AVX512_E6), +/*6068*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI64X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512,6853,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6069*/ XED_DEF_INST(XED_ICLASS_VBROADCASTI64X2,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512,6856,3,0,0,177,XED_EXCEPTION_AVX512_E6), +/*6070*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512,6859,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6071*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512,6862,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6072*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512,6865,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6073*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512,6868,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6074*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512,6871,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6075*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512,6874,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6076*/ XED_DEF_INST(XED_ICLASS_VCVTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512,6877,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6077*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512,6880,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6078*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512,6883,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6079*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512,6886,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6080*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512,6889,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6081*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512,6892,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6082*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512,6895,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6083*/ XED_DEF_INST(XED_ICLASS_VCVTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512,6898,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6084*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512,6901,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6085*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512,6904,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6086*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512,6907,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6087*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512,6910,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6088*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512,6913,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6089*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512,6916,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6090*/ XED_DEF_INST(XED_ICLASS_VCVTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512,6919,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6091*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512,6922,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6092*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512,6925,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6093*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512,6928,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6094*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512,6931,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6095*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512,6934,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6096*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512,6937,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6097*/ XED_DEF_INST(XED_ICLASS_VCVTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512,6940,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6098*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512,6859,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6099*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512,6862,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6100*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512,6865,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6101*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512,6868,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6102*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512,6871,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6103*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512,6874,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6104*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512,6877,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6105*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128,6943,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6106*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128,6946,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6107*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256,6949,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6108*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256,6946,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6109*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512,6952,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6110*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512,6955,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6111*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512,6958,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6112*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512,6859,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6113*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512,6862,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6114*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512,6865,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6115*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512,6868,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6116*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512,6871,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6117*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512,6961,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6118*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512,6877,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6119*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512,6880,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6120*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512,6883,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6121*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512,6886,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6122*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512,6889,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6123*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512,6892,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6124*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512,6964,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6125*/ XED_DEF_INST(XED_ICLASS_VCVTTPD2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512,6898,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6126*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512,6901,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6127*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512,6904,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6128*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512,6907,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6129*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512,6910,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6130*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512,6913,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6131*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512,6967,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6132*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512,6919,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6133*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512,6922,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6134*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512,6925,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6135*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512,6928,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6136*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512,6931,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6137*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512,6934,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6138*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512,6970,3,0,0,131,XED_EXCEPTION_AVX512_E3), +/*6139*/ XED_DEF_INST(XED_ICLASS_VCVTTPS2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512,6940,3,0,0,150,XED_EXCEPTION_AVX512_E3), +/*6140*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512,6973,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6141*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512,6976,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6142*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512,6979,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6143*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512,6982,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6144*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512,6985,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6145*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512,6988,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6146*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512,6991,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6147*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128,6943,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6148*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128,6946,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6149*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256,6949,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6150*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256,6946,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6151*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512,6952,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6152*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512,6955,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6153*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512,6958,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6154*/ XED_DEF_INST(XED_ICLASS_VDBPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512,6994,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6155*/ XED_DEF_INST(XED_ICLASS_VDBPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512,6999,5,0,0,169,XED_EXCEPTION_AVX512_E4), +/*6156*/ XED_DEF_INST(XED_ICLASS_VDBPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512,7004,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6157*/ XED_DEF_INST(XED_ICLASS_VDBPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512,7009,5,0,0,169,XED_EXCEPTION_AVX512_E4), +/*6158*/ XED_DEF_INST(XED_ICLASS_VDBPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512,7014,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6159*/ XED_DEF_INST(XED_ICLASS_VDBPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512,7019,5,0,0,169,XED_EXCEPTION_AVX512_E4), +/*6160*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512,7024,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6161*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512,7028,4,0,0,179,XED_EXCEPTION_AVX512_E6NF), +/*6162*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512,7032,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6163*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512,7036,4,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6164*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512,7040,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6165*/ XED_DEF_INST(XED_ICLASS_VEXTRACTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512,7044,4,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6166*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512,7048,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6167*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512,7052,4,0,0,179,XED_EXCEPTION_AVX512_E6NF), +/*6168*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512,7056,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6169*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512,7060,4,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6170*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512,7064,4,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6171*/ XED_DEF_INST(XED_ICLASS_VEXTRACTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512,7068,4,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6172*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512,7072,4,0,0,131,XED_EXCEPTION_AVX512_E4), +/*6173*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128,7076,4,0,0,132,XED_EXCEPTION_AVX512_E4), +/*6174*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512,7080,4,0,0,131,XED_EXCEPTION_AVX512_E4), +/*6175*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256,7076,4,0,0,132,XED_EXCEPTION_AVX512_E4), +/*6176*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512,7084,4,0,0,131,XED_EXCEPTION_AVX512_E4), +/*6177*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512,7076,4,0,0,132,XED_EXCEPTION_AVX512_E4), +/*6178*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512,7088,4,0,0,131,XED_EXCEPTION_AVX512_E4), +/*6179*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128,7092,4,0,0,132,XED_EXCEPTION_AVX512_E4), +/*6180*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512,7096,4,0,0,131,XED_EXCEPTION_AVX512_E4), +/*6181*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256,7092,4,0,0,132,XED_EXCEPTION_AVX512_E4), +/*6182*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512,7100,4,0,0,131,XED_EXCEPTION_AVX512_E4), +/*6183*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512,7092,4,0,0,132,XED_EXCEPTION_AVX512_E4), +/*6184*/ XED_DEF_INST(XED_ICLASS_VFPCLASSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512,7072,4,0,0,135,XED_EXCEPTION_AVX512_E6), +/*6185*/ XED_DEF_INST(XED_ICLASS_VFPCLASSSD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512,7104,4,0,0,136,XED_EXCEPTION_AVX512_E6), +/*6186*/ XED_DEF_INST(XED_ICLASS_VFPCLASSSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512,7088,4,0,0,135,XED_EXCEPTION_AVX512_E6), +/*6187*/ XED_DEF_INST(XED_ICLASS_VFPCLASSSS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512,7108,4,0,0,136,XED_EXCEPTION_AVX512_E6), +/*6188*/ XED_DEF_INST(XED_ICLASS_VINSERTF32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512,7112,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6189*/ XED_DEF_INST(XED_ICLASS_VINSERTF32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,7117,5,0,0,179,XED_EXCEPTION_AVX512_E6NF), +/*6190*/ XED_DEF_INST(XED_ICLASS_VINSERTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512,7122,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6191*/ XED_DEF_INST(XED_ICLASS_VINSERTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512,7127,5,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6192*/ XED_DEF_INST(XED_ICLASS_VINSERTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512,7132,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6193*/ XED_DEF_INST(XED_ICLASS_VINSERTF64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,7137,5,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6194*/ XED_DEF_INST(XED_ICLASS_VINSERTI32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512,7142,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6195*/ XED_DEF_INST(XED_ICLASS_VINSERTI32X8,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,7147,5,0,0,179,XED_EXCEPTION_AVX512_E6NF), +/*6196*/ XED_DEF_INST(XED_ICLASS_VINSERTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512,7152,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6197*/ XED_DEF_INST(XED_ICLASS_VINSERTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,7157,5,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6198*/ XED_DEF_INST(XED_ICLASS_VINSERTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512,7162,5,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6199*/ XED_DEF_INST(XED_ICLASS_VINSERTI64X2,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,7167,5,0,0,180,XED_EXCEPTION_AVX512_E6NF), +/*6200*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512,7172,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6201*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512,7175,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6202*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512,7178,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6203*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512,7181,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6204*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512,7184,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6205*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512,7187,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6206*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512,7190,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6207*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512,7193,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6208*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512,7196,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6209*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512,7199,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6210*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512,7202,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6211*/ XED_DEF_INST(XED_ICLASS_VMOVDQU16,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512,7205,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6212*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512,7208,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6213*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512,7211,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6214*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512,7214,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6215*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512,7217,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6216*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512,7220,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6217*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512,7223,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6218*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512,7226,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6219*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512,7229,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6220*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512,7232,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6221*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512,7235,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6222*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512,7238,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6223*/ XED_DEF_INST(XED_ICLASS_VMOVDQU8,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512,7241,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6224*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6225*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6226*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6227*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6228*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6229*/ XED_DEF_INST(XED_ICLASS_VORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6230*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6231*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6232*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6233*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6234*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6235*/ XED_DEF_INST(XED_ICLASS_VORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6236*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSB_XMMi8_MASKmskw_XMMi8_AVX512,7244,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6237*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSB_XMMi8_MASKmskw_MEMi8_AVX512,7247,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6238*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSB_YMMi8_MASKmskw_YMMi8_AVX512,7250,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6239*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSB_YMMi8_MASKmskw_MEMi8_AVX512,7253,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6240*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512,7256,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6241*/ XED_DEF_INST(XED_ICLASS_VPABSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512,7259,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6242*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSW_XMMi16_MASKmskw_XMMi16_AVX512,7262,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6243*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSW_XMMi16_MASKmskw_MEMi16_AVX512,7265,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6244*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSW_YMMi16_MASKmskw_YMMi16_AVX512,7268,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6245*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSW_YMMi16_MASKmskw_MEMi16_AVX512,7271,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6246*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512,7274,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6247*/ XED_DEF_INST(XED_ICLASS_VPABSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512,7277,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6248*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512,7280,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6249*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512,7284,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6250*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512,7288,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6251*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512,7292,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6252*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512,7296,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6253*/ XED_DEF_INST(XED_ICLASS_VPACKSSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512,7300,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6254*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512,7304,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6255*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512,7308,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6256*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512,7312,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6257*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512,7316,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6258*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512,7320,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6259*/ XED_DEF_INST(XED_ICLASS_VPACKSSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512,7324,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6260*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512,7328,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6261*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512,7332,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6262*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512,7336,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6263*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512,7340,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6264*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512,7344,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6265*/ XED_DEF_INST(XED_ICLASS_VPACKUSDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512,7348,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6266*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512,7352,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6267*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512,7356,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6268*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512,7360,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6269*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512,7364,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6270*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512,7368,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6271*/ XED_DEF_INST(XED_ICLASS_VPACKUSWB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512,7372,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6272*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6273*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6274*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6275*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6276*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6277*/ XED_DEF_INST(XED_ICLASS_VPADDB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6278*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512,7400,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6279*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512,7404,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6280*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512,7408,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6281*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512,7412,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6282*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512,7416,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6283*/ XED_DEF_INST(XED_ICLASS_VPADDSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512,7420,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6284*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512,7424,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6285*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512,7428,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6286*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512,7432,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6287*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512,7436,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6288*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512,7440,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6289*/ XED_DEF_INST(XED_ICLASS_VPADDSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512,7444,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6290*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6291*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6292*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6293*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6294*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6295*/ XED_DEF_INST(XED_ICLASS_VPADDUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6296*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6297*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6298*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6299*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6300*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6301*/ XED_DEF_INST(XED_ICLASS_VPADDUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6302*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6303*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6304*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6305*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6306*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6307*/ XED_DEF_INST(XED_ICLASS_VPADDW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6308*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512,7472,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6309*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512,7477,5,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6310*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512,7482,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6311*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512,7487,5,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6312*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512,7492,5,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6313*/ XED_DEF_INST(XED_ICLASS_VPALIGNR,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512,7497,5,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6314*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6315*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6316*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6317*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6318*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6319*/ XED_DEF_INST(XED_ICLASS_VPAVGB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6320*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6321*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6322*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6323*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6324*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6325*/ XED_DEF_INST(XED_ICLASS_VPAVGW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6326*/ XED_DEF_INST(XED_ICLASS_VPBLENDMB,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*6327*/ XED_DEF_INST(XED_ICLASS_VPBLENDMB,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,181,XED_EXCEPTION_AVX512_E4), +/*6328*/ XED_DEF_INST(XED_ICLASS_VPBLENDMB,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*6329*/ XED_DEF_INST(XED_ICLASS_VPBLENDMB,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,181,XED_EXCEPTION_AVX512_E4), +/*6330*/ XED_DEF_INST(XED_ICLASS_VPBLENDMB,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*6331*/ XED_DEF_INST(XED_ICLASS_VPBLENDMB,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,181,XED_EXCEPTION_AVX512_E4), +/*6332*/ XED_DEF_INST(XED_ICLASS_VPBLENDMW,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*6333*/ XED_DEF_INST(XED_ICLASS_VPBLENDMW,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,181,XED_EXCEPTION_AVX512_E4), +/*6334*/ XED_DEF_INST(XED_ICLASS_VPBLENDMW,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*6335*/ XED_DEF_INST(XED_ICLASS_VPBLENDMW,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,181,XED_EXCEPTION_AVX512_E4), +/*6336*/ XED_DEF_INST(XED_ICLASS_VPBLENDMW,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,142,XED_EXCEPTION_AVX512_E4), +/*6337*/ XED_DEF_INST(XED_ICLASS_VPBLENDMW,XED_CATEGORY_BLEND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,181,XED_EXCEPTION_AVX512_E4), +/*6338*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512,7208,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6339*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512,7502,3,0,0,182,XED_EXCEPTION_AVX512_E6), +/*6340*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512,7505,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*6341*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512,7508,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6342*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512,7511,3,0,0,182,XED_EXCEPTION_AVX512_E6), +/*6343*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512,7514,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*6344*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512,7517,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6345*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512,7520,3,0,0,182,XED_EXCEPTION_AVX512_E6), +/*6346*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTB,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512,7523,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*6347*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512,7172,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6348*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512,7526,3,0,0,183,XED_EXCEPTION_AVX512_E6), +/*6349*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512,7529,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*6350*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512,7532,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6351*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512,7535,3,0,0,183,XED_EXCEPTION_AVX512_E6), +/*6352*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512,7538,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*6353*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512,7541,3,0,0,128,XED_EXCEPTION_AVX512_E6), +/*6354*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512,7544,3,0,0,183,XED_EXCEPTION_AVX512_E6), +/*6355*/ XED_DEF_INST(XED_ICLASS_VPBROADCASTW,XED_CATEGORY_BROADCAST,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512,7547,3,0,0,128,XED_EXCEPTION_AVX512_E7NM), +/*6356*/ XED_DEF_INST(XED_ICLASS_VPCMPB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512,7550,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6357*/ XED_DEF_INST(XED_ICLASS_VPCMPB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512,7555,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6358*/ XED_DEF_INST(XED_ICLASS_VPCMPB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512,7560,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6359*/ XED_DEF_INST(XED_ICLASS_VPCMPB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512,7565,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6360*/ XED_DEF_INST(XED_ICLASS_VPCMPB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512,7570,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6361*/ XED_DEF_INST(XED_ICLASS_VPCMPB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512,7575,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6362*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512,7580,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6363*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512,7584,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6364*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512,7588,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6365*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512,7592,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6366*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512,7596,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6367*/ XED_DEF_INST(XED_ICLASS_VPCMPEQB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512,7600,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6368*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512,7604,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6369*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512,7608,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6370*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512,7612,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6371*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512,7616,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6372*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512,7620,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6373*/ XED_DEF_INST(XED_ICLASS_VPCMPEQW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512,7624,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6374*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512,7580,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6375*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512,7584,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6376*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512,7588,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6377*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512,7592,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6378*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512,7596,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6379*/ XED_DEF_INST(XED_ICLASS_VPCMPGTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512,7600,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6380*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512,7604,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6381*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512,7608,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6382*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512,7612,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6383*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512,7616,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6384*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512,7620,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6385*/ XED_DEF_INST(XED_ICLASS_VPCMPGTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512,7624,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6386*/ XED_DEF_INST(XED_ICLASS_VPCMPUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512,7628,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6387*/ XED_DEF_INST(XED_ICLASS_VPCMPUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512,7633,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6388*/ XED_DEF_INST(XED_ICLASS_VPCMPUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512,7638,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6389*/ XED_DEF_INST(XED_ICLASS_VPCMPUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512,7643,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6390*/ XED_DEF_INST(XED_ICLASS_VPCMPUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512,7648,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6391*/ XED_DEF_INST(XED_ICLASS_VPCMPUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512,7653,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6392*/ XED_DEF_INST(XED_ICLASS_VPCMPUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512,7658,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6393*/ XED_DEF_INST(XED_ICLASS_VPCMPUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512,7663,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6394*/ XED_DEF_INST(XED_ICLASS_VPCMPUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512,7668,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6395*/ XED_DEF_INST(XED_ICLASS_VPCMPUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512,7673,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6396*/ XED_DEF_INST(XED_ICLASS_VPCMPUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512,7678,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6397*/ XED_DEF_INST(XED_ICLASS_VPCMPUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512,7683,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6398*/ XED_DEF_INST(XED_ICLASS_VPCMPW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512,7688,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6399*/ XED_DEF_INST(XED_ICLASS_VPCMPW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512,7693,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6400*/ XED_DEF_INST(XED_ICLASS_VPCMPW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512,7698,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6401*/ XED_DEF_INST(XED_ICLASS_VPCMPW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512,7703,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6402*/ XED_DEF_INST(XED_ICLASS_VPCMPW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512,7708,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6403*/ XED_DEF_INST(XED_ICLASS_VPCMPW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512,7713,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6404*/ XED_DEF_INST(XED_ICLASS_VPERMI2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7718,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6405*/ XED_DEF_INST(XED_ICLASS_VPERMI2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7722,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6406*/ XED_DEF_INST(XED_ICLASS_VPERMI2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7726,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6407*/ XED_DEF_INST(XED_ICLASS_VPERMI2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7730,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6408*/ XED_DEF_INST(XED_ICLASS_VPERMI2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7734,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6409*/ XED_DEF_INST(XED_ICLASS_VPERMI2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7738,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6410*/ XED_DEF_INST(XED_ICLASS_VPERMT2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7718,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6411*/ XED_DEF_INST(XED_ICLASS_VPERMT2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7722,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6412*/ XED_DEF_INST(XED_ICLASS_VPERMT2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7726,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6413*/ XED_DEF_INST(XED_ICLASS_VPERMT2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7730,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6414*/ XED_DEF_INST(XED_ICLASS_VPERMT2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7734,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6415*/ XED_DEF_INST(XED_ICLASS_VPERMT2W,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7738,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6416*/ XED_DEF_INST(XED_ICLASS_VPERMW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6417*/ XED_DEF_INST(XED_ICLASS_VPERMW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6418*/ XED_DEF_INST(XED_ICLASS_VPERMW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6419*/ XED_DEF_INST(XED_ICLASS_VPERMW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6420*/ XED_DEF_INST(XED_ICLASS_VPERMW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6421*/ XED_DEF_INST(XED_ICLASS_VPERMW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6422*/ XED_DEF_INST(XED_ICLASS_VPEXTRB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512,7742,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6423*/ XED_DEF_INST(XED_ICLASS_VPEXTRB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRB_MEMu8_XMMu8_IMM8_AVX512,7745,3,0,0,184,XED_EXCEPTION_AVX512_E9NF), +/*6424*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512,7748,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6425*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512,7748,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6426*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512,7751,3,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*6427*/ XED_DEF_INST(XED_ICLASS_VPEXTRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRD_MEMu32_XMMu32_IMM8_AVX512,7751,3,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*6428*/ XED_DEF_INST(XED_ICLASS_VPEXTRQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512,7754,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6429*/ XED_DEF_INST(XED_ICLASS_VPEXTRQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512,7757,3,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*6430*/ XED_DEF_INST(XED_ICLASS_VPEXTRW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512,7760,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6431*/ XED_DEF_INST(XED_ICLASS_VPEXTRW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRW_MEMu16_XMMu16_IMM8_AVX512,7763,3,0,0,185,XED_EXCEPTION_AVX512_E9NF), +/*6432*/ XED_DEF_INST(XED_ICLASS_VPEXTRW_C5,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5,7766,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6433*/ XED_DEF_INST(XED_ICLASS_VPEXTRW_C5,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5,7766,3,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6434*/ XED_DEF_INST(XED_ICLASS_VPINSRB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512,7769,4,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6435*/ XED_DEF_INST(XED_ICLASS_VPINSRB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512,7773,4,0,0,186,XED_EXCEPTION_AVX512_E9NF), +/*6436*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512,7777,4,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6437*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512,7777,4,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6438*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512,7781,4,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*6439*/ XED_DEF_INST(XED_ICLASS_VPINSRD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512,7781,4,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*6440*/ XED_DEF_INST(XED_ICLASS_VPINSRQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512,7785,4,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6441*/ XED_DEF_INST(XED_ICLASS_VPINSRQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512,7789,4,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*6442*/ XED_DEF_INST(XED_ICLASS_VPINSRW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512,7793,4,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*6443*/ XED_DEF_INST(XED_ICLASS_VPINSRW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512,7797,4,0,0,187,XED_EXCEPTION_AVX512_E9NF), +/*6444*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512,7424,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6445*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512,7428,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6446*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512,7432,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6447*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512,7436,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6448*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512,7440,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6449*/ XED_DEF_INST(XED_ICLASS_VPMADDUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512,7444,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6450*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512,7801,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6451*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512,7805,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6452*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512,7809,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6453*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512,7813,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6454*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512,7817,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6455*/ XED_DEF_INST(XED_ICLASS_VPMADDWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512,7821,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6456*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512,7400,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6457*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512,7404,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6458*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512,7408,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6459*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512,7412,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6460*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512,7416,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6461*/ XED_DEF_INST(XED_ICLASS_VPMAXSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512,7420,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6462*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512,7424,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6463*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512,7428,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6464*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512,7432,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6465*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512,7436,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6466*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512,7440,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6467*/ XED_DEF_INST(XED_ICLASS_VPMAXSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512,7444,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6468*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6469*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6470*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6471*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6472*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6473*/ XED_DEF_INST(XED_ICLASS_VPMAXUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6474*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6475*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6476*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6477*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6478*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6479*/ XED_DEF_INST(XED_ICLASS_VPMAXUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6480*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512,7400,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6481*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512,7404,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6482*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512,7408,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6483*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512,7412,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6484*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512,7416,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6485*/ XED_DEF_INST(XED_ICLASS_VPMINSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512,7420,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6486*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512,7424,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6487*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512,7428,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6488*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512,7432,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6489*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512,7436,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6490*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512,7440,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6491*/ XED_DEF_INST(XED_ICLASS_VPMINSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512,7444,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6492*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6493*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6494*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6495*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6496*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6497*/ XED_DEF_INST(XED_ICLASS_VPMINUB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6498*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6499*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6500*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6501*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6502*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6503*/ XED_DEF_INST(XED_ICLASS_VPMINUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6504*/ XED_DEF_INST(XED_ICLASS_VPMOVB2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVB2M_MASKmskw_XMMu8_AVX512,7825,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6505*/ XED_DEF_INST(XED_ICLASS_VPMOVB2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVB2M_MASKmskw_YMMu8_AVX512,7827,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6506*/ XED_DEF_INST(XED_ICLASS_VPMOVB2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVB2M_MASKmskw_ZMMu8_AVX512,7829,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6507*/ XED_DEF_INST(XED_ICLASS_VPMOVD2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVD2M_MASKmskw_XMMu32_AVX512,7831,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6508*/ XED_DEF_INST(XED_ICLASS_VPMOVD2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVD2M_MASKmskw_YMMu32_AVX512,7833,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6509*/ XED_DEF_INST(XED_ICLASS_VPMOVD2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVD2M_MASKmskw_ZMMu32_AVX512,7835,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6510*/ XED_DEF_INST(XED_ICLASS_VPMOVM2B,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2B_XMMu8_MASKmskw_AVX512,7837,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6511*/ XED_DEF_INST(XED_ICLASS_VPMOVM2B,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2B_YMMu8_MASKmskw_AVX512,7839,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6512*/ XED_DEF_INST(XED_ICLASS_VPMOVM2B,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2B_ZMMu8_MASKmskw_AVX512,7841,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6513*/ XED_DEF_INST(XED_ICLASS_VPMOVM2D,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2D_XMMu32_MASKmskw_AVX512,7843,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6514*/ XED_DEF_INST(XED_ICLASS_VPMOVM2D,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2D_YMMu32_MASKmskw_AVX512,7845,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6515*/ XED_DEF_INST(XED_ICLASS_VPMOVM2D,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2D_ZMMu32_MASKmskw_AVX512,7847,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6516*/ XED_DEF_INST(XED_ICLASS_VPMOVM2Q,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2Q_XMMu64_MASKmskw_AVX512,7849,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6517*/ XED_DEF_INST(XED_ICLASS_VPMOVM2Q,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2Q_YMMu64_MASKmskw_AVX512,7851,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6518*/ XED_DEF_INST(XED_ICLASS_VPMOVM2Q,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2Q_ZMMu64_MASKmskw_AVX512,7853,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6519*/ XED_DEF_INST(XED_ICLASS_VPMOVM2W,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2W_XMMu16_MASKmskw_AVX512,7855,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6520*/ XED_DEF_INST(XED_ICLASS_VPMOVM2W,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2W_YMMu16_MASKmskw_AVX512,7857,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6521*/ XED_DEF_INST(XED_ICLASS_VPMOVM2W,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVM2W_ZMMu16_MASKmskw_AVX512,7859,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6522*/ XED_DEF_INST(XED_ICLASS_VPMOVQ2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQ2M_MASKmskw_XMMu64_AVX512,7861,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6523*/ XED_DEF_INST(XED_ICLASS_VPMOVQ2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQ2M_MASKmskw_YMMu64_AVX512,7863,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6524*/ XED_DEF_INST(XED_ICLASS_VPMOVQ2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVQ2M_MASKmskw_ZMMu64_AVX512,7865,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6525*/ XED_DEF_INST(XED_ICLASS_VPMOVSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512,7867,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6526*/ XED_DEF_INST(XED_ICLASS_VPMOVSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512,7870,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6527*/ XED_DEF_INST(XED_ICLASS_VPMOVSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512,7873,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6528*/ XED_DEF_INST(XED_ICLASS_VPMOVSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512,7876,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6529*/ XED_DEF_INST(XED_ICLASS_VPMOVSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512,7879,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6530*/ XED_DEF_INST(XED_ICLASS_VPMOVSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512,7882,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6531*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512,7885,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*6532*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512,7888,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*6533*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512,7891,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*6534*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512,7894,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*6535*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512,7897,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*6536*/ XED_DEF_INST(XED_ICLASS_VPMOVSXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512,7900,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*6537*/ XED_DEF_INST(XED_ICLASS_VPMOVUSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512,7903,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6538*/ XED_DEF_INST(XED_ICLASS_VPMOVUSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512,7906,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6539*/ XED_DEF_INST(XED_ICLASS_VPMOVUSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512,7909,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6540*/ XED_DEF_INST(XED_ICLASS_VPMOVUSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512,7912,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6541*/ XED_DEF_INST(XED_ICLASS_VPMOVUSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512,7915,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6542*/ XED_DEF_INST(XED_ICLASS_VPMOVUSWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512,7918,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6543*/ XED_DEF_INST(XED_ICLASS_VPMOVW2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVW2M_MASKmskw_XMMu16_AVX512,7921,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6544*/ XED_DEF_INST(XED_ICLASS_VPMOVW2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVW2M_MASKmskw_YMMu16_AVX512,7923,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6545*/ XED_DEF_INST(XED_ICLASS_VPMOVW2M,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVW2M_MASKmskw_ZMMu16_AVX512,7925,2,0,0,0,XED_EXCEPTION_AVX512_E7NM), +/*6546*/ XED_DEF_INST(XED_ICLASS_VPMOVWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512,7903,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6547*/ XED_DEF_INST(XED_ICLASS_VPMOVWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512,7906,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6548*/ XED_DEF_INST(XED_ICLASS_VPMOVWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512,7909,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6549*/ XED_DEF_INST(XED_ICLASS_VPMOVWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512,7912,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6550*/ XED_DEF_INST(XED_ICLASS_VPMOVWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512,7915,3,0,0,128,XED_EXCEPTION_AVX512_E6NF), +/*6551*/ XED_DEF_INST(XED_ICLASS_VPMOVWB,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512,7918,3,0,0,171,XED_EXCEPTION_AVX512_E6), +/*6552*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512,7885,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*6553*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512,7888,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*6554*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512,7891,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*6555*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512,7894,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*6556*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512,7897,3,0,0,128,XED_EXCEPTION_AVX512_E5), +/*6557*/ XED_DEF_INST(XED_ICLASS_VPMOVZXBW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512,7900,3,0,0,171,XED_EXCEPTION_AVX512_E5), +/*6558*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512,7424,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6559*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512,7428,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6560*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512,7432,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6561*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512,7436,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6562*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512,7440,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6563*/ XED_DEF_INST(XED_ICLASS_VPMULHRSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512,7444,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6564*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6565*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6566*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6567*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6568*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6569*/ XED_DEF_INST(XED_ICLASS_VPMULHUW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6570*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6571*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6572*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6573*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6574*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6575*/ XED_DEF_INST(XED_ICLASS_VPMULHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6576*/ XED_DEF_INST(XED_ICLASS_VPMULLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6577*/ XED_DEF_INST(XED_ICLASS_VPMULLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6578*/ XED_DEF_INST(XED_ICLASS_VPMULLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6579*/ XED_DEF_INST(XED_ICLASS_VPMULLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6580*/ XED_DEF_INST(XED_ICLASS_VPMULLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6581*/ XED_DEF_INST(XED_ICLASS_VPMULLQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6582*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6583*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6584*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6585*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6586*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6587*/ XED_DEF_INST(XED_ICLASS_VPMULLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6588*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSADBW_XMMu16_XMMu8_XMMu8_AVX512,7927,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6589*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSADBW_XMMu16_XMMu8_MEMu8_AVX512,7930,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6590*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSADBW_YMMu16_YMMu8_YMMu8_AVX512,7933,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6591*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSADBW_YMMu16_YMMu8_MEMu8_AVX512,7936,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6592*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512,7939,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6593*/ XED_DEF_INST(XED_ICLASS_VPSADBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512,7942,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6594*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6595*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6596*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6597*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6598*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6599*/ XED_DEF_INST(XED_ICLASS_VPSHUFB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6600*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512,7945,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6601*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512,7949,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6602*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512,7953,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6603*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512,7957,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6604*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512,7961,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6605*/ XED_DEF_INST(XED_ICLASS_VPSHUFHW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512,7965,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6606*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512,7945,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6607*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512,7949,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6608*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512,7953,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6609*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512,7957,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6610*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512,7961,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6611*/ XED_DEF_INST(XED_ICLASS_VPSHUFLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512,7965,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6612*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLDQ_XMMu8_XMMu8_IMM8_AVX512,7969,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6613*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLDQ_XMMu8_MEMu8_IMM8_AVX512,7972,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6614*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLDQ_YMMu8_YMMu8_IMM8_AVX512,7975,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6615*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLDQ_YMMu8_MEMu8_IMM8_AVX512,7978,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6616*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLDQ_ZMMu8_ZMMu8_IMM8_AVX512,7981,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6617*/ XED_DEF_INST(XED_ICLASS_VPSLLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLDQ_ZMMu8_MEMu8_IMM8_AVX512,7984,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6618*/ XED_DEF_INST(XED_ICLASS_VPSLLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6619*/ XED_DEF_INST(XED_ICLASS_VPSLLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6620*/ XED_DEF_INST(XED_ICLASS_VPSLLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6621*/ XED_DEF_INST(XED_ICLASS_VPSLLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6622*/ XED_DEF_INST(XED_ICLASS_VPSLLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6623*/ XED_DEF_INST(XED_ICLASS_VPSLLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6624*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6625*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6626*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512,7987,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6627*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512,7991,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6628*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512,7995,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6629*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7999,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6630*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512,8003,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6631*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512,8007,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6632*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512,8011,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6633*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,8015,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6634*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512,8019,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6635*/ XED_DEF_INST(XED_ICLASS_VPSLLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSLLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512,8023,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6636*/ XED_DEF_INST(XED_ICLASS_VPSRAVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6637*/ XED_DEF_INST(XED_ICLASS_VPSRAVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6638*/ XED_DEF_INST(XED_ICLASS_VPSRAVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6639*/ XED_DEF_INST(XED_ICLASS_VPSRAVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6640*/ XED_DEF_INST(XED_ICLASS_VPSRAVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6641*/ XED_DEF_INST(XED_ICLASS_VPSRAVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6642*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6643*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6644*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512,7987,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6645*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512,7991,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6646*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512,7995,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6647*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7999,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6648*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512,8003,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6649*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512,8007,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6650*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512,8011,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6651*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,8015,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6652*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512,8019,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6653*/ XED_DEF_INST(XED_ICLASS_VPSRAW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRAW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512,8023,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6654*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLDQ_XMMu8_XMMu8_IMM8_AVX512,7969,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6655*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLDQ_XMMu8_MEMu8_IMM8_AVX512,7972,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6656*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLDQ_YMMu8_YMMu8_IMM8_AVX512,7975,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6657*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLDQ_YMMu8_MEMu8_IMM8_AVX512,7978,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6658*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLDQ_ZMMu8_ZMMu8_IMM8_AVX512,7981,3,0,0,0,XED_EXCEPTION_AVX512_E4NF), +/*6659*/ XED_DEF_INST(XED_ICLASS_VPSRLDQ,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLDQ_ZMMu8_MEMu8_IMM8_AVX512,7984,3,0,0,188,XED_EXCEPTION_AVX512_E4NF), +/*6660*/ XED_DEF_INST(XED_ICLASS_VPSRLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6661*/ XED_DEF_INST(XED_ICLASS_VPSRLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6662*/ XED_DEF_INST(XED_ICLASS_VPSRLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6663*/ XED_DEF_INST(XED_ICLASS_VPSRLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6664*/ XED_DEF_INST(XED_ICLASS_VPSRLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6665*/ XED_DEF_INST(XED_ICLASS_VPSRLVW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6666*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6667*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6668*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512,7987,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6669*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512,7991,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6670*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512,7995,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6671*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7999,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6672*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512,8003,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6673*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512,8007,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6674*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512,8011,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6675*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,8015,4,0,0,176,XED_EXCEPTION_AVX512_E4NF), +/*6676*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512,8019,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6677*/ XED_DEF_INST(XED_ICLASS_VPSRLW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSRLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512,8023,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6678*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6679*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6680*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6681*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6682*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6683*/ XED_DEF_INST(XED_ICLASS_VPSUBB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6684*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512,7400,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6685*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512,7404,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6686*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512,7408,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6687*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512,7412,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6688*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512,7416,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6689*/ XED_DEF_INST(XED_ICLASS_VPSUBSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512,7420,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6690*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512,7424,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6691*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512,7428,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6692*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512,7432,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6693*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512,7436,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6694*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512,7440,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6695*/ XED_DEF_INST(XED_ICLASS_VPSUBSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512,7444,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6696*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6697*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6698*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6699*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6700*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6701*/ XED_DEF_INST(XED_ICLASS_VPSUBUSB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6702*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6703*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6704*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6705*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6706*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6707*/ XED_DEF_INST(XED_ICLASS_VPSUBUSW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6708*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6709*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6710*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6711*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6712*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6713*/ XED_DEF_INST(XED_ICLASS_VPSUBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6714*/ XED_DEF_INST(XED_ICLASS_VPTESTMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512,7580,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6715*/ XED_DEF_INST(XED_ICLASS_VPTESTMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512,7584,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6716*/ XED_DEF_INST(XED_ICLASS_VPTESTMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512,7588,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6717*/ XED_DEF_INST(XED_ICLASS_VPTESTMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512,7592,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6718*/ XED_DEF_INST(XED_ICLASS_VPTESTMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512,7596,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6719*/ XED_DEF_INST(XED_ICLASS_VPTESTMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512,7600,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6720*/ XED_DEF_INST(XED_ICLASS_VPTESTMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512,7604,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6721*/ XED_DEF_INST(XED_ICLASS_VPTESTMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512,7608,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6722*/ XED_DEF_INST(XED_ICLASS_VPTESTMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512,7612,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6723*/ XED_DEF_INST(XED_ICLASS_VPTESTMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512,7616,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6724*/ XED_DEF_INST(XED_ICLASS_VPTESTMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512,7620,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6725*/ XED_DEF_INST(XED_ICLASS_VPTESTMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512,7624,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6726*/ XED_DEF_INST(XED_ICLASS_VPTESTNMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512,7580,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6727*/ XED_DEF_INST(XED_ICLASS_VPTESTNMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512,7584,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6728*/ XED_DEF_INST(XED_ICLASS_VPTESTNMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512,7588,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6729*/ XED_DEF_INST(XED_ICLASS_VPTESTNMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512,7592,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6730*/ XED_DEF_INST(XED_ICLASS_VPTESTNMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512,7596,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6731*/ XED_DEF_INST(XED_ICLASS_VPTESTNMB,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512,7600,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6732*/ XED_DEF_INST(XED_ICLASS_VPTESTNMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512,7604,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6733*/ XED_DEF_INST(XED_ICLASS_VPTESTNMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512,7608,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6734*/ XED_DEF_INST(XED_ICLASS_VPTESTNMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512,7612,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6735*/ XED_DEF_INST(XED_ICLASS_VPTESTNMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512,7616,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6736*/ XED_DEF_INST(XED_ICLASS_VPTESTNMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512,7620,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6737*/ XED_DEF_INST(XED_ICLASS_VPTESTNMW,XED_CATEGORY_LOGICAL,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512,7624,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6738*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6739*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6740*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6741*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6742*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6743*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6744*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6745*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6746*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6747*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6748*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6749*/ XED_DEF_INST(XED_ICLASS_VPUNPCKHWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6750*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6751*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6752*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6753*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6754*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6755*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLBW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6756*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7448,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6757*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7452,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6758*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7456,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6759*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7460,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6760*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7464,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6761*/ XED_DEF_INST(XED_ICLASS_VPUNPCKLWD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7468,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6762*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5555,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6763*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,6798,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6764*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512,6788,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6765*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512,6793,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6766*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,6778,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6767*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512,8027,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6768*/ XED_DEF_INST(XED_ICLASS_VRANGEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512,6783,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6769*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5570,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6770*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,6803,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6771*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512,6768,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6772*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512,6773,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6773*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,6758,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6774*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512,8032,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6775*/ XED_DEF_INST(XED_ICLASS_VRANGEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512,6763,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6776*/ XED_DEF_INST(XED_ICLASS_VRANGESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5555,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6777*/ XED_DEF_INST(XED_ICLASS_VRANGESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5560,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6778*/ XED_DEF_INST(XED_ICLASS_VRANGESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,5565,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*6779*/ XED_DEF_INST(XED_ICLASS_VRANGESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5570,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6780*/ XED_DEF_INST(XED_ICLASS_VRANGESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5575,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6781*/ XED_DEF_INST(XED_ICLASS_VRANGESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,5580,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*6782*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512,5511,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6783*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512,5515,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6784*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512,5519,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6785*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512,5523,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6786*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5499,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6787*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512,5503,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6788*/ XED_DEF_INST(XED_ICLASS_VREDUCEPD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512,5507,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6789*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512,5539,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6790*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512,5543,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6791*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512,5547,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6792*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512,5551,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6793*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5527,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6794*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512,5531,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*6795*/ XED_DEF_INST(XED_ICLASS_VREDUCEPS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512,5535,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*6796*/ XED_DEF_INST(XED_ICLASS_VREDUCESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5555,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6797*/ XED_DEF_INST(XED_ICLASS_VREDUCESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512,5560,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6798*/ XED_DEF_INST(XED_ICLASS_VREDUCESD,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512,5565,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*6799*/ XED_DEF_INST(XED_ICLASS_VREDUCESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5570,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6800*/ XED_DEF_INST(XED_ICLASS_VREDUCESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512,5575,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*6801*/ XED_DEF_INST(XED_ICLASS_VREDUCESS,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512,5580,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*6802*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,5870,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6803*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,5874,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6804*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,5878,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6805*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,5882,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6806*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,5862,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6807*/ XED_DEF_INST(XED_ICLASS_VXORPD,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,5866,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6808*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,5846,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6809*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,5850,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6810*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,5854,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6811*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,5858,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6812*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,5838,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6813*/ XED_DEF_INST(XED_ICLASS_VXORPS,XED_CATEGORY_LOGICAL_FP,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,5842,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6814*/ XED_DEF_INST(XED_ICLASS_VPMADD52HUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,6182,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6815*/ XED_DEF_INST(XED_ICLASS_VPMADD52HUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6186,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6816*/ XED_DEF_INST(XED_ICLASS_VPMADD52HUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,6190,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6817*/ XED_DEF_INST(XED_ICLASS_VPMADD52HUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6194,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6818*/ XED_DEF_INST(XED_ICLASS_VPMADD52HUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,6174,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6819*/ XED_DEF_INST(XED_ICLASS_VPMADD52HUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6178,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6820*/ XED_DEF_INST(XED_ICLASS_VPMADD52LUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,6182,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6821*/ XED_DEF_INST(XED_ICLASS_VPMADD52LUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6186,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6822*/ XED_DEF_INST(XED_ICLASS_VPMADD52LUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,6190,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6823*/ XED_DEF_INST(XED_ICLASS_VPMADD52LUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6194,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6824*/ XED_DEF_INST(XED_ICLASS_VPMADD52LUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,6174,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6825*/ XED_DEF_INST(XED_ICLASS_VPMADD52LUQ,XED_CATEGORY_IFMA,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6178,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6826*/ XED_DEF_INST(XED_ICLASS_VPERMB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6827*/ XED_DEF_INST(XED_ICLASS_VPERMB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6828*/ XED_DEF_INST(XED_ICLASS_VPERMB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6829*/ XED_DEF_INST(XED_ICLASS_VPERMB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6830*/ XED_DEF_INST(XED_ICLASS_VPERMB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6831*/ XED_DEF_INST(XED_ICLASS_VPERMB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6832*/ XED_DEF_INST(XED_ICLASS_VPERMI2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,8037,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6833*/ XED_DEF_INST(XED_ICLASS_VPERMI2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,8041,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6834*/ XED_DEF_INST(XED_ICLASS_VPERMI2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,8045,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6835*/ XED_DEF_INST(XED_ICLASS_VPERMI2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,8049,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6836*/ XED_DEF_INST(XED_ICLASS_VPERMI2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,8053,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6837*/ XED_DEF_INST(XED_ICLASS_VPERMI2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,8057,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6838*/ XED_DEF_INST(XED_ICLASS_VPERMT2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,8037,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6839*/ XED_DEF_INST(XED_ICLASS_VPERMT2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,8041,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6840*/ XED_DEF_INST(XED_ICLASS_VPERMT2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,8045,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6841*/ XED_DEF_INST(XED_ICLASS_VPERMT2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,8049,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6842*/ XED_DEF_INST(XED_ICLASS_VPERMT2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,8053,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6843*/ XED_DEF_INST(XED_ICLASS_VPERMT2B,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,8057,4,0,0,169,XED_EXCEPTION_AVX512_E4NF), +/*6844*/ XED_DEF_INST(XED_ICLASS_VPMULTISHIFTQB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512,8061,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6845*/ XED_DEF_INST(XED_ICLASS_VPMULTISHIFTQB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512,8065,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6846*/ XED_DEF_INST(XED_ICLASS_VPMULTISHIFTQB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512,8069,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6847*/ XED_DEF_INST(XED_ICLASS_VPMULTISHIFTQB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512,8073,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6848*/ XED_DEF_INST(XED_ICLASS_VPMULTISHIFTQB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512,8077,4,0,0,128,XED_EXCEPTION_AVX512_E4NF), +/*6849*/ XED_DEF_INST(XED_ICLASS_VPMULTISHIFTQB,XED_CATEGORY_AVX512_VBMI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512,8081,4,0,0,130,XED_EXCEPTION_AVX512_E4NF), +/*6850*/ XED_DEF_INST(XED_ICLASS_VPOPCNTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512,7208,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6851*/ XED_DEF_INST(XED_ICLASS_VPOPCNTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512,7211,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6852*/ XED_DEF_INST(XED_ICLASS_VPOPCNTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512,7220,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6853*/ XED_DEF_INST(XED_ICLASS_VPOPCNTB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512,7223,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6854*/ XED_DEF_INST(XED_ICLASS_VPOPCNTB,XED_CATEGORY_AVX512_BITALG,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512,7232,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6855*/ XED_DEF_INST(XED_ICLASS_VPOPCNTB,XED_CATEGORY_AVX512_BITALG,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512,7235,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6856*/ XED_DEF_INST(XED_ICLASS_VPOPCNTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512,7172,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6857*/ XED_DEF_INST(XED_ICLASS_VPOPCNTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512,7175,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6858*/ XED_DEF_INST(XED_ICLASS_VPOPCNTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512,7184,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6859*/ XED_DEF_INST(XED_ICLASS_VPOPCNTW,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512,7187,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6860*/ XED_DEF_INST(XED_ICLASS_VPOPCNTW,XED_CATEGORY_AVX512_BITALG,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512,7196,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6861*/ XED_DEF_INST(XED_ICLASS_VPOPCNTW,XED_CATEGORY_AVX512_BITALG,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512,7199,3,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6862*/ XED_DEF_INST(XED_ICLASS_VPSHUFBITQMB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512,8085,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6863*/ XED_DEF_INST(XED_ICLASS_VPSHUFBITQMB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512,8089,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6864*/ XED_DEF_INST(XED_ICLASS_VPSHUFBITQMB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512,8093,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6865*/ XED_DEF_INST(XED_ICLASS_VPSHUFBITQMB,XED_CATEGORY_AVX512,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512,8097,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6866*/ XED_DEF_INST(XED_ICLASS_VPSHUFBITQMB,XED_CATEGORY_AVX512_BITALG,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512,8101,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6867*/ XED_DEF_INST(XED_ICLASS_VPSHUFBITQMB,XED_CATEGORY_AVX512_BITALG,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512,8105,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6868*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSB,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512,7217,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6869*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSB,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512,7214,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6870*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSB,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512,7229,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6871*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSB,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512,7226,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6872*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSB,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512,7241,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6873*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSB,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512,7238,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6874*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSW,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512,7181,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6875*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSW,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512,7178,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6876*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSW,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512,7193,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6877*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSW,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512,7190,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6878*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSW,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512,7205,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6879*/ XED_DEF_INST(XED_ICLASS_VPCOMPRESSW,XED_CATEGORY_COMPRESS,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512,7202,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6880*/ XED_DEF_INST(XED_ICLASS_VPEXPANDB,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512,7211,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6881*/ XED_DEF_INST(XED_ICLASS_VPEXPANDB,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512,7208,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6882*/ XED_DEF_INST(XED_ICLASS_VPEXPANDB,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512,7223,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6883*/ XED_DEF_INST(XED_ICLASS_VPEXPANDB,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512,7220,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6884*/ XED_DEF_INST(XED_ICLASS_VPEXPANDB,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512,7235,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6885*/ XED_DEF_INST(XED_ICLASS_VPEXPANDB,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512,7232,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6886*/ XED_DEF_INST(XED_ICLASS_VPEXPANDW,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512,7175,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6887*/ XED_DEF_INST(XED_ICLASS_VPEXPANDW,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512,7172,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6888*/ XED_DEF_INST(XED_ICLASS_VPEXPANDW,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512,7187,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6889*/ XED_DEF_INST(XED_ICLASS_VPEXPANDW,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512,7184,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6890*/ XED_DEF_INST(XED_ICLASS_VPEXPANDW,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512,7199,3,0,0,147,XED_EXCEPTION_AVX512_E4), +/*6891*/ XED_DEF_INST(XED_ICLASS_VPEXPANDW,XED_CATEGORY_EXPAND,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512,7196,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6892*/ XED_DEF_INST(XED_ICLASS_VPSHLDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512,4582,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6893*/ XED_DEF_INST(XED_ICLASS_VPSHLDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512,4587,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6894*/ XED_DEF_INST(XED_ICLASS_VPSHLDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512,4592,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6895*/ XED_DEF_INST(XED_ICLASS_VPSHLDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,4597,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6896*/ XED_DEF_INST(XED_ICLASS_VPSHLDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512,4572,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6897*/ XED_DEF_INST(XED_ICLASS_VPSHLDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,4577,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6898*/ XED_DEF_INST(XED_ICLASS_VPSHLDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512,4612,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6899*/ XED_DEF_INST(XED_ICLASS_VPSHLDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512,4617,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6900*/ XED_DEF_INST(XED_ICLASS_VPSHLDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512,4622,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6901*/ XED_DEF_INST(XED_ICLASS_VPSHLDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,4627,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6902*/ XED_DEF_INST(XED_ICLASS_VPSHLDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512,4602,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6903*/ XED_DEF_INST(XED_ICLASS_VPSHLDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,4607,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6904*/ XED_DEF_INST(XED_ICLASS_VPSHLDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,6158,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6905*/ XED_DEF_INST(XED_ICLASS_VPSHLDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6162,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6906*/ XED_DEF_INST(XED_ICLASS_VPSHLDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,6166,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6907*/ XED_DEF_INST(XED_ICLASS_VPSHLDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6170,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6908*/ XED_DEF_INST(XED_ICLASS_VPSHLDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,6150,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6909*/ XED_DEF_INST(XED_ICLASS_VPSHLDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6154,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6910*/ XED_DEF_INST(XED_ICLASS_VPSHLDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,6182,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6911*/ XED_DEF_INST(XED_ICLASS_VPSHLDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6186,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6912*/ XED_DEF_INST(XED_ICLASS_VPSHLDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,6190,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6913*/ XED_DEF_INST(XED_ICLASS_VPSHLDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6194,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6914*/ XED_DEF_INST(XED_ICLASS_VPSHLDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,6174,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6915*/ XED_DEF_INST(XED_ICLASS_VPSHLDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6178,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6916*/ XED_DEF_INST(XED_ICLASS_VPSHLDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7718,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6917*/ XED_DEF_INST(XED_ICLASS_VPSHLDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7722,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6918*/ XED_DEF_INST(XED_ICLASS_VPSHLDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7726,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6919*/ XED_DEF_INST(XED_ICLASS_VPSHLDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7730,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6920*/ XED_DEF_INST(XED_ICLASS_VPSHLDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7734,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6921*/ XED_DEF_INST(XED_ICLASS_VPSHLDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7738,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6922*/ XED_DEF_INST(XED_ICLASS_VPSHLDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512,8109,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6923*/ XED_DEF_INST(XED_ICLASS_VPSHLDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512,8114,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6924*/ XED_DEF_INST(XED_ICLASS_VPSHLDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512,8119,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6925*/ XED_DEF_INST(XED_ICLASS_VPSHLDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512,8124,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6926*/ XED_DEF_INST(XED_ICLASS_VPSHLDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512,8129,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6927*/ XED_DEF_INST(XED_ICLASS_VPSHLDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512,8134,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6928*/ XED_DEF_INST(XED_ICLASS_VPSHRDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512,4582,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6929*/ XED_DEF_INST(XED_ICLASS_VPSHRDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512,4587,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6930*/ XED_DEF_INST(XED_ICLASS_VPSHRDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512,4592,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6931*/ XED_DEF_INST(XED_ICLASS_VPSHRDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512,4597,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6932*/ XED_DEF_INST(XED_ICLASS_VPSHRDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512,4572,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6933*/ XED_DEF_INST(XED_ICLASS_VPSHRDD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512,4577,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6934*/ XED_DEF_INST(XED_ICLASS_VPSHRDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512,4612,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6935*/ XED_DEF_INST(XED_ICLASS_VPSHRDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512,4617,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6936*/ XED_DEF_INST(XED_ICLASS_VPSHRDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512,4622,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6937*/ XED_DEF_INST(XED_ICLASS_VPSHRDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512,4627,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6938*/ XED_DEF_INST(XED_ICLASS_VPSHRDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512,4602,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6939*/ XED_DEF_INST(XED_ICLASS_VPSHRDQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512,4607,5,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6940*/ XED_DEF_INST(XED_ICLASS_VPSHRDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512,6158,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6941*/ XED_DEF_INST(XED_ICLASS_VPSHRDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512,6162,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6942*/ XED_DEF_INST(XED_ICLASS_VPSHRDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512,6166,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6943*/ XED_DEF_INST(XED_ICLASS_VPSHRDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512,6170,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6944*/ XED_DEF_INST(XED_ICLASS_VPSHRDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512,6150,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6945*/ XED_DEF_INST(XED_ICLASS_VPSHRDVD,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512,6154,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6946*/ XED_DEF_INST(XED_ICLASS_VPSHRDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512,6182,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6947*/ XED_DEF_INST(XED_ICLASS_VPSHRDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512,6186,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6948*/ XED_DEF_INST(XED_ICLASS_VPSHRDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512,6190,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6949*/ XED_DEF_INST(XED_ICLASS_VPSHRDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512,6194,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6950*/ XED_DEF_INST(XED_ICLASS_VPSHRDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512,6174,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6951*/ XED_DEF_INST(XED_ICLASS_VPSHRDVQ,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512,6178,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*6952*/ XED_DEF_INST(XED_ICLASS_VPSHRDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512,7718,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6953*/ XED_DEF_INST(XED_ICLASS_VPSHRDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512,7722,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6954*/ XED_DEF_INST(XED_ICLASS_VPSHRDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512,7726,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6955*/ XED_DEF_INST(XED_ICLASS_VPSHRDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512,7730,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6956*/ XED_DEF_INST(XED_ICLASS_VPSHRDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512,7734,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6957*/ XED_DEF_INST(XED_ICLASS_VPSHRDVW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512,7738,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6958*/ XED_DEF_INST(XED_ICLASS_VPSHRDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512,8109,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6959*/ XED_DEF_INST(XED_ICLASS_VPSHRDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512,8114,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6960*/ XED_DEF_INST(XED_ICLASS_VPSHRDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512,8119,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6961*/ XED_DEF_INST(XED_ICLASS_VPSHRDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512,8124,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6962*/ XED_DEF_INST(XED_ICLASS_VPSHRDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512,8129,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6963*/ XED_DEF_INST(XED_ICLASS_VPSHRDW,XED_CATEGORY_VBMI2,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512,8134,5,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6964*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512,8139,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6965*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512,8144,5,0,0,130,XED_EXCEPTION_AVX512_E4), +/*6966*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512,8149,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6967*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512,8154,5,0,0,130,XED_EXCEPTION_AVX512_E4), +/*6968*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512,8159,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6969*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEINVQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512,8164,5,0,0,130,XED_EXCEPTION_AVX512_E4), +/*6970*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512,8139,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6971*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512,8144,5,0,0,130,XED_EXCEPTION_AVX512_E4), +/*6972*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512,8149,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6973*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512,8154,5,0,0,130,XED_EXCEPTION_AVX512_E4), +/*6974*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512,8159,5,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6975*/ XED_DEF_INST(XED_ICLASS_VGF2P8AFFINEQB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512,8164,5,0,0,130,XED_EXCEPTION_AVX512_E4), +/*6976*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512,7376,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6977*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512,7380,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6978*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512,7384,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6979*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512,7388,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6980*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512,7392,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*6981*/ XED_DEF_INST(XED_ICLASS_VGF2P8MULB,XED_CATEGORY_GFNI,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512,7396,4,0,0,163,XED_EXCEPTION_AVX512_E4), +/*6982*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDEC_XMMu128_XMMu128_XMMu128_AVX512,8169,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6983*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDEC_XMMu128_XMMu128_MEMu128_AVX512,8172,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6984*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDEC_YMMu128_YMMu128_YMMu128_AVX512,8175,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6985*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDEC_YMMu128_YMMu128_MEMu128_AVX512,8178,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6986*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512,8181,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6987*/ XED_DEF_INST(XED_ICLASS_VAESDEC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512,8184,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6988*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512,8169,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6989*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512,8172,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6990*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512,8175,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6991*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512,8178,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6992*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512,8181,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6993*/ XED_DEF_INST(XED_ICLASS_VAESDECLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512,8184,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6994*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENC_XMMu128_XMMu128_XMMu128_AVX512,8169,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6995*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENC_XMMu128_XMMu128_MEMu128_AVX512,8172,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6996*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENC_YMMu128_YMMu128_YMMu128_AVX512,8175,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6997*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENC_YMMu128_YMMu128_MEMu128_AVX512,8178,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*6998*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512,8181,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*6999*/ XED_DEF_INST(XED_ICLASS_VAESENC,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512,8184,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7000*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512,8169,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*7001*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512,8172,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7002*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512,8175,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*7003*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512,8178,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7004*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512,8181,3,0,0,0,XED_EXCEPTION_AVX512_E4), +/*7005*/ XED_DEF_INST(XED_ICLASS_VAESENCLAST,XED_CATEGORY_VAES,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512,8184,3,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7006*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512,8187,4,0,0,0,XED_EXCEPTION_AVX512_E4), +/*7007*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512,8191,4,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7008*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512,8195,4,0,0,0,XED_EXCEPTION_AVX512_E4), +/*7009*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512,8199,4,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7010*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512,8203,4,0,0,0,XED_EXCEPTION_AVX512_E4), +/*7011*/ XED_DEF_INST(XED_ICLASS_VPCLMULQDQ,XED_CATEGORY_VPCLMULQDQ,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512,8207,4,0,0,188,XED_EXCEPTION_AVX512_E4), +/*7012*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTD,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512,8211,3,0,0,189,XED_EXCEPTION_AVX512_E4), +/*7013*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTD,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512,8214,3,0,0,190,XED_EXCEPTION_AVX512_E4), +/*7014*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTD,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512,8217,3,0,0,189,XED_EXCEPTION_AVX512_E4), +/*7015*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTD,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512,8220,3,0,0,190,XED_EXCEPTION_AVX512_E4), +/*7016*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTD,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512,8223,3,0,0,189,XED_EXCEPTION_AVX512_E4), +/*7017*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTD,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512,8226,3,0,0,190,XED_EXCEPTION_AVX512_E4), +/*7018*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTQ,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512,8229,3,0,0,189,XED_EXCEPTION_AVX512_E4), +/*7019*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTQ,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512,8232,3,0,0,190,XED_EXCEPTION_AVX512_E4), +/*7020*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTQ,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512,8235,3,0,0,189,XED_EXCEPTION_AVX512_E4), +/*7021*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTQ,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512,8238,3,0,0,190,XED_EXCEPTION_AVX512_E4), +/*7022*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTQ,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512,8241,3,0,0,189,XED_EXCEPTION_AVX512_E4), +/*7023*/ XED_DEF_INST(XED_ICLASS_VP2INTERSECTQ,XED_CATEGORY_AVX512_VP2INTERSECT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512,8244,3,0,0,190,XED_EXCEPTION_AVX512_E4), +/*7024*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7025*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7026*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7027*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7028*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7029*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8267,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7030*/ XED_DEF_INST(XED_ICLASS_VADDPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7031*/ XED_DEF_INST(XED_ICLASS_VADDSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7032*/ XED_DEF_INST(XED_ICLASS_VADDSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8275,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7033*/ XED_DEF_INST(XED_ICLASS_VADDSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VADDSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7034*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8283,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7035*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512,8288,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7036*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_YMMf16_IMM8_AVX512,8293,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7037*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_YMMf16_MEMf16_IMM8_AVX512,8298,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7038*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512,8303,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7039*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_ZMMf16_IMM8_AVX512,8308,5,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7040*/ XED_DEF_INST(XED_ICLASS_VCMPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPPH_MASKmskw_MASKmskw_ZMMf16_MEMf16_IMM8_AVX512,8313,5,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7041*/ XED_DEF_INST(XED_ICLASS_VCMPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8283,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7042*/ XED_DEF_INST(XED_ICLASS_VCMPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8318,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7043*/ XED_DEF_INST(XED_ICLASS_VCMPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCMPSH_MASKmskw_MASKmskw_XMMf16_MEMf16_IMM8_AVX512,8323,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7044*/ XED_DEF_INST(XED_ICLASS_VCOMISH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512,8328,3,98,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7045*/ XED_DEF_INST(XED_ICLASS_VCOMISH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISH_XMMf16_XMMf16_AVX512,8331,3,98,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7046*/ XED_DEF_INST(XED_ICLASS_VCOMISH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCOMISH_XMMf16_MEMf16_AVX512,8334,3,98,0,146,XED_EXCEPTION_AVX512_E3NF), +/*7047*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_XMMi32_AVX512,8337,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7048*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL128,8340,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7049*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_YMMi32_AVX512,8343,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7050*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_XMMf16_MASKmskw_MEMi32_AVX512_VL256,8340,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7051*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512,8346,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7052*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_ZMMi32_AVX512,8349,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7053*/ XED_DEF_INST(XED_ICLASS_VCVTDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTDQ2PH_YMMf16_MASKmskw_MEMi32_AVX512,8352,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7054*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_XMMf64_AVX512,8355,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7055*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL128,8358,3,0,0,192,XED_EXCEPTION_AVX512_E2), +/*7056*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_YMMf64_AVX512,8361,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7057*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL256,8358,3,0,0,192,XED_EXCEPTION_AVX512_E2), +/*7058*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512,8364,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7059*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_ZMMf64_AVX512,8367,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7060*/ XED_DEF_INST(XED_ICLASS_VCVTPD2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPD2PH_XMMf16_MASKmskw_MEMf64_AVX512_VL512,8358,3,0,0,192,XED_EXCEPTION_AVX512_E2), +/*7061*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512,8370,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7062*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512,8373,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7063*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512,8376,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7064*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512,8379,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7065*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512,8382,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7066*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512,8385,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7067*/ XED_DEF_INST(XED_ICLASS_VCVTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512,8388,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7068*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_XMMf16_AVX512,8391,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7069*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_XMMf64_MASKmskw_MEMf16_AVX512,8394,3,0,0,194,XED_EXCEPTION_AVX512_E2), +/*7070*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_XMMf16_AVX512,8397,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7071*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_YMMf64_MASKmskw_MEMf16_AVX512,8400,3,0,0,194,XED_EXCEPTION_AVX512_E2), +/*7072*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512,8403,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7073*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_XMMf16_AVX512,8406,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7074*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PD_ZMMf64_MASKmskw_MEMf16_AVX512,8409,3,0,0,194,XED_EXCEPTION_AVX512_E2), +/*7075*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_XMMf16_AVX512,4926,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7076*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_XMMf32_MASKmskw_MEMf16_AVX512,8412,3,0,0,195,XED_EXCEPTION_AVX512_E2), +/*7077*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_XMMf16_AVX512,4932,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7078*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_YMMf32_MASKmskw_MEMf16_AVX512,8415,3,0,0,195,XED_EXCEPTION_AVX512_E2), +/*7079*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512,4917,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7080*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_YMMf16_AVX512,4920,3,0,0,193,XED_EXCEPTION_AVX512_E2), +/*7081*/ XED_DEF_INST(XED_ICLASS_VCVTPH2PSX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2PSX_ZMMf32_MASKmskw_MEMf16_AVX512,8418,3,0,0,195,XED_EXCEPTION_AVX512_E2), +/*7082*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512,8421,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7083*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512,8424,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7084*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512,8427,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7085*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512,8430,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7086*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512,8433,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7087*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512,8436,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7088*/ XED_DEF_INST(XED_ICLASS_VCVTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512,8439,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7089*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512,8442,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7090*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512,8445,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7091*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512,8448,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7092*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512,8451,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7093*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512,8454,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7094*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512,8457,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7095*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512,8460,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7096*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512,8463,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7097*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512,8466,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7098*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512,8469,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7099*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512,8472,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7100*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512,8475,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7101*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512,8478,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7102*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512,8481,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7103*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512,8484,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7104*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512,8487,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7105*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512,8490,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7106*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512,8493,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7107*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512,8496,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7108*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512,8499,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7109*/ XED_DEF_INST(XED_ICLASS_VCVTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512,8502,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7110*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_XMMf16_AVX512,8505,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7111*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_XMMi16_MASKmskw_MEMf16_AVX512,8508,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7112*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_YMMf16_AVX512,8511,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7113*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_YMMi16_MASKmskw_MEMf16_AVX512,8514,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7114*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512,8517,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7115*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512,8520,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7116*/ XED_DEF_INST(XED_ICLASS_VCVTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512,8523,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7117*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_XMMf32_AVX512,8526,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7118*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL128,8529,3,0,0,192,XED_EXCEPTION_AVX512_E2), +/*7119*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_YMMf32_AVX512,8532,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7120*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_XMMf16_MASKmskw_MEMf32_AVX512_VL256,8529,3,0,0,192,XED_EXCEPTION_AVX512_E2), +/*7121*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512,8535,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7122*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_ZMMf32_AVX512,8538,3,0,0,191,XED_EXCEPTION_AVX512_E2), +/*7123*/ XED_DEF_INST(XED_ICLASS_VCVTPS2PHX,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTPS2PHX_YMMf16_MASKmskw_MEMf32_AVX512_VL512,8541,3,0,0,192,XED_EXCEPTION_AVX512_E2), +/*7124*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512,8544,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7125*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128,8547,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7126*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512,8550,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7127*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256,8547,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7128*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512,8553,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7129*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512,8556,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7130*/ XED_DEF_INST(XED_ICLASS_VCVTQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512,8547,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7131*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512,8559,4,0,0,197,XED_EXCEPTION_AVX512_E3), +/*7132*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_XMMf64_AVX512,8563,4,0,0,197,XED_EXCEPTION_AVX512_E3), +/*7133*/ XED_DEF_INST(XED_ICLASS_VCVTSD2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSD2SH_XMMf16_MASKmskw_XMMf64_MEMf64_AVX512,8567,4,0,0,198,XED_EXCEPTION_AVX512_E3), +/*7134*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512,8571,4,0,0,199,XED_EXCEPTION_AVX512_E3), +/*7135*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_XMMf16_AVX512,8575,4,0,0,199,XED_EXCEPTION_AVX512_E3), +/*7136*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SD,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SD_XMMf64_MASKmskw_XMMf64_MEMf16_AVX512,8579,4,0,0,200,XED_EXCEPTION_AVX512_E3), +/*7137*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512,8583,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7138*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512,8585,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7139*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512,8587,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7140*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512,8583,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7141*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR32i32_XMMf16_AVX512,8585,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7142*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR32i32_MEMf16_AVX512,8587,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7143*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512,8589,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7144*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR64i64_XMMf16_AVX512,8591,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7145*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SI_GPR64i64_MEMf16_AVX512,8593,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7146*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512,8595,4,0,0,199,XED_EXCEPTION_AVX512_E3), +/*7147*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_XMMf16_AVX512,8599,4,0,0,199,XED_EXCEPTION_AVX512_E3), +/*7148*/ XED_DEF_INST(XED_ICLASS_VCVTSH2SS,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2SS_XMMf32_MASKmskw_XMMf32_MEMf16_AVX512,8603,4,0,0,200,XED_EXCEPTION_AVX512_E3), +/*7149*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512,8607,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7150*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512,8609,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7151*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512,8611,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7152*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512,8607,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7153*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR32u32_XMMf16_AVX512,8609,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7154*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR32u32_MEMf16_AVX512,8611,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7155*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512,8613,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7156*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR64u64_XMMf16_AVX512,8615,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7157*/ XED_DEF_INST(XED_ICLASS_VCVTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSH2USI_GPR64u64_MEMf16_AVX512,8617,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7158*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512,8619,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7159*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512,8622,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7160*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512,8625,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*7161*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512,8619,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7162*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR32i32_AVX512,8622,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7163*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi32_AVX512,8625,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*7164*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512,8628,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7165*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_GPR64i64_AVX512,8631,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7166*/ XED_DEF_INST(XED_ICLASS_VCVTSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSI2SH_XMMf16_XMMf16_MEMi64_AVX512,8634,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*7167*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512,8637,4,0,0,197,XED_EXCEPTION_AVX512_E3), +/*7168*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_XMMf32_AVX512,8641,4,0,0,197,XED_EXCEPTION_AVX512_E3), +/*7169*/ XED_DEF_INST(XED_ICLASS_VCVTSS2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTSS2SH_XMMf16_MASKmskw_XMMf16_MEMf32_AVX512,8645,4,0,0,198,XED_EXCEPTION_AVX512_E3), +/*7170*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_XMMf16_AVX512,8370,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7171*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_XMMi32_MASKmskw_MEMf16_AVX512,8373,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7172*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_XMMf16_AVX512,8376,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7173*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_YMMi32_MASKmskw_MEMf16_AVX512,8379,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7174*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512,8382,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7175*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_YMMf16_AVX512,8649,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7176*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2DQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2DQ_ZMMi32_MASKmskw_MEMf16_AVX512,8388,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7177*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_XMMf16_AVX512,8421,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7178*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_XMMi64_MASKmskw_MEMf16_AVX512,8424,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7179*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_XMMf16_AVX512,8427,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7180*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_YMMi64_MASKmskw_MEMf16_AVX512,8430,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7181*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512,8433,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7182*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_XMMf16_AVX512,8652,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7183*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2QQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2QQ_ZMMi64_MASKmskw_MEMf16_AVX512,8439,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7184*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_XMMf16_AVX512,8442,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7185*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_XMMu32_MASKmskw_MEMf16_AVX512,8445,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7186*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_XMMf16_AVX512,8448,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7187*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_YMMu32_MASKmskw_MEMf16_AVX512,8451,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7188*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512,8454,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7189*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_YMMf16_AVX512,8655,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7190*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UDQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UDQ_ZMMu32_MASKmskw_MEMf16_AVX512,8460,3,0,0,150,XED_EXCEPTION_AVX512_E2), +/*7191*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_XMMf16_AVX512,8463,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7192*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_XMMu64_MASKmskw_MEMf16_AVX512,8466,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7193*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_XMMf16_AVX512,8469,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7194*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_YMMu64_MASKmskw_MEMf16_AVX512,8472,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7195*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512,8475,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7196*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_XMMf16_AVX512,8658,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7197*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UQQ,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UQQ_ZMMu64_MASKmskw_MEMf16_AVX512,8481,3,0,0,196,XED_EXCEPTION_AVX512_E2), +/*7198*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_XMMf16_AVX512,8484,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7199*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_XMMu16_MASKmskw_MEMf16_AVX512,8487,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7200*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_YMMf16_AVX512,8490,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7201*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_YMMu16_MASKmskw_MEMf16_AVX512,8493,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7202*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512,8496,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7203*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_ZMMf16_AVX512,8661,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7204*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2UW,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2UW_ZMMu16_MASKmskw_MEMf16_AVX512,8502,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7205*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_XMMf16_AVX512,8505,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7206*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_XMMi16_MASKmskw_MEMf16_AVX512,8508,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7207*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_YMMf16_AVX512,8511,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7208*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_YMMi16_MASKmskw_MEMf16_AVX512,8514,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7209*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512,8517,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7210*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_ZMMf16_AVX512,8664,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7211*/ XED_DEF_INST(XED_ICLASS_VCVTTPH2W,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTPH2W_ZMMi16_MASKmskw_MEMf16_AVX512,8523,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7212*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512,8583,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7213*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512,8667,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7214*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512,8587,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7215*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512,8583,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7216*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR32i32_XMMf16_AVX512,8667,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7217*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR32i32_MEMf16_AVX512,8587,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7218*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512,8589,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7219*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR64i64_XMMf16_AVX512,8669,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7220*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2SI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2SI_GPR64i64_MEMf16_AVX512,8593,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7221*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512,8607,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7222*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512,8671,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7223*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512,8611,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7224*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512,8607,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7225*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR32u32_XMMf16_AVX512,8671,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7226*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR32u32_MEMf16_AVX512,8611,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7227*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512,8613,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7228*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR64u64_XMMf16_AVX512,8673,2,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7229*/ XED_DEF_INST(XED_ICLASS_VCVTTSH2USI,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTTSH2USI_GPR64u64_MEMf16_AVX512,8617,2,0,0,154,XED_EXCEPTION_AVX512_E3NF), +/*7230*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_XMMu32_AVX512,8675,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7231*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL128,8678,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7232*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_YMMu32_AVX512,8681,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7233*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_XMMf16_MASKmskw_MEMu32_AVX512_VL256,8678,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7234*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512,8684,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7235*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_ZMMu32_AVX512,8687,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7236*/ XED_DEF_INST(XED_ICLASS_VCVTUDQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUDQ2PH_YMMf16_MASKmskw_MEMu32_AVX512,8690,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7237*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_XMMu64_AVX512,8544,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7238*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL128,8547,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7239*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_YMMu64_AVX512,8550,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7240*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL256,8547,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7241*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512,8553,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7242*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_ZMMu64_AVX512,8556,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7243*/ XED_DEF_INST(XED_ICLASS_VCVTUQQ2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUQQ2PH_XMMf16_MASKmskw_MEMu64_AVX512_VL512,8547,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7244*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512,8693,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7245*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512,8696,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7246*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512,8699,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*7247*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512,8693,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7248*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR32u32_AVX512,8696,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7249*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu32_AVX512,8699,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*7250*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512,8702,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7251*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_GPR64u64_AVX512,8705,3,0,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7252*/ XED_DEF_INST(XED_ICLASS_VCVTUSI2SH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUSI2SH_XMMf16_XMMf16_MEMu64_AVX512,8708,3,0,0,153,XED_EXCEPTION_AVX512_E3NF), +/*7253*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_XMMu16_AVX512,8711,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7254*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_XMMf16_MASKmskw_MEMu16_AVX512,8714,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7255*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_YMMu16_AVX512,8717,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7256*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_YMMf16_MASKmskw_MEMu16_AVX512,8720,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7257*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512,8723,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7258*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_ZMMu16_AVX512,8726,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7259*/ XED_DEF_INST(XED_ICLASS_VCVTUW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTUW2PH_ZMMf16_MASKmskw_MEMu16_AVX512,8729,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7260*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_XMMi16_AVX512,8732,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7261*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_XMMf16_MASKmskw_MEMi16_AVX512,8735,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7262*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_YMMi16_AVX512,8738,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7263*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_YMMf16_MASKmskw_MEMi16_AVX512,8741,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7264*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512,8744,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7265*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_ZMMi16_AVX512,8747,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7266*/ XED_DEF_INST(XED_ICLASS_VCVTW2PH,XED_CATEGORY_CONVERT,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VCVTW2PH_ZMMf16_MASKmskw_MEMi16_AVX512,8750,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7267*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7268*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7269*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7270*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7271*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7272*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8267,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7273*/ XED_DEF_INST(XED_ICLASS_VDIVPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7274*/ XED_DEF_INST(XED_ICLASS_VDIVSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7275*/ XED_DEF_INST(XED_ICLASS_VDIVSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8275,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7276*/ XED_DEF_INST(XED_ICLASS_VDIVSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VDIVSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7277*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8753,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7278*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8757,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7279*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512,8761,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7280*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512,8765,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7281*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8769,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7282*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8773,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7283*/ XED_DEF_INST(XED_ICLASS_VFCMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512,8777,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7284*/ XED_DEF_INST(XED_ICLASS_VFCMADDCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8753,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7285*/ XED_DEF_INST(XED_ICLASS_VFCMADDCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8781,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7286*/ XED_DEF_INST(XED_ICLASS_VFCMADDCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8785,4,0,0,204,XED_EXCEPTION_AVX512_E10), +/*7287*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8789,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7288*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8793,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7289*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512,8797,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7290*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512,8801,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7291*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8805,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7292*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8809,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7293*/ XED_DEF_INST(XED_ICLASS_VFCMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512,8813,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7294*/ XED_DEF_INST(XED_ICLASS_VFCMULCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8789,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7295*/ XED_DEF_INST(XED_ICLASS_VFCMULCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8817,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7296*/ XED_DEF_INST(XED_ICLASS_VFCMULCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFCMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8821,4,0,0,204,XED_EXCEPTION_AVX512_E10), +/*7297*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7298*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7299*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7300*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7301*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7302*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7303*/ XED_DEF_INST(XED_ICLASS_VFMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7304*/ XED_DEF_INST(XED_ICLASS_VFMADD132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7305*/ XED_DEF_INST(XED_ICLASS_VFMADD132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7306*/ XED_DEF_INST(XED_ICLASS_VFMADD132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7307*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7308*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7309*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7310*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7311*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7312*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7313*/ XED_DEF_INST(XED_ICLASS_VFMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7314*/ XED_DEF_INST(XED_ICLASS_VFMADD213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7315*/ XED_DEF_INST(XED_ICLASS_VFMADD213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7316*/ XED_DEF_INST(XED_ICLASS_VFMADD213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7317*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7318*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7319*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7320*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7321*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7322*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7323*/ XED_DEF_INST(XED_ICLASS_VFMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7324*/ XED_DEF_INST(XED_ICLASS_VFMADD231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7325*/ XED_DEF_INST(XED_ICLASS_VFMADD231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7326*/ XED_DEF_INST(XED_ICLASS_VFMADD231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7327*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8753,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7328*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8757,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7329*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512,8761,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7330*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512,8765,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7331*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8769,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7332*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8773,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7333*/ XED_DEF_INST(XED_ICLASS_VFMADDCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512,8777,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7334*/ XED_DEF_INST(XED_ICLASS_VFMADDCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8753,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7335*/ XED_DEF_INST(XED_ICLASS_VFMADDCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8781,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7336*/ XED_DEF_INST(XED_ICLASS_VFMADDCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8785,4,0,0,204,XED_EXCEPTION_AVX512_E10), +/*7337*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7338*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7339*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7340*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7341*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7342*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7343*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7344*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7345*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7346*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7347*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7348*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7349*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7350*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7351*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7352*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7353*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7354*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7355*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7356*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7357*/ XED_DEF_INST(XED_ICLASS_VFMADDSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMADDSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7358*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7359*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7360*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7361*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7362*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7363*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7364*/ XED_DEF_INST(XED_ICLASS_VFMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7365*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7366*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7367*/ XED_DEF_INST(XED_ICLASS_VFMSUB132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7368*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7369*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7370*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7371*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7372*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7373*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7374*/ XED_DEF_INST(XED_ICLASS_VFMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7375*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7376*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7377*/ XED_DEF_INST(XED_ICLASS_VFMSUB213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7378*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7379*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7380*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7381*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7382*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7383*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7384*/ XED_DEF_INST(XED_ICLASS_VFMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7385*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7386*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7387*/ XED_DEF_INST(XED_ICLASS_VFMSUB231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7388*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7389*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7390*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7391*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7392*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7393*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7394*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7395*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7396*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7397*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7398*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7399*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7400*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7401*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7402*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7403*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7404*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7405*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7406*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7407*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7408*/ XED_DEF_INST(XED_ICLASS_VFMSUBADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMSUBADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7409*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8789,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7410*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8793,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7411*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_YMM2f16_AVX512,8797,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7412*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_YMM2f16_MASKmskw_YMM2f16_MEM2f16_AVX512,8801,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7413*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8805,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7414*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_ZMM2f16_AVX512,8809,4,0,0,201,XED_EXCEPTION_AVX512_E4), +/*7415*/ XED_DEF_INST(XED_ICLASS_VFMULCPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCPH_ZMM2f16_MASKmskw_ZMM2f16_MEM2f16_AVX512,8813,4,0,0,202,XED_EXCEPTION_AVX512_E4), +/*7416*/ XED_DEF_INST(XED_ICLASS_VFMULCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8789,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7417*/ XED_DEF_INST(XED_ICLASS_VFMULCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_XMM2f16_AVX512,8817,4,0,0,203,XED_EXCEPTION_AVX512_E10), +/*7418*/ XED_DEF_INST(XED_ICLASS_VFMULCSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFMULCSH_XMM2f16_MASKmskw_XMM2f16_MEM2f16_AVX512,8821,4,0,0,204,XED_EXCEPTION_AVX512_E10), +/*7419*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7420*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7421*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7422*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7423*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7424*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7425*/ XED_DEF_INST(XED_ICLASS_VFNMADD132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7426*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7427*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7428*/ XED_DEF_INST(XED_ICLASS_VFNMADD132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7429*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7430*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7431*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7432*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7433*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7434*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7435*/ XED_DEF_INST(XED_ICLASS_VFNMADD213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7436*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7437*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7438*/ XED_DEF_INST(XED_ICLASS_VFNMADD213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7439*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7440*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7441*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7442*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7443*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7444*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7445*/ XED_DEF_INST(XED_ICLASS_VFNMADD231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7446*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7447*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7448*/ XED_DEF_INST(XED_ICLASS_VFNMADD231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMADD231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7449*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7450*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7451*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7452*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7453*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7454*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7455*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7456*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7457*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7458*/ XED_DEF_INST(XED_ICLASS_VFNMSUB132SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB132SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7459*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7460*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7461*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7462*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7463*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7464*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7465*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7466*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7467*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7468*/ XED_DEF_INST(XED_ICLASS_VFNMSUB213SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB213SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7469*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7470*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8829,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7471*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8833,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7472*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8837,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7473*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8841,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7474*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8845,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7475*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231PH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231PH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8849,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7476*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8825,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7477*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8853,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7478*/ XED_DEF_INST(XED_ICLASS_VFNMSUB231SH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFNMSUB231SH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8857,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7479*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512,8861,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7480*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL128,8865,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7481*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_YMMf16_IMM8_AVX512,8869,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7482*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL256,8865,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7483*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_ZMMf16_IMM8_AVX512,8873,4,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7484*/ XED_DEF_INST(XED_ICLASS_VFPCLASSPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSPH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512_VL512,8865,4,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7485*/ XED_DEF_INST(XED_ICLASS_VFPCLASSSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_XMMf16_IMM8_AVX512,8861,4,0,0,168,XED_EXCEPTION_AVX512_E10), +/*7486*/ XED_DEF_INST(XED_ICLASS_VFPCLASSSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VFPCLASSSH_MASKmskw_MASKmskw_MEMf16_IMM8_AVX512,8877,4,0,0,167,XED_EXCEPTION_AVX512_E10), +/*7487*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_XMMf16_AVX512,8881,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7488*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_XMMf16_MASKmskw_MEMf16_AVX512,8884,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7489*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_YMMf16_AVX512,8887,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7490*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_YMMf16_MASKmskw_MEMf16_AVX512,8890,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7491*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512,8893,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7492*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_ZMMf16_AVX512,8896,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7493*/ XED_DEF_INST(XED_ICLASS_VGETEXPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPPH_ZMMf16_MASKmskw_MEMf16_AVX512,8899,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7494*/ XED_DEF_INST(XED_ICLASS_VGETEXPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7495*/ XED_DEF_INST(XED_ICLASS_VGETEXPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8902,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7496*/ XED_DEF_INST(XED_ICLASS_VGETEXPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETEXPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7497*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512,8906,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7498*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512,8910,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7499*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512,8914,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7500*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512,8918,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7501*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512,8922,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7502*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512,8926,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7503*/ XED_DEF_INST(XED_ICLASS_VGETMANTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512,8930,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7504*/ XED_DEF_INST(XED_ICLASS_VGETMANTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8934,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7505*/ XED_DEF_INST(XED_ICLASS_VGETMANTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8939,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7506*/ XED_DEF_INST(XED_ICLASS_VGETMANTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VGETMANTSH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512,8944,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7507*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7508*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7509*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7510*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7511*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7512*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8949,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7513*/ XED_DEF_INST(XED_ICLASS_VMAXPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7514*/ XED_DEF_INST(XED_ICLASS_VMAXSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7515*/ XED_DEF_INST(XED_ICLASS_VMAXSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8902,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7516*/ XED_DEF_INST(XED_ICLASS_VMAXSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMAXSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7517*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7518*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7519*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7520*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7521*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7522*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8949,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7523*/ XED_DEF_INST(XED_ICLASS_VMINPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7524*/ XED_DEF_INST(XED_ICLASS_VMINSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7525*/ XED_DEF_INST(XED_ICLASS_VMINSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8902,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7526*/ XED_DEF_INST(XED_ICLASS_VMINSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMINSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7527*/ XED_DEF_INST(XED_ICLASS_VMOVSH,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSH_XMMf16_MASKmskw_MEMf16_AVX512,8953,3,0,0,167,XED_EXCEPTION_AVX512_E5), +/*7528*/ XED_DEF_INST(XED_ICLASS_VMOVSH,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSH_MEMf16_MASKmskw_XMMf16_AVX512,8956,3,0,0,167,XED_EXCEPTION_AVX512_E5), +/*7529*/ XED_DEF_INST(XED_ICLASS_VMOVSH,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,168,XED_EXCEPTION_AVX512_E5), +/*7530*/ XED_DEF_INST(XED_ICLASS_VMOVSH,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8959,4,0,0,168,XED_EXCEPTION_AVX512_E5), +/*7531*/ XED_DEF_INST(XED_ICLASS_VMOVW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVW_XMMf16_GPR32f16_AVX512,8963,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*7532*/ XED_DEF_INST(XED_ICLASS_VMOVW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVW_XMMf16_MEMf16_AVX512,8965,2,0,0,161,XED_EXCEPTION_AVX512_E9NF), +/*7533*/ XED_DEF_INST(XED_ICLASS_VMOVW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVW_GPR32f16_XMMf16_AVX512,8967,2,0,0,0,XED_EXCEPTION_AVX512_E9NF), +/*7534*/ XED_DEF_INST(XED_ICLASS_VMOVW,XED_CATEGORY_DATAXFER,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMOVW_MEMf16_XMMf16_AVX512,8969,2,0,0,156,XED_EXCEPTION_AVX512_E9NF), +/*7535*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7536*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7537*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7538*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7539*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7540*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8267,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7541*/ XED_DEF_INST(XED_ICLASS_VMULPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7542*/ XED_DEF_INST(XED_ICLASS_VMULSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7543*/ XED_DEF_INST(XED_ICLASS_VMULSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8275,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7544*/ XED_DEF_INST(XED_ICLASS_VMULSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VMULSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7545*/ XED_DEF_INST(XED_ICLASS_VRCPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPPH_XMMf16_MASKmskw_XMMf16_AVX512,8881,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7546*/ XED_DEF_INST(XED_ICLASS_VRCPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPPH_XMMf16_MASKmskw_MEMf16_AVX512,8884,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7547*/ XED_DEF_INST(XED_ICLASS_VRCPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPPH_YMMf16_MASKmskw_YMMf16_AVX512,8887,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7548*/ XED_DEF_INST(XED_ICLASS_VRCPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPPH_YMMf16_MASKmskw_MEMf16_AVX512,8890,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7549*/ XED_DEF_INST(XED_ICLASS_VRCPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPPH_ZMMf16_MASKmskw_ZMMf16_AVX512,8893,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7550*/ XED_DEF_INST(XED_ICLASS_VRCPPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPPH_ZMMf16_MASKmskw_MEMf16_AVX512,8899,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7551*/ XED_DEF_INST(XED_ICLASS_VRCPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,168,XED_EXCEPTION_AVX512_E10), +/*7552*/ XED_DEF_INST(XED_ICLASS_VRCPSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRCPSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,167,XED_EXCEPTION_AVX512_E10), +/*7553*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512,8906,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7554*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512,8910,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7555*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512,8914,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7556*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512,8918,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7557*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512,8922,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7558*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512,8926,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7559*/ XED_DEF_INST(XED_ICLASS_VREDUCEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512,8930,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7560*/ XED_DEF_INST(XED_ICLASS_VREDUCESH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8934,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7561*/ XED_DEF_INST(XED_ICLASS_VREDUCESH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8939,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7562*/ XED_DEF_INST(XED_ICLASS_VREDUCESH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VREDUCESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512,8944,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7563*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_XMMf16_IMM8_AVX512,8906,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7564*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_XMMf16_MASKmskw_MEMf16_IMM8_AVX512,8910,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7565*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_YMMf16_IMM8_AVX512,8914,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7566*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_YMMf16_MASKmskw_MEMf16_IMM8_AVX512,8918,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7567*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512,8922,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7568*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_ZMMf16_IMM8_AVX512,8926,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7569*/ XED_DEF_INST(XED_ICLASS_VRNDSCALEPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALEPH_ZMMf16_MASKmskw_MEMf16_IMM8_AVX512,8930,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7570*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8934,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7571*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_XMMf16_IMM8_AVX512,8939,5,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7572*/ XED_DEF_INST(XED_ICLASS_VRNDSCALESH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRNDSCALESH_XMMf16_MASKmskw_XMMf16_MEMf16_IMM8_AVX512,8944,5,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7573*/ XED_DEF_INST(XED_ICLASS_VRSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512,8881,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7574*/ XED_DEF_INST(XED_ICLASS_VRSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512,8884,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7575*/ XED_DEF_INST(XED_ICLASS_VRSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512,8887,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7576*/ XED_DEF_INST(XED_ICLASS_VRSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512,8890,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7577*/ XED_DEF_INST(XED_ICLASS_VRSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512,8893,3,0,0,128,XED_EXCEPTION_AVX512_E4), +/*7578*/ XED_DEF_INST(XED_ICLASS_VRSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512,8899,3,0,0,129,XED_EXCEPTION_AVX512_E4), +/*7579*/ XED_DEF_INST(XED_ICLASS_VRSQRTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,168,XED_EXCEPTION_AVX512_E10), +/*7580*/ XED_DEF_INST(XED_ICLASS_VRSQRTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VRSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,167,XED_EXCEPTION_AVX512_E10), +/*7581*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7582*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7583*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7584*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7585*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7586*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8267,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7587*/ XED_DEF_INST(XED_ICLASS_VSCALEFPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7588*/ XED_DEF_INST(XED_ICLASS_VSCALEFSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7589*/ XED_DEF_INST(XED_ICLASS_VSCALEFSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8275,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7590*/ XED_DEF_INST(XED_ICLASS_VSCALEFSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSCALEFSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7591*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_XMMf16_MASKmskw_XMMf16_AVX512,8881,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7592*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_XMMf16_MASKmskw_MEMf16_AVX512,8884,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7593*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_YMMf16_MASKmskw_YMMf16_AVX512,8887,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7594*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_YMMf16_MASKmskw_MEMf16_AVX512,8890,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7595*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512,8893,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7596*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_ZMMf16_AVX512,8971,3,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7597*/ XED_DEF_INST(XED_ICLASS_VSQRTPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTPH_ZMMf16_MASKmskw_MEMf16_AVX512,8899,3,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7598*/ XED_DEF_INST(XED_ICLASS_VSQRTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7599*/ XED_DEF_INST(XED_ICLASS_VSQRTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8275,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7600*/ XED_DEF_INST(XED_ICLASS_VSQRTSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSQRTSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7601*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7602*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8251,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7603*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_YMMf16_AVX512,8255,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7604*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_YMMf16_MASKmskw_YMMf16_MEMf16_AVX512,8259,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7605*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8263,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7606*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_ZMMf16_AVX512,8267,4,0,0,131,XED_EXCEPTION_AVX512_E2), +/*7607*/ XED_DEF_INST(XED_ICLASS_VSUBPH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBPH_ZMMf16_MASKmskw_ZMMf16_MEMf16_AVX512,8271,4,0,0,132,XED_EXCEPTION_AVX512_E2), +/*7608*/ XED_DEF_INST(XED_ICLASS_VSUBSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8247,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7609*/ XED_DEF_INST(XED_ICLASS_VSUBSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_XMMf16_AVX512,8275,4,0,0,135,XED_EXCEPTION_AVX512_E3), +/*7610*/ XED_DEF_INST(XED_ICLASS_VSUBSH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VSUBSH_XMMf16_MASKmskw_XMMf16_MEMf16_AVX512,8279,4,0,0,136,XED_EXCEPTION_AVX512_E3), +/*7611*/ XED_DEF_INST(XED_ICLASS_VUCOMISH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512,8328,3,98,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7612*/ XED_DEF_INST(XED_ICLASS_VUCOMISH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISH_XMMf16_XMMf16_AVX512,8331,3,98,0,83,XED_EXCEPTION_AVX512_E3NF), +/*7613*/ XED_DEF_INST(XED_ICLASS_VUCOMISH,XED_CATEGORY_FP16,XED_EXTENSION_AVX512EVEX,3,XED_IFORM_VUCOMISH_XMMf16_MEMf16_AVX512,8334,3,98,0,146,XED_EXCEPTION_AVX512_E3NF), +}; diff --git a/CodeVirtualizer/build/obj/xed-init-inst-table.c b/CodeVirtualizer/build/obj/xed-init-inst-table.c new file mode 100644 index 0000000..62d5c12 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-inst-table.c @@ -0,0 +1,28 @@ +/// @file xed-init-inst-table.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_init_inst_table_0(void); +void xed_init_inst_table(void) +{ + xed_init_inst_table_0(); +} diff --git a/CodeVirtualizer/build/obj/xed-init-operand-data.c b/CodeVirtualizer/build/obj/xed-init-operand-data.c new file mode 100644 index 0000000..f652337 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-operand-data.c @@ -0,0 +1,1528 @@ +/// @file xed-init-operand-data.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-inst-defs.h" +XED_DLL_EXPORT const xed_operand_t xed_operand[XED_MAX_OPERAND_TABLE_NODES] = { +/* 0*/ XED_DEF_OPND(XED_OPERAND_REP,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x2,0), +/* 1*/ XED_DEF_OPND(XED_OPERAND_REP,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x3,0), +/* 2*/ XED_DEF_OPND(XED_OPERAND_LOCK,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x1,0), +/* 3*/ XED_DEF_OPND(XED_OPERAND_HINT,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x1,0), +/* 4*/ XED_DEF_OPND(XED_OPERAND_HINT,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x2,0), +/* 5*/ XED_DEF_OPND(XED_OPERAND_HINT,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x3,0), +/* 6*/ XED_DEF_OPND(XED_OPERAND_HINT,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x4,0), +/* 7*/ XED_DEF_OPND(XED_OPERAND_HINT,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x5,0), +/* 8*/ XED_DEF_OPND(XED_OPERAND_EOSZ,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x1,0), +/* 9*/ XED_DEF_OPND(XED_OPERAND_EOSZ,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x2,0), +/* 10*/ XED_DEF_OPND(XED_OPERAND_EOSZ,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x3,0), +/* 11*/ XED_DEF_OPND(XED_OPERAND_EASZ,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x1,0), +/* 12*/ XED_DEF_OPND(XED_OPERAND_EASZ,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x2,0), +/* 13*/ XED_DEF_OPND(XED_OPERAND_EASZ,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x3,0), +/* 14*/ XED_DEF_OPND(XED_OPERAND_IMM0SIGNED,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x1,0), +/* 15*/ XED_DEF_OPND(XED_OPERAND_DISP_WIDTH,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x10,0), +/* 16*/ XED_DEF_OPND(XED_OPERAND_DISP_WIDTH,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x20,0), +/* 17*/ XED_DEF_OPND(XED_OPERAND_DISP_WIDTH,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x40,0), +/* 18*/ XED_DEF_OPND(XED_OPERAND_DISP_WIDTH,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x8,0), +/* 19*/ XED_DEF_OPND(XED_OPERAND_DISP_WIDTH,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,0x0,0), +/* 20*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARAX,1), +/* 21*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR8,1), +/* 22*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARCX,1), +/* 23*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR9,1), +/* 24*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDX,1), +/* 25*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR10,1), +/* 26*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARBX,1), +/* 27*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR11,1), +/* 28*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RIPA,1), +/* 29*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSI,1), +/* 30*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR14,1), +/* 31*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 32*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR15,1), +/* 33*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARBP,1), +/* 34*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR13,1), +/* 35*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 36*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 37*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 38*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBX,0), +/* 39*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ESI,0), +/* 40*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDI,0), +/* 41*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBP,0), +/* 42*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_BX,0), +/* 43*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_BP,0), +/* 44*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SI,0), +/* 45*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DI,0), +/* 46*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_INVALID,0), +/* 47*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSP,1), +/* 48*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_AR12,1), +/* 49*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 50*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM32REAL,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 51*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 52*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F80,0,XED_NONTERMINAL_X87,1), +/* 53*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 54*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_M64REAL,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 55*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F80,0,XED_NONTERMINAL_X87,1), +/* 56*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 57*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 58*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87POP,0), +/* 59*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87POP,0), +/* 60*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 61*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 62*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87PUSH,0), +/* 63*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87PUSH,0), +/* 64*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM80REAL,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F80,0,1,0), +/* 65*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM32REAL,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 66*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_M64REAL,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 67*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F80,0,XED_NONTERMINAL_X87,1), +/* 68*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM80REAL,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F80,0,1,0), +/* 69*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM14,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 70*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 71*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM28,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 72*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM16,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 73*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87CONTROL,0), +/* 74*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM14,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 75*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM28,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 76*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM16,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 77*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87CONTROL,0), +/* 78*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F80,0,XED_NONTERMINAL_X87,1), +/* 79*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 80*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 81*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 82*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST1,0), +/* 83*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST1,0), +/* 84*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST1,0), +/* 85*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 86*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM32INT,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 87*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM16INT,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 88*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_F80,0,XED_REG_ST0,0), +/* 89*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 90*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87POP2,0), +/* 91*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 92*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_M64INT,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 93*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM32INT,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 94*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_M64INT,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 95*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM16INT,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 96*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87TAG,0), +/* 97*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 98*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM94,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 99*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM108,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 100*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM94,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 101*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87CONTROL,0), +/* 102*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87TAG,0), +/* 103*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM108,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 104*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 105*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87STATUS,0), +/* 106*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_F80,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F80,0,XED_NONTERMINAL_X87,1), +/* 107*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_X87POP2,0), +/* 108*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MEM80DEC,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_B80,0,1,0), +/* 109*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MEM80DEC,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_B80,0,1,0), +/* 110*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 111*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 112*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 113*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 114*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 115*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Z,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 116*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_R,1), +/* 117*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 118*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_R,1), +/* 119*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_B,1), +/* 120*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 121*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_B,1), +/* 122*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_R,1), +/* 123*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 124*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_R,1), +/* 125*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_R,1), +/* 126*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 127*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_B,1), +/* 128*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_R,1), +/* 129*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 130*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_B,1), +/* 131*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 132*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 133*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 134*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 135*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 136*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_B,1), +/* 137*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_B,1), +/* 138*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 139*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 140*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 141*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPOP,0), +/* 142*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 143*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_SSZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_SRSP,1), +/* 144*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_B,1), +/* 145*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPOP,0), +/* 146*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 147*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_SSZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_SRSP,1), +/* 148*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ES,0), +/* 149*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SS,0), +/* 150*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DS,0), +/* 151*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_SB,1), +/* 152*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_FS,0), +/* 153*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_GS,0), +/* 154*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 155*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CL,0), +/* 156*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 157*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CL,0), +/* 158*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 159*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 160*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 161*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 162*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 163*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 164*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 165*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 166*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORDX,1), +/* 167*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 168*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORDX,1), +/* 169*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_R,1), +/* 170*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 171*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 172*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORDX,1), +/* 173*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORDX,1), +/* 174*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_SB,1), +/* 175*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPUSH,0), +/* 176*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RIP,1), +/* 177*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 178*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPUSH,0), +/* 179*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RIP,1), +/* 180*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 181*/ XED_DEF_OPND(XED_OPERAND_RELBR,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Z,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 182*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EIP,0), +/* 183*/ XED_DEF_OPND(XED_OPERAND_RELBR,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 184*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RIP,0), +/* 185*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RIP,1), +/* 186*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RIP,1), +/* 187*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EIP,0), +/* 188*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RIP,0), +/* 189*/ XED_DEF_OPND(XED_OPERAND_RELBR,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 190*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_P2,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 191*/ XED_DEF_OPND(XED_OPERAND_PTR,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_P,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 192*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 193*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EIP,0), +/* 194*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ES,0), +/* 195*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CS,0), +/* 196*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SS,0), +/* 197*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DS,0), +/* 198*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_SB,1), +/* 199*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_FS,0), +/* 200*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_GS,0), +/* 201*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 202*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_LDTR,0), +/* 203*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_LDTR,0), +/* 204*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TR,0), +/* 205*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TR,0), +/* 206*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 207*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_LDTR,0), +/* 208*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR16_B,1), +/* 209*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_LDTR,0), +/* 210*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TR,0), +/* 211*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TR,0), +/* 212*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_S64,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 213*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_GDTR,0), +/* 214*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_S,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 215*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CR0,0), +/* 216*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CR0,0), +/* 217*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CR0,0), +/* 218*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CR0,0), +/* 219*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 220*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 221*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 222*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 223*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 224*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 225*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBX,0), +/* 226*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 227*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RDX,0), +/* 228*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 229*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 230*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RBX,0), +/* 231*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_B,1), +/* 232*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 233*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_R,1), +/* 234*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_SEG,1), +/* 235*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_SEG,1), +/* 236*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_SEG_MOV,1), +/* 237*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR16_B,1), +/* 238*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 239*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 240*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_SB,1), +/* 241*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 242*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_MMX_B,1), +/* 243*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B,1), +/* 244*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_MMX_R,1), +/* 245*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_MMX_B,1), +/* 246*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 247*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 248*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B,1), +/* 249*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_MMX_B,1), +/* 250*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B,1), +/* 251*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_MMX_R,1), +/* 252*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_R,1), +/* 253*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 254*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B,1), +/* 255*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R,1), +/* 256*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_MMX_B,1), +/* 257*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B,1), +/* 258*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_MMX_R,1), +/* 259*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_B,1), +/* 260*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B,1), +/* 261*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_R,1), +/* 262*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_MMX_B,1), +/* 263*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B,1), +/* 264*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_MMX_R,1), +/* 265*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R,1), +/* 266*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_B,1), +/* 267*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MFPXENV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 268*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MFPXENV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 269*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 270*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_MXCSR,0), +/* 271*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 272*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_MXCSR,0), +/* 273*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MPREFETCH,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 274*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 275*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_S64,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 276*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_GDTR,0), +/* 277*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_S,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 278*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_IDTR,0), +/* 279*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 280*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 281*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 282*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 283*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 284*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_IDTR,0), +/* 285*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 286*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 287*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 288*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TSC,0), +/* 289*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TSCAUX,0), +/* 290*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 291*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 292*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 293*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 294*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 295*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 296*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 297*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AH,0), +/* 298*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW8,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPUSH,0), +/* 299*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 300*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CX,0), +/* 301*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DX,0), +/* 302*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_BX,0), +/* 303*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SP,0), +/* 304*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_BP,0), +/* 305*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SI,0), +/* 306*/ XED_DEF_OPND(XED_OPERAND_REG8,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DI,0), +/* 307*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW8,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 308*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 309*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 310*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBX,0), +/* 311*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ESP,0), +/* 312*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBP,0), +/* 313*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ESI,0), +/* 314*/ XED_DEF_OPND(XED_OPERAND_REG8,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDI,0), +/* 315*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW8,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPOP,0), +/* 316*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CX,0), +/* 317*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DX,0), +/* 318*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_BX,0), +/* 319*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_BP,0), +/* 320*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SI,0), +/* 321*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DI,0), +/* 322*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW8,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 323*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 324*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 325*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBX,0), +/* 326*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBP,0), +/* 327*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ESI,0), +/* 328*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDI,0), +/* 329*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_A16,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 330*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_A32,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 331*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 332*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR16_R,1), +/* 333*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR16_B,1), +/* 334*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR16_R,1), +/* 335*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Z,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 336*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Z,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRZ_B,1), +/* 337*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 338*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 339*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DX,0), +/* 340*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARCX,1), +/* 341*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 342*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 343*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 344*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 345*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 346*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 347*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 348*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 349*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 350*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSI,1), +/* 351*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 352*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSI,1), +/* 353*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 354*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 355*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 356*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 357*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_R,1), +/* 358*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_R,1), +/* 359*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 360*/ XED_DEF_OPND(XED_OPERAND_AGEN,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INVALID,0,1,0), +/* 361*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 362*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 363*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DX,0), +/* 364*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RDX,0), +/* 365*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 366*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 367*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW2,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPUSH,0), +/* 368*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW2,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 369*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EIP,0), +/* 370*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SPW2,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 371*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I16,0,XED_REG_STACKPUSH,0), +/* 372*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_STACKPUSH,0), +/* 373*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I64,0,XED_REG_STACKPUSH,0), +/* 374*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 375*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I16,0,XED_REG_STACKPOP,0), +/* 376*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_STACKPOP,0), +/* 377*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I64,0,XED_REG_STACKPOP,0), +/* 378*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 379*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AH,0), +/* 380*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AH,0), +/* 381*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 382*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSI,1), +/* 383*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARCX,1), +/* 384*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 385*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSI,1), +/* 386*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 387*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 388*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 389*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 390*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 391*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 392*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 393*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 394*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 395*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 396*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CR,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 397*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 398*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 399*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AX,0), +/* 400*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 401*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 402*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Z,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRZ_R,1), +/* 403*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_P,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 404*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ES,0), +/* 405*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DS,0), +/* 406*/ XED_DEF_OPND(XED_OPERAND_IMM1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 407*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORBP,1), +/* 408*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 409*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARBP,1), +/* 410*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORBP,1), +/* 411*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORSP,1), +/* 412*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW2,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPOP,0), +/* 413*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW2,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 414*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW5,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_STACKPOP,0), +/* 415*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SPW5,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 416*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RIP,0), +/* 417*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AH,0), +/* 418*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARBX,1), +/* 419*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARCX,1), +/* 420*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CX,0), +/* 421*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_IP,0), +/* 422*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 423*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 424*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_OEAX,1), +/* 425*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DX,0), +/* 426*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_OEAX,1), +/* 427*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_DX,0), +/* 428*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 429*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_OEAX,1), +/* 430*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_R,1), +/* 431*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RIP,0), +/* 432*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 433*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_R11,0), +/* 434*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 435*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_R11,0), +/* 436*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 437*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 438*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 439*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 440*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 441*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 442*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 443*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_B,1), +/* 444*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 445*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 446*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 447*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 448*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 449*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 450*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 451*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 452*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 453*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 454*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 455*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 456*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 457*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 458*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 459*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 460*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 461*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 462*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 463*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 464*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 465*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 466*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 467*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 468*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 469*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_CR_R,1), +/* 470*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR32_B,1), +/* 471*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR64_B,1), +/* 472*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR32_B,1), +/* 473*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_CR_R,1), +/* 474*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR64_B,1), +/* 475*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_DR_R,1), +/* 476*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_DR_R,1), +/* 477*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 478*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_MSRS,0), +/* 479*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_TSC,0), +/* 480*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PSEUDO,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_MSRS,0), +/* 481*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ESP,0), +/* 482*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RSP,0), +/* 483*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RDX,0), +/* 484*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR32_R,1), +/* 485*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_XUD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R,1), +/* 486*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_XUD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 487*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_XUD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B,1), +/* 488*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_XUQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R,1), +/* 489*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_XUQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 490*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_XUQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B,1), +/* 491*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_MMX_R,1), +/* 492*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 493*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_MMX_B,1), +/* 494*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/* 495*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_MMX_B,1), +/* 496*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 497*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_MMX_B,1), +/* 498*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 499*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_MMX_B,1), +/* 500*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 501*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B,1), +/* 502*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_MMX_R,1), +/* 503*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 504*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_MMX_B,1), +/* 505*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_R,1), +/* 506*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 507*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B,1), +/* 508*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 509*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_B,1), +/* 510*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_MMX_R,1), +/* 511*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/* 512*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_MMX_B,1), +/* 513*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R,1), +/* 514*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 515*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B,1), +/* 516*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R,1), +/* 517*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/* 518*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B,1), +/* 519*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 520*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBX,0), +/* 521*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 522*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 523*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 524*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 525*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 526*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR8_B,1), +/* 527*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_AL,0), +/* 528*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRV_B,1), +/* 529*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 530*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_SS,0), +/* 531*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_FS,0), +/* 532*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_GS,0), +/* 533*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR32_R,1), +/* 534*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR64_R,1), +/* 535*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/* 536*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_SS,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 537*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_SD,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 538*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 539*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_MMX_B,1), +/* 540*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R,1), +/* 541*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_MMX_R,1), +/* 542*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B,1), +/* 543*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_MMX_R,1), +/* 544*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R,1), +/* 545*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 546*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B,1), +/* 547*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_MMX_R,1), +/* 548*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 549*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 550*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B,1), +/* 551*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 552*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_MMX_B,1), +/* 553*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_MMX_R,1), +/* 554*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 555*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 556*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 557*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_R,1), +/* 558*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_GPR32_B,1), +/* 559*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_GPR64_B,1), +/* 560*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_GPR32_R,1), +/* 561*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_GPR64_R,1), +/* 562*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_GPR64_B,1), +/* 563*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_B,1), +/* 564*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 565*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 566*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_MMX_R,1), +/* 567*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_R,1), +/* 568*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_MMX_R,1), +/* 569*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R,1), +/* 570*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R,1), +/* 571*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B,1), +/* 572*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_MMX_R,1), +/* 573*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_MMX_B,1), +/* 574*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 575*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR64_R,1), +/* 576*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPR32_R,1), +/* 577*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_CL,0), +/* 578*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 579*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_GPRV_R,1), +/* 580*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_GPRV_B,1), +/* 581*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_GPRY_R,1), +/* 582*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR8_B,1), +/* 583*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 584*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 585*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 586*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 587*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 588*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 589*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_XMM0,0), +/* 590*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_XMM0,0), +/* 591*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_XMM0,0), +/* 592*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_XMM0,0), +/* 593*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_GPR32_B,1), +/* 594*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_XMM0,0), +/* 595*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_XMM0,0), +/* 596*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_GPR64_B,1), +/* 597*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R,1), +/* 598*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R,1), +/* 599*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B,1), +/* 600*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_R,1), +/* 601*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B,1), +/* 602*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 603*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B,1), +/* 604*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R,1), +/* 605*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 606*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B,1), +/* 607*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B,1), +/* 608*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 609*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B,1), +/* 610*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 611*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B,1), +/* 612*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B,1), +/* 613*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 614*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B,1), +/* 615*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B,1), +/* 616*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B,1), +/* 617*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B,1), +/* 618*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 619*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 620*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 621*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 622*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RDX,0), +/* 623*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 624*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 625*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 626*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 627*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 628*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_XMM0,0), +/* 629*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_XMM0,0), +/* 630*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_XMM0,0), +/* 631*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_XMM0,0), +/* 632*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 633*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_XCR0,0), +/* 634*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_XCR0,0), +/* 635*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_MXSAVE,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 636*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 637*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_XCR0,0), +/* 638*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MXSAVE,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 639*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 640*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EBX,0), +/* 641*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORCX,1), +/* 642*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORAX,1), +/* 643*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORCX,1), +/* 644*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_V,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORDX,1), +/* 645*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORBX,1), +/* 646*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARAX,1), +/* 647*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARAX,1), +/* 648*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RCW,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ORCX,1), +/* 649*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARDI,1), +/* 650*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 651*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 652*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PMMSZ16,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 653*/ XED_DEF_OPND(XED_OPERAND_BASE0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARSI,1), +/* 654*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_PMMSZ32,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 655*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARAX,1), +/* 656*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 657*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 658*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_B,1), +/* 659*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ASZ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_ARAX,1), +/* 660*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_EDX,0), +/* 661*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_EAX,0), +/* 662*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_I32,0,XED_REG_ECX,0), +/* 663*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 664*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 665*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 666*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RDX,0), +/* 667*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EDX,0), +/* 668*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_ECX,0), +/* 669*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_IMPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RAX,0), +/* 670*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_BND_R,1), +/* 671*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_BND_R,1), +/* 672*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_BND_B,1), +/* 673*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_BND_B,1), +/* 674*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_BND_R,1), +/* 675*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 676*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 677*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_BND32,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 678*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_BND64,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 679*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_BND32,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 680*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_BND64,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 681*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 682*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR32_B,1), +/* 683*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_U64,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_SSP,0), +/* 684*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR64_B,1), +/* 685*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_GPR32_B,1), +/* 686*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_U64,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_SSP,0), +/* 687*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_GPR64_B,1), +/* 688*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_U64,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_SSP,0), +/* 689*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_U64,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_SSP,0), +/* 690*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 691*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_GPR32_R,1), +/* 692*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 693*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_GPR64_R,1), +/* 694*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM0,0), +/* 695*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM0,0), +/* 696*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MXSAVE,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_STRUCT,0,1,0), +/* 697*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRY_B,1), +/* 698*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_FSBASE,0), +/* 699*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_GSBASE,0), +/* 700*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_GPRY_B,1), +/* 701*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_FSBASE,0), +/* 702*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_GSBASE,0), +/* 703*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RBX,0), +/* 704*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RCX,0), +/* 705*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_RDX,0), +/* 706*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_TSCAUX,0), +/* 707*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_INT,0,1,0), +/* 708*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_A_GPR_R,1), +/* 709*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 710*/ XED_DEF_OPND(XED_OPERAND_MEM1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 711*/ XED_DEF_OPND(XED_OPERAND_BASE1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_A_GPR_R,1), +/* 712*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_GPR32_B,1), +/* 713*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_EDX,0), +/* 714*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_EAX,0), +/* 715*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_INVALID,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_A_GPR_B,1), +/* 716*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_EAX,0), +/* 717*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_RBX,0), +/* 718*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_RCX,0), +/* 719*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_RDX,0), +/* 720*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RIP,1), +/* 721*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INVALID,0,XED_REG_EAX,0), +/* 722*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_GPR32_R,1), +/* 723*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_GPR64_R,1), +/* 724*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_EAX,0), +/* 725*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_EBX,0), +/* 726*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_ECX,0), +/* 727*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_EDX,0), +/* 728*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_M384,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 729*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 730*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM0,0), +/* 731*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM1,0), +/* 732*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM2,0), +/* 733*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM3,0), +/* 734*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM4,0), +/* 735*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM5,0), +/* 736*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM6,0), +/* 737*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM7,0), +/* 738*/ XED_DEF_OPND(XED_OPERAND_REG8,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 739*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR32_R,1), +/* 740*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR32_B,1), +/* 741*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM0,0), +/* 742*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM1,0), +/* 743*/ XED_DEF_OPND(XED_OPERAND_REG4,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM2,0), +/* 744*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM4,0), +/* 745*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM5,0), +/* 746*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM6,0), +/* 747*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM1,0), +/* 748*/ XED_DEF_OPND(XED_OPERAND_REG5,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM3,0), +/* 749*/ XED_DEF_OPND(XED_OPERAND_REG6,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM4,0), +/* 750*/ XED_DEF_OPND(XED_OPERAND_REG7,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM5,0), +/* 751*/ XED_DEF_OPND(XED_OPERAND_REG8,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM6,0), +/* 752*/ XED_DEF_OPND(XED_OPERAND_REG9,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INVALID,0,XED_NONTERMINAL_RFLAGS,1), +/* 753*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R,1), +/* 754*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U8,0,XED_REG_XMM0,0), +/* 755*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_I1,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_UIF,0), +/* 756*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_I1,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_INT,0,XED_REG_UIF,0), +/* 757*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_RAX,0), +/* 758*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U64,0,XED_REG_RCX,0), +/* 759*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_REG,XED_OPERAND_XTYPE_U32,0,XED_REG_ECX,0), +/* 760*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_N,1), +/* 761*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_SE,1), +/* 762*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B,1), +/* 763*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_SE,1), +/* 764*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_SE,1), +/* 765*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_SE,1), +/* 766*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N,1), +/* 767*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_SE,1), +/* 768*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B,1), +/* 769*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_SE,1), +/* 770*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_XMM_R,1), +/* 771*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_XMM_N,1), +/* 772*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I1,0,1,0), +/* 773*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_XMM_SE,1), +/* 774*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_XMM_B,1), +/* 775*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_XMM_SE,1), +/* 776*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_XMM_B,1), +/* 777*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_YMM_R,1), +/* 778*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_YMM_N,1), +/* 779*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I1,0,1,0), +/* 780*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_YMM_SE,1), +/* 781*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_YMM_B,1), +/* 782*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_YMM_SE,1), +/* 783*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_YMM_B,1), +/* 784*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B,1), +/* 785*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R,1), +/* 786*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_N,1), +/* 787*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_N,1), +/* 788*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B,1), +/* 789*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_N,1), +/* 790*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_N,1), +/* 791*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B,1), +/* 792*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N,1), +/* 793*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N,1), +/* 794*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B,1), +/* 795*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N,1), +/* 796*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N,1), +/* 797*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B,1), +/* 798*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_R,1), +/* 799*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_N,1), +/* 800*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B,1), +/* 801*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_N,1), +/* 802*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 803*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_B,1), +/* 804*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R,1), +/* 805*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 806*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B,1), +/* 807*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 808*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 809*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B,1), +/* 810*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 811*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 812*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 813*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 814*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_N,1), +/* 815*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_N,1), +/* 816*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N,1), +/* 817*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_B,1), +/* 818*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_N,1), +/* 819*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_R,1), +/* 820*/ XED_DEF_OPND(XED_OPERAND_IMM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 821*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_VGPRY_R,1), +/* 822*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_B,1), +/* 823*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_VGPRY_B,1), +/* 824*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_N,1), +/* 825*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_VGPRY_N,1), +/* 826*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_VGPRY_B,1), +/* 827*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Y,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_INT,0,XED_NONTERMINAL_VGPR32_B,1), +/* 828*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N,1), +/* 829*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_SE,1), +/* 830*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 831*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_SE,1), +/* 832*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 833*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_N,1), +/* 834*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_SE,1), +/* 835*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B,1), +/* 836*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_SE,1), +/* 837*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B,1), +/* 838*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_N,1), +/* 839*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_SE,1), +/* 840*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 841*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_SE,1), +/* 842*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 843*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_N,1), +/* 844*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_SE,1), +/* 845*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B,1), +/* 846*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_SE,1), +/* 847*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B,1), +/* 848*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N,1), +/* 849*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_SE,1), +/* 850*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 851*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_SE,1), +/* 852*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 853*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_N,1), +/* 854*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_SE,1), +/* 855*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 856*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_SE,1), +/* 857*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 858*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R,1), +/* 859*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_N,1), +/* 860*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/* 861*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_B,1), +/* 862*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R,1), +/* 863*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_N,1), +/* 864*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 865*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_B,1), +/* 866*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 867*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 868*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_B,1), +/* 869*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_GPR32_B,1), +/* 870*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_GPR64_B,1), +/* 871*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 872*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 873*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B,1), +/* 874*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 875*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 876*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 877*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 878*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/* 879*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_B,1), +/* 880*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 881*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N,1), +/* 882*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/* 883*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_N,1), +/* 884*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R,1), +/* 885*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N,1), +/* 886*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 887*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 888*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_N,1), +/* 889*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 890*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R,1), +/* 891*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R,1), +/* 892*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 893*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 894*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B,1), +/* 895*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 896*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B,1), +/* 897*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/* 898*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_B,1), +/* 899*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R,1), +/* 900*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_R,1), +/* 901*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_N,1), +/* 902*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U128,0,1,0), +/* 903*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_B,1), +/* 904*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U256,0,XED_NONTERMINAL_YMM_R,1), +/* 905*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U256,0,XED_NONTERMINAL_YMM_N,1), +/* 906*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U256,0,1,0), +/* 907*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U256,0,XED_NONTERMINAL_YMM_B,1), +/* 908*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_R,1), +/* 909*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/* 910*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_B,1), +/* 911*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_R,1), +/* 912*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/* 913*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_B,1), +/* 914*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R,1), +/* 915*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_B,1), +/* 916*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/* 917*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_B,1), +/* 918*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_R,1), +/* 919*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_N,1), +/* 920*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_B,1), +/* 921*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_R,1), +/* 922*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_N,1), +/* 923*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_N,1), +/* 924*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B,1), +/* 925*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_N,1), +/* 926*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N,1), +/* 927*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_N,1), +/* 928*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_N,1), +/* 929*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N,1), +/* 930*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_N,1), +/* 931*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_B,1), +/* 932*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_N,1), +/* 933*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_N,1), +/* 934*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N,1), +/* 935*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_N,1), +/* 936*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_N,1), +/* 937*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_B,1), +/* 938*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_R,1), +/* 939*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_N,1), +/* 940*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,0,1,0), +/* 941*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_B,1), +/* 942*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_N,1), +/* 943*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 944*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_B,1), +/* 945*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_B,1), +/* 946*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_N,1), +/* 947*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_B,1), +/* 948*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_N,1), +/* 949*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_B,1), +/* 950*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N,1), +/* 951*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B,1), +/* 952*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/* 953*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/* 954*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 955*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_GPR32_R,1), +/* 956*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R,1), +/* 957*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R,1), +/* 958*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R,1), +/* 959*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R,1), +/* 960*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R,1), +/* 961*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R,1), +/* 962*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R,1), +/* 963*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR32_B,1), +/* 964*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_GPR32_B,1), +/* 965*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_GPR32_B,1), +/* 966*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_GPR64_B,1), +/* 967*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_SUPPRESSED,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/* 968*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_SE,1), +/* 969*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_SE,1), +/* 970*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_SE,1), +/* 971*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_SE,1), +/* 972*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_SE,1), +/* 973*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_SE,1), +/* 974*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_SE,1), +/* 975*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_SE,1), +/* 976*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_SE,1), +/* 977*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_SE,1), +/* 978*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_SE,1), +/* 979*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_SE,1), +/* 980*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_R,1), +/* 981*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_N,1), +/* 982*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_B,1), +/* 983*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U128,0,1,0), +/* 984*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/* 985*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B,1), +/* 986*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/* 987*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B,1), +/* 988*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/* 989*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B,1), +/* 990*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/* 991*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B,1), +/* 992*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 993*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R,1), +/* 994*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R,1), +/* 995*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_N,1), +/* 996*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R,1), +/* 997*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_N,1), +/* 998*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R,1), +/* 999*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_N,1), +/*1000*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/*1001*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N,1), +/*1002*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R,1), +/*1003*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N,1), +/*1004*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R,1), +/*1005*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R,1), +/*1006*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R,1), +/*1007*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R,1), +/*1008*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_CRW,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R,1), +/*1009*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U128,0,1,0), +/*1010*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_R,1), +/*1011*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_B,1), +/*1012*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_R,1), +/*1013*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/*1014*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N,1), +/*1015*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/*1016*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_N,1), +/*1017*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R,1), +/*1018*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/*1019*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R,1), +/*1020*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_B,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B,1), +/*1021*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_W,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B,1), +/*1022*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B,1), +/*1023*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_N,1), +/*1024*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_B,1), +/*1025*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_R,1), +/*1026*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_N,1), +/*1027*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_B,1), +/*1028*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_N,1), +/*1029*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_B,1), +/*1030*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_N,1), +/*1031*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_N,1), +/*1032*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_VGPR32_N,1), +/*1033*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_VGPR64_N,1), +/*1034*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK_R,1), +/*1035*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK_N,1), +/*1036*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK_B,1), +/*1037*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_MASK_B,1), +/*1038*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1039*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1040*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK_R,1), +/*1041*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_GPR32_B,1), +/*1042*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK_B,1), +/*1043*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_MASK_B,1), +/*1044*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_MASK_B,1), +/*1045*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_MASK_B,1), +/*1046*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_GPR64_B,1), +/*1047*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_GPR64_R,1), +/*1048*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R,1), +/*1049*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/*1050*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/*1051*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_TMM_R,1), +/*1052*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_TMM_B,1), +/*1053*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_TMM_N,1), +/*1054*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_TMM_R,1), +/*1055*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_TMM_R,1), +/*1056*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_TMM_R,1), +/*1057*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_PTR,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/*1058*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_PTR,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/*1059*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_TV,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_TMM_R,1), +/*1060*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R3,1), +/*1061*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,1,XED_NONTERMINAL_MASK1,1), +/*1062*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_N3,1), +/*1063*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B3,1), +/*1064*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,2,1,0), +/*1065*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R3,1), +/*1066*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_N3,1), +/*1067*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_B3,1), +/*1068*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1069*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_N3,1), +/*1070*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1071*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_N3,1), +/*1072*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_N3,1), +/*1073*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_N3,1), +/*1074*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_BF16,0,XED_NONTERMINAL_XMM_R3,1), +/*1075*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N3,1), +/*1076*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B3,1), +/*1077*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,2,1,0), +/*1078*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_BF16,0,XED_NONTERMINAL_YMM_R3,1), +/*1079*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_N3,1), +/*1080*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B3,1), +/*1081*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZBF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_BF16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1082*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_N3,1), +/*1083*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1084*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B3,1), +/*1085*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B3,1), +/*1086*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1087*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1088*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N3,1), +/*1089*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R3,1), +/*1090*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_N3,1), +/*1091*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1092*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_N3,1), +/*1093*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1094*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1095*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,3,XED_NONTERMINAL_ZMM_R3,1), +/*1096*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,2,1,0), +/*1097*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1098*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,3,XED_NONTERMINAL_ZMM_R3,1), +/*1099*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASKNOT0,1), +/*1100*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1101*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_N3,1), +/*1102*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B3,1), +/*1103*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,3,XED_NONTERMINAL_XMM_R3,1), +/*1104*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1105*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,3,XED_NONTERMINAL_XMM_R3,1), +/*1106*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN4,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_N3,1), +/*1107*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN4,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N3,1), +/*1108*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN4,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_N3,1), +/*1109*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1110*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1111*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R3,1), +/*1112*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B3,1), +/*1113*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R3,1), +/*1114*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_B3,1), +/*1115*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1116*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1117*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,2,1,0), +/*1118*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R3,1), +/*1119*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B3,1), +/*1120*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R3,1), +/*1121*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_B3,1), +/*1122*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_N3,1), +/*1123*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1124*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,4,XED_NONTERMINAL_ZMM_R3,1), +/*1125*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R3,1), +/*1126*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_N3,1), +/*1127*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B3,1), +/*1128*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,4,XED_NONTERMINAL_ZMM_R3,1), +/*1129*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R3,1), +/*1130*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,4,XED_NONTERMINAL_XMM_R3,1), +/*1131*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,4,XED_NONTERMINAL_XMM_R3,1), +/*1132*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_N3,1), +/*1133*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1134*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N3,1), +/*1135*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B3,1), +/*1136*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_N3,1), +/*1137*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_B3,1), +/*1138*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B3,1), +/*1139*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK1,1), +/*1140*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,3,XED_NONTERMINAL_MASK_R,1), +/*1141*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1142*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B3,1), +/*1143*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,3,XED_NONTERMINAL_XMM_R3,1), +/*1144*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1145*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B3,1), +/*1146*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,3,XED_NONTERMINAL_XMM_R3,1), +/*1147*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/*1148*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK1,1), +/*1149*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1150*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1151*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1152*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1153*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_B3,1), +/*1154*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1155*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R3,1), +/*1156*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B3,1), +/*1157*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R3,1), +/*1158*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/*1159*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1160*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1161*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1162*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1163*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B3,1), +/*1164*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1165*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R3,1), +/*1166*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_B3,1), +/*1167*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R3,1), +/*1168*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_B3,1), +/*1169*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,2,1,0), +/*1170*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B3,1), +/*1171*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1172*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R3,1), +/*1173*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,4,XED_NONTERMINAL_YMM_R3,1), +/*1174*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R3,1), +/*1175*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_B3,1), +/*1176*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,4,XED_NONTERMINAL_YMM_R3,1), +/*1177*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,4,XED_NONTERMINAL_YMM_R3,1), +/*1178*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_YMM_B3,1), +/*1179*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/*1180*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B3,1), +/*1181*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1182*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,4,XED_NONTERMINAL_ZMM_R3,1), +/*1183*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_YMM_B3,1), +/*1184*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,3,XED_NONTERMINAL_YMM_B3,1), +/*1185*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/*1186*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B3,1), +/*1187*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,4,XED_NONTERMINAL_ZMM_R3,1), +/*1188*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,4,XED_NONTERMINAL_GPR32_R,1), +/*1189*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,4,XED_NONTERMINAL_GPR64_R,1), +/*1190*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,4,XED_NONTERMINAL_GPR32_R,1), +/*1191*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,4,XED_NONTERMINAL_GPR64_R,1), +/*1192*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_N3,1), +/*1193*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N3,1), +/*1194*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,3,XED_NONTERMINAL_YMM_R3,1), +/*1195*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,3,XED_NONTERMINAL_YMM_R3,1), +/*1196*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,3,XED_NONTERMINAL_ZMM_R3,1), +/*1197*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,3,XED_NONTERMINAL_ZMM_R3,1), +/*1198*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,3,XED_NONTERMINAL_GPR32_R,1), +/*1199*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,3,XED_NONTERMINAL_GPR64_R,1), +/*1200*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,3,XED_NONTERMINAL_GPR32_R,1), +/*1201*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,3,XED_NONTERMINAL_GPR64_R,1), +/*1202*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F64,0,1,0), +/*1203*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F32,0,1,0), +/*1204*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B3,1), +/*1205*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1206*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1207*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R3,1), +/*1208*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R3,1), +/*1209*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_B3,1), +/*1210*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1211*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1212*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_GPR32_B,1), +/*1213*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1214*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,3,XED_NONTERMINAL_ZMM_R3,1), +/*1215*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1216*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R3,1), +/*1217*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,3,XED_NONTERMINAL_ZMM_R3,1), +/*1218*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,3,XED_NONTERMINAL_XMM_R3,1), +/*1219*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,3,XED_NONTERMINAL_XMM_R3,1), +/*1220*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,4,XED_NONTERMINAL_ZMM_R3,1), +/*1221*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,4,XED_NONTERMINAL_ZMM_R3,1), +/*1222*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,4,XED_NONTERMINAL_XMM_R3,1), +/*1223*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,4,XED_NONTERMINAL_XMM_R3,1), +/*1224*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASKNOT0,1), +/*1225*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R3,1), +/*1226*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R3,1), +/*1227*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1228*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U32,0,1,0), +/*1229*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R3,1), +/*1230*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_B3,1), +/*1231*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/*1232*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1233*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U64,0,1,0), +/*1234*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B3,1), +/*1235*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R3,1), +/*1236*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R3,1), +/*1237*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R3,1), +/*1238*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R3,1), +/*1239*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_N3,1), +/*1240*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_N3,1), +/*1241*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_B3,1), +/*1242*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1243*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1244*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1245*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R3,1), +/*1246*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1247*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_YMM_R3,1), +/*1248*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1249*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_YMM_R3,1), +/*1250*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R3,1), +/*1251*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_B3,1), +/*1252*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F64,0,XED_NONTERMINAL_XMM_R3,1), +/*1253*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F32,0,XED_NONTERMINAL_XMM_R3,1), +/*1254*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1255*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1256*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I64,2,1,0), +/*1257*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R3,1), +/*1258*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_B3,1), +/*1259*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_R3,1), +/*1260*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_B3,1), +/*1261*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_N3,1), +/*1262*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1263*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_N3,1), +/*1264*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B3,1), +/*1265*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_N3,1), +/*1266*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_B3,1), +/*1267*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_ZMM_N3,1), +/*1268*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1269*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_N3,1), +/*1270*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_B3,1), +/*1271*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_N3,1), +/*1272*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_B3,1), +/*1273*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1274*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_R3,1), +/*1275*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_R3,1), +/*1276*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1277*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_R3,1), +/*1278*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_R3,1), +/*1279*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B3,1), +/*1280*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/*1281*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/*1282*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/*1283*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_B3,1), +/*1284*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1285*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B3,1), +/*1286*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1287*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1288*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/*1289*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1290*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B3,1), +/*1291*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1292*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1293*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_ZMM_R3,1), +/*1294*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R3,1), +/*1295*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1296*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_R3,1), +/*1297*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R3,1), +/*1298*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1299*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_R3,1), +/*1300*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_B3,1), +/*1301*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/*1302*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B3,1), +/*1303*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/*1304*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/*1305*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1306*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_ZMM_R3,1), +/*1307*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R3,1), +/*1308*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1309*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_XMM_R3,1), +/*1310*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_R3,1), +/*1311*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,0,XED_NONTERMINAL_YMM_R3,1), +/*1312*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_YMM_B3,1), +/*1313*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I32,0,XED_NONTERMINAL_XMM_B3,1), +/*1314*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Q,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I32,0,1,0), +/*1315*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/*1316*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B3,1), +/*1317*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1318*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_B3,1), +/*1319*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B3,1), +/*1320*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_N3,1), +/*1321*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N3,1), +/*1322*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_N3,1), +/*1323*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_N3,1), +/*1324*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N3,1), +/*1325*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_N3,1), +/*1326*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,4,XED_NONTERMINAL_ZMM_R3,1), +/*1327*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,4,XED_NONTERMINAL_ZMM_R3,1), +/*1328*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I64,3,XED_NONTERMINAL_ZMM_R3,1), +/*1329*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,3,XED_NONTERMINAL_ZMM_R3,1), +/*1330*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R3,1), +/*1331*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B3,1), +/*1332*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_R3,1), +/*1333*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_B3,1), +/*1334*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1335*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_B3,1), +/*1336*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B3,1), +/*1337*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R3,1), +/*1338*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R3,1), +/*1339*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_B3,1), +/*1340*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_R3,1), +/*1341*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_R3,1), +/*1342*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1343*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1344*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1345*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1346*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,0,1,0), +/*1347*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1348*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R3,1), +/*1349*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B3,1), +/*1350*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R3,1), +/*1351*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R3,1), +/*1352*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_R3,1), +/*1353*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_B3,1), +/*1354*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_B3,1), +/*1355*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_R3,1), +/*1356*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/*1357*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_R3,1), +/*1358*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_R3,1), +/*1359*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_B3,1), +/*1360*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_B3,1), +/*1361*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_R3,1), +/*1362*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U8,0,1,0), +/*1363*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_R3,1), +/*1364*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_R3,1), +/*1365*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_R3,1), +/*1366*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_B3,1), +/*1367*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_ZMM_R3,1), +/*1368*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_ZMM_B3,1), +/*1369*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1370*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_R3,1), +/*1371*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_R3,1), +/*1372*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1373*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1374*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,0,1,0), +/*1375*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_B3,1), +/*1376*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_B3,1), +/*1377*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1378*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_N3,1), +/*1379*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B3,1), +/*1380*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_N3,1), +/*1381*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_B3,1), +/*1382*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_N3,1), +/*1383*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1384*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_N3,1), +/*1385*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_XMM_B3,1), +/*1386*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_N3,1), +/*1387*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_B3,1), +/*1388*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_ZMM_N3,1), +/*1389*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_ZMM_B3,1), +/*1390*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R3,1), +/*1391*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_R3,1), +/*1392*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1393*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_GPR32_B,1), +/*1394*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R3,1), +/*1395*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_GPR32_B,1), +/*1396*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_R3,1), +/*1397*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_GPR32_R,1), +/*1398*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_B3,1), +/*1399*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_N3,1), +/*1400*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_N3,1), +/*1401*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_XMM_N3,1), +/*1402*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_N3,1), +/*1403*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_B3,1), +/*1404*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_B3,1), +/*1405*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_B3,1), +/*1406*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_XMM_B3,1), +/*1407*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_B3,1), +/*1408*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_B3,1), +/*1409*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_B3,1), +/*1410*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_B3,1), +/*1411*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_R3,1), +/*1412*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_XMM_R3,1), +/*1413*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_R3,1), +/*1414*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_YMM_R3,1), +/*1415*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I8,0,XED_NONTERMINAL_YMM_B3,1), +/*1416*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1417*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I8,0,1,0), +/*1418*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1419*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_B3,1), +/*1420*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1421*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_N3,1), +/*1422*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_N3,1), +/*1423*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_N3,1), +/*1424*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_N3,1), +/*1425*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_N3,1), +/*1426*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_XMM_N3,1), +/*1427*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_YMM_N3,1), +/*1428*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,0,XED_NONTERMINAL_ZMM_N3,1), +/*1429*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_XMM_R3,1), +/*1430*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_YMM_R3,1), +/*1431*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZU8,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U8,0,XED_NONTERMINAL_ZMM_R3,1), +/*1432*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_R3,1), +/*1433*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_N3,1), +/*1434*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_XMM_B3,1), +/*1435*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_R3,1), +/*1436*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_N3,1), +/*1437*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_YMM_B3,1), +/*1438*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU128,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_ZMM_R3,1), +/*1439*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU128,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_ZMM_N3,1), +/*1440*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU128,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U128,0,XED_NONTERMINAL_ZMM_B3,1), +/*1441*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U128,0,1,0), +/*1442*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_YMM_N3,1), +/*1443*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU64,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U64,0,XED_NONTERMINAL_ZMM_N3,1), +/*1444*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_MSKW,XED_OPERAND_TYPE_NT_LOOKUP_FN2,XED_OPERAND_XTYPE_I1,0,XED_NONTERMINAL_MASK_R,1), +/*1445*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_YMM_N3,1), +/*1446*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZU32,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U32,0,XED_NONTERMINAL_ZMM_N3,1), +/*1447*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1448*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_N3,1), +/*1449*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B3,1), +/*1450*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,2,1,0), +/*1451*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_YMM_R3,1), +/*1452*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_YMM_N3,1), +/*1453*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_YMM_B3,1), +/*1454*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1455*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_ZMM_N3,1), +/*1456*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1457*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,4,XED_NONTERMINAL_ZMM_R3,1), +/*1458*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,4,XED_NONTERMINAL_XMM_R3,1), +/*1459*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/*1460*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1461*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_B3,1), +/*1462*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,3,XED_NONTERMINAL_XMM_R3,1), +/*1463*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,4,XED_NONTERMINAL_YMM_R3,1), +/*1464*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1465*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,4,XED_NONTERMINAL_ZMM_R3,1), +/*1466*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,4,XED_NONTERMINAL_ZMM_R3,1), +/*1467*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_N3,1), +/*1468*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZU16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_U16,3,XED_NONTERMINAL_ZMM_R3,1), +/*1469*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZI16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_I16,3,XED_NONTERMINAL_ZMM_R3,1), +/*1470*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_U16,2,1,0), +/*1471*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_I16,2,1,0), +/*1472*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1473*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_XMM_N3,1), +/*1474*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_XMM_B3,1), +/*1475*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_VV,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_2F16,2,1,0), +/*1476*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_YMM_R3,1), +/*1477*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_YMM_N3,1), +/*1478*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_YMM_B3,1), +/*1479*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Z2F16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1480*/ XED_DEF_OPND(XED_OPERAND_REG2,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Z2F16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_ZMM_N3,1), +/*1481*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_Z2F16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_ZMM_B3,1), +/*1482*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_Z2F16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,4,XED_NONTERMINAL_ZMM_R3,1), +/*1483*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,4,XED_NONTERMINAL_XMM_R3,1), +/*1484*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_2F16,0,1,0), +/*1485*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1486*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_YMM_R3,1), +/*1487*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Z2F16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1488*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_Z2F16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,4,XED_NONTERMINAL_ZMM_R3,1), +/*1489*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_2F16,4,XED_NONTERMINAL_XMM_R3,1), +/*1490*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1491*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_QQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_YMM_R3,1), +/*1492*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_ZMM_R3,1), +/*1493*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,4,XED_NONTERMINAL_ZMM_R3,1), +/*1494*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_RW,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,4,XED_NONTERMINAL_XMM_R3,1), +/*1495*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_ZF16,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,3,XED_NONTERMINAL_ZMM_R3,1), +/*1496*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,3,XED_NONTERMINAL_XMM_R3,1), +/*1497*/ XED_DEF_OPND(XED_OPERAND_MEM0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_WRD,XED_OPERAND_TYPE_IMM_CONST,XED_OPERAND_XTYPE_F16,0,1,0), +/*1498*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1499*/ XED_DEF_OPND(XED_OPERAND_REG3,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_DQ,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_XMM_R3,1), +/*1500*/ XED_DEF_OPND(XED_OPERAND_REG1,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_R,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_GPR32_B,1), +/*1501*/ XED_DEF_OPND(XED_OPERAND_REG0,XED_OPVIS_EXPLICIT,XED_OPERAND_ACTION_W,XED_OPERAND_WIDTH_D,XED_OPERAND_TYPE_NT_LOOKUP_FN,XED_OPERAND_XTYPE_F16,0,XED_NONTERMINAL_GPR32_B,1), +}; diff --git a/CodeVirtualizer/build/obj/xed-init-operand-sequences.c b/CodeVirtualizer/build/obj/xed-init-operand-sequences.c new file mode 100644 index 0000000..e91cb14 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-operand-sequences.c @@ -0,0 +1,9000 @@ +/// @file xed-init-operand-sequences.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-inst-defs.h" +XED_DLL_EXPORT const xed_uint16_t xed_operand_sequences[XED_MAX_OPERAND_SEQUENCES] = { +/* 0 1.0 */ 0, +/* 1 1.1 */ 0, +/* 2 2.0 */ 1, +/* 3 2.1 */ 1, +/* 4 3.0 */ 2, +/* 5 4.0 */ 3, +/* 6 5.0 */ 4, +/* 7 6.0 */ 5, +/* 8 7.0 */ 6, +/* 9 8.0 */ 7, +/* 10 9.0 */ 8, +/* 11 10.0 */ 9, +/* 12 11.0 */ 10, +/* 13 12.0 */ 11, +/* 14 13.0 */ 12, +/* 15 14.0 */ 13, +/* 16 15.0 */ 14, +/* 17 16.0 */ 15, +/* 18 17.0 */ 16, +/* 19 18.0 */ 17, +/* 20 19.0 */ 18, +/* 21 20.0 */ 19, +/* 22 21.0 */ 20, +/* 23 22.0 */ 21, +/* 24 23.0 */ 22, +/* 25 24.0 */ 23, +/* 26 25.0 */ 24, +/* 27 26.0 */ 25, +/* 28 27.0 */ 26, +/* 29 28.0 */ 27, +/* 30 29.0 */ 28, +/* 31 30.0 */ 29, +/* 32 31.0 */ 30, +/* 33 32.0 */ 31, +/* 34 33.0 */ 32, +/* 35 34.0 */ 33, +/* 36 35.0 */ 34, +/* 37 36.0 */ 35, +/* 38 37.0 */ 36, +/* 39 38.0 */ 37, +/* 40 39.0 */ 38, +/* 41 40.0 */ 39, +/* 42 41.0 */ 40, +/* 43 42.0 */ 41, +/* 44 43.0 */ 42, +/* 45 44.0 */ 43, +/* 46 45.0 */ 44, +/* 47 46.0 */ 45, +/* 48 47.0 */ 46, +/* 49 48.0 */ 47, +/* 50 49.0 */ 48, +/* 51 50.0 */ 33, +/* 52 50.1 */ 18, +/* 53 51.0 */ 33, +/* 54 51.1 */ 16, +/* 55 52.0 */ 34, +/* 56 52.1 */ 18, +/* 57 53.0 */ 34, +/* 58 53.1 */ 16, +/* 59 54.0 */ 49, +/* 60 54.1 */ 50, +/* 61 54.2 */ 51, +/* 62 55.0 */ 49, +/* 63 55.1 */ 52, +/* 64 55.2 */ 53, +/* 65 56.0 */ 49, +/* 66 56.1 */ 54, +/* 67 56.2 */ 51, +/* 68 57.0 */ 55, +/* 69 57.1 */ 56, +/* 70 57.2 */ 53, +/* 71 58.0 */ 57, +/* 72 58.1 */ 50, +/* 73 58.2 */ 58, +/* 74 58.3 */ 53, +/* 75 59.0 */ 57, +/* 76 59.1 */ 52, +/* 77 59.2 */ 59, +/* 78 59.3 */ 60, +/* 79 60.0 */ 57, +/* 80 60.1 */ 54, +/* 81 60.2 */ 58, +/* 82 60.3 */ 53, +/* 83 61.0 */ 57, +/* 84 61.1 */ 50, +/* 85 61.2 */ 51, +/* 86 62.0 */ 57, +/* 87 62.1 */ 54, +/* 88 62.2 */ 51, +/* 89 63.0 */ 57, +/* 90 63.1 */ 52, +/* 91 63.2 */ 53, +/* 92 64.0 */ 61, +/* 93 64.1 */ 50, +/* 94 64.2 */ 62, +/* 95 64.3 */ 53, +/* 96 65.0 */ 61, +/* 97 65.1 */ 52, +/* 98 65.2 */ 63, +/* 99 65.3 */ 60, +/* 100 66.0 */ 61, +/* 101 66.1 */ 64, +/* 102 66.2 */ 62, +/* 103 66.3 */ 53, +/* 104 67.0 */ 61, +/* 105 67.1 */ 54, +/* 106 67.2 */ 62, +/* 107 67.3 */ 53, +/* 108 68.0 */ 65, +/* 109 68.1 */ 57, +/* 110 68.2 */ 51, +/* 111 69.0 */ 66, +/* 112 69.1 */ 57, +/* 113 69.2 */ 51, +/* 114 70.0 */ 67, +/* 115 70.1 */ 56, +/* 116 70.2 */ 53, +/* 117 71.0 */ 65, +/* 118 71.1 */ 57, +/* 119 71.2 */ 58, +/* 120 71.3 */ 53, +/* 121 72.0 */ 68, +/* 122 72.1 */ 57, +/* 123 72.2 */ 58, +/* 124 72.3 */ 53, +/* 125 73.0 */ 66, +/* 126 73.1 */ 57, +/* 127 73.2 */ 58, +/* 128 73.3 */ 53, +/* 129 74.0 */ 67, +/* 130 74.1 */ 56, +/* 131 74.2 */ 59, +/* 132 74.3 */ 60, +/* 133 75.0 */ 69, +/* 134 75.1 */ 70, +/* 135 76.0 */ 71, +/* 136 76.1 */ 70, +/* 137 77.0 */ 72, +/* 138 77.1 */ 73, +/* 139 77.2 */ 51, +/* 140 78.0 */ 74, +/* 141 78.1 */ 70, +/* 142 79.0 */ 75, +/* 143 79.1 */ 70, +/* 144 80.0 */ 76, +/* 145 80.1 */ 77, +/* 146 80.2 */ 51, +/* 147 81.0 */ 49, +/* 148 81.1 */ 78, +/* 149 81.2 */ 53, +/* 150 82.0 */ 79, +/* 151 82.1 */ 51, +/* 152 83.0 */ 80, +/* 153 83.1 */ 62, +/* 154 83.2 */ 53, +/* 155 84.0 */ 81, +/* 156 84.1 */ 82, +/* 157 84.2 */ 59, +/* 158 84.3 */ 60, +/* 159 85.0 */ 79, +/* 160 85.1 */ 83, +/* 161 85.2 */ 53, +/* 162 86.0 */ 79, +/* 163 86.1 */ 84, +/* 164 86.2 */ 53, +/* 165 87.0 */ 85, +/* 166 88.0 */ 49, +/* 167 88.1 */ 86, +/* 168 88.2 */ 51, +/* 169 89.0 */ 49, +/* 170 89.1 */ 87, +/* 171 89.2 */ 51, +/* 172 90.0 */ 57, +/* 173 90.1 */ 86, +/* 174 90.2 */ 51, +/* 175 91.0 */ 57, +/* 176 91.1 */ 87, +/* 177 91.2 */ 51, +/* 178 92.0 */ 57, +/* 179 92.1 */ 86, +/* 180 92.2 */ 58, +/* 181 92.3 */ 53, +/* 182 93.0 */ 57, +/* 183 93.1 */ 87, +/* 184 93.2 */ 58, +/* 185 93.3 */ 53, +/* 186 94.0 */ 88, +/* 187 94.1 */ 52, +/* 188 94.2 */ 53, +/* 189 94.3 */ 89, +/* 190 95.0 */ 81, +/* 191 95.1 */ 84, +/* 192 95.2 */ 90, +/* 193 95.3 */ 91, +/* 194 96.0 */ 61, +/* 195 96.1 */ 86, +/* 196 96.2 */ 62, +/* 197 96.3 */ 53, +/* 198 97.0 */ 61, +/* 199 97.1 */ 87, +/* 200 97.2 */ 62, +/* 201 97.3 */ 53, +/* 202 98.0 */ 61, +/* 203 98.1 */ 92, +/* 204 98.2 */ 62, +/* 205 98.3 */ 53, +/* 206 99.0 */ 93, +/* 207 99.1 */ 57, +/* 208 99.2 */ 58, +/* 209 99.3 */ 53, +/* 210 100.0 */ 94, +/* 211 100.1 */ 57, +/* 212 100.2 */ 58, +/* 213 100.3 */ 53, +/* 214 101.0 */ 95, +/* 215 101.1 */ 57, +/* 216 101.2 */ 58, +/* 217 101.3 */ 53, +/* 218 102.0 */ 93, +/* 219 102.1 */ 57, +/* 220 102.2 */ 51, +/* 221 103.0 */ 95, +/* 222 103.1 */ 57, +/* 223 103.2 */ 51, +/* 224 104.0 */ 70, +/* 225 105.0 */ 73, +/* 226 105.1 */ 96, +/* 227 105.2 */ 53, +/* 228 106.0 */ 57, +/* 229 106.1 */ 52, +/* 230 106.2 */ 53, +/* 231 106.3 */ 97, +/* 232 107.0 */ 98, +/* 233 107.1 */ 73, +/* 234 108.0 */ 99, +/* 235 108.1 */ 73, +/* 236 109.0 */ 100, +/* 237 109.1 */ 101, +/* 238 109.2 */ 102, +/* 239 109.3 */ 91, +/* 240 110.0 */ 103, +/* 241 110.1 */ 101, +/* 242 110.2 */ 102, +/* 243 110.3 */ 91, +/* 244 111.0 */ 76, +/* 245 111.1 */ 85, +/* 246 112.0 */ 104, +/* 247 112.1 */ 105, +/* 248 113.0 */ 106, +/* 249 113.1 */ 96, +/* 250 114.0 */ 57, +/* 251 114.1 */ 52, +/* 252 114.2 */ 59, +/* 253 114.3 */ 91, +/* 254 115.0 */ 55, +/* 255 115.1 */ 56, +/* 256 115.2 */ 59, +/* 257 115.3 */ 60, +/* 258 116.0 */ 81, +/* 259 116.1 */ 84, +/* 260 116.2 */ 107, +/* 261 116.3 */ 91, +/* 262 117.0 */ 61, +/* 263 117.1 */ 108, +/* 264 117.2 */ 62, +/* 265 117.3 */ 53, +/* 266 118.0 */ 109, +/* 267 118.1 */ 57, +/* 268 118.2 */ 58, +/* 269 118.3 */ 53, +/* 270 119.0 */ 106, +/* 271 119.1 */ 96, +/* 272 119.2 */ 59, +/* 273 120.0 */ 57, +/* 274 120.1 */ 52, +/* 275 120.2 */ 59, +/* 276 120.3 */ 60, +/* 277 120.4 */ 110, +/* 278 121.0 */ 111, +/* 279 121.1 */ 112, +/* 280 121.2 */ 113, +/* 281 122.0 */ 114, +/* 282 122.1 */ 115, +/* 283 122.2 */ 113, +/* 284 123.0 */ 114, +/* 285 123.1 */ 112, +/* 286 123.2 */ 113, +/* 287 124.0 */ 111, +/* 288 124.1 */ 116, +/* 289 124.2 */ 117, +/* 290 125.0 */ 114, +/* 291 125.1 */ 118, +/* 292 125.2 */ 117, +/* 293 126.0 */ 119, +/* 294 126.1 */ 120, +/* 295 126.2 */ 117, +/* 296 127.0 */ 121, +/* 297 127.1 */ 115, +/* 298 127.2 */ 117, +/* 299 128.0 */ 119, +/* 300 128.1 */ 112, +/* 301 128.2 */ 117, +/* 302 129.0 */ 121, +/* 303 129.1 */ 112, +/* 304 129.2 */ 117, +/* 305 130.0 */ 119, +/* 306 130.1 */ 122, +/* 307 130.2 */ 123, +/* 308 131.0 */ 121, +/* 309 131.1 */ 124, +/* 310 131.2 */ 123, +/* 311 132.0 */ 125, +/* 312 132.1 */ 126, +/* 313 132.2 */ 117, +/* 314 133.0 */ 125, +/* 315 133.1 */ 127, +/* 316 133.2 */ 123, +/* 317 134.0 */ 128, +/* 318 134.1 */ 129, +/* 319 134.2 */ 117, +/* 320 135.0 */ 128, +/* 321 135.1 */ 130, +/* 322 135.2 */ 123, +/* 323 136.0 */ 131, +/* 324 136.1 */ 112, +/* 325 136.2 */ 117, +/* 326 137.0 */ 132, +/* 327 137.1 */ 115, +/* 328 137.2 */ 117, +/* 329 138.0 */ 131, +/* 330 138.1 */ 120, +/* 331 138.2 */ 117, +/* 332 139.0 */ 111, +/* 333 139.1 */ 112, +/* 334 139.2 */ 133, +/* 335 140.0 */ 114, +/* 336 140.1 */ 115, +/* 337 140.2 */ 133, +/* 338 141.0 */ 114, +/* 339 141.1 */ 112, +/* 340 141.2 */ 133, +/* 341 142.0 */ 111, +/* 342 142.1 */ 116, +/* 343 142.2 */ 134, +/* 344 143.0 */ 114, +/* 345 143.1 */ 118, +/* 346 143.2 */ 134, +/* 347 144.0 */ 119, +/* 348 144.1 */ 112, +/* 349 144.2 */ 134, +/* 350 145.0 */ 121, +/* 351 145.1 */ 115, +/* 352 145.2 */ 134, +/* 353 146.0 */ 121, +/* 354 146.1 */ 112, +/* 355 146.2 */ 134, +/* 356 147.0 */ 119, +/* 357 147.1 */ 122, +/* 358 147.2 */ 135, +/* 359 148.0 */ 121, +/* 360 148.1 */ 124, +/* 361 148.2 */ 135, +/* 362 149.0 */ 125, +/* 363 149.1 */ 126, +/* 364 149.2 */ 134, +/* 365 150.0 */ 125, +/* 366 150.1 */ 127, +/* 367 150.2 */ 135, +/* 368 151.0 */ 128, +/* 369 151.1 */ 129, +/* 370 151.2 */ 134, +/* 371 152.0 */ 128, +/* 372 152.1 */ 130, +/* 373 152.2 */ 135, +/* 374 153.0 */ 131, +/* 375 153.1 */ 112, +/* 376 153.2 */ 134, +/* 377 154.0 */ 132, +/* 378 154.1 */ 115, +/* 379 154.2 */ 134, +/* 380 155.0 */ 111, +/* 381 155.1 */ 120, +/* 382 155.2 */ 113, +/* 383 156.0 */ 126, +/* 384 156.1 */ 112, +/* 385 156.2 */ 113, +/* 386 157.0 */ 136, +/* 387 157.1 */ 112, +/* 388 157.2 */ 117, +/* 389 158.0 */ 129, +/* 390 158.1 */ 115, +/* 391 158.2 */ 113, +/* 392 159.0 */ 137, +/* 393 159.1 */ 115, +/* 394 159.2 */ 117, +/* 395 160.0 */ 129, +/* 396 160.1 */ 112, +/* 397 160.2 */ 113, +/* 398 161.0 */ 137, +/* 399 161.1 */ 112, +/* 400 161.2 */ 117, +/* 401 162.0 */ 126, +/* 402 162.1 */ 116, +/* 403 162.2 */ 117, +/* 404 163.0 */ 136, +/* 405 163.1 */ 122, +/* 406 163.2 */ 123, +/* 407 164.0 */ 129, +/* 408 164.1 */ 118, +/* 409 164.2 */ 117, +/* 410 165.0 */ 137, +/* 411 165.1 */ 124, +/* 412 165.2 */ 123, +/* 413 166.0 */ 116, +/* 414 166.1 */ 126, +/* 415 166.2 */ 117, +/* 416 167.0 */ 116, +/* 417 167.1 */ 127, +/* 418 167.2 */ 123, +/* 419 168.0 */ 118, +/* 420 168.1 */ 129, +/* 421 168.2 */ 117, +/* 422 169.0 */ 118, +/* 423 169.1 */ 130, +/* 424 169.2 */ 123, +/* 425 170.0 */ 138, +/* 426 170.1 */ 112, +/* 427 170.2 */ 117, +/* 428 171.0 */ 139, +/* 429 171.1 */ 115, +/* 430 171.2 */ 117, +/* 431 172.0 */ 140, +/* 432 172.1 */ 141, +/* 433 172.2 */ 142, +/* 434 172.3 */ 143, +/* 435 173.0 */ 144, +/* 436 173.1 */ 145, +/* 437 173.2 */ 146, +/* 438 173.3 */ 147, +/* 439 174.0 */ 148, +/* 440 174.1 */ 145, +/* 441 174.2 */ 146, +/* 442 174.3 */ 147, +/* 443 175.0 */ 149, +/* 444 175.1 */ 145, +/* 445 175.2 */ 146, +/* 446 175.3 */ 147, +/* 447 176.0 */ 150, +/* 448 176.1 */ 145, +/* 449 176.2 */ 146, +/* 450 176.3 */ 147, +/* 451 177.0 */ 151, +/* 452 177.1 */ 145, +/* 453 177.2 */ 146, +/* 454 177.3 */ 147, +/* 455 178.0 */ 152, +/* 456 178.1 */ 145, +/* 457 178.2 */ 146, +/* 458 178.3 */ 147, +/* 459 179.0 */ 153, +/* 460 179.1 */ 145, +/* 461 179.2 */ 146, +/* 462 179.3 */ 147, +/* 463 180.0 */ 114, +/* 464 180.1 */ 120, +/* 465 180.2 */ 113, +/* 466 181.0 */ 121, +/* 467 181.1 */ 120, +/* 468 181.2 */ 117, +/* 469 182.0 */ 111, +/* 470 182.1 */ 154, +/* 471 182.2 */ 113, +/* 472 183.0 */ 119, +/* 473 183.1 */ 154, +/* 474 183.2 */ 117, +/* 475 184.0 */ 114, +/* 476 184.1 */ 154, +/* 477 184.2 */ 113, +/* 478 185.0 */ 121, +/* 479 185.1 */ 154, +/* 480 185.2 */ 117, +/* 481 186.0 */ 111, +/* 482 186.1 */ 155, +/* 483 186.2 */ 156, +/* 484 187.0 */ 119, +/* 485 187.1 */ 157, +/* 486 187.2 */ 158, +/* 487 188.0 */ 114, +/* 488 188.1 */ 155, +/* 489 188.2 */ 156, +/* 490 189.0 */ 121, +/* 491 189.1 */ 157, +/* 492 189.2 */ 158, +/* 493 190.0 */ 111, +/* 494 190.1 */ 120, +/* 495 190.2 */ 133, +/* 496 191.0 */ 119, +/* 497 191.1 */ 120, +/* 498 191.2 */ 134, +/* 499 192.0 */ 114, +/* 500 192.1 */ 120, +/* 501 192.2 */ 133, +/* 502 193.0 */ 121, +/* 503 193.1 */ 120, +/* 504 193.2 */ 134, +/* 505 194.0 */ 111, +/* 506 194.1 */ 154, +/* 507 194.2 */ 133, +/* 508 195.0 */ 119, +/* 509 195.1 */ 154, +/* 510 195.2 */ 134, +/* 511 196.0 */ 114, +/* 512 196.1 */ 154, +/* 513 196.2 */ 133, +/* 514 197.0 */ 121, +/* 515 197.1 */ 154, +/* 516 197.2 */ 134, +/* 517 198.0 */ 111, +/* 518 198.1 */ 155, +/* 519 198.2 */ 159, +/* 520 199.0 */ 119, +/* 521 199.1 */ 157, +/* 522 199.2 */ 160, +/* 523 200.0 */ 114, +/* 524 200.1 */ 155, +/* 525 200.2 */ 159, +/* 526 201.0 */ 121, +/* 527 201.1 */ 157, +/* 528 201.2 */ 160, +/* 529 202.0 */ 111, +/* 530 203.0 */ 114, +/* 531 204.0 */ 119, +/* 532 205.0 */ 121, +/* 533 206.0 */ 111, +/* 534 206.1 */ 113, +/* 535 207.0 */ 114, +/* 536 207.1 */ 113, +/* 537 208.0 */ 119, +/* 538 208.1 */ 117, +/* 539 209.0 */ 121, +/* 540 209.1 */ 117, +/* 541 210.0 */ 126, +/* 542 210.1 */ 161, +/* 543 210.2 */ 162, +/* 544 210.3 */ 123, +/* 545 211.0 */ 136, +/* 546 211.1 */ 163, +/* 547 211.2 */ 164, +/* 548 211.3 */ 97, +/* 549 212.0 */ 129, +/* 550 212.1 */ 165, +/* 551 212.2 */ 166, +/* 552 212.3 */ 123, +/* 553 213.0 */ 137, +/* 554 213.1 */ 167, +/* 555 213.2 */ 168, +/* 556 213.3 */ 97, +/* 557 214.0 */ 169, +/* 558 214.1 */ 129, +/* 559 214.2 */ 115, +/* 560 214.3 */ 117, +/* 561 215.0 */ 169, +/* 562 215.1 */ 130, +/* 563 215.2 */ 115, +/* 564 215.3 */ 123, +/* 565 216.0 */ 169, +/* 566 216.1 */ 129, +/* 567 216.2 */ 112, +/* 568 216.3 */ 117, +/* 569 217.0 */ 169, +/* 570 217.1 */ 130, +/* 571 217.2 */ 112, +/* 572 217.3 */ 123, +/* 573 218.0 */ 126, +/* 574 218.1 */ 170, +/* 575 218.2 */ 117, +/* 576 219.0 */ 136, +/* 577 219.1 */ 171, +/* 578 219.2 */ 123, +/* 579 220.0 */ 129, +/* 580 220.1 */ 165, +/* 581 220.2 */ 172, +/* 582 220.3 */ 123, +/* 583 221.0 */ 137, +/* 584 221.1 */ 167, +/* 585 221.2 */ 173, +/* 586 221.3 */ 97, +/* 587 222.0 */ 174, +/* 588 222.1 */ 117, +/* 589 223.0 */ 129, +/* 590 223.1 */ 175, +/* 591 223.2 */ 176, +/* 592 223.3 */ 177, +/* 593 223.4 */ 143, +/* 594 224.0 */ 137, +/* 595 224.1 */ 178, +/* 596 224.2 */ 179, +/* 597 224.3 */ 180, +/* 598 224.4 */ 147, +/* 599 225.0 */ 181, +/* 600 225.1 */ 175, +/* 601 225.2 */ 182, +/* 602 225.3 */ 180, +/* 603 225.4 */ 147, +/* 604 226.0 */ 183, +/* 605 226.1 */ 175, +/* 606 226.2 */ 184, +/* 607 226.3 */ 180, +/* 608 226.4 */ 147, +/* 609 227.0 */ 129, +/* 610 227.1 */ 185, +/* 611 228.0 */ 137, +/* 612 228.1 */ 186, +/* 613 229.0 */ 181, +/* 614 229.1 */ 187, +/* 615 230.0 */ 183, +/* 616 230.1 */ 188, +/* 617 231.0 */ 189, +/* 618 231.1 */ 187, +/* 619 232.0 */ 189, +/* 620 232.1 */ 188, +/* 621 233.0 */ 190, +/* 622 233.1 */ 185, +/* 623 234.0 */ 191, +/* 624 234.1 */ 192, +/* 625 234.2 */ 193, +/* 626 235.0 */ 129, +/* 627 235.1 */ 175, +/* 628 235.2 */ 177, +/* 629 235.3 */ 143, +/* 630 236.0 */ 137, +/* 631 236.1 */ 178, +/* 632 236.2 */ 180, +/* 633 236.3 */ 147, +/* 634 237.0 */ 194, +/* 635 237.1 */ 178, +/* 636 237.2 */ 180, +/* 637 237.3 */ 147, +/* 638 238.0 */ 195, +/* 639 238.1 */ 178, +/* 640 238.2 */ 180, +/* 641 238.3 */ 147, +/* 642 239.0 */ 196, +/* 643 239.1 */ 178, +/* 644 239.2 */ 180, +/* 645 239.3 */ 147, +/* 646 240.0 */ 197, +/* 647 240.1 */ 178, +/* 648 240.2 */ 180, +/* 649 240.3 */ 147, +/* 650 241.0 */ 198, +/* 651 241.1 */ 178, +/* 652 241.2 */ 180, +/* 653 241.3 */ 147, +/* 654 242.0 */ 115, +/* 655 242.1 */ 175, +/* 656 242.2 */ 180, +/* 657 242.3 */ 147, +/* 658 243.0 */ 112, +/* 659 243.1 */ 175, +/* 660 243.2 */ 180, +/* 661 243.3 */ 147, +/* 662 244.0 */ 199, +/* 663 244.1 */ 178, +/* 664 244.2 */ 180, +/* 665 244.3 */ 147, +/* 666 245.0 */ 200, +/* 667 245.1 */ 178, +/* 668 245.2 */ 180, +/* 669 245.3 */ 147, +/* 670 246.0 */ 201, +/* 671 246.1 */ 202, +/* 672 247.0 */ 144, +/* 673 247.1 */ 203, +/* 674 248.0 */ 201, +/* 675 248.1 */ 204, +/* 676 249.0 */ 144, +/* 677 249.1 */ 205, +/* 678 250.0 */ 206, +/* 679 250.1 */ 207, +/* 680 251.0 */ 208, +/* 681 251.1 */ 209, +/* 682 252.0 */ 206, +/* 683 252.1 */ 210, +/* 684 253.0 */ 208, +/* 685 253.1 */ 211, +/* 686 254.0 */ 206, +/* 687 254.1 */ 113, +/* 688 255.0 */ 208, +/* 689 255.1 */ 117, +/* 690 256.0 */ 212, +/* 691 256.1 */ 213, +/* 692 257.0 */ 214, +/* 693 257.1 */ 213, +/* 694 258.0 */ 201, +/* 695 258.1 */ 215, +/* 696 259.0 */ 144, +/* 697 259.1 */ 216, +/* 698 260.0 */ 206, +/* 699 260.1 */ 217, +/* 700 261.0 */ 208, +/* 701 261.1 */ 218, +/* 702 262.0 */ 129, +/* 703 262.1 */ 120, +/* 704 262.2 */ 113, +/* 705 263.0 */ 137, +/* 706 263.1 */ 120, +/* 707 263.2 */ 117, +/* 708 264.0 */ 219, +/* 709 264.1 */ 113, +/* 710 265.0 */ 220, +/* 711 265.1 */ 113, +/* 712 266.0 */ 221, +/* 713 266.1 */ 222, +/* 714 266.2 */ 223, +/* 715 266.3 */ 224, +/* 716 266.4 */ 225, +/* 717 266.5 */ 110, +/* 718 267.0 */ 226, +/* 719 267.1 */ 227, +/* 720 267.2 */ 228, +/* 721 267.3 */ 229, +/* 722 267.4 */ 230, +/* 723 267.5 */ 110, +/* 724 268.0 */ 231, +/* 725 268.1 */ 120, +/* 726 269.0 */ 232, +/* 727 269.1 */ 120, +/* 728 270.0 */ 144, +/* 729 270.1 */ 115, +/* 730 271.0 */ 140, +/* 731 271.1 */ 115, +/* 732 272.0 */ 231, +/* 733 272.1 */ 122, +/* 734 273.0 */ 232, +/* 735 273.1 */ 116, +/* 736 274.0 */ 140, +/* 737 274.1 */ 118, +/* 738 275.0 */ 144, +/* 739 275.1 */ 124, +/* 740 276.0 */ 233, +/* 741 276.1 */ 126, +/* 742 277.0 */ 233, +/* 743 277.1 */ 127, +/* 744 278.0 */ 169, +/* 745 278.1 */ 129, +/* 746 279.0 */ 169, +/* 747 279.1 */ 130, +/* 748 280.0 */ 201, +/* 749 280.1 */ 234, +/* 750 281.0 */ 144, +/* 751 281.1 */ 235, +/* 752 282.0 */ 236, +/* 753 282.1 */ 206, +/* 754 283.0 */ 236, +/* 755 283.1 */ 237, +/* 756 284.0 */ 238, +/* 757 284.1 */ 126, +/* 758 285.0 */ 239, +/* 759 285.1 */ 129, +/* 760 286.0 */ 232, +/* 761 286.1 */ 138, +/* 762 287.0 */ 140, +/* 763 287.1 */ 139, +/* 764 288.0 */ 240, +/* 765 288.1 */ 120, +/* 766 289.0 */ 151, +/* 767 289.1 */ 241, +/* 768 290.0 */ 242, +/* 769 290.1 */ 120, +/* 770 291.0 */ 243, +/* 771 291.1 */ 120, +/* 772 292.0 */ 244, +/* 773 292.1 */ 219, +/* 774 293.0 */ 244, +/* 775 293.1 */ 245, +/* 776 294.0 */ 246, +/* 777 294.1 */ 247, +/* 778 295.0 */ 246, +/* 779 295.1 */ 248, +/* 780 296.0 */ 249, +/* 781 296.1 */ 120, +/* 782 297.0 */ 250, +/* 783 297.1 */ 120, +/* 784 298.0 */ 251, +/* 785 298.1 */ 219, +/* 786 299.0 */ 251, +/* 787 299.1 */ 245, +/* 788 300.0 */ 252, +/* 789 300.1 */ 253, +/* 790 301.0 */ 252, +/* 791 301.1 */ 254, +/* 792 302.0 */ 255, +/* 793 302.1 */ 247, +/* 794 303.0 */ 255, +/* 795 303.1 */ 248, +/* 796 304.0 */ 256, +/* 797 304.1 */ 120, +/* 798 305.0 */ 257, +/* 799 305.1 */ 120, +/* 800 306.0 */ 258, +/* 801 306.1 */ 219, +/* 802 307.0 */ 258, +/* 803 307.1 */ 245, +/* 804 308.0 */ 259, +/* 805 308.1 */ 120, +/* 806 309.0 */ 260, +/* 807 309.1 */ 120, +/* 808 310.0 */ 261, +/* 809 310.1 */ 219, +/* 810 311.0 */ 261, +/* 811 311.1 */ 245, +/* 812 312.0 */ 246, +/* 813 312.1 */ 253, +/* 814 313.0 */ 246, +/* 815 313.1 */ 254, +/* 816 314.0 */ 262, +/* 817 314.1 */ 120, +/* 818 315.0 */ 263, +/* 819 315.1 */ 120, +/* 820 316.0 */ 264, +/* 821 316.1 */ 219, +/* 822 317.0 */ 264, +/* 823 317.1 */ 245, +/* 824 318.0 */ 265, +/* 825 318.1 */ 253, +/* 826 319.0 */ 265, +/* 827 319.1 */ 254, +/* 828 320.0 */ 266, +/* 829 320.1 */ 120, +/* 830 321.0 */ 267, +/* 831 321.1 */ 77, +/* 832 322.0 */ 268, +/* 833 322.1 */ 73, +/* 834 323.0 */ 269, +/* 835 323.1 */ 270, +/* 836 324.0 */ 271, +/* 837 324.1 */ 272, +/* 838 325.0 */ 273, +/* 839 326.0 */ 137, +/* 840 327.0 */ 129, +/* 841 328.0 */ 129, +/* 842 328.1 */ 118, +/* 843 329.0 */ 137, +/* 844 329.1 */ 124, +/* 845 330.0 */ 137, +/* 846 330.1 */ 129, +/* 847 331.0 */ 274, +/* 848 332.0 */ 113, +/* 849 333.0 */ 275, +/* 850 333.1 */ 276, +/* 851 334.0 */ 277, +/* 852 334.1 */ 276, +/* 853 335.0 */ 212, +/* 854 335.1 */ 278, +/* 855 336.0 */ 214, +/* 856 336.1 */ 278, +/* 857 337.0 */ 279, +/* 858 337.1 */ 280, +/* 859 337.2 */ 281, +/* 860 338.0 */ 282, +/* 861 338.1 */ 280, +/* 862 338.2 */ 281, +/* 863 339.0 */ 283, +/* 864 339.1 */ 280, +/* 865 339.2 */ 281, +/* 866 340.0 */ 279, +/* 867 340.1 */ 280, +/* 868 341.0 */ 277, +/* 869 341.1 */ 284, +/* 870 342.0 */ 275, +/* 871 342.1 */ 284, +/* 872 343.0 */ 126, +/* 873 344.0 */ 285, +/* 874 344.1 */ 286, +/* 875 344.2 */ 287, +/* 876 344.3 */ 288, +/* 877 344.4 */ 289, +/* 878 345.0 */ 290, +/* 879 345.1 */ 291, +/* 880 346.0 */ 290, +/* 881 346.1 */ 292, +/* 882 347.0 */ 293, +/* 883 347.1 */ 294, +/* 884 348.0 */ 293, +/* 885 348.1 */ 295, +/* 886 349.0 */ 296, +/* 887 349.1 */ 134, +/* 888 350.0 */ 296, +/* 889 350.1 */ 297, +/* 890 350.2 */ 135, +/* 891 351.0 */ 298, +/* 892 351.1 */ 299, +/* 893 351.2 */ 300, +/* 894 351.3 */ 301, +/* 895 351.4 */ 302, +/* 896 351.5 */ 303, +/* 897 351.6 */ 304, +/* 898 351.7 */ 305, +/* 899 351.8 */ 306, +/* 900 351.9 */ 307, +/* 901 351.10 */ 147, +/* 902 352.0 */ 298, +/* 903 352.1 */ 308, +/* 904 352.2 */ 224, +/* 905 352.3 */ 309, +/* 906 352.4 */ 310, +/* 907 352.5 */ 311, +/* 908 352.6 */ 312, +/* 909 352.7 */ 313, +/* 910 352.8 */ 314, +/* 911 352.9 */ 307, +/* 912 352.10 */ 147, +/* 913 353.0 */ 315, +/* 914 353.1 */ 162, +/* 915 353.2 */ 316, +/* 916 353.3 */ 317, +/* 917 353.4 */ 318, +/* 918 353.5 */ 319, +/* 919 353.6 */ 320, +/* 920 353.7 */ 321, +/* 921 353.8 */ 322, +/* 922 353.9 */ 147, +/* 923 354.0 */ 315, +/* 924 354.1 */ 323, +/* 925 354.2 */ 287, +/* 926 354.3 */ 324, +/* 927 354.4 */ 325, +/* 928 354.5 */ 326, +/* 929 354.6 */ 327, +/* 930 354.7 */ 328, +/* 931 354.8 */ 322, +/* 932 354.9 */ 147, +/* 933 355.0 */ 118, +/* 934 355.1 */ 329, +/* 935 356.0 */ 118, +/* 936 356.1 */ 330, +/* 937 357.0 */ 331, +/* 938 357.1 */ 332, +/* 939 357.2 */ 117, +/* 940 358.0 */ 333, +/* 941 358.1 */ 334, +/* 942 358.2 */ 123, +/* 943 359.0 */ 169, +/* 944 359.1 */ 335, +/* 945 360.0 */ 169, +/* 946 360.1 */ 336, +/* 947 361.0 */ 337, +/* 948 361.1 */ 338, +/* 949 361.2 */ 339, +/* 950 361.3 */ 340, +/* 951 361.4 */ 341, +/* 952 362.0 */ 342, +/* 953 362.1 */ 343, +/* 954 362.2 */ 339, +/* 955 362.3 */ 344, +/* 956 363.0 */ 345, +/* 957 363.1 */ 338, +/* 958 363.2 */ 339, +/* 959 363.3 */ 340, +/* 960 363.4 */ 341, +/* 961 364.0 */ 346, +/* 962 364.1 */ 343, +/* 963 364.2 */ 339, +/* 964 364.3 */ 344, +/* 965 365.0 */ 347, +/* 966 365.1 */ 338, +/* 967 365.2 */ 339, +/* 968 365.3 */ 340, +/* 969 365.4 */ 341, +/* 970 366.0 */ 348, +/* 971 366.1 */ 343, +/* 972 366.2 */ 339, +/* 973 366.3 */ 344, +/* 974 367.0 */ 339, +/* 975 367.1 */ 349, +/* 976 367.2 */ 350, +/* 977 367.3 */ 340, +/* 978 367.4 */ 341, +/* 979 368.0 */ 339, +/* 980 368.1 */ 351, +/* 981 368.2 */ 352, +/* 982 368.3 */ 344, +/* 983 369.0 */ 339, +/* 984 369.1 */ 353, +/* 985 369.2 */ 350, +/* 986 369.3 */ 340, +/* 987 369.4 */ 341, +/* 988 370.0 */ 339, +/* 989 370.1 */ 354, +/* 990 370.2 */ 352, +/* 991 370.3 */ 344, +/* 992 371.0 */ 339, +/* 993 371.1 */ 355, +/* 994 371.2 */ 350, +/* 995 371.3 */ 340, +/* 996 371.4 */ 341, +/* 997 372.0 */ 339, +/* 998 372.1 */ 356, +/* 999 372.2 */ 352, +/* 1000 372.3 */ 344, +/* 1001 373.0 */ 189, +/* 1002 373.1 */ 188, +/* 1003 373.2 */ 344, +/* 1004 374.0 */ 189, +/* 1005 374.1 */ 187, +/* 1006 374.2 */ 344, +/* 1007 375.0 */ 183, +/* 1008 375.1 */ 188, +/* 1009 375.2 */ 344, +/* 1010 376.0 */ 181, +/* 1011 376.1 */ 187, +/* 1012 376.2 */ 344, +/* 1013 377.0 */ 111, +/* 1014 377.1 */ 125, +/* 1015 378.0 */ 119, +/* 1016 378.1 */ 357, +/* 1017 379.0 */ 114, +/* 1018 379.1 */ 128, +/* 1019 380.0 */ 121, +/* 1020 380.1 */ 358, +/* 1021 381.0 */ 174, +/* 1022 381.1 */ 359, +/* 1023 382.0 */ 169, +/* 1024 382.1 */ 360, +/* 1025 383.0 */ 361, +/* 1026 383.1 */ 163, +/* 1027 384.0 */ 362, +/* 1028 384.1 */ 308, +/* 1029 385.0 */ 285, +/* 1030 385.1 */ 299, +/* 1031 386.0 */ 363, +/* 1032 386.1 */ 299, +/* 1033 387.0 */ 364, +/* 1034 387.1 */ 365, +/* 1035 388.0 */ 366, +/* 1036 388.1 */ 308, +/* 1037 389.0 */ 190, +/* 1038 389.1 */ 367, +/* 1039 389.2 */ 186, +/* 1040 389.3 */ 368, +/* 1041 389.4 */ 143, +/* 1042 390.0 */ 191, +/* 1043 390.1 */ 192, +/* 1044 390.2 */ 367, +/* 1045 390.3 */ 369, +/* 1046 390.4 */ 370, +/* 1047 390.5 */ 147, +/* 1048 391.0 */ 371, +/* 1049 391.1 */ 346, +/* 1050 391.2 */ 147, +/* 1051 391.3 */ 344, +/* 1052 392.0 */ 372, +/* 1053 392.1 */ 348, +/* 1054 392.2 */ 147, +/* 1055 392.3 */ 344, +/* 1056 393.0 */ 373, +/* 1057 393.1 */ 374, +/* 1058 393.2 */ 147, +/* 1059 393.3 */ 344, +/* 1060 394.0 */ 375, +/* 1061 394.1 */ 354, +/* 1062 394.2 */ 147, +/* 1063 394.3 */ 134, +/* 1064 395.0 */ 376, +/* 1065 395.1 */ 356, +/* 1066 395.2 */ 147, +/* 1067 395.3 */ 134, +/* 1068 396.0 */ 377, +/* 1069 396.1 */ 378, +/* 1070 396.2 */ 147, +/* 1071 396.3 */ 134, +/* 1072 397.0 */ 379, +/* 1073 397.1 */ 117, +/* 1074 398.0 */ 380, +/* 1075 398.1 */ 344, +/* 1076 399.0 */ 337, +/* 1077 399.1 */ 338, +/* 1078 399.2 */ 381, +/* 1079 399.3 */ 382, +/* 1080 399.4 */ 383, +/* 1081 399.5 */ 344, +/* 1082 400.0 */ 342, +/* 1083 400.1 */ 343, +/* 1084 400.2 */ 384, +/* 1085 400.3 */ 385, +/* 1086 400.4 */ 386, +/* 1087 401.0 */ 345, +/* 1088 401.1 */ 338, +/* 1089 401.2 */ 387, +/* 1090 401.3 */ 382, +/* 1091 401.4 */ 383, +/* 1092 401.5 */ 344, +/* 1093 402.0 */ 346, +/* 1094 402.1 */ 343, +/* 1095 402.2 */ 388, +/* 1096 402.3 */ 385, +/* 1097 402.4 */ 386, +/* 1098 403.0 */ 347, +/* 1099 403.1 */ 338, +/* 1100 403.2 */ 389, +/* 1101 403.3 */ 382, +/* 1102 403.4 */ 383, +/* 1103 403.5 */ 344, +/* 1104 404.0 */ 348, +/* 1105 404.1 */ 343, +/* 1106 404.2 */ 390, +/* 1107 404.3 */ 385, +/* 1108 404.4 */ 386, +/* 1109 405.0 */ 391, +/* 1110 405.1 */ 338, +/* 1111 405.2 */ 392, +/* 1112 405.3 */ 382, +/* 1113 405.4 */ 383, +/* 1114 405.5 */ 344, +/* 1115 406.0 */ 374, +/* 1116 406.1 */ 343, +/* 1117 406.2 */ 393, +/* 1118 406.3 */ 385, +/* 1119 406.4 */ 386, +/* 1120 407.0 */ 349, +/* 1121 407.1 */ 350, +/* 1122 407.2 */ 381, +/* 1123 407.3 */ 394, +/* 1124 407.4 */ 383, +/* 1125 407.5 */ 159, +/* 1126 408.0 */ 351, +/* 1127 408.1 */ 352, +/* 1128 408.2 */ 384, +/* 1129 408.3 */ 395, +/* 1130 408.4 */ 133, +/* 1131 409.0 */ 353, +/* 1132 409.1 */ 350, +/* 1133 409.2 */ 387, +/* 1134 409.3 */ 394, +/* 1135 409.4 */ 383, +/* 1136 409.5 */ 159, +/* 1137 410.0 */ 354, +/* 1138 410.1 */ 352, +/* 1139 410.2 */ 388, +/* 1140 410.3 */ 395, +/* 1141 410.4 */ 133, +/* 1142 411.0 */ 355, +/* 1143 411.1 */ 350, +/* 1144 411.2 */ 389, +/* 1145 411.3 */ 394, +/* 1146 411.4 */ 383, +/* 1147 411.5 */ 159, +/* 1148 412.0 */ 356, +/* 1149 412.1 */ 352, +/* 1150 412.2 */ 390, +/* 1151 412.3 */ 395, +/* 1152 412.4 */ 133, +/* 1153 413.0 */ 396, +/* 1154 413.1 */ 350, +/* 1155 413.2 */ 392, +/* 1156 413.3 */ 394, +/* 1157 413.4 */ 383, +/* 1158 413.5 */ 159, +/* 1159 414.0 */ 378, +/* 1160 414.1 */ 352, +/* 1161 414.2 */ 393, +/* 1162 414.3 */ 395, +/* 1163 414.4 */ 133, +/* 1164 415.0 */ 337, +/* 1165 415.1 */ 338, +/* 1166 415.2 */ 161, +/* 1167 415.3 */ 340, +/* 1168 415.4 */ 341, +/* 1169 416.0 */ 342, +/* 1170 416.1 */ 343, +/* 1171 416.2 */ 161, +/* 1172 416.3 */ 344, +/* 1173 417.0 */ 345, +/* 1174 417.1 */ 338, +/* 1175 417.2 */ 282, +/* 1176 417.3 */ 340, +/* 1177 417.4 */ 341, +/* 1178 418.0 */ 346, +/* 1179 418.1 */ 343, +/* 1180 418.2 */ 282, +/* 1181 418.3 */ 344, +/* 1182 419.0 */ 347, +/* 1183 419.1 */ 338, +/* 1184 419.2 */ 279, +/* 1185 419.3 */ 340, +/* 1186 419.4 */ 341, +/* 1187 420.0 */ 348, +/* 1188 420.1 */ 343, +/* 1189 420.2 */ 279, +/* 1190 420.3 */ 344, +/* 1191 421.0 */ 391, +/* 1192 421.1 */ 338, +/* 1193 421.2 */ 283, +/* 1194 421.3 */ 340, +/* 1195 421.4 */ 341, +/* 1196 422.0 */ 374, +/* 1197 422.1 */ 343, +/* 1198 422.2 */ 283, +/* 1199 422.3 */ 344, +/* 1200 423.0 */ 397, +/* 1201 423.1 */ 349, +/* 1202 423.2 */ 350, +/* 1203 423.3 */ 340, +/* 1204 423.4 */ 341, +/* 1205 424.0 */ 398, +/* 1206 424.1 */ 351, +/* 1207 424.2 */ 352, +/* 1208 424.3 */ 344, +/* 1209 425.0 */ 399, +/* 1210 425.1 */ 353, +/* 1211 425.2 */ 350, +/* 1212 425.3 */ 340, +/* 1213 425.4 */ 341, +/* 1214 426.0 */ 361, +/* 1215 426.1 */ 354, +/* 1216 426.2 */ 352, +/* 1217 426.3 */ 344, +/* 1218 427.0 */ 400, +/* 1219 427.1 */ 355, +/* 1220 427.2 */ 350, +/* 1221 427.3 */ 340, +/* 1222 427.4 */ 341, +/* 1223 428.0 */ 285, +/* 1224 428.1 */ 356, +/* 1225 428.2 */ 352, +/* 1226 428.3 */ 344, +/* 1227 429.0 */ 401, +/* 1228 429.1 */ 396, +/* 1229 429.2 */ 350, +/* 1230 429.3 */ 340, +/* 1231 429.4 */ 341, +/* 1232 430.0 */ 362, +/* 1233 430.1 */ 378, +/* 1234 430.2 */ 352, +/* 1235 430.3 */ 344, +/* 1236 431.0 */ 161, +/* 1237 431.1 */ 349, +/* 1238 431.2 */ 338, +/* 1239 431.3 */ 340, +/* 1240 431.4 */ 160, +/* 1241 432.0 */ 161, +/* 1242 432.1 */ 351, +/* 1243 432.2 */ 343, +/* 1244 432.3 */ 134, +/* 1245 433.0 */ 282, +/* 1246 433.1 */ 353, +/* 1247 433.2 */ 338, +/* 1248 433.3 */ 340, +/* 1249 433.4 */ 160, +/* 1250 434.0 */ 282, +/* 1251 434.1 */ 354, +/* 1252 434.2 */ 343, +/* 1253 434.3 */ 134, +/* 1254 435.0 */ 279, +/* 1255 435.1 */ 355, +/* 1256 435.2 */ 338, +/* 1257 435.3 */ 340, +/* 1258 435.4 */ 160, +/* 1259 436.0 */ 279, +/* 1260 436.1 */ 356, +/* 1261 436.2 */ 343, +/* 1262 436.3 */ 134, +/* 1263 437.0 */ 283, +/* 1264 437.1 */ 396, +/* 1265 437.2 */ 338, +/* 1266 437.3 */ 340, +/* 1267 437.4 */ 160, +/* 1268 438.0 */ 283, +/* 1269 438.1 */ 378, +/* 1270 438.2 */ 343, +/* 1271 438.3 */ 134, +/* 1272 439.0 */ 192, +/* 1273 439.1 */ 141, +/* 1274 439.2 */ 186, +/* 1275 439.3 */ 146, +/* 1276 439.4 */ 147, +/* 1277 440.0 */ 141, +/* 1278 440.1 */ 186, +/* 1279 440.2 */ 146, +/* 1280 440.3 */ 147, +/* 1281 441.0 */ 402, +/* 1282 441.1 */ 403, +/* 1283 441.2 */ 404, +/* 1284 442.0 */ 402, +/* 1285 442.1 */ 403, +/* 1286 442.2 */ 405, +/* 1287 443.0 */ 192, +/* 1288 443.1 */ 406, +/* 1289 443.2 */ 175, +/* 1290 443.3 */ 407, +/* 1291 443.4 */ 180, +/* 1292 443.5 */ 147, +/* 1293 444.0 */ 408, +/* 1294 444.1 */ 409, +/* 1295 444.2 */ 410, +/* 1296 444.3 */ 411, +/* 1297 445.0 */ 192, +/* 1298 445.1 */ 412, +/* 1299 445.2 */ 186, +/* 1300 445.3 */ 413, +/* 1301 445.4 */ 147, +/* 1302 446.0 */ 412, +/* 1303 446.1 */ 186, +/* 1304 446.2 */ 413, +/* 1305 446.3 */ 147, +/* 1306 447.0 */ 185, +/* 1307 447.1 */ 134, +/* 1308 448.0 */ 120, +/* 1309 448.1 */ 185, +/* 1310 448.2 */ 134, +/* 1311 449.0 */ 193, +/* 1312 449.1 */ 134, +/* 1313 450.0 */ 414, +/* 1314 450.1 */ 186, +/* 1315 450.2 */ 415, +/* 1316 450.3 */ 147, +/* 1317 450.4 */ 135, +/* 1318 451.0 */ 414, +/* 1319 451.1 */ 416, +/* 1320 451.2 */ 415, +/* 1321 451.3 */ 147, +/* 1322 451.4 */ 135, +/* 1323 452.0 */ 112, +/* 1324 452.1 */ 296, +/* 1325 452.2 */ 417, +/* 1326 452.3 */ 123, +/* 1327 453.0 */ 112, +/* 1328 453.1 */ 296, +/* 1329 453.2 */ 297, +/* 1330 453.3 */ 123, +/* 1331 454.0 */ 398, +/* 1332 454.1 */ 344, +/* 1333 455.0 */ 351, +/* 1334 455.1 */ 418, +/* 1335 455.2 */ 398, +/* 1336 456.0 */ 189, +/* 1337 456.1 */ 419, +/* 1338 456.2 */ 176, +/* 1339 456.3 */ 341, +/* 1340 457.0 */ 189, +/* 1341 457.1 */ 419, +/* 1342 457.2 */ 176, +/* 1343 458.0 */ 189, +/* 1344 458.1 */ 420, +/* 1345 458.2 */ 421, +/* 1346 459.0 */ 189, +/* 1347 459.1 */ 422, +/* 1348 459.2 */ 182, +/* 1349 460.0 */ 189, +/* 1350 460.1 */ 422, +/* 1351 460.2 */ 184, +/* 1352 461.0 */ 189, +/* 1353 461.1 */ 423, +/* 1354 461.2 */ 184, +/* 1355 462.0 */ 238, +/* 1356 462.1 */ 120, +/* 1357 462.2 */ 344, +/* 1358 463.0 */ 424, +/* 1359 463.1 */ 120, +/* 1360 463.2 */ 344, +/* 1361 464.0 */ 238, +/* 1362 464.1 */ 425, +/* 1363 464.2 */ 341, +/* 1364 465.0 */ 424, +/* 1365 465.1 */ 425, +/* 1366 465.2 */ 341, +/* 1367 466.0 */ 120, +/* 1368 466.1 */ 138, +/* 1369 466.2 */ 344, +/* 1370 467.0 */ 120, +/* 1371 467.1 */ 426, +/* 1372 467.2 */ 344, +/* 1373 468.0 */ 427, +/* 1374 468.1 */ 428, +/* 1375 468.2 */ 341, +/* 1376 469.0 */ 427, +/* 1377 469.1 */ 429, +/* 1378 469.2 */ 341, +/* 1379 470.0 */ 185, +/* 1380 471.0 */ 133, +/* 1381 472.0 */ 430, +/* 1382 472.1 */ 206, +/* 1383 472.2 */ 117, +/* 1384 473.0 */ 430, +/* 1385 473.1 */ 130, +/* 1386 473.2 */ 123, +/* 1387 474.0 */ 128, +/* 1388 474.1 */ 206, +/* 1389 474.2 */ 117, +/* 1390 475.0 */ 128, +/* 1391 475.1 */ 336, +/* 1392 475.2 */ 123, +/* 1393 476.0 */ 431, +/* 1394 476.1 */ 432, +/* 1395 476.2 */ 433, +/* 1396 476.3 */ 97, +/* 1397 477.0 */ 193, +/* 1398 477.1 */ 280, +/* 1399 477.2 */ 123, +/* 1400 478.0 */ 431, +/* 1401 478.1 */ 434, +/* 1402 478.2 */ 435, +/* 1403 478.3 */ 97, +/* 1404 479.0 */ 436, +/* 1405 479.1 */ 437, +/* 1406 480.0 */ 436, +/* 1407 480.1 */ 438, +/* 1408 481.0 */ 439, +/* 1409 481.1 */ 295, +/* 1410 482.0 */ 440, +/* 1411 482.1 */ 441, +/* 1412 483.0 */ 442, +/* 1413 483.1 */ 247, +/* 1414 484.0 */ 442, +/* 1415 484.1 */ 443, +/* 1416 485.0 */ 442, +/* 1417 485.1 */ 248, +/* 1418 486.0 */ 444, +/* 1419 486.1 */ 445, +/* 1420 487.0 */ 446, +/* 1421 487.1 */ 447, +/* 1422 488.0 */ 448, +/* 1423 488.1 */ 449, +/* 1424 489.0 */ 450, +/* 1425 489.1 */ 451, +/* 1426 490.0 */ 452, +/* 1427 490.1 */ 453, +/* 1428 491.0 */ 452, +/* 1429 491.1 */ 454, +/* 1430 492.0 */ 455, +/* 1431 492.1 */ 456, +/* 1432 493.0 */ 457, +/* 1433 493.1 */ 458, +/* 1434 494.0 */ 459, +/* 1435 494.1 */ 219, +/* 1436 495.0 */ 220, +/* 1437 495.1 */ 460, +/* 1438 496.0 */ 461, +/* 1439 496.1 */ 247, +/* 1440 497.0 */ 461, +/* 1441 497.1 */ 443, +/* 1442 498.0 */ 462, +/* 1443 498.1 */ 463, +/* 1444 499.0 */ 459, +/* 1445 499.1 */ 464, +/* 1446 500.0 */ 465, +/* 1447 500.1 */ 460, +/* 1448 501.0 */ 466, +/* 1449 501.1 */ 467, +/* 1450 502.0 */ 468, +/* 1451 502.1 */ 219, +/* 1452 503.0 */ 468, +/* 1453 503.1 */ 443, +/* 1454 504.0 */ 469, +/* 1455 504.1 */ 470, +/* 1456 505.0 */ 469, +/* 1457 505.1 */ 471, +/* 1458 506.0 */ 472, +/* 1459 506.1 */ 473, +/* 1460 507.0 */ 474, +/* 1461 507.1 */ 473, +/* 1462 508.0 */ 475, +/* 1463 508.1 */ 470, +/* 1464 509.0 */ 475, +/* 1465 509.1 */ 471, +/* 1466 510.0 */ 472, +/* 1467 510.1 */ 476, +/* 1468 511.0 */ 474, +/* 1469 511.1 */ 476, +/* 1470 512.0 */ 279, +/* 1471 512.1 */ 477, +/* 1472 512.2 */ 224, +/* 1473 512.3 */ 478, +/* 1474 513.0 */ 285, +/* 1475 513.1 */ 286, +/* 1476 513.2 */ 479, +/* 1477 514.0 */ 285, +/* 1478 514.1 */ 286, +/* 1479 514.2 */ 224, +/* 1480 514.3 */ 480, +/* 1481 515.0 */ 193, +/* 1482 515.1 */ 481, +/* 1483 515.2 */ 123, +/* 1484 516.0 */ 431, +/* 1485 516.1 */ 482, +/* 1486 516.2 */ 123, +/* 1487 517.0 */ 193, +/* 1488 517.1 */ 481, +/* 1489 517.2 */ 224, +/* 1490 517.3 */ 309, +/* 1491 518.0 */ 431, +/* 1492 518.1 */ 482, +/* 1493 518.2 */ 229, +/* 1494 518.3 */ 483, +/* 1495 519.0 */ 430, +/* 1496 519.1 */ 129, +/* 1497 519.2 */ 344, +/* 1498 520.0 */ 430, +/* 1499 520.1 */ 130, +/* 1500 520.2 */ 341, +/* 1501 521.0 */ 484, +/* 1502 521.1 */ 438, +/* 1503 522.0 */ 485, +/* 1504 522.1 */ 486, +/* 1505 523.0 */ 485, +/* 1506 523.1 */ 487, +/* 1507 524.0 */ 446, +/* 1508 524.1 */ 445, +/* 1509 525.0 */ 484, +/* 1510 525.1 */ 454, +/* 1511 526.0 */ 488, +/* 1512 526.1 */ 489, +/* 1513 527.0 */ 488, +/* 1514 527.1 */ 490, +/* 1515 528.0 */ 459, +/* 1516 528.1 */ 463, +/* 1517 529.0 */ 491, +/* 1518 529.1 */ 492, +/* 1519 530.0 */ 491, +/* 1520 530.1 */ 493, +/* 1521 531.0 */ 246, +/* 1522 531.1 */ 443, +/* 1523 532.0 */ 244, +/* 1524 532.1 */ 494, +/* 1525 533.0 */ 244, +/* 1526 533.1 */ 495, +/* 1527 534.0 */ 258, +/* 1528 534.1 */ 496, +/* 1529 535.0 */ 258, +/* 1530 535.1 */ 497, +/* 1531 536.0 */ 251, +/* 1532 536.1 */ 498, +/* 1533 537.0 */ 251, +/* 1534 537.1 */ 499, +/* 1535 538.0 */ 252, +/* 1536 538.1 */ 500, +/* 1537 539.0 */ 252, +/* 1538 539.1 */ 501, +/* 1539 540.0 */ 502, +/* 1540 540.1 */ 503, +/* 1541 541.0 */ 502, +/* 1542 541.1 */ 504, +/* 1543 542.0 */ 505, +/* 1544 542.1 */ 506, +/* 1545 543.0 */ 505, +/* 1546 543.1 */ 507, +/* 1547 544.0 */ 261, +/* 1548 544.1 */ 508, +/* 1549 545.0 */ 261, +/* 1550 545.1 */ 509, +/* 1551 546.0 */ 510, +/* 1552 546.1 */ 511, +/* 1553 546.2 */ 120, +/* 1554 547.0 */ 510, +/* 1555 547.1 */ 512, +/* 1556 547.2 */ 120, +/* 1557 548.0 */ 513, +/* 1558 548.1 */ 514, +/* 1559 548.2 */ 120, +/* 1560 549.0 */ 513, +/* 1561 549.1 */ 515, +/* 1562 549.2 */ 120, +/* 1563 550.0 */ 516, +/* 1564 550.1 */ 517, +/* 1565 550.2 */ 120, +/* 1566 551.0 */ 516, +/* 1567 551.1 */ 518, +/* 1568 551.2 */ 120, +/* 1569 552.0 */ 232, +/* 1570 552.1 */ 386, +/* 1571 553.0 */ 231, +/* 1572 553.1 */ 344, +/* 1573 554.0 */ 519, +/* 1574 554.1 */ 520, +/* 1575 554.2 */ 521, +/* 1576 554.3 */ 324, +/* 1577 555.0 */ 522, +/* 1578 555.1 */ 116, +/* 1579 555.2 */ 523, +/* 1580 555.3 */ 123, +/* 1581 556.0 */ 524, +/* 1582 556.1 */ 118, +/* 1583 556.2 */ 525, +/* 1584 556.3 */ 123, +/* 1585 557.0 */ 526, +/* 1586 557.1 */ 122, +/* 1587 557.2 */ 527, +/* 1588 557.3 */ 97, +/* 1589 558.0 */ 528, +/* 1590 558.1 */ 124, +/* 1591 558.2 */ 529, +/* 1592 558.3 */ 97, +/* 1593 559.0 */ 169, +/* 1594 559.1 */ 190, +/* 1595 559.2 */ 530, +/* 1596 560.0 */ 169, +/* 1597 560.1 */ 190, +/* 1598 560.2 */ 531, +/* 1599 561.0 */ 169, +/* 1600 561.1 */ 190, +/* 1601 561.2 */ 532, +/* 1602 562.0 */ 169, +/* 1603 562.1 */ 126, +/* 1604 563.0 */ 169, +/* 1605 563.1 */ 127, +/* 1606 564.0 */ 169, +/* 1607 564.1 */ 206, +/* 1608 565.0 */ 169, +/* 1609 565.1 */ 237, +/* 1610 566.0 */ 111, +/* 1611 566.1 */ 125, +/* 1612 566.2 */ 117, +/* 1613 567.0 */ 114, +/* 1614 567.1 */ 128, +/* 1615 567.2 */ 117, +/* 1616 568.0 */ 119, +/* 1617 568.1 */ 357, +/* 1618 568.2 */ 123, +/* 1619 569.0 */ 121, +/* 1620 569.1 */ 358, +/* 1621 569.2 */ 123, +/* 1622 570.0 */ 442, +/* 1623 570.1 */ 437, +/* 1624 570.2 */ 120, +/* 1625 571.0 */ 442, +/* 1626 571.1 */ 438, +/* 1627 571.2 */ 120, +/* 1628 572.0 */ 271, +/* 1629 572.1 */ 533, +/* 1630 573.0 */ 220, +/* 1631 573.1 */ 534, +/* 1632 574.0 */ 244, +/* 1633 574.1 */ 535, +/* 1634 574.2 */ 120, +/* 1635 575.0 */ 244, +/* 1636 575.1 */ 470, +/* 1637 575.2 */ 120, +/* 1638 576.0 */ 246, +/* 1639 576.1 */ 206, +/* 1640 576.2 */ 120, +/* 1641 577.0 */ 246, +/* 1642 577.1 */ 470, +/* 1643 577.2 */ 120, +/* 1644 578.0 */ 484, +/* 1645 578.1 */ 512, +/* 1646 578.2 */ 120, +/* 1647 579.0 */ 484, +/* 1648 579.1 */ 248, +/* 1649 579.2 */ 120, +/* 1650 580.0 */ 536, +/* 1651 580.1 */ 445, +/* 1652 580.2 */ 120, +/* 1653 581.0 */ 536, +/* 1654 581.1 */ 447, +/* 1655 581.2 */ 120, +/* 1656 582.0 */ 461, +/* 1657 582.1 */ 453, +/* 1658 582.2 */ 120, +/* 1659 583.0 */ 461, +/* 1660 583.1 */ 454, +/* 1661 583.2 */ 120, +/* 1662 584.0 */ 537, +/* 1663 584.1 */ 463, +/* 1664 584.2 */ 120, +/* 1665 585.0 */ 537, +/* 1666 585.1 */ 464, +/* 1667 585.2 */ 120, +/* 1668 586.0 */ 264, +/* 1669 586.1 */ 538, +/* 1670 587.0 */ 264, +/* 1671 587.1 */ 539, +/* 1672 588.0 */ 484, +/* 1673 588.1 */ 504, +/* 1674 589.0 */ 484, +/* 1675 589.1 */ 507, +/* 1676 590.0 */ 461, +/* 1677 590.1 */ 453, +/* 1678 591.0 */ 461, +/* 1679 591.1 */ 454, +/* 1680 592.0 */ 540, +/* 1681 592.1 */ 539, +/* 1682 593.0 */ 442, +/* 1683 593.1 */ 437, +/* 1684 594.0 */ 442, +/* 1685 594.1 */ 438, +/* 1686 595.0 */ 541, +/* 1687 595.1 */ 542, +/* 1688 596.0 */ 543, +/* 1689 596.1 */ 219, +/* 1690 597.0 */ 544, +/* 1691 597.1 */ 545, +/* 1692 598.0 */ 544, +/* 1693 598.1 */ 546, +/* 1694 599.0 */ 255, +/* 1695 599.1 */ 517, +/* 1696 600.0 */ 255, +/* 1697 600.1 */ 518, +/* 1698 601.0 */ 244, +/* 1699 601.1 */ 511, +/* 1700 602.0 */ 244, +/* 1701 602.1 */ 512, +/* 1702 603.0 */ 220, +/* 1703 603.1 */ 547, +/* 1704 604.0 */ 468, +/* 1705 604.1 */ 453, +/* 1706 605.0 */ 468, +/* 1707 605.1 */ 454, +/* 1708 606.0 */ 548, +/* 1709 606.1 */ 549, +/* 1710 607.0 */ 452, +/* 1711 607.1 */ 508, +/* 1712 608.0 */ 452, +/* 1713 608.1 */ 550, +/* 1714 609.0 */ 258, +/* 1715 609.1 */ 551, +/* 1716 610.0 */ 258, +/* 1717 610.1 */ 552, +/* 1718 611.0 */ 543, +/* 1719 611.1 */ 245, +/* 1720 612.0 */ 553, +/* 1721 612.1 */ 504, +/* 1722 612.2 */ 374, +/* 1723 612.3 */ 554, +/* 1724 613.0 */ 549, +/* 1725 613.1 */ 248, +/* 1726 613.2 */ 555, +/* 1727 613.3 */ 554, +/* 1728 614.0 */ 452, +/* 1729 614.1 */ 247, +/* 1730 615.0 */ 533, +/* 1731 615.1 */ 269, +/* 1732 616.0 */ 533, +/* 1733 616.1 */ 470, +/* 1734 617.0 */ 556, +/* 1735 617.1 */ 508, +/* 1736 618.0 */ 556, +/* 1737 618.1 */ 509, +/* 1738 619.0 */ 548, +/* 1739 619.1 */ 295, +/* 1740 620.0 */ 557, +/* 1741 620.1 */ 292, +/* 1742 621.0 */ 557, +/* 1743 621.1 */ 291, +/* 1744 622.0 */ 449, +/* 1745 622.1 */ 445, +/* 1746 622.2 */ 117, +/* 1747 623.0 */ 449, +/* 1748 623.1 */ 447, +/* 1749 623.2 */ 123, +/* 1750 624.0 */ 536, +/* 1751 624.1 */ 269, +/* 1752 625.0 */ 536, +/* 1753 625.1 */ 558, +/* 1754 626.0 */ 536, +/* 1755 626.1 */ 508, +/* 1756 627.0 */ 536, +/* 1757 627.1 */ 559, +/* 1758 628.0 */ 560, +/* 1759 628.1 */ 445, +/* 1760 629.0 */ 560, +/* 1761 629.1 */ 447, +/* 1762 630.0 */ 561, +/* 1763 630.1 */ 445, +/* 1764 631.0 */ 561, +/* 1765 631.1 */ 447, +/* 1766 632.0 */ 452, +/* 1767 632.1 */ 509, +/* 1768 633.0 */ 548, +/* 1769 633.1 */ 456, +/* 1770 634.0 */ 557, +/* 1771 634.1 */ 453, +/* 1772 635.0 */ 557, +/* 1773 635.1 */ 454, +/* 1774 636.0 */ 460, +/* 1775 636.1 */ 463, +/* 1776 636.2 */ 117, +/* 1777 637.0 */ 460, +/* 1778 637.1 */ 464, +/* 1779 637.2 */ 123, +/* 1780 638.0 */ 537, +/* 1781 638.1 */ 269, +/* 1782 639.0 */ 537, +/* 1783 639.1 */ 558, +/* 1784 640.0 */ 537, +/* 1785 640.1 */ 219, +/* 1786 641.0 */ 537, +/* 1787 641.1 */ 562, +/* 1788 642.0 */ 560, +/* 1789 642.1 */ 463, +/* 1790 643.0 */ 560, +/* 1791 643.1 */ 464, +/* 1792 644.0 */ 561, +/* 1793 644.1 */ 463, +/* 1794 645.0 */ 561, +/* 1795 645.1 */ 464, +/* 1796 646.0 */ 452, +/* 1797 646.1 */ 292, +/* 1798 647.0 */ 452, +/* 1799 647.1 */ 291, +/* 1800 648.0 */ 436, +/* 1801 648.1 */ 247, +/* 1802 649.0 */ 436, +/* 1803 649.1 */ 248, +/* 1804 650.0 */ 536, +/* 1805 650.1 */ 445, +/* 1806 651.0 */ 536, +/* 1807 651.1 */ 447, +/* 1808 652.0 */ 537, +/* 1809 652.1 */ 445, +/* 1810 653.0 */ 537, +/* 1811 653.1 */ 447, +/* 1812 654.0 */ 468, +/* 1813 654.1 */ 437, +/* 1814 655.0 */ 468, +/* 1815 655.1 */ 438, +/* 1816 656.0 */ 436, +/* 1817 656.1 */ 453, +/* 1818 657.0 */ 436, +/* 1819 657.1 */ 454, +/* 1820 658.0 */ 537, +/* 1821 658.1 */ 463, +/* 1822 659.0 */ 537, +/* 1823 659.1 */ 464, +/* 1824 660.0 */ 536, +/* 1825 660.1 */ 463, +/* 1826 661.0 */ 536, +/* 1827 661.1 */ 464, +/* 1828 662.0 */ 543, +/* 1829 662.1 */ 563, +/* 1830 663.0 */ 468, +/* 1831 663.1 */ 269, +/* 1832 664.0 */ 468, +/* 1833 664.1 */ 470, +/* 1834 665.0 */ 271, +/* 1835 665.1 */ 564, +/* 1836 666.0 */ 472, +/* 1837 666.1 */ 565, +/* 1838 667.0 */ 566, +/* 1839 667.1 */ 269, +/* 1840 668.0 */ 566, +/* 1841 668.1 */ 470, +/* 1842 669.0 */ 271, +/* 1843 669.1 */ 567, +/* 1844 670.0 */ 472, +/* 1845 670.1 */ 568, +/* 1846 671.0 */ 468, +/* 1847 671.1 */ 471, +/* 1848 672.0 */ 220, +/* 1849 672.1 */ 569, +/* 1850 673.0 */ 474, +/* 1851 673.1 */ 570, +/* 1852 674.0 */ 571, +/* 1853 674.1 */ 570, +/* 1854 675.0 */ 566, +/* 1855 675.1 */ 219, +/* 1856 676.0 */ 566, +/* 1857 676.1 */ 471, +/* 1858 677.0 */ 474, +/* 1859 677.1 */ 572, +/* 1860 678.0 */ 566, +/* 1861 678.1 */ 245, +/* 1862 679.0 */ 573, +/* 1863 679.1 */ 572, +/* 1864 680.0 */ 468, +/* 1865 680.1 */ 247, +/* 1866 681.0 */ 468, +/* 1867 681.1 */ 248, +/* 1868 682.0 */ 571, +/* 1869 682.1 */ 574, +/* 1870 683.0 */ 220, +/* 1871 683.1 */ 534, +/* 1872 683.2 */ 117, +/* 1873 684.0 */ 474, +/* 1874 684.1 */ 575, +/* 1875 684.2 */ 123, +/* 1876 685.0 */ 271, +/* 1877 685.1 */ 533, +/* 1878 685.2 */ 117, +/* 1879 686.0 */ 472, +/* 1880 686.1 */ 576, +/* 1881 686.2 */ 123, +/* 1882 687.0 */ 534, +/* 1883 687.1 */ 219, +/* 1884 687.2 */ 117, +/* 1885 688.0 */ 534, +/* 1886 688.1 */ 471, +/* 1887 688.2 */ 123, +/* 1888 689.0 */ 533, +/* 1889 689.1 */ 269, +/* 1890 689.2 */ 117, +/* 1891 690.0 */ 533, +/* 1892 690.1 */ 470, +/* 1893 690.2 */ 123, +/* 1894 691.0 */ 185, +/* 1895 691.1 */ 117, +/* 1896 692.0 */ 524, +/* 1897 692.1 */ 118, +/* 1898 692.2 */ 120, +/* 1899 692.3 */ 117, +/* 1900 693.0 */ 528, +/* 1901 693.1 */ 124, +/* 1902 693.2 */ 120, +/* 1903 693.3 */ 123, +/* 1904 694.0 */ 524, +/* 1905 694.1 */ 118, +/* 1906 694.2 */ 157, +/* 1907 694.3 */ 158, +/* 1908 695.0 */ 528, +/* 1909 695.1 */ 124, +/* 1910 695.2 */ 577, +/* 1911 695.3 */ 578, +/* 1912 696.0 */ 174, +/* 1913 697.0 */ 543, +/* 1914 697.1 */ 219, +/* 1915 697.2 */ 120, +/* 1916 698.0 */ 543, +/* 1917 698.1 */ 245, +/* 1918 698.2 */ 120, +/* 1919 699.0 */ 246, +/* 1920 699.1 */ 247, +/* 1921 699.2 */ 120, +/* 1922 700.0 */ 246, +/* 1923 700.1 */ 248, +/* 1924 700.2 */ 120, +/* 1925 701.0 */ 579, +/* 1926 701.1 */ 129, +/* 1927 701.2 */ 117, +/* 1928 702.0 */ 579, +/* 1929 702.1 */ 580, +/* 1930 702.2 */ 123, +/* 1931 703.0 */ 581, +/* 1932 703.1 */ 126, +/* 1933 704.0 */ 581, +/* 1934 704.1 */ 582, +/* 1935 705.0 */ 581, +/* 1936 705.1 */ 129, +/* 1937 706.0 */ 581, +/* 1938 706.1 */ 580, +/* 1939 707.0 */ 583, +/* 1940 707.1 */ 584, +/* 1941 707.2 */ 120, +/* 1942 708.0 */ 583, +/* 1943 708.1 */ 585, +/* 1944 708.2 */ 120, +/* 1945 709.0 */ 586, +/* 1946 709.1 */ 587, +/* 1947 709.2 */ 120, +/* 1948 710.0 */ 586, +/* 1949 710.1 */ 588, +/* 1950 710.2 */ 120, +/* 1951 711.0 */ 583, +/* 1952 711.1 */ 584, +/* 1953 711.2 */ 589, +/* 1954 712.0 */ 583, +/* 1955 712.1 */ 585, +/* 1956 712.2 */ 590, +/* 1957 713.0 */ 586, +/* 1958 713.1 */ 587, +/* 1959 713.2 */ 591, +/* 1960 714.0 */ 586, +/* 1961 714.1 */ 588, +/* 1962 714.2 */ 592, +/* 1963 715.0 */ 271, +/* 1964 715.1 */ 295, +/* 1965 715.2 */ 120, +/* 1966 716.0 */ 593, +/* 1967 716.1 */ 574, +/* 1968 716.2 */ 120, +/* 1969 717.0 */ 442, +/* 1970 717.1 */ 269, +/* 1971 717.2 */ 120, +/* 1972 718.0 */ 544, +/* 1973 718.1 */ 545, +/* 1974 718.2 */ 120, +/* 1975 719.0 */ 544, +/* 1976 719.1 */ 546, +/* 1977 719.2 */ 120, +/* 1978 720.0 */ 246, +/* 1979 720.1 */ 247, +/* 1980 720.2 */ 594, +/* 1981 721.0 */ 246, +/* 1982 721.1 */ 248, +/* 1983 721.2 */ 595, +/* 1984 722.0 */ 232, +/* 1985 722.1 */ 549, +/* 1986 722.2 */ 120, +/* 1987 723.0 */ 201, +/* 1988 723.1 */ 549, +/* 1989 723.2 */ 120, +/* 1990 724.0 */ 472, +/* 1991 724.1 */ 574, +/* 1992 724.2 */ 120, +/* 1993 725.0 */ 220, +/* 1994 725.1 */ 549, +/* 1995 725.2 */ 120, +/* 1996 726.0 */ 596, +/* 1997 726.1 */ 574, +/* 1998 726.2 */ 120, +/* 1999 727.0 */ 271, +/* 2000 727.1 */ 549, +/* 2001 727.2 */ 120, +/* 2002 728.0 */ 246, +/* 2003 728.1 */ 126, +/* 2004 728.2 */ 120, +/* 2005 729.0 */ 246, +/* 2006 729.1 */ 558, +/* 2007 729.2 */ 120, +/* 2008 730.0 */ 246, +/* 2009 730.1 */ 269, +/* 2010 730.2 */ 120, +/* 2011 731.0 */ 246, +/* 2012 731.1 */ 219, +/* 2013 731.2 */ 120, +/* 2014 732.0 */ 246, +/* 2015 732.1 */ 562, +/* 2016 732.2 */ 120, +/* 2017 733.0 */ 452, +/* 2018 733.1 */ 453, +/* 2019 733.2 */ 120, +/* 2020 734.0 */ 452, +/* 2021 734.1 */ 454, +/* 2022 734.2 */ 120, +/* 2023 735.0 */ 436, +/* 2024 735.1 */ 437, +/* 2025 735.2 */ 120, +/* 2026 736.0 */ 436, +/* 2027 736.1 */ 438, +/* 2028 736.2 */ 120, +/* 2029 737.0 */ 597, +/* 2030 737.1 */ 219, +/* 2031 737.2 */ 120, +/* 2032 738.0 */ 597, +/* 2033 738.1 */ 443, +/* 2034 738.2 */ 120, +/* 2035 739.0 */ 598, +/* 2036 739.1 */ 269, +/* 2037 739.2 */ 120, +/* 2038 740.0 */ 598, +/* 2039 740.1 */ 599, +/* 2040 740.2 */ 120, +/* 2041 741.0 */ 549, +/* 2042 741.1 */ 247, +/* 2043 741.2 */ 117, +/* 2044 742.0 */ 549, +/* 2045 742.1 */ 248, +/* 2046 742.2 */ 123, +/* 2047 743.0 */ 600, +/* 2048 743.1 */ 503, +/* 2049 744.0 */ 600, +/* 2050 744.1 */ 601, +/* 2051 745.0 */ 468, +/* 2052 745.1 */ 602, +/* 2053 746.0 */ 468, +/* 2054 746.1 */ 603, +/* 2055 747.0 */ 604, +/* 2056 747.1 */ 605, +/* 2057 748.0 */ 604, +/* 2058 748.1 */ 606, +/* 2059 749.0 */ 468, +/* 2060 749.1 */ 498, +/* 2061 750.0 */ 468, +/* 2062 750.1 */ 607, +/* 2063 751.0 */ 604, +/* 2064 751.1 */ 608, +/* 2065 752.0 */ 604, +/* 2066 752.1 */ 609, +/* 2067 753.0 */ 604, +/* 2068 753.1 */ 508, +/* 2069 754.0 */ 604, +/* 2070 754.1 */ 550, +/* 2071 755.0 */ 516, +/* 2072 755.1 */ 610, +/* 2073 756.0 */ 516, +/* 2074 756.1 */ 611, +/* 2075 757.0 */ 513, +/* 2076 757.1 */ 492, +/* 2077 758.0 */ 513, +/* 2078 758.1 */ 612, +/* 2079 759.0 */ 540, +/* 2080 759.1 */ 613, +/* 2081 760.0 */ 540, +/* 2082 760.1 */ 614, +/* 2083 761.0 */ 513, +/* 2084 761.1 */ 511, +/* 2085 762.0 */ 513, +/* 2086 762.1 */ 615, +/* 2087 763.0 */ 540, +/* 2088 763.1 */ 494, +/* 2089 764.0 */ 540, +/* 2090 764.1 */ 616, +/* 2091 765.0 */ 540, +/* 2092 765.1 */ 551, +/* 2093 766.0 */ 540, +/* 2094 766.1 */ 617, +/* 2095 767.0 */ 549, +/* 2096 767.1 */ 247, +/* 2097 767.2 */ 120, +/* 2098 767.3 */ 308, +/* 2099 767.4 */ 281, +/* 2100 767.5 */ 618, +/* 2101 767.6 */ 110, +/* 2102 768.0 */ 549, +/* 2103 768.1 */ 248, +/* 2104 768.2 */ 120, +/* 2105 768.3 */ 619, +/* 2106 768.4 */ 309, +/* 2107 768.5 */ 620, +/* 2108 768.6 */ 621, +/* 2109 769.0 */ 549, +/* 2110 769.1 */ 247, +/* 2111 769.2 */ 120, +/* 2112 769.3 */ 365, +/* 2113 769.4 */ 622, +/* 2114 769.5 */ 623, +/* 2115 769.6 */ 110, +/* 2116 770.0 */ 549, +/* 2117 770.1 */ 248, +/* 2118 770.2 */ 120, +/* 2119 770.3 */ 624, +/* 2120 770.4 */ 483, +/* 2121 770.5 */ 625, +/* 2122 770.6 */ 621, +/* 2123 771.0 */ 549, +/* 2124 771.1 */ 247, +/* 2125 771.2 */ 120, +/* 2126 771.3 */ 626, +/* 2127 771.4 */ 123, +/* 2128 772.0 */ 549, +/* 2129 772.1 */ 248, +/* 2130 772.2 */ 120, +/* 2131 772.3 */ 287, +/* 2132 772.4 */ 97, +/* 2133 773.0 */ 549, +/* 2134 773.1 */ 247, +/* 2135 773.2 */ 120, +/* 2136 773.3 */ 432, +/* 2137 773.4 */ 123, +/* 2138 774.0 */ 549, +/* 2139 774.1 */ 248, +/* 2140 774.2 */ 120, +/* 2141 774.3 */ 627, +/* 2142 774.4 */ 97, +/* 2143 775.0 */ 549, +/* 2144 775.1 */ 247, +/* 2145 775.2 */ 120, +/* 2146 775.3 */ 308, +/* 2147 775.4 */ 281, +/* 2148 775.5 */ 628, +/* 2149 775.6 */ 110, +/* 2150 776.0 */ 549, +/* 2151 776.1 */ 248, +/* 2152 776.2 */ 120, +/* 2153 776.3 */ 619, +/* 2154 776.4 */ 309, +/* 2155 776.5 */ 629, +/* 2156 776.6 */ 621, +/* 2157 777.0 */ 549, +/* 2158 777.1 */ 247, +/* 2159 777.2 */ 120, +/* 2160 777.3 */ 365, +/* 2161 777.4 */ 622, +/* 2162 777.5 */ 628, +/* 2163 777.6 */ 110, +/* 2164 778.0 */ 549, +/* 2165 778.1 */ 248, +/* 2166 778.2 */ 120, +/* 2167 778.3 */ 624, +/* 2168 778.4 */ 483, +/* 2169 778.5 */ 629, +/* 2170 778.6 */ 621, +/* 2171 779.0 */ 549, +/* 2172 779.1 */ 247, +/* 2173 779.2 */ 120, +/* 2174 779.3 */ 630, +/* 2175 779.4 */ 123, +/* 2176 780.0 */ 549, +/* 2177 780.1 */ 248, +/* 2178 780.2 */ 120, +/* 2179 780.3 */ 631, +/* 2180 780.4 */ 97, +/* 2181 781.0 */ 422, +/* 2182 781.1 */ 286, +/* 2183 781.2 */ 632, +/* 2184 781.3 */ 633, +/* 2185 782.0 */ 422, +/* 2186 782.1 */ 477, +/* 2187 782.2 */ 619, +/* 2188 782.3 */ 634, +/* 2189 783.0 */ 635, +/* 2190 783.1 */ 636, +/* 2191 783.2 */ 308, +/* 2192 783.3 */ 637, +/* 2193 784.0 */ 638, +/* 2194 784.1 */ 636, +/* 2195 784.2 */ 308, +/* 2196 784.3 */ 637, +/* 2197 785.0 */ 639, +/* 2198 785.1 */ 640, +/* 2199 786.0 */ 468, +/* 2200 786.1 */ 248, +/* 2201 786.2 */ 120, +/* 2202 787.0 */ 468, +/* 2203 787.1 */ 247, +/* 2204 787.2 */ 120, +/* 2205 788.0 */ 534, +/* 2206 788.1 */ 247, +/* 2207 788.2 */ 117, +/* 2208 789.0 */ 533, +/* 2209 789.1 */ 247, +/* 2210 789.2 */ 117, +/* 2211 790.0 */ 342, +/* 2212 790.1 */ 641, +/* 2213 790.2 */ 172, +/* 2214 790.3 */ 642, +/* 2215 790.4 */ 343, +/* 2216 791.0 */ 342, +/* 2217 791.1 */ 643, +/* 2218 791.2 */ 172, +/* 2219 791.3 */ 642, +/* 2220 791.4 */ 343, +/* 2221 792.0 */ 342, +/* 2222 792.1 */ 643, +/* 2223 792.2 */ 644, +/* 2224 792.3 */ 645, +/* 2225 792.4 */ 343, +/* 2226 792.5 */ 381, +/* 2227 792.6 */ 382, +/* 2228 793.0 */ 342, +/* 2229 793.1 */ 643, +/* 2230 793.2 */ 644, +/* 2231 793.3 */ 645, +/* 2232 793.4 */ 646, +/* 2233 793.5 */ 343, +/* 2234 793.6 */ 381, +/* 2235 793.7 */ 382, +/* 2236 794.0 */ 647, +/* 2237 794.1 */ 648, +/* 2238 794.2 */ 342, +/* 2239 794.3 */ 352, +/* 2240 794.4 */ 384, +/* 2241 794.5 */ 649, +/* 2242 795.0 */ 519, +/* 2243 795.1 */ 650, +/* 2244 795.2 */ 651, +/* 2245 795.3 */ 652, +/* 2246 795.4 */ 653, +/* 2247 796.0 */ 519, +/* 2248 796.1 */ 650, +/* 2249 796.2 */ 651, +/* 2250 796.3 */ 654, +/* 2251 796.4 */ 653, +/* 2252 797.0 */ 193, +/* 2253 797.1 */ 117, +/* 2254 798.0 */ 655, +/* 2255 799.0 */ 656, +/* 2256 800.0 */ 655, +/* 2257 800.1 */ 657, +/* 2258 801.0 */ 658, +/* 2259 801.1 */ 120, +/* 2260 801.2 */ 406, +/* 2261 802.0 */ 597, +/* 2262 802.1 */ 248, +/* 2263 803.0 */ 597, +/* 2264 803.1 */ 443, +/* 2265 803.2 */ 120, +/* 2266 803.3 */ 406, +/* 2267 804.0 */ 659, +/* 2268 805.0 */ 519, +/* 2269 805.1 */ 280, +/* 2270 806.0 */ 660, +/* 2271 806.1 */ 661, +/* 2272 806.2 */ 662, +/* 2273 807.0 */ 663, +/* 2274 807.1 */ 117, +/* 2275 808.0 */ 663, +/* 2276 808.1 */ 657, +/* 2277 808.2 */ 664, +/* 2278 808.3 */ 97, +/* 2279 809.0 */ 663, +/* 2280 809.1 */ 665, +/* 2281 809.2 */ 666, +/* 2282 809.3 */ 97, +/* 2283 810.0 */ 663, +/* 2284 810.1 */ 665, +/* 2285 810.2 */ 123, +/* 2286 811.0 */ 656, +/* 2287 811.1 */ 667, +/* 2288 811.2 */ 668, +/* 2289 812.0 */ 669, +/* 2290 812.1 */ 667, +/* 2291 812.2 */ 668, +/* 2292 813.0 */ 670, +/* 2293 813.1 */ 360, +/* 2294 814.0 */ 671, +/* 2295 814.1 */ 360, +/* 2296 815.0 */ 671, +/* 2297 815.1 */ 471, +/* 2298 816.0 */ 671, +/* 2299 816.1 */ 470, +/* 2300 817.0 */ 670, +/* 2301 817.1 */ 672, +/* 2302 818.0 */ 670, +/* 2303 818.1 */ 551, +/* 2304 819.0 */ 670, +/* 2305 819.1 */ 253, +/* 2306 820.0 */ 673, +/* 2307 820.1 */ 674, +/* 2308 821.0 */ 675, +/* 2309 821.1 */ 671, +/* 2310 822.0 */ 676, +/* 2311 822.1 */ 671, +/* 2312 823.0 */ 670, +/* 2313 823.1 */ 677, +/* 2314 824.0 */ 670, +/* 2315 824.1 */ 678, +/* 2316 825.0 */ 679, +/* 2317 825.1 */ 671, +/* 2318 826.0 */ 680, +/* 2319 826.1 */ 671, +/* 2320 827.0 */ 681, +/* 2321 828.0 */ 682, +/* 2322 828.1 */ 683, +/* 2323 829.0 */ 684, +/* 2324 829.1 */ 683, +/* 2325 830.0 */ 685, +/* 2326 830.1 */ 686, +/* 2327 831.0 */ 687, +/* 2328 831.1 */ 686, +/* 2329 832.0 */ 681, +/* 2330 832.1 */ 688, +/* 2331 833.0 */ 689, +/* 2332 834.0 */ 690, +/* 2333 834.1 */ 691, +/* 2334 835.0 */ 692, +/* 2335 835.1 */ 693, +/* 2336 836.0 */ 144, +/* 2337 836.1 */ 117, +/* 2338 837.0 */ 246, +/* 2339 837.1 */ 248, +/* 2340 837.2 */ 694, +/* 2341 838.0 */ 246, +/* 2342 838.1 */ 247, +/* 2343 838.2 */ 695, +/* 2344 839.0 */ 696, +/* 2345 839.1 */ 636, +/* 2346 839.2 */ 308, +/* 2347 839.3 */ 637, +/* 2348 840.0 */ 697, +/* 2349 840.1 */ 698, +/* 2350 841.0 */ 697, +/* 2351 841.1 */ 699, +/* 2352 842.0 */ 700, +/* 2353 842.1 */ 701, +/* 2354 843.0 */ 700, +/* 2355 843.1 */ 702, +/* 2356 844.0 */ 279, +/* 2357 844.1 */ 703, +/* 2358 844.2 */ 704, +/* 2359 844.3 */ 705, +/* 2360 845.0 */ 685, +/* 2361 845.1 */ 706, +/* 2362 846.0 */ 687, +/* 2363 846.1 */ 706, +/* 2364 847.0 */ 700, +/* 2365 848.0 */ 707, +/* 2366 849.0 */ 708, +/* 2367 849.1 */ 709, +/* 2368 849.2 */ 710, +/* 2369 849.3 */ 711, +/* 2370 850.0 */ 712, +/* 2371 850.1 */ 713, +/* 2372 850.2 */ 714, +/* 2373 850.3 */ 97, +/* 2374 851.0 */ 715, +/* 2375 852.0 */ 716, +/* 2376 852.1 */ 717, +/* 2377 852.2 */ 718, +/* 2378 852.3 */ 719, +/* 2379 853.0 */ 169, +/* 2380 853.1 */ 129, +/* 2381 853.2 */ 117, +/* 2382 854.0 */ 169, +/* 2383 854.1 */ 130, +/* 2384 854.2 */ 123, +/* 2385 855.0 */ 430, +/* 2386 855.1 */ 129, +/* 2387 855.2 */ 117, +/* 2388 856.0 */ 279, +/* 2389 857.0 */ 534, +/* 2390 857.1 */ 247, +/* 2391 858.0 */ 533, +/* 2392 858.1 */ 247, +/* 2393 859.0 */ 181, +/* 2394 859.1 */ 720, +/* 2395 859.2 */ 721, +/* 2396 860.0 */ 639, +/* 2397 860.1 */ 120, +/* 2398 861.0 */ 722, +/* 2399 861.1 */ 558, +/* 2400 861.2 */ 135, +/* 2401 862.0 */ 722, +/* 2402 862.1 */ 269, +/* 2403 862.2 */ 134, +/* 2404 863.0 */ 723, +/* 2405 863.1 */ 562, +/* 2406 863.2 */ 135, +/* 2407 864.0 */ 723, +/* 2408 864.1 */ 219, +/* 2409 864.2 */ 134, +/* 2410 865.0 */ 366, +/* 2411 865.1 */ 323, +/* 2412 865.2 */ 224, +/* 2413 866.0 */ 636, +/* 2414 866.1 */ 308, +/* 2415 866.2 */ 224, +/* 2416 867.0 */ 724, +/* 2417 867.1 */ 725, +/* 2418 867.2 */ 726, +/* 2419 867.3 */ 727, +/* 2420 867.4 */ 110, +/* 2421 868.0 */ 724, +/* 2422 868.1 */ 717, +/* 2423 868.2 */ 718, +/* 2424 868.3 */ 719, +/* 2425 868.4 */ 110, +/* 2426 869.0 */ 544, +/* 2427 869.1 */ 254, +/* 2428 869.2 */ 120, +/* 2429 870.0 */ 544, +/* 2430 870.1 */ 253, +/* 2431 870.2 */ 120, +/* 2432 871.0 */ 544, +/* 2433 871.1 */ 728, +/* 2434 871.2 */ 117, +/* 2435 872.0 */ 544, +/* 2436 872.1 */ 729, +/* 2437 872.2 */ 117, +/* 2438 873.0 */ 728, +/* 2439 873.1 */ 730, +/* 2440 873.2 */ 731, +/* 2441 873.3 */ 732, +/* 2442 873.4 */ 733, +/* 2443 873.5 */ 734, +/* 2444 873.6 */ 735, +/* 2445 873.7 */ 736, +/* 2446 873.8 */ 737, +/* 2447 873.9 */ 738, +/* 2448 874.0 */ 729, +/* 2449 874.1 */ 730, +/* 2450 874.2 */ 731, +/* 2451 874.3 */ 732, +/* 2452 874.4 */ 733, +/* 2453 874.5 */ 734, +/* 2454 874.6 */ 735, +/* 2455 874.7 */ 736, +/* 2456 874.8 */ 737, +/* 2457 874.9 */ 738, +/* 2458 875.0 */ 739, +/* 2459 875.1 */ 740, +/* 2460 875.2 */ 741, +/* 2461 875.3 */ 742, +/* 2462 875.4 */ 743, +/* 2463 875.5 */ 744, +/* 2464 875.6 */ 745, +/* 2465 875.7 */ 746, +/* 2466 875.8 */ 738, +/* 2467 876.0 */ 739, +/* 2468 876.1 */ 740, +/* 2469 876.2 */ 741, +/* 2470 876.3 */ 747, +/* 2471 876.4 */ 743, +/* 2472 876.5 */ 748, +/* 2473 876.6 */ 749, +/* 2474 876.7 */ 750, +/* 2475 876.8 */ 751, +/* 2476 876.9 */ 752, +/* 2477 877.0 */ 753, +/* 2478 877.1 */ 546, +/* 2479 877.2 */ 714, +/* 2480 877.3 */ 754, +/* 2481 877.4 */ 110, +/* 2482 878.0 */ 120, +/* 2483 878.1 */ 716, +/* 2484 879.0 */ 755, +/* 2485 880.0 */ 712, +/* 2486 881.0 */ 756, +/* 2487 881.1 */ 117, +/* 2488 882.0 */ 185, +/* 2489 882.1 */ 145, +/* 2490 882.2 */ 146, +/* 2491 882.3 */ 147, +/* 2492 882.4 */ 123, +/* 2493 883.0 */ 708, +/* 2494 883.1 */ 709, +/* 2495 883.2 */ 117, +/* 2496 884.0 */ 757, +/* 2497 884.1 */ 117, +/* 2498 885.0 */ 758, +/* 2499 886.0 */ 759, +/* 2500 887.0 */ 600, +/* 2501 887.1 */ 760, +/* 2502 887.2 */ 500, +/* 2503 887.3 */ 761, +/* 2504 888.0 */ 600, +/* 2505 888.1 */ 760, +/* 2506 888.2 */ 762, +/* 2507 888.3 */ 763, +/* 2508 889.0 */ 468, +/* 2509 889.1 */ 760, +/* 2510 889.2 */ 500, +/* 2511 889.3 */ 764, +/* 2512 890.0 */ 468, +/* 2513 890.1 */ 760, +/* 2514 890.2 */ 762, +/* 2515 890.3 */ 765, +/* 2516 891.0 */ 604, +/* 2517 891.1 */ 766, +/* 2518 891.2 */ 247, +/* 2519 891.3 */ 767, +/* 2520 892.0 */ 604, +/* 2521 892.1 */ 766, +/* 2522 892.2 */ 768, +/* 2523 892.3 */ 769, +/* 2524 893.0 */ 770, +/* 2525 893.1 */ 771, +/* 2526 893.2 */ 772, +/* 2527 893.3 */ 773, +/* 2528 894.0 */ 770, +/* 2529 894.1 */ 771, +/* 2530 894.2 */ 774, +/* 2531 894.3 */ 775, +/* 2532 895.0 */ 770, +/* 2533 895.1 */ 771, +/* 2534 895.2 */ 773, +/* 2535 895.3 */ 772, +/* 2536 896.0 */ 770, +/* 2537 896.1 */ 771, +/* 2538 896.2 */ 773, +/* 2539 896.3 */ 776, +/* 2540 897.0 */ 777, +/* 2541 897.1 */ 778, +/* 2542 897.2 */ 779, +/* 2543 897.3 */ 780, +/* 2544 898.0 */ 777, +/* 2545 898.1 */ 778, +/* 2546 898.2 */ 781, +/* 2547 898.3 */ 782, +/* 2548 899.0 */ 777, +/* 2549 899.1 */ 778, +/* 2550 899.2 */ 780, +/* 2551 899.3 */ 779, +/* 2552 900.0 */ 777, +/* 2553 900.1 */ 778, +/* 2554 900.2 */ 780, +/* 2555 900.3 */ 783, +/* 2556 901.0 */ 600, +/* 2557 901.1 */ 760, +/* 2558 901.2 */ 761, +/* 2559 901.3 */ 500, +/* 2560 902.0 */ 600, +/* 2561 902.1 */ 760, +/* 2562 902.2 */ 761, +/* 2563 902.3 */ 784, +/* 2564 903.0 */ 785, +/* 2565 903.1 */ 545, +/* 2566 903.2 */ 120, +/* 2567 904.0 */ 785, +/* 2568 904.1 */ 546, +/* 2569 904.2 */ 120, +/* 2570 905.0 */ 785, +/* 2571 905.1 */ 545, +/* 2572 905.2 */ 786, +/* 2573 906.0 */ 785, +/* 2574 906.1 */ 546, +/* 2575 906.2 */ 787, +/* 2576 907.0 */ 785, +/* 2577 907.1 */ 786, +/* 2578 907.2 */ 545, +/* 2579 908.0 */ 785, +/* 2580 908.1 */ 786, +/* 2581 908.2 */ 788, +/* 2582 909.0 */ 516, +/* 2583 909.1 */ 517, +/* 2584 909.2 */ 789, +/* 2585 910.0 */ 516, +/* 2586 910.1 */ 518, +/* 2587 910.2 */ 790, +/* 2588 911.0 */ 516, +/* 2589 911.1 */ 789, +/* 2590 911.2 */ 517, +/* 2591 912.0 */ 516, +/* 2592 912.1 */ 789, +/* 2593 912.2 */ 791, +/* 2594 913.0 */ 513, +/* 2595 913.1 */ 514, +/* 2596 913.2 */ 792, +/* 2597 914.0 */ 513, +/* 2598 914.1 */ 515, +/* 2599 914.2 */ 793, +/* 2600 915.0 */ 513, +/* 2601 915.1 */ 792, +/* 2602 915.2 */ 514, +/* 2603 916.0 */ 513, +/* 2604 916.1 */ 792, +/* 2605 916.2 */ 794, +/* 2606 917.0 */ 540, +/* 2607 917.1 */ 253, +/* 2608 917.2 */ 120, +/* 2609 918.0 */ 540, +/* 2610 918.1 */ 254, +/* 2611 918.2 */ 120, +/* 2612 919.0 */ 540, +/* 2613 919.1 */ 253, +/* 2614 919.2 */ 795, +/* 2615 920.0 */ 540, +/* 2616 920.1 */ 254, +/* 2617 920.2 */ 796, +/* 2618 921.0 */ 540, +/* 2619 921.1 */ 795, +/* 2620 921.2 */ 253, +/* 2621 922.0 */ 540, +/* 2622 922.1 */ 795, +/* 2623 922.2 */ 797, +/* 2624 923.0 */ 468, +/* 2625 923.1 */ 766, +/* 2626 923.2 */ 247, +/* 2627 923.3 */ 764, +/* 2628 924.0 */ 468, +/* 2629 924.1 */ 766, +/* 2630 924.2 */ 768, +/* 2631 924.3 */ 765, +/* 2632 925.0 */ 798, +/* 2633 925.1 */ 799, +/* 2634 925.2 */ 506, +/* 2635 925.3 */ 120, +/* 2636 926.0 */ 798, +/* 2637 926.1 */ 799, +/* 2638 926.2 */ 800, +/* 2639 926.3 */ 120, +/* 2640 927.0 */ 600, +/* 2641 927.1 */ 760, +/* 2642 927.2 */ 500, +/* 2643 927.3 */ 120, +/* 2644 928.0 */ 600, +/* 2645 928.1 */ 760, +/* 2646 928.2 */ 762, +/* 2647 928.3 */ 120, +/* 2648 929.0 */ 468, +/* 2649 929.1 */ 766, +/* 2650 929.2 */ 247, +/* 2651 929.3 */ 120, +/* 2652 930.0 */ 468, +/* 2653 930.1 */ 766, +/* 2654 930.2 */ 768, +/* 2655 930.3 */ 120, +/* 2656 931.0 */ 604, +/* 2657 931.1 */ 801, +/* 2658 931.2 */ 802, +/* 2659 931.3 */ 120, +/* 2660 932.0 */ 604, +/* 2661 932.1 */ 801, +/* 2662 932.2 */ 803, +/* 2663 932.3 */ 120, +/* 2664 933.0 */ 785, +/* 2665 933.1 */ 786, +/* 2666 933.2 */ 545, +/* 2667 933.3 */ 120, +/* 2668 934.0 */ 785, +/* 2669 934.1 */ 786, +/* 2670 934.2 */ 788, +/* 2671 934.3 */ 120, +/* 2672 935.0 */ 516, +/* 2673 935.1 */ 789, +/* 2674 935.2 */ 517, +/* 2675 935.3 */ 120, +/* 2676 936.0 */ 516, +/* 2677 936.1 */ 789, +/* 2678 936.2 */ 791, +/* 2679 936.3 */ 120, +/* 2680 937.0 */ 513, +/* 2681 937.1 */ 792, +/* 2682 937.2 */ 514, +/* 2683 937.3 */ 120, +/* 2684 938.0 */ 513, +/* 2685 938.1 */ 792, +/* 2686 938.2 */ 794, +/* 2687 938.3 */ 120, +/* 2688 939.0 */ 540, +/* 2689 939.1 */ 795, +/* 2690 939.2 */ 253, +/* 2691 939.3 */ 120, +/* 2692 940.0 */ 540, +/* 2693 940.1 */ 795, +/* 2694 940.2 */ 797, +/* 2695 940.3 */ 120, +/* 2696 941.0 */ 444, +/* 2697 941.1 */ 587, +/* 2698 942.0 */ 444, +/* 2699 942.1 */ 588, +/* 2700 943.0 */ 804, +/* 2701 943.1 */ 805, +/* 2702 944.0 */ 804, +/* 2703 944.1 */ 806, +/* 2704 945.0 */ 462, +/* 2705 945.1 */ 584, +/* 2706 946.0 */ 462, +/* 2707 946.1 */ 585, +/* 2708 947.0 */ 807, +/* 2709 947.1 */ 808, +/* 2710 948.0 */ 807, +/* 2711 948.1 */ 809, +/* 2712 949.0 */ 444, +/* 2713 949.1 */ 810, +/* 2714 950.0 */ 444, +/* 2715 950.1 */ 811, +/* 2716 951.0 */ 462, +/* 2717 951.1 */ 812, +/* 2718 952.0 */ 462, +/* 2719 952.1 */ 813, +/* 2720 953.0 */ 798, +/* 2721 953.1 */ 506, +/* 2722 954.0 */ 798, +/* 2723 954.1 */ 507, +/* 2724 955.0 */ 468, +/* 2725 955.1 */ 506, +/* 2726 956.0 */ 468, +/* 2727 956.1 */ 507, +/* 2728 957.0 */ 604, +/* 2729 957.1 */ 506, +/* 2730 958.0 */ 604, +/* 2731 958.1 */ 507, +/* 2732 959.0 */ 468, +/* 2733 959.1 */ 500, +/* 2734 960.0 */ 468, +/* 2735 960.1 */ 501, +/* 2736 961.0 */ 604, +/* 2737 961.1 */ 500, +/* 2738 962.0 */ 604, +/* 2739 962.1 */ 501, +/* 2740 963.0 */ 516, +/* 2741 963.1 */ 545, +/* 2742 964.0 */ 516, +/* 2743 964.1 */ 546, +/* 2744 965.0 */ 513, +/* 2745 965.1 */ 545, +/* 2746 966.0 */ 513, +/* 2747 966.1 */ 546, +/* 2748 967.0 */ 540, +/* 2749 967.1 */ 545, +/* 2750 968.0 */ 540, +/* 2751 968.1 */ 546, +/* 2752 969.0 */ 513, +/* 2753 969.1 */ 517, +/* 2754 970.0 */ 513, +/* 2755 970.1 */ 518, +/* 2756 971.0 */ 540, +/* 2757 971.1 */ 517, +/* 2758 972.0 */ 540, +/* 2759 972.1 */ 518, +/* 2760 973.0 */ 600, +/* 2761 973.1 */ 506, +/* 2762 974.0 */ 600, +/* 2763 974.1 */ 507, +/* 2764 975.0 */ 604, +/* 2765 975.1 */ 247, +/* 2766 976.0 */ 604, +/* 2767 976.1 */ 248, +/* 2768 977.0 */ 798, +/* 2769 977.1 */ 506, +/* 2770 977.2 */ 799, +/* 2771 978.0 */ 798, +/* 2772 978.1 */ 507, +/* 2773 978.2 */ 814, +/* 2774 979.0 */ 798, +/* 2775 979.1 */ 799, +/* 2776 979.2 */ 506, +/* 2777 980.0 */ 798, +/* 2778 980.1 */ 799, +/* 2779 980.2 */ 800, +/* 2780 981.0 */ 600, +/* 2781 981.1 */ 500, +/* 2782 981.2 */ 760, +/* 2783 982.0 */ 600, +/* 2784 982.1 */ 501, +/* 2785 982.2 */ 815, +/* 2786 983.0 */ 600, +/* 2787 983.1 */ 760, +/* 2788 983.2 */ 500, +/* 2789 984.0 */ 600, +/* 2790 984.1 */ 760, +/* 2791 984.2 */ 762, +/* 2792 985.0 */ 468, +/* 2793 985.1 */ 247, +/* 2794 985.2 */ 766, +/* 2795 986.0 */ 468, +/* 2796 986.1 */ 248, +/* 2797 986.2 */ 816, +/* 2798 987.0 */ 468, +/* 2799 987.1 */ 766, +/* 2800 987.2 */ 247, +/* 2801 988.0 */ 468, +/* 2802 988.1 */ 766, +/* 2803 988.2 */ 768, +/* 2804 989.0 */ 604, +/* 2805 989.1 */ 802, +/* 2806 989.2 */ 801, +/* 2807 990.0 */ 604, +/* 2808 990.1 */ 817, +/* 2809 990.2 */ 818, +/* 2810 991.0 */ 604, +/* 2811 991.1 */ 801, +/* 2812 991.2 */ 802, +/* 2813 992.0 */ 604, +/* 2814 992.1 */ 801, +/* 2815 992.2 */ 803, +/* 2816 993.0 */ 540, +/* 2817 993.1 */ 514, +/* 2818 994.0 */ 540, +/* 2819 994.1 */ 515, +/* 2820 995.0 */ 819, +/* 2821 995.1 */ 269, +/* 2822 995.2 */ 820, +/* 2823 995.3 */ 117, +/* 2824 996.0 */ 821, +/* 2825 996.1 */ 707, +/* 2826 996.2 */ 820, +/* 2827 996.3 */ 117, +/* 2828 997.0 */ 819, +/* 2829 997.1 */ 822, +/* 2830 997.2 */ 820, +/* 2831 997.3 */ 123, +/* 2832 998.0 */ 821, +/* 2833 998.1 */ 823, +/* 2834 998.2 */ 820, +/* 2835 998.3 */ 123, +/* 2836 999.0 */ 824, +/* 2837 999.1 */ 269, +/* 2838 999.2 */ 117, +/* 2839 1000.0 */ 825, +/* 2840 1000.1 */ 707, +/* 2841 1000.2 */ 117, +/* 2842 1001.0 */ 824, +/* 2843 1001.1 */ 822, +/* 2844 1001.2 */ 123, +/* 2845 1002.0 */ 825, +/* 2846 1002.1 */ 823, +/* 2847 1002.2 */ 123, +/* 2848 1003.0 */ 826, +/* 2849 1004.0 */ 825, +/* 2850 1004.1 */ 269, +/* 2851 1004.2 */ 820, +/* 2852 1004.3 */ 117, +/* 2853 1005.0 */ 825, +/* 2854 1005.1 */ 827, +/* 2855 1005.2 */ 820, +/* 2856 1005.3 */ 123, +/* 2857 1006.0 */ 825, +/* 2858 1006.1 */ 269, +/* 2859 1006.2 */ 820, +/* 2860 1007.0 */ 825, +/* 2861 1007.1 */ 827, +/* 2862 1007.2 */ 820, +/* 2863 1008.0 */ 444, +/* 2864 1008.1 */ 828, +/* 2865 1008.2 */ 587, +/* 2866 1008.3 */ 829, +/* 2867 1009.0 */ 444, +/* 2868 1009.1 */ 828, +/* 2869 1009.2 */ 830, +/* 2870 1009.3 */ 831, +/* 2871 1010.0 */ 444, +/* 2872 1010.1 */ 828, +/* 2873 1010.2 */ 829, +/* 2874 1010.3 */ 587, +/* 2875 1011.0 */ 444, +/* 2876 1011.1 */ 828, +/* 2877 1011.2 */ 829, +/* 2878 1011.3 */ 832, +/* 2879 1012.0 */ 804, +/* 2880 1012.1 */ 833, +/* 2881 1012.2 */ 805, +/* 2882 1012.3 */ 834, +/* 2883 1013.0 */ 804, +/* 2884 1013.1 */ 833, +/* 2885 1013.2 */ 835, +/* 2886 1013.3 */ 836, +/* 2887 1014.0 */ 804, +/* 2888 1014.1 */ 833, +/* 2889 1014.2 */ 834, +/* 2890 1014.3 */ 805, +/* 2891 1015.0 */ 804, +/* 2892 1015.1 */ 833, +/* 2893 1015.2 */ 834, +/* 2894 1015.3 */ 837, +/* 2895 1016.0 */ 462, +/* 2896 1016.1 */ 838, +/* 2897 1016.2 */ 584, +/* 2898 1016.3 */ 839, +/* 2899 1017.0 */ 462, +/* 2900 1017.1 */ 838, +/* 2901 1017.2 */ 840, +/* 2902 1017.3 */ 841, +/* 2903 1018.0 */ 462, +/* 2904 1018.1 */ 838, +/* 2905 1018.2 */ 839, +/* 2906 1018.3 */ 584, +/* 2907 1019.0 */ 462, +/* 2908 1019.1 */ 838, +/* 2909 1019.2 */ 839, +/* 2910 1019.3 */ 842, +/* 2911 1020.0 */ 807, +/* 2912 1020.1 */ 843, +/* 2913 1020.2 */ 808, +/* 2914 1020.3 */ 844, +/* 2915 1021.0 */ 807, +/* 2916 1021.1 */ 843, +/* 2917 1021.2 */ 845, +/* 2918 1021.3 */ 846, +/* 2919 1022.0 */ 807, +/* 2920 1022.1 */ 843, +/* 2921 1022.2 */ 844, +/* 2922 1022.3 */ 808, +/* 2923 1023.0 */ 807, +/* 2924 1023.1 */ 843, +/* 2925 1023.2 */ 844, +/* 2926 1023.3 */ 847, +/* 2927 1024.0 */ 444, +/* 2928 1024.1 */ 848, +/* 2929 1024.2 */ 810, +/* 2930 1024.3 */ 849, +/* 2931 1025.0 */ 444, +/* 2932 1025.1 */ 848, +/* 2933 1025.2 */ 850, +/* 2934 1025.3 */ 851, +/* 2935 1026.0 */ 444, +/* 2936 1026.1 */ 848, +/* 2937 1026.2 */ 849, +/* 2938 1026.3 */ 810, +/* 2939 1027.0 */ 444, +/* 2940 1027.1 */ 848, +/* 2941 1027.2 */ 849, +/* 2942 1027.3 */ 852, +/* 2943 1028.0 */ 462, +/* 2944 1028.1 */ 853, +/* 2945 1028.2 */ 812, +/* 2946 1028.3 */ 854, +/* 2947 1029.0 */ 462, +/* 2948 1029.1 */ 853, +/* 2949 1029.2 */ 855, +/* 2950 1029.3 */ 856, +/* 2951 1030.0 */ 462, +/* 2952 1030.1 */ 853, +/* 2953 1030.2 */ 854, +/* 2954 1030.3 */ 812, +/* 2955 1031.0 */ 462, +/* 2956 1031.1 */ 853, +/* 2957 1031.2 */ 854, +/* 2958 1031.3 */ 857, +/* 2959 1032.0 */ 444, +/* 2960 1032.1 */ 828, +/* 2961 1032.2 */ 587, +/* 2962 1032.3 */ 829, +/* 2963 1032.4 */ 120, +/* 2964 1033.0 */ 444, +/* 2965 1033.1 */ 828, +/* 2966 1033.2 */ 830, +/* 2967 1033.3 */ 831, +/* 2968 1033.4 */ 120, +/* 2969 1034.0 */ 804, +/* 2970 1034.1 */ 833, +/* 2971 1034.2 */ 805, +/* 2972 1034.3 */ 834, +/* 2973 1034.4 */ 120, +/* 2974 1035.0 */ 804, +/* 2975 1035.1 */ 833, +/* 2976 1035.2 */ 835, +/* 2977 1035.3 */ 836, +/* 2978 1035.4 */ 120, +/* 2979 1036.0 */ 444, +/* 2980 1036.1 */ 828, +/* 2981 1036.2 */ 829, +/* 2982 1036.3 */ 587, +/* 2983 1036.4 */ 120, +/* 2984 1037.0 */ 444, +/* 2985 1037.1 */ 828, +/* 2986 1037.2 */ 829, +/* 2987 1037.3 */ 832, +/* 2988 1037.4 */ 120, +/* 2989 1038.0 */ 804, +/* 2990 1038.1 */ 833, +/* 2991 1038.2 */ 834, +/* 2992 1038.3 */ 805, +/* 2993 1038.4 */ 120, +/* 2994 1039.0 */ 804, +/* 2995 1039.1 */ 833, +/* 2996 1039.2 */ 834, +/* 2997 1039.3 */ 837, +/* 2998 1039.4 */ 120, +/* 2999 1040.0 */ 462, +/* 3000 1040.1 */ 838, +/* 3001 1040.2 */ 584, +/* 3002 1040.3 */ 839, +/* 3003 1040.4 */ 120, +/* 3004 1041.0 */ 462, +/* 3005 1041.1 */ 838, +/* 3006 1041.2 */ 840, +/* 3007 1041.3 */ 841, +/* 3008 1041.4 */ 120, +/* 3009 1042.0 */ 807, +/* 3010 1042.1 */ 843, +/* 3011 1042.2 */ 808, +/* 3012 1042.3 */ 844, +/* 3013 1042.4 */ 120, +/* 3014 1043.0 */ 807, +/* 3015 1043.1 */ 843, +/* 3016 1043.2 */ 845, +/* 3017 1043.3 */ 846, +/* 3018 1043.4 */ 120, +/* 3019 1044.0 */ 462, +/* 3020 1044.1 */ 838, +/* 3021 1044.2 */ 839, +/* 3022 1044.3 */ 584, +/* 3023 1044.4 */ 120, +/* 3024 1045.0 */ 462, +/* 3025 1045.1 */ 838, +/* 3026 1045.2 */ 839, +/* 3027 1045.3 */ 842, +/* 3028 1045.4 */ 120, +/* 3029 1046.0 */ 807, +/* 3030 1046.1 */ 843, +/* 3031 1046.2 */ 844, +/* 3032 1046.3 */ 808, +/* 3033 1046.4 */ 120, +/* 3034 1047.0 */ 807, +/* 3035 1047.1 */ 843, +/* 3036 1047.2 */ 844, +/* 3037 1047.3 */ 847, +/* 3038 1047.4 */ 120, +/* 3039 1048.0 */ 462, +/* 3040 1048.1 */ 838, +/* 3041 1048.2 */ 584, +/* 3042 1049.0 */ 462, +/* 3043 1049.1 */ 838, +/* 3044 1049.2 */ 840, +/* 3045 1050.0 */ 807, +/* 3046 1050.1 */ 843, +/* 3047 1050.2 */ 808, +/* 3048 1051.0 */ 807, +/* 3049 1051.1 */ 843, +/* 3050 1051.2 */ 845, +/* 3051 1052.0 */ 444, +/* 3052 1052.1 */ 828, +/* 3053 1052.2 */ 587, +/* 3054 1053.0 */ 444, +/* 3055 1053.1 */ 828, +/* 3056 1053.2 */ 830, +/* 3057 1054.0 */ 804, +/* 3058 1054.1 */ 833, +/* 3059 1054.2 */ 805, +/* 3060 1055.0 */ 804, +/* 3061 1055.1 */ 833, +/* 3062 1055.2 */ 835, +/* 3063 1056.0 */ 462, +/* 3064 1056.1 */ 838, +/* 3065 1056.2 */ 812, +/* 3066 1057.0 */ 462, +/* 3067 1057.1 */ 838, +/* 3068 1057.2 */ 855, +/* 3069 1058.0 */ 444, +/* 3070 1058.1 */ 828, +/* 3071 1058.2 */ 810, +/* 3072 1059.0 */ 444, +/* 3073 1059.1 */ 828, +/* 3074 1059.2 */ 850, +/* 3075 1060.0 */ 858, +/* 3076 1060.1 */ 859, +/* 3077 1060.2 */ 860, +/* 3078 1061.0 */ 858, +/* 3079 1061.1 */ 859, +/* 3080 1061.2 */ 861, +/* 3081 1062.0 */ 862, +/* 3082 1062.1 */ 863, +/* 3083 1062.2 */ 864, +/* 3084 1063.0 */ 862, +/* 3085 1063.1 */ 863, +/* 3086 1063.2 */ 865, +/* 3087 1064.0 */ 462, +/* 3088 1064.1 */ 838, +/* 3089 1064.2 */ 584, +/* 3090 1064.3 */ 120, +/* 3091 1065.0 */ 462, +/* 3092 1065.1 */ 838, +/* 3093 1065.2 */ 840, +/* 3094 1065.3 */ 120, +/* 3095 1066.0 */ 807, +/* 3096 1066.1 */ 843, +/* 3097 1066.2 */ 808, +/* 3098 1066.3 */ 120, +/* 3099 1067.0 */ 807, +/* 3100 1067.1 */ 843, +/* 3101 1067.2 */ 845, +/* 3102 1067.3 */ 120, +/* 3103 1068.0 */ 444, +/* 3104 1068.1 */ 828, +/* 3105 1068.2 */ 587, +/* 3106 1068.3 */ 120, +/* 3107 1069.0 */ 444, +/* 3108 1069.1 */ 828, +/* 3109 1069.2 */ 830, +/* 3110 1069.3 */ 120, +/* 3111 1070.0 */ 804, +/* 3112 1070.1 */ 833, +/* 3113 1070.2 */ 805, +/* 3114 1070.3 */ 120, +/* 3115 1071.0 */ 804, +/* 3116 1071.1 */ 833, +/* 3117 1071.2 */ 835, +/* 3118 1071.3 */ 120, +/* 3119 1072.0 */ 462, +/* 3120 1072.1 */ 838, +/* 3121 1072.2 */ 812, +/* 3122 1072.3 */ 120, +/* 3123 1073.0 */ 462, +/* 3124 1073.1 */ 838, +/* 3125 1073.2 */ 855, +/* 3126 1073.3 */ 120, +/* 3127 1074.0 */ 444, +/* 3128 1074.1 */ 828, +/* 3129 1074.2 */ 810, +/* 3130 1074.3 */ 120, +/* 3131 1075.0 */ 444, +/* 3132 1075.1 */ 828, +/* 3133 1075.2 */ 850, +/* 3134 1075.3 */ 120, +/* 3135 1076.0 */ 866, +/* 3136 1076.1 */ 812, +/* 3137 1076.2 */ 117, +/* 3138 1077.0 */ 866, +/* 3139 1077.1 */ 813, +/* 3140 1077.2 */ 123, +/* 3141 1078.0 */ 867, +/* 3142 1078.1 */ 810, +/* 3143 1078.2 */ 117, +/* 3144 1079.0 */ 867, +/* 3145 1079.1 */ 811, +/* 3146 1079.2 */ 123, +/* 3147 1080.0 */ 462, +/* 3148 1080.1 */ 508, +/* 3149 1081.0 */ 462, +/* 3150 1081.1 */ 550, +/* 3151 1082.0 */ 807, +/* 3152 1082.1 */ 247, +/* 3153 1083.0 */ 807, +/* 3154 1083.1 */ 248, +/* 3155 1084.0 */ 444, +/* 3156 1084.1 */ 247, +/* 3157 1085.0 */ 444, +/* 3158 1085.1 */ 248, +/* 3159 1086.0 */ 804, +/* 3160 1086.1 */ 864, +/* 3161 1087.0 */ 804, +/* 3162 1087.1 */ 868, +/* 3163 1088.0 */ 468, +/* 3164 1088.1 */ 584, +/* 3165 1089.0 */ 468, +/* 3166 1089.1 */ 585, +/* 3167 1090.0 */ 468, +/* 3168 1090.1 */ 808, +/* 3169 1091.0 */ 468, +/* 3170 1091.1 */ 809, +/* 3171 1092.0 */ 444, +/* 3172 1092.1 */ 584, +/* 3173 1093.0 */ 444, +/* 3174 1093.1 */ 585, +/* 3175 1094.0 */ 444, +/* 3176 1094.1 */ 808, +/* 3177 1095.0 */ 444, +/* 3178 1095.1 */ 809, +/* 3179 1096.0 */ 468, +/* 3180 1096.1 */ 587, +/* 3181 1097.0 */ 468, +/* 3182 1097.1 */ 588, +/* 3183 1098.0 */ 862, +/* 3184 1098.1 */ 805, +/* 3185 1099.0 */ 862, +/* 3186 1099.1 */ 806, +/* 3187 1100.0 */ 462, +/* 3188 1100.1 */ 292, +/* 3189 1101.0 */ 462, +/* 3190 1101.1 */ 291, +/* 3191 1102.0 */ 807, +/* 3192 1102.1 */ 587, +/* 3193 1103.0 */ 807, +/* 3194 1103.1 */ 588, +/* 3195 1104.0 */ 560, +/* 3196 1104.1 */ 812, +/* 3197 1105.0 */ 560, +/* 3198 1105.1 */ 813, +/* 3199 1106.0 */ 561, +/* 3200 1106.1 */ 812, +/* 3201 1107.0 */ 561, +/* 3202 1107.1 */ 813, +/* 3203 1108.0 */ 560, +/* 3204 1108.1 */ 810, +/* 3205 1109.0 */ 560, +/* 3206 1109.1 */ 811, +/* 3207 1110.0 */ 561, +/* 3208 1110.1 */ 810, +/* 3209 1111.0 */ 561, +/* 3210 1111.1 */ 811, +/* 3211 1112.0 */ 444, +/* 3212 1112.1 */ 828, +/* 3213 1112.2 */ 812, +/* 3214 1113.0 */ 444, +/* 3215 1113.1 */ 828, +/* 3216 1113.2 */ 855, +/* 3217 1114.0 */ 462, +/* 3218 1114.1 */ 838, +/* 3219 1114.2 */ 269, +/* 3220 1115.0 */ 462, +/* 3221 1115.1 */ 838, +/* 3222 1115.2 */ 869, +/* 3223 1116.0 */ 462, +/* 3224 1116.1 */ 838, +/* 3225 1116.2 */ 219, +/* 3226 1117.0 */ 462, +/* 3227 1117.1 */ 838, +/* 3228 1117.2 */ 870, +/* 3229 1118.0 */ 444, +/* 3230 1118.1 */ 828, +/* 3231 1118.2 */ 269, +/* 3232 1119.0 */ 444, +/* 3233 1119.1 */ 828, +/* 3234 1119.2 */ 869, +/* 3235 1120.0 */ 444, +/* 3236 1120.1 */ 828, +/* 3237 1120.2 */ 219, +/* 3238 1121.0 */ 444, +/* 3239 1121.1 */ 828, +/* 3240 1121.2 */ 870, +/* 3241 1122.0 */ 462, +/* 3242 1122.1 */ 838, +/* 3243 1122.2 */ 810, +/* 3244 1123.0 */ 462, +/* 3245 1123.1 */ 838, +/* 3246 1123.2 */ 850, +/* 3247 1124.0 */ 871, +/* 3248 1124.1 */ 872, +/* 3249 1124.2 */ 120, +/* 3250 1125.0 */ 873, +/* 3251 1125.1 */ 874, +/* 3252 1125.2 */ 120, +/* 3253 1126.0 */ 875, +/* 3254 1126.1 */ 876, +/* 3255 1126.2 */ 120, +/* 3256 1127.0 */ 472, +/* 3257 1127.1 */ 877, +/* 3258 1127.2 */ 120, +/* 3259 1128.0 */ 462, +/* 3260 1128.1 */ 838, +/* 3261 1128.2 */ 253, +/* 3262 1129.0 */ 462, +/* 3263 1129.1 */ 838, +/* 3264 1129.2 */ 797, +/* 3265 1130.0 */ 807, +/* 3266 1130.1 */ 843, +/* 3267 1130.2 */ 860, +/* 3268 1131.0 */ 807, +/* 3269 1131.1 */ 843, +/* 3270 1131.2 */ 861, +/* 3271 1132.0 */ 462, +/* 3272 1132.1 */ 584, +/* 3273 1132.2 */ 120, +/* 3274 1133.0 */ 462, +/* 3275 1133.1 */ 585, +/* 3276 1133.2 */ 120, +/* 3277 1134.0 */ 807, +/* 3278 1134.1 */ 808, +/* 3279 1134.2 */ 120, +/* 3280 1135.0 */ 807, +/* 3281 1135.1 */ 809, +/* 3282 1135.2 */ 120, +/* 3283 1136.0 */ 444, +/* 3284 1136.1 */ 828, +/* 3285 1136.2 */ 514, +/* 3286 1137.0 */ 444, +/* 3287 1137.1 */ 828, +/* 3288 1137.2 */ 794, +/* 3289 1138.0 */ 804, +/* 3290 1138.1 */ 833, +/* 3291 1138.2 */ 878, +/* 3292 1139.0 */ 804, +/* 3293 1139.1 */ 833, +/* 3294 1139.2 */ 879, +/* 3295 1140.0 */ 444, +/* 3296 1140.1 */ 587, +/* 3297 1140.2 */ 120, +/* 3298 1141.0 */ 444, +/* 3299 1141.1 */ 588, +/* 3300 1141.2 */ 120, +/* 3301 1142.0 */ 804, +/* 3302 1142.1 */ 805, +/* 3303 1142.2 */ 120, +/* 3304 1143.0 */ 804, +/* 3305 1143.1 */ 806, +/* 3306 1143.2 */ 120, +/* 3307 1144.0 */ 804, +/* 3308 1144.1 */ 810, +/* 3309 1145.0 */ 804, +/* 3310 1145.1 */ 588, +/* 3311 1146.0 */ 807, +/* 3312 1146.1 */ 812, +/* 3313 1147.0 */ 807, +/* 3314 1147.1 */ 585, +/* 3315 1148.0 */ 807, +/* 3316 1148.1 */ 584, +/* 3317 1149.0 */ 807, +/* 3318 1149.1 */ 843, +/* 3319 1149.2 */ 584, +/* 3320 1149.3 */ 120, +/* 3321 1150.0 */ 807, +/* 3322 1150.1 */ 843, +/* 3323 1150.2 */ 840, +/* 3324 1150.3 */ 120, +/* 3325 1151.0 */ 862, +/* 3326 1151.1 */ 864, +/* 3327 1152.0 */ 444, +/* 3328 1152.1 */ 766, +/* 3329 1152.2 */ 587, +/* 3330 1153.0 */ 804, +/* 3331 1153.1 */ 863, +/* 3332 1153.2 */ 805, +/* 3333 1154.0 */ 880, +/* 3334 1154.1 */ 881, +/* 3335 1154.2 */ 877, +/* 3336 1155.0 */ 882, +/* 3337 1155.1 */ 883, +/* 3338 1155.2 */ 884, +/* 3339 1156.0 */ 462, +/* 3340 1156.1 */ 795, +/* 3341 1156.2 */ 584, +/* 3342 1157.0 */ 807, +/* 3343 1157.1 */ 859, +/* 3344 1157.2 */ 808, +/* 3345 1158.0 */ 871, +/* 3346 1158.1 */ 885, +/* 3347 1158.2 */ 886, +/* 3348 1159.0 */ 887, +/* 3349 1159.1 */ 888, +/* 3350 1159.2 */ 889, +/* 3351 1160.0 */ 890, +/* 3352 1160.1 */ 864, +/* 3353 1160.2 */ 117, +/* 3354 1161.0 */ 890, +/* 3355 1161.1 */ 868, +/* 3356 1161.2 */ 123, +/* 3357 1162.0 */ 876, +/* 3358 1162.1 */ 587, +/* 3359 1162.2 */ 117, +/* 3360 1163.0 */ 876, +/* 3361 1163.1 */ 588, +/* 3362 1163.2 */ 123, +/* 3363 1164.0 */ 891, +/* 3364 1164.1 */ 805, +/* 3365 1164.2 */ 117, +/* 3366 1165.0 */ 891, +/* 3367 1165.1 */ 806, +/* 3368 1165.2 */ 123, +/* 3369 1166.0 */ 892, +/* 3370 1166.1 */ 584, +/* 3371 1166.2 */ 117, +/* 3372 1167.0 */ 892, +/* 3373 1167.1 */ 585, +/* 3374 1167.2 */ 123, +/* 3375 1168.0 */ 893, +/* 3376 1168.1 */ 808, +/* 3377 1168.2 */ 117, +/* 3378 1169.0 */ 893, +/* 3379 1169.1 */ 809, +/* 3380 1169.2 */ 123, +/* 3381 1170.0 */ 871, +/* 3382 1170.1 */ 892, +/* 3383 1171.0 */ 873, +/* 3384 1171.1 */ 886, +/* 3385 1172.0 */ 887, +/* 3386 1172.1 */ 893, +/* 3387 1173.0 */ 894, +/* 3388 1173.1 */ 889, +/* 3389 1174.0 */ 880, +/* 3390 1174.1 */ 876, +/* 3391 1175.0 */ 895, +/* 3392 1175.1 */ 877, +/* 3393 1176.0 */ 882, +/* 3394 1176.1 */ 891, +/* 3395 1177.0 */ 896, +/* 3396 1177.1 */ 884, +/* 3397 1178.0 */ 468, +/* 3398 1178.1 */ 558, +/* 3399 1179.0 */ 593, +/* 3400 1179.1 */ 565, +/* 3401 1180.0 */ 468, +/* 3402 1180.1 */ 562, +/* 3403 1181.0 */ 596, +/* 3404 1181.1 */ 570, +/* 3405 1182.0 */ 862, +/* 3406 1182.1 */ 868, +/* 3407 1183.0 */ 897, +/* 3408 1183.1 */ 890, +/* 3409 1184.0 */ 898, +/* 3410 1184.1 */ 899, +/* 3411 1185.0 */ 900, +/* 3412 1185.1 */ 901, +/* 3413 1185.2 */ 902, +/* 3414 1186.0 */ 900, +/* 3415 1186.1 */ 901, +/* 3416 1186.2 */ 903, +/* 3417 1187.0 */ 904, +/* 3418 1187.1 */ 905, +/* 3419 1187.2 */ 906, +/* 3420 1188.0 */ 904, +/* 3421 1188.1 */ 905, +/* 3422 1188.2 */ 907, +/* 3423 1189.0 */ 785, +/* 3424 1189.1 */ 506, +/* 3425 1190.0 */ 785, +/* 3426 1190.1 */ 507, +/* 3427 1191.0 */ 908, +/* 3428 1191.1 */ 909, +/* 3429 1192.0 */ 908, +/* 3430 1192.1 */ 910, +/* 3431 1193.0 */ 516, +/* 3432 1193.1 */ 500, +/* 3433 1194.0 */ 516, +/* 3434 1194.1 */ 501, +/* 3435 1195.0 */ 911, +/* 3436 1195.1 */ 912, +/* 3437 1196.0 */ 911, +/* 3438 1196.1 */ 913, +/* 3439 1197.0 */ 513, +/* 3440 1197.1 */ 247, +/* 3441 1198.0 */ 513, +/* 3442 1198.1 */ 248, +/* 3443 1199.0 */ 914, +/* 3444 1199.1 */ 864, +/* 3445 1200.0 */ 914, +/* 3446 1200.1 */ 868, +/* 3447 1201.0 */ 516, +/* 3448 1201.1 */ 517, +/* 3449 1202.0 */ 516, +/* 3450 1202.1 */ 518, +/* 3451 1203.0 */ 914, +/* 3452 1203.1 */ 878, +/* 3453 1203.2 */ 120, +/* 3454 1204.0 */ 914, +/* 3455 1204.1 */ 915, +/* 3456 1204.2 */ 120, +/* 3457 1205.0 */ 911, +/* 3458 1205.1 */ 916, +/* 3459 1205.2 */ 120, +/* 3460 1206.0 */ 911, +/* 3461 1206.1 */ 917, +/* 3462 1206.2 */ 120, +/* 3463 1207.0 */ 798, +/* 3464 1207.1 */ 760, +/* 3465 1207.2 */ 500, +/* 3466 1208.0 */ 798, +/* 3467 1208.1 */ 760, +/* 3468 1208.2 */ 762, +/* 3469 1209.0 */ 918, +/* 3470 1209.1 */ 919, +/* 3471 1209.2 */ 912, +/* 3472 1210.0 */ 918, +/* 3473 1210.1 */ 919, +/* 3474 1210.2 */ 920, +/* 3475 1211.0 */ 600, +/* 3476 1211.1 */ 766, +/* 3477 1211.2 */ 247, +/* 3478 1212.0 */ 600, +/* 3479 1212.1 */ 766, +/* 3480 1212.2 */ 768, +/* 3481 1213.0 */ 921, +/* 3482 1213.1 */ 863, +/* 3483 1213.2 */ 864, +/* 3484 1214.0 */ 921, +/* 3485 1214.1 */ 863, +/* 3486 1214.2 */ 865, +/* 3487 1215.0 */ 785, +/* 3488 1215.1 */ 760, +/* 3489 1215.2 */ 500, +/* 3490 1216.0 */ 785, +/* 3491 1216.1 */ 760, +/* 3492 1216.2 */ 762, +/* 3493 1217.0 */ 908, +/* 3494 1217.1 */ 919, +/* 3495 1217.2 */ 912, +/* 3496 1218.0 */ 908, +/* 3497 1218.1 */ 919, +/* 3498 1218.2 */ 920, +/* 3499 1219.0 */ 516, +/* 3500 1219.1 */ 766, +/* 3501 1219.2 */ 247, +/* 3502 1220.0 */ 516, +/* 3503 1220.1 */ 766, +/* 3504 1220.2 */ 768, +/* 3505 1221.0 */ 911, +/* 3506 1221.1 */ 863, +/* 3507 1221.2 */ 864, +/* 3508 1222.0 */ 911, +/* 3509 1222.1 */ 863, +/* 3510 1222.2 */ 865, +/* 3511 1223.0 */ 516, +/* 3512 1223.1 */ 789, +/* 3513 1223.2 */ 253, +/* 3514 1224.0 */ 516, +/* 3515 1224.1 */ 789, +/* 3516 1224.2 */ 797, +/* 3517 1225.0 */ 922, +/* 3518 1225.1 */ 518, +/* 3519 1225.2 */ 120, +/* 3520 1226.0 */ 911, +/* 3521 1226.1 */ 923, +/* 3522 1226.2 */ 253, +/* 3523 1227.0 */ 911, +/* 3524 1227.1 */ 923, +/* 3525 1227.2 */ 924, +/* 3526 1228.0 */ 925, +/* 3527 1228.1 */ 917, +/* 3528 1228.2 */ 120, +/* 3529 1229.0 */ 513, +/* 3530 1229.1 */ 792, +/* 3531 1229.2 */ 253, +/* 3532 1230.0 */ 513, +/* 3533 1230.1 */ 792, +/* 3534 1230.2 */ 797, +/* 3535 1231.0 */ 926, +/* 3536 1231.1 */ 515, +/* 3537 1231.2 */ 120, +/* 3538 1232.0 */ 914, +/* 3539 1232.1 */ 927, +/* 3540 1232.2 */ 253, +/* 3541 1233.0 */ 914, +/* 3542 1233.1 */ 927, +/* 3543 1233.2 */ 924, +/* 3544 1234.0 */ 928, +/* 3545 1234.1 */ 915, +/* 3546 1234.2 */ 120, +/* 3547 1235.0 */ 929, +/* 3548 1235.1 */ 254, +/* 3549 1235.2 */ 120, +/* 3550 1236.0 */ 858, +/* 3551 1236.1 */ 859, +/* 3552 1236.2 */ 253, +/* 3553 1237.0 */ 858, +/* 3554 1237.1 */ 859, +/* 3555 1237.2 */ 924, +/* 3556 1238.0 */ 930, +/* 3557 1238.1 */ 931, +/* 3558 1238.2 */ 120, +/* 3559 1239.0 */ 600, +/* 3560 1239.1 */ 760, +/* 3561 1239.2 */ 253, +/* 3562 1240.0 */ 600, +/* 3563 1240.1 */ 760, +/* 3564 1240.2 */ 797, +/* 3565 1241.0 */ 932, +/* 3566 1241.1 */ 501, +/* 3567 1241.2 */ 120, +/* 3568 1242.0 */ 921, +/* 3569 1242.1 */ 919, +/* 3570 1242.2 */ 253, +/* 3571 1243.0 */ 921, +/* 3572 1243.1 */ 919, +/* 3573 1243.2 */ 924, +/* 3574 1244.0 */ 933, +/* 3575 1244.1 */ 913, +/* 3576 1244.2 */ 120, +/* 3577 1245.0 */ 468, +/* 3578 1245.1 */ 766, +/* 3579 1245.2 */ 253, +/* 3580 1246.0 */ 468, +/* 3581 1246.1 */ 766, +/* 3582 1246.2 */ 797, +/* 3583 1247.0 */ 934, +/* 3584 1247.1 */ 248, +/* 3585 1247.2 */ 120, +/* 3586 1248.0 */ 862, +/* 3587 1248.1 */ 863, +/* 3588 1248.2 */ 253, +/* 3589 1249.0 */ 862, +/* 3590 1249.1 */ 863, +/* 3591 1249.2 */ 924, +/* 3592 1250.0 */ 935, +/* 3593 1250.1 */ 868, +/* 3594 1250.2 */ 120, +/* 3595 1251.0 */ 918, +/* 3596 1251.1 */ 936, +/* 3597 1251.2 */ 909, +/* 3598 1252.0 */ 918, +/* 3599 1252.1 */ 936, +/* 3600 1252.2 */ 937, +/* 3601 1253.0 */ 921, +/* 3602 1253.1 */ 919, +/* 3603 1253.2 */ 912, +/* 3604 1254.0 */ 921, +/* 3605 1254.1 */ 919, +/* 3606 1254.2 */ 920, +/* 3607 1255.0 */ 938, +/* 3608 1255.1 */ 939, +/* 3609 1255.2 */ 940, +/* 3610 1256.0 */ 938, +/* 3611 1256.1 */ 939, +/* 3612 1256.2 */ 941, +/* 3613 1257.0 */ 908, +/* 3614 1257.1 */ 942, +/* 3615 1257.2 */ 943, +/* 3616 1258.0 */ 908, +/* 3617 1258.1 */ 942, +/* 3618 1258.2 */ 944, +/* 3619 1259.0 */ 911, +/* 3620 1259.1 */ 923, +/* 3621 1259.2 */ 916, +/* 3622 1260.0 */ 911, +/* 3623 1260.1 */ 923, +/* 3624 1260.2 */ 945, +/* 3625 1261.0 */ 914, +/* 3626 1261.1 */ 927, +/* 3627 1261.2 */ 878, +/* 3628 1262.0 */ 914, +/* 3629 1262.1 */ 927, +/* 3630 1262.2 */ 879, +/* 3631 1263.0 */ 468, +/* 3632 1263.1 */ 801, +/* 3633 1263.2 */ 802, +/* 3634 1264.0 */ 468, +/* 3635 1264.1 */ 801, +/* 3636 1264.2 */ 803, +/* 3637 1265.0 */ 540, +/* 3638 1265.1 */ 792, +/* 3639 1265.2 */ 514, +/* 3640 1266.0 */ 540, +/* 3641 1266.1 */ 792, +/* 3642 1266.2 */ 794, +/* 3643 1267.0 */ 858, +/* 3644 1267.1 */ 927, +/* 3645 1267.2 */ 878, +/* 3646 1268.0 */ 858, +/* 3647 1268.1 */ 927, +/* 3648 1268.2 */ 879, +/* 3649 1269.0 */ 604, +/* 3650 1269.1 */ 766, +/* 3651 1269.2 */ 247, +/* 3652 1270.0 */ 604, +/* 3653 1270.1 */ 766, +/* 3654 1270.2 */ 768, +/* 3655 1271.0 */ 938, +/* 3656 1271.1 */ 863, +/* 3657 1271.2 */ 864, +/* 3658 1272.0 */ 938, +/* 3659 1272.1 */ 863, +/* 3660 1272.2 */ 865, +/* 3661 1273.0 */ 516, +/* 3662 1273.1 */ 786, +/* 3663 1273.2 */ 545, +/* 3664 1274.0 */ 516, +/* 3665 1274.1 */ 786, +/* 3666 1274.2 */ 788, +/* 3667 1275.0 */ 911, +/* 3668 1275.1 */ 942, +/* 3669 1275.2 */ 943, +/* 3670 1276.0 */ 911, +/* 3671 1276.1 */ 942, +/* 3672 1276.2 */ 944, +/* 3673 1277.0 */ 946, +/* 3674 1277.1 */ 947, +/* 3675 1277.2 */ 120, +/* 3676 1278.0 */ 948, +/* 3677 1278.1 */ 949, +/* 3678 1278.2 */ 120, +/* 3679 1279.0 */ 444, +/* 3680 1279.1 */ 950, +/* 3681 1279.2 */ 951, +/* 3682 1280.0 */ 908, +/* 3683 1280.1 */ 942, +/* 3684 1280.2 */ 943, +/* 3685 1280.3 */ 120, +/* 3686 1281.0 */ 908, +/* 3687 1281.1 */ 942, +/* 3688 1281.2 */ 944, +/* 3689 1281.3 */ 120, +/* 3690 1282.0 */ 911, +/* 3691 1282.1 */ 923, +/* 3692 1282.2 */ 916, +/* 3693 1282.3 */ 120, +/* 3694 1283.0 */ 911, +/* 3695 1283.1 */ 923, +/* 3696 1283.2 */ 945, +/* 3697 1283.3 */ 120, +/* 3698 1284.0 */ 468, +/* 3699 1284.1 */ 760, +/* 3700 1284.2 */ 500, +/* 3701 1285.0 */ 468, +/* 3702 1285.1 */ 760, +/* 3703 1285.2 */ 762, +/* 3704 1286.0 */ 862, +/* 3705 1286.1 */ 919, +/* 3706 1286.2 */ 912, +/* 3707 1287.0 */ 862, +/* 3708 1287.1 */ 919, +/* 3709 1287.2 */ 920, +/* 3710 1288.0 */ 600, +/* 3711 1288.1 */ 786, +/* 3712 1288.2 */ 506, +/* 3713 1289.0 */ 600, +/* 3714 1289.1 */ 786, +/* 3715 1289.2 */ 800, +/* 3716 1290.0 */ 921, +/* 3717 1290.1 */ 942, +/* 3718 1290.2 */ 909, +/* 3719 1291.0 */ 921, +/* 3720 1291.1 */ 942, +/* 3721 1291.2 */ 937, +/* 3722 1292.0 */ 516, +/* 3723 1292.1 */ 786, +/* 3724 1292.2 */ 545, +/* 3725 1292.3 */ 120, +/* 3726 1293.0 */ 516, +/* 3727 1293.1 */ 786, +/* 3728 1293.2 */ 788, +/* 3729 1293.3 */ 120, +/* 3730 1294.0 */ 911, +/* 3731 1294.1 */ 942, +/* 3732 1294.2 */ 943, +/* 3733 1294.3 */ 120, +/* 3734 1295.0 */ 911, +/* 3735 1295.1 */ 942, +/* 3736 1295.2 */ 944, +/* 3737 1295.3 */ 120, +/* 3738 1296.0 */ 892, +/* 3739 1296.1 */ 812, +/* 3740 1296.2 */ 117, +/* 3741 1297.0 */ 892, +/* 3742 1297.1 */ 813, +/* 3743 1297.2 */ 123, +/* 3744 1298.0 */ 876, +/* 3745 1298.1 */ 810, +/* 3746 1298.2 */ 117, +/* 3747 1299.0 */ 876, +/* 3748 1299.1 */ 811, +/* 3749 1299.2 */ 123, +/* 3750 1300.0 */ 875, +/* 3751 1300.1 */ 867, +/* 3752 1301.0 */ 895, +/* 3753 1301.1 */ 828, +/* 3754 1301.2 */ 952, +/* 3755 1302.0 */ 953, +/* 3756 1302.1 */ 866, +/* 3757 1303.0 */ 873, +/* 3758 1303.1 */ 838, +/* 3759 1303.2 */ 954, +/* 3760 1304.0 */ 444, +/* 3761 1304.1 */ 828, +/* 3762 1304.2 */ 292, +/* 3763 1305.0 */ 462, +/* 3764 1305.1 */ 853, +/* 3765 1305.2 */ 812, +/* 3766 1306.0 */ 953, +/* 3767 1306.1 */ 892, +/* 3768 1307.0 */ 444, +/* 3769 1307.1 */ 950, +/* 3770 1307.2 */ 292, +/* 3771 1308.0 */ 293, +/* 3772 1308.1 */ 876, +/* 3773 1309.0 */ 560, +/* 3774 1309.1 */ 585, +/* 3775 1310.0 */ 560, +/* 3776 1310.1 */ 809, +/* 3777 1311.0 */ 560, +/* 3778 1311.1 */ 588, +/* 3779 1312.0 */ 560, +/* 3780 1312.1 */ 806, +/* 3781 1313.0 */ 955, +/* 3782 1313.1 */ 507, +/* 3783 1314.0 */ 955, +/* 3784 1314.1 */ 910, +/* 3785 1315.0 */ 921, +/* 3786 1315.1 */ 507, +/* 3787 1316.0 */ 921, +/* 3788 1316.1 */ 506, +/* 3789 1317.0 */ 862, +/* 3790 1317.1 */ 601, +/* 3791 1318.0 */ 862, +/* 3792 1318.1 */ 503, +/* 3793 1319.0 */ 938, +/* 3794 1319.1 */ 603, +/* 3795 1320.0 */ 938, +/* 3796 1320.1 */ 602, +/* 3797 1321.0 */ 862, +/* 3798 1321.1 */ 501, +/* 3799 1322.0 */ 862, +/* 3800 1322.1 */ 500, +/* 3801 1323.0 */ 938, +/* 3802 1323.1 */ 607, +/* 3803 1324.0 */ 938, +/* 3804 1324.1 */ 498, +/* 3805 1325.0 */ 938, +/* 3806 1325.1 */ 248, +/* 3807 1326.0 */ 938, +/* 3808 1326.1 */ 247, +/* 3809 1327.0 */ 911, +/* 3810 1327.1 */ 546, +/* 3811 1328.0 */ 911, +/* 3812 1328.1 */ 545, +/* 3813 1329.0 */ 914, +/* 3814 1329.1 */ 611, +/* 3815 1330.0 */ 914, +/* 3816 1330.1 */ 610, +/* 3817 1331.0 */ 858, +/* 3818 1331.1 */ 612, +/* 3819 1332.0 */ 858, +/* 3820 1332.1 */ 492, +/* 3821 1333.0 */ 914, +/* 3822 1333.1 */ 518, +/* 3823 1334.0 */ 914, +/* 3824 1334.1 */ 517, +/* 3825 1335.0 */ 858, +/* 3826 1335.1 */ 615, +/* 3827 1336.0 */ 858, +/* 3828 1336.1 */ 511, +/* 3829 1337.0 */ 858, +/* 3830 1337.1 */ 515, +/* 3831 1338.0 */ 858, +/* 3832 1338.1 */ 514, +/* 3833 1339.0 */ 232, +/* 3834 1339.1 */ 753, +/* 3835 1339.2 */ 120, +/* 3836 1340.0 */ 593, +/* 3837 1340.1 */ 956, +/* 3838 1340.2 */ 120, +/* 3839 1341.0 */ 201, +/* 3840 1341.1 */ 957, +/* 3841 1341.2 */ 120, +/* 3842 1342.0 */ 593, +/* 3843 1342.1 */ 958, +/* 3844 1342.2 */ 120, +/* 3845 1343.0 */ 560, +/* 3846 1343.1 */ 518, +/* 3847 1343.2 */ 120, +/* 3848 1344.0 */ 220, +/* 3849 1344.1 */ 959, +/* 3850 1344.2 */ 120, +/* 3851 1345.0 */ 596, +/* 3852 1345.1 */ 960, +/* 3853 1345.2 */ 120, +/* 3854 1346.0 */ 271, +/* 3855 1346.1 */ 961, +/* 3856 1346.2 */ 120, +/* 3857 1347.0 */ 593, +/* 3858 1347.1 */ 962, +/* 3859 1347.2 */ 120, +/* 3860 1348.0 */ 785, +/* 3861 1348.1 */ 786, +/* 3862 1348.2 */ 126, +/* 3863 1348.3 */ 120, +/* 3864 1349.0 */ 785, +/* 3865 1349.1 */ 786, +/* 3866 1349.2 */ 963, +/* 3867 1349.3 */ 120, +/* 3868 1350.0 */ 516, +/* 3869 1350.1 */ 789, +/* 3870 1350.2 */ 535, +/* 3871 1350.3 */ 120, +/* 3872 1351.0 */ 516, +/* 3873 1351.1 */ 789, +/* 3874 1351.2 */ 964, +/* 3875 1351.3 */ 120, +/* 3876 1352.0 */ 513, +/* 3877 1352.1 */ 792, +/* 3878 1352.2 */ 496, +/* 3879 1352.3 */ 120, +/* 3880 1353.0 */ 513, +/* 3881 1353.1 */ 792, +/* 3882 1353.2 */ 965, +/* 3883 1353.3 */ 120, +/* 3884 1354.0 */ 540, +/* 3885 1354.1 */ 795, +/* 3886 1354.2 */ 538, +/* 3887 1354.3 */ 120, +/* 3888 1355.0 */ 540, +/* 3889 1355.1 */ 795, +/* 3890 1355.2 */ 966, +/* 3891 1355.3 */ 120, +/* 3892 1356.0 */ 753, +/* 3893 1356.1 */ 546, +/* 3894 1356.2 */ 967, +/* 3895 1356.3 */ 554, +/* 3896 1357.0 */ 798, +/* 3897 1357.1 */ 799, +/* 3898 1357.2 */ 506, +/* 3899 1357.3 */ 968, +/* 3900 1358.0 */ 798, +/* 3901 1358.1 */ 799, +/* 3902 1358.2 */ 800, +/* 3903 1358.3 */ 969, +/* 3904 1359.0 */ 908, +/* 3905 1359.1 */ 942, +/* 3906 1359.2 */ 943, +/* 3907 1359.3 */ 970, +/* 3908 1360.0 */ 908, +/* 3909 1360.1 */ 942, +/* 3910 1360.2 */ 944, +/* 3911 1360.3 */ 971, +/* 3912 1361.0 */ 462, +/* 3913 1361.1 */ 838, +/* 3914 1361.2 */ 584, +/* 3915 1361.3 */ 972, +/* 3916 1362.0 */ 462, +/* 3917 1362.1 */ 838, +/* 3918 1362.2 */ 840, +/* 3919 1362.3 */ 973, +/* 3920 1363.0 */ 807, +/* 3921 1363.1 */ 843, +/* 3922 1363.2 */ 808, +/* 3923 1363.3 */ 974, +/* 3924 1364.0 */ 807, +/* 3925 1364.1 */ 843, +/* 3926 1364.2 */ 845, +/* 3927 1364.3 */ 975, +/* 3928 1365.0 */ 444, +/* 3929 1365.1 */ 828, +/* 3930 1365.2 */ 587, +/* 3931 1365.3 */ 976, +/* 3932 1366.0 */ 444, +/* 3933 1366.1 */ 828, +/* 3934 1366.2 */ 830, +/* 3935 1366.3 */ 977, +/* 3936 1367.0 */ 804, +/* 3937 1367.1 */ 833, +/* 3938 1367.2 */ 805, +/* 3939 1367.3 */ 978, +/* 3940 1368.0 */ 804, +/* 3941 1368.1 */ 833, +/* 3942 1368.2 */ 835, +/* 3943 1368.3 */ 979, +/* 3944 1369.0 */ 980, +/* 3945 1369.1 */ 981, +/* 3946 1369.2 */ 982, +/* 3947 1370.0 */ 980, +/* 3948 1370.1 */ 981, +/* 3949 1370.2 */ 983, +/* 3950 1371.0 */ 900, +/* 3951 1371.1 */ 795, +/* 3952 1371.2 */ 797, +/* 3953 1371.3 */ 120, +/* 3954 1372.0 */ 900, +/* 3955 1372.1 */ 795, +/* 3956 1372.2 */ 253, +/* 3957 1372.3 */ 120, +/* 3958 1373.0 */ 980, +/* 3959 1373.1 */ 859, +/* 3960 1373.2 */ 861, +/* 3961 1373.3 */ 120, +/* 3962 1374.0 */ 980, +/* 3963 1374.1 */ 859, +/* 3964 1374.2 */ 860, +/* 3965 1374.3 */ 120, +/* 3966 1375.0 */ 444, +/* 3967 1375.1 */ 984, +/* 3968 1376.0 */ 444, +/* 3969 1376.1 */ 985, +/* 3970 1377.0 */ 804, +/* 3971 1377.1 */ 986, +/* 3972 1378.0 */ 804, +/* 3973 1378.1 */ 987, +/* 3974 1379.0 */ 988, +/* 3975 1379.1 */ 876, +/* 3976 1379.2 */ 120, +/* 3977 1380.0 */ 989, +/* 3978 1380.1 */ 877, +/* 3979 1380.2 */ 120, +/* 3980 1381.0 */ 990, +/* 3981 1381.1 */ 891, +/* 3982 1381.2 */ 120, +/* 3983 1382.0 */ 991, +/* 3984 1382.1 */ 884, +/* 3985 1382.2 */ 120, +/* 3986 1383.0 */ 583, +/* 3987 1383.1 */ 838, +/* 3988 1383.2 */ 584, +/* 3989 1384.0 */ 583, +/* 3990 1384.1 */ 838, +/* 3991 1384.2 */ 840, +/* 3992 1385.0 */ 992, +/* 3993 1385.1 */ 843, +/* 3994 1385.2 */ 808, +/* 3995 1386.0 */ 992, +/* 3996 1386.1 */ 843, +/* 3997 1386.2 */ 845, +/* 3998 1387.0 */ 586, +/* 3999 1387.1 */ 828, +/* 4000 1387.2 */ 587, +/* 4001 1388.0 */ 586, +/* 4002 1388.1 */ 828, +/* 4003 1388.2 */ 830, +/* 4004 1389.0 */ 993, +/* 4005 1389.1 */ 833, +/* 4006 1389.2 */ 805, +/* 4007 1390.0 */ 993, +/* 4008 1390.1 */ 833, +/* 4009 1390.2 */ 835, +/* 4010 1391.0 */ 583, +/* 4011 1391.1 */ 853, +/* 4012 1391.2 */ 812, +/* 4013 1392.0 */ 583, +/* 4014 1392.1 */ 853, +/* 4015 1392.2 */ 855, +/* 4016 1393.0 */ 586, +/* 4017 1393.1 */ 848, +/* 4018 1393.2 */ 810, +/* 4019 1394.0 */ 586, +/* 4020 1394.1 */ 848, +/* 4021 1394.2 */ 850, +/* 4022 1395.0 */ 994, +/* 4023 1395.1 */ 812, +/* 4024 1395.2 */ 995, +/* 4025 1396.0 */ 996, +/* 4026 1396.1 */ 812, +/* 4027 1396.2 */ 997, +/* 4028 1397.0 */ 998, +/* 4029 1397.1 */ 810, +/* 4030 1397.2 */ 999, +/* 4031 1398.0 */ 1000, +/* 4032 1398.1 */ 810, +/* 4033 1398.2 */ 1001, +/* 4034 1399.0 */ 1002, +/* 4035 1399.1 */ 810, +/* 4036 1399.2 */ 1003, +/* 4037 1400.0 */ 1004, +/* 4038 1400.1 */ 538, +/* 4039 1400.2 */ 995, +/* 4040 1401.0 */ 1005, +/* 4041 1401.1 */ 538, +/* 4042 1401.2 */ 997, +/* 4043 1402.0 */ 1006, +/* 4044 1402.1 */ 496, +/* 4045 1402.2 */ 999, +/* 4046 1403.0 */ 1007, +/* 4047 1403.1 */ 496, +/* 4048 1403.2 */ 1001, +/* 4049 1404.0 */ 1008, +/* 4050 1404.1 */ 496, +/* 4051 1404.2 */ 1003, +/* 4052 1405.0 */ 980, +/* 4053 1405.1 */ 981, +/* 4054 1405.2 */ 902, +/* 4055 1405.3 */ 120, +/* 4056 1406.0 */ 980, +/* 4057 1406.1 */ 981, +/* 4058 1406.2 */ 903, +/* 4059 1406.3 */ 120, +/* 4060 1407.0 */ 1009, +/* 4061 1407.1 */ 1010, +/* 4062 1407.2 */ 120, +/* 4063 1408.0 */ 1011, +/* 4064 1408.1 */ 1012, +/* 4065 1408.2 */ 120, +/* 4066 1409.0 */ 1013, +/* 4067 1409.1 */ 1014, +/* 4068 1409.2 */ 962, +/* 4069 1410.0 */ 1015, +/* 4070 1410.1 */ 1016, +/* 4071 1410.2 */ 1017, +/* 4072 1411.0 */ 676, +/* 4073 1411.1 */ 885, +/* 4074 1411.2 */ 960, +/* 4075 1412.0 */ 1018, +/* 4076 1412.1 */ 888, +/* 4077 1412.2 */ 1019, +/* 4078 1413.0 */ 980, +/* 4079 1413.1 */ 981, +/* 4080 1413.2 */ 983, +/* 4081 1413.3 */ 120, +/* 4082 1414.0 */ 980, +/* 4083 1414.1 */ 981, +/* 4084 1414.2 */ 982, +/* 4085 1414.3 */ 120, +/* 4086 1415.0 */ 858, +/* 4087 1415.1 */ 860, +/* 4088 1415.2 */ 120, +/* 4089 1416.0 */ 858, +/* 4090 1416.1 */ 931, +/* 4091 1416.2 */ 120, +/* 4092 1417.0 */ 914, +/* 4093 1417.1 */ 927, +/* 4094 1417.2 */ 878, +/* 4095 1417.3 */ 120, +/* 4096 1418.0 */ 914, +/* 4097 1418.1 */ 927, +/* 4098 1418.2 */ 879, +/* 4099 1418.3 */ 120, +/* 4100 1419.0 */ 785, +/* 4101 1419.1 */ 126, +/* 4102 1420.0 */ 785, +/* 4103 1420.1 */ 1020, +/* 4104 1421.0 */ 908, +/* 4105 1421.1 */ 126, +/* 4106 1422.0 */ 908, +/* 4107 1422.1 */ 1020, +/* 4108 1423.0 */ 516, +/* 4109 1423.1 */ 535, +/* 4110 1424.0 */ 516, +/* 4111 1424.1 */ 1021, +/* 4112 1425.0 */ 911, +/* 4113 1425.1 */ 535, +/* 4114 1426.0 */ 911, +/* 4115 1426.1 */ 1021, +/* 4116 1427.0 */ 513, +/* 4117 1427.1 */ 496, +/* 4118 1428.0 */ 513, +/* 4119 1428.1 */ 1022, +/* 4120 1429.0 */ 914, +/* 4121 1429.1 */ 496, +/* 4122 1430.0 */ 914, +/* 4123 1430.1 */ 1022, +/* 4124 1431.0 */ 540, +/* 4125 1431.1 */ 538, +/* 4126 1432.0 */ 540, +/* 4127 1432.1 */ 542, +/* 4128 1433.0 */ 858, +/* 4129 1433.1 */ 538, +/* 4130 1434.0 */ 858, +/* 4131 1434.1 */ 542, +/* 4132 1435.0 */ 980, +/* 4133 1435.1 */ 902, +/* 4134 1436.0 */ 819, +/* 4135 1436.1 */ 1023, +/* 4136 1436.2 */ 269, +/* 4137 1437.0 */ 819, +/* 4138 1437.1 */ 1023, +/* 4139 1437.2 */ 1024, +/* 4140 1438.0 */ 1025, +/* 4141 1438.1 */ 1026, +/* 4142 1438.2 */ 219, +/* 4143 1439.0 */ 1025, +/* 4144 1439.1 */ 1026, +/* 4145 1439.2 */ 1027, +/* 4146 1440.0 */ 819, +/* 4147 1440.1 */ 1023, +/* 4148 1440.2 */ 269, +/* 4149 1440.3 */ 123, +/* 4150 1441.0 */ 819, +/* 4151 1441.1 */ 1023, +/* 4152 1441.2 */ 1024, +/* 4153 1441.3 */ 97, +/* 4154 1442.0 */ 1025, +/* 4155 1442.1 */ 1026, +/* 4156 1442.2 */ 219, +/* 4157 1442.3 */ 123, +/* 4158 1443.0 */ 1025, +/* 4159 1443.1 */ 1026, +/* 4160 1443.2 */ 1027, +/* 4161 1443.3 */ 97, +/* 4162 1444.0 */ 1028, +/* 4163 1444.1 */ 219, +/* 4164 1444.2 */ 117, +/* 4165 1445.0 */ 1028, +/* 4166 1445.1 */ 1029, +/* 4167 1445.2 */ 123, +/* 4168 1446.0 */ 819, +/* 4169 1446.1 */ 269, +/* 4170 1446.2 */ 1023, +/* 4171 1446.3 */ 123, +/* 4172 1447.0 */ 819, +/* 4173 1447.1 */ 822, +/* 4174 1447.2 */ 1030, +/* 4175 1447.3 */ 97, +/* 4176 1448.0 */ 1025, +/* 4177 1448.1 */ 219, +/* 4178 1448.2 */ 1026, +/* 4179 1448.3 */ 123, +/* 4180 1449.0 */ 1025, +/* 4181 1449.1 */ 1029, +/* 4182 1449.2 */ 1031, +/* 4183 1449.3 */ 97, +/* 4184 1450.0 */ 819, +/* 4185 1450.1 */ 269, +/* 4186 1450.2 */ 1023, +/* 4187 1451.0 */ 819, +/* 4188 1451.1 */ 822, +/* 4189 1451.2 */ 1030, +/* 4190 1452.0 */ 1025, +/* 4191 1452.1 */ 219, +/* 4192 1452.2 */ 1026, +/* 4193 1453.0 */ 1025, +/* 4194 1453.1 */ 1029, +/* 4195 1453.2 */ 1031, +/* 4196 1454.0 */ 819, +/* 4197 1454.1 */ 1032, +/* 4198 1454.2 */ 1024, +/* 4199 1454.3 */ 309, +/* 4200 1455.0 */ 819, +/* 4201 1455.1 */ 1032, +/* 4202 1455.2 */ 269, +/* 4203 1455.3 */ 281, +/* 4204 1456.0 */ 1025, +/* 4205 1456.1 */ 1033, +/* 4206 1456.2 */ 1027, +/* 4207 1456.3 */ 483, +/* 4208 1457.0 */ 1025, +/* 4209 1457.1 */ 1033, +/* 4210 1457.2 */ 219, +/* 4211 1457.3 */ 622, +/* 4212 1458.0 */ 819, +/* 4213 1458.1 */ 822, +/* 4214 1458.2 */ 120, +/* 4215 1459.0 */ 819, +/* 4216 1459.1 */ 269, +/* 4217 1459.2 */ 120, +/* 4218 1460.0 */ 1025, +/* 4219 1460.1 */ 1029, +/* 4220 1460.2 */ 120, +/* 4221 1461.0 */ 1025, +/* 4222 1461.1 */ 219, +/* 4223 1461.2 */ 120, +/* 4224 1462.0 */ 1034, +/* 4225 1462.1 */ 1035, +/* 4226 1462.2 */ 1036, +/* 4227 1463.0 */ 1034, +/* 4228 1463.1 */ 1037, +/* 4229 1464.0 */ 1034, +/* 4230 1464.1 */ 1038, +/* 4231 1465.0 */ 1039, +/* 4232 1465.1 */ 1040, +/* 4233 1466.0 */ 1034, +/* 4234 1466.1 */ 1041, +/* 4235 1467.0 */ 955, +/* 4236 1467.1 */ 1042, +/* 4237 1468.0 */ 1034, +/* 4238 1468.1 */ 1042, +/* 4239 1469.0 */ 1040, +/* 4240 1469.1 */ 1042, +/* 4241 1469.2 */ 123, +/* 4242 1470.0 */ 1034, +/* 4243 1470.1 */ 1042, +/* 4244 1470.2 */ 120, +/* 4245 1471.0 */ 1034, +/* 4246 1471.1 */ 1043, +/* 4247 1472.0 */ 1034, +/* 4248 1472.1 */ 126, +/* 4249 1473.0 */ 232, +/* 4250 1473.1 */ 1040, +/* 4251 1474.0 */ 1034, +/* 4252 1474.1 */ 1044, +/* 4253 1475.0 */ 1034, +/* 4254 1475.1 */ 496, +/* 4255 1476.0 */ 690, +/* 4256 1476.1 */ 1040, +/* 4257 1477.0 */ 1034, +/* 4258 1477.1 */ 1045, +/* 4259 1478.0 */ 1034, +/* 4260 1478.1 */ 538, +/* 4261 1479.0 */ 692, +/* 4262 1479.1 */ 1040, +/* 4263 1480.0 */ 1034, +/* 4264 1480.1 */ 1046, +/* 4265 1481.0 */ 1047, +/* 4266 1481.1 */ 1042, +/* 4267 1482.0 */ 785, +/* 4268 1482.1 */ 786, +/* 4269 1482.2 */ 797, +/* 4270 1482.3 */ 120, +/* 4271 1483.0 */ 785, +/* 4272 1483.1 */ 786, +/* 4273 1483.2 */ 253, +/* 4274 1483.3 */ 120, +/* 4275 1484.0 */ 908, +/* 4276 1484.1 */ 942, +/* 4277 1484.2 */ 861, +/* 4278 1484.3 */ 120, +/* 4279 1485.0 */ 908, +/* 4280 1485.1 */ 942, +/* 4281 1485.2 */ 860, +/* 4282 1485.3 */ 120, +/* 4283 1486.0 */ 246, +/* 4284 1486.1 */ 792, +/* 4285 1486.2 */ 794, +/* 4286 1487.0 */ 246, +/* 4287 1487.1 */ 792, +/* 4288 1487.2 */ 514, +/* 4289 1488.0 */ 1048, +/* 4290 1488.1 */ 927, +/* 4291 1488.2 */ 879, +/* 4292 1489.0 */ 1048, +/* 4293 1489.1 */ 927, +/* 4294 1489.2 */ 878, +/* 4295 1490.0 */ 1049, +/* 4296 1491.0 */ 1050, +/* 4297 1492.0 */ 1051, +/* 4298 1492.1 */ 1052, +/* 4299 1492.2 */ 1053, +/* 4300 1493.0 */ 1054, +/* 4301 1493.1 */ 1052, +/* 4302 1493.2 */ 1053, +/* 4303 1494.0 */ 1055, +/* 4304 1494.1 */ 1052, +/* 4305 1494.2 */ 1053, +/* 4306 1495.0 */ 1056, +/* 4307 1495.1 */ 1057, +/* 4308 1496.0 */ 1058, +/* 4309 1496.1 */ 1059, +/* 4310 1497.0 */ 1056, +/* 4311 1498.0 */ 1060, +/* 4312 1498.1 */ 1061, +/* 4313 1498.2 */ 1062, +/* 4314 1498.3 */ 1063, +/* 4315 1499.0 */ 1060, +/* 4316 1499.1 */ 1061, +/* 4317 1499.2 */ 1062, +/* 4318 1499.3 */ 1064, +/* 4319 1500.0 */ 1065, +/* 4320 1500.1 */ 1061, +/* 4321 1500.2 */ 1066, +/* 4322 1500.3 */ 1067, +/* 4323 1501.0 */ 1065, +/* 4324 1501.1 */ 1061, +/* 4325 1501.2 */ 1066, +/* 4326 1501.3 */ 1064, +/* 4327 1502.0 */ 1068, +/* 4328 1502.1 */ 1061, +/* 4329 1502.2 */ 1069, +/* 4330 1502.3 */ 1070, +/* 4331 1503.0 */ 1068, +/* 4332 1503.1 */ 1061, +/* 4333 1503.2 */ 1069, +/* 4334 1503.3 */ 1064, +/* 4335 1504.0 */ 1060, +/* 4336 1504.1 */ 1061, +/* 4337 1504.2 */ 1071, +/* 4338 1504.3 */ 1063, +/* 4339 1505.0 */ 1060, +/* 4340 1505.1 */ 1061, +/* 4341 1505.2 */ 1071, +/* 4342 1505.3 */ 1064, +/* 4343 1506.0 */ 1065, +/* 4344 1506.1 */ 1061, +/* 4345 1506.2 */ 1072, +/* 4346 1506.3 */ 1067, +/* 4347 1507.0 */ 1065, +/* 4348 1507.1 */ 1061, +/* 4349 1507.2 */ 1072, +/* 4350 1507.3 */ 1064, +/* 4351 1508.0 */ 1068, +/* 4352 1508.1 */ 1061, +/* 4353 1508.2 */ 1073, +/* 4354 1508.3 */ 1070, +/* 4355 1509.0 */ 1068, +/* 4356 1509.1 */ 1061, +/* 4357 1509.2 */ 1073, +/* 4358 1509.3 */ 1064, +/* 4359 1510.0 */ 1074, +/* 4360 1510.1 */ 1061, +/* 4361 1510.2 */ 1075, +/* 4362 1510.3 */ 1076, +/* 4363 1511.0 */ 1074, +/* 4364 1511.1 */ 1061, +/* 4365 1511.2 */ 1075, +/* 4366 1511.3 */ 1077, +/* 4367 1512.0 */ 1078, +/* 4368 1512.1 */ 1061, +/* 4369 1512.2 */ 1079, +/* 4370 1512.3 */ 1080, +/* 4371 1513.0 */ 1078, +/* 4372 1513.1 */ 1061, +/* 4373 1513.2 */ 1079, +/* 4374 1513.3 */ 1077, +/* 4375 1514.0 */ 1081, +/* 4376 1514.1 */ 1061, +/* 4377 1514.2 */ 1082, +/* 4378 1514.3 */ 1083, +/* 4379 1515.0 */ 1081, +/* 4380 1515.1 */ 1061, +/* 4381 1515.2 */ 1082, +/* 4382 1515.3 */ 1077, +/* 4383 1516.0 */ 1074, +/* 4384 1516.1 */ 1061, +/* 4385 1516.2 */ 1084, +/* 4386 1517.0 */ 1074, +/* 4387 1517.1 */ 1061, +/* 4388 1517.2 */ 1077, +/* 4389 1518.0 */ 1074, +/* 4390 1518.1 */ 1061, +/* 4391 1518.2 */ 1085, +/* 4392 1519.0 */ 1078, +/* 4393 1519.1 */ 1061, +/* 4394 1519.2 */ 1086, +/* 4395 1520.0 */ 1078, +/* 4396 1520.1 */ 1061, +/* 4397 1520.2 */ 1077, +/* 4398 1521.0 */ 1087, +/* 4399 1521.1 */ 1061, +/* 4400 1521.2 */ 1088, +/* 4401 1521.3 */ 1063, +/* 4402 1522.0 */ 1087, +/* 4403 1522.1 */ 1061, +/* 4404 1522.2 */ 1088, +/* 4405 1522.3 */ 1064, +/* 4406 1523.0 */ 1089, +/* 4407 1523.1 */ 1061, +/* 4408 1523.2 */ 1090, +/* 4409 1523.3 */ 1067, +/* 4410 1524.0 */ 1089, +/* 4411 1524.1 */ 1061, +/* 4412 1524.2 */ 1090, +/* 4413 1524.3 */ 1064, +/* 4414 1525.0 */ 1091, +/* 4415 1525.1 */ 1061, +/* 4416 1525.2 */ 1092, +/* 4417 1525.3 */ 1070, +/* 4418 1526.0 */ 1091, +/* 4419 1526.1 */ 1061, +/* 4420 1526.2 */ 1092, +/* 4421 1526.3 */ 1064, +/* 4422 1527.0 */ 1093, +/* 4423 1527.1 */ 1061, +/* 4424 1527.2 */ 1094, +/* 4425 1528.0 */ 1095, +/* 4426 1528.1 */ 1061, +/* 4427 1528.2 */ 1094, +/* 4428 1529.0 */ 1093, +/* 4429 1529.1 */ 1061, +/* 4430 1529.2 */ 1096, +/* 4431 1530.0 */ 1097, +/* 4432 1530.1 */ 1061, +/* 4433 1530.2 */ 1086, +/* 4434 1531.0 */ 1098, +/* 4435 1531.1 */ 1061, +/* 4436 1531.2 */ 1086, +/* 4437 1532.0 */ 1097, +/* 4438 1532.1 */ 1061, +/* 4439 1532.2 */ 1077, +/* 4440 1533.0 */ 812, +/* 4441 1533.1 */ 1099, +/* 4442 1534.0 */ 810, +/* 4443 1534.1 */ 1099, +/* 4444 1535.0 */ 1100, +/* 4445 1535.1 */ 1061, +/* 4446 1535.2 */ 1101, +/* 4447 1535.3 */ 1102, +/* 4448 1536.0 */ 1103, +/* 4449 1536.1 */ 1061, +/* 4450 1536.2 */ 1101, +/* 4451 1536.3 */ 1102, +/* 4452 1537.0 */ 1100, +/* 4453 1537.1 */ 1061, +/* 4454 1537.2 */ 1101, +/* 4455 1537.3 */ 812, +/* 4456 1538.0 */ 1104, +/* 4457 1538.1 */ 1061, +/* 4458 1538.2 */ 1075, +/* 4459 1538.3 */ 1076, +/* 4460 1539.0 */ 1105, +/* 4461 1539.1 */ 1061, +/* 4462 1539.2 */ 1075, +/* 4463 1539.3 */ 1076, +/* 4464 1540.0 */ 1104, +/* 4465 1540.1 */ 1061, +/* 4466 1540.2 */ 1075, +/* 4467 1540.3 */ 810, +/* 4468 1541.0 */ 1091, +/* 4469 1541.1 */ 1061, +/* 4470 1541.2 */ 1106, +/* 4471 1541.3 */ 587, +/* 4472 1542.0 */ 1087, +/* 4473 1542.1 */ 1061, +/* 4474 1542.2 */ 1107, +/* 4475 1542.3 */ 587, +/* 4476 1543.0 */ 1068, +/* 4477 1543.1 */ 1061, +/* 4478 1543.2 */ 1108, +/* 4479 1543.3 */ 514, +/* 4480 1544.0 */ 1109, +/* 4481 1544.1 */ 1061, +/* 4482 1544.2 */ 1110, +/* 4483 1545.0 */ 1109, +/* 4484 1545.1 */ 1061, +/* 4485 1545.2 */ 1064, +/* 4486 1546.0 */ 1111, +/* 4487 1546.1 */ 1061, +/* 4488 1546.2 */ 1112, +/* 4489 1547.0 */ 1111, +/* 4490 1547.1 */ 1061, +/* 4491 1547.2 */ 1064, +/* 4492 1548.0 */ 1113, +/* 4493 1548.1 */ 1061, +/* 4494 1548.2 */ 1114, +/* 4495 1549.0 */ 1113, +/* 4496 1549.1 */ 1061, +/* 4497 1549.2 */ 1064, +/* 4498 1550.0 */ 1115, +/* 4499 1550.1 */ 1061, +/* 4500 1550.2 */ 1116, +/* 4501 1551.0 */ 1115, +/* 4502 1551.1 */ 1061, +/* 4503 1551.2 */ 1117, +/* 4504 1552.0 */ 1118, +/* 4505 1552.1 */ 1061, +/* 4506 1552.2 */ 1119, +/* 4507 1553.0 */ 1118, +/* 4508 1553.1 */ 1061, +/* 4509 1553.2 */ 1117, +/* 4510 1554.0 */ 1120, +/* 4511 1554.1 */ 1061, +/* 4512 1554.2 */ 1121, +/* 4513 1555.0 */ 1120, +/* 4514 1555.1 */ 1061, +/* 4515 1555.2 */ 1117, +/* 4516 1556.0 */ 1093, +/* 4517 1556.1 */ 1061, +/* 4518 1556.2 */ 1122, +/* 4519 1556.3 */ 1123, +/* 4520 1557.0 */ 1124, +/* 4521 1557.1 */ 1061, +/* 4522 1557.2 */ 1122, +/* 4523 1557.3 */ 1123, +/* 4524 1558.0 */ 1093, +/* 4525 1558.1 */ 1061, +/* 4526 1558.2 */ 1122, +/* 4527 1558.3 */ 1096, +/* 4528 1559.0 */ 1100, +/* 4529 1559.1 */ 1061, +/* 4530 1559.2 */ 1101, +/* 4531 1559.3 */ 1096, +/* 4532 1560.0 */ 1125, +/* 4533 1560.1 */ 1061, +/* 4534 1560.2 */ 1126, +/* 4535 1560.3 */ 1127, +/* 4536 1561.0 */ 1125, +/* 4537 1561.1 */ 1061, +/* 4538 1561.2 */ 1126, +/* 4539 1561.3 */ 1096, +/* 4540 1562.0 */ 1097, +/* 4541 1562.1 */ 1061, +/* 4542 1562.2 */ 1082, +/* 4543 1562.3 */ 1083, +/* 4544 1563.0 */ 1128, +/* 4545 1563.1 */ 1061, +/* 4546 1563.2 */ 1082, +/* 4547 1563.3 */ 1083, +/* 4548 1564.0 */ 1097, +/* 4549 1564.1 */ 1061, +/* 4550 1564.2 */ 1082, +/* 4551 1564.3 */ 1077, +/* 4552 1565.0 */ 1104, +/* 4553 1565.1 */ 1061, +/* 4554 1565.2 */ 1075, +/* 4555 1565.3 */ 1077, +/* 4556 1566.0 */ 1129, +/* 4557 1566.1 */ 1061, +/* 4558 1566.2 */ 1079, +/* 4559 1566.3 */ 1080, +/* 4560 1567.0 */ 1129, +/* 4561 1567.1 */ 1061, +/* 4562 1567.2 */ 1079, +/* 4563 1567.3 */ 1077, +/* 4564 1568.0 */ 1130, +/* 4565 1568.1 */ 1061, +/* 4566 1568.2 */ 1101, +/* 4567 1568.3 */ 1102, +/* 4568 1569.0 */ 1131, +/* 4569 1569.1 */ 1061, +/* 4570 1569.2 */ 1075, +/* 4571 1569.3 */ 1076, +/* 4572 1570.0 */ 1109, +/* 4573 1570.1 */ 1061, +/* 4574 1570.2 */ 1092, +/* 4575 1570.3 */ 1070, +/* 4576 1570.4 */ 120, +/* 4577 1571.0 */ 1109, +/* 4578 1571.1 */ 1061, +/* 4579 1571.2 */ 1092, +/* 4580 1571.3 */ 1064, +/* 4581 1571.4 */ 120, +/* 4582 1572.0 */ 1111, +/* 4583 1572.1 */ 1061, +/* 4584 1572.2 */ 1088, +/* 4585 1572.3 */ 1063, +/* 4586 1572.4 */ 120, +/* 4587 1573.0 */ 1111, +/* 4588 1573.1 */ 1061, +/* 4589 1573.2 */ 1088, +/* 4590 1573.3 */ 1064, +/* 4591 1573.4 */ 120, +/* 4592 1574.0 */ 1113, +/* 4593 1574.1 */ 1061, +/* 4594 1574.2 */ 1090, +/* 4595 1574.3 */ 1067, +/* 4596 1574.4 */ 120, +/* 4597 1575.0 */ 1113, +/* 4598 1575.1 */ 1061, +/* 4599 1575.2 */ 1090, +/* 4600 1575.3 */ 1064, +/* 4601 1575.4 */ 120, +/* 4602 1576.0 */ 1115, +/* 4603 1576.1 */ 1061, +/* 4604 1576.2 */ 1132, +/* 4605 1576.3 */ 1133, +/* 4606 1576.4 */ 120, +/* 4607 1577.0 */ 1115, +/* 4608 1577.1 */ 1061, +/* 4609 1577.2 */ 1132, +/* 4610 1577.3 */ 1117, +/* 4611 1577.4 */ 120, +/* 4612 1578.0 */ 1118, +/* 4613 1578.1 */ 1061, +/* 4614 1578.2 */ 1134, +/* 4615 1578.3 */ 1135, +/* 4616 1578.4 */ 120, +/* 4617 1579.0 */ 1118, +/* 4618 1579.1 */ 1061, +/* 4619 1579.2 */ 1134, +/* 4620 1579.3 */ 1117, +/* 4621 1579.4 */ 120, +/* 4622 1580.0 */ 1120, +/* 4623 1580.1 */ 1061, +/* 4624 1580.2 */ 1136, +/* 4625 1580.3 */ 1137, +/* 4626 1580.4 */ 120, +/* 4627 1581.0 */ 1120, +/* 4628 1581.1 */ 1061, +/* 4629 1581.2 */ 1136, +/* 4630 1581.3 */ 1117, +/* 4631 1581.4 */ 120, +/* 4632 1582.0 */ 1097, +/* 4633 1582.1 */ 1061, +/* 4634 1582.2 */ 587, +/* 4635 1583.0 */ 1129, +/* 4636 1583.1 */ 1061, +/* 4637 1583.2 */ 587, +/* 4638 1584.0 */ 1093, +/* 4639 1584.1 */ 1061, +/* 4640 1584.2 */ 808, +/* 4641 1585.0 */ 1109, +/* 4642 1585.1 */ 1061, +/* 4643 1585.2 */ 514, +/* 4644 1586.0 */ 1113, +/* 4645 1586.1 */ 1061, +/* 4646 1586.2 */ 514, +/* 4647 1587.0 */ 1115, +/* 4648 1587.1 */ 1061, +/* 4649 1587.2 */ 860, +/* 4650 1588.0 */ 1093, +/* 4651 1588.1 */ 1061, +/* 4652 1588.2 */ 812, +/* 4653 1589.0 */ 1093, +/* 4654 1589.1 */ 1061, +/* 4655 1589.2 */ 1138, +/* 4656 1590.0 */ 1125, +/* 4657 1590.1 */ 1061, +/* 4658 1590.2 */ 812, +/* 4659 1591.0 */ 1125, +/* 4660 1591.1 */ 1061, +/* 4661 1591.2 */ 1138, +/* 4662 1592.0 */ 1097, +/* 4663 1592.1 */ 1061, +/* 4664 1592.2 */ 810, +/* 4665 1593.0 */ 1097, +/* 4666 1593.1 */ 1061, +/* 4667 1593.2 */ 1084, +/* 4668 1594.0 */ 1104, +/* 4669 1594.1 */ 1061, +/* 4670 1594.2 */ 810, +/* 4671 1595.0 */ 1104, +/* 4672 1595.1 */ 1061, +/* 4673 1595.2 */ 1084, +/* 4674 1596.0 */ 1129, +/* 4675 1596.1 */ 1061, +/* 4676 1596.2 */ 810, +/* 4677 1597.0 */ 1129, +/* 4678 1597.1 */ 1061, +/* 4679 1597.2 */ 1084, +/* 4680 1598.0 */ 1034, +/* 4681 1598.1 */ 1139, +/* 4682 1598.2 */ 1122, +/* 4683 1598.3 */ 1123, +/* 4684 1598.4 */ 120, +/* 4685 1599.0 */ 1140, +/* 4686 1599.1 */ 1139, +/* 4687 1599.2 */ 1122, +/* 4688 1599.3 */ 1123, +/* 4689 1599.4 */ 120, +/* 4690 1600.0 */ 1034, +/* 4691 1600.1 */ 1139, +/* 4692 1600.2 */ 1122, +/* 4693 1600.3 */ 1096, +/* 4694 1600.4 */ 120, +/* 4695 1601.0 */ 1034, +/* 4696 1601.1 */ 1139, +/* 4697 1601.2 */ 1101, +/* 4698 1601.3 */ 1102, +/* 4699 1601.4 */ 120, +/* 4700 1602.0 */ 1034, +/* 4701 1602.1 */ 1139, +/* 4702 1602.2 */ 1101, +/* 4703 1602.3 */ 1096, +/* 4704 1602.4 */ 120, +/* 4705 1603.0 */ 1034, +/* 4706 1603.1 */ 1139, +/* 4707 1603.2 */ 1126, +/* 4708 1603.3 */ 1127, +/* 4709 1603.4 */ 120, +/* 4710 1604.0 */ 1034, +/* 4711 1604.1 */ 1139, +/* 4712 1604.2 */ 1126, +/* 4713 1604.3 */ 1096, +/* 4714 1604.4 */ 120, +/* 4715 1605.0 */ 1034, +/* 4716 1605.1 */ 1139, +/* 4717 1605.2 */ 1082, +/* 4718 1605.3 */ 1083, +/* 4719 1605.4 */ 120, +/* 4720 1606.0 */ 1140, +/* 4721 1606.1 */ 1139, +/* 4722 1606.2 */ 1082, +/* 4723 1606.3 */ 1083, +/* 4724 1606.4 */ 120, +/* 4725 1607.0 */ 1034, +/* 4726 1607.1 */ 1139, +/* 4727 1607.2 */ 1082, +/* 4728 1607.3 */ 1077, +/* 4729 1607.4 */ 120, +/* 4730 1608.0 */ 1034, +/* 4731 1608.1 */ 1139, +/* 4732 1608.2 */ 1075, +/* 4733 1608.3 */ 1076, +/* 4734 1608.4 */ 120, +/* 4735 1609.0 */ 1034, +/* 4736 1609.1 */ 1139, +/* 4737 1609.2 */ 1075, +/* 4738 1609.3 */ 1077, +/* 4739 1609.4 */ 120, +/* 4740 1610.0 */ 1034, +/* 4741 1610.1 */ 1139, +/* 4742 1610.2 */ 1079, +/* 4743 1610.3 */ 1080, +/* 4744 1610.4 */ 120, +/* 4745 1611.0 */ 1034, +/* 4746 1611.1 */ 1139, +/* 4747 1611.2 */ 1079, +/* 4748 1611.3 */ 1077, +/* 4749 1611.4 */ 120, +/* 4750 1612.0 */ 1140, +/* 4751 1612.1 */ 1139, +/* 4752 1612.2 */ 1101, +/* 4753 1612.3 */ 1102, +/* 4754 1612.4 */ 120, +/* 4755 1613.0 */ 1034, +/* 4756 1613.1 */ 1139, +/* 4757 1613.2 */ 1101, +/* 4758 1613.3 */ 812, +/* 4759 1613.4 */ 120, +/* 4760 1614.0 */ 1140, +/* 4761 1614.1 */ 1139, +/* 4762 1614.2 */ 1075, +/* 4763 1614.3 */ 1076, +/* 4764 1614.4 */ 120, +/* 4765 1615.0 */ 1034, +/* 4766 1615.1 */ 1139, +/* 4767 1615.2 */ 1075, +/* 4768 1615.3 */ 810, +/* 4769 1615.4 */ 120, +/* 4770 1616.0 */ 1141, +/* 4771 1616.1 */ 1142, +/* 4772 1616.2 */ 123, +/* 4773 1617.0 */ 1143, +/* 4774 1617.1 */ 1142, +/* 4775 1617.2 */ 123, +/* 4776 1618.0 */ 1141, +/* 4777 1618.1 */ 812, +/* 4778 1618.2 */ 117, +/* 4779 1619.0 */ 1144, +/* 4780 1619.1 */ 1145, +/* 4781 1619.2 */ 123, +/* 4782 1620.0 */ 1146, +/* 4783 1620.1 */ 1145, +/* 4784 1620.2 */ 123, +/* 4785 1621.0 */ 1144, +/* 4786 1621.1 */ 810, +/* 4787 1621.2 */ 117, +/* 4788 1622.0 */ 1147, +/* 4789 1622.1 */ 1148, +/* 4790 1622.2 */ 1149, +/* 4791 1623.0 */ 1150, +/* 4792 1623.1 */ 1061, +/* 4793 1623.2 */ 1151, +/* 4794 1624.0 */ 871, +/* 4795 1624.1 */ 1148, +/* 4796 1624.2 */ 1152, +/* 4797 1625.0 */ 1153, +/* 4798 1625.1 */ 1061, +/* 4799 1625.2 */ 1154, +/* 4800 1626.0 */ 887, +/* 4801 1626.1 */ 1148, +/* 4802 1626.2 */ 1155, +/* 4803 1627.0 */ 1156, +/* 4804 1627.1 */ 1061, +/* 4805 1627.2 */ 1157, +/* 4806 1628.0 */ 1158, +/* 4807 1628.1 */ 1148, +/* 4808 1628.2 */ 1159, +/* 4809 1629.0 */ 1160, +/* 4810 1629.1 */ 1061, +/* 4811 1629.2 */ 1161, +/* 4812 1630.0 */ 880, +/* 4813 1630.1 */ 1148, +/* 4814 1630.2 */ 1162, +/* 4815 1631.0 */ 1163, +/* 4816 1631.1 */ 1061, +/* 4817 1631.2 */ 1164, +/* 4818 1632.0 */ 882, +/* 4819 1632.1 */ 1148, +/* 4820 1632.2 */ 1165, +/* 4821 1633.0 */ 1166, +/* 4822 1633.1 */ 1061, +/* 4823 1633.2 */ 1167, +/* 4824 1634.0 */ 1093, +/* 4825 1634.1 */ 1061, +/* 4826 1634.2 */ 1168, +/* 4827 1635.0 */ 1093, +/* 4828 1635.1 */ 1061, +/* 4829 1635.2 */ 1169, +/* 4830 1636.0 */ 1100, +/* 4831 1636.1 */ 1061, +/* 4832 1636.2 */ 1170, +/* 4833 1637.0 */ 1100, +/* 4834 1637.1 */ 1061, +/* 4835 1637.2 */ 1169, +/* 4836 1638.0 */ 1125, +/* 4837 1638.1 */ 1061, +/* 4838 1638.2 */ 1170, +/* 4839 1639.0 */ 1125, +/* 4840 1639.1 */ 1061, +/* 4841 1639.2 */ 1169, +/* 4842 1640.0 */ 1097, +/* 4843 1640.1 */ 1061, +/* 4844 1640.2 */ 1171, +/* 4845 1641.0 */ 1128, +/* 4846 1641.1 */ 1061, +/* 4847 1641.2 */ 1171, +/* 4848 1642.0 */ 1097, +/* 4849 1642.1 */ 1061, +/* 4850 1642.2 */ 1169, +/* 4851 1643.0 */ 1104, +/* 4852 1643.1 */ 1061, +/* 4853 1643.2 */ 1170, +/* 4854 1644.0 */ 1104, +/* 4855 1644.1 */ 1061, +/* 4856 1644.2 */ 1169, +/* 4857 1645.0 */ 1129, +/* 4858 1645.1 */ 1061, +/* 4859 1645.2 */ 1168, +/* 4860 1646.0 */ 1129, +/* 4861 1646.1 */ 1061, +/* 4862 1646.2 */ 1169, +/* 4863 1647.0 */ 1172, +/* 4864 1647.1 */ 1061, +/* 4865 1647.2 */ 1094, +/* 4866 1648.0 */ 1173, +/* 4867 1648.1 */ 1061, +/* 4868 1648.2 */ 1094, +/* 4869 1649.0 */ 1172, +/* 4870 1649.1 */ 1061, +/* 4871 1649.2 */ 1096, +/* 4872 1650.0 */ 1174, +/* 4873 1650.1 */ 1061, +/* 4874 1650.2 */ 1138, +/* 4875 1651.0 */ 1174, +/* 4876 1651.1 */ 1061, +/* 4877 1651.2 */ 1096, +/* 4878 1652.0 */ 1174, +/* 4879 1652.1 */ 1061, +/* 4880 1652.2 */ 1175, +/* 4881 1653.0 */ 1129, +/* 4882 1653.1 */ 1061, +/* 4883 1653.2 */ 1094, +/* 4884 1654.0 */ 1176, +/* 4885 1654.1 */ 1061, +/* 4886 1654.2 */ 1094, +/* 4887 1655.0 */ 1129, +/* 4888 1655.1 */ 1061, +/* 4889 1655.2 */ 1096, +/* 4890 1656.0 */ 1104, +/* 4891 1656.1 */ 1061, +/* 4892 1656.2 */ 1138, +/* 4893 1657.0 */ 1104, +/* 4894 1657.1 */ 1061, +/* 4895 1657.2 */ 1096, +/* 4896 1658.0 */ 1104, +/* 4897 1658.1 */ 1061, +/* 4898 1658.2 */ 1175, +/* 4899 1659.0 */ 1113, +/* 4900 1659.1 */ 1061, +/* 4901 1659.2 */ 1094, +/* 4902 1660.0 */ 1177, +/* 4903 1660.1 */ 1061, +/* 4904 1660.2 */ 1094, +/* 4905 1661.0 */ 1113, +/* 4906 1661.1 */ 1061, +/* 4907 1661.2 */ 1096, +/* 4908 1662.0 */ 1111, +/* 4909 1662.1 */ 1061, +/* 4910 1662.2 */ 1138, +/* 4911 1663.0 */ 1111, +/* 4912 1663.1 */ 1061, +/* 4913 1663.2 */ 1096, +/* 4914 1664.0 */ 1111, +/* 4915 1664.1 */ 1061, +/* 4916 1664.2 */ 1175, +/* 4917 1665.0 */ 1097, +/* 4918 1665.1 */ 1061, +/* 4919 1665.2 */ 1178, +/* 4920 1666.0 */ 1098, +/* 4921 1666.1 */ 1061, +/* 4922 1666.2 */ 1178, +/* 4923 1667.0 */ 1097, +/* 4924 1667.1 */ 1061, +/* 4925 1667.2 */ 1179, +/* 4926 1668.0 */ 1104, +/* 4927 1668.1 */ 1061, +/* 4928 1668.2 */ 1180, +/* 4929 1669.0 */ 1104, +/* 4930 1669.1 */ 1061, +/* 4931 1669.2 */ 984, +/* 4932 1670.0 */ 1129, +/* 4933 1670.1 */ 1061, +/* 4934 1670.2 */ 1180, +/* 4935 1671.0 */ 1129, +/* 4936 1671.1 */ 1061, +/* 4937 1671.2 */ 986, +/* 4938 1672.0 */ 1181, +/* 4939 1672.1 */ 1061, +/* 4940 1672.2 */ 1086, +/* 4941 1673.0 */ 1182, +/* 4942 1673.1 */ 1061, +/* 4943 1673.2 */ 1086, +/* 4944 1674.0 */ 1181, +/* 4945 1674.1 */ 1061, +/* 4946 1674.2 */ 1077, +/* 4947 1675.0 */ 1174, +/* 4948 1675.1 */ 1061, +/* 4949 1675.2 */ 1084, +/* 4950 1676.0 */ 1174, +/* 4951 1676.1 */ 1061, +/* 4952 1676.2 */ 1077, +/* 4953 1677.0 */ 1172, +/* 4954 1677.1 */ 1061, +/* 4955 1677.2 */ 1085, +/* 4956 1678.0 */ 1172, +/* 4957 1678.1 */ 1061, +/* 4958 1678.2 */ 1077, +/* 4959 1679.0 */ 1093, +/* 4960 1679.1 */ 1061, +/* 4961 1679.2 */ 1085, +/* 4962 1680.0 */ 1095, +/* 4963 1680.1 */ 1061, +/* 4964 1680.2 */ 1085, +/* 4965 1681.0 */ 1093, +/* 4966 1681.1 */ 1061, +/* 4967 1681.2 */ 1077, +/* 4968 1682.0 */ 1100, +/* 4969 1682.1 */ 1061, +/* 4970 1682.2 */ 1084, +/* 4971 1683.0 */ 1100, +/* 4972 1683.1 */ 1061, +/* 4973 1683.2 */ 1077, +/* 4974 1684.0 */ 1125, +/* 4975 1684.1 */ 1061, +/* 4976 1684.2 */ 1084, +/* 4977 1685.0 */ 1125, +/* 4978 1685.1 */ 1061, +/* 4979 1685.2 */ 1077, +/* 4980 1686.0 */ 1183, +/* 4981 1686.1 */ 1061, +/* 4982 1686.2 */ 1161, +/* 4983 1686.3 */ 120, +/* 4984 1687.0 */ 1184, +/* 4985 1687.1 */ 1061, +/* 4986 1687.2 */ 1161, +/* 4987 1687.3 */ 120, +/* 4988 1688.0 */ 1185, +/* 4989 1688.1 */ 1148, +/* 4990 1688.2 */ 1159, +/* 4991 1688.3 */ 120, +/* 4992 1689.0 */ 1186, +/* 4993 1689.1 */ 1061, +/* 4994 1689.2 */ 1164, +/* 4995 1689.3 */ 120, +/* 4996 1690.0 */ 988, +/* 4997 1690.1 */ 1148, +/* 4998 1690.2 */ 1162, +/* 4999 1690.3 */ 120, +/* 5000 1691.0 */ 1186, +/* 5001 1691.1 */ 1061, +/* 5002 1691.2 */ 1167, +/* 5003 1691.3 */ 120, +/* 5004 1692.0 */ 990, +/* 5005 1692.1 */ 1148, +/* 5006 1692.2 */ 1165, +/* 5007 1692.3 */ 120, +/* 5008 1693.0 */ 1109, +/* 5009 1693.1 */ 1061, +/* 5010 1693.2 */ 1086, +/* 5011 1694.0 */ 1187, +/* 5012 1694.1 */ 1061, +/* 5013 1694.2 */ 1086, +/* 5014 1695.0 */ 1109, +/* 5015 1695.1 */ 1061, +/* 5016 1695.2 */ 1077, +/* 5017 1696.0 */ 1111, +/* 5018 1696.1 */ 1061, +/* 5019 1696.2 */ 1084, +/* 5020 1697.0 */ 1111, +/* 5021 1697.1 */ 1061, +/* 5022 1697.2 */ 1077, +/* 5023 1698.0 */ 1113, +/* 5024 1698.1 */ 1061, +/* 5025 1698.2 */ 1085, +/* 5026 1699.0 */ 1113, +/* 5027 1699.1 */ 1061, +/* 5028 1699.2 */ 1077, +/* 5029 1700.0 */ 560, +/* 5030 1700.1 */ 1142, +/* 5031 1701.0 */ 1188, +/* 5032 1701.1 */ 1142, +/* 5033 1702.0 */ 561, +/* 5034 1702.1 */ 1142, +/* 5035 1703.0 */ 1189, +/* 5036 1703.1 */ 1142, +/* 5037 1704.0 */ 1104, +/* 5038 1704.1 */ 1061, +/* 5039 1704.2 */ 1101, +/* 5040 1704.3 */ 1102, +/* 5041 1705.0 */ 1131, +/* 5042 1705.1 */ 1061, +/* 5043 1705.2 */ 1101, +/* 5044 1705.3 */ 1102, +/* 5045 1706.0 */ 1104, +/* 5046 1706.1 */ 1061, +/* 5047 1706.2 */ 1101, +/* 5048 1706.3 */ 812, +/* 5049 1707.0 */ 955, +/* 5050 1707.1 */ 1142, +/* 5051 1708.0 */ 1190, +/* 5052 1708.1 */ 1142, +/* 5053 1709.0 */ 955, +/* 5054 1709.1 */ 812, +/* 5055 1710.0 */ 1047, +/* 5056 1710.1 */ 1142, +/* 5057 1711.0 */ 1191, +/* 5058 1711.1 */ 1142, +/* 5059 1712.0 */ 1047, +/* 5060 1712.1 */ 812, +/* 5061 1713.0 */ 1100, +/* 5062 1713.1 */ 1192, +/* 5063 1713.2 */ 869, +/* 5064 1714.0 */ 1100, +/* 5065 1714.1 */ 1192, +/* 5066 1714.2 */ 269, +/* 5067 1715.0 */ 1100, +/* 5068 1715.1 */ 1192, +/* 5069 1715.2 */ 870, +/* 5070 1716.0 */ 1130, +/* 5071 1716.1 */ 1192, +/* 5072 1716.2 */ 870, +/* 5073 1717.0 */ 1100, +/* 5074 1717.1 */ 1192, +/* 5075 1717.2 */ 219, +/* 5076 1718.0 */ 1104, +/* 5077 1718.1 */ 1193, +/* 5078 1718.2 */ 869, +/* 5079 1719.0 */ 1131, +/* 5080 1719.1 */ 1193, +/* 5081 1719.2 */ 869, +/* 5082 1720.0 */ 1104, +/* 5083 1720.1 */ 1193, +/* 5084 1720.2 */ 269, +/* 5085 1721.0 */ 1104, +/* 5086 1721.1 */ 1193, +/* 5087 1721.2 */ 870, +/* 5088 1722.0 */ 1131, +/* 5089 1722.1 */ 1193, +/* 5090 1722.2 */ 870, +/* 5091 1723.0 */ 1104, +/* 5092 1723.1 */ 1193, +/* 5093 1723.2 */ 219, +/* 5094 1724.0 */ 1100, +/* 5095 1724.1 */ 1061, +/* 5096 1724.2 */ 1075, +/* 5097 1724.3 */ 1076, +/* 5098 1725.0 */ 1103, +/* 5099 1725.1 */ 1061, +/* 5100 1725.2 */ 1075, +/* 5101 1725.3 */ 1076, +/* 5102 1726.0 */ 1100, +/* 5103 1726.1 */ 1061, +/* 5104 1726.2 */ 1075, +/* 5105 1726.3 */ 810, +/* 5106 1727.0 */ 560, +/* 5107 1727.1 */ 1145, +/* 5108 1728.0 */ 1188, +/* 5109 1728.1 */ 1145, +/* 5110 1729.0 */ 561, +/* 5111 1729.1 */ 1145, +/* 5112 1730.0 */ 1189, +/* 5113 1730.1 */ 1145, +/* 5114 1731.0 */ 955, +/* 5115 1731.1 */ 1145, +/* 5116 1732.0 */ 1190, +/* 5117 1732.1 */ 1145, +/* 5118 1733.0 */ 955, +/* 5119 1733.1 */ 810, +/* 5120 1734.0 */ 1047, +/* 5121 1734.1 */ 1145, +/* 5122 1735.0 */ 1191, +/* 5123 1735.1 */ 1145, +/* 5124 1736.0 */ 1047, +/* 5125 1736.1 */ 810, +/* 5126 1737.0 */ 1194, +/* 5127 1737.1 */ 1061, +/* 5128 1737.2 */ 1094, +/* 5129 1738.0 */ 1195, +/* 5130 1738.1 */ 1061, +/* 5131 1738.2 */ 1094, +/* 5132 1739.0 */ 1196, +/* 5133 1739.1 */ 1061, +/* 5134 1739.2 */ 1086, +/* 5135 1740.0 */ 1197, +/* 5136 1740.1 */ 1061, +/* 5137 1740.2 */ 1086, +/* 5138 1741.0 */ 1198, +/* 5139 1741.1 */ 1142, +/* 5140 1742.0 */ 1199, +/* 5141 1742.1 */ 1142, +/* 5142 1743.0 */ 1200, +/* 5143 1743.1 */ 1142, +/* 5144 1744.0 */ 1201, +/* 5145 1744.1 */ 1142, +/* 5146 1745.0 */ 1198, +/* 5147 1745.1 */ 1145, +/* 5148 1746.0 */ 1199, +/* 5149 1746.1 */ 1145, +/* 5150 1747.0 */ 1200, +/* 5151 1747.1 */ 1145, +/* 5152 1748.0 */ 1201, +/* 5153 1748.1 */ 1145, +/* 5154 1749.0 */ 1093, +/* 5155 1749.1 */ 1061, +/* 5156 1749.2 */ 1114, +/* 5157 1750.0 */ 1093, +/* 5158 1750.1 */ 1061, +/* 5159 1750.2 */ 1064, +/* 5160 1751.0 */ 1100, +/* 5161 1751.1 */ 1061, +/* 5162 1751.2 */ 1112, +/* 5163 1752.0 */ 1100, +/* 5164 1752.1 */ 1061, +/* 5165 1752.2 */ 1064, +/* 5166 1753.0 */ 1125, +/* 5167 1753.1 */ 1061, +/* 5168 1753.2 */ 1112, +/* 5169 1754.0 */ 1125, +/* 5170 1754.1 */ 1061, +/* 5171 1754.2 */ 1064, +/* 5172 1755.0 */ 1097, +/* 5173 1755.1 */ 1061, +/* 5174 1755.2 */ 1110, +/* 5175 1756.0 */ 1128, +/* 5176 1756.1 */ 1061, +/* 5177 1756.2 */ 1110, +/* 5178 1757.0 */ 1097, +/* 5179 1757.1 */ 1061, +/* 5180 1757.2 */ 1064, +/* 5181 1758.0 */ 1104, +/* 5182 1758.1 */ 1061, +/* 5183 1758.2 */ 1112, +/* 5184 1759.0 */ 1104, +/* 5185 1759.1 */ 1061, +/* 5186 1759.2 */ 1064, +/* 5187 1760.0 */ 1129, +/* 5188 1760.1 */ 1061, +/* 5189 1760.2 */ 1114, +/* 5190 1761.0 */ 1129, +/* 5191 1761.1 */ 1061, +/* 5192 1761.2 */ 1064, +/* 5193 1762.0 */ 1100, +/* 5194 1762.1 */ 1192, +/* 5195 1762.2 */ 965, +/* 5196 1763.0 */ 1100, +/* 5197 1763.1 */ 1192, +/* 5198 1763.2 */ 496, +/* 5199 1764.0 */ 1100, +/* 5200 1764.1 */ 1192, +/* 5201 1764.2 */ 966, +/* 5202 1765.0 */ 1130, +/* 5203 1765.1 */ 1192, +/* 5204 1765.2 */ 966, +/* 5205 1766.0 */ 1100, +/* 5206 1766.1 */ 1192, +/* 5207 1766.2 */ 538, +/* 5208 1767.0 */ 1104, +/* 5209 1767.1 */ 1193, +/* 5210 1767.2 */ 965, +/* 5211 1768.0 */ 1131, +/* 5212 1768.1 */ 1193, +/* 5213 1768.2 */ 965, +/* 5214 1769.0 */ 1104, +/* 5215 1769.1 */ 1193, +/* 5216 1769.2 */ 496, +/* 5217 1770.0 */ 1104, +/* 5218 1770.1 */ 1193, +/* 5219 1770.2 */ 966, +/* 5220 1771.0 */ 1131, +/* 5221 1771.1 */ 1193, +/* 5222 1771.2 */ 966, +/* 5223 1772.0 */ 1104, +/* 5224 1772.1 */ 1193, +/* 5225 1772.2 */ 538, +/* 5226 1773.0 */ 1093, +/* 5227 1773.1 */ 1061, +/* 5228 1773.2 */ 1202, +/* 5229 1774.0 */ 1100, +/* 5230 1774.1 */ 1061, +/* 5231 1774.2 */ 584, +/* 5232 1775.0 */ 1100, +/* 5233 1775.1 */ 1061, +/* 5234 1775.2 */ 1138, +/* 5235 1776.0 */ 1125, +/* 5236 1776.1 */ 1061, +/* 5237 1776.2 */ 808, +/* 5238 1777.0 */ 1125, +/* 5239 1777.1 */ 1061, +/* 5240 1777.2 */ 1175, +/* 5241 1778.0 */ 1097, +/* 5242 1778.1 */ 1061, +/* 5243 1778.2 */ 1203, +/* 5244 1779.0 */ 1104, +/* 5245 1779.1 */ 1061, +/* 5246 1779.2 */ 587, +/* 5247 1780.0 */ 1129, +/* 5248 1780.1 */ 1061, +/* 5249 1780.2 */ 805, +/* 5250 1781.0 */ 1129, +/* 5251 1781.1 */ 1061, +/* 5252 1781.2 */ 1085, +/* 5253 1782.0 */ 1163, +/* 5254 1782.1 */ 1061, +/* 5255 1782.2 */ 1161, +/* 5256 1782.3 */ 120, +/* 5257 1783.0 */ 880, +/* 5258 1783.1 */ 1148, +/* 5259 1783.2 */ 1159, +/* 5260 1783.3 */ 120, +/* 5261 1784.0 */ 1163, +/* 5262 1784.1 */ 1061, +/* 5263 1784.2 */ 1167, +/* 5264 1784.3 */ 120, +/* 5265 1785.0 */ 880, +/* 5266 1785.1 */ 1148, +/* 5267 1785.2 */ 1165, +/* 5268 1785.3 */ 120, +/* 5269 1786.0 */ 1156, +/* 5270 1786.1 */ 1061, +/* 5271 1786.2 */ 1151, +/* 5272 1786.3 */ 120, +/* 5273 1787.0 */ 887, +/* 5274 1787.1 */ 1148, +/* 5275 1787.2 */ 1149, +/* 5276 1787.3 */ 120, +/* 5277 1788.0 */ 1204, +/* 5278 1788.1 */ 1061, +/* 5279 1788.2 */ 1205, +/* 5280 1788.3 */ 120, +/* 5281 1789.0 */ 1013, +/* 5282 1789.1 */ 1148, +/* 5283 1789.2 */ 1206, +/* 5284 1789.3 */ 120, +/* 5285 1790.0 */ 1204, +/* 5286 1790.1 */ 1061, +/* 5287 1790.2 */ 1207, +/* 5288 1790.3 */ 120, +/* 5289 1791.0 */ 1013, +/* 5290 1791.1 */ 1148, +/* 5291 1791.2 */ 1208, +/* 5292 1791.3 */ 120, +/* 5293 1792.0 */ 1209, +/* 5294 1792.1 */ 1061, +/* 5295 1792.2 */ 1210, +/* 5296 1792.3 */ 120, +/* 5297 1793.0 */ 1018, +/* 5298 1793.1 */ 1148, +/* 5299 1793.2 */ 1211, +/* 5300 1793.3 */ 120, +/* 5301 1794.0 */ 1212, +/* 5302 1794.1 */ 1162, +/* 5303 1794.2 */ 120, +/* 5304 1795.0 */ 875, +/* 5305 1795.1 */ 1144, +/* 5306 1795.2 */ 120, +/* 5307 1796.0 */ 1213, +/* 5308 1796.1 */ 1061, +/* 5309 1796.2 */ 1122, +/* 5310 1796.3 */ 1123, +/* 5311 1796.4 */ 120, +/* 5312 1797.0 */ 1214, +/* 5313 1797.1 */ 1061, +/* 5314 1797.2 */ 1122, +/* 5315 1797.3 */ 1123, +/* 5316 1797.4 */ 120, +/* 5317 1798.0 */ 1213, +/* 5318 1798.1 */ 1061, +/* 5319 1798.2 */ 1122, +/* 5320 1798.3 */ 1096, +/* 5321 1798.4 */ 120, +/* 5322 1799.0 */ 1215, +/* 5323 1799.1 */ 1061, +/* 5324 1799.2 */ 1101, +/* 5325 1799.3 */ 1102, +/* 5326 1799.4 */ 120, +/* 5327 1800.0 */ 1215, +/* 5328 1800.1 */ 1061, +/* 5329 1800.2 */ 1101, +/* 5330 1800.3 */ 1096, +/* 5331 1800.4 */ 120, +/* 5332 1801.0 */ 1216, +/* 5333 1801.1 */ 1061, +/* 5334 1801.2 */ 1126, +/* 5335 1801.3 */ 1127, +/* 5336 1801.4 */ 120, +/* 5337 1802.0 */ 1216, +/* 5338 1802.1 */ 1061, +/* 5339 1802.2 */ 1126, +/* 5340 1802.3 */ 1096, +/* 5341 1802.4 */ 120, +/* 5342 1803.0 */ 1091, +/* 5343 1803.1 */ 1061, +/* 5344 1803.2 */ 1082, +/* 5345 1803.3 */ 1083, +/* 5346 1803.4 */ 120, +/* 5347 1804.0 */ 1217, +/* 5348 1804.1 */ 1061, +/* 5349 1804.2 */ 1082, +/* 5350 1804.3 */ 1083, +/* 5351 1804.4 */ 120, +/* 5352 1805.0 */ 1091, +/* 5353 1805.1 */ 1061, +/* 5354 1805.2 */ 1082, +/* 5355 1805.3 */ 1077, +/* 5356 1805.4 */ 120, +/* 5357 1806.0 */ 1087, +/* 5358 1806.1 */ 1061, +/* 5359 1806.2 */ 1075, +/* 5360 1806.3 */ 1076, +/* 5361 1806.4 */ 120, +/* 5362 1807.0 */ 1087, +/* 5363 1807.1 */ 1061, +/* 5364 1807.2 */ 1075, +/* 5365 1807.3 */ 1077, +/* 5366 1807.4 */ 120, +/* 5367 1808.0 */ 1089, +/* 5368 1808.1 */ 1061, +/* 5369 1808.2 */ 1079, +/* 5370 1808.3 */ 1080, +/* 5371 1808.4 */ 120, +/* 5372 1809.0 */ 1089, +/* 5373 1809.1 */ 1061, +/* 5374 1809.2 */ 1079, +/* 5375 1809.3 */ 1077, +/* 5376 1809.4 */ 120, +/* 5377 1810.0 */ 1218, +/* 5378 1810.1 */ 1061, +/* 5379 1810.2 */ 1101, +/* 5380 1810.3 */ 1102, +/* 5381 1810.4 */ 120, +/* 5382 1811.0 */ 1215, +/* 5383 1811.1 */ 1061, +/* 5384 1811.2 */ 1101, +/* 5385 1811.3 */ 812, +/* 5386 1811.4 */ 120, +/* 5387 1812.0 */ 1219, +/* 5388 1812.1 */ 1061, +/* 5389 1812.2 */ 1075, +/* 5390 1812.3 */ 1076, +/* 5391 1812.4 */ 120, +/* 5392 1813.0 */ 1087, +/* 5393 1813.1 */ 1061, +/* 5394 1813.2 */ 1075, +/* 5395 1813.3 */ 810, +/* 5396 1813.4 */ 120, +/* 5397 1814.0 */ 1213, +/* 5398 1814.1 */ 1061, +/* 5399 1814.2 */ 1122, +/* 5400 1814.3 */ 1123, +/* 5401 1815.0 */ 1220, +/* 5402 1815.1 */ 1061, +/* 5403 1815.2 */ 1122, +/* 5404 1815.3 */ 1123, +/* 5405 1816.0 */ 1213, +/* 5406 1816.1 */ 1061, +/* 5407 1816.2 */ 1122, +/* 5408 1816.3 */ 1096, +/* 5409 1817.0 */ 1215, +/* 5410 1817.1 */ 1061, +/* 5411 1817.2 */ 1101, +/* 5412 1817.3 */ 1102, +/* 5413 1818.0 */ 1215, +/* 5414 1818.1 */ 1061, +/* 5415 1818.2 */ 1101, +/* 5416 1818.3 */ 1096, +/* 5417 1819.0 */ 1216, +/* 5418 1819.1 */ 1061, +/* 5419 1819.2 */ 1126, +/* 5420 1819.3 */ 1127, +/* 5421 1820.0 */ 1216, +/* 5422 1820.1 */ 1061, +/* 5423 1820.2 */ 1126, +/* 5424 1820.3 */ 1096, +/* 5425 1821.0 */ 1091, +/* 5426 1821.1 */ 1061, +/* 5427 1821.2 */ 1082, +/* 5428 1821.3 */ 1083, +/* 5429 1822.0 */ 1221, +/* 5430 1822.1 */ 1061, +/* 5431 1822.2 */ 1082, +/* 5432 1822.3 */ 1083, +/* 5433 1823.0 */ 1091, +/* 5434 1823.1 */ 1061, +/* 5435 1823.2 */ 1082, +/* 5436 1823.3 */ 1077, +/* 5437 1824.0 */ 1087, +/* 5438 1824.1 */ 1061, +/* 5439 1824.2 */ 1075, +/* 5440 1824.3 */ 1076, +/* 5441 1825.0 */ 1087, +/* 5442 1825.1 */ 1061, +/* 5443 1825.2 */ 1075, +/* 5444 1825.3 */ 1077, +/* 5445 1826.0 */ 1089, +/* 5446 1826.1 */ 1061, +/* 5447 1826.2 */ 1079, +/* 5448 1826.3 */ 1080, +/* 5449 1827.0 */ 1089, +/* 5450 1827.1 */ 1061, +/* 5451 1827.2 */ 1079, +/* 5452 1827.3 */ 1077, +/* 5453 1828.0 */ 1222, +/* 5454 1828.1 */ 1061, +/* 5455 1828.2 */ 1101, +/* 5456 1828.3 */ 1102, +/* 5457 1829.0 */ 1215, +/* 5458 1829.1 */ 1061, +/* 5459 1829.2 */ 1101, +/* 5460 1829.3 */ 812, +/* 5461 1830.0 */ 1223, +/* 5462 1830.1 */ 1061, +/* 5463 1830.2 */ 1075, +/* 5464 1830.3 */ 1076, +/* 5465 1831.0 */ 1087, +/* 5466 1831.1 */ 1061, +/* 5467 1831.2 */ 1075, +/* 5468 1831.3 */ 810, +/* 5469 1832.0 */ 1093, +/* 5470 1832.1 */ 1224, +/* 5471 1832.2 */ 812, +/* 5472 1833.0 */ 1100, +/* 5473 1833.1 */ 1224, +/* 5474 1833.2 */ 812, +/* 5475 1834.0 */ 1125, +/* 5476 1834.1 */ 1224, +/* 5477 1834.2 */ 812, +/* 5478 1835.0 */ 1097, +/* 5479 1835.1 */ 1224, +/* 5480 1835.2 */ 810, +/* 5481 1836.0 */ 1104, +/* 5482 1836.1 */ 1224, +/* 5483 1836.2 */ 810, +/* 5484 1837.0 */ 1129, +/* 5485 1837.1 */ 1224, +/* 5486 1837.2 */ 810, +/* 5487 1838.0 */ 1100, +/* 5488 1838.1 */ 1061, +/* 5489 1838.2 */ 1096, +/* 5490 1839.0 */ 1125, +/* 5491 1839.1 */ 1061, +/* 5492 1839.2 */ 1096, +/* 5493 1840.0 */ 1104, +/* 5494 1840.1 */ 1061, +/* 5495 1840.2 */ 1077, +/* 5496 1841.0 */ 1129, +/* 5497 1841.1 */ 1061, +/* 5498 1841.2 */ 1077, +/* 5499 1842.0 */ 1093, +/* 5500 1842.1 */ 1061, +/* 5501 1842.2 */ 1094, +/* 5502 1842.3 */ 120, +/* 5503 1843.0 */ 1095, +/* 5504 1843.1 */ 1061, +/* 5505 1843.2 */ 1094, +/* 5506 1843.3 */ 120, +/* 5507 1844.0 */ 1093, +/* 5508 1844.1 */ 1061, +/* 5509 1844.2 */ 1096, +/* 5510 1844.3 */ 120, +/* 5511 1845.0 */ 1100, +/* 5512 1845.1 */ 1061, +/* 5513 1845.2 */ 1138, +/* 5514 1845.3 */ 120, +/* 5515 1846.0 */ 1100, +/* 5516 1846.1 */ 1061, +/* 5517 1846.2 */ 1096, +/* 5518 1846.3 */ 120, +/* 5519 1847.0 */ 1125, +/* 5520 1847.1 */ 1061, +/* 5521 1847.2 */ 1175, +/* 5522 1847.3 */ 120, +/* 5523 1848.0 */ 1125, +/* 5524 1848.1 */ 1061, +/* 5525 1848.2 */ 1096, +/* 5526 1848.3 */ 120, +/* 5527 1849.0 */ 1097, +/* 5528 1849.1 */ 1061, +/* 5529 1849.2 */ 1086, +/* 5530 1849.3 */ 120, +/* 5531 1850.0 */ 1098, +/* 5532 1850.1 */ 1061, +/* 5533 1850.2 */ 1086, +/* 5534 1850.3 */ 120, +/* 5535 1851.0 */ 1097, +/* 5536 1851.1 */ 1061, +/* 5537 1851.2 */ 1077, +/* 5538 1851.3 */ 120, +/* 5539 1852.0 */ 1104, +/* 5540 1852.1 */ 1061, +/* 5541 1852.2 */ 1084, +/* 5542 1852.3 */ 120, +/* 5543 1853.0 */ 1104, +/* 5544 1853.1 */ 1061, +/* 5545 1853.2 */ 1077, +/* 5546 1853.3 */ 120, +/* 5547 1854.0 */ 1129, +/* 5548 1854.1 */ 1061, +/* 5549 1854.2 */ 1085, +/* 5550 1854.3 */ 120, +/* 5551 1855.0 */ 1129, +/* 5552 1855.1 */ 1061, +/* 5553 1855.2 */ 1077, +/* 5554 1855.3 */ 120, +/* 5555 1856.0 */ 1100, +/* 5556 1856.1 */ 1061, +/* 5557 1856.2 */ 1101, +/* 5558 1856.3 */ 1102, +/* 5559 1856.4 */ 120, +/* 5560 1857.0 */ 1103, +/* 5561 1857.1 */ 1061, +/* 5562 1857.2 */ 1101, +/* 5563 1857.3 */ 1102, +/* 5564 1857.4 */ 120, +/* 5565 1858.0 */ 1100, +/* 5566 1858.1 */ 1061, +/* 5567 1858.2 */ 1101, +/* 5568 1858.3 */ 812, +/* 5569 1858.4 */ 120, +/* 5570 1859.0 */ 1104, +/* 5571 1859.1 */ 1061, +/* 5572 1859.2 */ 1075, +/* 5573 1859.3 */ 1076, +/* 5574 1859.4 */ 120, +/* 5575 1860.0 */ 1105, +/* 5576 1860.1 */ 1061, +/* 5577 1860.2 */ 1075, +/* 5578 1860.3 */ 1076, +/* 5579 1860.4 */ 120, +/* 5580 1861.0 */ 1104, +/* 5581 1861.1 */ 1061, +/* 5582 1861.2 */ 1075, +/* 5583 1861.3 */ 810, +/* 5584 1861.4 */ 120, +/* 5585 1862.0 */ 1097, +/* 5586 1862.1 */ 1061, +/* 5587 1862.2 */ 1082, +/* 5588 1862.3 */ 1076, +/* 5589 1862.4 */ 120, +/* 5590 1863.0 */ 1097, +/* 5591 1863.1 */ 1061, +/* 5592 1863.2 */ 1082, +/* 5593 1863.3 */ 587, +/* 5594 1863.4 */ 120, +/* 5595 1864.0 */ 1129, +/* 5596 1864.1 */ 1061, +/* 5597 1864.2 */ 1079, +/* 5598 1864.3 */ 1076, +/* 5599 1864.4 */ 120, +/* 5600 1865.0 */ 1129, +/* 5601 1865.1 */ 1061, +/* 5602 1865.2 */ 1079, +/* 5603 1865.3 */ 587, +/* 5604 1865.4 */ 120, +/* 5605 1866.0 */ 1093, +/* 5606 1866.1 */ 1061, +/* 5607 1866.2 */ 1122, +/* 5608 1866.3 */ 1127, +/* 5609 1866.4 */ 120, +/* 5610 1867.0 */ 1093, +/* 5611 1867.1 */ 1061, +/* 5612 1867.2 */ 1122, +/* 5613 1867.3 */ 808, +/* 5614 1867.4 */ 120, +/* 5615 1868.0 */ 1109, +/* 5616 1868.1 */ 1061, +/* 5617 1868.2 */ 1092, +/* 5618 1868.3 */ 1063, +/* 5619 1868.4 */ 120, +/* 5620 1869.0 */ 1109, +/* 5621 1869.1 */ 1061, +/* 5622 1869.2 */ 1092, +/* 5623 1869.3 */ 514, +/* 5624 1869.4 */ 120, +/* 5625 1870.0 */ 1113, +/* 5626 1870.1 */ 1061, +/* 5627 1870.2 */ 1090, +/* 5628 1870.3 */ 1063, +/* 5629 1870.4 */ 120, +/* 5630 1871.0 */ 1113, +/* 5631 1871.1 */ 1061, +/* 5632 1871.2 */ 1090, +/* 5633 1871.3 */ 514, +/* 5634 1871.4 */ 120, +/* 5635 1872.0 */ 1115, +/* 5636 1872.1 */ 1061, +/* 5637 1872.2 */ 1132, +/* 5638 1872.3 */ 1137, +/* 5639 1872.4 */ 120, +/* 5640 1873.0 */ 1115, +/* 5641 1873.1 */ 1061, +/* 5642 1873.2 */ 1132, +/* 5643 1873.3 */ 860, +/* 5644 1873.4 */ 120, +/* 5645 1874.0 */ 1104, +/* 5646 1874.1 */ 1193, +/* 5647 1874.2 */ 1084, +/* 5648 1874.3 */ 120, +/* 5649 1875.0 */ 1104, +/* 5650 1875.1 */ 1193, +/* 5651 1875.2 */ 810, +/* 5652 1875.3 */ 120, +/* 5653 1876.0 */ 1095, +/* 5654 1876.1 */ 1061, +/* 5655 1876.2 */ 1122, +/* 5656 1876.3 */ 1123, +/* 5657 1877.0 */ 1098, +/* 5658 1877.1 */ 1061, +/* 5659 1877.2 */ 1082, +/* 5660 1877.3 */ 1083, +/* 5661 1878.0 */ 1111, +/* 5662 1878.1 */ 1041, +/* 5663 1879.0 */ 1111, +/* 5664 1879.1 */ 496, +/* 5665 1880.0 */ 685, +/* 5666 1880.1 */ 1225, +/* 5667 1881.0 */ 690, +/* 5668 1881.1 */ 1226, +/* 5669 1882.0 */ 1100, +/* 5670 1882.1 */ 1061, +/* 5671 1882.2 */ 812, +/* 5672 1883.0 */ 1109, +/* 5673 1883.1 */ 1061, +/* 5674 1883.2 */ 709, +/* 5675 1884.0 */ 1227, +/* 5676 1884.1 */ 1061, +/* 5677 1884.2 */ 1205, +/* 5678 1885.0 */ 1228, +/* 5679 1885.1 */ 1148, +/* 5680 1885.2 */ 1206, +/* 5681 1886.0 */ 1111, +/* 5682 1886.1 */ 1061, +/* 5683 1886.2 */ 514, +/* 5684 1887.0 */ 1204, +/* 5685 1887.1 */ 1061, +/* 5686 1887.2 */ 1229, +/* 5687 1888.0 */ 1013, +/* 5688 1888.1 */ 1148, +/* 5689 1888.2 */ 1225, +/* 5690 1889.0 */ 1113, +/* 5691 1889.1 */ 1061, +/* 5692 1889.2 */ 878, +/* 5693 1890.0 */ 1230, +/* 5694 1890.1 */ 1061, +/* 5695 1890.2 */ 1207, +/* 5696 1891.0 */ 1015, +/* 5697 1891.1 */ 1148, +/* 5698 1891.2 */ 1208, +/* 5699 1892.0 */ 1115, +/* 5700 1892.1 */ 1061, +/* 5701 1892.2 */ 1231, +/* 5702 1893.0 */ 1232, +/* 5703 1893.1 */ 1061, +/* 5704 1893.2 */ 1210, +/* 5705 1894.0 */ 1233, +/* 5706 1894.1 */ 1148, +/* 5707 1894.2 */ 1211, +/* 5708 1895.0 */ 1118, +/* 5709 1895.1 */ 1061, +/* 5710 1895.2 */ 253, +/* 5711 1896.0 */ 1234, +/* 5712 1896.1 */ 1061, +/* 5713 1896.2 */ 1235, +/* 5714 1897.0 */ 676, +/* 5715 1897.1 */ 1148, +/* 5716 1897.2 */ 1236, +/* 5717 1898.0 */ 1120, +/* 5718 1898.1 */ 1061, +/* 5719 1898.2 */ 860, +/* 5720 1899.0 */ 1209, +/* 5721 1899.1 */ 1061, +/* 5722 1899.2 */ 1237, +/* 5723 1900.0 */ 1018, +/* 5724 1900.1 */ 1148, +/* 5725 1900.2 */ 1238, +/* 5726 1901.0 */ 1104, +/* 5727 1901.1 */ 1193, +/* 5728 1901.2 */ 1084, +/* 5729 1902.0 */ 1100, +/* 5730 1902.1 */ 1239, +/* 5731 1902.2 */ 812, +/* 5732 1903.0 */ 953, +/* 5733 1903.1 */ 1141, +/* 5734 1904.0 */ 1104, +/* 5735 1904.1 */ 1240, +/* 5736 1904.2 */ 292, +/* 5737 1905.0 */ 293, +/* 5738 1905.1 */ 1144, +/* 5739 1906.0 */ 1104, +/* 5740 1906.1 */ 1240, +/* 5741 1906.2 */ 1241, +/* 5742 1907.0 */ 1100, +/* 5743 1907.1 */ 1192, +/* 5744 1907.2 */ 812, +/* 5745 1908.0 */ 953, +/* 5746 1908.1 */ 1242, +/* 5747 1909.0 */ 1104, +/* 5748 1909.1 */ 1193, +/* 5749 1909.2 */ 292, +/* 5750 1910.0 */ 293, +/* 5751 1910.1 */ 1243, +/* 5752 1911.0 */ 1228, +/* 5753 1911.1 */ 1244, +/* 5754 1912.0 */ 1013, +/* 5755 1912.1 */ 1226, +/* 5756 1913.0 */ 1015, +/* 5757 1913.1 */ 1245, +/* 5758 1914.0 */ 1109, +/* 5759 1914.1 */ 709, +/* 5760 1915.0 */ 1111, +/* 5761 1915.1 */ 514, +/* 5762 1916.0 */ 1113, +/* 5763 1916.1 */ 878, +/* 5764 1917.0 */ 1147, +/* 5765 1917.1 */ 1246, +/* 5766 1918.0 */ 871, +/* 5767 1918.1 */ 1141, +/* 5768 1919.0 */ 887, +/* 5769 1919.1 */ 1247, +/* 5770 1920.0 */ 1158, +/* 5771 1920.1 */ 1248, +/* 5772 1921.0 */ 880, +/* 5773 1921.1 */ 1144, +/* 5774 1922.0 */ 882, +/* 5775 1922.1 */ 1249, +/* 5776 1923.0 */ 1118, +/* 5777 1923.1 */ 1046, +/* 5778 1924.0 */ 1118, +/* 5779 1924.1 */ 538, +/* 5780 1925.0 */ 687, +/* 5781 1925.1 */ 1236, +/* 5782 1926.0 */ 692, +/* 5783 1926.1 */ 1250, +/* 5784 1927.0 */ 1118, +/* 5785 1927.1 */ 1251, +/* 5786 1928.0 */ 1234, +/* 5787 1928.1 */ 1236, +/* 5788 1929.0 */ 953, +/* 5789 1929.1 */ 1148, +/* 5790 1929.2 */ 1152, +/* 5791 1930.0 */ 1153, +/* 5792 1930.1 */ 1061, +/* 5793 1930.2 */ 1101, +/* 5794 1930.3 */ 1252, +/* 5795 1931.0 */ 875, +/* 5796 1931.1 */ 1148, +/* 5797 1931.2 */ 1162, +/* 5798 1932.0 */ 1163, +/* 5799 1932.1 */ 1061, +/* 5800 1932.2 */ 1075, +/* 5801 1932.3 */ 1253, +/* 5802 1933.0 */ 1181, +/* 5803 1933.1 */ 1061, +/* 5804 1933.2 */ 1171, +/* 5805 1934.0 */ 1181, +/* 5806 1934.1 */ 1061, +/* 5807 1934.2 */ 1169, +/* 5808 1935.0 */ 1174, +/* 5809 1935.1 */ 1061, +/* 5810 1935.2 */ 1170, +/* 5811 1936.0 */ 1174, +/* 5812 1936.1 */ 1061, +/* 5813 1936.2 */ 1169, +/* 5814 1937.0 */ 1172, +/* 5815 1937.1 */ 1061, +/* 5816 1937.2 */ 1168, +/* 5817 1938.0 */ 1172, +/* 5818 1938.1 */ 1061, +/* 5819 1938.2 */ 1169, +/* 5820 1939.0 */ 1254, +/* 5821 1939.1 */ 1061, +/* 5822 1939.2 */ 1255, +/* 5823 1940.0 */ 1254, +/* 5824 1940.1 */ 1061, +/* 5825 1940.2 */ 1256, +/* 5826 1941.0 */ 1257, +/* 5827 1941.1 */ 1061, +/* 5828 1941.2 */ 1258, +/* 5829 1942.0 */ 1257, +/* 5830 1942.1 */ 1061, +/* 5831 1942.2 */ 1256, +/* 5832 1943.0 */ 1259, +/* 5833 1943.1 */ 1061, +/* 5834 1943.2 */ 1260, +/* 5835 1944.0 */ 1259, +/* 5836 1944.1 */ 1061, +/* 5837 1944.2 */ 1256, +/* 5838 1945.0 */ 1109, +/* 5839 1945.1 */ 1061, +/* 5840 1945.2 */ 1092, +/* 5841 1945.3 */ 1070, +/* 5842 1946.0 */ 1109, +/* 5843 1946.1 */ 1061, +/* 5844 1946.2 */ 1092, +/* 5845 1946.3 */ 1064, +/* 5846 1947.0 */ 1111, +/* 5847 1947.1 */ 1061, +/* 5848 1947.2 */ 1088, +/* 5849 1947.3 */ 1063, +/* 5850 1948.0 */ 1111, +/* 5851 1948.1 */ 1061, +/* 5852 1948.2 */ 1088, +/* 5853 1948.3 */ 1064, +/* 5854 1949.0 */ 1113, +/* 5855 1949.1 */ 1061, +/* 5856 1949.2 */ 1090, +/* 5857 1949.3 */ 1067, +/* 5858 1950.0 */ 1113, +/* 5859 1950.1 */ 1061, +/* 5860 1950.2 */ 1090, +/* 5861 1950.3 */ 1064, +/* 5862 1951.0 */ 1115, +/* 5863 1951.1 */ 1061, +/* 5864 1951.2 */ 1132, +/* 5865 1951.3 */ 1133, +/* 5866 1952.0 */ 1115, +/* 5867 1952.1 */ 1061, +/* 5868 1952.2 */ 1132, +/* 5869 1952.3 */ 1117, +/* 5870 1953.0 */ 1118, +/* 5871 1953.1 */ 1061, +/* 5872 1953.2 */ 1134, +/* 5873 1953.3 */ 1135, +/* 5874 1954.0 */ 1118, +/* 5875 1954.1 */ 1061, +/* 5876 1954.2 */ 1134, +/* 5877 1954.3 */ 1117, +/* 5878 1955.0 */ 1120, +/* 5879 1955.1 */ 1061, +/* 5880 1955.2 */ 1136, +/* 5881 1955.3 */ 1137, +/* 5882 1956.0 */ 1120, +/* 5883 1956.1 */ 1061, +/* 5884 1956.2 */ 1136, +/* 5885 1956.3 */ 1117, +/* 5886 1957.0 */ 1109, +/* 5887 1957.1 */ 1061, +/* 5888 1957.2 */ 496, +/* 5889 1958.0 */ 1109, +/* 5890 1958.1 */ 1061, +/* 5891 1958.2 */ 1112, +/* 5892 1959.0 */ 1109, +/* 5893 1959.1 */ 1061, +/* 5894 1959.2 */ 965, +/* 5895 1960.0 */ 1111, +/* 5896 1960.1 */ 1061, +/* 5897 1960.2 */ 496, +/* 5898 1961.0 */ 1111, +/* 5899 1961.1 */ 1061, +/* 5900 1961.2 */ 965, +/* 5901 1962.0 */ 1113, +/* 5902 1962.1 */ 1061, +/* 5903 1962.2 */ 496, +/* 5904 1963.0 */ 1113, +/* 5905 1963.1 */ 1061, +/* 5906 1963.2 */ 1112, +/* 5907 1964.0 */ 1113, +/* 5908 1964.1 */ 1061, +/* 5909 1964.2 */ 965, +/* 5910 1965.0 */ 1115, +/* 5911 1965.1 */ 1061, +/* 5912 1965.2 */ 538, +/* 5913 1966.0 */ 1115, +/* 5914 1966.1 */ 1061, +/* 5915 1966.2 */ 1119, +/* 5916 1967.0 */ 1115, +/* 5917 1967.1 */ 1061, +/* 5918 1967.2 */ 966, +/* 5919 1968.0 */ 1118, +/* 5920 1968.1 */ 1061, +/* 5921 1968.2 */ 538, +/* 5922 1969.0 */ 1118, +/* 5923 1969.1 */ 1061, +/* 5924 1969.2 */ 966, +/* 5925 1970.0 */ 1120, +/* 5926 1970.1 */ 1061, +/* 5927 1970.2 */ 538, +/* 5928 1971.0 */ 1120, +/* 5929 1971.1 */ 1061, +/* 5930 1971.2 */ 1119, +/* 5931 1972.0 */ 1120, +/* 5932 1972.1 */ 1061, +/* 5933 1972.2 */ 966, +/* 5934 1973.0 */ 1034, +/* 5935 1973.1 */ 1139, +/* 5936 1973.2 */ 1261, +/* 5937 1973.3 */ 1262, +/* 5938 1973.4 */ 120, +/* 5939 1974.0 */ 1034, +/* 5940 1974.1 */ 1139, +/* 5941 1974.2 */ 1261, +/* 5942 1974.3 */ 1169, +/* 5943 1974.4 */ 120, +/* 5944 1975.0 */ 1034, +/* 5945 1975.1 */ 1139, +/* 5946 1975.2 */ 1263, +/* 5947 1975.3 */ 1264, +/* 5948 1975.4 */ 120, +/* 5949 1976.0 */ 1034, +/* 5950 1976.1 */ 1139, +/* 5951 1976.2 */ 1263, +/* 5952 1976.3 */ 1169, +/* 5953 1976.4 */ 120, +/* 5954 1977.0 */ 1034, +/* 5955 1977.1 */ 1139, +/* 5956 1977.2 */ 1265, +/* 5957 1977.3 */ 1266, +/* 5958 1977.4 */ 120, +/* 5959 1978.0 */ 1034, +/* 5960 1978.1 */ 1139, +/* 5961 1978.2 */ 1265, +/* 5962 1978.3 */ 1169, +/* 5963 1978.4 */ 120, +/* 5964 1979.0 */ 1034, +/* 5965 1979.1 */ 1139, +/* 5966 1979.2 */ 1092, +/* 5967 1979.3 */ 1070, +/* 5968 1980.0 */ 1034, +/* 5969 1980.1 */ 1139, +/* 5970 1980.2 */ 1092, +/* 5971 1980.3 */ 1064, +/* 5972 1981.0 */ 1034, +/* 5973 1981.1 */ 1139, +/* 5974 1981.2 */ 1088, +/* 5975 1981.3 */ 1063, +/* 5976 1982.0 */ 1034, +/* 5977 1982.1 */ 1139, +/* 5978 1982.2 */ 1088, +/* 5979 1982.3 */ 1064, +/* 5980 1983.0 */ 1034, +/* 5981 1983.1 */ 1139, +/* 5982 1983.2 */ 1090, +/* 5983 1983.3 */ 1067, +/* 5984 1984.0 */ 1034, +/* 5985 1984.1 */ 1139, +/* 5986 1984.2 */ 1090, +/* 5987 1984.3 */ 1064, +/* 5988 1985.0 */ 1034, +/* 5989 1985.1 */ 1139, +/* 5990 1985.2 */ 1132, +/* 5991 1985.3 */ 1133, +/* 5992 1986.0 */ 1034, +/* 5993 1986.1 */ 1139, +/* 5994 1986.2 */ 1132, +/* 5995 1986.3 */ 1117, +/* 5996 1987.0 */ 1034, +/* 5997 1987.1 */ 1139, +/* 5998 1987.2 */ 1134, +/* 5999 1987.3 */ 1135, +/* 6000 1988.0 */ 1034, +/* 6001 1988.1 */ 1139, +/* 6002 1988.2 */ 1134, +/* 6003 1988.3 */ 1117, +/* 6004 1989.0 */ 1034, +/* 6005 1989.1 */ 1139, +/* 6006 1989.2 */ 1136, +/* 6007 1989.3 */ 1137, +/* 6008 1990.0 */ 1034, +/* 6009 1990.1 */ 1139, +/* 6010 1990.2 */ 1136, +/* 6011 1990.3 */ 1117, +/* 6012 1991.0 */ 1034, +/* 6013 1991.1 */ 1139, +/* 6014 1991.2 */ 1261, +/* 6015 1991.3 */ 1262, +/* 6016 1992.0 */ 1034, +/* 6017 1992.1 */ 1139, +/* 6018 1992.2 */ 1261, +/* 6019 1992.3 */ 1169, +/* 6020 1993.0 */ 1034, +/* 6021 1993.1 */ 1139, +/* 6022 1993.2 */ 1263, +/* 6023 1993.3 */ 1264, +/* 6024 1994.0 */ 1034, +/* 6025 1994.1 */ 1139, +/* 6026 1994.2 */ 1263, +/* 6027 1994.3 */ 1169, +/* 6028 1995.0 */ 1034, +/* 6029 1995.1 */ 1139, +/* 6030 1995.2 */ 1265, +/* 6031 1995.3 */ 1266, +/* 6032 1996.0 */ 1034, +/* 6033 1996.1 */ 1139, +/* 6034 1996.2 */ 1265, +/* 6035 1996.3 */ 1169, +/* 6036 1997.0 */ 1034, +/* 6037 1997.1 */ 1139, +/* 6038 1997.2 */ 1267, +/* 6039 1997.3 */ 1268, +/* 6040 1998.0 */ 1034, +/* 6041 1998.1 */ 1139, +/* 6042 1998.2 */ 1267, +/* 6043 1998.3 */ 1256, +/* 6044 1999.0 */ 1034, +/* 6045 1999.1 */ 1139, +/* 6046 1999.2 */ 1269, +/* 6047 1999.3 */ 1270, +/* 6048 2000.0 */ 1034, +/* 6049 2000.1 */ 1139, +/* 6050 2000.2 */ 1269, +/* 6051 2000.3 */ 1256, +/* 6052 2001.0 */ 1034, +/* 6053 2001.1 */ 1139, +/* 6054 2001.2 */ 1271, +/* 6055 2001.3 */ 1272, +/* 6056 2002.0 */ 1034, +/* 6057 2002.1 */ 1139, +/* 6058 2002.2 */ 1271, +/* 6059 2002.3 */ 1256, +/* 6060 2003.0 */ 1034, +/* 6061 2003.1 */ 1139, +/* 6062 2003.2 */ 1267, +/* 6063 2003.3 */ 1268, +/* 6064 2003.4 */ 120, +/* 6065 2004.0 */ 1034, +/* 6066 2004.1 */ 1139, +/* 6067 2004.2 */ 1267, +/* 6068 2004.3 */ 1256, +/* 6069 2004.4 */ 120, +/* 6070 2005.0 */ 1034, +/* 6071 2005.1 */ 1139, +/* 6072 2005.2 */ 1269, +/* 6073 2005.3 */ 1270, +/* 6074 2005.4 */ 120, +/* 6075 2006.0 */ 1034, +/* 6076 2006.1 */ 1139, +/* 6077 2006.2 */ 1269, +/* 6078 2006.3 */ 1256, +/* 6079 2006.4 */ 120, +/* 6080 2007.0 */ 1034, +/* 6081 2007.1 */ 1139, +/* 6082 2007.2 */ 1271, +/* 6083 2007.3 */ 1272, +/* 6084 2007.4 */ 120, +/* 6085 2008.0 */ 1034, +/* 6086 2008.1 */ 1139, +/* 6087 2008.2 */ 1271, +/* 6088 2008.3 */ 1256, +/* 6089 2008.4 */ 120, +/* 6090 2009.0 */ 1034, +/* 6091 2009.1 */ 1139, +/* 6092 2009.2 */ 1092, +/* 6093 2009.3 */ 1070, +/* 6094 2009.4 */ 120, +/* 6095 2010.0 */ 1034, +/* 6096 2010.1 */ 1139, +/* 6097 2010.2 */ 1092, +/* 6098 2010.3 */ 1064, +/* 6099 2010.4 */ 120, +/* 6100 2011.0 */ 1034, +/* 6101 2011.1 */ 1139, +/* 6102 2011.2 */ 1088, +/* 6103 2011.3 */ 1063, +/* 6104 2011.4 */ 120, +/* 6105 2012.0 */ 1034, +/* 6106 2012.1 */ 1139, +/* 6107 2012.2 */ 1088, +/* 6108 2012.3 */ 1064, +/* 6109 2012.4 */ 120, +/* 6110 2013.0 */ 1034, +/* 6111 2013.1 */ 1139, +/* 6112 2013.2 */ 1090, +/* 6113 2013.3 */ 1067, +/* 6114 2013.4 */ 120, +/* 6115 2014.0 */ 1034, +/* 6116 2014.1 */ 1139, +/* 6117 2014.2 */ 1090, +/* 6118 2014.3 */ 1064, +/* 6119 2014.4 */ 120, +/* 6120 2015.0 */ 1034, +/* 6121 2015.1 */ 1139, +/* 6122 2015.2 */ 1132, +/* 6123 2015.3 */ 1133, +/* 6124 2015.4 */ 120, +/* 6125 2016.0 */ 1034, +/* 6126 2016.1 */ 1139, +/* 6127 2016.2 */ 1132, +/* 6128 2016.3 */ 1117, +/* 6129 2016.4 */ 120, +/* 6130 2017.0 */ 1034, +/* 6131 2017.1 */ 1139, +/* 6132 2017.2 */ 1134, +/* 6133 2017.3 */ 1135, +/* 6134 2017.4 */ 120, +/* 6135 2018.0 */ 1034, +/* 6136 2018.1 */ 1139, +/* 6137 2018.2 */ 1134, +/* 6138 2018.3 */ 1117, +/* 6139 2018.4 */ 120, +/* 6140 2019.0 */ 1034, +/* 6141 2019.1 */ 1139, +/* 6142 2019.2 */ 1136, +/* 6143 2019.3 */ 1137, +/* 6144 2019.4 */ 120, +/* 6145 2020.0 */ 1034, +/* 6146 2020.1 */ 1139, +/* 6147 2020.2 */ 1136, +/* 6148 2020.3 */ 1117, +/* 6149 2020.4 */ 120, +/* 6150 2021.0 */ 1273, +/* 6151 2021.1 */ 1061, +/* 6152 2021.2 */ 1092, +/* 6153 2021.3 */ 1070, +/* 6154 2022.0 */ 1273, +/* 6155 2022.1 */ 1061, +/* 6156 2022.2 */ 1092, +/* 6157 2022.3 */ 1064, +/* 6158 2023.0 */ 1274, +/* 6159 2023.1 */ 1061, +/* 6160 2023.2 */ 1088, +/* 6161 2023.3 */ 1063, +/* 6162 2024.0 */ 1274, +/* 6163 2024.1 */ 1061, +/* 6164 2024.2 */ 1088, +/* 6165 2024.3 */ 1064, +/* 6166 2025.0 */ 1275, +/* 6167 2025.1 */ 1061, +/* 6168 2025.2 */ 1090, +/* 6169 2025.3 */ 1067, +/* 6170 2026.0 */ 1275, +/* 6171 2026.1 */ 1061, +/* 6172 2026.2 */ 1090, +/* 6173 2026.3 */ 1064, +/* 6174 2027.0 */ 1276, +/* 6175 2027.1 */ 1061, +/* 6176 2027.2 */ 1132, +/* 6177 2027.3 */ 1133, +/* 6178 2028.0 */ 1276, +/* 6179 2028.1 */ 1061, +/* 6180 2028.2 */ 1132, +/* 6181 2028.3 */ 1117, +/* 6182 2029.0 */ 1277, +/* 6183 2029.1 */ 1061, +/* 6184 2029.2 */ 1134, +/* 6185 2029.3 */ 1135, +/* 6186 2030.0 */ 1277, +/* 6187 2030.1 */ 1061, +/* 6188 2030.2 */ 1134, +/* 6189 2030.3 */ 1117, +/* 6190 2031.0 */ 1278, +/* 6191 2031.1 */ 1061, +/* 6192 2031.2 */ 1136, +/* 6193 2031.3 */ 1137, +/* 6194 2032.0 */ 1278, +/* 6195 2032.1 */ 1061, +/* 6196 2032.2 */ 1136, +/* 6197 2032.3 */ 1117, +/* 6198 2033.0 */ 1115, +/* 6199 2033.1 */ 1061, +/* 6200 2033.2 */ 1116, +/* 6201 2033.3 */ 120, +/* 6202 2034.0 */ 1115, +/* 6203 2034.1 */ 1061, +/* 6204 2034.2 */ 1117, +/* 6205 2034.3 */ 120, +/* 6206 2035.0 */ 1120, +/* 6207 2035.1 */ 1061, +/* 6208 2035.2 */ 1121, +/* 6209 2035.3 */ 120, +/* 6210 2036.0 */ 1120, +/* 6211 2036.1 */ 1061, +/* 6212 2036.2 */ 1117, +/* 6213 2036.3 */ 120, +/* 6214 2037.0 */ 1109, +/* 6215 2037.1 */ 1224, +/* 6216 2037.2 */ 496, +/* 6217 2038.0 */ 1111, +/* 6218 2038.1 */ 1224, +/* 6219 2038.2 */ 496, +/* 6220 2039.0 */ 1113, +/* 6221 2039.1 */ 1224, +/* 6222 2039.2 */ 496, +/* 6223 2040.0 */ 1115, +/* 6224 2040.1 */ 1224, +/* 6225 2040.2 */ 538, +/* 6226 2041.0 */ 1118, +/* 6227 2041.1 */ 1224, +/* 6228 2041.2 */ 538, +/* 6229 2042.0 */ 1120, +/* 6230 2042.1 */ 1224, +/* 6231 2042.2 */ 538, +/* 6232 2043.0 */ 1181, +/* 6233 2043.1 */ 1061, +/* 6234 2043.2 */ 1261, +/* 6235 2043.3 */ 1262, +/* 6236 2044.0 */ 1181, +/* 6237 2044.1 */ 1061, +/* 6238 2044.2 */ 1261, +/* 6239 2044.3 */ 1169, +/* 6240 2045.0 */ 1174, +/* 6241 2045.1 */ 1061, +/* 6242 2045.2 */ 1263, +/* 6243 2045.3 */ 1264, +/* 6244 2046.0 */ 1174, +/* 6245 2046.1 */ 1061, +/* 6246 2046.2 */ 1263, +/* 6247 2046.3 */ 1169, +/* 6248 2047.0 */ 1172, +/* 6249 2047.1 */ 1061, +/* 6250 2047.2 */ 1265, +/* 6251 2047.3 */ 1266, +/* 6252 2048.0 */ 1172, +/* 6253 2048.1 */ 1061, +/* 6254 2048.2 */ 1265, +/* 6255 2048.3 */ 1169, +/* 6256 2049.0 */ 1254, +/* 6257 2049.1 */ 1061, +/* 6258 2049.2 */ 1267, +/* 6259 2049.3 */ 1268, +/* 6260 2050.0 */ 1254, +/* 6261 2050.1 */ 1061, +/* 6262 2050.2 */ 1267, +/* 6263 2050.3 */ 1256, +/* 6264 2051.0 */ 1257, +/* 6265 2051.1 */ 1061, +/* 6266 2051.2 */ 1269, +/* 6267 2051.3 */ 1270, +/* 6268 2052.0 */ 1257, +/* 6269 2052.1 */ 1061, +/* 6270 2052.2 */ 1269, +/* 6271 2052.3 */ 1256, +/* 6272 2053.0 */ 1259, +/* 6273 2053.1 */ 1061, +/* 6274 2053.2 */ 1271, +/* 6275 2053.3 */ 1272, +/* 6276 2054.0 */ 1259, +/* 6277 2054.1 */ 1061, +/* 6278 2054.2 */ 1271, +/* 6279 2054.3 */ 1256, +/* 6280 2055.0 */ 1279, +/* 6281 2055.1 */ 1061, +/* 6282 2055.2 */ 1205, +/* 6283 2056.0 */ 1280, +/* 6284 2056.1 */ 1148, +/* 6285 2056.2 */ 1206, +/* 6286 2057.0 */ 1279, +/* 6287 2057.1 */ 1061, +/* 6288 2057.2 */ 1229, +/* 6289 2058.0 */ 1281, +/* 6290 2058.1 */ 1148, +/* 6291 2058.2 */ 1225, +/* 6292 2059.0 */ 1279, +/* 6293 2059.1 */ 1061, +/* 6294 2059.2 */ 1207, +/* 6295 2060.0 */ 1282, +/* 6296 2060.1 */ 1148, +/* 6297 2060.2 */ 1208, +/* 6298 2061.0 */ 1283, +/* 6299 2061.1 */ 1061, +/* 6300 2061.2 */ 1205, +/* 6301 2062.0 */ 1284, +/* 6302 2062.1 */ 1148, +/* 6303 2062.2 */ 1206, +/* 6304 2063.0 */ 1285, +/* 6305 2063.1 */ 1061, +/* 6306 2063.2 */ 1229, +/* 6307 2064.0 */ 1286, +/* 6308 2064.1 */ 1148, +/* 6309 2064.2 */ 1225, +/* 6310 2065.0 */ 1285, +/* 6311 2065.1 */ 1061, +/* 6312 2065.2 */ 1207, +/* 6313 2066.0 */ 1287, +/* 6314 2066.1 */ 1148, +/* 6315 2066.2 */ 1208, +/* 6316 2067.0 */ 1279, +/* 6317 2067.1 */ 1061, +/* 6318 2067.2 */ 1210, +/* 6319 2068.0 */ 1282, +/* 6320 2068.1 */ 1148, +/* 6321 2068.2 */ 1211, +/* 6322 2069.0 */ 1279, +/* 6323 2069.1 */ 1061, +/* 6324 2069.2 */ 1235, +/* 6325 2070.0 */ 1288, +/* 6326 2070.1 */ 1148, +/* 6327 2070.2 */ 1236, +/* 6328 2071.0 */ 1279, +/* 6329 2071.1 */ 1061, +/* 6330 2071.2 */ 1237, +/* 6331 2072.0 */ 1281, +/* 6332 2072.1 */ 1148, +/* 6333 2072.2 */ 1238, +/* 6334 2073.0 */ 1230, +/* 6335 2073.1 */ 1061, +/* 6336 2073.2 */ 1210, +/* 6337 2074.0 */ 1015, +/* 6338 2074.1 */ 1148, +/* 6339 2074.2 */ 1211, +/* 6340 2075.0 */ 1204, +/* 6341 2075.1 */ 1061, +/* 6342 2075.2 */ 1235, +/* 6343 2076.0 */ 675, +/* 6344 2076.1 */ 1148, +/* 6345 2076.2 */ 1236, +/* 6346 2077.0 */ 1204, +/* 6347 2077.1 */ 1061, +/* 6348 2077.2 */ 1237, +/* 6349 2078.0 */ 1013, +/* 6350 2078.1 */ 1148, +/* 6351 2078.2 */ 1238, +/* 6352 2079.0 */ 1285, +/* 6353 2079.1 */ 1061, +/* 6354 2079.2 */ 1210, +/* 6355 2080.0 */ 1287, +/* 6356 2080.1 */ 1148, +/* 6357 2080.2 */ 1211, +/* 6358 2081.0 */ 1285, +/* 6359 2081.1 */ 1061, +/* 6360 2081.2 */ 1235, +/* 6361 2082.0 */ 1289, +/* 6362 2082.1 */ 1148, +/* 6363 2082.2 */ 1236, +/* 6364 2083.0 */ 1285, +/* 6365 2083.1 */ 1061, +/* 6366 2083.2 */ 1237, +/* 6367 2084.0 */ 1286, +/* 6368 2084.1 */ 1148, +/* 6369 2084.2 */ 1238, +/* 6370 2085.0 */ 1290, +/* 6371 2085.1 */ 1061, +/* 6372 2085.2 */ 1291, +/* 6373 2086.0 */ 1292, +/* 6374 2086.1 */ 1148, +/* 6375 2086.2 */ 1293, +/* 6376 2087.0 */ 1290, +/* 6377 2087.1 */ 1061, +/* 6378 2087.2 */ 1294, +/* 6379 2088.0 */ 1295, +/* 6380 2088.1 */ 1148, +/* 6381 2088.2 */ 1296, +/* 6382 2089.0 */ 1290, +/* 6383 2089.1 */ 1061, +/* 6384 2089.2 */ 1297, +/* 6385 2090.0 */ 1298, +/* 6386 2090.1 */ 1148, +/* 6387 2090.2 */ 1299, +/* 6388 2091.0 */ 1300, +/* 6389 2091.1 */ 1061, +/* 6390 2091.2 */ 1291, +/* 6391 2092.0 */ 1301, +/* 6392 2092.1 */ 1148, +/* 6393 2092.2 */ 1293, +/* 6394 2093.0 */ 1302, +/* 6395 2093.1 */ 1061, +/* 6396 2093.2 */ 1294, +/* 6397 2094.0 */ 1303, +/* 6398 2094.1 */ 1148, +/* 6399 2094.2 */ 1296, +/* 6400 2095.0 */ 1302, +/* 6401 2095.1 */ 1061, +/* 6402 2095.2 */ 1297, +/* 6403 2096.0 */ 1304, +/* 6404 2096.1 */ 1148, +/* 6405 2096.2 */ 1299, +/* 6406 2097.0 */ 1290, +/* 6407 2097.1 */ 1061, +/* 6408 2097.2 */ 1305, +/* 6409 2098.0 */ 1298, +/* 6410 2098.1 */ 1148, +/* 6411 2098.2 */ 1306, +/* 6412 2099.0 */ 1290, +/* 6413 2099.1 */ 1061, +/* 6414 2099.2 */ 1307, +/* 6415 2100.0 */ 1308, +/* 6416 2100.1 */ 1148, +/* 6417 2100.2 */ 1309, +/* 6418 2101.0 */ 1290, +/* 6419 2101.1 */ 1061, +/* 6420 2101.2 */ 1310, +/* 6421 2102.0 */ 1295, +/* 6422 2102.1 */ 1148, +/* 6423 2102.2 */ 1311, +/* 6424 2103.0 */ 1312, +/* 6425 2103.1 */ 1061, +/* 6426 2103.2 */ 1305, +/* 6427 2104.0 */ 897, +/* 6428 2104.1 */ 1148, +/* 6429 2104.2 */ 1306, +/* 6430 2105.0 */ 1313, +/* 6431 2105.1 */ 1061, +/* 6432 2105.2 */ 1307, +/* 6433 2106.0 */ 1314, +/* 6434 2106.1 */ 1148, +/* 6435 2106.2 */ 1309, +/* 6436 2107.0 */ 1313, +/* 6437 2107.1 */ 1061, +/* 6438 2107.2 */ 1310, +/* 6439 2108.0 */ 548, +/* 6440 2108.1 */ 1148, +/* 6441 2108.2 */ 1311, +/* 6442 2109.0 */ 1302, +/* 6443 2109.1 */ 1061, +/* 6444 2109.2 */ 1305, +/* 6445 2110.0 */ 1304, +/* 6446 2110.1 */ 1148, +/* 6447 2110.2 */ 1306, +/* 6448 2111.0 */ 1302, +/* 6449 2111.1 */ 1061, +/* 6450 2111.2 */ 1307, +/* 6451 2112.0 */ 1315, +/* 6452 2112.1 */ 1148, +/* 6453 2112.2 */ 1309, +/* 6454 2113.0 */ 1302, +/* 6455 2113.1 */ 1061, +/* 6456 2113.2 */ 1310, +/* 6457 2114.0 */ 1303, +/* 6458 2114.1 */ 1148, +/* 6459 2114.2 */ 1311, +/* 6460 2115.0 */ 1181, +/* 6461 2115.1 */ 1061, +/* 6462 2115.2 */ 1316, +/* 6463 2116.0 */ 1181, +/* 6464 2116.1 */ 1061, +/* 6465 2116.2 */ 506, +/* 6466 2117.0 */ 1174, +/* 6467 2117.1 */ 1061, +/* 6468 2117.2 */ 1316, +/* 6469 2118.0 */ 1174, +/* 6470 2118.1 */ 1061, +/* 6471 2118.2 */ 602, +/* 6472 2119.0 */ 1172, +/* 6473 2119.1 */ 1061, +/* 6474 2119.2 */ 1316, +/* 6475 2120.0 */ 1172, +/* 6476 2120.1 */ 1061, +/* 6477 2120.2 */ 503, +/* 6478 2121.0 */ 1254, +/* 6479 2121.1 */ 1061, +/* 6480 2121.2 */ 1316, +/* 6481 2122.0 */ 1254, +/* 6482 2122.1 */ 1061, +/* 6483 2122.2 */ 503, +/* 6484 2123.0 */ 1257, +/* 6485 2123.1 */ 1061, +/* 6486 2123.2 */ 1316, +/* 6487 2124.0 */ 1257, +/* 6488 2124.1 */ 1061, +/* 6489 2124.2 */ 1317, +/* 6490 2125.0 */ 1259, +/* 6491 2125.1 */ 1061, +/* 6492 2125.2 */ 1316, +/* 6493 2126.0 */ 1259, +/* 6494 2126.1 */ 1061, +/* 6495 2126.2 */ 602, +/* 6496 2127.0 */ 1254, +/* 6497 2127.1 */ 1061, +/* 6498 2127.2 */ 1168, +/* 6499 2128.0 */ 1254, +/* 6500 2128.1 */ 1061, +/* 6501 2128.2 */ 864, +/* 6502 2129.0 */ 1257, +/* 6503 2129.1 */ 1061, +/* 6504 2129.2 */ 1170, +/* 6505 2130.0 */ 1257, +/* 6506 2130.1 */ 1061, +/* 6507 2130.2 */ 508, +/* 6508 2131.0 */ 1259, +/* 6509 2131.1 */ 1061, +/* 6510 2131.2 */ 1170, +/* 6511 2132.0 */ 1259, +/* 6512 2132.1 */ 1061, +/* 6513 2132.2 */ 247, +/* 6514 2133.0 */ 1181, +/* 6515 2133.1 */ 1061, +/* 6516 2133.2 */ 1318, +/* 6517 2134.0 */ 1181, +/* 6518 2134.1 */ 1061, +/* 6519 2134.2 */ 912, +/* 6520 2135.0 */ 1174, +/* 6521 2135.1 */ 1061, +/* 6522 2135.2 */ 1319, +/* 6523 2136.0 */ 1174, +/* 6524 2136.1 */ 1061, +/* 6525 2136.2 */ 498, +/* 6526 2137.0 */ 1172, +/* 6527 2137.1 */ 1061, +/* 6528 2137.2 */ 1319, +/* 6529 2138.0 */ 1172, +/* 6530 2138.1 */ 1061, +/* 6531 2138.2 */ 500, +/* 6532 2139.0 */ 1254, +/* 6533 2139.1 */ 1061, +/* 6534 2139.2 */ 1319, +/* 6535 2140.0 */ 1254, +/* 6536 2140.1 */ 1061, +/* 6537 2140.2 */ 500, +/* 6538 2141.0 */ 1257, +/* 6539 2141.1 */ 1061, +/* 6540 2141.2 */ 1319, +/* 6541 2142.0 */ 1257, +/* 6542 2142.1 */ 1061, +/* 6543 2142.2 */ 608, +/* 6544 2143.0 */ 1259, +/* 6545 2143.1 */ 1061, +/* 6546 2143.2 */ 1319, +/* 6547 2144.0 */ 1259, +/* 6548 2144.1 */ 1061, +/* 6549 2144.2 */ 498, +/* 6550 2145.0 */ 1320, +/* 6551 2145.1 */ 1061, +/* 6552 2145.2 */ 1110, +/* 6553 2145.3 */ 120, +/* 6554 2146.0 */ 1320, +/* 6555 2146.1 */ 1061, +/* 6556 2146.2 */ 1064, +/* 6557 2146.3 */ 120, +/* 6558 2147.0 */ 1321, +/* 6559 2147.1 */ 1061, +/* 6560 2147.2 */ 1112, +/* 6561 2147.3 */ 120, +/* 6562 2148.0 */ 1321, +/* 6563 2148.1 */ 1061, +/* 6564 2148.2 */ 1064, +/* 6565 2148.3 */ 120, +/* 6566 2149.0 */ 1322, +/* 6567 2149.1 */ 1061, +/* 6568 2149.2 */ 1114, +/* 6569 2149.3 */ 120, +/* 6570 2150.0 */ 1322, +/* 6571 2150.1 */ 1061, +/* 6572 2150.2 */ 1064, +/* 6573 2150.3 */ 120, +/* 6574 2151.0 */ 1323, +/* 6575 2151.1 */ 1061, +/* 6576 2151.2 */ 1116, +/* 6577 2151.3 */ 120, +/* 6578 2152.0 */ 1323, +/* 6579 2152.1 */ 1061, +/* 6580 2152.2 */ 1117, +/* 6581 2152.3 */ 120, +/* 6582 2153.0 */ 1324, +/* 6583 2153.1 */ 1061, +/* 6584 2153.2 */ 1119, +/* 6585 2153.3 */ 120, +/* 6586 2154.0 */ 1324, +/* 6587 2154.1 */ 1061, +/* 6588 2154.2 */ 1117, +/* 6589 2154.3 */ 120, +/* 6590 2155.0 */ 1325, +/* 6591 2155.1 */ 1061, +/* 6592 2155.2 */ 1121, +/* 6593 2155.3 */ 120, +/* 6594 2156.0 */ 1325, +/* 6595 2156.1 */ 1061, +/* 6596 2156.2 */ 1117, +/* 6597 2156.3 */ 120, +/* 6598 2157.0 */ 690, +/* 6599 2157.1 */ 1099, +/* 6600 2157.2 */ 1206, +/* 6601 2158.0 */ 690, +/* 6602 2158.1 */ 1099, +/* 6603 2158.2 */ 1225, +/* 6604 2159.0 */ 690, +/* 6605 2159.1 */ 1099, +/* 6606 2159.2 */ 1208, +/* 6607 2160.0 */ 692, +/* 6608 2160.1 */ 1099, +/* 6609 2160.2 */ 1211, +/* 6610 2161.0 */ 692, +/* 6611 2161.1 */ 1099, +/* 6612 2161.2 */ 1236, +/* 6613 2162.0 */ 692, +/* 6614 2162.1 */ 1099, +/* 6615 2162.2 */ 1238, +/* 6616 2163.0 */ 1109, +/* 6617 2163.1 */ 1061, +/* 6618 2163.2 */ 1110, +/* 6619 2163.3 */ 120, +/* 6620 2164.0 */ 1109, +/* 6621 2164.1 */ 1061, +/* 6622 2164.2 */ 1064, +/* 6623 2164.3 */ 120, +/* 6624 2165.0 */ 1111, +/* 6625 2165.1 */ 1061, +/* 6626 2165.2 */ 1112, +/* 6627 2165.3 */ 120, +/* 6628 2166.0 */ 1111, +/* 6629 2166.1 */ 1061, +/* 6630 2166.2 */ 1064, +/* 6631 2166.3 */ 120, +/* 6632 2167.0 */ 1113, +/* 6633 2167.1 */ 1061, +/* 6634 2167.2 */ 1114, +/* 6635 2167.3 */ 120, +/* 6636 2168.0 */ 1113, +/* 6637 2168.1 */ 1061, +/* 6638 2168.2 */ 1064, +/* 6639 2168.3 */ 120, +/* 6640 2169.0 */ 1109, +/* 6641 2169.1 */ 1061, +/* 6642 2169.2 */ 1092, +/* 6643 2169.3 */ 1063, +/* 6644 2170.0 */ 1109, +/* 6645 2170.1 */ 1061, +/* 6646 2170.2 */ 1092, +/* 6647 2170.3 */ 514, +/* 6648 2171.0 */ 1111, +/* 6649 2171.1 */ 1061, +/* 6650 2171.2 */ 1088, +/* 6651 2171.3 */ 514, +/* 6652 2172.0 */ 1113, +/* 6653 2172.1 */ 1061, +/* 6654 2172.2 */ 1090, +/* 6655 2172.3 */ 1063, +/* 6656 2173.0 */ 1113, +/* 6657 2173.1 */ 1061, +/* 6658 2173.2 */ 1090, +/* 6659 2173.3 */ 514, +/* 6660 2174.0 */ 1115, +/* 6661 2174.1 */ 1061, +/* 6662 2174.2 */ 1132, +/* 6663 2174.3 */ 1135, +/* 6664 2175.0 */ 1115, +/* 6665 2175.1 */ 1061, +/* 6666 2175.2 */ 1132, +/* 6667 2175.3 */ 253, +/* 6668 2176.0 */ 1118, +/* 6669 2176.1 */ 1061, +/* 6670 2176.2 */ 1134, +/* 6671 2176.3 */ 253, +/* 6672 2177.0 */ 1120, +/* 6673 2177.1 */ 1061, +/* 6674 2177.2 */ 1136, +/* 6675 2177.3 */ 1135, +/* 6676 2178.0 */ 1120, +/* 6677 2178.1 */ 1061, +/* 6678 2178.2 */ 1136, +/* 6679 2178.3 */ 253, +/* 6680 2179.0 */ 1273, +/* 6681 2179.1 */ 1061, +/* 6682 2179.2 */ 1092, +/* 6683 2179.3 */ 1070, +/* 6684 2179.4 */ 120, +/* 6685 2180.0 */ 1273, +/* 6686 2180.1 */ 1061, +/* 6687 2180.2 */ 1092, +/* 6688 2180.3 */ 1064, +/* 6689 2180.4 */ 120, +/* 6690 2181.0 */ 1274, +/* 6691 2181.1 */ 1061, +/* 6692 2181.2 */ 1088, +/* 6693 2181.3 */ 1063, +/* 6694 2181.4 */ 120, +/* 6695 2182.0 */ 1274, +/* 6696 2182.1 */ 1061, +/* 6697 2182.2 */ 1088, +/* 6698 2182.3 */ 1064, +/* 6699 2182.4 */ 120, +/* 6700 2183.0 */ 1275, +/* 6701 2183.1 */ 1061, +/* 6702 2183.2 */ 1090, +/* 6703 2183.3 */ 1067, +/* 6704 2183.4 */ 120, +/* 6705 2184.0 */ 1275, +/* 6706 2184.1 */ 1061, +/* 6707 2184.2 */ 1090, +/* 6708 2184.3 */ 1064, +/* 6709 2184.4 */ 120, +/* 6710 2185.0 */ 1276, +/* 6711 2185.1 */ 1061, +/* 6712 2185.2 */ 1132, +/* 6713 2185.3 */ 1133, +/* 6714 2185.4 */ 120, +/* 6715 2186.0 */ 1276, +/* 6716 2186.1 */ 1061, +/* 6717 2186.2 */ 1132, +/* 6718 2186.3 */ 1117, +/* 6719 2186.4 */ 120, +/* 6720 2187.0 */ 1277, +/* 6721 2187.1 */ 1061, +/* 6722 2187.2 */ 1134, +/* 6723 2187.3 */ 1135, +/* 6724 2187.4 */ 120, +/* 6725 2188.0 */ 1277, +/* 6726 2188.1 */ 1061, +/* 6727 2188.2 */ 1134, +/* 6728 2188.3 */ 1117, +/* 6729 2188.4 */ 120, +/* 6730 2189.0 */ 1278, +/* 6731 2189.1 */ 1061, +/* 6732 2189.2 */ 1136, +/* 6733 2189.3 */ 1137, +/* 6734 2189.4 */ 120, +/* 6735 2190.0 */ 1278, +/* 6736 2190.1 */ 1061, +/* 6737 2190.2 */ 1136, +/* 6738 2190.3 */ 1117, +/* 6739 2190.4 */ 120, +/* 6740 2191.0 */ 953, +/* 6741 2191.1 */ 1099, +/* 6742 2191.2 */ 1149, +/* 6743 2192.0 */ 953, +/* 6744 2192.1 */ 1099, +/* 6745 2192.2 */ 1152, +/* 6746 2193.0 */ 953, +/* 6747 2193.1 */ 1099, +/* 6748 2193.2 */ 1155, +/* 6749 2194.0 */ 875, +/* 6750 2194.1 */ 1099, +/* 6751 2194.2 */ 1159, +/* 6752 2195.0 */ 875, +/* 6753 2195.1 */ 1099, +/* 6754 2195.2 */ 1162, +/* 6755 2196.0 */ 875, +/* 6756 2196.1 */ 1099, +/* 6757 2196.2 */ 1165, +/* 6758 2197.0 */ 1097, +/* 6759 2197.1 */ 1061, +/* 6760 2197.2 */ 1082, +/* 6761 2197.3 */ 1083, +/* 6762 2197.4 */ 120, +/* 6763 2198.0 */ 1097, +/* 6764 2198.1 */ 1061, +/* 6765 2198.2 */ 1082, +/* 6766 2198.3 */ 1077, +/* 6767 2198.4 */ 120, +/* 6768 2199.0 */ 1129, +/* 6769 2199.1 */ 1061, +/* 6770 2199.2 */ 1079, +/* 6771 2199.3 */ 1080, +/* 6772 2199.4 */ 120, +/* 6773 2200.0 */ 1129, +/* 6774 2200.1 */ 1061, +/* 6775 2200.2 */ 1079, +/* 6776 2200.3 */ 1077, +/* 6777 2200.4 */ 120, +/* 6778 2201.0 */ 1093, +/* 6779 2201.1 */ 1061, +/* 6780 2201.2 */ 1122, +/* 6781 2201.3 */ 1123, +/* 6782 2201.4 */ 120, +/* 6783 2202.0 */ 1093, +/* 6784 2202.1 */ 1061, +/* 6785 2202.2 */ 1122, +/* 6786 2202.3 */ 1096, +/* 6787 2202.4 */ 120, +/* 6788 2203.0 */ 1125, +/* 6789 2203.1 */ 1061, +/* 6790 2203.2 */ 1126, +/* 6791 2203.3 */ 1127, +/* 6792 2203.4 */ 120, +/* 6793 2204.0 */ 1125, +/* 6794 2204.1 */ 1061, +/* 6795 2204.2 */ 1126, +/* 6796 2204.3 */ 1096, +/* 6797 2204.4 */ 120, +/* 6798 2205.0 */ 1100, +/* 6799 2205.1 */ 1061, +/* 6800 2205.2 */ 1101, +/* 6801 2205.3 */ 1096, +/* 6802 2205.4 */ 120, +/* 6803 2206.0 */ 1104, +/* 6804 2206.1 */ 1061, +/* 6805 2206.2 */ 1075, +/* 6806 2206.3 */ 1077, +/* 6807 2206.4 */ 120, +/* 6808 2207.0 */ 1124, +/* 6809 2207.1 */ 1061, +/* 6810 2207.2 */ 1094, +/* 6811 2208.0 */ 1128, +/* 6812 2208.1 */ 1061, +/* 6813 2208.2 */ 1086, +/* 6814 2209.0 */ 1115, +/* 6815 2209.1 */ 1045, +/* 6816 2210.0 */ 1118, +/* 6817 2210.1 */ 1045, +/* 6818 2211.0 */ 1120, +/* 6819 2211.1 */ 1045, +/* 6820 2212.0 */ 1109, +/* 6821 2212.1 */ 1044, +/* 6822 2213.0 */ 1111, +/* 6823 2213.1 */ 1044, +/* 6824 2214.0 */ 1113, +/* 6825 2214.1 */ 1044, +/* 6826 2215.0 */ 1129, +/* 6827 2215.1 */ 1061, +/* 6828 2215.2 */ 292, +/* 6829 2216.0 */ 1097, +/* 6830 2216.1 */ 1061, +/* 6831 2216.2 */ 292, +/* 6832 2217.0 */ 1097, +/* 6833 2217.1 */ 1061, +/* 6834 2217.2 */ 805, +/* 6835 2218.0 */ 1125, +/* 6836 2218.1 */ 1061, +/* 6837 2218.2 */ 584, +/* 6838 2219.0 */ 1093, +/* 6839 2219.1 */ 1061, +/* 6840 2219.2 */ 584, +/* 6841 2220.0 */ 1111, +/* 6842 2220.1 */ 1061, +/* 6843 2220.2 */ 551, +/* 6844 2221.0 */ 1113, +/* 6845 2221.1 */ 1061, +/* 6846 2221.2 */ 551, +/* 6847 2222.0 */ 1109, +/* 6848 2222.1 */ 1061, +/* 6849 2222.2 */ 551, +/* 6850 2223.0 */ 1109, +/* 6851 2223.1 */ 1061, +/* 6852 2223.2 */ 878, +/* 6853 2224.0 */ 1120, +/* 6854 2224.1 */ 1061, +/* 6855 2224.2 */ 253, +/* 6856 2225.0 */ 1115, +/* 6857 2225.1 */ 1061, +/* 6858 2225.2 */ 253, +/* 6859 2226.0 */ 1257, +/* 6860 2226.1 */ 1061, +/* 6861 2226.2 */ 1138, +/* 6862 2227.0 */ 1257, +/* 6863 2227.1 */ 1061, +/* 6864 2227.2 */ 1096, +/* 6865 2228.0 */ 1259, +/* 6866 2228.1 */ 1061, +/* 6867 2228.2 */ 1175, +/* 6868 2229.0 */ 1259, +/* 6869 2229.1 */ 1061, +/* 6870 2229.2 */ 1096, +/* 6871 2230.0 */ 1254, +/* 6872 2230.1 */ 1061, +/* 6873 2230.2 */ 1094, +/* 6874 2231.0 */ 1326, +/* 6875 2231.1 */ 1061, +/* 6876 2231.2 */ 1094, +/* 6877 2232.0 */ 1254, +/* 6878 2232.1 */ 1061, +/* 6879 2232.2 */ 1096, +/* 6880 2233.0 */ 1118, +/* 6881 2233.1 */ 1061, +/* 6882 2233.2 */ 1138, +/* 6883 2234.0 */ 1118, +/* 6884 2234.1 */ 1061, +/* 6885 2234.2 */ 1096, +/* 6886 2235.0 */ 1120, +/* 6887 2235.1 */ 1061, +/* 6888 2235.2 */ 1175, +/* 6889 2236.0 */ 1120, +/* 6890 2236.1 */ 1061, +/* 6891 2236.2 */ 1096, +/* 6892 2237.0 */ 1115, +/* 6893 2237.1 */ 1061, +/* 6894 2237.2 */ 1094, +/* 6895 2238.0 */ 1327, +/* 6896 2238.1 */ 1061, +/* 6897 2238.2 */ 1094, +/* 6898 2239.0 */ 1115, +/* 6899 2239.1 */ 1061, +/* 6900 2239.2 */ 1096, +/* 6901 2240.0 */ 1257, +/* 6902 2240.1 */ 1061, +/* 6903 2240.2 */ 1084, +/* 6904 2241.0 */ 1257, +/* 6905 2241.1 */ 1061, +/* 6906 2241.2 */ 1077, +/* 6907 2242.0 */ 1259, +/* 6908 2242.1 */ 1061, +/* 6909 2242.2 */ 1084, +/* 6910 2243.0 */ 1259, +/* 6911 2243.1 */ 1061, +/* 6912 2243.2 */ 1077, +/* 6913 2244.0 */ 1254, +/* 6914 2244.1 */ 1061, +/* 6915 2244.2 */ 1085, +/* 6916 2245.0 */ 1326, +/* 6917 2245.1 */ 1061, +/* 6918 2245.2 */ 1085, +/* 6919 2246.0 */ 1254, +/* 6920 2246.1 */ 1061, +/* 6921 2246.2 */ 1077, +/* 6922 2247.0 */ 1118, +/* 6923 2247.1 */ 1061, +/* 6924 2247.2 */ 1084, +/* 6925 2248.0 */ 1118, +/* 6926 2248.1 */ 1061, +/* 6927 2248.2 */ 1077, +/* 6928 2249.0 */ 1120, +/* 6929 2249.1 */ 1061, +/* 6930 2249.2 */ 1084, +/* 6931 2250.0 */ 1120, +/* 6932 2250.1 */ 1061, +/* 6933 2250.2 */ 1077, +/* 6934 2251.0 */ 1115, +/* 6935 2251.1 */ 1061, +/* 6936 2251.2 */ 1085, +/* 6937 2252.0 */ 1327, +/* 6938 2252.1 */ 1061, +/* 6939 2252.2 */ 1085, +/* 6940 2253.0 */ 1115, +/* 6941 2253.1 */ 1061, +/* 6942 2253.2 */ 1077, +/* 6943 2254.0 */ 1104, +/* 6944 2254.1 */ 1061, +/* 6945 2254.2 */ 1119, +/* 6946 2255.0 */ 1104, +/* 6947 2255.1 */ 1061, +/* 6948 2255.2 */ 1117, +/* 6949 2256.0 */ 1104, +/* 6950 2256.1 */ 1061, +/* 6951 2256.2 */ 1121, +/* 6952 2257.0 */ 1129, +/* 6953 2257.1 */ 1061, +/* 6954 2257.2 */ 1116, +/* 6955 2258.0 */ 1176, +/* 6956 2258.1 */ 1061, +/* 6957 2258.2 */ 1116, +/* 6958 2259.0 */ 1129, +/* 6959 2259.1 */ 1061, +/* 6960 2259.2 */ 1117, +/* 6961 2260.0 */ 1328, +/* 6962 2260.1 */ 1061, +/* 6963 2260.2 */ 1094, +/* 6964 2261.0 */ 1329, +/* 6965 2261.1 */ 1061, +/* 6966 2261.2 */ 1094, +/* 6967 2262.0 */ 1328, +/* 6968 2262.1 */ 1061, +/* 6969 2262.2 */ 1085, +/* 6970 2263.0 */ 1329, +/* 6971 2263.1 */ 1061, +/* 6972 2263.2 */ 1085, +/* 6973 2264.0 */ 1100, +/* 6974 2264.1 */ 1061, +/* 6975 2264.2 */ 1119, +/* 6976 2265.0 */ 1100, +/* 6977 2265.1 */ 1061, +/* 6978 2265.2 */ 1117, +/* 6979 2266.0 */ 1125, +/* 6980 2266.1 */ 1061, +/* 6981 2266.2 */ 1121, +/* 6982 2267.0 */ 1125, +/* 6983 2267.1 */ 1061, +/* 6984 2267.2 */ 1117, +/* 6985 2268.0 */ 1093, +/* 6986 2268.1 */ 1061, +/* 6987 2268.2 */ 1116, +/* 6988 2269.0 */ 1124, +/* 6989 2269.1 */ 1061, +/* 6990 2269.2 */ 1116, +/* 6991 2270.0 */ 1093, +/* 6992 2270.1 */ 1061, +/* 6993 2270.2 */ 1117, +/* 6994 2271.0 */ 1330, +/* 6995 2271.1 */ 1061, +/* 6996 2271.2 */ 1062, +/* 6997 2271.3 */ 1331, +/* 6998 2271.4 */ 120, +/* 6999 2272.0 */ 1330, +/* 7000 2272.1 */ 1061, +/* 7001 2272.2 */ 1062, +/* 7002 2272.3 */ 545, +/* 7003 2272.4 */ 120, +/* 7004 2273.0 */ 1332, +/* 7005 2273.1 */ 1061, +/* 7006 2273.2 */ 1066, +/* 7007 2273.3 */ 1333, +/* 7008 2273.4 */ 120, +/* 7009 2274.0 */ 1332, +/* 7010 2274.1 */ 1061, +/* 7011 2274.2 */ 1066, +/* 7012 2274.3 */ 943, +/* 7013 2274.4 */ 120, +/* 7014 2275.0 */ 1334, +/* 7015 2275.1 */ 1061, +/* 7016 2275.2 */ 1069, +/* 7017 2275.3 */ 1335, +/* 7018 2275.4 */ 120, +/* 7019 2276.0 */ 1334, +/* 7020 2276.1 */ 1061, +/* 7021 2276.2 */ 1069, +/* 7022 2276.3 */ 729, +/* 7023 2276.4 */ 120, +/* 7024 2277.0 */ 1166, +/* 7025 2277.1 */ 1061, +/* 7026 2277.2 */ 1161, +/* 7027 2277.3 */ 120, +/* 7028 2278.0 */ 882, +/* 7029 2278.1 */ 1148, +/* 7030 2278.2 */ 1159, +/* 7031 2278.3 */ 120, +/* 7032 2279.0 */ 1153, +/* 7033 2279.1 */ 1061, +/* 7034 2279.2 */ 1157, +/* 7035 2279.3 */ 120, +/* 7036 2280.0 */ 871, +/* 7037 2280.1 */ 1148, +/* 7038 2280.2 */ 1155, +/* 7039 2280.3 */ 120, +/* 7040 2281.0 */ 1153, +/* 7041 2281.1 */ 1061, +/* 7042 2281.2 */ 1151, +/* 7043 2281.3 */ 120, +/* 7044 2282.0 */ 871, +/* 7045 2282.1 */ 1148, +/* 7046 2282.2 */ 1149, +/* 7047 2282.3 */ 120, +/* 7048 2283.0 */ 1230, +/* 7049 2283.1 */ 1061, +/* 7050 2283.2 */ 1205, +/* 7051 2283.3 */ 120, +/* 7052 2284.0 */ 1015, +/* 7053 2284.1 */ 1148, +/* 7054 2284.2 */ 1206, +/* 7055 2284.3 */ 120, +/* 7056 2285.0 */ 1234, +/* 7057 2285.1 */ 1061, +/* 7058 2285.2 */ 1237, +/* 7059 2285.3 */ 120, +/* 7060 2286.0 */ 676, +/* 7061 2286.1 */ 1148, +/* 7062 2286.2 */ 1238, +/* 7063 2286.3 */ 120, +/* 7064 2287.0 */ 1234, +/* 7065 2287.1 */ 1061, +/* 7066 2287.2 */ 1210, +/* 7067 2287.3 */ 120, +/* 7068 2288.0 */ 676, +/* 7069 2288.1 */ 1148, +/* 7070 2288.2 */ 1211, +/* 7071 2288.3 */ 120, +/* 7072 2289.0 */ 1034, +/* 7073 2289.1 */ 1139, +/* 7074 2289.2 */ 1138, +/* 7075 2289.3 */ 120, +/* 7076 2290.0 */ 1034, +/* 7077 2290.1 */ 1139, +/* 7078 2290.2 */ 1096, +/* 7079 2290.3 */ 120, +/* 7080 2291.0 */ 1034, +/* 7081 2291.1 */ 1139, +/* 7082 2291.2 */ 1175, +/* 7083 2291.3 */ 120, +/* 7084 2292.0 */ 1034, +/* 7085 2292.1 */ 1139, +/* 7086 2292.2 */ 1094, +/* 7087 2292.3 */ 120, +/* 7088 2293.0 */ 1034, +/* 7089 2293.1 */ 1139, +/* 7090 2293.2 */ 1084, +/* 7091 2293.3 */ 120, +/* 7092 2294.0 */ 1034, +/* 7093 2294.1 */ 1139, +/* 7094 2294.2 */ 1077, +/* 7095 2294.3 */ 120, +/* 7096 2295.0 */ 1034, +/* 7097 2295.1 */ 1139, +/* 7098 2295.2 */ 1085, +/* 7099 2295.3 */ 120, +/* 7100 2296.0 */ 1034, +/* 7101 2296.1 */ 1139, +/* 7102 2296.2 */ 1086, +/* 7103 2296.3 */ 120, +/* 7104 2297.0 */ 1034, +/* 7105 2297.1 */ 1139, +/* 7106 2297.2 */ 812, +/* 7107 2297.3 */ 120, +/* 7108 2298.0 */ 1034, +/* 7109 2298.1 */ 1139, +/* 7110 2298.2 */ 810, +/* 7111 2298.3 */ 120, +/* 7112 2299.0 */ 1097, +/* 7113 2299.1 */ 1061, +/* 7114 2299.2 */ 1082, +/* 7115 2299.3 */ 1080, +/* 7116 2299.4 */ 120, +/* 7117 2300.0 */ 1097, +/* 7118 2300.1 */ 1061, +/* 7119 2300.2 */ 1082, +/* 7120 2300.3 */ 805, +/* 7121 2300.4 */ 120, +/* 7122 2301.0 */ 1125, +/* 7123 2301.1 */ 1061, +/* 7124 2301.2 */ 1126, +/* 7125 2301.3 */ 1102, +/* 7126 2301.4 */ 120, +/* 7127 2302.0 */ 1125, +/* 7128 2302.1 */ 1061, +/* 7129 2302.2 */ 1126, +/* 7130 2302.3 */ 584, +/* 7131 2302.4 */ 120, +/* 7132 2303.0 */ 1093, +/* 7133 2303.1 */ 1061, +/* 7134 2303.2 */ 1122, +/* 7135 2303.3 */ 1102, +/* 7136 2303.4 */ 120, +/* 7137 2304.0 */ 1093, +/* 7138 2304.1 */ 1061, +/* 7139 2304.2 */ 1122, +/* 7140 2304.3 */ 584, +/* 7141 2304.4 */ 120, +/* 7142 2305.0 */ 1109, +/* 7143 2305.1 */ 1061, +/* 7144 2305.2 */ 1092, +/* 7145 2305.3 */ 1067, +/* 7146 2305.4 */ 120, +/* 7147 2306.0 */ 1109, +/* 7148 2306.1 */ 1061, +/* 7149 2306.2 */ 1092, +/* 7150 2306.3 */ 878, +/* 7151 2306.4 */ 120, +/* 7152 2307.0 */ 1120, +/* 7153 2307.1 */ 1061, +/* 7154 2307.2 */ 1136, +/* 7155 2307.3 */ 1135, +/* 7156 2307.4 */ 120, +/* 7157 2308.0 */ 1120, +/* 7158 2308.1 */ 1061, +/* 7159 2308.2 */ 1136, +/* 7160 2308.3 */ 253, +/* 7161 2308.4 */ 120, +/* 7162 2309.0 */ 1115, +/* 7163 2309.1 */ 1061, +/* 7164 2309.2 */ 1132, +/* 7165 2309.3 */ 1135, +/* 7166 2309.4 */ 120, +/* 7167 2310.0 */ 1115, +/* 7168 2310.1 */ 1061, +/* 7169 2310.2 */ 1132, +/* 7170 2310.3 */ 253, +/* 7171 2310.4 */ 120, +/* 7172 2311.0 */ 1330, +/* 7173 2311.1 */ 1061, +/* 7174 2311.2 */ 1336, +/* 7175 2312.0 */ 1330, +/* 7176 2312.1 */ 1061, +/* 7177 2312.2 */ 517, +/* 7178 2313.0 */ 1285, +/* 7179 2313.1 */ 1061, +/* 7180 2313.2 */ 1337, +/* 7181 2314.0 */ 1287, +/* 7182 2314.1 */ 1148, +/* 7183 2314.2 */ 1338, +/* 7184 2315.0 */ 1332, +/* 7185 2315.1 */ 1061, +/* 7186 2315.2 */ 1339, +/* 7187 2316.0 */ 1332, +/* 7188 2316.1 */ 1061, +/* 7189 2316.2 */ 916, +/* 7190 2317.0 */ 1283, +/* 7191 2317.1 */ 1061, +/* 7192 2317.2 */ 1340, +/* 7193 2318.0 */ 1284, +/* 7194 2318.1 */ 1148, +/* 7195 2318.2 */ 1341, +/* 7196 2319.0 */ 1334, +/* 7197 2319.1 */ 1061, +/* 7198 2319.2 */ 1342, +/* 7199 2320.0 */ 1334, +/* 7200 2320.1 */ 1061, +/* 7201 2320.2 */ 1343, +/* 7202 2321.0 */ 1344, +/* 7203 2321.1 */ 1061, +/* 7204 2321.2 */ 1345, +/* 7205 2322.0 */ 1346, +/* 7206 2322.1 */ 1148, +/* 7207 2322.2 */ 1347, +/* 7208 2323.0 */ 1348, +/* 7209 2323.1 */ 1061, +/* 7210 2323.2 */ 1349, +/* 7211 2324.0 */ 1348, +/* 7212 2324.1 */ 1061, +/* 7213 2324.2 */ 545, +/* 7214 2325.0 */ 1279, +/* 7215 2325.1 */ 1061, +/* 7216 2325.2 */ 1350, +/* 7217 2326.0 */ 1280, +/* 7218 2326.1 */ 1148, +/* 7219 2326.2 */ 1351, +/* 7220 2327.0 */ 1352, +/* 7221 2327.1 */ 1061, +/* 7222 2327.2 */ 1353, +/* 7223 2328.0 */ 1352, +/* 7224 2328.1 */ 1061, +/* 7225 2328.2 */ 943, +/* 7226 2329.0 */ 1354, +/* 7227 2329.1 */ 1061, +/* 7228 2329.2 */ 1355, +/* 7229 2330.0 */ 1356, +/* 7230 2330.1 */ 1148, +/* 7231 2330.2 */ 1357, +/* 7232 2331.0 */ 1358, +/* 7233 2331.1 */ 1061, +/* 7234 2331.2 */ 1359, +/* 7235 2332.0 */ 1358, +/* 7236 2332.1 */ 1061, +/* 7237 2332.2 */ 729, +/* 7238 2333.0 */ 1360, +/* 7239 2333.1 */ 1061, +/* 7240 2333.2 */ 1361, +/* 7241 2334.0 */ 1362, +/* 7242 2334.1 */ 1148, +/* 7243 2334.2 */ 1363, +/* 7244 2335.0 */ 1364, +/* 7245 2335.1 */ 1061, +/* 7246 2335.2 */ 1316, +/* 7247 2336.0 */ 1364, +/* 7248 2336.1 */ 1061, +/* 7249 2336.2 */ 506, +/* 7250 2337.0 */ 1365, +/* 7251 2337.1 */ 1061, +/* 7252 2337.2 */ 1366, +/* 7253 2338.0 */ 1365, +/* 7254 2338.1 */ 1061, +/* 7255 2338.2 */ 909, +/* 7256 2339.0 */ 1367, +/* 7257 2339.1 */ 1061, +/* 7258 2339.2 */ 1368, +/* 7259 2340.0 */ 1367, +/* 7260 2340.1 */ 1061, +/* 7261 2340.2 */ 1369, +/* 7262 2341.0 */ 1370, +/* 7263 2341.1 */ 1061, +/* 7264 2341.2 */ 1319, +/* 7265 2342.0 */ 1370, +/* 7266 2342.1 */ 1061, +/* 7267 2342.2 */ 500, +/* 7268 2343.0 */ 1371, +/* 7269 2343.1 */ 1061, +/* 7270 2343.2 */ 1318, +/* 7271 2344.0 */ 1371, +/* 7272 2344.1 */ 1061, +/* 7273 2344.2 */ 912, +/* 7274 2345.0 */ 1372, +/* 7275 2345.1 */ 1061, +/* 7276 2345.2 */ 1373, +/* 7277 2346.0 */ 1372, +/* 7278 2346.1 */ 1061, +/* 7279 2346.2 */ 1374, +/* 7280 2347.0 */ 1370, +/* 7281 2347.1 */ 1061, +/* 7282 2347.2 */ 1263, +/* 7283 2347.3 */ 1264, +/* 7284 2348.0 */ 1370, +/* 7285 2348.1 */ 1061, +/* 7286 2348.2 */ 1263, +/* 7287 2348.3 */ 1169, +/* 7288 2349.0 */ 1371, +/* 7289 2349.1 */ 1061, +/* 7290 2349.2 */ 1265, +/* 7291 2349.3 */ 1266, +/* 7292 2350.0 */ 1371, +/* 7293 2350.1 */ 1061, +/* 7294 2350.2 */ 1265, +/* 7295 2350.3 */ 1169, +/* 7296 2351.0 */ 1372, +/* 7297 2351.1 */ 1061, +/* 7298 2351.2 */ 1261, +/* 7299 2351.3 */ 1262, +/* 7300 2352.0 */ 1372, +/* 7301 2352.1 */ 1061, +/* 7302 2352.2 */ 1261, +/* 7303 2352.3 */ 1169, +/* 7304 2353.0 */ 1364, +/* 7305 2353.1 */ 1061, +/* 7306 2353.2 */ 1071, +/* 7307 2353.3 */ 1375, +/* 7308 2354.0 */ 1364, +/* 7309 2354.1 */ 1061, +/* 7310 2354.2 */ 1071, +/* 7311 2354.3 */ 500, +/* 7312 2355.0 */ 1365, +/* 7313 2355.1 */ 1061, +/* 7314 2355.2 */ 1072, +/* 7315 2355.3 */ 1376, +/* 7316 2356.0 */ 1365, +/* 7317 2356.1 */ 1061, +/* 7318 2356.2 */ 1072, +/* 7319 2356.3 */ 912, +/* 7320 2357.0 */ 1367, +/* 7321 2357.1 */ 1061, +/* 7322 2357.2 */ 1073, +/* 7323 2357.3 */ 1377, +/* 7324 2358.0 */ 1367, +/* 7325 2358.1 */ 1061, +/* 7326 2358.2 */ 1073, +/* 7327 2358.3 */ 1374, +/* 7328 2359.0 */ 1330, +/* 7329 2359.1 */ 1061, +/* 7330 2359.2 */ 1088, +/* 7331 2359.3 */ 1063, +/* 7332 2360.0 */ 1330, +/* 7333 2360.1 */ 1061, +/* 7334 2360.2 */ 1088, +/* 7335 2360.3 */ 1064, +/* 7336 2361.0 */ 1332, +/* 7337 2361.1 */ 1061, +/* 7338 2361.2 */ 1090, +/* 7339 2361.3 */ 1067, +/* 7340 2362.0 */ 1332, +/* 7341 2362.1 */ 1061, +/* 7342 2362.2 */ 1090, +/* 7343 2362.3 */ 1064, +/* 7344 2363.0 */ 1334, +/* 7345 2363.1 */ 1061, +/* 7346 2363.2 */ 1092, +/* 7347 2363.3 */ 1070, +/* 7348 2364.0 */ 1334, +/* 7349 2364.1 */ 1061, +/* 7350 2364.2 */ 1092, +/* 7351 2364.3 */ 1064, +/* 7352 2365.0 */ 1348, +/* 7353 2365.1 */ 1061, +/* 7354 2365.2 */ 1378, +/* 7355 2365.3 */ 1379, +/* 7356 2366.0 */ 1348, +/* 7357 2366.1 */ 1061, +/* 7358 2366.2 */ 1378, +/* 7359 2366.3 */ 517, +/* 7360 2367.0 */ 1352, +/* 7361 2367.1 */ 1061, +/* 7362 2367.2 */ 1380, +/* 7363 2367.3 */ 1381, +/* 7364 2368.0 */ 1352, +/* 7365 2368.1 */ 1061, +/* 7366 2368.2 */ 1380, +/* 7367 2368.3 */ 916, +/* 7368 2369.0 */ 1358, +/* 7369 2369.1 */ 1061, +/* 7370 2369.2 */ 1382, +/* 7371 2369.3 */ 1383, +/* 7372 2370.0 */ 1358, +/* 7373 2370.1 */ 1061, +/* 7374 2370.2 */ 1382, +/* 7375 2370.3 */ 1343, +/* 7376 2371.0 */ 1348, +/* 7377 2371.1 */ 1061, +/* 7378 2371.2 */ 1062, +/* 7379 2371.3 */ 1331, +/* 7380 2372.0 */ 1348, +/* 7381 2372.1 */ 1061, +/* 7382 2372.2 */ 1062, +/* 7383 2372.3 */ 545, +/* 7384 2373.0 */ 1352, +/* 7385 2373.1 */ 1061, +/* 7386 2373.2 */ 1066, +/* 7387 2373.3 */ 1333, +/* 7388 2374.0 */ 1352, +/* 7389 2374.1 */ 1061, +/* 7390 2374.2 */ 1066, +/* 7391 2374.3 */ 943, +/* 7392 2375.0 */ 1358, +/* 7393 2375.1 */ 1061, +/* 7394 2375.2 */ 1069, +/* 7395 2375.3 */ 1335, +/* 7396 2376.0 */ 1358, +/* 7397 2376.1 */ 1061, +/* 7398 2376.2 */ 1069, +/* 7399 2376.3 */ 729, +/* 7400 2377.0 */ 1364, +/* 7401 2377.1 */ 1061, +/* 7402 2377.2 */ 1384, +/* 7403 2377.3 */ 1385, +/* 7404 2378.0 */ 1364, +/* 7405 2378.1 */ 1061, +/* 7406 2378.2 */ 1384, +/* 7407 2378.3 */ 506, +/* 7408 2379.0 */ 1365, +/* 7409 2379.1 */ 1061, +/* 7410 2379.2 */ 1386, +/* 7411 2379.3 */ 1387, +/* 7412 2380.0 */ 1365, +/* 7413 2380.1 */ 1061, +/* 7414 2380.2 */ 1386, +/* 7415 2380.3 */ 909, +/* 7416 2381.0 */ 1367, +/* 7417 2381.1 */ 1061, +/* 7418 2381.2 */ 1388, +/* 7419 2381.3 */ 1389, +/* 7420 2382.0 */ 1367, +/* 7421 2382.1 */ 1061, +/* 7422 2382.2 */ 1388, +/* 7423 2382.3 */ 1369, +/* 7424 2383.0 */ 1370, +/* 7425 2383.1 */ 1061, +/* 7426 2383.2 */ 1071, +/* 7427 2383.3 */ 1375, +/* 7428 2384.0 */ 1370, +/* 7429 2384.1 */ 1061, +/* 7430 2384.2 */ 1071, +/* 7431 2384.3 */ 500, +/* 7432 2385.0 */ 1371, +/* 7433 2385.1 */ 1061, +/* 7434 2385.2 */ 1072, +/* 7435 2385.3 */ 1376, +/* 7436 2386.0 */ 1371, +/* 7437 2386.1 */ 1061, +/* 7438 2386.2 */ 1072, +/* 7439 2386.3 */ 912, +/* 7440 2387.0 */ 1372, +/* 7441 2387.1 */ 1061, +/* 7442 2387.2 */ 1073, +/* 7443 2387.3 */ 1377, +/* 7444 2388.0 */ 1372, +/* 7445 2388.1 */ 1061, +/* 7446 2388.2 */ 1073, +/* 7447 2388.3 */ 1374, +/* 7448 2389.0 */ 1330, +/* 7449 2389.1 */ 1061, +/* 7450 2389.2 */ 1378, +/* 7451 2389.3 */ 1379, +/* 7452 2390.0 */ 1330, +/* 7453 2390.1 */ 1061, +/* 7454 2390.2 */ 1378, +/* 7455 2390.3 */ 517, +/* 7456 2391.0 */ 1332, +/* 7457 2391.1 */ 1061, +/* 7458 2391.2 */ 1380, +/* 7459 2391.3 */ 1381, +/* 7460 2392.0 */ 1332, +/* 7461 2392.1 */ 1061, +/* 7462 2392.2 */ 1380, +/* 7463 2392.3 */ 916, +/* 7464 2393.0 */ 1334, +/* 7465 2393.1 */ 1061, +/* 7466 2393.2 */ 1382, +/* 7467 2393.3 */ 1383, +/* 7468 2394.0 */ 1334, +/* 7469 2394.1 */ 1061, +/* 7470 2394.2 */ 1382, +/* 7471 2394.3 */ 1343, +/* 7472 2395.0 */ 1348, +/* 7473 2395.1 */ 1061, +/* 7474 2395.2 */ 1062, +/* 7475 2395.3 */ 1331, +/* 7476 2395.4 */ 120, +/* 7477 2396.0 */ 1348, +/* 7478 2396.1 */ 1061, +/* 7479 2396.2 */ 1062, +/* 7480 2396.3 */ 545, +/* 7481 2396.4 */ 120, +/* 7482 2397.0 */ 1352, +/* 7483 2397.1 */ 1061, +/* 7484 2397.2 */ 1066, +/* 7485 2397.3 */ 1333, +/* 7486 2397.4 */ 120, +/* 7487 2398.0 */ 1352, +/* 7488 2398.1 */ 1061, +/* 7489 2398.2 */ 1066, +/* 7490 2398.3 */ 943, +/* 7491 2398.4 */ 120, +/* 7492 2399.0 */ 1358, +/* 7493 2399.1 */ 1061, +/* 7494 2399.2 */ 1069, +/* 7495 2399.3 */ 1335, +/* 7496 2399.4 */ 120, +/* 7497 2400.0 */ 1358, +/* 7498 2400.1 */ 1061, +/* 7499 2400.2 */ 1069, +/* 7500 2400.3 */ 729, +/* 7501 2400.4 */ 120, +/* 7502 2401.0 */ 1348, +/* 7503 2401.1 */ 1061, +/* 7504 2401.2 */ 126, +/* 7505 2402.0 */ 1348, +/* 7506 2402.1 */ 1061, +/* 7507 2402.2 */ 963, +/* 7508 2403.0 */ 1352, +/* 7509 2403.1 */ 1061, +/* 7510 2403.2 */ 1349, +/* 7511 2404.0 */ 1352, +/* 7512 2404.1 */ 1061, +/* 7513 2404.2 */ 126, +/* 7514 2405.0 */ 1352, +/* 7515 2405.1 */ 1061, +/* 7516 2405.2 */ 963, +/* 7517 2406.0 */ 1358, +/* 7518 2406.1 */ 1061, +/* 7519 2406.2 */ 1349, +/* 7520 2407.0 */ 1358, +/* 7521 2407.1 */ 1061, +/* 7522 2407.2 */ 126, +/* 7523 2408.0 */ 1358, +/* 7524 2408.1 */ 1061, +/* 7525 2408.2 */ 963, +/* 7526 2409.0 */ 1330, +/* 7527 2409.1 */ 1061, +/* 7528 2409.2 */ 1038, +/* 7529 2410.0 */ 1330, +/* 7530 2410.1 */ 1061, +/* 7531 2410.2 */ 964, +/* 7532 2411.0 */ 1332, +/* 7533 2411.1 */ 1061, +/* 7534 2411.2 */ 1336, +/* 7535 2412.0 */ 1332, +/* 7536 2412.1 */ 1061, +/* 7537 2412.2 */ 1038, +/* 7538 2413.0 */ 1332, +/* 7539 2413.1 */ 1061, +/* 7540 2413.2 */ 964, +/* 7541 2414.0 */ 1334, +/* 7542 2414.1 */ 1061, +/* 7543 2414.2 */ 1336, +/* 7544 2415.0 */ 1334, +/* 7545 2415.1 */ 1061, +/* 7546 2415.2 */ 1038, +/* 7547 2416.0 */ 1334, +/* 7548 2416.1 */ 1061, +/* 7549 2416.2 */ 964, +/* 7550 2417.0 */ 1034, +/* 7551 2417.1 */ 1139, +/* 7552 2417.2 */ 1384, +/* 7553 2417.3 */ 1385, +/* 7554 2417.4 */ 120, +/* 7555 2418.0 */ 1034, +/* 7556 2418.1 */ 1139, +/* 7557 2418.2 */ 1384, +/* 7558 2418.3 */ 506, +/* 7559 2418.4 */ 120, +/* 7560 2419.0 */ 1034, +/* 7561 2419.1 */ 1139, +/* 7562 2419.2 */ 1386, +/* 7563 2419.3 */ 1387, +/* 7564 2419.4 */ 120, +/* 7565 2420.0 */ 1034, +/* 7566 2420.1 */ 1139, +/* 7567 2420.2 */ 1386, +/* 7568 2420.3 */ 909, +/* 7569 2420.4 */ 120, +/* 7570 2421.0 */ 1034, +/* 7571 2421.1 */ 1139, +/* 7572 2421.2 */ 1388, +/* 7573 2421.3 */ 1389, +/* 7574 2421.4 */ 120, +/* 7575 2422.0 */ 1034, +/* 7576 2422.1 */ 1139, +/* 7577 2422.2 */ 1388, +/* 7578 2422.3 */ 1369, +/* 7579 2422.4 */ 120, +/* 7580 2423.0 */ 1034, +/* 7581 2423.1 */ 1139, +/* 7582 2423.2 */ 1062, +/* 7583 2423.3 */ 1331, +/* 7584 2424.0 */ 1034, +/* 7585 2424.1 */ 1139, +/* 7586 2424.2 */ 1062, +/* 7587 2424.3 */ 545, +/* 7588 2425.0 */ 1034, +/* 7589 2425.1 */ 1139, +/* 7590 2425.2 */ 1066, +/* 7591 2425.3 */ 1333, +/* 7592 2426.0 */ 1034, +/* 7593 2426.1 */ 1139, +/* 7594 2426.2 */ 1066, +/* 7595 2426.3 */ 943, +/* 7596 2427.0 */ 1034, +/* 7597 2427.1 */ 1139, +/* 7598 2427.2 */ 1069, +/* 7599 2427.3 */ 1335, +/* 7600 2428.0 */ 1034, +/* 7601 2428.1 */ 1139, +/* 7602 2428.2 */ 1069, +/* 7603 2428.3 */ 729, +/* 7604 2429.0 */ 1034, +/* 7605 2429.1 */ 1139, +/* 7606 2429.2 */ 1378, +/* 7607 2429.3 */ 1379, +/* 7608 2430.0 */ 1034, +/* 7609 2430.1 */ 1139, +/* 7610 2430.2 */ 1378, +/* 7611 2430.3 */ 517, +/* 7612 2431.0 */ 1034, +/* 7613 2431.1 */ 1139, +/* 7614 2431.2 */ 1380, +/* 7615 2431.3 */ 1381, +/* 7616 2432.0 */ 1034, +/* 7617 2432.1 */ 1139, +/* 7618 2432.2 */ 1380, +/* 7619 2432.3 */ 916, +/* 7620 2433.0 */ 1034, +/* 7621 2433.1 */ 1139, +/* 7622 2433.2 */ 1382, +/* 7623 2433.3 */ 1383, +/* 7624 2434.0 */ 1034, +/* 7625 2434.1 */ 1139, +/* 7626 2434.2 */ 1382, +/* 7627 2434.3 */ 1343, +/* 7628 2435.0 */ 1034, +/* 7629 2435.1 */ 1139, +/* 7630 2435.2 */ 1062, +/* 7631 2435.3 */ 1331, +/* 7632 2435.4 */ 120, +/* 7633 2436.0 */ 1034, +/* 7634 2436.1 */ 1139, +/* 7635 2436.2 */ 1062, +/* 7636 2436.3 */ 545, +/* 7637 2436.4 */ 120, +/* 7638 2437.0 */ 1034, +/* 7639 2437.1 */ 1139, +/* 7640 2437.2 */ 1066, +/* 7641 2437.3 */ 1333, +/* 7642 2437.4 */ 120, +/* 7643 2438.0 */ 1034, +/* 7644 2438.1 */ 1139, +/* 7645 2438.2 */ 1066, +/* 7646 2438.3 */ 943, +/* 7647 2438.4 */ 120, +/* 7648 2439.0 */ 1034, +/* 7649 2439.1 */ 1139, +/* 7650 2439.2 */ 1069, +/* 7651 2439.3 */ 1335, +/* 7652 2439.4 */ 120, +/* 7653 2440.0 */ 1034, +/* 7654 2440.1 */ 1139, +/* 7655 2440.2 */ 1069, +/* 7656 2440.3 */ 729, +/* 7657 2440.4 */ 120, +/* 7658 2441.0 */ 1034, +/* 7659 2441.1 */ 1139, +/* 7660 2441.2 */ 1378, +/* 7661 2441.3 */ 1379, +/* 7662 2441.4 */ 120, +/* 7663 2442.0 */ 1034, +/* 7664 2442.1 */ 1139, +/* 7665 2442.2 */ 1378, +/* 7666 2442.3 */ 517, +/* 7667 2442.4 */ 120, +/* 7668 2443.0 */ 1034, +/* 7669 2443.1 */ 1139, +/* 7670 2443.2 */ 1380, +/* 7671 2443.3 */ 1381, +/* 7672 2443.4 */ 120, +/* 7673 2444.0 */ 1034, +/* 7674 2444.1 */ 1139, +/* 7675 2444.2 */ 1380, +/* 7676 2444.3 */ 916, +/* 7677 2444.4 */ 120, +/* 7678 2445.0 */ 1034, +/* 7679 2445.1 */ 1139, +/* 7680 2445.2 */ 1382, +/* 7681 2445.3 */ 1383, +/* 7682 2445.4 */ 120, +/* 7683 2446.0 */ 1034, +/* 7684 2446.1 */ 1139, +/* 7685 2446.2 */ 1382, +/* 7686 2446.3 */ 1343, +/* 7687 2446.4 */ 120, +/* 7688 2447.0 */ 1034, +/* 7689 2447.1 */ 1139, +/* 7690 2447.2 */ 1071, +/* 7691 2447.3 */ 1375, +/* 7692 2447.4 */ 120, +/* 7693 2448.0 */ 1034, +/* 7694 2448.1 */ 1139, +/* 7695 2448.2 */ 1071, +/* 7696 2448.3 */ 500, +/* 7697 2448.4 */ 120, +/* 7698 2449.0 */ 1034, +/* 7699 2449.1 */ 1139, +/* 7700 2449.2 */ 1072, +/* 7701 2449.3 */ 1376, +/* 7702 2449.4 */ 120, +/* 7703 2450.0 */ 1034, +/* 7704 2450.1 */ 1139, +/* 7705 2450.2 */ 1072, +/* 7706 2450.3 */ 912, +/* 7707 2450.4 */ 120, +/* 7708 2451.0 */ 1034, +/* 7709 2451.1 */ 1139, +/* 7710 2451.2 */ 1073, +/* 7711 2451.3 */ 1377, +/* 7712 2451.4 */ 120, +/* 7713 2452.0 */ 1034, +/* 7714 2452.1 */ 1139, +/* 7715 2452.2 */ 1073, +/* 7716 2452.3 */ 1374, +/* 7717 2452.4 */ 120, +/* 7718 2453.0 */ 1390, +/* 7719 2453.1 */ 1061, +/* 7720 2453.2 */ 1378, +/* 7721 2453.3 */ 1379, +/* 7722 2454.0 */ 1390, +/* 7723 2454.1 */ 1061, +/* 7724 2454.2 */ 1378, +/* 7725 2454.3 */ 517, +/* 7726 2455.0 */ 1391, +/* 7727 2455.1 */ 1061, +/* 7728 2455.2 */ 1380, +/* 7729 2455.3 */ 1381, +/* 7730 2456.0 */ 1391, +/* 7731 2456.1 */ 1061, +/* 7732 2456.2 */ 1380, +/* 7733 2456.3 */ 916, +/* 7734 2457.0 */ 1392, +/* 7735 2457.1 */ 1061, +/* 7736 2457.2 */ 1382, +/* 7737 2457.3 */ 1383, +/* 7738 2458.0 */ 1392, +/* 7739 2458.1 */ 1061, +/* 7740 2458.2 */ 1382, +/* 7741 2458.3 */ 1343, +/* 7742 2459.0 */ 1393, +/* 7743 2459.1 */ 1351, +/* 7744 2459.2 */ 120, +/* 7745 2460.0 */ 232, +/* 7746 2460.1 */ 1394, +/* 7747 2460.2 */ 120, +/* 7748 2461.0 */ 685, +/* 7749 2461.1 */ 1225, +/* 7750 2461.2 */ 120, +/* 7751 2462.0 */ 690, +/* 7752 2462.1 */ 1226, +/* 7753 2462.2 */ 120, +/* 7754 2463.0 */ 687, +/* 7755 2463.1 */ 1236, +/* 7756 2463.2 */ 120, +/* 7757 2464.0 */ 692, +/* 7758 2464.1 */ 1250, +/* 7759 2464.2 */ 120, +/* 7760 2465.0 */ 1395, +/* 7761 2465.1 */ 1338, +/* 7762 2465.2 */ 120, +/* 7763 2466.0 */ 1039, +/* 7764 2466.1 */ 1396, +/* 7765 2466.2 */ 120, +/* 7766 2467.0 */ 1397, +/* 7767 2467.1 */ 1398, +/* 7768 2467.2 */ 120, +/* 7769 2468.0 */ 1348, +/* 7770 2468.1 */ 1399, +/* 7771 2468.2 */ 963, +/* 7772 2468.3 */ 120, +/* 7773 2469.0 */ 1348, +/* 7774 2469.1 */ 1399, +/* 7775 2469.2 */ 126, +/* 7776 2469.3 */ 120, +/* 7777 2470.0 */ 1111, +/* 7778 2470.1 */ 1400, +/* 7779 2470.2 */ 965, +/* 7780 2470.3 */ 120, +/* 7781 2471.0 */ 1111, +/* 7782 2471.1 */ 1400, +/* 7783 2471.2 */ 496, +/* 7784 2471.3 */ 120, +/* 7785 2472.0 */ 1118, +/* 7786 2472.1 */ 1401, +/* 7787 2472.2 */ 966, +/* 7788 2472.3 */ 120, +/* 7789 2473.0 */ 1118, +/* 7790 2473.1 */ 1401, +/* 7791 2473.2 */ 538, +/* 7792 2473.3 */ 120, +/* 7793 2474.0 */ 1330, +/* 7794 2474.1 */ 1402, +/* 7795 2474.2 */ 964, +/* 7796 2474.3 */ 120, +/* 7797 2475.0 */ 1330, +/* 7798 2475.1 */ 1402, +/* 7799 2475.2 */ 1038, +/* 7800 2475.3 */ 120, +/* 7801 2476.0 */ 1174, +/* 7802 2476.1 */ 1061, +/* 7803 2476.2 */ 1071, +/* 7804 2476.3 */ 1375, +/* 7805 2477.0 */ 1174, +/* 7806 2477.1 */ 1061, +/* 7807 2477.2 */ 1071, +/* 7808 2477.3 */ 500, +/* 7809 2478.0 */ 1172, +/* 7810 2478.1 */ 1061, +/* 7811 2478.2 */ 1072, +/* 7812 2478.3 */ 1376, +/* 7813 2479.0 */ 1172, +/* 7814 2479.1 */ 1061, +/* 7815 2479.2 */ 1072, +/* 7816 2479.3 */ 912, +/* 7817 2480.0 */ 1181, +/* 7818 2480.1 */ 1061, +/* 7819 2480.2 */ 1073, +/* 7820 2480.3 */ 1377, +/* 7821 2481.0 */ 1181, +/* 7822 2481.1 */ 1061, +/* 7823 2481.2 */ 1073, +/* 7824 2481.3 */ 1374, +/* 7825 2482.0 */ 1034, +/* 7826 2482.1 */ 1403, +/* 7827 2483.0 */ 1034, +/* 7828 2483.1 */ 1404, +/* 7829 2484.0 */ 1034, +/* 7830 2484.1 */ 1405, +/* 7831 2485.0 */ 1034, +/* 7832 2485.1 */ 1406, +/* 7833 2486.0 */ 1034, +/* 7834 2486.1 */ 1407, +/* 7835 2487.0 */ 1034, +/* 7836 2487.1 */ 1408, +/* 7837 2488.0 */ 1348, +/* 7838 2488.1 */ 1042, +/* 7839 2489.0 */ 1352, +/* 7840 2489.1 */ 1042, +/* 7841 2490.0 */ 1358, +/* 7842 2490.1 */ 1042, +/* 7843 2491.0 */ 1111, +/* 7844 2491.1 */ 1042, +/* 7845 2492.0 */ 1113, +/* 7846 2492.1 */ 1042, +/* 7847 2493.0 */ 1109, +/* 7848 2493.1 */ 1042, +/* 7849 2494.0 */ 1118, +/* 7850 2494.1 */ 1042, +/* 7851 2495.0 */ 1120, +/* 7852 2495.1 */ 1042, +/* 7853 2496.0 */ 1115, +/* 7854 2496.1 */ 1042, +/* 7855 2497.0 */ 1330, +/* 7856 2497.1 */ 1042, +/* 7857 2498.0 */ 1332, +/* 7858 2498.1 */ 1042, +/* 7859 2499.0 */ 1334, +/* 7860 2499.1 */ 1042, +/* 7861 2500.0 */ 1034, +/* 7862 2500.1 */ 1251, +/* 7863 2501.0 */ 1034, +/* 7864 2501.1 */ 1409, +/* 7865 2502.0 */ 1034, +/* 7866 2502.1 */ 1410, +/* 7867 2503.0 */ 1290, +/* 7868 2503.1 */ 1061, +/* 7869 2503.2 */ 1411, +/* 7870 2504.0 */ 1298, +/* 7871 2504.1 */ 1148, +/* 7872 2504.2 */ 1412, +/* 7873 2505.0 */ 1290, +/* 7874 2505.1 */ 1061, +/* 7875 2505.2 */ 1413, +/* 7876 2506.0 */ 1292, +/* 7877 2506.1 */ 1148, +/* 7878 2506.2 */ 1414, +/* 7879 2507.0 */ 1415, +/* 7880 2507.1 */ 1061, +/* 7881 2507.2 */ 1416, +/* 7882 2508.0 */ 1417, +/* 7883 2508.1 */ 1148, +/* 7884 2508.2 */ 1418, +/* 7885 2509.0 */ 1370, +/* 7886 2509.1 */ 1061, +/* 7887 2509.2 */ 1316, +/* 7888 2510.0 */ 1370, +/* 7889 2510.1 */ 1061, +/* 7890 2510.2 */ 503, +/* 7891 2511.0 */ 1371, +/* 7892 2511.1 */ 1061, +/* 7893 2511.2 */ 1316, +/* 7894 2512.0 */ 1371, +/* 7895 2512.1 */ 1061, +/* 7896 2512.2 */ 506, +/* 7897 2513.0 */ 1372, +/* 7898 2513.1 */ 1061, +/* 7899 2513.2 */ 1366, +/* 7900 2514.0 */ 1372, +/* 7901 2514.1 */ 1061, +/* 7902 2514.2 */ 909, +/* 7903 2515.0 */ 1279, +/* 7904 2515.1 */ 1061, +/* 7905 2515.2 */ 1337, +/* 7906 2516.0 */ 1282, +/* 7907 2516.1 */ 1148, +/* 7908 2516.2 */ 1338, +/* 7909 2517.0 */ 1279, +/* 7910 2517.1 */ 1061, +/* 7911 2517.2 */ 1340, +/* 7912 2518.0 */ 1280, +/* 7913 2518.1 */ 1148, +/* 7914 2518.2 */ 1341, +/* 7915 2519.0 */ 1354, +/* 7916 2519.1 */ 1061, +/* 7917 2519.2 */ 1345, +/* 7918 2520.0 */ 1356, +/* 7919 2520.1 */ 1148, +/* 7920 2520.2 */ 1347, +/* 7921 2521.0 */ 1034, +/* 7922 2521.1 */ 1398, +/* 7923 2522.0 */ 1034, +/* 7924 2522.1 */ 1419, +/* 7925 2523.0 */ 1034, +/* 7926 2523.1 */ 1420, +/* 7927 2524.0 */ 1330, +/* 7928 2524.1 */ 1399, +/* 7929 2524.2 */ 1349, +/* 7930 2525.0 */ 1330, +/* 7931 2525.1 */ 1399, +/* 7932 2525.2 */ 545, +/* 7933 2526.0 */ 1332, +/* 7934 2526.1 */ 1421, +/* 7935 2526.2 */ 1353, +/* 7936 2527.0 */ 1332, +/* 7937 2527.1 */ 1421, +/* 7938 2527.2 */ 943, +/* 7939 2528.0 */ 1334, +/* 7940 2528.1 */ 1422, +/* 7941 2528.2 */ 1359, +/* 7942 2529.0 */ 1334, +/* 7943 2529.1 */ 1422, +/* 7944 2529.2 */ 729, +/* 7945 2530.0 */ 1330, +/* 7946 2530.1 */ 1061, +/* 7947 2530.2 */ 1336, +/* 7948 2530.3 */ 120, +/* 7949 2531.0 */ 1330, +/* 7950 2531.1 */ 1061, +/* 7951 2531.2 */ 517, +/* 7952 2531.3 */ 120, +/* 7953 2532.0 */ 1332, +/* 7954 2532.1 */ 1061, +/* 7955 2532.2 */ 1339, +/* 7956 2532.3 */ 120, +/* 7957 2533.0 */ 1332, +/* 7958 2533.1 */ 1061, +/* 7959 2533.2 */ 916, +/* 7960 2533.3 */ 120, +/* 7961 2534.0 */ 1334, +/* 7962 2534.1 */ 1061, +/* 7963 2534.2 */ 1342, +/* 7964 2534.3 */ 120, +/* 7965 2535.0 */ 1334, +/* 7966 2535.1 */ 1061, +/* 7967 2535.2 */ 1343, +/* 7968 2535.3 */ 120, +/* 7969 2536.0 */ 1423, +/* 7970 2536.1 */ 1403, +/* 7971 2536.2 */ 120, +/* 7972 2537.0 */ 1423, +/* 7973 2537.1 */ 545, +/* 7974 2537.2 */ 120, +/* 7975 2538.0 */ 1424, +/* 7976 2538.1 */ 1404, +/* 7977 2538.2 */ 120, +/* 7978 2539.0 */ 1424, +/* 7979 2539.1 */ 943, +/* 7980 2539.2 */ 120, +/* 7981 2540.0 */ 1425, +/* 7982 2540.1 */ 1405, +/* 7983 2540.2 */ 120, +/* 7984 2541.0 */ 1425, +/* 7985 2541.1 */ 729, +/* 7986 2541.2 */ 120, +/* 7987 2542.0 */ 1426, +/* 7988 2542.1 */ 1061, +/* 7989 2542.2 */ 1336, +/* 7990 2542.3 */ 120, +/* 7991 2543.0 */ 1426, +/* 7992 2543.1 */ 1061, +/* 7993 2543.2 */ 517, +/* 7994 2543.3 */ 120, +/* 7995 2544.0 */ 1332, +/* 7996 2544.1 */ 1061, +/* 7997 2544.2 */ 1380, +/* 7998 2544.3 */ 1379, +/* 7999 2545.0 */ 1332, +/* 8000 2545.1 */ 1061, +/* 8001 2545.2 */ 1380, +/* 8002 2545.3 */ 517, +/* 8003 2546.0 */ 1427, +/* 8004 2546.1 */ 1061, +/* 8005 2546.2 */ 1339, +/* 8006 2546.3 */ 120, +/* 8007 2547.0 */ 1427, +/* 8008 2547.1 */ 1061, +/* 8009 2547.2 */ 916, +/* 8010 2547.3 */ 120, +/* 8011 2548.0 */ 1334, +/* 8012 2548.1 */ 1061, +/* 8013 2548.2 */ 1382, +/* 8014 2548.3 */ 1379, +/* 8015 2549.0 */ 1334, +/* 8016 2549.1 */ 1061, +/* 8017 2549.2 */ 1382, +/* 8018 2549.3 */ 517, +/* 8019 2550.0 */ 1428, +/* 8020 2550.1 */ 1061, +/* 8021 2550.2 */ 1342, +/* 8022 2550.3 */ 120, +/* 8023 2551.0 */ 1428, +/* 8024 2551.1 */ 1061, +/* 8025 2551.2 */ 1343, +/* 8026 2551.3 */ 120, +/* 8027 2552.0 */ 1095, +/* 8028 2552.1 */ 1061, +/* 8029 2552.2 */ 1122, +/* 8030 2552.3 */ 1123, +/* 8031 2552.4 */ 120, +/* 8032 2553.0 */ 1098, +/* 8033 2553.1 */ 1061, +/* 8034 2553.2 */ 1082, +/* 8035 2553.3 */ 1083, +/* 8036 2553.4 */ 120, +/* 8037 2554.0 */ 1429, +/* 8038 2554.1 */ 1061, +/* 8039 2554.2 */ 1062, +/* 8040 2554.3 */ 1331, +/* 8041 2555.0 */ 1429, +/* 8042 2555.1 */ 1061, +/* 8043 2555.2 */ 1062, +/* 8044 2555.3 */ 545, +/* 8045 2556.0 */ 1430, +/* 8046 2556.1 */ 1061, +/* 8047 2556.2 */ 1066, +/* 8048 2556.3 */ 1333, +/* 8049 2557.0 */ 1430, +/* 8050 2557.1 */ 1061, +/* 8051 2557.2 */ 1066, +/* 8052 2557.3 */ 943, +/* 8053 2558.0 */ 1431, +/* 8054 2558.1 */ 1061, +/* 8055 2558.2 */ 1069, +/* 8056 2558.3 */ 1335, +/* 8057 2559.0 */ 1431, +/* 8058 2559.1 */ 1061, +/* 8059 2559.2 */ 1069, +/* 8060 2559.3 */ 729, +/* 8061 2560.0 */ 1348, +/* 8062 2560.1 */ 1061, +/* 8063 2560.2 */ 1062, +/* 8064 2560.3 */ 1135, +/* 8065 2561.0 */ 1348, +/* 8066 2561.1 */ 1061, +/* 8067 2561.2 */ 1062, +/* 8068 2561.3 */ 1117, +/* 8069 2562.0 */ 1352, +/* 8070 2562.1 */ 1061, +/* 8071 2562.2 */ 1066, +/* 8072 2562.3 */ 1137, +/* 8073 2563.0 */ 1352, +/* 8074 2563.1 */ 1061, +/* 8075 2563.2 */ 1066, +/* 8076 2563.3 */ 1117, +/* 8077 2564.0 */ 1358, +/* 8078 2564.1 */ 1061, +/* 8079 2564.2 */ 1069, +/* 8080 2564.3 */ 1133, +/* 8081 2565.0 */ 1358, +/* 8082 2565.1 */ 1061, +/* 8083 2565.2 */ 1069, +/* 8084 2565.3 */ 1117, +/* 8085 2566.0 */ 1034, +/* 8086 2566.1 */ 1139, +/* 8087 2566.2 */ 1134, +/* 8088 2566.3 */ 1331, +/* 8089 2567.0 */ 1034, +/* 8090 2567.1 */ 1139, +/* 8091 2567.2 */ 1134, +/* 8092 2567.3 */ 545, +/* 8093 2568.0 */ 1034, +/* 8094 2568.1 */ 1139, +/* 8095 2568.2 */ 1136, +/* 8096 2568.3 */ 1333, +/* 8097 2569.0 */ 1034, +/* 8098 2569.1 */ 1139, +/* 8099 2569.2 */ 1136, +/* 8100 2569.3 */ 943, +/* 8101 2570.0 */ 1034, +/* 8102 2570.1 */ 1139, +/* 8103 2570.2 */ 1132, +/* 8104 2570.3 */ 1335, +/* 8105 2571.0 */ 1034, +/* 8106 2571.1 */ 1139, +/* 8107 2571.2 */ 1132, +/* 8108 2571.3 */ 729, +/* 8109 2572.0 */ 1330, +/* 8110 2572.1 */ 1061, +/* 8111 2572.2 */ 1378, +/* 8112 2572.3 */ 1379, +/* 8113 2572.4 */ 120, +/* 8114 2573.0 */ 1330, +/* 8115 2573.1 */ 1061, +/* 8116 2573.2 */ 1378, +/* 8117 2573.3 */ 517, +/* 8118 2573.4 */ 120, +/* 8119 2574.0 */ 1332, +/* 8120 2574.1 */ 1061, +/* 8121 2574.2 */ 1380, +/* 8122 2574.3 */ 1381, +/* 8123 2574.4 */ 120, +/* 8124 2575.0 */ 1332, +/* 8125 2575.1 */ 1061, +/* 8126 2575.2 */ 1380, +/* 8127 2575.3 */ 916, +/* 8128 2575.4 */ 120, +/* 8129 2576.0 */ 1334, +/* 8130 2576.1 */ 1061, +/* 8131 2576.2 */ 1382, +/* 8132 2576.3 */ 1383, +/* 8133 2576.4 */ 120, +/* 8134 2577.0 */ 1334, +/* 8135 2577.1 */ 1061, +/* 8136 2577.2 */ 1382, +/* 8137 2577.3 */ 1343, +/* 8138 2577.4 */ 120, +/* 8139 2578.0 */ 1348, +/* 8140 2578.1 */ 1061, +/* 8141 2578.2 */ 1062, +/* 8142 2578.3 */ 1135, +/* 8143 2578.4 */ 120, +/* 8144 2579.0 */ 1348, +/* 8145 2579.1 */ 1061, +/* 8146 2579.2 */ 1062, +/* 8147 2579.3 */ 1117, +/* 8148 2579.4 */ 120, +/* 8149 2580.0 */ 1352, +/* 8150 2580.1 */ 1061, +/* 8151 2580.2 */ 1066, +/* 8152 2580.3 */ 1137, +/* 8153 2580.4 */ 120, +/* 8154 2581.0 */ 1352, +/* 8155 2581.1 */ 1061, +/* 8156 2581.2 */ 1066, +/* 8157 2581.3 */ 1117, +/* 8158 2581.4 */ 120, +/* 8159 2582.0 */ 1358, +/* 8160 2582.1 */ 1061, +/* 8161 2582.2 */ 1069, +/* 8162 2582.3 */ 1133, +/* 8163 2582.4 */ 120, +/* 8164 2583.0 */ 1358, +/* 8165 2583.1 */ 1061, +/* 8166 2583.2 */ 1069, +/* 8167 2583.3 */ 1117, +/* 8168 2583.4 */ 120, +/* 8169 2584.0 */ 1432, +/* 8170 2584.1 */ 1433, +/* 8171 2584.2 */ 1434, +/* 8172 2585.0 */ 1432, +/* 8173 2585.1 */ 1433, +/* 8174 2585.2 */ 902, +/* 8175 2586.0 */ 1435, +/* 8176 2586.1 */ 1436, +/* 8177 2586.2 */ 1437, +/* 8178 2587.0 */ 1435, +/* 8179 2587.1 */ 1436, +/* 8180 2587.2 */ 983, +/* 8181 2588.0 */ 1438, +/* 8182 2588.1 */ 1439, +/* 8183 2588.2 */ 1440, +/* 8184 2589.0 */ 1438, +/* 8185 2589.1 */ 1439, +/* 8186 2589.2 */ 1441, +/* 8187 2590.0 */ 1432, +/* 8188 2590.1 */ 1401, +/* 8189 2590.2 */ 1119, +/* 8190 2590.3 */ 120, +/* 8191 2591.0 */ 1432, +/* 8192 2591.1 */ 1401, +/* 8193 2591.2 */ 253, +/* 8194 2591.3 */ 120, +/* 8195 2592.0 */ 1435, +/* 8196 2592.1 */ 1442, +/* 8197 2592.2 */ 1121, +/* 8198 2592.3 */ 120, +/* 8199 2593.0 */ 1435, +/* 8200 2593.1 */ 1442, +/* 8201 2593.2 */ 860, +/* 8202 2593.3 */ 120, +/* 8203 2594.0 */ 1438, +/* 8204 2594.1 */ 1443, +/* 8205 2594.2 */ 1116, +/* 8206 2594.3 */ 120, +/* 8207 2595.0 */ 1438, +/* 8208 2595.1 */ 1443, +/* 8209 2595.2 */ 1231, +/* 8210 2595.3 */ 120, +/* 8211 2596.0 */ 1444, +/* 8212 2596.1 */ 1400, +/* 8213 2596.2 */ 1112, +/* 8214 2597.0 */ 1444, +/* 8215 2597.1 */ 1400, +/* 8216 2597.2 */ 1064, +/* 8217 2598.0 */ 1444, +/* 8218 2598.1 */ 1445, +/* 8219 2598.2 */ 1114, +/* 8220 2599.0 */ 1444, +/* 8221 2599.1 */ 1445, +/* 8222 2599.2 */ 1064, +/* 8223 2600.0 */ 1444, +/* 8224 2600.1 */ 1446, +/* 8225 2600.2 */ 1110, +/* 8226 2601.0 */ 1444, +/* 8227 2601.1 */ 1446, +/* 8228 2601.2 */ 1064, +/* 8229 2602.0 */ 1444, +/* 8230 2602.1 */ 1401, +/* 8231 2602.2 */ 1119, +/* 8232 2603.0 */ 1444, +/* 8233 2603.1 */ 1401, +/* 8234 2603.2 */ 1117, +/* 8235 2604.0 */ 1444, +/* 8236 2604.1 */ 1442, +/* 8237 2604.2 */ 1121, +/* 8238 2605.0 */ 1444, +/* 8239 2605.1 */ 1442, +/* 8240 2605.2 */ 1117, +/* 8241 2606.0 */ 1444, +/* 8242 2606.1 */ 1443, +/* 8243 2606.2 */ 1116, +/* 8244 2607.0 */ 1444, +/* 8245 2607.1 */ 1443, +/* 8246 2607.2 */ 1117, +/* 8247 2608.0 */ 1447, +/* 8248 2608.1 */ 1061, +/* 8249 2608.2 */ 1448, +/* 8250 2608.3 */ 1449, +/* 8251 2609.0 */ 1447, +/* 8252 2609.1 */ 1061, +/* 8253 2609.2 */ 1448, +/* 8254 2609.3 */ 1450, +/* 8255 2610.0 */ 1451, +/* 8256 2610.1 */ 1061, +/* 8257 2610.2 */ 1452, +/* 8258 2610.3 */ 1453, +/* 8259 2611.0 */ 1451, +/* 8260 2611.1 */ 1061, +/* 8261 2611.2 */ 1452, +/* 8262 2611.3 */ 1450, +/* 8263 2612.0 */ 1454, +/* 8264 2612.1 */ 1061, +/* 8265 2612.2 */ 1455, +/* 8266 2612.3 */ 1456, +/* 8267 2613.0 */ 1457, +/* 8268 2613.1 */ 1061, +/* 8269 2613.2 */ 1455, +/* 8270 2613.3 */ 1456, +/* 8271 2614.0 */ 1454, +/* 8272 2614.1 */ 1061, +/* 8273 2614.2 */ 1455, +/* 8274 2614.3 */ 1450, +/* 8275 2615.0 */ 1458, +/* 8276 2615.1 */ 1061, +/* 8277 2615.2 */ 1448, +/* 8278 2615.3 */ 1449, +/* 8279 2616.0 */ 1447, +/* 8280 2616.1 */ 1061, +/* 8281 2616.2 */ 1448, +/* 8282 2616.3 */ 1459, +/* 8283 2617.0 */ 1034, +/* 8284 2617.1 */ 1139, +/* 8285 2617.2 */ 1448, +/* 8286 2617.3 */ 1449, +/* 8287 2617.4 */ 120, +/* 8288 2618.0 */ 1034, +/* 8289 2618.1 */ 1139, +/* 8290 2618.2 */ 1448, +/* 8291 2618.3 */ 1450, +/* 8292 2618.4 */ 120, +/* 8293 2619.0 */ 1034, +/* 8294 2619.1 */ 1139, +/* 8295 2619.2 */ 1452, +/* 8296 2619.3 */ 1453, +/* 8297 2619.4 */ 120, +/* 8298 2620.0 */ 1034, +/* 8299 2620.1 */ 1139, +/* 8300 2620.2 */ 1452, +/* 8301 2620.3 */ 1450, +/* 8302 2620.4 */ 120, +/* 8303 2621.0 */ 1034, +/* 8304 2621.1 */ 1139, +/* 8305 2621.2 */ 1455, +/* 8306 2621.3 */ 1456, +/* 8307 2621.4 */ 120, +/* 8308 2622.0 */ 1140, +/* 8309 2622.1 */ 1139, +/* 8310 2622.2 */ 1455, +/* 8311 2622.3 */ 1456, +/* 8312 2622.4 */ 120, +/* 8313 2623.0 */ 1034, +/* 8314 2623.1 */ 1139, +/* 8315 2623.2 */ 1455, +/* 8316 2623.3 */ 1450, +/* 8317 2623.4 */ 120, +/* 8318 2624.0 */ 1140, +/* 8319 2624.1 */ 1139, +/* 8320 2624.2 */ 1448, +/* 8321 2624.3 */ 1449, +/* 8322 2624.4 */ 120, +/* 8323 2625.0 */ 1034, +/* 8324 2625.1 */ 1139, +/* 8325 2625.2 */ 1448, +/* 8326 2625.3 */ 1459, +/* 8327 2625.4 */ 120, +/* 8328 2626.0 */ 1460, +/* 8329 2626.1 */ 1461, +/* 8330 2626.2 */ 123, +/* 8331 2627.0 */ 1462, +/* 8332 2627.1 */ 1461, +/* 8333 2627.2 */ 123, +/* 8334 2628.0 */ 1460, +/* 8335 2628.1 */ 1459, +/* 8336 2628.2 */ 117, +/* 8337 2629.0 */ 1447, +/* 8338 2629.1 */ 1061, +/* 8339 2629.2 */ 1170, +/* 8340 2630.0 */ 1447, +/* 8341 2630.1 */ 1061, +/* 8342 2630.2 */ 1169, +/* 8343 2631.0 */ 1447, +/* 8344 2631.1 */ 1061, +/* 8345 2631.2 */ 1168, +/* 8346 2632.0 */ 1451, +/* 8347 2632.1 */ 1061, +/* 8348 2632.2 */ 1171, +/* 8349 2633.0 */ 1463, +/* 8350 2633.1 */ 1061, +/* 8351 2633.2 */ 1171, +/* 8352 2634.0 */ 1451, +/* 8353 2634.1 */ 1061, +/* 8354 2634.2 */ 1169, +/* 8355 2635.0 */ 1447, +/* 8356 2635.1 */ 1061, +/* 8357 2635.2 */ 1138, +/* 8358 2636.0 */ 1447, +/* 8359 2636.1 */ 1061, +/* 8360 2636.2 */ 1096, +/* 8361 2637.0 */ 1447, +/* 8362 2637.1 */ 1061, +/* 8363 2637.2 */ 1175, +/* 8364 2638.0 */ 1447, +/* 8365 2638.1 */ 1061, +/* 8366 2638.2 */ 1094, +/* 8367 2639.0 */ 1458, +/* 8368 2639.1 */ 1061, +/* 8369 2639.2 */ 1094, +/* 8370 2640.0 */ 1174, +/* 8371 2640.1 */ 1061, +/* 8372 2640.2 */ 1180, +/* 8373 2641.0 */ 1174, +/* 8374 2641.1 */ 1061, +/* 8375 2641.2 */ 1450, +/* 8376 2642.0 */ 1172, +/* 8377 2642.1 */ 1061, +/* 8378 2642.2 */ 1180, +/* 8379 2643.0 */ 1172, +/* 8380 2643.1 */ 1061, +/* 8381 2643.2 */ 1450, +/* 8382 2644.0 */ 1181, +/* 8383 2644.1 */ 1061, +/* 8384 2644.2 */ 1178, +/* 8385 2645.0 */ 1182, +/* 8386 2645.1 */ 1061, +/* 8387 2645.2 */ 1178, +/* 8388 2646.0 */ 1181, +/* 8389 2646.1 */ 1061, +/* 8390 2646.2 */ 1450, +/* 8391 2647.0 */ 1100, +/* 8392 2647.1 */ 1061, +/* 8393 2647.2 */ 1180, +/* 8394 2648.0 */ 1100, +/* 8395 2648.1 */ 1061, +/* 8396 2648.2 */ 1450, +/* 8397 2649.0 */ 1125, +/* 8398 2649.1 */ 1061, +/* 8399 2649.2 */ 1180, +/* 8400 2650.0 */ 1125, +/* 8401 2650.1 */ 1061, +/* 8402 2650.2 */ 1450, +/* 8403 2651.0 */ 1093, +/* 8404 2651.1 */ 1061, +/* 8405 2651.2 */ 1180, +/* 8406 2652.0 */ 1095, +/* 8407 2652.1 */ 1061, +/* 8408 2652.2 */ 1180, +/* 8409 2653.0 */ 1093, +/* 8410 2653.1 */ 1061, +/* 8411 2653.2 */ 1450, +/* 8412 2654.0 */ 1104, +/* 8413 2654.1 */ 1061, +/* 8414 2654.2 */ 1450, +/* 8415 2655.0 */ 1129, +/* 8416 2655.1 */ 1061, +/* 8417 2655.2 */ 1450, +/* 8418 2656.0 */ 1097, +/* 8419 2656.1 */ 1061, +/* 8420 2656.2 */ 1450, +/* 8421 2657.0 */ 1257, +/* 8422 2657.1 */ 1061, +/* 8423 2657.2 */ 1180, +/* 8424 2658.0 */ 1257, +/* 8425 2658.1 */ 1061, +/* 8426 2658.2 */ 1450, +/* 8427 2659.0 */ 1259, +/* 8428 2659.1 */ 1061, +/* 8429 2659.2 */ 1180, +/* 8430 2660.0 */ 1259, +/* 8431 2660.1 */ 1061, +/* 8432 2660.2 */ 1450, +/* 8433 2661.0 */ 1254, +/* 8434 2661.1 */ 1061, +/* 8435 2661.2 */ 1180, +/* 8436 2662.0 */ 1326, +/* 8437 2662.1 */ 1061, +/* 8438 2662.2 */ 1180, +/* 8439 2663.0 */ 1254, +/* 8440 2663.1 */ 1061, +/* 8441 2663.2 */ 1450, +/* 8442 2664.0 */ 1111, +/* 8443 2664.1 */ 1061, +/* 8444 2664.2 */ 1180, +/* 8445 2665.0 */ 1111, +/* 8446 2665.1 */ 1061, +/* 8447 2665.2 */ 1450, +/* 8448 2666.0 */ 1113, +/* 8449 2666.1 */ 1061, +/* 8450 2666.2 */ 1180, +/* 8451 2667.0 */ 1113, +/* 8452 2667.1 */ 1061, +/* 8453 2667.2 */ 1450, +/* 8454 2668.0 */ 1109, +/* 8455 2668.1 */ 1061, +/* 8456 2668.2 */ 1178, +/* 8457 2669.0 */ 1187, +/* 8458 2669.1 */ 1061, +/* 8459 2669.2 */ 1178, +/* 8460 2670.0 */ 1109, +/* 8461 2670.1 */ 1061, +/* 8462 2670.2 */ 1450, +/* 8463 2671.0 */ 1118, +/* 8464 2671.1 */ 1061, +/* 8465 2671.2 */ 1180, +/* 8466 2672.0 */ 1118, +/* 8467 2672.1 */ 1061, +/* 8468 2672.2 */ 1450, +/* 8469 2673.0 */ 1120, +/* 8470 2673.1 */ 1061, +/* 8471 2673.2 */ 1180, +/* 8472 2674.0 */ 1120, +/* 8473 2674.1 */ 1061, +/* 8474 2674.2 */ 1450, +/* 8475 2675.0 */ 1115, +/* 8476 2675.1 */ 1061, +/* 8477 2675.2 */ 1180, +/* 8478 2676.0 */ 1327, +/* 8479 2676.1 */ 1061, +/* 8480 2676.2 */ 1180, +/* 8481 2677.0 */ 1115, +/* 8482 2677.1 */ 1061, +/* 8483 2677.2 */ 1450, +/* 8484 2678.0 */ 1330, +/* 8485 2678.1 */ 1061, +/* 8486 2678.2 */ 1180, +/* 8487 2679.0 */ 1330, +/* 8488 2679.1 */ 1061, +/* 8489 2679.2 */ 1450, +/* 8490 2680.0 */ 1332, +/* 8491 2680.1 */ 1061, +/* 8492 2680.2 */ 1178, +/* 8493 2681.0 */ 1332, +/* 8494 2681.1 */ 1061, +/* 8495 2681.2 */ 1450, +/* 8496 2682.0 */ 1334, +/* 8497 2682.1 */ 1061, +/* 8498 2682.2 */ 1464, +/* 8499 2683.0 */ 1465, +/* 8500 2683.1 */ 1061, +/* 8501 2683.2 */ 1464, +/* 8502 2684.0 */ 1334, +/* 8503 2684.1 */ 1061, +/* 8504 2684.2 */ 1450, +/* 8505 2685.0 */ 1370, +/* 8506 2685.1 */ 1061, +/* 8507 2685.2 */ 1180, +/* 8508 2686.0 */ 1370, +/* 8509 2686.1 */ 1061, +/* 8510 2686.2 */ 1450, +/* 8511 2687.0 */ 1371, +/* 8512 2687.1 */ 1061, +/* 8513 2687.2 */ 1178, +/* 8514 2688.0 */ 1371, +/* 8515 2688.1 */ 1061, +/* 8516 2688.2 */ 1450, +/* 8517 2689.0 */ 1372, +/* 8518 2689.1 */ 1061, +/* 8519 2689.2 */ 1464, +/* 8520 2690.0 */ 1466, +/* 8521 2690.1 */ 1061, +/* 8522 2690.2 */ 1464, +/* 8523 2691.0 */ 1372, +/* 8524 2691.1 */ 1061, +/* 8525 2691.2 */ 1450, +/* 8526 2692.0 */ 1447, +/* 8527 2692.1 */ 1061, +/* 8528 2692.2 */ 1084, +/* 8529 2693.0 */ 1447, +/* 8530 2693.1 */ 1061, +/* 8531 2693.2 */ 1077, +/* 8532 2694.0 */ 1447, +/* 8533 2694.1 */ 1061, +/* 8534 2694.2 */ 1085, +/* 8535 2695.0 */ 1451, +/* 8536 2695.1 */ 1061, +/* 8537 2695.2 */ 1086, +/* 8538 2696.0 */ 1463, +/* 8539 2696.1 */ 1061, +/* 8540 2696.2 */ 1086, +/* 8541 2697.0 */ 1451, +/* 8542 2697.1 */ 1061, +/* 8543 2697.2 */ 1077, +/* 8544 2698.0 */ 1447, +/* 8545 2698.1 */ 1061, +/* 8546 2698.2 */ 1119, +/* 8547 2699.0 */ 1447, +/* 8548 2699.1 */ 1061, +/* 8549 2699.2 */ 1117, +/* 8550 2700.0 */ 1447, +/* 8551 2700.1 */ 1061, +/* 8552 2700.2 */ 1121, +/* 8553 2701.0 */ 1447, +/* 8554 2701.1 */ 1061, +/* 8555 2701.2 */ 1116, +/* 8556 2702.0 */ 1458, +/* 8557 2702.1 */ 1061, +/* 8558 2702.2 */ 1116, +/* 8559 2703.0 */ 1447, +/* 8560 2703.1 */ 1061, +/* 8561 2703.2 */ 1101, +/* 8562 2703.3 */ 1102, +/* 8563 2704.0 */ 1458, +/* 8564 2704.1 */ 1061, +/* 8565 2704.2 */ 1101, +/* 8566 2704.3 */ 1102, +/* 8567 2705.0 */ 1447, +/* 8568 2705.1 */ 1061, +/* 8569 2705.2 */ 1101, +/* 8570 2705.3 */ 812, +/* 8571 2706.0 */ 1100, +/* 8572 2706.1 */ 1061, +/* 8573 2706.2 */ 1101, +/* 8574 2706.3 */ 1449, +/* 8575 2707.0 */ 1103, +/* 8576 2707.1 */ 1061, +/* 8577 2707.2 */ 1101, +/* 8578 2707.3 */ 1449, +/* 8579 2708.0 */ 1100, +/* 8580 2708.1 */ 1061, +/* 8581 2708.2 */ 1101, +/* 8582 2708.3 */ 1459, +/* 8583 2709.0 */ 560, +/* 8584 2709.1 */ 1461, +/* 8585 2710.0 */ 1188, +/* 8586 2710.1 */ 1461, +/* 8587 2711.0 */ 560, +/* 8588 2711.1 */ 1459, +/* 8589 2712.0 */ 561, +/* 8590 2712.1 */ 1461, +/* 8591 2713.0 */ 1189, +/* 8592 2713.1 */ 1461, +/* 8593 2714.0 */ 561, +/* 8594 2714.1 */ 1459, +/* 8595 2715.0 */ 1104, +/* 8596 2715.1 */ 1061, +/* 8597 2715.2 */ 1075, +/* 8598 2715.3 */ 1449, +/* 8599 2716.0 */ 1105, +/* 8600 2716.1 */ 1061, +/* 8601 2716.2 */ 1075, +/* 8602 2716.3 */ 1449, +/* 8603 2717.0 */ 1104, +/* 8604 2717.1 */ 1061, +/* 8605 2717.2 */ 1075, +/* 8606 2717.3 */ 1459, +/* 8607 2718.0 */ 955, +/* 8608 2718.1 */ 1461, +/* 8609 2719.0 */ 1190, +/* 8610 2719.1 */ 1461, +/* 8611 2720.0 */ 955, +/* 8612 2720.1 */ 1459, +/* 8613 2721.0 */ 1047, +/* 8614 2721.1 */ 1461, +/* 8615 2722.0 */ 1191, +/* 8616 2722.1 */ 1461, +/* 8617 2723.0 */ 1047, +/* 8618 2723.1 */ 1459, +/* 8619 2724.0 */ 1447, +/* 8620 2724.1 */ 1467, +/* 8621 2724.2 */ 869, +/* 8622 2725.0 */ 1458, +/* 8623 2725.1 */ 1467, +/* 8624 2725.2 */ 869, +/* 8625 2726.0 */ 1447, +/* 8626 2726.1 */ 1467, +/* 8627 2726.2 */ 269, +/* 8628 2727.0 */ 1447, +/* 8629 2727.1 */ 1467, +/* 8630 2727.2 */ 870, +/* 8631 2728.0 */ 1458, +/* 8632 2728.1 */ 1467, +/* 8633 2728.2 */ 870, +/* 8634 2729.0 */ 1447, +/* 8635 2729.1 */ 1467, +/* 8636 2729.2 */ 219, +/* 8637 2730.0 */ 1447, +/* 8638 2730.1 */ 1061, +/* 8639 2730.2 */ 1448, +/* 8640 2730.3 */ 1076, +/* 8641 2731.0 */ 1458, +/* 8642 2731.1 */ 1061, +/* 8643 2731.2 */ 1448, +/* 8644 2731.3 */ 1076, +/* 8645 2732.0 */ 1447, +/* 8646 2732.1 */ 1061, +/* 8647 2732.2 */ 1448, +/* 8648 2732.3 */ 810, +/* 8649 2733.0 */ 1196, +/* 8650 2733.1 */ 1061, +/* 8651 2733.2 */ 1178, +/* 8652 2734.0 */ 1328, +/* 8653 2734.1 */ 1061, +/* 8654 2734.2 */ 1180, +/* 8655 2735.0 */ 1197, +/* 8656 2735.1 */ 1061, +/* 8657 2735.2 */ 1178, +/* 8658 2736.0 */ 1329, +/* 8659 2736.1 */ 1061, +/* 8660 2736.2 */ 1180, +/* 8661 2737.0 */ 1468, +/* 8662 2737.1 */ 1061, +/* 8663 2737.2 */ 1464, +/* 8664 2738.0 */ 1469, +/* 8665 2738.1 */ 1061, +/* 8666 2738.2 */ 1464, +/* 8667 2739.0 */ 1198, +/* 8668 2739.1 */ 1461, +/* 8669 2740.0 */ 1199, +/* 8670 2740.1 */ 1461, +/* 8671 2741.0 */ 1200, +/* 8672 2741.1 */ 1461, +/* 8673 2742.0 */ 1201, +/* 8674 2742.1 */ 1461, +/* 8675 2743.0 */ 1447, +/* 8676 2743.1 */ 1061, +/* 8677 2743.2 */ 1112, +/* 8678 2744.0 */ 1447, +/* 8679 2744.1 */ 1061, +/* 8680 2744.2 */ 1064, +/* 8681 2745.0 */ 1447, +/* 8682 2745.1 */ 1061, +/* 8683 2745.2 */ 1114, +/* 8684 2746.0 */ 1451, +/* 8685 2746.1 */ 1061, +/* 8686 2746.2 */ 1110, +/* 8687 2747.0 */ 1463, +/* 8688 2747.1 */ 1061, +/* 8689 2747.2 */ 1110, +/* 8690 2748.0 */ 1451, +/* 8691 2748.1 */ 1061, +/* 8692 2748.2 */ 1064, +/* 8693 2749.0 */ 1447, +/* 8694 2749.1 */ 1467, +/* 8695 2749.2 */ 965, +/* 8696 2750.0 */ 1458, +/* 8697 2750.1 */ 1467, +/* 8698 2750.2 */ 965, +/* 8699 2751.0 */ 1447, +/* 8700 2751.1 */ 1467, +/* 8701 2751.2 */ 496, +/* 8702 2752.0 */ 1447, +/* 8703 2752.1 */ 1467, +/* 8704 2752.2 */ 966, +/* 8705 2753.0 */ 1458, +/* 8706 2753.1 */ 1467, +/* 8707 2753.2 */ 966, +/* 8708 2754.0 */ 1447, +/* 8709 2754.1 */ 1467, +/* 8710 2754.2 */ 538, +/* 8711 2755.0 */ 1447, +/* 8712 2755.1 */ 1061, +/* 8713 2755.2 */ 1336, +/* 8714 2756.0 */ 1447, +/* 8715 2756.1 */ 1061, +/* 8716 2756.2 */ 1470, +/* 8717 2757.0 */ 1451, +/* 8718 2757.1 */ 1061, +/* 8719 2757.2 */ 1339, +/* 8720 2758.0 */ 1451, +/* 8721 2758.1 */ 1061, +/* 8722 2758.2 */ 1470, +/* 8723 2759.0 */ 1454, +/* 8724 2759.1 */ 1061, +/* 8725 2759.2 */ 1342, +/* 8726 2760.0 */ 1457, +/* 8727 2760.1 */ 1061, +/* 8728 2760.2 */ 1342, +/* 8729 2761.0 */ 1454, +/* 8730 2761.1 */ 1061, +/* 8731 2761.2 */ 1470, +/* 8732 2762.0 */ 1447, +/* 8733 2762.1 */ 1061, +/* 8734 2762.2 */ 1319, +/* 8735 2763.0 */ 1447, +/* 8736 2763.1 */ 1061, +/* 8737 2763.2 */ 1471, +/* 8738 2764.0 */ 1451, +/* 8739 2764.1 */ 1061, +/* 8740 2764.2 */ 1318, +/* 8741 2765.0 */ 1451, +/* 8742 2765.1 */ 1061, +/* 8743 2765.2 */ 1471, +/* 8744 2766.0 */ 1454, +/* 8745 2766.1 */ 1061, +/* 8746 2766.2 */ 1373, +/* 8747 2767.0 */ 1457, +/* 8748 2767.1 */ 1061, +/* 8749 2767.2 */ 1373, +/* 8750 2768.0 */ 1454, +/* 8751 2768.1 */ 1061, +/* 8752 2768.2 */ 1471, +/* 8753 2769.0 */ 1472, +/* 8754 2769.1 */ 1061, +/* 8755 2769.2 */ 1473, +/* 8756 2769.3 */ 1474, +/* 8757 2770.0 */ 1472, +/* 8758 2770.1 */ 1061, +/* 8759 2770.2 */ 1473, +/* 8760 2770.3 */ 1475, +/* 8761 2771.0 */ 1476, +/* 8762 2771.1 */ 1061, +/* 8763 2771.2 */ 1477, +/* 8764 2771.3 */ 1478, +/* 8765 2772.0 */ 1476, +/* 8766 2772.1 */ 1061, +/* 8767 2772.2 */ 1477, +/* 8768 2772.3 */ 1475, +/* 8769 2773.0 */ 1479, +/* 8770 2773.1 */ 1061, +/* 8771 2773.2 */ 1480, +/* 8772 2773.3 */ 1481, +/* 8773 2774.0 */ 1482, +/* 8774 2774.1 */ 1061, +/* 8775 2774.2 */ 1480, +/* 8776 2774.3 */ 1481, +/* 8777 2775.0 */ 1479, +/* 8778 2775.1 */ 1061, +/* 8779 2775.2 */ 1480, +/* 8780 2775.3 */ 1475, +/* 8781 2776.0 */ 1483, +/* 8782 2776.1 */ 1061, +/* 8783 2776.2 */ 1473, +/* 8784 2776.3 */ 1474, +/* 8785 2777.0 */ 1472, +/* 8786 2777.1 */ 1061, +/* 8787 2777.2 */ 1473, +/* 8788 2777.3 */ 1484, +/* 8789 2778.0 */ 1485, +/* 8790 2778.1 */ 1061, +/* 8791 2778.2 */ 1473, +/* 8792 2778.3 */ 1474, +/* 8793 2779.0 */ 1485, +/* 8794 2779.1 */ 1061, +/* 8795 2779.2 */ 1473, +/* 8796 2779.3 */ 1475, +/* 8797 2780.0 */ 1486, +/* 8798 2780.1 */ 1061, +/* 8799 2780.2 */ 1477, +/* 8800 2780.3 */ 1478, +/* 8801 2781.0 */ 1486, +/* 8802 2781.1 */ 1061, +/* 8803 2781.2 */ 1477, +/* 8804 2781.3 */ 1475, +/* 8805 2782.0 */ 1487, +/* 8806 2782.1 */ 1061, +/* 8807 2782.2 */ 1480, +/* 8808 2782.3 */ 1481, +/* 8809 2783.0 */ 1488, +/* 8810 2783.1 */ 1061, +/* 8811 2783.2 */ 1480, +/* 8812 2783.3 */ 1481, +/* 8813 2784.0 */ 1487, +/* 8814 2784.1 */ 1061, +/* 8815 2784.2 */ 1480, +/* 8816 2784.3 */ 1475, +/* 8817 2785.0 */ 1489, +/* 8818 2785.1 */ 1061, +/* 8819 2785.2 */ 1473, +/* 8820 2785.3 */ 1474, +/* 8821 2786.0 */ 1485, +/* 8822 2786.1 */ 1061, +/* 8823 2786.2 */ 1473, +/* 8824 2786.3 */ 1484, +/* 8825 2787.0 */ 1490, +/* 8826 2787.1 */ 1061, +/* 8827 2787.2 */ 1448, +/* 8828 2787.3 */ 1449, +/* 8829 2788.0 */ 1490, +/* 8830 2788.1 */ 1061, +/* 8831 2788.2 */ 1448, +/* 8832 2788.3 */ 1450, +/* 8833 2789.0 */ 1491, +/* 8834 2789.1 */ 1061, +/* 8835 2789.2 */ 1452, +/* 8836 2789.3 */ 1453, +/* 8837 2790.0 */ 1491, +/* 8838 2790.1 */ 1061, +/* 8839 2790.2 */ 1452, +/* 8840 2790.3 */ 1450, +/* 8841 2791.0 */ 1492, +/* 8842 2791.1 */ 1061, +/* 8843 2791.2 */ 1455, +/* 8844 2791.3 */ 1456, +/* 8845 2792.0 */ 1493, +/* 8846 2792.1 */ 1061, +/* 8847 2792.2 */ 1455, +/* 8848 2792.3 */ 1456, +/* 8849 2793.0 */ 1492, +/* 8850 2793.1 */ 1061, +/* 8851 2793.2 */ 1455, +/* 8852 2793.3 */ 1450, +/* 8853 2794.0 */ 1494, +/* 8854 2794.1 */ 1061, +/* 8855 2794.2 */ 1448, +/* 8856 2794.3 */ 1449, +/* 8857 2795.0 */ 1490, +/* 8858 2795.1 */ 1061, +/* 8859 2795.2 */ 1448, +/* 8860 2795.3 */ 1459, +/* 8861 2796.0 */ 1034, +/* 8862 2796.1 */ 1139, +/* 8863 2796.2 */ 1180, +/* 8864 2796.3 */ 120, +/* 8865 2797.0 */ 1034, +/* 8866 2797.1 */ 1139, +/* 8867 2797.2 */ 1450, +/* 8868 2797.3 */ 120, +/* 8869 2798.0 */ 1034, +/* 8870 2798.1 */ 1139, +/* 8871 2798.2 */ 1178, +/* 8872 2798.3 */ 120, +/* 8873 2799.0 */ 1034, +/* 8874 2799.1 */ 1139, +/* 8875 2799.2 */ 1464, +/* 8876 2799.3 */ 120, +/* 8877 2800.0 */ 1034, +/* 8878 2800.1 */ 1139, +/* 8879 2800.2 */ 1459, +/* 8880 2800.3 */ 120, +/* 8881 2801.0 */ 1447, +/* 8882 2801.1 */ 1061, +/* 8883 2801.2 */ 1180, +/* 8884 2802.0 */ 1447, +/* 8885 2802.1 */ 1061, +/* 8886 2802.2 */ 1450, +/* 8887 2803.0 */ 1451, +/* 8888 2803.1 */ 1061, +/* 8889 2803.2 */ 1178, +/* 8890 2804.0 */ 1451, +/* 8891 2804.1 */ 1061, +/* 8892 2804.2 */ 1450, +/* 8893 2805.0 */ 1454, +/* 8894 2805.1 */ 1061, +/* 8895 2805.2 */ 1464, +/* 8896 2806.0 */ 1495, +/* 8897 2806.1 */ 1061, +/* 8898 2806.2 */ 1464, +/* 8899 2807.0 */ 1454, +/* 8900 2807.1 */ 1061, +/* 8901 2807.2 */ 1450, +/* 8902 2808.0 */ 1496, +/* 8903 2808.1 */ 1061, +/* 8904 2808.2 */ 1448, +/* 8905 2808.3 */ 1449, +/* 8906 2809.0 */ 1447, +/* 8907 2809.1 */ 1061, +/* 8908 2809.2 */ 1180, +/* 8909 2809.3 */ 120, +/* 8910 2810.0 */ 1447, +/* 8911 2810.1 */ 1061, +/* 8912 2810.2 */ 1450, +/* 8913 2810.3 */ 120, +/* 8914 2811.0 */ 1451, +/* 8915 2811.1 */ 1061, +/* 8916 2811.2 */ 1178, +/* 8917 2811.3 */ 120, +/* 8918 2812.0 */ 1451, +/* 8919 2812.1 */ 1061, +/* 8920 2812.2 */ 1450, +/* 8921 2812.3 */ 120, +/* 8922 2813.0 */ 1454, +/* 8923 2813.1 */ 1061, +/* 8924 2813.2 */ 1464, +/* 8925 2813.3 */ 120, +/* 8926 2814.0 */ 1495, +/* 8927 2814.1 */ 1061, +/* 8928 2814.2 */ 1464, +/* 8929 2814.3 */ 120, +/* 8930 2815.0 */ 1454, +/* 8931 2815.1 */ 1061, +/* 8932 2815.2 */ 1450, +/* 8933 2815.3 */ 120, +/* 8934 2816.0 */ 1447, +/* 8935 2816.1 */ 1061, +/* 8936 2816.2 */ 1448, +/* 8937 2816.3 */ 1449, +/* 8938 2816.4 */ 120, +/* 8939 2817.0 */ 1496, +/* 8940 2817.1 */ 1061, +/* 8941 2817.2 */ 1448, +/* 8942 2817.3 */ 1449, +/* 8943 2817.4 */ 120, +/* 8944 2818.0 */ 1447, +/* 8945 2818.1 */ 1061, +/* 8946 2818.2 */ 1448, +/* 8947 2818.3 */ 1459, +/* 8948 2818.4 */ 120, +/* 8949 2819.0 */ 1495, +/* 8950 2819.1 */ 1061, +/* 8951 2819.2 */ 1455, +/* 8952 2819.3 */ 1456, +/* 8953 2820.0 */ 1447, +/* 8954 2820.1 */ 1061, +/* 8955 2820.2 */ 1459, +/* 8956 2821.0 */ 1497, +/* 8957 2821.1 */ 1148, +/* 8958 2821.2 */ 1498, +/* 8959 2822.0 */ 1186, +/* 8960 2822.1 */ 1061, +/* 8961 2822.2 */ 1448, +/* 8962 2822.3 */ 1499, +/* 8963 2823.0 */ 1447, +/* 8964 2823.1 */ 1500, +/* 8965 2824.0 */ 1447, +/* 8966 2824.1 */ 1459, +/* 8967 2825.0 */ 1501, +/* 8968 2825.1 */ 1498, +/* 8969 2826.0 */ 1497, +/* 8970 2826.1 */ 1460, +/* 8971 2827.0 */ 1457, +/* 8972 2827.1 */ 1061, +/* 8973 2827.2 */ 1464, +}; diff --git a/CodeVirtualizer/build/obj/xed-init-operand-type-mappings.c b/CodeVirtualizer/build/obj/xed-init-operand-type-mappings.c new file mode 100644 index 0000000..f7d008c --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-operand-type-mappings.c @@ -0,0 +1,48 @@ +/// @file xed-init-operand-type-mappings.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +const xed_operand_type_info_t xed_operand_xtype_info[] = { +/* INVALID */ { XED_OPERAND_ELEMENT_TYPE_INVALID, 0 }, +/* 2f16 */ { XED_OPERAND_ELEMENT_TYPE_FLOAT16, 32 }, +/* b80 */ { XED_OPERAND_ELEMENT_TYPE_LONGBCD, 80 }, +/* bf16 */ { XED_OPERAND_ELEMENT_TYPE_BFLOAT16, 16 }, +/* f16 */ { XED_OPERAND_ELEMENT_TYPE_FLOAT16, 16 }, +/* f32 */ { XED_OPERAND_ELEMENT_TYPE_SINGLE, 32 }, +/* f64 */ { XED_OPERAND_ELEMENT_TYPE_DOUBLE, 64 }, +/* f80 */ { XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE, 80 }, +/* i1 */ { XED_OPERAND_ELEMENT_TYPE_INT, 1 }, +/* i16 */ { XED_OPERAND_ELEMENT_TYPE_INT, 16 }, +/* i32 */ { XED_OPERAND_ELEMENT_TYPE_INT, 32 }, +/* i64 */ { XED_OPERAND_ELEMENT_TYPE_INT, 64 }, +/* i8 */ { XED_OPERAND_ELEMENT_TYPE_INT, 8 }, +/* int */ { XED_OPERAND_ELEMENT_TYPE_INT, 0 }, +/* struct */ { XED_OPERAND_ELEMENT_TYPE_STRUCT, 0 }, +/* u128 */ { XED_OPERAND_ELEMENT_TYPE_UINT, 128 }, +/* u16 */ { XED_OPERAND_ELEMENT_TYPE_UINT, 16 }, +/* u256 */ { XED_OPERAND_ELEMENT_TYPE_UINT, 256 }, +/* u32 */ { XED_OPERAND_ELEMENT_TYPE_UINT, 32 }, +/* u64 */ { XED_OPERAND_ELEMENT_TYPE_UINT, 64 }, +/* u8 */ { XED_OPERAND_ELEMENT_TYPE_UINT, 8 }, +/* uint */ { XED_OPERAND_ELEMENT_TYPE_UINT, 0 }, +/* var */ { XED_OPERAND_ELEMENT_TYPE_VARIABLE, 0 }, +}; diff --git a/CodeVirtualizer/build/obj/xed-init-pointer-names.c b/CodeVirtualizer/build/obj/xed-init-pointer-names.c new file mode 100644 index 0000000..ef00086 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-pointer-names.c @@ -0,0 +1,46 @@ +/// @file xed-init-pointer-names.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-init-pointer-names.h" +#include +const char* xed_pointer_name[XED_MAX_POINTER_NAMES]; +const char* xed_pointer_name_suffix[XED_MAX_POINTER_NAMES]; +void xed_init_pointer_names(void) +{ + memset((void*)xed_pointer_name,0,sizeof(const char*)*XED_MAX_POINTER_NAMES); + xed_pointer_name[1] = "byte "; + xed_pointer_name[2] = "word "; + xed_pointer_name[4] = "dword "; + xed_pointer_name[8] = "qword "; + xed_pointer_name[16] = "xmmword "; + xed_pointer_name[32] = "ymmword "; + xed_pointer_name[64] = "zmmword "; + memset((void*)xed_pointer_name_suffix,0,sizeof(const char*)*XED_MAX_POINTER_NAMES); + xed_pointer_name_suffix[1] = "b "; + xed_pointer_name_suffix[2] = "w "; + xed_pointer_name_suffix[4] = "l "; + xed_pointer_name_suffix[8] = "q "; + xed_pointer_name_suffix[16] = "x "; + xed_pointer_name_suffix[32] = "y "; + xed_pointer_name_suffix[64] = "z "; +} diff --git a/CodeVirtualizer/build/obj/xed-init-pointer-names.h b/CodeVirtualizer/build/obj/xed-init-pointer-names.h new file mode 100644 index 0000000..b7f448b --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-pointer-names.h @@ -0,0 +1,27 @@ +/// @file xed-init-pointer-names.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_INIT_POINTER_NAMES_H) +# define XED_INIT_POINTER_NAMES_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#define XED_MAX_POINTER_NAMES 65 +#endif diff --git a/CodeVirtualizer/build/obj/xed-init-reg-class.c b/CodeVirtualizer/build/obj/xed-init-reg-class.c new file mode 100644 index 0000000..215c251 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-reg-class.c @@ -0,0 +1,1514 @@ +/// @file xed-init-reg-class.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_init_reg_mappings(void) +{ + xed_reg_class_array[XED_REG_INVALID]= XED_REG_CLASS_INVALID; + xed_reg_class_array[XED_REG_ERROR]= XED_REG_CLASS_INVALID; + xed_reg_class_array[XED_REG_RAX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_EAX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_AX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_AH]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_AL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RCX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_ECX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_CX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_CH]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_CL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RDX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_EDX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_DX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_DH]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_DL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RBX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_EBX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_BX]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_BH]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_BL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RSP]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_ESP]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_SP]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_SPL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RBP]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_EBP]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_BP]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_BPL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RSI]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_ESI]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_SI]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_SIL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RDI]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_EDI]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_DI]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_DIL]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R8]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R8D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R8W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R8B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R9]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R9D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R9W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R9B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R10]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R10D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R10W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R10B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R11]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R11D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R11W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R11B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R12]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R12D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R12W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R12B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R13]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R13D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R13W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R13B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R14]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R14D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R14W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R14B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R15]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R15D]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R15W]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_R15B]= XED_REG_CLASS_GPR; + xed_reg_class_array[XED_REG_RIP]= XED_REG_CLASS_IP; + xed_reg_class_array[XED_REG_EIP]= XED_REG_CLASS_IP; + xed_reg_class_array[XED_REG_IP]= XED_REG_CLASS_IP; + xed_reg_class_array[XED_REG_FLAGS]= XED_REG_CLASS_FLAGS; + xed_reg_class_array[XED_REG_EFLAGS]= XED_REG_CLASS_FLAGS; + xed_reg_class_array[XED_REG_RFLAGS]= XED_REG_CLASS_FLAGS; + xed_reg_class_array[XED_REG_ES]= XED_REG_CLASS_SR; + xed_reg_class_array[XED_REG_CS]= XED_REG_CLASS_SR; + xed_reg_class_array[XED_REG_SS]= XED_REG_CLASS_SR; + xed_reg_class_array[XED_REG_DS]= XED_REG_CLASS_SR; + xed_reg_class_array[XED_REG_FS]= XED_REG_CLASS_SR; + xed_reg_class_array[XED_REG_GS]= XED_REG_CLASS_SR; + xed_reg_class_array[XED_REG_MMX0]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX1]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX2]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX3]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX4]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX5]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX6]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_MMX7]= XED_REG_CLASS_MMX; + xed_reg_class_array[XED_REG_ST0]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST1]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST2]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST3]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST4]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST5]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST6]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_ST7]= XED_REG_CLASS_X87; + xed_reg_class_array[XED_REG_CR0]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR1]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR2]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR3]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR4]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR5]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR6]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR7]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR8]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR9]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR10]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR11]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR12]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR13]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR14]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_CR15]= XED_REG_CLASS_CR; + xed_reg_class_array[XED_REG_DR0]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR1]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR2]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR3]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR4]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR5]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR6]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_DR7]= XED_REG_CLASS_DR; + xed_reg_class_array[XED_REG_STACKPUSH]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_STACKPOP]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_GDTR]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_LDTR]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_IDTR]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_TR]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_TSC]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_TSCAUX]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_MSRS]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_X87CONTROL]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87STATUS]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87TAG]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87PUSH]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87POP]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87POP2]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87OPCODE]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87LASTCS]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87LASTIP]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87LASTDS]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_X87LASTDP]= XED_REG_CLASS_PSEUDOX87; + xed_reg_class_array[XED_REG_XCR0]= XED_REG_CLASS_XCR; + xed_reg_class_array[XED_REG_MXCSR]= XED_REG_CLASS_MXCSR; + xed_reg_class_array[XED_REG_TMP0]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP1]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP2]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP3]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP4]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP5]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP6]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP7]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP8]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP9]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP10]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP11]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP12]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP13]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP14]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_TMP15]= XED_REG_CLASS_TMP; + xed_reg_class_array[XED_REG_K0]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K1]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K2]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K3]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K4]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K5]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K6]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_K7]= XED_REG_CLASS_MASK; + xed_reg_class_array[XED_REG_BND0]= XED_REG_CLASS_BOUND; + xed_reg_class_array[XED_REG_BND1]= XED_REG_CLASS_BOUND; + xed_reg_class_array[XED_REG_BND2]= XED_REG_CLASS_BOUND; + xed_reg_class_array[XED_REG_BND3]= XED_REG_CLASS_BOUND; + xed_reg_class_array[XED_REG_BNDCFGU]= XED_REG_CLASS_BNDCFG; + xed_reg_class_array[XED_REG_BNDSTATUS]= XED_REG_CLASS_BNDSTAT; + xed_reg_class_array[XED_REG_SSP]= XED_REG_CLASS_MSR; + xed_reg_class_array[XED_REG_IA32_U_CET]= XED_REG_CLASS_MSR; + xed_reg_class_array[XED_REG_FSBASE]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_GSBASE]= XED_REG_CLASS_PSEUDO; + xed_reg_class_array[XED_REG_XMM0]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM1]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM2]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM3]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM4]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM5]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM6]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM7]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM8]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM9]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM10]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM11]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM12]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM13]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM14]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM15]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_YMM0]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM1]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM2]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM3]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM4]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM5]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM6]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM7]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM8]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM9]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM10]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM11]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM12]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM13]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM14]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM15]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_ZMM0]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM1]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM2]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM3]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM4]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM5]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM6]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM7]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM8]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM9]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM10]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM11]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM12]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM13]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM14]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM15]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM16]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM17]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM18]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM19]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM20]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM21]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM22]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM23]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM24]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM25]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM26]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM27]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM28]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM29]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM30]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_ZMM31]= XED_REG_CLASS_ZMM; + xed_reg_class_array[XED_REG_XMM16]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM17]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM18]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM19]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM20]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM21]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM22]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM23]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM24]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM25]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM26]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM27]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM28]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM29]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM30]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_XMM31]= XED_REG_CLASS_XMM; + xed_reg_class_array[XED_REG_YMM16]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM17]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM18]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM19]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM20]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM21]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM22]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM23]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM24]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM25]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM26]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM27]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM28]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM29]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM30]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_YMM31]= XED_REG_CLASS_YMM; + xed_reg_class_array[XED_REG_UIF]= XED_REG_CLASS_UIF; + xed_reg_class_array[XED_REG_TMM0]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM1]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM2]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM3]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM4]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM5]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM6]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TMM7]= XED_REG_CLASS_TREG; + xed_reg_class_array[XED_REG_TILECONFIG]= XED_REG_CLASS_PSEUDO; + xed_largest_enclosing_register_array[XED_REG_INVALID]= XED_REG_INVALID; + xed_largest_enclosing_register_array_32[XED_REG_INVALID]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ERROR]= XED_REG_ERROR; + xed_largest_enclosing_register_array_32[XED_REG_ERROR]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_RAX]= XED_REG_RAX; + xed_largest_enclosing_register_array_32[XED_REG_RAX]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_EAX]= XED_REG_RAX; + xed_largest_enclosing_register_array_32[XED_REG_EAX]= XED_REG_EAX; + xed_largest_enclosing_register_array[XED_REG_AX]= XED_REG_RAX; + xed_largest_enclosing_register_array_32[XED_REG_AX]= XED_REG_EAX; + xed_largest_enclosing_register_array[XED_REG_AH]= XED_REG_RAX; + xed_largest_enclosing_register_array_32[XED_REG_AH]= XED_REG_EAX; + xed_largest_enclosing_register_array[XED_REG_AL]= XED_REG_RAX; + xed_largest_enclosing_register_array_32[XED_REG_AL]= XED_REG_EAX; + xed_largest_enclosing_register_array[XED_REG_RCX]= XED_REG_RCX; + xed_largest_enclosing_register_array_32[XED_REG_RCX]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ECX]= XED_REG_RCX; + xed_largest_enclosing_register_array_32[XED_REG_ECX]= XED_REG_ECX; + xed_largest_enclosing_register_array[XED_REG_CX]= XED_REG_RCX; + xed_largest_enclosing_register_array_32[XED_REG_CX]= XED_REG_ECX; + xed_largest_enclosing_register_array[XED_REG_CH]= XED_REG_RCX; + xed_largest_enclosing_register_array_32[XED_REG_CH]= XED_REG_ECX; + xed_largest_enclosing_register_array[XED_REG_CL]= XED_REG_RCX; + xed_largest_enclosing_register_array_32[XED_REG_CL]= XED_REG_ECX; + xed_largest_enclosing_register_array[XED_REG_RDX]= XED_REG_RDX; + xed_largest_enclosing_register_array_32[XED_REG_RDX]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_EDX]= XED_REG_RDX; + xed_largest_enclosing_register_array_32[XED_REG_EDX]= XED_REG_EDX; + xed_largest_enclosing_register_array[XED_REG_DX]= XED_REG_RDX; + xed_largest_enclosing_register_array_32[XED_REG_DX]= XED_REG_EDX; + xed_largest_enclosing_register_array[XED_REG_DH]= XED_REG_RDX; + xed_largest_enclosing_register_array_32[XED_REG_DH]= XED_REG_EDX; + xed_largest_enclosing_register_array[XED_REG_DL]= XED_REG_RDX; + xed_largest_enclosing_register_array_32[XED_REG_DL]= XED_REG_EDX; + xed_largest_enclosing_register_array[XED_REG_RBX]= XED_REG_RBX; + xed_largest_enclosing_register_array_32[XED_REG_RBX]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_EBX]= XED_REG_RBX; + xed_largest_enclosing_register_array_32[XED_REG_EBX]= XED_REG_EBX; + xed_largest_enclosing_register_array[XED_REG_BX]= XED_REG_RBX; + xed_largest_enclosing_register_array_32[XED_REG_BX]= XED_REG_EBX; + xed_largest_enclosing_register_array[XED_REG_BH]= XED_REG_RBX; + xed_largest_enclosing_register_array_32[XED_REG_BH]= XED_REG_EBX; + xed_largest_enclosing_register_array[XED_REG_BL]= XED_REG_RBX; + xed_largest_enclosing_register_array_32[XED_REG_BL]= XED_REG_EBX; + xed_largest_enclosing_register_array[XED_REG_RSP]= XED_REG_RSP; + xed_largest_enclosing_register_array_32[XED_REG_RSP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ESP]= XED_REG_RSP; + xed_largest_enclosing_register_array_32[XED_REG_ESP]= XED_REG_ESP; + xed_largest_enclosing_register_array[XED_REG_SP]= XED_REG_RSP; + xed_largest_enclosing_register_array_32[XED_REG_SP]= XED_REG_ESP; + xed_largest_enclosing_register_array[XED_REG_SPL]= XED_REG_RSP; + xed_largest_enclosing_register_array_32[XED_REG_SPL]= XED_REG_ESP; + xed_largest_enclosing_register_array[XED_REG_RBP]= XED_REG_RBP; + xed_largest_enclosing_register_array_32[XED_REG_RBP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_EBP]= XED_REG_RBP; + xed_largest_enclosing_register_array_32[XED_REG_EBP]= XED_REG_EBP; + xed_largest_enclosing_register_array[XED_REG_BP]= XED_REG_RBP; + xed_largest_enclosing_register_array_32[XED_REG_BP]= XED_REG_EBP; + xed_largest_enclosing_register_array[XED_REG_BPL]= XED_REG_RBP; + xed_largest_enclosing_register_array_32[XED_REG_BPL]= XED_REG_EBP; + xed_largest_enclosing_register_array[XED_REG_RSI]= XED_REG_RSI; + xed_largest_enclosing_register_array_32[XED_REG_RSI]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ESI]= XED_REG_RSI; + xed_largest_enclosing_register_array_32[XED_REG_ESI]= XED_REG_ESI; + xed_largest_enclosing_register_array[XED_REG_SI]= XED_REG_RSI; + xed_largest_enclosing_register_array_32[XED_REG_SI]= XED_REG_ESI; + xed_largest_enclosing_register_array[XED_REG_SIL]= XED_REG_RSI; + xed_largest_enclosing_register_array_32[XED_REG_SIL]= XED_REG_ESI; + xed_largest_enclosing_register_array[XED_REG_RDI]= XED_REG_RDI; + xed_largest_enclosing_register_array_32[XED_REG_RDI]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_EDI]= XED_REG_RDI; + xed_largest_enclosing_register_array_32[XED_REG_EDI]= XED_REG_EDI; + xed_largest_enclosing_register_array[XED_REG_DI]= XED_REG_RDI; + xed_largest_enclosing_register_array_32[XED_REG_DI]= XED_REG_EDI; + xed_largest_enclosing_register_array[XED_REG_DIL]= XED_REG_RDI; + xed_largest_enclosing_register_array_32[XED_REG_DIL]= XED_REG_EDI; + xed_largest_enclosing_register_array[XED_REG_R8]= XED_REG_R8; + xed_largest_enclosing_register_array_32[XED_REG_R8]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R8D]= XED_REG_R8; + xed_largest_enclosing_register_array_32[XED_REG_R8D]= XED_REG_R8D; + xed_largest_enclosing_register_array[XED_REG_R8W]= XED_REG_R8; + xed_largest_enclosing_register_array_32[XED_REG_R8W]= XED_REG_R8D; + xed_largest_enclosing_register_array[XED_REG_R8B]= XED_REG_R8; + xed_largest_enclosing_register_array_32[XED_REG_R8B]= XED_REG_R8D; + xed_largest_enclosing_register_array[XED_REG_R9]= XED_REG_R9; + xed_largest_enclosing_register_array_32[XED_REG_R9]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R9D]= XED_REG_R9; + xed_largest_enclosing_register_array_32[XED_REG_R9D]= XED_REG_R9D; + xed_largest_enclosing_register_array[XED_REG_R9W]= XED_REG_R9; + xed_largest_enclosing_register_array_32[XED_REG_R9W]= XED_REG_R9D; + xed_largest_enclosing_register_array[XED_REG_R9B]= XED_REG_R9; + xed_largest_enclosing_register_array_32[XED_REG_R9B]= XED_REG_R9D; + xed_largest_enclosing_register_array[XED_REG_R10]= XED_REG_R10; + xed_largest_enclosing_register_array_32[XED_REG_R10]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R10D]= XED_REG_R10; + xed_largest_enclosing_register_array_32[XED_REG_R10D]= XED_REG_R10D; + xed_largest_enclosing_register_array[XED_REG_R10W]= XED_REG_R10; + xed_largest_enclosing_register_array_32[XED_REG_R10W]= XED_REG_R10D; + xed_largest_enclosing_register_array[XED_REG_R10B]= XED_REG_R10; + xed_largest_enclosing_register_array_32[XED_REG_R10B]= XED_REG_R10D; + xed_largest_enclosing_register_array[XED_REG_R11]= XED_REG_R11; + xed_largest_enclosing_register_array_32[XED_REG_R11]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R11D]= XED_REG_R11; + xed_largest_enclosing_register_array_32[XED_REG_R11D]= XED_REG_R11D; + xed_largest_enclosing_register_array[XED_REG_R11W]= XED_REG_R11; + xed_largest_enclosing_register_array_32[XED_REG_R11W]= XED_REG_R11D; + xed_largest_enclosing_register_array[XED_REG_R11B]= XED_REG_R11; + xed_largest_enclosing_register_array_32[XED_REG_R11B]= XED_REG_R11D; + xed_largest_enclosing_register_array[XED_REG_R12]= XED_REG_R12; + xed_largest_enclosing_register_array_32[XED_REG_R12]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R12D]= XED_REG_R12; + xed_largest_enclosing_register_array_32[XED_REG_R12D]= XED_REG_R12D; + xed_largest_enclosing_register_array[XED_REG_R12W]= XED_REG_R12; + xed_largest_enclosing_register_array_32[XED_REG_R12W]= XED_REG_R12D; + xed_largest_enclosing_register_array[XED_REG_R12B]= XED_REG_R12; + xed_largest_enclosing_register_array_32[XED_REG_R12B]= XED_REG_R12D; + xed_largest_enclosing_register_array[XED_REG_R13]= XED_REG_R13; + xed_largest_enclosing_register_array_32[XED_REG_R13]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R13D]= XED_REG_R13; + xed_largest_enclosing_register_array_32[XED_REG_R13D]= XED_REG_R13D; + xed_largest_enclosing_register_array[XED_REG_R13W]= XED_REG_R13; + xed_largest_enclosing_register_array_32[XED_REG_R13W]= XED_REG_R13D; + xed_largest_enclosing_register_array[XED_REG_R13B]= XED_REG_R13; + xed_largest_enclosing_register_array_32[XED_REG_R13B]= XED_REG_R13D; + xed_largest_enclosing_register_array[XED_REG_R14]= XED_REG_R14; + xed_largest_enclosing_register_array_32[XED_REG_R14]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R14D]= XED_REG_R14; + xed_largest_enclosing_register_array_32[XED_REG_R14D]= XED_REG_R14D; + xed_largest_enclosing_register_array[XED_REG_R14W]= XED_REG_R14; + xed_largest_enclosing_register_array_32[XED_REG_R14W]= XED_REG_R14D; + xed_largest_enclosing_register_array[XED_REG_R14B]= XED_REG_R14; + xed_largest_enclosing_register_array_32[XED_REG_R14B]= XED_REG_R14D; + xed_largest_enclosing_register_array[XED_REG_R15]= XED_REG_R15; + xed_largest_enclosing_register_array_32[XED_REG_R15]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_R15D]= XED_REG_R15; + xed_largest_enclosing_register_array_32[XED_REG_R15D]= XED_REG_R15D; + xed_largest_enclosing_register_array[XED_REG_R15W]= XED_REG_R15; + xed_largest_enclosing_register_array_32[XED_REG_R15W]= XED_REG_R15D; + xed_largest_enclosing_register_array[XED_REG_R15B]= XED_REG_R15; + xed_largest_enclosing_register_array_32[XED_REG_R15B]= XED_REG_R15D; + xed_largest_enclosing_register_array[XED_REG_RIP]= XED_REG_RIP; + xed_largest_enclosing_register_array_32[XED_REG_RIP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_EIP]= XED_REG_RIP; + xed_largest_enclosing_register_array_32[XED_REG_EIP]= XED_REG_EIP; + xed_largest_enclosing_register_array[XED_REG_IP]= XED_REG_RIP; + xed_largest_enclosing_register_array_32[XED_REG_IP]= XED_REG_EIP; + xed_largest_enclosing_register_array[XED_REG_FLAGS]= XED_REG_RFLAGS; + xed_largest_enclosing_register_array_32[XED_REG_FLAGS]= XED_REG_EFLAGS; + xed_largest_enclosing_register_array[XED_REG_EFLAGS]= XED_REG_RFLAGS; + xed_largest_enclosing_register_array_32[XED_REG_EFLAGS]= XED_REG_EFLAGS; + xed_largest_enclosing_register_array[XED_REG_RFLAGS]= XED_REG_RFLAGS; + xed_largest_enclosing_register_array_32[XED_REG_RFLAGS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ES]= XED_REG_ES; + xed_largest_enclosing_register_array_32[XED_REG_ES]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CS]= XED_REG_CS; + xed_largest_enclosing_register_array_32[XED_REG_CS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_SS]= XED_REG_SS; + xed_largest_enclosing_register_array_32[XED_REG_SS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DS]= XED_REG_DS; + xed_largest_enclosing_register_array_32[XED_REG_DS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_FS]= XED_REG_FS; + xed_largest_enclosing_register_array_32[XED_REG_FS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_GS]= XED_REG_GS; + xed_largest_enclosing_register_array_32[XED_REG_GS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX0]= XED_REG_MMX0; + xed_largest_enclosing_register_array_32[XED_REG_MMX0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX1]= XED_REG_MMX1; + xed_largest_enclosing_register_array_32[XED_REG_MMX1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX2]= XED_REG_MMX2; + xed_largest_enclosing_register_array_32[XED_REG_MMX2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX3]= XED_REG_MMX3; + xed_largest_enclosing_register_array_32[XED_REG_MMX3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX4]= XED_REG_MMX4; + xed_largest_enclosing_register_array_32[XED_REG_MMX4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX5]= XED_REG_MMX5; + xed_largest_enclosing_register_array_32[XED_REG_MMX5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX6]= XED_REG_MMX6; + xed_largest_enclosing_register_array_32[XED_REG_MMX6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MMX7]= XED_REG_MMX7; + xed_largest_enclosing_register_array_32[XED_REG_MMX7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST0]= XED_REG_ST0; + xed_largest_enclosing_register_array_32[XED_REG_ST0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST1]= XED_REG_ST1; + xed_largest_enclosing_register_array_32[XED_REG_ST1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST2]= XED_REG_ST2; + xed_largest_enclosing_register_array_32[XED_REG_ST2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST3]= XED_REG_ST3; + xed_largest_enclosing_register_array_32[XED_REG_ST3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST4]= XED_REG_ST4; + xed_largest_enclosing_register_array_32[XED_REG_ST4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST5]= XED_REG_ST5; + xed_largest_enclosing_register_array_32[XED_REG_ST5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST6]= XED_REG_ST6; + xed_largest_enclosing_register_array_32[XED_REG_ST6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ST7]= XED_REG_ST7; + xed_largest_enclosing_register_array_32[XED_REG_ST7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR0]= XED_REG_CR0; + xed_largest_enclosing_register_array_32[XED_REG_CR0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR1]= XED_REG_CR1; + xed_largest_enclosing_register_array_32[XED_REG_CR1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR2]= XED_REG_CR2; + xed_largest_enclosing_register_array_32[XED_REG_CR2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR3]= XED_REG_CR3; + xed_largest_enclosing_register_array_32[XED_REG_CR3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR4]= XED_REG_CR4; + xed_largest_enclosing_register_array_32[XED_REG_CR4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR5]= XED_REG_CR5; + xed_largest_enclosing_register_array_32[XED_REG_CR5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR6]= XED_REG_CR6; + xed_largest_enclosing_register_array_32[XED_REG_CR6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR7]= XED_REG_CR7; + xed_largest_enclosing_register_array_32[XED_REG_CR7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR8]= XED_REG_CR8; + xed_largest_enclosing_register_array_32[XED_REG_CR8]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR9]= XED_REG_CR9; + xed_largest_enclosing_register_array_32[XED_REG_CR9]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR10]= XED_REG_CR10; + xed_largest_enclosing_register_array_32[XED_REG_CR10]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR11]= XED_REG_CR11; + xed_largest_enclosing_register_array_32[XED_REG_CR11]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR12]= XED_REG_CR12; + xed_largest_enclosing_register_array_32[XED_REG_CR12]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR13]= XED_REG_CR13; + xed_largest_enclosing_register_array_32[XED_REG_CR13]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR14]= XED_REG_CR14; + xed_largest_enclosing_register_array_32[XED_REG_CR14]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_CR15]= XED_REG_CR15; + xed_largest_enclosing_register_array_32[XED_REG_CR15]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR0]= XED_REG_DR0; + xed_largest_enclosing_register_array_32[XED_REG_DR0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR1]= XED_REG_DR1; + xed_largest_enclosing_register_array_32[XED_REG_DR1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR2]= XED_REG_DR2; + xed_largest_enclosing_register_array_32[XED_REG_DR2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR3]= XED_REG_DR3; + xed_largest_enclosing_register_array_32[XED_REG_DR3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR4]= XED_REG_DR4; + xed_largest_enclosing_register_array_32[XED_REG_DR4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR5]= XED_REG_DR5; + xed_largest_enclosing_register_array_32[XED_REG_DR5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR6]= XED_REG_DR6; + xed_largest_enclosing_register_array_32[XED_REG_DR6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_DR7]= XED_REG_DR7; + xed_largest_enclosing_register_array_32[XED_REG_DR7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_STACKPUSH]= XED_REG_STACKPUSH; + xed_largest_enclosing_register_array_32[XED_REG_STACKPUSH]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_STACKPOP]= XED_REG_STACKPOP; + xed_largest_enclosing_register_array_32[XED_REG_STACKPOP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_GDTR]= XED_REG_GDTR; + xed_largest_enclosing_register_array_32[XED_REG_GDTR]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_LDTR]= XED_REG_LDTR; + xed_largest_enclosing_register_array_32[XED_REG_LDTR]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_IDTR]= XED_REG_IDTR; + xed_largest_enclosing_register_array_32[XED_REG_IDTR]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TR]= XED_REG_TR; + xed_largest_enclosing_register_array_32[XED_REG_TR]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TSC]= XED_REG_TSC; + xed_largest_enclosing_register_array_32[XED_REG_TSC]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TSCAUX]= XED_REG_TSCAUX; + xed_largest_enclosing_register_array_32[XED_REG_TSCAUX]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MSRS]= XED_REG_MSRS; + xed_largest_enclosing_register_array_32[XED_REG_MSRS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87CONTROL]= XED_REG_X87CONTROL; + xed_largest_enclosing_register_array_32[XED_REG_X87CONTROL]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87STATUS]= XED_REG_X87STATUS; + xed_largest_enclosing_register_array_32[XED_REG_X87STATUS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87TAG]= XED_REG_X87TAG; + xed_largest_enclosing_register_array_32[XED_REG_X87TAG]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87PUSH]= XED_REG_X87PUSH; + xed_largest_enclosing_register_array_32[XED_REG_X87PUSH]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87POP]= XED_REG_X87POP; + xed_largest_enclosing_register_array_32[XED_REG_X87POP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87POP2]= XED_REG_X87POP2; + xed_largest_enclosing_register_array_32[XED_REG_X87POP2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87OPCODE]= XED_REG_X87OPCODE; + xed_largest_enclosing_register_array_32[XED_REG_X87OPCODE]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87LASTCS]= XED_REG_X87LASTCS; + xed_largest_enclosing_register_array_32[XED_REG_X87LASTCS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87LASTIP]= XED_REG_X87LASTIP; + xed_largest_enclosing_register_array_32[XED_REG_X87LASTIP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87LASTDS]= XED_REG_X87LASTDS; + xed_largest_enclosing_register_array_32[XED_REG_X87LASTDS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_X87LASTDP]= XED_REG_X87LASTDP; + xed_largest_enclosing_register_array_32[XED_REG_X87LASTDP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XCR0]= XED_REG_XCR0; + xed_largest_enclosing_register_array_32[XED_REG_XCR0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_MXCSR]= XED_REG_MXCSR; + xed_largest_enclosing_register_array_32[XED_REG_MXCSR]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP0]= XED_REG_TMP0; + xed_largest_enclosing_register_array_32[XED_REG_TMP0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP1]= XED_REG_TMP1; + xed_largest_enclosing_register_array_32[XED_REG_TMP1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP2]= XED_REG_TMP2; + xed_largest_enclosing_register_array_32[XED_REG_TMP2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP3]= XED_REG_TMP3; + xed_largest_enclosing_register_array_32[XED_REG_TMP3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP4]= XED_REG_TMP4; + xed_largest_enclosing_register_array_32[XED_REG_TMP4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP5]= XED_REG_TMP5; + xed_largest_enclosing_register_array_32[XED_REG_TMP5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP6]= XED_REG_TMP6; + xed_largest_enclosing_register_array_32[XED_REG_TMP6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP7]= XED_REG_TMP7; + xed_largest_enclosing_register_array_32[XED_REG_TMP7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP8]= XED_REG_TMP8; + xed_largest_enclosing_register_array_32[XED_REG_TMP8]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP9]= XED_REG_TMP9; + xed_largest_enclosing_register_array_32[XED_REG_TMP9]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP10]= XED_REG_TMP10; + xed_largest_enclosing_register_array_32[XED_REG_TMP10]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP11]= XED_REG_TMP11; + xed_largest_enclosing_register_array_32[XED_REG_TMP11]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP12]= XED_REG_TMP12; + xed_largest_enclosing_register_array_32[XED_REG_TMP12]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP13]= XED_REG_TMP13; + xed_largest_enclosing_register_array_32[XED_REG_TMP13]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP14]= XED_REG_TMP14; + xed_largest_enclosing_register_array_32[XED_REG_TMP14]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMP15]= XED_REG_TMP15; + xed_largest_enclosing_register_array_32[XED_REG_TMP15]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K0]= XED_REG_K0; + xed_largest_enclosing_register_array_32[XED_REG_K0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K1]= XED_REG_K1; + xed_largest_enclosing_register_array_32[XED_REG_K1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K2]= XED_REG_K2; + xed_largest_enclosing_register_array_32[XED_REG_K2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K3]= XED_REG_K3; + xed_largest_enclosing_register_array_32[XED_REG_K3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K4]= XED_REG_K4; + xed_largest_enclosing_register_array_32[XED_REG_K4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K5]= XED_REG_K5; + xed_largest_enclosing_register_array_32[XED_REG_K5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K6]= XED_REG_K6; + xed_largest_enclosing_register_array_32[XED_REG_K6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_K7]= XED_REG_K7; + xed_largest_enclosing_register_array_32[XED_REG_K7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_BND0]= XED_REG_BND0; + xed_largest_enclosing_register_array_32[XED_REG_BND0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_BND1]= XED_REG_BND1; + xed_largest_enclosing_register_array_32[XED_REG_BND1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_BND2]= XED_REG_BND2; + xed_largest_enclosing_register_array_32[XED_REG_BND2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_BND3]= XED_REG_BND3; + xed_largest_enclosing_register_array_32[XED_REG_BND3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_BNDCFGU]= XED_REG_BNDCFGU; + xed_largest_enclosing_register_array_32[XED_REG_BNDCFGU]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_BNDSTATUS]= XED_REG_BNDSTATUS; + xed_largest_enclosing_register_array_32[XED_REG_BNDSTATUS]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_SSP]= XED_REG_SSP; + xed_largest_enclosing_register_array_32[XED_REG_SSP]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_IA32_U_CET]= XED_REG_IA32_U_CET; + xed_largest_enclosing_register_array_32[XED_REG_IA32_U_CET]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_FSBASE]= XED_REG_FSBASE; + xed_largest_enclosing_register_array_32[XED_REG_FSBASE]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_GSBASE]= XED_REG_GSBASE; + xed_largest_enclosing_register_array_32[XED_REG_GSBASE]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM0]= XED_REG_ZMM0; + xed_largest_enclosing_register_array_32[XED_REG_XMM0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM1]= XED_REG_ZMM1; + xed_largest_enclosing_register_array_32[XED_REG_XMM1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM2]= XED_REG_ZMM2; + xed_largest_enclosing_register_array_32[XED_REG_XMM2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM3]= XED_REG_ZMM3; + xed_largest_enclosing_register_array_32[XED_REG_XMM3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM4]= XED_REG_ZMM4; + xed_largest_enclosing_register_array_32[XED_REG_XMM4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM5]= XED_REG_ZMM5; + xed_largest_enclosing_register_array_32[XED_REG_XMM5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM6]= XED_REG_ZMM6; + xed_largest_enclosing_register_array_32[XED_REG_XMM6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM7]= XED_REG_ZMM7; + xed_largest_enclosing_register_array_32[XED_REG_XMM7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM8]= XED_REG_ZMM8; + xed_largest_enclosing_register_array_32[XED_REG_XMM8]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM9]= XED_REG_ZMM9; + xed_largest_enclosing_register_array_32[XED_REG_XMM9]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM10]= XED_REG_ZMM10; + xed_largest_enclosing_register_array_32[XED_REG_XMM10]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM11]= XED_REG_ZMM11; + xed_largest_enclosing_register_array_32[XED_REG_XMM11]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM12]= XED_REG_ZMM12; + xed_largest_enclosing_register_array_32[XED_REG_XMM12]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM13]= XED_REG_ZMM13; + xed_largest_enclosing_register_array_32[XED_REG_XMM13]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM14]= XED_REG_ZMM14; + xed_largest_enclosing_register_array_32[XED_REG_XMM14]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM15]= XED_REG_ZMM15; + xed_largest_enclosing_register_array_32[XED_REG_XMM15]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM0]= XED_REG_ZMM0; + xed_largest_enclosing_register_array_32[XED_REG_YMM0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM1]= XED_REG_ZMM1; + xed_largest_enclosing_register_array_32[XED_REG_YMM1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM2]= XED_REG_ZMM2; + xed_largest_enclosing_register_array_32[XED_REG_YMM2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM3]= XED_REG_ZMM3; + xed_largest_enclosing_register_array_32[XED_REG_YMM3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM4]= XED_REG_ZMM4; + xed_largest_enclosing_register_array_32[XED_REG_YMM4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM5]= XED_REG_ZMM5; + xed_largest_enclosing_register_array_32[XED_REG_YMM5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM6]= XED_REG_ZMM6; + xed_largest_enclosing_register_array_32[XED_REG_YMM6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM7]= XED_REG_ZMM7; + xed_largest_enclosing_register_array_32[XED_REG_YMM7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM8]= XED_REG_ZMM8; + xed_largest_enclosing_register_array_32[XED_REG_YMM8]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM9]= XED_REG_ZMM9; + xed_largest_enclosing_register_array_32[XED_REG_YMM9]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM10]= XED_REG_ZMM10; + xed_largest_enclosing_register_array_32[XED_REG_YMM10]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM11]= XED_REG_ZMM11; + xed_largest_enclosing_register_array_32[XED_REG_YMM11]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM12]= XED_REG_ZMM12; + xed_largest_enclosing_register_array_32[XED_REG_YMM12]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM13]= XED_REG_ZMM13; + xed_largest_enclosing_register_array_32[XED_REG_YMM13]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM14]= XED_REG_ZMM14; + xed_largest_enclosing_register_array_32[XED_REG_YMM14]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM15]= XED_REG_ZMM15; + xed_largest_enclosing_register_array_32[XED_REG_YMM15]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM0]= XED_REG_ZMM0; + xed_largest_enclosing_register_array_32[XED_REG_ZMM0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM1]= XED_REG_ZMM1; + xed_largest_enclosing_register_array_32[XED_REG_ZMM1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM2]= XED_REG_ZMM2; + xed_largest_enclosing_register_array_32[XED_REG_ZMM2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM3]= XED_REG_ZMM3; + xed_largest_enclosing_register_array_32[XED_REG_ZMM3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM4]= XED_REG_ZMM4; + xed_largest_enclosing_register_array_32[XED_REG_ZMM4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM5]= XED_REG_ZMM5; + xed_largest_enclosing_register_array_32[XED_REG_ZMM5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM6]= XED_REG_ZMM6; + xed_largest_enclosing_register_array_32[XED_REG_ZMM6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM7]= XED_REG_ZMM7; + xed_largest_enclosing_register_array_32[XED_REG_ZMM7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM8]= XED_REG_ZMM8; + xed_largest_enclosing_register_array_32[XED_REG_ZMM8]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM9]= XED_REG_ZMM9; + xed_largest_enclosing_register_array_32[XED_REG_ZMM9]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM10]= XED_REG_ZMM10; + xed_largest_enclosing_register_array_32[XED_REG_ZMM10]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM11]= XED_REG_ZMM11; + xed_largest_enclosing_register_array_32[XED_REG_ZMM11]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM12]= XED_REG_ZMM12; + xed_largest_enclosing_register_array_32[XED_REG_ZMM12]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM13]= XED_REG_ZMM13; + xed_largest_enclosing_register_array_32[XED_REG_ZMM13]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM14]= XED_REG_ZMM14; + xed_largest_enclosing_register_array_32[XED_REG_ZMM14]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM15]= XED_REG_ZMM15; + xed_largest_enclosing_register_array_32[XED_REG_ZMM15]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM16]= XED_REG_ZMM16; + xed_largest_enclosing_register_array_32[XED_REG_ZMM16]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM17]= XED_REG_ZMM17; + xed_largest_enclosing_register_array_32[XED_REG_ZMM17]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM18]= XED_REG_ZMM18; + xed_largest_enclosing_register_array_32[XED_REG_ZMM18]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM19]= XED_REG_ZMM19; + xed_largest_enclosing_register_array_32[XED_REG_ZMM19]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM20]= XED_REG_ZMM20; + xed_largest_enclosing_register_array_32[XED_REG_ZMM20]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM21]= XED_REG_ZMM21; + xed_largest_enclosing_register_array_32[XED_REG_ZMM21]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM22]= XED_REG_ZMM22; + xed_largest_enclosing_register_array_32[XED_REG_ZMM22]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM23]= XED_REG_ZMM23; + xed_largest_enclosing_register_array_32[XED_REG_ZMM23]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM24]= XED_REG_ZMM24; + xed_largest_enclosing_register_array_32[XED_REG_ZMM24]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM25]= XED_REG_ZMM25; + xed_largest_enclosing_register_array_32[XED_REG_ZMM25]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM26]= XED_REG_ZMM26; + xed_largest_enclosing_register_array_32[XED_REG_ZMM26]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM27]= XED_REG_ZMM27; + xed_largest_enclosing_register_array_32[XED_REG_ZMM27]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM28]= XED_REG_ZMM28; + xed_largest_enclosing_register_array_32[XED_REG_ZMM28]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM29]= XED_REG_ZMM29; + xed_largest_enclosing_register_array_32[XED_REG_ZMM29]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM30]= XED_REG_ZMM30; + xed_largest_enclosing_register_array_32[XED_REG_ZMM30]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_ZMM31]= XED_REG_ZMM31; + xed_largest_enclosing_register_array_32[XED_REG_ZMM31]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM16]= XED_REG_ZMM16; + xed_largest_enclosing_register_array_32[XED_REG_XMM16]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM17]= XED_REG_ZMM17; + xed_largest_enclosing_register_array_32[XED_REG_XMM17]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM18]= XED_REG_ZMM18; + xed_largest_enclosing_register_array_32[XED_REG_XMM18]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM19]= XED_REG_ZMM19; + xed_largest_enclosing_register_array_32[XED_REG_XMM19]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM20]= XED_REG_ZMM20; + xed_largest_enclosing_register_array_32[XED_REG_XMM20]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM21]= XED_REG_ZMM21; + xed_largest_enclosing_register_array_32[XED_REG_XMM21]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM22]= XED_REG_ZMM22; + xed_largest_enclosing_register_array_32[XED_REG_XMM22]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM23]= XED_REG_ZMM23; + xed_largest_enclosing_register_array_32[XED_REG_XMM23]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM24]= XED_REG_ZMM24; + xed_largest_enclosing_register_array_32[XED_REG_XMM24]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM25]= XED_REG_ZMM25; + xed_largest_enclosing_register_array_32[XED_REG_XMM25]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM26]= XED_REG_ZMM26; + xed_largest_enclosing_register_array_32[XED_REG_XMM26]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM27]= XED_REG_ZMM27; + xed_largest_enclosing_register_array_32[XED_REG_XMM27]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM28]= XED_REG_ZMM28; + xed_largest_enclosing_register_array_32[XED_REG_XMM28]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM29]= XED_REG_ZMM29; + xed_largest_enclosing_register_array_32[XED_REG_XMM29]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM30]= XED_REG_ZMM30; + xed_largest_enclosing_register_array_32[XED_REG_XMM30]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_XMM31]= XED_REG_ZMM31; + xed_largest_enclosing_register_array_32[XED_REG_XMM31]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM16]= XED_REG_ZMM16; + xed_largest_enclosing_register_array_32[XED_REG_YMM16]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM17]= XED_REG_ZMM17; + xed_largest_enclosing_register_array_32[XED_REG_YMM17]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM18]= XED_REG_ZMM18; + xed_largest_enclosing_register_array_32[XED_REG_YMM18]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM19]= XED_REG_ZMM19; + xed_largest_enclosing_register_array_32[XED_REG_YMM19]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM20]= XED_REG_ZMM20; + xed_largest_enclosing_register_array_32[XED_REG_YMM20]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM21]= XED_REG_ZMM21; + xed_largest_enclosing_register_array_32[XED_REG_YMM21]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM22]= XED_REG_ZMM22; + xed_largest_enclosing_register_array_32[XED_REG_YMM22]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM23]= XED_REG_ZMM23; + xed_largest_enclosing_register_array_32[XED_REG_YMM23]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM24]= XED_REG_ZMM24; + xed_largest_enclosing_register_array_32[XED_REG_YMM24]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM25]= XED_REG_ZMM25; + xed_largest_enclosing_register_array_32[XED_REG_YMM25]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM26]= XED_REG_ZMM26; + xed_largest_enclosing_register_array_32[XED_REG_YMM26]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM27]= XED_REG_ZMM27; + xed_largest_enclosing_register_array_32[XED_REG_YMM27]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM28]= XED_REG_ZMM28; + xed_largest_enclosing_register_array_32[XED_REG_YMM28]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM29]= XED_REG_ZMM29; + xed_largest_enclosing_register_array_32[XED_REG_YMM29]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM30]= XED_REG_ZMM30; + xed_largest_enclosing_register_array_32[XED_REG_YMM30]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_YMM31]= XED_REG_ZMM31; + xed_largest_enclosing_register_array_32[XED_REG_YMM31]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_UIF]= XED_REG_UIF; + xed_largest_enclosing_register_array_32[XED_REG_UIF]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM0]= XED_REG_TMM0; + xed_largest_enclosing_register_array_32[XED_REG_TMM0]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM1]= XED_REG_TMM1; + xed_largest_enclosing_register_array_32[XED_REG_TMM1]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM2]= XED_REG_TMM2; + xed_largest_enclosing_register_array_32[XED_REG_TMM2]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM3]= XED_REG_TMM3; + xed_largest_enclosing_register_array_32[XED_REG_TMM3]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM4]= XED_REG_TMM4; + xed_largest_enclosing_register_array_32[XED_REG_TMM4]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM5]= XED_REG_TMM5; + xed_largest_enclosing_register_array_32[XED_REG_TMM5]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM6]= XED_REG_TMM6; + xed_largest_enclosing_register_array_32[XED_REG_TMM6]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TMM7]= XED_REG_TMM7; + xed_largest_enclosing_register_array_32[XED_REG_TMM7]= XED_REG_INVALID; + xed_largest_enclosing_register_array[XED_REG_TILECONFIG]= XED_REG_TILECONFIG; + xed_largest_enclosing_register_array_32[XED_REG_TILECONFIG]= XED_REG_INVALID; + xed_gpr_reg_class_array[XED_REG_RAX]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_EAX]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_AX]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_AH]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_AL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RCX]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_ECX]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_CX]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_CH]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_CL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RDX]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_EDX]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_DX]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_DH]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_DL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RBX]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_EBX]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_BX]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_BH]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_BL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RSP]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_ESP]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_SP]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_SPL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RBP]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_EBP]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_BP]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_BPL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RSI]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_ESI]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_SI]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_SIL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_RDI]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_EDI]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_DI]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_DIL]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R8]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R8D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R8W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R8B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R9]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R9D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R9W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R9B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R10]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R10D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R10W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R10B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R11]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R11D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R11W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R11B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R12]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R12D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R12W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R12B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R13]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R13D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R13W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R13B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R14]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R14D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R14W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R14B]= XED_REG_CLASS_GPR8; + xed_gpr_reg_class_array[XED_REG_R15]= XED_REG_CLASS_GPR64; + xed_gpr_reg_class_array[XED_REG_R15D]= XED_REG_CLASS_GPR32; + xed_gpr_reg_class_array[XED_REG_R15W]= XED_REG_CLASS_GPR16; + xed_gpr_reg_class_array[XED_REG_R15B]= XED_REG_CLASS_GPR8; + xed_reg_width_bits[XED_REG_INVALID][0] = 0; + xed_reg_width_bits[XED_REG_INVALID][1] = 0; + xed_reg_width_bits[XED_REG_ERROR][0] = 0; + xed_reg_width_bits[XED_REG_ERROR][1] = 0; + xed_reg_width_bits[XED_REG_RAX][0] = 64; + xed_reg_width_bits[XED_REG_RAX][1] = 64; + xed_reg_width_bits[XED_REG_EAX][0] = 32; + xed_reg_width_bits[XED_REG_EAX][1] = 32; + xed_reg_width_bits[XED_REG_AX][0] = 16; + xed_reg_width_bits[XED_REG_AX][1] = 16; + xed_reg_width_bits[XED_REG_AH][0] = 8; + xed_reg_width_bits[XED_REG_AH][1] = 8; + xed_reg_width_bits[XED_REG_AL][0] = 8; + xed_reg_width_bits[XED_REG_AL][1] = 8; + xed_reg_width_bits[XED_REG_RCX][0] = 64; + xed_reg_width_bits[XED_REG_RCX][1] = 64; + xed_reg_width_bits[XED_REG_ECX][0] = 32; + xed_reg_width_bits[XED_REG_ECX][1] = 32; + xed_reg_width_bits[XED_REG_CX][0] = 16; + xed_reg_width_bits[XED_REG_CX][1] = 16; + xed_reg_width_bits[XED_REG_CH][0] = 8; + xed_reg_width_bits[XED_REG_CH][1] = 8; + xed_reg_width_bits[XED_REG_CL][0] = 8; + xed_reg_width_bits[XED_REG_CL][1] = 8; + xed_reg_width_bits[XED_REG_RDX][0] = 64; + xed_reg_width_bits[XED_REG_RDX][1] = 64; + xed_reg_width_bits[XED_REG_EDX][0] = 32; + xed_reg_width_bits[XED_REG_EDX][1] = 32; + xed_reg_width_bits[XED_REG_DX][0] = 16; + xed_reg_width_bits[XED_REG_DX][1] = 16; + xed_reg_width_bits[XED_REG_DH][0] = 8; + xed_reg_width_bits[XED_REG_DH][1] = 8; + xed_reg_width_bits[XED_REG_DL][0] = 8; + xed_reg_width_bits[XED_REG_DL][1] = 8; + xed_reg_width_bits[XED_REG_RBX][0] = 64; + xed_reg_width_bits[XED_REG_RBX][1] = 64; + xed_reg_width_bits[XED_REG_EBX][0] = 32; + xed_reg_width_bits[XED_REG_EBX][1] = 32; + xed_reg_width_bits[XED_REG_BX][0] = 16; + xed_reg_width_bits[XED_REG_BX][1] = 16; + xed_reg_width_bits[XED_REG_BH][0] = 8; + xed_reg_width_bits[XED_REG_BH][1] = 8; + xed_reg_width_bits[XED_REG_BL][0] = 8; + xed_reg_width_bits[XED_REG_BL][1] = 8; + xed_reg_width_bits[XED_REG_RSP][0] = 64; + xed_reg_width_bits[XED_REG_RSP][1] = 64; + xed_reg_width_bits[XED_REG_ESP][0] = 32; + xed_reg_width_bits[XED_REG_ESP][1] = 32; + xed_reg_width_bits[XED_REG_SP][0] = 16; + xed_reg_width_bits[XED_REG_SP][1] = 16; + xed_reg_width_bits[XED_REG_SPL][0] = 8; + xed_reg_width_bits[XED_REG_SPL][1] = 8; + xed_reg_width_bits[XED_REG_RBP][0] = 64; + xed_reg_width_bits[XED_REG_RBP][1] = 64; + xed_reg_width_bits[XED_REG_EBP][0] = 32; + xed_reg_width_bits[XED_REG_EBP][1] = 32; + xed_reg_width_bits[XED_REG_BP][0] = 16; + xed_reg_width_bits[XED_REG_BP][1] = 16; + xed_reg_width_bits[XED_REG_BPL][0] = 8; + xed_reg_width_bits[XED_REG_BPL][1] = 8; + xed_reg_width_bits[XED_REG_RSI][0] = 64; + xed_reg_width_bits[XED_REG_RSI][1] = 64; + xed_reg_width_bits[XED_REG_ESI][0] = 32; + xed_reg_width_bits[XED_REG_ESI][1] = 32; + xed_reg_width_bits[XED_REG_SI][0] = 16; + xed_reg_width_bits[XED_REG_SI][1] = 16; + xed_reg_width_bits[XED_REG_SIL][0] = 8; + xed_reg_width_bits[XED_REG_SIL][1] = 8; + xed_reg_width_bits[XED_REG_RDI][0] = 64; + xed_reg_width_bits[XED_REG_RDI][1] = 64; + xed_reg_width_bits[XED_REG_EDI][0] = 32; + xed_reg_width_bits[XED_REG_EDI][1] = 32; + xed_reg_width_bits[XED_REG_DI][0] = 16; + xed_reg_width_bits[XED_REG_DI][1] = 16; + xed_reg_width_bits[XED_REG_DIL][0] = 8; + xed_reg_width_bits[XED_REG_DIL][1] = 8; + xed_reg_width_bits[XED_REG_R8][0] = 64; + xed_reg_width_bits[XED_REG_R8][1] = 64; + xed_reg_width_bits[XED_REG_R8D][0] = 32; + xed_reg_width_bits[XED_REG_R8D][1] = 32; + xed_reg_width_bits[XED_REG_R8W][0] = 16; + xed_reg_width_bits[XED_REG_R8W][1] = 16; + xed_reg_width_bits[XED_REG_R8B][0] = 8; + xed_reg_width_bits[XED_REG_R8B][1] = 8; + xed_reg_width_bits[XED_REG_R9][0] = 64; + xed_reg_width_bits[XED_REG_R9][1] = 64; + xed_reg_width_bits[XED_REG_R9D][0] = 32; + xed_reg_width_bits[XED_REG_R9D][1] = 32; + xed_reg_width_bits[XED_REG_R9W][0] = 16; + xed_reg_width_bits[XED_REG_R9W][1] = 16; + xed_reg_width_bits[XED_REG_R9B][0] = 8; + xed_reg_width_bits[XED_REG_R9B][1] = 8; + xed_reg_width_bits[XED_REG_R10][0] = 64; + xed_reg_width_bits[XED_REG_R10][1] = 64; + xed_reg_width_bits[XED_REG_R10D][0] = 32; + xed_reg_width_bits[XED_REG_R10D][1] = 32; + xed_reg_width_bits[XED_REG_R10W][0] = 16; + xed_reg_width_bits[XED_REG_R10W][1] = 16; + xed_reg_width_bits[XED_REG_R10B][0] = 8; + xed_reg_width_bits[XED_REG_R10B][1] = 8; + xed_reg_width_bits[XED_REG_R11][0] = 64; + xed_reg_width_bits[XED_REG_R11][1] = 64; + xed_reg_width_bits[XED_REG_R11D][0] = 32; + xed_reg_width_bits[XED_REG_R11D][1] = 32; + xed_reg_width_bits[XED_REG_R11W][0] = 16; + xed_reg_width_bits[XED_REG_R11W][1] = 16; + xed_reg_width_bits[XED_REG_R11B][0] = 8; + xed_reg_width_bits[XED_REG_R11B][1] = 8; + xed_reg_width_bits[XED_REG_R12][0] = 64; + xed_reg_width_bits[XED_REG_R12][1] = 64; + xed_reg_width_bits[XED_REG_R12D][0] = 32; + xed_reg_width_bits[XED_REG_R12D][1] = 32; + xed_reg_width_bits[XED_REG_R12W][0] = 16; + xed_reg_width_bits[XED_REG_R12W][1] = 16; + xed_reg_width_bits[XED_REG_R12B][0] = 8; + xed_reg_width_bits[XED_REG_R12B][1] = 8; + xed_reg_width_bits[XED_REG_R13][0] = 64; + xed_reg_width_bits[XED_REG_R13][1] = 64; + xed_reg_width_bits[XED_REG_R13D][0] = 32; + xed_reg_width_bits[XED_REG_R13D][1] = 32; + xed_reg_width_bits[XED_REG_R13W][0] = 16; + xed_reg_width_bits[XED_REG_R13W][1] = 16; + xed_reg_width_bits[XED_REG_R13B][0] = 8; + xed_reg_width_bits[XED_REG_R13B][1] = 8; + xed_reg_width_bits[XED_REG_R14][0] = 64; + xed_reg_width_bits[XED_REG_R14][1] = 64; + xed_reg_width_bits[XED_REG_R14D][0] = 32; + xed_reg_width_bits[XED_REG_R14D][1] = 32; + xed_reg_width_bits[XED_REG_R14W][0] = 16; + xed_reg_width_bits[XED_REG_R14W][1] = 16; + xed_reg_width_bits[XED_REG_R14B][0] = 8; + xed_reg_width_bits[XED_REG_R14B][1] = 8; + xed_reg_width_bits[XED_REG_R15][0] = 64; + xed_reg_width_bits[XED_REG_R15][1] = 64; + xed_reg_width_bits[XED_REG_R15D][0] = 32; + xed_reg_width_bits[XED_REG_R15D][1] = 32; + xed_reg_width_bits[XED_REG_R15W][0] = 16; + xed_reg_width_bits[XED_REG_R15W][1] = 16; + xed_reg_width_bits[XED_REG_R15B][0] = 8; + xed_reg_width_bits[XED_REG_R15B][1] = 8; + xed_reg_width_bits[XED_REG_RIP][0] = 64; + xed_reg_width_bits[XED_REG_RIP][1] = 64; + xed_reg_width_bits[XED_REG_EIP][0] = 32; + xed_reg_width_bits[XED_REG_EIP][1] = 32; + xed_reg_width_bits[XED_REG_IP][0] = 16; + xed_reg_width_bits[XED_REG_IP][1] = 16; + xed_reg_width_bits[XED_REG_FLAGS][0] = 16; + xed_reg_width_bits[XED_REG_FLAGS][1] = 16; + xed_reg_width_bits[XED_REG_EFLAGS][0] = 32; + xed_reg_width_bits[XED_REG_EFLAGS][1] = 32; + xed_reg_width_bits[XED_REG_RFLAGS][0] = 64; + xed_reg_width_bits[XED_REG_RFLAGS][1] = 64; + xed_reg_width_bits[XED_REG_ES][0] = 16; + xed_reg_width_bits[XED_REG_ES][1] = 16; + xed_reg_width_bits[XED_REG_CS][0] = 16; + xed_reg_width_bits[XED_REG_CS][1] = 16; + xed_reg_width_bits[XED_REG_SS][0] = 16; + xed_reg_width_bits[XED_REG_SS][1] = 16; + xed_reg_width_bits[XED_REG_DS][0] = 16; + xed_reg_width_bits[XED_REG_DS][1] = 16; + xed_reg_width_bits[XED_REG_FS][0] = 16; + xed_reg_width_bits[XED_REG_FS][1] = 16; + xed_reg_width_bits[XED_REG_GS][0] = 16; + xed_reg_width_bits[XED_REG_GS][1] = 16; + xed_reg_width_bits[XED_REG_MMX0][0] = 64; + xed_reg_width_bits[XED_REG_MMX0][1] = 64; + xed_reg_width_bits[XED_REG_MMX1][0] = 64; + xed_reg_width_bits[XED_REG_MMX1][1] = 64; + xed_reg_width_bits[XED_REG_MMX2][0] = 64; + xed_reg_width_bits[XED_REG_MMX2][1] = 64; + xed_reg_width_bits[XED_REG_MMX3][0] = 64; + xed_reg_width_bits[XED_REG_MMX3][1] = 64; + xed_reg_width_bits[XED_REG_MMX4][0] = 64; + xed_reg_width_bits[XED_REG_MMX4][1] = 64; + xed_reg_width_bits[XED_REG_MMX5][0] = 64; + xed_reg_width_bits[XED_REG_MMX5][1] = 64; + xed_reg_width_bits[XED_REG_MMX6][0] = 64; + xed_reg_width_bits[XED_REG_MMX6][1] = 64; + xed_reg_width_bits[XED_REG_MMX7][0] = 64; + xed_reg_width_bits[XED_REG_MMX7][1] = 64; + xed_reg_width_bits[XED_REG_ST0][0] = 80; + xed_reg_width_bits[XED_REG_ST0][1] = 80; + xed_reg_width_bits[XED_REG_ST1][0] = 80; + xed_reg_width_bits[XED_REG_ST1][1] = 80; + xed_reg_width_bits[XED_REG_ST2][0] = 80; + xed_reg_width_bits[XED_REG_ST2][1] = 80; + xed_reg_width_bits[XED_REG_ST3][0] = 80; + xed_reg_width_bits[XED_REG_ST3][1] = 80; + xed_reg_width_bits[XED_REG_ST4][0] = 80; + xed_reg_width_bits[XED_REG_ST4][1] = 80; + xed_reg_width_bits[XED_REG_ST5][0] = 80; + xed_reg_width_bits[XED_REG_ST5][1] = 80; + xed_reg_width_bits[XED_REG_ST6][0] = 80; + xed_reg_width_bits[XED_REG_ST6][1] = 80; + xed_reg_width_bits[XED_REG_ST7][0] = 80; + xed_reg_width_bits[XED_REG_ST7][1] = 80; + xed_reg_width_bits[XED_REG_CR0][0] = 32; + xed_reg_width_bits[XED_REG_CR0][1] = 64; + xed_reg_width_bits[XED_REG_CR1][0] = 32; + xed_reg_width_bits[XED_REG_CR1][1] = 64; + xed_reg_width_bits[XED_REG_CR2][0] = 32; + xed_reg_width_bits[XED_REG_CR2][1] = 64; + xed_reg_width_bits[XED_REG_CR3][0] = 32; + xed_reg_width_bits[XED_REG_CR3][1] = 64; + xed_reg_width_bits[XED_REG_CR4][0] = 32; + xed_reg_width_bits[XED_REG_CR4][1] = 64; + xed_reg_width_bits[XED_REG_CR5][0] = 32; + xed_reg_width_bits[XED_REG_CR5][1] = 64; + xed_reg_width_bits[XED_REG_CR6][0] = 32; + xed_reg_width_bits[XED_REG_CR6][1] = 64; + xed_reg_width_bits[XED_REG_CR7][0] = 32; + xed_reg_width_bits[XED_REG_CR7][1] = 64; + xed_reg_width_bits[XED_REG_CR8][0] = 32; + xed_reg_width_bits[XED_REG_CR8][1] = 64; + xed_reg_width_bits[XED_REG_CR9][0] = 32; + xed_reg_width_bits[XED_REG_CR9][1] = 64; + xed_reg_width_bits[XED_REG_CR10][0] = 32; + xed_reg_width_bits[XED_REG_CR10][1] = 64; + xed_reg_width_bits[XED_REG_CR11][0] = 32; + xed_reg_width_bits[XED_REG_CR11][1] = 64; + xed_reg_width_bits[XED_REG_CR12][0] = 32; + xed_reg_width_bits[XED_REG_CR12][1] = 64; + xed_reg_width_bits[XED_REG_CR13][0] = 32; + xed_reg_width_bits[XED_REG_CR13][1] = 64; + xed_reg_width_bits[XED_REG_CR14][0] = 32; + xed_reg_width_bits[XED_REG_CR14][1] = 64; + xed_reg_width_bits[XED_REG_CR15][0] = 32; + xed_reg_width_bits[XED_REG_CR15][1] = 64; + xed_reg_width_bits[XED_REG_DR0][0] = 32; + xed_reg_width_bits[XED_REG_DR0][1] = 64; + xed_reg_width_bits[XED_REG_DR1][0] = 32; + xed_reg_width_bits[XED_REG_DR1][1] = 64; + xed_reg_width_bits[XED_REG_DR2][0] = 32; + xed_reg_width_bits[XED_REG_DR2][1] = 64; + xed_reg_width_bits[XED_REG_DR3][0] = 32; + xed_reg_width_bits[XED_REG_DR3][1] = 64; + xed_reg_width_bits[XED_REG_DR4][0] = 32; + xed_reg_width_bits[XED_REG_DR4][1] = 64; + xed_reg_width_bits[XED_REG_DR5][0] = 32; + xed_reg_width_bits[XED_REG_DR5][1] = 64; + xed_reg_width_bits[XED_REG_DR6][0] = 32; + xed_reg_width_bits[XED_REG_DR6][1] = 64; + xed_reg_width_bits[XED_REG_DR7][0] = 32; + xed_reg_width_bits[XED_REG_DR7][1] = 64; + xed_reg_width_bits[XED_REG_STACKPUSH][0] = 0; + xed_reg_width_bits[XED_REG_STACKPUSH][1] = 0; + xed_reg_width_bits[XED_REG_STACKPOP][0] = 0; + xed_reg_width_bits[XED_REG_STACKPOP][1] = 0; + xed_reg_width_bits[XED_REG_GDTR][0] = 80; + xed_reg_width_bits[XED_REG_GDTR][1] = 80; + xed_reg_width_bits[XED_REG_LDTR][0] = 80; + xed_reg_width_bits[XED_REG_LDTR][1] = 80; + xed_reg_width_bits[XED_REG_IDTR][0] = 80; + xed_reg_width_bits[XED_REG_IDTR][1] = 80; + xed_reg_width_bits[XED_REG_TR][0] = 80; + xed_reg_width_bits[XED_REG_TR][1] = 80; + xed_reg_width_bits[XED_REG_TSC][0] = 32; + xed_reg_width_bits[XED_REG_TSC][1] = 32; + xed_reg_width_bits[XED_REG_TSCAUX][0] = 32; + xed_reg_width_bits[XED_REG_TSCAUX][1] = 32; + xed_reg_width_bits[XED_REG_MSRS][0] = 0; + xed_reg_width_bits[XED_REG_MSRS][1] = 0; + xed_reg_width_bits[XED_REG_X87CONTROL][0] = 16; + xed_reg_width_bits[XED_REG_X87CONTROL][1] = 16; + xed_reg_width_bits[XED_REG_X87STATUS][0] = 16; + xed_reg_width_bits[XED_REG_X87STATUS][1] = 16; + xed_reg_width_bits[XED_REG_X87TAG][0] = 16; + xed_reg_width_bits[XED_REG_X87TAG][1] = 16; + xed_reg_width_bits[XED_REG_X87PUSH][0] = 0; + xed_reg_width_bits[XED_REG_X87PUSH][1] = 0; + xed_reg_width_bits[XED_REG_X87POP][0] = 0; + xed_reg_width_bits[XED_REG_X87POP][1] = 0; + xed_reg_width_bits[XED_REG_X87POP2][0] = 0; + xed_reg_width_bits[XED_REG_X87POP2][1] = 0; + xed_reg_width_bits[XED_REG_X87OPCODE][0] = 11; + xed_reg_width_bits[XED_REG_X87OPCODE][1] = 11; + xed_reg_width_bits[XED_REG_X87LASTCS][0] = 16; + xed_reg_width_bits[XED_REG_X87LASTCS][1] = 16; + xed_reg_width_bits[XED_REG_X87LASTIP][0] = 32; + xed_reg_width_bits[XED_REG_X87LASTIP][1] = 64; + xed_reg_width_bits[XED_REG_X87LASTDS][0] = 16; + xed_reg_width_bits[XED_REG_X87LASTDS][1] = 16; + xed_reg_width_bits[XED_REG_X87LASTDP][0] = 32; + xed_reg_width_bits[XED_REG_X87LASTDP][1] = 64; + xed_reg_width_bits[XED_REG_XCR0][0] = 64; + xed_reg_width_bits[XED_REG_XCR0][1] = 64; + xed_reg_width_bits[XED_REG_MXCSR][0] = 32; + xed_reg_width_bits[XED_REG_MXCSR][1] = 32; + xed_reg_width_bits[XED_REG_TMP0][0] = 0; + xed_reg_width_bits[XED_REG_TMP0][1] = 0; + xed_reg_width_bits[XED_REG_TMP1][0] = 0; + xed_reg_width_bits[XED_REG_TMP1][1] = 0; + xed_reg_width_bits[XED_REG_TMP2][0] = 0; + xed_reg_width_bits[XED_REG_TMP2][1] = 0; + xed_reg_width_bits[XED_REG_TMP3][0] = 0; + xed_reg_width_bits[XED_REG_TMP3][1] = 0; + xed_reg_width_bits[XED_REG_TMP4][0] = 0; + xed_reg_width_bits[XED_REG_TMP4][1] = 0; + xed_reg_width_bits[XED_REG_TMP5][0] = 0; + xed_reg_width_bits[XED_REG_TMP5][1] = 0; + xed_reg_width_bits[XED_REG_TMP6][0] = 0; + xed_reg_width_bits[XED_REG_TMP6][1] = 0; + xed_reg_width_bits[XED_REG_TMP7][0] = 0; + xed_reg_width_bits[XED_REG_TMP7][1] = 0; + xed_reg_width_bits[XED_REG_TMP8][0] = 0; + xed_reg_width_bits[XED_REG_TMP8][1] = 0; + xed_reg_width_bits[XED_REG_TMP9][0] = 0; + xed_reg_width_bits[XED_REG_TMP9][1] = 0; + xed_reg_width_bits[XED_REG_TMP10][0] = 0; + xed_reg_width_bits[XED_REG_TMP10][1] = 0; + xed_reg_width_bits[XED_REG_TMP11][0] = 0; + xed_reg_width_bits[XED_REG_TMP11][1] = 0; + xed_reg_width_bits[XED_REG_TMP12][0] = 0; + xed_reg_width_bits[XED_REG_TMP12][1] = 0; + xed_reg_width_bits[XED_REG_TMP13][0] = 0; + xed_reg_width_bits[XED_REG_TMP13][1] = 0; + xed_reg_width_bits[XED_REG_TMP14][0] = 0; + xed_reg_width_bits[XED_REG_TMP14][1] = 0; + xed_reg_width_bits[XED_REG_TMP15][0] = 0; + xed_reg_width_bits[XED_REG_TMP15][1] = 0; + xed_reg_width_bits[XED_REG_K0][0] = 64; + xed_reg_width_bits[XED_REG_K0][1] = 64; + xed_reg_width_bits[XED_REG_K1][0] = 64; + xed_reg_width_bits[XED_REG_K1][1] = 64; + xed_reg_width_bits[XED_REG_K2][0] = 64; + xed_reg_width_bits[XED_REG_K2][1] = 64; + xed_reg_width_bits[XED_REG_K3][0] = 64; + xed_reg_width_bits[XED_REG_K3][1] = 64; + xed_reg_width_bits[XED_REG_K4][0] = 64; + xed_reg_width_bits[XED_REG_K4][1] = 64; + xed_reg_width_bits[XED_REG_K5][0] = 64; + xed_reg_width_bits[XED_REG_K5][1] = 64; + xed_reg_width_bits[XED_REG_K6][0] = 64; + xed_reg_width_bits[XED_REG_K6][1] = 64; + xed_reg_width_bits[XED_REG_K7][0] = 64; + xed_reg_width_bits[XED_REG_K7][1] = 64; + xed_reg_width_bits[XED_REG_BND0][0] = 128; + xed_reg_width_bits[XED_REG_BND0][1] = 128; + xed_reg_width_bits[XED_REG_BND1][0] = 128; + xed_reg_width_bits[XED_REG_BND1][1] = 128; + xed_reg_width_bits[XED_REG_BND2][0] = 128; + xed_reg_width_bits[XED_REG_BND2][1] = 128; + xed_reg_width_bits[XED_REG_BND3][0] = 128; + xed_reg_width_bits[XED_REG_BND3][1] = 128; + xed_reg_width_bits[XED_REG_BNDCFGU][0] = 64; + xed_reg_width_bits[XED_REG_BNDCFGU][1] = 64; + xed_reg_width_bits[XED_REG_BNDSTATUS][0] = 64; + xed_reg_width_bits[XED_REG_BNDSTATUS][1] = 64; + xed_reg_width_bits[XED_REG_SSP][0] = 32; + xed_reg_width_bits[XED_REG_SSP][1] = 64; + xed_reg_width_bits[XED_REG_IA32_U_CET][0] = 0; + xed_reg_width_bits[XED_REG_IA32_U_CET][1] = 0; + xed_reg_width_bits[XED_REG_FSBASE][0] = 0; + xed_reg_width_bits[XED_REG_FSBASE][1] = 0; + xed_reg_width_bits[XED_REG_GSBASE][0] = 0; + xed_reg_width_bits[XED_REG_GSBASE][1] = 0; + xed_reg_width_bits[XED_REG_XMM0][0] = 128; + xed_reg_width_bits[XED_REG_XMM0][1] = 128; + xed_reg_width_bits[XED_REG_XMM1][0] = 128; + xed_reg_width_bits[XED_REG_XMM1][1] = 128; + xed_reg_width_bits[XED_REG_XMM2][0] = 128; + xed_reg_width_bits[XED_REG_XMM2][1] = 128; + xed_reg_width_bits[XED_REG_XMM3][0] = 128; + xed_reg_width_bits[XED_REG_XMM3][1] = 128; + xed_reg_width_bits[XED_REG_XMM4][0] = 128; + xed_reg_width_bits[XED_REG_XMM4][1] = 128; + xed_reg_width_bits[XED_REG_XMM5][0] = 128; + xed_reg_width_bits[XED_REG_XMM5][1] = 128; + xed_reg_width_bits[XED_REG_XMM6][0] = 128; + xed_reg_width_bits[XED_REG_XMM6][1] = 128; + xed_reg_width_bits[XED_REG_XMM7][0] = 128; + xed_reg_width_bits[XED_REG_XMM7][1] = 128; + xed_reg_width_bits[XED_REG_XMM8][0] = 128; + xed_reg_width_bits[XED_REG_XMM8][1] = 128; + xed_reg_width_bits[XED_REG_XMM9][0] = 128; + xed_reg_width_bits[XED_REG_XMM9][1] = 128; + xed_reg_width_bits[XED_REG_XMM10][0] = 128; + xed_reg_width_bits[XED_REG_XMM10][1] = 128; + xed_reg_width_bits[XED_REG_XMM11][0] = 128; + xed_reg_width_bits[XED_REG_XMM11][1] = 128; + xed_reg_width_bits[XED_REG_XMM12][0] = 128; + xed_reg_width_bits[XED_REG_XMM12][1] = 128; + xed_reg_width_bits[XED_REG_XMM13][0] = 128; + xed_reg_width_bits[XED_REG_XMM13][1] = 128; + xed_reg_width_bits[XED_REG_XMM14][0] = 128; + xed_reg_width_bits[XED_REG_XMM14][1] = 128; + xed_reg_width_bits[XED_REG_XMM15][0] = 128; + xed_reg_width_bits[XED_REG_XMM15][1] = 128; + xed_reg_width_bits[XED_REG_YMM0][0] = 256; + xed_reg_width_bits[XED_REG_YMM0][1] = 256; + xed_reg_width_bits[XED_REG_YMM1][0] = 256; + xed_reg_width_bits[XED_REG_YMM1][1] = 256; + xed_reg_width_bits[XED_REG_YMM2][0] = 256; + xed_reg_width_bits[XED_REG_YMM2][1] = 256; + xed_reg_width_bits[XED_REG_YMM3][0] = 256; + xed_reg_width_bits[XED_REG_YMM3][1] = 256; + xed_reg_width_bits[XED_REG_YMM4][0] = 256; + xed_reg_width_bits[XED_REG_YMM4][1] = 256; + xed_reg_width_bits[XED_REG_YMM5][0] = 256; + xed_reg_width_bits[XED_REG_YMM5][1] = 256; + xed_reg_width_bits[XED_REG_YMM6][0] = 256; + xed_reg_width_bits[XED_REG_YMM6][1] = 256; + xed_reg_width_bits[XED_REG_YMM7][0] = 256; + xed_reg_width_bits[XED_REG_YMM7][1] = 256; + xed_reg_width_bits[XED_REG_YMM8][0] = 256; + xed_reg_width_bits[XED_REG_YMM8][1] = 256; + xed_reg_width_bits[XED_REG_YMM9][0] = 256; + xed_reg_width_bits[XED_REG_YMM9][1] = 256; + xed_reg_width_bits[XED_REG_YMM10][0] = 256; + xed_reg_width_bits[XED_REG_YMM10][1] = 256; + xed_reg_width_bits[XED_REG_YMM11][0] = 256; + xed_reg_width_bits[XED_REG_YMM11][1] = 256; + xed_reg_width_bits[XED_REG_YMM12][0] = 256; + xed_reg_width_bits[XED_REG_YMM12][1] = 256; + xed_reg_width_bits[XED_REG_YMM13][0] = 256; + xed_reg_width_bits[XED_REG_YMM13][1] = 256; + xed_reg_width_bits[XED_REG_YMM14][0] = 256; + xed_reg_width_bits[XED_REG_YMM14][1] = 256; + xed_reg_width_bits[XED_REG_YMM15][0] = 256; + xed_reg_width_bits[XED_REG_YMM15][1] = 256; + xed_reg_width_bits[XED_REG_ZMM0][0] = 512; + xed_reg_width_bits[XED_REG_ZMM0][1] = 512; + xed_reg_width_bits[XED_REG_ZMM1][0] = 512; + xed_reg_width_bits[XED_REG_ZMM1][1] = 512; + xed_reg_width_bits[XED_REG_ZMM2][0] = 512; + xed_reg_width_bits[XED_REG_ZMM2][1] = 512; + xed_reg_width_bits[XED_REG_ZMM3][0] = 512; + xed_reg_width_bits[XED_REG_ZMM3][1] = 512; + xed_reg_width_bits[XED_REG_ZMM4][0] = 512; + xed_reg_width_bits[XED_REG_ZMM4][1] = 512; + xed_reg_width_bits[XED_REG_ZMM5][0] = 512; + xed_reg_width_bits[XED_REG_ZMM5][1] = 512; + xed_reg_width_bits[XED_REG_ZMM6][0] = 512; + xed_reg_width_bits[XED_REG_ZMM6][1] = 512; + xed_reg_width_bits[XED_REG_ZMM7][0] = 512; + xed_reg_width_bits[XED_REG_ZMM7][1] = 512; + xed_reg_width_bits[XED_REG_ZMM8][0] = 512; + xed_reg_width_bits[XED_REG_ZMM8][1] = 512; + xed_reg_width_bits[XED_REG_ZMM9][0] = 512; + xed_reg_width_bits[XED_REG_ZMM9][1] = 512; + xed_reg_width_bits[XED_REG_ZMM10][0] = 512; + xed_reg_width_bits[XED_REG_ZMM10][1] = 512; + xed_reg_width_bits[XED_REG_ZMM11][0] = 512; + xed_reg_width_bits[XED_REG_ZMM11][1] = 512; + xed_reg_width_bits[XED_REG_ZMM12][0] = 512; + xed_reg_width_bits[XED_REG_ZMM12][1] = 512; + xed_reg_width_bits[XED_REG_ZMM13][0] = 512; + xed_reg_width_bits[XED_REG_ZMM13][1] = 512; + xed_reg_width_bits[XED_REG_ZMM14][0] = 512; + xed_reg_width_bits[XED_REG_ZMM14][1] = 512; + xed_reg_width_bits[XED_REG_ZMM15][0] = 512; + xed_reg_width_bits[XED_REG_ZMM15][1] = 512; + xed_reg_width_bits[XED_REG_ZMM16][0] = 512; + xed_reg_width_bits[XED_REG_ZMM16][1] = 512; + xed_reg_width_bits[XED_REG_ZMM17][0] = 512; + xed_reg_width_bits[XED_REG_ZMM17][1] = 512; + xed_reg_width_bits[XED_REG_ZMM18][0] = 512; + xed_reg_width_bits[XED_REG_ZMM18][1] = 512; + xed_reg_width_bits[XED_REG_ZMM19][0] = 512; + xed_reg_width_bits[XED_REG_ZMM19][1] = 512; + xed_reg_width_bits[XED_REG_ZMM20][0] = 512; + xed_reg_width_bits[XED_REG_ZMM20][1] = 512; + xed_reg_width_bits[XED_REG_ZMM21][0] = 512; + xed_reg_width_bits[XED_REG_ZMM21][1] = 512; + xed_reg_width_bits[XED_REG_ZMM22][0] = 512; + xed_reg_width_bits[XED_REG_ZMM22][1] = 512; + xed_reg_width_bits[XED_REG_ZMM23][0] = 512; + xed_reg_width_bits[XED_REG_ZMM23][1] = 512; + xed_reg_width_bits[XED_REG_ZMM24][0] = 512; + xed_reg_width_bits[XED_REG_ZMM24][1] = 512; + xed_reg_width_bits[XED_REG_ZMM25][0] = 512; + xed_reg_width_bits[XED_REG_ZMM25][1] = 512; + xed_reg_width_bits[XED_REG_ZMM26][0] = 512; + xed_reg_width_bits[XED_REG_ZMM26][1] = 512; + xed_reg_width_bits[XED_REG_ZMM27][0] = 512; + xed_reg_width_bits[XED_REG_ZMM27][1] = 512; + xed_reg_width_bits[XED_REG_ZMM28][0] = 512; + xed_reg_width_bits[XED_REG_ZMM28][1] = 512; + xed_reg_width_bits[XED_REG_ZMM29][0] = 512; + xed_reg_width_bits[XED_REG_ZMM29][1] = 512; + xed_reg_width_bits[XED_REG_ZMM30][0] = 512; + xed_reg_width_bits[XED_REG_ZMM30][1] = 512; + xed_reg_width_bits[XED_REG_ZMM31][0] = 512; + xed_reg_width_bits[XED_REG_ZMM31][1] = 512; + xed_reg_width_bits[XED_REG_XMM16][0] = 128; + xed_reg_width_bits[XED_REG_XMM16][1] = 128; + xed_reg_width_bits[XED_REG_XMM17][0] = 128; + xed_reg_width_bits[XED_REG_XMM17][1] = 128; + xed_reg_width_bits[XED_REG_XMM18][0] = 128; + xed_reg_width_bits[XED_REG_XMM18][1] = 128; + xed_reg_width_bits[XED_REG_XMM19][0] = 128; + xed_reg_width_bits[XED_REG_XMM19][1] = 128; + xed_reg_width_bits[XED_REG_XMM20][0] = 128; + xed_reg_width_bits[XED_REG_XMM20][1] = 128; + xed_reg_width_bits[XED_REG_XMM21][0] = 128; + xed_reg_width_bits[XED_REG_XMM21][1] = 128; + xed_reg_width_bits[XED_REG_XMM22][0] = 128; + xed_reg_width_bits[XED_REG_XMM22][1] = 128; + xed_reg_width_bits[XED_REG_XMM23][0] = 128; + xed_reg_width_bits[XED_REG_XMM23][1] = 128; + xed_reg_width_bits[XED_REG_XMM24][0] = 128; + xed_reg_width_bits[XED_REG_XMM24][1] = 128; + xed_reg_width_bits[XED_REG_XMM25][0] = 128; + xed_reg_width_bits[XED_REG_XMM25][1] = 128; + xed_reg_width_bits[XED_REG_XMM26][0] = 128; + xed_reg_width_bits[XED_REG_XMM26][1] = 128; + xed_reg_width_bits[XED_REG_XMM27][0] = 128; + xed_reg_width_bits[XED_REG_XMM27][1] = 128; + xed_reg_width_bits[XED_REG_XMM28][0] = 128; + xed_reg_width_bits[XED_REG_XMM28][1] = 128; + xed_reg_width_bits[XED_REG_XMM29][0] = 128; + xed_reg_width_bits[XED_REG_XMM29][1] = 128; + xed_reg_width_bits[XED_REG_XMM30][0] = 128; + xed_reg_width_bits[XED_REG_XMM30][1] = 128; + xed_reg_width_bits[XED_REG_XMM31][0] = 128; + xed_reg_width_bits[XED_REG_XMM31][1] = 128; + xed_reg_width_bits[XED_REG_YMM16][0] = 256; + xed_reg_width_bits[XED_REG_YMM16][1] = 256; + xed_reg_width_bits[XED_REG_YMM17][0] = 256; + xed_reg_width_bits[XED_REG_YMM17][1] = 256; + xed_reg_width_bits[XED_REG_YMM18][0] = 256; + xed_reg_width_bits[XED_REG_YMM18][1] = 256; + xed_reg_width_bits[XED_REG_YMM19][0] = 256; + xed_reg_width_bits[XED_REG_YMM19][1] = 256; + xed_reg_width_bits[XED_REG_YMM20][0] = 256; + xed_reg_width_bits[XED_REG_YMM20][1] = 256; + xed_reg_width_bits[XED_REG_YMM21][0] = 256; + xed_reg_width_bits[XED_REG_YMM21][1] = 256; + xed_reg_width_bits[XED_REG_YMM22][0] = 256; + xed_reg_width_bits[XED_REG_YMM22][1] = 256; + xed_reg_width_bits[XED_REG_YMM23][0] = 256; + xed_reg_width_bits[XED_REG_YMM23][1] = 256; + xed_reg_width_bits[XED_REG_YMM24][0] = 256; + xed_reg_width_bits[XED_REG_YMM24][1] = 256; + xed_reg_width_bits[XED_REG_YMM25][0] = 256; + xed_reg_width_bits[XED_REG_YMM25][1] = 256; + xed_reg_width_bits[XED_REG_YMM26][0] = 256; + xed_reg_width_bits[XED_REG_YMM26][1] = 256; + xed_reg_width_bits[XED_REG_YMM27][0] = 256; + xed_reg_width_bits[XED_REG_YMM27][1] = 256; + xed_reg_width_bits[XED_REG_YMM28][0] = 256; + xed_reg_width_bits[XED_REG_YMM28][1] = 256; + xed_reg_width_bits[XED_REG_YMM29][0] = 256; + xed_reg_width_bits[XED_REG_YMM29][1] = 256; + xed_reg_width_bits[XED_REG_YMM30][0] = 256; + xed_reg_width_bits[XED_REG_YMM30][1] = 256; + xed_reg_width_bits[XED_REG_YMM31][0] = 256; + xed_reg_width_bits[XED_REG_YMM31][1] = 256; + xed_reg_width_bits[XED_REG_UIF][0] = 1; + xed_reg_width_bits[XED_REG_UIF][1] = 1; + xed_reg_width_bits[XED_REG_TMM0][0] = 8192; + xed_reg_width_bits[XED_REG_TMM0][1] = 8192; + xed_reg_width_bits[XED_REG_TMM1][0] = 8192; + xed_reg_width_bits[XED_REG_TMM1][1] = 8192; + xed_reg_width_bits[XED_REG_TMM2][0] = 8192; + xed_reg_width_bits[XED_REG_TMM2][1] = 8192; + xed_reg_width_bits[XED_REG_TMM3][0] = 8192; + xed_reg_width_bits[XED_REG_TMM3][1] = 8192; + xed_reg_width_bits[XED_REG_TMM4][0] = 8192; + xed_reg_width_bits[XED_REG_TMM4][1] = 8192; + xed_reg_width_bits[XED_REG_TMM5][0] = 8192; + xed_reg_width_bits[XED_REG_TMM5][1] = 8192; + xed_reg_width_bits[XED_REG_TMM6][0] = 8192; + xed_reg_width_bits[XED_REG_TMM6][1] = 8192; + xed_reg_width_bits[XED_REG_TMM7][0] = 8192; + xed_reg_width_bits[XED_REG_TMM7][1] = 8192; + xed_reg_width_bits[XED_REG_TILECONFIG][0] = 512; + xed_reg_width_bits[XED_REG_TILECONFIG][1] = 512; +} diff --git a/CodeVirtualizer/build/obj/xed-init-width.c b/CodeVirtualizer/build/obj/xed-init-width.c new file mode 100644 index 0000000..5c4ed6a --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-init-width.c @@ -0,0 +1,538 @@ +/// @file xed-init-width.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +void xed_init_width_mappings(void) +{ + xed_width_bits[XED_OPERAND_WIDTH_INVALID][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_INVALID][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_INVALID][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_INVALID][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ASZ][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ASZ][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_ASZ][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_ASZ][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SSZ][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SSZ][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_SSZ][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SSZ][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDO][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDO][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDO][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDO][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDOX87][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDOX87][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDOX87][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PSEUDOX87][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_A16][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_A16][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_A16][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_A16][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_A32][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_A32][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_A32][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_A32][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_B][0] = 8; + xed_width_bits[XED_OPERAND_WIDTH_B][1] = 8; + xed_width_bits[XED_OPERAND_WIDTH_B][2] = 8; + xed_width_bits[XED_OPERAND_WIDTH_B][3] = 8; + xed_width_bits[XED_OPERAND_WIDTH_D][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_D][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_D][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_D][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_I8][0] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I8][1] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I8][2] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I8][3] = 8; + xed_width_bits[XED_OPERAND_WIDTH_U8][0] = 8; + xed_width_bits[XED_OPERAND_WIDTH_U8][1] = 8; + xed_width_bits[XED_OPERAND_WIDTH_U8][2] = 8; + xed_width_bits[XED_OPERAND_WIDTH_U8][3] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I16][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_I16][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_I16][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_I16][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_U16][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_U16][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_U16][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_U16][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_I32][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_I32][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_I32][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_I32][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_U32][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_U32][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_U32][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_U32][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_I64][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_I64][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_I64][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_I64][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_U64][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_U64][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_U64][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_U64][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_F16][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_F16][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_F16][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_F16][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_F32][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_F32][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_F32][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_F32][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_F64][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_F64][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_F64][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_F64][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_DQ][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_DQ][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_DQ][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_DQ][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUB][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUB][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUB][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUB][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUW][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUW][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUW][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUW][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUD][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUD][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUD][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUD][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUQ][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUQ][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUQ][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XUQ][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_X128][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_X128][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_X128][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_X128][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XB][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XB][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XB][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XB][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XW][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XW][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XW][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XW][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XD][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XD][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XD][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XD][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XQ][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XQ][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XQ][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_XQ][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_ZB][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZB][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZB][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZB][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZW][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZW][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZW][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZW][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZD][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZD][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZD][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZD][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZQ][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZQ][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZQ][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZQ][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_MB][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MB][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MB][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MB][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MW][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MW][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MW][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MW][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MD][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MD][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MD][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MD][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MQ][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MQ][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MQ][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MQ][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64INT][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64INT][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64INT][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64INT][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64REAL][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64REAL][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64REAL][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_M64REAL][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MEM108][0] = 864; + xed_width_bits[XED_OPERAND_WIDTH_MEM108][1] = 864; + xed_width_bits[XED_OPERAND_WIDTH_MEM108][2] = 864; + xed_width_bits[XED_OPERAND_WIDTH_MEM108][3] = 864; + xed_width_bits[XED_OPERAND_WIDTH_MEM14][0] = 112; + xed_width_bits[XED_OPERAND_WIDTH_MEM14][1] = 112; + xed_width_bits[XED_OPERAND_WIDTH_MEM14][2] = 112; + xed_width_bits[XED_OPERAND_WIDTH_MEM14][3] = 112; + xed_width_bits[XED_OPERAND_WIDTH_MEM16][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16INT][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16INT][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16INT][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM16INT][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MEM28][0] = 224; + xed_width_bits[XED_OPERAND_WIDTH_MEM28][1] = 224; + xed_width_bits[XED_OPERAND_WIDTH_MEM28][2] = 224; + xed_width_bits[XED_OPERAND_WIDTH_MEM28][3] = 224; + xed_width_bits[XED_OPERAND_WIDTH_MEM32INT][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32INT][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32INT][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32INT][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32REAL][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32REAL][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32REAL][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM32REAL][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_MEM80DEC][0] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80DEC][1] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80DEC][2] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80DEC][3] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80REAL][0] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80REAL][1] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80REAL][2] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM80REAL][3] = 80; + xed_width_bits[XED_OPERAND_WIDTH_F80][0] = 80; + xed_width_bits[XED_OPERAND_WIDTH_F80][1] = 80; + xed_width_bits[XED_OPERAND_WIDTH_F80][2] = 80; + xed_width_bits[XED_OPERAND_WIDTH_F80][3] = 80; + xed_width_bits[XED_OPERAND_WIDTH_MEM94][0] = 752; + xed_width_bits[XED_OPERAND_WIDTH_MEM94][1] = 752; + xed_width_bits[XED_OPERAND_WIDTH_MEM94][2] = 752; + xed_width_bits[XED_OPERAND_WIDTH_MEM94][3] = 752; + xed_width_bits[XED_OPERAND_WIDTH_MFPXENV][0] = 4096; + xed_width_bits[XED_OPERAND_WIDTH_MFPXENV][1] = 4096; + xed_width_bits[XED_OPERAND_WIDTH_MFPXENV][2] = 4096; + xed_width_bits[XED_OPERAND_WIDTH_MFPXENV][3] = 4096; + xed_width_bits[XED_OPERAND_WIDTH_MXSAVE][0] = 4608; + xed_width_bits[XED_OPERAND_WIDTH_MXSAVE][1] = 4608; + xed_width_bits[XED_OPERAND_WIDTH_MXSAVE][2] = 4608; + xed_width_bits[XED_OPERAND_WIDTH_MXSAVE][3] = 4608; + xed_width_bits[XED_OPERAND_WIDTH_MPREFETCH][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_MPREFETCH][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_MPREFETCH][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_MPREFETCH][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_P][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_P][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_P][2] = 48; + xed_width_bits[XED_OPERAND_WIDTH_P][3] = 48; + xed_width_bits[XED_OPERAND_WIDTH_P2][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_P2][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_P2][2] = 48; + xed_width_bits[XED_OPERAND_WIDTH_P2][3] = 80; + xed_width_bits[XED_OPERAND_WIDTH_PD][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PD][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PD][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PD][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PS][0] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PS][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PS][2] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PS][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_PI][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_PI][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_PI][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_PI][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_Q][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_Q][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_Q][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_Q][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_S][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_S][1] = 48; + xed_width_bits[XED_OPERAND_WIDTH_S][2] = 48; + xed_width_bits[XED_OPERAND_WIDTH_S][3] = 80; + xed_width_bits[XED_OPERAND_WIDTH_S64][0] = 80; + xed_width_bits[XED_OPERAND_WIDTH_S64][1] = 80; + xed_width_bits[XED_OPERAND_WIDTH_S64][2] = 80; + xed_width_bits[XED_OPERAND_WIDTH_S64][3] = 80; + xed_width_bits[XED_OPERAND_WIDTH_SD][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SD][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SD][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SD][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SI][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SI][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SI][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SI][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SS][0] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SS][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SS][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SS][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_V][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_V][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_V][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_V][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_Y][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_Y][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_Y][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_Y][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_W][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_W][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_W][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_W][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_Z][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_Z][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_Z][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_Z][3] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SPW8][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SPW8][1] = 128; + xed_width_bits[XED_OPERAND_WIDTH_SPW8][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_SPW8][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SPW][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SPW][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_SPW][2] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SPW][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SPW5][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SPW5][1] = 80; + xed_width_bits[XED_OPERAND_WIDTH_SPW5][2] = 160; + xed_width_bits[XED_OPERAND_WIDTH_SPW5][3] = 320; + xed_width_bits[XED_OPERAND_WIDTH_SPW3][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SPW3][1] = 48; + xed_width_bits[XED_OPERAND_WIDTH_SPW3][2] = 96; + xed_width_bits[XED_OPERAND_WIDTH_SPW3][3] = 192; + xed_width_bits[XED_OPERAND_WIDTH_SPW2][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_SPW2][1] = 32; + xed_width_bits[XED_OPERAND_WIDTH_SPW2][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_SPW2][3] = 128; + xed_width_bits[XED_OPERAND_WIDTH_I1][0] = 1; + xed_width_bits[XED_OPERAND_WIDTH_I1][1] = 1; + xed_width_bits[XED_OPERAND_WIDTH_I1][2] = 1; + xed_width_bits[XED_OPERAND_WIDTH_I1][3] = 1; + xed_width_bits[XED_OPERAND_WIDTH_I2][0] = 2; + xed_width_bits[XED_OPERAND_WIDTH_I2][1] = 2; + xed_width_bits[XED_OPERAND_WIDTH_I2][2] = 2; + xed_width_bits[XED_OPERAND_WIDTH_I2][3] = 2; + xed_width_bits[XED_OPERAND_WIDTH_I3][0] = 3; + xed_width_bits[XED_OPERAND_WIDTH_I3][1] = 3; + xed_width_bits[XED_OPERAND_WIDTH_I3][2] = 3; + xed_width_bits[XED_OPERAND_WIDTH_I3][3] = 3; + xed_width_bits[XED_OPERAND_WIDTH_I4][0] = 4; + xed_width_bits[XED_OPERAND_WIDTH_I4][1] = 4; + xed_width_bits[XED_OPERAND_WIDTH_I4][2] = 4; + xed_width_bits[XED_OPERAND_WIDTH_I4][3] = 4; + xed_width_bits[XED_OPERAND_WIDTH_I5][0] = 5; + xed_width_bits[XED_OPERAND_WIDTH_I5][1] = 5; + xed_width_bits[XED_OPERAND_WIDTH_I5][2] = 5; + xed_width_bits[XED_OPERAND_WIDTH_I5][3] = 5; + xed_width_bits[XED_OPERAND_WIDTH_I6][0] = 6; + xed_width_bits[XED_OPERAND_WIDTH_I6][1] = 6; + xed_width_bits[XED_OPERAND_WIDTH_I6][2] = 6; + xed_width_bits[XED_OPERAND_WIDTH_I6][3] = 6; + xed_width_bits[XED_OPERAND_WIDTH_I7][0] = 7; + xed_width_bits[XED_OPERAND_WIDTH_I7][1] = 7; + xed_width_bits[XED_OPERAND_WIDTH_I7][2] = 7; + xed_width_bits[XED_OPERAND_WIDTH_I7][3] = 7; + xed_width_bits[XED_OPERAND_WIDTH_I8][0] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I8][1] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I8][2] = 8; + xed_width_bits[XED_OPERAND_WIDTH_I8][3] = 8; + xed_width_bits[XED_OPERAND_WIDTH_VAR][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_VAR][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_VAR][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_VAR][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_BND32][0] = 96; + xed_width_bits[XED_OPERAND_WIDTH_BND32][1] = 96; + xed_width_bits[XED_OPERAND_WIDTH_BND32][2] = 96; + xed_width_bits[XED_OPERAND_WIDTH_BND32][3] = 96; + xed_width_bits[XED_OPERAND_WIDTH_BND64][0] = 192; + xed_width_bits[XED_OPERAND_WIDTH_BND64][1] = 192; + xed_width_bits[XED_OPERAND_WIDTH_BND64][2] = 192; + xed_width_bits[XED_OPERAND_WIDTH_BND64][3] = 192; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ16][0] = 112; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ16][1] = 112; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ16][2] = 112; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ16][3] = 112; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ32][0] = 192; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ32][1] = 192; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ32][2] = 192; + xed_width_bits[XED_OPERAND_WIDTH_PMMSZ32][3] = 192; + xed_width_bits[XED_OPERAND_WIDTH_QQ][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_QQ][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_QQ][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_QQ][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUB][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUB][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUB][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUB][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUW][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUW][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUW][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUW][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUD][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUD][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUD][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUD][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUQ][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUQ][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUQ][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YUQ][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_Y128][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_Y128][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_Y128][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_Y128][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YB][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YB][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YB][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YB][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YW][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YW][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YW][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YW][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YD][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YD][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YD][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YD][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YQ][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YQ][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YQ][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YQ][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPS][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPS][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPS][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPS][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPD][0] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPD][1] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPD][2] = 256; + xed_width_bits[XED_OPERAND_WIDTH_YPD][3] = 256; + xed_width_bits[XED_OPERAND_WIDTH_ZBF16][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZBF16][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZBF16][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZBF16][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_VV][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_VV][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_VV][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_VV][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ZV][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ZV][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ZV][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ZV][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_WRD][0] = 16; + xed_width_bits[XED_OPERAND_WIDTH_WRD][1] = 16; + xed_width_bits[XED_OPERAND_WIDTH_WRD][2] = 16; + xed_width_bits[XED_OPERAND_WIDTH_WRD][3] = 16; + xed_width_bits[XED_OPERAND_WIDTH_MSKW][0] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MSKW][1] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MSKW][2] = 64; + xed_width_bits[XED_OPERAND_WIDTH_MSKW][3] = 64; + xed_width_bits[XED_OPERAND_WIDTH_ZMSKW][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZMSKW][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZMSKW][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZMSKW][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF32][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF32][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF32][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF32][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF64][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF64][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF64][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF64][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUB][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUB][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUB][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUB][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUW][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUW][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUW][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUW][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUD][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUD][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUD][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUD][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUQ][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUQ][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUQ][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZUQ][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI8][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI8][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI8][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI8][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI16][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI16][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI16][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI16][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI32][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI32][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI32][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI32][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI64][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI64][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI64][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZI64][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU8][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU8][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU8][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU8][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU16][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU16][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU16][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU16][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU32][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU32][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU32][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU32][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU64][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU64][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU64][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU64][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU128][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU128][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU128][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZU128][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_M384][0] = 384; + xed_width_bits[XED_OPERAND_WIDTH_M384][1] = 384; + xed_width_bits[XED_OPERAND_WIDTH_M384][2] = 384; + xed_width_bits[XED_OPERAND_WIDTH_M384][3] = 384; + xed_width_bits[XED_OPERAND_WIDTH_M512][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_M512][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_M512][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_M512][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_PTR][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PTR][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PTR][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_PTR][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMROW][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMROW][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMROW][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMROW][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMCOL][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMCOL][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMCOL][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TMEMCOL][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TV][0] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TV][1] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TV][2] = 0; + xed_width_bits[XED_OPERAND_WIDTH_TV][3] = 0; + xed_width_bits[XED_OPERAND_WIDTH_ZF16][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF16][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF16][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_ZF16][3] = 512; + xed_width_bits[XED_OPERAND_WIDTH_Z2F16][0] = 512; + xed_width_bits[XED_OPERAND_WIDTH_Z2F16][1] = 512; + xed_width_bits[XED_OPERAND_WIDTH_Z2F16][2] = 512; + xed_width_bits[XED_OPERAND_WIDTH_Z2F16][3] = 512; +} diff --git a/CodeVirtualizer/build/obj/xed-isa-set-enum.c b/CodeVirtualizer/build/obj/xed-isa-set-enum.c new file mode 100644 index 0000000..c89a1a3 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-isa-set-enum.c @@ -0,0 +1,420 @@ +/// @file xed-isa-set-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-isa-set-enum.h" + +typedef struct { + const char* name; + xed_isa_set_enum_t value; +} name_table_xed_isa_set_enum_t; +static const name_table_xed_isa_set_enum_t name_array_xed_isa_set_enum_t[] = { +{"INVALID", XED_ISA_SET_INVALID}, +{"3DNOW", XED_ISA_SET_3DNOW}, +{"3DNOW_PREFETCH", XED_ISA_SET_3DNOW_PREFETCH}, +{"ADOX_ADCX", XED_ISA_SET_ADOX_ADCX}, +{"AES", XED_ISA_SET_AES}, +{"AMD", XED_ISA_SET_AMD}, +{"AMD_INVLPGB", XED_ISA_SET_AMD_INVLPGB}, +{"AMX_BF16", XED_ISA_SET_AMX_BF16}, +{"AMX_INT8", XED_ISA_SET_AMX_INT8}, +{"AMX_TILE", XED_ISA_SET_AMX_TILE}, +{"AVX", XED_ISA_SET_AVX}, +{"AVX2", XED_ISA_SET_AVX2}, +{"AVX2GATHER", XED_ISA_SET_AVX2GATHER}, +{"AVX512BW_128", XED_ISA_SET_AVX512BW_128}, +{"AVX512BW_128N", XED_ISA_SET_AVX512BW_128N}, +{"AVX512BW_256", XED_ISA_SET_AVX512BW_256}, +{"AVX512BW_512", XED_ISA_SET_AVX512BW_512}, +{"AVX512BW_KOP", XED_ISA_SET_AVX512BW_KOP}, +{"AVX512CD_128", XED_ISA_SET_AVX512CD_128}, +{"AVX512CD_256", XED_ISA_SET_AVX512CD_256}, +{"AVX512CD_512", XED_ISA_SET_AVX512CD_512}, +{"AVX512DQ_128", XED_ISA_SET_AVX512DQ_128}, +{"AVX512DQ_128N", XED_ISA_SET_AVX512DQ_128N}, +{"AVX512DQ_256", XED_ISA_SET_AVX512DQ_256}, +{"AVX512DQ_512", XED_ISA_SET_AVX512DQ_512}, +{"AVX512DQ_KOP", XED_ISA_SET_AVX512DQ_KOP}, +{"AVX512DQ_SCALAR", XED_ISA_SET_AVX512DQ_SCALAR}, +{"AVX512ER_512", XED_ISA_SET_AVX512ER_512}, +{"AVX512ER_SCALAR", XED_ISA_SET_AVX512ER_SCALAR}, +{"AVX512F_128", XED_ISA_SET_AVX512F_128}, +{"AVX512F_128N", XED_ISA_SET_AVX512F_128N}, +{"AVX512F_256", XED_ISA_SET_AVX512F_256}, +{"AVX512F_512", XED_ISA_SET_AVX512F_512}, +{"AVX512F_KOP", XED_ISA_SET_AVX512F_KOP}, +{"AVX512F_SCALAR", XED_ISA_SET_AVX512F_SCALAR}, +{"AVX512PF_512", XED_ISA_SET_AVX512PF_512}, +{"AVX512_4FMAPS_512", XED_ISA_SET_AVX512_4FMAPS_512}, +{"AVX512_4FMAPS_SCALAR", XED_ISA_SET_AVX512_4FMAPS_SCALAR}, +{"AVX512_4VNNIW_512", XED_ISA_SET_AVX512_4VNNIW_512}, +{"AVX512_BF16_128", XED_ISA_SET_AVX512_BF16_128}, +{"AVX512_BF16_256", XED_ISA_SET_AVX512_BF16_256}, +{"AVX512_BF16_512", XED_ISA_SET_AVX512_BF16_512}, +{"AVX512_BITALG_128", XED_ISA_SET_AVX512_BITALG_128}, +{"AVX512_BITALG_256", XED_ISA_SET_AVX512_BITALG_256}, +{"AVX512_BITALG_512", XED_ISA_SET_AVX512_BITALG_512}, +{"AVX512_FP16_128", XED_ISA_SET_AVX512_FP16_128}, +{"AVX512_FP16_128N", XED_ISA_SET_AVX512_FP16_128N}, +{"AVX512_FP16_256", XED_ISA_SET_AVX512_FP16_256}, +{"AVX512_FP16_512", XED_ISA_SET_AVX512_FP16_512}, +{"AVX512_FP16_SCALAR", XED_ISA_SET_AVX512_FP16_SCALAR}, +{"AVX512_GFNI_128", XED_ISA_SET_AVX512_GFNI_128}, +{"AVX512_GFNI_256", XED_ISA_SET_AVX512_GFNI_256}, +{"AVX512_GFNI_512", XED_ISA_SET_AVX512_GFNI_512}, +{"AVX512_IFMA_128", XED_ISA_SET_AVX512_IFMA_128}, +{"AVX512_IFMA_256", XED_ISA_SET_AVX512_IFMA_256}, +{"AVX512_IFMA_512", XED_ISA_SET_AVX512_IFMA_512}, +{"AVX512_VAES_128", XED_ISA_SET_AVX512_VAES_128}, +{"AVX512_VAES_256", XED_ISA_SET_AVX512_VAES_256}, +{"AVX512_VAES_512", XED_ISA_SET_AVX512_VAES_512}, +{"AVX512_VBMI2_128", XED_ISA_SET_AVX512_VBMI2_128}, +{"AVX512_VBMI2_256", XED_ISA_SET_AVX512_VBMI2_256}, +{"AVX512_VBMI2_512", XED_ISA_SET_AVX512_VBMI2_512}, +{"AVX512_VBMI_128", XED_ISA_SET_AVX512_VBMI_128}, +{"AVX512_VBMI_256", XED_ISA_SET_AVX512_VBMI_256}, +{"AVX512_VBMI_512", XED_ISA_SET_AVX512_VBMI_512}, +{"AVX512_VNNI_128", XED_ISA_SET_AVX512_VNNI_128}, +{"AVX512_VNNI_256", XED_ISA_SET_AVX512_VNNI_256}, +{"AVX512_VNNI_512", XED_ISA_SET_AVX512_VNNI_512}, +{"AVX512_VP2INTERSECT_128", XED_ISA_SET_AVX512_VP2INTERSECT_128}, +{"AVX512_VP2INTERSECT_256", XED_ISA_SET_AVX512_VP2INTERSECT_256}, +{"AVX512_VP2INTERSECT_512", XED_ISA_SET_AVX512_VP2INTERSECT_512}, +{"AVX512_VPCLMULQDQ_128", XED_ISA_SET_AVX512_VPCLMULQDQ_128}, +{"AVX512_VPCLMULQDQ_256", XED_ISA_SET_AVX512_VPCLMULQDQ_256}, +{"AVX512_VPCLMULQDQ_512", XED_ISA_SET_AVX512_VPCLMULQDQ_512}, +{"AVX512_VPOPCNTDQ_128", XED_ISA_SET_AVX512_VPOPCNTDQ_128}, +{"AVX512_VPOPCNTDQ_256", XED_ISA_SET_AVX512_VPOPCNTDQ_256}, +{"AVX512_VPOPCNTDQ_512", XED_ISA_SET_AVX512_VPOPCNTDQ_512}, +{"AVXAES", XED_ISA_SET_AVXAES}, +{"AVX_GFNI", XED_ISA_SET_AVX_GFNI}, +{"AVX_VNNI", XED_ISA_SET_AVX_VNNI}, +{"BMI1", XED_ISA_SET_BMI1}, +{"BMI2", XED_ISA_SET_BMI2}, +{"CET", XED_ISA_SET_CET}, +{"CLDEMOTE", XED_ISA_SET_CLDEMOTE}, +{"CLFLUSHOPT", XED_ISA_SET_CLFLUSHOPT}, +{"CLFSH", XED_ISA_SET_CLFSH}, +{"CLWB", XED_ISA_SET_CLWB}, +{"CLZERO", XED_ISA_SET_CLZERO}, +{"CMOV", XED_ISA_SET_CMOV}, +{"CMPXCHG16B", XED_ISA_SET_CMPXCHG16B}, +{"ENQCMD", XED_ISA_SET_ENQCMD}, +{"F16C", XED_ISA_SET_F16C}, +{"FAT_NOP", XED_ISA_SET_FAT_NOP}, +{"FCMOV", XED_ISA_SET_FCMOV}, +{"FMA", XED_ISA_SET_FMA}, +{"FMA4", XED_ISA_SET_FMA4}, +{"FXSAVE", XED_ISA_SET_FXSAVE}, +{"FXSAVE64", XED_ISA_SET_FXSAVE64}, +{"GFNI", XED_ISA_SET_GFNI}, +{"HRESET", XED_ISA_SET_HRESET}, +{"I186", XED_ISA_SET_I186}, +{"I286PROTECTED", XED_ISA_SET_I286PROTECTED}, +{"I286REAL", XED_ISA_SET_I286REAL}, +{"I386", XED_ISA_SET_I386}, +{"I486", XED_ISA_SET_I486}, +{"I486REAL", XED_ISA_SET_I486REAL}, +{"I86", XED_ISA_SET_I86}, +{"INVPCID", XED_ISA_SET_INVPCID}, +{"KEYLOCKER", XED_ISA_SET_KEYLOCKER}, +{"KEYLOCKER_WIDE", XED_ISA_SET_KEYLOCKER_WIDE}, +{"LAHF", XED_ISA_SET_LAHF}, +{"LONGMODE", XED_ISA_SET_LONGMODE}, +{"LWP", XED_ISA_SET_LWP}, +{"LZCNT", XED_ISA_SET_LZCNT}, +{"MCOMMIT", XED_ISA_SET_MCOMMIT}, +{"MONITOR", XED_ISA_SET_MONITOR}, +{"MONITORX", XED_ISA_SET_MONITORX}, +{"MOVBE", XED_ISA_SET_MOVBE}, +{"MOVDIR", XED_ISA_SET_MOVDIR}, +{"MPX", XED_ISA_SET_MPX}, +{"PAUSE", XED_ISA_SET_PAUSE}, +{"PCLMULQDQ", XED_ISA_SET_PCLMULQDQ}, +{"PCONFIG", XED_ISA_SET_PCONFIG}, +{"PENTIUMMMX", XED_ISA_SET_PENTIUMMMX}, +{"PENTIUMREAL", XED_ISA_SET_PENTIUMREAL}, +{"PKU", XED_ISA_SET_PKU}, +{"POPCNT", XED_ISA_SET_POPCNT}, +{"PPRO", XED_ISA_SET_PPRO}, +{"PPRO_UD0_LONG", XED_ISA_SET_PPRO_UD0_LONG}, +{"PPRO_UD0_SHORT", XED_ISA_SET_PPRO_UD0_SHORT}, +{"PREFETCHW", XED_ISA_SET_PREFETCHW}, +{"PREFETCHWT1", XED_ISA_SET_PREFETCHWT1}, +{"PREFETCH_NOP", XED_ISA_SET_PREFETCH_NOP}, +{"PTWRITE", XED_ISA_SET_PTWRITE}, +{"RDPID", XED_ISA_SET_RDPID}, +{"RDPMC", XED_ISA_SET_RDPMC}, +{"RDPRU", XED_ISA_SET_RDPRU}, +{"RDRAND", XED_ISA_SET_RDRAND}, +{"RDSEED", XED_ISA_SET_RDSEED}, +{"RDTSCP", XED_ISA_SET_RDTSCP}, +{"RDWRFSGS", XED_ISA_SET_RDWRFSGS}, +{"RTM", XED_ISA_SET_RTM}, +{"SERIALIZE", XED_ISA_SET_SERIALIZE}, +{"SGX", XED_ISA_SET_SGX}, +{"SGX_ENCLV", XED_ISA_SET_SGX_ENCLV}, +{"SHA", XED_ISA_SET_SHA}, +{"SMAP", XED_ISA_SET_SMAP}, +{"SMX", XED_ISA_SET_SMX}, +{"SNP", XED_ISA_SET_SNP}, +{"SSE", XED_ISA_SET_SSE}, +{"SSE2", XED_ISA_SET_SSE2}, +{"SSE2MMX", XED_ISA_SET_SSE2MMX}, +{"SSE3", XED_ISA_SET_SSE3}, +{"SSE3X87", XED_ISA_SET_SSE3X87}, +{"SSE4", XED_ISA_SET_SSE4}, +{"SSE42", XED_ISA_SET_SSE42}, +{"SSE4A", XED_ISA_SET_SSE4A}, +{"SSEMXCSR", XED_ISA_SET_SSEMXCSR}, +{"SSE_PREFETCH", XED_ISA_SET_SSE_PREFETCH}, +{"SSSE3", XED_ISA_SET_SSSE3}, +{"SSSE3MMX", XED_ISA_SET_SSSE3MMX}, +{"SVM", XED_ISA_SET_SVM}, +{"TBM", XED_ISA_SET_TBM}, +{"TDX", XED_ISA_SET_TDX}, +{"TSX_LDTRK", XED_ISA_SET_TSX_LDTRK}, +{"UINTR", XED_ISA_SET_UINTR}, +{"VAES", XED_ISA_SET_VAES}, +{"VIA_PADLOCK_AES", XED_ISA_SET_VIA_PADLOCK_AES}, +{"VIA_PADLOCK_MONTMUL", XED_ISA_SET_VIA_PADLOCK_MONTMUL}, +{"VIA_PADLOCK_RNG", XED_ISA_SET_VIA_PADLOCK_RNG}, +{"VIA_PADLOCK_SHA", XED_ISA_SET_VIA_PADLOCK_SHA}, +{"VMFUNC", XED_ISA_SET_VMFUNC}, +{"VPCLMULQDQ", XED_ISA_SET_VPCLMULQDQ}, +{"VTX", XED_ISA_SET_VTX}, +{"WAITPKG", XED_ISA_SET_WAITPKG}, +{"WBNOINVD", XED_ISA_SET_WBNOINVD}, +{"X87", XED_ISA_SET_X87}, +{"XOP", XED_ISA_SET_XOP}, +{"XSAVE", XED_ISA_SET_XSAVE}, +{"XSAVEC", XED_ISA_SET_XSAVEC}, +{"XSAVEOPT", XED_ISA_SET_XSAVEOPT}, +{"XSAVES", XED_ISA_SET_XSAVES}, +{"LAST", XED_ISA_SET_LAST}, +{0, XED_ISA_SET_LAST}, +}; + + +xed_isa_set_enum_t str2xed_isa_set_enum_t(const char* s) +{ + const name_table_xed_isa_set_enum_t* p = name_array_xed_isa_set_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_ISA_SET_INVALID; +} + + +const char* xed_isa_set_enum_t2str(const xed_isa_set_enum_t p) +{ + xed_isa_set_enum_t type_idx = p; + if ( p > XED_ISA_SET_LAST) type_idx = XED_ISA_SET_LAST; + return name_array_xed_isa_set_enum_t[type_idx].name; +} + +xed_isa_set_enum_t xed_isa_set_enum_t_last(void) { + return XED_ISA_SET_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_ISA_SET_INVALID: + case XED_ISA_SET_3DNOW: + case XED_ISA_SET_3DNOW_PREFETCH: + case XED_ISA_SET_ADOX_ADCX: + case XED_ISA_SET_AES: + case XED_ISA_SET_AMD: + case XED_ISA_SET_AMD_INVLPGB: + case XED_ISA_SET_AMX_BF16: + case XED_ISA_SET_AMX_INT8: + case XED_ISA_SET_AMX_TILE: + case XED_ISA_SET_AVX: + case XED_ISA_SET_AVX2: + case XED_ISA_SET_AVX2GATHER: + case XED_ISA_SET_AVX512BW_128: + case XED_ISA_SET_AVX512BW_128N: + case XED_ISA_SET_AVX512BW_256: + case XED_ISA_SET_AVX512BW_512: + case XED_ISA_SET_AVX512BW_KOP: + case XED_ISA_SET_AVX512CD_128: + case XED_ISA_SET_AVX512CD_256: + case XED_ISA_SET_AVX512CD_512: + case XED_ISA_SET_AVX512DQ_128: + case XED_ISA_SET_AVX512DQ_128N: + case XED_ISA_SET_AVX512DQ_256: + case XED_ISA_SET_AVX512DQ_512: + case XED_ISA_SET_AVX512DQ_KOP: + case XED_ISA_SET_AVX512DQ_SCALAR: + case XED_ISA_SET_AVX512ER_512: + case XED_ISA_SET_AVX512ER_SCALAR: + case XED_ISA_SET_AVX512F_128: + case XED_ISA_SET_AVX512F_128N: + case XED_ISA_SET_AVX512F_256: + case XED_ISA_SET_AVX512F_512: + case XED_ISA_SET_AVX512F_KOP: + case XED_ISA_SET_AVX512F_SCALAR: + case XED_ISA_SET_AVX512PF_512: + case XED_ISA_SET_AVX512_4FMAPS_512: + case XED_ISA_SET_AVX512_4FMAPS_SCALAR: + case XED_ISA_SET_AVX512_4VNNIW_512: + case XED_ISA_SET_AVX512_BF16_128: + case XED_ISA_SET_AVX512_BF16_256: + case XED_ISA_SET_AVX512_BF16_512: + case XED_ISA_SET_AVX512_BITALG_128: + case XED_ISA_SET_AVX512_BITALG_256: + case XED_ISA_SET_AVX512_BITALG_512: + case XED_ISA_SET_AVX512_FP16_128: + case XED_ISA_SET_AVX512_FP16_128N: + case XED_ISA_SET_AVX512_FP16_256: + case XED_ISA_SET_AVX512_FP16_512: + case XED_ISA_SET_AVX512_FP16_SCALAR: + case XED_ISA_SET_AVX512_GFNI_128: + case XED_ISA_SET_AVX512_GFNI_256: + case XED_ISA_SET_AVX512_GFNI_512: + case XED_ISA_SET_AVX512_IFMA_128: + case XED_ISA_SET_AVX512_IFMA_256: + case XED_ISA_SET_AVX512_IFMA_512: + case XED_ISA_SET_AVX512_VAES_128: + case XED_ISA_SET_AVX512_VAES_256: + case XED_ISA_SET_AVX512_VAES_512: + case XED_ISA_SET_AVX512_VBMI2_128: + case XED_ISA_SET_AVX512_VBMI2_256: + case XED_ISA_SET_AVX512_VBMI2_512: + case XED_ISA_SET_AVX512_VBMI_128: + case XED_ISA_SET_AVX512_VBMI_256: + case XED_ISA_SET_AVX512_VBMI_512: + case XED_ISA_SET_AVX512_VNNI_128: + case XED_ISA_SET_AVX512_VNNI_256: + case XED_ISA_SET_AVX512_VNNI_512: + case XED_ISA_SET_AVX512_VP2INTERSECT_128: + case XED_ISA_SET_AVX512_VP2INTERSECT_256: + case XED_ISA_SET_AVX512_VP2INTERSECT_512: + case XED_ISA_SET_AVX512_VPCLMULQDQ_128: + case XED_ISA_SET_AVX512_VPCLMULQDQ_256: + case XED_ISA_SET_AVX512_VPCLMULQDQ_512: + case XED_ISA_SET_AVX512_VPOPCNTDQ_128: + case XED_ISA_SET_AVX512_VPOPCNTDQ_256: + case XED_ISA_SET_AVX512_VPOPCNTDQ_512: + case XED_ISA_SET_AVXAES: + case XED_ISA_SET_AVX_GFNI: + case XED_ISA_SET_AVX_VNNI: + case XED_ISA_SET_BMI1: + case XED_ISA_SET_BMI2: + case XED_ISA_SET_CET: + case XED_ISA_SET_CLDEMOTE: + case XED_ISA_SET_CLFLUSHOPT: + case XED_ISA_SET_CLFSH: + case XED_ISA_SET_CLWB: + case XED_ISA_SET_CLZERO: + case XED_ISA_SET_CMOV: + case XED_ISA_SET_CMPXCHG16B: + case XED_ISA_SET_ENQCMD: + case XED_ISA_SET_F16C: + case XED_ISA_SET_FAT_NOP: + case XED_ISA_SET_FCMOV: + case XED_ISA_SET_FMA: + case XED_ISA_SET_FMA4: + case XED_ISA_SET_FXSAVE: + case XED_ISA_SET_FXSAVE64: + case XED_ISA_SET_GFNI: + case XED_ISA_SET_HRESET: + case XED_ISA_SET_I186: + case XED_ISA_SET_I286PROTECTED: + case XED_ISA_SET_I286REAL: + case XED_ISA_SET_I386: + case XED_ISA_SET_I486: + case XED_ISA_SET_I486REAL: + case XED_ISA_SET_I86: + case XED_ISA_SET_INVPCID: + case XED_ISA_SET_KEYLOCKER: + case XED_ISA_SET_KEYLOCKER_WIDE: + case XED_ISA_SET_LAHF: + case XED_ISA_SET_LONGMODE: + case XED_ISA_SET_LWP: + case XED_ISA_SET_LZCNT: + case XED_ISA_SET_MCOMMIT: + case XED_ISA_SET_MONITOR: + case XED_ISA_SET_MONITORX: + case XED_ISA_SET_MOVBE: + case XED_ISA_SET_MOVDIR: + case XED_ISA_SET_MPX: + case XED_ISA_SET_PAUSE: + case XED_ISA_SET_PCLMULQDQ: + case XED_ISA_SET_PCONFIG: + case XED_ISA_SET_PENTIUMMMX: + case XED_ISA_SET_PENTIUMREAL: + case XED_ISA_SET_PKU: + case XED_ISA_SET_POPCNT: + case XED_ISA_SET_PPRO: + case XED_ISA_SET_PPRO_UD0_LONG: + case XED_ISA_SET_PPRO_UD0_SHORT: + case XED_ISA_SET_PREFETCHW: + case XED_ISA_SET_PREFETCHWT1: + case XED_ISA_SET_PREFETCH_NOP: + case XED_ISA_SET_PTWRITE: + case XED_ISA_SET_RDPID: + case XED_ISA_SET_RDPMC: + case XED_ISA_SET_RDPRU: + case XED_ISA_SET_RDRAND: + case XED_ISA_SET_RDSEED: + case XED_ISA_SET_RDTSCP: + case XED_ISA_SET_RDWRFSGS: + case XED_ISA_SET_RTM: + case XED_ISA_SET_SERIALIZE: + case XED_ISA_SET_SGX: + case XED_ISA_SET_SGX_ENCLV: + case XED_ISA_SET_SHA: + case XED_ISA_SET_SMAP: + case XED_ISA_SET_SMX: + case XED_ISA_SET_SNP: + case XED_ISA_SET_SSE: + case XED_ISA_SET_SSE2: + case XED_ISA_SET_SSE2MMX: + case XED_ISA_SET_SSE3: + case XED_ISA_SET_SSE3X87: + case XED_ISA_SET_SSE4: + case XED_ISA_SET_SSE42: + case XED_ISA_SET_SSE4A: + case XED_ISA_SET_SSEMXCSR: + case XED_ISA_SET_SSE_PREFETCH: + case XED_ISA_SET_SSSE3: + case XED_ISA_SET_SSSE3MMX: + case XED_ISA_SET_SVM: + case XED_ISA_SET_TBM: + case XED_ISA_SET_TDX: + case XED_ISA_SET_TSX_LDTRK: + case XED_ISA_SET_UINTR: + case XED_ISA_SET_VAES: + case XED_ISA_SET_VIA_PADLOCK_AES: + case XED_ISA_SET_VIA_PADLOCK_MONTMUL: + case XED_ISA_SET_VIA_PADLOCK_RNG: + case XED_ISA_SET_VIA_PADLOCK_SHA: + case XED_ISA_SET_VMFUNC: + case XED_ISA_SET_VPCLMULQDQ: + case XED_ISA_SET_VTX: + case XED_ISA_SET_WAITPKG: + case XED_ISA_SET_WBNOINVD: + case XED_ISA_SET_X87: + case XED_ISA_SET_XOP: + case XED_ISA_SET_XSAVE: + case XED_ISA_SET_XSAVEC: + case XED_ISA_SET_XSAVEOPT: + case XED_ISA_SET_XSAVES: + case XED_ISA_SET_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-isa-set-enum.h b/CodeVirtualizer/build/obj/xed-isa-set-enum.h new file mode 100644 index 0000000..4aa7024 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-isa-set-enum.h @@ -0,0 +1,393 @@ +/// @file xed-isa-set-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_ISA_SET_ENUM_H) +# define XED_ISA_SET_ENUM_H +#include "xed-common-hdrs.h" +#define XED_ISA_SET_INVALID_DEFINED 1 +#define XED_ISA_SET_3DNOW_DEFINED 1 +#define XED_ISA_SET_3DNOW_PREFETCH_DEFINED 1 +#define XED_ISA_SET_ADOX_ADCX_DEFINED 1 +#define XED_ISA_SET_AES_DEFINED 1 +#define XED_ISA_SET_AMD_DEFINED 1 +#define XED_ISA_SET_AMD_INVLPGB_DEFINED 1 +#define XED_ISA_SET_AMX_BF16_DEFINED 1 +#define XED_ISA_SET_AMX_INT8_DEFINED 1 +#define XED_ISA_SET_AMX_TILE_DEFINED 1 +#define XED_ISA_SET_AVX_DEFINED 1 +#define XED_ISA_SET_AVX2_DEFINED 1 +#define XED_ISA_SET_AVX2GATHER_DEFINED 1 +#define XED_ISA_SET_AVX512BW_128_DEFINED 1 +#define XED_ISA_SET_AVX512BW_128N_DEFINED 1 +#define XED_ISA_SET_AVX512BW_256_DEFINED 1 +#define XED_ISA_SET_AVX512BW_512_DEFINED 1 +#define XED_ISA_SET_AVX512BW_KOP_DEFINED 1 +#define XED_ISA_SET_AVX512CD_128_DEFINED 1 +#define XED_ISA_SET_AVX512CD_256_DEFINED 1 +#define XED_ISA_SET_AVX512CD_512_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_128_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_128N_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_256_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_512_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_KOP_DEFINED 1 +#define XED_ISA_SET_AVX512DQ_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512ER_512_DEFINED 1 +#define XED_ISA_SET_AVX512ER_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512F_128_DEFINED 1 +#define XED_ISA_SET_AVX512F_128N_DEFINED 1 +#define XED_ISA_SET_AVX512F_256_DEFINED 1 +#define XED_ISA_SET_AVX512F_512_DEFINED 1 +#define XED_ISA_SET_AVX512F_KOP_DEFINED 1 +#define XED_ISA_SET_AVX512F_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512PF_512_DEFINED 1 +#define XED_ISA_SET_AVX512_4FMAPS_512_DEFINED 1 +#define XED_ISA_SET_AVX512_4FMAPS_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512_4VNNIW_512_DEFINED 1 +#define XED_ISA_SET_AVX512_BF16_128_DEFINED 1 +#define XED_ISA_SET_AVX512_BF16_256_DEFINED 1 +#define XED_ISA_SET_AVX512_BF16_512_DEFINED 1 +#define XED_ISA_SET_AVX512_BITALG_128_DEFINED 1 +#define XED_ISA_SET_AVX512_BITALG_256_DEFINED 1 +#define XED_ISA_SET_AVX512_BITALG_512_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_128_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_128N_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_256_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_512_DEFINED 1 +#define XED_ISA_SET_AVX512_FP16_SCALAR_DEFINED 1 +#define XED_ISA_SET_AVX512_GFNI_128_DEFINED 1 +#define XED_ISA_SET_AVX512_GFNI_256_DEFINED 1 +#define XED_ISA_SET_AVX512_GFNI_512_DEFINED 1 +#define XED_ISA_SET_AVX512_IFMA_128_DEFINED 1 +#define XED_ISA_SET_AVX512_IFMA_256_DEFINED 1 +#define XED_ISA_SET_AVX512_IFMA_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VAES_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VAES_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VAES_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI2_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI2_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI2_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VBMI_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VNNI_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VNNI_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VNNI_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VP2INTERSECT_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VP2INTERSECT_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VP2INTERSECT_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VPCLMULQDQ_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VPCLMULQDQ_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VPCLMULQDQ_512_DEFINED 1 +#define XED_ISA_SET_AVX512_VPOPCNTDQ_128_DEFINED 1 +#define XED_ISA_SET_AVX512_VPOPCNTDQ_256_DEFINED 1 +#define XED_ISA_SET_AVX512_VPOPCNTDQ_512_DEFINED 1 +#define XED_ISA_SET_AVXAES_DEFINED 1 +#define XED_ISA_SET_AVX_GFNI_DEFINED 1 +#define XED_ISA_SET_AVX_VNNI_DEFINED 1 +#define XED_ISA_SET_BMI1_DEFINED 1 +#define XED_ISA_SET_BMI2_DEFINED 1 +#define XED_ISA_SET_CET_DEFINED 1 +#define XED_ISA_SET_CLDEMOTE_DEFINED 1 +#define XED_ISA_SET_CLFLUSHOPT_DEFINED 1 +#define XED_ISA_SET_CLFSH_DEFINED 1 +#define XED_ISA_SET_CLWB_DEFINED 1 +#define XED_ISA_SET_CLZERO_DEFINED 1 +#define XED_ISA_SET_CMOV_DEFINED 1 +#define XED_ISA_SET_CMPXCHG16B_DEFINED 1 +#define XED_ISA_SET_ENQCMD_DEFINED 1 +#define XED_ISA_SET_F16C_DEFINED 1 +#define XED_ISA_SET_FAT_NOP_DEFINED 1 +#define XED_ISA_SET_FCMOV_DEFINED 1 +#define XED_ISA_SET_FMA_DEFINED 1 +#define XED_ISA_SET_FMA4_DEFINED 1 +#define XED_ISA_SET_FXSAVE_DEFINED 1 +#define XED_ISA_SET_FXSAVE64_DEFINED 1 +#define XED_ISA_SET_GFNI_DEFINED 1 +#define XED_ISA_SET_HRESET_DEFINED 1 +#define XED_ISA_SET_I186_DEFINED 1 +#define XED_ISA_SET_I286PROTECTED_DEFINED 1 +#define XED_ISA_SET_I286REAL_DEFINED 1 +#define XED_ISA_SET_I386_DEFINED 1 +#define XED_ISA_SET_I486_DEFINED 1 +#define XED_ISA_SET_I486REAL_DEFINED 1 +#define XED_ISA_SET_I86_DEFINED 1 +#define XED_ISA_SET_INVPCID_DEFINED 1 +#define XED_ISA_SET_KEYLOCKER_DEFINED 1 +#define XED_ISA_SET_KEYLOCKER_WIDE_DEFINED 1 +#define XED_ISA_SET_LAHF_DEFINED 1 +#define XED_ISA_SET_LONGMODE_DEFINED 1 +#define XED_ISA_SET_LWP_DEFINED 1 +#define XED_ISA_SET_LZCNT_DEFINED 1 +#define XED_ISA_SET_MCOMMIT_DEFINED 1 +#define XED_ISA_SET_MONITOR_DEFINED 1 +#define XED_ISA_SET_MONITORX_DEFINED 1 +#define XED_ISA_SET_MOVBE_DEFINED 1 +#define XED_ISA_SET_MOVDIR_DEFINED 1 +#define XED_ISA_SET_MPX_DEFINED 1 +#define XED_ISA_SET_PAUSE_DEFINED 1 +#define XED_ISA_SET_PCLMULQDQ_DEFINED 1 +#define XED_ISA_SET_PCONFIG_DEFINED 1 +#define XED_ISA_SET_PENTIUMMMX_DEFINED 1 +#define XED_ISA_SET_PENTIUMREAL_DEFINED 1 +#define XED_ISA_SET_PKU_DEFINED 1 +#define XED_ISA_SET_POPCNT_DEFINED 1 +#define XED_ISA_SET_PPRO_DEFINED 1 +#define XED_ISA_SET_PPRO_UD0_LONG_DEFINED 1 +#define XED_ISA_SET_PPRO_UD0_SHORT_DEFINED 1 +#define XED_ISA_SET_PREFETCHW_DEFINED 1 +#define XED_ISA_SET_PREFETCHWT1_DEFINED 1 +#define XED_ISA_SET_PREFETCH_NOP_DEFINED 1 +#define XED_ISA_SET_PTWRITE_DEFINED 1 +#define XED_ISA_SET_RDPID_DEFINED 1 +#define XED_ISA_SET_RDPMC_DEFINED 1 +#define XED_ISA_SET_RDPRU_DEFINED 1 +#define XED_ISA_SET_RDRAND_DEFINED 1 +#define XED_ISA_SET_RDSEED_DEFINED 1 +#define XED_ISA_SET_RDTSCP_DEFINED 1 +#define XED_ISA_SET_RDWRFSGS_DEFINED 1 +#define XED_ISA_SET_RTM_DEFINED 1 +#define XED_ISA_SET_SERIALIZE_DEFINED 1 +#define XED_ISA_SET_SGX_DEFINED 1 +#define XED_ISA_SET_SGX_ENCLV_DEFINED 1 +#define XED_ISA_SET_SHA_DEFINED 1 +#define XED_ISA_SET_SMAP_DEFINED 1 +#define XED_ISA_SET_SMX_DEFINED 1 +#define XED_ISA_SET_SNP_DEFINED 1 +#define XED_ISA_SET_SSE_DEFINED 1 +#define XED_ISA_SET_SSE2_DEFINED 1 +#define XED_ISA_SET_SSE2MMX_DEFINED 1 +#define XED_ISA_SET_SSE3_DEFINED 1 +#define XED_ISA_SET_SSE3X87_DEFINED 1 +#define XED_ISA_SET_SSE4_DEFINED 1 +#define XED_ISA_SET_SSE42_DEFINED 1 +#define XED_ISA_SET_SSE4A_DEFINED 1 +#define XED_ISA_SET_SSEMXCSR_DEFINED 1 +#define XED_ISA_SET_SSE_PREFETCH_DEFINED 1 +#define XED_ISA_SET_SSSE3_DEFINED 1 +#define XED_ISA_SET_SSSE3MMX_DEFINED 1 +#define XED_ISA_SET_SVM_DEFINED 1 +#define XED_ISA_SET_TBM_DEFINED 1 +#define XED_ISA_SET_TDX_DEFINED 1 +#define XED_ISA_SET_TSX_LDTRK_DEFINED 1 +#define XED_ISA_SET_UINTR_DEFINED 1 +#define XED_ISA_SET_VAES_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_AES_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_MONTMUL_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_RNG_DEFINED 1 +#define XED_ISA_SET_VIA_PADLOCK_SHA_DEFINED 1 +#define XED_ISA_SET_VMFUNC_DEFINED 1 +#define XED_ISA_SET_VPCLMULQDQ_DEFINED 1 +#define XED_ISA_SET_VTX_DEFINED 1 +#define XED_ISA_SET_WAITPKG_DEFINED 1 +#define XED_ISA_SET_WBNOINVD_DEFINED 1 +#define XED_ISA_SET_X87_DEFINED 1 +#define XED_ISA_SET_XOP_DEFINED 1 +#define XED_ISA_SET_XSAVE_DEFINED 1 +#define XED_ISA_SET_XSAVEC_DEFINED 1 +#define XED_ISA_SET_XSAVEOPT_DEFINED 1 +#define XED_ISA_SET_XSAVES_DEFINED 1 +#define XED_ISA_SET_LAST_DEFINED 1 +typedef enum { + XED_ISA_SET_INVALID, + XED_ISA_SET_3DNOW, + XED_ISA_SET_3DNOW_PREFETCH, + XED_ISA_SET_ADOX_ADCX, + XED_ISA_SET_AES, + XED_ISA_SET_AMD, + XED_ISA_SET_AMD_INVLPGB, + XED_ISA_SET_AMX_BF16, + XED_ISA_SET_AMX_INT8, + XED_ISA_SET_AMX_TILE, + XED_ISA_SET_AVX, + XED_ISA_SET_AVX2, + XED_ISA_SET_AVX2GATHER, + XED_ISA_SET_AVX512BW_128, + XED_ISA_SET_AVX512BW_128N, + XED_ISA_SET_AVX512BW_256, + XED_ISA_SET_AVX512BW_512, + XED_ISA_SET_AVX512BW_KOP, + XED_ISA_SET_AVX512CD_128, + XED_ISA_SET_AVX512CD_256, + XED_ISA_SET_AVX512CD_512, + XED_ISA_SET_AVX512DQ_128, + XED_ISA_SET_AVX512DQ_128N, + XED_ISA_SET_AVX512DQ_256, + XED_ISA_SET_AVX512DQ_512, + XED_ISA_SET_AVX512DQ_KOP, + XED_ISA_SET_AVX512DQ_SCALAR, + XED_ISA_SET_AVX512ER_512, + XED_ISA_SET_AVX512ER_SCALAR, + XED_ISA_SET_AVX512F_128, + XED_ISA_SET_AVX512F_128N, + XED_ISA_SET_AVX512F_256, + XED_ISA_SET_AVX512F_512, + XED_ISA_SET_AVX512F_KOP, + XED_ISA_SET_AVX512F_SCALAR, + XED_ISA_SET_AVX512PF_512, + XED_ISA_SET_AVX512_4FMAPS_512, + XED_ISA_SET_AVX512_4FMAPS_SCALAR, + XED_ISA_SET_AVX512_4VNNIW_512, + XED_ISA_SET_AVX512_BF16_128, + XED_ISA_SET_AVX512_BF16_256, + XED_ISA_SET_AVX512_BF16_512, + XED_ISA_SET_AVX512_BITALG_128, + XED_ISA_SET_AVX512_BITALG_256, + XED_ISA_SET_AVX512_BITALG_512, + XED_ISA_SET_AVX512_FP16_128, + XED_ISA_SET_AVX512_FP16_128N, + XED_ISA_SET_AVX512_FP16_256, + XED_ISA_SET_AVX512_FP16_512, + XED_ISA_SET_AVX512_FP16_SCALAR, + XED_ISA_SET_AVX512_GFNI_128, + XED_ISA_SET_AVX512_GFNI_256, + XED_ISA_SET_AVX512_GFNI_512, + XED_ISA_SET_AVX512_IFMA_128, + XED_ISA_SET_AVX512_IFMA_256, + XED_ISA_SET_AVX512_IFMA_512, + XED_ISA_SET_AVX512_VAES_128, + XED_ISA_SET_AVX512_VAES_256, + XED_ISA_SET_AVX512_VAES_512, + XED_ISA_SET_AVX512_VBMI2_128, + XED_ISA_SET_AVX512_VBMI2_256, + XED_ISA_SET_AVX512_VBMI2_512, + XED_ISA_SET_AVX512_VBMI_128, + XED_ISA_SET_AVX512_VBMI_256, + XED_ISA_SET_AVX512_VBMI_512, + XED_ISA_SET_AVX512_VNNI_128, + XED_ISA_SET_AVX512_VNNI_256, + XED_ISA_SET_AVX512_VNNI_512, + XED_ISA_SET_AVX512_VP2INTERSECT_128, + XED_ISA_SET_AVX512_VP2INTERSECT_256, + XED_ISA_SET_AVX512_VP2INTERSECT_512, + XED_ISA_SET_AVX512_VPCLMULQDQ_128, + XED_ISA_SET_AVX512_VPCLMULQDQ_256, + XED_ISA_SET_AVX512_VPCLMULQDQ_512, + XED_ISA_SET_AVX512_VPOPCNTDQ_128, + XED_ISA_SET_AVX512_VPOPCNTDQ_256, + XED_ISA_SET_AVX512_VPOPCNTDQ_512, + XED_ISA_SET_AVXAES, + XED_ISA_SET_AVX_GFNI, + XED_ISA_SET_AVX_VNNI, + XED_ISA_SET_BMI1, + XED_ISA_SET_BMI2, + XED_ISA_SET_CET, + XED_ISA_SET_CLDEMOTE, + XED_ISA_SET_CLFLUSHOPT, + XED_ISA_SET_CLFSH, + XED_ISA_SET_CLWB, + XED_ISA_SET_CLZERO, + XED_ISA_SET_CMOV, + XED_ISA_SET_CMPXCHG16B, + XED_ISA_SET_ENQCMD, + XED_ISA_SET_F16C, + XED_ISA_SET_FAT_NOP, + XED_ISA_SET_FCMOV, + XED_ISA_SET_FMA, + XED_ISA_SET_FMA4, + XED_ISA_SET_FXSAVE, + XED_ISA_SET_FXSAVE64, + XED_ISA_SET_GFNI, + XED_ISA_SET_HRESET, + XED_ISA_SET_I186, + XED_ISA_SET_I286PROTECTED, + XED_ISA_SET_I286REAL, + XED_ISA_SET_I386, + XED_ISA_SET_I486, + XED_ISA_SET_I486REAL, + XED_ISA_SET_I86, + XED_ISA_SET_INVPCID, + XED_ISA_SET_KEYLOCKER, + XED_ISA_SET_KEYLOCKER_WIDE, + XED_ISA_SET_LAHF, + XED_ISA_SET_LONGMODE, + XED_ISA_SET_LWP, + XED_ISA_SET_LZCNT, + XED_ISA_SET_MCOMMIT, + XED_ISA_SET_MONITOR, + XED_ISA_SET_MONITORX, + XED_ISA_SET_MOVBE, + XED_ISA_SET_MOVDIR, + XED_ISA_SET_MPX, + XED_ISA_SET_PAUSE, + XED_ISA_SET_PCLMULQDQ, + XED_ISA_SET_PCONFIG, + XED_ISA_SET_PENTIUMMMX, + XED_ISA_SET_PENTIUMREAL, + XED_ISA_SET_PKU, + XED_ISA_SET_POPCNT, + XED_ISA_SET_PPRO, + XED_ISA_SET_PPRO_UD0_LONG, + XED_ISA_SET_PPRO_UD0_SHORT, + XED_ISA_SET_PREFETCHW, + XED_ISA_SET_PREFETCHWT1, + XED_ISA_SET_PREFETCH_NOP, + XED_ISA_SET_PTWRITE, + XED_ISA_SET_RDPID, + XED_ISA_SET_RDPMC, + XED_ISA_SET_RDPRU, + XED_ISA_SET_RDRAND, + XED_ISA_SET_RDSEED, + XED_ISA_SET_RDTSCP, + XED_ISA_SET_RDWRFSGS, + XED_ISA_SET_RTM, + XED_ISA_SET_SERIALIZE, + XED_ISA_SET_SGX, + XED_ISA_SET_SGX_ENCLV, + XED_ISA_SET_SHA, + XED_ISA_SET_SMAP, + XED_ISA_SET_SMX, + XED_ISA_SET_SNP, + XED_ISA_SET_SSE, + XED_ISA_SET_SSE2, + XED_ISA_SET_SSE2MMX, + XED_ISA_SET_SSE3, + XED_ISA_SET_SSE3X87, + XED_ISA_SET_SSE4, + XED_ISA_SET_SSE42, + XED_ISA_SET_SSE4A, + XED_ISA_SET_SSEMXCSR, + XED_ISA_SET_SSE_PREFETCH, + XED_ISA_SET_SSSE3, + XED_ISA_SET_SSSE3MMX, + XED_ISA_SET_SVM, + XED_ISA_SET_TBM, + XED_ISA_SET_TDX, + XED_ISA_SET_TSX_LDTRK, + XED_ISA_SET_UINTR, + XED_ISA_SET_VAES, + XED_ISA_SET_VIA_PADLOCK_AES, + XED_ISA_SET_VIA_PADLOCK_MONTMUL, + XED_ISA_SET_VIA_PADLOCK_RNG, + XED_ISA_SET_VIA_PADLOCK_SHA, + XED_ISA_SET_VMFUNC, + XED_ISA_SET_VPCLMULQDQ, + XED_ISA_SET_VTX, + XED_ISA_SET_WAITPKG, + XED_ISA_SET_WBNOINVD, + XED_ISA_SET_X87, + XED_ISA_SET_XOP, + XED_ISA_SET_XSAVE, + XED_ISA_SET_XSAVEC, + XED_ISA_SET_XSAVEOPT, + XED_ISA_SET_XSAVES, + XED_ISA_SET_LAST +} xed_isa_set_enum_t; + +/// This converts strings to #xed_isa_set_enum_t types. +/// @param s A C-string. +/// @return #xed_isa_set_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_isa_set_enum_t str2xed_isa_set_enum_t(const char* s); +/// This converts strings to #xed_isa_set_enum_t types. +/// @param p An enumeration element of type xed_isa_set_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_isa_set_enum_t2str(const xed_isa_set_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_isa_set_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_isa_set_enum_t xed_isa_set_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-isa-set-enum.txt b/CodeVirtualizer/build/obj/xed-isa-set-enum.txt new file mode 100644 index 0000000..fc0b899 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-isa-set-enum.txt @@ -0,0 +1,212 @@ +# @file xed-isa-set-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-isa-set-enum.c +hfn xed-isa-set-enum.h +typename xed_isa_set_enum_t +prefix XED_ISA_SET_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +3DNOW +3DNOW_PREFETCH +ADOX_ADCX +AES +AMD +AMD_INVLPGB +AMX_BF16 +AMX_INT8 +AMX_TILE +AVX +AVX2 +AVX2GATHER +AVX512BW_128 +AVX512BW_128N +AVX512BW_256 +AVX512BW_512 +AVX512BW_KOP +AVX512CD_128 +AVX512CD_256 +AVX512CD_512 +AVX512DQ_128 +AVX512DQ_128N +AVX512DQ_256 +AVX512DQ_512 +AVX512DQ_KOP +AVX512DQ_SCALAR +AVX512ER_512 +AVX512ER_SCALAR +AVX512F_128 +AVX512F_128N +AVX512F_256 +AVX512F_512 +AVX512F_KOP +AVX512F_SCALAR +AVX512PF_512 +AVX512_4FMAPS_512 +AVX512_4FMAPS_SCALAR +AVX512_4VNNIW_512 +AVX512_BF16_128 +AVX512_BF16_256 +AVX512_BF16_512 +AVX512_BITALG_128 +AVX512_BITALG_256 +AVX512_BITALG_512 +AVX512_FP16_128 +AVX512_FP16_128N +AVX512_FP16_256 +AVX512_FP16_512 +AVX512_FP16_SCALAR +AVX512_GFNI_128 +AVX512_GFNI_256 +AVX512_GFNI_512 +AVX512_IFMA_128 +AVX512_IFMA_256 +AVX512_IFMA_512 +AVX512_VAES_128 +AVX512_VAES_256 +AVX512_VAES_512 +AVX512_VBMI2_128 +AVX512_VBMI2_256 +AVX512_VBMI2_512 +AVX512_VBMI_128 +AVX512_VBMI_256 +AVX512_VBMI_512 +AVX512_VNNI_128 +AVX512_VNNI_256 +AVX512_VNNI_512 +AVX512_VP2INTERSECT_128 +AVX512_VP2INTERSECT_256 +AVX512_VP2INTERSECT_512 +AVX512_VPCLMULQDQ_128 +AVX512_VPCLMULQDQ_256 +AVX512_VPCLMULQDQ_512 +AVX512_VPOPCNTDQ_128 +AVX512_VPOPCNTDQ_256 +AVX512_VPOPCNTDQ_512 +AVXAES +AVX_GFNI +AVX_VNNI +BMI1 +BMI2 +CET +CLDEMOTE +CLFLUSHOPT +CLFSH +CLWB +CLZERO +CMOV +CMPXCHG16B +ENQCMD +F16C +FAT_NOP +FCMOV +FMA +FMA4 +FXSAVE +FXSAVE64 +GFNI +HRESET +I186 +I286PROTECTED +I286REAL +I386 +I486 +I486REAL +I86 +INVPCID +KEYLOCKER +KEYLOCKER_WIDE +LAHF +LONGMODE +LWP +LZCNT +MCOMMIT +MONITOR +MONITORX +MOVBE +MOVDIR +MPX +PAUSE +PCLMULQDQ +PCONFIG +PENTIUMMMX +PENTIUMREAL +PKU +POPCNT +PPRO +PPRO_UD0_LONG +PPRO_UD0_SHORT +PREFETCHW +PREFETCHWT1 +PREFETCH_NOP +PTWRITE +RDPID +RDPMC +RDPRU +RDRAND +RDSEED +RDTSCP +RDWRFSGS +RTM +SERIALIZE +SGX +SGX_ENCLV +SHA +SMAP +SMX +SNP +SSE +SSE2 +SSE2MMX +SSE3 +SSE3X87 +SSE4 +SSE42 +SSE4A +SSEMXCSR +SSE_PREFETCH +SSSE3 +SSSE3MMX +SVM +TBM +TDX +TSX_LDTRK +UINTR +VAES +VIA_PADLOCK_AES +VIA_PADLOCK_MONTMUL +VIA_PADLOCK_RNG +VIA_PADLOCK_SHA +VMFUNC +VPCLMULQDQ +VTX +WAITPKG +WBNOINVD +X87 +XOP +XSAVE +XSAVEC +XSAVEOPT +XSAVES diff --git a/CodeVirtualizer/build/obj/xed-machine-mode-enum.c b/CodeVirtualizer/build/obj/xed-machine-mode-enum.c new file mode 100644 index 0000000..327352d --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-machine-mode-enum.c @@ -0,0 +1,72 @@ +/// @file xed-machine-mode-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-machine-mode-enum.h" + +typedef struct { + const char* name; + xed_machine_mode_enum_t value; +} name_table_xed_machine_mode_enum_t; +static const name_table_xed_machine_mode_enum_t name_array_xed_machine_mode_enum_t[] = { +{"INVALID", XED_MACHINE_MODE_INVALID}, +{"LONG_64", XED_MACHINE_MODE_LONG_64}, +{"LONG_COMPAT_32", XED_MACHINE_MODE_LONG_COMPAT_32}, +{"LONG_COMPAT_16", XED_MACHINE_MODE_LONG_COMPAT_16}, +{"LEGACY_32", XED_MACHINE_MODE_LEGACY_32}, +{"LEGACY_16", XED_MACHINE_MODE_LEGACY_16}, +{"REAL_16", XED_MACHINE_MODE_REAL_16}, +{"REAL_32", XED_MACHINE_MODE_REAL_32}, +{"LAST", XED_MACHINE_MODE_LAST}, +{0, XED_MACHINE_MODE_LAST}, +}; + + +xed_machine_mode_enum_t str2xed_machine_mode_enum_t(const char* s) +{ + const name_table_xed_machine_mode_enum_t* p = name_array_xed_machine_mode_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_MACHINE_MODE_INVALID; +} + + +const char* xed_machine_mode_enum_t2str(const xed_machine_mode_enum_t p) +{ + xed_machine_mode_enum_t type_idx = p; + if ( p > XED_MACHINE_MODE_LAST) type_idx = XED_MACHINE_MODE_LAST; + return name_array_xed_machine_mode_enum_t[type_idx].name; +} + +xed_machine_mode_enum_t xed_machine_mode_enum_t_last(void) { + return XED_MACHINE_MODE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_MACHINE_MODE_INVALID: + case XED_MACHINE_MODE_LONG_64: + case XED_MACHINE_MODE_LONG_COMPAT_32: + case XED_MACHINE_MODE_LONG_COMPAT_16: + case XED_MACHINE_MODE_LEGACY_32: + case XED_MACHINE_MODE_LEGACY_16: + case XED_MACHINE_MODE_REAL_16: + case XED_MACHINE_MODE_REAL_32: + case XED_MACHINE_MODE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-machine-mode-enum.h b/CodeVirtualizer/build/obj/xed-machine-mode-enum.h new file mode 100644 index 0000000..326ff0f --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-machine-mode-enum.h @@ -0,0 +1,45 @@ +/// @file xed-machine-mode-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_MACHINE_MODE_ENUM_H) +# define XED_MACHINE_MODE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_MACHINE_MODE_INVALID_DEFINED 1 +#define XED_MACHINE_MODE_LONG_64_DEFINED 1 +#define XED_MACHINE_MODE_LONG_COMPAT_32_DEFINED 1 +#define XED_MACHINE_MODE_LONG_COMPAT_16_DEFINED 1 +#define XED_MACHINE_MODE_LEGACY_32_DEFINED 1 +#define XED_MACHINE_MODE_LEGACY_16_DEFINED 1 +#define XED_MACHINE_MODE_REAL_16_DEFINED 1 +#define XED_MACHINE_MODE_REAL_32_DEFINED 1 +#define XED_MACHINE_MODE_LAST_DEFINED 1 +typedef enum { + XED_MACHINE_MODE_INVALID, + XED_MACHINE_MODE_LONG_64, ///< 64b operating mode + XED_MACHINE_MODE_LONG_COMPAT_32, ///< 32b protected mode + XED_MACHINE_MODE_LONG_COMPAT_16, ///< 16b protected mode + XED_MACHINE_MODE_LEGACY_32, ///< 32b protected mode + XED_MACHINE_MODE_LEGACY_16, ///< 16b protected mode + XED_MACHINE_MODE_REAL_16, ///< 16b real mode + XED_MACHINE_MODE_REAL_32, ///< 32b real mode (CS.D bit = 1) + XED_MACHINE_MODE_LAST +} xed_machine_mode_enum_t; + +/// This converts strings to #xed_machine_mode_enum_t types. +/// @param s A C-string. +/// @return #xed_machine_mode_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_machine_mode_enum_t str2xed_machine_mode_enum_t(const char* s); +/// This converts strings to #xed_machine_mode_enum_t types. +/// @param p An enumeration element of type xed_machine_mode_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_machine_mode_enum_t2str(const xed_machine_mode_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_machine_mode_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_machine_mode_enum_t xed_machine_mode_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-mapu-enum.c b/CodeVirtualizer/build/obj/xed-mapu-enum.c new file mode 100644 index 0000000..c8b7f67 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-mapu-enum.c @@ -0,0 +1,90 @@ +/// @file xed-mapu-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-mapu-enum.h" + +typedef struct { + const char* name; + xed_mapu_enum_t value; +} name_table_xed_mapu_enum_t; +static const name_table_xed_mapu_enum_t name_array_xed_mapu_enum_t[] = { +{"INVALID", XED_MAPU_INVALID}, +{"AMD_3DNOW", XED_MAPU_AMD_3DNOW}, +{"AMD_XOP8", XED_MAPU_AMD_XOP8}, +{"AMD_XOP9", XED_MAPU_AMD_XOP9}, +{"AMD_XOPA", XED_MAPU_AMD_XOPA}, +{"EVEX_MAP1", XED_MAPU_EVEX_MAP1}, +{"EVEX_MAP2", XED_MAPU_EVEX_MAP2}, +{"EVEX_MAP3", XED_MAPU_EVEX_MAP3}, +{"EVEX_MAP5", XED_MAPU_EVEX_MAP5}, +{"EVEX_MAP6", XED_MAPU_EVEX_MAP6}, +{"LEGACY_MAP0", XED_MAPU_LEGACY_MAP0}, +{"LEGACY_MAP1", XED_MAPU_LEGACY_MAP1}, +{"LEGACY_MAP2", XED_MAPU_LEGACY_MAP2}, +{"LEGACY_MAP3", XED_MAPU_LEGACY_MAP3}, +{"VEX_MAP1", XED_MAPU_VEX_MAP1}, +{"VEX_MAP2", XED_MAPU_VEX_MAP2}, +{"VEX_MAP3", XED_MAPU_VEX_MAP3}, +{"LAST", XED_MAPU_LAST}, +{0, XED_MAPU_LAST}, +}; + + +xed_mapu_enum_t str2xed_mapu_enum_t(const char* s) +{ + const name_table_xed_mapu_enum_t* p = name_array_xed_mapu_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_MAPU_INVALID; +} + + +const char* xed_mapu_enum_t2str(const xed_mapu_enum_t p) +{ + xed_mapu_enum_t type_idx = p; + if ( p > XED_MAPU_LAST) type_idx = XED_MAPU_LAST; + return name_array_xed_mapu_enum_t[type_idx].name; +} + +xed_mapu_enum_t xed_mapu_enum_t_last(void) { + return XED_MAPU_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_MAPU_INVALID: + case XED_MAPU_AMD_3DNOW: + case XED_MAPU_AMD_XOP8: + case XED_MAPU_AMD_XOP9: + case XED_MAPU_AMD_XOPA: + case XED_MAPU_EVEX_MAP1: + case XED_MAPU_EVEX_MAP2: + case XED_MAPU_EVEX_MAP3: + case XED_MAPU_EVEX_MAP5: + case XED_MAPU_EVEX_MAP6: + case XED_MAPU_LEGACY_MAP0: + case XED_MAPU_LEGACY_MAP1: + case XED_MAPU_LEGACY_MAP2: + case XED_MAPU_LEGACY_MAP3: + case XED_MAPU_VEX_MAP1: + case XED_MAPU_VEX_MAP2: + case XED_MAPU_VEX_MAP3: + case XED_MAPU_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-mapu-enum.h b/CodeVirtualizer/build/obj/xed-mapu-enum.h new file mode 100644 index 0000000..622850b --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-mapu-enum.h @@ -0,0 +1,63 @@ +/// @file xed-mapu-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_MAPU_ENUM_H) +# define XED_MAPU_ENUM_H +#include "xed-common-hdrs.h" +#define XED_MAPU_INVALID_DEFINED 1 +#define XED_MAPU_AMD_3DNOW_DEFINED 1 +#define XED_MAPU_AMD_XOP8_DEFINED 1 +#define XED_MAPU_AMD_XOP9_DEFINED 1 +#define XED_MAPU_AMD_XOPA_DEFINED 1 +#define XED_MAPU_EVEX_MAP1_DEFINED 1 +#define XED_MAPU_EVEX_MAP2_DEFINED 1 +#define XED_MAPU_EVEX_MAP3_DEFINED 1 +#define XED_MAPU_EVEX_MAP5_DEFINED 1 +#define XED_MAPU_EVEX_MAP6_DEFINED 1 +#define XED_MAPU_LEGACY_MAP0_DEFINED 1 +#define XED_MAPU_LEGACY_MAP1_DEFINED 1 +#define XED_MAPU_LEGACY_MAP2_DEFINED 1 +#define XED_MAPU_LEGACY_MAP3_DEFINED 1 +#define XED_MAPU_VEX_MAP1_DEFINED 1 +#define XED_MAPU_VEX_MAP2_DEFINED 1 +#define XED_MAPU_VEX_MAP3_DEFINED 1 +#define XED_MAPU_LAST_DEFINED 1 +typedef enum { + XED_MAPU_INVALID, + XED_MAPU_AMD_3DNOW, + XED_MAPU_AMD_XOP8, + XED_MAPU_AMD_XOP9, + XED_MAPU_AMD_XOPA, + XED_MAPU_EVEX_MAP1, + XED_MAPU_EVEX_MAP2, + XED_MAPU_EVEX_MAP3, + XED_MAPU_EVEX_MAP5, + XED_MAPU_EVEX_MAP6, + XED_MAPU_LEGACY_MAP0, + XED_MAPU_LEGACY_MAP1, + XED_MAPU_LEGACY_MAP2, + XED_MAPU_LEGACY_MAP3, + XED_MAPU_VEX_MAP1, + XED_MAPU_VEX_MAP2, + XED_MAPU_VEX_MAP3, + XED_MAPU_LAST +} xed_mapu_enum_t; + +/// This converts strings to #xed_mapu_enum_t types. +/// @param s A C-string. +/// @return #xed_mapu_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_mapu_enum_t str2xed_mapu_enum_t(const char* s); +/// This converts strings to #xed_mapu_enum_t types. +/// @param p An enumeration element of type xed_mapu_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_mapu_enum_t2str(const xed_mapu_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_mapu_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_mapu_enum_t xed_mapu_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-nonterminal-enum.c b/CodeVirtualizer/build/obj/xed-nonterminal-enum.c new file mode 100644 index 0000000..6e8e1cc --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-nonterminal-enum.c @@ -0,0 +1,572 @@ +/// @file xed-nonterminal-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-nonterminal-enum.h" + +typedef struct { + const char* name; + xed_nonterminal_enum_t value; +} name_table_xed_nonterminal_enum_t; +static const name_table_xed_nonterminal_enum_t name_array_xed_nonterminal_enum_t[] = { +{"INVALID", XED_NONTERMINAL_INVALID}, +{"AR10", XED_NONTERMINAL_AR10}, +{"AR11", XED_NONTERMINAL_AR11}, +{"AR12", XED_NONTERMINAL_AR12}, +{"AR13", XED_NONTERMINAL_AR13}, +{"AR14", XED_NONTERMINAL_AR14}, +{"AR15", XED_NONTERMINAL_AR15}, +{"AR8", XED_NONTERMINAL_AR8}, +{"AR9", XED_NONTERMINAL_AR9}, +{"ARAX", XED_NONTERMINAL_ARAX}, +{"ARBP", XED_NONTERMINAL_ARBP}, +{"ARBX", XED_NONTERMINAL_ARBX}, +{"ARCX", XED_NONTERMINAL_ARCX}, +{"ARDI", XED_NONTERMINAL_ARDI}, +{"ARDX", XED_NONTERMINAL_ARDX}, +{"ARSI", XED_NONTERMINAL_ARSI}, +{"ARSP", XED_NONTERMINAL_ARSP}, +{"ASZ_NONTERM", XED_NONTERMINAL_ASZ_NONTERM}, +{"AVX512_ROUND", XED_NONTERMINAL_AVX512_ROUND}, +{"AVX_INSTRUCTIONS", XED_NONTERMINAL_AVX_INSTRUCTIONS}, +{"AVX_SPLITTER", XED_NONTERMINAL_AVX_SPLITTER}, +{"A_GPR_B", XED_NONTERMINAL_A_GPR_B}, +{"A_GPR_R", XED_NONTERMINAL_A_GPR_R}, +{"BND_B", XED_NONTERMINAL_BND_B}, +{"BND_B_CHECK", XED_NONTERMINAL_BND_B_CHECK}, +{"BND_R", XED_NONTERMINAL_BND_R}, +{"BND_R_CHECK", XED_NONTERMINAL_BND_R_CHECK}, +{"BRANCH_HINT", XED_NONTERMINAL_BRANCH_HINT}, +{"BRDISP32", XED_NONTERMINAL_BRDISP32}, +{"BRDISP8", XED_NONTERMINAL_BRDISP8}, +{"BRDISPZ", XED_NONTERMINAL_BRDISPZ}, +{"CET_NO_TRACK", XED_NONTERMINAL_CET_NO_TRACK}, +{"CR_B", XED_NONTERMINAL_CR_B}, +{"CR_R", XED_NONTERMINAL_CR_R}, +{"CR_WIDTH", XED_NONTERMINAL_CR_WIDTH}, +{"DF64", XED_NONTERMINAL_DF64}, +{"DR_R", XED_NONTERMINAL_DR_R}, +{"ESIZE_128_BITS", XED_NONTERMINAL_ESIZE_128_BITS}, +{"ESIZE_16_BITS", XED_NONTERMINAL_ESIZE_16_BITS}, +{"ESIZE_1_BITS", XED_NONTERMINAL_ESIZE_1_BITS}, +{"ESIZE_2_BITS", XED_NONTERMINAL_ESIZE_2_BITS}, +{"ESIZE_32_BITS", XED_NONTERMINAL_ESIZE_32_BITS}, +{"ESIZE_4_BITS", XED_NONTERMINAL_ESIZE_4_BITS}, +{"ESIZE_64_BITS", XED_NONTERMINAL_ESIZE_64_BITS}, +{"ESIZE_8_BITS", XED_NONTERMINAL_ESIZE_8_BITS}, +{"EVEX_INSTRUCTIONS", XED_NONTERMINAL_EVEX_INSTRUCTIONS}, +{"EVEX_SPLITTER", XED_NONTERMINAL_EVEX_SPLITTER}, +{"FINAL_DSEG", XED_NONTERMINAL_FINAL_DSEG}, +{"FINAL_DSEG1", XED_NONTERMINAL_FINAL_DSEG1}, +{"FINAL_DSEG1_MODE64", XED_NONTERMINAL_FINAL_DSEG1_MODE64}, +{"FINAL_DSEG1_NOT64", XED_NONTERMINAL_FINAL_DSEG1_NOT64}, +{"FINAL_DSEG_MODE64", XED_NONTERMINAL_FINAL_DSEG_MODE64}, +{"FINAL_DSEG_NOT64", XED_NONTERMINAL_FINAL_DSEG_NOT64}, +{"FINAL_ESEG", XED_NONTERMINAL_FINAL_ESEG}, +{"FINAL_ESEG1", XED_NONTERMINAL_FINAL_ESEG1}, +{"FINAL_SSEG", XED_NONTERMINAL_FINAL_SSEG}, +{"FINAL_SSEG0", XED_NONTERMINAL_FINAL_SSEG0}, +{"FINAL_SSEG1", XED_NONTERMINAL_FINAL_SSEG1}, +{"FINAL_SSEG_MODE64", XED_NONTERMINAL_FINAL_SSEG_MODE64}, +{"FINAL_SSEG_NOT64", XED_NONTERMINAL_FINAL_SSEG_NOT64}, +{"FIX_ROUND_LEN128", XED_NONTERMINAL_FIX_ROUND_LEN128}, +{"FIX_ROUND_LEN512", XED_NONTERMINAL_FIX_ROUND_LEN512}, +{"FORCE64", XED_NONTERMINAL_FORCE64}, +{"GPR16_B", XED_NONTERMINAL_GPR16_B}, +{"GPR16_R", XED_NONTERMINAL_GPR16_R}, +{"GPR16_SB", XED_NONTERMINAL_GPR16_SB}, +{"GPR32_B", XED_NONTERMINAL_GPR32_B}, +{"GPR32_R", XED_NONTERMINAL_GPR32_R}, +{"GPR32_SB", XED_NONTERMINAL_GPR32_SB}, +{"GPR32_X", XED_NONTERMINAL_GPR32_X}, +{"GPR64_B", XED_NONTERMINAL_GPR64_B}, +{"GPR64_R", XED_NONTERMINAL_GPR64_R}, +{"GPR64_SB", XED_NONTERMINAL_GPR64_SB}, +{"GPR64_X", XED_NONTERMINAL_GPR64_X}, +{"GPR8_B", XED_NONTERMINAL_GPR8_B}, +{"GPR8_R", XED_NONTERMINAL_GPR8_R}, +{"GPR8_SB", XED_NONTERMINAL_GPR8_SB}, +{"GPRV_B", XED_NONTERMINAL_GPRV_B}, +{"GPRV_R", XED_NONTERMINAL_GPRV_R}, +{"GPRV_SB", XED_NONTERMINAL_GPRV_SB}, +{"GPRY_B", XED_NONTERMINAL_GPRY_B}, +{"GPRY_R", XED_NONTERMINAL_GPRY_R}, +{"GPRZ_B", XED_NONTERMINAL_GPRZ_B}, +{"GPRZ_R", XED_NONTERMINAL_GPRZ_R}, +{"IGNORE66", XED_NONTERMINAL_IGNORE66}, +{"IMMUNE66", XED_NONTERMINAL_IMMUNE66}, +{"IMMUNE66_LOOP64", XED_NONTERMINAL_IMMUNE66_LOOP64}, +{"IMMUNE_REXW", XED_NONTERMINAL_IMMUNE_REXW}, +{"INSTRUCTIONS", XED_NONTERMINAL_INSTRUCTIONS}, +{"ISA", XED_NONTERMINAL_ISA}, +{"MASK1", XED_NONTERMINAL_MASK1}, +{"MASKNOT0", XED_NONTERMINAL_MASKNOT0}, +{"MASK_B", XED_NONTERMINAL_MASK_B}, +{"MASK_N", XED_NONTERMINAL_MASK_N}, +{"MASK_N32", XED_NONTERMINAL_MASK_N32}, +{"MASK_N64", XED_NONTERMINAL_MASK_N64}, +{"MASK_R", XED_NONTERMINAL_MASK_R}, +{"MEMDISP", XED_NONTERMINAL_MEMDISP}, +{"MEMDISP16", XED_NONTERMINAL_MEMDISP16}, +{"MEMDISP32", XED_NONTERMINAL_MEMDISP32}, +{"MEMDISP8", XED_NONTERMINAL_MEMDISP8}, +{"MEMDISPV", XED_NONTERMINAL_MEMDISPV}, +{"MMX_B", XED_NONTERMINAL_MMX_B}, +{"MMX_R", XED_NONTERMINAL_MMX_R}, +{"MODRM", XED_NONTERMINAL_MODRM}, +{"MODRM16", XED_NONTERMINAL_MODRM16}, +{"MODRM32", XED_NONTERMINAL_MODRM32}, +{"MODRM64ALT32", XED_NONTERMINAL_MODRM64ALT32}, +{"NELEM_EIGHTHMEM", XED_NONTERMINAL_NELEM_EIGHTHMEM}, +{"NELEM_FULL", XED_NONTERMINAL_NELEM_FULL}, +{"NELEM_FULLMEM", XED_NONTERMINAL_NELEM_FULLMEM}, +{"NELEM_GPR_READER", XED_NONTERMINAL_NELEM_GPR_READER}, +{"NELEM_GPR_READER_BYTE", XED_NONTERMINAL_NELEM_GPR_READER_BYTE}, +{"NELEM_GPR_READER_SUBDWORD", XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD}, +{"NELEM_GPR_READER_WORD", XED_NONTERMINAL_NELEM_GPR_READER_WORD}, +{"NELEM_GPR_WRITER_LDOP", XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP}, +{"NELEM_GPR_WRITER_LDOP_D", XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D}, +{"NELEM_GPR_WRITER_LDOP_Q", XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q}, +{"NELEM_GPR_WRITER_STORE", XED_NONTERMINAL_NELEM_GPR_WRITER_STORE}, +{"NELEM_GPR_WRITER_STORE_BYTE", XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE}, +{"NELEM_GPR_WRITER_STORE_SUBDWORD", XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD}, +{"NELEM_GPR_WRITER_STORE_WORD", XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD}, +{"NELEM_GSCAT", XED_NONTERMINAL_NELEM_GSCAT}, +{"NELEM_HALF", XED_NONTERMINAL_NELEM_HALF}, +{"NELEM_HALFMEM", XED_NONTERMINAL_NELEM_HALFMEM}, +{"NELEM_MEM128", XED_NONTERMINAL_NELEM_MEM128}, +{"NELEM_MOVDDUP", XED_NONTERMINAL_NELEM_MOVDDUP}, +{"NELEM_QUARTER", XED_NONTERMINAL_NELEM_QUARTER}, +{"NELEM_QUARTERMEM", XED_NONTERMINAL_NELEM_QUARTERMEM}, +{"NELEM_SCALAR", XED_NONTERMINAL_NELEM_SCALAR}, +{"NELEM_TUPLE1", XED_NONTERMINAL_NELEM_TUPLE1}, +{"NELEM_TUPLE1_4X", XED_NONTERMINAL_NELEM_TUPLE1_4X}, +{"NELEM_TUPLE1_BYTE", XED_NONTERMINAL_NELEM_TUPLE1_BYTE}, +{"NELEM_TUPLE1_SUBDWORD", XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD}, +{"NELEM_TUPLE1_WORD", XED_NONTERMINAL_NELEM_TUPLE1_WORD}, +{"NELEM_TUPLE2", XED_NONTERMINAL_NELEM_TUPLE2}, +{"NELEM_TUPLE4", XED_NONTERMINAL_NELEM_TUPLE4}, +{"NELEM_TUPLE8", XED_NONTERMINAL_NELEM_TUPLE8}, +{"OEAX", XED_NONTERMINAL_OEAX}, +{"ONE", XED_NONTERMINAL_ONE}, +{"ORAX", XED_NONTERMINAL_ORAX}, +{"ORBP", XED_NONTERMINAL_ORBP}, +{"ORBX", XED_NONTERMINAL_ORBX}, +{"ORCX", XED_NONTERMINAL_ORCX}, +{"ORDX", XED_NONTERMINAL_ORDX}, +{"ORSP", XED_NONTERMINAL_ORSP}, +{"OSZ_NONTERM", XED_NONTERMINAL_OSZ_NONTERM}, +{"OVERRIDE_SEG0", XED_NONTERMINAL_OVERRIDE_SEG0}, +{"OVERRIDE_SEG1", XED_NONTERMINAL_OVERRIDE_SEG1}, +{"PREFIXES", XED_NONTERMINAL_PREFIXES}, +{"REFINING66", XED_NONTERMINAL_REFINING66}, +{"REMOVE_SEGMENT", XED_NONTERMINAL_REMOVE_SEGMENT}, +{"RFLAGS", XED_NONTERMINAL_RFLAGS}, +{"RIP", XED_NONTERMINAL_RIP}, +{"RIPA", XED_NONTERMINAL_RIPA}, +{"SAE", XED_NONTERMINAL_SAE}, +{"SEG", XED_NONTERMINAL_SEG}, +{"SEG_MOV", XED_NONTERMINAL_SEG_MOV}, +{"SE_IMM8", XED_NONTERMINAL_SE_IMM8}, +{"SIB", XED_NONTERMINAL_SIB}, +{"SIB_BASE0", XED_NONTERMINAL_SIB_BASE0}, +{"SIMM8", XED_NONTERMINAL_SIMM8}, +{"SIMMZ", XED_NONTERMINAL_SIMMZ}, +{"SRBP", XED_NONTERMINAL_SRBP}, +{"SRSP", XED_NONTERMINAL_SRSP}, +{"TMM_B", XED_NONTERMINAL_TMM_B}, +{"TMM_N", XED_NONTERMINAL_TMM_N}, +{"TMM_R", XED_NONTERMINAL_TMM_R}, +{"UIMM16", XED_NONTERMINAL_UIMM16}, +{"UIMM32", XED_NONTERMINAL_UIMM32}, +{"UIMM8", XED_NONTERMINAL_UIMM8}, +{"UIMM8_1", XED_NONTERMINAL_UIMM8_1}, +{"UIMMV", XED_NONTERMINAL_UIMMV}, +{"UISA_VMODRM_XMM", XED_NONTERMINAL_UISA_VMODRM_XMM}, +{"UISA_VMODRM_YMM", XED_NONTERMINAL_UISA_VMODRM_YMM}, +{"UISA_VMODRM_ZMM", XED_NONTERMINAL_UISA_VMODRM_ZMM}, +{"UISA_VSIB_BASE", XED_NONTERMINAL_UISA_VSIB_BASE}, +{"UISA_VSIB_INDEX_XMM", XED_NONTERMINAL_UISA_VSIB_INDEX_XMM}, +{"UISA_VSIB_INDEX_YMM", XED_NONTERMINAL_UISA_VSIB_INDEX_YMM}, +{"UISA_VSIB_INDEX_ZMM", XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM}, +{"UISA_VSIB_XMM", XED_NONTERMINAL_UISA_VSIB_XMM}, +{"UISA_VSIB_YMM", XED_NONTERMINAL_UISA_VSIB_YMM}, +{"UISA_VSIB_ZMM", XED_NONTERMINAL_UISA_VSIB_ZMM}, +{"VGPR32_B", XED_NONTERMINAL_VGPR32_B}, +{"VGPR32_B_32", XED_NONTERMINAL_VGPR32_B_32}, +{"VGPR32_B_64", XED_NONTERMINAL_VGPR32_B_64}, +{"VGPR32_N", XED_NONTERMINAL_VGPR32_N}, +{"VGPR32_N_32", XED_NONTERMINAL_VGPR32_N_32}, +{"VGPR32_N_64", XED_NONTERMINAL_VGPR32_N_64}, +{"VGPR32_R", XED_NONTERMINAL_VGPR32_R}, +{"VGPR32_R_32", XED_NONTERMINAL_VGPR32_R_32}, +{"VGPR32_R_64", XED_NONTERMINAL_VGPR32_R_64}, +{"VGPR64_B", XED_NONTERMINAL_VGPR64_B}, +{"VGPR64_N", XED_NONTERMINAL_VGPR64_N}, +{"VGPR64_R", XED_NONTERMINAL_VGPR64_R}, +{"VGPRY_B", XED_NONTERMINAL_VGPRY_B}, +{"VGPRY_N", XED_NONTERMINAL_VGPRY_N}, +{"VGPRY_R", XED_NONTERMINAL_VGPRY_R}, +{"VMODRM_XMM", XED_NONTERMINAL_VMODRM_XMM}, +{"VMODRM_YMM", XED_NONTERMINAL_VMODRM_YMM}, +{"VSIB_BASE", XED_NONTERMINAL_VSIB_BASE}, +{"VSIB_INDEX_XMM", XED_NONTERMINAL_VSIB_INDEX_XMM}, +{"VSIB_INDEX_YMM", XED_NONTERMINAL_VSIB_INDEX_YMM}, +{"VSIB_XMM", XED_NONTERMINAL_VSIB_XMM}, +{"VSIB_YMM", XED_NONTERMINAL_VSIB_YMM}, +{"X87", XED_NONTERMINAL_X87}, +{"XMM_B", XED_NONTERMINAL_XMM_B}, +{"XMM_B3", XED_NONTERMINAL_XMM_B3}, +{"XMM_B3_32", XED_NONTERMINAL_XMM_B3_32}, +{"XMM_B3_64", XED_NONTERMINAL_XMM_B3_64}, +{"XMM_B_32", XED_NONTERMINAL_XMM_B_32}, +{"XMM_B_64", XED_NONTERMINAL_XMM_B_64}, +{"XMM_N", XED_NONTERMINAL_XMM_N}, +{"XMM_N3", XED_NONTERMINAL_XMM_N3}, +{"XMM_N3_32", XED_NONTERMINAL_XMM_N3_32}, +{"XMM_N3_64", XED_NONTERMINAL_XMM_N3_64}, +{"XMM_N_32", XED_NONTERMINAL_XMM_N_32}, +{"XMM_N_64", XED_NONTERMINAL_XMM_N_64}, +{"XMM_R", XED_NONTERMINAL_XMM_R}, +{"XMM_R3", XED_NONTERMINAL_XMM_R3}, +{"XMM_R3_32", XED_NONTERMINAL_XMM_R3_32}, +{"XMM_R3_64", XED_NONTERMINAL_XMM_R3_64}, +{"XMM_R_32", XED_NONTERMINAL_XMM_R_32}, +{"XMM_R_64", XED_NONTERMINAL_XMM_R_64}, +{"XMM_SE", XED_NONTERMINAL_XMM_SE}, +{"XMM_SE32", XED_NONTERMINAL_XMM_SE32}, +{"XMM_SE64", XED_NONTERMINAL_XMM_SE64}, +{"XOP_INSTRUCTIONS", XED_NONTERMINAL_XOP_INSTRUCTIONS}, +{"YMM_B", XED_NONTERMINAL_YMM_B}, +{"YMM_B3", XED_NONTERMINAL_YMM_B3}, +{"YMM_B3_32", XED_NONTERMINAL_YMM_B3_32}, +{"YMM_B3_64", XED_NONTERMINAL_YMM_B3_64}, +{"YMM_B_32", XED_NONTERMINAL_YMM_B_32}, +{"YMM_B_64", XED_NONTERMINAL_YMM_B_64}, +{"YMM_N", XED_NONTERMINAL_YMM_N}, +{"YMM_N3", XED_NONTERMINAL_YMM_N3}, +{"YMM_N3_32", XED_NONTERMINAL_YMM_N3_32}, +{"YMM_N3_64", XED_NONTERMINAL_YMM_N3_64}, +{"YMM_N_32", XED_NONTERMINAL_YMM_N_32}, +{"YMM_N_64", XED_NONTERMINAL_YMM_N_64}, +{"YMM_R", XED_NONTERMINAL_YMM_R}, +{"YMM_R3", XED_NONTERMINAL_YMM_R3}, +{"YMM_R3_32", XED_NONTERMINAL_YMM_R3_32}, +{"YMM_R3_64", XED_NONTERMINAL_YMM_R3_64}, +{"YMM_R_32", XED_NONTERMINAL_YMM_R_32}, +{"YMM_R_64", XED_NONTERMINAL_YMM_R_64}, +{"YMM_SE", XED_NONTERMINAL_YMM_SE}, +{"YMM_SE32", XED_NONTERMINAL_YMM_SE32}, +{"YMM_SE64", XED_NONTERMINAL_YMM_SE64}, +{"ZMM_B3", XED_NONTERMINAL_ZMM_B3}, +{"ZMM_B3_32", XED_NONTERMINAL_ZMM_B3_32}, +{"ZMM_B3_64", XED_NONTERMINAL_ZMM_B3_64}, +{"ZMM_N3", XED_NONTERMINAL_ZMM_N3}, +{"ZMM_N3_32", XED_NONTERMINAL_ZMM_N3_32}, +{"ZMM_N3_64", XED_NONTERMINAL_ZMM_N3_64}, +{"ZMM_R3", XED_NONTERMINAL_ZMM_R3}, +{"ZMM_R3_32", XED_NONTERMINAL_ZMM_R3_32}, +{"ZMM_R3_64", XED_NONTERMINAL_ZMM_R3_64}, +{"LAST", XED_NONTERMINAL_LAST}, +{0, XED_NONTERMINAL_LAST}, +}; + + +xed_nonterminal_enum_t str2xed_nonterminal_enum_t(const char* s) +{ + const name_table_xed_nonterminal_enum_t* p = name_array_xed_nonterminal_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_NONTERMINAL_INVALID; +} + + +const char* xed_nonterminal_enum_t2str(const xed_nonterminal_enum_t p) +{ + xed_nonterminal_enum_t type_idx = p; + if ( p > XED_NONTERMINAL_LAST) type_idx = XED_NONTERMINAL_LAST; + return name_array_xed_nonterminal_enum_t[type_idx].name; +} + +xed_nonterminal_enum_t xed_nonterminal_enum_t_last(void) { + return XED_NONTERMINAL_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_NONTERMINAL_INVALID: + case XED_NONTERMINAL_AR10: + case XED_NONTERMINAL_AR11: + case XED_NONTERMINAL_AR12: + case XED_NONTERMINAL_AR13: + case XED_NONTERMINAL_AR14: + case XED_NONTERMINAL_AR15: + case XED_NONTERMINAL_AR8: + case XED_NONTERMINAL_AR9: + case XED_NONTERMINAL_ARAX: + case XED_NONTERMINAL_ARBP: + case XED_NONTERMINAL_ARBX: + case XED_NONTERMINAL_ARCX: + case XED_NONTERMINAL_ARDI: + case XED_NONTERMINAL_ARDX: + case XED_NONTERMINAL_ARSI: + case XED_NONTERMINAL_ARSP: + case XED_NONTERMINAL_ASZ_NONTERM: + case XED_NONTERMINAL_AVX512_ROUND: + case XED_NONTERMINAL_AVX_INSTRUCTIONS: + case XED_NONTERMINAL_AVX_SPLITTER: + case XED_NONTERMINAL_A_GPR_B: + case XED_NONTERMINAL_A_GPR_R: + case XED_NONTERMINAL_BND_B: + case XED_NONTERMINAL_BND_B_CHECK: + case XED_NONTERMINAL_BND_R: + case XED_NONTERMINAL_BND_R_CHECK: + case XED_NONTERMINAL_BRANCH_HINT: + case XED_NONTERMINAL_BRDISP32: + case XED_NONTERMINAL_BRDISP8: + case XED_NONTERMINAL_BRDISPZ: + case XED_NONTERMINAL_CET_NO_TRACK: + case XED_NONTERMINAL_CR_B: + case XED_NONTERMINAL_CR_R: + case XED_NONTERMINAL_CR_WIDTH: + case XED_NONTERMINAL_DF64: + case XED_NONTERMINAL_DR_R: + case XED_NONTERMINAL_ESIZE_128_BITS: + case XED_NONTERMINAL_ESIZE_16_BITS: + case XED_NONTERMINAL_ESIZE_1_BITS: + case XED_NONTERMINAL_ESIZE_2_BITS: + case XED_NONTERMINAL_ESIZE_32_BITS: + case XED_NONTERMINAL_ESIZE_4_BITS: + case XED_NONTERMINAL_ESIZE_64_BITS: + case XED_NONTERMINAL_ESIZE_8_BITS: + case XED_NONTERMINAL_EVEX_INSTRUCTIONS: + case XED_NONTERMINAL_EVEX_SPLITTER: + case XED_NONTERMINAL_FINAL_DSEG: + case XED_NONTERMINAL_FINAL_DSEG1: + case XED_NONTERMINAL_FINAL_DSEG1_MODE64: + case XED_NONTERMINAL_FINAL_DSEG1_NOT64: + case XED_NONTERMINAL_FINAL_DSEG_MODE64: + case XED_NONTERMINAL_FINAL_DSEG_NOT64: + case XED_NONTERMINAL_FINAL_ESEG: + case XED_NONTERMINAL_FINAL_ESEG1: + case XED_NONTERMINAL_FINAL_SSEG: + case XED_NONTERMINAL_FINAL_SSEG0: + case XED_NONTERMINAL_FINAL_SSEG1: + case XED_NONTERMINAL_FINAL_SSEG_MODE64: + case XED_NONTERMINAL_FINAL_SSEG_NOT64: + case XED_NONTERMINAL_FIX_ROUND_LEN128: + case XED_NONTERMINAL_FIX_ROUND_LEN512: + case XED_NONTERMINAL_FORCE64: + case XED_NONTERMINAL_GPR16_B: + case XED_NONTERMINAL_GPR16_R: + case XED_NONTERMINAL_GPR16_SB: + case XED_NONTERMINAL_GPR32_B: + case XED_NONTERMINAL_GPR32_R: + case XED_NONTERMINAL_GPR32_SB: + case XED_NONTERMINAL_GPR32_X: + case XED_NONTERMINAL_GPR64_B: + case XED_NONTERMINAL_GPR64_R: + case XED_NONTERMINAL_GPR64_SB: + case XED_NONTERMINAL_GPR64_X: + case XED_NONTERMINAL_GPR8_B: + case XED_NONTERMINAL_GPR8_R: + case XED_NONTERMINAL_GPR8_SB: + case XED_NONTERMINAL_GPRV_B: + case XED_NONTERMINAL_GPRV_R: + case XED_NONTERMINAL_GPRV_SB: + case XED_NONTERMINAL_GPRY_B: + case XED_NONTERMINAL_GPRY_R: + case XED_NONTERMINAL_GPRZ_B: + case XED_NONTERMINAL_GPRZ_R: + case XED_NONTERMINAL_IGNORE66: + case XED_NONTERMINAL_IMMUNE66: + case XED_NONTERMINAL_IMMUNE66_LOOP64: + case XED_NONTERMINAL_IMMUNE_REXW: + case XED_NONTERMINAL_INSTRUCTIONS: + case XED_NONTERMINAL_ISA: + case XED_NONTERMINAL_MASK1: + case XED_NONTERMINAL_MASKNOT0: + case XED_NONTERMINAL_MASK_B: + case XED_NONTERMINAL_MASK_N: + case XED_NONTERMINAL_MASK_N32: + case XED_NONTERMINAL_MASK_N64: + case XED_NONTERMINAL_MASK_R: + case XED_NONTERMINAL_MEMDISP: + case XED_NONTERMINAL_MEMDISP16: + case XED_NONTERMINAL_MEMDISP32: + case XED_NONTERMINAL_MEMDISP8: + case XED_NONTERMINAL_MEMDISPV: + case XED_NONTERMINAL_MMX_B: + case XED_NONTERMINAL_MMX_R: + case XED_NONTERMINAL_MODRM: + case XED_NONTERMINAL_MODRM16: + case XED_NONTERMINAL_MODRM32: + case XED_NONTERMINAL_MODRM64ALT32: + case XED_NONTERMINAL_NELEM_EIGHTHMEM: + case XED_NONTERMINAL_NELEM_FULL: + case XED_NONTERMINAL_NELEM_FULLMEM: + case XED_NONTERMINAL_NELEM_GPR_READER: + case XED_NONTERMINAL_NELEM_GPR_READER_BYTE: + case XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD: + case XED_NONTERMINAL_NELEM_GPR_READER_WORD: + case XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP: + case XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D: + case XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q: + case XED_NONTERMINAL_NELEM_GPR_WRITER_STORE: + case XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE: + case XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD: + case XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD: + case XED_NONTERMINAL_NELEM_GSCAT: + case XED_NONTERMINAL_NELEM_HALF: + case XED_NONTERMINAL_NELEM_HALFMEM: + case XED_NONTERMINAL_NELEM_MEM128: + case XED_NONTERMINAL_NELEM_MOVDDUP: + case XED_NONTERMINAL_NELEM_QUARTER: + case XED_NONTERMINAL_NELEM_QUARTERMEM: + case XED_NONTERMINAL_NELEM_SCALAR: + case XED_NONTERMINAL_NELEM_TUPLE1: + case XED_NONTERMINAL_NELEM_TUPLE1_4X: + case XED_NONTERMINAL_NELEM_TUPLE1_BYTE: + case XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD: + case XED_NONTERMINAL_NELEM_TUPLE1_WORD: + case XED_NONTERMINAL_NELEM_TUPLE2: + case XED_NONTERMINAL_NELEM_TUPLE4: + case XED_NONTERMINAL_NELEM_TUPLE8: + case XED_NONTERMINAL_OEAX: + case XED_NONTERMINAL_ONE: + case XED_NONTERMINAL_ORAX: + case XED_NONTERMINAL_ORBP: + case XED_NONTERMINAL_ORBX: + case XED_NONTERMINAL_ORCX: + case XED_NONTERMINAL_ORDX: + case XED_NONTERMINAL_ORSP: + case XED_NONTERMINAL_OSZ_NONTERM: + case XED_NONTERMINAL_OVERRIDE_SEG0: + case XED_NONTERMINAL_OVERRIDE_SEG1: + case XED_NONTERMINAL_PREFIXES: + case XED_NONTERMINAL_REFINING66: + case XED_NONTERMINAL_REMOVE_SEGMENT: + case XED_NONTERMINAL_RFLAGS: + case XED_NONTERMINAL_RIP: + case XED_NONTERMINAL_RIPA: + case XED_NONTERMINAL_SAE: + case XED_NONTERMINAL_SEG: + case XED_NONTERMINAL_SEG_MOV: + case XED_NONTERMINAL_SE_IMM8: + case XED_NONTERMINAL_SIB: + case XED_NONTERMINAL_SIB_BASE0: + case XED_NONTERMINAL_SIMM8: + case XED_NONTERMINAL_SIMMZ: + case XED_NONTERMINAL_SRBP: + case XED_NONTERMINAL_SRSP: + case XED_NONTERMINAL_TMM_B: + case XED_NONTERMINAL_TMM_N: + case XED_NONTERMINAL_TMM_R: + case XED_NONTERMINAL_UIMM16: + case XED_NONTERMINAL_UIMM32: + case XED_NONTERMINAL_UIMM8: + case XED_NONTERMINAL_UIMM8_1: + case XED_NONTERMINAL_UIMMV: + case XED_NONTERMINAL_UISA_VMODRM_XMM: + case XED_NONTERMINAL_UISA_VMODRM_YMM: + case XED_NONTERMINAL_UISA_VMODRM_ZMM: + case XED_NONTERMINAL_UISA_VSIB_BASE: + case XED_NONTERMINAL_UISA_VSIB_INDEX_XMM: + case XED_NONTERMINAL_UISA_VSIB_INDEX_YMM: + case XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM: + case XED_NONTERMINAL_UISA_VSIB_XMM: + case XED_NONTERMINAL_UISA_VSIB_YMM: + case XED_NONTERMINAL_UISA_VSIB_ZMM: + case XED_NONTERMINAL_VGPR32_B: + case XED_NONTERMINAL_VGPR32_B_32: + case XED_NONTERMINAL_VGPR32_B_64: + case XED_NONTERMINAL_VGPR32_N: + case XED_NONTERMINAL_VGPR32_N_32: + case XED_NONTERMINAL_VGPR32_N_64: + case XED_NONTERMINAL_VGPR32_R: + case XED_NONTERMINAL_VGPR32_R_32: + case XED_NONTERMINAL_VGPR32_R_64: + case XED_NONTERMINAL_VGPR64_B: + case XED_NONTERMINAL_VGPR64_N: + case XED_NONTERMINAL_VGPR64_R: + case XED_NONTERMINAL_VGPRY_B: + case XED_NONTERMINAL_VGPRY_N: + case XED_NONTERMINAL_VGPRY_R: + case XED_NONTERMINAL_VMODRM_XMM: + case XED_NONTERMINAL_VMODRM_YMM: + case XED_NONTERMINAL_VSIB_BASE: + case XED_NONTERMINAL_VSIB_INDEX_XMM: + case XED_NONTERMINAL_VSIB_INDEX_YMM: + case XED_NONTERMINAL_VSIB_XMM: + case XED_NONTERMINAL_VSIB_YMM: + case XED_NONTERMINAL_X87: + case XED_NONTERMINAL_XMM_B: + case XED_NONTERMINAL_XMM_B3: + case XED_NONTERMINAL_XMM_B3_32: + case XED_NONTERMINAL_XMM_B3_64: + case XED_NONTERMINAL_XMM_B_32: + case XED_NONTERMINAL_XMM_B_64: + case XED_NONTERMINAL_XMM_N: + case XED_NONTERMINAL_XMM_N3: + case XED_NONTERMINAL_XMM_N3_32: + case XED_NONTERMINAL_XMM_N3_64: + case XED_NONTERMINAL_XMM_N_32: + case XED_NONTERMINAL_XMM_N_64: + case XED_NONTERMINAL_XMM_R: + case XED_NONTERMINAL_XMM_R3: + case XED_NONTERMINAL_XMM_R3_32: + case XED_NONTERMINAL_XMM_R3_64: + case XED_NONTERMINAL_XMM_R_32: + case XED_NONTERMINAL_XMM_R_64: + case XED_NONTERMINAL_XMM_SE: + case XED_NONTERMINAL_XMM_SE32: + case XED_NONTERMINAL_XMM_SE64: + case XED_NONTERMINAL_XOP_INSTRUCTIONS: + case XED_NONTERMINAL_YMM_B: + case XED_NONTERMINAL_YMM_B3: + case XED_NONTERMINAL_YMM_B3_32: + case XED_NONTERMINAL_YMM_B3_64: + case XED_NONTERMINAL_YMM_B_32: + case XED_NONTERMINAL_YMM_B_64: + case XED_NONTERMINAL_YMM_N: + case XED_NONTERMINAL_YMM_N3: + case XED_NONTERMINAL_YMM_N3_32: + case XED_NONTERMINAL_YMM_N3_64: + case XED_NONTERMINAL_YMM_N_32: + case XED_NONTERMINAL_YMM_N_64: + case XED_NONTERMINAL_YMM_R: + case XED_NONTERMINAL_YMM_R3: + case XED_NONTERMINAL_YMM_R3_32: + case XED_NONTERMINAL_YMM_R3_64: + case XED_NONTERMINAL_YMM_R_32: + case XED_NONTERMINAL_YMM_R_64: + case XED_NONTERMINAL_YMM_SE: + case XED_NONTERMINAL_YMM_SE32: + case XED_NONTERMINAL_YMM_SE64: + case XED_NONTERMINAL_ZMM_B3: + case XED_NONTERMINAL_ZMM_B3_32: + case XED_NONTERMINAL_ZMM_B3_64: + case XED_NONTERMINAL_ZMM_N3: + case XED_NONTERMINAL_ZMM_N3_32: + case XED_NONTERMINAL_ZMM_N3_64: + case XED_NONTERMINAL_ZMM_R3: + case XED_NONTERMINAL_ZMM_R3_32: + case XED_NONTERMINAL_ZMM_R3_64: + case XED_NONTERMINAL_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-nonterminal-enum.h b/CodeVirtualizer/build/obj/xed-nonterminal-enum.h new file mode 100644 index 0000000..0256187 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-nonterminal-enum.h @@ -0,0 +1,545 @@ +/// @file xed-nonterminal-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_NONTERMINAL_ENUM_H) +# define XED_NONTERMINAL_ENUM_H +#include "xed-common-hdrs.h" +#define XED_NONTERMINAL_INVALID_DEFINED 1 +#define XED_NONTERMINAL_AR10_DEFINED 1 +#define XED_NONTERMINAL_AR11_DEFINED 1 +#define XED_NONTERMINAL_AR12_DEFINED 1 +#define XED_NONTERMINAL_AR13_DEFINED 1 +#define XED_NONTERMINAL_AR14_DEFINED 1 +#define XED_NONTERMINAL_AR15_DEFINED 1 +#define XED_NONTERMINAL_AR8_DEFINED 1 +#define XED_NONTERMINAL_AR9_DEFINED 1 +#define XED_NONTERMINAL_ARAX_DEFINED 1 +#define XED_NONTERMINAL_ARBP_DEFINED 1 +#define XED_NONTERMINAL_ARBX_DEFINED 1 +#define XED_NONTERMINAL_ARCX_DEFINED 1 +#define XED_NONTERMINAL_ARDI_DEFINED 1 +#define XED_NONTERMINAL_ARDX_DEFINED 1 +#define XED_NONTERMINAL_ARSI_DEFINED 1 +#define XED_NONTERMINAL_ARSP_DEFINED 1 +#define XED_NONTERMINAL_ASZ_NONTERM_DEFINED 1 +#define XED_NONTERMINAL_AVX512_ROUND_DEFINED 1 +#define XED_NONTERMINAL_AVX_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_AVX_SPLITTER_DEFINED 1 +#define XED_NONTERMINAL_A_GPR_B_DEFINED 1 +#define XED_NONTERMINAL_A_GPR_R_DEFINED 1 +#define XED_NONTERMINAL_BND_B_DEFINED 1 +#define XED_NONTERMINAL_BND_B_CHECK_DEFINED 1 +#define XED_NONTERMINAL_BND_R_DEFINED 1 +#define XED_NONTERMINAL_BND_R_CHECK_DEFINED 1 +#define XED_NONTERMINAL_BRANCH_HINT_DEFINED 1 +#define XED_NONTERMINAL_BRDISP32_DEFINED 1 +#define XED_NONTERMINAL_BRDISP8_DEFINED 1 +#define XED_NONTERMINAL_BRDISPZ_DEFINED 1 +#define XED_NONTERMINAL_CET_NO_TRACK_DEFINED 1 +#define XED_NONTERMINAL_CR_B_DEFINED 1 +#define XED_NONTERMINAL_CR_R_DEFINED 1 +#define XED_NONTERMINAL_CR_WIDTH_DEFINED 1 +#define XED_NONTERMINAL_DF64_DEFINED 1 +#define XED_NONTERMINAL_DR_R_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_128_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_16_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_1_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_2_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_32_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_4_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_64_BITS_DEFINED 1 +#define XED_NONTERMINAL_ESIZE_8_BITS_DEFINED 1 +#define XED_NONTERMINAL_EVEX_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_EVEX_SPLITTER_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG1_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG1_MODE64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG1_NOT64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG_MODE64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_DSEG_NOT64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_ESEG_DEFINED 1 +#define XED_NONTERMINAL_FINAL_ESEG1_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG0_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG1_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG_MODE64_DEFINED 1 +#define XED_NONTERMINAL_FINAL_SSEG_NOT64_DEFINED 1 +#define XED_NONTERMINAL_FIX_ROUND_LEN128_DEFINED 1 +#define XED_NONTERMINAL_FIX_ROUND_LEN512_DEFINED 1 +#define XED_NONTERMINAL_FORCE64_DEFINED 1 +#define XED_NONTERMINAL_GPR16_B_DEFINED 1 +#define XED_NONTERMINAL_GPR16_R_DEFINED 1 +#define XED_NONTERMINAL_GPR16_SB_DEFINED 1 +#define XED_NONTERMINAL_GPR32_B_DEFINED 1 +#define XED_NONTERMINAL_GPR32_R_DEFINED 1 +#define XED_NONTERMINAL_GPR32_SB_DEFINED 1 +#define XED_NONTERMINAL_GPR32_X_DEFINED 1 +#define XED_NONTERMINAL_GPR64_B_DEFINED 1 +#define XED_NONTERMINAL_GPR64_R_DEFINED 1 +#define XED_NONTERMINAL_GPR64_SB_DEFINED 1 +#define XED_NONTERMINAL_GPR64_X_DEFINED 1 +#define XED_NONTERMINAL_GPR8_B_DEFINED 1 +#define XED_NONTERMINAL_GPR8_R_DEFINED 1 +#define XED_NONTERMINAL_GPR8_SB_DEFINED 1 +#define XED_NONTERMINAL_GPRV_B_DEFINED 1 +#define XED_NONTERMINAL_GPRV_R_DEFINED 1 +#define XED_NONTERMINAL_GPRV_SB_DEFINED 1 +#define XED_NONTERMINAL_GPRY_B_DEFINED 1 +#define XED_NONTERMINAL_GPRY_R_DEFINED 1 +#define XED_NONTERMINAL_GPRZ_B_DEFINED 1 +#define XED_NONTERMINAL_GPRZ_R_DEFINED 1 +#define XED_NONTERMINAL_IGNORE66_DEFINED 1 +#define XED_NONTERMINAL_IMMUNE66_DEFINED 1 +#define XED_NONTERMINAL_IMMUNE66_LOOP64_DEFINED 1 +#define XED_NONTERMINAL_IMMUNE_REXW_DEFINED 1 +#define XED_NONTERMINAL_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_ISA_DEFINED 1 +#define XED_NONTERMINAL_MASK1_DEFINED 1 +#define XED_NONTERMINAL_MASKNOT0_DEFINED 1 +#define XED_NONTERMINAL_MASK_B_DEFINED 1 +#define XED_NONTERMINAL_MASK_N_DEFINED 1 +#define XED_NONTERMINAL_MASK_N32_DEFINED 1 +#define XED_NONTERMINAL_MASK_N64_DEFINED 1 +#define XED_NONTERMINAL_MASK_R_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP16_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP32_DEFINED 1 +#define XED_NONTERMINAL_MEMDISP8_DEFINED 1 +#define XED_NONTERMINAL_MEMDISPV_DEFINED 1 +#define XED_NONTERMINAL_MMX_B_DEFINED 1 +#define XED_NONTERMINAL_MMX_R_DEFINED 1 +#define XED_NONTERMINAL_MODRM_DEFINED 1 +#define XED_NONTERMINAL_MODRM16_DEFINED 1 +#define XED_NONTERMINAL_MODRM32_DEFINED 1 +#define XED_NONTERMINAL_MODRM64ALT32_DEFINED 1 +#define XED_NONTERMINAL_NELEM_EIGHTHMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_FULL_DEFINED 1 +#define XED_NONTERMINAL_NELEM_FULLMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_BYTE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_READER_WORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_GSCAT_DEFINED 1 +#define XED_NONTERMINAL_NELEM_HALF_DEFINED 1 +#define XED_NONTERMINAL_NELEM_HALFMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_MEM128_DEFINED 1 +#define XED_NONTERMINAL_NELEM_MOVDDUP_DEFINED 1 +#define XED_NONTERMINAL_NELEM_QUARTER_DEFINED 1 +#define XED_NONTERMINAL_NELEM_QUARTERMEM_DEFINED 1 +#define XED_NONTERMINAL_NELEM_SCALAR_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_4X_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_BYTE_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE1_WORD_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE2_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE4_DEFINED 1 +#define XED_NONTERMINAL_NELEM_TUPLE8_DEFINED 1 +#define XED_NONTERMINAL_OEAX_DEFINED 1 +#define XED_NONTERMINAL_ONE_DEFINED 1 +#define XED_NONTERMINAL_ORAX_DEFINED 1 +#define XED_NONTERMINAL_ORBP_DEFINED 1 +#define XED_NONTERMINAL_ORBX_DEFINED 1 +#define XED_NONTERMINAL_ORCX_DEFINED 1 +#define XED_NONTERMINAL_ORDX_DEFINED 1 +#define XED_NONTERMINAL_ORSP_DEFINED 1 +#define XED_NONTERMINAL_OSZ_NONTERM_DEFINED 1 +#define XED_NONTERMINAL_OVERRIDE_SEG0_DEFINED 1 +#define XED_NONTERMINAL_OVERRIDE_SEG1_DEFINED 1 +#define XED_NONTERMINAL_PREFIXES_DEFINED 1 +#define XED_NONTERMINAL_REFINING66_DEFINED 1 +#define XED_NONTERMINAL_REMOVE_SEGMENT_DEFINED 1 +#define XED_NONTERMINAL_RFLAGS_DEFINED 1 +#define XED_NONTERMINAL_RIP_DEFINED 1 +#define XED_NONTERMINAL_RIPA_DEFINED 1 +#define XED_NONTERMINAL_SAE_DEFINED 1 +#define XED_NONTERMINAL_SEG_DEFINED 1 +#define XED_NONTERMINAL_SEG_MOV_DEFINED 1 +#define XED_NONTERMINAL_SE_IMM8_DEFINED 1 +#define XED_NONTERMINAL_SIB_DEFINED 1 +#define XED_NONTERMINAL_SIB_BASE0_DEFINED 1 +#define XED_NONTERMINAL_SIMM8_DEFINED 1 +#define XED_NONTERMINAL_SIMMZ_DEFINED 1 +#define XED_NONTERMINAL_SRBP_DEFINED 1 +#define XED_NONTERMINAL_SRSP_DEFINED 1 +#define XED_NONTERMINAL_TMM_B_DEFINED 1 +#define XED_NONTERMINAL_TMM_N_DEFINED 1 +#define XED_NONTERMINAL_TMM_R_DEFINED 1 +#define XED_NONTERMINAL_UIMM16_DEFINED 1 +#define XED_NONTERMINAL_UIMM32_DEFINED 1 +#define XED_NONTERMINAL_UIMM8_DEFINED 1 +#define XED_NONTERMINAL_UIMM8_1_DEFINED 1 +#define XED_NONTERMINAL_UIMMV_DEFINED 1 +#define XED_NONTERMINAL_UISA_VMODRM_XMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VMODRM_YMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VMODRM_ZMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_BASE_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_INDEX_XMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_INDEX_YMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_XMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_YMM_DEFINED 1 +#define XED_NONTERMINAL_UISA_VSIB_ZMM_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_B_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_B_32_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_B_64_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_N_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_N_32_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_N_64_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_R_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_R_32_DEFINED 1 +#define XED_NONTERMINAL_VGPR32_R_64_DEFINED 1 +#define XED_NONTERMINAL_VGPR64_B_DEFINED 1 +#define XED_NONTERMINAL_VGPR64_N_DEFINED 1 +#define XED_NONTERMINAL_VGPR64_R_DEFINED 1 +#define XED_NONTERMINAL_VGPRY_B_DEFINED 1 +#define XED_NONTERMINAL_VGPRY_N_DEFINED 1 +#define XED_NONTERMINAL_VGPRY_R_DEFINED 1 +#define XED_NONTERMINAL_VMODRM_XMM_DEFINED 1 +#define XED_NONTERMINAL_VMODRM_YMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_BASE_DEFINED 1 +#define XED_NONTERMINAL_VSIB_INDEX_XMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_INDEX_YMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_XMM_DEFINED 1 +#define XED_NONTERMINAL_VSIB_YMM_DEFINED 1 +#define XED_NONTERMINAL_X87_DEFINED 1 +#define XED_NONTERMINAL_XMM_B_DEFINED 1 +#define XED_NONTERMINAL_XMM_B3_DEFINED 1 +#define XED_NONTERMINAL_XMM_B3_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_B3_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_B_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_B_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_N_DEFINED 1 +#define XED_NONTERMINAL_XMM_N3_DEFINED 1 +#define XED_NONTERMINAL_XMM_N3_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_N3_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_N_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_N_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_R_DEFINED 1 +#define XED_NONTERMINAL_XMM_R3_DEFINED 1 +#define XED_NONTERMINAL_XMM_R3_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_R3_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_R_32_DEFINED 1 +#define XED_NONTERMINAL_XMM_R_64_DEFINED 1 +#define XED_NONTERMINAL_XMM_SE_DEFINED 1 +#define XED_NONTERMINAL_XMM_SE32_DEFINED 1 +#define XED_NONTERMINAL_XMM_SE64_DEFINED 1 +#define XED_NONTERMINAL_XOP_INSTRUCTIONS_DEFINED 1 +#define XED_NONTERMINAL_YMM_B_DEFINED 1 +#define XED_NONTERMINAL_YMM_B3_DEFINED 1 +#define XED_NONTERMINAL_YMM_B3_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_B3_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_B_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_B_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_N_DEFINED 1 +#define XED_NONTERMINAL_YMM_N3_DEFINED 1 +#define XED_NONTERMINAL_YMM_N3_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_N3_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_N_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_N_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_R_DEFINED 1 +#define XED_NONTERMINAL_YMM_R3_DEFINED 1 +#define XED_NONTERMINAL_YMM_R3_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_R3_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_R_32_DEFINED 1 +#define XED_NONTERMINAL_YMM_R_64_DEFINED 1 +#define XED_NONTERMINAL_YMM_SE_DEFINED 1 +#define XED_NONTERMINAL_YMM_SE32_DEFINED 1 +#define XED_NONTERMINAL_YMM_SE64_DEFINED 1 +#define XED_NONTERMINAL_ZMM_B3_DEFINED 1 +#define XED_NONTERMINAL_ZMM_B3_32_DEFINED 1 +#define XED_NONTERMINAL_ZMM_B3_64_DEFINED 1 +#define XED_NONTERMINAL_ZMM_N3_DEFINED 1 +#define XED_NONTERMINAL_ZMM_N3_32_DEFINED 1 +#define XED_NONTERMINAL_ZMM_N3_64_DEFINED 1 +#define XED_NONTERMINAL_ZMM_R3_DEFINED 1 +#define XED_NONTERMINAL_ZMM_R3_32_DEFINED 1 +#define XED_NONTERMINAL_ZMM_R3_64_DEFINED 1 +#define XED_NONTERMINAL_LAST_DEFINED 1 +typedef enum { + XED_NONTERMINAL_INVALID, + XED_NONTERMINAL_AR10, + XED_NONTERMINAL_AR11, + XED_NONTERMINAL_AR12, + XED_NONTERMINAL_AR13, + XED_NONTERMINAL_AR14, + XED_NONTERMINAL_AR15, + XED_NONTERMINAL_AR8, + XED_NONTERMINAL_AR9, + XED_NONTERMINAL_ARAX, + XED_NONTERMINAL_ARBP, + XED_NONTERMINAL_ARBX, + XED_NONTERMINAL_ARCX, + XED_NONTERMINAL_ARDI, + XED_NONTERMINAL_ARDX, + XED_NONTERMINAL_ARSI, + XED_NONTERMINAL_ARSP, + XED_NONTERMINAL_ASZ_NONTERM, + XED_NONTERMINAL_AVX512_ROUND, + XED_NONTERMINAL_AVX_INSTRUCTIONS, + XED_NONTERMINAL_AVX_SPLITTER, + XED_NONTERMINAL_A_GPR_B, + XED_NONTERMINAL_A_GPR_R, + XED_NONTERMINAL_BND_B, + XED_NONTERMINAL_BND_B_CHECK, + XED_NONTERMINAL_BND_R, + XED_NONTERMINAL_BND_R_CHECK, + XED_NONTERMINAL_BRANCH_HINT, + XED_NONTERMINAL_BRDISP32, + XED_NONTERMINAL_BRDISP8, + XED_NONTERMINAL_BRDISPZ, + XED_NONTERMINAL_CET_NO_TRACK, + XED_NONTERMINAL_CR_B, + XED_NONTERMINAL_CR_R, + XED_NONTERMINAL_CR_WIDTH, + XED_NONTERMINAL_DF64, + XED_NONTERMINAL_DR_R, + XED_NONTERMINAL_ESIZE_128_BITS, + XED_NONTERMINAL_ESIZE_16_BITS, + XED_NONTERMINAL_ESIZE_1_BITS, + XED_NONTERMINAL_ESIZE_2_BITS, + XED_NONTERMINAL_ESIZE_32_BITS, + XED_NONTERMINAL_ESIZE_4_BITS, + XED_NONTERMINAL_ESIZE_64_BITS, + XED_NONTERMINAL_ESIZE_8_BITS, + XED_NONTERMINAL_EVEX_INSTRUCTIONS, + XED_NONTERMINAL_EVEX_SPLITTER, + XED_NONTERMINAL_FINAL_DSEG, + XED_NONTERMINAL_FINAL_DSEG1, + XED_NONTERMINAL_FINAL_DSEG1_MODE64, + XED_NONTERMINAL_FINAL_DSEG1_NOT64, + XED_NONTERMINAL_FINAL_DSEG_MODE64, + XED_NONTERMINAL_FINAL_DSEG_NOT64, + XED_NONTERMINAL_FINAL_ESEG, + XED_NONTERMINAL_FINAL_ESEG1, + XED_NONTERMINAL_FINAL_SSEG, + XED_NONTERMINAL_FINAL_SSEG0, + XED_NONTERMINAL_FINAL_SSEG1, + XED_NONTERMINAL_FINAL_SSEG_MODE64, + XED_NONTERMINAL_FINAL_SSEG_NOT64, + XED_NONTERMINAL_FIX_ROUND_LEN128, + XED_NONTERMINAL_FIX_ROUND_LEN512, + XED_NONTERMINAL_FORCE64, + XED_NONTERMINAL_GPR16_B, + XED_NONTERMINAL_GPR16_R, + XED_NONTERMINAL_GPR16_SB, + XED_NONTERMINAL_GPR32_B, + XED_NONTERMINAL_GPR32_R, + XED_NONTERMINAL_GPR32_SB, + XED_NONTERMINAL_GPR32_X, + XED_NONTERMINAL_GPR64_B, + XED_NONTERMINAL_GPR64_R, + XED_NONTERMINAL_GPR64_SB, + XED_NONTERMINAL_GPR64_X, + XED_NONTERMINAL_GPR8_B, + XED_NONTERMINAL_GPR8_R, + XED_NONTERMINAL_GPR8_SB, + XED_NONTERMINAL_GPRV_B, + XED_NONTERMINAL_GPRV_R, + XED_NONTERMINAL_GPRV_SB, + XED_NONTERMINAL_GPRY_B, + XED_NONTERMINAL_GPRY_R, + XED_NONTERMINAL_GPRZ_B, + XED_NONTERMINAL_GPRZ_R, + XED_NONTERMINAL_IGNORE66, + XED_NONTERMINAL_IMMUNE66, + XED_NONTERMINAL_IMMUNE66_LOOP64, + XED_NONTERMINAL_IMMUNE_REXW, + XED_NONTERMINAL_INSTRUCTIONS, + XED_NONTERMINAL_ISA, + XED_NONTERMINAL_MASK1, + XED_NONTERMINAL_MASKNOT0, + XED_NONTERMINAL_MASK_B, + XED_NONTERMINAL_MASK_N, + XED_NONTERMINAL_MASK_N32, + XED_NONTERMINAL_MASK_N64, + XED_NONTERMINAL_MASK_R, + XED_NONTERMINAL_MEMDISP, + XED_NONTERMINAL_MEMDISP16, + XED_NONTERMINAL_MEMDISP32, + XED_NONTERMINAL_MEMDISP8, + XED_NONTERMINAL_MEMDISPV, + XED_NONTERMINAL_MMX_B, + XED_NONTERMINAL_MMX_R, + XED_NONTERMINAL_MODRM, + XED_NONTERMINAL_MODRM16, + XED_NONTERMINAL_MODRM32, + XED_NONTERMINAL_MODRM64ALT32, + XED_NONTERMINAL_NELEM_EIGHTHMEM, + XED_NONTERMINAL_NELEM_FULL, + XED_NONTERMINAL_NELEM_FULLMEM, + XED_NONTERMINAL_NELEM_GPR_READER, + XED_NONTERMINAL_NELEM_GPR_READER_BYTE, + XED_NONTERMINAL_NELEM_GPR_READER_SUBDWORD, + XED_NONTERMINAL_NELEM_GPR_READER_WORD, + XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP, + XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_D, + XED_NONTERMINAL_NELEM_GPR_WRITER_LDOP_Q, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_BYTE, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_SUBDWORD, + XED_NONTERMINAL_NELEM_GPR_WRITER_STORE_WORD, + XED_NONTERMINAL_NELEM_GSCAT, + XED_NONTERMINAL_NELEM_HALF, + XED_NONTERMINAL_NELEM_HALFMEM, + XED_NONTERMINAL_NELEM_MEM128, + XED_NONTERMINAL_NELEM_MOVDDUP, + XED_NONTERMINAL_NELEM_QUARTER, + XED_NONTERMINAL_NELEM_QUARTERMEM, + XED_NONTERMINAL_NELEM_SCALAR, + XED_NONTERMINAL_NELEM_TUPLE1, + XED_NONTERMINAL_NELEM_TUPLE1_4X, + XED_NONTERMINAL_NELEM_TUPLE1_BYTE, + XED_NONTERMINAL_NELEM_TUPLE1_SUBDWORD, + XED_NONTERMINAL_NELEM_TUPLE1_WORD, + XED_NONTERMINAL_NELEM_TUPLE2, + XED_NONTERMINAL_NELEM_TUPLE4, + XED_NONTERMINAL_NELEM_TUPLE8, + XED_NONTERMINAL_OEAX, + XED_NONTERMINAL_ONE, + XED_NONTERMINAL_ORAX, + XED_NONTERMINAL_ORBP, + XED_NONTERMINAL_ORBX, + XED_NONTERMINAL_ORCX, + XED_NONTERMINAL_ORDX, + XED_NONTERMINAL_ORSP, + XED_NONTERMINAL_OSZ_NONTERM, + XED_NONTERMINAL_OVERRIDE_SEG0, + XED_NONTERMINAL_OVERRIDE_SEG1, + XED_NONTERMINAL_PREFIXES, + XED_NONTERMINAL_REFINING66, + XED_NONTERMINAL_REMOVE_SEGMENT, + XED_NONTERMINAL_RFLAGS, + XED_NONTERMINAL_RIP, + XED_NONTERMINAL_RIPA, + XED_NONTERMINAL_SAE, + XED_NONTERMINAL_SEG, + XED_NONTERMINAL_SEG_MOV, + XED_NONTERMINAL_SE_IMM8, + XED_NONTERMINAL_SIB, + XED_NONTERMINAL_SIB_BASE0, + XED_NONTERMINAL_SIMM8, + XED_NONTERMINAL_SIMMZ, + XED_NONTERMINAL_SRBP, + XED_NONTERMINAL_SRSP, + XED_NONTERMINAL_TMM_B, + XED_NONTERMINAL_TMM_N, + XED_NONTERMINAL_TMM_R, + XED_NONTERMINAL_UIMM16, + XED_NONTERMINAL_UIMM32, + XED_NONTERMINAL_UIMM8, + XED_NONTERMINAL_UIMM8_1, + XED_NONTERMINAL_UIMMV, + XED_NONTERMINAL_UISA_VMODRM_XMM, + XED_NONTERMINAL_UISA_VMODRM_YMM, + XED_NONTERMINAL_UISA_VMODRM_ZMM, + XED_NONTERMINAL_UISA_VSIB_BASE, + XED_NONTERMINAL_UISA_VSIB_INDEX_XMM, + XED_NONTERMINAL_UISA_VSIB_INDEX_YMM, + XED_NONTERMINAL_UISA_VSIB_INDEX_ZMM, + XED_NONTERMINAL_UISA_VSIB_XMM, + XED_NONTERMINAL_UISA_VSIB_YMM, + XED_NONTERMINAL_UISA_VSIB_ZMM, + XED_NONTERMINAL_VGPR32_B, + XED_NONTERMINAL_VGPR32_B_32, + XED_NONTERMINAL_VGPR32_B_64, + XED_NONTERMINAL_VGPR32_N, + XED_NONTERMINAL_VGPR32_N_32, + XED_NONTERMINAL_VGPR32_N_64, + XED_NONTERMINAL_VGPR32_R, + XED_NONTERMINAL_VGPR32_R_32, + XED_NONTERMINAL_VGPR32_R_64, + XED_NONTERMINAL_VGPR64_B, + XED_NONTERMINAL_VGPR64_N, + XED_NONTERMINAL_VGPR64_R, + XED_NONTERMINAL_VGPRY_B, + XED_NONTERMINAL_VGPRY_N, + XED_NONTERMINAL_VGPRY_R, + XED_NONTERMINAL_VMODRM_XMM, + XED_NONTERMINAL_VMODRM_YMM, + XED_NONTERMINAL_VSIB_BASE, + XED_NONTERMINAL_VSIB_INDEX_XMM, + XED_NONTERMINAL_VSIB_INDEX_YMM, + XED_NONTERMINAL_VSIB_XMM, + XED_NONTERMINAL_VSIB_YMM, + XED_NONTERMINAL_X87, + XED_NONTERMINAL_XMM_B, + XED_NONTERMINAL_XMM_B3, + XED_NONTERMINAL_XMM_B3_32, + XED_NONTERMINAL_XMM_B3_64, + XED_NONTERMINAL_XMM_B_32, + XED_NONTERMINAL_XMM_B_64, + XED_NONTERMINAL_XMM_N, + XED_NONTERMINAL_XMM_N3, + XED_NONTERMINAL_XMM_N3_32, + XED_NONTERMINAL_XMM_N3_64, + XED_NONTERMINAL_XMM_N_32, + XED_NONTERMINAL_XMM_N_64, + XED_NONTERMINAL_XMM_R, + XED_NONTERMINAL_XMM_R3, + XED_NONTERMINAL_XMM_R3_32, + XED_NONTERMINAL_XMM_R3_64, + XED_NONTERMINAL_XMM_R_32, + XED_NONTERMINAL_XMM_R_64, + XED_NONTERMINAL_XMM_SE, + XED_NONTERMINAL_XMM_SE32, + XED_NONTERMINAL_XMM_SE64, + XED_NONTERMINAL_XOP_INSTRUCTIONS, + XED_NONTERMINAL_YMM_B, + XED_NONTERMINAL_YMM_B3, + XED_NONTERMINAL_YMM_B3_32, + XED_NONTERMINAL_YMM_B3_64, + XED_NONTERMINAL_YMM_B_32, + XED_NONTERMINAL_YMM_B_64, + XED_NONTERMINAL_YMM_N, + XED_NONTERMINAL_YMM_N3, + XED_NONTERMINAL_YMM_N3_32, + XED_NONTERMINAL_YMM_N3_64, + XED_NONTERMINAL_YMM_N_32, + XED_NONTERMINAL_YMM_N_64, + XED_NONTERMINAL_YMM_R, + XED_NONTERMINAL_YMM_R3, + XED_NONTERMINAL_YMM_R3_32, + XED_NONTERMINAL_YMM_R3_64, + XED_NONTERMINAL_YMM_R_32, + XED_NONTERMINAL_YMM_R_64, + XED_NONTERMINAL_YMM_SE, + XED_NONTERMINAL_YMM_SE32, + XED_NONTERMINAL_YMM_SE64, + XED_NONTERMINAL_ZMM_B3, + XED_NONTERMINAL_ZMM_B3_32, + XED_NONTERMINAL_ZMM_B3_64, + XED_NONTERMINAL_ZMM_N3, + XED_NONTERMINAL_ZMM_N3_32, + XED_NONTERMINAL_ZMM_N3_64, + XED_NONTERMINAL_ZMM_R3, + XED_NONTERMINAL_ZMM_R3_32, + XED_NONTERMINAL_ZMM_R3_64, + XED_NONTERMINAL_LAST +} xed_nonterminal_enum_t; + +/// This converts strings to #xed_nonterminal_enum_t types. +/// @param s A C-string. +/// @return #xed_nonterminal_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_nonterminal_enum_t str2xed_nonterminal_enum_t(const char* s); +/// This converts strings to #xed_nonterminal_enum_t types. +/// @param p An enumeration element of type xed_nonterminal_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_nonterminal_enum_t2str(const xed_nonterminal_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_nonterminal_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_nonterminal_enum_t xed_nonterminal_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-nonterminal-enum.txt b/CodeVirtualizer/build/obj/xed-nonterminal-enum.txt new file mode 100644 index 0000000..f09ed48 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-nonterminal-enum.txt @@ -0,0 +1,288 @@ +# @file xed-nonterminal-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-nonterminal-enum.c +hfn xed-nonterminal-enum.h +typename xed_nonterminal_enum_t +prefix XED_NONTERMINAL_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +AR10 +AR11 +AR12 +AR13 +AR14 +AR15 +AR8 +AR9 +ARAX +ARBP +ARBX +ARCX +ARDI +ARDX +ARSI +ARSP +ASZ_NONTERM +AVX512_ROUND +AVX_INSTRUCTIONS +AVX_SPLITTER +A_GPR_B +A_GPR_R +BND_B +BND_B_CHECK +BND_R +BND_R_CHECK +BRANCH_HINT +BRDISP32 +BRDISP8 +BRDISPZ +CET_NO_TRACK +CR_B +CR_R +CR_WIDTH +DF64 +DR_R +ESIZE_128_BITS +ESIZE_16_BITS +ESIZE_1_BITS +ESIZE_2_BITS +ESIZE_32_BITS +ESIZE_4_BITS +ESIZE_64_BITS +ESIZE_8_BITS +EVEX_INSTRUCTIONS +EVEX_SPLITTER +FINAL_DSEG +FINAL_DSEG1 +FINAL_DSEG1_MODE64 +FINAL_DSEG1_NOT64 +FINAL_DSEG_MODE64 +FINAL_DSEG_NOT64 +FINAL_ESEG +FINAL_ESEG1 +FINAL_SSEG +FINAL_SSEG0 +FINAL_SSEG1 +FINAL_SSEG_MODE64 +FINAL_SSEG_NOT64 +FIX_ROUND_LEN128 +FIX_ROUND_LEN512 +FORCE64 +GPR16_B +GPR16_R +GPR16_SB +GPR32_B +GPR32_R +GPR32_SB +GPR32_X +GPR64_B +GPR64_R +GPR64_SB +GPR64_X +GPR8_B +GPR8_R +GPR8_SB +GPRV_B +GPRV_R +GPRV_SB +GPRY_B +GPRY_R +GPRZ_B +GPRZ_R +IGNORE66 +IMMUNE66 +IMMUNE66_LOOP64 +IMMUNE_REXW +INSTRUCTIONS +ISA +MASK1 +MASKNOT0 +MASK_B +MASK_N +MASK_N32 +MASK_N64 +MASK_R +MEMDISP +MEMDISP16 +MEMDISP32 +MEMDISP8 +MEMDISPV +MMX_B +MMX_R +MODRM +MODRM16 +MODRM32 +MODRM64ALT32 +NELEM_EIGHTHMEM +NELEM_FULL +NELEM_FULLMEM +NELEM_GPR_READER +NELEM_GPR_READER_BYTE +NELEM_GPR_READER_SUBDWORD +NELEM_GPR_READER_WORD +NELEM_GPR_WRITER_LDOP +NELEM_GPR_WRITER_LDOP_D +NELEM_GPR_WRITER_LDOP_Q +NELEM_GPR_WRITER_STORE +NELEM_GPR_WRITER_STORE_BYTE +NELEM_GPR_WRITER_STORE_SUBDWORD +NELEM_GPR_WRITER_STORE_WORD +NELEM_GSCAT +NELEM_HALF +NELEM_HALFMEM +NELEM_MEM128 +NELEM_MOVDDUP +NELEM_QUARTER +NELEM_QUARTERMEM +NELEM_SCALAR +NELEM_TUPLE1 +NELEM_TUPLE1_4X +NELEM_TUPLE1_BYTE +NELEM_TUPLE1_SUBDWORD +NELEM_TUPLE1_WORD +NELEM_TUPLE2 +NELEM_TUPLE4 +NELEM_TUPLE8 +OEAX +ONE +ORAX +ORBP +ORBX +ORCX +ORDX +ORSP +OSZ_NONTERM +OVERRIDE_SEG0 +OVERRIDE_SEG1 +PREFIXES +REFINING66 +REMOVE_SEGMENT +RFLAGS +RIP +RIPA +SAE +SEG +SEG_MOV +SE_IMM8 +SIB +SIB_BASE0 +SIMM8 +SIMMZ +SRBP +SRSP +TMM_B +TMM_N +TMM_R +UIMM16 +UIMM32 +UIMM8 +UIMM8_1 +UIMMV +UISA_VMODRM_XMM +UISA_VMODRM_YMM +UISA_VMODRM_ZMM +UISA_VSIB_BASE +UISA_VSIB_INDEX_XMM +UISA_VSIB_INDEX_YMM +UISA_VSIB_INDEX_ZMM +UISA_VSIB_XMM +UISA_VSIB_YMM +UISA_VSIB_ZMM +VGPR32_B +VGPR32_B_32 +VGPR32_B_64 +VGPR32_N +VGPR32_N_32 +VGPR32_N_64 +VGPR32_R +VGPR32_R_32 +VGPR32_R_64 +VGPR64_B +VGPR64_N +VGPR64_R +VGPRY_B +VGPRY_N +VGPRY_R +VMODRM_XMM +VMODRM_YMM +VSIB_BASE +VSIB_INDEX_XMM +VSIB_INDEX_YMM +VSIB_XMM +VSIB_YMM +X87 +XMM_B +XMM_B3 +XMM_B3_32 +XMM_B3_64 +XMM_B_32 +XMM_B_64 +XMM_N +XMM_N3 +XMM_N3_32 +XMM_N3_64 +XMM_N_32 +XMM_N_64 +XMM_R +XMM_R3 +XMM_R3_32 +XMM_R3_64 +XMM_R_32 +XMM_R_64 +XMM_SE +XMM_SE32 +XMM_SE64 +XOP_INSTRUCTIONS +YMM_B +YMM_B3 +YMM_B3_32 +YMM_B3_64 +YMM_B_32 +YMM_B_64 +YMM_N +YMM_N3 +YMM_N3_32 +YMM_N3_64 +YMM_N_32 +YMM_N_64 +YMM_R +YMM_R3 +YMM_R3_32 +YMM_R3_64 +YMM_R_32 +YMM_R_64 +YMM_SE +YMM_SE32 +YMM_SE64 +ZMM_B3 +ZMM_B3_32 +ZMM_B3_64 +ZMM_N3 +ZMM_N3_32 +ZMM_N3_64 +ZMM_R3 +ZMM_R3_32 +ZMM_R3_64 diff --git a/CodeVirtualizer/build/obj/xed-operand-accessors.c b/CodeVirtualizer/build/obj/xed-operand-accessors.c new file mode 100644 index 0000000..dab258e --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-accessors.c @@ -0,0 +1,778 @@ +/// @file xed-operand-accessors.c + +// This file was automatically generated. +// Do not edit this file. + +#include "xed-operand-accessors.h" +XED_DLL_EXPORT void xed3_get_generic_operand(const xed_decoded_inst_t* d, xed_operand_enum_t operand, void* ret_arg) +{ + switch(operand) { + case XED_OPERAND_AGEN: + *((xed_bits_t*)ret_arg)=xed3_operand_get_agen(d); + break; + case XED_OPERAND_AMD3DNOW: + *((xed_bits_t*)ret_arg)=xed3_operand_get_amd3dnow(d); + break; + case XED_OPERAND_ASZ: + *((xed_bits_t*)ret_arg)=xed3_operand_get_asz(d); + break; + case XED_OPERAND_BASE0: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_base0(d); + break; + case XED_OPERAND_BASE1: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_base1(d); + break; + case XED_OPERAND_BCAST: + *((xed_bits_t*)ret_arg)=xed3_operand_get_bcast(d); + break; + case XED_OPERAND_BCRC: + *((xed_bits_t*)ret_arg)=xed3_operand_get_bcrc(d); + break; + case XED_OPERAND_BRDISP_WIDTH: + *((xed_uint8_t*)ret_arg)=xed3_operand_get_brdisp_width(d); + break; + case XED_OPERAND_CET: + *((xed_bits_t*)ret_arg)=xed3_operand_get_cet(d); + break; + case XED_OPERAND_CHIP: + *((xed_chip_enum_t*)ret_arg)=xed3_operand_get_chip(d); + break; + case XED_OPERAND_CLDEMOTE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_cldemote(d); + break; + case XED_OPERAND_DEFAULT_SEG: + *((xed_bits_t*)ret_arg)=xed3_operand_get_default_seg(d); + break; + case XED_OPERAND_DF32: + *((xed_bits_t*)ret_arg)=xed3_operand_get_df32(d); + break; + case XED_OPERAND_DF64: + *((xed_bits_t*)ret_arg)=xed3_operand_get_df64(d); + break; + case XED_OPERAND_DISP: + *((xed_int64_t*)ret_arg)=xed3_operand_get_disp(d); + break; + case XED_OPERAND_DISP_WIDTH: + *((xed_uint8_t*)ret_arg)=xed3_operand_get_disp_width(d); + break; + case XED_OPERAND_DUMMY: + *((xed_bits_t*)ret_arg)=xed3_operand_get_dummy(d); + break; + case XED_OPERAND_EASZ: + *((xed_bits_t*)ret_arg)=xed3_operand_get_easz(d); + break; + case XED_OPERAND_ELEMENT_SIZE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_element_size(d); + break; + case XED_OPERAND_ENCODER_PREFERRED: + *((xed_bits_t*)ret_arg)=xed3_operand_get_encoder_preferred(d); + break; + case XED_OPERAND_ENCODE_FORCE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_encode_force(d); + break; + case XED_OPERAND_EOSZ: + *((xed_bits_t*)ret_arg)=xed3_operand_get_eosz(d); + break; + case XED_OPERAND_ERROR: + *((xed_error_enum_t*)ret_arg)=xed3_operand_get_error(d); + break; + case XED_OPERAND_ESRC: + *((xed_bits_t*)ret_arg)=xed3_operand_get_esrc(d); + break; + case XED_OPERAND_FIRST_F2F3: + *((xed_bits_t*)ret_arg)=xed3_operand_get_first_f2f3(d); + break; + case XED_OPERAND_HAS_MODRM: + *((xed_bits_t*)ret_arg)=xed3_operand_get_has_modrm(d); + break; + case XED_OPERAND_HAS_SIB: + *((xed_bits_t*)ret_arg)=xed3_operand_get_has_sib(d); + break; + case XED_OPERAND_HINT: + *((xed_bits_t*)ret_arg)=xed3_operand_get_hint(d); + break; + case XED_OPERAND_ICLASS: + *((xed_iclass_enum_t*)ret_arg)=xed3_operand_get_iclass(d); + break; + case XED_OPERAND_ILD_F2: + *((xed_bits_t*)ret_arg)=xed3_operand_get_ild_f2(d); + break; + case XED_OPERAND_ILD_F3: + *((xed_bits_t*)ret_arg)=xed3_operand_get_ild_f3(d); + break; + case XED_OPERAND_ILD_SEG: + *((xed_bits_t*)ret_arg)=xed3_operand_get_ild_seg(d); + break; + case XED_OPERAND_IMM0: + *((xed_bits_t*)ret_arg)=xed3_operand_get_imm0(d); + break; + case XED_OPERAND_IMM0SIGNED: + *((xed_bits_t*)ret_arg)=xed3_operand_get_imm0signed(d); + break; + case XED_OPERAND_IMM1: + *((xed_bits_t*)ret_arg)=xed3_operand_get_imm1(d); + break; + case XED_OPERAND_IMM1_BYTES: + *((xed_bits_t*)ret_arg)=xed3_operand_get_imm1_bytes(d); + break; + case XED_OPERAND_IMM_WIDTH: + *((xed_uint8_t*)ret_arg)=xed3_operand_get_imm_width(d); + break; + case XED_OPERAND_INDEX: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_index(d); + break; + case XED_OPERAND_LAST_F2F3: + *((xed_bits_t*)ret_arg)=xed3_operand_get_last_f2f3(d); + break; + case XED_OPERAND_LLRC: + *((xed_bits_t*)ret_arg)=xed3_operand_get_llrc(d); + break; + case XED_OPERAND_LOCK: + *((xed_bits_t*)ret_arg)=xed3_operand_get_lock(d); + break; + case XED_OPERAND_LZCNT: + *((xed_bits_t*)ret_arg)=xed3_operand_get_lzcnt(d); + break; + case XED_OPERAND_MAP: + *((xed_bits_t*)ret_arg)=xed3_operand_get_map(d); + break; + case XED_OPERAND_MASK: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mask(d); + break; + case XED_OPERAND_MAX_BYTES: + *((xed_bits_t*)ret_arg)=xed3_operand_get_max_bytes(d); + break; + case XED_OPERAND_MEM0: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mem0(d); + break; + case XED_OPERAND_MEM1: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mem1(d); + break; + case XED_OPERAND_MEM_WIDTH: + *((xed_uint16_t*)ret_arg)=xed3_operand_get_mem_width(d); + break; + case XED_OPERAND_MOD: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mod(d); + break; + case XED_OPERAND_MODE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mode(d); + break; + case XED_OPERAND_MODEP5: + *((xed_bits_t*)ret_arg)=xed3_operand_get_modep5(d); + break; + case XED_OPERAND_MODEP55C: + *((xed_bits_t*)ret_arg)=xed3_operand_get_modep55c(d); + break; + case XED_OPERAND_MODE_FIRST_PREFIX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mode_first_prefix(d); + break; + case XED_OPERAND_MODE_SHORT_UD0: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mode_short_ud0(d); + break; + case XED_OPERAND_MODRM_BYTE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_modrm_byte(d); + break; + case XED_OPERAND_MPXMODE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_mpxmode(d); + break; + case XED_OPERAND_MUST_USE_EVEX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_must_use_evex(d); + break; + case XED_OPERAND_NEEDREX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_needrex(d); + break; + case XED_OPERAND_NEED_MEMDISP: + *((xed_bits_t*)ret_arg)=xed3_operand_get_need_memdisp(d); + break; + case XED_OPERAND_NEED_SIB: + *((xed_bits_t*)ret_arg)=xed3_operand_get_need_sib(d); + break; + case XED_OPERAND_NELEM: + *((xed_bits_t*)ret_arg)=xed3_operand_get_nelem(d); + break; + case XED_OPERAND_NOMINAL_OPCODE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_nominal_opcode(d); + break; + case XED_OPERAND_NOREX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_norex(d); + break; + case XED_OPERAND_NO_SCALE_DISP8: + *((xed_bits_t*)ret_arg)=xed3_operand_get_no_scale_disp8(d); + break; + case XED_OPERAND_NPREFIXES: + *((xed_bits_t*)ret_arg)=xed3_operand_get_nprefixes(d); + break; + case XED_OPERAND_NREXES: + *((xed_bits_t*)ret_arg)=xed3_operand_get_nrexes(d); + break; + case XED_OPERAND_NSEG_PREFIXES: + *((xed_bits_t*)ret_arg)=xed3_operand_get_nseg_prefixes(d); + break; + case XED_OPERAND_OSZ: + *((xed_bits_t*)ret_arg)=xed3_operand_get_osz(d); + break; + case XED_OPERAND_OUTREG: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_outreg(d); + break; + case XED_OPERAND_OUT_OF_BYTES: + *((xed_bits_t*)ret_arg)=xed3_operand_get_out_of_bytes(d); + break; + case XED_OPERAND_P4: + *((xed_bits_t*)ret_arg)=xed3_operand_get_p4(d); + break; + case XED_OPERAND_POS_DISP: + *((xed_bits_t*)ret_arg)=xed3_operand_get_pos_disp(d); + break; + case XED_OPERAND_POS_IMM: + *((xed_bits_t*)ret_arg)=xed3_operand_get_pos_imm(d); + break; + case XED_OPERAND_POS_IMM1: + *((xed_bits_t*)ret_arg)=xed3_operand_get_pos_imm1(d); + break; + case XED_OPERAND_POS_MODRM: + *((xed_bits_t*)ret_arg)=xed3_operand_get_pos_modrm(d); + break; + case XED_OPERAND_POS_NOMINAL_OPCODE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_pos_nominal_opcode(d); + break; + case XED_OPERAND_POS_SIB: + *((xed_bits_t*)ret_arg)=xed3_operand_get_pos_sib(d); + break; + case XED_OPERAND_PREFIX66: + *((xed_bits_t*)ret_arg)=xed3_operand_get_prefix66(d); + break; + case XED_OPERAND_PTR: + *((xed_bits_t*)ret_arg)=xed3_operand_get_ptr(d); + break; + case XED_OPERAND_REALMODE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_realmode(d); + break; + case XED_OPERAND_REG: + *((xed_bits_t*)ret_arg)=xed3_operand_get_reg(d); + break; + case XED_OPERAND_REG0: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg0(d); + break; + case XED_OPERAND_REG1: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg1(d); + break; + case XED_OPERAND_REG2: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg2(d); + break; + case XED_OPERAND_REG3: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg3(d); + break; + case XED_OPERAND_REG4: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg4(d); + break; + case XED_OPERAND_REG5: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg5(d); + break; + case XED_OPERAND_REG6: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg6(d); + break; + case XED_OPERAND_REG7: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg7(d); + break; + case XED_OPERAND_REG8: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg8(d); + break; + case XED_OPERAND_REG9: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_reg9(d); + break; + case XED_OPERAND_RELBR: + *((xed_bits_t*)ret_arg)=xed3_operand_get_relbr(d); + break; + case XED_OPERAND_REP: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rep(d); + break; + case XED_OPERAND_REX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rex(d); + break; + case XED_OPERAND_REXB: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rexb(d); + break; + case XED_OPERAND_REXR: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rexr(d); + break; + case XED_OPERAND_REXRR: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rexrr(d); + break; + case XED_OPERAND_REXW: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rexw(d); + break; + case XED_OPERAND_REXX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rexx(d); + break; + case XED_OPERAND_RM: + *((xed_bits_t*)ret_arg)=xed3_operand_get_rm(d); + break; + case XED_OPERAND_ROUNDC: + *((xed_bits_t*)ret_arg)=xed3_operand_get_roundc(d); + break; + case XED_OPERAND_SAE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_sae(d); + break; + case XED_OPERAND_SCALE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_scale(d); + break; + case XED_OPERAND_SEG0: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_seg0(d); + break; + case XED_OPERAND_SEG1: + *((xed_reg_enum_t*)ret_arg)=xed3_operand_get_seg1(d); + break; + case XED_OPERAND_SEG_OVD: + *((xed_bits_t*)ret_arg)=xed3_operand_get_seg_ovd(d); + break; + case XED_OPERAND_SIBBASE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_sibbase(d); + break; + case XED_OPERAND_SIBINDEX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_sibindex(d); + break; + case XED_OPERAND_SIBSCALE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_sibscale(d); + break; + case XED_OPERAND_SMODE: + *((xed_bits_t*)ret_arg)=xed3_operand_get_smode(d); + break; + case XED_OPERAND_SRM: + *((xed_bits_t*)ret_arg)=xed3_operand_get_srm(d); + break; + case XED_OPERAND_TZCNT: + *((xed_bits_t*)ret_arg)=xed3_operand_get_tzcnt(d); + break; + case XED_OPERAND_UBIT: + *((xed_bits_t*)ret_arg)=xed3_operand_get_ubit(d); + break; + case XED_OPERAND_UIMM0: + *((xed_uint64_t*)ret_arg)=xed3_operand_get_uimm0(d); + break; + case XED_OPERAND_UIMM1: + *((xed_uint8_t*)ret_arg)=xed3_operand_get_uimm1(d); + break; + case XED_OPERAND_USING_DEFAULT_SEGMENT0: + *((xed_bits_t*)ret_arg)=xed3_operand_get_using_default_segment0(d); + break; + case XED_OPERAND_USING_DEFAULT_SEGMENT1: + *((xed_bits_t*)ret_arg)=xed3_operand_get_using_default_segment1(d); + break; + case XED_OPERAND_VEXDEST210: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vexdest210(d); + break; + case XED_OPERAND_VEXDEST3: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vexdest3(d); + break; + case XED_OPERAND_VEXDEST4: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vexdest4(d); + break; + case XED_OPERAND_VEXVALID: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vexvalid(d); + break; + case XED_OPERAND_VEX_C4: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vex_c4(d); + break; + case XED_OPERAND_VEX_PREFIX: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vex_prefix(d); + break; + case XED_OPERAND_VL: + *((xed_bits_t*)ret_arg)=xed3_operand_get_vl(d); + break; + case XED_OPERAND_WBNOINVD: + *((xed_bits_t*)ret_arg)=xed3_operand_get_wbnoinvd(d); + break; + case XED_OPERAND_ZEROING: + *((xed_bits_t*)ret_arg)=xed3_operand_get_zeroing(d); + break; + default: + xed_assert(0); + break; + } +} +XED_DLL_EXPORT void xed3_set_generic_operand(xed_decoded_inst_t* d, xed_operand_enum_t operand, xed_uint32_t val) +{ + switch(operand) { + case XED_OPERAND_AGEN: + xed3_operand_set_agen(d,(xed_bits_t)val); + break; + case XED_OPERAND_AMD3DNOW: + xed3_operand_set_amd3dnow(d,(xed_bits_t)val); + break; + case XED_OPERAND_ASZ: + xed3_operand_set_asz(d,(xed_bits_t)val); + break; + case XED_OPERAND_BASE0: + xed3_operand_set_base0(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_BASE1: + xed3_operand_set_base1(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_BCAST: + xed3_operand_set_bcast(d,(xed_bits_t)val); + break; + case XED_OPERAND_BCRC: + xed3_operand_set_bcrc(d,(xed_bits_t)val); + break; + case XED_OPERAND_BRDISP_WIDTH: + xed3_operand_set_brdisp_width(d,(xed_uint8_t)val); + break; + case XED_OPERAND_CET: + xed3_operand_set_cet(d,(xed_bits_t)val); + break; + case XED_OPERAND_CHIP: + xed3_operand_set_chip(d,(xed_chip_enum_t)val); + break; + case XED_OPERAND_CLDEMOTE: + xed3_operand_set_cldemote(d,(xed_bits_t)val); + break; + case XED_OPERAND_DEFAULT_SEG: + xed3_operand_set_default_seg(d,(xed_bits_t)val); + break; + case XED_OPERAND_DF32: + xed3_operand_set_df32(d,(xed_bits_t)val); + break; + case XED_OPERAND_DF64: + xed3_operand_set_df64(d,(xed_bits_t)val); + break; + case XED_OPERAND_DISP: + xed3_operand_set_disp(d,(xed_int64_t)val); + break; + case XED_OPERAND_DISP_WIDTH: + xed3_operand_set_disp_width(d,(xed_uint8_t)val); + break; + case XED_OPERAND_DUMMY: + xed3_operand_set_dummy(d,(xed_bits_t)val); + break; + case XED_OPERAND_EASZ: + xed3_operand_set_easz(d,(xed_bits_t)val); + break; + case XED_OPERAND_ELEMENT_SIZE: + xed3_operand_set_element_size(d,(xed_bits_t)val); + break; + case XED_OPERAND_ENCODER_PREFERRED: + xed3_operand_set_encoder_preferred(d,(xed_bits_t)val); + break; + case XED_OPERAND_ENCODE_FORCE: + xed3_operand_set_encode_force(d,(xed_bits_t)val); + break; + case XED_OPERAND_EOSZ: + xed3_operand_set_eosz(d,(xed_bits_t)val); + break; + case XED_OPERAND_ERROR: + xed3_operand_set_error(d,(xed_error_enum_t)val); + break; + case XED_OPERAND_ESRC: + xed3_operand_set_esrc(d,(xed_bits_t)val); + break; + case XED_OPERAND_FIRST_F2F3: + xed3_operand_set_first_f2f3(d,(xed_bits_t)val); + break; + case XED_OPERAND_HAS_MODRM: + xed3_operand_set_has_modrm(d,(xed_bits_t)val); + break; + case XED_OPERAND_HAS_SIB: + xed3_operand_set_has_sib(d,(xed_bits_t)val); + break; + case XED_OPERAND_HINT: + xed3_operand_set_hint(d,(xed_bits_t)val); + break; + case XED_OPERAND_ICLASS: + xed3_operand_set_iclass(d,(xed_iclass_enum_t)val); + break; + case XED_OPERAND_ILD_F2: + xed3_operand_set_ild_f2(d,(xed_bits_t)val); + break; + case XED_OPERAND_ILD_F3: + xed3_operand_set_ild_f3(d,(xed_bits_t)val); + break; + case XED_OPERAND_ILD_SEG: + xed3_operand_set_ild_seg(d,(xed_bits_t)val); + break; + case XED_OPERAND_IMM0: + xed3_operand_set_imm0(d,(xed_bits_t)val); + break; + case XED_OPERAND_IMM0SIGNED: + xed3_operand_set_imm0signed(d,(xed_bits_t)val); + break; + case XED_OPERAND_IMM1: + xed3_operand_set_imm1(d,(xed_bits_t)val); + break; + case XED_OPERAND_IMM1_BYTES: + xed3_operand_set_imm1_bytes(d,(xed_bits_t)val); + break; + case XED_OPERAND_IMM_WIDTH: + xed3_operand_set_imm_width(d,(xed_uint8_t)val); + break; + case XED_OPERAND_INDEX: + xed3_operand_set_index(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_LAST_F2F3: + xed3_operand_set_last_f2f3(d,(xed_bits_t)val); + break; + case XED_OPERAND_LLRC: + xed3_operand_set_llrc(d,(xed_bits_t)val); + break; + case XED_OPERAND_LOCK: + xed3_operand_set_lock(d,(xed_bits_t)val); + break; + case XED_OPERAND_LZCNT: + xed3_operand_set_lzcnt(d,(xed_bits_t)val); + break; + case XED_OPERAND_MAP: + xed3_operand_set_map(d,(xed_bits_t)val); + break; + case XED_OPERAND_MASK: + xed3_operand_set_mask(d,(xed_bits_t)val); + break; + case XED_OPERAND_MAX_BYTES: + xed3_operand_set_max_bytes(d,(xed_bits_t)val); + break; + case XED_OPERAND_MEM0: + xed3_operand_set_mem0(d,(xed_bits_t)val); + break; + case XED_OPERAND_MEM1: + xed3_operand_set_mem1(d,(xed_bits_t)val); + break; + case XED_OPERAND_MEM_WIDTH: + xed3_operand_set_mem_width(d,(xed_uint16_t)val); + break; + case XED_OPERAND_MOD: + xed3_operand_set_mod(d,(xed_bits_t)val); + break; + case XED_OPERAND_MODE: + xed3_operand_set_mode(d,(xed_bits_t)val); + break; + case XED_OPERAND_MODEP5: + xed3_operand_set_modep5(d,(xed_bits_t)val); + break; + case XED_OPERAND_MODEP55C: + xed3_operand_set_modep55c(d,(xed_bits_t)val); + break; + case XED_OPERAND_MODE_FIRST_PREFIX: + xed3_operand_set_mode_first_prefix(d,(xed_bits_t)val); + break; + case XED_OPERAND_MODE_SHORT_UD0: + xed3_operand_set_mode_short_ud0(d,(xed_bits_t)val); + break; + case XED_OPERAND_MODRM_BYTE: + xed3_operand_set_modrm_byte(d,(xed_bits_t)val); + break; + case XED_OPERAND_MPXMODE: + xed3_operand_set_mpxmode(d,(xed_bits_t)val); + break; + case XED_OPERAND_MUST_USE_EVEX: + xed3_operand_set_must_use_evex(d,(xed_bits_t)val); + break; + case XED_OPERAND_NEEDREX: + xed3_operand_set_needrex(d,(xed_bits_t)val); + break; + case XED_OPERAND_NEED_MEMDISP: + xed3_operand_set_need_memdisp(d,(xed_bits_t)val); + break; + case XED_OPERAND_NEED_SIB: + xed3_operand_set_need_sib(d,(xed_bits_t)val); + break; + case XED_OPERAND_NELEM: + xed3_operand_set_nelem(d,(xed_bits_t)val); + break; + case XED_OPERAND_NOMINAL_OPCODE: + xed3_operand_set_nominal_opcode(d,(xed_bits_t)val); + break; + case XED_OPERAND_NOREX: + xed3_operand_set_norex(d,(xed_bits_t)val); + break; + case XED_OPERAND_NO_SCALE_DISP8: + xed3_operand_set_no_scale_disp8(d,(xed_bits_t)val); + break; + case XED_OPERAND_NPREFIXES: + xed3_operand_set_nprefixes(d,(xed_bits_t)val); + break; + case XED_OPERAND_NREXES: + xed3_operand_set_nrexes(d,(xed_bits_t)val); + break; + case XED_OPERAND_NSEG_PREFIXES: + xed3_operand_set_nseg_prefixes(d,(xed_bits_t)val); + break; + case XED_OPERAND_OSZ: + xed3_operand_set_osz(d,(xed_bits_t)val); + break; + case XED_OPERAND_OUTREG: + xed3_operand_set_outreg(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_OUT_OF_BYTES: + xed3_operand_set_out_of_bytes(d,(xed_bits_t)val); + break; + case XED_OPERAND_P4: + xed3_operand_set_p4(d,(xed_bits_t)val); + break; + case XED_OPERAND_POS_DISP: + xed3_operand_set_pos_disp(d,(xed_bits_t)val); + break; + case XED_OPERAND_POS_IMM: + xed3_operand_set_pos_imm(d,(xed_bits_t)val); + break; + case XED_OPERAND_POS_IMM1: + xed3_operand_set_pos_imm1(d,(xed_bits_t)val); + break; + case XED_OPERAND_POS_MODRM: + xed3_operand_set_pos_modrm(d,(xed_bits_t)val); + break; + case XED_OPERAND_POS_NOMINAL_OPCODE: + xed3_operand_set_pos_nominal_opcode(d,(xed_bits_t)val); + break; + case XED_OPERAND_POS_SIB: + xed3_operand_set_pos_sib(d,(xed_bits_t)val); + break; + case XED_OPERAND_PREFIX66: + xed3_operand_set_prefix66(d,(xed_bits_t)val); + break; + case XED_OPERAND_PTR: + xed3_operand_set_ptr(d,(xed_bits_t)val); + break; + case XED_OPERAND_REALMODE: + xed3_operand_set_realmode(d,(xed_bits_t)val); + break; + case XED_OPERAND_REG: + xed3_operand_set_reg(d,(xed_bits_t)val); + break; + case XED_OPERAND_REG0: + xed3_operand_set_reg0(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG1: + xed3_operand_set_reg1(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG2: + xed3_operand_set_reg2(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG3: + xed3_operand_set_reg3(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG4: + xed3_operand_set_reg4(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG5: + xed3_operand_set_reg5(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG6: + xed3_operand_set_reg6(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG7: + xed3_operand_set_reg7(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG8: + xed3_operand_set_reg8(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_REG9: + xed3_operand_set_reg9(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_RELBR: + xed3_operand_set_relbr(d,(xed_bits_t)val); + break; + case XED_OPERAND_REP: + xed3_operand_set_rep(d,(xed_bits_t)val); + break; + case XED_OPERAND_REX: + xed3_operand_set_rex(d,(xed_bits_t)val); + break; + case XED_OPERAND_REXB: + xed3_operand_set_rexb(d,(xed_bits_t)val); + break; + case XED_OPERAND_REXR: + xed3_operand_set_rexr(d,(xed_bits_t)val); + break; + case XED_OPERAND_REXRR: + xed3_operand_set_rexrr(d,(xed_bits_t)val); + break; + case XED_OPERAND_REXW: + xed3_operand_set_rexw(d,(xed_bits_t)val); + break; + case XED_OPERAND_REXX: + xed3_operand_set_rexx(d,(xed_bits_t)val); + break; + case XED_OPERAND_RM: + xed3_operand_set_rm(d,(xed_bits_t)val); + break; + case XED_OPERAND_ROUNDC: + xed3_operand_set_roundc(d,(xed_bits_t)val); + break; + case XED_OPERAND_SAE: + xed3_operand_set_sae(d,(xed_bits_t)val); + break; + case XED_OPERAND_SCALE: + xed3_operand_set_scale(d,(xed_bits_t)val); + break; + case XED_OPERAND_SEG0: + xed3_operand_set_seg0(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_SEG1: + xed3_operand_set_seg1(d,(xed_reg_enum_t)val); + break; + case XED_OPERAND_SEG_OVD: + xed3_operand_set_seg_ovd(d,(xed_bits_t)val); + break; + case XED_OPERAND_SIBBASE: + xed3_operand_set_sibbase(d,(xed_bits_t)val); + break; + case XED_OPERAND_SIBINDEX: + xed3_operand_set_sibindex(d,(xed_bits_t)val); + break; + case XED_OPERAND_SIBSCALE: + xed3_operand_set_sibscale(d,(xed_bits_t)val); + break; + case XED_OPERAND_SMODE: + xed3_operand_set_smode(d,(xed_bits_t)val); + break; + case XED_OPERAND_SRM: + xed3_operand_set_srm(d,(xed_bits_t)val); + break; + case XED_OPERAND_TZCNT: + xed3_operand_set_tzcnt(d,(xed_bits_t)val); + break; + case XED_OPERAND_UBIT: + xed3_operand_set_ubit(d,(xed_bits_t)val); + break; + case XED_OPERAND_UIMM0: + xed3_operand_set_uimm0(d,(xed_uint64_t)val); + break; + case XED_OPERAND_UIMM1: + xed3_operand_set_uimm1(d,(xed_uint8_t)val); + break; + case XED_OPERAND_USING_DEFAULT_SEGMENT0: + xed3_operand_set_using_default_segment0(d,(xed_bits_t)val); + break; + case XED_OPERAND_USING_DEFAULT_SEGMENT1: + xed3_operand_set_using_default_segment1(d,(xed_bits_t)val); + break; + case XED_OPERAND_VEXDEST210: + xed3_operand_set_vexdest210(d,(xed_bits_t)val); + break; + case XED_OPERAND_VEXDEST3: + xed3_operand_set_vexdest3(d,(xed_bits_t)val); + break; + case XED_OPERAND_VEXDEST4: + xed3_operand_set_vexdest4(d,(xed_bits_t)val); + break; + case XED_OPERAND_VEXVALID: + xed3_operand_set_vexvalid(d,(xed_bits_t)val); + break; + case XED_OPERAND_VEX_C4: + xed3_operand_set_vex_c4(d,(xed_bits_t)val); + break; + case XED_OPERAND_VEX_PREFIX: + xed3_operand_set_vex_prefix(d,(xed_bits_t)val); + break; + case XED_OPERAND_VL: + xed3_operand_set_vl(d,(xed_bits_t)val); + break; + case XED_OPERAND_WBNOINVD: + xed3_operand_set_wbnoinvd(d,(xed_bits_t)val); + break; + case XED_OPERAND_ZEROING: + xed3_operand_set_zeroing(d,(xed_bits_t)val); + break; + default: + xed_assert(0); + break; + } +} diff --git a/CodeVirtualizer/build/obj/xed-operand-accessors.h b/CodeVirtualizer/build/obj/xed-operand-accessors.h new file mode 100644 index 0000000..003a3c6 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-accessors.h @@ -0,0 +1,1543 @@ +/// @file xed-operand-accessors.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ACCESSORS_H) +# define XED_OPERAND_ACCESSORS_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-decoded-inst.h" +#include "xed-operand-storage.h" +static XED_INLINE xed_bits_t xed3_operand_get_seg_ovd(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_seg_ovd(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_hint(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_hint(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_encode_force(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_encode_force(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_lock(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_lock(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_need_memdisp(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_need_memdisp(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_int64_t xed3_operand_get_disp(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_disp(xed_decoded_inst_t* d, xed_int64_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_disp_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_disp_width(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_brdisp_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_brdisp_width(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_df32(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_df32(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_df64(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_df64(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_norex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_norex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_needrex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_needrex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexw(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexw(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexx(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexx(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexb(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexb(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rep(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rep(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_osz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_osz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_prefix66(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_prefix66(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_asz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_asz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_eosz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_eosz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_easz(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_easz(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mod(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mod(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_reg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_srm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_srm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_realmode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_realmode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_chip_enum_t xed3_operand_get_chip(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_chip(xed_decoded_inst_t* d, xed_chip_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_smode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_smode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_modep5(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_modep5(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_modep55c(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_modep55c(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_p4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_p4(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_lzcnt(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_lzcnt(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_tzcnt(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_tzcnt(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mode_first_prefix(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mode_first_prefix(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mode_short_ud0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mode_short_ud0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm0signed(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm0signed(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_uint64_t xed3_operand_get_uimm0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_uimm0(xed_decoded_inst_t* d, xed_uint64_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_uimm1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_uimm1(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_uint8_t xed3_operand_get_imm_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm_width(xed_decoded_inst_t* d, xed_uint8_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_using_default_segment0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_using_default_segment1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_default_seg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_default_seg(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_seg0(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_base0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_base0(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_index(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_index(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_scale(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_scale(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_need_sib(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_need_sib(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sibscale(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sibscale(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sibbase(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sibbase(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sibindex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sibindex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_seg1(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_base1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_base1(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mem0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mem0(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mem1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mem1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_uint16_t xed3_operand_get_mem_width(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mem_width(xed_decoded_inst_t* d, xed_uint16_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_agen(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_agen(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_relbr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_relbr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ptr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ptr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg0(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg0(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg1(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg2(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg2(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg3(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg4(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg5(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg5(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg6(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg6(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg7(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg7(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg8(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg8(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg9(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_reg9(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_reg_enum_t xed3_operand_get_outreg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_outreg(xed_decoded_inst_t* d, xed_reg_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_encoder_preferred(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_encoder_preferred(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_error_enum_t xed3_operand_get_error(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_error(xed_decoded_inst_t* d, xed_error_enum_t opval); + +static XED_INLINE xed_iclass_enum_t xed3_operand_get_iclass(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_iclass(xed_decoded_inst_t* d, xed_iclass_enum_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nelem(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nelem(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_element_size(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_element_size(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_map(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_map(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_out_of_bytes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_out_of_bytes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_first_f2f3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_first_f2f3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_last_f2f3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_last_f2f3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ild_f2(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ild_f2(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ild_f3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ild_f3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_max_bytes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_max_bytes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ild_seg(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ild_seg(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nseg_prefixes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nseg_prefixes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nrexes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nrexes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nprefixes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nprefixes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_nominal_opcode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_nominal_opcode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_has_modrm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_has_modrm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_has_sib(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_has_sib(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_modrm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_modrm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_sib(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_sib(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_disp(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_disp(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_imm(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm1(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_pos_imm1(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_imm1_bytes(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_imm1_bytes(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_modrm_byte(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_modrm_byte(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_esrc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_esrc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexvalid(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexvalid(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_dummy(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_dummy(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_amd3dnow(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_amd3dnow(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mpxmode(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mpxmode(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_cet(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_cet(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_cldemote(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_cldemote(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexdest3(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexdest3(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexdest210(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexdest210(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vl(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vl(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vex_prefix(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vex_prefix(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vex_c4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vex_c4(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_bcast(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_bcast(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_must_use_evex(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_must_use_evex(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_zeroing(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_zeroing(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_llrc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_llrc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_bcrc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_bcrc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_rexrr(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_rexrr(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_vexdest4(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_vexdest4(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_mask(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_mask(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_roundc(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_roundc(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_sae(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_sae(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_no_scale_disp8(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_no_scale_disp8(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_ubit(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_ubit(xed_decoded_inst_t* d, xed_bits_t opval); + +static XED_INLINE xed_bits_t xed3_operand_get_wbnoinvd(const xed_decoded_inst_t* d); + +static XED_INLINE void xed3_operand_set_wbnoinvd(xed_decoded_inst_t* d, xed_bits_t opval); + +XED_DLL_EXPORT void xed3_get_generic_operand(const xed_decoded_inst_t* d, xed_operand_enum_t operand, void* ret_arg); + +XED_DLL_EXPORT void xed3_set_generic_operand(xed_decoded_inst_t* d, xed_operand_enum_t operand, xed_uint32_t val); + +static XED_INLINE xed_bits_t xed3_operand_get_seg_ovd(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.seg_ovd; +} +static XED_INLINE void xed3_operand_set_seg_ovd(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.seg_ovd = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_hint(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.hint; +} +static XED_INLINE void xed3_operand_set_hint(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.hint = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_encode_force(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.encode_force; +} +static XED_INLINE void xed3_operand_set_encode_force(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.encode_force = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_lock(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.lock; +} +static XED_INLINE void xed3_operand_set_lock(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.lock = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_need_memdisp(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.need_memdisp; +} +static XED_INLINE void xed3_operand_set_need_memdisp(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.need_memdisp = (xed_uint8_t)opval; +} +static XED_INLINE xed_int64_t xed3_operand_get_disp(const xed_decoded_inst_t* d) +{ +return (xed_int64_t)d->_operands.disp; +} +static XED_INLINE void xed3_operand_set_disp(xed_decoded_inst_t* d, xed_int64_t opval) +{ +d->_operands.disp = (xed_uint64_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_disp_width(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.disp_width; +} +static XED_INLINE void xed3_operand_set_disp_width(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.disp_width = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_brdisp_width(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.brdisp_width; +} +static XED_INLINE void xed3_operand_set_brdisp_width(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.brdisp_width = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_df32(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.df32; +} +static XED_INLINE void xed3_operand_set_df32(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.df32 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_df64(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.df64; +} +static XED_INLINE void xed3_operand_set_df64(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.df64 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_norex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.norex; +} +static XED_INLINE void xed3_operand_set_norex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.norex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_needrex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.needrex; +} +static XED_INLINE void xed3_operand_set_needrex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.needrex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rex; +} +static XED_INLINE void xed3_operand_set_rex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexw(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexw; +} +static XED_INLINE void xed3_operand_set_rexw(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexw = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexr; +} +static XED_INLINE void xed3_operand_set_rexr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexr = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexx(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexx; +} +static XED_INLINE void xed3_operand_set_rexx(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexx = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexb(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexb; +} +static XED_INLINE void xed3_operand_set_rexb(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexb = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rep(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rep; +} +static XED_INLINE void xed3_operand_set_rep(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rep = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_osz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.osz; +} +static XED_INLINE void xed3_operand_set_osz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.osz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_prefix66(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.prefix66; +} +static XED_INLINE void xed3_operand_set_prefix66(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.prefix66 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_asz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.asz; +} +static XED_INLINE void xed3_operand_set_asz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.asz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_eosz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.eosz; +} +static XED_INLINE void xed3_operand_set_eosz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.eosz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_easz(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.easz; +} +static XED_INLINE void xed3_operand_set_easz(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.easz = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mod(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mod; +} +static XED_INLINE void xed3_operand_set_mod(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mod = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_reg(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.reg; +} +static XED_INLINE void xed3_operand_set_reg(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.reg = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_srm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.srm; +} +static XED_INLINE void xed3_operand_set_srm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.srm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rm; +} +static XED_INLINE void xed3_operand_set_rm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_realmode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.realmode; +} +static XED_INLINE void xed3_operand_set_realmode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.realmode = (xed_uint8_t)opval; +} +static XED_INLINE xed_chip_enum_t xed3_operand_get_chip(const xed_decoded_inst_t* d) +{ +return (xed_chip_enum_t)d->_operands.chip; +} +static XED_INLINE void xed3_operand_set_chip(xed_decoded_inst_t* d, xed_chip_enum_t opval) +{ +d->_operands.chip = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mode; +} +static XED_INLINE void xed3_operand_set_mode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_smode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.smode; +} +static XED_INLINE void xed3_operand_set_smode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.smode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_modep5(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.modep5; +} +static XED_INLINE void xed3_operand_set_modep5(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.modep5 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_modep55c(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.modep55c; +} +static XED_INLINE void xed3_operand_set_modep55c(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.modep55c = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_p4(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.p4; +} +static XED_INLINE void xed3_operand_set_p4(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.p4 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_lzcnt(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.lzcnt; +} +static XED_INLINE void xed3_operand_set_lzcnt(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.lzcnt = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_tzcnt(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.tzcnt; +} +static XED_INLINE void xed3_operand_set_tzcnt(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.tzcnt = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mode_first_prefix(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mode_first_prefix; +} +static XED_INLINE void xed3_operand_set_mode_first_prefix(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mode_first_prefix = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mode_short_ud0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mode_short_ud0; +} +static XED_INLINE void xed3_operand_set_mode_short_ud0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mode_short_ud0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm0; +} +static XED_INLINE void xed3_operand_set_imm0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm1; +} +static XED_INLINE void xed3_operand_set_imm1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm0signed(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm0signed; +} +static XED_INLINE void xed3_operand_set_imm0signed(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm0signed = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint64_t xed3_operand_get_uimm0(const xed_decoded_inst_t* d) +{ +return (xed_uint64_t)d->_operands.uimm0; +} +static XED_INLINE void xed3_operand_set_uimm0(xed_decoded_inst_t* d, xed_uint64_t opval) +{ +d->_operands.uimm0 = (xed_uint64_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_uimm1(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.uimm1; +} +static XED_INLINE void xed3_operand_set_uimm1(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.uimm1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint8_t xed3_operand_get_imm_width(const xed_decoded_inst_t* d) +{ +return (xed_uint8_t)d->_operands.imm_width; +} +static XED_INLINE void xed3_operand_set_imm_width(xed_decoded_inst_t* d, xed_uint8_t opval) +{ +d->_operands.imm_width = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.using_default_segment0; +} +static XED_INLINE void xed3_operand_set_using_default_segment0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.using_default_segment0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_using_default_segment1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.using_default_segment1; +} +static XED_INLINE void xed3_operand_set_using_default_segment1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.using_default_segment1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_default_seg(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.default_seg; +} +static XED_INLINE void xed3_operand_set_default_seg(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.default_seg = (xed_uint8_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg0(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.seg0; +} +static XED_INLINE void xed3_operand_set_seg0(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.seg0 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_base0(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.base0; +} +static XED_INLINE void xed3_operand_set_base0(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.base0 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_index(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.index; +} +static XED_INLINE void xed3_operand_set_index(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.index = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_scale(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.scale; +} +static XED_INLINE void xed3_operand_set_scale(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.scale = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_need_sib(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.need_sib; +} +static XED_INLINE void xed3_operand_set_need_sib(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.need_sib = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sibscale(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sibscale; +} +static XED_INLINE void xed3_operand_set_sibscale(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sibscale = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sibbase(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sibbase; +} +static XED_INLINE void xed3_operand_set_sibbase(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sibbase = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sibindex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sibindex; +} +static XED_INLINE void xed3_operand_set_sibindex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sibindex = (xed_uint8_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_seg1(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.seg1; +} +static XED_INLINE void xed3_operand_set_seg1(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.seg1 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_base1(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.base1; +} +static XED_INLINE void xed3_operand_set_base1(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.base1 = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mem0(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mem0; +} +static XED_INLINE void xed3_operand_set_mem0(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mem0 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mem1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mem1; +} +static XED_INLINE void xed3_operand_set_mem1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mem1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_uint16_t xed3_operand_get_mem_width(const xed_decoded_inst_t* d) +{ +return (xed_uint16_t)d->_operands.mem_width; +} +static XED_INLINE void xed3_operand_set_mem_width(xed_decoded_inst_t* d, xed_uint16_t opval) +{ +d->_operands.mem_width = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_agen(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.agen; +} +static XED_INLINE void xed3_operand_set_agen(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.agen = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_relbr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.relbr; +} +static XED_INLINE void xed3_operand_set_relbr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.relbr = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ptr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ptr; +} +static XED_INLINE void xed3_operand_set_ptr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ptr = (xed_uint8_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg0(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg0; +} +static XED_INLINE void xed3_operand_set_reg0(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg0 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg1(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg1; +} +static XED_INLINE void xed3_operand_set_reg1(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg1 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg2(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg2; +} +static XED_INLINE void xed3_operand_set_reg2(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg2 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg3(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg3; +} +static XED_INLINE void xed3_operand_set_reg3(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg3 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg4(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg4; +} +static XED_INLINE void xed3_operand_set_reg4(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg4 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg5(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg5; +} +static XED_INLINE void xed3_operand_set_reg5(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg5 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg6(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg6; +} +static XED_INLINE void xed3_operand_set_reg6(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg6 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg7(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg7; +} +static XED_INLINE void xed3_operand_set_reg7(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg7 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg8(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg8; +} +static XED_INLINE void xed3_operand_set_reg8(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg8 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_reg9(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.reg9; +} +static XED_INLINE void xed3_operand_set_reg9(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.reg9 = (xed_uint16_t)opval; +} +static XED_INLINE xed_reg_enum_t xed3_operand_get_outreg(const xed_decoded_inst_t* d) +{ +return (xed_reg_enum_t)d->_operands.outreg; +} +static XED_INLINE void xed3_operand_set_outreg(xed_decoded_inst_t* d, xed_reg_enum_t opval) +{ +d->_operands.outreg = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_encoder_preferred(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.encoder_preferred; +} +static XED_INLINE void xed3_operand_set_encoder_preferred(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.encoder_preferred = (xed_uint8_t)opval; +} +static XED_INLINE xed_error_enum_t xed3_operand_get_error(const xed_decoded_inst_t* d) +{ +return (xed_error_enum_t)d->_operands.error; +} +static XED_INLINE void xed3_operand_set_error(xed_decoded_inst_t* d, xed_error_enum_t opval) +{ +d->_operands.error = (xed_uint8_t)opval; +} +static XED_INLINE xed_iclass_enum_t xed3_operand_get_iclass(const xed_decoded_inst_t* d) +{ +return (xed_iclass_enum_t)d->_operands.iclass; +} +static XED_INLINE void xed3_operand_set_iclass(xed_decoded_inst_t* d, xed_iclass_enum_t opval) +{ +d->_operands.iclass = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nelem(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nelem; +} +static XED_INLINE void xed3_operand_set_nelem(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nelem = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_element_size(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.element_size; +} +static XED_INLINE void xed3_operand_set_element_size(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.element_size = (xed_uint16_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_map(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.map; +} +static XED_INLINE void xed3_operand_set_map(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.map = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_out_of_bytes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.out_of_bytes; +} +static XED_INLINE void xed3_operand_set_out_of_bytes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.out_of_bytes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_first_f2f3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.first_f2f3; +} +static XED_INLINE void xed3_operand_set_first_f2f3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.first_f2f3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_last_f2f3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.last_f2f3; +} +static XED_INLINE void xed3_operand_set_last_f2f3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.last_f2f3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ild_f2(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ild_f2; +} +static XED_INLINE void xed3_operand_set_ild_f2(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ild_f2 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ild_f3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ild_f3; +} +static XED_INLINE void xed3_operand_set_ild_f3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ild_f3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_max_bytes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.max_bytes; +} +static XED_INLINE void xed3_operand_set_max_bytes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.max_bytes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ild_seg(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ild_seg; +} +static XED_INLINE void xed3_operand_set_ild_seg(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ild_seg = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nseg_prefixes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nseg_prefixes; +} +static XED_INLINE void xed3_operand_set_nseg_prefixes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nseg_prefixes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nrexes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nrexes; +} +static XED_INLINE void xed3_operand_set_nrexes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nrexes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nprefixes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nprefixes; +} +static XED_INLINE void xed3_operand_set_nprefixes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nprefixes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_nominal_opcode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.nominal_opcode; +} +static XED_INLINE void xed3_operand_set_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.nominal_opcode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_nominal_opcode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_nominal_opcode; +} +static XED_INLINE void xed3_operand_set_pos_nominal_opcode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_nominal_opcode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_has_modrm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.has_modrm; +} +static XED_INLINE void xed3_operand_set_has_modrm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.has_modrm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_has_sib(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.has_sib; +} +static XED_INLINE void xed3_operand_set_has_sib(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.has_sib = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_modrm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_modrm; +} +static XED_INLINE void xed3_operand_set_pos_modrm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_modrm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_sib(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_sib; +} +static XED_INLINE void xed3_operand_set_pos_sib(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_sib = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_disp(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_disp; +} +static XED_INLINE void xed3_operand_set_pos_disp(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_disp = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_imm; +} +static XED_INLINE void xed3_operand_set_pos_imm(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_imm = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_pos_imm1(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.pos_imm1; +} +static XED_INLINE void xed3_operand_set_pos_imm1(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.pos_imm1 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_imm1_bytes(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.imm1_bytes; +} +static XED_INLINE void xed3_operand_set_imm1_bytes(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.imm1_bytes = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_modrm_byte(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.modrm_byte; +} +static XED_INLINE void xed3_operand_set_modrm_byte(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.modrm_byte = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_esrc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.esrc; +} +static XED_INLINE void xed3_operand_set_esrc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.esrc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexvalid(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexvalid; +} +static XED_INLINE void xed3_operand_set_vexvalid(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexvalid = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_dummy(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.dummy; +} +static XED_INLINE void xed3_operand_set_dummy(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.dummy = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_amd3dnow(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.amd3dnow; +} +static XED_INLINE void xed3_operand_set_amd3dnow(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.amd3dnow = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mpxmode(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mpxmode; +} +static XED_INLINE void xed3_operand_set_mpxmode(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mpxmode = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_cet(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.cet; +} +static XED_INLINE void xed3_operand_set_cet(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.cet = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_cldemote(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.cldemote; +} +static XED_INLINE void xed3_operand_set_cldemote(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.cldemote = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexdest3(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexdest3; +} +static XED_INLINE void xed3_operand_set_vexdest3(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexdest3 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexdest210(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexdest210; +} +static XED_INLINE void xed3_operand_set_vexdest210(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexdest210 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vl(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vl; +} +static XED_INLINE void xed3_operand_set_vl(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vl = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vex_prefix(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vex_prefix; +} +static XED_INLINE void xed3_operand_set_vex_prefix(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vex_prefix = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vex_c4(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vex_c4; +} +static XED_INLINE void xed3_operand_set_vex_c4(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vex_c4 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_bcast(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.bcast; +} +static XED_INLINE void xed3_operand_set_bcast(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.bcast = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_must_use_evex(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.must_use_evex; +} +static XED_INLINE void xed3_operand_set_must_use_evex(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.must_use_evex = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_zeroing(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.zeroing; +} +static XED_INLINE void xed3_operand_set_zeroing(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.zeroing = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_llrc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.llrc; +} +static XED_INLINE void xed3_operand_set_llrc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.llrc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_bcrc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.bcrc; +} +static XED_INLINE void xed3_operand_set_bcrc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.bcrc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_rexrr(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.rexrr; +} +static XED_INLINE void xed3_operand_set_rexrr(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.rexrr = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_vexdest4(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.vexdest4; +} +static XED_INLINE void xed3_operand_set_vexdest4(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.vexdest4 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_mask(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.mask; +} +static XED_INLINE void xed3_operand_set_mask(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.mask = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_roundc(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.roundc; +} +static XED_INLINE void xed3_operand_set_roundc(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.roundc = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_sae(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.sae; +} +static XED_INLINE void xed3_operand_set_sae(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.sae = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_no_scale_disp8(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.no_scale_disp8; +} +static XED_INLINE void xed3_operand_set_no_scale_disp8(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.no_scale_disp8 = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_ubit(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.ubit; +} +static XED_INLINE void xed3_operand_set_ubit(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.ubit = (xed_uint8_t)opval; +} +static XED_INLINE xed_bits_t xed3_operand_get_wbnoinvd(const xed_decoded_inst_t* d) +{ +return (xed_bits_t)d->_operands.wbnoinvd; +} +static XED_INLINE void xed3_operand_set_wbnoinvd(xed_decoded_inst_t* d, xed_bits_t opval) +{ +d->_operands.wbnoinvd = (xed_uint8_t)opval; +} +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-action-enum.c b/CodeVirtualizer/build/obj/xed-operand-action-enum.c new file mode 100644 index 0000000..9fbcaae --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-action-enum.c @@ -0,0 +1,72 @@ +/// @file xed-operand-action-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-action-enum.h" + +typedef struct { + const char* name; + xed_operand_action_enum_t value; +} name_table_xed_operand_action_enum_t; +static const name_table_xed_operand_action_enum_t name_array_xed_operand_action_enum_t[] = { +{"INVALID", XED_OPERAND_ACTION_INVALID}, +{"RW", XED_OPERAND_ACTION_RW}, +{"R", XED_OPERAND_ACTION_R}, +{"W", XED_OPERAND_ACTION_W}, +{"RCW", XED_OPERAND_ACTION_RCW}, +{"CW", XED_OPERAND_ACTION_CW}, +{"CRW", XED_OPERAND_ACTION_CRW}, +{"CR", XED_OPERAND_ACTION_CR}, +{"LAST", XED_OPERAND_ACTION_LAST}, +{0, XED_OPERAND_ACTION_LAST}, +}; + + +xed_operand_action_enum_t str2xed_operand_action_enum_t(const char* s) +{ + const name_table_xed_operand_action_enum_t* p = name_array_xed_operand_action_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_ACTION_INVALID; +} + + +const char* xed_operand_action_enum_t2str(const xed_operand_action_enum_t p) +{ + xed_operand_action_enum_t type_idx = p; + if ( p > XED_OPERAND_ACTION_LAST) type_idx = XED_OPERAND_ACTION_LAST; + return name_array_xed_operand_action_enum_t[type_idx].name; +} + +xed_operand_action_enum_t xed_operand_action_enum_t_last(void) { + return XED_OPERAND_ACTION_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_ACTION_INVALID: + case XED_OPERAND_ACTION_RW: + case XED_OPERAND_ACTION_R: + case XED_OPERAND_ACTION_W: + case XED_OPERAND_ACTION_RCW: + case XED_OPERAND_ACTION_CW: + case XED_OPERAND_ACTION_CRW: + case XED_OPERAND_ACTION_CR: + case XED_OPERAND_ACTION_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-action-enum.h b/CodeVirtualizer/build/obj/xed-operand-action-enum.h new file mode 100644 index 0000000..386b8c2 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-action-enum.h @@ -0,0 +1,45 @@ +/// @file xed-operand-action-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ACTION_ENUM_H) +# define XED_OPERAND_ACTION_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_ACTION_INVALID_DEFINED 1 +#define XED_OPERAND_ACTION_RW_DEFINED 1 +#define XED_OPERAND_ACTION_R_DEFINED 1 +#define XED_OPERAND_ACTION_W_DEFINED 1 +#define XED_OPERAND_ACTION_RCW_DEFINED 1 +#define XED_OPERAND_ACTION_CW_DEFINED 1 +#define XED_OPERAND_ACTION_CRW_DEFINED 1 +#define XED_OPERAND_ACTION_CR_DEFINED 1 +#define XED_OPERAND_ACTION_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_ACTION_INVALID, + XED_OPERAND_ACTION_RW, ///< Read and written (must write) + XED_OPERAND_ACTION_R, ///< Read-only + XED_OPERAND_ACTION_W, ///< Write-only (must write) + XED_OPERAND_ACTION_RCW, ///< Read and conditionlly written (may write) + XED_OPERAND_ACTION_CW, ///< Conditionlly written (may write) + XED_OPERAND_ACTION_CRW, ///< Conditionlly read, always written (must write) + XED_OPERAND_ACTION_CR, ///< Conditional read + XED_OPERAND_ACTION_LAST +} xed_operand_action_enum_t; + +/// This converts strings to #xed_operand_action_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_action_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_action_enum_t str2xed_operand_action_enum_t(const char* s); +/// This converts strings to #xed_operand_action_enum_t types. +/// @param p An enumeration element of type xed_operand_action_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_action_enum_t2str(const xed_operand_action_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_action_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_action_enum_t xed_operand_action_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-convert-enum.c b/CodeVirtualizer/build/obj/xed-operand-convert-enum.c new file mode 100644 index 0000000..7b6e95e --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-convert-enum.c @@ -0,0 +1,66 @@ +/// @file xed-operand-convert-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-convert-enum.h" + +typedef struct { + const char* name; + xed_operand_convert_enum_t value; +} name_table_xed_operand_convert_enum_t; +static const name_table_xed_operand_convert_enum_t name_array_xed_operand_convert_enum_t[] = { +{"INVALID", XED_OPERAND_CONVERT_INVALID}, +{"ZEROSTR", XED_OPERAND_CONVERT_ZEROSTR}, +{"SAESTR", XED_OPERAND_CONVERT_SAESTR}, +{"ROUNDC", XED_OPERAND_CONVERT_ROUNDC}, +{"BCASTSTR", XED_OPERAND_CONVERT_BCASTSTR}, +{"LAST", XED_OPERAND_CONVERT_LAST}, +{0, XED_OPERAND_CONVERT_LAST}, +}; + + +xed_operand_convert_enum_t str2xed_operand_convert_enum_t(const char* s) +{ + const name_table_xed_operand_convert_enum_t* p = name_array_xed_operand_convert_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_CONVERT_INVALID; +} + + +const char* xed_operand_convert_enum_t2str(const xed_operand_convert_enum_t p) +{ + xed_operand_convert_enum_t type_idx = p; + if ( p > XED_OPERAND_CONVERT_LAST) type_idx = XED_OPERAND_CONVERT_LAST; + return name_array_xed_operand_convert_enum_t[type_idx].name; +} + +xed_operand_convert_enum_t xed_operand_convert_enum_t_last(void) { + return XED_OPERAND_CONVERT_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_CONVERT_INVALID: + case XED_OPERAND_CONVERT_ZEROSTR: + case XED_OPERAND_CONVERT_SAESTR: + case XED_OPERAND_CONVERT_ROUNDC: + case XED_OPERAND_CONVERT_BCASTSTR: + case XED_OPERAND_CONVERT_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-convert-enum.h b/CodeVirtualizer/build/obj/xed-operand-convert-enum.h new file mode 100644 index 0000000..50f83e3 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-convert-enum.h @@ -0,0 +1,39 @@ +/// @file xed-operand-convert-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_CONVERT_ENUM_H) +# define XED_OPERAND_CONVERT_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_CONVERT_INVALID_DEFINED 1 +#define XED_OPERAND_CONVERT_ZEROSTR_DEFINED 1 +#define XED_OPERAND_CONVERT_SAESTR_DEFINED 1 +#define XED_OPERAND_CONVERT_ROUNDC_DEFINED 1 +#define XED_OPERAND_CONVERT_BCASTSTR_DEFINED 1 +#define XED_OPERAND_CONVERT_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_CONVERT_INVALID, + XED_OPERAND_CONVERT_ZEROSTR, + XED_OPERAND_CONVERT_SAESTR, + XED_OPERAND_CONVERT_ROUNDC, + XED_OPERAND_CONVERT_BCASTSTR, + XED_OPERAND_CONVERT_LAST +} xed_operand_convert_enum_t; + +/// This converts strings to #xed_operand_convert_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_convert_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_convert_enum_t str2xed_operand_convert_enum_t(const char* s); +/// This converts strings to #xed_operand_convert_enum_t types. +/// @param p An enumeration element of type xed_operand_convert_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_convert_enum_t2str(const xed_operand_convert_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_convert_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_convert_enum_t xed_operand_convert_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-convert-enum.txt b/CodeVirtualizer/build/obj/xed-operand-convert-enum.txt new file mode 100644 index 0000000..52d16bb --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-convert-enum.txt @@ -0,0 +1,35 @@ +# @file xed-operand-convert-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-operand-convert-enum.c +hfn xed-operand-convert-enum.h +typename xed_operand_convert_enum_t +prefix XED_OPERAND_CONVERT_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +ZEROSTR +SAESTR +ROUNDC +BCASTSTR diff --git a/CodeVirtualizer/build/obj/xed-operand-convert-init.c b/CodeVirtualizer/build/obj/xed-operand-convert-init.c new file mode 100644 index 0000000..f8f1972 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-convert-init.c @@ -0,0 +1,34 @@ +/// @file xed-operand-convert-init.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-operand-convert-enum.h" +#include "xed-gen-table-defs.h" + +const xed_operand_convert_enum_t xed_operand_convert[XED_MAX_CONVERT_PATTERNS][XED_MAX_DECORATIONS_PER_OPERAND] = { +/* 0 */ { XED_OPERAND_CONVERT_INVALID, XED_OPERAND_CONVERT_INVALID, XED_OPERAND_CONVERT_INVALID }, +/* 1 */ { XED_OPERAND_CONVERT_ZEROSTR, XED_OPERAND_CONVERT_INVALID, XED_OPERAND_CONVERT_INVALID }, +/* 2 */ { XED_OPERAND_CONVERT_BCASTSTR, XED_OPERAND_CONVERT_INVALID, XED_OPERAND_CONVERT_INVALID }, +/* 3 */ { XED_OPERAND_CONVERT_SAESTR, XED_OPERAND_CONVERT_INVALID, XED_OPERAND_CONVERT_INVALID }, +/* 4 */ { XED_OPERAND_CONVERT_ROUNDC, XED_OPERAND_CONVERT_INVALID, XED_OPERAND_CONVERT_INVALID }, + +}; diff --git a/CodeVirtualizer/build/obj/xed-operand-ctype-enum.c b/CodeVirtualizer/build/obj/xed-operand-ctype-enum.c new file mode 100644 index 0000000..707eed8 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-ctype-enum.c @@ -0,0 +1,76 @@ +/// @file xed-operand-ctype-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-ctype-enum.h" + +typedef struct { + const char* name; + xed_operand_ctype_enum_t value; +} name_table_xed_operand_ctype_enum_t; +static const name_table_xed_operand_ctype_enum_t name_array_xed_operand_ctype_enum_t[] = { +{"INVALID", XED_OPERAND_CTYPE_INVALID}, +{"XED_BITS_T", XED_OPERAND_CTYPE_XED_BITS_T}, +{"XED_CHIP_ENUM_T", XED_OPERAND_CTYPE_XED_CHIP_ENUM_T}, +{"XED_ERROR_ENUM_T", XED_OPERAND_CTYPE_XED_ERROR_ENUM_T}, +{"XED_ICLASS_ENUM_T", XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T}, +{"XED_INT64_T", XED_OPERAND_CTYPE_XED_INT64_T}, +{"XED_REG_ENUM_T", XED_OPERAND_CTYPE_XED_REG_ENUM_T}, +{"XED_UINT16_T", XED_OPERAND_CTYPE_XED_UINT16_T}, +{"XED_UINT64_T", XED_OPERAND_CTYPE_XED_UINT64_T}, +{"XED_UINT8_T", XED_OPERAND_CTYPE_XED_UINT8_T}, +{"LAST", XED_OPERAND_CTYPE_LAST}, +{0, XED_OPERAND_CTYPE_LAST}, +}; + + +xed_operand_ctype_enum_t str2xed_operand_ctype_enum_t(const char* s) +{ + const name_table_xed_operand_ctype_enum_t* p = name_array_xed_operand_ctype_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_CTYPE_INVALID; +} + + +const char* xed_operand_ctype_enum_t2str(const xed_operand_ctype_enum_t p) +{ + xed_operand_ctype_enum_t type_idx = p; + if ( p > XED_OPERAND_CTYPE_LAST) type_idx = XED_OPERAND_CTYPE_LAST; + return name_array_xed_operand_ctype_enum_t[type_idx].name; +} + +xed_operand_ctype_enum_t xed_operand_ctype_enum_t_last(void) { + return XED_OPERAND_CTYPE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_CTYPE_INVALID: + case XED_OPERAND_CTYPE_XED_BITS_T: + case XED_OPERAND_CTYPE_XED_CHIP_ENUM_T: + case XED_OPERAND_CTYPE_XED_ERROR_ENUM_T: + case XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T: + case XED_OPERAND_CTYPE_XED_INT64_T: + case XED_OPERAND_CTYPE_XED_REG_ENUM_T: + case XED_OPERAND_CTYPE_XED_UINT16_T: + case XED_OPERAND_CTYPE_XED_UINT64_T: + case XED_OPERAND_CTYPE_XED_UINT8_T: + case XED_OPERAND_CTYPE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-ctype-enum.h b/CodeVirtualizer/build/obj/xed-operand-ctype-enum.h new file mode 100644 index 0000000..e694fa8 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-ctype-enum.h @@ -0,0 +1,49 @@ +/// @file xed-operand-ctype-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_CTYPE_ENUM_H) +# define XED_OPERAND_CTYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_CTYPE_INVALID_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_BITS_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_CHIP_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_ERROR_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_INT64_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_REG_ENUM_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_UINT16_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_UINT64_T_DEFINED 1 +#define XED_OPERAND_CTYPE_XED_UINT8_T_DEFINED 1 +#define XED_OPERAND_CTYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_CTYPE_INVALID, + XED_OPERAND_CTYPE_XED_BITS_T, + XED_OPERAND_CTYPE_XED_CHIP_ENUM_T, + XED_OPERAND_CTYPE_XED_ERROR_ENUM_T, + XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T, + XED_OPERAND_CTYPE_XED_INT64_T, + XED_OPERAND_CTYPE_XED_REG_ENUM_T, + XED_OPERAND_CTYPE_XED_UINT16_T, + XED_OPERAND_CTYPE_XED_UINT64_T, + XED_OPERAND_CTYPE_XED_UINT8_T, + XED_OPERAND_CTYPE_LAST +} xed_operand_ctype_enum_t; + +/// This converts strings to #xed_operand_ctype_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_ctype_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_ctype_enum_t str2xed_operand_ctype_enum_t(const char* s); +/// This converts strings to #xed_operand_ctype_enum_t types. +/// @param p An enumeration element of type xed_operand_ctype_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_ctype_enum_t2str(const xed_operand_ctype_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_ctype_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_ctype_enum_t xed_operand_ctype_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-ctype-enum.txt b/CodeVirtualizer/build/obj/xed-operand-ctype-enum.txt new file mode 100644 index 0000000..eecdcdd --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-ctype-enum.txt @@ -0,0 +1,40 @@ +# @file xed-operand-ctype-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-operand-ctype-enum.c +hfn xed-operand-ctype-enum.h +typename xed_operand_ctype_enum_t +prefix XED_OPERAND_CTYPE_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +XED_BITS_T +XED_CHIP_ENUM_T +XED_ERROR_ENUM_T +XED_ICLASS_ENUM_T +XED_INT64_T +XED_REG_ENUM_T +XED_UINT16_T +XED_UINT64_T +XED_UINT8_T diff --git a/CodeVirtualizer/build/obj/xed-operand-ctype-map.c b/CodeVirtualizer/build/obj/xed-operand-ctype-map.c new file mode 100644 index 0000000..48fd404 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-ctype-map.c @@ -0,0 +1,291 @@ +/// @file xed-operand-ctype-map.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed-operand-ctype-map.h" +static xed_operand_ctype_enum_t xed_operand_ctype[XED_OPERAND_LAST]; +static unsigned int xed_operand_bits[XED_OPERAND_LAST]; +void xed_init_operand_ctypes(void) +{ + xed_operand_ctype[XED_OPERAND_SEG_OVD]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_HINT]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ENCODE_FORCE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_LOCK]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NEED_MEMDISP]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_DISP]=XED_OPERAND_CTYPE_XED_INT64_T; + xed_operand_ctype[XED_OPERAND_DISP_WIDTH]=XED_OPERAND_CTYPE_XED_UINT8_T; + xed_operand_ctype[XED_OPERAND_BRDISP_WIDTH]=XED_OPERAND_CTYPE_XED_UINT8_T; + xed_operand_ctype[XED_OPERAND_DF32]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_DF64]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NOREX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NEEDREX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REXW]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REXR]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REXX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REXB]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REP]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_OSZ]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_PREFIX66]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ASZ]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_EOSZ]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_EASZ]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MOD]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REG]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SRM]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_RM]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REALMODE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_CHIP]=XED_OPERAND_CTYPE_XED_CHIP_ENUM_T; + xed_operand_ctype[XED_OPERAND_MODE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SMODE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MODEP5]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MODEP55C]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_P4]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_LZCNT]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_TZCNT]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MODE_FIRST_PREFIX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MODE_SHORT_UD0]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_IMM0]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_IMM1]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_IMM0SIGNED]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_UIMM0]=XED_OPERAND_CTYPE_XED_UINT64_T; + xed_operand_ctype[XED_OPERAND_UIMM1]=XED_OPERAND_CTYPE_XED_UINT8_T; + xed_operand_ctype[XED_OPERAND_IMM_WIDTH]=XED_OPERAND_CTYPE_XED_UINT8_T; + xed_operand_ctype[XED_OPERAND_USING_DEFAULT_SEGMENT0]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_USING_DEFAULT_SEGMENT1]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_DEFAULT_SEG]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SEG0]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_BASE0]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_INDEX]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_SCALE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NEED_SIB]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SIBSCALE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SIBBASE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SIBINDEX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SEG1]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_BASE1]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_MEM0]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MEM1]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MEM_WIDTH]=XED_OPERAND_CTYPE_XED_UINT16_T; + xed_operand_ctype[XED_OPERAND_AGEN]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_RELBR]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_PTR]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REG0]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG1]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG2]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG3]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG4]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG5]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG6]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG7]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG8]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_REG9]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_OUTREG]=XED_OPERAND_CTYPE_XED_REG_ENUM_T; + xed_operand_ctype[XED_OPERAND_ENCODER_PREFERRED]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ERROR]=XED_OPERAND_CTYPE_XED_ERROR_ENUM_T; + xed_operand_ctype[XED_OPERAND_ICLASS]=XED_OPERAND_CTYPE_XED_ICLASS_ENUM_T; + xed_operand_ctype[XED_OPERAND_NELEM]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ELEMENT_SIZE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MAP]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_OUT_OF_BYTES]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_FIRST_F2F3]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_LAST_F2F3]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ILD_F2]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ILD_F3]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MAX_BYTES]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ILD_SEG]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NSEG_PREFIXES]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NREXES]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NPREFIXES]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NOMINAL_OPCODE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_POS_NOMINAL_OPCODE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_HAS_MODRM]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_HAS_SIB]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_POS_MODRM]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_POS_SIB]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_POS_DISP]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_POS_IMM]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_POS_IMM1]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_IMM1_BYTES]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MODRM_BYTE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ESRC]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VEXVALID]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_DUMMY]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_AMD3DNOW]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MPXMODE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_CET]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_CLDEMOTE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VEXDEST3]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VEXDEST210]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VL]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VEX_PREFIX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VEX_C4]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_BCAST]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MUST_USE_EVEX]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ZEROING]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_LLRC]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_BCRC]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_REXRR]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_VEXDEST4]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_MASK]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_ROUNDC]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_SAE]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_NO_SCALE_DISP8]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_UBIT]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_ctype[XED_OPERAND_WBNOINVD]=XED_OPERAND_CTYPE_XED_BITS_T; + xed_operand_bits[XED_OPERAND_SEG_OVD]=3; + xed_operand_bits[XED_OPERAND_HINT]=3; + xed_operand_bits[XED_OPERAND_ENCODE_FORCE]=1; + xed_operand_bits[XED_OPERAND_LOCK]=1; + xed_operand_bits[XED_OPERAND_NEED_MEMDISP]=6; + xed_operand_bits[XED_OPERAND_DISP]=64; + xed_operand_bits[XED_OPERAND_DISP_WIDTH]=8; + xed_operand_bits[XED_OPERAND_BRDISP_WIDTH]=8; + xed_operand_bits[XED_OPERAND_DF32]=1; + xed_operand_bits[XED_OPERAND_DF64]=1; + xed_operand_bits[XED_OPERAND_NOREX]=1; + xed_operand_bits[XED_OPERAND_NEEDREX]=1; + xed_operand_bits[XED_OPERAND_REX]=1; + xed_operand_bits[XED_OPERAND_REXW]=1; + xed_operand_bits[XED_OPERAND_REXR]=1; + xed_operand_bits[XED_OPERAND_REXX]=1; + xed_operand_bits[XED_OPERAND_REXB]=1; + xed_operand_bits[XED_OPERAND_REP]=2; + xed_operand_bits[XED_OPERAND_OSZ]=1; + xed_operand_bits[XED_OPERAND_PREFIX66]=1; + xed_operand_bits[XED_OPERAND_ASZ]=1; + xed_operand_bits[XED_OPERAND_EOSZ]=2; + xed_operand_bits[XED_OPERAND_EASZ]=2; + xed_operand_bits[XED_OPERAND_MOD]=2; + xed_operand_bits[XED_OPERAND_REG]=3; + xed_operand_bits[XED_OPERAND_SRM]=3; + xed_operand_bits[XED_OPERAND_RM]=3; + xed_operand_bits[XED_OPERAND_REALMODE]=1; + xed_operand_bits[XED_OPERAND_CHIP]=16; + xed_operand_bits[XED_OPERAND_MODE]=2; + xed_operand_bits[XED_OPERAND_SMODE]=2; + xed_operand_bits[XED_OPERAND_MODEP5]=1; + xed_operand_bits[XED_OPERAND_MODEP55C]=1; + xed_operand_bits[XED_OPERAND_P4]=1; + xed_operand_bits[XED_OPERAND_LZCNT]=1; + xed_operand_bits[XED_OPERAND_TZCNT]=1; + xed_operand_bits[XED_OPERAND_MODE_FIRST_PREFIX]=1; + xed_operand_bits[XED_OPERAND_MODE_SHORT_UD0]=1; + xed_operand_bits[XED_OPERAND_IMM0]=1; + xed_operand_bits[XED_OPERAND_IMM1]=1; + xed_operand_bits[XED_OPERAND_IMM0SIGNED]=1; + xed_operand_bits[XED_OPERAND_UIMM0]=64; + xed_operand_bits[XED_OPERAND_UIMM1]=8; + xed_operand_bits[XED_OPERAND_IMM_WIDTH]=8; + xed_operand_bits[XED_OPERAND_USING_DEFAULT_SEGMENT0]=1; + xed_operand_bits[XED_OPERAND_USING_DEFAULT_SEGMENT1]=1; + xed_operand_bits[XED_OPERAND_DEFAULT_SEG]=2; + xed_operand_bits[XED_OPERAND_SEG0]=16; + xed_operand_bits[XED_OPERAND_BASE0]=16; + xed_operand_bits[XED_OPERAND_INDEX]=16; + xed_operand_bits[XED_OPERAND_SCALE]=4; + xed_operand_bits[XED_OPERAND_NEED_SIB]=1; + xed_operand_bits[XED_OPERAND_SIBSCALE]=2; + xed_operand_bits[XED_OPERAND_SIBBASE]=3; + xed_operand_bits[XED_OPERAND_SIBINDEX]=3; + xed_operand_bits[XED_OPERAND_SEG1]=16; + xed_operand_bits[XED_OPERAND_BASE1]=16; + xed_operand_bits[XED_OPERAND_MEM0]=1; + xed_operand_bits[XED_OPERAND_MEM1]=1; + xed_operand_bits[XED_OPERAND_MEM_WIDTH]=16; + xed_operand_bits[XED_OPERAND_AGEN]=1; + xed_operand_bits[XED_OPERAND_RELBR]=1; + xed_operand_bits[XED_OPERAND_PTR]=1; + xed_operand_bits[XED_OPERAND_REG0]=16; + xed_operand_bits[XED_OPERAND_REG1]=16; + xed_operand_bits[XED_OPERAND_REG2]=16; + xed_operand_bits[XED_OPERAND_REG3]=16; + xed_operand_bits[XED_OPERAND_REG4]=16; + xed_operand_bits[XED_OPERAND_REG5]=16; + xed_operand_bits[XED_OPERAND_REG6]=16; + xed_operand_bits[XED_OPERAND_REG7]=16; + xed_operand_bits[XED_OPERAND_REG8]=16; + xed_operand_bits[XED_OPERAND_REG9]=16; + xed_operand_bits[XED_OPERAND_OUTREG]=16; + xed_operand_bits[XED_OPERAND_ENCODER_PREFERRED]=1; + xed_operand_bits[XED_OPERAND_ERROR]=8; + xed_operand_bits[XED_OPERAND_ICLASS]=16; + xed_operand_bits[XED_OPERAND_NELEM]=4; + xed_operand_bits[XED_OPERAND_ELEMENT_SIZE]=9; + xed_operand_bits[XED_OPERAND_MAP]=4; + xed_operand_bits[XED_OPERAND_OUT_OF_BYTES]=1; + xed_operand_bits[XED_OPERAND_FIRST_F2F3]=2; + xed_operand_bits[XED_OPERAND_LAST_F2F3]=2; + xed_operand_bits[XED_OPERAND_ILD_F2]=1; + xed_operand_bits[XED_OPERAND_ILD_F3]=1; + xed_operand_bits[XED_OPERAND_MAX_BYTES]=8; + xed_operand_bits[XED_OPERAND_ILD_SEG]=8; + xed_operand_bits[XED_OPERAND_NSEG_PREFIXES]=8; + xed_operand_bits[XED_OPERAND_NREXES]=8; + xed_operand_bits[XED_OPERAND_NPREFIXES]=8; + xed_operand_bits[XED_OPERAND_NOMINAL_OPCODE]=8; + xed_operand_bits[XED_OPERAND_POS_NOMINAL_OPCODE]=8; + xed_operand_bits[XED_OPERAND_HAS_MODRM]=2; + xed_operand_bits[XED_OPERAND_HAS_SIB]=1; + xed_operand_bits[XED_OPERAND_POS_MODRM]=8; + xed_operand_bits[XED_OPERAND_POS_SIB]=8; + xed_operand_bits[XED_OPERAND_POS_DISP]=8; + xed_operand_bits[XED_OPERAND_POS_IMM]=8; + xed_operand_bits[XED_OPERAND_POS_IMM1]=8; + xed_operand_bits[XED_OPERAND_IMM1_BYTES]=8; + xed_operand_bits[XED_OPERAND_MODRM_BYTE]=8; + xed_operand_bits[XED_OPERAND_ESRC]=4; + xed_operand_bits[XED_OPERAND_VEXVALID]=3; + xed_operand_bits[XED_OPERAND_DUMMY]=1; + xed_operand_bits[XED_OPERAND_AMD3DNOW]=1; + xed_operand_bits[XED_OPERAND_MPXMODE]=1; + xed_operand_bits[XED_OPERAND_CET]=1; + xed_operand_bits[XED_OPERAND_CLDEMOTE]=1; + xed_operand_bits[XED_OPERAND_VEXDEST3]=1; + xed_operand_bits[XED_OPERAND_VEXDEST210]=3; + xed_operand_bits[XED_OPERAND_VL]=2; + xed_operand_bits[XED_OPERAND_VEX_PREFIX]=2; + xed_operand_bits[XED_OPERAND_VEX_C4]=1; + xed_operand_bits[XED_OPERAND_BCAST]=5; + xed_operand_bits[XED_OPERAND_MUST_USE_EVEX]=1; + xed_operand_bits[XED_OPERAND_ZEROING]=1; + xed_operand_bits[XED_OPERAND_LLRC]=2; + xed_operand_bits[XED_OPERAND_BCRC]=1; + xed_operand_bits[XED_OPERAND_REXRR]=1; + xed_operand_bits[XED_OPERAND_VEXDEST4]=1; + xed_operand_bits[XED_OPERAND_MASK]=3; + xed_operand_bits[XED_OPERAND_ROUNDC]=3; + xed_operand_bits[XED_OPERAND_SAE]=1; + xed_operand_bits[XED_OPERAND_NO_SCALE_DISP8]=1; + xed_operand_bits[XED_OPERAND_UBIT]=1; + xed_operand_bits[XED_OPERAND_WBNOINVD]=1; +} +xed_operand_ctype_enum_t xed_operand_get_ctype(xed_operand_enum_t opname) +{ + xed_assert(opname +#include +#include "xed-operand-element-type-enum.h" + +typedef struct { + const char* name; + xed_operand_element_type_enum_t value; +} name_table_xed_operand_element_type_enum_t; +static const name_table_xed_operand_element_type_enum_t name_array_xed_operand_element_type_enum_t[] = { +{"INVALID", XED_OPERAND_ELEMENT_TYPE_INVALID}, +{"UINT", XED_OPERAND_ELEMENT_TYPE_UINT}, +{"INT", XED_OPERAND_ELEMENT_TYPE_INT}, +{"SINGLE", XED_OPERAND_ELEMENT_TYPE_SINGLE}, +{"DOUBLE", XED_OPERAND_ELEMENT_TYPE_DOUBLE}, +{"LONGDOUBLE", XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE}, +{"LONGBCD", XED_OPERAND_ELEMENT_TYPE_LONGBCD}, +{"STRUCT", XED_OPERAND_ELEMENT_TYPE_STRUCT}, +{"VARIABLE", XED_OPERAND_ELEMENT_TYPE_VARIABLE}, +{"FLOAT16", XED_OPERAND_ELEMENT_TYPE_FLOAT16}, +{"BFLOAT16", XED_OPERAND_ELEMENT_TYPE_BFLOAT16}, +{"LAST", XED_OPERAND_ELEMENT_TYPE_LAST}, +{0, XED_OPERAND_ELEMENT_TYPE_LAST}, +}; + + +xed_operand_element_type_enum_t str2xed_operand_element_type_enum_t(const char* s) +{ + const name_table_xed_operand_element_type_enum_t* p = name_array_xed_operand_element_type_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_ELEMENT_TYPE_INVALID; +} + + +const char* xed_operand_element_type_enum_t2str(const xed_operand_element_type_enum_t p) +{ + xed_operand_element_type_enum_t type_idx = p; + if ( p > XED_OPERAND_ELEMENT_TYPE_LAST) type_idx = XED_OPERAND_ELEMENT_TYPE_LAST; + return name_array_xed_operand_element_type_enum_t[type_idx].name; +} + +xed_operand_element_type_enum_t xed_operand_element_type_enum_t_last(void) { + return XED_OPERAND_ELEMENT_TYPE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_ELEMENT_TYPE_INVALID: + case XED_OPERAND_ELEMENT_TYPE_UINT: + case XED_OPERAND_ELEMENT_TYPE_INT: + case XED_OPERAND_ELEMENT_TYPE_SINGLE: + case XED_OPERAND_ELEMENT_TYPE_DOUBLE: + case XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE: + case XED_OPERAND_ELEMENT_TYPE_LONGBCD: + case XED_OPERAND_ELEMENT_TYPE_STRUCT: + case XED_OPERAND_ELEMENT_TYPE_VARIABLE: + case XED_OPERAND_ELEMENT_TYPE_FLOAT16: + case XED_OPERAND_ELEMENT_TYPE_BFLOAT16: + case XED_OPERAND_ELEMENT_TYPE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-element-type-enum.h b/CodeVirtualizer/build/obj/xed-operand-element-type-enum.h new file mode 100644 index 0000000..d5c1ca4 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-element-type-enum.h @@ -0,0 +1,51 @@ +/// @file xed-operand-element-type-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ELEMENT_TYPE_ENUM_H) +# define XED_OPERAND_ELEMENT_TYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_ELEMENT_TYPE_INVALID_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_UINT_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_INT_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_SINGLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_DOUBLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_LONGBCD_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_STRUCT_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_VARIABLE_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_FLOAT16_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_BFLOAT16_DEFINED 1 +#define XED_OPERAND_ELEMENT_TYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_ELEMENT_TYPE_INVALID, + XED_OPERAND_ELEMENT_TYPE_UINT, ///< Unsigned integer + XED_OPERAND_ELEMENT_TYPE_INT, ///< Signed integer + XED_OPERAND_ELEMENT_TYPE_SINGLE, ///< 32b FP single precision + XED_OPERAND_ELEMENT_TYPE_DOUBLE, ///< 64b FP double precision + XED_OPERAND_ELEMENT_TYPE_LONGDOUBLE, ///< 80b FP x87 + XED_OPERAND_ELEMENT_TYPE_LONGBCD, ///< 80b decimal BCD + XED_OPERAND_ELEMENT_TYPE_STRUCT, ///< a structure of various fields + XED_OPERAND_ELEMENT_TYPE_VARIABLE, ///< depends on other fields in the instruction + XED_OPERAND_ELEMENT_TYPE_FLOAT16, ///< 16b floating point + XED_OPERAND_ELEMENT_TYPE_BFLOAT16, ///< bfloat16 floating point + XED_OPERAND_ELEMENT_TYPE_LAST +} xed_operand_element_type_enum_t; + +/// This converts strings to #xed_operand_element_type_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_element_type_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_type_enum_t str2xed_operand_element_type_enum_t(const char* s); +/// This converts strings to #xed_operand_element_type_enum_t types. +/// @param p An enumeration element of type xed_operand_element_type_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_element_type_enum_t2str(const xed_operand_element_type_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_element_type_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_type_enum_t xed_operand_element_type_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.c b/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.c new file mode 100644 index 0000000..81f9126 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.c @@ -0,0 +1,102 @@ +/// @file xed-operand-element-xtype-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-element-xtype-enum.h" + +typedef struct { + const char* name; + xed_operand_element_xtype_enum_t value; +} name_table_xed_operand_element_xtype_enum_t; +static const name_table_xed_operand_element_xtype_enum_t name_array_xed_operand_element_xtype_enum_t[] = { +{"INVALID", XED_OPERAND_XTYPE_INVALID}, +{"2F16", XED_OPERAND_XTYPE_2F16}, +{"B80", XED_OPERAND_XTYPE_B80}, +{"BF16", XED_OPERAND_XTYPE_BF16}, +{"F16", XED_OPERAND_XTYPE_F16}, +{"F32", XED_OPERAND_XTYPE_F32}, +{"F64", XED_OPERAND_XTYPE_F64}, +{"F80", XED_OPERAND_XTYPE_F80}, +{"I1", XED_OPERAND_XTYPE_I1}, +{"I16", XED_OPERAND_XTYPE_I16}, +{"I32", XED_OPERAND_XTYPE_I32}, +{"I64", XED_OPERAND_XTYPE_I64}, +{"I8", XED_OPERAND_XTYPE_I8}, +{"INT", XED_OPERAND_XTYPE_INT}, +{"STRUCT", XED_OPERAND_XTYPE_STRUCT}, +{"U128", XED_OPERAND_XTYPE_U128}, +{"U16", XED_OPERAND_XTYPE_U16}, +{"U256", XED_OPERAND_XTYPE_U256}, +{"U32", XED_OPERAND_XTYPE_U32}, +{"U64", XED_OPERAND_XTYPE_U64}, +{"U8", XED_OPERAND_XTYPE_U8}, +{"UINT", XED_OPERAND_XTYPE_UINT}, +{"VAR", XED_OPERAND_XTYPE_VAR}, +{"LAST", XED_OPERAND_XTYPE_LAST}, +{0, XED_OPERAND_XTYPE_LAST}, +}; + + +xed_operand_element_xtype_enum_t str2xed_operand_element_xtype_enum_t(const char* s) +{ + const name_table_xed_operand_element_xtype_enum_t* p = name_array_xed_operand_element_xtype_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_XTYPE_INVALID; +} + + +const char* xed_operand_element_xtype_enum_t2str(const xed_operand_element_xtype_enum_t p) +{ + xed_operand_element_xtype_enum_t type_idx = p; + if ( p > XED_OPERAND_XTYPE_LAST) type_idx = XED_OPERAND_XTYPE_LAST; + return name_array_xed_operand_element_xtype_enum_t[type_idx].name; +} + +xed_operand_element_xtype_enum_t xed_operand_element_xtype_enum_t_last(void) { + return XED_OPERAND_XTYPE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_XTYPE_INVALID: + case XED_OPERAND_XTYPE_2F16: + case XED_OPERAND_XTYPE_B80: + case XED_OPERAND_XTYPE_BF16: + case XED_OPERAND_XTYPE_F16: + case XED_OPERAND_XTYPE_F32: + case XED_OPERAND_XTYPE_F64: + case XED_OPERAND_XTYPE_F80: + case XED_OPERAND_XTYPE_I1: + case XED_OPERAND_XTYPE_I16: + case XED_OPERAND_XTYPE_I32: + case XED_OPERAND_XTYPE_I64: + case XED_OPERAND_XTYPE_I8: + case XED_OPERAND_XTYPE_INT: + case XED_OPERAND_XTYPE_STRUCT: + case XED_OPERAND_XTYPE_U128: + case XED_OPERAND_XTYPE_U16: + case XED_OPERAND_XTYPE_U256: + case XED_OPERAND_XTYPE_U32: + case XED_OPERAND_XTYPE_U64: + case XED_OPERAND_XTYPE_U8: + case XED_OPERAND_XTYPE_UINT: + case XED_OPERAND_XTYPE_VAR: + case XED_OPERAND_XTYPE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.h b/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.h new file mode 100644 index 0000000..2b62501 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.h @@ -0,0 +1,75 @@ +/// @file xed-operand-element-xtype-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ELEMENT_XTYPE_ENUM_H) +# define XED_OPERAND_ELEMENT_XTYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_XTYPE_INVALID_DEFINED 1 +#define XED_OPERAND_XTYPE_2F16_DEFINED 1 +#define XED_OPERAND_XTYPE_B80_DEFINED 1 +#define XED_OPERAND_XTYPE_BF16_DEFINED 1 +#define XED_OPERAND_XTYPE_F16_DEFINED 1 +#define XED_OPERAND_XTYPE_F32_DEFINED 1 +#define XED_OPERAND_XTYPE_F64_DEFINED 1 +#define XED_OPERAND_XTYPE_F80_DEFINED 1 +#define XED_OPERAND_XTYPE_I1_DEFINED 1 +#define XED_OPERAND_XTYPE_I16_DEFINED 1 +#define XED_OPERAND_XTYPE_I32_DEFINED 1 +#define XED_OPERAND_XTYPE_I64_DEFINED 1 +#define XED_OPERAND_XTYPE_I8_DEFINED 1 +#define XED_OPERAND_XTYPE_INT_DEFINED 1 +#define XED_OPERAND_XTYPE_STRUCT_DEFINED 1 +#define XED_OPERAND_XTYPE_U128_DEFINED 1 +#define XED_OPERAND_XTYPE_U16_DEFINED 1 +#define XED_OPERAND_XTYPE_U256_DEFINED 1 +#define XED_OPERAND_XTYPE_U32_DEFINED 1 +#define XED_OPERAND_XTYPE_U64_DEFINED 1 +#define XED_OPERAND_XTYPE_U8_DEFINED 1 +#define XED_OPERAND_XTYPE_UINT_DEFINED 1 +#define XED_OPERAND_XTYPE_VAR_DEFINED 1 +#define XED_OPERAND_XTYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_XTYPE_INVALID, + XED_OPERAND_XTYPE_2F16, + XED_OPERAND_XTYPE_B80, + XED_OPERAND_XTYPE_BF16, + XED_OPERAND_XTYPE_F16, + XED_OPERAND_XTYPE_F32, + XED_OPERAND_XTYPE_F64, + XED_OPERAND_XTYPE_F80, + XED_OPERAND_XTYPE_I1, + XED_OPERAND_XTYPE_I16, + XED_OPERAND_XTYPE_I32, + XED_OPERAND_XTYPE_I64, + XED_OPERAND_XTYPE_I8, + XED_OPERAND_XTYPE_INT, + XED_OPERAND_XTYPE_STRUCT, + XED_OPERAND_XTYPE_U128, + XED_OPERAND_XTYPE_U16, + XED_OPERAND_XTYPE_U256, + XED_OPERAND_XTYPE_U32, + XED_OPERAND_XTYPE_U64, + XED_OPERAND_XTYPE_U8, + XED_OPERAND_XTYPE_UINT, + XED_OPERAND_XTYPE_VAR, + XED_OPERAND_XTYPE_LAST +} xed_operand_element_xtype_enum_t; + +/// This converts strings to #xed_operand_element_xtype_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_element_xtype_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_xtype_enum_t str2xed_operand_element_xtype_enum_t(const char* s); +/// This converts strings to #xed_operand_element_xtype_enum_t types. +/// @param p An enumeration element of type xed_operand_element_xtype_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_element_xtype_enum_t2str(const xed_operand_element_xtype_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_element_xtype_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_element_xtype_enum_t xed_operand_element_xtype_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.txt b/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.txt new file mode 100644 index 0000000..75a2636 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-element-xtype-enum.txt @@ -0,0 +1,53 @@ +# @file xed-operand-element-xtype-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-operand-element-xtype-enum.c +hfn xed-operand-element-xtype-enum.h +typename xed_operand_element_xtype_enum_t +prefix XED_OPERAND_XTYPE_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +2F16 +B80 +BF16 +F16 +F32 +F64 +F80 +I1 +I16 +I32 +I64 +I8 +INT +STRUCT +U128 +U16 +U256 +U32 +U64 +U8 +UINT +VAR diff --git a/CodeVirtualizer/build/obj/xed-operand-enum.c b/CodeVirtualizer/build/obj/xed-operand-enum.c new file mode 100644 index 0000000..a9b9662 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-enum.c @@ -0,0 +1,310 @@ +/// @file xed-operand-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-enum.h" + +typedef struct { + const char* name; + xed_operand_enum_t value; +} name_table_xed_operand_enum_t; +static const name_table_xed_operand_enum_t name_array_xed_operand_enum_t[] = { +{"INVALID", XED_OPERAND_INVALID}, +{"AGEN", XED_OPERAND_AGEN}, +{"AMD3DNOW", XED_OPERAND_AMD3DNOW}, +{"ASZ", XED_OPERAND_ASZ}, +{"BASE0", XED_OPERAND_BASE0}, +{"BASE1", XED_OPERAND_BASE1}, +{"BCAST", XED_OPERAND_BCAST}, +{"BCRC", XED_OPERAND_BCRC}, +{"BRDISP_WIDTH", XED_OPERAND_BRDISP_WIDTH}, +{"CET", XED_OPERAND_CET}, +{"CHIP", XED_OPERAND_CHIP}, +{"CLDEMOTE", XED_OPERAND_CLDEMOTE}, +{"DEFAULT_SEG", XED_OPERAND_DEFAULT_SEG}, +{"DF32", XED_OPERAND_DF32}, +{"DF64", XED_OPERAND_DF64}, +{"DISP", XED_OPERAND_DISP}, +{"DISP_WIDTH", XED_OPERAND_DISP_WIDTH}, +{"DUMMY", XED_OPERAND_DUMMY}, +{"EASZ", XED_OPERAND_EASZ}, +{"ELEMENT_SIZE", XED_OPERAND_ELEMENT_SIZE}, +{"ENCODER_PREFERRED", XED_OPERAND_ENCODER_PREFERRED}, +{"ENCODE_FORCE", XED_OPERAND_ENCODE_FORCE}, +{"EOSZ", XED_OPERAND_EOSZ}, +{"ERROR", XED_OPERAND_ERROR}, +{"ESRC", XED_OPERAND_ESRC}, +{"FIRST_F2F3", XED_OPERAND_FIRST_F2F3}, +{"HAS_MODRM", XED_OPERAND_HAS_MODRM}, +{"HAS_SIB", XED_OPERAND_HAS_SIB}, +{"HINT", XED_OPERAND_HINT}, +{"ICLASS", XED_OPERAND_ICLASS}, +{"ILD_F2", XED_OPERAND_ILD_F2}, +{"ILD_F3", XED_OPERAND_ILD_F3}, +{"ILD_SEG", XED_OPERAND_ILD_SEG}, +{"IMM0", XED_OPERAND_IMM0}, +{"IMM0SIGNED", XED_OPERAND_IMM0SIGNED}, +{"IMM1", XED_OPERAND_IMM1}, +{"IMM1_BYTES", XED_OPERAND_IMM1_BYTES}, +{"IMM_WIDTH", XED_OPERAND_IMM_WIDTH}, +{"INDEX", XED_OPERAND_INDEX}, +{"LAST_F2F3", XED_OPERAND_LAST_F2F3}, +{"LLRC", XED_OPERAND_LLRC}, +{"LOCK", XED_OPERAND_LOCK}, +{"LZCNT", XED_OPERAND_LZCNT}, +{"MAP", XED_OPERAND_MAP}, +{"MASK", XED_OPERAND_MASK}, +{"MAX_BYTES", XED_OPERAND_MAX_BYTES}, +{"MEM0", XED_OPERAND_MEM0}, +{"MEM1", XED_OPERAND_MEM1}, +{"MEM_WIDTH", XED_OPERAND_MEM_WIDTH}, +{"MOD", XED_OPERAND_MOD}, +{"MODE", XED_OPERAND_MODE}, +{"MODEP5", XED_OPERAND_MODEP5}, +{"MODEP55C", XED_OPERAND_MODEP55C}, +{"MODE_FIRST_PREFIX", XED_OPERAND_MODE_FIRST_PREFIX}, +{"MODE_SHORT_UD0", XED_OPERAND_MODE_SHORT_UD0}, +{"MODRM_BYTE", XED_OPERAND_MODRM_BYTE}, +{"MPXMODE", XED_OPERAND_MPXMODE}, +{"MUST_USE_EVEX", XED_OPERAND_MUST_USE_EVEX}, +{"NEEDREX", XED_OPERAND_NEEDREX}, +{"NEED_MEMDISP", XED_OPERAND_NEED_MEMDISP}, +{"NEED_SIB", XED_OPERAND_NEED_SIB}, +{"NELEM", XED_OPERAND_NELEM}, +{"NOMINAL_OPCODE", XED_OPERAND_NOMINAL_OPCODE}, +{"NOREX", XED_OPERAND_NOREX}, +{"NO_SCALE_DISP8", XED_OPERAND_NO_SCALE_DISP8}, +{"NPREFIXES", XED_OPERAND_NPREFIXES}, +{"NREXES", XED_OPERAND_NREXES}, +{"NSEG_PREFIXES", XED_OPERAND_NSEG_PREFIXES}, +{"OSZ", XED_OPERAND_OSZ}, +{"OUTREG", XED_OPERAND_OUTREG}, +{"OUT_OF_BYTES", XED_OPERAND_OUT_OF_BYTES}, +{"P4", XED_OPERAND_P4}, +{"POS_DISP", XED_OPERAND_POS_DISP}, +{"POS_IMM", XED_OPERAND_POS_IMM}, +{"POS_IMM1", XED_OPERAND_POS_IMM1}, +{"POS_MODRM", XED_OPERAND_POS_MODRM}, +{"POS_NOMINAL_OPCODE", XED_OPERAND_POS_NOMINAL_OPCODE}, +{"POS_SIB", XED_OPERAND_POS_SIB}, +{"PREFIX66", XED_OPERAND_PREFIX66}, +{"PTR", XED_OPERAND_PTR}, +{"REALMODE", XED_OPERAND_REALMODE}, +{"REG", XED_OPERAND_REG}, +{"REG0", XED_OPERAND_REG0}, +{"REG1", XED_OPERAND_REG1}, +{"REG2", XED_OPERAND_REG2}, +{"REG3", XED_OPERAND_REG3}, +{"REG4", XED_OPERAND_REG4}, +{"REG5", XED_OPERAND_REG5}, +{"REG6", XED_OPERAND_REG6}, +{"REG7", XED_OPERAND_REG7}, +{"REG8", XED_OPERAND_REG8}, +{"REG9", XED_OPERAND_REG9}, +{"RELBR", XED_OPERAND_RELBR}, +{"REP", XED_OPERAND_REP}, +{"REX", XED_OPERAND_REX}, +{"REXB", XED_OPERAND_REXB}, +{"REXR", XED_OPERAND_REXR}, +{"REXRR", XED_OPERAND_REXRR}, +{"REXW", XED_OPERAND_REXW}, +{"REXX", XED_OPERAND_REXX}, +{"RM", XED_OPERAND_RM}, +{"ROUNDC", XED_OPERAND_ROUNDC}, +{"SAE", XED_OPERAND_SAE}, +{"SCALE", XED_OPERAND_SCALE}, +{"SEG0", XED_OPERAND_SEG0}, +{"SEG1", XED_OPERAND_SEG1}, +{"SEG_OVD", XED_OPERAND_SEG_OVD}, +{"SIBBASE", XED_OPERAND_SIBBASE}, +{"SIBINDEX", XED_OPERAND_SIBINDEX}, +{"SIBSCALE", XED_OPERAND_SIBSCALE}, +{"SMODE", XED_OPERAND_SMODE}, +{"SRM", XED_OPERAND_SRM}, +{"TZCNT", XED_OPERAND_TZCNT}, +{"UBIT", XED_OPERAND_UBIT}, +{"UIMM0", XED_OPERAND_UIMM0}, +{"UIMM1", XED_OPERAND_UIMM1}, +{"USING_DEFAULT_SEGMENT0", XED_OPERAND_USING_DEFAULT_SEGMENT0}, +{"USING_DEFAULT_SEGMENT1", XED_OPERAND_USING_DEFAULT_SEGMENT1}, +{"VEXDEST210", XED_OPERAND_VEXDEST210}, +{"VEXDEST3", XED_OPERAND_VEXDEST3}, +{"VEXDEST4", XED_OPERAND_VEXDEST4}, +{"VEXVALID", XED_OPERAND_VEXVALID}, +{"VEX_C4", XED_OPERAND_VEX_C4}, +{"VEX_PREFIX", XED_OPERAND_VEX_PREFIX}, +{"VL", XED_OPERAND_VL}, +{"WBNOINVD", XED_OPERAND_WBNOINVD}, +{"ZEROING", XED_OPERAND_ZEROING}, +{"LAST", XED_OPERAND_LAST}, +{0, XED_OPERAND_LAST}, +}; + + +xed_operand_enum_t str2xed_operand_enum_t(const char* s) +{ + const name_table_xed_operand_enum_t* p = name_array_xed_operand_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_INVALID; +} + + +const char* xed_operand_enum_t2str(const xed_operand_enum_t p) +{ + xed_operand_enum_t type_idx = p; + if ( p > XED_OPERAND_LAST) type_idx = XED_OPERAND_LAST; + return name_array_xed_operand_enum_t[type_idx].name; +} + +xed_operand_enum_t xed_operand_enum_t_last(void) { + return XED_OPERAND_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_INVALID: + case XED_OPERAND_AGEN: + case XED_OPERAND_AMD3DNOW: + case XED_OPERAND_ASZ: + case XED_OPERAND_BASE0: + case XED_OPERAND_BASE1: + case XED_OPERAND_BCAST: + case XED_OPERAND_BCRC: + case XED_OPERAND_BRDISP_WIDTH: + case XED_OPERAND_CET: + case XED_OPERAND_CHIP: + case XED_OPERAND_CLDEMOTE: + case XED_OPERAND_DEFAULT_SEG: + case XED_OPERAND_DF32: + case XED_OPERAND_DF64: + case XED_OPERAND_DISP: + case XED_OPERAND_DISP_WIDTH: + case XED_OPERAND_DUMMY: + case XED_OPERAND_EASZ: + case XED_OPERAND_ELEMENT_SIZE: + case XED_OPERAND_ENCODER_PREFERRED: + case XED_OPERAND_ENCODE_FORCE: + case XED_OPERAND_EOSZ: + case XED_OPERAND_ERROR: + case XED_OPERAND_ESRC: + case XED_OPERAND_FIRST_F2F3: + case XED_OPERAND_HAS_MODRM: + case XED_OPERAND_HAS_SIB: + case XED_OPERAND_HINT: + case XED_OPERAND_ICLASS: + case XED_OPERAND_ILD_F2: + case XED_OPERAND_ILD_F3: + case XED_OPERAND_ILD_SEG: + case XED_OPERAND_IMM0: + case XED_OPERAND_IMM0SIGNED: + case XED_OPERAND_IMM1: + case XED_OPERAND_IMM1_BYTES: + case XED_OPERAND_IMM_WIDTH: + case XED_OPERAND_INDEX: + case XED_OPERAND_LAST_F2F3: + case XED_OPERAND_LLRC: + case XED_OPERAND_LOCK: + case XED_OPERAND_LZCNT: + case XED_OPERAND_MAP: + case XED_OPERAND_MASK: + case XED_OPERAND_MAX_BYTES: + case XED_OPERAND_MEM0: + case XED_OPERAND_MEM1: + case XED_OPERAND_MEM_WIDTH: + case XED_OPERAND_MOD: + case XED_OPERAND_MODE: + case XED_OPERAND_MODEP5: + case XED_OPERAND_MODEP55C: + case XED_OPERAND_MODE_FIRST_PREFIX: + case XED_OPERAND_MODE_SHORT_UD0: + case XED_OPERAND_MODRM_BYTE: + case XED_OPERAND_MPXMODE: + case XED_OPERAND_MUST_USE_EVEX: + case XED_OPERAND_NEEDREX: + case XED_OPERAND_NEED_MEMDISP: + case XED_OPERAND_NEED_SIB: + case XED_OPERAND_NELEM: + case XED_OPERAND_NOMINAL_OPCODE: + case XED_OPERAND_NOREX: + case XED_OPERAND_NO_SCALE_DISP8: + case XED_OPERAND_NPREFIXES: + case XED_OPERAND_NREXES: + case XED_OPERAND_NSEG_PREFIXES: + case XED_OPERAND_OSZ: + case XED_OPERAND_OUTREG: + case XED_OPERAND_OUT_OF_BYTES: + case XED_OPERAND_P4: + case XED_OPERAND_POS_DISP: + case XED_OPERAND_POS_IMM: + case XED_OPERAND_POS_IMM1: + case XED_OPERAND_POS_MODRM: + case XED_OPERAND_POS_NOMINAL_OPCODE: + case XED_OPERAND_POS_SIB: + case XED_OPERAND_PREFIX66: + case XED_OPERAND_PTR: + case XED_OPERAND_REALMODE: + case XED_OPERAND_REG: + case XED_OPERAND_REG0: + case XED_OPERAND_REG1: + case XED_OPERAND_REG2: + case XED_OPERAND_REG3: + case XED_OPERAND_REG4: + case XED_OPERAND_REG5: + case XED_OPERAND_REG6: + case XED_OPERAND_REG7: + case XED_OPERAND_REG8: + case XED_OPERAND_REG9: + case XED_OPERAND_RELBR: + case XED_OPERAND_REP: + case XED_OPERAND_REX: + case XED_OPERAND_REXB: + case XED_OPERAND_REXR: + case XED_OPERAND_REXRR: + case XED_OPERAND_REXW: + case XED_OPERAND_REXX: + case XED_OPERAND_RM: + case XED_OPERAND_ROUNDC: + case XED_OPERAND_SAE: + case XED_OPERAND_SCALE: + case XED_OPERAND_SEG0: + case XED_OPERAND_SEG1: + case XED_OPERAND_SEG_OVD: + case XED_OPERAND_SIBBASE: + case XED_OPERAND_SIBINDEX: + case XED_OPERAND_SIBSCALE: + case XED_OPERAND_SMODE: + case XED_OPERAND_SRM: + case XED_OPERAND_TZCNT: + case XED_OPERAND_UBIT: + case XED_OPERAND_UIMM0: + case XED_OPERAND_UIMM1: + case XED_OPERAND_USING_DEFAULT_SEGMENT0: + case XED_OPERAND_USING_DEFAULT_SEGMENT1: + case XED_OPERAND_VEXDEST210: + case XED_OPERAND_VEXDEST3: + case XED_OPERAND_VEXDEST4: + case XED_OPERAND_VEXVALID: + case XED_OPERAND_VEX_C4: + case XED_OPERAND_VEX_PREFIX: + case XED_OPERAND_VL: + case XED_OPERAND_WBNOINVD: + case XED_OPERAND_ZEROING: + case XED_OPERAND_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-enum.h b/CodeVirtualizer/build/obj/xed-operand-enum.h new file mode 100644 index 0000000..880a247 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-enum.h @@ -0,0 +1,283 @@ +/// @file xed-operand-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_ENUM_H) +# define XED_OPERAND_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_INVALID_DEFINED 1 +#define XED_OPERAND_AGEN_DEFINED 1 +#define XED_OPERAND_AMD3DNOW_DEFINED 1 +#define XED_OPERAND_ASZ_DEFINED 1 +#define XED_OPERAND_BASE0_DEFINED 1 +#define XED_OPERAND_BASE1_DEFINED 1 +#define XED_OPERAND_BCAST_DEFINED 1 +#define XED_OPERAND_BCRC_DEFINED 1 +#define XED_OPERAND_BRDISP_WIDTH_DEFINED 1 +#define XED_OPERAND_CET_DEFINED 1 +#define XED_OPERAND_CHIP_DEFINED 1 +#define XED_OPERAND_CLDEMOTE_DEFINED 1 +#define XED_OPERAND_DEFAULT_SEG_DEFINED 1 +#define XED_OPERAND_DF32_DEFINED 1 +#define XED_OPERAND_DF64_DEFINED 1 +#define XED_OPERAND_DISP_DEFINED 1 +#define XED_OPERAND_DISP_WIDTH_DEFINED 1 +#define XED_OPERAND_DUMMY_DEFINED 1 +#define XED_OPERAND_EASZ_DEFINED 1 +#define XED_OPERAND_ELEMENT_SIZE_DEFINED 1 +#define XED_OPERAND_ENCODER_PREFERRED_DEFINED 1 +#define XED_OPERAND_ENCODE_FORCE_DEFINED 1 +#define XED_OPERAND_EOSZ_DEFINED 1 +#define XED_OPERAND_ERROR_DEFINED 1 +#define XED_OPERAND_ESRC_DEFINED 1 +#define XED_OPERAND_FIRST_F2F3_DEFINED 1 +#define XED_OPERAND_HAS_MODRM_DEFINED 1 +#define XED_OPERAND_HAS_SIB_DEFINED 1 +#define XED_OPERAND_HINT_DEFINED 1 +#define XED_OPERAND_ICLASS_DEFINED 1 +#define XED_OPERAND_ILD_F2_DEFINED 1 +#define XED_OPERAND_ILD_F3_DEFINED 1 +#define XED_OPERAND_ILD_SEG_DEFINED 1 +#define XED_OPERAND_IMM0_DEFINED 1 +#define XED_OPERAND_IMM0SIGNED_DEFINED 1 +#define XED_OPERAND_IMM1_DEFINED 1 +#define XED_OPERAND_IMM1_BYTES_DEFINED 1 +#define XED_OPERAND_IMM_WIDTH_DEFINED 1 +#define XED_OPERAND_INDEX_DEFINED 1 +#define XED_OPERAND_LAST_F2F3_DEFINED 1 +#define XED_OPERAND_LLRC_DEFINED 1 +#define XED_OPERAND_LOCK_DEFINED 1 +#define XED_OPERAND_LZCNT_DEFINED 1 +#define XED_OPERAND_MAP_DEFINED 1 +#define XED_OPERAND_MASK_DEFINED 1 +#define XED_OPERAND_MAX_BYTES_DEFINED 1 +#define XED_OPERAND_MEM0_DEFINED 1 +#define XED_OPERAND_MEM1_DEFINED 1 +#define XED_OPERAND_MEM_WIDTH_DEFINED 1 +#define XED_OPERAND_MOD_DEFINED 1 +#define XED_OPERAND_MODE_DEFINED 1 +#define XED_OPERAND_MODEP5_DEFINED 1 +#define XED_OPERAND_MODEP55C_DEFINED 1 +#define XED_OPERAND_MODE_FIRST_PREFIX_DEFINED 1 +#define XED_OPERAND_MODE_SHORT_UD0_DEFINED 1 +#define XED_OPERAND_MODRM_BYTE_DEFINED 1 +#define XED_OPERAND_MPXMODE_DEFINED 1 +#define XED_OPERAND_MUST_USE_EVEX_DEFINED 1 +#define XED_OPERAND_NEEDREX_DEFINED 1 +#define XED_OPERAND_NEED_MEMDISP_DEFINED 1 +#define XED_OPERAND_NEED_SIB_DEFINED 1 +#define XED_OPERAND_NELEM_DEFINED 1 +#define XED_OPERAND_NOMINAL_OPCODE_DEFINED 1 +#define XED_OPERAND_NOREX_DEFINED 1 +#define XED_OPERAND_NO_SCALE_DISP8_DEFINED 1 +#define XED_OPERAND_NPREFIXES_DEFINED 1 +#define XED_OPERAND_NREXES_DEFINED 1 +#define XED_OPERAND_NSEG_PREFIXES_DEFINED 1 +#define XED_OPERAND_OSZ_DEFINED 1 +#define XED_OPERAND_OUTREG_DEFINED 1 +#define XED_OPERAND_OUT_OF_BYTES_DEFINED 1 +#define XED_OPERAND_P4_DEFINED 1 +#define XED_OPERAND_POS_DISP_DEFINED 1 +#define XED_OPERAND_POS_IMM_DEFINED 1 +#define XED_OPERAND_POS_IMM1_DEFINED 1 +#define XED_OPERAND_POS_MODRM_DEFINED 1 +#define XED_OPERAND_POS_NOMINAL_OPCODE_DEFINED 1 +#define XED_OPERAND_POS_SIB_DEFINED 1 +#define XED_OPERAND_PREFIX66_DEFINED 1 +#define XED_OPERAND_PTR_DEFINED 1 +#define XED_OPERAND_REALMODE_DEFINED 1 +#define XED_OPERAND_REG_DEFINED 1 +#define XED_OPERAND_REG0_DEFINED 1 +#define XED_OPERAND_REG1_DEFINED 1 +#define XED_OPERAND_REG2_DEFINED 1 +#define XED_OPERAND_REG3_DEFINED 1 +#define XED_OPERAND_REG4_DEFINED 1 +#define XED_OPERAND_REG5_DEFINED 1 +#define XED_OPERAND_REG6_DEFINED 1 +#define XED_OPERAND_REG7_DEFINED 1 +#define XED_OPERAND_REG8_DEFINED 1 +#define XED_OPERAND_REG9_DEFINED 1 +#define XED_OPERAND_RELBR_DEFINED 1 +#define XED_OPERAND_REP_DEFINED 1 +#define XED_OPERAND_REX_DEFINED 1 +#define XED_OPERAND_REXB_DEFINED 1 +#define XED_OPERAND_REXR_DEFINED 1 +#define XED_OPERAND_REXRR_DEFINED 1 +#define XED_OPERAND_REXW_DEFINED 1 +#define XED_OPERAND_REXX_DEFINED 1 +#define XED_OPERAND_RM_DEFINED 1 +#define XED_OPERAND_ROUNDC_DEFINED 1 +#define XED_OPERAND_SAE_DEFINED 1 +#define XED_OPERAND_SCALE_DEFINED 1 +#define XED_OPERAND_SEG0_DEFINED 1 +#define XED_OPERAND_SEG1_DEFINED 1 +#define XED_OPERAND_SEG_OVD_DEFINED 1 +#define XED_OPERAND_SIBBASE_DEFINED 1 +#define XED_OPERAND_SIBINDEX_DEFINED 1 +#define XED_OPERAND_SIBSCALE_DEFINED 1 +#define XED_OPERAND_SMODE_DEFINED 1 +#define XED_OPERAND_SRM_DEFINED 1 +#define XED_OPERAND_TZCNT_DEFINED 1 +#define XED_OPERAND_UBIT_DEFINED 1 +#define XED_OPERAND_UIMM0_DEFINED 1 +#define XED_OPERAND_UIMM1_DEFINED 1 +#define XED_OPERAND_USING_DEFAULT_SEGMENT0_DEFINED 1 +#define XED_OPERAND_USING_DEFAULT_SEGMENT1_DEFINED 1 +#define XED_OPERAND_VEXDEST210_DEFINED 1 +#define XED_OPERAND_VEXDEST3_DEFINED 1 +#define XED_OPERAND_VEXDEST4_DEFINED 1 +#define XED_OPERAND_VEXVALID_DEFINED 1 +#define XED_OPERAND_VEX_C4_DEFINED 1 +#define XED_OPERAND_VEX_PREFIX_DEFINED 1 +#define XED_OPERAND_VL_DEFINED 1 +#define XED_OPERAND_WBNOINVD_DEFINED 1 +#define XED_OPERAND_ZEROING_DEFINED 1 +#define XED_OPERAND_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_INVALID, + XED_OPERAND_AGEN, + XED_OPERAND_AMD3DNOW, + XED_OPERAND_ASZ, + XED_OPERAND_BASE0, + XED_OPERAND_BASE1, + XED_OPERAND_BCAST, + XED_OPERAND_BCRC, + XED_OPERAND_BRDISP_WIDTH, + XED_OPERAND_CET, + XED_OPERAND_CHIP, + XED_OPERAND_CLDEMOTE, + XED_OPERAND_DEFAULT_SEG, + XED_OPERAND_DF32, + XED_OPERAND_DF64, + XED_OPERAND_DISP, + XED_OPERAND_DISP_WIDTH, + XED_OPERAND_DUMMY, + XED_OPERAND_EASZ, + XED_OPERAND_ELEMENT_SIZE, + XED_OPERAND_ENCODER_PREFERRED, + XED_OPERAND_ENCODE_FORCE, + XED_OPERAND_EOSZ, + XED_OPERAND_ERROR, + XED_OPERAND_ESRC, + XED_OPERAND_FIRST_F2F3, + XED_OPERAND_HAS_MODRM, + XED_OPERAND_HAS_SIB, + XED_OPERAND_HINT, + XED_OPERAND_ICLASS, + XED_OPERAND_ILD_F2, + XED_OPERAND_ILD_F3, + XED_OPERAND_ILD_SEG, + XED_OPERAND_IMM0, + XED_OPERAND_IMM0SIGNED, + XED_OPERAND_IMM1, + XED_OPERAND_IMM1_BYTES, + XED_OPERAND_IMM_WIDTH, + XED_OPERAND_INDEX, + XED_OPERAND_LAST_F2F3, + XED_OPERAND_LLRC, + XED_OPERAND_LOCK, + XED_OPERAND_LZCNT, + XED_OPERAND_MAP, + XED_OPERAND_MASK, + XED_OPERAND_MAX_BYTES, + XED_OPERAND_MEM0, + XED_OPERAND_MEM1, + XED_OPERAND_MEM_WIDTH, + XED_OPERAND_MOD, + XED_OPERAND_MODE, + XED_OPERAND_MODEP5, + XED_OPERAND_MODEP55C, + XED_OPERAND_MODE_FIRST_PREFIX, + XED_OPERAND_MODE_SHORT_UD0, + XED_OPERAND_MODRM_BYTE, + XED_OPERAND_MPXMODE, + XED_OPERAND_MUST_USE_EVEX, + XED_OPERAND_NEEDREX, + XED_OPERAND_NEED_MEMDISP, + XED_OPERAND_NEED_SIB, + XED_OPERAND_NELEM, + XED_OPERAND_NOMINAL_OPCODE, + XED_OPERAND_NOREX, + XED_OPERAND_NO_SCALE_DISP8, + XED_OPERAND_NPREFIXES, + XED_OPERAND_NREXES, + XED_OPERAND_NSEG_PREFIXES, + XED_OPERAND_OSZ, + XED_OPERAND_OUTREG, + XED_OPERAND_OUT_OF_BYTES, + XED_OPERAND_P4, + XED_OPERAND_POS_DISP, + XED_OPERAND_POS_IMM, + XED_OPERAND_POS_IMM1, + XED_OPERAND_POS_MODRM, + XED_OPERAND_POS_NOMINAL_OPCODE, + XED_OPERAND_POS_SIB, + XED_OPERAND_PREFIX66, + XED_OPERAND_PTR, + XED_OPERAND_REALMODE, + XED_OPERAND_REG, + XED_OPERAND_REG0, + XED_OPERAND_REG1, + XED_OPERAND_REG2, + XED_OPERAND_REG3, + XED_OPERAND_REG4, + XED_OPERAND_REG5, + XED_OPERAND_REG6, + XED_OPERAND_REG7, + XED_OPERAND_REG8, + XED_OPERAND_REG9, + XED_OPERAND_RELBR, + XED_OPERAND_REP, + XED_OPERAND_REX, + XED_OPERAND_REXB, + XED_OPERAND_REXR, + XED_OPERAND_REXRR, + XED_OPERAND_REXW, + XED_OPERAND_REXX, + XED_OPERAND_RM, + XED_OPERAND_ROUNDC, + XED_OPERAND_SAE, + XED_OPERAND_SCALE, + XED_OPERAND_SEG0, + XED_OPERAND_SEG1, + XED_OPERAND_SEG_OVD, + XED_OPERAND_SIBBASE, + XED_OPERAND_SIBINDEX, + XED_OPERAND_SIBSCALE, + XED_OPERAND_SMODE, + XED_OPERAND_SRM, + XED_OPERAND_TZCNT, + XED_OPERAND_UBIT, + XED_OPERAND_UIMM0, + XED_OPERAND_UIMM1, + XED_OPERAND_USING_DEFAULT_SEGMENT0, + XED_OPERAND_USING_DEFAULT_SEGMENT1, + XED_OPERAND_VEXDEST210, + XED_OPERAND_VEXDEST3, + XED_OPERAND_VEXDEST4, + XED_OPERAND_VEXVALID, + XED_OPERAND_VEX_C4, + XED_OPERAND_VEX_PREFIX, + XED_OPERAND_VL, + XED_OPERAND_WBNOINVD, + XED_OPERAND_ZEROING, + XED_OPERAND_LAST +} xed_operand_enum_t; + +/// This converts strings to #xed_operand_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_enum_t str2xed_operand_enum_t(const char* s); +/// This converts strings to #xed_operand_enum_t types. +/// @param p An enumeration element of type xed_operand_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_enum_t2str(const xed_operand_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_enum_t xed_operand_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-enum.txt b/CodeVirtualizer/build/obj/xed-operand-enum.txt new file mode 100644 index 0000000..9fb9390 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-enum.txt @@ -0,0 +1,157 @@ +# @file xed-operand-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-operand-enum.c +hfn xed-operand-enum.h +typename xed_operand_enum_t +prefix XED_OPERAND_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +AGEN +AMD3DNOW +ASZ +BASE0 +BASE1 +BCAST +BCRC +BRDISP_WIDTH +CET +CHIP +CLDEMOTE +DEFAULT_SEG +DF32 +DF64 +DISP +DISP_WIDTH +DUMMY +EASZ +ELEMENT_SIZE +ENCODER_PREFERRED +ENCODE_FORCE +EOSZ +ERROR +ESRC +FIRST_F2F3 +HAS_MODRM +HAS_SIB +HINT +ICLASS +ILD_F2 +ILD_F3 +ILD_SEG +IMM0 +IMM0SIGNED +IMM1 +IMM1_BYTES +IMM_WIDTH +INDEX +LAST_F2F3 +LLRC +LOCK +LZCNT +MAP +MASK +MAX_BYTES +MEM0 +MEM1 +MEM_WIDTH +MOD +MODE +MODEP5 +MODEP55C +MODE_FIRST_PREFIX +MODE_SHORT_UD0 +MODRM_BYTE +MPXMODE +MUST_USE_EVEX +NEEDREX +NEED_MEMDISP +NEED_SIB +NELEM +NOMINAL_OPCODE +NOREX +NO_SCALE_DISP8 +NPREFIXES +NREXES +NSEG_PREFIXES +OSZ +OUTREG +OUT_OF_BYTES +P4 +POS_DISP +POS_IMM +POS_IMM1 +POS_MODRM +POS_NOMINAL_OPCODE +POS_SIB +PREFIX66 +PTR +REALMODE +REG +REG0 +REG1 +REG2 +REG3 +REG4 +REG5 +REG6 +REG7 +REG8 +REG9 +RELBR +REP +REX +REXB +REXR +REXRR +REXW +REXX +RM +ROUNDC +SAE +SCALE +SEG0 +SEG1 +SEG_OVD +SIBBASE +SIBINDEX +SIBSCALE +SMODE +SRM +TZCNT +UBIT +UIMM0 +UIMM1 +USING_DEFAULT_SEGMENT0 +USING_DEFAULT_SEGMENT1 +VEXDEST210 +VEXDEST3 +VEXDEST4 +VEXVALID +VEX_C4 +VEX_PREFIX +VL +WBNOINVD +ZEROING diff --git a/CodeVirtualizer/build/obj/xed-operand-storage.h b/CodeVirtualizer/build/obj/xed-operand-storage.h new file mode 100644 index 0000000..9921b48 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-storage.h @@ -0,0 +1,158 @@ +/// @file xed-operand-storage.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_STORAGE_H) +# define XED_OPERAND_STORAGE_H +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-chip-enum.h" +#include "xed-error-enum.h" +#include "xed-iclass-enum.h" +#include "xed-reg-enum.h" +#include "xed-operand-element-type-enum.h" +typedef struct xed_operand_storage_s { + xed_uint8_t agen; + xed_uint8_t amd3dnow; + xed_uint8_t asz; + xed_uint8_t bcrc; + xed_uint8_t cet; + xed_uint8_t cldemote; + xed_uint8_t df32; + xed_uint8_t df64; + xed_uint8_t dummy; + xed_uint8_t encoder_preferred; + xed_uint8_t encode_force; + xed_uint8_t has_sib; + xed_uint8_t ild_f2; + xed_uint8_t ild_f3; + xed_uint8_t imm0; + xed_uint8_t imm0signed; + xed_uint8_t imm1; + xed_uint8_t lock; + xed_uint8_t lzcnt; + xed_uint8_t mem0; + xed_uint8_t mem1; + xed_uint8_t modep5; + xed_uint8_t modep55c; + xed_uint8_t mode_first_prefix; + xed_uint8_t mode_short_ud0; + xed_uint8_t mpxmode; + xed_uint8_t must_use_evex; + xed_uint8_t needrex; + xed_uint8_t need_sib; + xed_uint8_t norex; + xed_uint8_t no_scale_disp8; + xed_uint8_t osz; + xed_uint8_t out_of_bytes; + xed_uint8_t p4; + xed_uint8_t prefix66; + xed_uint8_t ptr; + xed_uint8_t realmode; + xed_uint8_t relbr; + xed_uint8_t rex; + xed_uint8_t rexb; + xed_uint8_t rexr; + xed_uint8_t rexrr; + xed_uint8_t rexw; + xed_uint8_t rexx; + xed_uint8_t sae; + xed_uint8_t tzcnt; + xed_uint8_t ubit; + xed_uint8_t using_default_segment0; + xed_uint8_t using_default_segment1; + xed_uint8_t vexdest3; + xed_uint8_t vexdest4; + xed_uint8_t vex_c4; + xed_uint8_t wbnoinvd; + xed_uint8_t zeroing; + xed_uint8_t default_seg; + xed_uint8_t easz; + xed_uint8_t eosz; + xed_uint8_t first_f2f3; + xed_uint8_t has_modrm; + xed_uint8_t last_f2f3; + xed_uint8_t llrc; + xed_uint8_t mod; + xed_uint8_t mode; + xed_uint8_t rep; + xed_uint8_t sibscale; + xed_uint8_t smode; + xed_uint8_t vex_prefix; + xed_uint8_t vl; + xed_uint8_t hint; + xed_uint8_t mask; + xed_uint8_t reg; + xed_uint8_t rm; + xed_uint8_t roundc; + xed_uint8_t seg_ovd; + xed_uint8_t sibbase; + xed_uint8_t sibindex; + xed_uint8_t srm; + xed_uint8_t vexdest210; + xed_uint8_t vexvalid; + xed_uint8_t error; + xed_uint8_t esrc; + xed_uint8_t map; + xed_uint8_t nelem; + xed_uint8_t scale; + xed_uint8_t bcast; + xed_uint8_t need_memdisp; + xed_uint8_t chip; + xed_uint8_t brdisp_width; + xed_uint8_t disp_width; + xed_uint8_t ild_seg; + xed_uint8_t imm1_bytes; + xed_uint8_t imm_width; + xed_uint8_t max_bytes; + xed_uint8_t modrm_byte; + xed_uint8_t nominal_opcode; + xed_uint8_t nprefixes; + xed_uint8_t nrexes; + xed_uint8_t nseg_prefixes; + xed_uint8_t pos_disp; + xed_uint8_t pos_imm; + xed_uint8_t pos_imm1; + xed_uint8_t pos_modrm; + xed_uint8_t pos_nominal_opcode; + xed_uint8_t pos_sib; + xed_uint8_t uimm1; + xed_uint16_t base0; + xed_uint16_t base1; + xed_uint16_t element_size; + xed_uint16_t index; + xed_uint16_t outreg; + xed_uint16_t reg0; + xed_uint16_t reg1; + xed_uint16_t reg2; + xed_uint16_t reg3; + xed_uint16_t reg4; + xed_uint16_t reg5; + xed_uint16_t reg6; + xed_uint16_t reg7; + xed_uint16_t reg8; + xed_uint16_t reg9; + xed_uint16_t seg0; + xed_uint16_t seg1; + xed_uint16_t iclass; + xed_uint16_t mem_width; + xed_uint64_t disp; + xed_uint64_t uimm0; +} xed_operand_storage_t; +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-type-enum.c b/CodeVirtualizer/build/obj/xed-operand-type-enum.c new file mode 100644 index 0000000..cc5d35a --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-type-enum.c @@ -0,0 +1,72 @@ +/// @file xed-operand-type-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-type-enum.h" + +typedef struct { + const char* name; + xed_operand_type_enum_t value; +} name_table_xed_operand_type_enum_t; +static const name_table_xed_operand_type_enum_t name_array_xed_operand_type_enum_t[] = { +{"INVALID", XED_OPERAND_TYPE_INVALID}, +{"ERROR", XED_OPERAND_TYPE_ERROR}, +{"IMM", XED_OPERAND_TYPE_IMM}, +{"IMM_CONST", XED_OPERAND_TYPE_IMM_CONST}, +{"NT_LOOKUP_FN", XED_OPERAND_TYPE_NT_LOOKUP_FN}, +{"NT_LOOKUP_FN2", XED_OPERAND_TYPE_NT_LOOKUP_FN2}, +{"NT_LOOKUP_FN4", XED_OPERAND_TYPE_NT_LOOKUP_FN4}, +{"REG", XED_OPERAND_TYPE_REG}, +{"LAST", XED_OPERAND_TYPE_LAST}, +{0, XED_OPERAND_TYPE_LAST}, +}; + + +xed_operand_type_enum_t str2xed_operand_type_enum_t(const char* s) +{ + const name_table_xed_operand_type_enum_t* p = name_array_xed_operand_type_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_TYPE_INVALID; +} + + +const char* xed_operand_type_enum_t2str(const xed_operand_type_enum_t p) +{ + xed_operand_type_enum_t type_idx = p; + if ( p > XED_OPERAND_TYPE_LAST) type_idx = XED_OPERAND_TYPE_LAST; + return name_array_xed_operand_type_enum_t[type_idx].name; +} + +xed_operand_type_enum_t xed_operand_type_enum_t_last(void) { + return XED_OPERAND_TYPE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_TYPE_INVALID: + case XED_OPERAND_TYPE_ERROR: + case XED_OPERAND_TYPE_IMM: + case XED_OPERAND_TYPE_IMM_CONST: + case XED_OPERAND_TYPE_NT_LOOKUP_FN: + case XED_OPERAND_TYPE_NT_LOOKUP_FN2: + case XED_OPERAND_TYPE_NT_LOOKUP_FN4: + case XED_OPERAND_TYPE_REG: + case XED_OPERAND_TYPE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-type-enum.h b/CodeVirtualizer/build/obj/xed-operand-type-enum.h new file mode 100644 index 0000000..bb8eb96 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-type-enum.h @@ -0,0 +1,45 @@ +/// @file xed-operand-type-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_TYPE_ENUM_H) +# define XED_OPERAND_TYPE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_TYPE_INVALID_DEFINED 1 +#define XED_OPERAND_TYPE_ERROR_DEFINED 1 +#define XED_OPERAND_TYPE_IMM_DEFINED 1 +#define XED_OPERAND_TYPE_IMM_CONST_DEFINED 1 +#define XED_OPERAND_TYPE_NT_LOOKUP_FN_DEFINED 1 +#define XED_OPERAND_TYPE_NT_LOOKUP_FN2_DEFINED 1 +#define XED_OPERAND_TYPE_NT_LOOKUP_FN4_DEFINED 1 +#define XED_OPERAND_TYPE_REG_DEFINED 1 +#define XED_OPERAND_TYPE_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_TYPE_INVALID, + XED_OPERAND_TYPE_ERROR, + XED_OPERAND_TYPE_IMM, + XED_OPERAND_TYPE_IMM_CONST, + XED_OPERAND_TYPE_NT_LOOKUP_FN, + XED_OPERAND_TYPE_NT_LOOKUP_FN2, + XED_OPERAND_TYPE_NT_LOOKUP_FN4, + XED_OPERAND_TYPE_REG, + XED_OPERAND_TYPE_LAST +} xed_operand_type_enum_t; + +/// This converts strings to #xed_operand_type_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_type_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_type_enum_t str2xed_operand_type_enum_t(const char* s); +/// This converts strings to #xed_operand_type_enum_t types. +/// @param p An enumeration element of type xed_operand_type_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_type_enum_t2str(const xed_operand_type_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_type_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_type_enum_t xed_operand_type_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-type-enum.txt b/CodeVirtualizer/build/obj/xed-operand-type-enum.txt new file mode 100644 index 0000000..da461d5 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-type-enum.txt @@ -0,0 +1,38 @@ +# @file xed-operand-type-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-operand-type-enum.c +hfn xed-operand-type-enum.h +typename xed_operand_type_enum_t +prefix XED_OPERAND_TYPE_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +ERROR +IMM +IMM_CONST +NT_LOOKUP_FN +NT_LOOKUP_FN2 +NT_LOOKUP_FN4 +REG diff --git a/CodeVirtualizer/build/obj/xed-operand-visibility-enum.c b/CodeVirtualizer/build/obj/xed-operand-visibility-enum.c new file mode 100644 index 0000000..9d0cd85 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-visibility-enum.c @@ -0,0 +1,64 @@ +/// @file xed-operand-visibility-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-visibility-enum.h" + +typedef struct { + const char* name; + xed_operand_visibility_enum_t value; +} name_table_xed_operand_visibility_enum_t; +static const name_table_xed_operand_visibility_enum_t name_array_xed_operand_visibility_enum_t[] = { +{"INVALID", XED_OPVIS_INVALID}, +{"EXPLICIT", XED_OPVIS_EXPLICIT}, +{"IMPLICIT", XED_OPVIS_IMPLICIT}, +{"SUPPRESSED", XED_OPVIS_SUPPRESSED}, +{"LAST", XED_OPVIS_LAST}, +{0, XED_OPVIS_LAST}, +}; + + +xed_operand_visibility_enum_t str2xed_operand_visibility_enum_t(const char* s) +{ + const name_table_xed_operand_visibility_enum_t* p = name_array_xed_operand_visibility_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPVIS_INVALID; +} + + +const char* xed_operand_visibility_enum_t2str(const xed_operand_visibility_enum_t p) +{ + xed_operand_visibility_enum_t type_idx = p; + if ( p > XED_OPVIS_LAST) type_idx = XED_OPVIS_LAST; + return name_array_xed_operand_visibility_enum_t[type_idx].name; +} + +xed_operand_visibility_enum_t xed_operand_visibility_enum_t_last(void) { + return XED_OPVIS_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPVIS_INVALID: + case XED_OPVIS_EXPLICIT: + case XED_OPVIS_IMPLICIT: + case XED_OPVIS_SUPPRESSED: + case XED_OPVIS_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-visibility-enum.h b/CodeVirtualizer/build/obj/xed-operand-visibility-enum.h new file mode 100644 index 0000000..03ad87d --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-visibility-enum.h @@ -0,0 +1,37 @@ +/// @file xed-operand-visibility-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_VISIBILITY_ENUM_H) +# define XED_OPERAND_VISIBILITY_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPVIS_INVALID_DEFINED 1 +#define XED_OPVIS_EXPLICIT_DEFINED 1 +#define XED_OPVIS_IMPLICIT_DEFINED 1 +#define XED_OPVIS_SUPPRESSED_DEFINED 1 +#define XED_OPVIS_LAST_DEFINED 1 +typedef enum { + XED_OPVIS_INVALID, + XED_OPVIS_EXPLICIT, ///< Shows up in operand encoding + XED_OPVIS_IMPLICIT, ///< Part of the opcode, but listed as an operand + XED_OPVIS_SUPPRESSED, ///< Part of the opcode, but not typically listed as an operand + XED_OPVIS_LAST +} xed_operand_visibility_enum_t; + +/// This converts strings to #xed_operand_visibility_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_visibility_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_visibility_enum_t str2xed_operand_visibility_enum_t(const char* s); +/// This converts strings to #xed_operand_visibility_enum_t types. +/// @param p An enumeration element of type xed_operand_visibility_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_visibility_enum_t2str(const xed_operand_visibility_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_visibility_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_visibility_enum_t xed_operand_visibility_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-width-enum.c b/CodeVirtualizer/build/obj/xed-operand-width-enum.c new file mode 100644 index 0000000..a7b0b82 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-width-enum.c @@ -0,0 +1,310 @@ +/// @file xed-operand-width-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-operand-width-enum.h" + +typedef struct { + const char* name; + xed_operand_width_enum_t value; +} name_table_xed_operand_width_enum_t; +static const name_table_xed_operand_width_enum_t name_array_xed_operand_width_enum_t[] = { +{"INVALID", XED_OPERAND_WIDTH_INVALID}, +{"ASZ", XED_OPERAND_WIDTH_ASZ}, +{"SSZ", XED_OPERAND_WIDTH_SSZ}, +{"PSEUDO", XED_OPERAND_WIDTH_PSEUDO}, +{"PSEUDOX87", XED_OPERAND_WIDTH_PSEUDOX87}, +{"A16", XED_OPERAND_WIDTH_A16}, +{"A32", XED_OPERAND_WIDTH_A32}, +{"B", XED_OPERAND_WIDTH_B}, +{"D", XED_OPERAND_WIDTH_D}, +{"I8", XED_OPERAND_WIDTH_I8}, +{"U8", XED_OPERAND_WIDTH_U8}, +{"I16", XED_OPERAND_WIDTH_I16}, +{"U16", XED_OPERAND_WIDTH_U16}, +{"I32", XED_OPERAND_WIDTH_I32}, +{"U32", XED_OPERAND_WIDTH_U32}, +{"I64", XED_OPERAND_WIDTH_I64}, +{"U64", XED_OPERAND_WIDTH_U64}, +{"F16", XED_OPERAND_WIDTH_F16}, +{"F32", XED_OPERAND_WIDTH_F32}, +{"F64", XED_OPERAND_WIDTH_F64}, +{"DQ", XED_OPERAND_WIDTH_DQ}, +{"XUB", XED_OPERAND_WIDTH_XUB}, +{"XUW", XED_OPERAND_WIDTH_XUW}, +{"XUD", XED_OPERAND_WIDTH_XUD}, +{"XUQ", XED_OPERAND_WIDTH_XUQ}, +{"X128", XED_OPERAND_WIDTH_X128}, +{"XB", XED_OPERAND_WIDTH_XB}, +{"XW", XED_OPERAND_WIDTH_XW}, +{"XD", XED_OPERAND_WIDTH_XD}, +{"XQ", XED_OPERAND_WIDTH_XQ}, +{"ZB", XED_OPERAND_WIDTH_ZB}, +{"ZW", XED_OPERAND_WIDTH_ZW}, +{"ZD", XED_OPERAND_WIDTH_ZD}, +{"ZQ", XED_OPERAND_WIDTH_ZQ}, +{"MB", XED_OPERAND_WIDTH_MB}, +{"MW", XED_OPERAND_WIDTH_MW}, +{"MD", XED_OPERAND_WIDTH_MD}, +{"MQ", XED_OPERAND_WIDTH_MQ}, +{"M64INT", XED_OPERAND_WIDTH_M64INT}, +{"M64REAL", XED_OPERAND_WIDTH_M64REAL}, +{"MEM108", XED_OPERAND_WIDTH_MEM108}, +{"MEM14", XED_OPERAND_WIDTH_MEM14}, +{"MEM16", XED_OPERAND_WIDTH_MEM16}, +{"MEM16INT", XED_OPERAND_WIDTH_MEM16INT}, +{"MEM28", XED_OPERAND_WIDTH_MEM28}, +{"MEM32INT", XED_OPERAND_WIDTH_MEM32INT}, +{"MEM32REAL", XED_OPERAND_WIDTH_MEM32REAL}, +{"MEM80DEC", XED_OPERAND_WIDTH_MEM80DEC}, +{"MEM80REAL", XED_OPERAND_WIDTH_MEM80REAL}, +{"F80", XED_OPERAND_WIDTH_F80}, +{"MEM94", XED_OPERAND_WIDTH_MEM94}, +{"MFPXENV", XED_OPERAND_WIDTH_MFPXENV}, +{"MXSAVE", XED_OPERAND_WIDTH_MXSAVE}, +{"MPREFETCH", XED_OPERAND_WIDTH_MPREFETCH}, +{"P", XED_OPERAND_WIDTH_P}, +{"P2", XED_OPERAND_WIDTH_P2}, +{"PD", XED_OPERAND_WIDTH_PD}, +{"PS", XED_OPERAND_WIDTH_PS}, +{"PI", XED_OPERAND_WIDTH_PI}, +{"Q", XED_OPERAND_WIDTH_Q}, +{"S", XED_OPERAND_WIDTH_S}, +{"S64", XED_OPERAND_WIDTH_S64}, +{"SD", XED_OPERAND_WIDTH_SD}, +{"SI", XED_OPERAND_WIDTH_SI}, +{"SS", XED_OPERAND_WIDTH_SS}, +{"V", XED_OPERAND_WIDTH_V}, +{"Y", XED_OPERAND_WIDTH_Y}, +{"W", XED_OPERAND_WIDTH_W}, +{"Z", XED_OPERAND_WIDTH_Z}, +{"SPW8", XED_OPERAND_WIDTH_SPW8}, +{"SPW", XED_OPERAND_WIDTH_SPW}, +{"SPW5", XED_OPERAND_WIDTH_SPW5}, +{"SPW3", XED_OPERAND_WIDTH_SPW3}, +{"SPW2", XED_OPERAND_WIDTH_SPW2}, +{"I1", XED_OPERAND_WIDTH_I1}, +{"I2", XED_OPERAND_WIDTH_I2}, +{"I3", XED_OPERAND_WIDTH_I3}, +{"I4", XED_OPERAND_WIDTH_I4}, +{"I5", XED_OPERAND_WIDTH_I5}, +{"I6", XED_OPERAND_WIDTH_I6}, +{"I7", XED_OPERAND_WIDTH_I7}, +{"VAR", XED_OPERAND_WIDTH_VAR}, +{"BND32", XED_OPERAND_WIDTH_BND32}, +{"BND64", XED_OPERAND_WIDTH_BND64}, +{"PMMSZ16", XED_OPERAND_WIDTH_PMMSZ16}, +{"PMMSZ32", XED_OPERAND_WIDTH_PMMSZ32}, +{"QQ", XED_OPERAND_WIDTH_QQ}, +{"YUB", XED_OPERAND_WIDTH_YUB}, +{"YUW", XED_OPERAND_WIDTH_YUW}, +{"YUD", XED_OPERAND_WIDTH_YUD}, +{"YUQ", XED_OPERAND_WIDTH_YUQ}, +{"Y128", XED_OPERAND_WIDTH_Y128}, +{"YB", XED_OPERAND_WIDTH_YB}, +{"YW", XED_OPERAND_WIDTH_YW}, +{"YD", XED_OPERAND_WIDTH_YD}, +{"YQ", XED_OPERAND_WIDTH_YQ}, +{"YPS", XED_OPERAND_WIDTH_YPS}, +{"YPD", XED_OPERAND_WIDTH_YPD}, +{"ZBF16", XED_OPERAND_WIDTH_ZBF16}, +{"VV", XED_OPERAND_WIDTH_VV}, +{"ZV", XED_OPERAND_WIDTH_ZV}, +{"WRD", XED_OPERAND_WIDTH_WRD}, +{"MSKW", XED_OPERAND_WIDTH_MSKW}, +{"ZMSKW", XED_OPERAND_WIDTH_ZMSKW}, +{"ZF32", XED_OPERAND_WIDTH_ZF32}, +{"ZF64", XED_OPERAND_WIDTH_ZF64}, +{"ZUB", XED_OPERAND_WIDTH_ZUB}, +{"ZUW", XED_OPERAND_WIDTH_ZUW}, +{"ZUD", XED_OPERAND_WIDTH_ZUD}, +{"ZUQ", XED_OPERAND_WIDTH_ZUQ}, +{"ZI8", XED_OPERAND_WIDTH_ZI8}, +{"ZI16", XED_OPERAND_WIDTH_ZI16}, +{"ZI32", XED_OPERAND_WIDTH_ZI32}, +{"ZI64", XED_OPERAND_WIDTH_ZI64}, +{"ZU8", XED_OPERAND_WIDTH_ZU8}, +{"ZU16", XED_OPERAND_WIDTH_ZU16}, +{"ZU32", XED_OPERAND_WIDTH_ZU32}, +{"ZU64", XED_OPERAND_WIDTH_ZU64}, +{"ZU128", XED_OPERAND_WIDTH_ZU128}, +{"M384", XED_OPERAND_WIDTH_M384}, +{"M512", XED_OPERAND_WIDTH_M512}, +{"PTR", XED_OPERAND_WIDTH_PTR}, +{"TMEMROW", XED_OPERAND_WIDTH_TMEMROW}, +{"TMEMCOL", XED_OPERAND_WIDTH_TMEMCOL}, +{"TV", XED_OPERAND_WIDTH_TV}, +{"ZF16", XED_OPERAND_WIDTH_ZF16}, +{"Z2F16", XED_OPERAND_WIDTH_Z2F16}, +{"LAST", XED_OPERAND_WIDTH_LAST}, +{0, XED_OPERAND_WIDTH_LAST}, +}; + + +xed_operand_width_enum_t str2xed_operand_width_enum_t(const char* s) +{ + const name_table_xed_operand_width_enum_t* p = name_array_xed_operand_width_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_OPERAND_WIDTH_INVALID; +} + + +const char* xed_operand_width_enum_t2str(const xed_operand_width_enum_t p) +{ + xed_operand_width_enum_t type_idx = p; + if ( p > XED_OPERAND_WIDTH_LAST) type_idx = XED_OPERAND_WIDTH_LAST; + return name_array_xed_operand_width_enum_t[type_idx].name; +} + +xed_operand_width_enum_t xed_operand_width_enum_t_last(void) { + return XED_OPERAND_WIDTH_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_OPERAND_WIDTH_INVALID: + case XED_OPERAND_WIDTH_ASZ: + case XED_OPERAND_WIDTH_SSZ: + case XED_OPERAND_WIDTH_PSEUDO: + case XED_OPERAND_WIDTH_PSEUDOX87: + case XED_OPERAND_WIDTH_A16: + case XED_OPERAND_WIDTH_A32: + case XED_OPERAND_WIDTH_B: + case XED_OPERAND_WIDTH_D: + case XED_OPERAND_WIDTH_I8: + case XED_OPERAND_WIDTH_U8: + case XED_OPERAND_WIDTH_I16: + case XED_OPERAND_WIDTH_U16: + case XED_OPERAND_WIDTH_I32: + case XED_OPERAND_WIDTH_U32: + case XED_OPERAND_WIDTH_I64: + case XED_OPERAND_WIDTH_U64: + case XED_OPERAND_WIDTH_F16: + case XED_OPERAND_WIDTH_F32: + case XED_OPERAND_WIDTH_F64: + case XED_OPERAND_WIDTH_DQ: + case XED_OPERAND_WIDTH_XUB: + case XED_OPERAND_WIDTH_XUW: + case XED_OPERAND_WIDTH_XUD: + case XED_OPERAND_WIDTH_XUQ: + case XED_OPERAND_WIDTH_X128: + case XED_OPERAND_WIDTH_XB: + case XED_OPERAND_WIDTH_XW: + case XED_OPERAND_WIDTH_XD: + case XED_OPERAND_WIDTH_XQ: + case XED_OPERAND_WIDTH_ZB: + case XED_OPERAND_WIDTH_ZW: + case XED_OPERAND_WIDTH_ZD: + case XED_OPERAND_WIDTH_ZQ: + case XED_OPERAND_WIDTH_MB: + case XED_OPERAND_WIDTH_MW: + case XED_OPERAND_WIDTH_MD: + case XED_OPERAND_WIDTH_MQ: + case XED_OPERAND_WIDTH_M64INT: + case XED_OPERAND_WIDTH_M64REAL: + case XED_OPERAND_WIDTH_MEM108: + case XED_OPERAND_WIDTH_MEM14: + case XED_OPERAND_WIDTH_MEM16: + case XED_OPERAND_WIDTH_MEM16INT: + case XED_OPERAND_WIDTH_MEM28: + case XED_OPERAND_WIDTH_MEM32INT: + case XED_OPERAND_WIDTH_MEM32REAL: + case XED_OPERAND_WIDTH_MEM80DEC: + case XED_OPERAND_WIDTH_MEM80REAL: + case XED_OPERAND_WIDTH_F80: + case XED_OPERAND_WIDTH_MEM94: + case XED_OPERAND_WIDTH_MFPXENV: + case XED_OPERAND_WIDTH_MXSAVE: + case XED_OPERAND_WIDTH_MPREFETCH: + case XED_OPERAND_WIDTH_P: + case XED_OPERAND_WIDTH_P2: + case XED_OPERAND_WIDTH_PD: + case XED_OPERAND_WIDTH_PS: + case XED_OPERAND_WIDTH_PI: + case XED_OPERAND_WIDTH_Q: + case XED_OPERAND_WIDTH_S: + case XED_OPERAND_WIDTH_S64: + case XED_OPERAND_WIDTH_SD: + case XED_OPERAND_WIDTH_SI: + case XED_OPERAND_WIDTH_SS: + case XED_OPERAND_WIDTH_V: + case XED_OPERAND_WIDTH_Y: + case XED_OPERAND_WIDTH_W: + case XED_OPERAND_WIDTH_Z: + case XED_OPERAND_WIDTH_SPW8: + case XED_OPERAND_WIDTH_SPW: + case XED_OPERAND_WIDTH_SPW5: + case XED_OPERAND_WIDTH_SPW3: + case XED_OPERAND_WIDTH_SPW2: + case XED_OPERAND_WIDTH_I1: + case XED_OPERAND_WIDTH_I2: + case XED_OPERAND_WIDTH_I3: + case XED_OPERAND_WIDTH_I4: + case XED_OPERAND_WIDTH_I5: + case XED_OPERAND_WIDTH_I6: + case XED_OPERAND_WIDTH_I7: + case XED_OPERAND_WIDTH_VAR: + case XED_OPERAND_WIDTH_BND32: + case XED_OPERAND_WIDTH_BND64: + case XED_OPERAND_WIDTH_PMMSZ16: + case XED_OPERAND_WIDTH_PMMSZ32: + case XED_OPERAND_WIDTH_QQ: + case XED_OPERAND_WIDTH_YUB: + case XED_OPERAND_WIDTH_YUW: + case XED_OPERAND_WIDTH_YUD: + case XED_OPERAND_WIDTH_YUQ: + case XED_OPERAND_WIDTH_Y128: + case XED_OPERAND_WIDTH_YB: + case XED_OPERAND_WIDTH_YW: + case XED_OPERAND_WIDTH_YD: + case XED_OPERAND_WIDTH_YQ: + case XED_OPERAND_WIDTH_YPS: + case XED_OPERAND_WIDTH_YPD: + case XED_OPERAND_WIDTH_ZBF16: + case XED_OPERAND_WIDTH_VV: + case XED_OPERAND_WIDTH_ZV: + case XED_OPERAND_WIDTH_WRD: + case XED_OPERAND_WIDTH_MSKW: + case XED_OPERAND_WIDTH_ZMSKW: + case XED_OPERAND_WIDTH_ZF32: + case XED_OPERAND_WIDTH_ZF64: + case XED_OPERAND_WIDTH_ZUB: + case XED_OPERAND_WIDTH_ZUW: + case XED_OPERAND_WIDTH_ZUD: + case XED_OPERAND_WIDTH_ZUQ: + case XED_OPERAND_WIDTH_ZI8: + case XED_OPERAND_WIDTH_ZI16: + case XED_OPERAND_WIDTH_ZI32: + case XED_OPERAND_WIDTH_ZI64: + case XED_OPERAND_WIDTH_ZU8: + case XED_OPERAND_WIDTH_ZU16: + case XED_OPERAND_WIDTH_ZU32: + case XED_OPERAND_WIDTH_ZU64: + case XED_OPERAND_WIDTH_ZU128: + case XED_OPERAND_WIDTH_M384: + case XED_OPERAND_WIDTH_M512: + case XED_OPERAND_WIDTH_PTR: + case XED_OPERAND_WIDTH_TMEMROW: + case XED_OPERAND_WIDTH_TMEMCOL: + case XED_OPERAND_WIDTH_TV: + case XED_OPERAND_WIDTH_ZF16: + case XED_OPERAND_WIDTH_Z2F16: + case XED_OPERAND_WIDTH_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-operand-width-enum.h b/CodeVirtualizer/build/obj/xed-operand-width-enum.h new file mode 100644 index 0000000..ff65f96 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-width-enum.h @@ -0,0 +1,283 @@ +/// @file xed-operand-width-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_OPERAND_WIDTH_ENUM_H) +# define XED_OPERAND_WIDTH_ENUM_H +#include "xed-common-hdrs.h" +#define XED_OPERAND_WIDTH_INVALID_DEFINED 1 +#define XED_OPERAND_WIDTH_ASZ_DEFINED 1 +#define XED_OPERAND_WIDTH_SSZ_DEFINED 1 +#define XED_OPERAND_WIDTH_PSEUDO_DEFINED 1 +#define XED_OPERAND_WIDTH_PSEUDOX87_DEFINED 1 +#define XED_OPERAND_WIDTH_A16_DEFINED 1 +#define XED_OPERAND_WIDTH_A32_DEFINED 1 +#define XED_OPERAND_WIDTH_B_DEFINED 1 +#define XED_OPERAND_WIDTH_D_DEFINED 1 +#define XED_OPERAND_WIDTH_I8_DEFINED 1 +#define XED_OPERAND_WIDTH_U8_DEFINED 1 +#define XED_OPERAND_WIDTH_I16_DEFINED 1 +#define XED_OPERAND_WIDTH_U16_DEFINED 1 +#define XED_OPERAND_WIDTH_I32_DEFINED 1 +#define XED_OPERAND_WIDTH_U32_DEFINED 1 +#define XED_OPERAND_WIDTH_I64_DEFINED 1 +#define XED_OPERAND_WIDTH_U64_DEFINED 1 +#define XED_OPERAND_WIDTH_F16_DEFINED 1 +#define XED_OPERAND_WIDTH_F32_DEFINED 1 +#define XED_OPERAND_WIDTH_F64_DEFINED 1 +#define XED_OPERAND_WIDTH_DQ_DEFINED 1 +#define XED_OPERAND_WIDTH_XUB_DEFINED 1 +#define XED_OPERAND_WIDTH_XUW_DEFINED 1 +#define XED_OPERAND_WIDTH_XUD_DEFINED 1 +#define XED_OPERAND_WIDTH_XUQ_DEFINED 1 +#define XED_OPERAND_WIDTH_X128_DEFINED 1 +#define XED_OPERAND_WIDTH_XB_DEFINED 1 +#define XED_OPERAND_WIDTH_XW_DEFINED 1 +#define XED_OPERAND_WIDTH_XD_DEFINED 1 +#define XED_OPERAND_WIDTH_XQ_DEFINED 1 +#define XED_OPERAND_WIDTH_ZB_DEFINED 1 +#define XED_OPERAND_WIDTH_ZW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZD_DEFINED 1 +#define XED_OPERAND_WIDTH_ZQ_DEFINED 1 +#define XED_OPERAND_WIDTH_MB_DEFINED 1 +#define XED_OPERAND_WIDTH_MW_DEFINED 1 +#define XED_OPERAND_WIDTH_MD_DEFINED 1 +#define XED_OPERAND_WIDTH_MQ_DEFINED 1 +#define XED_OPERAND_WIDTH_M64INT_DEFINED 1 +#define XED_OPERAND_WIDTH_M64REAL_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM108_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM14_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM16_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM16INT_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM28_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM32INT_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM32REAL_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM80DEC_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM80REAL_DEFINED 1 +#define XED_OPERAND_WIDTH_F80_DEFINED 1 +#define XED_OPERAND_WIDTH_MEM94_DEFINED 1 +#define XED_OPERAND_WIDTH_MFPXENV_DEFINED 1 +#define XED_OPERAND_WIDTH_MXSAVE_DEFINED 1 +#define XED_OPERAND_WIDTH_MPREFETCH_DEFINED 1 +#define XED_OPERAND_WIDTH_P_DEFINED 1 +#define XED_OPERAND_WIDTH_P2_DEFINED 1 +#define XED_OPERAND_WIDTH_PD_DEFINED 1 +#define XED_OPERAND_WIDTH_PS_DEFINED 1 +#define XED_OPERAND_WIDTH_PI_DEFINED 1 +#define XED_OPERAND_WIDTH_Q_DEFINED 1 +#define XED_OPERAND_WIDTH_S_DEFINED 1 +#define XED_OPERAND_WIDTH_S64_DEFINED 1 +#define XED_OPERAND_WIDTH_SD_DEFINED 1 +#define XED_OPERAND_WIDTH_SI_DEFINED 1 +#define XED_OPERAND_WIDTH_SS_DEFINED 1 +#define XED_OPERAND_WIDTH_V_DEFINED 1 +#define XED_OPERAND_WIDTH_Y_DEFINED 1 +#define XED_OPERAND_WIDTH_W_DEFINED 1 +#define XED_OPERAND_WIDTH_Z_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW8_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW5_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW3_DEFINED 1 +#define XED_OPERAND_WIDTH_SPW2_DEFINED 1 +#define XED_OPERAND_WIDTH_I1_DEFINED 1 +#define XED_OPERAND_WIDTH_I2_DEFINED 1 +#define XED_OPERAND_WIDTH_I3_DEFINED 1 +#define XED_OPERAND_WIDTH_I4_DEFINED 1 +#define XED_OPERAND_WIDTH_I5_DEFINED 1 +#define XED_OPERAND_WIDTH_I6_DEFINED 1 +#define XED_OPERAND_WIDTH_I7_DEFINED 1 +#define XED_OPERAND_WIDTH_VAR_DEFINED 1 +#define XED_OPERAND_WIDTH_BND32_DEFINED 1 +#define XED_OPERAND_WIDTH_BND64_DEFINED 1 +#define XED_OPERAND_WIDTH_PMMSZ16_DEFINED 1 +#define XED_OPERAND_WIDTH_PMMSZ32_DEFINED 1 +#define XED_OPERAND_WIDTH_QQ_DEFINED 1 +#define XED_OPERAND_WIDTH_YUB_DEFINED 1 +#define XED_OPERAND_WIDTH_YUW_DEFINED 1 +#define XED_OPERAND_WIDTH_YUD_DEFINED 1 +#define XED_OPERAND_WIDTH_YUQ_DEFINED 1 +#define XED_OPERAND_WIDTH_Y128_DEFINED 1 +#define XED_OPERAND_WIDTH_YB_DEFINED 1 +#define XED_OPERAND_WIDTH_YW_DEFINED 1 +#define XED_OPERAND_WIDTH_YD_DEFINED 1 +#define XED_OPERAND_WIDTH_YQ_DEFINED 1 +#define XED_OPERAND_WIDTH_YPS_DEFINED 1 +#define XED_OPERAND_WIDTH_YPD_DEFINED 1 +#define XED_OPERAND_WIDTH_ZBF16_DEFINED 1 +#define XED_OPERAND_WIDTH_VV_DEFINED 1 +#define XED_OPERAND_WIDTH_ZV_DEFINED 1 +#define XED_OPERAND_WIDTH_WRD_DEFINED 1 +#define XED_OPERAND_WIDTH_MSKW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZMSKW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZF32_DEFINED 1 +#define XED_OPERAND_WIDTH_ZF64_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUB_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUW_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUD_DEFINED 1 +#define XED_OPERAND_WIDTH_ZUQ_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI8_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI16_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI32_DEFINED 1 +#define XED_OPERAND_WIDTH_ZI64_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU8_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU16_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU32_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU64_DEFINED 1 +#define XED_OPERAND_WIDTH_ZU128_DEFINED 1 +#define XED_OPERAND_WIDTH_M384_DEFINED 1 +#define XED_OPERAND_WIDTH_M512_DEFINED 1 +#define XED_OPERAND_WIDTH_PTR_DEFINED 1 +#define XED_OPERAND_WIDTH_TMEMROW_DEFINED 1 +#define XED_OPERAND_WIDTH_TMEMCOL_DEFINED 1 +#define XED_OPERAND_WIDTH_TV_DEFINED 1 +#define XED_OPERAND_WIDTH_ZF16_DEFINED 1 +#define XED_OPERAND_WIDTH_Z2F16_DEFINED 1 +#define XED_OPERAND_WIDTH_LAST_DEFINED 1 +typedef enum { + XED_OPERAND_WIDTH_INVALID, + XED_OPERAND_WIDTH_ASZ, + XED_OPERAND_WIDTH_SSZ, + XED_OPERAND_WIDTH_PSEUDO, + XED_OPERAND_WIDTH_PSEUDOX87, + XED_OPERAND_WIDTH_A16, + XED_OPERAND_WIDTH_A32, + XED_OPERAND_WIDTH_B, + XED_OPERAND_WIDTH_D, + XED_OPERAND_WIDTH_I8, + XED_OPERAND_WIDTH_U8, + XED_OPERAND_WIDTH_I16, + XED_OPERAND_WIDTH_U16, + XED_OPERAND_WIDTH_I32, + XED_OPERAND_WIDTH_U32, + XED_OPERAND_WIDTH_I64, + XED_OPERAND_WIDTH_U64, + XED_OPERAND_WIDTH_F16, + XED_OPERAND_WIDTH_F32, + XED_OPERAND_WIDTH_F64, + XED_OPERAND_WIDTH_DQ, + XED_OPERAND_WIDTH_XUB, + XED_OPERAND_WIDTH_XUW, + XED_OPERAND_WIDTH_XUD, + XED_OPERAND_WIDTH_XUQ, + XED_OPERAND_WIDTH_X128, + XED_OPERAND_WIDTH_XB, + XED_OPERAND_WIDTH_XW, + XED_OPERAND_WIDTH_XD, + XED_OPERAND_WIDTH_XQ, + XED_OPERAND_WIDTH_ZB, + XED_OPERAND_WIDTH_ZW, + XED_OPERAND_WIDTH_ZD, + XED_OPERAND_WIDTH_ZQ, + XED_OPERAND_WIDTH_MB, + XED_OPERAND_WIDTH_MW, + XED_OPERAND_WIDTH_MD, + XED_OPERAND_WIDTH_MQ, + XED_OPERAND_WIDTH_M64INT, + XED_OPERAND_WIDTH_M64REAL, + XED_OPERAND_WIDTH_MEM108, + XED_OPERAND_WIDTH_MEM14, + XED_OPERAND_WIDTH_MEM16, + XED_OPERAND_WIDTH_MEM16INT, + XED_OPERAND_WIDTH_MEM28, + XED_OPERAND_WIDTH_MEM32INT, + XED_OPERAND_WIDTH_MEM32REAL, + XED_OPERAND_WIDTH_MEM80DEC, + XED_OPERAND_WIDTH_MEM80REAL, + XED_OPERAND_WIDTH_F80, + XED_OPERAND_WIDTH_MEM94, + XED_OPERAND_WIDTH_MFPXENV, + XED_OPERAND_WIDTH_MXSAVE, + XED_OPERAND_WIDTH_MPREFETCH, + XED_OPERAND_WIDTH_P, + XED_OPERAND_WIDTH_P2, + XED_OPERAND_WIDTH_PD, + XED_OPERAND_WIDTH_PS, + XED_OPERAND_WIDTH_PI, + XED_OPERAND_WIDTH_Q, + XED_OPERAND_WIDTH_S, + XED_OPERAND_WIDTH_S64, + XED_OPERAND_WIDTH_SD, + XED_OPERAND_WIDTH_SI, + XED_OPERAND_WIDTH_SS, + XED_OPERAND_WIDTH_V, + XED_OPERAND_WIDTH_Y, + XED_OPERAND_WIDTH_W, + XED_OPERAND_WIDTH_Z, + XED_OPERAND_WIDTH_SPW8, + XED_OPERAND_WIDTH_SPW, + XED_OPERAND_WIDTH_SPW5, + XED_OPERAND_WIDTH_SPW3, + XED_OPERAND_WIDTH_SPW2, + XED_OPERAND_WIDTH_I1, + XED_OPERAND_WIDTH_I2, + XED_OPERAND_WIDTH_I3, + XED_OPERAND_WIDTH_I4, + XED_OPERAND_WIDTH_I5, + XED_OPERAND_WIDTH_I6, + XED_OPERAND_WIDTH_I7, + XED_OPERAND_WIDTH_VAR, + XED_OPERAND_WIDTH_BND32, + XED_OPERAND_WIDTH_BND64, + XED_OPERAND_WIDTH_PMMSZ16, + XED_OPERAND_WIDTH_PMMSZ32, + XED_OPERAND_WIDTH_QQ, + XED_OPERAND_WIDTH_YUB, + XED_OPERAND_WIDTH_YUW, + XED_OPERAND_WIDTH_YUD, + XED_OPERAND_WIDTH_YUQ, + XED_OPERAND_WIDTH_Y128, + XED_OPERAND_WIDTH_YB, + XED_OPERAND_WIDTH_YW, + XED_OPERAND_WIDTH_YD, + XED_OPERAND_WIDTH_YQ, + XED_OPERAND_WIDTH_YPS, + XED_OPERAND_WIDTH_YPD, + XED_OPERAND_WIDTH_ZBF16, + XED_OPERAND_WIDTH_VV, + XED_OPERAND_WIDTH_ZV, + XED_OPERAND_WIDTH_WRD, + XED_OPERAND_WIDTH_MSKW, + XED_OPERAND_WIDTH_ZMSKW, + XED_OPERAND_WIDTH_ZF32, + XED_OPERAND_WIDTH_ZF64, + XED_OPERAND_WIDTH_ZUB, + XED_OPERAND_WIDTH_ZUW, + XED_OPERAND_WIDTH_ZUD, + XED_OPERAND_WIDTH_ZUQ, + XED_OPERAND_WIDTH_ZI8, + XED_OPERAND_WIDTH_ZI16, + XED_OPERAND_WIDTH_ZI32, + XED_OPERAND_WIDTH_ZI64, + XED_OPERAND_WIDTH_ZU8, + XED_OPERAND_WIDTH_ZU16, + XED_OPERAND_WIDTH_ZU32, + XED_OPERAND_WIDTH_ZU64, + XED_OPERAND_WIDTH_ZU128, + XED_OPERAND_WIDTH_M384, + XED_OPERAND_WIDTH_M512, + XED_OPERAND_WIDTH_PTR, + XED_OPERAND_WIDTH_TMEMROW, + XED_OPERAND_WIDTH_TMEMCOL, + XED_OPERAND_WIDTH_TV, + XED_OPERAND_WIDTH_ZF16, + XED_OPERAND_WIDTH_Z2F16, + XED_OPERAND_WIDTH_LAST +} xed_operand_width_enum_t; + +/// This converts strings to #xed_operand_width_enum_t types. +/// @param s A C-string. +/// @return #xed_operand_width_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_width_enum_t str2xed_operand_width_enum_t(const char* s); +/// This converts strings to #xed_operand_width_enum_t types. +/// @param p An enumeration element of type xed_operand_width_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_operand_width_enum_t2str(const xed_operand_width_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_operand_width_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_operand_width_enum_t xed_operand_width_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-operand-width-enum.txt b/CodeVirtualizer/build/obj/xed-operand-width-enum.txt new file mode 100644 index 0000000..2ea5820 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-operand-width-enum.txt @@ -0,0 +1,158 @@ +# @file xed-operand-width-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-operand-width-enum.c +hfn xed-operand-width-enum.h +typename xed_operand_width_enum_t +prefix XED_OPERAND_WIDTH_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +ASZ +SSZ +PSEUDO +PSEUDOX87 +A16 +A32 +B +D +I8 +U8 +I16 +U16 +I32 +U32 +I64 +U64 +F16 +F32 +F64 +DQ +XUB +XUW +XUD +XUQ +X128 +XB +XW +XD +XQ +ZB +ZW +ZD +ZQ +MB +MW +MD +MQ +M64INT +M64REAL +MEM108 +MEM14 +MEM16 +MEM16INT +MEM28 +MEM32INT +MEM32REAL +MEM80DEC +MEM80REAL +F80 +MEM94 +MFPXENV +MXSAVE +MPREFETCH +P +P2 +PD +PS +PI +Q +S +S64 +SD +SI +SS +V +Y +W +Z +SPW8 +SPW +SPW5 +SPW3 +SPW2 +I1 +I2 +I3 +I4 +I5 +I6 +I7 +I8 +VAR +BND32 +BND64 +PMMSZ16 +PMMSZ32 +QQ +YUB +YUW +YUD +YUQ +Y128 +YB +YW +YD +YQ +YPS +YPD +ZBF16 +VV +ZV +WRD +MSKW +ZMSKW +ZF32 +ZF64 +ZUB +ZUW +ZUD +ZUQ +ZI8 +ZI16 +ZI32 +ZI64 +ZU8 +ZU16 +ZU32 +ZU64 +ZU128 +M384 +M512 +PTR +TMEMROW +TMEMCOL +TV +ZF16 +Z2F16 diff --git a/CodeVirtualizer/build/obj/xed-reg-class-enum.c b/CodeVirtualizer/build/obj/xed-reg-class-enum.c new file mode 100644 index 0000000..4f3afc3 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-reg-class-enum.c @@ -0,0 +1,112 @@ +/// @file xed-reg-class-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-reg-class-enum.h" + +typedef struct { + const char* name; + xed_reg_class_enum_t value; +} name_table_xed_reg_class_enum_t; +static const name_table_xed_reg_class_enum_t name_array_xed_reg_class_enum_t[] = { +{"INVALID", XED_REG_CLASS_INVALID}, +{"BNDCFG", XED_REG_CLASS_BNDCFG}, +{"BNDSTAT", XED_REG_CLASS_BNDSTAT}, +{"BOUND", XED_REG_CLASS_BOUND}, +{"CR", XED_REG_CLASS_CR}, +{"DR", XED_REG_CLASS_DR}, +{"FLAGS", XED_REG_CLASS_FLAGS}, +{"GPR", XED_REG_CLASS_GPR}, +{"GPR16", XED_REG_CLASS_GPR16}, +{"GPR32", XED_REG_CLASS_GPR32}, +{"GPR64", XED_REG_CLASS_GPR64}, +{"GPR8", XED_REG_CLASS_GPR8}, +{"IP", XED_REG_CLASS_IP}, +{"MASK", XED_REG_CLASS_MASK}, +{"MMX", XED_REG_CLASS_MMX}, +{"MSR", XED_REG_CLASS_MSR}, +{"MXCSR", XED_REG_CLASS_MXCSR}, +{"PSEUDO", XED_REG_CLASS_PSEUDO}, +{"PSEUDOX87", XED_REG_CLASS_PSEUDOX87}, +{"SR", XED_REG_CLASS_SR}, +{"TMP", XED_REG_CLASS_TMP}, +{"TREG", XED_REG_CLASS_TREG}, +{"UIF", XED_REG_CLASS_UIF}, +{"X87", XED_REG_CLASS_X87}, +{"XCR", XED_REG_CLASS_XCR}, +{"XMM", XED_REG_CLASS_XMM}, +{"YMM", XED_REG_CLASS_YMM}, +{"ZMM", XED_REG_CLASS_ZMM}, +{"LAST", XED_REG_CLASS_LAST}, +{0, XED_REG_CLASS_LAST}, +}; + + +xed_reg_class_enum_t str2xed_reg_class_enum_t(const char* s) +{ + const name_table_xed_reg_class_enum_t* p = name_array_xed_reg_class_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_REG_CLASS_INVALID; +} + + +const char* xed_reg_class_enum_t2str(const xed_reg_class_enum_t p) +{ + xed_reg_class_enum_t type_idx = p; + if ( p > XED_REG_CLASS_LAST) type_idx = XED_REG_CLASS_LAST; + return name_array_xed_reg_class_enum_t[type_idx].name; +} + +xed_reg_class_enum_t xed_reg_class_enum_t_last(void) { + return XED_REG_CLASS_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_REG_CLASS_INVALID: + case XED_REG_CLASS_BNDCFG: + case XED_REG_CLASS_BNDSTAT: + case XED_REG_CLASS_BOUND: + case XED_REG_CLASS_CR: + case XED_REG_CLASS_DR: + case XED_REG_CLASS_FLAGS: + case XED_REG_CLASS_GPR: + case XED_REG_CLASS_GPR16: + case XED_REG_CLASS_GPR32: + case XED_REG_CLASS_GPR64: + case XED_REG_CLASS_GPR8: + case XED_REG_CLASS_IP: + case XED_REG_CLASS_MASK: + case XED_REG_CLASS_MMX: + case XED_REG_CLASS_MSR: + case XED_REG_CLASS_MXCSR: + case XED_REG_CLASS_PSEUDO: + case XED_REG_CLASS_PSEUDOX87: + case XED_REG_CLASS_SR: + case XED_REG_CLASS_TMP: + case XED_REG_CLASS_TREG: + case XED_REG_CLASS_UIF: + case XED_REG_CLASS_X87: + case XED_REG_CLASS_XCR: + case XED_REG_CLASS_XMM: + case XED_REG_CLASS_YMM: + case XED_REG_CLASS_ZMM: + case XED_REG_CLASS_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-reg-class-enum.h b/CodeVirtualizer/build/obj/xed-reg-class-enum.h new file mode 100644 index 0000000..ca46c61 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-reg-class-enum.h @@ -0,0 +1,85 @@ +/// @file xed-reg-class-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_REG_CLASS_ENUM_H) +# define XED_REG_CLASS_ENUM_H +#include "xed-common-hdrs.h" +#define XED_REG_CLASS_INVALID_DEFINED 1 +#define XED_REG_CLASS_BNDCFG_DEFINED 1 +#define XED_REG_CLASS_BNDSTAT_DEFINED 1 +#define XED_REG_CLASS_BOUND_DEFINED 1 +#define XED_REG_CLASS_CR_DEFINED 1 +#define XED_REG_CLASS_DR_DEFINED 1 +#define XED_REG_CLASS_FLAGS_DEFINED 1 +#define XED_REG_CLASS_GPR_DEFINED 1 +#define XED_REG_CLASS_GPR16_DEFINED 1 +#define XED_REG_CLASS_GPR32_DEFINED 1 +#define XED_REG_CLASS_GPR64_DEFINED 1 +#define XED_REG_CLASS_GPR8_DEFINED 1 +#define XED_REG_CLASS_IP_DEFINED 1 +#define XED_REG_CLASS_MASK_DEFINED 1 +#define XED_REG_CLASS_MMX_DEFINED 1 +#define XED_REG_CLASS_MSR_DEFINED 1 +#define XED_REG_CLASS_MXCSR_DEFINED 1 +#define XED_REG_CLASS_PSEUDO_DEFINED 1 +#define XED_REG_CLASS_PSEUDOX87_DEFINED 1 +#define XED_REG_CLASS_SR_DEFINED 1 +#define XED_REG_CLASS_TMP_DEFINED 1 +#define XED_REG_CLASS_TREG_DEFINED 1 +#define XED_REG_CLASS_UIF_DEFINED 1 +#define XED_REG_CLASS_X87_DEFINED 1 +#define XED_REG_CLASS_XCR_DEFINED 1 +#define XED_REG_CLASS_XMM_DEFINED 1 +#define XED_REG_CLASS_YMM_DEFINED 1 +#define XED_REG_CLASS_ZMM_DEFINED 1 +#define XED_REG_CLASS_LAST_DEFINED 1 +typedef enum { + XED_REG_CLASS_INVALID, + XED_REG_CLASS_BNDCFG, + XED_REG_CLASS_BNDSTAT, + XED_REG_CLASS_BOUND, + XED_REG_CLASS_CR, + XED_REG_CLASS_DR, + XED_REG_CLASS_FLAGS, + XED_REG_CLASS_GPR, + XED_REG_CLASS_GPR16, + XED_REG_CLASS_GPR32, + XED_REG_CLASS_GPR64, + XED_REG_CLASS_GPR8, + XED_REG_CLASS_IP, + XED_REG_CLASS_MASK, + XED_REG_CLASS_MMX, + XED_REG_CLASS_MSR, + XED_REG_CLASS_MXCSR, + XED_REG_CLASS_PSEUDO, + XED_REG_CLASS_PSEUDOX87, + XED_REG_CLASS_SR, + XED_REG_CLASS_TMP, + XED_REG_CLASS_TREG, + XED_REG_CLASS_UIF, + XED_REG_CLASS_X87, + XED_REG_CLASS_XCR, + XED_REG_CLASS_XMM, + XED_REG_CLASS_YMM, + XED_REG_CLASS_ZMM, + XED_REG_CLASS_LAST +} xed_reg_class_enum_t; + +/// This converts strings to #xed_reg_class_enum_t types. +/// @param s A C-string. +/// @return #xed_reg_class_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_reg_class_enum_t str2xed_reg_class_enum_t(const char* s); +/// This converts strings to #xed_reg_class_enum_t types. +/// @param p An enumeration element of type xed_reg_class_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_reg_class_enum_t2str(const xed_reg_class_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_reg_class_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_reg_class_enum_t xed_reg_class_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-reg-class-enum.txt b/CodeVirtualizer/build/obj/xed-reg-class-enum.txt new file mode 100644 index 0000000..6e59549 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-reg-class-enum.txt @@ -0,0 +1,58 @@ +# @file xed-reg-class-enum.txt + +# This file was automatically generated. +# Do not edit this file. + +#BEGIN_LEGAL +# +#Copyright (c) 2021 Intel Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#END_LEGAL +namespace XED +cfn xed-reg-class-enum.c +hfn xed-reg-class-enum.h +typename xed_reg_class_enum_t +prefix XED_REG_CLASS_ +stream_ifdef XED_PRINT +proto_prefix XED_DLL_EXPORT +extra_header xed-common-hdrs.h +INVALID +BNDCFG +BNDSTAT +BOUND +CR +DR +FLAGS +GPR +GPR16 +GPR32 +GPR64 +GPR8 +IP +MASK +MMX +MSR +MXCSR +PSEUDO +PSEUDOX87 +SR +TMP +TREG +UIF +X87 +XCR +XMM +YMM +ZMM diff --git a/CodeVirtualizer/build/obj/xed-reg-enum.c b/CodeVirtualizer/build/obj/xed-reg-enum.c new file mode 100644 index 0000000..f4d17c0 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-reg-enum.c @@ -0,0 +1,694 @@ +/// @file xed-reg-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-reg-enum.h" + +typedef struct { + const char* name; + xed_reg_enum_t value; +} name_table_xed_reg_enum_t; +static const name_table_xed_reg_enum_t name_array_xed_reg_enum_t[] = { +{"INVALID", XED_REG_INVALID}, +{"BNDCFGU", XED_REG_BNDCFGU}, +{"BNDSTATUS", XED_REG_BNDSTATUS}, +{"BND0", XED_REG_BND0}, +{"BND1", XED_REG_BND1}, +{"BND2", XED_REG_BND2}, +{"BND3", XED_REG_BND3}, +{"CR0", XED_REG_CR0}, +{"CR1", XED_REG_CR1}, +{"CR2", XED_REG_CR2}, +{"CR3", XED_REG_CR3}, +{"CR4", XED_REG_CR4}, +{"CR5", XED_REG_CR5}, +{"CR6", XED_REG_CR6}, +{"CR7", XED_REG_CR7}, +{"CR8", XED_REG_CR8}, +{"CR9", XED_REG_CR9}, +{"CR10", XED_REG_CR10}, +{"CR11", XED_REG_CR11}, +{"CR12", XED_REG_CR12}, +{"CR13", XED_REG_CR13}, +{"CR14", XED_REG_CR14}, +{"CR15", XED_REG_CR15}, +{"DR0", XED_REG_DR0}, +{"DR1", XED_REG_DR1}, +{"DR2", XED_REG_DR2}, +{"DR3", XED_REG_DR3}, +{"DR4", XED_REG_DR4}, +{"DR5", XED_REG_DR5}, +{"DR6", XED_REG_DR6}, +{"DR7", XED_REG_DR7}, +{"FLAGS", XED_REG_FLAGS}, +{"EFLAGS", XED_REG_EFLAGS}, +{"RFLAGS", XED_REG_RFLAGS}, +{"AX", XED_REG_AX}, +{"CX", XED_REG_CX}, +{"DX", XED_REG_DX}, +{"BX", XED_REG_BX}, +{"SP", XED_REG_SP}, +{"BP", XED_REG_BP}, +{"SI", XED_REG_SI}, +{"DI", XED_REG_DI}, +{"R8W", XED_REG_R8W}, +{"R9W", XED_REG_R9W}, +{"R10W", XED_REG_R10W}, +{"R11W", XED_REG_R11W}, +{"R12W", XED_REG_R12W}, +{"R13W", XED_REG_R13W}, +{"R14W", XED_REG_R14W}, +{"R15W", XED_REG_R15W}, +{"EAX", XED_REG_EAX}, +{"ECX", XED_REG_ECX}, +{"EDX", XED_REG_EDX}, +{"EBX", XED_REG_EBX}, +{"ESP", XED_REG_ESP}, +{"EBP", XED_REG_EBP}, +{"ESI", XED_REG_ESI}, +{"EDI", XED_REG_EDI}, +{"R8D", XED_REG_R8D}, +{"R9D", XED_REG_R9D}, +{"R10D", XED_REG_R10D}, +{"R11D", XED_REG_R11D}, +{"R12D", XED_REG_R12D}, +{"R13D", XED_REG_R13D}, +{"R14D", XED_REG_R14D}, +{"R15D", XED_REG_R15D}, +{"RAX", XED_REG_RAX}, +{"RCX", XED_REG_RCX}, +{"RDX", XED_REG_RDX}, +{"RBX", XED_REG_RBX}, +{"RSP", XED_REG_RSP}, +{"RBP", XED_REG_RBP}, +{"RSI", XED_REG_RSI}, +{"RDI", XED_REG_RDI}, +{"R8", XED_REG_R8}, +{"R9", XED_REG_R9}, +{"R10", XED_REG_R10}, +{"R11", XED_REG_R11}, +{"R12", XED_REG_R12}, +{"R13", XED_REG_R13}, +{"R14", XED_REG_R14}, +{"R15", XED_REG_R15}, +{"AL", XED_REG_AL}, +{"CL", XED_REG_CL}, +{"DL", XED_REG_DL}, +{"BL", XED_REG_BL}, +{"SPL", XED_REG_SPL}, +{"BPL", XED_REG_BPL}, +{"SIL", XED_REG_SIL}, +{"DIL", XED_REG_DIL}, +{"R8B", XED_REG_R8B}, +{"R9B", XED_REG_R9B}, +{"R10B", XED_REG_R10B}, +{"R11B", XED_REG_R11B}, +{"R12B", XED_REG_R12B}, +{"R13B", XED_REG_R13B}, +{"R14B", XED_REG_R14B}, +{"R15B", XED_REG_R15B}, +{"AH", XED_REG_AH}, +{"CH", XED_REG_CH}, +{"DH", XED_REG_DH}, +{"BH", XED_REG_BH}, +{"ERROR", XED_REG_ERROR}, +{"RIP", XED_REG_RIP}, +{"EIP", XED_REG_EIP}, +{"IP", XED_REG_IP}, +{"K0", XED_REG_K0}, +{"K1", XED_REG_K1}, +{"K2", XED_REG_K2}, +{"K3", XED_REG_K3}, +{"K4", XED_REG_K4}, +{"K5", XED_REG_K5}, +{"K6", XED_REG_K6}, +{"K7", XED_REG_K7}, +{"MM0", XED_REG_MMX0}, +{"MM1", XED_REG_MMX1}, +{"MM2", XED_REG_MMX2}, +{"MM3", XED_REG_MMX3}, +{"MM4", XED_REG_MMX4}, +{"MM5", XED_REG_MMX5}, +{"MM6", XED_REG_MMX6}, +{"MM7", XED_REG_MMX7}, +{"SSP", XED_REG_SSP}, +{"IA32_U_CET", XED_REG_IA32_U_CET}, +{"MXCSR", XED_REG_MXCSR}, +{"STACKPUSH", XED_REG_STACKPUSH}, +{"STACKPOP", XED_REG_STACKPOP}, +{"GDTR", XED_REG_GDTR}, +{"LDTR", XED_REG_LDTR}, +{"IDTR", XED_REG_IDTR}, +{"TR", XED_REG_TR}, +{"TSC", XED_REG_TSC}, +{"TSCAUX", XED_REG_TSCAUX}, +{"MSRS", XED_REG_MSRS}, +{"FSBASE", XED_REG_FSBASE}, +{"GSBASE", XED_REG_GSBASE}, +{"TILECONFIG", XED_REG_TILECONFIG}, +{"X87CONTROL", XED_REG_X87CONTROL}, +{"X87STATUS", XED_REG_X87STATUS}, +{"X87TAG", XED_REG_X87TAG}, +{"X87PUSH", XED_REG_X87PUSH}, +{"X87POP", XED_REG_X87POP}, +{"X87POP2", XED_REG_X87POP2}, +{"X87OPCODE", XED_REG_X87OPCODE}, +{"X87LASTCS", XED_REG_X87LASTCS}, +{"X87LASTIP", XED_REG_X87LASTIP}, +{"X87LASTDS", XED_REG_X87LASTDS}, +{"X87LASTDP", XED_REG_X87LASTDP}, +{"ES", XED_REG_ES}, +{"CS", XED_REG_CS}, +{"SS", XED_REG_SS}, +{"DS", XED_REG_DS}, +{"FS", XED_REG_FS}, +{"GS", XED_REG_GS}, +{"TMP0", XED_REG_TMP0}, +{"TMP1", XED_REG_TMP1}, +{"TMP2", XED_REG_TMP2}, +{"TMP3", XED_REG_TMP3}, +{"TMP4", XED_REG_TMP4}, +{"TMP5", XED_REG_TMP5}, +{"TMP6", XED_REG_TMP6}, +{"TMP7", XED_REG_TMP7}, +{"TMP8", XED_REG_TMP8}, +{"TMP9", XED_REG_TMP9}, +{"TMP10", XED_REG_TMP10}, +{"TMP11", XED_REG_TMP11}, +{"TMP12", XED_REG_TMP12}, +{"TMP13", XED_REG_TMP13}, +{"TMP14", XED_REG_TMP14}, +{"TMP15", XED_REG_TMP15}, +{"TMM0", XED_REG_TMM0}, +{"TMM1", XED_REG_TMM1}, +{"TMM2", XED_REG_TMM2}, +{"TMM3", XED_REG_TMM3}, +{"TMM4", XED_REG_TMM4}, +{"TMM5", XED_REG_TMM5}, +{"TMM6", XED_REG_TMM6}, +{"TMM7", XED_REG_TMM7}, +{"UIF", XED_REG_UIF}, +{"ST(0)", XED_REG_ST0}, +{"ST(1)", XED_REG_ST1}, +{"ST(2)", XED_REG_ST2}, +{"ST(3)", XED_REG_ST3}, +{"ST(4)", XED_REG_ST4}, +{"ST(5)", XED_REG_ST5}, +{"ST(6)", XED_REG_ST6}, +{"ST(7)", XED_REG_ST7}, +{"XCR0", XED_REG_XCR0}, +{"XMM0", XED_REG_XMM0}, +{"XMM1", XED_REG_XMM1}, +{"XMM2", XED_REG_XMM2}, +{"XMM3", XED_REG_XMM3}, +{"XMM4", XED_REG_XMM4}, +{"XMM5", XED_REG_XMM5}, +{"XMM6", XED_REG_XMM6}, +{"XMM7", XED_REG_XMM7}, +{"XMM8", XED_REG_XMM8}, +{"XMM9", XED_REG_XMM9}, +{"XMM10", XED_REG_XMM10}, +{"XMM11", XED_REG_XMM11}, +{"XMM12", XED_REG_XMM12}, +{"XMM13", XED_REG_XMM13}, +{"XMM14", XED_REG_XMM14}, +{"XMM15", XED_REG_XMM15}, +{"XMM16", XED_REG_XMM16}, +{"XMM17", XED_REG_XMM17}, +{"XMM18", XED_REG_XMM18}, +{"XMM19", XED_REG_XMM19}, +{"XMM20", XED_REG_XMM20}, +{"XMM21", XED_REG_XMM21}, +{"XMM22", XED_REG_XMM22}, +{"XMM23", XED_REG_XMM23}, +{"XMM24", XED_REG_XMM24}, +{"XMM25", XED_REG_XMM25}, +{"XMM26", XED_REG_XMM26}, +{"XMM27", XED_REG_XMM27}, +{"XMM28", XED_REG_XMM28}, +{"XMM29", XED_REG_XMM29}, +{"XMM30", XED_REG_XMM30}, +{"XMM31", XED_REG_XMM31}, +{"YMM0", XED_REG_YMM0}, +{"YMM1", XED_REG_YMM1}, +{"YMM2", XED_REG_YMM2}, +{"YMM3", XED_REG_YMM3}, +{"YMM4", XED_REG_YMM4}, +{"YMM5", XED_REG_YMM5}, +{"YMM6", XED_REG_YMM6}, +{"YMM7", XED_REG_YMM7}, +{"YMM8", XED_REG_YMM8}, +{"YMM9", XED_REG_YMM9}, +{"YMM10", XED_REG_YMM10}, +{"YMM11", XED_REG_YMM11}, +{"YMM12", XED_REG_YMM12}, +{"YMM13", XED_REG_YMM13}, +{"YMM14", XED_REG_YMM14}, +{"YMM15", XED_REG_YMM15}, +{"YMM16", XED_REG_YMM16}, +{"YMM17", XED_REG_YMM17}, +{"YMM18", XED_REG_YMM18}, +{"YMM19", XED_REG_YMM19}, +{"YMM20", XED_REG_YMM20}, +{"YMM21", XED_REG_YMM21}, +{"YMM22", XED_REG_YMM22}, +{"YMM23", XED_REG_YMM23}, +{"YMM24", XED_REG_YMM24}, +{"YMM25", XED_REG_YMM25}, +{"YMM26", XED_REG_YMM26}, +{"YMM27", XED_REG_YMM27}, +{"YMM28", XED_REG_YMM28}, +{"YMM29", XED_REG_YMM29}, +{"YMM30", XED_REG_YMM30}, +{"YMM31", XED_REG_YMM31}, +{"ZMM0", XED_REG_ZMM0}, +{"ZMM1", XED_REG_ZMM1}, +{"ZMM2", XED_REG_ZMM2}, +{"ZMM3", XED_REG_ZMM3}, +{"ZMM4", XED_REG_ZMM4}, +{"ZMM5", XED_REG_ZMM5}, +{"ZMM6", XED_REG_ZMM6}, +{"ZMM7", XED_REG_ZMM7}, +{"ZMM8", XED_REG_ZMM8}, +{"ZMM9", XED_REG_ZMM9}, +{"ZMM10", XED_REG_ZMM10}, +{"ZMM11", XED_REG_ZMM11}, +{"ZMM12", XED_REG_ZMM12}, +{"ZMM13", XED_REG_ZMM13}, +{"ZMM14", XED_REG_ZMM14}, +{"ZMM15", XED_REG_ZMM15}, +{"ZMM16", XED_REG_ZMM16}, +{"ZMM17", XED_REG_ZMM17}, +{"ZMM18", XED_REG_ZMM18}, +{"ZMM19", XED_REG_ZMM19}, +{"ZMM20", XED_REG_ZMM20}, +{"ZMM21", XED_REG_ZMM21}, +{"ZMM22", XED_REG_ZMM22}, +{"ZMM23", XED_REG_ZMM23}, +{"ZMM24", XED_REG_ZMM24}, +{"ZMM25", XED_REG_ZMM25}, +{"ZMM26", XED_REG_ZMM26}, +{"ZMM27", XED_REG_ZMM27}, +{"ZMM28", XED_REG_ZMM28}, +{"ZMM29", XED_REG_ZMM29}, +{"ZMM30", XED_REG_ZMM30}, +{"ZMM31", XED_REG_ZMM31}, +{"LAST", XED_REG_LAST}, +{0, XED_REG_LAST}, +}; +static const name_table_xed_reg_enum_t dup_name_array_xed_reg_enum_t[] = { +{"BNDCFG_FIRST", XED_REG_BNDCFG_FIRST}, +{"BNDCFG_LAST", XED_REG_BNDCFG_LAST}, +{"BNDSTAT_FIRST", XED_REG_BNDSTAT_FIRST}, +{"BNDSTAT_LAST", XED_REG_BNDSTAT_LAST}, +{"BOUND_FIRST", XED_REG_BOUND_FIRST}, +{"BOUND_LAST", XED_REG_BOUND_LAST}, +{"CR_FIRST", XED_REG_CR_FIRST}, +{"CR_LAST", XED_REG_CR_LAST}, +{"DR_FIRST", XED_REG_DR_FIRST}, +{"DR_LAST", XED_REG_DR_LAST}, +{"FLAGS_FIRST", XED_REG_FLAGS_FIRST}, +{"FLAGS_LAST", XED_REG_FLAGS_LAST}, +{"GPR16_FIRST", XED_REG_GPR16_FIRST}, +{"GPR16_LAST", XED_REG_GPR16_LAST}, +{"GPR32_FIRST", XED_REG_GPR32_FIRST}, +{"GPR32_LAST", XED_REG_GPR32_LAST}, +{"GPR64_FIRST", XED_REG_GPR64_FIRST}, +{"GPR64_LAST", XED_REG_GPR64_LAST}, +{"GPR8_FIRST", XED_REG_GPR8_FIRST}, +{"GPR8_LAST", XED_REG_GPR8_LAST}, +{"GPR8h_FIRST", XED_REG_GPR8h_FIRST}, +{"GPR8h_LAST", XED_REG_GPR8h_LAST}, +{"INVALID_FIRST", XED_REG_INVALID_FIRST}, +{"INVALID_LAST", XED_REG_INVALID_LAST}, +{"IP_FIRST", XED_REG_IP_FIRST}, +{"IP_LAST", XED_REG_IP_LAST}, +{"MASK_FIRST", XED_REG_MASK_FIRST}, +{"MASK_LAST", XED_REG_MASK_LAST}, +{"MMX_FIRST", XED_REG_MMX_FIRST}, +{"MMX_LAST", XED_REG_MMX_LAST}, +{"MSR_FIRST", XED_REG_MSR_FIRST}, +{"MSR_LAST", XED_REG_MSR_LAST}, +{"MXCSR_FIRST", XED_REG_MXCSR_FIRST}, +{"MXCSR_LAST", XED_REG_MXCSR_LAST}, +{"PSEUDO_FIRST", XED_REG_PSEUDO_FIRST}, +{"PSEUDO_LAST", XED_REG_PSEUDO_LAST}, +{"PSEUDOX87_FIRST", XED_REG_PSEUDOX87_FIRST}, +{"PSEUDOX87_LAST", XED_REG_PSEUDOX87_LAST}, +{"SR_FIRST", XED_REG_SR_FIRST}, +{"SR_LAST", XED_REG_SR_LAST}, +{"TMP_FIRST", XED_REG_TMP_FIRST}, +{"TMP_LAST", XED_REG_TMP_LAST}, +{"TREG_FIRST", XED_REG_TREG_FIRST}, +{"TREG_LAST", XED_REG_TREG_LAST}, +{"UIF_FIRST", XED_REG_UIF_FIRST}, +{"UIF_LAST", XED_REG_UIF_LAST}, +{"X87_FIRST", XED_REG_X87_FIRST}, +{"X87_LAST", XED_REG_X87_LAST}, +{"XCR_FIRST", XED_REG_XCR_FIRST}, +{"XCR_LAST", XED_REG_XCR_LAST}, +{"XMM_FIRST", XED_REG_XMM_FIRST}, +{"XMM_LAST", XED_REG_XMM_LAST}, +{"YMM_FIRST", XED_REG_YMM_FIRST}, +{"YMM_LAST", XED_REG_YMM_LAST}, +{"ZMM_FIRST", XED_REG_ZMM_FIRST}, +{"ZMM_LAST", XED_REG_ZMM_LAST}, +{0, XED_REG_LAST}, +}; + + +xed_reg_enum_t str2xed_reg_enum_t(const char* s) +{ + const name_table_xed_reg_enum_t* p = name_array_xed_reg_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + { + const name_table_xed_reg_enum_t* q = dup_name_array_xed_reg_enum_t; + while( q->name ) { + if (strcmp(q->name,s) == 0) { + return q->value; + } + q++; + } + } + + + return XED_REG_INVALID; +} + + +const char* xed_reg_enum_t2str(const xed_reg_enum_t p) +{ + xed_reg_enum_t type_idx = p; + if ( p > XED_REG_LAST) type_idx = XED_REG_LAST; + return name_array_xed_reg_enum_t[type_idx].name; +} + +xed_reg_enum_t xed_reg_enum_t_last(void) { + return XED_REG_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_REG_INVALID: + case XED_REG_BNDCFGU: + case XED_REG_BNDSTATUS: + case XED_REG_BND0: + case XED_REG_BND1: + case XED_REG_BND2: + case XED_REG_BND3: + case XED_REG_CR0: + case XED_REG_CR1: + case XED_REG_CR2: + case XED_REG_CR3: + case XED_REG_CR4: + case XED_REG_CR5: + case XED_REG_CR6: + case XED_REG_CR7: + case XED_REG_CR8: + case XED_REG_CR9: + case XED_REG_CR10: + case XED_REG_CR11: + case XED_REG_CR12: + case XED_REG_CR13: + case XED_REG_CR14: + case XED_REG_CR15: + case XED_REG_DR0: + case XED_REG_DR1: + case XED_REG_DR2: + case XED_REG_DR3: + case XED_REG_DR4: + case XED_REG_DR5: + case XED_REG_DR6: + case XED_REG_DR7: + case XED_REG_FLAGS: + case XED_REG_EFLAGS: + case XED_REG_RFLAGS: + case XED_REG_AX: + case XED_REG_CX: + case XED_REG_DX: + case XED_REG_BX: + case XED_REG_SP: + case XED_REG_BP: + case XED_REG_SI: + case XED_REG_DI: + case XED_REG_R8W: + case XED_REG_R9W: + case XED_REG_R10W: + case XED_REG_R11W: + case XED_REG_R12W: + case XED_REG_R13W: + case XED_REG_R14W: + case XED_REG_R15W: + case XED_REG_EAX: + case XED_REG_ECX: + case XED_REG_EDX: + case XED_REG_EBX: + case XED_REG_ESP: + case XED_REG_EBP: + case XED_REG_ESI: + case XED_REG_EDI: + case XED_REG_R8D: + case XED_REG_R9D: + case XED_REG_R10D: + case XED_REG_R11D: + case XED_REG_R12D: + case XED_REG_R13D: + case XED_REG_R14D: + case XED_REG_R15D: + case XED_REG_RAX: + case XED_REG_RCX: + case XED_REG_RDX: + case XED_REG_RBX: + case XED_REG_RSP: + case XED_REG_RBP: + case XED_REG_RSI: + case XED_REG_RDI: + case XED_REG_R8: + case XED_REG_R9: + case XED_REG_R10: + case XED_REG_R11: + case XED_REG_R12: + case XED_REG_R13: + case XED_REG_R14: + case XED_REG_R15: + case XED_REG_AL: + case XED_REG_CL: + case XED_REG_DL: + case XED_REG_BL: + case XED_REG_SPL: + case XED_REG_BPL: + case XED_REG_SIL: + case XED_REG_DIL: + case XED_REG_R8B: + case XED_REG_R9B: + case XED_REG_R10B: + case XED_REG_R11B: + case XED_REG_R12B: + case XED_REG_R13B: + case XED_REG_R14B: + case XED_REG_R15B: + case XED_REG_AH: + case XED_REG_CH: + case XED_REG_DH: + case XED_REG_BH: + case XED_REG_ERROR: + case XED_REG_RIP: + case XED_REG_EIP: + case XED_REG_IP: + case XED_REG_K0: + case XED_REG_K1: + case XED_REG_K2: + case XED_REG_K3: + case XED_REG_K4: + case XED_REG_K5: + case XED_REG_K6: + case XED_REG_K7: + case XED_REG_MMX0: + case XED_REG_MMX1: + case XED_REG_MMX2: + case XED_REG_MMX3: + case XED_REG_MMX4: + case XED_REG_MMX5: + case XED_REG_MMX6: + case XED_REG_MMX7: + case XED_REG_SSP: + case XED_REG_IA32_U_CET: + case XED_REG_MXCSR: + case XED_REG_STACKPUSH: + case XED_REG_STACKPOP: + case XED_REG_GDTR: + case XED_REG_LDTR: + case XED_REG_IDTR: + case XED_REG_TR: + case XED_REG_TSC: + case XED_REG_TSCAUX: + case XED_REG_MSRS: + case XED_REG_FSBASE: + case XED_REG_GSBASE: + case XED_REG_TILECONFIG: + case XED_REG_X87CONTROL: + case XED_REG_X87STATUS: + case XED_REG_X87TAG: + case XED_REG_X87PUSH: + case XED_REG_X87POP: + case XED_REG_X87POP2: + case XED_REG_X87OPCODE: + case XED_REG_X87LASTCS: + case XED_REG_X87LASTIP: + case XED_REG_X87LASTDS: + case XED_REG_X87LASTDP: + case XED_REG_ES: + case XED_REG_CS: + case XED_REG_SS: + case XED_REG_DS: + case XED_REG_FS: + case XED_REG_GS: + case XED_REG_TMP0: + case XED_REG_TMP1: + case XED_REG_TMP2: + case XED_REG_TMP3: + case XED_REG_TMP4: + case XED_REG_TMP5: + case XED_REG_TMP6: + case XED_REG_TMP7: + case XED_REG_TMP8: + case XED_REG_TMP9: + case XED_REG_TMP10: + case XED_REG_TMP11: + case XED_REG_TMP12: + case XED_REG_TMP13: + case XED_REG_TMP14: + case XED_REG_TMP15: + case XED_REG_TMM0: + case XED_REG_TMM1: + case XED_REG_TMM2: + case XED_REG_TMM3: + case XED_REG_TMM4: + case XED_REG_TMM5: + case XED_REG_TMM6: + case XED_REG_TMM7: + case XED_REG_UIF: + case XED_REG_ST0: + case XED_REG_ST1: + case XED_REG_ST2: + case XED_REG_ST3: + case XED_REG_ST4: + case XED_REG_ST5: + case XED_REG_ST6: + case XED_REG_ST7: + case XED_REG_XCR0: + case XED_REG_XMM0: + case XED_REG_XMM1: + case XED_REG_XMM2: + case XED_REG_XMM3: + case XED_REG_XMM4: + case XED_REG_XMM5: + case XED_REG_XMM6: + case XED_REG_XMM7: + case XED_REG_XMM8: + case XED_REG_XMM9: + case XED_REG_XMM10: + case XED_REG_XMM11: + case XED_REG_XMM12: + case XED_REG_XMM13: + case XED_REG_XMM14: + case XED_REG_XMM15: + case XED_REG_XMM16: + case XED_REG_XMM17: + case XED_REG_XMM18: + case XED_REG_XMM19: + case XED_REG_XMM20: + case XED_REG_XMM21: + case XED_REG_XMM22: + case XED_REG_XMM23: + case XED_REG_XMM24: + case XED_REG_XMM25: + case XED_REG_XMM26: + case XED_REG_XMM27: + case XED_REG_XMM28: + case XED_REG_XMM29: + case XED_REG_XMM30: + case XED_REG_XMM31: + case XED_REG_YMM0: + case XED_REG_YMM1: + case XED_REG_YMM2: + case XED_REG_YMM3: + case XED_REG_YMM4: + case XED_REG_YMM5: + case XED_REG_YMM6: + case XED_REG_YMM7: + case XED_REG_YMM8: + case XED_REG_YMM9: + case XED_REG_YMM10: + case XED_REG_YMM11: + case XED_REG_YMM12: + case XED_REG_YMM13: + case XED_REG_YMM14: + case XED_REG_YMM15: + case XED_REG_YMM16: + case XED_REG_YMM17: + case XED_REG_YMM18: + case XED_REG_YMM19: + case XED_REG_YMM20: + case XED_REG_YMM21: + case XED_REG_YMM22: + case XED_REG_YMM23: + case XED_REG_YMM24: + case XED_REG_YMM25: + case XED_REG_YMM26: + case XED_REG_YMM27: + case XED_REG_YMM28: + case XED_REG_YMM29: + case XED_REG_YMM30: + case XED_REG_YMM31: + case XED_REG_ZMM0: + case XED_REG_ZMM1: + case XED_REG_ZMM2: + case XED_REG_ZMM3: + case XED_REG_ZMM4: + case XED_REG_ZMM5: + case XED_REG_ZMM6: + case XED_REG_ZMM7: + case XED_REG_ZMM8: + case XED_REG_ZMM9: + case XED_REG_ZMM10: + case XED_REG_ZMM11: + case XED_REG_ZMM12: + case XED_REG_ZMM13: + case XED_REG_ZMM14: + case XED_REG_ZMM15: + case XED_REG_ZMM16: + case XED_REG_ZMM17: + case XED_REG_ZMM18: + case XED_REG_ZMM19: + case XED_REG_ZMM20: + case XED_REG_ZMM21: + case XED_REG_ZMM22: + case XED_REG_ZMM23: + case XED_REG_ZMM24: + case XED_REG_ZMM25: + case XED_REG_ZMM26: + case XED_REG_ZMM27: + case XED_REG_ZMM28: + case XED_REG_ZMM29: + case XED_REG_ZMM30: + case XED_REG_ZMM31: + case XED_REG_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-reg-enum.h b/CodeVirtualizer/build/obj/xed-reg-enum.h new file mode 100644 index 0000000..4906770 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-reg-enum.h @@ -0,0 +1,709 @@ +/// @file xed-reg-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_REG_ENUM_H) +# define XED_REG_ENUM_H +#include "xed-common-hdrs.h" +#define XED_REG_INVALID_DEFINED 1 +#define XED_REG_BNDCFGU_DEFINED 1 +#define XED_REG_BNDSTATUS_DEFINED 1 +#define XED_REG_BND0_DEFINED 1 +#define XED_REG_BND1_DEFINED 1 +#define XED_REG_BND2_DEFINED 1 +#define XED_REG_BND3_DEFINED 1 +#define XED_REG_CR0_DEFINED 1 +#define XED_REG_CR1_DEFINED 1 +#define XED_REG_CR2_DEFINED 1 +#define XED_REG_CR3_DEFINED 1 +#define XED_REG_CR4_DEFINED 1 +#define XED_REG_CR5_DEFINED 1 +#define XED_REG_CR6_DEFINED 1 +#define XED_REG_CR7_DEFINED 1 +#define XED_REG_CR8_DEFINED 1 +#define XED_REG_CR9_DEFINED 1 +#define XED_REG_CR10_DEFINED 1 +#define XED_REG_CR11_DEFINED 1 +#define XED_REG_CR12_DEFINED 1 +#define XED_REG_CR13_DEFINED 1 +#define XED_REG_CR14_DEFINED 1 +#define XED_REG_CR15_DEFINED 1 +#define XED_REG_DR0_DEFINED 1 +#define XED_REG_DR1_DEFINED 1 +#define XED_REG_DR2_DEFINED 1 +#define XED_REG_DR3_DEFINED 1 +#define XED_REG_DR4_DEFINED 1 +#define XED_REG_DR5_DEFINED 1 +#define XED_REG_DR6_DEFINED 1 +#define XED_REG_DR7_DEFINED 1 +#define XED_REG_FLAGS_DEFINED 1 +#define XED_REG_EFLAGS_DEFINED 1 +#define XED_REG_RFLAGS_DEFINED 1 +#define XED_REG_AX_DEFINED 1 +#define XED_REG_CX_DEFINED 1 +#define XED_REG_DX_DEFINED 1 +#define XED_REG_BX_DEFINED 1 +#define XED_REG_SP_DEFINED 1 +#define XED_REG_BP_DEFINED 1 +#define XED_REG_SI_DEFINED 1 +#define XED_REG_DI_DEFINED 1 +#define XED_REG_R8W_DEFINED 1 +#define XED_REG_R9W_DEFINED 1 +#define XED_REG_R10W_DEFINED 1 +#define XED_REG_R11W_DEFINED 1 +#define XED_REG_R12W_DEFINED 1 +#define XED_REG_R13W_DEFINED 1 +#define XED_REG_R14W_DEFINED 1 +#define XED_REG_R15W_DEFINED 1 +#define XED_REG_EAX_DEFINED 1 +#define XED_REG_ECX_DEFINED 1 +#define XED_REG_EDX_DEFINED 1 +#define XED_REG_EBX_DEFINED 1 +#define XED_REG_ESP_DEFINED 1 +#define XED_REG_EBP_DEFINED 1 +#define XED_REG_ESI_DEFINED 1 +#define XED_REG_EDI_DEFINED 1 +#define XED_REG_R8D_DEFINED 1 +#define XED_REG_R9D_DEFINED 1 +#define XED_REG_R10D_DEFINED 1 +#define XED_REG_R11D_DEFINED 1 +#define XED_REG_R12D_DEFINED 1 +#define XED_REG_R13D_DEFINED 1 +#define XED_REG_R14D_DEFINED 1 +#define XED_REG_R15D_DEFINED 1 +#define XED_REG_RAX_DEFINED 1 +#define XED_REG_RCX_DEFINED 1 +#define XED_REG_RDX_DEFINED 1 +#define XED_REG_RBX_DEFINED 1 +#define XED_REG_RSP_DEFINED 1 +#define XED_REG_RBP_DEFINED 1 +#define XED_REG_RSI_DEFINED 1 +#define XED_REG_RDI_DEFINED 1 +#define XED_REG_R8_DEFINED 1 +#define XED_REG_R9_DEFINED 1 +#define XED_REG_R10_DEFINED 1 +#define XED_REG_R11_DEFINED 1 +#define XED_REG_R12_DEFINED 1 +#define XED_REG_R13_DEFINED 1 +#define XED_REG_R14_DEFINED 1 +#define XED_REG_R15_DEFINED 1 +#define XED_REG_AL_DEFINED 1 +#define XED_REG_CL_DEFINED 1 +#define XED_REG_DL_DEFINED 1 +#define XED_REG_BL_DEFINED 1 +#define XED_REG_SPL_DEFINED 1 +#define XED_REG_BPL_DEFINED 1 +#define XED_REG_SIL_DEFINED 1 +#define XED_REG_DIL_DEFINED 1 +#define XED_REG_R8B_DEFINED 1 +#define XED_REG_R9B_DEFINED 1 +#define XED_REG_R10B_DEFINED 1 +#define XED_REG_R11B_DEFINED 1 +#define XED_REG_R12B_DEFINED 1 +#define XED_REG_R13B_DEFINED 1 +#define XED_REG_R14B_DEFINED 1 +#define XED_REG_R15B_DEFINED 1 +#define XED_REG_AH_DEFINED 1 +#define XED_REG_CH_DEFINED 1 +#define XED_REG_DH_DEFINED 1 +#define XED_REG_BH_DEFINED 1 +#define XED_REG_ERROR_DEFINED 1 +#define XED_REG_RIP_DEFINED 1 +#define XED_REG_EIP_DEFINED 1 +#define XED_REG_IP_DEFINED 1 +#define XED_REG_K0_DEFINED 1 +#define XED_REG_K1_DEFINED 1 +#define XED_REG_K2_DEFINED 1 +#define XED_REG_K3_DEFINED 1 +#define XED_REG_K4_DEFINED 1 +#define XED_REG_K5_DEFINED 1 +#define XED_REG_K6_DEFINED 1 +#define XED_REG_K7_DEFINED 1 +#define XED_REG_MMX0_DEFINED 1 +#define XED_REG_MMX1_DEFINED 1 +#define XED_REG_MMX2_DEFINED 1 +#define XED_REG_MMX3_DEFINED 1 +#define XED_REG_MMX4_DEFINED 1 +#define XED_REG_MMX5_DEFINED 1 +#define XED_REG_MMX6_DEFINED 1 +#define XED_REG_MMX7_DEFINED 1 +#define XED_REG_SSP_DEFINED 1 +#define XED_REG_IA32_U_CET_DEFINED 1 +#define XED_REG_MXCSR_DEFINED 1 +#define XED_REG_STACKPUSH_DEFINED 1 +#define XED_REG_STACKPOP_DEFINED 1 +#define XED_REG_GDTR_DEFINED 1 +#define XED_REG_LDTR_DEFINED 1 +#define XED_REG_IDTR_DEFINED 1 +#define XED_REG_TR_DEFINED 1 +#define XED_REG_TSC_DEFINED 1 +#define XED_REG_TSCAUX_DEFINED 1 +#define XED_REG_MSRS_DEFINED 1 +#define XED_REG_FSBASE_DEFINED 1 +#define XED_REG_GSBASE_DEFINED 1 +#define XED_REG_TILECONFIG_DEFINED 1 +#define XED_REG_X87CONTROL_DEFINED 1 +#define XED_REG_X87STATUS_DEFINED 1 +#define XED_REG_X87TAG_DEFINED 1 +#define XED_REG_X87PUSH_DEFINED 1 +#define XED_REG_X87POP_DEFINED 1 +#define XED_REG_X87POP2_DEFINED 1 +#define XED_REG_X87OPCODE_DEFINED 1 +#define XED_REG_X87LASTCS_DEFINED 1 +#define XED_REG_X87LASTIP_DEFINED 1 +#define XED_REG_X87LASTDS_DEFINED 1 +#define XED_REG_X87LASTDP_DEFINED 1 +#define XED_REG_ES_DEFINED 1 +#define XED_REG_CS_DEFINED 1 +#define XED_REG_SS_DEFINED 1 +#define XED_REG_DS_DEFINED 1 +#define XED_REG_FS_DEFINED 1 +#define XED_REG_GS_DEFINED 1 +#define XED_REG_TMP0_DEFINED 1 +#define XED_REG_TMP1_DEFINED 1 +#define XED_REG_TMP2_DEFINED 1 +#define XED_REG_TMP3_DEFINED 1 +#define XED_REG_TMP4_DEFINED 1 +#define XED_REG_TMP5_DEFINED 1 +#define XED_REG_TMP6_DEFINED 1 +#define XED_REG_TMP7_DEFINED 1 +#define XED_REG_TMP8_DEFINED 1 +#define XED_REG_TMP9_DEFINED 1 +#define XED_REG_TMP10_DEFINED 1 +#define XED_REG_TMP11_DEFINED 1 +#define XED_REG_TMP12_DEFINED 1 +#define XED_REG_TMP13_DEFINED 1 +#define XED_REG_TMP14_DEFINED 1 +#define XED_REG_TMP15_DEFINED 1 +#define XED_REG_TMM0_DEFINED 1 +#define XED_REG_TMM1_DEFINED 1 +#define XED_REG_TMM2_DEFINED 1 +#define XED_REG_TMM3_DEFINED 1 +#define XED_REG_TMM4_DEFINED 1 +#define XED_REG_TMM5_DEFINED 1 +#define XED_REG_TMM6_DEFINED 1 +#define XED_REG_TMM7_DEFINED 1 +#define XED_REG_UIF_DEFINED 1 +#define XED_REG_ST0_DEFINED 1 +#define XED_REG_ST1_DEFINED 1 +#define XED_REG_ST2_DEFINED 1 +#define XED_REG_ST3_DEFINED 1 +#define XED_REG_ST4_DEFINED 1 +#define XED_REG_ST5_DEFINED 1 +#define XED_REG_ST6_DEFINED 1 +#define XED_REG_ST7_DEFINED 1 +#define XED_REG_XCR0_DEFINED 1 +#define XED_REG_XMM0_DEFINED 1 +#define XED_REG_XMM1_DEFINED 1 +#define XED_REG_XMM2_DEFINED 1 +#define XED_REG_XMM3_DEFINED 1 +#define XED_REG_XMM4_DEFINED 1 +#define XED_REG_XMM5_DEFINED 1 +#define XED_REG_XMM6_DEFINED 1 +#define XED_REG_XMM7_DEFINED 1 +#define XED_REG_XMM8_DEFINED 1 +#define XED_REG_XMM9_DEFINED 1 +#define XED_REG_XMM10_DEFINED 1 +#define XED_REG_XMM11_DEFINED 1 +#define XED_REG_XMM12_DEFINED 1 +#define XED_REG_XMM13_DEFINED 1 +#define XED_REG_XMM14_DEFINED 1 +#define XED_REG_XMM15_DEFINED 1 +#define XED_REG_XMM16_DEFINED 1 +#define XED_REG_XMM17_DEFINED 1 +#define XED_REG_XMM18_DEFINED 1 +#define XED_REG_XMM19_DEFINED 1 +#define XED_REG_XMM20_DEFINED 1 +#define XED_REG_XMM21_DEFINED 1 +#define XED_REG_XMM22_DEFINED 1 +#define XED_REG_XMM23_DEFINED 1 +#define XED_REG_XMM24_DEFINED 1 +#define XED_REG_XMM25_DEFINED 1 +#define XED_REG_XMM26_DEFINED 1 +#define XED_REG_XMM27_DEFINED 1 +#define XED_REG_XMM28_DEFINED 1 +#define XED_REG_XMM29_DEFINED 1 +#define XED_REG_XMM30_DEFINED 1 +#define XED_REG_XMM31_DEFINED 1 +#define XED_REG_YMM0_DEFINED 1 +#define XED_REG_YMM1_DEFINED 1 +#define XED_REG_YMM2_DEFINED 1 +#define XED_REG_YMM3_DEFINED 1 +#define XED_REG_YMM4_DEFINED 1 +#define XED_REG_YMM5_DEFINED 1 +#define XED_REG_YMM6_DEFINED 1 +#define XED_REG_YMM7_DEFINED 1 +#define XED_REG_YMM8_DEFINED 1 +#define XED_REG_YMM9_DEFINED 1 +#define XED_REG_YMM10_DEFINED 1 +#define XED_REG_YMM11_DEFINED 1 +#define XED_REG_YMM12_DEFINED 1 +#define XED_REG_YMM13_DEFINED 1 +#define XED_REG_YMM14_DEFINED 1 +#define XED_REG_YMM15_DEFINED 1 +#define XED_REG_YMM16_DEFINED 1 +#define XED_REG_YMM17_DEFINED 1 +#define XED_REG_YMM18_DEFINED 1 +#define XED_REG_YMM19_DEFINED 1 +#define XED_REG_YMM20_DEFINED 1 +#define XED_REG_YMM21_DEFINED 1 +#define XED_REG_YMM22_DEFINED 1 +#define XED_REG_YMM23_DEFINED 1 +#define XED_REG_YMM24_DEFINED 1 +#define XED_REG_YMM25_DEFINED 1 +#define XED_REG_YMM26_DEFINED 1 +#define XED_REG_YMM27_DEFINED 1 +#define XED_REG_YMM28_DEFINED 1 +#define XED_REG_YMM29_DEFINED 1 +#define XED_REG_YMM30_DEFINED 1 +#define XED_REG_YMM31_DEFINED 1 +#define XED_REG_ZMM0_DEFINED 1 +#define XED_REG_ZMM1_DEFINED 1 +#define XED_REG_ZMM2_DEFINED 1 +#define XED_REG_ZMM3_DEFINED 1 +#define XED_REG_ZMM4_DEFINED 1 +#define XED_REG_ZMM5_DEFINED 1 +#define XED_REG_ZMM6_DEFINED 1 +#define XED_REG_ZMM7_DEFINED 1 +#define XED_REG_ZMM8_DEFINED 1 +#define XED_REG_ZMM9_DEFINED 1 +#define XED_REG_ZMM10_DEFINED 1 +#define XED_REG_ZMM11_DEFINED 1 +#define XED_REG_ZMM12_DEFINED 1 +#define XED_REG_ZMM13_DEFINED 1 +#define XED_REG_ZMM14_DEFINED 1 +#define XED_REG_ZMM15_DEFINED 1 +#define XED_REG_ZMM16_DEFINED 1 +#define XED_REG_ZMM17_DEFINED 1 +#define XED_REG_ZMM18_DEFINED 1 +#define XED_REG_ZMM19_DEFINED 1 +#define XED_REG_ZMM20_DEFINED 1 +#define XED_REG_ZMM21_DEFINED 1 +#define XED_REG_ZMM22_DEFINED 1 +#define XED_REG_ZMM23_DEFINED 1 +#define XED_REG_ZMM24_DEFINED 1 +#define XED_REG_ZMM25_DEFINED 1 +#define XED_REG_ZMM26_DEFINED 1 +#define XED_REG_ZMM27_DEFINED 1 +#define XED_REG_ZMM28_DEFINED 1 +#define XED_REG_ZMM29_DEFINED 1 +#define XED_REG_ZMM30_DEFINED 1 +#define XED_REG_ZMM31_DEFINED 1 +#define XED_REG_LAST_DEFINED 1 +#define XED_REG_BNDCFG_FIRST_DEFINED 1 +#define XED_REG_BNDCFG_LAST_DEFINED 1 +#define XED_REG_BNDSTAT_FIRST_DEFINED 1 +#define XED_REG_BNDSTAT_LAST_DEFINED 1 +#define XED_REG_BOUND_FIRST_DEFINED 1 +#define XED_REG_BOUND_LAST_DEFINED 1 +#define XED_REG_CR_FIRST_DEFINED 1 +#define XED_REG_CR_LAST_DEFINED 1 +#define XED_REG_DR_FIRST_DEFINED 1 +#define XED_REG_DR_LAST_DEFINED 1 +#define XED_REG_FLAGS_FIRST_DEFINED 1 +#define XED_REG_FLAGS_LAST_DEFINED 1 +#define XED_REG_GPR16_FIRST_DEFINED 1 +#define XED_REG_GPR16_LAST_DEFINED 1 +#define XED_REG_GPR32_FIRST_DEFINED 1 +#define XED_REG_GPR32_LAST_DEFINED 1 +#define XED_REG_GPR64_FIRST_DEFINED 1 +#define XED_REG_GPR64_LAST_DEFINED 1 +#define XED_REG_GPR8_FIRST_DEFINED 1 +#define XED_REG_GPR8_LAST_DEFINED 1 +#define XED_REG_GPR8h_FIRST_DEFINED 1 +#define XED_REG_GPR8h_LAST_DEFINED 1 +#define XED_REG_INVALID_FIRST_DEFINED 1 +#define XED_REG_INVALID_LAST_DEFINED 1 +#define XED_REG_IP_FIRST_DEFINED 1 +#define XED_REG_IP_LAST_DEFINED 1 +#define XED_REG_MASK_FIRST_DEFINED 1 +#define XED_REG_MASK_LAST_DEFINED 1 +#define XED_REG_MMX_FIRST_DEFINED 1 +#define XED_REG_MMX_LAST_DEFINED 1 +#define XED_REG_MSR_FIRST_DEFINED 1 +#define XED_REG_MSR_LAST_DEFINED 1 +#define XED_REG_MXCSR_FIRST_DEFINED 1 +#define XED_REG_MXCSR_LAST_DEFINED 1 +#define XED_REG_PSEUDO_FIRST_DEFINED 1 +#define XED_REG_PSEUDO_LAST_DEFINED 1 +#define XED_REG_PSEUDOX87_FIRST_DEFINED 1 +#define XED_REG_PSEUDOX87_LAST_DEFINED 1 +#define XED_REG_SR_FIRST_DEFINED 1 +#define XED_REG_SR_LAST_DEFINED 1 +#define XED_REG_TMP_FIRST_DEFINED 1 +#define XED_REG_TMP_LAST_DEFINED 1 +#define XED_REG_TREG_FIRST_DEFINED 1 +#define XED_REG_TREG_LAST_DEFINED 1 +#define XED_REG_UIF_FIRST_DEFINED 1 +#define XED_REG_UIF_LAST_DEFINED 1 +#define XED_REG_X87_FIRST_DEFINED 1 +#define XED_REG_X87_LAST_DEFINED 1 +#define XED_REG_XCR_FIRST_DEFINED 1 +#define XED_REG_XCR_LAST_DEFINED 1 +#define XED_REG_XMM_FIRST_DEFINED 1 +#define XED_REG_XMM_LAST_DEFINED 1 +#define XED_REG_YMM_FIRST_DEFINED 1 +#define XED_REG_YMM_LAST_DEFINED 1 +#define XED_REG_ZMM_FIRST_DEFINED 1 +#define XED_REG_ZMM_LAST_DEFINED 1 +typedef enum { + XED_REG_INVALID, + XED_REG_BNDCFGU, + XED_REG_BNDSTATUS, + XED_REG_BND0, + XED_REG_BND1, + XED_REG_BND2, + XED_REG_BND3, + XED_REG_CR0, + XED_REG_CR1, + XED_REG_CR2, + XED_REG_CR3, + XED_REG_CR4, + XED_REG_CR5, + XED_REG_CR6, + XED_REG_CR7, + XED_REG_CR8, + XED_REG_CR9, + XED_REG_CR10, + XED_REG_CR11, + XED_REG_CR12, + XED_REG_CR13, + XED_REG_CR14, + XED_REG_CR15, + XED_REG_DR0, + XED_REG_DR1, + XED_REG_DR2, + XED_REG_DR3, + XED_REG_DR4, + XED_REG_DR5, + XED_REG_DR6, + XED_REG_DR7, + XED_REG_FLAGS, + XED_REG_EFLAGS, + XED_REG_RFLAGS, + XED_REG_AX, + XED_REG_CX, + XED_REG_DX, + XED_REG_BX, + XED_REG_SP, + XED_REG_BP, + XED_REG_SI, + XED_REG_DI, + XED_REG_R8W, + XED_REG_R9W, + XED_REG_R10W, + XED_REG_R11W, + XED_REG_R12W, + XED_REG_R13W, + XED_REG_R14W, + XED_REG_R15W, + XED_REG_EAX, + XED_REG_ECX, + XED_REG_EDX, + XED_REG_EBX, + XED_REG_ESP, + XED_REG_EBP, + XED_REG_ESI, + XED_REG_EDI, + XED_REG_R8D, + XED_REG_R9D, + XED_REG_R10D, + XED_REG_R11D, + XED_REG_R12D, + XED_REG_R13D, + XED_REG_R14D, + XED_REG_R15D, + XED_REG_RAX, + XED_REG_RCX, + XED_REG_RDX, + XED_REG_RBX, + XED_REG_RSP, + XED_REG_RBP, + XED_REG_RSI, + XED_REG_RDI, + XED_REG_R8, + XED_REG_R9, + XED_REG_R10, + XED_REG_R11, + XED_REG_R12, + XED_REG_R13, + XED_REG_R14, + XED_REG_R15, + XED_REG_AL, + XED_REG_CL, + XED_REG_DL, + XED_REG_BL, + XED_REG_SPL, + XED_REG_BPL, + XED_REG_SIL, + XED_REG_DIL, + XED_REG_R8B, + XED_REG_R9B, + XED_REG_R10B, + XED_REG_R11B, + XED_REG_R12B, + XED_REG_R13B, + XED_REG_R14B, + XED_REG_R15B, + XED_REG_AH, + XED_REG_CH, + XED_REG_DH, + XED_REG_BH, + XED_REG_ERROR, + XED_REG_RIP, + XED_REG_EIP, + XED_REG_IP, + XED_REG_K0, + XED_REG_K1, + XED_REG_K2, + XED_REG_K3, + XED_REG_K4, + XED_REG_K5, + XED_REG_K6, + XED_REG_K7, + XED_REG_MMX0, + XED_REG_MMX1, + XED_REG_MMX2, + XED_REG_MMX3, + XED_REG_MMX4, + XED_REG_MMX5, + XED_REG_MMX6, + XED_REG_MMX7, + XED_REG_SSP, + XED_REG_IA32_U_CET, + XED_REG_MXCSR, + XED_REG_STACKPUSH, + XED_REG_STACKPOP, + XED_REG_GDTR, + XED_REG_LDTR, + XED_REG_IDTR, + XED_REG_TR, + XED_REG_TSC, + XED_REG_TSCAUX, + XED_REG_MSRS, + XED_REG_FSBASE, + XED_REG_GSBASE, + XED_REG_TILECONFIG, + XED_REG_X87CONTROL, + XED_REG_X87STATUS, + XED_REG_X87TAG, + XED_REG_X87PUSH, + XED_REG_X87POP, + XED_REG_X87POP2, + XED_REG_X87OPCODE, + XED_REG_X87LASTCS, + XED_REG_X87LASTIP, + XED_REG_X87LASTDS, + XED_REG_X87LASTDP, + XED_REG_ES, + XED_REG_CS, + XED_REG_SS, + XED_REG_DS, + XED_REG_FS, + XED_REG_GS, + XED_REG_TMP0, + XED_REG_TMP1, + XED_REG_TMP2, + XED_REG_TMP3, + XED_REG_TMP4, + XED_REG_TMP5, + XED_REG_TMP6, + XED_REG_TMP7, + XED_REG_TMP8, + XED_REG_TMP9, + XED_REG_TMP10, + XED_REG_TMP11, + XED_REG_TMP12, + XED_REG_TMP13, + XED_REG_TMP14, + XED_REG_TMP15, + XED_REG_TMM0, + XED_REG_TMM1, + XED_REG_TMM2, + XED_REG_TMM3, + XED_REG_TMM4, + XED_REG_TMM5, + XED_REG_TMM6, + XED_REG_TMM7, + XED_REG_UIF, + XED_REG_ST0, + XED_REG_ST1, + XED_REG_ST2, + XED_REG_ST3, + XED_REG_ST4, + XED_REG_ST5, + XED_REG_ST6, + XED_REG_ST7, + XED_REG_XCR0, + XED_REG_XMM0, + XED_REG_XMM1, + XED_REG_XMM2, + XED_REG_XMM3, + XED_REG_XMM4, + XED_REG_XMM5, + XED_REG_XMM6, + XED_REG_XMM7, + XED_REG_XMM8, + XED_REG_XMM9, + XED_REG_XMM10, + XED_REG_XMM11, + XED_REG_XMM12, + XED_REG_XMM13, + XED_REG_XMM14, + XED_REG_XMM15, + XED_REG_XMM16, + XED_REG_XMM17, + XED_REG_XMM18, + XED_REG_XMM19, + XED_REG_XMM20, + XED_REG_XMM21, + XED_REG_XMM22, + XED_REG_XMM23, + XED_REG_XMM24, + XED_REG_XMM25, + XED_REG_XMM26, + XED_REG_XMM27, + XED_REG_XMM28, + XED_REG_XMM29, + XED_REG_XMM30, + XED_REG_XMM31, + XED_REG_YMM0, + XED_REG_YMM1, + XED_REG_YMM2, + XED_REG_YMM3, + XED_REG_YMM4, + XED_REG_YMM5, + XED_REG_YMM6, + XED_REG_YMM7, + XED_REG_YMM8, + XED_REG_YMM9, + XED_REG_YMM10, + XED_REG_YMM11, + XED_REG_YMM12, + XED_REG_YMM13, + XED_REG_YMM14, + XED_REG_YMM15, + XED_REG_YMM16, + XED_REG_YMM17, + XED_REG_YMM18, + XED_REG_YMM19, + XED_REG_YMM20, + XED_REG_YMM21, + XED_REG_YMM22, + XED_REG_YMM23, + XED_REG_YMM24, + XED_REG_YMM25, + XED_REG_YMM26, + XED_REG_YMM27, + XED_REG_YMM28, + XED_REG_YMM29, + XED_REG_YMM30, + XED_REG_YMM31, + XED_REG_ZMM0, + XED_REG_ZMM1, + XED_REG_ZMM2, + XED_REG_ZMM3, + XED_REG_ZMM4, + XED_REG_ZMM5, + XED_REG_ZMM6, + XED_REG_ZMM7, + XED_REG_ZMM8, + XED_REG_ZMM9, + XED_REG_ZMM10, + XED_REG_ZMM11, + XED_REG_ZMM12, + XED_REG_ZMM13, + XED_REG_ZMM14, + XED_REG_ZMM15, + XED_REG_ZMM16, + XED_REG_ZMM17, + XED_REG_ZMM18, + XED_REG_ZMM19, + XED_REG_ZMM20, + XED_REG_ZMM21, + XED_REG_ZMM22, + XED_REG_ZMM23, + XED_REG_ZMM24, + XED_REG_ZMM25, + XED_REG_ZMM26, + XED_REG_ZMM27, + XED_REG_ZMM28, + XED_REG_ZMM29, + XED_REG_ZMM30, + XED_REG_ZMM31, + XED_REG_LAST, + XED_REG_BNDCFG_FIRST=XED_REG_BNDCFGU, //< PSEUDO + XED_REG_BNDCFG_LAST=XED_REG_BNDCFGU, // +#include +#include "xed-reg-role-enum.h" + +typedef struct { + const char* name; + xed_reg_role_enum_t value; +} name_table_xed_reg_role_enum_t; +static const name_table_xed_reg_role_enum_t name_array_xed_reg_role_enum_t[] = { +{"INVALID", XED_REG_ROLE_INVALID}, +{"NORMAL", XED_REG_ROLE_NORMAL}, +{"SEGREG0", XED_REG_ROLE_SEGREG0}, +{"SEGREG1", XED_REG_ROLE_SEGREG1}, +{"BASE0", XED_REG_ROLE_BASE0}, +{"BASE1", XED_REG_ROLE_BASE1}, +{"INDEX", XED_REG_ROLE_INDEX}, +{"LAST", XED_REG_ROLE_LAST}, +{0, XED_REG_ROLE_LAST}, +}; + + +xed_reg_role_enum_t str2xed_reg_role_enum_t(const char* s) +{ + const name_table_xed_reg_role_enum_t* p = name_array_xed_reg_role_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_REG_ROLE_INVALID; +} + + +const char* xed_reg_role_enum_t2str(const xed_reg_role_enum_t p) +{ + xed_reg_role_enum_t type_idx = p; + if ( p > XED_REG_ROLE_LAST) type_idx = XED_REG_ROLE_LAST; + return name_array_xed_reg_role_enum_t[type_idx].name; +} + +xed_reg_role_enum_t xed_reg_role_enum_t_last(void) { + return XED_REG_ROLE_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_REG_ROLE_INVALID: + case XED_REG_ROLE_NORMAL: + case XED_REG_ROLE_SEGREG0: + case XED_REG_ROLE_SEGREG1: + case XED_REG_ROLE_BASE0: + case XED_REG_ROLE_BASE1: + case XED_REG_ROLE_INDEX: + case XED_REG_ROLE_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-reg-role-enum.h b/CodeVirtualizer/build/obj/xed-reg-role-enum.h new file mode 100644 index 0000000..cd8b757 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-reg-role-enum.h @@ -0,0 +1,43 @@ +/// @file xed-reg-role-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_REG_ROLE_ENUM_H) +# define XED_REG_ROLE_ENUM_H +#include "xed-common-hdrs.h" +#define XED_REG_ROLE_INVALID_DEFINED 1 +#define XED_REG_ROLE_NORMAL_DEFINED 1 +#define XED_REG_ROLE_SEGREG0_DEFINED 1 +#define XED_REG_ROLE_SEGREG1_DEFINED 1 +#define XED_REG_ROLE_BASE0_DEFINED 1 +#define XED_REG_ROLE_BASE1_DEFINED 1 +#define XED_REG_ROLE_INDEX_DEFINED 1 +#define XED_REG_ROLE_LAST_DEFINED 1 +typedef enum { + XED_REG_ROLE_INVALID, + XED_REG_ROLE_NORMAL, ///< Register is a normal register + XED_REG_ROLE_SEGREG0, ///< The segment register associated with the first memop + XED_REG_ROLE_SEGREG1, ///< The segment register associated with the second memop + XED_REG_ROLE_BASE0, ///< The base register associated with the first memop + XED_REG_ROLE_BASE1, ///< The base register associated with the second memop + XED_REG_ROLE_INDEX, ///< The index register associated with the first memop + XED_REG_ROLE_LAST +} xed_reg_role_enum_t; + +/// This converts strings to #xed_reg_role_enum_t types. +/// @param s A C-string. +/// @return #xed_reg_role_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_reg_role_enum_t str2xed_reg_role_enum_t(const char* s); +/// This converts strings to #xed_reg_role_enum_t types. +/// @param p An enumeration element of type xed_reg_role_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_reg_role_enum_t2str(const xed_reg_role_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_reg_role_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_reg_role_enum_t xed_reg_role_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed-rep-map.c b/CodeVirtualizer/build/obj/xed-rep-map.c new file mode 100644 index 0000000..5d7653f --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-rep-map.c @@ -0,0 +1,275 @@ +/// @file xed-rep-map.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +XED_DLL_EXPORT xed_iclass_enum_t xed_repe_map(xed_iclass_enum_t iclass) +{ + const xed_uint16_t lu_table[96] = { + /* 0xFFFF -> 0 */ 0xFFFF, 0, + /* 115 -> 1 */ 115, 698, + /* 113 -> 2 */ 113, 697, + /* 0xFFFF -> 3 */ 0xFFFF, 0, + /* 0xFFFF -> 4 */ 0xFFFF, 0, + /* 0xFFFF -> 5 */ 0xFFFF, 0, + /* 0xFFFF -> 6 */ 0xFFFF, 0, + /* 0xFFFF -> 7 */ 0xFFFF, 0, + /* 762 -> 8 */ 762, 701, + /* 0xFFFF -> 9 */ 0xFFFF, 0, + /* 0xFFFF -> 10 */ 0xFFFF, 0, + /* 0xFFFF -> 11 */ 0xFFFF, 0, + /* 0xFFFF -> 12 */ 0xFFFF, 0, + /* 0xFFFF -> 13 */ 0xFFFF, 0, + /* 0xFFFF -> 14 */ 0xFFFF, 0, + /* 0xFFFF -> 15 */ 0xFFFF, 0, + /* 0xFFFF -> 16 */ 0xFFFF, 0, + /* 0xFFFF -> 17 */ 0xFFFF, 0, + /* 0xFFFF -> 18 */ 0xFFFF, 0, + /* 763 -> 19 */ 763, 702, + /* 761 -> 20 */ 761, 700, + /* 0xFFFF -> 21 */ 0xFFFF, 0, + /* 0xFFFF -> 22 */ 0xFFFF, 0, + /* 117 -> 23 */ 117, 699, + /* 0xFFFF -> 24 */ 0xFFFF, 0, + /* 0xFFFF -> 25 */ 0xFFFF, 0, + /* 0xFFFF -> 26 */ 0xFFFF, 0, + /* 0xFFFF -> 27 */ 0xFFFF, 0, + /* 0xFFFF -> 28 */ 0xFFFF, 0, + /* 0xFFFF -> 29 */ 0xFFFF, 0, + /* 764 -> 30 */ 764, 703, + /* 0xFFFF -> 31 */ 0xFFFF, 0, + /* 0xFFFF -> 32 */ 0xFFFF, 0, + /* 0xFFFF -> 33 */ 0xFFFF, 0, + /* 0xFFFF -> 34 */ 0xFFFF, 0, + /* 0xFFFF -> 35 */ 0xFFFF, 0, + /* 0xFFFF -> 36 */ 0xFFFF, 0, + /* 0xFFFF -> 37 */ 0xFFFF, 0, + /* 0xFFFF -> 38 */ 0xFFFF, 0, + /* 0xFFFF -> 39 */ 0xFFFF, 0, + /* 0xFFFF -> 40 */ 0xFFFF, 0, + /* 0xFFFF -> 41 */ 0xFFFF, 0, + /* 0xFFFF -> 42 */ 0xFFFF, 0, + /* 0xFFFF -> 43 */ 0xFFFF, 0, + /* 0xFFFF -> 44 */ 0xFFFF, 0, + /* 0xFFFF -> 45 */ 0xFFFF, 0, + /* 0xFFFF -> 46 */ 0xFFFF, 0, + /* 112 -> 47 */ 112, 696, + }; + const xed_uint_t key = (xed_uint_t)iclass; + const xed_uint_t hash = ((11*key % 79) % 56); + if (hash <= 47) { + const xed_uint_t ek = lu_table[2*hash]; + if (ek == key) { + const xed_uint_t v = lu_table[2*hash+1]; + return (xed_iclass_enum_t) v; + } + } + return XED_ICLASS_INVALID; +} +XED_DLL_EXPORT xed_iclass_enum_t xed_repne_map(xed_iclass_enum_t iclass) +{ + const xed_uint16_t lu_table[96] = { + /* 0xFFFF -> 0 */ 0xFFFF, 0, + /* 115 -> 1 */ 115, 706, + /* 113 -> 2 */ 113, 705, + /* 0xFFFF -> 3 */ 0xFFFF, 0, + /* 0xFFFF -> 4 */ 0xFFFF, 0, + /* 0xFFFF -> 5 */ 0xFFFF, 0, + /* 0xFFFF -> 6 */ 0xFFFF, 0, + /* 0xFFFF -> 7 */ 0xFFFF, 0, + /* 762 -> 8 */ 762, 709, + /* 0xFFFF -> 9 */ 0xFFFF, 0, + /* 0xFFFF -> 10 */ 0xFFFF, 0, + /* 0xFFFF -> 11 */ 0xFFFF, 0, + /* 0xFFFF -> 12 */ 0xFFFF, 0, + /* 0xFFFF -> 13 */ 0xFFFF, 0, + /* 0xFFFF -> 14 */ 0xFFFF, 0, + /* 0xFFFF -> 15 */ 0xFFFF, 0, + /* 0xFFFF -> 16 */ 0xFFFF, 0, + /* 0xFFFF -> 17 */ 0xFFFF, 0, + /* 0xFFFF -> 18 */ 0xFFFF, 0, + /* 763 -> 19 */ 763, 710, + /* 761 -> 20 */ 761, 708, + /* 0xFFFF -> 21 */ 0xFFFF, 0, + /* 0xFFFF -> 22 */ 0xFFFF, 0, + /* 117 -> 23 */ 117, 707, + /* 0xFFFF -> 24 */ 0xFFFF, 0, + /* 0xFFFF -> 25 */ 0xFFFF, 0, + /* 0xFFFF -> 26 */ 0xFFFF, 0, + /* 0xFFFF -> 27 */ 0xFFFF, 0, + /* 0xFFFF -> 28 */ 0xFFFF, 0, + /* 0xFFFF -> 29 */ 0xFFFF, 0, + /* 764 -> 30 */ 764, 711, + /* 0xFFFF -> 31 */ 0xFFFF, 0, + /* 0xFFFF -> 32 */ 0xFFFF, 0, + /* 0xFFFF -> 33 */ 0xFFFF, 0, + /* 0xFFFF -> 34 */ 0xFFFF, 0, + /* 0xFFFF -> 35 */ 0xFFFF, 0, + /* 0xFFFF -> 36 */ 0xFFFF, 0, + /* 0xFFFF -> 37 */ 0xFFFF, 0, + /* 0xFFFF -> 38 */ 0xFFFF, 0, + /* 0xFFFF -> 39 */ 0xFFFF, 0, + /* 0xFFFF -> 40 */ 0xFFFF, 0, + /* 0xFFFF -> 41 */ 0xFFFF, 0, + /* 0xFFFF -> 42 */ 0xFFFF, 0, + /* 0xFFFF -> 43 */ 0xFFFF, 0, + /* 0xFFFF -> 44 */ 0xFFFF, 0, + /* 0xFFFF -> 45 */ 0xFFFF, 0, + /* 0xFFFF -> 46 */ 0xFFFF, 0, + /* 112 -> 47 */ 112, 704, + }; + const xed_uint_t key = (xed_uint_t)iclass; + const xed_uint_t hash = ((11*key % 79) % 56); + if (hash <= 47) { + const xed_uint_t ek = lu_table[2*hash]; + if (ek == key) { + const xed_uint_t v = lu_table[2*hash+1]; + return (xed_iclass_enum_t) v; + } + } + return XED_ICLASS_INVALID; +} +XED_DLL_EXPORT xed_iclass_enum_t xed_rep_map(xed_iclass_enum_t iclass) +{ + const xed_uint16_t lu_table[112] = { + /* 0 -> 0 */ 0, 737, + /* 0xFFFF -> 1 */ 0xFFFF, 0, + /* 0xFFFF -> 2 */ 0xFFFF, 0, + /* 819 -> 3 */ 819, 727, + /* 0xFFFF -> 4 */ 0xFFFF, 0, + /* 0xFFFF -> 5 */ 0xFFFF, 0, + /* 295 -> 6 */ 295, 714, + /* 0xFFFF -> 7 */ 0xFFFF, 0, + /* 0xFFFF -> 8 */ 0xFFFF, 0, + /* 403 -> 9 */ 403, 718, + /* 401 -> 10 */ 401, 716, + /* 0xFFFF -> 11 */ 0xFFFF, 0, + /* 0xFFFF -> 12 */ 0xFFFF, 0, + /* 0xFFFF -> 13 */ 0xFFFF, 0, + /* 820 -> 14 */ 820, 728, + /* 461 -> 15 */ 461, 722, + /* 0xFFFF -> 16 */ 0xFFFF, 0, + /* 0xFFFF -> 17 */ 0xFFFF, 0, + /* 0xFFFF -> 18 */ 0xFFFF, 0, + /* 0xFFFF -> 19 */ 0xFFFF, 0, + /* 0xFFFF -> 20 */ 0xFFFF, 0, + /* 402 -> 21 */ 402, 717, + /* 0xFFFF -> 22 */ 0xFFFF, 0, + /* 0xFFFF -> 23 */ 0xFFFF, 0, + /* 0xFFFF -> 24 */ 0xFFFF, 0, + /* 821 -> 25 */ 821, 729, + /* 0xFFFF -> 26 */ 0xFFFF, 0, + /* 498 -> 27 */ 498, 724, + /* 0xFFFF -> 28 */ 0xFFFF, 0, + /* 0xFFFF -> 29 */ 0xFFFF, 0, + /* 0xFFFF -> 30 */ 0xFFFF, 0, + /* 0xFFFF -> 31 */ 0xFFFF, 0, + /* 0xFFFF -> 32 */ 0xFFFF, 0, + /* 1741 -> 33 */ 1741, 738, + /* 0xFFFF -> 34 */ 0xFFFF, 0, + /* 0xFFFF -> 35 */ 0xFFFF, 0, + /* 822 -> 36 */ 822, 730, + /* 463 -> 37 */ 463, 723, + /* 499 -> 38 */ 499, 725, + /* 456 -> 39 */ 456, 720, + /* 0xFFFF -> 40 */ 0xFFFF, 0, + /* 291 -> 41 */ 291, 712, + /* 0xFFFF -> 42 */ 0xFFFF, 0, + /* 0xFFFF -> 43 */ 0xFFFF, 0, + /* 0xFFFF -> 44 */ 0xFFFF, 0, + /* 0xFFFF -> 45 */ 0xFFFF, 0, + /* 0xFFFF -> 46 */ 0xFFFF, 0, + /* 0xFFFF -> 47 */ 0xFFFF, 0, + /* 0xFFFF -> 48 */ 0xFFFF, 0, + /* 500 -> 49 */ 500, 726, + /* 457 -> 50 */ 457, 721, + /* 0xFFFF -> 51 */ 0xFFFF, 0, + /* 292 -> 52 */ 292, 713, + /* 0xFFFF -> 53 */ 0xFFFF, 0, + /* 0xFFFF -> 54 */ 0xFFFF, 0, + /* 400 -> 55 */ 400, 715, + }; + const xed_uint_t key = (xed_uint_t)iclass; + const xed_uint_t hash = ((11*key % 79) % 56); + if (hash <= 55) { + const xed_uint_t ek = lu_table[2*hash]; + if (ek == key) { + const xed_uint_t v = lu_table[2*hash+1]; + return (xed_iclass_enum_t) v; + } + } + return XED_ICLASS_INVALID; +} +XED_DLL_EXPORT xed_iclass_enum_t xed_norep_map(xed_iclass_enum_t iclass) +{ + const xed_uint16_t lu_table[43] = { + /* 696 -> 0 */ 112, + /* 697 -> 1 */ 113, + /* 698 -> 2 */ 115, + /* 699 -> 3 */ 117, + /* 700 -> 4 */ 761, + /* 701 -> 5 */ 762, + /* 702 -> 6 */ 763, + /* 703 -> 7 */ 764, + /* 704 -> 8 */ 112, + /* 705 -> 9 */ 113, + /* 706 -> 10 */ 115, + /* 707 -> 11 */ 117, + /* 708 -> 12 */ 761, + /* 709 -> 13 */ 762, + /* 710 -> 14 */ 763, + /* 711 -> 15 */ 764, + /* 712 -> 16 */ 291, + /* 713 -> 17 */ 292, + /* 714 -> 18 */ 295, + /* 715 -> 19 */ 400, + /* 716 -> 20 */ 401, + /* 717 -> 21 */ 402, + /* 718 -> 22 */ 403, + /* 719 -> 23 */ 0, + /* 720 -> 24 */ 456, + /* 721 -> 25 */ 457, + /* 722 -> 26 */ 461, + /* 723 -> 27 */ 463, + /* 724 -> 28 */ 498, + /* 725 -> 29 */ 499, + /* 726 -> 30 */ 500, + /* 727 -> 31 */ 819, + /* 728 -> 32 */ 820, + /* 729 -> 33 */ 821, + /* 730 -> 34 */ 822, + /* 731 -> 35 */ 0, + /* 732 -> 36 */ 0, + /* 733 -> 37 */ 0, + /* 734 -> 38 */ 0, + /* 735 -> 39 */ 0, + /* 736 -> 40 */ 0, + /* 737 -> 41 */ 0, + /* 738 -> 42 */ 1741, + }; + const xed_uint_t key = (xed_uint_t)iclass; + const xed_uint_t hash = key - 696; + if (hash <= 42) { + const xed_uint_t v = lu_table[hash]; + return (xed_iclass_enum_t) v; + } + return XED_ICLASS_INVALID; +} diff --git a/CodeVirtualizer/build/obj/xed-syntax-enum.c b/CodeVirtualizer/build/obj/xed-syntax-enum.c new file mode 100644 index 0000000..0440374 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-syntax-enum.c @@ -0,0 +1,64 @@ +/// @file xed-syntax-enum.c + +// This file was automatically generated. +// Do not edit this file. + +#include +#include +#include "xed-syntax-enum.h" + +typedef struct { + const char* name; + xed_syntax_enum_t value; +} name_table_xed_syntax_enum_t; +static const name_table_xed_syntax_enum_t name_array_xed_syntax_enum_t[] = { +{"INVALID", XED_SYNTAX_INVALID}, +{"XED", XED_SYNTAX_XED}, +{"ATT", XED_SYNTAX_ATT}, +{"INTEL", XED_SYNTAX_INTEL}, +{"LAST", XED_SYNTAX_LAST}, +{0, XED_SYNTAX_LAST}, +}; + + +xed_syntax_enum_t str2xed_syntax_enum_t(const char* s) +{ + const name_table_xed_syntax_enum_t* p = name_array_xed_syntax_enum_t; + while( p->name ) { + if (strcmp(p->name,s) == 0) { + return p->value; + } + p++; + } + + + return XED_SYNTAX_INVALID; +} + + +const char* xed_syntax_enum_t2str(const xed_syntax_enum_t p) +{ + xed_syntax_enum_t type_idx = p; + if ( p > XED_SYNTAX_LAST) type_idx = XED_SYNTAX_LAST; + return name_array_xed_syntax_enum_t[type_idx].name; +} + +xed_syntax_enum_t xed_syntax_enum_t_last(void) { + return XED_SYNTAX_LAST; +} + +/* + +Here is a skeleton switch statement embedded in a comment + + + switch(p) { + case XED_SYNTAX_INVALID: + case XED_SYNTAX_XED: + case XED_SYNTAX_ATT: + case XED_SYNTAX_INTEL: + case XED_SYNTAX_LAST: + default: + xed_assert(0); + } +*/ diff --git a/CodeVirtualizer/build/obj/xed-syntax-enum.h b/CodeVirtualizer/build/obj/xed-syntax-enum.h new file mode 100644 index 0000000..daefdd4 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed-syntax-enum.h @@ -0,0 +1,37 @@ +/// @file xed-syntax-enum.h + +// This file was automatically generated. +// Do not edit this file. + +#if !defined(XED_SYNTAX_ENUM_H) +# define XED_SYNTAX_ENUM_H +#include "xed-common-hdrs.h" +#define XED_SYNTAX_INVALID_DEFINED 1 +#define XED_SYNTAX_XED_DEFINED 1 +#define XED_SYNTAX_ATT_DEFINED 1 +#define XED_SYNTAX_INTEL_DEFINED 1 +#define XED_SYNTAX_LAST_DEFINED 1 +typedef enum { + XED_SYNTAX_INVALID, + XED_SYNTAX_XED, ///< XED disassembly syntax + XED_SYNTAX_ATT, ///< ATT SYSV disassembly syntax + XED_SYNTAX_INTEL, ///< Intel disassembly syntax + XED_SYNTAX_LAST +} xed_syntax_enum_t; + +/// This converts strings to #xed_syntax_enum_t types. +/// @param s A C-string. +/// @return #xed_syntax_enum_t +/// @ingroup ENUM +XED_DLL_EXPORT xed_syntax_enum_t str2xed_syntax_enum_t(const char* s); +/// This converts strings to #xed_syntax_enum_t types. +/// @param p An enumeration element of type xed_syntax_enum_t. +/// @return string +/// @ingroup ENUM +XED_DLL_EXPORT const char* xed_syntax_enum_t2str(const xed_syntax_enum_t p); + +/// Returns the last element of the enumeration +/// @return xed_syntax_enum_t The last element of the enumeration. +/// @ingroup ENUM +XED_DLL_EXPORT xed_syntax_enum_t xed_syntax_enum_t_last(void); +#endif diff --git a/CodeVirtualizer/build/obj/xed3-operand-lu.c b/CodeVirtualizer/build/obj/xed3-operand-lu.c new file mode 100644 index 0000000..6cfbb4c --- /dev/null +++ b/CodeVirtualizer/build/obj/xed3-operand-lu.c @@ -0,0 +1,934 @@ +/// @file xed3-operand-lu.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-operand-lu.h" +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_OSZ_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((1)); +key += (xed3_operand_get_rep(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +key += (xed3_operand_get_rep(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((1)); +key += (xed3_operand_get_rep(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_rep(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REP_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +key += (xed3_operand_get_rep(d)) << ((4)); +key += (xed3_operand_get_rexw(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_REP_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((1)); +key += (xed3_operand_get_rep(d)) << ((4)); +key += (xed3_operand_get_rm(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_MODE_OSZ_REG_REP_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_osz(d)) << ((5)); +key += (xed3_operand_get_reg(d)) << ((6)); +key += (xed3_operand_get_rep(d)) << ((9)); +key += (xed3_operand_get_rm(d)) << ((11)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_REP_WBNOINVD(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_rep(d)) << ((0)); +key += (xed3_operand_get_wbnoinvd(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD_MODE_MPXMODE_OSZ_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((0)); +key += (xed3_operand_get_mod(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((4)); +key += (xed3_operand_get_mpxmode(d)) << ((6)); +key += (xed3_operand_get_osz(d)) << ((7)); +key += (xed3_operand_get_rep(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_CLDEMOTE_MOD3_OSZ_REG_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_cldemote(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((2)); +key += (xed3_operand_get_reg(d)) << ((3)); +key += (xed3_operand_get_rep(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_CET_MOD3_MODE_OSZ_REG_REP_REXW_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_cet(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_mode(d)) << ((2)); +key += (xed3_operand_get_osz(d)) << ((4)); +key += (xed3_operand_get_reg(d)) << ((5)); +key += (xed3_operand_get_rep(d)) << ((8)); +key += (xed3_operand_get_rexw(d)) << ((10)); +key += (xed3_operand_get_rm(d)) << ((11)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_OSZ_REP_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((1)); +key += (xed3_operand_get_rep(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_OSZ_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_osz(d)) << ((0)); +key += (xed3_operand_get_rep(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_OSZ_REG_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((2)); +key += (xed3_operand_get_rep(d)) << ((5)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +key += (xed3_operand_get_reg(d)) << ((4)); +key += (xed3_operand_get_rep(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD_REG_REP_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((0)); +key += (xed3_operand_get_mod(d)) << ((2)); +key += (xed3_operand_get_reg(d)) << ((4)); +key += (xed3_operand_get_rep(d)) << ((7)); +key += (xed3_operand_get_rm(d)) << ((9)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD_REG_REP_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((2)); +key += (xed3_operand_get_rep(d)) << ((5)); +key += (xed3_operand_get_rm(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_lock(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REP_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +key += (xed3_operand_get_reg(d)) << ((4)); +key += (xed3_operand_get_rep(d)) << ((7)); +key += (xed3_operand_get_rexw(d)) << ((9)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3_REG(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_lock(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REP_TZCNT(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_rep(d)) << ((1)); +key += (xed3_operand_get_tzcnt(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_LZCNT_MOD3_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_lzcnt(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rep(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3_MODE_OSZ_REG_REP_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_lock(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_mode(d)) << ((2)); +key += (xed3_operand_get_osz(d)) << ((4)); +key += (xed3_operand_get_reg(d)) << ((5)); +key += (xed3_operand_get_rep(d)) << ((8)); +key += (xed3_operand_get_rexw(d)) << ((10)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD_MODE_SHORT_UD0(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod(d)) << ((0)); +key += (xed3_operand_get_mode_short_ud0(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_OSZ(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_rep(d)) << ((0)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_OSZ_REP_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((2)); +key += (xed3_operand_get_rep(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((5)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_LOCK_MOD3_MODE_REG(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_lock(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_mode(d)) << ((2)); +key += (xed3_operand_get_reg(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_P4_REP_REXB_SRM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_p4(d)) << ((0)); +key += (xed3_operand_get_rep(d)) << ((1)); +key += (xed3_operand_get_rexb(d)) << ((3)); +key += (xed3_operand_get_srm(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_REP_REXB_SRM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_rep(d)) << ((0)); +key += (xed3_operand_get_rexb(d)) << ((2)); +key += (xed3_operand_get_srm(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MODE_OSZ_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mode(d)) << ((0)); +key += (xed3_operand_get_osz(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((1)); +key += (xed3_operand_get_rm(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REXW_RM(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +key += (xed3_operand_get_reg(d)) << ((4)); +key += (xed3_operand_get_rexw(d)) << ((7)); +key += (xed3_operand_get_rm(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_OSZ_REG_REXW(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_osz(d)) << ((3)); +key += (xed3_operand_get_reg(d)) << ((4)); +key += (xed3_operand_get_rexw(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MODEP5_REP(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_modep5(d)) << ((0)); +key += (xed3_operand_get_rep(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MODE(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_vex_prefix(d)) << ((1)); +key += (xed3_operand_get_vl(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((1)); +key += (xed3_operand_get_vex_prefix(d)) << ((2)); +key += (xed3_operand_get_vl(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((1)); +key += (xed3_operand_get_vexdest210_7(d)) << ((2)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +key += (xed3_operand_get_vex_prefix(d)) << ((4)); +key += (xed3_operand_get_vl(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_vexdest210_7(d)) << ((1)); +key += (xed3_operand_get_vexdest3(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((3)); +key += (xed3_operand_get_vl(d)) << ((5)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REG_REXW_RM_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((6)); +key += (xed3_operand_get_rm(d)) << ((7)); +key += (xed3_operand_get_vexdest210_7(d)) << ((10)); +key += (xed3_operand_get_vexdest3(d)) << ((11)); +key += (xed3_operand_get_vex_prefix(d)) << ((12)); +key += (xed3_operand_get_vl(d)) << ((14)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_rm4(d)) << ((4)); +key += (xed3_operand_get_vexdest210_7(d)) << ((5)); +key += (xed3_operand_get_vexdest3(d)) << ((6)); +key += (xed3_operand_get_vex_prefix(d)) << ((7)); +key += (xed3_operand_get_vl(d)) << ((9)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vex_prefix(d)) << ((4)); +key += (xed3_operand_get_vl(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_rm4(d)) << ((4)); +key += (xed3_operand_get_vex_prefix(d)) << ((5)); +key += (xed3_operand_get_vl(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REXW_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_rexw(d)) << ((1)); +key += (xed3_operand_get_vex_prefix(d)) << ((2)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REG_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((6)); +key += (xed3_operand_get_vex_prefix(d)) << ((7)); +key += (xed3_operand_get_vl(d)) << ((9)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_vex_prefix(d)) << ((1)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vexdest210_7(d)) << ((4)); +key += (xed3_operand_get_vexdest3(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vex_prefix(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vexdest210_7(d)) << ((4)); +key += (xed3_operand_get_vexdest3(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_VEXDEST210_7_VEXDEST3_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_vexdest210_7(d)) << ((1)); +key += (xed3_operand_get_vexdest3(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((1)); +key += (xed3_operand_get_vex_prefix(d)) << ((4)); +key += (xed3_operand_get_vl(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_vexdest210_7(d)) << ((0)); +key += (xed3_operand_get_vexdest3(d)) << ((1)); +key += (xed3_operand_get_vex_prefix(d)) << ((2)); +key += (xed3_operand_get_vl(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_REG_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_reg(d)) << ((1)); +key += (xed3_operand_get_vexdest210_7(d)) << ((4)); +key += (xed3_operand_get_vexdest3(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_vex_prefix(d)) << ((2)); +key += (xed3_operand_get_vl(d)) << ((4)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((3)); +key += (xed3_operand_get_vl(d)) << ((5)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vexdest210_7(d)) << ((3)); +key += (xed3_operand_get_vexdest3(d)) << ((4)); +key += (xed3_operand_get_vexdest4(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +key += (xed3_operand_get_zeroing(d)) << ((10)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vexdest210_7(d)) << ((3)); +key += (xed3_operand_get_vexdest3(d)) << ((4)); +key += (xed3_operand_get_vexdest4(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_vexdest210_7(d)) << ((2)); +key += (xed3_operand_get_vexdest3(d)) << ((3)); +key += (xed3_operand_get_vexdest4(d)) << ((4)); +key += (xed3_operand_get_vex_prefix(d)) << ((5)); +key += (xed3_operand_get_vl(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((3)); +key += (xed3_operand_get_vl(d)) << ((5)); +key += (xed3_operand_get_zeroing(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vexdest210_7(d)) << ((4)); +key += (xed3_operand_get_vexdest3(d)) << ((5)); +key += (xed3_operand_get_vexdest4(d)) << ((6)); +key += (xed3_operand_get_vex_prefix(d)) << ((7)); +key += (xed3_operand_get_vl(d)) << ((9)); +key += (xed3_operand_get_zeroing(d)) << ((11)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((3)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vex_prefix(d)) << ((4)); +key += (xed3_operand_get_vl(d)) << ((6)); +key += (xed3_operand_get_zeroing(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_mode(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((4)); +key += (xed3_operand_get_vexdest210_7(d)) << ((5)); +key += (xed3_operand_get_vexdest3(d)) << ((6)); +key += (xed3_operand_get_vexdest4(d)) << ((7)); +key += (xed3_operand_get_vex_prefix(d)) << ((8)); +key += (xed3_operand_get_vl(d)) << ((10)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((4)); +key += (xed3_operand_get_rm4(d)) << ((5)); +key += (xed3_operand_get_vexdest210_7(d)) << ((6)); +key += (xed3_operand_get_vexdest3(d)) << ((7)); +key += (xed3_operand_get_vex_prefix(d)) << ((8)); +key += (xed3_operand_get_vl(d)) << ((10)); +key += (xed3_operand_get_zeroing(d)) << ((12)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_ASZ_NONTERM_EASZ_MOD3_REG_REXW_RM4_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed_lookup_function_ASZ_NONTERM_EASZ_getter(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((3)); +key += (xed3_operand_get_reg(d)) << ((4)); +key += (xed3_operand_get_rexw(d)) << ((7)); +key += (xed3_operand_get_rm4(d)) << ((8)); +key += (xed3_operand_get_vexdest210_7(d)) << ((9)); +key += (xed3_operand_get_vexdest3(d)) << ((10)); +key += (xed3_operand_get_vex_prefix(d)) << ((11)); +key += (xed3_operand_get_vl(d)) << ((13)); +key += (xed3_operand_get_zeroing(d)) << ((15)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((3)); +key += (xed3_operand_get_vl(d)) << ((5)); +key += (xed3_operand_get_zeroing(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_vexdest210_7(d)) << ((3)); +key += (xed3_operand_get_vexdest3(d)) << ((4)); +key += (xed3_operand_get_vexdest4(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +key += (xed3_operand_get_zeroing(d)) << ((10)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((5)); +key += (xed3_operand_get_vexdest210_7(d)) << ((6)); +key += (xed3_operand_get_vexdest3(d)) << ((7)); +key += (xed3_operand_get_vexdest4(d)) << ((8)); +key += (xed3_operand_get_vex_prefix(d)) << ((9)); +key += (xed3_operand_get_vl(d)) << ((11)); +key += (xed3_operand_get_zeroing(d)) << ((13)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +key += (xed3_operand_get_zeroing(d)) << ((10)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vexdest210_7(d)) << ((3)); +key += (xed3_operand_get_vexdest3(d)) << ((4)); +key += (xed3_operand_get_vexdest4(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_zeroing(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_rexw(d)) << ((2)); +key += (xed3_operand_get_vexdest210_7(d)) << ((3)); +key += (xed3_operand_get_vexdest3(d)) << ((4)); +key += (xed3_operand_get_vexdest4(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXW_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_zeroing(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((5)); +key += (xed3_operand_get_rexw(d)) << ((6)); +key += (xed3_operand_get_vexdest210_7(d)) << ((7)); +key += (xed3_operand_get_vexdest3(d)) << ((8)); +key += (xed3_operand_get_vexdest4(d)) << ((9)); +key += (xed3_operand_get_vex_prefix(d)) << ((10)); +key += (xed3_operand_get_zeroing(d)) << ((12)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((3)); +key += (xed3_operand_get_vexdest210_7(d)) << ((4)); +key += (xed3_operand_get_vexdest3(d)) << ((5)); +key += (xed3_operand_get_vexdest4(d)) << ((6)); +key += (xed3_operand_get_vex_prefix(d)) << ((7)); +key += (xed3_operand_get_zeroing(d)) << ((9)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_REXW_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((5)); +key += (xed3_operand_get_rexw(d)) << ((6)); +key += (xed3_operand_get_vexdest210_7(d)) << ((7)); +key += (xed3_operand_get_vexdest3(d)) << ((8)); +key += (xed3_operand_get_vexdest4(d)) << ((9)); +key += (xed3_operand_get_vex_prefix(d)) << ((10)); +key += (xed3_operand_get_vl(d)) << ((12)); +key += (xed3_operand_get_zeroing(d)) << ((14)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_vex_prefix(d)) << ((2)); +key += (xed3_operand_get_vl(d)) << ((4)); +key += (xed3_operand_get_zeroing(d)) << ((6)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REG_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((2)); +key += (xed3_operand_get_vex_prefix(d)) << ((5)); +key += (xed3_operand_get_vl(d)) << ((7)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MOD3_REG_REXW_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mod3(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((2)); +key += (xed3_operand_get_rexw(d)) << ((5)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_REG_REXW_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_reg(d)) << ((3)); +key += (xed3_operand_get_rexw(d)) << ((6)); +key += (xed3_operand_get_vex_prefix(d)) << ((7)); +key += (xed3_operand_get_vl(d)) << ((9)); +key += (xed3_operand_get_zeroing(d)) << ((11)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_BCRC_MASK_ZERO_MOD3_MODE_REXRR_VEXDEST210_7_VEXDEST3_VEXDEST4_VEX_PREFIX_VL_ZEROING(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_bcrc(d)) << ((0)); +key += (xed3_operand_get_mask_zero(d)) << ((1)); +key += (xed3_operand_get_mod3(d)) << ((2)); +key += (xed3_operand_get_mode(d)) << ((3)); +key += (xed3_operand_get_rexrr(d)) << ((5)); +key += (xed3_operand_get_vexdest210_7(d)) << ((6)); +key += (xed3_operand_get_vexdest3(d)) << ((7)); +key += (xed3_operand_get_vexdest4(d)) << ((8)); +key += (xed3_operand_get_vex_prefix(d)) << ((9)); +key += (xed3_operand_get_vl(d)) << ((11)); +key += (xed3_operand_get_zeroing(d)) << ((13)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_REG_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_reg(d)) << ((3)); +key += (xed3_operand_get_vex_prefix(d)) << ((6)); +key += (xed3_operand_get_vl(d)) << ((8)); +return key; +} +XED_NOINLINE xed_uint64_t xed_dec_lu_MOD3_MODE_VEXDEST210_7_VEXDEST3_VEX_PREFIX_VL(const xed_decoded_inst_t* d) +{ +xed_uint64_t key = 0; +key += (xed3_operand_get_mod3(d)) << ((0)); +key += (xed3_operand_get_mode(d)) << ((1)); +key += (xed3_operand_get_vexdest210_7(d)) << ((3)); +key += (xed3_operand_get_vexdest3(d)) << ((4)); +key += (xed3_operand_get_vex_prefix(d)) << ((5)); +key += (xed3_operand_get_vl(d)) << ((7)); +return key; +} diff --git a/CodeVirtualizer/build/obj/xed3-phash-lu-vv0.c b/CodeVirtualizer/build/obj/xed3-phash-lu-vv0.c new file mode 100644 index 0000000..134f263 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed3-phash-lu-vv0.c @@ -0,0 +1,1314 @@ +/// @file xed3-phash-lu-vv0.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-phash-vv0.h" +const xed3_find_func_t xed3_phash_vv0_map_amd_3dnow[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ xed3_phash_find_mapamd_3dnow_opcode0xc_vv0, +/*opcode 0xd*/ xed3_phash_find_mapamd_3dnow_opcode0xd_vv0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ xed3_phash_find_mapamd_3dnow_opcode0x1c_vv0, +/*opcode 0x1d*/ xed3_phash_find_mapamd_3dnow_opcode0x1d_vv0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ xed3_phash_find_mapamd_3dnow_opcode0x8a_vv0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ xed3_phash_find_mapamd_3dnow_opcode0x8e_vv0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ xed3_phash_find_mapamd_3dnow_opcode0x90_vv0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ xed3_phash_find_mapamd_3dnow_opcode0x94_vv0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ xed3_phash_find_mapamd_3dnow_opcode0x96_vv0, +/*opcode 0x97*/ xed3_phash_find_mapamd_3dnow_opcode0x97_vv0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ xed3_phash_find_mapamd_3dnow_opcode0x9a_vv0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ xed3_phash_find_mapamd_3dnow_opcode0x9e_vv0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ xed3_phash_find_mapamd_3dnow_opcode0xa0_vv0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ xed3_phash_find_mapamd_3dnow_opcode0xa4_vv0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ xed3_phash_find_mapamd_3dnow_opcode0xa6_vv0, +/*opcode 0xa7*/ xed3_phash_find_mapamd_3dnow_opcode0xa7_vv0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ xed3_phash_find_mapamd_3dnow_opcode0xaa_vv0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ xed3_phash_find_mapamd_3dnow_opcode0xae_vv0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ xed3_phash_find_mapamd_3dnow_opcode0xb0_vv0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ xed3_phash_find_mapamd_3dnow_opcode0xb4_vv0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ xed3_phash_find_mapamd_3dnow_opcode0xb6_vv0, +/*opcode 0xb7*/ xed3_phash_find_mapamd_3dnow_opcode0xb7_vv0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ xed3_phash_find_mapamd_3dnow_opcode0xbb_vv0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ xed3_phash_find_mapamd_3dnow_opcode0xbf_vv0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv0_map_legacy_map0[256] = { +/*opcode 0x0*/ xed3_phash_find_maplegacy_map0_opcode0x0_vv0, +/*opcode 0x1*/ xed3_phash_find_maplegacy_map0_opcode0x1_vv0, +/*opcode 0x2*/ xed3_phash_find_maplegacy_map0_opcode0x2_vv0, +/*opcode 0x3*/ xed3_phash_find_maplegacy_map0_opcode0x3_vv0, +/*opcode 0x4*/ xed3_phash_find_maplegacy_map0_opcode0x4_vv0, +/*opcode 0x5*/ xed3_phash_find_maplegacy_map0_opcode0x5_vv0, +/*opcode 0x6*/ xed3_phash_find_maplegacy_map0_opcode0x6_vv0, +/*opcode 0x7*/ xed3_phash_find_maplegacy_map0_opcode0x7_vv0, +/*opcode 0x8*/ xed3_phash_find_maplegacy_map0_opcode0x8_vv0, +/*opcode 0x9*/ xed3_phash_find_maplegacy_map0_opcode0x9_vv0, +/*opcode 0xa*/ xed3_phash_find_maplegacy_map0_opcode0xa_vv0, +/*opcode 0xb*/ xed3_phash_find_maplegacy_map0_opcode0xb_vv0, +/*opcode 0xc*/ xed3_phash_find_maplegacy_map0_opcode0xc_vv0, +/*opcode 0xd*/ xed3_phash_find_maplegacy_map0_opcode0xd_vv0, +/*opcode 0xe*/ xed3_phash_find_maplegacy_map0_opcode0xe_vv0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_maplegacy_map0_opcode0x10_vv0, +/*opcode 0x11*/ xed3_phash_find_maplegacy_map0_opcode0x11_vv0, +/*opcode 0x12*/ xed3_phash_find_maplegacy_map0_opcode0x12_vv0, +/*opcode 0x13*/ xed3_phash_find_maplegacy_map0_opcode0x13_vv0, +/*opcode 0x14*/ xed3_phash_find_maplegacy_map0_opcode0x14_vv0, +/*opcode 0x15*/ xed3_phash_find_maplegacy_map0_opcode0x15_vv0, +/*opcode 0x16*/ xed3_phash_find_maplegacy_map0_opcode0x16_vv0, +/*opcode 0x17*/ xed3_phash_find_maplegacy_map0_opcode0x17_vv0, +/*opcode 0x18*/ xed3_phash_find_maplegacy_map0_opcode0x18_vv0, +/*opcode 0x19*/ xed3_phash_find_maplegacy_map0_opcode0x19_vv0, +/*opcode 0x1a*/ xed3_phash_find_maplegacy_map0_opcode0x1a_vv0, +/*opcode 0x1b*/ xed3_phash_find_maplegacy_map0_opcode0x1b_vv0, +/*opcode 0x1c*/ xed3_phash_find_maplegacy_map0_opcode0x1c_vv0, +/*opcode 0x1d*/ xed3_phash_find_maplegacy_map0_opcode0x1d_vv0, +/*opcode 0x1e*/ xed3_phash_find_maplegacy_map0_opcode0x1e_vv0, +/*opcode 0x1f*/ xed3_phash_find_maplegacy_map0_opcode0x1f_vv0, +/*opcode 0x20*/ xed3_phash_find_maplegacy_map0_opcode0x20_vv0, +/*opcode 0x21*/ xed3_phash_find_maplegacy_map0_opcode0x21_vv0, +/*opcode 0x22*/ xed3_phash_find_maplegacy_map0_opcode0x22_vv0, +/*opcode 0x23*/ xed3_phash_find_maplegacy_map0_opcode0x23_vv0, +/*opcode 0x24*/ xed3_phash_find_maplegacy_map0_opcode0x24_vv0, +/*opcode 0x25*/ xed3_phash_find_maplegacy_map0_opcode0x25_vv0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ xed3_phash_find_maplegacy_map0_opcode0x27_vv0, +/*opcode 0x28*/ xed3_phash_find_maplegacy_map0_opcode0x28_vv0, +/*opcode 0x29*/ xed3_phash_find_maplegacy_map0_opcode0x29_vv0, +/*opcode 0x2a*/ xed3_phash_find_maplegacy_map0_opcode0x2a_vv0, +/*opcode 0x2b*/ xed3_phash_find_maplegacy_map0_opcode0x2b_vv0, +/*opcode 0x2c*/ xed3_phash_find_maplegacy_map0_opcode0x2c_vv0, +/*opcode 0x2d*/ xed3_phash_find_maplegacy_map0_opcode0x2d_vv0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ xed3_phash_find_maplegacy_map0_opcode0x2f_vv0, +/*opcode 0x30*/ xed3_phash_find_maplegacy_map0_opcode0x30_vv0, +/*opcode 0x31*/ xed3_phash_find_maplegacy_map0_opcode0x31_vv0, +/*opcode 0x32*/ xed3_phash_find_maplegacy_map0_opcode0x32_vv0, +/*opcode 0x33*/ xed3_phash_find_maplegacy_map0_opcode0x33_vv0, +/*opcode 0x34*/ xed3_phash_find_maplegacy_map0_opcode0x34_vv0, +/*opcode 0x35*/ xed3_phash_find_maplegacy_map0_opcode0x35_vv0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ xed3_phash_find_maplegacy_map0_opcode0x37_vv0, +/*opcode 0x38*/ xed3_phash_find_maplegacy_map0_opcode0x38_vv0, +/*opcode 0x39*/ xed3_phash_find_maplegacy_map0_opcode0x39_vv0, +/*opcode 0x3a*/ xed3_phash_find_maplegacy_map0_opcode0x3a_vv0, +/*opcode 0x3b*/ xed3_phash_find_maplegacy_map0_opcode0x3b_vv0, +/*opcode 0x3c*/ xed3_phash_find_maplegacy_map0_opcode0x3c_vv0, +/*opcode 0x3d*/ xed3_phash_find_maplegacy_map0_opcode0x3d_vv0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ xed3_phash_find_maplegacy_map0_opcode0x3f_vv0, +/*opcode 0x40*/ xed3_phash_find_maplegacy_map0_opcode0x40_vv0, +/*opcode 0x41*/ xed3_phash_find_maplegacy_map0_opcode0x41_vv0, +/*opcode 0x42*/ xed3_phash_find_maplegacy_map0_opcode0x42_vv0, +/*opcode 0x43*/ xed3_phash_find_maplegacy_map0_opcode0x43_vv0, +/*opcode 0x44*/ xed3_phash_find_maplegacy_map0_opcode0x44_vv0, +/*opcode 0x45*/ xed3_phash_find_maplegacy_map0_opcode0x45_vv0, +/*opcode 0x46*/ xed3_phash_find_maplegacy_map0_opcode0x46_vv0, +/*opcode 0x47*/ xed3_phash_find_maplegacy_map0_opcode0x47_vv0, +/*opcode 0x48*/ xed3_phash_find_maplegacy_map0_opcode0x48_vv0, +/*opcode 0x49*/ xed3_phash_find_maplegacy_map0_opcode0x49_vv0, +/*opcode 0x4a*/ xed3_phash_find_maplegacy_map0_opcode0x4a_vv0, +/*opcode 0x4b*/ xed3_phash_find_maplegacy_map0_opcode0x4b_vv0, +/*opcode 0x4c*/ xed3_phash_find_maplegacy_map0_opcode0x4c_vv0, +/*opcode 0x4d*/ xed3_phash_find_maplegacy_map0_opcode0x4d_vv0, +/*opcode 0x4e*/ xed3_phash_find_maplegacy_map0_opcode0x4e_vv0, +/*opcode 0x4f*/ xed3_phash_find_maplegacy_map0_opcode0x4f_vv0, +/*opcode 0x50*/ xed3_phash_find_maplegacy_map0_opcode0x50_vv0, +/*opcode 0x51*/ xed3_phash_find_maplegacy_map0_opcode0x51_vv0, +/*opcode 0x52*/ xed3_phash_find_maplegacy_map0_opcode0x52_vv0, +/*opcode 0x53*/ xed3_phash_find_maplegacy_map0_opcode0x53_vv0, +/*opcode 0x54*/ xed3_phash_find_maplegacy_map0_opcode0x54_vv0, +/*opcode 0x55*/ xed3_phash_find_maplegacy_map0_opcode0x55_vv0, +/*opcode 0x56*/ xed3_phash_find_maplegacy_map0_opcode0x56_vv0, +/*opcode 0x57*/ xed3_phash_find_maplegacy_map0_opcode0x57_vv0, +/*opcode 0x58*/ xed3_phash_find_maplegacy_map0_opcode0x58_vv0, +/*opcode 0x59*/ xed3_phash_find_maplegacy_map0_opcode0x59_vv0, +/*opcode 0x5a*/ xed3_phash_find_maplegacy_map0_opcode0x5a_vv0, +/*opcode 0x5b*/ xed3_phash_find_maplegacy_map0_opcode0x5b_vv0, +/*opcode 0x5c*/ xed3_phash_find_maplegacy_map0_opcode0x5c_vv0, +/*opcode 0x5d*/ xed3_phash_find_maplegacy_map0_opcode0x5d_vv0, +/*opcode 0x5e*/ xed3_phash_find_maplegacy_map0_opcode0x5e_vv0, +/*opcode 0x5f*/ xed3_phash_find_maplegacy_map0_opcode0x5f_vv0, +/*opcode 0x60*/ xed3_phash_find_maplegacy_map0_opcode0x60_vv0, +/*opcode 0x61*/ xed3_phash_find_maplegacy_map0_opcode0x61_vv0, +/*opcode 0x62*/ xed3_phash_find_maplegacy_map0_opcode0x62_vv0, +/*opcode 0x63*/ xed3_phash_find_maplegacy_map0_opcode0x63_vv0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ xed3_phash_find_maplegacy_map0_opcode0x68_vv0, +/*opcode 0x69*/ xed3_phash_find_maplegacy_map0_opcode0x69_vv0, +/*opcode 0x6a*/ xed3_phash_find_maplegacy_map0_opcode0x6a_vv0, +/*opcode 0x6b*/ xed3_phash_find_maplegacy_map0_opcode0x6b_vv0, +/*opcode 0x6c*/ xed3_phash_find_maplegacy_map0_opcode0x6c_vv0, +/*opcode 0x6d*/ xed3_phash_find_maplegacy_map0_opcode0x6d_vv0, +/*opcode 0x6e*/ xed3_phash_find_maplegacy_map0_opcode0x6e_vv0, +/*opcode 0x6f*/ xed3_phash_find_maplegacy_map0_opcode0x6f_vv0, +/*opcode 0x70*/ xed3_phash_find_maplegacy_map0_opcode0x70_vv0, +/*opcode 0x71*/ xed3_phash_find_maplegacy_map0_opcode0x71_vv0, +/*opcode 0x72*/ xed3_phash_find_maplegacy_map0_opcode0x72_vv0, +/*opcode 0x73*/ xed3_phash_find_maplegacy_map0_opcode0x73_vv0, +/*opcode 0x74*/ xed3_phash_find_maplegacy_map0_opcode0x74_vv0, +/*opcode 0x75*/ xed3_phash_find_maplegacy_map0_opcode0x75_vv0, +/*opcode 0x76*/ xed3_phash_find_maplegacy_map0_opcode0x76_vv0, +/*opcode 0x77*/ xed3_phash_find_maplegacy_map0_opcode0x77_vv0, +/*opcode 0x78*/ xed3_phash_find_maplegacy_map0_opcode0x78_vv0, +/*opcode 0x79*/ xed3_phash_find_maplegacy_map0_opcode0x79_vv0, +/*opcode 0x7a*/ xed3_phash_find_maplegacy_map0_opcode0x7a_vv0, +/*opcode 0x7b*/ xed3_phash_find_maplegacy_map0_opcode0x7b_vv0, +/*opcode 0x7c*/ xed3_phash_find_maplegacy_map0_opcode0x7c_vv0, +/*opcode 0x7d*/ xed3_phash_find_maplegacy_map0_opcode0x7d_vv0, +/*opcode 0x7e*/ xed3_phash_find_maplegacy_map0_opcode0x7e_vv0, +/*opcode 0x7f*/ xed3_phash_find_maplegacy_map0_opcode0x7f_vv0, +/*opcode 0x80*/ xed3_phash_find_maplegacy_map0_opcode0x80_vv0, +/*opcode 0x81*/ xed3_phash_find_maplegacy_map0_opcode0x81_vv0, +/*opcode 0x82*/ xed3_phash_find_maplegacy_map0_opcode0x82_vv0, +/*opcode 0x83*/ xed3_phash_find_maplegacy_map0_opcode0x83_vv0, +/*opcode 0x84*/ xed3_phash_find_maplegacy_map0_opcode0x84_vv0, +/*opcode 0x85*/ xed3_phash_find_maplegacy_map0_opcode0x85_vv0, +/*opcode 0x86*/ xed3_phash_find_maplegacy_map0_opcode0x86_vv0, +/*opcode 0x87*/ xed3_phash_find_maplegacy_map0_opcode0x87_vv0, +/*opcode 0x88*/ xed3_phash_find_maplegacy_map0_opcode0x88_vv0, +/*opcode 0x89*/ xed3_phash_find_maplegacy_map0_opcode0x89_vv0, +/*opcode 0x8a*/ xed3_phash_find_maplegacy_map0_opcode0x8a_vv0, +/*opcode 0x8b*/ xed3_phash_find_maplegacy_map0_opcode0x8b_vv0, +/*opcode 0x8c*/ xed3_phash_find_maplegacy_map0_opcode0x8c_vv0, +/*opcode 0x8d*/ xed3_phash_find_maplegacy_map0_opcode0x8d_vv0, +/*opcode 0x8e*/ xed3_phash_find_maplegacy_map0_opcode0x8e_vv0, +/*opcode 0x8f*/ xed3_phash_find_maplegacy_map0_opcode0x8f_vv0, +/*opcode 0x90*/ xed3_phash_find_maplegacy_map0_opcode0x90_vv0, +/*opcode 0x91*/ xed3_phash_find_maplegacy_map0_opcode0x91_vv0, +/*opcode 0x92*/ xed3_phash_find_maplegacy_map0_opcode0x92_vv0, +/*opcode 0x93*/ xed3_phash_find_maplegacy_map0_opcode0x93_vv0, +/*opcode 0x94*/ xed3_phash_find_maplegacy_map0_opcode0x94_vv0, +/*opcode 0x95*/ xed3_phash_find_maplegacy_map0_opcode0x95_vv0, +/*opcode 0x96*/ xed3_phash_find_maplegacy_map0_opcode0x96_vv0, +/*opcode 0x97*/ xed3_phash_find_maplegacy_map0_opcode0x97_vv0, +/*opcode 0x98*/ xed3_phash_find_maplegacy_map0_opcode0x98_vv0, +/*opcode 0x99*/ xed3_phash_find_maplegacy_map0_opcode0x99_vv0, +/*opcode 0x9a*/ xed3_phash_find_maplegacy_map0_opcode0x9a_vv0, +/*opcode 0x9b*/ xed3_phash_find_maplegacy_map0_opcode0x9b_vv0, +/*opcode 0x9c*/ xed3_phash_find_maplegacy_map0_opcode0x9c_vv0, +/*opcode 0x9d*/ xed3_phash_find_maplegacy_map0_opcode0x9d_vv0, +/*opcode 0x9e*/ xed3_phash_find_maplegacy_map0_opcode0x9e_vv0, +/*opcode 0x9f*/ xed3_phash_find_maplegacy_map0_opcode0x9f_vv0, +/*opcode 0xa0*/ xed3_phash_find_maplegacy_map0_opcode0xa0_vv0, +/*opcode 0xa1*/ xed3_phash_find_maplegacy_map0_opcode0xa1_vv0, +/*opcode 0xa2*/ xed3_phash_find_maplegacy_map0_opcode0xa2_vv0, +/*opcode 0xa3*/ xed3_phash_find_maplegacy_map0_opcode0xa3_vv0, +/*opcode 0xa4*/ xed3_phash_find_maplegacy_map0_opcode0xa4_vv0, +/*opcode 0xa5*/ xed3_phash_find_maplegacy_map0_opcode0xa5_vv0, +/*opcode 0xa6*/ xed3_phash_find_maplegacy_map0_opcode0xa6_vv0, +/*opcode 0xa7*/ xed3_phash_find_maplegacy_map0_opcode0xa7_vv0, +/*opcode 0xa8*/ xed3_phash_find_maplegacy_map0_opcode0xa8_vv0, +/*opcode 0xa9*/ xed3_phash_find_maplegacy_map0_opcode0xa9_vv0, +/*opcode 0xaa*/ xed3_phash_find_maplegacy_map0_opcode0xaa_vv0, +/*opcode 0xab*/ xed3_phash_find_maplegacy_map0_opcode0xab_vv0, +/*opcode 0xac*/ xed3_phash_find_maplegacy_map0_opcode0xac_vv0, +/*opcode 0xad*/ xed3_phash_find_maplegacy_map0_opcode0xad_vv0, +/*opcode 0xae*/ xed3_phash_find_maplegacy_map0_opcode0xae_vv0, +/*opcode 0xaf*/ xed3_phash_find_maplegacy_map0_opcode0xaf_vv0, +/*opcode 0xb0*/ xed3_phash_find_maplegacy_map0_opcode0xb0_vv0, +/*opcode 0xb1*/ xed3_phash_find_maplegacy_map0_opcode0xb1_vv0, +/*opcode 0xb2*/ xed3_phash_find_maplegacy_map0_opcode0xb2_vv0, +/*opcode 0xb3*/ xed3_phash_find_maplegacy_map0_opcode0xb3_vv0, +/*opcode 0xb4*/ xed3_phash_find_maplegacy_map0_opcode0xb4_vv0, +/*opcode 0xb5*/ xed3_phash_find_maplegacy_map0_opcode0xb5_vv0, +/*opcode 0xb6*/ xed3_phash_find_maplegacy_map0_opcode0xb6_vv0, +/*opcode 0xb7*/ xed3_phash_find_maplegacy_map0_opcode0xb7_vv0, +/*opcode 0xb8*/ xed3_phash_find_maplegacy_map0_opcode0xb8_vv0, +/*opcode 0xb9*/ xed3_phash_find_maplegacy_map0_opcode0xb9_vv0, +/*opcode 0xba*/ xed3_phash_find_maplegacy_map0_opcode0xba_vv0, +/*opcode 0xbb*/ xed3_phash_find_maplegacy_map0_opcode0xbb_vv0, +/*opcode 0xbc*/ xed3_phash_find_maplegacy_map0_opcode0xbc_vv0, +/*opcode 0xbd*/ xed3_phash_find_maplegacy_map0_opcode0xbd_vv0, +/*opcode 0xbe*/ xed3_phash_find_maplegacy_map0_opcode0xbe_vv0, +/*opcode 0xbf*/ xed3_phash_find_maplegacy_map0_opcode0xbf_vv0, +/*opcode 0xc0*/ xed3_phash_find_maplegacy_map0_opcode0xc0_vv0, +/*opcode 0xc1*/ xed3_phash_find_maplegacy_map0_opcode0xc1_vv0, +/*opcode 0xc2*/ xed3_phash_find_maplegacy_map0_opcode0xc2_vv0, +/*opcode 0xc3*/ xed3_phash_find_maplegacy_map0_opcode0xc3_vv0, +/*opcode 0xc4*/ xed3_phash_find_maplegacy_map0_opcode0xc4_vv0, +/*opcode 0xc5*/ xed3_phash_find_maplegacy_map0_opcode0xc5_vv0, +/*opcode 0xc6*/ xed3_phash_find_maplegacy_map0_opcode0xc6_vv0, +/*opcode 0xc7*/ xed3_phash_find_maplegacy_map0_opcode0xc7_vv0, +/*opcode 0xc8*/ xed3_phash_find_maplegacy_map0_opcode0xc8_vv0, +/*opcode 0xc9*/ xed3_phash_find_maplegacy_map0_opcode0xc9_vv0, +/*opcode 0xca*/ xed3_phash_find_maplegacy_map0_opcode0xca_vv0, +/*opcode 0xcb*/ xed3_phash_find_maplegacy_map0_opcode0xcb_vv0, +/*opcode 0xcc*/ xed3_phash_find_maplegacy_map0_opcode0xcc_vv0, +/*opcode 0xcd*/ xed3_phash_find_maplegacy_map0_opcode0xcd_vv0, +/*opcode 0xce*/ xed3_phash_find_maplegacy_map0_opcode0xce_vv0, +/*opcode 0xcf*/ xed3_phash_find_maplegacy_map0_opcode0xcf_vv0, +/*opcode 0xd0*/ xed3_phash_find_maplegacy_map0_opcode0xd0_vv0, +/*opcode 0xd1*/ xed3_phash_find_maplegacy_map0_opcode0xd1_vv0, +/*opcode 0xd2*/ xed3_phash_find_maplegacy_map0_opcode0xd2_vv0, +/*opcode 0xd3*/ xed3_phash_find_maplegacy_map0_opcode0xd3_vv0, +/*opcode 0xd4*/ xed3_phash_find_maplegacy_map0_opcode0xd4_vv0, +/*opcode 0xd5*/ xed3_phash_find_maplegacy_map0_opcode0xd5_vv0, +/*opcode 0xd6*/ xed3_phash_find_maplegacy_map0_opcode0xd6_vv0, +/*opcode 0xd7*/ xed3_phash_find_maplegacy_map0_opcode0xd7_vv0, +/*opcode 0xd8*/ xed3_phash_find_maplegacy_map0_opcode0xd8_vv0, +/*opcode 0xd9*/ xed3_phash_find_maplegacy_map0_opcode0xd9_vv0, +/*opcode 0xda*/ xed3_phash_find_maplegacy_map0_opcode0xda_vv0, +/*opcode 0xdb*/ xed3_phash_find_maplegacy_map0_opcode0xdb_vv0, +/*opcode 0xdc*/ xed3_phash_find_maplegacy_map0_opcode0xdc_vv0, +/*opcode 0xdd*/ xed3_phash_find_maplegacy_map0_opcode0xdd_vv0, +/*opcode 0xde*/ xed3_phash_find_maplegacy_map0_opcode0xde_vv0, +/*opcode 0xdf*/ xed3_phash_find_maplegacy_map0_opcode0xdf_vv0, +/*opcode 0xe0*/ xed3_phash_find_maplegacy_map0_opcode0xe0_vv0, +/*opcode 0xe1*/ xed3_phash_find_maplegacy_map0_opcode0xe1_vv0, +/*opcode 0xe2*/ xed3_phash_find_maplegacy_map0_opcode0xe2_vv0, +/*opcode 0xe3*/ xed3_phash_find_maplegacy_map0_opcode0xe3_vv0, +/*opcode 0xe4*/ xed3_phash_find_maplegacy_map0_opcode0xe4_vv0, +/*opcode 0xe5*/ xed3_phash_find_maplegacy_map0_opcode0xe5_vv0, +/*opcode 0xe6*/ xed3_phash_find_maplegacy_map0_opcode0xe6_vv0, +/*opcode 0xe7*/ xed3_phash_find_maplegacy_map0_opcode0xe7_vv0, +/*opcode 0xe8*/ xed3_phash_find_maplegacy_map0_opcode0xe8_vv0, +/*opcode 0xe9*/ xed3_phash_find_maplegacy_map0_opcode0xe9_vv0, +/*opcode 0xea*/ xed3_phash_find_maplegacy_map0_opcode0xea_vv0, +/*opcode 0xeb*/ xed3_phash_find_maplegacy_map0_opcode0xeb_vv0, +/*opcode 0xec*/ xed3_phash_find_maplegacy_map0_opcode0xec_vv0, +/*opcode 0xed*/ xed3_phash_find_maplegacy_map0_opcode0xed_vv0, +/*opcode 0xee*/ xed3_phash_find_maplegacy_map0_opcode0xee_vv0, +/*opcode 0xef*/ xed3_phash_find_maplegacy_map0_opcode0xef_vv0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ xed3_phash_find_maplegacy_map0_opcode0xf1_vv0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ xed3_phash_find_maplegacy_map0_opcode0xf4_vv0, +/*opcode 0xf5*/ xed3_phash_find_maplegacy_map0_opcode0xf5_vv0, +/*opcode 0xf6*/ xed3_phash_find_maplegacy_map0_opcode0xf6_vv0, +/*opcode 0xf7*/ xed3_phash_find_maplegacy_map0_opcode0xf7_vv0, +/*opcode 0xf8*/ xed3_phash_find_maplegacy_map0_opcode0xf8_vv0, +/*opcode 0xf9*/ xed3_phash_find_maplegacy_map0_opcode0xf9_vv0, +/*opcode 0xfa*/ xed3_phash_find_maplegacy_map0_opcode0xfa_vv0, +/*opcode 0xfb*/ xed3_phash_find_maplegacy_map0_opcode0xfb_vv0, +/*opcode 0xfc*/ xed3_phash_find_maplegacy_map0_opcode0xfc_vv0, +/*opcode 0xfd*/ xed3_phash_find_maplegacy_map0_opcode0xfd_vv0, +/*opcode 0xfe*/ xed3_phash_find_maplegacy_map0_opcode0xfe_vv0, +/*opcode 0xff*/ xed3_phash_find_maplegacy_map0_opcode0xff_vv0, +}; +const xed3_find_func_t xed3_phash_vv0_map_legacy_map1[256] = { +/*opcode 0x0*/ xed3_phash_find_maplegacy_map1_opcode0x0_vv0, +/*opcode 0x1*/ xed3_phash_find_maplegacy_map1_opcode0x1_vv0, +/*opcode 0x2*/ xed3_phash_find_maplegacy_map1_opcode0x2_vv0, +/*opcode 0x3*/ xed3_phash_find_maplegacy_map1_opcode0x3_vv0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ xed3_phash_find_maplegacy_map1_opcode0x5_vv0, +/*opcode 0x6*/ xed3_phash_find_maplegacy_map1_opcode0x6_vv0, +/*opcode 0x7*/ xed3_phash_find_maplegacy_map1_opcode0x7_vv0, +/*opcode 0x8*/ xed3_phash_find_maplegacy_map1_opcode0x8_vv0, +/*opcode 0x9*/ xed3_phash_find_maplegacy_map1_opcode0x9_vv0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ xed3_phash_find_maplegacy_map1_opcode0xb_vv0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ xed3_phash_find_maplegacy_map1_opcode0xd_vv0, +/*opcode 0xe*/ xed3_phash_find_maplegacy_map1_opcode0xe_vv0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_maplegacy_map1_opcode0x10_vv0, +/*opcode 0x11*/ xed3_phash_find_maplegacy_map1_opcode0x11_vv0, +/*opcode 0x12*/ xed3_phash_find_maplegacy_map1_opcode0x12_vv0, +/*opcode 0x13*/ xed3_phash_find_maplegacy_map1_opcode0x13_vv0, +/*opcode 0x14*/ xed3_phash_find_maplegacy_map1_opcode0x14_vv0, +/*opcode 0x15*/ xed3_phash_find_maplegacy_map1_opcode0x15_vv0, +/*opcode 0x16*/ xed3_phash_find_maplegacy_map1_opcode0x16_vv0, +/*opcode 0x17*/ xed3_phash_find_maplegacy_map1_opcode0x17_vv0, +/*opcode 0x18*/ xed3_phash_find_maplegacy_map1_opcode0x18_vv0, +/*opcode 0x19*/ xed3_phash_find_maplegacy_map1_opcode0x19_vv0, +/*opcode 0x1a*/ xed3_phash_find_maplegacy_map1_opcode0x1a_vv0, +/*opcode 0x1b*/ xed3_phash_find_maplegacy_map1_opcode0x1b_vv0, +/*opcode 0x1c*/ xed3_phash_find_maplegacy_map1_opcode0x1c_vv0, +/*opcode 0x1d*/ xed3_phash_find_maplegacy_map1_opcode0x1d_vv0, +/*opcode 0x1e*/ xed3_phash_find_maplegacy_map1_opcode0x1e_vv0, +/*opcode 0x1f*/ xed3_phash_find_maplegacy_map1_opcode0x1f_vv0, +/*opcode 0x20*/ xed3_phash_find_maplegacy_map1_opcode0x20_vv0, +/*opcode 0x21*/ xed3_phash_find_maplegacy_map1_opcode0x21_vv0, +/*opcode 0x22*/ xed3_phash_find_maplegacy_map1_opcode0x22_vv0, +/*opcode 0x23*/ xed3_phash_find_maplegacy_map1_opcode0x23_vv0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ xed3_phash_find_maplegacy_map1_opcode0x28_vv0, +/*opcode 0x29*/ xed3_phash_find_maplegacy_map1_opcode0x29_vv0, +/*opcode 0x2a*/ xed3_phash_find_maplegacy_map1_opcode0x2a_vv0, +/*opcode 0x2b*/ xed3_phash_find_maplegacy_map1_opcode0x2b_vv0, +/*opcode 0x2c*/ xed3_phash_find_maplegacy_map1_opcode0x2c_vv0, +/*opcode 0x2d*/ xed3_phash_find_maplegacy_map1_opcode0x2d_vv0, +/*opcode 0x2e*/ xed3_phash_find_maplegacy_map1_opcode0x2e_vv0, +/*opcode 0x2f*/ xed3_phash_find_maplegacy_map1_opcode0x2f_vv0, +/*opcode 0x30*/ xed3_phash_find_maplegacy_map1_opcode0x30_vv0, +/*opcode 0x31*/ xed3_phash_find_maplegacy_map1_opcode0x31_vv0, +/*opcode 0x32*/ xed3_phash_find_maplegacy_map1_opcode0x32_vv0, +/*opcode 0x33*/ xed3_phash_find_maplegacy_map1_opcode0x33_vv0, +/*opcode 0x34*/ xed3_phash_find_maplegacy_map1_opcode0x34_vv0, +/*opcode 0x35*/ xed3_phash_find_maplegacy_map1_opcode0x35_vv0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ xed3_phash_find_maplegacy_map1_opcode0x37_vv0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ xed3_phash_find_maplegacy_map1_opcode0x40_vv0, +/*opcode 0x41*/ xed3_phash_find_maplegacy_map1_opcode0x41_vv0, +/*opcode 0x42*/ xed3_phash_find_maplegacy_map1_opcode0x42_vv0, +/*opcode 0x43*/ xed3_phash_find_maplegacy_map1_opcode0x43_vv0, +/*opcode 0x44*/ xed3_phash_find_maplegacy_map1_opcode0x44_vv0, +/*opcode 0x45*/ xed3_phash_find_maplegacy_map1_opcode0x45_vv0, +/*opcode 0x46*/ xed3_phash_find_maplegacy_map1_opcode0x46_vv0, +/*opcode 0x47*/ xed3_phash_find_maplegacy_map1_opcode0x47_vv0, +/*opcode 0x48*/ xed3_phash_find_maplegacy_map1_opcode0x48_vv0, +/*opcode 0x49*/ xed3_phash_find_maplegacy_map1_opcode0x49_vv0, +/*opcode 0x4a*/ xed3_phash_find_maplegacy_map1_opcode0x4a_vv0, +/*opcode 0x4b*/ xed3_phash_find_maplegacy_map1_opcode0x4b_vv0, +/*opcode 0x4c*/ xed3_phash_find_maplegacy_map1_opcode0x4c_vv0, +/*opcode 0x4d*/ xed3_phash_find_maplegacy_map1_opcode0x4d_vv0, +/*opcode 0x4e*/ xed3_phash_find_maplegacy_map1_opcode0x4e_vv0, +/*opcode 0x4f*/ xed3_phash_find_maplegacy_map1_opcode0x4f_vv0, +/*opcode 0x50*/ xed3_phash_find_maplegacy_map1_opcode0x50_vv0, +/*opcode 0x51*/ xed3_phash_find_maplegacy_map1_opcode0x51_vv0, +/*opcode 0x52*/ xed3_phash_find_maplegacy_map1_opcode0x52_vv0, +/*opcode 0x53*/ xed3_phash_find_maplegacy_map1_opcode0x53_vv0, +/*opcode 0x54*/ xed3_phash_find_maplegacy_map1_opcode0x54_vv0, +/*opcode 0x55*/ xed3_phash_find_maplegacy_map1_opcode0x55_vv0, +/*opcode 0x56*/ xed3_phash_find_maplegacy_map1_opcode0x56_vv0, +/*opcode 0x57*/ xed3_phash_find_maplegacy_map1_opcode0x57_vv0, +/*opcode 0x58*/ xed3_phash_find_maplegacy_map1_opcode0x58_vv0, +/*opcode 0x59*/ xed3_phash_find_maplegacy_map1_opcode0x59_vv0, +/*opcode 0x5a*/ xed3_phash_find_maplegacy_map1_opcode0x5a_vv0, +/*opcode 0x5b*/ xed3_phash_find_maplegacy_map1_opcode0x5b_vv0, +/*opcode 0x5c*/ xed3_phash_find_maplegacy_map1_opcode0x5c_vv0, +/*opcode 0x5d*/ xed3_phash_find_maplegacy_map1_opcode0x5d_vv0, +/*opcode 0x5e*/ xed3_phash_find_maplegacy_map1_opcode0x5e_vv0, +/*opcode 0x5f*/ xed3_phash_find_maplegacy_map1_opcode0x5f_vv0, +/*opcode 0x60*/ xed3_phash_find_maplegacy_map1_opcode0x60_vv0, +/*opcode 0x61*/ xed3_phash_find_maplegacy_map1_opcode0x61_vv0, +/*opcode 0x62*/ xed3_phash_find_maplegacy_map1_opcode0x62_vv0, +/*opcode 0x63*/ xed3_phash_find_maplegacy_map1_opcode0x63_vv0, +/*opcode 0x64*/ xed3_phash_find_maplegacy_map1_opcode0x64_vv0, +/*opcode 0x65*/ xed3_phash_find_maplegacy_map1_opcode0x65_vv0, +/*opcode 0x66*/ xed3_phash_find_maplegacy_map1_opcode0x66_vv0, +/*opcode 0x67*/ xed3_phash_find_maplegacy_map1_opcode0x67_vv0, +/*opcode 0x68*/ xed3_phash_find_maplegacy_map1_opcode0x68_vv0, +/*opcode 0x69*/ xed3_phash_find_maplegacy_map1_opcode0x69_vv0, +/*opcode 0x6a*/ xed3_phash_find_maplegacy_map1_opcode0x6a_vv0, +/*opcode 0x6b*/ xed3_phash_find_maplegacy_map1_opcode0x6b_vv0, +/*opcode 0x6c*/ xed3_phash_find_maplegacy_map1_opcode0x6c_vv0, +/*opcode 0x6d*/ xed3_phash_find_maplegacy_map1_opcode0x6d_vv0, +/*opcode 0x6e*/ xed3_phash_find_maplegacy_map1_opcode0x6e_vv0, +/*opcode 0x6f*/ xed3_phash_find_maplegacy_map1_opcode0x6f_vv0, +/*opcode 0x70*/ xed3_phash_find_maplegacy_map1_opcode0x70_vv0, +/*opcode 0x71*/ xed3_phash_find_maplegacy_map1_opcode0x71_vv0, +/*opcode 0x72*/ xed3_phash_find_maplegacy_map1_opcode0x72_vv0, +/*opcode 0x73*/ xed3_phash_find_maplegacy_map1_opcode0x73_vv0, +/*opcode 0x74*/ xed3_phash_find_maplegacy_map1_opcode0x74_vv0, +/*opcode 0x75*/ xed3_phash_find_maplegacy_map1_opcode0x75_vv0, +/*opcode 0x76*/ xed3_phash_find_maplegacy_map1_opcode0x76_vv0, +/*opcode 0x77*/ xed3_phash_find_maplegacy_map1_opcode0x77_vv0, +/*opcode 0x78*/ xed3_phash_find_maplegacy_map1_opcode0x78_vv0, +/*opcode 0x79*/ xed3_phash_find_maplegacy_map1_opcode0x79_vv0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ xed3_phash_find_maplegacy_map1_opcode0x7c_vv0, +/*opcode 0x7d*/ xed3_phash_find_maplegacy_map1_opcode0x7d_vv0, +/*opcode 0x7e*/ xed3_phash_find_maplegacy_map1_opcode0x7e_vv0, +/*opcode 0x7f*/ xed3_phash_find_maplegacy_map1_opcode0x7f_vv0, +/*opcode 0x80*/ xed3_phash_find_maplegacy_map1_opcode0x80_vv0, +/*opcode 0x81*/ xed3_phash_find_maplegacy_map1_opcode0x81_vv0, +/*opcode 0x82*/ xed3_phash_find_maplegacy_map1_opcode0x82_vv0, +/*opcode 0x83*/ xed3_phash_find_maplegacy_map1_opcode0x83_vv0, +/*opcode 0x84*/ xed3_phash_find_maplegacy_map1_opcode0x84_vv0, +/*opcode 0x85*/ xed3_phash_find_maplegacy_map1_opcode0x85_vv0, +/*opcode 0x86*/ xed3_phash_find_maplegacy_map1_opcode0x86_vv0, +/*opcode 0x87*/ xed3_phash_find_maplegacy_map1_opcode0x87_vv0, +/*opcode 0x88*/ xed3_phash_find_maplegacy_map1_opcode0x88_vv0, +/*opcode 0x89*/ xed3_phash_find_maplegacy_map1_opcode0x89_vv0, +/*opcode 0x8a*/ xed3_phash_find_maplegacy_map1_opcode0x8a_vv0, +/*opcode 0x8b*/ xed3_phash_find_maplegacy_map1_opcode0x8b_vv0, +/*opcode 0x8c*/ xed3_phash_find_maplegacy_map1_opcode0x8c_vv0, +/*opcode 0x8d*/ xed3_phash_find_maplegacy_map1_opcode0x8d_vv0, +/*opcode 0x8e*/ xed3_phash_find_maplegacy_map1_opcode0x8e_vv0, +/*opcode 0x8f*/ xed3_phash_find_maplegacy_map1_opcode0x8f_vv0, +/*opcode 0x90*/ xed3_phash_find_maplegacy_map1_opcode0x90_vv0, +/*opcode 0x91*/ xed3_phash_find_maplegacy_map1_opcode0x91_vv0, +/*opcode 0x92*/ xed3_phash_find_maplegacy_map1_opcode0x92_vv0, +/*opcode 0x93*/ xed3_phash_find_maplegacy_map1_opcode0x93_vv0, +/*opcode 0x94*/ xed3_phash_find_maplegacy_map1_opcode0x94_vv0, +/*opcode 0x95*/ xed3_phash_find_maplegacy_map1_opcode0x95_vv0, +/*opcode 0x96*/ xed3_phash_find_maplegacy_map1_opcode0x96_vv0, +/*opcode 0x97*/ xed3_phash_find_maplegacy_map1_opcode0x97_vv0, +/*opcode 0x98*/ xed3_phash_find_maplegacy_map1_opcode0x98_vv0, +/*opcode 0x99*/ xed3_phash_find_maplegacy_map1_opcode0x99_vv0, +/*opcode 0x9a*/ xed3_phash_find_maplegacy_map1_opcode0x9a_vv0, +/*opcode 0x9b*/ xed3_phash_find_maplegacy_map1_opcode0x9b_vv0, +/*opcode 0x9c*/ xed3_phash_find_maplegacy_map1_opcode0x9c_vv0, +/*opcode 0x9d*/ xed3_phash_find_maplegacy_map1_opcode0x9d_vv0, +/*opcode 0x9e*/ xed3_phash_find_maplegacy_map1_opcode0x9e_vv0, +/*opcode 0x9f*/ xed3_phash_find_maplegacy_map1_opcode0x9f_vv0, +/*opcode 0xa0*/ xed3_phash_find_maplegacy_map1_opcode0xa0_vv0, +/*opcode 0xa1*/ xed3_phash_find_maplegacy_map1_opcode0xa1_vv0, +/*opcode 0xa2*/ xed3_phash_find_maplegacy_map1_opcode0xa2_vv0, +/*opcode 0xa3*/ xed3_phash_find_maplegacy_map1_opcode0xa3_vv0, +/*opcode 0xa4*/ xed3_phash_find_maplegacy_map1_opcode0xa4_vv0, +/*opcode 0xa5*/ xed3_phash_find_maplegacy_map1_opcode0xa5_vv0, +/*opcode 0xa6*/ xed3_phash_find_maplegacy_map1_opcode0xa6_vv0, +/*opcode 0xa7*/ xed3_phash_find_maplegacy_map1_opcode0xa7_vv0, +/*opcode 0xa8*/ xed3_phash_find_maplegacy_map1_opcode0xa8_vv0, +/*opcode 0xa9*/ xed3_phash_find_maplegacy_map1_opcode0xa9_vv0, +/*opcode 0xaa*/ xed3_phash_find_maplegacy_map1_opcode0xaa_vv0, +/*opcode 0xab*/ xed3_phash_find_maplegacy_map1_opcode0xab_vv0, +/*opcode 0xac*/ xed3_phash_find_maplegacy_map1_opcode0xac_vv0, +/*opcode 0xad*/ xed3_phash_find_maplegacy_map1_opcode0xad_vv0, +/*opcode 0xae*/ xed3_phash_find_maplegacy_map1_opcode0xae_vv0, +/*opcode 0xaf*/ xed3_phash_find_maplegacy_map1_opcode0xaf_vv0, +/*opcode 0xb0*/ xed3_phash_find_maplegacy_map1_opcode0xb0_vv0, +/*opcode 0xb1*/ xed3_phash_find_maplegacy_map1_opcode0xb1_vv0, +/*opcode 0xb2*/ xed3_phash_find_maplegacy_map1_opcode0xb2_vv0, +/*opcode 0xb3*/ xed3_phash_find_maplegacy_map1_opcode0xb3_vv0, +/*opcode 0xb4*/ xed3_phash_find_maplegacy_map1_opcode0xb4_vv0, +/*opcode 0xb5*/ xed3_phash_find_maplegacy_map1_opcode0xb5_vv0, +/*opcode 0xb6*/ xed3_phash_find_maplegacy_map1_opcode0xb6_vv0, +/*opcode 0xb7*/ xed3_phash_find_maplegacy_map1_opcode0xb7_vv0, +/*opcode 0xb8*/ xed3_phash_find_maplegacy_map1_opcode0xb8_vv0, +/*opcode 0xb9*/ xed3_phash_find_maplegacy_map1_opcode0xb9_vv0, +/*opcode 0xba*/ xed3_phash_find_maplegacy_map1_opcode0xba_vv0, +/*opcode 0xbb*/ xed3_phash_find_maplegacy_map1_opcode0xbb_vv0, +/*opcode 0xbc*/ xed3_phash_find_maplegacy_map1_opcode0xbc_vv0, +/*opcode 0xbd*/ xed3_phash_find_maplegacy_map1_opcode0xbd_vv0, +/*opcode 0xbe*/ xed3_phash_find_maplegacy_map1_opcode0xbe_vv0, +/*opcode 0xbf*/ xed3_phash_find_maplegacy_map1_opcode0xbf_vv0, +/*opcode 0xc0*/ xed3_phash_find_maplegacy_map1_opcode0xc0_vv0, +/*opcode 0xc1*/ xed3_phash_find_maplegacy_map1_opcode0xc1_vv0, +/*opcode 0xc2*/ xed3_phash_find_maplegacy_map1_opcode0xc2_vv0, +/*opcode 0xc3*/ xed3_phash_find_maplegacy_map1_opcode0xc3_vv0, +/*opcode 0xc4*/ xed3_phash_find_maplegacy_map1_opcode0xc4_vv0, +/*opcode 0xc5*/ xed3_phash_find_maplegacy_map1_opcode0xc5_vv0, +/*opcode 0xc6*/ xed3_phash_find_maplegacy_map1_opcode0xc6_vv0, +/*opcode 0xc7*/ xed3_phash_find_maplegacy_map1_opcode0xc7_vv0, +/*opcode 0xc8*/ xed3_phash_find_maplegacy_map1_opcode0xc8_vv0, +/*opcode 0xc9*/ xed3_phash_find_maplegacy_map1_opcode0xc9_vv0, +/*opcode 0xca*/ xed3_phash_find_maplegacy_map1_opcode0xca_vv0, +/*opcode 0xcb*/ xed3_phash_find_maplegacy_map1_opcode0xcb_vv0, +/*opcode 0xcc*/ xed3_phash_find_maplegacy_map1_opcode0xcc_vv0, +/*opcode 0xcd*/ xed3_phash_find_maplegacy_map1_opcode0xcd_vv0, +/*opcode 0xce*/ xed3_phash_find_maplegacy_map1_opcode0xce_vv0, +/*opcode 0xcf*/ xed3_phash_find_maplegacy_map1_opcode0xcf_vv0, +/*opcode 0xd0*/ xed3_phash_find_maplegacy_map1_opcode0xd0_vv0, +/*opcode 0xd1*/ xed3_phash_find_maplegacy_map1_opcode0xd1_vv0, +/*opcode 0xd2*/ xed3_phash_find_maplegacy_map1_opcode0xd2_vv0, +/*opcode 0xd3*/ xed3_phash_find_maplegacy_map1_opcode0xd3_vv0, +/*opcode 0xd4*/ xed3_phash_find_maplegacy_map1_opcode0xd4_vv0, +/*opcode 0xd5*/ xed3_phash_find_maplegacy_map1_opcode0xd5_vv0, +/*opcode 0xd6*/ xed3_phash_find_maplegacy_map1_opcode0xd6_vv0, +/*opcode 0xd7*/ xed3_phash_find_maplegacy_map1_opcode0xd7_vv0, +/*opcode 0xd8*/ xed3_phash_find_maplegacy_map1_opcode0xd8_vv0, +/*opcode 0xd9*/ xed3_phash_find_maplegacy_map1_opcode0xd9_vv0, +/*opcode 0xda*/ xed3_phash_find_maplegacy_map1_opcode0xda_vv0, +/*opcode 0xdb*/ xed3_phash_find_maplegacy_map1_opcode0xdb_vv0, +/*opcode 0xdc*/ xed3_phash_find_maplegacy_map1_opcode0xdc_vv0, +/*opcode 0xdd*/ xed3_phash_find_maplegacy_map1_opcode0xdd_vv0, +/*opcode 0xde*/ xed3_phash_find_maplegacy_map1_opcode0xde_vv0, +/*opcode 0xdf*/ xed3_phash_find_maplegacy_map1_opcode0xdf_vv0, +/*opcode 0xe0*/ xed3_phash_find_maplegacy_map1_opcode0xe0_vv0, +/*opcode 0xe1*/ xed3_phash_find_maplegacy_map1_opcode0xe1_vv0, +/*opcode 0xe2*/ xed3_phash_find_maplegacy_map1_opcode0xe2_vv0, +/*opcode 0xe3*/ xed3_phash_find_maplegacy_map1_opcode0xe3_vv0, +/*opcode 0xe4*/ xed3_phash_find_maplegacy_map1_opcode0xe4_vv0, +/*opcode 0xe5*/ xed3_phash_find_maplegacy_map1_opcode0xe5_vv0, +/*opcode 0xe6*/ xed3_phash_find_maplegacy_map1_opcode0xe6_vv0, +/*opcode 0xe7*/ xed3_phash_find_maplegacy_map1_opcode0xe7_vv0, +/*opcode 0xe8*/ xed3_phash_find_maplegacy_map1_opcode0xe8_vv0, +/*opcode 0xe9*/ xed3_phash_find_maplegacy_map1_opcode0xe9_vv0, +/*opcode 0xea*/ xed3_phash_find_maplegacy_map1_opcode0xea_vv0, +/*opcode 0xeb*/ xed3_phash_find_maplegacy_map1_opcode0xeb_vv0, +/*opcode 0xec*/ xed3_phash_find_maplegacy_map1_opcode0xec_vv0, +/*opcode 0xed*/ xed3_phash_find_maplegacy_map1_opcode0xed_vv0, +/*opcode 0xee*/ xed3_phash_find_maplegacy_map1_opcode0xee_vv0, +/*opcode 0xef*/ xed3_phash_find_maplegacy_map1_opcode0xef_vv0, +/*opcode 0xf0*/ xed3_phash_find_maplegacy_map1_opcode0xf0_vv0, +/*opcode 0xf1*/ xed3_phash_find_maplegacy_map1_opcode0xf1_vv0, +/*opcode 0xf2*/ xed3_phash_find_maplegacy_map1_opcode0xf2_vv0, +/*opcode 0xf3*/ xed3_phash_find_maplegacy_map1_opcode0xf3_vv0, +/*opcode 0xf4*/ xed3_phash_find_maplegacy_map1_opcode0xf4_vv0, +/*opcode 0xf5*/ xed3_phash_find_maplegacy_map1_opcode0xf5_vv0, +/*opcode 0xf6*/ xed3_phash_find_maplegacy_map1_opcode0xf6_vv0, +/*opcode 0xf7*/ xed3_phash_find_maplegacy_map1_opcode0xf7_vv0, +/*opcode 0xf8*/ xed3_phash_find_maplegacy_map1_opcode0xf8_vv0, +/*opcode 0xf9*/ xed3_phash_find_maplegacy_map1_opcode0xf9_vv0, +/*opcode 0xfa*/ xed3_phash_find_maplegacy_map1_opcode0xfa_vv0, +/*opcode 0xfb*/ xed3_phash_find_maplegacy_map1_opcode0xfb_vv0, +/*opcode 0xfc*/ xed3_phash_find_maplegacy_map1_opcode0xfc_vv0, +/*opcode 0xfd*/ xed3_phash_find_maplegacy_map1_opcode0xfd_vv0, +/*opcode 0xfe*/ xed3_phash_find_maplegacy_map1_opcode0xfe_vv0, +/*opcode 0xff*/ xed3_phash_find_maplegacy_map1_opcode0xff_vv0, +}; +const xed3_find_func_t xed3_phash_vv0_map_legacy_map2[256] = { +/*opcode 0x0*/ xed3_phash_find_maplegacy_map2_opcode0x0_vv0, +/*opcode 0x1*/ xed3_phash_find_maplegacy_map2_opcode0x1_vv0, +/*opcode 0x2*/ xed3_phash_find_maplegacy_map2_opcode0x2_vv0, +/*opcode 0x3*/ xed3_phash_find_maplegacy_map2_opcode0x3_vv0, +/*opcode 0x4*/ xed3_phash_find_maplegacy_map2_opcode0x4_vv0, +/*opcode 0x5*/ xed3_phash_find_maplegacy_map2_opcode0x5_vv0, +/*opcode 0x6*/ xed3_phash_find_maplegacy_map2_opcode0x6_vv0, +/*opcode 0x7*/ xed3_phash_find_maplegacy_map2_opcode0x7_vv0, +/*opcode 0x8*/ xed3_phash_find_maplegacy_map2_opcode0x8_vv0, +/*opcode 0x9*/ xed3_phash_find_maplegacy_map2_opcode0x9_vv0, +/*opcode 0xa*/ xed3_phash_find_maplegacy_map2_opcode0xa_vv0, +/*opcode 0xb*/ xed3_phash_find_maplegacy_map2_opcode0xb_vv0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_maplegacy_map2_opcode0x10_vv0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ xed3_phash_find_maplegacy_map2_opcode0x14_vv0, +/*opcode 0x15*/ xed3_phash_find_maplegacy_map2_opcode0x15_vv0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ xed3_phash_find_maplegacy_map2_opcode0x17_vv0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ xed3_phash_find_maplegacy_map2_opcode0x1c_vv0, +/*opcode 0x1d*/ xed3_phash_find_maplegacy_map2_opcode0x1d_vv0, +/*opcode 0x1e*/ xed3_phash_find_maplegacy_map2_opcode0x1e_vv0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ xed3_phash_find_maplegacy_map2_opcode0x20_vv0, +/*opcode 0x21*/ xed3_phash_find_maplegacy_map2_opcode0x21_vv0, +/*opcode 0x22*/ xed3_phash_find_maplegacy_map2_opcode0x22_vv0, +/*opcode 0x23*/ xed3_phash_find_maplegacy_map2_opcode0x23_vv0, +/*opcode 0x24*/ xed3_phash_find_maplegacy_map2_opcode0x24_vv0, +/*opcode 0x25*/ xed3_phash_find_maplegacy_map2_opcode0x25_vv0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ xed3_phash_find_maplegacy_map2_opcode0x28_vv0, +/*opcode 0x29*/ xed3_phash_find_maplegacy_map2_opcode0x29_vv0, +/*opcode 0x2a*/ xed3_phash_find_maplegacy_map2_opcode0x2a_vv0, +/*opcode 0x2b*/ xed3_phash_find_maplegacy_map2_opcode0x2b_vv0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ xed3_phash_find_maplegacy_map2_opcode0x30_vv0, +/*opcode 0x31*/ xed3_phash_find_maplegacy_map2_opcode0x31_vv0, +/*opcode 0x32*/ xed3_phash_find_maplegacy_map2_opcode0x32_vv0, +/*opcode 0x33*/ xed3_phash_find_maplegacy_map2_opcode0x33_vv0, +/*opcode 0x34*/ xed3_phash_find_maplegacy_map2_opcode0x34_vv0, +/*opcode 0x35*/ xed3_phash_find_maplegacy_map2_opcode0x35_vv0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ xed3_phash_find_maplegacy_map2_opcode0x37_vv0, +/*opcode 0x38*/ xed3_phash_find_maplegacy_map2_opcode0x38_vv0, +/*opcode 0x39*/ xed3_phash_find_maplegacy_map2_opcode0x39_vv0, +/*opcode 0x3a*/ xed3_phash_find_maplegacy_map2_opcode0x3a_vv0, +/*opcode 0x3b*/ xed3_phash_find_maplegacy_map2_opcode0x3b_vv0, +/*opcode 0x3c*/ xed3_phash_find_maplegacy_map2_opcode0x3c_vv0, +/*opcode 0x3d*/ xed3_phash_find_maplegacy_map2_opcode0x3d_vv0, +/*opcode 0x3e*/ xed3_phash_find_maplegacy_map2_opcode0x3e_vv0, +/*opcode 0x3f*/ xed3_phash_find_maplegacy_map2_opcode0x3f_vv0, +/*opcode 0x40*/ xed3_phash_find_maplegacy_map2_opcode0x40_vv0, +/*opcode 0x41*/ xed3_phash_find_maplegacy_map2_opcode0x41_vv0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ xed3_phash_find_maplegacy_map2_opcode0x80_vv0, +/*opcode 0x81*/ xed3_phash_find_maplegacy_map2_opcode0x81_vv0, +/*opcode 0x82*/ xed3_phash_find_maplegacy_map2_opcode0x82_vv0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ xed3_phash_find_maplegacy_map2_opcode0xc8_vv0, +/*opcode 0xc9*/ xed3_phash_find_maplegacy_map2_opcode0xc9_vv0, +/*opcode 0xca*/ xed3_phash_find_maplegacy_map2_opcode0xca_vv0, +/*opcode 0xcb*/ xed3_phash_find_maplegacy_map2_opcode0xcb_vv0, +/*opcode 0xcc*/ xed3_phash_find_maplegacy_map2_opcode0xcc_vv0, +/*opcode 0xcd*/ xed3_phash_find_maplegacy_map2_opcode0xcd_vv0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ xed3_phash_find_maplegacy_map2_opcode0xcf_vv0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ xed3_phash_find_maplegacy_map2_opcode0xd8_vv0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ xed3_phash_find_maplegacy_map2_opcode0xdb_vv0, +/*opcode 0xdc*/ xed3_phash_find_maplegacy_map2_opcode0xdc_vv0, +/*opcode 0xdd*/ xed3_phash_find_maplegacy_map2_opcode0xdd_vv0, +/*opcode 0xde*/ xed3_phash_find_maplegacy_map2_opcode0xde_vv0, +/*opcode 0xdf*/ xed3_phash_find_maplegacy_map2_opcode0xdf_vv0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ xed3_phash_find_maplegacy_map2_opcode0xf0_vv0, +/*opcode 0xf1*/ xed3_phash_find_maplegacy_map2_opcode0xf1_vv0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ xed3_phash_find_maplegacy_map2_opcode0xf5_vv0, +/*opcode 0xf6*/ xed3_phash_find_maplegacy_map2_opcode0xf6_vv0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ xed3_phash_find_maplegacy_map2_opcode0xf8_vv0, +/*opcode 0xf9*/ xed3_phash_find_maplegacy_map2_opcode0xf9_vv0, +/*opcode 0xfa*/ xed3_phash_find_maplegacy_map2_opcode0xfa_vv0, +/*opcode 0xfb*/ xed3_phash_find_maplegacy_map2_opcode0xfb_vv0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv0_map_legacy_map3[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ xed3_phash_find_maplegacy_map3_opcode0x8_vv0, +/*opcode 0x9*/ xed3_phash_find_maplegacy_map3_opcode0x9_vv0, +/*opcode 0xa*/ xed3_phash_find_maplegacy_map3_opcode0xa_vv0, +/*opcode 0xb*/ xed3_phash_find_maplegacy_map3_opcode0xb_vv0, +/*opcode 0xc*/ xed3_phash_find_maplegacy_map3_opcode0xc_vv0, +/*opcode 0xd*/ xed3_phash_find_maplegacy_map3_opcode0xd_vv0, +/*opcode 0xe*/ xed3_phash_find_maplegacy_map3_opcode0xe_vv0, +/*opcode 0xf*/ xed3_phash_find_maplegacy_map3_opcode0xf_vv0, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ xed3_phash_find_maplegacy_map3_opcode0x14_vv0, +/*opcode 0x15*/ xed3_phash_find_maplegacy_map3_opcode0x15_vv0, +/*opcode 0x16*/ xed3_phash_find_maplegacy_map3_opcode0x16_vv0, +/*opcode 0x17*/ xed3_phash_find_maplegacy_map3_opcode0x17_vv0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ xed3_phash_find_maplegacy_map3_opcode0x20_vv0, +/*opcode 0x21*/ xed3_phash_find_maplegacy_map3_opcode0x21_vv0, +/*opcode 0x22*/ xed3_phash_find_maplegacy_map3_opcode0x22_vv0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ xed3_phash_find_maplegacy_map3_opcode0x40_vv0, +/*opcode 0x41*/ xed3_phash_find_maplegacy_map3_opcode0x41_vv0, +/*opcode 0x42*/ xed3_phash_find_maplegacy_map3_opcode0x42_vv0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ xed3_phash_find_maplegacy_map3_opcode0x44_vv0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ xed3_phash_find_maplegacy_map3_opcode0x60_vv0, +/*opcode 0x61*/ xed3_phash_find_maplegacy_map3_opcode0x61_vv0, +/*opcode 0x62*/ xed3_phash_find_maplegacy_map3_opcode0x62_vv0, +/*opcode 0x63*/ xed3_phash_find_maplegacy_map3_opcode0x63_vv0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ xed3_phash_find_maplegacy_map3_opcode0xcc_vv0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ xed3_phash_find_maplegacy_map3_opcode0xce_vv0, +/*opcode 0xcf*/ xed3_phash_find_maplegacy_map3_opcode0xcf_vv0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ xed3_phash_find_maplegacy_map3_opcode0xdf_vv0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ xed3_phash_find_maplegacy_map3_opcode0xf0_vv0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; diff --git a/CodeVirtualizer/build/obj/xed3-phash-lu-vv1.c b/CodeVirtualizer/build/obj/xed3-phash-lu-vv1.c new file mode 100644 index 0000000..603c255 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed3-phash-lu-vv1.c @@ -0,0 +1,798 @@ +/// @file xed3-phash-lu-vv1.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-phash-vv1.h" +const xed3_find_func_t xed3_phash_vv1_map_vex_map1[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_mapvex_map1_opcode0x10_vv1, +/*opcode 0x11*/ xed3_phash_find_mapvex_map1_opcode0x11_vv1, +/*opcode 0x12*/ xed3_phash_find_mapvex_map1_opcode0x12_vv1, +/*opcode 0x13*/ xed3_phash_find_mapvex_map1_opcode0x13_vv1, +/*opcode 0x14*/ xed3_phash_find_mapvex_map1_opcode0x14_vv1, +/*opcode 0x15*/ xed3_phash_find_mapvex_map1_opcode0x15_vv1, +/*opcode 0x16*/ xed3_phash_find_mapvex_map1_opcode0x16_vv1, +/*opcode 0x17*/ xed3_phash_find_mapvex_map1_opcode0x17_vv1, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ xed3_phash_find_mapvex_map1_opcode0x28_vv1, +/*opcode 0x29*/ xed3_phash_find_mapvex_map1_opcode0x29_vv1, +/*opcode 0x2a*/ xed3_phash_find_mapvex_map1_opcode0x2a_vv1, +/*opcode 0x2b*/ xed3_phash_find_mapvex_map1_opcode0x2b_vv1, +/*opcode 0x2c*/ xed3_phash_find_mapvex_map1_opcode0x2c_vv1, +/*opcode 0x2d*/ xed3_phash_find_mapvex_map1_opcode0x2d_vv1, +/*opcode 0x2e*/ xed3_phash_find_mapvex_map1_opcode0x2e_vv1, +/*opcode 0x2f*/ xed3_phash_find_mapvex_map1_opcode0x2f_vv1, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ xed3_phash_find_mapvex_map1_opcode0x41_vv1, +/*opcode 0x42*/ xed3_phash_find_mapvex_map1_opcode0x42_vv1, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ xed3_phash_find_mapvex_map1_opcode0x44_vv1, +/*opcode 0x45*/ xed3_phash_find_mapvex_map1_opcode0x45_vv1, +/*opcode 0x46*/ xed3_phash_find_mapvex_map1_opcode0x46_vv1, +/*opcode 0x47*/ xed3_phash_find_mapvex_map1_opcode0x47_vv1, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ xed3_phash_find_mapvex_map1_opcode0x4a_vv1, +/*opcode 0x4b*/ xed3_phash_find_mapvex_map1_opcode0x4b_vv1, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ xed3_phash_find_mapvex_map1_opcode0x50_vv1, +/*opcode 0x51*/ xed3_phash_find_mapvex_map1_opcode0x51_vv1, +/*opcode 0x52*/ xed3_phash_find_mapvex_map1_opcode0x52_vv1, +/*opcode 0x53*/ xed3_phash_find_mapvex_map1_opcode0x53_vv1, +/*opcode 0x54*/ xed3_phash_find_mapvex_map1_opcode0x54_vv1, +/*opcode 0x55*/ xed3_phash_find_mapvex_map1_opcode0x55_vv1, +/*opcode 0x56*/ xed3_phash_find_mapvex_map1_opcode0x56_vv1, +/*opcode 0x57*/ xed3_phash_find_mapvex_map1_opcode0x57_vv1, +/*opcode 0x58*/ xed3_phash_find_mapvex_map1_opcode0x58_vv1, +/*opcode 0x59*/ xed3_phash_find_mapvex_map1_opcode0x59_vv1, +/*opcode 0x5a*/ xed3_phash_find_mapvex_map1_opcode0x5a_vv1, +/*opcode 0x5b*/ xed3_phash_find_mapvex_map1_opcode0x5b_vv1, +/*opcode 0x5c*/ xed3_phash_find_mapvex_map1_opcode0x5c_vv1, +/*opcode 0x5d*/ xed3_phash_find_mapvex_map1_opcode0x5d_vv1, +/*opcode 0x5e*/ xed3_phash_find_mapvex_map1_opcode0x5e_vv1, +/*opcode 0x5f*/ xed3_phash_find_mapvex_map1_opcode0x5f_vv1, +/*opcode 0x60*/ xed3_phash_find_mapvex_map1_opcode0x60_vv1, +/*opcode 0x61*/ xed3_phash_find_mapvex_map1_opcode0x61_vv1, +/*opcode 0x62*/ xed3_phash_find_mapvex_map1_opcode0x62_vv1, +/*opcode 0x63*/ xed3_phash_find_mapvex_map1_opcode0x63_vv1, +/*opcode 0x64*/ xed3_phash_find_mapvex_map1_opcode0x64_vv1, +/*opcode 0x65*/ xed3_phash_find_mapvex_map1_opcode0x65_vv1, +/*opcode 0x66*/ xed3_phash_find_mapvex_map1_opcode0x66_vv1, +/*opcode 0x67*/ xed3_phash_find_mapvex_map1_opcode0x67_vv1, +/*opcode 0x68*/ xed3_phash_find_mapvex_map1_opcode0x68_vv1, +/*opcode 0x69*/ xed3_phash_find_mapvex_map1_opcode0x69_vv1, +/*opcode 0x6a*/ xed3_phash_find_mapvex_map1_opcode0x6a_vv1, +/*opcode 0x6b*/ xed3_phash_find_mapvex_map1_opcode0x6b_vv1, +/*opcode 0x6c*/ xed3_phash_find_mapvex_map1_opcode0x6c_vv1, +/*opcode 0x6d*/ xed3_phash_find_mapvex_map1_opcode0x6d_vv1, +/*opcode 0x6e*/ xed3_phash_find_mapvex_map1_opcode0x6e_vv1, +/*opcode 0x6f*/ xed3_phash_find_mapvex_map1_opcode0x6f_vv1, +/*opcode 0x70*/ xed3_phash_find_mapvex_map1_opcode0x70_vv1, +/*opcode 0x71*/ xed3_phash_find_mapvex_map1_opcode0x71_vv1, +/*opcode 0x72*/ xed3_phash_find_mapvex_map1_opcode0x72_vv1, +/*opcode 0x73*/ xed3_phash_find_mapvex_map1_opcode0x73_vv1, +/*opcode 0x74*/ xed3_phash_find_mapvex_map1_opcode0x74_vv1, +/*opcode 0x75*/ xed3_phash_find_mapvex_map1_opcode0x75_vv1, +/*opcode 0x76*/ xed3_phash_find_mapvex_map1_opcode0x76_vv1, +/*opcode 0x77*/ xed3_phash_find_mapvex_map1_opcode0x77_vv1, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ xed3_phash_find_mapvex_map1_opcode0x7c_vv1, +/*opcode 0x7d*/ xed3_phash_find_mapvex_map1_opcode0x7d_vv1, +/*opcode 0x7e*/ xed3_phash_find_mapvex_map1_opcode0x7e_vv1, +/*opcode 0x7f*/ xed3_phash_find_mapvex_map1_opcode0x7f_vv1, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ xed3_phash_find_mapvex_map1_opcode0x90_vv1, +/*opcode 0x91*/ xed3_phash_find_mapvex_map1_opcode0x91_vv1, +/*opcode 0x92*/ xed3_phash_find_mapvex_map1_opcode0x92_vv1, +/*opcode 0x93*/ xed3_phash_find_mapvex_map1_opcode0x93_vv1, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ xed3_phash_find_mapvex_map1_opcode0x98_vv1, +/*opcode 0x99*/ xed3_phash_find_mapvex_map1_opcode0x99_vv1, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ xed3_phash_find_mapvex_map1_opcode0xae_vv1, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ xed3_phash_find_mapvex_map1_opcode0xc2_vv1, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ xed3_phash_find_mapvex_map1_opcode0xc4_vv1, +/*opcode 0xc5*/ xed3_phash_find_mapvex_map1_opcode0xc5_vv1, +/*opcode 0xc6*/ xed3_phash_find_mapvex_map1_opcode0xc6_vv1, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ xed3_phash_find_mapvex_map1_opcode0xd0_vv1, +/*opcode 0xd1*/ xed3_phash_find_mapvex_map1_opcode0xd1_vv1, +/*opcode 0xd2*/ xed3_phash_find_mapvex_map1_opcode0xd2_vv1, +/*opcode 0xd3*/ xed3_phash_find_mapvex_map1_opcode0xd3_vv1, +/*opcode 0xd4*/ xed3_phash_find_mapvex_map1_opcode0xd4_vv1, +/*opcode 0xd5*/ xed3_phash_find_mapvex_map1_opcode0xd5_vv1, +/*opcode 0xd6*/ xed3_phash_find_mapvex_map1_opcode0xd6_vv1, +/*opcode 0xd7*/ xed3_phash_find_mapvex_map1_opcode0xd7_vv1, +/*opcode 0xd8*/ xed3_phash_find_mapvex_map1_opcode0xd8_vv1, +/*opcode 0xd9*/ xed3_phash_find_mapvex_map1_opcode0xd9_vv1, +/*opcode 0xda*/ xed3_phash_find_mapvex_map1_opcode0xda_vv1, +/*opcode 0xdb*/ xed3_phash_find_mapvex_map1_opcode0xdb_vv1, +/*opcode 0xdc*/ xed3_phash_find_mapvex_map1_opcode0xdc_vv1, +/*opcode 0xdd*/ xed3_phash_find_mapvex_map1_opcode0xdd_vv1, +/*opcode 0xde*/ xed3_phash_find_mapvex_map1_opcode0xde_vv1, +/*opcode 0xdf*/ xed3_phash_find_mapvex_map1_opcode0xdf_vv1, +/*opcode 0xe0*/ xed3_phash_find_mapvex_map1_opcode0xe0_vv1, +/*opcode 0xe1*/ xed3_phash_find_mapvex_map1_opcode0xe1_vv1, +/*opcode 0xe2*/ xed3_phash_find_mapvex_map1_opcode0xe2_vv1, +/*opcode 0xe3*/ xed3_phash_find_mapvex_map1_opcode0xe3_vv1, +/*opcode 0xe4*/ xed3_phash_find_mapvex_map1_opcode0xe4_vv1, +/*opcode 0xe5*/ xed3_phash_find_mapvex_map1_opcode0xe5_vv1, +/*opcode 0xe6*/ xed3_phash_find_mapvex_map1_opcode0xe6_vv1, +/*opcode 0xe7*/ xed3_phash_find_mapvex_map1_opcode0xe7_vv1, +/*opcode 0xe8*/ xed3_phash_find_mapvex_map1_opcode0xe8_vv1, +/*opcode 0xe9*/ xed3_phash_find_mapvex_map1_opcode0xe9_vv1, +/*opcode 0xea*/ xed3_phash_find_mapvex_map1_opcode0xea_vv1, +/*opcode 0xeb*/ xed3_phash_find_mapvex_map1_opcode0xeb_vv1, +/*opcode 0xec*/ xed3_phash_find_mapvex_map1_opcode0xec_vv1, +/*opcode 0xed*/ xed3_phash_find_mapvex_map1_opcode0xed_vv1, +/*opcode 0xee*/ xed3_phash_find_mapvex_map1_opcode0xee_vv1, +/*opcode 0xef*/ xed3_phash_find_mapvex_map1_opcode0xef_vv1, +/*opcode 0xf0*/ xed3_phash_find_mapvex_map1_opcode0xf0_vv1, +/*opcode 0xf1*/ xed3_phash_find_mapvex_map1_opcode0xf1_vv1, +/*opcode 0xf2*/ xed3_phash_find_mapvex_map1_opcode0xf2_vv1, +/*opcode 0xf3*/ xed3_phash_find_mapvex_map1_opcode0xf3_vv1, +/*opcode 0xf4*/ xed3_phash_find_mapvex_map1_opcode0xf4_vv1, +/*opcode 0xf5*/ xed3_phash_find_mapvex_map1_opcode0xf5_vv1, +/*opcode 0xf6*/ xed3_phash_find_mapvex_map1_opcode0xf6_vv1, +/*opcode 0xf7*/ xed3_phash_find_mapvex_map1_opcode0xf7_vv1, +/*opcode 0xf8*/ xed3_phash_find_mapvex_map1_opcode0xf8_vv1, +/*opcode 0xf9*/ xed3_phash_find_mapvex_map1_opcode0xf9_vv1, +/*opcode 0xfa*/ xed3_phash_find_mapvex_map1_opcode0xfa_vv1, +/*opcode 0xfb*/ xed3_phash_find_mapvex_map1_opcode0xfb_vv1, +/*opcode 0xfc*/ xed3_phash_find_mapvex_map1_opcode0xfc_vv1, +/*opcode 0xfd*/ xed3_phash_find_mapvex_map1_opcode0xfd_vv1, +/*opcode 0xfe*/ xed3_phash_find_mapvex_map1_opcode0xfe_vv1, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv1_map_vex_map2[256] = { +/*opcode 0x0*/ xed3_phash_find_mapvex_map2_opcode0x0_vv1, +/*opcode 0x1*/ xed3_phash_find_mapvex_map2_opcode0x1_vv1, +/*opcode 0x2*/ xed3_phash_find_mapvex_map2_opcode0x2_vv1, +/*opcode 0x3*/ xed3_phash_find_mapvex_map2_opcode0x3_vv1, +/*opcode 0x4*/ xed3_phash_find_mapvex_map2_opcode0x4_vv1, +/*opcode 0x5*/ xed3_phash_find_mapvex_map2_opcode0x5_vv1, +/*opcode 0x6*/ xed3_phash_find_mapvex_map2_opcode0x6_vv1, +/*opcode 0x7*/ xed3_phash_find_mapvex_map2_opcode0x7_vv1, +/*opcode 0x8*/ xed3_phash_find_mapvex_map2_opcode0x8_vv1, +/*opcode 0x9*/ xed3_phash_find_mapvex_map2_opcode0x9_vv1, +/*opcode 0xa*/ xed3_phash_find_mapvex_map2_opcode0xa_vv1, +/*opcode 0xb*/ xed3_phash_find_mapvex_map2_opcode0xb_vv1, +/*opcode 0xc*/ xed3_phash_find_mapvex_map2_opcode0xc_vv1, +/*opcode 0xd*/ xed3_phash_find_mapvex_map2_opcode0xd_vv1, +/*opcode 0xe*/ xed3_phash_find_mapvex_map2_opcode0xe_vv1, +/*opcode 0xf*/ xed3_phash_find_mapvex_map2_opcode0xf_vv1, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ xed3_phash_find_mapvex_map2_opcode0x13_vv1, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ xed3_phash_find_mapvex_map2_opcode0x16_vv1, +/*opcode 0x17*/ xed3_phash_find_mapvex_map2_opcode0x17_vv1, +/*opcode 0x18*/ xed3_phash_find_mapvex_map2_opcode0x18_vv1, +/*opcode 0x19*/ xed3_phash_find_mapvex_map2_opcode0x19_vv1, +/*opcode 0x1a*/ xed3_phash_find_mapvex_map2_opcode0x1a_vv1, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ xed3_phash_find_mapvex_map2_opcode0x1c_vv1, +/*opcode 0x1d*/ xed3_phash_find_mapvex_map2_opcode0x1d_vv1, +/*opcode 0x1e*/ xed3_phash_find_mapvex_map2_opcode0x1e_vv1, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ xed3_phash_find_mapvex_map2_opcode0x20_vv1, +/*opcode 0x21*/ xed3_phash_find_mapvex_map2_opcode0x21_vv1, +/*opcode 0x22*/ xed3_phash_find_mapvex_map2_opcode0x22_vv1, +/*opcode 0x23*/ xed3_phash_find_mapvex_map2_opcode0x23_vv1, +/*opcode 0x24*/ xed3_phash_find_mapvex_map2_opcode0x24_vv1, +/*opcode 0x25*/ xed3_phash_find_mapvex_map2_opcode0x25_vv1, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ xed3_phash_find_mapvex_map2_opcode0x28_vv1, +/*opcode 0x29*/ xed3_phash_find_mapvex_map2_opcode0x29_vv1, +/*opcode 0x2a*/ xed3_phash_find_mapvex_map2_opcode0x2a_vv1, +/*opcode 0x2b*/ xed3_phash_find_mapvex_map2_opcode0x2b_vv1, +/*opcode 0x2c*/ xed3_phash_find_mapvex_map2_opcode0x2c_vv1, +/*opcode 0x2d*/ xed3_phash_find_mapvex_map2_opcode0x2d_vv1, +/*opcode 0x2e*/ xed3_phash_find_mapvex_map2_opcode0x2e_vv1, +/*opcode 0x2f*/ xed3_phash_find_mapvex_map2_opcode0x2f_vv1, +/*opcode 0x30*/ xed3_phash_find_mapvex_map2_opcode0x30_vv1, +/*opcode 0x31*/ xed3_phash_find_mapvex_map2_opcode0x31_vv1, +/*opcode 0x32*/ xed3_phash_find_mapvex_map2_opcode0x32_vv1, +/*opcode 0x33*/ xed3_phash_find_mapvex_map2_opcode0x33_vv1, +/*opcode 0x34*/ xed3_phash_find_mapvex_map2_opcode0x34_vv1, +/*opcode 0x35*/ xed3_phash_find_mapvex_map2_opcode0x35_vv1, +/*opcode 0x36*/ xed3_phash_find_mapvex_map2_opcode0x36_vv1, +/*opcode 0x37*/ xed3_phash_find_mapvex_map2_opcode0x37_vv1, +/*opcode 0x38*/ xed3_phash_find_mapvex_map2_opcode0x38_vv1, +/*opcode 0x39*/ xed3_phash_find_mapvex_map2_opcode0x39_vv1, +/*opcode 0x3a*/ xed3_phash_find_mapvex_map2_opcode0x3a_vv1, +/*opcode 0x3b*/ xed3_phash_find_mapvex_map2_opcode0x3b_vv1, +/*opcode 0x3c*/ xed3_phash_find_mapvex_map2_opcode0x3c_vv1, +/*opcode 0x3d*/ xed3_phash_find_mapvex_map2_opcode0x3d_vv1, +/*opcode 0x3e*/ xed3_phash_find_mapvex_map2_opcode0x3e_vv1, +/*opcode 0x3f*/ xed3_phash_find_mapvex_map2_opcode0x3f_vv1, +/*opcode 0x40*/ xed3_phash_find_mapvex_map2_opcode0x40_vv1, +/*opcode 0x41*/ xed3_phash_find_mapvex_map2_opcode0x41_vv1, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ xed3_phash_find_mapvex_map2_opcode0x45_vv1, +/*opcode 0x46*/ xed3_phash_find_mapvex_map2_opcode0x46_vv1, +/*opcode 0x47*/ xed3_phash_find_mapvex_map2_opcode0x47_vv1, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ xed3_phash_find_mapvex_map2_opcode0x49_vv1, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ xed3_phash_find_mapvex_map2_opcode0x4b_vv1, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ xed3_phash_find_mapvex_map2_opcode0x50_vv1, +/*opcode 0x51*/ xed3_phash_find_mapvex_map2_opcode0x51_vv1, +/*opcode 0x52*/ xed3_phash_find_mapvex_map2_opcode0x52_vv1, +/*opcode 0x53*/ xed3_phash_find_mapvex_map2_opcode0x53_vv1, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ xed3_phash_find_mapvex_map2_opcode0x58_vv1, +/*opcode 0x59*/ xed3_phash_find_mapvex_map2_opcode0x59_vv1, +/*opcode 0x5a*/ xed3_phash_find_mapvex_map2_opcode0x5a_vv1, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ xed3_phash_find_mapvex_map2_opcode0x5c_vv1, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ xed3_phash_find_mapvex_map2_opcode0x5e_vv1, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ xed3_phash_find_mapvex_map2_opcode0x78_vv1, +/*opcode 0x79*/ xed3_phash_find_mapvex_map2_opcode0x79_vv1, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ xed3_phash_find_mapvex_map2_opcode0x8c_vv1, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ xed3_phash_find_mapvex_map2_opcode0x8e_vv1, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ xed3_phash_find_mapvex_map2_opcode0x90_vv1, +/*opcode 0x91*/ xed3_phash_find_mapvex_map2_opcode0x91_vv1, +/*opcode 0x92*/ xed3_phash_find_mapvex_map2_opcode0x92_vv1, +/*opcode 0x93*/ xed3_phash_find_mapvex_map2_opcode0x93_vv1, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ xed3_phash_find_mapvex_map2_opcode0x96_vv1, +/*opcode 0x97*/ xed3_phash_find_mapvex_map2_opcode0x97_vv1, +/*opcode 0x98*/ xed3_phash_find_mapvex_map2_opcode0x98_vv1, +/*opcode 0x99*/ xed3_phash_find_mapvex_map2_opcode0x99_vv1, +/*opcode 0x9a*/ xed3_phash_find_mapvex_map2_opcode0x9a_vv1, +/*opcode 0x9b*/ xed3_phash_find_mapvex_map2_opcode0x9b_vv1, +/*opcode 0x9c*/ xed3_phash_find_mapvex_map2_opcode0x9c_vv1, +/*opcode 0x9d*/ xed3_phash_find_mapvex_map2_opcode0x9d_vv1, +/*opcode 0x9e*/ xed3_phash_find_mapvex_map2_opcode0x9e_vv1, +/*opcode 0x9f*/ xed3_phash_find_mapvex_map2_opcode0x9f_vv1, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ xed3_phash_find_mapvex_map2_opcode0xa6_vv1, +/*opcode 0xa7*/ xed3_phash_find_mapvex_map2_opcode0xa7_vv1, +/*opcode 0xa8*/ xed3_phash_find_mapvex_map2_opcode0xa8_vv1, +/*opcode 0xa9*/ xed3_phash_find_mapvex_map2_opcode0xa9_vv1, +/*opcode 0xaa*/ xed3_phash_find_mapvex_map2_opcode0xaa_vv1, +/*opcode 0xab*/ xed3_phash_find_mapvex_map2_opcode0xab_vv1, +/*opcode 0xac*/ xed3_phash_find_mapvex_map2_opcode0xac_vv1, +/*opcode 0xad*/ xed3_phash_find_mapvex_map2_opcode0xad_vv1, +/*opcode 0xae*/ xed3_phash_find_mapvex_map2_opcode0xae_vv1, +/*opcode 0xaf*/ xed3_phash_find_mapvex_map2_opcode0xaf_vv1, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ xed3_phash_find_mapvex_map2_opcode0xb6_vv1, +/*opcode 0xb7*/ xed3_phash_find_mapvex_map2_opcode0xb7_vv1, +/*opcode 0xb8*/ xed3_phash_find_mapvex_map2_opcode0xb8_vv1, +/*opcode 0xb9*/ xed3_phash_find_mapvex_map2_opcode0xb9_vv1, +/*opcode 0xba*/ xed3_phash_find_mapvex_map2_opcode0xba_vv1, +/*opcode 0xbb*/ xed3_phash_find_mapvex_map2_opcode0xbb_vv1, +/*opcode 0xbc*/ xed3_phash_find_mapvex_map2_opcode0xbc_vv1, +/*opcode 0xbd*/ xed3_phash_find_mapvex_map2_opcode0xbd_vv1, +/*opcode 0xbe*/ xed3_phash_find_mapvex_map2_opcode0xbe_vv1, +/*opcode 0xbf*/ xed3_phash_find_mapvex_map2_opcode0xbf_vv1, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ xed3_phash_find_mapvex_map2_opcode0xcf_vv1, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ xed3_phash_find_mapvex_map2_opcode0xdb_vv1, +/*opcode 0xdc*/ xed3_phash_find_mapvex_map2_opcode0xdc_vv1, +/*opcode 0xdd*/ xed3_phash_find_mapvex_map2_opcode0xdd_vv1, +/*opcode 0xde*/ xed3_phash_find_mapvex_map2_opcode0xde_vv1, +/*opcode 0xdf*/ xed3_phash_find_mapvex_map2_opcode0xdf_vv1, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ xed3_phash_find_mapvex_map2_opcode0xf2_vv1, +/*opcode 0xf3*/ xed3_phash_find_mapvex_map2_opcode0xf3_vv1, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ xed3_phash_find_mapvex_map2_opcode0xf5_vv1, +/*opcode 0xf6*/ xed3_phash_find_mapvex_map2_opcode0xf6_vv1, +/*opcode 0xf7*/ xed3_phash_find_mapvex_map2_opcode0xf7_vv1, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv1_map_vex_map3[256] = { +/*opcode 0x0*/ xed3_phash_find_mapvex_map3_opcode0x0_vv1, +/*opcode 0x1*/ xed3_phash_find_mapvex_map3_opcode0x1_vv1, +/*opcode 0x2*/ xed3_phash_find_mapvex_map3_opcode0x2_vv1, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ xed3_phash_find_mapvex_map3_opcode0x4_vv1, +/*opcode 0x5*/ xed3_phash_find_mapvex_map3_opcode0x5_vv1, +/*opcode 0x6*/ xed3_phash_find_mapvex_map3_opcode0x6_vv1, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ xed3_phash_find_mapvex_map3_opcode0x8_vv1, +/*opcode 0x9*/ xed3_phash_find_mapvex_map3_opcode0x9_vv1, +/*opcode 0xa*/ xed3_phash_find_mapvex_map3_opcode0xa_vv1, +/*opcode 0xb*/ xed3_phash_find_mapvex_map3_opcode0xb_vv1, +/*opcode 0xc*/ xed3_phash_find_mapvex_map3_opcode0xc_vv1, +/*opcode 0xd*/ xed3_phash_find_mapvex_map3_opcode0xd_vv1, +/*opcode 0xe*/ xed3_phash_find_mapvex_map3_opcode0xe_vv1, +/*opcode 0xf*/ xed3_phash_find_mapvex_map3_opcode0xf_vv1, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ xed3_phash_find_mapvex_map3_opcode0x14_vv1, +/*opcode 0x15*/ xed3_phash_find_mapvex_map3_opcode0x15_vv1, +/*opcode 0x16*/ xed3_phash_find_mapvex_map3_opcode0x16_vv1, +/*opcode 0x17*/ xed3_phash_find_mapvex_map3_opcode0x17_vv1, +/*opcode 0x18*/ xed3_phash_find_mapvex_map3_opcode0x18_vv1, +/*opcode 0x19*/ xed3_phash_find_mapvex_map3_opcode0x19_vv1, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ xed3_phash_find_mapvex_map3_opcode0x1d_vv1, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ xed3_phash_find_mapvex_map3_opcode0x20_vv1, +/*opcode 0x21*/ xed3_phash_find_mapvex_map3_opcode0x21_vv1, +/*opcode 0x22*/ xed3_phash_find_mapvex_map3_opcode0x22_vv1, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ xed3_phash_find_mapvex_map3_opcode0x30_vv1, +/*opcode 0x31*/ xed3_phash_find_mapvex_map3_opcode0x31_vv1, +/*opcode 0x32*/ xed3_phash_find_mapvex_map3_opcode0x32_vv1, +/*opcode 0x33*/ xed3_phash_find_mapvex_map3_opcode0x33_vv1, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ xed3_phash_find_mapvex_map3_opcode0x38_vv1, +/*opcode 0x39*/ xed3_phash_find_mapvex_map3_opcode0x39_vv1, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ xed3_phash_find_mapvex_map3_opcode0x40_vv1, +/*opcode 0x41*/ xed3_phash_find_mapvex_map3_opcode0x41_vv1, +/*opcode 0x42*/ xed3_phash_find_mapvex_map3_opcode0x42_vv1, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ xed3_phash_find_mapvex_map3_opcode0x44_vv1, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ xed3_phash_find_mapvex_map3_opcode0x46_vv1, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ xed3_phash_find_mapvex_map3_opcode0x48_vv1, +/*opcode 0x49*/ xed3_phash_find_mapvex_map3_opcode0x49_vv1, +/*opcode 0x4a*/ xed3_phash_find_mapvex_map3_opcode0x4a_vv1, +/*opcode 0x4b*/ xed3_phash_find_mapvex_map3_opcode0x4b_vv1, +/*opcode 0x4c*/ xed3_phash_find_mapvex_map3_opcode0x4c_vv1, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ xed3_phash_find_mapvex_map3_opcode0x5c_vv1, +/*opcode 0x5d*/ xed3_phash_find_mapvex_map3_opcode0x5d_vv1, +/*opcode 0x5e*/ xed3_phash_find_mapvex_map3_opcode0x5e_vv1, +/*opcode 0x5f*/ xed3_phash_find_mapvex_map3_opcode0x5f_vv1, +/*opcode 0x60*/ xed3_phash_find_mapvex_map3_opcode0x60_vv1, +/*opcode 0x61*/ xed3_phash_find_mapvex_map3_opcode0x61_vv1, +/*opcode 0x62*/ xed3_phash_find_mapvex_map3_opcode0x62_vv1, +/*opcode 0x63*/ xed3_phash_find_mapvex_map3_opcode0x63_vv1, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ xed3_phash_find_mapvex_map3_opcode0x68_vv1, +/*opcode 0x69*/ xed3_phash_find_mapvex_map3_opcode0x69_vv1, +/*opcode 0x6a*/ xed3_phash_find_mapvex_map3_opcode0x6a_vv1, +/*opcode 0x6b*/ xed3_phash_find_mapvex_map3_opcode0x6b_vv1, +/*opcode 0x6c*/ xed3_phash_find_mapvex_map3_opcode0x6c_vv1, +/*opcode 0x6d*/ xed3_phash_find_mapvex_map3_opcode0x6d_vv1, +/*opcode 0x6e*/ xed3_phash_find_mapvex_map3_opcode0x6e_vv1, +/*opcode 0x6f*/ xed3_phash_find_mapvex_map3_opcode0x6f_vv1, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ xed3_phash_find_mapvex_map3_opcode0x78_vv1, +/*opcode 0x79*/ xed3_phash_find_mapvex_map3_opcode0x79_vv1, +/*opcode 0x7a*/ xed3_phash_find_mapvex_map3_opcode0x7a_vv1, +/*opcode 0x7b*/ xed3_phash_find_mapvex_map3_opcode0x7b_vv1, +/*opcode 0x7c*/ xed3_phash_find_mapvex_map3_opcode0x7c_vv1, +/*opcode 0x7d*/ xed3_phash_find_mapvex_map3_opcode0x7d_vv1, +/*opcode 0x7e*/ xed3_phash_find_mapvex_map3_opcode0x7e_vv1, +/*opcode 0x7f*/ xed3_phash_find_mapvex_map3_opcode0x7f_vv1, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ xed3_phash_find_mapvex_map3_opcode0xce_vv1, +/*opcode 0xcf*/ xed3_phash_find_mapvex_map3_opcode0xcf_vv1, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ xed3_phash_find_mapvex_map3_opcode0xdf_vv1, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ xed3_phash_find_mapvex_map3_opcode0xf0_vv1, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; diff --git a/CodeVirtualizer/build/obj/xed3-phash-lu-vv2.c b/CodeVirtualizer/build/obj/xed3-phash-lu-vv2.c new file mode 100644 index 0000000..424f0b1 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed3-phash-lu-vv2.c @@ -0,0 +1,1314 @@ +/// @file xed3-phash-lu-vv2.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-phash-vv2.h" +const xed3_find_func_t xed3_phash_vv2_map_evex_map1[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_mapevex_map1_opcode0x10_vv2, +/*opcode 0x11*/ xed3_phash_find_mapevex_map1_opcode0x11_vv2, +/*opcode 0x12*/ xed3_phash_find_mapevex_map1_opcode0x12_vv2, +/*opcode 0x13*/ xed3_phash_find_mapevex_map1_opcode0x13_vv2, +/*opcode 0x14*/ xed3_phash_find_mapevex_map1_opcode0x14_vv2, +/*opcode 0x15*/ xed3_phash_find_mapevex_map1_opcode0x15_vv2, +/*opcode 0x16*/ xed3_phash_find_mapevex_map1_opcode0x16_vv2, +/*opcode 0x17*/ xed3_phash_find_mapevex_map1_opcode0x17_vv2, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ xed3_phash_find_mapevex_map1_opcode0x28_vv2, +/*opcode 0x29*/ xed3_phash_find_mapevex_map1_opcode0x29_vv2, +/*opcode 0x2a*/ xed3_phash_find_mapevex_map1_opcode0x2a_vv2, +/*opcode 0x2b*/ xed3_phash_find_mapevex_map1_opcode0x2b_vv2, +/*opcode 0x2c*/ xed3_phash_find_mapevex_map1_opcode0x2c_vv2, +/*opcode 0x2d*/ xed3_phash_find_mapevex_map1_opcode0x2d_vv2, +/*opcode 0x2e*/ xed3_phash_find_mapevex_map1_opcode0x2e_vv2, +/*opcode 0x2f*/ xed3_phash_find_mapevex_map1_opcode0x2f_vv2, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ xed3_phash_find_mapevex_map1_opcode0x51_vv2, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ xed3_phash_find_mapevex_map1_opcode0x54_vv2, +/*opcode 0x55*/ xed3_phash_find_mapevex_map1_opcode0x55_vv2, +/*opcode 0x56*/ xed3_phash_find_mapevex_map1_opcode0x56_vv2, +/*opcode 0x57*/ xed3_phash_find_mapevex_map1_opcode0x57_vv2, +/*opcode 0x58*/ xed3_phash_find_mapevex_map1_opcode0x58_vv2, +/*opcode 0x59*/ xed3_phash_find_mapevex_map1_opcode0x59_vv2, +/*opcode 0x5a*/ xed3_phash_find_mapevex_map1_opcode0x5a_vv2, +/*opcode 0x5b*/ xed3_phash_find_mapevex_map1_opcode0x5b_vv2, +/*opcode 0x5c*/ xed3_phash_find_mapevex_map1_opcode0x5c_vv2, +/*opcode 0x5d*/ xed3_phash_find_mapevex_map1_opcode0x5d_vv2, +/*opcode 0x5e*/ xed3_phash_find_mapevex_map1_opcode0x5e_vv2, +/*opcode 0x5f*/ xed3_phash_find_mapevex_map1_opcode0x5f_vv2, +/*opcode 0x60*/ xed3_phash_find_mapevex_map1_opcode0x60_vv2, +/*opcode 0x61*/ xed3_phash_find_mapevex_map1_opcode0x61_vv2, +/*opcode 0x62*/ xed3_phash_find_mapevex_map1_opcode0x62_vv2, +/*opcode 0x63*/ xed3_phash_find_mapevex_map1_opcode0x63_vv2, +/*opcode 0x64*/ xed3_phash_find_mapevex_map1_opcode0x64_vv2, +/*opcode 0x65*/ xed3_phash_find_mapevex_map1_opcode0x65_vv2, +/*opcode 0x66*/ xed3_phash_find_mapevex_map1_opcode0x66_vv2, +/*opcode 0x67*/ xed3_phash_find_mapevex_map1_opcode0x67_vv2, +/*opcode 0x68*/ xed3_phash_find_mapevex_map1_opcode0x68_vv2, +/*opcode 0x69*/ xed3_phash_find_mapevex_map1_opcode0x69_vv2, +/*opcode 0x6a*/ xed3_phash_find_mapevex_map1_opcode0x6a_vv2, +/*opcode 0x6b*/ xed3_phash_find_mapevex_map1_opcode0x6b_vv2, +/*opcode 0x6c*/ xed3_phash_find_mapevex_map1_opcode0x6c_vv2, +/*opcode 0x6d*/ xed3_phash_find_mapevex_map1_opcode0x6d_vv2, +/*opcode 0x6e*/ xed3_phash_find_mapevex_map1_opcode0x6e_vv2, +/*opcode 0x6f*/ xed3_phash_find_mapevex_map1_opcode0x6f_vv2, +/*opcode 0x70*/ xed3_phash_find_mapevex_map1_opcode0x70_vv2, +/*opcode 0x71*/ xed3_phash_find_mapevex_map1_opcode0x71_vv2, +/*opcode 0x72*/ xed3_phash_find_mapevex_map1_opcode0x72_vv2, +/*opcode 0x73*/ xed3_phash_find_mapevex_map1_opcode0x73_vv2, +/*opcode 0x74*/ xed3_phash_find_mapevex_map1_opcode0x74_vv2, +/*opcode 0x75*/ xed3_phash_find_mapevex_map1_opcode0x75_vv2, +/*opcode 0x76*/ xed3_phash_find_mapevex_map1_opcode0x76_vv2, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ xed3_phash_find_mapevex_map1_opcode0x78_vv2, +/*opcode 0x79*/ xed3_phash_find_mapevex_map1_opcode0x79_vv2, +/*opcode 0x7a*/ xed3_phash_find_mapevex_map1_opcode0x7a_vv2, +/*opcode 0x7b*/ xed3_phash_find_mapevex_map1_opcode0x7b_vv2, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ xed3_phash_find_mapevex_map1_opcode0x7e_vv2, +/*opcode 0x7f*/ xed3_phash_find_mapevex_map1_opcode0x7f_vv2, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ xed3_phash_find_mapevex_map1_opcode0xc2_vv2, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ xed3_phash_find_mapevex_map1_opcode0xc4_vv2, +/*opcode 0xc5*/ xed3_phash_find_mapevex_map1_opcode0xc5_vv2, +/*opcode 0xc6*/ xed3_phash_find_mapevex_map1_opcode0xc6_vv2, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ xed3_phash_find_mapevex_map1_opcode0xd1_vv2, +/*opcode 0xd2*/ xed3_phash_find_mapevex_map1_opcode0xd2_vv2, +/*opcode 0xd3*/ xed3_phash_find_mapevex_map1_opcode0xd3_vv2, +/*opcode 0xd4*/ xed3_phash_find_mapevex_map1_opcode0xd4_vv2, +/*opcode 0xd5*/ xed3_phash_find_mapevex_map1_opcode0xd5_vv2, +/*opcode 0xd6*/ xed3_phash_find_mapevex_map1_opcode0xd6_vv2, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ xed3_phash_find_mapevex_map1_opcode0xd8_vv2, +/*opcode 0xd9*/ xed3_phash_find_mapevex_map1_opcode0xd9_vv2, +/*opcode 0xda*/ xed3_phash_find_mapevex_map1_opcode0xda_vv2, +/*opcode 0xdb*/ xed3_phash_find_mapevex_map1_opcode0xdb_vv2, +/*opcode 0xdc*/ xed3_phash_find_mapevex_map1_opcode0xdc_vv2, +/*opcode 0xdd*/ xed3_phash_find_mapevex_map1_opcode0xdd_vv2, +/*opcode 0xde*/ xed3_phash_find_mapevex_map1_opcode0xde_vv2, +/*opcode 0xdf*/ xed3_phash_find_mapevex_map1_opcode0xdf_vv2, +/*opcode 0xe0*/ xed3_phash_find_mapevex_map1_opcode0xe0_vv2, +/*opcode 0xe1*/ xed3_phash_find_mapevex_map1_opcode0xe1_vv2, +/*opcode 0xe2*/ xed3_phash_find_mapevex_map1_opcode0xe2_vv2, +/*opcode 0xe3*/ xed3_phash_find_mapevex_map1_opcode0xe3_vv2, +/*opcode 0xe4*/ xed3_phash_find_mapevex_map1_opcode0xe4_vv2, +/*opcode 0xe5*/ xed3_phash_find_mapevex_map1_opcode0xe5_vv2, +/*opcode 0xe6*/ xed3_phash_find_mapevex_map1_opcode0xe6_vv2, +/*opcode 0xe7*/ xed3_phash_find_mapevex_map1_opcode0xe7_vv2, +/*opcode 0xe8*/ xed3_phash_find_mapevex_map1_opcode0xe8_vv2, +/*opcode 0xe9*/ xed3_phash_find_mapevex_map1_opcode0xe9_vv2, +/*opcode 0xea*/ xed3_phash_find_mapevex_map1_opcode0xea_vv2, +/*opcode 0xeb*/ xed3_phash_find_mapevex_map1_opcode0xeb_vv2, +/*opcode 0xec*/ xed3_phash_find_mapevex_map1_opcode0xec_vv2, +/*opcode 0xed*/ xed3_phash_find_mapevex_map1_opcode0xed_vv2, +/*opcode 0xee*/ xed3_phash_find_mapevex_map1_opcode0xee_vv2, +/*opcode 0xef*/ xed3_phash_find_mapevex_map1_opcode0xef_vv2, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ xed3_phash_find_mapevex_map1_opcode0xf1_vv2, +/*opcode 0xf2*/ xed3_phash_find_mapevex_map1_opcode0xf2_vv2, +/*opcode 0xf3*/ xed3_phash_find_mapevex_map1_opcode0xf3_vv2, +/*opcode 0xf4*/ xed3_phash_find_mapevex_map1_opcode0xf4_vv2, +/*opcode 0xf5*/ xed3_phash_find_mapevex_map1_opcode0xf5_vv2, +/*opcode 0xf6*/ xed3_phash_find_mapevex_map1_opcode0xf6_vv2, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ xed3_phash_find_mapevex_map1_opcode0xf8_vv2, +/*opcode 0xf9*/ xed3_phash_find_mapevex_map1_opcode0xf9_vv2, +/*opcode 0xfa*/ xed3_phash_find_mapevex_map1_opcode0xfa_vv2, +/*opcode 0xfb*/ xed3_phash_find_mapevex_map1_opcode0xfb_vv2, +/*opcode 0xfc*/ xed3_phash_find_mapevex_map1_opcode0xfc_vv2, +/*opcode 0xfd*/ xed3_phash_find_mapevex_map1_opcode0xfd_vv2, +/*opcode 0xfe*/ xed3_phash_find_mapevex_map1_opcode0xfe_vv2, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv2_map_evex_map2[256] = { +/*opcode 0x0*/ xed3_phash_find_mapevex_map2_opcode0x0_vv2, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ xed3_phash_find_mapevex_map2_opcode0x4_vv2, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ xed3_phash_find_mapevex_map2_opcode0xb_vv2, +/*opcode 0xc*/ xed3_phash_find_mapevex_map2_opcode0xc_vv2, +/*opcode 0xd*/ xed3_phash_find_mapevex_map2_opcode0xd_vv2, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_mapevex_map2_opcode0x10_vv2, +/*opcode 0x11*/ xed3_phash_find_mapevex_map2_opcode0x11_vv2, +/*opcode 0x12*/ xed3_phash_find_mapevex_map2_opcode0x12_vv2, +/*opcode 0x13*/ xed3_phash_find_mapevex_map2_opcode0x13_vv2, +/*opcode 0x14*/ xed3_phash_find_mapevex_map2_opcode0x14_vv2, +/*opcode 0x15*/ xed3_phash_find_mapevex_map2_opcode0x15_vv2, +/*opcode 0x16*/ xed3_phash_find_mapevex_map2_opcode0x16_vv2, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ xed3_phash_find_mapevex_map2_opcode0x18_vv2, +/*opcode 0x19*/ xed3_phash_find_mapevex_map2_opcode0x19_vv2, +/*opcode 0x1a*/ xed3_phash_find_mapevex_map2_opcode0x1a_vv2, +/*opcode 0x1b*/ xed3_phash_find_mapevex_map2_opcode0x1b_vv2, +/*opcode 0x1c*/ xed3_phash_find_mapevex_map2_opcode0x1c_vv2, +/*opcode 0x1d*/ xed3_phash_find_mapevex_map2_opcode0x1d_vv2, +/*opcode 0x1e*/ xed3_phash_find_mapevex_map2_opcode0x1e_vv2, +/*opcode 0x1f*/ xed3_phash_find_mapevex_map2_opcode0x1f_vv2, +/*opcode 0x20*/ xed3_phash_find_mapevex_map2_opcode0x20_vv2, +/*opcode 0x21*/ xed3_phash_find_mapevex_map2_opcode0x21_vv2, +/*opcode 0x22*/ xed3_phash_find_mapevex_map2_opcode0x22_vv2, +/*opcode 0x23*/ xed3_phash_find_mapevex_map2_opcode0x23_vv2, +/*opcode 0x24*/ xed3_phash_find_mapevex_map2_opcode0x24_vv2, +/*opcode 0x25*/ xed3_phash_find_mapevex_map2_opcode0x25_vv2, +/*opcode 0x26*/ xed3_phash_find_mapevex_map2_opcode0x26_vv2, +/*opcode 0x27*/ xed3_phash_find_mapevex_map2_opcode0x27_vv2, +/*opcode 0x28*/ xed3_phash_find_mapevex_map2_opcode0x28_vv2, +/*opcode 0x29*/ xed3_phash_find_mapevex_map2_opcode0x29_vv2, +/*opcode 0x2a*/ xed3_phash_find_mapevex_map2_opcode0x2a_vv2, +/*opcode 0x2b*/ xed3_phash_find_mapevex_map2_opcode0x2b_vv2, +/*opcode 0x2c*/ xed3_phash_find_mapevex_map2_opcode0x2c_vv2, +/*opcode 0x2d*/ xed3_phash_find_mapevex_map2_opcode0x2d_vv2, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ xed3_phash_find_mapevex_map2_opcode0x30_vv2, +/*opcode 0x31*/ xed3_phash_find_mapevex_map2_opcode0x31_vv2, +/*opcode 0x32*/ xed3_phash_find_mapevex_map2_opcode0x32_vv2, +/*opcode 0x33*/ xed3_phash_find_mapevex_map2_opcode0x33_vv2, +/*opcode 0x34*/ xed3_phash_find_mapevex_map2_opcode0x34_vv2, +/*opcode 0x35*/ xed3_phash_find_mapevex_map2_opcode0x35_vv2, +/*opcode 0x36*/ xed3_phash_find_mapevex_map2_opcode0x36_vv2, +/*opcode 0x37*/ xed3_phash_find_mapevex_map2_opcode0x37_vv2, +/*opcode 0x38*/ xed3_phash_find_mapevex_map2_opcode0x38_vv2, +/*opcode 0x39*/ xed3_phash_find_mapevex_map2_opcode0x39_vv2, +/*opcode 0x3a*/ xed3_phash_find_mapevex_map2_opcode0x3a_vv2, +/*opcode 0x3b*/ xed3_phash_find_mapevex_map2_opcode0x3b_vv2, +/*opcode 0x3c*/ xed3_phash_find_mapevex_map2_opcode0x3c_vv2, +/*opcode 0x3d*/ xed3_phash_find_mapevex_map2_opcode0x3d_vv2, +/*opcode 0x3e*/ xed3_phash_find_mapevex_map2_opcode0x3e_vv2, +/*opcode 0x3f*/ xed3_phash_find_mapevex_map2_opcode0x3f_vv2, +/*opcode 0x40*/ xed3_phash_find_mapevex_map2_opcode0x40_vv2, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ xed3_phash_find_mapevex_map2_opcode0x42_vv2, +/*opcode 0x43*/ xed3_phash_find_mapevex_map2_opcode0x43_vv2, +/*opcode 0x44*/ xed3_phash_find_mapevex_map2_opcode0x44_vv2, +/*opcode 0x45*/ xed3_phash_find_mapevex_map2_opcode0x45_vv2, +/*opcode 0x46*/ xed3_phash_find_mapevex_map2_opcode0x46_vv2, +/*opcode 0x47*/ xed3_phash_find_mapevex_map2_opcode0x47_vv2, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ xed3_phash_find_mapevex_map2_opcode0x4c_vv2, +/*opcode 0x4d*/ xed3_phash_find_mapevex_map2_opcode0x4d_vv2, +/*opcode 0x4e*/ xed3_phash_find_mapevex_map2_opcode0x4e_vv2, +/*opcode 0x4f*/ xed3_phash_find_mapevex_map2_opcode0x4f_vv2, +/*opcode 0x50*/ xed3_phash_find_mapevex_map2_opcode0x50_vv2, +/*opcode 0x51*/ xed3_phash_find_mapevex_map2_opcode0x51_vv2, +/*opcode 0x52*/ xed3_phash_find_mapevex_map2_opcode0x52_vv2, +/*opcode 0x53*/ xed3_phash_find_mapevex_map2_opcode0x53_vv2, +/*opcode 0x54*/ xed3_phash_find_mapevex_map2_opcode0x54_vv2, +/*opcode 0x55*/ xed3_phash_find_mapevex_map2_opcode0x55_vv2, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ xed3_phash_find_mapevex_map2_opcode0x58_vv2, +/*opcode 0x59*/ xed3_phash_find_mapevex_map2_opcode0x59_vv2, +/*opcode 0x5a*/ xed3_phash_find_mapevex_map2_opcode0x5a_vv2, +/*opcode 0x5b*/ xed3_phash_find_mapevex_map2_opcode0x5b_vv2, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ xed3_phash_find_mapevex_map2_opcode0x62_vv2, +/*opcode 0x63*/ xed3_phash_find_mapevex_map2_opcode0x63_vv2, +/*opcode 0x64*/ xed3_phash_find_mapevex_map2_opcode0x64_vv2, +/*opcode 0x65*/ xed3_phash_find_mapevex_map2_opcode0x65_vv2, +/*opcode 0x66*/ xed3_phash_find_mapevex_map2_opcode0x66_vv2, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ xed3_phash_find_mapevex_map2_opcode0x68_vv2, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ xed3_phash_find_mapevex_map2_opcode0x70_vv2, +/*opcode 0x71*/ xed3_phash_find_mapevex_map2_opcode0x71_vv2, +/*opcode 0x72*/ xed3_phash_find_mapevex_map2_opcode0x72_vv2, +/*opcode 0x73*/ xed3_phash_find_mapevex_map2_opcode0x73_vv2, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ xed3_phash_find_mapevex_map2_opcode0x75_vv2, +/*opcode 0x76*/ xed3_phash_find_mapevex_map2_opcode0x76_vv2, +/*opcode 0x77*/ xed3_phash_find_mapevex_map2_opcode0x77_vv2, +/*opcode 0x78*/ xed3_phash_find_mapevex_map2_opcode0x78_vv2, +/*opcode 0x79*/ xed3_phash_find_mapevex_map2_opcode0x79_vv2, +/*opcode 0x7a*/ xed3_phash_find_mapevex_map2_opcode0x7a_vv2, +/*opcode 0x7b*/ xed3_phash_find_mapevex_map2_opcode0x7b_vv2, +/*opcode 0x7c*/ xed3_phash_find_mapevex_map2_opcode0x7c_vv2, +/*opcode 0x7d*/ xed3_phash_find_mapevex_map2_opcode0x7d_vv2, +/*opcode 0x7e*/ xed3_phash_find_mapevex_map2_opcode0x7e_vv2, +/*opcode 0x7f*/ xed3_phash_find_mapevex_map2_opcode0x7f_vv2, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ xed3_phash_find_mapevex_map2_opcode0x83_vv2, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ xed3_phash_find_mapevex_map2_opcode0x88_vv2, +/*opcode 0x89*/ xed3_phash_find_mapevex_map2_opcode0x89_vv2, +/*opcode 0x8a*/ xed3_phash_find_mapevex_map2_opcode0x8a_vv2, +/*opcode 0x8b*/ xed3_phash_find_mapevex_map2_opcode0x8b_vv2, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ xed3_phash_find_mapevex_map2_opcode0x8d_vv2, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ xed3_phash_find_mapevex_map2_opcode0x8f_vv2, +/*opcode 0x90*/ xed3_phash_find_mapevex_map2_opcode0x90_vv2, +/*opcode 0x91*/ xed3_phash_find_mapevex_map2_opcode0x91_vv2, +/*opcode 0x92*/ xed3_phash_find_mapevex_map2_opcode0x92_vv2, +/*opcode 0x93*/ xed3_phash_find_mapevex_map2_opcode0x93_vv2, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ xed3_phash_find_mapevex_map2_opcode0x96_vv2, +/*opcode 0x97*/ xed3_phash_find_mapevex_map2_opcode0x97_vv2, +/*opcode 0x98*/ xed3_phash_find_mapevex_map2_opcode0x98_vv2, +/*opcode 0x99*/ xed3_phash_find_mapevex_map2_opcode0x99_vv2, +/*opcode 0x9a*/ xed3_phash_find_mapevex_map2_opcode0x9a_vv2, +/*opcode 0x9b*/ xed3_phash_find_mapevex_map2_opcode0x9b_vv2, +/*opcode 0x9c*/ xed3_phash_find_mapevex_map2_opcode0x9c_vv2, +/*opcode 0x9d*/ xed3_phash_find_mapevex_map2_opcode0x9d_vv2, +/*opcode 0x9e*/ xed3_phash_find_mapevex_map2_opcode0x9e_vv2, +/*opcode 0x9f*/ xed3_phash_find_mapevex_map2_opcode0x9f_vv2, +/*opcode 0xa0*/ xed3_phash_find_mapevex_map2_opcode0xa0_vv2, +/*opcode 0xa1*/ xed3_phash_find_mapevex_map2_opcode0xa1_vv2, +/*opcode 0xa2*/ xed3_phash_find_mapevex_map2_opcode0xa2_vv2, +/*opcode 0xa3*/ xed3_phash_find_mapevex_map2_opcode0xa3_vv2, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ xed3_phash_find_mapevex_map2_opcode0xa6_vv2, +/*opcode 0xa7*/ xed3_phash_find_mapevex_map2_opcode0xa7_vv2, +/*opcode 0xa8*/ xed3_phash_find_mapevex_map2_opcode0xa8_vv2, +/*opcode 0xa9*/ xed3_phash_find_mapevex_map2_opcode0xa9_vv2, +/*opcode 0xaa*/ xed3_phash_find_mapevex_map2_opcode0xaa_vv2, +/*opcode 0xab*/ xed3_phash_find_mapevex_map2_opcode0xab_vv2, +/*opcode 0xac*/ xed3_phash_find_mapevex_map2_opcode0xac_vv2, +/*opcode 0xad*/ xed3_phash_find_mapevex_map2_opcode0xad_vv2, +/*opcode 0xae*/ xed3_phash_find_mapevex_map2_opcode0xae_vv2, +/*opcode 0xaf*/ xed3_phash_find_mapevex_map2_opcode0xaf_vv2, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ xed3_phash_find_mapevex_map2_opcode0xb4_vv2, +/*opcode 0xb5*/ xed3_phash_find_mapevex_map2_opcode0xb5_vv2, +/*opcode 0xb6*/ xed3_phash_find_mapevex_map2_opcode0xb6_vv2, +/*opcode 0xb7*/ xed3_phash_find_mapevex_map2_opcode0xb7_vv2, +/*opcode 0xb8*/ xed3_phash_find_mapevex_map2_opcode0xb8_vv2, +/*opcode 0xb9*/ xed3_phash_find_mapevex_map2_opcode0xb9_vv2, +/*opcode 0xba*/ xed3_phash_find_mapevex_map2_opcode0xba_vv2, +/*opcode 0xbb*/ xed3_phash_find_mapevex_map2_opcode0xbb_vv2, +/*opcode 0xbc*/ xed3_phash_find_mapevex_map2_opcode0xbc_vv2, +/*opcode 0xbd*/ xed3_phash_find_mapevex_map2_opcode0xbd_vv2, +/*opcode 0xbe*/ xed3_phash_find_mapevex_map2_opcode0xbe_vv2, +/*opcode 0xbf*/ xed3_phash_find_mapevex_map2_opcode0xbf_vv2, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ xed3_phash_find_mapevex_map2_opcode0xc4_vv2, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ xed3_phash_find_mapevex_map2_opcode0xc6_vv2, +/*opcode 0xc7*/ xed3_phash_find_mapevex_map2_opcode0xc7_vv2, +/*opcode 0xc8*/ xed3_phash_find_mapevex_map2_opcode0xc8_vv2, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ xed3_phash_find_mapevex_map2_opcode0xca_vv2, +/*opcode 0xcb*/ xed3_phash_find_mapevex_map2_opcode0xcb_vv2, +/*opcode 0xcc*/ xed3_phash_find_mapevex_map2_opcode0xcc_vv2, +/*opcode 0xcd*/ xed3_phash_find_mapevex_map2_opcode0xcd_vv2, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ xed3_phash_find_mapevex_map2_opcode0xcf_vv2, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ xed3_phash_find_mapevex_map2_opcode0xdc_vv2, +/*opcode 0xdd*/ xed3_phash_find_mapevex_map2_opcode0xdd_vv2, +/*opcode 0xde*/ xed3_phash_find_mapevex_map2_opcode0xde_vv2, +/*opcode 0xdf*/ xed3_phash_find_mapevex_map2_opcode0xdf_vv2, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv2_map_evex_map3[256] = { +/*opcode 0x0*/ xed3_phash_find_mapevex_map3_opcode0x0_vv2, +/*opcode 0x1*/ xed3_phash_find_mapevex_map3_opcode0x1_vv2, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ xed3_phash_find_mapevex_map3_opcode0x3_vv2, +/*opcode 0x4*/ xed3_phash_find_mapevex_map3_opcode0x4_vv2, +/*opcode 0x5*/ xed3_phash_find_mapevex_map3_opcode0x5_vv2, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ xed3_phash_find_mapevex_map3_opcode0x8_vv2, +/*opcode 0x9*/ xed3_phash_find_mapevex_map3_opcode0x9_vv2, +/*opcode 0xa*/ xed3_phash_find_mapevex_map3_opcode0xa_vv2, +/*opcode 0xb*/ xed3_phash_find_mapevex_map3_opcode0xb_vv2, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ xed3_phash_find_mapevex_map3_opcode0xf_vv2, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ xed3_phash_find_mapevex_map3_opcode0x14_vv2, +/*opcode 0x15*/ xed3_phash_find_mapevex_map3_opcode0x15_vv2, +/*opcode 0x16*/ xed3_phash_find_mapevex_map3_opcode0x16_vv2, +/*opcode 0x17*/ xed3_phash_find_mapevex_map3_opcode0x17_vv2, +/*opcode 0x18*/ xed3_phash_find_mapevex_map3_opcode0x18_vv2, +/*opcode 0x19*/ xed3_phash_find_mapevex_map3_opcode0x19_vv2, +/*opcode 0x1a*/ xed3_phash_find_mapevex_map3_opcode0x1a_vv2, +/*opcode 0x1b*/ xed3_phash_find_mapevex_map3_opcode0x1b_vv2, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ xed3_phash_find_mapevex_map3_opcode0x1d_vv2, +/*opcode 0x1e*/ xed3_phash_find_mapevex_map3_opcode0x1e_vv2, +/*opcode 0x1f*/ xed3_phash_find_mapevex_map3_opcode0x1f_vv2, +/*opcode 0x20*/ xed3_phash_find_mapevex_map3_opcode0x20_vv2, +/*opcode 0x21*/ xed3_phash_find_mapevex_map3_opcode0x21_vv2, +/*opcode 0x22*/ xed3_phash_find_mapevex_map3_opcode0x22_vv2, +/*opcode 0x23*/ xed3_phash_find_mapevex_map3_opcode0x23_vv2, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ xed3_phash_find_mapevex_map3_opcode0x25_vv2, +/*opcode 0x26*/ xed3_phash_find_mapevex_map3_opcode0x26_vv2, +/*opcode 0x27*/ xed3_phash_find_mapevex_map3_opcode0x27_vv2, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ xed3_phash_find_mapevex_map3_opcode0x38_vv2, +/*opcode 0x39*/ xed3_phash_find_mapevex_map3_opcode0x39_vv2, +/*opcode 0x3a*/ xed3_phash_find_mapevex_map3_opcode0x3a_vv2, +/*opcode 0x3b*/ xed3_phash_find_mapevex_map3_opcode0x3b_vv2, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ xed3_phash_find_mapevex_map3_opcode0x3e_vv2, +/*opcode 0x3f*/ xed3_phash_find_mapevex_map3_opcode0x3f_vv2, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ xed3_phash_find_mapevex_map3_opcode0x42_vv2, +/*opcode 0x43*/ xed3_phash_find_mapevex_map3_opcode0x43_vv2, +/*opcode 0x44*/ xed3_phash_find_mapevex_map3_opcode0x44_vv2, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ xed3_phash_find_mapevex_map3_opcode0x50_vv2, +/*opcode 0x51*/ xed3_phash_find_mapevex_map3_opcode0x51_vv2, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ xed3_phash_find_mapevex_map3_opcode0x54_vv2, +/*opcode 0x55*/ xed3_phash_find_mapevex_map3_opcode0x55_vv2, +/*opcode 0x56*/ xed3_phash_find_mapevex_map3_opcode0x56_vv2, +/*opcode 0x57*/ xed3_phash_find_mapevex_map3_opcode0x57_vv2, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ xed3_phash_find_mapevex_map3_opcode0x66_vv2, +/*opcode 0x67*/ xed3_phash_find_mapevex_map3_opcode0x67_vv2, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ xed3_phash_find_mapevex_map3_opcode0x70_vv2, +/*opcode 0x71*/ xed3_phash_find_mapevex_map3_opcode0x71_vv2, +/*opcode 0x72*/ xed3_phash_find_mapevex_map3_opcode0x72_vv2, +/*opcode 0x73*/ xed3_phash_find_mapevex_map3_opcode0x73_vv2, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ xed3_phash_find_mapevex_map3_opcode0xc2_vv2, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ xed3_phash_find_mapevex_map3_opcode0xce_vv2, +/*opcode 0xcf*/ xed3_phash_find_mapevex_map3_opcode0xcf_vv2, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv2_map_evex_map5[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_mapevex_map5_opcode0x10_vv2, +/*opcode 0x11*/ xed3_phash_find_mapevex_map5_opcode0x11_vv2, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ xed3_phash_find_mapevex_map5_opcode0x1d_vv2, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ xed3_phash_find_mapevex_map5_opcode0x2a_vv2, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ xed3_phash_find_mapevex_map5_opcode0x2c_vv2, +/*opcode 0x2d*/ xed3_phash_find_mapevex_map5_opcode0x2d_vv2, +/*opcode 0x2e*/ xed3_phash_find_mapevex_map5_opcode0x2e_vv2, +/*opcode 0x2f*/ xed3_phash_find_mapevex_map5_opcode0x2f_vv2, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ xed3_phash_find_mapevex_map5_opcode0x51_vv2, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ xed3_phash_find_mapevex_map5_opcode0x58_vv2, +/*opcode 0x59*/ xed3_phash_find_mapevex_map5_opcode0x59_vv2, +/*opcode 0x5a*/ xed3_phash_find_mapevex_map5_opcode0x5a_vv2, +/*opcode 0x5b*/ xed3_phash_find_mapevex_map5_opcode0x5b_vv2, +/*opcode 0x5c*/ xed3_phash_find_mapevex_map5_opcode0x5c_vv2, +/*opcode 0x5d*/ xed3_phash_find_mapevex_map5_opcode0x5d_vv2, +/*opcode 0x5e*/ xed3_phash_find_mapevex_map5_opcode0x5e_vv2, +/*opcode 0x5f*/ xed3_phash_find_mapevex_map5_opcode0x5f_vv2, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ xed3_phash_find_mapevex_map5_opcode0x6e_vv2, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ xed3_phash_find_mapevex_map5_opcode0x78_vv2, +/*opcode 0x79*/ xed3_phash_find_mapevex_map5_opcode0x79_vv2, +/*opcode 0x7a*/ xed3_phash_find_mapevex_map5_opcode0x7a_vv2, +/*opcode 0x7b*/ xed3_phash_find_mapevex_map5_opcode0x7b_vv2, +/*opcode 0x7c*/ xed3_phash_find_mapevex_map5_opcode0x7c_vv2, +/*opcode 0x7d*/ xed3_phash_find_mapevex_map5_opcode0x7d_vv2, +/*opcode 0x7e*/ xed3_phash_find_mapevex_map5_opcode0x7e_vv2, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv2_map_evex_map6[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ xed3_phash_find_mapevex_map6_opcode0x13_vv2, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ xed3_phash_find_mapevex_map6_opcode0x2c_vv2, +/*opcode 0x2d*/ xed3_phash_find_mapevex_map6_opcode0x2d_vv2, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ xed3_phash_find_mapevex_map6_opcode0x42_vv2, +/*opcode 0x43*/ xed3_phash_find_mapevex_map6_opcode0x43_vv2, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ xed3_phash_find_mapevex_map6_opcode0x4c_vv2, +/*opcode 0x4d*/ xed3_phash_find_mapevex_map6_opcode0x4d_vv2, +/*opcode 0x4e*/ xed3_phash_find_mapevex_map6_opcode0x4e_vv2, +/*opcode 0x4f*/ xed3_phash_find_mapevex_map6_opcode0x4f_vv2, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ xed3_phash_find_mapevex_map6_opcode0x56_vv2, +/*opcode 0x57*/ xed3_phash_find_mapevex_map6_opcode0x57_vv2, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ xed3_phash_find_mapevex_map6_opcode0x96_vv2, +/*opcode 0x97*/ xed3_phash_find_mapevex_map6_opcode0x97_vv2, +/*opcode 0x98*/ xed3_phash_find_mapevex_map6_opcode0x98_vv2, +/*opcode 0x99*/ xed3_phash_find_mapevex_map6_opcode0x99_vv2, +/*opcode 0x9a*/ xed3_phash_find_mapevex_map6_opcode0x9a_vv2, +/*opcode 0x9b*/ xed3_phash_find_mapevex_map6_opcode0x9b_vv2, +/*opcode 0x9c*/ xed3_phash_find_mapevex_map6_opcode0x9c_vv2, +/*opcode 0x9d*/ xed3_phash_find_mapevex_map6_opcode0x9d_vv2, +/*opcode 0x9e*/ xed3_phash_find_mapevex_map6_opcode0x9e_vv2, +/*opcode 0x9f*/ xed3_phash_find_mapevex_map6_opcode0x9f_vv2, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ xed3_phash_find_mapevex_map6_opcode0xa6_vv2, +/*opcode 0xa7*/ xed3_phash_find_mapevex_map6_opcode0xa7_vv2, +/*opcode 0xa8*/ xed3_phash_find_mapevex_map6_opcode0xa8_vv2, +/*opcode 0xa9*/ xed3_phash_find_mapevex_map6_opcode0xa9_vv2, +/*opcode 0xaa*/ xed3_phash_find_mapevex_map6_opcode0xaa_vv2, +/*opcode 0xab*/ xed3_phash_find_mapevex_map6_opcode0xab_vv2, +/*opcode 0xac*/ xed3_phash_find_mapevex_map6_opcode0xac_vv2, +/*opcode 0xad*/ xed3_phash_find_mapevex_map6_opcode0xad_vv2, +/*opcode 0xae*/ xed3_phash_find_mapevex_map6_opcode0xae_vv2, +/*opcode 0xaf*/ xed3_phash_find_mapevex_map6_opcode0xaf_vv2, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ xed3_phash_find_mapevex_map6_opcode0xb6_vv2, +/*opcode 0xb7*/ xed3_phash_find_mapevex_map6_opcode0xb7_vv2, +/*opcode 0xb8*/ xed3_phash_find_mapevex_map6_opcode0xb8_vv2, +/*opcode 0xb9*/ xed3_phash_find_mapevex_map6_opcode0xb9_vv2, +/*opcode 0xba*/ xed3_phash_find_mapevex_map6_opcode0xba_vv2, +/*opcode 0xbb*/ xed3_phash_find_mapevex_map6_opcode0xbb_vv2, +/*opcode 0xbc*/ xed3_phash_find_mapevex_map6_opcode0xbc_vv2, +/*opcode 0xbd*/ xed3_phash_find_mapevex_map6_opcode0xbd_vv2, +/*opcode 0xbe*/ xed3_phash_find_mapevex_map6_opcode0xbe_vv2, +/*opcode 0xbf*/ xed3_phash_find_mapevex_map6_opcode0xbf_vv2, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ xed3_phash_find_mapevex_map6_opcode0xd6_vv2, +/*opcode 0xd7*/ xed3_phash_find_mapevex_map6_opcode0xd7_vv2, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; diff --git a/CodeVirtualizer/build/obj/xed3-phash-lu-vv3.c b/CodeVirtualizer/build/obj/xed3-phash-lu-vv3.c new file mode 100644 index 0000000..ca88e46 --- /dev/null +++ b/CodeVirtualizer/build/obj/xed3-phash-lu-vv3.c @@ -0,0 +1,798 @@ +/// @file xed3-phash-lu-vv3.c + +// This file was automatically generated. +// Do not edit this file. + +/*BEGIN_LEGAL + +Copyright (c) 2021 Intel Corporation + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. + +END_LEGAL */ +#include "xed-internal-header.h" +#include "xed3-phash-vv3.h" +const xed3_find_func_t xed3_phash_vv3_map_amd_xop8[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ (xed3_find_func_t)0, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ xed3_phash_find_mapamd_xop8_opcode0x85_vv3, +/*opcode 0x86*/ xed3_phash_find_mapamd_xop8_opcode0x86_vv3, +/*opcode 0x87*/ xed3_phash_find_mapamd_xop8_opcode0x87_vv3, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ xed3_phash_find_mapamd_xop8_opcode0x8e_vv3, +/*opcode 0x8f*/ xed3_phash_find_mapamd_xop8_opcode0x8f_vv3, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ xed3_phash_find_mapamd_xop8_opcode0x95_vv3, +/*opcode 0x96*/ xed3_phash_find_mapamd_xop8_opcode0x96_vv3, +/*opcode 0x97*/ xed3_phash_find_mapamd_xop8_opcode0x97_vv3, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ xed3_phash_find_mapamd_xop8_opcode0x9e_vv3, +/*opcode 0x9f*/ xed3_phash_find_mapamd_xop8_opcode0x9f_vv3, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ xed3_phash_find_mapamd_xop8_opcode0xa2_vv3, +/*opcode 0xa3*/ xed3_phash_find_mapamd_xop8_opcode0xa3_vv3, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ xed3_phash_find_mapamd_xop8_opcode0xa6_vv3, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ xed3_phash_find_mapamd_xop8_opcode0xb6_vv3, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ xed3_phash_find_mapamd_xop8_opcode0xc0_vv3, +/*opcode 0xc1*/ xed3_phash_find_mapamd_xop8_opcode0xc1_vv3, +/*opcode 0xc2*/ xed3_phash_find_mapamd_xop8_opcode0xc2_vv3, +/*opcode 0xc3*/ xed3_phash_find_mapamd_xop8_opcode0xc3_vv3, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ xed3_phash_find_mapamd_xop8_opcode0xcc_vv3, +/*opcode 0xcd*/ xed3_phash_find_mapamd_xop8_opcode0xcd_vv3, +/*opcode 0xce*/ xed3_phash_find_mapamd_xop8_opcode0xce_vv3, +/*opcode 0xcf*/ xed3_phash_find_mapamd_xop8_opcode0xcf_vv3, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ xed3_phash_find_mapamd_xop8_opcode0xec_vv3, +/*opcode 0xed*/ xed3_phash_find_mapamd_xop8_opcode0xed_vv3, +/*opcode 0xee*/ xed3_phash_find_mapamd_xop8_opcode0xee_vv3, +/*opcode 0xef*/ xed3_phash_find_mapamd_xop8_opcode0xef_vv3, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv3_map_amd_xop9[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ xed3_phash_find_mapamd_xop9_opcode0x1_vv3, +/*opcode 0x2*/ xed3_phash_find_mapamd_xop9_opcode0x2_vv3, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ (xed3_find_func_t)0, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ xed3_phash_find_mapamd_xop9_opcode0x12_vv3, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ xed3_phash_find_mapamd_xop9_opcode0x80_vv3, +/*opcode 0x81*/ xed3_phash_find_mapamd_xop9_opcode0x81_vv3, +/*opcode 0x82*/ xed3_phash_find_mapamd_xop9_opcode0x82_vv3, +/*opcode 0x83*/ xed3_phash_find_mapamd_xop9_opcode0x83_vv3, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ xed3_phash_find_mapamd_xop9_opcode0x90_vv3, +/*opcode 0x91*/ xed3_phash_find_mapamd_xop9_opcode0x91_vv3, +/*opcode 0x92*/ xed3_phash_find_mapamd_xop9_opcode0x92_vv3, +/*opcode 0x93*/ xed3_phash_find_mapamd_xop9_opcode0x93_vv3, +/*opcode 0x94*/ xed3_phash_find_mapamd_xop9_opcode0x94_vv3, +/*opcode 0x95*/ xed3_phash_find_mapamd_xop9_opcode0x95_vv3, +/*opcode 0x96*/ xed3_phash_find_mapamd_xop9_opcode0x96_vv3, +/*opcode 0x97*/ xed3_phash_find_mapamd_xop9_opcode0x97_vv3, +/*opcode 0x98*/ xed3_phash_find_mapamd_xop9_opcode0x98_vv3, +/*opcode 0x99*/ xed3_phash_find_mapamd_xop9_opcode0x99_vv3, +/*opcode 0x9a*/ xed3_phash_find_mapamd_xop9_opcode0x9a_vv3, +/*opcode 0x9b*/ xed3_phash_find_mapamd_xop9_opcode0x9b_vv3, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ xed3_phash_find_mapamd_xop9_opcode0xc1_vv3, +/*opcode 0xc2*/ xed3_phash_find_mapamd_xop9_opcode0xc2_vv3, +/*opcode 0xc3*/ xed3_phash_find_mapamd_xop9_opcode0xc3_vv3, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ xed3_phash_find_mapamd_xop9_opcode0xc6_vv3, +/*opcode 0xc7*/ xed3_phash_find_mapamd_xop9_opcode0xc7_vv3, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ xed3_phash_find_mapamd_xop9_opcode0xcb_vv3, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ xed3_phash_find_mapamd_xop9_opcode0xd1_vv3, +/*opcode 0xd2*/ xed3_phash_find_mapamd_xop9_opcode0xd2_vv3, +/*opcode 0xd3*/ xed3_phash_find_mapamd_xop9_opcode0xd3_vv3, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ xed3_phash_find_mapamd_xop9_opcode0xd6_vv3, +/*opcode 0xd7*/ xed3_phash_find_mapamd_xop9_opcode0xd7_vv3, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ xed3_phash_find_mapamd_xop9_opcode0xdb_vv3, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ xed3_phash_find_mapamd_xop9_opcode0xe1_vv3, +/*opcode 0xe2*/ xed3_phash_find_mapamd_xop9_opcode0xe2_vv3, +/*opcode 0xe3*/ xed3_phash_find_mapamd_xop9_opcode0xe3_vv3, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; +const xed3_find_func_t xed3_phash_vv3_map_amd_xopA[256] = { +/*opcode 0x0*/ (xed3_find_func_t)0, +/*opcode 0x1*/ (xed3_find_func_t)0, +/*opcode 0x2*/ (xed3_find_func_t)0, +/*opcode 0x3*/ (xed3_find_func_t)0, +/*opcode 0x4*/ (xed3_find_func_t)0, +/*opcode 0x5*/ (xed3_find_func_t)0, +/*opcode 0x6*/ (xed3_find_func_t)0, +/*opcode 0x7*/ (xed3_find_func_t)0, +/*opcode 0x8*/ (xed3_find_func_t)0, +/*opcode 0x9*/ (xed3_find_func_t)0, +/*opcode 0xa*/ (xed3_find_func_t)0, +/*opcode 0xb*/ (xed3_find_func_t)0, +/*opcode 0xc*/ (xed3_find_func_t)0, +/*opcode 0xd*/ (xed3_find_func_t)0, +/*opcode 0xe*/ (xed3_find_func_t)0, +/*opcode 0xf*/ (xed3_find_func_t)0, +/*opcode 0x10*/ xed3_phash_find_mapamd_xopA_opcode0x10_vv3, +/*opcode 0x11*/ (xed3_find_func_t)0, +/*opcode 0x12*/ xed3_phash_find_mapamd_xopA_opcode0x12_vv3, +/*opcode 0x13*/ (xed3_find_func_t)0, +/*opcode 0x14*/ (xed3_find_func_t)0, +/*opcode 0x15*/ (xed3_find_func_t)0, +/*opcode 0x16*/ (xed3_find_func_t)0, +/*opcode 0x17*/ (xed3_find_func_t)0, +/*opcode 0x18*/ (xed3_find_func_t)0, +/*opcode 0x19*/ (xed3_find_func_t)0, +/*opcode 0x1a*/ (xed3_find_func_t)0, +/*opcode 0x1b*/ (xed3_find_func_t)0, +/*opcode 0x1c*/ (xed3_find_func_t)0, +/*opcode 0x1d*/ (xed3_find_func_t)0, +/*opcode 0x1e*/ (xed3_find_func_t)0, +/*opcode 0x1f*/ (xed3_find_func_t)0, +/*opcode 0x20*/ (xed3_find_func_t)0, +/*opcode 0x21*/ (xed3_find_func_t)0, +/*opcode 0x22*/ (xed3_find_func_t)0, +/*opcode 0x23*/ (xed3_find_func_t)0, +/*opcode 0x24*/ (xed3_find_func_t)0, +/*opcode 0x25*/ (xed3_find_func_t)0, +/*opcode 0x26*/ (xed3_find_func_t)0, +/*opcode 0x27*/ (xed3_find_func_t)0, +/*opcode 0x28*/ (xed3_find_func_t)0, +/*opcode 0x29*/ (xed3_find_func_t)0, +/*opcode 0x2a*/ (xed3_find_func_t)0, +/*opcode 0x2b*/ (xed3_find_func_t)0, +/*opcode 0x2c*/ (xed3_find_func_t)0, +/*opcode 0x2d*/ (xed3_find_func_t)0, +/*opcode 0x2e*/ (xed3_find_func_t)0, +/*opcode 0x2f*/ (xed3_find_func_t)0, +/*opcode 0x30*/ (xed3_find_func_t)0, +/*opcode 0x31*/ (xed3_find_func_t)0, +/*opcode 0x32*/ (xed3_find_func_t)0, +/*opcode 0x33*/ (xed3_find_func_t)0, +/*opcode 0x34*/ (xed3_find_func_t)0, +/*opcode 0x35*/ (xed3_find_func_t)0, +/*opcode 0x36*/ (xed3_find_func_t)0, +/*opcode 0x37*/ (xed3_find_func_t)0, +/*opcode 0x38*/ (xed3_find_func_t)0, +/*opcode 0x39*/ (xed3_find_func_t)0, +/*opcode 0x3a*/ (xed3_find_func_t)0, +/*opcode 0x3b*/ (xed3_find_func_t)0, +/*opcode 0x3c*/ (xed3_find_func_t)0, +/*opcode 0x3d*/ (xed3_find_func_t)0, +/*opcode 0x3e*/ (xed3_find_func_t)0, +/*opcode 0x3f*/ (xed3_find_func_t)0, +/*opcode 0x40*/ (xed3_find_func_t)0, +/*opcode 0x41*/ (xed3_find_func_t)0, +/*opcode 0x42*/ (xed3_find_func_t)0, +/*opcode 0x43*/ (xed3_find_func_t)0, +/*opcode 0x44*/ (xed3_find_func_t)0, +/*opcode 0x45*/ (xed3_find_func_t)0, +/*opcode 0x46*/ (xed3_find_func_t)0, +/*opcode 0x47*/ (xed3_find_func_t)0, +/*opcode 0x48*/ (xed3_find_func_t)0, +/*opcode 0x49*/ (xed3_find_func_t)0, +/*opcode 0x4a*/ (xed3_find_func_t)0, +/*opcode 0x4b*/ (xed3_find_func_t)0, +/*opcode 0x4c*/ (xed3_find_func_t)0, +/*opcode 0x4d*/ (xed3_find_func_t)0, +/*opcode 0x4e*/ (xed3_find_func_t)0, +/*opcode 0x4f*/ (xed3_find_func_t)0, +/*opcode 0x50*/ (xed3_find_func_t)0, +/*opcode 0x51*/ (xed3_find_func_t)0, +/*opcode 0x52*/ (xed3_find_func_t)0, +/*opcode 0x53*/ (xed3_find_func_t)0, +/*opcode 0x54*/ (xed3_find_func_t)0, +/*opcode 0x55*/ (xed3_find_func_t)0, +/*opcode 0x56*/ (xed3_find_func_t)0, +/*opcode 0x57*/ (xed3_find_func_t)0, +/*opcode 0x58*/ (xed3_find_func_t)0, +/*opcode 0x59*/ (xed3_find_func_t)0, +/*opcode 0x5a*/ (xed3_find_func_t)0, +/*opcode 0x5b*/ (xed3_find_func_t)0, +/*opcode 0x5c*/ (xed3_find_func_t)0, +/*opcode 0x5d*/ (xed3_find_func_t)0, +/*opcode 0x5e*/ (xed3_find_func_t)0, +/*opcode 0x5f*/ (xed3_find_func_t)0, +/*opcode 0x60*/ (xed3_find_func_t)0, +/*opcode 0x61*/ (xed3_find_func_t)0, +/*opcode 0x62*/ (xed3_find_func_t)0, +/*opcode 0x63*/ (xed3_find_func_t)0, +/*opcode 0x64*/ (xed3_find_func_t)0, +/*opcode 0x65*/ (xed3_find_func_t)0, +/*opcode 0x66*/ (xed3_find_func_t)0, +/*opcode 0x67*/ (xed3_find_func_t)0, +/*opcode 0x68*/ (xed3_find_func_t)0, +/*opcode 0x69*/ (xed3_find_func_t)0, +/*opcode 0x6a*/ (xed3_find_func_t)0, +/*opcode 0x6b*/ (xed3_find_func_t)0, +/*opcode 0x6c*/ (xed3_find_func_t)0, +/*opcode 0x6d*/ (xed3_find_func_t)0, +/*opcode 0x6e*/ (xed3_find_func_t)0, +/*opcode 0x6f*/ (xed3_find_func_t)0, +/*opcode 0x70*/ (xed3_find_func_t)0, +/*opcode 0x71*/ (xed3_find_func_t)0, +/*opcode 0x72*/ (xed3_find_func_t)0, +/*opcode 0x73*/ (xed3_find_func_t)0, +/*opcode 0x74*/ (xed3_find_func_t)0, +/*opcode 0x75*/ (xed3_find_func_t)0, +/*opcode 0x76*/ (xed3_find_func_t)0, +/*opcode 0x77*/ (xed3_find_func_t)0, +/*opcode 0x78*/ (xed3_find_func_t)0, +/*opcode 0x79*/ (xed3_find_func_t)0, +/*opcode 0x7a*/ (xed3_find_func_t)0, +/*opcode 0x7b*/ (xed3_find_func_t)0, +/*opcode 0x7c*/ (xed3_find_func_t)0, +/*opcode 0x7d*/ (xed3_find_func_t)0, +/*opcode 0x7e*/ (xed3_find_func_t)0, +/*opcode 0x7f*/ (xed3_find_func_t)0, +/*opcode 0x80*/ (xed3_find_func_t)0, +/*opcode 0x81*/ (xed3_find_func_t)0, +/*opcode 0x82*/ (xed3_find_func_t)0, +/*opcode 0x83*/ (xed3_find_func_t)0, +/*opcode 0x84*/ (xed3_find_func_t)0, +/*opcode 0x85*/ (xed3_find_func_t)0, +/*opcode 0x86*/ (xed3_find_func_t)0, +/*opcode 0x87*/ (xed3_find_func_t)0, +/*opcode 0x88*/ (xed3_find_func_t)0, +/*opcode 0x89*/ (xed3_find_func_t)0, +/*opcode 0x8a*/ (xed3_find_func_t)0, +/*opcode 0x8b*/ (xed3_find_func_t)0, +/*opcode 0x8c*/ (xed3_find_func_t)0, +/*opcode 0x8d*/ (xed3_find_func_t)0, +/*opcode 0x8e*/ (xed3_find_func_t)0, +/*opcode 0x8f*/ (xed3_find_func_t)0, +/*opcode 0x90*/ (xed3_find_func_t)0, +/*opcode 0x91*/ (xed3_find_func_t)0, +/*opcode 0x92*/ (xed3_find_func_t)0, +/*opcode 0x93*/ (xed3_find_func_t)0, +/*opcode 0x94*/ (xed3_find_func_t)0, +/*opcode 0x95*/ (xed3_find_func_t)0, +/*opcode 0x96*/ (xed3_find_func_t)0, +/*opcode 0x97*/ (xed3_find_func_t)0, +/*opcode 0x98*/ (xed3_find_func_t)0, +/*opcode 0x99*/ (xed3_find_func_t)0, +/*opcode 0x9a*/ (xed3_find_func_t)0, +/*opcode 0x9b*/ (xed3_find_func_t)0, +/*opcode 0x9c*/ (xed3_find_func_t)0, +/*opcode 0x9d*/ (xed3_find_func_t)0, +/*opcode 0x9e*/ (xed3_find_func_t)0, +/*opcode 0x9f*/ (xed3_find_func_t)0, +/*opcode 0xa0*/ (xed3_find_func_t)0, +/*opcode 0xa1*/ (xed3_find_func_t)0, +/*opcode 0xa2*/ (xed3_find_func_t)0, +/*opcode 0xa3*/ (xed3_find_func_t)0, +/*opcode 0xa4*/ (xed3_find_func_t)0, +/*opcode 0xa5*/ (xed3_find_func_t)0, +/*opcode 0xa6*/ (xed3_find_func_t)0, +/*opcode 0xa7*/ (xed3_find_func_t)0, +/*opcode 0xa8*/ (xed3_find_func_t)0, +/*opcode 0xa9*/ (xed3_find_func_t)0, +/*opcode 0xaa*/ (xed3_find_func_t)0, +/*opcode 0xab*/ (xed3_find_func_t)0, +/*opcode 0xac*/ (xed3_find_func_t)0, +/*opcode 0xad*/ (xed3_find_func_t)0, +/*opcode 0xae*/ (xed3_find_func_t)0, +/*opcode 0xaf*/ (xed3_find_func_t)0, +/*opcode 0xb0*/ (xed3_find_func_t)0, +/*opcode 0xb1*/ (xed3_find_func_t)0, +/*opcode 0xb2*/ (xed3_find_func_t)0, +/*opcode 0xb3*/ (xed3_find_func_t)0, +/*opcode 0xb4*/ (xed3_find_func_t)0, +/*opcode 0xb5*/ (xed3_find_func_t)0, +/*opcode 0xb6*/ (xed3_find_func_t)0, +/*opcode 0xb7*/ (xed3_find_func_t)0, +/*opcode 0xb8*/ (xed3_find_func_t)0, +/*opcode 0xb9*/ (xed3_find_func_t)0, +/*opcode 0xba*/ (xed3_find_func_t)0, +/*opcode 0xbb*/ (xed3_find_func_t)0, +/*opcode 0xbc*/ (xed3_find_func_t)0, +/*opcode 0xbd*/ (xed3_find_func_t)0, +/*opcode 0xbe*/ (xed3_find_func_t)0, +/*opcode 0xbf*/ (xed3_find_func_t)0, +/*opcode 0xc0*/ (xed3_find_func_t)0, +/*opcode 0xc1*/ (xed3_find_func_t)0, +/*opcode 0xc2*/ (xed3_find_func_t)0, +/*opcode 0xc3*/ (xed3_find_func_t)0, +/*opcode 0xc4*/ (xed3_find_func_t)0, +/*opcode 0xc5*/ (xed3_find_func_t)0, +/*opcode 0xc6*/ (xed3_find_func_t)0, +/*opcode 0xc7*/ (xed3_find_func_t)0, +/*opcode 0xc8*/ (xed3_find_func_t)0, +/*opcode 0xc9*/ (xed3_find_func_t)0, +/*opcode 0xca*/ (xed3_find_func_t)0, +/*opcode 0xcb*/ (xed3_find_func_t)0, +/*opcode 0xcc*/ (xed3_find_func_t)0, +/*opcode 0xcd*/ (xed3_find_func_t)0, +/*opcode 0xce*/ (xed3_find_func_t)0, +/*opcode 0xcf*/ (xed3_find_func_t)0, +/*opcode 0xd0*/ (xed3_find_func_t)0, +/*opcode 0xd1*/ (xed3_find_func_t)0, +/*opcode 0xd2*/ (xed3_find_func_t)0, +/*opcode 0xd3*/ (xed3_find_func_t)0, +/*opcode 0xd4*/ (xed3_find_func_t)0, +/*opcode 0xd5*/ (xed3_find_func_t)0, +/*opcode 0xd6*/ (xed3_find_func_t)0, +/*opcode 0xd7*/ (xed3_find_func_t)0, +/*opcode 0xd8*/ (xed3_find_func_t)0, +/*opcode 0xd9*/ (xed3_find_func_t)0, +/*opcode 0xda*/ (xed3_find_func_t)0, +/*opcode 0xdb*/ (xed3_find_func_t)0, +/*opcode 0xdc*/ (xed3_find_func_t)0, +/*opcode 0xdd*/ (xed3_find_func_t)0, +/*opcode 0xde*/ (xed3_find_func_t)0, +/*opcode 0xdf*/ (xed3_find_func_t)0, +/*opcode 0xe0*/ (xed3_find_func_t)0, +/*opcode 0xe1*/ (xed3_find_func_t)0, +/*opcode 0xe2*/ (xed3_find_func_t)0, +/*opcode 0xe3*/ (xed3_find_func_t)0, +/*opcode 0xe4*/ (xed3_find_func_t)0, +/*opcode 0xe5*/ (xed3_find_func_t)0, +/*opcode 0xe6*/ (xed3_find_func_t)0, +/*opcode 0xe7*/ (xed3_find_func_t)0, +/*opcode 0xe8*/ (xed3_find_func_t)0, +/*opcode 0xe9*/ (xed3_find_func_t)0, +/*opcode 0xea*/ (xed3_find_func_t)0, +/*opcode 0xeb*/ (xed3_find_func_t)0, +/*opcode 0xec*/ (xed3_find_func_t)0, +/*opcode 0xed*/ (xed3_find_func_t)0, +/*opcode 0xee*/ (xed3_find_func_t)0, +/*opcode 0xef*/ (xed3_find_func_t)0, +/*opcode 0xf0*/ (xed3_find_func_t)0, +/*opcode 0xf1*/ (xed3_find_func_t)0, +/*opcode 0xf2*/ (xed3_find_func_t)0, +/*opcode 0xf3*/ (xed3_find_func_t)0, +/*opcode 0xf4*/ (xed3_find_func_t)0, +/*opcode 0xf5*/ (xed3_find_func_t)0, +/*opcode 0xf6*/ (xed3_find_func_t)0, +/*opcode 0xf7*/ (xed3_find_func_t)0, +/*opcode 0xf8*/ (xed3_find_func_t)0, +/*opcode 0xf9*/ (xed3_find_func_t)0, +/*opcode 0xfa*/ (xed3_find_func_t)0, +/*opcode 0xfb*/ (xed3_find_func_t)0, +/*opcode 0xfc*/ (xed3_find_func_t)0, +/*opcode 0xfd*/ (xed3_find_func_t)0, +/*opcode 0xfe*/ (xed3_find_func_t)0, +/*opcode 0xff*/ (xed3_find_func_t)0, +}; diff --git a/CodeVirtualizer/build/obj/xed3_nt_cdicts.txt b/CodeVirtualizer/build/obj/xed3_nt_cdicts.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/x64/Debug/Assembly.lst b/CodeVirtualizer/x64/Debug/Assembly.lst index 45493cc..bedac6e 100644 --- a/CodeVirtualizer/x64/Debug/Assembly.lst +++ b/CodeVirtualizer/x64/Debug/Assembly.lst @@ -1,4 +1,4 @@ -Microsoft (R) Macro Assembler (x64) Version 14.27.29111.0 10/14/21 00:59:02 +Microsoft (R) Macro Assembler (x64) Version 14.27.29111.0 10/16/21 19:53:02 Assembly.asm Page 1 - 1 @@ -6,7 +6,7 @@ Assembly.asm Page 1 - 1 END - Microsoft (R) Macro Assembler (x64) Version 14.27.29111.0 10/14/21 00:59:02 + Microsoft (R) Macro Assembler (x64) Version 14.27.29111.0 10/16/21 19:53:02 Assembly.asm Symbols 2 - 1 diff --git a/CodeVirtualizer/x64/Debug/CodeVirtualizer.vcxproj.FileListAbsolute.txt b/CodeVirtualizer/x64/Debug/CodeVirtualizer.vcxproj.FileListAbsolute.txt new file mode 100644 index 0000000..e69de29 diff --git a/CodeVirtualizer/x64/Debug/Jit.cod b/CodeVirtualizer/x64/Debug/Jit.cod index af9c399..394117e 100644 --- a/CodeVirtualizer/x64/Debug/Jit.cod +++ b/CodeVirtualizer/x64/Debug/Jit.cod @@ -147,6 +147,7 @@ EXTRN __imp__invalid_parameter:PROC EXTRN memcpy:PROC EXTRN __imp_wcslen:PROC EXTRN strlen:PROC +EXTRN __imp_rand:PROC EXTRN __imp__calloc_dbg:PROC EXTRN __imp__CrtDbgReport:PROC EXTRN __imp_??0_Lockit@std@@QEAA@H@Z:PROC @@ -403,7 +404,7 @@ pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z DD imagerel $LN25 - DD imagerel $LN25+1205 + DD imagerel $LN25+1241 DD imagerel $unwind$?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z pdata ENDS ; COMDAT pdata @@ -1832,7 +1833,7 @@ RipDelta$ = 256 Value$ = 264 ?JitiEmitWrapperB@@YAHKPEAU_NATIVE_CODE_BLOCK@@HK@Z PROC ; JitiEmitWrapperB, COMDAT -; 283 : { +; 286 : { $LN8: 00000 44 89 4c 24 20 mov DWORD PTR [rsp+32], r9d @@ -1854,7 +1855,7 @@ $LN8: 00 00 lea rcx, OFFSET FLAT:__DD050276_Jit@cpp 0003e e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 284 : switch (OpType) +; 287 : switch (OpType) 00043 8b 85 f0 00 00 00 mov eax, DWORD PTR OpType$[rbp] @@ -1872,8 +1873,8 @@ $LN8: 0006a eb 4f jmp SHORT $LN2@JitiEmitWr $LN4@JitiEmitWr: -; 285 : { -; 286 : case JIT_BITWISE_XOR: return JitEmitRipRelativeXorB(Block, RipDelta, Value); +; 288 : { +; 289 : case JIT_BITWISE_XOR: return JitEmitRipRelativeXorB(Block, RipDelta, Value); 0006c 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -1885,7 +1886,7 @@ $LN4@JitiEmitWr: 00085 eb 34 jmp SHORT $LN1@JitiEmitWr $LN5@JitiEmitWr: -; 287 : case JIT_BITWISE_AND: return JitEmitRipRelativeAndB(Block, RipDelta, Value); +; 290 : case JIT_BITWISE_AND: return JitEmitRipRelativeAndB(Block, RipDelta, Value); 00087 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -1897,7 +1898,7 @@ $LN5@JitiEmitWr: 000a0 eb 19 jmp SHORT $LN1@JitiEmitWr $LN6@JitiEmitWr: -; 288 : case JIT_BITWISE_OR: return JitEmitRipRelativeOrB(Block, RipDelta, Value); +; 291 : case JIT_BITWISE_OR: return JitEmitRipRelativeOrB(Block, RipDelta, Value); 000a2 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -1909,8 +1910,8 @@ $LN6@JitiEmitWr: $LN2@JitiEmitWr: $LN1@JitiEmitWr: -; 289 : } -; 290 : } +; 292 : } +; 293 : } 000bb 48 8d a5 d8 00 00 00 lea rsp, QWORD PTR [rbp+216] @@ -1930,7 +1931,7 @@ RipDelta$ = 256 Value$ = 264 ?JitiEmitWrapperW@@YAHKPEAU_NATIVE_CODE_BLOCK@@HK@Z PROC ; JitiEmitWrapperW, COMDAT -; 274 : { +; 277 : { $LN8: 00000 44 89 4c 24 20 mov DWORD PTR [rsp+32], r9d @@ -1952,7 +1953,7 @@ $LN8: 00 00 lea rcx, OFFSET FLAT:__DD050276_Jit@cpp 0003e e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 275 : switch (OpType) +; 278 : switch (OpType) 00043 8b 85 f0 00 00 00 mov eax, DWORD PTR OpType$[rbp] @@ -1970,8 +1971,8 @@ $LN8: 0006a eb 4f jmp SHORT $LN2@JitiEmitWr $LN4@JitiEmitWr: -; 276 : { -; 277 : case JIT_BITWISE_XOR: return JitEmitRipRelativeXorW(Block, RipDelta, Value); +; 279 : { +; 280 : case JIT_BITWISE_XOR: return JitEmitRipRelativeXorW(Block, RipDelta, Value); 0006c 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -1983,7 +1984,7 @@ $LN4@JitiEmitWr: 00085 eb 34 jmp SHORT $LN1@JitiEmitWr $LN5@JitiEmitWr: -; 278 : case JIT_BITWISE_AND: return JitEmitRipRelativeAndW(Block, RipDelta, Value); +; 281 : case JIT_BITWISE_AND: return JitEmitRipRelativeAndW(Block, RipDelta, Value); 00087 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -1995,7 +1996,7 @@ $LN5@JitiEmitWr: 000a0 eb 19 jmp SHORT $LN1@JitiEmitWr $LN6@JitiEmitWr: -; 279 : case JIT_BITWISE_OR: return JitEmitRipRelativeOrW(Block, RipDelta, Value); +; 282 : case JIT_BITWISE_OR: return JitEmitRipRelativeOrW(Block, RipDelta, Value); 000a2 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -2007,8 +2008,8 @@ $LN6@JitiEmitWr: $LN2@JitiEmitWr: $LN1@JitiEmitWr: -; 280 : } -; 281 : } +; 283 : } +; 284 : } 000bb 48 8d a5 d8 00 00 00 lea rsp, QWORD PTR [rbp+216] @@ -2028,7 +2029,7 @@ RipDelta$ = 256 Value$ = 264 ?JitiEmitWrapperD@@YAHKPEAU_NATIVE_CODE_BLOCK@@HK@Z PROC ; JitiEmitWrapperD, COMDAT -; 265 : { +; 268 : { $LN8: 00000 44 89 4c 24 20 mov DWORD PTR [rsp+32], r9d @@ -2050,7 +2051,7 @@ $LN8: 00 00 lea rcx, OFFSET FLAT:__DD050276_Jit@cpp 0003e e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 266 : switch (OpType) +; 269 : switch (OpType) 00043 8b 85 f0 00 00 00 mov eax, DWORD PTR OpType$[rbp] @@ -2068,8 +2069,8 @@ $LN8: 0006a eb 4f jmp SHORT $LN2@JitiEmitWr $LN4@JitiEmitWr: -; 267 : { -; 268 : case JIT_BITWISE_XOR: return JitEmitRipRelativeXorD(Block, RipDelta, Value); +; 270 : { +; 271 : case JIT_BITWISE_XOR: return JitEmitRipRelativeXorD(Block, RipDelta, Value); 0006c 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -2081,7 +2082,7 @@ $LN4@JitiEmitWr: 00085 eb 34 jmp SHORT $LN1@JitiEmitWr $LN5@JitiEmitWr: -; 269 : case JIT_BITWISE_AND: return JitEmitRipRelativeAndD(Block, RipDelta, Value); +; 272 : case JIT_BITWISE_AND: return JitEmitRipRelativeAndD(Block, RipDelta, Value); 00087 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -2093,7 +2094,7 @@ $LN5@JitiEmitWr: 000a0 eb 19 jmp SHORT $LN1@JitiEmitWr $LN6@JitiEmitWr: -; 270 : case JIT_BITWISE_OR: return JitEmitRipRelativeOrD(Block, RipDelta, Value); +; 273 : case JIT_BITWISE_OR: return JitEmitRipRelativeOrD(Block, RipDelta, Value); 000a2 44 8b 85 08 01 00 00 mov r8d, DWORD PTR Value$[rbp] @@ -2105,8 +2106,8 @@ $LN6@JitiEmitWr: $LN2@JitiEmitWr: $LN1@JitiEmitWr: -; 271 : } -; 272 : } +; 274 : } +; 275 : } 000bb 48 8d a5 d8 00 00 00 lea rsp, QWORD PTR [rbp+216] @@ -2147,7 +2148,7 @@ SaveFlags$ = 728 Delta$ = 736 ?JitEmitPostRipBitwiseOp@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@PEAU_JIT_BITWISE_DATA@@KHH@Z PROC ; JitEmitPostRipBitwiseOp, COMDAT -; 367 : { +; 370 : { $LN29: 00000 44 89 4c 24 20 mov DWORD PTR [rsp+32], r9d @@ -2169,7 +2170,7 @@ $LN29: 00 00 lea rcx, OFFSET FLAT:__DD050276_Jit@cpp 00040 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 368 : ULONG FourByte = Link->RawDataSize / 4; +; 371 : ULONG FourByte = Link->RawDataSize / 4; 00045 33 d2 xor edx, edx 00047 48 8b 85 c0 02 @@ -2179,7 +2180,7 @@ $LN29: 00056 f7 f1 div ecx 00058 89 45 04 mov DWORD PTR FourByte$[rbp], eax -; 369 : ULONG TwoByte = (Link->RawDataSize - (FourByte * 4)) / 2; +; 372 : ULONG TwoByte = (Link->RawDataSize - (FourByte * 4)) / 2; 0005b 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0005e c1 e0 02 shl eax, 2 @@ -2193,7 +2194,7 @@ $LN29: 00076 f7 f1 div ecx 00078 89 45 24 mov DWORD PTR TwoByte$[rbp], eax -; 370 : ULONG OneByte = (Link->RawDataSize - (FourByte * 4) - (TwoByte * 2)); +; 373 : ULONG OneByte = (Link->RawDataSize - (FourByte * 4) - (TwoByte * 2)); 0007b 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0007e c1 e0 02 shl eax, 2 @@ -2207,8 +2208,8 @@ $LN29: 00094 2b c1 sub eax, ecx 00096 89 45 44 mov DWORD PTR OneByte$[rbp], eax -; 371 : -; 372 : PNATIVE_CODE_BLOCK Block = new NATIVE_CODE_BLOCK; +; 374 : +; 375 : PNATIVE_CODE_BLOCK Block = new NATIVE_CODE_BLOCK; 00099 b9 30 00 00 00 mov ecx, 48 ; 00000030H 0009e e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new @@ -2236,19 +2237,19 @@ $LN17@JitEmitPos: 00 00 mov rax, QWORD PTR $T4[rbp] 000e9 48 89 45 68 mov QWORD PTR Block$[rbp], rax -; 373 : if (!Block) +; 376 : if (!Block) 000ed 48 83 7d 68 00 cmp QWORD PTR Block$[rbp], 0 000f2 75 07 jne SHORT $LN4@JitEmitPos -; 374 : return NULL; +; 377 : return NULL; 000f4 33 c0 xor eax, eax 000f6 e9 ed 03 00 00 jmp $LN1@JitEmitPos $LN4@JitEmitPos: -; 375 : -; 376 : if (SaveFlags && !JitEmitPushfqInst(Block)) +; 378 : +; 379 : if (SaveFlags && !JitEmitPushfqInst(Block)) 000fb 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 @@ -2258,13 +2259,13 @@ $LN4@JitEmitPos: 0010d 85 c0 test eax, eax 0010f 75 4a jne SHORT $LN5@JitEmitPos -; 377 : { -; 378 : NcDeleteBlock(Block); +; 380 : { +; 381 : NcDeleteBlock(Block); 00111 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 00115 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 379 : delete Block; +; 382 : delete Block; 0011a 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 0011e 48 89 85 08 02 @@ -2285,30 +2286,30 @@ $LN18@JitEmitPos: 00 mov QWORD PTR tv128[rbp], 0 $LN19@JitEmitPos: -; 380 : return NULL; +; 383 : return NULL; 00154 33 c0 xor eax, eax 00156 e9 8d 03 00 00 jmp $LN1@JitEmitPos $LN5@JitEmitPos: -; 381 : } -; 382 : -; 383 : ULONG Count = FourByte; +; 384 : } +; 385 : +; 386 : ULONG Count = FourByte; 0015b 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0015e 89 85 84 00 00 00 mov DWORD PTR Count$[rbp], eax $LN2@JitEmitPos: -; 384 : while (Count) +; 387 : while (Count) 00164 83 bd 84 00 00 00 00 cmp DWORD PTR Count$[rbp], 0 0016b 0f 84 11 01 00 00 je $LN3@JitEmitPos -; 385 : { -; 386 : INT32 RipDelta = Link->RawDataSize - ((FourByte - Count) * 4); +; 388 : { +; 389 : INT32 RipDelta = Link->RawDataSize - ((FourByte - Count) * 4); 00171 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -2324,13 +2325,13 @@ $LN2@JitEmitPos: 0018f 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 387 : if (SaveFlags) +; 390 : if (SaveFlags) 00195 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 0019c 74 0e je SHORT $LN6@JitEmitPos -; 388 : RipDelta += 1; +; 391 : RipDelta += 1; 0019e 8b 85 a4 00 00 00 mov eax, DWORD PTR RipDelta$1[rbp] @@ -2339,7 +2340,7 @@ $LN2@JitEmitPos: 00 mov DWORD PTR RipDelta$1[rbp], eax $LN6@JitEmitPos: -; 389 : RipDelta += (FourByte - (Count - 1)) * DWORD_RIP_INST_LENGTH; +; 392 : RipDelta += (FourByte - (Count - 1)) * DWORD_RIP_INST_LENGTH; 001ac 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -2355,14 +2356,14 @@ $LN6@JitEmitPos: 001c8 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 390 : RipDelta *= (-1); +; 393 : RipDelta *= (-1); 001ce 6b 85 a4 00 00 00 ff imul eax, DWORD PTR RipDelta$1[rbp], -1 001d5 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 391 : RipDelta += Delta; +; 394 : RipDelta += Delta; 001db 8b 85 e0 02 00 00 mov eax, DWORD PTR Delta$[rbp] @@ -2373,7 +2374,7 @@ $LN6@JitEmitPos: 001eb 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 392 : if (!JitiEmitWrapperD(OpType, Block, RipDelta, JitData->Data[FourByte - Count])) +; 395 : if (!JitiEmitWrapperD(OpType, Block, RipDelta, JitData->Data[FourByte - Count])) 001f1 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -2393,13 +2394,13 @@ $LN6@JitEmitPos: 00221 85 c0 test eax, eax 00223 75 4a jne SHORT $LN7@JitEmitPos -; 393 : { -; 394 : NcDeleteBlock(Block); +; 396 : { +; 397 : NcDeleteBlock(Block); 00225 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 00229 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 395 : delete Block; +; 398 : delete Block; 0022e 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 00232 48 89 85 28 02 @@ -2420,14 +2421,14 @@ $LN20@JitEmitPos: 00 mov QWORD PTR tv158[rbp], 0 $LN21@JitEmitPos: -; 396 : return NULL; +; 399 : return NULL; 00268 33 c0 xor eax, eax 0026a e9 79 02 00 00 jmp $LN1@JitEmitPos $LN7@JitEmitPos: -; 397 : } -; 398 : --Count; +; 400 : } +; 401 : --Count; 0026f 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -2435,20 +2436,20 @@ $LN7@JitEmitPos: 00277 89 85 84 00 00 00 mov DWORD PTR Count$[rbp], eax -; 399 : } +; 402 : } 0027d e9 e2 fe ff ff jmp $LN2@JitEmitPos $LN3@JitEmitPos: -; 400 : -; 401 : if (TwoByte) +; 403 : +; 404 : if (TwoByte) 00282 83 7d 24 00 cmp DWORD PTR TwoByte$[rbp], 0 00286 0f 84 ef 00 00 00 je $LN8@JitEmitPos -; 402 : { -; 403 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4); +; 405 : { +; 406 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4); 0028c 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0028f c1 e0 02 shl eax, 2 @@ -2460,13 +2461,13 @@ $LN3@JitEmitPos: 002a0 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 404 : if (SaveFlags) +; 407 : if (SaveFlags) 002a6 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 002ad 74 0e je SHORT $LN9@JitEmitPos -; 405 : RipDelta += 1; +; 408 : RipDelta += 1; 002af 8b 85 c4 00 00 00 mov eax, DWORD PTR RipDelta$2[rbp] @@ -2475,7 +2476,7 @@ $LN3@JitEmitPos: 00 mov DWORD PTR RipDelta$2[rbp], eax $LN9@JitEmitPos: -; 406 : RipDelta += (FourByte * DWORD_RIP_INST_LENGTH); +; 409 : RipDelta += (FourByte * DWORD_RIP_INST_LENGTH); 002bd 6b 45 04 0a imul eax, DWORD PTR FourByte$[rbp], 10 002c1 8b 8d c4 00 00 @@ -2485,7 +2486,7 @@ $LN9@JitEmitPos: 002cb 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 407 : RipDelta += WORD_RIP_INST_LENGTH; +; 410 : RipDelta += WORD_RIP_INST_LENGTH; 002d1 8b 85 c4 00 00 00 mov eax, DWORD PTR RipDelta$2[rbp] @@ -2493,14 +2494,14 @@ $LN9@JitEmitPos: 002da 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 408 : RipDelta *= (-1); +; 411 : RipDelta *= (-1); 002e0 6b 85 c4 00 00 00 ff imul eax, DWORD PTR RipDelta$2[rbp], -1 002e7 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 409 : RipDelta += Delta; +; 412 : RipDelta += Delta; 002ed 8b 85 e0 02 00 00 mov eax, DWORD PTR Delta$[rbp] @@ -2511,7 +2512,7 @@ $LN9@JitEmitPos: 002fd 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 410 : if (!JitiEmitWrapperW(OpType, Block, RipDelta, JitData->Data[3])) +; 413 : if (!JitiEmitWrapperW(OpType, Block, RipDelta, JitData->Data[3])) 00303 b8 04 00 00 00 mov eax, 4 00308 48 6b c0 03 imul rax, rax, 3 @@ -2527,13 +2528,13 @@ $LN9@JitEmitPos: 0032d 85 c0 test eax, eax 0032f 75 4a jne SHORT $LN8@JitEmitPos -; 411 : { -; 412 : NcDeleteBlock(Block); +; 414 : { +; 415 : NcDeleteBlock(Block); 00331 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 00335 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 413 : delete Block; +; 416 : delete Block; 0033a 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 0033e 48 89 85 48 02 @@ -2554,23 +2555,23 @@ $LN22@JitEmitPos: 00 mov QWORD PTR tv185[rbp], 0 $LN23@JitEmitPos: -; 414 : return NULL; +; 417 : return NULL; 00374 33 c0 xor eax, eax 00376 e9 6d 01 00 00 jmp $LN1@JitEmitPos $LN8@JitEmitPos: -; 415 : } -; 416 : } -; 417 : -; 418 : if (OneByte) +; 418 : } +; 419 : } +; 420 : +; 421 : if (OneByte) 0037b 83 7d 44 00 cmp DWORD PTR OneByte$[rbp], 0 0037f 0f 84 02 01 00 00 je $LN11@JitEmitPos -; 419 : { -; 420 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4) - (TwoByte * 2); +; 422 : { +; 423 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4) - (TwoByte * 2); 00385 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 00388 c1 e0 02 shl eax, 2 @@ -2585,13 +2586,13 @@ $LN8@JitEmitPos: 003a0 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 421 : if (SaveFlags) +; 424 : if (SaveFlags) 003a6 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 003ad 74 0e je SHORT $LN12@JitEmitPos -; 422 : RipDelta += 1; +; 425 : RipDelta += 1; 003af 8b 85 e4 00 00 00 mov eax, DWORD PTR RipDelta$3[rbp] @@ -2600,7 +2601,7 @@ $LN8@JitEmitPos: 00 mov DWORD PTR RipDelta$3[rbp], eax $LN12@JitEmitPos: -; 423 : RipDelta += (FourByte * DWORD_RIP_INST_LENGTH); +; 426 : RipDelta += (FourByte * DWORD_RIP_INST_LENGTH); 003bd 6b 45 04 0a imul eax, DWORD PTR FourByte$[rbp], 10 003c1 8b 8d e4 00 00 @@ -2610,7 +2611,7 @@ $LN12@JitEmitPos: 003cb 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 424 : RipDelta += WORD_RIP_INST_LENGTH; +; 427 : RipDelta += WORD_RIP_INST_LENGTH; 003d1 8b 85 e4 00 00 00 mov eax, DWORD PTR RipDelta$3[rbp] @@ -2618,7 +2619,7 @@ $LN12@JitEmitPos: 003da 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 425 : RipDelta += BYTE_RIP_INST_LENGTH; +; 428 : RipDelta += BYTE_RIP_INST_LENGTH; 003e0 8b 85 e4 00 00 00 mov eax, DWORD PTR RipDelta$3[rbp] @@ -2626,14 +2627,14 @@ $LN12@JitEmitPos: 003e9 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 426 : RipDelta *= (-1); +; 429 : RipDelta *= (-1); 003ef 6b 85 e4 00 00 00 ff imul eax, DWORD PTR RipDelta$3[rbp], -1 003f6 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 427 : RipDelta += Delta; +; 430 : RipDelta += Delta; 003fc 8b 85 e0 02 00 00 mov eax, DWORD PTR Delta$[rbp] @@ -2644,7 +2645,7 @@ $LN12@JitEmitPos: 0040c 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 428 : if (!JitiEmitWrapperB(OpType, Block, RipDelta, JitData->Data[4])) +; 431 : if (!JitiEmitWrapperB(OpType, Block, RipDelta, JitData->Data[4])) 00412 b8 04 00 00 00 mov eax, 4 00417 48 6b c0 04 imul rax, rax, 4 @@ -2660,13 +2661,13 @@ $LN12@JitEmitPos: 0043c 85 c0 test eax, eax 0043e 75 47 jne SHORT $LN11@JitEmitPos -; 429 : { -; 430 : NcDeleteBlock(Block); +; 432 : { +; 433 : NcDeleteBlock(Block); 00440 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 00444 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 431 : delete Block; +; 434 : delete Block; 00449 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 0044d 48 89 85 68 02 @@ -2687,16 +2688,16 @@ $LN24@JitEmitPos: 00 mov QWORD PTR tv214[rbp], 0 $LN25@JitEmitPos: -; 432 : return NULL; +; 435 : return NULL; 00483 33 c0 xor eax, eax 00485 eb 61 jmp SHORT $LN1@JitEmitPos $LN11@JitEmitPos: -; 433 : } -; 434 : } -; 435 : -; 436 : if (SaveFlags && !JitEmitPopfqInst(Block)) +; 436 : } +; 437 : } +; 438 : +; 439 : if (SaveFlags && !JitEmitPopfqInst(Block)) 00487 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 @@ -2706,13 +2707,13 @@ $LN11@JitEmitPos: 00499 85 c0 test eax, eax 0049b 75 47 jne SHORT $LN14@JitEmitPos -; 437 : { -; 438 : NcDeleteBlock(Block); +; 440 : { +; 441 : NcDeleteBlock(Block); 0049d 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 004a1 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 439 : delete Block; +; 442 : delete Block; 004a6 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 004aa 48 89 85 88 02 @@ -2733,20 +2734,20 @@ $LN26@JitEmitPos: 00 mov QWORD PTR tv224[rbp], 0 $LN27@JitEmitPos: -; 440 : return NULL; +; 443 : return NULL; 004e0 33 c0 xor eax, eax 004e2 eb 04 jmp SHORT $LN1@JitEmitPos $LN14@JitEmitPos: -; 441 : } -; 442 : -; 443 : return Block; +; 444 : } +; 445 : +; 446 : return Block; 004e4 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] $LN1@JitEmitPos: -; 444 : } +; 447 : } 004e8 48 8d a5 a8 02 00 00 lea rsp, QWORD PTR [rbp+680] @@ -2878,7 +2879,7 @@ SaveFlags$ = 728 Delta$ = 736 ?JitEmitPreRipBitwiseOp@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@PEAU_JIT_BITWISE_DATA@@KHH@Z PROC ; JitEmitPreRipBitwiseOp, COMDAT -; 293 : { +; 296 : { $LN29: 00000 44 89 4c 24 20 mov DWORD PTR [rsp+32], r9d @@ -2900,7 +2901,7 @@ $LN29: 00 00 lea rcx, OFFSET FLAT:__DD050276_Jit@cpp 00040 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 294 : ULONG FourByte = Link->RawDataSize / 4; +; 297 : ULONG FourByte = Link->RawDataSize / 4; 00045 33 d2 xor edx, edx 00047 48 8b 85 c0 02 @@ -2910,7 +2911,7 @@ $LN29: 00056 f7 f1 div ecx 00058 89 45 04 mov DWORD PTR FourByte$[rbp], eax -; 295 : ULONG TwoByte = (Link->RawDataSize - (FourByte * 4)) / 2; +; 298 : ULONG TwoByte = (Link->RawDataSize - (FourByte * 4)) / 2; 0005b 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0005e c1 e0 02 shl eax, 2 @@ -2924,7 +2925,7 @@ $LN29: 00076 f7 f1 div ecx 00078 89 45 24 mov DWORD PTR TwoByte$[rbp], eax -; 296 : ULONG OneByte = (Link->RawDataSize - (FourByte * 4) - (TwoByte * 2)); +; 299 : ULONG OneByte = (Link->RawDataSize - (FourByte * 4) - (TwoByte * 2)); 0007b 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0007e c1 e0 02 shl eax, 2 @@ -2938,8 +2939,8 @@ $LN29: 00094 2b c1 sub eax, ecx 00096 89 45 44 mov DWORD PTR OneByte$[rbp], eax -; 297 : -; 298 : PNATIVE_CODE_BLOCK Block = new NATIVE_CODE_BLOCK; +; 300 : +; 301 : PNATIVE_CODE_BLOCK Block = new NATIVE_CODE_BLOCK; 00099 b9 30 00 00 00 mov ecx, 48 ; 00000030H 0009e e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new @@ -2967,19 +2968,19 @@ $LN17@JitEmitPre: 00 00 mov rax, QWORD PTR $T4[rbp] 000e9 48 89 45 68 mov QWORD PTR Block$[rbp], rax -; 299 : if (!Block) +; 302 : if (!Block) 000ed 48 83 7d 68 00 cmp QWORD PTR Block$[rbp], 0 000f2 75 07 jne SHORT $LN4@JitEmitPre -; 300 : return NULL; +; 303 : return NULL; 000f4 33 c0 xor eax, eax 000f6 e9 67 03 00 00 jmp $LN1@JitEmitPre $LN4@JitEmitPre: -; 301 : -; 302 : if (SaveFlags && !JitEmitPushfqInst(Block)) +; 304 : +; 305 : if (SaveFlags && !JitEmitPushfqInst(Block)) 000fb 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 @@ -2989,13 +2990,13 @@ $LN4@JitEmitPre: 0010d 85 c0 test eax, eax 0010f 75 4a jne SHORT $LN5@JitEmitPre -; 303 : { -; 304 : NcDeleteBlock(Block); +; 306 : { +; 307 : NcDeleteBlock(Block); 00111 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 00115 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 305 : delete Block; +; 308 : delete Block; 0011a 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 0011e 48 89 85 08 02 @@ -3016,30 +3017,30 @@ $LN18@JitEmitPre: 00 mov QWORD PTR tv128[rbp], 0 $LN19@JitEmitPre: -; 306 : return NULL; +; 309 : return NULL; 00154 33 c0 xor eax, eax 00156 e9 07 03 00 00 jmp $LN1@JitEmitPre $LN5@JitEmitPre: -; 307 : } -; 308 : -; 309 : ULONG Count = FourByte; +; 310 : } +; 311 : +; 312 : ULONG Count = FourByte; 0015b 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] 0015e 89 85 84 00 00 00 mov DWORD PTR Count$[rbp], eax $LN2@JitEmitPre: -; 310 : while (Count) +; 313 : while (Count) 00164 83 bd 84 00 00 00 00 cmp DWORD PTR Count$[rbp], 0 0016b 0f 84 f7 00 00 00 je $LN3@JitEmitPre -; 311 : { -; 312 : INT32 RipDelta = (((Count - 1) * DWORD_RIP_INST_LENGTH) + (TwoByte * WORD_RIP_INST_LENGTH) + (OneByte * BYTE_RIP_INST_LENGTH)); +; 314 : { +; 315 : INT32 RipDelta = (((Count - 1) * DWORD_RIP_INST_LENGTH) + (TwoByte * WORD_RIP_INST_LENGTH) + (OneByte * BYTE_RIP_INST_LENGTH)); 00171 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -3052,13 +3053,13 @@ $LN2@JitEmitPre: 00188 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 313 : if (SaveFlags) +; 316 : if (SaveFlags) 0018e 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 00195 74 0e je SHORT $LN6@JitEmitPre -; 314 : RipDelta += 1; +; 317 : RipDelta += 1; 00197 8b 85 a4 00 00 00 mov eax, DWORD PTR RipDelta$1[rbp] @@ -3067,7 +3068,7 @@ $LN2@JitEmitPre: 00 mov DWORD PTR RipDelta$1[rbp], eax $LN6@JitEmitPre: -; 315 : RipDelta += ((FourByte - Count) * 4); +; 318 : RipDelta += ((FourByte - Count) * 4); 001a5 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -3080,7 +3081,7 @@ $LN6@JitEmitPre: 001bb 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 316 : RipDelta += Delta; +; 319 : RipDelta += Delta; 001c1 8b 85 e0 02 00 00 mov eax, DWORD PTR Delta$[rbp] @@ -3091,7 +3092,7 @@ $LN6@JitEmitPre: 001d1 89 85 a4 00 00 00 mov DWORD PTR RipDelta$1[rbp], eax -; 317 : if (!JitiEmitWrapperD(OpType, Block, RipDelta, JitData->Data[FourByte - Count])) +; 320 : if (!JitiEmitWrapperD(OpType, Block, RipDelta, JitData->Data[FourByte - Count])) 001d7 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -3111,13 +3112,13 @@ $LN6@JitEmitPre: 00207 85 c0 test eax, eax 00209 75 4a jne SHORT $LN7@JitEmitPre -; 318 : { -; 319 : NcDeleteBlock(Block); +; 321 : { +; 322 : NcDeleteBlock(Block); 0020b 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 0020f e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 320 : delete Block; +; 323 : delete Block; 00214 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 00218 48 89 85 28 02 @@ -3138,14 +3139,14 @@ $LN20@JitEmitPre: 00 mov QWORD PTR tv158[rbp], 0 $LN21@JitEmitPre: -; 321 : return NULL; +; 324 : return NULL; 0024e 33 c0 xor eax, eax 00250 e9 0d 02 00 00 jmp $LN1@JitEmitPre $LN7@JitEmitPre: -; 322 : } -; 323 : --Count; +; 325 : } +; 326 : --Count; 00255 8b 85 84 00 00 00 mov eax, DWORD PTR Count$[rbp] @@ -3153,32 +3154,32 @@ $LN7@JitEmitPre: 0025d 89 85 84 00 00 00 mov DWORD PTR Count$[rbp], eax -; 324 : } +; 327 : } 00263 e9 fc fe ff ff jmp $LN2@JitEmitPre $LN3@JitEmitPre: -; 325 : -; 326 : if (TwoByte) +; 328 : +; 329 : if (TwoByte) 00268 83 7d 24 00 cmp DWORD PTR TwoByte$[rbp], 0 0026c 0f 84 c1 00 00 00 je $LN8@JitEmitPre -; 327 : { -; 328 : INT32 RipDelta = (OneByte * BYTE_RIP_INST_LENGTH); +; 330 : { +; 331 : INT32 RipDelta = (OneByte * BYTE_RIP_INST_LENGTH); 00272 6b 45 44 07 imul eax, DWORD PTR OneByte$[rbp], 7 00276 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 329 : if (SaveFlags) +; 332 : if (SaveFlags) 0027c 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 00283 74 0e je SHORT $LN9@JitEmitPre -; 330 : RipDelta += 1; +; 333 : RipDelta += 1; 00285 8b 85 c4 00 00 00 mov eax, DWORD PTR RipDelta$2[rbp] @@ -3187,7 +3188,7 @@ $LN3@JitEmitPre: 00 mov DWORD PTR RipDelta$2[rbp], eax $LN9@JitEmitPre: -; 331 : RipDelta += (FourByte * 4); +; 334 : RipDelta += (FourByte * 4); 00293 8b 85 c4 00 00 00 mov eax, DWORD PTR RipDelta$2[rbp] @@ -3196,7 +3197,7 @@ $LN9@JitEmitPre: 0029f 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 332 : RipDelta += Delta; +; 335 : RipDelta += Delta; 002a5 8b 85 e0 02 00 00 mov eax, DWORD PTR Delta$[rbp] @@ -3207,7 +3208,7 @@ $LN9@JitEmitPre: 002b5 89 85 c4 00 00 00 mov DWORD PTR RipDelta$2[rbp], eax -; 333 : if (!JitiEmitWrapperW(OpType, Block, RipDelta, JitData->Data[3])) +; 336 : if (!JitiEmitWrapperW(OpType, Block, RipDelta, JitData->Data[3])) 002bb b8 04 00 00 00 mov eax, 4 002c0 48 6b c0 03 imul rax, rax, 3 @@ -3223,13 +3224,13 @@ $LN9@JitEmitPre: 002e5 85 c0 test eax, eax 002e7 75 4a jne SHORT $LN8@JitEmitPre -; 334 : { -; 335 : NcDeleteBlock(Block); +; 337 : { +; 338 : NcDeleteBlock(Block); 002e9 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 002ed e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 336 : delete Block; +; 339 : delete Block; 002f2 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 002f6 48 89 85 48 02 @@ -3250,34 +3251,34 @@ $LN22@JitEmitPre: 00 mov QWORD PTR tv181[rbp], 0 $LN23@JitEmitPre: -; 337 : return NULL; +; 340 : return NULL; 0032c 33 c0 xor eax, eax 0032e e9 2f 01 00 00 jmp $LN1@JitEmitPre $LN8@JitEmitPre: -; 338 : } -; 339 : } -; 340 : -; 341 : if (OneByte) +; 341 : } +; 342 : } +; 343 : +; 344 : if (OneByte) 00333 83 7d 44 00 cmp DWORD PTR OneByte$[rbp], 0 00337 0f 84 c4 00 00 00 je $LN11@JitEmitPre -; 342 : { -; 343 : INT32 RipDelta = 0; +; 345 : { +; 346 : INT32 RipDelta = 0; 0033d c7 85 e4 00 00 00 00 00 00 00 mov DWORD PTR RipDelta$3[rbp], 0 -; 344 : if (SaveFlags) +; 347 : if (SaveFlags) 00347 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 0034e 74 0e je SHORT $LN12@JitEmitPre -; 345 : RipDelta += 1; +; 348 : RipDelta += 1; 00350 8b 85 e4 00 00 00 mov eax, DWORD PTR RipDelta$3[rbp] @@ -3286,7 +3287,7 @@ $LN8@JitEmitPre: 00 mov DWORD PTR RipDelta$3[rbp], eax $LN12@JitEmitPre: -; 346 : RipDelta += (FourByte * 4) + (TwoByte * 2); +; 349 : RipDelta += (FourByte * 4) + (TwoByte * 2); 0035e 8b 85 e4 00 00 00 mov eax, DWORD PTR RipDelta$3[rbp] @@ -3297,7 +3298,7 @@ $LN12@JitEmitPre: 00370 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 347 : RipDelta += Delta; +; 350 : RipDelta += Delta; 00376 8b 85 e0 02 00 00 mov eax, DWORD PTR Delta$[rbp] @@ -3308,7 +3309,7 @@ $LN12@JitEmitPre: 00386 89 85 e4 00 00 00 mov DWORD PTR RipDelta$3[rbp], eax -; 348 : if (!JitiEmitWrapperB(OpType, Block, RipDelta, JitData->Data[4])) +; 351 : if (!JitiEmitWrapperB(OpType, Block, RipDelta, JitData->Data[4])) 0038c b8 04 00 00 00 mov eax, 4 00391 48 6b c0 04 imul rax, rax, 4 @@ -3324,13 +3325,13 @@ $LN12@JitEmitPre: 003b6 85 c0 test eax, eax 003b8 75 47 jne SHORT $LN11@JitEmitPre -; 349 : { -; 350 : NcDeleteBlock(Block); +; 352 : { +; 353 : NcDeleteBlock(Block); 003ba 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 003be e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 351 : delete Block; +; 354 : delete Block; 003c3 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 003c7 48 89 85 68 02 @@ -3351,16 +3352,16 @@ $LN24@JitEmitPre: 00 mov QWORD PTR tv204[rbp], 0 $LN25@JitEmitPre: -; 352 : return NULL; +; 355 : return NULL; 003fd 33 c0 xor eax, eax 003ff eb 61 jmp SHORT $LN1@JitEmitPre $LN11@JitEmitPre: -; 353 : } -; 354 : } -; 355 : -; 356 : if (SaveFlags && !JitEmitPopfqInst(Block)) +; 356 : } +; 357 : } +; 358 : +; 359 : if (SaveFlags && !JitEmitPopfqInst(Block)) 00401 83 bd d8 02 00 00 00 cmp DWORD PTR SaveFlags$[rbp], 0 @@ -3370,13 +3371,13 @@ $LN11@JitEmitPre: 00413 85 c0 test eax, eax 00415 75 47 jne SHORT $LN14@JitEmitPre -; 357 : { -; 358 : NcDeleteBlock(Block); +; 360 : { +; 361 : NcDeleteBlock(Block); 00417 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] 0041b e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 359 : delete Block; +; 362 : delete Block; 00420 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] 00424 48 89 85 88 02 @@ -3397,20 +3398,20 @@ $LN26@JitEmitPre: 00 mov QWORD PTR tv214[rbp], 0 $LN27@JitEmitPre: -; 360 : return NULL; +; 363 : return NULL; 0045a 33 c0 xor eax, eax 0045c eb 04 jmp SHORT $LN1@JitEmitPre $LN14@JitEmitPre: -; 361 : } -; 362 : -; 363 : return Block; +; 364 : } +; 365 : +; 366 : return Block; 0045e 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] $LN1@JitEmitPre: -; 364 : } +; 367 : } 00462 48 8d a5 a8 02 00 00 lea rsp, QWORD PTR [rbp+680] @@ -3532,10 +3533,10 @@ $T11 = 840 $T12 = 872 $T13 = 904 $T14 = 936 -tv210 = 952 -tv197 = 952 -tv173 = 952 -tv152 = 952 +tv213 = 952 +tv200 = 952 +tv175 = 952 +tv153 = 952 tv131 = 952 tv86 = 952 __$ArrayPad$ = 960 @@ -3685,7 +3686,7 @@ $LN2@JitEmitPos: 0016c 83 bd a4 00 00 00 00 cmp DWORD PTR Count$[rbp], 0 - 00173 0f 84 e0 00 00 + 00173 0f 84 ec 00 00 00 je $LN3@JitEmitPos ; 210 : { @@ -3739,356 +3740,377 @@ $LN2@JitEmitPos: 001dc 89 85 c4 00 00 00 mov DWORD PTR RipDelta$4[rbp], eax -; 215 : if (!JitEmitRipRelativeMovD(Block, RipDelta, (PUCHAR)&ZeroValue)) +; 215 : ZeroValue = rand(); + + 001e2 ff 15 00 00 00 + 00 call QWORD PTR __imp_rand + 001e8 89 85 84 00 00 + 00 mov DWORD PTR ZeroValue$[rbp], eax - 001e2 4c 8d 85 84 00 +; 216 : if (!JitEmitRipRelativeMovD(Block, RipDelta, (PUCHAR)&ZeroValue)) + + 001ee 4c 8d 85 84 00 00 00 lea r8, QWORD PTR ZeroValue$[rbp] - 001e9 8b 95 c4 00 00 + 001f5 8b 95 c4 00 00 00 mov edx, DWORD PTR RipDelta$4[rbp] - 001ef 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 001f3 e8 00 00 00 00 call ?JitEmitRipRelativeMovD@@YAHPEAU_NATIVE_CODE_BLOCK@@HPEAE@Z ; JitEmitRipRelativeMovD - 001f8 85 c0 test eax, eax - 001fa 75 4a jne SHORT $LN4@JitEmitPos + 001fb 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 001ff e8 00 00 00 00 call ?JitEmitRipRelativeMovD@@YAHPEAU_NATIVE_CODE_BLOCK@@HPEAE@Z ; JitEmitRipRelativeMovD + 00204 85 c0 test eax, eax + 00206 75 4a jne SHORT $LN4@JitEmitPos -; 216 : { -; 217 : NcDeleteBlock(Block); +; 217 : { +; 218 : NcDeleteBlock(Block); - 001fc 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 00200 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock + 00208 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 0020c e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 218 : delete Block; +; 219 : delete Block; - 00205 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 00209 48 89 85 48 03 + 00211 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 00215 48 89 85 48 03 00 00 mov QWORD PTR $T11[rbp], rax - 00210 48 83 bd 48 03 + 0021c 48 83 bd 48 03 00 00 00 cmp QWORD PTR $T11[rbp], 0 - 00218 74 1a je SHORT $LN15@JitEmitPos - 0021a ba 01 00 00 00 mov edx, 1 - 0021f 48 8b 8d 48 03 + 00224 74 1a je SHORT $LN15@JitEmitPos + 00226 ba 01 00 00 00 mov edx, 1 + 0022b 48 8b 8d 48 03 00 00 mov rcx, QWORD PTR $T11[rbp] - 00226 e8 00 00 00 00 call ??_G_NATIVE_CODE_BLOCK@@QEAAPEAXI@Z - 0022b 48 89 85 b8 03 - 00 00 mov QWORD PTR tv152[rbp], rax - 00232 eb 0b jmp SHORT $LN16@JitEmitPos + 00232 e8 00 00 00 00 call ??_G_NATIVE_CODE_BLOCK@@QEAAPEAXI@Z + 00237 48 89 85 b8 03 + 00 00 mov QWORD PTR tv153[rbp], rax + 0023e eb 0b jmp SHORT $LN16@JitEmitPos $LN15@JitEmitPos: - 00234 48 c7 85 b8 03 + 00240 48 c7 85 b8 03 00 00 00 00 00 - 00 mov QWORD PTR tv152[rbp], 0 + 00 mov QWORD PTR tv153[rbp], 0 $LN16@JitEmitPos: -; 219 : return NULL; +; 220 : return NULL; - 0023f 33 c0 xor eax, eax - 00241 e9 40 02 00 00 jmp $LN1@JitEmitPos + 0024b 33 c0 xor eax, eax + 0024d e9 58 02 00 00 jmp $LN1@JitEmitPos $LN4@JitEmitPos: -; 220 : } -; 221 : --Count; +; 221 : } +; 222 : --Count; - 00246 8b 85 a4 00 00 + 00252 8b 85 a4 00 00 00 mov eax, DWORD PTR Count$[rbp] - 0024c ff c8 dec eax - 0024e 89 85 a4 00 00 + 00258 ff c8 dec eax + 0025a 89 85 a4 00 00 00 mov DWORD PTR Count$[rbp], eax -; 222 : } +; 223 : } - 00254 e9 13 ff ff ff jmp $LN2@JitEmitPos + 00260 e9 07 ff ff ff jmp $LN2@JitEmitPos $LN3@JitEmitPos: -; 223 : -; 224 : if (TwoByte) +; 224 : +; 225 : if (TwoByte) - 00259 83 7d 24 00 cmp DWORD PTR TwoByte$[rbp], 0 - 0025d 0f 84 c4 00 00 + 00265 83 7d 24 00 cmp DWORD PTR TwoByte$[rbp], 0 + 00269 0f 84 d0 00 00 00 je $LN5@JitEmitPos -; 225 : { -; 226 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4); +; 226 : { +; 227 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4); - 00263 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] - 00266 c1 e0 02 shl eax, 2 - 00269 48 8b 8d f0 03 + 0026f 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] + 00272 c1 e0 02 shl eax, 2 + 00275 48 8b 8d f0 03 00 00 mov rcx, QWORD PTR Link$[rbp] - 00270 8b 49 28 mov ecx, DWORD PTR [rcx+40] - 00273 2b c8 sub ecx, eax - 00275 8b c1 mov eax, ecx - 00277 89 85 e4 00 00 + 0027c 8b 49 28 mov ecx, DWORD PTR [rcx+40] + 0027f 2b c8 sub ecx, eax + 00281 8b c1 mov eax, ecx + 00283 89 85 e4 00 00 00 mov DWORD PTR RipDelta$5[rbp], eax -; 227 : RipDelta += (FourByte * DWORD_MOV_INST_LENGTH); +; 228 : RipDelta += (FourByte * DWORD_MOV_INST_LENGTH); - 0027d 6b 45 04 0a imul eax, DWORD PTR FourByte$[rbp], 10 - 00281 8b 8d e4 00 00 + 00289 6b 45 04 0a imul eax, DWORD PTR FourByte$[rbp], 10 + 0028d 8b 8d e4 00 00 00 mov ecx, DWORD PTR RipDelta$5[rbp] - 00287 03 c8 add ecx, eax - 00289 8b c1 mov eax, ecx - 0028b 89 85 e4 00 00 + 00293 03 c8 add ecx, eax + 00295 8b c1 mov eax, ecx + 00297 89 85 e4 00 00 00 mov DWORD PTR RipDelta$5[rbp], eax -; 228 : RipDelta += WORD_MOV_INST_LENGTH; +; 229 : RipDelta += WORD_MOV_INST_LENGTH; - 00291 8b 85 e4 00 00 + 0029d 8b 85 e4 00 00 00 mov eax, DWORD PTR RipDelta$5[rbp] - 00297 83 c0 09 add eax, 9 - 0029a 89 85 e4 00 00 + 002a3 83 c0 09 add eax, 9 + 002a6 89 85 e4 00 00 00 mov DWORD PTR RipDelta$5[rbp], eax -; 229 : RipDelta *= (-1); +; 230 : RipDelta *= (-1); - 002a0 6b 85 e4 00 00 + 002ac 6b 85 e4 00 00 00 ff imul eax, DWORD PTR RipDelta$5[rbp], -1 - 002a7 89 85 e4 00 00 + 002b3 89 85 e4 00 00 00 mov DWORD PTR RipDelta$5[rbp], eax -; 230 : RipDelta += Delta; +; 231 : RipDelta += Delta; - 002ad 8b 85 f8 03 00 + 002b9 8b 85 f8 03 00 00 mov eax, DWORD PTR Delta$[rbp] - 002b3 8b 8d e4 00 00 + 002bf 8b 8d e4 00 00 00 mov ecx, DWORD PTR RipDelta$5[rbp] - 002b9 03 c8 add ecx, eax - 002bb 8b c1 mov eax, ecx - 002bd 89 85 e4 00 00 + 002c5 03 c8 add ecx, eax + 002c7 8b c1 mov eax, ecx + 002c9 89 85 e4 00 00 00 mov DWORD PTR RipDelta$5[rbp], eax -; 231 : if (!JitEmitRipRelativeMovW(Block, RipDelta, (PUCHAR)&ZeroValue)) +; 232 : ZeroValue = rand(); + + 002cf ff 15 00 00 00 + 00 call QWORD PTR __imp_rand + 002d5 89 85 84 00 00 + 00 mov DWORD PTR ZeroValue$[rbp], eax + +; 233 : if (!JitEmitRipRelativeMovW(Block, RipDelta, (PUCHAR)&ZeroValue)) - 002c3 4c 8d 85 84 00 + 002db 4c 8d 85 84 00 00 00 lea r8, QWORD PTR ZeroValue$[rbp] - 002ca 8b 95 e4 00 00 + 002e2 8b 95 e4 00 00 00 mov edx, DWORD PTR RipDelta$5[rbp] - 002d0 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 002d4 e8 00 00 00 00 call ?JitEmitRipRelativeMovW@@YAHPEAU_NATIVE_CODE_BLOCK@@HPEAE@Z ; JitEmitRipRelativeMovW - 002d9 85 c0 test eax, eax - 002db 75 4a jne SHORT $LN5@JitEmitPos + 002e8 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 002ec e8 00 00 00 00 call ?JitEmitRipRelativeMovW@@YAHPEAU_NATIVE_CODE_BLOCK@@HPEAE@Z ; JitEmitRipRelativeMovW + 002f1 85 c0 test eax, eax + 002f3 75 4a jne SHORT $LN5@JitEmitPos -; 232 : { -; 233 : NcDeleteBlock(Block); +; 234 : { +; 235 : NcDeleteBlock(Block); - 002dd 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 002e1 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock + 002f5 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 002f9 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 234 : delete Block; +; 236 : delete Block; - 002e6 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 002ea 48 89 85 68 03 + 002fe 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 00302 48 89 85 68 03 00 00 mov QWORD PTR $T12[rbp], rax - 002f1 48 83 bd 68 03 + 00309 48 83 bd 68 03 00 00 00 cmp QWORD PTR $T12[rbp], 0 - 002f9 74 1a je SHORT $LN17@JitEmitPos - 002fb ba 01 00 00 00 mov edx, 1 - 00300 48 8b 8d 68 03 + 00311 74 1a je SHORT $LN17@JitEmitPos + 00313 ba 01 00 00 00 mov edx, 1 + 00318 48 8b 8d 68 03 00 00 mov rcx, QWORD PTR $T12[rbp] - 00307 e8 00 00 00 00 call ??_G_NATIVE_CODE_BLOCK@@QEAAPEAXI@Z - 0030c 48 89 85 b8 03 - 00 00 mov QWORD PTR tv173[rbp], rax - 00313 eb 0b jmp SHORT $LN18@JitEmitPos + 0031f e8 00 00 00 00 call ??_G_NATIVE_CODE_BLOCK@@QEAAPEAXI@Z + 00324 48 89 85 b8 03 + 00 00 mov QWORD PTR tv175[rbp], rax + 0032b eb 0b jmp SHORT $LN18@JitEmitPos $LN17@JitEmitPos: - 00315 48 c7 85 b8 03 + 0032d 48 c7 85 b8 03 00 00 00 00 00 - 00 mov QWORD PTR tv173[rbp], 0 + 00 mov QWORD PTR tv175[rbp], 0 $LN18@JitEmitPos: -; 235 : return NULL; +; 237 : return NULL; - 00320 33 c0 xor eax, eax - 00322 e9 5f 01 00 00 jmp $LN1@JitEmitPos + 00338 33 c0 xor eax, eax + 0033a e9 6b 01 00 00 jmp $LN1@JitEmitPos $LN5@JitEmitPos: -; 236 : } -; 237 : } -; 238 : -; 239 : if (OneByte) +; 238 : } +; 239 : } +; 240 : +; 241 : if (OneByte) - 00327 83 7d 44 00 cmp DWORD PTR OneByte$[rbp], 0 - 0032b 0f 84 dc 00 00 + 0033f 83 7d 44 00 cmp DWORD PTR OneByte$[rbp], 0 + 00343 0f 84 e8 00 00 00 je $LN7@JitEmitPos -; 240 : { -; 241 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4) - (TwoByte * 2); +; 242 : { +; 243 : INT32 RipDelta = Link->RawDataSize - (FourByte * 4) - (TwoByte * 2); - 00331 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] - 00334 c1 e0 02 shl eax, 2 - 00337 48 8b 8d f0 03 + 00349 8b 45 04 mov eax, DWORD PTR FourByte$[rbp] + 0034c c1 e0 02 shl eax, 2 + 0034f 48 8b 8d f0 03 00 00 mov rcx, QWORD PTR Link$[rbp] - 0033e 8b 49 28 mov ecx, DWORD PTR [rcx+40] - 00341 2b c8 sub ecx, eax - 00343 8b c1 mov eax, ecx - 00345 8b 4d 24 mov ecx, DWORD PTR TwoByte$[rbp] - 00348 d1 e1 shl ecx, 1 - 0034a 2b c1 sub eax, ecx - 0034c 89 85 04 01 00 + 00356 8b 49 28 mov ecx, DWORD PTR [rcx+40] + 00359 2b c8 sub ecx, eax + 0035b 8b c1 mov eax, ecx + 0035d 8b 4d 24 mov ecx, DWORD PTR TwoByte$[rbp] + 00360 d1 e1 shl ecx, 1 + 00362 2b c1 sub eax, ecx + 00364 89 85 04 01 00 00 mov DWORD PTR RipDelta$6[rbp], eax -; 242 : RipDelta += (FourByte * DWORD_MOV_INST_LENGTH); +; 244 : RipDelta += (FourByte * DWORD_MOV_INST_LENGTH); - 00352 6b 45 04 0a imul eax, DWORD PTR FourByte$[rbp], 10 - 00356 8b 8d 04 01 00 + 0036a 6b 45 04 0a imul eax, DWORD PTR FourByte$[rbp], 10 + 0036e 8b 8d 04 01 00 00 mov ecx, DWORD PTR RipDelta$6[rbp] - 0035c 03 c8 add ecx, eax - 0035e 8b c1 mov eax, ecx - 00360 89 85 04 01 00 + 00374 03 c8 add ecx, eax + 00376 8b c1 mov eax, ecx + 00378 89 85 04 01 00 00 mov DWORD PTR RipDelta$6[rbp], eax -; 243 : RipDelta += (TwoByte * WORD_MOV_INST_LENGTH); +; 245 : RipDelta += (TwoByte * WORD_MOV_INST_LENGTH); - 00366 6b 45 24 09 imul eax, DWORD PTR TwoByte$[rbp], 9 - 0036a 8b 8d 04 01 00 + 0037e 6b 45 24 09 imul eax, DWORD PTR TwoByte$[rbp], 9 + 00382 8b 8d 04 01 00 00 mov ecx, DWORD PTR RipDelta$6[rbp] - 00370 03 c8 add ecx, eax - 00372 8b c1 mov eax, ecx - 00374 89 85 04 01 00 + 00388 03 c8 add ecx, eax + 0038a 8b c1 mov eax, ecx + 0038c 89 85 04 01 00 00 mov DWORD PTR RipDelta$6[rbp], eax -; 244 : RipDelta += BYTE_MOV_INST_LENGTH; +; 246 : RipDelta += BYTE_MOV_INST_LENGTH; - 0037a 8b 85 04 01 00 + 00392 8b 85 04 01 00 00 mov eax, DWORD PTR RipDelta$6[rbp] - 00380 83 c0 07 add eax, 7 - 00383 89 85 04 01 00 + 00398 83 c0 07 add eax, 7 + 0039b 89 85 04 01 00 00 mov DWORD PTR RipDelta$6[rbp], eax -; 245 : RipDelta *= (-1); +; 247 : RipDelta *= (-1); - 00389 6b 85 04 01 00 + 003a1 6b 85 04 01 00 00 ff imul eax, DWORD PTR RipDelta$6[rbp], -1 - 00390 89 85 04 01 00 + 003a8 89 85 04 01 00 00 mov DWORD PTR RipDelta$6[rbp], eax -; 246 : RipDelta += Delta; +; 248 : RipDelta += Delta; - 00396 8b 85 f8 03 00 + 003ae 8b 85 f8 03 00 00 mov eax, DWORD PTR Delta$[rbp] - 0039c 8b 8d 04 01 00 + 003b4 8b 8d 04 01 00 00 mov ecx, DWORD PTR RipDelta$6[rbp] - 003a2 03 c8 add ecx, eax - 003a4 8b c1 mov eax, ecx - 003a6 89 85 04 01 00 + 003ba 03 c8 add ecx, eax + 003bc 8b c1 mov eax, ecx + 003be 89 85 04 01 00 00 mov DWORD PTR RipDelta$6[rbp], eax -; 247 : if (!JitEmitRipRelativeMovB(Block, RipDelta, (PUCHAR)&ZeroValue)) +; 249 : ZeroValue = rand(); - 003ac 4c 8d 85 84 00 + 003c4 ff 15 00 00 00 + 00 call QWORD PTR __imp_rand + 003ca 89 85 84 00 00 + 00 mov DWORD PTR ZeroValue$[rbp], eax + +; 250 : if (!JitEmitRipRelativeMovB(Block, RipDelta, (PUCHAR)&ZeroValue)) + + 003d0 4c 8d 85 84 00 00 00 lea r8, QWORD PTR ZeroValue$[rbp] - 003b3 8b 95 04 01 00 + 003d7 8b 95 04 01 00 00 mov edx, DWORD PTR RipDelta$6[rbp] - 003b9 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 003bd e8 00 00 00 00 call ?JitEmitRipRelativeMovB@@YAHPEAU_NATIVE_CODE_BLOCK@@HPEAE@Z ; JitEmitRipRelativeMovB - 003c2 85 c0 test eax, eax - 003c4 75 47 jne SHORT $LN7@JitEmitPos + 003dd 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 003e1 e8 00 00 00 00 call ?JitEmitRipRelativeMovB@@YAHPEAU_NATIVE_CODE_BLOCK@@HPEAE@Z ; JitEmitRipRelativeMovB + 003e6 85 c0 test eax, eax + 003e8 75 47 jne SHORT $LN7@JitEmitPos -; 248 : { -; 249 : NcDeleteBlock(Block); +; 251 : { +; 252 : NcDeleteBlock(Block); - 003c6 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 003ca e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock + 003ea 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 003ee e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 250 : delete Block; +; 253 : delete Block; - 003cf 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 003d3 48 89 85 88 03 + 003f3 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 003f7 48 89 85 88 03 00 00 mov QWORD PTR $T13[rbp], rax - 003da 48 83 bd 88 03 + 003fe 48 83 bd 88 03 00 00 00 cmp QWORD PTR $T13[rbp], 0 - 003e2 74 1a je SHORT $LN19@JitEmitPos - 003e4 ba 01 00 00 00 mov edx, 1 - 003e9 48 8b 8d 88 03 + 00406 74 1a je SHORT $LN19@JitEmitPos + 00408 ba 01 00 00 00 mov edx, 1 + 0040d 48 8b 8d 88 03 00 00 mov rcx, QWORD PTR $T13[rbp] - 003f0 e8 00 00 00 00 call ??_G_NATIVE_CODE_BLOCK@@QEAAPEAXI@Z - 003f5 48 89 85 b8 03 - 00 00 mov QWORD PTR tv197[rbp], rax - 003fc eb 0b jmp SHORT $LN20@JitEmitPos + 00414 e8 00 00 00 00 call ??_G_NATIVE_CODE_BLOCK@@QEAAPEAXI@Z + 00419 48 89 85 b8 03 + 00 00 mov QWORD PTR tv200[rbp], rax + 00420 eb 0b jmp SHORT $LN20@JitEmitPos $LN19@JitEmitPos: - 003fe 48 c7 85 b8 03 + 00422 48 c7 85 b8 03 00 00 00 00 00 - 00 mov QWORD PTR tv197[rbp], 0 + 00 mov QWORD PTR tv200[rbp], 0 $LN20@JitEmitPos: -; 251 : return NULL; +; 254 : return NULL; - 00409 33 c0 xor eax, eax - 0040b eb 79 jmp SHORT $LN1@JitEmitPos + 0042d 33 c0 xor eax, eax + 0042f eb 79 jmp SHORT $LN1@JitEmitPos $LN7@JitEmitPos: -; 252 : } -; 253 : } -; 254 : -; 255 : PNATIVE_CODE_LINK StartLink = Block->Start; +; 255 : } +; 256 : } +; 257 : +; 258 : PNATIVE_CODE_LINK StartLink = Block->Start; - 0040d 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 00411 48 8b 00 mov rax, QWORD PTR [rax] - 00414 48 89 85 28 01 + 00431 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 00435 48 8b 00 mov rax, QWORD PTR [rax] + 00438 48 89 85 28 01 00 00 mov QWORD PTR StartLink$[rbp], rax -; 256 : Block->Start = Block->Start->Next; +; 259 : Block->Start = Block->Start->Next; - 0041b 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 0041f 48 8b 00 mov rax, QWORD PTR [rax] - 00422 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] - 00426 48 8b 00 mov rax, QWORD PTR [rax] - 00429 48 89 01 mov QWORD PTR [rcx], rax + 0043f 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 00443 48 8b 00 mov rax, QWORD PTR [rax] + 00446 48 8b 4d 68 mov rcx, QWORD PTR Block$[rbp] + 0044a 48 8b 00 mov rax, QWORD PTR [rax] + 0044d 48 89 01 mov QWORD PTR [rcx], rax -; 257 : if (Block->Start) +; 260 : if (Block->Start) - 0042c 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 00430 48 83 38 00 cmp QWORD PTR [rax], 0 - 00434 74 0f je SHORT $LN9@JitEmitPos + 00450 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 00454 48 83 38 00 cmp QWORD PTR [rax], 0 + 00458 74 0f je SHORT $LN9@JitEmitPos -; 258 : Block->Start->Prev = NULL; +; 261 : Block->Start->Prev = NULL; - 00436 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] - 0043a 48 8b 00 mov rax, QWORD PTR [rax] - 0043d 48 c7 40 08 00 + 0045a 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 0045e 48 8b 00 mov rax, QWORD PTR [rax] + 00461 48 c7 40 08 00 00 00 00 mov QWORD PTR [rax+8], 0 $LN9@JitEmitPos: -; 259 : delete StartLink; +; 262 : delete StartLink; - 00445 48 8b 85 28 01 + 00469 48 8b 85 28 01 00 00 mov rax, QWORD PTR StartLink$[rbp] - 0044c 48 89 85 a8 03 + 00470 48 89 85 a8 03 00 00 mov QWORD PTR $T14[rbp], rax - 00453 48 83 bd a8 03 + 00477 48 83 bd a8 03 00 00 00 cmp QWORD PTR $T14[rbp], 0 - 0045b 74 1a je SHORT $LN21@JitEmitPos - 0045d ba 01 00 00 00 mov edx, 1 - 00462 48 8b 8d a8 03 + 0047f 74 1a je SHORT $LN21@JitEmitPos + 00481 ba 01 00 00 00 mov edx, 1 + 00486 48 8b 8d a8 03 00 00 mov rcx, QWORD PTR $T14[rbp] - 00469 e8 00 00 00 00 call ??_G_NATIVE_CODE_LINK@@QEAAPEAXI@Z - 0046e 48 89 85 b8 03 - 00 00 mov QWORD PTR tv210[rbp], rax - 00475 eb 0b jmp SHORT $LN22@JitEmitPos + 0048d e8 00 00 00 00 call ??_G_NATIVE_CODE_LINK@@QEAAPEAXI@Z + 00492 48 89 85 b8 03 + 00 00 mov QWORD PTR tv213[rbp], rax + 00499 eb 0b jmp SHORT $LN22@JitEmitPos $LN21@JitEmitPos: - 00477 48 c7 85 b8 03 + 0049b 48 c7 85 b8 03 00 00 00 00 00 - 00 mov QWORD PTR tv210[rbp], 0 + 00 mov QWORD PTR tv213[rbp], 0 $LN22@JitEmitPos: -; 260 : -; 261 : return Block; +; 263 : +; 264 : return Block; - 00482 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] + 004a6 48 8b 45 68 mov rax, QWORD PTR Block$[rbp] $LN1@JitEmitPos: -; 262 : } +; 265 : } - 00486 48 8b f8 mov rdi, rax - 00489 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] - 0048d 48 8d 15 00 00 + 004aa 48 8b f8 mov rdi, rax + 004ad 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] + 004b1 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z$rtcFrameData - 00494 e8 00 00 00 00 call _RTC_CheckStackVars - 00499 48 8b c7 mov rax, rdi - 0049c 48 8b 8d c0 03 + 004b8 e8 00 00 00 00 call _RTC_CheckStackVars + 004bd 48 8b c7 mov rax, rdi + 004c0 48 8b 8d c0 03 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] - 004a3 48 33 cd xor rcx, rbp - 004a6 e8 00 00 00 00 call __security_check_cookie - 004ab 48 8d a5 d8 03 + 004c7 48 33 cd xor rcx, rbp + 004ca e8 00 00 00 00 call __security_check_cookie + 004cf 48 8d a5 d8 03 00 00 lea rsp, QWORD PTR [rbp+984] - 004b2 5f pop rdi - 004b3 5d pop rbp - 004b4 c3 ret 0 + 004d6 5f pop rdi + 004d7 5d pop rbp + 004d8 c3 ret 0 ?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z ENDP ; JitEmitPostRipMov _TEXT ENDS ; COMDAT text$x @@ -4111,10 +4133,10 @@ $T11 = 840 $T12 = 872 $T13 = 904 $T14 = 936 -tv210 = 952 -tv197 = 952 -tv173 = 952 -tv152 = 952 +tv213 = 952 +tv200 = 952 +tv175 = 952 +tv153 = 952 tv131 = 952 tv86 = 952 __$ArrayPad$ = 960 @@ -4157,10 +4179,10 @@ $T11 = 840 $T12 = 872 $T13 = 904 $T14 = 936 -tv210 = 952 -tv197 = 952 -tv173 = 952 -tv152 = 952 +tv213 = 952 +tv200 = 952 +tv175 = 952 +tv153 = 952 tv131 = 952 tv86 = 952 __$ArrayPad$ = 960 @@ -4204,10 +4226,10 @@ $T11 = 840 $T12 = 872 $T13 = 904 $T14 = 936 -tv210 = 952 -tv197 = 952 -tv173 = 952 -tv152 = 952 +tv213 = 952 +tv200 = 952 +tv175 = 952 +tv153 = 952 tv131 = 952 tv86 = 952 __$ArrayPad$ = 960 @@ -4251,10 +4273,10 @@ $T11 = 840 $T12 = 872 $T13 = 904 $T14 = 936 -tv210 = 952 -tv197 = 952 -tv173 = 952 -tv152 = 952 +tv213 = 952 +tv200 = 952 +tv175 = 952 +tv153 = 952 tv131 = 952 tv86 = 952 __$ArrayPad$ = 960 diff --git a/CodeVirtualizer/x64/Debug/Main.cod b/CodeVirtualizer/x64/Debug/Main.cod index cfde90d..6f4c015 100644 --- a/CodeVirtualizer/x64/Debug/Main.cod +++ b/CodeVirtualizer/x64/Debug/Main.cod @@ -78,7 +78,6 @@ __BB5B4FF8_xed-encode@h DB 01H __21860875_xed-encoder-hl@h DB 01H __F7815311_xed-decoded-inst-api@h DB 01H __4031338C_Main@cpp DB 01H -__BF2A7ACC_vector DB 01H __7EA464AF_istream DB 01H __1D745195_ostream DB 01H __6FFBAAB7_streambuf DB 01H @@ -87,6 +86,7 @@ __3E6EDFAA_iosfwd DB 01H __CF1C1A3F_utility DB 01H __38038D2D_xstddef DB 01H __EE19A480_xatomic@h DB 01H +__8266A2FD_iomanip DB 01H msvcjmc ENDS _DATA SEGMENT ?TestBuffer@@3PAEA DB 048H ; TestBuffer @@ -152,58 +152,48 @@ PUBLIC __local_stdio_printf_options PUBLIC _vfprintf_l PUBLIC printf PUBLIC wmemcpy -PUBLIC ?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z ; std::_Adjust_manually_vector_aligned -PUBLIC ?_Orphan_all@_Container_base12@std@@QEAAXXZ ; std::_Container_base12::_Orphan_all +PUBLIC ?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z ; std::_Narrow_char_traits::eq_int_type +PUBLIC ?eof@?$_Narrow_char_traits@DH@std@@SAHXZ ; std::_Narrow_char_traits::eof PUBLIC ??$_Maklocstr@_W@std@@YAPEA_WPEBDPEA_WAEBU_Cvtvec@@@Z ; std::_Maklocstr PUBLIC ?_Maklocwcs@std@@YAPEA_WPEB_W@Z ; std::_Maklocwcs PUBLIC ??$_Maklocstr@D@std@@YAPEADPEBDPEADAEBU_Cvtvec@@@Z ; std::_Maklocstr +PUBLIC ?hex@std@@YAAEAVios_base@1@AEAV21@@Z ; std::hex PUBLIC ??$_Getvals@_W@?$time_get@DV?$istreambuf_iterator@DU?$char_traits@D@std@@@std@@@std@@IEAAX_WAEBV_Locinfo@1@@Z ; std::time_get > >::_Getvals PUBLIC ??$_Getvals@_W@?$time_get@_WV?$istreambuf_iterator@_WU?$char_traits@_W@std@@@std@@@std@@IEAAX_WAEBV_Locinfo@1@@Z ; std::time_get > >::_Getvals -PUBLIC ?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z ; std::allocator::deallocate -PUBLIC ??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ ; std::vector >::~vector > -PUBLIC ?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z ; std::vector >::_Destroy -PUBLIC ?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ ; std::vector >::_Tidy -PUBLIC ?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ ; std::vector >::_Getal -PUBLIC ?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ ; std::_Compressed_pair,std::_Vector_val >,1>::_Get_first -PUBLIC ??1_NATIVE_CODE_BLOCK@@QEAA@XZ ; _NATIVE_CODE_BLOCK::~_NATIVE_CODE_BLOCK PUBLIC ?MakeExecutableBuffer@@YAPEAXPEAXK@Z ; MakeExecutableBuffer PUBLIC main -PUBLIC ??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z ; std::allocator::allocator -PUBLIC ??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z ; std::exchange -PUBLIC ??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z ; std::_Delete_plain_internal > -PUBLIC ??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z ; std::_Destroy_range > -PUBLIC ??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z ; std::_Deallocate<16,0> -PUBLIC ??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z ; std::_Deallocate_plain > -PUBLIC ?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z ; std::_Default_allocator_traits >::deallocate +PUBLIC ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z ; std::operator<< > +PUBLIC ??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z ; std::operator<<,__int64> +PUBLIC ??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z ; std::setfill +PUBLIC ??0?$_Fillobj@D@std@@QEAA@D@Z ; std::_Fillobj::_Fillobj +PUBLIC ??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z ; std::operator<<,char> +PUBLIC ??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z ; std::basic_ostream >::_Sentry_base::_Sentry_base +PUBLIC ??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::_Sentry_base::~_Sentry_base +PUBLIC ??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z ; std::basic_ostream >::sentry::sentry +PUBLIC ??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::sentry::~sentry +PUBLIC ??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ ; std::basic_ostream >::sentry::operator bool PUBLIC __JustMyCode_Default PUBLIC ?_OptionsStorage@?1??__local_stdio_printf_options@@9@4_KA ; `__local_stdio_printf_options'::`2'::_OptionsStorage -PUBLIC ?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA ; `std::_Adjust_manually_vector_aligned'::`1'::__LINE__Var -PUBLIC ??_C@_0BB@FCMFBGOM@invalid?5argument@ ; `string' -PUBLIC ??_C@_02DKCKIIND@?$CFs@ ; `string' -PUBLIC ??_C@_0GI@JMEOMKJO@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ ; `string' -PUBLIC ??_C@_1NA@FEEOBALC@?$AAC?$AA?3?$AA?2?$AAP?$AAr?$AAo?$AAg?$AAr?$AAa?$AAm?$AA?5?$AAF?$AAi?$AAl?$AAe@ ; `string' -PUBLIC ??_C@_1EK@NIFDJFDG@?$AAs?$AAt?$AAd?$AA?3?$AA?3?$AA_?$AAA?$AAd?$AAj?$AAu?$AAs?$AAt?$AA_?$AAm?$AAa@ ; `string' -PUBLIC ??_C@_1CG@JNLFBNGN@?$AA?$CC?$AAi?$AAn?$AAv?$AAa?$AAl?$AAi?$AAd?$AA?5?$AAa?$AAr?$AAg?$AAu?$AAm?$AAe@ ; `string' PUBLIC ??_C@_0GI@DEICPIDJ@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ ; `string' PUBLIC ?__LINE__Var@?0??_Maklocwcs@std@@YAPEA_WPEB_W@Z@4JA ; `std::_Maklocwcs'::`1'::__LINE__Var PUBLIC ??_C@_0GI@LHMPPKJI@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ ; `string' -PUBLIC ??_C@_0M@INKCCKOG@?6?6Original?6@ ; `string' -PUBLIC ??_C@_06CHBCCLOP@?6?6New?6@ ; `string' +PUBLIC ??_C@_05PDJBBECF@pause@ ; `string' +PUBLIC ??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ ; `string' PUBLIC ??_C@_0N@LPFKKEBD@?3AM?3am?3PM?3pm@ ; `string' PUBLIC ??_C@_1BK@MHIKGOKE@?$AA?3?$AAA?$AAM?$AA?3?$AAa?$AAm?$AA?3?$AAP?$AAM?$AA?3?$AAp?$AAm@ ; `string' +EXTRN ??2@YAPEAX_K@Z:PROC ; operator new EXTRN ??3@YAXPEAX_K@Z:PROC ; operator delete -EXTRN __imp__invalid_parameter:PROC EXTRN memcpy:PROC EXTRN __imp_wcslen:PROC EXTRN strlen:PROC EXTRN __imp_VirtualAlloc:PROC EXTRN __imp_srand:PROC +EXTRN __imp_rand:PROC +EXTRN __imp_system:PROC EXTRN __imp___acrt_iob_func:PROC EXTRN __imp___stdio_common_vfprintf:PROC EXTRN __imp__calloc_dbg:PROC -EXTRN __imp__CrtDbgReport:PROC -EXTRN __imp_??0_Lockit@std@@QEAA@H@Z:PROC -EXTRN __imp_??1_Lockit@std@@QEAA@XZ:PROC +EXTRN ?uncaught_exception@std@@YA_NXZ:PROC ; std::uncaught_exception EXTRN ?_Xbad_alloc@std@@YAXXZ:PROC ; std::_Xbad_alloc EXTRN _Mbrtowc:PROC EXTRN __imp_?_Getcvt@_Locinfo@std@@QEBA?AU_Cvtvec@@XZ:PROC @@ -211,15 +201,30 @@ EXTRN __imp_?_Getdays@_Locinfo@std@@QEBAPEBDXZ:PROC EXTRN __imp_?_Getmonths@_Locinfo@std@@QEBAPEBDXZ:PROC EXTRN __imp_?_W_Getdays@_Locinfo@std@@QEBAPEBGXZ:PROC EXTRN __imp_?_W_Getmonths@_Locinfo@std@@QEBAPEBGXZ:PROC +EXTRN __imp_?good@ios_base@std@@QEBA_NXZ:PROC +EXTRN __imp_?flags@ios_base@std@@QEBAHXZ:PROC +EXTRN __imp_?setf@ios_base@std@@QEAAHHH@Z:PROC +EXTRN __imp_?width@ios_base@std@@QEBA_JXZ:PROC +EXTRN __imp_?width@ios_base@std@@QEAA_J_J@Z:PROC +EXTRN __imp_?sputc@?$basic_streambuf@DU?$char_traits@D@std@@@std@@QEAAHD@Z:PROC +EXTRN __imp_?setstate@?$basic_ios@DU?$char_traits@D@std@@@std@@QEAAXH_N@Z:PROC +EXTRN __imp_?tie@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_ostream@DU?$char_traits@D@std@@@2@XZ:PROC +EXTRN __imp_?rdbuf@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_streambuf@DU?$char_traits@D@std@@@2@XZ:PROC +EXTRN __imp_?fill@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBADXZ:PROC +EXTRN __imp_?fill@?$basic_ios@DU?$char_traits@D@std@@@std@@QEAADD@Z:PROC +EXTRN __imp_?_Osfx@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAXXZ:PROC +EXTRN __imp_??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAVios_base@1@AEAV21@@Z@Z:PROC +EXTRN __imp_??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z:PROC +EXTRN __imp_?flush@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV12@XZ:PROC EXTRN __imp__time64:PROC +EXTRN ?setw@std@@YA?AU?$_Smanip@_J@1@_J@Z:PROC ; std::setw EXTRN xed_tables_init:PROC -EXTRN ??0_NATIVE_CODE_BLOCK@@QEAA@XZ:PROC ; _NATIVE_CODE_BLOCK::_NATIVE_CODE_BLOCK -EXTRN ?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z:PROC ; NcGenUnusedLabelId -EXTRN ?NcDisassemble@@YAHPEAU_NATIVE_CODE_BLOCK@@PEAXK@Z:PROC ; NcDisassemble -EXTRN ?NcDebugPrint@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z:PROC ; NcDebugPrint -EXTRN ?ObfCreateOpaqueBranches@@YAHPEAU_NATIVE_CODE_LINK@@0PEAU_NATIVE_CODE_BLOCK@@1@Z:PROC ; ObfCreateOpaqueBranches -EXTRN ?ObfCombineOpaqueBranches@@YAHPEAU_NATIVE_CODE_BLOCK@@0KK@Z:PROC ; ObfCombineOpaqueBranches -EXTRN ?ObfInsertOpaqueBranchBlock@@YAHPEAU_NATIVE_CODE_LINK@@0PEAU_NATIVE_CODE_BLOCK@@@Z:PROC ; ObfInsertOpaqueBranchBlock +EXTRN ??0_NATIVE_CODE_LINK@@QEAA@KPEAXKH@Z:PROC ; _NATIVE_CODE_LINK::_NATIVE_CODE_LINK +EXTRN ?NcAppendToBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@@Z:PROC ; NcAppendToBlock +EXTRN ?NcInsertBlockAfter@@YAHPEAU_NATIVE_CODE_LINK@@PEAU_NATIVE_CODE_BLOCK@@H@Z:PROC ; NcInsertBlockAfter +EXTRN ?NcAssemble@@YAPEAXPEAU_NATIVE_CODE_BLOCK@@PEAK@Z:PROC ; NcAssemble +EXTRN ?JitEmitPreRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z:PROC ; JitEmitPreRipMov +EXTRN ?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z:PROC ; JitEmitPostRipMov EXTRN _RTC_CheckStackVars:PROC EXTRN _RTC_InitBase:PROC EXTRN _RTC_Shutdown:PROC @@ -228,6 +233,7 @@ EXTRN __CxxFrameHandler4:PROC EXTRN __GSHandlerCheck:PROC EXTRN __GSHandlerCheck_EH4:PROC EXTRN __security_check_cookie:PROC +EXTRN __imp_?cout@std@@3V?$basic_ostream@DU?$char_traits@D@std@@@1@A:BYTE EXTRN __security_cookie:QWORD ; COMDAT ?_OptionsStorage@?1??__local_stdio_printf_options@@9@4_KA _BSS SEGMENT @@ -283,15 +289,15 @@ $pdata$wmemcpy DD imagerel $LN3 pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z DD imagerel $LN21 - DD imagerel $LN21+476 - DD imagerel $unwind$?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z +$pdata$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z DD imagerel $LN5 + DD imagerel $LN5+118 + DD imagerel $unwind$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?_Orphan_all@_Container_base12@std@@QEAAXXZ DD imagerel $LN7 - DD imagerel $LN7+233 - DD imagerel $unwind$?_Orphan_all@_Container_base12@std@@QEAAXXZ +$pdata$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ DD imagerel $LN3 + DD imagerel $LN3+57 + DD imagerel $unwind$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ pdata ENDS ; COMDAT pdata pdata SEGMENT @@ -313,6 +319,12 @@ $pdata$??$_Maklocstr@D@std@@YAPEADPEBDPEADAEBU_Cvtvec@@@Z DD imagerel $LN7 pdata ENDS ; COMDAT pdata pdata SEGMENT +$pdata$?hex@std@@YAAEAVios_base@1@AEAV21@@Z DD imagerel $LN3 + DD imagerel $LN3+95 + DD imagerel $unwind$?hex@std@@YAAEAVios_base@1@AEAV21@@Z +pdata ENDS +; COMDAT pdata +pdata SEGMENT $pdata$time DD imagerel time DD imagerel time+77 DD imagerel $unwind$time @@ -331,117 +343,105 @@ $pdata$??$_Getvals@_W@?$time_get@_WV?$istreambuf_iterator@_WU?$char_traits@_W@st pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z DD imagerel $LN3 - DD imagerel $LN3+100 - DD imagerel $unwind$?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z -pdata ENDS -; COMDAT pdata -pdata SEGMENT -$pdata$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ DD imagerel $LN3 - DD imagerel $LN3+202 - DD imagerel $unwind$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ -pdata ENDS -; COMDAT pdata -pdata SEGMENT -$pdata$?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z DD imagerel $LN3 - DD imagerel $LN3+108 - DD imagerel $unwind$?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z +$pdata$?MakeExecutableBuffer@@YAPEAXPEAXK@Z DD imagerel $LN4 + DD imagerel $LN4+136 + DD imagerel $unwind$?MakeExecutableBuffer@@YAPEAXPEAXK@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ DD imagerel $LN4 - DD imagerel $LN4+280 - DD imagerel $unwind$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ +$pdata$main DD imagerel $LN19 + DD imagerel $LN19+1068 + DD imagerel $unwind$main pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ DD imagerel $LN3 - DD imagerel $LN3+80 - DD imagerel $unwind$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ +$pdata$main$dtor$0 DD imagerel main$dtor$0 + DD imagerel main$dtor$0+44 + DD imagerel $unwind$main$dtor$0 pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ DD imagerel $LN3 - DD imagerel $LN3+71 - DD imagerel $unwind$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ +$pdata$main$dtor$1 DD imagerel main$dtor$1 + DD imagerel main$dtor$1+44 + DD imagerel $unwind$main$dtor$1 pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??1_NATIVE_CODE_BLOCK@@QEAA@XZ DD imagerel $LN3 - DD imagerel $LN3+71 - DD imagerel $unwind$??1_NATIVE_CODE_BLOCK@@QEAA@XZ +$pdata$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DD imagerel $LN23 + DD imagerel $LN23+1095 + DD imagerel $unwind$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?MakeExecutableBuffer@@YAPEAXPEAXK@Z DD imagerel $LN4 - DD imagerel $LN4+136 - DD imagerel $unwind$?MakeExecutableBuffer@@YAPEAXPEAXK@Z +$pdata$?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA DD imagerel ?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA + DD imagerel ?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA+36 + DD imagerel $unwind$?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$main DD imagerel $LN6 - DD imagerel $LN6+388 - DD imagerel $unwind$main +$pdata$?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA DD imagerel ?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA + DD imagerel ?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA+91 + DD imagerel $unwind$?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$main$dtor$0 DD imagerel main$dtor$0 - DD imagerel main$dtor$0+36 - DD imagerel $unwind$main$dtor$0 +$pdata$??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z DD imagerel $LN3 + DD imagerel $LN3+140 + DD imagerel $unwind$??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$main$dtor$1 DD imagerel main$dtor$1 - DD imagerel main$dtor$1+36 - DD imagerel $unwind$main$dtor$1 +$pdata$??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z DD imagerel $LN3 + DD imagerel $LN3+94 + DD imagerel $unwind$??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$main$dtor$2 DD imagerel main$dtor$2 - DD imagerel main$dtor$2+39 - DD imagerel $unwind$main$dtor$2 +$pdata$??0?$_Fillobj@D@std@@QEAA@D@Z DD imagerel $LN3 + DD imagerel $LN3+91 + DD imagerel $unwind$??0?$_Fillobj@D@std@@QEAA@D@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z DD imagerel $LN3 - DD imagerel $LN3+76 - DD imagerel $unwind$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z +$pdata$??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z DD imagerel $LN3 + DD imagerel $LN3+133 + DD imagerel $unwind$??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z DD imagerel $LN3 - DD imagerel $LN3+107 - DD imagerel $unwind$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z +$pdata$??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DD imagerel $LN4 + DD imagerel $LN4+171 + DD imagerel $unwind$??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DD imagerel $LN3 - DD imagerel $LN3+89 - DD imagerel $unwind$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z +$pdata$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DD imagerel $LN4 + DD imagerel $LN4+143 + DD imagerel $unwind$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z DD imagerel $LN3 - DD imagerel $LN3+75 - DD imagerel $unwind$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z +$pdata$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DD imagerel $LN7 + DD imagerel $LN7+284 + DD imagerel $unwind$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z DD imagerel $LN4 - DD imagerel $LN4+121 - DD imagerel $unwind$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z +$pdata$?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA DD imagerel ?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA + DD imagerel ?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA+39 + DD imagerel $unwind$?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DD imagerel $LN3 - DD imagerel $LN3+95 - DD imagerel $unwind$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z +$pdata$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DD imagerel $LN6 + DD imagerel $LN6+139 + DD imagerel $unwind$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ pdata ENDS ; COMDAT pdata pdata SEGMENT -$pdata$?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z DD imagerel $LN3 - DD imagerel $LN3+97 - DD imagerel $unwind$?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z +$pdata$??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ DD imagerel $LN3 + DD imagerel $LN3+75 + DD imagerel $unwind$??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ pdata ENDS ; COMDAT rtc$TMZ rtc$TMZ SEGMENT @@ -461,13 +461,14 @@ CONST ENDS CONST SEGMENT ??_C@_0N@LPFKKEBD@?3AM?3am?3PM?3pm@ DB ':AM:am:PM:pm', 00H ; `string' CONST ENDS -; COMDAT ??_C@_06CHBCCLOP@?6?6New?6@ +; COMDAT ??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ CONST SEGMENT -??_C@_06CHBCCLOP@?6?6New?6@ DB 0aH, 0aH, 'New', 0aH, 00H ; `string' +??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ DB 'The numba was: %X', 0aH + DB 00H ; `string' CONST ENDS -; COMDAT ??_C@_0M@INKCCKOG@?6?6Original?6@ +; COMDAT ??_C@_05PDJBBECF@pause@ CONST SEGMENT -??_C@_0M@INKCCKOG@?6?6Original?6@ DB 0aH, 0aH, 'Original', 0aH, 00H ; `string' +??_C@_05PDJBBECF@pause@ DB 'pause', 00H ; `string' CONST ENDS ; COMDAT ??_C@_0GI@LHMPPKJI@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ CONST SEGMENT @@ -485,413 +486,280 @@ CONST SEGMENT DB 'gram Files (x86)\Microsoft Visual Studio\2019\Community\VC\To' DB 'ols\MSVC\14.27.29110\include\xlocale', 00H ; `string' CONST ENDS -; COMDAT ??_C@_1CG@JNLFBNGN@?$AA?$CC?$AAi?$AAn?$AAv?$AAa?$AAl?$AAi?$AAd?$AA?5?$AAa?$AAr?$AAg?$AAu?$AAm?$AAe@ -CONST SEGMENT -??_C@_1CG@JNLFBNGN@?$AA?$CC?$AAi?$AAn?$AAv?$AAa?$AAl?$AAi?$AAd?$AA?5?$AAa?$AAr?$AAg?$AAu?$AAm?$AAe@ DB '"' - DB 00H, 'i', 00H, 'n', 00H, 'v', 00H, 'a', 00H, 'l', 00H, 'i', 00H - DB 'd', 00H, ' ', 00H, 'a', 00H, 'r', 00H, 'g', 00H, 'u', 00H, 'm' - DB 00H, 'e', 00H, 'n', 00H, 't', 00H, '"', 00H, 00H, 00H ; `string' -CONST ENDS -; COMDAT ??_C@_1EK@NIFDJFDG@?$AAs?$AAt?$AAd?$AA?3?$AA?3?$AA_?$AAA?$AAd?$AAj?$AAu?$AAs?$AAt?$AA_?$AAm?$AAa@ -CONST SEGMENT -??_C@_1EK@NIFDJFDG@?$AAs?$AAt?$AAd?$AA?3?$AA?3?$AA_?$AAA?$AAd?$AAj?$AAu?$AAs?$AAt?$AA_?$AAm?$AAa@ DB 's' - DB 00H, 't', 00H, 'd', 00H, ':', 00H, ':', 00H, '_', 00H, 'A', 00H - DB 'd', 00H, 'j', 00H, 'u', 00H, 's', 00H, 't', 00H, '_', 00H, 'm' - DB 00H, 'a', 00H, 'n', 00H, 'u', 00H, 'a', 00H, 'l', 00H, 'l', 00H - DB 'y', 00H, '_', 00H, 'v', 00H, 'e', 00H, 'c', 00H, 't', 00H, 'o' - DB 00H, 'r', 00H, '_', 00H, 'a', 00H, 'l', 00H, 'i', 00H, 'g', 00H - DB 'n', 00H, 'e', 00H, 'd', 00H, 00H, 00H ; `string' -CONST ENDS -; COMDAT ??_C@_1NA@FEEOBALC@?$AAC?$AA?3?$AA?2?$AAP?$AAr?$AAo?$AAg?$AAr?$AAa?$AAm?$AA?5?$AAF?$AAi?$AAl?$AAe@ -CONST SEGMENT -??_C@_1NA@FEEOBALC@?$AAC?$AA?3?$AA?2?$AAP?$AAr?$AAo?$AAg?$AAr?$AAa?$AAm?$AA?5?$AAF?$AAi?$AAl?$AAe@ DB 'C' - DB 00H, ':', 00H, '\', 00H, 'P', 00H, 'r', 00H, 'o', 00H, 'g', 00H - DB 'r', 00H, 'a', 00H, 'm', 00H, ' ', 00H, 'F', 00H, 'i', 00H, 'l' - DB 00H, 'e', 00H, 's', 00H, ' ', 00H, '(', 00H, 'x', 00H, '8', 00H - DB '6', 00H, ')', 00H, '\', 00H, 'M', 00H, 'i', 00H, 'c', 00H, 'r' - DB 00H, 'o', 00H, 's', 00H, 'o', 00H, 'f', 00H, 't', 00H, ' ', 00H - DB 'V', 00H, 'i', 00H, 's', 00H, 'u', 00H, 'a', 00H, 'l', 00H, ' ' - DB 00H, 'S', 00H, 't', 00H, 'u', 00H, 'd', 00H, 'i', 00H, 'o', 00H - DB '\', 00H, '2', 00H, '0', 00H, '1', 00H, '9', 00H, '\', 00H, 'C' - DB 00H, 'o', 00H, 'm', 00H, 'm', 00H, 'u', 00H, 'n', 00H, 'i', 00H - DB 't', 00H, 'y', 00H, '\', 00H, 'V', 00H, 'C', 00H, '\', 00H, 'T' - DB 00H, 'o', 00H, 'o', 00H, 'l', 00H, 's', 00H, '\', 00H, 'M', 00H - DB 'S', 00H, 'V', 00H, 'C', 00H, '\', 00H, '1', 00H, '4', 00H, '.' - DB 00H, '2', 00H, '7', 00H, '.', 00H, '2', 00H, '9', 00H, '1', 00H - DB '1', 00H, '0', 00H, '\', 00H, 'i', 00H, 'n', 00H, 'c', 00H, 'l' - DB 00H, 'u', 00H, 'd', 00H, 'e', 00H, '\', 00H, 'x', 00H, 'm', 00H - DB 'e', 00H, 'm', 00H, 'o', 00H, 'r', 00H, 'y', 00H, 00H, 00H ; `string' -CONST ENDS -; COMDAT ??_C@_0GI@JMEOMKJO@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ -CONST SEGMENT -??_C@_0GI@JMEOMKJO@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ DB 'C:\Pro' - DB 'gram Files (x86)\Microsoft Visual Studio\2019\Community\VC\To' - DB 'ols\MSVC\14.27.29110\include\xmemory', 00H ; `string' -CONST ENDS -; COMDAT ??_C@_02DKCKIIND@?$CFs@ -CONST SEGMENT -??_C@_02DKCKIIND@?$CFs@ DB '%s', 00H ; `string' -CONST ENDS -; COMDAT ??_C@_0BB@FCMFBGOM@invalid?5argument@ -CONST SEGMENT -??_C@_0BB@FCMFBGOM@invalid?5argument@ DB 'invalid argument', 00H ; `string' -CONST ENDS -; COMDAT ?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA -_DATA SEGMENT -?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA DD 084H ; `std::_Adjust_manually_vector_aligned'::`1'::__LINE__Var -_DATA ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z DD 025053401H - DD 0118231dH - DD 07011001dH - DD 05010H +$unwind$??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ DD 025052a01H + DD 010e2313H + DD 07007001dH + DD 05006H xdata ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DB 02H +$ip2state$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DB 02H DB 00H DB 00H xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DB 060H - DD imagerel $ip2state$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z +$cppxdata$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DB 060H + DD imagerel $ip2state$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DD 025052f19H - DD 01132318H - DD 0700c001dH - DD 0500bH +$unwind$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DD 025052a19H + DD 010e2313H + DD 070070021H + DD 05006H DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$ip2state$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z DB 02H - DB 00H - DB 00H + DD imagerel $cppxdata$??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z DB 060H - DD imagerel $ip2state$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$unwind$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z DD 025052f19H - DD 01132318H - DD 0700c001dH +$unwind$?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA DD 031001H + DD 0700c4210H DD 0500bH - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z xdata ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z DB 02H +$ip2state$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DB 06H DB 00H DB 00H + DB 09eH + DB 02H + DB 0f1H, 02H + DB 00H xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z DB 060H - DD imagerel $ip2state$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$unwind$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z DD 025053419H - DD 0118231dH - DD 07011001dH - DD 05010H - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$ip2state$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DB 02H - DB 00H - DB 00H +$stateUnwindMap$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DB 02H + DB 0eH + DD imagerel ?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DB 060H - DD imagerel $ip2state$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z +$cppxdata$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DB 028H + DD imagerel $stateUnwindMap$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z + DD imagerel $ip2state$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z DD 025052f19H +$unwind$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DD 025052f11H DD 01132318H - DD 0700c001dH + DD 0700c0021H DD 0500bH DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z + DD imagerel $cppxdata$??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z xdata ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z DB 02H +$ip2state$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DB 02H DB 00H DB 00H xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z DB 060H - DD imagerel $ip2state$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z +$cppxdata$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DB 060H + DD imagerel $ip2state$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ +xdata ENDS +; COMDAT xdata +xdata SEGMENT +$unwind$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ DD 025052a19H + DD 010e2313H + DD 070070021H + DD 05006H + DD imagerel __CxxFrameHandler4 + DD imagerel $cppxdata$??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z DD 025052f19H +$unwind$??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z DD 025052f01H DD 01132318H DD 0700c0021H DD 0500bH - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z xdata ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z DB 02H - DB 00H - DB 00H +$unwind$??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z DD 025052f01H + DD 01132318H + DD 0700c001fH + DD 0500bH xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z DB 060H - DD imagerel $ip2state$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z +$unwind$??0?$_Fillobj@D@std@@QEAA@D@Z DD 025052e01H + DD 01122317H + DD 0700b001dH + DD 0500aH xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z DD 025052f19H - DD 01132318H - DD 0700c001dH - DD 0500bH - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z +$unwind$??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z DD 025052e01H + DD 01122317H + DD 0700b001dH + DD 0500aH xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$main$dtor$2 DD 031001H - DD 0700c4210H +$unwind$??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z DD 025052f01H + DD 01132318H + DD 0700c001fH DD 0500bH xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$main$dtor$1 DD 031001H +$unwind$?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA DD 031001H DD 0700c4210H DD 0500bH xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$main$dtor$0 DD 031001H +$unwind$?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA DD 031001H DD 0700c4210H DD 0500bH xdata ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$main DB 0eH +$ip2state$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DB 0aH DB 00H DB 00H - DB 0b2H + DB 0c6H DB 02H - DB 'B' - DB 04H - DB 01aH - DB 06H - DB 0b9H, 02H + DB 011H, 02H DB 04H - DB 01aH + DB 0adH, 0aH DB 02H - DB 014H + DB 0ecH DB 00H xdata ENDS ; COMDAT xdata xdata SEGMENT -$stateUnwindMap$main DB 06H +$handlerMap$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DB 02H + DB 01H + DB 080H + DD imagerel ?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA +xdata ENDS +; COMDAT xdata +xdata SEGMENT +$tryMap$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DB 02H + DB 02H + DB 02H + DB 04H + DD imagerel $handlerMap$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z +xdata ENDS +; COMDAT xdata +xdata SEGMENT +$stateUnwindMap$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DB 06H DB 0eH - DD imagerel main$dtor$0 - DB 02eH - DD imagerel main$dtor$1 - DB 02eH - DD imagerel main$dtor$2 + DD imagerel ?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA + DB 028H + DB 030H xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$main DB 028H - DD imagerel $stateUnwindMap$main - DD imagerel $ip2state$main +$cppxdata$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DB 038H + DD imagerel $stateUnwindMap$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z + DD imagerel $tryMap$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z + DD imagerel $ip2state$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$main DD 025052f19H - DD 010a230fH - DD 07003003dH - DD 05002H +$unwind$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z DD 025053f19H + DD 01122317H + DD 0700b004bH + DD 0500aH DD imagerel __GSHandlerCheck_EH4 - DD imagerel $cppxdata$main - DD 01d2H + DD imagerel $cppxdata$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z + DD 0243H xdata ENDS ; COMDAT CONST CONST SEGMENT -main$rtcName$0 DB 042H - DB 06cH - DB 06fH - DB 063H - DB 06bH - DB 00H - ORG $+2 -main$rtcName$1 DB 04eH - DB 06fH - DB 074H - DB 054H - DB 061H - DB 06bH - DB 065H - DB 06eH - DB 00H - ORG $+3 -main$rtcName$2 DB 054H - DB 061H +??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$rtcName$0 DB 05fH ; std::operator<< > + DB 04fH DB 06bH - DB 065H - DB 06eH DB 00H - ORG $+6 -main$rtcVarDesc DD 0c8H - DD 030H - DQ FLAT:main$rtcName$2 - DD 078H - DD 030H - DQ FLAT:main$rtcName$1 - DD 028H - DD 030H - DQ FLAT:main$rtcName$0 - ORG $+144 -main$rtcFrameData DD 03H + ORG $+12 +??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$rtcVarDesc DD 048H ; std::operator<< > + DD 010H + DQ FLAT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$rtcName$0 + ORG $+48 +??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$rtcFrameData DD 01H ; std::operator<< > DD 00H - DQ FLAT:main$rtcVarDesc + DQ FLAT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$rtcVarDesc CONST ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?MakeExecutableBuffer@@YAPEAXPEAXK@Z DD 025052e01H - DD 01122317H - DD 0700b0021H - DD 0500aH -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$unwind$??1_NATIVE_CODE_BLOCK@@QEAA@XZ DD 025052a01H - DD 010e2313H - DD 07007001dH - DD 05006H -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$ip2state$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ DB 02H - DB 00H - DB 00H -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$cppxdata$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ DB 060H - DD imagerel $ip2state$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ +$unwind$main$dtor$1 DD 031001H + DD 0700c4210H + DD 0500bH xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ DD 025052a19H - DD 010e2313H - DD 07007001dH - DD 05006H - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ +$unwind$main$dtor$0 DD 031001H + DD 0700c4210H + DD 0500bH xdata ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ DB 02H +$ip2state$main DB 0aH DB 00H DB 00H -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$cppxdata$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ DB 060H - DD imagerel $ip2state$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$unwind$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ DD 025052a19H - DD 010e2313H - DD 07007001dH - DD 05006H - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$ip2state$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ DB 02H + DB 0c0H + DB 02H + DB 0a4H DB 00H + DB '8' + DB 04H + DB 0a4H DB 00H xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ DB 060H - DD imagerel $ip2state$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$unwind$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ DD 025052a19H - DD 010e2313H - DD 07007002fH - DD 05006H - DD imagerel __CxxFrameHandler4 - DD imagerel $cppxdata$?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$unwind$?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z DD 025053401H - DD 0118231dH - DD 07011001dH - DD 05010H -xdata ENDS -; COMDAT xdata -xdata SEGMENT -$ip2state$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ DB 02H - DB 00H - DB 00H +$stateUnwindMap$main DB 04H + DB 0eH + DD imagerel main$dtor$0 + DB 036H + DD imagerel main$dtor$1 xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ DB 060H - DD imagerel $ip2state$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ +$cppxdata$main DB 028H + DD imagerel $stateUnwindMap$main + DD imagerel $ip2state$main xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ DD 025053b19H - DD 010e2313H - DD 070070029H - DD 05006H +$unwind$main DD 035052f19H + DD 010a330fH + DD 07003008bH + DD 05002H DD imagerel __GSHandlerCheck_EH4 - DD imagerel $cppxdata$??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ - DD 013bH + DD imagerel $cppxdata$main + DD 044aH xdata ENDS ; COMDAT CONST CONST SEGMENT -??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ$rtcName$0 DB 024H ; std::vector >::~vector > - DB 053H - DB 031H +main$rtcName$0 DB 041H + DB 073H + DB 06dH + DB 04cH + DB 065H + DB 06eH DB 00H - ORG $+12 -??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ$rtcVarDesc DD 044H ; std::vector >::~vector > - DD 01H - DQ FLAT:??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ$rtcName$0 + ORG $+9 +main$rtcVarDesc DD 0134H + DD 04H + DQ FLAT:main$rtcName$0 ORG $+48 -??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ$rtcFrameData DD 01H ; std::vector >::~vector > +main$rtcFrameData DD 01H DD 00H - DQ FLAT:??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ$rtcVarDesc + DQ FLAT:main$rtcVarDesc CONST ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z DD 025053401H - DD 0118231dH - DD 07011001dH - DD 05010H +$unwind$?MakeExecutableBuffer@@YAPEAXPEAXK@Z DD 025052e01H + DD 01122317H + DD 0700b0021H + DD 0500aH xdata ENDS ; COMDAT xdata xdata SEGMENT @@ -916,6 +784,13 @@ $unwind$time DD 025052a01H xdata ENDS ; COMDAT xdata xdata SEGMENT +$unwind$?hex@std@@YAAEAVios_base@1@AEAV21@@Z DD 025052a01H + DD 010e2313H + DD 07007001dH + DD 05006H +xdata ENDS +; COMDAT xdata +xdata SEGMENT $unwind$??$_Maklocstr@D@std@@YAPEADPEBDPEADAEBU_Cvtvec@@@Z DD 035053401H DD 0118331dH DD 07011002bH @@ -975,48 +850,43 @@ CONST SEGMENT CONST ENDS ; COMDAT xdata xdata SEGMENT -$ip2state$?_Orphan_all@_Container_base12@std@@QEAAXXZ DB 02H +$ip2state$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ DB 02H DB 00H DB 00H xdata ENDS ; COMDAT xdata xdata SEGMENT -$cppxdata$?_Orphan_all@_Container_base12@std@@QEAAXXZ DB 060H - DD imagerel $ip2state$?_Orphan_all@_Container_base12@std@@QEAAXXZ +$cppxdata$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ DB 060H + DD imagerel $ip2state$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?_Orphan_all@_Container_base12@std@@QEAAXXZ DD 025053b19H - DD 010e2313H - DD 070070025H - DD 05006H - DD imagerel __GSHandlerCheck_EH4 - DD imagerel $cppxdata$?_Orphan_all@_Container_base12@std@@QEAAXXZ - DD 011bH +$unwind$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ DD 025051e19H + DD 010a230fH + DD 07003001dH + DD 05002H + DD imagerel __CxxFrameHandler4 + DD imagerel $cppxdata$?eof@?$_Narrow_char_traits@DH@std@@SAHXZ xdata ENDS -; COMDAT CONST -CONST SEGMENT -?_Orphan_all@_Container_base12@std@@QEAAXXZ$rtcName$0 DB 05fH ; std::_Container_base12::_Orphan_all - DB 04cH - DB 06fH - DB 063H - DB 06bH - DB 00H - ORG $+10 -?_Orphan_all@_Container_base12@std@@QEAAXXZ$rtcVarDesc DD 024H ; std::_Container_base12::_Orphan_all - DD 04H - DQ FLAT:?_Orphan_all@_Container_base12@std@@QEAAXXZ$rtcName$0 - ORG $+48 -?_Orphan_all@_Container_base12@std@@QEAAXXZ$rtcFrameData DD 01H ; std::_Container_base12::_Orphan_all - DD 00H - DQ FLAT:?_Orphan_all@_Container_base12@std@@QEAAXXZ$rtcVarDesc -CONST ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z DD 035052f01H - DD 01133318H - DD 0700c002fH - DD 0500bH +$ip2state$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z DB 02H + DB 00H + DB 00H +xdata ENDS +; COMDAT xdata +xdata SEGMENT +$cppxdata$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z DB 060H + DD imagerel $ip2state$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z +xdata ENDS +; COMDAT xdata +xdata SEGMENT +$unwind$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z DD 025052f19H + DD 01132318H + DD 0700c001fH + DD 0500bH + DD imagerel __CxxFrameHandler4 + DD imagerel $cppxdata$?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z xdata ENDS ; COMDAT xdata xdata SEGMENT @@ -1156,1297 +1026,2185 @@ __JustMyCode_Default PROC ; COMDAT __JustMyCode_Default ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ostream +; COMDAT ??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ _TEXT SEGMENT -__formal$ = 224 -_Ptr$ = 232 -_Count$ = 240 -?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z PROC ; std::_Default_allocator_traits >::deallocate, COMDAT +this$ = 224 +??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ PROC ; std::basic_ostream >::sentry::operator bool, COMDAT -; 687 : static void deallocate(_Alloc&, const pointer _Ptr, const size_type _Count) { +; 125 : explicit __CLR_OR_THIS_CALL operator bool() const { $LN3: - 00000 4c 89 44 24 18 mov QWORD PTR [rsp+24], r8 - 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 0000a 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 0000f 55 push rbp - 00010 57 push rdi - 00011 48 81 ec e8 00 + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 55 push rbp + 00006 57 push rdi + 00007 48 81 ec e8 00 00 00 sub rsp, 232 ; 000000e8H - 00018 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 0001d 48 8b fc mov rdi, rsp - 00020 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 00025 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 0002a f3 ab rep stosd - 0002c 48 8b 8c 24 08 + 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00013 48 8b fc mov rdi, rsp + 00016 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00020 f3 ab rep stosd + 00022 48 8b 8c 24 08 01 00 00 mov rcx, QWORD PTR [rsp+264] - 00034 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode + 0002a 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__1D745195_ostream + 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 688 : // no overflow check on the following multiply; we assume _Allocate did that check -; 689 : _Deallocate<_New_alignof>(_Ptr, sizeof(value_type) * _Count); +; 126 : return _Ok; - 00040 48 6b 85 f0 00 - 00 00 10 imul rax, QWORD PTR _Count$[rbp], 16 - 00048 48 8b d0 mov rdx, rax - 0004b 48 8b 8d e8 00 - 00 00 mov rcx, QWORD PTR _Ptr$[rbp] - 00052 e8 00 00 00 00 call ??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z ; std::_Deallocate<16,0> + 00036 48 8b 85 e0 00 + 00 00 mov rax, QWORD PTR this$[rbp] + 0003d 0f b6 40 08 movzx eax, BYTE PTR [rax+8] -; 690 : } +; 127 : } - 00057 48 8d a5 c8 00 + 00041 48 8d a5 c8 00 00 00 lea rsp, QWORD PTR [rbp+200] - 0005e 5f pop rdi - 0005f 5d pop rbp - 00060 c3 ret 0 -?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z ENDP ; std::_Default_allocator_traits >::deallocate + 00048 5f pop rdi + 00049 5d pop rbp + 0004a c3 ret 0 +??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ ENDP ; std::basic_ostream >::sentry::operator bool _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ostream +; COMDAT ??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ _TEXT SEGMENT -_Al$ = 224 -_Ptr$ = 232 -??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z PROC ; std::_Deallocate_plain >, COMDAT +_Zero_uncaught_exceptions$ = 4 +tv72 = 212 +this$ = 256 +??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ PROC ; std::basic_ostream >::sentry::~sentry, COMDAT -; 998 : void _Deallocate_plain(_Alloc& _Al, typename _Alloc::value_type* const _Ptr) noexcept { +; 110 : __CLR_OR_THIS_CALL ~sentry() noexcept { -$LN3: - 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 0000a 55 push rbp - 0000b 57 push rdi - 0000c 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00018 48 8b fc mov rdi, rsp - 0001b b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00025 f3 ab rep stosd - 00027 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode +$LN6: + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 55 push rbp + 00006 57 push rdi + 00007 48 81 ec 08 01 + 00 00 sub rsp, 264 ; 00000108H + 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00013 48 8b fc mov rdi, rsp + 00016 b9 42 00 00 00 mov ecx, 66 ; 00000042H + 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00020 f3 ab rep stosd + 00022 48 8b 8c 24 28 + 01 00 00 mov rcx, QWORD PTR [rsp+296] + 0002a 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__1D745195_ostream + 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 999 : // deallocate a plain pointer using an allocator -; 1000 : using _Alloc_traits = allocator_traits<_Alloc>; -; 1001 : if constexpr (is_same_v<_Alloc_ptr_t<_Alloc>, typename _Alloc::value_type*>) { -; 1002 : _Alloc_traits::deallocate(_Al, _Ptr, 1); +; 111 : #if !_HAS_EXCEPTIONS +; 112 : const bool _Zero_uncaught_exceptions = true; +; 113 : #elif _HAS_DEPRECATED_UNCAUGHT_EXCEPTION +; 114 : const bool _Zero_uncaught_exceptions = !_STD uncaught_exception(); // TRANSITION, ArchivedOS-12000909 + + 00036 e8 00 00 00 00 call ?uncaught_exception@std@@YA_NXZ ; std::uncaught_exception + 0003b 0f b6 c0 movzx eax, al + 0003e 85 c0 test eax, eax + 00040 75 09 jne SHORT $LN4@sentry + 00042 c6 85 d4 00 00 + 00 01 mov BYTE PTR tv72[rbp], 1 + 00049 eb 07 jmp SHORT $LN5@sentry +$LN4@sentry: + 0004b c6 85 d4 00 00 + 00 00 mov BYTE PTR tv72[rbp], 0 +$LN5@sentry: + 00052 0f b6 85 d4 00 + 00 00 movzx eax, BYTE PTR tv72[rbp] + 00059 88 45 04 mov BYTE PTR _Zero_uncaught_exceptions$[rbp], al + +; 115 : #else // ^^^ _HAS_DEPRECATED_UNCAUGHT_EXCEPTION / !_HAS_DEPRECATED_UNCAUGHT_EXCEPTION vvv +; 116 : const bool _Zero_uncaught_exceptions = _STD uncaught_exceptions() == 0; +; 117 : #endif // !_HAS_DEPRECATED_UNCAUGHT_EXCEPTION +; 118 : +; 119 : if (_Zero_uncaught_exceptions) { - 0003b 41 b8 01 00 00 - 00 mov r8d, 1 - 00041 48 8b 95 e8 00 - 00 00 mov rdx, QWORD PTR _Ptr$[rbp] - 00048 48 8b 8d e0 00 - 00 00 mov rcx, QWORD PTR _Al$[rbp] - 0004f e8 00 00 00 00 call ?deallocate@?$_Default_allocator_traits@V?$allocator@U_Container_proxy@std@@@std@@@std@@SAXAEAV?$allocator@U_Container_proxy@std@@@2@QEAU_Container_proxy@2@_K@Z ; std::_Default_allocator_traits >::deallocate - 00054 90 npad 1 + 0005c 0f b6 45 04 movzx eax, BYTE PTR _Zero_uncaught_exceptions$[rbp] + 00060 85 c0 test eax, eax + 00062 74 10 je SHORT $LN2@sentry -; 1003 : } else { -; 1004 : using _Ptr_traits = pointer_traits<_Alloc_ptr_t<_Alloc>>; -; 1005 : _Alloc_traits::deallocate(_Al, _Ptr_traits::pointer_to(*_Ptr), 1); -; 1006 : } -; 1007 : } +; 120 : this->_Myostr._Osfx(); - 00055 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 0005c 5f pop rdi - 0005d 5d pop rbp - 0005e c3 ret 0 -??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z ENDP ; std::_Deallocate_plain > + 00064 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 0006b 48 8b 08 mov rcx, QWORD PTR [rax] + 0006e ff 15 00 00 00 + 00 call QWORD PTR __imp_?_Osfx@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAXXZ +$LN2@sentry: + +; 121 : } +; 122 : } + + 00074 48 8b 8d 00 01 + 00 00 mov rcx, QWORD PTR this$[rbp] + 0007b e8 00 00 00 00 call ??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::_Sentry_base::~_Sentry_base + 00080 90 npad 1 + 00081 48 8d a5 e8 00 + 00 00 lea rsp, QWORD PTR [rbp+232] + 00088 5f pop rdi + 00089 5d pop rbp + 0008a c3 ret 0 +??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ENDP ; std::basic_ostream >::sentry::~sentry _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ostream +; COMDAT ??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z _TEXT SEGMENT -_Ptr$ = 224 -_Bytes$ = 232 -??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z PROC ; std::_Deallocate<16,0>, COMDAT +_Tied$ = 8 +this$ = 256 +_Ostr$ = 264 +??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z PROC ; std::basic_ostream >::sentry::sentry, COMDAT -; 213 : void _Deallocate(void* _Ptr, size_t _Bytes) noexcept { +; 92 : explicit __CLR_OR_THIS_CALL sentry(basic_ostream& _Ostr) : _Sentry_base(_Ostr) { -$LN4: +$LN7: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 0000a 55 push rbp 0000b 57 push rdi - 0000c 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H + 0000c 48 81 ec 08 01 + 00 00 sub rsp, 264 ; 00000108H 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00018 48 8b fc mov rdi, rsp - 0001b b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 0001b b9 42 00 00 00 mov ecx, 66 ; 00000042H 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 00025 f3 ab rep stosd - 00027 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] + 00027 48 8b 8c 24 28 + 01 00 00 mov rcx, QWORD PTR [rsp+296] 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory + 00 00 lea rcx, OFFSET FLAT:__1D745195_ostream 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + 0003b 48 8b 95 08 01 + 00 00 mov rdx, QWORD PTR _Ostr$[rbp] + 00042 48 8b 8d 00 01 + 00 00 mov rcx, QWORD PTR this$[rbp] + 00049 e8 00 00 00 00 call ??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z ; std::basic_ostream >::_Sentry_base::_Sentry_base + 0004e 90 npad 1 -; 214 : // deallocate storage allocated by _Allocate when !_HAS_ALIGNED_NEW || _Align <= __STDCPP_DEFAULT_NEW_ALIGNMENT__ -; 215 : #if defined(_M_IX86) || defined(_M_X64) -; 216 : if (_Bytes >= _Big_allocation_threshold) { // boost the alignment of big allocations to help autovectorization +; 93 : if (!_Ostr.good()) { + + 0004f 48 8b 85 08 01 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00056 48 8b 00 mov rax, QWORD PTR [rax] + 00059 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 0005d 48 8b 8d 08 01 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00064 48 03 c8 add rcx, rax + 00067 48 8b c1 mov rax, rcx + 0006a 48 8b c8 mov rcx, rax + 0006d ff 15 00 00 00 + 00 call QWORD PTR __imp_?good@ios_base@std@@QEBA_NXZ + 00073 0f b6 c0 movzx eax, al + 00076 85 c0 test eax, eax + 00078 75 10 jne SHORT $LN2@sentry + +; 94 : _Ok = false; - 0003b 48 81 bd e8 00 - 00 00 00 10 00 - 00 cmp QWORD PTR _Bytes$[rbp], 4096 ; 00001000H - 00046 72 13 jb SHORT $LN2@Deallocate + 0007a 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 00081 c6 40 08 00 mov BYTE PTR [rax+8], 0 -; 217 : _Adjust_manually_vector_aligned(_Ptr, _Bytes); +; 95 : return; - 00048 48 8d 95 e8 00 - 00 00 lea rdx, QWORD PTR _Bytes$[rbp] - 0004f 48 8d 8d e0 00 - 00 00 lea rcx, QWORD PTR _Ptr$[rbp] - 00056 e8 00 00 00 00 call ?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z ; std::_Adjust_manually_vector_aligned -$LN2@Deallocate: + 00085 e9 81 00 00 00 jmp $LN1@sentry +$LN2@sentry: -; 218 : } -; 219 : #endif // defined(_M_IX86) || defined(_M_X64) -; 220 : -; 221 : ::operator delete(_Ptr, _Bytes); +; 96 : } +; 97 : +; 98 : const auto _Tied = _Ostr.tie(); - 0005b 48 8b 95 e8 00 - 00 00 mov rdx, QWORD PTR _Bytes$[rbp] - 00062 48 8b 8d e0 00 - 00 00 mov rcx, QWORD PTR _Ptr$[rbp] - 00069 e8 00 00 00 00 call ??3@YAXPEAX_K@Z ; operator delete - 0006e 90 npad 1 + 0008a 48 8b 85 08 01 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00091 48 8b 00 mov rax, QWORD PTR [rax] + 00094 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00098 48 8b 8d 08 01 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 0009f 48 03 c8 add rcx, rax + 000a2 48 8b c1 mov rax, rcx + 000a5 48 8b c8 mov rcx, rax + 000a8 ff 15 00 00 00 + 00 call QWORD PTR __imp_?tie@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_ostream@DU?$char_traits@D@std@@@2@XZ + 000ae 48 89 45 08 mov QWORD PTR _Tied$[rbp], rax -; 222 : } +; 99 : if (!_Tied || _Tied == &_Ostr) { - 0006f 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00076 5f pop rdi - 00077 5d pop rbp - 00078 c3 ret 0 -??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z ENDP ; std::_Deallocate<16,0> + 000b2 48 83 7d 08 00 cmp QWORD PTR _Tied$[rbp], 0 + 000b7 74 0d je SHORT $LN4@sentry + 000b9 48 8b 85 08 01 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 000c0 48 39 45 08 cmp QWORD PTR _Tied$[rbp], rax + 000c4 75 0d jne SHORT $LN3@sentry +$LN4@sentry: + +; 100 : _Ok = true; + + 000c6 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 000cd c6 40 08 01 mov BYTE PTR [rax+8], 1 + +; 101 : return; + + 000d1 eb 38 jmp SHORT $LN1@sentry +$LN3@sentry: + +; 102 : } +; 103 : +; 104 : +; 105 : _Tied->flush(); + + 000d3 48 8b 4d 08 mov rcx, QWORD PTR _Tied$[rbp] + 000d7 ff 15 00 00 00 + 00 call QWORD PTR __imp_?flush@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV12@XZ + +; 106 : _Ok = _Ostr.good(); // store test only after flushing tie + + 000dd 48 8b 85 08 01 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 000e4 48 8b 00 mov rax, QWORD PTR [rax] + 000e7 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 000eb 48 8b 8d 08 01 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 000f2 48 03 c8 add rcx, rax + 000f5 48 8b c1 mov rax, rcx + 000f8 48 8b c8 mov rcx, rax + 000fb ff 15 00 00 00 + 00 call QWORD PTR __imp_?good@ios_base@std@@QEBA_NXZ + 00101 48 8b 8d 00 01 + 00 00 mov rcx, QWORD PTR this$[rbp] + 00108 88 41 08 mov BYTE PTR [rcx+8], al +$LN1@sentry: + +; 107 : } + + 0010b 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 00112 48 8d a5 e8 00 + 00 00 lea rsp, QWORD PTR [rbp+232] + 00119 5f pop rdi + 0011a 5d pop rbp + 0011b c3 ret 0 +??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z ENDP ; std::basic_ostream >::sentry::sentry _TEXT ENDS +; COMDAT text$x +text$x SEGMENT +_Tied$ = 8 +this$ = 256 +_Ostr$ = 264 +?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA PROC ; `std::basic_ostream >::sentry::sentry'::`1'::dtor$0 + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 0000a 55 push rbp + 0000b 57 push rdi + 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H + 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] + 00014 48 8b 8d 00 01 + 00 00 mov rcx, QWORD PTR this$[rbp] + 0001b e8 00 00 00 00 call ??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::_Sentry_base::~_Sentry_base + 00020 48 83 c4 28 add rsp, 40 ; 00000028H + 00024 5f pop rdi + 00025 5d pop rbp + 00026 c3 ret 0 +?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA ENDP ; `std::basic_ostream >::sentry::sentry'::`1'::dtor$0 +text$x ENDS +; Function compile flags: /Odtp /RTCsu /ZI +; COMDAT text$x +text$x SEGMENT +_Tied$ = 8 +this$ = 256 +_Ostr$ = 264 +?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA PROC ; `std::basic_ostream >::sentry::sentry'::`1'::dtor$0 + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 0000a 55 push rbp + 0000b 57 push rdi + 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H + 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] + 00014 48 8b 8d 00 01 + 00 00 mov rcx, QWORD PTR this$[rbp] + 0001b e8 00 00 00 00 call ??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::_Sentry_base::~_Sentry_base + 00020 48 83 c4 28 add rsp, 40 ; 00000028H + 00024 5f pop rdi + 00025 5d pop rbp + 00026 c3 ret 0 +?dtor$0@?0???0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z@4HA ENDP ; `std::basic_ostream >::sentry::sentry'::`1'::dtor$0 +text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ostream +; COMDAT ??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ _TEXT SEGMENT -_First$ = 224 -_Last$ = 232 -_Al$ = 240 -??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z PROC ; std::_Destroy_range >, COMDAT +_Rdbuf$ = 8 +tv72 = 216 +this$ = 256 +??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ PROC ; std::basic_ostream >::_Sentry_base::~_Sentry_base, COMDAT -; 955 : void _Destroy_range(_Alloc_ptr_t<_Alloc> _First, const _Alloc_ptr_t<_Alloc> _Last, _Alloc& _Al) noexcept { +; 78 : __CLR_OR_THIS_CALL ~_Sentry_base() noexcept { // destroy after unlocking -$LN3: - 00000 4c 89 44 24 18 mov QWORD PTR [rsp+24], r8 - 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 0000a 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 0000f 55 push rbp - 00010 57 push rdi - 00011 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 00018 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 0001d 48 8b fc mov rdi, rsp - 00020 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 00025 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 0002a f3 ab rep stosd - 0002c 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 00034 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode - 00040 90 npad 1 +$LN4: + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 55 push rbp + 00006 57 push rdi + 00007 48 81 ec 08 01 + 00 00 sub rsp, 264 ; 00000108H + 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00013 48 8b fc mov rdi, rsp + 00016 b9 42 00 00 00 mov ecx, 66 ; 00000042H + 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00020 f3 ab rep stosd + 00022 48 8b 8c 24 28 + 01 00 00 mov rcx, QWORD PTR [rsp+296] + 0002a 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__1D745195_ostream + 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 956 : // note that this is an optimization for debug mode codegen; in release mode the BE removes all of this -; 957 : using _Ty = typename _Alloc::value_type; -; 958 : if _CONSTEXPR_IF (!conjunction_v, _Uses_default_destroy<_Alloc, _Ty*>>) { -; 959 : for (; _First != _Last; ++_First) { -; 960 : allocator_traits<_Alloc>::destroy(_Al, _Unfancy(_First)); -; 961 : } -; 962 : } -; 963 : } +; 79 : const auto _Rdbuf = _Myostr.rdbuf(); - 00041 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00048 5f pop rdi - 00049 5d pop rbp - 0004a c3 ret 0 -??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z ENDP ; std::_Destroy_range > + 00036 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 0003d 48 8b 00 mov rax, QWORD PTR [rax] + 00040 48 89 85 d8 00 + 00 00 mov QWORD PTR tv72[rbp], rax + 00047 48 8b 85 d8 00 + 00 00 mov rax, QWORD PTR tv72[rbp] + 0004e 48 8b 00 mov rax, QWORD PTR [rax] + 00051 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00055 48 8b 8d d8 00 + 00 00 mov rcx, QWORD PTR tv72[rbp] + 0005c 48 03 c8 add rcx, rax + 0005f 48 8b c1 mov rax, rcx + 00062 48 8b c8 mov rcx, rax + 00065 ff 15 00 00 00 + 00 call QWORD PTR __imp_?rdbuf@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_streambuf@DU?$char_traits@D@std@@@2@XZ + 0006b 48 89 45 08 mov QWORD PTR _Rdbuf$[rbp], rax + +; 80 : if (_Rdbuf) { + + 0006f 48 83 7d 08 00 cmp QWORD PTR _Rdbuf$[rbp], 0 + 00074 74 0f je SHORT $LN2@Sentry_bas + +; 81 : _Rdbuf->_Unlock(); + + 00076 48 8b 45 08 mov rax, QWORD PTR _Rdbuf$[rbp] + 0007a 48 8b 00 mov rax, QWORD PTR [rax] + 0007d 48 8b 4d 08 mov rcx, QWORD PTR _Rdbuf$[rbp] + 00081 ff 50 10 call QWORD PTR [rax+16] + 00084 90 npad 1 +$LN2@Sentry_bas: + +; 82 : } +; 83 : } + + 00085 48 8d a5 e8 00 + 00 00 lea rsp, QWORD PTR [rbp+232] + 0008c 5f pop rdi + 0008d 5d pop rbp + 0008e c3 ret 0 +??1_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ENDP ; std::basic_ostream >::_Sentry_base::~_Sentry_base _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ostream +; COMDAT ??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z _TEXT SEGMENT -_Al$ = 224 -_Ptr$ = 232 -??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z PROC ; std::_Delete_plain_internal >, COMDAT +_Rdbuf$ = 8 +tv73 = 216 +this$ = 256 +_Ostr$ = 264 +??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z PROC ; std::basic_ostream >::_Sentry_base::_Sentry_base, COMDAT -; 1026 : void _Delete_plain_internal(_Alloc& _Al, typename _Alloc::value_type* const _Ptr) noexcept { +; 71 : __CLR_OR_THIS_CALL _Sentry_base(basic_ostream& _Ostr) : _Myostr(_Ostr) { // lock the stream buffer, if there -$LN3: +$LN4: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 0000a 55 push rbp 0000b 57 push rdi - 0000c 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H + 0000c 48 81 ec 08 01 + 00 00 sub rsp, 264 ; 00000108H 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00018 48 8b fc mov rdi, rsp - 0001b b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 0001b b9 42 00 00 00 mov ecx, 66 ; 00000042H 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 00025 f3 ab rep stosd - 00027 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] + 00027 48 8b 8c 24 28 + 01 00 00 mov rcx, QWORD PTR [rsp+296] 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory + 00 00 lea rcx, OFFSET FLAT:__1D745195_ostream 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + 0003b 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 00042 48 8b 8d 08 01 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00049 48 89 08 mov QWORD PTR [rax], rcx -; 1027 : // destroy *_Ptr in place, then deallocate _Ptr using _Al; used for internal container types the user didn't name -; 1028 : using _Ty = typename _Alloc::value_type; -; 1029 : _Ptr->~_Ty(); -; 1030 : _Deallocate_plain(_Al, _Ptr); - - 0003b 48 8b 95 e8 00 - 00 00 mov rdx, QWORD PTR _Ptr$[rbp] - 00042 48 8b 8d e0 00 - 00 00 mov rcx, QWORD PTR _Al$[rbp] - 00049 e8 00 00 00 00 call ??$_Deallocate_plain@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z ; std::_Deallocate_plain > - 0004e 90 npad 1 - -; 1031 : } +; 72 : const auto _Rdbuf = _Myostr.rdbuf(); - 0004f 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00056 5f pop rdi - 00057 5d pop rbp - 00058 c3 ret 0 -??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z ENDP ; std::_Delete_plain_internal > + 0004c 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 00053 48 8b 00 mov rax, QWORD PTR [rax] + 00056 48 89 85 d8 00 + 00 00 mov QWORD PTR tv73[rbp], rax + 0005d 48 8b 85 d8 00 + 00 00 mov rax, QWORD PTR tv73[rbp] + 00064 48 8b 00 mov rax, QWORD PTR [rax] + 00067 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 0006b 48 8b 8d d8 00 + 00 00 mov rcx, QWORD PTR tv73[rbp] + 00072 48 03 c8 add rcx, rax + 00075 48 8b c1 mov rax, rcx + 00078 48 8b c8 mov rcx, rax + 0007b ff 15 00 00 00 + 00 call QWORD PTR __imp_?rdbuf@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_streambuf@DU?$char_traits@D@std@@@2@XZ + 00081 48 89 45 08 mov QWORD PTR _Rdbuf$[rbp], rax + +; 73 : if (_Rdbuf) { + + 00085 48 83 7d 08 00 cmp QWORD PTR _Rdbuf$[rbp], 0 + 0008a 74 0e je SHORT $LN2@Sentry_bas + +; 74 : _Rdbuf->_Lock(); + + 0008c 48 8b 45 08 mov rax, QWORD PTR _Rdbuf$[rbp] + 00090 48 8b 00 mov rax, QWORD PTR [rax] + 00093 48 8b 4d 08 mov rcx, QWORD PTR _Rdbuf$[rbp] + 00097 ff 50 08 call QWORD PTR [rax+8] +$LN2@Sentry_bas: + +; 75 : } +; 76 : } + + 0009a 48 8b 85 00 01 + 00 00 mov rax, QWORD PTR this$[rbp] + 000a1 48 8d a5 e8 00 + 00 00 lea rsp, QWORD PTR [rbp+232] + 000a8 5f pop rdi + 000a9 5d pop rbp + 000aa c3 ret 0 +??0_Sentry_base@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z ENDP ; std::basic_ostream >::_Sentry_base::_Sentry_base _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\utility -; COMDAT ??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\iomanip +; COMDAT ??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z _TEXT SEGMENT -_Old_val$ = 8 -_Val$ = 256 -_New_val$ = 264 -??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z PROC ; std::exchange, COMDAT +tv79 = 192 +_Ostr$ = 240 +_Manip$ = 248 +??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z PROC ; std::operator<<,char>, COMDAT -; 597 : conjunction_v, is_nothrow_assignable<_Ty&, _Other>>) /* strengthened */ { +; 49 : const _Fillobj<_Elem2>& _Manip) { // set fill character in output stream $LN3: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 0000a 55 push rbp 0000b 57 push rdi - 0000c 48 81 ec 08 01 - 00 00 sub rsp, 264 ; 00000108H + 0000c 48 81 ec f8 00 + 00 00 sub rsp, 248 ; 000000f8H 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00018 48 8b fc mov rdi, rsp - 0001b b9 42 00 00 00 mov ecx, 66 ; 00000042H + 0001b b9 3e 00 00 00 mov ecx, 62 ; 0000003eH 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 00025 f3 ab rep stosd - 00027 48 8b 8c 24 28 - 01 00 00 mov rcx, QWORD PTR [rsp+296] + 00027 48 8b 8c 24 18 + 01 00 00 mov rcx, QWORD PTR [rsp+280] 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__CF1C1A3F_utility + 00 00 lea rcx, OFFSET FLAT:__8266A2FD_iomanip 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 598 : // assign _New_val to _Val, return previous _Val -; 599 : _Ty _Old_val = static_cast<_Ty&&>(_Val); +; 50 : static_assert(is_same_v<_Elem, _Elem2>, "wrong character type for setfill"); +; 51 : +; 52 : _Ostr.fill(_Manip._Fill); - 0003b 48 8b 85 00 01 - 00 00 mov rax, QWORD PTR _Val$[rbp] + 0003b 48 8b 85 f0 00 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] 00042 48 8b 00 mov rax, QWORD PTR [rax] - 00045 48 89 45 08 mov QWORD PTR _Old_val$[rbp], rax - -; 600 : _Val = static_cast<_Other&&>(_New_val); - - 00049 48 8b 85 00 01 - 00 00 mov rax, QWORD PTR _Val$[rbp] - 00050 48 8b 8d 08 01 - 00 00 mov rcx, QWORD PTR _New_val$[rbp] - 00057 48 8b 09 mov rcx, QWORD PTR [rcx] - 0005a 48 89 08 mov QWORD PTR [rax], rcx + 00045 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00049 48 8b 8d f0 00 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00050 48 03 c8 add rcx, rax + 00053 48 8b c1 mov rax, rcx + 00056 48 89 85 c0 00 + 00 00 mov QWORD PTR tv79[rbp], rax + 0005d 48 8b 85 f8 00 + 00 00 mov rax, QWORD PTR _Manip$[rbp] + 00064 0f b6 10 movzx edx, BYTE PTR [rax] + 00067 48 8b 8d c0 00 + 00 00 mov rcx, QWORD PTR tv79[rbp] + 0006e ff 15 00 00 00 + 00 call QWORD PTR __imp_?fill@?$basic_ios@DU?$char_traits@D@std@@@std@@QEAADD@Z -; 601 : return _Old_val; +; 53 : return _Ostr; - 0005d 48 8b 45 08 mov rax, QWORD PTR _Old_val$[rbp] + 00074 48 8b 85 f0 00 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] -; 602 : } +; 54 : } - 00061 48 8d a5 e8 00 - 00 00 lea rsp, QWORD PTR [rbp+232] - 00068 5f pop rdi - 00069 5d pop rbp - 0006a c3 ret 0 -??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z ENDP ; std::exchange + 0007b 48 8d a5 d8 00 + 00 00 lea rsp, QWORD PTR [rbp+216] + 00082 5f pop rdi + 00083 5d pop rbp + 00084 c3 ret 0 +??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z ENDP ; std::operator<<,char> _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\iomanip +; COMDAT ??0?$_Fillobj@D@std@@QEAA@D@Z _TEXT SEGMENT this$ = 224 -__formal$ = 232 -??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z PROC ; std::allocator::allocator, COMDAT +_Ch$ = 232 +??0?$_Fillobj@D@std@@QEAA@D@Z PROC ; std::_Fillobj::_Fillobj, COMDAT -; 799 : constexpr allocator(const allocator<_Other>&) noexcept {} +; 27 : _Fillobj(_Elem _Ch) : _Fill(_Ch) {} $LN3: - 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 0000a 55 push rbp - 0000b 57 push rdi - 0000c 48 81 ec e8 00 + 00000 88 54 24 10 mov BYTE PTR [rsp+16], dl + 00004 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00009 55 push rbp + 0000a 57 push rdi + 0000b 48 81 ec e8 00 00 00 sub rsp, 232 ; 000000e8H - 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00018 48 8b fc mov rdi, rsp - 0001b b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00025 f3 ab rep stosd - 00027 48 8b 8c 24 08 + 00012 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00017 48 8b fc mov rdi, rsp + 0001a b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 0001f b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00024 f3 ab rep stosd + 00026 48 8b 8c 24 08 01 00 00 mov rcx, QWORD PTR [rsp+264] - 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode - 0003b 48 8b 85 e0 00 + 0002e 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__8266A2FD_iomanip + 00035 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + 0003a 48 8b 85 e0 00 00 00 mov rax, QWORD PTR this$[rbp] - 00042 48 8d a5 c8 00 + 00041 0f b6 8d e8 00 + 00 00 movzx ecx, BYTE PTR _Ch$[rbp] + 00048 88 08 mov BYTE PTR [rax], cl + 0004a 48 8b 85 e0 00 + 00 00 mov rax, QWORD PTR this$[rbp] + 00051 48 8d a5 c8 00 00 00 lea rsp, QWORD PTR [rbp+200] - 00049 5f pop rdi - 0004a 5d pop rbp - 0004b c3 ret 0 -??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z ENDP ; std::allocator::allocator + 00058 5f pop rdi + 00059 5d pop rbp + 0005a c3 ret 0 +??0?$_Fillobj@D@std@@QEAA@D@Z ENDP ; std::_Fillobj::_Fillobj _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\$Fanta\code-virtualizer\CodeVirtualizer\Main.cpp -; COMDAT main +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\iomanip +; COMDAT ??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z _TEXT SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main PROC ; COMDAT +__$ReturnUdt$ = 224 +_Ch$ = 232 +??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z PROC ; std::setfill, COMDAT -; 44 : { +; 34 : _NODISCARD _Fillobj<_Elem> setfill(_Elem _Ch) { -$LN6: - 00000 40 55 push rbp - 00002 57 push rdi - 00003 48 81 ec e8 01 - 00 00 sub rsp, 488 ; 000001e8H - 0000a 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 0000f 48 8b fc mov rdi, rsp - 00012 b9 7a 00 00 00 mov ecx, 122 ; 0000007aH - 00017 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 0001c f3 ab rep stosd - 0001e 48 8b 05 00 00 - 00 00 mov rax, QWORD PTR __security_cookie - 00025 48 33 c5 xor rax, rbp - 00028 48 89 85 b0 01 - 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax - 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__4031338C_Main@cpp - 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode +$LN3: + 00000 88 54 24 10 mov BYTE PTR [rsp+16], dl + 00004 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00009 55 push rbp + 0000a 57 push rdi + 0000b 48 81 ec e8 00 + 00 00 sub rsp, 232 ; 000000e8H + 00012 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00017 48 8b fc mov rdi, rsp + 0001a b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 0001f b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00024 f3 ab rep stosd + 00026 48 8b 8c 24 08 + 01 00 00 mov rcx, QWORD PTR [rsp+264] + 0002e 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__8266A2FD_iomanip + 00035 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 45 : XedTablesInit(); +; 35 : return _Fillobj<_Elem>(_Ch); - 0003b e8 00 00 00 00 call xed_tables_init + 0003a 0f b6 95 e8 00 + 00 00 movzx edx, BYTE PTR _Ch$[rbp] + 00041 48 8b 8d e0 00 + 00 00 mov rcx, QWORD PTR __$ReturnUdt$[rbp] + 00048 e8 00 00 00 00 call ??0?$_Fillobj@D@std@@QEAA@D@Z ; std::_Fillobj::_Fillobj + 0004d 48 8b 85 e0 00 + 00 00 mov rax, QWORD PTR __$ReturnUdt$[rbp] -; 46 : srand(time(NULL)); +; 36 : } - 00040 33 c9 xor ecx, ecx - 00042 e8 00 00 00 00 call time - 00047 8b c8 mov ecx, eax - 00049 ff 15 00 00 00 - 00 call QWORD PTR __imp_srand + 00054 48 8d a5 c8 00 + 00 00 lea rsp, QWORD PTR [rbp+200] + 0005b 5f pop rdi + 0005c 5d pop rbp + 0005d c3 ret 0 +??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z ENDP ; std::setfill +_TEXT ENDS +; Function compile flags: /Odtp /RTCsu /ZI +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\iomanip +; COMDAT ??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z +_TEXT SEGMENT +tv79 = 192 +_Ostr$ = 240 +_Manip$ = 248 +??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z PROC ; std::operator<<,__int64>, COMDAT -; 47 : -; 48 : -; 49 : NATIVE_CODE_BLOCK Block; - - 0004f 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 00053 e8 00 00 00 00 call ??0_NATIVE_CODE_BLOCK@@QEAA@XZ ; _NATIVE_CODE_BLOCK::_NATIVE_CODE_BLOCK - 00058 90 npad 1 - -; 50 : NcDisassemble(&Block, TestBuffer, TestBufferSize); - - 00059 44 8b 05 00 00 - 00 00 mov r8d, DWORD PTR ?TestBufferSize@@3KA ; TestBufferSize - 00060 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:?TestBuffer@@3PAEA ; TestBuffer - 00067 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 0006b e8 00 00 00 00 call ?NcDisassemble@@YAHPEAU_NATIVE_CODE_BLOCK@@PEAXK@Z ; NcDisassemble - -; 51 : NATIVE_CODE_BLOCK NotTaken; - - 00070 48 8d 4d 58 lea rcx, QWORD PTR NotTaken$[rbp] - 00074 e8 00 00 00 00 call ??0_NATIVE_CODE_BLOCK@@QEAA@XZ ; _NATIVE_CODE_BLOCK::_NATIVE_CODE_BLOCK - 00079 90 npad 1 - -; 52 : NATIVE_CODE_BLOCK Taken; - - 0007a 48 8d 8d a8 00 - 00 00 lea rcx, QWORD PTR Taken$[rbp] - 00081 e8 00 00 00 00 call ??0_NATIVE_CODE_BLOCK@@QEAA@XZ ; _NATIVE_CODE_BLOCK::_NATIVE_CODE_BLOCK - 00086 90 npad 1 - -; 53 : printf("\n\nOriginal\n"); - - 00087 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_0M@INKCCKOG@?6?6Original?6@ - 0008e e8 00 00 00 00 call printf - -; 54 : NcDebugPrint(&Block); - - 00093 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 00097 e8 00 00 00 00 call ?NcDebugPrint@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDebugPrint - -; 55 : ObfCreateOpaqueBranches(Block.Start->Next, Block.Start->Next->Next->Next->Next, &NotTaken, &Taken); - - 0009c 48 8b 45 08 mov rax, QWORD PTR Block$[rbp] - 000a0 48 8b 00 mov rax, QWORD PTR [rax] - 000a3 48 8b 00 mov rax, QWORD PTR [rax] - 000a6 48 8b 00 mov rax, QWORD PTR [rax] - 000a9 4c 8d 8d a8 00 - 00 00 lea r9, QWORD PTR Taken$[rbp] - 000b0 4c 8d 45 58 lea r8, QWORD PTR NotTaken$[rbp] - 000b4 48 8b 10 mov rdx, QWORD PTR [rax] - 000b7 48 8b 45 08 mov rax, QWORD PTR Block$[rbp] - 000bb 48 8b 08 mov rcx, QWORD PTR [rax] - 000be e8 00 00 00 00 call ?ObfCreateOpaqueBranches@@YAHPEAU_NATIVE_CODE_LINK@@0PEAU_NATIVE_CODE_BLOCK@@1@Z ; ObfCreateOpaqueBranches - -; 56 : //printf("\n\nNotTaken\n"); -; 57 : //NcDebugPrint(&NotTaken); -; 58 : //printf("\n\nTaken\n"); -; 59 : //NcDebugPrint(&Taken); -; 60 : //printf("\n\nCombined\n"); -; 61 : ObfCombineOpaqueBranches(&NotTaken, &Taken, NcGenUnusedLabelId(&Block), NcGenUnusedLabelId(&Block)); - - 000c3 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 000c7 e8 00 00 00 00 call ?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z ; NcGenUnusedLabelId - 000cc 89 85 a4 01 00 - 00 mov DWORD PTR tv135[rbp], eax - 000d2 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 000d6 e8 00 00 00 00 call ?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z ; NcGenUnusedLabelId - 000db 89 85 a8 01 00 - 00 mov DWORD PTR tv133[rbp], eax - 000e1 44 8b 8d a4 01 - 00 00 mov r9d, DWORD PTR tv135[rbp] - 000e8 44 8b 85 a8 01 - 00 00 mov r8d, DWORD PTR tv133[rbp] - 000ef 48 8d 95 a8 00 - 00 00 lea rdx, QWORD PTR Taken$[rbp] - 000f6 48 8d 4d 58 lea rcx, QWORD PTR NotTaken$[rbp] - 000fa e8 00 00 00 00 call ?ObfCombineOpaqueBranches@@YAHPEAU_NATIVE_CODE_BLOCK@@0KK@Z ; ObfCombineOpaqueBranches - -; 62 : ObfInsertOpaqueBranchBlock(Block.Start->Next, Block.Start->Next->Next->Next->Next, &NotTaken); - - 000ff 48 8b 45 08 mov rax, QWORD PTR Block$[rbp] - 00103 48 8b 00 mov rax, QWORD PTR [rax] - 00106 48 8b 00 mov rax, QWORD PTR [rax] - 00109 48 8b 00 mov rax, QWORD PTR [rax] - 0010c 4c 8d 45 58 lea r8, QWORD PTR NotTaken$[rbp] - 00110 48 8b 10 mov rdx, QWORD PTR [rax] - 00113 48 8b 45 08 mov rax, QWORD PTR Block$[rbp] - 00117 48 8b 08 mov rcx, QWORD PTR [rax] - 0011a e8 00 00 00 00 call ?ObfInsertOpaqueBranchBlock@@YAHPEAU_NATIVE_CODE_LINK@@0PEAU_NATIVE_CODE_BLOCK@@@Z ; ObfInsertOpaqueBranchBlock - -; 63 : printf("\n\nNew\n"); - - 0011f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_06CHBCCLOP@?6?6New?6@ - 00126 e8 00 00 00 00 call printf - -; 64 : NcDebugPrint(&Block); - - 0012b 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 0012f e8 00 00 00 00 call ?NcDebugPrint@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDebugPrint - 00134 90 npad 1 +; 423 : const _Smanip<_Arg>& _Manip) { // insert by calling function with output stream and argument -; 65 : -; 66 : -; 67 : //PNATIVE_CODE_LINK Return1776 = new NATIVE_CODE_LINK(CODE_FLAG_IS_INST, meme1, sizeof(meme1)); -; 68 : //PNATIVE_CODE_LINK RetInst = new NATIVE_CODE_LINK(CODE_FLAG_IS_INST, meme2, sizeof(meme2)); -; 69 : //PNATIVE_CODE_BLOCK Pre1 = JitEmitPreRipMov(Return1776); -; 70 : //PNATIVE_CODE_BLOCK Post1 = JitEmitPostRipMov(Return1776); -; 71 : //PNATIVE_CODE_BLOCK Pre2 = JitEmitPreRipMov(RetInst); -; 72 : //PNATIVE_CODE_BLOCK Post2 = JitEmitPostRipMov(RetInst); -; 73 : -; 74 : //NcAppendToBlock(Pre1, Return1776); -; 75 : //NcInsertBlockAfter(Pre1->End, Post1, 0); -; 76 : //Pre1->End = Post1->End; -; 77 : //NcInsertBlockAfter(Pre1->End, Pre2, 0); -; 78 : //Pre1->End = Pre2->End; -; 79 : //NcAppendToBlock(Pre1, RetInst); -; 80 : //NcInsertBlockAfter(Pre1->End, Post2, 0); -; 81 : //Pre1->End = Post2->End; -; 82 : -; 83 : ///*Pre->Start = Return1776; -; 84 : //Pre->End = Return1776;*/ -; 85 : -; 86 : //for (ULONG i = 0; i < Return1776->RawDataSize; i++) -; 87 : // Return1776->RawData[i] = (UCHAR)rand(); -; 88 : //for (ULONG i = 0; i < RetInst->RawDataSize; i++) -; 89 : // RetInst->RawData[i] = (UCHAR)rand(); -; 90 : -; 91 : -; 92 : -; 93 : //ULONG AsmLen; -; 94 : //PVOID Asm = NcAssemble(Pre1, &AsmLen); -; 95 : //PUCHAR Tb = (PUCHAR)Asm; -; 96 : //for (uint32_t i = 0; i < AsmLen; i++) -; 97 : //{ -; 98 : // std::cout << std::hex << std::setw(2) << std::setfill('0') << (int)Tb[i] << ' '; -; 99 : //} -; 100 : -; 101 : //system("pause"); -; 102 : -; 103 : //typedef ULONG64(*FnGet1776)(); -; 104 : //FnGet1776 ExecBuffer = (FnGet1776)MakeExecutableBuffer(Asm, AsmLen); -; 105 : //if (ExecBuffer) -; 106 : //{ -; 107 : // printf("The numba was: %X\n", ExecBuffer()); -; 108 : // printf("The numba was: %X\n", ExecBuffer()); -; 109 : -; 110 : // printf("The numba was: %X\n", ExecBuffer()); -; 111 : -; 112 : // printf("The numba was: %X\n", ExecBuffer()); -; 113 : -; 114 : //} -; 115 : -; 116 : -; 117 : //NcDebugPrint(Post); -; 118 : -; 119 : -; 120 : -; 121 : /*NATIVE_CODE_BLOCK Block; -; 122 : NcDisassemble(&Block, TestBuffer, TestBufferSize); -; 123 : PNATIVE_CODE_LINK NewLink = new NATIVE_CODE_LINK(CODE_FLAG_IS_INST, meme1, sizeof(meme1)); -; 124 : -; 125 : NcInsertLinkBefore(Block.End->Prev->Prev->Prev->Prev, NewLink); -; 126 : ULONG AssembledSize; -; 127 : PVOID AssembledBlock = NcAssemble(&Block, &AssembledSize); -; 128 : if (!AssembledBlock || !AssembledSize) -; 129 : { -; 130 : printf("Something failed nicka.\n"); -; 131 : system("pause"); -; 132 : return -1; -; 133 : } -; 134 : PUCHAR Tb = (PUCHAR)AssembledBlock; -; 135 : for (uint32_t i = 0; i < AssembledSize; i++) -; 136 : { -; 137 : std::cout << std::hex << std::setw(2) << std::setfill('0') << (int)Tb[i] << ' '; -; 138 : } -; 139 : */ -; 140 : -; 141 : -; 142 : //PNATIVE_CODE_BLOCK OpaqueBranch = ObfGenOpaqueBranch(Block.Start, Block.End); -; 143 : //NcDebugPrint(OpaqueBranch); -; 144 : -; 145 : -; 146 : -; 147 : /*NATIVE_CODE_LINK T; -; 148 : T.RawDataSize = 10; -; 149 : T.RawData = new UCHAR[10]; -; 150 : memset(T.RawData, 0xAA, 10); -; 151 : JIT_BITWISE_DATA Data; -; 152 : RtlSecureZeroMemory(&Data, sizeof(JIT_BITWISE_DATA)); -; 153 : PNATIVE_CODE_BLOCK NewBlock = JitEmitPreRipMov(&T); -; 154 : if (NewBlock) -; 155 : { -; 156 : printf("\n"); -; 157 : NcDebugPrint(NewBlock); -; 158 : printf("\n"); -; 159 : NcPrintBlockCode(NewBlock); -; 160 : } -; 161 : system("pause");*/ -; 162 : -; 163 : } - - 00135 48 8d 8d a8 00 - 00 00 lea rcx, QWORD PTR Taken$[rbp] - 0013c e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 00141 90 npad 1 - 00142 48 8d 4d 58 lea rcx, QWORD PTR NotTaken$[rbp] - 00146 e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 0014b 90 npad 1 - 0014c 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 00150 e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 00155 33 c0 xor eax, eax - 00157 8b f8 mov edi, eax - 00159 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] - 0015d 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:main$rtcFrameData - 00164 e8 00 00 00 00 call _RTC_CheckStackVars - 00169 8b c7 mov eax, edi - 0016b 48 8b 8d b0 01 - 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] - 00172 48 33 cd xor rcx, rbp - 00175 e8 00 00 00 00 call __security_check_cookie - 0017a 48 8d a5 c8 01 - 00 00 lea rsp, QWORD PTR [rbp+456] - 00181 5f pop rdi - 00182 5d pop rbp - 00183 c3 ret 0 -main ENDP -_TEXT ENDS -; COMDAT text$x -text$x SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main$dtor$0 PROC - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx +$LN3: + 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 0000a 55 push rbp 0000b 57 push rdi - 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H - 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 00018 e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 0001d 48 83 c4 28 add rsp, 40 ; 00000028H - 00021 5f pop rdi - 00022 5d pop rbp - 00023 c3 ret 0 -main$dtor$0 ENDP -text$x ENDS + 0000c 48 81 ec f8 00 + 00 00 sub rsp, 248 ; 000000f8H + 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00018 48 8b fc mov rdi, rsp + 0001b b9 3e 00 00 00 mov ecx, 62 ; 0000003eH + 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00025 f3 ab rep stosd + 00027 48 8b 8c 24 18 + 01 00 00 mov rcx, QWORD PTR [rsp+280] + 0002f 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__8266A2FD_iomanip + 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + +; 424 : (*_Manip._Pfun)(_Ostr, _Manip._Manarg); + + 0003b 48 8b 85 f8 00 + 00 00 mov rax, QWORD PTR _Manip$[rbp] + 00042 48 8b 00 mov rax, QWORD PTR [rax] + 00045 48 89 85 c0 00 + 00 00 mov QWORD PTR tv79[rbp], rax + 0004c 48 8b 85 f0 00 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00053 48 8b 00 mov rax, QWORD PTR [rax] + 00056 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 0005a 48 8b 8d f0 00 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00061 48 03 c8 add rcx, rax + 00064 48 8b c1 mov rax, rcx + 00067 48 8b 8d f8 00 + 00 00 mov rcx, QWORD PTR _Manip$[rbp] + 0006e 48 8b 51 08 mov rdx, QWORD PTR [rcx+8] + 00072 48 8b c8 mov rcx, rax + 00075 ff 95 c0 00 00 + 00 call QWORD PTR tv79[rbp] + +; 425 : return _Ostr; + + 0007b 48 8b 85 f0 00 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + +; 426 : } + + 00082 48 8d a5 d8 00 + 00 00 lea rsp, QWORD PTR [rbp+216] + 00089 5f pop rdi + 0008a 5d pop rbp + 0008b c3 ret 0 +??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z ENDP ; std::operator<<,__int64> +_TEXT ENDS +; Function compile flags: /Odtp /RTCsu /ZI +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ostream +; COMDAT ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z +_TEXT SEGMENT +_State$ = 4 +_Ok$ = 40 +_Pad$4 = 88 +$T5 = 308 +$T6 = 340 +$T7 = 372 +$T8 = 404 +$T9 = 436 +$T10 = 468 +$T11 = 504 +tv65 = 516 +tv305 = 520 +tv303 = 520 +tv300 = 520 +tv295 = 520 +tv281 = 520 +tv266 = 520 +tv130 = 520 +tv245 = 528 +tv204 = 528 +tv179 = 528 +tv306 = 536 +tv304 = 536 +tv301 = 536 +tv243 = 537 +tv177 = 537 +tv307 = 540 +tv302 = 540 +__$ArrayPad$ = 544 +_Ostr$ = 592 +_Ch$ = 600 +??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z PROC ; std::operator<< >, COMDAT + +; 780 : basic_ostream& _Ostr, char _Ch) { // insert a char into char stream + +$LN23: + 00000 88 54 24 10 mov BYTE PTR [rsp+16], dl + 00004 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00009 55 push rbp + 0000a 57 push rdi + 0000b 48 81 ec 58 02 + 00 00 sub rsp, 600 ; 00000258H + 00012 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00017 48 8b fc mov rdi, rsp + 0001a b9 96 00 00 00 mov ecx, 150 ; 00000096H + 0001f b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00024 f3 ab rep stosd + 00026 48 8b 8c 24 78 + 02 00 00 mov rcx, QWORD PTR [rsp+632] + 0002e 48 8b 05 00 00 + 00 00 mov rax, QWORD PTR __security_cookie + 00035 48 33 c5 xor rax, rbp + 00038 48 89 85 20 02 + 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax + 0003f 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__1D745195_ostream + 00046 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + +; 781 : using _Elem = char; +; 782 : using _Myos = basic_ostream<_Elem, _Traits>; +; 783 : +; 784 : ios_base::iostate _State = ios_base::goodbit; + + 0004b c7 45 04 00 00 + 00 00 mov DWORD PTR _State$[rbp], 0 + +; 785 : const typename _Myos::sentry _Ok(_Ostr); + + 00052 48 8b 95 50 02 + 00 00 mov rdx, QWORD PTR _Ostr$[rbp] + 00059 48 8d 4d 28 lea rcx, QWORD PTR _Ok$[rbp] + 0005d e8 00 00 00 00 call ??0sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@AEAV12@@Z ; std::basic_ostream >::sentry::sentry + 00062 90 npad 1 + +; 786 : +; 787 : if (_Ok) { // state okay, insert + + 00063 48 8d 4d 28 lea rcx, QWORD PTR _Ok$[rbp] + 00067 e8 00 00 00 00 call ??Bsentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEBA_NXZ ; std::basic_ostream >::sentry::operator bool + 0006c 0f b6 c0 movzx eax, al + 0006f 85 c0 test eax, eax + 00071 0f 84 1d 03 00 + 00 je $LN8@operator + +; 788 : streamsize _Pad = _Ostr.width() <= 1 ? 0 : _Ostr.width() - 1; + + 00077 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 0007e 48 8b 00 mov rax, QWORD PTR [rax] + 00081 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00085 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 0008c 48 03 c8 add rcx, rax + 0008f 48 8b c1 mov rax, rcx + 00092 48 8b c8 mov rcx, rax + 00095 ff 15 00 00 00 + 00 call QWORD PTR __imp_?width@ios_base@std@@QEBA_JXZ + 0009b 48 83 f8 01 cmp rax, 1 + 0009f 7f 0d jg SHORT $LN15@operator + 000a1 48 c7 85 08 02 + 00 00 00 00 00 + 00 mov QWORD PTR tv130[rbp], 0 + 000ac eb 2e jmp SHORT $LN16@operator +$LN15@operator: + 000ae 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 000b5 48 8b 00 mov rax, QWORD PTR [rax] + 000b8 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 000bc 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 000c3 48 03 c8 add rcx, rax + 000c6 48 8b c1 mov rax, rcx + 000c9 48 8b c8 mov rcx, rax + 000cc ff 15 00 00 00 + 00 call QWORD PTR __imp_?width@ios_base@std@@QEBA_JXZ + 000d2 48 ff c8 dec rax + 000d5 48 89 85 08 02 + 00 00 mov QWORD PTR tv130[rbp], rax +$LN16@operator: + 000dc 48 8b 85 08 02 + 00 00 mov rax, QWORD PTR tv130[rbp] + 000e3 48 89 45 58 mov QWORD PTR _Pad$4[rbp], rax + +; 789 : +; 790 : _TRY_IO_BEGIN +; 791 : if ((_Ostr.flags() & ios_base::adjustfield) != ios_base::left) { + + 000e7 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 000ee 48 8b 00 mov rax, QWORD PTR [rax] + 000f1 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 000f5 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 000fc 48 03 c8 add rcx, rax + 000ff 48 8b c1 mov rax, rcx + 00102 48 8b c8 mov rcx, rax + 00105 ff 15 00 00 00 + 00 call QWORD PTR __imp_?flags@ios_base@std@@QEBAHXZ + 0010b 89 85 04 02 00 + 00 mov DWORD PTR tv65[rbp], eax + 00111 8b 85 04 02 00 + 00 mov eax, DWORD PTR tv65[rbp] + 00117 25 c0 01 00 00 and eax, 448 ; 000001c0H + 0011c 83 f8 40 cmp eax, 64 ; 00000040H + 0011f 0f 84 eb 00 00 + 00 je $LN10@operator + +; 792 : for (; _State == ios_base::goodbit && 0 < _Pad; --_Pad) { // pad on left + + 00125 eb 0b jmp SHORT $LN4@operator +$LN2@operator: + 00127 48 8b 45 58 mov rax, QWORD PTR _Pad$4[rbp] + 0012b 48 ff c8 dec rax + 0012e 48 89 45 58 mov QWORD PTR _Pad$4[rbp], rax +$LN4@operator: + 00132 83 7d 04 00 cmp DWORD PTR _State$[rbp], 0 + 00136 0f 85 d4 00 00 + 00 jne $LN10@operator + 0013c 48 83 7d 58 00 cmp QWORD PTR _Pad$4[rbp], 0 + 00141 0f 8e c9 00 00 + 00 jle $LN10@operator + +; 793 : if (_Traits::eq_int_type(_Traits::eof(), _Ostr.rdbuf()->sputc(_Ostr.fill()))) { + + 00147 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 0014e 48 8b 00 mov rax, QWORD PTR [rax] + 00151 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00155 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 0015c 48 03 c8 add rcx, rax + 0015f 48 8b c1 mov rax, rcx + 00162 48 8b c8 mov rcx, rax + 00165 ff 15 00 00 00 + 00 call QWORD PTR __imp_?rdbuf@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_streambuf@DU?$char_traits@D@std@@@2@XZ + 0016b 48 89 85 08 02 + 00 00 mov QWORD PTR tv300[rbp], rax + 00172 48 8b 85 08 02 + 00 00 mov rax, QWORD PTR tv300[rbp] + 00179 48 89 85 10 02 + 00 00 mov QWORD PTR tv179[rbp], rax + 00180 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00187 48 8b 00 mov rax, QWORD PTR [rax] + 0018a 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 0018e 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00195 48 03 c8 add rcx, rax + 00198 48 8b c1 mov rax, rcx + 0019b 48 8b c8 mov rcx, rax + 0019e ff 15 00 00 00 + 00 call QWORD PTR __imp_?fill@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBADXZ + 001a4 88 85 18 02 00 + 00 mov BYTE PTR tv301[rbp], al + 001aa 0f b6 85 18 02 + 00 00 movzx eax, BYTE PTR tv301[rbp] + 001b1 88 85 19 02 00 + 00 mov BYTE PTR tv177[rbp], al + 001b7 0f b6 95 19 02 + 00 00 movzx edx, BYTE PTR tv177[rbp] + 001be 48 8b 8d 10 02 + 00 00 mov rcx, QWORD PTR tv179[rbp] + 001c5 ff 15 00 00 00 + 00 call QWORD PTR __imp_?sputc@?$basic_streambuf@DU?$char_traits@D@std@@@std@@QEAAHD@Z + 001cb 89 85 1c 02 00 + 00 mov DWORD PTR tv302[rbp], eax + 001d1 8b 85 1c 02 00 + 00 mov eax, DWORD PTR tv302[rbp] + 001d7 89 85 34 01 00 + 00 mov DWORD PTR $T5[rbp], eax + 001dd e8 00 00 00 00 call ?eof@?$_Narrow_char_traits@DH@std@@SAHXZ ; std::_Narrow_char_traits::eof + 001e2 89 85 54 01 00 + 00 mov DWORD PTR $T6[rbp], eax + 001e8 48 8d 95 34 01 + 00 00 lea rdx, QWORD PTR $T5[rbp] + 001ef 48 8d 8d 54 01 + 00 00 lea rcx, QWORD PTR $T6[rbp] + 001f6 e8 00 00 00 00 call ?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z ; std::_Narrow_char_traits::eq_int_type + 001fb 0f b6 c0 movzx eax, al + 001fe 85 c0 test eax, eax + 00200 74 09 je SHORT $LN11@operator + +; 794 : _State |= ios_base::badbit; + + 00202 8b 45 04 mov eax, DWORD PTR _State$[rbp] + 00205 83 c8 04 or eax, 4 + 00208 89 45 04 mov DWORD PTR _State$[rbp], eax +$LN11@operator: + +; 795 : } +; 796 : } + + 0020b e9 17 ff ff ff jmp $LN2@operator +$LN10@operator: + +; 797 : } +; 798 : +; 799 : if (_State == ios_base::goodbit && _Traits::eq_int_type(_Traits::eof(), _Ostr.rdbuf()->sputc(_Ch))) { + + 00210 83 7d 04 00 cmp DWORD PTR _State$[rbp], 0 + 00214 0f 85 8d 00 00 + 00 jne $LN12@operator + 0021a 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00221 48 8b 00 mov rax, QWORD PTR [rax] + 00224 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00228 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 0022f 48 03 c8 add rcx, rax + 00232 48 8b c1 mov rax, rcx + 00235 48 8b c8 mov rcx, rax + 00238 ff 15 00 00 00 + 00 call QWORD PTR __imp_?rdbuf@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_streambuf@DU?$char_traits@D@std@@@2@XZ + 0023e 48 89 85 08 02 + 00 00 mov QWORD PTR tv303[rbp], rax + 00245 48 8b 85 08 02 + 00 00 mov rax, QWORD PTR tv303[rbp] + 0024c 48 89 85 10 02 + 00 00 mov QWORD PTR tv204[rbp], rax + 00253 0f b6 95 58 02 + 00 00 movzx edx, BYTE PTR _Ch$[rbp] + 0025a 48 8b 8d 10 02 + 00 00 mov rcx, QWORD PTR tv204[rbp] + 00261 ff 15 00 00 00 + 00 call QWORD PTR __imp_?sputc@?$basic_streambuf@DU?$char_traits@D@std@@@std@@QEAAHD@Z + 00267 89 85 18 02 00 + 00 mov DWORD PTR tv304[rbp], eax + 0026d 8b 85 18 02 00 + 00 mov eax, DWORD PTR tv304[rbp] + 00273 89 85 74 01 00 + 00 mov DWORD PTR $T7[rbp], eax + 00279 e8 00 00 00 00 call ?eof@?$_Narrow_char_traits@DH@std@@SAHXZ ; std::_Narrow_char_traits::eof + 0027e 89 85 94 01 00 + 00 mov DWORD PTR $T8[rbp], eax + 00284 48 8d 95 74 01 + 00 00 lea rdx, QWORD PTR $T7[rbp] + 0028b 48 8d 8d 94 01 + 00 00 lea rcx, QWORD PTR $T8[rbp] + 00292 e8 00 00 00 00 call ?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z ; std::_Narrow_char_traits::eq_int_type + 00297 0f b6 c0 movzx eax, al + 0029a 85 c0 test eax, eax + 0029c 74 09 je SHORT $LN12@operator + +; 800 : _State |= ios_base::badbit; + + 0029e 8b 45 04 mov eax, DWORD PTR _State$[rbp] + 002a1 83 c8 04 or eax, 4 + 002a4 89 45 04 mov DWORD PTR _State$[rbp], eax +$LN12@operator: + +; 801 : } +; 802 : +; 803 : for (; _State == ios_base::goodbit && 0 < _Pad; --_Pad) { // pad on right + + 002a7 eb 0b jmp SHORT $LN7@operator +$LN5@operator: + 002a9 48 8b 45 58 mov rax, QWORD PTR _Pad$4[rbp] + 002ad 48 ff c8 dec rax + 002b0 48 89 45 58 mov QWORD PTR _Pad$4[rbp], rax +$LN7@operator: + 002b4 83 7d 04 00 cmp DWORD PTR _State$[rbp], 0 + 002b8 0f 85 d4 00 00 + 00 jne $LN6@operator + 002be 48 83 7d 58 00 cmp QWORD PTR _Pad$4[rbp], 0 + 002c3 0f 8e c9 00 00 + 00 jle $LN6@operator + +; 804 : if (_Traits::eq_int_type(_Traits::eof(), _Ostr.rdbuf()->sputc(_Ostr.fill()))) { + + 002c9 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 002d0 48 8b 00 mov rax, QWORD PTR [rax] + 002d3 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 002d7 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 002de 48 03 c8 add rcx, rax + 002e1 48 8b c1 mov rax, rcx + 002e4 48 8b c8 mov rcx, rax + 002e7 ff 15 00 00 00 + 00 call QWORD PTR __imp_?rdbuf@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBAPEAV?$basic_streambuf@DU?$char_traits@D@std@@@2@XZ + 002ed 48 89 85 08 02 + 00 00 mov QWORD PTR tv305[rbp], rax + 002f4 48 8b 85 08 02 + 00 00 mov rax, QWORD PTR tv305[rbp] + 002fb 48 89 85 10 02 + 00 00 mov QWORD PTR tv245[rbp], rax + 00302 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00309 48 8b 00 mov rax, QWORD PTR [rax] + 0030c 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00310 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00317 48 03 c8 add rcx, rax + 0031a 48 8b c1 mov rax, rcx + 0031d 48 8b c8 mov rcx, rax + 00320 ff 15 00 00 00 + 00 call QWORD PTR __imp_?fill@?$basic_ios@DU?$char_traits@D@std@@@std@@QEBADXZ + 00326 88 85 18 02 00 + 00 mov BYTE PTR tv306[rbp], al + 0032c 0f b6 85 18 02 + 00 00 movzx eax, BYTE PTR tv306[rbp] + 00333 88 85 19 02 00 + 00 mov BYTE PTR tv243[rbp], al + 00339 0f b6 95 19 02 + 00 00 movzx edx, BYTE PTR tv243[rbp] + 00340 48 8b 8d 10 02 + 00 00 mov rcx, QWORD PTR tv245[rbp] + 00347 ff 15 00 00 00 + 00 call QWORD PTR __imp_?sputc@?$basic_streambuf@DU?$char_traits@D@std@@@std@@QEAAHD@Z + 0034d 89 85 1c 02 00 + 00 mov DWORD PTR tv307[rbp], eax + 00353 8b 85 1c 02 00 + 00 mov eax, DWORD PTR tv307[rbp] + 00359 89 85 b4 01 00 + 00 mov DWORD PTR $T9[rbp], eax + 0035f e8 00 00 00 00 call ?eof@?$_Narrow_char_traits@DH@std@@SAHXZ ; std::_Narrow_char_traits::eof + 00364 89 85 d4 01 00 + 00 mov DWORD PTR $T10[rbp], eax + 0036a 48 8d 95 b4 01 + 00 00 lea rdx, QWORD PTR $T9[rbp] + 00371 48 8d 8d d4 01 + 00 00 lea rcx, QWORD PTR $T10[rbp] + 00378 e8 00 00 00 00 call ?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z ; std::_Narrow_char_traits::eq_int_type + 0037d 0f b6 c0 movzx eax, al + 00380 85 c0 test eax, eax + 00382 74 09 je SHORT $LN13@operator + +; 805 : _State |= ios_base::badbit; + + 00384 8b 45 04 mov eax, DWORD PTR _State$[rbp] + 00387 83 c8 04 or eax, 4 + 0038a 89 45 04 mov DWORD PTR _State$[rbp], eax +$LN13@operator: + +; 806 : } +; 807 : } + + 0038d e9 17 ff ff ff jmp $LN5@operator +$LN6@operator: + 00392 eb 00 jmp SHORT $LN8@operator +$LN21@operator: +$LN8@operator: + +; 808 : _CATCH_IO_(ios_base, _Ostr) +; 809 : } +; 810 : +; 811 : _Ostr.width(0); + + 00394 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 0039b 48 8b 00 mov rax, QWORD PTR [rax] + 0039e 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 003a2 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 003a9 48 03 c8 add rcx, rax + 003ac 48 8b c1 mov rax, rcx + 003af 48 89 85 08 02 + 00 00 mov QWORD PTR tv281[rbp], rax + 003b6 33 d2 xor edx, edx + 003b8 48 8b 8d 08 02 + 00 00 mov rcx, QWORD PTR tv281[rbp] + 003bf ff 15 00 00 00 + 00 call QWORD PTR __imp_?width@ios_base@std@@QEAA_J_J@Z + +; 812 : _Ostr.setstate(_State); + + 003c5 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 003cc 48 8b 00 mov rax, QWORD PTR [rax] + 003cf 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 003d3 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 003da 48 03 c8 add rcx, rax + 003dd 48 8b c1 mov rax, rcx + 003e0 48 89 85 08 02 + 00 00 mov QWORD PTR tv295[rbp], rax + 003e7 45 33 c0 xor r8d, r8d + 003ea 8b 55 04 mov edx, DWORD PTR _State$[rbp] + 003ed 48 8b 8d 08 02 + 00 00 mov rcx, QWORD PTR tv295[rbp] + 003f4 ff 15 00 00 00 + 00 call QWORD PTR __imp_?setstate@?$basic_ios@DU?$char_traits@D@std@@@std@@QEAAXH_N@Z + +; 813 : return _Ostr; + + 003fa 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 00401 48 89 85 f8 01 + 00 00 mov QWORD PTR $T11[rbp], rax + 00408 48 8d 4d 28 lea rcx, QWORD PTR _Ok$[rbp] + 0040c e8 00 00 00 00 call ??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::sentry::~sentry + 00411 48 8b 85 f8 01 + 00 00 mov rax, QWORD PTR $T11[rbp] + +; 814 : } + + 00418 48 8b f8 mov rdi, rax + 0041b 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] + 0041f 48 8d 15 00 00 + 00 00 lea rdx, OFFSET FLAT:??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$rtcFrameData + 00426 e8 00 00 00 00 call _RTC_CheckStackVars + 0042b 48 8b c7 mov rax, rdi + 0042e 48 8b 8d 20 02 + 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] + 00435 48 33 cd xor rcx, rbp + 00438 e8 00 00 00 00 call __security_check_cookie + 0043d 48 8d a5 38 02 + 00 00 lea rsp, QWORD PTR [rbp+568] + 00444 5f pop rdi + 00445 5d pop rbp + 00446 c3 ret 0 +??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z ENDP ; std::operator<< > +_TEXT ENDS ; COMDAT text$x text$x SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main$dtor$1 PROC +_State$ = 4 +_Ok$ = 40 +_Pad$4 = 88 +$T5 = 308 +$T6 = 340 +$T7 = 372 +$T8 = 404 +$T9 = 436 +$T10 = 468 +$T11 = 504 +tv65 = 516 +tv305 = 520 +tv303 = 520 +tv300 = 520 +tv295 = 520 +tv281 = 520 +tv266 = 520 +tv130 = 520 +tv245 = 528 +tv204 = 528 +tv179 = 528 +tv306 = 536 +tv304 = 536 +tv301 = 536 +tv243 = 537 +tv177 = 537 +tv307 = 540 +tv302 = 540 +__$ArrayPad$ = 544 +_Ostr$ = 592 +_Ch$ = 600 +?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA PROC ; `std::operator<< >'::`1'::dtor$0 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 0000a 55 push rbp 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 48 8d 4d 58 lea rcx, QWORD PTR NotTaken$[rbp] - 00018 e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ + 00014 48 8d 4d 28 lea rcx, QWORD PTR _Ok$[rbp] + 00018 e8 00 00 00 00 call ??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::sentry::~sentry 0001d 48 83 c4 28 add rsp, 40 ; 00000028H 00021 5f pop rdi 00022 5d pop rbp 00023 c3 ret 0 -main$dtor$1 ENDP -text$x ENDS -; COMDAT text$x -text$x SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main$dtor$2 PROC - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 0000a 55 push rbp - 0000b 57 push rdi - 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H - 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 48 8d 8d a8 00 - 00 00 lea rcx, QWORD PTR Taken$[rbp] - 0001b e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 00020 48 83 c4 28 add rsp, 40 ; 00000028H - 00024 5f pop rdi - 00025 5d pop rbp - 00026 c3 ret 0 -main$dtor$2 ENDP +?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA ENDP ; `std::operator<< >'::`1'::dtor$0 text$x ENDS -; Function compile flags: /Odtp /RTCsu /ZI ; COMDAT text$x text$x SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main$dtor$0 PROC +_State$ = 4 +_Ok$ = 40 +_Pad$4 = 88 +$T5 = 308 +$T6 = 340 +$T7 = 372 +$T8 = 404 +$T9 = 436 +$T10 = 468 +$T11 = 504 +tv65 = 516 +tv305 = 520 +tv303 = 520 +tv300 = 520 +tv295 = 520 +tv281 = 520 +tv266 = 520 +tv130 = 520 +tv245 = 528 +tv204 = 528 +tv179 = 528 +tv306 = 536 +tv304 = 536 +tv301 = 536 +tv243 = 537 +tv177 = 537 +tv307 = 540 +tv302 = 540 +__$ArrayPad$ = 544 +_Ostr$ = 592 +_Ch$ = 600 +?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA PROC ; `std::operator<< >'::`1'::catch$1 + +; 808 : _CATCH_IO_(ios_base, _Ostr) + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 0000a 55 push rbp 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 48 8d 4d 08 lea rcx, QWORD PTR Block$[rbp] - 00018 e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 0001d 48 83 c4 28 add rsp, 40 ; 00000028H - 00021 5f pop rdi - 00022 5d pop rbp - 00023 c3 ret 0 -main$dtor$0 ENDP +__catch$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$0: + 00014 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 0001b 48 8b 00 mov rax, QWORD PTR [rax] + 0001e 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00022 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00029 48 03 c8 add rcx, rax + 0002c 48 8b c1 mov rax, rcx + 0002f 48 89 85 08 02 + 00 00 mov QWORD PTR tv266[rbp], rax + 00036 41 b0 01 mov r8b, 1 + 00039 ba 04 00 00 00 mov edx, 4 + 0003e 48 8b 8d 08 02 + 00 00 mov rcx, QWORD PTR tv266[rbp] + 00045 ff 15 00 00 00 + 00 call QWORD PTR __imp_?setstate@?$basic_ios@DU?$char_traits@D@std@@@std@@QEAAXH_N@Z + 0004b 90 npad 1 + 0004c 48 8d 05 00 00 + 00 00 lea rax, $LN21@catch$1 + 00053 48 83 c4 28 add rsp, 40 ; 00000028H + 00057 5f pop rdi + 00058 5d pop rbp + 00059 c3 ret 0 + 0005a cc int 3 +?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA ENDP ; `std::operator<< >'::`1'::catch$1 text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; COMDAT text$x text$x SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main$dtor$1 PROC +_State$ = 4 +_Ok$ = 40 +_Pad$4 = 88 +$T5 = 308 +$T6 = 340 +$T7 = 372 +$T8 = 404 +$T9 = 436 +$T10 = 468 +$T11 = 504 +tv65 = 516 +tv305 = 520 +tv303 = 520 +tv300 = 520 +tv295 = 520 +tv281 = 520 +tv266 = 520 +tv130 = 520 +tv245 = 528 +tv204 = 528 +tv179 = 528 +tv306 = 536 +tv304 = 536 +tv301 = 536 +tv243 = 537 +tv177 = 537 +tv307 = 540 +tv302 = 540 +__$ArrayPad$ = 544 +_Ostr$ = 592 +_Ch$ = 600 +?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA PROC ; `std::operator<< >'::`1'::dtor$0 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 0000a 55 push rbp 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 48 8d 4d 58 lea rcx, QWORD PTR NotTaken$[rbp] - 00018 e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ + 00014 48 8d 4d 28 lea rcx, QWORD PTR _Ok$[rbp] + 00018 e8 00 00 00 00 call ??1sentry@?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAA@XZ ; std::basic_ostream >::sentry::~sentry 0001d 48 83 c4 28 add rsp, 40 ; 00000028H 00021 5f pop rdi 00022 5d pop rbp 00023 c3 ret 0 -main$dtor$1 ENDP +?dtor$0@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA ENDP ; `std::operator<< >'::`1'::dtor$0 text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; COMDAT text$x text$x SEGMENT -Block$ = 8 -NotTaken$ = 88 -Taken$ = 168 -tv135 = 420 -tv133 = 424 -__$ArrayPad$ = 432 -main$dtor$2 PROC +_State$ = 4 +_Ok$ = 40 +_Pad$4 = 88 +$T5 = 308 +$T6 = 340 +$T7 = 372 +$T8 = 404 +$T9 = 436 +$T10 = 468 +$T11 = 504 +tv65 = 516 +tv305 = 520 +tv303 = 520 +tv300 = 520 +tv295 = 520 +tv281 = 520 +tv266 = 520 +tv130 = 520 +tv245 = 528 +tv204 = 528 +tv179 = 528 +tv306 = 536 +tv304 = 536 +tv301 = 536 +tv243 = 537 +tv177 = 537 +tv307 = 540 +tv302 = 540 +__$ArrayPad$ = 544 +_Ostr$ = 592 +_Ch$ = 600 +?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA PROC ; `std::operator<< >'::`1'::catch$1 + +; 808 : _CATCH_IO_(ios_base, _Ostr) + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 0000a 55 push rbp 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 48 8d 8d a8 00 - 00 00 lea rcx, QWORD PTR Taken$[rbp] - 0001b e8 00 00 00 00 call ??1_NATIVE_CODE_BLOCK@@QEAA@XZ - 00020 48 83 c4 28 add rsp, 40 ; 00000028H - 00024 5f pop rdi - 00025 5d pop rbp - 00026 c3 ret 0 -main$dtor$2 ENDP +__catch$??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z$0: + 00014 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR _Ostr$[rbp] + 0001b 48 8b 00 mov rax, QWORD PTR [rax] + 0001e 48 63 40 04 movsxd rax, DWORD PTR [rax+4] + 00022 48 8b 8d 50 02 + 00 00 mov rcx, QWORD PTR _Ostr$[rbp] + 00029 48 03 c8 add rcx, rax + 0002c 48 8b c1 mov rax, rcx + 0002f 48 89 85 08 02 + 00 00 mov QWORD PTR tv266[rbp], rax + 00036 41 b0 01 mov r8b, 1 + 00039 ba 04 00 00 00 mov edx, 4 + 0003e 48 8b 8d 08 02 + 00 00 mov rcx, QWORD PTR tv266[rbp] + 00045 ff 15 00 00 00 + 00 call QWORD PTR __imp_?setstate@?$basic_ios@DU?$char_traits@D@std@@@std@@QEAAXH_N@Z + 0004b 90 npad 1 + 0004c 48 8d 05 00 00 + 00 00 lea rax, $LN21@catch$1 + 00053 48 83 c4 28 add rsp, 40 ; 00000028H + 00057 5f pop rdi + 00058 5d pop rbp + 00059 c3 ret 0 + 0005a cc int 3 +?catch$1@?0???$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z@4HA ENDP ; `std::operator<< >'::`1'::catch$1 text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File C:\$Fanta\code-virtualizer\CodeVirtualizer\Main.cpp -; COMDAT ?MakeExecutableBuffer@@YAPEAXPEAXK@Z +; COMDAT main _TEXT SEGMENT -ExecBuffer$ = 8 -Buffer$ = 256 -BufferSize$ = 264 -?MakeExecutableBuffer@@YAPEAXPEAXK@Z PROC ; MakeExecutableBuffer, COMDAT +Return1776$ = 8 +RetInst$ = 40 +Pre1$ = 72 +Post1$ = 104 +Pre2$ = 136 +Post2$ = 168 +i$4 = 196 +i$5 = 228 +AsmLen$ = 260 +Asm$ = 296 +Tb$ = 328 +i$6 = 356 +ExecBuffer$ = 392 +$T7 = 808 +$T8 = 840 +$T9 = 872 +$T10 = 904 +$T11 = 932 +$T12 = 968 +tv179 = 996 +tv168 = 996 +tv202 = 1000 +tv130 = 1000 +tv83 = 1000 +tv204 = 1008 +tv207 = 1016 +tv209 = 1024 +tv220 = 1032 +tv218 = 1040 +__$ArrayPad$ = 1048 +main PROC ; COMDAT -; 14 : { +; 44 : { -$LN4: - 00000 89 54 24 10 mov DWORD PTR [rsp+16], edx - 00004 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00009 55 push rbp - 0000a 57 push rdi - 0000b 48 81 ec 08 01 - 00 00 sub rsp, 264 ; 00000108H - 00012 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00017 48 8b fc mov rdi, rsp - 0001a b9 42 00 00 00 mov ecx, 66 ; 00000042H - 0001f b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00024 f3 ab rep stosd - 00026 48 8b 8c 24 28 - 01 00 00 mov rcx, QWORD PTR [rsp+296] - 0002e 48 8d 0d 00 00 +$LN19: + 00000 40 55 push rbp + 00002 57 push rdi + 00003 48 81 ec 58 04 + 00 00 sub rsp, 1112 ; 00000458H + 0000a 48 8d 6c 24 30 lea rbp, QWORD PTR [rsp+48] + 0000f 48 8b fc mov rdi, rsp + 00012 b9 16 01 00 00 mov ecx, 278 ; 00000116H + 00017 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 0001c f3 ab rep stosd + 0001e 48 8b 05 00 00 + 00 00 mov rax, QWORD PTR __security_cookie + 00025 48 33 c5 xor rax, rbp + 00028 48 89 85 18 04 + 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax + 0002f 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__4031338C_Main@cpp - 00035 e8 00 00 00 00 call __CheckForDebuggerJustMyCode - -; 15 : PVOID ExecBuffer = VirtualAlloc(nullptr, BufferSize, MEM_COMMIT, PAGE_EXECUTE_READWRITE); - - 0003a 8b 85 08 01 00 - 00 mov eax, DWORD PTR BufferSize$[rbp] - 00040 41 b9 40 00 00 - 00 mov r9d, 64 ; 00000040H - 00046 41 b8 00 10 00 - 00 mov r8d, 4096 ; 00001000H - 0004c 8b d0 mov edx, eax - 0004e 33 c9 xor ecx, ecx - 00050 ff 15 00 00 00 - 00 call QWORD PTR __imp_VirtualAlloc - 00056 48 89 45 08 mov QWORD PTR ExecBuffer$[rbp], rax - -; 16 : if (!ExecBuffer) - - 0005a 48 83 7d 08 00 cmp QWORD PTR ExecBuffer$[rbp], 0 - 0005f 75 04 jne SHORT $LN2@MakeExecut - -; 17 : return NULL; - - 00061 33 c0 xor eax, eax - 00063 eb 19 jmp SHORT $LN1@MakeExecut -$LN2@MakeExecut: - -; 18 : RtlCopyMemory(ExecBuffer, Buffer, BufferSize); - - 00065 8b 85 08 01 00 - 00 mov eax, DWORD PTR BufferSize$[rbp] - 0006b 44 8b c0 mov r8d, eax - 0006e 48 8b 95 00 01 - 00 00 mov rdx, QWORD PTR Buffer$[rbp] - 00075 48 8b 4d 08 mov rcx, QWORD PTR ExecBuffer$[rbp] - 00079 e8 00 00 00 00 call memcpy -$LN1@MakeExecut: - -; 19 : } - - 0007e 48 8d a5 e8 00 - 00 00 lea rsp, QWORD PTR [rbp+232] - 00085 5f pop rdi - 00086 5d pop rbp - 00087 c3 ret 0 -?MakeExecutableBuffer@@YAPEAXPEAXK@Z ENDP ; MakeExecutableBuffer -_TEXT ENDS -; Function compile flags: /Odtp /RTCsu /ZI -; COMDAT ??1_NATIVE_CODE_BLOCK@@QEAA@XZ -_TEXT SEGMENT -this$ = 224 -??1_NATIVE_CODE_BLOCK@@QEAA@XZ PROC ; _NATIVE_CODE_BLOCK::~_NATIVE_CODE_BLOCK, COMDAT -$LN3: - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 55 push rbp - 00006 57 push rdi - 00007 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00013 48 8b fc mov rdi, rsp - 00016 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00020 f3 ab rep stosd - 00022 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 0002a 48 8b 85 e0 00 - 00 00 mov rax, QWORD PTR this$[rbp] - 00031 48 83 c0 10 add rax, 16 - 00035 48 8b c8 mov rcx, rax - 00038 e8 00 00 00 00 call ??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ ; std::vector >::~vector > - 0003d 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00044 5f pop rdi - 00045 5d pop rbp - 00046 c3 ret 0 -??1_NATIVE_CODE_BLOCK@@QEAA@XZ ENDP ; _NATIVE_CODE_BLOCK::~_NATIVE_CODE_BLOCK -_TEXT ENDS -; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ -_TEXT SEGMENT -this$ = 224 -?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ PROC ; std::_Compressed_pair,std::_Vector_val >,1>::_Get_first, COMDAT - -; 1343 : constexpr _Ty1& _Get_first() noexcept { - -$LN3: - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 55 push rbp - 00006 57 push rdi - 00007 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00013 48 8b fc mov rdi, rsp - 00016 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00020 f3 ab rep stosd - 00022 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 0002a 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode - -; 1344 : return *this; - - 00036 48 8b 85 e0 00 - 00 00 mov rax, QWORD PTR this$[rbp] - -; 1345 : } - - 0003d 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00044 5f pop rdi - 00045 5d pop rbp - 00046 c3 ret 0 -?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ ENDP ; std::_Compressed_pair,std::_Vector_val >,1>::_Get_first -_TEXT ENDS -; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\vector -; COMDAT ?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ -_TEXT SEGMENT -this$ = 224 -?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ PROC ; std::vector >::_Getal, COMDAT - -; 1731 : _Alty& _Getal() noexcept { - -$LN3: - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 55 push rbp - 00006 57 push rdi - 00007 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00013 48 8b fc mov rdi, rsp - 00016 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00020 f3 ab rep stosd - 00022 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 0002a 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__BF2A7ACC_vector - 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode - -; 1732 : return _Mypair._Get_first(); - - 00036 48 8b 85 e0 00 - 00 00 mov rax, QWORD PTR this$[rbp] - 0003d 48 8b c8 mov rcx, rax - 00040 e8 00 00 00 00 call ?_Get_first@?$_Compressed_pair@V?$allocator@K@std@@V?$_Vector_val@U?$_Simple_types@K@std@@@2@$00@std@@QEAAAEAV?$allocator@K@2@XZ ; std::_Compressed_pair,std::_Vector_val >,1>::_Get_first - 00045 90 npad 1 - -; 1733 : } - - 00046 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 0004d 5f pop rdi - 0004e 5d pop rbp - 0004f c3 ret 0 -?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ ENDP ; std::vector >::_Getal -_TEXT ENDS -; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\vector -; COMDAT ?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ -_TEXT SEGMENT -_My_data$ = 8 -_Myfirst$ = 40 -_Mylast$ = 72 -_Myend$ = 104 -tv90 = 312 -tv88 = 320 -tv86 = 328 -this$ = 368 -?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ PROC ; std::vector >::_Tidy, COMDAT - -; 1685 : void _Tidy() noexcept { // free all storage - -$LN4: - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 55 push rbp - 00006 57 push rdi - 00007 48 81 ec 78 01 - 00 00 sub rsp, 376 ; 00000178H - 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00013 48 8b fc mov rdi, rsp - 00016 b9 5e 00 00 00 mov ecx, 94 ; 0000005eH - 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00020 f3 ab rep stosd - 00022 48 8b 8c 24 98 - 01 00 00 mov rcx, QWORD PTR [rsp+408] - 0002a 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__BF2A7ACC_vector - 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode - -; 1686 : auto& _My_data = _Mypair._Myval2; - - 00036 48 8b 85 70 01 - 00 00 mov rax, QWORD PTR this$[rbp] - 0003d 48 89 45 08 mov QWORD PTR _My_data$[rbp], rax - -; 1687 : pointer& _Myfirst = _My_data._Myfirst; - - 00041 48 8b 45 08 mov rax, QWORD PTR _My_data$[rbp] - 00045 48 83 c0 08 add rax, 8 - 00049 48 89 45 28 mov QWORD PTR _Myfirst$[rbp], rax - -; 1688 : pointer& _Mylast = _My_data._Mylast; - - 0004d 48 8b 45 08 mov rax, QWORD PTR _My_data$[rbp] - 00051 48 83 c0 10 add rax, 16 - 00055 48 89 45 48 mov QWORD PTR _Mylast$[rbp], rax - -; 1689 : pointer& _Myend = _My_data._Myend; - - 00059 48 8b 45 08 mov rax, QWORD PTR _My_data$[rbp] - 0005d 48 83 c0 18 add rax, 24 - 00061 48 89 45 68 mov QWORD PTR _Myend$[rbp], rax - -; 1690 : -; 1691 : _My_data._Orphan_all(); - - 00065 48 8b 4d 08 mov rcx, QWORD PTR _My_data$[rbp] - 00069 e8 00 00 00 00 call ?_Orphan_all@_Container_base12@std@@QEAAXXZ ; std::_Container_base12::_Orphan_all - -; 1692 : -; 1693 : if (_Myfirst) { // destroy and deallocate old array - - 0006e 48 8b 45 28 mov rax, QWORD PTR _Myfirst$[rbp] - 00072 48 83 38 00 cmp QWORD PTR [rax], 0 - 00076 0f 84 92 00 00 - 00 je $LN2@Tidy - -; 1694 : _Destroy(_Myfirst, _Mylast); + 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode - 0007c 48 8b 45 48 mov rax, QWORD PTR _Mylast$[rbp] - 00080 4c 8b 00 mov r8, QWORD PTR [rax] - 00083 48 8b 45 28 mov rax, QWORD PTR _Myfirst$[rbp] - 00087 48 8b 10 mov rdx, QWORD PTR [rax] - 0008a 48 8b 8d 70 01 - 00 00 mov rcx, QWORD PTR this$[rbp] - 00091 e8 00 00 00 00 call ?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z ; std::vector >::_Destroy +; 45 : XedTablesInit(); -; 1695 : _Getal().deallocate(_Myfirst, static_cast(_Myend - _Myfirst)); + 0003b e8 00 00 00 00 call xed_tables_init - 00096 48 8b 8d 70 01 - 00 00 mov rcx, QWORD PTR this$[rbp] - 0009d e8 00 00 00 00 call ?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ ; std::vector >::_Getal - 000a2 48 89 85 38 01 - 00 00 mov QWORD PTR tv90[rbp], rax - 000a9 48 8b 45 68 mov rax, QWORD PTR _Myend$[rbp] - 000ad 48 8b 4d 28 mov rcx, QWORD PTR _Myfirst$[rbp] - 000b1 48 8b 09 mov rcx, QWORD PTR [rcx] - 000b4 48 8b 00 mov rax, QWORD PTR [rax] - 000b7 48 2b c1 sub rax, rcx - 000ba 48 c1 f8 02 sar rax, 2 - 000be 48 89 85 40 01 - 00 00 mov QWORD PTR tv88[rbp], rax - 000c5 48 8b 45 28 mov rax, QWORD PTR _Myfirst$[rbp] - 000c9 48 8b 00 mov rax, QWORD PTR [rax] - 000cc 48 89 85 48 01 - 00 00 mov QWORD PTR tv86[rbp], rax - 000d3 4c 8b 85 40 01 - 00 00 mov r8, QWORD PTR tv88[rbp] - 000da 48 8b 95 48 01 - 00 00 mov rdx, QWORD PTR tv86[rbp] - 000e1 48 8b 8d 38 01 - 00 00 mov rcx, QWORD PTR tv90[rbp] - 000e8 e8 00 00 00 00 call ?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z ; std::allocator::deallocate - -; 1696 : -; 1697 : _Myfirst = pointer(); - - 000ed 48 8b 45 28 mov rax, QWORD PTR _Myfirst$[rbp] - 000f1 48 c7 00 00 00 - 00 00 mov QWORD PTR [rax], 0 - -; 1698 : _Mylast = pointer(); - - 000f8 48 8b 45 48 mov rax, QWORD PTR _Mylast$[rbp] - 000fc 48 c7 00 00 00 - 00 00 mov QWORD PTR [rax], 0 - -; 1699 : _Myend = pointer(); - - 00103 48 8b 45 68 mov rax, QWORD PTR _Myend$[rbp] - 00107 48 c7 00 00 00 - 00 00 mov QWORD PTR [rax], 0 -$LN2@Tidy: - -; 1700 : } -; 1701 : } - - 0010e 48 8d a5 58 01 - 00 00 lea rsp, QWORD PTR [rbp+344] - 00115 5f pop rdi - 00116 5d pop rbp - 00117 c3 ret 0 -?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ ENDP ; std::vector >::_Tidy -_TEXT ENDS -; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\vector -; COMDAT ?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z -_TEXT SEGMENT -this$ = 224 -_First$ = 232 -_Last$ = 240 -?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z PROC ; std::vector >::_Destroy, COMDAT +; 46 : srand(time(NULL)); -; 1611 : void _Destroy(pointer _First, pointer _Last) { // destroy [_First, _Last) using allocator + 00040 33 c9 xor ecx, ecx + 00042 e8 00 00 00 00 call time + 00047 8b c8 mov ecx, eax + 00049 ff 15 00 00 00 + 00 call QWORD PTR __imp_srand -$LN3: - 00000 4c 89 44 24 18 mov QWORD PTR [rsp+24], r8 - 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 0000a 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 0000f 55 push rbp - 00010 57 push rdi - 00011 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 00018 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 0001d 48 8b fc mov rdi, rsp - 00020 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 00025 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 0002a f3 ab rep stosd - 0002c 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 00034 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__BF2A7ACC_vector - 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode +; 47 : +; 48 : +; 49 : //NATIVE_CODE_BLOCK Block; +; 50 : //NcDisassemble(&Block, TestBuffer, TestBufferSize); +; 51 : //NATIVE_CODE_BLOCK NotTaken; +; 52 : //NATIVE_CODE_BLOCK Taken; +; 53 : //printf("\n\nOriginal\n"); +; 54 : //NcDebugPrint(&Block); +; 55 : //ObfCreateOpaqueBranches(Block.Start->Next, Block.Start->Next->Next->Next->Next, &NotTaken, &Taken); +; 56 : ////printf("\n\nNotTaken\n"); +; 57 : ////NcDebugPrint(&NotTaken); +; 58 : ////printf("\n\nTaken\n"); +; 59 : ////NcDebugPrint(&Taken); +; 60 : ////printf("\n\nCombined\n"); +; 61 : //ObfCombineOpaqueBranches(&NotTaken, &Taken, NcGenUnusedLabelId(&Block), NcGenUnusedLabelId(&Block)); +; 62 : //ObfInsertOpaqueBranchBlock(Block.Start->Next, Block.Start->Next->Next->Next->Next, &NotTaken); +; 63 : //printf("\n\nNew\n"); +; 64 : //NcDebugPrint(&Block); +; 65 : +; 66 : +; 67 : PNATIVE_CODE_LINK Return1776 = new NATIVE_CODE_LINK(CODE_FLAG_IS_INST, meme1, sizeof(meme1)); + + 0004f b9 f0 00 00 00 mov ecx, 240 ; 000000f0H + 00054 e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new + 00059 48 89 85 48 03 + 00 00 mov QWORD PTR $T8[rbp], rax + 00060 48 83 bd 48 03 + 00 00 00 cmp QWORD PTR $T8[rbp], 0 + 00068 74 2f je SHORT $LN13@main + 0006a c7 44 24 20 00 + 00 00 00 mov DWORD PTR [rsp+32], 0 + 00072 41 b9 05 00 00 + 00 mov r9d, 5 + 00078 4c 8d 05 00 00 + 00 00 lea r8, OFFSET FLAT:?meme1@@3PAEA ; meme1 + 0007f ba 04 00 00 00 mov edx, 4 + 00084 48 8b 8d 48 03 + 00 00 mov rcx, QWORD PTR $T8[rbp] + 0008b e8 00 00 00 00 call ??0_NATIVE_CODE_LINK@@QEAA@KPEAXKH@Z ; _NATIVE_CODE_LINK::_NATIVE_CODE_LINK + 00090 48 89 85 e8 03 + 00 00 mov QWORD PTR tv83[rbp], rax + 00097 eb 0b jmp SHORT $LN14@main +$LN13@main: + 00099 48 c7 85 e8 03 + 00 00 00 00 00 + 00 mov QWORD PTR tv83[rbp], 0 +$LN14@main: + 000a4 48 8b 85 e8 03 + 00 00 mov rax, QWORD PTR tv83[rbp] + 000ab 48 89 85 28 03 + 00 00 mov QWORD PTR $T7[rbp], rax + 000b2 48 8b 85 28 03 + 00 00 mov rax, QWORD PTR $T7[rbp] + 000b9 48 89 45 08 mov QWORD PTR Return1776$[rbp], rax + +; 68 : PNATIVE_CODE_LINK RetInst = new NATIVE_CODE_LINK(CODE_FLAG_IS_INST, meme2, sizeof(meme2)); + + 000bd b9 f0 00 00 00 mov ecx, 240 ; 000000f0H + 000c2 e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new + 000c7 48 89 85 88 03 + 00 00 mov QWORD PTR $T10[rbp], rax + 000ce 48 83 bd 88 03 + 00 00 00 cmp QWORD PTR $T10[rbp], 0 + 000d6 74 2f je SHORT $LN15@main + 000d8 c7 44 24 20 00 + 00 00 00 mov DWORD PTR [rsp+32], 0 + 000e0 41 b9 01 00 00 + 00 mov r9d, 1 + 000e6 4c 8d 05 00 00 + 00 00 lea r8, OFFSET FLAT:?meme2@@3PAEA ; meme2 + 000ed ba 04 00 00 00 mov edx, 4 + 000f2 48 8b 8d 88 03 + 00 00 mov rcx, QWORD PTR $T10[rbp] + 000f9 e8 00 00 00 00 call ??0_NATIVE_CODE_LINK@@QEAA@KPEAXKH@Z ; _NATIVE_CODE_LINK::_NATIVE_CODE_LINK + 000fe 48 89 85 e8 03 + 00 00 mov QWORD PTR tv130[rbp], rax + 00105 eb 0b jmp SHORT $LN16@main +$LN15@main: + 00107 48 c7 85 e8 03 + 00 00 00 00 00 + 00 mov QWORD PTR tv130[rbp], 0 +$LN16@main: + 00112 48 8b 85 e8 03 + 00 00 mov rax, QWORD PTR tv130[rbp] + 00119 48 89 85 68 03 + 00 00 mov QWORD PTR $T9[rbp], rax + 00120 48 8b 85 68 03 + 00 00 mov rax, QWORD PTR $T9[rbp] + 00127 48 89 45 28 mov QWORD PTR RetInst$[rbp], rax + +; 69 : PNATIVE_CODE_BLOCK Pre1 = JitEmitPreRipMov(Return1776); + + 0012b 33 d2 xor edx, edx + 0012d 48 8b 4d 08 mov rcx, QWORD PTR Return1776$[rbp] + 00131 e8 00 00 00 00 call ?JitEmitPreRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z ; JitEmitPreRipMov + 00136 48 89 45 48 mov QWORD PTR Pre1$[rbp], rax + +; 70 : PNATIVE_CODE_BLOCK Post1 = JitEmitPostRipMov(Return1776); + + 0013a 33 d2 xor edx, edx + 0013c 48 8b 4d 08 mov rcx, QWORD PTR Return1776$[rbp] + 00140 e8 00 00 00 00 call ?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z ; JitEmitPostRipMov + 00145 48 89 45 68 mov QWORD PTR Post1$[rbp], rax + +; 71 : PNATIVE_CODE_BLOCK Pre2 = JitEmitPreRipMov(RetInst); + + 00149 33 d2 xor edx, edx + 0014b 48 8b 4d 28 mov rcx, QWORD PTR RetInst$[rbp] + 0014f e8 00 00 00 00 call ?JitEmitPreRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z ; JitEmitPreRipMov + 00154 48 89 85 88 00 + 00 00 mov QWORD PTR Pre2$[rbp], rax + +; 72 : PNATIVE_CODE_BLOCK Post2 = JitEmitPostRipMov(RetInst); + + 0015b 33 d2 xor edx, edx + 0015d 48 8b 4d 28 mov rcx, QWORD PTR RetInst$[rbp] + 00161 e8 00 00 00 00 call ?JitEmitPostRipMov@@YAPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@H@Z ; JitEmitPostRipMov + 00166 48 89 85 a8 00 + 00 00 mov QWORD PTR Post2$[rbp], rax -; 1612 : _Destroy_range(_First, _Last, _Getal()); +; 73 : +; 74 : NcAppendToBlock(Pre1, Return1776); - 00040 48 8b 8d e0 00 - 00 00 mov rcx, QWORD PTR this$[rbp] - 00047 e8 00 00 00 00 call ?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ ; std::vector >::_Getal - 0004c 4c 8b c0 mov r8, rax - 0004f 48 8b 95 f0 00 - 00 00 mov rdx, QWORD PTR _Last$[rbp] - 00056 48 8b 8d e8 00 - 00 00 mov rcx, QWORD PTR _First$[rbp] - 0005d e8 00 00 00 00 call ??$_Destroy_range@V?$allocator@K@std@@@std@@YAXPEAKQEAKAEAV?$allocator@K@0@@Z ; std::_Destroy_range > + 0016d 48 8b 55 08 mov rdx, QWORD PTR Return1776$[rbp] + 00171 48 8b 4d 48 mov rcx, QWORD PTR Pre1$[rbp] + 00175 e8 00 00 00 00 call ?NcAppendToBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@@Z ; NcAppendToBlock -; 1613 : } +; 75 : NcInsertBlockAfter(Pre1->End, Post1, 0); - 00062 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00069 5f pop rdi - 0006a 5d pop rbp - 0006b c3 ret 0 -?_Destroy@?$vector@KV?$allocator@K@std@@@std@@AEAAXPEAK0@Z ENDP ; std::vector >::_Destroy -_TEXT ENDS -; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\vector -; COMDAT ??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ -_TEXT SEGMENT -_Alproxy$ = 8 -$S1$ = 36 -$T4 = 260 -__$ArrayPad$ = 280 -this$ = 320 -??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ PROC ; std::vector >::~vector >, COMDAT + 0017a 45 33 c0 xor r8d, r8d + 0017d 48 8b 55 68 mov rdx, QWORD PTR Post1$[rbp] + 00181 48 8b 45 48 mov rax, QWORD PTR Pre1$[rbp] + 00185 48 8b 48 08 mov rcx, QWORD PTR [rax+8] + 00189 e8 00 00 00 00 call ?NcInsertBlockAfter@@YAHPEAU_NATIVE_CODE_LINK@@PEAU_NATIVE_CODE_BLOCK@@H@Z ; NcInsertBlockAfter -; 672 : ~vector() noexcept { +; 76 : Pre1->End = Post1->End; -$LN3: - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 55 push rbp - 00006 57 push rdi - 00007 48 81 ec 48 01 - 00 00 sub rsp, 328 ; 00000148H - 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00013 48 8b fc mov rdi, rsp - 00016 b9 52 00 00 00 mov ecx, 82 ; 00000052H - 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00020 f3 ab rep stosd - 00022 48 8b 8c 24 68 - 01 00 00 mov rcx, QWORD PTR [rsp+360] - 0002a 48 8b 05 00 00 - 00 00 mov rax, QWORD PTR __security_cookie - 00031 48 33 c5 xor rax, rbp - 00034 48 89 85 18 01 - 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax - 0003b 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__BF2A7ACC_vector - 00042 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + 0018e 48 8b 45 48 mov rax, QWORD PTR Pre1$[rbp] + 00192 48 8b 4d 68 mov rcx, QWORD PTR Post1$[rbp] + 00196 48 8b 49 08 mov rcx, QWORD PTR [rcx+8] + 0019a 48 89 48 08 mov QWORD PTR [rax+8], rcx -; 673 : _Tidy(); +; 77 : NcInsertBlockAfter(Pre1->End, Pre2, 0); - 00047 48 8b 8d 40 01 - 00 00 mov rcx, QWORD PTR this$[rbp] - 0004e e8 00 00 00 00 call ?_Tidy@?$vector@KV?$allocator@K@std@@@std@@AEAAXXZ ; std::vector >::_Tidy + 0019e 45 33 c0 xor r8d, r8d + 001a1 48 8b 95 88 00 + 00 00 mov rdx, QWORD PTR Pre2$[rbp] + 001a8 48 8b 45 48 mov rax, QWORD PTR Pre1$[rbp] + 001ac 48 8b 48 08 mov rcx, QWORD PTR [rax+8] + 001b0 e8 00 00 00 00 call ?NcInsertBlockAfter@@YAHPEAU_NATIVE_CODE_LINK@@PEAU_NATIVE_CODE_BLOCK@@H@Z ; NcInsertBlockAfter -; 674 : #if _ITERATOR_DEBUG_LEVEL != 0 -; 675 : auto&& _Alproxy = _GET_PROXY_ALLOCATOR(_Alty, _Getal()); +; 78 : Pre1->End = Pre2->End; - 00053 48 8b 8d 40 01 - 00 00 mov rcx, QWORD PTR this$[rbp] - 0005a e8 00 00 00 00 call ?_Getal@?$vector@KV?$allocator@K@std@@@std@@AEAAAEAV?$allocator@K@2@XZ ; std::vector >::_Getal - 0005f 48 8b d0 mov rdx, rax - 00062 48 8d 4d 24 lea rcx, QWORD PTR $S1$[rbp] - 00066 e8 00 00 00 00 call ??$?0K@?$allocator@U_Container_proxy@std@@@std@@QEAA@AEBV?$allocator@K@1@@Z ; std::allocator::allocator - 0006b 48 8d 45 24 lea rax, QWORD PTR $S1$[rbp] - 0006f 48 89 45 08 mov QWORD PTR _Alproxy$[rbp], rax + 001b5 48 8b 45 48 mov rax, QWORD PTR Pre1$[rbp] + 001b9 48 8b 8d 88 00 + 00 00 mov rcx, QWORD PTR Pre2$[rbp] + 001c0 48 8b 49 08 mov rcx, QWORD PTR [rcx+8] + 001c4 48 89 48 08 mov QWORD PTR [rax+8], rcx -; 676 : _Delete_plain_internal(_Alproxy, _STD exchange(_Mypair._Myval2._Myproxy, nullptr)); +; 79 : NcAppendToBlock(Pre1, RetInst);/* - 00073 48 c7 85 04 01 - 00 00 00 00 00 - 00 mov QWORD PTR $T4[rbp], 0 - 0007e 48 8b 85 40 01 - 00 00 mov rax, QWORD PTR this$[rbp] - 00085 48 8d 95 04 01 - 00 00 lea rdx, QWORD PTR $T4[rbp] - 0008c 48 8b c8 mov rcx, rax - 0008f e8 00 00 00 00 call ??$exchange@PEAU_Container_proxy@std@@$$T@std@@YAPEAU_Container_proxy@0@AEAPEAU10@$$QEA$$T@Z ; std::exchange - 00094 48 8b d0 mov rdx, rax - 00097 48 8b 4d 08 mov rcx, QWORD PTR _Alproxy$[rbp] - 0009b e8 00 00 00 00 call ??$_Delete_plain_internal@V?$allocator@U_Container_proxy@std@@@std@@@std@@YAXAEAV?$allocator@U_Container_proxy@std@@@0@QEAU_Container_proxy@0@@Z ; std::_Delete_plain_internal > - -; 677 : #endif // _ITERATOR_DEBUG_LEVEL != 0 -; 678 : } - - 000a0 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] - 000a4 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ$rtcFrameData - 000ab e8 00 00 00 00 call _RTC_CheckStackVars - 000b0 90 npad 1 - 000b1 48 8b 8d 18 01 + 001c8 48 8b 55 28 mov rdx, QWORD PTR RetInst$[rbp] + 001cc 48 8b 4d 48 mov rcx, QWORD PTR Pre1$[rbp] + 001d0 e8 00 00 00 00 call ?NcAppendToBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@@Z ; NcAppendToBlock + +; 80 : NcInsertBlockAfter(Pre1->End, Post2, 0); +; 81 : Pre1->End = Post2->End;*/ +; 82 : +; 83 : /*Pre->Start = Return1776; +; 84 : Pre->End = Return1776;*/ +; 85 : +; 86 : for (ULONG i = 0; i < Return1776->RawDataSize; i++) + + 001d5 c7 85 c4 00 00 + 00 00 00 00 00 mov DWORD PTR i$4[rbp], 0 + 001df eb 0e jmp SHORT $LN4@main +$LN2@main: + 001e1 8b 85 c4 00 00 + 00 mov eax, DWORD PTR i$4[rbp] + 001e7 ff c0 inc eax + 001e9 89 85 c4 00 00 + 00 mov DWORD PTR i$4[rbp], eax +$LN4@main: + 001ef 48 8b 45 08 mov rax, QWORD PTR Return1776$[rbp] + 001f3 8b 40 28 mov eax, DWORD PTR [rax+40] + 001f6 39 85 c4 00 00 + 00 cmp DWORD PTR i$4[rbp], eax + 001fc 73 26 jae SHORT $LN3@main + +; 87 : Return1776->RawData[i] = (UCHAR)rand(); + + 001fe ff 15 00 00 00 + 00 call QWORD PTR __imp_rand + 00204 88 85 e4 03 00 + 00 mov BYTE PTR tv168[rbp], al + 0020a 8b 85 c4 00 00 + 00 mov eax, DWORD PTR i$4[rbp] + 00210 48 8b 4d 08 mov rcx, QWORD PTR Return1776$[rbp] + 00214 48 8b 49 20 mov rcx, QWORD PTR [rcx+32] + 00218 0f b6 95 e4 03 + 00 00 movzx edx, BYTE PTR tv168[rbp] + 0021f 88 14 01 mov BYTE PTR [rcx+rax], dl + 00222 eb bd jmp SHORT $LN2@main +$LN3@main: + +; 88 : for (ULONG i = 0; i < RetInst->RawDataSize; i++) + + 00224 c7 85 e4 00 00 + 00 00 00 00 00 mov DWORD PTR i$5[rbp], 0 + 0022e eb 0e jmp SHORT $LN7@main +$LN5@main: + 00230 8b 85 e4 00 00 + 00 mov eax, DWORD PTR i$5[rbp] + 00236 ff c0 inc eax + 00238 89 85 e4 00 00 + 00 mov DWORD PTR i$5[rbp], eax +$LN7@main: + 0023e 48 8b 45 28 mov rax, QWORD PTR RetInst$[rbp] + 00242 8b 40 28 mov eax, DWORD PTR [rax+40] + 00245 39 85 e4 00 00 + 00 cmp DWORD PTR i$5[rbp], eax + 0024b 73 26 jae SHORT $LN6@main + +; 89 : RetInst->RawData[i] = (UCHAR)rand(); + + 0024d ff 15 00 00 00 + 00 call QWORD PTR __imp_rand + 00253 88 85 e4 03 00 + 00 mov BYTE PTR tv179[rbp], al + 00259 8b 85 e4 00 00 + 00 mov eax, DWORD PTR i$5[rbp] + 0025f 48 8b 4d 28 mov rcx, QWORD PTR RetInst$[rbp] + 00263 48 8b 49 20 mov rcx, QWORD PTR [rcx+32] + 00267 0f b6 95 e4 03 + 00 00 movzx edx, BYTE PTR tv179[rbp] + 0026e 88 14 01 mov BYTE PTR [rcx+rax], dl + 00271 eb bd jmp SHORT $LN5@main +$LN6@main: + +; 90 : +; 91 : ULONG AsmLen; +; 92 : PVOID Asm = NcAssemble(Pre1, &AsmLen); + + 00273 48 8d 95 04 01 + 00 00 lea rdx, QWORD PTR AsmLen$[rbp] + 0027a 48 8b 4d 48 mov rcx, QWORD PTR Pre1$[rbp] + 0027e e8 00 00 00 00 call ?NcAssemble@@YAPEAXPEAU_NATIVE_CODE_BLOCK@@PEAK@Z ; NcAssemble + 00283 48 89 85 28 01 + 00 00 mov QWORD PTR Asm$[rbp], rax + +; 93 : PUCHAR Tb = (PUCHAR)Asm; + + 0028a 48 8b 85 28 01 + 00 00 mov rax, QWORD PTR Asm$[rbp] + 00291 48 89 85 48 01 + 00 00 mov QWORD PTR Tb$[rbp], rax + +; 94 : for (uint32_t i = 0; i < AsmLen; i++) + + 00298 c7 85 64 01 00 + 00 00 00 00 00 mov DWORD PTR i$6[rbp], 0 + 002a2 eb 0e jmp SHORT $LN10@main +$LN8@main: + 002a4 8b 85 64 01 00 + 00 mov eax, DWORD PTR i$6[rbp] + 002aa ff c0 inc eax + 002ac 89 85 64 01 00 + 00 mov DWORD PTR i$6[rbp], eax +$LN10@main: + 002b2 8b 85 04 01 00 + 00 mov eax, DWORD PTR AsmLen$[rbp] + 002b8 39 85 64 01 00 + 00 cmp DWORD PTR i$6[rbp], eax + 002be 0f 83 b5 00 00 + 00 jae $LN9@main + +; 95 : { +; 96 : std::cout << std::hex << std::setw(2) << std::setfill('0') << (int)Tb[i] << ' '; + + 002c4 48 8d 15 00 00 + 00 00 lea rdx, OFFSET FLAT:?hex@std@@YAAEAVios_base@1@AEAV21@@Z ; std::hex + 002cb 48 8b 0d 00 00 + 00 00 mov rcx, QWORD PTR __imp_?cout@std@@3V?$basic_ostream@DU?$char_traits@D@std@@@1@A + 002d2 ff 15 00 00 00 + 00 call QWORD PTR __imp_??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAVios_base@1@AEAV21@@Z@Z + 002d8 48 89 85 e8 03 + 00 00 mov QWORD PTR tv202[rbp], rax + 002df ba 02 00 00 00 mov edx, 2 + 002e4 48 8d 8d c8 03 + 00 00 lea rcx, QWORD PTR $T12[rbp] + 002eb e8 00 00 00 00 call ?setw@std@@YA?AU?$_Smanip@_J@1@_J@Z ; std::setw + 002f0 48 89 85 f0 03 + 00 00 mov QWORD PTR tv204[rbp], rax + 002f7 48 8b 95 f0 03 + 00 00 mov rdx, QWORD PTR tv204[rbp] + 002fe 48 8b 8d e8 03 + 00 00 mov rcx, QWORD PTR tv202[rbp] + 00305 e8 00 00 00 00 call ??$?6DU?$char_traits@D@std@@_J@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Smanip@_J@0@@Z ; std::operator<<,__int64> + 0030a 48 89 85 f8 03 + 00 00 mov QWORD PTR tv207[rbp], rax + 00311 b2 30 mov dl, 48 ; 00000030H + 00313 48 8d 8d a4 03 + 00 00 lea rcx, QWORD PTR $T11[rbp] + 0031a e8 00 00 00 00 call ??$setfill@D@std@@YA?AU?$_Fillobj@D@0@D@Z ; std::setfill + 0031f 48 89 85 00 04 + 00 00 mov QWORD PTR tv209[rbp], rax + 00326 48 8b 95 00 04 + 00 00 mov rdx, QWORD PTR tv209[rbp] + 0032d 48 8b 8d f8 03 + 00 00 mov rcx, QWORD PTR tv207[rbp] + 00334 e8 00 00 00 00 call ??$?6DU?$char_traits@D@std@@D@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@AEBU?$_Fillobj@D@0@@Z ; std::operator<<,char> + 00339 48 89 85 08 04 + 00 00 mov QWORD PTR tv220[rbp], rax + 00340 8b 85 64 01 00 + 00 mov eax, DWORD PTR i$6[rbp] + 00346 48 8b 8d 48 01 + 00 00 mov rcx, QWORD PTR Tb$[rbp] + 0034d 0f b6 04 01 movzx eax, BYTE PTR [rcx+rax] + 00351 89 85 10 04 00 + 00 mov DWORD PTR tv218[rbp], eax + 00357 8b 95 10 04 00 + 00 mov edx, DWORD PTR tv218[rbp] + 0035d 48 8b 8d 08 04 + 00 00 mov rcx, QWORD PTR tv220[rbp] + 00364 ff 15 00 00 00 + 00 call QWORD PTR __imp_??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z + 0036a b2 20 mov dl, 32 ; 00000020H + 0036c 48 8b c8 mov rcx, rax + 0036f e8 00 00 00 00 call ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z ; std::operator<< > + +; 97 : } + + 00374 e9 2b ff ff ff jmp $LN8@main +$LN9@main: + +; 98 : +; 99 : system("pause"); + + 00379 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:??_C@_05PDJBBECF@pause@ + 00380 ff 15 00 00 00 + 00 call QWORD PTR __imp_system + +; 100 : +; 101 : typedef ULONG64(*FnGet1776)(); +; 102 : FnGet1776 ExecBuffer = (FnGet1776)MakeExecutableBuffer(Asm, AsmLen); + + 00386 8b 95 04 01 00 + 00 mov edx, DWORD PTR AsmLen$[rbp] + 0038c 48 8b 8d 28 01 + 00 00 mov rcx, QWORD PTR Asm$[rbp] + 00393 e8 00 00 00 00 call ?MakeExecutableBuffer@@YAPEAXPEAXK@Z ; MakeExecutableBuffer + 00398 48 89 85 88 01 + 00 00 mov QWORD PTR ExecBuffer$[rbp], rax + +; 103 : if (ExecBuffer) + + 0039f 48 83 bd 88 01 + 00 00 00 cmp QWORD PTR ExecBuffer$[rbp], 0 + 003a7 74 54 je SHORT $LN11@main + +; 104 : { +; 105 : printf("The numba was: %X\n", ExecBuffer()); + + 003a9 ff 95 88 01 00 + 00 call QWORD PTR ExecBuffer$[rbp] + 003af 48 8b d0 mov rdx, rax + 003b2 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ + 003b9 e8 00 00 00 00 call printf + +; 106 : printf("The numba was: %X\n", ExecBuffer()); + + 003be ff 95 88 01 00 + 00 call QWORD PTR ExecBuffer$[rbp] + 003c4 48 8b d0 mov rdx, rax + 003c7 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ + 003ce e8 00 00 00 00 call printf + +; 107 : +; 108 : printf("The numba was: %X\n", ExecBuffer()); + + 003d3 ff 95 88 01 00 + 00 call QWORD PTR ExecBuffer$[rbp] + 003d9 48 8b d0 mov rdx, rax + 003dc 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ + 003e3 e8 00 00 00 00 call printf + +; 109 : +; 110 : printf("The numba was: %X\n", ExecBuffer()); + + 003e8 ff 95 88 01 00 + 00 call QWORD PTR ExecBuffer$[rbp] + 003ee 48 8b d0 mov rdx, rax + 003f1 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:??_C@_0BD@FOIEMPBM@The?5numba?5was?3?5?$CFX?6@ + 003f8 e8 00 00 00 00 call printf +$LN11@main: + +; 111 : +; 112 : } +; 113 : +; 114 : +; 115 : //NcDebugPrint(Post); +; 116 : +; 117 : +; 118 : +; 119 : /*NATIVE_CODE_BLOCK Block; +; 120 : NcDisassemble(&Block, TestBuffer, TestBufferSize); +; 121 : PNATIVE_CODE_LINK NewLink = new NATIVE_CODE_LINK(CODE_FLAG_IS_INST, meme1, sizeof(meme1)); +; 122 : +; 123 : NcInsertLinkBefore(Block.End->Prev->Prev->Prev->Prev, NewLink); +; 124 : ULONG AssembledSize; +; 125 : PVOID AssembledBlock = NcAssemble(&Block, &AssembledSize); +; 126 : if (!AssembledBlock || !AssembledSize) +; 127 : { +; 128 : printf("Something failed nicka.\n"); +; 129 : system("pause"); +; 130 : return -1; +; 131 : } +; 132 : PUCHAR Tb = (PUCHAR)AssembledBlock; +; 133 : for (uint32_t i = 0; i < AssembledSize; i++) +; 134 : { +; 135 : std::cout << std::hex << std::setw(2) << std::setfill('0') << (int)Tb[i] << ' '; +; 136 : } +; 137 : */ +; 138 : +; 139 : +; 140 : //PNATIVE_CODE_BLOCK OpaqueBranch = ObfGenOpaqueBranch(Block.Start, Block.End); +; 141 : //NcDebugPrint(OpaqueBranch); +; 142 : +; 143 : +; 144 : +; 145 : /*NATIVE_CODE_LINK T; +; 146 : T.RawDataSize = 10; +; 147 : T.RawData = new UCHAR[10]; +; 148 : memset(T.RawData, 0xAA, 10); +; 149 : JIT_BITWISE_DATA Data; +; 150 : RtlSecureZeroMemory(&Data, sizeof(JIT_BITWISE_DATA)); +; 151 : PNATIVE_CODE_BLOCK NewBlock = JitEmitPreRipMov(&T); +; 152 : if (NewBlock) +; 153 : { +; 154 : printf("\n"); +; 155 : NcDebugPrint(NewBlock); +; 156 : printf("\n"); +; 157 : NcPrintBlockCode(NewBlock); +; 158 : } +; 159 : system("pause");*/ +; 160 : +; 161 : } + + 003fd 33 c0 xor eax, eax + 003ff 8b f8 mov edi, eax + 00401 48 8d 4d d0 lea rcx, QWORD PTR [rbp-48] + 00405 48 8d 15 00 00 + 00 00 lea rdx, OFFSET FLAT:main$rtcFrameData + 0040c e8 00 00 00 00 call _RTC_CheckStackVars + 00411 8b c7 mov eax, edi + 00413 48 8b 8d 18 04 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] - 000b8 48 33 cd xor rcx, rbp - 000bb e8 00 00 00 00 call __security_check_cookie - 000c0 48 8d a5 28 01 - 00 00 lea rsp, QWORD PTR [rbp+296] - 000c7 5f pop rdi - 000c8 5d pop rbp - 000c9 c3 ret 0 -??1?$vector@KV?$allocator@K@std@@@std@@QEAA@XZ ENDP ; std::vector >::~vector > + 0041a 48 33 cd xor rcx, rbp + 0041d e8 00 00 00 00 call __security_check_cookie + 00422 48 8d a5 28 04 + 00 00 lea rsp, QWORD PTR [rbp+1064] + 00429 5f pop rdi + 0042a 5d pop rbp + 0042b c3 ret 0 +main ENDP _TEXT ENDS +; COMDAT text$x +text$x SEGMENT +Return1776$ = 8 +RetInst$ = 40 +Pre1$ = 72 +Post1$ = 104 +Pre2$ = 136 +Post2$ = 168 +i$4 = 196 +i$5 = 228 +AsmLen$ = 260 +Asm$ = 296 +Tb$ = 328 +i$6 = 356 +ExecBuffer$ = 392 +$T7 = 808 +$T8 = 840 +$T9 = 872 +$T10 = 904 +$T11 = 932 +$T12 = 968 +tv179 = 996 +tv168 = 996 +tv202 = 1000 +tv130 = 1000 +tv83 = 1000 +tv204 = 1008 +tv207 = 1016 +tv209 = 1024 +tv220 = 1032 +tv218 = 1040 +__$ArrayPad$ = 1048 +main$dtor$0 PROC + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 0000a 55 push rbp + 0000b 57 push rdi + 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H + 00010 48 8d 6a 30 lea rbp, QWORD PTR [rdx+48] + 00014 ba f0 00 00 00 mov edx, 240 ; 000000f0H + 00019 48 8b 8d 48 03 + 00 00 mov rcx, QWORD PTR $T8[rbp] + 00020 e8 00 00 00 00 call ??3@YAXPEAX_K@Z ; operator delete + 00025 48 83 c4 28 add rsp, 40 ; 00000028H + 00029 5f pop rdi + 0002a 5d pop rbp + 0002b c3 ret 0 +main$dtor$0 ENDP +text$x ENDS +; COMDAT text$x +text$x SEGMENT +Return1776$ = 8 +RetInst$ = 40 +Pre1$ = 72 +Post1$ = 104 +Pre2$ = 136 +Post2$ = 168 +i$4 = 196 +i$5 = 228 +AsmLen$ = 260 +Asm$ = 296 +Tb$ = 328 +i$6 = 356 +ExecBuffer$ = 392 +$T7 = 808 +$T8 = 840 +$T9 = 872 +$T10 = 904 +$T11 = 932 +$T12 = 968 +tv179 = 996 +tv168 = 996 +tv202 = 1000 +tv130 = 1000 +tv83 = 1000 +tv204 = 1008 +tv207 = 1016 +tv209 = 1024 +tv220 = 1032 +tv218 = 1040 +__$ArrayPad$ = 1048 +main$dtor$1 PROC + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 0000a 55 push rbp + 0000b 57 push rdi + 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H + 00010 48 8d 6a 30 lea rbp, QWORD PTR [rdx+48] + 00014 ba f0 00 00 00 mov edx, 240 ; 000000f0H + 00019 48 8b 8d 88 03 + 00 00 mov rcx, QWORD PTR $T10[rbp] + 00020 e8 00 00 00 00 call ??3@YAXPEAX_K@Z ; operator delete + 00025 48 83 c4 28 add rsp, 40 ; 00000028H + 00029 5f pop rdi + 0002a 5d pop rbp + 0002b c3 ret 0 +main$dtor$1 ENDP +text$x ENDS +; Function compile flags: /Odtp /RTCsu /ZI +; COMDAT text$x +text$x SEGMENT +Return1776$ = 8 +RetInst$ = 40 +Pre1$ = 72 +Post1$ = 104 +Pre2$ = 136 +Post2$ = 168 +i$4 = 196 +i$5 = 228 +AsmLen$ = 260 +Asm$ = 296 +Tb$ = 328 +i$6 = 356 +ExecBuffer$ = 392 +$T7 = 808 +$T8 = 840 +$T9 = 872 +$T10 = 904 +$T11 = 932 +$T12 = 968 +tv179 = 996 +tv168 = 996 +tv202 = 1000 +tv130 = 1000 +tv83 = 1000 +tv204 = 1008 +tv207 = 1016 +tv209 = 1024 +tv220 = 1032 +tv218 = 1040 +__$ArrayPad$ = 1048 +main$dtor$0 PROC + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 0000a 55 push rbp + 0000b 57 push rdi + 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H + 00010 48 8d 6a 30 lea rbp, QWORD PTR [rdx+48] + 00014 ba f0 00 00 00 mov edx, 240 ; 000000f0H + 00019 48 8b 8d 48 03 + 00 00 mov rcx, QWORD PTR $T8[rbp] + 00020 e8 00 00 00 00 call ??3@YAXPEAX_K@Z ; operator delete + 00025 48 83 c4 28 add rsp, 40 ; 00000028H + 00029 5f pop rdi + 0002a 5d pop rbp + 0002b c3 ret 0 +main$dtor$0 ENDP +text$x ENDS +; Function compile flags: /Odtp /RTCsu /ZI +; COMDAT text$x +text$x SEGMENT +Return1776$ = 8 +RetInst$ = 40 +Pre1$ = 72 +Post1$ = 104 +Pre2$ = 136 +Post2$ = 168 +i$4 = 196 +i$5 = 228 +AsmLen$ = 260 +Asm$ = 296 +Tb$ = 328 +i$6 = 356 +ExecBuffer$ = 392 +$T7 = 808 +$T8 = 840 +$T9 = 872 +$T10 = 904 +$T11 = 932 +$T12 = 968 +tv179 = 996 +tv168 = 996 +tv202 = 1000 +tv130 = 1000 +tv83 = 1000 +tv204 = 1008 +tv207 = 1016 +tv209 = 1024 +tv220 = 1032 +tv218 = 1040 +__$ArrayPad$ = 1048 +main$dtor$1 PROC + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx + 0000a 55 push rbp + 0000b 57 push rdi + 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H + 00010 48 8d 6a 30 lea rbp, QWORD PTR [rdx+48] + 00014 ba f0 00 00 00 mov edx, 240 ; 000000f0H + 00019 48 8b 8d 88 03 + 00 00 mov rcx, QWORD PTR $T10[rbp] + 00020 e8 00 00 00 00 call ??3@YAXPEAX_K@Z ; operator delete + 00025 48 83 c4 28 add rsp, 40 ; 00000028H + 00029 5f pop rdi + 0002a 5d pop rbp + 0002b c3 ret 0 +main$dtor$1 ENDP +text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z +; File C:\$Fanta\code-virtualizer\CodeVirtualizer\Main.cpp +; COMDAT ?MakeExecutableBuffer@@YAPEAXPEAXK@Z _TEXT SEGMENT -this$ = 224 -_Ptr$ = 232 -_Count$ = 240 -?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z PROC ; std::allocator::deallocate, COMDAT +ExecBuffer$ = 8 +Buffer$ = 256 +BufferSize$ = 264 +?MakeExecutableBuffer@@YAPEAXPEAXK@Z PROC ; MakeExecutableBuffer, COMDAT -; 801 : void deallocate(_Ty* const _Ptr, const size_t _Count) { +; 14 : { -$LN3: - 00000 4c 89 44 24 18 mov QWORD PTR [rsp+24], r8 - 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx - 0000a 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 0000f 55 push rbp - 00010 57 push rdi - 00011 48 81 ec e8 00 - 00 00 sub rsp, 232 ; 000000e8H - 00018 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 0001d 48 8b fc mov rdi, rsp - 00020 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH - 00025 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 0002a f3 ab rep stosd - 0002c 48 8b 8c 24 08 - 01 00 00 mov rcx, QWORD PTR [rsp+264] - 00034 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode +$LN4: + 00000 89 54 24 10 mov DWORD PTR [rsp+16], edx + 00004 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00009 55 push rbp + 0000a 57 push rdi + 0000b 48 81 ec 08 01 + 00 00 sub rsp, 264 ; 00000108H + 00012 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00017 48 8b fc mov rdi, rsp + 0001a b9 42 00 00 00 mov ecx, 66 ; 00000042H + 0001f b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00024 f3 ab rep stosd + 00026 48 8b 8c 24 28 + 01 00 00 mov rcx, QWORD PTR [rsp+296] + 0002e 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__4031338C_Main@cpp + 00035 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 802 : // no overflow check on the following multiply; we assume _Allocate did that check -; 803 : _Deallocate<_New_alignof<_Ty>>(_Ptr, sizeof(_Ty) * _Count); +; 15 : PVOID ExecBuffer = VirtualAlloc(nullptr, BufferSize, MEM_COMMIT, PAGE_EXECUTE_READWRITE); - 00040 48 8b 85 f0 00 - 00 00 mov rax, QWORD PTR _Count$[rbp] - 00047 48 c1 e0 02 shl rax, 2 - 0004b 48 8b d0 mov rdx, rax - 0004e 48 8b 8d e8 00 - 00 00 mov rcx, QWORD PTR _Ptr$[rbp] - 00055 e8 00 00 00 00 call ??$_Deallocate@$0BA@$0A@@std@@YAXPEAX_K@Z ; std::_Deallocate<16,0> + 0003a 8b 85 08 01 00 + 00 mov eax, DWORD PTR BufferSize$[rbp] + 00040 41 b9 40 00 00 + 00 mov r9d, 64 ; 00000040H + 00046 41 b8 00 10 00 + 00 mov r8d, 4096 ; 00001000H + 0004c 8b d0 mov edx, eax + 0004e 33 c9 xor ecx, ecx + 00050 ff 15 00 00 00 + 00 call QWORD PTR __imp_VirtualAlloc + 00056 48 89 45 08 mov QWORD PTR ExecBuffer$[rbp], rax + +; 16 : if (!ExecBuffer) -; 804 : } + 0005a 48 83 7d 08 00 cmp QWORD PTR ExecBuffer$[rbp], 0 + 0005f 75 04 jne SHORT $LN2@MakeExecut - 0005a 48 8d a5 c8 00 - 00 00 lea rsp, QWORD PTR [rbp+200] - 00061 5f pop rdi - 00062 5d pop rbp - 00063 c3 ret 0 -?deallocate@?$allocator@K@std@@QEAAXQEAK_K@Z ENDP ; std::allocator::deallocate +; 17 : return NULL; + + 00061 33 c0 xor eax, eax + 00063 eb 19 jmp SHORT $LN1@MakeExecut +$LN2@MakeExecut: + +; 18 : RtlCopyMemory(ExecBuffer, Buffer, BufferSize); + + 00065 8b 85 08 01 00 + 00 mov eax, DWORD PTR BufferSize$[rbp] + 0006b 44 8b c0 mov r8d, eax + 0006e 48 8b 95 00 01 + 00 00 mov rdx, QWORD PTR Buffer$[rbp] + 00075 48 8b 4d 08 mov rcx, QWORD PTR ExecBuffer$[rbp] + 00079 e8 00 00 00 00 call memcpy +$LN1@MakeExecut: + +; 19 : } + + 0007e 48 8d a5 e8 00 + 00 00 lea rsp, QWORD PTR [rbp+232] + 00085 5f pop rdi + 00086 5d pop rbp + 00087 c3 ret 0 +?MakeExecutableBuffer@@YAPEAXPEAXK@Z ENDP ; MakeExecutableBuffer _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xloctime @@ -2816,6 +3574,56 @@ time PROC ; COMDAT time ENDP _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\ios +; COMDAT ?hex@std@@YAAEAVios_base@1@AEAV21@@Z +_TEXT SEGMENT +_Iosbase$ = 224 +?hex@std@@YAAEAVios_base@1@AEAV21@@Z PROC ; std::hex, COMDAT + +; 206 : inline ios_base& __CLRCALL_OR_CDECL hex(ios_base& _Iosbase) { // set basefield to hex + +$LN3: + 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx + 00005 55 push rbp + 00006 57 push rdi + 00007 48 81 ec e8 00 + 00 00 sub rsp, 232 ; 000000e8H + 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 00013 48 8b fc mov rdi, rsp + 00016 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 00020 f3 ab rep stosd + 00022 48 8b 8c 24 08 + 01 00 00 mov rcx, QWORD PTR [rsp+264] + 0002a 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__165C22CB_ios + 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + +; 207 : _Iosbase.setf(ios_base::hex, ios_base::basefield); + + 00036 41 b8 00 0e 00 + 00 mov r8d, 3584 ; 00000e00H + 0003c ba 00 08 00 00 mov edx, 2048 ; 00000800H + 00041 48 8b 8d e0 00 + 00 00 mov rcx, QWORD PTR _Iosbase$[rbp] + 00048 ff 15 00 00 00 + 00 call QWORD PTR __imp_?setf@ios_base@std@@QEAAHHH@Z + +; 208 : return _Iosbase; + + 0004e 48 8b 85 e0 00 + 00 00 mov rax, QWORD PTR _Iosbase$[rbp] + +; 209 : } + + 00055 48 8d a5 c8 00 + 00 00 lea rsp, QWORD PTR [rbp+200] + 0005c 5f pop rdi + 0005d 5d pop rbp + 0005e c3 ret 0 +?hex@std@@YAAEAVios_base@1@AEAV21@@Z ENDP ; std::hex +_TEXT ENDS +; Function compile flags: /Odtp /RTCsu /ZI ; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xlocale ; COMDAT ??$_Maklocstr@D@std@@YAPEADPEBDPEADAEBU_Cvtvec@@@Z _TEXT SEGMENT @@ -3302,330 +4110,96 @@ $LN11@Maklocstr: ??$_Maklocstr@_W@std@@YAPEA_WPEBDPEA_WAEBU_Cvtvec@@@Z ENDP ; std::_Maklocstr _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ?_Orphan_all@_Container_base12@std@@QEAAXXZ +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xstring +; COMDAT ?eof@?$_Narrow_char_traits@DH@std@@SAHXZ _TEXT SEGMENT -_Lock$4 = 4 -_Pnext$5 = 40 -__$ArrayPad$ = 248 -this$ = 288 -?_Orphan_all@_Container_base12@std@@QEAAXXZ PROC ; std::_Container_base12::_Orphan_all, COMDAT - -; 1205 : inline void _Container_base12::_Orphan_all() noexcept { - -$LN7: - 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx - 00005 55 push rbp - 00006 57 push rdi - 00007 48 81 ec 28 01 - 00 00 sub rsp, 296 ; 00000128H - 0000e 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] - 00013 48 8b fc mov rdi, rsp - 00016 b9 4a 00 00 00 mov ecx, 74 ; 0000004aH - 0001b b8 cc cc cc cc mov eax, -858993460 ; ccccccccH - 00020 f3 ab rep stosd - 00022 48 8b 8c 24 48 - 01 00 00 mov rcx, QWORD PTR [rsp+328] - 0002a 48 8b 05 00 00 - 00 00 mov rax, QWORD PTR __security_cookie - 00031 48 33 c5 xor rax, rbp - 00034 48 89 85 f8 00 - 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax - 0003b 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory - 00042 e8 00 00 00 00 call __CheckForDebuggerJustMyCode +?eof@?$_Narrow_char_traits@DH@std@@SAHXZ PROC ; std::_Narrow_char_traits::eof, COMDAT -; 1206 : #if _ITERATOR_DEBUG_LEVEL == 2 -; 1207 : if (_Myproxy) { // proxy allocated, drain it +; 400 : _NODISCARD static constexpr int_type eof() noexcept { - 00047 48 8b 85 20 01 - 00 00 mov rax, QWORD PTR this$[rbp] - 0004e 48 83 38 00 cmp QWORD PTR [rax], 0 - 00052 74 6b je SHORT $LN5@Orphan_all +$LN3: + 00000 40 55 push rbp + 00002 57 push rdi + 00003 48 81 ec e8 00 + 00 00 sub rsp, 232 ; 000000e8H + 0000a 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] + 0000f 48 8b fc mov rdi, rsp + 00012 b9 3a 00 00 00 mov ecx, 58 ; 0000003aH + 00017 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH + 0001c f3 ab rep stosd + 0001e 48 8d 0d 00 00 + 00 00 lea rcx, OFFSET FLAT:__D15AFF60_xstring + 00025 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 1208 : _Lockit _Lock(_LOCK_DEBUG); +; 401 : return static_cast(EOF); - 00054 ba 03 00 00 00 mov edx, 3 - 00059 48 8d 4d 04 lea rcx, QWORD PTR _Lock$4[rbp] - 0005d ff 15 00 00 00 - 00 call QWORD PTR __imp_??0_Lockit@std@@QEAA@H@Z + 0002a b8 ff ff ff ff mov eax, -1 -; 1209 : -; 1210 : for (auto _Pnext = &_Myproxy->_Myfirstiter; *_Pnext; *_Pnext = (*_Pnext)->_Mynextiter) { +; 402 : } - 00063 48 8b 85 20 01 - 00 00 mov rax, QWORD PTR this$[rbp] - 0006a 48 8b 00 mov rax, QWORD PTR [rax] - 0006d 48 83 c0 08 add rax, 8 - 00071 48 89 45 28 mov QWORD PTR _Pnext$5[rbp], rax - 00075 eb 12 jmp SHORT $LN4@Orphan_all -$LN2@Orphan_all: - 00077 48 8b 45 28 mov rax, QWORD PTR _Pnext$5[rbp] - 0007b 48 8b 00 mov rax, QWORD PTR [rax] - 0007e 48 8b 4d 28 mov rcx, QWORD PTR _Pnext$5[rbp] - 00082 48 8b 40 08 mov rax, QWORD PTR [rax+8] - 00086 48 89 01 mov QWORD PTR [rcx], rax -$LN4@Orphan_all: - 00089 48 8b 45 28 mov rax, QWORD PTR _Pnext$5[rbp] - 0008d 48 83 38 00 cmp QWORD PTR [rax], 0 - 00091 74 10 je SHORT $LN3@Orphan_all - -; 1211 : (*_Pnext)->_Myproxy = nullptr; - - 00093 48 8b 45 28 mov rax, QWORD PTR _Pnext$5[rbp] - 00097 48 8b 00 mov rax, QWORD PTR [rax] - 0009a 48 c7 00 00 00 - 00 00 mov QWORD PTR [rax], 0 - -; 1212 : } - - 000a1 eb d4 jmp SHORT $LN2@Orphan_all -$LN3@Orphan_all: - -; 1213 : -; 1214 : _Myproxy->_Myfirstiter = nullptr; - - 000a3 48 8b 85 20 01 - 00 00 mov rax, QWORD PTR this$[rbp] - 000aa 48 8b 00 mov rax, QWORD PTR [rax] - 000ad 48 c7 40 08 00 - 00 00 00 mov QWORD PTR [rax+8], 0 - -; 1215 : } - - 000b5 48 8d 4d 04 lea rcx, QWORD PTR _Lock$4[rbp] - 000b9 ff 15 00 00 00 - 00 call QWORD PTR __imp_??1_Lockit@std@@QEAA@XZ -$LN5@Orphan_all: - -; 1216 : #endif // _ITERATOR_DEBUG_LEVEL == 2 -; 1217 : } - - 000bf 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] - 000c3 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:?_Orphan_all@_Container_base12@std@@QEAAXXZ$rtcFrameData - 000ca e8 00 00 00 00 call _RTC_CheckStackVars - 000cf 90 npad 1 - 000d0 48 8b 8d f8 00 - 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] - 000d7 48 33 cd xor rcx, rbp - 000da e8 00 00 00 00 call __security_check_cookie - 000df 48 8d a5 08 01 - 00 00 lea rsp, QWORD PTR [rbp+264] - 000e6 5f pop rdi - 000e7 5d pop rbp - 000e8 c3 ret 0 -?_Orphan_all@_Container_base12@std@@QEAAXXZ ENDP ; std::_Container_base12::_Orphan_all + 0002f 48 8d a5 c8 00 + 00 00 lea rsp, QWORD PTR [rbp+200] + 00036 5f pop rdi + 00037 5d pop rbp + 00038 c3 ret 0 +?eof@?$_Narrow_char_traits@DH@std@@SAHXZ ENDP ; std::_Narrow_char_traits::eof _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI -; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xmemory -; COMDAT ?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z +; File C:\Program Files (x86)\Microsoft Visual Studio\2019\Community\VC\Tools\MSVC\14.27.29110\include\xstring +; COMDAT ?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z _TEXT SEGMENT -_Ptr_user$ = 8 -_Ptr_container$ = 40 -_Min_back_shift$ = 72 -_Back_shift$ = 104 -_Ptr$ = 352 -_Bytes$ = 360 -?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z PROC ; std::_Adjust_manually_vector_aligned, COMDAT +tv65 = 192 +_Left$ = 240 +_Right$ = 248 +?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z PROC ; std::_Narrow_char_traits::eq_int_type, COMDAT -; 132 : inline void _Adjust_manually_vector_aligned(void*& _Ptr, size_t& _Bytes) { +; 392 : _NODISCARD static constexpr bool eq_int_type(const int_type& _Left, const int_type& _Right) noexcept { -$LN21: +$LN5: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 0000a 55 push rbp 0000b 57 push rdi - 0000c 48 81 ec 78 01 - 00 00 sub rsp, 376 ; 00000178H - 00013 48 8d 6c 24 30 lea rbp, QWORD PTR [rsp+48] + 0000c 48 81 ec f8 00 + 00 00 sub rsp, 248 ; 000000f8H + 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00018 48 8b fc mov rdi, rsp - 0001b b9 5e 00 00 00 mov ecx, 94 ; 0000005eH + 0001b b9 3e 00 00 00 mov ecx, 62 ; 0000003eH 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 00025 f3 ab rep stosd - 00027 48 8b 8c 24 98 - 01 00 00 mov rcx, QWORD PTR [rsp+408] + 00027 48 8b 8c 24 18 + 01 00 00 mov rcx, QWORD PTR [rsp+280] 0002f 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:__A58979FC_xmemory + 00 00 lea rcx, OFFSET FLAT:__D15AFF60_xstring 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 133 : // adjust parameters from _Allocate_manually_vector_aligned to pass to operator delete -; 134 : _Bytes += _Non_user_size; - - 0003b 48 8b 85 68 01 - 00 00 mov rax, QWORD PTR _Bytes$[rbp] - 00042 48 8b 00 mov rax, QWORD PTR [rax] - 00045 48 83 c0 2f add rax, 47 ; 0000002fH - 00049 48 8b 8d 68 01 - 00 00 mov rcx, QWORD PTR _Bytes$[rbp] - 00050 48 89 01 mov QWORD PTR [rcx], rax - -; 135 : -; 136 : const uintptr_t* const _Ptr_user = reinterpret_cast(_Ptr); - - 00053 48 8b 85 60 01 - 00 00 mov rax, QWORD PTR _Ptr$[rbp] - 0005a 48 8b 00 mov rax, QWORD PTR [rax] - 0005d 48 89 45 08 mov QWORD PTR _Ptr_user$[rbp], rax - -; 137 : const uintptr_t _Ptr_container = _Ptr_user[-1]; - - 00061 b8 08 00 00 00 mov eax, 8 - 00066 48 6b c0 ff imul rax, rax, -1 - 0006a 48 8b 4d 08 mov rcx, QWORD PTR _Ptr_user$[rbp] - 0006e 48 8b 04 01 mov rax, QWORD PTR [rcx+rax] - 00072 48 89 45 28 mov QWORD PTR _Ptr_container$[rbp], rax -$LN4@Adjust_man: - -; 138 : -; 139 : // If the following asserts, it likely means that we are performing -; 140 : // an aligned delete on memory coming from an unaligned allocation. -; 141 : _STL_ASSERT(_Ptr_user[-2] == _Big_allocation_sentinel, "invalid argument"); - - 00076 b8 08 00 00 00 mov eax, 8 - 0007b 48 6b c0 fe imul rax, rax, -2 - 0007f 48 8b 4d 08 mov rcx, QWORD PTR _Ptr_user$[rbp] - 00083 48 ba fa fa fa - fa fa fa fa fa mov rdx, -361700864190383366 ; fafafafafafafafaH - 0008d 48 39 14 01 cmp QWORD PTR [rcx+rax], rdx - 00091 75 02 jne SHORT $LN14@Adjust_man - 00093 eb 77 jmp SHORT $LN15@Adjust_man -$LN14@Adjust_man: -$LN7@Adjust_man: - 00095 8b 05 00 00 00 - 00 mov eax, DWORD PTR ?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA - 0009b 83 c0 09 add eax, 9 - 0009e 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_0BB@FCMFBGOM@invalid?5argument@ - 000a5 48 89 4c 24 28 mov QWORD PTR [rsp+40], rcx - 000aa 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_02DKCKIIND@?$CFs@ - 000b1 48 89 4c 24 20 mov QWORD PTR [rsp+32], rcx - 000b6 45 33 c9 xor r9d, r9d - 000b9 44 8b c0 mov r8d, eax - 000bc 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:??_C@_0GI@JMEOMKJO@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ - 000c3 b9 02 00 00 00 mov ecx, 2 - 000c8 ff 15 00 00 00 - 00 call QWORD PTR __imp__CrtDbgReport - 000ce 83 f8 01 cmp eax, 1 - 000d1 75 03 jne SHORT $LN19@Adjust_man - 000d3 cc int 3 - 000d4 33 c0 xor eax, eax -$LN19@Adjust_man: - 000d6 8b 05 00 00 00 - 00 mov eax, DWORD PTR ?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA - 000dc 83 c0 09 add eax, 9 - 000df 48 c7 44 24 20 - 00 00 00 00 mov QWORD PTR [rsp+32], 0 - 000e8 44 8b c8 mov r9d, eax - 000eb 4c 8d 05 00 00 - 00 00 lea r8, OFFSET FLAT:??_C@_1NA@FEEOBALC@?$AAC?$AA?3?$AA?2?$AAP?$AAr?$AAo?$AAg?$AAr?$AAa?$AAm?$AA?5?$AAF?$AAi?$AAl?$AAe@ - 000f2 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:??_C@_1EK@NIFDJFDG@?$AAs?$AAt?$AAd?$AA?3?$AA?3?$AA_?$AAA?$AAd?$AAj?$AAu?$AAs?$AAt?$AA_?$AAm?$AAa@ - 000f9 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_1CG@JNLFBNGN@?$AA?$CC?$AAi?$AAn?$AAv?$AAa?$AAl?$AAi?$AAd?$AA?5?$AAa?$AAr?$AAg?$AAu?$AAm?$AAe@ - 00100 ff 15 00 00 00 - 00 call QWORD PTR __imp__invalid_parameter - 00106 33 c0 xor eax, eax - 00108 85 c0 test eax, eax - 0010a 75 89 jne SHORT $LN7@Adjust_man -$LN15@Adjust_man: - 0010c 33 c0 xor eax, eax - 0010e 85 c0 test eax, eax - 00110 0f 85 60 ff ff - ff jne $LN4@Adjust_man - -; 142 : -; 143 : // Extra paranoia on aligned allocation/deallocation; ensure _Ptr_container is -; 144 : // in range [_Min_back_shift, _Non_user_size] -; 145 : #ifdef _DEBUG -; 146 : constexpr uintptr_t _Min_back_shift = 2 * sizeof(void*); - - 00116 48 c7 45 48 10 - 00 00 00 mov QWORD PTR _Min_back_shift$[rbp], 16 - -; 147 : #else // ^^^ _DEBUG ^^^ // vvv !_DEBUG vvv -; 148 : constexpr uintptr_t _Min_back_shift = sizeof(void*); -; 149 : #endif // _DEBUG -; 150 : const uintptr_t _Back_shift = reinterpret_cast(_Ptr) - _Ptr_container; - - 0011e 48 8b 85 60 01 - 00 00 mov rax, QWORD PTR _Ptr$[rbp] - 00125 48 8b 4d 28 mov rcx, QWORD PTR _Ptr_container$[rbp] - 00129 48 8b 00 mov rax, QWORD PTR [rax] - 0012c 48 2b c1 sub rax, rcx - 0012f 48 89 45 68 mov QWORD PTR _Back_shift$[rbp], rax -$LN10@Adjust_man: - -; 151 : _STL_VERIFY(_Back_shift >= _Min_back_shift && _Back_shift <= _Non_user_size, "invalid argument"); - - 00133 48 83 7d 68 10 cmp QWORD PTR _Back_shift$[rbp], 16 - 00138 72 09 jb SHORT $LN16@Adjust_man - 0013a 48 83 7d 68 2f cmp QWORD PTR _Back_shift$[rbp], 47 ; 0000002fH - 0013f 77 02 ja SHORT $LN16@Adjust_man - 00141 eb 77 jmp SHORT $LN17@Adjust_man -$LN16@Adjust_man: -$LN13@Adjust_man: - 00143 8b 05 00 00 00 - 00 mov eax, DWORD PTR ?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA - 00149 83 c0 13 add eax, 19 - 0014c 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_0BB@FCMFBGOM@invalid?5argument@ - 00153 48 89 4c 24 28 mov QWORD PTR [rsp+40], rcx - 00158 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_02DKCKIIND@?$CFs@ - 0015f 48 89 4c 24 20 mov QWORD PTR [rsp+32], rcx - 00164 45 33 c9 xor r9d, r9d - 00167 44 8b c0 mov r8d, eax - 0016a 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:??_C@_0GI@JMEOMKJO@C?3?2Program?5Files?5?$CIx86?$CJ?2Microsof@ - 00171 b9 02 00 00 00 mov ecx, 2 - 00176 ff 15 00 00 00 - 00 call QWORD PTR __imp__CrtDbgReport - 0017c 83 f8 01 cmp eax, 1 - 0017f 75 03 jne SHORT $LN20@Adjust_man - 00181 cc int 3 - 00182 33 c0 xor eax, eax -$LN20@Adjust_man: - 00184 8b 05 00 00 00 - 00 mov eax, DWORD PTR ?__LINE__Var@?0??_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z@4JA - 0018a 83 c0 13 add eax, 19 - 0018d 48 c7 44 24 20 - 00 00 00 00 mov QWORD PTR [rsp+32], 0 - 00196 44 8b c8 mov r9d, eax - 00199 4c 8d 05 00 00 - 00 00 lea r8, OFFSET FLAT:??_C@_1NA@FEEOBALC@?$AAC?$AA?3?$AA?2?$AAP?$AAr?$AAo?$AAg?$AAr?$AAa?$AAm?$AA?5?$AAF?$AAi?$AAl?$AAe@ - 001a0 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:??_C@_1EK@NIFDJFDG@?$AAs?$AAt?$AAd?$AA?3?$AA?3?$AA_?$AAA?$AAd?$AAj?$AAu?$AAs?$AAt?$AA_?$AAm?$AAa@ - 001a7 48 8d 0d 00 00 - 00 00 lea rcx, OFFSET FLAT:??_C@_1CG@JNLFBNGN@?$AA?$CC?$AAi?$AAn?$AAv?$AAa?$AAl?$AAi?$AAd?$AA?5?$AAa?$AAr?$AAg?$AAu?$AAm?$AAe@ - 001ae ff 15 00 00 00 - 00 call QWORD PTR __imp__invalid_parameter - 001b4 33 c0 xor eax, eax - 001b6 85 c0 test eax, eax - 001b8 75 89 jne SHORT $LN13@Adjust_man -$LN17@Adjust_man: - 001ba 33 c0 xor eax, eax - 001bc 85 c0 test eax, eax - 001be 0f 85 6f ff ff - ff jne $LN10@Adjust_man - -; 152 : _Ptr = reinterpret_cast(_Ptr_container); - - 001c4 48 8b 85 60 01 - 00 00 mov rax, QWORD PTR _Ptr$[rbp] - 001cb 48 8b 4d 28 mov rcx, QWORD PTR _Ptr_container$[rbp] - 001cf 48 89 08 mov QWORD PTR [rax], rcx - -; 153 : } - - 001d2 48 8d a5 48 01 - 00 00 lea rsp, QWORD PTR [rbp+328] - 001d9 5f pop rdi - 001da 5d pop rbp - 001db c3 ret 0 -?_Adjust_manually_vector_aligned@std@@YAXAEAPEAXAEA_K@Z ENDP ; std::_Adjust_manually_vector_aligned +; 393 : return _Left == _Right; + + 0003b 48 8b 85 f0 00 + 00 00 mov rax, QWORD PTR _Left$[rbp] + 00042 48 8b 8d f8 00 + 00 00 mov rcx, QWORD PTR _Right$[rbp] + 00049 8b 09 mov ecx, DWORD PTR [rcx] + 0004b 39 08 cmp DWORD PTR [rax], ecx + 0004d 75 0c jne SHORT $LN3@eq_int_typ + 0004f c7 85 c0 00 00 + 00 01 00 00 00 mov DWORD PTR tv65[rbp], 1 + 00059 eb 0a jmp SHORT $LN4@eq_int_typ +$LN3@eq_int_typ: + 0005b c7 85 c0 00 00 + 00 00 00 00 00 mov DWORD PTR tv65[rbp], 0 +$LN4@eq_int_typ: + 00065 0f b6 85 c0 00 + 00 00 movzx eax, BYTE PTR tv65[rbp] + +; 394 : } + + 0006c 48 8d a5 d8 00 + 00 00 lea rsp, QWORD PTR [rbp+216] + 00073 5f pop rdi + 00074 5d pop rbp + 00075 c3 ret 0 +?eq_int_type@?$_Narrow_char_traits@DH@std@@SA_NAEBH0@Z ENDP ; std::_Narrow_char_traits::eq_int_type _TEXT ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; File C:\Program Files (x86)\Windows Kits\10\Include\10.0.19041.0\ucrt\wchar.h diff --git a/CodeVirtualizer/x64/Debug/NativeCode.cod b/CodeVirtualizer/x64/Debug/NativeCode.cod index 600581e..abc56a9 100644 --- a/CodeVirtualizer/x64/Debug/NativeCode.cod +++ b/CodeVirtualizer/x64/Debug/NativeCode.cod @@ -990,7 +990,7 @@ pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z DD imagerel $LN9 - DD imagerel $LN9+484 + DD imagerel $LN9+518 DD imagerel $unwind$?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z pdata ENDS ; COMDAT pdata @@ -1008,7 +1008,7 @@ pdata ENDS ; COMDAT pdata pdata SEGMENT $pdata$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z DD imagerel $LN17 - DD imagerel $LN17+739 + DD imagerel $LN17+675 DD imagerel $unwind$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z pdata ENDS ; COMDAT pdata @@ -3099,7 +3099,7 @@ xdata SEGMENT $ip2state$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z DB 0aH DB 00H DB 00H - DB 0c1H, 05H + DB '}', 05H DB 02H DB 0aeH DB 04H @@ -3124,29 +3124,13 @@ $cppxdata$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z DB 028H xdata ENDS ; COMDAT xdata xdata SEGMENT -$unwind$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z DD 025054019H +$unwind$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z DD 025052f11H DD 01132318H - DD 0700c005bH + DD 0700c0057H DD 0500bH - DD imagerel __GSHandlerCheck_EH4 + DD imagerel __CxxFrameHandler4 DD imagerel $cppxdata$?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z - DD 02caH xdata ENDS -; COMDAT CONST -CONST SEGMENT -?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z$rtcName$0 DB 04cH ; NcFixLabelsForBlocks - DB 069H - DB 064H - DB 00H - ORG $+12 -?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z$rtcVarDesc DD 044H ; NcFixLabelsForBlocks - DD 04H - DQ FLAT:?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z$rtcName$0 - ORG $+48 -?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z$rtcFrameData DD 01H ; NcFixLabelsForBlocks - DD 00H - DQ FLAT:?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z$rtcVarDesc -CONST ENDS ; COMDAT xdata xdata SEGMENT $unwind$?dtor$3@?0??NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z@4HA DD 031001H @@ -9306,7 +9290,7 @@ tv142 = 368 Block$ = 416 ?NcPrintBlockCode@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z PROC ; NcPrintBlockCode, COMDAT -; 568 : { +; 567 : { $LN10: 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx @@ -9325,7 +9309,7 @@ $LN10: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 569 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) +; 568 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) 00036 48 8b 85 a0 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -9348,8 +9332,8 @@ $LN4@NcPrintBlo: 0006e 0f 84 eb 00 00 00 je $LN3@NcPrintBlo -; 570 : { -; 571 : if (!(T->Flags & CODE_FLAG_IS_LABEL)) +; 569 : { +; 570 : if (!(T->Flags & CODE_FLAG_IS_LABEL)) 00074 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] 00078 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -9358,8 +9342,8 @@ $LN4@NcPrintBlo: 00080 0f 85 d4 00 00 00 jne $LN8@NcPrintBlo -; 572 : { -; 573 : for (uint32_t i = 0; i < T->RawDataSize; i++) +; 571 : { +; 572 : for (uint32_t i = 0; i < T->RawDataSize; i++) 00086 c7 45 24 00 00 00 00 mov DWORD PTR i$2[rbp], 0 @@ -9375,8 +9359,8 @@ $LN7@NcPrintBlo: 000a1 0f 83 b3 00 00 00 jae $LN6@NcPrintBlo -; 574 : { -; 575 : std::cout << std::hex << std::setw(2) << std::setfill('0') << (int)T->RawData[i] << ' '; +; 573 : { +; 574 : std::cout << std::hex << std::setw(2) << std::setfill('0') << (int)T->RawData[i] << ' '; 000a7 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:?hex@std@@YAAEAVios_base@1@AEAV21@@Z ; std::hex @@ -9428,19 +9412,19 @@ $LN7@NcPrintBlo: 0014d 48 8b c8 mov rcx, rax 00150 e8 00 00 00 00 call ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z ; std::operator<< > -; 576 : } +; 575 : } 00155 e9 35 ff ff ff jmp $LN5@NcPrintBlo $LN6@NcPrintBlo: $LN8@NcPrintBlo: -; 577 : } -; 578 : } +; 576 : } +; 577 : } 0015a e9 e7 fe ff ff jmp $LN2@NcPrintBlo $LN3@NcPrintBlo: -; 579 : } +; 578 : } 0015f 48 8d a5 88 01 00 00 lea rsp, QWORD PTR [rbp+392] @@ -9461,7 +9445,7 @@ tv129 = 280 Block$ = 320 ?NcDebugPrint@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z PROC ; NcDebugPrint, COMDAT -; 538 : { +; 537 : { $LN11: 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx @@ -9480,25 +9464,25 @@ $LN11: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 539 : HANDLE ConsoleHandle = GetStdHandle(STD_OUTPUT_HANDLE); +; 538 : HANDLE ConsoleHandle = GetStdHandle(STD_OUTPUT_HANDLE); 00036 b9 f5 ff ff ff mov ecx, -11 ; fffffff5H 0003b ff 15 00 00 00 00 call QWORD PTR __imp_GetStdHandle 00041 48 89 45 08 mov QWORD PTR ConsoleHandle$[rbp], rax -; 540 : if (!ConsoleHandle) +; 539 : if (!ConsoleHandle) 00045 48 83 7d 08 00 cmp QWORD PTR ConsoleHandle$[rbp], 0 0004a 75 05 jne SHORT $LN5@NcDebugPri -; 541 : return; +; 540 : return; 0004c e9 03 01 00 00 jmp $LN1@NcDebugPri $LN5@NcDebugPri: -; 542 : -; 543 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) +; 541 : +; 542 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) 00051 48 8b 85 40 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -9521,8 +9505,8 @@ $LN4@NcDebugPri: 00089 0f 84 c5 00 00 00 je $LN3@NcDebugPri -; 544 : { -; 545 : if (T->Flags & CODE_FLAG_IS_LABEL) +; 543 : { +; 544 : if (T->Flags & CODE_FLAG_IS_LABEL) 0008f 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 00093 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -9530,15 +9514,15 @@ $LN4@NcDebugPri: 00099 85 c0 test eax, eax 0009b 74 26 je SHORT $LN6@NcDebugPri -; 546 : { -; 547 : SetConsoleTextAttribute(ConsoleHandle, FOREGROUND_GREEN | FOREGROUND_RED); +; 545 : { +; 546 : SetConsoleTextAttribute(ConsoleHandle, FOREGROUND_GREEN | FOREGROUND_RED); 0009d 66 ba 06 00 mov dx, 6 000a1 48 8b 4d 08 mov rcx, QWORD PTR ConsoleHandle$[rbp] 000a5 ff 15 00 00 00 00 call QWORD PTR __imp_SetConsoleTextAttribute -; 548 : printf("Label: %u\n", T->Label); +; 547 : printf("Label: %u\n", T->Label); 000ab 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 000af 8b 50 1c mov edx, DWORD PTR [rax+28] @@ -9546,14 +9530,14 @@ $LN4@NcDebugPri: 00 00 lea rcx, OFFSET FLAT:??_C@_0L@ILJOJNOL@Label?3?5?$CFu?6@ 000b9 e8 00 00 00 00 call printf -; 549 : } +; 548 : } 000be e9 8c 00 00 00 jmp $LN7@NcDebugPri $LN6@NcDebugPri: -; 550 : else -; 551 : { -; 552 : XED_ICLASS_ENUM IClass = XedDecodedInstGetIClass(&T->XedInstruction); +; 549 : else +; 550 : { +; 551 : XED_ICLASS_ENUM IClass = XedDecodedInstGetIClass(&T->XedInstruction); 000c3 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 000c7 48 83 c0 30 add rax, 48 ; 00000030H @@ -9561,7 +9545,7 @@ $LN6@NcDebugPri: 000ce e8 00 00 00 00 call xed_decoded_inst_get_iclass 000d3 89 45 44 mov DWORD PTR IClass$2[rbp], eax -; 553 : if (T->Flags & CODE_FLAG_IS_REL_JMP) +; 552 : if (T->Flags & CODE_FLAG_IS_REL_JMP) 000d6 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 000da 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -9569,15 +9553,15 @@ $LN6@NcDebugPri: 000e0 85 c0 test eax, eax 000e2 74 46 je SHORT $LN8@NcDebugPri -; 554 : { -; 555 : SetConsoleTextAttribute(ConsoleHandle, FOREGROUND_GREEN | FOREGROUND_RED); +; 553 : { +; 554 : SetConsoleTextAttribute(ConsoleHandle, FOREGROUND_GREEN | FOREGROUND_RED); 000e4 66 ba 06 00 mov dx, 6 000e8 48 8b 4d 08 mov rcx, QWORD PTR ConsoleHandle$[rbp] 000ec ff 15 00 00 00 00 call QWORD PTR __imp_SetConsoleTextAttribute -; 556 : printf("%s: %u\n", XedIClassEnumToString(IClass), T->Label); +; 555 : printf("%s: %u\n", XedIClassEnumToString(IClass), T->Label); 000f2 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 000f6 8b 40 1c mov eax, DWORD PTR [rax+28] @@ -9595,21 +9579,21 @@ $LN6@NcDebugPri: 00 00 lea rcx, OFFSET FLAT:??_C@_07KNNCJAOA@?$CFs?3?5?$CFu?6@ 00123 e8 00 00 00 00 call printf -; 557 : } +; 556 : } 00128 eb 25 jmp SHORT $LN9@NcDebugPri $LN8@NcDebugPri: -; 558 : else -; 559 : { -; 560 : SetConsoleTextAttribute(ConsoleHandle, FOREGROUND_GREEN | FOREGROUND_BLUE); +; 557 : else +; 558 : { +; 559 : SetConsoleTextAttribute(ConsoleHandle, FOREGROUND_GREEN | FOREGROUND_BLUE); 0012a 66 ba 03 00 mov dx, 3 0012e 48 8b 4d 08 mov rcx, QWORD PTR ConsoleHandle$[rbp] 00132 ff 15 00 00 00 00 call QWORD PTR __imp_SetConsoleTextAttribute -; 561 : printf("%s\n", XedIClassEnumToString(IClass)); +; 560 : printf("%s\n", XedIClassEnumToString(IClass)); 00138 8b 4d 44 mov ecx, DWORD PTR IClass$2[rbp] 0013b e8 00 00 00 00 call xed_iclass_enum_t2str @@ -9620,15 +9604,15 @@ $LN8@NcDebugPri: $LN9@NcDebugPri: $LN7@NcDebugPri: -; 562 : } -; 563 : } -; 564 : } +; 561 : } +; 562 : } +; 563 : } 0014f e9 0d ff ff ff jmp $LN2@NcDebugPri $LN3@NcDebugPri: $LN1@NcDebugPri: -; 565 : } +; 564 : } 00154 48 8d a5 28 01 00 00 lea rsp, QWORD PTR [rbp+296] @@ -9649,7 +9633,7 @@ tv78 = 312 Block$ = 352 ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z PROC ; NcDeleteBlock, COMDAT -; 523 : { +; 522 : { $LN10: 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx @@ -9668,7 +9652,7 @@ $LN10: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 524 : if (!Block->Start || !Block->End) +; 523 : if (!Block->Start || !Block->End) 00036 48 8b 85 60 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -9680,13 +9664,13 @@ $LN10: 0004f 75 05 jne SHORT $LN5@NcDeleteBl $LN6@NcDeleteBl: -; 525 : return; +; 524 : return; 00051 e9 80 00 00 00 jmp $LN1@NcDeleteBl $LN5@NcDeleteBl: -; 526 : -; 527 : PNATIVE_CODE_LINK BlockEnding = Block->End->Next; +; 525 : +; 526 : PNATIVE_CODE_LINK BlockEnding = Block->End->Next; 00056 48 8b 85 60 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -9694,8 +9678,8 @@ $LN5@NcDeleteBl: 00061 48 8b 00 mov rax, QWORD PTR [rax] 00064 48 89 45 08 mov QWORD PTR BlockEnding$[rbp], rax -; 528 : -; 529 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != BlockEnding;) +; 527 : +; 528 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != BlockEnding;) 00068 48 8b 85 60 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -9708,14 +9692,14 @@ $LN2@NcDeleteBl: 00081 48 39 45 28 cmp QWORD PTR T$1[rbp], rax 00085 74 4f je SHORT $LN3@NcDeleteBl -; 530 : { -; 531 : PNATIVE_CODE_LINK Next = T->Next; +; 529 : { +; 530 : PNATIVE_CODE_LINK Next = T->Next; 00087 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 0008b 48 8b 00 mov rax, QWORD PTR [rax] 0008e 48 89 45 48 mov QWORD PTR Next$2[rbp], rax -; 532 : delete T; +; 531 : delete T; 00092 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 00096 48 89 85 28 01 @@ -9736,18 +9720,18 @@ $LN8@NcDeleteBl: 00 mov QWORD PTR tv78[rbp], 0 $LN9@NcDeleteBl: -; 533 : T = Next; +; 532 : T = Next; 000cc 48 8b 45 48 mov rax, QWORD PTR Next$2[rbp] 000d0 48 89 45 28 mov QWORD PTR T$1[rbp], rax -; 534 : } +; 533 : } 000d4 eb a0 jmp SHORT $LN2@NcDeleteBl $LN3@NcDeleteBl: $LN1@NcDeleteBl: -; 535 : } +; 534 : } 000d6 48 8d a5 48 01 00 00 lea rsp, QWORD PTR [rbp+328] @@ -9767,7 +9751,7 @@ Block$ = 320 OutSize$ = 328 ?NcAssemble@@YAPEAXPEAU_NATIVE_CODE_BLOCK@@PEAK@Z PROC ; NcAssemble, COMDAT -; 498 : { +; 497 : { $LN9: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -9787,7 +9771,7 @@ $LN9: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 499 : if (!NcFixRelJmps(Block)) +; 498 : if (!NcFixRelJmps(Block)) 0003b 48 8b 8d 40 01 00 00 mov rcx, QWORD PTR Block$[rbp] @@ -9795,14 +9779,14 @@ $LN9: 00047 85 c0 test eax, eax 00049 75 07 jne SHORT $LN5@NcAssemble -; 500 : return NULL; +; 499 : return NULL; 0004b 33 c0 xor eax, eax 0004d e9 bc 00 00 00 jmp $LN1@NcAssemble $LN5@NcAssemble: -; 501 : -; 502 : *OutSize = NcCalcBlockSize(Block); +; 500 : +; 501 : *OutSize = NcCalcBlockSize(Block); 00052 48 8b 8d 40 01 00 00 mov rcx, QWORD PTR Block$[rbp] @@ -9811,8 +9795,8 @@ $LN5@NcAssemble: 00 00 mov rcx, QWORD PTR OutSize$[rbp] 00065 89 01 mov DWORD PTR [rcx], eax -; 503 : -; 504 : PUCHAR Buffer = (PUCHAR)malloc(*OutSize); +; 502 : +; 503 : PUCHAR Buffer = (PUCHAR)malloc(*OutSize); 00067 48 8b 85 48 01 00 00 mov rax, QWORD PTR OutSize$[rbp] @@ -9822,25 +9806,25 @@ $LN5@NcAssemble: 00 call QWORD PTR __imp_malloc 00078 48 89 45 08 mov QWORD PTR Buffer$[rbp], rax -; 505 : if (!Buffer) +; 504 : if (!Buffer) 0007c 48 83 7d 08 00 cmp QWORD PTR Buffer$[rbp], 0 00081 75 07 jne SHORT $LN6@NcAssemble -; 506 : return NULL; +; 505 : return NULL; 00083 33 c0 xor eax, eax 00085 e9 84 00 00 00 jmp $LN1@NcAssemble $LN6@NcAssemble: -; 507 : -; 508 : PUCHAR BufferOffset = Buffer; +; 506 : +; 507 : PUCHAR BufferOffset = Buffer; 0008a 48 8b 45 08 mov rax, QWORD PTR Buffer$[rbp] 0008e 48 89 45 28 mov QWORD PTR BufferOffset$[rbp], rax -; 509 : -; 510 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) +; 508 : +; 509 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) 00092 48 8b 85 40 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -9861,8 +9845,8 @@ $LN4@NcAssemble: 000c2 48 39 45 48 cmp QWORD PTR T$1[rbp], rax 000c6 74 42 je SHORT $LN3@NcAssemble -; 511 : { -; 512 : if (T->Flags & CODE_FLAG_IS_LABEL) +; 510 : { +; 511 : if (T->Flags & CODE_FLAG_IS_LABEL) 000c8 48 8b 45 48 mov rax, QWORD PTR T$1[rbp] 000cc 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -9870,13 +9854,13 @@ $LN4@NcAssemble: 000d2 85 c0 test eax, eax 000d4 74 02 je SHORT $LN7@NcAssemble -; 513 : continue; +; 512 : continue; 000d6 eb ca jmp SHORT $LN2@NcAssemble $LN7@NcAssemble: -; 514 : -; 515 : RtlCopyMemory(BufferOffset, T->RawData, T->RawDataSize); +; 513 : +; 514 : RtlCopyMemory(BufferOffset, T->RawData, T->RawDataSize); 000d8 48 8b 45 48 mov rax, QWORD PTR T$1[rbp] 000dc 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -9886,7 +9870,7 @@ $LN7@NcAssemble: 000ea 48 8b 4d 28 mov rcx, QWORD PTR BufferOffset$[rbp] 000ee e8 00 00 00 00 call memcpy -; 516 : BufferOffset += T->RawDataSize; +; 515 : BufferOffset += T->RawDataSize; 000f3 48 8b 45 48 mov rax, QWORD PTR T$1[rbp] 000f7 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -9895,18 +9879,18 @@ $LN7@NcAssemble: 00101 48 8b c1 mov rax, rcx 00104 48 89 45 28 mov QWORD PTR BufferOffset$[rbp], rax -; 517 : } +; 516 : } 00108 eb 98 jmp SHORT $LN2@NcAssemble $LN3@NcAssemble: -; 518 : -; 519 : return Buffer; +; 517 : +; 518 : return Buffer; 0010a 48 8b 45 08 mov rax, QWORD PTR Buffer$[rbp] $LN1@NcAssemble: -; 520 : } +; 519 : } 0010e 48 8d a5 28 01 00 00 lea rsp, QWORD PTR [rbp+296] @@ -9936,7 +9920,7 @@ Buffer$ = 520 BufferSize$ = 528 ?NcDisassemble@@YAHPEAU_NATIVE_CODE_BLOCK@@PEAXK@Z PROC ; NcDisassemble, COMDAT -; 466 : { +; 465 : { $LN13: 00000 44 89 44 24 18 mov DWORD PTR [rsp+24], r8d @@ -9957,20 +9941,20 @@ $LN13: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 467 : PUCHAR Buf = (PUCHAR)Buffer; +; 466 : PUCHAR Buf = (PUCHAR)Buffer; 00040 48 8b 85 08 02 00 00 mov rax, QWORD PTR Buffer$[rbp] 00047 48 89 45 08 mov QWORD PTR Buf$[rbp], rax -; 468 : ULONG Offset = 0; +; 467 : ULONG Offset = 0; 0004b c7 45 24 00 00 00 00 mov DWORD PTR Offset$[rbp], 0 $LN2@NcDisassem: -; 469 : -; 470 : while (Offset < BufferSize) +; 468 : +; 469 : while (Offset < BufferSize) 00052 8b 85 10 02 00 00 mov eax, DWORD PTR BufferSize$[rbp] @@ -9978,8 +9962,8 @@ $LN2@NcDisassem: 0005b 0f 83 b8 01 00 00 jae $LN3@NcDisassem -; 471 : { -; 472 : PNATIVE_CODE_LINK Link = new NATIVE_CODE_LINK; +; 470 : { +; 471 : PNATIVE_CODE_LINK Link = new NATIVE_CODE_LINK; 00061 b9 f0 00 00 00 mov ecx, 240 ; 000000f0H 00066 e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new @@ -10007,13 +9991,13 @@ $LN7@NcDisassem: 00 00 mov rax, QWORD PTR $T4[rbp] 000b1 48 89 45 48 mov QWORD PTR Link$1[rbp], rax -; 473 : Link->Flags = CODE_FLAG_IS_INST; +; 472 : Link->Flags = CODE_FLAG_IS_INST; 000b5 48 8b 45 48 mov rax, QWORD PTR Link$1[rbp] 000b9 c7 40 18 04 00 00 00 mov DWORD PTR [rax+24], 4 -; 474 : ULONG PossibleSize = min(15, BufferSize - Offset); +; 473 : ULONG PossibleSize = min(15, BufferSize - Offset); 000c0 8b 45 24 mov eax, DWORD PTR Offset$[rbp] 000c3 8b 8d 10 02 00 @@ -10038,7 +10022,7 @@ $LN9@NcDisassem: 00 mov eax, DWORD PTR tv80[rbp] 000f7 89 45 64 mov DWORD PTR PossibleSize$2[rbp], eax -; 475 : XED_ERROR_ENUM DecodeError = XedDecode(&Link->XedInstruction, (Buf + Offset), PossibleSize); +; 474 : XED_ERROR_ENUM DecodeError = XedDecode(&Link->XedInstruction, (Buf + Offset), PossibleSize); 000fa 8b 45 24 mov eax, DWORD PTR Offset$[rbp] 000fd 48 8b 4d 08 mov rcx, QWORD PTR Buf$[rbp] @@ -10052,14 +10036,14 @@ $LN9@NcDisassem: 0011b 89 85 84 00 00 00 mov DWORD PTR DecodeError$3[rbp], eax -; 476 : if (DecodeError != XED_ERROR_NONE) +; 475 : if (DecodeError != XED_ERROR_NONE) 00121 83 bd 84 00 00 00 00 cmp DWORD PTR DecodeError$3[rbp], 0 00128 74 67 je SHORT $LN4@NcDisassem -; 477 : { -; 478 : printf("XedDecode failed with error %s\n", XedErrorEnumToString(DecodeError)); +; 476 : { +; 477 : printf("XedDecode failed with error %s\n", XedErrorEnumToString(DecodeError)); 0012a 8b 8d 84 00 00 00 mov ecx, DWORD PTR DecodeError$3[rbp] @@ -10069,13 +10053,13 @@ $LN9@NcDisassem: 00 00 lea rcx, OFFSET FLAT:??_C@_0CA@KDIENFLL@XedDecode?5failed?5with?5error?5?$CFs?6@ 0013f e8 00 00 00 00 call printf -; 479 : NcDeleteBlock(Block); +; 478 : NcDeleteBlock(Block); 00144 48 8b 8d 00 02 00 00 mov rcx, QWORD PTR Block$[rbp] 0014b e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 480 : delete Link; +; 479 : delete Link; 00150 48 8b 45 48 mov rax, QWORD PTR Link$1[rbp] 00154 48 89 85 a8 01 @@ -10096,14 +10080,14 @@ $LN10@NcDisassem: 00 mov QWORD PTR tv130[rbp], 0 $LN11@NcDisassem: -; 481 : return FALSE; +; 480 : return FALSE; 0018a 33 c0 xor eax, eax 0018c e9 99 00 00 00 jmp $LN1@NcDisassem $LN4@NcDisassem: -; 482 : } -; 483 : Link->RawDataSize = XedDecodedInstGetLength(&Link->XedInstruction); +; 481 : } +; 482 : Link->RawDataSize = XedDecodedInstGetLength(&Link->XedInstruction); 00191 48 8b 45 48 mov rax, QWORD PTR Link$1[rbp] 00195 48 83 c0 30 add rax, 48 ; 00000030H @@ -10112,7 +10096,7 @@ $LN4@NcDisassem: 001a1 48 8b 4d 48 mov rcx, QWORD PTR Link$1[rbp] 001a5 89 41 28 mov DWORD PTR [rcx+40], eax -; 484 : Link->RawData = new UCHAR[Link->RawDataSize]; +; 483 : Link->RawData = new UCHAR[Link->RawDataSize]; 001a8 48 8b 45 48 mov rax, QWORD PTR Link$1[rbp] 001ac 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -10125,7 +10109,7 @@ $LN4@NcDisassem: 00 00 mov rcx, QWORD PTR $T7[rbp] 001c8 48 89 48 20 mov QWORD PTR [rax+32], rcx -; 485 : RtlCopyMemory(Link->RawData, (Buf + Offset), Link->RawDataSize); +; 484 : RtlCopyMemory(Link->RawData, (Buf + Offset), Link->RawDataSize); 001cc 48 8b 45 48 mov rax, QWORD PTR Link$1[rbp] 001d0 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -10139,16 +10123,16 @@ $LN4@NcDisassem: 001ea 48 8b 48 20 mov rcx, QWORD PTR [rax+32] 001ee e8 00 00 00 00 call memcpy -; 486 : -; 487 : NcAppendToBlock(Block, Link); +; 485 : +; 486 : NcAppendToBlock(Block, Link); 001f3 48 8b 55 48 mov rdx, QWORD PTR Link$1[rbp] 001f7 48 8b 8d 00 02 00 00 mov rcx, QWORD PTR Block$[rbp] 001fe e8 00 00 00 00 call ?NcAppendToBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@@Z ; NcAppendToBlock -; 488 : -; 489 : Offset += Link->RawDataSize; +; 487 : +; 488 : Offset += Link->RawDataSize; 00203 48 8b 45 48 mov rax, QWORD PTR Link$1[rbp] 00207 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -10157,25 +10141,25 @@ $LN4@NcDisassem: 0020f 8b c1 mov eax, ecx 00211 89 45 24 mov DWORD PTR Offset$[rbp], eax -; 490 : } +; 489 : } 00214 e9 39 fe ff ff jmp $LN2@NcDisassem $LN3@NcDisassem: -; 491 : -; 492 : NcCreateLabels(Block); +; 490 : +; 491 : NcCreateLabels(Block); 00219 48 8b 8d 00 02 00 00 mov rcx, QWORD PTR Block$[rbp] 00220 e8 00 00 00 00 call ?NcCreateLabels@@YAHPEAU_NATIVE_CODE_BLOCK@@@Z ; NcCreateLabels -; 493 : -; 494 : return TRUE; +; 492 : +; 493 : return TRUE; 00225 b8 01 00 00 00 mov eax, 1 $LN1@NcDisassem: -; 495 : } +; 494 : } 0022a 48 8d a5 e8 01 00 00 lea rsp, QWORD PTR [rbp+488] @@ -10276,7 +10260,7 @@ __$ArrayPad$ = 1784 Block$ = 1824 ?NcFixRelJmps@@YAHPEAU_NATIVE_CODE_BLOCK@@@Z PROC ; NcFixRelJmps, COMDAT -; 386 : { +; 385 : { $LN21: 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx @@ -10301,7 +10285,7 @@ $LN21: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00043 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 387 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next;) +; 386 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next;) 00048 48 8b 85 20 07 00 00 mov rax, QWORD PTR Block$[rbp] @@ -10319,8 +10303,8 @@ $LN2@NcFixRelJm: 00073 0f 84 04 03 00 00 je $LN3@NcFixRelJm -; 388 : { -; 389 : if (T->Flags & CODE_FLAG_IS_REL_JMP) +; 387 : { +; 388 : if (T->Flags & CODE_FLAG_IS_REL_JMP) 00079 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 0007d 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -10329,13 +10313,13 @@ $LN2@NcFixRelJm: 00085 0f 84 e2 02 00 00 je $LN7@NcFixRelJm -; 390 : { -; 391 : INT32 BranchDisp = 0; +; 389 : { +; 390 : INT32 BranchDisp = 0; 0008b c7 45 24 00 00 00 00 mov DWORD PTR BranchDisp$10[rbp], 0 -; 392 : if (!NcGetDeltaToLabel(T, &BranchDisp)) +; 391 : if (!NcGetDeltaToLabel(T, &BranchDisp)) 00092 48 8d 55 24 lea rdx, QWORD PTR BranchDisp$10[rbp] 00096 48 8b 4d 08 mov rcx, QWORD PTR T$9[rbp] @@ -10343,14 +10327,14 @@ $LN2@NcFixRelJm: 0009f 85 c0 test eax, eax 000a1 75 07 jne SHORT $LN8@NcFixRelJm -; 393 : return FALSE; +; 392 : return FALSE; 000a3 33 c0 xor eax, eax 000a5 e9 d8 02 00 00 jmp $LN1@NcFixRelJm $LN8@NcFixRelJm: -; 394 : -; 395 : ULONG DispWidth = XedDecodedInstGetBranchDisplacementWidthBits(&T->XedInstruction); +; 393 : +; 394 : ULONG DispWidth = XedDecodedInstGetBranchDisplacementWidthBits(&T->XedInstruction); 000aa 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 000ae 48 83 c0 30 add rax, 48 ; 00000030H @@ -10358,7 +10342,7 @@ $LN8@NcFixRelJm: 000b5 e8 00 00 00 00 call xed_decoded_inst_get_branch_displacement_width_bits 000ba 89 45 44 mov DWORD PTR DispWidth$11[rbp], eax -; 396 : if (log2(abs(BranchDisp)) + 1 > DispWidth) +; 395 : if (log2(abs(BranchDisp)) + 1 > DispWidth) 000bd 8b 4d 24 mov ecx, DWORD PTR BranchDisp$10[rbp] 000c0 e8 00 00 00 00 call abs @@ -10372,30 +10356,30 @@ $LN8@NcFixRelJm: 000e0 0f 86 f3 01 00 00 jbe $LN9@NcFixRelJm -; 397 : { -; 398 : //duh oh -; 399 : if (DispWidth == 32) +; 396 : { +; 397 : //duh oh +; 398 : if (DispWidth == 32) 000e6 83 7d 44 20 cmp DWORD PTR DispWidth$11[rbp], 32 ; 00000020H 000ea 75 07 jne SHORT $LN11@NcFixRelJm -; 400 : return FALSE; +; 399 : return FALSE; 000ec 33 c0 xor eax, eax 000ee e9 8f 02 00 00 jmp $LN1@NcFixRelJm $LN11@NcFixRelJm: -; 401 : -; 402 : //Grow displacement width to required size -; 403 : DispWidth *= 2; +; 400 : +; 401 : //Grow displacement width to required size +; 402 : DispWidth *= 2; 000f3 8b 45 44 mov eax, DWORD PTR DispWidth$11[rbp] 000f6 d1 e0 shl eax, 1 000f8 89 45 44 mov DWORD PTR DispWidth$11[rbp], eax -; 404 : -; 405 : //Check again -; 406 : if (log2(abs(BranchDisp)) + 1 > DispWidth) +; 403 : +; 404 : //Check again +; 405 : if (log2(abs(BranchDisp)) + 1 > DispWidth) 000fb 8b 4d 24 mov ecx, DWORD PTR BranchDisp$10[rbp] 000fe e8 00 00 00 00 call abs @@ -10408,46 +10392,46 @@ $LN11@NcFixRelJm: 0011a 66 0f 2f c1 comisd xmm0, xmm1 0011e 76 15 jbe SHORT $LN12@NcFixRelJm -; 407 : { -; 408 : if (DispWidth == 32) +; 406 : { +; 407 : if (DispWidth == 32) 00120 83 7d 44 20 cmp DWORD PTR DispWidth$11[rbp], 32 ; 00000020H 00124 75 07 jne SHORT $LN13@NcFixRelJm -; 409 : return FALSE; +; 408 : return FALSE; 00126 33 c0 xor eax, eax 00128 e9 55 02 00 00 jmp $LN1@NcFixRelJm $LN13@NcFixRelJm: -; 410 : -; 411 : //Grow once more if not already at 32 -; 412 : DispWidth *= 2; +; 409 : +; 410 : //Grow once more if not already at 32 +; 411 : DispWidth *= 2; 0012d 8b 45 44 mov eax, DWORD PTR DispWidth$11[rbp] 00130 d1 e0 shl eax, 1 00132 89 45 44 mov DWORD PTR DispWidth$11[rbp], eax $LN12@NcFixRelJm: -; 413 : } -; 414 : -; 415 : //Encode new instruction -; 416 : XED_STATE MachineState; -; 417 : MachineState.mmode = XED_MACHINE_MODE_LONG_64; +; 412 : } +; 413 : +; 414 : //Encode new instruction +; 415 : XED_STATE MachineState; +; 416 : MachineState.mmode = XED_MACHINE_MODE_LONG_64; 00135 c7 45 68 01 00 00 00 mov DWORD PTR MachineState$12[rbp], 1 -; 418 : MachineState.stack_addr_width = XED_ADDRESS_WIDTH_64b; +; 417 : MachineState.stack_addr_width = XED_ADDRESS_WIDTH_64b; 0013c c7 45 6c 08 00 00 00 mov DWORD PTR MachineState$12[rbp+4], 8 -; 419 : XED_ENCODER_INSTRUCTION EncoderInstruction; -; 420 : XED_ENCODER_REQUEST EncoderRequest; -; 421 : UCHAR EncodeBuffer[15]; -; 422 : UINT ReturnedSize; -; 423 : XED_ICLASS_ENUM IClass = XedDecodedInstGetIClass(&T->XedInstruction); +; 418 : XED_ENCODER_INSTRUCTION EncoderInstruction; +; 419 : XED_ENCODER_REQUEST EncoderRequest; +; 420 : UCHAR EncodeBuffer[15]; +; 421 : UINT ReturnedSize; +; 422 : XED_ICLASS_ENUM IClass = XedDecodedInstGetIClass(&T->XedInstruction); 00143 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00147 48 83 c0 30 add rax, 48 ; 00000030H @@ -10456,9 +10440,9 @@ $LN12@NcFixRelJm: 00153 89 85 74 03 00 00 mov DWORD PTR IClass$17[rbp], eax -; 424 : -; 425 : //Do the encoding -; 426 : XedInst1(&EncoderInstruction, MachineState, IClass, DispWidth, XedRelBr(0, DispWidth)); +; 423 : +; 424 : //Do the encoding +; 425 : XedInst1(&EncoderInstruction, MachineState, IClass, DispWidth, XedRelBr(0, DispWidth)); 00159 44 8b 45 44 mov r8d, DWORD PTR DispWidth$11[rbp] 0015d 33 d2 xor edx, edx @@ -10490,14 +10474,14 @@ $LN12@NcFixRelJm: 00 00 lea rcx, QWORD PTR EncoderInstruction$13[rbp] 001bc e8 00 00 00 00 call xed_inst1 -; 427 : XedEncoderRequestZeroSetMode(&EncoderRequest, &MachineState); +; 426 : XedEncoderRequestZeroSetMode(&EncoderRequest, &MachineState); 001c1 48 8d 55 68 lea rdx, QWORD PTR MachineState$12[rbp] 001c5 48 8d 8d 50 02 00 00 lea rcx, QWORD PTR EncoderRequest$14[rbp] 001cc e8 00 00 00 00 call xed_encoder_request_zero_set_mode -; 428 : if (!XedConvertToEncoderRequest(&EncoderRequest, &EncoderInstruction)) +; 427 : if (!XedConvertToEncoderRequest(&EncoderRequest, &EncoderInstruction)) 001d1 48 8d 95 90 00 00 00 lea rdx, QWORD PTR EncoderInstruction$13[rbp] @@ -10507,13 +10491,13 @@ $LN12@NcFixRelJm: 001e4 85 c0 test eax, eax 001e6 75 07 jne SHORT $LN14@NcFixRelJm -; 429 : return FALSE; +; 428 : return FALSE; 001e8 33 c0 xor eax, eax 001ea e9 93 01 00 00 jmp $LN1@NcFixRelJm $LN14@NcFixRelJm: -; 430 : if (XED_ERROR_NONE != XedEncode(&EncoderRequest, EncodeBuffer, 15, &ReturnedSize)) +; 429 : if (XED_ERROR_NONE != XedEncode(&EncoderRequest, EncodeBuffer, 15, &ReturnedSize)) 001ef 4c 8d 8d 54 03 00 00 lea r9, QWORD PTR ReturnedSize$16[rbp] @@ -10527,15 +10511,15 @@ $LN14@NcFixRelJm: 0020f 85 c0 test eax, eax 00211 74 07 je SHORT $LN15@NcFixRelJm -; 431 : return FALSE; +; 430 : return FALSE; 00213 33 c0 xor eax, eax 00215 e9 68 01 00 00 jmp $LN1@NcFixRelJm $LN15@NcFixRelJm: -; 432 : -; 433 : //fixup T->RawData -; 434 : delete[] T->RawData; +; 431 : +; 432 : //fixup T->RawData +; 433 : delete[] T->RawData; 0021a 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 0021e 48 8b 40 20 mov rax, QWORD PTR [rax+32] @@ -10545,14 +10529,14 @@ $LN15@NcFixRelJm: 00 00 mov rcx, QWORD PTR $T20[rbp] 00230 e8 00 00 00 00 call ??_V@YAXPEAX@Z ; operator delete[] -; 435 : T->RawDataSize = ReturnedSize; +; 434 : T->RawDataSize = ReturnedSize; 00235 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00239 8b 8d 54 03 00 00 mov ecx, DWORD PTR ReturnedSize$16[rbp] 0023f 89 48 28 mov DWORD PTR [rax+40], ecx -; 436 : T->RawData = new UCHAR[ReturnedSize]; +; 435 : T->RawData = new UCHAR[ReturnedSize]; 00242 8b 85 54 03 00 00 mov eax, DWORD PTR ReturnedSize$16[rbp] @@ -10565,7 +10549,7 @@ $LN15@NcFixRelJm: 00 00 mov rcx, QWORD PTR $T21[rbp] 00261 48 89 48 20 mov QWORD PTR [rax+32], rcx -; 437 : RtlCopyMemory(T->RawData, EncodeBuffer, ReturnedSize); +; 436 : RtlCopyMemory(T->RawData, EncodeBuffer, ReturnedSize); 00265 8b 85 54 03 00 00 mov eax, DWORD PTR ReturnedSize$16[rbp] @@ -10576,9 +10560,9 @@ $LN15@NcFixRelJm: 00279 48 8b 48 20 mov rcx, QWORD PTR [rax+32] 0027d e8 00 00 00 00 call memcpy -; 438 : -; 439 : //Decode instruction so its proper and all that -; 440 : XedDecodedInstZeroSetMode(&T->XedInstruction, &MachineState); +; 437 : +; 438 : //Decode instruction so its proper and all that +; 439 : XedDecodedInstZeroSetMode(&T->XedInstruction, &MachineState); 00282 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00286 48 83 c0 30 add rax, 48 ; 00000030H @@ -10586,7 +10570,7 @@ $LN15@NcFixRelJm: 0028e 48 8b c8 mov rcx, rax 00291 e8 00 00 00 00 call xed_decoded_inst_zero_set_mode -; 441 : if (XED_ERROR_NONE != XedDecode(&T->XedInstruction, T->RawData, T->RawDataSize)) +; 440 : if (XED_ERROR_NONE != XedDecode(&T->XedInstruction, T->RawData, T->RawDataSize)) 00296 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 0029a 48 83 c0 30 add rax, 48 ; 00000030H @@ -10599,33 +10583,33 @@ $LN15@NcFixRelJm: 002b6 85 c0 test eax, eax 002b8 74 07 je SHORT $LN16@NcFixRelJm -; 442 : return FALSE; +; 441 : return FALSE; 002ba 33 c0 xor eax, eax 002bc e9 c1 00 00 00 jmp $LN1@NcFixRelJm $LN16@NcFixRelJm: -; 443 : -; 444 : //Go back to the start and loop through all labels again because now this instruction is larger :)))) -; 445 : T = Block->Start; +; 442 : +; 443 : //Go back to the start and loop through all labels again because now this instruction is larger :)))) +; 444 : T = Block->Start; 002c1 48 8b 85 20 07 00 00 mov rax, QWORD PTR Block$[rbp] 002c8 48 8b 00 mov rax, QWORD PTR [rax] 002cb 48 89 45 08 mov QWORD PTR T$9[rbp], rax -; 446 : continue; +; 445 : continue; 002cf e9 82 fd ff ff jmp $LN2@NcFixRelJm -; 447 : } +; 446 : } 002d4 e9 94 00 00 00 jmp $LN10@NcFixRelJm $LN9@NcFixRelJm: -; 448 : else -; 449 : { -; 450 : DispWidth = XedDecodedInstGetBranchDisplacementWidth(&T->XedInstruction); +; 447 : else +; 448 : { +; 449 : DispWidth = XedDecodedInstGetBranchDisplacementWidth(&T->XedInstruction); 002d9 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 002dd 48 83 c0 30 add rax, 48 ; 00000030H @@ -10633,7 +10617,7 @@ $LN9@NcFixRelJm: 002e4 e8 00 00 00 00 call xed_decoded_inst_get_branch_displacement_width 002e9 89 45 44 mov DWORD PTR DispWidth$11[rbp], eax -; 451 : switch (DispWidth) +; 450 : switch (DispWidth) 002ec 8b 45 44 mov eax, DWORD PTR DispWidth$11[rbp] 002ef 89 85 f4 06 00 @@ -10650,8 +10634,8 @@ $LN9@NcFixRelJm: 00310 eb 5b jmp SHORT $LN5@NcFixRelJm $LN17@NcFixRelJm: -; 452 : { -; 453 : case 1: *(PINT8)&T->RawData[T->RawDataSize - DispWidth] = (INT8)BranchDisp; break; +; 451 : { +; 452 : case 1: *(PINT8)&T->RawData[T->RawDataSize - DispWidth] = (INT8)BranchDisp; break; 00312 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00316 8b 4d 44 mov ecx, DWORD PTR DispWidth$11[rbp] @@ -10665,7 +10649,7 @@ $LN17@NcFixRelJm: 0032f eb 3c jmp SHORT $LN5@NcFixRelJm $LN18@NcFixRelJm: -; 454 : case 2: *(PINT16)&T->RawData[T->RawDataSize - DispWidth] = (INT16)BranchDisp; break; +; 453 : case 2: *(PINT16)&T->RawData[T->RawDataSize - DispWidth] = (INT16)BranchDisp; break; 00331 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00335 8b 4d 44 mov ecx, DWORD PTR DispWidth$11[rbp] @@ -10679,7 +10663,7 @@ $LN18@NcFixRelJm: 0034f eb 1c jmp SHORT $LN5@NcFixRelJm $LN19@NcFixRelJm: -; 455 : case 4: *(PINT32)&T->RawData[T->RawDataSize - DispWidth] = (INT32)BranchDisp; break; +; 454 : case 4: *(PINT32)&T->RawData[T->RawDataSize - DispWidth] = (INT32)BranchDisp; break; 00351 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00355 8b 4d 44 mov ecx, DWORD PTR DispWidth$11[rbp] @@ -10694,27 +10678,27 @@ $LN5@NcFixRelJm: $LN10@NcFixRelJm: $LN7@NcFixRelJm: -; 456 : } -; 457 : } -; 458 : } -; 459 : -; 460 : T = T->Next; +; 455 : } +; 456 : } +; 457 : } +; 458 : +; 459 : T = T->Next; 0036d 48 8b 45 08 mov rax, QWORD PTR T$9[rbp] 00371 48 8b 00 mov rax, QWORD PTR [rax] 00374 48 89 45 08 mov QWORD PTR T$9[rbp], rax -; 461 : } +; 460 : } 00378 e9 d9 fc ff ff jmp $LN2@NcFixRelJm $LN3@NcFixRelJm: -; 462 : return TRUE; +; 461 : return TRUE; 0037d b8 01 00 00 00 mov eax, 1 $LN1@NcFixRelJm: -; 463 : } +; 462 : } 00382 48 8b f8 mov rdi, rax 00385 48 8d 4d d0 lea rcx, QWORD PTR [rbp-48] @@ -10745,7 +10729,7 @@ Link$ = 320 DeltaOut$ = 328 ?NcGetDeltaToLabel@@YAHPEAU_NATIVE_CODE_LINK@@PEAH@Z PROC ; NcGetDeltaToLabel, COMDAT -; 350 : { +; 349 : { $LN13: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -10765,13 +10749,13 @@ $LN13: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 351 : INT32 Delta = 0; +; 350 : INT32 Delta = 0; 0003b c7 45 04 00 00 00 00 mov DWORD PTR Delta$[rbp], 0 -; 352 : //First checking backwards because I feel like thats the direction most jmps are in -; 353 : for (PNATIVE_CODE_LINK T = Link; T; T = T->Prev) +; 351 : //First checking backwards because I feel like thats the direction most jmps are in +; 352 : for (PNATIVE_CODE_LINK T = Link; T; T = T->Prev) 00042 48 8b 85 40 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -10785,8 +10769,8 @@ $LN4@NcGetDelta: 0005b 48 83 7d 28 00 cmp QWORD PTR T$1[rbp], 0 00060 74 4c je SHORT $LN3@NcGetDelta -; 354 : { -; 355 : if (T->Flags & CODE_FLAG_IS_LABEL) +; 353 : { +; 354 : if (T->Flags & CODE_FLAG_IS_LABEL) 00062 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 00066 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -10794,8 +10778,8 @@ $LN4@NcGetDelta: 0006c 85 c0 test eax, eax 0006e 74 2b je SHORT $LN8@NcGetDelta -; 356 : { -; 357 : if (T->Label == Link->Label) +; 355 : { +; 356 : if (T->Label == Link->Label) 00070 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 00074 48 8b 8d 40 01 @@ -10804,28 +10788,28 @@ $LN4@NcGetDelta: 0007e 39 48 1c cmp DWORD PTR [rax+28], ecx 00081 75 16 jne SHORT $LN9@NcGetDelta -; 358 : { -; 359 : *DeltaOut = Delta; +; 357 : { +; 358 : *DeltaOut = Delta; 00083 48 8b 85 48 01 00 00 mov rax, QWORD PTR DeltaOut$[rbp] 0008a 8b 4d 04 mov ecx, DWORD PTR Delta$[rbp] 0008d 89 08 mov DWORD PTR [rax], ecx -; 360 : return TRUE; +; 359 : return TRUE; 0008f b8 01 00 00 00 mov eax, 1 00094 e9 89 00 00 00 jmp $LN1@NcGetDelta $LN9@NcGetDelta: -; 361 : } -; 362 : continue; +; 360 : } +; 361 : continue; 00099 eb b4 jmp SHORT $LN2@NcGetDelta $LN8@NcGetDelta: -; 363 : } -; 364 : Delta -= T->RawDataSize; +; 362 : } +; 363 : Delta -= T->RawDataSize; 0009b 48 8b 45 28 mov rax, QWORD PTR T$1[rbp] 0009f 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -10834,19 +10818,19 @@ $LN8@NcGetDelta: 000a7 8b c1 mov eax, ecx 000a9 89 45 04 mov DWORD PTR Delta$[rbp], eax -; 365 : } +; 364 : } 000ac eb a1 jmp SHORT $LN2@NcGetDelta $LN3@NcGetDelta: -; 366 : -; 367 : //Now check forwards -; 368 : Delta = 0; +; 365 : +; 366 : //Now check forwards +; 367 : Delta = 0; 000ae c7 45 04 00 00 00 00 mov DWORD PTR Delta$[rbp], 0 -; 369 : for (PNATIVE_CODE_LINK T = Link->Next; T; T = T->Next) +; 368 : for (PNATIVE_CODE_LINK T = Link->Next; T; T = T->Next) 000b5 48 8b 85 40 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -10861,8 +10845,8 @@ $LN7@NcGetDelta: 000d0 48 83 7d 48 00 cmp QWORD PTR T$2[rbp], 0 000d5 74 49 je SHORT $LN6@NcGetDelta -; 370 : { -; 371 : if (T->Flags & CODE_FLAG_IS_LABEL) +; 369 : { +; 370 : if (T->Flags & CODE_FLAG_IS_LABEL) 000d7 48 8b 45 48 mov rax, QWORD PTR T$2[rbp] 000db 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -10870,8 +10854,8 @@ $LN7@NcGetDelta: 000e1 85 c0 test eax, eax 000e3 74 28 je SHORT $LN10@NcGetDelta -; 372 : { -; 373 : if (T->Label == Link->Label) +; 371 : { +; 372 : if (T->Label == Link->Label) 000e5 48 8b 45 48 mov rax, QWORD PTR T$2[rbp] 000e9 48 8b 8d 40 01 @@ -10880,28 +10864,28 @@ $LN7@NcGetDelta: 000f3 39 48 1c cmp DWORD PTR [rax+28], ecx 000f6 75 13 jne SHORT $LN11@NcGetDelta -; 374 : { -; 375 : *DeltaOut = Delta; +; 373 : { +; 374 : *DeltaOut = Delta; 000f8 48 8b 85 48 01 00 00 mov rax, QWORD PTR DeltaOut$[rbp] 000ff 8b 4d 04 mov ecx, DWORD PTR Delta$[rbp] 00102 89 08 mov DWORD PTR [rax], ecx -; 376 : return TRUE; +; 375 : return TRUE; 00104 b8 01 00 00 00 mov eax, 1 00109 eb 17 jmp SHORT $LN1@NcGetDelta $LN11@NcGetDelta: -; 377 : } -; 378 : continue; +; 376 : } +; 377 : continue; 0010b eb b8 jmp SHORT $LN5@NcGetDelta $LN10@NcGetDelta: -; 379 : } -; 380 : Delta += T->RawDataSize; +; 378 : } +; 379 : Delta += T->RawDataSize; 0010d 48 8b 45 48 mov rax, QWORD PTR T$2[rbp] 00111 8b 40 28 mov eax, DWORD PTR [rax+40] @@ -10910,17 +10894,17 @@ $LN10@NcGetDelta: 00119 8b c1 mov eax, ecx 0011b 89 45 04 mov DWORD PTR Delta$[rbp], eax -; 381 : } +; 380 : } 0011e eb a5 jmp SHORT $LN5@NcGetDelta $LN6@NcGetDelta: -; 382 : return FALSE; +; 381 : return FALSE; 00120 33 c0 xor eax, eax $LN1@NcGetDelta: -; 383 : } +; 382 : } 00122 48 8d a5 28 01 00 00 lea rsp, QWORD PTR [rbp+296] @@ -10937,7 +10921,7 @@ Block$ = 224 BlockCopy$ = 232 ?NcDeepCopyBlock@@YAHPEAU_NATIVE_CODE_BLOCK@@0@Z PROC ; NcDeepCopyBlock, COMDAT -; 345 : { +; 344 : { $LN3: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -10957,7 +10941,7 @@ $LN3: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00036 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 346 : return NcDeepCopyPartialBlock(Block->Start, Block->End, BlockCopy); +; 345 : return NcDeepCopyPartialBlock(Block->Start, Block->End, BlockCopy); 0003b 4c 8b 85 e8 00 00 00 mov r8, QWORD PTR BlockCopy$[rbp] @@ -10969,7 +10953,7 @@ $LN3: 00054 48 8b 08 mov rcx, QWORD PTR [rax] 00057 e8 00 00 00 00 call ?NcDeepCopyPartialBlock@@YAHPEAU_NATIVE_CODE_LINK@@0PEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeepCopyPartialBlock -; 347 : } +; 346 : } 0005c 48 8d a5 c8 00 00 00 lea rsp, QWORD PTR [rbp+200] @@ -10995,7 +10979,7 @@ End$ = 440 Block$ = 448 ?NcDeepCopyPartialBlock@@YAHPEAU_NATIVE_CODE_LINK@@0PEAU_NATIVE_CODE_BLOCK@@@Z PROC ; NcDeepCopyPartialBlock, COMDAT -; 320 : { +; 319 : { $LN12: 00000 4c 89 44 24 18 mov QWORD PTR [rsp+24], r8 @@ -11021,7 +11005,7 @@ $LN12: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 0004c e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 321 : if (!Start || !End || !Start->Block || Start->Block != End->Block || !Block) +; 320 : if (!Start || !End || !Start->Block || Start->Block != End->Block || !Block) 00051 48 83 bd b0 01 00 00 00 cmp QWORD PTR Start$[rbp], 0 @@ -11045,14 +11029,14 @@ $LN12: 00093 75 07 jne SHORT $LN8@NcDeepCopy $LN9@NcDeepCopy: -; 322 : return FALSE; +; 321 : return FALSE; 00095 33 c0 xor eax, eax 00097 e9 27 01 00 00 jmp $LN1@NcDeepCopy $LN8@NcDeepCopy: -; 323 : -; 324 : Block->LabelIds.clear(); +; 322 : +; 323 : Block->LabelIds.clear(); 0009c 48 8b 85 c0 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -11060,7 +11044,7 @@ $LN8@NcDeepCopy: 000a7 48 8b c8 mov rcx, rax 000aa e8 00 00 00 00 call ?clear@?$vector@KV?$allocator@K@std@@@std@@QEAAXXZ ; std::vector >::clear -; 325 : Block->Start = Block->End = NULL; +; 324 : Block->Start = Block->End = NULL; 000af 48 8b 85 c0 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -11071,8 +11055,8 @@ $LN8@NcDeepCopy: 000c5 48 c7 00 00 00 00 00 mov QWORD PTR [rax], 0 -; 326 : -; 327 : for (ULONG L : Start->Block->LabelIds) +; 325 : +; 326 : for (ULONG L : Start->Block->LabelIds) 000cc 48 8b 85 b0 01 00 00 mov rax, QWORD PTR Start$[rbp] @@ -11098,7 +11082,7 @@ $LN4@NcDeepCopy: 00115 8b 00 mov eax, DWORD PTR [rax] 00117 89 45 64 mov DWORD PTR L$7[rbp], eax -; 328 : Block->LabelIds.push_back(L); +; 327 : Block->LabelIds.push_back(L); 0011a 48 8b 85 c0 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -11112,8 +11096,8 @@ $LN4@NcDeepCopy: 0013c eb bd jmp SHORT $LN2@NcDeepCopy $LN3@NcDeepCopy: -; 329 : -; 330 : for (PNATIVE_CODE_LINK CurLink = Start; CurLink && CurLink != End->Next; CurLink = CurLink->Next) +; 328 : +; 329 : for (PNATIVE_CODE_LINK CurLink = Start; CurLink && CurLink != End->Next; CurLink = CurLink->Next) 0013e 48 8b 85 b0 01 00 00 mov rax, QWORD PTR Start$[rbp] @@ -11137,8 +11121,8 @@ $LN7@NcDeepCopy: 00 00 cmp QWORD PTR CurLink$8[rbp], rax 0017a 74 42 je SHORT $LN6@NcDeepCopy -; 331 : { -; 332 : PNATIVE_CODE_LINK Temp = NcDeepCopyLink(CurLink); +; 330 : { +; 331 : PNATIVE_CODE_LINK Temp = NcDeepCopyLink(CurLink); 0017c 48 8b 8d 88 00 00 00 mov rcx, QWORD PTR CurLink$8[rbp] @@ -11146,27 +11130,27 @@ $LN7@NcDeepCopy: 00188 48 89 85 a8 00 00 00 mov QWORD PTR Temp$9[rbp], rax -; 333 : if (!Temp) +; 332 : if (!Temp) 0018f 48 83 bd a8 00 00 00 00 cmp QWORD PTR Temp$9[rbp], 0 00197 75 10 jne SHORT $LN10@NcDeepCopy -; 334 : { -; 335 : NcDeleteBlock(Block); +; 333 : { +; 334 : NcDeleteBlock(Block); 00199 48 8b 8d c0 01 00 00 mov rcx, QWORD PTR Block$[rbp] 001a0 e8 00 00 00 00 call ?NcDeleteBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@@Z ; NcDeleteBlock -; 336 : return FALSE; +; 335 : return FALSE; 001a5 33 c0 xor eax, eax 001a7 eb 1a jmp SHORT $LN1@NcDeepCopy $LN10@NcDeepCopy: -; 337 : } -; 338 : NcAppendToBlock(Block, Temp); +; 336 : } +; 337 : NcAppendToBlock(Block, Temp); 001a9 48 8b 95 a8 00 00 00 mov rdx, QWORD PTR Temp$9[rbp] @@ -11174,18 +11158,18 @@ $LN10@NcDeepCopy: 00 00 mov rcx, QWORD PTR Block$[rbp] 001b7 e8 00 00 00 00 call ?NcAppendToBlock@@YAXPEAU_NATIVE_CODE_BLOCK@@PEAU_NATIVE_CODE_LINK@@@Z ; NcAppendToBlock -; 339 : } +; 338 : } 001bc eb 90 jmp SHORT $LN5@NcDeepCopy $LN6@NcDeepCopy: -; 340 : -; 341 : return TRUE; +; 339 : +; 340 : return TRUE; 001be b8 01 00 00 00 mov eax, 1 $LN1@NcDeepCopy: -; 342 : } +; 341 : } 001c3 48 8b f8 mov rdi, rax 001c6 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] @@ -11223,7 +11207,7 @@ tv81 = 408 Link$ = 448 ?NcDeepCopyLink@@YAPEAU_NATIVE_CODE_LINK@@PEAU1@@Z PROC ; NcDeepCopyLink, COMDAT -; 299 : { +; 298 : { $LN14: 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx @@ -11242,7 +11226,7 @@ $LN14: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00031 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 300 : if (Link->Flags & CODE_FLAG_IS_LABEL) +; 299 : if (Link->Flags & CODE_FLAG_IS_LABEL) 00036 48 8b 85 c0 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -11251,8 +11235,8 @@ $LN14: 00043 85 c0 test eax, eax 00045 74 67 je SHORT $LN2@NcDeepCopy -; 301 : { -; 302 : return new NATIVE_CODE_LINK(Link->Label, NULL); +; 300 : { +; 301 : return new NATIVE_CODE_LINK(Link->Label, NULL); 00047 b9 f0 00 00 00 mov ecx, 240 ; 000000f0H 0004c e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new @@ -11284,14 +11268,14 @@ $LN7@NcDeepCopy: 00 00 mov rax, QWORD PTR $T3[rbp] 000a4 e9 3c 01 00 00 jmp $LN1@NcDeepCopy -; 303 : } +; 302 : } 000a9 e9 37 01 00 00 jmp $LN1@NcDeepCopy $LN2@NcDeepCopy: -; 304 : else -; 305 : { -; 306 : PNATIVE_CODE_LINK NewLink = new NATIVE_CODE_LINK(Link->Flags, Link->RawData, Link->RawDataSize); +; 303 : else +; 304 : { +; 305 : PNATIVE_CODE_LINK NewLink = new NATIVE_CODE_LINK(Link->Flags, Link->RawData, Link->RawDataSize); 000ae b9 f0 00 00 00 mov ecx, 240 ; 000000f0H 000b3 e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new @@ -11330,7 +11314,7 @@ $LN9@NcDeepCopy: 00 00 mov rax, QWORD PTR $T5[rbp] 00126 48 89 45 08 mov QWORD PTR NewLink$1[rbp], rax -; 307 : NewLink->Label = Link->Label; +; 306 : NewLink->Label = Link->Label; 0012a 48 8b 45 08 mov rax, QWORD PTR NewLink$1[rbp] 0012e 48 8b 8d c0 01 @@ -11338,7 +11322,7 @@ $LN9@NcDeepCopy: 00135 8b 49 1c mov ecx, DWORD PTR [rcx+28] 00138 89 48 1c mov DWORD PTR [rax+28], ecx -; 308 : XED_ERROR_ENUM DecodeError = XedDecode(&NewLink->XedInstruction, Link->RawData, Link->RawDataSize); +; 307 : XED_ERROR_ENUM DecodeError = XedDecode(&NewLink->XedInstruction, Link->RawData, Link->RawDataSize); 0013b 48 8b 45 08 mov rax, QWORD PTR NewLink$1[rbp] 0013f 48 83 c0 30 add rax, 48 ; 00000030H @@ -11352,13 +11336,13 @@ $LN9@NcDeepCopy: 0015c e8 00 00 00 00 call xed_decode 00161 89 45 24 mov DWORD PTR DecodeError$2[rbp], eax -; 309 : if (DecodeError != XED_ERROR_NONE) +; 308 : if (DecodeError != XED_ERROR_NONE) 00164 83 7d 24 00 cmp DWORD PTR DecodeError$2[rbp], 0 00168 74 77 je SHORT $LN4@NcDeepCopy -; 310 : { -; 311 : printf("XedDecode failed in NcDeepCopyLink: %s %u\n", XedErrorEnumToString(DecodeError), Link->RawDataSize); +; 309 : { +; 310 : printf("XedDecode failed in NcDeepCopyLink: %s %u\n", XedErrorEnumToString(DecodeError), Link->RawDataSize); 0016a 48 8b 85 c0 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -11377,7 +11361,7 @@ $LN9@NcDeepCopy: 00 00 lea rcx, OFFSET FLAT:??_C@_0CL@COPJALEP@XedDecode?5failed?5in?5NcDeepCopyL@ 0019e e8 00 00 00 00 call printf -; 312 : delete NewLink; +; 311 : delete NewLink; 001a3 48 8b 45 08 mov rax, QWORD PTR NewLink$1[rbp] 001a7 48 89 85 88 01 @@ -11398,20 +11382,20 @@ $LN10@NcDeepCopy: 00 mov QWORD PTR tv155[rbp], 0 $LN11@NcDeepCopy: -; 313 : return NULL; +; 312 : return NULL; 001dd 33 c0 xor eax, eax 001df eb 04 jmp SHORT $LN1@NcDeepCopy $LN4@NcDeepCopy: -; 314 : } -; 315 : return NewLink; +; 313 : } +; 314 : return NewLink; 001e1 48 8b 45 08 mov rax, QWORD PTR NewLink$1[rbp] $LN1@NcDeepCopy: -; 316 : } -; 317 : } +; 315 : } +; 316 : } 001e5 48 8d a5 a8 01 00 00 lea rsp, QWORD PTR [rbp+424] @@ -11559,7 +11543,7 @@ Jmp$ = 256 Delta$ = 264 ?NcValidateJmp@@YAPEAU_NATIVE_CODE_LINK@@PEAU1@H@Z PROC ; NcValidateJmp, COMDAT -; 259 : { +; 258 : { $LN23: 00000 89 54 24 10 mov DWORD PTR [rsp+16], edx @@ -11579,16 +11563,16 @@ $LN23: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00035 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 260 : PNATIVE_CODE_LINK T; -; 261 : if (Delta > 0) +; 259 : PNATIVE_CODE_LINK T; +; 260 : if (Delta > 0) 0003a 83 bd 08 01 00 00 00 cmp DWORD PTR Delta$[rbp], 0 00041 0f 8e a2 00 00 00 jle $LN10@NcValidate -; 262 : { -; 263 : T = Jmp->Next; +; 261 : { +; 262 : T = Jmp->Next; 00047 48 8b 85 00 01 00 00 mov rax, QWORD PTR Jmp$[rbp] @@ -11597,7 +11581,7 @@ $LN23: $LN21@NcValidate: $LN2@NcValidate: -; 264 : while (Delta > 0 && T) +; 263 : while (Delta > 0 && T) 00055 83 bd 08 01 00 00 00 cmp DWORD PTR Delta$[rbp], 0 @@ -11605,8 +11589,8 @@ $LN2@NcValidate: 0005e 48 83 7d 08 00 cmp QWORD PTR T$[rbp], 0 00063 74 3d je SHORT $LN3@NcValidate -; 265 : { -; 266 : if (T->Flags & CODE_FLAG_IS_LABEL) +; 264 : { +; 265 : if (T->Flags & CODE_FLAG_IS_LABEL) 00065 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 00069 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -11614,12 +11598,12 @@ $LN2@NcValidate: 0006f 85 c0 test eax, eax 00071 74 02 je SHORT $LN12@NcValidate -; 267 : continue; +; 266 : continue; 00073 eb e0 jmp SHORT $LN2@NcValidate $LN12@NcValidate: -; 268 : Delta -= XedDecodedInstGetLength(&T->XedInstruction); +; 267 : Delta -= XedDecodedInstGetLength(&T->XedInstruction); 00075 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 00079 48 83 c0 30 add rax, 48 ; 00000030H @@ -11632,18 +11616,18 @@ $LN12@NcValidate: 0008f 89 85 08 01 00 00 mov DWORD PTR Delta$[rbp], eax -; 269 : T = T->Next; +; 268 : T = T->Next; 00095 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 00099 48 8b 00 mov rax, QWORD PTR [rax] 0009c 48 89 45 08 mov QWORD PTR T$[rbp], rax -; 270 : } +; 269 : } 000a0 eb b3 jmp SHORT $LN21@NcValidate $LN3@NcValidate: -; 271 : if (Delta != 0 || !T) +; 270 : if (Delta != 0 || !T) 000a2 83 bd 08 01 00 00 00 cmp DWORD PTR Delta$[rbp], 0 @@ -11652,14 +11636,14 @@ $LN3@NcValidate: 000b0 75 07 jne SHORT $LN13@NcValidate $LN14@NcValidate: -; 272 : return NULL; +; 271 : return NULL; 000b2 33 c0 xor eax, eax 000b4 e9 db 00 00 00 jmp $LN1@NcValidate $LN13@NcValidate: $LN4@NcValidate: -; 273 : while (T && (T->Flags & CODE_FLAG_IS_LABEL)) +; 272 : while (T && (T->Flags & CODE_FLAG_IS_LABEL)) 000b9 48 83 7d 08 00 cmp QWORD PTR T$[rbp], 0 000be 74 1b je SHORT $LN5@NcValidate @@ -11669,7 +11653,7 @@ $LN4@NcValidate: 000ca 85 c0 test eax, eax 000cc 74 0d je SHORT $LN5@NcValidate -; 274 : T = T->Next; +; 273 : T = T->Next; 000ce 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 000d2 48 8b 00 mov rax, QWORD PTR [rax] @@ -11677,25 +11661,25 @@ $LN4@NcValidate: 000d9 eb de jmp SHORT $LN4@NcValidate $LN5@NcValidate: -; 275 : return T; +; 274 : return T; 000db 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 000df e9 b0 00 00 00 jmp $LN1@NcValidate -; 276 : } +; 275 : } 000e4 e9 a4 00 00 00 jmp $LN11@NcValidate $LN10@NcValidate: -; 277 : else if (Delta < 0) +; 276 : else if (Delta < 0) 000e9 83 bd 08 01 00 00 00 cmp DWORD PTR Delta$[rbp], 0 000f0 0f 8d 97 00 00 00 jge $LN15@NcValidate -; 278 : { -; 279 : T = Jmp; +; 277 : { +; 278 : T = Jmp; 000f6 48 8b 85 00 01 00 00 mov rax, QWORD PTR Jmp$[rbp] @@ -11703,13 +11687,13 @@ $LN10@NcValidate: $LN22@NcValidate: $LN6@NcValidate: -; 280 : while (T) +; 279 : while (T) 00101 48 83 7d 08 00 cmp QWORD PTR T$[rbp], 0 00106 74 49 je SHORT $LN7@NcValidate -; 281 : { -; 282 : if (T->Flags & CODE_FLAG_IS_LABEL) +; 280 : { +; 281 : if (T->Flags & CODE_FLAG_IS_LABEL) 00108 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 0010c 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -11717,12 +11701,12 @@ $LN6@NcValidate: 00112 85 c0 test eax, eax 00114 74 02 je SHORT $LN16@NcValidate -; 283 : continue; +; 282 : continue; 00116 eb e9 jmp SHORT $LN6@NcValidate $LN16@NcValidate: -; 284 : Delta += XedDecodedInstGetLength(&T->XedInstruction); +; 283 : Delta += XedDecodedInstGetLength(&T->XedInstruction); 00118 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 0011c 48 83 c0 30 add rax, 48 ; 00000030H @@ -11735,29 +11719,29 @@ $LN16@NcValidate: 00132 89 85 08 01 00 00 mov DWORD PTR Delta$[rbp], eax -; 285 : if (Delta >= 0) +; 284 : if (Delta >= 0) 00138 83 bd 08 01 00 00 00 cmp DWORD PTR Delta$[rbp], 0 0013f 7c 02 jl SHORT $LN17@NcValidate -; 286 : break; +; 285 : break; 00141 eb 0e jmp SHORT $LN7@NcValidate $LN17@NcValidate: -; 287 : T = T->Prev; +; 286 : T = T->Prev; 00143 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 00147 48 8b 40 08 mov rax, QWORD PTR [rax+8] 0014b 48 89 45 08 mov QWORD PTR T$[rbp], rax -; 288 : } +; 287 : } 0014f eb b0 jmp SHORT $LN22@NcValidate $LN7@NcValidate: -; 289 : if (Delta != 0 || !T) +; 288 : if (Delta != 0 || !T) 00151 83 bd 08 01 00 00 00 cmp DWORD PTR Delta$[rbp], 0 @@ -11766,14 +11750,14 @@ $LN7@NcValidate: 0015f 75 04 jne SHORT $LN18@NcValidate $LN19@NcValidate: -; 290 : return NULL; +; 289 : return NULL; 00161 33 c0 xor eax, eax 00163 eb 2f jmp SHORT $LN1@NcValidate $LN18@NcValidate: $LN8@NcValidate: -; 291 : while (T && (T->Flags & CODE_FLAG_IS_LABEL)) +; 290 : while (T && (T->Flags & CODE_FLAG_IS_LABEL)) 00165 48 83 7d 08 00 cmp QWORD PTR T$[rbp], 0 0016a 74 1b je SHORT $LN9@NcValidate @@ -11783,7 +11767,7 @@ $LN8@NcValidate: 00176 85 c0 test eax, eax 00178 74 0d je SHORT $LN9@NcValidate -; 292 : T = T->Next; +; 291 : T = T->Next; 0017a 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 0017e 48 8b 00 mov rax, QWORD PTR [rax] @@ -11791,21 +11775,21 @@ $LN8@NcValidate: 00185 eb de jmp SHORT $LN8@NcValidate $LN9@NcValidate: -; 293 : return T; +; 292 : return T; 00187 48 8b 45 08 mov rax, QWORD PTR T$[rbp] 0018b eb 07 jmp SHORT $LN1@NcValidate $LN15@NcValidate: $LN11@NcValidate: -; 294 : } -; 295 : return Jmp; +; 293 : } +; 294 : return Jmp; 0018d 48 8b 85 00 01 00 00 mov rax, QWORD PTR Jmp$[rbp] $LN1@NcValidate: -; 296 : } +; 295 : } 00194 48 8d a5 e8 00 00 00 lea rsp, QWORD PTR [rbp+232] @@ -11835,7 +11819,7 @@ __$ArrayPad$ = 544 Block$ = 592 ?NcCreateLabels@@YAHPEAU_NATIVE_CODE_BLOCK@@@Z PROC ; NcCreateLabels, COMDAT -; 207 : { +; 206 : { $LN18: 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx @@ -11859,12 +11843,12 @@ $LN18: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 00042 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 208 : ULONG CurrentLabelId = 0; +; 207 : ULONG CurrentLabelId = 0; 00047 c7 45 04 00 00 00 00 mov DWORD PTR CurrentLabelId$[rbp], 0 -; 209 : for (PNATIVE_CODE_LINK T = Block->Start; T; T = T->Next) +; 208 : for (PNATIVE_CODE_LINK T = Block->Start; T; T = T->Next) 0004e 48 8b 85 50 02 00 00 mov rax, QWORD PTR Block$[rbp] @@ -11880,8 +11864,8 @@ $LN4@NcCreateLa: 0006e 0f 84 07 02 00 00 je $LN3@NcCreateLa -; 210 : { -; 211 : if (!(T->Flags & CODE_FLAG_IS_INST)) +; 209 : { +; 210 : if (!(T->Flags & CODE_FLAG_IS_INST)) 00074 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 00078 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -11889,13 +11873,13 @@ $LN4@NcCreateLa: 0007e 85 c0 test eax, eax 00080 75 02 jne SHORT $LN5@NcCreateLa -; 212 : continue; +; 211 : continue; 00082 eb da jmp SHORT $LN2@NcCreateLa $LN5@NcCreateLa: -; 213 : -; 214 : XED_CATEGORY_ENUM Category = XedDecodedInstGetCategory(&T->XedInstruction); +; 212 : +; 213 : XED_CATEGORY_ENUM Category = XedDecodedInstGetCategory(&T->XedInstruction); 00084 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 00088 48 83 c0 30 add rax, 48 ; 00000030H @@ -11903,20 +11887,20 @@ $LN5@NcCreateLa: 0008f e8 00 00 00 00 call xed_decoded_inst_get_category 00094 89 45 44 mov DWORD PTR Category$5[rbp], eax -; 215 : if (Category != XED_CATEGORY_COND_BR && Category != XED_CATEGORY_UNCOND_BR) +; 214 : if (Category != XED_CATEGORY_COND_BR && Category != XED_CATEGORY_UNCOND_BR) 00097 83 7d 44 1c cmp DWORD PTR Category$5[rbp], 28 0009b 74 08 je SHORT $LN6@NcCreateLa 0009d 83 7d 44 5b cmp DWORD PTR Category$5[rbp], 91 ; 0000005bH 000a1 74 02 je SHORT $LN6@NcCreateLa -; 216 : continue; +; 215 : continue; 000a3 eb b9 jmp SHORT $LN2@NcCreateLa $LN6@NcCreateLa: -; 217 : -; 218 : ULONG OperandCount = XedDecodedInstNumOperands(&T->XedInstruction); +; 216 : +; 217 : ULONG OperandCount = XedDecodedInstNumOperands(&T->XedInstruction); 000a5 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 000a9 48 83 c0 30 add rax, 48 ; 00000030H @@ -11924,18 +11908,18 @@ $LN6@NcCreateLa: 000b0 e8 00 00 00 00 call xed_decoded_inst_noperands 000b5 89 45 64 mov DWORD PTR OperandCount$6[rbp], eax -; 219 : if (OperandCount < 1) +; 218 : if (OperandCount < 1) 000b8 83 7d 64 01 cmp DWORD PTR OperandCount$6[rbp], 1 000bc 73 02 jae SHORT $LN7@NcCreateLa -; 220 : continue; +; 219 : continue; 000be eb 9e jmp SHORT $LN2@NcCreateLa $LN7@NcCreateLa: -; 221 : -; 222 : CONST XED_INST* Inst = XedDecodedInstInst(&T->XedInstruction); +; 220 : +; 221 : CONST XED_INST* Inst = XedDecodedInstInst(&T->XedInstruction); 000c0 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 000c4 48 83 c0 30 add rax, 48 ; 00000030H @@ -11944,19 +11928,19 @@ $LN7@NcCreateLa: 000d0 48 89 85 88 00 00 00 mov QWORD PTR Inst$7[rbp], rax -; 223 : if (!Inst) +; 222 : if (!Inst) 000d7 48 83 bd 88 00 00 00 00 cmp QWORD PTR Inst$7[rbp], 0 000df 75 05 jne SHORT $LN8@NcCreateLa -; 224 : continue; +; 223 : continue; 000e1 e9 78 ff ff ff jmp $LN2@NcCreateLa $LN8@NcCreateLa: -; 225 : -; 226 : CONST XED_OPERAND* Operand = XedInstOperand(Inst, 0); +; 224 : +; 225 : CONST XED_OPERAND* Operand = XedInstOperand(Inst, 0); 000e6 33 d2 xor edx, edx 000e8 48 8b 8d 88 00 @@ -11965,19 +11949,19 @@ $LN8@NcCreateLa: 000f4 48 89 85 a8 00 00 00 mov QWORD PTR Operand$8[rbp], rax -; 227 : if (!Operand) +; 226 : if (!Operand) 000fb 48 83 bd a8 00 00 00 00 cmp QWORD PTR Operand$8[rbp], 0 00103 75 05 jne SHORT $LN9@NcCreateLa -; 228 : continue; +; 227 : continue; 00105 e9 54 ff ff ff jmp $LN2@NcCreateLa $LN9@NcCreateLa: -; 229 : -; 230 : XED_OPERAND_TYPE_ENUM OperandType = XedOperandType(Operand); +; 228 : +; 229 : XED_OPERAND_TYPE_ENUM OperandType = XedOperandType(Operand); 0010a 48 8b 8d a8 00 00 00 mov rcx, QWORD PTR Operand$8[rbp] @@ -11985,7 +11969,7 @@ $LN9@NcCreateLa: 00116 89 85 c4 00 00 00 mov DWORD PTR OperandType$9[rbp], eax -; 231 : if (OperandType != XED_OPERAND_TYPE_IMM && OperandType != XED_OPERAND_TYPE_IMM_CONST) +; 230 : if (OperandType != XED_OPERAND_TYPE_IMM && OperandType != XED_OPERAND_TYPE_IMM_CONST) 0011c 83 bd c4 00 00 00 02 cmp DWORD PTR OperandType$9[rbp], 2 @@ -11994,13 +11978,13 @@ $LN9@NcCreateLa: 00 03 cmp DWORD PTR OperandType$9[rbp], 3 0012c 74 05 je SHORT $LN10@NcCreateLa -; 232 : continue; +; 231 : continue; 0012e e9 2b ff ff ff jmp $LN2@NcCreateLa $LN10@NcCreateLa: -; 233 : -; 234 : INT32 BranchDisplacement = XedDecodedInstGetBranchDisplacement(&T->XedInstruction); +; 232 : +; 233 : INT32 BranchDisplacement = XedDecodedInstGetBranchDisplacement(&T->XedInstruction); 00133 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 00137 48 83 c0 30 add rax, 48 ; 00000030H @@ -12009,7 +11993,7 @@ $LN10@NcCreateLa: 00143 89 85 e4 00 00 00 mov DWORD PTR BranchDisplacement$10[rbp], eax -; 235 : PNATIVE_CODE_LINK JmpPos = NcValidateJmp(T, BranchDisplacement); +; 234 : PNATIVE_CODE_LINK JmpPos = NcValidateJmp(T, BranchDisplacement); 00149 8b 95 e4 00 00 00 mov edx, DWORD PTR BranchDisplacement$10[rbp] @@ -12018,14 +12002,14 @@ $LN10@NcCreateLa: 00158 48 89 85 08 01 00 00 mov QWORD PTR JmpPos$11[rbp], rax -; 236 : if (!JmpPos) +; 235 : if (!JmpPos) 0015f 48 83 bd 08 01 00 00 00 cmp QWORD PTR JmpPos$11[rbp], 0 00167 75 25 jne SHORT $LN11@NcCreateLa -; 237 : { -; 238 : printf("Failed to validate jump. Type: %s, Displacement: %d\n", XedCategoryEnumToString(Category), BranchDisplacement); +; 236 : { +; 237 : printf("Failed to validate jump. Type: %s, Displacement: %d\n", XedCategoryEnumToString(Category), BranchDisplacement); 00169 8b 4d 44 mov ecx, DWORD PTR Category$5[rbp] 0016c e8 00 00 00 00 call xed_category_enum_t2str @@ -12036,15 +12020,15 @@ $LN10@NcCreateLa: 00 00 lea rcx, OFFSET FLAT:??_C@_0DF@KKBEBOEB@Failed?5to?5validate?5jump?4?5Type?3?5@ 00182 e8 00 00 00 00 call printf -; 239 : return FALSE; +; 238 : return FALSE; 00187 33 c0 xor eax, eax 00189 e9 f2 00 00 00 jmp $LN1@NcCreateLa $LN11@NcCreateLa: -; 240 : } -; 241 : -; 242 : if (JmpPos->Prev && (JmpPos->Prev->Flags & CODE_FLAG_IS_LABEL)) +; 239 : } +; 240 : +; 241 : if (JmpPos->Prev && (JmpPos->Prev->Flags & CODE_FLAG_IS_LABEL)) 0018e 48 8b 85 08 01 00 00 mov rax, QWORD PTR JmpPos$11[rbp] @@ -12058,8 +12042,8 @@ $LN11@NcCreateLa: 001ad 85 c0 test eax, eax 001af 74 1a je SHORT $LN12@NcCreateLa -; 243 : { -; 244 : T->Label = JmpPos->Prev->Label; +; 242 : { +; 243 : T->Label = JmpPos->Prev->Label; 001b1 48 8b 85 08 01 00 00 mov rax, QWORD PTR JmpPos$11[rbp] @@ -12068,14 +12052,14 @@ $LN11@NcCreateLa: 001c0 8b 40 1c mov eax, DWORD PTR [rax+28] 001c3 89 41 1c mov DWORD PTR [rcx+28], eax -; 245 : } +; 244 : } 001c6 e9 9a 00 00 00 jmp $LN13@NcCreateLa $LN12@NcCreateLa: -; 246 : else -; 247 : { -; 248 : NcInsertLinkBefore(JmpPos, new NATIVE_CODE_LINK(CurrentLabelId, Block)); +; 245 : else +; 246 : { +; 247 : NcInsertLinkBefore(JmpPos, new NATIVE_CODE_LINK(CurrentLabelId, Block)); 001cb b9 f0 00 00 00 mov ecx, 240 ; 000000f0H 001d0 e8 00 00 00 00 call ??2@YAPEAX_K@Z ; operator new @@ -12108,7 +12092,7 @@ $LN16@NcCreateLa: 00 00 mov rcx, QWORD PTR JmpPos$11[rbp] 0022c e8 00 00 00 00 call ?NcInsertLinkBefore@@YAXPEAU_NATIVE_CODE_LINK@@0@Z ; NcInsertLinkBefore -; 249 : Block->LabelIds.push_back(CurrentLabelId); +; 248 : Block->LabelIds.push_back(CurrentLabelId); 00231 48 8b 85 50 02 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12120,21 +12104,21 @@ $LN16@NcCreateLa: 00 00 mov rcx, QWORD PTR tv163[rbp] 0024e e8 00 00 00 00 call ?push_back@?$vector@KV?$allocator@K@std@@@std@@QEAAXAEBK@Z ; std::vector >::push_back -; 250 : T->Label = CurrentLabelId; +; 249 : T->Label = CurrentLabelId; 00253 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 00257 8b 4d 04 mov ecx, DWORD PTR CurrentLabelId$[rbp] 0025a 89 48 1c mov DWORD PTR [rax+28], ecx -; 251 : ++CurrentLabelId; +; 250 : ++CurrentLabelId; 0025d 8b 45 04 mov eax, DWORD PTR CurrentLabelId$[rbp] 00260 ff c0 inc eax 00262 89 45 04 mov DWORD PTR CurrentLabelId$[rbp], eax $LN13@NcCreateLa: -; 252 : } -; 253 : T->Flags |= CODE_FLAG_IS_REL_JMP; +; 251 : } +; 252 : T->Flags |= CODE_FLAG_IS_REL_JMP; 00265 48 8b 45 28 mov rax, QWORD PTR T$4[rbp] 00269 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -12142,17 +12126,17 @@ $LN13@NcCreateLa: 0026f 48 8b 4d 28 mov rcx, QWORD PTR T$4[rbp] 00273 89 41 18 mov DWORD PTR [rcx+24], eax -; 254 : } +; 253 : } 00276 e9 e3 fd ff ff jmp $LN2@NcCreateLa $LN3@NcCreateLa: -; 255 : return TRUE; +; 254 : return TRUE; 0027b b8 01 00 00 00 mov eax, 1 $LN1@NcCreateLa: -; 256 : } +; 255 : } 00280 48 8b f8 mov rdi, rax 00283 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] @@ -12250,7 +12234,7 @@ Block$ = 264 FixLabels$ = 272 ?NcInsertBlockBefore@@YAHPEAU_NATIVE_CODE_LINK@@PEAU_NATIVE_CODE_BLOCK@@H@Z PROC ; NcInsertBlockBefore, COMDAT -; 187 : { +; 186 : { $LN10: 00000 44 89 44 24 18 mov DWORD PTR [rsp+24], r8d @@ -12271,7 +12255,7 @@ $LN10: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 188 : if (!Link || !Link->Block || !Block || !Block->Start || !Block->End) +; 187 : if (!Link || !Link->Block || !Block || !Block->Start || !Block->End) 00040 48 83 bd 00 01 00 00 00 cmp QWORD PTR Link$[rbp], 0 @@ -12293,14 +12277,14 @@ $LN10: 0007b 75 07 jne SHORT $LN5@NcInsertBl $LN6@NcInsertBl: -; 189 : return FALSE; +; 188 : return FALSE; 0007d 33 c0 xor eax, eax 0007f e9 0e 01 00 00 jmp $LN1@NcInsertBl $LN5@NcInsertBl: -; 190 : -; 191 : if (FixLabels && Block->LabelIds.size() && Link->Block->LabelIds.size()) +; 189 : +; 190 : if (FixLabels && Block->LabelIds.size() && Link->Block->LabelIds.size()) 00084 83 bd 10 01 00 00 00 cmp DWORD PTR FixLabels$[rbp], 0 @@ -12321,7 +12305,7 @@ $LN5@NcInsertBl: 000bc 48 85 c0 test rax, rax 000bf 74 17 je SHORT $LN7@NcInsertBl -; 192 : NcFixLabelsForBlocks(Link->Block, Block); +; 191 : NcFixLabelsForBlocks(Link->Block, Block); 000c1 48 8b 95 08 01 00 00 mov rdx, QWORD PTR Block$[rbp] @@ -12331,15 +12315,15 @@ $LN5@NcInsertBl: 000d3 e8 00 00 00 00 call ?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z ; NcFixLabelsForBlocks $LN7@NcInsertBl: -; 193 : -; 194 : if (Link->Prev) +; 192 : +; 193 : if (Link->Prev) 000d8 48 8b 85 00 01 00 00 mov rax, QWORD PTR Link$[rbp] 000df 48 83 78 08 00 cmp QWORD PTR [rax+8], 0 000e4 74 18 je SHORT $LN8@NcInsertBl -; 195 : Link->Prev->Next = Block->Start; +; 194 : Link->Prev->Next = Block->Start; 000e6 48 8b 85 00 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -12350,7 +12334,7 @@ $LN7@NcInsertBl: 000fb 48 89 08 mov QWORD PTR [rax], rcx $LN8@NcInsertBl: -; 196 : Block->Start->Prev = Link->Prev; +; 195 : Block->Start->Prev = Link->Prev; 000fe 48 8b 85 08 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12360,7 +12344,7 @@ $LN8@NcInsertBl: 0010f 48 8b 49 08 mov rcx, QWORD PTR [rcx+8] 00113 48 89 48 08 mov QWORD PTR [rax+8], rcx -; 197 : Block->End->Next = Link; +; 196 : Block->End->Next = Link; 00117 48 8b 85 08 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12369,7 +12353,7 @@ $LN8@NcInsertBl: 00 00 mov rcx, QWORD PTR Link$[rbp] 00129 48 89 08 mov QWORD PTR [rax], rcx -; 198 : Link->Prev = Block->End; +; 197 : Link->Prev = Block->End; 0012c 48 8b 85 00 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -12378,8 +12362,8 @@ $LN8@NcInsertBl: 0013a 48 8b 49 08 mov rcx, QWORD PTR [rcx+8] 0013e 48 89 48 08 mov QWORD PTR [rax+8], rcx -; 199 : -; 200 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) +; 198 : +; 199 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) 00142 48 8b 85 08 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12400,7 +12384,7 @@ $LN4@NcInsertBl: 00172 48 39 45 08 cmp QWORD PTR T$1[rbp], rax 00176 74 15 je SHORT $LN3@NcInsertBl -; 201 : T->Block = Link->Block; +; 200 : T->Block = Link->Block; 00178 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] 0017c 48 8b 8d 00 01 @@ -12410,13 +12394,13 @@ $LN4@NcInsertBl: 0018b eb c5 jmp SHORT $LN2@NcInsertBl $LN3@NcInsertBl: -; 202 : -; 203 : return TRUE; +; 201 : +; 202 : return TRUE; 0018d b8 01 00 00 00 mov eax, 1 $LN1@NcInsertBl: -; 204 : } +; 203 : } 00192 48 8d a5 e8 00 00 00 lea rsp, QWORD PTR [rbp+232] @@ -12435,7 +12419,7 @@ Block$ = 264 FixLabels$ = 272 ?NcInsertBlockAfter@@YAHPEAU_NATIVE_CODE_LINK@@PEAU_NATIVE_CODE_BLOCK@@H@Z PROC ; NcInsertBlockAfter, COMDAT -; 167 : { +; 166 : { $LN10: 00000 44 89 44 24 18 mov DWORD PTR [rsp+24], r8d @@ -12456,7 +12440,7 @@ $LN10: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 0003b e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 168 : if (!Link || !Link->Block || !Block || !Block->Start || !Block->End || Link->Block == Block) +; 167 : if (!Link || !Link->Block || !Block || !Block->Start || !Block->End || Link->Block == Block) 00040 48 83 bd 00 01 00 00 00 cmp QWORD PTR Link$[rbp], 0 @@ -12484,14 +12468,14 @@ $LN10: 0008f 75 07 jne SHORT $LN5@NcInsertBl $LN6@NcInsertBl: -; 169 : return FALSE; +; 168 : return FALSE; 00091 33 c0 xor eax, eax 00093 e9 0b 01 00 00 jmp $LN1@NcInsertBl $LN5@NcInsertBl: -; 170 : -; 171 : if (FixLabels && Block->LabelIds.size() && Link->Block->LabelIds.size()) +; 169 : +; 170 : if (FixLabels && Block->LabelIds.size() && Link->Block->LabelIds.size()) 00098 83 bd 10 01 00 00 00 cmp DWORD PTR FixLabels$[rbp], 0 @@ -12512,7 +12496,7 @@ $LN5@NcInsertBl: 000d0 48 85 c0 test rax, rax 000d3 74 17 je SHORT $LN7@NcInsertBl -; 172 : NcFixLabelsForBlocks(Link->Block, Block); +; 171 : NcFixLabelsForBlocks(Link->Block, Block); 000d5 48 8b 95 08 01 00 00 mov rdx, QWORD PTR Block$[rbp] @@ -12522,15 +12506,15 @@ $LN5@NcInsertBl: 000e7 e8 00 00 00 00 call ?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z ; NcFixLabelsForBlocks $LN7@NcInsertBl: -; 173 : -; 174 : if (Link->Next) +; 172 : +; 173 : if (Link->Next) 000ec 48 8b 85 00 01 00 00 mov rax, QWORD PTR Link$[rbp] 000f3 48 83 38 00 cmp QWORD PTR [rax], 0 000f7 74 19 je SHORT $LN8@NcInsertBl -; 175 : Link->Next->Prev = Block->End; +; 174 : Link->Next->Prev = Block->End; 000f9 48 8b 85 00 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -12541,7 +12525,7 @@ $LN7@NcInsertBl: 0010e 48 89 48 08 mov QWORD PTR [rax+8], rcx $LN8@NcInsertBl: -; 176 : Block->End->Next = Link->Next; +; 175 : Block->End->Next = Link->Next; 00112 48 8b 85 08 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12551,7 +12535,7 @@ $LN8@NcInsertBl: 00124 48 8b 09 mov rcx, QWORD PTR [rcx] 00127 48 89 08 mov QWORD PTR [rax], rcx -; 177 : Block->Start->Prev = Link; +; 176 : Block->Start->Prev = Link; 0012a 48 8b 85 08 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12560,7 +12544,7 @@ $LN8@NcInsertBl: 00 00 mov rcx, QWORD PTR Link$[rbp] 0013b 48 89 48 08 mov QWORD PTR [rax+8], rcx -; 178 : Link->Next = Block->Start; +; 177 : Link->Next = Block->Start; 0013f 48 8b 85 00 01 00 00 mov rax, QWORD PTR Link$[rbp] @@ -12569,8 +12553,8 @@ $LN8@NcInsertBl: 0014d 48 8b 09 mov rcx, QWORD PTR [rcx] 00150 48 89 08 mov QWORD PTR [rax], rcx -; 179 : -; 180 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) +; 178 : +; 179 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) 00153 48 8b 85 08 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -12591,7 +12575,7 @@ $LN4@NcInsertBl: 00183 48 39 45 08 cmp QWORD PTR T$1[rbp], rax 00187 74 15 je SHORT $LN3@NcInsertBl -; 181 : T->Block = Link->Block; +; 180 : T->Block = Link->Block; 00189 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] 0018d 48 8b 8d 00 01 @@ -12601,13 +12585,13 @@ $LN4@NcInsertBl: 0019c eb c5 jmp SHORT $LN2@NcInsertBl $LN3@NcInsertBl: -; 182 : -; 183 : return TRUE; +; 181 : +; 182 : return TRUE; 0019e b8 01 00 00 00 mov eax, 1 $LN1@NcInsertBl: -; 184 : } +; 183 : } 001a3 48 8d a5 e8 00 00 00 lea rsp, QWORD PTR [rbp+232] @@ -12620,315 +12604,291 @@ _TEXT ENDS ; File C:\$Fanta\code-virtualizer\CodeVirtualizer\NativeCode.cpp ; COMDAT ?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z _TEXT SEGMENT -T$4 = 8 -Lid$5 = 36 -$T6 = 260 -$T7 = 296 -$T8 = 344 -$T9 = 376 -$T10 = 424 -$T11 = 456 -$T12 = 504 -$T13 = 548 -tv179 = 568 -tv89 = 568 -tv182 = 576 -tv138 = 584 -tv133 = 592 -tv184 = 600 -tv92 = 608 +T$1 = 8 +$T2 = 228 +$T3 = 264 +$T4 = 312 +$T5 = 344 +$T6 = 392 +$T7 = 424 +$T8 = 472 +$T9 = 516 +tv178 = 532 +tv176 = 536 +tv89 = 536 +tv181 = 544 +tv138 = 552 +tv133 = 560 +tv183 = 568 +tv92 = 576 +tv198 = 584 +tv188 = 592 +tv161 = 600 +tv153 = 608 tv199 = 616 -tv189 = 624 -tv161 = 632 -tv153 = 640 -tv200 = 648 -tv194 = 656 -tv159 = 664 -tv165 = 672 -__$ArrayPad$ = 680 -Block1$ = 720 -Block2$ = 728 +tv193 = 624 +tv159 = 632 +tv165 = 640 +Block1$ = 688 +Block2$ = 696 ?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z PROC ; NcFixLabelsForBlocks, COMDAT -; 154 : { +; 155 : { $LN17: 00000 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx 00005 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 0000a 55 push rbp 0000b 57 push rdi - 0000c 48 81 ec d8 02 - 00 00 sub rsp, 728 ; 000002d8H + 0000c 48 81 ec b8 02 + 00 00 sub rsp, 696 ; 000002b8H 00013 48 8d 6c 24 20 lea rbp, QWORD PTR [rsp+32] 00018 48 8b fc mov rdi, rsp - 0001b b9 b6 00 00 00 mov ecx, 182 ; 000000b6H + 0001b b9 ae 00 00 00 mov ecx, 174 ; 000000aeH 00020 b8 cc cc cc cc mov eax, -858993460 ; ccccccccH 00025 f3 ab rep stosd - 00027 48 8b 8c 24 f8 - 02 00 00 mov rcx, QWORD PTR [rsp+760] - 0002f 48 8b 05 00 00 - 00 00 mov rax, QWORD PTR __security_cookie - 00036 48 33 c5 xor rax, rbp - 00039 48 89 85 a8 02 - 00 00 mov QWORD PTR __$ArrayPad$[rbp], rax - 00040 c7 85 24 02 00 - 00 00 00 00 00 mov DWORD PTR $T13[rbp], 0 - 0004a 48 8d 0d 00 00 + 00027 48 8b 8c 24 d8 + 02 00 00 mov rcx, QWORD PTR [rsp+728] + 0002f c7 85 04 02 00 + 00 00 00 00 00 mov DWORD PTR $T9[rbp], 0 + 00039 48 8d 0d 00 00 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp - 00051 e8 00 00 00 00 call __CheckForDebuggerJustMyCode + 00040 e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 155 : for (PNATIVE_CODE_LINK T = Block2->Start; T && T != Block2->End->Next; T = T->Next) +; 156 : for (PNATIVE_CODE_LINK T = Block2->Start; T && T != Block2->End->Next; T = T->Next) - 00056 48 8b 85 d8 02 + 00045 48 8b 85 b8 02 00 00 mov rax, QWORD PTR Block2$[rbp] - 0005d 48 8b 00 mov rax, QWORD PTR [rax] - 00060 48 89 45 08 mov QWORD PTR T$4[rbp], rax - 00064 eb 0b jmp SHORT $LN4@NcFixLabel + 0004c 48 8b 00 mov rax, QWORD PTR [rax] + 0004f 48 89 45 08 mov QWORD PTR T$1[rbp], rax + 00053 eb 0b jmp SHORT $LN4@NcFixLabel $LN2@NcFixLabel: - 00066 48 8b 45 08 mov rax, QWORD PTR T$4[rbp] - 0006a 48 8b 00 mov rax, QWORD PTR [rax] - 0006d 48 89 45 08 mov QWORD PTR T$4[rbp], rax + 00055 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] + 00059 48 8b 00 mov rax, QWORD PTR [rax] + 0005c 48 89 45 08 mov QWORD PTR T$1[rbp], rax $LN4@NcFixLabel: - 00071 48 83 7d 08 00 cmp QWORD PTR T$4[rbp], 0 - 00076 0f 84 3e 02 00 + 00060 48 83 7d 08 00 cmp QWORD PTR T$1[rbp], 0 + 00065 0f 84 2e 02 00 00 je $LN3@NcFixLabel - 0007c 48 8b 85 d8 02 + 0006b 48 8b 85 b8 02 00 00 mov rax, QWORD PTR Block2$[rbp] - 00083 48 8b 40 08 mov rax, QWORD PTR [rax+8] - 00087 48 8b 00 mov rax, QWORD PTR [rax] - 0008a 48 39 45 08 cmp QWORD PTR T$4[rbp], rax - 0008e 0f 84 26 02 00 + 00072 48 8b 40 08 mov rax, QWORD PTR [rax+8] + 00076 48 8b 00 mov rax, QWORD PTR [rax] + 00079 48 39 45 08 cmp QWORD PTR T$1[rbp], rax + 0007d 0f 84 16 02 00 00 je $LN3@NcFixLabel -; 156 : { -; 157 : if ((T->Flags & CODE_FLAG_IS_LABEL) && StdFind(Block1->LabelIds.begin(), Block1->LabelIds.end(), T->Label) != Block1->LabelIds.end()) +; 157 : { +; 158 : if ((T->Flags & CODE_FLAG_IS_LABEL) && StdFind(Block1->LabelIds.begin(), Block1->LabelIds.end(), T->Label) != Block1->LabelIds.end()) - 00094 48 8b 45 08 mov rax, QWORD PTR T$4[rbp] - 00098 8b 40 18 mov eax, DWORD PTR [rax+24] - 0009b 83 e0 01 and eax, 1 - 0009e 85 c0 test eax, eax - 000a0 0f 84 64 01 00 + 00083 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] + 00087 8b 40 18 mov eax, DWORD PTR [rax+24] + 0008a 83 e0 01 and eax, 1 + 0008d 85 c0 test eax, eax + 0008f 0f 84 64 01 00 00 je $LN7@NcFixLabel - 000a6 48 8d 85 28 01 - 00 00 lea rax, QWORD PTR $T7[rbp] - 000ad 48 89 85 58 01 - 00 00 mov QWORD PTR $T8[rbp], rax - 000b4 48 8b 85 d0 02 + 00095 48 8d 85 08 01 + 00 00 lea rax, QWORD PTR $T3[rbp] + 0009c 48 89 85 38 01 + 00 00 mov QWORD PTR $T4[rbp], rax + 000a3 48 8b 85 b0 02 00 00 mov rax, QWORD PTR Block1$[rbp] - 000bb 48 83 c0 10 add rax, 16 - 000bf 48 89 85 38 02 + 000aa 48 83 c0 10 add rax, 16 + 000ae 48 89 85 18 02 00 00 mov QWORD PTR tv89[rbp], rax - 000c6 48 8b 95 58 01 - 00 00 mov rdx, QWORD PTR $T8[rbp] - 000cd 48 8b 8d 38 02 + 000b5 48 8b 95 38 01 + 00 00 mov rdx, QWORD PTR $T4[rbp] + 000bc 48 8b 8d 18 02 00 00 mov rcx, QWORD PTR tv89[rbp] - 000d4 e8 00 00 00 00 call ?end@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::end - 000d9 48 89 85 40 02 - 00 00 mov QWORD PTR tv182[rbp], rax - 000e0 48 8b 85 40 02 - 00 00 mov rax, QWORD PTR tv182[rbp] - 000e7 48 89 85 48 02 + 000c3 e8 00 00 00 00 call ?end@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::end + 000c8 48 89 85 20 02 + 00 00 mov QWORD PTR tv181[rbp], rax + 000cf 48 8b 85 20 02 + 00 00 mov rax, QWORD PTR tv181[rbp] + 000d6 48 89 85 28 02 00 00 mov QWORD PTR tv138[rbp], rax - 000ee 48 8d 85 78 01 - 00 00 lea rax, QWORD PTR $T9[rbp] - 000f5 48 89 85 a8 01 - 00 00 mov QWORD PTR $T10[rbp], rax - 000fc 48 8b 85 d0 02 + 000dd 48 8d 85 58 01 + 00 00 lea rax, QWORD PTR $T5[rbp] + 000e4 48 89 85 88 01 + 00 00 mov QWORD PTR $T6[rbp], rax + 000eb 48 8b 85 b0 02 00 00 mov rax, QWORD PTR Block1$[rbp] - 00103 48 83 c0 10 add rax, 16 - 00107 48 89 85 50 02 + 000f2 48 83 c0 10 add rax, 16 + 000f6 48 89 85 30 02 00 00 mov QWORD PTR tv133[rbp], rax - 0010e 48 8b 95 a8 01 - 00 00 mov rdx, QWORD PTR $T10[rbp] - 00115 48 8b 8d 50 02 + 000fd 48 8b 95 88 01 + 00 00 mov rdx, QWORD PTR $T6[rbp] + 00104 48 8b 8d 30 02 00 00 mov rcx, QWORD PTR tv133[rbp] - 0011c e8 00 00 00 00 call ?begin@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::begin - 00121 48 89 85 58 02 - 00 00 mov QWORD PTR tv184[rbp], rax - 00128 48 8b 85 58 02 - 00 00 mov rax, QWORD PTR tv184[rbp] - 0012f 48 89 85 60 02 + 0010b e8 00 00 00 00 call ?begin@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::begin + 00110 48 89 85 38 02 + 00 00 mov QWORD PTR tv183[rbp], rax + 00117 48 8b 85 38 02 + 00 00 mov rax, QWORD PTR tv183[rbp] + 0011e 48 89 85 40 02 00 00 mov QWORD PTR tv92[rbp], rax - 00136 48 8b 45 08 mov rax, QWORD PTR T$4[rbp] - 0013a 48 83 c0 1c add rax, 28 - 0013e 4c 8b c8 mov r9, rax - 00141 4c 8b 85 48 02 + 00125 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] + 00129 48 83 c0 1c add rax, 28 + 0012d 4c 8b c8 mov r9, rax + 00130 4c 8b 85 28 02 00 00 mov r8, QWORD PTR tv138[rbp] - 00148 48 8b 95 60 02 + 00137 48 8b 95 40 02 00 00 mov rdx, QWORD PTR tv92[rbp] - 0014f 48 8d 8d c8 01 - 00 00 lea rcx, QWORD PTR $T11[rbp] - 00156 e8 00 00 00 00 call ??$find@V?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@K@std@@YA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@0@V10@V10@AEBK@Z ; std::find > >,unsigned long> - 0015b 48 89 85 68 02 - 00 00 mov QWORD PTR tv199[rbp], rax - 00162 48 8b 85 68 02 - 00 00 mov rax, QWORD PTR tv199[rbp] - 00169 48 89 85 70 02 - 00 00 mov QWORD PTR tv189[rbp], rax - 00170 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] - 00176 83 c8 01 or eax, 1 - 00179 89 85 24 02 00 - 00 mov DWORD PTR $T13[rbp], eax - 0017f 48 8b 85 70 02 - 00 00 mov rax, QWORD PTR tv189[rbp] - 00186 48 89 85 78 02 + 0013e 48 8d 8d a8 01 + 00 00 lea rcx, QWORD PTR $T7[rbp] + 00145 e8 00 00 00 00 call ??$find@V?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@K@std@@YA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@0@V10@V10@AEBK@Z ; std::find > >,unsigned long> + 0014a 48 89 85 48 02 + 00 00 mov QWORD PTR tv198[rbp], rax + 00151 48 8b 85 48 02 + 00 00 mov rax, QWORD PTR tv198[rbp] + 00158 48 89 85 50 02 + 00 00 mov QWORD PTR tv188[rbp], rax + 0015f 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] + 00165 83 c8 01 or eax, 1 + 00168 89 85 04 02 00 + 00 mov DWORD PTR $T9[rbp], eax + 0016e 48 8b 85 50 02 + 00 00 mov rax, QWORD PTR tv188[rbp] + 00175 48 89 85 58 02 00 00 mov QWORD PTR tv161[rbp], rax - 0018d 48 8b 85 d0 02 + 0017c 48 8b 85 b0 02 00 00 mov rax, QWORD PTR Block1$[rbp] - 00194 48 83 c0 10 add rax, 16 - 00198 48 89 85 80 02 + 00183 48 83 c0 10 add rax, 16 + 00187 48 89 85 60 02 00 00 mov QWORD PTR tv153[rbp], rax - 0019f 48 8d 95 f8 01 - 00 00 lea rdx, QWORD PTR $T12[rbp] - 001a6 48 8b 8d 80 02 + 0018e 48 8d 95 d8 01 + 00 00 lea rdx, QWORD PTR $T8[rbp] + 00195 48 8b 8d 60 02 00 00 mov rcx, QWORD PTR tv153[rbp] - 001ad e8 00 00 00 00 call ?end@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::end - 001b2 48 89 85 88 02 - 00 00 mov QWORD PTR tv200[rbp], rax - 001b9 48 8b 85 88 02 - 00 00 mov rax, QWORD PTR tv200[rbp] - 001c0 48 89 85 90 02 - 00 00 mov QWORD PTR tv194[rbp], rax - 001c7 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] - 001cd 83 c8 02 or eax, 2 - 001d0 89 85 24 02 00 - 00 mov DWORD PTR $T13[rbp], eax - 001d6 48 8b 85 90 02 - 00 00 mov rax, QWORD PTR tv194[rbp] - 001dd 48 89 85 98 02 + 0019c e8 00 00 00 00 call ?end@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::end + 001a1 48 89 85 68 02 + 00 00 mov QWORD PTR tv199[rbp], rax + 001a8 48 8b 85 68 02 + 00 00 mov rax, QWORD PTR tv199[rbp] + 001af 48 89 85 70 02 + 00 00 mov QWORD PTR tv193[rbp], rax + 001b6 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] + 001bc 83 c8 02 or eax, 2 + 001bf 89 85 04 02 00 + 00 mov DWORD PTR $T9[rbp], eax + 001c5 48 8b 85 70 02 + 00 00 mov rax, QWORD PTR tv193[rbp] + 001cc 48 89 85 78 02 00 00 mov QWORD PTR tv159[rbp], rax - 001e4 48 8b 95 98 02 + 001d3 48 8b 95 78 02 00 00 mov rdx, QWORD PTR tv159[rbp] - 001eb 48 8b 8d 78 02 + 001da 48 8b 8d 58 02 00 00 mov rcx, QWORD PTR tv161[rbp] - 001f2 e8 00 00 00 00 call ??9?$_Vector_const_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEBA_NAEBV01@@Z ; std::_Vector_const_iterator > >::operator!= - 001f7 0f b6 c0 movzx eax, al - 001fa 85 c0 test eax, eax - 001fc 74 0c je SHORT $LN7@NcFixLabel - 001fe c7 85 a0 02 00 + 001e1 e8 00 00 00 00 call ??9?$_Vector_const_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEBA_NAEBV01@@Z ; std::_Vector_const_iterator > >::operator!= + 001e6 0f b6 c0 movzx eax, al + 001e9 85 c0 test eax, eax + 001eb 74 0c je SHORT $LN7@NcFixLabel + 001ed c7 85 80 02 00 00 01 00 00 00 mov DWORD PTR tv165[rbp], 1 - 00208 eb 0a jmp SHORT $LN8@NcFixLabel + 001f7 eb 0a jmp SHORT $LN8@NcFixLabel $LN7@NcFixLabel: - 0020a c7 85 a0 02 00 + 001f9 c7 85 80 02 00 00 00 00 00 00 mov DWORD PTR tv165[rbp], 0 $LN8@NcFixLabel: - 00214 0f b6 85 a0 02 + 00203 0f b6 85 80 02 00 00 movzx eax, BYTE PTR tv165[rbp] - 0021b 88 85 04 01 00 - 00 mov BYTE PTR $T6[rbp], al - 00221 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] - 00227 83 e0 02 and eax, 2 - 0022a 85 c0 test eax, eax - 0022c 74 14 je SHORT $LN15@NcFixLabel - 0022e 83 a5 24 02 00 - 00 fd and DWORD PTR $T13[rbp], -3 - 00235 48 8d 8d f8 01 - 00 00 lea rcx, QWORD PTR $T12[rbp] - 0023c e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ - 00241 90 npad 1 + 0020a 88 85 e4 00 00 + 00 mov BYTE PTR $T2[rbp], al + 00210 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] + 00216 83 e0 02 and eax, 2 + 00219 85 c0 test eax, eax + 0021b 74 14 je SHORT $LN15@NcFixLabel + 0021d 83 a5 04 02 00 + 00 fd and DWORD PTR $T9[rbp], -3 + 00224 48 8d 8d d8 01 + 00 00 lea rcx, QWORD PTR $T8[rbp] + 0022b e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ + 00230 90 npad 1 $LN15@NcFixLabel: - 00242 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] - 00248 83 e0 01 and eax, 1 - 0024b 85 c0 test eax, eax - 0024d 74 13 je SHORT $LN16@NcFixLabel - 0024f 83 a5 24 02 00 - 00 fe and DWORD PTR $T13[rbp], -2 - 00256 48 8d 8d c8 01 - 00 00 lea rcx, QWORD PTR $T11[rbp] - 0025d e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ + 00231 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] + 00237 83 e0 01 and eax, 1 + 0023a 85 c0 test eax, eax + 0023c 74 13 je SHORT $LN16@NcFixLabel + 0023e 83 a5 04 02 00 + 00 fe and DWORD PTR $T9[rbp], -2 + 00245 48 8d 8d a8 01 + 00 00 lea rcx, QWORD PTR $T7[rbp] + 0024c e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ $LN16@NcFixLabel: - 00262 0f b6 85 04 01 - 00 00 movzx eax, BYTE PTR $T6[rbp] - 00269 85 c0 test eax, eax - 0026b 74 48 je SHORT $LN5@NcFixLabel + 00251 0f b6 85 e4 00 + 00 00 movzx eax, BYTE PTR $T2[rbp] + 00258 85 c0 test eax, eax + 0025a 74 38 je SHORT $LN5@NcFixLabel -; 158 : { -; 159 : ULONG Lid = NcGenUnusedLabelId(Block1); +; 159 : { +; 160 : NcChangeLabelId(Block2, T->Label, NcGenUnusedLabelId(Block1)); - 0026d 48 8b 8d d0 02 + 0025c 48 8b 8d b0 02 00 00 mov rcx, QWORD PTR Block1$[rbp] - 00274 e8 00 00 00 00 call ?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z ; NcGenUnusedLabelId - 00279 89 45 24 mov DWORD PTR Lid$5[rbp], eax - -; 160 : NcChangeLabelId(Block2, T->Label, Lid); - - 0027c 44 8b 45 24 mov r8d, DWORD PTR Lid$5[rbp] - 00280 48 8b 45 08 mov rax, QWORD PTR T$4[rbp] - 00284 8b 50 1c mov edx, DWORD PTR [rax+28] - 00287 48 8b 8d d8 02 + 00263 e8 00 00 00 00 call ?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z ; NcGenUnusedLabelId + 00268 89 85 14 02 00 + 00 mov DWORD PTR tv178[rbp], eax + 0026e 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] + 00272 8b 40 1c mov eax, DWORD PTR [rax+28] + 00275 89 85 18 02 00 + 00 mov DWORD PTR tv176[rbp], eax + 0027b 44 8b 85 14 02 + 00 00 mov r8d, DWORD PTR tv178[rbp] + 00282 8b 95 18 02 00 + 00 mov edx, DWORD PTR tv176[rbp] + 00288 48 8b 8d b8 02 00 00 mov rcx, QWORD PTR Block2$[rbp] - 0028e e8 00 00 00 00 call ?NcChangeLabelId@@YAXPEAU_NATIVE_CODE_BLOCK@@KK@Z ; NcChangeLabelId - -; 161 : Block1->LabelIds.push_back(Lid); - - 00293 48 8b 85 d0 02 - 00 00 mov rax, QWORD PTR Block1$[rbp] - 0029a 48 83 c0 10 add rax, 16 - 0029e 48 89 85 38 02 - 00 00 mov QWORD PTR tv179[rbp], rax - 002a5 48 8d 55 24 lea rdx, QWORD PTR Lid$5[rbp] - 002a9 48 8b 8d 38 02 - 00 00 mov rcx, QWORD PTR tv179[rbp] - 002b0 e8 00 00 00 00 call ?push_back@?$vector@KV?$allocator@K@std@@@std@@QEAAXAEBK@Z ; std::vector >::push_back + 0028f e8 00 00 00 00 call ?NcChangeLabelId@@YAXPEAU_NATIVE_CODE_BLOCK@@KK@Z ; NcChangeLabelId $LN5@NcFixLabel: -; 162 : } -; 163 : } +; 161 : } +; 162 : } - 002b5 e9 ac fd ff ff jmp $LN2@NcFixLabel + 00294 e9 bc fd ff ff jmp $LN2@NcFixLabel $LN3@NcFixLabel: -; 164 : } +; 163 : } - 002ba 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] - 002be 48 8d 15 00 00 - 00 00 lea rdx, OFFSET FLAT:?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z$rtcFrameData - 002c5 e8 00 00 00 00 call _RTC_CheckStackVars - 002ca 48 8b 8d a8 02 - 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] - 002d1 48 33 cd xor rcx, rbp - 002d4 e8 00 00 00 00 call __security_check_cookie - 002d9 48 8d a5 b8 02 - 00 00 lea rsp, QWORD PTR [rbp+696] - 002e0 5f pop rdi - 002e1 5d pop rbp - 002e2 c3 ret 0 + 00299 48 8d a5 98 02 + 00 00 lea rsp, QWORD PTR [rbp+664] + 002a0 5f pop rdi + 002a1 5d pop rbp + 002a2 c3 ret 0 ?NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z ENDP ; NcFixLabelsForBlocks _TEXT ENDS ; COMDAT text$x text$x SEGMENT -T$4 = 8 -Lid$5 = 36 -$T6 = 260 -$T7 = 296 -$T8 = 344 -$T9 = 376 -$T10 = 424 -$T11 = 456 -$T12 = 504 -$T13 = 548 -tv179 = 568 -tv89 = 568 -tv182 = 576 -tv138 = 584 -tv133 = 592 -tv184 = 600 -tv92 = 608 +T$1 = 8 +$T2 = 228 +$T3 = 264 +$T4 = 312 +$T5 = 344 +$T6 = 392 +$T7 = 424 +$T8 = 472 +$T9 = 516 +tv178 = 532 +tv176 = 536 +tv89 = 536 +tv181 = 544 +tv138 = 552 +tv133 = 560 +tv183 = 568 +tv92 = 576 +tv198 = 584 +tv188 = 592 +tv161 = 600 +tv153 = 608 tv199 = 616 -tv189 = 624 -tv161 = 632 -tv153 = 640 -tv200 = 648 -tv194 = 656 -tv159 = 664 -tv165 = 672 -__$ArrayPad$ = 680 -Block1$ = 720 -Block2$ = 728 +tv193 = 624 +tv159 = 632 +tv165 = 640 +Block1$ = 688 +Block2$ = 696 ?dtor$2@?0??NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z@4HA PROC ; `NcFixLabelsForBlocks'::`1'::dtor$2 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -12936,15 +12896,15 @@ Block2$ = 728 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] + 00014 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] 0001a 83 e0 01 and eax, 1 0001d 85 c0 test eax, eax 0001f 74 13 je SHORT $LN12@dtor$2 - 00021 83 a5 24 02 00 - 00 fe and DWORD PTR $T13[rbp], -2 - 00028 48 8d 8d c8 01 - 00 00 lea rcx, QWORD PTR $T11[rbp] + 00021 83 a5 04 02 00 + 00 fe and DWORD PTR $T9[rbp], -2 + 00028 48 8d 8d a8 01 + 00 00 lea rcx, QWORD PTR $T7[rbp] 0002f e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ $LN12@dtor$2: 00034 48 83 c4 28 add rsp, 40 ; 00000028H @@ -12955,34 +12915,33 @@ $LN12@dtor$2: text$x ENDS ; COMDAT text$x text$x SEGMENT -T$4 = 8 -Lid$5 = 36 -$T6 = 260 -$T7 = 296 -$T8 = 344 -$T9 = 376 -$T10 = 424 -$T11 = 456 -$T12 = 504 -$T13 = 548 -tv179 = 568 -tv89 = 568 -tv182 = 576 -tv138 = 584 -tv133 = 592 -tv184 = 600 -tv92 = 608 +T$1 = 8 +$T2 = 228 +$T3 = 264 +$T4 = 312 +$T5 = 344 +$T6 = 392 +$T7 = 424 +$T8 = 472 +$T9 = 516 +tv178 = 532 +tv176 = 536 +tv89 = 536 +tv181 = 544 +tv138 = 552 +tv133 = 560 +tv183 = 568 +tv92 = 576 +tv198 = 584 +tv188 = 592 +tv161 = 600 +tv153 = 608 tv199 = 616 -tv189 = 624 -tv161 = 632 -tv153 = 640 -tv200 = 648 -tv194 = 656 -tv159 = 664 -tv165 = 672 -__$ArrayPad$ = 680 -Block1$ = 720 -Block2$ = 728 +tv193 = 624 +tv159 = 632 +tv165 = 640 +Block1$ = 688 +Block2$ = 696 ?dtor$3@?0??NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z@4HA PROC ; `NcFixLabelsForBlocks'::`1'::dtor$3 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -12990,15 +12949,15 @@ Block2$ = 728 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] + 00014 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] 0001a 83 e0 02 and eax, 2 0001d 85 c0 test eax, eax 0001f 74 13 je SHORT $LN14@dtor$3 - 00021 83 a5 24 02 00 - 00 fd and DWORD PTR $T13[rbp], -3 - 00028 48 8d 8d f8 01 - 00 00 lea rcx, QWORD PTR $T12[rbp] + 00021 83 a5 04 02 00 + 00 fd and DWORD PTR $T9[rbp], -3 + 00028 48 8d 8d d8 01 + 00 00 lea rcx, QWORD PTR $T8[rbp] 0002f e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ $LN14@dtor$3: 00034 48 83 c4 28 add rsp, 40 ; 00000028H @@ -13010,34 +12969,33 @@ text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; COMDAT text$x text$x SEGMENT -T$4 = 8 -Lid$5 = 36 -$T6 = 260 -$T7 = 296 -$T8 = 344 -$T9 = 376 -$T10 = 424 -$T11 = 456 -$T12 = 504 -$T13 = 548 -tv179 = 568 -tv89 = 568 -tv182 = 576 -tv138 = 584 -tv133 = 592 -tv184 = 600 -tv92 = 608 +T$1 = 8 +$T2 = 228 +$T3 = 264 +$T4 = 312 +$T5 = 344 +$T6 = 392 +$T7 = 424 +$T8 = 472 +$T9 = 516 +tv178 = 532 +tv176 = 536 +tv89 = 536 +tv181 = 544 +tv138 = 552 +tv133 = 560 +tv183 = 568 +tv92 = 576 +tv198 = 584 +tv188 = 592 +tv161 = 600 +tv153 = 608 tv199 = 616 -tv189 = 624 -tv161 = 632 -tv153 = 640 -tv200 = 648 -tv194 = 656 -tv159 = 664 -tv165 = 672 -__$ArrayPad$ = 680 -Block1$ = 720 -Block2$ = 728 +tv193 = 624 +tv159 = 632 +tv165 = 640 +Block1$ = 688 +Block2$ = 696 ?dtor$2@?0??NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z@4HA PROC ; `NcFixLabelsForBlocks'::`1'::dtor$2 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -13045,15 +13003,15 @@ Block2$ = 728 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] + 00014 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] 0001a 83 e0 01 and eax, 1 0001d 85 c0 test eax, eax 0001f 74 13 je SHORT $LN12@dtor$2 - 00021 83 a5 24 02 00 - 00 fe and DWORD PTR $T13[rbp], -2 - 00028 48 8d 8d c8 01 - 00 00 lea rcx, QWORD PTR $T11[rbp] + 00021 83 a5 04 02 00 + 00 fe and DWORD PTR $T9[rbp], -2 + 00028 48 8d 8d a8 01 + 00 00 lea rcx, QWORD PTR $T7[rbp] 0002f e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ $LN12@dtor$2: 00034 48 83 c4 28 add rsp, 40 ; 00000028H @@ -13065,34 +13023,33 @@ text$x ENDS ; Function compile flags: /Odtp /RTCsu /ZI ; COMDAT text$x text$x SEGMENT -T$4 = 8 -Lid$5 = 36 -$T6 = 260 -$T7 = 296 -$T8 = 344 -$T9 = 376 -$T10 = 424 -$T11 = 456 -$T12 = 504 -$T13 = 548 -tv179 = 568 -tv89 = 568 -tv182 = 576 -tv138 = 584 -tv133 = 592 -tv184 = 600 -tv92 = 608 +T$1 = 8 +$T2 = 228 +$T3 = 264 +$T4 = 312 +$T5 = 344 +$T6 = 392 +$T7 = 424 +$T8 = 472 +$T9 = 516 +tv178 = 532 +tv176 = 536 +tv89 = 536 +tv181 = 544 +tv138 = 552 +tv133 = 560 +tv183 = 568 +tv92 = 576 +tv198 = 584 +tv188 = 592 +tv161 = 600 +tv153 = 608 tv199 = 616 -tv189 = 624 -tv161 = 632 -tv153 = 640 -tv200 = 648 -tv194 = 656 -tv159 = 664 -tv165 = 672 -__$ArrayPad$ = 680 -Block1$ = 720 -Block2$ = 728 +tv193 = 624 +tv159 = 632 +tv165 = 640 +Block1$ = 688 +Block2$ = 696 ?dtor$3@?0??NcFixLabelsForBlocks@@YAXPEAU_NATIVE_CODE_BLOCK@@0@Z@4HA PROC ; `NcFixLabelsForBlocks'::`1'::dtor$3 00000 48 89 4c 24 08 mov QWORD PTR [rsp+8], rcx 00005 48 89 54 24 10 mov QWORD PTR [rsp+16], rdx @@ -13100,15 +13057,15 @@ Block2$ = 728 0000b 57 push rdi 0000c 48 83 ec 28 sub rsp, 40 ; 00000028H 00010 48 8d 6a 20 lea rbp, QWORD PTR [rdx+32] - 00014 8b 85 24 02 00 - 00 mov eax, DWORD PTR $T13[rbp] + 00014 8b 85 04 02 00 + 00 mov eax, DWORD PTR $T9[rbp] 0001a 83 e0 02 and eax, 2 0001d 85 c0 test eax, eax 0001f 74 13 je SHORT $LN14@dtor$3 - 00021 83 a5 24 02 00 - 00 fd and DWORD PTR $T13[rbp], -3 - 00028 48 8d 8d f8 01 - 00 00 lea rcx, QWORD PTR $T12[rbp] + 00021 83 a5 04 02 00 + 00 fd and DWORD PTR $T9[rbp], -3 + 00028 48 8d 8d d8 01 + 00 00 lea rcx, QWORD PTR $T8[rbp] 0002f e8 00 00 00 00 call ??1?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@QEAA@XZ $LN14@dtor$3: 00034 48 83 c4 28 add rsp, 40 ; 00000028H @@ -13129,18 +13086,19 @@ $T7 = 344 $T8 = 392 $T9 = 424 $T10 = 472 +tv161 = 504 tv81 = 504 -tv159 = 512 +tv164 = 512 tv130 = 520 tv93 = 528 -tv161 = 536 +tv166 = 536 tv84 = 544 -tv166 = 552 -tv163 = 560 +tv171 = 552 +tv168 = 560 tv153 = 568 tv145 = 576 -tv167 = 584 -tv165 = 592 +tv172 = 584 +tv170 = 592 tv151 = 600 __$ArrayPad$ = 608 Block$ = 656 @@ -13194,9 +13152,9 @@ $LN2@NcGenUnuse: 00 00 mov rcx, QWORD PTR tv81[rbp] 0007e e8 00 00 00 00 call ?end@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::end 00083 48 89 85 00 02 - 00 00 mov QWORD PTR tv159[rbp], rax + 00 00 mov QWORD PTR tv164[rbp], rax 0008a 48 8b 85 00 02 - 00 00 mov rax, QWORD PTR tv159[rbp] + 00 00 mov rax, QWORD PTR tv164[rbp] 00091 48 89 85 08 02 00 00 mov QWORD PTR tv130[rbp], rax 00098 48 8d 85 58 01 @@ -13214,9 +13172,9 @@ $LN2@NcGenUnuse: 00 00 mov rcx, QWORD PTR tv93[rbp] 000c6 e8 00 00 00 00 call ?begin@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::begin 000cb 48 89 85 18 02 - 00 00 mov QWORD PTR tv161[rbp], rax + 00 00 mov QWORD PTR tv166[rbp], rax 000d2 48 8b 85 18 02 - 00 00 mov rax, QWORD PTR tv161[rbp] + 00 00 mov rax, QWORD PTR tv166[rbp] 000d9 48 89 85 20 02 00 00 mov QWORD PTR tv84[rbp], rax 000e0 4c 8d 4d 04 lea r9, QWORD PTR ReturnLabelId$[rbp] @@ -13228,13 +13186,13 @@ $LN2@NcGenUnuse: 00 00 lea rcx, QWORD PTR $T9[rbp] 000f9 e8 00 00 00 00 call ??$find@V?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@std@@K@std@@YA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@0@V10@V10@AEBK@Z ; std::find > >,unsigned long> 000fe 48 89 85 28 02 - 00 00 mov QWORD PTR tv166[rbp], rax + 00 00 mov QWORD PTR tv171[rbp], rax 00105 48 8b 85 28 02 - 00 00 mov rax, QWORD PTR tv166[rbp] + 00 00 mov rax, QWORD PTR tv171[rbp] 0010c 48 89 85 30 02 - 00 00 mov QWORD PTR tv163[rbp], rax + 00 00 mov QWORD PTR tv168[rbp], rax 00113 48 8b 85 30 02 - 00 00 mov rax, QWORD PTR tv163[rbp] + 00 00 mov rax, QWORD PTR tv168[rbp] 0011a 48 89 85 38 02 00 00 mov QWORD PTR tv153[rbp], rax 00121 48 8b 85 90 02 @@ -13248,13 +13206,13 @@ $LN2@NcGenUnuse: 00 00 mov rcx, QWORD PTR tv145[rbp] 00141 e8 00 00 00 00 call ?end@?$vector@KV?$allocator@K@std@@@std@@QEAA?AV?$_Vector_iterator@V?$_Vector_val@U?$_Simple_types@K@std@@@std@@@2@XZ ; std::vector >::end 00146 48 89 85 48 02 - 00 00 mov QWORD PTR tv167[rbp], rax + 00 00 mov QWORD PTR tv172[rbp], rax 0014d 48 8b 85 48 02 - 00 00 mov rax, QWORD PTR tv167[rbp] + 00 00 mov rax, QWORD PTR tv172[rbp] 00154 48 89 85 50 02 - 00 00 mov QWORD PTR tv165[rbp], rax + 00 00 mov QWORD PTR tv170[rbp], rax 0015b 48 8b 85 50 02 - 00 00 mov rax, QWORD PTR tv165[rbp] + 00 00 mov rax, QWORD PTR tv170[rbp] 00162 48 89 85 58 02 00 00 mov QWORD PTR tv151[rbp], rax 00169 48 8b 95 58 02 @@ -13284,27 +13242,39 @@ $LN2@NcGenUnuse: 001af e9 9c fe ff ff jmp $LN2@NcGenUnuse $LN3@NcGenUnuse: -; 141 : return ReturnLabelId; +; 141 : Block->LabelIds.push_back(ReturnLabelId); + + 001b4 48 8b 85 90 02 + 00 00 mov rax, QWORD PTR Block$[rbp] + 001bb 48 83 c0 10 add rax, 16 + 001bf 48 89 85 f8 01 + 00 00 mov QWORD PTR tv161[rbp], rax + 001c6 48 8d 55 04 lea rdx, QWORD PTR ReturnLabelId$[rbp] + 001ca 48 8b 8d f8 01 + 00 00 mov rcx, QWORD PTR tv161[rbp] + 001d1 e8 00 00 00 00 call ?push_back@?$vector@KV?$allocator@K@std@@@std@@QEAAXAEBK@Z ; std::vector >::push_back + +; 142 : return ReturnLabelId; - 001b4 8b 45 04 mov eax, DWORD PTR ReturnLabelId$[rbp] + 001d6 8b 45 04 mov eax, DWORD PTR ReturnLabelId$[rbp] -; 142 : } +; 143 : } - 001b7 8b f8 mov edi, eax - 001b9 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] - 001bd 48 8d 15 00 00 + 001d9 8b f8 mov edi, eax + 001db 48 8d 4d e0 lea rcx, QWORD PTR [rbp-32] + 001df 48 8d 15 00 00 00 00 lea rdx, OFFSET FLAT:?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z$rtcFrameData - 001c4 e8 00 00 00 00 call _RTC_CheckStackVars - 001c9 8b c7 mov eax, edi - 001cb 48 8b 8d 60 02 + 001e6 e8 00 00 00 00 call _RTC_CheckStackVars + 001eb 8b c7 mov eax, edi + 001ed 48 8b 8d 60 02 00 00 mov rcx, QWORD PTR __$ArrayPad$[rbp] - 001d2 48 33 cd xor rcx, rbp - 001d5 e8 00 00 00 00 call __security_check_cookie - 001da 48 8d a5 78 02 + 001f4 48 33 cd xor rcx, rbp + 001f7 e8 00 00 00 00 call __security_check_cookie + 001fc 48 8d a5 78 02 00 00 lea rsp, QWORD PTR [rbp+632] - 001e1 5f pop rdi - 001e2 5d pop rbp - 001e3 c3 ret 0 + 00203 5f pop rdi + 00204 5d pop rbp + 00205 c3 ret 0 ?NcGenUnusedLabelId@@YAKPEAU_NATIVE_CODE_BLOCK@@@Z ENDP ; NcGenUnusedLabelId _TEXT ENDS ; COMDAT text$x @@ -13317,18 +13287,19 @@ $T7 = 344 $T8 = 392 $T9 = 424 $T10 = 472 +tv161 = 504 tv81 = 504 -tv159 = 512 +tv164 = 512 tv130 = 520 tv93 = 528 -tv161 = 536 +tv166 = 536 tv84 = 544 -tv166 = 552 -tv163 = 560 +tv171 = 552 +tv168 = 560 tv153 = 568 tv145 = 576 -tv167 = 584 -tv165 = 592 +tv172 = 584 +tv170 = 592 tv151 = 600 __$ArrayPad$ = 608 Block$ = 656 @@ -13358,18 +13329,19 @@ $T7 = 344 $T8 = 392 $T9 = 424 $T10 = 472 +tv161 = 504 tv81 = 504 -tv159 = 512 +tv164 = 512 tv130 = 520 tv93 = 528 -tv161 = 536 +tv166 = 536 tv84 = 544 -tv166 = 552 -tv163 = 560 +tv171 = 552 +tv168 = 560 tv153 = 568 tv145 = 576 -tv167 = 584 -tv165 = 592 +tv172 = 584 +tv170 = 592 tv151 = 600 __$ArrayPad$ = 608 Block$ = 656 @@ -13400,18 +13372,19 @@ $T7 = 344 $T8 = 392 $T9 = 424 $T10 = 472 +tv161 = 504 tv81 = 504 -tv159 = 512 +tv164 = 512 tv130 = 520 tv93 = 528 -tv161 = 536 +tv166 = 536 tv84 = 544 -tv166 = 552 -tv163 = 560 +tv171 = 552 +tv168 = 560 tv153 = 568 tv145 = 576 -tv167 = 584 -tv165 = 592 +tv172 = 584 +tv170 = 592 tv151 = 600 __$ArrayPad$ = 608 Block$ = 656 @@ -13442,18 +13415,19 @@ $T7 = 344 $T8 = 392 $T9 = 424 $T10 = 472 +tv161 = 504 tv81 = 504 -tv159 = 512 +tv164 = 512 tv130 = 520 tv93 = 528 -tv161 = 536 +tv166 = 536 tv84 = 544 -tv166 = 552 -tv163 = 560 +tv171 = 552 +tv168 = 560 tv153 = 568 tv145 = 576 -tv167 = 584 -tv165 = 592 +tv172 = 584 +tv170 = 592 tv151 = 600 __$ArrayPad$ = 608 Block$ = 656 @@ -13483,7 +13457,7 @@ Original$ = 264 New$ = 272 ?NcChangeLabelId@@YAXPEAU_NATIVE_CODE_BLOCK@@KK@Z PROC ; NcChangeLabelId, COMDAT -; 145 : { +; 146 : { $LN8: 00000 44 89 44 24 18 mov DWORD PTR [rsp+24], r8d @@ -13504,7 +13478,7 @@ $LN8: 00 00 lea rcx, OFFSET FLAT:__84EFCFFB_NativeCode@cpp 0003a e8 00 00 00 00 call __CheckForDebuggerJustMyCode -; 146 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) +; 147 : for (PNATIVE_CODE_LINK T = Block->Start; T && T != Block->End->Next; T = T->Next) 0003f 48 8b 85 00 01 00 00 mov rax, QWORD PTR Block$[rbp] @@ -13525,8 +13499,8 @@ $LN4@NcChangeLa: 0006f 48 39 45 08 cmp QWORD PTR T$1[rbp], rax 00073 74 3a je SHORT $LN3@NcChangeLa -; 147 : { -; 148 : if (((T->Flags & CODE_FLAG_IS_LABEL) || (T->Flags & CODE_FLAG_IS_REL_JMP)) && T->Label == Original) +; 148 : { +; 149 : if (((T->Flags & CODE_FLAG_IS_LABEL) || (T->Flags & CODE_FLAG_IS_REL_JMP)) && T->Label == Original) 00075 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] 00079 8b 40 18 mov eax, DWORD PTR [rax+24] @@ -13545,7 +13519,7 @@ $LN6@NcChangeLa: 0009b 39 48 1c cmp DWORD PTR [rax+28], ecx 0009e 75 0d jne SHORT $LN5@NcChangeLa -; 149 : T->Label = New; +; 150 : T->Label = New; 000a0 48 8b 45 08 mov rax, QWORD PTR T$1[rbp] 000a4 8b 8d 10 01 00 @@ -13553,12 +13527,12 @@ $LN6@NcChangeLa: 000aa 89 48 1c mov DWORD PTR [rax+28], ecx $LN5@NcChangeLa: -; 150 : } +; 151 : } 000ad eb a0 jmp SHORT $LN2@NcChangeLa $LN3@NcChangeLa: -; 151 : } +; 152 : } 000af 48 8d a5 e8 00 00 00 lea rsp, QWORD PTR [rbp+232] diff --git a/x64/Debug/CodeVirtualizer.ilk b/x64/Debug/CodeVirtualizer.ilk index adde3c0113b74dc8c4707b4fe9f3860a359cf99b..7a03a9da5439e4dd2a8de8775bc442b94e187b3f 100644 GIT binary patch literal 2701876 zcmeFa4}9Iz{XhOrni3TRK@eO7sYV4sRB+SYwox~2+NKqRrkb{Cn`*SF1{nt#F=0Uv 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